; -------------------------------------------------------------------------------- ; @Title: STM32MP1 On-Chip Peripherals ; @Props: Released ; @Author: JAM, KWI, JON, KRZ, NEJ ; @Changelog: 2019-05-22 JAM ; 2021-02-18 KWI ; 2022-01-29 JON ; 2023-09-28 KRZ ; 2024-03-22 NEJ ; @Manufacturer: STM - ST Microelectronics N.V. ; @Doc: Generated (TRACE32, build: 167751.), based on: ; STM32MP13xx.svd (Ver. 1.5), STM32MP151x.svd (Rev. 1.4), ; STM32MP153x.svd (Rev. 1.4), STM32MP157x.svd (Rev. 1.7) ; @Core: Cortex-A7, Cortex-M4F ; @Chip: STM32MP131A, STM32MP131C, STM32MP131D, STM32MP131F, STM32MP133A, ; STM32MP133C, STM32MP133D, STM32MP133F, STM32MP137A, STM32MP137C, ; STM32MP137D, STM32MP137F, STM32MP151A-CA7, STM32MP151A-CM4, ; STM32MP151C-CA7, STM32MP151C-CM4, STM32MP153A-CA7, STM32MP153A-CM4, ; STM32MP153C-CA7, STM32MP153C-CM4, STM32MP157A-CA7, STM32MP157A-CM4, ; STM32MP157C-CA7, STM32MP157C-CM4, STM32MP151D-CA7, STM32MP151D-CM4, ; STM32MP151F-CA7, STM32MP151F-CM4, STM32MP153D-CA7, STM32MP153D-CM4, ; STM32MP153F-CA7, STM32MP153F-CM4, STM32MP157D-CA7, STM32MP157D-CM4, ; STM32MP157F-CA7, STM32MP157F-CM4 ; @Copyright: (C) 1989-2024 Lauterbach GmbH, licensed for use with TRACE32(R) only ; -------------------------------------------------------------------------------- ; $Id: perstm32mp1.per 17687 2024-03-27 11:04:47Z kwisniewski $ AUTOINDENT.ON CENTER TREE ENUMDELIMITER "," base ad:0x0 sif (CORENAME()=="CORTEXM4F") tree.close "Core Registers (Cortex-M4F)" AUTOINDENT.PUSH AUTOINDENT.OFF tree "System Control" sif COMPonent.AVAILABLE("COREDEBUG") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1)) width 12. group.long 0x08++0x03 line.long 0x00 "ACTLR,Auxiliary Control Register" bitfld.long 0x00 9. " DISFPCA ,Disables lazy stacking of floating point context" "No,Yes" bitfld.long 0x00 8. " DISOOFP ,Disables floating point instructions completing" "No,Yes" bitfld.long 0x00 2. " DISFOLD ,Disables folding of IT instructions" "No,Yes" textline " " bitfld.long 0x00 1. " DISDEFWBUF ,Disables write buffer use during default memory map accesses" "No,Yes" bitfld.long 0x00 0. " DISMCYCINT ,Disables interruption of multi-cycle instructions" "No,Yes" group.long 0x10++0x0B line.long 0x00 "SYST_CSR,SysTick Control and Status Register" rbitfld.long 0x00 16. " COUNTFLAG ,Counter Flag" "Not counted,Counted" bitfld.long 0x00 2. " CLKSOURCE ,SysTick clock source" "External,Core" bitfld.long 0x00 1. " TICKINT ,SysTick Handler" "No SysTick,SysTick" textline " " bitfld.long 0x00 0. " ENABLE ,Counter Enable" "Disabled,Enabled" line.long 0x04 "SYST_RVR,SysTick Reload Value Register" hexmask.long.tbyte 0x04 0.--23. 1. " RELOAD ,The value to load into the SYST_CVR when the counter reaches 0" line.long 0x08 "SYST_CVR,SysTick Current Value Register" rgroup.long 0x1C++0x03 line.long 0x00 "SYST_CALIB,SysTick Calibration Value Register" bitfld.long 0x00 31. " NOREF ,Indicates whether the implementation defined reference clock is implemented" "Implemented,Not implemented" bitfld.long 0x00 30. " SKEW ,Indicates whether the 10ms calibration value is exact" "Exact,Inexact" hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,Holds a reload value to be used for 10ms (100Hz) timing" rgroup.long 0xD00++0x03 line.long 0x00 "CPUID,CPU ID Base Register" hexmask.long.byte 0x00 24.--31. 1. " IMPLEMENTER ,Implementer Code" bitfld.long 0x00 20.--23. " VARIANT ,Indicates processor revision" "Revision 0,?..." bitfld.long 0x00 16.--19. " ARCHITECTURE ,Architecture" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.word 0x00 4.--15. 1. " PARTNO ,Indicates part number" bitfld.long 0x00 0.--3. " REVISION ,Indicates patch release" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xD04++0x23 line.long 0x00 "ICSR,Interrupt Control State Register" bitfld.long 0x00 31. " NMIPENDSET ,Set Pending NMI Bit" "Inactive,Active" bitfld.long 0x00 28. " PENDSVSET ,Set Pending pendSV Bit" "Not pending,Pending" bitfld.long 0x00 27. " PENDSVCLR ,Removes the pending status of the PendSV exception" "No effect,Removed" textline " " bitfld.long 0x00 26. " PENDSTSET ,Set Pending SysTick Bit" "Not pending,Pending" bitfld.long 0x00 25. " PENDSTCLR ,Clear Pending SysTick Bit" "No effect,Removed" bitfld.long 0x00 23. " ISRPREEMPT ,Use Only at Debug Time" "Not active,Active" textline " " bitfld.long 0x00 22. " ISRPENDING ,Indicates whether an external interrupt" "Not pending,Pending" hexmask.long.word 0x00 12.--20. 1. " VECTPENDING ,Pending ISR Number Field" bitfld.long 0x00 11. " RETTOBASE ,Interrupt Exception" "Active,Not active" textline " " hexmask.long.word 0x00 0.--8. 1. " VECTACTIVE ,The exception number of the current executing exception" line.long 0x04 "VTOR,Vector Table Offset Register" hexmask.long 0x04 7.--31. 0x80 " TBLOFF ,Vector table address" line.long 0x08 "AIRCR,Application Interrupt and Reset Control Register" hexmask.long.word 0x08 16.--31. 1. " VECTKEY ,Register Key" rbitfld.long 0x08 15. " ENDIANESS ,Data endianness Bit" "Little,Big" bitfld.long 0x08 8.--10. " PRIGROUP ,Interrupt Priority Grouping Field" "[7:1]/[0],[7:2]/[1:0],[7:3]/[2:0],[7:4]/[3:0],[7:5]/[4:0],[7:6]/[5:0],[7]/[6:0],-/[7:0]" textline " " bitfld.long 0x08 2. " SYSRESETREQ ,System Reset Request" "Not requested,Requested" bitfld.long 0x08 1. " VECTCLRACTIVE ,Clear Active Vector Bit" "No effect,Clear" bitfld.long 0x08 0. " VECTRESET ,System Reset" "No effect,Reset" line.long 0x0C "SCR,System Control Register" bitfld.long 0x0C 4. " SEVONPEND ,Determines whether an interrupt transition from inactive state to pending state is a wakeup event" "Not wakeup,Wakeup" bitfld.long 0x0C 2. " SLEEPDEEP ,Provides a qualifying hint indicating that waking from sleep might take longer" "Not deep sleep,Deep sleep" bitfld.long 0x0C 1. " SLEEPONEXIT ,Determines whether, on an exit from an ISR that returns to the base level of execution priority, the processor enters a sleep state" "Disabled,Enabled" line.long 0x10 "CCR,Configuration Control Register" bitfld.long 0x10 18. " BP ,Branch prediction enable bit" "Disabled,Enabled" bitfld.long 0x10 17. " IC ,Instruction cache enable bit" "Disabled,Enabled" bitfld.long 0x10 16. " DC ,Cache enable bit" "Disabled,Enabled" textline " " bitfld.long 0x10 9. " STKALIGN ,8-byte Stack Frame Alignment" "4-byte/no adjustment,8-byte/adjustment" bitfld.long 0x10 8. " BFHFNMIGN ,Enable NMI and Hard Fault and FAULTMASK to Ignore Bus Fault" "Disabled,Enabled" bitfld.long 0x10 4. " DIV_0_TRP ,Trap Divide by Zero" "Disabled,Enabled" textline " " bitfld.long 0x10 3. " UNALIGN_TRP ,Trap for Unaligned Access" "Disabled,Enabled" bitfld.long 0x10 1. " USERSETMPEND ,Controls whether unprivileged software can access the STIR" "Denied,Allowed" bitfld.long 0x10 0. " NONEBASETHRDENA ,Control Entry to Thread Mode" "Only from last exception,Any level" line.long 0x14 "SHPR1,SSystem Handler Priority Register 1" hexmask.long.byte 0x14 24.--31. 1. " PRI_7 ,Priority of System Handler 7" hexmask.long.byte 0x14 16.--23. 1. " PRI_6 ,Priority of system handler 6(UsageFault)" hexmask.long.byte 0x14 8.--15. 1. " PRI_5 ,Priority of system handler 5(BusFault)" textline " " hexmask.long.byte 0x14 0.--7. 1. " PRI_4 ,Priority of system handler 4(MemManage)" line.long 0x18 "SHPR2,System Handler Priority Register 2" hexmask.long.byte 0x18 24.--31. 1. " PRI_11 ,Priority of system handler 11(SVCall)" hexmask.long.byte 0x18 16.--23. 1. " PRI_10 ,Priority of System Handler 10" hexmask.long.byte 0x18 8.--15. 1. " PRI_9 ,Priority of System Handler 9" textline " " hexmask.long.byte 0x18 0.--7. 1. " PRI_8 ,Priority of System Handler 8" line.long 0x1C "SHPR3,System Handler Priority Register 3" hexmask.long.byte 0x1C 24.--31. 1. " PRI_15 ,Priority of System Handler 15(SysTick)" hexmask.long.byte 0x1C 16.--23. 1. " PRI_14 ,Priority of System Handler 14(PendSV)" hexmask.long.byte 0x1C 8.--15. 1. " PRI_13 ,Priority of System Handler 13" textline " " hexmask.long.byte 0x1C 0.--7. 1. " PRI_12 ,Priority of System Handler 12(DebugMonitor)" line.long 0x20 "SHCSR,System Handler Control and State Register" bitfld.long 0x20 18. " USGFAULTENA ,Enable UsageFault" "Disabled,Enabled" bitfld.long 0x20 17. " BUSFAULTENA ,Enable BusFault" "Disabled,Enabled" bitfld.long 0x20 16. " MEMFAULTENA ,Enable MemManage fault" "Disabled,Enabled" textline " " bitfld.long 0x20 15. " SVCALLPENDED ,SVCall is pending" "Not pending,Pending" bitfld.long 0x20 14. " BUSFAULTPENDED ,BusFault is pending" "Not pending,Pending" bitfld.long 0x20 13. " MEMFAULTPENDED ,MemManage is pending" "Not pending,Pending" textline " " bitfld.long 0x20 12. " USGFAULTPENDED ,UsageFault is pending" "Not pending,Pending" bitfld.long 0x20 11. " SYSTICKACT ,SysTick is Active" "Not active,Active" bitfld.long 0x20 10. " PENDSVACT ,PendSV is Active" "Not active,Active" textline " " bitfld.long 0x20 8. " MONITORACT ,Monitor is Active" "Not active,Active" bitfld.long 0x20 7. " SVCALLACT ,SVCall is Active" "Not active,Active" bitfld.long 0x20 3. " USGFAULTACT ,UsageFault is Active" "Not active,Active" textline " " bitfld.long 0x20 1. " BUSFAULTACT ,BusFault is Active" "Not active,Active" bitfld.long 0x20 0. " MEMFAULTACT ,MemManage is Active" "Not active,Active" group.byte 0xD28++0x1 line.byte 0x00 "MMFSR,MemManage Status Register" bitfld.byte 0x00 7. " MMARVALID ,Address Valid Flag" "Not valid,Valid" bitfld.byte 0x00 5. " MLSPERR ,A MemManage fault occurred during FP lazy state preservation" "Not occurred,Occurred" bitfld.byte 0x00 4. " MSTKERR ,tacking Access Violations" "Not occurred,Occurred" textline " " bitfld.byte 0x00 3. " MUNSTKERR ,Unstack Access Violations" "Not occurred,Occurred" bitfld.byte 0x00 1. " DACCVIOL ,Data Access Violation" "Not occurred,Occurred" bitfld.byte 0x00 0. " IACCVIOL ,Instruction Access Violation" "Not occurred,Occurred" line.byte 0x01 "BFSR,Bus Fault Status Register" bitfld.byte 0x01 7. " BFARVALID ,Address Valid Flag" "Not valid,Valid" bitfld.byte 0x01 5. " LSPERR ,A bus fault occurred during FP lazy state preservation" "Not occurred,Occurred" bitfld.byte 0x01 4. " STKERR ,Derived bus fault(exception entry)" "Not occurred,Occurred" textline " " bitfld.byte 0x01 3. " UNSTKERR ,Derived bus fault(exception return)" "Not occurred,Occurred" bitfld.byte 0x01 2. " IMPRECISERR ,Imprecise data access error" "Not occurred,Occurred" bitfld.byte 0x01 1. " PRECISERR ,Precise data access error" "Not occurred,Occurred" textline " " bitfld.byte 0x01 0. " IBUSERR ,Bus fault on an instruction prefetch" "Not occurred,Occurred" group.word 0xD2A++0x1 line.word 0x00 "USAFAULT,Usage Fault Status Register" bitfld.word 0x00 9. " DIVBYZERO ,Divide by zero error" "No error,Error" bitfld.word 0x00 8. " UNALIGNED ,Unaligned access error" "No error,Error" bitfld.word 0x00 3. " NOCP ,A coprocessor access error" "No error,Error" textline " " bitfld.word 0x00 2. " INVPC ,An integrity check error" "No error,Error" bitfld.word 0x00 1. " INVSTATE ,Invalid Combination of EPSR and Instruction" "No error,Error" bitfld.word 0x00 0. " UNDEFINSTR ,Undefined instruction error" "No error,Error" group.long 0xD2C++0x07 line.long 0x00 "HFSR,Hard Fault Status Register" bitfld.long 0x00 31. " DEBUGEVT ,Indicates when a Debug event has occurred" "Not occurred,Occurred" bitfld.long 0x00 30. " FORCED ,Indicates that a fault with configurable priority" "Not occurred,Occurred" bitfld.long 0x00 1. " VECTTBL ,Indicates when a fault has occurred because of a vector table read error on exception processing" "Not occurred,Occurred" line.long 0x04 "DFSR,Debug Fault Status Register" bitfld.long 0x04 4. " EXTERNAL ,Indicates a debug event generated because of the assertion of EDBGRQ" "Not asserted,Asserted" bitfld.long 0x04 3. " VCATCH ,Vector Catch Flag" "Not occurred,Occurred" bitfld.long 0x04 2. " DWTTRAP ,Indicates a debug event generated by the DWT" "Not occurred,Occurred" textline " " bitfld.long 0x04 1. " BKPT ,BKPT Flag" "Not executed,Executed" bitfld.long 0x04 0. " HALTED ,Indicates a debug event generated by either" "Not requested,Requested" group.long 0xD34++0x0B line.long 0x00 "MMFAR,MemManage Fault Address Register" line.long 0x04 "BFAR,BusFault Address Register" line.long 0x08 "AFSR,Auxiliary Fault Status Register" group.long 0xD88++0x03 line.long 0x00 "CPACR,Coprocessor Access Control Register" bitfld.long 0x00 22.--23. " CP11 ,Access privileges for coprocessor 11" "Access denied,Privileged only,Reserved,Full access" bitfld.long 0x00 20.--21. " CP10 ,Access privileges for coprocessor 10" "Access denied,Privileged only,Reserved,Full access" bitfld.long 0x00 14.--15. " CP7 ,Access privileges for coprocessor 7" "Access denied,Privileged only,Reserved,Full access" textline " " bitfld.long 0x00 12.--13. " CP6 ,Access privileges for coprocessor 6" "Access denied,Privileged only,Reserved,Full access" bitfld.long 0x00 10.--11. " CP5 ,Access privileges for coprocessor 5" "Access denied,Privileged only,Reserved,Full access" bitfld.long 0x00 8.--9. " CP4 ,Access privileges for coprocessor 4" "Access denied,Privileged only,Reserved,Full access" textline " " bitfld.long 0x00 6.--7. " CP3 ,Access privileges for coprocessor 3" "Access denied,Privileged only,Reserved,Full access" bitfld.long 0x00 4.--5. " CP2 ,Access privileges for coprocessor 2" "Access denied,Privileged only,Reserved,Full access" bitfld.long 0x00 2.--3. " CP1 ,Access privileges for coprocessor 1" "Access denied,Privileged only,Reserved,Full access" textline " " bitfld.long 0x00 0.--1. " CP0 ,Access privileges for coprocessor 0" "Access denied,Privileged only,Reserved,Full access" wgroup.long 0xF00++0x03 line.long 0x00 "STIR,Software Trigger Interrupt Register" hexmask.long.word 0x00 0.--8. 1. " INTID ,Indicates the interrupt to be triggered" width 10. tree "Feature Registers" rgroup.long 0xD40++0x0B line.long 0x00 "ID_PFR0,Processor Feature Register 0" bitfld.long 0x00 4.--7. " STATE1 ,Thumb instruction set support" ",,,Supported,?..." bitfld.long 0x00 0.--3. " STATE0 ,ARM instruction set support" "Not supported,?..." line.long 0x04 "ID_PFR1,Processor Feature Register 1" bitfld.long 0x04 8.--11. " MPROF ,M profile programmers' model" ",,2-stack,?..." line.long 0x08 "ID_DFR0,Debug Feature Register 0" bitfld.long 0x08 20.--23. " DBGMOD ,Support for memory-mapped debug model for M profile processors" "Not supported,Supported,?..." hgroup.long 0xD4C++0x03 hide.long 0x00 "ID_AFR0,Auxiliary Feature Register 0" rgroup.long 0xD50++0x03 line.long 0x00 "ID_MMFR0,Memory Model Feature Register 0" bitfld.long 0x00 20.--23. " AUXREG ,Indicates the support for Auxiliary registers" "Not supported,ACTLR only,?..." bitfld.long 0x00 16.--19. " TCMSUP ,Indicates the support for Tightly Coupled Memory (TCM)" "Not supported,Supported,?..." bitfld.long 0x00 12.--15. " SHRLEV ,Indicates the number of shareability levels implemented" "Level 1,?..." textline " " bitfld.long 0x00 8.--11. " OUTMSHR ,Indicates the outermost shareability domain implemented" "Non-cacheable,,,,,,,,,,,,,,,Ignored" bitfld.long 0x00 4.--7. " PMSASUP ,Indicates support for a PMSA" "Not supported,,,PMSAv7,?..." hgroup.long 0xD54++0x03 hide.long 0x00 "ID_MMFR1,Memory Model Feature Register 1" rgroup.long 0xD58++0x03 line.long 0x00 "ID_MMFR2,Memory Model Feature Register 2" bitfld.long 0x00 24.--27. " WFISTALL ,Indicates the support for Wait For Interrupt (WFI) stalling" "Not supported,Supported,?..." rgroup.long 0xD60++0x13 line.long 0x00 "ID_ISAR0,Instruction Set Attributes Register 0" bitfld.long 0x00 24.--27. " DIVIDE ,Indicates the supported divide instructions" "Not supported,SDIV/UDIV,?..." bitfld.long 0x00 20.--23. " DEBUG ,Indicates the supported debug instructions" "Not supported,BKPT,?..." bitfld.long 0x00 16.--19. " COPROC ,Indicates the supported coprocessor instructions" "Not supported,CDP/LDC/MCR/STC,CDP2/LDC2/MCR2/STC2,MCRR/MRRC,MCRR2/MRRC2,?..." textline " " bitfld.long 0x00 12.--15. " CMPBRANCH ,Indicates the supported combined compare and branch instructions" "Not supported,CBNZ/CBZ,?..." bitfld.long 0x00 8.--11. " BITFIELD ,Indicates the supported bitfield instructions" "Not supported,BFC/BFI/SBFX/UBFX,?..." bitfld.long 0x00 4.--7. " BITCOUNT ,Indicates the supported bit counting instructions" "Not supported,CLZ,?..." line.long 0x04 "ID_ISAR1,Instruction Set Attributes Register 1" bitfld.long 0x04 24.--27. " INTERWORK ,Indicates the supported Interworking instructions" "Not supported,BX,BX/BLX,?..." bitfld.long 0x04 20.--23. " IMMEDIATE ,Indicates the support for data-processing instructions with long immediates" "Not supported,ADDW/MOVW/MOVT/SUBW,?..." bitfld.long 0x04 16.--19. " IFTHEN ,Indicates the supported IfThen instructions" "Not supported,IT,?..." textline " " bitfld.long 0x04 12.--15. " EXTEND ,Indicates the supported Extend instructions" "Not supported,Supported,Supported,?..." line.long 0x08 "ID_ISAR2,Instruction Set Attributes Register 2" bitfld.long 0x08 24.--27. " REVERSAL ,Indicates the supported reversal instructions" "Not supported,REV/REV16/REVSH,REV/REV16/REVSH/RBIT,?..." bitfld.long 0x08 20.--23. " MULTU ,Indicates the supported advanced unsigned multiply instructions" "Not supported,UMULL/UMLAL,UMULL/UMLAL/UMAAL,?..." bitfld.long 0x08 16.--19. " MULTS ,Indicates the supported advanced signed multiply instructions" "Not supported,Supported,Supported,Supported,?..." textline " " bitfld.long 0x08 12.--15. " MULT ,Indicates the supported additional multiply instructions" "Not supported,MLA,MLA/MLS,?..." bitfld.long 0x08 8.--11. " MULTIACCESSINT ,Indicates the support for multi-access interruptible instructions" "Not supported,LDM/STM restartable,LDM/STM continuable,?..." bitfld.long 0x08 4.--7. " MEMHINT ,Indicates the supported memory hint instructions" "Not supported,,,PLD/PLI,?..." textline " " bitfld.long 0x08 0.--3. " LOADSTORE ,Indicates the supported additional load and store instructions" "Not supported,LDRD/STRD,?..." line.long 0x0C "ID_ISAR3,Instruction Set Attributes Register 3" bitfld.long 0x0C 24.--27. " TRUENOP ,Indicates the support for a true NOP instruction" "Not supported,Supported,?..." bitfld.long 0x0C 20.--23. " THUMBCOPY ,Indicates the supported non flag-setting MOV instructions" "Not supported,Supported,?..." bitfld.long 0x0C 16.--19. " TABBRANCH ,Indicates the supported Table Branch instructions" "Not supported,TBB/TBH,?..." textline " " bitfld.long 0x0C 12.--15. " SYNCHPRIM ,Indicates the supported Table Branch instructions" "Not supported,Supported,Supported,Supported,?..." bitfld.long 0x0C 8.--11. " SVC ,Indicates the supported SVC instructions" "Not supported,SVC,?..." bitfld.long 0x0C 4.--7. " SIMD ,Indicates the supported SIMD instructions" "Not supported,Supported,,Supported,?..." textline " " bitfld.long 0x0C 0.--3. " SATURATE ,Indicates the supported Saturate instructions" "Not supported,QADD/QDADD/QDSUB/QSUB,?..." line.long 0x10 "ID_ISAR4,Instruction Set Attributes Register 4" bitfld.long 0x10 24.--27. " PSR_M ,Indicates the supported M profile instructions to modify the PSRs" "Not supported,Supported,?..." bitfld.long 0x10 20.--23. " SYNCHPRIMFRAC ,Indicates the supported M profile instructions to modify the PSRs" "Not supported,Supported,Supported,Supported,?..." bitfld.long 0x10 16.--19. " BARRIER ,Indicates the supported Barrier instructions" "Not supported,DMB/DSB/ISB,?..." textline " " bitfld.long 0x10 8.--11. " WRITEBACK ,Indicates the support for writeback addressing modes" "Basic support,Full support,?..." bitfld.long 0x10 4.--7. " WITHSHIFTS ,Indicates the support for instructions with shifts" "MOV/shift,Shift LSL 0-3,,Shift other,?..." bitfld.long 0x10 0.--3. " UNPRIV ,Indicates the supported unprivileged instructions" "Not supported,LDRBT/LDRT/STRBT/STRT,LDRBT/LDRT/STRBT/STRT/LDRHT/LDRSBT/LDRSHTSTRHT,?..." tree.end width 6. tree "CoreSight Identification Registers" rgroup.long 0xFE0++0x0F line.long 0x00 "PID0,Peripheral ID0" hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]" line.long 0x04 "PID1,Peripheral ID1" hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]" hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]" line.long 0x08 "PID2,Peripheral ID2" hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision" bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC" hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]" line.long 0x0C "PID3,Peripheral ID3" hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field" hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block" rgroup.long 0xFD0++0x03 line.long 0x00 "PID4,Peripheral Identification Register 4" hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count" hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code" rgroup.long 0xFF0++0x0F line.long 0x00 "CID0,Component ID0 (Preamble)" line.long 0x04 "CID1,Component ID1" hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class" hexmask.long.byte 0x04 0.--3. 1. " Preamble ,Preamble" line.long 0x08 "CID2,Component ID2" line.long 0x0C "CID3,Component ID3" tree.end width 0x0B else newline textline "COREDEBUG component base address not specified" newline endif tree.end tree "Memory Protection Unit" sif COMPonent.AVAILABLE("COREDEBUG") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1)) width 15. rgroup.long 0xD90++0x03 line.long 0x00 "MPU_TYPE,MPU Type Register" bitfld.long 0x00 16.--23. " IREGION ,Instruction region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..." bitfld.long 0x00 8.--15. " DREGION ,Number of regions supported by the MPU" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..." bitfld.long 0x00 0. " SEPARATE ,Indicates support for separate instruction and data address maps" "Not supported,Supported" group.long 0xD94++0x03 line.long 0x00 "MPU_CTRL,MPU Control Register" bitfld.long 0x00 2. " PRIVDEFENA ,Enables the default memory map as a background region for privileged access" "Disabled,Enabled" bitfld.long 0x00 1. " HFNMIENA ,Handlers executing with priority less than 0 access memory with the MPU enabled or with the MPU disabled" "MPU disabled,MPU enabled" bitfld.long 0x00 0. " ENABLE ,Enables the MPU" "Disabled,Enabled" group.long 0xD98++0x03 line.long 0x00 "MPU_RNR,MPU Region Number Register" hexmask.long.byte 0x00 0.--7. 1. " REGION ,Indicates the memory region accessed by MPU_RBAR and MPU_RASR" tree.close "MPU regions" if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x0 group.long 0xD9C++0x03 "Region 0" saveout 0xD98 %l 0x0 line.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x0 line.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 0 (not implemented)" saveout 0xD98 %l 0x0 hide.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x0 hide.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x1 group.long 0xD9C++0x03 "Region 1" saveout 0xD98 %l 0x1 line.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x1 line.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 1 (not implemented)" saveout 0xD98 %l 0x1 hide.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x1 hide.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x2 group.long 0xD9C++0x03 "Region 2" saveout 0xD98 %l 0x2 line.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x2 line.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 2 (not implemented)" saveout 0xD98 %l 0x2 hide.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x2 hide.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x3 group.long 0xD9C++0x03 "Region 3" saveout 0xD98 %l 0x3 line.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x3 line.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 3 (not implemented)" saveout 0xD98 %l 0x3 hide.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x3 hide.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x4 group.long 0xD9C++0x03 "Region 4" saveout 0xD98 %l 0x4 line.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x4 line.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 4 (not implemented)" saveout 0xD98 %l 0x4 hide.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x4 hide.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x5 group.long 0xD9C++0x03 "Region 5" saveout 0xD98 %l 0x5 line.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x5 line.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 5 (not implemented)" saveout 0xD98 %l 0x5 hide.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x5 hide.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x6 group.long 0xD9C++0x03 "Region 6" saveout 0xD98 %l 0x6 line.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x6 line.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 6 (not implemented)" saveout 0xD98 %l 0x6 hide.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x6 hide.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x7 group.long 0xD9C++0x03 "Region 7" saveout 0xD98 %l 0x7 line.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x7 line.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 7 (not implemented)" saveout 0xD98 %l 0x7 hide.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x7 hide.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x8 group.long 0xD9C++0x03 "Region 8" saveout 0xD98 %l 0x8 line.long 0x00 "MPU_RBAR8,MPU Region Base Address Register 8" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x8 line.long 0x00 "MPU_RASR8,MPU Region Attribute and Size Register 8" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 8 (not implemented)" saveout 0xD98 %l 0x8 hide.long 0x00 "MPU_RBAR8,MPU Region Base Address Register 8" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x8 hide.long 0x00 "MPU_RASR8,MPU Region Attribute and Size Register 8" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x9 group.long 0xD9C++0x03 "Region 9" saveout 0xD98 %l 0x9 line.long 0x00 "MPU_RBAR9,MPU Region Base Address Register 9" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x9 line.long 0x00 "MPU_RASR9,MPU Region Attribute and Size Register 9" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 9 (not implemented)" saveout 0xD98 %l 0x9 hide.long 0x00 "MPU_RBAR9,MPU Region Base Address Register 9" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x9 hide.long 0x00 "MPU_RASR9,MPU Region Attribute and Size Register 9" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xA group.long 0xD9C++0x03 "Region 10" saveout 0xD98 %l 0xA line.long 0x00 "MPU_RBAR10,MPU Region Base Address Register 10" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0xA line.long 0x00 "MPU_RASR10,MPU Region Attribute and Size Register 10" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 10 (not implemented)" saveout 0xD98 %l 0xA hide.long 0x00 "MPU_RBAR10,MPU Region Base Address Register 10" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0xA hide.long 0x00 "MPU_RASR10,MPU Region Attribute and Size Register 10" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xB group.long 0xD9C++0x03 "Region 11" saveout 0xD98 %l 0xB line.long 0x00 "MPU_RBAR11,MPU Region Base Address Register 11" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0xB line.long 0x00 "MPU_RASR11,MPU Region Attribute and Size Register 11" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 11 (not implemented)" saveout 0xD98 %l 0xB hide.long 0x00 "MPU_RBAR11,MPU Region Base Address Register 11" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0xB hide.long 0x00 "MPU_RASR11,MPU Region Attribute and Size Register 11" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xC group.long 0xD9C++0x03 "Region 12" saveout 0xD98 %l 0xC line.long 0x00 "MPU_RBAR12,MPU Region Base Address Register 12" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0xC line.long 0x00 "MPU_RASR12,MPU Region Attribute and Size Register 12" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 12 (not implemented)" saveout 0xD98 %l 0xC hide.long 0x00 "MPU_RBAR12,MPU Region Base Address Register 12" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0xC hide.long 0x00 "MPU_RASR12,MPU Region Attribute and Size Register 12" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xD group.long 0xD9C++0x03 "Region 13" saveout 0xD98 %l 0xD line.long 0x00 "MPU_RBAR13,MPU Region Base Address Register 13" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0xD line.long 0x00 "MPU_RASR13,MPU Region Attribute and Size Register 13" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 13 (not implemented)" saveout 0xD98 %l 0xD hide.long 0x00 "MPU_RBAR13,MPU Region Base Address Register 13" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0xD hide.long 0x00 "MPU_RASR13,MPU Region Attribute and Size Register 13" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xE group.long 0xD9C++0x03 "Region 14" saveout 0xD98 %l 0xE line.long 0x00 "MPU_RBAR14,MPU Region Base Address Register 14" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0xE line.long 0x00 "MPU_RASR14,MPU Region Attribute and Size Register 14" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 14 (not implemented)" saveout 0xD98 %l 0xE hide.long 0x00 "MPU_RBAR14,MPU Region Base Address Register 14" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0xE hide.long 0x00 "MPU_RASR14,MPU Region Attribute and Size Register 14" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xF group.long 0xD9C++0x03 "Region 15" saveout 0xD98 %l 0xF line.long 0x00 "MPU_RBAR15,MPU Region Base Address Register 15" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0xF line.long 0x00 "MPU_RASR15,MPU Region Attribute and Size Register 15" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 15 (not implemented)" saveout 0xD98 %l 0xF hide.long 0x00 "MPU_RBAR15,MPU Region Base Address Register 15" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0xF hide.long 0x00 "MPU_RASR15,MPU Region Attribute and Size Register 15" textline " " textline " " endif tree.end width 0x0b else newline textline "COREDEBUG component base address not specified" newline endif tree.end tree "Nested Vectored Interrupt Controller" sif COMPonent.AVAILABLE("COREDEBUG") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1)) width 6. rgroup.long 0x04++0x03 line.long 0x00 "ICTR,Interrupt Controller Type Register" bitfld.long 0x00 0.--3. " INTLINESNUM ,Total Number of Interrupt" "0-32,33-64,65-96,97-128,129-160,161-192,193-224,225-240,?..." tree "Interrupt Enable Registers" width 23. if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00) group.long 0x100++0x03 line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01) group.long 0x100++0x7 line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02) group.long 0x100++0x0B line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03) group.long 0x100++0x0F line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04) group.long 0x100++0x13 line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05) group.long 0x100++0x17 line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 30. 0x14 30. 0x94 30. " ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 29. 0x14 29. 0x94 29. " ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 28. 0x14 28. 0x94 28. " ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 27. 0x14 27. 0x94 27. " ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 26. 0x14 26. 0x94 26. " ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 24. 0x14 24. 0x94 24. " ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 23. 0x14 23. 0x94 23. " ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 22. 0x14 22. 0x94 22. " ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 21. 0x14 21. 0x94 21. " ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 20. 0x14 20. 0x94 20. " ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 18. 0x14 18. 0x94 18. " ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 17. 0x14 17. 0x94 17. " ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 16. 0x14 16. 0x94 16. " ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 15. 0x14 15. 0x94 15. " ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 14. 0x14 14. 0x94 14. " ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 12. 0x14 12. 0x94 12. " ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 11. 0x14 11. 0x94 11. " ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 10. 0x14 10. 0x94 10. " ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 9. 0x14 9. 0x94 9. " ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 8. 0x14 8. 0x94 8. " ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 6. 0x14 6. 0x94 6. " ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 5. 0x14 5. 0x94 5. " ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 4. 0x14 4. 0x94 4. " ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 3. 0x14 3. 0x94 3. " ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 2. 0x14 2. 0x94 2. " ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 0. 0x14 0. 0x94 0. " ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06) group.long 0x100++0x1B line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 30. 0x14 30. 0x94 30. " ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 29. 0x14 29. 0x94 29. " ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 28. 0x14 28. 0x94 28. " ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 27. 0x14 27. 0x94 27. " ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 26. 0x14 26. 0x94 26. " ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 24. 0x14 24. 0x94 24. " ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 23. 0x14 23. 0x94 23. " ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 22. 0x14 22. 0x94 22. " ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 21. 0x14 21. 0x94 21. " ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 20. 0x14 20. 0x94 20. " ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 18. 0x14 18. 0x94 18. " ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 17. 0x14 17. 0x94 17. " ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 16. 0x14 16. 0x94 16. " ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 15. 0x14 15. 0x94 15. " ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 14. 0x14 14. 0x94 14. " ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 12. 0x14 12. 0x94 12. " ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 11. 0x14 11. 0x94 11. " ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 10. 0x14 10. 0x94 10. " ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 9. 0x14 9. 0x94 9. " ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 8. 0x14 8. 0x94 8. " ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 6. 0x14 6. 0x94 6. " ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 5. 0x14 5. 0x94 5. " ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 4. 0x14 4. 0x94 4. " ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 3. 0x14 3. 0x94 3. " ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 2. 0x14 2. 0x94 2. " ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 0. 0x14 0. 0x94 0. " ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x18 31. 0x18 31. 0x98 31. " ENA223 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 30. 0x18 30. 0x98 30. " ENA222 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 29. 0x18 29. 0x98 29. " ENA221 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 28. 0x18 28. 0x98 28. " ENA220 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 27. 0x18 27. 0x98 27. " ENA219 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 26. 0x18 26. 0x98 26. " ENA218 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 25. 0x18 25. 0x98 25. " ENA217 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 24. 0x18 24. 0x98 24. " ENA216 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 23. 0x18 23. 0x98 23. " ENA215 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 22. 0x18 22. 0x98 22. " ENA214 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 21. 0x18 21. 0x98 21. " ENA213 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 20. 0x18 20. 0x98 20. " ENA212 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 19. 0x18 19. 0x98 19. " ENA211 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 18. 0x18 18. 0x98 18. " ENA210 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 17. 0x18 17. 0x98 17. " ENA209 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 16. 0x18 16. 0x98 16. " ENA208 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 15. 0x18 15. 0x98 15. " ENA207 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 14. 0x18 14. 0x98 14. " ENA206 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 13. 0x18 13. 0x98 13. " ENA205 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 12. 0x18 12. 0x98 12. " ENA204 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 11. 0x18 11. 0x98 11. " ENA203 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 10. 0x18 10. 0x98 10. " ENA202 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 9. 0x18 9. 0x98 9. " ENA201 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 8. 0x18 8. 0x98 8. " ENA200 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 7. 0x18 7. 0x98 7. " ENA199 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 6. 0x18 6. 0x98 6. " ENA198 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 5. 0x18 5. 0x98 5. " ENA197 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 4. 0x18 4. 0x98 4. " ENA196 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 3. 0x18 3. 0x98 3. " ENA195 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 2. 0x18 2. 0x98 2. " ENA194 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 1. 0x18 1. 0x98 1. " ENA193 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 0. 0x18 0. 0x98 0. " ENA192 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07) group.long 0x100++0x1F line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 30. 0x14 30. 0x94 30. " ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 29. 0x14 29. 0x94 29. " ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 28. 0x14 28. 0x94 28. " ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 27. 0x14 27. 0x94 27. " ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 26. 0x14 26. 0x94 26. " ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 24. 0x14 24. 0x94 24. " ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 23. 0x14 23. 0x94 23. " ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 22. 0x14 22. 0x94 22. " ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 21. 0x14 21. 0x94 21. " ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 20. 0x14 20. 0x94 20. " ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 18. 0x14 18. 0x94 18. " ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 17. 0x14 17. 0x94 17. " ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 16. 0x14 16. 0x94 16. " ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 15. 0x14 15. 0x94 15. " ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 14. 0x14 14. 0x94 14. " ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 12. 0x14 12. 0x94 12. " ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 11. 0x14 11. 0x94 11. " ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 10. 0x14 10. 0x94 10. " ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 9. 0x14 9. 0x94 9. " ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 8. 0x14 8. 0x94 8. " ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 6. 0x14 6. 0x94 6. " ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 5. 0x14 5. 0x94 5. " ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 4. 0x14 4. 0x94 4. " ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 3. 0x14 3. 0x94 3. " ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 2. 0x14 2. 0x94 2. " ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 0. 0x14 0. 0x94 0. " ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x18 31. 0x18 31. 0x98 31. " ENA223 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 30. 0x18 30. 0x98 30. " ENA222 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 29. 0x18 29. 0x98 29. " ENA221 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 28. 0x18 28. 0x98 28. " ENA220 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 27. 0x18 27. 0x98 27. " ENA219 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 26. 0x18 26. 0x98 26. " ENA218 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 25. 0x18 25. 0x98 25. " ENA217 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 24. 0x18 24. 0x98 24. " ENA216 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 23. 0x18 23. 0x98 23. " ENA215 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 22. 0x18 22. 0x98 22. " ENA214 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 21. 0x18 21. 0x98 21. " ENA213 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 20. 0x18 20. 0x98 20. " ENA212 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 19. 0x18 19. 0x98 19. " ENA211 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 18. 0x18 18. 0x98 18. " ENA210 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 17. 0x18 17. 0x98 17. " ENA209 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 16. 0x18 16. 0x98 16. " ENA208 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 15. 0x18 15. 0x98 15. " ENA207 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 14. 0x18 14. 0x98 14. " ENA206 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 13. 0x18 13. 0x98 13. " ENA205 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 12. 0x18 12. 0x98 12. " ENA204 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 11. 0x18 11. 0x98 11. " ENA203 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 10. 0x18 10. 0x98 10. " ENA202 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 9. 0x18 9. 0x98 9. " ENA201 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 8. 0x18 8. 0x98 8. " ENA200 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 7. 0x18 7. 0x98 7. " ENA199 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 6. 0x18 6. 0x98 6. " ENA198 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 5. 0x18 5. 0x98 5. " ENA197 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 4. 0x18 4. 0x98 4. " ENA196 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 3. 0x18 3. 0x98 3. " ENA195 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 2. 0x18 2. 0x98 2. " ENA194 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 1. 0x18 1. 0x98 1. " ENA193 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 0. 0x18 0. 0x98 0. " ENA192 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x1c "IRQ224_239_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x1c 15. 0x1c 15. 0x9c 15. " ENA239 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 14. 0x1c 14. 0x9c 14. " ENA238 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 13. 0x1c 13. 0x9c 13. " ENA237 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 12. 0x1c 12. 0x9c 12. " ENA236 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 11. 0x1c 11. 0x9c 11. " ENA235 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 10. 0x1c 10. 0x9c 10. " ENA234 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x1c 9. 0x1c 9. 0x9c 9. " ENA233 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 8. 0x1c 8. 0x9c 8. " ENA232 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 7. 0x1c 7. 0x9c 7. " ENA231 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 6. 0x1c 6. 0x9c 6. " ENA230 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 5. 0x1c 5. 0x9c 5. " ENA229 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 4. 0x1c 4. 0x9c 4. " ENA228 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x1c 3. 0x1c 3. 0x9c 3. " ENA227 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 2. 0x1c 2. 0x9c 2. " ENA226 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 1. 0x1c 1. 0x9c 1. " ENA225 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 0. 0x1c 0. 0x9c 0. " ENA224 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" else hgroup.long 0x100++0x1F hide.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" hide.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register" hide.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register" hide.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register" hide.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register" hide.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register" hide.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register" hide.long 0x1c "IRQ224_239_EN_SET/CLR,Interrupt Enable Register" endif tree.end tree "Interrupt Pending Registers" width 23. if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00) group.long 0x200++0x03 line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01) group.long 0x200++0x07 line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02) group.long 0x200++0x0B line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03) group.long 0x200++0x0F line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04) group.long 0x200++0x13 line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05) group.long 0x200++0x17 line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 30. 0x14 30. 0x94 30. " PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 29. 0x14 29. 0x94 29. " PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 28. 0x14 28. 0x94 28. " PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 27. 0x14 27. 0x94 27. " PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 26. 0x14 26. 0x94 26. " PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 24. 0x14 24. 0x94 24. " PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 23. 0x14 23. 0x94 23. " PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 22. 0x14 22. 0x94 22. " PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 21. 0x14 21. 0x94 21. " PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 20. 0x14 20. 0x94 20. " PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 18. 0x14 18. 0x94 18. " PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 17. 0x14 17. 0x94 17. " PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 16. 0x14 16. 0x94 16. " PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 15. 0x14 15. 0x94 15. " PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 14. 0x14 14. 0x94 14. " PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 12. 0x14 12. 0x94 12. " PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 11. 0x14 11. 0x94 11. " PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 10. 0x14 10. 0x94 10. " PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 9. 0x14 9. 0x94 9. " PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 8. 0x14 8. 0x94 8. " PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 6. 0x14 6. 0x94 6. " PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 5. 0x14 5. 0x94 5. " PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 4. 0x14 4. 0x94 4. " PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 3. 0x14 3. 0x94 3. " PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 2. 0x14 2. 0x94 2. " PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 0. 0x14 0. 0x94 0. " PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06) group.long 0x200++0x1B line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 30. 0x14 30. 0x94 30. " PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 29. 0x14 29. 0x94 29. " PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 28. 0x14 28. 0x94 28. " PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 27. 0x14 27. 0x94 27. " PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 26. 0x14 26. 0x94 26. " PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 24. 0x14 24. 0x94 24. " PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 23. 0x14 23. 0x94 23. " PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 22. 0x14 22. 0x94 22. " PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 21. 0x14 21. 0x94 21. " PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 20. 0x14 20. 0x94 20. " PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 18. 0x14 18. 0x94 18. " PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 17. 0x14 17. 0x94 17. " PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 16. 0x14 16. 0x94 16. " PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 15. 0x14 15. 0x94 15. " PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 14. 0x14 14. 0x94 14. " PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 12. 0x14 12. 0x94 12. " PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 11. 0x14 11. 0x94 11. " PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 10. 0x14 10. 0x94 10. " PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 9. 0x14 9. 0x94 9. " PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 8. 0x14 8. 0x94 8. " PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 6. 0x14 6. 0x94 6. " PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 5. 0x14 5. 0x94 5. " PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 4. 0x14 4. 0x94 4. " PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 3. 0x14 3. 0x94 3. " PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 2. 0x14 2. 0x94 2. " PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 0. 0x14 0. 0x94 0. " PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x18 31. 0x18 31. 0x98 31. " PEN223 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 30. 0x18 30. 0x98 30. " PEN222 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 29. 0x18 29. 0x98 29. " PEN221 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 28. 0x18 28. 0x98 28. " PEN220 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 27. 0x18 27. 0x98 27. " PEN219 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 26. 0x18 26. 0x98 26. " PEN218 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 25. 0x18 25. 0x98 25. " PEN217 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 24. 0x18 24. 0x98 24. " PEN216 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 23. 0x18 23. 0x98 23. " PEN215 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 22. 0x18 22. 0x98 22. " PEN214 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 21. 0x18 21. 0x98 21. " PEN213 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 20. 0x18 20. 0x98 20. " PEN212 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 19. 0x18 19. 0x98 19. " PEN211 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 18. 0x18 18. 0x98 18. " PEN210 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 17. 0x18 17. 0x98 17. " PEN209 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 16. 0x18 16. 0x98 16. " PEN208 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 15. 0x18 15. 0x98 15. " PEN207 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 14. 0x18 14. 0x98 14. " PEN206 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 13. 0x18 13. 0x98 13. " PEN205 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 12. 0x18 12. 0x98 12. " PEN204 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 11. 0x18 11. 0x98 11. " PEN203 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 10. 0x18 10. 0x98 10. " PEN202 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 9. 0x18 9. 0x98 9. " PEN201 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 8. 0x18 8. 0x98 8. " PEN200 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 7. 0x18 7. 0x98 7. " PEN199 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 6. 0x18 6. 0x98 6. " PEN198 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 5. 0x18 5. 0x98 5. " PEN197 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 4. 0x18 4. 0x98 4. " PEN196 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 3. 0x18 3. 0x98 3. " PEN195 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 2. 0x18 2. 0x98 2. " PEN194 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 1. 0x18 1. 0x98 1. " PEN193 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 0. 0x18 0. 0x98 0. " PEN192 ,Interrupt Set/Clear Pending" "Not pending,Pending" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07) group.long 0x200++0x1F line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 30. 0x14 30. 0x94 30. " PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 29. 0x14 29. 0x94 29. " PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 28. 0x14 28. 0x94 28. " PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 27. 0x14 27. 0x94 27. " PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 26. 0x14 26. 0x94 26. " PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 24. 0x14 24. 0x94 24. " PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 23. 0x14 23. 0x94 23. " PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 22. 0x14 22. 0x94 22. " PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 21. 0x14 21. 0x94 21. " PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 20. 0x14 20. 0x94 20. " PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 18. 0x14 18. 0x94 18. " PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 17. 0x14 17. 0x94 17. " PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 16. 0x14 16. 0x94 16. " PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 15. 0x14 15. 0x94 15. " PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 14. 0x14 14. 0x94 14. " PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 12. 0x14 12. 0x94 12. " PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 11. 0x14 11. 0x94 11. " PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 10. 0x14 10. 0x94 10. " PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 9. 0x14 9. 0x94 9. " PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 8. 0x14 8. 0x94 8. " PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 6. 0x14 6. 0x94 6. " PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 5. 0x14 5. 0x94 5. " PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 4. 0x14 4. 0x94 4. " PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 3. 0x14 3. 0x94 3. " PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 2. 0x14 2. 0x94 2. " PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 0. 0x14 0. 0x94 0. " PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x18 31. 0x18 31. 0x98 31. " PEN223 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 30. 0x18 30. 0x98 30. " PEN222 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 29. 0x18 29. 0x98 29. " PEN221 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 28. 0x18 28. 0x98 28. " PEN220 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 27. 0x18 27. 0x98 27. " PEN219 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 26. 0x18 26. 0x98 26. " PEN218 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 25. 0x18 25. 0x98 25. " PEN217 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 24. 0x18 24. 0x98 24. " PEN216 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 23. 0x18 23. 0x98 23. " PEN215 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 22. 0x18 22. 0x98 22. " PEN214 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 21. 0x18 21. 0x98 21. " PEN213 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 20. 0x18 20. 0x98 20. " PEN212 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 19. 0x18 19. 0x98 19. " PEN211 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 18. 0x18 18. 0x98 18. " PEN210 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 17. 0x18 17. 0x98 17. " PEN209 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 16. 0x18 16. 0x98 16. " PEN208 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 15. 0x18 15. 0x98 15. " PEN207 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 14. 0x18 14. 0x98 14. " PEN206 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 13. 0x18 13. 0x98 13. " PEN205 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 12. 0x18 12. 0x98 12. " PEN204 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 11. 0x18 11. 0x98 11. " PEN203 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 10. 0x18 10. 0x98 10. " PEN202 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 9. 0x18 9. 0x98 9. " PEN201 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 8. 0x18 8. 0x98 8. " PEN200 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 7. 0x18 7. 0x98 7. " PEN199 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 6. 0x18 6. 0x98 6. " PEN198 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 5. 0x18 5. 0x98 5. " PEN197 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 4. 0x18 4. 0x98 4. " PEN196 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 3. 0x18 3. 0x98 3. " PEN195 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 2. 0x18 2. 0x98 2. " PEN194 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 1. 0x18 1. 0x98 1. " PEN193 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 0. 0x18 0. 0x98 0. " PEN192 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x1c "IRQ224_239_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x1c 15. 0x1c 15. 0x9c 15. " PEN239 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 14. 0x1c 14. 0x9c 14. " PEN238 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 13. 0x1c 13. 0x9c 13. " PEN237 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 12. 0x1c 12. 0x9c 12. " PEN236 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 11. 0x1c 11. 0x9c 11. " PEN235 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 10. 0x1c 10. 0x9c 10. " PEN234 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x1c 9. 0x1c 9. 0x9c 9. " PEN233 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 8. 0x1c 8. 0x9c 8. " PEN232 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 7. 0x1c 7. 0x9c 7. " PEN231 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 6. 0x1c 6. 0x9c 6. " PEN230 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 5. 0x1c 5. 0x9c 5. " PEN229 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 4. 0x1c 4. 0x9c 4. " PEN228 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x1c 3. 0x1c 3. 0x9c 3. " PEN227 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 2. 0x1c 2. 0x9c 2. " PEN226 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 1. 0x1c 1. 0x9c 1. " PEN225 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 0. 0x1c 0. 0x9c 0. " PEN224 ,Interrupt Set/Clear Pending" "Not pending,Pending" else hgroup.long 0x200++0x1F hide.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" hide.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register" hide.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register" hide.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register" hide.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register" hide.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register" hide.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register" hide.long 0x1c "IRQ224_239_PEN_SET/CLR,Interrupt Pending Register" endif tree.end tree "Interrupt Active Bit Registers" width 9. if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00) rgroup.long 0x300++0x03 line.long 0x00 "ACTIVE1,Active Bit Register 1" bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01) rgroup.long 0x300++0x07 line.long 0x00 "ACTIVE1,Active Bit Register 1" bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active" line.long 0x04 "ACTIVE2,Active Bit Register 2" bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02) rgroup.long 0x300++0x0B line.long 0x00 "ACTIVE1,Active Bit Register 1" bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active" line.long 0x04 "ACTIVE2,Active Bit Register 2" bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active" line.long 0x08 "ACTIVE3,Active Bit Register 3" bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03) rgroup.long 0x300++0x0F line.long 0x00 "ACTIVE1,Active Bit Register 1" bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active" line.long 0x04 "ACTIVE2,Active Bit Register 2" bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active" line.long 0x08 "ACTIVE3,Active Bit Register 3" bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active" line.long 0x0c "ACTIVE4,Active Bit Register 4" bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04) rgroup.long 0x300++0x13 line.long 0x00 "ACTIVE1,Active Bit Register 1" bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active" line.long 0x04 "ACTIVE2,Active Bit Register 2" bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active" line.long 0x08 "ACTIVE3,Active Bit Register 3" bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active" line.long 0x0c "ACTIVE4,Active Bit Register 4" bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active" line.long 0x10 "ACTIVE5,Active Bit Register 5" bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05) rgroup.long 0x300++0x17 line.long 0x00 "ACTIVE1,Active Bit Register 1" bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active" line.long 0x04 "ACTIVE2,Active Bit Register 2" bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active" line.long 0x08 "ACTIVE3,Active Bit Register 3" bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active" line.long 0x0c "ACTIVE4,Active Bit Register 4" bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active" line.long 0x10 "ACTIVE5,Active Bit Register 5" bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active" line.long 0x14 "ACTIVE6,Active Bit Register 6" bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 30. " ACTIVE190 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 29. " ACTIVE189 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 28. " ACTIVE188 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 27. " ACTIVE187 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 26. " ACTIVE186 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 24. " ACTIVE184 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 23. " ACTIVE183 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 22. " ACTIVE182 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 21. " ACTIVE181 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 20. " ACTIVE180 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 18. " ACTIVE178 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 17. " ACTIVE177 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 16. " ACTIVE176 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 15. " ACTIVE175 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 14. " ACTIVE174 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 12. " ACTIVE172 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 11. " ACTIVE171 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 10. " ACTIVE170 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 9. " ACTIVE169 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 8. " ACTIVE168 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 6. " ACTIVE166 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 5. " ACTIVE165 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 4. " ACTIVE164 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 3. " ACTIVE163 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 2. " ACTIVE162 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 0. " ACTIVE160 ,Interrupt Active Flag" "Not active,Active" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06) rgroup.long 0x300++0x1B line.long 0x00 "ACTIVE1,Active Bit Register 1" bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active" line.long 0x04 "ACTIVE2,Active Bit Register 2" bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active" line.long 0x08 "ACTIVE3,Active Bit Register 3" bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active" line.long 0x0c "ACTIVE4,Active Bit Register 4" bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active" line.long 0x10 "ACTIVE5,Active Bit Register 5" bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active" line.long 0x14 "ACTIVE6,Active Bit Register 6" bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 30. " ACTIVE190 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 29. " ACTIVE189 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 28. " ACTIVE188 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 27. " ACTIVE187 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 26. " ACTIVE186 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 24. " ACTIVE184 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 23. " ACTIVE183 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 22. " ACTIVE182 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 21. " ACTIVE181 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 20. " ACTIVE180 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 18. " ACTIVE178 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 17. " ACTIVE177 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 16. " ACTIVE176 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 15. " ACTIVE175 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 14. " ACTIVE174 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 12. " ACTIVE172 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 11. " ACTIVE171 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 10. " ACTIVE170 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 9. " ACTIVE169 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 8. " ACTIVE168 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 6. " ACTIVE166 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 5. " ACTIVE165 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 4. " ACTIVE164 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 3. " ACTIVE163 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 2. " ACTIVE162 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 0. " ACTIVE160 ,Interrupt Active Flag" "Not active,Active" line.long 0x18 "ACTIVE7,Active Bit Register 7" bitfld.long 0x18 31. " ACTIVE223 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 30. " ACTIVE222 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 29. " ACTIVE221 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 28. " ACTIVE220 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 27. " ACTIVE219 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 26. " ACTIVE218 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 25. " ACTIVE217 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 24. " ACTIVE216 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 23. " ACTIVE215 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 22. " ACTIVE214 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 21. " ACTIVE213 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 20. " ACTIVE212 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 19. " ACTIVE211 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 18. " ACTIVE210 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 17. " ACTIVE209 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 16. " ACTIVE208 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 15. " ACTIVE207 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 14. " ACTIVE206 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 13. " ACTIVE205 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 12. " ACTIVE204 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 11. " ACTIVE203 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 10. " ACTIVE202 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 9. " ACTIVE201 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 8. " ACTIVE200 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 7. " ACTIVE199 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 6. " ACTIVE198 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 5. " ACTIVE197 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 4. " ACTIVE196 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 3. " ACTIVE195 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 2. " ACTIVE194 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 1. " ACTIVE193 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 0. " ACTIVE192 ,Interrupt Active Flag" "Not active,Active" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07) rgroup.long 0x300++0x1F line.long 0x00 "ACTIVE1,Active Bit Register 1" bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active" line.long 0x04 "ACTIVE2,Active Bit Register 2" bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active" line.long 0x08 "ACTIVE3,Active Bit Register 3" bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active" line.long 0x0c "ACTIVE4,Active Bit Register 4" bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active" line.long 0x10 "ACTIVE5,Active Bit Register 5" bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active" line.long 0x14 "ACTIVE6,Active Bit Register 6" bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 30. " ACTIVE190 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 29. " ACTIVE189 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 28. " ACTIVE188 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 27. " ACTIVE187 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 26. " ACTIVE186 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 24. " ACTIVE184 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 23. " ACTIVE183 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 22. " ACTIVE182 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 21. " ACTIVE181 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 20. " ACTIVE180 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 18. " ACTIVE178 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 17. " ACTIVE177 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 16. " ACTIVE176 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 15. " ACTIVE175 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 14. " ACTIVE174 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 12. " ACTIVE172 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 11. " ACTIVE171 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 10. " ACTIVE170 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 9. " ACTIVE169 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 8. " ACTIVE168 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 6. " ACTIVE166 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 5. " ACTIVE165 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 4. " ACTIVE164 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 3. " ACTIVE163 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 2. " ACTIVE162 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 0. " ACTIVE160 ,Interrupt Active Flag" "Not active,Active" line.long 0x18 "ACTIVE7,Active Bit Register 7" bitfld.long 0x18 31. " ACTIVE223 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 30. " ACTIVE222 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 29. " ACTIVE221 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 28. " ACTIVE220 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 27. " ACTIVE219 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 26. " ACTIVE218 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 25. " ACTIVE217 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 24. " ACTIVE216 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 23. " ACTIVE215 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 22. " ACTIVE214 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 21. " ACTIVE213 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 20. " ACTIVE212 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 19. " ACTIVE211 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 18. " ACTIVE210 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 17. " ACTIVE209 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 16. " ACTIVE208 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 15. " ACTIVE207 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 14. " ACTIVE206 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 13. " ACTIVE205 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 12. " ACTIVE204 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 11. " ACTIVE203 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 10. " ACTIVE202 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 9. " ACTIVE201 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 8. " ACTIVE200 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 7. " ACTIVE199 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 6. " ACTIVE198 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 5. " ACTIVE197 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 4. " ACTIVE196 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 3. " ACTIVE195 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 2. " ACTIVE194 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 1. " ACTIVE193 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 0. " ACTIVE192 ,Interrupt Active Flag" "Not active,Active" line.long 0x1c "ACTIVE8,Active Bit Register 8" bitfld.long 0x1c 15. " ACTIVE239 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 14. " ACTIVE238 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 13. " ACTIVE237 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 12. " ACTIVE236 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 11. " ACTIVE235 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 10. " ACTIVE234 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x1c 9. " ACTIVE233 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 8. " ACTIVE232 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 7. " ACTIVE231 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 6. " ACTIVE230 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 5. " ACTIVE229 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 4. " ACTIVE228 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x1c 3. " ACTIVE227 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 2. " ACTIVE226 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 1. " ACTIVE225 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 0. " ACTIVE224 ,Interrupt Active Flag" "Not active,Active" else hgroup.long 0x300++0x1F hide.long 0x00 "ACTIVE1,Active Bit Register 1" hide.long 0x04 "ACTIVE2,Active Bit Register 2" hide.long 0x08 "ACTIVE3,Active Bit Register 3" hide.long 0x0c "ACTIVE4,Active Bit Register 4" hide.long 0x10 "ACTIVE5,Active Bit Register 5" hide.long 0x14 "ACTIVE6,Active Bit Register 6" hide.long 0x18 "ACTIVE7,Active Bit Register 7" hide.long 0x1c "ACTIVE8,Active Bit Register 8" endif tree.end tree "Interrupt Priority Registers" if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00) group.long 0x400++0x1F line.long 0x0 "IPR0,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority" line.long 0x4 "IPR1,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority" line.long 0x8 "IPR2,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority" line.long 0xC "IPR3,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority" line.long 0x10 "IPR4,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority" line.long 0x14 "IPR5,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority" line.long 0x18 "IPR6,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority" line.long 0x1C "IPR7,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01) group.long 0x400++0x3F line.long 0x0 "IPR0,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority" line.long 0x4 "IPR1,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority" line.long 0x8 "IPR2,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority" line.long 0xC "IPR3,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority" line.long 0x10 "IPR4,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority" line.long 0x14 "IPR5,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority" line.long 0x18 "IPR6,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority" line.long 0x1C "IPR7,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority" line.long 0x20 "IPR8,Interrupt Priority Register" hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority" hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority" hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority" hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority" line.long 0x24 "IPR9,Interrupt Priority Register" hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority" hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority" hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority" hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority" line.long 0x28 "IPR10,Interrupt Priority Register" hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority" hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority" hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority" hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority" line.long 0x2C "IPR11,Interrupt Priority Register" hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority" hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority" hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority" hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority" line.long 0x30 "IPR12,Interrupt Priority Register" hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority" hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority" hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority" hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority" line.long 0x34 "IPR13,Interrupt Priority Register" hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority" hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority" hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority" hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority" line.long 0x38 "IPR14,Interrupt Priority Register" hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority" hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority" hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority" hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority" line.long 0x3C "IPR15,Interrupt Priority Register" hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority" hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority" hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority" hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02) group.long 0x400++0x5F line.long 0x0 "IPR0,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority" line.long 0x4 "IPR1,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority" line.long 0x8 "IPR2,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority" line.long 0xC "IPR3,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority" line.long 0x10 "IPR4,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority" line.long 0x14 "IPR5,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority" line.long 0x18 "IPR6,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority" line.long 0x1C "IPR7,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority" line.long 0x20 "IPR8,Interrupt Priority Register" hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority" hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority" hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority" hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority" line.long 0x24 "IPR9,Interrupt Priority Register" hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority" hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority" hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority" hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority" line.long 0x28 "IPR10,Interrupt Priority Register" hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority" hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority" hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority" hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority" line.long 0x2C "IPR11,Interrupt Priority Register" hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority" hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority" hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority" hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority" line.long 0x30 "IPR12,Interrupt Priority Register" hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority" hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority" hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority" hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority" line.long 0x34 "IPR13,Interrupt Priority Register" hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority" hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority" hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority" hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority" line.long 0x38 "IPR14,Interrupt Priority Register" hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority" hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority" hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority" hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority" line.long 0x3C "IPR15,Interrupt Priority Register" hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority" hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority" hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority" hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority" line.long 0x40 "IPR16,Interrupt Priority Register" hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority" hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority" hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority" hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority" line.long 0x44 "IPR17,Interrupt Priority Register" hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority" hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority" hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority" hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority" line.long 0x48 "IPR18,Interrupt Priority Register" hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority" hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority" hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority" hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority" line.long 0x4C "IPR19,Interrupt Priority Register" hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority" hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority" hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority" hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority" line.long 0x50 "IPR20,Interrupt Priority Register" hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority" hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority" hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority" hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority" line.long 0x54 "IPR21,Interrupt Priority Register" hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority" hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority" hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority" hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority" line.long 0x58 "IPR22,Interrupt Priority Register" hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority" hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority" hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority" hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority" line.long 0x5C "IPR23,Interrupt Priority Register" hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority" hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority" hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority" hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03) group.long 0x400++0x7F line.long 0x0 "IPR0,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority" line.long 0x4 "IPR1,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority" line.long 0x8 "IPR2,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority" line.long 0xC "IPR3,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority" line.long 0x10 "IPR4,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority" line.long 0x14 "IPR5,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority" line.long 0x18 "IPR6,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority" line.long 0x1C "IPR7,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority" line.long 0x20 "IPR8,Interrupt Priority Register" hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority" hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority" hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority" hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority" line.long 0x24 "IPR9,Interrupt Priority Register" hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority" hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority" hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority" hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority" line.long 0x28 "IPR10,Interrupt Priority Register" hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority" hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority" hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority" hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority" line.long 0x2C "IPR11,Interrupt Priority Register" hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority" hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority" hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority" hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority" line.long 0x30 "IPR12,Interrupt Priority Register" hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority" hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority" hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority" hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority" line.long 0x34 "IPR13,Interrupt Priority Register" hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority" hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority" hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority" hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority" line.long 0x38 "IPR14,Interrupt Priority Register" hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority" hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority" hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority" hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority" line.long 0x3C "IPR15,Interrupt Priority Register" hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority" hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority" hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority" hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority" line.long 0x40 "IPR16,Interrupt Priority Register" hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority" hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority" hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority" hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority" line.long 0x44 "IPR17,Interrupt Priority Register" hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority" hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority" hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority" hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority" line.long 0x48 "IPR18,Interrupt Priority Register" hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority" hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority" hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority" hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority" line.long 0x4C "IPR19,Interrupt Priority Register" hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority" hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority" hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority" hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority" line.long 0x50 "IPR20,Interrupt Priority Register" hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority" hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority" hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority" hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority" line.long 0x54 "IPR21,Interrupt Priority Register" hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority" hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority" hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority" hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority" line.long 0x58 "IPR22,Interrupt Priority Register" hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority" hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority" hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority" hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority" line.long 0x5C "IPR23,Interrupt Priority Register" hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority" hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority" hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority" hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority" line.long 0x60 "IPR24,Interrupt Priority Register" hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority" hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority" hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority" hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority" line.long 0x64 "IPR25,Interrupt Priority Register" hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority" hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority" hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority" hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority" line.long 0x68 "IPR26,Interrupt Priority Register" hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority" hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority" hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority" hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority" line.long 0x6C "IPR27,Interrupt Priority Register" hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority" hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority" hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority" hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority" line.long 0x70 "IPR28,Interrupt Priority Register" hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority" hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority" hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority" hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority" line.long 0x74 "IPR29,Interrupt Priority Register" hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority" hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority" hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority" hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority" line.long 0x78 "IPR30,Interrupt Priority Register" hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority" hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority" hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority" hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority" line.long 0x7C "IPR31,Interrupt Priority Register" hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority" hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority" hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority" hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04) group.long 0x400++0x9F line.long 0x0 "IPR0,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority" line.long 0x4 "IPR1,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority" line.long 0x8 "IPR2,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority" line.long 0xC "IPR3,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority" line.long 0x10 "IPR4,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority" line.long 0x14 "IPR5,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority" line.long 0x18 "IPR6,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority" line.long 0x1C "IPR7,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority" line.long 0x20 "IPR8,Interrupt Priority Register" hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority" hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority" hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority" hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority" line.long 0x24 "IPR9,Interrupt Priority Register" hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority" hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority" hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority" hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority" line.long 0x28 "IPR10,Interrupt Priority Register" hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority" hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority" hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority" hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority" line.long 0x2C "IPR11,Interrupt Priority Register" hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority" hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority" hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority" hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority" line.long 0x30 "IPR12,Interrupt Priority Register" hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority" hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority" hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority" hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority" line.long 0x34 "IPR13,Interrupt Priority Register" hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority" hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority" hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority" hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority" line.long 0x38 "IPR14,Interrupt Priority Register" hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority" hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority" hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority" hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority" line.long 0x3C "IPR15,Interrupt Priority Register" hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority" hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority" hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority" hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority" line.long 0x40 "IPR16,Interrupt Priority Register" hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority" hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority" hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority" hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority" line.long 0x44 "IPR17,Interrupt Priority Register" hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority" hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority" hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority" hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority" line.long 0x48 "IPR18,Interrupt Priority Register" hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority" hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority" hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority" hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority" line.long 0x4C "IPR19,Interrupt Priority Register" hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority" hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority" hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority" hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority" line.long 0x50 "IPR20,Interrupt Priority Register" hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority" hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority" hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority" hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority" line.long 0x54 "IPR21,Interrupt Priority Register" hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority" hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority" hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority" hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority" line.long 0x58 "IPR22,Interrupt Priority Register" hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority" hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority" hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority" hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority" line.long 0x5C "IPR23,Interrupt Priority Register" hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority" hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority" hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority" hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority" line.long 0x60 "IPR24,Interrupt Priority Register" hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority" hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority" hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority" hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority" line.long 0x64 "IPR25,Interrupt Priority Register" hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority" hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority" hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority" hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority" line.long 0x68 "IPR26,Interrupt Priority Register" hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority" hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority" hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority" hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority" line.long 0x6C "IPR27,Interrupt Priority Register" hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority" hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority" hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority" hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority" line.long 0x70 "IPR28,Interrupt Priority Register" hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority" hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority" hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority" hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority" line.long 0x74 "IPR29,Interrupt Priority Register" hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority" hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority" hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority" hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority" line.long 0x78 "IPR30,Interrupt Priority Register" hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority" hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority" hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority" hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority" line.long 0x7C "IPR31,Interrupt Priority Register" hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority" hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority" hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority" hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority" line.long 0x80 "IPR32,Interrupt Priority Register" hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority" hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority" hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority" hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority" line.long 0x84 "IPR33,Interrupt Priority Register" hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority" hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority" hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority" hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority" line.long 0x88 "IPR34,Interrupt Priority Register" hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority" hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority" hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority" hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority" line.long 0x8C "IPR35,Interrupt Priority Register" hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority" hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority" hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority" hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority" line.long 0x90 "IPR36,Interrupt Priority Register" hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority" hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority" hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority" hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority" line.long 0x94 "IPR37,Interrupt Priority Register" hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority" hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority" hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority" hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority" line.long 0x98 "IPR38,Interrupt Priority Register" hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority" hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority" hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority" hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority" line.long 0x9C "IPR39,Interrupt Priority Register" hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority" hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority" hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority" hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05) group.long 0x400++0xBF line.long 0x0 "IPR0,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority" line.long 0x4 "IPR1,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority" line.long 0x8 "IPR2,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority" line.long 0xC "IPR3,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority" line.long 0x10 "IPR4,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority" line.long 0x14 "IPR5,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority" line.long 0x18 "IPR6,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority" line.long 0x1C "IPR7,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority" line.long 0x20 "IPR8,Interrupt Priority Register" hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority" hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority" hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority" hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority" line.long 0x24 "IPR9,Interrupt Priority Register" hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority" hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority" hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority" hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority" line.long 0x28 "IPR10,Interrupt Priority Register" hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority" hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority" hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority" hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority" line.long 0x2C "IPR11,Interrupt Priority Register" hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority" hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority" hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority" hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority" line.long 0x30 "IPR12,Interrupt Priority Register" hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority" hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority" hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority" hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority" line.long 0x34 "IPR13,Interrupt Priority Register" hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority" hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority" hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority" hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority" line.long 0x38 "IPR14,Interrupt Priority Register" hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority" hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority" hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority" hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority" line.long 0x3C "IPR15,Interrupt Priority Register" hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority" hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority" hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority" hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority" line.long 0x40 "IPR16,Interrupt Priority Register" hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority" hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority" hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority" hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority" line.long 0x44 "IPR17,Interrupt Priority Register" hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority" hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority" hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority" hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority" line.long 0x48 "IPR18,Interrupt Priority Register" hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority" hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority" hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority" hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority" line.long 0x4C "IPR19,Interrupt Priority Register" hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority" hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority" hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority" hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority" line.long 0x50 "IPR20,Interrupt Priority Register" hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority" hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority" hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority" hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority" line.long 0x54 "IPR21,Interrupt Priority Register" hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority" hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority" hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority" hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority" line.long 0x58 "IPR22,Interrupt Priority Register" hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority" hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority" hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority" hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority" line.long 0x5C "IPR23,Interrupt Priority Register" hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority" hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority" hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority" hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority" line.long 0x60 "IPR24,Interrupt Priority Register" hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority" hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority" hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority" hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority" line.long 0x64 "IPR25,Interrupt Priority Register" hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority" hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority" hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority" hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority" line.long 0x68 "IPR26,Interrupt Priority Register" hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority" hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority" hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority" hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority" line.long 0x6C "IPR27,Interrupt Priority Register" hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority" hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority" hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority" hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority" line.long 0x70 "IPR28,Interrupt Priority Register" hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority" hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority" hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority" hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority" line.long 0x74 "IPR29,Interrupt Priority Register" hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority" hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority" hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority" hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority" line.long 0x78 "IPR30,Interrupt Priority Register" hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority" hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority" hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority" hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority" line.long 0x7C "IPR31,Interrupt Priority Register" hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority" hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority" hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority" hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority" line.long 0x80 "IPR32,Interrupt Priority Register" hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority" hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority" hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority" hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority" line.long 0x84 "IPR33,Interrupt Priority Register" hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority" hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority" hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority" hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority" line.long 0x88 "IPR34,Interrupt Priority Register" hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority" hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority" hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority" hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority" line.long 0x8C "IPR35,Interrupt Priority Register" hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority" hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority" hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority" hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority" line.long 0x90 "IPR36,Interrupt Priority Register" hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority" hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority" hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority" hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority" line.long 0x94 "IPR37,Interrupt Priority Register" hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority" hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority" hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority" hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority" line.long 0x98 "IPR38,Interrupt Priority Register" hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority" hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority" hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority" hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority" line.long 0x9C "IPR39,Interrupt Priority Register" hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority" hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority" hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority" hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority" line.long 0xA0 "IPR40,Interrupt Priority Register" hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority" hexmask.long.byte 0xA0 16.--23. 1. " PRI_162 ,Interrupt 162 Priority" hexmask.long.byte 0xA0 8.--15. 1. " PRI_161 ,Interrupt 161 Priority" hexmask.long.byte 0xA0 0.--7. 1. " PRI_160 ,Interrupt 160 Priority" line.long 0xA4 "IPR41,Interrupt Priority Register" hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority" hexmask.long.byte 0xA4 16.--23. 1. " PRI_166 ,Interrupt 166 Priority" hexmask.long.byte 0xA4 8.--15. 1. " PRI_165 ,Interrupt 165 Priority" hexmask.long.byte 0xA4 0.--7. 1. " PRI_164 ,Interrupt 164 Priority" line.long 0xA8 "IPR42,Interrupt Priority Register" hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority" hexmask.long.byte 0xA8 16.--23. 1. " PRI_170 ,Interrupt 170 Priority" hexmask.long.byte 0xA8 8.--15. 1. " PRI_169 ,Interrupt 169 Priority" hexmask.long.byte 0xA8 0.--7. 1. " PRI_168 ,Interrupt 168 Priority" line.long 0xAC "IPR43,Interrupt Priority Register" hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority" hexmask.long.byte 0xAC 16.--23. 1. " PRI_174 ,Interrupt 174 Priority" hexmask.long.byte 0xAC 8.--15. 1. " PRI_173 ,Interrupt 173 Priority" hexmask.long.byte 0xAC 0.--7. 1. " PRI_172 ,Interrupt 172 Priority" line.long 0xB0 "IPR44,Interrupt Priority Register" hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority" hexmask.long.byte 0xB0 16.--23. 1. " PRI_178 ,Interrupt 178 Priority" hexmask.long.byte 0xB0 8.--15. 1. " PRI_177 ,Interrupt 177 Priority" hexmask.long.byte 0xB0 0.--7. 1. " PRI_176 ,Interrupt 176 Priority" line.long 0xB4 "IPR45,Interrupt Priority Register" hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority" hexmask.long.byte 0xB4 16.--23. 1. " PRI_182 ,Interrupt 182 Priority" hexmask.long.byte 0xB4 8.--15. 1. " PRI_181 ,Interrupt 181 Priority" hexmask.long.byte 0xB4 0.--7. 1. " PRI_180 ,Interrupt 180 Priority" line.long 0xB8 "IPR46,Interrupt Priority Register" hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority" hexmask.long.byte 0xB8 16.--23. 1. " PRI_186 ,Interrupt 186 Priority" hexmask.long.byte 0xB8 8.--15. 1. " PRI_185 ,Interrupt 185 Priority" hexmask.long.byte 0xB8 0.--7. 1. " PRI_184 ,Interrupt 184 Priority" line.long 0xBC "IPR47,Interrupt Priority Register" hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority" hexmask.long.byte 0xBC 16.--23. 1. " PRI_190 ,Interrupt 190 Priority" hexmask.long.byte 0xBC 8.--15. 1. " PRI_189 ,Interrupt 189 Priority" hexmask.long.byte 0xBC 0.--7. 1. " PRI_188 ,Interrupt 188 Priority" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06) group.long 0x400++0xDF line.long 0x0 "IPR0,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority" line.long 0x4 "IPR1,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority" line.long 0x8 "IPR2,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority" line.long 0xC "IPR3,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority" line.long 0x10 "IPR4,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority" line.long 0x14 "IPR5,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority" line.long 0x18 "IPR6,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority" line.long 0x1C "IPR7,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority" line.long 0x20 "IPR8,Interrupt Priority Register" hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority" hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority" hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority" hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority" line.long 0x24 "IPR9,Interrupt Priority Register" hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority" hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority" hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority" hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority" line.long 0x28 "IPR10,Interrupt Priority Register" hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority" hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority" hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority" hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority" line.long 0x2C "IPR11,Interrupt Priority Register" hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority" hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority" hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority" hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority" line.long 0x30 "IPR12,Interrupt Priority Register" hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority" hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority" hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority" hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority" line.long 0x34 "IPR13,Interrupt Priority Register" hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority" hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority" hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority" hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority" line.long 0x38 "IPR14,Interrupt Priority Register" hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority" hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority" hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority" hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority" line.long 0x3C "IPR15,Interrupt Priority Register" hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority" hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority" hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority" hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority" line.long 0x40 "IPR16,Interrupt Priority Register" hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority" hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority" hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority" hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority" line.long 0x44 "IPR17,Interrupt Priority Register" hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority" hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority" hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority" hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority" line.long 0x48 "IPR18,Interrupt Priority Register" hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority" hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority" hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority" hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority" line.long 0x4C "IPR19,Interrupt Priority Register" hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority" hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority" hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority" hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority" line.long 0x50 "IPR20,Interrupt Priority Register" hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority" hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority" hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority" hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority" line.long 0x54 "IPR21,Interrupt Priority Register" hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority" hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority" hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority" hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority" line.long 0x58 "IPR22,Interrupt Priority Register" hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority" hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority" hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority" hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority" line.long 0x5C "IPR23,Interrupt Priority Register" hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority" hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority" hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority" hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority" line.long 0x60 "IPR24,Interrupt Priority Register" hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority" hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority" hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority" hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority" line.long 0x64 "IPR25,Interrupt Priority Register" hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority" hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority" hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority" hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority" line.long 0x68 "IPR26,Interrupt Priority Register" hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority" hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority" hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority" hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority" line.long 0x6C "IPR27,Interrupt Priority Register" hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority" hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority" hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority" hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority" line.long 0x70 "IPR28,Interrupt Priority Register" hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority" hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority" hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority" hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority" line.long 0x74 "IPR29,Interrupt Priority Register" hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority" hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority" hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority" hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority" line.long 0x78 "IPR30,Interrupt Priority Register" hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority" hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority" hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority" hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority" line.long 0x7C "IPR31,Interrupt Priority Register" hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority" hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority" hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority" hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority" line.long 0x80 "IPR32,Interrupt Priority Register" hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority" hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority" hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority" hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority" line.long 0x84 "IPR33,Interrupt Priority Register" hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority" hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority" hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority" hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority" line.long 0x88 "IPR34,Interrupt Priority Register" hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority" hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority" hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority" hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority" line.long 0x8C "IPR35,Interrupt Priority Register" hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority" hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority" hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority" hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority" line.long 0x90 "IPR36,Interrupt Priority Register" hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority" hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority" hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority" hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority" line.long 0x94 "IPR37,Interrupt Priority Register" hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority" hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority" hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority" hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority" line.long 0x98 "IPR38,Interrupt Priority Register" hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority" hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority" hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority" hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority" line.long 0x9C "IPR39,Interrupt Priority Register" hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority" hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority" hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority" hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority" line.long 0xA0 "IPR40,Interrupt Priority Register" hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority" hexmask.long.byte 0xA0 16.--23. 1. " PRI_162 ,Interrupt 162 Priority" hexmask.long.byte 0xA0 8.--15. 1. " PRI_161 ,Interrupt 161 Priority" hexmask.long.byte 0xA0 0.--7. 1. " PRI_160 ,Interrupt 160 Priority" line.long 0xA4 "IPR41,Interrupt Priority Register" hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority" hexmask.long.byte 0xA4 16.--23. 1. " PRI_166 ,Interrupt 166 Priority" hexmask.long.byte 0xA4 8.--15. 1. " PRI_165 ,Interrupt 165 Priority" hexmask.long.byte 0xA4 0.--7. 1. " PRI_164 ,Interrupt 164 Priority" line.long 0xA8 "IPR42,Interrupt Priority Register" hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority" hexmask.long.byte 0xA8 16.--23. 1. " PRI_170 ,Interrupt 170 Priority" hexmask.long.byte 0xA8 8.--15. 1. " PRI_169 ,Interrupt 169 Priority" hexmask.long.byte 0xA8 0.--7. 1. " PRI_168 ,Interrupt 168 Priority" line.long 0xAC "IPR43,Interrupt Priority Register" hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority" hexmask.long.byte 0xAC 16.--23. 1. " PRI_174 ,Interrupt 174 Priority" hexmask.long.byte 0xAC 8.--15. 1. " PRI_173 ,Interrupt 173 Priority" hexmask.long.byte 0xAC 0.--7. 1. " PRI_172 ,Interrupt 172 Priority" line.long 0xB0 "IPR44,Interrupt Priority Register" hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority" hexmask.long.byte 0xB0 16.--23. 1. " PRI_178 ,Interrupt 178 Priority" hexmask.long.byte 0xB0 8.--15. 1. " PRI_177 ,Interrupt 177 Priority" hexmask.long.byte 0xB0 0.--7. 1. " PRI_176 ,Interrupt 176 Priority" line.long 0xB4 "IPR45,Interrupt Priority Register" hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority" hexmask.long.byte 0xB4 16.--23. 1. " PRI_182 ,Interrupt 182 Priority" hexmask.long.byte 0xB4 8.--15. 1. " PRI_181 ,Interrupt 181 Priority" hexmask.long.byte 0xB4 0.--7. 1. " PRI_180 ,Interrupt 180 Priority" line.long 0xB8 "IPR46,Interrupt Priority Register" hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority" hexmask.long.byte 0xB8 16.--23. 1. " PRI_186 ,Interrupt 186 Priority" hexmask.long.byte 0xB8 8.--15. 1. " PRI_185 ,Interrupt 185 Priority" hexmask.long.byte 0xB8 0.--7. 1. " PRI_184 ,Interrupt 184 Priority" line.long 0xBC "IPR47,Interrupt Priority Register" hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority" hexmask.long.byte 0xBC 16.--23. 1. " PRI_190 ,Interrupt 190 Priority" hexmask.long.byte 0xBC 8.--15. 1. " PRI_189 ,Interrupt 189 Priority" hexmask.long.byte 0xBC 0.--7. 1. " PRI_188 ,Interrupt 188 Priority" line.long 0xC0 "IPR48,Interrupt Priority Register" hexmask.long.byte 0xC0 24.--31. 1. " PRI_195 ,Interrupt 195 Priority" hexmask.long.byte 0xC0 16.--23. 1. " PRI_194 ,Interrupt 194 Priority" hexmask.long.byte 0xC0 8.--15. 1. " PRI_193 ,Interrupt 193 Priority" hexmask.long.byte 0xC0 0.--7. 1. " PRI_192 ,Interrupt 192 Priority" line.long 0xC4 "IPR49,Interrupt Priority Register" hexmask.long.byte 0xC4 24.--31. 1. " PRI_199 ,Interrupt 199 Priority" hexmask.long.byte 0xC4 16.--23. 1. " PRI_198 ,Interrupt 198 Priority" hexmask.long.byte 0xC4 8.--15. 1. " PRI_197 ,Interrupt 197 Priority" hexmask.long.byte 0xC4 0.--7. 1. " PRI_196 ,Interrupt 196 Priority" line.long 0xC8 "IPR50,Interrupt Priority Register" hexmask.long.byte 0xC8 24.--31. 1. " PRI_203 ,Interrupt 203 Priority" hexmask.long.byte 0xC8 16.--23. 1. " PRI_202 ,Interrupt 202 Priority" hexmask.long.byte 0xC8 8.--15. 1. " PRI_201 ,Interrupt 201 Priority" hexmask.long.byte 0xC8 0.--7. 1. " PRI_200 ,Interrupt 200 Priority" line.long 0xCC "IPR51,Interrupt Priority Register" hexmask.long.byte 0xCC 24.--31. 1. " PRI_207 ,Interrupt 207 Priority" hexmask.long.byte 0xCC 16.--23. 1. " PRI_206 ,Interrupt 206 Priority" hexmask.long.byte 0xCC 8.--15. 1. " PRI_205 ,Interrupt 205 Priority" hexmask.long.byte 0xCC 0.--7. 1. " PRI_204 ,Interrupt 204 Priority" line.long 0xD0 "IPR52,Interrupt Priority Register" hexmask.long.byte 0xD0 24.--31. 1. " PRI_211 ,Interrupt 211 Priority" hexmask.long.byte 0xD0 16.--23. 1. " PRI_210 ,Interrupt 210 Priority" hexmask.long.byte 0xD0 8.--15. 1. " PRI_209 ,Interrupt 209 Priority" hexmask.long.byte 0xD0 0.--7. 1. " PRI_208 ,Interrupt 208 Priority" line.long 0xD4 "IPR53,Interrupt Priority Register" hexmask.long.byte 0xD4 24.--31. 1. " PRI_215 ,Interrupt 215 Priority" hexmask.long.byte 0xD4 16.--23. 1. " PRI_214 ,Interrupt 214 Priority" hexmask.long.byte 0xD4 8.--15. 1. " PRI_213 ,Interrupt 213 Priority" hexmask.long.byte 0xD4 0.--7. 1. " PRI_212 ,Interrupt 212 Priority" line.long 0xD8 "IPR54,Interrupt Priority Register" hexmask.long.byte 0xD8 24.--31. 1. " PRI_219 ,Interrupt 219 Priority" hexmask.long.byte 0xD8 16.--23. 1. " PRI_218 ,Interrupt 218 Priority" hexmask.long.byte 0xD8 8.--15. 1. " PRI_217 ,Interrupt 217 Priority" hexmask.long.byte 0xD8 0.--7. 1. " PRI_216 ,Interrupt 216 Priority" line.long 0xDC "IPR55,Interrupt Priority Register" hexmask.long.byte 0xDC 24.--31. 1. " PRI_223 ,Interrupt 223 Priority" hexmask.long.byte 0xDC 16.--23. 1. " PRI_222 ,Interrupt 222 Priority" hexmask.long.byte 0xDC 8.--15. 1. " PRI_221 ,Interrupt 221 Priority" hexmask.long.byte 0xDC 0.--7. 1. " PRI_220 ,Interrupt 220 Priority" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07) group.long 0x400++0xEF line.long 0x0 "IPR0,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority" line.long 0x4 "IPR1,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority" line.long 0x8 "IPR2,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority" line.long 0xC "IPR3,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority" line.long 0x10 "IPR4,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority" line.long 0x14 "IPR5,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority" line.long 0x18 "IPR6,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority" line.long 0x1C "IPR7,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority" line.long 0x20 "IPR8,Interrupt Priority Register" hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority" hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority" hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority" hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority" line.long 0x24 "IPR9,Interrupt Priority Register" hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority" hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority" hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority" hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority" line.long 0x28 "IPR10,Interrupt Priority Register" hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority" hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority" hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority" hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority" line.long 0x2C "IPR11,Interrupt Priority Register" hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority" hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority" hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority" hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority" line.long 0x30 "IPR12,Interrupt Priority Register" hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority" hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority" hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority" hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority" line.long 0x34 "IPR13,Interrupt Priority Register" hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority" hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority" hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority" hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority" line.long 0x38 "IPR14,Interrupt Priority Register" hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority" hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority" hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority" hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority" line.long 0x3C "IPR15,Interrupt Priority Register" hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority" hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority" hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority" hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority" line.long 0x40 "IPR16,Interrupt Priority Register" hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority" hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority" hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority" hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority" line.long 0x44 "IPR17,Interrupt Priority Register" hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority" hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority" hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority" hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority" line.long 0x48 "IPR18,Interrupt Priority Register" hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority" hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority" hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority" hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority" line.long 0x4C "IPR19,Interrupt Priority Register" hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority" hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority" hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority" hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority" line.long 0x50 "IPR20,Interrupt Priority Register" hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority" hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority" hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority" hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority" line.long 0x54 "IPR21,Interrupt Priority Register" hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority" hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority" hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority" hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority" line.long 0x58 "IPR22,Interrupt Priority Register" hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority" hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority" hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority" hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority" line.long 0x5C "IPR23,Interrupt Priority Register" hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority" hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority" hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority" hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority" line.long 0x60 "IPR24,Interrupt Priority Register" hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority" hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority" hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority" hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority" line.long 0x64 "IPR25,Interrupt Priority Register" hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority" hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority" hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority" hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority" line.long 0x68 "IPR26,Interrupt Priority Register" hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority" hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority" hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority" hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority" line.long 0x6C "IPR27,Interrupt Priority Register" hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority" hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority" hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority" hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority" line.long 0x70 "IPR28,Interrupt Priority Register" hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority" hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority" hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority" hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority" line.long 0x74 "IPR29,Interrupt Priority Register" hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority" hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority" hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority" hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority" line.long 0x78 "IPR30,Interrupt Priority Register" hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority" hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority" hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority" hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority" line.long 0x7C "IPR31,Interrupt Priority Register" hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority" hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority" hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority" hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority" line.long 0x80 "IPR32,Interrupt Priority Register" hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority" hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority" hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority" hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority" line.long 0x84 "IPR33,Interrupt Priority Register" hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority" hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority" hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority" hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority" line.long 0x88 "IPR34,Interrupt Priority Register" hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority" hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority" hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority" hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority" line.long 0x8C "IPR35,Interrupt Priority Register" hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority" hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority" hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority" hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority" line.long 0x90 "IPR36,Interrupt Priority Register" hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority" hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority" hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority" hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority" line.long 0x94 "IPR37,Interrupt Priority Register" hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority" hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority" hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority" hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority" line.long 0x98 "IPR38,Interrupt Priority Register" hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority" hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority" hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority" hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority" line.long 0x9C "IPR39,Interrupt Priority Register" hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority" hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority" hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority" hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority" line.long 0xA0 "IPR40,Interrupt Priority Register" hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority" hexmask.long.byte 0xA0 16.--23. 1. " PRI_162 ,Interrupt 162 Priority" hexmask.long.byte 0xA0 8.--15. 1. " PRI_161 ,Interrupt 161 Priority" hexmask.long.byte 0xA0 0.--7. 1. " PRI_160 ,Interrupt 160 Priority" line.long 0xA4 "IPR41,Interrupt Priority Register" hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority" hexmask.long.byte 0xA4 16.--23. 1. " PRI_166 ,Interrupt 166 Priority" hexmask.long.byte 0xA4 8.--15. 1. " PRI_165 ,Interrupt 165 Priority" hexmask.long.byte 0xA4 0.--7. 1. " PRI_164 ,Interrupt 164 Priority" line.long 0xA8 "IPR42,Interrupt Priority Register" hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority" hexmask.long.byte 0xA8 16.--23. 1. " PRI_170 ,Interrupt 170 Priority" hexmask.long.byte 0xA8 8.--15. 1. " PRI_169 ,Interrupt 169 Priority" hexmask.long.byte 0xA8 0.--7. 1. " PRI_168 ,Interrupt 168 Priority" line.long 0xAC "IPR43,Interrupt Priority Register" hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority" hexmask.long.byte 0xAC 16.--23. 1. " PRI_174 ,Interrupt 174 Priority" hexmask.long.byte 0xAC 8.--15. 1. " PRI_173 ,Interrupt 173 Priority" hexmask.long.byte 0xAC 0.--7. 1. " PRI_172 ,Interrupt 172 Priority" line.long 0xB0 "IPR44,Interrupt Priority Register" hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority" hexmask.long.byte 0xB0 16.--23. 1. " PRI_178 ,Interrupt 178 Priority" hexmask.long.byte 0xB0 8.--15. 1. " PRI_177 ,Interrupt 177 Priority" hexmask.long.byte 0xB0 0.--7. 1. " PRI_176 ,Interrupt 176 Priority" line.long 0xB4 "IPR45,Interrupt Priority Register" hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority" hexmask.long.byte 0xB4 16.--23. 1. " PRI_182 ,Interrupt 182 Priority" hexmask.long.byte 0xB4 8.--15. 1. " PRI_181 ,Interrupt 181 Priority" hexmask.long.byte 0xB4 0.--7. 1. " PRI_180 ,Interrupt 180 Priority" line.long 0xB8 "IPR46,Interrupt Priority Register" hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority" hexmask.long.byte 0xB8 16.--23. 1. " PRI_186 ,Interrupt 186 Priority" hexmask.long.byte 0xB8 8.--15. 1. " PRI_185 ,Interrupt 185 Priority" hexmask.long.byte 0xB8 0.--7. 1. " PRI_184 ,Interrupt 184 Priority" line.long 0xBC "IPR47,Interrupt Priority Register" hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority" hexmask.long.byte 0xBC 16.--23. 1. " PRI_190 ,Interrupt 190 Priority" hexmask.long.byte 0xBC 8.--15. 1. " PRI_189 ,Interrupt 189 Priority" hexmask.long.byte 0xBC 0.--7. 1. " PRI_188 ,Interrupt 188 Priority" line.long 0xC0 "IPR48,Interrupt Priority Register" hexmask.long.byte 0xC0 24.--31. 1. " PRI_195 ,Interrupt 195 Priority" hexmask.long.byte 0xC0 16.--23. 1. " PRI_194 ,Interrupt 194 Priority" hexmask.long.byte 0xC0 8.--15. 1. " PRI_193 ,Interrupt 193 Priority" hexmask.long.byte 0xC0 0.--7. 1. " PRI_192 ,Interrupt 192 Priority" line.long 0xC4 "IPR49,Interrupt Priority Register" hexmask.long.byte 0xC4 24.--31. 1. " PRI_199 ,Interrupt 199 Priority" hexmask.long.byte 0xC4 16.--23. 1. " PRI_198 ,Interrupt 198 Priority" hexmask.long.byte 0xC4 8.--15. 1. " PRI_197 ,Interrupt 197 Priority" hexmask.long.byte 0xC4 0.--7. 1. " PRI_196 ,Interrupt 196 Priority" line.long 0xC8 "IPR50,Interrupt Priority Register" hexmask.long.byte 0xC8 24.--31. 1. " PRI_203 ,Interrupt 203 Priority" hexmask.long.byte 0xC8 16.--23. 1. " PRI_202 ,Interrupt 202 Priority" hexmask.long.byte 0xC8 8.--15. 1. " PRI_201 ,Interrupt 201 Priority" hexmask.long.byte 0xC8 0.--7. 1. " PRI_200 ,Interrupt 200 Priority" line.long 0xCC "IPR51,Interrupt Priority Register" hexmask.long.byte 0xCC 24.--31. 1. " PRI_207 ,Interrupt 207 Priority" hexmask.long.byte 0xCC 16.--23. 1. " PRI_206 ,Interrupt 206 Priority" hexmask.long.byte 0xCC 8.--15. 1. " PRI_205 ,Interrupt 205 Priority" hexmask.long.byte 0xCC 0.--7. 1. " PRI_204 ,Interrupt 204 Priority" line.long 0xD0 "IPR52,Interrupt Priority Register" hexmask.long.byte 0xD0 24.--31. 1. " PRI_211 ,Interrupt 211 Priority" hexmask.long.byte 0xD0 16.--23. 1. " PRI_210 ,Interrupt 210 Priority" hexmask.long.byte 0xD0 8.--15. 1. " PRI_209 ,Interrupt 209 Priority" hexmask.long.byte 0xD0 0.--7. 1. " PRI_208 ,Interrupt 208 Priority" line.long 0xD4 "IPR53,Interrupt Priority Register" hexmask.long.byte 0xD4 24.--31. 1. " PRI_215 ,Interrupt 215 Priority" hexmask.long.byte 0xD4 16.--23. 1. " PRI_214 ,Interrupt 214 Priority" hexmask.long.byte 0xD4 8.--15. 1. " PRI_213 ,Interrupt 213 Priority" hexmask.long.byte 0xD4 0.--7. 1. " PRI_212 ,Interrupt 212 Priority" line.long 0xD8 "IPR54,Interrupt Priority Register" hexmask.long.byte 0xD8 24.--31. 1. " PRI_219 ,Interrupt 219 Priority" hexmask.long.byte 0xD8 16.--23. 1. " PRI_218 ,Interrupt 218 Priority" hexmask.long.byte 0xD8 8.--15. 1. " PRI_217 ,Interrupt 217 Priority" hexmask.long.byte 0xD8 0.--7. 1. " PRI_216 ,Interrupt 216 Priority" line.long 0xDC "IPR55,Interrupt Priority Register" hexmask.long.byte 0xDC 24.--31. 1. " PRI_223 ,Interrupt 223 Priority" hexmask.long.byte 0xDC 16.--23. 1. " PRI_222 ,Interrupt 222 Priority" hexmask.long.byte 0xDC 8.--15. 1. " PRI_221 ,Interrupt 221 Priority" hexmask.long.byte 0xDC 0.--7. 1. " PRI_220 ,Interrupt 220 Priority" line.long 0xE0 "IPR56,Interrupt Priority Register" hexmask.long.byte 0xE0 24.--31. 1. " PRI_227 ,Interrupt 227 Priority" hexmask.long.byte 0xE0 16.--23. 1. " PRI_226 ,Interrupt 226 Priority" hexmask.long.byte 0xE0 8.--15. 1. " PRI_225 ,Interrupt 225 Priority" hexmask.long.byte 0xE0 0.--7. 1. " PRI_224 ,Interrupt 224 Priority" line.long 0xE4 "IPR57,Interrupt Priority Register" hexmask.long.byte 0xE4 24.--31. 1. " PRI_231 ,Interrupt 231 Priority" hexmask.long.byte 0xE4 16.--23. 1. " PRI_230 ,Interrupt 230 Priority" hexmask.long.byte 0xE4 8.--15. 1. " PRI_229 ,Interrupt 229 Priority" hexmask.long.byte 0xE4 0.--7. 1. " PRI_228 ,Interrupt 228 Priority" line.long 0xE8 "IPR58,Interrupt Priority Register" hexmask.long.byte 0xE8 24.--31. 1. " PRI_235 ,Interrupt 235 Priority" hexmask.long.byte 0xE8 16.--23. 1. " PRI_234 ,Interrupt 234 Priority" hexmask.long.byte 0xE8 8.--15. 1. " PRI_233 ,Interrupt 233 Priority" hexmask.long.byte 0xE8 0.--7. 1. " PRI_232 ,Interrupt 232 Priority" line.long 0xEC "IPR59,Interrupt Priority Register" hexmask.long.byte 0xEC 24.--31. 1. " PRI_239 ,Interrupt 239 Priority" hexmask.long.byte 0xEC 16.--23. 1. " PRI_238 ,Interrupt 238 Priority" hexmask.long.byte 0xEC 8.--15. 1. " PRI_237 ,Interrupt 237 Priority" hexmask.long.byte 0xEC 0.--7. 1. " PRI_236 ,Interrupt 236 Priority" else hgroup.long 0x400++0xEF hide.long 0x0 "IPR0,Interrupt Priority Register" hide.long 0x4 "IPR1,Interrupt Priority Register" hide.long 0x8 "IPR2,Interrupt Priority Register" hide.long 0xC "IPR3,Interrupt Priority Register" hide.long 0x10 "IPR4,Interrupt Priority Register" hide.long 0x14 "IPR5,Interrupt Priority Register" hide.long 0x18 "IPR6,Interrupt Priority Register" hide.long 0x1C "IPR7,Interrupt Priority Register" hide.long 0x20 "IPR8,Interrupt Priority Register" hide.long 0x24 "IPR9,Interrupt Priority Register" hide.long 0x28 "IPR10,Interrupt Priority Register" hide.long 0x2C "IPR11,Interrupt Priority Register" hide.long 0x30 "IPR12,Interrupt Priority Register" hide.long 0x34 "IPR13,Interrupt Priority Register" hide.long 0x38 "IPR14,Interrupt Priority Register" hide.long 0x3C "IPR15,Interrupt Priority Register" hide.long 0x40 "IPR16,Interrupt Priority Register" hide.long 0x44 "IPR17,Interrupt Priority Register" hide.long 0x48 "IPR18,Interrupt Priority Register" hide.long 0x4C "IPR19,Interrupt Priority Register" hide.long 0x50 "IPR20,Interrupt Priority Register" hide.long 0x54 "IPR21,Interrupt Priority Register" hide.long 0x58 "IPR22,Interrupt Priority Register" hide.long 0x5C "IPR23,Interrupt Priority Register" hide.long 0x60 "IPR24,Interrupt Priority Register" hide.long 0x64 "IPR25,Interrupt Priority Register" hide.long 0x68 "IPR26,Interrupt Priority Register" hide.long 0x6C "IPR27,Interrupt Priority Register" hide.long 0x70 "IPR28,Interrupt Priority Register" hide.long 0x74 "IPR29,Interrupt Priority Register" hide.long 0x78 "IPR30,Interrupt Priority Register" hide.long 0x7C "IPR31,Interrupt Priority Register" hide.long 0x80 "IPR32,Interrupt Priority Register" hide.long 0x84 "IPR33,Interrupt Priority Register" hide.long 0x88 "IPR34,Interrupt Priority Register" hide.long 0x8C "IPR35,Interrupt Priority Register" hide.long 0x90 "IPR36,Interrupt Priority Register" hide.long 0x94 "IPR37,Interrupt Priority Register" hide.long 0x98 "IPR38,Interrupt Priority Register" hide.long 0x9C "IPR39,Interrupt Priority Register" hide.long 0xA0 "IPR40,Interrupt Priority Register" hide.long 0xA4 "IPR41,Interrupt Priority Register" hide.long 0xA8 "IPR42,Interrupt Priority Register" hide.long 0xAC "IPR43,Interrupt Priority Register" hide.long 0xB0 "IPR44,Interrupt Priority Register" hide.long 0xB4 "IPR45,Interrupt Priority Register" hide.long 0xB8 "IPR46,Interrupt Priority Register" hide.long 0xBC "IPR47,Interrupt Priority Register" hide.long 0xC0 "IPR48,Interrupt Priority Register" hide.long 0xC4 "IPR49,Interrupt Priority Register" hide.long 0xC8 "IPR50,Interrupt Priority Register" hide.long 0xCC "IPR51,Interrupt Priority Register" hide.long 0xD0 "IPR52,Interrupt Priority Register" hide.long 0xD4 "IPR53,Interrupt Priority Register" hide.long 0xD8 "IPR54,Interrupt Priority Register" hide.long 0xDC "IPR55,Interrupt Priority Register" hide.long 0xE0 "IPR56,Interrupt Priority Register" hide.long 0xE4 "IPR57,Interrupt Priority Register" hide.long 0xE8 "IPR58,Interrupt Priority Register" hide.long 0xEC "IPR59,Interrupt Priority Register" endif tree.end width 0x0b else newline textline "COREDEBUG component base address not specified" newline endif tree.end sif CORENAME()=="CORTEXM4F" tree "Floating-point Unit (FPU)" sif COMPonent.AVAILABLE("COREDEBUG") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1)) width 8. group.long 0xF34++0x0B line.long 0x00 "FPCCR,Floating-Point Context Control Register" bitfld.long 0x00 31. " ASPEN ,Execution of a floating-point instruction sets the CONTROL.FPCA bit to 1" "Disabled,Enabled" bitfld.long 0x00 30. " LSPEN ,Enables lazy context save of FP state" "Disabled,Enabled" bitfld.long 0x00 8. " MONRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the DebugMonitor exception to pending" "Not able,Able" textline " " bitfld.long 0x00 6. " BFRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the BusFault exception to pending" "Not able,Able" bitfld.long 0x00 5. " MMRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the MemManage exception to pending" "Not able,Able" bitfld.long 0x00 4. " HFRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the HardFault exception to pending" "Not able,Able" textline " " bitfld.long 0x00 3. " THREAD ,Indicates the processor mode when it allocated the FP stack frame" "Handler,Thread" bitfld.long 0x00 1. " USER ,Indicates the privilege level of the software executing" "Privileged,Unprivileged" bitfld.long 0x00 0. " LSPACT ,Indicates whether Lazy preservation of the FP state is active" "Not active,Active" line.long 0x04 "FPCAR,Floating-Point Context Address Register" hexmask.long 0x04 3.--31. 0x8 " ADDRESS ,The location of the unpopulated floating-point register space allocated on an exception stack frame" line.long 0x08 "FPDSCR,Floating-Point Default Status Control Register" bitfld.long 0x08 26. " AHP ,Default value for FPSCR.AHP" "IEEE 754-2008,Alternative" bitfld.long 0x08 25. " DN ,Default value for FPSCR.DN" "NaN operands,Any operation" bitfld.long 0x08 24. " FZ ,Default value for FPSCR.FZ" "No Flush mode,Flush mode" textline " " bitfld.long 0x08 22.--23. " RMODE ,Default value for FPSCR.RMode" "Round to Nearest,Round towards Plus Infinity,Round towards Minus Infinity,Round towards Zero" rgroup.long 0xF40++0x07 line.long 0x00 "MVFR0,Media and FP Feature Register 0" bitfld.long 0x00 28.--31. " FPRNDMOD ,Indicates the rounding modes supported by the FP floating-point hardware" ",All supported,?..." bitfld.long 0x00 24.--27. " SRTERR ,Indicates the hardware support for FP short vectors" "Not supported,?..." bitfld.long 0x00 20.--23. " SQRROOT ,Indicates the hardware support for FP square root operations" ",Supported,?..." textline " " bitfld.long 0x00 16.--19. " DIV ,Indicates the hardware support for FP divide operations" ",Supported,?..." bitfld.long 0x00 12.--15. " FPEXTRP ,Indicates whether the FP hardware implementation supports exception trapping" "Not supported,?..." bitfld.long 0x00 8.--11. " DBLPREC ,Indicates the hardware support for FP double_precision operations" "Not supported,,Supported,?..." textline " " bitfld.long 0x00 4.--7. " SNGLPREC ,Indicates the hardware support for FP single-precision operations" ",,Supported,?..." bitfld.long 0x00 0.--3. " A_SIMD ,Indicates the size of the FP register bank" ",Supported-16x64-bit,?..." line.long 0x04 "MVFR1,Media and FP Feature Register 1" bitfld.long 0x04 28.--31. " FP_FUSED_MAC ,Indicates whether the FP supports fused multiply accumulate operations" ",Supported,?..." bitfld.long 0x04 24.--27. " FP_HPFP ,Indicates whether the FP supports half-precision and double-precision floating-point conversion instructions" ",Half-single,Half-single and half-double,?..." textline " " bitfld.long 0x04 4.--7. " D_NAN ,Indicates whether the FP hardware implementation supports only the Default NaN mode" ",NaN propagation,?..." bitfld.long 0x04 0.--3. " FTZ_MODE ,Indicates whether the FP hardware implementation supports only the Flush-to-Zero mode of operation" ",Full denorm. num. arit.,?..." width 0xB else newline textline "COREDEBUG component base address not specified" newline endif tree.end endif tree "Debug" tree "Core Debug" sif COMPonent.AVAILABLE("COREDEBUG") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1)) width 7. group.long 0xD30++0x03 line.long 0x00 "DFSR,Debug Fault Status Register" eventfld.long 0x00 4. " EXTERNAL ,Indicates a debug event generated because of the assertion of an external debug request" "Not generated,Generated" eventfld.long 0x00 3. " VCATCH ,Indicates triggering of a Vector catch" "Not triggered,Triggered" eventfld.long 0x00 2. " DWTTRAP ,Indicates a debug event generated by the DWT" "Not generated,Generated" newline eventfld.long 0x00 1. " BKPT ,Indicates a debug event generated by BKPT instruction execution or a breakpoint match in FPB" "Not generated,Generated" eventfld.long 0x00 0. " HALTED ,Indicates a debug event generated by either a C_HALT or C_STEP request, triggered by a write to the DHCSR or a step request triggered by setting DEMCR.MON_STEP to 1" "Not generated,Generated" newline hgroup.long 0xDF0++0x03 hide.long 0x00 "DHCSR,Debug Halting Control and Status Register" in newline wgroup.long 0xDF4++0x03 line.long 0x00 "DCRSR,Debug Core Register Selector Register" bitfld.long 0x00 16. " REGWNR ,Register Read/Write" "Read,Write" hexmask.long.byte 0x00 0.--6. 1. " REGSEL ,Specifies the ARM core register or special-purpose register or Floating-point extension register" group.long 0xDF8++0x03 line.long 0x00 "DCRDR,Debug Core Register Data Register" if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDFC))&0x10000)==0x10000) group.long 0xDFC++0x03 line.long 0x00 "DEMCR,Debug Exception and Monitor Control Register" bitfld.long 0x00 24. " TRCENA ,Global enable for all DWT and ITM features" "Disabled,Enabled" bitfld.long 0x00 19. " MON_REQ ,DebugMonitor semaphore bit" "0,1" bitfld.long 0x00 18. " MON_STEP ,Setting this bit to 1 makes the step request pending" "No step,Step" newline bitfld.long 0x00 17. " MON_PEND ,Sets or clears the pending state of the DebugMonitor exception" "Not pending,Pending" bitfld.long 0x00 16. " MON_EN ,Enable the DebugMonitor exception" "Disabled,Enabled" bitfld.long 0x00 10. " VC_HARDERR ,Enable halting debug trap on a HardFault exception" "Disabled,Enabled" newline bitfld.long 0x00 9. " VC_INTERR ,Enable halting debug trap" "Disabled,Enabled" bitfld.long 0x00 8. " VC_BUSERR ,Enable halting debug trap on a BusFault exception" "Disabled,Enabled" bitfld.long 0x00 7. " VC_STATERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled" newline bitfld.long 0x00 6. " VC_CHKERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled" bitfld.long 0x00 5. " VC_NOCPERR ,Enable halting debug trap on a UsageFault caused by an access to a Coprocessor" "Disabled,Enabled" bitfld.long 0x00 4. " VC_MMERR ,Enable halting debug trap on a MemManage exception" "Disabled,Enabled" newline bitfld.long 0x00 0. " VC_CORERESET ,Enable Reset Vector Catch" "Disabled,Enabled" else group.long 0xDFC++0x03 line.long 0x00 "DEMCR,Debug Exception and Monitor Control Register" bitfld.long 0x00 24. " TRCENA ,Global enable for all DWT and ITM features" "Disabled,Enabled" bitfld.long 0x00 19. " MON_REQ ,DebugMonitor semaphore bit" "0,1" newline bitfld.long 0x00 17. " MON_PEND ,Sets or clears the pending state of the DebugMonitor exception" "Not pending,Pending" bitfld.long 0x00 16. " MON_EN ,Enable the DebugMonitor exception" "Disabled,Enabled" bitfld.long 0x00 10. " VC_HARDERR ,Enable halting debug trap on a HardFault exception" "Disabled,Enabled" newline bitfld.long 0x00 9. " VC_INTERR ,Enable halting debug trap" "Disabled,Enabled" bitfld.long 0x00 8. " VC_BUSERR ,Enable halting debug trap on a BusFault exception" "Disabled,Enabled" bitfld.long 0x00 7. " VC_STATERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled" newline bitfld.long 0x00 6. " VC_CHKERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled" bitfld.long 0x00 5. " VC_NOCPERR ,Enable halting debug trap on a UsageFault caused by an access to a Coprocessor" "Disabled,Enabled" bitfld.long 0x00 4. " VC_MMERR ,Enable halting debug trap on a MemManage exception" "Disabled,Enabled" newline bitfld.long 0x00 0. " VC_CORERESET ,Enable Reset Vector Catch" "Disabled,Enabled" endif width 0x0B else newline textline "COREDEBUG component base address not specified" newline endif tree.end tree "Flash Patch and Breakpoint Unit (FPB)" sif COMPonent.AVAILABLE("FPB") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1)) width 10. group.long 0x00++0x07 line.long 0x00 "FP_CTRL,Flash Patch Control Register" bitfld.long 0x00 28.--31. " REV ,Flash Patch Breakpoint architecture revision" "Version 1,Version 2,?..." rbitfld.long 0x00 4.--7. 12.--14. " NUM_CODE ,The number of instruction address comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127" bitfld.long 0x00 1. " KEY ,Key Field" "Low,High" bitfld.long 0x00 0. " ENABLE ,Flash Patch Unit Enable" "Disabled,Enabled" textline "" line.long 0x04 "FP_REMAP,Flash Patch Remap Register" bitfld.long 0x04 29. " RMPSPT ,Indicates whether the FPB unit supports flash patch remap" "Not supported,SRAM region" hexmask.long.tbyte 0x04 5.--28. 0x20 " REMAP ,Remap Base Address Field" if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00) group.long 0x8++0x03 line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0" bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both" hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address" bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000) if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x8))&0x01)==0x00) group.long 0x8++0x03 line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" else group.long 0x8++0x03 line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0" hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" endif endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00) group.long 0xC++0x03 line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1" bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both" hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address" bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000) if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0xC))&0x01)==0x00) group.long 0xC++0x03 line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" else group.long 0xC++0x03 line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1" hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" endif endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00) group.long 0x10++0x03 line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2" bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both" hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address" bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000) if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x10))&0x01)==0x00) group.long 0x10++0x03 line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" else group.long 0x10++0x03 line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2" hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" endif endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00) group.long 0x14++0x03 line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3" bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both" hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address" bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000) if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x14))&0x01)==0x00) group.long 0x14++0x03 line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" else group.long 0x14++0x03 line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3" hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" endif endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00) group.long 0x18++0x03 line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4" bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both" hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address" bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000) if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x18))&0x01)==0x00) group.long 0x18++0x03 line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" else group.long 0x18++0x03 line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4" hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" endif endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00) group.long 0x1C++0x03 line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5" bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both" hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address" bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000) if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x1C))&0x01)==0x00) group.long 0x1C++0x03 line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" else group.long 0x1C++0x03 line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5" hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" endif endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00) group.long 0x20++0x03 line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6" bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both" hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address" bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000) if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x20))&0x01)==0x00) group.long 0x20++0x03 line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" else group.long 0x20++0x03 line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6" hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" endif endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00) group.long 0x24++0x03 line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7" bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both" hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address" bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000) if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x24))&0x01)==0x00) group.long 0x24++0x03 line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" else group.long 0x24++0x03 line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7" hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" endif endif width 6. tree "CoreSight Identification Registers" rgroup.long 0xFE0++0x0F line.long 0x00 "PID0,Peripheral ID0" hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]" line.long 0x04 "PID1,Peripheral ID1" hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]" hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]" line.long 0x08 "PID2,Peripheral ID2" hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision" bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC" hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]" line.long 0x0c "PID3,Peripheral ID3" hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field" hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block" rgroup.long 0xFD0++0x03 line.long 0x00 "PID4,Peripheral Identification Register 4" hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count" hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code" rgroup.long 0xFF0++0x0F line.long 0x00 "CID0,Component ID0 (Preamble)" line.long 0x04 "CID1,Component ID1" hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class" hexmask.long.byte 0x04 0.--3. 1. " Preamble ,Preamble" line.long 0x08 "CID2,Component ID2" line.long 0x0c "CID3,Component ID3" tree.end width 0xB else newline textline "FPB component base address not specified" newline endif tree.end tree "Data Watchpoint and Trace Unit (DWT)" sif COMPonent.AVAILABLE("DWT") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1)) width 15. group.long 0x00++0x1B line.long 0x00 "DWT_CTRL,Control Register" rbitfld.long 0x00 28.--31. " NUMCOMP ,Number of comparators implemented" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. " NOTRCPKT ,Shows whether the implementation supports trace sampling and exception tracing" "Supported,Not supported" rbitfld.long 0x00 26. " NOEXTTRIG ,Shows whether the implementation includes external match signals" "Supported,Not supported" textline " " rbitfld.long 0x00 25. " NOCYCCNT ,Shows whether the implementation supports a cycle counter" "Supported,Not supported" rbitfld.long 0x00 24. " NOPRFCNT ,Shows whether the implementation supports the profiling counters" "Supported,Not supported" bitfld.long 0x00 22. " CYCEVTENA ,Enables POSTCNT underflow Event counter packets generation" "Disabled,Enabled" textline " " bitfld.long 0x00 21. " FOLDEVTENA ,Enables generation of the Folded-instruction counter overflow event" "Disabled,Enabled" bitfld.long 0x00 20. " LSUEVTENA ,Enables generation of the LSU counter overflow event" "Disabled,Enabled" bitfld.long 0x00 19. " SLEEPEVTENA ,Enables generation of the Sleep counter overflow event" "Disabled,Enabled" textline " " bitfld.long 0x00 18. " EXCEVTENA ,Enables generation of the Exception overhead counter overflow event" "Disabled,Enabled" bitfld.long 0x00 17. " CPIEVTENA ,Enables generation of the CPI counter overflow event" "Disabled,Enabled" bitfld.long 0x00 16. " EXCTRCENA ,Enables generation of exception trace" "Disabled,Enabled" textline " " bitfld.long 0x00 12. " PCSAMPLEENA ,Enables use of POSTCNT counter as a timer for Periodic PC sample packet generation" "Disabled,Enabled" bitfld.long 0x00 10.--11. " SYNCTAP ,Selects the position of the synchronization packet counter tap on the CYCCNT counter" "Disabled,CYCCNT[24],CYCCNT[26],CYCCNT[28]" bitfld.long 0x00 9. " CYCTAP ,Selects the position of the POSTCNT tap on the CYCCNT counter" "CYCCNT[6],CYCCNT[10]" textline " " bitfld.long 0x00 5.--8. " POSTINIT ,Initial value for the POSTCNT counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 1.--4. " POSTPRESET ,Reload value for the POSTCNT counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0. " CYCCNTENA ,Enables CYCCNT" "Disabled,Enabled" line.long 0x04 "DWT_CYCCNT,Cycle Count Register" line.long 0x08 "DWT_CPICNT,CPI Count Register" hexmask.long.byte 0x08 0.--7. 1. " CPICNT ,The base CPI counter" line.long 0x0c "DWT_EXCCNT,Exception Overhead Count Register" hexmask.long.byte 0x0c 0.--7. 1. " EXCCNT ,The exception overhead counter" line.long 0x10 "DWT_SLEEPCNT,Sleep Count Register" hexmask.long.byte 0x10 0.--7. 1. " SLEEPCNT ,Sleep Counter" line.long 0x14 "DWT_LSUCNT,LSU Count Register" hexmask.long.byte 0x14 0.--7. 1. " LSUCNT ,Load-store counter" line.long 0x18 "DWT_FOLDCNT,Folded-instruction Count Register" hexmask.long.byte 0x18 0.--7. 1. " FOLDCNT ,Folded-instruction counter" rgroup.long 0x1C++0x03 line.long 0x00 "DWT_PCSR,Program Counter Sample register" textline " " group.long 0x20++0x07 line.long 0x00 "DWT_COMP0,DWT Comparator Register 0" line.long 0x04 "DWT_MASK0,DWT Mask Registers 0" bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x28))&0x1A0)==0x20) group.long 0x28++0x03 line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled" bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE" elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x28))&0x1A0)==0x00) group.long 0x28++0x03 line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled" bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE" elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x28))&0x180)==0x80) group.long 0x28++0x03 line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled" bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet,UNPREDICTABLE,UNPREDICTABLE,Generate watchpoint debug event,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,CMPMATCH[N] event,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE" else group.long 0x28++0x03 line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled" bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE" endif group.long (0x30)++0x07 line.long 0x00 "DWT_COMP1,DWT Comparator Register 1" line.long 0x04 "DWT_MASK1,DWT Mask Registers 1" bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08))&0x120)==0x20) group.long (0x30+0x08)++0x03 line.long 0x00 "DWT_FUNCTION1,DWT Function Registers 1" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE" elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08))&0x120)==0x00) group.long (0x30+0x08)++0x03 line.long 0x00 "DWT_FUNCTION1,DWT Function Registers 1" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE" else group.long (0x30+0x08)++0x03 line.long 0x00 "DWT_FUNCTION1,DWT Function Registers 1" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " EMITRANGE ,Enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE" endif group.long (0x40)++0x07 line.long 0x00 "DWT_COMP2,DWT Comparator Register 2" line.long 0x04 "DWT_MASK2,DWT Mask Registers 2" bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08))&0x120)==0x20) group.long (0x40+0x08)++0x03 line.long 0x00 "DWT_FUNCTION2,DWT Function Registers 2" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE" elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08))&0x120)==0x00) group.long (0x40+0x08)++0x03 line.long 0x00 "DWT_FUNCTION2,DWT Function Registers 2" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE" else group.long (0x40+0x08)++0x03 line.long 0x00 "DWT_FUNCTION2,DWT Function Registers 2" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " EMITRANGE ,Enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE" endif group.long (0x50)++0x07 line.long 0x00 "DWT_COMP3,DWT Comparator Register 3" line.long 0x04 "DWT_MASK3,DWT Mask Registers 3" bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08))&0x120)==0x20) group.long (0x50+0x08)++0x03 line.long 0x00 "DWT_FUNCTION3,DWT Function Registers 3" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE" elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08))&0x120)==0x00) group.long (0x50+0x08)++0x03 line.long 0x00 "DWT_FUNCTION3,DWT Function Registers 3" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE" else group.long (0x50+0x08)++0x03 line.long 0x00 "DWT_FUNCTION3,DWT Function Registers 3" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " EMITRANGE ,Enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE" endif width 6. tree "CoreSight Identification Registers" rgroup.long 0xFE0++0x0F line.long 0x00 "PID0,Peripheral ID0" hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]" line.long 0x04 "PID1,Peripheral ID1" hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]" hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]" line.long 0x08 "PID2,Peripheral ID2" hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision" bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC" hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]" line.long 0x0c "PID3,Peripheral ID3" hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field" hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block" rgroup.long 0xFD0++0x03 line.long 0x00 "PID4,Peripheral Identification Register 4" hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count" hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code" rgroup.long 0xFF0++0x0F line.long 0x00 "CID0,Component ID0 (Preamble)" line.long 0x04 "CID1,Component ID1" hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class" hexmask.long.byte 0x04 0.--3. 1. " Preamble ,Preamble" line.long 0x08 "CID2,Component ID2" line.long 0x0c "CID3,Component ID3" tree.end width 0x0B else newline textline "DWT component base address not specified" newline endif tree.end tree.end AUTOINDENT.POP tree.end endif sif (CORENAME()=="CORTEXA7MPCORE") tree "Core Registers (Cortex-A7MPCore)" AUTOINDENT.PUSH AUTOINDENT.OFF ; -------------------------------------------------------------------------------- ; Identification registers ; -------------------------------------------------------------------------------- width 10. tree "ID Registers" group.long c15:0x0++0x0 line.long 0x0 "MIDR,Main ID Register" hexmask.long.byte 0x0 24.--31. 0x1 " IMPL ,Implementer code" bitfld.long 0x0 20.--23. " VAR ,Variant" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 16.--19. " ARCH , Architecture" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,ARMv7" textline " " hexmask.long.word 0x0 4.--15. 1. " PART ,Primary Part Number" bitfld.long 0x0 0.--3. " REV ,Revision Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" if (corename()=="CORTEXA15"||corename()=="CORTEXA15MPCORE") rgroup.long c15:0x100++0x0 line.long 0x0 "CTR,Cache Type Register" bitfld.long 0x0 29.--31. " FORMAT ,Format" "Reserved,Reserved,Reserved,Reserved,ARMv7,?..." bitfld.long 0x0 24.--27. " CWG ,Cache writeback granule size" "Reserved,Reserved,Reserved,Reserved,16 words,?..." bitfld.long 0x0 20.--23. " ERG ,Exclusives reservation granule size" "Reserved,Reserved,Reserved,Reserved,16 words,?..." textline " " bitfld.long 0x0 16.--19. " DMINLINE ,Smallest data cache line size" "Reserved,Reserved,Reserved,Reserved,16 words,?..." bitfld.long 0x0 14.--15. " L1POLICY ,L1 Instruction cache policy" "Reserved,Reserved,Reserved,Physical" bitfld.long 0x0 0.--3. " IMINLINE ,I-Cache Minimum Line Size" "Reserved,Reserved,Reserved,8 words,16 words,?..." elif (corename()=="CORTEXA7"||corename()=="CORTEXA7MPCORE"||corename()=="CORTEXA17"||corename()=="CORTEXA17MPCORE") rgroup.long c15:0x100++0x0 line.long 0x0 "CTR,Cache Type Register" bitfld.long 0x0 29.--31. " FORMAT ,Format" "Reserved,Reserved,Reserved,Reserved,ARMv7,?..." bitfld.long 0x0 24.--27. " CWG ,Cache writeback granule size" "Reserved,Reserved,Reserved,Reserved,16 words,?..." bitfld.long 0x0 20.--23. " ERG ,Exclusives reservation granule size" "Reserved,Reserved,Reserved,Reserved,16 words,?..." textline " " bitfld.long 0x0 16.--19. " DMINLINE ,Smallest data cache line size" "Reserved,Reserved,Reserved,Reserved,16 words,?..." bitfld.long 0x0 14.--15. " L1POLICY ,L1 Instruction cache policy" "Reserved,Reserved,VIPT,?..." bitfld.long 0x0 0.--3. " IMINLINE ,I-Cache Minimum Line Size" "Reserved,Reserved,Reserved,8 words,?..." endif rgroup.long c15:0x300++0x0 line.long 0x0 "TLBTR,TLB Type Register" bitfld.long 0x0 0. " NU ,Unified or Separate TLBs" "Unified,?..." rgroup.long c15:0x500++0x0 line.long 0x0 "MPIDR,Multiprocessor Affinity Register" bitfld.long 0x00 31. " MPERF ,Multiprocessing Extensions register format" "Not supported,Supported" bitfld.long 0x00 30. " U ,Processor is part of a multiprocessor or uniprocessor system" "Multiprocessor,Uniprocessor" bitfld.long 0x00 24. " MT ,Lowest level of affinity consist of logical processors" "Not implemented,Implemented" textline " " bitfld.long 0x00 8.--11. " CLUSTERID ,Value read in CLUSTERID configuration pins" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--1. " CPUID ,Value depends on the number of configured CPUs" "1,2,3,4" rgroup.long c15:0x400++0x0 line.long 0x0 "MIDR2,Main ID Register" hexmask.long.byte 0x0 24.--31. 0x1 " IMPL ,Implementer code" bitfld.long 0x0 20.--23. " VAR ,Variant" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 16.--19. " ARCH , Architecture" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,ARMv7" textline " " hexmask.long.word 0x0 4.--15. 1. " PART ,Primary Part Number" bitfld.long 0x0 0.--3. " REV ,Revision Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long c15:0x600++0x0 line.long 0x0 "REVIDR,Revision ID Register" rgroup.long c15:0x700++0x0 line.long 0x0 "MIDR3,Main ID Register" hexmask.long.byte 0x0 24.--31. 0x1 " IMPL ,Implementer code" bitfld.long 0x0 20.--23. " VAR ,Variant" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 16.--19. " ARCH , Architecture" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,ARMv7" textline " " hexmask.long.word 0x0 4.--15. 1. " PART ,Primary Part Number" bitfld.long 0x0 0.--3. " REV ,Revision Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" if (corename()=="CORTEXA15"||corename()=="CORTEXA15MPCORE") rgroup.long c15:0x0410++0x00 line.long 0x00 "ID_MMFR0,Memory Model Feature Register 0" bitfld.long 0x00 28.--31. " IS ,Indicates innermost shareability domain implemented" "Reserved,Implemented,?..." bitfld.long 0x00 24.--27. " FCSE ,Fast Context Switch Memory Mappings Support" "Not supported,?..." bitfld.long 0x00 20.--23. " AR ,Auxiliary Register Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 16.--19. " TCM ,TCM and Associated DMA Support" "Not supported,?..." bitfld.long 0x00 12.--15. " SL ,Shareability levels" "Reserved,Implemented 2 levels,?..." bitfld.long 0x00 8.--11. " OSS ,Outer Shareable Support" "Not supported,?..." textline " " bitfld.long 0x00 4.--7. " PMSA ,Physical Memory System Architecture (PMSA) Support" "Not supported,?..." bitfld.long 0x00 0.--3. " VMSA ,Virtual Memory System Architecture (VMSA) Support" "Reserved,Reserved,Reserved,Supported,PXN,64-bit,?..." elif (corename()=="CORTEXA7"||corename()=="CORTEXA7MPCORE"||corename()=="CORTEXA17"||corename()=="CORTEXA17MPCORE") rgroup.long c15:0x0410++0x00 line.long 0x00 "ID_MMFR0,Memory Model Feature Register 0" bitfld.long 0x00 28.--31. " IS ,Indicates innermost shareability domain implemented" "Reserved,Implemented,?..." bitfld.long 0x00 24.--27. " FCSE ,Fast Context Switch Memory Mappings Support" "Not supported,?..." bitfld.long 0x00 20.--23. " AR ,Auxiliary Register Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 16.--19. " TCM ,TCM and Associated DMA Support" "Not supported,?..." bitfld.long 0x00 12.--15. " SL ,Shareability levels" "Reserved,Implemented 2 levels,?..." bitfld.long 0x00 8.--11. " OSS ,Outer Shareable Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 4.--7. " PMSA ,Physical Memory System Architecture (PMSA) Support" "Not supported,?..." bitfld.long 0x00 0.--3. " VMSA ,Virtual Memory System Architecture (VMSA) Support" "Reserved,Reserved,Reserved,Reserved,Reserved,Supported,?..." endif if (corename()=="CORTEXA15"||corename()=="CORTEXA15MPCORE") rgroup.long c15:0x0510++0x00 line.long 0x00 "ID_MMFR1,Memory Model Feature Register 1" bitfld.long 0x00 28.--31. " BTB ,Branch Predictor" "Reserved,Reserved,Required,?..." bitfld.long 0x00 24.--27. " L1TCO ,Test and Clean Operations on Data Cache/Harvard/Unified Architecture Support" "Not supported,?..." bitfld.long 0x00 20.--23. " L1UCMO ,L1 Cache/All Maintenance Operations/Unified Architecture Support" "Not supported,?..." textline " " bitfld.long 0x00 16.--19. " L1HCMO ,L1 Cache/All Maintenance Operations/Harvard Architecture Support" "Not supported,?..." bitfld.long 0x00 12.--15. " L1UCLMOSW ,L1 Cache Line Maintenance Operations by Set and Way/Unified Architecture Support" "Not supported,?..." bitfld.long 0x00 8.--11. " L1HCLMOSW ,L1 Cache Line Maintenance Operations by Set and Way/Harvard Architecture Support" "Not supported,?..." textline " " bitfld.long 0x00 4.--7. " L1UCLMOMVA ,L1 Cache Line Maintenance Operations by VA/Unified Architecture Support" "Not supported,?..." bitfld.long 0x00 0.--3. " L1HCLMOMVA ,L1 Cache Line Maintenance Operations by VA/Harvard Architecture" "Not supported,?..." elif (corename()=="CORTEXA7"||corename()=="CORTEXA7MPCORE"||corename()=="CORTEXA17"||corename()=="CORTEXA17MPCORE") rgroup.long c15:0x0510++0x00 line.long 0x00 "ID_MMFR1,Memory Model Feature Register 1" bitfld.long 0x00 28.--31. " BTB ,Branch Predictor" "Reserved,Reserved,Reserved,Reserved,Required,?..." bitfld.long 0x00 24.--27. " L1TCO ,Test and Clean Operations on Data Cache/Harvard/Unified Architecture Support" "Not supported,?..." bitfld.long 0x00 20.--23. " L1UCMO ,L1 Cache/All Maintenance Operations/Unified Architecture Support" "Not supported,?..." textline " " bitfld.long 0x00 16.--19. " L1HCMO ,L1 Cache/All Maintenance Operations/Harvard Architecture Support" "Not supported,?..." bitfld.long 0x00 12.--15. " L1UCLMOSW ,L1 Cache Line Maintenance Operations by Set and Way/Unified Architecture Support" "Not supported,?..." bitfld.long 0x00 8.--11. " L1HCLMOSW ,L1 Cache Line Maintenance Operations by Set and Way/Harvard Architecture Support" "Not supported,?..." textline " " bitfld.long 0x00 4.--7. " L1UCLMOMVA ,L1 Cache Line Maintenance Operations by VA/Unified Architecture Support" "Not supported,?..." bitfld.long 0x00 0.--3. " L1HCLMOMVA ,L1 Cache Line Maintenance Operations by VA/Harvard Architecture" "Not supported,?..." endif rgroup.long c15:0x0610++0x00 line.long 0x00 "ID_MMFR2,Memory Model Feature Register 2" bitfld.long 0x00 28.--31. " HAF ,Hardware Access Flag Support" "Not supported,?..." bitfld.long 0x00 24.--27. " WFI ,Wait for Interrupt Stalling Support" "Reserved,Supported,?..." bitfld.long 0x00 20.--23. " MBF ,Memory Barrier Operations Support" "Reserved,Reserved,Supported,?..." textline " " bitfld.long 0x00 16.--19. " UTLBMO ,TLB Maintenance Operations/Unified Architecture Support" "Reserved,Reserved,Reserved,Reserved,Supported,?..." bitfld.long 0x00 12.--15. " HTLBMO ,TLB Maintenance Operations/Harvard Architecture Support" "Not supported,?..." bitfld.long 0x00 8.--11. " HL1CMRO ,Cache Maintenance Range Operations/Harvard Architecture Support" "Not supported,?..." textline " " bitfld.long 0x00 4.--7. " HL1BPCRO ,Background Prefetch Cache Range Operations/Harvard Architecture Support" "Not supported,?..." bitfld.long 0x00 0.--3. " HL1FPCRO ,Foreground Prefetch Cache Range Operations/Harvard Architecture Support" "Not supported,?..." rgroup.long c15:0x0710++0x00 line.long 0x00 "ID_MMFR3,Memory Model Feature Register 3" bitfld.long 0x00 28.--31. " SS ,Supersection support" "Supported,?..." bitfld.long 0x00 24.--27. " PMS ,Physical memory size supported by processor caches" "Reserved,Reserved,40-bit,?..." bitfld.long 0x00 20.--23. " CW ,Coherent walk" "Reserved,Supported,?..." textline " " bitfld.long 0x00 12.--15. " MB ,Maintenance broadcast Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 8.--11. " BPM ,Invalidate Branch predictor Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 4.--7. " HCMOSW ,Invalidate Cache by Set and Way/Clean by Set and Way/Invalidate and Clean by Set and Way Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 0.--3. " HCMOMVA ,Invalidate Cache MVA Support" "Reserved,Supported,?..." if (corename()=="CORTEXA15"||corename()=="CORTEXA15MPCORE"||corename()=="CORTEXA17"||corename()=="CORTEXA17MPCORE") rgroup.long c15:0x0020++0x00 line.long 0x00 "ID_ISAR0,Instruction Set Attribute Register 0" bitfld.long 0x00 24.--27. " DIVI ,Divide Instructions Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 20.--23. " DEBI ,Debug Instructions Support" "Reserved,BKPT,?..." bitfld.long 0x00 16.--19. " CI ,Coprocessor Instructions Support" "Not supported,?..." textline " " bitfld.long 0x00 12.--15. " CBI ,Combined Compare and Branch Instructions Support" "Reserved,CBNZ/CBZ,?..." bitfld.long 0x00 8.--11. " BI ,Bitfield Instructions Support" "Reserved,BFC/BFI/SBFX/UBFX,?..." bitfld.long 0x00 4.--7. " BCI ,Bit Counting Instructions Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 0.--3. " SI ,Swap Instructions Support" "Not supported,?..." elif (corename()=="CORTEXA7"||corename()=="CORTEXA7MPCORE") rgroup.long c15:0x0020++0x00 line.long 0x00 "ID_ISAR0,Instruction Set Attribute Register 0" bitfld.long 0x00 24.--27. " DIVI ,Divide Instructions Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 20.--23. " DEBI ,Debug Instructions Support" "Reserved,BKPT,?..." bitfld.long 0x00 16.--19. " CI ,Coprocessor Instructions Support" "Not supported,?..." textline " " bitfld.long 0x00 12.--15. " CBI ,Combined Compare and Branch Instructions Support" "Reserved,CBNZ/CBZ,?..." bitfld.long 0x00 8.--11. " BI ,Bitfield Instructions Support" "Reserved,BFC/BFI/SBFX/UBFX,?..." bitfld.long 0x00 4.--7. " BCI ,Bit Counting Instructions Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 0.--3. " SI ,Swap Instructions Support" "Supported,?..." endif rgroup.long c15:0x0120++0x00 line.long 0x00 "ID_ISAR1,Instruction Set Attribute Register 1" bitfld.long 0x00 28.--31. " JI ,Jazelle Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 24.--27. " INTI ,Interwork Instructions Support" "Reserved,Reserved,Reserved,Supported,?..." bitfld.long 0x00 20.--23. " IMMI ,Immediate Instructions Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 16.--19. " ITEI ,If Then Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 12.--15. " EXTI ,Extend Instructions Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 8.--11. " EARI ,Exception A and R Instructions Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 4.--7. " EXIN ,Exception in ARM Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 0.--3. " ENDI ,Endian Instructions Support" "Reserved,Supported,?..." rgroup.long c15:0x0220++0x00 line.long 0x00 "ID_ISAR2,Instruction Set Attribute Register 2" bitfld.long 0x00 28.--31. " RI ,Reversal Instructions Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 24.--27. " PSRI ,PSR Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 20.--23. " UMI ,Advanced Unsigned Multiply Instructions Support" "Reserved,Reserved,Supported,?..." textline " " bitfld.long 0x00 16.--19. " SMI ,Advanced Signed Multiply Instructions Support" "Reserved,Reserved,Reserved,Supported,?..." bitfld.long 0x00 12.--15. " MI ,Multiply Instructions Support" "Reserved,Reserved,MUL/MLA/MLS,?..." bitfld.long 0x00 8.--11. " II ,Multi-Access Interruptible Instructions Support" "Not supported,?..." textline " " bitfld.long 0x00 4.--7. " MHI ,Memory Hint Instructions Support" "Reserved,Reserved,Reserved,Reserved,PLD/PLI/PLWD,?..." bitfld.long 0x00 0.--3. " LSI ,Load and Store Instructions Support" "Reserved,LDRD/STRD,?..." rgroup.long c15:0x0320++0x00 line.long 0x00 "ID_ISAR3,Instruction Set Attribute Register 3" bitfld.long 0x00 28.--31. " TEEEI ,Thumb-EE Extensions Support" "Reserved,Supported,?..." bitfld.long 0x00 24.--27. " NOPI ,True NOP Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 20.--23. " TCI ,Thumb Copy Instructions Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 16.--19. " TBI ,Table Branch Instructions Support" "Reserved,TBB/TBH,?..." bitfld.long 0x00 12.--15. " SPI ,Synchronization Primitive Instructions Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 8.--11. " SVCI ,SVC Instructions Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 4.--7. " SIMDI ,Single Instruction Multiple Data (SIMD) Instructions Support" "Reserved,Reserved,Reserved,Supported,?..." bitfld.long 0x00 0.--3. " SI ,Saturate Instructions Support" "Reserved,Supported,?..." rgroup.long c15:0x0420++0x00 line.long 0x00 "ID_ISAR4,Instruction Set Attribute Register 4" bitfld.long 0x00 28.--31. " SWP_FRAC ,Memory System Locking Support" "Reserved,Supported,?..." bitfld.long 0x00 24.--27. " PSR_M_I ,PSR_M Instructions Support" "Not supported,?..." bitfld.long 0x00 20.--23. " SPRI ,Synchronization Primitive instructions" "Supported,?..." textline " " bitfld.long 0x00 16.--19. " BI ,Barrier Instructions Support" "Reserved,DMB/DSB/ISB,?..." bitfld.long 0x00 12.--15. " SMCI ,SMC Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 8.--11. " WBI ,Write-Back Instructions Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 4.--7. " WSI ,With-Shift Instructions Support" "Reserved,Reserved,Reserved,Reserved,Supported,?..." bitfld.long 0x00 0.--3. " UI ,Unprivileged Instructions Support" "Reserved,Reserved,Supported,?..." rgroup.long c15:0x0010++0x00 line.long 0x00 "ID_PFR0,Processor Feature Register 0" bitfld.long 0x00 12.--15. " STATE3 ,Thumb Execution Environment (Thumb-EE) Support" "Reserved,Supported,?..." bitfld.long 0x00 8.--11. " STATE2 ,Support for Jazelle extension" "Not supported,?..." bitfld.long 0x00 4.--7. " STATE1 ,Thumb Encoding Supported by the Processor Type" "Reserved,Reserved,Reserved,Supported,?..." textline " " bitfld.long 0x00 0.--3. " STATE0 ,ARM Instruction Set Support" "Reserved,Supported,?..." rgroup.long c15:0x0110++0x00 line.long 0x00 "ID_PFR1,Processor Feature Register 1" bitfld.long 0x00 16.--19. " GT ,Generic Timer Support" "Reserved,Supported,?..." bitfld.long 0x00 12.--15. " VE ,Virtualization Extensions Support" "Reserved,Supported,?..." bitfld.long 0x00 8.--11. " MPM ,Microcontroller Programmer's Model Support" "Not supported,?..." textline " " bitfld.long 0x00 4.--7. " SE ,Security Extensions Architecture v1 Support" "Reserved,Supported,?..." bitfld.long 0x00 0.--3. " PM ,Standard ARMv4 Programmer's Model Support" "Reserved,Supported,?..." rgroup.long c15:0x0210++0x00 line.long 0x00 "ID_DFR0,Debug Feature Register 0" bitfld.long 0x00 24.--27. " PMM ,Performance Monitor Model Support" "Reserved,Reserved,ID_DFR0,?..." bitfld.long 0x00 20.--23. " MDM_MM ,Memory-mapped Debug Model for M profile processors Support" "Not supported,?..." bitfld.long 0x00 16.--19. " TM_MM ,Trace Model (Memory-Mapped) Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 12.--15. " CTM_CB ,Coprocessor-Based Trace Debug Model Support" "Not supported,?..." bitfld.long 0x00 8.--11. " CDM_MM ,Memory-Mapped Debug Model Support" "Reserved,Reserved,Reserved,Reserved,Reserved,ARMv7.1,?..." bitfld.long 0x00 4.--7. " SDM_CB ,Secure Debug Model (Coprocessor) Support" "Reserved,Reserved,Reserved,Reserved,Reserved,ARMv7.1/CP14,?..." textline " " bitfld.long 0x00 0.--3. " CDM_CB ,Coprocessor Debug Model Support" "Reserved,Reserved,Reserved,Reserved,Reserved,ARMv7.1/CP14,?..." if (corename()=="CORTEXA7"||corename()=="CORTEXA7MPCORE") rgroup.long c15:0x6C9++0x0 line.long 0x00 "PMCEID0,Common Event Identification Register 0" bitfld.long 0x00 29. " PMCEID0[29] ,Bus cycle" "Not implemented,Implemented" bitfld.long 0x00 28. " [28] ,Instruction architecturally executed. Condition code check pass, write to TTBR" "Not implemented,Implemented" bitfld.long 0x00 27. " [27] ,Instruction speculatively executed" "Not implemented,Implemented" bitfld.long 0x00 26. " [26] ,Local memory error" "Not implemented,Implemented" textline " " bitfld.long 0x00 25. " [25] ,Bus access" "Not implemented,Implemented" bitfld.long 0x00 24. " [24] ,Level 2 data cache write-back" "Not implemented,Implemented" bitfld.long 0x00 23. " [23] ,Level 2 data cache refill" "Not implemented,Implemented" bitfld.long 0x00 22. " [22] ,Level 2 data cache access" "Not implemented,Implemented" textline " " bitfld.long 0x00 21. " [21] ,Level 1 instruction cache access" "Not implemented,Implemented" bitfld.long 0x00 20. " [20] ,Level 1 instruction cache access" "Not implemented,Implemented" bitfld.long 0x00 19. " [19] ,Data memory access" "Not implemented,Implemented" bitfld.long 0x00 15. " [15] ,Instruction architecturally executed, condition code check pass, unaligned load or store" "Not implemented,Implemented" textline " " bitfld.long 0x00 14. " [14] ,Instruction architecturally executed, condition code check pass, procedure return" "Not implemented,Implemented" bitfld.long 0x00 13. " [13] ,Instruction architecturally executed, immediate branch" "Not implemented,Implemented" bitfld.long 0x00 12. " [12] ,Instruction architecturally executed, condition code check pass, software change of the PC" "Not implemented,Implemented" bitfld.long 0x00 11. " [11] ,Instruction architecturally executed, condition code check pass, write to CONTEXTIDR" "Not implemented,Implemented" textline " " bitfld.long 0x00 10. " [10] ,Instruction architecturally executed, condition code check pass, exception return" "Not implemented,Implemented" bitfld.long 0x00 9. " [9] ,Exception taken" "Not implemented,Implemented" bitfld.long 0x00 8. " [8] ,Instruction architecturally executed" "Not implemented,Implemented" bitfld.long 0x00 7. " [7] ,Instruction architecturally executed, condition code check pass, store" "Not implemented,Implemented" textline " " bitfld.long 0x00 6. " [6] ,Instruction architecturally executed, condition code check pass, load" "Not implemented,Implemented" bitfld.long 0x00 5. " [5] ,Level 1 data TLB refill" "Not implemented,Implemented" bitfld.long 0x00 2. " [2] ,Level 1 instruction TLB refill" "Not implemented,Implemented" bitfld.long 0x00 1. " [1] ,Level 1 instruction cache refill" "Not implemented,Implemented" elif (corename()=="CORTEXA17"||corename()=="CORTEXA17MPCORE") rgroup.long c15:0x6C9++0x0 line.long 0x00 "PMCEID0,Common Event Identification Register 0" bitfld.long 0x00 31. " PMCEID0[31] ,Level 1 instruction cache access" "Not implemented,Implemented" bitfld.long 0x00 30. " [30] ,Level 1 data memory access" "Not implemented,Implemented" bitfld.long 0x00 29. " [29] ,Level 1 data memory access" "Not implemented,Implemented" bitfld.long 0x00 28. " [28] ,Level 1 data memory access" "Not implemented,Implemented" textline " " bitfld.long 0x00 27. " [27] ,Branches or other change in program flow that could have been predicted by the branch prediction resources of the processor" "Not implemented,Implemented" bitfld.long 0x00 26. " [26] ,Branch mispredicted or not predicted" "Not implemented,Implemented" bitfld.long 0x00 25. " [25] ,Unaligned access" "Not implemented,Implemented" bitfld.long 0x00 24. " [24] ,Unaligned access" "Not implemented,Implemented" textline " " bitfld.long 0x00 23. " [23] ,Branch speculatively executed - Procedure return" "Not implemented,Implemented" bitfld.long 0x00 22. " [22] ,Branch speculatively executed - Immediate branch" "Not implemented,Implemented" bitfld.long 0x00 21. " [21] ,Instruction speculatively executed - Software change of the PC" "Not implemented,Implemented" bitfld.long 0x00 20. " [20] ,Write to translation table register (TTBR0 or TTBR1)" "Not implemented,Implemented" textline " " bitfld.long 0x00 19. " [19] ,Change to ContextID retired" "Not implemented,Implemented" bitfld.long 0x00 18. " [18] ,Exception return architecturally executed" "Not implemented,Implemented" bitfld.long 0x00 17. " [17] ,Exception taken. Counts the number of exceptions architecturally taken" "Not implemented,Implemented" bitfld.long 0x00 16. " [16] ,Instruction architecturally executed" "Not implemented,Implemented" textline " " bitfld.long 0x00 15. " [15] ,Instruction architecturally executed" "Not implemented,Implemented" bitfld.long 0x00 14. " [14] ,Instruction architecturally executed" "Not implemented,Implemented" bitfld.long 0x00 13. " [13] ,Instruction architecturally executed" "Not implemented,Implemented" bitfld.long 0x00 12. " [12] ,Instruction architecturally executed" "Not implemented,Implemented" textline " " bitfld.long 0x00 11. " [11] ,Instruction architecturally executed" "Not implemented,Implemented" bitfld.long 0x00 10. " [10] ,Instruction architecturally executed" "Not implemented,Implemented" bitfld.long 0x00 9. " [9] ,Store instruction speculatively executed" "Not implemented,Implemented" bitfld.long 0x00 8. " [8] ,Store instruction speculatively executed" "Not implemented,Implemented" textline " " bitfld.long 0x00 7. " [7] ,Load instruction speculatively executed" "Not implemented,Implemented" bitfld.long 0x00 6. " [6] ,Load instruction speculatively executed" "Not implemented,Implemented" bitfld.long 0x00 5. " [5] ,Data read or write operation that causes a TLB refill at (at least) the lowest level of TLB" "Not implemented,Implemented" bitfld.long 0x00 4. " [4] ,Data read or write operation that causes a cache access at (at least) the lowest level of data or unified cache" "Not implemented,Implemented" textline " " bitfld.long 0x00 3. " [3] ,Data read or write operation that causes a cache access at (at least) the lowest level of data or unified cache" "Not implemented,Implemented" bitfld.long 0x00 2. " [2] ,Data read or write operation that causes a refill at (at least) the lowest level of data or unified cache" "Not implemented,Implemented" bitfld.long 0x00 1. " [1] ,Instruction fetch that causes a TLB refill at (at least) the lowest level of TLB" "Not implemented,Implemented" bitfld.long 0x00 0. " [0] ,Instruction fetch that causes a refill at (at least) the lowest level of instruction or unified cache" "Not implemented,Implemented" elif (corename()=="CORTEXA15"||corename()=="CORTEXA15MPCORE") rgroup.long c15:0x6C9++0x0 line.long 0x00 "PMCEID0,Common Event Identification Register 0" bitfld.long 0x00 29. " PMCEID0[29] ,Bus cycle" "Not implemented,Implemented" bitfld.long 0x00 28. " [28] ,Instruction architecturally executed. Condition code check pass, write to TTBR" "Not implemented,Implemented" bitfld.long 0x00 27. " [27] ,Instruction speculatively executed" "Not implemented,Implemented" bitfld.long 0x00 26. " [26] ,Local memory error" "Not implemented,Implemented" textline " " bitfld.long 0x00 25. " [25] ,Bus access" "Not implemented,Implemented" bitfld.long 0x00 24. " [24] ,Level 2 data cache write-back" "Not implemented,Implemented" bitfld.long 0x00 23. " [23] ,Level 2 data cache refill" "Not implemented,Implemented" bitfld.long 0x00 22. " [22] ,Level 2 data cache access" "Not implemented,Implemented" textline " " bitfld.long 0x00 21. " [21] ,Level 1 instruction cache access" "Not implemented,Implemented" bitfld.long 0x00 20. " [20] ,Level 1 instruction cache access" "Not implemented,Implemented" bitfld.long 0x00 19. " [19] ,Data memory access" "Not implemented,Implemented" bitfld.long 0x00 14. " [14] ,Instruction architecturally executed, condition code check pass, procedure return" "Not implemented,Implemented" textline " " bitfld.long 0x00 11. " [11] ,Instruction architecturally executed, condition code check pass, write to CONTEXTIDR" "Not implemented,Implemented" bitfld.long 0x00 10. " [10] ,Instruction architecturally executed, condition code check pass, exception return" "Not implemented,Implemented" bitfld.long 0x00 9. " [9] ,Exception taken" "Not implemented,Implemented" bitfld.long 0x00 5. " [5] ,Level 1 data TLB refill" "Not implemented,Implemented" textline " " bitfld.long 0x00 2. " [2] ,Level 1 instruction TLB refill" "Not implemented,Implemented" bitfld.long 0x00 1. " [1] ,Level 1 instruction cache refill" "Not implemented,Implemented" endif tree.end width 12. tree "System Control and Configuration" if (corename()=="CORTEXA15"||corename()=="CORTEXA15MPCORE"||corename()=="CORTEXA7"||corename()=="CORTEXA7MPCORE") group.long c15:0x1++0x0 line.long 0x0 "SCTLR,Control Register" bitfld.long 0x0 30. " TE ,Thumb exception enable" "ARM,Thumb" bitfld.long 0x0 29. " AFE ,Access Flag Enable" "Disabled,Enabled" bitfld.long 0x0 28. " TRE ,TEX remap enable" "Disabled,Enabled" bitfld.long 0x0 25. " EE ,Exception endianness" "Little,Big" textline " " bitfld.long 0x0 20. " UWXN ,Unprivileged write permission implies PL1 Execute Never" "Not forced,Forced" bitfld.long 0x0 19. " WXN ,Write permission implies PL1 Execute Never" "Not forced,Forced" bitfld.long 0x0 13. " V ,Base Location of Exception Registers" "0x00000000,0xFFFF0000" bitfld.long 0x0 12. " I ,Instruction Cache Enable" "Disabled,Enabled" textline " " bitfld.long 0x0 11. " Z ,Branch Prediction Enable" "Disabled,Enabled" bitfld.long 0x0 10. " SW ,SWP/SWPB Enable" "Disabled,Enabled" bitfld.long 0x0 2. " C ,Enable unified cache or data cache" "Disabled,Enabled" bitfld.long 0x0 1. " A ,Strict Alignment" "Disabled,Enabled" textline " " bitfld.long 0x0 0. " M ,MMU or Protection Unit" "Disabled,Enabled" elif (corename()=="CORTEXA17"||corename()=="CORTEXA17MPCORE") group.long c15:0x1++0x0 line.long 0x0 "SCTLR,System Control Register" bitfld.long 0x0 30. " TE ,Thumb exception enable" "ARM,Thumb" bitfld.long 0x0 29. " AFE ,Access Flag Enable" "Disabled,Enabled" bitfld.long 0x0 28. " TRE ,TEX remap enable" "Disabled,Enabled" textline " " bitfld.long 0x0 25. " EE ,Exception endianness" "Little,Big" bitfld.long 0x0 20. " UWXN ,Unprivileged write permission implies PL1 Execute Never" "Not forced,Forced" bitfld.long 0x0 19. " WXN ,Write permission implies PL1 Execute Never" "Not forced,Forced" textline " " bitfld.long 0x0 13. " V ,Base Location of Exception Registers" "0x00000000,0xFFFF0000" bitfld.long 0x0 12. " I ,Instruction Cache Enable" "Disabled,Enabled" bitfld.long 0x0 11. " Z ,Branch Prediction Enable" "Disabled,Enabled" textline " " bitfld.long 0x0 2. " C ,Enable unified cache or data cache" "Disabled,Enabled" bitfld.long 0x0 1. " A ,Alignment Fault Check enable" "Disabled,Enabled" bitfld.long 0x0 0. " M ,Address translation enable bit" "Disabled,Enabled" textline " " endif if (corename()=="CORTEXA17"||corename()=="CORTEXA17MPCORE") group.long c15:0x0101++0x0 line.long 0x0 "ACTLR,Auxiliary Control Register" bitfld.long 0x00 6. " SMP ,Enables coherent requests to the processor" "Disabled,Enabled" bitfld.long 0x00 3. " ASSE ,ACE STREX Signalling Enable" "Disabled,Enabled" bitfld.long 0x00 2. " L2PF ,Enable L2 prefetch" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " L1PF ,Enable L1 prefetch" "Disabled,Enabled" elif (corename()=="CORTEXA15"||corename()=="CORTEXA15MPCORE") group.long c15:0x101++0x0 line.long 0x0 "ACTLR,Auxiliary Control Register" bitfld.long 0x00 31. " SDEH ,Snoop-delayed exclusive handling" "Normal,Modified" bitfld.long 0x00 30. " FMCEA ,Force main clock processor enable active" "Not prevented,Prevented" bitfld.long 0x00 29. " FNVCEA ,Force NEON/VFP clock enable active" "Not prevented,Prevented" textline " " bitfld.long 0x00 27.--28. " WSNAT ,Write streaming no-allocate threshold" "12th,128th,512th,Disabled" bitfld.long 0x00 25.--26. " WSNL1AT ,Write streaming no L1-allocate threshold" "14th,64th,128th,Disabled" bitfld.long 0x00 24. " NCSE ,Non-cacheable streaming enhancement" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " FIORRTTSSAW ,Forces in-order requests to the same set and way" "Not forced,Forced" bitfld.long 0x00 22. " FIOLI ,Force in-order load issue" "Not forced,Forced" bitfld.long 0x00 21. " DL2TLBP ,Disabled L2 TLB prefetching" "No,Yes" textline " " bitfld.long 0x00 20. " DL2TBWIPAPAC ,Disable L2 TBW IPA PA cache" "No,Yes" bitfld.long 0x00 19. " DL2TBWS1WC ,Disable L2 TBW Stage 1 walk cache" "No,Yes" bitfld.long 0x00 18. " DL2TBWS1L2PAC ,Disable L2 TBW stage 1 L2 PA cache" "No,Yes" textline " " bitfld.long 0x00 17. " DL2TLBPO ,Disable L2 TLB Performance Optimization" "No,Yes" bitfld.long 0x00 16. " EFSOADLR ,Enables full Strongly-ordered and Device load replay" "Disabled,Enabled" bitfld.long 0x00 15. " FIIBEU ,Force in-order issue in branch execution unit" "Not forced,Forced" textline " " bitfld.long 0x00 14. " FLOIGCDPC ,Force limit of one instruction group commit/de-allocate per cycle" "Not forced,Limited" bitfld.long 0x00 13. " FACP14WCP15 ,Flush after CP14 and CP15 writes" "Normal,Flushed" bitfld.long 0x00 12. " FPCP14CP15 ,Force push of CP14 and CP15 registers" "Not forced,Pushed" textline " " bitfld.long 0x00 11. " FOISEG ,Force one instruction to start and end a group" "Not forced,Forced" bitfld.long 0x00 10. " FSAEIG ,Force serialization after each instruction group" "Not forced,Forced" bitfld.long 0x00 9. " DFRO ,Disable flag renaming optimization" "No,Yes" textline " " bitfld.long 0x00 8. " EWFIIANOPI ,Executes WFI instructions as NOP instructions" "Disabled,Enabled" bitfld.long 0x00 7. " EWFEIANOPI ,Executes WFE instructions as NOP instructions" "Disabled,Enabled" bitfld.long 0x00 6. " SMP ,Broadcast of cache and TLB maintenance operations enable" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " EPLDIANOP ,Execute PLD and PLDW instructions as a NOP instruction" "Disabled,Enabled" bitfld.long 0x00 4. " DIP ,Disable indirect predictor" "No,Yes" bitfld.long 0x00 3. " DMBTB ,Disable micro-BTB" "No,Yes" textline " " bitfld.long 0x00 2. " LOLBDPF ,Limits to one loop buffer detect per flush" "Normal,Limited" bitfld.long 0x00 1. " DLB ,Disable loop buffer" "No,Yes" bitfld.long 0x00 0. " EIBTB ,Enable invalidate of BTB" "Disabled,Enabled" elif (corename()=="CORTEXA7"||corename()=="CORTEXA7MPCORE") group.long c15:0x101++0x0 line.long 0x0 "ACTLR,Auxiliary Control Register" bitfld.long 0x00 28. " DBDI ,Disable branch dual issue" "No,Yes" bitfld.long 0x00 15. " DDVM ,Disable Distributed Virtual Memory (DVM) transactions" "No,Yes" bitfld.long 0x00 13.--14. " L1PCTL ,L1 Data prefetch control" "Disabled,1 pre-fetch,2 pre-fetches,3 pre-fetches" textline " " bitfld.long 0x00 12. " L1RADIS ,L1 Data Cache read-allocate mode disable" "No,Yes" bitfld.long 0x00 11. " L2RADIS ,L2 Data Cache read-allocate mode disable" "No,Yes" bitfld.long 0x00 10. " DODMBS ,Disable optimised data memory barrier behaviour" "No,Yes" textline " " bitfld.long 0x00 6. " SMP ,Enables coherent requests to the processor" "Disabled,Enabled" endif if (corename()=="CORTEXA15"||corename()=="CORTEXA15MPCORE") group.long c15:0x140F++0x00 line.long 0x0 "ACTLR2,Auxiliary Control Register 2" bitfld.long 0x00 31. " ECRCG ,Enable CPU regional clock gates" "Disabled,Enabled" bitfld.long 0x00 0. " EDCCADCCI ,Execute data cache clean as data cache clean/invalidate" "Disabled,Enabled" textline " " else hgroup.long c15:0x140F++0x00 hide.long 0x0 "ACTLR2,Auxiliary Control Register 2" endif if (corename()=="CORTEXA15"||corename()=="CORTEXA15MPCORE"||corename()=="CORTEXA17"||corename()=="CORTEXA17MPCORE") rgroup.long c15:0x201++0x00 line.long 0x0 "CPACR,Coprocessor Access Control Register" bitfld.long 0x0 31. " ASEDIS ,Disable Advanced SIMD Extension functionality" "No,Yes" bitfld.long 0x0 22.--23. " CP11 ,Coprocessor access control" "Denied,Privileged,Reserved,Full" bitfld.long 0x0 20.--21. " CP10 ,Coprocessor access control" "Denied,Privileged,Reserved,Full" elif (corename()=="CORTEXA7"||corename()=="CORTEXA7MPCORE") rgroup.long c15:0x201++0x00 line.long 0x0 "CPACR,Coprocessor Access Control Register" bitfld.long 0x0 31. " ASEDIS ,Disable Advanced SIMD Extension functionality" "No,Yes" bitfld.long 0x0 30. " D32DIS ,Disable use of registers D16-D31 of the VFP register file" "No,Yes" bitfld.long 0x0 22.--23. " CP11 ,Coprocessor access control" "Denied,Privileged,Reserved,Full" textline " " bitfld.long 0x0 20.--21. " CP10 ,Coprocessor access control" "Denied,Privileged,Reserved,Full" endif group.long c15:0x11++0x0 line.long 0x0 "SCR,Secure Configuration Register" bitfld.long 0x00 9. " SIF ,Secure Instruction Fetch" "Permitted,Not permitted" bitfld.long 0x00 8. " HCE ,Hyp Call enable" "Undefined,Enabled" bitfld.long 0x00 7. " SCD ,Secure Monitor Call disable" "No,Yes" textline " " bitfld.long 0x00 5. " AW ,Controls whether the Non-secure world can modify the A-bit in the CPSR" "Not allowed,Allowed" bitfld.long 0x00 4. " FW ,Controls whether the Non-secure world can modify the F-bit in the CPSR" "Not allowed,Allowed" bitfld.long 0x00 3. " EA ,External Abort exceptions handled in Abort mode or Monitor mode" "Abort,Monitor" textline " " bitfld.long 0x00 2. " FIQ ,FIQ exceptions handled in Abort mode or Monitor mode" "FIQ,Monitor" bitfld.long 0x00 1. " IRQ ,IRQ exceptions handled in Abort mode or Monitor mode" "IRQ,Monitor" bitfld.long 0x00 0. " NS ,Secure mode " "Secure,Non-secure" group.long c15:0x0111++0x00 line.long 0x00 "SDER,Secure Debug Enable Register" bitfld.long 0x00 1. " SUNIDEN ,Non-Invasive Secure User Debug Enable bit" "Denied,Permitted" bitfld.long 0x00 0. " SUIDEN ,Invasive Secure User Debug Enable bit" "Denied,Permitted" if (corename()=="CORTEXA15"||corename()=="CORTEXA15MPCORE") group.long c15:0x0211++0x00 line.long 0x00 "NSACR,Non-Secure Access Control Register" bitfld.long 0x00 18. " NS_SMP ,Determines if the SMP bit of the Auxiliary Control Register is writeable in Non-secure state" "Disabled,Enabled" bitfld.long 0x00 17. " NS_L2ERR ,L2 internal asynchronous error and AXI asynchronous error writeable in Non-secure state" "Disabled,Enabled" bitfld.long 0x00 15. " NSASEDIS ,Disable Non-secure Advanced SIMD Extension functionality" "No,Yes" textline " " bitfld.long 0x00 11. " CP11 ,Coprocessor 11 in the Non-secure World Access Permission" "Denied,Permitted" bitfld.long 0x00 10. " CP10 ,Coprocessor 10 in the Non-secure World Access Permission" "Denied,Permitted" elif (corename()=="CORTEXA7"||corename()=="CORTEXA7MPCORE") group.long c15:0x0211++0x00 line.long 0x00 "NSACR,Non-Secure Access Control Register" bitfld.long 0x00 18. " NS_SMP ,Determines if the SMP bit of the Auxiliary Control Register is writeable in Non-secure state" "Disabled,Enabled" bitfld.long 0x00 15. " NSASEDIS ,Disable Non-secure Advanced SIMD Extension functionality" "No,Yes" bitfld.long 0x00 14. " NSD32DIS ,Disable the Non-secure use of D16-D31 of the VFP register file" "No,Yes" textline " " bitfld.long 0x00 11. " CP11 ,Coprocessor 11 in the Non-secure World Access Permission" "Denied,Permitted" bitfld.long 0x00 10. " CP10 ,Coprocessor 10 in the Non-secure World Access Permission" "Denied,Permitted" elif (corename()=="CORTEXA17"||corename()=="CORTEXA17MPCORE") group.long c15:0x0211++0x00 line.long 0x00 "NSACR,Non-Secure Access Control Register" bitfld.long 0x00 18. " NS_SMP ,Determines if the SMP bit of the Auxiliary Control Register is writeable in Non-secure state" "Non-writeable,Writeable" bitfld.long 0x00 17. " NS_L2ERR ,Determines if the L2 Extended Control Register(L2ECTLR), is writeable in Non-secure state" "Non-writeable,Writeable" bitfld.long 0x00 16. " NS_ACTLR_PF_WRITE ,Determines if the ACTLR.L1PF and ACTLR.L2PF registers are writeable in Non-secure state" "Non-writeable,Writeable" textline " " bitfld.long 0x00 15. " NSASEDIS ,Disable Non-secure Advanced SIMD Extension functionality" "No,Yes" bitfld.long 0x00 14. " NSD32DIS ,Disable the Non-secure use of D16-D31 of the VFP register file" "No,Yes" bitfld.long 0x00 11. " CP11 ,Coprocessor 11 in the Non-secure World Access Permission" "Denied,Permitted" textline " " bitfld.long 0x00 10. " CP10 ,Coprocessor 10 in the Non-secure World Access Permission" "Denied,Permitted" endif group.long c15:0x000C++0x00 line.long 0x00 "VBAR,Vector Base Address Register" hexmask.long 0x00 5.--31. 0x20 " VBADDR ,Vector Base Address" group.long c15:0x010C++0x00 line.long 0x00 "MVBAR,Monitor Vector Base Address Register" hexmask.long 0x00 5.--31. 0x20 " MVBADDR ,Monitor Vector Base Address" textline " " rgroup.long c15:0x001C++0x00 line.long 0x00 "ISR,Interrupt Status Register" bitfld.long 0x00 8. " A ,External abort pending flag" "Not pending,Pending" bitfld.long 0x00 7. " I ,Interrupt pending flag" "Not pending,Pending" bitfld.long 0x00 6. " F ,Fast interrupt pending flag" "Not pending,Pending" textline " " if (corename()=="CORTEXA15"||corename()=="CORTEXA15MPCORE"||corename()=="CORTEXA7"||corename()=="CORTEXA7MPCORE") rgroup.long c15:0x400F++0x00 line.long 0x00 "CBAR,Configuration Base Address Register" hexmask.long.tbyte 0x00 15.--31. 1. " PERIPHBASE[31:15] ,Periphbase[31:15]" hexmask.long.byte 0x00 0.--7. 1. " PERIPHBASE[39:32] ,Periphbase[39:32]" else hgroup.long c15:0x400F++0x00 hide.long 0x00 "CBAR,Configuration Base Address Register" endif if (corename()=="CORTEXA17"||corename()=="CORTEXA17MPCORE") if (((d.l(c15:0x1609))&0x3)==0x3) group.long c15:0x1609++0x00 line.long 0x00 "SCUCTLR,SCU Control Register" bitfld.long 0x00 30. " PRM3 ,Disable processor 3 retention" "No,Yes" bitfld.long 0x00 28.--29. " PPS3 ,Processor 3 power status" "Normal,Not present,Retention,Powerdown" bitfld.long 0x00 26. " PRM2 ,Disable processor 2 retention" "No,Yes" textline " " bitfld.long 0x00 24.--25. " PPS2 ,Processor 2 power status" "Normal,Not present,Retention,Powerdown" bitfld.long 0x00 22. " PRM1 ,Disable processor 1 retention" "No,Yes" bitfld.long 0x00 20.--21. " PPS1 ,Processor 1 power status" "Normal,Not present,Retention,Powerdown" textline " " bitfld.long 0x00 18. " PRM0 ,Disable processor 0 retention" "No,Yes" bitfld.long 0x00 16.--17. " PPS0 ,Processor 0 power status" "Normal,Not present,Retention,Powerdown" bitfld.long 0x00 7. " CPSMP[3] ,Copy of the ACTLR.SMP for processor 3" "Disabled,Enabled" textline " " bitfld.long 0x00 6. " CPSMP[2] ,Copy of the ACTLR.SMP for processor 2" "Disabled,Enabled" bitfld.long 0x00 5. " CPSMP[1] ,Copy of the ACTLR.SMP for processor 1" "Disabled,Enabled" bitfld.long 0x00 4. " CPSMP[0] ,Copy of the ACTLR.SMP for processor 0" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " NP ,Number of processors" "1,2,3,4" textline " " elif (((d.l(c15:0x1609))&0x3)==0x2) group.long c15:0x1609++0x00 line.long 0x00 "SCUCTLR,SCU Control Register" bitfld.long 0x00 26. " PRM2 ,Disable processor 2 retention" "No,Yes" bitfld.long 0x00 24.--25. " PPS2 ,Processor 2 power status" "Normal,Not present,Retention,Powerdown" bitfld.long 0x00 22. " PRM1 ,Disable processor 1 retention" "No,Yes" textline " " bitfld.long 0x00 20.--21. " PPS1 ,Processor 1 power status" "Normal,Not present,Retention,Powerdown" bitfld.long 0x00 18. " PRM0 ,Disable processor 0 retention" "No,Yes" bitfld.long 0x00 16.--17. " PPS0 ,Processor 0 power status" "Normal,Not present,Retention,Powerdown" textline " " bitfld.long 0x00 6. " CPSMP[2] ,Copy of the ACTLR.SMP for processor 2" "Disabled,Enabled" bitfld.long 0x00 5. " CPSMP[1] ,Copy of the ACTLR.SMP for processor 1" "Disabled,Enabled" bitfld.long 0x00 4. " CPSMP[0] ,Copy of the ACTLR.SMP for processor 0" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " NP ,Number of processors" "1,2,3,4" textline " " elif (((d.l(c15:0x1609))&0x3)==0x1) group.long c15:0x1609++0x00 line.long 0x00 "SCUCTLR,SCU Control Register" bitfld.long 0x00 22. " PRM1 ,Disable processor 1 retention" "No,Yes" bitfld.long 0x00 20.--21. " PPS1 ,Processor 1 power status" "Normal,Not present,Retention,Powerdown" bitfld.long 0x00 18. " PRM0 ,Disable processor 0 retention" "No,Yes" textline " " bitfld.long 0x00 16.--17. " PPS0 ,Processor 0 power status" "Normal,Not present,Retention,Powerdown" bitfld.long 0x00 5. " CPSMP[1] ,Copy of the ACTLR.SMP for processor 1" "Disabled,Enabled" bitfld.long 0x00 4. " CPSMP[0] ,Copy of the ACTLR.SMP for processor 0" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " NP ,Number of processors" "1,2,3,4" textline " " elif (((d.l(c15:0x1609))&0x3)==0x0) group.long c15:0x1609++0x00 line.long 0x00 "SCUCTLR,SCU Control Register" bitfld.long 0x00 18. " PRM0 ,Disable processor 0 retention" "No,Yes" bitfld.long 0x00 16.--17. " PPS0 ,Processor 0 power status" "Normal,Not present,Retention,Powerdown" bitfld.long 0x00 4. " CPSMP[0] ,Copy of the ACTLR.SMP for processor 0" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " NP ,Number of processors" "1,2,3,4" textline " " endif group.long c15:0x410F++0x00 line.long 0x00 "FILASTARTR,Peripheral port start address register" hexmask.long.tbyte 0x00 12.--31. 0x10 " FLT_START_ADDR ,Start address of the peripheral port physical memory region" bitfld.long 0x00 0. " FILT_EN ,FLT_START_ADDR and FLT_END_ADDR are valid" "Invalid,Valid" group.long c15:0x420F++0x00 line.long 0x00 "FILAENDR,Peripheral port end address register" hexmask.long.tbyte 0x00 12.--31. 0x10 " FLT_END_ADDR ,End address of the peripheral port physical memory region" elif (corename()=="CORTEXA15"||corename()=="CORTEXA15MPCORE"||corename()=="CORTEXA7"||corename()=="CORTEXA7MPCORE") hgroup.long c15:0x1609++0x00 hide.long 0x00 "SCUCTLR,SCU Control Register" hgroup.long c15:0x410F++0x00 hide.long 0x00 "FILASTARTR,Peripheral port start address register" hgroup.long c15:0x420F++0x00 hide.long 0x00 "FILAENDR,Peripheral port end address register" endif tree.end width 12. tree "Memory Management Unit" if (corename()=="CORTEXA17"||corename()=="CORTEXA17MPCORE") group.long c15:0x0001++0x0 line.long 0x0 "SCTLR,System Control Register" bitfld.long 0x0 30. " TE ,Thumb exception enable" "ARM,Thumb" bitfld.long 0x0 29. " AFE ,Access Flag Enable" "Disabled,Enabled" bitfld.long 0x0 28. " TRE ,TEX remap enable" "Disabled,Enabled" textline " " bitfld.long 0x0 25. " EE ,Exception endianness" "Little,Big" bitfld.long 0x0 20. " UWXN ,Unprivileged write permission implies PL1 Execute Never" "Not forced,Forced" bitfld.long 0x0 19. " WXN ,Write permission implies PL1 Execute Never" "Not forced,Forced" textline " " bitfld.long 0x0 13. " V ,Base Location of Exception Registers" "0x00000000,0xFFFF0000" bitfld.long 0x0 12. " I ,Instruction Cache Enable" "Disabled,Enabled" bitfld.long 0x0 11. " Z ,Branch Prediction Enable" "Disabled,Enabled" textline " " bitfld.long 0x0 2. " C ,Enable unified cache or data cache" "Disabled,Enabled" bitfld.long 0x0 1. " A ,Alignment Fault Check enable" "Disabled,Enabled" bitfld.long 0x0 0. " M ,Address translation enable bit" "Disabled,Enabled" textline " " elif (corename()=="CORTEXA15"||corename()=="CORTEXA15MPCORE"||corename()=="CORTEXA7"||corename()=="CORTEXA7MPCORE") group.long c15:0x1++0x0 line.long 0x0 "SCTLR,Control Register" bitfld.long 0x0 30. " TE ,Thumb exception enable" "ARM,Thumb" bitfld.long 0x0 29. " AFE ,Access Flag Enable" "Disabled,Enabled" bitfld.long 0x0 28. " TRE ,TEX remap enable" "Disabled,Enabled" textline " " bitfld.long 0x0 25. " EE ,Exception endianness" "Little,Big" bitfld.long 0x0 20. " UWXN ,Unprivileged write permission implies PL1 Execute Never" "Not forced,Forced" bitfld.long 0x0 19. " WXN ,Write permission implies PL1 Execute Never" "Not forced,Forced" textline " " bitfld.long 0x0 13. " V ,Base Location of Exception Registers" "0x00000000,0xFFFF0000" bitfld.long 0x0 12. " I ,Instruction Cache Enable" "Disabled,Enabled" bitfld.long 0x0 11. " Z ,Branch Prediction Enable" "Disabled,Enabled" textline " " bitfld.long 0x0 10. " SW ,SWP/SWPB Enable" "Disabled,Enabled" bitfld.long 0x0 2. " C ,Enable unified cache or data cache" "Disabled,Enabled" bitfld.long 0x0 1. " A ,Strict Alignment" "Disabled,Enabled" textline " " bitfld.long 0x0 0. " M ,MMU or Protection Unit" "Disabled,Enabled" textline " " endif if (((d.l(c15:0x0002))&0x2)==0x2)&&(((d.l(c15:0x0202))&0x80000000)==0x00000000) group.long c15:0x0002++0x00 line.long 0x00 "TTBR0,Translation Table Base Register 0" hexmask.long.tbyte 0x00 14.--31. 0x40 " TTB0_ADDR ,Translation table base 0 address" bitfld.long 0x00 5. " NOS ,Not Outer Shareable bit" "Outer,Inner" bitfld.long 0x00 3.--4. " RGN ,Region bits" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable" textline " " bitfld.long 0x00 2. " IMP ,Implementation defined" "Low,High" bitfld.long 0x00 1. " S ,Shareable bit" "Non-shareable,Shareable" bitfld.long 0x00 0. 6. " IRGN ,Inner region bits for Multiprocessing Extensions" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable" elif (((d.l(c15:0x0002))&0x2)==0x0)&&(((d.l(c15:0x0202))&0x80000000)==0x00000000) group.long c15:0x0002++0x00 line.long 0x00 "TTBR0,Translation Table Base Register 0" hexmask.long.tbyte 0x00 14.--31. 0x40 " TTB0_ADDR ,Translation table base 0 address" bitfld.long 0x00 3.--4. " RGN ,Region bits" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable" bitfld.long 0x00 2. " IMP ,Implementation defined" "Low,High" textline " " bitfld.long 0x00 1. " S ,Shareable bit" "Non-shareable,Shareable" bitfld.long 0x00 0. 6. " IRGN ,Inner region bits for Multiprocessing Extensions" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable" elif (((d.l(c15:0x0202))&0x80000000)==0x80000000) group.quad c15:0x10020++0x01 line.quad 0x00 "TTBR0,Translation Table Base Register 0" hexmask.quad.byte 0x00 48.--55. 1. " ASID ,ASID for the translation table base address" hexmask.quad 0x00 0.--39. 1. " BADDR ,Translation table base address" endif if (((d.l(c15:0x0102))&0x2)==0x2)&&(((d.l(c15:0x0202))&0x80000000)==0x00000000) group.long c15:0x0102++0x00 line.long 0x00 "TTBR1,Translation Table Base Register 1" hexmask.long.tbyte 0x00 14.--31. 0x40 " TTB1_ADDR ,Translation table base 1 address" bitfld.long 0x00 5. " NOS ,Not Outer Shareable bit" "Outer,Inner" bitfld.long 0x00 3.--4. " RGN ,Region bits" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable" textline " " bitfld.long 0x00 2. " IMP ,Implementation defined" "Low,High" bitfld.long 0x00 1. " S ,Shareable bit" "Non-shareable,Shareable" bitfld.long 0x00 0. 6. " IRGN ,Inner region bits for Multiprocessing Extensions" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable" elif (((d.l(c15:0x0102))&0x2)==0x0)&&(((d.l(c15:0x0202))&0x80000000)==0x00000000) group.long c15:0x0102++0x00 line.long 0x00 "TTBR1,Translation Table Base Register 1" hexmask.long.tbyte 0x00 14.--31. 0x40 " TTB1_ADDR ,Translation table base 1 address" bitfld.long 0x00 3.--4. " RGN ,Region bits" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable" bitfld.long 0x00 2. " IMP ,Implementation defined" "Low,High" textline " " bitfld.long 0x00 1. " S ,Shareable bit" "Non-shareable,Shareable" bitfld.long 0x00 0. 6. " IRGN ,Inner region bits for Multiprocessing Extensions" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable" elif (((d.l(c15:0x0202))&0x80000000)==0x80000000) group.quad c15:0x11020++0x01 line.quad 0x00 "TTBR1,Translation Table Base Register 1" hexmask.quad.byte 0x00 48.--55. 1. " ASID ,ASID for the translation table base address" hexmask.quad 0x00 0.--39. 1. " BADDR ,Translation table base address" endif if (((d.l(c15:0x0202))&0x80000000)==0x00000000) group.long c15:0x0202++0x00 line.long 0x00 "TTBCR,Translation Table Base Control Register" bitfld.long 0x00 31. " EAE ,Extended Address Enable" "32-bit,40-bit" bitfld.long 0x00 5. " PD1 ,Translation table walk Disable bit for TTBR1" "No,Yes" bitfld.long 0x00 4. " PD0 ,Translation table walk Disable bit for TTBR0" "No,Yes" textline " " bitfld.long 0x00 0.--2. " N ,Indicate the width of the base address held in TTBR0" "16KB,8KB,4KB,2KB,1KB,512 bytes,256 bytes,128 bytes" else group.long c15:0x0202++0x00 line.long 0x00 "TTBCR,Translation Table Base Control Register" bitfld.long 0x00 31. " EAE ,Extended Address Enable" "32-bit,40-bit" bitfld.long 0x00 30. " IMP ,IMPLEMENTATION DEFINED" "Low,High" bitfld.long 0x00 28.--29. " SH1 ,Shareability attributes for the memory associated with the translation table walks using TTBR1" "Non-Shareable,Reserved,Outer Shareable,Inner Shareable" textline " " bitfld.long 0x00 26.--27. " ORGN1 ,Outer Cacheability attributes for the memory associated with the translation table walks using TTBR1" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable" bitfld.long 0x00 24.--25. " IRGN1 ,Inner Cacheability attributes for the memory associated with the translation table walks using TTBR1" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable" bitfld.long 0x00 23. " EPD1 ,Translation table walk disable for translations using TTBR1" "No,Yes" textline " " bitfld.long 0x00 22. " A1 ,Selects whether TTBR0 or TTBR1 defines the ASID" "TTBR0,TTBR1" bitfld.long 0x00 16.--18. " T1SZ ,The Size offset of the TTBR1 addressed region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 12.--13. " SH0 ,Shareability attributes for the memory associated with the translation table walks using TTBR0" "Non-Shareable,Reserved,Outer Shareable,Inner Shareable" textline " " bitfld.long 0x00 10.--11. " ORGN0 ,Outer Cacheability attributes for the memory associated with the translation table walks using TTBR0" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable" bitfld.long 0x00 8.--9. " IRGN0 ,Inner Cacheability attributes for the memory associated with the translation table walks using TTBR0" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable" bitfld.long 0x00 7. " EPD0 ,Translation table walk disable for translations using TTBR0" "No,Yes" textline " " bitfld.long 0x00 0.--2. " T0SZ ,The Size offset of the TTBR0 addressed memory region" "0,1,2,3,4,5,6,7" endif textline " " group.long c15:0x0003++0x00 line.long 0x00 "DACR,Domain Access Control Register" bitfld.long 0x0 30.--31. " D15 ,Domain Access 15" "Denied,Client,Reserved,Manager" bitfld.long 0x0 28.--29. " D14 ,Domain Access 14" "Denied,Client,Reserved,Manager" bitfld.long 0x0 26.--27. " D13 ,Domain Access 13" "Denied,Client,Reserved,Manager" textline " " bitfld.long 0x0 24.--25. " D12 ,Domain Access 12" "Denied,Client,Reserved,Manager" bitfld.long 0x0 22.--23. " D11 ,Domain Access 11" "Denied,Client,Reserved,Manager" bitfld.long 0x0 20.--21. " D10 ,Domain Access 10" "Denied,Client,Reserved,Manager" textline " " bitfld.long 0x0 18.--19. " D9 ,Domain Access 9" "Denied,Client,Reserved,Manager" bitfld.long 0x0 16.--17. " D8 ,Domain Access 8" "Denied,Client,Reserved,Manager" bitfld.long 0x0 14.--15. " D7 ,Domain Access 7" "Denied,Client,Reserved,Manager" textline " " bitfld.long 0x0 12.--13. " D6 ,Domain Access 6" "Denied,Client,Reserved,Manager" bitfld.long 0x0 10.--11. " D5 ,Domain Access 5" "Denied,Client,Reserved,Manager" bitfld.long 0x0 8.--9. " D4 ,Domain Access 4" "Denied,Client,Reserved,Manager" textline " " bitfld.long 0x0 6.--7. " D3 ,Domain Access 3" "Denied,Client,Reserved,Manager" bitfld.long 0x0 4.--5. " D2 ,Domain Access 2" "Denied,Client,Reserved,Manager" bitfld.long 0x0 2.--3. " D1 ,Domain Access 1" "Denied,Client,Reserved,Manager" textline " " bitfld.long 0x0 0.--1. " D0 ,Domain Access 0" "Denied,Client,Reserved,Manager" textline " " if (corename()=="CORTEXA15"||corename()=="CORTEXA15MPCORE") if (((d.l(c15:0x0202))&0x80000000)==0x80000000) group.long c15:0x0005++0x00 line.long 0x00 "DFSR,Data Fault Status Register" bitfld.long 0x00 13. " CM ,Cache maintenance fault" "Not aborted,Aborted" bitfld.long 0x00 12. " EXT ,External Abort Qualifier" "DECERR,SLVERR" bitfld.long 0x00 11. " WNR ,Access Caused an Abort Type" "Read,Write" textline " " bitfld.long 0x00 0.--5. " STATUS ,Fault Status" "Reserved,Reserved,Reserved,Reserved,Reserved,Translation fault/First level,Translation fault/Second level,Translation fault/Third level,Reserved,Access flag fault/First level,Access flag fault/Second level,Access flag fault/Third level,Reserved,Permission fault/First level,Permission fault/Second level,Permission fault/Third level,Synchronous external abort,Asynchronous external abort,Reserved,Reserved,Reserved,Synchronous external abort on translation table walk/First level,Synchronous external abort on translation table walk/Second level,Synchronous external abort on translation table walk/Third level,Synchronous parity error on memory access,Asynchronous parity error on memory access,Reserved,Reserved,Reserved,Synchronous parity error on memory access on translation table walk/First level,Synchronous parity error on memory access on translation table walk/Second level,Synchronous parity error on memory access on translation table walk/Third level,Reserved,Alignment fault,Debug event,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Lockdown Abort,Reserved,Reserved,Reserved,Reserved,Reserved,Coprocessor Abort,?..." else group.long c15:0x0005++0x00 line.long 0x00 "DFSR,Data Fault Status Register" bitfld.long 0x00 13. " CM ,Cache maintenance fault" "Not aborted,Aborted" bitfld.long 0x00 12. " EXT ,External Abort Qualifier" "DECERR,SLVERR" bitfld.long 0x00 11. " WNR ,Access Caused an Abort Type" "Read,Write" textline " " bitfld.long 0x00 4.--7. " DOMAIN ,Domain Accessed When a Data Fault Occurs" "D0,D1,D2,D3,D4,D5,D6,D7,D8,D9,D10,D11,D12,D13,D14,D15" bitfld.long 0x00 0.--3. 10. " FS ,Fault Status" "Reserved,Alignment fault,Reserved,Reserved,Instruction cache maintenance fault,Translation fault/First level,Access flag fault/Second level,Translation fault/Second level,Synchronous external abort,Domain fault/First level,Reserved,Domain fault/Second level,Synchronous external abort/First level,Permission fault/First level,Synchronous external abort/Second level,Permission fault/Second level,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Asynchronous external abort,Reserved,Asynchronous parity error on memory access,Synchronous parity error on memory access,Reserved,Reserved,Synchronous parity error on translation table walk/First level,Reserved,Synchronous parity error on translation table walk/Second level,Reserved" endif elif (corename()=="CORTEXA7"||corename()=="CORTEXA7MPCORE") if (((d.l(c15:0x0202))&0x80000000)==0x80000000) group.long c15:0x0005++0x00 line.long 0x00 "DFSR,Data Fault Status Register" bitfld.long 0x00 13. " CM ,Cache maintenance fault" "Not aborted,Aborted" bitfld.long 0x00 12. " EXT ,External Abort Qualifier" "DECERR,SLVERR" bitfld.long 0x00 11. " WNR ,Access Caused an Abort Type" "Read,Write" textline " " bitfld.long 0x00 0.--5. " STATUS ,Fault Status" "Reserved,Reserved,Reserved,Reserved,Reserved,Translation fault/First level,Translation fault/Second level,Translation fault/Third level,Reserved,Access flag fault/First level,Access flag fault/Second level,Access flag fault/Third level,Reserved,Permission fault/First level,Permission fault/Second level,Permission fault/Third level,Synchronous external abort,Asynchronous external abort,Reserved,Reserved,Reserved,Synchronous external abort on translation table walk/First level,Synchronous external abort on translation table walk/Second level,Synchronous external abort on translation table walk/Third level,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Alignment fault,Debug event,?..." else group.long c15:0x0005++0x00 line.long 0x00 "DFSR,Data Fault Status Register" bitfld.long 0x00 13. " CM ,Cache maintenance fault" "Not aborted,Aborted" bitfld.long 0x00 12. " EXT ,External Abort Qualifier" "DECERR,SLVERR" bitfld.long 0x00 11. " WNR ,Access Caused an Abort Type" "Read,Write" textline " " bitfld.long 0x00 4.--7. " DOMAIN ,Domain Accessed When a Data Fault Occurs" "D0,D1,D2,D3,D4,D5,D6,D7,D8,D9,D10,D11,D12,D13,D14,D15" bitfld.long 0x00 0.--3. 10. " FS ,Generated Exception Type" "Reserved,Alignment,Debug,Access/section,Instruction,Translation/section,Access/page,Translation/page,Non-translation/synchronous external,Domain/section,Reserved,Domain/page,L1/synchronous external,Permission/section,L2/synchronous external,Permission/page,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Asynchronous external,?..." endif elif (corename()=="CORTEXA17"||corename()=="CORTEXA17MPCORE") if (((d.l(c15:0x0202))&0x80000000)==0x00000000) group.long c15:0x0005++0x00 line.long 0x00 "DFSR,Data Fault Status Register" bitfld.long 0x00 13. " CM ,Cache maintenance fault" "Not aborted,Aborted" bitfld.long 0x00 12. " EXT ,External Abort Qualifier" "DECERR,SLVERR" bitfld.long 0x00 11. " WNR ,Access Caused an Abort Type" "Read,Write" textline " " bitfld.long 0x00 4.--7. " DOMAIN ,Domain Accessed When a Data Fault Occurs" "D0,D1,D2,D3,D4,D5,D6,D7,D8,D9,D10,D11,D12,D13,D14,D15" bitfld.long 0x00 0.--3. 10. " FS ,Generated Exception Type" "Reserved,Alignment,Debug,Access/section,Reserved,Translation/section,Access/page,Translation/page,Reserved,Domain/section,Reserved,Domain/page,L1/external,Permission/section,L2/external,Permission/page,TLB,Reserved,Reserved,Reserved,Reserved,Reserved,Asynchronous external,?..." else group.long c15:0x0005++0x00 line.long 0x00 "DFSR,Data Fault Status Register" bitfld.long 0x00 13. " CM ,Cache maintenance fault" "Not aborted,Aborted" bitfld.long 0x00 12. " EXT ,External Abort Qualifier" "DECERR,SLVERR" bitfld.long 0x00 11. " WNR ,Access Caused an Abort Type" "Read,Write" textline " " bitfld.long 0x00 0.--5. " STATUS ,Fault Status" "Reserved,Reserved,Reserved,Reserved,Reserved,Translation fault/1st level,Translation fault/2nd level,Translation fault/3rd level,Reserved,Access flag fault/1st level,Access flag fault/2nd level,Access flag fault/3rd level,Reserved,Permission fault/1st level,Permission fault/2nd level,Permission fault/3rd level,Reserved,Asynchronous external abort,Reserved,Reserved,Reserved,Synchronous external abort on translation table walk/1st level,Synchronous external abort on translation table walk/2nd level,Synchronous external abort on translation table walk/3rd level,TLB,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Alignment fault,Debug event,?..." endif endif if (corename()=="CORTEXA15"||corename()=="CORTEXA15MPCORE") group.long c15:0x0015++0x00 line.long 0x00 "ADFSR,Auxiliary Data Fault Status Register" bitfld.long 0x00 31. " VALID ,L1 or L2 ECC double bit error indicator" "No error,Error" hexmask.long.byte 0x00 24.--30. 1. " RAMID ,RAM identifier" bitfld.long 0x00 23. " L2E ,L2 Error" "No error,Error" textline " " bitfld.long 0x00 18.--22. " B/W ,Bank/Way" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.tbyte 0x00 0.--17. 1. " IND ,Index" else hgroup.long c15:0x0015++0x00 hide.long 0x00 "ADFSR,Auxiliary Data Fault Status Register" endif group.long c15:0x0006++0x00 line.long 0x00 "DFAR,Data Fault Address Register" if (corename()=="CORTEXA15"||corename()=="CORTEXA15MPCORE") if (((d.l(c15:0x0202))&0x80000000)==0x80000000) group.long c15:0x0105++0x00 line.long 0x00 "IFSR,Instruction Fault Status Register" bitfld.long 0x00 12. " EXT ,External Abort Type" "DECERR,SLVERR" textline " " bitfld.long 0x00 0.--5. " STATUS ,Fault Status" "Reserved,Reserved,Reserved,Reserved,Reserved,Translation fault/First level,Translation fault/Second level,Translation fault/Third level,Reserved,Access flag fault/First level,Access flag fault/Second level,Access flag fault/Third level,Reserved,Permission fault/First level,Permission fault/Second level,Permission fault/Third level,Synchronous external abort,Reserved,Reserved,Reserved,Reserved,Synchronous external abort on translation table walk/First level,Synchronous external abort on translation table walk/Second level,Synchronous external abort on translation table walk/Third level,Synchronous parity error on memory access,Reserved,Reserved,Reserved,Reserved,Synchronous parity error on memory access on translation table walk/First level,Synchronous parity error on memory access on translation table walk/Second level,Synchronous parity error on memory access on translation table walk/Third level,?..." else group.long c15:0x0105++0x00 line.long 0x00 "IFSR,Instruction Fault Status Register" bitfld.long 0x00 12. " EXT ,External Abort Type" "DECERR,SLVERR" textline " " bitfld.long 0x00 0.--3. 10. " FS ,Generated Exception Type" "Reserved,Reserved,Debug event,Access flag fault/First level,Reserved,Translation fault/First level,Access flag fault/Second level,Translation fault/Second level,Non-translation/synchronous external abort,Domain fault/First level,Reserved,Domain fault/Second level,Synchronous external abort on translation table walk/First level,Permission fault/First level,Synchronous external abort on translation table walk/Second level,Permission fault/Second level,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Synchronous parity error on memory access,Reserved,Reserved,Synchronous parity error on translation table walk,Reserved,Synchronous parity error on translation table walk,Reserved" endif elif (corename()=="CORTEXA7"||corename()=="CORTEXA7MPCORE") if (((d.l(c15:0x0202))&0x80000000)==0x80000000) group.long c15:0x0105++0x00 line.long 0x00 "IFSR,Instruction Fault Status Register" bitfld.long 0x00 12. " EXT ,External Abort Type" "DECERR,SLVERR" textline " " bitfld.long 0x00 0.--5. " STATUS ,Generated Exception Type" "Reserved,Reserved,Reserved,Reserved,Reserved,Translation fault/First level,Translation fault/Second level,Translation fault/Third level,Reserved,Access fault flag/First level,Access fault flag/Second level,Access fault flag/Third level,Reserved,Permission fault/First level,Permission fault/Second level,Permission fault/Third level,Synchronous external abort,Reserved,Debug event,?..." else group.long c15:0x0105++0x00 line.long 0x00 "IFSR,Instruction Fault Status Register" bitfld.long 0x00 12. " EXT ,External Abort Type" "DECERR,SLVERR" textline " " bitfld.long 0x00 0.--3. 10. " FS ,Generated Exception Type" "Reserved,Reserved,Debug,Access/section,Reserved,Translation/section,Access/page,Translation/page,Non-translation/synchronous external,Domain/section,Reserved,Domain/page,L1/external,Permission/section,L2/external,Permission/page,?..." endif elif (corename()=="CORTEXA17"||corename()=="CORTEXA17MPCORE") if (((d.l(c15:0x202))&0x80000000)==0x80000000) group.long c15:0x0105++0x00 line.long 0x00 "IFSR,Instruction Fault Status Register" bitfld.long 0x00 12. " EXT ,External Abort Type" "DECERR,SLVERR" bitfld.long 0x00 9. " LPAE ,Large physical address extension" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--5. " STATUS ,Fault Status" "Reserved,Reserved,Reserved,Reserved,Reserved,Translation fault/1st level,Translation fault/2nd level,Translation fault/3rd level,Reserved,Access flag fault/1st level,Access flag fault/2nd level,Access flag fault/3rd level,Reserved,Permission fault/1st level,Permission fault/2nd level,Permission fault/3rd level,Reserved,Asynchronous external abort,Reserved,Reserved,Reserved,Synchronous external abort on translation table walk/1st level,Synchronous external abort on translation table walk/2nd level,Synchronous external abort on translation table walk/3rd level,TLB,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Alignment fault,Debug event,?..." else group.long c15:0x0105++0x00 line.long 0x00 "IFSR,Instruction Fault Status Register" bitfld.long 0x00 12. " EXT ,External Abort Type" "DECERR,SLVERR" bitfld.long 0x00 9. " LPAE ,Large physical address extension" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--3. 10. " FS ,Generated Exception Type" "Reserved,Alignment,Debug,Access/section,Reserved,Translation/section,Access/page,Translation/page,Reserved,Domain/section,Reserved,Domain/page,L1/external,Permission/section,L2/external,Permission/page,TLB,Reserved,Reserved,Reserved,Reserved,Reserved,Asynchronous external,?..." endif endif group.long c15:0x0206++0x00 line.long 0x00 "IFAR,Instruction Fault Address Register" if (((d.l(c15:0x202))&0x80000000)==0x80000000&&((d.q(c15:0x0047))&0x1)==0x0) group.quad c15:0x0047++0x01 line.quad 0x00 "PAR,Physical Address Register" hexmask.quad.byte 0x00 56.--63. 1. " ATTR ,Memory attributes for the returned PA" hexmask.quad 0x00 12.--39. 0x1000 " PA ,Physical Address" bitfld.quad 0x00 11. " LPAE ,Long-descriptor translation table format use" "Not used,Used" textline " " bitfld.quad 0x00 9. " NS ,Non-secure" "Secure,Non-secure" bitfld.quad 0x00 7.--8. " SH ,Shareability attribute" "Non-shareable,Unpredictable,Outer Shareable,Inner Shareable" bitfld.quad 0x00 0. " F ,Conversion completed successfully" "Successful,Unsuccessful" textline " " elif (((d.l(c15:0x202))&0x80000000)==0x80000000&&((d.q(c15:0x0047))&0x1)==0x1) group.quad c15:0x0047++0x01 line.quad 0x00 "PAR,Physical Address Register" bitfld.quad 0x00 11. " LPAE ,Long-descriptor translation table format use" "Not used,Used" bitfld.quad 0x00 9. " FSTAGE ,Translation stage at which the translation aborted" "Stage 1,Stage 2" bitfld.quad 0x00 8. " S2WLK ,Stage 2 fault during a stage 1 translation table walk" "Not occurred,Occurred" textline " " bitfld.quad 0x00 1.--6. " FS ,Fault status field" "Reserved,Reserved,Reserved,Reserved,Reserved,Translation fault/1st level,Translation fault/2nd level,Translation fault/3rd level,Reserved,Access flag fault/1st level,Access flag fault/2nd level,Access flag fault/3rd level,Reserved,Permission fault/1st level,Permission fault/2nd level,Permission fault/3rd level,Synchronous external abort,Asynchronous external abort,Reserved,Reserved,Reserved,Synchronous external abort on translation table walk/1st level,Synchronous external abort on translation table walk/2nd level,Synchronous external abort on translation table walk/3rd level,Synchronous parity error on memory access, Asynchronous parity error on memory access,Reserved,Reserved,Reserved,Synchronous parity error on memory access on translation table walk/1st lvl,Synchronous parity error on memory access on translation table walk/2nd lvl,Synchronous parity error on memory access on translation table walk/3rd lvl,Reserved,Alignment fault,Debug event,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict abort,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Domain fault/1st lvl,Domain fault/2nd lvl,Reserved" textline " " bitfld.quad 0x00 0. " F ,Conversion completed successfully" "Successful,Unsuccessful" textline " " elif (((d.l(c15:0x202))&0x80000000)==0x00&&((d.q(c15:0x0047))&0x1)==0x0) group.long c15:0x0047++0x00 line.long 0x00 "PAR,Physical Address Register" hexmask.long.tbyte 0x00 12.--31. 0x1000 " PA ,Physical Address" bitfld.long 0x00 11. " LPAE ,Long-descriptor translation table format use" "Not used,Used" bitfld.long 0x00 10. " NOS ,Not Outer Shareable attribute" "Outer shareable,Not outer shareable" textline " " bitfld.long 0x00 9. " NS ,Non-secure" "Secure,Non-secure" bitfld.long 0x00 7. " SH ,Shareability attribute" "Non-shareable,Shareable" bitfld.long 0x00 4.--6. " INNER ,Inner memory attributes" "Non-cacheable,Strongly-ordered,-,Device,-,Write-Back Write-Allocate,Write-Through,Write-Back no Write-Allocate" textline " " bitfld.long 0x00 2.--3. " OUTER ,Outer memory attributes" "Non-cacheable,Write-Back Write-Allocate,Write-Through no Write-Allocate,Write-Back no Write-Allocate" bitfld.long 0x00 1. " SS ,Supersection" "Not a Supersection,Supersection" bitfld.long 0x00 0. " F ,Conversion completed successfully" "Successful,Unsuccessful" textline " " elif (((d.l(c15:0x202))&0x80000000)==0x00&&((d.q(c15:0x0047))&0x1)==0x1) group.long c15:0x0047++0x00 line.long 0x00 "PAR,Physical Address Register" bitfld.long 0x00 11. " LPAE ,Long-descriptor translation table format use" "Not used,Used" textline " " bitfld.long 0x00 1.--6. " FS ,Fault status" "Reserved,Alignment fault,Debug event,Access flag fault/1st lvl,Fault on instruction cache maintenance,Translation fault/1st lvl,Access flag fault/2nd lvl,Translation fault/2nd lvl,Synchronous external abort,Domain fault/1st lvl,Reserved,Domain fault/2nd lvl,Synchronous external abort on translation table walk/1st lvl,Permission fault/1st lvl,Synchronous external abort on translation table walk/2nd lvl,Permission fault/2nd lvl,TLB conflict abort,Reserved,Reserved,Reserved,Reserved,Reserved,Asynchronous external abort,Reserved,Asynchronous parity error on memory access,Synchronous parity error on memory access,,,Synchronous parity error on translation table walk/1st lvl,Reserved,Synchronous parity error on translation table walk/2nd lvl,Reserved,?..." textline " " bitfld.long 0x00 0. " F ,Conversion completed successfully" "Successful,Unsuccessful" textline " " endif if (((d.l(c15:0x202))&0x80000000)==0x80000000) group.long c15:0x002A++0x00 line.long 0x00 "MAIR0,Memory Attribute Indirection Register 0" hexmask.long.byte 0x00 24.--31. 1. " ATTR3 ,Attribute 3" hexmask.long.byte 0x00 16.--23. 1. " ATTR2 ,Attribute 2" hexmask.long.byte 0x00 8.--15. 1. " ATTR1 ,Attribute 1" hexmask.long.byte 0x00 0.--7. 1. " ATTR0 ,Attribute 0" group.long c15:0x012A++0x00 line.long 0x00 "MAIR1,Memory Attribute Indirection Register 1" hexmask.long.byte 0x00 24.--31. 1. " ATTR7 ,Attribute 7" hexmask.long.byte 0x00 16.--23. 1. " ATTR6 ,Attribute 6" hexmask.long.byte 0x00 8.--15. 1. " ATTR5 ,Attribute 5" hexmask.long.byte 0x00 0.--7. 1. " ATTR4 ,Attribute 4" if (corename()=="CORTEXA15"||corename()=="CORTEXA15MPCORE") group.long c15:0x003A++0x00 line.long 0x00 "AMAIR0,Auxiliary Memory Attribute Indirection Register 0" hexmask.long.byte 0x00 24.--31. 1. " ATTR3 ,Attribute 3" hexmask.long.byte 0x00 16.--23. 1. " ATTR2 ,Attribute 2" hexmask.long.byte 0x00 8.--15. 1. " ATTR1 ,Attribute 1" textline " " hexmask.long.byte 0x00 0.--7. 1. " ATTR0 ,Attribute 0" group.long c15:0x013A++0x00 line.long 0x00 "AMAIR1,Auxiliary Memory Attribute Indirection Register 1" hexmask.long.byte 0x00 24.--31. 1. " ATTR7 ,Attribute 7" hexmask.long.byte 0x00 16.--23. 1. " ATTR6 ,Attribute 6" hexmask.long.byte 0x00 8.--15. 1. " ATTR5 ,Attribute 5" textline " " hexmask.long.byte 0x00 0.--7. 1. " ATTR4 ,Attribute 4" elif (corename()=="CORTEXA7"||corename()=="CORTEXA7MPCORE"||corename()=="CORTEXA17"||corename()=="CORTEXA17MPCORE") hgroup.long c15:0x003A++0x00 hide.long 0x00 "AMAIR0,Auxiliary Memory Attribute Indirection Register 0" hgroup.long c15:0x013A++0x00 hide.long 0x00 "AMAIR1,Auxiliary Memory Attribute Indirection Register 1" endif else group.long c15:0x002A++0x0 line.long 0x00 "PRRR,Primary Region Remap Register" bitfld.long 0x00 31. " NOS7 ,Outer Shareable property mapping for memory attributes" "Outer,Inner" bitfld.long 0x00 30. " NOS6 ,Outer Shareable property mapping for memory attributes" "Outer,Inner" bitfld.long 0x00 29. " NOS5 ,Outer Shareable property mapping for memory attributes" "Outer,Inner" textline " " bitfld.long 0x00 28. " NOS4 ,Outer Shareable property mapping for memory attributes" "Outer,Inner" bitfld.long 0x00 27. " NOS3 ,Outer Shareable property mapping for memory attributes" "Outer,Inner" bitfld.long 0x00 26. " NOS2 ,Outer Shareable property mapping for memory attributes" "Outer,Inner" textline " " bitfld.long 0x00 25. " NOS1 ,Outer Shareable property mapping for memory attributes" "Outer,Inner" bitfld.long 0x00 24. " NOS0 ,Outer Shareable property mapping for memory attributes" "Outer,Inner" bitfld.long 0x00 19. " NS1 ,Shareable Attribute Remap when S=1 for Normal Regions" "Remapped,Not remapped" textline " " bitfld.long 0x00 18. " NS0 ,Shareable Attribute Remap when S=0 for Normal Regions" "Not remapped,Remapped" bitfld.long 0x00 17. " DS1 ,Shareable Attribute Remap when S=1 for Device regions" "Remapped,Not remapped" bitfld.long 0x00 16. " DS0 ,Shareable Attribute Remap when S=0 for Device regions" "Not remapped,Remapped" textline " " bitfld.long 0x00 14.--15. " TR7 ,{TEX[0] C B} = b111 Remap" "Strongly ordered,Device,Normal,UNP" bitfld.long 0x00 12.--13. " TR6 ,{TEX[0] C B} = b110 Remap" "Strongly ordered,Device,Normal,UNP" bitfld.long 0x00 10.--11. " TR5 ,{TEX[0] C B} = b101 Remap" "Strongly ordered,Device,Normal,UNP" textline " " bitfld.long 0x00 8.--9. " TR4 ,{TEX[0] C B} = b100 Remap" "Strongly ordered,Device,Normal,UNP" bitfld.long 0x00 6.--7. " TR3 ,{TEX[0] C B} = b011 Remap" "Strongly ordered,Device,Normal,UNP" bitfld.long 0x00 4.--5. " TR2 ,{TEX[0] C B} = b010 Remap" "Strongly ordered,Device,Normal,UNP" textline " " bitfld.long 0x00 2.--3. " TR1 ,{TEX[0] C B} = b001 Remap" "Strongly ordered,Device,Normal,UNP" bitfld.long 0x00 0.--1. " TR0 ,{TEX[0] C B} = b000 Remap" "Strongly ordered,Device,Normal,UNP" group.long c15:0x012A++0x0 line.long 0x00 "NMRR,Normal Memory Remap Register" bitfld.long 0x00 30.--31. " OR7 ,Outer Attribute for {TEX[0] C B} = b111 Remap" "Noncacheable,Write-back allocate,Write-through no allocate,Write-back no allocate" bitfld.long 0x00 28.--29. " OR6 ,Outer Attribute for {TEX[0] C B} = b110 Remap" "Noncacheable,Write-back allocate,Write-through no allocate,Write-back no allocate" bitfld.long 0x00 26.--27. " OR5 ,Outer Attribute for {TEX[0] C B} = b101 Remap" "Noncacheable,Write-back allocate,Write-through no allocate,Write-back no allocate" textline " " bitfld.long 0x00 24.--25. " OR4 ,Outer Attribute for {TEX[0] C B} = b100 Remap" "Noncacheable,Write-back allocate,Write-through no allocate,Write-back no allocate" bitfld.long 0x00 22.--23. " OR3 ,Outer Attribute for {TEX[0] C B} = b011 Remap" "Noncacheable,Write-back allocate,Write-through no allocate,Write-back no allocate" bitfld.long 0x00 20.--21. " OR2 ,Outer Attribute for {TEX[0] C B} = b010 Remap" "Noncacheable,Write-back allocate,Write-through no allocate,Write-back no allocate" textline " " bitfld.long 0x00 18.--19. " OR1 ,Outer Attribute for {TEX[0] C B} = b001 Remap" "Noncacheable,Write-back allocate,Write-through no allocate,Write-back no allocate" bitfld.long 0x00 16.--17. " OR0 ,Outer Attribute for {TEX[0] C B} = b000 Remap" "Noncacheable,Write-back allocate,Write-through no allocate,Write-back no allocate" bitfld.long 0x00 14.--15. " IR7 ,Inner attribute for {TEX[0] C B} = b111 Remap" "Noncacheable,Write-back allocate,Write-through no allocate,Write-back no allocate" textline " " bitfld.long 0x00 12.--13. " IR6 ,Inner attribute for {TEX[0] C B} = b110 Remap" "Noncacheable,Write-back allocate,Write-through no allocate,Write-back no allocate" bitfld.long 0x00 10.--11. " IR5 ,Inner attribute for {TEX[0] C B} = b101 Remap" "Noncacheable,Write-back allocate,Write-through no allocate,Write-back no allocate" bitfld.long 0x00 8.--9. " IR4 ,Inner attribute for {TEX[0] C B} = b100 Remap" "Noncacheable,Write-back allocate,Write-through no allocate,Write-back no allocate" textline " " bitfld.long 0x00 6.--7. " IR3 ,Inner attribute for {TEX[0] C B} = b011 Remap" "Noncacheable,Write-back allocate,Write-through no allocate,Write-back no allocate" bitfld.long 0x00 4.--5. " IR2 ,Inner attribute for {TEX[0] C B} = b010 Remap" "Noncacheable,Write-back allocate,Write-through no allocate,Write-back no allocate" bitfld.long 0x00 2.--3. " IR1 ,Inner attribute for {TEX[0] C B} = b001 Remap" "Noncacheable,Write-back allocate,Write-through no allocate,Write-back no allocate" textline " " bitfld.long 0x00 0.--1. " IR0 ,Inner attribute for {TEX[0] C B} = b000 Remap" "Noncacheable,Write-back allocate,Write-through no allocate,Write-back no allocate" textline " " endif if (corename()=="CORTEXA7"||corename()=="CORTEXA7MPCORE"||corename()=="CORTEXA15"||corename()=="CORTEXA15MPCORE") group.long c15:0x400F++0x00 line.long 0x00 "CBAR,Configuration Base Address Register" hexmask.long.tbyte 0x00 15.--31. 0x80 " PERIPHBASE[31:15] ,Periphbase[31:15]" hexmask.long.byte 0x00 0.--7. 1. " PERIPHBASE[39:32] ,Periphbase[39:32]" elif (corename()=="CORTEXA17"||corename()=="CORTEXA17MPCORE") hgroup.long c15:0x400F++0x00 hide.long 0x00 "CBAR,Configuration Base Address Register" endif textline " " if (((d.l(c15:0x202))&0x80000000)==0x80000000) group.long c15:0x10d++0x00 line.long 0x0 "CONTEXTIDR,Context ID Register" else group.long c15:0x10d++0x00 line.long 0x0 "CONTEXTIDR,Context ID Register" hexmask.long.tbyte 0x00 8.--31. 1. " PROCID ,Process identifier" hexmask.long.byte 0x00 0.--7. 1. " ASID ,Address space identifier" endif group.long c15:0x020D++0x00 line.long 0x00 "TPIDRURW,User Read/Write Thread ID Register" group.long c15:0x030D++0x00 line.long 0x00 "TPIDRURO,User Read-Only Thread ID Register" group.long c15:0x040D++0x00 line.long 0x00 "TPIDRPRW,EL1 only Thread ID Register" group.long c15:0x420D++0x00 line.long 0x00 "HTPIDR,Hyp Software Thread ID Register" tree.end width 15. tree "Virtualization Extensions" group.long c15:0x4000++0x00 line.long 0x0 "VPIDR,Virtualization Processor ID Register" group.long c15:0x4500++0x00 line.long 0x0 "VMPIDR,Virtualization Multiprocessor ID Register" group.long c15:0x4001++0x00 line.long 0x00 "HSCTLR,System Control Register" bitfld.long 0x0 30. " TE ,Thumb exception enable" "ARM,Thumb" bitfld.long 0x0 25. " EE ,Exception endianness" "Little,Big" bitfld.long 0x0 19. " WXN ,Write permission implies XN" "Not forced,Forced" textline " " bitfld.long 0x0 12. " I ,Instruction Cache Enable" "Disabled,Enabled" bitfld.long 0x0 2. " C ,Enable unified cache or data cache" "Disabled,Enabled" bitfld.long 0x0 1. " A ,Strict Alignment" "Disabled,Enabled" textline " " bitfld.long 0x0 0. " M ,Enable address translation" "Disabled,Enabled" group.long c15:0x4011++0x00 line.long 0x00 "HCR,Hyp Configuration Register" bitfld.long 0x00 27. " TGE ,Trap General Exceptions" "Disabled,Enabled" bitfld.long 0x00 26. " TVM ,Trap Virtual Memory Controls" "Disabled,Enabled" bitfld.long 0x00 25. " TTLB ,Trap TLB maintenance instructions" "Disabled,Enabled" textline " " bitfld.long 0x00 24. " TPU ,Trap Cache maintenance instructions to point of unification" "Disabled,Enabled" bitfld.long 0x00 23. " TPC ,Trap Data/Unified cache maintenance instructions to point of coherency" "Disabled,Enabled" bitfld.long 0x00 22. " TSW ,Trap Data/Unified cache Set/Way instructions" "Disabled,Enabled" textline " " bitfld.long 0x00 21. " TAC ,Trap Auxiliary Control Register Accesses" "Disabled,Enabled" bitfld.long 0x00 20. " TIDCP ,Trap Lockdown" "Disabled,Enabled" bitfld.long 0x00 19. " TSC ,Trap SMC" "Disabled,Enabled" textline " " bitfld.long 0x00 18. " TID3 ,Trap ID Group 3" "Disabled,Enabled" bitfld.long 0x00 17. " TID2 ,Trap ID Group 2" "Disabled,Enabled" bitfld.long 0x00 16. " TID1 ,Trap ID Group 1" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " TID0 ,Trap ID Group 0" "Disabled,Enabled" bitfld.long 0x00 14. " TWE ,Trap WFE" "Disabled,Enabled" bitfld.long 0x00 13. " TWI ,Trap WFI" "Disabled,Enabled" textline " " bitfld.long 0x00 12. " DC ,Default Cacheable" "Disabled,Enabled" bitfld.long 0x00 10.--11. " BSU ,Barrier Shareability Upgrade" "No effect,Inner,Outer,Full system" bitfld.long 0x00 9. " FB ,Force Broadcast of TLB maintenance BPIALL and ICIALLU instructions" "Disabled,Enabled" textline " " bitfld.long 0x00 8. " VA ,Virtual External Asynchronous Abort" "Not aborted,Aborted" bitfld.long 0x00 7. " VI ,Virtual IRQ interrupt" "No interrupt,Interrupt" bitfld.long 0x00 6. " VF ,Virtual FIQ interrupt" "No interrupt,Interrupt" textline " " bitfld.long 0x00 5. " AMO ,A-bit Mask Override" "No override,Override" bitfld.long 0x00 4. " IMO ,I-bit Mask Override" "No override,Override" bitfld.long 0x00 3. " FMO ,F-bit Mask Override" "No override,Override" textline " " bitfld.long 0x00 2. " PTW ,Protected Table Walk" "Disabled,Enabled" bitfld.long 0x00 1. " SWIO ,Set/Way Invalidation Override" "No override,Override" bitfld.long 0x00 0. " VM ,Second Stage of Translation Enable" "Disabled,Enabled" group.long c15:0x4111++0x00 line.long 0x00 "HDCR,Hyp Debug Control Register" bitfld.long 0x00 11. " TDRA ,Trap Debug ROM Access" "No effect,Valid" bitfld.long 0x00 10. " TDOSA ,Trap Debug OS-related register Access" "No effect,Valid" bitfld.long 0x00 9. " TDA ,Trap Debug Access" "No effect,Valid" textline " " bitfld.long 0x00 8. " TDE ,Trap Debug Exceptions" "No effect,Valid" bitfld.long 0x00 7. " HPME ,Hypervisor Performance Monitors Enable" "Disabled,Enabled" bitfld.long 0x00 6. " TPM ,Trap Performance Monitors accesses" "No effect,Valid" textline " " bitfld.long 0x00 5. " TPMCR ,Trap Performance Monitor Control Register accesses" "No effect,Valid" bitfld.long 0x00 0.--4. " HPMN ,Defines the number of Performance Monitors counters" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long c15:0x4211++0x00 line.long 0x00 "HCPTR,Hyp Coprocessor Trap Register" bitfld.long 0x0 31. " TCPAC ,Trap Coprocessor Access Control" "Not trapped,Trapped" bitfld.long 0x0 15. " TASE ,Trap Advanced SIMD extensions" "Not trapped,Trapped" bitfld.long 0x0 11. " TCP11 ,Trap coprocessor 11" "Not trapped,Trapped" textline " " bitfld.long 0x0 10. " TCP10 ,Trap coprocessor 10" "Not trapped,Trapped" group.long c15:0x4025++0x00 line.long 0x00 "HSR,Hyp Syndrome Register" bitfld.long 0x00 26.--31. " EC ,Exception class" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 25. " IL ,Instruction length" "16-bit,32-bit" hexmask.long 0x00 0.--24. 1. " ISS ,Instruction specific syndrome" group.long c15:0x4311++0x00 line.long 0x00 "HSTR,Hyp System Trap Register" bitfld.long 0x00 17. " TJDBX ,Trap Jazelle-DBX" "Disabled,Enabled" bitfld.long 0x00 16. " TTEE ,Trap ThumbEE" "Disabled,Enabled" bitfld.long 0x00 15. " T15 ,Trap to Hyp mode Non-secure priv 15" "Not trapped,Trapped" textline " " bitfld.long 0x00 13. " T13 ,Trap to Hyp mode Non-secure priv 13" "Not trapped,Trapped" bitfld.long 0x00 12. " T12 ,Trap to Hyp mode Non-secure priv 12" "Not trapped,Trapped" bitfld.long 0x00 11. " T11 ,Trap to Hyp mode Non-secure priv 11" "Not trapped,Trapped" textline " " bitfld.long 0x00 10. " T10 ,Trap to Hyp mode Non-secure priv 10" "Not trapped,Trapped" bitfld.long 0x00 9. " T9 ,Trap to Hyp mode Non-secure priv 9" "Not trapped,Trapped" bitfld.long 0x00 8. " T8 ,Trap to Hyp mode Non-secure priv 8" "Not trapped,Trapped" textline " " bitfld.long 0x00 7. " T7 ,Trap to Hyp mode Non-secure priv 7" "Not trapped,Trapped" bitfld.long 0x00 6. " T6 ,Trap to Hyp mode Non-secure priv 6" "Not trapped,Trapped" bitfld.long 0x00 5. " T5 ,Trap to Hyp mode Non-secure priv 5" "Not trapped,Trapped" textline " " bitfld.long 0x00 3. " T3 ,Trap to Hyp mode Non-secure priv 3" "Not trapped,Trapped" bitfld.long 0x00 2. " T2 ,Trap to Hyp mode Non-secure priv 2" "Not trapped,Trapped" bitfld.long 0x00 1. " T1 ,Trap to Hyp mode Non-secure priv 1" "Not trapped,Trapped" textline " " bitfld.long 0x00 0. " T0 ,Trap to Hyp mode Non-secure priv 0" "Not trapped,Trapped" group.quad c15:0x14020++0x01 line.quad 0x00 "HTTBR,Hyp Translation Table Base Register" hexmask.quad 0x00 0.--39. 1. " BADDR ,Translation table base address" group.long c15:0x4202++0x00 line.long 0x00 "HTCR,Hyp Translation Control Register" bitfld.long 0x00 12.--13. " SH0 ,Shareability attributes for the memory associated with the translation table walks using HTTBR" "Non-shareable,Reserved,Outer Shareable,Inner Shareable" bitfld.long 0x00 10.--11. " ORGN0 ,Outer Cacheability attributes for the memory associated with the translation table walks using HTTBR" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable" textline " " bitfld.long 0x00 8.--9. " IRGN0 ,Inner Cacheability attributes for the memory associated with the translation table walks VTTBR" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable" textline " " bitfld.long 0x00 0.--3. " T0SZ ,The Size offset(four-bit signed integer) of the VTCR addressed region" "0,1,2,3,4,5,6,7,-8,-7,-6,-5,-4,-3,-2,-1" group.quad c15:0x16020++0x01 line.quad 0x00 "VTTBR,Virtualization Translation Table Base Register" hexmask.quad.byte 0x00 48.--55. 1. " VMID ,VMID for the translation table" hexmask.quad 0x00 0.--39. 1. " BADDR ,Translation table base address" group.long c15:0x4212++0x00 line.long 0x00 "VTCR,Virtualization Translation Control Register" bitfld.long 0x00 12.--13. " SH0 ,Shareability attributes for the memory associated with the translation table walks using VTTBR" "Non-shareable,Reserved,Outer Shareable,Inner Shareable" bitfld.long 0x00 10.--11. " ORGN0 ,Outer Cacheability attributes for the memory associated with the translation table walks using VTTBR" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable" textline " " bitfld.long 0x00 8.--9. " IRGN0 ,Inner Cacheability attributes for the memory associated with the translation table walks VTTBR" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable" textline " " bitfld.long 0x00 6.--7. " SL0 ,Starting Level for VTCR addressed region" "Second level,First level,Reserved,Reserved" bitfld.long 0x00 4. " S ,Sign extension bit" "0,1" bitfld.long 0x00 0.--3. " T0SZ ,The Size offset(four-bit signed integer) of the VTCR addressed region" "0,1,2,3,4,5,6,7,-8,-7,-6,-5,-4,-3,-2,-1" if (corename()=="CORTEXA15"||corename()=="CORTEXA15MPCORE") group.long c15:0x4015++0x00 line.long 0x00 "HADFSR,Hyp Auxiliary Data Fault Status Syndrome Register" bitfld.long 0x00 31. " VALID ,L1 or L2 ECC double bit error indicator" "No error,Error" hexmask.long.byte 0x00 24.--30. 1. " RAMID ,RAM identifier" bitfld.long 0x00 23. " L2E ,L2 Error" "No error,Error" textline " " bitfld.long 0x00 18.--22. " B/W ,Bank/Way" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.tbyte 0x00 0.--17. 1. " IND ,Index" endif group.long c15:0x4006++0x00 line.long 0x00 "HDFAR,Hyp Data Fault Address Register" group.long c15:0x4025++0x00 line.long 0x00 "HSR,Hyp Syndrome Register" bitfld.long 0x00 26.--31. " EC ,Exception class" "Unknown reason,Trapped WFI/WFE,Reserved,Trapped MCR/MRC to CP15,Trapped MCRR/MRRC to CP15,Trapped MCR/MRC to CP14,Trapped LDC/STC to CP14,Trapped Coprocessor Usage,Trapped MRC,Trapped Jazelle instruction,Trapped BXJ,Reserved,Trapped MRRC,Reserved,Reserved,Reserved,Reserved,SVC,HVC,Trapped SMC,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Entry into Hyp mode Instruction Abort,Executing within Hyp mode Instruction Abort,Reserved,Reserved,Entry into Hyp mode Data Abort,Executing within Hyp mode Data Abort,?..." textline " " bitfld.long 0x00 25. " IL ,Instruction length" "16-bit,32-bit" hexmask.long 0x00 0.--24. 1. " ISS ,Instruction specific syndrome" group.long c15:0x4206++0x00 line.long 0x00 "HIFAR,Hyp Instruction Fault Address Register" group.long c15:0x4406++0x00 line.long 0x00 "HPFAR,Hyp IPA Fault Address Register" hexmask.long 0x00 4.--31. 1. " FIPA ,Faulting IPA bits" textline " " hgroup.long c15:0x407++0x00 hide.long 0x00 "NOP,No Operation Register" in wgroup.long c15:0x17++0x00 line.long 0x00 "ICIALLUIS,Invalidate All Instruction Caches To PoU Inner Shareable Register" bitfld.long 0x00 30.--31. " WAY ,Cache way to invalidate or clean" "0,1,2,3" hexmask.long.byte 0x00 5.--10. 1. " SET ,Cache set to invalidate or clean" bitfld.long 0x00 1.--3. " LEVEL ,Cache level" "0,1,2,3,4,5,6,7" wgroup.long c15:0x617++0x00 line.long 0x00 "BPIALLIS,Invalidate Entire Branch Predictor Array Inner Shareable Register" bitfld.long 0x00 30.--31. " WAY ,Cache way to invalidate or clean" "0,1,2,3" hexmask.long.byte 0x00 5.--10. 1. " SET ,Cache set to invalidate or clean" bitfld.long 0x00 1.--3. " LEVEL ,Cache level" "0,1,2,3,4,5,6,7" wgroup.long c15:0x57++0x00 line.long 0x00 "ICIALLU,Invalidate Entire Instruction Cache Register" bitfld.long 0x00 30.--31. " WAY ,Cache way to invalidate or clean" "0,1,2,3" hexmask.long.byte 0x00 5.--10. 1. " SET ,Cache set to invalidate or clean" bitfld.long 0x00 1.--3. " LEVEL ,Cache level" "0,1,2,3,4,5,6,7" wgroup.long c15:0x157++0x00 line.long 0x00 "ICIMVAU,Invalidate Instruction Cache Line by VA to Point-of-Unification Register" bitfld.long 0x00 30.--31. " WAY ,Cache way to invalidate or clean" "0,1,2,3" hexmask.long.byte 0x00 5.--10. 1. " SET ,Cache set to invalidate or clean" bitfld.long 0x00 1.--3. " LEVEL ,Cache level" "0,1,2,3,4,5,6,7" wgroup.long c15:0x457++0x00 line.long 0x00 "CP15ISB,Instruction Synchronization Barrier Register" bitfld.long 0x00 30.--31. " WAY ,Cache way to invalidate or clean" "0,1,2,3" hexmask.long.byte 0x00 5.--10. 1. " SET ,Cache set to invalidate or clean" bitfld.long 0x00 1.--3. " LEVEL ,Cache level" "0,1,2,3,4,5,6,7" wgroup.long c15:0x657++0x00 line.long 0x00 "BPIALL,Invalidate Entire Branch Predictor Array (NOP) Register" bitfld.long 0x00 30.--31. " WAY ,Cache way to invalidate or clean" "0,1,2,3" hexmask.long.byte 0x00 5.--10. 1. " SET ,Cache set to invalidate or clean" bitfld.long 0x00 1.--3. " LEVEL ,Cache level" "0,1,2,3,4,5,6,7" wgroup.long c15:0x757++0x00 line.long 0x00 "BPIMVA,Invalidate MVA From Branch Predictors Register" bitfld.long 0x00 30.--31. " WAY ,Cache way to invalidate or clean" "0,1,2,3" hexmask.long.word 0x00 5.--15. 1. " SET ,Cache set to invalidate or clean" bitfld.long 0x00 1.--3. " LEVEL ,Cache level" "0,1,2,3,4,5,6,7" wgroup.long c15:0x167++0x00 line.long 0x00 "DCIMVAC,Invalidate Data Cache Line by VA to PoC Register" bitfld.long 0x00 30.--31. " WAY ,Cache way to invalidate or clean" "0,1,2,3" hexmask.long.byte 0x00 5.--10. 1. " SET ,Cache set to invalidate or clean" bitfld.long 0x00 1.--3. " LEVEL ,Cache level" "0,1,2,3,4,5,6,7" wgroup.long c15:0x267++0x00 line.long 0x00 "DCISW,Invalidate Data Cache Line by Set/Way Register" bitfld.long 0x00 30.--31. " WAY ,Cache way to invalidate or clean" "0,1,2,3" hexmask.long.byte 0x00 5.--10. 1. " SET ,Cache set to invalidate or clean" bitfld.long 0x00 1.--3. " LEVEL ,Cache level" "0,1,2,3,4,5,6,7" wgroup.long c15:0x0087++0x00 line.long 0x00 "ATS1CPR,Stage 1 current state PL1 read" wgroup.long c15:0x0187++0x00 line.long 0x00 "ATS1CPW,Stage 1 current state PL1 write" wgroup.long c15:0x0287++0x00 line.long 0x00 "ATS1CUR,Stage 1 current state unprivileged (PL0) read" wgroup.long c15:0x0387++0x00 line.long 0x00 "ATS1CUW,Stage 1 current state unprivileged (PL0) write" wgroup.long c15:0x0487++0x00 line.long 0x00 "ATS12NSOPR,Stages 1 and 2 Non-secure PL1 read" wgroup.long c15:0x0587++0x00 line.long 0x00 "ATS12NSOPW,Stages 1 and 2 Non-secure PL1 write" wgroup.long c15:0x0687++0x00 line.long 0x00 "ATS12NSOUR,Stages 1 and 2 Non-secure unprivileged (PL0) read" wgroup.long c15:0x0787++0x00 line.long 0x00 "ATS12NSOUW,Stages 1 and 2 Non-secure unprivileged (PL0) write" wgroup.long c15:0x1a7++0x00 line.long 0x00 "DCCMVAC,Clean Data Cache Line to PoC by VA Register" bitfld.long 0x00 30.--31. " WAY ,Cache way to invalidate or clean" "0,1,2,3" hexmask.long.byte 0x00 5.--10. 1. " SET ,Cache set to invalidate or clean" bitfld.long 0x00 1.--3. " LEVEL ,Cache level" "0,1,2,3,4,5,6,7" wgroup.long c15:0x2a7++0x00 line.long 0x00 "DCCSW,Clean Data Cache Line by Set/Way Register" bitfld.long 0x00 30.--31. " WAY ,Cache way to invalidate or clean" "0,1,2,3" hexmask.long.byte 0x00 5.--10. 1. " SET ,Cache set to invalidate or clean" bitfld.long 0x00 1.--3. " LEVEL ,Cache level" "0,1,2,3,4,5,6,7" wgroup.long c15:0x4a7++0x00 line.long 0x00 "CP15DSB,Data Synchronization Barrier Register" hexmask.long 0x00 5.--31. 0x20 " ADDRESS ,Address to invalidate or clean" wgroup.long c15:0x5a7++0x00 line.long 0x00 "CP15DMB,Data Memory Barrier Register" hexmask.long 0x00 5.--31. 0x20 " ADDRESS ,Address to invalidate or clean" wgroup.long c15:0x1b7++0x00 line.long 0x00 "DCCMVAU,Clean Data Or Unified Cache Line By VA To PoU Register" bitfld.long 0x00 30.--31. " WAY ,Cache way to invalidate or clean" "0,1,2,3" hexmask.long.byte 0x00 5.--10. 1. " SET ,Cache set to invalidate or clean" wgroup.long c15:0x1e7++0x00 line.long 0x00 "DCCIMVAC,Clean and Invalidate Data Cache Line by VA to PoC Register" bitfld.long 0x00 30.--31. " WAY ,Cache way to invalidate or clean" "0,1,2,3" hexmask.long.byte 0x00 5.--10. 1. " SET ,Cache set to invalidate or clean" wgroup.long c15:0x2e7++0x00 line.long 0x00 "DCCISW,Clean and Invalidate Data Cache Line by Set/Way Register" bitfld.long 0x00 30.--31. " WAY ,Cache way to invalidate or clean" "0,1,2,3" hexmask.long.byte 0x00 5.--10. 1. " SET ,Cache set to invalidate or clean" wgroup.long c15:0x4087++0x00 line.long 0x00 "ATS1HR,Address Translate Stage 1 Hyp mode Read" wgroup.long c15:0x4187++0x00 line.long 0x00 "ATS1HW,Address Translate Stage 1 Hyp mode Write" wgroup.long c15:0x0038++0x00 line.long 0x00 "TLBIALLIS,Invalidate entire TLB Inner Shareable" wgroup.long c15:0x0138++0x00 line.long 0x00 "TLBIMVAIS,Invalidate unified TLB entry by MVA Inner Shareable" wgroup.long c15:0x0238++0x00 line.long 0x00 "TLBIASIDIS,Invalidate unified TLB byASID match Inner Shareable" wgroup.long c15:0x0338++0x00 line.long 0x00 "TLBIMVAAIS,Invalidate unified TLB by MVA all ASID Inner Shareable" wgroup.long c15:0x0058++0x00 line.long 0x00 "ITLBIALL,Invalidate instruction TLB" wgroup.long c15:0x0158++0x00 line.long 0x00 "ITLBIMVA,Invalidate instruction TLB entry by MVA" wgroup.long c15:0x0258++0x00 line.long 0x00 "ITLBIASID,Invalidate instruction TLB by ASID match" wgroup.long c15:0x0068++0x00 line.long 0x00 "DTLBIALL,Invalidate data TLB" wgroup.long c15:0x0168++0x00 line.long 0x00 "DTLBIMVA,Invalidate data TLB entry by MVA" wgroup.long c15:0x0268++0x00 line.long 0x00 "DTLBIASID,Invalidate data TLB by ASID match" wgroup.long c15:0x0078++0x00 line.long 0x00 "TLBIALL,Invalidate unified TLB" wgroup.long c15:0x0178++0x00 line.long 0x00 "TLBIMVA,Invalidate unified TLB entry by MVA" wgroup.long c15:0x0278++0x00 line.long 0x00 "TLBIASID,Invalidate unified TLB byASID match" wgroup.long c15:0x0378++0x00 line.long 0x00 "TLBIMVAA,Invalidate unified TLB by MVA all ASID" wgroup.long c15:0x4038++0x00 line.long 0x00 "TLBIALLHIS,Invalidate entire Hyp unified TLB Inner Shareable" wgroup.long c15:0x4138++0x00 line.long 0x00 "TLBIMVAHIS,Invalidate Hyp unified TLB entry by MVA Inner Shareable" wgroup.long c15:0x4438++0x00 line.long 0x00 "TLBIALLNSNHIS,Invalidate entire Non-secure Non-Hyp unified TLB Inner Shareable" wgroup.long c15:0x4078++0x00 line.long 0x00 "TLBIALLH,Invalidate entire Hyp unified TLB" wgroup.long c15:0x4178++0x00 line.long 0x00 "TLBIMVAH,Invalidate Hyp unified TLB entry by MVA" wgroup.long c15:0x4478++0x00 line.long 0x00 "TLBIALLNSNH,Invalidate entire Non-secure Non-Hyp unified TLB" group.long c15:0x402A++0x00 line.long 0x00 "HMAIR0,Hyp Memory Attribute Indirection Register 0" hexmask.long.byte 0x00 24.--31. 1. " ATTR3 ,Attribute 3" hexmask.long.byte 0x00 16.--23. 1. " ATTR2 ,Attribute 2" hexmask.long.byte 0x00 8.--15. 1. " ATTR1 ,Attribute 1" textline " " hexmask.long.byte 0x00 0.--7. 1. " ATTR0 ,Attribute 0" group.long c15:0x412A++0x00 line.long 0x00 "HMAIR1,Hyp Memory Attribute Indirection Register 1" hexmask.long.byte 0x00 24.--31. 1. " ATTR7 ,Attribute 7" hexmask.long.byte 0x00 16.--23. 1. " ATTR6 ,Attribute 6" hexmask.long.byte 0x00 8.--15. 1. " ATTR5 ,Attribute 5" textline " " hexmask.long.byte 0x00 0.--7. 1. " ATTR4 ,Attribute 4" if (corename()=="CORTEXA15"||corename()=="CORTEXA15MPCORE") group.long c15:0x403A++0x00 line.long 0x00 "HAMAIR0,Hyp Auxiliary Memory Attribute Indirection Register 0" hexmask.long.byte 0x00 24.--31. 1. " ATTR3 ,Attribute 3" hexmask.long.byte 0x00 16.--23. 1. " ATTR2 ,Attribute 2" hexmask.long.byte 0x00 8.--15. 1. " ATTR1 ,Attribute 1" textline " " hexmask.long.byte 0x00 0.--7. 1. " ATTR0 ,Attribute 0" group.long c15:0x413A++0x00 line.long 0x00 "HAMAIR1,Hyp Auxiliary Memory Attribute Indirection Register 1" hexmask.long.byte 0x00 24.--31. 1. " ATTR7 ,Attribute 7" hexmask.long.byte 0x00 16.--23. 1. " ATTR6 ,Attribute 6" hexmask.long.byte 0x00 8.--15. 1. " ATTR5 ,Attribute 5" textline " " hexmask.long.byte 0x00 0.--7. 1. " ATTR4 ,Attribute 4" else hgroup.long c15:0x403A++0x00 hide.long 0x00 "HAMAIR0,Hyp Auxiliary Memory Attribute Indirection Register 0" hgroup.long c15:0x413A++0x00 hide.long 0x00 "HAMAIR1,Hyp Auxiliary Memory Attribute Indirection Register 1" endif group.long c15:0x400C++0x00 line.long 0x00 "HVBAR,Hyp Vector Base Address Register" hexmask.long 0x00 5.--31. 0x20 " HVBADDR ,Hyp Vector Base Address" tree.end width 12. tree "Cache Control and Configuration" if (corename()=="CORTEXA15"||corename()=="CORTEXA15MPCORE") rgroup.long c15:0x1100++0x0 line.long 0x0 "CLIDR,Cache Level ID Register" bitfld.long 0x00 27.--29. " LOUU ,Level of Unification Uniprocessor" "Reserved,Level 2,?..." bitfld.long 0x00 24.--26. " LOC ,Level of Coherency" "Reserved,Reserved,Level 3,?..." bitfld.long 0x00 21.--23. " LOUIS ,Level of Unification Inner Shareable" "Reserved,Level 2,?..." bitfld.long 0x00 18.--20. " CTYPE7 ,Cache type for levels 7" "No cache,?..." textline " " bitfld.long 0x00 15.--17. " CTYPE6 ,Cache type for levels 6" "No cache,?..." bitfld.long 0x00 12.--14. " CTYPE5 ,Cache type for levels 5" "No cache,?..." bitfld.long 0x00 9.--11. " CTYPE4 ,Cache type for levels 4" "No cache,?..." bitfld.long 0x00 6.--8. " CTYPE3 ,Cache type for levels 3" "No cache,?..." textline " " bitfld.long 0x00 3.--5. " CTYPE2 ,Cache type for levels 2" "Reserved,Reserved,Reserved,Reserved,Unified,?..." bitfld.long 0x00 0.--2. " CTYPE1 ,Cache type for levels 1" "Reserved,Reserved,Reserved,Separate I/D,?..." elif (corename()=="CORTEXA7"||corename()=="CORTEXA7MPCORE"||corename()=="CORTEXA17"||corename()=="CORTEXA17MPCORE") rgroup.long c15:0x1100++0x0 line.long 0x0 "CLIDR,Cache Level ID Register" bitfld.long 0x00 27.--29. " LOUU ,Level of Unification Uniprocessor" "Reserved,Level 2,?..." bitfld.long 0x00 24.--26. " LOC ,Level of Coherency" "Reserved,Reserved,Level 3,?..." bitfld.long 0x00 21.--23. " LOUIS ,Level of Unification Inner Shareable" "Reserved,Level 2,?..." textline " " bitfld.long 0x00 3.--5. " CTYPE2 ,Cache type for levels 2" "Not implemented,Reserved,Reserved,Reserved,Unified,?..." bitfld.long 0x00 0.--2. " CTYPE1 ,Cache type for levels 1" "Reserved,Reserved,Reserved,Separate I/D,?..." endif if (corename()=="CORTEXA15"||corename()=="CORTEXA15MPCORE") rgroup.long c15:0x1000++0x0 line.long 0x0 "CCSIDR,Current Cache Size ID Register" bitfld.long 0x00 31. " WT ,Write-Through" "Not Supported,Supported" bitfld.long 0x00 30. " WB ,Write-Back" "Not Supported,Supported" bitfld.long 0x00 29. " RA ,Read-Allocate" "Not Supported,Supported" textline " " bitfld.long 0x00 28. " WA ,Write-Allocate" "Not Supported,Supported" hexmask.long.word 0x00 13.--27. 1. " SETS ,Number of Sets" hexmask.long.word 0x00 3.--12. 1. " ASSOC ,Associativity" textline " " bitfld.long 0x00 0.--2. " LSIZE ,Line Size" "Reserved,Reserved,16 words,?..." elif (corename()=="CORTEXA7"||corename()=="CORTEXA7MPCORE"||corename()=="CORTEXA17"||corename()=="CORTEXA17MPCORE") rgroup.long c15:0x1000++0x0 line.long 0x0 "CCSIDR,Current Cache Size ID Register" bitfld.long 0x00 31. " WT ,Write-Through" "Not Supported,Supported" bitfld.long 0x00 30. " WB ,Write-Back" "Not Supported,Supported" bitfld.long 0x00 29. " RA ,Read-Allocate" "Not Supported,Supported" textline " " bitfld.long 0x00 28. " WA ,Write-Allocate" "Not Supported,Supported" hexmask.long.word 0x00 13.--27. 1. " NUMSETS ,Number of Sets" hexmask.long.word 0x00 3.--12. 1. " ASSOC ,Associativity" textline " " bitfld.long 0x00 0.--2. " LSIZE ,Line Size" "Reserved,8 words,16 words,?..." endif group.long c15:0x2000++0x0 line.long 0x0 "CSSELR,Cache Size Selection Register" bitfld.long 0x00 1.--3. " LEVEL ,Cache level of required cache" "Level 1,Level 2,?..." bitfld.long 0x00 0. " IND ,Instruction/Not Data" "Data/Unified,Instruction" if (corename()=="CORTEXA17"||corename()=="CORTEXA17MPCORE") wgroup.long c15:0x10EF++0x00 line.long 0x00 "DCCIALL,Data Cache Clean and Invalidate All Register" bitfld.long 0x00 1.--2. " LEVEL ,Cache level" "L1,L2,Reserved,Reserved" else hgroup.long c15:0x10EF++0x00 hide.long 0x00 "DCCIALL,Data Cache Clean and Invalidate All Register" endif tree "Level 1 memory system" width 10. if (corename()=="CORTEXA15"||corename()=="CORTEXA15MPCORE") group.long c15:0x000F++0x00 line.long 0x00 "IL1DATA0,Instruction L1 Data 0 Register" group.long c15:0x010F++0x00 line.long 0x00 "IL1DATA1,Instruction L1 Data 1 Register" group.long c15:0x020F++0x00 line.long 0x00 "IL1DATA2,Instruction L1 Data 2 Register" group.long c15:0x001F++0x00 line.long 0x00 "DL1DATA0,Data L1 Data 0 Register" group.long c15:0x011F++0x00 line.long 0x00 "DL1DATA1,Data L1 Data 1 Register" group.long c15:0x021F++0x00 line.long 0x00 "DL1DATA2,Data L1 Data 2 Register" group.long c15:0x031F++0x00 line.long 0x00 "DL1DATA3,Data L1 Data 3 Register" wgroup.long c15:0x004F++0x00 line.long 0x00 "RAMINDEX,RAM Index Register" hexmask.long.byte 0x00 24.--31. 1. " RAMID ,RAM identifier" bitfld.long 0x00 18.--21. " B/W ,Bank/Way" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.tbyte 0x00 0.--17. 1. " IND ,Index" textline " " group.quad c15:0x100F0++0x01 line.quad 0x00 "CPUMERRSR,CPU Memory Error Syndrome Register" bitfld.quad 0x00 63. " FATAL ,Fatal bit" "0,1" hexmask.quad.byte 0x00 40.--47. 1. " OEC ,Other error count" hexmask.quad.byte 0x00 32.--39. 1. " REC ,Repeat error count" bitfld.quad 0x00 31. " VALID ,Valid bit" "Not valid,Valid" textline " " hexmask.quad.byte 0x00 24.--30. 1. " RAMID ,RAM Identifier" bitfld.quad 0x00 18.--22. " B/W ,Bank/Way" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.quad.tbyte 0x00 0.--17. 1. " IND ,Index" elif (corename()=="CORTEXA7"||corename()=="CORTEXA7MPCORE") rgroup.long c15:0x300F++0x0 line.long 0x00 "CDBGDR0,Data Register 0" rgroup.long c15:0x310F++0x0 line.long 0x00 "CDBGDR1,Data Register 1" rgroup.long c15:0x320F++0x0 line.long 0x00 "CDBGDR2,Data Register 2" wgroup.long c15:0x302F++0x0 line.long 0x00 "CDBGDCT,Data Cache Tag Read Operation Register" bitfld.long 0x00 30.--31. " CW ,Cache Way" "0,1,2,3" hexmask.long.tbyte 0x00 6.--29. 1. " SI ,Set index" bitfld.long 0x00 3.--5. " CWDO ,Cache word data offset" "0,1,2,3,4,5,6,7" wgroup.long c15:0x312F++0x0 line.long 0x00 "CDBGICT,Instruction Cache Tag Read Operation Register" bitfld.long 0x00 31. " CW ,Cache Way" "Low,High" hexmask.long 0x00 5.--30. 1. " SI ,Set index" bitfld.long 0x00 2.--4. " CDEO ,Cache data element offset" "0,1,2,3,4,5,6,7" wgroup.long c15:0x304F++0x0 line.long 0x00 "CDBGDCD,Data Cache Data Read Operation Register" bitfld.long 0x00 30.--31. " CW ,Cache Way" "0,1,2,3" hexmask.long.tbyte 0x00 6.--29. 1. " SI ,Set index" bitfld.long 0x00 3.--5. " CWDO ,Cache word data offset" "0,1,2,3,4,5,6,7" wgroup.long c15:0x314F++0x0 line.long 0x00 "CDBGICD,Instruction Cache Data Read Operation Register" bitfld.long 0x00 31. " CW ,Cache Way" "Low,High" hexmask.long 0x00 5.--30. 1. " SI ,Set index" bitfld.long 0x00 2.--4. " CDEO ,Cache data element offset" "0,1,2,3,4,5,6,7" wgroup.long c15:0x324F++0x0 line.long 0x00 "CDBGTD,TLB Data Read Operation Register" bitfld.long 0x00 31. " TLB_WAY ,TLB Way" "Low,High" hexmask.long.byte 0x00 0.--7. 1. " TLB_IND ,TLB index" elif (corename()=="CORTEXA17"||corename()=="CORTEXA17MPCORE") rgroup.long c15:0x300F++0x0 line.long 0x00 "CDBGDR0,Data Register 0" bitfld.long 0x00 31. " PMOESID ,Partial MOESI state / Dirty" "Low,High" bitfld.long 0x00 30. " POMA ,Partial Outer memory attribute" "Low,High" bitfld.long 0x00 29. " PMOESIE ,Partial MOESI state / Exclusive" "Low,High" textline " " bitfld.long 0x00 28. " PMOESIV ,Partial MOESI state / Valid" "Low,High" bitfld.long 0x00 27. " NS ,Non-Secure state" "Low,High" hexmask.long 0x00 0.--26. 1. " TA ,Tag Address" rgroup.long c15:0x310F++0x0 line.long 0x00 "CDBGDR1,Data Register 1" bitfld.long 0x00 0. " PMOESID ,Partial MOESI state / Globally shared" "Low,High" rgroup.long c15:0x320F++0x0 line.long 0x00 "CDBGDR2,Data Register 2" wgroup.long c15:0x302F++0x0 line.long 0x00 "CDBGDCT,Data Cache Tag Read Operation Register" bitfld.long 0x00 30.--31. " CW ,Cache Way" "0,1,2,3" hexmask.long.byte 0x00 6.--12. 1. " SI ,Set index" wgroup.long c15:0x312F++0x0 line.long 0x00 "CDBGICT,Instruction Cache Tag Read Operation Register" bitfld.long 0x00 30.--31. " CW ,Cache Way" "0,1,2,3" hexmask.long 0x00 6.--30. 1. " SI ,Set index" wgroup.long c15:0x304F++0x0 line.long 0x00 "CDBGDCD,Data Cache Data Read Operation Register" bitfld.long 0x00 30.--31. " CW ,Cache Way" "0,1,2,3" hexmask.long.byte 0x00 6.--12. 1. " SI ,Set index" bitfld.long 0x00 3.--5. " CDDO ,Cache doubleword data offset" "0,1,2,3,4,5,6,7" if (((d.l(c15:0x1000))&0xFFFE000)==0x1DE000) wgroup.long c15:0x314F++0x0 line.long 0x00 "CDBGICD,Instruction Cache Data Read Operation Register" bitfld.long 0x00 30.--31. " CW ,Cache Way" "0,1,2,3" hexmask.long.byte 0x00 6.--12. 1. " SI ,Set index" bitfld.long 0x00 3.--5. " CDDO ,Cache doubleword data offset" "0,1,2,3,4,5,6,7" elif (((d.l(c15:0x1000))&0xFFFE000)==0x1FE000&&((d.l(c15:0x2000))&0x3)==0x1) wgroup.long c15:0x314F++0x0 line.long 0x00 "CDBGICD,Instruction Cache Data Read Operation Register" bitfld.long 0x00 30.--31. " CW ,Cache Way" "0,1,2,3" hexmask.long.byte 0x00 6.--13. 1. " SI ,Set index" bitfld.long 0x00 3.--5. " CDDO ,Cache doubleword data offset" "0,1,2,3,4,5,6,7" elif (((d.l(c15:0x1000))&0xFFFE000)==0x1FE000&&((d.l(c15:0x2000))&0x3)==0x2) wgroup.long c15:0x314F++0x0 line.long 0x00 "CDBGICD,Instruction Cache Data Read Operation Register" bitfld.long 0x00 30.--31. " CW ,Cache Way" "0,1,2,3" hexmask.long.word 0x00 6.--15. 1. " SI ,Set index" bitfld.long 0x00 3.--5. " CDDO ,Cache doubleword data offset" "0,1,2,3,4,5,6,7" elif (((d.l(c15:0x1000))&0xFFFE000)==0x3FE000) wgroup.long c15:0x314F++0x0 line.long 0x00 "CDBGICD,Instruction Cache Data Read Operation Register" bitfld.long 0x00 30.--31. " CW ,Cache Way" "0,1,2,3" hexmask.long.word 0x00 6.--16. 1. " SI ,Set index" bitfld.long 0x00 3.--5. " CDDO ,Cache doubleword data offset" "0,1,2,3,4,5,6,7" elif (((d.l(c15:0x1000))&0xFFFE000)==0x7FE000) wgroup.long c15:0x314F++0x0 line.long 0x00 "CDBGICD,Instruction Cache Data Read Operation Register" bitfld.long 0x00 30.--31. " CW ,Cache Way" "0,1,2,3" hexmask.long.word 0x00 6.--17. 1. " SI ,Set index" bitfld.long 0x00 3.--5. " CDDO ,Cache doubleword data offset" "0,1,2,3,4,5,6,7" elif (((d.l(c15:0x1000))&0xFFFE000)==0xFFE000) wgroup.long c15:0x314F++0x0 line.long 0x00 "CDBGICD,Instruction Cache Data Read Operation Register" bitfld.long 0x00 30.--31. " CW ,Cache Way" "0,1,2,3" hexmask.long.word 0x00 6.--18. 1. " SI ,Set index" bitfld.long 0x00 3.--5. " CDDO ,Cache doubleword data offset" "0,1,2,3,4,5,6,7" elif (((d.l(c15:0x1000))&0xFFFE000)==0x1FFE000) wgroup.long c15:0x314F++0x0 line.long 0x00 "CDBGICD,Instruction Cache Data Read Operation Register" bitfld.long 0x00 30.--31. " CW ,Cache Way" "0,1,2,3" hexmask.long.word 0x00 6.--19. 1. " SI ,Set index" bitfld.long 0x00 3.--5. " CDDO ,Cache doubleword data offset" "0,1,2,3,4,5,6,7" elif (((d.l(c15:0x1000))&0xFFFE000)==0x3FFE000) wgroup.long c15:0x314F++0x0 line.long 0x00 "CDBGICD,Instruction Cache Data Read Operation Register" bitfld.long 0x00 30.--31. " CW ,Cache Way" "0,1,2,3" hexmask.long.word 0x00 6.--20. 1. " SI ,Set index" bitfld.long 0x00 3.--5. " CDDO ,Cache doubleword data offset" "0,1,2,3,4,5,6,7" else hgroup.long c15:0x314F++0x0 hide.long 0x00 "CDBGICD,Instruction Cache Data Read Operation Register" endif if (((d.l(c15:0x324F))&0x100)==0x100) wgroup.long c15:0x324F++0x0 line.long 0x00 "CDBGTD,TLB Data Read Operation Register" bitfld.long 0x00 8. " TYPE ,Type" "RAM0,RAM1" else wgroup.long c15:0x324F++0x0 line.long 0x00 "CDBGTD,TLB Data Read Operation Register" bitfld.long 0x00 30.--31. " TLB_WAY ,TLB Way" "0,1,2,3" bitfld.long 0x00 8. " TYPE ,Type" "RAM0,RAM1" hexmask.long.byte 0x00 0.--7. 1. " TLB_IND ,TLB index" endif endif tree.end tree "Level 2 memory system" width 11. if (corename()=="CORTEXA15"||corename()=="CORTEXA15MPCORE") group.long c15:0x1209++0x0 line.long 0x00 "L2CTLR,L2 Control Register" rbitfld.long 0x00 31. " L2RSTDISABLE ,L2 hardware reset disable pin monitor" "No,Yes" bitfld.long 0x00 24.--25. " NCPU , Number of CPU" "1,2,3,4" bitfld.long 0x00 23. " IE ,Interrupt Controller" "Not present,Present" textline " " bitfld.long 0x00 21. " ECCPE ,ECC and parity enable" "Disabled,Enabled" bitfld.long 0x00 12. " TRAMS ,L2 Tag RAM setup" "0 cycle,1 cycle" bitfld.long 0x00 10.--11. " DRAMSLICE ,Data RAM slice" "0,1,2,Invalid" textline " " bitfld.long 0x00 9. " TRAMS ,L2 Tag RAM setup" "0 cycle,1 cycle" bitfld.long 0x00 6.--8. " TRAML ,L2 Tag RAM latency" "2 cycles,2 cycles,3 cycles,4 cycles,5 cycles,5 cycles,5 cycles,5 cycles" bitfld.long 0x00 5. " DRAMS ,L2 Data RAM setup" "0 cycle,1 cycle" textline " " bitfld.long 0x00 0.--2. " DRAML ,L2 Data RAM latency" "2 cycles,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles" elif (corename()=="CORTEXA7"||corename()=="CORTEXA7MPCORE") group.long c15:0x1209++0x0 line.long 0x00 "L2CTLR,L2 Control Register" bitfld.long 0x00 24.--25. " NCPU ,Number of CPU" "1,2,3,4" bitfld.long 0x00 23. " IE ,Interrupt Controller" "Not present,Present" bitfld.long 0x00 0. " DRAML ,L2 data RAM latency" "2 cycles,3 cycles" elif (corename()=="CORTEXA17"||corename()=="CORTEXA17MPCORE") group.long c15:0x1209++0x0 line.long 0x00 "L2CTLR,L2 Control Register" rbitfld.long 0x00 31. " L2RSTDISABLE ,L2 hardware reset disable pin monitor" "No,Yes" bitfld.long 0x00 27.--30. " IWINC ,Controls index incrementation method" "1.,1.,3.,7.,15.,31.,63.,127.,255.,511.,1023.,2047.,4095.,8191.,8191.,8191." rbitfld.long 0x00 24.--25. " NCPU , Number of CPU" "1,2,3,4" bitfld.long 0x00 20. " SFEN , Snoop Filter Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " L2ECCD ,L2 ECC Disable" "No,Yes" bitfld.long 0x00 18. " L2CD ,L2 cache disable" "No,Yes" bitfld.long 0x00 15.--17. " TRAMSL ,Tag RAM setup latency" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles" bitfld.long 0x00 12.--14. " TRAMRL ,Tag RAM read latency" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles" textline " " bitfld.long 0x00 9.--11. " TRAMWL ,Tag RAM write latency" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles" bitfld.long 0x00 6.--8. " DRAMSL ,Data RAM setup latency" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles" bitfld.long 0x00 3.--5. " DRAMRL ,Data RAM read latency" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles" bitfld.long 0x00 0.--2. " DRAMWL ,Data RAM write latency" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles" endif if (corename()=="CORTEXA15"||corename()=="CORTEXA15MPCORE") group.long c15:0x1309++0x0 line.long 0x00 "L2ECTLR,L2 Extended Control Register" bitfld.long 0x00 30. " L2INTASYNCERR ,L2 internal asynchronous error" "No error,Error" bitfld.long 0x00 29. " AXIASYNCERR ,AXI asynchronous error" "No error,Error" group.long c15:0x100F++0x00 line.long 0x00 "L2ACTLR,L2 Auxiliary Control Register" bitfld.long 0x00 28. " FL2TBCEA ,Forces L2 tag bank clock enable active" "Not forced,Forced" bitfld.long 0x00 27. " FL2LCEA ,Forces L2 logic clock enable active" "Not forced,Forced" bitfld.long 0x00 26. " EL2GTRCG ,Enables L2 GIC and Timer regional clock gates" "Disabled,Enabled" textline " " bitfld.long 0x00 16. " ERTSI ,Enables replay threshold single issue" "Disabled,Enabled" bitfld.long 0x00 15. " ECWRM ,Enable CPU WFI retention mode" "Disabled,Enabled" bitfld.long 0x00 14. " EUCE ,Enables UniqueClean evictions with data" "Disabled,Enabled" textline " " bitfld.long 0x00 13. " DSCDT ,Disables SharedClean data transfers" "No,Yes" bitfld.long 0x00 12. " DWCWBE ,Disable multiple outstanding WriteClean/WriteBack/Evicts using the same AWID" "No,Yes" bitfld.long 0x00 11. " DDSB ,Disables DSB with no DVM synchronization" "No,Yes" textline " " bitfld.long 0x00 10. " DNSDAR ,Disables non-secure debug array read" "No,Yes" bitfld.long 0x00 9. " EPF ,Enable use of Prefetch bit in L2 cache replacement algorithm" "Disabled,Enabled" bitfld.long 0x00 8. " DDVMCMOMB ,Disables Distributed Virtual Memory (DVM) transactions and cache maintenance operation message broadcast" "No,Yes" textline " " bitfld.long 0x00 7. " EHDT ,Enables hazard detect timeout" "Disabled,Enabled" bitfld.long 0x00 6. " DSTFM ,Disables shared transactions from master" "No,Yes" bitfld.long 0x00 4. " DWUAWLUTFM ,Disables WriteUnique and WriteLineUnique transactions from master" "No,Yes" textline " " bitfld.long 0x00 3. " DCEPTE ,Disables clean/evict push to external" "No,Yes" bitfld.long 0x00 2. " LTORPTB ,Limit to one request per tag bank" "Disabled,Enabled" bitfld.long 0x00 1. " EARTT ,Enable arbitration replay threshold timeout" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " DPF ,Disable prefetch forwarding" "No,Yes" group.long c15:0x130F++0x00 line.long 0x00 "L2PFR,L2 Prefetch Control Register" bitfld.long 0x00 12. " DDTOLSPR ,Disable dynamic throttling of load/store prefetch requests" "No,Yes" bitfld.long 0x00 11. " EPRFRUT ,Enable prefetch request from ReadUnique transactions" "Disabled,Enabled" bitfld.long 0x00 10. " DTWDAP ,Disable table walk descriptor access prefetch" "No,Yes" textline " " bitfld.long 0x00 7.--8. " L2IFPD ,L2 instruction fetch prefetch distance" "0 lines,1 line,2 lines,3 lines" bitfld.long 0x00 4.--5. " L2LSDPD ,L2 load/store data prefetch distance" "0 lines,2 lines,4 lines,8 lines" textline " " group.quad c15:0x110F0++0x01 line.quad 0x00 "L2MERRSR,L2 Memory Error Syndrome Register" bitfld.quad 0x00 63. " FATAL ,Fatal bit" "0,1" hexmask.quad.byte 0x00 40.--47. 1. " OEC ,Other error count" hexmask.quad.byte 0x00 32.--39. 1. " REC ,Repeat error count" bitfld.quad 0x00 31. " VALID ,Valid bit" "Not valid,Valid" textline " " hexmask.quad.byte 0x00 24.--30. 1. " RAMID ,RAM Identifier" bitfld.quad 0x00 18.--21. " C/W ,CPUID/Way" "CPU0 tag way 0,CPU0 tag way 1,CPU1 tag way 0,CPU1 tag way 1,CPU2 tag way 0,CPU2 tag way 1,CPU3 tag way 0,CPU3 tag way 1,?..." hexmask.quad.tbyte 0x00 0.--17. 1. " IND ,Index" elif (corename()=="CORTEXA7"||corename()=="CORTEXA7MPCORE") group.long c15:0x1309++0x0 line.long 0x00 "L2ECTLR,L2 Extended Control Register" bitfld.long 0x00 29. " AXIASYNCERR ,AXI asynchronous error" "No error,Error" hgroup.quad c15:0x110F0++0x01 hide.quad 0x00 "L2MERRSR,L2 Memory Error Syndrome Register" elif (corename()=="CORTEXA17"||corename()=="CORTEXA17MPCORE") group.long c15:0x1309++0x0 line.long 0x00 "L2ECTLR,L2 Extended Control Register" bitfld.long 0x00 30. " ECCUNERR ,ECC uncorrectable error " "No error,Error" bitfld.long 0x00 29. " AXIASYNCERR ,AXI asynchronous error" "No error,Error" bitfld.long 0x00 0. " L2DRC ,Disable L2 retention" "No,Yes" rgroup.long c15:0x1609++0x00 line.long 0x00 "L2MRERRSR,L2 Memory Error Syndrome Register" bitfld.long 0x00 31. " FATAL ,Fatal bit" "0,1" bitfld.long 0x00 25.--30. " OEC ,Other error count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 19.--24. " REC ,Repeat error count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.word 0x00 6.--18. 1. " ERRLIND ,Index Error Location" textline " " bitfld.long 0x00 2.--5. " ERRLWAY ,Way Error Location" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 1. " RAMID ,RAM Identifier" "TAG,DATA" bitfld.long 0x00 0. " VALID ,Valid bit" "Not valid,Valid" endif tree.end tree.end width 12. tree "System Performance Monitor" group.long c15:0xc9++0x00 line.long 0x0 "PMCR,Performance Monitor Control Register" hexmask.long.byte 0x00 24.--31. 1. " IMP ,Implementer code" hexmask.long.byte 0x00 16.--23. 1. " IDCODE ,Identification code" bitfld.long 0x00 11.--15. " N ,Number of counters implemented" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 5. " DP ,Disable CCNT when prohibited" "No,Yes" bitfld.long 0x00 4. " X ,Export Enable" "Disabled,Enabled" bitfld.long 0x00 3. " D ,Clock Divider" "Every cycle,64th cycle" textline " " bitfld.long 0x00 2. " C ,Clock Counter Reset" "No reset,Reset" bitfld.long 0x00 1. " P ,Performance Counter Reset" "No reset,Reset" bitfld.long 0x00 0. " E ,All Counters Enable" "Disabled,Enabled" group.long c15:0x1c9++0x00 line.long 0x00 "PMNCNTENSET,Count Enable Set Register " bitfld.long 0x00 5. " P5 ,Event Counter 5 enable bit" "Disabled,Enabled" bitfld.long 0x00 4. " P4 ,Event Counter 4 enable bit" "Disabled,Enabled" bitfld.long 0x00 3. " P3 ,Event Counter 3 enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " P2 ,Event Counter 2 enable bit" "Disabled,Enabled" bitfld.long 0x00 1. " P1 ,Event Counter 1 enable bit" "Disabled,Enabled" bitfld.long 0x00 0. " P0 ,Event Counter 0 enable bit" "Disabled,Enabled" group.long c15:0x2c9++0x00 line.long 0x00 "PMCNTENCLR,Count Enable Clear Register" eventfld.long 0x00 5. " P5 ,Event Counter 5 clear bit" "Disabled,Enabled" eventfld.long 0x00 4. " P4 ,Event Counter 4 clear bit" "Disabled,Enabled" eventfld.long 0x00 3. " P3 ,Event Counter 3 clear bit" "Disabled,Enabled" textline " " eventfld.long 0x00 2. " P2 ,Event Counter 2 clear bit" "Disabled,Enabled" eventfld.long 0x00 1. " P1 ,Event Counter 1 clear bit" "Disabled,Enabled" eventfld.long 0x00 0. " P0 ,Event Counter 0 clear bit" "Disabled,Enabled" group.long c15:0x3c9++0x00 line.long 0x00 "PMOVSR,Performance Monitor Overflow Status Register" eventfld.long 0x00 5. " P5 ,PMN5 overflow" "No overflow,Overflow" eventfld.long 0x00 4. " P4 ,PMN4 overflow" "No overflow,Overflow" eventfld.long 0x00 3. " P3 ,PMN3 overflow" "No overflow,Overflow" textline " " eventfld.long 0x00 2. " P2 ,PMN2 overflow" "No overflow,Overflow" eventfld.long 0x00 1. " P1 ,PMN1 overflow" "No overflow,Overflow" eventfld.long 0x00 0. " P0 ,PMN0 overflow" "No overflow,Overflow" group.long c15:0x4c9++0x00 line.long 0x00 "PMSWINC,Performance Monitor Software Increment" bitfld.long 0x00 5. " P5 ,Increment PMN5" "No action,Increment" bitfld.long 0x00 4. " P4 ,Increment PMN4" "No action,Increment" bitfld.long 0x00 3. " P3 ,Increment PMN3" "No action,Increment" textline " " bitfld.long 0x00 2. " P2 ,Increment PMN2" "No action,Increment" bitfld.long 0x00 1. " P1 ,Increment PMN1" "No action,Increment" bitfld.long 0x00 0. " P0 ,Increment PMN0" "No action,Increment" group.long c15:0x5c9++0x00 line.long 0x00 "PMSELR,Performance Monitor Select Register" bitfld.long 0x00 0.--4. " SEL ,Current event counter select" "0,1,2,3,4,5,?..." group.long c15:0xd9++0x00 line.long 0x00 "PMCCNTR,Performance Monitor Cycle Count Register" group.long c15:0x1d9++0x00 line.long 0x00 "PMXEVTYPER,Performance Monitor Event Type Register" bitfld.long 0x00 31. " P ,Execution at PL1 events counting disable" "No,Yes" bitfld.long 0x00 30. " U ,Execution at PL0 events counting disable" "No,Yes" bitfld.long 0x00 29. " NSK ,Execution in Non-secure state at PL1 events counting disable" "No,Yes" bitfld.long 0x00 28. " NSU ,Execution in Non-secure state at PL0 events counting disable" "No,Yes" textline " " bitfld.long 0x00 27. " NSH ,Execution in Non-secure state at PL2 events counting enable" "Disabled,Enabled" hexmask.long.byte 0x00 0.--7. 1. " EVTCOUNT ,Event to count" group.long c15:0x2d9++0x00 line.long 0x00 "PMXEVCNTR,Performance Monitor Event Count Register" group.long c15:0xe9++0x00 line.long 0x00 "PMUSERENR,Performance Monitor User Enable Register" bitfld.long 0x00 0. " EN ,User mode access enable" "Disabled,Enabled" group.long c15:0x1e9++0x00 line.long 0x00 "PMINTENSET,Performance Monitor Interrupt Enable Set" bitfld.long 0x00 5. " P5 ,PMCNT5 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4. " P4 ,PMCNT4 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 3. " P3 ,PMCNT3 Overflow Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " P2 ,PMCNT2 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 1. " P1 ,PMCNT1 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 0. " P0 ,PMCNT0 Overflow Interrupt Enable" "Disabled,Enabled" group.long c15:0x2e9++0x00 line.long 0x00 "PMINTENCLR,Performance Monitor Interrupt Enable Clear" eventfld.long 0x00 5. " P5 ,Overflow Interrupt Clear" "Disabled,Enabled" textline " " eventfld.long 0x00 4. " P4 ,Overflow Interrupt Clear" "Disabled,Enabled" eventfld.long 0x00 3. " P3 ,Overflow Interrupt Clear" "Disabled,Enabled" eventfld.long 0x00 2. " P2 ,Overflow Interrupt Clear" "Disabled,Enabled" textline " " eventfld.long 0x00 1. " P1 ,Overflow Interrupt Clear" "Disabled,Enabled" eventfld.long 0x00 0. " P0 ,Overflow Interrupt Clear" "Disabled,Enabled" group.long c15:0x3e9++0x00 line.long 0x00 "PMOVSSET,Performance Monitor Overflow Flag Status Set Register" bitfld.long 0x00 31. " C ,PMCCNTR overflow bit" "Not overflowed,Overflowed" bitfld.long 0x00 30. " P30 ,Event Counter Overflow" "Disabled,Enabled" bitfld.long 0x00 29. " P29 ,Event Counter Overflow" "Disabled,Enabled" bitfld.long 0x00 28. " P28 ,Event Counter Overflow" "Disabled,Enabled" textline " " bitfld.long 0x00 27. " P27 ,Event Counter Overflow" "Disabled,Enabled" bitfld.long 0x00 26. " P26 ,Event Counter Overflow" "Disabled,Enabled" bitfld.long 0x00 25. " P25 ,Event Counter Overflow" "Disabled,Enabled" bitfld.long 0x00 24. " P24 ,Event Counter Overflow" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " P23 ,Event Counter Overflow" "Disabled,Enabled" bitfld.long 0x00 22. " P22 ,Event Counter Overflow" "Disabled,Enabled" bitfld.long 0x00 21. " P21 ,Event Counter Overflow" "Disabled,Enabled" bitfld.long 0x00 20. " P20 ,Event Counter Overflow" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " P19 ,Event Counter Overflow" "Disabled,Enabled" bitfld.long 0x00 18. " P18 ,Event Counter Overflow" "Disabled,Enabled" bitfld.long 0x00 17. " P17 ,Event Counter Overflow" "Disabled,Enabled" bitfld.long 0x00 16. " P16 ,Event Counter Overflow" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " P15 ,Event Counter Overflow" "Disabled,Enabled" bitfld.long 0x00 14. " P14 ,Event Counter Overflow" "Disabled,Enabled" bitfld.long 0x00 13. " P13 ,Event Counter Overflow" "Disabled,Enabled" bitfld.long 0x00 12. " P12 ,Event Counter Overflow" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " P11 ,Event Counter Overflow" "Disabled,Enabled" bitfld.long 0x00 10. " P10 ,Event Counter Overflow" "Disabled,Enabled" bitfld.long 0x00 9. " P9 ,Event Counter Overflow" "Disabled,Enabled" bitfld.long 0x00 8. " P8 ,Event Counter Overflow" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " P7 ,Event Counter Overflow" "Disabled,Enabled" bitfld.long 0x00 6. " P6 ,Event Counter Overflow" "Disabled,Enabled" bitfld.long 0x00 5. " P5 ,Event Counter Overflow" "Disabled,Enabled" bitfld.long 0x00 4. " P4 ,Event Counter Overflow" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " P3 ,Event Counter Overflow" "Disabled,Enabled" bitfld.long 0x00 2. " P2 ,Event Counter Overflow" "Disabled,Enabled" bitfld.long 0x00 1. " P1 ,Event Counter Overflow" "Disabled,Enabled" bitfld.long 0x00 0. " P0 ,Event Counter Overflow" "Disabled,Enabled" tree.end width 12. tree "System Timer Register" group.long c15:0x000E++0x00 line.long 0x00 "CNTFRQ,Counter Frequency Register" group.long c15:0x001E++0x00 line.long 0x00 "CNTKCTL,Timer PL1 Control Register" bitfld.long 0x00 9. " PL0PTEN ,Controls whether the physical timer registers are accessible from PL0 modes" "Not accessible,Accessible" bitfld.long 0x00 8. " PL0VTEN ,Controls whether the virtual timer registers are accessible from PL0 modes" "Not accessible,Accessible" bitfld.long 0x00 4.--7. " EVNTI ,Selects which bit of CNTVCT is the trigger for the event stream generated from the virtual counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 3. " EVNTDIR ,Controls which transition of the CNTVCT trigger bit" "0 to 1,1 to 0" bitfld.long 0x00 2. " EVNTEN ,Enables the generation of an event stream from the virtual counter" "Disabled,Enabled" bitfld.long 0x00 1. " PL0VCTEN ,Controls whether the virtual counter, CNTVCT, and the frequency register CNTFRQ, are accessible from PL0 modes" "Not accessible,Accessible" textline " " bitfld.long 0x00 0. " PL0PCTEN ,Controls whether the physical counter, CNTPCT, and the frequency register CNTFRQ, are accessible from PL0 modes" "Not accessible,Accessible" textline "" group.quad c15:0x100E0++0x01 line.quad 0x00 "CNTPCT,Counter Physical Count Register" group.quad c15:0x120E0++0x01 line.quad 0x00 "CNTP_CVAL,Counter PL1 Physical Compare Value Register" group.long c15:0x002E++0x00 line.long 0x00 "CNTP_TVAL,Counter PL1 Physical Timer Value Register" group.long c15:0x012E++0x00 line.long 0x00 "CNTP_CTL,Counter PL1 Physical Timer Control Register" bitfld.long 0x00 2. " ISTATUS ,The status of the timer interrupt" "No interrupt,Interrupt" bitfld.long 0x00 1. " IMASK ,Timer interrupt mask bit" "Not masked,Masked" bitfld.long 0x00 0. " ENABLE ,Enables the timer" "Disabled,Enabled" textline "" group.quad c15:0x110E0++0x01 line.quad 0x00 "CNTVCT,Counter Virtual Count Register" group.quad c15:0x130E0++0x01 line.quad 0x00 "CNTV_CVAL,Counter PL1 Virtual Compare Value Register" group.long c15:0x003E++0x00 line.long 0x00 "CNTV_TVAL,Counter PL1 Virtual Timer Value Register" group.long c15:0x013E++0x00 line.long 0x00 "CNTV_CTL,Counter PL1 Virtual Timer Control Register" bitfld.long 0x00 2. " ISTATUS ,The status of the timer interrupt" "No interrupt,Interrupt" bitfld.long 0x00 1. " IMASK ,Timer interrupt mask bit" "Not masked,Masked" bitfld.long 0x00 0. " ENABLE ,Enables the timer" "Disabled,Enabled" group.quad c15:0x140E0++0x01 line.quad 0x00 "CNTVOFF,Counter Virtual Offset Register" textline "" group.long c15:0x401E++0x00 line.long 0x00 "CNTHCTL,Counter Non-secure PL2 Control Register" bitfld.long 0x00 4.--7. " EVNTI ,Selects which bit of CNTPCTis the trigger for the event stream generated from the physical counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. " EVNTDIR ,Controls which transition of the CNTVCT trigger bit" "0 to 1,1 to 0" bitfld.long 0x00 2. " EVNTEN ,Enables the generation of an event stream from the virtual counter" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " PL1VCTEN ,Controls whether the virtual counter, CNTVCT, and the frequency register CNTFRQ, are accessible from PL0 modes" "Not accessible,Accessible" bitfld.long 0x00 0. " PL1PCTEN ,Controls whether the physical counter, CNTPCT, and the frequency register CNTFRQ, are accessible from PL0 modes" "Not accessible,Accessible" group.quad c15:0x160E0++0x01 line.quad 0x00 "CNTHP_CVAL,Counter Non-secure PL2 Physical Compare Value Register" group.long c15:0x402E++0x00 line.long 0x00 "CNTHP_TVAL,Counter Non-secure PL2 Physical Timer Value Register" group.long c15:0x412E++0x00 line.long 0x00 "CNTHP_CTL,Counter Non-secure PL2 Physical Timer Control Register" bitfld.long 0x00 2. " ISTATUS ,The status of the timer interrupt" "No interrupt,Interrupt" bitfld.long 0x00 1. " IMASK ,Timer interrupt mask bit" "Not masked,Masked" bitfld.long 0x00 0. " ENABLE ,Enables the timer" "Disabled,Enabled" tree.end width 11. width 15. tree "Debug Registers" rgroup.long c14:0.++0x0 line.long 0x0 "DBGDIDR,Debug ID Register" bitfld.long 0x0 28.--31. " WRP ,Number of Watchpoint Register Pairs" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x0 24.--27. " BRP ,Number of Breakpoint Register Pairs" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x0 20.--23. " CTX_CMP ,Number of BRPs with Context ID Comparison Capability" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" textline " " hexmask.long.byte 0x0 16.--19. 1. " VERSION ,Debug Architecture Version" bitfld.long 0x0 15. " DEVID ,Debug Device ID" "Low,High" bitfld.long 0x0 14. " NSUHD ,Secure User halting debug-mode" "Supported,Not supported" textline " " bitfld.long 0x0 13. " PCSR ,PC Sample register implemented" "Not implemented,Implemented" bitfld.long 0x0 12. " SE ,Security Extensions implemented" "Not implemented,Implemented" hexmask.long.byte 0x0 4.--7. 1. " VARIANT ,Implementation-defined Variant Number" textline " " hexmask.long.byte 0x0 0.--3. 1. " REVISION ,Implementation-defined Revision Number" textline " " if (corename()=="CORTEXA15"||corename()=="CORTEXA15MPCORE") wgroup.long c14:6.++0x0 line.long 0x00 "DBGWFAR,Watchpoint Fault Address Register" elif (corename()=="CORTEXA7"||corename()=="CORTEXA7MPCORE") rgroup.long c14:1.++0x0 line.long 0x00 "DBGDSCR,Debug Status and Control Register (Internal View)" bitfld.long 0x00 30. " RXFULL ,DBGDTRRX Register full" "Empty,Full" bitfld.long 0x00 29. " TXFULL ,DBGDTRTX Register full" "Empty,Full" bitfld.long 0x00 27. " RXFULL_L ,Latched RXFULL bit" "Not latched,Latched" textline " " bitfld.long 0x00 26. " TXFULL_L ,Latched TXFULL bit" "Not latched,Latched" bitfld.long 0x00 25. " PIPEADV ,PIPEADV Processor Idle flag" "Not idle,Idle" bitfld.long 0x00 24. " INSTRCOMPL_L ,Latched instruction complete" "Not completed,Completed" textline " " bitfld.long 0x00 20.--21. " EXTDCCMODE ,External DCC access mode field" "Non-blocking,Stall,Fast,?..." bitfld.long 0x00 19. " ADADISCARD ,Asynchronous Data Aborts Discarded bit" "Normal,Abort" bitfld.long 0x00 18. " NS ,Non-secure status bit" "Secure,Non-secure" textline " " bitfld.long 0x00 17. " SPNIDDIS ,Secure Privileged Non-Invasive Debug Disable" "No,Yes" bitfld.long 0x00 16. " SPIDDIS ,Secure Privileged Invasive Debug Disable" "No,Yes" bitfld.long 0x00 15. " MDBGEN ,Monitor debug-mode enable" "Disabled,Enabled" textline " " bitfld.long 0x00 14. " HDBGEN ,Halting debug-mode" "Disabled,Enabled" bitfld.long 0x00 13. " ITREN ,Execute ARM instruction enable" "Disabled,Enabled" bitfld.long 0x00 12. " UDCCDIS ,User mode access to Communications Channel disable" "No,Yes" textline " " bitfld.long 0x00 11. " INTDIS ,Interrupt disable" "No,Yes" bitfld.long 0x00 10. " DBGACK ,Force debug acknowledge" "Normal,Forced" bitfld.long 0x00 9. " DBGNOPWRDWN ,Debug no power-down" "Low,High" textline " " bitfld.long 0x00 8. " UND_L ,Sticky undefined bit" "Not occurred,Occurred" bitfld.long 0x00 7. " ADABORT ,Asynchronous data abort" "Not aborted,Aborted" bitfld.long 0x00 6. " SDABORT ,Synchronous data abort" "Not aborted,Aborted" textline " " bitfld.long 0x00 2.--5. " MOE ,Method of debug entry field" "Halt Request,Breakpoint,Asynchronous Watchpoint,BKPT Instruction,External Debug Request,Vector Catch,Reserved,Reserved,OS Unlock Catch,Reserved,Synchronous Watchpoint,?..." bitfld.long 0x00 1. " RESTARTED ,Processor restarted" "Pending,Exited" bitfld.long 0x00 0. " HALTED ,Processor halted" "Non-debug,Debug" wgroup.long c14:5.++0x0 line.long 0x00 "DBGDTRTX,Debug Transmit/Receive Register (Internal View)" elif (corename()=="CORTEXA17"||corename()=="CORTEXA17MPCORE") if (((d.l(c14:195.))&0x1)==0x1) group.long c14:1.++0x0 line.long 0x00 "DBGDSCR,Debug Status and Control Register (Internal View)" bitfld.long 0x00 30. " RXFULL ,DBGDTRRX Register full" "Empty,Full" bitfld.long 0x00 29. " TXFULL ,DBGDTRTX Register full" "Empty,Full" bitfld.long 0x00 27. " RXFULL_L ,Latched RXFULL bit" "Not latched,Latched" textline " " bitfld.long 0x00 26. " TXFULL_L ,Latched TXFULL bit" "Not latched,Latched" rbitfld.long 0x00 25. " PIPEADV ,PIPEADV Processor Idle flag" "Not idle,Idle" rbitfld.long 0x00 24. " INSTRCOMPL_L ,Latched instruction complete" "Not completed,Completed" textline " " bitfld.long 0x00 20.--21. " EXTDCCMODE ,External DCC access mode field" "Non-blocking,Stall,Fast,?..." rbitfld.long 0x00 19. " ADADISCARD ,Asynchronous Data Aborts Discarded bit" "Normal,Abort" rbitfld.long 0x00 18. " NS ,Non-secure state status" "Secure,Non-secure" textline " " rbitfld.long 0x00 17. " SPNIDDIS ,Secure Privileged Non-Invasive Debug Disable" "Enabled,Disabled" rbitfld.long 0x00 16. " SPIDDIS ,Secure Privileged Invasive Debug Disable" "Enabled,Disabled" bitfld.long 0x00 15. " MDBGEN ,Monitor debug-mode enable" "Disabled,Enabled" textline " " bitfld.long 0x00 14. " HDBGEN ,Halting debug-mode" "Disabled,Enabled" bitfld.long 0x00 13. " ITREN ,Execute ARM instruction enable" "Disabled,Enabled" bitfld.long 0x00 12. " UDCCDIS ,User mode access to Communications Channel disable" "Enabled,Disabled" textline " " bitfld.long 0x00 11. " INTDIS ,Interrupt disable" "Enabled,Disabled" bitfld.long 0x00 10. " DBGACK ,Force debug acknowledge" "Normal,Forced" rbitfld.long 0x00 9. " FS ,Fault status" "No exception,Exception" textline " " rbitfld.long 0x00 8. " UND_L ,Sticky undefined bit" "Not occurred,Occurred" rbitfld.long 0x00 7. " ADABORT_L ,Sticky Asynchronous Abort" "Not occurred,Occurred" rbitfld.long 0x00 6. " SDABORT_L ,Sticky Synchronous Data Abort" "Not occurred,Occurred" textline " " rbitfld.long 0x00 2.--5. " MOE ,Method of debug entry field" "Halt Request,Breakpoint,Asynchronous Watchpoint,BKPT Instruction,External Debug Request,Vector Catch,Reserved,Reserved,OS Unlock Catch,Reserved,Synchronous Watchpoint,?..." rbitfld.long 0x00 1. " RESTARTED ,Processor restarted" "Pending,Exited" rbitfld.long 0x00 0. " HALTED ,Processor halted" "Non-debug,Debug" else rgroup.long c14:1.++0x0 line.long 0x00 "DBGDSCR,Debug Status and Control Register (Internal View)" rbitfld.long 0x00 30. " RXFULL ,DBGDTRRX Register full" "Empty,Full" rbitfld.long 0x00 29. " TXFULL ,DBGDTRTX Register full" "Empty,Full" rbitfld.long 0x00 27. " RXFULL_L ,Latched RXFULL bit" "Not latched,Latched" textline " " rbitfld.long 0x00 26. " TXFULL_L ,Latched TXFULL bit" "Not latched,Latched" rbitfld.long 0x00 25. " PIPEADV ,PIPEADV Processor Idle flag" "Not idle,Idle" rbitfld.long 0x00 24. " INSTRCOMPL_L ,Latched instruction complete" "Not completed,Completed" textline " " bitfld.long 0x00 20.--21. " EXTDCCMODE ,External DCC access mode field" "Non-blocking,Stall,Fast,?..." bitfld.long 0x00 19. " ADADISCARD ,Asynchronous Data Aborts Discarded bit" "Normal,Abort" rbitfld.long 0x00 18. " NS ,Non-secure state status" "Secure,Non-secure" textline " " rbitfld.long 0x00 17. " SPNIDDIS ,Secure Privileged Non-Invasive Debug Disable" "Enabled,Disabled" rbitfld.long 0x00 16. " SPIDDIS ,Secure Privileged Invasive Debug Disable" "Enabled,Disabled" bitfld.long 0x00 15. " MDBGEN ,Monitor debug-mode enable" "Disabled,Enabled" textline " " bitfld.long 0x00 14. " HDBGEN ,Halting debug-mode" "Disabled,Enabled" bitfld.long 0x00 13. " ITREN ,Execute ARM instruction enable" "Disabled,Enabled" bitfld.long 0x00 12. " UDCCDIS ,User mode access to Communications Channel disable" "Enabled,Disabled" textline " " bitfld.long 0x00 11. " INTDIS ,Interrupt disable" "Enabled,Disabled" bitfld.long 0x00 10. " DBGACK ,Force debug acknowledge" "Normal,Forced" bitfld.long 0x00 9. " FS ,Fault status" "No exception,Exception" textline " " rbitfld.long 0x00 8. " UND_L ,Sticky undefined bit" "Not occurred,Occurred" rbitfld.long 0x00 7. " ADABORT_L ,Sticky Asynchronous Abort" "Not occurred,Occurred" rbitfld.long 0x00 6. " SDABORT_L ,Sticky Synchronous Data Abort" "Not occurred,Occurred" textline " " bitfld.long 0x00 2.--5. " MOE ,Method of debug entry field" "Halt Request,Breakpoint,Asynchronous Watchpoint,BKPT Instruction,External Debug Request,Vector Catch,Reserved,Reserved,OS Unlock Catch,Reserved,Synchronous Watchpoint,?..." rbitfld.long 0x00 1. " RESTARTED ,Processor restarted" "Pending,Exited" rbitfld.long 0x00 0. " HALTED ,Processor halted" "Non-debug,Debug" endif wgroup.long c14:5.++0x0 line.long 0x00 "DBGDTRTX,Debug Transmit/Receive Register (Internal View)" endif group.long c14:0x7++0x0 line.long 0x00 "DBGVCR,Debug Vector Catch register" bitfld.long 0x00 31. " NSF ,FIQ vector catch in Non-secure state" "Disabled,Enabled" bitfld.long 0x00 30. " NSI ,IRG vector catch in Non-secure state" "Disabled,Enabled" bitfld.long 0x00 28. " NSD ,Data Abort vector catch in Non-secure state" "Disabled,Enabled" textline " " bitfld.long 0x00 27. " NSP ,Prefetch Abort vector catch in Non-secure state" "Disabled,Enabled" bitfld.long 0x00 26. " NSS ,SVC vector catch in Non-secure state" "Disabled,Enabled" bitfld.long 0x00 25. " NSU ,Undefined instruction vector catch in Non-secure state" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " NSHF ,FIQ interrupt exception vector catch enable in Non-secure state" "Disabled,Enabled" bitfld.long 0x00 22. " NSHI ,IRQ interrupt exception vector catch enable in Non-secure state" "Disabled,Enabled" bitfld.long 0x00 21. " NSHE ,Hyp Trap or Hyp mode entry exception vector catch enable in Non-secure state" "Disabled,Enabled" textline " " bitfld.long 0x00 20. " NSHD ,Data Abort, from Hyp mode exception vector catch enable in Non-secure state" "Disabled,Enabled" bitfld.long 0x00 19. " NSHP ,Prefetch Abort, from Hyp mode exception vector catch enable in Non-secure state" "Disabled,Enabled" bitfld.long 0x00 18. " NSHC ,Hypervisor Call. from Hyp mode exception vector catch enable in Non-secure state" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " NSHU ,Undefined Instruction, from Hyp mode exception vector catch enable in Non-secure state" "Disabled,Enabled" bitfld.long 0x00 15. " MF ,FIQ vector catch enable, in Secure state on Monitor mode vector" "Disabled,Enabled" bitfld.long 0x00 14. " MI ,IRQ vector catch enable in Secure state on Monitor mode vector" "Disabled,Enabled" textline " " bitfld.long 0x00 12. " MD ,Data Abort vector catch enable in Secure state on Monitor mode vector" "Disabled,Enabled" bitfld.long 0x00 11. " MP ,Prefetch Abort vector catch enable in Secure state on Monitor mode vector" "Disabled,Enabled" bitfld.long 0x00 10. " MS ,SMC vector catch enable in Secure state" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " SF ,FIQ vector catch in Secure state" "Disabled,Enabled" bitfld.long 0x00 6. " SI ,IRQ vector catch in Secure state" "Disabled,Enabled" bitfld.long 0x00 4. " SD ,Data Abort vector catch in Secure state" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " SP ,Prefetch Abort vector catch in Secure state" "Disabled,Enabled" bitfld.long 0x00 2. " SS ,SVC vector catch in Secure state" "Disabled,Enabled" bitfld.long 0x00 1. " SU ,Undefined instruction vector catch in Secure state" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " R ,Reset vector catch enable" "Disabled,Enabled" group.long c14:9.++0x0 line.long 0x00 "DBGECR,Debug Event Catch Register" bitfld.long 0x00 0. " OSUC ,OS Unlock Catch" "Disabled,Enabled" group.long c14:32.++0x0 line.long 0x00 "DBGDTRRX,Debug Receive Register (External View)" wgroup.long c14:33.++0x0 line.long 0x00 "DBGITR,Debug Instruction Transfer Register" rgroup.long c14:33.++0x0 line.long 0x00 "DBGPCSR,Program Counter Sampling Register" hexmask.long 0x00 2.--31. 1. " PCS ,Program Counter sample value" bitfld.long 0x00 0.--1. " T ,Meaning of PC sample value" "ARM,Thumb,Reserved,Thumb" if (corename()=="CORTEXA15"||corename()=="CORTEXA15MPCORE") group.long c14:34.++0x0 line.long 0x00 "DBGDSCR,Debug Status and Control Register (External View)" bitfld.long 0x00 30. " RXFULL ,DBGDTRRX Register full" "Empty,Full" bitfld.long 0x00 29. " TXFULL ,DBGDTRTX Register full" "Empty,Full" bitfld.long 0x00 27. " RXFULL_L ,Latched RXFULL bit" "Not latched,Latched" textline " " bitfld.long 0x00 26. " TXFULL_L ,Latched TXFULL bit" "Not latched,Latched" bitfld.long 0x00 25. " PIPEADC ,PIPEADV Processor Idle flag" "Not idle,Idle" bitfld.long 0x00 24. " INSTRCOMPL_L ,Latched instruction complete" "Not completed,Completed" textline " " bitfld.long 0x00 20.--21. " EXTDCCMODE ,External DCC acces mode field" "Non-blocking,Stall,Fast,?..." bitfld.long 0x00 19. " ADADISCARD ,Asynchronous Data Aborts Discarded bit" "Normal,Abort" bitfld.long 0x00 18. " NS ,Non-secure status bit" "Secure,Non-secure" textline " " bitfld.long 0x00 17. " SPNIDDIS ,Secure Privileged Non-Invasive Debug Disable" "No,Yes" bitfld.long 0x00 16. " SPIDDIS ,Secure Privileged Invasive Debug Disable" "No,Yes" bitfld.long 0x00 15. " MDBGEN ,Monitor debug-mode enable" "Disabled,Enabled" textline " " bitfld.long 0x00 14. " HDBGEN ,Halting debug-mode" "Disabled,Enabled" bitfld.long 0x00 13. " ITREN ,Execute ARM instruction enable" "Disabled,Enabled" bitfld.long 0x00 12. " UDCCDIS ,User mode access to Communications Channel disable" "No,Yes" textline " " bitfld.long 0x00 11. " INTDIS ,Interrupt disable" "No,Yes" bitfld.long 0x00 10. " DBGACK ,Force debug acknowledge" "Normal,Forced" bitfld.long 0x00 9. " FS ,Fault Status" "Not caused,Caused" textline " " bitfld.long 0x00 8. " UND_L ,Sticky undefined bit" "Not occurred,Occurred" bitfld.long 0x00 7. " ADABORT ,Asynchronous data abort" "Not aborted,Aborted" bitfld.long 0x00 6. " SDABORT ,Synchronous data abort" "Not aborted,Aborted" textline " " bitfld.long 0x00 2.--5. " MOE ,Method of debug entry field" "Halt Request,Breakpoint,Asynchronous Watchpoint,BKPT Instruction,External Debug Request,Vector Catch,Reserved,Reserved,OS Unlock Catch,Reserved,Synchronous Watchpoint,?..." bitfld.long 0x00 1. " RESTARTED ,Processor restarted" "Pending,Exited" bitfld.long 0x00 0. " HALTED ,Processor halted" "Non-debug,Debug" elif (corename()=="CORTEXA7"||corename()=="CORTEXA7MPCORE") group.long c14:34.++0x0 line.long 0x00 "DBGDSCR,Debug Status and Control Register (External View)" bitfld.long 0x00 30. " RXFULL ,DBGDTRRX Register full" "Empty,Full" bitfld.long 0x00 29. " TXFULL ,DBGDTRTX Register full" "Empty,Full" bitfld.long 0x00 27. " RXFULL_L ,Latched RXFULL bit" "Not latched,Latched" textline " " bitfld.long 0x00 26. " TXFULL_L ,Latched TXFULL bit" "Not latched,Latched" bitfld.long 0x00 25. " PIPEADC ,PIPEADV Processor Idle flag" "Not idle,Idle" bitfld.long 0x00 24. " INSTRCOMPL_L ,Latched instruction complete" "Not completed,Completed" textline " " bitfld.long 0x00 20.--21. " EXTDCCMODE ,External DCC acces mode field" "Non-blocking,Stall,Fast,?..." bitfld.long 0x00 19. " ADADISCARD ,Asynchronous Data Aborts Discarded bit" "Normal,Abort" bitfld.long 0x00 18. " NS ,Non-secure status bit" "Secure,Non-secure" textline " " bitfld.long 0x00 17. " SPNIDDIS ,Secure Privileged Non-Invasive Debug Disable" "No,Yes" bitfld.long 0x00 16. " SPIDDIS ,Secure Privileged Invasive Debug Disable" "No,Yes" bitfld.long 0x00 15. " MDBGEN ,Monitor debug-mode enable" "Disabled,Enabled" textline " " bitfld.long 0x00 14. " HDBGEN ,Halting debug-mode" "Disabled,Enabled" bitfld.long 0x00 13. " ITREN ,Execute ARM instruction enable" "Disabled,Enabled" bitfld.long 0x00 12. " UDCCDIS ,User mode access to Communications Channel disable" "No,Yes" textline " " bitfld.long 0x00 11. " INTDIS ,Interrupt disable" "No,Yes" bitfld.long 0x00 10. " DBGACK ,Force debug acknowledge" "Normal,Forced" bitfld.long 0x00 9. " DBGNOPWRDWN ,Debug no power-down" "Low,High" textline " " bitfld.long 0x00 8. " UND_L ,Sticky undefined bit" "Not occurred,Occurred" bitfld.long 0x00 7. " ADABORT ,Asynchronous data abort" "Not aborted,Aborted" bitfld.long 0x00 6. " SDABORT ,Synchronous data abort" "Not aborted,Aborted" textline " " bitfld.long 0x00 2.--5. " MOE ,Method of debug entry field" "Halt Request,Breakpoint,Asynchronous Watchpoint,BKPT Instruction,External Debug Request,Vector Catch,Reserved,Reserved,OS Unlock Catch,Reserved,Synchronous Watchpoint,?..." bitfld.long 0x00 1. " RESTARTED ,Processor restarted" "Pending,Exited" bitfld.long 0x00 0. " HALTED ,Processor halted" "Non-debug,Debug" elif (corename()=="CORTEXA17"||corename()=="CORTEXA17MPCORE") if (((d.l(c14:195.))&0x1)==0x1) group.long c14:34.++0x0 line.long 0x00 "DBGDSCR,Debug Status and Control Register (External View)" bitfld.long 0x00 30. " RXFULL ,DBGDTRRX Register full" "Empty,Full" bitfld.long 0x00 29. " TXFULL ,DBGDTRTX Register full" "Empty,Full" bitfld.long 0x00 27. " RXFULL_L ,Latched RXFULL bit" "Not latched,Latched" textline " " bitfld.long 0x00 26. " TXFULL_L ,Latched TXFULL bit" "Not latched,Latched" rbitfld.long 0x00 25. " PIPEADV ,Sticky Pipeline Advance bit" "Not idle,Idle" rbitfld.long 0x00 24. " INSTRCOMPL_L ,Latched instruction complete" "Not complete,Complete" textline " " bitfld.long 0x00 20.--21. " EXTDCCMODE ,External DCC acces mode field" "Non-blocking,Stall,Fast,?..." bitfld.long 0x00 19. " ADADISCARD ,Asynchronous Data Aborts Discarded bit" "Normal,Discarded" bitfld.long 0x00 18. " NS ,Non-secure status bit" "Secure,Non-secure" textline " " rbitfld.long 0x00 17. " SPNIDDIS ,Secure Privileged Non-Invasive Debug Disable" "Enabled,Disabled" rbitfld.long 0x00 16. " SPIDDIS ,Secure Privileged Invasive Debug Disable" "Enabled,Disabled" bitfld.long 0x00 15. " MDBGEN ,Monitor debug-mode enable" "Disabled,Enabled" textline " " bitfld.long 0x00 14. " HDBGEN ,Halting debug-mode" "Disabled,Enabled" bitfld.long 0x00 13. " ITREN ,Execute ARM instruction enable" "Disabled,Enabled" bitfld.long 0x00 12. " UDCCDIS ,User mode access to Communications Channel disable" "Enabled,Disabled" textline " " bitfld.long 0x00 11. " INTDIS ,Interrupt disable" "Enabled,Disabled" bitfld.long 0x00 10. " DBGACK ,Force debug acknowledge" "Normal,Forced" bitfld.long 0x00 9. " FS ,Fault status" "Low,High" textline " " rbitfld.long 0x00 8. " UND_L ,Sticky undefined bit" "Not occurred,Occurred" rbitfld.long 0x00 7. " ADABORT_L ,Sticky Asynchronous Abort" "Not occurred,Occurred" rbitfld.long 0x00 6. " SDABORT_L ,Sticky Synchronous Data Abort" "Not occurred,Occurred" textline " " bitfld.long 0x00 2.--5. " MOE ,Method of debug entry field" "Halt Request,Breakpoint,Asynchronous Watchpoint,BKPT Instruction,External Debug Request,Vector Catch,Reserved,Reserved,OS Unlock Catch,Reserved,Synchronous Watchpoint,?..." rbitfld.long 0x00 1. " RESTARTED ,Processor restarted" "Pending,Exited" rbitfld.long 0x00 0. " HALTED ,Processor halted" "Non-debug,Debug" else group.long c14:34.++0x0 line.long 0x00 "DBGDSCR,Debug Status and Control Register (External View)" rbitfld.long 0x00 30. " RXFULL ,DBGDTRRX Register full" "Empty,Full" rbitfld.long 0x00 29. " TXFULL ,DBGDTRTX Register full" "Empty,Full" rbitfld.long 0x00 27. " RXFULL_L ,Latched RXFULL bit" "Not latched,Latched" textline " " rbitfld.long 0x00 26. " TXFULL_L ,Latched TXFULL bit" "Not latched,Latched" rbitfld.long 0x00 25. " PIPEADV ,Sticky Pipeline Advance bit" "Not idle,Idle" rbitfld.long 0x00 24. " INSTRCOMPL_L ,Latched instruction complete" "Not complete,Complete" textline " " bitfld.long 0x00 20.--21. " EXTDCCMODE ,External DCC acces mode field" "Non-blocking,Stall,Fast,?..." bitfld.long 0x00 19. " ADADISCARD ,Asynchronous Data Aborts Discarded bit" "Normal,Discarded" bitfld.long 0x00 18. " NS ,Non-secure status bit" "Secure,Non-secure" textline " " rbitfld.long 0x00 17. " SPNIDDIS ,Secure Privileged Non-Invasive Debug Disable" "Enabled,Disabled" rbitfld.long 0x00 16. " SPIDDIS ,Secure Privileged Invasive Debug Disable" "Enabled,Disabled" bitfld.long 0x00 15. " MDBGEN ,Monitor debug-mode enable" "Disabled,Enabled" textline " " bitfld.long 0x00 14. " HDBGEN ,Halting debug-mode" "Disabled,Enabled" bitfld.long 0x00 13. " ITREN ,Execute ARM instruction enable" "Disabled,Enabled" bitfld.long 0x00 12. " UDCCDIS ,User mode access to Communications Channel disable" "Enabled,Disabled" textline " " rbitfld.long 0x00 11. " INTDIS ,Interrupt disable" "Enabled,Disabled" bitfld.long 0x00 10. " DBGACK ,Force debug acknowledge" "Normal,Forced" bitfld.long 0x00 9. " FS ,Fault status" "Low,High" textline " " rbitfld.long 0x00 8. " UND_L ,Sticky undefined bit" "Not occurred,Occurred" rbitfld.long 0x00 7. " ADABORT_L ,Sticky Asynchronous Abort" "Not occurred,Occurred" rbitfld.long 0x00 6. " SDABORT_L ,Sticky Synchronous Data Abort" "Not occurred,Occurred" textline " " bitfld.long 0x00 2.--5. " MOE ,Method of debug entry field" "Halt Request,Breakpoint,Asynchronous Watchpoint,BKPT Instruction,External Debug Request,Vector Catch,Reserved,Reserved,OS Unlock Catch,Reserved,Synchronous Watchpoint,?..." rbitfld.long 0x00 1. " RESTARTED ,Processor restarted" "Pending,Exited" rbitfld.long 0x00 0. " HALTED ,Processor halted" "Non-debug,Debug" endif endif wgroup.long c14:35.++0x0 line.long 0x00 "DBGDTRTX,Debug Transmit Register (External View)" if (corename()=="CORTEXA15"||corename()=="CORTEXA15MPCORE"||corename()=="CORTEXA17"||corename()=="CORTEXA17MPCORE") wgroup.long c14:36.++0x0 line.long 0x00 "DBGDRCR,Debug Run Control Register" bitfld.long 0x00 3. " CSPA ,Clear Sticky Pipeline Advance bit" "No effect,Clear" bitfld.long 0x00 2. " CSE ,Clear Sticky Exceptions bits" "No effect,Clear" bitfld.long 0x00 1. " RRQ ,Restart request" "No effect,Restart" bitfld.long 0x00 0. " HRQ ,Halt request" "No effect,Halt" elif (corename()=="CORTEXA7"||corename()=="CORTEXA7MPCORE") wgroup.long c14:36.++0x0 line.long 0x00 "DBGDRCR,Debug Run Control Register" bitfld.long 0x00 4. " CBRRQ ,CBRRQ" "Low,High" bitfld.long 0x00 3. " CSPA ,Clear Sticky Pipeline Advance bit" "No effect,Clear" bitfld.long 0x00 2. " CSE ,Clear Sticky Exceptions bits" "No effect,Clear" textline " " bitfld.long 0x00 1. " RR ,Restart request" "No effect,Restart" bitfld.long 0x00 0. " HR ,Halt request" "No effect,Halt" endif if (corename()=="CORTEXA15"||corename()=="CORTEXA15MPCORE") group.long c14:37.++0x0 line.long 0x00 "DBGEACR,Debug External Auxiliary Control Register" bitfld.long 0x00 3. " CDRS ,Core debug reset status" "No reset,Reset" bitfld.long 0x00 2. " DECRR ,Debug extend core reset request" "No request,Request" bitfld.long 0x00 1. " DPDO ,Debug power-down override" "Disabled,Enabled" bitfld.long 0x00 0. " DCSC ,Debug clock stop control" "Stopped,Running" textline " " elif (corename()=="CORTEXA7"||corename()=="CORTEXA7MPCORE") group.long c14:37.++0x0 line.long 0x00 "DBGEACR,Debug External Auxiliary Control Register" bitfld.long 0x00 3. " CDRS ,Core debug reset status" "No reset,Reset" endif rgroup.long c14:40.++0x0 line.long 0x00 "DBGPCSR,Program Counter Sampling Register" hexmask.long 0x00 2.--31. 1. " PCS ,Program Counter sample value" bitfld.long 0x00 0.--1. " T ,Meaning of PC sample value" "ARM,Thumb,?..." rgroup.long c14:41.++0x0 line.long 0x00 "DBGCIDSR,DBGCIDSR" if (corename()=="CORTEXA15"||corename()=="CORTEXA15MPCORE"||corename()=="CORTEXA17"||corename()=="CORTEXA17MPCORE") rgroup.long c14:42.++0x0 line.long 0x00 "DBGVIDSR,Virtualization ID Sampling Register" bitfld.long 0x00 31. " NS ,NS state sample" "Secure,Non-secure" bitfld.long 0x00 30. " H ,Hyp mode sample" "Not associated,Associated" hexmask.long.byte 0x00 0.--7. 1. " VMID ,VMID sample" elif (corename()=="CORTEXA7"||corename()=="CORTEXA7MPCORE") rgroup.long c14:42.++0x0 line.long 0x00 "DBGVIDSR,DBGVIDSR" endif width 15. if (corename()=="CORTEXA15"||corename()=="CORTEXA15MPCORE") textline " " wgroup.long c14:958.++0x0 line.long 0x00 "DBGITOCTRL,Debug Integration Output Control Register" bitfld.long 0x00 3. " NPMUIRQ ,Drives the nPMUIRQ output" "Low,High" bitfld.long 0x00 2. " CTI_PMUIRQ ,Drives the internal signal equivalent to PMUIRQ that goes from the Performance Monitor Unit (PMU) to the Cross Trigger Interface (CTI)" "Low,High" bitfld.long 0x00 1. " CTI_DBGRESTARTED ,Drives the internal signal that goes from the Debug unit to the CTI to acknowledge success of a debug restart command" "Low,High" bitfld.long 0x00 0. " CTI_DBGTRIGGER ,Drives the internal signal equivalent to DBGTRIGGER that goes from the Debug unit to the CTI" "Low,High" elif (corename()=="CORTEXA7"||corename()=="CORTEXA7MPCORE") textline " " wgroup.long c14:958.++0x0 line.long 0x00 "DBGITMISCOUT,Integration Miscellaneous Signals Output Register" bitfld.long 0x00 9. " DBGRESTARTED ,Value of the DBGRESTARTED output pin" "Low,High" bitfld.long 0x00 4. " PMUIRQ ,Value of PMUIRQ output pin" "Low,High" bitfld.long 0x00 0. " DBGACK ,Value of the DBGACK output pin" "Low,High" endif if (corename()=="CORTEXA15"||corename()=="CORTEXA15MPCORE") rgroup.long c14:959.++0x0 line.long 0x00 "DBGITISR,Debug Integration Input Status Register" bitfld.long 0x00 3. " DBGSWENABLE ,Reads the state of the DBGSWENABLE input" "Low,High" bitfld.long 0x00 2. " CTI_DBGRESTART ,CTI debug restart" "Low,High" bitfld.long 0x00 1. " CTI_EDBGRQ ,CTI debug request" "Low,High" bitfld.long 0x00 0. " EDBGRQ ,Reads the state of the EDBGRQ input" "Low,High" elif (corename()=="CORTEXA7"||corename()=="CORTEXA7MPCORE") textline " " rgroup.long c14:959.++0x0 line.long 0x00 "DBGITMISCIN,Integration Miscellaneous Signals Input Register" bitfld.long 0x00 2. " NFIQ ,Read value of nFIQ input pin" "Low,High" bitfld.long 0x00 1. " NIRQ ,Read value of nIRQ input pin" "Low,High" bitfld.long 0x00 0. " EDBGRQ ,Read value of EDBGRQ input pin" "Low,High" endif if (corename()=="CORTEXA17"||corename()=="CORTEXA17MPCORE") if (((d.l(c15:0x202))&0x80000000)==0x80000000) rgroup.quad c14:128.++0x1 line.quad 0x0 "DBGDRAR,Debug ROM Address Register" hexmask.quad 0x0 12.--39. 0x1000 " ROMADDR ,ROM physical address" bitfld.quad 0x0 0.--1. " VALID ,ROM table address valid" "Not valid,Reserved,Reserved,Valid" rgroup.quad c14:256.++0x1 line.quad 0x0 "DBGDSAR,Debug Self Address Offset Register" hexmask.quad 0x0 12.--39. 0x1000 " SELFOFFSET ,Debug bus self-address offset value" bitfld.quad 0x0 0.--1. " VALID ,Debug self address offset valid" "Not valid,Reserved,Reserved,Valid" else rgroup.long c14:128.++0x0 line.long 0x0 "DBGDRAR,Debug ROM Address Register" hexmask.long 0x0 12.--31. 0x1000 " ROMADDR ,ROM physical address" bitfld.long 0x0 0.--1. " VALID ,ROM table address valid" "Not valid,Reserved,Reserved,Valid" rgroup.long c14:256.++0x0 line.long 0x0 "DBGDSAR,Debug Self Address Offset Register" hexmask.long 0x0 12.--31. 0x1000 " SELFOFFSET ,Debug bus self-address offset value" bitfld.long 0x0 0.--1. " VALID ,Debug self address offset valid" "Not valid,Reserved,Reserved,Valid" endif group.long c14:195.++0x00 line.long 0x00 "DBGOSDLR,OS Double Lock Register" bitfld.long 0x00 0. " DLK ,OS Double Lock control bit" "Unlocked,Locked" else hgroup.quad c14:128.++0x1 hide.quad 0x0 "DBGDRAR,Debug ROM Address Register" hgroup.quad c14:256.++0x1 hide.quad 0x0 "DBGDSAR,Debug Self Address Offset Register" hgroup.long c14:195.++0x00 hide.long 0x00 "DBGOSDLR,OS Double Lock Register" endif wgroup.long c14:192.++0x00 line.long 0x00 "DBGOSLAR,Operating System Lock Access Register" rgroup.long c14:193.++0x00 line.long 0x00 "DBGOSLSR,Operating System Lock Status Register" bitfld.long 0x00 1. " OSLK ,Status of the OS Lock" "Not locked,Locked" bitfld.long 0x00 0. 3. " OSLM ,OS Lock Model implemented Bit" "Reserved,Reserved,W/o DBGOSSRR,?..." group.long c14:196.++0x00 line.long 0x00 "DBGPRCR,Device Power-Down and Reset Control Register" bitfld.long 0x00 3. " COREPURQ ,Core Power Up Request" "Low,High" bitfld.long 0x00 2. " HCWR ,Hold Core Warm Reset" "No reset,Reset" bitfld.long 0x00 1. " CWRR ,Core Warm Reset Request" "Not requested,Requested" textline " " bitfld.long 0x00 0. " CORENPDRQ ,Core No Power down Request" "Low,High" rgroup.long c14:197.++0x0 line.long 0x00 "DBGPRSR,Device Power-down and Reset Status Register" bitfld.long 0x00 6. " DLK ,OS Double Lock status" "Low,High" bitfld.long 0x00 5. " OSLK ,OS Lock status" "Low,High" bitfld.long 0x00 4. " HALTED ,Halted" "Low,High" textline " " bitfld.long 0x00 3. " SR ,Sticky Reset Status" "Low,High" bitfld.long 0x00 2. " RS ,Reset Status" "Low,High" bitfld.long 0x00 1. " SPD ,Sticky Power-down Status" "Low,High" textline " " bitfld.long 0x00 0. " PU ,Power-up Status" "Low,High" tree "Processor ID registers" rgroup.long c14:(832.+0.)++0x00 line.long 0x00 "PIDR0,Processor ID register 0" rgroup.long c14:(832.+1.)++0x00 line.long 0x00 "PIDR1,Processor ID register 1" rgroup.long c14:(832.+2.)++0x00 line.long 0x00 "PIDR2,Processor ID register 2" rgroup.long c14:(832.+3.)++0x00 line.long 0x00 "PIDR3,Processor ID register 3" rgroup.long c14:(832.+4.)++0x00 line.long 0x00 "PIDR4,Processor ID register 4" rgroup.long c14:(832.+5.)++0x00 line.long 0x00 "PIDR5,Processor ID register 5" rgroup.long c14:(832.+6.)++0x00 line.long 0x00 "PIDR6,Processor ID register 6" rgroup.long c14:(832.+7.)++0x00 line.long 0x00 "PIDR7,Processor ID register 7" rgroup.long c14:(832.+8.)++0x00 line.long 0x00 "PIDR8,Processor ID register 8" rgroup.long c14:(832.+9.)++0x00 line.long 0x00 "PIDR9,Processor ID register 9" rgroup.long c14:(832.+10.)++0x00 line.long 0x00 "PIDR10,Processor ID register 10" rgroup.long c14:(832.+11.)++0x00 line.long 0x00 "PIDR11,Processor ID register 11" rgroup.long c14:(832.+12.)++0x00 line.long 0x00 "PIDR12,Processor ID register 12" rgroup.long c14:(832.+13.)++0x00 line.long 0x00 "PIDR13,Processor ID register 13" rgroup.long c14:(832.+14.)++0x00 line.long 0x00 "PIDR14,Processor ID register 14" rgroup.long c14:(832.+15.)++0x00 line.long 0x00 "PIDR15,Processor ID register 15" rgroup.long c14:(832.+16.)++0x00 line.long 0x00 "PIDR16,Processor ID register 16" rgroup.long c14:(832.+17.)++0x00 line.long 0x00 "PIDR17,Processor ID register 17" rgroup.long c14:(832.+18.)++0x00 line.long 0x00 "PIDR18,Processor ID register 18" rgroup.long c14:(832.+19.)++0x00 line.long 0x00 "PIDR19,Processor ID register 19" rgroup.long c14:(832.+20.)++0x00 line.long 0x00 "PIDR20,Processor ID register 20" rgroup.long c14:(832.+21.)++0x00 line.long 0x00 "PIDR21,Processor ID register 21" rgroup.long c14:(832.+22.)++0x00 line.long 0x00 "PIDR22,Processor ID register 22" rgroup.long c14:(832.+23.)++0x00 line.long 0x00 "PIDR23,Processor ID register 23" rgroup.long c14:(832.+24.)++0x00 line.long 0x00 "PIDR24,Processor ID register 24" rgroup.long c14:(832.+25.)++0x00 line.long 0x00 "PIDR25,Processor ID register 25" rgroup.long c14:(832.+26.)++0x00 line.long 0x00 "PIDR26,Processor ID register 26" rgroup.long c14:(832.+27.)++0x00 line.long 0x00 "PIDR27,Processor ID register 27" rgroup.long c14:(832.+28.)++0x00 line.long 0x00 "PIDR28,Processor ID register 28" rgroup.long c14:(832.+29.)++0x00 line.long 0x00 "PIDR29,Processor ID register 29" rgroup.long c14:(832.+30.)++0x00 line.long 0x00 "PIDR30,Processor ID register 30" rgroup.long c14:(832.+31.)++0x00 line.long 0x00 "PIDR31,Processor ID register 31" rgroup.long c14:(832.+32.)++0x00 line.long 0x00 "PIDR32,Processor ID register 32" rgroup.long c14:(832.+33.)++0x00 line.long 0x00 "PIDR33,Processor ID register 33" rgroup.long c14:(832.+34.)++0x00 line.long 0x00 "PIDR34,Processor ID register 34" rgroup.long c14:(832.+35.)++0x00 line.long 0x00 "PIDR35,Processor ID register 35" rgroup.long c14:(832.+36.)++0x00 line.long 0x00 "PIDR36,Processor ID register 36" rgroup.long c14:(832.+37.)++0x00 line.long 0x00 "PIDR37,Processor ID register 37" rgroup.long c14:(832.+38.)++0x00 line.long 0x00 "PIDR38,Processor ID register 38" rgroup.long c14:(832.+39.)++0x00 line.long 0x00 "PIDR39,Processor ID register 39" rgroup.long c14:(832.+40.)++0x00 line.long 0x00 "PIDR40,Processor ID register 40" rgroup.long c14:(832.+41.)++0x00 line.long 0x00 "PIDR41,Processor ID register 41" rgroup.long c14:(832.+42.)++0x00 line.long 0x00 "PIDR42,Processor ID register 42" rgroup.long c14:(832.+43.)++0x00 line.long 0x00 "PIDR43,Processor ID register 43" rgroup.long c14:(832.+44.)++0x00 line.long 0x00 "PIDR44,Processor ID register 44" rgroup.long c14:(832.+45.)++0x00 line.long 0x00 "PIDR45,Processor ID register 45" rgroup.long c14:(832.+46.)++0x00 line.long 0x00 "PIDR46,Processor ID register 46" rgroup.long c14:(832.+47.)++0x00 line.long 0x00 "PIDR47,Processor ID register 47" rgroup.long c14:(832.+48.)++0x00 line.long 0x00 "PIDR48,Processor ID register 48" rgroup.long c14:(832.+49.)++0x00 line.long 0x00 "PIDR49,Processor ID register 49" rgroup.long c14:(832.+50.)++0x00 line.long 0x00 "PIDR50,Processor ID register 50" rgroup.long c14:(832.+51.)++0x00 line.long 0x00 "PIDR51,Processor ID register 51" rgroup.long c14:(832.+52.)++0x00 line.long 0x00 "PIDR52,Processor ID register 52" rgroup.long c14:(832.+53.)++0x00 line.long 0x00 "PIDR53,Processor ID register 53" rgroup.long c14:(832.+54.)++0x00 line.long 0x00 "PIDR54,Processor ID register 54" rgroup.long c14:(832.+55.)++0x00 line.long 0x00 "PIDR55,Processor ID register 55" rgroup.long c14:(832.+56.)++0x00 line.long 0x00 "PIDR56,Processor ID register 56" rgroup.long c14:(832.+57.)++0x00 line.long 0x00 "PIDR57,Processor ID register 57" rgroup.long c14:(832.+58.)++0x00 line.long 0x00 "PIDR58,Processor ID register 58" rgroup.long c14:(832.+59.)++0x00 line.long 0x00 "PIDR59,Processor ID register 59" rgroup.long c14:(832.+60.)++0x00 line.long 0x00 "PIDR60,Processor ID register 60" rgroup.long c14:(832.+61.)++0x00 line.long 0x00 "PIDR61,Processor ID register 61" rgroup.long c14:(832.+62.)++0x00 line.long 0x00 "PIDR62,Processor ID register 62" rgroup.long c14:(832.+63.)++0x00 line.long 0x00 "PIDR63,Processor ID register 63" tree.end tree "Coresight Management Registers" group.long c14:960.++0x0 line.long 0x00 "DBGITCTRL,Debug Integration Mode Control Register" bitfld.long 0x00 0. " IME ,Integration Mode Enable" "Disabled,Enabled" group.long c14:1000.++0x0 line.long 0x0 "DBGCLAIMSET,Claim Tag Set Register" bitfld.long 0x0 7. " CT7 ,Claim Tag 7 Set" "Not set,Set" bitfld.long 0x0 6. " CT6 ,Claim Tag 6 Set" "Not set,Set" bitfld.long 0x0 5. " CT5 ,Claim Tag 5 Set" "Not set,Set" textline " " bitfld.long 0x0 4. " CT4 ,Claim Tag 4 Set" "Not set,Set" bitfld.long 0x0 3. " CT3 ,Claim Tag 3 Set" "Not set,Set" bitfld.long 0x0 2. " CT2 ,Claim Tag 2 Set" "Not set,Set" textline " " bitfld.long 0x0 1. " CT1 ,Claim Tag 1 Set" "Not set,Set" bitfld.long 0x0 0. " CT0 ,Claim Tag 0 Set" "Not set,Set" group.long c14:1001.++0x0 line.long 0x0 "DBGCLAIMCLR,Claim Tag Clear Register" bitfld.long 0x0 7. " CT7 ,Claim Tag 7 Clear" "Not cleared,Cleared" bitfld.long 0x0 6. " CT6 ,Claim Tag 6 Clear" "Not cleared,Cleared" bitfld.long 0x0 5. " CT5 ,Claim Tag 5 Clear" "Not cleared,Cleared" textline " " bitfld.long 0x0 4. " CT4 ,Claim Tag 4 Clear" "Not cleared,Cleared" bitfld.long 0x0 3. " CT3 ,Claim Tag 3 Clear" "Not cleared,Cleared" bitfld.long 0x0 2. " CT2 ,Claim Tag 2 Clear" "Not cleared,Cleared" textline " " bitfld.long 0x0 1. " CT1 ,Claim Tag 1 Clear" "Not cleared,Cleared" bitfld.long 0x0 0. " CT0 ,Claim Tag 0 Clear" "Not cleared,Cleared" wgroup.long c14:1004.++0x00 line.long 0x00 "DBGLAR,Lock Access Register" rgroup.long c14:1005.++0x00 line.long 0x00 "DBGLSR,Lock Status Register" bitfld.long 0x00 2. " NTT ,Not 32-bit access" "32-bit,Not 32-bit" bitfld.long 0x00 1. " SLK ,Software Lock status" "Not locked,Locked" bitfld.long 0x00 0. " SLI ,Software Lock Implemented" "Not implemented,Implemented" textline " " rgroup.long c14:1006.++0x0 line.long 0x0 "DBGAUTHSTATUS,Debug Authentication Status Register" bitfld.long 0x00 7. " SNI ,Secure non-invasive debug features implementation" "No effect,Implemented" bitfld.long 0x00 6. " SNE ,Secure non-invasive debug enable (DBGEN OR NIDEN) AND (SPIDEN OR SPNIDEN)" "Disabled,Enabled" bitfld.long 0x00 5. " SI ,Secure invasive debug features implementation" "No effect,Implemented" textline " " bitfld.long 0x00 4. " SE ,Secure invasive debug enable (DBGEN AND SPIDEN)" "Disabled,Enabled" bitfld.long 0x00 3. " NSNI ,Non-secure non-invasive debug features implementation" "Not implemented,Implemented" bitfld.long 0x00 2. " NSNE ,Non-secure non-invasive debug enable (DBGEN OR NIDEN)" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " NSI ,Non-secure invasive debug features implementation" "Not implemented,Implemented" bitfld.long 0x00 0. " NSE ,Non-secure invasive debug enable (DBGEN)" "Disabled,Enabled" textline " " if (corename()=="CORTEXA15"||corename()=="CORTEXA15MPCORE"||corename()=="CORTEXA17"||corename()=="CORTEXA17MPCORE") rgroup.long c14:1009.++0x0 line.long 0x0 "DBGDEVID1,Debug Device ID Register 1" bitfld.long 0x00 0.--3. " PCSROFFSET ,Defines the offset applied to DBGPCSR samples" "Depends on instr set state,No offset,?..." elif (corename()=="CORTEXA7"||corename()=="CORTEXA7MPCORE") rgroup.long c14:1009.++0x0 line.long 0x0 "DBGDEVID1,Debug Device ID Register 1" bitfld.long 0x00 0.--3. " PCSROFFSET ,Defines the offset applied to DBGPCSR samples" "Reserved,No offset,?..." endif textline " " rgroup.long c14:1010.++0x0 line.long 0x0 "DBGDEVID0,Debug Device ID Register 0" bitfld.long 0x0 24.--27. " AR ,Debug External Auxiliary Control Register support status" "Reserved,Supported,?..." bitfld.long 0x0 20.--23. " DL ,Support for Debug OS Double Lock Register" "Reserved,Supported,?..." bitfld.long 0x0 16.--19. " VE ,Specifies implementation of Virtualization Extension" "Reserved,Implemented,?..." textline " " bitfld.long 0x0 12.--15. " VC ,Form of the vector catch event implemented" "Implemented,?..." bitfld.long 0x0 8.--11. " BPAM ,Level of support for Immediate Virtual Address matching breakpoint masking capability" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Not implemented" bitfld.long 0x0 4.--7. " WPAM ,Level of support for the DVA matching watchpoint masking capability" "Reserved,Implemented,?..." textline " " bitfld.long 0x0 0.--3. " PCS ,Level of support for Program Counter sampling using debug registers 40 and 41" "Reserved,Reserved,Reserved,Implemented,?..." textline " " rgroup.long c14:1011.++0x00 line.long 0x00 "DBGDEVTYPE,Debug Device Type Register" bitfld.long 0x00 4.--7. " T ,Sub type" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " C ,Main class" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long c14:1016.++0x00 line.long 0x00 "DBGPID0,Debug Peripheral ID 0" hexmask.long.byte 0x00 0.--7. 1. " PN[7:0] ,Part Number [7:0]" rgroup.long c14:1017.++0x00 line.long 0x00 "DBGPID1,Debug Peripheral ID 1" hexmask.long.byte 0x00 4.--7. 1. " JEPID[3:0] ,JEP Identity Code[3:0]" hexmask.long.byte 0x00 0.--3. 1. " PN[11:8] ,Part Number [11:8]" rgroup.long c14:1018.++0x00 line.long 0x00 "DBGPID2,Debug Peripheral ID 2" hexmask.long.byte 0x00 4.--7. 1. " REV ,Revision" bitfld.long 0x00 3. " UJEPCODE ,Uses JEP Code" "Disabled,Enabled" hexmask.long.byte 0x00 0.--2. 1. " JEPID[6:4] ,JEP Identity Code[6:4]" rgroup.long c14:1019.++0x00 line.long 0x00 "DBGPID3,Debug Peripheral ID 3" hexmask.long.byte 0x00 4.--7. 1. " REVAND ,Manufacturing revision" hexmask.long.byte 0x00 0.--3. 1. " CM ,Customer modified" rgroup.long c14:1012.++0x00 line.long 0x00 "DBGPID4,Debug Peripheral ID 4" hexmask.long.byte 0x00 4.--7. 1. " 4KB_COUNT ,4KB count" hexmask.long.byte 0x00 0.--3. 1. " JEP106_CONT_CODE ,JEP 106 Continuation code" rgroup.long c14:1020.++0x00 line.long 0x00 "DBGCID0,Debug Component ID 0" hexmask.long.byte 0x00 0.--7. 1. " PREAMBLE ,Preamble byte 0" rgroup.long c14:1021.++0x00 line.long 0x00 "DBGCID1,Debug Component ID 1" hexmask.long.byte 0x00 4.--7. 1. " CC ,Component class" hexmask.long.byte 0x00 0.--3. 1. " PREAMBLE ,Preamble byte 1" rgroup.long c14:1022.++0x00 line.long 0x00 "DBGCID2,Debug Component ID 2" hexmask.long.byte 0x00 0.--7. 1. " PREAMBLE ,Preamble byte 2" rgroup.long c14:1023.++0x00 line.long 0x00 "DBGCID3,Debug Component ID 3" hexmask.long.byte 0x00 0.--7. 1. " PREAMBLE ,Preamble byte 3" tree.end tree.end width 10. tree "Breakpoint Registers" if ((d.l(c14:80.+0.)&0x500000)==(0x500000||0x400000||0x100000||0x0)) group.long c14:(64.+0.)++0x0 line.long 0x00 "DBGBVR0,Breakpoint Value Register(Address comparison)" hexmask.long 0x00 2.--31. 0x4 " INSTADDR ,Address value for comparison. Bits 2-31" else group.long c14:(64.+0.)++0x0 line.long 0x00 "DBGBVR0,Breakpoint Value Register(Context matching)" endif group.long c14:(80.+0.)++0x0 line.long 0x00 "DBGBCR0,Breakpoint Control Register" bitfld.long 0x00 20.--23. " BT ,Breakpoint Type. Match - m / Mismatch - mm" "Unlinked instr addr m,Linked instr addr m,Unlinked Context ID m,Linked Context ID m,Unlinked instr addr mm,Linked instr addr mm,Reserved,Reserved,Unlinked VMID m,Linked VMID m,Unlinked VMID/Context ID m,Linked VMID/Context ID m,?..." bitfld.long 0x00 16.--19. " LBN ,Linked Breakpoint Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 14.--15. " SSC ,Security state control" "Both,Non-secure,Secure,Non-secure" textline " " bitfld.long 0x00 13. " HMC ,Hyp mode control bit" "0,1" bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1" bitfld.long 0x0 7. ",Byte 2 address select" "0,1" bitfld.long 0x0 6. ",Byte 1 address select" "0,1" bitfld.long 0x0 5. ",Byte 0 address select" "0,1" textline " " bitfld.long 0x00 1.--2. " PMC ,Privileged mode control" "User/System/Supervisor/Hyp,PL1/Hyp,User only,Any mode" bitfld.long 0x00 0. " E ,Breakpoint enable" "Disabled,Enabled" if ((d.l(c14:80.+1.)&0x500000)==(0x500000||0x400000||0x100000||0x0)) group.long c14:(64.+1.)++0x0 line.long 0x00 "DBGBVR1,Breakpoint Value Register(Address comparison)" hexmask.long 0x00 2.--31. 0x4 " INSTADDR ,Address value for comparison. Bits 2-31" else group.long c14:(64.+1.)++0x0 line.long 0x00 "DBGBVR1,Breakpoint Value Register(Context matching)" endif group.long c14:(80.+1.)++0x0 line.long 0x00 "DBGBCR1,Breakpoint Control Register" bitfld.long 0x00 20.--23. " BT ,Breakpoint Type. Match - m / Mismatch - mm" "Unlinked instr addr m,Linked instr addr m,Unlinked Context ID m,Linked Context ID m,Unlinked instr addr mm,Linked instr addr mm,Reserved,Reserved,Unlinked VMID m,Linked VMID m,Unlinked VMID/Context ID m,Linked VMID/Context ID m,?..." bitfld.long 0x00 16.--19. " LBN ,Linked Breakpoint Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 14.--15. " SSC ,Security state control" "Both,Non-secure,Secure,Non-secure" textline " " bitfld.long 0x00 13. " HMC ,Hyp mode control bit" "0,1" bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1" bitfld.long 0x0 7. ",Byte 2 address select" "0,1" bitfld.long 0x0 6. ",Byte 1 address select" "0,1" bitfld.long 0x0 5. ",Byte 0 address select" "0,1" textline " " bitfld.long 0x00 1.--2. " PMC ,Privileged mode control" "User/System/Supervisor/Hyp,PL1/Hyp,User only,Any mode" bitfld.long 0x00 0. " E ,Breakpoint enable" "Disabled,Enabled" if ((d.l(c14:80.+2.)&0x500000)==(0x500000||0x400000||0x100000||0x0)) group.long c14:(64.+2.)++0x0 line.long 0x00 "DBGBVR2,Breakpoint Value Register(Address comparison)" hexmask.long 0x00 2.--31. 0x4 " INSTADDR ,Address value for comparison. Bits 2-31" else group.long c14:(64.+2.)++0x0 line.long 0x00 "DBGBVR2,Breakpoint Value Register(Context matching)" endif group.long c14:(80.+2.)++0x0 line.long 0x00 "DBGBCR2,Breakpoint Control Register" bitfld.long 0x00 20.--23. " BT ,Breakpoint Type. Match - m / Mismatch - mm" "Unlinked instr addr m,Linked instr addr m,Unlinked Context ID m,Linked Context ID m,Unlinked instr addr mm,Linked instr addr mm,Reserved,Reserved,Unlinked VMID m,Linked VMID m,Unlinked VMID/Context ID m,Linked VMID/Context ID m,?..." bitfld.long 0x00 16.--19. " LBN ,Linked Breakpoint Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 14.--15. " SSC ,Security state control" "Both,Non-secure,Secure,Non-secure" textline " " bitfld.long 0x00 13. " HMC ,Hyp mode control bit" "0,1" bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1" bitfld.long 0x0 7. ",Byte 2 address select" "0,1" bitfld.long 0x0 6. ",Byte 1 address select" "0,1" bitfld.long 0x0 5. ",Byte 0 address select" "0,1" textline " " bitfld.long 0x00 1.--2. " PMC ,Privileged mode control" "User/System/Supervisor/Hyp,PL1/Hyp,User only,Any mode" bitfld.long 0x00 0. " E ,Breakpoint enable" "Disabled,Enabled" if ((d.l(c14:80.+3.)&0x500000)==(0x500000||0x400000||0x100000||0x0)) group.long c14:(64.+3.)++0x0 line.long 0x00 "DBGBVR3,Breakpoint Value Register(Address comparison)" hexmask.long 0x00 2.--31. 0x4 " INSTADDR ,Address value for comparison. Bits 2-31" else group.long c14:(64.+3.)++0x0 line.long 0x00 "DBGBVR3,Breakpoint Value Register(Context matching)" endif group.long c14:(80.+3.)++0x0 line.long 0x00 "DBGBCR3,Breakpoint Control Register" bitfld.long 0x00 20.--23. " BT ,Breakpoint Type. Match - m / Mismatch - mm" "Unlinked instr addr m,Linked instr addr m,Unlinked Context ID m,Linked Context ID m,Unlinked instr addr mm,Linked instr addr mm,Reserved,Reserved,Unlinked VMID m,Linked VMID m,Unlinked VMID/Context ID m,Linked VMID/Context ID m,?..." bitfld.long 0x00 16.--19. " LBN ,Linked Breakpoint Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 14.--15. " SSC ,Security state control" "Both,Non-secure,Secure,Non-secure" textline " " bitfld.long 0x00 13. " HMC ,Hyp mode control bit" "0,1" bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1" bitfld.long 0x0 7. ",Byte 2 address select" "0,1" bitfld.long 0x0 6. ",Byte 1 address select" "0,1" bitfld.long 0x0 5. ",Byte 0 address select" "0,1" textline " " bitfld.long 0x00 1.--2. " PMC ,Privileged mode control" "User/System/Supervisor/Hyp,PL1/Hyp,User only,Any mode" bitfld.long 0x00 0. " E ,Breakpoint enable" "Disabled,Enabled" if ((d.l(c14:80.+4.)&0x500000)==(0x500000||0x400000||0x100000||0x0)) group.long c14:(64.+4.)++0x0 line.long 0x00 "DBGBVR4,Breakpoint Value Register(Address comparison)" hexmask.long 0x00 2.--31. 0x4 " INSTADDR ,Address value for comparison. Bits 2-31" else group.long c14:(64.+4.)++0x0 line.long 0x00 "DBGBVR4,Breakpoint Value Register(Context matching)" endif group.long c14:(80.+4.)++0x0 line.long 0x00 "DBGBCR4,Breakpoint Control Register" bitfld.long 0x00 20.--23. " BT ,Breakpoint Type. Match - m / Mismatch - mm" "Unlinked instr addr m,Linked instr addr m,Unlinked Context ID m,Linked Context ID m,Unlinked instr addr mm,Linked instr addr mm,Reserved,Reserved,Unlinked VMID m,Linked VMID m,Unlinked VMID/Context ID m,Linked VMID/Context ID m,?..." bitfld.long 0x00 16.--19. " LBN ,Linked Breakpoint Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 14.--15. " SSC ,Security state control" "Both,Non-secure,Secure,Non-secure" textline " " bitfld.long 0x00 13. " HMC ,Hyp mode control bit" "0,1" bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1" bitfld.long 0x0 7. ",Byte 2 address select" "0,1" bitfld.long 0x0 6. ",Byte 1 address select" "0,1" bitfld.long 0x0 5. ",Byte 0 address select" "0,1" textline " " bitfld.long 0x00 1.--2. " PMC ,Privileged mode control" "User/System/Supervisor/Hyp,PL1/Hyp,User only,Any mode" bitfld.long 0x00 0. " E ,Breakpoint enable" "Disabled,Enabled" if ((d.l(c14:80.+5.)&0x500000)==(0x500000||0x400000||0x100000||0x0)) group.long c14:(64.+5.)++0x0 line.long 0x00 "DBGBVR5,Breakpoint Value Register(Address comparison)" hexmask.long 0x00 2.--31. 0x4 " INSTADDR ,Address value for comparison. Bits 2-31" else group.long c14:(64.+5.)++0x0 line.long 0x00 "DBGBVR5,Breakpoint Value Register(Context matching)" endif group.long c14:(80.+5.)++0x0 line.long 0x00 "DBGBCR5,Breakpoint Control Register" bitfld.long 0x00 20.--23. " BT ,Breakpoint Type. Match - m / Mismatch - mm" "Unlinked instr addr m,Linked instr addr m,Unlinked Context ID m,Linked Context ID m,Unlinked instr addr mm,Linked instr addr mm,Reserved,Reserved,Unlinked VMID m,Linked VMID m,Unlinked VMID/Context ID m,Linked VMID/Context ID m,?..." bitfld.long 0x00 16.--19. " LBN ,Linked Breakpoint Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 14.--15. " SSC ,Security state control" "Both,Non-secure,Secure,Non-secure" textline " " bitfld.long 0x00 13. " HMC ,Hyp mode control bit" "0,1" bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1" bitfld.long 0x0 7. ",Byte 2 address select" "0,1" bitfld.long 0x0 6. ",Byte 1 address select" "0,1" bitfld.long 0x0 5. ",Byte 0 address select" "0,1" textline " " bitfld.long 0x00 1.--2. " PMC ,Privileged mode control" "User/System/Supervisor/Hyp,PL1/Hyp,User only,Any mode" bitfld.long 0x00 0. " E ,Breakpoint enable" "Disabled,Enabled" group.long c14:148.++0x0 line.long 0x00 "DBGBXVR0,Debug Breakpoint Extended Value Register" hexmask.long.byte 0x00 0.--7. 1. " VMID , VMID value" group.long c14:149.++0x0 line.long 0x00 "DBGBXVR1,Debug Breakpoint Extended Value Register" hexmask.long.byte 0x00 0.--7. 1. " VMID , VMID value" tree.end width 10. tree "Watchpoint Control Registers" group.long c14:(96.+0.)++0x00 line.long 0x00 "DBGWVR0,Watchpoint Value Register" hexmask.long 0x00 2.--31. 0x4 " DA ,Data address" if (corename()=="CORTEXA17"||corename()=="CORTEXA17MPCORE") group.long c14:(112.+0.)++0x00 line.long 0x00 "DBGWCR0,Watchpoint Control Register" bitfld.long 0x0 24.--28. " Mask ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x0 20. " WT ,Watchpoint Type" "Unlinked data addr match,Linked data addr match" bitfld.long 0x0 16.--19. " LBN ,Linked breakpoint number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" textline " " bitfld.long 0x0 14.--15. " SSC ,Secure state control" "Both,Non-secure,Secure,Non-secure" bitfld.long 0x0 13. " HMC ,Hyp Mode Control" "0,1" bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1" bitfld.long 0x0 7. ",Byte 2 address select" "0,1" bitfld.long 0x0 6. ",Byte 1 address select" "0,1" bitfld.long 0x0 5. ",Byte 0 address select" "0,1" textline " " bitfld.long 0x0 3.--4. " LSC ,Load/store access control" "Reserved,Load,Store,Any" bitfld.long 0x0 1.--2. " PAC ,Privileged Access control" "Hyp,Privileged,Unprivileged,Any" bitfld.long 0x0 0. " E ,Watchpoint enable" "Disabled,Enabled" elif (corename()=="CORTEXA15"||corename()=="CORTEXA15MPCORE"||corename()=="CORTEXA7"||corename()=="CORTEXA7MPCORE") group.long c14:(112.+0.)++0x00 line.long 0x00 "DBGWCR0,Watchpoint Control Register" bitfld.long 0x0 24.--28. " MASK ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x0 20. " WT ,Watchpoint Type" "Disabled,Enabled" bitfld.long 0x0 16.--19. " LBN ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" textline " " bitfld.long 0x0 14.--15. " SSC ,Secure state control" "Both,Non-secure,Secure,?..." bitfld.long 0x0 13. " HMC ,Hyp Mode Control" "Disabled,Enabled" bitfld.long 0x0 12. " BAS ,Byte 7 address select" "0,1" bitfld.long 0x0 11. ",Byte 6 address select" "0,1" bitfld.long 0x0 10. ",Byte 5 address select" "0,1" bitfld.long 0x0 9. ",Byte 4 address select" "0,1" bitfld.long 0x0 8. ",Byte 3 address select" "0,1" bitfld.long 0x0 7. ",Byte 2 address select" "0,1" bitfld.long 0x0 6. ",Byte 1 address select" "0,1" bitfld.long 0x0 5. ",Byte 0 address select" "0,1" textline " " bitfld.long 0x0 3.--4. " LSC ,Load/Store access control" "Reserved,Load,Store,Any" bitfld.long 0x0 1.--2. " PAC ,Privileged Access control" "Reserved,Match privileged accesses,Match unprivileged accesses,Match all accesses" textline " " bitfld.long 0x0 0. " WE ,Watchpoint enable" "Disabled,Enabled" endif group.long c14:(96.+1.)++0x00 line.long 0x00 "DBGWVR1,Watchpoint Value Register" hexmask.long 0x00 2.--31. 0x4 " DA ,Data address" if (corename()=="CORTEXA17"||corename()=="CORTEXA17MPCORE") group.long c14:(112.+1.)++0x00 line.long 0x00 "DBGWCR1,Watchpoint Control Register" bitfld.long 0x0 24.--28. " Mask ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x0 20. " WT ,Watchpoint Type" "Unlinked data addr match,Linked data addr match" bitfld.long 0x0 16.--19. " LBN ,Linked breakpoint number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" textline " " bitfld.long 0x0 14.--15. " SSC ,Secure state control" "Both,Non-secure,Secure,Non-secure" bitfld.long 0x0 13. " HMC ,Hyp Mode Control" "0,1" bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1" bitfld.long 0x0 7. ",Byte 2 address select" "0,1" bitfld.long 0x0 6. ",Byte 1 address select" "0,1" bitfld.long 0x0 5. ",Byte 0 address select" "0,1" textline " " bitfld.long 0x0 3.--4. " LSC ,Load/store access control" "Reserved,Load,Store,Any" bitfld.long 0x0 1.--2. " PAC ,Privileged Access control" "Hyp,Privileged,Unprivileged,Any" bitfld.long 0x0 0. " E ,Watchpoint enable" "Disabled,Enabled" elif (corename()=="CORTEXA15"||corename()=="CORTEXA15MPCORE"||corename()=="CORTEXA7"||corename()=="CORTEXA7MPCORE") group.long c14:(112.+1.)++0x00 line.long 0x00 "DBGWCR1,Watchpoint Control Register" bitfld.long 0x0 24.--28. " MASK ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x0 20. " WT ,Watchpoint Type" "Disabled,Enabled" bitfld.long 0x0 16.--19. " LBN ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" textline " " bitfld.long 0x0 14.--15. " SSC ,Secure state control" "Both,Non-secure,Secure,?..." bitfld.long 0x0 13. " HMC ,Hyp Mode Control" "Disabled,Enabled" bitfld.long 0x0 12. " BAS ,Byte 7 address select" "0,1" bitfld.long 0x0 11. ",Byte 6 address select" "0,1" bitfld.long 0x0 10. ",Byte 5 address select" "0,1" bitfld.long 0x0 9. ",Byte 4 address select" "0,1" bitfld.long 0x0 8. ",Byte 3 address select" "0,1" bitfld.long 0x0 7. ",Byte 2 address select" "0,1" bitfld.long 0x0 6. ",Byte 1 address select" "0,1" bitfld.long 0x0 5. ",Byte 0 address select" "0,1" textline " " bitfld.long 0x0 3.--4. " LSC ,Load/Store access control" "Reserved,Load,Store,Any" bitfld.long 0x0 1.--2. " PAC ,Privileged Access control" "Reserved,Match privileged accesses,Match unprivileged accesses,Match all accesses" textline " " bitfld.long 0x0 0. " WE ,Watchpoint enable" "Disabled,Enabled" endif group.long c14:(96.+2.)++0x00 line.long 0x00 "DBGWVR2,Watchpoint Value Register" hexmask.long 0x00 2.--31. 0x4 " DA ,Data address" if (corename()=="CORTEXA17"||corename()=="CORTEXA17MPCORE") group.long c14:(112.+2.)++0x00 line.long 0x00 "DBGWCR2,Watchpoint Control Register" bitfld.long 0x0 24.--28. " Mask ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x0 20. " WT ,Watchpoint Type" "Unlinked data addr match,Linked data addr match" bitfld.long 0x0 16.--19. " LBN ,Linked breakpoint number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" textline " " bitfld.long 0x0 14.--15. " SSC ,Secure state control" "Both,Non-secure,Secure,Non-secure" bitfld.long 0x0 13. " HMC ,Hyp Mode Control" "0,1" bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1" bitfld.long 0x0 7. ",Byte 2 address select" "0,1" bitfld.long 0x0 6. ",Byte 1 address select" "0,1" bitfld.long 0x0 5. ",Byte 0 address select" "0,1" textline " " bitfld.long 0x0 3.--4. " LSC ,Load/store access control" "Reserved,Load,Store,Any" bitfld.long 0x0 1.--2. " PAC ,Privileged Access control" "Hyp,Privileged,Unprivileged,Any" bitfld.long 0x0 0. " E ,Watchpoint enable" "Disabled,Enabled" elif (corename()=="CORTEXA15"||corename()=="CORTEXA15MPCORE"||corename()=="CORTEXA7"||corename()=="CORTEXA7MPCORE") group.long c14:(112.+2.)++0x00 line.long 0x00 "DBGWCR2,Watchpoint Control Register" bitfld.long 0x0 24.--28. " MASK ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x0 20. " WT ,Watchpoint Type" "Disabled,Enabled" bitfld.long 0x0 16.--19. " LBN ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" textline " " bitfld.long 0x0 14.--15. " SSC ,Secure state control" "Both,Non-secure,Secure,?..." bitfld.long 0x0 13. " HMC ,Hyp Mode Control" "Disabled,Enabled" bitfld.long 0x0 12. " BAS ,Byte 7 address select" "0,1" bitfld.long 0x0 11. ",Byte 6 address select" "0,1" bitfld.long 0x0 10. ",Byte 5 address select" "0,1" bitfld.long 0x0 9. ",Byte 4 address select" "0,1" bitfld.long 0x0 8. ",Byte 3 address select" "0,1" bitfld.long 0x0 7. ",Byte 2 address select" "0,1" bitfld.long 0x0 6. ",Byte 1 address select" "0,1" bitfld.long 0x0 5. ",Byte 0 address select" "0,1" textline " " bitfld.long 0x0 3.--4. " LSC ,Load/Store access control" "Reserved,Load,Store,Any" bitfld.long 0x0 1.--2. " PAC ,Privileged Access control" "Reserved,Match privileged accesses,Match unprivileged accesses,Match all accesses" textline " " bitfld.long 0x0 0. " WE ,Watchpoint enable" "Disabled,Enabled" endif group.long c14:(96.+3.)++0x00 line.long 0x00 "DBGWVR3,Watchpoint Value Register" hexmask.long 0x00 2.--31. 0x4 " DA ,Data address" if (corename()=="CORTEXA17"||corename()=="CORTEXA17MPCORE") group.long c14:(112.+3.)++0x00 line.long 0x00 "DBGWCR3,Watchpoint Control Register" bitfld.long 0x0 24.--28. " Mask ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x0 20. " WT ,Watchpoint Type" "Unlinked data addr match,Linked data addr match" bitfld.long 0x0 16.--19. " LBN ,Linked breakpoint number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" textline " " bitfld.long 0x0 14.--15. " SSC ,Secure state control" "Both,Non-secure,Secure,Non-secure" bitfld.long 0x0 13. " HMC ,Hyp Mode Control" "0,1" bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1" bitfld.long 0x0 7. ",Byte 2 address select" "0,1" bitfld.long 0x0 6. ",Byte 1 address select" "0,1" bitfld.long 0x0 5. ",Byte 0 address select" "0,1" textline " " bitfld.long 0x0 3.--4. " LSC ,Load/store access control" "Reserved,Load,Store,Any" bitfld.long 0x0 1.--2. " PAC ,Privileged Access control" "Hyp,Privileged,Unprivileged,Any" bitfld.long 0x0 0. " E ,Watchpoint enable" "Disabled,Enabled" elif (corename()=="CORTEXA15"||corename()=="CORTEXA15MPCORE"||corename()=="CORTEXA7"||corename()=="CORTEXA7MPCORE") group.long c14:(112.+3.)++0x00 line.long 0x00 "DBGWCR3,Watchpoint Control Register" bitfld.long 0x0 24.--28. " MASK ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x0 20. " WT ,Watchpoint Type" "Disabled,Enabled" bitfld.long 0x0 16.--19. " LBN ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" textline " " bitfld.long 0x0 14.--15. " SSC ,Secure state control" "Both,Non-secure,Secure,?..." bitfld.long 0x0 13. " HMC ,Hyp Mode Control" "Disabled,Enabled" bitfld.long 0x0 12. " BAS ,Byte 7 address select" "0,1" bitfld.long 0x0 11. ",Byte 6 address select" "0,1" bitfld.long 0x0 10. ",Byte 5 address select" "0,1" bitfld.long 0x0 9. ",Byte 4 address select" "0,1" bitfld.long 0x0 8. ",Byte 3 address select" "0,1" bitfld.long 0x0 7. ",Byte 2 address select" "0,1" bitfld.long 0x0 6. ",Byte 1 address select" "0,1" bitfld.long 0x0 5. ",Byte 0 address select" "0,1" textline " " bitfld.long 0x0 3.--4. " LSC ,Load/Store access control" "Reserved,Load,Store,Any" bitfld.long 0x0 1.--2. " PAC ,Privileged Access control" "Reserved,Match privileged accesses,Match unprivileged accesses,Match all accesses" textline " " bitfld.long 0x0 0. " WE ,Watchpoint enable" "Disabled,Enabled" endif tree.end width 0xb tree.open "Interrupt Controller (GIC-400)" width 17. width 17. base ad:0xA0021000 tree "Distributor Interface" if (((per.l(ad:0xA0021000+0x04))&0x400)==0x400) if PER.ADDRESS.isSECUREEX(ad:0xA0021000) group.long 0x0000++0x03 line.long 0x00 "GICD_CTLR,Distributor Control Register (Secure access)" bitfld.long 0x00 1. " ENABLEGRP1 ,Global Interrupt Enable Group 1" "Disabled,Enabled" bitfld.long 0x00 0. " ENABLEGRP0 ,Global Interrupt Enable Group 1" "Disabled,Enabled" else group.long 0x0000++0x03 line.long 0x00 "GICD_CTLR,Distributor Control Register (Non-secure access)" bitfld.long 0x00 0. " ENABLE ,Global enable for forwarding pending interrupts from the Distributor to the CPU interfaces" "Disabled,Enabled" endif else group.long 0x0000++0x03 line.long 0x00 "GICD_CTLR,Distributor Control Register" bitfld.long 0x00 0. " ENABLE ,Global enable for forwarding pending interrupts from the Distributor to the CPU interfaces" "Disabled,Enabled" endif if (((per.l(ad:0xA0021000+0x04))&0x400)==0x400) rgroup.long 0x0004++0x03 line.long 0x00 "GICD_TYPER,Interrupt Controller Type Register" bitfld.long 0x00 11.--15. " LSPI ,Locable Shared Peripheral Interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 10. " SECURITYEXTN ,Indicate whether interrupt controller implements the security extensions" "Not implemented,Implemented" textline " " bitfld.long 0x00 5.--7. " CPUNUMBER ,Indicates the number of implemented CPU interfaces" "1,2,3,4,?..." bitfld.long 0x00 0.--4. " ITLN ,Indicates the number of interrupts that the interrupt controller supports" "Up to 32,Up to 64,Up to 96,Up to 128,Up to 160,Up to 192,Up to 224,Up to 256,Up to 288,Up to 320,Up to 352,Up to 384,Up to 416,Up to 448,Up to 480,Up to 512,Up to 544,Up to 576,Up to 608,Up to 640,Up to 672,Up to 704,Up to 736,Up to 768,Up to 800,Up to 832,Up to 864,Up to 896,Up to 928,Up to 960,Up to 992,Up to 1020" else rgroup.long 0x0004++0x03 line.long 0x00 "GICD_TYPER,Interrupt Controller Type Register" bitfld.long 0x00 10. " SECURITYEXTN ,Indicates whether interrupt controller implements the security extensions" "Not implemented,Implemented" textline " " bitfld.long 0x00 5.--7. " CPUNUMBER ,Indicates the number of implemented CPU interfaces" "1,2,3,4,?..." bitfld.long 0x00 0.--4. " ITLN ,Indicates the number of interrupts that the interrupt controller supports" "Up to 32,Up to 64,Up to 96,Up to 128,Up to 160,Up to 192,Up to 224,Up to 256,Up to 288,Up to 320,Up to 352,Up to 384,Up to 416,Up to 448,Up to 480,Up to 512,Up to 544,Up to 576,Up to 608,Up to 640,Up to 672,Up to 704,Up to 736,Up to 768,Up to 800,Up to 832,Up to 864,Up to 896,Up to 928,Up to 960,Up to 992,Up to 1020" endif rgroup.long 0x0008++0x03 line.long 0x00 "GICD_IIDR,Distributor Implementer Identification Register" bitfld.long 0x00 24.--31. " PRODID ,Indicates the product ID" "PL390,PL390,GIC400,GIC400,?..." bitfld.long 0x00 16.--19. " VAR ,Major revison number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 12.--15. " REV ,Minor revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x00 0.--11. 1. " IMP ,Implementer" sif CPU.FEATURE(hypervisor)||CPU.FEATURE(secure) width 17. tree "Group/Security Registers" if PER.ADDRESS.isSECUREEX(ad:0xA0021000+0x0080) group.long 0x0080++0x03 line.long 0x0 "GICD_IGROUPR0,Interrupt Group Register 0 (Secure Access)" bitfld.long 0x00 31. " GSB31 ,Group Status Bit 31" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 30. " GSB30 ,Group Status Bit 30" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 29. " GSB29 ,Group Status Bit 29" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 28. " GSB28 ,Group Status Bit 28" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 27. " GSB27 ,Group Status Bit 27" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 26. " GSB26 ,Group Status Bit 26" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 25. " GSB25 ,Group Status Bit 25" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 24. " GSB24 ,Group Status Bit 24" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 23. " GSB23 ,Group Status Bit 23" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 22. " GSB22 ,Group Status Bit 22" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 21. " GSB21 ,Group Status Bit 21" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 20. " GSB20 ,Group Status Bit 20" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 19. " GSB19 ,Group Status Bit 19" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 18. " GSB18 ,Group Status Bit 18" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 17. " GSB17 ,Group Status Bit 17" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 16. " GSB16 ,Group Status Bit 16" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 15. " GSB15 ,Group Status Bit 15" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 14. " GSB14 ,Group Status Bit 14" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 13. " GSB13 ,Group Status Bit 13" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 12. " GSB12 ,Group Status Bit 12" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 11. " GSB11 ,Group Status Bit 11" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 10. " GSB10 ,Group Status Bit 10" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 9. " GSB9 ,Group Status Bit 9" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 8. " GSB8 ,Group Status Bit 8" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 7. " GSB7 ,Group Status Bit 7" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 6. " GSB6 ,Group Status Bit 6" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 5. " GSB5 ,Group Status Bit 5" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 4. " GSB4 ,Group Status Bit 4" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 3. " GSB3 ,Group Status Bit 3" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 2. " GSB2 ,Group Status Bit 2" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 1. " GSB1 ,Group Status Bit 1" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 0. " GSB0 ,Group Status Bit 0" "Group 0 (Secure),Group 1 (Non-secure)" else group.long 0x0080++0x03 line.long 0x0 "GICD_IGROUPR0,Interrupt Group Register 0 (Non-secure access)" bitfld.long 0x00 31. " GSB31 ,Group Status Bit 31" "Group 0,Group 1" bitfld.long 0x00 30. " GSB30 ,Group Status Bit 30" "Group 0,Group 1" bitfld.long 0x00 29. " GSB29 ,Group Status Bit 29" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB28 ,Group Status Bit 28" "Group 0,Group 1" bitfld.long 0x00 27. " GSB27 ,Group Status Bit 27" "Group 0,Group 1" bitfld.long 0x00 26. " GSB26 ,Group Status Bit 26" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB25 ,Group Status Bit 25" "Group 0,Group 1" bitfld.long 0x00 24. " GSB24 ,Group Status Bit 24" "Group 0,Group 1" bitfld.long 0x00 23. " GSB23 ,Group Status Bit 23" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB22 ,Group Status Bit 22" "Group 0,Group 1" bitfld.long 0x00 21. " GSB21 ,Group Status Bit 21" "Group 0,Group 1" bitfld.long 0x00 20. " GSB20 ,Group Status Bit 20" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB19 ,Group Status Bit 19" "Group 0,Group 1" bitfld.long 0x00 18. " GSB18 ,Group Status Bit 18" "Group 0,Group 1" bitfld.long 0x00 17. " GSB17 ,Group Status Bit 17" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB16 ,Group Status Bit 16" "Group 0,Group 1" bitfld.long 0x00 15. " GSB15 ,Group Status Bit 15" "Group 0,Group 1" bitfld.long 0x00 14. " GSB14 ,Group Status Bit 14" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB13 ,Group Status Bit 13" "Group 0,Group 1" bitfld.long 0x00 12. " GSB12 ,Group Status Bit 12" "Group 0,Group 1" bitfld.long 0x00 11. " GSB11 ,Group Status Bit 11" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB10 ,Group Status Bit 10" "Group 0,Group 1" bitfld.long 0x00 9. " GSB9 ,Group Status Bit 9" "Group 0,Group 1" bitfld.long 0x00 8. " GSB8 ,Group Status Bit 8" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB7 ,Group Status Bit 7" "Group 0,Group 1" bitfld.long 0x00 6. " GSB6 ,Group Status Bit 6" "Group 0,Group 1" bitfld.long 0x00 5. " GSB5 ,Group Status Bit 5" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB4 ,Group Status Bit 4" "Group 0,Group 1" bitfld.long 0x00 3. " GSB3 ,Group Status Bit 3" "Group 0,Group 1" bitfld.long 0x00 2. " GSB2 ,Group Status Bit 2" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB1 ,Group Status Bit 1" "Group 0,Group 1" bitfld.long 0x00 0. " GSB0 ,Group Status Bit 0" "Group 0,Group 1" endif if (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x01)&&(PER.ADDRESS.isSECUREEX(ad:0xA0021000+0x0084)) group.long 0x0084++0x03 line.long 0x0 "GICD_IGROUPR1,Interrupt Group Register 1 (Secure Access)" bitfld.long 0x00 31. " GSB63 ,Group Status Bit 63" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 30. " GSB62 ,Group Status Bit 62" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 29. " GSB61 ,Group Status Bit 61" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 28. " GSB60 ,Group Status Bit 60" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 27. " GSB59 ,Group Status Bit 59" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 26. " GSB58 ,Group Status Bit 58" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 25. " GSB57 ,Group Status Bit 57" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 24. " GSB56 ,Group Status Bit 56" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 23. " GSB55 ,Group Status Bit 55" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 22. " GSB54 ,Group Status Bit 54" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 21. " GSB53 ,Group Status Bit 53" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 20. " GSB52 ,Group Status Bit 52" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 19. " GSB51 ,Group Status Bit 51" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 18. " GSB50 ,Group Status Bit 50" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 17. " GSB49 ,Group Status Bit 49" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 16. " GSB48 ,Group Status Bit 48" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 15. " GSB47 ,Group Status Bit 47" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 14. " GSB46 ,Group Status Bit 46" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 13. " GSB45 ,Group Status Bit 45" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 12. " GSB44 ,Group Status Bit 44" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 11. " GSB43 ,Group Status Bit 43" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 10. " GSB42 ,Group Status Bit 42" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 9. " GSB41 ,Group Status Bit 41" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 8. " GSB40 ,Group Status Bit 40" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 7. " GSB39 ,Group Status Bit 39" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 6. " GSB38 ,Group Status Bit 38" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 5. " GSB37 ,Group Status Bit 37" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 4. " GSB36 ,Group Status Bit 36" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 3. " GSB35 ,Group Status Bit 35" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 2. " GSB34 ,Group Status Bit 34" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 1. " GSB33 ,Group Status Bit 33" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 0. " GSB32 ,Group Status Bit 32" "Group 0 (Secure),Group 1 (Non-secure)" elif (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x01) group.long 0x0084++0x03 line.long 0x0 "GICD_IGROUPR1,Interrupt Group Register 1 (Non-secure access)" bitfld.long 0x00 31. " GSB63 ,Group Status Bit 63" "Group 0,Group 1" bitfld.long 0x00 30. " GSB62 ,Group Status Bit 62" "Group 0,Group 1" bitfld.long 0x00 29. " GSB61 ,Group Status Bit 61" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB60 ,Group Status Bit 60" "Group 0,Group 1" bitfld.long 0x00 27. " GSB59 ,Group Status Bit 59" "Group 0,Group 1" bitfld.long 0x00 26. " GSB58 ,Group Status Bit 58" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB57 ,Group Status Bit 57" "Group 0,Group 1" bitfld.long 0x00 24. " GSB56 ,Group Status Bit 56" "Group 0,Group 1" bitfld.long 0x00 23. " GSB55 ,Group Status Bit 55" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB54 ,Group Status Bit 54" "Group 0,Group 1" bitfld.long 0x00 21. " GSB53 ,Group Status Bit 53" "Group 0,Group 1" bitfld.long 0x00 20. " GSB52 ,Group Status Bit 52" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB51 ,Group Status Bit 51" "Group 0,Group 1" bitfld.long 0x00 18. " GSB50 ,Group Status Bit 50" "Group 0,Group 1" bitfld.long 0x00 17. " GSB49 ,Group Status Bit 49" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB48 ,Group Status Bit 48" "Group 0,Group 1" bitfld.long 0x00 15. " GSB47 ,Group Status Bit 47" "Group 0,Group 1" bitfld.long 0x00 14. " GSB46 ,Group Status Bit 46" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB45 ,Group Status Bit 45" "Group 0,Group 1" bitfld.long 0x00 12. " GSB44 ,Group Status Bit 44" "Group 0,Group 1" bitfld.long 0x00 11. " GSB43 ,Group Status Bit 43" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB42 ,Group Status Bit 42" "Group 0,Group 1" bitfld.long 0x00 9. " GSB41 ,Group Status Bit 41" "Group 0,Group 1" bitfld.long 0x00 8. " GSB40 ,Group Status Bit 40" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB39 ,Group Status Bit 39" "Group 0,Group 1" bitfld.long 0x00 6. " GSB38 ,Group Status Bit 38" "Group 0,Group 1" bitfld.long 0x00 5. " GSB37 ,Group Status Bit 37" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB36 ,Group Status Bit 36" "Group 0,Group 1" bitfld.long 0x00 3. " GSB35 ,Group Status Bit 35" "Group 0,Group 1" bitfld.long 0x00 2. " GSB34 ,Group Status Bit 34" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB33 ,Group Status Bit 33" "Group 0,Group 1" bitfld.long 0x00 0. " GSB32 ,Group Status Bit 32" "Group 0,Group 1" else rgroup.long 0x0084++0x03 line.long 0x0 "GICD_IGROUPR1,Interrupt Group Register 1" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x02)&&(PER.ADDRESS.isSECUREEX(ad:0xA0021000+0x0088)) group.long 0x0088++0x03 line.long 0x0 "GICD_IGROUPR2,Interrupt Group Register 2 (Secure access)" bitfld.long 0x00 31. " GSB95 ,Group Status Bit 95" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 30. " GSB94 ,Group Status Bit 94" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 29. " GSB93 ,Group Status Bit 93" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 28. " GSB92 ,Group Status Bit 92" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 27. " GSB91 ,Group Status Bit 91" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 26. " GSB90 ,Group Status Bit 90" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 25. " GSB89 ,Group Status Bit 89" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 24. " GSB88 ,Group Status Bit 88" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 23. " GSB87 ,Group Status Bit 87" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 22. " GSB86 ,Group Status Bit 86" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 21. " GSB85 ,Group Status Bit 85" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 20. " GSB84 ,Group Status Bit 84" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 19. " GSB83 ,Group Status Bit 83" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 18. " GSB82 ,Group Status Bit 82" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 17. " GSB81 ,Group Status Bit 81" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 16. " GSB80 ,Group Status Bit 80" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 15. " GSB79 ,Group Status Bit 79" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 14. " GSB78 ,Group Status Bit 78" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 13. " GSB77 ,Group Status Bit 77" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 12. " GSB76 ,Group Status Bit 76" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 11. " GSB75 ,Group Status Bit 75" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 10. " GSB74 ,Group Status Bit 74" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 9. " GSB73 ,Group Status Bit 73" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 8. " GSB72 ,Group Status Bit 72" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 7. " GSB71 ,Group Status Bit 71" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 6. " GSB70 ,Group Status Bit 70" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 5. " GSB69 ,Group Status Bit 69" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 4. " GSB68 ,Group Status Bit 68" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 3. " GSB67 ,Group Status Bit 67" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 2. " GSB66 ,Group Status Bit 66" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 1. " GSB65 ,Group Status Bit 65" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 0. " GSB64 ,Group Status Bit 64" "Group 0 (Secure),Group 1 (Non-secure)" elif (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x02) group.long 0x0088++0x03 line.long 0x0 "GICD_IGROUPR2,Interrupt Group Register 2 (Non-secure access)" bitfld.long 0x00 31. " GSB95 ,Group Status Bit 95" "Group 0,Group 1" bitfld.long 0x00 30. " GSB94 ,Group Status Bit 94" "Group 0,Group 1" bitfld.long 0x00 29. " GSB93 ,Group Status Bit 93" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB92 ,Group Status Bit 92" "Group 0,Group 1" bitfld.long 0x00 27. " GSB91 ,Group Status Bit 91" "Group 0,Group 1" bitfld.long 0x00 26. " GSB90 ,Group Status Bit 90" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB89 ,Group Status Bit 89" "Group 0,Group 1" bitfld.long 0x00 24. " GSB88 ,Group Status Bit 88" "Group 0,Group 1" bitfld.long 0x00 23. " GSB87 ,Group Status Bit 87" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB86 ,Group Status Bit 86" "Group 0,Group 1" bitfld.long 0x00 21. " GSB85 ,Group Status Bit 85" "Group 0,Group 1" bitfld.long 0x00 20. " GSB84 ,Group Status Bit 84" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB83 ,Group Status Bit 83" "Group 0,Group 1" bitfld.long 0x00 18. " GSB82 ,Group Status Bit 82" "Group 0,Group 1" bitfld.long 0x00 17. " GSB81 ,Group Status Bit 81" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB80 ,Group Status Bit 80" "Group 0,Group 1" bitfld.long 0x00 15. " GSB79 ,Group Status Bit 79" "Group 0,Group 1" bitfld.long 0x00 14. " GSB78 ,Group Status Bit 78" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB77 ,Group Status Bit 77" "Group 0,Group 1" bitfld.long 0x00 12. " GSB76 ,Group Status Bit 76" "Group 0,Group 1" bitfld.long 0x00 11. " GSB75 ,Group Status Bit 75" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB74 ,Group Status Bit 74" "Group 0,Group 1" bitfld.long 0x00 9. " GSB73 ,Group Status Bit 73" "Group 0,Group 1" bitfld.long 0x00 8. " GSB72 ,Group Status Bit 72" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB71 ,Group Status Bit 71" "Group 0,Group 1" bitfld.long 0x00 6. " GSB70 ,Group Status Bit 70" "Group 0,Group 1" bitfld.long 0x00 5. " GSB69 ,Group Status Bit 69" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB68 ,Group Status Bit 68" "Group 0,Group 1" bitfld.long 0x00 3. " GSB67 ,Group Status Bit 67" "Group 0,Group 1" bitfld.long 0x00 2. " GSB66 ,Group Status Bit 66" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB65 ,Group Status Bit 65" "Group 0,Group 1" bitfld.long 0x00 0. " GSB64 ,Group Status Bit 64" "Group 0,Group 1" else rgroup.long 0x0088++0x03 line.long 0x0 "GICD_IGROUPR2,Interrupt Group Register 2" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x03)&&(PER.ADDRESS.isSECUREEX(ad:0xA0021000+0x008C)) group.long 0x008C++0x03 line.long 0x0 "GICD_IGROUPR3,Interrupt Group Register 3 (Secure access)" bitfld.long 0x00 31. " GSB127 ,Group Status Bit 127" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 30. " GSB126 ,Group Status Bit 126" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 29. " GSB125 ,Group Status Bit 125" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 28. " GSB124 ,Group Status Bit 124" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 27. " GSB123 ,Group Status Bit 123" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 26. " GSB122 ,Group Status Bit 122" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 25. " GSB121 ,Group Status Bit 121" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 24. " GSB120 ,Group Status Bit 120" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 23. " GSB119 ,Group Status Bit 119" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 22. " GSB118 ,Group Status Bit 118" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 21. " GSB117 ,Group Status Bit 117" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 20. " GSB116 ,Group Status Bit 116" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 19. " GSB115 ,Group Status Bit 115" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 18. " GSB114 ,Group Status Bit 114" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 17. " GSB113 ,Group Status Bit 113" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 16. " GSB112 ,Group Status Bit 112" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 15. " GSB111 ,Group Status Bit 111" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 14. " GSB110 ,Group Status Bit 110" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 13. " GSB109 ,Group Status Bit 109" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 12. " GSB108 ,Group Status Bit 108" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 11. " GSB107 ,Group Status Bit 107" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 10. " GSB106 ,Group Status Bit 106" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 9. " GSB105 ,Group Status Bit 105" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 8. " GSB104 ,Group Status Bit 104" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 7. " GSB103 ,Group Status Bit 103" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 6. " GSB102 ,Group Status Bit 102" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 5. " GSB101 ,Group Status Bit 101" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 4. " GSB100 ,Group Status Bit 100" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 3. " GSB99 ,Group Status Bit 99" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 2. " GSB98 ,Group Status Bit 98" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 1. " GSB97 ,Group Status Bit 97" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 0. " GSB96 ,Group Status Bit 96" "Group 0 (Secure),Group 1 (Non-secure)" elif (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x03) group.long 0x008C++0x03 line.long 0x0 "GICD_IGROUPR3,Interrupt Group Register 3 (Non-secure access)" bitfld.long 0x00 31. " GSB127 ,Group Status Bit 127" "Group 0,Group 1" bitfld.long 0x00 30. " GSB126 ,Group Status Bit 126" "Group 0,Group 1" bitfld.long 0x00 29. " GSB125 ,Group Status Bit 125" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB124 ,Group Status Bit 124" "Group 0,Group 1" bitfld.long 0x00 27. " GSB123 ,Group Status Bit 123" "Group 0,Group 1" bitfld.long 0x00 26. " GSB122 ,Group Status Bit 122" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB121 ,Group Status Bit 121" "Group 0,Group 1" bitfld.long 0x00 24. " GSB120 ,Group Status Bit 120" "Group 0,Group 1" bitfld.long 0x00 23. " GSB119 ,Group Status Bit 119" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB118 ,Group Status Bit 118" "Group 0,Group 1" bitfld.long 0x00 21. " GSB117 ,Group Status Bit 117" "Group 0,Group 1" bitfld.long 0x00 20. " GSB116 ,Group Status Bit 116" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB115 ,Group Status Bit 115" "Group 0,Group 1" bitfld.long 0x00 18. " GSB114 ,Group Status Bit 114" "Group 0,Group 1" bitfld.long 0x00 17. " GSB113 ,Group Status Bit 113" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB112 ,Group Status Bit 112" "Group 0,Group 1" bitfld.long 0x00 15. " GSB111 ,Group Status Bit 111" "Group 0,Group 1" bitfld.long 0x00 14. " GSB110 ,Group Status Bit 110" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB109 ,Group Status Bit 109" "Group 0,Group 1" bitfld.long 0x00 12. " GSB108 ,Group Status Bit 108" "Group 0,Group 1" bitfld.long 0x00 11. " GSB107 ,Group Status Bit 107" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB106 ,Group Status Bit 106" "Group 0,Group 1" bitfld.long 0x00 9. " GSB105 ,Group Status Bit 105" "Group 0,Group 1" bitfld.long 0x00 8. " GSB104 ,Group Status Bit 104" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB103 ,Group Status Bit 103" "Group 0,Group 1" bitfld.long 0x00 6. " GSB102 ,Group Status Bit 102" "Group 0,Group 1" bitfld.long 0x00 5. " GSB101 ,Group Status Bit 101" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB100 ,Group Status Bit 100" "Group 0,Group 1" bitfld.long 0x00 3. " GSB99 ,Group Status Bit 99" "Group 0,Group 1" bitfld.long 0x00 2. " GSB98 ,Group Status Bit 98" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB97 ,Group Status Bit 97" "Group 0,Group 1" bitfld.long 0x00 0. " GSB96 ,Group Status Bit 96" "Group 0,Group 1" else rgroup.long 0x008C++0x03 line.long 0x0 "GICD_IGROUPR3,Interrupt Group Register 3" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x04)&&(PER.ADDRESS.isSECUREEX(ad:0xA0021000+0x0090)) group.long 0x0090++0x03 line.long 0x0 "GICD_IGROUPR4,Interrupt Group Register 4 (Secure access)" bitfld.long 0x00 31. " GSB159 ,Group Status Bit 159" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 30. " GSB158 ,Group Status Bit 158" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 29. " GSB157 ,Group Status Bit 157" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 28. " GSB156 ,Group Status Bit 156" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 27. " GSB155 ,Group Status Bit 155" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 26. " GSB154 ,Group Status Bit 154" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 25. " GSB153 ,Group Status Bit 153" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 24. " GSB152 ,Group Status Bit 152" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 23. " GSB151 ,Group Status Bit 151" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 22. " GSB150 ,Group Status Bit 150" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 21. " GSB149 ,Group Status Bit 149" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 20. " GSB148 ,Group Status Bit 148" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 19. " GSB147 ,Group Status Bit 147" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 18. " GSB146 ,Group Status Bit 146" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 17. " GSB145 ,Group Status Bit 145" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 16. " GSB144 ,Group Status Bit 144" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 15. " GSB143 ,Group Status Bit 143" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 14. " GSB142 ,Group Status Bit 142" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 13. " GSB141 ,Group Status Bit 141" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 12. " GSB140 ,Group Status Bit 140" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 11. " GSB139 ,Group Status Bit 139" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 10. " GSB138 ,Group Status Bit 138" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 9. " GSB137 ,Group Status Bit 137" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 8. " GSB136 ,Group Status Bit 136" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 7. " GSB135 ,Group Status Bit 135" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 6. " GSB134 ,Group Status Bit 134" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 5. " GSB133 ,Group Status Bit 133" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 4. " GSB132 ,Group Status Bit 132" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 3. " GSB131 ,Group Status Bit 131" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 2. " GSB130 ,Group Status Bit 130" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 1. " GSB129 ,Group Status Bit 129" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 0. " GSB128 ,Group Status Bit 128" "Group 0 (Secure),Group 1 (Non-secure)" elif (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x04) group.long 0x0090++0x03 line.long 0x0 "GICD_IGROUPR4,Interrupt Group Register 4 (Non-secure access)" bitfld.long 0x00 31. " GSB159 ,Group Status Bit 159" "Group 0,Group 1" bitfld.long 0x00 30. " GSB158 ,Group Status Bit 158" "Group 0,Group 1" bitfld.long 0x00 29. " GSB157 ,Group Status Bit 157" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB156 ,Group Status Bit 156" "Group 0,Group 1" bitfld.long 0x00 27. " GSB155 ,Group Status Bit 155" "Group 0,Group 1" bitfld.long 0x00 26. " GSB154 ,Group Status Bit 154" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB153 ,Group Status Bit 153" "Group 0,Group 1" bitfld.long 0x00 24. " GSB152 ,Group Status Bit 152" "Group 0,Group 1" bitfld.long 0x00 23. " GSB151 ,Group Status Bit 151" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB150 ,Group Status Bit 150" "Group 0,Group 1" bitfld.long 0x00 21. " GSB149 ,Group Status Bit 149" "Group 0,Group 1" bitfld.long 0x00 20. " GSB148 ,Group Status Bit 148" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB147 ,Group Status Bit 147" "Group 0,Group 1" bitfld.long 0x00 18. " GSB146 ,Group Status Bit 146" "Group 0,Group 1" bitfld.long 0x00 17. " GSB145 ,Group Status Bit 145" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB144 ,Group Status Bit 144" "Group 0,Group 1" bitfld.long 0x00 15. " GSB143 ,Group Status Bit 143" "Group 0,Group 1" bitfld.long 0x00 14. " GSB142 ,Group Status Bit 142" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB141 ,Group Status Bit 141" "Group 0,Group 1" bitfld.long 0x00 12. " GSB140 ,Group Status Bit 140" "Group 0,Group 1" bitfld.long 0x00 11. " GSB139 ,Group Status Bit 139" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB138 ,Group Status Bit 138" "Group 0,Group 1" bitfld.long 0x00 9. " GSB137 ,Group Status Bit 137" "Group 0,Group 1" bitfld.long 0x00 8. " GSB136 ,Group Status Bit 136" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB135 ,Group Status Bit 135" "Group 0,Group 1" bitfld.long 0x00 6. " GSB134 ,Group Status Bit 134" "Group 0,Group 1" bitfld.long 0x00 5. " GSB133 ,Group Status Bit 133" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB132 ,Group Status Bit 132" "Group 0,Group 1" bitfld.long 0x00 3. " GSB131 ,Group Status Bit 131" "Group 0,Group 1" bitfld.long 0x00 2. " GSB130 ,Group Status Bit 130" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB129 ,Group Status Bit 129" "Group 0,Group 1" bitfld.long 0x00 0. " GSB128 ,Group Status Bit 128" "Group 0,Group 1" else rgroup.long 0x0090++0x03 line.long 0x0 "GICD_IGROUPR4,Interrupt Group Register 4" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x05)&&(PER.ADDRESS.isSECUREEX(ad:0xA0021000+0x0094)) group.long 0x0094++0x03 line.long 0x0 "GICD_IGROUPR5,Interrupt Group Register 5 (Secure access)" bitfld.long 0x00 31. " GSB191 ,Group Status Bit 191" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 30. " GSB190 ,Group Status Bit 190" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 29. " GSB189 ,Group Status Bit 189" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 28. " GSB188 ,Group Status Bit 188" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 27. " GSB187 ,Group Status Bit 187" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 26. " GSB186 ,Group Status Bit 186" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 25. " GSB185 ,Group Status Bit 185" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 24. " GSB184 ,Group Status Bit 184" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 23. " GSB183 ,Group Status Bit 183" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 22. " GSB182 ,Group Status Bit 182" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 21. " GSB181 ,Group Status Bit 181" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 20. " GSB180 ,Group Status Bit 180" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 19. " GSB179 ,Group Status Bit 179" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 18. " GSB178 ,Group Status Bit 178" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 17. " GSB177 ,Group Status Bit 177" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 16. " GSB176 ,Group Status Bit 176" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 15. " GSB175 ,Group Status Bit 175" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 14. " GSB174 ,Group Status Bit 174" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 13. " GSB173 ,Group Status Bit 173" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 12. " GSB172 ,Group Status Bit 172" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 11. " GSB171 ,Group Status Bit 171" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 10. " GSB170 ,Group Status Bit 170" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 9. " GSB169 ,Group Status Bit 169" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 8. " GSB168 ,Group Status Bit 168" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 7. " GSB167 ,Group Status Bit 167" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 6. " GSB166 ,Group Status Bit 166" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 5. " GSB165 ,Group Status Bit 165" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 4. " GSB164 ,Group Status Bit 164" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 3. " GSB163 ,Group Status Bit 163" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 2. " GSB162 ,Group Status Bit 162" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 1. " GSB161 ,Group Status Bit 161" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 0. " GSB160 ,Group Status Bit 160" "Group 0 (Secure),Group 1 (Non-secure)" elif (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x05) group.long 0x0094++0x03 line.long 0x0 "GICD_IGROUPR5,Interrupt Group Register 5 (Non-secure access)" bitfld.long 0x00 31. " GSB191 ,Group Status Bit 191" "Group 0,Group 1" bitfld.long 0x00 30. " GSB190 ,Group Status Bit 190" "Group 0,Group 1" bitfld.long 0x00 29. " GSB189 ,Group Status Bit 189" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB188 ,Group Status Bit 188" "Group 0,Group 1" bitfld.long 0x00 27. " GSB187 ,Group Status Bit 187" "Group 0,Group 1" bitfld.long 0x00 26. " GSB186 ,Group Status Bit 186" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB185 ,Group Status Bit 185" "Group 0,Group 1" bitfld.long 0x00 24. " GSB184 ,Group Status Bit 184" "Group 0,Group 1" bitfld.long 0x00 23. " GSB183 ,Group Status Bit 183" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB182 ,Group Status Bit 182" "Group 0,Group 1" bitfld.long 0x00 21. " GSB181 ,Group Status Bit 181" "Group 0,Group 1" bitfld.long 0x00 20. " GSB180 ,Group Status Bit 180" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB179 ,Group Status Bit 179" "Group 0,Group 1" bitfld.long 0x00 18. " GSB178 ,Group Status Bit 178" "Group 0,Group 1" bitfld.long 0x00 17. " GSB177 ,Group Status Bit 177" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB176 ,Group Status Bit 176" "Group 0,Group 1" bitfld.long 0x00 15. " GSB175 ,Group Status Bit 175" "Group 0,Group 1" bitfld.long 0x00 14. " GSB174 ,Group Status Bit 174" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB173 ,Group Status Bit 173" "Group 0,Group 1" bitfld.long 0x00 12. " GSB172 ,Group Status Bit 172" "Group 0,Group 1" bitfld.long 0x00 11. " GSB171 ,Group Status Bit 171" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB170 ,Group Status Bit 170" "Group 0,Group 1" bitfld.long 0x00 9. " GSB169 ,Group Status Bit 169" "Group 0,Group 1" bitfld.long 0x00 8. " GSB168 ,Group Status Bit 168" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB167 ,Group Status Bit 167" "Group 0,Group 1" bitfld.long 0x00 6. " GSB166 ,Group Status Bit 166" "Group 0,Group 1" bitfld.long 0x00 5. " GSB165 ,Group Status Bit 165" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB164 ,Group Status Bit 164" "Group 0,Group 1" bitfld.long 0x00 3. " GSB163 ,Group Status Bit 163" "Group 0,Group 1" bitfld.long 0x00 2. " GSB162 ,Group Status Bit 162" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB161 ,Group Status Bit 161" "Group 0,Group 1" bitfld.long 0x00 0. " GSB160 ,Group Status Bit 160" "Group 0,Group 1" else rgroup.long 0x0094++0x03 line.long 0x0 "GICD_IGROUPR5,Interrupt Group Register 5" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x06)&&(PER.ADDRESS.isSECUREEX(ad:0xA0021000+0x0098)) group.long 0x0098++0x03 line.long 0x0 "GICD_IGROUPR6,Interrupt Group Register 6 (Secure access)" bitfld.long 0x00 31. " GSB223 ,Group Status Bit 223" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 30. " GSB222 ,Group Status Bit 222" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 29. " GSB221 ,Group Status Bit 221" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 28. " GSB220 ,Group Status Bit 220" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 27. " GSB219 ,Group Status Bit 219" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 26. " GSB218 ,Group Status Bit 218" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 25. " GSB217 ,Group Status Bit 217" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 24. " GSB216 ,Group Status Bit 216" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 23. " GSB215 ,Group Status Bit 215" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 22. " GSB214 ,Group Status Bit 214" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 21. " GSB213 ,Group Status Bit 213" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 20. " GSB212 ,Group Status Bit 212" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 19. " GSB211 ,Group Status Bit 211" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 18. " GSB210 ,Group Status Bit 210" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 17. " GSB209 ,Group Status Bit 209" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 16. " GSB208 ,Group Status Bit 208" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 15. " GSB207 ,Group Status Bit 207" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 14. " GSB206 ,Group Status Bit 206" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 13. " GSB205 ,Group Status Bit 205" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 12. " GSB204 ,Group Status Bit 204" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 11. " GSB203 ,Group Status Bit 203" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 10. " GSB202 ,Group Status Bit 202" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 9. " GSB201 ,Group Status Bit 201" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 8. " GSB200 ,Group Status Bit 200" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 7. " GSB199 ,Group Status Bit 199" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 6. " GSB198 ,Group Status Bit 198" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 5. " GSB197 ,Group Status Bit 197" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 4. " GSB196 ,Group Status Bit 196" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 3. " GSB195 ,Group Status Bit 195" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 2. " GSB194 ,Group Status Bit 194" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 1. " GSB193 ,Group Status Bit 193" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 0. " GSB192 ,Group Status Bit 192" "Group 0 (Secure),Group 1 (Non-secure)" elif (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x06) group.long 0x0098++0x03 line.long 0x0 "GICD_IGROUPR6,Interrupt Group Register 6 (Non-secure access)" bitfld.long 0x00 31. " GSB223 ,Group Status Bit 223" "Group 0,Group 1" bitfld.long 0x00 30. " GSB222 ,Group Status Bit 222" "Group 0,Group 1" bitfld.long 0x00 29. " GSB221 ,Group Status Bit 221" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB220 ,Group Status Bit 220" "Group 0,Group 1" bitfld.long 0x00 27. " GSB219 ,Group Status Bit 219" "Group 0,Group 1" bitfld.long 0x00 26. " GSB218 ,Group Status Bit 218" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB217 ,Group Status Bit 217" "Group 0,Group 1" bitfld.long 0x00 24. " GSB216 ,Group Status Bit 216" "Group 0,Group 1" bitfld.long 0x00 23. " GSB215 ,Group Status Bit 215" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB214 ,Group Status Bit 214" "Group 0,Group 1" bitfld.long 0x00 21. " GSB213 ,Group Status Bit 213" "Group 0,Group 1" bitfld.long 0x00 20. " GSB212 ,Group Status Bit 212" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB211 ,Group Status Bit 211" "Group 0,Group 1" bitfld.long 0x00 18. " GSB210 ,Group Status Bit 210" "Group 0,Group 1" bitfld.long 0x00 17. " GSB209 ,Group Status Bit 209" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB208 ,Group Status Bit 208" "Group 0,Group 1" bitfld.long 0x00 15. " GSB207 ,Group Status Bit 207" "Group 0,Group 1" bitfld.long 0x00 14. " GSB206 ,Group Status Bit 206" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB205 ,Group Status Bit 205" "Group 0,Group 1" bitfld.long 0x00 12. " GSB204 ,Group Status Bit 204" "Group 0,Group 1" bitfld.long 0x00 11. " GSB203 ,Group Status Bit 203" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB202 ,Group Status Bit 202" "Group 0,Group 1" bitfld.long 0x00 9. " GSB201 ,Group Status Bit 201" "Group 0,Group 1" bitfld.long 0x00 8. " GSB200 ,Group Status Bit 200" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB199 ,Group Status Bit 199" "Group 0,Group 1" bitfld.long 0x00 6. " GSB198 ,Group Status Bit 198" "Group 0,Group 1" bitfld.long 0x00 5. " GSB197 ,Group Status Bit 197" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB196 ,Group Status Bit 196" "Group 0,Group 1" bitfld.long 0x00 3. " GSB195 ,Group Status Bit 195" "Group 0,Group 1" bitfld.long 0x00 2. " GSB194 ,Group Status Bit 194" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB193 ,Group Status Bit 193" "Group 0,Group 1" bitfld.long 0x00 0. " GSB192 ,Group Status Bit 192" "Group 0,Group 1" else rgroup.long 0x0098++0x03 line.long 0x0 "GICD_IGROUPR6,Interrupt Group Register 6" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x07)&&(PER.ADDRESS.isSECUREEX(ad:0xA0021000+0x009C)) group.long 0x009C++0x03 line.long 0x0 "GICD_IGROUPR7,Interrupt Group Register 7 (Secure access)" bitfld.long 0x00 31. " GSB255 ,Group Status Bit 255" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 30. " GSB254 ,Group Status Bit 254" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 29. " GSB253 ,Group Status Bit 253" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 28. " GSB252 ,Group Status Bit 252" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 27. " GSB251 ,Group Status Bit 251" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 26. " GSB250 ,Group Status Bit 250" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 25. " GSB249 ,Group Status Bit 249" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 24. " GSB248 ,Group Status Bit 248" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 23. " GSB247 ,Group Status Bit 247" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 22. " GSB246 ,Group Status Bit 246" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 21. " GSB245 ,Group Status Bit 245" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 20. " GSB244 ,Group Status Bit 244" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 19. " GSB243 ,Group Status Bit 243" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 18. " GSB242 ,Group Status Bit 242" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 17. " GSB241 ,Group Status Bit 241" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 16. " GSB240 ,Group Status Bit 240" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 15. " GSB239 ,Group Status Bit 239" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 14. " GSB238 ,Group Status Bit 238" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 13. " GSB237 ,Group Status Bit 237" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 12. " GSB236 ,Group Status Bit 236" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 11. " GSB235 ,Group Status Bit 235" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 10. " GSB234 ,Group Status Bit 234" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 9. " GSB233 ,Group Status Bit 233" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 8. " GSB232 ,Group Status Bit 232" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 7. " GSB231 ,Group Status Bit 231" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 6. " GSB230 ,Group Status Bit 230" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 5. " GSB229 ,Group Status Bit 229" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 4. " GSB228 ,Group Status Bit 228" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 3. " GSB227 ,Group Status Bit 227" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 2. " GSB226 ,Group Status Bit 226" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 1. " GSB225 ,Group Status Bit 225" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 0. " GSB224 ,Group Status Bit 224" "Group 0 (Secure),Group 1 (Non-secure)" elif (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x07) group.long 0x009C++0x03 line.long 0x0 "GICD_IGROUPR7,Interrupt Group Register 7 (Non-secure access)" bitfld.long 0x00 31. " GSB255 ,Group Status Bit 255" "Group 0,Group 1" bitfld.long 0x00 30. " GSB254 ,Group Status Bit 254" "Group 0,Group 1" bitfld.long 0x00 29. " GSB253 ,Group Status Bit 253" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB252 ,Group Status Bit 252" "Group 0,Group 1" bitfld.long 0x00 27. " GSB251 ,Group Status Bit 251" "Group 0,Group 1" bitfld.long 0x00 26. " GSB250 ,Group Status Bit 250" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB249 ,Group Status Bit 249" "Group 0,Group 1" bitfld.long 0x00 24. " GSB248 ,Group Status Bit 248" "Group 0,Group 1" bitfld.long 0x00 23. " GSB247 ,Group Status Bit 247" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB246 ,Group Status Bit 246" "Group 0,Group 1" bitfld.long 0x00 21. " GSB245 ,Group Status Bit 245" "Group 0,Group 1" bitfld.long 0x00 20. " GSB244 ,Group Status Bit 244" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB243 ,Group Status Bit 243" "Group 0,Group 1" bitfld.long 0x00 18. " GSB242 ,Group Status Bit 242" "Group 0,Group 1" bitfld.long 0x00 17. " GSB241 ,Group Status Bit 241" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB240 ,Group Status Bit 240" "Group 0,Group 1" bitfld.long 0x00 15. " GSB239 ,Group Status Bit 239" "Group 0,Group 1" bitfld.long 0x00 14. " GSB238 ,Group Status Bit 238" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB237 ,Group Status Bit 237" "Group 0,Group 1" bitfld.long 0x00 12. " GSB236 ,Group Status Bit 236" "Group 0,Group 1" bitfld.long 0x00 11. " GSB235 ,Group Status Bit 235" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB234 ,Group Status Bit 234" "Group 0,Group 1" bitfld.long 0x00 9. " GSB233 ,Group Status Bit 233" "Group 0,Group 1" bitfld.long 0x00 8. " GSB232 ,Group Status Bit 232" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB231 ,Group Status Bit 231" "Group 0,Group 1" bitfld.long 0x00 6. " GSB230 ,Group Status Bit 230" "Group 0,Group 1" bitfld.long 0x00 5. " GSB229 ,Group Status Bit 229" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB228 ,Group Status Bit 228" "Group 0,Group 1" bitfld.long 0x00 3. " GSB227 ,Group Status Bit 227" "Group 0,Group 1" bitfld.long 0x00 2. " GSB226 ,Group Status Bit 226" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB225 ,Group Status Bit 225" "Group 0,Group 1" bitfld.long 0x00 0. " GSB224 ,Group Status Bit 224" "Group 0,Group 1" else rgroup.long 0x009C++0x03 line.long 0x0 "GICD_IGROUPR7,Interrupt Group Register 7" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x08)&&(PER.ADDRESS.isSECUREEX(ad:0xA0021000+0x00A0)) group.long 0x00A0++0x03 line.long 0x0 "GICD_IGROUPR8,Interrupt Group Register 8 (Secure access)" bitfld.long 0x00 31. " GSB287 ,Group Status Bit 287" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 30. " GSB286 ,Group Status Bit 286" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 29. " GSB285 ,Group Status Bit 285" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 28. " GSB284 ,Group Status Bit 284" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 27. " GSB283 ,Group Status Bit 283" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 26. " GSB282 ,Group Status Bit 282" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 25. " GSB281 ,Group Status Bit 281" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 24. " GSB280 ,Group Status Bit 280" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 23. " GSB279 ,Group Status Bit 279" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 22. " GSB278 ,Group Status Bit 278" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 21. " GSB277 ,Group Status Bit 277" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 20. " GSB276 ,Group Status Bit 276" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 19. " GSB275 ,Group Status Bit 275" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 18. " GSB274 ,Group Status Bit 274" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 17. " GSB273 ,Group Status Bit 273" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 16. " GSB272 ,Group Status Bit 272" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 15. " GSB271 ,Group Status Bit 271" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 14. " GSB270 ,Group Status Bit 270" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 13. " GSB269 ,Group Status Bit 269" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 12. " GSB268 ,Group Status Bit 268" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 11. " GSB267 ,Group Status Bit 267" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 10. " GSB266 ,Group Status Bit 266" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 9. " GSB265 ,Group Status Bit 265" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 8. " GSB264 ,Group Status Bit 264" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 7. " GSB263 ,Group Status Bit 263" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 6. " GSB262 ,Group Status Bit 262" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 5. " GSB261 ,Group Status Bit 261" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 4. " GSB260 ,Group Status Bit 260" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 3. " GSB259 ,Group Status Bit 259" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 2. " GSB258 ,Group Status Bit 258" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 1. " GSB257 ,Group Status Bit 257" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 0. " GSB256 ,Group Status Bit 256" "Group 0 (Secure),Group 1 (Non-secure)" elif (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x08) group.long 0x00A0++0x03 line.long 0x0 "GICD_IGROUPR8,Interrupt Group Register 8 (Non-secure access)" bitfld.long 0x00 31. " GSB287 ,Group Status Bit 287" "Group 0,Group 1" bitfld.long 0x00 30. " GSB286 ,Group Status Bit 286" "Group 0,Group 1" bitfld.long 0x00 29. " GSB285 ,Group Status Bit 285" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB284 ,Group Status Bit 284" "Group 0,Group 1" bitfld.long 0x00 27. " GSB283 ,Group Status Bit 283" "Group 0,Group 1" bitfld.long 0x00 26. " GSB282 ,Group Status Bit 282" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB281 ,Group Status Bit 281" "Group 0,Group 1" bitfld.long 0x00 24. " GSB280 ,Group Status Bit 280" "Group 0,Group 1" bitfld.long 0x00 23. " GSB279 ,Group Status Bit 279" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB278 ,Group Status Bit 278" "Group 0,Group 1" bitfld.long 0x00 21. " GSB277 ,Group Status Bit 277" "Group 0,Group 1" bitfld.long 0x00 20. " GSB276 ,Group Status Bit 276" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB275 ,Group Status Bit 275" "Group 0,Group 1" bitfld.long 0x00 18. " GSB274 ,Group Status Bit 274" "Group 0,Group 1" bitfld.long 0x00 17. " GSB273 ,Group Status Bit 273" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB272 ,Group Status Bit 272" "Group 0,Group 1" bitfld.long 0x00 15. " GSB271 ,Group Status Bit 271" "Group 0,Group 1" bitfld.long 0x00 14. " GSB270 ,Group Status Bit 270" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB269 ,Group Status Bit 269" "Group 0,Group 1" bitfld.long 0x00 12. " GSB268 ,Group Status Bit 268" "Group 0,Group 1" bitfld.long 0x00 11. " GSB267 ,Group Status Bit 267" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB266 ,Group Status Bit 266" "Group 0,Group 1" bitfld.long 0x00 9. " GSB265 ,Group Status Bit 265" "Group 0,Group 1" bitfld.long 0x00 8. " GSB264 ,Group Status Bit 264" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB263 ,Group Status Bit 263" "Group 0,Group 1" bitfld.long 0x00 6. " GSB262 ,Group Status Bit 262" "Group 0,Group 1" bitfld.long 0x00 5. " GSB261 ,Group Status Bit 261" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB260 ,Group Status Bit 260" "Group 0,Group 1" bitfld.long 0x00 3. " GSB259 ,Group Status Bit 259" "Group 0,Group 1" bitfld.long 0x00 2. " GSB258 ,Group Status Bit 258" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB257 ,Group Status Bit 257" "Group 0,Group 1" bitfld.long 0x00 0. " GSB256 ,Group Status Bit 256" "Group 0,Group 1" else rgroup.long 0x00A0++0x03 line.long 0x0 "GICD_IGROUPR8,Interrupt Group Register 8" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x09)&&(PER.ADDRESS.isSECUREEX(ad:0xA0021000+0x00A4)) group.long 0x00A4++0x03 line.long 0x0 "GICD_IGROUPR9,Interrupt Group Register 9 (Secure access)" bitfld.long 0x00 31. " GSB319 ,Group Status Bit 319" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 30. " GSB318 ,Group Status Bit 318" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 29. " GSB317 ,Group Status Bit 317" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 28. " GSB316 ,Group Status Bit 316" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 27. " GSB315 ,Group Status Bit 315" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 26. " GSB314 ,Group Status Bit 314" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 25. " GSB313 ,Group Status Bit 313" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 24. " GSB312 ,Group Status Bit 312" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 23. " GSB311 ,Group Status Bit 311" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 22. " GSB310 ,Group Status Bit 310" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 21. " GSB309 ,Group Status Bit 309" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 20. " GSB308 ,Group Status Bit 308" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 19. " GSB307 ,Group Status Bit 307" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 18. " GSB306 ,Group Status Bit 306" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 17. " GSB305 ,Group Status Bit 305" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 16. " GSB304 ,Group Status Bit 304" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 15. " GSB303 ,Group Status Bit 303" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 14. " GSB302 ,Group Status Bit 302" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 13. " GSB301 ,Group Status Bit 301" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 12. " GSB300 ,Group Status Bit 300" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 11. " GSB299 ,Group Status Bit 299" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 10. " GSB298 ,Group Status Bit 298" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 9. " GSB297 ,Group Status Bit 297" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 8. " GSB296 ,Group Status Bit 296" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 7. " GSB295 ,Group Status Bit 295" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 6. " GSB294 ,Group Status Bit 294" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 5. " GSB293 ,Group Status Bit 293" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 4. " GSB292 ,Group Status Bit 292" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 3. " GSB291 ,Group Status Bit 291" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 2. " GSB290 ,Group Status Bit 290" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 1. " GSB289 ,Group Status Bit 289" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 0. " GSB288 ,Group Status Bit 288" "Group 0 (Secure),Group 1 (Non-secure)" elif (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x09) group.long 0x00A4++0x03 line.long 0x0 "GICD_IGROUPR9,Interrupt Group Register 9 (Non-secure access)" bitfld.long 0x00 31. " GSB319 ,Group Status Bit 319" "Group 0,Group 1" bitfld.long 0x00 30. " GSB318 ,Group Status Bit 318" "Group 0,Group 1" bitfld.long 0x00 29. " GSB317 ,Group Status Bit 317" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB316 ,Group Status Bit 316" "Group 0,Group 1" bitfld.long 0x00 27. " GSB315 ,Group Status Bit 315" "Group 0,Group 1" bitfld.long 0x00 26. " GSB314 ,Group Status Bit 314" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB313 ,Group Status Bit 313" "Group 0,Group 1" bitfld.long 0x00 24. " GSB312 ,Group Status Bit 312" "Group 0,Group 1" bitfld.long 0x00 23. " GSB311 ,Group Status Bit 311" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB310 ,Group Status Bit 310" "Group 0,Group 1" bitfld.long 0x00 21. " GSB309 ,Group Status Bit 309" "Group 0,Group 1" bitfld.long 0x00 20. " GSB308 ,Group Status Bit 308" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB307 ,Group Status Bit 307" "Group 0,Group 1" bitfld.long 0x00 18. " GSB306 ,Group Status Bit 306" "Group 0,Group 1" bitfld.long 0x00 17. " GSB305 ,Group Status Bit 305" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB304 ,Group Status Bit 304" "Group 0,Group 1" bitfld.long 0x00 15. " GSB303 ,Group Status Bit 303" "Group 0,Group 1" bitfld.long 0x00 14. " GSB302 ,Group Status Bit 302" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB301 ,Group Status Bit 301" "Group 0,Group 1" bitfld.long 0x00 12. " GSB300 ,Group Status Bit 300" "Group 0,Group 1" bitfld.long 0x00 11. " GSB299 ,Group Status Bit 299" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB298 ,Group Status Bit 298" "Group 0,Group 1" bitfld.long 0x00 9. " GSB297 ,Group Status Bit 297" "Group 0,Group 1" bitfld.long 0x00 8. " GSB296 ,Group Status Bit 296" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB295 ,Group Status Bit 295" "Group 0,Group 1" bitfld.long 0x00 6. " GSB294 ,Group Status Bit 294" "Group 0,Group 1" bitfld.long 0x00 5. " GSB293 ,Group Status Bit 293" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB292 ,Group Status Bit 292" "Group 0,Group 1" bitfld.long 0x00 3. " GSB291 ,Group Status Bit 291" "Group 0,Group 1" bitfld.long 0x00 2. " GSB290 ,Group Status Bit 290" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB289 ,Group Status Bit 289" "Group 0,Group 1" bitfld.long 0x00 0. " GSB288 ,Group Status Bit 288" "Group 0,Group 1" else rgroup.long 0x00A4++0x03 line.long 0x0 "GICD_IGROUPR9,Interrupt Group Register 9" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x0A)&&(PER.ADDRESS.isSECUREEX(ad:0xA0021000+0x00A8)) group.long 0x00A8++0x03 line.long 0x0 "GICD_IGROUPR10,Interrupt Group Register 10 (Secure access)" bitfld.long 0x00 31. " GSB351 ,Group Status Bit 351" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 30. " GSB350 ,Group Status Bit 350" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 29. " GSB349 ,Group Status Bit 349" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 28. " GSB348 ,Group Status Bit 348" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 27. " GSB347 ,Group Status Bit 347" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 26. " GSB346 ,Group Status Bit 346" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 25. " GSB345 ,Group Status Bit 345" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 24. " GSB344 ,Group Status Bit 344" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 23. " GSB343 ,Group Status Bit 343" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 22. " GSB342 ,Group Status Bit 342" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 21. " GSB341 ,Group Status Bit 341" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 20. " GSB340 ,Group Status Bit 340" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 19. " GSB339 ,Group Status Bit 339" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 18. " GSB338 ,Group Status Bit 338" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 17. " GSB337 ,Group Status Bit 337" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 16. " GSB336 ,Group Status Bit 336" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 15. " GSB335 ,Group Status Bit 335" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 14. " GSB334 ,Group Status Bit 334" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 13. " GSB333 ,Group Status Bit 333" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 12. " GSB332 ,Group Status Bit 332" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 11. " GSB331 ,Group Status Bit 331" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 10. " GSB330 ,Group Status Bit 330" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 9. " GSB329 ,Group Status Bit 329" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 8. " GSB328 ,Group Status Bit 328" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 7. " GSB327 ,Group Status Bit 327" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 6. " GSB326 ,Group Status Bit 326" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 5. " GSB325 ,Group Status Bit 325" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 4. " GSB324 ,Group Status Bit 324" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 3. " GSB323 ,Group Status Bit 323" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 2. " GSB322 ,Group Status Bit 322" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 1. " GSB321 ,Group Status Bit 321" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 0. " GSB320 ,Group Status Bit 320" "Group 0 (Secure),Group 1 (Non-secure)" elif (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x0A) group.long 0x00A8++0x03 line.long 0x0 "GICD_IGROUPR10,Interrupt Group Register 10 (Non-secure access)" bitfld.long 0x00 31. " GSB351 ,Group Status Bit 351" "Group 0,Group 1" bitfld.long 0x00 30. " GSB350 ,Group Status Bit 350" "Group 0,Group 1" bitfld.long 0x00 29. " GSB349 ,Group Status Bit 349" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB348 ,Group Status Bit 348" "Group 0,Group 1" bitfld.long 0x00 27. " GSB347 ,Group Status Bit 347" "Group 0,Group 1" bitfld.long 0x00 26. " GSB346 ,Group Status Bit 346" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB345 ,Group Status Bit 345" "Group 0,Group 1" bitfld.long 0x00 24. " GSB344 ,Group Status Bit 344" "Group 0,Group 1" bitfld.long 0x00 23. " GSB343 ,Group Status Bit 343" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB342 ,Group Status Bit 342" "Group 0,Group 1" bitfld.long 0x00 21. " GSB341 ,Group Status Bit 341" "Group 0,Group 1" bitfld.long 0x00 20. " GSB340 ,Group Status Bit 340" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB339 ,Group Status Bit 339" "Group 0,Group 1" bitfld.long 0x00 18. " GSB338 ,Group Status Bit 338" "Group 0,Group 1" bitfld.long 0x00 17. " GSB337 ,Group Status Bit 337" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB336 ,Group Status Bit 336" "Group 0,Group 1" bitfld.long 0x00 15. " GSB335 ,Group Status Bit 335" "Group 0,Group 1" bitfld.long 0x00 14. " GSB334 ,Group Status Bit 334" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB333 ,Group Status Bit 333" "Group 0,Group 1" bitfld.long 0x00 12. " GSB332 ,Group Status Bit 332" "Group 0,Group 1" bitfld.long 0x00 11. " GSB331 ,Group Status Bit 331" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB330 ,Group Status Bit 330" "Group 0,Group 1" bitfld.long 0x00 9. " GSB329 ,Group Status Bit 329" "Group 0,Group 1" bitfld.long 0x00 8. " GSB328 ,Group Status Bit 328" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB327 ,Group Status Bit 327" "Group 0,Group 1" bitfld.long 0x00 6. " GSB326 ,Group Status Bit 326" "Group 0,Group 1" bitfld.long 0x00 5. " GSB325 ,Group Status Bit 325" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB324 ,Group Status Bit 324" "Group 0,Group 1" bitfld.long 0x00 3. " GSB323 ,Group Status Bit 323" "Group 0,Group 1" bitfld.long 0x00 2. " GSB322 ,Group Status Bit 322" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB321 ,Group Status Bit 321" "Group 0,Group 1" bitfld.long 0x00 0. " GSB320 ,Group Status Bit 320" "Group 0,Group 1" else rgroup.long 0x00A8++0x03 line.long 0x0 "GICD_IGROUPR10,Interrupt Group Register 10" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x0B)&&(PER.ADDRESS.isSECUREEX(ad:0xA0021000+0x00AC)) group.long 0x00AC++0x03 line.long 0x0 "GICD_IGROUPR11,Interrupt Group Register 11 (Secure access)" bitfld.long 0x00 31. " GSB383 ,Group Status Bit 383" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 30. " GSB382 ,Group Status Bit 382" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 29. " GSB381 ,Group Status Bit 381" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 28. " GSB380 ,Group Status Bit 380" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 27. " GSB379 ,Group Status Bit 379" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 26. " GSB378 ,Group Status Bit 378" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 25. " GSB377 ,Group Status Bit 377" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 24. " GSB376 ,Group Status Bit 376" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 23. " GSB375 ,Group Status Bit 375" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 22. " GSB374 ,Group Status Bit 374" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 21. " GSB373 ,Group Status Bit 373" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 20. " GSB372 ,Group Status Bit 372" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 19. " GSB371 ,Group Status Bit 371" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 18. " GSB370 ,Group Status Bit 370" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 17. " GSB369 ,Group Status Bit 369" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 16. " GSB368 ,Group Status Bit 368" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 15. " GSB367 ,Group Status Bit 367" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 14. " GSB366 ,Group Status Bit 366" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 13. " GSB365 ,Group Status Bit 365" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 12. " GSB364 ,Group Status Bit 364" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 11. " GSB363 ,Group Status Bit 363" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 10. " GSB362 ,Group Status Bit 362" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 9. " GSB361 ,Group Status Bit 361" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 8. " GSB360 ,Group Status Bit 360" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 7. " GSB359 ,Group Status Bit 359" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 6. " GSB358 ,Group Status Bit 358" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 5. " GSB357 ,Group Status Bit 357" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 4. " GSB356 ,Group Status Bit 356" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 3. " GSB355 ,Group Status Bit 355" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 2. " GSB354 ,Group Status Bit 354" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 1. " GSB353 ,Group Status Bit 353" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 0. " GSB352 ,Group Status Bit 352" "Group 0 (Secure),Group 1 (Non-secure)" elif (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x0B) group.long 0x00AC++0x03 line.long 0x0 "GICD_IGROUPR11,Interrupt Group Register 11 (Non-secure access)" bitfld.long 0x00 31. " GSB383 ,Group Status Bit 383" "Group 0,Group 1" bitfld.long 0x00 30. " GSB382 ,Group Status Bit 382" "Group 0,Group 1" bitfld.long 0x00 29. " GSB381 ,Group Status Bit 381" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB380 ,Group Status Bit 380" "Group 0,Group 1" bitfld.long 0x00 27. " GSB379 ,Group Status Bit 379" "Group 0,Group 1" bitfld.long 0x00 26. " GSB378 ,Group Status Bit 378" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB377 ,Group Status Bit 377" "Group 0,Group 1" bitfld.long 0x00 24. " GSB376 ,Group Status Bit 376" "Group 0,Group 1" bitfld.long 0x00 23. " GSB375 ,Group Status Bit 375" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB374 ,Group Status Bit 374" "Group 0,Group 1" bitfld.long 0x00 21. " GSB373 ,Group Status Bit 373" "Group 0,Group 1" bitfld.long 0x00 20. " GSB372 ,Group Status Bit 372" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB371 ,Group Status Bit 371" "Group 0,Group 1" bitfld.long 0x00 18. " GSB370 ,Group Status Bit 370" "Group 0,Group 1" bitfld.long 0x00 17. " GSB369 ,Group Status Bit 369" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB368 ,Group Status Bit 368" "Group 0,Group 1" bitfld.long 0x00 15. " GSB367 ,Group Status Bit 367" "Group 0,Group 1" bitfld.long 0x00 14. " GSB366 ,Group Status Bit 366" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB365 ,Group Status Bit 365" "Group 0,Group 1" bitfld.long 0x00 12. " GSB364 ,Group Status Bit 364" "Group 0,Group 1" bitfld.long 0x00 11. " GSB363 ,Group Status Bit 363" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB362 ,Group Status Bit 362" "Group 0,Group 1" bitfld.long 0x00 9. " GSB361 ,Group Status Bit 361" "Group 0,Group 1" bitfld.long 0x00 8. " GSB360 ,Group Status Bit 360" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB359 ,Group Status Bit 359" "Group 0,Group 1" bitfld.long 0x00 6. " GSB358 ,Group Status Bit 358" "Group 0,Group 1" bitfld.long 0x00 5. " GSB357 ,Group Status Bit 357" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB356 ,Group Status Bit 356" "Group 0,Group 1" bitfld.long 0x00 3. " GSB355 ,Group Status Bit 355" "Group 0,Group 1" bitfld.long 0x00 2. " GSB354 ,Group Status Bit 354" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB353 ,Group Status Bit 353" "Group 0,Group 1" bitfld.long 0x00 0. " GSB352 ,Group Status Bit 352" "Group 0,Group 1" else rgroup.long 0x00AC++0x03 line.long 0x0 "GICD_IGROUPR11,Interrupt Group Register 11" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x0C)&&(PER.ADDRESS.isSECUREEX(ad:0xA0021000+0x00B0)) group.long 0x00B0++0x03 line.long 0x0 "GICD_IGROUPR12,Interrupt Group Register 12 (Secure access)" bitfld.long 0x00 31. " GSB415 ,Group Status Bit 415" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 30. " GSB414 ,Group Status Bit 414" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 29. " GSB413 ,Group Status Bit 413" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 28. " GSB412 ,Group Status Bit 412" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 27. " GSB411 ,Group Status Bit 411" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 26. " GSB410 ,Group Status Bit 410" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 25. " GSB409 ,Group Status Bit 409" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 24. " GSB408 ,Group Status Bit 408" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 23. " GSB407 ,Group Status Bit 407" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 22. " GSB406 ,Group Status Bit 406" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 21. " GSB405 ,Group Status Bit 405" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 20. " GSB404 ,Group Status Bit 404" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 19. " GSB403 ,Group Status Bit 403" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 18. " GSB402 ,Group Status Bit 402" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 17. " GSB401 ,Group Status Bit 401" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 16. " GSB400 ,Group Status Bit 400" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 15. " GSB399 ,Group Status Bit 399" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 14. " GSB398 ,Group Status Bit 398" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 13. " GSB397 ,Group Status Bit 397" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 12. " GSB396 ,Group Status Bit 396" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 11. " GSB395 ,Group Status Bit 395" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 10. " GSB394 ,Group Status Bit 394" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 9. " GSB393 ,Group Status Bit 393" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 8. " GSB392 ,Group Status Bit 392" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 7. " GSB391 ,Group Status Bit 391" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 6. " GSB390 ,Group Status Bit 390" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 5. " GSB389 ,Group Status Bit 389" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 4. " GSB388 ,Group Status Bit 388" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 3. " GSB387 ,Group Status Bit 387" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 2. " GSB386 ,Group Status Bit 386" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 1. " GSB385 ,Group Status Bit 385" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 0. " GSB384 ,Group Status Bit 384" "Group 0 (Secure),Group 1 (Non-secure)" elif (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x0C) group.long 0x00B0++0x03 line.long 0x0 "GICD_IGROUPR12,Interrupt Group Register 12 (Non-secure access)" bitfld.long 0x00 31. " GSB415 ,Group Status Bit 415" "Group 0,Group 1" bitfld.long 0x00 30. " GSB414 ,Group Status Bit 414" "Group 0,Group 1" bitfld.long 0x00 29. " GSB413 ,Group Status Bit 413" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB412 ,Group Status Bit 412" "Group 0,Group 1" bitfld.long 0x00 27. " GSB411 ,Group Status Bit 411" "Group 0,Group 1" bitfld.long 0x00 26. " GSB410 ,Group Status Bit 410" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB409 ,Group Status Bit 409" "Group 0,Group 1" bitfld.long 0x00 24. " GSB408 ,Group Status Bit 408" "Group 0,Group 1" bitfld.long 0x00 23. " GSB407 ,Group Status Bit 407" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB406 ,Group Status Bit 406" "Group 0,Group 1" bitfld.long 0x00 21. " GSB405 ,Group Status Bit 405" "Group 0,Group 1" bitfld.long 0x00 20. " GSB404 ,Group Status Bit 404" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB403 ,Group Status Bit 403" "Group 0,Group 1" bitfld.long 0x00 18. " GSB402 ,Group Status Bit 402" "Group 0,Group 1" bitfld.long 0x00 17. " GSB401 ,Group Status Bit 401" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB400 ,Group Status Bit 400" "Group 0,Group 1" bitfld.long 0x00 15. " GSB399 ,Group Status Bit 399" "Group 0,Group 1" bitfld.long 0x00 14. " GSB398 ,Group Status Bit 398" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB397 ,Group Status Bit 397" "Group 0,Group 1" bitfld.long 0x00 12. " GSB396 ,Group Status Bit 396" "Group 0,Group 1" bitfld.long 0x00 11. " GSB395 ,Group Status Bit 395" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB394 ,Group Status Bit 394" "Group 0,Group 1" bitfld.long 0x00 9. " GSB393 ,Group Status Bit 393" "Group 0,Group 1" bitfld.long 0x00 8. " GSB392 ,Group Status Bit 392" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB391 ,Group Status Bit 391" "Group 0,Group 1" bitfld.long 0x00 6. " GSB390 ,Group Status Bit 390" "Group 0,Group 1" bitfld.long 0x00 5. " GSB389 ,Group Status Bit 389" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB388 ,Group Status Bit 388" "Group 0,Group 1" bitfld.long 0x00 3. " GSB387 ,Group Status Bit 387" "Group 0,Group 1" bitfld.long 0x00 2. " GSB386 ,Group Status Bit 386" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB385 ,Group Status Bit 385" "Group 0,Group 1" bitfld.long 0x00 0. " GSB384 ,Group Status Bit 384" "Group 0,Group 1" else rgroup.long 0x00B0++0x03 line.long 0x0 "GICD_IGROUPR12,Interrupt Group Register 12" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x0D)&&(PER.ADDRESS.isSECUREEX(ad:0xA0021000+0x00B4)) group.long 0x00B4++0x03 line.long 0x0 "GICD_IGROUPR13,Interrupt Group Register 13 (Secure access)" bitfld.long 0x00 31. " GSB447 ,Group Status Bit 447" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 30. " GSB446 ,Group Status Bit 446" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 29. " GSB445 ,Group Status Bit 445" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 28. " GSB444 ,Group Status Bit 444" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 27. " GSB443 ,Group Status Bit 443" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 26. " GSB442 ,Group Status Bit 442" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 25. " GSB441 ,Group Status Bit 441" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 24. " GSB440 ,Group Status Bit 440" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 23. " GSB439 ,Group Status Bit 439" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 22. " GSB438 ,Group Status Bit 438" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 21. " GSB437 ,Group Status Bit 437" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 20. " GSB436 ,Group Status Bit 436" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 19. " GSB435 ,Group Status Bit 435" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 18. " GSB434 ,Group Status Bit 434" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 17. " GSB433 ,Group Status Bit 433" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 16. " GSB432 ,Group Status Bit 432" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 15. " GSB431 ,Group Status Bit 431" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 14. " GSB430 ,Group Status Bit 430" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 13. " GSB429 ,Group Status Bit 429" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 12. " GSB428 ,Group Status Bit 428" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 11. " GSB427 ,Group Status Bit 427" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 10. " GSB426 ,Group Status Bit 426" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 9. " GSB425 ,Group Status Bit 425" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 8. " GSB424 ,Group Status Bit 424" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 7. " GSB423 ,Group Status Bit 423" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 6. " GSB422 ,Group Status Bit 422" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 5. " GSB421 ,Group Status Bit 421" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 4. " GSB420 ,Group Status Bit 420" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 3. " GSB419 ,Group Status Bit 419" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 2. " GSB418 ,Group Status Bit 418" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 1. " GSB417 ,Group Status Bit 417" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 0. " GSB416 ,Group Status Bit 416" "Group 0 (Secure),Group 1 (Non-secure)" elif (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x0D) group.long 0x00B4++0x03 line.long 0x0 "GICD_IGROUPR13,Interrupt Group Register 13 (Non-secure access)" bitfld.long 0x00 31. " GSB447 ,Group Status Bit 447" "Group 0,Group 1" bitfld.long 0x00 30. " GSB446 ,Group Status Bit 446" "Group 0,Group 1" bitfld.long 0x00 29. " GSB445 ,Group Status Bit 445" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB444 ,Group Status Bit 444" "Group 0,Group 1" bitfld.long 0x00 27. " GSB443 ,Group Status Bit 443" "Group 0,Group 1" bitfld.long 0x00 26. " GSB442 ,Group Status Bit 442" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB441 ,Group Status Bit 441" "Group 0,Group 1" bitfld.long 0x00 24. " GSB440 ,Group Status Bit 440" "Group 0,Group 1" bitfld.long 0x00 23. " GSB439 ,Group Status Bit 439" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB438 ,Group Status Bit 438" "Group 0,Group 1" bitfld.long 0x00 21. " GSB437 ,Group Status Bit 437" "Group 0,Group 1" bitfld.long 0x00 20. " GSB436 ,Group Status Bit 436" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB435 ,Group Status Bit 435" "Group 0,Group 1" bitfld.long 0x00 18. " GSB434 ,Group Status Bit 434" "Group 0,Group 1" bitfld.long 0x00 17. " GSB433 ,Group Status Bit 433" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB432 ,Group Status Bit 432" "Group 0,Group 1" bitfld.long 0x00 15. " GSB431 ,Group Status Bit 431" "Group 0,Group 1" bitfld.long 0x00 14. " GSB430 ,Group Status Bit 430" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB429 ,Group Status Bit 429" "Group 0,Group 1" bitfld.long 0x00 12. " GSB428 ,Group Status Bit 428" "Group 0,Group 1" bitfld.long 0x00 11. " GSB427 ,Group Status Bit 427" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB426 ,Group Status Bit 426" "Group 0,Group 1" bitfld.long 0x00 9. " GSB425 ,Group Status Bit 425" "Group 0,Group 1" bitfld.long 0x00 8. " GSB424 ,Group Status Bit 424" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB423 ,Group Status Bit 423" "Group 0,Group 1" bitfld.long 0x00 6. " GSB422 ,Group Status Bit 422" "Group 0,Group 1" bitfld.long 0x00 5. " GSB421 ,Group Status Bit 421" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB420 ,Group Status Bit 420" "Group 0,Group 1" bitfld.long 0x00 3. " GSB419 ,Group Status Bit 419" "Group 0,Group 1" bitfld.long 0x00 2. " GSB418 ,Group Status Bit 418" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB417 ,Group Status Bit 417" "Group 0,Group 1" bitfld.long 0x00 0. " GSB416 ,Group Status Bit 416" "Group 0,Group 1" else rgroup.long 0x00B4++0x03 line.long 0x0 "GICD_IGROUPR13,Interrupt Group Register 13" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x0E)&&(PER.ADDRESS.isSECUREEX(ad:0xA0021000+0x00B8)) group.long 0x00B8++0x03 line.long 0x0 "GICD_IGROUPR14,Interrupt Group Register 14 (Secure access)" bitfld.long 0x00 31. " GSB479 ,Group Status Bit 479" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 30. " GSB478 ,Group Status Bit 478" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 29. " GSB477 ,Group Status Bit 477" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 28. " GSB476 ,Group Status Bit 476" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 27. " GSB475 ,Group Status Bit 475" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 26. " GSB474 ,Group Status Bit 474" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 25. " GSB473 ,Group Status Bit 473" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 24. " GSB472 ,Group Status Bit 472" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 23. " GSB471 ,Group Status Bit 471" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 22. " GSB470 ,Group Status Bit 470" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 21. " GSB469 ,Group Status Bit 469" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 20. " GSB468 ,Group Status Bit 468" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 19. " GSB467 ,Group Status Bit 467" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 18. " GSB466 ,Group Status Bit 466" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 17. " GSB465 ,Group Status Bit 465" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 16. " GSB464 ,Group Status Bit 464" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 15. " GSB463 ,Group Status Bit 463" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 14. " GSB462 ,Group Status Bit 462" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 13. " GSB461 ,Group Status Bit 461" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 12. " GSB460 ,Group Status Bit 460" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 11. " GSB459 ,Group Status Bit 459" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 10. " GSB458 ,Group Status Bit 458" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 9. " GSB457 ,Group Status Bit 457" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 8. " GSB456 ,Group Status Bit 456" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 7. " GSB455 ,Group Status Bit 455" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 6. " GSB454 ,Group Status Bit 454" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 5. " GSB453 ,Group Status Bit 453" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 4. " GSB452 ,Group Status Bit 452" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 3. " GSB451 ,Group Status Bit 451" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 2. " GSB450 ,Group Status Bit 450" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 1. " GSB449 ,Group Status Bit 449" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 0. " GSB448 ,Group Status Bit 448" "Group 0 (Secure),Group 1 (Non-secure)" elif (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x0E) group.long 0x00B8++0x03 line.long 0x0 "GICD_IGROUPR14,Interrupt Group Register 14 (Non-secure access)" bitfld.long 0x00 31. " GSB479 ,Group Status Bit 479" "Group 0,Group 1" bitfld.long 0x00 30. " GSB478 ,Group Status Bit 478" "Group 0,Group 1" bitfld.long 0x00 29. " GSB477 ,Group Status Bit 477" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB476 ,Group Status Bit 476" "Group 0,Group 1" bitfld.long 0x00 27. " GSB475 ,Group Status Bit 475" "Group 0,Group 1" bitfld.long 0x00 26. " GSB474 ,Group Status Bit 474" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB473 ,Group Status Bit 473" "Group 0,Group 1" bitfld.long 0x00 24. " GSB472 ,Group Status Bit 472" "Group 0,Group 1" bitfld.long 0x00 23. " GSB471 ,Group Status Bit 471" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB470 ,Group Status Bit 470" "Group 0,Group 1" bitfld.long 0x00 21. " GSB469 ,Group Status Bit 469" "Group 0,Group 1" bitfld.long 0x00 20. " GSB468 ,Group Status Bit 468" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB467 ,Group Status Bit 467" "Group 0,Group 1" bitfld.long 0x00 18. " GSB466 ,Group Status Bit 466" "Group 0,Group 1" bitfld.long 0x00 17. " GSB465 ,Group Status Bit 465" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB464 ,Group Status Bit 464" "Group 0,Group 1" bitfld.long 0x00 15. " GSB463 ,Group Status Bit 463" "Group 0,Group 1" bitfld.long 0x00 14. " GSB462 ,Group Status Bit 462" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB461 ,Group Status Bit 461" "Group 0,Group 1" bitfld.long 0x00 12. " GSB460 ,Group Status Bit 460" "Group 0,Group 1" bitfld.long 0x00 11. " GSB459 ,Group Status Bit 459" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB458 ,Group Status Bit 458" "Group 0,Group 1" bitfld.long 0x00 9. " GSB457 ,Group Status Bit 457" "Group 0,Group 1" bitfld.long 0x00 8. " GSB456 ,Group Status Bit 456" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB455 ,Group Status Bit 455" "Group 0,Group 1" bitfld.long 0x00 6. " GSB454 ,Group Status Bit 454" "Group 0,Group 1" bitfld.long 0x00 5. " GSB453 ,Group Status Bit 453" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB452 ,Group Status Bit 452" "Group 0,Group 1" bitfld.long 0x00 3. " GSB451 ,Group Status Bit 451" "Group 0,Group 1" bitfld.long 0x00 2. " GSB450 ,Group Status Bit 450" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB449 ,Group Status Bit 449" "Group 0,Group 1" bitfld.long 0x00 0. " GSB448 ,Group Status Bit 448" "Group 0,Group 1" else rgroup.long 0x00B8++0x03 line.long 0x0 "GICD_IGROUPR14,Interrupt Group Register 14" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x0F)&&(PER.ADDRESS.isSECUREEX(ad:0xA0021000+0x00BC)) group.long 0x00BC++0x03 line.long 0x0 "GICD_IGROUPR15,Interrupt Group Register 15 (Secure access)" bitfld.long 0x00 31. " GSB511 ,Group Status Bit 511" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 30. " GSB510 ,Group Status Bit 510" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 29. " GSB509 ,Group Status Bit 509" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 28. " GSB508 ,Group Status Bit 508" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 27. " GSB507 ,Group Status Bit 507" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 26. " GSB506 ,Group Status Bit 506" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 25. " GSB505 ,Group Status Bit 505" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 24. " GSB504 ,Group Status Bit 504" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 23. " GSB503 ,Group Status Bit 503" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 22. " GSB502 ,Group Status Bit 502" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 21. " GSB501 ,Group Status Bit 501" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 20. " GSB500 ,Group Status Bit 500" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 19. " GSB499 ,Group Status Bit 499" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 18. " GSB498 ,Group Status Bit 498" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 17. " GSB497 ,Group Status Bit 497" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 16. " GSB496 ,Group Status Bit 496" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 15. " GSB495 ,Group Status Bit 495" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 14. " GSB494 ,Group Status Bit 494" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 13. " GSB493 ,Group Status Bit 493" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 12. " GSB492 ,Group Status Bit 492" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 11. " GSB491 ,Group Status Bit 491" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 10. " GSB490 ,Group Status Bit 490" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 9. " GSB489 ,Group Status Bit 489" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 8. " GSB488 ,Group Status Bit 488" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 7. " GSB487 ,Group Status Bit 487" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 6. " GSB486 ,Group Status Bit 486" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 5. " GSB485 ,Group Status Bit 485" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 4. " GSB484 ,Group Status Bit 484" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 3. " GSB483 ,Group Status Bit 483" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 2. " GSB482 ,Group Status Bit 482" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 1. " GSB481 ,Group Status Bit 481" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 0. " GSB480 ,Group Status Bit 480" "Group 0 (Secure),Group 1 (Non-secure)" elif (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x0F) group.long 0x00BC++0x03 line.long 0x0 "GICD_IGROUPR15,Interrupt Group Register 15 (Non-secure access)" bitfld.long 0x00 31. " GSB511 ,Group Status Bit 511" "Group 0,Group 1" bitfld.long 0x00 30. " GSB510 ,Group Status Bit 510" "Group 0,Group 1" bitfld.long 0x00 29. " GSB509 ,Group Status Bit 509" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB508 ,Group Status Bit 508" "Group 0,Group 1" bitfld.long 0x00 27. " GSB507 ,Group Status Bit 507" "Group 0,Group 1" bitfld.long 0x00 26. " GSB506 ,Group Status Bit 506" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB505 ,Group Status Bit 505" "Group 0,Group 1" bitfld.long 0x00 24. " GSB504 ,Group Status Bit 504" "Group 0,Group 1" bitfld.long 0x00 23. " GSB503 ,Group Status Bit 503" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB502 ,Group Status Bit 502" "Group 0,Group 1" bitfld.long 0x00 21. " GSB501 ,Group Status Bit 501" "Group 0,Group 1" bitfld.long 0x00 20. " GSB500 ,Group Status Bit 500" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB499 ,Group Status Bit 499" "Group 0,Group 1" bitfld.long 0x00 18. " GSB498 ,Group Status Bit 498" "Group 0,Group 1" bitfld.long 0x00 17. " GSB497 ,Group Status Bit 497" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB496 ,Group Status Bit 496" "Group 0,Group 1" bitfld.long 0x00 15. " GSB495 ,Group Status Bit 495" "Group 0,Group 1" bitfld.long 0x00 14. " GSB494 ,Group Status Bit 494" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB493 ,Group Status Bit 493" "Group 0,Group 1" bitfld.long 0x00 12. " GSB492 ,Group Status Bit 492" "Group 0,Group 1" bitfld.long 0x00 11. " GSB491 ,Group Status Bit 491" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB490 ,Group Status Bit 490" "Group 0,Group 1" bitfld.long 0x00 9. " GSB489 ,Group Status Bit 489" "Group 0,Group 1" bitfld.long 0x00 8. " GSB488 ,Group Status Bit 488" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB487 ,Group Status Bit 487" "Group 0,Group 1" bitfld.long 0x00 6. " GSB486 ,Group Status Bit 486" "Group 0,Group 1" bitfld.long 0x00 5. " GSB485 ,Group Status Bit 485" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB484 ,Group Status Bit 484" "Group 0,Group 1" bitfld.long 0x00 3. " GSB483 ,Group Status Bit 483" "Group 0,Group 1" bitfld.long 0x00 2. " GSB482 ,Group Status Bit 482" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB481 ,Group Status Bit 481" "Group 0,Group 1" bitfld.long 0x00 0. " GSB480 ,Group Status Bit 480" "Group 0,Group 1" else rgroup.long 0x00BC++0x03 line.long 0x0 "GICD_IGROUPR15,Interrupt Group Register 15" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x10)&&(PER.ADDRESS.isSECUREEX(ad:0xA0021000+0x00C0)) group.long 0x00C0++0x03 line.long 0x0 "GICD_IGROUPR16,Interrupt Group Register 16 (Secure access)" bitfld.long 0x00 31. " GSB543 ,Group Status Bit 543" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 30. " GSB542 ,Group Status Bit 542" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 29. " GSB541 ,Group Status Bit 541" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 28. " GSB540 ,Group Status Bit 540" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 27. " GSB539 ,Group Status Bit 539" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 26. " GSB538 ,Group Status Bit 538" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 25. " GSB537 ,Group Status Bit 537" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 24. " GSB536 ,Group Status Bit 536" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 23. " GSB535 ,Group Status Bit 535" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 22. " GSB534 ,Group Status Bit 534" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 21. " GSB533 ,Group Status Bit 533" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 20. " GSB532 ,Group Status Bit 532" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 19. " GSB531 ,Group Status Bit 531" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 18. " GSB530 ,Group Status Bit 530" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 17. " GSB529 ,Group Status Bit 529" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 16. " GSB528 ,Group Status Bit 528" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 15. " GSB527 ,Group Status Bit 527" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 14. " GSB526 ,Group Status Bit 526" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 13. " GSB525 ,Group Status Bit 525" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 12. " GSB524 ,Group Status Bit 524" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 11. " GSB523 ,Group Status Bit 523" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 10. " GSB522 ,Group Status Bit 522" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 9. " GSB521 ,Group Status Bit 521" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 8. " GSB520 ,Group Status Bit 520" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 7. " GSB519 ,Group Status Bit 519" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 6. " GSB518 ,Group Status Bit 518" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 5. " GSB517 ,Group Status Bit 517" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 4. " GSB516 ,Group Status Bit 516" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 3. " GSB515 ,Group Status Bit 515" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 2. " GSB514 ,Group Status Bit 514" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 1. " GSB513 ,Group Status Bit 513" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 0. " GSB512 ,Group Status Bit 512" "Group 0 (Secure),Group 1 (Non-secure)" elif (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x10) group.long 0x00C0++0x03 line.long 0x0 "GICD_IGROUPR16,Interrupt Group Register 16 (Non-secure access)" bitfld.long 0x00 31. " GSB543 ,Group Status Bit 543" "Group 0,Group 1" bitfld.long 0x00 30. " GSB542 ,Group Status Bit 542" "Group 0,Group 1" bitfld.long 0x00 29. " GSB541 ,Group Status Bit 541" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB540 ,Group Status Bit 540" "Group 0,Group 1" bitfld.long 0x00 27. " GSB539 ,Group Status Bit 539" "Group 0,Group 1" bitfld.long 0x00 26. " GSB538 ,Group Status Bit 538" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB537 ,Group Status Bit 537" "Group 0,Group 1" bitfld.long 0x00 24. " GSB536 ,Group Status Bit 536" "Group 0,Group 1" bitfld.long 0x00 23. " GSB535 ,Group Status Bit 535" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB534 ,Group Status Bit 534" "Group 0,Group 1" bitfld.long 0x00 21. " GSB533 ,Group Status Bit 533" "Group 0,Group 1" bitfld.long 0x00 20. " GSB532 ,Group Status Bit 532" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB531 ,Group Status Bit 531" "Group 0,Group 1" bitfld.long 0x00 18. " GSB530 ,Group Status Bit 530" "Group 0,Group 1" bitfld.long 0x00 17. " GSB529 ,Group Status Bit 529" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB528 ,Group Status Bit 528" "Group 0,Group 1" bitfld.long 0x00 15. " GSB527 ,Group Status Bit 527" "Group 0,Group 1" bitfld.long 0x00 14. " GSB526 ,Group Status Bit 526" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB525 ,Group Status Bit 525" "Group 0,Group 1" bitfld.long 0x00 12. " GSB524 ,Group Status Bit 524" "Group 0,Group 1" bitfld.long 0x00 11. " GSB523 ,Group Status Bit 523" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB522 ,Group Status Bit 522" "Group 0,Group 1" bitfld.long 0x00 9. " GSB521 ,Group Status Bit 521" "Group 0,Group 1" bitfld.long 0x00 8. " GSB520 ,Group Status Bit 520" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB519 ,Group Status Bit 519" "Group 0,Group 1" bitfld.long 0x00 6. " GSB518 ,Group Status Bit 518" "Group 0,Group 1" bitfld.long 0x00 5. " GSB517 ,Group Status Bit 517" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB516 ,Group Status Bit 516" "Group 0,Group 1" bitfld.long 0x00 3. " GSB515 ,Group Status Bit 515" "Group 0,Group 1" bitfld.long 0x00 2. " GSB514 ,Group Status Bit 514" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB513 ,Group Status Bit 513" "Group 0,Group 1" bitfld.long 0x00 0. " GSB512 ,Group Status Bit 512" "Group 0,Group 1" else rgroup.long 0x00C0++0x03 line.long 0x0 "GICD_IGROUPR16,Interrupt Group Register 16" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x11)&&(PER.ADDRESS.isSECUREEX(ad:0xA0021000+0x00C4)) group.long 0x00C4++0x03 line.long 0x0 "GICD_IGROUPR17,Interrupt Group Register 17 (Secure access)" bitfld.long 0x00 31. " GSB575 ,Group Status Bit 575" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 30. " GSB574 ,Group Status Bit 574" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 29. " GSB573 ,Group Status Bit 573" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 28. " GSB572 ,Group Status Bit 572" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 27. " GSB571 ,Group Status Bit 571" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 26. " GSB570 ,Group Status Bit 570" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 25. " GSB569 ,Group Status Bit 569" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 24. " GSB568 ,Group Status Bit 568" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 23. " GSB567 ,Group Status Bit 567" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 22. " GSB566 ,Group Status Bit 566" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 21. " GSB565 ,Group Status Bit 565" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 20. " GSB564 ,Group Status Bit 564" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 19. " GSB563 ,Group Status Bit 563" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 18. " GSB562 ,Group Status Bit 562" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 17. " GSB561 ,Group Status Bit 561" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 16. " GSB560 ,Group Status Bit 560" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 15. " GSB559 ,Group Status Bit 559" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 14. " GSB558 ,Group Status Bit 558" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 13. " GSB557 ,Group Status Bit 557" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 12. " GSB556 ,Group Status Bit 556" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 11. " GSB555 ,Group Status Bit 555" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 10. " GSB554 ,Group Status Bit 554" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 9. " GSB553 ,Group Status Bit 553" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 8. " GSB552 ,Group Status Bit 552" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 7. " GSB551 ,Group Status Bit 551" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 6. " GSB550 ,Group Status Bit 550" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 5. " GSB549 ,Group Status Bit 549" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 4. " GSB548 ,Group Status Bit 548" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 3. " GSB547 ,Group Status Bit 547" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 2. " GSB546 ,Group Status Bit 546" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 1. " GSB545 ,Group Status Bit 545" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 0. " GSB544 ,Group Status Bit 544" "Group 0 (Secure),Group 1 (Non-secure)" elif (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x11) group.long 0x00C4++0x03 line.long 0x0 "GICD_IGROUPR17,Interrupt Group Register 17 (Non-secure access)" bitfld.long 0x00 31. " GSB575 ,Group Status Bit 575" "Group 0,Group 1" bitfld.long 0x00 30. " GSB574 ,Group Status Bit 574" "Group 0,Group 1" bitfld.long 0x00 29. " GSB573 ,Group Status Bit 573" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB572 ,Group Status Bit 572" "Group 0,Group 1" bitfld.long 0x00 27. " GSB571 ,Group Status Bit 571" "Group 0,Group 1" bitfld.long 0x00 26. " GSB570 ,Group Status Bit 570" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB569 ,Group Status Bit 569" "Group 0,Group 1" bitfld.long 0x00 24. " GSB568 ,Group Status Bit 568" "Group 0,Group 1" bitfld.long 0x00 23. " GSB567 ,Group Status Bit 567" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB566 ,Group Status Bit 566" "Group 0,Group 1" bitfld.long 0x00 21. " GSB565 ,Group Status Bit 565" "Group 0,Group 1" bitfld.long 0x00 20. " GSB564 ,Group Status Bit 564" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB563 ,Group Status Bit 563" "Group 0,Group 1" bitfld.long 0x00 18. " GSB562 ,Group Status Bit 562" "Group 0,Group 1" bitfld.long 0x00 17. " GSB561 ,Group Status Bit 561" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB560 ,Group Status Bit 560" "Group 0,Group 1" bitfld.long 0x00 15. " GSB559 ,Group Status Bit 559" "Group 0,Group 1" bitfld.long 0x00 14. " GSB558 ,Group Status Bit 558" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB557 ,Group Status Bit 557" "Group 0,Group 1" bitfld.long 0x00 12. " GSB556 ,Group Status Bit 556" "Group 0,Group 1" bitfld.long 0x00 11. " GSB555 ,Group Status Bit 555" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB554 ,Group Status Bit 554" "Group 0,Group 1" bitfld.long 0x00 9. " GSB553 ,Group Status Bit 553" "Group 0,Group 1" bitfld.long 0x00 8. " GSB552 ,Group Status Bit 552" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB551 ,Group Status Bit 551" "Group 0,Group 1" bitfld.long 0x00 6. " GSB550 ,Group Status Bit 550" "Group 0,Group 1" bitfld.long 0x00 5. " GSB549 ,Group Status Bit 549" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB548 ,Group Status Bit 548" "Group 0,Group 1" bitfld.long 0x00 3. " GSB547 ,Group Status Bit 547" "Group 0,Group 1" bitfld.long 0x00 2. " GSB546 ,Group Status Bit 546" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB545 ,Group Status Bit 545" "Group 0,Group 1" bitfld.long 0x00 0. " GSB544 ,Group Status Bit 544" "Group 0,Group 1" else rgroup.long 0x00C4++0x03 line.long 0x0 "GICD_IGROUPR17,Interrupt Group Register 17" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x12)&&(PER.ADDRESS.isSECUREEX(ad:0xA0021000+0x00C8)) group.long 0x00C8++0x03 line.long 0x0 "GICD_IGROUPR18,Interrupt Group Register 18 (Secure access)" bitfld.long 0x00 31. " GSB607 ,Group Status Bit 607" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 30. " GSB606 ,Group Status Bit 606" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 29. " GSB605 ,Group Status Bit 605" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 28. " GSB604 ,Group Status Bit 604" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 27. " GSB603 ,Group Status Bit 603" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 26. " GSB602 ,Group Status Bit 602" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 25. " GSB601 ,Group Status Bit 601" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 24. " GSB600 ,Group Status Bit 600" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 23. " GSB599 ,Group Status Bit 599" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 22. " GSB598 ,Group Status Bit 598" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 21. " GSB597 ,Group Status Bit 597" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 20. " GSB596 ,Group Status Bit 596" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 19. " GSB595 ,Group Status Bit 595" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 18. " GSB594 ,Group Status Bit 594" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 17. " GSB593 ,Group Status Bit 593" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 16. " GSB592 ,Group Status Bit 592" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 15. " GSB591 ,Group Status Bit 591" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 14. " GSB590 ,Group Status Bit 590" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 13. " GSB589 ,Group Status Bit 589" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 12. " GSB588 ,Group Status Bit 588" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 11. " GSB587 ,Group Status Bit 587" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 10. " GSB586 ,Group Status Bit 586" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 9. " GSB585 ,Group Status Bit 585" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 8. " GSB584 ,Group Status Bit 584" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 7. " GSB583 ,Group Status Bit 583" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 6. " GSB582 ,Group Status Bit 582" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 5. " GSB581 ,Group Status Bit 581" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 4. " GSB580 ,Group Status Bit 580" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 3. " GSB579 ,Group Status Bit 579" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 2. " GSB578 ,Group Status Bit 578" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 1. " GSB577 ,Group Status Bit 577" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 0. " GSB576 ,Group Status Bit 576" "Group 0 (Secure),Group 1 (Non-secure)" elif (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x12) group.long 0x00C8++0x03 line.long 0x0 "GICD_IGROUPR18,Interrupt Group Register 18 (Non-secure access)" bitfld.long 0x00 31. " GSB607 ,Group Status Bit 607" "Group 0,Group 1" bitfld.long 0x00 30. " GSB606 ,Group Status Bit 606" "Group 0,Group 1" bitfld.long 0x00 29. " GSB605 ,Group Status Bit 605" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB604 ,Group Status Bit 604" "Group 0,Group 1" bitfld.long 0x00 27. " GSB603 ,Group Status Bit 603" "Group 0,Group 1" bitfld.long 0x00 26. " GSB602 ,Group Status Bit 602" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB601 ,Group Status Bit 601" "Group 0,Group 1" bitfld.long 0x00 24. " GSB600 ,Group Status Bit 600" "Group 0,Group 1" bitfld.long 0x00 23. " GSB599 ,Group Status Bit 599" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB598 ,Group Status Bit 598" "Group 0,Group 1" bitfld.long 0x00 21. " GSB597 ,Group Status Bit 597" "Group 0,Group 1" bitfld.long 0x00 20. " GSB596 ,Group Status Bit 596" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB595 ,Group Status Bit 595" "Group 0,Group 1" bitfld.long 0x00 18. " GSB594 ,Group Status Bit 594" "Group 0,Group 1" bitfld.long 0x00 17. " GSB593 ,Group Status Bit 593" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB592 ,Group Status Bit 592" "Group 0,Group 1" bitfld.long 0x00 15. " GSB591 ,Group Status Bit 591" "Group 0,Group 1" bitfld.long 0x00 14. " GSB590 ,Group Status Bit 590" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB589 ,Group Status Bit 589" "Group 0,Group 1" bitfld.long 0x00 12. " GSB588 ,Group Status Bit 588" "Group 0,Group 1" bitfld.long 0x00 11. " GSB587 ,Group Status Bit 587" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB586 ,Group Status Bit 586" "Group 0,Group 1" bitfld.long 0x00 9. " GSB585 ,Group Status Bit 585" "Group 0,Group 1" bitfld.long 0x00 8. " GSB584 ,Group Status Bit 584" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB583 ,Group Status Bit 583" "Group 0,Group 1" bitfld.long 0x00 6. " GSB582 ,Group Status Bit 582" "Group 0,Group 1" bitfld.long 0x00 5. " GSB581 ,Group Status Bit 581" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB580 ,Group Status Bit 580" "Group 0,Group 1" bitfld.long 0x00 3. " GSB579 ,Group Status Bit 579" "Group 0,Group 1" bitfld.long 0x00 2. " GSB578 ,Group Status Bit 578" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB577 ,Group Status Bit 577" "Group 0,Group 1" bitfld.long 0x00 0. " GSB576 ,Group Status Bit 576" "Group 0,Group 1" else rgroup.long 0x00C8++0x03 line.long 0x0 "GICD_IGROUPR18,Interrupt Group Register 18" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x13)&&(PER.ADDRESS.isSECUREEX(ad:0xA0021000+0x00CC)) group.long 0x00CC++0x03 line.long 0x0 "GICD_IGROUPR19,Interrupt Group Register 19 (Secure access)" bitfld.long 0x00 31. " GSB639 ,Group Status Bit 639" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 30. " GSB638 ,Group Status Bit 638" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 29. " GSB637 ,Group Status Bit 637" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 28. " GSB636 ,Group Status Bit 636" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 27. " GSB635 ,Group Status Bit 635" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 26. " GSB634 ,Group Status Bit 634" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 25. " GSB633 ,Group Status Bit 633" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 24. " GSB632 ,Group Status Bit 632" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 23. " GSB631 ,Group Status Bit 631" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 22. " GSB630 ,Group Status Bit 630" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 21. " GSB629 ,Group Status Bit 629" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 20. " GSB628 ,Group Status Bit 628" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 19. " GSB627 ,Group Status Bit 627" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 18. " GSB626 ,Group Status Bit 626" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 17. " GSB625 ,Group Status Bit 625" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 16. " GSB624 ,Group Status Bit 624" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 15. " GSB623 ,Group Status Bit 623" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 14. " GSB622 ,Group Status Bit 622" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 13. " GSB621 ,Group Status Bit 621" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 12. " GSB620 ,Group Status Bit 620" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 11. " GSB619 ,Group Status Bit 619" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 10. " GSB618 ,Group Status Bit 618" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 9. " GSB617 ,Group Status Bit 617" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 8. " GSB616 ,Group Status Bit 616" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 7. " GSB615 ,Group Status Bit 615" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 6. " GSB614 ,Group Status Bit 614" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 5. " GSB613 ,Group Status Bit 613" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 4. " GSB612 ,Group Status Bit 612" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 3. " GSB611 ,Group Status Bit 611" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 2. " GSB610 ,Group Status Bit 610" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 1. " GSB609 ,Group Status Bit 609" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 0. " GSB608 ,Group Status Bit 608" "Group 0 (Secure),Group 1 (Non-secure)" elif (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x13) group.long 0x00CC++0x03 line.long 0x0 "GICD_IGROUPR19,Interrupt Group Register 19 (Non-secure access)" bitfld.long 0x00 31. " GSB639 ,Group Status Bit 639" "Group 0,Group 1" bitfld.long 0x00 30. " GSB638 ,Group Status Bit 638" "Group 0,Group 1" bitfld.long 0x00 29. " GSB637 ,Group Status Bit 637" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB636 ,Group Status Bit 636" "Group 0,Group 1" bitfld.long 0x00 27. " GSB635 ,Group Status Bit 635" "Group 0,Group 1" bitfld.long 0x00 26. " GSB634 ,Group Status Bit 634" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB633 ,Group Status Bit 633" "Group 0,Group 1" bitfld.long 0x00 24. " GSB632 ,Group Status Bit 632" "Group 0,Group 1" bitfld.long 0x00 23. " GSB631 ,Group Status Bit 631" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB630 ,Group Status Bit 630" "Group 0,Group 1" bitfld.long 0x00 21. " GSB629 ,Group Status Bit 629" "Group 0,Group 1" bitfld.long 0x00 20. " GSB628 ,Group Status Bit 628" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB627 ,Group Status Bit 627" "Group 0,Group 1" bitfld.long 0x00 18. " GSB626 ,Group Status Bit 626" "Group 0,Group 1" bitfld.long 0x00 17. " GSB625 ,Group Status Bit 625" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB624 ,Group Status Bit 624" "Group 0,Group 1" bitfld.long 0x00 15. " GSB623 ,Group Status Bit 623" "Group 0,Group 1" bitfld.long 0x00 14. " GSB622 ,Group Status Bit 622" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB621 ,Group Status Bit 621" "Group 0,Group 1" bitfld.long 0x00 12. " GSB620 ,Group Status Bit 620" "Group 0,Group 1" bitfld.long 0x00 11. " GSB619 ,Group Status Bit 619" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB618 ,Group Status Bit 618" "Group 0,Group 1" bitfld.long 0x00 9. " GSB617 ,Group Status Bit 617" "Group 0,Group 1" bitfld.long 0x00 8. " GSB616 ,Group Status Bit 616" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB615 ,Group Status Bit 615" "Group 0,Group 1" bitfld.long 0x00 6. " GSB614 ,Group Status Bit 614" "Group 0,Group 1" bitfld.long 0x00 5. " GSB613 ,Group Status Bit 613" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB612 ,Group Status Bit 612" "Group 0,Group 1" bitfld.long 0x00 3. " GSB611 ,Group Status Bit 611" "Group 0,Group 1" bitfld.long 0x00 2. " GSB610 ,Group Status Bit 610" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB609 ,Group Status Bit 609" "Group 0,Group 1" bitfld.long 0x00 0. " GSB608 ,Group Status Bit 608" "Group 0,Group 1" else rgroup.long 0x00CC++0x03 line.long 0x0 "GICD_IGROUPR19,Interrupt Group Register 19" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x14)&&(PER.ADDRESS.isSECUREEX(ad:0xA0021000+0x00D0)) group.long 0x00D0++0x03 line.long 0x0 "GICD_IGROUPR20,Interrupt Group Register 20 (Secure access)" bitfld.long 0x00 31. " GSB671 ,Group Status Bit 671" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 30. " GSB670 ,Group Status Bit 670" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 29. " GSB669 ,Group Status Bit 669" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 28. " GSB668 ,Group Status Bit 668" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 27. " GSB667 ,Group Status Bit 667" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 26. " GSB666 ,Group Status Bit 666" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 25. " GSB665 ,Group Status Bit 665" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 24. " GSB664 ,Group Status Bit 664" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 23. " GSB663 ,Group Status Bit 663" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 22. " GSB662 ,Group Status Bit 662" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 21. " GSB661 ,Group Status Bit 661" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 20. " GSB660 ,Group Status Bit 660" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 19. " GSB659 ,Group Status Bit 659" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 18. " GSB658 ,Group Status Bit 658" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 17. " GSB657 ,Group Status Bit 657" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 16. " GSB656 ,Group Status Bit 656" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 15. " GSB655 ,Group Status Bit 655" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 14. " GSB654 ,Group Status Bit 654" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 13. " GSB653 ,Group Status Bit 653" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 12. " GSB652 ,Group Status Bit 652" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 11. " GSB651 ,Group Status Bit 651" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 10. " GSB650 ,Group Status Bit 650" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 9. " GSB649 ,Group Status Bit 649" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 8. " GSB648 ,Group Status Bit 648" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 7. " GSB647 ,Group Status Bit 647" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 6. " GSB646 ,Group Status Bit 646" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 5. " GSB645 ,Group Status Bit 645" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 4. " GSB644 ,Group Status Bit 644" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 3. " GSB643 ,Group Status Bit 643" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 2. " GSB642 ,Group Status Bit 642" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 1. " GSB641 ,Group Status Bit 641" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 0. " GSB640 ,Group Status Bit 640" "Group 0 (Secure),Group 1 (Non-secure)" elif (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x14) group.long 0x00D0++0x03 line.long 0x0 "GICD_IGROUPR20,Interrupt Group Register 20 (Non-secure access)" bitfld.long 0x00 31. " GSB671 ,Group Status Bit 671" "Group 0,Group 1" bitfld.long 0x00 30. " GSB670 ,Group Status Bit 670" "Group 0,Group 1" bitfld.long 0x00 29. " GSB669 ,Group Status Bit 669" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB668 ,Group Status Bit 668" "Group 0,Group 1" bitfld.long 0x00 27. " GSB667 ,Group Status Bit 667" "Group 0,Group 1" bitfld.long 0x00 26. " GSB666 ,Group Status Bit 666" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB665 ,Group Status Bit 665" "Group 0,Group 1" bitfld.long 0x00 24. " GSB664 ,Group Status Bit 664" "Group 0,Group 1" bitfld.long 0x00 23. " GSB663 ,Group Status Bit 663" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB662 ,Group Status Bit 662" "Group 0,Group 1" bitfld.long 0x00 21. " GSB661 ,Group Status Bit 661" "Group 0,Group 1" bitfld.long 0x00 20. " GSB660 ,Group Status Bit 660" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB659 ,Group Status Bit 659" "Group 0,Group 1" bitfld.long 0x00 18. " GSB658 ,Group Status Bit 658" "Group 0,Group 1" bitfld.long 0x00 17. " GSB657 ,Group Status Bit 657" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB656 ,Group Status Bit 656" "Group 0,Group 1" bitfld.long 0x00 15. " GSB655 ,Group Status Bit 655" "Group 0,Group 1" bitfld.long 0x00 14. " GSB654 ,Group Status Bit 654" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB653 ,Group Status Bit 653" "Group 0,Group 1" bitfld.long 0x00 12. " GSB652 ,Group Status Bit 652" "Group 0,Group 1" bitfld.long 0x00 11. " GSB651 ,Group Status Bit 651" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB650 ,Group Status Bit 650" "Group 0,Group 1" bitfld.long 0x00 9. " GSB649 ,Group Status Bit 649" "Group 0,Group 1" bitfld.long 0x00 8. " GSB648 ,Group Status Bit 648" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB647 ,Group Status Bit 647" "Group 0,Group 1" bitfld.long 0x00 6. " GSB646 ,Group Status Bit 646" "Group 0,Group 1" bitfld.long 0x00 5. " GSB645 ,Group Status Bit 645" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB644 ,Group Status Bit 644" "Group 0,Group 1" bitfld.long 0x00 3. " GSB643 ,Group Status Bit 643" "Group 0,Group 1" bitfld.long 0x00 2. " GSB642 ,Group Status Bit 642" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB641 ,Group Status Bit 641" "Group 0,Group 1" bitfld.long 0x00 0. " GSB640 ,Group Status Bit 640" "Group 0,Group 1" else rgroup.long 0x00D0++0x03 line.long 0x0 "GICD_IGROUPR20,Interrupt Group Register 20" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x15)&&(PER.ADDRESS.isSECUREEX(ad:0xA0021000+0x00D4)) group.long 0x00D4++0x03 line.long 0x0 "GICD_IGROUPR21,Interrupt Group Register 21 (Secure access)" bitfld.long 0x00 31. " GSB703 ,Group Status Bit 703" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 30. " GSB702 ,Group Status Bit 702" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 29. " GSB701 ,Group Status Bit 701" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 28. " GSB700 ,Group Status Bit 700" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 27. " GSB699 ,Group Status Bit 699" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 26. " GSB698 ,Group Status Bit 698" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 25. " GSB697 ,Group Status Bit 697" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 24. " GSB696 ,Group Status Bit 696" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 23. " GSB695 ,Group Status Bit 695" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 22. " GSB694 ,Group Status Bit 694" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 21. " GSB693 ,Group Status Bit 693" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 20. " GSB692 ,Group Status Bit 692" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 19. " GSB691 ,Group Status Bit 691" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 18. " GSB690 ,Group Status Bit 690" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 17. " GSB689 ,Group Status Bit 689" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 16. " GSB688 ,Group Status Bit 688" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 15. " GSB687 ,Group Status Bit 687" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 14. " GSB686 ,Group Status Bit 686" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 13. " GSB685 ,Group Status Bit 685" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 12. " GSB684 ,Group Status Bit 684" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 11. " GSB683 ,Group Status Bit 683" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 10. " GSB682 ,Group Status Bit 682" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 9. " GSB681 ,Group Status Bit 681" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 8. " GSB680 ,Group Status Bit 680" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 7. " GSB679 ,Group Status Bit 679" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 6. " GSB678 ,Group Status Bit 678" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 5. " GSB677 ,Group Status Bit 677" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 4. " GSB676 ,Group Status Bit 676" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 3. " GSB675 ,Group Status Bit 675" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 2. " GSB674 ,Group Status Bit 674" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 1. " GSB673 ,Group Status Bit 673" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 0. " GSB672 ,Group Status Bit 672" "Group 0 (Secure),Group 1 (Non-secure)" elif (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x15) group.long 0x00D4++0x03 line.long 0x0 "GICD_IGROUPR21,Interrupt Group Register 21 (Non-secure access)" bitfld.long 0x00 31. " GSB703 ,Group Status Bit 703" "Group 0,Group 1" bitfld.long 0x00 30. " GSB702 ,Group Status Bit 702" "Group 0,Group 1" bitfld.long 0x00 29. " GSB701 ,Group Status Bit 701" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB700 ,Group Status Bit 700" "Group 0,Group 1" bitfld.long 0x00 27. " GSB699 ,Group Status Bit 699" "Group 0,Group 1" bitfld.long 0x00 26. " GSB698 ,Group Status Bit 698" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB697 ,Group Status Bit 697" "Group 0,Group 1" bitfld.long 0x00 24. " GSB696 ,Group Status Bit 696" "Group 0,Group 1" bitfld.long 0x00 23. " GSB695 ,Group Status Bit 695" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB694 ,Group Status Bit 694" "Group 0,Group 1" bitfld.long 0x00 21. " GSB693 ,Group Status Bit 693" "Group 0,Group 1" bitfld.long 0x00 20. " GSB692 ,Group Status Bit 692" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB691 ,Group Status Bit 691" "Group 0,Group 1" bitfld.long 0x00 18. " GSB690 ,Group Status Bit 690" "Group 0,Group 1" bitfld.long 0x00 17. " GSB689 ,Group Status Bit 689" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB688 ,Group Status Bit 688" "Group 0,Group 1" bitfld.long 0x00 15. " GSB687 ,Group Status Bit 687" "Group 0,Group 1" bitfld.long 0x00 14. " GSB686 ,Group Status Bit 686" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB685 ,Group Status Bit 685" "Group 0,Group 1" bitfld.long 0x00 12. " GSB684 ,Group Status Bit 684" "Group 0,Group 1" bitfld.long 0x00 11. " GSB683 ,Group Status Bit 683" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB682 ,Group Status Bit 682" "Group 0,Group 1" bitfld.long 0x00 9. " GSB681 ,Group Status Bit 681" "Group 0,Group 1" bitfld.long 0x00 8. " GSB680 ,Group Status Bit 680" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB679 ,Group Status Bit 679" "Group 0,Group 1" bitfld.long 0x00 6. " GSB678 ,Group Status Bit 678" "Group 0,Group 1" bitfld.long 0x00 5. " GSB677 ,Group Status Bit 677" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB676 ,Group Status Bit 676" "Group 0,Group 1" bitfld.long 0x00 3. " GSB675 ,Group Status Bit 675" "Group 0,Group 1" bitfld.long 0x00 2. " GSB674 ,Group Status Bit 674" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB673 ,Group Status Bit 673" "Group 0,Group 1" bitfld.long 0x00 0. " GSB672 ,Group Status Bit 672" "Group 0,Group 1" else rgroup.long 0x00D4++0x03 line.long 0x0 "GICD_IGROUPR21,Interrupt Group Register 21" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x16)&&(PER.ADDRESS.isSECUREEX(ad:0xA0021000+0x00D8)) group.long 0x00D8++0x03 line.long 0x0 "GICD_IGROUPR22,Interrupt Group Register 22 (Secure access)" bitfld.long 0x00 31. " GSB735 ,Group Status Bit 735" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 30. " GSB734 ,Group Status Bit 734" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 29. " GSB733 ,Group Status Bit 733" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 28. " GSB732 ,Group Status Bit 732" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 27. " GSB731 ,Group Status Bit 731" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 26. " GSB730 ,Group Status Bit 730" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 25. " GSB729 ,Group Status Bit 729" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 24. " GSB728 ,Group Status Bit 728" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 23. " GSB727 ,Group Status Bit 727" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 22. " GSB726 ,Group Status Bit 726" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 21. " GSB725 ,Group Status Bit 725" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 20. " GSB724 ,Group Status Bit 724" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 19. " GSB723 ,Group Status Bit 723" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 18. " GSB722 ,Group Status Bit 722" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 17. " GSB721 ,Group Status Bit 721" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 16. " GSB720 ,Group Status Bit 720" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 15. " GSB719 ,Group Status Bit 719" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 14. " GSB718 ,Group Status Bit 718" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 13. " GSB717 ,Group Status Bit 717" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 12. " GSB716 ,Group Status Bit 716" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 11. " GSB715 ,Group Status Bit 715" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 10. " GSB714 ,Group Status Bit 714" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 9. " GSB713 ,Group Status Bit 713" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 8. " GSB712 ,Group Status Bit 712" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 7. " GSB711 ,Group Status Bit 711" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 6. " GSB710 ,Group Status Bit 710" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 5. " GSB709 ,Group Status Bit 709" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 4. " GSB708 ,Group Status Bit 708" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 3. " GSB707 ,Group Status Bit 707" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 2. " GSB706 ,Group Status Bit 706" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 1. " GSB705 ,Group Status Bit 705" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 0. " GSB704 ,Group Status Bit 704" "Group 0 (Secure),Group 1 (Non-secure)" elif (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x16) group.long 0x00D8++0x03 line.long 0x0 "GICD_IGROUPR22,Interrupt Group Register 22 (Non-secure access)" bitfld.long 0x00 31. " GSB735 ,Group Status Bit 735" "Group 0,Group 1" bitfld.long 0x00 30. " GSB734 ,Group Status Bit 734" "Group 0,Group 1" bitfld.long 0x00 29. " GSB733 ,Group Status Bit 733" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB732 ,Group Status Bit 732" "Group 0,Group 1" bitfld.long 0x00 27. " GSB731 ,Group Status Bit 731" "Group 0,Group 1" bitfld.long 0x00 26. " GSB730 ,Group Status Bit 730" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB729 ,Group Status Bit 729" "Group 0,Group 1" bitfld.long 0x00 24. " GSB728 ,Group Status Bit 728" "Group 0,Group 1" bitfld.long 0x00 23. " GSB727 ,Group Status Bit 727" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB726 ,Group Status Bit 726" "Group 0,Group 1" bitfld.long 0x00 21. " GSB725 ,Group Status Bit 725" "Group 0,Group 1" bitfld.long 0x00 20. " GSB724 ,Group Status Bit 724" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB723 ,Group Status Bit 723" "Group 0,Group 1" bitfld.long 0x00 18. " GSB722 ,Group Status Bit 722" "Group 0,Group 1" bitfld.long 0x00 17. " GSB721 ,Group Status Bit 721" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB720 ,Group Status Bit 720" "Group 0,Group 1" bitfld.long 0x00 15. " GSB719 ,Group Status Bit 719" "Group 0,Group 1" bitfld.long 0x00 14. " GSB718 ,Group Status Bit 718" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB717 ,Group Status Bit 717" "Group 0,Group 1" bitfld.long 0x00 12. " GSB716 ,Group Status Bit 716" "Group 0,Group 1" bitfld.long 0x00 11. " GSB715 ,Group Status Bit 715" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB714 ,Group Status Bit 714" "Group 0,Group 1" bitfld.long 0x00 9. " GSB713 ,Group Status Bit 713" "Group 0,Group 1" bitfld.long 0x00 8. " GSB712 ,Group Status Bit 712" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB711 ,Group Status Bit 711" "Group 0,Group 1" bitfld.long 0x00 6. " GSB710 ,Group Status Bit 710" "Group 0,Group 1" bitfld.long 0x00 5. " GSB709 ,Group Status Bit 709" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB708 ,Group Status Bit 708" "Group 0,Group 1" bitfld.long 0x00 3. " GSB707 ,Group Status Bit 707" "Group 0,Group 1" bitfld.long 0x00 2. " GSB706 ,Group Status Bit 706" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB705 ,Group Status Bit 705" "Group 0,Group 1" bitfld.long 0x00 0. " GSB704 ,Group Status Bit 704" "Group 0,Group 1" else rgroup.long 0x00D8++0x03 line.long 0x0 "GICD_IGROUPR22,Interrupt Group Register 22" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x17)&&(PER.ADDRESS.isSECUREEX(ad:0xA0021000+0x00DC)) group.long 0x00DC++0x03 line.long 0x0 "GICD_IGROUPR23,Interrupt Group Register 23 (Secure access)" bitfld.long 0x00 31. " GSB767 ,Group Status Bit 767" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 30. " GSB766 ,Group Status Bit 766" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 29. " GSB765 ,Group Status Bit 765" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 28. " GSB764 ,Group Status Bit 764" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 27. " GSB763 ,Group Status Bit 763" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 26. " GSB762 ,Group Status Bit 762" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 25. " GSB761 ,Group Status Bit 761" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 24. " GSB760 ,Group Status Bit 760" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 23. " GSB759 ,Group Status Bit 759" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 22. " GSB758 ,Group Status Bit 758" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 21. " GSB757 ,Group Status Bit 757" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 20. " GSB756 ,Group Status Bit 756" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 19. " GSB755 ,Group Status Bit 755" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 18. " GSB754 ,Group Status Bit 754" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 17. " GSB753 ,Group Status Bit 753" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 16. " GSB752 ,Group Status Bit 752" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 15. " GSB751 ,Group Status Bit 751" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 14. " GSB750 ,Group Status Bit 750" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 13. " GSB749 ,Group Status Bit 749" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 12. " GSB748 ,Group Status Bit 748" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 11. " GSB747 ,Group Status Bit 747" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 10. " GSB746 ,Group Status Bit 746" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 9. " GSB745 ,Group Status Bit 745" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 8. " GSB744 ,Group Status Bit 744" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 7. " GSB743 ,Group Status Bit 743" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 6. " GSB742 ,Group Status Bit 742" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 5. " GSB741 ,Group Status Bit 741" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 4. " GSB740 ,Group Status Bit 740" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 3. " GSB739 ,Group Status Bit 739" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 2. " GSB738 ,Group Status Bit 738" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 1. " GSB737 ,Group Status Bit 737" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 0. " GSB736 ,Group Status Bit 736" "Group 0 (Secure),Group 1 (Non-secure)" elif (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x17) group.long 0x00DC++0x03 line.long 0x0 "GICD_IGROUPR23,Interrupt Group Register 23 (Non-secure access)" bitfld.long 0x00 31. " GSB767 ,Group Status Bit 767" "Group 0,Group 1" bitfld.long 0x00 30. " GSB766 ,Group Status Bit 766" "Group 0,Group 1" bitfld.long 0x00 29. " GSB765 ,Group Status Bit 765" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB764 ,Group Status Bit 764" "Group 0,Group 1" bitfld.long 0x00 27. " GSB763 ,Group Status Bit 763" "Group 0,Group 1" bitfld.long 0x00 26. " GSB762 ,Group Status Bit 762" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB761 ,Group Status Bit 761" "Group 0,Group 1" bitfld.long 0x00 24. " GSB760 ,Group Status Bit 760" "Group 0,Group 1" bitfld.long 0x00 23. " GSB759 ,Group Status Bit 759" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB758 ,Group Status Bit 758" "Group 0,Group 1" bitfld.long 0x00 21. " GSB757 ,Group Status Bit 757" "Group 0,Group 1" bitfld.long 0x00 20. " GSB756 ,Group Status Bit 756" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB755 ,Group Status Bit 755" "Group 0,Group 1" bitfld.long 0x00 18. " GSB754 ,Group Status Bit 754" "Group 0,Group 1" bitfld.long 0x00 17. " GSB753 ,Group Status Bit 753" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB752 ,Group Status Bit 752" "Group 0,Group 1" bitfld.long 0x00 15. " GSB751 ,Group Status Bit 751" "Group 0,Group 1" bitfld.long 0x00 14. " GSB750 ,Group Status Bit 750" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB749 ,Group Status Bit 749" "Group 0,Group 1" bitfld.long 0x00 12. " GSB748 ,Group Status Bit 748" "Group 0,Group 1" bitfld.long 0x00 11. " GSB747 ,Group Status Bit 747" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB746 ,Group Status Bit 746" "Group 0,Group 1" bitfld.long 0x00 9. " GSB745 ,Group Status Bit 745" "Group 0,Group 1" bitfld.long 0x00 8. " GSB744 ,Group Status Bit 744" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB743 ,Group Status Bit 743" "Group 0,Group 1" bitfld.long 0x00 6. " GSB742 ,Group Status Bit 742" "Group 0,Group 1" bitfld.long 0x00 5. " GSB741 ,Group Status Bit 741" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB740 ,Group Status Bit 740" "Group 0,Group 1" bitfld.long 0x00 3. " GSB739 ,Group Status Bit 739" "Group 0,Group 1" bitfld.long 0x00 2. " GSB738 ,Group Status Bit 738" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB737 ,Group Status Bit 737" "Group 0,Group 1" bitfld.long 0x00 0. " GSB736 ,Group Status Bit 736" "Group 0,Group 1" else rgroup.long 0x00DC++0x03 line.long 0x0 "GICD_IGROUPR23,Interrupt Group Register 23" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x18)&&(PER.ADDRESS.isSECUREEX(ad:0xA0021000+0x00E0)) group.long 0x00E0++0x03 line.long 0x0 "GICD_IGROUPR24,Interrupt Group Register 24 (Secure access)" bitfld.long 0x00 31. " GSB799 ,Group Status Bit 799" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 30. " GSB798 ,Group Status Bit 798" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 29. " GSB797 ,Group Status Bit 797" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 28. " GSB796 ,Group Status Bit 796" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 27. " GSB795 ,Group Status Bit 795" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 26. " GSB794 ,Group Status Bit 794" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 25. " GSB793 ,Group Status Bit 793" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 24. " GSB792 ,Group Status Bit 792" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 23. " GSB791 ,Group Status Bit 791" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 22. " GSB790 ,Group Status Bit 790" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 21. " GSB789 ,Group Status Bit 789" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 20. " GSB788 ,Group Status Bit 788" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 19. " GSB787 ,Group Status Bit 787" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 18. " GSB786 ,Group Status Bit 786" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 17. " GSB785 ,Group Status Bit 785" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 16. " GSB784 ,Group Status Bit 784" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 15. " GSB783 ,Group Status Bit 783" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 14. " GSB782 ,Group Status Bit 782" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 13. " GSB781 ,Group Status Bit 781" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 12. " GSB780 ,Group Status Bit 780" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 11. " GSB779 ,Group Status Bit 779" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 10. " GSB778 ,Group Status Bit 778" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 9. " GSB777 ,Group Status Bit 777" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 8. " GSB776 ,Group Status Bit 776" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 7. " GSB775 ,Group Status Bit 775" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 6. " GSB774 ,Group Status Bit 774" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 5. " GSB773 ,Group Status Bit 773" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 4. " GSB772 ,Group Status Bit 772" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 3. " GSB771 ,Group Status Bit 771" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 2. " GSB770 ,Group Status Bit 770" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 1. " GSB769 ,Group Status Bit 769" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 0. " GSB768 ,Group Status Bit 768" "Group 0 (Secure),Group 1 (Non-secure)" elif (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x18) group.long 0x00E0++0x03 line.long 0x0 "GICD_IGROUPR24,Interrupt Group Register 24 (Non-secure access)" bitfld.long 0x00 31. " GSB799 ,Group Status Bit 799" "Group 0,Group 1" bitfld.long 0x00 30. " GSB798 ,Group Status Bit 798" "Group 0,Group 1" bitfld.long 0x00 29. " GSB797 ,Group Status Bit 797" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB796 ,Group Status Bit 796" "Group 0,Group 1" bitfld.long 0x00 27. " GSB795 ,Group Status Bit 795" "Group 0,Group 1" bitfld.long 0x00 26. " GSB794 ,Group Status Bit 794" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB793 ,Group Status Bit 793" "Group 0,Group 1" bitfld.long 0x00 24. " GSB792 ,Group Status Bit 792" "Group 0,Group 1" bitfld.long 0x00 23. " GSB791 ,Group Status Bit 791" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB790 ,Group Status Bit 790" "Group 0,Group 1" bitfld.long 0x00 21. " GSB789 ,Group Status Bit 789" "Group 0,Group 1" bitfld.long 0x00 20. " GSB788 ,Group Status Bit 788" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB787 ,Group Status Bit 787" "Group 0,Group 1" bitfld.long 0x00 18. " GSB786 ,Group Status Bit 786" "Group 0,Group 1" bitfld.long 0x00 17. " GSB785 ,Group Status Bit 785" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB784 ,Group Status Bit 784" "Group 0,Group 1" bitfld.long 0x00 15. " GSB783 ,Group Status Bit 783" "Group 0,Group 1" bitfld.long 0x00 14. " GSB782 ,Group Status Bit 782" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB781 ,Group Status Bit 781" "Group 0,Group 1" bitfld.long 0x00 12. " GSB780 ,Group Status Bit 780" "Group 0,Group 1" bitfld.long 0x00 11. " GSB779 ,Group Status Bit 779" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB778 ,Group Status Bit 778" "Group 0,Group 1" bitfld.long 0x00 9. " GSB777 ,Group Status Bit 777" "Group 0,Group 1" bitfld.long 0x00 8. " GSB776 ,Group Status Bit 776" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB775 ,Group Status Bit 775" "Group 0,Group 1" bitfld.long 0x00 6. " GSB774 ,Group Status Bit 774" "Group 0,Group 1" bitfld.long 0x00 5. " GSB773 ,Group Status Bit 773" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB772 ,Group Status Bit 772" "Group 0,Group 1" bitfld.long 0x00 3. " GSB771 ,Group Status Bit 771" "Group 0,Group 1" bitfld.long 0x00 2. " GSB770 ,Group Status Bit 770" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB769 ,Group Status Bit 769" "Group 0,Group 1" bitfld.long 0x00 0. " GSB768 ,Group Status Bit 768" "Group 0,Group 1" else rgroup.long 0x0E0++0x03 line.long 0x0 "GICD_IGROUPR24,Interrupt Group Register 24" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x19)&&(PER.ADDRESS.isSECUREEX(ad:0xA0021000+0x00E4)) group.long 0x00E4++0x03 line.long 0x0 "GICD_IGROUPR25,Interrupt Group Register 25 (Secure access)" bitfld.long 0x00 31. " GSB831 ,Group Status Bit 831" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 30. " GSB830 ,Group Status Bit 830" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 29. " GSB829 ,Group Status Bit 829" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 28. " GSB828 ,Group Status Bit 828" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 27. " GSB827 ,Group Status Bit 827" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 26. " GSB826 ,Group Status Bit 826" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 25. " GSB825 ,Group Status Bit 825" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 24. " GSB824 ,Group Status Bit 824" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 23. " GSB823 ,Group Status Bit 823" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 22. " GSB822 ,Group Status Bit 822" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 21. " GSB821 ,Group Status Bit 821" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 20. " GSB820 ,Group Status Bit 820" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 19. " GSB819 ,Group Status Bit 819" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 18. " GSB818 ,Group Status Bit 818" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 17. " GSB817 ,Group Status Bit 817" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 16. " GSB816 ,Group Status Bit 816" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 15. " GSB815 ,Group Status Bit 815" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 14. " GSB814 ,Group Status Bit 814" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 13. " GSB813 ,Group Status Bit 813" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 12. " GSB812 ,Group Status Bit 812" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 11. " GSB811 ,Group Status Bit 811" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 10. " GSB810 ,Group Status Bit 810" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 9. " GSB809 ,Group Status Bit 809" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 8. " GSB808 ,Group Status Bit 808" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 7. " GSB807 ,Group Status Bit 807" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 6. " GSB806 ,Group Status Bit 806" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 5. " GSB805 ,Group Status Bit 805" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 4. " GSB804 ,Group Status Bit 804" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 3. " GSB803 ,Group Status Bit 803" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 2. " GSB802 ,Group Status Bit 802" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 1. " GSB801 ,Group Status Bit 801" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 0. " GSB800 ,Group Status Bit 800" "Group 0 (Secure),Group 1 (Non-secure)" elif (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x19) group.long 0x00E4++0x03 line.long 0x0 "GICD_IGROUPR25,Interrupt Group Register 25 (Non-secure access)" bitfld.long 0x00 31. " GSB831 ,Group Status Bit 831" "Group 0,Group 1" bitfld.long 0x00 30. " GSB830 ,Group Status Bit 830" "Group 0,Group 1" bitfld.long 0x00 29. " GSB829 ,Group Status Bit 829" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB828 ,Group Status Bit 828" "Group 0,Group 1" bitfld.long 0x00 27. " GSB827 ,Group Status Bit 827" "Group 0,Group 1" bitfld.long 0x00 26. " GSB826 ,Group Status Bit 826" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB825 ,Group Status Bit 825" "Group 0,Group 1" bitfld.long 0x00 24. " GSB824 ,Group Status Bit 824" "Group 0,Group 1" bitfld.long 0x00 23. " GSB823 ,Group Status Bit 823" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB822 ,Group Status Bit 822" "Group 0,Group 1" bitfld.long 0x00 21. " GSB821 ,Group Status Bit 821" "Group 0,Group 1" bitfld.long 0x00 20. " GSB820 ,Group Status Bit 820" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB819 ,Group Status Bit 819" "Group 0,Group 1" bitfld.long 0x00 18. " GSB818 ,Group Status Bit 818" "Group 0,Group 1" bitfld.long 0x00 17. " GSB817 ,Group Status Bit 817" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB816 ,Group Status Bit 816" "Group 0,Group 1" bitfld.long 0x00 15. " GSB815 ,Group Status Bit 815" "Group 0,Group 1" bitfld.long 0x00 14. " GSB814 ,Group Status Bit 814" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB813 ,Group Status Bit 813" "Group 0,Group 1" bitfld.long 0x00 12. " GSB812 ,Group Status Bit 812" "Group 0,Group 1" bitfld.long 0x00 11. " GSB811 ,Group Status Bit 811" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB810 ,Group Status Bit 810" "Group 0,Group 1" bitfld.long 0x00 9. " GSB809 ,Group Status Bit 809" "Group 0,Group 1" bitfld.long 0x00 8. " GSB808 ,Group Status Bit 808" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB807 ,Group Status Bit 807" "Group 0,Group 1" bitfld.long 0x00 6. " GSB806 ,Group Status Bit 806" "Group 0,Group 1" bitfld.long 0x00 5. " GSB805 ,Group Status Bit 805" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB804 ,Group Status Bit 804" "Group 0,Group 1" bitfld.long 0x00 3. " GSB803 ,Group Status Bit 803" "Group 0,Group 1" bitfld.long 0x00 2. " GSB802 ,Group Status Bit 802" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB801 ,Group Status Bit 801" "Group 0,Group 1" bitfld.long 0x00 0. " GSB800 ,Group Status Bit 800" "Group 0,Group 1" else rgroup.long 0x00E4++0x03 line.long 0x0 "GICD_IGROUPR25,Interrupt Group Register 25" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x1A)&&(PER.ADDRESS.isSECUREEX(ad:0xA0021000+0x00E8)) group.long 0x00E8++0x03 line.long 0x0 "GICD_IGROUPR26,Interrupt Group Register 26 (Secure access)" bitfld.long 0x00 31. " GSB863 ,Group Status Bit 863" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 30. " GSB862 ,Group Status Bit 862" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 29. " GSB861 ,Group Status Bit 861" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 28. " GSB860 ,Group Status Bit 860" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 27. " GSB859 ,Group Status Bit 859" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 26. " GSB858 ,Group Status Bit 858" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 25. " GSB857 ,Group Status Bit 857" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 24. " GSB856 ,Group Status Bit 856" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 23. " GSB855 ,Group Status Bit 855" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 22. " GSB854 ,Group Status Bit 854" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 21. " GSB853 ,Group Status Bit 853" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 20. " GSB852 ,Group Status Bit 852" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 19. " GSB851 ,Group Status Bit 851" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 18. " GSB850 ,Group Status Bit 850" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 17. " GSB849 ,Group Status Bit 849" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 16. " GSB848 ,Group Status Bit 848" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 15. " GSB847 ,Group Status Bit 847" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 14. " GSB846 ,Group Status Bit 846" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 13. " GSB845 ,Group Status Bit 845" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 12. " GSB844 ,Group Status Bit 844" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 11. " GSB843 ,Group Status Bit 843" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 10. " GSB842 ,Group Status Bit 842" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 9. " GSB841 ,Group Status Bit 841" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 8. " GSB840 ,Group Status Bit 840" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 7. " GSB839 ,Group Status Bit 839" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 6. " GSB838 ,Group Status Bit 838" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 5. " GSB837 ,Group Status Bit 837" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 4. " GSB836 ,Group Status Bit 836" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 3. " GSB835 ,Group Status Bit 835" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 2. " GSB834 ,Group Status Bit 834" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 1. " GSB833 ,Group Status Bit 833" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 0. " GSB832 ,Group Status Bit 832" "Group 0 (Secure),Group 1 (Non-secure)" elif (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x1A) group.long 0x00E8++0x03 line.long 0x0 "GICD_IGROUPR26,Interrupt Group Register 26 (Non-secure access)" bitfld.long 0x00 31. " GSB863 ,Group Status Bit 863" "Group 0,Group 1" bitfld.long 0x00 30. " GSB862 ,Group Status Bit 862" "Group 0,Group 1" bitfld.long 0x00 29. " GSB861 ,Group Status Bit 861" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB860 ,Group Status Bit 860" "Group 0,Group 1" bitfld.long 0x00 27. " GSB859 ,Group Status Bit 859" "Group 0,Group 1" bitfld.long 0x00 26. " GSB858 ,Group Status Bit 858" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB857 ,Group Status Bit 857" "Group 0,Group 1" bitfld.long 0x00 24. " GSB856 ,Group Status Bit 856" "Group 0,Group 1" bitfld.long 0x00 23. " GSB855 ,Group Status Bit 855" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB854 ,Group Status Bit 854" "Group 0,Group 1" bitfld.long 0x00 21. " GSB853 ,Group Status Bit 853" "Group 0,Group 1" bitfld.long 0x00 20. " GSB852 ,Group Status Bit 852" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB851 ,Group Status Bit 851" "Group 0,Group 1" bitfld.long 0x00 18. " GSB850 ,Group Status Bit 850" "Group 0,Group 1" bitfld.long 0x00 17. " GSB849 ,Group Status Bit 849" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB848 ,Group Status Bit 848" "Group 0,Group 1" bitfld.long 0x00 15. " GSB847 ,Group Status Bit 847" "Group 0,Group 1" bitfld.long 0x00 14. " GSB846 ,Group Status Bit 846" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB845 ,Group Status Bit 845" "Group 0,Group 1" bitfld.long 0x00 12. " GSB844 ,Group Status Bit 844" "Group 0,Group 1" bitfld.long 0x00 11. " GSB843 ,Group Status Bit 843" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB842 ,Group Status Bit 842" "Group 0,Group 1" bitfld.long 0x00 9. " GSB841 ,Group Status Bit 841" "Group 0,Group 1" bitfld.long 0x00 8. " GSB840 ,Group Status Bit 840" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB839 ,Group Status Bit 839" "Group 0,Group 1" bitfld.long 0x00 6. " GSB838 ,Group Status Bit 838" "Group 0,Group 1" bitfld.long 0x00 5. " GSB837 ,Group Status Bit 837" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB836 ,Group Status Bit 836" "Group 0,Group 1" bitfld.long 0x00 3. " GSB835 ,Group Status Bit 835" "Group 0,Group 1" bitfld.long 0x00 2. " GSB834 ,Group Status Bit 834" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB833 ,Group Status Bit 833" "Group 0,Group 1" bitfld.long 0x00 0. " GSB832 ,Group Status Bit 832" "Group 0,Group 1" else rgroup.long 0x00E8++0x03 line.long 0x0 "GICD_IGROUPR26,Interrupt Group Register 26" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x1B)&&(PER.ADDRESS.isSECUREEX(ad:0xA0021000+0x00EC)) group.long 0x00EC++0x03 line.long 0x0 "GICD_IGROUPR27,Interrupt Group Register 27 (Secure access)" bitfld.long 0x00 31. " GSB895 ,Group Status Bit 895" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 30. " GSB894 ,Group Status Bit 894" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 29. " GSB893 ,Group Status Bit 893" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 28. " GSB892 ,Group Status Bit 892" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 27. " GSB891 ,Group Status Bit 891" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 26. " GSB890 ,Group Status Bit 890" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 25. " GSB889 ,Group Status Bit 889" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 24. " GSB888 ,Group Status Bit 888" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 23. " GSB887 ,Group Status Bit 887" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 22. " GSB886 ,Group Status Bit 886" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 21. " GSB885 ,Group Status Bit 885" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 20. " GSB884 ,Group Status Bit 884" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 19. " GSB883 ,Group Status Bit 883" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 18. " GSB882 ,Group Status Bit 882" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 17. " GSB881 ,Group Status Bit 881" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 16. " GSB880 ,Group Status Bit 880" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 15. " GSB879 ,Group Status Bit 879" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 14. " GSB878 ,Group Status Bit 878" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 13. " GSB877 ,Group Status Bit 877" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 12. " GSB876 ,Group Status Bit 876" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 11. " GSB875 ,Group Status Bit 875" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 10. " GSB874 ,Group Status Bit 874" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 9. " GSB873 ,Group Status Bit 873" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 8. " GSB872 ,Group Status Bit 872" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 7. " GSB871 ,Group Status Bit 871" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 6. " GSB870 ,Group Status Bit 870" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 5. " GSB869 ,Group Status Bit 869" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 4. " GSB868 ,Group Status Bit 868" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 3. " GSB867 ,Group Status Bit 867" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 2. " GSB866 ,Group Status Bit 866" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 1. " GSB865 ,Group Status Bit 865" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 0. " GSB864 ,Group Status Bit 864" "Group 0 (Secure),Group 1 (Non-secure)" elif (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x1B) group.long 0x00EC++0x03 line.long 0x0 "GICD_IGROUPR27,Interrupt Group Register 27 (Non-Secure access)" bitfld.long 0x00 31. " GSB895 ,Group Status Bit 895" "Group 0,Group 1" bitfld.long 0x00 30. " GSB894 ,Group Status Bit 894" "Group 0,Group 1" bitfld.long 0x00 29. " GSB893 ,Group Status Bit 893" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB892 ,Group Status Bit 892" "Group 0,Group 1" bitfld.long 0x00 27. " GSB891 ,Group Status Bit 891" "Group 0,Group 1" bitfld.long 0x00 26. " GSB890 ,Group Status Bit 890" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB889 ,Group Status Bit 889" "Group 0,Group 1" bitfld.long 0x00 24. " GSB888 ,Group Status Bit 888" "Group 0,Group 1" bitfld.long 0x00 23. " GSB887 ,Group Status Bit 887" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB886 ,Group Status Bit 886" "Group 0,Group 1" bitfld.long 0x00 21. " GSB885 ,Group Status Bit 885" "Group 0,Group 1" bitfld.long 0x00 20. " GSB884 ,Group Status Bit 884" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB883 ,Group Status Bit 883" "Group 0,Group 1" bitfld.long 0x00 18. " GSB882 ,Group Status Bit 882" "Group 0,Group 1" bitfld.long 0x00 17. " GSB881 ,Group Status Bit 881" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB880 ,Group Status Bit 880" "Group 0,Group 1" bitfld.long 0x00 15. " GSB879 ,Group Status Bit 879" "Group 0,Group 1" bitfld.long 0x00 14. " GSB878 ,Group Status Bit 878" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB877 ,Group Status Bit 877" "Group 0,Group 1" bitfld.long 0x00 12. " GSB876 ,Group Status Bit 876" "Group 0,Group 1" bitfld.long 0x00 11. " GSB875 ,Group Status Bit 875" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB874 ,Group Status Bit 874" "Group 0,Group 1" bitfld.long 0x00 9. " GSB873 ,Group Status Bit 873" "Group 0,Group 1" bitfld.long 0x00 8. " GSB872 ,Group Status Bit 872" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB871 ,Group Status Bit 871" "Group 0,Group 1" bitfld.long 0x00 6. " GSB870 ,Group Status Bit 870" "Group 0,Group 1" bitfld.long 0x00 5. " GSB869 ,Group Status Bit 869" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB868 ,Group Status Bit 868" "Group 0,Group 1" bitfld.long 0x00 3. " GSB867 ,Group Status Bit 867" "Group 0,Group 1" bitfld.long 0x00 2. " GSB866 ,Group Status Bit 866" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB865 ,Group Status Bit 865" "Group 0,Group 1" bitfld.long 0x00 0. " GSB864 ,Group Status Bit 864" "Group 0,Group 1" else rgroup.long 0x00EC++0x03 line.long 0x0 "GICD_IGROUPR27,Interrupt Group Register 27" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x1C)&&(PER.ADDRESS.isSECUREEX(ad:0xA0021000+0x00F0)) group.long 0x00F0++0x03 line.long 0x0 "GICD_IGROUPR28,Interrupt Group Register 28 (Secure access)" bitfld.long 0x00 31. " GSB927 ,Group Status Bit 927" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 30. " GSB926 ,Group Status Bit 926" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 29. " GSB925 ,Group Status Bit 925" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 28. " GSB924 ,Group Status Bit 924" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 27. " GSB923 ,Group Status Bit 923" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 26. " GSB922 ,Group Status Bit 922" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 25. " GSB921 ,Group Status Bit 921" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 24. " GSB920 ,Group Status Bit 920" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 23. " GSB919 ,Group Status Bit 919" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 22. " GSB918 ,Group Status Bit 918" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 21. " GSB917 ,Group Status Bit 917" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 20. " GSB916 ,Group Status Bit 916" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 19. " GSB915 ,Group Status Bit 915" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 18. " GSB914 ,Group Status Bit 914" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 17. " GSB913 ,Group Status Bit 913" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 16. " GSB912 ,Group Status Bit 912" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 15. " GSB911 ,Group Status Bit 911" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 14. " GSB910 ,Group Status Bit 910" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 13. " GSB909 ,Group Status Bit 909" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 12. " GSB908 ,Group Status Bit 908" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 11. " GSB907 ,Group Status Bit 907" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 10. " GSB906 ,Group Status Bit 906" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 9. " GSB905 ,Group Status Bit 905" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 8. " GSB904 ,Group Status Bit 904" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 7. " GSB903 ,Group Status Bit 903" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 6. " GSB902 ,Group Status Bit 902" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 5. " GSB901 ,Group Status Bit 901" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 4. " GSB900 ,Group Status Bit 900" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 3. " GSB899 ,Group Status Bit 899" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 2. " GSB898 ,Group Status Bit 898" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 1. " GSB897 ,Group Status Bit 897" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 0. " GSB896 ,Group Status Bit 896" "Group 0 (Secure),Group 1 (Non-secure)" elif (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x1C) group.long 0x00F0++0x03 line.long 0x0 "GICD_IGROUPR28,Interrupt Group Register 28 (Non-secure access)" bitfld.long 0x00 31. " GSB927 ,Group Status Bit 927" "Group 0,Group 1" bitfld.long 0x00 30. " GSB926 ,Group Status Bit 926" "Group 0,Group 1" bitfld.long 0x00 29. " GSB925 ,Group Status Bit 925" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB924 ,Group Status Bit 924" "Group 0,Group 1" bitfld.long 0x00 27. " GSB923 ,Group Status Bit 923" "Group 0,Group 1" bitfld.long 0x00 26. " GSB922 ,Group Status Bit 922" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB921 ,Group Status Bit 921" "Group 0,Group 1" bitfld.long 0x00 24. " GSB920 ,Group Status Bit 920" "Group 0,Group 1" bitfld.long 0x00 23. " GSB919 ,Group Status Bit 919" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB918 ,Group Status Bit 918" "Group 0,Group 1" bitfld.long 0x00 21. " GSB917 ,Group Status Bit 917" "Group 0,Group 1" bitfld.long 0x00 20. " GSB916 ,Group Status Bit 916" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB915 ,Group Status Bit 915" "Group 0,Group 1" bitfld.long 0x00 18. " GSB914 ,Group Status Bit 914" "Group 0,Group 1" bitfld.long 0x00 17. " GSB913 ,Group Status Bit 913" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB912 ,Group Status Bit 912" "Group 0,Group 1" bitfld.long 0x00 15. " GSB911 ,Group Status Bit 911" "Group 0,Group 1" bitfld.long 0x00 14. " GSB910 ,Group Status Bit 910" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB909 ,Group Status Bit 909" "Group 0,Group 1" bitfld.long 0x00 12. " GSB908 ,Group Status Bit 908" "Group 0,Group 1" bitfld.long 0x00 11. " GSB907 ,Group Status Bit 907" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB906 ,Group Status Bit 906" "Group 0,Group 1" bitfld.long 0x00 9. " GSB905 ,Group Status Bit 905" "Group 0,Group 1" bitfld.long 0x00 8. " GSB904 ,Group Status Bit 904" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB903 ,Group Status Bit 903" "Group 0,Group 1" bitfld.long 0x00 6. " GSB902 ,Group Status Bit 902" "Group 0,Group 1" bitfld.long 0x00 5. " GSB901 ,Group Status Bit 901" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB900 ,Group Status Bit 900" "Group 0,Group 1" bitfld.long 0x00 3. " GSB899 ,Group Status Bit 899" "Group 0,Group 1" bitfld.long 0x00 2. " GSB898 ,Group Status Bit 898" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB897 ,Group Status Bit 897" "Group 0,Group 1" bitfld.long 0x00 0. " GSB896 ,Group Status Bit 896" "Group 0,Group 1" else rgroup.long 0x0F0++0x03 line.long 0x0 "GICD_IGROUPR28,Interrupt Group Register 28" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x1D)&&(PER.ADDRESS.isSECUREEX(ad:0xA0021000+0x00F4)) group.long 0x00F4++0x03 line.long 0x0 "GICD_IGROUPR29,Interrupt Group Register 29 (Secure access)" bitfld.long 0x00 31. " GSB959 ,Group Status Bit 959" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 30. " GSB958 ,Group Status Bit 958" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 29. " GSB957 ,Group Status Bit 957" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 28. " GSB956 ,Group Status Bit 956" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 27. " GSB955 ,Group Status Bit 955" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 26. " GSB954 ,Group Status Bit 954" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 25. " GSB953 ,Group Status Bit 953" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 24. " GSB952 ,Group Status Bit 952" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 23. " GSB951 ,Group Status Bit 951" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 22. " GSB950 ,Group Status Bit 950" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 21. " GSB949 ,Group Status Bit 949" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 20. " GSB948 ,Group Status Bit 948" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 19. " GSB947 ,Group Status Bit 947" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 18. " GSB946 ,Group Status Bit 946" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 17. " GSB945 ,Group Status Bit 945" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 16. " GSB944 ,Group Status Bit 944" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 15. " GSB943 ,Group Status Bit 943" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 14. " GSB942 ,Group Status Bit 942" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 13. " GSB941 ,Group Status Bit 941" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 12. " GSB940 ,Group Status Bit 940" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 11. " GSB939 ,Group Status Bit 939" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 10. " GSB938 ,Group Status Bit 938" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 9. " GSB937 ,Group Status Bit 937" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 8. " GSB936 ,Group Status Bit 936" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 7. " GSB935 ,Group Status Bit 935" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 6. " GSB934 ,Group Status Bit 934" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 5. " GSB933 ,Group Status Bit 933" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 4. " GSB932 ,Group Status Bit 932" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 3. " GSB931 ,Group Status Bit 931" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 2. " GSB930 ,Group Status Bit 930" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 1. " GSB929 ,Group Status Bit 929" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 0. " GSB928 ,Group Status Bit 928" "Group 0 (Secure),Group 1 (Non-secure)" elif (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x1D) group.long 0x00F4++0x03 line.long 0x0 "GICD_IGROUPR29,Interrupt Group Register 29 (Non-secure access)" bitfld.long 0x00 31. " GSB959 ,Group Status Bit 959" "Group 0,Group 1" bitfld.long 0x00 30. " GSB958 ,Group Status Bit 958" "Group 0,Group 1" bitfld.long 0x00 29. " GSB957 ,Group Status Bit 957" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB956 ,Group Status Bit 956" "Group 0,Group 1" bitfld.long 0x00 27. " GSB955 ,Group Status Bit 955" "Group 0,Group 1" bitfld.long 0x00 26. " GSB954 ,Group Status Bit 954" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB953 ,Group Status Bit 953" "Group 0,Group 1" bitfld.long 0x00 24. " GSB952 ,Group Status Bit 952" "Group 0,Group 1" bitfld.long 0x00 23. " GSB951 ,Group Status Bit 951" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB950 ,Group Status Bit 950" "Group 0,Group 1" bitfld.long 0x00 21. " GSB949 ,Group Status Bit 949" "Group 0,Group 1" bitfld.long 0x00 20. " GSB948 ,Group Status Bit 948" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB947 ,Group Status Bit 947" "Group 0,Group 1" bitfld.long 0x00 18. " GSB946 ,Group Status Bit 946" "Group 0,Group 1" bitfld.long 0x00 17. " GSB945 ,Group Status Bit 945" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB944 ,Group Status Bit 944" "Group 0,Group 1" bitfld.long 0x00 15. " GSB943 ,Group Status Bit 943" "Group 0,Group 1" bitfld.long 0x00 14. " GSB942 ,Group Status Bit 942" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB941 ,Group Status Bit 941" "Group 0,Group 1" bitfld.long 0x00 12. " GSB940 ,Group Status Bit 940" "Group 0,Group 1" bitfld.long 0x00 11. " GSB939 ,Group Status Bit 939" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB938 ,Group Status Bit 938" "Group 0,Group 1" bitfld.long 0x00 9. " GSB937 ,Group Status Bit 937" "Group 0,Group 1" bitfld.long 0x00 8. " GSB936 ,Group Status Bit 936" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB935 ,Group Status Bit 935" "Group 0,Group 1" bitfld.long 0x00 6. " GSB934 ,Group Status Bit 934" "Group 0,Group 1" bitfld.long 0x00 5. " GSB933 ,Group Status Bit 933" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB932 ,Group Status Bit 932" "Group 0,Group 1" bitfld.long 0x00 3. " GSB931 ,Group Status Bit 931" "Group 0,Group 1" bitfld.long 0x00 2. " GSB930 ,Group Status Bit 930" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB929 ,Group Status Bit 929" "Group 0,Group 1" bitfld.long 0x00 0. " GSB928 ,Group Status Bit 928" "Group 0,Group 1" else rgroup.long 0x00F4++0x03 line.long 0x0 "GICD_IGROUPR29,Interrupt Group Register 29" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x1E)&&(PER.ADDRESS.isSECUREEX(ad:0xA0021000+0x00F8)) group.long 0x00F8++0x03 line.long 0x0 "GICD_IGROUPR30,Interrupt Group Register 30 (Secure access)" bitfld.long 0x00 31. " GSB991 ,Group Status Bit 991" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 30. " GSB990 ,Group Status Bit 990" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 29. " GSB989 ,Group Status Bit 989" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 28. " GSB988 ,Group Status Bit 988" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 27. " GSB987 ,Group Status Bit 987" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 26. " GSB986 ,Group Status Bit 986" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 25. " GSB985 ,Group Status Bit 985" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 24. " GSB984 ,Group Status Bit 984" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 23. " GSB983 ,Group Status Bit 983" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 22. " GSB982 ,Group Status Bit 982" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 21. " GSB981 ,Group Status Bit 981" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 20. " GSB980 ,Group Status Bit 980" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 19. " GSB979 ,Group Status Bit 979" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 18. " GSB978 ,Group Status Bit 978" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 17. " GSB977 ,Group Status Bit 977" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 16. " GSB976 ,Group Status Bit 976" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 15. " GSB975 ,Group Status Bit 975" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 14. " GSB974 ,Group Status Bit 974" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 13. " GSB973 ,Group Status Bit 973" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 12. " GSB972 ,Group Status Bit 972" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 11. " GSB971 ,Group Status Bit 971" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 10. " GSB970 ,Group Status Bit 970" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 9. " GSB969 ,Group Status Bit 969" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 8. " GSB968 ,Group Status Bit 968" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 7. " GSB967 ,Group Status Bit 967" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 6. " GSB966 ,Group Status Bit 966" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 5. " GSB965 ,Group Status Bit 965" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 4. " GSB964 ,Group Status Bit 964" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 3. " GSB963 ,Group Status Bit 963" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 2. " GSB962 ,Group Status Bit 962" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 1. " GSB961 ,Group Status Bit 961" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 0. " GSB960 ,Group Status Bit 960" "Group 0 (Secure),Group 1 (Non-secure)" elif (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x1E) group.long 0x00F8++0x03 line.long 0x0 "GICD_IGROUPR30,Interrupt Group Register 30 (Non-secure access)" bitfld.long 0x00 31. " GSB991 ,Group Status Bit 991" "Group 0,Group 1" bitfld.long 0x00 30. " GSB990 ,Group Status Bit 990" "Group 0,Group 1" bitfld.long 0x00 29. " GSB989 ,Group Status Bit 989" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB988 ,Group Status Bit 988" "Group 0,Group 1" bitfld.long 0x00 27. " GSB987 ,Group Status Bit 987" "Group 0,Group 1" bitfld.long 0x00 26. " GSB986 ,Group Status Bit 986" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB985 ,Group Status Bit 985" "Group 0,Group 1" bitfld.long 0x00 24. " GSB984 ,Group Status Bit 984" "Group 0,Group 1" bitfld.long 0x00 23. " GSB983 ,Group Status Bit 983" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB982 ,Group Status Bit 982" "Group 0,Group 1" bitfld.long 0x00 21. " GSB981 ,Group Status Bit 981" "Group 0,Group 1" bitfld.long 0x00 20. " GSB980 ,Group Status Bit 980" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB979 ,Group Status Bit 979" "Group 0,Group 1" bitfld.long 0x00 18. " GSB978 ,Group Status Bit 978" "Group 0,Group 1" bitfld.long 0x00 17. " GSB977 ,Group Status Bit 977" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB976 ,Group Status Bit 976" "Group 0,Group 1" bitfld.long 0x00 15. " GSB975 ,Group Status Bit 975" "Group 0,Group 1" bitfld.long 0x00 14. " GSB974 ,Group Status Bit 974" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB973 ,Group Status Bit 973" "Group 0,Group 1" bitfld.long 0x00 12. " GSB972 ,Group Status Bit 972" "Group 0,Group 1" bitfld.long 0x00 11. " GSB971 ,Group Status Bit 971" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB970 ,Group Status Bit 970" "Group 0,Group 1" bitfld.long 0x00 9. " GSB969 ,Group Status Bit 969" "Group 0,Group 1" bitfld.long 0x00 8. " GSB968 ,Group Status Bit 968" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB967 ,Group Status Bit 967" "Group 0,Group 1" bitfld.long 0x00 6. " GSB966 ,Group Status Bit 966" "Group 0,Group 1" bitfld.long 0x00 5. " GSB965 ,Group Status Bit 965" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB964 ,Group Status Bit 964" "Group 0,Group 1" bitfld.long 0x00 3. " GSB963 ,Group Status Bit 963" "Group 0,Group 1" bitfld.long 0x00 2. " GSB962 ,Group Status Bit 962" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB961 ,Group Status Bit 961" "Group 0,Group 1" bitfld.long 0x00 0. " GSB960 ,Group Status Bit 960" "Group 0,Group 1" else rgroup.long 0x00F8++0x03 line.long 0x0 "GICD_IGROUPR30,Interrupt Group Register 30" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0xA0021000+0x04))&0x0000001F)==0x1F)&&(PER.ADDRESS.isSECUREEX(ad:0xA0021000+0x00FC)) group.long 0x00FC++0x03 line.long 0x0 "GICD_IGROUPR31,Interrupt Group Register 31 (Secure access)" bitfld.long 0x00 27. " GSB1019 ,Group Status Bit 1019" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 26. " GSB1018 ,Group Status Bit 1018" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 25. " GSB1017 ,Group Status Bit 1017" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 24. " GSB1016 ,Group Status Bit 1016" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 23. " GSB1015 ,Group Status Bit 1015" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 22. " GSB1014 ,Group Status Bit 1014" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 21. " GSB1013 ,Group Status Bit 1013" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 20. " GSB1012 ,Group Status Bit 1012" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 19. " GSB1011 ,Group Status Bit 1011" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 18. " GSB1010 ,Group Status Bit 1010" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 17. " GSB1009 ,Group Status Bit 1009" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 16. " GSB1008 ,Group Status Bit 1008" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 15. " GSB1007 ,Group Status Bit 1007" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 14. " GSB1006 ,Group Status Bit 1006" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 13. " GSB1005 ,Group Status Bit 1005" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 12. " GSB1004 ,Group Status Bit 1004" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 11. " GSB1003 ,Group Status Bit 1003" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 10. " GSB1002 ,Group Status Bit 1002" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 9. " GSB1001 ,Group Status Bit 1001" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 8. " GSB1000 ,Group Status Bit 1000" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 7. " GSB999 ,Group Status Bit 999" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 6. " GSB998 ,Group Status Bit 998" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 5. " GSB997 ,Group Status Bit 997" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 4. " GSB996 ,Group Status Bit 996" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 3. " GSB995 ,Group Status Bit 995" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 2. " GSB994 ,Group Status Bit 994" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 1. " GSB993 ,Group Status Bit 993" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 0. " GSB992 ,Group Status Bit 992" "Group 0 (Secure),Group 1 (Non-secure)" elif (((per.l(ad:0xA0021000+0x04))&0x0000001F)==0x1F) group.long 0x00FC++0x03 line.long 0x0 "GICD_IGROUPR31,Interrupt Group Register 31 (Non-secure access)" bitfld.long 0x00 27. " GSB1019 ,Group Status Bit 1019" "Group 0,Group 1" bitfld.long 0x00 26. " GSB1018 ,Group Status Bit 1018" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB1017 ,Group Status Bit 1017" "Group 0,Group 1" bitfld.long 0x00 24. " GSB1016 ,Group Status Bit 1016" "Group 0,Group 1" bitfld.long 0x00 23. " GSB1015 ,Group Status Bit 1015" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB1014 ,Group Status Bit 1014" "Group 0,Group 1" bitfld.long 0x00 21. " GSB1013 ,Group Status Bit 1013" "Group 0,Group 1" bitfld.long 0x00 20. " GSB1012 ,Group Status Bit 1012" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB1011 ,Group Status Bit 1011" "Group 0,Group 1" bitfld.long 0x00 18. " GSB1010 ,Group Status Bit 1010" "Group 0,Group 1" bitfld.long 0x00 17. " GSB1009 ,Group Status Bit 1009" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB1008 ,Group Status Bit 1008" "Group 0,Group 1" bitfld.long 0x00 15. " GSB1007 ,Group Status Bit 1007" "Group 0,Group 1" bitfld.long 0x00 14. " GSB1006 ,Group Status Bit 1006" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB1005 ,Group Status Bit 1005" "Group 0,Group 1" bitfld.long 0x00 12. " GSB1004 ,Group Status Bit 1004" "Group 0,Group 1" bitfld.long 0x00 11. " GSB1003 ,Group Status Bit 1003" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB1002 ,Group Status Bit 1002" "Group 0,Group 1" bitfld.long 0x00 9. " GSB1001 ,Group Status Bit 1001" "Group 0,Group 1" bitfld.long 0x00 8. " GSB1000 ,Group Status Bit 1000" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB999 ,Group Status Bit 999" "Group 0,Group 1" bitfld.long 0x00 6. " GSB998 ,Group Status Bit 998" "Group 0,Group 1" bitfld.long 0x00 5. " GSB997 ,Group Status Bit 997" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB996 ,Group Status Bit 996" "Group 0,Group 1" bitfld.long 0x00 3. " GSB995 ,Group Status Bit 995" "Group 0,Group 1" bitfld.long 0x00 2. " GSB994 ,Group Status Bit 994" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB993 ,Group Status Bit 993" "Group 0,Group 1" bitfld.long 0x00 0. " GSB992 ,Group Status Bit 992" "Group 0,Group 1" else rgroup.long 0x00FC++0x03 line.long 0x0 "GICD_IGROUPR31,Interrupt Group Register 31" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif tree.end endif width 24. tree "Set/Clear Enable Registers" group.long 0x0100++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER0,Interrupt Set/Clear Enable Register 0" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB31 ,Set/Clear Enable Bit 31" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB30 ,Set/Clear Enable Bit 30" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB29 ,Set/Clear Enable Bit 29" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB28 ,Set/Clear Enable Bit 28" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB27 ,Set/Clear Enable Bit 27" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB26 ,Set/Clear Enable Bit 26" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB25 ,Set/Clear Enable Bit 25" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB24 ,Set/Clear Enable Bit 24" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB23 ,Set/Clear Enable Bit 23" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB22 ,Set/Clear Enable Bit 22" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB21 ,Set/Clear Enable Bit 21" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB20 ,Set/Clear Enable Bit 20" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB19 ,Set/Clear Enable Bit 19" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB18 ,Set/Clear Enable Bit 18" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB17 ,Set/Clear Enable Bit 17" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB16 ,Set/Clear Enable Bit 16" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB15 ,Set/Clear Enable Bit 15" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB14 ,Set/Clear Enable Bit 14" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB13 ,Set/Clear Enable Bit 13" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB12 ,Set/Clear Enable Bit 12" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB11 ,Set/Clear Enable Bit 11" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB10 ,Set/Clear Enable Bit 10" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB9 ,Set/Clear Enable Bit 9" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB8 ,Set/Clear Enable Bit 8" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB7 ,Set/Clear Enable Bit 7" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB6 ,Set/Clear Enable Bit 6" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB5 ,Set/Clear Enable Bit 5" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB4 ,Set/Clear Enable Bit 4" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB3 ,Set/Clear Enable Bit 3" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB2 ,Set/Clear Enable Bit 2" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB1 ,Set/Clear Enable Bit 1" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB0 ,Set/Clear Enable Bit 0" "Disabled,Enabled" if (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x01) group.long 0x0104++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER1,Interrupt Set/Clear Enable Register 1" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB63 ,Set/Clear Enable Bit 63" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB62 ,Set/Clear Enable Bit 62" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB61 ,Set/Clear Enable Bit 61" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB60 ,Set/Clear Enable Bit 60" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB59 ,Set/Clear Enable Bit 59" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB58 ,Set/Clear Enable Bit 58" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB57 ,Set/Clear Enable Bit 57" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB56 ,Set/Clear Enable Bit 56" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB55 ,Set/Clear Enable Bit 55" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB54 ,Set/Clear Enable Bit 54" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB53 ,Set/Clear Enable Bit 53" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB52 ,Set/Clear Enable Bit 52" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB51 ,Set/Clear Enable Bit 51" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB50 ,Set/Clear Enable Bit 50" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB49 ,Set/Clear Enable Bit 49" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB48 ,Set/Clear Enable Bit 48" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB47 ,Set/Clear Enable Bit 47" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB46 ,Set/Clear Enable Bit 46" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB45 ,Set/Clear Enable Bit 45" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB44 ,Set/Clear Enable Bit 44" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB43 ,Set/Clear Enable Bit 43" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB42 ,Set/Clear Enable Bit 42" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB41 ,Set/Clear Enable Bit 41" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB40 ,Set/Clear Enable Bit 40" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB39 ,Set/Clear Enable Bit 39" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB38 ,Set/Clear Enable Bit 38" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB37 ,Set/Clear Enable Bit 37" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB36 ,Set/Clear Enable Bit 36" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB35 ,Set/Clear Enable Bit 35" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB34 ,Set/Clear Enable Bit 34" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB33 ,Set/Clear Enable Bit 33" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB32 ,Set/Clear Enable Bit 32" "Disabled,Enabled" else rgroup.long 0x0104++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER1,Interrupt Set/Clear Enable Register 1" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x02) group.long 0x0108++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER2,Interrupt Set/Clear Enable Register 2" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB95 ,Set/Clear Enable Bit 95" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB94 ,Set/Clear Enable Bit 94" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB93 ,Set/Clear Enable Bit 93" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB92 ,Set/Clear Enable Bit 92" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB91 ,Set/Clear Enable Bit 91" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB90 ,Set/Clear Enable Bit 90" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB89 ,Set/Clear Enable Bit 89" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB88 ,Set/Clear Enable Bit 88" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB87 ,Set/Clear Enable Bit 87" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB86 ,Set/Clear Enable Bit 86" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB85 ,Set/Clear Enable Bit 85" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB84 ,Set/Clear Enable Bit 84" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB83 ,Set/Clear Enable Bit 83" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB82 ,Set/Clear Enable Bit 82" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB81 ,Set/Clear Enable Bit 81" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB80 ,Set/Clear Enable Bit 80" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB79 ,Set/Clear Enable Bit 79" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB78 ,Set/Clear Enable Bit 78" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB77 ,Set/Clear Enable Bit 77" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB76 ,Set/Clear Enable Bit 76" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB75 ,Set/Clear Enable Bit 75" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB74 ,Set/Clear Enable Bit 74" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB73 ,Set/Clear Enable Bit 73" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB72 ,Set/Clear Enable Bit 72" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB71 ,Set/Clear Enable Bit 71" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB70 ,Set/Clear Enable Bit 70" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB69 ,Set/Clear Enable Bit 69" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB68 ,Set/Clear Enable Bit 68" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB67 ,Set/Clear Enable Bit 67" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB66 ,Set/Clear Enable Bit 66" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB65 ,Set/Clear Enable Bit 65" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB64 ,Set/Clear Enable Bit 64" "Disabled,Enabled" else rgroup.long 0x0108++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER2,Interrupt Set/Clear Enable Register 2" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x03) group.long 0x010C++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER3,Interrupt Set/Clear Enable Register 3" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB127 ,Set/Clear Enable Bit 127" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB126 ,Set/Clear Enable Bit 126" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB125 ,Set/Clear Enable Bit 125" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB124 ,Set/Clear Enable Bit 124" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB123 ,Set/Clear Enable Bit 123" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB122 ,Set/Clear Enable Bit 122" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB121 ,Set/Clear Enable Bit 121" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB120 ,Set/Clear Enable Bit 120" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB119 ,Set/Clear Enable Bit 119" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB118 ,Set/Clear Enable Bit 118" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB117 ,Set/Clear Enable Bit 117" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB116 ,Set/Clear Enable Bit 116" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB115 ,Set/Clear Enable Bit 115" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB114 ,Set/Clear Enable Bit 114" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB113 ,Set/Clear Enable Bit 113" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB112 ,Set/Clear Enable Bit 112" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB111 ,Set/Clear Enable Bit 111" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB110 ,Set/Clear Enable Bit 110" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB109 ,Set/Clear Enable Bit 109" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB108 ,Set/Clear Enable Bit 108" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB107 ,Set/Clear Enable Bit 107" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB106 ,Set/Clear Enable Bit 106" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB105 ,Set/Clear Enable Bit 105" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB104 ,Set/Clear Enable Bit 104" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB103 ,Set/Clear Enable Bit 103" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB102 ,Set/Clear Enable Bit 102" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB101 ,Set/Clear Enable Bit 101" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB100 ,Set/Clear Enable Bit 100" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB99 ,Set/Clear Enable Bit 99" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB98 ,Set/Clear Enable Bit 98" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB97 ,Set/Clear Enable Bit 97" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB96 ,Set/Clear Enable Bit 96" "Disabled,Enabled" else rgroup.long 0x010C++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER3,Interrupt Set/Clear Enable Register 3" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x04) group.long 0x0110++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER4,Interrupt Set/Clear Enable Register 4" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB159 ,Set/Clear Enable Bit 159" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB158 ,Set/Clear Enable Bit 158" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB157 ,Set/Clear Enable Bit 157" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB156 ,Set/Clear Enable Bit 156" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB155 ,Set/Clear Enable Bit 155" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB154 ,Set/Clear Enable Bit 154" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB153 ,Set/Clear Enable Bit 153" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB152 ,Set/Clear Enable Bit 152" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB151 ,Set/Clear Enable Bit 151" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB150 ,Set/Clear Enable Bit 150" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB149 ,Set/Clear Enable Bit 149" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB148 ,Set/Clear Enable Bit 148" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB147 ,Set/Clear Enable Bit 147" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB146 ,Set/Clear Enable Bit 146" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB145 ,Set/Clear Enable Bit 145" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB144 ,Set/Clear Enable Bit 144" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB143 ,Set/Clear Enable Bit 143" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB142 ,Set/Clear Enable Bit 142" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB141 ,Set/Clear Enable Bit 141" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB140 ,Set/Clear Enable Bit 140" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB139 ,Set/Clear Enable Bit 139" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB138 ,Set/Clear Enable Bit 138" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB137 ,Set/Clear Enable Bit 137" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB136 ,Set/Clear Enable Bit 136" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB135 ,Set/Clear Enable Bit 135" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB134 ,Set/Clear Enable Bit 134" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB133 ,Set/Clear Enable Bit 133" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB132 ,Set/Clear Enable Bit 132" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB131 ,Set/Clear Enable Bit 131" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB130 ,Set/Clear Enable Bit 130" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB129 ,Set/Clear Enable Bit 129" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB128 ,Set/Clear Enable Bit 128" "Disabled,Enabled" else rgroup.long 0x0110++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER4,Interrupt Set/Clear Enable Register 4" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x05) group.long 0x0114++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER5,Interrupt Set/Clear Enable Register 5" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB191 ,Set/Clear Enable Bit 191" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB190 ,Set/Clear Enable Bit 190" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB189 ,Set/Clear Enable Bit 189" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB188 ,Set/Clear Enable Bit 188" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB187 ,Set/Clear Enable Bit 187" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB186 ,Set/Clear Enable Bit 186" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB185 ,Set/Clear Enable Bit 185" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB184 ,Set/Clear Enable Bit 184" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB183 ,Set/Clear Enable Bit 183" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB182 ,Set/Clear Enable Bit 182" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB181 ,Set/Clear Enable Bit 181" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB180 ,Set/Clear Enable Bit 180" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB179 ,Set/Clear Enable Bit 179" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB178 ,Set/Clear Enable Bit 178" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB177 ,Set/Clear Enable Bit 177" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB176 ,Set/Clear Enable Bit 176" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB175 ,Set/Clear Enable Bit 175" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB174 ,Set/Clear Enable Bit 174" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB173 ,Set/Clear Enable Bit 173" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB172 ,Set/Clear Enable Bit 172" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB171 ,Set/Clear Enable Bit 171" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB170 ,Set/Clear Enable Bit 170" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB169 ,Set/Clear Enable Bit 169" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB168 ,Set/Clear Enable Bit 168" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB167 ,Set/Clear Enable Bit 167" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB166 ,Set/Clear Enable Bit 166" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB165 ,Set/Clear Enable Bit 165" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB164 ,Set/Clear Enable Bit 164" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB163 ,Set/Clear Enable Bit 163" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB162 ,Set/Clear Enable Bit 162" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB161 ,Set/Clear Enable Bit 161" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB160 ,Set/Clear Enable Bit 160" "Disabled,Enabled" else rgroup.long 0x0114++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER5,Interrupt Set/Clear Enable Register 5" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x06) group.long 0x0118++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER6,Interrupt Set/Clear Enable Register 6" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB223 ,Set/Clear Enable Bit 223" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB222 ,Set/Clear Enable Bit 222" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB221 ,Set/Clear Enable Bit 221" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB220 ,Set/Clear Enable Bit 220" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB219 ,Set/Clear Enable Bit 219" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB218 ,Set/Clear Enable Bit 218" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB217 ,Set/Clear Enable Bit 217" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB216 ,Set/Clear Enable Bit 216" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB215 ,Set/Clear Enable Bit 215" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB214 ,Set/Clear Enable Bit 214" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB213 ,Set/Clear Enable Bit 213" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB212 ,Set/Clear Enable Bit 212" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB211 ,Set/Clear Enable Bit 211" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB210 ,Set/Clear Enable Bit 210" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB209 ,Set/Clear Enable Bit 209" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB208 ,Set/Clear Enable Bit 208" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB207 ,Set/Clear Enable Bit 207" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB206 ,Set/Clear Enable Bit 206" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB205 ,Set/Clear Enable Bit 205" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB204 ,Set/Clear Enable Bit 204" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB203 ,Set/Clear Enable Bit 203" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB202 ,Set/Clear Enable Bit 202" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB201 ,Set/Clear Enable Bit 201" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB200 ,Set/Clear Enable Bit 200" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB199 ,Set/Clear Enable Bit 199" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB198 ,Set/Clear Enable Bit 198" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB197 ,Set/Clear Enable Bit 197" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB196 ,Set/Clear Enable Bit 196" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB195 ,Set/Clear Enable Bit 195" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB194 ,Set/Clear Enable Bit 194" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB193 ,Set/Clear Enable Bit 193" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB192 ,Set/Clear Enable Bit 192" "Disabled,Enabled" else rgroup.long 0x0118++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER6,Interrupt Set/Clear Enable Register 6" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x07) group.long 0x011C++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER7,Interrupt Set/Clear Enable Register 7" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB255 ,Set/Clear Enable Bit 255" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB254 ,Set/Clear Enable Bit 254" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB253 ,Set/Clear Enable Bit 253" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB252 ,Set/Clear Enable Bit 252" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB251 ,Set/Clear Enable Bit 251" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB250 ,Set/Clear Enable Bit 250" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB249 ,Set/Clear Enable Bit 249" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB248 ,Set/Clear Enable Bit 248" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB247 ,Set/Clear Enable Bit 247" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB246 ,Set/Clear Enable Bit 246" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB245 ,Set/Clear Enable Bit 245" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB244 ,Set/Clear Enable Bit 244" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB243 ,Set/Clear Enable Bit 243" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB242 ,Set/Clear Enable Bit 242" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB241 ,Set/Clear Enable Bit 241" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB240 ,Set/Clear Enable Bit 240" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB239 ,Set/Clear Enable Bit 239" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB238 ,Set/Clear Enable Bit 238" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB237 ,Set/Clear Enable Bit 237" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB236 ,Set/Clear Enable Bit 236" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB235 ,Set/Clear Enable Bit 235" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB234 ,Set/Clear Enable Bit 234" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB233 ,Set/Clear Enable Bit 233" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB232 ,Set/Clear Enable Bit 232" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB231 ,Set/Clear Enable Bit 231" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB230 ,Set/Clear Enable Bit 230" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB229 ,Set/Clear Enable Bit 229" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB228 ,Set/Clear Enable Bit 228" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB227 ,Set/Clear Enable Bit 227" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB226 ,Set/Clear Enable Bit 226" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB225 ,Set/Clear Enable Bit 225" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB224 ,Set/Clear Enable Bit 224" "Disabled,Enabled" else rgroup.long 0x011C++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER7,Interrupt Set/Clear Enable Register 7" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x08) group.long 0x0120++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER8,Interrupt Set/Clear Enable Register 8" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB287 ,Set/Clear Enable Bit 287" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB286 ,Set/Clear Enable Bit 286" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB285 ,Set/Clear Enable Bit 285" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB284 ,Set/Clear Enable Bit 284" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB283 ,Set/Clear Enable Bit 283" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB282 ,Set/Clear Enable Bit 282" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB281 ,Set/Clear Enable Bit 281" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB280 ,Set/Clear Enable Bit 280" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB279 ,Set/Clear Enable Bit 279" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB278 ,Set/Clear Enable Bit 278" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB277 ,Set/Clear Enable Bit 277" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB276 ,Set/Clear Enable Bit 276" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB275 ,Set/Clear Enable Bit 275" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB274 ,Set/Clear Enable Bit 274" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB273 ,Set/Clear Enable Bit 273" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB272 ,Set/Clear Enable Bit 272" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB271 ,Set/Clear Enable Bit 271" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB270 ,Set/Clear Enable Bit 270" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB269 ,Set/Clear Enable Bit 269" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB268 ,Set/Clear Enable Bit 268" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB267 ,Set/Clear Enable Bit 267" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB266 ,Set/Clear Enable Bit 266" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB265 ,Set/Clear Enable Bit 265" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB264 ,Set/Clear Enable Bit 264" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB263 ,Set/Clear Enable Bit 263" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB262 ,Set/Clear Enable Bit 262" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB261 ,Set/Clear Enable Bit 261" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB260 ,Set/Clear Enable Bit 260" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB259 ,Set/Clear Enable Bit 259" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB258 ,Set/Clear Enable Bit 258" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB257 ,Set/Clear Enable Bit 257" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB256 ,Set/Clear Enable Bit 256" "Disabled,Enabled" else rgroup.long 0x0120++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER8,Interrupt Set/Clear Enable Register 8" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x09) group.long 0x0124++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER9,Interrupt Set/Clear Enable Register 9" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB319 ,Set/Clear Enable Bit 319" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB318 ,Set/Clear Enable Bit 318" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB317 ,Set/Clear Enable Bit 317" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB316 ,Set/Clear Enable Bit 316" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB315 ,Set/Clear Enable Bit 315" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB314 ,Set/Clear Enable Bit 314" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB313 ,Set/Clear Enable Bit 313" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB312 ,Set/Clear Enable Bit 312" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB311 ,Set/Clear Enable Bit 311" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB310 ,Set/Clear Enable Bit 310" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB309 ,Set/Clear Enable Bit 309" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB308 ,Set/Clear Enable Bit 308" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB307 ,Set/Clear Enable Bit 307" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB306 ,Set/Clear Enable Bit 306" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB305 ,Set/Clear Enable Bit 305" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB304 ,Set/Clear Enable Bit 304" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB303 ,Set/Clear Enable Bit 303" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB302 ,Set/Clear Enable Bit 302" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB301 ,Set/Clear Enable Bit 301" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB300 ,Set/Clear Enable Bit 300" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB299 ,Set/Clear Enable Bit 299" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB298 ,Set/Clear Enable Bit 298" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB297 ,Set/Clear Enable Bit 297" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB296 ,Set/Clear Enable Bit 296" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB295 ,Set/Clear Enable Bit 295" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB294 ,Set/Clear Enable Bit 294" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB293 ,Set/Clear Enable Bit 293" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB292 ,Set/Clear Enable Bit 292" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB291 ,Set/Clear Enable Bit 291" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB290 ,Set/Clear Enable Bit 290" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB289 ,Set/Clear Enable Bit 289" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB288 ,Set/Clear Enable Bit 288" "Disabled,Enabled" else rgroup.long 0x0124++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER9,Interrupt Set/Clear Enable Register 9" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x0A) group.long 0x0128++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER10,Interrupt Set/Clear Enable Register 10" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB351 ,Set/Clear Enable Bit 351" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB350 ,Set/Clear Enable Bit 350" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB349 ,Set/Clear Enable Bit 349" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB348 ,Set/Clear Enable Bit 348" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB347 ,Set/Clear Enable Bit 347" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB346 ,Set/Clear Enable Bit 346" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB345 ,Set/Clear Enable Bit 345" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB344 ,Set/Clear Enable Bit 344" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB343 ,Set/Clear Enable Bit 343" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB342 ,Set/Clear Enable Bit 342" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB341 ,Set/Clear Enable Bit 341" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB340 ,Set/Clear Enable Bit 340" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB339 ,Set/Clear Enable Bit 339" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB338 ,Set/Clear Enable Bit 338" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB337 ,Set/Clear Enable Bit 337" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB336 ,Set/Clear Enable Bit 336" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB335 ,Set/Clear Enable Bit 335" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB334 ,Set/Clear Enable Bit 334" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB333 ,Set/Clear Enable Bit 333" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB332 ,Set/Clear Enable Bit 332" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB331 ,Set/Clear Enable Bit 331" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB330 ,Set/Clear Enable Bit 330" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB329 ,Set/Clear Enable Bit 329" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB328 ,Set/Clear Enable Bit 328" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB327 ,Set/Clear Enable Bit 327" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB326 ,Set/Clear Enable Bit 326" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB325 ,Set/Clear Enable Bit 325" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB324 ,Set/Clear Enable Bit 324" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB323 ,Set/Clear Enable Bit 323" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB322 ,Set/Clear Enable Bit 322" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB321 ,Set/Clear Enable Bit 321" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB320 ,Set/Clear Enable Bit 320" "Disabled,Enabled" else rgroup.long 0x0128++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER10,Interrupt Set/Clear Enable Register 10" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x0B) group.long 0x012C++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER11,Interrupt Set/Clear Enable Register 11" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB383 ,Set/Clear Enable Bit 383" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB382 ,Set/Clear Enable Bit 382" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB381 ,Set/Clear Enable Bit 381" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB380 ,Set/Clear Enable Bit 380" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB379 ,Set/Clear Enable Bit 379" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB378 ,Set/Clear Enable Bit 378" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB377 ,Set/Clear Enable Bit 377" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB376 ,Set/Clear Enable Bit 376" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB375 ,Set/Clear Enable Bit 375" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB374 ,Set/Clear Enable Bit 374" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB373 ,Set/Clear Enable Bit 373" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB372 ,Set/Clear Enable Bit 372" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB371 ,Set/Clear Enable Bit 371" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB370 ,Set/Clear Enable Bit 370" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB369 ,Set/Clear Enable Bit 369" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB368 ,Set/Clear Enable Bit 368" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB367 ,Set/Clear Enable Bit 367" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB366 ,Set/Clear Enable Bit 366" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB365 ,Set/Clear Enable Bit 365" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB364 ,Set/Clear Enable Bit 364" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB363 ,Set/Clear Enable Bit 363" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB362 ,Set/Clear Enable Bit 362" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB361 ,Set/Clear Enable Bit 361" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB360 ,Set/Clear Enable Bit 360" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB359 ,Set/Clear Enable Bit 359" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB358 ,Set/Clear Enable Bit 358" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB357 ,Set/Clear Enable Bit 357" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB356 ,Set/Clear Enable Bit 356" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB355 ,Set/Clear Enable Bit 355" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB354 ,Set/Clear Enable Bit 354" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB353 ,Set/Clear Enable Bit 353" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB352 ,Set/Clear Enable Bit 352" "Disabled,Enabled" else rgroup.long 0x012C++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER11,Interrupt Set/Clear Enable Register 11" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x0C) group.long 0x0130++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER12,Interrupt Set/Clear Enable Register 12" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB415 ,Set/Clear Enable Bit 415" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB414 ,Set/Clear Enable Bit 414" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB413 ,Set/Clear Enable Bit 413" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB412 ,Set/Clear Enable Bit 412" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB411 ,Set/Clear Enable Bit 411" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB410 ,Set/Clear Enable Bit 410" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB409 ,Set/Clear Enable Bit 409" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB408 ,Set/Clear Enable Bit 408" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB407 ,Set/Clear Enable Bit 407" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB406 ,Set/Clear Enable Bit 406" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB405 ,Set/Clear Enable Bit 405" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB404 ,Set/Clear Enable Bit 404" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB403 ,Set/Clear Enable Bit 403" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB402 ,Set/Clear Enable Bit 402" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB401 ,Set/Clear Enable Bit 401" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB400 ,Set/Clear Enable Bit 400" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB399 ,Set/Clear Enable Bit 399" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB398 ,Set/Clear Enable Bit 398" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB397 ,Set/Clear Enable Bit 397" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB396 ,Set/Clear Enable Bit 396" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB395 ,Set/Clear Enable Bit 395" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB394 ,Set/Clear Enable Bit 394" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB393 ,Set/Clear Enable Bit 393" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB392 ,Set/Clear Enable Bit 392" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB391 ,Set/Clear Enable Bit 391" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB390 ,Set/Clear Enable Bit 390" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB389 ,Set/Clear Enable Bit 389" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB388 ,Set/Clear Enable Bit 388" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB387 ,Set/Clear Enable Bit 387" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB386 ,Set/Clear Enable Bit 386" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB385 ,Set/Clear Enable Bit 385" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB384 ,Set/Clear Enable Bit 384" "Disabled,Enabled" else rgroup.long 0x0130++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER12,Interrupt Set/Clear Enable Register 12" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x0D) group.long 0x0134++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER13,Interrupt Set/Clear Enable Register 13" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB447 ,Set/Clear Enable Bit 447" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB446 ,Set/Clear Enable Bit 446" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB445 ,Set/Clear Enable Bit 445" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB444 ,Set/Clear Enable Bit 444" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB443 ,Set/Clear Enable Bit 443" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB442 ,Set/Clear Enable Bit 442" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB441 ,Set/Clear Enable Bit 441" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB440 ,Set/Clear Enable Bit 440" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB439 ,Set/Clear Enable Bit 439" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB438 ,Set/Clear Enable Bit 438" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB437 ,Set/Clear Enable Bit 437" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB436 ,Set/Clear Enable Bit 436" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB435 ,Set/Clear Enable Bit 435" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB434 ,Set/Clear Enable Bit 434" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB433 ,Set/Clear Enable Bit 433" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB432 ,Set/Clear Enable Bit 432" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB431 ,Set/Clear Enable Bit 431" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB430 ,Set/Clear Enable Bit 430" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB429 ,Set/Clear Enable Bit 429" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB428 ,Set/Clear Enable Bit 428" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB427 ,Set/Clear Enable Bit 427" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB426 ,Set/Clear Enable Bit 426" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB425 ,Set/Clear Enable Bit 425" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB424 ,Set/Clear Enable Bit 424" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB423 ,Set/Clear Enable Bit 423" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB422 ,Set/Clear Enable Bit 422" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB421 ,Set/Clear Enable Bit 421" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB420 ,Set/Clear Enable Bit 420" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB419 ,Set/Clear Enable Bit 419" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB418 ,Set/Clear Enable Bit 418" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB417 ,Set/Clear Enable Bit 417" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB416 ,Set/Clear Enable Bit 416" "Disabled,Enabled" else rgroup.long 0x0134++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER13,Interrupt Set/Clear Enable Register 13" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x0E) group.long 0x0138++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER14,Interrupt Set/Clear Enable Register 14" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB479 ,Set/Clear Enable Bit 479" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB478 ,Set/Clear Enable Bit 478" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB477 ,Set/Clear Enable Bit 477" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB476 ,Set/Clear Enable Bit 476" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB475 ,Set/Clear Enable Bit 475" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB474 ,Set/Clear Enable Bit 474" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB473 ,Set/Clear Enable Bit 473" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB472 ,Set/Clear Enable Bit 472" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB471 ,Set/Clear Enable Bit 471" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB470 ,Set/Clear Enable Bit 470" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB469 ,Set/Clear Enable Bit 469" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB468 ,Set/Clear Enable Bit 468" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB467 ,Set/Clear Enable Bit 467" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB466 ,Set/Clear Enable Bit 466" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB465 ,Set/Clear Enable Bit 465" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB464 ,Set/Clear Enable Bit 464" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB463 ,Set/Clear Enable Bit 463" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB462 ,Set/Clear Enable Bit 462" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB461 ,Set/Clear Enable Bit 461" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB460 ,Set/Clear Enable Bit 460" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB459 ,Set/Clear Enable Bit 459" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB458 ,Set/Clear Enable Bit 458" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB457 ,Set/Clear Enable Bit 457" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB456 ,Set/Clear Enable Bit 456" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB455 ,Set/Clear Enable Bit 455" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB454 ,Set/Clear Enable Bit 454" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB453 ,Set/Clear Enable Bit 453" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB452 ,Set/Clear Enable Bit 452" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB451 ,Set/Clear Enable Bit 451" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB450 ,Set/Clear Enable Bit 450" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB449 ,Set/Clear Enable Bit 449" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB448 ,Set/Clear Enable Bit 448" "Disabled,Enabled" else rgroup.long 0x0138++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER14,Interrupt Set/Clear Enable Register 14" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x0F) group.long 0x013C++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER15,Interrupt Set/Clear Enable Register 15" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB511 ,Set/Clear Enable Bit 511" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB510 ,Set/Clear Enable Bit 510" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB509 ,Set/Clear Enable Bit 509" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB508 ,Set/Clear Enable Bit 508" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB507 ,Set/Clear Enable Bit 507" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB506 ,Set/Clear Enable Bit 506" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB505 ,Set/Clear Enable Bit 505" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB504 ,Set/Clear Enable Bit 504" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB503 ,Set/Clear Enable Bit 503" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB502 ,Set/Clear Enable Bit 502" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB501 ,Set/Clear Enable Bit 501" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB500 ,Set/Clear Enable Bit 500" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB499 ,Set/Clear Enable Bit 499" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB498 ,Set/Clear Enable Bit 498" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB497 ,Set/Clear Enable Bit 497" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB496 ,Set/Clear Enable Bit 496" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB495 ,Set/Clear Enable Bit 495" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB494 ,Set/Clear Enable Bit 494" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB493 ,Set/Clear Enable Bit 493" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB492 ,Set/Clear Enable Bit 492" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB491 ,Set/Clear Enable Bit 491" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB490 ,Set/Clear Enable Bit 490" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB489 ,Set/Clear Enable Bit 489" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB488 ,Set/Clear Enable Bit 488" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB487 ,Set/Clear Enable Bit 487" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB486 ,Set/Clear Enable Bit 486" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB485 ,Set/Clear Enable Bit 485" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB484 ,Set/Clear Enable Bit 484" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB483 ,Set/Clear Enable Bit 483" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB482 ,Set/Clear Enable Bit 482" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB481 ,Set/Clear Enable Bit 481" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB480 ,Set/Clear Enable Bit 480" "Disabled,Enabled" else rgroup.long 0x013C++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER15,Interrupt Set/Clear Enable Register 15" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x10) group.long 0x0140++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER16,Interrupt Set/Clear Enable Register 16" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB543 ,Set/Clear Enable Bit 543" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB542 ,Set/Clear Enable Bit 542" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB541 ,Set/Clear Enable Bit 541" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB540 ,Set/Clear Enable Bit 540" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB539 ,Set/Clear Enable Bit 539" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB538 ,Set/Clear Enable Bit 538" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB537 ,Set/Clear Enable Bit 537" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB536 ,Set/Clear Enable Bit 536" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB535 ,Set/Clear Enable Bit 535" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB534 ,Set/Clear Enable Bit 534" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB533 ,Set/Clear Enable Bit 533" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB532 ,Set/Clear Enable Bit 532" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB531 ,Set/Clear Enable Bit 531" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB530 ,Set/Clear Enable Bit 530" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB529 ,Set/Clear Enable Bit 529" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB528 ,Set/Clear Enable Bit 528" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB527 ,Set/Clear Enable Bit 527" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB526 ,Set/Clear Enable Bit 526" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB525 ,Set/Clear Enable Bit 525" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB524 ,Set/Clear Enable Bit 524" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB523 ,Set/Clear Enable Bit 523" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB522 ,Set/Clear Enable Bit 522" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB521 ,Set/Clear Enable Bit 521" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB520 ,Set/Clear Enable Bit 520" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB519 ,Set/Clear Enable Bit 519" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB518 ,Set/Clear Enable Bit 518" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB517 ,Set/Clear Enable Bit 517" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB516 ,Set/Clear Enable Bit 516" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB515 ,Set/Clear Enable Bit 515" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB514 ,Set/Clear Enable Bit 514" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB513 ,Set/Clear Enable Bit 513" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB512 ,Set/Clear Enable Bit 512" "Disabled,Enabled" else rgroup.long 0x0140++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER16,Interrupt Set/Clear Enable Register 16" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x11) group.long 0x0144++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER17,Interrupt Set/Clear Enable Register 17" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB575 ,Set/Clear Enable Bit 575" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB574 ,Set/Clear Enable Bit 574" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB573 ,Set/Clear Enable Bit 573" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB572 ,Set/Clear Enable Bit 572" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB571 ,Set/Clear Enable Bit 571" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB570 ,Set/Clear Enable Bit 570" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB569 ,Set/Clear Enable Bit 569" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB568 ,Set/Clear Enable Bit 568" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB567 ,Set/Clear Enable Bit 567" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB566 ,Set/Clear Enable Bit 566" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB565 ,Set/Clear Enable Bit 565" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB564 ,Set/Clear Enable Bit 564" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB563 ,Set/Clear Enable Bit 563" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB562 ,Set/Clear Enable Bit 562" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB561 ,Set/Clear Enable Bit 561" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB560 ,Set/Clear Enable Bit 560" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB559 ,Set/Clear Enable Bit 559" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB558 ,Set/Clear Enable Bit 558" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB557 ,Set/Clear Enable Bit 557" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB556 ,Set/Clear Enable Bit 556" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB555 ,Set/Clear Enable Bit 555" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB554 ,Set/Clear Enable Bit 554" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB553 ,Set/Clear Enable Bit 553" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB552 ,Set/Clear Enable Bit 552" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB551 ,Set/Clear Enable Bit 551" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB550 ,Set/Clear Enable Bit 550" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB549 ,Set/Clear Enable Bit 549" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB548 ,Set/Clear Enable Bit 548" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB547 ,Set/Clear Enable Bit 547" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB546 ,Set/Clear Enable Bit 546" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB545 ,Set/Clear Enable Bit 545" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB544 ,Set/Clear Enable Bit 544" "Disabled,Enabled" else rgroup.long 0x0144++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER17,Interrupt Set/Clear Enable Register 17" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x12) group.long 0x0148++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER18,Interrupt Set/Clear Enable Register 18" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB607 ,Set/Clear Enable Bit 607" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB606 ,Set/Clear Enable Bit 606" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB605 ,Set/Clear Enable Bit 605" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB604 ,Set/Clear Enable Bit 604" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB603 ,Set/Clear Enable Bit 603" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB602 ,Set/Clear Enable Bit 602" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB601 ,Set/Clear Enable Bit 601" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB600 ,Set/Clear Enable Bit 600" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB599 ,Set/Clear Enable Bit 599" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB598 ,Set/Clear Enable Bit 598" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB597 ,Set/Clear Enable Bit 597" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB596 ,Set/Clear Enable Bit 596" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB595 ,Set/Clear Enable Bit 595" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB594 ,Set/Clear Enable Bit 594" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB593 ,Set/Clear Enable Bit 593" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB592 ,Set/Clear Enable Bit 592" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB591 ,Set/Clear Enable Bit 591" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB590 ,Set/Clear Enable Bit 590" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB589 ,Set/Clear Enable Bit 589" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB588 ,Set/Clear Enable Bit 588" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB587 ,Set/Clear Enable Bit 587" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB586 ,Set/Clear Enable Bit 586" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB585 ,Set/Clear Enable Bit 585" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB584 ,Set/Clear Enable Bit 584" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB583 ,Set/Clear Enable Bit 583" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB582 ,Set/Clear Enable Bit 582" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB581 ,Set/Clear Enable Bit 581" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB580 ,Set/Clear Enable Bit 580" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB579 ,Set/Clear Enable Bit 579" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB578 ,Set/Clear Enable Bit 578" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB577 ,Set/Clear Enable Bit 577" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB576 ,Set/Clear Enable Bit 576" "Disabled,Enabled" else rgroup.long 0x0148++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER18,Interrupt Set/Clear Enable Register 18" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x13) group.long 0x014C++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER19,Interrupt Set/Clear Enable Register 19" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB639 ,Set/Clear Enable Bit 639" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB638 ,Set/Clear Enable Bit 638" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB637 ,Set/Clear Enable Bit 637" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB636 ,Set/Clear Enable Bit 636" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB635 ,Set/Clear Enable Bit 635" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB634 ,Set/Clear Enable Bit 634" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB633 ,Set/Clear Enable Bit 633" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB632 ,Set/Clear Enable Bit 632" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB631 ,Set/Clear Enable Bit 631" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB630 ,Set/Clear Enable Bit 630" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB629 ,Set/Clear Enable Bit 629" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB628 ,Set/Clear Enable Bit 628" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB627 ,Set/Clear Enable Bit 627" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB626 ,Set/Clear Enable Bit 626" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB625 ,Set/Clear Enable Bit 625" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB624 ,Set/Clear Enable Bit 624" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB623 ,Set/Clear Enable Bit 623" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB622 ,Set/Clear Enable Bit 622" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB621 ,Set/Clear Enable Bit 621" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB620 ,Set/Clear Enable Bit 620" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB619 ,Set/Clear Enable Bit 619" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB618 ,Set/Clear Enable Bit 618" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB617 ,Set/Clear Enable Bit 617" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB616 ,Set/Clear Enable Bit 616" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB615 ,Set/Clear Enable Bit 615" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB614 ,Set/Clear Enable Bit 614" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB613 ,Set/Clear Enable Bit 613" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB612 ,Set/Clear Enable Bit 612" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB611 ,Set/Clear Enable Bit 611" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB610 ,Set/Clear Enable Bit 610" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB609 ,Set/Clear Enable Bit 609" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB608 ,Set/Clear Enable Bit 608" "Disabled,Enabled" else rgroup.long 0x014C++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER19,Interrupt Set/Clear Enable Register 19" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x14) group.long 0x0150++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER20,Interrupt Set/Clear Enable Register 20" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB671 ,Set/Clear Enable Bit 671" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB670 ,Set/Clear Enable Bit 670" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB669 ,Set/Clear Enable Bit 669" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB668 ,Set/Clear Enable Bit 668" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB667 ,Set/Clear Enable Bit 667" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB666 ,Set/Clear Enable Bit 666" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB665 ,Set/Clear Enable Bit 665" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB664 ,Set/Clear Enable Bit 664" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB663 ,Set/Clear Enable Bit 663" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB662 ,Set/Clear Enable Bit 662" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB661 ,Set/Clear Enable Bit 661" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB660 ,Set/Clear Enable Bit 660" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB659 ,Set/Clear Enable Bit 659" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB658 ,Set/Clear Enable Bit 658" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB657 ,Set/Clear Enable Bit 657" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB656 ,Set/Clear Enable Bit 656" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB655 ,Set/Clear Enable Bit 655" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB654 ,Set/Clear Enable Bit 654" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB653 ,Set/Clear Enable Bit 653" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB652 ,Set/Clear Enable Bit 652" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB651 ,Set/Clear Enable Bit 651" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB650 ,Set/Clear Enable Bit 650" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB649 ,Set/Clear Enable Bit 649" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB648 ,Set/Clear Enable Bit 648" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB647 ,Set/Clear Enable Bit 647" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB646 ,Set/Clear Enable Bit 646" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB645 ,Set/Clear Enable Bit 645" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB644 ,Set/Clear Enable Bit 644" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB643 ,Set/Clear Enable Bit 643" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB642 ,Set/Clear Enable Bit 642" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB641 ,Set/Clear Enable Bit 641" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB640 ,Set/Clear Enable Bit 640" "Disabled,Enabled" else rgroup.long 0x0150++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER20,Interrupt Set/Clear Enable Register 20" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x15) group.long 0x0154++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER21,Interrupt Set/Clear Enable Register 21" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB703 ,Set/Clear Enable Bit 703" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB702 ,Set/Clear Enable Bit 702" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB701 ,Set/Clear Enable Bit 701" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB700 ,Set/Clear Enable Bit 700" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB699 ,Set/Clear Enable Bit 699" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB698 ,Set/Clear Enable Bit 698" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB697 ,Set/Clear Enable Bit 697" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB696 ,Set/Clear Enable Bit 696" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB695 ,Set/Clear Enable Bit 695" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB694 ,Set/Clear Enable Bit 694" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB693 ,Set/Clear Enable Bit 693" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB692 ,Set/Clear Enable Bit 692" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB691 ,Set/Clear Enable Bit 691" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB690 ,Set/Clear Enable Bit 690" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB689 ,Set/Clear Enable Bit 689" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB688 ,Set/Clear Enable Bit 688" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB687 ,Set/Clear Enable Bit 687" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB686 ,Set/Clear Enable Bit 686" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB685 ,Set/Clear Enable Bit 685" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB684 ,Set/Clear Enable Bit 684" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB683 ,Set/Clear Enable Bit 683" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB682 ,Set/Clear Enable Bit 682" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB681 ,Set/Clear Enable Bit 681" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB680 ,Set/Clear Enable Bit 680" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB679 ,Set/Clear Enable Bit 679" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB678 ,Set/Clear Enable Bit 678" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB677 ,Set/Clear Enable Bit 677" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB676 ,Set/Clear Enable Bit 676" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB675 ,Set/Clear Enable Bit 675" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB674 ,Set/Clear Enable Bit 674" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB673 ,Set/Clear Enable Bit 673" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB672 ,Set/Clear Enable Bit 672" "Disabled,Enabled" else rgroup.long 0x0154++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER21,Interrupt Set/Clear Enable Register 21" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x16) group.long 0x0158++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER22,Interrupt Set/Clear Enable Register 22" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB735 ,Set/Clear Enable Bit 735" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB734 ,Set/Clear Enable Bit 734" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB733 ,Set/Clear Enable Bit 733" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB732 ,Set/Clear Enable Bit 732" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB731 ,Set/Clear Enable Bit 731" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB730 ,Set/Clear Enable Bit 730" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB729 ,Set/Clear Enable Bit 729" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB728 ,Set/Clear Enable Bit 728" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB727 ,Set/Clear Enable Bit 727" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB726 ,Set/Clear Enable Bit 726" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB725 ,Set/Clear Enable Bit 725" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB724 ,Set/Clear Enable Bit 724" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB723 ,Set/Clear Enable Bit 723" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB722 ,Set/Clear Enable Bit 722" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB721 ,Set/Clear Enable Bit 721" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB720 ,Set/Clear Enable Bit 720" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB719 ,Set/Clear Enable Bit 719" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB718 ,Set/Clear Enable Bit 718" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB717 ,Set/Clear Enable Bit 717" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB716 ,Set/Clear Enable Bit 716" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB715 ,Set/Clear Enable Bit 715" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB714 ,Set/Clear Enable Bit 714" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB713 ,Set/Clear Enable Bit 713" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB712 ,Set/Clear Enable Bit 712" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB711 ,Set/Clear Enable Bit 711" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB710 ,Set/Clear Enable Bit 710" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB709 ,Set/Clear Enable Bit 709" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB708 ,Set/Clear Enable Bit 708" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB707 ,Set/Clear Enable Bit 707" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB706 ,Set/Clear Enable Bit 706" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB705 ,Set/Clear Enable Bit 705" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB704 ,Set/Clear Enable Bit 704" "Disabled,Enabled" else rgroup.long 0x0158++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER22,Interrupt Set/Clear Enable Register 22" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x17) group.long 0x015C++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER23,Interrupt Set/Clear Enable Register 23" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB767 ,Set/Clear Enable Bit 767" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB766 ,Set/Clear Enable Bit 766" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB765 ,Set/Clear Enable Bit 765" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB764 ,Set/Clear Enable Bit 764" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB763 ,Set/Clear Enable Bit 763" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB762 ,Set/Clear Enable Bit 762" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB761 ,Set/Clear Enable Bit 761" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB760 ,Set/Clear Enable Bit 760" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB759 ,Set/Clear Enable Bit 759" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB758 ,Set/Clear Enable Bit 758" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB757 ,Set/Clear Enable Bit 757" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB756 ,Set/Clear Enable Bit 756" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB755 ,Set/Clear Enable Bit 755" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB754 ,Set/Clear Enable Bit 754" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB753 ,Set/Clear Enable Bit 753" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB752 ,Set/Clear Enable Bit 752" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB751 ,Set/Clear Enable Bit 751" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB750 ,Set/Clear Enable Bit 750" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB749 ,Set/Clear Enable Bit 749" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB748 ,Set/Clear Enable Bit 748" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB747 ,Set/Clear Enable Bit 747" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB746 ,Set/Clear Enable Bit 746" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB745 ,Set/Clear Enable Bit 745" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB744 ,Set/Clear Enable Bit 744" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB743 ,Set/Clear Enable Bit 743" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB742 ,Set/Clear Enable Bit 742" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB741 ,Set/Clear Enable Bit 741" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB740 ,Set/Clear Enable Bit 740" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB739 ,Set/Clear Enable Bit 739" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB738 ,Set/Clear Enable Bit 738" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB737 ,Set/Clear Enable Bit 737" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB736 ,Set/Clear Enable Bit 736" "Disabled,Enabled" else rgroup.long 0x015C++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER23,Interrupt Set/Clear Enable Register 23" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x18) group.long 0x0160++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER24,Interrupt Set/Clear Enable Register 24" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB799 ,Set/Clear Enable Bit 799" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB798 ,Set/Clear Enable Bit 798" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB797 ,Set/Clear Enable Bit 797" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB796 ,Set/Clear Enable Bit 796" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB795 ,Set/Clear Enable Bit 795" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB794 ,Set/Clear Enable Bit 794" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB793 ,Set/Clear Enable Bit 793" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB792 ,Set/Clear Enable Bit 792" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB791 ,Set/Clear Enable Bit 791" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB790 ,Set/Clear Enable Bit 790" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB789 ,Set/Clear Enable Bit 789" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB788 ,Set/Clear Enable Bit 788" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB787 ,Set/Clear Enable Bit 787" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB786 ,Set/Clear Enable Bit 786" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB785 ,Set/Clear Enable Bit 785" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB784 ,Set/Clear Enable Bit 784" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB783 ,Set/Clear Enable Bit 783" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB782 ,Set/Clear Enable Bit 782" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB781 ,Set/Clear Enable Bit 781" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB780 ,Set/Clear Enable Bit 780" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB779 ,Set/Clear Enable Bit 779" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB778 ,Set/Clear Enable Bit 778" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB777 ,Set/Clear Enable Bit 777" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB776 ,Set/Clear Enable Bit 776" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB775 ,Set/Clear Enable Bit 775" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB774 ,Set/Clear Enable Bit 774" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB773 ,Set/Clear Enable Bit 773" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB772 ,Set/Clear Enable Bit 772" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB771 ,Set/Clear Enable Bit 771" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB770 ,Set/Clear Enable Bit 770" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB769 ,Set/Clear Enable Bit 769" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB768 ,Set/Clear Enable Bit 768" "Disabled,Enabled" else rgroup.long 0x0160++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER24,Interrupt Set/Clear Enable Register 24" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x19) group.long 0x0164++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER25,Interrupt Set/Clear Enable Register 25" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB831 ,Set/Clear Enable Bit 831" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB830 ,Set/Clear Enable Bit 830" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB829 ,Set/Clear Enable Bit 829" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB828 ,Set/Clear Enable Bit 828" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB827 ,Set/Clear Enable Bit 827" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB826 ,Set/Clear Enable Bit 826" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB825 ,Set/Clear Enable Bit 825" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB824 ,Set/Clear Enable Bit 824" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB823 ,Set/Clear Enable Bit 823" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB822 ,Set/Clear Enable Bit 822" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB821 ,Set/Clear Enable Bit 821" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB820 ,Set/Clear Enable Bit 820" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB819 ,Set/Clear Enable Bit 819" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB818 ,Set/Clear Enable Bit 818" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB817 ,Set/Clear Enable Bit 817" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB816 ,Set/Clear Enable Bit 816" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB815 ,Set/Clear Enable Bit 815" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB814 ,Set/Clear Enable Bit 814" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB813 ,Set/Clear Enable Bit 813" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB812 ,Set/Clear Enable Bit 812" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB811 ,Set/Clear Enable Bit 811" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB810 ,Set/Clear Enable Bit 810" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB809 ,Set/Clear Enable Bit 809" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB808 ,Set/Clear Enable Bit 808" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB807 ,Set/Clear Enable Bit 807" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB806 ,Set/Clear Enable Bit 806" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB805 ,Set/Clear Enable Bit 805" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB804 ,Set/Clear Enable Bit 804" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB803 ,Set/Clear Enable Bit 803" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB802 ,Set/Clear Enable Bit 802" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB801 ,Set/Clear Enable Bit 801" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB800 ,Set/Clear Enable Bit 800" "Disabled,Enabled" else rgroup.long 0x0164++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER25,Interrupt Set/Clear Enable Register 25" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x1A) group.long 0x0168++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER26,Interrupt Set/Clear Enable Register 26" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB863 ,Set/Clear Enable Bit 863" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB862 ,Set/Clear Enable Bit 862" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB861 ,Set/Clear Enable Bit 861" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB860 ,Set/Clear Enable Bit 860" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB859 ,Set/Clear Enable Bit 859" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB858 ,Set/Clear Enable Bit 858" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB857 ,Set/Clear Enable Bit 857" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB856 ,Set/Clear Enable Bit 856" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB855 ,Set/Clear Enable Bit 855" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB854 ,Set/Clear Enable Bit 854" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB853 ,Set/Clear Enable Bit 853" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB852 ,Set/Clear Enable Bit 852" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB851 ,Set/Clear Enable Bit 851" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB850 ,Set/Clear Enable Bit 850" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB849 ,Set/Clear Enable Bit 849" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB848 ,Set/Clear Enable Bit 848" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB847 ,Set/Clear Enable Bit 847" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB846 ,Set/Clear Enable Bit 846" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB845 ,Set/Clear Enable Bit 845" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB844 ,Set/Clear Enable Bit 844" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB843 ,Set/Clear Enable Bit 843" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB842 ,Set/Clear Enable Bit 842" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB841 ,Set/Clear Enable Bit 841" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB840 ,Set/Clear Enable Bit 840" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB839 ,Set/Clear Enable Bit 839" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB838 ,Set/Clear Enable Bit 838" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB837 ,Set/Clear Enable Bit 837" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB836 ,Set/Clear Enable Bit 836" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB835 ,Set/Clear Enable Bit 835" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB834 ,Set/Clear Enable Bit 834" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB833 ,Set/Clear Enable Bit 833" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB832 ,Set/Clear Enable Bit 832" "Disabled,Enabled" else rgroup.long 0x0168++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER26,Interrupt Set/Clear Enable Register 26" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x1B) group.long 0x016C++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER27,Interrupt Set/Clear Enable Register 27" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB895 ,Set/Clear Enable Bit 895" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB894 ,Set/Clear Enable Bit 894" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB893 ,Set/Clear Enable Bit 893" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB892 ,Set/Clear Enable Bit 892" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB891 ,Set/Clear Enable Bit 891" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB890 ,Set/Clear Enable Bit 890" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB889 ,Set/Clear Enable Bit 889" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB888 ,Set/Clear Enable Bit 888" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB887 ,Set/Clear Enable Bit 887" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB886 ,Set/Clear Enable Bit 886" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB885 ,Set/Clear Enable Bit 885" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB884 ,Set/Clear Enable Bit 884" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB883 ,Set/Clear Enable Bit 883" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB882 ,Set/Clear Enable Bit 882" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB881 ,Set/Clear Enable Bit 881" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB880 ,Set/Clear Enable Bit 880" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB879 ,Set/Clear Enable Bit 879" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB878 ,Set/Clear Enable Bit 878" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB877 ,Set/Clear Enable Bit 877" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB876 ,Set/Clear Enable Bit 876" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB875 ,Set/Clear Enable Bit 875" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB874 ,Set/Clear Enable Bit 874" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB873 ,Set/Clear Enable Bit 873" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB872 ,Set/Clear Enable Bit 872" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB871 ,Set/Clear Enable Bit 871" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB870 ,Set/Clear Enable Bit 870" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB869 ,Set/Clear Enable Bit 869" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB868 ,Set/Clear Enable Bit 868" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB867 ,Set/Clear Enable Bit 867" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB866 ,Set/Clear Enable Bit 866" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB865 ,Set/Clear Enable Bit 865" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB864 ,Set/Clear Enable Bit 864" "Disabled,Enabled" else rgroup.long 0x016C++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER27,Interrupt Set/Clear Enable Register 27" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x1C) group.long 0x0170++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER28,Interrupt Set/Clear Enable Register 28" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB927 ,Set/Clear Enable Bit 927" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB926 ,Set/Clear Enable Bit 926" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB925 ,Set/Clear Enable Bit 925" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB924 ,Set/Clear Enable Bit 924" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB923 ,Set/Clear Enable Bit 923" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB922 ,Set/Clear Enable Bit 922" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB921 ,Set/Clear Enable Bit 921" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB920 ,Set/Clear Enable Bit 920" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB919 ,Set/Clear Enable Bit 919" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB918 ,Set/Clear Enable Bit 918" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB917 ,Set/Clear Enable Bit 917" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB916 ,Set/Clear Enable Bit 916" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB915 ,Set/Clear Enable Bit 915" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB914 ,Set/Clear Enable Bit 914" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB913 ,Set/Clear Enable Bit 913" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB912 ,Set/Clear Enable Bit 912" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB911 ,Set/Clear Enable Bit 911" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB910 ,Set/Clear Enable Bit 910" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB909 ,Set/Clear Enable Bit 909" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB908 ,Set/Clear Enable Bit 908" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB907 ,Set/Clear Enable Bit 907" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB906 ,Set/Clear Enable Bit 906" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB905 ,Set/Clear Enable Bit 905" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB904 ,Set/Clear Enable Bit 904" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB903 ,Set/Clear Enable Bit 903" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB902 ,Set/Clear Enable Bit 902" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB901 ,Set/Clear Enable Bit 901" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB900 ,Set/Clear Enable Bit 900" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB899 ,Set/Clear Enable Bit 899" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB898 ,Set/Clear Enable Bit 898" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB897 ,Set/Clear Enable Bit 897" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB896 ,Set/Clear Enable Bit 896" "Disabled,Enabled" else rgroup.long 0x0170++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER28,Interrupt Set/Clear Enable Register 28" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x1D) group.long 0x0174++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER29,Interrupt Set/Clear Enable Register 29" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB959 ,Set/Clear Enable Bit 959" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB958 ,Set/Clear Enable Bit 958" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB957 ,Set/Clear Enable Bit 957" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB956 ,Set/Clear Enable Bit 956" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB955 ,Set/Clear Enable Bit 955" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB954 ,Set/Clear Enable Bit 954" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB953 ,Set/Clear Enable Bit 953" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB952 ,Set/Clear Enable Bit 952" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB951 ,Set/Clear Enable Bit 951" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB950 ,Set/Clear Enable Bit 950" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB949 ,Set/Clear Enable Bit 949" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB948 ,Set/Clear Enable Bit 948" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB947 ,Set/Clear Enable Bit 947" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB946 ,Set/Clear Enable Bit 946" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB945 ,Set/Clear Enable Bit 945" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB944 ,Set/Clear Enable Bit 944" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB943 ,Set/Clear Enable Bit 943" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB942 ,Set/Clear Enable Bit 942" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB941 ,Set/Clear Enable Bit 941" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB940 ,Set/Clear Enable Bit 940" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB939 ,Set/Clear Enable Bit 939" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB938 ,Set/Clear Enable Bit 938" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB937 ,Set/Clear Enable Bit 937" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB936 ,Set/Clear Enable Bit 936" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB935 ,Set/Clear Enable Bit 935" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB934 ,Set/Clear Enable Bit 934" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB933 ,Set/Clear Enable Bit 933" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB932 ,Set/Clear Enable Bit 932" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB931 ,Set/Clear Enable Bit 931" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB930 ,Set/Clear Enable Bit 930" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB929 ,Set/Clear Enable Bit 929" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB928 ,Set/Clear Enable Bit 928" "Disabled,Enabled" else rgroup.long 0x0174++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER29,Interrupt Set/Clear Enable Register 29" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x1E) group.long 0x0178++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER30,Interrupt Set/Clear Enable Register 30" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB991 ,Set/Clear Enable Bit 991" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB990 ,Set/Clear Enable Bit 990" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB989 ,Set/Clear Enable Bit 989" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB988 ,Set/Clear Enable Bit 988" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB987 ,Set/Clear Enable Bit 987" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB986 ,Set/Clear Enable Bit 986" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB985 ,Set/Clear Enable Bit 985" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB984 ,Set/Clear Enable Bit 984" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB983 ,Set/Clear Enable Bit 983" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB982 ,Set/Clear Enable Bit 982" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB981 ,Set/Clear Enable Bit 981" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB980 ,Set/Clear Enable Bit 980" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB979 ,Set/Clear Enable Bit 979" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB978 ,Set/Clear Enable Bit 978" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB977 ,Set/Clear Enable Bit 977" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB976 ,Set/Clear Enable Bit 976" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB975 ,Set/Clear Enable Bit 975" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB974 ,Set/Clear Enable Bit 974" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB973 ,Set/Clear Enable Bit 973" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB972 ,Set/Clear Enable Bit 972" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB971 ,Set/Clear Enable Bit 971" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB970 ,Set/Clear Enable Bit 970" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB969 ,Set/Clear Enable Bit 969" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB968 ,Set/Clear Enable Bit 968" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB967 ,Set/Clear Enable Bit 967" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB966 ,Set/Clear Enable Bit 966" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB965 ,Set/Clear Enable Bit 965" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB964 ,Set/Clear Enable Bit 964" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB963 ,Set/Clear Enable Bit 963" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB962 ,Set/Clear Enable Bit 962" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB961 ,Set/Clear Enable Bit 961" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB960 ,Set/Clear Enable Bit 960" "Disabled,Enabled" else rgroup.long 0x0178++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER30,Interrupt Set/Clear Enable Register 30" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0xA0021000+0x04))&0x0000001F)==0x1F) group.long 0x017C++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER31,Interrupt Set/Clear Enable Register 31" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB1019 ,Set/Clear Enable Bit 1019" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB1018 ,Set/Clear Enable Bit 1018" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB1017 ,Set/Clear Enable Bit 1017" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB1016 ,Set/Clear Enable Bit 1016" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB1015 ,Set/Clear Enable Bit 1015" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB1014 ,Set/Clear Enable Bit 1014" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB1013 ,Set/Clear Enable Bit 1013" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB1012 ,Set/Clear Enable Bit 1012" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB1011 ,Set/Clear Enable Bit 1011" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB1010 ,Set/Clear Enable Bit 1010" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB1009 ,Set/Clear Enable Bit 1009" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB1008 ,Set/Clear Enable Bit 1008" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB1007 ,Set/Clear Enable Bit 1007" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB1006 ,Set/Clear Enable Bit 1006" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB1005 ,Set/Clear Enable Bit 1005" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB1004 ,Set/Clear Enable Bit 1004" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB1003 ,Set/Clear Enable Bit 1003" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB1002 ,Set/Clear Enable Bit 1002" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB1001 ,Set/Clear Enable Bit 1001" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB1000 ,Set/Clear Enable Bit 1000" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB999 ,Set/Clear Enable Bit 999" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB998 ,Set/Clear Enable Bit 998" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB997 ,Set/Clear Enable Bit 997" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB996 ,Set/Clear Enable Bit 996" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB995 ,Set/Clear Enable Bit 995" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB994 ,Set/Clear Enable Bit 994" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB993 ,Set/Clear Enable Bit 993" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB992 ,Set/Clear Enable Bit 992" "Disabled,Enabled" else rgroup.long 0x017C++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER31,Interrupt Set/Clear Enable Register 31" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif tree.end width 22. tree "Set/Clear Pending Registers" group.long 0x0200++0x03 line.long 0x0 "GICD_SET/CLR_PENDR0,Interrupt Set/Clear Pending Register 0" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND31 ,Set/Clear Pending Bit 31" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND30 ,Set/Clear Pending Bit 30" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND29 ,Set/Clear Pending Bit 29" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND28 ,Set/Clear Pending Bit 28" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND27 ,Set/Clear Pending Bit 27" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND26 ,Set/Clear Pending Bit 26" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND25 ,Set/Clear Pending Bit 25" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND24 ,Set/Clear Pending Bit 24" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND23 ,Set/Clear Pending Bit 23" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND22 ,Set/Clear Pending Bit 22" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND21 ,Set/Clear Pending Bit 21" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND20 ,Set/Clear Pending Bit 20" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND19 ,Set/Clear Pending Bit 19" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND18 ,Set/Clear Pending Bit 18" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND17 ,Set/Clear Pending Bit 17" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND16 ,Set/Clear Pending Bit 16" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND15 ,Set/Clear Pending Bit 15" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND14 ,Set/Clear Pending Bit 14" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND13 ,Set/Clear Pending Bit 13" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND12 ,Set/Clear Pending Bit 12" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND11 ,Set/Clear Pending Bit 11" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND10 ,Set/Clear Pending Bit 10" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND9 ,Set/Clear Pending Bit 9" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND8 ,Set/Clear Pending Bit 8" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND7 ,Set/Clear Pending Bit 7" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND6 ,Set/Clear Pending Bit 6" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND5 ,Set/Clear Pending Bit 5" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND4 ,Set/Clear Pending Bit 4" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND3 ,Set/Clear Pending Bit 3" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND2 ,Set/Clear Pending Bit 2" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND1 ,Set/Clear Pending Bit 1" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND0 ,Set/Clear Pending Bit 0" "Not pending,Pending" if (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x01) group.long 0x0204++0x03 line.long 0x0 "GICD_SET/CLR_PENDR1,Interrupt Set/Clear Pending Register 1" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND63 ,Set/Clear Pending Bit 63" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND62 ,Set/Clear Pending Bit 62" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND61 ,Set/Clear Pending Bit 61" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND60 ,Set/Clear Pending Bit 60" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND59 ,Set/Clear Pending Bit 59" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND58 ,Set/Clear Pending Bit 58" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND57 ,Set/Clear Pending Bit 57" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND56 ,Set/Clear Pending Bit 56" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND55 ,Set/Clear Pending Bit 55" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND54 ,Set/Clear Pending Bit 54" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND53 ,Set/Clear Pending Bit 53" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND52 ,Set/Clear Pending Bit 52" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND51 ,Set/Clear Pending Bit 51" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND50 ,Set/Clear Pending Bit 50" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND49 ,Set/Clear Pending Bit 49" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND48 ,Set/Clear Pending Bit 48" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND47 ,Set/Clear Pending Bit 47" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND46 ,Set/Clear Pending Bit 46" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND45 ,Set/Clear Pending Bit 45" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND44 ,Set/Clear Pending Bit 44" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND43 ,Set/Clear Pending Bit 43" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND42 ,Set/Clear Pending Bit 42" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND41 ,Set/Clear Pending Bit 41" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND40 ,Set/Clear Pending Bit 40" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND39 ,Set/Clear Pending Bit 39" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND38 ,Set/Clear Pending Bit 38" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND37 ,Set/Clear Pending Bit 37" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND36 ,Set/Clear Pending Bit 36" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND35 ,Set/Clear Pending Bit 35" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND34 ,Set/Clear Pending Bit 34" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND33 ,Set/Clear Pending Bit 33" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND32 ,Set/Clear Pending Bit 32" "Not pending,Pending" else rgroup.long 0x0204++0x03 line.long 0x0 "GICD_SET/CLR_PENDR1,Interrupt Set/Clear Pending Register 1" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x02) group.long 0x0208++0x03 line.long 0x0 "GICD_SET/CLR_PENDR2,Interrupt Set/Clear Pending Register 2" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND95 ,Set/Clear Pending Bit 95" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND94 ,Set/Clear Pending Bit 94" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND93 ,Set/Clear Pending Bit 93" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND92 ,Set/Clear Pending Bit 92" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND91 ,Set/Clear Pending Bit 91" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND90 ,Set/Clear Pending Bit 90" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND89 ,Set/Clear Pending Bit 89" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND88 ,Set/Clear Pending Bit 88" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND87 ,Set/Clear Pending Bit 87" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND86 ,Set/Clear Pending Bit 86" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND85 ,Set/Clear Pending Bit 85" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND84 ,Set/Clear Pending Bit 84" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND83 ,Set/Clear Pending Bit 83" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND82 ,Set/Clear Pending Bit 82" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND81 ,Set/Clear Pending Bit 81" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND80 ,Set/Clear Pending Bit 80" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND79 ,Set/Clear Pending Bit 79" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND78 ,Set/Clear Pending Bit 78" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND77 ,Set/Clear Pending Bit 77" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND76 ,Set/Clear Pending Bit 76" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND75 ,Set/Clear Pending Bit 75" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND74 ,Set/Clear Pending Bit 74" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND73 ,Set/Clear Pending Bit 73" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND72 ,Set/Clear Pending Bit 72" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND71 ,Set/Clear Pending Bit 71" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND70 ,Set/Clear Pending Bit 70" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND69 ,Set/Clear Pending Bit 69" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND68 ,Set/Clear Pending Bit 68" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND67 ,Set/Clear Pending Bit 67" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND66 ,Set/Clear Pending Bit 66" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND65 ,Set/Clear Pending Bit 65" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND64 ,Set/Clear Pending Bit 64" "Not pending,Pending" else rgroup.long 0x0208++0x03 line.long 0x0 "GICD_SET/CLR_PENDR2,Interrupt Set/Clear Pending Register 2" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x03) group.long 0x020C++0x03 line.long 0x0 "GICD_SET/CLR_PENDR3,Interrupt Set/Clear Pending Register 3" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND127 ,Set/Clear Pending Bit 127" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND126 ,Set/Clear Pending Bit 126" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND125 ,Set/Clear Pending Bit 125" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND124 ,Set/Clear Pending Bit 124" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND123 ,Set/Clear Pending Bit 123" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND122 ,Set/Clear Pending Bit 122" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND121 ,Set/Clear Pending Bit 121" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND120 ,Set/Clear Pending Bit 120" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND119 ,Set/Clear Pending Bit 119" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND118 ,Set/Clear Pending Bit 118" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND117 ,Set/Clear Pending Bit 117" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND116 ,Set/Clear Pending Bit 116" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND115 ,Set/Clear Pending Bit 115" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND114 ,Set/Clear Pending Bit 114" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND113 ,Set/Clear Pending Bit 113" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND112 ,Set/Clear Pending Bit 112" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND111 ,Set/Clear Pending Bit 111" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND110 ,Set/Clear Pending Bit 110" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND109 ,Set/Clear Pending Bit 109" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND108 ,Set/Clear Pending Bit 108" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND107 ,Set/Clear Pending Bit 107" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND106 ,Set/Clear Pending Bit 106" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND105 ,Set/Clear Pending Bit 105" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND104 ,Set/Clear Pending Bit 104" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND103 ,Set/Clear Pending Bit 103" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND102 ,Set/Clear Pending Bit 102" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND101 ,Set/Clear Pending Bit 101" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND100 ,Set/Clear Pending Bit 100" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND99 ,Set/Clear Pending Bit 99" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND98 ,Set/Clear Pending Bit 98" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND97 ,Set/Clear Pending Bit 97" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND96 ,Set/Clear Pending Bit 96" "Not pending,Pending" else rgroup.long 0x020C++0x03 line.long 0x0 "GICD_SET/CLR_PENDR3,Interrupt Set/Clear Pending Register 3" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x04) group.long 0x0210++0x03 line.long 0x0 "GICD_SET/CLR_PENDR4,Interrupt Set/Clear Pending Register 4" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND159 ,Set/Clear Pending Bit 159" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND158 ,Set/Clear Pending Bit 158" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND157 ,Set/Clear Pending Bit 157" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND156 ,Set/Clear Pending Bit 156" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND155 ,Set/Clear Pending Bit 155" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND154 ,Set/Clear Pending Bit 154" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND153 ,Set/Clear Pending Bit 153" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND152 ,Set/Clear Pending Bit 152" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND151 ,Set/Clear Pending Bit 151" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND150 ,Set/Clear Pending Bit 150" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND149 ,Set/Clear Pending Bit 149" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND148 ,Set/Clear Pending Bit 148" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND147 ,Set/Clear Pending Bit 147" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND146 ,Set/Clear Pending Bit 146" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND145 ,Set/Clear Pending Bit 145" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND144 ,Set/Clear Pending Bit 144" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND143 ,Set/Clear Pending Bit 143" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND142 ,Set/Clear Pending Bit 142" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND141 ,Set/Clear Pending Bit 141" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND140 ,Set/Clear Pending Bit 140" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND139 ,Set/Clear Pending Bit 139" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND138 ,Set/Clear Pending Bit 138" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND137 ,Set/Clear Pending Bit 137" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND136 ,Set/Clear Pending Bit 136" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND135 ,Set/Clear Pending Bit 135" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND134 ,Set/Clear Pending Bit 134" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND133 ,Set/Clear Pending Bit 133" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND132 ,Set/Clear Pending Bit 132" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND131 ,Set/Clear Pending Bit 131" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND130 ,Set/Clear Pending Bit 130" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND129 ,Set/Clear Pending Bit 129" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND128 ,Set/Clear Pending Bit 128" "Not pending,Pending" else rgroup.long 0x0210++0x03 line.long 0x0 "GICD_SET/CLR_PENDR4,Interrupt Set/Clear Pending Register 4" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x05) group.long 0x0214++0x03 line.long 0x0 "GICD_SET/CLR_PENDR5,Interrupt Set/Clear Pending Register 5" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND191 ,Set/Clear Pending Bit 191" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND190 ,Set/Clear Pending Bit 190" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND189 ,Set/Clear Pending Bit 189" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND188 ,Set/Clear Pending Bit 188" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND187 ,Set/Clear Pending Bit 187" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND186 ,Set/Clear Pending Bit 186" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND185 ,Set/Clear Pending Bit 185" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND184 ,Set/Clear Pending Bit 184" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND183 ,Set/Clear Pending Bit 183" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND182 ,Set/Clear Pending Bit 182" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND181 ,Set/Clear Pending Bit 181" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND180 ,Set/Clear Pending Bit 180" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND179 ,Set/Clear Pending Bit 179" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND178 ,Set/Clear Pending Bit 178" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND177 ,Set/Clear Pending Bit 177" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND176 ,Set/Clear Pending Bit 176" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND175 ,Set/Clear Pending Bit 175" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND174 ,Set/Clear Pending Bit 174" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND173 ,Set/Clear Pending Bit 173" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND172 ,Set/Clear Pending Bit 172" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND171 ,Set/Clear Pending Bit 171" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND170 ,Set/Clear Pending Bit 170" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND169 ,Set/Clear Pending Bit 169" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND168 ,Set/Clear Pending Bit 168" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND167 ,Set/Clear Pending Bit 167" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND166 ,Set/Clear Pending Bit 166" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND165 ,Set/Clear Pending Bit 165" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND164 ,Set/Clear Pending Bit 164" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND163 ,Set/Clear Pending Bit 163" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND162 ,Set/Clear Pending Bit 162" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND161 ,Set/Clear Pending Bit 161" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND160 ,Set/Clear Pending Bit 160" "Not pending,Pending" else rgroup.long 0x0214++0x03 line.long 0x0 "GICD_SET/CLR_PENDR5,Interrupt Set/Clear Pending Register 5" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x06) group.long 0x0218++0x03 line.long 0x0 "GICD_SET/CLR_PENDR6,Interrupt Set/Clear Pending Register 6" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND223 ,Set/Clear Pending Bit 223" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND222 ,Set/Clear Pending Bit 222" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND221 ,Set/Clear Pending Bit 221" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND220 ,Set/Clear Pending Bit 220" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND219 ,Set/Clear Pending Bit 219" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND218 ,Set/Clear Pending Bit 218" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND217 ,Set/Clear Pending Bit 217" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND216 ,Set/Clear Pending Bit 216" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND215 ,Set/Clear Pending Bit 215" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND214 ,Set/Clear Pending Bit 214" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND213 ,Set/Clear Pending Bit 213" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND212 ,Set/Clear Pending Bit 212" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND211 ,Set/Clear Pending Bit 211" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND210 ,Set/Clear Pending Bit 210" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND209 ,Set/Clear Pending Bit 209" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND208 ,Set/Clear Pending Bit 208" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND207 ,Set/Clear Pending Bit 207" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND206 ,Set/Clear Pending Bit 206" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND205 ,Set/Clear Pending Bit 205" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND204 ,Set/Clear Pending Bit 204" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND203 ,Set/Clear Pending Bit 203" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND202 ,Set/Clear Pending Bit 202" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND201 ,Set/Clear Pending Bit 201" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND200 ,Set/Clear Pending Bit 200" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND199 ,Set/Clear Pending Bit 199" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND198 ,Set/Clear Pending Bit 198" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND197 ,Set/Clear Pending Bit 197" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND196 ,Set/Clear Pending Bit 196" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND195 ,Set/Clear Pending Bit 195" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND194 ,Set/Clear Pending Bit 194" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND193 ,Set/Clear Pending Bit 193" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND192 ,Set/Clear Pending Bit 192" "Not pending,Pending" else rgroup.long 0x0218++0x03 line.long 0x0 "GICD_SET/CLR_PENDR6,Interrupt Set/Clear Pending Register 6" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x07) group.long 0x021C++0x03 line.long 0x0 "GICD_SET/CLR_PENDR7,Interrupt Set/Clear Pending Register 7" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND255 ,Set/Clear Pending Bit 255" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND254 ,Set/Clear Pending Bit 254" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND253 ,Set/Clear Pending Bit 253" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND252 ,Set/Clear Pending Bit 252" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND251 ,Set/Clear Pending Bit 251" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND250 ,Set/Clear Pending Bit 250" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND249 ,Set/Clear Pending Bit 249" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND248 ,Set/Clear Pending Bit 248" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND247 ,Set/Clear Pending Bit 247" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND246 ,Set/Clear Pending Bit 246" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND245 ,Set/Clear Pending Bit 245" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND244 ,Set/Clear Pending Bit 244" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND243 ,Set/Clear Pending Bit 243" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND242 ,Set/Clear Pending Bit 242" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND241 ,Set/Clear Pending Bit 241" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND240 ,Set/Clear Pending Bit 240" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND239 ,Set/Clear Pending Bit 239" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND238 ,Set/Clear Pending Bit 238" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND237 ,Set/Clear Pending Bit 237" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND236 ,Set/Clear Pending Bit 236" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND235 ,Set/Clear Pending Bit 235" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND234 ,Set/Clear Pending Bit 234" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND233 ,Set/Clear Pending Bit 233" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND232 ,Set/Clear Pending Bit 232" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND231 ,Set/Clear Pending Bit 231" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND230 ,Set/Clear Pending Bit 230" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND229 ,Set/Clear Pending Bit 229" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND228 ,Set/Clear Pending Bit 228" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND227 ,Set/Clear Pending Bit 227" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND226 ,Set/Clear Pending Bit 226" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND225 ,Set/Clear Pending Bit 225" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND224 ,Set/Clear Pending Bit 224" "Not pending,Pending" else rgroup.long 0x021C++0x03 line.long 0x0 "GICD_SET/CLR_PENDR7,Interrupt Set/Clear Pending Register 7" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x08) group.long 0x0220++0x03 line.long 0x0 "GICD_SET/CLR_PENDR8,Interrupt Set/Clear Pending Register 8" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND287 ,Set/Clear Pending Bit 287" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND286 ,Set/Clear Pending Bit 286" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND285 ,Set/Clear Pending Bit 285" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND284 ,Set/Clear Pending Bit 284" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND283 ,Set/Clear Pending Bit 283" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND282 ,Set/Clear Pending Bit 282" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND281 ,Set/Clear Pending Bit 281" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND280 ,Set/Clear Pending Bit 280" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND279 ,Set/Clear Pending Bit 279" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND278 ,Set/Clear Pending Bit 278" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND277 ,Set/Clear Pending Bit 277" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND276 ,Set/Clear Pending Bit 276" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND275 ,Set/Clear Pending Bit 275" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND274 ,Set/Clear Pending Bit 274" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND273 ,Set/Clear Pending Bit 273" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND272 ,Set/Clear Pending Bit 272" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND271 ,Set/Clear Pending Bit 271" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND270 ,Set/Clear Pending Bit 270" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND269 ,Set/Clear Pending Bit 269" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND268 ,Set/Clear Pending Bit 268" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND267 ,Set/Clear Pending Bit 267" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND266 ,Set/Clear Pending Bit 266" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND265 ,Set/Clear Pending Bit 265" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND264 ,Set/Clear Pending Bit 264" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND263 ,Set/Clear Pending Bit 263" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND262 ,Set/Clear Pending Bit 262" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND261 ,Set/Clear Pending Bit 261" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND260 ,Set/Clear Pending Bit 260" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND259 ,Set/Clear Pending Bit 259" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND258 ,Set/Clear Pending Bit 258" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND257 ,Set/Clear Pending Bit 257" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND256 ,Set/Clear Pending Bit 256" "Not pending,Pending" else rgroup.long 0x0220++0x03 line.long 0x0 "GICD_SET/CLR_PENDR8,Interrupt Set/Clear Pending Register 8" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x09) group.long 0x0224++0x03 line.long 0x0 "GICD_SET/CLR_PENDR9,Interrupt Set/Clear Pending Register 9" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND319 ,Set/Clear Pending Bit 319" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND318 ,Set/Clear Pending Bit 318" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND317 ,Set/Clear Pending Bit 317" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND316 ,Set/Clear Pending Bit 316" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND315 ,Set/Clear Pending Bit 315" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND314 ,Set/Clear Pending Bit 314" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND313 ,Set/Clear Pending Bit 313" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND312 ,Set/Clear Pending Bit 312" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND311 ,Set/Clear Pending Bit 311" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND310 ,Set/Clear Pending Bit 310" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND309 ,Set/Clear Pending Bit 309" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND308 ,Set/Clear Pending Bit 308" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND307 ,Set/Clear Pending Bit 307" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND306 ,Set/Clear Pending Bit 306" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND305 ,Set/Clear Pending Bit 305" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND304 ,Set/Clear Pending Bit 304" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND303 ,Set/Clear Pending Bit 303" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND302 ,Set/Clear Pending Bit 302" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND301 ,Set/Clear Pending Bit 301" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND300 ,Set/Clear Pending Bit 300" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND299 ,Set/Clear Pending Bit 299" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND298 ,Set/Clear Pending Bit 298" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND297 ,Set/Clear Pending Bit 297" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND296 ,Set/Clear Pending Bit 296" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND295 ,Set/Clear Pending Bit 295" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND294 ,Set/Clear Pending Bit 294" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND293 ,Set/Clear Pending Bit 293" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND292 ,Set/Clear Pending Bit 292" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND291 ,Set/Clear Pending Bit 291" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND290 ,Set/Clear Pending Bit 290" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND289 ,Set/Clear Pending Bit 289" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND288 ,Set/Clear Pending Bit 288" "Not pending,Pending" else rgroup.long 0x0224++0x03 line.long 0x0 "GICD_SET/CLR_PENDR9,Interrupt Set/Clear Pending Register 9" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x0A) group.long 0x0228++0x03 line.long 0x0 "GICD_SET/CLR_PENDR10,Interrupt Set/Clear Pending Register 10" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND351 ,Set/Clear Pending Bit 351" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND350 ,Set/Clear Pending Bit 350" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND349 ,Set/Clear Pending Bit 349" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND348 ,Set/Clear Pending Bit 348" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND347 ,Set/Clear Pending Bit 347" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND346 ,Set/Clear Pending Bit 346" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND345 ,Set/Clear Pending Bit 345" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND344 ,Set/Clear Pending Bit 344" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND343 ,Set/Clear Pending Bit 343" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND342 ,Set/Clear Pending Bit 342" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND341 ,Set/Clear Pending Bit 341" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND340 ,Set/Clear Pending Bit 340" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND339 ,Set/Clear Pending Bit 339" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND338 ,Set/Clear Pending Bit 338" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND337 ,Set/Clear Pending Bit 337" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND336 ,Set/Clear Pending Bit 336" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND335 ,Set/Clear Pending Bit 335" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND334 ,Set/Clear Pending Bit 334" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND333 ,Set/Clear Pending Bit 333" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND332 ,Set/Clear Pending Bit 332" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND331 ,Set/Clear Pending Bit 331" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND330 ,Set/Clear Pending Bit 330" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND329 ,Set/Clear Pending Bit 329" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND328 ,Set/Clear Pending Bit 328" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND327 ,Set/Clear Pending Bit 327" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND326 ,Set/Clear Pending Bit 326" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND325 ,Set/Clear Pending Bit 325" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND324 ,Set/Clear Pending Bit 324" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND323 ,Set/Clear Pending Bit 323" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND322 ,Set/Clear Pending Bit 322" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND321 ,Set/Clear Pending Bit 321" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND320 ,Set/Clear Pending Bit 320" "Not pending,Pending" else rgroup.long 0x0228++0x03 line.long 0x0 "GICD_SET/CLR_PENDR10,Interrupt Set/Clear Pending Register 10" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x0B) group.long 0x022C++0x03 line.long 0x0 "GICD_SET/CLR_PENDR11,Interrupt Set/Clear Pending Register 11" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND383 ,Set/Clear Pending Bit 383" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND382 ,Set/Clear Pending Bit 382" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND381 ,Set/Clear Pending Bit 381" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND380 ,Set/Clear Pending Bit 380" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND379 ,Set/Clear Pending Bit 379" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND378 ,Set/Clear Pending Bit 378" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND377 ,Set/Clear Pending Bit 377" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND376 ,Set/Clear Pending Bit 376" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND375 ,Set/Clear Pending Bit 375" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND374 ,Set/Clear Pending Bit 374" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND373 ,Set/Clear Pending Bit 373" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND372 ,Set/Clear Pending Bit 372" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND371 ,Set/Clear Pending Bit 371" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND370 ,Set/Clear Pending Bit 370" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND369 ,Set/Clear Pending Bit 369" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND368 ,Set/Clear Pending Bit 368" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND367 ,Set/Clear Pending Bit 367" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND366 ,Set/Clear Pending Bit 366" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND365 ,Set/Clear Pending Bit 365" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND364 ,Set/Clear Pending Bit 364" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND363 ,Set/Clear Pending Bit 363" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND362 ,Set/Clear Pending Bit 362" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND361 ,Set/Clear Pending Bit 361" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND360 ,Set/Clear Pending Bit 360" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND359 ,Set/Clear Pending Bit 359" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND358 ,Set/Clear Pending Bit 358" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND357 ,Set/Clear Pending Bit 357" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND356 ,Set/Clear Pending Bit 356" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND355 ,Set/Clear Pending Bit 355" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND354 ,Set/Clear Pending Bit 354" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND353 ,Set/Clear Pending Bit 353" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND352 ,Set/Clear Pending Bit 352" "Not pending,Pending" else rgroup.long 0x022C++0x03 line.long 0x0 "GICD_SET/CLR_PENDR11,Interrupt Set/Clear Pending Register 11" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x0C) group.long 0x0230++0x03 line.long 0x0 "GICD_SET/CLR_PENDR12,Interrupt Set/Clear Pending Register 12" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND415 ,Set/Clear Pending Bit 415" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND414 ,Set/Clear Pending Bit 414" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND413 ,Set/Clear Pending Bit 413" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND412 ,Set/Clear Pending Bit 412" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND411 ,Set/Clear Pending Bit 411" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND410 ,Set/Clear Pending Bit 410" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND409 ,Set/Clear Pending Bit 409" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND408 ,Set/Clear Pending Bit 408" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND407 ,Set/Clear Pending Bit 407" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND406 ,Set/Clear Pending Bit 406" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND405 ,Set/Clear Pending Bit 405" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND404 ,Set/Clear Pending Bit 404" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND403 ,Set/Clear Pending Bit 403" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND402 ,Set/Clear Pending Bit 402" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND401 ,Set/Clear Pending Bit 401" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND400 ,Set/Clear Pending Bit 400" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND399 ,Set/Clear Pending Bit 399" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND398 ,Set/Clear Pending Bit 398" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND397 ,Set/Clear Pending Bit 397" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND396 ,Set/Clear Pending Bit 396" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND395 ,Set/Clear Pending Bit 395" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND394 ,Set/Clear Pending Bit 394" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND393 ,Set/Clear Pending Bit 393" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND392 ,Set/Clear Pending Bit 392" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND391 ,Set/Clear Pending Bit 391" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND390 ,Set/Clear Pending Bit 390" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND389 ,Set/Clear Pending Bit 389" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND388 ,Set/Clear Pending Bit 388" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND387 ,Set/Clear Pending Bit 387" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND386 ,Set/Clear Pending Bit 386" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND385 ,Set/Clear Pending Bit 385" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND384 ,Set/Clear Pending Bit 384" "Not pending,Pending" else rgroup.long 0x0230++0x03 line.long 0x0 "GICD_SET/CLR_PENDR12,Interrupt Set/Clear Pending Register 12" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x0D) group.long 0x0234++0x03 line.long 0x0 "GICD_SET/CLR_PENDR13,Interrupt Set/Clear Pending Register 13" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND447 ,Set/Clear Pending Bit 447" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND446 ,Set/Clear Pending Bit 446" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND445 ,Set/Clear Pending Bit 445" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND444 ,Set/Clear Pending Bit 444" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND443 ,Set/Clear Pending Bit 443" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND442 ,Set/Clear Pending Bit 442" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND441 ,Set/Clear Pending Bit 441" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND440 ,Set/Clear Pending Bit 440" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND439 ,Set/Clear Pending Bit 439" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND438 ,Set/Clear Pending Bit 438" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND437 ,Set/Clear Pending Bit 437" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND436 ,Set/Clear Pending Bit 436" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND435 ,Set/Clear Pending Bit 435" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND434 ,Set/Clear Pending Bit 434" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND433 ,Set/Clear Pending Bit 433" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND432 ,Set/Clear Pending Bit 432" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND431 ,Set/Clear Pending Bit 431" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND430 ,Set/Clear Pending Bit 430" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND429 ,Set/Clear Pending Bit 429" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND428 ,Set/Clear Pending Bit 428" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND427 ,Set/Clear Pending Bit 427" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND426 ,Set/Clear Pending Bit 426" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND425 ,Set/Clear Pending Bit 425" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND424 ,Set/Clear Pending Bit 424" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND423 ,Set/Clear Pending Bit 423" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND422 ,Set/Clear Pending Bit 422" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND421 ,Set/Clear Pending Bit 421" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND420 ,Set/Clear Pending Bit 420" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND419 ,Set/Clear Pending Bit 419" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND418 ,Set/Clear Pending Bit 418" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND417 ,Set/Clear Pending Bit 417" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND416 ,Set/Clear Pending Bit 416" "Not pending,Pending" else rgroup.long 0x0234++0x03 line.long 0x0 "GICD_SET/CLR_PENDR13,Interrupt Set/Clear Pending Register 13" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x0E) group.long 0x0238++0x03 line.long 0x0 "GICD_SET/CLR_PENDR14,Interrupt Set/Clear Pending Register 14" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND479 ,Set/Clear Pending Bit 479" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND478 ,Set/Clear Pending Bit 478" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND477 ,Set/Clear Pending Bit 477" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND476 ,Set/Clear Pending Bit 476" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND475 ,Set/Clear Pending Bit 475" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND474 ,Set/Clear Pending Bit 474" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND473 ,Set/Clear Pending Bit 473" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND472 ,Set/Clear Pending Bit 472" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND471 ,Set/Clear Pending Bit 471" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND470 ,Set/Clear Pending Bit 470" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND469 ,Set/Clear Pending Bit 469" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND468 ,Set/Clear Pending Bit 468" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND467 ,Set/Clear Pending Bit 467" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND466 ,Set/Clear Pending Bit 466" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND465 ,Set/Clear Pending Bit 465" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND464 ,Set/Clear Pending Bit 464" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND463 ,Set/Clear Pending Bit 463" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND462 ,Set/Clear Pending Bit 462" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND461 ,Set/Clear Pending Bit 461" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND460 ,Set/Clear Pending Bit 460" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND459 ,Set/Clear Pending Bit 459" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND458 ,Set/Clear Pending Bit 458" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND457 ,Set/Clear Pending Bit 457" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND456 ,Set/Clear Pending Bit 456" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND455 ,Set/Clear Pending Bit 455" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND454 ,Set/Clear Pending Bit 454" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND453 ,Set/Clear Pending Bit 453" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND452 ,Set/Clear Pending Bit 452" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND451 ,Set/Clear Pending Bit 451" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND450 ,Set/Clear Pending Bit 450" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND449 ,Set/Clear Pending Bit 449" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND448 ,Set/Clear Pending Bit 448" "Not pending,Pending" else rgroup.long 0x0238++0x03 line.long 0x0 "GICD_SET/CLR_PENDR14,Interrupt Set/Clear Pending Register 14" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x0F) group.long 0x023C++0x03 line.long 0x0 "GICD_SET/CLR_PENDR15,Interrupt Set/Clear Pending Register 15" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND511 ,Set/Clear Pending Bit 511" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND510 ,Set/Clear Pending Bit 510" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND509 ,Set/Clear Pending Bit 509" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND508 ,Set/Clear Pending Bit 508" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND507 ,Set/Clear Pending Bit 507" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND506 ,Set/Clear Pending Bit 506" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND505 ,Set/Clear Pending Bit 505" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND504 ,Set/Clear Pending Bit 504" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND503 ,Set/Clear Pending Bit 503" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND502 ,Set/Clear Pending Bit 502" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND501 ,Set/Clear Pending Bit 501" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND500 ,Set/Clear Pending Bit 500" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND499 ,Set/Clear Pending Bit 499" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND498 ,Set/Clear Pending Bit 498" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND497 ,Set/Clear Pending Bit 497" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND496 ,Set/Clear Pending Bit 496" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND495 ,Set/Clear Pending Bit 495" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND494 ,Set/Clear Pending Bit 494" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND493 ,Set/Clear Pending Bit 493" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND492 ,Set/Clear Pending Bit 492" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND491 ,Set/Clear Pending Bit 491" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND490 ,Set/Clear Pending Bit 490" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND489 ,Set/Clear Pending Bit 489" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND488 ,Set/Clear Pending Bit 488" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND487 ,Set/Clear Pending Bit 487" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND486 ,Set/Clear Pending Bit 486" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND485 ,Set/Clear Pending Bit 485" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND484 ,Set/Clear Pending Bit 484" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND483 ,Set/Clear Pending Bit 483" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND482 ,Set/Clear Pending Bit 482" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND481 ,Set/Clear Pending Bit 481" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND480 ,Set/Clear Pending Bit 480" "Not pending,Pending" else rgroup.long 0x023C++0x03 line.long 0x0 "GICD_SET/CLR_PENDR15,Interrupt Set/Clear Pending Register 15" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x10) group.long 0x0240++0x03 line.long 0x0 "GICD_SET/CLR_PENDR16,Interrupt Set/Clear Pending Register 16" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND543 ,Set/Clear Pending Bit 543" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND542 ,Set/Clear Pending Bit 542" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND541 ,Set/Clear Pending Bit 541" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND540 ,Set/Clear Pending Bit 540" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND539 ,Set/Clear Pending Bit 539" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND538 ,Set/Clear Pending Bit 538" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND537 ,Set/Clear Pending Bit 537" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND536 ,Set/Clear Pending Bit 536" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND535 ,Set/Clear Pending Bit 535" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND534 ,Set/Clear Pending Bit 534" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND533 ,Set/Clear Pending Bit 533" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND532 ,Set/Clear Pending Bit 532" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND531 ,Set/Clear Pending Bit 531" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND530 ,Set/Clear Pending Bit 530" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND529 ,Set/Clear Pending Bit 529" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND528 ,Set/Clear Pending Bit 528" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND527 ,Set/Clear Pending Bit 527" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND526 ,Set/Clear Pending Bit 526" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND525 ,Set/Clear Pending Bit 525" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND524 ,Set/Clear Pending Bit 524" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND523 ,Set/Clear Pending Bit 523" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND522 ,Set/Clear Pending Bit 522" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND521 ,Set/Clear Pending Bit 521" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND520 ,Set/Clear Pending Bit 520" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND519 ,Set/Clear Pending Bit 519" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND518 ,Set/Clear Pending Bit 518" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND517 ,Set/Clear Pending Bit 517" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND516 ,Set/Clear Pending Bit 516" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND515 ,Set/Clear Pending Bit 515" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND514 ,Set/Clear Pending Bit 514" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND513 ,Set/Clear Pending Bit 513" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND512 ,Set/Clear Pending Bit 512" "Not pending,Pending" else rgroup.long 0x0240++0x03 line.long 0x0 "GICD_SET/CLR_PENDR16,Interrupt Set/Clear Pending Register 16" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x11) group.long 0x0244++0x03 line.long 0x0 "GICD_SET/CLR_PENDR17,Interrupt Set/Clear Pending Register 17" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND575 ,Set/Clear Pending Bit 575" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND574 ,Set/Clear Pending Bit 574" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND573 ,Set/Clear Pending Bit 573" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND572 ,Set/Clear Pending Bit 572" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND571 ,Set/Clear Pending Bit 571" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND570 ,Set/Clear Pending Bit 570" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND569 ,Set/Clear Pending Bit 569" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND568 ,Set/Clear Pending Bit 568" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND567 ,Set/Clear Pending Bit 567" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND566 ,Set/Clear Pending Bit 566" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND565 ,Set/Clear Pending Bit 565" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND564 ,Set/Clear Pending Bit 564" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND563 ,Set/Clear Pending Bit 563" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND562 ,Set/Clear Pending Bit 562" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND561 ,Set/Clear Pending Bit 561" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND560 ,Set/Clear Pending Bit 560" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND559 ,Set/Clear Pending Bit 559" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND558 ,Set/Clear Pending Bit 558" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND557 ,Set/Clear Pending Bit 557" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND556 ,Set/Clear Pending Bit 556" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND555 ,Set/Clear Pending Bit 555" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND554 ,Set/Clear Pending Bit 554" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND553 ,Set/Clear Pending Bit 553" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND552 ,Set/Clear Pending Bit 552" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND551 ,Set/Clear Pending Bit 551" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND550 ,Set/Clear Pending Bit 550" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND549 ,Set/Clear Pending Bit 549" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND548 ,Set/Clear Pending Bit 548" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND547 ,Set/Clear Pending Bit 547" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND546 ,Set/Clear Pending Bit 546" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND545 ,Set/Clear Pending Bit 545" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND544 ,Set/Clear Pending Bit 544" "Not pending,Pending" else rgroup.long 0x0244++0x03 line.long 0x0 "GICD_SET/CLR_PENDR17,Interrupt Set/Clear Pending Register 17" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x12) group.long 0x0248++0x03 line.long 0x0 "GICD_SET/CLR_PENDR18,Interrupt Set/Clear Pending Register 18" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND607 ,Set/Clear Pending Bit 607" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND606 ,Set/Clear Pending Bit 606" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND605 ,Set/Clear Pending Bit 605" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND604 ,Set/Clear Pending Bit 604" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND603 ,Set/Clear Pending Bit 603" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND602 ,Set/Clear Pending Bit 602" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND601 ,Set/Clear Pending Bit 601" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND600 ,Set/Clear Pending Bit 600" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND599 ,Set/Clear Pending Bit 599" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND598 ,Set/Clear Pending Bit 598" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND597 ,Set/Clear Pending Bit 597" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND596 ,Set/Clear Pending Bit 596" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND595 ,Set/Clear Pending Bit 595" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND594 ,Set/Clear Pending Bit 594" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND593 ,Set/Clear Pending Bit 593" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND592 ,Set/Clear Pending Bit 592" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND591 ,Set/Clear Pending Bit 591" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND590 ,Set/Clear Pending Bit 590" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND589 ,Set/Clear Pending Bit 589" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND588 ,Set/Clear Pending Bit 588" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND587 ,Set/Clear Pending Bit 587" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND586 ,Set/Clear Pending Bit 586" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND585 ,Set/Clear Pending Bit 585" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND584 ,Set/Clear Pending Bit 584" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND583 ,Set/Clear Pending Bit 583" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND582 ,Set/Clear Pending Bit 582" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND581 ,Set/Clear Pending Bit 581" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND580 ,Set/Clear Pending Bit 580" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND579 ,Set/Clear Pending Bit 579" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND578 ,Set/Clear Pending Bit 578" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND577 ,Set/Clear Pending Bit 577" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND576 ,Set/Clear Pending Bit 576" "Not pending,Pending" else rgroup.long 0x0248++0x03 line.long 0x0 "GICD_SET/CLR_PENDR18,Interrupt Set/Clear Pending Register 18" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x13) group.long 0x024C++0x03 line.long 0x0 "GICD_SET/CLR_PENDR19,Interrupt Set/Clear Pending Register 19" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND639 ,Set/Clear Pending Bit 639" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND638 ,Set/Clear Pending Bit 638" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND637 ,Set/Clear Pending Bit 637" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND636 ,Set/Clear Pending Bit 636" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND635 ,Set/Clear Pending Bit 635" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND634 ,Set/Clear Pending Bit 634" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND633 ,Set/Clear Pending Bit 633" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND632 ,Set/Clear Pending Bit 632" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND631 ,Set/Clear Pending Bit 631" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND630 ,Set/Clear Pending Bit 630" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND629 ,Set/Clear Pending Bit 629" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND628 ,Set/Clear Pending Bit 628" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND627 ,Set/Clear Pending Bit 627" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND626 ,Set/Clear Pending Bit 626" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND625 ,Set/Clear Pending Bit 625" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND624 ,Set/Clear Pending Bit 624" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND623 ,Set/Clear Pending Bit 623" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND622 ,Set/Clear Pending Bit 622" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND621 ,Set/Clear Pending Bit 621" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND620 ,Set/Clear Pending Bit 620" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND619 ,Set/Clear Pending Bit 619" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND618 ,Set/Clear Pending Bit 618" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND617 ,Set/Clear Pending Bit 617" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND616 ,Set/Clear Pending Bit 616" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND615 ,Set/Clear Pending Bit 615" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND614 ,Set/Clear Pending Bit 614" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND613 ,Set/Clear Pending Bit 613" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND612 ,Set/Clear Pending Bit 612" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND611 ,Set/Clear Pending Bit 611" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND610 ,Set/Clear Pending Bit 610" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND609 ,Set/Clear Pending Bit 609" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND608 ,Set/Clear Pending Bit 608" "Not pending,Pending" else rgroup.long 0x024C++0x03 line.long 0x0 "GICD_SET/CLR_PENDR19,Interrupt Set/Clear Pending Register 19" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x14) group.long 0x0250++0x03 line.long 0x0 "GICD_SET/CLR_PENDR20,Interrupt Set/Clear Pending Register 20" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND671 ,Set/Clear Pending Bit 671" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND670 ,Set/Clear Pending Bit 670" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND669 ,Set/Clear Pending Bit 669" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND668 ,Set/Clear Pending Bit 668" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND667 ,Set/Clear Pending Bit 667" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND666 ,Set/Clear Pending Bit 666" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND665 ,Set/Clear Pending Bit 665" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND664 ,Set/Clear Pending Bit 664" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND663 ,Set/Clear Pending Bit 663" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND662 ,Set/Clear Pending Bit 662" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND661 ,Set/Clear Pending Bit 661" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND660 ,Set/Clear Pending Bit 660" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND659 ,Set/Clear Pending Bit 659" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND658 ,Set/Clear Pending Bit 658" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND657 ,Set/Clear Pending Bit 657" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND656 ,Set/Clear Pending Bit 656" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND655 ,Set/Clear Pending Bit 655" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND654 ,Set/Clear Pending Bit 654" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND653 ,Set/Clear Pending Bit 653" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND652 ,Set/Clear Pending Bit 652" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND651 ,Set/Clear Pending Bit 651" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND650 ,Set/Clear Pending Bit 650" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND649 ,Set/Clear Pending Bit 649" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND648 ,Set/Clear Pending Bit 648" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND647 ,Set/Clear Pending Bit 647" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND646 ,Set/Clear Pending Bit 646" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND645 ,Set/Clear Pending Bit 645" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND644 ,Set/Clear Pending Bit 644" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND643 ,Set/Clear Pending Bit 643" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND642 ,Set/Clear Pending Bit 642" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND641 ,Set/Clear Pending Bit 641" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND640 ,Set/Clear Pending Bit 640" "Not pending,Pending" else rgroup.long 0x0250++0x03 line.long 0x0 "GICD_SET/CLR_PENDR20,Interrupt Set/Clear Pending Register 20" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x15) group.long 0x0254++0x03 line.long 0x0 "GICD_SET/CLR_PENDR21,Interrupt Set/Clear Pending Register 21" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND703 ,Set/Clear Pending Bit 703" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND702 ,Set/Clear Pending Bit 702" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND701 ,Set/Clear Pending Bit 701" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND700 ,Set/Clear Pending Bit 700" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND699 ,Set/Clear Pending Bit 699" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND698 ,Set/Clear Pending Bit 698" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND697 ,Set/Clear Pending Bit 697" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND696 ,Set/Clear Pending Bit 696" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND695 ,Set/Clear Pending Bit 695" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND694 ,Set/Clear Pending Bit 694" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND693 ,Set/Clear Pending Bit 693" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND692 ,Set/Clear Pending Bit 692" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND691 ,Set/Clear Pending Bit 691" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND690 ,Set/Clear Pending Bit 690" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND689 ,Set/Clear Pending Bit 689" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND688 ,Set/Clear Pending Bit 688" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND687 ,Set/Clear Pending Bit 687" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND686 ,Set/Clear Pending Bit 686" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND685 ,Set/Clear Pending Bit 685" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND684 ,Set/Clear Pending Bit 684" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND683 ,Set/Clear Pending Bit 683" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND682 ,Set/Clear Pending Bit 682" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND681 ,Set/Clear Pending Bit 681" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND680 ,Set/Clear Pending Bit 680" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND679 ,Set/Clear Pending Bit 679" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND678 ,Set/Clear Pending Bit 678" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND677 ,Set/Clear Pending Bit 677" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND676 ,Set/Clear Pending Bit 676" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND675 ,Set/Clear Pending Bit 675" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND674 ,Set/Clear Pending Bit 674" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND673 ,Set/Clear Pending Bit 673" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND672 ,Set/Clear Pending Bit 672" "Not pending,Pending" else rgroup.long 0x0254++0x03 line.long 0x0 "GICD_SET/CLR_PENDR21,Interrupt Set/Clear Pending Register 21" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x16) group.long 0x0258++0x03 line.long 0x0 "GICD_SET/CLR_PENDR22,Interrupt Set/Clear Pending Register 22" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND735 ,Set/Clear Pending Bit 735" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND734 ,Set/Clear Pending Bit 734" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND733 ,Set/Clear Pending Bit 733" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND732 ,Set/Clear Pending Bit 732" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND731 ,Set/Clear Pending Bit 731" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND730 ,Set/Clear Pending Bit 730" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND729 ,Set/Clear Pending Bit 729" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND728 ,Set/Clear Pending Bit 728" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND727 ,Set/Clear Pending Bit 727" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND726 ,Set/Clear Pending Bit 726" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND725 ,Set/Clear Pending Bit 725" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND724 ,Set/Clear Pending Bit 724" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND723 ,Set/Clear Pending Bit 723" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND722 ,Set/Clear Pending Bit 722" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND721 ,Set/Clear Pending Bit 721" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND720 ,Set/Clear Pending Bit 720" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND719 ,Set/Clear Pending Bit 719" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND718 ,Set/Clear Pending Bit 718" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND717 ,Set/Clear Pending Bit 717" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND716 ,Set/Clear Pending Bit 716" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND715 ,Set/Clear Pending Bit 715" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND714 ,Set/Clear Pending Bit 714" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND713 ,Set/Clear Pending Bit 713" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND712 ,Set/Clear Pending Bit 712" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND711 ,Set/Clear Pending Bit 711" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND710 ,Set/Clear Pending Bit 710" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND709 ,Set/Clear Pending Bit 709" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND708 ,Set/Clear Pending Bit 708" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND707 ,Set/Clear Pending Bit 707" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND706 ,Set/Clear Pending Bit 706" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND705 ,Set/Clear Pending Bit 705" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND704 ,Set/Clear Pending Bit 704" "Not pending,Pending" else rgroup.long 0x0258++0x03 line.long 0x0 "GICD_SET/CLR_PENDR22,Interrupt Set/Clear Pending Register 22" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x17) group.long 0x025C++0x03 line.long 0x0 "GICD_SET/CLR_PENDR23,Interrupt Set/Clear Pending Register 23" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND767 ,Set/Clear Pending Bit 767" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND766 ,Set/Clear Pending Bit 766" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND765 ,Set/Clear Pending Bit 765" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND764 ,Set/Clear Pending Bit 764" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND763 ,Set/Clear Pending Bit 763" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND762 ,Set/Clear Pending Bit 762" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND761 ,Set/Clear Pending Bit 761" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND760 ,Set/Clear Pending Bit 760" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND759 ,Set/Clear Pending Bit 759" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND758 ,Set/Clear Pending Bit 758" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND757 ,Set/Clear Pending Bit 757" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND756 ,Set/Clear Pending Bit 756" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND755 ,Set/Clear Pending Bit 755" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND754 ,Set/Clear Pending Bit 754" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND753 ,Set/Clear Pending Bit 753" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND752 ,Set/Clear Pending Bit 752" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND751 ,Set/Clear Pending Bit 751" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND750 ,Set/Clear Pending Bit 750" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND749 ,Set/Clear Pending Bit 749" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND748 ,Set/Clear Pending Bit 748" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND747 ,Set/Clear Pending Bit 747" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND746 ,Set/Clear Pending Bit 746" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND745 ,Set/Clear Pending Bit 745" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND744 ,Set/Clear Pending Bit 744" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND743 ,Set/Clear Pending Bit 743" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND742 ,Set/Clear Pending Bit 742" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND741 ,Set/Clear Pending Bit 741" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND740 ,Set/Clear Pending Bit 740" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND739 ,Set/Clear Pending Bit 739" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND738 ,Set/Clear Pending Bit 738" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND737 ,Set/Clear Pending Bit 737" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND736 ,Set/Clear Pending Bit 736" "Not pending,Pending" else rgroup.long 0x025C++0x03 line.long 0x0 "GICD_SET/CLR_PENDR23,Interrupt Set/Clear Pending Register 23" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x18) group.long 0x0260++0x03 line.long 0x0 "GICD_SET/CLR_PENDR24,Interrupt Set/Clear Pending Register 24" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND799 ,Set/Clear Pending Bit 799" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND798 ,Set/Clear Pending Bit 798" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND797 ,Set/Clear Pending Bit 797" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND796 ,Set/Clear Pending Bit 796" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND795 ,Set/Clear Pending Bit 795" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND794 ,Set/Clear Pending Bit 794" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND793 ,Set/Clear Pending Bit 793" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND792 ,Set/Clear Pending Bit 792" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND791 ,Set/Clear Pending Bit 791" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND790 ,Set/Clear Pending Bit 790" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND789 ,Set/Clear Pending Bit 789" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND788 ,Set/Clear Pending Bit 788" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND787 ,Set/Clear Pending Bit 787" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND786 ,Set/Clear Pending Bit 786" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND785 ,Set/Clear Pending Bit 785" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND784 ,Set/Clear Pending Bit 784" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND783 ,Set/Clear Pending Bit 783" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND782 ,Set/Clear Pending Bit 782" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND781 ,Set/Clear Pending Bit 781" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND780 ,Set/Clear Pending Bit 780" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND779 ,Set/Clear Pending Bit 779" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND778 ,Set/Clear Pending Bit 778" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND777 ,Set/Clear Pending Bit 777" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND776 ,Set/Clear Pending Bit 776" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND775 ,Set/Clear Pending Bit 775" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND774 ,Set/Clear Pending Bit 774" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND773 ,Set/Clear Pending Bit 773" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND772 ,Set/Clear Pending Bit 772" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND771 ,Set/Clear Pending Bit 771" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND770 ,Set/Clear Pending Bit 770" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND769 ,Set/Clear Pending Bit 769" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND768 ,Set/Clear Pending Bit 768" "Not pending,Pending" else rgroup.long 0x0260++0x03 line.long 0x0 "GICD_SET/CLR_PENDR24,Interrupt Set/Clear Pending Register 24" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x19) group.long 0x0264++0x03 line.long 0x0 "GICD_SET/CLR_PENDR25,Interrupt Set/Clear Pending Register 25" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND831 ,Set/Clear Pending Bit 831" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND830 ,Set/Clear Pending Bit 830" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND829 ,Set/Clear Pending Bit 829" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND828 ,Set/Clear Pending Bit 828" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND827 ,Set/Clear Pending Bit 827" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND826 ,Set/Clear Pending Bit 826" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND825 ,Set/Clear Pending Bit 825" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND824 ,Set/Clear Pending Bit 824" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND823 ,Set/Clear Pending Bit 823" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND822 ,Set/Clear Pending Bit 822" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND821 ,Set/Clear Pending Bit 821" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND820 ,Set/Clear Pending Bit 820" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND819 ,Set/Clear Pending Bit 819" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND818 ,Set/Clear Pending Bit 818" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND817 ,Set/Clear Pending Bit 817" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND816 ,Set/Clear Pending Bit 816" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND815 ,Set/Clear Pending Bit 815" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND814 ,Set/Clear Pending Bit 814" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND813 ,Set/Clear Pending Bit 813" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND812 ,Set/Clear Pending Bit 812" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND811 ,Set/Clear Pending Bit 811" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND810 ,Set/Clear Pending Bit 810" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND809 ,Set/Clear Pending Bit 809" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND808 ,Set/Clear Pending Bit 808" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND807 ,Set/Clear Pending Bit 807" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND806 ,Set/Clear Pending Bit 806" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND805 ,Set/Clear Pending Bit 805" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND804 ,Set/Clear Pending Bit 804" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND803 ,Set/Clear Pending Bit 803" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND802 ,Set/Clear Pending Bit 802" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND801 ,Set/Clear Pending Bit 801" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND800 ,Set/Clear Pending Bit 800" "Not pending,Pending" else rgroup.long 0x0264++0x03 line.long 0x0 "GICD_SET/CLR_PENDR25,Interrupt Set/Clear Pending Register 25" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x1A) group.long 0x0268++0x03 line.long 0x0 "GICD_SET/CLR_PENDR26,Interrupt Set/Clear Pending Register 26" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND863 ,Set/Clear Pending Bit 863" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND862 ,Set/Clear Pending Bit 862" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND861 ,Set/Clear Pending Bit 861" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND860 ,Set/Clear Pending Bit 860" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND859 ,Set/Clear Pending Bit 859" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND858 ,Set/Clear Pending Bit 858" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND857 ,Set/Clear Pending Bit 857" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND856 ,Set/Clear Pending Bit 856" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND855 ,Set/Clear Pending Bit 855" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND854 ,Set/Clear Pending Bit 854" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND853 ,Set/Clear Pending Bit 853" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND852 ,Set/Clear Pending Bit 852" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND851 ,Set/Clear Pending Bit 851" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND850 ,Set/Clear Pending Bit 850" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND849 ,Set/Clear Pending Bit 849" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND848 ,Set/Clear Pending Bit 848" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND847 ,Set/Clear Pending Bit 847" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND846 ,Set/Clear Pending Bit 846" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND845 ,Set/Clear Pending Bit 845" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND844 ,Set/Clear Pending Bit 844" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND843 ,Set/Clear Pending Bit 843" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND842 ,Set/Clear Pending Bit 842" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND841 ,Set/Clear Pending Bit 841" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND840 ,Set/Clear Pending Bit 840" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND839 ,Set/Clear Pending Bit 839" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND838 ,Set/Clear Pending Bit 838" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND837 ,Set/Clear Pending Bit 837" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND836 ,Set/Clear Pending Bit 836" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND835 ,Set/Clear Pending Bit 835" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND834 ,Set/Clear Pending Bit 834" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND833 ,Set/Clear Pending Bit 833" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND832 ,Set/Clear Pending Bit 832" "Not pending,Pending" else rgroup.long 0x0268++0x03 line.long 0x0 "GICD_SET/CLR_PENDR26,Interrupt Set/Clear Pending Register 26" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x1B) group.long 0x026C++0x03 line.long 0x0 "GICD_SET/CLR_PENDR27,Interrupt Set/Clear Pending Register 27" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND895 ,Set/Clear Pending Bit 895" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND894 ,Set/Clear Pending Bit 894" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND893 ,Set/Clear Pending Bit 893" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND892 ,Set/Clear Pending Bit 892" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND891 ,Set/Clear Pending Bit 891" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND890 ,Set/Clear Pending Bit 890" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND889 ,Set/Clear Pending Bit 889" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND888 ,Set/Clear Pending Bit 888" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND887 ,Set/Clear Pending Bit 887" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND886 ,Set/Clear Pending Bit 886" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND885 ,Set/Clear Pending Bit 885" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND884 ,Set/Clear Pending Bit 884" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND883 ,Set/Clear Pending Bit 883" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND882 ,Set/Clear Pending Bit 882" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND881 ,Set/Clear Pending Bit 881" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND880 ,Set/Clear Pending Bit 880" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND879 ,Set/Clear Pending Bit 879" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND878 ,Set/Clear Pending Bit 878" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND877 ,Set/Clear Pending Bit 877" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND876 ,Set/Clear Pending Bit 876" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND875 ,Set/Clear Pending Bit 875" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND874 ,Set/Clear Pending Bit 874" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND873 ,Set/Clear Pending Bit 873" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND872 ,Set/Clear Pending Bit 872" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND871 ,Set/Clear Pending Bit 871" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND870 ,Set/Clear Pending Bit 870" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND869 ,Set/Clear Pending Bit 869" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND868 ,Set/Clear Pending Bit 868" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND867 ,Set/Clear Pending Bit 867" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND866 ,Set/Clear Pending Bit 866" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND865 ,Set/Clear Pending Bit 865" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND864 ,Set/Clear Pending Bit 864" "Not pending,Pending" else rgroup.long 0x026C++0x03 line.long 0x0 "GICD_SET/CLR_PENDR27,Interrupt Set/Clear Pending Register 27" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x1C) group.long 0x0270++0x03 line.long 0x0 "GICD_SET/CLR_PENDR28,Interrupt Set/Clear Pending Register 28" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND927 ,Set/Clear Pending Bit 927" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND926 ,Set/Clear Pending Bit 926" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND925 ,Set/Clear Pending Bit 925" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND924 ,Set/Clear Pending Bit 924" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND923 ,Set/Clear Pending Bit 923" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND922 ,Set/Clear Pending Bit 922" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND921 ,Set/Clear Pending Bit 921" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND920 ,Set/Clear Pending Bit 920" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND919 ,Set/Clear Pending Bit 919" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND918 ,Set/Clear Pending Bit 918" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND917 ,Set/Clear Pending Bit 917" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND916 ,Set/Clear Pending Bit 916" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND915 ,Set/Clear Pending Bit 915" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND914 ,Set/Clear Pending Bit 914" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND913 ,Set/Clear Pending Bit 913" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND912 ,Set/Clear Pending Bit 912" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND911 ,Set/Clear Pending Bit 911" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND910 ,Set/Clear Pending Bit 910" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND909 ,Set/Clear Pending Bit 909" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND908 ,Set/Clear Pending Bit 908" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND907 ,Set/Clear Pending Bit 907" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND906 ,Set/Clear Pending Bit 906" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND905 ,Set/Clear Pending Bit 905" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND904 ,Set/Clear Pending Bit 904" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND903 ,Set/Clear Pending Bit 903" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND902 ,Set/Clear Pending Bit 902" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND901 ,Set/Clear Pending Bit 901" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND900 ,Set/Clear Pending Bit 900" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND899 ,Set/Clear Pending Bit 899" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND898 ,Set/Clear Pending Bit 898" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND897 ,Set/Clear Pending Bit 897" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND896 ,Set/Clear Pending Bit 896" "Not pending,Pending" else rgroup.long 0x0270++0x03 line.long 0x0 "GICD_SET/CLR_PENDR28,Interrupt Set/Clear Pending Register 28" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x1D) group.long 0x0274++0x03 line.long 0x0 "GICD_SET/CLR_PENDR29,Interrupt Set/Clear Pending Register 29" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND959 ,Set/Clear Pending Bit 959" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND958 ,Set/Clear Pending Bit 958" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND957 ,Set/Clear Pending Bit 957" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND956 ,Set/Clear Pending Bit 956" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND955 ,Set/Clear Pending Bit 955" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND954 ,Set/Clear Pending Bit 954" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND953 ,Set/Clear Pending Bit 953" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND952 ,Set/Clear Pending Bit 952" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND951 ,Set/Clear Pending Bit 951" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND950 ,Set/Clear Pending Bit 950" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND949 ,Set/Clear Pending Bit 949" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND948 ,Set/Clear Pending Bit 948" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND947 ,Set/Clear Pending Bit 947" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND946 ,Set/Clear Pending Bit 946" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND945 ,Set/Clear Pending Bit 945" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND944 ,Set/Clear Pending Bit 944" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND943 ,Set/Clear Pending Bit 943" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND942 ,Set/Clear Pending Bit 942" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND941 ,Set/Clear Pending Bit 941" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND940 ,Set/Clear Pending Bit 940" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND939 ,Set/Clear Pending Bit 939" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND938 ,Set/Clear Pending Bit 938" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND937 ,Set/Clear Pending Bit 937" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND936 ,Set/Clear Pending Bit 936" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND935 ,Set/Clear Pending Bit 935" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND934 ,Set/Clear Pending Bit 934" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND933 ,Set/Clear Pending Bit 933" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND932 ,Set/Clear Pending Bit 932" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND931 ,Set/Clear Pending Bit 931" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND930 ,Set/Clear Pending Bit 930" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND929 ,Set/Clear Pending Bit 929" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND928 ,Set/Clear Pending Bit 928" "Not pending,Pending" else rgroup.long 0x0274++0x03 line.long 0x0 "GICD_SET/CLR_PENDR29,Interrupt Set/Clear Pending Register 29" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x1E) group.long 0x0278++0x03 line.long 0x0 "GICD_SET/CLR_PENDR30,Interrupt Set/Clear Pending Register 30" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND991 ,Set/Clear Pending Bit 991" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND990 ,Set/Clear Pending Bit 990" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND989 ,Set/Clear Pending Bit 989" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND988 ,Set/Clear Pending Bit 988" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND987 ,Set/Clear Pending Bit 987" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND986 ,Set/Clear Pending Bit 986" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND985 ,Set/Clear Pending Bit 985" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND984 ,Set/Clear Pending Bit 984" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND983 ,Set/Clear Pending Bit 983" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND982 ,Set/Clear Pending Bit 982" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND981 ,Set/Clear Pending Bit 981" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND980 ,Set/Clear Pending Bit 980" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND979 ,Set/Clear Pending Bit 979" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND978 ,Set/Clear Pending Bit 978" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND977 ,Set/Clear Pending Bit 977" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND976 ,Set/Clear Pending Bit 976" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND975 ,Set/Clear Pending Bit 975" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND974 ,Set/Clear Pending Bit 974" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND973 ,Set/Clear Pending Bit 973" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND972 ,Set/Clear Pending Bit 972" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND971 ,Set/Clear Pending Bit 971" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND970 ,Set/Clear Pending Bit 970" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND969 ,Set/Clear Pending Bit 969" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND968 ,Set/Clear Pending Bit 968" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND967 ,Set/Clear Pending Bit 967" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND966 ,Set/Clear Pending Bit 966" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND965 ,Set/Clear Pending Bit 965" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND964 ,Set/Clear Pending Bit 964" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND963 ,Set/Clear Pending Bit 963" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND962 ,Set/Clear Pending Bit 962" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND961 ,Set/Clear Pending Bit 961" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND960 ,Set/Clear Pending Bit 960" "Not pending,Pending" else rgroup.long 0x0278++0x03 line.long 0x0 "GICD_SET/CLR_PENDR30,Interrupt Set/Clear Pending Register 30" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0xA0021000+0x04))&0x0000001F)==0x1F) group.long 0x027C++0x03 line.long 0x0 "GICD_SET/CLR_PENDR31,Interrupt Set/Clear Pending Register 31" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND1019 ,Set/Clear Pending Bit 1019" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND1018 ,Set/Clear Pending Bit 1018" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND1017 ,Set/Clear Pending Bit 1017" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND1016 ,Set/Clear Pending Bit 1016" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND1015 ,Set/Clear Pending Bit 1015" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND1014 ,Set/Clear Pending Bit 1014" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND1013 ,Set/Clear Pending Bit 1013" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND1012 ,Set/Clear Pending Bit 1012" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND1011 ,Set/Clear Pending Bit 1011" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND1010 ,Set/Clear Pending Bit 1010" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND1009 ,Set/Clear Pending Bit 1009" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND1008 ,Set/Clear Pending Bit 1008" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND1007 ,Set/Clear Pending Bit 1007" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND1006 ,Set/Clear Pending Bit 1006" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND1005 ,Set/Clear Pending Bit 1005" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND1004 ,Set/Clear Pending Bit 1004" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND1003 ,Set/Clear Pending Bit 1003" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND1002 ,Set/Clear Pending Bit 1002" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND1001 ,Set/Clear Pending Bit 1001" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND1000 ,Set/Clear Pending Bit 1000" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND999 ,Set/Clear Pending Bit 999" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND998 ,Set/Clear Pending Bit 998" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND997 ,Set/Clear Pending Bit 997" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND996 ,Set/Clear Pending Bit 996" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND995 ,Set/Clear Pending Bit 995" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND994 ,Set/Clear Pending Bit 994" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND993 ,Set/Clear Pending Bit 993" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND992 ,Set/Clear Pending Bit 992" "Not pending,Pending" else rgroup.long 0x027C++0x03 line.long 0x0 "GICD_SET/CLR_PENDR31,Interrupt Set/Clear Pending Register 31" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif tree.end width 24. tree "Set/Clear Active Registers" if (((per.l(ad:0xA0021000+0x08))&0xFF000000)==(0x0000000||0x1000000)) rgroup.long 0x0300++0x03 line.long 0x0 "GICD_ICDABR0,Active Status Register 0" bitfld.long 0x00 31. " ASB31 ,Active Status Bit 31" "Not active,Active" bitfld.long 0x00 30. " ASB30 ,Active Status Bit 30" "Not active,Active" bitfld.long 0x00 29. " ASB29 ,Active Status Bit 29" "Not active,Active" textline " " bitfld.long 0x00 28. " ASB28 ,Active Status Bit 28" "Not active,Active" bitfld.long 0x00 27. " ASB27 ,Active Status Bit 27" "Not active,Active" bitfld.long 0x00 26. " ASB26 ,Active Status Bit 26" "Not active,Active" textline " " bitfld.long 0x00 25. " ASB25 ,Active Status Bit 25" "Not active,Active" bitfld.long 0x00 24. " ASB24 ,Active Status Bit 24" "Not active,Active" bitfld.long 0x00 23. " ASB23 ,Active Status Bit 23" "Not active,Active" textline " " bitfld.long 0x00 22. " ASB22 ,Active Status Bit 22" "Not active,Active" bitfld.long 0x00 21. " ASB21 ,Active Status Bit 21" "Not active,Active" bitfld.long 0x00 20. " ASB20 ,Active Status Bit 20" "Not active,Active" textline " " bitfld.long 0x00 19. " ASB19 ,Active Status Bit 19" "Not active,Active" bitfld.long 0x00 18. " ASB18 ,Active Status Bit 18" "Not active,Active" bitfld.long 0x00 17. " ASB17 ,Active Status Bit 17" "Not active,Active" textline " " bitfld.long 0x00 16. " ASB16 ,Active Status Bit 16" "Not active,Active" bitfld.long 0x00 15. " ASB15 ,Active Status Bit 15" "Not active,Active" bitfld.long 0x00 14. " ASB14 ,Active Status Bit 14" "Not active,Active" textline " " bitfld.long 0x00 13. " ASB13 ,Active Status Bit 13" "Not active,Active" bitfld.long 0x00 12. " ASB12 ,Active Status Bit 12" "Not active,Active" bitfld.long 0x00 11. " ASB11 ,Active Status Bit 11" "Not active,Active" textline " " bitfld.long 0x00 10. " ASB10 ,Active Status Bit 10" "Not active,Active" bitfld.long 0x00 9. " ASB9 ,Active Status Bit 9" "Not active,Active" bitfld.long 0x00 8. " ASB8 ,Active Status Bit 8" "Not active,Active" textline " " bitfld.long 0x00 7. " ASB7 ,Active Status Bit 7" "Not active,Active" bitfld.long 0x00 6. " ASB6 ,Active Status Bit 6" "Not active,Active" bitfld.long 0x00 5. " ASB5 ,Active Status Bit 5" "Not active,Active" textline " " bitfld.long 0x00 4. " ASB4 ,Active Status Bit 4" "Not active,Active" bitfld.long 0x00 3. " ASB3 ,Active Status Bit 3" "Not active,Active" bitfld.long 0x00 2. " ASB2 ,Active Status Bit 2" "Not active,Active" textline " " bitfld.long 0x00 1. " ASB1 ,Active Status Bit 1" "Not active,Active" bitfld.long 0x00 0. " ASB0 ,Active Status Bit 0" "Not active,Active" if (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x01) rgroup.long 0x0304++0x03 line.long 0x0 "GICD_ICDABR1,Active Status Register 1" bitfld.long 0x00 31. " ASB63 ,Active Status Bit 63" "Not active,Active" bitfld.long 0x00 30. " ASB62 ,Active Status Bit 62" "Not active,Active" bitfld.long 0x00 29. " ASB61 ,Active Status Bit 61" "Not active,Active" textline " " bitfld.long 0x00 28. " ASB60 ,Active Status Bit 60" "Not active,Active" bitfld.long 0x00 27. " ASB59 ,Active Status Bit 59" "Not active,Active" bitfld.long 0x00 26. " ASB58 ,Active Status Bit 58" "Not active,Active" textline " " bitfld.long 0x00 25. " ASB57 ,Active Status Bit 57" "Not active,Active" bitfld.long 0x00 24. " ASB56 ,Active Status Bit 56" "Not active,Active" bitfld.long 0x00 23. " ASB55 ,Active Status Bit 55" "Not active,Active" textline " " bitfld.long 0x00 22. " ASB54 ,Active Status Bit 54" "Not active,Active" bitfld.long 0x00 21. " ASB53 ,Active Status Bit 53" "Not active,Active" bitfld.long 0x00 20. " ASB52 ,Active Status Bit 52" "Not active,Active" textline " " bitfld.long 0x00 19. " ASB51 ,Active Status Bit 51" "Not active,Active" bitfld.long 0x00 18. " ASB50 ,Active Status Bit 50" "Not active,Active" bitfld.long 0x00 17. " ASB49 ,Active Status Bit 49" "Not active,Active" textline " " bitfld.long 0x00 16. " ASB48 ,Active Status Bit 48" "Not active,Active" bitfld.long 0x00 15. " ASB47 ,Active Status Bit 47" "Not active,Active" bitfld.long 0x00 14. " ASB46 ,Active Status Bit 46" "Not active,Active" textline " " bitfld.long 0x00 13. " ASB45 ,Active Status Bit 45" "Not active,Active" bitfld.long 0x00 12. " ASB44 ,Active Status Bit 44" "Not active,Active" bitfld.long 0x00 11. " ASB43 ,Active Status Bit 43" "Not active,Active" textline " " bitfld.long 0x00 10. " ASB42 ,Active Status Bit 42" "Not active,Active" bitfld.long 0x00 9. " ASB41 ,Active Status Bit 41" "Not active,Active" bitfld.long 0x00 8. " ASB40 ,Active Status Bit 40" "Not active,Active" textline " " bitfld.long 0x00 7. " ASB39 ,Active Status Bit 39" "Not active,Active" bitfld.long 0x00 6. " ASB38 ,Active Status Bit 38" "Not active,Active" bitfld.long 0x00 5. " ASB37 ,Active Status Bit 37" "Not active,Active" textline " " bitfld.long 0x00 4. " ASB36 ,Active Status Bit 36" "Not active,Active" bitfld.long 0x00 3. " ASB35 ,Active Status Bit 35" "Not active,Active" bitfld.long 0x00 2. " ASB34 ,Active Status Bit 34" "Not active,Active" textline " " bitfld.long 0x00 1. " ASB33 ,Active Status Bit 33" "Not active,Active" bitfld.long 0x00 0. " ASB32 ,Active Status Bit 32" "Not active,Active" else rgroup.long 0x0304++0x03 line.long 0x0 "GICD_ICDABR1,Active Status Register 1" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x02) rgroup.long 0x0308++0x03 line.long 0x0 "GICD_ICDABR2,Active Status Register 2" bitfld.long 0x00 31. " ASB95 ,Active Status Bit 95" "Not active,Active" bitfld.long 0x00 30. " ASB94 ,Active Status Bit 94" "Not active,Active" bitfld.long 0x00 29. " ASB93 ,Active Status Bit 93" "Not active,Active" textline " " bitfld.long 0x00 28. " ASB92 ,Active Status Bit 92" "Not active,Active" bitfld.long 0x00 27. " ASB91 ,Active Status Bit 91" "Not active,Active" bitfld.long 0x00 26. " ASB90 ,Active Status Bit 90" "Not active,Active" textline " " bitfld.long 0x00 25. " ASB89 ,Active Status Bit 89" "Not active,Active" bitfld.long 0x00 24. " ASB88 ,Active Status Bit 88" "Not active,Active" bitfld.long 0x00 23. " ASB87 ,Active Status Bit 87" "Not active,Active" textline " " bitfld.long 0x00 22. " ASB86 ,Active Status Bit 86" "Not active,Active" bitfld.long 0x00 21. " ASB85 ,Active Status Bit 85" "Not active,Active" bitfld.long 0x00 20. " ASB84 ,Active Status Bit 84" "Not active,Active" textline " " bitfld.long 0x00 19. " ASB83 ,Active Status Bit 83" "Not active,Active" bitfld.long 0x00 18. " ASB82 ,Active Status Bit 82" "Not active,Active" bitfld.long 0x00 17. " ASB81 ,Active Status Bit 81" "Not active,Active" textline " " bitfld.long 0x00 16. " ASB80 ,Active Status Bit 80" "Not active,Active" bitfld.long 0x00 15. " ASB79 ,Active Status Bit 79" "Not active,Active" bitfld.long 0x00 14. " ASB78 ,Active Status Bit 78" "Not active,Active" textline " " bitfld.long 0x00 13. " ASB77 ,Active Status Bit 77" "Not active,Active" bitfld.long 0x00 12. " ASB76 ,Active Status Bit 76" "Not active,Active" bitfld.long 0x00 11. " ASB75 ,Active Status Bit 75" "Not active,Active" textline " " bitfld.long 0x00 10. " ASB74 ,Active Status Bit 74" "Not active,Active" bitfld.long 0x00 9. " ASB73 ,Active Status Bit 73" "Not active,Active" bitfld.long 0x00 8. " ASB72 ,Active Status Bit 72" "Not active,Active" textline " " bitfld.long 0x00 7. " ASB71 ,Active Status Bit 71" "Not active,Active" bitfld.long 0x00 6. " ASB70 ,Active Status Bit 70" "Not active,Active" bitfld.long 0x00 5. " ASB69 ,Active Status Bit 69" "Not active,Active" textline " " bitfld.long 0x00 4. " ASB68 ,Active Status Bit 68" "Not active,Active" bitfld.long 0x00 3. " ASB67 ,Active Status Bit 67" "Not active,Active" bitfld.long 0x00 2. " ASB66 ,Active Status Bit 66" "Not active,Active" textline " " bitfld.long 0x00 1. " ASB65 ,Active Status Bit 65" "Not active,Active" bitfld.long 0x00 0. " ASB64 ,Active Status Bit 64" "Not active,Active" else rgroup.long 0x0308++0x03 line.long 0x0 "GICD_ICDABR2,Active Status Register 2" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x03) rgroup.long 0x030C++0x03 line.long 0x0 "GICD_ICDABR3,Active Status Register 3" bitfld.long 0x00 31. " ASB127 ,Active Status Bit 127" "Not active,Active" bitfld.long 0x00 30. " ASB126 ,Active Status Bit 126" "Not active,Active" bitfld.long 0x00 29. " ASB125 ,Active Status Bit 125" "Not active,Active" textline " " bitfld.long 0x00 28. " ASB124 ,Active Status Bit 124" "Not active,Active" bitfld.long 0x00 27. " ASB123 ,Active Status Bit 123" "Not active,Active" bitfld.long 0x00 26. " ASB122 ,Active Status Bit 122" "Not active,Active" textline " " bitfld.long 0x00 25. " ASB121 ,Active Status Bit 121" "Not active,Active" bitfld.long 0x00 24. " ASB120 ,Active Status Bit 120" "Not active,Active" bitfld.long 0x00 23. " ASB119 ,Active Status Bit 119" "Not active,Active" textline " " bitfld.long 0x00 22. " ASB118 ,Active Status Bit 118" "Not active,Active" bitfld.long 0x00 21. " ASB117 ,Active Status Bit 117" "Not active,Active" bitfld.long 0x00 20. " ASB116 ,Active Status Bit 116" "Not active,Active" textline " " bitfld.long 0x00 19. " ASB115 ,Active Status Bit 115" "Not active,Active" bitfld.long 0x00 18. " ASB114 ,Active Status Bit 114" "Not active,Active" bitfld.long 0x00 17. " ASB113 ,Active Status Bit 113" "Not active,Active" textline " " bitfld.long 0x00 16. " ASB112 ,Active Status Bit 112" "Not active,Active" bitfld.long 0x00 15. " ASB111 ,Active Status Bit 111" "Not active,Active" bitfld.long 0x00 14. " ASB110 ,Active Status Bit 110" "Not active,Active" textline " " bitfld.long 0x00 13. " ASB109 ,Active Status Bit 109" "Not active,Active" bitfld.long 0x00 12. " ASB108 ,Active Status Bit 108" "Not active,Active" bitfld.long 0x00 11. " ASB107 ,Active Status Bit 107" "Not active,Active" textline " " bitfld.long 0x00 10. " ASB106 ,Active Status Bit 106" "Not active,Active" bitfld.long 0x00 9. " ASB105 ,Active Status Bit 105" "Not active,Active" bitfld.long 0x00 8. " ASB104 ,Active Status Bit 104" "Not active,Active" textline " " bitfld.long 0x00 7. " ASB103 ,Active Status Bit 103" "Not active,Active" bitfld.long 0x00 6. " ASB102 ,Active Status Bit 102" "Not active,Active" bitfld.long 0x00 5. " ASB101 ,Active Status Bit 101" "Not active,Active" textline " " bitfld.long 0x00 4. " ASB100 ,Active Status Bit 100" "Not active,Active" bitfld.long 0x00 3. " ASB99 ,Active Status Bit 99" "Not active,Active" bitfld.long 0x00 2. " ASB98 ,Active Status Bit 98" "Not active,Active" textline " " bitfld.long 0x00 1. " ASB97 ,Active Status Bit 97" "Not active,Active" bitfld.long 0x00 0. " ASB96 ,Active Status Bit 96" "Not active,Active" else rgroup.long 0x030C++0x03 line.long 0x0 "GICD_ICDABR3,Active Status Register 3" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x04) rgroup.long 0x0310++0x03 line.long 0x0 "GICD_ICDABR4,Active Status Register 4" bitfld.long 0x00 31. " ASB159 ,Active Status Bit 159" "Not active,Active" bitfld.long 0x00 30. " ASB158 ,Active Status Bit 158" "Not active,Active" bitfld.long 0x00 29. " ASB157 ,Active Status Bit 157" "Not active,Active" textline " " bitfld.long 0x00 28. " ASB156 ,Active Status Bit 156" "Not active,Active" bitfld.long 0x00 27. " ASB155 ,Active Status Bit 155" "Not active,Active" bitfld.long 0x00 26. " ASB154 ,Active Status Bit 154" "Not active,Active" textline " " bitfld.long 0x00 25. " ASB153 ,Active Status Bit 153" "Not active,Active" bitfld.long 0x00 24. " ASB152 ,Active Status Bit 152" "Not active,Active" bitfld.long 0x00 23. " ASB151 ,Active Status Bit 151" "Not active,Active" textline " " bitfld.long 0x00 22. " ASB150 ,Active Status Bit 150" "Not active,Active" bitfld.long 0x00 21. " ASB149 ,Active Status Bit 149" "Not active,Active" bitfld.long 0x00 20. " ASB148 ,Active Status Bit 148" "Not active,Active" textline " " bitfld.long 0x00 19. " ASB147 ,Active Status Bit 147" "Not active,Active" bitfld.long 0x00 18. " ASB146 ,Active Status Bit 146" "Not active,Active" bitfld.long 0x00 17. " ASB145 ,Active Status Bit 145" "Not active,Active" textline " " bitfld.long 0x00 16. " ASB144 ,Active Status Bit 144" "Not active,Active" bitfld.long 0x00 15. " ASB143 ,Active Status Bit 143" "Not active,Active" bitfld.long 0x00 14. " ASB142 ,Active Status Bit 142" "Not active,Active" textline " " bitfld.long 0x00 13. " ASB141 ,Active Status Bit 141" "Not active,Active" bitfld.long 0x00 12. " ASB140 ,Active Status Bit 140" "Not active,Active" bitfld.long 0x00 11. " ASB139 ,Active Status Bit 139" "Not active,Active" textline " " bitfld.long 0x00 10. " ASB138 ,Active Status Bit 138" "Not active,Active" bitfld.long 0x00 9. " ASB137 ,Active Status Bit 137" "Not active,Active" bitfld.long 0x00 8. " ASB136 ,Active Status Bit 136" "Not active,Active" textline " " bitfld.long 0x00 7. " ASB135 ,Active Status Bit 135" "Not active,Active" bitfld.long 0x00 6. " ASB134 ,Active Status Bit 134" "Not active,Active" bitfld.long 0x00 5. " ASB133 ,Active Status Bit 133" "Not active,Active" textline " " bitfld.long 0x00 4. " ASB132 ,Active Status Bit 132" "Not active,Active" bitfld.long 0x00 3. " ASB131 ,Active Status Bit 131" "Not active,Active" bitfld.long 0x00 2. " ASB130 ,Active Status Bit 130" "Not active,Active" textline " " bitfld.long 0x00 1. " ASB129 ,Active Status Bit 129" "Not active,Active" bitfld.long 0x00 0. " ASB128 ,Active Status Bit 128" "Not active,Active" else rgroup.long 0x0310++0x03 line.long 0x0 "GICD_ICDABR4,Active Status Register 4" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x05) rgroup.long 0x0314++0x03 line.long 0x0 "GICD_ICDABR5,Active Status Register 5" bitfld.long 0x00 31. " ASB191 ,Active Status Bit 191" "Not active,Active" bitfld.long 0x00 30. " ASB190 ,Active Status Bit 190" "Not active,Active" bitfld.long 0x00 29. " ASB189 ,Active Status Bit 189" "Not active,Active" textline " " bitfld.long 0x00 28. " ASB188 ,Active Status Bit 188" "Not active,Active" bitfld.long 0x00 27. " ASB187 ,Active Status Bit 187" "Not active,Active" bitfld.long 0x00 26. " ASB186 ,Active Status Bit 186" "Not active,Active" textline " " bitfld.long 0x00 25. " ASB185 ,Active Status Bit 185" "Not active,Active" bitfld.long 0x00 24. " ASB184 ,Active Status Bit 184" "Not active,Active" bitfld.long 0x00 23. " ASB183 ,Active Status Bit 183" "Not active,Active" textline " " bitfld.long 0x00 22. " ASB182 ,Active Status Bit 182" "Not active,Active" bitfld.long 0x00 21. " ASB181 ,Active Status Bit 181" "Not active,Active" bitfld.long 0x00 20. " ASB180 ,Active Status Bit 180" "Not active,Active" textline " " bitfld.long 0x00 19. " ASB179 ,Active Status Bit 179" "Not active,Active" bitfld.long 0x00 18. " ASB178 ,Active Status Bit 178" "Not active,Active" bitfld.long 0x00 17. " ASB177 ,Active Status Bit 177" "Not active,Active" textline " " bitfld.long 0x00 16. " ASB176 ,Active Status Bit 176" "Not active,Active" bitfld.long 0x00 15. " ASB175 ,Active Status Bit 175" "Not active,Active" bitfld.long 0x00 14. " ASB174 ,Active Status Bit 174" "Not active,Active" textline " " bitfld.long 0x00 13. " ASB173 ,Active Status Bit 173" "Not active,Active" bitfld.long 0x00 12. " ASB172 ,Active Status Bit 172" "Not active,Active" bitfld.long 0x00 11. " ASB171 ,Active Status Bit 171" "Not active,Active" textline " " bitfld.long 0x00 10. " ASB170 ,Active Status Bit 170" "Not active,Active" bitfld.long 0x00 9. " ASB169 ,Active Status Bit 169" "Not active,Active" bitfld.long 0x00 8. " ASB168 ,Active Status Bit 168" "Not active,Active" textline " " bitfld.long 0x00 7. " ASB167 ,Active Status Bit 167" "Not active,Active" bitfld.long 0x00 6. " ASB166 ,Active Status Bit 166" "Not active,Active" bitfld.long 0x00 5. " ASB165 ,Active Status Bit 165" "Not active,Active" textline " " bitfld.long 0x00 4. " ASB164 ,Active Status Bit 164" "Not active,Active" bitfld.long 0x00 3. " ASB163 ,Active Status Bit 163" "Not active,Active" bitfld.long 0x00 2. " ASB162 ,Active Status Bit 162" "Not active,Active" textline " " bitfld.long 0x00 1. " ASB161 ,Active Status Bit 161" "Not active,Active" bitfld.long 0x00 0. " ASB160 ,Active Status Bit 160" "Not active,Active" else rgroup.long 0x0314++0x03 line.long 0x0 "GICD_ICDABR5,Active Status Register 5" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x06) rgroup.long 0x0318++0x03 line.long 0x0 "GICD_ICDABR6,Active Status Register 6" bitfld.long 0x00 31. " ASB223 ,Active Status Bit 223" "Not active,Active" bitfld.long 0x00 30. " ASB222 ,Active Status Bit 222" "Not active,Active" bitfld.long 0x00 29. " ASB221 ,Active Status Bit 221" "Not active,Active" textline " " bitfld.long 0x00 28. " ASB220 ,Active Status Bit 220" "Not active,Active" bitfld.long 0x00 27. " ASB219 ,Active Status Bit 219" "Not active,Active" bitfld.long 0x00 26. " ASB218 ,Active Status Bit 218" "Not active,Active" textline " " bitfld.long 0x00 25. " ASB217 ,Active Status Bit 217" "Not active,Active" bitfld.long 0x00 24. " ASB216 ,Active Status Bit 216" "Not active,Active" bitfld.long 0x00 23. " ASB215 ,Active Status Bit 215" "Not active,Active" textline " " bitfld.long 0x00 22. " ASB214 ,Active Status Bit 214" "Not active,Active" bitfld.long 0x00 21. " ASB213 ,Active Status Bit 213" "Not active,Active" bitfld.long 0x00 20. " ASB212 ,Active Status Bit 212" "Not active,Active" textline " " bitfld.long 0x00 19. " ASB211 ,Active Status Bit 211" "Not active,Active" bitfld.long 0x00 18. " ASB210 ,Active Status Bit 210" "Not active,Active" bitfld.long 0x00 17. " ASB209 ,Active Status Bit 209" "Not active,Active" textline " " bitfld.long 0x00 16. " ASB208 ,Active Status Bit 208" "Not active,Active" bitfld.long 0x00 15. " ASB207 ,Active Status Bit 207" "Not active,Active" bitfld.long 0x00 14. " ASB206 ,Active Status Bit 206" "Not active,Active" textline " " bitfld.long 0x00 13. " ASB205 ,Active Status Bit 205" "Not active,Active" bitfld.long 0x00 12. " ASB204 ,Active Status Bit 204" "Not active,Active" bitfld.long 0x00 11. " ASB203 ,Active Status Bit 203" "Not active,Active" textline " " bitfld.long 0x00 10. " ASB202 ,Active Status Bit 202" "Not active,Active" bitfld.long 0x00 9. " ASB201 ,Active Status Bit 201" "Not active,Active" bitfld.long 0x00 8. " ASB200 ,Active Status Bit 200" "Not active,Active" textline " " bitfld.long 0x00 7. " ASB199 ,Active Status Bit 199" "Not active,Active" bitfld.long 0x00 6. " ASB198 ,Active Status Bit 198" "Not active,Active" bitfld.long 0x00 5. " ASB197 ,Active Status Bit 197" "Not active,Active" textline " " bitfld.long 0x00 4. " ASB196 ,Active Status Bit 196" "Not active,Active" bitfld.long 0x00 3. " ASB195 ,Active Status Bit 195" "Not active,Active" bitfld.long 0x00 2. " ASB194 ,Active Status Bit 194" "Not active,Active" textline " " bitfld.long 0x00 1. " ASB193 ,Active Status Bit 193" "Not active,Active" bitfld.long 0x00 0. " ASB192 ,Active Status Bit 192" "Not active,Active" else rgroup.long 0x0318++0x03 line.long 0x0 "GICD_ICDABR6,Active Status Register 6" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x07) rgroup.long 0x031C++0x03 line.long 0x0 "GICD_ICDABR7,Active Status Register 7" bitfld.long 0x00 31. " ASB255 ,Active Status Bit 255" "Not active,Active" bitfld.long 0x00 30. " ASB254 ,Active Status Bit 254" "Not active,Active" bitfld.long 0x00 29. " ASB253 ,Active Status Bit 253" "Not active,Active" textline " " bitfld.long 0x00 28. " ASB252 ,Active Status Bit 252" "Not active,Active" bitfld.long 0x00 27. " ASB251 ,Active Status Bit 251" "Not active,Active" bitfld.long 0x00 26. " ASB250 ,Active Status Bit 250" "Not active,Active" textline " " bitfld.long 0x00 25. " ASB249 ,Active Status Bit 249" "Not active,Active" bitfld.long 0x00 24. " ASB248 ,Active Status Bit 248" "Not active,Active" bitfld.long 0x00 23. " ASB247 ,Active Status Bit 247" "Not active,Active" textline " " bitfld.long 0x00 22. " ASB246 ,Active Status Bit 246" "Not active,Active" bitfld.long 0x00 21. " ASB245 ,Active Status Bit 245" "Not active,Active" bitfld.long 0x00 20. " ASB244 ,Active Status Bit 244" "Not active,Active" textline " " bitfld.long 0x00 19. " ASB243 ,Active Status Bit 243" "Not active,Active" bitfld.long 0x00 18. " ASB242 ,Active Status Bit 242" "Not active,Active" bitfld.long 0x00 17. " ASB241 ,Active Status Bit 241" "Not active,Active" textline " " bitfld.long 0x00 16. " ASB240 ,Active Status Bit 240" "Not active,Active" bitfld.long 0x00 15. " ASB239 ,Active Status Bit 239" "Not active,Active" bitfld.long 0x00 14. " ASB238 ,Active Status Bit 238" "Not active,Active" textline " " bitfld.long 0x00 13. " ASB237 ,Active Status Bit 237" "Not active,Active" bitfld.long 0x00 12. " ASB236 ,Active Status Bit 236" "Not active,Active" bitfld.long 0x00 11. " ASB235 ,Active Status Bit 235" "Not active,Active" textline " " bitfld.long 0x00 10. " ASB234 ,Active Status Bit 234" "Not active,Active" bitfld.long 0x00 9. " ASB233 ,Active Status Bit 233" "Not active,Active" bitfld.long 0x00 8. " ASB232 ,Active Status Bit 232" "Not active,Active" textline " " bitfld.long 0x00 7. " ASB231 ,Active Status Bit 231" "Not active,Active" bitfld.long 0x00 6. " ASB230 ,Active Status Bit 230" "Not active,Active" bitfld.long 0x00 5. " ASB229 ,Active Status Bit 229" "Not active,Active" textline " " bitfld.long 0x00 4. " ASB228 ,Active Status Bit 228" "Not active,Active" bitfld.long 0x00 3. " ASB227 ,Active Status Bit 227" "Not active,Active" bitfld.long 0x00 2. " ASB226 ,Active Status Bit 226" "Not active,Active" textline " " bitfld.long 0x00 1. " ASB225 ,Active Status Bit 225" "Not active,Active" bitfld.long 0x00 0. " ASB224 ,Active Status Bit 224" "Not active,Active" else rgroup.long 0x031C++0x03 line.long 0x0 "GICD_ICDABR7,Active Status Register 7" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x08) rgroup.long 0x0320++0x03 line.long 0x0 "GICD_ICDABR8,Active Status Register 8" bitfld.long 0x00 31. " ASB287 ,Active Status Bit 287" "Not active,Active" bitfld.long 0x00 30. " ASB286 ,Active Status Bit 286" "Not active,Active" bitfld.long 0x00 29. " ASB285 ,Active Status Bit 285" "Not active,Active" textline " " bitfld.long 0x00 28. " ASB284 ,Active Status Bit 284" "Not active,Active" bitfld.long 0x00 27. " ASB283 ,Active Status Bit 283" "Not active,Active" bitfld.long 0x00 26. " ASB282 ,Active Status Bit 282" "Not active,Active" textline " " bitfld.long 0x00 25. " ASB281 ,Active Status Bit 281" "Not active,Active" bitfld.long 0x00 24. " ASB280 ,Active Status Bit 280" "Not active,Active" bitfld.long 0x00 23. " ASB279 ,Active Status Bit 279" "Not active,Active" textline " " bitfld.long 0x00 22. " ASB278 ,Active Status Bit 278" "Not active,Active" bitfld.long 0x00 21. " ASB277 ,Active Status Bit 277" "Not active,Active" bitfld.long 0x00 20. " ASB276 ,Active Status Bit 276" "Not active,Active" textline " " bitfld.long 0x00 19. " ASB275 ,Active Status Bit 275" "Not active,Active" bitfld.long 0x00 18. " ASB274 ,Active Status Bit 274" "Not active,Active" bitfld.long 0x00 17. " ASB273 ,Active Status Bit 273" "Not active,Active" textline " " bitfld.long 0x00 16. " ASB272 ,Active Status Bit 272" "Not active,Active" bitfld.long 0x00 15. " ASB271 ,Active Status Bit 271" "Not active,Active" bitfld.long 0x00 14. " ASB270 ,Active Status Bit 270" "Not active,Active" textline " " bitfld.long 0x00 13. " ASB269 ,Active Status Bit 269" "Not active,Active" bitfld.long 0x00 12. " ASB268 ,Active Status Bit 268" "Not active,Active" bitfld.long 0x00 11. " ASB267 ,Active Status Bit 267" "Not active,Active" textline " " bitfld.long 0x00 10. " ASB266 ,Active Status Bit 266" "Not active,Active" bitfld.long 0x00 9. " ASB265 ,Active Status Bit 265" "Not active,Active" bitfld.long 0x00 8. " ASB264 ,Active Status Bit 264" "Not active,Active" textline " " bitfld.long 0x00 7. " ASB263 ,Active Status Bit 263" "Not active,Active" bitfld.long 0x00 6. " ASB262 ,Active Status Bit 262" "Not active,Active" bitfld.long 0x00 5. " ASB261 ,Active Status Bit 261" "Not active,Active" textline " " bitfld.long 0x00 4. " ASB260 ,Active Status Bit 260" "Not active,Active" bitfld.long 0x00 3. " ASB259 ,Active Status Bit 259" "Not active,Active" bitfld.long 0x00 2. " ASB258 ,Active Status Bit 258" "Not active,Active" textline " " bitfld.long 0x00 1. " ASB257 ,Active Status Bit 257" "Not active,Active" bitfld.long 0x00 0. " ASB256 ,Active Status Bit 256" "Not active,Active" else rgroup.long 0x0320++0x03 line.long 0x0 "GICD_ICDABR8,Active Status Register 8" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x09) rgroup.long 0x0324++0x03 line.long 0x0 "GICD_ICDABR9,Active Status Register 9" bitfld.long 0x00 31. " ASB319 ,Active Status Bit 319" "Not active,Active" bitfld.long 0x00 30. " ASB318 ,Active Status Bit 318" "Not active,Active" bitfld.long 0x00 29. " ASB317 ,Active Status Bit 317" "Not active,Active" textline " " bitfld.long 0x00 28. " ASB316 ,Active Status Bit 316" "Not active,Active" bitfld.long 0x00 27. " ASB315 ,Active Status Bit 315" "Not active,Active" bitfld.long 0x00 26. " ASB314 ,Active Status Bit 314" "Not active,Active" textline " " bitfld.long 0x00 25. " ASB313 ,Active Status Bit 313" "Not active,Active" bitfld.long 0x00 24. " ASB312 ,Active Status Bit 312" "Not active,Active" bitfld.long 0x00 23. " ASB311 ,Active Status Bit 311" "Not active,Active" textline " " bitfld.long 0x00 22. " ASB310 ,Active Status Bit 310" "Not active,Active" bitfld.long 0x00 21. " ASB309 ,Active Status Bit 309" "Not active,Active" bitfld.long 0x00 20. " ASB308 ,Active Status Bit 308" "Not active,Active" textline " " bitfld.long 0x00 19. " ASB307 ,Active Status Bit 307" "Not active,Active" bitfld.long 0x00 18. " ASB306 ,Active Status Bit 306" "Not active,Active" bitfld.long 0x00 17. " ASB305 ,Active Status Bit 305" "Not active,Active" textline " " bitfld.long 0x00 16. " ASB304 ,Active Status Bit 304" "Not active,Active" bitfld.long 0x00 15. " ASB303 ,Active Status Bit 303" "Not active,Active" bitfld.long 0x00 14. " ASB302 ,Active Status Bit 302" "Not active,Active" textline " " bitfld.long 0x00 13. " ASB301 ,Active Status Bit 301" "Not active,Active" bitfld.long 0x00 12. " ASB300 ,Active Status Bit 300" "Not active,Active" bitfld.long 0x00 11. " ASB299 ,Active Status Bit 299" "Not active,Active" textline " " bitfld.long 0x00 10. " ASB298 ,Active Status Bit 298" "Not active,Active" bitfld.long 0x00 9. " ASB297 ,Active Status Bit 297" "Not active,Active" bitfld.long 0x00 8. " ASB296 ,Active Status Bit 296" "Not active,Active" textline " " bitfld.long 0x00 7. " ASB295 ,Active Status Bit 295" "Not active,Active" bitfld.long 0x00 6. " ASB294 ,Active Status Bit 294" "Not active,Active" bitfld.long 0x00 5. " ASB293 ,Active Status Bit 293" "Not active,Active" textline " " bitfld.long 0x00 4. " ASB292 ,Active Status Bit 292" "Not active,Active" bitfld.long 0x00 3. " ASB291 ,Active Status Bit 291" "Not active,Active" bitfld.long 0x00 2. " ASB290 ,Active Status Bit 290" "Not active,Active" textline " " bitfld.long 0x00 1. " ASB289 ,Active Status Bit 289" "Not active,Active" bitfld.long 0x00 0. " ASB288 ,Active Status Bit 288" "Not active,Active" else rgroup.long 0x0324++0x03 line.long 0x0 "GICD_ICDABR9,Active Status Register 9" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x0A) rgroup.long 0x0328++0x03 line.long 0x0 "GICD_ICDABR10,Active Status Register 10" bitfld.long 0x00 31. " ASB351 ,Active Status Bit 351" "Not active,Active" bitfld.long 0x00 30. " ASB350 ,Active Status Bit 350" "Not active,Active" bitfld.long 0x00 29. " ASB349 ,Active Status Bit 349" "Not active,Active" textline " " bitfld.long 0x00 28. " ASB348 ,Active Status Bit 348" "Not active,Active" bitfld.long 0x00 27. " ASB347 ,Active Status Bit 347" "Not active,Active" bitfld.long 0x00 26. " ASB346 ,Active Status Bit 346" "Not active,Active" textline " " bitfld.long 0x00 25. " ASB345 ,Active Status Bit 345" "Not active,Active" bitfld.long 0x00 24. " ASB344 ,Active Status Bit 344" "Not active,Active" bitfld.long 0x00 23. " ASB343 ,Active Status Bit 343" "Not active,Active" textline " " bitfld.long 0x00 22. " ASB342 ,Active Status Bit 342" "Not active,Active" bitfld.long 0x00 21. " ASB341 ,Active Status Bit 341" "Not active,Active" bitfld.long 0x00 20. " ASB340 ,Active Status Bit 340" "Not active,Active" textline " " bitfld.long 0x00 19. " ASB339 ,Active Status Bit 339" "Not active,Active" bitfld.long 0x00 18. " ASB338 ,Active Status Bit 338" "Not active,Active" bitfld.long 0x00 17. " ASB337 ,Active Status Bit 337" "Not active,Active" textline " " bitfld.long 0x00 16. " ASB336 ,Active Status Bit 336" "Not active,Active" bitfld.long 0x00 15. " ASB335 ,Active Status Bit 335" "Not active,Active" bitfld.long 0x00 14. " ASB334 ,Active Status Bit 334" "Not active,Active" textline " " bitfld.long 0x00 13. " ASB333 ,Active Status Bit 333" "Not active,Active" bitfld.long 0x00 12. " ASB332 ,Active Status Bit 332" "Not active,Active" bitfld.long 0x00 11. " ASB331 ,Active Status Bit 331" "Not active,Active" textline " " bitfld.long 0x00 10. " ASB330 ,Active Status Bit 330" "Not active,Active" bitfld.long 0x00 9. " ASB329 ,Active Status Bit 329" "Not active,Active" bitfld.long 0x00 8. " ASB328 ,Active Status Bit 328" "Not active,Active" textline " " bitfld.long 0x00 7. " ASB327 ,Active Status Bit 327" "Not active,Active" bitfld.long 0x00 6. " ASB326 ,Active Status Bit 326" "Not active,Active" bitfld.long 0x00 5. " ASB325 ,Active Status Bit 325" "Not active,Active" textline " " bitfld.long 0x00 4. " ASB324 ,Active Status Bit 324" "Not active,Active" bitfld.long 0x00 3. " ASB323 ,Active Status Bit 323" "Not active,Active" bitfld.long 0x00 2. " ASB322 ,Active Status Bit 322" "Not active,Active" textline " " bitfld.long 0x00 1. " ASB321 ,Active Status Bit 321" "Not active,Active" bitfld.long 0x00 0. " ASB320 ,Active Status Bit 320" "Not active,Active" else rgroup.long 0x0328++0x03 line.long 0x0 "GICD_ICDABR10,Active Status Register 10" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x0B) rgroup.long 0x032C++0x03 line.long 0x0 "GICD_ICDABR11,Active Status Register 11" bitfld.long 0x00 31. " ASB383 ,Active Status Bit 383" "Not active,Active" bitfld.long 0x00 30. " ASB382 ,Active Status Bit 382" "Not active,Active" bitfld.long 0x00 29. " ASB381 ,Active Status Bit 381" "Not active,Active" textline " " bitfld.long 0x00 28. " ASB380 ,Active Status Bit 380" "Not active,Active" bitfld.long 0x00 27. " ASB379 ,Active Status Bit 379" "Not active,Active" bitfld.long 0x00 26. " ASB378 ,Active Status Bit 378" "Not active,Active" textline " " bitfld.long 0x00 25. " ASB377 ,Active Status Bit 377" "Not active,Active" bitfld.long 0x00 24. " ASB376 ,Active Status Bit 376" "Not active,Active" bitfld.long 0x00 23. " ASB375 ,Active Status Bit 375" "Not active,Active" textline " " bitfld.long 0x00 22. " ASB374 ,Active Status Bit 374" "Not active,Active" bitfld.long 0x00 21. " ASB373 ,Active Status Bit 373" "Not active,Active" bitfld.long 0x00 20. " ASB372 ,Active Status Bit 372" "Not active,Active" textline " " bitfld.long 0x00 19. " ASB371 ,Active Status Bit 371" "Not active,Active" bitfld.long 0x00 18. " ASB370 ,Active Status Bit 370" "Not active,Active" bitfld.long 0x00 17. " ASB369 ,Active Status Bit 369" "Not active,Active" textline " " bitfld.long 0x00 16. " ASB368 ,Active Status Bit 368" "Not active,Active" bitfld.long 0x00 15. " ASB367 ,Active Status Bit 367" "Not active,Active" bitfld.long 0x00 14. " ASB366 ,Active Status Bit 366" "Not active,Active" textline " " bitfld.long 0x00 13. " ASB365 ,Active Status Bit 365" "Not active,Active" bitfld.long 0x00 12. " ASB364 ,Active Status Bit 364" "Not active,Active" bitfld.long 0x00 11. " ASB363 ,Active Status Bit 363" "Not active,Active" textline " " bitfld.long 0x00 10. " ASB362 ,Active Status Bit 362" "Not active,Active" bitfld.long 0x00 9. " ASB361 ,Active Status Bit 361" "Not active,Active" bitfld.long 0x00 8. " ASB360 ,Active Status Bit 360" "Not active,Active" textline " " bitfld.long 0x00 7. " ASB359 ,Active Status Bit 359" "Not active,Active" bitfld.long 0x00 6. " ASB358 ,Active Status Bit 358" "Not active,Active" bitfld.long 0x00 5. " ASB357 ,Active Status Bit 357" "Not active,Active" textline " " bitfld.long 0x00 4. " ASB356 ,Active Status Bit 356" "Not active,Active" bitfld.long 0x00 3. " ASB355 ,Active Status Bit 355" "Not active,Active" bitfld.long 0x00 2. " ASB354 ,Active Status Bit 354" "Not active,Active" textline " " bitfld.long 0x00 1. " ASB353 ,Active Status Bit 353" "Not active,Active" bitfld.long 0x00 0. " ASB352 ,Active Status Bit 352" "Not active,Active" else rgroup.long 0x032C++0x03 line.long 0x0 "GICD_ICDABR11,Active Status Register 11" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x0C) rgroup.long 0x0330++0x03 line.long 0x0 "GICD_ICDABR12,Active Status Register 12" bitfld.long 0x00 31. " ASB415 ,Active Status Bit 415" "Not active,Active" bitfld.long 0x00 30. " ASB414 ,Active Status Bit 414" "Not active,Active" bitfld.long 0x00 29. " ASB413 ,Active Status Bit 413" "Not active,Active" textline " " bitfld.long 0x00 28. " ASB412 ,Active Status Bit 412" "Not active,Active" bitfld.long 0x00 27. " ASB411 ,Active Status Bit 411" "Not active,Active" bitfld.long 0x00 26. " ASB410 ,Active Status Bit 410" "Not active,Active" textline " " bitfld.long 0x00 25. " ASB409 ,Active Status Bit 409" "Not active,Active" bitfld.long 0x00 24. " ASB408 ,Active Status Bit 408" "Not active,Active" bitfld.long 0x00 23. " ASB407 ,Active Status Bit 407" "Not active,Active" textline " " bitfld.long 0x00 22. " ASB406 ,Active Status Bit 406" "Not active,Active" bitfld.long 0x00 21. " ASB405 ,Active Status Bit 405" "Not active,Active" bitfld.long 0x00 20. " ASB404 ,Active Status Bit 404" "Not active,Active" textline " " bitfld.long 0x00 19. " ASB403 ,Active Status Bit 403" "Not active,Active" bitfld.long 0x00 18. " ASB402 ,Active Status Bit 402" "Not active,Active" bitfld.long 0x00 17. " ASB401 ,Active Status Bit 401" "Not active,Active" textline " " bitfld.long 0x00 16. " ASB400 ,Active Status Bit 400" "Not active,Active" bitfld.long 0x00 15. " ASB399 ,Active Status Bit 399" "Not active,Active" bitfld.long 0x00 14. " ASB398 ,Active Status Bit 398" "Not active,Active" textline " " bitfld.long 0x00 13. " ASB397 ,Active Status Bit 397" "Not active,Active" bitfld.long 0x00 12. " ASB396 ,Active Status Bit 396" "Not active,Active" bitfld.long 0x00 11. " ASB395 ,Active Status Bit 395" "Not active,Active" textline " " bitfld.long 0x00 10. " ASB394 ,Active Status Bit 394" "Not active,Active" bitfld.long 0x00 9. " ASB393 ,Active Status Bit 393" "Not active,Active" bitfld.long 0x00 8. " ASB392 ,Active Status Bit 392" "Not active,Active" textline " " bitfld.long 0x00 7. " ASB391 ,Active Status Bit 391" "Not active,Active" bitfld.long 0x00 6. " ASB390 ,Active Status Bit 390" "Not active,Active" bitfld.long 0x00 5. " ASB389 ,Active Status Bit 389" "Not active,Active" textline " " bitfld.long 0x00 4. " ASB388 ,Active Status Bit 388" "Not active,Active" bitfld.long 0x00 3. " ASB387 ,Active Status Bit 387" "Not active,Active" bitfld.long 0x00 2. " ASB386 ,Active Status Bit 386" "Not active,Active" textline " " bitfld.long 0x00 1. " ASB385 ,Active Status Bit 385" "Not active,Active" bitfld.long 0x00 0. " ASB384 ,Active Status Bit 384" "Not active,Active" else rgroup.long 0x0330++0x03 line.long 0x0 "GICD_ICDABR12,Active Status Register 12" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x0D) rgroup.long 0x0334++0x03 line.long 0x0 "GICD_ICDABR13,Active Status Register 13" bitfld.long 0x00 31. " ASB447 ,Active Status Bit 447" "Not active,Active" bitfld.long 0x00 30. " ASB446 ,Active Status Bit 446" "Not active,Active" bitfld.long 0x00 29. " ASB445 ,Active Status Bit 445" "Not active,Active" textline " " bitfld.long 0x00 28. " ASB444 ,Active Status Bit 444" "Not active,Active" bitfld.long 0x00 27. " ASB443 ,Active Status Bit 443" "Not active,Active" bitfld.long 0x00 26. " ASB442 ,Active Status Bit 442" "Not active,Active" textline " " bitfld.long 0x00 25. " ASB441 ,Active Status Bit 441" "Not active,Active" bitfld.long 0x00 24. " ASB440 ,Active Status Bit 440" "Not active,Active" bitfld.long 0x00 23. " ASB439 ,Active Status Bit 439" "Not active,Active" textline " " bitfld.long 0x00 22. " ASB438 ,Active Status Bit 438" "Not active,Active" bitfld.long 0x00 21. " ASB437 ,Active Status Bit 437" "Not active,Active" bitfld.long 0x00 20. " ASB436 ,Active Status Bit 436" "Not active,Active" textline " " bitfld.long 0x00 19. " ASB435 ,Active Status Bit 435" "Not active,Active" bitfld.long 0x00 18. " ASB434 ,Active Status Bit 434" "Not active,Active" bitfld.long 0x00 17. " ASB433 ,Active Status Bit 433" "Not active,Active" textline " " bitfld.long 0x00 16. " ASB432 ,Active Status Bit 432" "Not active,Active" bitfld.long 0x00 15. " ASB431 ,Active Status Bit 431" "Not active,Active" bitfld.long 0x00 14. " ASB430 ,Active Status Bit 430" "Not active,Active" textline " " bitfld.long 0x00 13. " ASB429 ,Active Status Bit 429" "Not active,Active" bitfld.long 0x00 12. " ASB428 ,Active Status Bit 428" "Not active,Active" bitfld.long 0x00 11. " ASB427 ,Active Status Bit 427" "Not active,Active" textline " " bitfld.long 0x00 10. " ASB426 ,Active Status Bit 426" "Not active,Active" bitfld.long 0x00 9. " ASB425 ,Active Status Bit 425" "Not active,Active" bitfld.long 0x00 8. " ASB424 ,Active Status Bit 424" "Not active,Active" textline " " bitfld.long 0x00 7. " ASB423 ,Active Status Bit 423" "Not active,Active" bitfld.long 0x00 6. " ASB422 ,Active Status Bit 422" "Not active,Active" bitfld.long 0x00 5. " ASB421 ,Active Status Bit 421" "Not active,Active" textline " " bitfld.long 0x00 4. " ASB420 ,Active Status Bit 420" "Not active,Active" bitfld.long 0x00 3. " ASB419 ,Active Status Bit 419" "Not active,Active" bitfld.long 0x00 2. " ASB418 ,Active Status Bit 418" "Not active,Active" textline " " bitfld.long 0x00 1. " ASB417 ,Active Status Bit 417" "Not active,Active" bitfld.long 0x00 0. " ASB416 ,Active Status Bit 416" "Not active,Active" else rgroup.long 0x0334++0x03 line.long 0x0 "GICD_ICDABR13,Active Status Register 13" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x0E) rgroup.long 0x0338++0x03 line.long 0x0 "GICD_ICDABR14,Active Status Register 14" bitfld.long 0x00 31. " ASB479 ,Active Status Bit 479" "Not active,Active" bitfld.long 0x00 30. " ASB478 ,Active Status Bit 478" "Not active,Active" bitfld.long 0x00 29. " ASB477 ,Active Status Bit 477" "Not active,Active" textline " " bitfld.long 0x00 28. " ASB476 ,Active Status Bit 476" "Not active,Active" bitfld.long 0x00 27. " ASB475 ,Active Status Bit 475" "Not active,Active" bitfld.long 0x00 26. " ASB474 ,Active Status Bit 474" "Not active,Active" textline " " bitfld.long 0x00 25. " ASB473 ,Active Status Bit 473" "Not active,Active" bitfld.long 0x00 24. " ASB472 ,Active Status Bit 472" "Not active,Active" bitfld.long 0x00 23. " ASB471 ,Active Status Bit 471" "Not active,Active" textline " " bitfld.long 0x00 22. " ASB470 ,Active Status Bit 470" "Not active,Active" bitfld.long 0x00 21. " ASB469 ,Active Status Bit 469" "Not active,Active" bitfld.long 0x00 20. " ASB468 ,Active Status Bit 468" "Not active,Active" textline " " bitfld.long 0x00 19. " ASB467 ,Active Status Bit 467" "Not active,Active" bitfld.long 0x00 18. " ASB466 ,Active Status Bit 466" "Not active,Active" bitfld.long 0x00 17. " ASB465 ,Active Status Bit 465" "Not active,Active" textline " " bitfld.long 0x00 16. " ASB464 ,Active Status Bit 464" "Not active,Active" bitfld.long 0x00 15. " ASB463 ,Active Status Bit 463" "Not active,Active" bitfld.long 0x00 14. " ASB462 ,Active Status Bit 462" "Not active,Active" textline " " bitfld.long 0x00 13. " ASB461 ,Active Status Bit 461" "Not active,Active" bitfld.long 0x00 12. " ASB460 ,Active Status Bit 460" "Not active,Active" bitfld.long 0x00 11. " ASB459 ,Active Status Bit 459" "Not active,Active" textline " " bitfld.long 0x00 10. " ASB458 ,Active Status Bit 458" "Not active,Active" bitfld.long 0x00 9. " ASB457 ,Active Status Bit 457" "Not active,Active" bitfld.long 0x00 8. " ASB456 ,Active Status Bit 456" "Not active,Active" textline " " bitfld.long 0x00 7. " ASB455 ,Active Status Bit 455" "Not active,Active" bitfld.long 0x00 6. " ASB454 ,Active Status Bit 454" "Not active,Active" bitfld.long 0x00 5. " ASB453 ,Active Status Bit 453" "Not active,Active" textline " " bitfld.long 0x00 4. " ASB452 ,Active Status Bit 452" "Not active,Active" bitfld.long 0x00 3. " ASB451 ,Active Status Bit 451" "Not active,Active" bitfld.long 0x00 2. " ASB450 ,Active Status Bit 450" "Not active,Active" textline " " bitfld.long 0x00 1. " ASB449 ,Active Status Bit 449" "Not active,Active" bitfld.long 0x00 0. " ASB448 ,Active Status Bit 448" "Not active,Active" else rgroup.long 0x0338++0x03 line.long 0x0 "GICD_ICDABR14,Active Status Register 14" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x0F) rgroup.long 0x033C++0x03 line.long 0x0 "GICD_ICDABR15,Active Status Register 15" bitfld.long 0x00 31. " ASB511 ,Active Status Bit 511" "Not active,Active" bitfld.long 0x00 30. " ASB510 ,Active Status Bit 510" "Not active,Active" bitfld.long 0x00 29. " ASB509 ,Active Status Bit 509" "Not active,Active" textline " " bitfld.long 0x00 28. " ASB508 ,Active Status Bit 508" "Not active,Active" bitfld.long 0x00 27. " ASB507 ,Active Status Bit 507" "Not active,Active" bitfld.long 0x00 26. " ASB506 ,Active Status Bit 506" "Not active,Active" textline " " bitfld.long 0x00 25. " ASB505 ,Active Status Bit 505" "Not active,Active" bitfld.long 0x00 24. " ASB504 ,Active Status Bit 504" "Not active,Active" bitfld.long 0x00 23. " ASB503 ,Active Status Bit 503" "Not active,Active" textline " " bitfld.long 0x00 22. " ASB502 ,Active Status Bit 502" "Not active,Active" bitfld.long 0x00 21. " ASB501 ,Active Status Bit 501" "Not active,Active" bitfld.long 0x00 20. " ASB500 ,Active Status Bit 500" "Not active,Active" textline " " bitfld.long 0x00 19. " ASB499 ,Active Status Bit 499" "Not active,Active" bitfld.long 0x00 18. " ASB498 ,Active Status Bit 498" "Not active,Active" bitfld.long 0x00 17. " ASB497 ,Active Status Bit 497" "Not active,Active" textline " " bitfld.long 0x00 16. " ASB496 ,Active Status Bit 496" "Not active,Active" bitfld.long 0x00 15. " ASB495 ,Active Status Bit 495" "Not active,Active" bitfld.long 0x00 14. " ASB494 ,Active Status Bit 494" "Not active,Active" textline " " bitfld.long 0x00 13. " ASB493 ,Active Status Bit 493" "Not active,Active" bitfld.long 0x00 12. " ASB492 ,Active Status Bit 492" "Not active,Active" bitfld.long 0x00 11. " ASB491 ,Active Status Bit 491" "Not active,Active" textline " " bitfld.long 0x00 10. " ASB490 ,Active Status Bit 490" "Not active,Active" bitfld.long 0x00 9. " ASB489 ,Active Status Bit 489" "Not active,Active" bitfld.long 0x00 8. " ASB488 ,Active Status Bit 488" "Not active,Active" textline " " bitfld.long 0x00 7. " ASB487 ,Active Status Bit 487" "Not active,Active" bitfld.long 0x00 6. " ASB486 ,Active Status Bit 486" "Not active,Active" bitfld.long 0x00 5. " ASB485 ,Active Status Bit 485" "Not active,Active" textline " " bitfld.long 0x00 4. " ASB484 ,Active Status Bit 484" "Not active,Active" bitfld.long 0x00 3. " ASB483 ,Active Status Bit 483" "Not active,Active" bitfld.long 0x00 2. " ASB482 ,Active Status Bit 482" "Not active,Active" textline " " bitfld.long 0x00 1. " ASB481 ,Active Status Bit 481" "Not active,Active" bitfld.long 0x00 0. " ASB480 ,Active Status Bit 480" "Not active,Active" else rgroup.long 0x033C++0x03 line.long 0x0 "GICD_ICDABR15,Active Status Register 15" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x10) rgroup.long 0x0340++0x03 line.long 0x0 "GICD_ICDABR16,Active Status Register 16" bitfld.long 0x00 31. " ASB543 ,Active Status Bit 543" "Not active,Active" bitfld.long 0x00 30. " ASB542 ,Active Status Bit 542" "Not active,Active" bitfld.long 0x00 29. " ASB541 ,Active Status Bit 541" "Not active,Active" textline " " bitfld.long 0x00 28. " ASB540 ,Active Status Bit 540" "Not active,Active" bitfld.long 0x00 27. " ASB539 ,Active Status Bit 539" "Not active,Active" bitfld.long 0x00 26. " ASB538 ,Active Status Bit 538" "Not active,Active" textline " " bitfld.long 0x00 25. " ASB537 ,Active Status Bit 537" "Not active,Active" bitfld.long 0x00 24. " ASB536 ,Active Status Bit 536" "Not active,Active" bitfld.long 0x00 23. " ASB535 ,Active Status Bit 535" "Not active,Active" textline " " bitfld.long 0x00 22. " ASB534 ,Active Status Bit 534" "Not active,Active" bitfld.long 0x00 21. " ASB533 ,Active Status Bit 533" "Not active,Active" bitfld.long 0x00 20. " ASB532 ,Active Status Bit 532" "Not active,Active" textline " " bitfld.long 0x00 19. " ASB531 ,Active Status Bit 531" "Not active,Active" bitfld.long 0x00 18. " ASB530 ,Active Status Bit 530" "Not active,Active" bitfld.long 0x00 17. " ASB529 ,Active Status Bit 529" "Not active,Active" textline " " bitfld.long 0x00 16. " ASB528 ,Active Status Bit 528" "Not active,Active" bitfld.long 0x00 15. " ASB527 ,Active Status Bit 527" "Not active,Active" bitfld.long 0x00 14. " ASB526 ,Active Status Bit 526" "Not active,Active" textline " " bitfld.long 0x00 13. " ASB525 ,Active Status Bit 525" "Not active,Active" bitfld.long 0x00 12. " ASB524 ,Active Status Bit 524" "Not active,Active" bitfld.long 0x00 11. " ASB523 ,Active Status Bit 523" "Not active,Active" textline " " bitfld.long 0x00 10. " ASB522 ,Active Status Bit 522" "Not active,Active" bitfld.long 0x00 9. " ASB521 ,Active Status Bit 521" "Not active,Active" bitfld.long 0x00 8. " ASB520 ,Active Status Bit 520" "Not active,Active" textline " " bitfld.long 0x00 7. " ASB519 ,Active Status Bit 519" "Not active,Active" bitfld.long 0x00 6. " ASB518 ,Active Status Bit 518" "Not active,Active" bitfld.long 0x00 5. " ASB517 ,Active Status Bit 517" "Not active,Active" textline " " bitfld.long 0x00 4. " ASB516 ,Active Status Bit 516" "Not active,Active" bitfld.long 0x00 3. " ASB515 ,Active Status Bit 515" "Not active,Active" bitfld.long 0x00 2. " ASB514 ,Active Status Bit 514" "Not active,Active" textline " " bitfld.long 0x00 1. " ASB513 ,Active Status Bit 513" "Not active,Active" bitfld.long 0x00 0. " ASB512 ,Active Status Bit 512" "Not active,Active" else rgroup.long 0x0340++0x03 line.long 0x0 "GICD_ICDABR16,Active Status Register 16" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x11) rgroup.long 0x0344++0x03 line.long 0x0 "GICD_ICDABR17,Active Status Register 17" bitfld.long 0x00 31. " ASB575 ,Active Status Bit 575" "Not active,Active" bitfld.long 0x00 30. " ASB574 ,Active Status Bit 574" "Not active,Active" bitfld.long 0x00 29. " ASB573 ,Active Status Bit 573" "Not active,Active" textline " " bitfld.long 0x00 28. " ASB572 ,Active Status Bit 572" "Not active,Active" bitfld.long 0x00 27. " ASB571 ,Active Status Bit 571" "Not active,Active" bitfld.long 0x00 26. " ASB570 ,Active Status Bit 570" "Not active,Active" textline " " bitfld.long 0x00 25. " ASB569 ,Active Status Bit 569" "Not active,Active" bitfld.long 0x00 24. " ASB568 ,Active Status Bit 568" "Not active,Active" bitfld.long 0x00 23. " ASB567 ,Active Status Bit 567" "Not active,Active" textline " " bitfld.long 0x00 22. " ASB566 ,Active Status Bit 566" "Not active,Active" bitfld.long 0x00 21. " ASB565 ,Active Status Bit 565" "Not active,Active" bitfld.long 0x00 20. " ASB564 ,Active Status Bit 564" "Not active,Active" textline " " bitfld.long 0x00 19. " ASB563 ,Active Status Bit 563" "Not active,Active" bitfld.long 0x00 18. " ASB562 ,Active Status Bit 562" "Not active,Active" bitfld.long 0x00 17. " ASB561 ,Active Status Bit 561" "Not active,Active" textline " " bitfld.long 0x00 16. " ASB560 ,Active Status Bit 560" "Not active,Active" bitfld.long 0x00 15. " ASB559 ,Active Status Bit 559" "Not active,Active" bitfld.long 0x00 14. " ASB558 ,Active Status Bit 558" "Not active,Active" textline " " bitfld.long 0x00 13. " ASB557 ,Active Status Bit 557" "Not active,Active" bitfld.long 0x00 12. " ASB556 ,Active Status Bit 556" "Not active,Active" bitfld.long 0x00 11. " ASB555 ,Active Status Bit 555" "Not active,Active" textline " " bitfld.long 0x00 10. " ASB554 ,Active Status Bit 554" "Not active,Active" bitfld.long 0x00 9. " ASB553 ,Active Status Bit 553" "Not active,Active" bitfld.long 0x00 8. " ASB552 ,Active Status Bit 552" "Not active,Active" textline " " bitfld.long 0x00 7. " ASB551 ,Active Status Bit 551" "Not active,Active" bitfld.long 0x00 6. " ASB550 ,Active Status Bit 550" "Not active,Active" bitfld.long 0x00 5. " ASB549 ,Active Status Bit 549" "Not active,Active" textline " " bitfld.long 0x00 4. " ASB548 ,Active Status Bit 548" "Not active,Active" bitfld.long 0x00 3. " ASB547 ,Active Status Bit 547" "Not active,Active" bitfld.long 0x00 2. " ASB546 ,Active Status Bit 546" "Not active,Active" textline " " bitfld.long 0x00 1. " ASB545 ,Active Status Bit 545" "Not active,Active" bitfld.long 0x00 0. " ASB544 ,Active Status Bit 544" "Not active,Active" else rgroup.long 0x0344++0x03 line.long 0x0 "GICD_ICDABR17,Active Status Register 17" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x12) rgroup.long 0x0348++0x03 line.long 0x0 "GICD_ICDABR18,Active Status Register 18" bitfld.long 0x00 31. " ASB607 ,Active Status Bit 607" "Not active,Active" bitfld.long 0x00 30. " ASB606 ,Active Status Bit 606" "Not active,Active" bitfld.long 0x00 29. " ASB605 ,Active Status Bit 605" "Not active,Active" textline " " bitfld.long 0x00 28. " ASB604 ,Active Status Bit 604" "Not active,Active" bitfld.long 0x00 27. " ASB603 ,Active Status Bit 603" "Not active,Active" bitfld.long 0x00 26. " ASB602 ,Active Status Bit 602" "Not active,Active" textline " " bitfld.long 0x00 25. " ASB601 ,Active Status Bit 601" "Not active,Active" bitfld.long 0x00 24. " ASB600 ,Active Status Bit 600" "Not active,Active" bitfld.long 0x00 23. " ASB599 ,Active Status Bit 599" "Not active,Active" textline " " bitfld.long 0x00 22. " ASB598 ,Active Status Bit 598" "Not active,Active" bitfld.long 0x00 21. " ASB597 ,Active Status Bit 597" "Not active,Active" bitfld.long 0x00 20. " ASB596 ,Active Status Bit 596" "Not active,Active" textline " " bitfld.long 0x00 19. " ASB595 ,Active Status Bit 595" "Not active,Active" bitfld.long 0x00 18. " ASB594 ,Active Status Bit 594" "Not active,Active" bitfld.long 0x00 17. " ASB593 ,Active Status Bit 593" "Not active,Active" textline " " bitfld.long 0x00 16. " ASB592 ,Active Status Bit 592" "Not active,Active" bitfld.long 0x00 15. " ASB591 ,Active Status Bit 591" "Not active,Active" bitfld.long 0x00 14. " ASB590 ,Active Status Bit 590" "Not active,Active" textline " " bitfld.long 0x00 13. " ASB589 ,Active Status Bit 589" "Not active,Active" bitfld.long 0x00 12. " ASB588 ,Active Status Bit 588" "Not active,Active" bitfld.long 0x00 11. " ASB587 ,Active Status Bit 587" "Not active,Active" textline " " bitfld.long 0x00 10. " ASB586 ,Active Status Bit 586" "Not active,Active" bitfld.long 0x00 9. " ASB585 ,Active Status Bit 585" "Not active,Active" bitfld.long 0x00 8. " ASB584 ,Active Status Bit 584" "Not active,Active" textline " " bitfld.long 0x00 7. " ASB583 ,Active Status Bit 583" "Not active,Active" bitfld.long 0x00 6. " ASB582 ,Active Status Bit 582" "Not active,Active" bitfld.long 0x00 5. " ASB581 ,Active Status Bit 581" "Not active,Active" textline " " bitfld.long 0x00 4. " ASB580 ,Active Status Bit 580" "Not active,Active" bitfld.long 0x00 3. " ASB579 ,Active Status Bit 579" "Not active,Active" bitfld.long 0x00 2. " ASB578 ,Active Status Bit 578" "Not active,Active" textline " " bitfld.long 0x00 1. " ASB577 ,Active Status Bit 577" "Not active,Active" bitfld.long 0x00 0. " ASB576 ,Active Status Bit 576" "Not active,Active" else rgroup.long 0x0348++0x03 line.long 0x0 "GICD_ICDABR18,Active Status Register 18" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x13) rgroup.long 0x034C++0x03 line.long 0x0 "GICD_ICDABR19,Active Status Register 19" bitfld.long 0x00 31. " ASB639 ,Active Status Bit 639" "Not active,Active" bitfld.long 0x00 30. " ASB638 ,Active Status Bit 638" "Not active,Active" bitfld.long 0x00 29. " ASB637 ,Active Status Bit 637" "Not active,Active" textline " " bitfld.long 0x00 28. " ASB636 ,Active Status Bit 636" "Not active,Active" bitfld.long 0x00 27. " ASB635 ,Active Status Bit 635" "Not active,Active" bitfld.long 0x00 26. " ASB634 ,Active Status Bit 634" "Not active,Active" textline " " bitfld.long 0x00 25. " ASB633 ,Active Status Bit 633" "Not active,Active" bitfld.long 0x00 24. " ASB632 ,Active Status Bit 632" "Not active,Active" bitfld.long 0x00 23. " ASB631 ,Active Status Bit 631" "Not active,Active" textline " " bitfld.long 0x00 22. " ASB630 ,Active Status Bit 630" "Not active,Active" bitfld.long 0x00 21. " ASB629 ,Active Status Bit 629" "Not active,Active" bitfld.long 0x00 20. " ASB628 ,Active Status Bit 628" "Not active,Active" textline " " bitfld.long 0x00 19. " ASB627 ,Active Status Bit 627" "Not active,Active" bitfld.long 0x00 18. " ASB626 ,Active Status Bit 626" "Not active,Active" bitfld.long 0x00 17. " ASB625 ,Active Status Bit 625" "Not active,Active" textline " " bitfld.long 0x00 16. " ASB624 ,Active Status Bit 624" "Not active,Active" bitfld.long 0x00 15. " ASB623 ,Active Status Bit 623" "Not active,Active" bitfld.long 0x00 14. " ASB622 ,Active Status Bit 622" "Not active,Active" textline " " bitfld.long 0x00 13. " ASB621 ,Active Status Bit 621" "Not active,Active" bitfld.long 0x00 12. " ASB620 ,Active Status Bit 620" "Not active,Active" bitfld.long 0x00 11. " ASB619 ,Active Status Bit 619" "Not active,Active" textline " " bitfld.long 0x00 10. " ASB618 ,Active Status Bit 618" "Not active,Active" bitfld.long 0x00 9. " ASB617 ,Active Status Bit 617" "Not active,Active" bitfld.long 0x00 8. " ASB616 ,Active Status Bit 616" "Not active,Active" textline " " bitfld.long 0x00 7. " ASB615 ,Active Status Bit 615" "Not active,Active" bitfld.long 0x00 6. " ASB614 ,Active Status Bit 614" "Not active,Active" bitfld.long 0x00 5. " ASB613 ,Active Status Bit 613" "Not active,Active" textline " " bitfld.long 0x00 4. " ASB612 ,Active Status Bit 612" "Not active,Active" bitfld.long 0x00 3. " ASB611 ,Active Status Bit 611" "Not active,Active" bitfld.long 0x00 2. " ASB610 ,Active Status Bit 610" "Not active,Active" textline " " bitfld.long 0x00 1. " ASB609 ,Active Status Bit 609" "Not active,Active" bitfld.long 0x00 0. " ASB608 ,Active Status Bit 608" "Not active,Active" else rgroup.long 0x034C++0x03 line.long 0x0 "GICD_ICDABR19,Active Status Register 19" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x14) rgroup.long 0x0350++0x03 line.long 0x0 "GICD_ICDABR20,Active Status Register 20" bitfld.long 0x00 31. " ASB671 ,Active Status Bit 671" "Not active,Active" bitfld.long 0x00 30. " ASB670 ,Active Status Bit 670" "Not active,Active" bitfld.long 0x00 29. " ASB669 ,Active Status Bit 669" "Not active,Active" textline " " bitfld.long 0x00 28. " ASB668 ,Active Status Bit 668" "Not active,Active" bitfld.long 0x00 27. " ASB667 ,Active Status Bit 667" "Not active,Active" bitfld.long 0x00 26. " ASB666 ,Active Status Bit 666" "Not active,Active" textline " " bitfld.long 0x00 25. " ASB665 ,Active Status Bit 665" "Not active,Active" bitfld.long 0x00 24. " ASB664 ,Active Status Bit 664" "Not active,Active" bitfld.long 0x00 23. " ASB663 ,Active Status Bit 663" "Not active,Active" textline " " bitfld.long 0x00 22. " ASB662 ,Active Status Bit 662" "Not active,Active" bitfld.long 0x00 21. " ASB661 ,Active Status Bit 661" "Not active,Active" bitfld.long 0x00 20. " ASB660 ,Active Status Bit 660" "Not active,Active" textline " " bitfld.long 0x00 19. " ASB659 ,Active Status Bit 659" "Not active,Active" bitfld.long 0x00 18. " ASB658 ,Active Status Bit 658" "Not active,Active" bitfld.long 0x00 17. " ASB657 ,Active Status Bit 657" "Not active,Active" textline " " bitfld.long 0x00 16. " ASB656 ,Active Status Bit 656" "Not active,Active" bitfld.long 0x00 15. " ASB655 ,Active Status Bit 655" "Not active,Active" bitfld.long 0x00 14. " ASB654 ,Active Status Bit 654" "Not active,Active" textline " " bitfld.long 0x00 13. " ASB653 ,Active Status Bit 653" "Not active,Active" bitfld.long 0x00 12. " ASB652 ,Active Status Bit 652" "Not active,Active" bitfld.long 0x00 11. " ASB651 ,Active Status Bit 651" "Not active,Active" textline " " bitfld.long 0x00 10. " ASB650 ,Active Status Bit 650" "Not active,Active" bitfld.long 0x00 9. " ASB649 ,Active Status Bit 649" "Not active,Active" bitfld.long 0x00 8. " ASB648 ,Active Status Bit 648" "Not active,Active" textline " " bitfld.long 0x00 7. " ASB647 ,Active Status Bit 647" "Not active,Active" bitfld.long 0x00 6. " ASB646 ,Active Status Bit 646" "Not active,Active" bitfld.long 0x00 5. " ASB645 ,Active Status Bit 645" "Not active,Active" textline " " bitfld.long 0x00 4. " ASB644 ,Active Status Bit 644" "Not active,Active" bitfld.long 0x00 3. " ASB643 ,Active Status Bit 643" "Not active,Active" bitfld.long 0x00 2. " ASB642 ,Active Status Bit 642" "Not active,Active" textline " " bitfld.long 0x00 1. " ASB641 ,Active Status Bit 641" "Not active,Active" bitfld.long 0x00 0. " ASB640 ,Active Status Bit 640" "Not active,Active" else rgroup.long 0x0350++0x03 line.long 0x0 "GICD_ICDABR20,Active Status Register 20" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x15) rgroup.long 0x0354++0x03 line.long 0x0 "GICD_ICDABR21,Active Status Register 21" bitfld.long 0x00 31. " ASB703 ,Active Status Bit 703" "Not active,Active" bitfld.long 0x00 30. " ASB702 ,Active Status Bit 702" "Not active,Active" bitfld.long 0x00 29. " ASB701 ,Active Status Bit 701" "Not active,Active" textline " " bitfld.long 0x00 28. " ASB700 ,Active Status Bit 700" "Not active,Active" bitfld.long 0x00 27. " ASB699 ,Active Status Bit 699" "Not active,Active" bitfld.long 0x00 26. " ASB698 ,Active Status Bit 698" "Not active,Active" textline " " bitfld.long 0x00 25. " ASB697 ,Active Status Bit 697" "Not active,Active" bitfld.long 0x00 24. " ASB696 ,Active Status Bit 696" "Not active,Active" bitfld.long 0x00 23. " ASB695 ,Active Status Bit 695" "Not active,Active" textline " " bitfld.long 0x00 22. " ASB694 ,Active Status Bit 694" "Not active,Active" bitfld.long 0x00 21. " ASB693 ,Active Status Bit 693" "Not active,Active" bitfld.long 0x00 20. " ASB692 ,Active Status Bit 692" "Not active,Active" textline " " bitfld.long 0x00 19. " ASB691 ,Active Status Bit 691" "Not active,Active" bitfld.long 0x00 18. " ASB690 ,Active Status Bit 690" "Not active,Active" bitfld.long 0x00 17. " ASB689 ,Active Status Bit 689" "Not active,Active" textline " " bitfld.long 0x00 16. " ASB688 ,Active Status Bit 688" "Not active,Active" bitfld.long 0x00 15. " ASB687 ,Active Status Bit 687" "Not active,Active" bitfld.long 0x00 14. " ASB686 ,Active Status Bit 686" "Not active,Active" textline " " bitfld.long 0x00 13. " ASB685 ,Active Status Bit 685" "Not active,Active" bitfld.long 0x00 12. " ASB684 ,Active Status Bit 684" "Not active,Active" bitfld.long 0x00 11. " ASB683 ,Active Status Bit 683" "Not active,Active" textline " " bitfld.long 0x00 10. " ASB682 ,Active Status Bit 682" "Not active,Active" bitfld.long 0x00 9. " ASB681 ,Active Status Bit 681" "Not active,Active" bitfld.long 0x00 8. " ASB680 ,Active Status Bit 680" "Not active,Active" textline " " bitfld.long 0x00 7. " ASB679 ,Active Status Bit 679" "Not active,Active" bitfld.long 0x00 6. " ASB678 ,Active Status Bit 678" "Not active,Active" bitfld.long 0x00 5. " ASB677 ,Active Status Bit 677" "Not active,Active" textline " " bitfld.long 0x00 4. " ASB676 ,Active Status Bit 676" "Not active,Active" bitfld.long 0x00 3. " ASB675 ,Active Status Bit 675" "Not active,Active" bitfld.long 0x00 2. " ASB674 ,Active Status Bit 674" "Not active,Active" textline " " bitfld.long 0x00 1. " ASB673 ,Active Status Bit 673" "Not active,Active" bitfld.long 0x00 0. " ASB672 ,Active Status Bit 672" "Not active,Active" else rgroup.long 0x0354++0x03 line.long 0x0 "GICD_ICDABR21,Active Status Register 21" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x16) rgroup.long 0x0358++0x03 line.long 0x0 "GICD_ICDABR22,Active Status Register 22" bitfld.long 0x00 31. " ASB735 ,Active Status Bit 735" "Not active,Active" bitfld.long 0x00 30. " ASB734 ,Active Status Bit 734" "Not active,Active" bitfld.long 0x00 29. " ASB733 ,Active Status Bit 733" "Not active,Active" textline " " bitfld.long 0x00 28. " ASB732 ,Active Status Bit 732" "Not active,Active" bitfld.long 0x00 27. " ASB731 ,Active Status Bit 731" "Not active,Active" bitfld.long 0x00 26. " ASB730 ,Active Status Bit 730" "Not active,Active" textline " " bitfld.long 0x00 25. " ASB729 ,Active Status Bit 729" "Not active,Active" bitfld.long 0x00 24. " ASB728 ,Active Status Bit 728" "Not active,Active" bitfld.long 0x00 23. " ASB727 ,Active Status Bit 727" "Not active,Active" textline " " bitfld.long 0x00 22. " ASB726 ,Active Status Bit 726" "Not active,Active" bitfld.long 0x00 21. " ASB725 ,Active Status Bit 725" "Not active,Active" bitfld.long 0x00 20. " ASB724 ,Active Status Bit 724" "Not active,Active" textline " " bitfld.long 0x00 19. " ASB723 ,Active Status Bit 723" "Not active,Active" bitfld.long 0x00 18. " ASB722 ,Active Status Bit 722" "Not active,Active" bitfld.long 0x00 17. " ASB721 ,Active Status Bit 721" "Not active,Active" textline " " bitfld.long 0x00 16. " ASB720 ,Active Status Bit 720" "Not active,Active" bitfld.long 0x00 15. " ASB719 ,Active Status Bit 719" "Not active,Active" bitfld.long 0x00 14. " ASB718 ,Active Status Bit 718" "Not active,Active" textline " " bitfld.long 0x00 13. " ASB717 ,Active Status Bit 717" "Not active,Active" bitfld.long 0x00 12. " ASB716 ,Active Status Bit 716" "Not active,Active" bitfld.long 0x00 11. " ASB715 ,Active Status Bit 715" "Not active,Active" textline " " bitfld.long 0x00 10. " ASB714 ,Active Status Bit 714" "Not active,Active" bitfld.long 0x00 9. " ASB713 ,Active Status Bit 713" "Not active,Active" bitfld.long 0x00 8. " ASB712 ,Active Status Bit 712" "Not active,Active" textline " " bitfld.long 0x00 7. " ASB711 ,Active Status Bit 711" "Not active,Active" bitfld.long 0x00 6. " ASB710 ,Active Status Bit 710" "Not active,Active" bitfld.long 0x00 5. " ASB709 ,Active Status Bit 709" "Not active,Active" textline " " bitfld.long 0x00 4. " ASB708 ,Active Status Bit 708" "Not active,Active" bitfld.long 0x00 3. " ASB707 ,Active Status Bit 707" "Not active,Active" bitfld.long 0x00 2. " ASB706 ,Active Status Bit 706" "Not active,Active" textline " " bitfld.long 0x00 1. " ASB705 ,Active Status Bit 705" "Not active,Active" bitfld.long 0x00 0. " ASB704 ,Active Status Bit 704" "Not active,Active" else rgroup.long 0x0358++0x03 line.long 0x0 "GICD_ICDABR22,Active Status Register 22" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x17) rgroup.long 0x035C++0x03 line.long 0x0 "GICD_ICDABR23,Active Status Register 23" bitfld.long 0x00 31. " ASB767 ,Active Status Bit 767" "Not active,Active" bitfld.long 0x00 30. " ASB766 ,Active Status Bit 766" "Not active,Active" bitfld.long 0x00 29. " ASB765 ,Active Status Bit 765" "Not active,Active" textline " " bitfld.long 0x00 28. " ASB764 ,Active Status Bit 764" "Not active,Active" bitfld.long 0x00 27. " ASB763 ,Active Status Bit 763" "Not active,Active" bitfld.long 0x00 26. " ASB762 ,Active Status Bit 762" "Not active,Active" textline " " bitfld.long 0x00 25. " ASB761 ,Active Status Bit 761" "Not active,Active" bitfld.long 0x00 24. " ASB760 ,Active Status Bit 760" "Not active,Active" bitfld.long 0x00 23. " ASB759 ,Active Status Bit 759" "Not active,Active" textline " " bitfld.long 0x00 22. " ASB758 ,Active Status Bit 758" "Not active,Active" bitfld.long 0x00 21. " ASB757 ,Active Status Bit 757" "Not active,Active" bitfld.long 0x00 20. " ASB756 ,Active Status Bit 756" "Not active,Active" textline " " bitfld.long 0x00 19. " ASB755 ,Active Status Bit 755" "Not active,Active" bitfld.long 0x00 18. " ASB754 ,Active Status Bit 754" "Not active,Active" bitfld.long 0x00 17. " ASB753 ,Active Status Bit 753" "Not active,Active" textline " " bitfld.long 0x00 16. " ASB752 ,Active Status Bit 752" "Not active,Active" bitfld.long 0x00 15. " ASB751 ,Active Status Bit 751" "Not active,Active" bitfld.long 0x00 14. " ASB750 ,Active Status Bit 750" "Not active,Active" textline " " bitfld.long 0x00 13. " ASB749 ,Active Status Bit 749" "Not active,Active" bitfld.long 0x00 12. " ASB748 ,Active Status Bit 748" "Not active,Active" bitfld.long 0x00 11. " ASB747 ,Active Status Bit 747" "Not active,Active" textline " " bitfld.long 0x00 10. " ASB746 ,Active Status Bit 746" "Not active,Active" bitfld.long 0x00 9. " ASB745 ,Active Status Bit 745" "Not active,Active" bitfld.long 0x00 8. " ASB744 ,Active Status Bit 744" "Not active,Active" textline " " bitfld.long 0x00 7. " ASB743 ,Active Status Bit 743" "Not active,Active" bitfld.long 0x00 6. " ASB742 ,Active Status Bit 742" "Not active,Active" bitfld.long 0x00 5. " ASB741 ,Active Status Bit 741" "Not active,Active" textline " " bitfld.long 0x00 4. " ASB740 ,Active Status Bit 740" "Not active,Active" bitfld.long 0x00 3. " ASB739 ,Active Status Bit 739" "Not active,Active" bitfld.long 0x00 2. " ASB738 ,Active Status Bit 738" "Not active,Active" textline " " bitfld.long 0x00 1. " ASB737 ,Active Status Bit 737" "Not active,Active" bitfld.long 0x00 0. " ASB736 ,Active Status Bit 736" "Not active,Active" else rgroup.long 0x035C++0x03 line.long 0x0 "GICD_ICDABR23,Active Status Register 23" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x18) rgroup.long 0x0360++0x03 line.long 0x0 "GICD_ICDABR24,Active Status Register 24" bitfld.long 0x00 31. " ASB799 ,Active Status Bit 799" "Not active,Active" bitfld.long 0x00 30. " ASB798 ,Active Status Bit 798" "Not active,Active" bitfld.long 0x00 29. " ASB797 ,Active Status Bit 797" "Not active,Active" textline " " bitfld.long 0x00 28. " ASB796 ,Active Status Bit 796" "Not active,Active" bitfld.long 0x00 27. " ASB795 ,Active Status Bit 795" "Not active,Active" bitfld.long 0x00 26. " ASB794 ,Active Status Bit 794" "Not active,Active" textline " " bitfld.long 0x00 25. " ASB793 ,Active Status Bit 793" "Not active,Active" bitfld.long 0x00 24. " ASB792 ,Active Status Bit 792" "Not active,Active" bitfld.long 0x00 23. " ASB791 ,Active Status Bit 791" "Not active,Active" textline " " bitfld.long 0x00 22. " ASB790 ,Active Status Bit 790" "Not active,Active" bitfld.long 0x00 21. " ASB789 ,Active Status Bit 789" "Not active,Active" bitfld.long 0x00 20. " ASB788 ,Active Status Bit 788" "Not active,Active" textline " " bitfld.long 0x00 19. " ASB787 ,Active Status Bit 787" "Not active,Active" bitfld.long 0x00 18. " ASB786 ,Active Status Bit 786" "Not active,Active" bitfld.long 0x00 17. " ASB785 ,Active Status Bit 785" "Not active,Active" textline " " bitfld.long 0x00 16. " ASB784 ,Active Status Bit 784" "Not active,Active" bitfld.long 0x00 15. " ASB783 ,Active Status Bit 783" "Not active,Active" bitfld.long 0x00 14. " ASB782 ,Active Status Bit 782" "Not active,Active" textline " " bitfld.long 0x00 13. " ASB781 ,Active Status Bit 781" "Not active,Active" bitfld.long 0x00 12. " ASB780 ,Active Status Bit 780" "Not active,Active" bitfld.long 0x00 11. " ASB779 ,Active Status Bit 779" "Not active,Active" textline " " bitfld.long 0x00 10. " ASB778 ,Active Status Bit 778" "Not active,Active" bitfld.long 0x00 9. " ASB777 ,Active Status Bit 777" "Not active,Active" bitfld.long 0x00 8. " ASB776 ,Active Status Bit 776" "Not active,Active" textline " " bitfld.long 0x00 7. " ASB775 ,Active Status Bit 775" "Not active,Active" bitfld.long 0x00 6. " ASB774 ,Active Status Bit 774" "Not active,Active" bitfld.long 0x00 5. " ASB773 ,Active Status Bit 773" "Not active,Active" textline " " bitfld.long 0x00 4. " ASB772 ,Active Status Bit 772" "Not active,Active" bitfld.long 0x00 3. " ASB771 ,Active Status Bit 771" "Not active,Active" bitfld.long 0x00 2. " ASB770 ,Active Status Bit 770" "Not active,Active" textline " " bitfld.long 0x00 1. " ASB769 ,Active Status Bit 769" "Not active,Active" bitfld.long 0x00 0. " ASB768 ,Active Status Bit 768" "Not active,Active" else rgroup.long 0x0360++0x03 line.long 0x0 "GICD_ICDABR24,Active Status Register 24" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x19) rgroup.long 0x0364++0x03 line.long 0x0 "GICD_ICDABR25,Active Status Register 25" bitfld.long 0x00 31. " ASB831 ,Active Status Bit 831" "Not active,Active" bitfld.long 0x00 30. " ASB830 ,Active Status Bit 830" "Not active,Active" bitfld.long 0x00 29. " ASB829 ,Active Status Bit 829" "Not active,Active" textline " " bitfld.long 0x00 28. " ASB828 ,Active Status Bit 828" "Not active,Active" bitfld.long 0x00 27. " ASB827 ,Active Status Bit 827" "Not active,Active" bitfld.long 0x00 26. " ASB826 ,Active Status Bit 826" "Not active,Active" textline " " bitfld.long 0x00 25. " ASB825 ,Active Status Bit 825" "Not active,Active" bitfld.long 0x00 24. " ASB824 ,Active Status Bit 824" "Not active,Active" bitfld.long 0x00 23. " ASB823 ,Active Status Bit 823" "Not active,Active" textline " " bitfld.long 0x00 22. " ASB822 ,Active Status Bit 822" "Not active,Active" bitfld.long 0x00 21. " ASB821 ,Active Status Bit 821" "Not active,Active" bitfld.long 0x00 20. " ASB820 ,Active Status Bit 820" "Not active,Active" textline " " bitfld.long 0x00 19. " ASB819 ,Active Status Bit 819" "Not active,Active" bitfld.long 0x00 18. " ASB818 ,Active Status Bit 818" "Not active,Active" bitfld.long 0x00 17. " ASB817 ,Active Status Bit 817" "Not active,Active" textline " " bitfld.long 0x00 16. " ASB816 ,Active Status Bit 816" "Not active,Active" bitfld.long 0x00 15. " ASB815 ,Active Status Bit 815" "Not active,Active" bitfld.long 0x00 14. " ASB814 ,Active Status Bit 814" "Not active,Active" textline " " bitfld.long 0x00 13. " ASB813 ,Active Status Bit 813" "Not active,Active" bitfld.long 0x00 12. " ASB812 ,Active Status Bit 812" "Not active,Active" bitfld.long 0x00 11. " ASB811 ,Active Status Bit 811" "Not active,Active" textline " " bitfld.long 0x00 10. " ASB810 ,Active Status Bit 810" "Not active,Active" bitfld.long 0x00 9. " ASB809 ,Active Status Bit 809" "Not active,Active" bitfld.long 0x00 8. " ASB808 ,Active Status Bit 808" "Not active,Active" textline " " bitfld.long 0x00 7. " ASB807 ,Active Status Bit 807" "Not active,Active" bitfld.long 0x00 6. " ASB806 ,Active Status Bit 806" "Not active,Active" bitfld.long 0x00 5. " ASB805 ,Active Status Bit 805" "Not active,Active" textline " " bitfld.long 0x00 4. " ASB804 ,Active Status Bit 804" "Not active,Active" bitfld.long 0x00 3. " ASB803 ,Active Status Bit 803" "Not active,Active" bitfld.long 0x00 2. " ASB802 ,Active Status Bit 802" "Not active,Active" textline " " bitfld.long 0x00 1. " ASB801 ,Active Status Bit 801" "Not active,Active" bitfld.long 0x00 0. " ASB800 ,Active Status Bit 800" "Not active,Active" else rgroup.long 0x0364++0x03 line.long 0x0 "GICD_ICDABR25,Active Status Register 25" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x1A) rgroup.long 0x0368++0x03 line.long 0x0 "GICD_ICDABR26,Active Status Register 26" bitfld.long 0x00 31. " ASB863 ,Active Status Bit 863" "Not active,Active" bitfld.long 0x00 30. " ASB862 ,Active Status Bit 862" "Not active,Active" bitfld.long 0x00 29. " ASB861 ,Active Status Bit 861" "Not active,Active" textline " " bitfld.long 0x00 28. " ASB860 ,Active Status Bit 860" "Not active,Active" bitfld.long 0x00 27. " ASB859 ,Active Status Bit 859" "Not active,Active" bitfld.long 0x00 26. " ASB858 ,Active Status Bit 858" "Not active,Active" textline " " bitfld.long 0x00 25. " ASB857 ,Active Status Bit 857" "Not active,Active" bitfld.long 0x00 24. " ASB856 ,Active Status Bit 856" "Not active,Active" bitfld.long 0x00 23. " ASB855 ,Active Status Bit 855" "Not active,Active" textline " " bitfld.long 0x00 22. " ASB854 ,Active Status Bit 854" "Not active,Active" bitfld.long 0x00 21. " ASB853 ,Active Status Bit 853" "Not active,Active" bitfld.long 0x00 20. " ASB852 ,Active Status Bit 852" "Not active,Active" textline " " bitfld.long 0x00 19. " ASB851 ,Active Status Bit 851" "Not active,Active" bitfld.long 0x00 18. " ASB850 ,Active Status Bit 850" "Not active,Active" bitfld.long 0x00 17. " ASB849 ,Active Status Bit 849" "Not active,Active" textline " " bitfld.long 0x00 16. " ASB848 ,Active Status Bit 848" "Not active,Active" bitfld.long 0x00 15. " ASB847 ,Active Status Bit 847" "Not active,Active" bitfld.long 0x00 14. " ASB846 ,Active Status Bit 846" "Not active,Active" textline " " bitfld.long 0x00 13. " ASB845 ,Active Status Bit 845" "Not active,Active" bitfld.long 0x00 12. " ASB844 ,Active Status Bit 844" "Not active,Active" bitfld.long 0x00 11. " ASB843 ,Active Status Bit 843" "Not active,Active" textline " " bitfld.long 0x00 10. " ASB842 ,Active Status Bit 842" "Not active,Active" bitfld.long 0x00 9. " ASB841 ,Active Status Bit 841" "Not active,Active" bitfld.long 0x00 8. " ASB840 ,Active Status Bit 840" "Not active,Active" textline " " bitfld.long 0x00 7. " ASB839 ,Active Status Bit 839" "Not active,Active" bitfld.long 0x00 6. " ASB838 ,Active Status Bit 838" "Not active,Active" bitfld.long 0x00 5. " ASB837 ,Active Status Bit 837" "Not active,Active" textline " " bitfld.long 0x00 4. " ASB836 ,Active Status Bit 836" "Not active,Active" bitfld.long 0x00 3. " ASB835 ,Active Status Bit 835" "Not active,Active" bitfld.long 0x00 2. " ASB834 ,Active Status Bit 834" "Not active,Active" textline " " bitfld.long 0x00 1. " ASB833 ,Active Status Bit 833" "Not active,Active" bitfld.long 0x00 0. " ASB832 ,Active Status Bit 832" "Not active,Active" else rgroup.long 0x0368++0x03 line.long 0x0 "GICD_ICDABR26,Active Status Register 26" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x1B) rgroup.long 0x036C++0x03 line.long 0x0 "GICD_ICDABR27,Active Status Register 27" bitfld.long 0x00 31. " ASB895 ,Active Status Bit 895" "Not active,Active" bitfld.long 0x00 30. " ASB894 ,Active Status Bit 894" "Not active,Active" bitfld.long 0x00 29. " ASB893 ,Active Status Bit 893" "Not active,Active" textline " " bitfld.long 0x00 28. " ASB892 ,Active Status Bit 892" "Not active,Active" bitfld.long 0x00 27. " ASB891 ,Active Status Bit 891" "Not active,Active" bitfld.long 0x00 26. " ASB890 ,Active Status Bit 890" "Not active,Active" textline " " bitfld.long 0x00 25. " ASB889 ,Active Status Bit 889" "Not active,Active" bitfld.long 0x00 24. " ASB888 ,Active Status Bit 888" "Not active,Active" bitfld.long 0x00 23. " ASB887 ,Active Status Bit 887" "Not active,Active" textline " " bitfld.long 0x00 22. " ASB886 ,Active Status Bit 886" "Not active,Active" bitfld.long 0x00 21. " ASB885 ,Active Status Bit 885" "Not active,Active" bitfld.long 0x00 20. " ASB884 ,Active Status Bit 884" "Not active,Active" textline " " bitfld.long 0x00 19. " ASB883 ,Active Status Bit 883" "Not active,Active" bitfld.long 0x00 18. " ASB882 ,Active Status Bit 882" "Not active,Active" bitfld.long 0x00 17. " ASB881 ,Active Status Bit 881" "Not active,Active" textline " " bitfld.long 0x00 16. " ASB880 ,Active Status Bit 880" "Not active,Active" bitfld.long 0x00 15. " ASB879 ,Active Status Bit 879" "Not active,Active" bitfld.long 0x00 14. " ASB878 ,Active Status Bit 878" "Not active,Active" textline " " bitfld.long 0x00 13. " ASB877 ,Active Status Bit 877" "Not active,Active" bitfld.long 0x00 12. " ASB876 ,Active Status Bit 876" "Not active,Active" bitfld.long 0x00 11. " ASB875 ,Active Status Bit 875" "Not active,Active" textline " " bitfld.long 0x00 10. " ASB874 ,Active Status Bit 874" "Not active,Active" bitfld.long 0x00 9. " ASB873 ,Active Status Bit 873" "Not active,Active" bitfld.long 0x00 8. " ASB872 ,Active Status Bit 872" "Not active,Active" textline " " bitfld.long 0x00 7. " ASB871 ,Active Status Bit 871" "Not active,Active" bitfld.long 0x00 6. " ASB870 ,Active Status Bit 870" "Not active,Active" bitfld.long 0x00 5. " ASB869 ,Active Status Bit 869" "Not active,Active" textline " " bitfld.long 0x00 4. " ASB868 ,Active Status Bit 868" "Not active,Active" bitfld.long 0x00 3. " ASB867 ,Active Status Bit 867" "Not active,Active" bitfld.long 0x00 2. " ASB866 ,Active Status Bit 866" "Not active,Active" textline " " bitfld.long 0x00 1. " ASB865 ,Active Status Bit 865" "Not active,Active" bitfld.long 0x00 0. " ASB864 ,Active Status Bit 864" "Not active,Active" else rgroup.long 0x036C++0x03 line.long 0x0 "GICD_ICDABR27,Active Status Register 27" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x1C) rgroup.long 0x0370++0x03 line.long 0x0 "GICD_ICDABR28,Active Status Register 28" bitfld.long 0x00 31. " ASB927 ,Active Status Bit 927" "Not active,Active" bitfld.long 0x00 30. " ASB926 ,Active Status Bit 926" "Not active,Active" bitfld.long 0x00 29. " ASB925 ,Active Status Bit 925" "Not active,Active" textline " " bitfld.long 0x00 28. " ASB924 ,Active Status Bit 924" "Not active,Active" bitfld.long 0x00 27. " ASB923 ,Active Status Bit 923" "Not active,Active" bitfld.long 0x00 26. " ASB922 ,Active Status Bit 922" "Not active,Active" textline " " bitfld.long 0x00 25. " ASB921 ,Active Status Bit 921" "Not active,Active" bitfld.long 0x00 24. " ASB920 ,Active Status Bit 920" "Not active,Active" bitfld.long 0x00 23. " ASB919 ,Active Status Bit 919" "Not active,Active" textline " " bitfld.long 0x00 22. " ASB918 ,Active Status Bit 918" "Not active,Active" bitfld.long 0x00 21. " ASB917 ,Active Status Bit 917" "Not active,Active" bitfld.long 0x00 20. " ASB916 ,Active Status Bit 916" "Not active,Active" textline " " bitfld.long 0x00 19. " ASB915 ,Active Status Bit 915" "Not active,Active" bitfld.long 0x00 18. " ASB914 ,Active Status Bit 914" "Not active,Active" bitfld.long 0x00 17. " ASB913 ,Active Status Bit 913" "Not active,Active" textline " " bitfld.long 0x00 16. " ASB912 ,Active Status Bit 912" "Not active,Active" bitfld.long 0x00 15. " ASB911 ,Active Status Bit 911" "Not active,Active" bitfld.long 0x00 14. " ASB910 ,Active Status Bit 910" "Not active,Active" textline " " bitfld.long 0x00 13. " ASB909 ,Active Status Bit 909" "Not active,Active" bitfld.long 0x00 12. " ASB908 ,Active Status Bit 908" "Not active,Active" bitfld.long 0x00 11. " ASB907 ,Active Status Bit 907" "Not active,Active" textline " " bitfld.long 0x00 10. " ASB906 ,Active Status Bit 906" "Not active,Active" bitfld.long 0x00 9. " ASB905 ,Active Status Bit 905" "Not active,Active" bitfld.long 0x00 8. " ASB904 ,Active Status Bit 904" "Not active,Active" textline " " bitfld.long 0x00 7. " ASB903 ,Active Status Bit 903" "Not active,Active" bitfld.long 0x00 6. " ASB902 ,Active Status Bit 902" "Not active,Active" bitfld.long 0x00 5. " ASB901 ,Active Status Bit 901" "Not active,Active" textline " " bitfld.long 0x00 4. " ASB900 ,Active Status Bit 900" "Not active,Active" bitfld.long 0x00 3. " ASB899 ,Active Status Bit 899" "Not active,Active" bitfld.long 0x00 2. " ASB898 ,Active Status Bit 898" "Not active,Active" textline " " bitfld.long 0x00 1. " ASB897 ,Active Status Bit 897" "Not active,Active" bitfld.long 0x00 0. " ASB896 ,Active Status Bit 896" "Not active,Active" else rgroup.long 0x0370++0x03 line.long 0x0 "GICD_ICDABR28,Active Status Register 28" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x1D) rgroup.long 0x0374++0x03 line.long 0x0 "GICD_ICDABR29,Active Status Register 29" bitfld.long 0x00 31. " ASB959 ,Active Status Bit 959" "Not active,Active" bitfld.long 0x00 30. " ASB958 ,Active Status Bit 958" "Not active,Active" bitfld.long 0x00 29. " ASB957 ,Active Status Bit 957" "Not active,Active" textline " " bitfld.long 0x00 28. " ASB956 ,Active Status Bit 956" "Not active,Active" bitfld.long 0x00 27. " ASB955 ,Active Status Bit 955" "Not active,Active" bitfld.long 0x00 26. " ASB954 ,Active Status Bit 954" "Not active,Active" textline " " bitfld.long 0x00 25. " ASB953 ,Active Status Bit 953" "Not active,Active" bitfld.long 0x00 24. " ASB952 ,Active Status Bit 952" "Not active,Active" bitfld.long 0x00 23. " ASB951 ,Active Status Bit 951" "Not active,Active" textline " " bitfld.long 0x00 22. " ASB950 ,Active Status Bit 950" "Not active,Active" bitfld.long 0x00 21. " ASB949 ,Active Status Bit 949" "Not active,Active" bitfld.long 0x00 20. " ASB948 ,Active Status Bit 948" "Not active,Active" textline " " bitfld.long 0x00 19. " ASB947 ,Active Status Bit 947" "Not active,Active" bitfld.long 0x00 18. " ASB946 ,Active Status Bit 946" "Not active,Active" bitfld.long 0x00 17. " ASB945 ,Active Status Bit 945" "Not active,Active" textline " " bitfld.long 0x00 16. " ASB944 ,Active Status Bit 944" "Not active,Active" bitfld.long 0x00 15. " ASB943 ,Active Status Bit 943" "Not active,Active" bitfld.long 0x00 14. " ASB942 ,Active Status Bit 942" "Not active,Active" textline " " bitfld.long 0x00 13. " ASB941 ,Active Status Bit 941" "Not active,Active" bitfld.long 0x00 12. " ASB940 ,Active Status Bit 940" "Not active,Active" bitfld.long 0x00 11. " ASB939 ,Active Status Bit 939" "Not active,Active" textline " " bitfld.long 0x00 10. " ASB938 ,Active Status Bit 938" "Not active,Active" bitfld.long 0x00 9. " ASB937 ,Active Status Bit 937" "Not active,Active" bitfld.long 0x00 8. " ASB936 ,Active Status Bit 936" "Not active,Active" textline " " bitfld.long 0x00 7. " ASB935 ,Active Status Bit 935" "Not active,Active" bitfld.long 0x00 6. " ASB934 ,Active Status Bit 934" "Not active,Active" bitfld.long 0x00 5. " ASB933 ,Active Status Bit 933" "Not active,Active" textline " " bitfld.long 0x00 4. " ASB932 ,Active Status Bit 932" "Not active,Active" bitfld.long 0x00 3. " ASB931 ,Active Status Bit 931" "Not active,Active" bitfld.long 0x00 2. " ASB930 ,Active Status Bit 930" "Not active,Active" textline " " bitfld.long 0x00 1. " ASB929 ,Active Status Bit 929" "Not active,Active" bitfld.long 0x00 0. " ASB928 ,Active Status Bit 928" "Not active,Active" else rgroup.long 0x0374++0x03 line.long 0x0 "GICD_ICDABR29,Active Status Register 29" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x1E) rgroup.long 0x0378++0x03 line.long 0x0 "GICD_ICDABR30,Active Status Register 30" bitfld.long 0x00 31. " ASB991 ,Active Status Bit 991" "Not active,Active" bitfld.long 0x00 30. " ASB990 ,Active Status Bit 990" "Not active,Active" bitfld.long 0x00 29. " ASB989 ,Active Status Bit 989" "Not active,Active" textline " " bitfld.long 0x00 28. " ASB988 ,Active Status Bit 988" "Not active,Active" bitfld.long 0x00 27. " ASB987 ,Active Status Bit 987" "Not active,Active" bitfld.long 0x00 26. " ASB986 ,Active Status Bit 986" "Not active,Active" textline " " bitfld.long 0x00 25. " ASB985 ,Active Status Bit 985" "Not active,Active" bitfld.long 0x00 24. " ASB984 ,Active Status Bit 984" "Not active,Active" bitfld.long 0x00 23. " ASB983 ,Active Status Bit 983" "Not active,Active" textline " " bitfld.long 0x00 22. " ASB982 ,Active Status Bit 982" "Not active,Active" bitfld.long 0x00 21. " ASB981 ,Active Status Bit 981" "Not active,Active" bitfld.long 0x00 20. " ASB980 ,Active Status Bit 980" "Not active,Active" textline " " bitfld.long 0x00 19. " ASB979 ,Active Status Bit 979" "Not active,Active" bitfld.long 0x00 18. " ASB978 ,Active Status Bit 978" "Not active,Active" bitfld.long 0x00 17. " ASB977 ,Active Status Bit 977" "Not active,Active" textline " " bitfld.long 0x00 16. " ASB976 ,Active Status Bit 976" "Not active,Active" bitfld.long 0x00 15. " ASB975 ,Active Status Bit 975" "Not active,Active" bitfld.long 0x00 14. " ASB974 ,Active Status Bit 974" "Not active,Active" textline " " bitfld.long 0x00 13. " ASB973 ,Active Status Bit 973" "Not active,Active" bitfld.long 0x00 12. " ASB972 ,Active Status Bit 972" "Not active,Active" bitfld.long 0x00 11. " ASB971 ,Active Status Bit 971" "Not active,Active" textline " " bitfld.long 0x00 10. " ASB970 ,Active Status Bit 970" "Not active,Active" bitfld.long 0x00 9. " ASB969 ,Active Status Bit 969" "Not active,Active" bitfld.long 0x00 8. " ASB968 ,Active Status Bit 968" "Not active,Active" textline " " bitfld.long 0x00 7. " ASB967 ,Active Status Bit 967" "Not active,Active" bitfld.long 0x00 6. " ASB966 ,Active Status Bit 966" "Not active,Active" bitfld.long 0x00 5. " ASB965 ,Active Status Bit 965" "Not active,Active" textline " " bitfld.long 0x00 4. " ASB964 ,Active Status Bit 964" "Not active,Active" bitfld.long 0x00 3. " ASB963 ,Active Status Bit 963" "Not active,Active" bitfld.long 0x00 2. " ASB962 ,Active Status Bit 962" "Not active,Active" textline " " bitfld.long 0x00 1. " ASB961 ,Active Status Bit 961" "Not active,Active" bitfld.long 0x00 0. " ASB960 ,Active Status Bit 960" "Not active,Active" else rgroup.long 0x0378++0x03 line.long 0x0 "GICD_ICDABR30,Active Status Register 30" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0xA0021000+0x04))&0x0000001F)==0x1F) rgroup.long 0x037C++0x03 line.long 0x0 "GICD_ICDABR31,Active Status Register 31" bitfld.long 0x00 27. " ASB1019 ,Active Status Bit 1019" "Not active,Active" bitfld.long 0x00 26. " ASB1018 ,Active Status Bit 1018" "Not active,Active" textline " " bitfld.long 0x00 25. " ASB1017 ,Active Status Bit 1017" "Not active,Active" bitfld.long 0x00 24. " ASB1016 ,Active Status Bit 1016" "Not active,Active" bitfld.long 0x00 23. " ASB1015 ,Active Status Bit 1015" "Not active,Active" textline " " bitfld.long 0x00 22. " ASB1014 ,Active Status Bit 1014" "Not active,Active" bitfld.long 0x00 21. " ASB1013 ,Active Status Bit 1013" "Not active,Active" bitfld.long 0x00 20. " ASB1012 ,Active Status Bit 1012" "Not active,Active" textline " " bitfld.long 0x00 19. " ASB1011 ,Active Status Bit 1011" "Not active,Active" bitfld.long 0x00 18. " ASB1010 ,Active Status Bit 1010" "Not active,Active" bitfld.long 0x00 17. " ASB1009 ,Active Status Bit 1009" "Not active,Active" textline " " bitfld.long 0x00 16. " ASB1008 ,Active Status Bit 1008" "Not active,Active" bitfld.long 0x00 15. " ASB1007 ,Active Status Bit 1007" "Not active,Active" bitfld.long 0x00 14. " ASB1006 ,Active Status Bit 1006" "Not active,Active" textline " " bitfld.long 0x00 13. " ASB1005 ,Active Status Bit 1005" "Not active,Active" bitfld.long 0x00 12. " ASB1004 ,Active Status Bit 1004" "Not active,Active" bitfld.long 0x00 11. " ASB1003 ,Active Status Bit 1003" "Not active,Active" textline " " bitfld.long 0x00 10. " ASB1002 ,Active Status Bit 1002" "Not active,Active" bitfld.long 0x00 9. " ASB1001 ,Active Status Bit 1001" "Not active,Active" bitfld.long 0x00 8. " ASB1000 ,Active Status Bit 1000" "Not active,Active" textline " " bitfld.long 0x00 7. " ASB999 ,Active Status Bit 999" "Not active,Active" bitfld.long 0x00 6. " ASB998 ,Active Status Bit 998" "Not active,Active" bitfld.long 0x00 5. " ASB997 ,Active Status Bit 997" "Not active,Active" textline " " bitfld.long 0x00 4. " ASB996 ,Active Status Bit 996" "Not active,Active" bitfld.long 0x00 3. " ASB995 ,Active Status Bit 995" "Not active,Active" bitfld.long 0x00 2. " ASB994 ,Active Status Bit 994" "Not active,Active" textline " " bitfld.long 0x00 1. " ASB993 ,Active Status Bit 993" "Not active,Active" bitfld.long 0x00 0. " ASB992 ,Active Status Bit 992" "Not active,Active" else rgroup.long 0x037C++0x03 line.long 0x0 "GICD_ICDABR31,Active Status Register 31" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif else group.long 0x0300++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER0,Interrupt Set/Clear Active Register 0" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE31 ,Set/Clear Active Bit 31" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE30 ,Set/Clear Active Bit 30" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE29 ,Set/Clear Active Bit 29" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE28 ,Set/Clear Active Bit 28" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE27 ,Set/Clear Active Bit 27" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE26 ,Set/Clear Active Bit 26" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE25 ,Set/Clear Active Bit 25" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE24 ,Set/Clear Active Bit 24" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE23 ,Set/Clear Active Bit 23" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE22 ,Set/Clear Active Bit 22" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE21 ,Set/Clear Active Bit 21" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE20 ,Set/Clear Active Bit 20" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE19 ,Set/Clear Active Bit 19" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE18 ,Set/Clear Active Bit 18" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE17 ,Set/Clear Active Bit 17" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE16 ,Set/Clear Active Bit 16" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE15 ,Set/Clear Active Bit 15" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE14 ,Set/Clear Active Bit 14" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE13 ,Set/Clear Active Bit 13" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE12 ,Set/Clear Active Bit 12" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE11 ,Set/Clear Active Bit 11" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE10 ,Set/Clear Active Bit 10" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE9 ,Set/Clear Active Bit 9" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE8 ,Set/Clear Active Bit 8" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE7 ,Set/Clear Active Bit 7" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE6 ,Set/Clear Active Bit 6" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE5 ,Set/Clear Active Bit 5" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE4 ,Set/Clear Active Bit 4" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE3 ,Set/Clear Active Bit 3" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE2 ,Set/Clear Active Bit 2" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE1 ,Set/Clear Active Bit 1" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE0 ,Set/Clear Active Bit 0" "Not active,Active" if (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x01) group.long 0x0304++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER1,Interrupt Set/Clear Active Register 1" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE63 ,Set/Clear Active Bit 63" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE62 ,Set/Clear Active Bit 62" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE61 ,Set/Clear Active Bit 61" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE60 ,Set/Clear Active Bit 60" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE59 ,Set/Clear Active Bit 59" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE58 ,Set/Clear Active Bit 58" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE57 ,Set/Clear Active Bit 57" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE56 ,Set/Clear Active Bit 56" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE55 ,Set/Clear Active Bit 55" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE54 ,Set/Clear Active Bit 54" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE53 ,Set/Clear Active Bit 53" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE52 ,Set/Clear Active Bit 52" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE51 ,Set/Clear Active Bit 51" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE50 ,Set/Clear Active Bit 50" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE49 ,Set/Clear Active Bit 49" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE48 ,Set/Clear Active Bit 48" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE47 ,Set/Clear Active Bit 47" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE46 ,Set/Clear Active Bit 46" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE45 ,Set/Clear Active Bit 45" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE44 ,Set/Clear Active Bit 44" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE43 ,Set/Clear Active Bit 43" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE42 ,Set/Clear Active Bit 42" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE41 ,Set/Clear Active Bit 41" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE40 ,Set/Clear Active Bit 40" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE39 ,Set/Clear Active Bit 39" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE38 ,Set/Clear Active Bit 38" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE37 ,Set/Clear Active Bit 37" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE36 ,Set/Clear Active Bit 36" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE35 ,Set/Clear Active Bit 35" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE34 ,Set/Clear Active Bit 34" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE33 ,Set/Clear Active Bit 33" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE32 ,Set/Clear Active Bit 32" "Not active,Active" else rgroup.long 0x0304++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER1,Interrupt Set/Clear Active Register 1" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x02) group.long 0x0308++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER2,Interrupt Set/Clear Active Register 2" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE95 ,Set/Clear Active Bit 95" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE94 ,Set/Clear Active Bit 94" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE93 ,Set/Clear Active Bit 93" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE92 ,Set/Clear Active Bit 92" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE91 ,Set/Clear Active Bit 91" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE90 ,Set/Clear Active Bit 90" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE89 ,Set/Clear Active Bit 89" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE88 ,Set/Clear Active Bit 88" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE87 ,Set/Clear Active Bit 87" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE86 ,Set/Clear Active Bit 86" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE85 ,Set/Clear Active Bit 85" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE84 ,Set/Clear Active Bit 84" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE83 ,Set/Clear Active Bit 83" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE82 ,Set/Clear Active Bit 82" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE81 ,Set/Clear Active Bit 81" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE80 ,Set/Clear Active Bit 80" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE79 ,Set/Clear Active Bit 79" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE78 ,Set/Clear Active Bit 78" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE77 ,Set/Clear Active Bit 77" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE76 ,Set/Clear Active Bit 76" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE75 ,Set/Clear Active Bit 75" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE74 ,Set/Clear Active Bit 74" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE73 ,Set/Clear Active Bit 73" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE72 ,Set/Clear Active Bit 72" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE71 ,Set/Clear Active Bit 71" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE70 ,Set/Clear Active Bit 70" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE69 ,Set/Clear Active Bit 69" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE68 ,Set/Clear Active Bit 68" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE67 ,Set/Clear Active Bit 67" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE66 ,Set/Clear Active Bit 66" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE65 ,Set/Clear Active Bit 65" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE64 ,Set/Clear Active Bit 64" "Not active,Active" else rgroup.long 0x0308++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER2,Interrupt Set/Clear Active Register 2" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x03) group.long 0x030C++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER3,Interrupt Set/Clear Active Register 3" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE127 ,Set/Clear Active Bit 127" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE126 ,Set/Clear Active Bit 126" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE125 ,Set/Clear Active Bit 125" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE124 ,Set/Clear Active Bit 124" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE123 ,Set/Clear Active Bit 123" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE122 ,Set/Clear Active Bit 122" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE121 ,Set/Clear Active Bit 121" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE120 ,Set/Clear Active Bit 120" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE119 ,Set/Clear Active Bit 119" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE118 ,Set/Clear Active Bit 118" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE117 ,Set/Clear Active Bit 117" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE116 ,Set/Clear Active Bit 116" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE115 ,Set/Clear Active Bit 115" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE114 ,Set/Clear Active Bit 114" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE113 ,Set/Clear Active Bit 113" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE112 ,Set/Clear Active Bit 112" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE111 ,Set/Clear Active Bit 111" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE110 ,Set/Clear Active Bit 110" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE109 ,Set/Clear Active Bit 109" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE108 ,Set/Clear Active Bit 108" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE107 ,Set/Clear Active Bit 107" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE106 ,Set/Clear Active Bit 106" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE105 ,Set/Clear Active Bit 105" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE104 ,Set/Clear Active Bit 104" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE103 ,Set/Clear Active Bit 103" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE102 ,Set/Clear Active Bit 102" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE101 ,Set/Clear Active Bit 101" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE100 ,Set/Clear Active Bit 100" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE99 ,Set/Clear Active Bit 99" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE98 ,Set/Clear Active Bit 98" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE97 ,Set/Clear Active Bit 97" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE96 ,Set/Clear Active Bit 96" "Not active,Active" else rgroup.long 0x030C++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER3,Interrupt Set/Clear Active Register 3" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x04) group.long 0x0310++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER4,Interrupt Set/Clear Active Register 4" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE159 ,Set/Clear Active Bit 159" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE158 ,Set/Clear Active Bit 158" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE157 ,Set/Clear Active Bit 157" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE156 ,Set/Clear Active Bit 156" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE155 ,Set/Clear Active Bit 155" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE154 ,Set/Clear Active Bit 154" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE153 ,Set/Clear Active Bit 153" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE152 ,Set/Clear Active Bit 152" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE151 ,Set/Clear Active Bit 151" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE150 ,Set/Clear Active Bit 150" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE149 ,Set/Clear Active Bit 149" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE148 ,Set/Clear Active Bit 148" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE147 ,Set/Clear Active Bit 147" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE146 ,Set/Clear Active Bit 146" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE145 ,Set/Clear Active Bit 145" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE144 ,Set/Clear Active Bit 144" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE143 ,Set/Clear Active Bit 143" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE142 ,Set/Clear Active Bit 142" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE141 ,Set/Clear Active Bit 141" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE140 ,Set/Clear Active Bit 140" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE139 ,Set/Clear Active Bit 139" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE138 ,Set/Clear Active Bit 138" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE137 ,Set/Clear Active Bit 137" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE136 ,Set/Clear Active Bit 136" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE135 ,Set/Clear Active Bit 135" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE134 ,Set/Clear Active Bit 134" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE133 ,Set/Clear Active Bit 133" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE132 ,Set/Clear Active Bit 132" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE131 ,Set/Clear Active Bit 131" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE130 ,Set/Clear Active Bit 130" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE129 ,Set/Clear Active Bit 129" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE128 ,Set/Clear Active Bit 128" "Not active,Active" else rgroup.long 0x0310++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER4,Interrupt Set/Clear Active Register 4" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x05) group.long 0x0314++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER5,Interrupt Set/Clear Active Register 5" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE191 ,Set/Clear Active Bit 191" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE190 ,Set/Clear Active Bit 190" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE189 ,Set/Clear Active Bit 189" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE188 ,Set/Clear Active Bit 188" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE187 ,Set/Clear Active Bit 187" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE186 ,Set/Clear Active Bit 186" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE185 ,Set/Clear Active Bit 185" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE184 ,Set/Clear Active Bit 184" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE183 ,Set/Clear Active Bit 183" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE182 ,Set/Clear Active Bit 182" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE181 ,Set/Clear Active Bit 181" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE180 ,Set/Clear Active Bit 180" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE179 ,Set/Clear Active Bit 179" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE178 ,Set/Clear Active Bit 178" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE177 ,Set/Clear Active Bit 177" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE176 ,Set/Clear Active Bit 176" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE175 ,Set/Clear Active Bit 175" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE174 ,Set/Clear Active Bit 174" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE173 ,Set/Clear Active Bit 173" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE172 ,Set/Clear Active Bit 172" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE171 ,Set/Clear Active Bit 171" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE170 ,Set/Clear Active Bit 170" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE169 ,Set/Clear Active Bit 169" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE168 ,Set/Clear Active Bit 168" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE167 ,Set/Clear Active Bit 167" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE166 ,Set/Clear Active Bit 166" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE165 ,Set/Clear Active Bit 165" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE164 ,Set/Clear Active Bit 164" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE163 ,Set/Clear Active Bit 163" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE162 ,Set/Clear Active Bit 162" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE161 ,Set/Clear Active Bit 161" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE160 ,Set/Clear Active Bit 160" "Not active,Active" else rgroup.long 0x0314++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER5,Interrupt Set/Clear Active Register 5" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x06) group.long 0x0318++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER6,Interrupt Set/Clear Active Register 6" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE223 ,Set/Clear Active Bit 223" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE222 ,Set/Clear Active Bit 222" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE221 ,Set/Clear Active Bit 221" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE220 ,Set/Clear Active Bit 220" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE219 ,Set/Clear Active Bit 219" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE218 ,Set/Clear Active Bit 218" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE217 ,Set/Clear Active Bit 217" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE216 ,Set/Clear Active Bit 216" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE215 ,Set/Clear Active Bit 215" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE214 ,Set/Clear Active Bit 214" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE213 ,Set/Clear Active Bit 213" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE212 ,Set/Clear Active Bit 212" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE211 ,Set/Clear Active Bit 211" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE210 ,Set/Clear Active Bit 210" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE209 ,Set/Clear Active Bit 209" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE208 ,Set/Clear Active Bit 208" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE207 ,Set/Clear Active Bit 207" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE206 ,Set/Clear Active Bit 206" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE205 ,Set/Clear Active Bit 205" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE204 ,Set/Clear Active Bit 204" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE203 ,Set/Clear Active Bit 203" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE202 ,Set/Clear Active Bit 202" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE201 ,Set/Clear Active Bit 201" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE200 ,Set/Clear Active Bit 200" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE199 ,Set/Clear Active Bit 199" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE198 ,Set/Clear Active Bit 198" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE197 ,Set/Clear Active Bit 197" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE196 ,Set/Clear Active Bit 196" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE195 ,Set/Clear Active Bit 195" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE194 ,Set/Clear Active Bit 194" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE193 ,Set/Clear Active Bit 193" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE192 ,Set/Clear Active Bit 192" "Not active,Active" else rgroup.long 0x0318++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER6,Interrupt Set/Clear Active Register 6" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x07) group.long 0x031C++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER7,Interrupt Set/Clear Active Register 7" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE255 ,Set/Clear Active Bit 255" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE254 ,Set/Clear Active Bit 254" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE253 ,Set/Clear Active Bit 253" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE252 ,Set/Clear Active Bit 252" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE251 ,Set/Clear Active Bit 251" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE250 ,Set/Clear Active Bit 250" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE249 ,Set/Clear Active Bit 249" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE248 ,Set/Clear Active Bit 248" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE247 ,Set/Clear Active Bit 247" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE246 ,Set/Clear Active Bit 246" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE245 ,Set/Clear Active Bit 245" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE244 ,Set/Clear Active Bit 244" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE243 ,Set/Clear Active Bit 243" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE242 ,Set/Clear Active Bit 242" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE241 ,Set/Clear Active Bit 241" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE240 ,Set/Clear Active Bit 240" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE239 ,Set/Clear Active Bit 239" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE238 ,Set/Clear Active Bit 238" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE237 ,Set/Clear Active Bit 237" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE236 ,Set/Clear Active Bit 236" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE235 ,Set/Clear Active Bit 235" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE234 ,Set/Clear Active Bit 234" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE233 ,Set/Clear Active Bit 233" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE232 ,Set/Clear Active Bit 232" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE231 ,Set/Clear Active Bit 231" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE230 ,Set/Clear Active Bit 230" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE229 ,Set/Clear Active Bit 229" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE228 ,Set/Clear Active Bit 228" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE227 ,Set/Clear Active Bit 227" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE226 ,Set/Clear Active Bit 226" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE225 ,Set/Clear Active Bit 225" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE224 ,Set/Clear Active Bit 224" "Not active,Active" else rgroup.long 0x031C++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER7,Interrupt Set/Clear Active Register 7" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x08) group.long 0x0320++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER8,Interrupt Set/Clear Active Register 8" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE287 ,Set/Clear Active Bit 287" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE286 ,Set/Clear Active Bit 286" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE285 ,Set/Clear Active Bit 285" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE284 ,Set/Clear Active Bit 284" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE283 ,Set/Clear Active Bit 283" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE282 ,Set/Clear Active Bit 282" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE281 ,Set/Clear Active Bit 281" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE280 ,Set/Clear Active Bit 280" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE279 ,Set/Clear Active Bit 279" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE278 ,Set/Clear Active Bit 278" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE277 ,Set/Clear Active Bit 277" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE276 ,Set/Clear Active Bit 276" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE275 ,Set/Clear Active Bit 275" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE274 ,Set/Clear Active Bit 274" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE273 ,Set/Clear Active Bit 273" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE272 ,Set/Clear Active Bit 272" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE271 ,Set/Clear Active Bit 271" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE270 ,Set/Clear Active Bit 270" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE269 ,Set/Clear Active Bit 269" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE268 ,Set/Clear Active Bit 268" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE267 ,Set/Clear Active Bit 267" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE266 ,Set/Clear Active Bit 266" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE265 ,Set/Clear Active Bit 265" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE264 ,Set/Clear Active Bit 264" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE263 ,Set/Clear Active Bit 263" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE262 ,Set/Clear Active Bit 262" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE261 ,Set/Clear Active Bit 261" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE260 ,Set/Clear Active Bit 260" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE259 ,Set/Clear Active Bit 259" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE258 ,Set/Clear Active Bit 258" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE257 ,Set/Clear Active Bit 257" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE256 ,Set/Clear Active Bit 256" "Not active,Active" else rgroup.long 0x0320++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER8,Interrupt Set/Clear Active Register 8" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x09) group.long 0x0324++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER9,Interrupt Set/Clear Active Register 9" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE319 ,Set/Clear Active Bit 319" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE318 ,Set/Clear Active Bit 318" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE317 ,Set/Clear Active Bit 317" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE316 ,Set/Clear Active Bit 316" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE315 ,Set/Clear Active Bit 315" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE314 ,Set/Clear Active Bit 314" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE313 ,Set/Clear Active Bit 313" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE312 ,Set/Clear Active Bit 312" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE311 ,Set/Clear Active Bit 311" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE310 ,Set/Clear Active Bit 310" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE309 ,Set/Clear Active Bit 309" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE308 ,Set/Clear Active Bit 308" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE307 ,Set/Clear Active Bit 307" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE306 ,Set/Clear Active Bit 306" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE305 ,Set/Clear Active Bit 305" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE304 ,Set/Clear Active Bit 304" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE303 ,Set/Clear Active Bit 303" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE302 ,Set/Clear Active Bit 302" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE301 ,Set/Clear Active Bit 301" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE300 ,Set/Clear Active Bit 300" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE299 ,Set/Clear Active Bit 299" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE298 ,Set/Clear Active Bit 298" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE297 ,Set/Clear Active Bit 297" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE296 ,Set/Clear Active Bit 296" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE295 ,Set/Clear Active Bit 295" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE294 ,Set/Clear Active Bit 294" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE293 ,Set/Clear Active Bit 293" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE292 ,Set/Clear Active Bit 292" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE291 ,Set/Clear Active Bit 291" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE290 ,Set/Clear Active Bit 290" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE289 ,Set/Clear Active Bit 289" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE288 ,Set/Clear Active Bit 288" "Not active,Active" else rgroup.long 0x0324++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER9,Interrupt Set/Clear Active Register 9" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x0A) group.long 0x0328++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER10,Interrupt Set/Clear Active Register 10" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE351 ,Set/Clear Active Bit 351" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE350 ,Set/Clear Active Bit 350" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE349 ,Set/Clear Active Bit 349" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE348 ,Set/Clear Active Bit 348" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE347 ,Set/Clear Active Bit 347" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE346 ,Set/Clear Active Bit 346" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE345 ,Set/Clear Active Bit 345" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE344 ,Set/Clear Active Bit 344" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE343 ,Set/Clear Active Bit 343" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE342 ,Set/Clear Active Bit 342" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE341 ,Set/Clear Active Bit 341" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE340 ,Set/Clear Active Bit 340" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE339 ,Set/Clear Active Bit 339" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE338 ,Set/Clear Active Bit 338" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE337 ,Set/Clear Active Bit 337" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE336 ,Set/Clear Active Bit 336" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE335 ,Set/Clear Active Bit 335" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE334 ,Set/Clear Active Bit 334" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE333 ,Set/Clear Active Bit 333" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE332 ,Set/Clear Active Bit 332" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE331 ,Set/Clear Active Bit 331" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE330 ,Set/Clear Active Bit 330" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE329 ,Set/Clear Active Bit 329" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE328 ,Set/Clear Active Bit 328" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE327 ,Set/Clear Active Bit 327" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE326 ,Set/Clear Active Bit 326" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE325 ,Set/Clear Active Bit 325" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE324 ,Set/Clear Active Bit 324" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE323 ,Set/Clear Active Bit 323" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE322 ,Set/Clear Active Bit 322" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE321 ,Set/Clear Active Bit 321" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE320 ,Set/Clear Active Bit 320" "Not active,Active" else rgroup.long 0x0328++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER10,Interrupt Set/Clear Active Register 10" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x0B) group.long 0x032C++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER11,Interrupt Set/Clear Active Register 11" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE383 ,Set/Clear Active Bit 383" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE382 ,Set/Clear Active Bit 382" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE381 ,Set/Clear Active Bit 381" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE380 ,Set/Clear Active Bit 380" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE379 ,Set/Clear Active Bit 379" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE378 ,Set/Clear Active Bit 378" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE377 ,Set/Clear Active Bit 377" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE376 ,Set/Clear Active Bit 376" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE375 ,Set/Clear Active Bit 375" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE374 ,Set/Clear Active Bit 374" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE373 ,Set/Clear Active Bit 373" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE372 ,Set/Clear Active Bit 372" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE371 ,Set/Clear Active Bit 371" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE370 ,Set/Clear Active Bit 370" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE369 ,Set/Clear Active Bit 369" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE368 ,Set/Clear Active Bit 368" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE367 ,Set/Clear Active Bit 367" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE366 ,Set/Clear Active Bit 366" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE365 ,Set/Clear Active Bit 365" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE364 ,Set/Clear Active Bit 364" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE363 ,Set/Clear Active Bit 363" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE362 ,Set/Clear Active Bit 362" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE361 ,Set/Clear Active Bit 361" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE360 ,Set/Clear Active Bit 360" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE359 ,Set/Clear Active Bit 359" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE358 ,Set/Clear Active Bit 358" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE357 ,Set/Clear Active Bit 357" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE356 ,Set/Clear Active Bit 356" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE355 ,Set/Clear Active Bit 355" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE354 ,Set/Clear Active Bit 354" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE353 ,Set/Clear Active Bit 353" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE352 ,Set/Clear Active Bit 352" "Not active,Active" else rgroup.long 0x032C++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER11,Interrupt Set/Clear Active Register 11" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x0C) group.long 0x0330++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER12,Interrupt Set/Clear Active Register 12" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE415 ,Set/Clear Active Bit 415" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE414 ,Set/Clear Active Bit 414" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE413 ,Set/Clear Active Bit 413" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE412 ,Set/Clear Active Bit 412" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE411 ,Set/Clear Active Bit 411" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE410 ,Set/Clear Active Bit 410" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE409 ,Set/Clear Active Bit 409" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE408 ,Set/Clear Active Bit 408" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE407 ,Set/Clear Active Bit 407" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE406 ,Set/Clear Active Bit 406" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE405 ,Set/Clear Active Bit 405" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE404 ,Set/Clear Active Bit 404" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE403 ,Set/Clear Active Bit 403" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE402 ,Set/Clear Active Bit 402" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE401 ,Set/Clear Active Bit 401" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE400 ,Set/Clear Active Bit 400" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE399 ,Set/Clear Active Bit 399" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE398 ,Set/Clear Active Bit 398" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE397 ,Set/Clear Active Bit 397" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE396 ,Set/Clear Active Bit 396" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE395 ,Set/Clear Active Bit 395" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE394 ,Set/Clear Active Bit 394" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE393 ,Set/Clear Active Bit 393" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE392 ,Set/Clear Active Bit 392" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE391 ,Set/Clear Active Bit 391" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE390 ,Set/Clear Active Bit 390" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE389 ,Set/Clear Active Bit 389" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE388 ,Set/Clear Active Bit 388" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE387 ,Set/Clear Active Bit 387" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE386 ,Set/Clear Active Bit 386" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE385 ,Set/Clear Active Bit 385" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE384 ,Set/Clear Active Bit 384" "Not active,Active" else rgroup.long 0x0330++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER12,Interrupt Set/Clear Active Register 12" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x0D) group.long 0x0334++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER13,Interrupt Set/Clear Active Register 13" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE447 ,Set/Clear Active Bit 447" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE446 ,Set/Clear Active Bit 446" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE445 ,Set/Clear Active Bit 445" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE444 ,Set/Clear Active Bit 444" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE443 ,Set/Clear Active Bit 443" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE442 ,Set/Clear Active Bit 442" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE441 ,Set/Clear Active Bit 441" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE440 ,Set/Clear Active Bit 440" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE439 ,Set/Clear Active Bit 439" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE438 ,Set/Clear Active Bit 438" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE437 ,Set/Clear Active Bit 437" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE436 ,Set/Clear Active Bit 436" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE435 ,Set/Clear Active Bit 435" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE434 ,Set/Clear Active Bit 434" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE433 ,Set/Clear Active Bit 433" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE432 ,Set/Clear Active Bit 432" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE431 ,Set/Clear Active Bit 431" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE430 ,Set/Clear Active Bit 430" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE429 ,Set/Clear Active Bit 429" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE428 ,Set/Clear Active Bit 428" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE427 ,Set/Clear Active Bit 427" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE426 ,Set/Clear Active Bit 426" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE425 ,Set/Clear Active Bit 425" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE424 ,Set/Clear Active Bit 424" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE423 ,Set/Clear Active Bit 423" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE422 ,Set/Clear Active Bit 422" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE421 ,Set/Clear Active Bit 421" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE420 ,Set/Clear Active Bit 420" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE419 ,Set/Clear Active Bit 419" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE418 ,Set/Clear Active Bit 418" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE417 ,Set/Clear Active Bit 417" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE416 ,Set/Clear Active Bit 416" "Not active,Active" else rgroup.long 0x0334++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER13,Interrupt Set/Clear Active Register 13" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x0E) group.long 0x0338++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER14,Interrupt Set/Clear Active Register 14" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE479 ,Set/Clear Active Bit 479" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE478 ,Set/Clear Active Bit 478" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE477 ,Set/Clear Active Bit 477" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE476 ,Set/Clear Active Bit 476" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE475 ,Set/Clear Active Bit 475" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE474 ,Set/Clear Active Bit 474" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE473 ,Set/Clear Active Bit 473" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE472 ,Set/Clear Active Bit 472" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE471 ,Set/Clear Active Bit 471" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE470 ,Set/Clear Active Bit 470" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE469 ,Set/Clear Active Bit 469" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE468 ,Set/Clear Active Bit 468" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE467 ,Set/Clear Active Bit 467" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE466 ,Set/Clear Active Bit 466" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE465 ,Set/Clear Active Bit 465" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE464 ,Set/Clear Active Bit 464" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE463 ,Set/Clear Active Bit 463" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE462 ,Set/Clear Active Bit 462" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE461 ,Set/Clear Active Bit 461" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE460 ,Set/Clear Active Bit 460" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE459 ,Set/Clear Active Bit 459" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE458 ,Set/Clear Active Bit 458" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE457 ,Set/Clear Active Bit 457" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE456 ,Set/Clear Active Bit 456" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE455 ,Set/Clear Active Bit 455" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE454 ,Set/Clear Active Bit 454" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE453 ,Set/Clear Active Bit 453" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE452 ,Set/Clear Active Bit 452" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE451 ,Set/Clear Active Bit 451" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE450 ,Set/Clear Active Bit 450" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE449 ,Set/Clear Active Bit 449" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE448 ,Set/Clear Active Bit 448" "Not active,Active" else rgroup.long 0x0338++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER14,Interrupt Set/Clear Active Register 14" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x0F) group.long 0x033C++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER15,Interrupt Set/Clear Active Register 15" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE511 ,Set/Clear Active Bit 511" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE510 ,Set/Clear Active Bit 510" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE509 ,Set/Clear Active Bit 509" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE508 ,Set/Clear Active Bit 508" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE507 ,Set/Clear Active Bit 507" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE506 ,Set/Clear Active Bit 506" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE505 ,Set/Clear Active Bit 505" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE504 ,Set/Clear Active Bit 504" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE503 ,Set/Clear Active Bit 503" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE502 ,Set/Clear Active Bit 502" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE501 ,Set/Clear Active Bit 501" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE500 ,Set/Clear Active Bit 500" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE499 ,Set/Clear Active Bit 499" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE498 ,Set/Clear Active Bit 498" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE497 ,Set/Clear Active Bit 497" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE496 ,Set/Clear Active Bit 496" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE495 ,Set/Clear Active Bit 495" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE494 ,Set/Clear Active Bit 494" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE493 ,Set/Clear Active Bit 493" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE492 ,Set/Clear Active Bit 492" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE491 ,Set/Clear Active Bit 491" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE490 ,Set/Clear Active Bit 490" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE489 ,Set/Clear Active Bit 489" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE488 ,Set/Clear Active Bit 488" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE487 ,Set/Clear Active Bit 487" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE486 ,Set/Clear Active Bit 486" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE485 ,Set/Clear Active Bit 485" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE484 ,Set/Clear Active Bit 484" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE483 ,Set/Clear Active Bit 483" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE482 ,Set/Clear Active Bit 482" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE481 ,Set/Clear Active Bit 481" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE480 ,Set/Clear Active Bit 480" "Not active,Active" else rgroup.long 0x033C++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER15,Interrupt Set/Clear Active Register 15" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif rgroup.long 0x0340++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER16,Interrupt Set/Clear Active Register 16" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " rgroup.long 0x0344++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER17,Interrupt Set/Clear Active Register 17" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " rgroup.long 0x0348++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER18,Interrupt Set/Clear Active Register 18" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " rgroup.long 0x034C++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER19,Interrupt Set/Clear Active Register 19" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " rgroup.long 0x0350++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER20,Interrupt Set/Clear Active Register 20" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " rgroup.long 0x0354++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER21,Interrupt Set/Clear Active Register 21" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " rgroup.long 0x0358++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER22,Interrupt Set/Clear Active Register 22" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " rgroup.long 0x035C++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER23,Interrupt Set/Clear Active Register 23" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " rgroup.long 0x0360++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER24,Interrupt Set/Clear Active Register 24" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " rgroup.long 0x0364++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER25,Interrupt Set/Clear Active Register 25" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " rgroup.long 0x0368++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER26,Interrupt Set/Clear Active Register 26" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " rgroup.long 0x036C++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER27,Interrupt Set/Clear Active Register 27" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " rgroup.long 0x0370++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER28,Interrupt Set/Clear Active Register 28" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " rgroup.long 0x0374++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER29,Interrupt Set/Clear Active Register 29" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " rgroup.long 0x0378++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER30,Interrupt Set/Clear Active Register 30" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " rgroup.long 0x037C++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER31,Interrupt Set/Clear Active Register 31" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif tree.end tree "Priority Registers" group.long 0x400++0x03 line.long 0x00 "GICD_IPRIORITYR0,Interrupt Priority Register 0" hexmask.long.byte 0x00 24.--31. 1. " INTID3 ,Interrupt ID3 Priority/Priority Byte Offset 3 " hexmask.long.byte 0x00 16.--23. 1. " INTID2 ,Interrupt ID2 Priority/Priority Byte Offset 2 " hexmask.long.byte 0x00 8.--15. 1. " INTID1 ,Interrupt ID1 Priority/Priority Byte Offset 1 " hexmask.long.byte 0x00 0.--7. 1. " INTID0 ,Interrupt ID0 Priority/Priority Byte Offset 0 " group.long 0x404++0x03 line.long 0x00 "GICD_IPRIORITYR1,Interrupt Priority Register 1" hexmask.long.byte 0x00 24.--31. 1. " INTID7 ,Interrupt ID7 Priority/Priority Byte Offset 7 " hexmask.long.byte 0x00 16.--23. 1. " INTID6 ,Interrupt ID6 Priority/Priority Byte Offset 6 " hexmask.long.byte 0x00 8.--15. 1. " INTID5 ,Interrupt ID5 Priority/Priority Byte Offset 5 " hexmask.long.byte 0x00 0.--7. 1. " INTID4 ,Interrupt ID4 Priority/Priority Byte Offset 4 " group.long 0x408++0x03 line.long 0x00 "GICD_IPRIORITYR2,Interrupt Priority Register 2" hexmask.long.byte 0x00 24.--31. 1. " INTID11 ,Interrupt ID11 Priority/Priority Byte Offset 11 " hexmask.long.byte 0x00 16.--23. 1. " INTID10 ,Interrupt ID10 Priority/Priority Byte Offset 10 " hexmask.long.byte 0x00 8.--15. 1. " INTID9 ,Interrupt ID9 Priority/Priority Byte Offset 9 " hexmask.long.byte 0x00 0.--7. 1. " INTID8 ,Interrupt ID8 Priority/Priority Byte Offset 8 " group.long 0x40C++0x03 line.long 0x00 "GICD_IPRIORITYR3,Interrupt Priority Register 3" hexmask.long.byte 0x00 24.--31. 1. " INTID15 ,Interrupt ID15 Priority/Priority Byte Offset 15 " hexmask.long.byte 0x00 16.--23. 1. " INTID14 ,Interrupt ID14 Priority/Priority Byte Offset 14 " hexmask.long.byte 0x00 8.--15. 1. " INTID13 ,Interrupt ID13 Priority/Priority Byte Offset 13 " hexmask.long.byte 0x00 0.--7. 1. " INTID12 ,Interrupt ID12 Priority/Priority Byte Offset 12 " group.long 0x410++0x03 line.long 0x00 "GICD_IPRIORITYR4,Interrupt Priority Register 4" hexmask.long.byte 0x00 24.--31. 1. " INTID19 ,Interrupt ID19 Priority/Priority Byte Offset 19 " hexmask.long.byte 0x00 16.--23. 1. " INTID18 ,Interrupt ID18 Priority/Priority Byte Offset 18 " hexmask.long.byte 0x00 8.--15. 1. " INTID17 ,Interrupt ID17 Priority/Priority Byte Offset 17 " hexmask.long.byte 0x00 0.--7. 1. " INTID16 ,Interrupt ID16 Priority/Priority Byte Offset 16 " group.long 0x414++0x03 line.long 0x00 "GICD_IPRIORITYR5,Interrupt Priority Register 5" hexmask.long.byte 0x00 24.--31. 1. " INTID23 ,Interrupt ID23 Priority/Priority Byte Offset 23 " hexmask.long.byte 0x00 16.--23. 1. " INTID22 ,Interrupt ID22 Priority/Priority Byte Offset 22 " hexmask.long.byte 0x00 8.--15. 1. " INTID21 ,Interrupt ID21 Priority/Priority Byte Offset 21 " hexmask.long.byte 0x00 0.--7. 1. " INTID20 ,Interrupt ID20 Priority/Priority Byte Offset 20 " group.long 0x418++0x03 line.long 0x00 "GICD_IPRIORITYR6,Interrupt Priority Register 6" hexmask.long.byte 0x00 24.--31. 1. " INTID27 ,Interrupt ID27 Priority/Priority Byte Offset 27 " hexmask.long.byte 0x00 16.--23. 1. " INTID26 ,Interrupt ID26 Priority/Priority Byte Offset 26 " hexmask.long.byte 0x00 8.--15. 1. " INTID25 ,Interrupt ID25 Priority/Priority Byte Offset 25 " hexmask.long.byte 0x00 0.--7. 1. " INTID24 ,Interrupt ID24 Priority/Priority Byte Offset 24 " group.long 0x41C++0x03 line.long 0x00 "GICD_IPRIORITYR7,Interrupt Priority Register 7" hexmask.long.byte 0x00 24.--31. 1. " INTID31 ,Interrupt ID31 Priority/Priority Byte Offset 31 " hexmask.long.byte 0x00 16.--23. 1. " INTID30 ,Interrupt ID30 Priority/Priority Byte Offset 30 " hexmask.long.byte 0x00 8.--15. 1. " INTID29 ,Interrupt ID29 Priority/Priority Byte Offset 29 " hexmask.long.byte 0x00 0.--7. 1. " INTID28 ,Interrupt ID28 Priority/Priority Byte Offset 28 " if (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x01) group.long 0x420++0x03 line.long 0x00 "GICD_IPRIORITYR8,Interrupt Priority Register 8" hexmask.long.byte 0x00 24.--31. 1. " INTID35 ,Interrupt ID35 Priority/Priority Byte Offset 35 " hexmask.long.byte 0x00 16.--23. 1. " INTID34 ,Interrupt ID34 Priority/Priority Byte Offset 34 " hexmask.long.byte 0x00 8.--15. 1. " INTID33 ,Interrupt ID33 Priority/Priority Byte Offset 33 " hexmask.long.byte 0x00 0.--7. 1. " INTID32 ,Interrupt ID32 Priority/Priority Byte Offset 32 " group.long 0x424++0x03 line.long 0x00 "GICD_IPRIORITYR9,Interrupt Priority Register 9" hexmask.long.byte 0x00 24.--31. 1. " INTID39 ,Interrupt ID39 Priority/Priority Byte Offset 39 " hexmask.long.byte 0x00 16.--23. 1. " INTID38 ,Interrupt ID38 Priority/Priority Byte Offset 38 " hexmask.long.byte 0x00 8.--15. 1. " INTID37 ,Interrupt ID37 Priority/Priority Byte Offset 37 " hexmask.long.byte 0x00 0.--7. 1. " INTID36 ,Interrupt ID36 Priority/Priority Byte Offset 36 " group.long 0x428++0x03 line.long 0x00 "GICD_IPRIORITYR10,Interrupt Priority Register 10" hexmask.long.byte 0x00 24.--31. 1. " INTID43 ,Interrupt ID43 Priority/Priority Byte Offset 43 " hexmask.long.byte 0x00 16.--23. 1. " INTID42 ,Interrupt ID42 Priority/Priority Byte Offset 42 " hexmask.long.byte 0x00 8.--15. 1. " INTID41 ,Interrupt ID41 Priority/Priority Byte Offset 41 " hexmask.long.byte 0x00 0.--7. 1. " INTID40 ,Interrupt ID40 Priority/Priority Byte Offset 40 " group.long 0x42C++0x03 line.long 0x00 "GICD_IPRIORITYR11,Interrupt Priority Register 11" hexmask.long.byte 0x00 24.--31. 1. " INTID47 ,Interrupt ID47 Priority/Priority Byte Offset 47 " hexmask.long.byte 0x00 16.--23. 1. " INTID46 ,Interrupt ID46 Priority/Priority Byte Offset 46 " hexmask.long.byte 0x00 8.--15. 1. " INTID45 ,Interrupt ID45 Priority/Priority Byte Offset 45 " hexmask.long.byte 0x00 0.--7. 1. " INTID44 ,Interrupt ID44 Priority/Priority Byte Offset 44 " group.long 0x430++0x03 line.long 0x00 "GICD_IPRIORITYR12,Interrupt Priority Register 12" hexmask.long.byte 0x00 24.--31. 1. " INTID51 ,Interrupt ID51 Priority/Priority Byte Offset 51 " hexmask.long.byte 0x00 16.--23. 1. " INTID50 ,Interrupt ID50 Priority/Priority Byte Offset 50 " hexmask.long.byte 0x00 8.--15. 1. " INTID49 ,Interrupt ID49 Priority/Priority Byte Offset 49 " hexmask.long.byte 0x00 0.--7. 1. " INTID48 ,Interrupt ID48 Priority/Priority Byte Offset 48 " group.long 0x434++0x03 line.long 0x00 "GICD_IPRIORITYR13,Interrupt Priority Register 13" hexmask.long.byte 0x00 24.--31. 1. " INTID55 ,Interrupt ID55 Priority/Priority Byte Offset 55 " hexmask.long.byte 0x00 16.--23. 1. " INTID54 ,Interrupt ID54 Priority/Priority Byte Offset 54 " hexmask.long.byte 0x00 8.--15. 1. " INTID53 ,Interrupt ID53 Priority/Priority Byte Offset 53 " hexmask.long.byte 0x00 0.--7. 1. " INTID52 ,Interrupt ID52 Priority/Priority Byte Offset 52 " group.long 0x438++0x03 line.long 0x00 "GICD_IPRIORITYR14,Interrupt Priority Register 14" hexmask.long.byte 0x00 24.--31. 1. " INTID59 ,Interrupt ID59 Priority/Priority Byte Offset 59 " hexmask.long.byte 0x00 16.--23. 1. " INTID58 ,Interrupt ID58 Priority/Priority Byte Offset 58 " hexmask.long.byte 0x00 8.--15. 1. " INTID57 ,Interrupt ID57 Priority/Priority Byte Offset 57 " hexmask.long.byte 0x00 0.--7. 1. " INTID56 ,Interrupt ID56 Priority/Priority Byte Offset 56 " group.long 0x43C++0x03 line.long 0x00 "GICD_IPRIORITYR15,Interrupt Priority Register 15" hexmask.long.byte 0x00 24.--31. 1. " INTID63 ,Interrupt ID63 Priority/Priority Byte Offset 63 " hexmask.long.byte 0x00 16.--23. 1. " INTID62 ,Interrupt ID62 Priority/Priority Byte Offset 62 " hexmask.long.byte 0x00 8.--15. 1. " INTID61 ,Interrupt ID61 Priority/Priority Byte Offset 61 " hexmask.long.byte 0x00 0.--7. 1. " INTID60 ,Interrupt ID60 Priority/Priority Byte Offset 60 " else rgroup.long 0x420++0x03 line.long 0x00 "GICD_IPRIORITYR8,Interrupt Priority Register 8" rgroup.long 0x424++0x03 line.long 0x00 "GICD_IPRIORITYR9,Interrupt Priority Register 9" rgroup.long 0x428++0x03 line.long 0x00 "GICD_IPRIORITYR10,Interrupt Priority Register 10" rgroup.long 0x42C++0x03 line.long 0x00 "GICD_IPRIORITYR11,Interrupt Priority Register 11" rgroup.long 0x430++0x03 line.long 0x00 "GICD_IPRIORITYR12,Interrupt Priority Register 12" rgroup.long 0x434++0x03 line.long 0x00 "GICD_IPRIORITYR13,Interrupt Priority Register 13" rgroup.long 0x438++0x03 line.long 0x00 "GICD_IPRIORITYR14,Interrupt Priority Register 14" rgroup.long 0x43C++0x03 line.long 0x00 "GICD_IPRIORITYR15,Interrupt Priority Register 15" endif if (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x02) group.long 0x440++0x03 line.long 0x00 "GICD_IPRIORITYR16,Interrupt Priority Register 16" hexmask.long.byte 0x00 24.--31. 1. " INTID67 ,Interrupt ID67 Priority/Priority Byte Offset 67 " hexmask.long.byte 0x00 16.--23. 1. " INTID66 ,Interrupt ID66 Priority/Priority Byte Offset 66 " hexmask.long.byte 0x00 8.--15. 1. " INTID65 ,Interrupt ID65 Priority/Priority Byte Offset 65 " hexmask.long.byte 0x00 0.--7. 1. " INTID64 ,Interrupt ID64 Priority/Priority Byte Offset 64 " group.long 0x444++0x03 line.long 0x00 "GICD_IPRIORITYR17,Interrupt Priority Register 17" hexmask.long.byte 0x00 24.--31. 1. " INTID71 ,Interrupt ID71 Priority/Priority Byte Offset 71 " hexmask.long.byte 0x00 16.--23. 1. " INTID70 ,Interrupt ID70 Priority/Priority Byte Offset 70 " hexmask.long.byte 0x00 8.--15. 1. " INTID69 ,Interrupt ID69 Priority/Priority Byte Offset 69 " hexmask.long.byte 0x00 0.--7. 1. " INTID68 ,Interrupt ID68 Priority/Priority Byte Offset 68 " group.long 0x448++0x03 line.long 0x00 "GICD_IPRIORITYR18,Interrupt Priority Register 18" hexmask.long.byte 0x00 24.--31. 1. " INTID75 ,Interrupt ID75 Priority/Priority Byte Offset 75 " hexmask.long.byte 0x00 16.--23. 1. " INTID74 ,Interrupt ID74 Priority/Priority Byte Offset 74 " hexmask.long.byte 0x00 8.--15. 1. " INTID73 ,Interrupt ID73 Priority/Priority Byte Offset 73 " hexmask.long.byte 0x00 0.--7. 1. " INTID72 ,Interrupt ID72 Priority/Priority Byte Offset 72 " group.long 0x44C++0x03 line.long 0x00 "GICD_IPRIORITYR19,Interrupt Priority Register 19" hexmask.long.byte 0x00 24.--31. 1. " INTID79 ,Interrupt ID79 Priority/Priority Byte Offset 79 " hexmask.long.byte 0x00 16.--23. 1. " INTID78 ,Interrupt ID78 Priority/Priority Byte Offset 78 " hexmask.long.byte 0x00 8.--15. 1. " INTID77 ,Interrupt ID77 Priority/Priority Byte Offset 77 " hexmask.long.byte 0x00 0.--7. 1. " INTID76 ,Interrupt ID76 Priority/Priority Byte Offset 76 " group.long 0x450++0x03 line.long 0x00 "GICD_IPRIORITYR20,Interrupt Priority Register 20" hexmask.long.byte 0x00 24.--31. 1. " INTID83 ,Interrupt ID83 Priority/Priority Byte Offset 83 " hexmask.long.byte 0x00 16.--23. 1. " INTID82 ,Interrupt ID82 Priority/Priority Byte Offset 82 " hexmask.long.byte 0x00 8.--15. 1. " INTID81 ,Interrupt ID81 Priority/Priority Byte Offset 81 " hexmask.long.byte 0x00 0.--7. 1. " INTID80 ,Interrupt ID80 Priority/Priority Byte Offset 80 " group.long 0x454++0x03 line.long 0x00 "GICD_IPRIORITYR21,Interrupt Priority Register 21" hexmask.long.byte 0x00 24.--31. 1. " INTID87 ,Interrupt ID87 Priority/Priority Byte Offset 87 " hexmask.long.byte 0x00 16.--23. 1. " INTID86 ,Interrupt ID86 Priority/Priority Byte Offset 86 " hexmask.long.byte 0x00 8.--15. 1. " INTID85 ,Interrupt ID85 Priority/Priority Byte Offset 85 " hexmask.long.byte 0x00 0.--7. 1. " INTID84 ,Interrupt ID84 Priority/Priority Byte Offset 84 " group.long 0x458++0x03 line.long 0x00 "GICD_IPRIORITYR22,Interrupt Priority Register 22" hexmask.long.byte 0x00 24.--31. 1. " INTID91 ,Interrupt ID91 Priority/Priority Byte Offset 91 " hexmask.long.byte 0x00 16.--23. 1. " INTID90 ,Interrupt ID90 Priority/Priority Byte Offset 90 " hexmask.long.byte 0x00 8.--15. 1. " INTID89 ,Interrupt ID89 Priority/Priority Byte Offset 89 " hexmask.long.byte 0x00 0.--7. 1. " INTID88 ,Interrupt ID88 Priority/Priority Byte Offset 88 " group.long 0x45C++0x03 line.long 0x00 "GICD_IPRIORITYR23,Interrupt Priority Register 23" hexmask.long.byte 0x00 24.--31. 1. " INTID95 ,Interrupt ID95 Priority/Priority Byte Offset 95 " hexmask.long.byte 0x00 16.--23. 1. " INTID94 ,Interrupt ID94 Priority/Priority Byte Offset 94 " hexmask.long.byte 0x00 8.--15. 1. " INTID93 ,Interrupt ID93 Priority/Priority Byte Offset 93 " hexmask.long.byte 0x00 0.--7. 1. " INTID92 ,Interrupt ID92 Priority/Priority Byte Offset 92 " else rgroup.long 0x440++0x03 line.long 0x00 "GICD_IPRIORITYR16,Interrupt Priority Register 16" rgroup.long 0x444++0x03 line.long 0x00 "GICD_IPRIORITYR17,Interrupt Priority Register 17" rgroup.long 0x448++0x03 line.long 0x00 "GICD_IPRIORITYR18,Interrupt Priority Register 18" rgroup.long 0x44C++0x03 line.long 0x00 "GICD_IPRIORITYR19,Interrupt Priority Register 19" rgroup.long 0x450++0x03 line.long 0x00 "GICD_IPRIORITYR20,Interrupt Priority Register 20" rgroup.long 0x454++0x03 line.long 0x00 "GICD_IPRIORITYR21,Interrupt Priority Register 21" rgroup.long 0x458++0x03 line.long 0x00 "GICD_IPRIORITYR22,Interrupt Priority Register 22" rgroup.long 0x45C++0x03 line.long 0x00 "GICD_IPRIORITYR23,Interrupt Priority Register 23" endif if (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x03) group.long 0x460++0x03 line.long 0x00 "GICD_IPRIORITYR24,Interrupt Priority Register 24" hexmask.long.byte 0x00 24.--31. 1. " INTID99 ,Interrupt ID99 Priority/Priority Byte Offset 99 " hexmask.long.byte 0x00 16.--23. 1. " INTID98 ,Interrupt ID98 Priority/Priority Byte Offset 98 " hexmask.long.byte 0x00 8.--15. 1. " INTID97 ,Interrupt ID97 Priority/Priority Byte Offset 97 " hexmask.long.byte 0x00 0.--7. 1. " INTID96 ,Interrupt ID96 Priority/Priority Byte Offset 96 " group.long 0x464++0x03 line.long 0x00 "GICD_IPRIORITYR25,Interrupt Priority Register 25" hexmask.long.byte 0x00 24.--31. 1. " INTID103 ,Interrupt ID103 Priority/Priority Byte Offset 103 " hexmask.long.byte 0x00 16.--23. 1. " INTID102 ,Interrupt ID102 Priority/Priority Byte Offset 102 " hexmask.long.byte 0x00 8.--15. 1. " INTID101 ,Interrupt ID101 Priority/Priority Byte Offset 101 " hexmask.long.byte 0x00 0.--7. 1. " INTID100 ,Interrupt ID100 Priority/Priority Byte Offset 100 " group.long 0x468++0x03 line.long 0x00 "GICD_IPRIORITYR26,Interrupt Priority Register 26" hexmask.long.byte 0x00 24.--31. 1. " INTID107 ,Interrupt ID107 Priority/Priority Byte Offset 107 " hexmask.long.byte 0x00 16.--23. 1. " INTID106 ,Interrupt ID106 Priority/Priority Byte Offset 106 " hexmask.long.byte 0x00 8.--15. 1. " INTID105 ,Interrupt ID105 Priority/Priority Byte Offset 105 " hexmask.long.byte 0x00 0.--7. 1. " INTID104 ,Interrupt ID104 Priority/Priority Byte Offset 104 " group.long 0x46C++0x03 line.long 0x00 "GICD_IPRIORITYR27,Interrupt Priority Register 27" hexmask.long.byte 0x00 24.--31. 1. " INTID111 ,Interrupt ID111 Priority/Priority Byte Offset 111 " hexmask.long.byte 0x00 16.--23. 1. " INTID110 ,Interrupt ID110 Priority/Priority Byte Offset 110 " hexmask.long.byte 0x00 8.--15. 1. " INTID109 ,Interrupt ID109 Priority/Priority Byte Offset 109 " hexmask.long.byte 0x00 0.--7. 1. " INTID108 ,Interrupt ID108 Priority/Priority Byte Offset 108 " group.long 0x470++0x03 line.long 0x00 "GICD_IPRIORITYR28,Interrupt Priority Register 28" hexmask.long.byte 0x00 24.--31. 1. " INTID115 ,Interrupt ID115 Priority/Priority Byte Offset 115 " hexmask.long.byte 0x00 16.--23. 1. " INTID114 ,Interrupt ID114 Priority/Priority Byte Offset 114 " hexmask.long.byte 0x00 8.--15. 1. " INTID113 ,Interrupt ID113 Priority/Priority Byte Offset 113 " hexmask.long.byte 0x00 0.--7. 1. " INTID112 ,Interrupt ID112 Priority/Priority Byte Offset 112 " group.long 0x474++0x03 line.long 0x00 "GICD_IPRIORITYR29,Interrupt Priority Register 29" hexmask.long.byte 0x00 24.--31. 1. " INTID119 ,Interrupt ID119 Priority/Priority Byte Offset 119 " hexmask.long.byte 0x00 16.--23. 1. " INTID118 ,Interrupt ID118 Priority/Priority Byte Offset 118 " hexmask.long.byte 0x00 8.--15. 1. " INTID117 ,Interrupt ID117 Priority/Priority Byte Offset 117 " hexmask.long.byte 0x00 0.--7. 1. " INTID116 ,Interrupt ID116 Priority/Priority Byte Offset 116 " group.long 0x478++0x03 line.long 0x00 "GICD_IPRIORITYR30,Interrupt Priority Register 30" hexmask.long.byte 0x00 24.--31. 1. " INTID123 ,Interrupt ID123 Priority/Priority Byte Offset 123 " hexmask.long.byte 0x00 16.--23. 1. " INTID122 ,Interrupt ID122 Priority/Priority Byte Offset 122 " hexmask.long.byte 0x00 8.--15. 1. " INTID121 ,Interrupt ID121 Priority/Priority Byte Offset 121 " hexmask.long.byte 0x00 0.--7. 1. " INTID120 ,Interrupt ID120 Priority/Priority Byte Offset 120 " group.long 0x47C++0x03 line.long 0x00 "GICD_IPRIORITYR31,Interrupt Priority Register 31" hexmask.long.byte 0x00 24.--31. 1. " INTID127 ,Interrupt ID127 Priority/Priority Byte Offset 127 " hexmask.long.byte 0x00 16.--23. 1. " INTID126 ,Interrupt ID126 Priority/Priority Byte Offset 126 " hexmask.long.byte 0x00 8.--15. 1. " INTID125 ,Interrupt ID125 Priority/Priority Byte Offset 125 " hexmask.long.byte 0x00 0.--7. 1. " INTID124 ,Interrupt ID124 Priority/Priority Byte Offset 124 " else rgroup.long 0x460++0x03 line.long 0x00 "GICD_IPRIORITYR24,Interrupt Priority Register 24" rgroup.long 0x464++0x03 line.long 0x00 "GICD_IPRIORITYR25,Interrupt Priority Register 25" rgroup.long 0x468++0x03 line.long 0x00 "GICD_IPRIORITYR26,Interrupt Priority Register 26" rgroup.long 0x46C++0x03 line.long 0x00 "GICD_IPRIORITYR27,Interrupt Priority Register 27" rgroup.long 0x470++0x03 line.long 0x00 "GICD_IPRIORITYR28,Interrupt Priority Register 28" rgroup.long 0x474++0x03 line.long 0x00 "GICD_IPRIORITYR29,Interrupt Priority Register 29" rgroup.long 0x478++0x03 line.long 0x00 "GICD_IPRIORITYR30,Interrupt Priority Register 30" rgroup.long 0x47C++0x03 line.long 0x00 "GICD_IPRIORITYR31,Interrupt Priority Register 31" endif if (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x04) group.long 0x480++0x03 line.long 0x00 "GICD_IPRIORITYR32,Interrupt Priority Register 32" hexmask.long.byte 0x00 24.--31. 1. " INTID131 ,Interrupt ID131 Priority/Priority Byte Offset 131 " hexmask.long.byte 0x00 16.--23. 1. " INTID130 ,Interrupt ID130 Priority/Priority Byte Offset 130 " hexmask.long.byte 0x00 8.--15. 1. " INTID129 ,Interrupt ID129 Priority/Priority Byte Offset 129 " hexmask.long.byte 0x00 0.--7. 1. " INTID128 ,Interrupt ID128 Priority/Priority Byte Offset 128 " group.long 0x484++0x03 line.long 0x00 "GICD_IPRIORITYR33,Interrupt Priority Register 33" hexmask.long.byte 0x00 24.--31. 1. " INTID135 ,Interrupt ID135 Priority/Priority Byte Offset 135 " hexmask.long.byte 0x00 16.--23. 1. " INTID134 ,Interrupt ID134 Priority/Priority Byte Offset 134 " hexmask.long.byte 0x00 8.--15. 1. " INTID133 ,Interrupt ID133 Priority/Priority Byte Offset 133 " hexmask.long.byte 0x00 0.--7. 1. " INTID132 ,Interrupt ID132 Priority/Priority Byte Offset 132 " group.long 0x488++0x03 line.long 0x00 "GICD_IPRIORITYR34,Interrupt Priority Register 34" hexmask.long.byte 0x00 24.--31. 1. " INTID139 ,Interrupt ID139 Priority/Priority Byte Offset 139 " hexmask.long.byte 0x00 16.--23. 1. " INTID138 ,Interrupt ID138 Priority/Priority Byte Offset 138 " hexmask.long.byte 0x00 8.--15. 1. " INTID137 ,Interrupt ID137 Priority/Priority Byte Offset 137 " hexmask.long.byte 0x00 0.--7. 1. " INTID136 ,Interrupt ID136 Priority/Priority Byte Offset 136 " group.long 0x48C++0x03 line.long 0x00 "GICD_IPRIORITYR35,Interrupt Priority Register 35" hexmask.long.byte 0x00 24.--31. 1. " INTID143 ,Interrupt ID143 Priority/Priority Byte Offset 143 " hexmask.long.byte 0x00 16.--23. 1. " INTID142 ,Interrupt ID142 Priority/Priority Byte Offset 142 " hexmask.long.byte 0x00 8.--15. 1. " INTID141 ,Interrupt ID141 Priority/Priority Byte Offset 141 " hexmask.long.byte 0x00 0.--7. 1. " INTID140 ,Interrupt ID140 Priority/Priority Byte Offset 140 " group.long 0x490++0x03 line.long 0x00 "GICD_IPRIORITYR36,Interrupt Priority Register 36" hexmask.long.byte 0x00 24.--31. 1. " INTID147 ,Interrupt ID147 Priority/Priority Byte Offset 147 " hexmask.long.byte 0x00 16.--23. 1. " INTID146 ,Interrupt ID146 Priority/Priority Byte Offset 146 " hexmask.long.byte 0x00 8.--15. 1. " INTID145 ,Interrupt ID145 Priority/Priority Byte Offset 145 " hexmask.long.byte 0x00 0.--7. 1. " INTID144 ,Interrupt ID144 Priority/Priority Byte Offset 144 " group.long 0x494++0x03 line.long 0x00 "GICD_IPRIORITYR37,Interrupt Priority Register 37" hexmask.long.byte 0x00 24.--31. 1. " INTID151 ,Interrupt ID151 Priority/Priority Byte Offset 151 " hexmask.long.byte 0x00 16.--23. 1. " INTID150 ,Interrupt ID150 Priority/Priority Byte Offset 150 " hexmask.long.byte 0x00 8.--15. 1. " INTID149 ,Interrupt ID149 Priority/Priority Byte Offset 149 " hexmask.long.byte 0x00 0.--7. 1. " INTID148 ,Interrupt ID148 Priority/Priority Byte Offset 148 " group.long 0x498++0x03 line.long 0x00 "GICD_IPRIORITYR38,Interrupt Priority Register 38" hexmask.long.byte 0x00 24.--31. 1. " INTID155 ,Interrupt ID155 Priority/Priority Byte Offset 155 " hexmask.long.byte 0x00 16.--23. 1. " INTID154 ,Interrupt ID154 Priority/Priority Byte Offset 154 " hexmask.long.byte 0x00 8.--15. 1. " INTID153 ,Interrupt ID153 Priority/Priority Byte Offset 153 " hexmask.long.byte 0x00 0.--7. 1. " INTID152 ,Interrupt ID152 Priority/Priority Byte Offset 152 " group.long 0x49C++0x03 line.long 0x00 "GICD_IPRIORITYR39,Interrupt Priority Register 39" hexmask.long.byte 0x00 24.--31. 1. " INTID159 ,Interrupt ID159 Priority/Priority Byte Offset 159 " hexmask.long.byte 0x00 16.--23. 1. " INTID158 ,Interrupt ID158 Priority/Priority Byte Offset 158 " hexmask.long.byte 0x00 8.--15. 1. " INTID157 ,Interrupt ID157 Priority/Priority Byte Offset 157 " hexmask.long.byte 0x00 0.--7. 1. " INTID156 ,Interrupt ID156 Priority/Priority Byte Offset 156 " else rgroup.long 0x480++0x03 line.long 0x00 "GICD_IPRIORITYR32,Interrupt Priority Register 32" rgroup.long 0x484++0x03 line.long 0x00 "GICD_IPRIORITYR33,Interrupt Priority Register 33" rgroup.long 0x488++0x03 line.long 0x00 "GICD_IPRIORITYR34,Interrupt Priority Register 34" rgroup.long 0x48C++0x03 line.long 0x00 "GICD_IPRIORITYR35,Interrupt Priority Register 35" rgroup.long 0x490++0x03 line.long 0x00 "GICD_IPRIORITYR36,Interrupt Priority Register 36" rgroup.long 0x494++0x03 line.long 0x00 "GICD_IPRIORITYR37,Interrupt Priority Register 37" rgroup.long 0x498++0x03 line.long 0x00 "GICD_IPRIORITYR38,Interrupt Priority Register 38" rgroup.long 0x49C++0x03 line.long 0x00 "GICD_IPRIORITYR39,Interrupt Priority Register 39" endif if (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x05) group.long 0x4A0++0x03 line.long 0x00 "GICD_IPRIORITYR40,Interrupt Priority Register 40" hexmask.long.byte 0x00 24.--31. 1. " INTID163 ,Interrupt ID163 Priority/Priority Byte Offset 163 " hexmask.long.byte 0x00 16.--23. 1. " INTID162 ,Interrupt ID162 Priority/Priority Byte Offset 162 " hexmask.long.byte 0x00 8.--15. 1. " INTID161 ,Interrupt ID161 Priority/Priority Byte Offset 161 " hexmask.long.byte 0x00 0.--7. 1. " INTID160 ,Interrupt ID160 Priority/Priority Byte Offset 160 " group.long 0x4A4++0x03 line.long 0x00 "GICD_IPRIORITYR41,Interrupt Priority Register 41" hexmask.long.byte 0x00 24.--31. 1. " INTID167 ,Interrupt ID167 Priority/Priority Byte Offset 167 " hexmask.long.byte 0x00 16.--23. 1. " INTID166 ,Interrupt ID166 Priority/Priority Byte Offset 166 " hexmask.long.byte 0x00 8.--15. 1. " INTID165 ,Interrupt ID165 Priority/Priority Byte Offset 165 " hexmask.long.byte 0x00 0.--7. 1. " INTID164 ,Interrupt ID164 Priority/Priority Byte Offset 164 " group.long 0x4A8++0x03 line.long 0x00 "GICD_IPRIORITYR42,Interrupt Priority Register 42" hexmask.long.byte 0x00 24.--31. 1. " INTID171 ,Interrupt ID171 Priority/Priority Byte Offset 171 " hexmask.long.byte 0x00 16.--23. 1. " INTID170 ,Interrupt ID170 Priority/Priority Byte Offset 170 " hexmask.long.byte 0x00 8.--15. 1. " INTID169 ,Interrupt ID169 Priority/Priority Byte Offset 169 " hexmask.long.byte 0x00 0.--7. 1. " INTID168 ,Interrupt ID168 Priority/Priority Byte Offset 168 " group.long 0x4AC++0x03 line.long 0x00 "GICD_IPRIORITYR43,Interrupt Priority Register 43" hexmask.long.byte 0x00 24.--31. 1. " INTID175 ,Interrupt ID175 Priority/Priority Byte Offset 175 " hexmask.long.byte 0x00 16.--23. 1. " INTID174 ,Interrupt ID174 Priority/Priority Byte Offset 174 " hexmask.long.byte 0x00 8.--15. 1. " INTID173 ,Interrupt ID173 Priority/Priority Byte Offset 173 " hexmask.long.byte 0x00 0.--7. 1. " INTID172 ,Interrupt ID172 Priority/Priority Byte Offset 172 " group.long 0x4B0++0x03 line.long 0x00 "GICD_IPRIORITYR44,Interrupt Priority Register 44" hexmask.long.byte 0x00 24.--31. 1. " INTID179 ,Interrupt ID179 Priority/Priority Byte Offset 179 " hexmask.long.byte 0x00 16.--23. 1. " INTID178 ,Interrupt ID178 Priority/Priority Byte Offset 178 " hexmask.long.byte 0x00 8.--15. 1. " INTID177 ,Interrupt ID177 Priority/Priority Byte Offset 177 " hexmask.long.byte 0x00 0.--7. 1. " INTID176 ,Interrupt ID176 Priority/Priority Byte Offset 176 " group.long 0x4B4++0x03 line.long 0x00 "GICD_IPRIORITYR45,Interrupt Priority Register 45" hexmask.long.byte 0x00 24.--31. 1. " INTID183 ,Interrupt ID183 Priority/Priority Byte Offset 183 " hexmask.long.byte 0x00 16.--23. 1. " INTID182 ,Interrupt ID182 Priority/Priority Byte Offset 182 " hexmask.long.byte 0x00 8.--15. 1. " INTID181 ,Interrupt ID181 Priority/Priority Byte Offset 181 " hexmask.long.byte 0x00 0.--7. 1. " INTID180 ,Interrupt ID180 Priority/Priority Byte Offset 180 " group.long 0x4B8++0x03 line.long 0x00 "GICD_IPRIORITYR46,Interrupt Priority Register 46" hexmask.long.byte 0x00 24.--31. 1. " INTID187 ,Interrupt ID187 Priority/Priority Byte Offset 187 " hexmask.long.byte 0x00 16.--23. 1. " INTID186 ,Interrupt ID186 Priority/Priority Byte Offset 186 " hexmask.long.byte 0x00 8.--15. 1. " INTID185 ,Interrupt ID185 Priority/Priority Byte Offset 185 " hexmask.long.byte 0x00 0.--7. 1. " INTID184 ,Interrupt ID184 Priority/Priority Byte Offset 184 " group.long 0x4BC++0x03 line.long 0x00 "GICD_IPRIORITYR47,Interrupt Priority Register 47" hexmask.long.byte 0x00 24.--31. 1. " INTID191 ,Interrupt ID191 Priority/Priority Byte Offset 191 " hexmask.long.byte 0x00 16.--23. 1. " INTID190 ,Interrupt ID190 Priority/Priority Byte Offset 190 " hexmask.long.byte 0x00 8.--15. 1. " INTID189 ,Interrupt ID189 Priority/Priority Byte Offset 189 " hexmask.long.byte 0x00 0.--7. 1. " INTID188 ,Interrupt ID188 Priority/Priority Byte Offset 188 " else rgroup.long 0x4A0++0x03 line.long 0x00 "GICD_IPRIORITYR40,Interrupt Priority Register 40" rgroup.long 0x4A4++0x03 line.long 0x00 "GICD_IPRIORITYR41,Interrupt Priority Register 41" rgroup.long 0x4A8++0x03 line.long 0x00 "GICD_IPRIORITYR42,Interrupt Priority Register 42" rgroup.long 0x4AC++0x03 line.long 0x00 "GICD_IPRIORITYR43,Interrupt Priority Register 43" rgroup.long 0x4B0++0x03 line.long 0x00 "GICD_IPRIORITYR44,Interrupt Priority Register 44" rgroup.long 0x4B4++0x03 line.long 0x00 "GICD_IPRIORITYR45,Interrupt Priority Register 45" rgroup.long 0x4B8++0x03 line.long 0x00 "GICD_IPRIORITYR46,Interrupt Priority Register 46" rgroup.long 0x4BC++0x03 line.long 0x00 "GICD_IPRIORITYR47,Interrupt Priority Register 47" endif if (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x06) group.long 0x4C0++0x03 line.long 0x00 "GICD_IPRIORITYR48,Interrupt Priority Register 48" hexmask.long.byte 0x00 24.--31. 1. " INTID195 ,Interrupt ID195 Priority/Priority Byte Offset 195 " hexmask.long.byte 0x00 16.--23. 1. " INTID194 ,Interrupt ID194 Priority/Priority Byte Offset 194 " hexmask.long.byte 0x00 8.--15. 1. " INTID193 ,Interrupt ID193 Priority/Priority Byte Offset 193 " hexmask.long.byte 0x00 0.--7. 1. " INTID192 ,Interrupt ID192 Priority/Priority Byte Offset 192 " group.long 0x4C4++0x03 line.long 0x00 "GICD_IPRIORITYR49,Interrupt Priority Register 49" hexmask.long.byte 0x00 24.--31. 1. " INTID199 ,Interrupt ID199 Priority/Priority Byte Offset 199 " hexmask.long.byte 0x00 16.--23. 1. " INTID198 ,Interrupt ID198 Priority/Priority Byte Offset 198 " hexmask.long.byte 0x00 8.--15. 1. " INTID197 ,Interrupt ID197 Priority/Priority Byte Offset 197 " hexmask.long.byte 0x00 0.--7. 1. " INTID196 ,Interrupt ID196 Priority/Priority Byte Offset 196 " group.long 0x4C8++0x03 line.long 0x00 "GICD_IPRIORITYR50,Interrupt Priority Register 50" hexmask.long.byte 0x00 24.--31. 1. " INTID203 ,Interrupt ID203 Priority/Priority Byte Offset 203 " hexmask.long.byte 0x00 16.--23. 1. " INTID202 ,Interrupt ID202 Priority/Priority Byte Offset 202 " hexmask.long.byte 0x00 8.--15. 1. " INTID201 ,Interrupt ID201 Priority/Priority Byte Offset 201 " hexmask.long.byte 0x00 0.--7. 1. " INTID200 ,Interrupt ID200 Priority/Priority Byte Offset 200 " group.long 0x4CC++0x03 line.long 0x00 "GICD_IPRIORITYR51,Interrupt Priority Register 51" hexmask.long.byte 0x00 24.--31. 1. " INTID207 ,Interrupt ID207 Priority/Priority Byte Offset 207 " hexmask.long.byte 0x00 16.--23. 1. " INTID206 ,Interrupt ID206 Priority/Priority Byte Offset 206 " hexmask.long.byte 0x00 8.--15. 1. " INTID205 ,Interrupt ID205 Priority/Priority Byte Offset 205 " hexmask.long.byte 0x00 0.--7. 1. " INTID204 ,Interrupt ID204 Priority/Priority Byte Offset 204 " group.long 0x4D0++0x03 line.long 0x00 "GICD_IPRIORITYR52,Interrupt Priority Register 52" hexmask.long.byte 0x00 24.--31. 1. " INTID211 ,Interrupt ID211 Priority/Priority Byte Offset 211 " hexmask.long.byte 0x00 16.--23. 1. " INTID210 ,Interrupt ID210 Priority/Priority Byte Offset 210 " hexmask.long.byte 0x00 8.--15. 1. " INTID209 ,Interrupt ID209 Priority/Priority Byte Offset 209 " hexmask.long.byte 0x00 0.--7. 1. " INTID208 ,Interrupt ID208 Priority/Priority Byte Offset 208 " group.long 0x4D4++0x03 line.long 0x00 "GICD_IPRIORITYR53,Interrupt Priority Register 53" hexmask.long.byte 0x00 24.--31. 1. " INTID215 ,Interrupt ID215 Priority/Priority Byte Offset 215 " hexmask.long.byte 0x00 16.--23. 1. " INTID214 ,Interrupt ID214 Priority/Priority Byte Offset 214 " hexmask.long.byte 0x00 8.--15. 1. " INTID213 ,Interrupt ID213 Priority/Priority Byte Offset 213 " hexmask.long.byte 0x00 0.--7. 1. " INTID212 ,Interrupt ID212 Priority/Priority Byte Offset 212 " group.long 0x4D8++0x03 line.long 0x00 "GICD_IPRIORITYR54,Interrupt Priority Register 54" hexmask.long.byte 0x00 24.--31. 1. " INTID219 ,Interrupt ID219 Priority/Priority Byte Offset 219 " hexmask.long.byte 0x00 16.--23. 1. " INTID218 ,Interrupt ID218 Priority/Priority Byte Offset 218 " hexmask.long.byte 0x00 8.--15. 1. " INTID217 ,Interrupt ID217 Priority/Priority Byte Offset 217 " hexmask.long.byte 0x00 0.--7. 1. " INTID216 ,Interrupt ID216 Priority/Priority Byte Offset 216 " group.long 0x4DC++0x03 line.long 0x00 "GICD_IPRIORITYR55,Interrupt Priority Register 55" hexmask.long.byte 0x00 24.--31. 1. " INTID223 ,Interrupt ID223 Priority/Priority Byte Offset 223 " hexmask.long.byte 0x00 16.--23. 1. " INTID222 ,Interrupt ID222 Priority/Priority Byte Offset 222 " hexmask.long.byte 0x00 8.--15. 1. " INTID221 ,Interrupt ID221 Priority/Priority Byte Offset 221 " hexmask.long.byte 0x00 0.--7. 1. " INTID220 ,Interrupt ID220 Priority/Priority Byte Offset 220 " else rgroup.long 0x4C0++0x03 line.long 0x00 "GICD_IPRIORITYR48,Interrupt Priority Register 48" rgroup.long 0x4C4++0x03 line.long 0x00 "GICD_IPRIORITYR49,Interrupt Priority Register 49" rgroup.long 0x4C8++0x03 line.long 0x00 "GICD_IPRIORITYR50,Interrupt Priority Register 50" rgroup.long 0x4CC++0x03 line.long 0x00 "GICD_IPRIORITYR51,Interrupt Priority Register 51" rgroup.long 0x4D0++0x03 line.long 0x00 "GICD_IPRIORITYR52,Interrupt Priority Register 52" rgroup.long 0x4D4++0x03 line.long 0x00 "GICD_IPRIORITYR53,Interrupt Priority Register 53" rgroup.long 0x4D8++0x03 line.long 0x00 "GICD_IPRIORITYR54,Interrupt Priority Register 54" rgroup.long 0x4DC++0x03 line.long 0x00 "GICD_IPRIORITYR55,Interrupt Priority Register 55" endif if (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x07) group.long 0x4E0++0x03 line.long 0x00 "GICD_IPRIORITYR56,Interrupt Priority Register 56" hexmask.long.byte 0x00 24.--31. 1. " INTID227 ,Interrupt ID227 Priority/Priority Byte Offset 227 " hexmask.long.byte 0x00 16.--23. 1. " INTID226 ,Interrupt ID226 Priority/Priority Byte Offset 226 " hexmask.long.byte 0x00 8.--15. 1. " INTID225 ,Interrupt ID225 Priority/Priority Byte Offset 225 " hexmask.long.byte 0x00 0.--7. 1. " INTID224 ,Interrupt ID224 Priority/Priority Byte Offset 224 " group.long 0x4E4++0x03 line.long 0x00 "GICD_IPRIORITYR57,Interrupt Priority Register 57" hexmask.long.byte 0x00 24.--31. 1. " INTID231 ,Interrupt ID231 Priority/Priority Byte Offset 231 " hexmask.long.byte 0x00 16.--23. 1. " INTID230 ,Interrupt ID230 Priority/Priority Byte Offset 230 " hexmask.long.byte 0x00 8.--15. 1. " INTID229 ,Interrupt ID229 Priority/Priority Byte Offset 229 " hexmask.long.byte 0x00 0.--7. 1. " INTID228 ,Interrupt ID228 Priority/Priority Byte Offset 228 " group.long 0x4E8++0x03 line.long 0x00 "GICD_IPRIORITYR58,Interrupt Priority Register 58" hexmask.long.byte 0x00 24.--31. 1. " INTID235 ,Interrupt ID235 Priority/Priority Byte Offset 235 " hexmask.long.byte 0x00 16.--23. 1. " INTID234 ,Interrupt ID234 Priority/Priority Byte Offset 234 " hexmask.long.byte 0x00 8.--15. 1. " INTID233 ,Interrupt ID233 Priority/Priority Byte Offset 233 " hexmask.long.byte 0x00 0.--7. 1. " INTID232 ,Interrupt ID232 Priority/Priority Byte Offset 232 " group.long 0x4EC++0x03 line.long 0x00 "GICD_IPRIORITYR59,Interrupt Priority Register 59" hexmask.long.byte 0x00 24.--31. 1. " INTID239 ,Interrupt ID239 Priority/Priority Byte Offset 239 " hexmask.long.byte 0x00 16.--23. 1. " INTID238 ,Interrupt ID238 Priority/Priority Byte Offset 238 " hexmask.long.byte 0x00 8.--15. 1. " INTID237 ,Interrupt ID237 Priority/Priority Byte Offset 237 " hexmask.long.byte 0x00 0.--7. 1. " INTID236 ,Interrupt ID236 Priority/Priority Byte Offset 236 " group.long 0x4F0++0x03 line.long 0x00 "GICD_IPRIORITYR60,Interrupt Priority Register 60" hexmask.long.byte 0x00 24.--31. 1. " INTID243 ,Interrupt ID243 Priority/Priority Byte Offset 243 " hexmask.long.byte 0x00 16.--23. 1. " INTID242 ,Interrupt ID242 Priority/Priority Byte Offset 242 " hexmask.long.byte 0x00 8.--15. 1. " INTID241 ,Interrupt ID241 Priority/Priority Byte Offset 241 " hexmask.long.byte 0x00 0.--7. 1. " INTID240 ,Interrupt ID240 Priority/Priority Byte Offset 240 " group.long 0x4F4++0x03 line.long 0x00 "GICD_IPRIORITYR61,Interrupt Priority Register 61" hexmask.long.byte 0x00 24.--31. 1. " INTID247 ,Interrupt ID247 Priority/Priority Byte Offset 247 " hexmask.long.byte 0x00 16.--23. 1. " INTID246 ,Interrupt ID246 Priority/Priority Byte Offset 246 " hexmask.long.byte 0x00 8.--15. 1. " INTID245 ,Interrupt ID245 Priority/Priority Byte Offset 245 " hexmask.long.byte 0x00 0.--7. 1. " INTID244 ,Interrupt ID244 Priority/Priority Byte Offset 244 " group.long 0x4F8++0x03 line.long 0x00 "GICD_IPRIORITYR62,Interrupt Priority Register 62" hexmask.long.byte 0x00 24.--31. 1. " INTID251 ,Interrupt ID251 Priority/Priority Byte Offset 251 " hexmask.long.byte 0x00 16.--23. 1. " INTID250 ,Interrupt ID250 Priority/Priority Byte Offset 250 " hexmask.long.byte 0x00 8.--15. 1. " INTID249 ,Interrupt ID249 Priority/Priority Byte Offset 249 " hexmask.long.byte 0x00 0.--7. 1. " INTID248 ,Interrupt ID248 Priority/Priority Byte Offset 248 " group.long 0x4FC++0x03 line.long 0x00 "GICD_IPRIORITYR63,Interrupt Priority Register 63" hexmask.long.byte 0x00 24.--31. 1. " INTID255 ,Interrupt ID255 Priority/Priority Byte Offset 255 " hexmask.long.byte 0x00 16.--23. 1. " INTID254 ,Interrupt ID254 Priority/Priority Byte Offset 254 " hexmask.long.byte 0x00 8.--15. 1. " INTID253 ,Interrupt ID253 Priority/Priority Byte Offset 253 " hexmask.long.byte 0x00 0.--7. 1. " INTID252 ,Interrupt ID252 Priority/Priority Byte Offset 252 " else rgroup.long 0x4E0++0x03 line.long 0x00 "GICD_IPRIORITYR56,Interrupt Priority Register 56" rgroup.long 0x4E4++0x03 line.long 0x00 "GICD_IPRIORITYR57,Interrupt Priority Register 57" rgroup.long 0x4E8++0x03 line.long 0x00 "GICD_IPRIORITYR58,Interrupt Priority Register 58" rgroup.long 0x4EC++0x03 line.long 0x00 "GICD_IPRIORITYR59,Interrupt Priority Register 59" rgroup.long 0x4F0++0x03 line.long 0x00 "GICD_IPRIORITYR60,Interrupt Priority Register 60" rgroup.long 0x4F4++0x03 line.long 0x00 "GICD_IPRIORITYR61,Interrupt Priority Register 61" rgroup.long 0x4F8++0x03 line.long 0x00 "GICD_IPRIORITYR62,Interrupt Priority Register 62" rgroup.long 0x4FC++0x03 line.long 0x00 "GICD_IPRIORITYR63,Interrupt Priority Register 63" endif if (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x08) group.long 0x500++0x03 line.long 0x00 "GICD_IPRIORITYR64,Interrupt Priority Register 64" hexmask.long.byte 0x00 24.--31. 1. " INTID259 ,Interrupt ID259 Priority/Priority Byte Offset 259 " hexmask.long.byte 0x00 16.--23. 1. " INTID258 ,Interrupt ID258 Priority/Priority Byte Offset 258 " hexmask.long.byte 0x00 8.--15. 1. " INTID257 ,Interrupt ID257 Priority/Priority Byte Offset 257 " hexmask.long.byte 0x00 0.--7. 1. " INTID256 ,Interrupt ID256 Priority/Priority Byte Offset 256 " group.long 0x504++0x03 line.long 0x00 "GICD_IPRIORITYR65,Interrupt Priority Register 65" hexmask.long.byte 0x00 24.--31. 1. " INTID263 ,Interrupt ID263 Priority/Priority Byte Offset 263 " hexmask.long.byte 0x00 16.--23. 1. " INTID262 ,Interrupt ID262 Priority/Priority Byte Offset 262 " hexmask.long.byte 0x00 8.--15. 1. " INTID261 ,Interrupt ID261 Priority/Priority Byte Offset 261 " hexmask.long.byte 0x00 0.--7. 1. " INTID260 ,Interrupt ID260 Priority/Priority Byte Offset 260 " group.long 0x508++0x03 line.long 0x00 "GICD_IPRIORITYR66,Interrupt Priority Register 66" hexmask.long.byte 0x00 24.--31. 1. " INTID267 ,Interrupt ID267 Priority/Priority Byte Offset 267 " hexmask.long.byte 0x00 16.--23. 1. " INTID266 ,Interrupt ID266 Priority/Priority Byte Offset 266 " hexmask.long.byte 0x00 8.--15. 1. " INTID265 ,Interrupt ID265 Priority/Priority Byte Offset 265 " hexmask.long.byte 0x00 0.--7. 1. " INTID264 ,Interrupt ID264 Priority/Priority Byte Offset 264 " group.long 0x50C++0x03 line.long 0x00 "GICD_IPRIORITYR67,Interrupt Priority Register 67" hexmask.long.byte 0x00 24.--31. 1. " INTID271 ,Interrupt ID271 Priority/Priority Byte Offset 271 " hexmask.long.byte 0x00 16.--23. 1. " INTID270 ,Interrupt ID270 Priority/Priority Byte Offset 270 " hexmask.long.byte 0x00 8.--15. 1. " INTID269 ,Interrupt ID269 Priority/Priority Byte Offset 269 " hexmask.long.byte 0x00 0.--7. 1. " INTID268 ,Interrupt ID268 Priority/Priority Byte Offset 268 " group.long 0x510++0x03 line.long 0x00 "GICD_IPRIORITYR68,Interrupt Priority Register 68" hexmask.long.byte 0x00 24.--31. 1. " INTID275 ,Interrupt ID275 Priority/Priority Byte Offset 275 " hexmask.long.byte 0x00 16.--23. 1. " INTID274 ,Interrupt ID274 Priority/Priority Byte Offset 274 " hexmask.long.byte 0x00 8.--15. 1. " INTID273 ,Interrupt ID273 Priority/Priority Byte Offset 273 " hexmask.long.byte 0x00 0.--7. 1. " INTID272 ,Interrupt ID272 Priority/Priority Byte Offset 272 " group.long 0x514++0x03 line.long 0x00 "GICD_IPRIORITYR69,Interrupt Priority Register 69" hexmask.long.byte 0x00 24.--31. 1. " INTID279 ,Interrupt ID279 Priority/Priority Byte Offset 279 " hexmask.long.byte 0x00 16.--23. 1. " INTID278 ,Interrupt ID278 Priority/Priority Byte Offset 278 " hexmask.long.byte 0x00 8.--15. 1. " INTID277 ,Interrupt ID277 Priority/Priority Byte Offset 277 " hexmask.long.byte 0x00 0.--7. 1. " INTID276 ,Interrupt ID276 Priority/Priority Byte Offset 276 " group.long 0x518++0x03 line.long 0x00 "GICD_IPRIORITYR70,Interrupt Priority Register 70" hexmask.long.byte 0x00 24.--31. 1. " INTID283 ,Interrupt ID283 Priority/Priority Byte Offset 283 " hexmask.long.byte 0x00 16.--23. 1. " INTID282 ,Interrupt ID282 Priority/Priority Byte Offset 282 " hexmask.long.byte 0x00 8.--15. 1. " INTID281 ,Interrupt ID281 Priority/Priority Byte Offset 281 " hexmask.long.byte 0x00 0.--7. 1. " INTID280 ,Interrupt ID280 Priority/Priority Byte Offset 280 " group.long 0x51C++0x03 line.long 0x00 "GICD_IPRIORITYR71,Interrupt Priority Register 71" hexmask.long.byte 0x00 24.--31. 1. " INTID287 ,Interrupt ID287 Priority/Priority Byte Offset 287 " hexmask.long.byte 0x00 16.--23. 1. " INTID286 ,Interrupt ID286 Priority/Priority Byte Offset 286 " hexmask.long.byte 0x00 8.--15. 1. " INTID285 ,Interrupt ID285 Priority/Priority Byte Offset 285 " hexmask.long.byte 0x00 0.--7. 1. " INTID284 ,Interrupt ID284 Priority/Priority Byte Offset 284 " else rgroup.long 0x500++0x03 line.long 0x00 "GICD_IPRIORITYR64,Interrupt Priority Register 64" rgroup.long 0x504++0x03 line.long 0x00 "GICD_IPRIORITYR65,Interrupt Priority Register 65" rgroup.long 0x508++0x03 line.long 0x00 "GICD_IPRIORITYR66,Interrupt Priority Register 66" rgroup.long 0x50C++0x03 line.long 0x00 "GICD_IPRIORITYR67,Interrupt Priority Register 67" rgroup.long 0x510++0x03 line.long 0x00 "GICD_IPRIORITYR68,Interrupt Priority Register 68" rgroup.long 0x514++0x03 line.long 0x00 "GICD_IPRIORITYR69,Interrupt Priority Register 69" rgroup.long 0x518++0x03 line.long 0x00 "GICD_IPRIORITYR70,Interrupt Priority Register 70" rgroup.long 0x51C++0x03 line.long 0x00 "GICD_IPRIORITYR71,Interrupt Priority Register 71" endif if (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x09) group.long 0x520++0x03 line.long 0x00 "GICD_IPRIORITYR72,Interrupt Priority Register 72" hexmask.long.byte 0x00 24.--31. 1. " INTID291 ,Interrupt ID291 Priority/Priority Byte Offset 291 " hexmask.long.byte 0x00 16.--23. 1. " INTID290 ,Interrupt ID290 Priority/Priority Byte Offset 290 " hexmask.long.byte 0x00 8.--15. 1. " INTID289 ,Interrupt ID289 Priority/Priority Byte Offset 289 " hexmask.long.byte 0x00 0.--7. 1. " INTID288 ,Interrupt ID288 Priority/Priority Byte Offset 288 " group.long 0x524++0x03 line.long 0x00 "GICD_IPRIORITYR73,Interrupt Priority Register 73" hexmask.long.byte 0x00 24.--31. 1. " INTID295 ,Interrupt ID295 Priority/Priority Byte Offset 295 " hexmask.long.byte 0x00 16.--23. 1. " INTID294 ,Interrupt ID294 Priority/Priority Byte Offset 294 " hexmask.long.byte 0x00 8.--15. 1. " INTID293 ,Interrupt ID293 Priority/Priority Byte Offset 293 " hexmask.long.byte 0x00 0.--7. 1. " INTID292 ,Interrupt ID292 Priority/Priority Byte Offset 292 " group.long 0x528++0x03 line.long 0x00 "GICD_IPRIORITYR74,Interrupt Priority Register 74" hexmask.long.byte 0x00 24.--31. 1. " INTID299 ,Interrupt ID299 Priority/Priority Byte Offset 299 " hexmask.long.byte 0x00 16.--23. 1. " INTID298 ,Interrupt ID298 Priority/Priority Byte Offset 298 " hexmask.long.byte 0x00 8.--15. 1. " INTID297 ,Interrupt ID297 Priority/Priority Byte Offset 297 " hexmask.long.byte 0x00 0.--7. 1. " INTID296 ,Interrupt ID296 Priority/Priority Byte Offset 296 " group.long 0x52C++0x03 line.long 0x00 "GICD_IPRIORITYR75,Interrupt Priority Register 75" hexmask.long.byte 0x00 24.--31. 1. " INTID303 ,Interrupt ID303 Priority/Priority Byte Offset 303 " hexmask.long.byte 0x00 16.--23. 1. " INTID302 ,Interrupt ID302 Priority/Priority Byte Offset 302 " hexmask.long.byte 0x00 8.--15. 1. " INTID301 ,Interrupt ID301 Priority/Priority Byte Offset 301 " hexmask.long.byte 0x00 0.--7. 1. " INTID300 ,Interrupt ID300 Priority/Priority Byte Offset 300 " group.long 0x530++0x03 line.long 0x00 "GICD_IPRIORITYR76,Interrupt Priority Register 76" hexmask.long.byte 0x00 24.--31. 1. " INTID307 ,Interrupt ID307 Priority/Priority Byte Offset 307 " hexmask.long.byte 0x00 16.--23. 1. " INTID306 ,Interrupt ID306 Priority/Priority Byte Offset 306 " hexmask.long.byte 0x00 8.--15. 1. " INTID305 ,Interrupt ID305 Priority/Priority Byte Offset 305 " hexmask.long.byte 0x00 0.--7. 1. " INTID304 ,Interrupt ID304 Priority/Priority Byte Offset 304 " group.long 0x534++0x03 line.long 0x00 "GICD_IPRIORITYR77,Interrupt Priority Register 77" hexmask.long.byte 0x00 24.--31. 1. " INTID311 ,Interrupt ID311 Priority/Priority Byte Offset 311 " hexmask.long.byte 0x00 16.--23. 1. " INTID310 ,Interrupt ID310 Priority/Priority Byte Offset 310 " hexmask.long.byte 0x00 8.--15. 1. " INTID309 ,Interrupt ID309 Priority/Priority Byte Offset 309 " hexmask.long.byte 0x00 0.--7. 1. " INTID308 ,Interrupt ID308 Priority/Priority Byte Offset 308 " group.long 0x538++0x03 line.long 0x00 "GICD_IPRIORITYR78,Interrupt Priority Register 78" hexmask.long.byte 0x00 24.--31. 1. " INTID315 ,Interrupt ID315 Priority/Priority Byte Offset 315 " hexmask.long.byte 0x00 16.--23. 1. " INTID314 ,Interrupt ID314 Priority/Priority Byte Offset 314 " hexmask.long.byte 0x00 8.--15. 1. " INTID313 ,Interrupt ID313 Priority/Priority Byte Offset 313 " hexmask.long.byte 0x00 0.--7. 1. " INTID312 ,Interrupt ID312 Priority/Priority Byte Offset 312 " group.long 0x53C++0x03 line.long 0x00 "GICD_IPRIORITYR79,Interrupt Priority Register 79" hexmask.long.byte 0x00 24.--31. 1. " INTID319 ,Interrupt ID319 Priority/Priority Byte Offset 319 " hexmask.long.byte 0x00 16.--23. 1. " INTID318 ,Interrupt ID318 Priority/Priority Byte Offset 318 " hexmask.long.byte 0x00 8.--15. 1. " INTID317 ,Interrupt ID317 Priority/Priority Byte Offset 317 " hexmask.long.byte 0x00 0.--7. 1. " INTID316 ,Interrupt ID316 Priority/Priority Byte Offset 316 " else rgroup.long 0x520++0x03 line.long 0x00 "GICD_IPRIORITYR72,Interrupt Priority Register 72" rgroup.long 0x524++0x03 line.long 0x00 "GICD_IPRIORITYR73,Interrupt Priority Register 73" rgroup.long 0x528++0x03 line.long 0x00 "GICD_IPRIORITYR74,Interrupt Priority Register 74" rgroup.long 0x52C++0x03 line.long 0x00 "GICD_IPRIORITYR75,Interrupt Priority Register 75" rgroup.long 0x530++0x03 line.long 0x00 "GICD_IPRIORITYR76,Interrupt Priority Register 76" rgroup.long 0x534++0x03 line.long 0x00 "GICD_IPRIORITYR77,Interrupt Priority Register 77" rgroup.long 0x538++0x03 line.long 0x00 "GICD_IPRIORITYR78,Interrupt Priority Register 78" rgroup.long 0x53C++0x03 line.long 0x00 "GICD_IPRIORITYR79,Interrupt Priority Register 79" endif if (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x0A) group.long 0x540++0x03 line.long 0x00 "GICD_IPRIORITYR80,Interrupt Priority Register 80" hexmask.long.byte 0x00 24.--31. 1. " INTID323 ,Interrupt ID323 Priority/Priority Byte Offset 323 " hexmask.long.byte 0x00 16.--23. 1. " INTID322 ,Interrupt ID322 Priority/Priority Byte Offset 322 " hexmask.long.byte 0x00 8.--15. 1. " INTID321 ,Interrupt ID321 Priority/Priority Byte Offset 321 " hexmask.long.byte 0x00 0.--7. 1. " INTID320 ,Interrupt ID320 Priority/Priority Byte Offset 320 " group.long 0x544++0x03 line.long 0x00 "GICD_IPRIORITYR81,Interrupt Priority Register 81" hexmask.long.byte 0x00 24.--31. 1. " INTID327 ,Interrupt ID327 Priority/Priority Byte Offset 327 " hexmask.long.byte 0x00 16.--23. 1. " INTID326 ,Interrupt ID326 Priority/Priority Byte Offset 326 " hexmask.long.byte 0x00 8.--15. 1. " INTID325 ,Interrupt ID325 Priority/Priority Byte Offset 325 " hexmask.long.byte 0x00 0.--7. 1. " INTID324 ,Interrupt ID324 Priority/Priority Byte Offset 324 " group.long 0x548++0x03 line.long 0x00 "GICD_IPRIORITYR82,Interrupt Priority Register 82" hexmask.long.byte 0x00 24.--31. 1. " INTID331 ,Interrupt ID331 Priority/Priority Byte Offset 331 " hexmask.long.byte 0x00 16.--23. 1. " INTID330 ,Interrupt ID330 Priority/Priority Byte Offset 330 " hexmask.long.byte 0x00 8.--15. 1. " INTID329 ,Interrupt ID329 Priority/Priority Byte Offset 329 " hexmask.long.byte 0x00 0.--7. 1. " INTID328 ,Interrupt ID328 Priority/Priority Byte Offset 328 " group.long 0x54C++0x03 line.long 0x00 "GICD_IPRIORITYR83,Interrupt Priority Register 83" hexmask.long.byte 0x00 24.--31. 1. " INTID335 ,Interrupt ID335 Priority/Priority Byte Offset 335 " hexmask.long.byte 0x00 16.--23. 1. " INTID334 ,Interrupt ID334 Priority/Priority Byte Offset 334 " hexmask.long.byte 0x00 8.--15. 1. " INTID333 ,Interrupt ID333 Priority/Priority Byte Offset 333 " hexmask.long.byte 0x00 0.--7. 1. " INTID332 ,Interrupt ID332 Priority/Priority Byte Offset 332 " group.long 0x550++0x03 line.long 0x00 "GICD_IPRIORITYR84,Interrupt Priority Register 84" hexmask.long.byte 0x00 24.--31. 1. " INTID339 ,Interrupt ID339 Priority/Priority Byte Offset 339 " hexmask.long.byte 0x00 16.--23. 1. " INTID338 ,Interrupt ID338 Priority/Priority Byte Offset 338 " hexmask.long.byte 0x00 8.--15. 1. " INTID337 ,Interrupt ID337 Priority/Priority Byte Offset 337 " hexmask.long.byte 0x00 0.--7. 1. " INTID336 ,Interrupt ID336 Priority/Priority Byte Offset 336 " group.long 0x554++0x03 line.long 0x00 "GICD_IPRIORITYR85,Interrupt Priority Register 85" hexmask.long.byte 0x00 24.--31. 1. " INTID343 ,Interrupt ID343 Priority/Priority Byte Offset 343 " hexmask.long.byte 0x00 16.--23. 1. " INTID342 ,Interrupt ID342 Priority/Priority Byte Offset 342 " hexmask.long.byte 0x00 8.--15. 1. " INTID341 ,Interrupt ID341 Priority/Priority Byte Offset 341 " hexmask.long.byte 0x00 0.--7. 1. " INTID340 ,Interrupt ID340 Priority/Priority Byte Offset 340 " group.long 0x558++0x03 line.long 0x00 "GICD_IPRIORITYR86,Interrupt Priority Register 86" hexmask.long.byte 0x00 24.--31. 1. " INTID347 ,Interrupt ID347 Priority/Priority Byte Offset 347 " hexmask.long.byte 0x00 16.--23. 1. " INTID346 ,Interrupt ID346 Priority/Priority Byte Offset 346 " hexmask.long.byte 0x00 8.--15. 1. " INTID345 ,Interrupt ID345 Priority/Priority Byte Offset 345 " hexmask.long.byte 0x00 0.--7. 1. " INTID344 ,Interrupt ID344 Priority/Priority Byte Offset 344 " group.long 0x55C++0x03 line.long 0x00 "GICD_IPRIORITYR87,Interrupt Priority Register 87" hexmask.long.byte 0x00 24.--31. 1. " INTID351 ,Interrupt ID351 Priority/Priority Byte Offset 351 " hexmask.long.byte 0x00 16.--23. 1. " INTID350 ,Interrupt ID350 Priority/Priority Byte Offset 350 " hexmask.long.byte 0x00 8.--15. 1. " INTID349 ,Interrupt ID349 Priority/Priority Byte Offset 349 " hexmask.long.byte 0x00 0.--7. 1. " INTID348 ,Interrupt ID348 Priority/Priority Byte Offset 348 " else rgroup.long 0x540++0x03 line.long 0x00 "GICD_IPRIORITYR80,Interrupt Priority Register 80" rgroup.long 0x544++0x03 line.long 0x00 "GICD_IPRIORITYR81,Interrupt Priority Register 81" rgroup.long 0x548++0x03 line.long 0x00 "GICD_IPRIORITYR82,Interrupt Priority Register 82" rgroup.long 0x54C++0x03 line.long 0x00 "GICD_IPRIORITYR83,Interrupt Priority Register 83" rgroup.long 0x550++0x03 line.long 0x00 "GICD_IPRIORITYR84,Interrupt Priority Register 84" rgroup.long 0x554++0x03 line.long 0x00 "GICD_IPRIORITYR85,Interrupt Priority Register 85" rgroup.long 0x558++0x03 line.long 0x00 "GICD_IPRIORITYR86,Interrupt Priority Register 86" rgroup.long 0x55C++0x03 line.long 0x00 "GICD_IPRIORITYR87,Interrupt Priority Register 87" endif if (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x0B) group.long 0x560++0x03 line.long 0x00 "GICD_IPRIORITYR88,Interrupt Priority Register 88" hexmask.long.byte 0x00 24.--31. 1. " INTID355 ,Interrupt ID355 Priority/Priority Byte Offset 355 " hexmask.long.byte 0x00 16.--23. 1. " INTID354 ,Interrupt ID354 Priority/Priority Byte Offset 354 " hexmask.long.byte 0x00 8.--15. 1. " INTID353 ,Interrupt ID353 Priority/Priority Byte Offset 353 " hexmask.long.byte 0x00 0.--7. 1. " INTID352 ,Interrupt ID352 Priority/Priority Byte Offset 352 " group.long 0x564++0x03 line.long 0x00 "GICD_IPRIORITYR89,Interrupt Priority Register 89" hexmask.long.byte 0x00 24.--31. 1. " INTID359 ,Interrupt ID359 Priority/Priority Byte Offset 359 " hexmask.long.byte 0x00 16.--23. 1. " INTID358 ,Interrupt ID358 Priority/Priority Byte Offset 358 " hexmask.long.byte 0x00 8.--15. 1. " INTID357 ,Interrupt ID357 Priority/Priority Byte Offset 357 " hexmask.long.byte 0x00 0.--7. 1. " INTID356 ,Interrupt ID356 Priority/Priority Byte Offset 356 " group.long 0x568++0x03 line.long 0x00 "GICD_IPRIORITYR90,Interrupt Priority Register 90" hexmask.long.byte 0x00 24.--31. 1. " INTID363 ,Interrupt ID363 Priority/Priority Byte Offset 363 " hexmask.long.byte 0x00 16.--23. 1. " INTID362 ,Interrupt ID362 Priority/Priority Byte Offset 362 " hexmask.long.byte 0x00 8.--15. 1. " INTID361 ,Interrupt ID361 Priority/Priority Byte Offset 361 " hexmask.long.byte 0x00 0.--7. 1. " INTID360 ,Interrupt ID360 Priority/Priority Byte Offset 360 " group.long 0x56C++0x03 line.long 0x00 "GICD_IPRIORITYR91,Interrupt Priority Register 91" hexmask.long.byte 0x00 24.--31. 1. " INTID367 ,Interrupt ID367 Priority/Priority Byte Offset 367 " hexmask.long.byte 0x00 16.--23. 1. " INTID366 ,Interrupt ID366 Priority/Priority Byte Offset 366 " hexmask.long.byte 0x00 8.--15. 1. " INTID365 ,Interrupt ID365 Priority/Priority Byte Offset 365 " hexmask.long.byte 0x00 0.--7. 1. " INTID364 ,Interrupt ID364 Priority/Priority Byte Offset 364 " group.long 0x570++0x03 line.long 0x00 "GICD_IPRIORITYR92,Interrupt Priority Register 92" hexmask.long.byte 0x00 24.--31. 1. " INTID371 ,Interrupt ID371 Priority/Priority Byte Offset 371 " hexmask.long.byte 0x00 16.--23. 1. " INTID370 ,Interrupt ID370 Priority/Priority Byte Offset 370 " hexmask.long.byte 0x00 8.--15. 1. " INTID369 ,Interrupt ID369 Priority/Priority Byte Offset 369 " hexmask.long.byte 0x00 0.--7. 1. " INTID368 ,Interrupt ID368 Priority/Priority Byte Offset 368 " group.long 0x574++0x03 line.long 0x00 "GICD_IPRIORITYR93,Interrupt Priority Register 93" hexmask.long.byte 0x00 24.--31. 1. " INTID375 ,Interrupt ID375 Priority/Priority Byte Offset 375 " hexmask.long.byte 0x00 16.--23. 1. " INTID374 ,Interrupt ID374 Priority/Priority Byte Offset 374 " hexmask.long.byte 0x00 8.--15. 1. " INTID373 ,Interrupt ID373 Priority/Priority Byte Offset 373 " hexmask.long.byte 0x00 0.--7. 1. " INTID372 ,Interrupt ID372 Priority/Priority Byte Offset 372 " group.long 0x578++0x03 line.long 0x00 "GICD_IPRIORITYR94,Interrupt Priority Register 94" hexmask.long.byte 0x00 24.--31. 1. " INTID379 ,Interrupt ID379 Priority/Priority Byte Offset 379 " hexmask.long.byte 0x00 16.--23. 1. " INTID378 ,Interrupt ID378 Priority/Priority Byte Offset 378 " hexmask.long.byte 0x00 8.--15. 1. " INTID377 ,Interrupt ID377 Priority/Priority Byte Offset 377 " hexmask.long.byte 0x00 0.--7. 1. " INTID376 ,Interrupt ID376 Priority/Priority Byte Offset 376 " group.long 0x57C++0x03 line.long 0x00 "GICD_IPRIORITYR95,Interrupt Priority Register 95" hexmask.long.byte 0x00 24.--31. 1. " INTID383 ,Interrupt ID383 Priority/Priority Byte Offset 383 " hexmask.long.byte 0x00 16.--23. 1. " INTID382 ,Interrupt ID382 Priority/Priority Byte Offset 382 " hexmask.long.byte 0x00 8.--15. 1. " INTID381 ,Interrupt ID381 Priority/Priority Byte Offset 381 " hexmask.long.byte 0x00 0.--7. 1. " INTID380 ,Interrupt ID380 Priority/Priority Byte Offset 380 " else rgroup.long 0x560++0x03 line.long 0x00 "GICD_IPRIORITYR88,Interrupt Priority Register 88" rgroup.long 0x564++0x03 line.long 0x00 "GICD_IPRIORITYR89,Interrupt Priority Register 89" rgroup.long 0x568++0x03 line.long 0x00 "GICD_IPRIORITYR90,Interrupt Priority Register 90" rgroup.long 0x56C++0x03 line.long 0x00 "GICD_IPRIORITYR91,Interrupt Priority Register 91" rgroup.long 0x570++0x03 line.long 0x00 "GICD_IPRIORITYR92,Interrupt Priority Register 92" rgroup.long 0x574++0x03 line.long 0x00 "GICD_IPRIORITYR93,Interrupt Priority Register 93" rgroup.long 0x578++0x03 line.long 0x00 "GICD_IPRIORITYR94,Interrupt Priority Register 94" rgroup.long 0x57C++0x03 line.long 0x00 "GICD_IPRIORITYR95,Interrupt Priority Register 95" endif if (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x0C) group.long 0x580++0x03 line.long 0x00 "GICD_IPRIORITYR96,Interrupt Priority Register 96" hexmask.long.byte 0x00 24.--31. 1. " INTID387 ,Interrupt ID387 Priority/Priority Byte Offset 387 " hexmask.long.byte 0x00 16.--23. 1. " INTID386 ,Interrupt ID386 Priority/Priority Byte Offset 386 " hexmask.long.byte 0x00 8.--15. 1. " INTID385 ,Interrupt ID385 Priority/Priority Byte Offset 385 " hexmask.long.byte 0x00 0.--7. 1. " INTID384 ,Interrupt ID384 Priority/Priority Byte Offset 384 " group.long 0x584++0x03 line.long 0x00 "GICD_IPRIORITYR97,Interrupt Priority Register 97" hexmask.long.byte 0x00 24.--31. 1. " INTID391 ,Interrupt ID391 Priority/Priority Byte Offset 391 " hexmask.long.byte 0x00 16.--23. 1. " INTID390 ,Interrupt ID390 Priority/Priority Byte Offset 390 " hexmask.long.byte 0x00 8.--15. 1. " INTID389 ,Interrupt ID389 Priority/Priority Byte Offset 389 " hexmask.long.byte 0x00 0.--7. 1. " INTID388 ,Interrupt ID388 Priority/Priority Byte Offset 388 " group.long 0x588++0x03 line.long 0x00 "GICD_IPRIORITYR98,Interrupt Priority Register 98" hexmask.long.byte 0x00 24.--31. 1. " INTID395 ,Interrupt ID395 Priority/Priority Byte Offset 395 " hexmask.long.byte 0x00 16.--23. 1. " INTID394 ,Interrupt ID394 Priority/Priority Byte Offset 394 " hexmask.long.byte 0x00 8.--15. 1. " INTID393 ,Interrupt ID393 Priority/Priority Byte Offset 393 " hexmask.long.byte 0x00 0.--7. 1. " INTID392 ,Interrupt ID392 Priority/Priority Byte Offset 392 " group.long 0x58C++0x03 line.long 0x00 "GICD_IPRIORITYR99,Interrupt Priority Register 99" hexmask.long.byte 0x00 24.--31. 1. " INTID399 ,Interrupt ID399 Priority/Priority Byte Offset 399 " hexmask.long.byte 0x00 16.--23. 1. " INTID398 ,Interrupt ID398 Priority/Priority Byte Offset 398 " hexmask.long.byte 0x00 8.--15. 1. " INTID397 ,Interrupt ID397 Priority/Priority Byte Offset 397 " hexmask.long.byte 0x00 0.--7. 1. " INTID396 ,Interrupt ID396 Priority/Priority Byte Offset 396 " group.long 0x590++0x03 line.long 0x00 "GICD_IPRIORITYR100,Interrupt Priority Register 100" hexmask.long.byte 0x00 24.--31. 1. " INTID403 ,Interrupt ID403 Priority/Priority Byte Offset 403 " hexmask.long.byte 0x00 16.--23. 1. " INTID402 ,Interrupt ID402 Priority/Priority Byte Offset 402 " hexmask.long.byte 0x00 8.--15. 1. " INTID401 ,Interrupt ID401 Priority/Priority Byte Offset 401 " hexmask.long.byte 0x00 0.--7. 1. " INTID400 ,Interrupt ID400 Priority/Priority Byte Offset 400 " group.long 0x594++0x03 line.long 0x00 "GICD_IPRIORITYR101,Interrupt Priority Register 101" hexmask.long.byte 0x00 24.--31. 1. " INTID407 ,Interrupt ID407 Priority/Priority Byte Offset 407 " hexmask.long.byte 0x00 16.--23. 1. " INTID406 ,Interrupt ID406 Priority/Priority Byte Offset 406 " hexmask.long.byte 0x00 8.--15. 1. " INTID405 ,Interrupt ID405 Priority/Priority Byte Offset 405 " hexmask.long.byte 0x00 0.--7. 1. " INTID404 ,Interrupt ID404 Priority/Priority Byte Offset 404 " group.long 0x598++0x03 line.long 0x00 "GICD_IPRIORITYR102,Interrupt Priority Register 102" hexmask.long.byte 0x00 24.--31. 1. " INTID411 ,Interrupt ID411 Priority/Priority Byte Offset 411 " hexmask.long.byte 0x00 16.--23. 1. " INTID410 ,Interrupt ID410 Priority/Priority Byte Offset 410 " hexmask.long.byte 0x00 8.--15. 1. " INTID409 ,Interrupt ID409 Priority/Priority Byte Offset 409 " hexmask.long.byte 0x00 0.--7. 1. " INTID408 ,Interrupt ID408 Priority/Priority Byte Offset 408 " group.long 0x59C++0x03 line.long 0x00 "GICD_IPRIORITYR103,Interrupt Priority Register 103" hexmask.long.byte 0x00 24.--31. 1. " INTID415 ,Interrupt ID415 Priority/Priority Byte Offset 415 " hexmask.long.byte 0x00 16.--23. 1. " INTID414 ,Interrupt ID414 Priority/Priority Byte Offset 414 " hexmask.long.byte 0x00 8.--15. 1. " INTID413 ,Interrupt ID413 Priority/Priority Byte Offset 413 " hexmask.long.byte 0x00 0.--7. 1. " INTID412 ,Interrupt ID412 Priority/Priority Byte Offset 412 " else rgroup.long 0x580++0x03 line.long 0x00 "GICD_IPRIORITYR96,Interrupt Priority Register 96" rgroup.long 0x584++0x03 line.long 0x00 "GICD_IPRIORITYR97,Interrupt Priority Register 97" rgroup.long 0x588++0x03 line.long 0x00 "GICD_IPRIORITYR98,Interrupt Priority Register 98" rgroup.long 0x58C++0x03 line.long 0x00 "GICD_IPRIORITYR99,Interrupt Priority Register 99" rgroup.long 0x590++0x03 line.long 0x00 "GICD_IPRIORITYR100,Interrupt Priority Register 100" rgroup.long 0x594++0x03 line.long 0x00 "GICD_IPRIORITYR101,Interrupt Priority Register 101" rgroup.long 0x598++0x03 line.long 0x00 "GICD_IPRIORITYR102,Interrupt Priority Register 102" rgroup.long 0x59C++0x03 line.long 0x00 "GICD_IPRIORITYR103,Interrupt Priority Register 103" endif if (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x0D) group.long 0x5A0++0x03 line.long 0x00 "GICD_IPRIORITYR104,Interrupt Priority Register 104" hexmask.long.byte 0x00 24.--31. 1. " INTID419 ,Interrupt ID419 Priority/Priority Byte Offset 419 " hexmask.long.byte 0x00 16.--23. 1. " INTID418 ,Interrupt ID418 Priority/Priority Byte Offset 418 " hexmask.long.byte 0x00 8.--15. 1. " INTID417 ,Interrupt ID417 Priority/Priority Byte Offset 417 " hexmask.long.byte 0x00 0.--7. 1. " INTID416 ,Interrupt ID416 Priority/Priority Byte Offset 416 " group.long 0x5A4++0x03 line.long 0x00 "GICD_IPRIORITYR105,Interrupt Priority Register 105" hexmask.long.byte 0x00 24.--31. 1. " INTID423 ,Interrupt ID423 Priority/Priority Byte Offset 423 " hexmask.long.byte 0x00 16.--23. 1. " INTID422 ,Interrupt ID422 Priority/Priority Byte Offset 422 " hexmask.long.byte 0x00 8.--15. 1. " INTID421 ,Interrupt ID421 Priority/Priority Byte Offset 421 " hexmask.long.byte 0x00 0.--7. 1. " INTID420 ,Interrupt ID420 Priority/Priority Byte Offset 420 " group.long 0x5A8++0x03 line.long 0x00 "GICD_IPRIORITYR106,Interrupt Priority Register 106" hexmask.long.byte 0x00 24.--31. 1. " INTID427 ,Interrupt ID427 Priority/Priority Byte Offset 427 " hexmask.long.byte 0x00 16.--23. 1. " INTID426 ,Interrupt ID426 Priority/Priority Byte Offset 426 " hexmask.long.byte 0x00 8.--15. 1. " INTID425 ,Interrupt ID425 Priority/Priority Byte Offset 425 " hexmask.long.byte 0x00 0.--7. 1. " INTID424 ,Interrupt ID424 Priority/Priority Byte Offset 424 " group.long 0x5AC++0x03 line.long 0x00 "GICD_IPRIORITYR107,Interrupt Priority Register 107" hexmask.long.byte 0x00 24.--31. 1. " INTID431 ,Interrupt ID431 Priority/Priority Byte Offset 431 " hexmask.long.byte 0x00 16.--23. 1. " INTID430 ,Interrupt ID430 Priority/Priority Byte Offset 430 " hexmask.long.byte 0x00 8.--15. 1. " INTID429 ,Interrupt ID429 Priority/Priority Byte Offset 429 " hexmask.long.byte 0x00 0.--7. 1. " INTID428 ,Interrupt ID428 Priority/Priority Byte Offset 428 " group.long 0x5B0++0x03 line.long 0x00 "GICD_IPRIORITYR108,Interrupt Priority Register 108" hexmask.long.byte 0x00 24.--31. 1. " INTID435 ,Interrupt ID435 Priority/Priority Byte Offset 435 " hexmask.long.byte 0x00 16.--23. 1. " INTID434 ,Interrupt ID434 Priority/Priority Byte Offset 434 " hexmask.long.byte 0x00 8.--15. 1. " INTID433 ,Interrupt ID433 Priority/Priority Byte Offset 433 " hexmask.long.byte 0x00 0.--7. 1. " INTID432 ,Interrupt ID432 Priority/Priority Byte Offset 432 " group.long 0x5B4++0x03 line.long 0x00 "GICD_IPRIORITYR109,Interrupt Priority Register 109" hexmask.long.byte 0x00 24.--31. 1. " INTID439 ,Interrupt ID439 Priority/Priority Byte Offset 439 " hexmask.long.byte 0x00 16.--23. 1. " INTID438 ,Interrupt ID438 Priority/Priority Byte Offset 438 " hexmask.long.byte 0x00 8.--15. 1. " INTID437 ,Interrupt ID437 Priority/Priority Byte Offset 437 " hexmask.long.byte 0x00 0.--7. 1. " INTID436 ,Interrupt ID436 Priority/Priority Byte Offset 436 " group.long 0x5B8++0x03 line.long 0x00 "GICD_IPRIORITYR110,Interrupt Priority Register 110" hexmask.long.byte 0x00 24.--31. 1. " INTID443 ,Interrupt ID443 Priority/Priority Byte Offset 443 " hexmask.long.byte 0x00 16.--23. 1. " INTID442 ,Interrupt ID442 Priority/Priority Byte Offset 442 " hexmask.long.byte 0x00 8.--15. 1. " INTID441 ,Interrupt ID441 Priority/Priority Byte Offset 441 " hexmask.long.byte 0x00 0.--7. 1. " INTID440 ,Interrupt ID440 Priority/Priority Byte Offset 440 " group.long 0x5BC++0x03 line.long 0x00 "GICD_IPRIORITYR111,Interrupt Priority Register 111" hexmask.long.byte 0x00 24.--31. 1. " INTID447 ,Interrupt ID447 Priority/Priority Byte Offset 447 " hexmask.long.byte 0x00 16.--23. 1. " INTID446 ,Interrupt ID446 Priority/Priority Byte Offset 446 " hexmask.long.byte 0x00 8.--15. 1. " INTID445 ,Interrupt ID445 Priority/Priority Byte Offset 445 " hexmask.long.byte 0x00 0.--7. 1. " INTID444 ,Interrupt ID444 Priority/Priority Byte Offset 444 " else rgroup.long 0x5A0++0x03 line.long 0x00 "GICD_IPRIORITYR104,Interrupt Priority Register 104" rgroup.long 0x5A4++0x03 line.long 0x00 "GICD_IPRIORITYR105,Interrupt Priority Register 105" rgroup.long 0x5A8++0x03 line.long 0x00 "GICD_IPRIORITYR106,Interrupt Priority Register 106" rgroup.long 0x5AC++0x03 line.long 0x00 "GICD_IPRIORITYR107,Interrupt Priority Register 107" rgroup.long 0x5B0++0x03 line.long 0x00 "GICD_IPRIORITYR108,Interrupt Priority Register 108" rgroup.long 0x5B4++0x03 line.long 0x00 "GICD_IPRIORITYR109,Interrupt Priority Register 109" rgroup.long 0x5B8++0x03 line.long 0x00 "GICD_IPRIORITYR110,Interrupt Priority Register 110" rgroup.long 0x5BC++0x03 line.long 0x00 "GICD_IPRIORITYR111,Interrupt Priority Register 111" endif if (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x0E) group.long 0x5C0++0x03 line.long 0x00 "GICD_IPRIORITYR112,Interrupt Priority Register 112" hexmask.long.byte 0x00 24.--31. 1. " INTID451 ,Interrupt ID451 Priority/Priority Byte Offset 451 " hexmask.long.byte 0x00 16.--23. 1. " INTID450 ,Interrupt ID450 Priority/Priority Byte Offset 450 " hexmask.long.byte 0x00 8.--15. 1. " INTID449 ,Interrupt ID449 Priority/Priority Byte Offset 449 " hexmask.long.byte 0x00 0.--7. 1. " INTID448 ,Interrupt ID448 Priority/Priority Byte Offset 448 " group.long 0x5C4++0x03 line.long 0x00 "GICD_IPRIORITYR113,Interrupt Priority Register 113" hexmask.long.byte 0x00 24.--31. 1. " INTID455 ,Interrupt ID455 Priority/Priority Byte Offset 455 " hexmask.long.byte 0x00 16.--23. 1. " INTID454 ,Interrupt ID454 Priority/Priority Byte Offset 454 " hexmask.long.byte 0x00 8.--15. 1. " INTID453 ,Interrupt ID453 Priority/Priority Byte Offset 453 " hexmask.long.byte 0x00 0.--7. 1. " INTID452 ,Interrupt ID452 Priority/Priority Byte Offset 452 " group.long 0x5C8++0x03 line.long 0x00 "GICD_IPRIORITYR114,Interrupt Priority Register 114" hexmask.long.byte 0x00 24.--31. 1. " INTID459 ,Interrupt ID459 Priority/Priority Byte Offset 459 " hexmask.long.byte 0x00 16.--23. 1. " INTID458 ,Interrupt ID458 Priority/Priority Byte Offset 458 " hexmask.long.byte 0x00 8.--15. 1. " INTID457 ,Interrupt ID457 Priority/Priority Byte Offset 457 " hexmask.long.byte 0x00 0.--7. 1. " INTID456 ,Interrupt ID456 Priority/Priority Byte Offset 456 " group.long 0x5CC++0x03 line.long 0x00 "GICD_IPRIORITYR115,Interrupt Priority Register 115" hexmask.long.byte 0x00 24.--31. 1. " INTID463 ,Interrupt ID463 Priority/Priority Byte Offset 463 " hexmask.long.byte 0x00 16.--23. 1. " INTID462 ,Interrupt ID462 Priority/Priority Byte Offset 462 " hexmask.long.byte 0x00 8.--15. 1. " INTID461 ,Interrupt ID461 Priority/Priority Byte Offset 461 " hexmask.long.byte 0x00 0.--7. 1. " INTID460 ,Interrupt ID460 Priority/Priority Byte Offset 460 " group.long 0x5D0++0x03 line.long 0x00 "GICD_IPRIORITYR116,Interrupt Priority Register 116" hexmask.long.byte 0x00 24.--31. 1. " INTID467 ,Interrupt ID467 Priority/Priority Byte Offset 467 " hexmask.long.byte 0x00 16.--23. 1. " INTID466 ,Interrupt ID466 Priority/Priority Byte Offset 466 " hexmask.long.byte 0x00 8.--15. 1. " INTID465 ,Interrupt ID465 Priority/Priority Byte Offset 465 " hexmask.long.byte 0x00 0.--7. 1. " INTID464 ,Interrupt ID464 Priority/Priority Byte Offset 464 " group.long 0x5D4++0x03 line.long 0x00 "GICD_IPRIORITYR117,Interrupt Priority Register 117" hexmask.long.byte 0x00 24.--31. 1. " INTID471 ,Interrupt ID471 Priority/Priority Byte Offset 471 " hexmask.long.byte 0x00 16.--23. 1. " INTID470 ,Interrupt ID470 Priority/Priority Byte Offset 470 " hexmask.long.byte 0x00 8.--15. 1. " INTID469 ,Interrupt ID469 Priority/Priority Byte Offset 469 " hexmask.long.byte 0x00 0.--7. 1. " INTID468 ,Interrupt ID468 Priority/Priority Byte Offset 468 " group.long 0x5D8++0x03 line.long 0x00 "GICD_IPRIORITYR118,Interrupt Priority Register 118" hexmask.long.byte 0x00 24.--31. 1. " INTID475 ,Interrupt ID475 Priority/Priority Byte Offset 475 " hexmask.long.byte 0x00 16.--23. 1. " INTID474 ,Interrupt ID474 Priority/Priority Byte Offset 474 " hexmask.long.byte 0x00 8.--15. 1. " INTID473 ,Interrupt ID473 Priority/Priority Byte Offset 473 " hexmask.long.byte 0x00 0.--7. 1. " INTID472 ,Interrupt ID472 Priority/Priority Byte Offset 472 " group.long 0x5DC++0x03 line.long 0x00 "GICD_IPRIORITYR119,Interrupt Priority Register 119" hexmask.long.byte 0x00 24.--31. 1. " INTID479 ,Interrupt ID479 Priority/Priority Byte Offset 479 " hexmask.long.byte 0x00 16.--23. 1. " INTID478 ,Interrupt ID478 Priority/Priority Byte Offset 478 " hexmask.long.byte 0x00 8.--15. 1. " INTID477 ,Interrupt ID477 Priority/Priority Byte Offset 477 " hexmask.long.byte 0x00 0.--7. 1. " INTID476 ,Interrupt ID476 Priority/Priority Byte Offset 476 " else rgroup.long 0x5C0++0x03 line.long 0x00 "GICD_IPRIORITYR112,Interrupt Priority Register 112" rgroup.long 0x5C4++0x03 line.long 0x00 "GICD_IPRIORITYR113,Interrupt Priority Register 113" rgroup.long 0x5C8++0x03 line.long 0x00 "GICD_IPRIORITYR114,Interrupt Priority Register 114" rgroup.long 0x5CC++0x03 line.long 0x00 "GICD_IPRIORITYR115,Interrupt Priority Register 115" rgroup.long 0x5D0++0x03 line.long 0x00 "GICD_IPRIORITYR116,Interrupt Priority Register 116" rgroup.long 0x5D4++0x03 line.long 0x00 "GICD_IPRIORITYR117,Interrupt Priority Register 117" rgroup.long 0x5D8++0x03 line.long 0x00 "GICD_IPRIORITYR118,Interrupt Priority Register 118" rgroup.long 0x5DC++0x03 line.long 0x00 "GICD_IPRIORITYR119,Interrupt Priority Register 119" endif if (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x0F) group.long 0x5E0++0x03 line.long 0x00 "GICD_IPRIORITYR120,Interrupt Priority Register 120" hexmask.long.byte 0x00 24.--31. 1. " INTID483 ,Interrupt ID483 Priority/Priority Byte Offset 483 " hexmask.long.byte 0x00 16.--23. 1. " INTID482 ,Interrupt ID482 Priority/Priority Byte Offset 482 " hexmask.long.byte 0x00 8.--15. 1. " INTID481 ,Interrupt ID481 Priority/Priority Byte Offset 481 " hexmask.long.byte 0x00 0.--7. 1. " INTID480 ,Interrupt ID480 Priority/Priority Byte Offset 480 " group.long 0x5E4++0x03 line.long 0x00 "GICD_IPRIORITYR121,Interrupt Priority Register 121" hexmask.long.byte 0x00 24.--31. 1. " INTID487 ,Interrupt ID487 Priority/Priority Byte Offset 487 " hexmask.long.byte 0x00 16.--23. 1. " INTID486 ,Interrupt ID486 Priority/Priority Byte Offset 486 " hexmask.long.byte 0x00 8.--15. 1. " INTID485 ,Interrupt ID485 Priority/Priority Byte Offset 485 " hexmask.long.byte 0x00 0.--7. 1. " INTID484 ,Interrupt ID484 Priority/Priority Byte Offset 484 " group.long 0x5E8++0x03 line.long 0x00 "GICD_IPRIORITYR122,Interrupt Priority Register 122" hexmask.long.byte 0x00 24.--31. 1. " INTID491 ,Interrupt ID491 Priority/Priority Byte Offset 491 " hexmask.long.byte 0x00 16.--23. 1. " INTID490 ,Interrupt ID490 Priority/Priority Byte Offset 490 " hexmask.long.byte 0x00 8.--15. 1. " INTID489 ,Interrupt ID489 Priority/Priority Byte Offset 489 " hexmask.long.byte 0x00 0.--7. 1. " INTID488 ,Interrupt ID488 Priority/Priority Byte Offset 488 " group.long 0x5EC++0x03 line.long 0x00 "GICD_IPRIORITYR123,Interrupt Priority Register 123" hexmask.long.byte 0x00 24.--31. 1. " INTID495 ,Interrupt ID495 Priority/Priority Byte Offset 495 " hexmask.long.byte 0x00 16.--23. 1. " INTID494 ,Interrupt ID494 Priority/Priority Byte Offset 494 " hexmask.long.byte 0x00 8.--15. 1. " INTID493 ,Interrupt ID493 Priority/Priority Byte Offset 493 " hexmask.long.byte 0x00 0.--7. 1. " INTID492 ,Interrupt ID492 Priority/Priority Byte Offset 492 " group.long 0x5F0++0x03 line.long 0x00 "GICD_IPRIORITYR124,Interrupt Priority Register 124" hexmask.long.byte 0x00 24.--31. 1. " INTID499 ,Interrupt ID499 Priority/Priority Byte Offset 499 " hexmask.long.byte 0x00 16.--23. 1. " INTID498 ,Interrupt ID498 Priority/Priority Byte Offset 498 " hexmask.long.byte 0x00 8.--15. 1. " INTID497 ,Interrupt ID497 Priority/Priority Byte Offset 497 " hexmask.long.byte 0x00 0.--7. 1. " INTID496 ,Interrupt ID496 Priority/Priority Byte Offset 496 " group.long 0x5F4++0x03 line.long 0x00 "GICD_IPRIORITYR125,Interrupt Priority Register 125" hexmask.long.byte 0x00 24.--31. 1. " INTID503 ,Interrupt ID503 Priority/Priority Byte Offset 503 " hexmask.long.byte 0x00 16.--23. 1. " INTID502 ,Interrupt ID502 Priority/Priority Byte Offset 502 " hexmask.long.byte 0x00 8.--15. 1. " INTID501 ,Interrupt ID501 Priority/Priority Byte Offset 501 " hexmask.long.byte 0x00 0.--7. 1. " INTID500 ,Interrupt ID500 Priority/Priority Byte Offset 500 " group.long 0x5F8++0x03 line.long 0x00 "GICD_IPRIORITYR126,Interrupt Priority Register 126" hexmask.long.byte 0x00 24.--31. 1. " INTID507 ,Interrupt ID507 Priority/Priority Byte Offset 507 " hexmask.long.byte 0x00 16.--23. 1. " INTID506 ,Interrupt ID506 Priority/Priority Byte Offset 506 " hexmask.long.byte 0x00 8.--15. 1. " INTID505 ,Interrupt ID505 Priority/Priority Byte Offset 505 " hexmask.long.byte 0x00 0.--7. 1. " INTID504 ,Interrupt ID504 Priority/Priority Byte Offset 504 " group.long 0x5FC++0x03 line.long 0x00 "GICD_IPRIORITYR127,Interrupt Priority Register 127" hexmask.long.byte 0x00 24.--31. 1. " INTID511 ,Interrupt ID511 Priority/Priority Byte Offset 511 " hexmask.long.byte 0x00 16.--23. 1. " INTID510 ,Interrupt ID510 Priority/Priority Byte Offset 510 " hexmask.long.byte 0x00 8.--15. 1. " INTID509 ,Interrupt ID509 Priority/Priority Byte Offset 509 " hexmask.long.byte 0x00 0.--7. 1. " INTID508 ,Interrupt ID508 Priority/Priority Byte Offset 508 " else rgroup.long 0x5E0++0x03 line.long 0x00 "GICD_IPRIORITYR120,Interrupt Priority Register 120" rgroup.long 0x5E4++0x03 line.long 0x00 "GICD_IPRIORITYR121,Interrupt Priority Register 121" rgroup.long 0x5E8++0x03 line.long 0x00 "GICD_IPRIORITYR122,Interrupt Priority Register 122" rgroup.long 0x5EC++0x03 line.long 0x00 "GICD_IPRIORITYR123,Interrupt Priority Register 123" rgroup.long 0x5F0++0x03 line.long 0x00 "GICD_IPRIORITYR124,Interrupt Priority Register 124" rgroup.long 0x5F4++0x03 line.long 0x00 "GICD_IPRIORITYR125,Interrupt Priority Register 125" rgroup.long 0x5F8++0x03 line.long 0x00 "GICD_IPRIORITYR126,Interrupt Priority Register 126" rgroup.long 0x5FC++0x03 line.long 0x00 "GICD_IPRIORITYR127,Interrupt Priority Register 127" endif if (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x10) group.long 0x600++0x03 line.long 0x00 "GICD_IPRIORITYR128,Interrupt Priority Register 128" hexmask.long.byte 0x00 24.--31. 1. " INTID515 ,Interrupt ID515 Priority/Priority Byte Offset 515 " hexmask.long.byte 0x00 16.--23. 1. " INTID514 ,Interrupt ID514 Priority/Priority Byte Offset 514 " hexmask.long.byte 0x00 8.--15. 1. " INTID513 ,Interrupt ID513 Priority/Priority Byte Offset 513 " hexmask.long.byte 0x00 0.--7. 1. " INTID512 ,Interrupt ID512 Priority/Priority Byte Offset 512 " group.long 0x604++0x03 line.long 0x00 "GICD_IPRIORITYR129,Interrupt Priority Register 129" hexmask.long.byte 0x00 24.--31. 1. " INTID519 ,Interrupt ID519 Priority/Priority Byte Offset 519 " hexmask.long.byte 0x00 16.--23. 1. " INTID518 ,Interrupt ID518 Priority/Priority Byte Offset 518 " hexmask.long.byte 0x00 8.--15. 1. " INTID517 ,Interrupt ID517 Priority/Priority Byte Offset 517 " hexmask.long.byte 0x00 0.--7. 1. " INTID516 ,Interrupt ID516 Priority/Priority Byte Offset 516 " group.long 0x608++0x03 line.long 0x00 "GICD_IPRIORITYR130,Interrupt Priority Register 130" hexmask.long.byte 0x00 24.--31. 1. " INTID523 ,Interrupt ID523 Priority/Priority Byte Offset 523 " hexmask.long.byte 0x00 16.--23. 1. " INTID522 ,Interrupt ID522 Priority/Priority Byte Offset 522 " hexmask.long.byte 0x00 8.--15. 1. " INTID521 ,Interrupt ID521 Priority/Priority Byte Offset 521 " hexmask.long.byte 0x00 0.--7. 1. " INTID520 ,Interrupt ID520 Priority/Priority Byte Offset 520 " group.long 0x60C++0x03 line.long 0x00 "GICD_IPRIORITYR131,Interrupt Priority Register 131" hexmask.long.byte 0x00 24.--31. 1. " INTID527 ,Interrupt ID527 Priority/Priority Byte Offset 527 " hexmask.long.byte 0x00 16.--23. 1. " INTID526 ,Interrupt ID526 Priority/Priority Byte Offset 526 " hexmask.long.byte 0x00 8.--15. 1. " INTID525 ,Interrupt ID525 Priority/Priority Byte Offset 525 " hexmask.long.byte 0x00 0.--7. 1. " INTID524 ,Interrupt ID524 Priority/Priority Byte Offset 524 " group.long 0x610++0x03 line.long 0x00 "GICD_IPRIORITYR132,Interrupt Priority Register 132" hexmask.long.byte 0x00 24.--31. 1. " INTID531 ,Interrupt ID531 Priority/Priority Byte Offset 531 " hexmask.long.byte 0x00 16.--23. 1. " INTID530 ,Interrupt ID530 Priority/Priority Byte Offset 530 " hexmask.long.byte 0x00 8.--15. 1. " INTID529 ,Interrupt ID529 Priority/Priority Byte Offset 529 " hexmask.long.byte 0x00 0.--7. 1. " INTID528 ,Interrupt ID528 Priority/Priority Byte Offset 528 " group.long 0x614++0x03 line.long 0x00 "GICD_IPRIORITYR133,Interrupt Priority Register 133" hexmask.long.byte 0x00 24.--31. 1. " INTID535 ,Interrupt ID535 Priority/Priority Byte Offset 535 " hexmask.long.byte 0x00 16.--23. 1. " INTID534 ,Interrupt ID534 Priority/Priority Byte Offset 534 " hexmask.long.byte 0x00 8.--15. 1. " INTID533 ,Interrupt ID533 Priority/Priority Byte Offset 533 " hexmask.long.byte 0x00 0.--7. 1. " INTID532 ,Interrupt ID532 Priority/Priority Byte Offset 532 " group.long 0x618++0x03 line.long 0x00 "GICD_IPRIORITYR134,Interrupt Priority Register 134" hexmask.long.byte 0x00 24.--31. 1. " INTID539 ,Interrupt ID539 Priority/Priority Byte Offset 539 " hexmask.long.byte 0x00 16.--23. 1. " INTID538 ,Interrupt ID538 Priority/Priority Byte Offset 538 " hexmask.long.byte 0x00 8.--15. 1. " INTID537 ,Interrupt ID537 Priority/Priority Byte Offset 537 " hexmask.long.byte 0x00 0.--7. 1. " INTID536 ,Interrupt ID536 Priority/Priority Byte Offset 536 " group.long 0x61C++0x03 line.long 0x00 "GICD_IPRIORITYR135,Interrupt Priority Register 135" hexmask.long.byte 0x00 24.--31. 1. " INTID543 ,Interrupt ID543 Priority/Priority Byte Offset 543 " hexmask.long.byte 0x00 16.--23. 1. " INTID542 ,Interrupt ID542 Priority/Priority Byte Offset 542 " hexmask.long.byte 0x00 8.--15. 1. " INTID541 ,Interrupt ID541 Priority/Priority Byte Offset 541 " hexmask.long.byte 0x00 0.--7. 1. " INTID540 ,Interrupt ID540 Priority/Priority Byte Offset 540 " else rgroup.long 0x600++0x03 line.long 0x00 "GICD_IPRIORITYR128,Interrupt Priority Register 128" rgroup.long 0x604++0x03 line.long 0x00 "GICD_IPRIORITYR129,Interrupt Priority Register 129" rgroup.long 0x608++0x03 line.long 0x00 "GICD_IPRIORITYR130,Interrupt Priority Register 130" rgroup.long 0x60C++0x03 line.long 0x00 "GICD_IPRIORITYR131,Interrupt Priority Register 131" rgroup.long 0x610++0x03 line.long 0x00 "GICD_IPRIORITYR132,Interrupt Priority Register 132" rgroup.long 0x614++0x03 line.long 0x00 "GICD_IPRIORITYR133,Interrupt Priority Register 133" rgroup.long 0x618++0x03 line.long 0x00 "GICD_IPRIORITYR134,Interrupt Priority Register 134" rgroup.long 0x61C++0x03 line.long 0x00 "GICD_IPRIORITYR135,Interrupt Priority Register 135" endif if (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x11) group.long 0x620++0x03 line.long 0x00 "GICD_IPRIORITYR136,Interrupt Priority Register 136" hexmask.long.byte 0x00 24.--31. 1. " INTID547 ,Interrupt ID547 Priority/Priority Byte Offset 547 " hexmask.long.byte 0x00 16.--23. 1. " INTID546 ,Interrupt ID546 Priority/Priority Byte Offset 546 " hexmask.long.byte 0x00 8.--15. 1. " INTID545 ,Interrupt ID545 Priority/Priority Byte Offset 545 " hexmask.long.byte 0x00 0.--7. 1. " INTID544 ,Interrupt ID544 Priority/Priority Byte Offset 544 " group.long 0x624++0x03 line.long 0x00 "GICD_IPRIORITYR137,Interrupt Priority Register 137" hexmask.long.byte 0x00 24.--31. 1. " INTID551 ,Interrupt ID551 Priority/Priority Byte Offset 551 " hexmask.long.byte 0x00 16.--23. 1. " INTID550 ,Interrupt ID550 Priority/Priority Byte Offset 550 " hexmask.long.byte 0x00 8.--15. 1. " INTID549 ,Interrupt ID549 Priority/Priority Byte Offset 549 " hexmask.long.byte 0x00 0.--7. 1. " INTID548 ,Interrupt ID548 Priority/Priority Byte Offset 548 " group.long 0x628++0x03 line.long 0x00 "GICD_IPRIORITYR138,Interrupt Priority Register 138" hexmask.long.byte 0x00 24.--31. 1. " INTID555 ,Interrupt ID555 Priority/Priority Byte Offset 555 " hexmask.long.byte 0x00 16.--23. 1. " INTID554 ,Interrupt ID554 Priority/Priority Byte Offset 554 " hexmask.long.byte 0x00 8.--15. 1. " INTID553 ,Interrupt ID553 Priority/Priority Byte Offset 553 " hexmask.long.byte 0x00 0.--7. 1. " INTID552 ,Interrupt ID552 Priority/Priority Byte Offset 552 " group.long 0x62C++0x03 line.long 0x00 "GICD_IPRIORITYR139,Interrupt Priority Register 139" hexmask.long.byte 0x00 24.--31. 1. " INTID559 ,Interrupt ID559 Priority/Priority Byte Offset 559 " hexmask.long.byte 0x00 16.--23. 1. " INTID558 ,Interrupt ID558 Priority/Priority Byte Offset 558 " hexmask.long.byte 0x00 8.--15. 1. " INTID557 ,Interrupt ID557 Priority/Priority Byte Offset 557 " hexmask.long.byte 0x00 0.--7. 1. " INTID556 ,Interrupt ID556 Priority/Priority Byte Offset 556 " group.long 0x630++0x03 line.long 0x00 "GICD_IPRIORITYR140,Interrupt Priority Register 140" hexmask.long.byte 0x00 24.--31. 1. " INTID563 ,Interrupt ID563 Priority/Priority Byte Offset 563 " hexmask.long.byte 0x00 16.--23. 1. " INTID562 ,Interrupt ID562 Priority/Priority Byte Offset 562 " hexmask.long.byte 0x00 8.--15. 1. " INTID561 ,Interrupt ID561 Priority/Priority Byte Offset 561 " hexmask.long.byte 0x00 0.--7. 1. " INTID560 ,Interrupt ID560 Priority/Priority Byte Offset 560 " group.long 0x634++0x03 line.long 0x00 "GICD_IPRIORITYR141,Interrupt Priority Register 141" hexmask.long.byte 0x00 24.--31. 1. " INTID567 ,Interrupt ID567 Priority/Priority Byte Offset 567 " hexmask.long.byte 0x00 16.--23. 1. " INTID566 ,Interrupt ID566 Priority/Priority Byte Offset 566 " hexmask.long.byte 0x00 8.--15. 1. " INTID565 ,Interrupt ID565 Priority/Priority Byte Offset 565 " hexmask.long.byte 0x00 0.--7. 1. " INTID564 ,Interrupt ID564 Priority/Priority Byte Offset 564 " group.long 0x638++0x03 line.long 0x00 "GICD_IPRIORITYR142,Interrupt Priority Register 142" hexmask.long.byte 0x00 24.--31. 1. " INTID571 ,Interrupt ID571 Priority/Priority Byte Offset 571 " hexmask.long.byte 0x00 16.--23. 1. " INTID570 ,Interrupt ID570 Priority/Priority Byte Offset 570 " hexmask.long.byte 0x00 8.--15. 1. " INTID569 ,Interrupt ID569 Priority/Priority Byte Offset 569 " hexmask.long.byte 0x00 0.--7. 1. " INTID568 ,Interrupt ID568 Priority/Priority Byte Offset 568 " group.long 0x63C++0x03 line.long 0x00 "GICD_IPRIORITYR143,Interrupt Priority Register 143" hexmask.long.byte 0x00 24.--31. 1. " INTID575 ,Interrupt ID575 Priority/Priority Byte Offset 575 " hexmask.long.byte 0x00 16.--23. 1. " INTID574 ,Interrupt ID574 Priority/Priority Byte Offset 574 " hexmask.long.byte 0x00 8.--15. 1. " INTID573 ,Interrupt ID573 Priority/Priority Byte Offset 573 " hexmask.long.byte 0x00 0.--7. 1. " INTID572 ,Interrupt ID572 Priority/Priority Byte Offset 572 " else rgroup.long 0x620++0x03 line.long 0x00 "GICD_IPRIORITYR136,Interrupt Priority Register 136" rgroup.long 0x624++0x03 line.long 0x00 "GICD_IPRIORITYR137,Interrupt Priority Register 137" rgroup.long 0x628++0x03 line.long 0x00 "GICD_IPRIORITYR138,Interrupt Priority Register 138" rgroup.long 0x62C++0x03 line.long 0x00 "GICD_IPRIORITYR139,Interrupt Priority Register 139" rgroup.long 0x630++0x03 line.long 0x00 "GICD_IPRIORITYR140,Interrupt Priority Register 140" rgroup.long 0x634++0x03 line.long 0x00 "GICD_IPRIORITYR141,Interrupt Priority Register 141" rgroup.long 0x638++0x03 line.long 0x00 "GICD_IPRIORITYR142,Interrupt Priority Register 142" rgroup.long 0x63C++0x03 line.long 0x00 "GICD_IPRIORITYR143,Interrupt Priority Register 143" endif if (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x12) group.long 0x640++0x03 line.long 0x00 "GICD_IPRIORITYR144,Interrupt Priority Register 144" hexmask.long.byte 0x00 24.--31. 1. " INTID579 ,Interrupt ID579 Priority/Priority Byte Offset 579 " hexmask.long.byte 0x00 16.--23. 1. " INTID578 ,Interrupt ID578 Priority/Priority Byte Offset 578 " hexmask.long.byte 0x00 8.--15. 1. " INTID577 ,Interrupt ID577 Priority/Priority Byte Offset 577 " hexmask.long.byte 0x00 0.--7. 1. " INTID576 ,Interrupt ID576 Priority/Priority Byte Offset 576 " group.long 0x644++0x03 line.long 0x00 "GICD_IPRIORITYR145,Interrupt Priority Register 145" hexmask.long.byte 0x00 24.--31. 1. " INTID583 ,Interrupt ID583 Priority/Priority Byte Offset 583 " hexmask.long.byte 0x00 16.--23. 1. " INTID582 ,Interrupt ID582 Priority/Priority Byte Offset 582 " hexmask.long.byte 0x00 8.--15. 1. " INTID581 ,Interrupt ID581 Priority/Priority Byte Offset 581 " hexmask.long.byte 0x00 0.--7. 1. " INTID580 ,Interrupt ID580 Priority/Priority Byte Offset 580 " group.long 0x648++0x03 line.long 0x00 "GICD_IPRIORITYR146,Interrupt Priority Register 146" hexmask.long.byte 0x00 24.--31. 1. " INTID587 ,Interrupt ID587 Priority/Priority Byte Offset 587 " hexmask.long.byte 0x00 16.--23. 1. " INTID586 ,Interrupt ID586 Priority/Priority Byte Offset 586 " hexmask.long.byte 0x00 8.--15. 1. " INTID585 ,Interrupt ID585 Priority/Priority Byte Offset 585 " hexmask.long.byte 0x00 0.--7. 1. " INTID584 ,Interrupt ID584 Priority/Priority Byte Offset 584 " group.long 0x64C++0x03 line.long 0x00 "GICD_IPRIORITYR147,Interrupt Priority Register 147" hexmask.long.byte 0x00 24.--31. 1. " INTID591 ,Interrupt ID591 Priority/Priority Byte Offset 591 " hexmask.long.byte 0x00 16.--23. 1. " INTID590 ,Interrupt ID590 Priority/Priority Byte Offset 590 " hexmask.long.byte 0x00 8.--15. 1. " INTID589 ,Interrupt ID589 Priority/Priority Byte Offset 589 " hexmask.long.byte 0x00 0.--7. 1. " INTID588 ,Interrupt ID588 Priority/Priority Byte Offset 588 " group.long 0x650++0x03 line.long 0x00 "GICD_IPRIORITYR148,Interrupt Priority Register 148" hexmask.long.byte 0x00 24.--31. 1. " INTID595 ,Interrupt ID595 Priority/Priority Byte Offset 595 " hexmask.long.byte 0x00 16.--23. 1. " INTID594 ,Interrupt ID594 Priority/Priority Byte Offset 594 " hexmask.long.byte 0x00 8.--15. 1. " INTID593 ,Interrupt ID593 Priority/Priority Byte Offset 593 " hexmask.long.byte 0x00 0.--7. 1. " INTID592 ,Interrupt ID592 Priority/Priority Byte Offset 592 " group.long 0x654++0x03 line.long 0x00 "GICD_IPRIORITYR149,Interrupt Priority Register 149" hexmask.long.byte 0x00 24.--31. 1. " INTID599 ,Interrupt ID599 Priority/Priority Byte Offset 599 " hexmask.long.byte 0x00 16.--23. 1. " INTID598 ,Interrupt ID598 Priority/Priority Byte Offset 598 " hexmask.long.byte 0x00 8.--15. 1. " INTID597 ,Interrupt ID597 Priority/Priority Byte Offset 597 " hexmask.long.byte 0x00 0.--7. 1. " INTID596 ,Interrupt ID596 Priority/Priority Byte Offset 596 " group.long 0x658++0x03 line.long 0x00 "GICD_IPRIORITYR150,Interrupt Priority Register 150" hexmask.long.byte 0x00 24.--31. 1. " INTID603 ,Interrupt ID603 Priority/Priority Byte Offset 603 " hexmask.long.byte 0x00 16.--23. 1. " INTID602 ,Interrupt ID602 Priority/Priority Byte Offset 602 " hexmask.long.byte 0x00 8.--15. 1. " INTID601 ,Interrupt ID601 Priority/Priority Byte Offset 601 " hexmask.long.byte 0x00 0.--7. 1. " INTID600 ,Interrupt ID600 Priority/Priority Byte Offset 600 " group.long 0x65C++0x03 line.long 0x00 "GICD_IPRIORITYR151,Interrupt Priority Register 151" hexmask.long.byte 0x00 24.--31. 1. " INTID607 ,Interrupt ID607 Priority/Priority Byte Offset 607 " hexmask.long.byte 0x00 16.--23. 1. " INTID606 ,Interrupt ID606 Priority/Priority Byte Offset 606 " hexmask.long.byte 0x00 8.--15. 1. " INTID605 ,Interrupt ID605 Priority/Priority Byte Offset 605 " hexmask.long.byte 0x00 0.--7. 1. " INTID604 ,Interrupt ID604 Priority/Priority Byte Offset 604 " else rgroup.long 0x640++0x03 line.long 0x00 "GICD_IPRIORITYR144,Interrupt Priority Register 144" rgroup.long 0x644++0x03 line.long 0x00 "GICD_IPRIORITYR145,Interrupt Priority Register 145" rgroup.long 0x648++0x03 line.long 0x00 "GICD_IPRIORITYR146,Interrupt Priority Register 146" rgroup.long 0x64C++0x03 line.long 0x00 "GICD_IPRIORITYR147,Interrupt Priority Register 147" rgroup.long 0x650++0x03 line.long 0x00 "GICD_IPRIORITYR148,Interrupt Priority Register 148" rgroup.long 0x654++0x03 line.long 0x00 "GICD_IPRIORITYR149,Interrupt Priority Register 149" rgroup.long 0x658++0x03 line.long 0x00 "GICD_IPRIORITYR150,Interrupt Priority Register 150" rgroup.long 0x65C++0x03 line.long 0x00 "GICD_IPRIORITYR151,Interrupt Priority Register 151" endif if (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x13) group.long 0x660++0x03 line.long 0x00 "GICD_IPRIORITYR152,Interrupt Priority Register 152" hexmask.long.byte 0x00 24.--31. 1. " INTID611 ,Interrupt ID611 Priority/Priority Byte Offset 611 " hexmask.long.byte 0x00 16.--23. 1. " INTID610 ,Interrupt ID610 Priority/Priority Byte Offset 610 " hexmask.long.byte 0x00 8.--15. 1. " INTID609 ,Interrupt ID609 Priority/Priority Byte Offset 609 " hexmask.long.byte 0x00 0.--7. 1. " INTID608 ,Interrupt ID608 Priority/Priority Byte Offset 608 " group.long 0x664++0x03 line.long 0x00 "GICD_IPRIORITYR153,Interrupt Priority Register 153" hexmask.long.byte 0x00 24.--31. 1. " INTID615 ,Interrupt ID615 Priority/Priority Byte Offset 615 " hexmask.long.byte 0x00 16.--23. 1. " INTID614 ,Interrupt ID614 Priority/Priority Byte Offset 614 " hexmask.long.byte 0x00 8.--15. 1. " INTID613 ,Interrupt ID613 Priority/Priority Byte Offset 613 " hexmask.long.byte 0x00 0.--7. 1. " INTID612 ,Interrupt ID612 Priority/Priority Byte Offset 612 " group.long 0x668++0x03 line.long 0x00 "GICD_IPRIORITYR154,Interrupt Priority Register 154" hexmask.long.byte 0x00 24.--31. 1. " INTID619 ,Interrupt ID619 Priority/Priority Byte Offset 619 " hexmask.long.byte 0x00 16.--23. 1. " INTID618 ,Interrupt ID618 Priority/Priority Byte Offset 618 " hexmask.long.byte 0x00 8.--15. 1. " INTID617 ,Interrupt ID617 Priority/Priority Byte Offset 617 " hexmask.long.byte 0x00 0.--7. 1. " INTID616 ,Interrupt ID616 Priority/Priority Byte Offset 616 " group.long 0x66C++0x03 line.long 0x00 "GICD_IPRIORITYR155,Interrupt Priority Register 155" hexmask.long.byte 0x00 24.--31. 1. " INTID623 ,Interrupt ID623 Priority/Priority Byte Offset 623 " hexmask.long.byte 0x00 16.--23. 1. " INTID622 ,Interrupt ID622 Priority/Priority Byte Offset 622 " hexmask.long.byte 0x00 8.--15. 1. " INTID621 ,Interrupt ID621 Priority/Priority Byte Offset 621 " hexmask.long.byte 0x00 0.--7. 1. " INTID620 ,Interrupt ID620 Priority/Priority Byte Offset 620 " group.long 0x670++0x03 line.long 0x00 "GICD_IPRIORITYR156,Interrupt Priority Register 156" hexmask.long.byte 0x00 24.--31. 1. " INTID627 ,Interrupt ID627 Priority/Priority Byte Offset 627 " hexmask.long.byte 0x00 16.--23. 1. " INTID626 ,Interrupt ID626 Priority/Priority Byte Offset 626 " hexmask.long.byte 0x00 8.--15. 1. " INTID625 ,Interrupt ID625 Priority/Priority Byte Offset 625 " hexmask.long.byte 0x00 0.--7. 1. " INTID624 ,Interrupt ID624 Priority/Priority Byte Offset 624 " group.long 0x674++0x03 line.long 0x00 "GICD_IPRIORITYR157,Interrupt Priority Register 157" hexmask.long.byte 0x00 24.--31. 1. " INTID631 ,Interrupt ID631 Priority/Priority Byte Offset 631 " hexmask.long.byte 0x00 16.--23. 1. " INTID630 ,Interrupt ID630 Priority/Priority Byte Offset 630 " hexmask.long.byte 0x00 8.--15. 1. " INTID629 ,Interrupt ID629 Priority/Priority Byte Offset 629 " hexmask.long.byte 0x00 0.--7. 1. " INTID628 ,Interrupt ID628 Priority/Priority Byte Offset 628 " group.long 0x678++0x03 line.long 0x00 "GICD_IPRIORITYR158,Interrupt Priority Register 158" hexmask.long.byte 0x00 24.--31. 1. " INTID635 ,Interrupt ID635 Priority/Priority Byte Offset 635 " hexmask.long.byte 0x00 16.--23. 1. " INTID634 ,Interrupt ID634 Priority/Priority Byte Offset 634 " hexmask.long.byte 0x00 8.--15. 1. " INTID633 ,Interrupt ID633 Priority/Priority Byte Offset 633 " hexmask.long.byte 0x00 0.--7. 1. " INTID632 ,Interrupt ID632 Priority/Priority Byte Offset 632 " group.long 0x67C++0x03 line.long 0x00 "GICD_IPRIORITYR159,Interrupt Priority Register 159" hexmask.long.byte 0x00 24.--31. 1. " INTID639 ,Interrupt ID639 Priority/Priority Byte Offset 639 " hexmask.long.byte 0x00 16.--23. 1. " INTID638 ,Interrupt ID638 Priority/Priority Byte Offset 638 " hexmask.long.byte 0x00 8.--15. 1. " INTID637 ,Interrupt ID637 Priority/Priority Byte Offset 637 " hexmask.long.byte 0x00 0.--7. 1. " INTID636 ,Interrupt ID636 Priority/Priority Byte Offset 636 " else rgroup.long 0x660++0x03 line.long 0x00 "GICD_IPRIORITYR152,Interrupt Priority Register 152" rgroup.long 0x664++0x03 line.long 0x00 "GICD_IPRIORITYR153,Interrupt Priority Register 153" rgroup.long 0x668++0x03 line.long 0x00 "GICD_IPRIORITYR154,Interrupt Priority Register 154" rgroup.long 0x66C++0x03 line.long 0x00 "GICD_IPRIORITYR155,Interrupt Priority Register 155" rgroup.long 0x670++0x03 line.long 0x00 "GICD_IPRIORITYR156,Interrupt Priority Register 156" rgroup.long 0x674++0x03 line.long 0x00 "GICD_IPRIORITYR157,Interrupt Priority Register 157" rgroup.long 0x678++0x03 line.long 0x00 "GICD_IPRIORITYR158,Interrupt Priority Register 158" rgroup.long 0x67C++0x03 line.long 0x00 "GICD_IPRIORITYR159,Interrupt Priority Register 159" endif if (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x14) group.long 0x680++0x03 line.long 0x00 "GICD_IPRIORITYR160,Interrupt Priority Register 160" hexmask.long.byte 0x00 24.--31. 1. " INTID643 ,Interrupt ID643 Priority/Priority Byte Offset 643 " hexmask.long.byte 0x00 16.--23. 1. " INTID642 ,Interrupt ID642 Priority/Priority Byte Offset 642 " hexmask.long.byte 0x00 8.--15. 1. " INTID641 ,Interrupt ID641 Priority/Priority Byte Offset 641 " hexmask.long.byte 0x00 0.--7. 1. " INTID640 ,Interrupt ID640 Priority/Priority Byte Offset 640 " group.long 0x684++0x03 line.long 0x00 "GICD_IPRIORITYR161,Interrupt Priority Register 161" hexmask.long.byte 0x00 24.--31. 1. " INTID647 ,Interrupt ID647 Priority/Priority Byte Offset 647 " hexmask.long.byte 0x00 16.--23. 1. " INTID646 ,Interrupt ID646 Priority/Priority Byte Offset 646 " hexmask.long.byte 0x00 8.--15. 1. " INTID645 ,Interrupt ID645 Priority/Priority Byte Offset 645 " hexmask.long.byte 0x00 0.--7. 1. " INTID644 ,Interrupt ID644 Priority/Priority Byte Offset 644 " group.long 0x688++0x03 line.long 0x00 "GICD_IPRIORITYR162,Interrupt Priority Register 162" hexmask.long.byte 0x00 24.--31. 1. " INTID651 ,Interrupt ID651 Priority/Priority Byte Offset 651 " hexmask.long.byte 0x00 16.--23. 1. " INTID650 ,Interrupt ID650 Priority/Priority Byte Offset 650 " hexmask.long.byte 0x00 8.--15. 1. " INTID649 ,Interrupt ID649 Priority/Priority Byte Offset 649 " hexmask.long.byte 0x00 0.--7. 1. " INTID648 ,Interrupt ID648 Priority/Priority Byte Offset 648 " group.long 0x68C++0x03 line.long 0x00 "GICD_IPRIORITYR163,Interrupt Priority Register 163" hexmask.long.byte 0x00 24.--31. 1. " INTID655 ,Interrupt ID655 Priority/Priority Byte Offset 655 " hexmask.long.byte 0x00 16.--23. 1. " INTID654 ,Interrupt ID654 Priority/Priority Byte Offset 654 " hexmask.long.byte 0x00 8.--15. 1. " INTID653 ,Interrupt ID653 Priority/Priority Byte Offset 653 " hexmask.long.byte 0x00 0.--7. 1. " INTID652 ,Interrupt ID652 Priority/Priority Byte Offset 652 " group.long 0x690++0x03 line.long 0x00 "GICD_IPRIORITYR164,Interrupt Priority Register 164" hexmask.long.byte 0x00 24.--31. 1. " INTID659 ,Interrupt ID659 Priority/Priority Byte Offset 659 " hexmask.long.byte 0x00 16.--23. 1. " INTID658 ,Interrupt ID658 Priority/Priority Byte Offset 658 " hexmask.long.byte 0x00 8.--15. 1. " INTID657 ,Interrupt ID657 Priority/Priority Byte Offset 657 " hexmask.long.byte 0x00 0.--7. 1. " INTID656 ,Interrupt ID656 Priority/Priority Byte Offset 656 " group.long 0x694++0x03 line.long 0x00 "GICD_IPRIORITYR165,Interrupt Priority Register 165" hexmask.long.byte 0x00 24.--31. 1. " INTID663 ,Interrupt ID663 Priority/Priority Byte Offset 663 " hexmask.long.byte 0x00 16.--23. 1. " INTID662 ,Interrupt ID662 Priority/Priority Byte Offset 662 " hexmask.long.byte 0x00 8.--15. 1. " INTID661 ,Interrupt ID661 Priority/Priority Byte Offset 661 " hexmask.long.byte 0x00 0.--7. 1. " INTID660 ,Interrupt ID660 Priority/Priority Byte Offset 660 " group.long 0x698++0x03 line.long 0x00 "GICD_IPRIORITYR166,Interrupt Priority Register 166" hexmask.long.byte 0x00 24.--31. 1. " INTID667 ,Interrupt ID667 Priority/Priority Byte Offset 667 " hexmask.long.byte 0x00 16.--23. 1. " INTID666 ,Interrupt ID666 Priority/Priority Byte Offset 666 " hexmask.long.byte 0x00 8.--15. 1. " INTID665 ,Interrupt ID665 Priority/Priority Byte Offset 665 " hexmask.long.byte 0x00 0.--7. 1. " INTID664 ,Interrupt ID664 Priority/Priority Byte Offset 664 " group.long 0x69C++0x03 line.long 0x00 "GICD_IPRIORITYR167,Interrupt Priority Register 167" hexmask.long.byte 0x00 24.--31. 1. " INTID671 ,Interrupt ID671 Priority/Priority Byte Offset 671 " hexmask.long.byte 0x00 16.--23. 1. " INTID670 ,Interrupt ID670 Priority/Priority Byte Offset 670 " hexmask.long.byte 0x00 8.--15. 1. " INTID669 ,Interrupt ID669 Priority/Priority Byte Offset 669 " hexmask.long.byte 0x00 0.--7. 1. " INTID668 ,Interrupt ID668 Priority/Priority Byte Offset 668 " else rgroup.long 0x680++0x03 line.long 0x00 "GICD_IPRIORITYR160,Interrupt Priority Register 160" rgroup.long 0x684++0x03 line.long 0x00 "GICD_IPRIORITYR161,Interrupt Priority Register 161" rgroup.long 0x688++0x03 line.long 0x00 "GICD_IPRIORITYR162,Interrupt Priority Register 162" rgroup.long 0x68C++0x03 line.long 0x00 "GICD_IPRIORITYR163,Interrupt Priority Register 163" rgroup.long 0x690++0x03 line.long 0x00 "GICD_IPRIORITYR164,Interrupt Priority Register 164" rgroup.long 0x694++0x03 line.long 0x00 "GICD_IPRIORITYR165,Interrupt Priority Register 165" rgroup.long 0x698++0x03 line.long 0x00 "GICD_IPRIORITYR166,Interrupt Priority Register 166" rgroup.long 0x69C++0x03 line.long 0x00 "GICD_IPRIORITYR167,Interrupt Priority Register 167" endif if (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x15) group.long 0x6A0++0x03 line.long 0x00 "GICD_IPRIORITYR168,Interrupt Priority Register 168" hexmask.long.byte 0x00 24.--31. 1. " INTID675 ,Interrupt ID675 Priority/Priority Byte Offset 675 " hexmask.long.byte 0x00 16.--23. 1. " INTID674 ,Interrupt ID674 Priority/Priority Byte Offset 674 " hexmask.long.byte 0x00 8.--15. 1. " INTID673 ,Interrupt ID673 Priority/Priority Byte Offset 673 " hexmask.long.byte 0x00 0.--7. 1. " INTID672 ,Interrupt ID672 Priority/Priority Byte Offset 672 " group.long 0x6A4++0x03 line.long 0x00 "GICD_IPRIORITYR169,Interrupt Priority Register 169" hexmask.long.byte 0x00 24.--31. 1. " INTID679 ,Interrupt ID679 Priority/Priority Byte Offset 679 " hexmask.long.byte 0x00 16.--23. 1. " INTID678 ,Interrupt ID678 Priority/Priority Byte Offset 678 " hexmask.long.byte 0x00 8.--15. 1. " INTID677 ,Interrupt ID677 Priority/Priority Byte Offset 677 " hexmask.long.byte 0x00 0.--7. 1. " INTID676 ,Interrupt ID676 Priority/Priority Byte Offset 676 " group.long 0x6A8++0x03 line.long 0x00 "GICD_IPRIORITYR170,Interrupt Priority Register 170" hexmask.long.byte 0x00 24.--31. 1. " INTID683 ,Interrupt ID683 Priority/Priority Byte Offset 683 " hexmask.long.byte 0x00 16.--23. 1. " INTID682 ,Interrupt ID682 Priority/Priority Byte Offset 682 " hexmask.long.byte 0x00 8.--15. 1. " INTID681 ,Interrupt ID681 Priority/Priority Byte Offset 681 " hexmask.long.byte 0x00 0.--7. 1. " INTID680 ,Interrupt ID680 Priority/Priority Byte Offset 680 " group.long 0x6AC++0x03 line.long 0x00 "GICD_IPRIORITYR171,Interrupt Priority Register 171" hexmask.long.byte 0x00 24.--31. 1. " INTID687 ,Interrupt ID687 Priority/Priority Byte Offset 687 " hexmask.long.byte 0x00 16.--23. 1. " INTID686 ,Interrupt ID686 Priority/Priority Byte Offset 686 " hexmask.long.byte 0x00 8.--15. 1. " INTID685 ,Interrupt ID685 Priority/Priority Byte Offset 685 " hexmask.long.byte 0x00 0.--7. 1. " INTID684 ,Interrupt ID684 Priority/Priority Byte Offset 684 " group.long 0x6B0++0x03 line.long 0x00 "GICD_IPRIORITYR172,Interrupt Priority Register 172" hexmask.long.byte 0x00 24.--31. 1. " INTID691 ,Interrupt ID691 Priority/Priority Byte Offset 691 " hexmask.long.byte 0x00 16.--23. 1. " INTID690 ,Interrupt ID690 Priority/Priority Byte Offset 690 " hexmask.long.byte 0x00 8.--15. 1. " INTID689 ,Interrupt ID689 Priority/Priority Byte Offset 689 " hexmask.long.byte 0x00 0.--7. 1. " INTID688 ,Interrupt ID688 Priority/Priority Byte Offset 688 " group.long 0x6B4++0x03 line.long 0x00 "GICD_IPRIORITYR173,Interrupt Priority Register 173" hexmask.long.byte 0x00 24.--31. 1. " INTID695 ,Interrupt ID695 Priority/Priority Byte Offset 695 " hexmask.long.byte 0x00 16.--23. 1. " INTID694 ,Interrupt ID694 Priority/Priority Byte Offset 694 " hexmask.long.byte 0x00 8.--15. 1. " INTID693 ,Interrupt ID693 Priority/Priority Byte Offset 693 " hexmask.long.byte 0x00 0.--7. 1. " INTID692 ,Interrupt ID692 Priority/Priority Byte Offset 692 " group.long 0x6B8++0x03 line.long 0x00 "GICD_IPRIORITYR174,Interrupt Priority Register 174" hexmask.long.byte 0x00 24.--31. 1. " INTID699 ,Interrupt ID699 Priority/Priority Byte Offset 699 " hexmask.long.byte 0x00 16.--23. 1. " INTID698 ,Interrupt ID698 Priority/Priority Byte Offset 698 " hexmask.long.byte 0x00 8.--15. 1. " INTID697 ,Interrupt ID697 Priority/Priority Byte Offset 697 " hexmask.long.byte 0x00 0.--7. 1. " INTID696 ,Interrupt ID696 Priority/Priority Byte Offset 696 " group.long 0x6BC++0x03 line.long 0x00 "GICD_IPRIORITYR175,Interrupt Priority Register 175" hexmask.long.byte 0x00 24.--31. 1. " INTID703 ,Interrupt ID703 Priority/Priority Byte Offset 703 " hexmask.long.byte 0x00 16.--23. 1. " INTID702 ,Interrupt ID702 Priority/Priority Byte Offset 702 " hexmask.long.byte 0x00 8.--15. 1. " INTID701 ,Interrupt ID701 Priority/Priority Byte Offset 701 " hexmask.long.byte 0x00 0.--7. 1. " INTID700 ,Interrupt ID700 Priority/Priority Byte Offset 700 " else rgroup.long 0x6A0++0x03 line.long 0x00 "GICD_IPRIORITYR168,Interrupt Priority Register 168" rgroup.long 0x6A4++0x03 line.long 0x00 "GICD_IPRIORITYR169,Interrupt Priority Register 169" rgroup.long 0x6A8++0x03 line.long 0x00 "GICD_IPRIORITYR170,Interrupt Priority Register 170" rgroup.long 0x6AC++0x03 line.long 0x00 "GICD_IPRIORITYR171,Interrupt Priority Register 171" rgroup.long 0x6B0++0x03 line.long 0x00 "GICD_IPRIORITYR172,Interrupt Priority Register 172" rgroup.long 0x6B4++0x03 line.long 0x00 "GICD_IPRIORITYR173,Interrupt Priority Register 173" rgroup.long 0x6B8++0x03 line.long 0x00 "GICD_IPRIORITYR174,Interrupt Priority Register 174" rgroup.long 0x6BC++0x03 line.long 0x00 "GICD_IPRIORITYR175,Interrupt Priority Register 175" endif if (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x16) group.long 0x6C0++0x03 line.long 0x00 "GICD_IPRIORITYR176,Interrupt Priority Register 176" hexmask.long.byte 0x00 24.--31. 1. " INTID707 ,Interrupt ID707 Priority/Priority Byte Offset 707 " hexmask.long.byte 0x00 16.--23. 1. " INTID706 ,Interrupt ID706 Priority/Priority Byte Offset 706 " hexmask.long.byte 0x00 8.--15. 1. " INTID705 ,Interrupt ID705 Priority/Priority Byte Offset 705 " hexmask.long.byte 0x00 0.--7. 1. " INTID704 ,Interrupt ID704 Priority/Priority Byte Offset 704 " group.long 0x6C4++0x03 line.long 0x00 "GICD_IPRIORITYR177,Interrupt Priority Register 177" hexmask.long.byte 0x00 24.--31. 1. " INTID711 ,Interrupt ID711 Priority/Priority Byte Offset 711 " hexmask.long.byte 0x00 16.--23. 1. " INTID710 ,Interrupt ID710 Priority/Priority Byte Offset 710 " hexmask.long.byte 0x00 8.--15. 1. " INTID709 ,Interrupt ID709 Priority/Priority Byte Offset 709 " hexmask.long.byte 0x00 0.--7. 1. " INTID708 ,Interrupt ID708 Priority/Priority Byte Offset 708 " group.long 0x6C8++0x03 line.long 0x00 "GICD_IPRIORITYR178,Interrupt Priority Register 178" hexmask.long.byte 0x00 24.--31. 1. " INTID715 ,Interrupt ID715 Priority/Priority Byte Offset 715 " hexmask.long.byte 0x00 16.--23. 1. " INTID714 ,Interrupt ID714 Priority/Priority Byte Offset 714 " hexmask.long.byte 0x00 8.--15. 1. " INTID713 ,Interrupt ID713 Priority/Priority Byte Offset 713 " hexmask.long.byte 0x00 0.--7. 1. " INTID712 ,Interrupt ID712 Priority/Priority Byte Offset 712 " group.long 0x6CC++0x03 line.long 0x00 "GICD_IPRIORITYR179,Interrupt Priority Register 179" hexmask.long.byte 0x00 24.--31. 1. " INTID719 ,Interrupt ID719 Priority/Priority Byte Offset 719 " hexmask.long.byte 0x00 16.--23. 1. " INTID718 ,Interrupt ID718 Priority/Priority Byte Offset 718 " hexmask.long.byte 0x00 8.--15. 1. " INTID717 ,Interrupt ID717 Priority/Priority Byte Offset 717 " hexmask.long.byte 0x00 0.--7. 1. " INTID716 ,Interrupt ID716 Priority/Priority Byte Offset 716 " group.long 0x6D0++0x03 line.long 0x00 "GICD_IPRIORITYR180,Interrupt Priority Register 180" hexmask.long.byte 0x00 24.--31. 1. " INTID723 ,Interrupt ID723 Priority/Priority Byte Offset 723 " hexmask.long.byte 0x00 16.--23. 1. " INTID722 ,Interrupt ID722 Priority/Priority Byte Offset 722 " hexmask.long.byte 0x00 8.--15. 1. " INTID721 ,Interrupt ID721 Priority/Priority Byte Offset 721 " hexmask.long.byte 0x00 0.--7. 1. " INTID720 ,Interrupt ID720 Priority/Priority Byte Offset 720 " group.long 0x6D4++0x03 line.long 0x00 "GICD_IPRIORITYR181,Interrupt Priority Register 181" hexmask.long.byte 0x00 24.--31. 1. " INTID727 ,Interrupt ID727 Priority/Priority Byte Offset 727 " hexmask.long.byte 0x00 16.--23. 1. " INTID726 ,Interrupt ID726 Priority/Priority Byte Offset 726 " hexmask.long.byte 0x00 8.--15. 1. " INTID725 ,Interrupt ID725 Priority/Priority Byte Offset 725 " hexmask.long.byte 0x00 0.--7. 1. " INTID724 ,Interrupt ID724 Priority/Priority Byte Offset 724 " group.long 0x6D8++0x03 line.long 0x00 "GICD_IPRIORITYR182,Interrupt Priority Register 182" hexmask.long.byte 0x00 24.--31. 1. " INTID731 ,Interrupt ID731 Priority/Priority Byte Offset 731 " hexmask.long.byte 0x00 16.--23. 1. " INTID730 ,Interrupt ID730 Priority/Priority Byte Offset 730 " hexmask.long.byte 0x00 8.--15. 1. " INTID729 ,Interrupt ID729 Priority/Priority Byte Offset 729 " hexmask.long.byte 0x00 0.--7. 1. " INTID728 ,Interrupt ID728 Priority/Priority Byte Offset 728 " group.long 0x6DC++0x03 line.long 0x00 "GICD_IPRIORITYR183,Interrupt Priority Register 183" hexmask.long.byte 0x00 24.--31. 1. " INTID735 ,Interrupt ID735 Priority/Priority Byte Offset 735 " hexmask.long.byte 0x00 16.--23. 1. " INTID734 ,Interrupt ID734 Priority/Priority Byte Offset 734 " hexmask.long.byte 0x00 8.--15. 1. " INTID733 ,Interrupt ID733 Priority/Priority Byte Offset 733 " hexmask.long.byte 0x00 0.--7. 1. " INTID732 ,Interrupt ID732 Priority/Priority Byte Offset 732 " else rgroup.long 0x6C0++0x03 line.long 0x00 "GICD_IPRIORITYR176,Interrupt Priority Register 176" rgroup.long 0x6C4++0x03 line.long 0x00 "GICD_IPRIORITYR177,Interrupt Priority Register 177" rgroup.long 0x6C8++0x03 line.long 0x00 "GICD_IPRIORITYR178,Interrupt Priority Register 178" rgroup.long 0x6CC++0x03 line.long 0x00 "GICD_IPRIORITYR179,Interrupt Priority Register 179" rgroup.long 0x6D0++0x03 line.long 0x00 "GICD_IPRIORITYR180,Interrupt Priority Register 180" rgroup.long 0x6D4++0x03 line.long 0x00 "GICD_IPRIORITYR181,Interrupt Priority Register 181" rgroup.long 0x6D8++0x03 line.long 0x00 "GICD_IPRIORITYR182,Interrupt Priority Register 182" rgroup.long 0x6DC++0x03 line.long 0x00 "GICD_IPRIORITYR183,Interrupt Priority Register 183" endif if (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x17) group.long 0x6E0++0x03 line.long 0x00 "GICD_IPRIORITYR184,Interrupt Priority Register 184" hexmask.long.byte 0x00 24.--31. 1. " INTID739 ,Interrupt ID739 Priority/Priority Byte Offset 739 " hexmask.long.byte 0x00 16.--23. 1. " INTID738 ,Interrupt ID738 Priority/Priority Byte Offset 738 " hexmask.long.byte 0x00 8.--15. 1. " INTID737 ,Interrupt ID737 Priority/Priority Byte Offset 737 " hexmask.long.byte 0x00 0.--7. 1. " INTID736 ,Interrupt ID736 Priority/Priority Byte Offset 736 " group.long 0x6E4++0x03 line.long 0x00 "GICD_IPRIORITYR185,Interrupt Priority Register 185" hexmask.long.byte 0x00 24.--31. 1. " INTID743 ,Interrupt ID743 Priority/Priority Byte Offset 743 " hexmask.long.byte 0x00 16.--23. 1. " INTID742 ,Interrupt ID742 Priority/Priority Byte Offset 742 " hexmask.long.byte 0x00 8.--15. 1. " INTID741 ,Interrupt ID741 Priority/Priority Byte Offset 741 " hexmask.long.byte 0x00 0.--7. 1. " INTID740 ,Interrupt ID740 Priority/Priority Byte Offset 740 " group.long 0x6E8++0x03 line.long 0x00 "GICD_IPRIORITYR186,Interrupt Priority Register 186" hexmask.long.byte 0x00 24.--31. 1. " INTID747 ,Interrupt ID747 Priority/Priority Byte Offset 747 " hexmask.long.byte 0x00 16.--23. 1. " INTID746 ,Interrupt ID746 Priority/Priority Byte Offset 746 " hexmask.long.byte 0x00 8.--15. 1. " INTID745 ,Interrupt ID745 Priority/Priority Byte Offset 745 " hexmask.long.byte 0x00 0.--7. 1. " INTID744 ,Interrupt ID744 Priority/Priority Byte Offset 744 " group.long 0x6EC++0x03 line.long 0x00 "GICD_IPRIORITYR187,Interrupt Priority Register 187" hexmask.long.byte 0x00 24.--31. 1. " INTID751 ,Interrupt ID751 Priority/Priority Byte Offset 751 " hexmask.long.byte 0x00 16.--23. 1. " INTID750 ,Interrupt ID750 Priority/Priority Byte Offset 750 " hexmask.long.byte 0x00 8.--15. 1. " INTID749 ,Interrupt ID749 Priority/Priority Byte Offset 749 " hexmask.long.byte 0x00 0.--7. 1. " INTID748 ,Interrupt ID748 Priority/Priority Byte Offset 748 " group.long 0x6F0++0x03 line.long 0x00 "GICD_IPRIORITYR188,Interrupt Priority Register 188" hexmask.long.byte 0x00 24.--31. 1. " INTID755 ,Interrupt ID755 Priority/Priority Byte Offset 755 " hexmask.long.byte 0x00 16.--23. 1. " INTID754 ,Interrupt ID754 Priority/Priority Byte Offset 754 " hexmask.long.byte 0x00 8.--15. 1. " INTID753 ,Interrupt ID753 Priority/Priority Byte Offset 753 " hexmask.long.byte 0x00 0.--7. 1. " INTID752 ,Interrupt ID752 Priority/Priority Byte Offset 752 " group.long 0x6F4++0x03 line.long 0x00 "GICD_IPRIORITYR189,Interrupt Priority Register 189" hexmask.long.byte 0x00 24.--31. 1. " INTID759 ,Interrupt ID759 Priority/Priority Byte Offset 759 " hexmask.long.byte 0x00 16.--23. 1. " INTID758 ,Interrupt ID758 Priority/Priority Byte Offset 758 " hexmask.long.byte 0x00 8.--15. 1. " INTID757 ,Interrupt ID757 Priority/Priority Byte Offset 757 " hexmask.long.byte 0x00 0.--7. 1. " INTID756 ,Interrupt ID756 Priority/Priority Byte Offset 756 " group.long 0x6F8++0x03 line.long 0x00 "GICD_IPRIORITYR190,Interrupt Priority Register 190" hexmask.long.byte 0x00 24.--31. 1. " INTID763 ,Interrupt ID763 Priority/Priority Byte Offset 763 " hexmask.long.byte 0x00 16.--23. 1. " INTID762 ,Interrupt ID762 Priority/Priority Byte Offset 762 " hexmask.long.byte 0x00 8.--15. 1. " INTID761 ,Interrupt ID761 Priority/Priority Byte Offset 761 " hexmask.long.byte 0x00 0.--7. 1. " INTID760 ,Interrupt ID760 Priority/Priority Byte Offset 760 " group.long 0x6FC++0x03 line.long 0x00 "GICD_IPRIORITYR191,Interrupt Priority Register 191" hexmask.long.byte 0x00 24.--31. 1. " INTID767 ,Interrupt ID767 Priority/Priority Byte Offset 767 " hexmask.long.byte 0x00 16.--23. 1. " INTID766 ,Interrupt ID766 Priority/Priority Byte Offset 766 " hexmask.long.byte 0x00 8.--15. 1. " INTID765 ,Interrupt ID765 Priority/Priority Byte Offset 765 " hexmask.long.byte 0x00 0.--7. 1. " INTID764 ,Interrupt ID764 Priority/Priority Byte Offset 764 " else rgroup.long 0x6E0++0x03 line.long 0x00 "GICD_IPRIORITYR184,Interrupt Priority Register 184" rgroup.long 0x6E4++0x03 line.long 0x00 "GICD_IPRIORITYR185,Interrupt Priority Register 185" rgroup.long 0x6E8++0x03 line.long 0x00 "GICD_IPRIORITYR186,Interrupt Priority Register 186" rgroup.long 0x6EC++0x03 line.long 0x00 "GICD_IPRIORITYR187,Interrupt Priority Register 187" rgroup.long 0x6F0++0x03 line.long 0x00 "GICD_IPRIORITYR188,Interrupt Priority Register 188" rgroup.long 0x6F4++0x03 line.long 0x00 "GICD_IPRIORITYR189,Interrupt Priority Register 189" rgroup.long 0x6F8++0x03 line.long 0x00 "GICD_IPRIORITYR190,Interrupt Priority Register 190" rgroup.long 0x6FC++0x03 line.long 0x00 "GICD_IPRIORITYR191,Interrupt Priority Register 191" endif if (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x18) group.long 0x700++0x03 line.long 0x00 "GICD_IPRIORITYR192,Interrupt Priority Register 192" hexmask.long.byte 0x00 24.--31. 1. " INTID771 ,Interrupt ID771 Priority/Priority Byte Offset 771 " hexmask.long.byte 0x00 16.--23. 1. " INTID770 ,Interrupt ID770 Priority/Priority Byte Offset 770 " hexmask.long.byte 0x00 8.--15. 1. " INTID769 ,Interrupt ID769 Priority/Priority Byte Offset 769 " hexmask.long.byte 0x00 0.--7. 1. " INTID768 ,Interrupt ID768 Priority/Priority Byte Offset 768 " group.long 0x704++0x03 line.long 0x00 "GICD_IPRIORITYR193,Interrupt Priority Register 193" hexmask.long.byte 0x00 24.--31. 1. " INTID775 ,Interrupt ID775 Priority/Priority Byte Offset 775 " hexmask.long.byte 0x00 16.--23. 1. " INTID774 ,Interrupt ID774 Priority/Priority Byte Offset 774 " hexmask.long.byte 0x00 8.--15. 1. " INTID773 ,Interrupt ID773 Priority/Priority Byte Offset 773 " hexmask.long.byte 0x00 0.--7. 1. " INTID772 ,Interrupt ID772 Priority/Priority Byte Offset 772 " group.long 0x708++0x03 line.long 0x00 "GICD_IPRIORITYR194,Interrupt Priority Register 194" hexmask.long.byte 0x00 24.--31. 1. " INTID779 ,Interrupt ID779 Priority/Priority Byte Offset 779 " hexmask.long.byte 0x00 16.--23. 1. " INTID778 ,Interrupt ID778 Priority/Priority Byte Offset 778 " hexmask.long.byte 0x00 8.--15. 1. " INTID777 ,Interrupt ID777 Priority/Priority Byte Offset 777 " hexmask.long.byte 0x00 0.--7. 1. " INTID776 ,Interrupt ID776 Priority/Priority Byte Offset 776 " group.long 0x70C++0x03 line.long 0x00 "GICD_IPRIORITYR195,Interrupt Priority Register 195" hexmask.long.byte 0x00 24.--31. 1. " INTID783 ,Interrupt ID783 Priority/Priority Byte Offset 783 " hexmask.long.byte 0x00 16.--23. 1. " INTID782 ,Interrupt ID782 Priority/Priority Byte Offset 782 " hexmask.long.byte 0x00 8.--15. 1. " INTID781 ,Interrupt ID781 Priority/Priority Byte Offset 781 " hexmask.long.byte 0x00 0.--7. 1. " INTID780 ,Interrupt ID780 Priority/Priority Byte Offset 780 " group.long 0x710++0x03 line.long 0x00 "GICD_IPRIORITYR196,Interrupt Priority Register 196" hexmask.long.byte 0x00 24.--31. 1. " INTID787 ,Interrupt ID787 Priority/Priority Byte Offset 787 " hexmask.long.byte 0x00 16.--23. 1. " INTID786 ,Interrupt ID786 Priority/Priority Byte Offset 786 " hexmask.long.byte 0x00 8.--15. 1. " INTID785 ,Interrupt ID785 Priority/Priority Byte Offset 785 " hexmask.long.byte 0x00 0.--7. 1. " INTID784 ,Interrupt ID784 Priority/Priority Byte Offset 784 " group.long 0x714++0x03 line.long 0x00 "GICD_IPRIORITYR197,Interrupt Priority Register 197" hexmask.long.byte 0x00 24.--31. 1. " INTID791 ,Interrupt ID791 Priority/Priority Byte Offset 791 " hexmask.long.byte 0x00 16.--23. 1. " INTID790 ,Interrupt ID790 Priority/Priority Byte Offset 790 " hexmask.long.byte 0x00 8.--15. 1. " INTID789 ,Interrupt ID789 Priority/Priority Byte Offset 789 " hexmask.long.byte 0x00 0.--7. 1. " INTID788 ,Interrupt ID788 Priority/Priority Byte Offset 788 " group.long 0x718++0x03 line.long 0x00 "GICD_IPRIORITYR198,Interrupt Priority Register 198" hexmask.long.byte 0x00 24.--31. 1. " INTID795 ,Interrupt ID795 Priority/Priority Byte Offset 795 " hexmask.long.byte 0x00 16.--23. 1. " INTID794 ,Interrupt ID794 Priority/Priority Byte Offset 794 " hexmask.long.byte 0x00 8.--15. 1. " INTID793 ,Interrupt ID793 Priority/Priority Byte Offset 793 " hexmask.long.byte 0x00 0.--7. 1. " INTID792 ,Interrupt ID792 Priority/Priority Byte Offset 792 " group.long 0x71C++0x03 line.long 0x00 "GICD_IPRIORITYR199,Interrupt Priority Register 199" hexmask.long.byte 0x00 24.--31. 1. " INTID799 ,Interrupt ID799 Priority/Priority Byte Offset 799 " hexmask.long.byte 0x00 16.--23. 1. " INTID798 ,Interrupt ID798 Priority/Priority Byte Offset 798 " hexmask.long.byte 0x00 8.--15. 1. " INTID797 ,Interrupt ID797 Priority/Priority Byte Offset 797 " hexmask.long.byte 0x00 0.--7. 1. " INTID796 ,Interrupt ID796 Priority/Priority Byte Offset 796 " else rgroup.long 0x700++0x03 line.long 0x00 "GICD_IPRIORITYR192,Interrupt Priority Register 192" rgroup.long 0x704++0x03 line.long 0x00 "GICD_IPRIORITYR193,Interrupt Priority Register 193" rgroup.long 0x708++0x03 line.long 0x00 "GICD_IPRIORITYR194,Interrupt Priority Register 194" rgroup.long 0x70C++0x03 line.long 0x00 "GICD_IPRIORITYR195,Interrupt Priority Register 195" rgroup.long 0x710++0x03 line.long 0x00 "GICD_IPRIORITYR196,Interrupt Priority Register 196" rgroup.long 0x714++0x03 line.long 0x00 "GICD_IPRIORITYR197,Interrupt Priority Register 197" rgroup.long 0x718++0x03 line.long 0x00 "GICD_IPRIORITYR198,Interrupt Priority Register 198" rgroup.long 0x71C++0x03 line.long 0x00 "GICD_IPRIORITYR199,Interrupt Priority Register 199" endif if (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x19) group.long 0x720++0x03 line.long 0x00 "GICD_IPRIORITYR200,Interrupt Priority Register 200" hexmask.long.byte 0x00 24.--31. 1. " INTID803 ,Interrupt ID803 Priority/Priority Byte Offset 803 " hexmask.long.byte 0x00 16.--23. 1. " INTID802 ,Interrupt ID802 Priority/Priority Byte Offset 802 " hexmask.long.byte 0x00 8.--15. 1. " INTID801 ,Interrupt ID801 Priority/Priority Byte Offset 801 " hexmask.long.byte 0x00 0.--7. 1. " INTID800 ,Interrupt ID800 Priority/Priority Byte Offset 800 " group.long 0x724++0x03 line.long 0x00 "GICD_IPRIORITYR201,Interrupt Priority Register 201" hexmask.long.byte 0x00 24.--31. 1. " INTID807 ,Interrupt ID807 Priority/Priority Byte Offset 807 " hexmask.long.byte 0x00 16.--23. 1. " INTID806 ,Interrupt ID806 Priority/Priority Byte Offset 806 " hexmask.long.byte 0x00 8.--15. 1. " INTID805 ,Interrupt ID805 Priority/Priority Byte Offset 805 " hexmask.long.byte 0x00 0.--7. 1. " INTID804 ,Interrupt ID804 Priority/Priority Byte Offset 804 " group.long 0x728++0x03 line.long 0x00 "GICD_IPRIORITYR202,Interrupt Priority Register 202" hexmask.long.byte 0x00 24.--31. 1. " INTID811 ,Interrupt ID811 Priority/Priority Byte Offset 811 " hexmask.long.byte 0x00 16.--23. 1. " INTID810 ,Interrupt ID810 Priority/Priority Byte Offset 810 " hexmask.long.byte 0x00 8.--15. 1. " INTID809 ,Interrupt ID809 Priority/Priority Byte Offset 809 " hexmask.long.byte 0x00 0.--7. 1. " INTID808 ,Interrupt ID808 Priority/Priority Byte Offset 808 " group.long 0x72C++0x03 line.long 0x00 "GICD_IPRIORITYR203,Interrupt Priority Register 203" hexmask.long.byte 0x00 24.--31. 1. " INTID815 ,Interrupt ID815 Priority/Priority Byte Offset 815 " hexmask.long.byte 0x00 16.--23. 1. " INTID814 ,Interrupt ID814 Priority/Priority Byte Offset 814 " hexmask.long.byte 0x00 8.--15. 1. " INTID813 ,Interrupt ID813 Priority/Priority Byte Offset 813 " hexmask.long.byte 0x00 0.--7. 1. " INTID812 ,Interrupt ID812 Priority/Priority Byte Offset 812 " group.long 0x730++0x03 line.long 0x00 "GICD_IPRIORITYR204,Interrupt Priority Register 204" hexmask.long.byte 0x00 24.--31. 1. " INTID819 ,Interrupt ID819 Priority/Priority Byte Offset 819 " hexmask.long.byte 0x00 16.--23. 1. " INTID818 ,Interrupt ID818 Priority/Priority Byte Offset 818 " hexmask.long.byte 0x00 8.--15. 1. " INTID817 ,Interrupt ID817 Priority/Priority Byte Offset 817 " hexmask.long.byte 0x00 0.--7. 1. " INTID816 ,Interrupt ID816 Priority/Priority Byte Offset 816 " group.long 0x734++0x03 line.long 0x00 "GICD_IPRIORITYR205,Interrupt Priority Register 205" hexmask.long.byte 0x00 24.--31. 1. " INTID823 ,Interrupt ID823 Priority/Priority Byte Offset 823 " hexmask.long.byte 0x00 16.--23. 1. " INTID822 ,Interrupt ID822 Priority/Priority Byte Offset 822 " hexmask.long.byte 0x00 8.--15. 1. " INTID821 ,Interrupt ID821 Priority/Priority Byte Offset 821 " hexmask.long.byte 0x00 0.--7. 1. " INTID820 ,Interrupt ID820 Priority/Priority Byte Offset 820 " group.long 0x738++0x03 line.long 0x00 "GICD_IPRIORITYR206,Interrupt Priority Register 206" hexmask.long.byte 0x00 24.--31. 1. " INTID827 ,Interrupt ID827 Priority/Priority Byte Offset 827 " hexmask.long.byte 0x00 16.--23. 1. " INTID826 ,Interrupt ID826 Priority/Priority Byte Offset 826 " hexmask.long.byte 0x00 8.--15. 1. " INTID825 ,Interrupt ID825 Priority/Priority Byte Offset 825 " hexmask.long.byte 0x00 0.--7. 1. " INTID824 ,Interrupt ID824 Priority/Priority Byte Offset 824 " group.long 0x73C++0x03 line.long 0x00 "GICD_IPRIORITYR207,Interrupt Priority Register 207" hexmask.long.byte 0x00 24.--31. 1. " INTID831 ,Interrupt ID831 Priority/Priority Byte Offset 831 " hexmask.long.byte 0x00 16.--23. 1. " INTID830 ,Interrupt ID830 Priority/Priority Byte Offset 830 " hexmask.long.byte 0x00 8.--15. 1. " INTID829 ,Interrupt ID829 Priority/Priority Byte Offset 829 " hexmask.long.byte 0x00 0.--7. 1. " INTID828 ,Interrupt ID828 Priority/Priority Byte Offset 828 " else rgroup.long 0x720++0x03 line.long 0x00 "GICD_IPRIORITYR200,Interrupt Priority Register 200" rgroup.long 0x724++0x03 line.long 0x00 "GICD_IPRIORITYR201,Interrupt Priority Register 201" rgroup.long 0x728++0x03 line.long 0x00 "GICD_IPRIORITYR202,Interrupt Priority Register 202" rgroup.long 0x72C++0x03 line.long 0x00 "GICD_IPRIORITYR203,Interrupt Priority Register 203" rgroup.long 0x730++0x03 line.long 0x00 "GICD_IPRIORITYR204,Interrupt Priority Register 204" rgroup.long 0x734++0x03 line.long 0x00 "GICD_IPRIORITYR205,Interrupt Priority Register 205" rgroup.long 0x738++0x03 line.long 0x00 "GICD_IPRIORITYR206,Interrupt Priority Register 206" rgroup.long 0x73C++0x03 line.long 0x00 "GICD_IPRIORITYR207,Interrupt Priority Register 207" endif if (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x1A) group.long 0x740++0x03 line.long 0x00 "GICD_IPRIORITYR208,Interrupt Priority Register 208" hexmask.long.byte 0x00 24.--31. 1. " INTID835 ,Interrupt ID835 Priority/Priority Byte Offset 835 " hexmask.long.byte 0x00 16.--23. 1. " INTID834 ,Interrupt ID834 Priority/Priority Byte Offset 834 " hexmask.long.byte 0x00 8.--15. 1. " INTID833 ,Interrupt ID833 Priority/Priority Byte Offset 833 " hexmask.long.byte 0x00 0.--7. 1. " INTID832 ,Interrupt ID832 Priority/Priority Byte Offset 832 " group.long 0x744++0x03 line.long 0x00 "GICD_IPRIORITYR209,Interrupt Priority Register 209" hexmask.long.byte 0x00 24.--31. 1. " INTID839 ,Interrupt ID839 Priority/Priority Byte Offset 839 " hexmask.long.byte 0x00 16.--23. 1. " INTID838 ,Interrupt ID838 Priority/Priority Byte Offset 838 " hexmask.long.byte 0x00 8.--15. 1. " INTID837 ,Interrupt ID837 Priority/Priority Byte Offset 837 " hexmask.long.byte 0x00 0.--7. 1. " INTID836 ,Interrupt ID836 Priority/Priority Byte Offset 836 " group.long 0x748++0x03 line.long 0x00 "GICD_IPRIORITYR210,Interrupt Priority Register 210" hexmask.long.byte 0x00 24.--31. 1. " INTID843 ,Interrupt ID843 Priority/Priority Byte Offset 843 " hexmask.long.byte 0x00 16.--23. 1. " INTID842 ,Interrupt ID842 Priority/Priority Byte Offset 842 " hexmask.long.byte 0x00 8.--15. 1. " INTID841 ,Interrupt ID841 Priority/Priority Byte Offset 841 " hexmask.long.byte 0x00 0.--7. 1. " INTID840 ,Interrupt ID840 Priority/Priority Byte Offset 840 " group.long 0x74C++0x03 line.long 0x00 "GICD_IPRIORITYR211,Interrupt Priority Register 211" hexmask.long.byte 0x00 24.--31. 1. " INTID847 ,Interrupt ID847 Priority/Priority Byte Offset 847 " hexmask.long.byte 0x00 16.--23. 1. " INTID846 ,Interrupt ID846 Priority/Priority Byte Offset 846 " hexmask.long.byte 0x00 8.--15. 1. " INTID845 ,Interrupt ID845 Priority/Priority Byte Offset 845 " hexmask.long.byte 0x00 0.--7. 1. " INTID844 ,Interrupt ID844 Priority/Priority Byte Offset 844 " group.long 0x750++0x03 line.long 0x00 "GICD_IPRIORITYR212,Interrupt Priority Register 212" hexmask.long.byte 0x00 24.--31. 1. " INTID851 ,Interrupt ID851 Priority/Priority Byte Offset 851 " hexmask.long.byte 0x00 16.--23. 1. " INTID850 ,Interrupt ID850 Priority/Priority Byte Offset 850 " hexmask.long.byte 0x00 8.--15. 1. " INTID849 ,Interrupt ID849 Priority/Priority Byte Offset 849 " hexmask.long.byte 0x00 0.--7. 1. " INTID848 ,Interrupt ID848 Priority/Priority Byte Offset 848 " group.long 0x754++0x03 line.long 0x00 "GICD_IPRIORITYR213,Interrupt Priority Register 213" hexmask.long.byte 0x00 24.--31. 1. " INTID855 ,Interrupt ID855 Priority/Priority Byte Offset 855 " hexmask.long.byte 0x00 16.--23. 1. " INTID854 ,Interrupt ID854 Priority/Priority Byte Offset 854 " hexmask.long.byte 0x00 8.--15. 1. " INTID853 ,Interrupt ID853 Priority/Priority Byte Offset 853 " hexmask.long.byte 0x00 0.--7. 1. " INTID852 ,Interrupt ID852 Priority/Priority Byte Offset 852 " group.long 0x758++0x03 line.long 0x00 "GICD_IPRIORITYR214,Interrupt Priority Register 214" hexmask.long.byte 0x00 24.--31. 1. " INTID859 ,Interrupt ID859 Priority/Priority Byte Offset 859 " hexmask.long.byte 0x00 16.--23. 1. " INTID858 ,Interrupt ID858 Priority/Priority Byte Offset 858 " hexmask.long.byte 0x00 8.--15. 1. " INTID857 ,Interrupt ID857 Priority/Priority Byte Offset 857 " hexmask.long.byte 0x00 0.--7. 1. " INTID856 ,Interrupt ID856 Priority/Priority Byte Offset 856 " group.long 0x75C++0x03 line.long 0x00 "GICD_IPRIORITYR215,Interrupt Priority Register 215" hexmask.long.byte 0x00 24.--31. 1. " INTID863 ,Interrupt ID863 Priority/Priority Byte Offset 863 " hexmask.long.byte 0x00 16.--23. 1. " INTID862 ,Interrupt ID862 Priority/Priority Byte Offset 862 " hexmask.long.byte 0x00 8.--15. 1. " INTID861 ,Interrupt ID861 Priority/Priority Byte Offset 861 " hexmask.long.byte 0x00 0.--7. 1. " INTID860 ,Interrupt ID860 Priority/Priority Byte Offset 860 " else rgroup.long 0x740++0x03 line.long 0x00 "GICD_IPRIORITYR208,Interrupt Priority Register 208" rgroup.long 0x744++0x03 line.long 0x00 "GICD_IPRIORITYR209,Interrupt Priority Register 209" rgroup.long 0x748++0x03 line.long 0x00 "GICD_IPRIORITYR210,Interrupt Priority Register 210" rgroup.long 0x74C++0x03 line.long 0x00 "GICD_IPRIORITYR211,Interrupt Priority Register 211" rgroup.long 0x750++0x03 line.long 0x00 "GICD_IPRIORITYR212,Interrupt Priority Register 212" rgroup.long 0x754++0x03 line.long 0x00 "GICD_IPRIORITYR213,Interrupt Priority Register 213" rgroup.long 0x758++0x03 line.long 0x00 "GICD_IPRIORITYR214,Interrupt Priority Register 214" rgroup.long 0x75C++0x03 line.long 0x00 "GICD_IPRIORITYR215,Interrupt Priority Register 215" endif if (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x1B) group.long 0x760++0x03 line.long 0x00 "GICD_IPRIORITYR216,Interrupt Priority Register 216" hexmask.long.byte 0x00 24.--31. 1. " INTID867 ,Interrupt ID867 Priority/Priority Byte Offset 867 " hexmask.long.byte 0x00 16.--23. 1. " INTID866 ,Interrupt ID866 Priority/Priority Byte Offset 866 " hexmask.long.byte 0x00 8.--15. 1. " INTID865 ,Interrupt ID865 Priority/Priority Byte Offset 865 " hexmask.long.byte 0x00 0.--7. 1. " INTID864 ,Interrupt ID864 Priority/Priority Byte Offset 864 " group.long 0x764++0x03 line.long 0x00 "GICD_IPRIORITYR217,Interrupt Priority Register 217" hexmask.long.byte 0x00 24.--31. 1. " INTID871 ,Interrupt ID871 Priority/Priority Byte Offset 871 " hexmask.long.byte 0x00 16.--23. 1. " INTID870 ,Interrupt ID870 Priority/Priority Byte Offset 870 " hexmask.long.byte 0x00 8.--15. 1. " INTID869 ,Interrupt ID869 Priority/Priority Byte Offset 869 " hexmask.long.byte 0x00 0.--7. 1. " INTID868 ,Interrupt ID868 Priority/Priority Byte Offset 868 " group.long 0x768++0x03 line.long 0x00 "GICD_IPRIORITYR218,Interrupt Priority Register 218" hexmask.long.byte 0x00 24.--31. 1. " INTID875 ,Interrupt ID875 Priority/Priority Byte Offset 875 " hexmask.long.byte 0x00 16.--23. 1. " INTID874 ,Interrupt ID874 Priority/Priority Byte Offset 874 " hexmask.long.byte 0x00 8.--15. 1. " INTID873 ,Interrupt ID873 Priority/Priority Byte Offset 873 " hexmask.long.byte 0x00 0.--7. 1. " INTID872 ,Interrupt ID872 Priority/Priority Byte Offset 872 " group.long 0x76C++0x03 line.long 0x00 "GICD_IPRIORITYR219,Interrupt Priority Register 219" hexmask.long.byte 0x00 24.--31. 1. " INTID879 ,Interrupt ID879 Priority/Priority Byte Offset 879 " hexmask.long.byte 0x00 16.--23. 1. " INTID878 ,Interrupt ID878 Priority/Priority Byte Offset 878 " hexmask.long.byte 0x00 8.--15. 1. " INTID877 ,Interrupt ID877 Priority/Priority Byte Offset 877 " hexmask.long.byte 0x00 0.--7. 1. " INTID876 ,Interrupt ID876 Priority/Priority Byte Offset 876 " group.long 0x770++0x03 line.long 0x00 "GICD_IPRIORITYR220,Interrupt Priority Register 220" hexmask.long.byte 0x00 24.--31. 1. " INTID883 ,Interrupt ID883 Priority/Priority Byte Offset 883 " hexmask.long.byte 0x00 16.--23. 1. " INTID882 ,Interrupt ID882 Priority/Priority Byte Offset 882 " hexmask.long.byte 0x00 8.--15. 1. " INTID881 ,Interrupt ID881 Priority/Priority Byte Offset 881 " hexmask.long.byte 0x00 0.--7. 1. " INTID880 ,Interrupt ID880 Priority/Priority Byte Offset 880 " group.long 0x774++0x03 line.long 0x00 "GICD_IPRIORITYR221,Interrupt Priority Register 221" hexmask.long.byte 0x00 24.--31. 1. " INTID887 ,Interrupt ID887 Priority/Priority Byte Offset 887 " hexmask.long.byte 0x00 16.--23. 1. " INTID886 ,Interrupt ID886 Priority/Priority Byte Offset 886 " hexmask.long.byte 0x00 8.--15. 1. " INTID885 ,Interrupt ID885 Priority/Priority Byte Offset 885 " hexmask.long.byte 0x00 0.--7. 1. " INTID884 ,Interrupt ID884 Priority/Priority Byte Offset 884 " group.long 0x778++0x03 line.long 0x00 "GICD_IPRIORITYR222,Interrupt Priority Register 222" hexmask.long.byte 0x00 24.--31. 1. " INTID891 ,Interrupt ID891 Priority/Priority Byte Offset 891 " hexmask.long.byte 0x00 16.--23. 1. " INTID890 ,Interrupt ID890 Priority/Priority Byte Offset 890 " hexmask.long.byte 0x00 8.--15. 1. " INTID889 ,Interrupt ID889 Priority/Priority Byte Offset 889 " hexmask.long.byte 0x00 0.--7. 1. " INTID888 ,Interrupt ID888 Priority/Priority Byte Offset 888 " group.long 0x77C++0x03 line.long 0x00 "GICD_IPRIORITYR223,Interrupt Priority Register 223" hexmask.long.byte 0x00 24.--31. 1. " INTID895 ,Interrupt ID895 Priority/Priority Byte Offset 895 " hexmask.long.byte 0x00 16.--23. 1. " INTID894 ,Interrupt ID894 Priority/Priority Byte Offset 894 " hexmask.long.byte 0x00 8.--15. 1. " INTID893 ,Interrupt ID893 Priority/Priority Byte Offset 893 " hexmask.long.byte 0x00 0.--7. 1. " INTID892 ,Interrupt ID892 Priority/Priority Byte Offset 892 " else rgroup.long 0x760++0x03 line.long 0x00 "GICD_IPRIORITYR216,Interrupt Priority Register 216" rgroup.long 0x764++0x03 line.long 0x00 "GICD_IPRIORITYR217,Interrupt Priority Register 217" rgroup.long 0x768++0x03 line.long 0x00 "GICD_IPRIORITYR218,Interrupt Priority Register 218" rgroup.long 0x76C++0x03 line.long 0x00 "GICD_IPRIORITYR219,Interrupt Priority Register 219" rgroup.long 0x770++0x03 line.long 0x00 "GICD_IPRIORITYR220,Interrupt Priority Register 220" rgroup.long 0x774++0x03 line.long 0x00 "GICD_IPRIORITYR221,Interrupt Priority Register 221" rgroup.long 0x778++0x03 line.long 0x00 "GICD_IPRIORITYR222,Interrupt Priority Register 222" rgroup.long 0x77C++0x03 line.long 0x00 "GICD_IPRIORITYR223,Interrupt Priority Register 223" endif if (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x1C) group.long 0x780++0x03 line.long 0x00 "GICD_IPRIORITYR224,Interrupt Priority Register 224" hexmask.long.byte 0x00 24.--31. 1. " INTID899 ,Interrupt ID899 Priority/Priority Byte Offset 899 " hexmask.long.byte 0x00 16.--23. 1. " INTID898 ,Interrupt ID898 Priority/Priority Byte Offset 898 " hexmask.long.byte 0x00 8.--15. 1. " INTID897 ,Interrupt ID897 Priority/Priority Byte Offset 897 " hexmask.long.byte 0x00 0.--7. 1. " INTID896 ,Interrupt ID896 Priority/Priority Byte Offset 896 " group.long 0x784++0x03 line.long 0x00 "GICD_IPRIORITYR225,Interrupt Priority Register 225" hexmask.long.byte 0x00 24.--31. 1. " INTID903 ,Interrupt ID903 Priority/Priority Byte Offset 903 " hexmask.long.byte 0x00 16.--23. 1. " INTID902 ,Interrupt ID902 Priority/Priority Byte Offset 902 " hexmask.long.byte 0x00 8.--15. 1. " INTID901 ,Interrupt ID901 Priority/Priority Byte Offset 901 " hexmask.long.byte 0x00 0.--7. 1. " INTID900 ,Interrupt ID900 Priority/Priority Byte Offset 900 " group.long 0x788++0x03 line.long 0x00 "GICD_IPRIORITYR226,Interrupt Priority Register 226" hexmask.long.byte 0x00 24.--31. 1. " INTID907 ,Interrupt ID907 Priority/Priority Byte Offset 907 " hexmask.long.byte 0x00 16.--23. 1. " INTID906 ,Interrupt ID906 Priority/Priority Byte Offset 906 " hexmask.long.byte 0x00 8.--15. 1. " INTID905 ,Interrupt ID905 Priority/Priority Byte Offset 905 " hexmask.long.byte 0x00 0.--7. 1. " INTID904 ,Interrupt ID904 Priority/Priority Byte Offset 904 " group.long 0x78C++0x03 line.long 0x00 "GICD_IPRIORITYR227,Interrupt Priority Register 227" hexmask.long.byte 0x00 24.--31. 1. " INTID911 ,Interrupt ID911 Priority/Priority Byte Offset 911 " hexmask.long.byte 0x00 16.--23. 1. " INTID910 ,Interrupt ID910 Priority/Priority Byte Offset 910 " hexmask.long.byte 0x00 8.--15. 1. " INTID909 ,Interrupt ID909 Priority/Priority Byte Offset 909 " hexmask.long.byte 0x00 0.--7. 1. " INTID908 ,Interrupt ID908 Priority/Priority Byte Offset 908 " group.long 0x790++0x03 line.long 0x00 "GICD_IPRIORITYR228,Interrupt Priority Register 228" hexmask.long.byte 0x00 24.--31. 1. " INTID915 ,Interrupt ID915 Priority/Priority Byte Offset 915 " hexmask.long.byte 0x00 16.--23. 1. " INTID914 ,Interrupt ID914 Priority/Priority Byte Offset 914 " hexmask.long.byte 0x00 8.--15. 1. " INTID913 ,Interrupt ID913 Priority/Priority Byte Offset 913 " hexmask.long.byte 0x00 0.--7. 1. " INTID912 ,Interrupt ID912 Priority/Priority Byte Offset 912 " group.long 0x794++0x03 line.long 0x00 "GICD_IPRIORITYR229,Interrupt Priority Register 229" hexmask.long.byte 0x00 24.--31. 1. " INTID919 ,Interrupt ID919 Priority/Priority Byte Offset 919 " hexmask.long.byte 0x00 16.--23. 1. " INTID918 ,Interrupt ID918 Priority/Priority Byte Offset 918 " hexmask.long.byte 0x00 8.--15. 1. " INTID917 ,Interrupt ID917 Priority/Priority Byte Offset 917 " hexmask.long.byte 0x00 0.--7. 1. " INTID916 ,Interrupt ID916 Priority/Priority Byte Offset 916 " group.long 0x798++0x03 line.long 0x00 "GICD_IPRIORITYR230,Interrupt Priority Register 230" hexmask.long.byte 0x00 24.--31. 1. " INTID923 ,Interrupt ID923 Priority/Priority Byte Offset 923 " hexmask.long.byte 0x00 16.--23. 1. " INTID922 ,Interrupt ID922 Priority/Priority Byte Offset 922 " hexmask.long.byte 0x00 8.--15. 1. " INTID921 ,Interrupt ID921 Priority/Priority Byte Offset 921 " hexmask.long.byte 0x00 0.--7. 1. " INTID920 ,Interrupt ID920 Priority/Priority Byte Offset 920 " group.long 0x79C++0x03 line.long 0x00 "GICD_IPRIORITYR231,Interrupt Priority Register 231" hexmask.long.byte 0x00 24.--31. 1. " INTID927 ,Interrupt ID927 Priority/Priority Byte Offset 927 " hexmask.long.byte 0x00 16.--23. 1. " INTID926 ,Interrupt ID926 Priority/Priority Byte Offset 926 " hexmask.long.byte 0x00 8.--15. 1. " INTID925 ,Interrupt ID925 Priority/Priority Byte Offset 925 " hexmask.long.byte 0x00 0.--7. 1. " INTID924 ,Interrupt ID924 Priority/Priority Byte Offset 924 " else rgroup.long 0x780++0x03 line.long 0x00 "GICD_IPRIORITYR224,Interrupt Priority Register 224" rgroup.long 0x784++0x03 line.long 0x00 "GICD_IPRIORITYR225,Interrupt Priority Register 225" rgroup.long 0x788++0x03 line.long 0x00 "GICD_IPRIORITYR226,Interrupt Priority Register 226" rgroup.long 0x78C++0x03 line.long 0x00 "GICD_IPRIORITYR227,Interrupt Priority Register 227" rgroup.long 0x790++0x03 line.long 0x00 "GICD_IPRIORITYR228,Interrupt Priority Register 228" rgroup.long 0x794++0x03 line.long 0x00 "GICD_IPRIORITYR229,Interrupt Priority Register 229" rgroup.long 0x798++0x03 line.long 0x00 "GICD_IPRIORITYR230,Interrupt Priority Register 230" rgroup.long 0x79C++0x03 line.long 0x00 "GICD_IPRIORITYR231,Interrupt Priority Register 231" endif if (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x1D) group.long 0x7A0++0x03 line.long 0x00 "GICD_IPRIORITYR232,Interrupt Priority Register 232" hexmask.long.byte 0x00 24.--31. 1. " INTID931 ,Interrupt ID931 Priority/Priority Byte Offset 931 " hexmask.long.byte 0x00 16.--23. 1. " INTID930 ,Interrupt ID930 Priority/Priority Byte Offset 930 " hexmask.long.byte 0x00 8.--15. 1. " INTID929 ,Interrupt ID929 Priority/Priority Byte Offset 929 " hexmask.long.byte 0x00 0.--7. 1. " INTID928 ,Interrupt ID928 Priority/Priority Byte Offset 928 " group.long 0x7A4++0x03 line.long 0x00 "GICD_IPRIORITYR233,Interrupt Priority Register 233" hexmask.long.byte 0x00 24.--31. 1. " INTID935 ,Interrupt ID935 Priority/Priority Byte Offset 935 " hexmask.long.byte 0x00 16.--23. 1. " INTID934 ,Interrupt ID934 Priority/Priority Byte Offset 934 " hexmask.long.byte 0x00 8.--15. 1. " INTID933 ,Interrupt ID933 Priority/Priority Byte Offset 933 " hexmask.long.byte 0x00 0.--7. 1. " INTID932 ,Interrupt ID932 Priority/Priority Byte Offset 932 " group.long 0x7A8++0x03 line.long 0x00 "GICD_IPRIORITYR234,Interrupt Priority Register 234" hexmask.long.byte 0x00 24.--31. 1. " INTID939 ,Interrupt ID939 Priority/Priority Byte Offset 939 " hexmask.long.byte 0x00 16.--23. 1. " INTID938 ,Interrupt ID938 Priority/Priority Byte Offset 938 " hexmask.long.byte 0x00 8.--15. 1. " INTID937 ,Interrupt ID937 Priority/Priority Byte Offset 937 " hexmask.long.byte 0x00 0.--7. 1. " INTID936 ,Interrupt ID936 Priority/Priority Byte Offset 936 " group.long 0x7AC++0x03 line.long 0x00 "GICD_IPRIORITYR235,Interrupt Priority Register 235" hexmask.long.byte 0x00 24.--31. 1. " INTID943 ,Interrupt ID943 Priority/Priority Byte Offset 943 " hexmask.long.byte 0x00 16.--23. 1. " INTID942 ,Interrupt ID942 Priority/Priority Byte Offset 942 " hexmask.long.byte 0x00 8.--15. 1. " INTID941 ,Interrupt ID941 Priority/Priority Byte Offset 941 " hexmask.long.byte 0x00 0.--7. 1. " INTID940 ,Interrupt ID940 Priority/Priority Byte Offset 940 " group.long 0x7B0++0x03 line.long 0x00 "GICD_IPRIORITYR236,Interrupt Priority Register 236" hexmask.long.byte 0x00 24.--31. 1. " INTID947 ,Interrupt ID947 Priority/Priority Byte Offset 947 " hexmask.long.byte 0x00 16.--23. 1. " INTID946 ,Interrupt ID946 Priority/Priority Byte Offset 946 " hexmask.long.byte 0x00 8.--15. 1. " INTID945 ,Interrupt ID945 Priority/Priority Byte Offset 945 " hexmask.long.byte 0x00 0.--7. 1. " INTID944 ,Interrupt ID944 Priority/Priority Byte Offset 944 " group.long 0x7B4++0x03 line.long 0x00 "GICD_IPRIORITYR237,Interrupt Priority Register 237" hexmask.long.byte 0x00 24.--31. 1. " INTID951 ,Interrupt ID951 Priority/Priority Byte Offset 951 " hexmask.long.byte 0x00 16.--23. 1. " INTID950 ,Interrupt ID950 Priority/Priority Byte Offset 950 " hexmask.long.byte 0x00 8.--15. 1. " INTID949 ,Interrupt ID949 Priority/Priority Byte Offset 949 " hexmask.long.byte 0x00 0.--7. 1. " INTID948 ,Interrupt ID948 Priority/Priority Byte Offset 948 " group.long 0x7B8++0x03 line.long 0x00 "GICD_IPRIORITYR238,Interrupt Priority Register 238" hexmask.long.byte 0x00 24.--31. 1. " INTID955 ,Interrupt ID955 Priority/Priority Byte Offset 955 " hexmask.long.byte 0x00 16.--23. 1. " INTID954 ,Interrupt ID954 Priority/Priority Byte Offset 954 " hexmask.long.byte 0x00 8.--15. 1. " INTID953 ,Interrupt ID953 Priority/Priority Byte Offset 953 " hexmask.long.byte 0x00 0.--7. 1. " INTID952 ,Interrupt ID952 Priority/Priority Byte Offset 952 " group.long 0x7BC++0x03 line.long 0x00 "GICD_IPRIORITYR239,Interrupt Priority Register 239" hexmask.long.byte 0x00 24.--31. 1. " INTID959 ,Interrupt ID959 Priority/Priority Byte Offset 959 " hexmask.long.byte 0x00 16.--23. 1. " INTID958 ,Interrupt ID958 Priority/Priority Byte Offset 958 " hexmask.long.byte 0x00 8.--15. 1. " INTID957 ,Interrupt ID957 Priority/Priority Byte Offset 957 " hexmask.long.byte 0x00 0.--7. 1. " INTID956 ,Interrupt ID956 Priority/Priority Byte Offset 956 " else rgroup.long 0x7A0++0x03 line.long 0x00 "GICD_IPRIORITYR232,Interrupt Priority Register 232" rgroup.long 0x7A4++0x03 line.long 0x00 "GICD_IPRIORITYR233,Interrupt Priority Register 233" rgroup.long 0x7A8++0x03 line.long 0x00 "GICD_IPRIORITYR234,Interrupt Priority Register 234" rgroup.long 0x7AC++0x03 line.long 0x00 "GICD_IPRIORITYR235,Interrupt Priority Register 235" rgroup.long 0x7B0++0x03 line.long 0x00 "GICD_IPRIORITYR236,Interrupt Priority Register 236" rgroup.long 0x7B4++0x03 line.long 0x00 "GICD_IPRIORITYR237,Interrupt Priority Register 237" rgroup.long 0x7B8++0x03 line.long 0x00 "GICD_IPRIORITYR238,Interrupt Priority Register 238" rgroup.long 0x7BC++0x03 line.long 0x00 "GICD_IPRIORITYR239,Interrupt Priority Register 239" endif if (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x1E) group.long 0x7C0++0x03 line.long 0x00 "GICD_IPRIORITYR240,Interrupt Priority Register 240" hexmask.long.byte 0x00 24.--31. 1. " INTID963 ,Interrupt ID963 Priority/Priority Byte Offset 963 " hexmask.long.byte 0x00 16.--23. 1. " INTID962 ,Interrupt ID962 Priority/Priority Byte Offset 962 " hexmask.long.byte 0x00 8.--15. 1. " INTID961 ,Interrupt ID961 Priority/Priority Byte Offset 961 " hexmask.long.byte 0x00 0.--7. 1. " INTID960 ,Interrupt ID960 Priority/Priority Byte Offset 960 " group.long 0x7C4++0x03 line.long 0x00 "GICD_IPRIORITYR241,Interrupt Priority Register 241" hexmask.long.byte 0x00 24.--31. 1. " INTID967 ,Interrupt ID967 Priority/Priority Byte Offset 967 " hexmask.long.byte 0x00 16.--23. 1. " INTID966 ,Interrupt ID966 Priority/Priority Byte Offset 966 " hexmask.long.byte 0x00 8.--15. 1. " INTID965 ,Interrupt ID965 Priority/Priority Byte Offset 965 " hexmask.long.byte 0x00 0.--7. 1. " INTID964 ,Interrupt ID964 Priority/Priority Byte Offset 964 " group.long 0x7C8++0x03 line.long 0x00 "GICD_IPRIORITYR242,Interrupt Priority Register 242" hexmask.long.byte 0x00 24.--31. 1. " INTID971 ,Interrupt ID971 Priority/Priority Byte Offset 971 " hexmask.long.byte 0x00 16.--23. 1. " INTID970 ,Interrupt ID970 Priority/Priority Byte Offset 970 " hexmask.long.byte 0x00 8.--15. 1. " INTID969 ,Interrupt ID969 Priority/Priority Byte Offset 969 " hexmask.long.byte 0x00 0.--7. 1. " INTID968 ,Interrupt ID968 Priority/Priority Byte Offset 968 " group.long 0x7CC++0x03 line.long 0x00 "GICD_IPRIORITYR243,Interrupt Priority Register 243" hexmask.long.byte 0x00 24.--31. 1. " INTID975 ,Interrupt ID975 Priority/Priority Byte Offset 975 " hexmask.long.byte 0x00 16.--23. 1. " INTID974 ,Interrupt ID974 Priority/Priority Byte Offset 974 " hexmask.long.byte 0x00 8.--15. 1. " INTID973 ,Interrupt ID973 Priority/Priority Byte Offset 973 " hexmask.long.byte 0x00 0.--7. 1. " INTID972 ,Interrupt ID972 Priority/Priority Byte Offset 972 " group.long 0x7D0++0x03 line.long 0x00 "GICD_IPRIORITYR244,Interrupt Priority Register 244" hexmask.long.byte 0x00 24.--31. 1. " INTID979 ,Interrupt ID979 Priority/Priority Byte Offset 979 " hexmask.long.byte 0x00 16.--23. 1. " INTID978 ,Interrupt ID978 Priority/Priority Byte Offset 978 " hexmask.long.byte 0x00 8.--15. 1. " INTID977 ,Interrupt ID977 Priority/Priority Byte Offset 977 " hexmask.long.byte 0x00 0.--7. 1. " INTID976 ,Interrupt ID976 Priority/Priority Byte Offset 976 " group.long 0x7D4++0x03 line.long 0x00 "GICD_IPRIORITYR245,Interrupt Priority Register 245" hexmask.long.byte 0x00 24.--31. 1. " INTID983 ,Interrupt ID983 Priority/Priority Byte Offset 983 " hexmask.long.byte 0x00 16.--23. 1. " INTID982 ,Interrupt ID982 Priority/Priority Byte Offset 982 " hexmask.long.byte 0x00 8.--15. 1. " INTID981 ,Interrupt ID981 Priority/Priority Byte Offset 981 " hexmask.long.byte 0x00 0.--7. 1. " INTID980 ,Interrupt ID980 Priority/Priority Byte Offset 980 " group.long 0x7D8++0x03 line.long 0x00 "GICD_IPRIORITYR246,Interrupt Priority Register 246" hexmask.long.byte 0x00 24.--31. 1. " INTID987 ,Interrupt ID987 Priority/Priority Byte Offset 987 " hexmask.long.byte 0x00 16.--23. 1. " INTID986 ,Interrupt ID986 Priority/Priority Byte Offset 986 " hexmask.long.byte 0x00 8.--15. 1. " INTID985 ,Interrupt ID985 Priority/Priority Byte Offset 985 " hexmask.long.byte 0x00 0.--7. 1. " INTID984 ,Interrupt ID984 Priority/Priority Byte Offset 984 " group.long 0x7DC++0x03 line.long 0x00 "GICD_IPRIORITYR247,Interrupt Priority Register 247" hexmask.long.byte 0x00 24.--31. 1. " INTID991 ,Interrupt ID991 Priority/Priority Byte Offset 991 " hexmask.long.byte 0x00 16.--23. 1. " INTID990 ,Interrupt ID990 Priority/Priority Byte Offset 990 " hexmask.long.byte 0x00 8.--15. 1. " INTID989 ,Interrupt ID989 Priority/Priority Byte Offset 989 " hexmask.long.byte 0x00 0.--7. 1. " INTID988 ,Interrupt ID988 Priority/Priority Byte Offset 988 " else rgroup.long 0x7C0++0x03 line.long 0x00 "GICD_IPRIORITYR240,Interrupt Priority Register 240" rgroup.long 0x7C4++0x03 line.long 0x00 "GICD_IPRIORITYR241,Interrupt Priority Register 241" rgroup.long 0x7C8++0x03 line.long 0x00 "GICD_IPRIORITYR242,Interrupt Priority Register 242" rgroup.long 0x7CC++0x03 line.long 0x00 "GICD_IPRIORITYR243,Interrupt Priority Register 243" rgroup.long 0x7D0++0x03 line.long 0x00 "GICD_IPRIORITYR244,Interrupt Priority Register 244" rgroup.long 0x7D4++0x03 line.long 0x00 "GICD_IPRIORITYR245,Interrupt Priority Register 245" rgroup.long 0x7D8++0x03 line.long 0x00 "GICD_IPRIORITYR246,Interrupt Priority Register 246" rgroup.long 0x7DC++0x03 line.long 0x00 "GICD_IPRIORITYR247,Interrupt Priority Register 247" endif if (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x1F) group.long 0x7E0++0x03 line.long 0x00 "GICD_IPRIORITYR248,Interrupt Priority Register 248" hexmask.long.byte 0x00 24.--31. 1. " INTID995 ,Interrupt ID995 Priority/Priority Byte Offset 995 " hexmask.long.byte 0x00 16.--23. 1. " INTID994 ,Interrupt ID994 Priority/Priority Byte Offset 994 " hexmask.long.byte 0x00 8.--15. 1. " INTID993 ,Interrupt ID993 Priority/Priority Byte Offset 993 " hexmask.long.byte 0x00 0.--7. 1. " INTID992 ,Interrupt ID992 Priority/Priority Byte Offset 992 " group.long 0x7E4++0x03 line.long 0x00 "GICD_IPRIORITYR249,Interrupt Priority Register 249" hexmask.long.byte 0x00 24.--31. 1. " INTID999 ,Interrupt ID999 Priority/Priority Byte Offset 999 " hexmask.long.byte 0x00 16.--23. 1. " INTID998 ,Interrupt ID998 Priority/Priority Byte Offset 998 " hexmask.long.byte 0x00 8.--15. 1. " INTID997 ,Interrupt ID997 Priority/Priority Byte Offset 997 " hexmask.long.byte 0x00 0.--7. 1. " INTID996 ,Interrupt ID996 Priority/Priority Byte Offset 996 " group.long 0x7E8++0x03 line.long 0x00 "GICD_IPRIORITYR250,Interrupt Priority Register 250" hexmask.long.byte 0x00 24.--31. 1. " INTID1003 ,Interrupt ID1003 Priority/Priority Byte Offset 1003" hexmask.long.byte 0x00 16.--23. 1. " INTID1002 ,Interrupt ID1002 Priority/Priority Byte Offset 1002" hexmask.long.byte 0x00 8.--15. 1. " INTID1001 ,Interrupt ID1001 Priority/Priority Byte Offset 1001" hexmask.long.byte 0x00 0.--7. 1. " INTID1000 ,Interrupt ID1000 Priority/Priority Byte Offset 1000" group.long 0x7EC++0x03 line.long 0x00 "GICD_IPRIORITYR251,Interrupt Priority Register 251" hexmask.long.byte 0x00 24.--31. 1. " INTID1007 ,Interrupt ID1007 Priority/Priority Byte Offset 1007" hexmask.long.byte 0x00 16.--23. 1. " INTID1006 ,Interrupt ID1006 Priority/Priority Byte Offset 1006" hexmask.long.byte 0x00 8.--15. 1. " INTID1005 ,Interrupt ID1005 Priority/Priority Byte Offset 1005" hexmask.long.byte 0x00 0.--7. 1. " INTID1004 ,Interrupt ID1004 Priority/Priority Byte Offset 1004" group.long 0x7F0++0x03 line.long 0x00 "GICD_IPRIORITYR252,Interrupt Priority Register 252" hexmask.long.byte 0x00 24.--31. 1. " INTID1011 ,Interrupt ID1011 Priority/Priority Byte Offset 1011" hexmask.long.byte 0x00 16.--23. 1. " INTID1010 ,Interrupt ID1010 Priority/Priority Byte Offset 1010" hexmask.long.byte 0x00 8.--15. 1. " INTID1009 ,Interrupt ID1009 Priority/Priority Byte Offset 1009" hexmask.long.byte 0x00 0.--7. 1. " INTID1008 ,Interrupt ID1008 Priority/Priority Byte Offset 1008" group.long 0x7F4++0x03 line.long 0x00 "GICD_IPRIORITYR253,Interrupt Priority Register 253" hexmask.long.byte 0x00 24.--31. 1. " INTID1015 ,Interrupt ID1015 Priority/Priority Byte Offset 1015" hexmask.long.byte 0x00 16.--23. 1. " INTID1014 ,Interrupt ID1014 Priority/Priority Byte Offset 1014" hexmask.long.byte 0x00 8.--15. 1. " INTID1013 ,Interrupt ID1013 Priority/Priority Byte Offset 1013" hexmask.long.byte 0x00 0.--7. 1. " INTID1012 ,Interrupt ID1012 Priority/Priority Byte Offset 1012" group.long 0x7F8++0x03 line.long 0x00 "GICD_IPRIORITYR254,Interrupt Priority Register 254" hexmask.long.byte 0x00 24.--31. 1. " INTID1019 ,Interrupt ID1019 Priority/Priority Byte Offset 1019" hexmask.long.byte 0x00 16.--23. 1. " INTID1018 ,Interrupt ID1018 Priority/Priority Byte Offset 1018" hexmask.long.byte 0x00 8.--15. 1. " INTID1017 ,Interrupt ID1017 Priority/Priority Byte Offset 1017" hexmask.long.byte 0x00 0.--7. 1. " INTID1016 ,Interrupt ID1016 Priority/Priority Byte Offset 1016" else rgroup.long 0x7E0++0x03 line.long 0x00 "GICD_IPRIORITYR248,Interrupt Priority Register 248" rgroup.long 0x7E4++0x03 line.long 0x00 "GICD_IPRIORITYR249,Interrupt Priority Register 249" rgroup.long 0x7E8++0x03 line.long 0x00 "GICD_IPRIORITYR250,Interrupt Priority Register 250" rgroup.long 0x7EC++0x03 line.long 0x00 "GICD_IPRIORITYR251,Interrupt Priority Register 251" rgroup.long 0x7F0++0x03 line.long 0x00 "GICD_IPRIORITYR252,Interrupt Priority Register 252" rgroup.long 0x7F4++0x03 line.long 0x00 "GICD_IPRIORITYR253,Interrupt Priority Register 253" rgroup.long 0x7F8++0x03 line.long 0x00 "GICD_IPRIORITYR254,Interrupt Priority Register 254" endif tree.end width 19. tree "Processor Targets Registers" if (((per.l(ad:0xA0021000+0x04))&0x000000E0)>0x1) rgroup.long 0x800++0x03 line.long 0x00 "GICD_ITARGETSR0,Interrupt Processor Targets Register 0" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO3 ,CPU Targets Byte Offset 3 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO2 ,CPU Targets Byte Offset 2 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1 ,CPU Targets Byte Offset 1 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO0 ,CPU Targets Byte Offset 0 " rgroup.long 0x804++0x03 line.long 0x00 "GICD_ITARGETSR1,Interrupt Processor Targets Register 1" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO7 ,CPU Targets Byte Offset 7 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO6 ,CPU Targets Byte Offset 6 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO5 ,CPU Targets Byte Offset 5 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO4 ,CPU Targets Byte Offset 4 " rgroup.long 0x808++0x03 line.long 0x00 "GICD_ITARGETSR2,Interrupt Processor Targets Register 2" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO11 ,CPU Targets Byte Offset 11 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO10 ,CPU Targets Byte Offset 10 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO9 ,CPU Targets Byte Offset 9 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO8 ,CPU Targets Byte Offset 8 " rgroup.long 0x80C++0x03 line.long 0x00 "GICD_ITARGETSR3,Interrupt Processor Targets Register 3" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO15 ,CPU Targets Byte Offset 15 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO14 ,CPU Targets Byte Offset 14 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO13 ,CPU Targets Byte Offset 13 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO12 ,CPU Targets Byte Offset 12 " rgroup.long 0x810++0x03 line.long 0x00 "GICD_ITARGETSR4,Interrupt Processor Targets Register 4" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO19 ,CPU Targets Byte Offset 19 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO18 ,CPU Targets Byte Offset 18 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO17 ,CPU Targets Byte Offset 17 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO16 ,CPU Targets Byte Offset 16 " rgroup.long 0x814++0x03 line.long 0x00 "GICD_ITARGETSR5,Interrupt Processor Targets Register 5" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO23 ,CPU Targets Byte Offset 23 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO22 ,CPU Targets Byte Offset 22 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO21 ,CPU Targets Byte Offset 21 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO20 ,CPU Targets Byte Offset 20 " rgroup.long 0x818++0x03 line.long 0x00 "GICD_ITARGETSR6,Interrupt Processor Targets Register 6" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO27 ,CPU Targets Byte Offset 27 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO26 ,CPU Targets Byte Offset 26 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO25 ,CPU Targets Byte Offset 25 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO24 ,CPU Targets Byte Offset 24 " rgroup.long 0x81C++0x03 line.long 0x00 "GICD_ITARGETSR7,Interrupt Processor Targets Register 7" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO31 ,CPU Targets Byte Offset 31 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO30 ,CPU Targets Byte Offset 30 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO29 ,CPU Targets Byte Offset 29 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO28 ,CPU Targets Byte Offset 28 " if (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x01) group.long 0x820++0x03 line.long 0x00 "GICD_ITARGETSR8,Interrupt Processor Targets Register 8" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO35 ,CPU Targets Byte Offset 35 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO34 ,CPU Targets Byte Offset 34 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO33 ,CPU Targets Byte Offset 33 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO32 ,CPU Targets Byte Offset 32 " group.long 0x824++0x03 line.long 0x00 "GICD_ITARGETSR9,Interrupt Processor Targets Register 9" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO39 ,CPU Targets Byte Offset 39 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO38 ,CPU Targets Byte Offset 38 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO37 ,CPU Targets Byte Offset 37 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO36 ,CPU Targets Byte Offset 36 " group.long 0x828++0x03 line.long 0x00 "GICD_ITARGETSR10,Interrupt Processor Targets Register 10" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO43 ,CPU Targets Byte Offset 43 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO42 ,CPU Targets Byte Offset 42 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO41 ,CPU Targets Byte Offset 41 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO40 ,CPU Targets Byte Offset 40 " group.long 0x82C++0x03 line.long 0x00 "GICD_ITARGETSR11,Interrupt Processor Targets Register 11" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO47 ,CPU Targets Byte Offset 47 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO46 ,CPU Targets Byte Offset 46 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO45 ,CPU Targets Byte Offset 45 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO44 ,CPU Targets Byte Offset 44 " group.long 0x830++0x03 line.long 0x00 "GICD_ITARGETSR12,Interrupt Processor Targets Register 12" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO51 ,CPU Targets Byte Offset 51 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO50 ,CPU Targets Byte Offset 50 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO49 ,CPU Targets Byte Offset 49 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO48 ,CPU Targets Byte Offset 48 " group.long 0x834++0x03 line.long 0x00 "GICD_ITARGETSR13,Interrupt Processor Targets Register 13" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO55 ,CPU Targets Byte Offset 55 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO54 ,CPU Targets Byte Offset 54 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO53 ,CPU Targets Byte Offset 53 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO52 ,CPU Targets Byte Offset 52 " group.long 0x838++0x03 line.long 0x00 "GICD_ITARGETSR14,Interrupt Processor Targets Register 14" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO59 ,CPU Targets Byte Offset 59 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO58 ,CPU Targets Byte Offset 58 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO57 ,CPU Targets Byte Offset 57 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO56 ,CPU Targets Byte Offset 56 " group.long 0x83C++0x03 line.long 0x00 "GICD_ITARGETSR15,Interrupt Processor Targets Register 15" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO63 ,CPU Targets Byte Offset 63 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO62 ,CPU Targets Byte Offset 62 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO61 ,CPU Targets Byte Offset 61 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO60 ,CPU Targets Byte Offset 60 " else rgroup.long 0x820++0x03 line.long 0x00 "GICD_ITARGETSR8,Interrupt Processor Targets Register 8" rgroup.long 0x824++0x03 line.long 0x00 "GICD_ITARGETSR9,Interrupt Processor Targets Register 9" rgroup.long 0x828++0x03 line.long 0x00 "GICD_ITARGETSR10,Interrupt Processor Targets Register 10" rgroup.long 0x82C++0x03 line.long 0x00 "GICD_ITARGETSR11,Interrupt Processor Targets Register 11" rgroup.long 0x830++0x03 line.long 0x00 "GICD_ITARGETSR12,Interrupt Processor Targets Register 12" rgroup.long 0x834++0x03 line.long 0x00 "GICD_ITARGETSR13,Interrupt Processor Targets Register 13" rgroup.long 0x838++0x03 line.long 0x00 "GICD_ITARGETSR14,Interrupt Processor Targets Register 14" rgroup.long 0x83C++0x03 line.long 0x00 "GICD_ITARGETSR15,Interrupt Processor Targets Register 15" endif if (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x02) group.long 0x840++0x03 line.long 0x00 "GICD_ITARGETSR16,Interrupt Processor Targets Register 16" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO67 ,CPU Targets Byte Offset 67 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO66 ,CPU Targets Byte Offset 66 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO65 ,CPU Targets Byte Offset 65 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO64 ,CPU Targets Byte Offset 64 " group.long 0x844++0x03 line.long 0x00 "GICD_ITARGETSR17,Interrupt Processor Targets Register 17" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO71 ,CPU Targets Byte Offset 71 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO70 ,CPU Targets Byte Offset 70 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO69 ,CPU Targets Byte Offset 69 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO68 ,CPU Targets Byte Offset 68 " group.long 0x848++0x03 line.long 0x00 "GICD_ITARGETSR18,Interrupt Processor Targets Register 18" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO75 ,CPU Targets Byte Offset 75 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO74 ,CPU Targets Byte Offset 74 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO73 ,CPU Targets Byte Offset 73 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO72 ,CPU Targets Byte Offset 72 " group.long 0x84C++0x03 line.long 0x00 "GICD_ITARGETSR19,Interrupt Processor Targets Register 19" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO79 ,CPU Targets Byte Offset 79 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO78 ,CPU Targets Byte Offset 78 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO77 ,CPU Targets Byte Offset 77 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO76 ,CPU Targets Byte Offset 76 " group.long 0x850++0x03 line.long 0x00 "GICD_ITARGETSR20,Interrupt Processor Targets Register 20" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO83 ,CPU Targets Byte Offset 83 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO82 ,CPU Targets Byte Offset 82 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO81 ,CPU Targets Byte Offset 81 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO80 ,CPU Targets Byte Offset 80 " group.long 0x854++0x03 line.long 0x00 "GICD_ITARGETSR21,Interrupt Processor Targets Register 21" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO87 ,CPU Targets Byte Offset 87 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO86 ,CPU Targets Byte Offset 86 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO85 ,CPU Targets Byte Offset 85 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO84 ,CPU Targets Byte Offset 84 " group.long 0x858++0x03 line.long 0x00 "GICD_ITARGETSR22,Interrupt Processor Targets Register 22" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO91 ,CPU Targets Byte Offset 91 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO90 ,CPU Targets Byte Offset 90 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO89 ,CPU Targets Byte Offset 89 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO88 ,CPU Targets Byte Offset 88 " group.long 0x85C++0x03 line.long 0x00 "GICD_ITARGETSR23,Interrupt Processor Targets Register 23" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO95 ,CPU Targets Byte Offset 95 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO94 ,CPU Targets Byte Offset 94 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO93 ,CPU Targets Byte Offset 93 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO92 ,CPU Targets Byte Offset 92 " else rgroup.long 0x840++0x03 line.long 0x00 "GICD_ITARGETSR16,Interrupt Processor Targets Register 16" rgroup.long 0x844++0x03 line.long 0x00 "GICD_ITARGETSR17,Interrupt Processor Targets Register 17" rgroup.long 0x848++0x03 line.long 0x00 "GICD_ITARGETSR18,Interrupt Processor Targets Register 18" rgroup.long 0x84C++0x03 line.long 0x00 "GICD_ITARGETSR19,Interrupt Processor Targets Register 19" rgroup.long 0x850++0x03 line.long 0x00 "GICD_ITARGETSR20,Interrupt Processor Targets Register 20" rgroup.long 0x854++0x03 line.long 0x00 "GICD_ITARGETSR21,Interrupt Processor Targets Register 21" rgroup.long 0x858++0x03 line.long 0x00 "GICD_ITARGETSR22,Interrupt Processor Targets Register 22" rgroup.long 0x85C++0x03 line.long 0x00 "GICD_ITARGETSR23,Interrupt Processor Targets Register 23" endif if (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x03) group.long 0x860++0x03 line.long 0x00 "GICD_ITARGETSR24,Interrupt Processor Targets Register 24" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO99 ,CPU Targets Byte Offset 99 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO98 ,CPU Targets Byte Offset 98 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO97 ,CPU Targets Byte Offset 97 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO96 ,CPU Targets Byte Offset 96 " group.long 0x864++0x03 line.long 0x00 "GICD_ITARGETSR25,Interrupt Processor Targets Register 25" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO103 ,CPU Targets Byte Offset 103 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO102 ,CPU Targets Byte Offset 102 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO101 ,CPU Targets Byte Offset 101 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO100 ,CPU Targets Byte Offset 100 " group.long 0x868++0x03 line.long 0x00 "GICD_ITARGETSR26,Interrupt Processor Targets Register 26" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO107 ,CPU Targets Byte Offset 107 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO106 ,CPU Targets Byte Offset 106 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO105 ,CPU Targets Byte Offset 105 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO104 ,CPU Targets Byte Offset 104 " group.long 0x86C++0x03 line.long 0x00 "GICD_ITARGETSR27,Interrupt Processor Targets Register 27" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO111 ,CPU Targets Byte Offset 111 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO110 ,CPU Targets Byte Offset 110 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO109 ,CPU Targets Byte Offset 109 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO108 ,CPU Targets Byte Offset 108 " group.long 0x870++0x03 line.long 0x00 "GICD_ITARGETSR28,Interrupt Processor Targets Register 28" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO115 ,CPU Targets Byte Offset 115 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO114 ,CPU Targets Byte Offset 114 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO113 ,CPU Targets Byte Offset 113 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO112 ,CPU Targets Byte Offset 112 " group.long 0x874++0x03 line.long 0x00 "GICD_ITARGETSR29,Interrupt Processor Targets Register 29" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO119 ,CPU Targets Byte Offset 119 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO118 ,CPU Targets Byte Offset 118 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO117 ,CPU Targets Byte Offset 117 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO116 ,CPU Targets Byte Offset 116 " group.long 0x878++0x03 line.long 0x00 "GICD_ITARGETSR30,Interrupt Processor Targets Register 30" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO123 ,CPU Targets Byte Offset 123 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO122 ,CPU Targets Byte Offset 122 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO121 ,CPU Targets Byte Offset 121 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO120 ,CPU Targets Byte Offset 120 " group.long 0x87C++0x03 line.long 0x00 "GICD_ITARGETSR31,Interrupt Processor Targets Register 31" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO127 ,CPU Targets Byte Offset 127 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO126 ,CPU Targets Byte Offset 126 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO125 ,CPU Targets Byte Offset 125 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO124 ,CPU Targets Byte Offset 124 " else rgroup.long 0x860++0x03 line.long 0x00 "GICD_ITARGETSR24,Interrupt Processor Targets Register 24" rgroup.long 0x864++0x03 line.long 0x00 "GICD_ITARGETSR25,Interrupt Processor Targets Register 25" rgroup.long 0x868++0x03 line.long 0x00 "GICD_ITARGETSR26,Interrupt Processor Targets Register 26" rgroup.long 0x86C++0x03 line.long 0x00 "GICD_ITARGETSR27,Interrupt Processor Targets Register 27" rgroup.long 0x870++0x03 line.long 0x00 "GICD_ITARGETSR28,Interrupt Processor Targets Register 28" rgroup.long 0x874++0x03 line.long 0x00 "GICD_ITARGETSR29,Interrupt Processor Targets Register 29" rgroup.long 0x878++0x03 line.long 0x00 "GICD_ITARGETSR30,Interrupt Processor Targets Register 30" rgroup.long 0x87C++0x03 line.long 0x00 "GICD_ITARGETSR31,Interrupt Processor Targets Register 31" endif if (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x04) group.long 0x880++0x03 line.long 0x00 "GICD_ITARGETSR32,Interrupt Processor Targets Register 32" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO131 ,CPU Targets Byte Offset 131 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO130 ,CPU Targets Byte Offset 130 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO129 ,CPU Targets Byte Offset 129 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO128 ,CPU Targets Byte Offset 128 " group.long 0x884++0x03 line.long 0x00 "GICD_ITARGETSR33,Interrupt Processor Targets Register 33" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO135 ,CPU Targets Byte Offset 135 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO134 ,CPU Targets Byte Offset 134 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO133 ,CPU Targets Byte Offset 133 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO132 ,CPU Targets Byte Offset 132 " group.long 0x888++0x03 line.long 0x00 "GICD_ITARGETSR34,Interrupt Processor Targets Register 34" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO139 ,CPU Targets Byte Offset 139 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO138 ,CPU Targets Byte Offset 138 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO137 ,CPU Targets Byte Offset 137 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO136 ,CPU Targets Byte Offset 136 " group.long 0x88C++0x03 line.long 0x00 "GICD_ITARGETSR35,Interrupt Processor Targets Register 35" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO143 ,CPU Targets Byte Offset 143 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO142 ,CPU Targets Byte Offset 142 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO141 ,CPU Targets Byte Offset 141 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO140 ,CPU Targets Byte Offset 140 " group.long 0x890++0x03 line.long 0x00 "GICD_ITARGETSR36,Interrupt Processor Targets Register 36" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO147 ,CPU Targets Byte Offset 147 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO146 ,CPU Targets Byte Offset 146 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO145 ,CPU Targets Byte Offset 145 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO144 ,CPU Targets Byte Offset 144 " group.long 0x894++0x03 line.long 0x00 "GICD_ITARGETSR37,Interrupt Processor Targets Register 37" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO151 ,CPU Targets Byte Offset 151 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO150 ,CPU Targets Byte Offset 150 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO149 ,CPU Targets Byte Offset 149 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO148 ,CPU Targets Byte Offset 148 " group.long 0x898++0x03 line.long 0x00 "GICD_ITARGETSR38,Interrupt Processor Targets Register 38" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO155 ,CPU Targets Byte Offset 155 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO154 ,CPU Targets Byte Offset 154 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO153 ,CPU Targets Byte Offset 153 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO152 ,CPU Targets Byte Offset 152 " group.long 0x89C++0x03 line.long 0x00 "GICD_ITARGETSR39,Interrupt Processor Targets Register 39" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO159 ,CPU Targets Byte Offset 159 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO158 ,CPU Targets Byte Offset 158 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO157 ,CPU Targets Byte Offset 157 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO156 ,CPU Targets Byte Offset 156 " else rgroup.long 0x880++0x03 line.long 0x00 "GICD_ITARGETSR32,Interrupt Processor Targets Register 32" rgroup.long 0x884++0x03 line.long 0x00 "GICD_ITARGETSR33,Interrupt Processor Targets Register 33" rgroup.long 0x888++0x03 line.long 0x00 "GICD_ITARGETSR34,Interrupt Processor Targets Register 34" rgroup.long 0x88C++0x03 line.long 0x00 "GICD_ITARGETSR35,Interrupt Processor Targets Register 35" rgroup.long 0x890++0x03 line.long 0x00 "GICD_ITARGETSR36,Interrupt Processor Targets Register 36" rgroup.long 0x894++0x03 line.long 0x00 "GICD_ITARGETSR37,Interrupt Processor Targets Register 37" rgroup.long 0x898++0x03 line.long 0x00 "GICD_ITARGETSR38,Interrupt Processor Targets Register 38" rgroup.long 0x89C++0x03 line.long 0x00 "GICD_ITARGETSR39,Interrupt Processor Targets Register 39" endif if (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x05) group.long 0x8A0++0x03 line.long 0x00 "GICD_ITARGETSR40,Interrupt Processor Targets Register 40" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO163 ,CPU Targets Byte Offset 163 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO162 ,CPU Targets Byte Offset 162 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO161 ,CPU Targets Byte Offset 161 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO160 ,CPU Targets Byte Offset 160 " group.long 0x8A4++0x03 line.long 0x00 "GICD_ITARGETSR41,Interrupt Processor Targets Register 41" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO167 ,CPU Targets Byte Offset 167 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO166 ,CPU Targets Byte Offset 166 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO165 ,CPU Targets Byte Offset 165 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO164 ,CPU Targets Byte Offset 164 " group.long 0x8A8++0x03 line.long 0x00 "GICD_ITARGETSR42,Interrupt Processor Targets Register 42" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO171 ,CPU Targets Byte Offset 171 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO170 ,CPU Targets Byte Offset 170 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO169 ,CPU Targets Byte Offset 169 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO168 ,CPU Targets Byte Offset 168 " group.long 0x8AC++0x03 line.long 0x00 "GICD_ITARGETSR43,Interrupt Processor Targets Register 43" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO175 ,CPU Targets Byte Offset 175 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO174 ,CPU Targets Byte Offset 174 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO173 ,CPU Targets Byte Offset 173 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO172 ,CPU Targets Byte Offset 172 " group.long 0x8B0++0x03 line.long 0x00 "GICD_ITARGETSR44,Interrupt Processor Targets Register 44" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO179 ,CPU Targets Byte Offset 179 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO178 ,CPU Targets Byte Offset 178 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO177 ,CPU Targets Byte Offset 177 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO176 ,CPU Targets Byte Offset 176 " group.long 0x8B4++0x03 line.long 0x00 "GICD_ITARGETSR45,Interrupt Processor Targets Register 45" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO183 ,CPU Targets Byte Offset 183 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO182 ,CPU Targets Byte Offset 182 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO181 ,CPU Targets Byte Offset 181 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO180 ,CPU Targets Byte Offset 180 " group.long 0x8B8++0x03 line.long 0x00 "GICD_ITARGETSR46,Interrupt Processor Targets Register 46" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO187 ,CPU Targets Byte Offset 187 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO186 ,CPU Targets Byte Offset 186 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO185 ,CPU Targets Byte Offset 185 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO184 ,CPU Targets Byte Offset 184 " group.long 0x8BC++0x03 line.long 0x00 "GICD_ITARGETSR47,Interrupt Processor Targets Register 47" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO191 ,CPU Targets Byte Offset 191 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO190 ,CPU Targets Byte Offset 190 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO189 ,CPU Targets Byte Offset 189 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO188 ,CPU Targets Byte Offset 188 " else rgroup.long 0x8A0++0x03 line.long 0x00 "GICD_ITARGETSR40,Interrupt Processor Targets Register 40" rgroup.long 0x8A4++0x03 line.long 0x00 "GICD_ITARGETSR41,Interrupt Processor Targets Register 41" rgroup.long 0x8A8++0x03 line.long 0x00 "GICD_ITARGETSR42,Interrupt Processor Targets Register 42" rgroup.long 0x8AC++0x03 line.long 0x00 "GICD_ITARGETSR43,Interrupt Processor Targets Register 43" rgroup.long 0x8B0++0x03 line.long 0x00 "GICD_ITARGETSR44,Interrupt Processor Targets Register 44" rgroup.long 0x8B4++0x03 line.long 0x00 "GICD_ITARGETSR45,Interrupt Processor Targets Register 45" rgroup.long 0x8B8++0x03 line.long 0x00 "GICD_ITARGETSR46,Interrupt Processor Targets Register 46" rgroup.long 0x8BC++0x03 line.long 0x00 "GICD_ITARGETSR47,Interrupt Processor Targets Register 47" endif if (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x06) group.long 0x8C0++0x03 line.long 0x00 "GICD_ITARGETSR48,Interrupt Processor Targets Register 48" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO195 ,CPU Targets Byte Offset 195 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO194 ,CPU Targets Byte Offset 194 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO193 ,CPU Targets Byte Offset 193 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO192 ,CPU Targets Byte Offset 192 " group.long 0x8C4++0x03 line.long 0x00 "GICD_ITARGETSR49,Interrupt Processor Targets Register 49" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO199 ,CPU Targets Byte Offset 199 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO198 ,CPU Targets Byte Offset 198 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO197 ,CPU Targets Byte Offset 197 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO196 ,CPU Targets Byte Offset 196 " group.long 0x8C8++0x03 line.long 0x00 "GICD_ITARGETSR50,Interrupt Processor Targets Register 50" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO203 ,CPU Targets Byte Offset 203 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO202 ,CPU Targets Byte Offset 202 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO201 ,CPU Targets Byte Offset 201 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO200 ,CPU Targets Byte Offset 200 " group.long 0x8CC++0x03 line.long 0x00 "GICD_ITARGETSR51,Interrupt Processor Targets Register 51" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO207 ,CPU Targets Byte Offset 207 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO206 ,CPU Targets Byte Offset 206 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO205 ,CPU Targets Byte Offset 205 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO204 ,CPU Targets Byte Offset 204 " group.long 0x8D0++0x03 line.long 0x00 "GICD_ITARGETSR52,Interrupt Processor Targets Register 52" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO211 ,CPU Targets Byte Offset 211 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO210 ,CPU Targets Byte Offset 210 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO209 ,CPU Targets Byte Offset 209 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO208 ,CPU Targets Byte Offset 208 " group.long 0x8D4++0x03 line.long 0x00 "GICD_ITARGETSR53,Interrupt Processor Targets Register 53" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO215 ,CPU Targets Byte Offset 215 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO214 ,CPU Targets Byte Offset 214 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO213 ,CPU Targets Byte Offset 213 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO212 ,CPU Targets Byte Offset 212 " group.long 0x8D8++0x03 line.long 0x00 "GICD_ITARGETSR54,Interrupt Processor Targets Register 54" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO219 ,CPU Targets Byte Offset 219 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO218 ,CPU Targets Byte Offset 218 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO217 ,CPU Targets Byte Offset 217 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO216 ,CPU Targets Byte Offset 216 " group.long 0x8DC++0x03 line.long 0x00 "GICD_ITARGETSR55,Interrupt Processor Targets Register 55" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO223 ,CPU Targets Byte Offset 223 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO222 ,CPU Targets Byte Offset 222 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO221 ,CPU Targets Byte Offset 221 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO220 ,CPU Targets Byte Offset 220 " else rgroup.long 0x8C0++0x03 line.long 0x00 "GICD_ITARGETSR48,Interrupt Processor Targets Register 48" rgroup.long 0x8C4++0x03 line.long 0x00 "GICD_ITARGETSR49,Interrupt Processor Targets Register 49" rgroup.long 0x8C8++0x03 line.long 0x00 "GICD_ITARGETSR50,Interrupt Processor Targets Register 50" rgroup.long 0x8CC++0x03 line.long 0x00 "GICD_ITARGETSR51,Interrupt Processor Targets Register 51" rgroup.long 0x8D0++0x03 line.long 0x00 "GICD_ITARGETSR52,Interrupt Processor Targets Register 52" rgroup.long 0x8D4++0x03 line.long 0x00 "GICD_ITARGETSR53,Interrupt Processor Targets Register 53" rgroup.long 0x8D8++0x03 line.long 0x00 "GICD_ITARGETSR54,Interrupt Processor Targets Register 54" rgroup.long 0x8DC++0x03 line.long 0x00 "GICD_ITARGETSR55,Interrupt Processor Targets Register 55" endif if (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x07) group.long 0x8E0++0x03 line.long 0x00 "GICD_ITARGETSR56,Interrupt Processor Targets Register 56" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO227 ,CPU Targets Byte Offset 227 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO226 ,CPU Targets Byte Offset 226 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO225 ,CPU Targets Byte Offset 225 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO224 ,CPU Targets Byte Offset 224 " group.long 0x8E4++0x03 line.long 0x00 "GICD_ITARGETSR57,Interrupt Processor Targets Register 57" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO231 ,CPU Targets Byte Offset 231 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO230 ,CPU Targets Byte Offset 230 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO229 ,CPU Targets Byte Offset 229 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO228 ,CPU Targets Byte Offset 228 " group.long 0x8E8++0x03 line.long 0x00 "GICD_ITARGETSR58,Interrupt Processor Targets Register 58" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO235 ,CPU Targets Byte Offset 235 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO234 ,CPU Targets Byte Offset 234 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO233 ,CPU Targets Byte Offset 233 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO232 ,CPU Targets Byte Offset 232 " group.long 0x8EC++0x03 line.long 0x00 "GICD_ITARGETSR59,Interrupt Processor Targets Register 59" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO239 ,CPU Targets Byte Offset 239 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO238 ,CPU Targets Byte Offset 238 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO237 ,CPU Targets Byte Offset 237 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO236 ,CPU Targets Byte Offset 236 " group.long 0x8F0++0x03 line.long 0x00 "GICD_ITARGETSR60,Interrupt Processor Targets Register 60" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO243 ,CPU Targets Byte Offset 243 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO242 ,CPU Targets Byte Offset 242 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO241 ,CPU Targets Byte Offset 241 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO240 ,CPU Targets Byte Offset 240 " group.long 0x8F4++0x03 line.long 0x00 "GICD_ITARGETSR61,Interrupt Processor Targets Register 61" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO247 ,CPU Targets Byte Offset 247 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO246 ,CPU Targets Byte Offset 246 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO245 ,CPU Targets Byte Offset 245 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO244 ,CPU Targets Byte Offset 244 " group.long 0x8F8++0x03 line.long 0x00 "GICD_ITARGETSR62,Interrupt Processor Targets Register 62" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO251 ,CPU Targets Byte Offset 251 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO250 ,CPU Targets Byte Offset 250 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO249 ,CPU Targets Byte Offset 249 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO248 ,CPU Targets Byte Offset 248 " group.long 0x8FC++0x03 line.long 0x00 "GICD_ITARGETSR63,Interrupt Processor Targets Register 63" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO255 ,CPU Targets Byte Offset 255 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO254 ,CPU Targets Byte Offset 254 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO253 ,CPU Targets Byte Offset 253 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO252 ,CPU Targets Byte Offset 252 " else rgroup.long 0x8E0++0x03 line.long 0x00 "GICD_ITARGETSR56,Interrupt Processor Targets Register 56" rgroup.long 0x8E4++0x03 line.long 0x00 "GICD_ITARGETSR57,Interrupt Processor Targets Register 57" rgroup.long 0x8E8++0x03 line.long 0x00 "GICD_ITARGETSR58,Interrupt Processor Targets Register 58" rgroup.long 0x8EC++0x03 line.long 0x00 "GICD_ITARGETSR59,Interrupt Processor Targets Register 59" rgroup.long 0x8F0++0x03 line.long 0x00 "GICD_ITARGETSR60,Interrupt Processor Targets Register 60" rgroup.long 0x8F4++0x03 line.long 0x00 "GICD_ITARGETSR61,Interrupt Processor Targets Register 61" rgroup.long 0x8F8++0x03 line.long 0x00 "GICD_ITARGETSR62,Interrupt Processor Targets Register 62" rgroup.long 0x8FC++0x03 line.long 0x00 "GICD_ITARGETSR63,Interrupt Processor Targets Register 63" endif if (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x08) group.long 0x900++0x03 line.long 0x00 "GICD_ITARGETSR64,Interrupt Processor Targets Register 64" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO259 ,CPU Targets Byte Offset 259 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO258 ,CPU Targets Byte Offset 258 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO257 ,CPU Targets Byte Offset 257 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO256 ,CPU Targets Byte Offset 256 " group.long 0x904++0x03 line.long 0x00 "GICD_ITARGETSR65,Interrupt Processor Targets Register 65" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO263 ,CPU Targets Byte Offset 263 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO262 ,CPU Targets Byte Offset 262 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO261 ,CPU Targets Byte Offset 261 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO260 ,CPU Targets Byte Offset 260 " group.long 0x908++0x03 line.long 0x00 "GICD_ITARGETSR66,Interrupt Processor Targets Register 66" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO267 ,CPU Targets Byte Offset 267 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO266 ,CPU Targets Byte Offset 266 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO265 ,CPU Targets Byte Offset 265 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO264 ,CPU Targets Byte Offset 264 " group.long 0x90C++0x03 line.long 0x00 "GICD_ITARGETSR67,Interrupt Processor Targets Register 67" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO271 ,CPU Targets Byte Offset 271 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO270 ,CPU Targets Byte Offset 270 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO269 ,CPU Targets Byte Offset 269 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO268 ,CPU Targets Byte Offset 268 " group.long 0x910++0x03 line.long 0x00 "GICD_ITARGETSR68,Interrupt Processor Targets Register 68" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO275 ,CPU Targets Byte Offset 275 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO274 ,CPU Targets Byte Offset 274 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO273 ,CPU Targets Byte Offset 273 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO272 ,CPU Targets Byte Offset 272 " group.long 0x914++0x03 line.long 0x00 "GICD_ITARGETSR69,Interrupt Processor Targets Register 69" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO279 ,CPU Targets Byte Offset 279 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO278 ,CPU Targets Byte Offset 278 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO277 ,CPU Targets Byte Offset 277 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO276 ,CPU Targets Byte Offset 276 " group.long 0x918++0x03 line.long 0x00 "GICD_ITARGETSR70,Interrupt Processor Targets Register 70" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO283 ,CPU Targets Byte Offset 283 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO282 ,CPU Targets Byte Offset 282 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO281 ,CPU Targets Byte Offset 281 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO280 ,CPU Targets Byte Offset 280 " group.long 0x91C++0x03 line.long 0x00 "GICD_ITARGETSR71,Interrupt Processor Targets Register 71" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO287 ,CPU Targets Byte Offset 287 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO286 ,CPU Targets Byte Offset 286 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO285 ,CPU Targets Byte Offset 285 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO284 ,CPU Targets Byte Offset 284 " else rgroup.long 0x900++0x03 line.long 0x00 "GICD_ITARGETSR64,Interrupt Processor Targets Register 64" rgroup.long 0x904++0x03 line.long 0x00 "GICD_ITARGETSR65,Interrupt Processor Targets Register 65" rgroup.long 0x908++0x03 line.long 0x00 "GICD_ITARGETSR66,Interrupt Processor Targets Register 66" rgroup.long 0x90C++0x03 line.long 0x00 "GICD_ITARGETSR67,Interrupt Processor Targets Register 67" rgroup.long 0x910++0x03 line.long 0x00 "GICD_ITARGETSR68,Interrupt Processor Targets Register 68" rgroup.long 0x914++0x03 line.long 0x00 "GICD_ITARGETSR69,Interrupt Processor Targets Register 69" rgroup.long 0x918++0x03 line.long 0x00 "GICD_ITARGETSR70,Interrupt Processor Targets Register 70" rgroup.long 0x91C++0x03 line.long 0x00 "GICD_ITARGETSR71,Interrupt Processor Targets Register 71" endif if (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x09) group.long 0x920++0x03 line.long 0x00 "GICD_ITARGETSR72,Interrupt Processor Targets Register 72" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO291 ,CPU Targets Byte Offset 291 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO290 ,CPU Targets Byte Offset 290 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO289 ,CPU Targets Byte Offset 289 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO288 ,CPU Targets Byte Offset 288 " group.long 0x924++0x03 line.long 0x00 "GICD_ITARGETSR73,Interrupt Processor Targets Register 73" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO295 ,CPU Targets Byte Offset 295 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO294 ,CPU Targets Byte Offset 294 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO293 ,CPU Targets Byte Offset 293 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO292 ,CPU Targets Byte Offset 292 " group.long 0x928++0x03 line.long 0x00 "GICD_ITARGETSR74,Interrupt Processor Targets Register 74" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO299 ,CPU Targets Byte Offset 299 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO298 ,CPU Targets Byte Offset 298 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO297 ,CPU Targets Byte Offset 297 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO296 ,CPU Targets Byte Offset 296 " group.long 0x92C++0x03 line.long 0x00 "GICD_ITARGETSR75,Interrupt Processor Targets Register 75" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO303 ,CPU Targets Byte Offset 303 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO302 ,CPU Targets Byte Offset 302 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO301 ,CPU Targets Byte Offset 301 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO300 ,CPU Targets Byte Offset 300 " group.long 0x930++0x03 line.long 0x00 "GICD_ITARGETSR76,Interrupt Processor Targets Register 76" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO307 ,CPU Targets Byte Offset 307 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO306 ,CPU Targets Byte Offset 306 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO305 ,CPU Targets Byte Offset 305 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO304 ,CPU Targets Byte Offset 304 " group.long 0x934++0x03 line.long 0x00 "GICD_ITARGETSR77,Interrupt Processor Targets Register 77" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO311 ,CPU Targets Byte Offset 311 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO310 ,CPU Targets Byte Offset 310 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO309 ,CPU Targets Byte Offset 309 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO308 ,CPU Targets Byte Offset 308 " group.long 0x938++0x03 line.long 0x00 "GICD_ITARGETSR78,Interrupt Processor Targets Register 78" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO315 ,CPU Targets Byte Offset 315 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO314 ,CPU Targets Byte Offset 314 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO313 ,CPU Targets Byte Offset 313 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO312 ,CPU Targets Byte Offset 312 " group.long 0x93C++0x03 line.long 0x00 "GICD_ITARGETSR79,Interrupt Processor Targets Register 79" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO319 ,CPU Targets Byte Offset 319 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO318 ,CPU Targets Byte Offset 318 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO317 ,CPU Targets Byte Offset 317 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO316 ,CPU Targets Byte Offset 316 " else rgroup.long 0x920++0x03 line.long 0x00 "GICD_ITARGETSR72,Interrupt Processor Targets Register 72" rgroup.long 0x924++0x03 line.long 0x00 "GICD_ITARGETSR73,Interrupt Processor Targets Register 73" rgroup.long 0x928++0x03 line.long 0x00 "GICD_ITARGETSR74,Interrupt Processor Targets Register 74" rgroup.long 0x92C++0x03 line.long 0x00 "GICD_ITARGETSR75,Interrupt Processor Targets Register 75" rgroup.long 0x930++0x03 line.long 0x00 "GICD_ITARGETSR76,Interrupt Processor Targets Register 76" rgroup.long 0x934++0x03 line.long 0x00 "GICD_ITARGETSR77,Interrupt Processor Targets Register 77" rgroup.long 0x938++0x03 line.long 0x00 "GICD_ITARGETSR78,Interrupt Processor Targets Register 78" rgroup.long 0x93C++0x03 line.long 0x00 "GICD_ITARGETSR79,Interrupt Processor Targets Register 79" endif if (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x0A) group.long 0x940++0x03 line.long 0x00 "GICD_ITARGETSR80,Interrupt Processor Targets Register 80" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO323 ,CPU Targets Byte Offset 323 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO322 ,CPU Targets Byte Offset 322 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO321 ,CPU Targets Byte Offset 321 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO320 ,CPU Targets Byte Offset 320 " group.long 0x944++0x03 line.long 0x00 "GICD_ITARGETSR81,Interrupt Processor Targets Register 81" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO327 ,CPU Targets Byte Offset 327 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO326 ,CPU Targets Byte Offset 326 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO325 ,CPU Targets Byte Offset 325 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO324 ,CPU Targets Byte Offset 324 " group.long 0x948++0x03 line.long 0x00 "GICD_ITARGETSR82,Interrupt Processor Targets Register 82" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO331 ,CPU Targets Byte Offset 331 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO330 ,CPU Targets Byte Offset 330 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO329 ,CPU Targets Byte Offset 329 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO328 ,CPU Targets Byte Offset 328 " group.long 0x94C++0x03 line.long 0x00 "GICD_ITARGETSR83,Interrupt Processor Targets Register 83" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO335 ,CPU Targets Byte Offset 335 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO334 ,CPU Targets Byte Offset 334 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO333 ,CPU Targets Byte Offset 333 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO332 ,CPU Targets Byte Offset 332 " group.long 0x950++0x03 line.long 0x00 "GICD_ITARGETSR84,Interrupt Processor Targets Register 84" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO339 ,CPU Targets Byte Offset 339 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO338 ,CPU Targets Byte Offset 338 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO337 ,CPU Targets Byte Offset 337 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO336 ,CPU Targets Byte Offset 336 " group.long 0x954++0x03 line.long 0x00 "GICD_ITARGETSR85,Interrupt Processor Targets Register 85" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO343 ,CPU Targets Byte Offset 343 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO342 ,CPU Targets Byte Offset 342 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO341 ,CPU Targets Byte Offset 341 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO340 ,CPU Targets Byte Offset 340 " group.long 0x958++0x03 line.long 0x00 "GICD_ITARGETSR86,Interrupt Processor Targets Register 86" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO347 ,CPU Targets Byte Offset 347 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO346 ,CPU Targets Byte Offset 346 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO345 ,CPU Targets Byte Offset 345 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO344 ,CPU Targets Byte Offset 344 " group.long 0x95C++0x03 line.long 0x00 "GICD_ITARGETSR87,Interrupt Processor Targets Register 87" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO351 ,CPU Targets Byte Offset 351 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO350 ,CPU Targets Byte Offset 350 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO349 ,CPU Targets Byte Offset 349 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO348 ,CPU Targets Byte Offset 348 " else rgroup.long 0x940++0x03 line.long 0x00 "GICD_ITARGETSR80,Interrupt Processor Targets Register 80" rgroup.long 0x944++0x03 line.long 0x00 "GICD_ITARGETSR81,Interrupt Processor Targets Register 81" rgroup.long 0x948++0x03 line.long 0x00 "GICD_ITARGETSR82,Interrupt Processor Targets Register 82" rgroup.long 0x94C++0x03 line.long 0x00 "GICD_ITARGETSR83,Interrupt Processor Targets Register 83" rgroup.long 0x950++0x03 line.long 0x00 "GICD_ITARGETSR84,Interrupt Processor Targets Register 84" rgroup.long 0x954++0x03 line.long 0x00 "GICD_ITARGETSR85,Interrupt Processor Targets Register 85" rgroup.long 0x958++0x03 line.long 0x00 "GICD_ITARGETSR86,Interrupt Processor Targets Register 86" rgroup.long 0x95C++0x03 line.long 0x00 "GICD_ITARGETSR87,Interrupt Processor Targets Register 87" endif if (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x0B) group.long 0x960++0x03 line.long 0x00 "GICD_ITARGETSR88,Interrupt Processor Targets Register 88" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO355 ,CPU Targets Byte Offset 355 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO354 ,CPU Targets Byte Offset 354 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO353 ,CPU Targets Byte Offset 353 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO352 ,CPU Targets Byte Offset 352 " group.long 0x964++0x03 line.long 0x00 "GICD_ITARGETSR89,Interrupt Processor Targets Register 89" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO359 ,CPU Targets Byte Offset 359 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO358 ,CPU Targets Byte Offset 358 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO357 ,CPU Targets Byte Offset 357 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO356 ,CPU Targets Byte Offset 356 " group.long 0x968++0x03 line.long 0x00 "GICD_ITARGETSR90,Interrupt Processor Targets Register 90" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO363 ,CPU Targets Byte Offset 363 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO362 ,CPU Targets Byte Offset 362 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO361 ,CPU Targets Byte Offset 361 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO360 ,CPU Targets Byte Offset 360 " group.long 0x96C++0x03 line.long 0x00 "GICD_ITARGETSR91,Interrupt Processor Targets Register 91" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO367 ,CPU Targets Byte Offset 367 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO366 ,CPU Targets Byte Offset 366 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO365 ,CPU Targets Byte Offset 365 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO364 ,CPU Targets Byte Offset 364 " group.long 0x970++0x03 line.long 0x00 "GICD_ITARGETSR92,Interrupt Processor Targets Register 92" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO371 ,CPU Targets Byte Offset 371 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO370 ,CPU Targets Byte Offset 370 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO369 ,CPU Targets Byte Offset 369 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO368 ,CPU Targets Byte Offset 368 " group.long 0x974++0x03 line.long 0x00 "GICD_ITARGETSR93,Interrupt Processor Targets Register 93" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO375 ,CPU Targets Byte Offset 375 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO374 ,CPU Targets Byte Offset 374 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO373 ,CPU Targets Byte Offset 373 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO372 ,CPU Targets Byte Offset 372 " group.long 0x978++0x03 line.long 0x00 "GICD_ITARGETSR94,Interrupt Processor Targets Register 94" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO379 ,CPU Targets Byte Offset 379 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO378 ,CPU Targets Byte Offset 378 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO377 ,CPU Targets Byte Offset 377 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO376 ,CPU Targets Byte Offset 376 " group.long 0x97C++0x03 line.long 0x00 "GICD_ITARGETSR95,Interrupt Processor Targets Register 95" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO383 ,CPU Targets Byte Offset 383 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO382 ,CPU Targets Byte Offset 382 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO381 ,CPU Targets Byte Offset 381 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO380 ,CPU Targets Byte Offset 380 " else rgroup.long 0x960++0x03 line.long 0x00 "GICD_ITARGETSR88,Interrupt Processor Targets Register 88" rgroup.long 0x964++0x03 line.long 0x00 "GICD_ITARGETSR89,Interrupt Processor Targets Register 89" rgroup.long 0x968++0x03 line.long 0x00 "GICD_ITARGETSR90,Interrupt Processor Targets Register 90" rgroup.long 0x96C++0x03 line.long 0x00 "GICD_ITARGETSR91,Interrupt Processor Targets Register 91" rgroup.long 0x970++0x03 line.long 0x00 "GICD_ITARGETSR92,Interrupt Processor Targets Register 92" rgroup.long 0x974++0x03 line.long 0x00 "GICD_ITARGETSR93,Interrupt Processor Targets Register 93" rgroup.long 0x978++0x03 line.long 0x00 "GICD_ITARGETSR94,Interrupt Processor Targets Register 94" rgroup.long 0x97C++0x03 line.long 0x00 "GICD_ITARGETSR95,Interrupt Processor Targets Register 95" endif if (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x0C) group.long 0x980++0x03 line.long 0x00 "GICD_ITARGETSR96,Interrupt Processor Targets Register 96" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO387 ,CPU Targets Byte Offset 387 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO386 ,CPU Targets Byte Offset 386 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO385 ,CPU Targets Byte Offset 385 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO384 ,CPU Targets Byte Offset 384 " group.long 0x984++0x03 line.long 0x00 "GICD_ITARGETSR97,Interrupt Processor Targets Register 97" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO391 ,CPU Targets Byte Offset 391 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO390 ,CPU Targets Byte Offset 390 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO389 ,CPU Targets Byte Offset 389 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO388 ,CPU Targets Byte Offset 388 " group.long 0x988++0x03 line.long 0x00 "GICD_ITARGETSR98,Interrupt Processor Targets Register 98" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO395 ,CPU Targets Byte Offset 395 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO394 ,CPU Targets Byte Offset 394 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO393 ,CPU Targets Byte Offset 393 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO392 ,CPU Targets Byte Offset 392 " group.long 0x98C++0x03 line.long 0x00 "GICD_ITARGETSR99,Interrupt Processor Targets Register 99" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO399 ,CPU Targets Byte Offset 399 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO398 ,CPU Targets Byte Offset 398 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO397 ,CPU Targets Byte Offset 397 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO396 ,CPU Targets Byte Offset 396 " group.long 0x990++0x03 line.long 0x00 "GICD_ITARGETSR100,Interrupt Processor Targets Register 100" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO403 ,CPU Targets Byte Offset 403 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO402 ,CPU Targets Byte Offset 402 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO401 ,CPU Targets Byte Offset 401 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO400 ,CPU Targets Byte Offset 400 " group.long 0x994++0x03 line.long 0x00 "GICD_ITARGETSR101,Interrupt Processor Targets Register 101" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO407 ,CPU Targets Byte Offset 407 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO406 ,CPU Targets Byte Offset 406 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO405 ,CPU Targets Byte Offset 405 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO404 ,CPU Targets Byte Offset 404 " group.long 0x998++0x03 line.long 0x00 "GICD_ITARGETSR102,Interrupt Processor Targets Register 102" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO411 ,CPU Targets Byte Offset 411 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO410 ,CPU Targets Byte Offset 410 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO409 ,CPU Targets Byte Offset 409 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO408 ,CPU Targets Byte Offset 408 " group.long 0x99C++0x03 line.long 0x00 "GICD_ITARGETSR103,Interrupt Processor Targets Register 103" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO415 ,CPU Targets Byte Offset 415 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO414 ,CPU Targets Byte Offset 414 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO413 ,CPU Targets Byte Offset 413 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO412 ,CPU Targets Byte Offset 412 " else rgroup.long 0x980++0x03 line.long 0x00 "GICD_ITARGETSR96,Interrupt Processor Targets Register 96" rgroup.long 0x984++0x03 line.long 0x00 "GICD_ITARGETSR97,Interrupt Processor Targets Register 97" rgroup.long 0x988++0x03 line.long 0x00 "GICD_ITARGETSR98,Interrupt Processor Targets Register 98" rgroup.long 0x98C++0x03 line.long 0x00 "GICD_ITARGETSR99,Interrupt Processor Targets Register 99" rgroup.long 0x990++0x03 line.long 0x00 "GICD_ITARGETSR100,Interrupt Processor Targets Register 100" rgroup.long 0x994++0x03 line.long 0x00 "GICD_ITARGETSR101,Interrupt Processor Targets Register 101" rgroup.long 0x998++0x03 line.long 0x00 "GICD_ITARGETSR102,Interrupt Processor Targets Register 102" rgroup.long 0x99C++0x03 line.long 0x00 "GICD_ITARGETSR103,Interrupt Processor Targets Register 103" endif if (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x0D) group.long 0x9A0++0x03 line.long 0x00 "GICD_ITARGETSR104,Interrupt Processor Targets Register 104" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO419 ,CPU Targets Byte Offset 419 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO418 ,CPU Targets Byte Offset 418 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO417 ,CPU Targets Byte Offset 417 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO416 ,CPU Targets Byte Offset 416 " group.long 0x9A4++0x03 line.long 0x00 "GICD_ITARGETSR105,Interrupt Processor Targets Register 105" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO423 ,CPU Targets Byte Offset 423 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO422 ,CPU Targets Byte Offset 422 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO421 ,CPU Targets Byte Offset 421 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO420 ,CPU Targets Byte Offset 420 " group.long 0x9A8++0x03 line.long 0x00 "GICD_ITARGETSR106,Interrupt Processor Targets Register 106" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO427 ,CPU Targets Byte Offset 427 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO426 ,CPU Targets Byte Offset 426 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO425 ,CPU Targets Byte Offset 425 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO424 ,CPU Targets Byte Offset 424 " group.long 0x9AC++0x03 line.long 0x00 "GICD_ITARGETSR107,Interrupt Processor Targets Register 107" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO431 ,CPU Targets Byte Offset 431 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO430 ,CPU Targets Byte Offset 430 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO429 ,CPU Targets Byte Offset 429 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO428 ,CPU Targets Byte Offset 428 " group.long 0x9B0++0x03 line.long 0x00 "GICD_ITARGETSR108,Interrupt Processor Targets Register 108" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO435 ,CPU Targets Byte Offset 435 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO434 ,CPU Targets Byte Offset 434 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO433 ,CPU Targets Byte Offset 433 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO432 ,CPU Targets Byte Offset 432 " group.long 0x9B4++0x03 line.long 0x00 "GICD_ITARGETSR109,Interrupt Processor Targets Register 109" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO439 ,CPU Targets Byte Offset 439 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO438 ,CPU Targets Byte Offset 438 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO437 ,CPU Targets Byte Offset 437 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO436 ,CPU Targets Byte Offset 436 " group.long 0x9B8++0x03 line.long 0x00 "GICD_ITARGETSR110,Interrupt Processor Targets Register 110" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO443 ,CPU Targets Byte Offset 443 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO442 ,CPU Targets Byte Offset 442 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO441 ,CPU Targets Byte Offset 441 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO440 ,CPU Targets Byte Offset 440 " group.long 0x9BC++0x03 line.long 0x00 "GICD_ITARGETSR111,Interrupt Processor Targets Register 111" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO447 ,CPU Targets Byte Offset 447 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO446 ,CPU Targets Byte Offset 446 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO445 ,CPU Targets Byte Offset 445 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO444 ,CPU Targets Byte Offset 444 " else rgroup.long 0x9A0++0x03 line.long 0x00 "GICD_ITARGETSR104,Interrupt Processor Targets Register 104" rgroup.long 0x9A4++0x03 line.long 0x00 "GICD_ITARGETSR105,Interrupt Processor Targets Register 105" rgroup.long 0x9A8++0x03 line.long 0x00 "GICD_ITARGETSR106,Interrupt Processor Targets Register 106" rgroup.long 0x9AC++0x03 line.long 0x00 "GICD_ITARGETSR107,Interrupt Processor Targets Register 107" rgroup.long 0x9B0++0x03 line.long 0x00 "GICD_ITARGETSR108,Interrupt Processor Targets Register 108" rgroup.long 0x9B4++0x03 line.long 0x00 "GICD_ITARGETSR109,Interrupt Processor Targets Register 109" rgroup.long 0x9B8++0x03 line.long 0x00 "GICD_ITARGETSR110,Interrupt Processor Targets Register 110" rgroup.long 0x9BC++0x03 line.long 0x00 "GICD_ITARGETSR111,Interrupt Processor Targets Register 111" endif if (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x0E) group.long 0x9C0++0x03 line.long 0x00 "GICD_ITARGETSR112,Interrupt Processor Targets Register 112" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO451 ,CPU Targets Byte Offset 451 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO450 ,CPU Targets Byte Offset 450 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO449 ,CPU Targets Byte Offset 449 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO448 ,CPU Targets Byte Offset 448 " group.long 0x9C4++0x03 line.long 0x00 "GICD_ITARGETSR113,Interrupt Processor Targets Register 113" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO455 ,CPU Targets Byte Offset 455 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO454 ,CPU Targets Byte Offset 454 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO453 ,CPU Targets Byte Offset 453 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO452 ,CPU Targets Byte Offset 452 " group.long 0x9C8++0x03 line.long 0x00 "GICD_ITARGETSR114,Interrupt Processor Targets Register 114" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO459 ,CPU Targets Byte Offset 459 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO458 ,CPU Targets Byte Offset 458 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO457 ,CPU Targets Byte Offset 457 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO456 ,CPU Targets Byte Offset 456 " group.long 0x9CC++0x03 line.long 0x00 "GICD_ITARGETSR115,Interrupt Processor Targets Register 115" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO463 ,CPU Targets Byte Offset 463 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO462 ,CPU Targets Byte Offset 462 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO461 ,CPU Targets Byte Offset 461 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO460 ,CPU Targets Byte Offset 460 " group.long 0x9D0++0x03 line.long 0x00 "GICD_ITARGETSR116,Interrupt Processor Targets Register 116" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO467 ,CPU Targets Byte Offset 467 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO466 ,CPU Targets Byte Offset 466 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO465 ,CPU Targets Byte Offset 465 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO464 ,CPU Targets Byte Offset 464 " group.long 0x9D4++0x03 line.long 0x00 "GICD_ITARGETSR117,Interrupt Processor Targets Register 117" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO471 ,CPU Targets Byte Offset 471 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO470 ,CPU Targets Byte Offset 470 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO469 ,CPU Targets Byte Offset 469 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO468 ,CPU Targets Byte Offset 468 " group.long 0x9D8++0x03 line.long 0x00 "GICD_ITARGETSR118,Interrupt Processor Targets Register 118" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO475 ,CPU Targets Byte Offset 475 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO474 ,CPU Targets Byte Offset 474 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO473 ,CPU Targets Byte Offset 473 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO472 ,CPU Targets Byte Offset 472 " group.long 0x9DC++0x03 line.long 0x00 "GICD_ITARGETSR119,Interrupt Processor Targets Register 119" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO479 ,CPU Targets Byte Offset 479 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO478 ,CPU Targets Byte Offset 478 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO477 ,CPU Targets Byte Offset 477 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO476 ,CPU Targets Byte Offset 476 " else rgroup.long 0x9C0++0x03 line.long 0x00 "GICD_ITARGETSR112,Interrupt Processor Targets Register 112" rgroup.long 0x9C4++0x03 line.long 0x00 "GICD_ITARGETSR113,Interrupt Processor Targets Register 113" rgroup.long 0x9C8++0x03 line.long 0x00 "GICD_ITARGETSR114,Interrupt Processor Targets Register 114" rgroup.long 0x9CC++0x03 line.long 0x00 "GICD_ITARGETSR115,Interrupt Processor Targets Register 115" rgroup.long 0x9D0++0x03 line.long 0x00 "GICD_ITARGETSR116,Interrupt Processor Targets Register 116" rgroup.long 0x9D4++0x03 line.long 0x00 "GICD_ITARGETSR117,Interrupt Processor Targets Register 117" rgroup.long 0x9D8++0x03 line.long 0x00 "GICD_ITARGETSR118,Interrupt Processor Targets Register 118" rgroup.long 0x9DC++0x03 line.long 0x00 "GICD_ITARGETSR119,Interrupt Processor Targets Register 119" endif if (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x0F) group.long 0x9E0++0x03 line.long 0x00 "GICD_ITARGETSR120,Interrupt Processor Targets Register 120" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO483 ,CPU Targets Byte Offset 483 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO482 ,CPU Targets Byte Offset 482 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO481 ,CPU Targets Byte Offset 481 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO480 ,CPU Targets Byte Offset 480 " group.long 0x9E4++0x03 line.long 0x00 "GICD_ITARGETSR121,Interrupt Processor Targets Register 121" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO487 ,CPU Targets Byte Offset 487 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO486 ,CPU Targets Byte Offset 486 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO485 ,CPU Targets Byte Offset 485 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO484 ,CPU Targets Byte Offset 484 " group.long 0x9E8++0x03 line.long 0x00 "GICD_ITARGETSR122,Interrupt Processor Targets Register 122" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO491 ,CPU Targets Byte Offset 491 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO490 ,CPU Targets Byte Offset 490 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO489 ,CPU Targets Byte Offset 489 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO488 ,CPU Targets Byte Offset 488 " group.long 0x9EC++0x03 line.long 0x00 "GICD_ITARGETSR123,Interrupt Processor Targets Register 123" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO495 ,CPU Targets Byte Offset 495 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO494 ,CPU Targets Byte Offset 494 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO493 ,CPU Targets Byte Offset 493 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO492 ,CPU Targets Byte Offset 492 " group.long 0x9F0++0x03 line.long 0x00 "GICD_ITARGETSR124,Interrupt Processor Targets Register 124" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO499 ,CPU Targets Byte Offset 499 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO498 ,CPU Targets Byte Offset 498 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO497 ,CPU Targets Byte Offset 497 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO496 ,CPU Targets Byte Offset 496 " group.long 0x9F4++0x03 line.long 0x00 "GICD_ITARGETSR125,Interrupt Processor Targets Register 125" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO503 ,CPU Targets Byte Offset 503 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO502 ,CPU Targets Byte Offset 502 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO501 ,CPU Targets Byte Offset 501 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO500 ,CPU Targets Byte Offset 500 " group.long 0x9F8++0x03 line.long 0x00 "GICD_ITARGETSR126,Interrupt Processor Targets Register 126" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO507 ,CPU Targets Byte Offset 507 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO506 ,CPU Targets Byte Offset 506 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO505 ,CPU Targets Byte Offset 505 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO504 ,CPU Targets Byte Offset 504 " group.long 0x9FC++0x03 line.long 0x00 "GICD_ITARGETSR127,Interrupt Processor Targets Register 127" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO511 ,CPU Targets Byte Offset 511 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO510 ,CPU Targets Byte Offset 510 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO509 ,CPU Targets Byte Offset 509 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO508 ,CPU Targets Byte Offset 508 " else rgroup.long 0x9E0++0x03 line.long 0x00 "GICD_ITARGETSR120,Interrupt Processor Targets Register 120" rgroup.long 0x9E4++0x03 line.long 0x00 "GICD_ITARGETSR121,Interrupt Processor Targets Register 121" rgroup.long 0x9E8++0x03 line.long 0x00 "GICD_ITARGETSR122,Interrupt Processor Targets Register 122" rgroup.long 0x9EC++0x03 line.long 0x00 "GICD_ITARGETSR123,Interrupt Processor Targets Register 123" rgroup.long 0x9F0++0x03 line.long 0x00 "GICD_ITARGETSR124,Interrupt Processor Targets Register 124" rgroup.long 0x9F4++0x03 line.long 0x00 "GICD_ITARGETSR125,Interrupt Processor Targets Register 125" rgroup.long 0x9F8++0x03 line.long 0x00 "GICD_ITARGETSR126,Interrupt Processor Targets Register 126" rgroup.long 0x9FC++0x03 line.long 0x00 "GICD_ITARGETSR127,Interrupt Processor Targets Register 127" endif if (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x10) group.long 0xA00++0x03 line.long 0x00 "GICD_ITARGETSR128,Interrupt Processor Targets Register 128" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO515 ,CPU Targets Byte Offset 515 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO514 ,CPU Targets Byte Offset 514 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO513 ,CPU Targets Byte Offset 513 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO512 ,CPU Targets Byte Offset 512 " group.long 0xA04++0x03 line.long 0x00 "GICD_ITARGETSR129,Interrupt Processor Targets Register 129" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO519 ,CPU Targets Byte Offset 519 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO518 ,CPU Targets Byte Offset 518 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO517 ,CPU Targets Byte Offset 517 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO516 ,CPU Targets Byte Offset 516 " group.long 0xA08++0x03 line.long 0x00 "GICD_ITARGETSR130,Interrupt Processor Targets Register 130" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO523 ,CPU Targets Byte Offset 523 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO522 ,CPU Targets Byte Offset 522 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO521 ,CPU Targets Byte Offset 521 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO520 ,CPU Targets Byte Offset 520 " group.long 0xA0C++0x03 line.long 0x00 "GICD_ITARGETSR131,Interrupt Processor Targets Register 131" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO527 ,CPU Targets Byte Offset 527 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO526 ,CPU Targets Byte Offset 526 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO525 ,CPU Targets Byte Offset 525 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO524 ,CPU Targets Byte Offset 524 " group.long 0xA10++0x03 line.long 0x00 "GICD_ITARGETSR132,Interrupt Processor Targets Register 132" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO531 ,CPU Targets Byte Offset 531 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO530 ,CPU Targets Byte Offset 530 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO529 ,CPU Targets Byte Offset 529 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO528 ,CPU Targets Byte Offset 528 " group.long 0xA14++0x03 line.long 0x00 "GICD_ITARGETSR133,Interrupt Processor Targets Register 133" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO535 ,CPU Targets Byte Offset 535 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO534 ,CPU Targets Byte Offset 534 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO533 ,CPU Targets Byte Offset 533 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO532 ,CPU Targets Byte Offset 532 " group.long 0xA18++0x03 line.long 0x00 "GICD_ITARGETSR134,Interrupt Processor Targets Register 134" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO539 ,CPU Targets Byte Offset 539 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO538 ,CPU Targets Byte Offset 538 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO537 ,CPU Targets Byte Offset 537 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO536 ,CPU Targets Byte Offset 536 " group.long 0xA1C++0x03 line.long 0x00 "GICD_ITARGETSR135,Interrupt Processor Targets Register 135" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO543 ,CPU Targets Byte Offset 543 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO542 ,CPU Targets Byte Offset 542 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO541 ,CPU Targets Byte Offset 541 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO540 ,CPU Targets Byte Offset 540 " else rgroup.long 0xA00++0x03 line.long 0x00 "GICD_ITARGETSR128,Interrupt Processor Targets Register 128" rgroup.long 0xA04++0x03 line.long 0x00 "GICD_ITARGETSR129,Interrupt Processor Targets Register 129" rgroup.long 0xA08++0x03 line.long 0x00 "GICD_ITARGETSR130,Interrupt Processor Targets Register 130" rgroup.long 0xA0C++0x03 line.long 0x00 "GICD_ITARGETSR131,Interrupt Processor Targets Register 131" rgroup.long 0xA10++0x03 line.long 0x00 "GICD_ITARGETSR132,Interrupt Processor Targets Register 132" rgroup.long 0xA14++0x03 line.long 0x00 "GICD_ITARGETSR133,Interrupt Processor Targets Register 133" rgroup.long 0xA18++0x03 line.long 0x00 "GICD_ITARGETSR134,Interrupt Processor Targets Register 134" rgroup.long 0xA1C++0x03 line.long 0x00 "GICD_ITARGETSR135,Interrupt Processor Targets Register 135" endif if (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x11) group.long 0xA20++0x03 line.long 0x00 "GICD_ITARGETSR136,Interrupt Processor Targets Register 136" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO547 ,CPU Targets Byte Offset 547 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO546 ,CPU Targets Byte Offset 546 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO545 ,CPU Targets Byte Offset 545 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO544 ,CPU Targets Byte Offset 544 " group.long 0xA24++0x03 line.long 0x00 "GICD_ITARGETSR137,Interrupt Processor Targets Register 137" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO551 ,CPU Targets Byte Offset 551 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO550 ,CPU Targets Byte Offset 550 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO549 ,CPU Targets Byte Offset 549 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO548 ,CPU Targets Byte Offset 548 " group.long 0xA28++0x03 line.long 0x00 "GICD_ITARGETSR138,Interrupt Processor Targets Register 138" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO555 ,CPU Targets Byte Offset 555 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO554 ,CPU Targets Byte Offset 554 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO553 ,CPU Targets Byte Offset 553 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO552 ,CPU Targets Byte Offset 552 " group.long 0xA2C++0x03 line.long 0x00 "GICD_ITARGETSR139,Interrupt Processor Targets Register 139" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO559 ,CPU Targets Byte Offset 559 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO558 ,CPU Targets Byte Offset 558 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO557 ,CPU Targets Byte Offset 557 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO556 ,CPU Targets Byte Offset 556 " group.long 0xA30++0x03 line.long 0x00 "GICD_ITARGETSR140,Interrupt Processor Targets Register 140" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO563 ,CPU Targets Byte Offset 563 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO562 ,CPU Targets Byte Offset 562 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO561 ,CPU Targets Byte Offset 561 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO560 ,CPU Targets Byte Offset 560 " group.long 0xA34++0x03 line.long 0x00 "GICD_ITARGETSR141,Interrupt Processor Targets Register 141" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO567 ,CPU Targets Byte Offset 567 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO566 ,CPU Targets Byte Offset 566 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO565 ,CPU Targets Byte Offset 565 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO564 ,CPU Targets Byte Offset 564 " group.long 0xA38++0x03 line.long 0x00 "GICD_ITARGETSR142,Interrupt Processor Targets Register 142" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO571 ,CPU Targets Byte Offset 571 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO570 ,CPU Targets Byte Offset 570 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO569 ,CPU Targets Byte Offset 569 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO568 ,CPU Targets Byte Offset 568 " group.long 0xA3C++0x03 line.long 0x00 "GICD_ITARGETSR143,Interrupt Processor Targets Register 143" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO575 ,CPU Targets Byte Offset 575 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO574 ,CPU Targets Byte Offset 574 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO573 ,CPU Targets Byte Offset 573 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO572 ,CPU Targets Byte Offset 572 " else rgroup.long 0xA20++0x03 line.long 0x00 "GICD_ITARGETSR136,Interrupt Processor Targets Register 136" rgroup.long 0xA24++0x03 line.long 0x00 "GICD_ITARGETSR137,Interrupt Processor Targets Register 137" rgroup.long 0xA28++0x03 line.long 0x00 "GICD_ITARGETSR138,Interrupt Processor Targets Register 138" rgroup.long 0xA2C++0x03 line.long 0x00 "GICD_ITARGETSR139,Interrupt Processor Targets Register 139" rgroup.long 0xA30++0x03 line.long 0x00 "GICD_ITARGETSR140,Interrupt Processor Targets Register 140" rgroup.long 0xA34++0x03 line.long 0x00 "GICD_ITARGETSR141,Interrupt Processor Targets Register 141" rgroup.long 0xA38++0x03 line.long 0x00 "GICD_ITARGETSR142,Interrupt Processor Targets Register 142" rgroup.long 0xA3C++0x03 line.long 0x00 "GICD_ITARGETSR143,Interrupt Processor Targets Register 143" endif if (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x12) group.long 0xA40++0x03 line.long 0x00 "GICD_ITARGETSR144,Interrupt Processor Targets Register 144" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO579 ,CPU Targets Byte Offset 579 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO578 ,CPU Targets Byte Offset 578 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO577 ,CPU Targets Byte Offset 577 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO576 ,CPU Targets Byte Offset 576 " group.long 0xA44++0x03 line.long 0x00 "GICD_ITARGETSR145,Interrupt Processor Targets Register 145" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO583 ,CPU Targets Byte Offset 583 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO582 ,CPU Targets Byte Offset 582 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO581 ,CPU Targets Byte Offset 581 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO580 ,CPU Targets Byte Offset 580 " group.long 0xA48++0x03 line.long 0x00 "GICD_ITARGETSR146,Interrupt Processor Targets Register 146" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO587 ,CPU Targets Byte Offset 587 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO586 ,CPU Targets Byte Offset 586 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO585 ,CPU Targets Byte Offset 585 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO584 ,CPU Targets Byte Offset 584 " group.long 0xA4C++0x03 line.long 0x00 "GICD_ITARGETSR147,Interrupt Processor Targets Register 147" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO591 ,CPU Targets Byte Offset 591 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO590 ,CPU Targets Byte Offset 590 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO589 ,CPU Targets Byte Offset 589 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO588 ,CPU Targets Byte Offset 588 " group.long 0xA50++0x03 line.long 0x00 "GICD_ITARGETSR148,Interrupt Processor Targets Register 148" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO595 ,CPU Targets Byte Offset 595 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO594 ,CPU Targets Byte Offset 594 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO593 ,CPU Targets Byte Offset 593 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO592 ,CPU Targets Byte Offset 592 " group.long 0xA54++0x03 line.long 0x00 "GICD_ITARGETSR149,Interrupt Processor Targets Register 149" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO599 ,CPU Targets Byte Offset 599 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO598 ,CPU Targets Byte Offset 598 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO597 ,CPU Targets Byte Offset 597 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO596 ,CPU Targets Byte Offset 596 " group.long 0xA58++0x03 line.long 0x00 "GICD_ITARGETSR150,Interrupt Processor Targets Register 150" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO603 ,CPU Targets Byte Offset 603 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO602 ,CPU Targets Byte Offset 602 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO601 ,CPU Targets Byte Offset 601 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO600 ,CPU Targets Byte Offset 600 " group.long 0xA5C++0x03 line.long 0x00 "GICD_ITARGETSR151,Interrupt Processor Targets Register 151" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO607 ,CPU Targets Byte Offset 607 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO606 ,CPU Targets Byte Offset 606 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO605 ,CPU Targets Byte Offset 605 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO604 ,CPU Targets Byte Offset 604 " else rgroup.long 0xA40++0x03 line.long 0x00 "GICD_ITARGETSR144,Interrupt Processor Targets Register 144" rgroup.long 0xA44++0x03 line.long 0x00 "GICD_ITARGETSR145,Interrupt Processor Targets Register 145" rgroup.long 0xA48++0x03 line.long 0x00 "GICD_ITARGETSR146,Interrupt Processor Targets Register 146" rgroup.long 0xA4C++0x03 line.long 0x00 "GICD_ITARGETSR147,Interrupt Processor Targets Register 147" rgroup.long 0xA50++0x03 line.long 0x00 "GICD_ITARGETSR148,Interrupt Processor Targets Register 148" rgroup.long 0xA54++0x03 line.long 0x00 "GICD_ITARGETSR149,Interrupt Processor Targets Register 149" rgroup.long 0xA58++0x03 line.long 0x00 "GICD_ITARGETSR150,Interrupt Processor Targets Register 150" rgroup.long 0xA5C++0x03 line.long 0x00 "GICD_ITARGETSR151,Interrupt Processor Targets Register 151" endif if (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x13) group.long 0xA60++0x03 line.long 0x00 "GICD_ITARGETSR152,Interrupt Processor Targets Register 152" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO611 ,CPU Targets Byte Offset 611 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO610 ,CPU Targets Byte Offset 610 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO609 ,CPU Targets Byte Offset 609 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO608 ,CPU Targets Byte Offset 608 " group.long 0xA64++0x03 line.long 0x00 "GICD_ITARGETSR153,Interrupt Processor Targets Register 153" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO615 ,CPU Targets Byte Offset 615 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO614 ,CPU Targets Byte Offset 614 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO613 ,CPU Targets Byte Offset 613 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO612 ,CPU Targets Byte Offset 612 " group.long 0xA68++0x03 line.long 0x00 "GICD_ITARGETSR154,Interrupt Processor Targets Register 154" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO619 ,CPU Targets Byte Offset 619 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO618 ,CPU Targets Byte Offset 618 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO617 ,CPU Targets Byte Offset 617 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO616 ,CPU Targets Byte Offset 616 " group.long 0xA6C++0x03 line.long 0x00 "GICD_ITARGETSR155,Interrupt Processor Targets Register 155" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO623 ,CPU Targets Byte Offset 623 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO622 ,CPU Targets Byte Offset 622 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO621 ,CPU Targets Byte Offset 621 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO620 ,CPU Targets Byte Offset 620 " group.long 0xA70++0x03 line.long 0x00 "GICD_ITARGETSR156,Interrupt Processor Targets Register 156" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO627 ,CPU Targets Byte Offset 627 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO626 ,CPU Targets Byte Offset 626 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO625 ,CPU Targets Byte Offset 625 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO624 ,CPU Targets Byte Offset 624 " group.long 0xA74++0x03 line.long 0x00 "GICD_ITARGETSR157,Interrupt Processor Targets Register 157" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO631 ,CPU Targets Byte Offset 631 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO630 ,CPU Targets Byte Offset 630 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO629 ,CPU Targets Byte Offset 629 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO628 ,CPU Targets Byte Offset 628 " group.long 0xA78++0x03 line.long 0x00 "GICD_ITARGETSR158,Interrupt Processor Targets Register 158" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO635 ,CPU Targets Byte Offset 635 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO634 ,CPU Targets Byte Offset 634 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO633 ,CPU Targets Byte Offset 633 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO632 ,CPU Targets Byte Offset 632 " group.long 0xA7C++0x03 line.long 0x00 "GICD_ITARGETSR159,Interrupt Processor Targets Register 159" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO639 ,CPU Targets Byte Offset 639 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO638 ,CPU Targets Byte Offset 638 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO637 ,CPU Targets Byte Offset 637 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO636 ,CPU Targets Byte Offset 636 " else rgroup.long 0xA60++0x03 line.long 0x00 "GICD_ITARGETSR152,Interrupt Processor Targets Register 152" rgroup.long 0xA64++0x03 line.long 0x00 "GICD_ITARGETSR153,Interrupt Processor Targets Register 153" rgroup.long 0xA68++0x03 line.long 0x00 "GICD_ITARGETSR154,Interrupt Processor Targets Register 154" rgroup.long 0xA6C++0x03 line.long 0x00 "GICD_ITARGETSR155,Interrupt Processor Targets Register 155" rgroup.long 0xA70++0x03 line.long 0x00 "GICD_ITARGETSR156,Interrupt Processor Targets Register 156" rgroup.long 0xA74++0x03 line.long 0x00 "GICD_ITARGETSR157,Interrupt Processor Targets Register 157" rgroup.long 0xA78++0x03 line.long 0x00 "GICD_ITARGETSR158,Interrupt Processor Targets Register 158" rgroup.long 0xA7C++0x03 line.long 0x00 "GICD_ITARGETSR159,Interrupt Processor Targets Register 159" endif if (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x14) group.long 0xA80++0x03 line.long 0x00 "GICD_ITARGETSR160,Interrupt Processor Targets Register 160" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO643 ,CPU Targets Byte Offset 643 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO642 ,CPU Targets Byte Offset 642 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO641 ,CPU Targets Byte Offset 641 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO640 ,CPU Targets Byte Offset 640 " group.long 0xA84++0x03 line.long 0x00 "GICD_ITARGETSR161,Interrupt Processor Targets Register 161" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO647 ,CPU Targets Byte Offset 647 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO646 ,CPU Targets Byte Offset 646 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO645 ,CPU Targets Byte Offset 645 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO644 ,CPU Targets Byte Offset 644 " group.long 0xA88++0x03 line.long 0x00 "GICD_ITARGETSR162,Interrupt Processor Targets Register 162" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO651 ,CPU Targets Byte Offset 651 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO650 ,CPU Targets Byte Offset 650 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO649 ,CPU Targets Byte Offset 649 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO648 ,CPU Targets Byte Offset 648 " group.long 0xA8C++0x03 line.long 0x00 "GICD_ITARGETSR163,Interrupt Processor Targets Register 163" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO655 ,CPU Targets Byte Offset 655 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO654 ,CPU Targets Byte Offset 654 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO653 ,CPU Targets Byte Offset 653 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO652 ,CPU Targets Byte Offset 652 " group.long 0xA90++0x03 line.long 0x00 "GICD_ITARGETSR164,Interrupt Processor Targets Register 164" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO659 ,CPU Targets Byte Offset 659 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO658 ,CPU Targets Byte Offset 658 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO657 ,CPU Targets Byte Offset 657 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO656 ,CPU Targets Byte Offset 656 " group.long 0xA94++0x03 line.long 0x00 "GICD_ITARGETSR165,Interrupt Processor Targets Register 165" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO663 ,CPU Targets Byte Offset 663 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO662 ,CPU Targets Byte Offset 662 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO661 ,CPU Targets Byte Offset 661 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO660 ,CPU Targets Byte Offset 660 " group.long 0xA98++0x03 line.long 0x00 "GICD_ITARGETSR166,Interrupt Processor Targets Register 166" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO667 ,CPU Targets Byte Offset 667 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO666 ,CPU Targets Byte Offset 666 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO665 ,CPU Targets Byte Offset 665 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO664 ,CPU Targets Byte Offset 664 " group.long 0xA9C++0x03 line.long 0x00 "GICD_ITARGETSR167,Interrupt Processor Targets Register 167" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO671 ,CPU Targets Byte Offset 671 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO670 ,CPU Targets Byte Offset 670 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO669 ,CPU Targets Byte Offset 669 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO668 ,CPU Targets Byte Offset 668 " else rgroup.long 0xA80++0x03 line.long 0x00 "GICD_ITARGETSR160,Interrupt Processor Targets Register 160" rgroup.long 0xA84++0x03 line.long 0x00 "GICD_ITARGETSR161,Interrupt Processor Targets Register 161" rgroup.long 0xA88++0x03 line.long 0x00 "GICD_ITARGETSR162,Interrupt Processor Targets Register 162" rgroup.long 0xA8C++0x03 line.long 0x00 "GICD_ITARGETSR163,Interrupt Processor Targets Register 163" rgroup.long 0xA90++0x03 line.long 0x00 "GICD_ITARGETSR164,Interrupt Processor Targets Register 164" rgroup.long 0xA94++0x03 line.long 0x00 "GICD_ITARGETSR165,Interrupt Processor Targets Register 165" rgroup.long 0xA98++0x03 line.long 0x00 "GICD_ITARGETSR166,Interrupt Processor Targets Register 166" rgroup.long 0xA9C++0x03 line.long 0x00 "GICD_ITARGETSR167,Interrupt Processor Targets Register 167" endif if (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x15) group.long 0xAA0++0x03 line.long 0x00 "GICD_ITARGETSR168,Interrupt Processor Targets Register 168" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO675 ,CPU Targets Byte Offset 675 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO674 ,CPU Targets Byte Offset 674 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO673 ,CPU Targets Byte Offset 673 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO672 ,CPU Targets Byte Offset 672 " group.long 0xAA4++0x03 line.long 0x00 "GICD_ITARGETSR169,Interrupt Processor Targets Register 169" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO679 ,CPU Targets Byte Offset 679 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO678 ,CPU Targets Byte Offset 678 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO677 ,CPU Targets Byte Offset 677 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO676 ,CPU Targets Byte Offset 676 " group.long 0xAA8++0x03 line.long 0x00 "GICD_ITARGETSR170,Interrupt Processor Targets Register 170" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO683 ,CPU Targets Byte Offset 683 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO682 ,CPU Targets Byte Offset 682 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO681 ,CPU Targets Byte Offset 681 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO680 ,CPU Targets Byte Offset 680 " group.long 0xAAC++0x03 line.long 0x00 "GICD_ITARGETSR171,Interrupt Processor Targets Register 171" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO687 ,CPU Targets Byte Offset 687 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO686 ,CPU Targets Byte Offset 686 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO685 ,CPU Targets Byte Offset 685 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO684 ,CPU Targets Byte Offset 684 " group.long 0xAB0++0x03 line.long 0x00 "GICD_ITARGETSR172,Interrupt Processor Targets Register 172" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO691 ,CPU Targets Byte Offset 691 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO690 ,CPU Targets Byte Offset 690 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO689 ,CPU Targets Byte Offset 689 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO688 ,CPU Targets Byte Offset 688 " group.long 0xAB4++0x03 line.long 0x00 "GICD_ITARGETSR173,Interrupt Processor Targets Register 173" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO695 ,CPU Targets Byte Offset 695 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO694 ,CPU Targets Byte Offset 694 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO693 ,CPU Targets Byte Offset 693 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO692 ,CPU Targets Byte Offset 692 " group.long 0xAB8++0x03 line.long 0x00 "GICD_ITARGETSR174,Interrupt Processor Targets Register 174" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO699 ,CPU Targets Byte Offset 699 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO698 ,CPU Targets Byte Offset 698 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO697 ,CPU Targets Byte Offset 697 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO696 ,CPU Targets Byte Offset 696 " group.long 0xABC++0x03 line.long 0x00 "GICD_ITARGETSR175,Interrupt Processor Targets Register 175" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO703 ,CPU Targets Byte Offset 703 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO702 ,CPU Targets Byte Offset 702 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO701 ,CPU Targets Byte Offset 701 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO700 ,CPU Targets Byte Offset 700 " else rgroup.long 0xAA0++0x03 line.long 0x00 "GICD_ITARGETSR168,Interrupt Processor Targets Register 168" rgroup.long 0xAA4++0x03 line.long 0x00 "GICD_ITARGETSR169,Interrupt Processor Targets Register 169" rgroup.long 0xAA8++0x03 line.long 0x00 "GICD_ITARGETSR170,Interrupt Processor Targets Register 170" rgroup.long 0xAAC++0x03 line.long 0x00 "GICD_ITARGETSR171,Interrupt Processor Targets Register 171" rgroup.long 0xAB0++0x03 line.long 0x00 "GICD_ITARGETSR172,Interrupt Processor Targets Register 172" rgroup.long 0xAB4++0x03 line.long 0x00 "GICD_ITARGETSR173,Interrupt Processor Targets Register 173" rgroup.long 0xAB8++0x03 line.long 0x00 "GICD_ITARGETSR174,Interrupt Processor Targets Register 174" rgroup.long 0xABC++0x03 line.long 0x00 "GICD_ITARGETSR175,Interrupt Processor Targets Register 175" endif if (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x16) group.long 0xAC0++0x03 line.long 0x00 "GICD_ITARGETSR176,Interrupt Processor Targets Register 176" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO707 ,CPU Targets Byte Offset 707 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO706 ,CPU Targets Byte Offset 706 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO705 ,CPU Targets Byte Offset 705 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO704 ,CPU Targets Byte Offset 704 " group.long 0xAC4++0x03 line.long 0x00 "GICD_ITARGETSR177,Interrupt Processor Targets Register 177" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO711 ,CPU Targets Byte Offset 711 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO710 ,CPU Targets Byte Offset 710 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO709 ,CPU Targets Byte Offset 709 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO708 ,CPU Targets Byte Offset 708 " group.long 0xAC8++0x03 line.long 0x00 "GICD_ITARGETSR178,Interrupt Processor Targets Register 178" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO715 ,CPU Targets Byte Offset 715 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO714 ,CPU Targets Byte Offset 714 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO713 ,CPU Targets Byte Offset 713 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO712 ,CPU Targets Byte Offset 712 " group.long 0xACC++0x03 line.long 0x00 "GICD_ITARGETSR179,Interrupt Processor Targets Register 179" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO719 ,CPU Targets Byte Offset 719 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO718 ,CPU Targets Byte Offset 718 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO717 ,CPU Targets Byte Offset 717 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO716 ,CPU Targets Byte Offset 716 " group.long 0xAD0++0x03 line.long 0x00 "GICD_ITARGETSR180,Interrupt Processor Targets Register 180" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO723 ,CPU Targets Byte Offset 723 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO722 ,CPU Targets Byte Offset 722 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO721 ,CPU Targets Byte Offset 721 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO720 ,CPU Targets Byte Offset 720 " group.long 0xAD4++0x03 line.long 0x00 "GICD_ITARGETSR181,Interrupt Processor Targets Register 181" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO727 ,CPU Targets Byte Offset 727 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO726 ,CPU Targets Byte Offset 726 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO725 ,CPU Targets Byte Offset 725 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO724 ,CPU Targets Byte Offset 724 " group.long 0xAD8++0x03 line.long 0x00 "GICD_ITARGETSR182,Interrupt Processor Targets Register 182" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO731 ,CPU Targets Byte Offset 731 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO730 ,CPU Targets Byte Offset 730 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO729 ,CPU Targets Byte Offset 729 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO728 ,CPU Targets Byte Offset 728 " group.long 0xADC++0x03 line.long 0x00 "GICD_ITARGETSR183,Interrupt Processor Targets Register 183" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO735 ,CPU Targets Byte Offset 735 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO734 ,CPU Targets Byte Offset 734 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO733 ,CPU Targets Byte Offset 733 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO732 ,CPU Targets Byte Offset 732 " else rgroup.long 0xAC0++0x03 line.long 0x00 "GICD_ITARGETSR176,Interrupt Processor Targets Register 176" rgroup.long 0xAC4++0x03 line.long 0x00 "GICD_ITARGETSR177,Interrupt Processor Targets Register 177" rgroup.long 0xAC8++0x03 line.long 0x00 "GICD_ITARGETSR178,Interrupt Processor Targets Register 178" rgroup.long 0xACC++0x03 line.long 0x00 "GICD_ITARGETSR179,Interrupt Processor Targets Register 179" rgroup.long 0xAD0++0x03 line.long 0x00 "GICD_ITARGETSR180,Interrupt Processor Targets Register 180" rgroup.long 0xAD4++0x03 line.long 0x00 "GICD_ITARGETSR181,Interrupt Processor Targets Register 181" rgroup.long 0xAD8++0x03 line.long 0x00 "GICD_ITARGETSR182,Interrupt Processor Targets Register 182" rgroup.long 0xADC++0x03 line.long 0x00 "GICD_ITARGETSR183,Interrupt Processor Targets Register 183" endif if (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x17) group.long 0xAE0++0x03 line.long 0x00 "GICD_ITARGETSR184,Interrupt Processor Targets Register 184" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO739 ,CPU Targets Byte Offset 739 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO738 ,CPU Targets Byte Offset 738 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO737 ,CPU Targets Byte Offset 737 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO736 ,CPU Targets Byte Offset 736 " group.long 0xAE4++0x03 line.long 0x00 "GICD_ITARGETSR185,Interrupt Processor Targets Register 185" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO743 ,CPU Targets Byte Offset 743 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO742 ,CPU Targets Byte Offset 742 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO741 ,CPU Targets Byte Offset 741 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO740 ,CPU Targets Byte Offset 740 " group.long 0xAE8++0x03 line.long 0x00 "GICD_ITARGETSR186,Interrupt Processor Targets Register 186" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO747 ,CPU Targets Byte Offset 747 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO746 ,CPU Targets Byte Offset 746 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO745 ,CPU Targets Byte Offset 745 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO744 ,CPU Targets Byte Offset 744 " group.long 0xAEC++0x03 line.long 0x00 "GICD_ITARGETSR187,Interrupt Processor Targets Register 187" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO751 ,CPU Targets Byte Offset 751 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO750 ,CPU Targets Byte Offset 750 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO749 ,CPU Targets Byte Offset 749 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO748 ,CPU Targets Byte Offset 748 " group.long 0xAF0++0x03 line.long 0x00 "GICD_ITARGETSR188,Interrupt Processor Targets Register 188" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO755 ,CPU Targets Byte Offset 755 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO754 ,CPU Targets Byte Offset 754 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO753 ,CPU Targets Byte Offset 753 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO752 ,CPU Targets Byte Offset 752 " group.long 0xAF4++0x03 line.long 0x00 "GICD_ITARGETSR189,Interrupt Processor Targets Register 189" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO759 ,CPU Targets Byte Offset 759 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO758 ,CPU Targets Byte Offset 758 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO757 ,CPU Targets Byte Offset 757 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO756 ,CPU Targets Byte Offset 756 " group.long 0xAF8++0x03 line.long 0x00 "GICD_ITARGETSR190,Interrupt Processor Targets Register 190" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO763 ,CPU Targets Byte Offset 763 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO762 ,CPU Targets Byte Offset 762 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO761 ,CPU Targets Byte Offset 761 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO760 ,CPU Targets Byte Offset 760 " group.long 0xAFC++0x03 line.long 0x00 "GICD_ITARGETSR191,Interrupt Processor Targets Register 191" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO767 ,CPU Targets Byte Offset 767 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO766 ,CPU Targets Byte Offset 766 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO765 ,CPU Targets Byte Offset 765 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO764 ,CPU Targets Byte Offset 764 " else rgroup.long 0xAE0++0x03 line.long 0x00 "GICD_ITARGETSR184,Interrupt Processor Targets Register 184" rgroup.long 0xAE4++0x03 line.long 0x00 "GICD_ITARGETSR185,Interrupt Processor Targets Register 185" rgroup.long 0xAE8++0x03 line.long 0x00 "GICD_ITARGETSR186,Interrupt Processor Targets Register 186" rgroup.long 0xAEC++0x03 line.long 0x00 "GICD_ITARGETSR187,Interrupt Processor Targets Register 187" rgroup.long 0xAF0++0x03 line.long 0x00 "GICD_ITARGETSR188,Interrupt Processor Targets Register 188" rgroup.long 0xAF4++0x03 line.long 0x00 "GICD_ITARGETSR189,Interrupt Processor Targets Register 189" rgroup.long 0xAF8++0x03 line.long 0x00 "GICD_ITARGETSR190,Interrupt Processor Targets Register 190" rgroup.long 0xAFC++0x03 line.long 0x00 "GICD_ITARGETSR191,Interrupt Processor Targets Register 191" endif if (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x18) group.long 0xB00++0x03 line.long 0x00 "GICD_ITARGETSR192,Interrupt Processor Targets Register 192" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO771 ,CPU Targets Byte Offset 771 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO770 ,CPU Targets Byte Offset 770 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO769 ,CPU Targets Byte Offset 769 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO768 ,CPU Targets Byte Offset 768 " group.long 0xB04++0x03 line.long 0x00 "GICD_ITARGETSR193,Interrupt Processor Targets Register 193" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO775 ,CPU Targets Byte Offset 775 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO774 ,CPU Targets Byte Offset 774 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO773 ,CPU Targets Byte Offset 773 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO772 ,CPU Targets Byte Offset 772 " group.long 0xB08++0x03 line.long 0x00 "GICD_ITARGETSR194,Interrupt Processor Targets Register 194" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO779 ,CPU Targets Byte Offset 779 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO778 ,CPU Targets Byte Offset 778 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO777 ,CPU Targets Byte Offset 777 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO776 ,CPU Targets Byte Offset 776 " group.long 0xB0C++0x03 line.long 0x00 "GICD_ITARGETSR195,Interrupt Processor Targets Register 195" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO783 ,CPU Targets Byte Offset 783 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO782 ,CPU Targets Byte Offset 782 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO781 ,CPU Targets Byte Offset 781 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO780 ,CPU Targets Byte Offset 780 " group.long 0xB10++0x03 line.long 0x00 "GICD_ITARGETSR196,Interrupt Processor Targets Register 196" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO787 ,CPU Targets Byte Offset 787 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO786 ,CPU Targets Byte Offset 786 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO785 ,CPU Targets Byte Offset 785 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO784 ,CPU Targets Byte Offset 784 " group.long 0xB14++0x03 line.long 0x00 "GICD_ITARGETSR197,Interrupt Processor Targets Register 197" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO791 ,CPU Targets Byte Offset 791 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO790 ,CPU Targets Byte Offset 790 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO789 ,CPU Targets Byte Offset 789 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO788 ,CPU Targets Byte Offset 788 " group.long 0xB18++0x03 line.long 0x00 "GICD_ITARGETSR198,Interrupt Processor Targets Register 198" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO795 ,CPU Targets Byte Offset 795 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO794 ,CPU Targets Byte Offset 794 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO793 ,CPU Targets Byte Offset 793 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO792 ,CPU Targets Byte Offset 792 " group.long 0xB1C++0x03 line.long 0x00 "GICD_ITARGETSR199,Interrupt Processor Targets Register 199" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO799 ,CPU Targets Byte Offset 799 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO798 ,CPU Targets Byte Offset 798 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO797 ,CPU Targets Byte Offset 797 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO796 ,CPU Targets Byte Offset 796 " else rgroup.long 0xB00++0x03 line.long 0x00 "GICD_ITARGETSR192,Interrupt Processor Targets Register 192" rgroup.long 0xB04++0x03 line.long 0x00 "GICD_ITARGETSR193,Interrupt Processor Targets Register 193" rgroup.long 0xB08++0x03 line.long 0x00 "GICD_ITARGETSR194,Interrupt Processor Targets Register 194" rgroup.long 0xB0C++0x03 line.long 0x00 "GICD_ITARGETSR195,Interrupt Processor Targets Register 195" rgroup.long 0xB10++0x03 line.long 0x00 "GICD_ITARGETSR196,Interrupt Processor Targets Register 196" rgroup.long 0xB14++0x03 line.long 0x00 "GICD_ITARGETSR197,Interrupt Processor Targets Register 197" rgroup.long 0xB18++0x03 line.long 0x00 "GICD_ITARGETSR198,Interrupt Processor Targets Register 198" rgroup.long 0xB1C++0x03 line.long 0x00 "GICD_ITARGETSR199,Interrupt Processor Targets Register 199" endif if (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x19) group.long 0xB20++0x03 line.long 0x00 "GICD_ITARGETSR200,Interrupt Processor Targets Register 200" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO803 ,CPU Targets Byte Offset 803 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO802 ,CPU Targets Byte Offset 802 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO801 ,CPU Targets Byte Offset 801 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO800 ,CPU Targets Byte Offset 800 " group.long 0xB24++0x03 line.long 0x00 "GICD_ITARGETSR201,Interrupt Processor Targets Register 201" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO807 ,CPU Targets Byte Offset 807 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO806 ,CPU Targets Byte Offset 806 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO805 ,CPU Targets Byte Offset 805 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO804 ,CPU Targets Byte Offset 804 " group.long 0xB28++0x03 line.long 0x00 "GICD_ITARGETSR202,Interrupt Processor Targets Register 202" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO811 ,CPU Targets Byte Offset 811 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO810 ,CPU Targets Byte Offset 810 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO809 ,CPU Targets Byte Offset 809 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO808 ,CPU Targets Byte Offset 808 " group.long 0xB2C++0x03 line.long 0x00 "GICD_ITARGETSR203,Interrupt Processor Targets Register 203" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO815 ,CPU Targets Byte Offset 815 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO814 ,CPU Targets Byte Offset 814 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO813 ,CPU Targets Byte Offset 813 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO812 ,CPU Targets Byte Offset 812 " group.long 0xB30++0x03 line.long 0x00 "GICD_ITARGETSR204,Interrupt Processor Targets Register 204" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO819 ,CPU Targets Byte Offset 819 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO818 ,CPU Targets Byte Offset 818 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO817 ,CPU Targets Byte Offset 817 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO816 ,CPU Targets Byte Offset 816 " group.long 0xB34++0x03 line.long 0x00 "GICD_ITARGETSR205,Interrupt Processor Targets Register 205" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO823 ,CPU Targets Byte Offset 823 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO822 ,CPU Targets Byte Offset 822 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO821 ,CPU Targets Byte Offset 821 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO820 ,CPU Targets Byte Offset 820 " group.long 0xB38++0x03 line.long 0x00 "GICD_ITARGETSR206,Interrupt Processor Targets Register 206" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO827 ,CPU Targets Byte Offset 827 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO826 ,CPU Targets Byte Offset 826 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO825 ,CPU Targets Byte Offset 825 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO824 ,CPU Targets Byte Offset 824 " group.long 0xB3C++0x03 line.long 0x00 "GICD_ITARGETSR207,Interrupt Processor Targets Register 207" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO831 ,CPU Targets Byte Offset 831 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO830 ,CPU Targets Byte Offset 830 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO829 ,CPU Targets Byte Offset 829 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO828 ,CPU Targets Byte Offset 828 " else rgroup.long 0xB20++0x03 line.long 0x00 "GICD_ITARGETSR200,Interrupt Processor Targets Register 200" rgroup.long 0xB24++0x03 line.long 0x00 "GICD_ITARGETSR201,Interrupt Processor Targets Register 201" rgroup.long 0xB28++0x03 line.long 0x00 "GICD_ITARGETSR202,Interrupt Processor Targets Register 202" rgroup.long 0xB2C++0x03 line.long 0x00 "GICD_ITARGETSR203,Interrupt Processor Targets Register 203" rgroup.long 0xB30++0x03 line.long 0x00 "GICD_ITARGETSR204,Interrupt Processor Targets Register 204" rgroup.long 0xB34++0x03 line.long 0x00 "GICD_ITARGETSR205,Interrupt Processor Targets Register 205" rgroup.long 0xB38++0x03 line.long 0x00 "GICD_ITARGETSR206,Interrupt Processor Targets Register 206" rgroup.long 0xB3C++0x03 line.long 0x00 "GICD_ITARGETSR207,Interrupt Processor Targets Register 207" endif if (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x1A) group.long 0xB40++0x03 line.long 0x00 "GICD_ITARGETSR208,Interrupt Processor Targets Register 208" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO835 ,CPU Targets Byte Offset 835 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO834 ,CPU Targets Byte Offset 834 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO833 ,CPU Targets Byte Offset 833 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO832 ,CPU Targets Byte Offset 832 " group.long 0xB44++0x03 line.long 0x00 "GICD_ITARGETSR209,Interrupt Processor Targets Register 209" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO839 ,CPU Targets Byte Offset 839 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO838 ,CPU Targets Byte Offset 838 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO837 ,CPU Targets Byte Offset 837 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO836 ,CPU Targets Byte Offset 836 " group.long 0xB48++0x03 line.long 0x00 "GICD_ITARGETSR210,Interrupt Processor Targets Register 210" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO843 ,CPU Targets Byte Offset 843 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO842 ,CPU Targets Byte Offset 842 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO841 ,CPU Targets Byte Offset 841 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO840 ,CPU Targets Byte Offset 840 " group.long 0xB4C++0x03 line.long 0x00 "GICD_ITARGETSR211,Interrupt Processor Targets Register 211" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO847 ,CPU Targets Byte Offset 847 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO846 ,CPU Targets Byte Offset 846 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO845 ,CPU Targets Byte Offset 845 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO844 ,CPU Targets Byte Offset 844 " group.long 0xB50++0x03 line.long 0x00 "GICD_ITARGETSR212,Interrupt Processor Targets Register 212" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO851 ,CPU Targets Byte Offset 851 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO850 ,CPU Targets Byte Offset 850 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO849 ,CPU Targets Byte Offset 849 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO848 ,CPU Targets Byte Offset 848 " group.long 0xB54++0x03 line.long 0x00 "GICD_ITARGETSR213,Interrupt Processor Targets Register 213" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO855 ,CPU Targets Byte Offset 855 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO854 ,CPU Targets Byte Offset 854 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO853 ,CPU Targets Byte Offset 853 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO852 ,CPU Targets Byte Offset 852 " group.long 0xB58++0x03 line.long 0x00 "GICD_ITARGETSR214,Interrupt Processor Targets Register 214" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO859 ,CPU Targets Byte Offset 859 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO858 ,CPU Targets Byte Offset 858 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO857 ,CPU Targets Byte Offset 857 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO856 ,CPU Targets Byte Offset 856 " group.long 0xB5C++0x03 line.long 0x00 "GICD_ITARGETSR215,Interrupt Processor Targets Register 215" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO863 ,CPU Targets Byte Offset 863 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO862 ,CPU Targets Byte Offset 862 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO861 ,CPU Targets Byte Offset 861 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO860 ,CPU Targets Byte Offset 860 " else rgroup.long 0xB40++0x03 line.long 0x00 "GICD_ITARGETSR208,Interrupt Processor Targets Register 208" rgroup.long 0xB44++0x03 line.long 0x00 "GICD_ITARGETSR209,Interrupt Processor Targets Register 209" rgroup.long 0xB48++0x03 line.long 0x00 "GICD_ITARGETSR210,Interrupt Processor Targets Register 210" rgroup.long 0xB4C++0x03 line.long 0x00 "GICD_ITARGETSR211,Interrupt Processor Targets Register 211" rgroup.long 0xB50++0x03 line.long 0x00 "GICD_ITARGETSR212,Interrupt Processor Targets Register 212" rgroup.long 0xB54++0x03 line.long 0x00 "GICD_ITARGETSR213,Interrupt Processor Targets Register 213" rgroup.long 0xB58++0x03 line.long 0x00 "GICD_ITARGETSR214,Interrupt Processor Targets Register 214" rgroup.long 0xB5C++0x03 line.long 0x00 "GICD_ITARGETSR215,Interrupt Processor Targets Register 215" endif if (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x1B) group.long 0xB60++0x03 line.long 0x00 "GICD_ITARGETSR216,Interrupt Processor Targets Register 216" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO867 ,CPU Targets Byte Offset 867 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO866 ,CPU Targets Byte Offset 866 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO865 ,CPU Targets Byte Offset 865 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO864 ,CPU Targets Byte Offset 864 " group.long 0xB64++0x03 line.long 0x00 "GICD_ITARGETSR217,Interrupt Processor Targets Register 217" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO871 ,CPU Targets Byte Offset 871 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO870 ,CPU Targets Byte Offset 870 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO869 ,CPU Targets Byte Offset 869 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO868 ,CPU Targets Byte Offset 868 " group.long 0xB68++0x03 line.long 0x00 "GICD_ITARGETSR218,Interrupt Processor Targets Register 218" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO875 ,CPU Targets Byte Offset 875 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO874 ,CPU Targets Byte Offset 874 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO873 ,CPU Targets Byte Offset 873 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO872 ,CPU Targets Byte Offset 872 " group.long 0xB6C++0x03 line.long 0x00 "GICD_ITARGETSR219,Interrupt Processor Targets Register 219" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO879 ,CPU Targets Byte Offset 879 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO878 ,CPU Targets Byte Offset 878 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO877 ,CPU Targets Byte Offset 877 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO876 ,CPU Targets Byte Offset 876 " group.long 0xB70++0x03 line.long 0x00 "GICD_ITARGETSR220,Interrupt Processor Targets Register 220" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO883 ,CPU Targets Byte Offset 883 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO882 ,CPU Targets Byte Offset 882 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO881 ,CPU Targets Byte Offset 881 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO880 ,CPU Targets Byte Offset 880 " group.long 0xB74++0x03 line.long 0x00 "GICD_ITARGETSR221,Interrupt Processor Targets Register 221" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO887 ,CPU Targets Byte Offset 887 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO886 ,CPU Targets Byte Offset 886 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO885 ,CPU Targets Byte Offset 885 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO884 ,CPU Targets Byte Offset 884 " group.long 0xB78++0x03 line.long 0x00 "GICD_ITARGETSR222,Interrupt Processor Targets Register 222" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO891 ,CPU Targets Byte Offset 891 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO890 ,CPU Targets Byte Offset 890 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO889 ,CPU Targets Byte Offset 889 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO888 ,CPU Targets Byte Offset 888 " group.long 0xB7C++0x03 line.long 0x00 "GICD_ITARGETSR223,Interrupt Processor Targets Register 223" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO895 ,CPU Targets Byte Offset 895 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO894 ,CPU Targets Byte Offset 894 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO893 ,CPU Targets Byte Offset 893 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO892 ,CPU Targets Byte Offset 892 " else rgroup.long 0xB60++0x03 line.long 0x00 "GICD_ITARGETSR216,Interrupt Processor Targets Register 216" rgroup.long 0xB64++0x03 line.long 0x00 "GICD_ITARGETSR217,Interrupt Processor Targets Register 217" rgroup.long 0xB68++0x03 line.long 0x00 "GICD_ITARGETSR218,Interrupt Processor Targets Register 218" rgroup.long 0xB6C++0x03 line.long 0x00 "GICD_ITARGETSR219,Interrupt Processor Targets Register 219" rgroup.long 0xB70++0x03 line.long 0x00 "GICD_ITARGETSR220,Interrupt Processor Targets Register 220" rgroup.long 0xB74++0x03 line.long 0x00 "GICD_ITARGETSR221,Interrupt Processor Targets Register 221" rgroup.long 0xB78++0x03 line.long 0x00 "GICD_ITARGETSR222,Interrupt Processor Targets Register 222" rgroup.long 0xB7C++0x03 line.long 0x00 "GICD_ITARGETSR223,Interrupt Processor Targets Register 223" endif if (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x1C) group.long 0xB80++0x03 line.long 0x00 "GICD_ITARGETSR224,Interrupt Processor Targets Register 224" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO899 ,CPU Targets Byte Offset 899 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO898 ,CPU Targets Byte Offset 898 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO897 ,CPU Targets Byte Offset 897 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO896 ,CPU Targets Byte Offset 896 " group.long 0xB84++0x03 line.long 0x00 "GICD_ITARGETSR225,Interrupt Processor Targets Register 225" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO903 ,CPU Targets Byte Offset 903 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO902 ,CPU Targets Byte Offset 902 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO901 ,CPU Targets Byte Offset 901 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO900 ,CPU Targets Byte Offset 900 " group.long 0xB88++0x03 line.long 0x00 "GICD_ITARGETSR226,Interrupt Processor Targets Register 226" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO907 ,CPU Targets Byte Offset 907 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO906 ,CPU Targets Byte Offset 906 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO905 ,CPU Targets Byte Offset 905 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO904 ,CPU Targets Byte Offset 904 " group.long 0xB8C++0x03 line.long 0x00 "GICD_ITARGETSR227,Interrupt Processor Targets Register 227" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO911 ,CPU Targets Byte Offset 911 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO910 ,CPU Targets Byte Offset 910 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO909 ,CPU Targets Byte Offset 909 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO908 ,CPU Targets Byte Offset 908 " group.long 0xB90++0x03 line.long 0x00 "GICD_ITARGETSR228,Interrupt Processor Targets Register 228" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO915 ,CPU Targets Byte Offset 915 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO914 ,CPU Targets Byte Offset 914 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO913 ,CPU Targets Byte Offset 913 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO912 ,CPU Targets Byte Offset 912 " group.long 0xB94++0x03 line.long 0x00 "GICD_ITARGETSR229,Interrupt Processor Targets Register 229" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO919 ,CPU Targets Byte Offset 919 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO918 ,CPU Targets Byte Offset 918 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO917 ,CPU Targets Byte Offset 917 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO916 ,CPU Targets Byte Offset 916 " group.long 0xB98++0x03 line.long 0x00 "GICD_ITARGETSR230,Interrupt Processor Targets Register 230" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO923 ,CPU Targets Byte Offset 923 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO922 ,CPU Targets Byte Offset 922 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO921 ,CPU Targets Byte Offset 921 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO920 ,CPU Targets Byte Offset 920 " group.long 0xB9C++0x03 line.long 0x00 "GICD_ITARGETSR231,Interrupt Processor Targets Register 231" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO927 ,CPU Targets Byte Offset 927 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO926 ,CPU Targets Byte Offset 926 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO925 ,CPU Targets Byte Offset 925 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO924 ,CPU Targets Byte Offset 924 " else rgroup.long 0xB80++0x03 line.long 0x00 "GICD_ITARGETSR224,Interrupt Processor Targets Register 224" rgroup.long 0xB84++0x03 line.long 0x00 "GICD_ITARGETSR225,Interrupt Processor Targets Register 225" rgroup.long 0xB88++0x03 line.long 0x00 "GICD_ITARGETSR226,Interrupt Processor Targets Register 226" rgroup.long 0xB8C++0x03 line.long 0x00 "GICD_ITARGETSR227,Interrupt Processor Targets Register 227" rgroup.long 0xB90++0x03 line.long 0x00 "GICD_ITARGETSR228,Interrupt Processor Targets Register 228" rgroup.long 0xB94++0x03 line.long 0x00 "GICD_ITARGETSR229,Interrupt Processor Targets Register 229" rgroup.long 0xB98++0x03 line.long 0x00 "GICD_ITARGETSR230,Interrupt Processor Targets Register 230" rgroup.long 0xB9C++0x03 line.long 0x00 "GICD_ITARGETSR231,Interrupt Processor Targets Register 231" endif if (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x1D) group.long 0xBA0++0x03 line.long 0x00 "GICD_ITARGETSR232,Interrupt Processor Targets Register 232" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO931 ,CPU Targets Byte Offset 931 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO930 ,CPU Targets Byte Offset 930 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO929 ,CPU Targets Byte Offset 929 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO928 ,CPU Targets Byte Offset 928 " group.long 0xBA4++0x03 line.long 0x00 "GICD_ITARGETSR233,Interrupt Processor Targets Register 233" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO935 ,CPU Targets Byte Offset 935 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO934 ,CPU Targets Byte Offset 934 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO933 ,CPU Targets Byte Offset 933 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO932 ,CPU Targets Byte Offset 932 " group.long 0xBA8++0x03 line.long 0x00 "GICD_ITARGETSR234,Interrupt Processor Targets Register 234" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO939 ,CPU Targets Byte Offset 939 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO938 ,CPU Targets Byte Offset 938 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO937 ,CPU Targets Byte Offset 937 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO936 ,CPU Targets Byte Offset 936 " group.long 0xBAC++0x03 line.long 0x00 "GICD_ITARGETSR235,Interrupt Processor Targets Register 235" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO943 ,CPU Targets Byte Offset 943 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO942 ,CPU Targets Byte Offset 942 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO941 ,CPU Targets Byte Offset 941 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO940 ,CPU Targets Byte Offset 940 " group.long 0xBB0++0x03 line.long 0x00 "GICD_ITARGETSR236,Interrupt Processor Targets Register 236" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO947 ,CPU Targets Byte Offset 947 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO946 ,CPU Targets Byte Offset 946 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO945 ,CPU Targets Byte Offset 945 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO944 ,CPU Targets Byte Offset 944 " group.long 0xBB4++0x03 line.long 0x00 "GICD_ITARGETSR237,Interrupt Processor Targets Register 237" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO951 ,CPU Targets Byte Offset 951 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO950 ,CPU Targets Byte Offset 950 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO949 ,CPU Targets Byte Offset 949 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO948 ,CPU Targets Byte Offset 948 " group.long 0xBB8++0x03 line.long 0x00 "GICD_ITARGETSR238,Interrupt Processor Targets Register 238" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO955 ,CPU Targets Byte Offset 955 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO954 ,CPU Targets Byte Offset 954 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO953 ,CPU Targets Byte Offset 953 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO952 ,CPU Targets Byte Offset 952 " group.long 0xBBC++0x03 line.long 0x00 "GICD_ITARGETSR239,Interrupt Processor Targets Register 239" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO959 ,CPU Targets Byte Offset 959 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO958 ,CPU Targets Byte Offset 958 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO957 ,CPU Targets Byte Offset 957 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO956 ,CPU Targets Byte Offset 956 " else rgroup.long 0xBA0++0x03 line.long 0x00 "GICD_ITARGETSR232,Interrupt Processor Targets Register 232" rgroup.long 0xBA4++0x03 line.long 0x00 "GICD_ITARGETSR233,Interrupt Processor Targets Register 233" rgroup.long 0xBA8++0x03 line.long 0x00 "GICD_ITARGETSR234,Interrupt Processor Targets Register 234" rgroup.long 0xBAC++0x03 line.long 0x00 "GICD_ITARGETSR235,Interrupt Processor Targets Register 235" rgroup.long 0xBB0++0x03 line.long 0x00 "GICD_ITARGETSR236,Interrupt Processor Targets Register 236" rgroup.long 0xBB4++0x03 line.long 0x00 "GICD_ITARGETSR237,Interrupt Processor Targets Register 237" rgroup.long 0xBB8++0x03 line.long 0x00 "GICD_ITARGETSR238,Interrupt Processor Targets Register 238" rgroup.long 0xBBC++0x03 line.long 0x00 "GICD_ITARGETSR239,Interrupt Processor Targets Register 239" endif if (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x1E) group.long 0xBC0++0x03 line.long 0x00 "GICD_ITARGETSR240,Interrupt Processor Targets Register 240" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO963 ,CPU Targets Byte Offset 963 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO962 ,CPU Targets Byte Offset 962 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO961 ,CPU Targets Byte Offset 961 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO960 ,CPU Targets Byte Offset 960 " group.long 0xBC4++0x03 line.long 0x00 "GICD_ITARGETSR241,Interrupt Processor Targets Register 241" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO967 ,CPU Targets Byte Offset 967 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO966 ,CPU Targets Byte Offset 966 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO965 ,CPU Targets Byte Offset 965 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO964 ,CPU Targets Byte Offset 964 " group.long 0xBC8++0x03 line.long 0x00 "GICD_ITARGETSR242,Interrupt Processor Targets Register 242" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO971 ,CPU Targets Byte Offset 971 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO970 ,CPU Targets Byte Offset 970 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO969 ,CPU Targets Byte Offset 969 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO968 ,CPU Targets Byte Offset 968 " group.long 0xBCC++0x03 line.long 0x00 "GICD_ITARGETSR243,Interrupt Processor Targets Register 243" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO975 ,CPU Targets Byte Offset 975 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO974 ,CPU Targets Byte Offset 974 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO973 ,CPU Targets Byte Offset 973 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO972 ,CPU Targets Byte Offset 972 " group.long 0xBD0++0x03 line.long 0x00 "GICD_ITARGETSR244,Interrupt Processor Targets Register 244" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO979 ,CPU Targets Byte Offset 979 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO978 ,CPU Targets Byte Offset 978 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO977 ,CPU Targets Byte Offset 977 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO976 ,CPU Targets Byte Offset 976 " group.long 0xBD4++0x03 line.long 0x00 "GICD_ITARGETSR245,Interrupt Processor Targets Register 245" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO983 ,CPU Targets Byte Offset 983 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO982 ,CPU Targets Byte Offset 982 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO981 ,CPU Targets Byte Offset 981 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO980 ,CPU Targets Byte Offset 980 " group.long 0xBD8++0x03 line.long 0x00 "GICD_ITARGETSR246,Interrupt Processor Targets Register 246" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO987 ,CPU Targets Byte Offset 987 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO986 ,CPU Targets Byte Offset 986 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO985 ,CPU Targets Byte Offset 985 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO984 ,CPU Targets Byte Offset 984 " group.long 0xBDC++0x03 line.long 0x00 "GICD_ITARGETSR247,Interrupt Processor Targets Register 247" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO991 ,CPU Targets Byte Offset 991 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO990 ,CPU Targets Byte Offset 990 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO989 ,CPU Targets Byte Offset 989 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO988 ,CPU Targets Byte Offset 988 " else rgroup.long 0xBC0++0x03 line.long 0x00 "GICD_ITARGETSR240,Interrupt Processor Targets Register 240" rgroup.long 0xBC4++0x03 line.long 0x00 "GICD_ITARGETSR241,Interrupt Processor Targets Register 241" rgroup.long 0xBC8++0x03 line.long 0x00 "GICD_ITARGETSR242,Interrupt Processor Targets Register 242" rgroup.long 0xBCC++0x03 line.long 0x00 "GICD_ITARGETSR243,Interrupt Processor Targets Register 243" rgroup.long 0xBD0++0x03 line.long 0x00 "GICD_ITARGETSR244,Interrupt Processor Targets Register 244" rgroup.long 0xBD4++0x03 line.long 0x00 "GICD_ITARGETSR245,Interrupt Processor Targets Register 245" rgroup.long 0xBD8++0x03 line.long 0x00 "GICD_ITARGETSR246,Interrupt Processor Targets Register 246" rgroup.long 0xBDC++0x03 line.long 0x00 "GICD_ITARGETSR247,Interrupt Processor Targets Register 247" endif if (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x1F) group.long 0xBE0++0x03 line.long 0x00 "GICD_ITARGETSR248,Interrupt Processor Targets Register 248" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO995 ,CPU Targets Byte Offset 995 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO994 ,CPU Targets Byte Offset 994 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO993 ,CPU Targets Byte Offset 993 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO992 ,CPU Targets Byte Offset 992 " group.long 0xBE4++0x03 line.long 0x00 "GICD_ITARGETSR249,Interrupt Processor Targets Register 249" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO999 ,CPU Targets Byte Offset 999 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO998 ,CPU Targets Byte Offset 998 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO997 ,CPU Targets Byte Offset 997 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO996 ,CPU Targets Byte Offset 996 " group.long 0xBE8++0x03 line.long 0x00 "GICD_ITARGETSR250,Interrupt Processor Targets Register 250" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO1003 ,CPU Targets Byte Offset 1003" hexmask.long.byte 0x00 16.--23. 1. " CPUTBO1002 ,CPU Targets Byte Offset 1002" hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1001 ,CPU Targets Byte Offset 1001" hexmask.long.byte 0x00 0.--7. 1. " CPUTBO1000 ,CPU Targets Byte Offset 1000" group.long 0xBEC++0x03 line.long 0x00 "GICD_ITARGETSR251,Interrupt Processor Targets Register 251" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO1007 ,CPU Targets Byte Offset 1007" hexmask.long.byte 0x00 16.--23. 1. " CPUTBO1006 ,CPU Targets Byte Offset 1006" hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1005 ,CPU Targets Byte Offset 1005" hexmask.long.byte 0x00 0.--7. 1. " CPUTBO1004 ,CPU Targets Byte Offset 1004" group.long 0xBF0++0x03 line.long 0x00 "GICD_ITARGETSR252,Interrupt Processor Targets Register 252" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO1011 ,CPU Targets Byte Offset 1011" hexmask.long.byte 0x00 16.--23. 1. " CPUTBO1010 ,CPU Targets Byte Offset 1010" hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1009 ,CPU Targets Byte Offset 1009" hexmask.long.byte 0x00 0.--7. 1. " CPUTBO1008 ,CPU Targets Byte Offset 1008" group.long 0xBF4++0x03 line.long 0x00 "GICD_ITARGETSR253,Interrupt Processor Targets Register 253" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO1015 ,CPU Targets Byte Offset 1015" hexmask.long.byte 0x00 16.--23. 1. " CPUTBO1014 ,CPU Targets Byte Offset 1014" hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1013 ,CPU Targets Byte Offset 1013" hexmask.long.byte 0x00 0.--7. 1. " CPUTBO1012 ,CPU Targets Byte Offset 1012" group.long 0xBF8++0x03 line.long 0x00 "GICD_ITARGETSR254,Interrupt Processor Targets Register 254" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO1019 ,CPU Targets Byte Offset 1019" hexmask.long.byte 0x00 16.--23. 1. " CPUTBO1018 ,CPU Targets Byte Offset 1018" hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1017 ,CPU Targets Byte Offset 1017" hexmask.long.byte 0x00 0.--7. 1. " CPUTBO1016 ,CPU Targets Byte Offset 1016" else rgroup.long 0xBE0++0x03 line.long 0x00 "GICD_ITARGETSR248,Interrupt Processor Targets Register 248" rgroup.long 0xBE4++0x03 line.long 0x00 "GICD_ITARGETSR249,Interrupt Processor Targets Register 249" rgroup.long 0xBE8++0x03 line.long 0x00 "GICD_ITARGETSR250,Interrupt Processor Targets Register 250" rgroup.long 0xBEC++0x03 line.long 0x00 "GICD_ITARGETSR251,Interrupt Processor Targets Register 251" rgroup.long 0xBF0++0x03 line.long 0x00 "GICD_ITARGETSR252,Interrupt Processor Targets Register 252" rgroup.long 0xBF4++0x03 line.long 0x00 "GICD_ITARGETSR253,Interrupt Processor Targets Register 253" rgroup.long 0xBF8++0x03 line.long 0x00 "GICD_ITARGETSR254,Interrupt Processor Targets Register 254" endif else rgroup.long 0x800++0x03 line.long 0x00 "GICD_ITARGETSR0 ,Interrupt Processor Targets Register 0 " rgroup.long 0x804++0x03 line.long 0x00 "GICD_ITARGETSR1 ,Interrupt Processor Targets Register 1 " rgroup.long 0x808++0x03 line.long 0x00 "GICD_ITARGETSR2 ,Interrupt Processor Targets Register 2 " rgroup.long 0x80C++0x03 line.long 0x00 "GICD_ITARGETSR3 ,Interrupt Processor Targets Register 3 " rgroup.long 0x810++0x03 line.long 0x00 "GICD_ITARGETSR4 ,Interrupt Processor Targets Register 4 " rgroup.long 0x814++0x03 line.long 0x00 "GICD_ITARGETSR5 ,Interrupt Processor Targets Register 5 " rgroup.long 0x818++0x03 line.long 0x00 "GICD_ITARGETSR6 ,Interrupt Processor Targets Register 6 " rgroup.long 0x81C++0x03 line.long 0x00 "GICD_ITARGETSR7 ,Interrupt Processor Targets Register 7 " rgroup.long 0x820++0x03 line.long 0x00 "GICD_ITARGETSR8 ,Interrupt Processor Targets Register 8 " rgroup.long 0x824++0x03 line.long 0x00 "GICD_ITARGETSR9 ,Interrupt Processor Targets Register 9 " rgroup.long 0x828++0x03 line.long 0x00 "GICD_ITARGETSR10 ,Interrupt Processor Targets Register 10 " rgroup.long 0x82C++0x03 line.long 0x00 "GICD_ITARGETSR11 ,Interrupt Processor Targets Register 11 " rgroup.long 0x830++0x03 line.long 0x00 "GICD_ITARGETSR12 ,Interrupt Processor Targets Register 12 " rgroup.long 0x834++0x03 line.long 0x00 "GICD_ITARGETSR13 ,Interrupt Processor Targets Register 13 " rgroup.long 0x838++0x03 line.long 0x00 "GICD_ITARGETSR14 ,Interrupt Processor Targets Register 14 " rgroup.long 0x83C++0x03 line.long 0x00 "GICD_ITARGETSR15 ,Interrupt Processor Targets Register 15 " rgroup.long 0x840++0x03 line.long 0x00 "GICD_ITARGETSR16 ,Interrupt Processor Targets Register 16 " rgroup.long 0x844++0x03 line.long 0x00 "GICD_ITARGETSR17 ,Interrupt Processor Targets Register 17 " rgroup.long 0x848++0x03 line.long 0x00 "GICD_ITARGETSR18 ,Interrupt Processor Targets Register 18 " rgroup.long 0x84C++0x03 line.long 0x00 "GICD_ITARGETSR19 ,Interrupt Processor Targets Register 19 " rgroup.long 0x850++0x03 line.long 0x00 "GICD_ITARGETSR20 ,Interrupt Processor Targets Register 20 " rgroup.long 0x854++0x03 line.long 0x00 "GICD_ITARGETSR21 ,Interrupt Processor Targets Register 21 " rgroup.long 0x858++0x03 line.long 0x00 "GICD_ITARGETSR22 ,Interrupt Processor Targets Register 22 " rgroup.long 0x85C++0x03 line.long 0x00 "GICD_ITARGETSR23 ,Interrupt Processor Targets Register 23 " rgroup.long 0x860++0x03 line.long 0x00 "GICD_ITARGETSR24 ,Interrupt Processor Targets Register 24 " rgroup.long 0x864++0x03 line.long 0x00 "GICD_ITARGETSR25 ,Interrupt Processor Targets Register 25 " rgroup.long 0x868++0x03 line.long 0x00 "GICD_ITARGETSR26 ,Interrupt Processor Targets Register 26 " rgroup.long 0x86C++0x03 line.long 0x00 "GICD_ITARGETSR27 ,Interrupt Processor Targets Register 27 " rgroup.long 0x870++0x03 line.long 0x00 "GICD_ITARGETSR28 ,Interrupt Processor Targets Register 28 " rgroup.long 0x874++0x03 line.long 0x00 "GICD_ITARGETSR29 ,Interrupt Processor Targets Register 29 " rgroup.long 0x878++0x03 line.long 0x00 "GICD_ITARGETSR30 ,Interrupt Processor Targets Register 30 " rgroup.long 0x87C++0x03 line.long 0x00 "GICD_ITARGETSR31 ,Interrupt Processor Targets Register 31 " rgroup.long 0x880++0x03 line.long 0x00 "GICD_ITARGETSR32 ,Interrupt Processor Targets Register 32 " rgroup.long 0x884++0x03 line.long 0x00 "GICD_ITARGETSR33 ,Interrupt Processor Targets Register 33 " rgroup.long 0x888++0x03 line.long 0x00 "GICD_ITARGETSR34 ,Interrupt Processor Targets Register 34 " rgroup.long 0x88C++0x03 line.long 0x00 "GICD_ITARGETSR35 ,Interrupt Processor Targets Register 35 " rgroup.long 0x890++0x03 line.long 0x00 "GICD_ITARGETSR36 ,Interrupt Processor Targets Register 36 " rgroup.long 0x894++0x03 line.long 0x00 "GICD_ITARGETSR37 ,Interrupt Processor Targets Register 37 " rgroup.long 0x898++0x03 line.long 0x00 "GICD_ITARGETSR38 ,Interrupt Processor Targets Register 38 " rgroup.long 0x89C++0x03 line.long 0x00 "GICD_ITARGETSR39 ,Interrupt Processor Targets Register 39 " rgroup.long 0x8A0++0x03 line.long 0x00 "GICD_ITARGETSR40 ,Interrupt Processor Targets Register 40 " rgroup.long 0x8A4++0x03 line.long 0x00 "GICD_ITARGETSR41 ,Interrupt Processor Targets Register 41 " rgroup.long 0x8A8++0x03 line.long 0x00 "GICD_ITARGETSR42 ,Interrupt Processor Targets Register 42 " rgroup.long 0x8AC++0x03 line.long 0x00 "GICD_ITARGETSR43 ,Interrupt Processor Targets Register 43 " rgroup.long 0x8B0++0x03 line.long 0x00 "GICD_ITARGETSR44 ,Interrupt Processor Targets Register 44 " rgroup.long 0x8B4++0x03 line.long 0x00 "GICD_ITARGETSR45 ,Interrupt Processor Targets Register 45 " rgroup.long 0x8B8++0x03 line.long 0x00 "GICD_ITARGETSR46 ,Interrupt Processor Targets Register 46 " rgroup.long 0x8BC++0x03 line.long 0x00 "GICD_ITARGETSR47 ,Interrupt Processor Targets Register 47 " rgroup.long 0x8C0++0x03 line.long 0x00 "GICD_ITARGETSR48 ,Interrupt Processor Targets Register 48 " rgroup.long 0x8C4++0x03 line.long 0x00 "GICD_ITARGETSR49 ,Interrupt Processor Targets Register 49 " rgroup.long 0x8C8++0x03 line.long 0x00 "GICD_ITARGETSR50 ,Interrupt Processor Targets Register 50 " rgroup.long 0x8CC++0x03 line.long 0x00 "GICD_ITARGETSR51 ,Interrupt Processor Targets Register 51 " rgroup.long 0x8D0++0x03 line.long 0x00 "GICD_ITARGETSR52 ,Interrupt Processor Targets Register 52 " rgroup.long 0x8D4++0x03 line.long 0x00 "GICD_ITARGETSR53 ,Interrupt Processor Targets Register 53 " rgroup.long 0x8D8++0x03 line.long 0x00 "GICD_ITARGETSR54 ,Interrupt Processor Targets Register 54 " rgroup.long 0x8DC++0x03 line.long 0x00 "GICD_ITARGETSR55 ,Interrupt Processor Targets Register 55 " rgroup.long 0x8E0++0x03 line.long 0x00 "GICD_ITARGETSR56 ,Interrupt Processor Targets Register 56 " rgroup.long 0x8E4++0x03 line.long 0x00 "GICD_ITARGETSR57 ,Interrupt Processor Targets Register 57 " rgroup.long 0x8E8++0x03 line.long 0x00 "GICD_ITARGETSR58 ,Interrupt Processor Targets Register 58 " rgroup.long 0x8EC++0x03 line.long 0x00 "GICD_ITARGETSR59 ,Interrupt Processor Targets Register 59 " rgroup.long 0x8F0++0x03 line.long 0x00 "GICD_ITARGETSR60 ,Interrupt Processor Targets Register 60 " rgroup.long 0x8F4++0x03 line.long 0x00 "GICD_ITARGETSR61 ,Interrupt Processor Targets Register 61 " rgroup.long 0x8F8++0x03 line.long 0x00 "GICD_ITARGETSR62 ,Interrupt Processor Targets Register 62 " rgroup.long 0x8FC++0x03 line.long 0x00 "GICD_ITARGETSR63 ,Interrupt Processor Targets Register 63 " rgroup.long 0x900++0x03 line.long 0x00 "GICD_ITARGETSR64 ,Interrupt Processor Targets Register 64 " rgroup.long 0x904++0x03 line.long 0x00 "GICD_ITARGETSR65 ,Interrupt Processor Targets Register 65 " rgroup.long 0x908++0x03 line.long 0x00 "GICD_ITARGETSR66 ,Interrupt Processor Targets Register 66 " rgroup.long 0x90C++0x03 line.long 0x00 "GICD_ITARGETSR67 ,Interrupt Processor Targets Register 67 " rgroup.long 0x910++0x03 line.long 0x00 "GICD_ITARGETSR68 ,Interrupt Processor Targets Register 68 " rgroup.long 0x914++0x03 line.long 0x00 "GICD_ITARGETSR69 ,Interrupt Processor Targets Register 69 " rgroup.long 0x918++0x03 line.long 0x00 "GICD_ITARGETSR70 ,Interrupt Processor Targets Register 70 " rgroup.long 0x91C++0x03 line.long 0x00 "GICD_ITARGETSR71 ,Interrupt Processor Targets Register 71 " rgroup.long 0x920++0x03 line.long 0x00 "GICD_ITARGETSR72 ,Interrupt Processor Targets Register 72 " rgroup.long 0x924++0x03 line.long 0x00 "GICD_ITARGETSR73 ,Interrupt Processor Targets Register 73 " rgroup.long 0x928++0x03 line.long 0x00 "GICD_ITARGETSR74 ,Interrupt Processor Targets Register 74 " rgroup.long 0x92C++0x03 line.long 0x00 "GICD_ITARGETSR75 ,Interrupt Processor Targets Register 75 " rgroup.long 0x930++0x03 line.long 0x00 "GICD_ITARGETSR76 ,Interrupt Processor Targets Register 76 " rgroup.long 0x934++0x03 line.long 0x00 "GICD_ITARGETSR77 ,Interrupt Processor Targets Register 77 " rgroup.long 0x938++0x03 line.long 0x00 "GICD_ITARGETSR78 ,Interrupt Processor Targets Register 78 " rgroup.long 0x93C++0x03 line.long 0x00 "GICD_ITARGETSR79 ,Interrupt Processor Targets Register 79 " rgroup.long 0x940++0x03 line.long 0x00 "GICD_ITARGETSR80 ,Interrupt Processor Targets Register 80 " rgroup.long 0x944++0x03 line.long 0x00 "GICD_ITARGETSR81 ,Interrupt Processor Targets Register 81 " rgroup.long 0x948++0x03 line.long 0x00 "GICD_ITARGETSR82 ,Interrupt Processor Targets Register 82 " rgroup.long 0x94C++0x03 line.long 0x00 "GICD_ITARGETSR83 ,Interrupt Processor Targets Register 83 " rgroup.long 0x950++0x03 line.long 0x00 "GICD_ITARGETSR84 ,Interrupt Processor Targets Register 84 " rgroup.long 0x954++0x03 line.long 0x00 "GICD_ITARGETSR85 ,Interrupt Processor Targets Register 85 " rgroup.long 0x958++0x03 line.long 0x00 "GICD_ITARGETSR86 ,Interrupt Processor Targets Register 86 " rgroup.long 0x95C++0x03 line.long 0x00 "GICD_ITARGETSR87 ,Interrupt Processor Targets Register 87 " rgroup.long 0x960++0x03 line.long 0x00 "GICD_ITARGETSR88 ,Interrupt Processor Targets Register 88 " rgroup.long 0x964++0x03 line.long 0x00 "GICD_ITARGETSR89 ,Interrupt Processor Targets Register 89 " rgroup.long 0x968++0x03 line.long 0x00 "GICD_ITARGETSR90 ,Interrupt Processor Targets Register 90 " rgroup.long 0x96C++0x03 line.long 0x00 "GICD_ITARGETSR91 ,Interrupt Processor Targets Register 91 " rgroup.long 0x970++0x03 line.long 0x00 "GICD_ITARGETSR92 ,Interrupt Processor Targets Register 92 " rgroup.long 0x974++0x03 line.long 0x00 "GICD_ITARGETSR93 ,Interrupt Processor Targets Register 93 " rgroup.long 0x978++0x03 line.long 0x00 "GICD_ITARGETSR94 ,Interrupt Processor Targets Register 94 " rgroup.long 0x97C++0x03 line.long 0x00 "GICD_ITARGETSR95 ,Interrupt Processor Targets Register 95 " rgroup.long 0x980++0x03 line.long 0x00 "GICD_ITARGETSR96 ,Interrupt Processor Targets Register 96 " rgroup.long 0x984++0x03 line.long 0x00 "GICD_ITARGETSR97 ,Interrupt Processor Targets Register 97 " rgroup.long 0x988++0x03 line.long 0x00 "GICD_ITARGETSR98 ,Interrupt Processor Targets Register 98 " rgroup.long 0x98C++0x03 line.long 0x00 "GICD_ITARGETSR99 ,Interrupt Processor Targets Register 99 " rgroup.long 0x990++0x03 line.long 0x00 "GICD_ITARGETSR100,Interrupt Processor Targets Register 100" rgroup.long 0x994++0x03 line.long 0x00 "GICD_ITARGETSR101,Interrupt Processor Targets Register 101" rgroup.long 0x998++0x03 line.long 0x00 "GICD_ITARGETSR102,Interrupt Processor Targets Register 102" rgroup.long 0x99C++0x03 line.long 0x00 "GICD_ITARGETSR103,Interrupt Processor Targets Register 103" rgroup.long 0x9A0++0x03 line.long 0x00 "GICD_ITARGETSR104,Interrupt Processor Targets Register 104" rgroup.long 0x9A4++0x03 line.long 0x00 "GICD_ITARGETSR105,Interrupt Processor Targets Register 105" rgroup.long 0x9A8++0x03 line.long 0x00 "GICD_ITARGETSR106,Interrupt Processor Targets Register 106" rgroup.long 0x9AC++0x03 line.long 0x00 "GICD_ITARGETSR107,Interrupt Processor Targets Register 107" rgroup.long 0x9B0++0x03 line.long 0x00 "GICD_ITARGETSR108,Interrupt Processor Targets Register 108" rgroup.long 0x9B4++0x03 line.long 0x00 "GICD_ITARGETSR109,Interrupt Processor Targets Register 109" rgroup.long 0x9B8++0x03 line.long 0x00 "GICD_ITARGETSR110,Interrupt Processor Targets Register 110" rgroup.long 0x9BC++0x03 line.long 0x00 "GICD_ITARGETSR111,Interrupt Processor Targets Register 111" rgroup.long 0x9C0++0x03 line.long 0x00 "GICD_ITARGETSR112,Interrupt Processor Targets Register 112" rgroup.long 0x9C4++0x03 line.long 0x00 "GICD_ITARGETSR113,Interrupt Processor Targets Register 113" rgroup.long 0x9C8++0x03 line.long 0x00 "GICD_ITARGETSR114,Interrupt Processor Targets Register 114" rgroup.long 0x9CC++0x03 line.long 0x00 "GICD_ITARGETSR115,Interrupt Processor Targets Register 115" rgroup.long 0x9D0++0x03 line.long 0x00 "GICD_ITARGETSR116,Interrupt Processor Targets Register 116" rgroup.long 0x9D4++0x03 line.long 0x00 "GICD_ITARGETSR117,Interrupt Processor Targets Register 117" rgroup.long 0x9D8++0x03 line.long 0x00 "GICD_ITARGETSR118,Interrupt Processor Targets Register 118" rgroup.long 0x9DC++0x03 line.long 0x00 "GICD_ITARGETSR119,Interrupt Processor Targets Register 119" rgroup.long 0x9E0++0x03 line.long 0x00 "GICD_ITARGETSR120,Interrupt Processor Targets Register 120" rgroup.long 0x9E4++0x03 line.long 0x00 "GICD_ITARGETSR121,Interrupt Processor Targets Register 121" rgroup.long 0x9E8++0x03 line.long 0x00 "GICD_ITARGETSR122,Interrupt Processor Targets Register 122" rgroup.long 0x9EC++0x03 line.long 0x00 "GICD_ITARGETSR123,Interrupt Processor Targets Register 123" rgroup.long 0x9F0++0x03 line.long 0x00 "GICD_ITARGETSR124,Interrupt Processor Targets Register 124" rgroup.long 0x9F4++0x03 line.long 0x00 "GICD_ITARGETSR125,Interrupt Processor Targets Register 125" rgroup.long 0x9F8++0x03 line.long 0x00 "GICD_ITARGETSR126,Interrupt Processor Targets Register 126" rgroup.long 0x9FC++0x03 line.long 0x00 "GICD_ITARGETSR127,Interrupt Processor Targets Register 127" rgroup.long 0xA00++0x03 line.long 0x00 "GICD_ITARGETSR128,Interrupt Processor Targets Register 128" rgroup.long 0xA04++0x03 line.long 0x00 "GICD_ITARGETSR129,Interrupt Processor Targets Register 129" rgroup.long 0xA08++0x03 line.long 0x00 "GICD_ITARGETSR130,Interrupt Processor Targets Register 130" rgroup.long 0xA0C++0x03 line.long 0x00 "GICD_ITARGETSR131,Interrupt Processor Targets Register 131" rgroup.long 0xA10++0x03 line.long 0x00 "GICD_ITARGETSR132,Interrupt Processor Targets Register 132" rgroup.long 0xA14++0x03 line.long 0x00 "GICD_ITARGETSR133,Interrupt Processor Targets Register 133" rgroup.long 0xA18++0x03 line.long 0x00 "GICD_ITARGETSR134,Interrupt Processor Targets Register 134" rgroup.long 0xA1C++0x03 line.long 0x00 "GICD_ITARGETSR135,Interrupt Processor Targets Register 135" rgroup.long 0xA20++0x03 line.long 0x00 "GICD_ITARGETSR136,Interrupt Processor Targets Register 136" rgroup.long 0xA24++0x03 line.long 0x00 "GICD_ITARGETSR137,Interrupt Processor Targets Register 137" rgroup.long 0xA28++0x03 line.long 0x00 "GICD_ITARGETSR138,Interrupt Processor Targets Register 138" rgroup.long 0xA2C++0x03 line.long 0x00 "GICD_ITARGETSR139,Interrupt Processor Targets Register 139" rgroup.long 0xA30++0x03 line.long 0x00 "GICD_ITARGETSR140,Interrupt Processor Targets Register 140" rgroup.long 0xA34++0x03 line.long 0x00 "GICD_ITARGETSR141,Interrupt Processor Targets Register 141" rgroup.long 0xA38++0x03 line.long 0x00 "GICD_ITARGETSR142,Interrupt Processor Targets Register 142" rgroup.long 0xA3C++0x03 line.long 0x00 "GICD_ITARGETSR143,Interrupt Processor Targets Register 143" rgroup.long 0xA40++0x03 line.long 0x00 "GICD_ITARGETSR144,Interrupt Processor Targets Register 144" rgroup.long 0xA44++0x03 line.long 0x00 "GICD_ITARGETSR145,Interrupt Processor Targets Register 145" rgroup.long 0xA48++0x03 line.long 0x00 "GICD_ITARGETSR146,Interrupt Processor Targets Register 146" rgroup.long 0xA4C++0x03 line.long 0x00 "GICD_ITARGETSR147,Interrupt Processor Targets Register 147" rgroup.long 0xA50++0x03 line.long 0x00 "GICD_ITARGETSR148,Interrupt Processor Targets Register 148" rgroup.long 0xA54++0x03 line.long 0x00 "GICD_ITARGETSR149,Interrupt Processor Targets Register 149" rgroup.long 0xA58++0x03 line.long 0x00 "GICD_ITARGETSR150,Interrupt Processor Targets Register 150" rgroup.long 0xA5C++0x03 line.long 0x00 "GICD_ITARGETSR151,Interrupt Processor Targets Register 151" rgroup.long 0xA60++0x03 line.long 0x00 "GICD_ITARGETSR152,Interrupt Processor Targets Register 152" rgroup.long 0xA64++0x03 line.long 0x00 "GICD_ITARGETSR153,Interrupt Processor Targets Register 153" rgroup.long 0xA68++0x03 line.long 0x00 "GICD_ITARGETSR154,Interrupt Processor Targets Register 154" rgroup.long 0xA6C++0x03 line.long 0x00 "GICD_ITARGETSR155,Interrupt Processor Targets Register 155" rgroup.long 0xA70++0x03 line.long 0x00 "GICD_ITARGETSR156,Interrupt Processor Targets Register 156" rgroup.long 0xA74++0x03 line.long 0x00 "GICD_ITARGETSR157,Interrupt Processor Targets Register 157" rgroup.long 0xA78++0x03 line.long 0x00 "GICD_ITARGETSR158,Interrupt Processor Targets Register 158" rgroup.long 0xA7C++0x03 line.long 0x00 "GICD_ITARGETSR159,Interrupt Processor Targets Register 159" rgroup.long 0xA80++0x03 line.long 0x00 "GICD_ITARGETSR160,Interrupt Processor Targets Register 160" rgroup.long 0xA84++0x03 line.long 0x00 "GICD_ITARGETSR161,Interrupt Processor Targets Register 161" rgroup.long 0xA88++0x03 line.long 0x00 "GICD_ITARGETSR162,Interrupt Processor Targets Register 162" rgroup.long 0xA8C++0x03 line.long 0x00 "GICD_ITARGETSR163,Interrupt Processor Targets Register 163" rgroup.long 0xA90++0x03 line.long 0x00 "GICD_ITARGETSR164,Interrupt Processor Targets Register 164" rgroup.long 0xA94++0x03 line.long 0x00 "GICD_ITARGETSR165,Interrupt Processor Targets Register 165" rgroup.long 0xA98++0x03 line.long 0x00 "GICD_ITARGETSR166,Interrupt Processor Targets Register 166" rgroup.long 0xA9C++0x03 line.long 0x00 "GICD_ITARGETSR167,Interrupt Processor Targets Register 167" rgroup.long 0xAA0++0x03 line.long 0x00 "GICD_ITARGETSR168,Interrupt Processor Targets Register 168" rgroup.long 0xAA4++0x03 line.long 0x00 "GICD_ITARGETSR169,Interrupt Processor Targets Register 169" rgroup.long 0xAA8++0x03 line.long 0x00 "GICD_ITARGETSR170,Interrupt Processor Targets Register 170" rgroup.long 0xAAC++0x03 line.long 0x00 "GICD_ITARGETSR171,Interrupt Processor Targets Register 171" rgroup.long 0xAB0++0x03 line.long 0x00 "GICD_ITARGETSR172,Interrupt Processor Targets Register 172" rgroup.long 0xAB4++0x03 line.long 0x00 "GICD_ITARGETSR173,Interrupt Processor Targets Register 173" rgroup.long 0xAB8++0x03 line.long 0x00 "GICD_ITARGETSR174,Interrupt Processor Targets Register 174" rgroup.long 0xABC++0x03 line.long 0x00 "GICD_ITARGETSR175,Interrupt Processor Targets Register 175" rgroup.long 0xAC0++0x03 line.long 0x00 "GICD_ITARGETSR176,Interrupt Processor Targets Register 176" rgroup.long 0xAC4++0x03 line.long 0x00 "GICD_ITARGETSR177,Interrupt Processor Targets Register 177" rgroup.long 0xAC8++0x03 line.long 0x00 "GICD_ITARGETSR178,Interrupt Processor Targets Register 178" rgroup.long 0xACC++0x03 line.long 0x00 "GICD_ITARGETSR179,Interrupt Processor Targets Register 179" rgroup.long 0xAD0++0x03 line.long 0x00 "GICD_ITARGETSR180,Interrupt Processor Targets Register 180" rgroup.long 0xAD4++0x03 line.long 0x00 "GICD_ITARGETSR181,Interrupt Processor Targets Register 181" rgroup.long 0xAD8++0x03 line.long 0x00 "GICD_ITARGETSR182,Interrupt Processor Targets Register 182" rgroup.long 0xADC++0x03 line.long 0x00 "GICD_ITARGETSR183,Interrupt Processor Targets Register 183" rgroup.long 0xAE0++0x03 line.long 0x00 "GICD_ITARGETSR184,Interrupt Processor Targets Register 184" rgroup.long 0xAE4++0x03 line.long 0x00 "GICD_ITARGETSR185,Interrupt Processor Targets Register 185" rgroup.long 0xAE8++0x03 line.long 0x00 "GICD_ITARGETSR186,Interrupt Processor Targets Register 186" rgroup.long 0xAEC++0x03 line.long 0x00 "GICD_ITARGETSR187,Interrupt Processor Targets Register 187" rgroup.long 0xAF0++0x03 line.long 0x00 "GICD_ITARGETSR188,Interrupt Processor Targets Register 188" rgroup.long 0xAF4++0x03 line.long 0x00 "GICD_ITARGETSR189,Interrupt Processor Targets Register 189" rgroup.long 0xAF8++0x03 line.long 0x00 "GICD_ITARGETSR190,Interrupt Processor Targets Register 190" rgroup.long 0xAFC++0x03 line.long 0x00 "GICD_ITARGETSR191,Interrupt Processor Targets Register 191" rgroup.long 0xB00++0x03 line.long 0x00 "GICD_ITARGETSR192,Interrupt Processor Targets Register 192" rgroup.long 0xB04++0x03 line.long 0x00 "GICD_ITARGETSR193,Interrupt Processor Targets Register 193" rgroup.long 0xB08++0x03 line.long 0x00 "GICD_ITARGETSR194,Interrupt Processor Targets Register 194" rgroup.long 0xB0C++0x03 line.long 0x00 "GICD_ITARGETSR195,Interrupt Processor Targets Register 195" rgroup.long 0xB10++0x03 line.long 0x00 "GICD_ITARGETSR196,Interrupt Processor Targets Register 196" rgroup.long 0xB14++0x03 line.long 0x00 "GICD_ITARGETSR197,Interrupt Processor Targets Register 197" rgroup.long 0xB18++0x03 line.long 0x00 "GICD_ITARGETSR198,Interrupt Processor Targets Register 198" rgroup.long 0xB1C++0x03 line.long 0x00 "GICD_ITARGETSR199,Interrupt Processor Targets Register 199" rgroup.long 0xB20++0x03 line.long 0x00 "GICD_ITARGETSR200,Interrupt Processor Targets Register 200" rgroup.long 0xB24++0x03 line.long 0x00 "GICD_ITARGETSR201,Interrupt Processor Targets Register 201" rgroup.long 0xB28++0x03 line.long 0x00 "GICD_ITARGETSR202,Interrupt Processor Targets Register 202" rgroup.long 0xB2C++0x03 line.long 0x00 "GICD_ITARGETSR203,Interrupt Processor Targets Register 203" rgroup.long 0xB30++0x03 line.long 0x00 "GICD_ITARGETSR204,Interrupt Processor Targets Register 204" rgroup.long 0xB34++0x03 line.long 0x00 "GICD_ITARGETSR205,Interrupt Processor Targets Register 205" rgroup.long 0xB38++0x03 line.long 0x00 "GICD_ITARGETSR206,Interrupt Processor Targets Register 206" rgroup.long 0xB3C++0x03 line.long 0x00 "GICD_ITARGETSR207,Interrupt Processor Targets Register 207" rgroup.long 0xB40++0x03 line.long 0x00 "GICD_ITARGETSR208,Interrupt Processor Targets Register 208" rgroup.long 0xB44++0x03 line.long 0x00 "GICD_ITARGETSR209,Interrupt Processor Targets Register 209" rgroup.long 0xB48++0x03 line.long 0x00 "GICD_ITARGETSR210,Interrupt Processor Targets Register 210" rgroup.long 0xB4C++0x03 line.long 0x00 "GICD_ITARGETSR211,Interrupt Processor Targets Register 211" rgroup.long 0xB50++0x03 line.long 0x00 "GICD_ITARGETSR212,Interrupt Processor Targets Register 212" rgroup.long 0xB54++0x03 line.long 0x00 "GICD_ITARGETSR213,Interrupt Processor Targets Register 213" rgroup.long 0xB58++0x03 line.long 0x00 "GICD_ITARGETSR214,Interrupt Processor Targets Register 214" rgroup.long 0xB5C++0x03 line.long 0x00 "GICD_ITARGETSR215,Interrupt Processor Targets Register 215" rgroup.long 0xB60++0x03 line.long 0x00 "GICD_ITARGETSR216,Interrupt Processor Targets Register 216" rgroup.long 0xB64++0x03 line.long 0x00 "GICD_ITARGETSR217,Interrupt Processor Targets Register 217" rgroup.long 0xB68++0x03 line.long 0x00 "GICD_ITARGETSR218,Interrupt Processor Targets Register 218" rgroup.long 0xB6C++0x03 line.long 0x00 "GICD_ITARGETSR219,Interrupt Processor Targets Register 219" rgroup.long 0xB70++0x03 line.long 0x00 "GICD_ITARGETSR220,Interrupt Processor Targets Register 220" rgroup.long 0xB74++0x03 line.long 0x00 "GICD_ITARGETSR221,Interrupt Processor Targets Register 221" rgroup.long 0xB78++0x03 line.long 0x00 "GICD_ITARGETSR222,Interrupt Processor Targets Register 222" rgroup.long 0xB7C++0x03 line.long 0x00 "GICD_ITARGETSR223,Interrupt Processor Targets Register 223" rgroup.long 0xB80++0x03 line.long 0x00 "GICD_ITARGETSR224,Interrupt Processor Targets Register 224" rgroup.long 0xB84++0x03 line.long 0x00 "GICD_ITARGETSR225,Interrupt Processor Targets Register 225" rgroup.long 0xB88++0x03 line.long 0x00 "GICD_ITARGETSR226,Interrupt Processor Targets Register 226" rgroup.long 0xB8C++0x03 line.long 0x00 "GICD_ITARGETSR227,Interrupt Processor Targets Register 227" rgroup.long 0xB90++0x03 line.long 0x00 "GICD_ITARGETSR228,Interrupt Processor Targets Register 228" rgroup.long 0xB94++0x03 line.long 0x00 "GICD_ITARGETSR229,Interrupt Processor Targets Register 229" rgroup.long 0xB98++0x03 line.long 0x00 "GICD_ITARGETSR230,Interrupt Processor Targets Register 230" rgroup.long 0xB9C++0x03 line.long 0x00 "GICD_ITARGETSR231,Interrupt Processor Targets Register 231" rgroup.long 0xBA0++0x03 line.long 0x00 "GICD_ITARGETSR232,Interrupt Processor Targets Register 232" rgroup.long 0xBA4++0x03 line.long 0x00 "GICD_ITARGETSR233,Interrupt Processor Targets Register 233" rgroup.long 0xBA8++0x03 line.long 0x00 "GICD_ITARGETSR234,Interrupt Processor Targets Register 234" rgroup.long 0xBAC++0x03 line.long 0x00 "GICD_ITARGETSR235,Interrupt Processor Targets Register 235" rgroup.long 0xBB0++0x03 line.long 0x00 "GICD_ITARGETSR236,Interrupt Processor Targets Register 236" rgroup.long 0xBB4++0x03 line.long 0x00 "GICD_ITARGETSR237,Interrupt Processor Targets Register 237" rgroup.long 0xBB8++0x03 line.long 0x00 "GICD_ITARGETSR238,Interrupt Processor Targets Register 238" rgroup.long 0xBBC++0x03 line.long 0x00 "GICD_ITARGETSR239,Interrupt Processor Targets Register 239" rgroup.long 0xBC0++0x03 line.long 0x00 "GICD_ITARGETSR240,Interrupt Processor Targets Register 240" rgroup.long 0xBC4++0x03 line.long 0x00 "GICD_ITARGETSR241,Interrupt Processor Targets Register 241" rgroup.long 0xBC8++0x03 line.long 0x00 "GICD_ITARGETSR242,Interrupt Processor Targets Register 242" rgroup.long 0xBCC++0x03 line.long 0x00 "GICD_ITARGETSR243,Interrupt Processor Targets Register 243" rgroup.long 0xBD0++0x03 line.long 0x00 "GICD_ITARGETSR244,Interrupt Processor Targets Register 244" rgroup.long 0xBD4++0x03 line.long 0x00 "GICD_ITARGETSR245,Interrupt Processor Targets Register 245" rgroup.long 0xBD8++0x03 line.long 0x00 "GICD_ITARGETSR246,Interrupt Processor Targets Register 246" rgroup.long 0xBDC++0x03 line.long 0x00 "GICD_ITARGETSR247,Interrupt Processor Targets Register 247" rgroup.long 0xBE0++0x03 line.long 0x00 "GICD_ITARGETSR248,Interrupt Processor Targets Register 248" rgroup.long 0xBE4++0x03 line.long 0x00 "GICD_ITARGETSR249,Interrupt Processor Targets Register 249" rgroup.long 0xBE8++0x03 line.long 0x00 "GICD_ITARGETSR250,Interrupt Processor Targets Register 250" rgroup.long 0xBEC++0x03 line.long 0x00 "GICD_ITARGETSR251,Interrupt Processor Targets Register 251" rgroup.long 0xBF0++0x03 line.long 0x00 "GICD_ITARGETSR252,Interrupt Processor Targets Register 252" rgroup.long 0xBF4++0x03 line.long 0x00 "GICD_ITARGETSR253,Interrupt Processor Targets Register 253" rgroup.long 0xBF8++0x03 line.long 0x00 "GICD_ITARGETSR254,Interrupt Processor Targets Register 254" endif tree.end width 14. tree "Configuration Registers" rgroup.long 0xC00++0x03 line.long 0x00 "GICD_ICFGR0,Interrupt Configuration Register" textline " " rgroup.long 0xC04++0x03 line.long 0x00 "GICD_ICFGR1,Interrupt Configuration Register" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" if (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x1) group.long 0xC08++0x03 line.long 0x00 "GICD_ICFGR2,Interrupt Configuration Register 2" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xC0C++0x03 line.long 0x00 "GICD_ICFGR3,Interrupt Configuration Register 3" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else rgroup.long 0xC08++0x03 line.long 0x00 "GICD_ICFGR2,Interrupt Configuration Register 2" rgroup.long 0xC0C++0x03 line.long 0x00 "GICD_ICFGR3,Interrupt Configuration Register 3" endif if (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x2) group.long 0xC10++0x03 line.long 0x00 "GICD_ICFGR4,Interrupt Configuration Register 4" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xC14++0x03 line.long 0x00 "GICD_ICFGR5,Interrupt Configuration Register 5" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else rgroup.long 0xC10++0x03 line.long 0x00 "GICD_ICFGR4,Interrupt Configuration Register 4" rgroup.long 0xC14++0x03 line.long 0x00 "GICD_ICFGR5,Interrupt Configuration Register 5" endif if (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x3) group.long 0xC18++0x03 line.long 0x00 "GICD_ICFGR6,Interrupt Configuration Register 6" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xC1C++0x03 line.long 0x00 "GICD_ICFGR7,Interrupt Configuration Register 7" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else rgroup.long 0xC18++0x03 line.long 0x00 "GICD_ICFGR6,Interrupt Configuration Register 6" rgroup.long 0xC1C++0x03 line.long 0x00 "GICD_ICFGR7,Interrupt Configuration Register 7" endif if (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x4) group.long 0xC20++0x03 line.long 0x00 "GICD_ICFGR8,Interrupt Configuration Register 8" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xC24++0x03 line.long 0x00 "GICD_ICFGR9,Interrupt Configuration Register 9" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else rgroup.long 0xC20++0x03 line.long 0x00 "GICD_ICFGR8,Interrupt Configuration Register 8" rgroup.long 0xC24++0x03 line.long 0x00 "GICD_ICFGR9,Interrupt Configuration Register 9" endif if (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x5) group.long 0xC28++0x03 line.long 0x00 "GICD_ICFGR10,Interrupt Configuration Register 10" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xC2C++0x03 line.long 0x00 "GICD_ICFGR11,Interrupt Configuration Register 11" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else rgroup.long 0xC28++0x03 line.long 0x00 "GICD_ICFGR10,Interrupt Configuration Register 10" rgroup.long 0xC2C++0x03 line.long 0x00 "GICD_ICFGR11,Interrupt Configuration Register 11" endif if (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x6) group.long 0xC30++0x03 line.long 0x00 "GICD_ICFGR12,Interrupt Configuration Register 12" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xC34++0x03 line.long 0x00 "GICD_ICFGR13,Interrupt Configuration Register 13" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else rgroup.long 0xC30++0x03 line.long 0x00 "GICD_ICFGR12,Interrupt Configuration Register 12" rgroup.long 0xC34++0x03 line.long 0x00 "GICD_ICFGR13,Interrupt Configuration Register 13" endif if (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x7) group.long 0xC38++0x03 line.long 0x00 "GICD_ICFGR14,Interrupt Configuration Register 14" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xC3C++0x03 line.long 0x00 "GICD_ICFGR15,Interrupt Configuration Register 15" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else rgroup.long 0xC38++0x03 line.long 0x00 "GICD_ICFGR14,Interrupt Configuration Register 14" rgroup.long 0xC3C++0x03 line.long 0x00 "GICD_ICFGR15,Interrupt Configuration Register 15" endif if (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x8) group.long 0xC40++0x03 line.long 0x00 "GICD_ICFGR16,Interrupt Configuration Register 16" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xC44++0x03 line.long 0x00 "GICD_ICFGR17,Interrupt Configuration Register 17" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else rgroup.long 0xC40++0x03 line.long 0x00 "GICD_ICFGR16,Interrupt Configuration Register 16" rgroup.long 0xC44++0x03 line.long 0x00 "GICD_ICFGR17,Interrupt Configuration Register 17" endif if (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x9) group.long 0xC48++0x03 line.long 0x00 "GICD_ICFGR18,Interrupt Configuration Register 18" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xC4C++0x03 line.long 0x00 "GICD_ICFGR19,Interrupt Configuration Register 19" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else rgroup.long 0xC48++0x03 line.long 0x00 "GICD_ICFGR18,Interrupt Configuration Register 18" rgroup.long 0xC4C++0x03 line.long 0x00 "GICD_ICFGR19,Interrupt Configuration Register 19" endif if (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0xA) group.long 0xC50++0x03 line.long 0x00 "GICD_ICFGR20,Interrupt Configuration Register 20" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xC54++0x03 line.long 0x00 "GICD_ICFGR21,Interrupt Configuration Register 21" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else rgroup.long 0xC50++0x03 line.long 0x00 "GICD_ICFGR20,Interrupt Configuration Register 20" rgroup.long 0xC54++0x03 line.long 0x00 "GICD_ICFGR21,Interrupt Configuration Register 21" endif if (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0xB) group.long 0xC58++0x03 line.long 0x00 "GICD_ICFGR22,Interrupt Configuration Register 22" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xC5C++0x03 line.long 0x00 "GICD_ICFGR23,Interrupt Configuration Register 23" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else rgroup.long 0xC58++0x03 line.long 0x00 "GICD_ICFGR22,Interrupt Configuration Register 22" rgroup.long 0xC5C++0x03 line.long 0x00 "GICD_ICFGR23,Interrupt Configuration Register 23" endif if (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0xC) group.long 0xC60++0x03 line.long 0x00 "GICD_ICFGR24,Interrupt Configuration Register 24" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xC64++0x03 line.long 0x00 "GICD_ICFGR25,Interrupt Configuration Register 25" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else rgroup.long 0xC60++0x03 line.long 0x00 "GICD_ICFGR24,Interrupt Configuration Register 24" rgroup.long 0xC64++0x03 line.long 0x00 "GICD_ICFGR25,Interrupt Configuration Register 25" endif if (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0xD) group.long 0xC68++0x03 line.long 0x00 "GICD_ICFGR26,Interrupt Configuration Register 26" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xC6C++0x03 line.long 0x00 "GICD_ICFGR27,Interrupt Configuration Register 27" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else rgroup.long 0xC68++0x03 line.long 0x00 "GICD_ICFGR26,Interrupt Configuration Register 26" rgroup.long 0xC6C++0x03 line.long 0x00 "GICD_ICFGR27,Interrupt Configuration Register 27" endif if (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0xE) group.long 0xC70++0x03 line.long 0x00 "GICD_ICFGR28,Interrupt Configuration Register 28" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xC74++0x03 line.long 0x00 "GICD_ICFGR29,Interrupt Configuration Register 29" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else rgroup.long 0xC70++0x03 line.long 0x00 "GICD_ICFGR28,Interrupt Configuration Register 28" rgroup.long 0xC74++0x03 line.long 0x00 "GICD_ICFGR29,Interrupt Configuration Register 29" endif if (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0xF) group.long 0xC78++0x03 line.long 0x00 "GICD_ICFGR30,Interrupt Configuration Register 30" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xC7C++0x03 line.long 0x00 "GICD_ICFGR31,Interrupt Configuration Register 31" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else rgroup.long 0xC78++0x03 line.long 0x00 "GICD_ICFGR30,Interrupt Configuration Register 30" rgroup.long 0xC7C++0x03 line.long 0x00 "GICD_ICFGR31,Interrupt Configuration Register 31" endif if (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x10) group.long 0xC80++0x03 line.long 0x00 "GICD_ICFGR32,Interrupt Configuration Register 32" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xC84++0x03 line.long 0x00 "GICD_ICFGR33,Interrupt Configuration Register 33" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else rgroup.long 0xC80++0x03 line.long 0x00 "GICD_ICFGR32,Interrupt Configuration Register 32" rgroup.long 0xC84++0x03 line.long 0x00 "GICD_ICFGR33,Interrupt Configuration Register 33" endif if (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x11) group.long 0xC88++0x03 line.long 0x00 "GICD_ICFGR34,Interrupt Configuration Register 34" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xC8C++0x03 line.long 0x00 "GICD_ICFGR35,Interrupt Configuration Register 35" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else rgroup.long 0xC88++0x03 line.long 0x00 "GICD_ICFGR34,Interrupt Configuration Register 34" rgroup.long 0xC8C++0x03 line.long 0x00 "GICD_ICFGR35,Interrupt Configuration Register 35" endif if (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x12) group.long 0xC90++0x03 line.long 0x00 "GICD_ICFGR36,Interrupt Configuration Register 36" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xC94++0x03 line.long 0x00 "GICD_ICFGR37,Interrupt Configuration Register 37" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else rgroup.long 0xC90++0x03 line.long 0x00 "GICD_ICFGR36,Interrupt Configuration Register 36" rgroup.long 0xC94++0x03 line.long 0x00 "GICD_ICFGR37,Interrupt Configuration Register 37" endif if (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x13) group.long 0xC98++0x03 line.long 0x00 "GICD_ICFGR38,Interrupt Configuration Register 38" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xC9C++0x03 line.long 0x00 "GICD_ICFGR39,Interrupt Configuration Register 39" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else rgroup.long 0xC98++0x03 line.long 0x00 "GICD_ICFGR38,Interrupt Configuration Register 38" rgroup.long 0xC9C++0x03 line.long 0x00 "GICD_ICFGR39,Interrupt Configuration Register 39" endif if (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x14) group.long 0xCA0++0x03 line.long 0x00 "GICD_ICFGR40,Interrupt Configuration Register 40" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xCA4++0x03 line.long 0x00 "GICD_ICFGR41,Interrupt Configuration Register 41" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else rgroup.long 0xCA0++0x03 line.long 0x00 "GICD_ICFGR40,Interrupt Configuration Register 40" rgroup.long 0xCA4++0x03 line.long 0x00 "GICD_ICFGR41,Interrupt Configuration Register 41" endif if (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x15) group.long 0xCA8++0x03 line.long 0x00 "GICD_ICFGR42,Interrupt Configuration Register 42" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xCAC++0x03 line.long 0x00 "GICD_ICFGR43,Interrupt Configuration Register 43" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else rgroup.long 0xCA8++0x03 line.long 0x00 "GICD_ICFGR42,Interrupt Configuration Register 42" rgroup.long 0xCAC++0x03 line.long 0x00 "GICD_ICFGR43,Interrupt Configuration Register 43" endif if (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x16) group.long 0xCB0++0x03 line.long 0x00 "GICD_ICFGR44,Interrupt Configuration Register 44" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xCB4++0x03 line.long 0x00 "GICD_ICFGR45,Interrupt Configuration Register 45" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else rgroup.long 0xCB0++0x03 line.long 0x00 "GICD_ICFGR44,Interrupt Configuration Register 44" rgroup.long 0xCB4++0x03 line.long 0x00 "GICD_ICFGR45,Interrupt Configuration Register 45" endif if (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x17) group.long 0xCB8++0x03 line.long 0x00 "GICD_ICFGR46,Interrupt Configuration Register 46" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xCBC++0x03 line.long 0x00 "GICD_ICFGR47,Interrupt Configuration Register 47" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else rgroup.long 0xCB8++0x03 line.long 0x00 "GICD_ICFGR46,Interrupt Configuration Register 46" rgroup.long 0xCBC++0x03 line.long 0x00 "GICD_ICFGR47,Interrupt Configuration Register 47" endif if (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x18) group.long 0xCC0++0x03 line.long 0x00 "GICD_ICFGR48,Interrupt Configuration Register 48" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xCC4++0x03 line.long 0x00 "GICD_ICFGR49,Interrupt Configuration Register 49" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else rgroup.long 0xCC0++0x03 line.long 0x00 "GICD_ICFGR48,Interrupt Configuration Register 48" rgroup.long 0xCC4++0x03 line.long 0x00 "GICD_ICFGR49,Interrupt Configuration Register 49" endif if (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x19) group.long 0xCC8++0x03 line.long 0x00 "GICD_ICFGR50,Interrupt Configuration Register 50" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xCCC++0x03 line.long 0x00 "GICD_ICFGR51,Interrupt Configuration Register 51" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else rgroup.long 0xCC8++0x03 line.long 0x00 "GICD_ICFGR50,Interrupt Configuration Register 50" rgroup.long 0xCCC++0x03 line.long 0x00 "GICD_ICFGR51,Interrupt Configuration Register 51" endif if (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x1A) group.long 0xCD0++0x03 line.long 0x00 "GICD_ICFGR52,Interrupt Configuration Register 52" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xCD4++0x03 line.long 0x00 "GICD_ICFGR53,Interrupt Configuration Register 53" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else rgroup.long 0xCD0++0x03 line.long 0x00 "GICD_ICFGR52,Interrupt Configuration Register 52" rgroup.long 0xCD4++0x03 line.long 0x00 "GICD_ICFGR53,Interrupt Configuration Register 53" endif if (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x1B) group.long 0xCD8++0x03 line.long 0x00 "GICD_ICFGR54,Interrupt Configuration Register 54" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xCDC++0x03 line.long 0x00 "GICD_ICFGR55,Interrupt Configuration Register 55" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else rgroup.long 0xCD8++0x03 line.long 0x00 "GICD_ICFGR54,Interrupt Configuration Register 54" rgroup.long 0xCDC++0x03 line.long 0x00 "GICD_ICFGR55,Interrupt Configuration Register 55" endif if (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x1C) group.long 0xCE0++0x03 line.long 0x00 "GICD_ICFGR56,Interrupt Configuration Register 56" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xCE4++0x03 line.long 0x00 "GICD_ICFGR57,Interrupt Configuration Register 57" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else rgroup.long 0xCE0++0x03 line.long 0x00 "GICD_ICFGR56,Interrupt Configuration Register 56" rgroup.long 0xCE4++0x03 line.long 0x00 "GICD_ICFGR57,Interrupt Configuration Register 57" endif if (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x1D) group.long 0xCE8++0x03 line.long 0x00 "GICD_ICFGR58,Interrupt Configuration Register 58" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xCEC++0x03 line.long 0x00 "GICD_ICFGR59,Interrupt Configuration Register 59" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else rgroup.long 0xCE8++0x03 line.long 0x00 "GICD_ICFGR58,Interrupt Configuration Register 58" rgroup.long 0xCEC++0x03 line.long 0x00 "GICD_ICFGR59,Interrupt Configuration Register 59" endif if (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x1E) group.long 0xCF0++0x03 line.long 0x00 "GICD_ICFGR60,Interrupt Configuration Register 60" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xCF4++0x03 line.long 0x00 "GICD_ICFGR61,Interrupt Configuration Register 61" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else rgroup.long 0xCF0++0x03 line.long 0x00 "GICD_ICFGR60,Interrupt Configuration Register 60" rgroup.long 0xCF4++0x03 line.long 0x00 "GICD_ICFGR61,Interrupt Configuration Register 61" endif if (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x1F) group.long 0xCF8++0x03 line.long 0x00 "GICD_ICFGR62,Interrupt Configuration Register 62" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xCFC++0x03 line.long 0x00 "GICD_ICFGR63,Interrupt Configuration Register 63" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else rgroup.long 0xCF8++0x03 line.long 0x00 "GICD_ICFGR62,Interrupt Configuration Register 62" rgroup.long 0xCFC++0x03 line.long 0x00 "GICD_ICFGR63,Interrupt Configuration Register 63" endif tree.end width 12. tree "Peripheral Interrupt Status Registers" rgroup.long 0x0D00++0x03 line.long 0x00 "GICD_PPISR,Private Peripheral Interrupt Status Register" bitfld.long 0x00 15. " PPI3S ,nIRQ pin status" "No interrupt,Interrupt" bitfld.long 0x00 14. " PPI2S ,Non-secure Physical Timer event status" "No interrupt,Interrupt" textline " " bitfld.long 0x00 13. " PPI1S ,Secure Physical Timer event status" "No interrupt,Interrupt" bitfld.long 0x00 12. " PPI0S ,nFIQ pin status" "No interrupt,Interrupt" textline " " bitfld.long 0x00 11. " PPI4S ,Virtual Timer event status" "No interrupt,Interrupt" bitfld.long 0x00 10. " PPI5S ,Hypervisor Timer event status" "No interrupt,Interrupt" textline " " bitfld.long 0x00 9. " PPI6S ,Virtual Maintenance Status" "No interrupt,Interrupt" textline " " width 22. if (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x01) rgroup.long 0x0D04++0x03 line.long 0x0 "GICD_SPISR0,Shared Peripheral Interrupt Status Register 0" bitfld.long 0x00 31. " IRQS31 ,IRQS Status Bit 31" "Low,High" bitfld.long 0x00 30. " IRQS30 ,IRQS Status Bit 30" "Low,High" bitfld.long 0x00 29. " IRQS29 ,IRQS Status Bit 29" "Low,High" textline " " bitfld.long 0x00 28. " IRQS28 ,IRQS Status Bit 28" "Low,High" bitfld.long 0x00 27. " IRQS27 ,IRQS Status Bit 27" "Low,High" bitfld.long 0x00 26. " IRQS26 ,IRQS Status Bit 26" "Low,High" textline " " bitfld.long 0x00 25. " IRQS25 ,IRQS Status Bit 25" "Low,High" bitfld.long 0x00 24. " IRQS24 ,IRQS Status Bit 24" "Low,High" bitfld.long 0x00 23. " IRQS23 ,IRQS Status Bit 23" "Low,High" textline " " bitfld.long 0x00 22. " IRQS22 ,IRQS Status Bit 22" "Low,High" bitfld.long 0x00 21. " IRQS21 ,IRQS Status Bit 21" "Low,High" bitfld.long 0x00 20. " IRQS20 ,IRQS Status Bit 20" "Low,High" textline " " bitfld.long 0x00 19. " IRQS19 ,IRQS Status Bit 19" "Low,High" bitfld.long 0x00 18. " IRQS18 ,IRQS Status Bit 18" "Low,High" bitfld.long 0x00 17. " IRQS17 ,IRQS Status Bit 17" "Low,High" textline " " bitfld.long 0x00 16. " IRQS16 ,IRQS Status Bit 16" "Low,High" bitfld.long 0x00 15. " IRQS15 ,IRQS Status Bit 15" "Low,High" bitfld.long 0x00 14. " IRQS14 ,IRQS Status Bit 14" "Low,High" textline " " bitfld.long 0x00 13. " IRQS13 ,IRQS Status Bit 13" "Low,High" bitfld.long 0x00 12. " IRQS12 ,IRQS Status Bit 12" "Low,High" bitfld.long 0x00 11. " IRQS11 ,IRQS Status Bit 11" "Low,High" textline " " bitfld.long 0x00 10. " IRQS10 ,IRQS Status Bit 10" "Low,High" bitfld.long 0x00 9. " IRQS9 ,IRQS Status Bit 9" "Low,High" bitfld.long 0x00 8. " IRQS8 ,IRQS Status Bit 8" "Low,High" textline " " bitfld.long 0x00 7. " IRQS7 ,IRQS Status Bit 7" "Low,High" bitfld.long 0x00 6. " IRQS6 ,IRQS Status Bit 6" "Low,High" bitfld.long 0x00 5. " IRQS5 ,IRQS Status Bit 5" "Low,High" textline " " bitfld.long 0x00 4. " IRQS4 ,IRQS Status Bit 4" "Low,High" bitfld.long 0x00 3. " IRQS3 ,IRQS Status Bit 3" "Low,High" bitfld.long 0x00 2. " IRQS2 ,IRQS Status Bit 2" "Low,High" textline " " bitfld.long 0x00 1. " IRQS1 ,IRQS Status Bit 1" "Low,High" bitfld.long 0x00 0. " IRQS0 ,IRQS Status Bit 0" "Low,High" else rgroup.long 0x0D04++0x03 line.long 0x0 "GICD_SPISR0,Shared Peripheral Interrupt Status Register 1" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x02) rgroup.long 0x0D08++0x03 line.long 0x0 "GICD_SPISR1,Shared Peripheral Interrupt Status Register 1" bitfld.long 0x00 31. " IRQS63 ,IRQS Status Bit 63" "Low,High" bitfld.long 0x00 30. " IRQS62 ,IRQS Status Bit 62" "Low,High" bitfld.long 0x00 29. " IRQS61 ,IRQS Status Bit 61" "Low,High" textline " " bitfld.long 0x00 28. " IRQS60 ,IRQS Status Bit 60" "Low,High" bitfld.long 0x00 27. " IRQS59 ,IRQS Status Bit 59" "Low,High" bitfld.long 0x00 26. " IRQS58 ,IRQS Status Bit 58" "Low,High" textline " " bitfld.long 0x00 25. " IRQS57 ,IRQS Status Bit 57" "Low,High" bitfld.long 0x00 24. " IRQS56 ,IRQS Status Bit 56" "Low,High" bitfld.long 0x00 23. " IRQS55 ,IRQS Status Bit 55" "Low,High" textline " " bitfld.long 0x00 22. " IRQS54 ,IRQS Status Bit 54" "Low,High" bitfld.long 0x00 21. " IRQS53 ,IRQS Status Bit 53" "Low,High" bitfld.long 0x00 20. " IRQS52 ,IRQS Status Bit 52" "Low,High" textline " " bitfld.long 0x00 19. " IRQS51 ,IRQS Status Bit 51" "Low,High" bitfld.long 0x00 18. " IRQS50 ,IRQS Status Bit 50" "Low,High" bitfld.long 0x00 17. " IRQS49 ,IRQS Status Bit 49" "Low,High" textline " " bitfld.long 0x00 16. " IRQS48 ,IRQS Status Bit 48" "Low,High" bitfld.long 0x00 15. " IRQS47 ,IRQS Status Bit 47" "Low,High" bitfld.long 0x00 14. " IRQS46 ,IRQS Status Bit 46" "Low,High" textline " " bitfld.long 0x00 13. " IRQS45 ,IRQS Status Bit 45" "Low,High" bitfld.long 0x00 12. " IRQS44 ,IRQS Status Bit 44" "Low,High" bitfld.long 0x00 11. " IRQS43 ,IRQS Status Bit 43" "Low,High" textline " " bitfld.long 0x00 10. " IRQS42 ,IRQS Status Bit 42" "Low,High" bitfld.long 0x00 9. " IRQS41 ,IRQS Status Bit 41" "Low,High" bitfld.long 0x00 8. " IRQS40 ,IRQS Status Bit 40" "Low,High" textline " " bitfld.long 0x00 7. " IRQS39 ,IRQS Status Bit 39" "Low,High" bitfld.long 0x00 6. " IRQS38 ,IRQS Status Bit 38" "Low,High" bitfld.long 0x00 5. " IRQS37 ,IRQS Status Bit 37" "Low,High" textline " " bitfld.long 0x00 4. " IRQS36 ,IRQS Status Bit 36" "Low,High" bitfld.long 0x00 3. " IRQS35 ,IRQS Status Bit 35" "Low,High" bitfld.long 0x00 2. " IRQS34 ,IRQS Status Bit 34" "Low,High" textline " " bitfld.long 0x00 1. " IRQS33 ,IRQS Status Bit 33" "Low,High" bitfld.long 0x00 0. " IRQS32 ,IRQS Status Bit 32" "Low,High" else rgroup.long 0x0D08++0x03 line.long 0x0 "GICD_SPISR1,Shared Peripheral Interrupt Status Register 1" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x03) rgroup.long 0x0D0C++0x03 line.long 0x0 "GICD_SPISR2,Shared Peripheral Interrupt Status Register 2" bitfld.long 0x00 31. " IRQS95 ,IRQS Status Bit 95" "Low,High" bitfld.long 0x00 30. " IRQS94 ,IRQS Status Bit 94" "Low,High" bitfld.long 0x00 29. " IRQS93 ,IRQS Status Bit 93" "Low,High" textline " " bitfld.long 0x00 28. " IRQS92 ,IRQS Status Bit 92" "Low,High" bitfld.long 0x00 27. " IRQS91 ,IRQS Status Bit 91" "Low,High" bitfld.long 0x00 26. " IRQS90 ,IRQS Status Bit 90" "Low,High" textline " " bitfld.long 0x00 25. " IRQS89 ,IRQS Status Bit 89" "Low,High" bitfld.long 0x00 24. " IRQS88 ,IRQS Status Bit 88" "Low,High" bitfld.long 0x00 23. " IRQS87 ,IRQS Status Bit 87" "Low,High" textline " " bitfld.long 0x00 22. " IRQS86 ,IRQS Status Bit 86" "Low,High" bitfld.long 0x00 21. " IRQS85 ,IRQS Status Bit 85" "Low,High" bitfld.long 0x00 20. " IRQS84 ,IRQS Status Bit 84" "Low,High" textline " " bitfld.long 0x00 19. " IRQS83 ,IRQS Status Bit 83" "Low,High" bitfld.long 0x00 18. " IRQS82 ,IRQS Status Bit 82" "Low,High" bitfld.long 0x00 17. " IRQS81 ,IRQS Status Bit 81" "Low,High" textline " " bitfld.long 0x00 16. " IRQS80 ,IRQS Status Bit 80" "Low,High" bitfld.long 0x00 15. " IRQS79 ,IRQS Status Bit 79" "Low,High" bitfld.long 0x00 14. " IRQS78 ,IRQS Status Bit 78" "Low,High" textline " " bitfld.long 0x00 13. " IRQS77 ,IRQS Status Bit 77" "Low,High" bitfld.long 0x00 12. " IRQS76 ,IRQS Status Bit 76" "Low,High" bitfld.long 0x00 11. " IRQS75 ,IRQS Status Bit 75" "Low,High" textline " " bitfld.long 0x00 10. " IRQS74 ,IRQS Status Bit 74" "Low,High" bitfld.long 0x00 9. " IRQS73 ,IRQS Status Bit 73" "Low,High" bitfld.long 0x00 8. " IRQS72 ,IRQS Status Bit 72" "Low,High" textline " " bitfld.long 0x00 7. " IRQS71 ,IRQS Status Bit 71" "Low,High" bitfld.long 0x00 6. " IRQS70 ,IRQS Status Bit 70" "Low,High" bitfld.long 0x00 5. " IRQS69 ,IRQS Status Bit 69" "Low,High" textline " " bitfld.long 0x00 4. " IRQS68 ,IRQS Status Bit 68" "Low,High" bitfld.long 0x00 3. " IRQS67 ,IRQS Status Bit 67" "Low,High" bitfld.long 0x00 2. " IRQS66 ,IRQS Status Bit 66" "Low,High" textline " " bitfld.long 0x00 1. " IRQS65 ,IRQS Status Bit 65" "Low,High" bitfld.long 0x00 0. " IRQS64 ,IRQS Status Bit 64" "Low,High" else rgroup.long 0x0D0C++0x03 line.long 0x0 "GICD_SPISR2,Shared Peripheral Interrupt Status Register 2" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x04) rgroup.long 0x0D10++0x03 line.long 0x0 "GICD_SPISR3,Shared Peripheral Interrupt Status Register 3" bitfld.long 0x00 31. " IRQS127 ,IRQS Status Bit 127" "Low,High" bitfld.long 0x00 30. " IRQS126 ,IRQS Status Bit 126" "Low,High" bitfld.long 0x00 29. " IRQS125 ,IRQS Status Bit 125" "Low,High" textline " " bitfld.long 0x00 28. " IRQS124 ,IRQS Status Bit 124" "Low,High" bitfld.long 0x00 27. " IRQS123 ,IRQS Status Bit 123" "Low,High" bitfld.long 0x00 26. " IRQS122 ,IRQS Status Bit 122" "Low,High" textline " " bitfld.long 0x00 25. " IRQS121 ,IRQS Status Bit 121" "Low,High" bitfld.long 0x00 24. " IRQS120 ,IRQS Status Bit 120" "Low,High" bitfld.long 0x00 23. " IRQS119 ,IRQS Status Bit 119" "Low,High" textline " " bitfld.long 0x00 22. " IRQS118 ,IRQS Status Bit 118" "Low,High" bitfld.long 0x00 21. " IRQS117 ,IRQS Status Bit 117" "Low,High" bitfld.long 0x00 20. " IRQS116 ,IRQS Status Bit 116" "Low,High" textline " " bitfld.long 0x00 19. " IRQS115 ,IRQS Status Bit 115" "Low,High" bitfld.long 0x00 18. " IRQS114 ,IRQS Status Bit 114" "Low,High" bitfld.long 0x00 17. " IRQS113 ,IRQS Status Bit 113" "Low,High" textline " " bitfld.long 0x00 16. " IRQS112 ,IRQS Status Bit 112" "Low,High" bitfld.long 0x00 15. " IRQS111 ,IRQS Status Bit 111" "Low,High" bitfld.long 0x00 14. " IRQS110 ,IRQS Status Bit 110" "Low,High" textline " " bitfld.long 0x00 13. " IRQS109 ,IRQS Status Bit 109" "Low,High" bitfld.long 0x00 12. " IRQS108 ,IRQS Status Bit 108" "Low,High" bitfld.long 0x00 11. " IRQS107 ,IRQS Status Bit 107" "Low,High" textline " " bitfld.long 0x00 10. " IRQS106 ,IRQS Status Bit 106" "Low,High" bitfld.long 0x00 9. " IRQS105 ,IRQS Status Bit 105" "Low,High" bitfld.long 0x00 8. " IRQS104 ,IRQS Status Bit 104" "Low,High" textline " " bitfld.long 0x00 7. " IRQS103 ,IRQS Status Bit 103" "Low,High" bitfld.long 0x00 6. " IRQS102 ,IRQS Status Bit 102" "Low,High" bitfld.long 0x00 5. " IRQS101 ,IRQS Status Bit 101" "Low,High" textline " " bitfld.long 0x00 4. " IRQS100 ,IRQS Status Bit 100" "Low,High" bitfld.long 0x00 3. " IRQS99 ,IRQS Status Bit 99" "Low,High" bitfld.long 0x00 2. " IRQS98 ,IRQS Status Bit 98" "Low,High" textline " " bitfld.long 0x00 1. " IRQS97 ,IRQS Status Bit 97" "Low,High" bitfld.long 0x00 0. " IRQS96 ,IRQS Status Bit 96" "Low,High" else rgroup.long 0x0D10++0x03 line.long 0x0 "GICD_SPISR3,Shared Peripheral Interrupt Status Register 3" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x05) rgroup.long 0x0D14++0x03 line.long 0x0 "GICD_SPISR4,Shared Peripheral Interrupt Status Register 4" bitfld.long 0x00 31. " IRQS159 ,IRQS Status Bit 159" "Low,High" bitfld.long 0x00 30. " IRQS158 ,IRQS Status Bit 158" "Low,High" bitfld.long 0x00 29. " IRQS157 ,IRQS Status Bit 157" "Low,High" textline " " bitfld.long 0x00 28. " IRQS156 ,IRQS Status Bit 156" "Low,High" bitfld.long 0x00 27. " IRQS155 ,IRQS Status Bit 155" "Low,High" bitfld.long 0x00 26. " IRQS154 ,IRQS Status Bit 154" "Low,High" textline " " bitfld.long 0x00 25. " IRQS153 ,IRQS Status Bit 153" "Low,High" bitfld.long 0x00 24. " IRQS152 ,IRQS Status Bit 152" "Low,High" bitfld.long 0x00 23. " IRQS151 ,IRQS Status Bit 151" "Low,High" textline " " bitfld.long 0x00 22. " IRQS150 ,IRQS Status Bit 150" "Low,High" bitfld.long 0x00 21. " IRQS149 ,IRQS Status Bit 149" "Low,High" bitfld.long 0x00 20. " IRQS148 ,IRQS Status Bit 148" "Low,High" textline " " bitfld.long 0x00 19. " IRQS147 ,IRQS Status Bit 147" "Low,High" bitfld.long 0x00 18. " IRQS146 ,IRQS Status Bit 146" "Low,High" bitfld.long 0x00 17. " IRQS145 ,IRQS Status Bit 145" "Low,High" textline " " bitfld.long 0x00 16. " IRQS144 ,IRQS Status Bit 144" "Low,High" bitfld.long 0x00 15. " IRQS143 ,IRQS Status Bit 143" "Low,High" bitfld.long 0x00 14. " IRQS142 ,IRQS Status Bit 142" "Low,High" textline " " bitfld.long 0x00 13. " IRQS141 ,IRQS Status Bit 141" "Low,High" bitfld.long 0x00 12. " IRQS140 ,IRQS Status Bit 140" "Low,High" bitfld.long 0x00 11. " IRQS139 ,IRQS Status Bit 139" "Low,High" textline " " bitfld.long 0x00 10. " IRQS138 ,IRQS Status Bit 138" "Low,High" bitfld.long 0x00 9. " IRQS137 ,IRQS Status Bit 137" "Low,High" bitfld.long 0x00 8. " IRQS136 ,IRQS Status Bit 136" "Low,High" textline " " bitfld.long 0x00 7. " IRQS135 ,IRQS Status Bit 135" "Low,High" bitfld.long 0x00 6. " IRQS134 ,IRQS Status Bit 134" "Low,High" bitfld.long 0x00 5. " IRQS133 ,IRQS Status Bit 133" "Low,High" textline " " bitfld.long 0x00 4. " IRQS132 ,IRQS Status Bit 132" "Low,High" bitfld.long 0x00 3. " IRQS131 ,IRQS Status Bit 131" "Low,High" bitfld.long 0x00 2. " IRQS130 ,IRQS Status Bit 130" "Low,High" textline " " bitfld.long 0x00 1. " IRQS129 ,IRQS Status Bit 129" "Low,High" bitfld.long 0x00 0. " IRQS128 ,IRQS Status Bit 128" "Low,High" else rgroup.long 0x0D14++0x03 line.long 0x0 "GICD_SPISR4,Shared Peripheral Interrupt Status Register 4" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x06) rgroup.long 0x0D18++0x03 line.long 0x0 "GICD_SPISR5,Shared Peripheral Interrupt Status Register 5" bitfld.long 0x00 31. " IRQS191 ,IRQS Status Bit 191" "Low,High" bitfld.long 0x00 30. " IRQS190 ,IRQS Status Bit 190" "Low,High" bitfld.long 0x00 29. " IRQS189 ,IRQS Status Bit 189" "Low,High" textline " " bitfld.long 0x00 28. " IRQS188 ,IRQS Status Bit 188" "Low,High" bitfld.long 0x00 27. " IRQS187 ,IRQS Status Bit 187" "Low,High" bitfld.long 0x00 26. " IRQS186 ,IRQS Status Bit 186" "Low,High" textline " " bitfld.long 0x00 25. " IRQS185 ,IRQS Status Bit 185" "Low,High" bitfld.long 0x00 24. " IRQS184 ,IRQS Status Bit 184" "Low,High" bitfld.long 0x00 23. " IRQS183 ,IRQS Status Bit 183" "Low,High" textline " " bitfld.long 0x00 22. " IRQS182 ,IRQS Status Bit 182" "Low,High" bitfld.long 0x00 21. " IRQS181 ,IRQS Status Bit 181" "Low,High" bitfld.long 0x00 20. " IRQS180 ,IRQS Status Bit 180" "Low,High" textline " " bitfld.long 0x00 19. " IRQS179 ,IRQS Status Bit 179" "Low,High" bitfld.long 0x00 18. " IRQS178 ,IRQS Status Bit 178" "Low,High" bitfld.long 0x00 17. " IRQS177 ,IRQS Status Bit 177" "Low,High" textline " " bitfld.long 0x00 16. " IRQS176 ,IRQS Status Bit 176" "Low,High" bitfld.long 0x00 15. " IRQS175 ,IRQS Status Bit 175" "Low,High" bitfld.long 0x00 14. " IRQS174 ,IRQS Status Bit 174" "Low,High" textline " " bitfld.long 0x00 13. " IRQS173 ,IRQS Status Bit 173" "Low,High" bitfld.long 0x00 12. " IRQS172 ,IRQS Status Bit 172" "Low,High" bitfld.long 0x00 11. " IRQS171 ,IRQS Status Bit 171" "Low,High" textline " " bitfld.long 0x00 10. " IRQS170 ,IRQS Status Bit 170" "Low,High" bitfld.long 0x00 9. " IRQS169 ,IRQS Status Bit 169" "Low,High" bitfld.long 0x00 8. " IRQS168 ,IRQS Status Bit 168" "Low,High" textline " " bitfld.long 0x00 7. " IRQS167 ,IRQS Status Bit 167" "Low,High" bitfld.long 0x00 6. " IRQS166 ,IRQS Status Bit 166" "Low,High" bitfld.long 0x00 5. " IRQS165 ,IRQS Status Bit 165" "Low,High" textline " " bitfld.long 0x00 4. " IRQS164 ,IRQS Status Bit 164" "Low,High" bitfld.long 0x00 3. " IRQS163 ,IRQS Status Bit 163" "Low,High" bitfld.long 0x00 2. " IRQS162 ,IRQS Status Bit 162" "Low,High" textline " " bitfld.long 0x00 1. " IRQS161 ,IRQS Status Bit 161" "Low,High" bitfld.long 0x00 0. " IRQS160 ,IRQS Status Bit 160" "Low,High" else rgroup.long 0x0D18++0x03 line.long 0x0 "GICD_SPISR5,Shared Peripheral Interrupt Status Register 5" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x07) rgroup.long 0x0D1C++0x03 line.long 0x0 "GICD_SPISR6,Shared Peripheral Interrupt Status Register 6" bitfld.long 0x00 31. " IRQS223 ,IRQS Status Bit 223" "Low,High" bitfld.long 0x00 30. " IRQS222 ,IRQS Status Bit 222" "Low,High" bitfld.long 0x00 29. " IRQS221 ,IRQS Status Bit 221" "Low,High" textline " " bitfld.long 0x00 28. " IRQS220 ,IRQS Status Bit 220" "Low,High" bitfld.long 0x00 27. " IRQS219 ,IRQS Status Bit 219" "Low,High" bitfld.long 0x00 26. " IRQS218 ,IRQS Status Bit 218" "Low,High" textline " " bitfld.long 0x00 25. " IRQS217 ,IRQS Status Bit 217" "Low,High" bitfld.long 0x00 24. " IRQS216 ,IRQS Status Bit 216" "Low,High" bitfld.long 0x00 23. " IRQS215 ,IRQS Status Bit 215" "Low,High" textline " " bitfld.long 0x00 22. " IRQS214 ,IRQS Status Bit 214" "Low,High" bitfld.long 0x00 21. " IRQS213 ,IRQS Status Bit 213" "Low,High" bitfld.long 0x00 20. " IRQS212 ,IRQS Status Bit 212" "Low,High" textline " " bitfld.long 0x00 19. " IRQS211 ,IRQS Status Bit 211" "Low,High" bitfld.long 0x00 18. " IRQS210 ,IRQS Status Bit 210" "Low,High" bitfld.long 0x00 17. " IRQS209 ,IRQS Status Bit 209" "Low,High" textline " " bitfld.long 0x00 16. " IRQS208 ,IRQS Status Bit 208" "Low,High" bitfld.long 0x00 15. " IRQS207 ,IRQS Status Bit 207" "Low,High" bitfld.long 0x00 14. " IRQS206 ,IRQS Status Bit 206" "Low,High" textline " " bitfld.long 0x00 13. " IRQS205 ,IRQS Status Bit 205" "Low,High" bitfld.long 0x00 12. " IRQS204 ,IRQS Status Bit 204" "Low,High" bitfld.long 0x00 11. " IRQS203 ,IRQS Status Bit 203" "Low,High" textline " " bitfld.long 0x00 10. " IRQS202 ,IRQS Status Bit 202" "Low,High" bitfld.long 0x00 9. " IRQS201 ,IRQS Status Bit 201" "Low,High" bitfld.long 0x00 8. " IRQS200 ,IRQS Status Bit 200" "Low,High" textline " " bitfld.long 0x00 7. " IRQS199 ,IRQS Status Bit 199" "Low,High" bitfld.long 0x00 6. " IRQS198 ,IRQS Status Bit 198" "Low,High" bitfld.long 0x00 5. " IRQS197 ,IRQS Status Bit 197" "Low,High" textline " " bitfld.long 0x00 4. " IRQS196 ,IRQS Status Bit 196" "Low,High" bitfld.long 0x00 3. " IRQS195 ,IRQS Status Bit 195" "Low,High" bitfld.long 0x00 2. " IRQS194 ,IRQS Status Bit 194" "Low,High" textline " " bitfld.long 0x00 1. " IRQS193 ,IRQS Status Bit 193" "Low,High" bitfld.long 0x00 0. " IRQS192 ,IRQS Status Bit 192" "Low,High" else rgroup.long 0x0D1C++0x03 line.long 0x0 "GICD_SPISR6,Shared Peripheral Interrupt Status Register 6" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x08) rgroup.long 0x0D20++0x03 line.long 0x0 "GICD_SPISR7,Shared Peripheral Interrupt Status Register 7" bitfld.long 0x00 31. " IRQS255 ,IRQS Status Bit 255" "Low,High" bitfld.long 0x00 30. " IRQS254 ,IRQS Status Bit 254" "Low,High" bitfld.long 0x00 29. " IRQS253 ,IRQS Status Bit 253" "Low,High" textline " " bitfld.long 0x00 28. " IRQS252 ,IRQS Status Bit 252" "Low,High" bitfld.long 0x00 27. " IRQS251 ,IRQS Status Bit 251" "Low,High" bitfld.long 0x00 26. " IRQS250 ,IRQS Status Bit 250" "Low,High" textline " " bitfld.long 0x00 25. " IRQS249 ,IRQS Status Bit 249" "Low,High" bitfld.long 0x00 24. " IRQS248 ,IRQS Status Bit 248" "Low,High" bitfld.long 0x00 23. " IRQS247 ,IRQS Status Bit 247" "Low,High" textline " " bitfld.long 0x00 22. " IRQS246 ,IRQS Status Bit 246" "Low,High" bitfld.long 0x00 21. " IRQS245 ,IRQS Status Bit 245" "Low,High" bitfld.long 0x00 20. " IRQS244 ,IRQS Status Bit 244" "Low,High" textline " " bitfld.long 0x00 19. " IRQS243 ,IRQS Status Bit 243" "Low,High" bitfld.long 0x00 18. " IRQS242 ,IRQS Status Bit 242" "Low,High" bitfld.long 0x00 17. " IRQS241 ,IRQS Status Bit 241" "Low,High" textline " " bitfld.long 0x00 16. " IRQS240 ,IRQS Status Bit 240" "Low,High" bitfld.long 0x00 15. " IRQS239 ,IRQS Status Bit 239" "Low,High" bitfld.long 0x00 14. " IRQS238 ,IRQS Status Bit 238" "Low,High" textline " " bitfld.long 0x00 13. " IRQS237 ,IRQS Status Bit 237" "Low,High" bitfld.long 0x00 12. " IRQS236 ,IRQS Status Bit 236" "Low,High" bitfld.long 0x00 11. " IRQS235 ,IRQS Status Bit 235" "Low,High" textline " " bitfld.long 0x00 10. " IRQS234 ,IRQS Status Bit 234" "Low,High" bitfld.long 0x00 9. " IRQS233 ,IRQS Status Bit 233" "Low,High" bitfld.long 0x00 8. " IRQS232 ,IRQS Status Bit 232" "Low,High" textline " " bitfld.long 0x00 7. " IRQS231 ,IRQS Status Bit 231" "Low,High" bitfld.long 0x00 6. " IRQS230 ,IRQS Status Bit 230" "Low,High" bitfld.long 0x00 5. " IRQS229 ,IRQS Status Bit 229" "Low,High" textline " " bitfld.long 0x00 4. " IRQS228 ,IRQS Status Bit 228" "Low,High" bitfld.long 0x00 3. " IRQS227 ,IRQS Status Bit 227" "Low,High" bitfld.long 0x00 2. " IRQS226 ,IRQS Status Bit 226" "Low,High" textline " " bitfld.long 0x00 1. " IRQS225 ,IRQS Status Bit 225" "Low,High" bitfld.long 0x00 0. " IRQS224 ,IRQS Status Bit 224" "Low,High" else rgroup.long 0x0D20++0x03 line.long 0x0 "GICD_SPISR7,Shared Peripheral Interrupt Status Register 7" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x09) rgroup.long 0x0D24++0x03 line.long 0x0 "GICD_SPISR8,Shared Peripheral Interrupt Status Register 8" bitfld.long 0x00 31. " IRQS287 ,IRQS Status Bit 287" "Low,High" bitfld.long 0x00 30. " IRQS286 ,IRQS Status Bit 286" "Low,High" bitfld.long 0x00 29. " IRQS285 ,IRQS Status Bit 285" "Low,High" textline " " bitfld.long 0x00 28. " IRQS284 ,IRQS Status Bit 284" "Low,High" bitfld.long 0x00 27. " IRQS283 ,IRQS Status Bit 283" "Low,High" bitfld.long 0x00 26. " IRQS282 ,IRQS Status Bit 282" "Low,High" textline " " bitfld.long 0x00 25. " IRQS281 ,IRQS Status Bit 281" "Low,High" bitfld.long 0x00 24. " IRQS280 ,IRQS Status Bit 280" "Low,High" bitfld.long 0x00 23. " IRQS279 ,IRQS Status Bit 279" "Low,High" textline " " bitfld.long 0x00 22. " IRQS278 ,IRQS Status Bit 278" "Low,High" bitfld.long 0x00 21. " IRQS277 ,IRQS Status Bit 277" "Low,High" bitfld.long 0x00 20. " IRQS276 ,IRQS Status Bit 276" "Low,High" textline " " bitfld.long 0x00 19. " IRQS275 ,IRQS Status Bit 275" "Low,High" bitfld.long 0x00 18. " IRQS274 ,IRQS Status Bit 274" "Low,High" bitfld.long 0x00 17. " IRQS273 ,IRQS Status Bit 273" "Low,High" textline " " bitfld.long 0x00 16. " IRQS272 ,IRQS Status Bit 272" "Low,High" bitfld.long 0x00 15. " IRQS271 ,IRQS Status Bit 271" "Low,High" bitfld.long 0x00 14. " IRQS270 ,IRQS Status Bit 270" "Low,High" textline " " bitfld.long 0x00 13. " IRQS269 ,IRQS Status Bit 269" "Low,High" bitfld.long 0x00 12. " IRQS268 ,IRQS Status Bit 268" "Low,High" bitfld.long 0x00 11. " IRQS267 ,IRQS Status Bit 267" "Low,High" textline " " bitfld.long 0x00 10. " IRQS266 ,IRQS Status Bit 266" "Low,High" bitfld.long 0x00 9. " IRQS265 ,IRQS Status Bit 265" "Low,High" bitfld.long 0x00 8. " IRQS264 ,IRQS Status Bit 264" "Low,High" textline " " bitfld.long 0x00 7. " IRQS263 ,IRQS Status Bit 263" "Low,High" bitfld.long 0x00 6. " IRQS262 ,IRQS Status Bit 262" "Low,High" bitfld.long 0x00 5. " IRQS261 ,IRQS Status Bit 261" "Low,High" textline " " bitfld.long 0x00 4. " IRQS260 ,IRQS Status Bit 260" "Low,High" bitfld.long 0x00 3. " IRQS259 ,IRQS Status Bit 259" "Low,High" bitfld.long 0x00 2. " IRQS258 ,IRQS Status Bit 258" "Low,High" textline " " bitfld.long 0x00 1. " IRQS257 ,IRQS Status Bit 257" "Low,High" bitfld.long 0x00 0. " IRQS256 ,IRQS Status Bit 256" "Low,High" else rgroup.long 0x0D24++0x03 line.long 0x0 "GICD_SPISR8,Shared Peripheral Interrupt Status Register 8" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x0A) rgroup.long 0x0D28++0x03 line.long 0x0 "GICD_SPISR9,Shared Peripheral Interrupt Status Register 9" bitfld.long 0x00 31. " IRQS319 ,IRQS Status Bit 319" "Low,High" bitfld.long 0x00 30. " IRQS318 ,IRQS Status Bit 318" "Low,High" bitfld.long 0x00 29. " IRQS317 ,IRQS Status Bit 317" "Low,High" textline " " bitfld.long 0x00 28. " IRQS316 ,IRQS Status Bit 316" "Low,High" bitfld.long 0x00 27. " IRQS315 ,IRQS Status Bit 315" "Low,High" bitfld.long 0x00 26. " IRQS314 ,IRQS Status Bit 314" "Low,High" textline " " bitfld.long 0x00 25. " IRQS313 ,IRQS Status Bit 313" "Low,High" bitfld.long 0x00 24. " IRQS312 ,IRQS Status Bit 312" "Low,High" bitfld.long 0x00 23. " IRQS311 ,IRQS Status Bit 311" "Low,High" textline " " bitfld.long 0x00 22. " IRQS310 ,IRQS Status Bit 310" "Low,High" bitfld.long 0x00 21. " IRQS309 ,IRQS Status Bit 309" "Low,High" bitfld.long 0x00 20. " IRQS308 ,IRQS Status Bit 308" "Low,High" textline " " bitfld.long 0x00 19. " IRQS307 ,IRQS Status Bit 307" "Low,High" bitfld.long 0x00 18. " IRQS306 ,IRQS Status Bit 306" "Low,High" bitfld.long 0x00 17. " IRQS305 ,IRQS Status Bit 305" "Low,High" textline " " bitfld.long 0x00 16. " IRQS304 ,IRQS Status Bit 304" "Low,High" bitfld.long 0x00 15. " IRQS303 ,IRQS Status Bit 303" "Low,High" bitfld.long 0x00 14. " IRQS302 ,IRQS Status Bit 302" "Low,High" textline " " bitfld.long 0x00 13. " IRQS301 ,IRQS Status Bit 301" "Low,High" bitfld.long 0x00 12. " IRQS300 ,IRQS Status Bit 300" "Low,High" bitfld.long 0x00 11. " IRQS299 ,IRQS Status Bit 299" "Low,High" textline " " bitfld.long 0x00 10. " IRQS298 ,IRQS Status Bit 298" "Low,High" bitfld.long 0x00 9. " IRQS297 ,IRQS Status Bit 297" "Low,High" bitfld.long 0x00 8. " IRQS296 ,IRQS Status Bit 296" "Low,High" textline " " bitfld.long 0x00 7. " IRQS295 ,IRQS Status Bit 295" "Low,High" bitfld.long 0x00 6. " IRQS294 ,IRQS Status Bit 294" "Low,High" bitfld.long 0x00 5. " IRQS293 ,IRQS Status Bit 293" "Low,High" textline " " bitfld.long 0x00 4. " IRQS292 ,IRQS Status Bit 292" "Low,High" bitfld.long 0x00 3. " IRQS291 ,IRQS Status Bit 291" "Low,High" bitfld.long 0x00 2. " IRQS290 ,IRQS Status Bit 290" "Low,High" textline " " bitfld.long 0x00 1. " IRQS289 ,IRQS Status Bit 289" "Low,High" bitfld.long 0x00 0. " IRQS288 ,IRQS Status Bit 288" "Low,High" else rgroup.long 0x0D28++0x03 line.long 0x0 "GICD_SPISR9,Shared Peripheral Interrupt Status Register 9" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x0B) rgroup.long 0x0D2C++0x03 line.long 0x0 "GICD_SPISR10,Shared Peripheral Interrupt Status Register 10" bitfld.long 0x00 31. " IRQS351 ,IRQS Status Bit 351" "Low,High" bitfld.long 0x00 30. " IRQS350 ,IRQS Status Bit 350" "Low,High" bitfld.long 0x00 29. " IRQS349 ,IRQS Status Bit 349" "Low,High" textline " " bitfld.long 0x00 28. " IRQS348 ,IRQS Status Bit 348" "Low,High" bitfld.long 0x00 27. " IRQS347 ,IRQS Status Bit 347" "Low,High" bitfld.long 0x00 26. " IRQS346 ,IRQS Status Bit 346" "Low,High" textline " " bitfld.long 0x00 25. " IRQS345 ,IRQS Status Bit 345" "Low,High" bitfld.long 0x00 24. " IRQS344 ,IRQS Status Bit 344" "Low,High" bitfld.long 0x00 23. " IRQS343 ,IRQS Status Bit 343" "Low,High" textline " " bitfld.long 0x00 22. " IRQS342 ,IRQS Status Bit 342" "Low,High" bitfld.long 0x00 21. " IRQS341 ,IRQS Status Bit 341" "Low,High" bitfld.long 0x00 20. " IRQS340 ,IRQS Status Bit 340" "Low,High" textline " " bitfld.long 0x00 19. " IRQS339 ,IRQS Status Bit 339" "Low,High" bitfld.long 0x00 18. " IRQS338 ,IRQS Status Bit 338" "Low,High" bitfld.long 0x00 17. " IRQS337 ,IRQS Status Bit 337" "Low,High" textline " " bitfld.long 0x00 16. " IRQS336 ,IRQS Status Bit 336" "Low,High" bitfld.long 0x00 15. " IRQS335 ,IRQS Status Bit 335" "Low,High" bitfld.long 0x00 14. " IRQS334 ,IRQS Status Bit 334" "Low,High" textline " " bitfld.long 0x00 13. " IRQS333 ,IRQS Status Bit 333" "Low,High" bitfld.long 0x00 12. " IRQS332 ,IRQS Status Bit 332" "Low,High" bitfld.long 0x00 11. " IRQS331 ,IRQS Status Bit 331" "Low,High" textline " " bitfld.long 0x00 10. " IRQS330 ,IRQS Status Bit 330" "Low,High" bitfld.long 0x00 9. " IRQS329 ,IRQS Status Bit 329" "Low,High" bitfld.long 0x00 8. " IRQS328 ,IRQS Status Bit 328" "Low,High" textline " " bitfld.long 0x00 7. " IRQS327 ,IRQS Status Bit 327" "Low,High" bitfld.long 0x00 6. " IRQS326 ,IRQS Status Bit 326" "Low,High" bitfld.long 0x00 5. " IRQS325 ,IRQS Status Bit 325" "Low,High" textline " " bitfld.long 0x00 4. " IRQS324 ,IRQS Status Bit 324" "Low,High" bitfld.long 0x00 3. " IRQS323 ,IRQS Status Bit 323" "Low,High" bitfld.long 0x00 2. " IRQS322 ,IRQS Status Bit 322" "Low,High" textline " " bitfld.long 0x00 1. " IRQS321 ,IRQS Status Bit 321" "Low,High" bitfld.long 0x00 0. " IRQS320 ,IRQS Status Bit 320" "Low,High" else rgroup.long 0x0D2C++0x03 line.long 0x0 "GICD_SPISR10,Shared Peripheral Interrupt Status Register 10" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x0C) rgroup.long 0x0D30++0x03 line.long 0x0 "GICD_SPISR11,Shared Peripheral Interrupt Status Register 11" bitfld.long 0x00 31. " IRQS383 ,IRQS Status Bit 383" "Low,High" bitfld.long 0x00 30. " IRQS382 ,IRQS Status Bit 382" "Low,High" bitfld.long 0x00 29. " IRQS381 ,IRQS Status Bit 381" "Low,High" textline " " bitfld.long 0x00 28. " IRQS380 ,IRQS Status Bit 380" "Low,High" bitfld.long 0x00 27. " IRQS379 ,IRQS Status Bit 379" "Low,High" bitfld.long 0x00 26. " IRQS378 ,IRQS Status Bit 378" "Low,High" textline " " bitfld.long 0x00 25. " IRQS377 ,IRQS Status Bit 377" "Low,High" bitfld.long 0x00 24. " IRQS376 ,IRQS Status Bit 376" "Low,High" bitfld.long 0x00 23. " IRQS375 ,IRQS Status Bit 375" "Low,High" textline " " bitfld.long 0x00 22. " IRQS374 ,IRQS Status Bit 374" "Low,High" bitfld.long 0x00 21. " IRQS373 ,IRQS Status Bit 373" "Low,High" bitfld.long 0x00 20. " IRQS372 ,IRQS Status Bit 372" "Low,High" textline " " bitfld.long 0x00 19. " IRQS371 ,IRQS Status Bit 371" "Low,High" bitfld.long 0x00 18. " IRQS370 ,IRQS Status Bit 370" "Low,High" bitfld.long 0x00 17. " IRQS369 ,IRQS Status Bit 369" "Low,High" textline " " bitfld.long 0x00 16. " IRQS368 ,IRQS Status Bit 368" "Low,High" bitfld.long 0x00 15. " IRQS367 ,IRQS Status Bit 367" "Low,High" bitfld.long 0x00 14. " IRQS366 ,IRQS Status Bit 366" "Low,High" textline " " bitfld.long 0x00 13. " IRQS365 ,IRQS Status Bit 365" "Low,High" bitfld.long 0x00 12. " IRQS364 ,IRQS Status Bit 364" "Low,High" bitfld.long 0x00 11. " IRQS363 ,IRQS Status Bit 363" "Low,High" textline " " bitfld.long 0x00 10. " IRQS362 ,IRQS Status Bit 362" "Low,High" bitfld.long 0x00 9. " IRQS361 ,IRQS Status Bit 361" "Low,High" bitfld.long 0x00 8. " IRQS360 ,IRQS Status Bit 360" "Low,High" textline " " bitfld.long 0x00 7. " IRQS359 ,IRQS Status Bit 359" "Low,High" bitfld.long 0x00 6. " IRQS358 ,IRQS Status Bit 358" "Low,High" bitfld.long 0x00 5. " IRQS357 ,IRQS Status Bit 357" "Low,High" textline " " bitfld.long 0x00 4. " IRQS356 ,IRQS Status Bit 356" "Low,High" bitfld.long 0x00 3. " IRQS355 ,IRQS Status Bit 355" "Low,High" bitfld.long 0x00 2. " IRQS354 ,IRQS Status Bit 354" "Low,High" textline " " bitfld.long 0x00 1. " IRQS353 ,IRQS Status Bit 353" "Low,High" bitfld.long 0x00 0. " IRQS352 ,IRQS Status Bit 352" "Low,High" else rgroup.long 0x0D30++0x03 line.long 0x0 "GICD_SPISR11,Shared Peripheral Interrupt Status Register 11" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x0D) rgroup.long 0x0D34++0x03 line.long 0x0 "GICD_SPISR12,Shared Peripheral Interrupt Status Register 12" bitfld.long 0x00 31. " IRQS415 ,IRQS Status Bit 415" "Low,High" bitfld.long 0x00 30. " IRQS414 ,IRQS Status Bit 414" "Low,High" bitfld.long 0x00 29. " IRQS413 ,IRQS Status Bit 413" "Low,High" textline " " bitfld.long 0x00 28. " IRQS412 ,IRQS Status Bit 412" "Low,High" bitfld.long 0x00 27. " IRQS411 ,IRQS Status Bit 411" "Low,High" bitfld.long 0x00 26. " IRQS410 ,IRQS Status Bit 410" "Low,High" textline " " bitfld.long 0x00 25. " IRQS409 ,IRQS Status Bit 409" "Low,High" bitfld.long 0x00 24. " IRQS408 ,IRQS Status Bit 408" "Low,High" bitfld.long 0x00 23. " IRQS407 ,IRQS Status Bit 407" "Low,High" textline " " bitfld.long 0x00 22. " IRQS406 ,IRQS Status Bit 406" "Low,High" bitfld.long 0x00 21. " IRQS405 ,IRQS Status Bit 405" "Low,High" bitfld.long 0x00 20. " IRQS404 ,IRQS Status Bit 404" "Low,High" textline " " bitfld.long 0x00 19. " IRQS403 ,IRQS Status Bit 403" "Low,High" bitfld.long 0x00 18. " IRQS402 ,IRQS Status Bit 402" "Low,High" bitfld.long 0x00 17. " IRQS401 ,IRQS Status Bit 401" "Low,High" textline " " bitfld.long 0x00 16. " IRQS400 ,IRQS Status Bit 400" "Low,High" bitfld.long 0x00 15. " IRQS399 ,IRQS Status Bit 399" "Low,High" bitfld.long 0x00 14. " IRQS398 ,IRQS Status Bit 398" "Low,High" textline " " bitfld.long 0x00 13. " IRQS397 ,IRQS Status Bit 397" "Low,High" bitfld.long 0x00 12. " IRQS396 ,IRQS Status Bit 396" "Low,High" bitfld.long 0x00 11. " IRQS395 ,IRQS Status Bit 395" "Low,High" textline " " bitfld.long 0x00 10. " IRQS394 ,IRQS Status Bit 394" "Low,High" bitfld.long 0x00 9. " IRQS393 ,IRQS Status Bit 393" "Low,High" bitfld.long 0x00 8. " IRQS392 ,IRQS Status Bit 392" "Low,High" textline " " bitfld.long 0x00 7. " IRQS391 ,IRQS Status Bit 391" "Low,High" bitfld.long 0x00 6. " IRQS390 ,IRQS Status Bit 390" "Low,High" bitfld.long 0x00 5. " IRQS389 ,IRQS Status Bit 389" "Low,High" textline " " bitfld.long 0x00 4. " IRQS388 ,IRQS Status Bit 388" "Low,High" bitfld.long 0x00 3. " IRQS387 ,IRQS Status Bit 387" "Low,High" bitfld.long 0x00 2. " IRQS386 ,IRQS Status Bit 386" "Low,High" textline " " bitfld.long 0x00 1. " IRQS385 ,IRQS Status Bit 385" "Low,High" bitfld.long 0x00 0. " IRQS384 ,IRQS Status Bit 384" "Low,High" else rgroup.long 0x0D34++0x03 line.long 0x0 "GICD_SPISR12,Shared Peripheral Interrupt Status Register 12" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x0E) rgroup.long 0x0D38++0x03 line.long 0x0 "GICD_SPISR13,Shared Peripheral Interrupt Status Register 13" bitfld.long 0x00 31. " IRQS447 ,IRQS Status Bit 447" "Low,High" bitfld.long 0x00 30. " IRQS446 ,IRQS Status Bit 446" "Low,High" bitfld.long 0x00 29. " IRQS445 ,IRQS Status Bit 445" "Low,High" textline " " bitfld.long 0x00 28. " IRQS444 ,IRQS Status Bit 444" "Low,High" bitfld.long 0x00 27. " IRQS443 ,IRQS Status Bit 443" "Low,High" bitfld.long 0x00 26. " IRQS442 ,IRQS Status Bit 442" "Low,High" textline " " bitfld.long 0x00 25. " IRQS441 ,IRQS Status Bit 441" "Low,High" bitfld.long 0x00 24. " IRQS440 ,IRQS Status Bit 440" "Low,High" bitfld.long 0x00 23. " IRQS439 ,IRQS Status Bit 439" "Low,High" textline " " bitfld.long 0x00 22. " IRQS438 ,IRQS Status Bit 438" "Low,High" bitfld.long 0x00 21. " IRQS437 ,IRQS Status Bit 437" "Low,High" bitfld.long 0x00 20. " IRQS436 ,IRQS Status Bit 436" "Low,High" textline " " bitfld.long 0x00 19. " IRQS435 ,IRQS Status Bit 435" "Low,High" bitfld.long 0x00 18. " IRQS434 ,IRQS Status Bit 434" "Low,High" bitfld.long 0x00 17. " IRQS433 ,IRQS Status Bit 433" "Low,High" textline " " bitfld.long 0x00 16. " IRQS432 ,IRQS Status Bit 432" "Low,High" bitfld.long 0x00 15. " IRQS431 ,IRQS Status Bit 431" "Low,High" bitfld.long 0x00 14. " IRQS430 ,IRQS Status Bit 430" "Low,High" textline " " bitfld.long 0x00 13. " IRQS429 ,IRQS Status Bit 429" "Low,High" bitfld.long 0x00 12. " IRQS428 ,IRQS Status Bit 428" "Low,High" bitfld.long 0x00 11. " IRQS427 ,IRQS Status Bit 427" "Low,High" textline " " bitfld.long 0x00 10. " IRQS426 ,IRQS Status Bit 426" "Low,High" bitfld.long 0x00 9. " IRQS425 ,IRQS Status Bit 425" "Low,High" bitfld.long 0x00 8. " IRQS424 ,IRQS Status Bit 424" "Low,High" textline " " bitfld.long 0x00 7. " IRQS423 ,IRQS Status Bit 423" "Low,High" bitfld.long 0x00 6. " IRQS422 ,IRQS Status Bit 422" "Low,High" bitfld.long 0x00 5. " IRQS421 ,IRQS Status Bit 421" "Low,High" textline " " bitfld.long 0x00 4. " IRQS420 ,IRQS Status Bit 420" "Low,High" bitfld.long 0x00 3. " IRQS419 ,IRQS Status Bit 419" "Low,High" bitfld.long 0x00 2. " IRQS418 ,IRQS Status Bit 418" "Low,High" textline " " bitfld.long 0x00 1. " IRQS417 ,IRQS Status Bit 417" "Low,High" bitfld.long 0x00 0. " IRQS416 ,IRQS Status Bit 416" "Low,High" else rgroup.long 0x0D38++0x03 line.long 0x0 "GICD_SPISR13,Shared Peripheral Interrupt Status Register 13" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x0F) rgroup.long 0x0D3C++0x03 line.long 0x0 "GICD_SPISR14,Shared Peripheral Interrupt Status Register 14" bitfld.long 0x00 31. " IRQS479 ,IRQS Status Bit 479" "Low,High" bitfld.long 0x00 30. " IRQS478 ,IRQS Status Bit 478" "Low,High" bitfld.long 0x00 29. " IRQS477 ,IRQS Status Bit 477" "Low,High" textline " " bitfld.long 0x00 28. " IRQS476 ,IRQS Status Bit 476" "Low,High" bitfld.long 0x00 27. " IRQS475 ,IRQS Status Bit 475" "Low,High" bitfld.long 0x00 26. " IRQS474 ,IRQS Status Bit 474" "Low,High" textline " " bitfld.long 0x00 25. " IRQS473 ,IRQS Status Bit 473" "Low,High" bitfld.long 0x00 24. " IRQS472 ,IRQS Status Bit 472" "Low,High" bitfld.long 0x00 23. " IRQS471 ,IRQS Status Bit 471" "Low,High" textline " " bitfld.long 0x00 22. " IRQS470 ,IRQS Status Bit 470" "Low,High" bitfld.long 0x00 21. " IRQS469 ,IRQS Status Bit 469" "Low,High" bitfld.long 0x00 20. " IRQS468 ,IRQS Status Bit 468" "Low,High" textline " " bitfld.long 0x00 19. " IRQS467 ,IRQS Status Bit 467" "Low,High" bitfld.long 0x00 18. " IRQS466 ,IRQS Status Bit 466" "Low,High" bitfld.long 0x00 17. " IRQS465 ,IRQS Status Bit 465" "Low,High" textline " " bitfld.long 0x00 16. " IRQS464 ,IRQS Status Bit 464" "Low,High" bitfld.long 0x00 15. " IRQS463 ,IRQS Status Bit 463" "Low,High" bitfld.long 0x00 14. " IRQS462 ,IRQS Status Bit 462" "Low,High" textline " " bitfld.long 0x00 13. " IRQS461 ,IRQS Status Bit 461" "Low,High" bitfld.long 0x00 12. " IRQS460 ,IRQS Status Bit 460" "Low,High" bitfld.long 0x00 11. " IRQS459 ,IRQS Status Bit 459" "Low,High" textline " " bitfld.long 0x00 10. " IRQS458 ,IRQS Status Bit 458" "Low,High" bitfld.long 0x00 9. " IRQS457 ,IRQS Status Bit 457" "Low,High" bitfld.long 0x00 8. " IRQS456 ,IRQS Status Bit 456" "Low,High" textline " " bitfld.long 0x00 7. " IRQS455 ,IRQS Status Bit 455" "Low,High" bitfld.long 0x00 6. " IRQS454 ,IRQS Status Bit 454" "Low,High" bitfld.long 0x00 5. " IRQS453 ,IRQS Status Bit 453" "Low,High" textline " " bitfld.long 0x00 4. " IRQS452 ,IRQS Status Bit 452" "Low,High" bitfld.long 0x00 3. " IRQS451 ,IRQS Status Bit 451" "Low,High" bitfld.long 0x00 2. " IRQS450 ,IRQS Status Bit 450" "Low,High" textline " " bitfld.long 0x00 1. " IRQS449 ,IRQS Status Bit 449" "Low,High" bitfld.long 0x00 0. " IRQS448 ,IRQS Status Bit 448" "Low,High" else rgroup.long 0x0D3C++0x03 line.long 0x0 "GICD_SPISR14,Shared Peripheral Interrupt Status Register 14" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x10) rgroup.long 0x0D40++0x03 line.long 0x0 "GICD_SPISR15,Shared Peripheral Interrupt Status Register 15" bitfld.long 0x00 31. " IRQS511 ,IRQS Status Bit 511" "Low,High" bitfld.long 0x00 30. " IRQS510 ,IRQS Status Bit 510" "Low,High" bitfld.long 0x00 29. " IRQS509 ,IRQS Status Bit 509" "Low,High" textline " " bitfld.long 0x00 28. " IRQS508 ,IRQS Status Bit 508" "Low,High" bitfld.long 0x00 27. " IRQS507 ,IRQS Status Bit 507" "Low,High" bitfld.long 0x00 26. " IRQS506 ,IRQS Status Bit 506" "Low,High" textline " " bitfld.long 0x00 25. " IRQS505 ,IRQS Status Bit 505" "Low,High" bitfld.long 0x00 24. " IRQS504 ,IRQS Status Bit 504" "Low,High" bitfld.long 0x00 23. " IRQS503 ,IRQS Status Bit 503" "Low,High" textline " " bitfld.long 0x00 22. " IRQS502 ,IRQS Status Bit 502" "Low,High" bitfld.long 0x00 21. " IRQS501 ,IRQS Status Bit 501" "Low,High" bitfld.long 0x00 20. " IRQS500 ,IRQS Status Bit 500" "Low,High" textline " " bitfld.long 0x00 19. " IRQS499 ,IRQS Status Bit 499" "Low,High" bitfld.long 0x00 18. " IRQS498 ,IRQS Status Bit 498" "Low,High" bitfld.long 0x00 17. " IRQS497 ,IRQS Status Bit 497" "Low,High" textline " " bitfld.long 0x00 16. " IRQS496 ,IRQS Status Bit 496" "Low,High" bitfld.long 0x00 15. " IRQS495 ,IRQS Status Bit 495" "Low,High" bitfld.long 0x00 14. " IRQS494 ,IRQS Status Bit 494" "Low,High" textline " " bitfld.long 0x00 13. " IRQS493 ,IRQS Status Bit 493" "Low,High" bitfld.long 0x00 12. " IRQS492 ,IRQS Status Bit 492" "Low,High" bitfld.long 0x00 11. " IRQS491 ,IRQS Status Bit 491" "Low,High" textline " " bitfld.long 0x00 10. " IRQS490 ,IRQS Status Bit 490" "Low,High" bitfld.long 0x00 9. " IRQS489 ,IRQS Status Bit 489" "Low,High" bitfld.long 0x00 8. " IRQS488 ,IRQS Status Bit 488" "Low,High" textline " " bitfld.long 0x00 7. " IRQS487 ,IRQS Status Bit 487" "Low,High" bitfld.long 0x00 6. " IRQS486 ,IRQS Status Bit 486" "Low,High" bitfld.long 0x00 5. " IRQS485 ,IRQS Status Bit 485" "Low,High" textline " " bitfld.long 0x00 4. " IRQS484 ,IRQS Status Bit 484" "Low,High" bitfld.long 0x00 3. " IRQS483 ,IRQS Status Bit 483" "Low,High" bitfld.long 0x00 2. " IRQS482 ,IRQS Status Bit 482" "Low,High" textline " " bitfld.long 0x00 1. " IRQS481 ,IRQS Status Bit 481" "Low,High" bitfld.long 0x00 0. " IRQS480 ,IRQS Status Bit 480" "Low,High" else rgroup.long 0x0D40++0x03 line.long 0x0 "GICD_SPISR15,Shared Peripheral Interrupt Status Register 15" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x11) rgroup.long 0x0D44++0x03 line.long 0x0 "GICD_SPISR16,Shared Peripheral Interrupt Status Register 16" bitfld.long 0x00 31. " IRQS543 ,IRQS Status Bit 543" "Low,High" bitfld.long 0x00 30. " IRQS542 ,IRQS Status Bit 542" "Low,High" bitfld.long 0x00 29. " IRQS541 ,IRQS Status Bit 541" "Low,High" textline " " bitfld.long 0x00 28. " IRQS540 ,IRQS Status Bit 540" "Low,High" bitfld.long 0x00 27. " IRQS539 ,IRQS Status Bit 539" "Low,High" bitfld.long 0x00 26. " IRQS538 ,IRQS Status Bit 538" "Low,High" textline " " bitfld.long 0x00 25. " IRQS537 ,IRQS Status Bit 537" "Low,High" bitfld.long 0x00 24. " IRQS536 ,IRQS Status Bit 536" "Low,High" bitfld.long 0x00 23. " IRQS535 ,IRQS Status Bit 535" "Low,High" textline " " bitfld.long 0x00 22. " IRQS534 ,IRQS Status Bit 534" "Low,High" bitfld.long 0x00 21. " IRQS533 ,IRQS Status Bit 533" "Low,High" bitfld.long 0x00 20. " IRQS532 ,IRQS Status Bit 532" "Low,High" textline " " bitfld.long 0x00 19. " IRQS531 ,IRQS Status Bit 531" "Low,High" bitfld.long 0x00 18. " IRQS530 ,IRQS Status Bit 530" "Low,High" bitfld.long 0x00 17. " IRQS529 ,IRQS Status Bit 529" "Low,High" textline " " bitfld.long 0x00 16. " IRQS528 ,IRQS Status Bit 528" "Low,High" bitfld.long 0x00 15. " IRQS527 ,IRQS Status Bit 527" "Low,High" bitfld.long 0x00 14. " IRQS526 ,IRQS Status Bit 526" "Low,High" textline " " bitfld.long 0x00 13. " IRQS525 ,IRQS Status Bit 525" "Low,High" bitfld.long 0x00 12. " IRQS524 ,IRQS Status Bit 524" "Low,High" bitfld.long 0x00 11. " IRQS523 ,IRQS Status Bit 523" "Low,High" textline " " bitfld.long 0x00 10. " IRQS522 ,IRQS Status Bit 522" "Low,High" bitfld.long 0x00 9. " IRQS521 ,IRQS Status Bit 521" "Low,High" bitfld.long 0x00 8. " IRQS520 ,IRQS Status Bit 520" "Low,High" textline " " bitfld.long 0x00 7. " IRQS519 ,IRQS Status Bit 519" "Low,High" bitfld.long 0x00 6. " IRQS518 ,IRQS Status Bit 518" "Low,High" bitfld.long 0x00 5. " IRQS517 ,IRQS Status Bit 517" "Low,High" textline " " bitfld.long 0x00 4. " IRQS516 ,IRQS Status Bit 516" "Low,High" bitfld.long 0x00 3. " IRQS515 ,IRQS Status Bit 515" "Low,High" bitfld.long 0x00 2. " IRQS514 ,IRQS Status Bit 514" "Low,High" textline " " bitfld.long 0x00 1. " IRQS513 ,IRQS Status Bit 513" "Low,High" bitfld.long 0x00 0. " IRQS512 ,IRQS Status Bit 512" "Low,High" else rgroup.long 0x0D44++0x03 line.long 0x0 "GICD_SPISR16,Shared Peripheral Interrupt Status Register 16" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x12) rgroup.long 0x0D48++0x03 line.long 0x0 "GICD_SPISR17,Shared Peripheral Interrupt Status Register 17" bitfld.long 0x00 31. " IRQS575 ,IRQS Status Bit 575" "Low,High" bitfld.long 0x00 30. " IRQS574 ,IRQS Status Bit 574" "Low,High" bitfld.long 0x00 29. " IRQS573 ,IRQS Status Bit 573" "Low,High" textline " " bitfld.long 0x00 28. " IRQS572 ,IRQS Status Bit 572" "Low,High" bitfld.long 0x00 27. " IRQS571 ,IRQS Status Bit 571" "Low,High" bitfld.long 0x00 26. " IRQS570 ,IRQS Status Bit 570" "Low,High" textline " " bitfld.long 0x00 25. " IRQS569 ,IRQS Status Bit 569" "Low,High" bitfld.long 0x00 24. " IRQS568 ,IRQS Status Bit 568" "Low,High" bitfld.long 0x00 23. " IRQS567 ,IRQS Status Bit 567" "Low,High" textline " " bitfld.long 0x00 22. " IRQS566 ,IRQS Status Bit 566" "Low,High" bitfld.long 0x00 21. " IRQS565 ,IRQS Status Bit 565" "Low,High" bitfld.long 0x00 20. " IRQS564 ,IRQS Status Bit 564" "Low,High" textline " " bitfld.long 0x00 19. " IRQS563 ,IRQS Status Bit 563" "Low,High" bitfld.long 0x00 18. " IRQS562 ,IRQS Status Bit 562" "Low,High" bitfld.long 0x00 17. " IRQS561 ,IRQS Status Bit 561" "Low,High" textline " " bitfld.long 0x00 16. " IRQS560 ,IRQS Status Bit 560" "Low,High" bitfld.long 0x00 15. " IRQS559 ,IRQS Status Bit 559" "Low,High" bitfld.long 0x00 14. " IRQS558 ,IRQS Status Bit 558" "Low,High" textline " " bitfld.long 0x00 13. " IRQS557 ,IRQS Status Bit 557" "Low,High" bitfld.long 0x00 12. " IRQS556 ,IRQS Status Bit 556" "Low,High" bitfld.long 0x00 11. " IRQS555 ,IRQS Status Bit 555" "Low,High" textline " " bitfld.long 0x00 10. " IRQS554 ,IRQS Status Bit 554" "Low,High" bitfld.long 0x00 9. " IRQS553 ,IRQS Status Bit 553" "Low,High" bitfld.long 0x00 8. " IRQS552 ,IRQS Status Bit 552" "Low,High" textline " " bitfld.long 0x00 7. " IRQS551 ,IRQS Status Bit 551" "Low,High" bitfld.long 0x00 6. " IRQS550 ,IRQS Status Bit 550" "Low,High" bitfld.long 0x00 5. " IRQS549 ,IRQS Status Bit 549" "Low,High" textline " " bitfld.long 0x00 4. " IRQS548 ,IRQS Status Bit 548" "Low,High" bitfld.long 0x00 3. " IRQS547 ,IRQS Status Bit 547" "Low,High" bitfld.long 0x00 2. " IRQS546 ,IRQS Status Bit 546" "Low,High" textline " " bitfld.long 0x00 1. " IRQS545 ,IRQS Status Bit 545" "Low,High" bitfld.long 0x00 0. " IRQS544 ,IRQS Status Bit 544" "Low,High" else rgroup.long 0x0D48++0x03 line.long 0x0 "GICD_SPISR17,Shared Peripheral Interrupt Status Register 17" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x13) rgroup.long 0x0D4C++0x03 line.long 0x0 "GICD_SPISR18,Shared Peripheral Interrupt Status Register 18" bitfld.long 0x00 31. " IRQS607 ,IRQS Status Bit 607" "Low,High" bitfld.long 0x00 30. " IRQS606 ,IRQS Status Bit 606" "Low,High" bitfld.long 0x00 29. " IRQS605 ,IRQS Status Bit 605" "Low,High" textline " " bitfld.long 0x00 28. " IRQS604 ,IRQS Status Bit 604" "Low,High" bitfld.long 0x00 27. " IRQS603 ,IRQS Status Bit 603" "Low,High" bitfld.long 0x00 26. " IRQS602 ,IRQS Status Bit 602" "Low,High" textline " " bitfld.long 0x00 25. " IRQS601 ,IRQS Status Bit 601" "Low,High" bitfld.long 0x00 24. " IRQS600 ,IRQS Status Bit 600" "Low,High" bitfld.long 0x00 23. " IRQS599 ,IRQS Status Bit 599" "Low,High" textline " " bitfld.long 0x00 22. " IRQS598 ,IRQS Status Bit 598" "Low,High" bitfld.long 0x00 21. " IRQS597 ,IRQS Status Bit 597" "Low,High" bitfld.long 0x00 20. " IRQS596 ,IRQS Status Bit 596" "Low,High" textline " " bitfld.long 0x00 19. " IRQS595 ,IRQS Status Bit 595" "Low,High" bitfld.long 0x00 18. " IRQS594 ,IRQS Status Bit 594" "Low,High" bitfld.long 0x00 17. " IRQS593 ,IRQS Status Bit 593" "Low,High" textline " " bitfld.long 0x00 16. " IRQS592 ,IRQS Status Bit 592" "Low,High" bitfld.long 0x00 15. " IRQS591 ,IRQS Status Bit 591" "Low,High" bitfld.long 0x00 14. " IRQS590 ,IRQS Status Bit 590" "Low,High" textline " " bitfld.long 0x00 13. " IRQS589 ,IRQS Status Bit 589" "Low,High" bitfld.long 0x00 12. " IRQS588 ,IRQS Status Bit 588" "Low,High" bitfld.long 0x00 11. " IRQS587 ,IRQS Status Bit 587" "Low,High" textline " " bitfld.long 0x00 10. " IRQS586 ,IRQS Status Bit 586" "Low,High" bitfld.long 0x00 9. " IRQS585 ,IRQS Status Bit 585" "Low,High" bitfld.long 0x00 8. " IRQS584 ,IRQS Status Bit 584" "Low,High" textline " " bitfld.long 0x00 7. " IRQS583 ,IRQS Status Bit 583" "Low,High" bitfld.long 0x00 6. " IRQS582 ,IRQS Status Bit 582" "Low,High" bitfld.long 0x00 5. " IRQS581 ,IRQS Status Bit 581" "Low,High" textline " " bitfld.long 0x00 4. " IRQS580 ,IRQS Status Bit 580" "Low,High" bitfld.long 0x00 3. " IRQS579 ,IRQS Status Bit 579" "Low,High" bitfld.long 0x00 2. " IRQS578 ,IRQS Status Bit 578" "Low,High" textline " " bitfld.long 0x00 1. " IRQS577 ,IRQS Status Bit 577" "Low,High" bitfld.long 0x00 0. " IRQS576 ,IRQS Status Bit 576" "Low,High" else rgroup.long 0x0D4C++0x03 line.long 0x0 "GICD_SPISR18,Shared Peripheral Interrupt Status Register 18" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x14) rgroup.long 0x0D50++0x03 line.long 0x0 "GICD_SPISR19,Shared Peripheral Interrupt Status Register 19" bitfld.long 0x00 31. " IRQS639 ,IRQS Status Bit 639" "Low,High" bitfld.long 0x00 30. " IRQS638 ,IRQS Status Bit 638" "Low,High" bitfld.long 0x00 29. " IRQS637 ,IRQS Status Bit 637" "Low,High" textline " " bitfld.long 0x00 28. " IRQS636 ,IRQS Status Bit 636" "Low,High" bitfld.long 0x00 27. " IRQS635 ,IRQS Status Bit 635" "Low,High" bitfld.long 0x00 26. " IRQS634 ,IRQS Status Bit 634" "Low,High" textline " " bitfld.long 0x00 25. " IRQS633 ,IRQS Status Bit 633" "Low,High" bitfld.long 0x00 24. " IRQS632 ,IRQS Status Bit 632" "Low,High" bitfld.long 0x00 23. " IRQS631 ,IRQS Status Bit 631" "Low,High" textline " " bitfld.long 0x00 22. " IRQS630 ,IRQS Status Bit 630" "Low,High" bitfld.long 0x00 21. " IRQS629 ,IRQS Status Bit 629" "Low,High" bitfld.long 0x00 20. " IRQS628 ,IRQS Status Bit 628" "Low,High" textline " " bitfld.long 0x00 19. " IRQS627 ,IRQS Status Bit 627" "Low,High" bitfld.long 0x00 18. " IRQS626 ,IRQS Status Bit 626" "Low,High" bitfld.long 0x00 17. " IRQS625 ,IRQS Status Bit 625" "Low,High" textline " " bitfld.long 0x00 16. " IRQS624 ,IRQS Status Bit 624" "Low,High" bitfld.long 0x00 15. " IRQS623 ,IRQS Status Bit 623" "Low,High" bitfld.long 0x00 14. " IRQS622 ,IRQS Status Bit 622" "Low,High" textline " " bitfld.long 0x00 13. " IRQS621 ,IRQS Status Bit 621" "Low,High" bitfld.long 0x00 12. " IRQS620 ,IRQS Status Bit 620" "Low,High" bitfld.long 0x00 11. " IRQS619 ,IRQS Status Bit 619" "Low,High" textline " " bitfld.long 0x00 10. " IRQS618 ,IRQS Status Bit 618" "Low,High" bitfld.long 0x00 9. " IRQS617 ,IRQS Status Bit 617" "Low,High" bitfld.long 0x00 8. " IRQS616 ,IRQS Status Bit 616" "Low,High" textline " " bitfld.long 0x00 7. " IRQS615 ,IRQS Status Bit 615" "Low,High" bitfld.long 0x00 6. " IRQS614 ,IRQS Status Bit 614" "Low,High" bitfld.long 0x00 5. " IRQS613 ,IRQS Status Bit 613" "Low,High" textline " " bitfld.long 0x00 4. " IRQS612 ,IRQS Status Bit 612" "Low,High" bitfld.long 0x00 3. " IRQS611 ,IRQS Status Bit 611" "Low,High" bitfld.long 0x00 2. " IRQS610 ,IRQS Status Bit 610" "Low,High" textline " " bitfld.long 0x00 1. " IRQS609 ,IRQS Status Bit 609" "Low,High" bitfld.long 0x00 0. " IRQS608 ,IRQS Status Bit 608" "Low,High" else rgroup.long 0x0D50++0x03 line.long 0x0 "GICD_SPISR19,Shared Peripheral Interrupt Status Register 19" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x15) rgroup.long 0x0D54++0x03 line.long 0x0 "GICD_SPISR20,Shared Peripheral Interrupt Status Register 20" bitfld.long 0x00 31. " IRQS671 ,IRQS Status Bit 671" "Low,High" bitfld.long 0x00 30. " IRQS670 ,IRQS Status Bit 670" "Low,High" bitfld.long 0x00 29. " IRQS669 ,IRQS Status Bit 669" "Low,High" textline " " bitfld.long 0x00 28. " IRQS668 ,IRQS Status Bit 668" "Low,High" bitfld.long 0x00 27. " IRQS667 ,IRQS Status Bit 667" "Low,High" bitfld.long 0x00 26. " IRQS666 ,IRQS Status Bit 666" "Low,High" textline " " bitfld.long 0x00 25. " IRQS665 ,IRQS Status Bit 665" "Low,High" bitfld.long 0x00 24. " IRQS664 ,IRQS Status Bit 664" "Low,High" bitfld.long 0x00 23. " IRQS663 ,IRQS Status Bit 663" "Low,High" textline " " bitfld.long 0x00 22. " IRQS662 ,IRQS Status Bit 662" "Low,High" bitfld.long 0x00 21. " IRQS661 ,IRQS Status Bit 661" "Low,High" bitfld.long 0x00 20. " IRQS660 ,IRQS Status Bit 660" "Low,High" textline " " bitfld.long 0x00 19. " IRQS659 ,IRQS Status Bit 659" "Low,High" bitfld.long 0x00 18. " IRQS658 ,IRQS Status Bit 658" "Low,High" bitfld.long 0x00 17. " IRQS657 ,IRQS Status Bit 657" "Low,High" textline " " bitfld.long 0x00 16. " IRQS656 ,IRQS Status Bit 656" "Low,High" bitfld.long 0x00 15. " IRQS655 ,IRQS Status Bit 655" "Low,High" bitfld.long 0x00 14. " IRQS654 ,IRQS Status Bit 654" "Low,High" textline " " bitfld.long 0x00 13. " IRQS653 ,IRQS Status Bit 653" "Low,High" bitfld.long 0x00 12. " IRQS652 ,IRQS Status Bit 652" "Low,High" bitfld.long 0x00 11. " IRQS651 ,IRQS Status Bit 651" "Low,High" textline " " bitfld.long 0x00 10. " IRQS650 ,IRQS Status Bit 650" "Low,High" bitfld.long 0x00 9. " IRQS649 ,IRQS Status Bit 649" "Low,High" bitfld.long 0x00 8. " IRQS648 ,IRQS Status Bit 648" "Low,High" textline " " bitfld.long 0x00 7. " IRQS647 ,IRQS Status Bit 647" "Low,High" bitfld.long 0x00 6. " IRQS646 ,IRQS Status Bit 646" "Low,High" bitfld.long 0x00 5. " IRQS645 ,IRQS Status Bit 645" "Low,High" textline " " bitfld.long 0x00 4. " IRQS644 ,IRQS Status Bit 644" "Low,High" bitfld.long 0x00 3. " IRQS643 ,IRQS Status Bit 643" "Low,High" bitfld.long 0x00 2. " IRQS642 ,IRQS Status Bit 642" "Low,High" textline " " bitfld.long 0x00 1. " IRQS641 ,IRQS Status Bit 641" "Low,High" bitfld.long 0x00 0. " IRQS640 ,IRQS Status Bit 640" "Low,High" else rgroup.long 0x0D54++0x03 line.long 0x0 "GICD_SPISR20,Shared Peripheral Interrupt Status Register 20" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x16) rgroup.long 0x0D58++0x03 line.long 0x0 "GICD_SPISR21,Shared Peripheral Interrupt Status Register 21" bitfld.long 0x00 31. " IRQS703 ,IRQS Status Bit 703" "Low,High" bitfld.long 0x00 30. " IRQS702 ,IRQS Status Bit 702" "Low,High" bitfld.long 0x00 29. " IRQS701 ,IRQS Status Bit 701" "Low,High" textline " " bitfld.long 0x00 28. " IRQS700 ,IRQS Status Bit 700" "Low,High" bitfld.long 0x00 27. " IRQS699 ,IRQS Status Bit 699" "Low,High" bitfld.long 0x00 26. " IRQS698 ,IRQS Status Bit 698" "Low,High" textline " " bitfld.long 0x00 25. " IRQS697 ,IRQS Status Bit 697" "Low,High" bitfld.long 0x00 24. " IRQS696 ,IRQS Status Bit 696" "Low,High" bitfld.long 0x00 23. " IRQS695 ,IRQS Status Bit 695" "Low,High" textline " " bitfld.long 0x00 22. " IRQS694 ,IRQS Status Bit 694" "Low,High" bitfld.long 0x00 21. " IRQS693 ,IRQS Status Bit 693" "Low,High" bitfld.long 0x00 20. " IRQS692 ,IRQS Status Bit 692" "Low,High" textline " " bitfld.long 0x00 19. " IRQS691 ,IRQS Status Bit 691" "Low,High" bitfld.long 0x00 18. " IRQS690 ,IRQS Status Bit 690" "Low,High" bitfld.long 0x00 17. " IRQS689 ,IRQS Status Bit 689" "Low,High" textline " " bitfld.long 0x00 16. " IRQS688 ,IRQS Status Bit 688" "Low,High" bitfld.long 0x00 15. " IRQS687 ,IRQS Status Bit 687" "Low,High" bitfld.long 0x00 14. " IRQS686 ,IRQS Status Bit 686" "Low,High" textline " " bitfld.long 0x00 13. " IRQS685 ,IRQS Status Bit 685" "Low,High" bitfld.long 0x00 12. " IRQS684 ,IRQS Status Bit 684" "Low,High" bitfld.long 0x00 11. " IRQS683 ,IRQS Status Bit 683" "Low,High" textline " " bitfld.long 0x00 10. " IRQS682 ,IRQS Status Bit 682" "Low,High" bitfld.long 0x00 9. " IRQS681 ,IRQS Status Bit 681" "Low,High" bitfld.long 0x00 8. " IRQS680 ,IRQS Status Bit 680" "Low,High" textline " " bitfld.long 0x00 7. " IRQS679 ,IRQS Status Bit 679" "Low,High" bitfld.long 0x00 6. " IRQS678 ,IRQS Status Bit 678" "Low,High" bitfld.long 0x00 5. " IRQS677 ,IRQS Status Bit 677" "Low,High" textline " " bitfld.long 0x00 4. " IRQS676 ,IRQS Status Bit 676" "Low,High" bitfld.long 0x00 3. " IRQS675 ,IRQS Status Bit 675" "Low,High" bitfld.long 0x00 2. " IRQS674 ,IRQS Status Bit 674" "Low,High" textline " " bitfld.long 0x00 1. " IRQS673 ,IRQS Status Bit 673" "Low,High" bitfld.long 0x00 0. " IRQS672 ,IRQS Status Bit 672" "Low,High" else rgroup.long 0x0D58++0x03 line.long 0x0 "GICD_SPISR21,Shared Peripheral Interrupt Status Register 21" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x17) rgroup.long 0x0D5C++0x03 line.long 0x0 "GICD_SPISR22,Shared Peripheral Interrupt Status Register 22" bitfld.long 0x00 31. " IRQS735 ,IRQS Status Bit 735" "Low,High" bitfld.long 0x00 30. " IRQS734 ,IRQS Status Bit 734" "Low,High" bitfld.long 0x00 29. " IRQS733 ,IRQS Status Bit 733" "Low,High" textline " " bitfld.long 0x00 28. " IRQS732 ,IRQS Status Bit 732" "Low,High" bitfld.long 0x00 27. " IRQS731 ,IRQS Status Bit 731" "Low,High" bitfld.long 0x00 26. " IRQS730 ,IRQS Status Bit 730" "Low,High" textline " " bitfld.long 0x00 25. " IRQS729 ,IRQS Status Bit 729" "Low,High" bitfld.long 0x00 24. " IRQS728 ,IRQS Status Bit 728" "Low,High" bitfld.long 0x00 23. " IRQS727 ,IRQS Status Bit 727" "Low,High" textline " " bitfld.long 0x00 22. " IRQS726 ,IRQS Status Bit 726" "Low,High" bitfld.long 0x00 21. " IRQS725 ,IRQS Status Bit 725" "Low,High" bitfld.long 0x00 20. " IRQS724 ,IRQS Status Bit 724" "Low,High" textline " " bitfld.long 0x00 19. " IRQS723 ,IRQS Status Bit 723" "Low,High" bitfld.long 0x00 18. " IRQS722 ,IRQS Status Bit 722" "Low,High" bitfld.long 0x00 17. " IRQS721 ,IRQS Status Bit 721" "Low,High" textline " " bitfld.long 0x00 16. " IRQS720 ,IRQS Status Bit 720" "Low,High" bitfld.long 0x00 15. " IRQS719 ,IRQS Status Bit 719" "Low,High" bitfld.long 0x00 14. " IRQS718 ,IRQS Status Bit 718" "Low,High" textline " " bitfld.long 0x00 13. " IRQS717 ,IRQS Status Bit 717" "Low,High" bitfld.long 0x00 12. " IRQS716 ,IRQS Status Bit 716" "Low,High" bitfld.long 0x00 11. " IRQS715 ,IRQS Status Bit 715" "Low,High" textline " " bitfld.long 0x00 10. " IRQS714 ,IRQS Status Bit 714" "Low,High" bitfld.long 0x00 9. " IRQS713 ,IRQS Status Bit 713" "Low,High" bitfld.long 0x00 8. " IRQS712 ,IRQS Status Bit 712" "Low,High" textline " " bitfld.long 0x00 7. " IRQS711 ,IRQS Status Bit 711" "Low,High" bitfld.long 0x00 6. " IRQS710 ,IRQS Status Bit 710" "Low,High" bitfld.long 0x00 5. " IRQS709 ,IRQS Status Bit 709" "Low,High" textline " " bitfld.long 0x00 4. " IRQS708 ,IRQS Status Bit 708" "Low,High" bitfld.long 0x00 3. " IRQS707 ,IRQS Status Bit 707" "Low,High" bitfld.long 0x00 2. " IRQS706 ,IRQS Status Bit 706" "Low,High" textline " " bitfld.long 0x00 1. " IRQS705 ,IRQS Status Bit 705" "Low,High" bitfld.long 0x00 0. " IRQS704 ,IRQS Status Bit 704" "Low,High" else rgroup.long 0x0D5C++0x03 line.long 0x0 "GICD_SPISR22,Shared Peripheral Interrupt Status Register 22" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x18) rgroup.long 0x060++0x03 line.long 0x0 "GICD_SPISR23,Shared Peripheral Interrupt Status Register 23" bitfld.long 0x00 31. " IRQS767 ,IRQS Status Bit 767" "Low,High" bitfld.long 0x00 30. " IRQS766 ,IRQS Status Bit 766" "Low,High" bitfld.long 0x00 29. " IRQS765 ,IRQS Status Bit 765" "Low,High" textline " " bitfld.long 0x00 28. " IRQS764 ,IRQS Status Bit 764" "Low,High" bitfld.long 0x00 27. " IRQS763 ,IRQS Status Bit 763" "Low,High" bitfld.long 0x00 26. " IRQS762 ,IRQS Status Bit 762" "Low,High" textline " " bitfld.long 0x00 25. " IRQS761 ,IRQS Status Bit 761" "Low,High" bitfld.long 0x00 24. " IRQS760 ,IRQS Status Bit 760" "Low,High" bitfld.long 0x00 23. " IRQS759 ,IRQS Status Bit 759" "Low,High" textline " " bitfld.long 0x00 22. " IRQS758 ,IRQS Status Bit 758" "Low,High" bitfld.long 0x00 21. " IRQS757 ,IRQS Status Bit 757" "Low,High" bitfld.long 0x00 20. " IRQS756 ,IRQS Status Bit 756" "Low,High" textline " " bitfld.long 0x00 19. " IRQS755 ,IRQS Status Bit 755" "Low,High" bitfld.long 0x00 18. " IRQS754 ,IRQS Status Bit 754" "Low,High" bitfld.long 0x00 17. " IRQS753 ,IRQS Status Bit 753" "Low,High" textline " " bitfld.long 0x00 16. " IRQS752 ,IRQS Status Bit 752" "Low,High" bitfld.long 0x00 15. " IRQS751 ,IRQS Status Bit 751" "Low,High" bitfld.long 0x00 14. " IRQS750 ,IRQS Status Bit 750" "Low,High" textline " " bitfld.long 0x00 13. " IRQS749 ,IRQS Status Bit 749" "Low,High" bitfld.long 0x00 12. " IRQS748 ,IRQS Status Bit 748" "Low,High" bitfld.long 0x00 11. " IRQS747 ,IRQS Status Bit 747" "Low,High" textline " " bitfld.long 0x00 10. " IRQS746 ,IRQS Status Bit 746" "Low,High" bitfld.long 0x00 9. " IRQS745 ,IRQS Status Bit 745" "Low,High" bitfld.long 0x00 8. " IRQS744 ,IRQS Status Bit 744" "Low,High" textline " " bitfld.long 0x00 7. " IRQS743 ,IRQS Status Bit 743" "Low,High" bitfld.long 0x00 6. " IRQS742 ,IRQS Status Bit 742" "Low,High" bitfld.long 0x00 5. " IRQS741 ,IRQS Status Bit 741" "Low,High" textline " " bitfld.long 0x00 4. " IRQS740 ,IRQS Status Bit 740" "Low,High" bitfld.long 0x00 3. " IRQS739 ,IRQS Status Bit 739" "Low,High" bitfld.long 0x00 2. " IRQS738 ,IRQS Status Bit 738" "Low,High" textline " " bitfld.long 0x00 1. " IRQS737 ,IRQS Status Bit 737" "Low,High" bitfld.long 0x00 0. " IRQS736 ,IRQS Status Bit 736" "Low,High" else rgroup.long 0x0D60++0x03 line.long 0x0 "GICD_SPISR23,Shared Peripheral Interrupt Status Register 23" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x19) rgroup.long 0x0D64++0x03 line.long 0x0 "GICD_SPISR24,Shared Peripheral Interrupt Status Register 24" bitfld.long 0x00 31. " IRQS799 ,IRQS Status Bit 799" "Low,High" bitfld.long 0x00 30. " IRQS798 ,IRQS Status Bit 798" "Low,High" bitfld.long 0x00 29. " IRQS797 ,IRQS Status Bit 797" "Low,High" textline " " bitfld.long 0x00 28. " IRQS796 ,IRQS Status Bit 796" "Low,High" bitfld.long 0x00 27. " IRQS795 ,IRQS Status Bit 795" "Low,High" bitfld.long 0x00 26. " IRQS794 ,IRQS Status Bit 794" "Low,High" textline " " bitfld.long 0x00 25. " IRQS793 ,IRQS Status Bit 793" "Low,High" bitfld.long 0x00 24. " IRQS792 ,IRQS Status Bit 792" "Low,High" bitfld.long 0x00 23. " IRQS791 ,IRQS Status Bit 791" "Low,High" textline " " bitfld.long 0x00 22. " IRQS790 ,IRQS Status Bit 790" "Low,High" bitfld.long 0x00 21. " IRQS789 ,IRQS Status Bit 789" "Low,High" bitfld.long 0x00 20. " IRQS788 ,IRQS Status Bit 788" "Low,High" textline " " bitfld.long 0x00 19. " IRQS787 ,IRQS Status Bit 787" "Low,High" bitfld.long 0x00 18. " IRQS786 ,IRQS Status Bit 786" "Low,High" bitfld.long 0x00 17. " IRQS785 ,IRQS Status Bit 785" "Low,High" textline " " bitfld.long 0x00 16. " IRQS784 ,IRQS Status Bit 784" "Low,High" bitfld.long 0x00 15. " IRQS783 ,IRQS Status Bit 783" "Low,High" bitfld.long 0x00 14. " IRQS782 ,IRQS Status Bit 782" "Low,High" textline " " bitfld.long 0x00 13. " IRQS781 ,IRQS Status Bit 781" "Low,High" bitfld.long 0x00 12. " IRQS780 ,IRQS Status Bit 780" "Low,High" bitfld.long 0x00 11. " IRQS779 ,IRQS Status Bit 779" "Low,High" textline " " bitfld.long 0x00 10. " IRQS778 ,IRQS Status Bit 778" "Low,High" bitfld.long 0x00 9. " IRQS777 ,IRQS Status Bit 777" "Low,High" bitfld.long 0x00 8. " IRQS776 ,IRQS Status Bit 776" "Low,High" textline " " bitfld.long 0x00 7. " IRQS775 ,IRQS Status Bit 775" "Low,High" bitfld.long 0x00 6. " IRQS774 ,IRQS Status Bit 774" "Low,High" bitfld.long 0x00 5. " IRQS773 ,IRQS Status Bit 773" "Low,High" textline " " bitfld.long 0x00 4. " IRQS772 ,IRQS Status Bit 772" "Low,High" bitfld.long 0x00 3. " IRQS771 ,IRQS Status Bit 771" "Low,High" bitfld.long 0x00 2. " IRQS770 ,IRQS Status Bit 770" "Low,High" textline " " bitfld.long 0x00 1. " IRQS769 ,IRQS Status Bit 769" "Low,High" bitfld.long 0x00 0. " IRQS768 ,IRQS Status Bit 768" "Low,High" else rgroup.long 0x0D64++0x03 line.long 0x0 "GICD_SPISR24,Shared Peripheral Interrupt Status Register 24" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x1A) rgroup.long 0x0D68++0x03 line.long 0x0 "GICD_SPISR25,Shared Peripheral Interrupt Status Register 25" bitfld.long 0x00 31. " IRQS831 ,IRQS Status Bit 831" "Low,High" bitfld.long 0x00 30. " IRQS830 ,IRQS Status Bit 830" "Low,High" bitfld.long 0x00 29. " IRQS829 ,IRQS Status Bit 829" "Low,High" textline " " bitfld.long 0x00 28. " IRQS828 ,IRQS Status Bit 828" "Low,High" bitfld.long 0x00 27. " IRQS827 ,IRQS Status Bit 827" "Low,High" bitfld.long 0x00 26. " IRQS826 ,IRQS Status Bit 826" "Low,High" textline " " bitfld.long 0x00 25. " IRQS825 ,IRQS Status Bit 825" "Low,High" bitfld.long 0x00 24. " IRQS824 ,IRQS Status Bit 824" "Low,High" bitfld.long 0x00 23. " IRQS823 ,IRQS Status Bit 823" "Low,High" textline " " bitfld.long 0x00 22. " IRQS822 ,IRQS Status Bit 822" "Low,High" bitfld.long 0x00 21. " IRQS821 ,IRQS Status Bit 821" "Low,High" bitfld.long 0x00 20. " IRQS820 ,IRQS Status Bit 820" "Low,High" textline " " bitfld.long 0x00 19. " IRQS819 ,IRQS Status Bit 819" "Low,High" bitfld.long 0x00 18. " IRQS818 ,IRQS Status Bit 818" "Low,High" bitfld.long 0x00 17. " IRQS817 ,IRQS Status Bit 817" "Low,High" textline " " bitfld.long 0x00 16. " IRQS816 ,IRQS Status Bit 816" "Low,High" bitfld.long 0x00 15. " IRQS815 ,IRQS Status Bit 815" "Low,High" bitfld.long 0x00 14. " IRQS814 ,IRQS Status Bit 814" "Low,High" textline " " bitfld.long 0x00 13. " IRQS813 ,IRQS Status Bit 813" "Low,High" bitfld.long 0x00 12. " IRQS812 ,IRQS Status Bit 812" "Low,High" bitfld.long 0x00 11. " IRQS811 ,IRQS Status Bit 811" "Low,High" textline " " bitfld.long 0x00 10. " IRQS810 ,IRQS Status Bit 810" "Low,High" bitfld.long 0x00 9. " IRQS809 ,IRQS Status Bit 809" "Low,High" bitfld.long 0x00 8. " IRQS808 ,IRQS Status Bit 808" "Low,High" textline " " bitfld.long 0x00 7. " IRQS807 ,IRQS Status Bit 807" "Low,High" bitfld.long 0x00 6. " IRQS806 ,IRQS Status Bit 806" "Low,High" bitfld.long 0x00 5. " IRQS805 ,IRQS Status Bit 805" "Low,High" textline " " bitfld.long 0x00 4. " IRQS804 ,IRQS Status Bit 804" "Low,High" bitfld.long 0x00 3. " IRQS803 ,IRQS Status Bit 803" "Low,High" bitfld.long 0x00 2. " IRQS802 ,IRQS Status Bit 802" "Low,High" textline " " bitfld.long 0x00 1. " IRQS801 ,IRQS Status Bit 801" "Low,High" bitfld.long 0x00 0. " IRQS800 ,IRQS Status Bit 800" "Low,High" else rgroup.long 0x0D68++0x03 line.long 0x0 "GICD_SPISR25,Shared Peripheral Interrupt Status Register 25" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x1B) rgroup.long 0x0D6C++0x03 line.long 0x0 "GICD_SPISR26,Shared Peripheral Interrupt Status Register 26" bitfld.long 0x00 31. " IRQS863 ,IRQS Status Bit 863" "Low,High" bitfld.long 0x00 30. " IRQS862 ,IRQS Status Bit 862" "Low,High" bitfld.long 0x00 29. " IRQS861 ,IRQS Status Bit 861" "Low,High" textline " " bitfld.long 0x00 28. " IRQS860 ,IRQS Status Bit 860" "Low,High" bitfld.long 0x00 27. " IRQS859 ,IRQS Status Bit 859" "Low,High" bitfld.long 0x00 26. " IRQS858 ,IRQS Status Bit 858" "Low,High" textline " " bitfld.long 0x00 25. " IRQS857 ,IRQS Status Bit 857" "Low,High" bitfld.long 0x00 24. " IRQS856 ,IRQS Status Bit 856" "Low,High" bitfld.long 0x00 23. " IRQS855 ,IRQS Status Bit 855" "Low,High" textline " " bitfld.long 0x00 22. " IRQS854 ,IRQS Status Bit 854" "Low,High" bitfld.long 0x00 21. " IRQS853 ,IRQS Status Bit 853" "Low,High" bitfld.long 0x00 20. " IRQS852 ,IRQS Status Bit 852" "Low,High" textline " " bitfld.long 0x00 19. " IRQS851 ,IRQS Status Bit 851" "Low,High" bitfld.long 0x00 18. " IRQS850 ,IRQS Status Bit 850" "Low,High" bitfld.long 0x00 17. " IRQS849 ,IRQS Status Bit 849" "Low,High" textline " " bitfld.long 0x00 16. " IRQS848 ,IRQS Status Bit 848" "Low,High" bitfld.long 0x00 15. " IRQS847 ,IRQS Status Bit 847" "Low,High" bitfld.long 0x00 14. " IRQS846 ,IRQS Status Bit 846" "Low,High" textline " " bitfld.long 0x00 13. " IRQS845 ,IRQS Status Bit 845" "Low,High" bitfld.long 0x00 12. " IRQS844 ,IRQS Status Bit 844" "Low,High" bitfld.long 0x00 11. " IRQS843 ,IRQS Status Bit 843" "Low,High" textline " " bitfld.long 0x00 10. " IRQS842 ,IRQS Status Bit 842" "Low,High" bitfld.long 0x00 9. " IRQS841 ,IRQS Status Bit 841" "Low,High" bitfld.long 0x00 8. " IRQS840 ,IRQS Status Bit 840" "Low,High" textline " " bitfld.long 0x00 7. " IRQS839 ,IRQS Status Bit 839" "Low,High" bitfld.long 0x00 6. " IRQS838 ,IRQS Status Bit 838" "Low,High" bitfld.long 0x00 5. " IRQS837 ,IRQS Status Bit 837" "Low,High" textline " " bitfld.long 0x00 4. " IRQS836 ,IRQS Status Bit 836" "Low,High" bitfld.long 0x00 3. " IRQS835 ,IRQS Status Bit 835" "Low,High" bitfld.long 0x00 2. " IRQS834 ,IRQS Status Bit 834" "Low,High" textline " " bitfld.long 0x00 1. " IRQS833 ,IRQS Status Bit 833" "Low,High" bitfld.long 0x00 0. " IRQS832 ,IRQS Status Bit 832" "Low,High" else rgroup.long 0x0D6C++0x03 line.long 0x0 "GICD_SPISR26,Shared Peripheral Interrupt Status Register 26" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x1C) rgroup.long 0x0D70++0x03 line.long 0x0 "GICD_SPISR27,Shared Peripheral Interrupt Status Register 27" bitfld.long 0x00 31. " IRQS895 ,IRQS Status Bit 895" "Low,High" bitfld.long 0x00 30. " IRQS894 ,IRQS Status Bit 894" "Low,High" bitfld.long 0x00 29. " IRQS893 ,IRQS Status Bit 893" "Low,High" textline " " bitfld.long 0x00 28. " IRQS892 ,IRQS Status Bit 892" "Low,High" bitfld.long 0x00 27. " IRQS891 ,IRQS Status Bit 891" "Low,High" bitfld.long 0x00 26. " IRQS890 ,IRQS Status Bit 890" "Low,High" textline " " bitfld.long 0x00 25. " IRQS889 ,IRQS Status Bit 889" "Low,High" bitfld.long 0x00 24. " IRQS888 ,IRQS Status Bit 888" "Low,High" bitfld.long 0x00 23. " IRQS887 ,IRQS Status Bit 887" "Low,High" textline " " bitfld.long 0x00 22. " IRQS886 ,IRQS Status Bit 886" "Low,High" bitfld.long 0x00 21. " IRQS885 ,IRQS Status Bit 885" "Low,High" bitfld.long 0x00 20. " IRQS884 ,IRQS Status Bit 884" "Low,High" textline " " bitfld.long 0x00 19. " IRQS883 ,IRQS Status Bit 883" "Low,High" bitfld.long 0x00 18. " IRQS882 ,IRQS Status Bit 882" "Low,High" bitfld.long 0x00 17. " IRQS881 ,IRQS Status Bit 881" "Low,High" textline " " bitfld.long 0x00 16. " IRQS880 ,IRQS Status Bit 880" "Low,High" bitfld.long 0x00 15. " IRQS879 ,IRQS Status Bit 879" "Low,High" bitfld.long 0x00 14. " IRQS878 ,IRQS Status Bit 878" "Low,High" textline " " bitfld.long 0x00 13. " IRQS877 ,IRQS Status Bit 877" "Low,High" bitfld.long 0x00 12. " IRQS876 ,IRQS Status Bit 876" "Low,High" bitfld.long 0x00 11. " IRQS875 ,IRQS Status Bit 875" "Low,High" textline " " bitfld.long 0x00 10. " IRQS874 ,IRQS Status Bit 874" "Low,High" bitfld.long 0x00 9. " IRQS873 ,IRQS Status Bit 873" "Low,High" bitfld.long 0x00 8. " IRQS872 ,IRQS Status Bit 872" "Low,High" textline " " bitfld.long 0x00 7. " IRQS871 ,IRQS Status Bit 871" "Low,High" bitfld.long 0x00 6. " IRQS870 ,IRQS Status Bit 870" "Low,High" bitfld.long 0x00 5. " IRQS869 ,IRQS Status Bit 869" "Low,High" textline " " bitfld.long 0x00 4. " IRQS868 ,IRQS Status Bit 868" "Low,High" bitfld.long 0x00 3. " IRQS867 ,IRQS Status Bit 867" "Low,High" bitfld.long 0x00 2. " IRQS866 ,IRQS Status Bit 866" "Low,High" textline " " bitfld.long 0x00 1. " IRQS865 ,IRQS Status Bit 865" "Low,High" bitfld.long 0x00 0. " IRQS864 ,IRQS Status Bit 864" "Low,High" else rgroup.long 0x0D70++0x03 line.long 0x0 "GICD_SPISR27,Shared Peripheral Interrupt Status Register 27" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x1D) rgroup.long 0x0D74++0x03 line.long 0x0 "GICD_SPISR28,Shared Peripheral Interrupt Status Register 28" bitfld.long 0x00 31. " IRQS927 ,IRQS Status Bit 927" "Low,High" bitfld.long 0x00 30. " IRQS926 ,IRQS Status Bit 926" "Low,High" bitfld.long 0x00 29. " IRQS925 ,IRQS Status Bit 925" "Low,High" textline " " bitfld.long 0x00 28. " IRQS924 ,IRQS Status Bit 924" "Low,High" bitfld.long 0x00 27. " IRQS923 ,IRQS Status Bit 923" "Low,High" bitfld.long 0x00 26. " IRQS922 ,IRQS Status Bit 922" "Low,High" textline " " bitfld.long 0x00 25. " IRQS921 ,IRQS Status Bit 921" "Low,High" bitfld.long 0x00 24. " IRQS920 ,IRQS Status Bit 920" "Low,High" bitfld.long 0x00 23. " IRQS919 ,IRQS Status Bit 919" "Low,High" textline " " bitfld.long 0x00 22. " IRQS918 ,IRQS Status Bit 918" "Low,High" bitfld.long 0x00 21. " IRQS917 ,IRQS Status Bit 917" "Low,High" bitfld.long 0x00 20. " IRQS916 ,IRQS Status Bit 916" "Low,High" textline " " bitfld.long 0x00 19. " IRQS915 ,IRQS Status Bit 915" "Low,High" bitfld.long 0x00 18. " IRQS914 ,IRQS Status Bit 914" "Low,High" bitfld.long 0x00 17. " IRQS913 ,IRQS Status Bit 913" "Low,High" textline " " bitfld.long 0x00 16. " IRQS912 ,IRQS Status Bit 912" "Low,High" bitfld.long 0x00 15. " IRQS911 ,IRQS Status Bit 911" "Low,High" bitfld.long 0x00 14. " IRQS910 ,IRQS Status Bit 910" "Low,High" textline " " bitfld.long 0x00 13. " IRQS909 ,IRQS Status Bit 909" "Low,High" bitfld.long 0x00 12. " IRQS908 ,IRQS Status Bit 908" "Low,High" bitfld.long 0x00 11. " IRQS907 ,IRQS Status Bit 907" "Low,High" textline " " bitfld.long 0x00 10. " IRQS906 ,IRQS Status Bit 906" "Low,High" bitfld.long 0x00 9. " IRQS905 ,IRQS Status Bit 905" "Low,High" bitfld.long 0x00 8. " IRQS904 ,IRQS Status Bit 904" "Low,High" textline " " bitfld.long 0x00 7. " IRQS903 ,IRQS Status Bit 903" "Low,High" bitfld.long 0x00 6. " IRQS902 ,IRQS Status Bit 902" "Low,High" bitfld.long 0x00 5. " IRQS901 ,IRQS Status Bit 901" "Low,High" textline " " bitfld.long 0x00 4. " IRQS900 ,IRQS Status Bit 900" "Low,High" bitfld.long 0x00 3. " IRQS899 ,IRQS Status Bit 899" "Low,High" bitfld.long 0x00 2. " IRQS898 ,IRQS Status Bit 898" "Low,High" textline " " bitfld.long 0x00 1. " IRQS897 ,IRQS Status Bit 897" "Low,High" bitfld.long 0x00 0. " IRQS896 ,IRQS Status Bit 896" "Low,High" else rgroup.long 0x0D74++0x03 line.long 0x0 "GICD_SPISR28,Shared Peripheral Interrupt Status Register 28" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x1E) rgroup.long 0x0D78++0x03 line.long 0x0 "GICD_SPISR29,Shared Peripheral Interrupt Status Register 29" bitfld.long 0x00 31. " IRQS959 ,IRQS Status Bit 959" "Low,High" bitfld.long 0x00 30. " IRQS958 ,IRQS Status Bit 958" "Low,High" bitfld.long 0x00 29. " IRQS957 ,IRQS Status Bit 957" "Low,High" textline " " bitfld.long 0x00 28. " IRQS956 ,IRQS Status Bit 956" "Low,High" bitfld.long 0x00 27. " IRQS955 ,IRQS Status Bit 955" "Low,High" bitfld.long 0x00 26. " IRQS954 ,IRQS Status Bit 954" "Low,High" textline " " bitfld.long 0x00 25. " IRQS953 ,IRQS Status Bit 953" "Low,High" bitfld.long 0x00 24. " IRQS952 ,IRQS Status Bit 952" "Low,High" bitfld.long 0x00 23. " IRQS951 ,IRQS Status Bit 951" "Low,High" textline " " bitfld.long 0x00 22. " IRQS950 ,IRQS Status Bit 950" "Low,High" bitfld.long 0x00 21. " IRQS949 ,IRQS Status Bit 949" "Low,High" bitfld.long 0x00 20. " IRQS948 ,IRQS Status Bit 948" "Low,High" textline " " bitfld.long 0x00 19. " IRQS947 ,IRQS Status Bit 947" "Low,High" bitfld.long 0x00 18. " IRQS946 ,IRQS Status Bit 946" "Low,High" bitfld.long 0x00 17. " IRQS945 ,IRQS Status Bit 945" "Low,High" textline " " bitfld.long 0x00 16. " IRQS944 ,IRQS Status Bit 944" "Low,High" bitfld.long 0x00 15. " IRQS943 ,IRQS Status Bit 943" "Low,High" bitfld.long 0x00 14. " IRQS942 ,IRQS Status Bit 942" "Low,High" textline " " bitfld.long 0x00 13. " IRQS941 ,IRQS Status Bit 941" "Low,High" bitfld.long 0x00 12. " IRQS940 ,IRQS Status Bit 940" "Low,High" bitfld.long 0x00 11. " IRQS939 ,IRQS Status Bit 939" "Low,High" textline " " bitfld.long 0x00 10. " IRQS938 ,IRQS Status Bit 938" "Low,High" bitfld.long 0x00 9. " IRQS937 ,IRQS Status Bit 937" "Low,High" bitfld.long 0x00 8. " IRQS936 ,IRQS Status Bit 936" "Low,High" textline " " bitfld.long 0x00 7. " IRQS935 ,IRQS Status Bit 935" "Low,High" bitfld.long 0x00 6. " IRQS934 ,IRQS Status Bit 934" "Low,High" bitfld.long 0x00 5. " IRQS933 ,IRQS Status Bit 933" "Low,High" textline " " bitfld.long 0x00 4. " IRQS932 ,IRQS Status Bit 932" "Low,High" bitfld.long 0x00 3. " IRQS931 ,IRQS Status Bit 931" "Low,High" bitfld.long 0x00 2. " IRQS930 ,IRQS Status Bit 930" "Low,High" textline " " bitfld.long 0x00 1. " IRQS929 ,IRQS Status Bit 929" "Low,High" bitfld.long 0x00 0. " IRQS928 ,IRQS Status Bit 928" "Low,High" else rgroup.long 0x0D78++0x03 line.long 0x0 "GICD_SPISR29,Shared Peripheral Interrupt Status Register 29" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:0xA0021000+0x04))&0x0000001F)>=0x1F) rgroup.long 0x0D7C++0x03 line.long 0x0 "GICD_SPISR30,Shared Peripheral Interrupt Status Register 30" bitfld.long 0x00 27. " IRQS987 ,IRQS Status Bit 987" "Low,High" bitfld.long 0x00 26. " IRQS986 ,IRQS Status Bit 986" "Low,High" textline " " bitfld.long 0x00 25. " IRQS985 ,IRQS Status Bit 985" "Low,High" bitfld.long 0x00 24. " IRQS984 ,IRQS Status Bit 984" "Low,High" bitfld.long 0x00 23. " IRQS983 ,IRQS Status Bit 983" "Low,High" textline " " bitfld.long 0x00 22. " IRQS982 ,IRQS Status Bit 982" "Low,High" bitfld.long 0x00 21. " IRQS981 ,IRQS Status Bit 981" "Low,High" bitfld.long 0x00 20. " IRQS980 ,IRQS Status Bit 980" "Low,High" textline " " bitfld.long 0x00 19. " IRQS979 ,IRQS Status Bit 979" "Low,High" bitfld.long 0x00 18. " IRQS978 ,IRQS Status Bit 978" "Low,High" bitfld.long 0x00 17. " IRQS977 ,IRQS Status Bit 977" "Low,High" textline " " bitfld.long 0x00 16. " IRQS976 ,IRQS Status Bit 976" "Low,High" bitfld.long 0x00 15. " IRQS975 ,IRQS Status Bit 975" "Low,High" bitfld.long 0x00 14. " IRQS974 ,IRQS Status Bit 974" "Low,High" textline " " bitfld.long 0x00 13. " IRQS973 ,IRQS Status Bit 973" "Low,High" bitfld.long 0x00 12. " IRQS972 ,IRQS Status Bit 972" "Low,High" bitfld.long 0x00 11. " IRQS971 ,IRQS Status Bit 971" "Low,High" textline " " bitfld.long 0x00 10. " IRQS970 ,IRQS Status Bit 970" "Low,High" bitfld.long 0x00 9. " IRQS969 ,IRQS Status Bit 969" "Low,High" bitfld.long 0x00 8. " IRQS968 ,IRQS Status Bit 968" "Low,High" textline " " bitfld.long 0x00 7. " IRQS967 ,IRQS Status Bit 967" "Low,High" bitfld.long 0x00 6. " IRQS966 ,IRQS Status Bit 966" "Low,High" bitfld.long 0x00 5. " IRQS965 ,IRQS Status Bit 965" "Low,High" textline " " bitfld.long 0x00 4. " IRQS964 ,IRQS Status Bit 964" "Low,High" bitfld.long 0x00 3. " IRQS963 ,IRQS Status Bit 963" "Low,High" bitfld.long 0x00 2. " IRQS962 ,IRQS Status Bit 962" "Low,High" textline " " bitfld.long 0x00 1. " IRQS961 ,IRQS Status Bit 961" "Low,High" bitfld.long 0x00 0. " IRQS960 ,IRQS Status Bit 960" "Low,High" else rgroup.long 0x0D7C++0x03 line.long 0x0 "GICD_SPISR30,Shared Peripheral Interrupt Status Register 30" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif tree.end width 25. tree "Software Generated Interrupt" if (((per.l(ad:0xA0021000+0x04))&0x400)==0x400) wgroup.long 0x0F00++0x03 line.long 0x00 "GICD_SGIR,Software Generated Interrupt Register" bitfld.long 0x00 24.--25. " TLF ,Target List Filter" "TargetList,All CPUs,Request CPU,?..." hexmask.long.byte 0x00 16.--23. 1. " CPUTL ,CPU Target List" textline " " bitfld.long 0x00 15. " NSATT ,NSATT" "Secure,Non-secure" bitfld.long 0x00 0.--3. " SGINTID ,SGI Interrupt ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else wgroup.long 0x0F00++0x03 line.long 0x00 "GICD_SGIR,Software Generated Interrupt Register" bitfld.long 0x00 24.--25. " TLF ,Target List Filter" "TargetList,All CPUs,Request CPU,?..." hexmask.long.byte 0x00 16.--23. 1. " CPUTL ,CPU Target List" textline " " bitfld.long 0x00 0.--3. " SGINTID ,SGI Interrupt ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif group.long 0x0F20++0x03 line.long 0x00 "GICD_SET/CLR_PENDSGIR0,SGI Set/Clear Pending Register 0" setclrfld.long 0x00 31. 0x00 31. -0x10 31. " SET/CLR_SGI0 ,SGI0 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. -0x10 30. " SET/CLR_SGI0 ,SGI0 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. -0x10 29. " SET/CLR_SGI0 ,SGI0 Set/Clear Pending Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. -0x10 28. " SET/CLR_SGI0 ,SGI0 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. -0x10 27. " SET/CLR_SGI0 ,SGI0 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. -0x10 26. " SET/CLR_SGI0 ,SGI0 Set/Clear Pending Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. -0x10 25. " SET/CLR_SGI0 ,SGI0 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. -0x10 24. " SET/CLR_SGI0 ,SGI0 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. -0x10 23. " SET/CLR_SGI1 ,SGI1 Set/Clear Pending Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. -0x10 22. " SET/CLR_SGI1 ,SGI1 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. -0x10 21. " SET/CLR_SGI1 ,SGI1 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. -0x10 20. " SET/CLR_SGI1 ,SGI1 Set/Clear Pending Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. -0x10 19. " SET/CLR_SGI1 ,SGI1 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. -0x10 18. " SET/CLR_SGI1 ,SGI1 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. -0x10 17. " SET/CLR_SGI1 ,SGI1 Set/Clear Pending Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. -0x10 16. " SET/CLR_SGI1 ,SGI1 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. -0x10 15. " SET/CLR_SGI2 ,SGI2 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. -0x10 14. " SET/CLR_SGI2 ,SGI2 Set/Clear Pending Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. -0x10 13. " SET/CLR_SGI2 ,SGI2 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. -0x10 12. " SET/CLR_SGI2 ,SGI2 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. -0x10 11. " SET/CLR_SGI2 ,SGI2 Set/Clear Pending Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. -0x10 10. " SET/CLR_SGI2 ,SGI2 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. -0x10 9. " SET/CLR_SGI2 ,SGI2 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. -0x10 8. " SET/CLR_SGI2 ,SGI2 Set/Clear Pending Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. -0x10 7. " SET/CLR_SGI3 ,SGI3 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. -0x10 6. " SET/CLR_SGI3 ,SGI3 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. -0x10 5. " SET/CLR_SGI3 ,SGI3 Set/Clear Pending Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. -0x10 4. " SET/CLR_SGI3 ,SGI3 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. -0x10 3. " SET/CLR_SGI3 ,SGI3 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. -0x10 2. " SET/CLR_SGI3 ,SGI3 Set/Clear Pending Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. -0x10 1. " SET/CLR_SGI3 ,SGI3 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. -0x10 0. " SET/CLR_SGI3 ,SGI3 Set/Clear Pending Bit" "Disabled,Enabled" group.long 0x0F24++0x03 line.long 0x00 "GICD_SET/CLR_PENDSGIR1,SGI Set/Clear Pending Register 1" setclrfld.long 0x00 31. 0x00 31. -0x10 31. " SET/CLR_SGI4 ,SGI4 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. -0x10 30. " SET/CLR_SGI4 ,SGI4 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. -0x10 29. " SET/CLR_SGI4 ,SGI4 Set/Clear Pending Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. -0x10 28. " SET/CLR_SGI4 ,SGI4 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. -0x10 27. " SET/CLR_SGI4 ,SGI4 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. -0x10 26. " SET/CLR_SGI4 ,SGI4 Set/Clear Pending Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. -0x10 25. " SET/CLR_SGI4 ,SGI4 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. -0x10 24. " SET/CLR_SGI4 ,SGI4 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. -0x10 23. " SET/CLR_SGI5 ,SGI5 Set/Clear Pending Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. -0x10 22. " SET/CLR_SGI5 ,SGI5 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. -0x10 21. " SET/CLR_SGI5 ,SGI5 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. -0x10 20. " SET/CLR_SGI5 ,SGI5 Set/Clear Pending Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. -0x10 19. " SET/CLR_SGI5 ,SGI5 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. -0x10 18. " SET/CLR_SGI5 ,SGI5 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. -0x10 17. " SET/CLR_SGI5 ,SGI5 Set/Clear Pending Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. -0x10 16. " SET/CLR_SGI5 ,SGI5 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. -0x10 15. " SET/CLR_SGI6 ,SGI6 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. -0x10 14. " SET/CLR_SGI6 ,SGI6 Set/Clear Pending Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. -0x10 13. " SET/CLR_SGI6 ,SGI6 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. -0x10 12. " SET/CLR_SGI6 ,SGI6 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. -0x10 11. " SET/CLR_SGI6 ,SGI6 Set/Clear Pending Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. -0x10 10. " SET/CLR_SGI6 ,SGI6 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. -0x10 9. " SET/CLR_SGI6 ,SGI6 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. -0x10 8. " SET/CLR_SGI6 ,SGI6 Set/Clear Pending Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. -0x10 7. " SET/CLR_SGI7 ,SGI7 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. -0x10 6. " SET/CLR_SGI7 ,SGI7 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. -0x10 5. " SET/CLR_SGI7 ,SGI7 Set/Clear Pending Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. -0x10 4. " SET/CLR_SGI7 ,SGI7 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. -0x10 3. " SET/CLR_SGI7 ,SGI7 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. -0x10 2. " SET/CLR_SGI7 ,SGI7 Set/Clear Pending Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. -0x10 1. " SET/CLR_SGI7 ,SGI7 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. -0x10 0. " SET/CLR_SGI7 ,SGI7 Set/Clear Pending Bit" "Disabled,Enabled" group.long 0x0F28++0x03 line.long 0x00 "GICD_SET/CLR_PENDSGIR2,SGI Set/Clear Pending Register 2" setclrfld.long 0x00 31. 0x00 31. -0x10 31. " SET/CLR_SGI8 ,SGI8 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. -0x10 30. " SET/CLR_SGI8 ,SGI8 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. -0x10 29. " SET/CLR_SGI8 ,SGI8 Set/Clear Pending Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. -0x10 28. " SET/CLR_SGI8 ,SGI8 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. -0x10 27. " SET/CLR_SGI8 ,SGI8 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. -0x10 26. " SET/CLR_SGI8 ,SGI8 Set/Clear Pending Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. -0x10 25. " SET/CLR_SGI8 ,SGI8 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. -0x10 24. " SET/CLR_SGI8 ,SGI8 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. -0x10 23. " SET/CLR_SGI9 ,SGI9 Set/Clear Pending Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. -0x10 22. " SET/CLR_SGI9 ,SGI9 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. -0x10 21. " SET/CLR_SGI9 ,SGI9 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. -0x10 20. " SET/CLR_SGI9 ,SGI9 Set/Clear Pending Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. -0x10 19. " SET/CLR_SGI9 ,SGI9 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. -0x10 18. " SET/CLR_SGI9 ,SGI9 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. -0x10 17. " SET/CLR_SGI9 ,SGI9 Set/Clear Pending Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. -0x10 16. " SET/CLR_SGI9 ,SGI9 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. -0x10 15. " SET/CLR_SGI10 ,SGI10 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. -0x10 14. " SET/CLR_SGI10 ,SGI10 Set/Clear Pending Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. -0x10 13. " SET/CLR_SGI10 ,SGI10 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. -0x10 12. " SET/CLR_SGI10 ,SGI10 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. -0x10 11. " SET/CLR_SGI10 ,SGI10 Set/Clear Pending Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. -0x10 10. " SET/CLR_SGI10 ,SGI10 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. -0x10 9. " SET/CLR_SGI10 ,SGI10 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. -0x10 8. " SET/CLR_SGI10 ,SGI10 Set/Clear Pending Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. -0x10 7. " SET/CLR_SGI11 ,SGI11 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. -0x10 6. " SET/CLR_SGI11 ,SGI11 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. -0x10 5. " SET/CLR_SGI11 ,SGI11 Set/Clear Pending Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. -0x10 4. " SET/CLR_SGI11 ,SGI11 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. -0x10 3. " SET/CLR_SGI11 ,SGI11 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. -0x10 2. " SET/CLR_SGI11 ,SGI11 Set/Clear Pending Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. -0x10 1. " SET/CLR_SGI11 ,SGI11 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. -0x10 0. " SET/CLR_SGI11 ,SGI11 Set/Clear Pending Bit" "Disabled,Enabled" group.long 0x0F2C++0x03 line.long 0x00 "GICD_SET/CLR_PENDSGIR2,SGI Set/Clear Pending Register 3" setclrfld.long 0x00 31. 0x00 31. -0x10 31. " SET/CLR_SGI12 ,SGI12 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. -0x10 30. " SET/CLR_SGI12 ,SGI12 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. -0x10 29. " SET/CLR_SGI12 ,SGI12 Set/Clear Pending Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. -0x10 28. " SET/CLR_SGI12 ,SGI12 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. -0x10 27. " SET/CLR_SGI12 ,SGI12 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. -0x10 26. " SET/CLR_SGI12 ,SGI12 Set/Clear Pending Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. -0x10 25. " SET/CLR_SGI12 ,SGI12 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. -0x10 24. " SET/CLR_SGI12 ,SGI12 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. -0x10 23. " SET/CLR_SGI13 ,SGI13 Set/Clear Pending Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. -0x10 22. " SET/CLR_SGI13 ,SGI13 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. -0x10 21. " SET/CLR_SGI13 ,SGI13 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. -0x10 20. " SET/CLR_SGI13 ,SGI13 Set/Clear Pending Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. -0x10 19. " SET/CLR_SGI13 ,SGI13 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. -0x10 18. " SET/CLR_SGI13 ,SGI13 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. -0x10 17. " SET/CLR_SGI13 ,SGI13 Set/Clear Pending Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. -0x10 16. " SET/CLR_SGI13 ,SGI13 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. -0x10 15. " SET/CLR_SGI14 ,SGI14 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. -0x10 14. " SET/CLR_SGI14 ,SGI14 Set/Clear Pending Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. -0x10 13. " SET/CLR_SGI14 ,SGI14 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. -0x10 12. " SET/CLR_SGI14 ,SGI14 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. -0x10 11. " SET/CLR_SGI14 ,SGI14 Set/Clear Pending Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. -0x10 10. " SET/CLR_SGI14 ,SGI14 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. -0x10 9. " SET/CLR_SGI14 ,SGI14 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. -0x10 8. " SET/CLR_SGI14 ,SGI14 Set/Clear Pending Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. -0x10 7. " SET/CLR_SGI15 ,SGI15 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. -0x10 6. " SET/CLR_SGI15 ,SGI15 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. -0x10 5. " SET/CLR_SGI15 ,SGI15 Set/Clear Pending Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. -0x10 4. " SET/CLR_SGI15 ,SGI15 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. -0x10 3. " SET/CLR_SGI15 ,SGI15 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. -0x10 2. " SET/CLR_SGI15 ,SGI15 Set/Clear Pending Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. -0x10 1. " SET/CLR_SGI15 ,SGI15 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. -0x10 0. " SET/CLR_SGI15 ,SGI15 Set/Clear Pending Bit" "Disabled,Enabled" tree.end width 12. tree "Peripheral/Component ID Registers" rgroup.byte 0x0FE0++0x00 line.byte 0x00 "GICD_PIDR0,Peripheral ID0 Register" hexmask.byte 0x00 0.--7. 1. " DEVID ,DevID field" rgroup.byte 0x0FE4++0x00 line.byte 0x00 "GICD_PIDR1,Peripheral ID1 Register" bitfld.byte 0x00 4.--7. " ARCHID ,ArchID field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.byte 0x00 0.--3. " DEVID ,DevID field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.byte 0x0FE8++0x00 line.byte 0x00 "GICD_PIDR2,Peripheral ID2 Register" bitfld.byte 0x00 4.--7. " ARCHREV ,ArchRev field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.byte 0x00 3. " UJEPCODE ,UsesJEPcode field" "Low,High" bitfld.byte 0x00 0.--2. " ARCHID ,ArchID field" "0,1,2,3,4,5,6,7" rgroup.byte 0x0FEC++0x00 line.byte 0x00 "GICD_PIDR3,Peripheral ID3 Register" bitfld.byte 0x00 4.--7. " REVID ,Revision field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.byte 0x0FD0++0x00 line.byte 0x00 "GICD_PIDR4,Peripheral ID4 Register" bitfld.byte 0x00 0.--3. " CC ,ContinuationCode field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.byte 0xFD4++0x00 line.byte 0x00 "GICD_PIDR5,Peripheral ID5 Register" rgroup.byte 0xFD8++0x00 line.byte 0x00 "GICD_PIDR6,Peripheral ID6 Register" rgroup.byte 0xFDC++0x00 line.byte 0x00 "GICD_PIDR7,Peripheral ID7 Register" textline " " rgroup.byte 0xFF0++0x00 line.byte 0x00 "GICD_CIDR0,Component ID0 Register" hexmask.byte 0x00 0.--7. 1. " FIXVAL ,ARM-defined fixed values for the preamble for component discovery" rgroup.byte 0xFF4++0x00 line.byte 0x00 "GICD_CIDR1,Component ID1 Register" hexmask.byte 0x00 0.--7. 1. " FIXVAL ,ARM-defined fixed values for the preamble for component discovery" rgroup.byte 0xFF8++0x00 line.byte 0x00 "GICD_CIDR2,Component ID2 Register" hexmask.byte 0x00 0.--7. 1. " FIXVAL ,ARM-defined fixed values for the preamble for component discovery" rgroup.byte 0xFFC++0x00 line.byte 0x00 "GICD_CIDR3,Component ID3 Register" hexmask.byte 0x00 0.--7. 1. " FIXVAL ,ARM-defined fixed values for the preamble for component discovery" textline " " tree.end tree.end width 0x0B base ad:0xA0022000 width 17. tree "CPU Interface" if (((per.l(ad:0xA0021000+0x04))&0x400)==0x0) group.long 0x0000++0x03 line.long 0x00 "GICC_CTLR,CPU Interface Control Register" bitfld.long 0x00 9. " EOIMODENS ,Controls the behavior of Non-secure accesses to the GICC_EOIR and GICC_DIR registers" "Priority drop/Deactivate,Priority drop" bitfld.long 0x00 6. " IRQBYPDISGRP1 ,When the signaling of IRQs by the CPU interface is disabled this bit partly controls whether the bypass IRQ signal is signaled to the processor" "Signaled,Not signaled" bitfld.long 0x00 5. " FIQBYPDISGRP1 ,When the signaling of FIQs by the CPU interface is disabled this bit partly controls whether the bypass FIQ signal is signaled to the processor" "Signaled,Not signaled" textline " " bitfld.long 0x00 0. " ENABLEGRP1 ,Enable for the signaling of Group 1 interrupts by the CPU interface to the connected processor" "Disabled,Enabled" textline " " textline " " else if PER.ADDRESS.isSECUREEX(ad:0xA0022000) group.long 0x0000++0x03 line.long 0x00 "GICC_CTLR,CPU Interface Control Register (Secure access)" bitfld.long 0x00 10. " EOIMODENS ,Controls the behavior of Non-secure accesses to the GICC_EOIR and GICC_DIR registers" "Priority drop/Deactivate,Priority drop" bitfld.long 0x00 9. " EOIMODES ,Controls the behavior of accesses to GICC_EOIR and GICC_DIR registers" "Priority drop/Deactivate,Priority drop" bitfld.long 0x00 8. " IRQBYPDISGRP1 ,When the signaling of IRQs by the CPU interface is disabled this bit partly controls whether the bypass IRQ signal is signaled to the processor" "Signaled,Not signaled" textline " " bitfld.long 0x00 7. " FIQBYPDISGRP1 ,When the signaling of FIQs by the CPU interface is disabled this bit partly controls whether the bypass FIQ signal is signaled to the processor" "Signaled,Not signaled" bitfld.long 0x00 6. " IRQBYPDISGRP0 ,When the signaling of FIQs by the CPU interface is disabled this bit partly controls whether the bypass FIQ signal is signaled to the processor" "Signaled,Not signaled" bitfld.long 0x00 5. " FIQBYPDISGRP0 ,When the signaling of FIQs by the CPU interface is disabled this bit partly controls whether the bypass FIQ signal is signaled to the processor" "Signaled,Not signaled" textline " " bitfld.long 0x00 4. " CBPR ,Controls whether the GICC_BPR provides common control to Group 0 and Group 1 interrupts" "BPR/ABPR split,BPR common" bitfld.long 0x00 3. " FIQEN ,Controls whether the CPU interface signals Group 0 interrupts to a target processor using the FIQ or the IRQ signal" "IRQ,FIQ" bitfld.long 0x00 2. " ACKCTL ,Acknowledge Control" "ID 1022 interrupt,Corresponding interrupt" textline " " bitfld.long 0x00 1. " ENABLEGRP1 ,Enable for the signaling of Group 1 interrupts by the CPU interface to the connected processor" "Disabled,Enabled" bitfld.long 0x00 0. " ENABLEGRP0 ,Enable for the signaling of Group 0 interrupts by the CPU interface to the connected processor" "Disabled,Enabled" else group.long 0x0000++0x03 line.long 0x00 "GICC_CTLR,CPU Interface Control Register (Non-secure access)" bitfld.long 0x00 9. " EOIMODENS ,Controls the behavior of Non-secure accesses to the GICC_EOIR and GICC_DIR registers" "Priority drop/Deactivate,Priority drop" bitfld.long 0x00 6. " IRQBYPDISGRP1 ,When the signaling of IRQs by the CPU interface is disabled this bit partly controls whether the bypass IRQ signal is signaled to the processor" "Signaled,Not signaled" bitfld.long 0x00 5. " FIQBYPDISGRP1 ,When the signaling of FIQs by the CPU interface is disabled this bit partly controls whether the bypass FIQ signal is signaled to the processor" "Signaled,Not signaled" textline " " bitfld.long 0x00 0. " ENABLEGRP1 ,Enable for the signaling of Group 1 interrupts by the CPU interface to the connected processor" "Disabled,Enabled" textline " " textline " " endif endif group.long 0x0004++0x03 line.long 0x00 "GICC_PMR,Interrupt Priority Mask Register" hexmask.long.byte 0x00 0.--7. 1. " PRIORITY ,Priority mask level for CPU interface" if (((per.l(ad:0xA0021000+0x04))&0x400)==0x400) if PER.ADDRESS.isSECUREEX(ad:0xA0022000+0x0008) group.long 0x0008++0x03 line.long 0x00 "GICC_BPR,Binary Point Register (Secure access)" bitfld.long 0x00 0.--2. " BINARY_POINT ,The value of this field controls how the 8-bit interrupt priority field is split into a group priority field and subpriority field" "Reserved,Reserved,[7:3]/[2:0],[7:4]/[3:0],[7:5]/[4:0],[7:6]/[5:0],[7]/[6:0],-/[7:0]" else group.long 0x0008++0x03 line.long 0x00 "GICC_BPR,Binary Point Register (Non-secure access)" bitfld.long 0x00 0.--2. " BINARY_POINT ,The value of this field controls how the 8-bit interrupt priority field is split into a group priority field and subpriority field" "Reserved,Reserved,Reserved,[7:4]/[3:0],[7:5]/[4:0],[7:6]/[5:0],[7]/[6:0],-/[7:0]" endif else group.long 0x0008++0x03 line.long 0x00 "GICC_BPR,Binary Point Register" bitfld.long 0x00 0.--2. " BINARY_POINT ,The value of this field controls how the 8-bit interrupt priority field is split into a group priority field and subpriority field" "Reserved,Reserved,Reserved,[7:4]/[3:0],[7:5]/[4:0],[7:6]/[5:0],[7]/[6:0],-/[7:0]" endif hgroup.long 0x000C++0x03 hide.long 0x00 "GICC_IAR,Interrupt Acknowledge Register" in wgroup.long 0x0010++0x03 line.long 0x00 "GICC_EOIR,End Of Interrupt Register" bitfld.long 0x00 10.--12. " CPUID ,On a multiprocessor implementation if the write refers to an SGI this field contains the CPUID value from the corresponding GICC_IAR access" "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 0.--9. 1. " EOIINTID ,The Interrupt ID value from the corresponding GICC_IAR access" rgroup.long 0x0014++0x03 line.long 0x00 "GICC_RPR,Running Priority Register" hexmask.long.byte 0x00 0.--7. 1. " PRIORITY ,The current running priority on the CPU interface" rgroup.long 0x0018++0x03 line.long 0x00 "GICC_HPIR,Highest Priority Pending Interrupt Register" bitfld.long 0x00 10.--12. " CPUID ,On a multiprocessor implementation if the PENDINTID field returns the ID of an SGI this field contains the CPUID value for that interrupt" "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 0.--9. 1. " PENDINTID ,The interrupt ID of the highest priority pending interrupt" if (((per.l(ad:0xA0021000+0x04))&0x400)==0x400) group.long 0x001C++0x03 line.long 0x00 "GICC_ABPR,Aliased Binary Point Register" bitfld.long 0x00 0.--2. " BINARY_POINT ,The value of this field controls how the 8-bit interrupt priority field is split into a group priority field and subpriority field" "[7:1]/[0],[7:2]/[1:0],[7:3]/[2:0],[7:4]/[3:0],[7:5]/[4:0],[7:6]/[5:0],[7]/[6:0],-/[7:0]" else hgroup.long 0x001C++0x03 hide.long 0x00 "GICC_ABPR,Aliased Binary Point Register" endif hgroup.long 0x0020++0x003 hide.long 0x00 "GICC_AIAR,Aliased Interrupt Acknowledge Register" in if (((per.l(ad:0xA0021000+0x04))&0x400)==0x400) wgroup.long 0x0024++0x03 line.long 0x00 "GICC_AEOIR,Aliased End of Interrupt Register" bitfld.long 0x00 10.--12. " CPUID ,On a multiprocessor implementation if the write refers to an SGI this field contains the CPUID value from the corresponding GICC_IAR access" "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 0.--9. 1. " EOIINTID ,The Interrupt ID value from the corresponding GICC_IAR access" rgroup.long 0x0028++0x03 line.long 0x00 "GICC_AHPPIR,Aliased Highest Priority Pending Interrupt Register" bitfld.long 0x00 10.--12. " CPUID ,On a multiprocessor implementation if the PENDINTID field returns the ID of an SGI this field contains the CPUID value for that interrupt" "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 0.--9. 1. " PENDINTID ,The interrupt ID of the highest priority pending interrupt" else hgroup.long 0x0024++0x03 hide.long 0x00 "GICC_AEOIR,Aliased End of Interrupt Register" hgroup.long 0x0028++0x03 hide.long 0x00 "GICC_AHPPIR,Aliased Highest Priority Pending Interrupt Register" endif group.long 0x00D0++0x03 line.long 0x00 "GICC_APR0,Active Priorities Register" if (((per.l(ad:0xA0021000+0x04))&0x400)==0x400) group.long 0x00E0++0x03 line.long 0x00 "GICC_NSAPR0,Non-Secure Active Priorities Register" else hgroup.long 0x00E0++0x03 hide.long 0x00 "GICC_NSAPR0,Non-Secure Active Priorities Register" endif rgroup.long 0x00FC++0x03 line.long 0x00 "GICC_IIDR,CPU and Virtual CPU Interface Identification Register" hexmask.long.word 0x00 20.--31. 1. " PRODID ,Product ID" bitfld.long 0x00 16.--19. " ARCH_VER ,Identifies the architecture version of the GIC" "GICv1,GICv1,GICv2,GICv2,?..." textline " " bitfld.long 0x00 12.--15. " REV ,Revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x00 0.--11. 1. " IMP ,Implementer" wgroup.long 0x1000++0x03 line.long 0x00 "GICC_DIR,Deactivate Interrupt Register" bitfld.long 0x00 10.--12. " CPUID ,On a multiprocessor implementation this field identifies the processor that requested the interrupt" "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 0.--9. 1. " INTID ,The interrupt ID" tree.end sif CPU.FEATURE(hypervisor) base ad:0xA0024000 width 12. tree "Virtual CPU Control Interface" group.long 0x0000++0x03 line.long 0x00 "GICH_HCR,Hypervisor Control Register" bitfld.long 0x00 27.--31. " EOICOUNT ,Counts the number of EOIs received that do not have a corresponding entry in the List registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 7. " VGRP1DIE ,VM Disable Group 1 Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 6. " VGRP1EIE ,VM Enable Group 1 Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " VGRP0DIE ,VM Disable Group 0 Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4. " VGRP0EIE ,VM Disable Group 0 Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 3. " NPIE ,No Pending Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " LRENPIE ,List Register Entry Not Present Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 1. " UIE ,Underflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled" rgroup.long 0x0004++0x03 line.long 0x00 "GICH_VTR,VGIC Type Register" bitfld.long 0x00 29.--31. " PRIBITS ,Number of priority bits" "Reserved,Reserved,Reserved,Reserved,5 bits 32 PRI levels,?..." textline " " bitfld.long 0x00 26.--28. " PREBITS ,Number of pre-emption bits" "Reserved,Reserved,Reserved,Reserved,5 bits 32 PRE levels,?..." textline " " bitfld.long 0x00 0.--5. " LISTREGS ,List regs number" "Reserved,Reserved,Reserved,4 lists,?..." group.long 0x008++0x03 line.long 0x00 "GICH_VMCR,Virtual Machine Control Register" bitfld.long 0x00 27.--31. " VMPRIMASK ,Alias of GICV_PMR.Priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 21.--23. " VMBP ,Alias of GICV_BPR.Binary point" "0,1,2,3,4,5,6,7" bitfld.long 0x00 18.--20. " VMABP ,Alias of GICV_ABPR.Binary point" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 9. " VEM ,Alias of GICV_CTLR.EOImode" "0,1" bitfld.long 0x00 4. " VMCBPR ,Alias of GICV_CTLR.CBPR" "0,1" bitfld.long 0x00 3. " VMFIQEN ,Alias of GICV_CTLR.FIQEn" "0,1" textline " " bitfld.long 0x00 2. " VMACKCTL ,Alias of GICV_CTLR.AckCtl" "0,1" bitfld.long 0x00 1. " VMGRP1EN ,Alias of GICV_CTLR.EnableGrp1" "0,1" bitfld.long 0x00 0. " VMGRP0EN ,Alias of GICV_CTLR.EnableGrp0" "0,1" rgroup.long 0x0010++0x03 line.long 0x00 "GICH_MISR,Maintenance Interrupt Status Register" bitfld.long 0x00 7. " VGRP1D ,Disabled Group 1 maintenance interrupt" "No interrupt,Interrupt" bitfld.long 0x00 6. " VGRP1E ,Enabled Group 1 maintenance interrupt" "No interrupt,Interrupt" bitfld.long 0x00 5. " VGRP0D ,Disabled Group 0 maintenance interrupt" "No interrupt,Interrupt" textline " " bitfld.long 0x00 4. " VGRP0E ,Enabled Group 0 maintenance interrupt" "No interrupt,Interrupt" bitfld.long 0x00 3. " NP ,No Pending maintenance interrupt" "No interrupt,Interrupt" bitfld.long 0x00 2. " LRENP ,List Register Entry Not Present maintenance interrupt" "No interrupt,Interrupt" textline " " bitfld.long 0x00 1. " U ,Underflow maintenance interrupt" "No interrupt,Interrupt" bitfld.long 0x00 0. " EOI ,EOI maintenance interrupt" "No interrupt,Interrupt" rgroup.long 0x020++0x03 line.long 0x00 "GICH_EISR0,End of Interrupt Status Register" bitfld.long 0x00 3. " STATUS3 ,EOI maintenance interrupt status for List register 3" "No interrupt,Interrupt" bitfld.long 0x00 2. " STATUS2 ,EOI maintenance interrupt status for List register 2" "No interrupt,Interrupt" bitfld.long 0x00 1. " STATUS1 ,EOI maintenance interrupt status for List register 1" "No interrupt,Interrupt" textline " " bitfld.long 0x00 0. " STATUS0 ,EOI maintenance interrupt status for List register 0" "No interrupt,Interrupt" rgroup.long 0x0030++0x03 line.long 0x00 "GICH_ELSR0,Empty List register Status Register" bitfld.long 0x00 3. " STATUS3 ,Emptiness status bit for List register 3" "Not empty,Empty" bitfld.long 0x00 2. " STATUS2 ,Emptiness status bit for List register 2" "Not empty,Empty" bitfld.long 0x00 1. " STATUS1 ,Emptiness status bit for List register 1" "Not empty,Empty" textline " " bitfld.long 0x00 0. " STATUS0 ,Emptiness status bit for List register 0" "Not empty,Empty" group.long 0x00F0++0x03 line.long 0x00 "GICH_APR0,Active Priorities Register" bitfld.long 0x00 31. " APB31 ,Determines whether the corresponding preemption level is active" "Not active,Active" bitfld.long 0x00 30. " APB30 ,Determines whether the corresponding preemption level is active" "Not active,Active" bitfld.long 0x00 29. " APB29 ,Determines whether the corresponding preemption level is active" "Not active,Active" textline " " bitfld.long 0x00 28. " APB28 ,Determines whether the corresponding preemption level is active" "Not active,Active" bitfld.long 0x00 27. " APB27 ,Determines whether the corresponding preemption level is active" "Not active,Active" bitfld.long 0x00 26. " APB26 ,Determines whether the corresponding preemption level is active" "Not active,Active" textline " " bitfld.long 0x00 25. " APB25 ,Determines whether the corresponding preemption level is active" "Not active,Active" bitfld.long 0x00 24. " APB24 ,Determines whether the corresponding preemption level is active" "Not active,Active" bitfld.long 0x00 23. " APB23 ,Determines whether the corresponding preemption level is active" "Not active,Active" textline " " bitfld.long 0x00 22. " APB22 ,Determines whether the corresponding preemption level is active" "Not active,Active" bitfld.long 0x00 21. " APB21 ,Determines whether the corresponding preemption level is active" "Not active,Active" bitfld.long 0x00 20. " APB20 ,Determines whether the corresponding preemption level is active" "Not active,Active" textline " " bitfld.long 0x00 19. " APB19 ,Determines whether the corresponding preemption level is active" "Not active,Active" bitfld.long 0x00 18. " APB18 ,Determines whether the corresponding preemption level is active" "Not active,Active" bitfld.long 0x00 17. " APB17 ,Determines whether the corresponding preemption level is active" "Not active,Active" textline " " bitfld.long 0x00 16. " APB16 ,Determines whether the corresponding preemption level is active" "Not active,Active" bitfld.long 0x00 15. " APB15 ,Determines whether the corresponding preemption level is active" "Not active,Active" bitfld.long 0x00 14. " APB14 ,Determines whether the corresponding preemption level is active" "Not active,Active" textline " " bitfld.long 0x00 13. " APB13 ,Determines whether the corresponding preemption level is active" "Not active,Active" bitfld.long 0x00 12. " APB12 ,Determines whether the corresponding preemption level is active" "Not active,Active" bitfld.long 0x00 11. " APB11 ,Determines whether the corresponding preemption level is active" "Not active,Active" textline " " bitfld.long 0x00 10. " APB10 ,Determines whether the corresponding preemption level is active" "Not active,Active" bitfld.long 0x00 9. " APB9 ,Determines whether the corresponding preemption level is active" "Not active,Active" bitfld.long 0x00 8. " APB8 ,Determines whether the corresponding preemption level is active" "Not active,Active" textline " " bitfld.long 0x00 7. " APB7 ,Determines whether the corresponding preemption level is active" "Not active,Active" bitfld.long 0x00 6. " APB6 ,Determines whether the corresponding preemption level is active" "Not active,Active" bitfld.long 0x00 5. " APB5 ,Determines whether the corresponding preemption level is active" "Not active,Active" textline " " bitfld.long 0x00 4. " APB4 ,Determines whether the corresponding preemption level is active" "Not active,Active" bitfld.long 0x00 3. " APB3 ,Determines whether the corresponding preemption level is active" "Not active,Active" bitfld.long 0x00 2. " APB2 ,Determines whether the corresponding preemption level is active" "Not active,Active" textline " " bitfld.long 0x00 1. " APB1 ,Determines whether the corresponding preemption level is active" "Not active,Active" bitfld.long 0x00 0. " APB0 ,Determines whether the corresponding preemption level is active" "Not active,Active" if (((per.l(ad:0xA0024000+0x100))&0x80000000)==0x80000000) group.long 0x100++0x03 line.long 0x00 "GICH_LR0,List Register 0" bitfld.long 0x00 31. " HW ,Indicates whether this virtual interrupt is a hardware interrupt" "Software,Hardware" bitfld.long 0x00 30. " GRP1 ,Indicates whether this virtual interrupt is a Group 1 virtual interrupt" "Group 0,Group 1" bitfld.long 0x00 28.--29. " STATE ,The state of the interrupt" "Invalid,Pending,Active,Pending and active" textline " " bitfld.long 0x00 23.--27. " PRIORITY ,The priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 10.--19. 1. " PHYSICALID ,Indicates the physical interrupt ID that the hypervisor forwards to the Distributor" hexmask.long.word 0x00 0.--9. 1. " VIRTUALID ,This ID is returned to the Guest OS when the interrupt is acknowledged through the VM Interrupt Acknowledge register, GICV_IAR" else group.long 0x100++0x03 line.long 0x00 "GICH_LR0,List Register 0" bitfld.long 0x00 31. " HW ,Indicates whether this virtual interrupt is a hardware interrupt" "Software,Hardware" bitfld.long 0x00 30. " GRP1 ,Indicates whether this virtual interrupt is a Group 1 virtual interrupt" "Group 0,Group 1" bitfld.long 0x00 28.--29. " STATE ,The state of the interrupt" "Invalid,Pending,Active,Pending and active" textline " " bitfld.long 0x00 23.--27. " PRIORITY ,The priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 19. " EOI ,Indicates whether this interrupt triggers an EOI maintenance interrupt" "Not asserted,Asserted" bitfld.long 0x00 10.--12. " CPUID ,If the interrupt has the VirtualID for an SGI that is 0-15 this field shows the requesting CPU ID" "0,1,2,3,4,5,6,7" textline " " hexmask.long.word 0x00 0.--9. 1. " VIRTUALID ,This ID is returned to the Guest OS when the interrupt is acknowledged through the VM Interrupt Acknowledge register, GICV_IAR" endif if (((per.l(ad:0xA0024000+0x104))&0x80000000)==0x80000000) group.long 0x104++0x03 line.long 0x00 "GICH_LR1,List Register 1" bitfld.long 0x00 31. " HW ,Indicates whether this virtual interrupt is a hardware interrupt" "Software,Hardware" bitfld.long 0x00 30. " GRP1 ,Indicates whether this virtual interrupt is a Group 1 virtual interrupt" "Group 0,Group 1" bitfld.long 0x00 28.--29. " STATE ,The state of the interrupt" "Invalid,Pending,Active,Pending and active" textline " " bitfld.long 0x00 23.--27. " PRIORITY ,The priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 10.--19. 1. " PHYSICALID ,Indicates the physical interrupt ID that the hypervisor forwards to the Distributor" hexmask.long.word 0x00 0.--9. 1. " VIRTUALID ,This ID is returned to the Guest OS when the interrupt is acknowledged through the VM Interrupt Acknowledge register, GICV_IAR" else group.long 0x104++0x03 line.long 0x00 "GICH_LR1,List Register 1" bitfld.long 0x00 31. " HW ,Indicates whether this virtual interrupt is a hardware interrupt" "Software,Hardware" bitfld.long 0x00 30. " GRP1 ,Indicates whether this virtual interrupt is a Group 1 virtual interrupt" "Group 0,Group 1" bitfld.long 0x00 28.--29. " STATE ,The state of the interrupt" "Invalid,Pending,Active,Pending and active" textline " " bitfld.long 0x00 23.--27. " PRIORITY ,The priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 19. " EOI ,Indicates whether this interrupt triggers an EOI maintenance interrupt" "Not asserted,Asserted" bitfld.long 0x00 10.--12. " CPUID ,If the interrupt has the VirtualID for an SGI that is 0-15 this field shows the requesting CPU ID" "0,1,2,3,4,5,6,7" textline " " hexmask.long.word 0x00 0.--9. 1. " VIRTUALID ,This ID is returned to the Guest OS when the interrupt is acknowledged through the VM Interrupt Acknowledge register, GICV_IAR" endif if (((per.l(ad:0xA0024000+0x108))&0x80000000)==0x80000000) group.long 0x108++0x03 line.long 0x00 "GICH_LR2,List Register 2" bitfld.long 0x00 31. " HW ,Indicates whether this virtual interrupt is a hardware interrupt" "Software,Hardware" bitfld.long 0x00 30. " GRP1 ,Indicates whether this virtual interrupt is a Group 1 virtual interrupt" "Group 0,Group 1" bitfld.long 0x00 28.--29. " STATE ,The state of the interrupt" "Invalid,Pending,Active,Pending and active" textline " " bitfld.long 0x00 23.--27. " PRIORITY ,The priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 10.--19. 1. " PHYSICALID ,Indicates the physical interrupt ID that the hypervisor forwards to the Distributor" hexmask.long.word 0x00 0.--9. 1. " VIRTUALID ,This ID is returned to the Guest OS when the interrupt is acknowledged through the VM Interrupt Acknowledge register, GICV_IAR" else group.long 0x108++0x03 line.long 0x00 "GICH_LR2,List Register 2" bitfld.long 0x00 31. " HW ,Indicates whether this virtual interrupt is a hardware interrupt" "Software,Hardware" bitfld.long 0x00 30. " GRP1 ,Indicates whether this virtual interrupt is a Group 1 virtual interrupt" "Group 0,Group 1" bitfld.long 0x00 28.--29. " STATE ,The state of the interrupt" "Invalid,Pending,Active,Pending and active" textline " " bitfld.long 0x00 23.--27. " PRIORITY ,The priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 19. " EOI ,Indicates whether this interrupt triggers an EOI maintenance interrupt" "Not asserted,Asserted" bitfld.long 0x00 10.--12. " CPUID ,If the interrupt has the VirtualID for an SGI that is 0-15 this field shows the requesting CPU ID" "0,1,2,3,4,5,6,7" textline " " hexmask.long.word 0x00 0.--9. 1. " VIRTUALID ,This ID is returned to the Guest OS when the interrupt is acknowledged through the VM Interrupt Acknowledge register, GICV_IAR" endif if (((per.l(ad:0xA0024000+0x10C))&0x80000000)==0x80000000) group.long 0x10C++0x03 line.long 0x00 "GICH_LR3,List Register 3" bitfld.long 0x00 31. " HW ,Indicates whether this virtual interrupt is a hardware interrupt" "Software,Hardware" bitfld.long 0x00 30. " GRP1 ,Indicates whether this virtual interrupt is a Group 1 virtual interrupt" "Group 0,Group 1" bitfld.long 0x00 28.--29. " STATE ,The state of the interrupt" "Invalid,Pending,Active,Pending and active" textline " " bitfld.long 0x00 23.--27. " PRIORITY ,The priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 10.--19. 1. " PHYSICALID ,Indicates the physical interrupt ID that the hypervisor forwards to the Distributor" hexmask.long.word 0x00 0.--9. 1. " VIRTUALID ,This ID is returned to the Guest OS when the interrupt is acknowledged through the VM Interrupt Acknowledge register, GICV_IAR" else group.long 0x10C++0x03 line.long 0x00 "GICH_LR3,List Register 3" bitfld.long 0x00 31. " HW ,Indicates whether this virtual interrupt is a hardware interrupt" "Software,Hardware" bitfld.long 0x00 30. " GRP1 ,Indicates whether this virtual interrupt is a Group 1 virtual interrupt" "Group 0,Group 1" bitfld.long 0x00 28.--29. " STATE ,The state of the interrupt" "Invalid,Pending,Active,Pending and active" textline " " bitfld.long 0x00 23.--27. " PRIORITY ,The priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 19. " EOI ,Indicates whether this interrupt triggers an EOI maintenance interrupt" "Not asserted,Asserted" bitfld.long 0x00 10.--12. " CPUID ,If the interrupt has the VirtualID for an SGI that is 0-15 this field shows the requesting CPU ID" "0,1,2,3,4,5,6,7" textline " " hexmask.long.word 0x00 0.--9. 1. " VIRTUALID ,This ID is returned to the Guest OS when the interrupt is acknowledged through the VM Interrupt Acknowledge register, GICV_IAR" endif tree.end base ad:0xA0026000 width 12. tree "Virtual CPU Interface" group.long 0x0000++0x03 line.long 0x00 "GICV_CTLR,Virtual Machine Control Register" bitfld.long 0x00 9. " EOIMODE ,Controls the behavior associated with the GICV_EOIR GICV_AEOIR and GICV_DIR registers" "Priority drop/Deactivate,Priority drop" bitfld.long 0x00 4. " CBPR ,Controls whether the GICV_BPR controls both Group 0 and Group 1 virtual interrupts" "BPR/ABPR split,BPR common" bitfld.long 0x00 3. " FIQEN ,Controls whether interrupts marked as Group 0 are presented as virtual FIQs" "IRQs,FIQs" textline " " bitfld.long 0x00 2. " ACKCTL ,Acknowledge Control" "ID 1022 interrupt,Corresponding interrupt" bitfld.long 0x00 1. " ENABLEGRP1 ,Enables the signaling of Group 1 virtual interrupts by the virtual CPU interface to the virtual machine" "Disabled,Enabled" bitfld.long 0x00 0. " ENABLEGRP0 ,Enables the signaling of Group 0 virtual interrupts by the virtual CPU interface to the virtual machine" "Disabled,Enabled" group.long 0x0004++0x03 line.long 0x00 "GICV_PMR,VM Priority Mask Register" bitfld.long 0x00 3.--7. " PRIORITY ,Priority mask level for CPU interface" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x0008++0x03 line.long 0x00 "GICV_BPR,VM Binary Point Register" bitfld.long 0x00 0.--2. " BINARY_POINT ,The value of this field controls how the 8-bit interrupt priority field is split into a group priority field and subpriority field" "Reserved,Reserved,[7:3]/[2:0],[7:4]/[3:0],[7:5]/[4:0],[7:6]/[5:0],[7]/[6:0],-/[7:0]" hgroup.long 0x000C++0x03 hide.long 0x00 "GICV_IAR,VM Interrupt Acknowledge Register" in wgroup.long 0x0010++0x03 line.long 0x00 "GICV_EOIR,VM End of Interrupt Register" bitfld.long 0x00 10.--12. " CPUID ,On a multiprocessor implementation if the write refers to an SGI this field contains the CPUID value from the corresponding GICC_IAR access" "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 0.--9. 1. " EOIINTID ,The Interrupt ID value from the corresponding GICC_IAR access" rgroup.long 0x0014++0x03 line.long 0x00 "GICV_RPR,VM Running Priority Register" hexmask.long.byte 0x00 0.--7. 1. " PRIORITY ,The current running priority on the Virtual CPU interface" rgroup.long 0x0018++0x03 line.long 0x00 "GICV_HPPIR,VM Highest Priority Pending Interrupt Register" bitfld.long 0x00 10.--12. " CPUID ,On a multiprocessor implementation if the PENDINTID field returns the ID of an SGI this field contains the CPUID value for that interrupt" "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 0.--9. 1. " PENDINTID ,The interrupt ID of the highest priority pending interrupt" group.long 0x001C++0x03 line.long 0x00 "GICV_ABPR,VM Aliased Binary Point Register" bitfld.long 0x00 0.--2. " BINARY_POINT ,The value of this field controls how the 8-bit interrupt priority field is split into a group priority field and subpriority field" "[7:1]/[0],[7:2]/[1:0],[7:3]/[2:0],[7:4]/[3:0],[7:5]/[4:0],[7:6]/[5:0],[7]/[6:0],-/[7:0]" hgroup.long 0x0020++0x03 hide.long 0x00 "GICV_AIAR,VM Aliased Interrupt Acknowledge Register" in wgroup.long 0x0024++0x03 line.long 0x00 "GICV_AEOIR,VM Aliased End of Interrupt Register" bitfld.long 0x00 10.--12. " CPUID ,On a multiprocessor implementation if the write refers to an SGI this field contains the CPUID value from the corresponding GICC_IAR access" "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 0.--9. 1. " EOIINTID ,The Interrupt ID value from the corresponding GICC_IAR access" rgroup.long 0x0028++0x03 line.long 0x00 "GICV_AHPPIR,VM Aliased Highest Priority Pending Interrupt Register" bitfld.long 0x00 10.--12. " CPUID ,On a multiprocessor implementation if the PENDINTID field returns the ID of an SGI this field contains the CPUID value for that interrupt" "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 0.--9. 1. " PENDINTID ,The interrupt ID of the highest priority pending interrupt" group.long 0x00D0++0x03 line.long 0x00 "GICV_APR0,VM Active Priority Register" bitfld.long 0x00 31. " APB31 ,Determines whether the corresponding preemption level is active" "Not active,Active" bitfld.long 0x00 30. " APB30 ,Determines whether the corresponding preemption level is active" "Not active,Active" bitfld.long 0x00 29. " APB29 ,Determines whether the corresponding preemption level is active" "Not active,Active" textline " " bitfld.long 0x00 28. " APB28 ,Determines whether the corresponding preemption level is active" "Not active,Active" bitfld.long 0x00 27. " APB27 ,Determines whether the corresponding preemption level is active" "Not active,Active" bitfld.long 0x00 26. " APB26 ,Determines whether the corresponding preemption level is active" "Not active,Active" textline " " bitfld.long 0x00 25. " APB25 ,Determines whether the corresponding preemption level is active" "Not active,Active" bitfld.long 0x00 24. " APB24 ,Determines whether the corresponding preemption level is active" "Not active,Active" bitfld.long 0x00 23. " APB23 ,Determines whether the corresponding preemption level is active" "Not active,Active" textline " " bitfld.long 0x00 22. " APB22 ,Determines whether the corresponding preemption level is active" "Not active,Active" bitfld.long 0x00 21. " APB21 ,Determines whether the corresponding preemption level is active" "Not active,Active" bitfld.long 0x00 20. " APB20 ,Determines whether the corresponding preemption level is active" "Not active,Active" textline " " bitfld.long 0x00 19. " APB19 ,Determines whether the corresponding preemption level is active" "Not active,Active" bitfld.long 0x00 18. " APB18 ,Determines whether the corresponding preemption level is active" "Not active,Active" bitfld.long 0x00 17. " APB17 ,Determines whether the corresponding preemption level is active" "Not active,Active" textline " " bitfld.long 0x00 16. " APB16 ,Determines whether the corresponding preemption level is active" "Not active,Active" bitfld.long 0x00 15. " APB15 ,Determines whether the corresponding preemption level is active" "Not active,Active" bitfld.long 0x00 14. " APB14 ,Determines whether the corresponding preemption level is active" "Not active,Active" textline " " bitfld.long 0x00 13. " APB13 ,Determines whether the corresponding preemption level is active" "Not active,Active" bitfld.long 0x00 12. " APB12 ,Determines whether the corresponding preemption level is active" "Not active,Active" bitfld.long 0x00 11. " APB11 ,Determines whether the corresponding preemption level is active" "Not active,Active" textline " " bitfld.long 0x00 10. " APB10 ,Determines whether the corresponding preemption level is active" "Not active,Active" bitfld.long 0x00 9. " APB9 ,Determines whether the corresponding preemption level is active" "Not active,Active" bitfld.long 0x00 8. " APB8 ,Determines whether the corresponding preemption level is active" "Not active,Active" textline " " bitfld.long 0x00 7. " APB7 ,Determines whether the corresponding preemption level is active" "Not active,Active" bitfld.long 0x00 6. " APB6 ,Determines whether the corresponding preemption level is active" "Not active,Active" bitfld.long 0x00 5. " APB5 ,Determines whether the corresponding preemption level is active" "Not active,Active" textline " " bitfld.long 0x00 4. " APB4 ,Determines whether the corresponding preemption level is active" "Not active,Active" bitfld.long 0x00 3. " APB3 ,Determines whether the corresponding preemption level is active" "Not active,Active" bitfld.long 0x00 2. " APB2 ,Determines whether the corresponding preemption level is active" "Not active,Active" textline " " bitfld.long 0x00 1. " APB1 ,Determines whether the corresponding preemption level is active" "Not active,Active" bitfld.long 0x00 0. " APB0 ,Determines whether the corresponding preemption level is active" "Not active,Active" rgroup.long 0x00FC++0x03 line.long 0x00 "GICV_IIDR,VM CPU Interface Identification Register" hexmask.long.word 0x00 20.--31. 1. " PRODID ,Product ID" bitfld.long 0x00 16.--19. " ARCH_VER ,Identifies the architecture version of the GIC" "GICv1,GICv2,?..." textline " " bitfld.long 0x00 12.--15. " REV ,Revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x00 0.--11. 1. " IMP ,Implementer" wgroup.long 0x1000++0x03 line.long 0x00 "GICV_DIR,VM Deactivate Interrupt Register" bitfld.long 0x00 10.--12. " CPUID ,On a multiprocessor implementation this field identifies the processor that requested the interrupt" "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 0.--9. 1. " INTID ,The interrupt ID" tree.end endif width 0x0B tree.end AUTOINDENT.POP tree.end endif tree "ADC (Analog-to-Digital Converter)" base ad:0x0 sif (cpuis("STM32MP13*")) tree "ADC1" base ad:0x48003000 group.long 0x0++0x1B line.long 0x0 "ADC_ISR,ADC interrupt and status register" bitfld.long 0x0 10. "JQOVF,Injected context queue overflow" "0: No injected context queue overflow occurred (or..,1: Injected context queue overflow has occurred" bitfld.long 0x0 9. "AWD3,Analog watchdog 3 flag" "0: No analog watchdog 3 event occurred (or the flag..,1: Analog watchdog 3 event occurred" newline bitfld.long 0x0 8. "AWD2,Analog watchdog 2 flag" "0: No analog watchdog 2 event occurred (or the flag..,1: Analog watchdog 2 event occurred" bitfld.long 0x0 7. "AWD1,Analog watchdog 1 flag" "0: No analog watchdog 1 event occurred (or the flag..,1: Analog watchdog 1 event occurred" newline bitfld.long 0x0 6. "JEOS,Injected channel end of sequence flag" "0: Injected conversion sequence not complete (or..,1: Injected conversions complete" bitfld.long 0x0 5. "JEOC,Injected channel end of conversion flag" "0: Injected channel conversion not complete (or the..,1: Injected channel conversion complete" newline bitfld.long 0x0 4. "OVR,ADC overrun" "0: No overrun occurred (or the flag event was..,1: Overrun has occurred" bitfld.long 0x0 3. "EOS,End of regular sequence flag" "0: Regular Conversions sequence not complete (or..,1: Regular Conversions sequence complete" newline bitfld.long 0x0 2. "EOC,End of conversion flag" "0: Regular channel conversion not complete (or the..,1: Regular channel conversion complete" bitfld.long 0x0 1. "EOSMP,End of sampling flag" "0: not at the end of the sampling phase (or the..,1: End of sampling phase reached" newline bitfld.long 0x0 0. "ADRDY,ADC ready" "0: ADC not yet ready to start conversion (or the..,1: ADC is ready to start conversion" line.long 0x4 "ADC_IER,ADC interrupt enable register" bitfld.long 0x4 10. "JQOVFIE,Injected context queue overflow interrupt enable" "0: Injected Context Queue Overflow interrupt disabled,1: Injected Context Queue Overflow interrupt.." bitfld.long 0x4 9. "AWD3IE,Analog watchdog 3 interrupt enable" "0: Analog watchdog 3 interrupt disabled,1: Analog watchdog 3 interrupt enabled" newline bitfld.long 0x4 8. "AWD2IE,Analog watchdog 2 interrupt enable" "0: Analog watchdog 2 interrupt disabled,1: Analog watchdog 2 interrupt enabled" bitfld.long 0x4 7. "AWD1IE,Analog watchdog 1 interrupt enable" "0: Analog watchdog 1 interrupt disabled,1: Analog watchdog 1 interrupt enabled" newline bitfld.long 0x4 6. "JEOSIE,End of injected sequence of conversions interrupt enable" "0: JEOS interrupt disabled,1: JEOS interrupt enabled. An interrupt is.." bitfld.long 0x4 5. "JEOCIE,End of injected conversion interrupt enable" "0: JEOC interrupt disabled.,1: JEOC interrupt enabled. An interrupt is.." newline bitfld.long 0x4 4. "OVRIE,Overrun interrupt enable" "0: Overrun interrupt disabled,1: Overrun interrupt enabled. An interrupt is.." bitfld.long 0x4 3. "EOSIE,End of regular sequence of conversions interrupt enable" "0: EOS interrupt disabled,1: EOS interrupt enabled. An interrupt is generated.." newline bitfld.long 0x4 2. "EOCIE,End of regular conversion interrupt enable" "0: EOC interrupt disabled.,1: EOC interrupt enabled. An interrupt is generated.." bitfld.long 0x4 1. "EOSMPIE,End of sampling flag interrupt enable for regular conversions" "0: EOSMP interrupt disabled.,1: EOSMP interrupt enabled. An interrupt is.." newline bitfld.long 0x4 0. "ADRDYIE,ADC ready interrupt enable" "0: ADRDY interrupt disabled,1: ADRDY interrupt enabled. An interrupt is.." line.long 0x8 "ADC_CR,ADC control register" bitfld.long 0x8 31. "ADCAL,ADC calibration" "0: Calibration complete,1: Write 1 to calibrate the ADC. Read at 1 means.." bitfld.long 0x8 30. "ADCALDIF,Differential mode for calibration" "0: Writing ADCAL launches a calibration in..,1: Writing ADCAL launches a calibration in.." newline bitfld.long 0x8 29. "DEEPPWD,Deep-power-down enable" "0: ADC not in Deep-power down,1: ADC in Deep-power-down (default reset state)" bitfld.long 0x8 28. "ADVREGEN,ADC voltage regulator enable" "0: ADC Voltage regulator disabled,1: ADC Voltage regulator enabled." newline bitfld.long 0x8 5. "JADSTP,ADC stop of injected conversion command" "0: No ADC stop injected conversion command ongoing,1: Write 1 to stop injected conversions ongoing." bitfld.long 0x8 4. "ADSTP,ADC stop of regular conversion command" "0: No ADC stop regular conversion command ongoing,1: Write 1 to stop regular conversions ongoing." newline bitfld.long 0x8 3. "JADSTART,ADC start of injected conversion" "0: No ADC injected conversion is ongoing.,1: Write 1 to start injected conversions. Read 1.." bitfld.long 0x8 2. "ADSTART,ADC start of regular conversion" "0: No ADC regular conversion is ongoing.,1: Write 1 to start regular conversions. Read 1.." newline bitfld.long 0x8 1. "ADDIS,ADC disable command" "0: no ADDIS command ongoing,1: Write 1 to disable the ADC. Read 1 means that an.." bitfld.long 0x8 0. "ADEN,ADC enable control" "0: ADC is disabled (OFF state),1: Write 1 to enable the ADC." line.long 0xC "ADC_CFGR,ADC configuration register" bitfld.long 0xC 31. "JQDIS,Injected Queue disable" "0: Injected Queue enabled,1: Injected Queue disabled" hexmask.long.byte 0xC 26.--30. 1. "AWD1CH,Analog watchdog 1 channel selection" newline bitfld.long 0xC 25. "JAUTO,Automatic injected group conversion" "0: Automatic injected group conversion disabled,1: Automatic injected group conversion enabled" bitfld.long 0xC 24. "JAWD1EN,Analog watchdog 1 enable on injected channels" "0: Analog watchdog 1 disabled on injected channels,1: Analog watchdog 1 enabled on injected channels" newline bitfld.long 0xC 23. "AWD1EN,Analog watchdog 1 enable on regular channels" "0: Analog watchdog 1 disabled on regular channels,1: Analog watchdog 1 enabled on regular channels" bitfld.long 0xC 22. "AWD1SGL,Enable the watchdog 1 on a single channel or on all channels" "0: Analog watchdog 1 enabled on all channels,1: Analog watchdog 1 enabled on a single channel" newline bitfld.long 0xC 21. "JQM,JSQR queue mode" "0: JSQR mode 0: The Queue is never empty and..,1: JSQR mode 1: The Queue can be empty and when.." bitfld.long 0xC 20. "JDISCEN,Discontinuous mode on injected channels" "0: Discontinuous mode on injected channels disabled,1: Discontinuous mode on injected channels enabled" newline bitfld.long 0xC 17.--19. "DISCNUM,Discontinuous mode channel count" "0: 1 channel,1: 2 channels,?,?,?,?,?,7: 8 channels" bitfld.long 0xC 16. "DISCEN,Discontinuous mode for regular channels" "0: Discontinuous mode for regular channels disabled,1: Discontinuous mode for regular channels enabled" newline bitfld.long 0xC 15. "ALIGN,Data alignment" "0: Right alignment,1: Left alignment" bitfld.long 0xC 14. "AUTDLY,Delayed conversion mode" "0: Auto-delayed conversion mode off,1: Auto-delayed conversion mode on" newline bitfld.long 0xC 13. "CONT,Single / Continuous conversion mode for regular conversions" "0: Single conversion mode,1: Continuous conversion mode" bitfld.long 0xC 12. "OVRMOD,Overrun mode" "0: ADC_DR register is preserved with the old data..,1: ADC_DR register is overwritten with the last.." newline bitfld.long 0xC 10.--11. "EXTEN,External trigger enable and polarity selection for regular channels" "0,1,2,3" bitfld.long 0xC 9. "EXTSEL4,External trigger selection for regular group" "0,1" newline bitfld.long 0xC 8. "EXTSEL3,External trigger selection for regular group" "0,1" bitfld.long 0xC 7. "EXTSEL2,External trigger selection for regular group" "0,1" newline bitfld.long 0xC 6. "EXTSEL1,External trigger selection for regular group" "0,1" bitfld.long 0xC 5. "EXTSEL0,External trigger selection for regular group" "0,1" newline bitfld.long 0xC 3.--4. "RES,Data resolution" "0: 12-bit,1: 10-bit,2: 8-bit,3: 6-bit" bitfld.long 0xC 2. "DFSDMCFG,DFSDM mode configuration" "0: DFSDM mode disabled,1: DFSDM mode enabled" newline bitfld.long 0xC 1. "DMACFG,Direct memory access configuration" "0: DMA One Shot mode selected,1: DMA Circular mode selected" bitfld.long 0xC 0. "DMAEN,Direct memory access enable" "0: DMA disabled,1: DMA enabled" line.long 0x10 "ADC_CFGR2,ADC configuration register 2" bitfld.long 0x10 27. "SMPTRIG,Sampling time control trigger mode" "0: Sampling time control trigger mode disabled,1: Sampling time control trigger mode enabled" bitfld.long 0x10 26. "BULB,Bulb sampling mode" "0: Bulb sampling mode disabled,1: Bulb sampling mode enabled. The sampling period.." newline bitfld.long 0x10 25. "SWTRIG,Software trigger bit for sampling time control trigger mode" "0: Software trigger starts the conversion for..,1: Software trigger starts the sampling for.." bitfld.long 0x10 10. "ROVSM,Regular Oversampling mode" "0: Continued mode: When injected conversions are..,1: Resumed mode: When injected conversions are.." newline bitfld.long 0x10 9. "TROVS,Triggered Regular Oversampling" "0: All oversampled conversions for a channel are..,1: Each oversampled conversion for a channel needs.." hexmask.long.byte 0x10 5.--8. 1. "OVSS,Oversampling shift" newline bitfld.long 0x10 2.--4. "OVSR,Oversampling ratio" "0: 2x,1: 4x,2: 8x,3: 16x,4: 32x,5: 64x,6: 128x,7: 256x" bitfld.long 0x10 1. "JOVSE,Injected Oversampling Enable" "0: Injected Oversampling disabled,1: Injected Oversampling enabled" newline bitfld.long 0x10 0. "ROVSE,Regular Oversampling Enable" "0: Regular Oversampling disabled,1: Regular Oversampling enabled" line.long 0x14 "ADC_SMPR1,ADC sample time register 1" bitfld.long 0x14 31. "SMPPLUS,Addition of one clock cycle to the sampling time." "0: The sampling time remains set to 2.5 ADC clock..,1: 2.5 ADC clock cycle sampling time becomes 3.5.." bitfld.long 0x14 27.--29. "SMP9,Channel x sampling time selection" "0: 2.5 ADC clock cycles,1: 6.5 ADC clock cycles,2: 12.5 ADC clock cycles,3: 24.5 ADC clock cycles,4: 47.5 ADC clock cycles,5: 92.5 ADC clock cycles,6: 247.5 ADC clock cycles,7: 640.5 ADC clock cycles" newline bitfld.long 0x14 24.--26. "SMP8,Channel x sampling time selection" "0: 2.5 ADC clock cycles,1: 6.5 ADC clock cycles,2: 12.5 ADC clock cycles,3: 24.5 ADC clock cycles,4: 47.5 ADC clock cycles,5: 92.5 ADC clock cycles,6: 247.5 ADC clock cycles,7: 640.5 ADC clock cycles" bitfld.long 0x14 21.--23. "SMP7,Channel x sampling time selection" "0: 2.5 ADC clock cycles,1: 6.5 ADC clock cycles,2: 12.5 ADC clock cycles,3: 24.5 ADC clock cycles,4: 47.5 ADC clock cycles,5: 92.5 ADC clock cycles,6: 247.5 ADC clock cycles,7: 640.5 ADC clock cycles" newline bitfld.long 0x14 18.--20. "SMP6,Channel x sampling time selection" "0: 2.5 ADC clock cycles,1: 6.5 ADC clock cycles,2: 12.5 ADC clock cycles,3: 24.5 ADC clock cycles,4: 47.5 ADC clock cycles,5: 92.5 ADC clock cycles,6: 247.5 ADC clock cycles,7: 640.5 ADC clock cycles" bitfld.long 0x14 15.--17. "SMP5,Channel x sampling time selection" "0: 2.5 ADC clock cycles,1: 6.5 ADC clock cycles,2: 12.5 ADC clock cycles,3: 24.5 ADC clock cycles,4: 47.5 ADC clock cycles,5: 92.5 ADC clock cycles,6: 247.5 ADC clock cycles,7: 640.5 ADC clock cycles" newline bitfld.long 0x14 12.--14. "SMP4,Channel x sampling time selection" "0: 2.5 ADC clock cycles,1: 6.5 ADC clock cycles,2: 12.5 ADC clock cycles,3: 24.5 ADC clock cycles,4: 47.5 ADC clock cycles,5: 92.5 ADC clock cycles,6: 247.5 ADC clock cycles,7: 640.5 ADC clock cycles" bitfld.long 0x14 9.--11. "SMP3,Channel x sampling time selection" "0: 2.5 ADC clock cycles,1: 6.5 ADC clock cycles,2: 12.5 ADC clock cycles,3: 24.5 ADC clock cycles,4: 47.5 ADC clock cycles,5: 92.5 ADC clock cycles,6: 247.5 ADC clock cycles,7: 640.5 ADC clock cycles" newline bitfld.long 0x14 6.--8. "SMP2,Channel x sampling time selection" "0: 2.5 ADC clock cycles,1: 6.5 ADC clock cycles,2: 12.5 ADC clock cycles,3: 24.5 ADC clock cycles,4: 47.5 ADC clock cycles,5: 92.5 ADC clock cycles,6: 247.5 ADC clock cycles,7: 640.5 ADC clock cycles" bitfld.long 0x14 3.--5. "SMP1,Channel x sampling time selection" "0: 2.5 ADC clock cycles,1: 6.5 ADC clock cycles,2: 12.5 ADC clock cycles,3: 24.5 ADC clock cycles,4: 47.5 ADC clock cycles,5: 92.5 ADC clock cycles,6: 247.5 ADC clock cycles,7: 640.5 ADC clock cycles" newline bitfld.long 0x14 0.--2. "SMP0,Channel x sampling time selection" "0: 2.5 ADC clock cycles,1: 6.5 ADC clock cycles,2: 12.5 ADC clock cycles,3: 24.5 ADC clock cycles,4: 47.5 ADC clock cycles,5: 92.5 ADC clock cycles,6: 247.5 ADC clock cycles,7: 640.5 ADC clock cycles" line.long 0x18 "ADC_SMPR2,ADC sample time register 2" bitfld.long 0x18 24.--26. "SMP18,Channel x sampling time selection" "0: 2.5 ADC clock cycles,1: 6.5 ADC clock cycles,2: 12.5 ADC clock cycles,3: 24.5 ADC clock cycles,4: 47.5 ADC clock cycles,5: 92.5 ADC clock cycles,6: 247.5 ADC clock cycles,7: 640.5 ADC clock cycles" bitfld.long 0x18 21.--23. "SMP17,Channel x sampling time selection" "0: 2.5 ADC clock cycles,1: 6.5 ADC clock cycles,2: 12.5 ADC clock cycles,3: 24.5 ADC clock cycles,4: 47.5 ADC clock cycles,5: 92.5 ADC clock cycles,6: 247.5 ADC clock cycles,7: 640.5 ADC clock cycles" newline bitfld.long 0x18 18.--20. "SMP16,Channel x sampling time selection" "0: 2.5 ADC clock cycles,1: 6.5 ADC clock cycles,2: 12.5 ADC clock cycles,3: 24.5 ADC clock cycles,4: 47.5 ADC clock cycles,5: 92.5 ADC clock cycles,6: 247.5 ADC clock cycles,7: 640.5 ADC clock cycles" bitfld.long 0x18 15.--17. "SMP15,Channel x sampling time selection" "0: 2.5 ADC clock cycles,1: 6.5 ADC clock cycles,2: 12.5 ADC clock cycles,3: 24.5 ADC clock cycles,4: 47.5 ADC clock cycles,5: 92.5 ADC clock cycles,6: 247.5 ADC clock cycles,7: 640.5 ADC clock cycles" newline bitfld.long 0x18 12.--14. "SMP14,Channel x sampling time selection" "0: 2.5 ADC clock cycles,1: 6.5 ADC clock cycles,2: 12.5 ADC clock cycles,3: 24.5 ADC clock cycles,4: 47.5 ADC clock cycles,5: 92.5 ADC clock cycles,6: 247.5 ADC clock cycles,7: 640.5 ADC clock cycles" bitfld.long 0x18 9.--11. "SMP13,Channel x sampling time selection" "0: 2.5 ADC clock cycles,1: 6.5 ADC clock cycles,2: 12.5 ADC clock cycles,3: 24.5 ADC clock cycles,4: 47.5 ADC clock cycles,5: 92.5 ADC clock cycles,6: 247.5 ADC clock cycles,7: 640.5 ADC clock cycles" newline bitfld.long 0x18 6.--8. "SMP12,Channel x sampling time selection" "0: 2.5 ADC clock cycles,1: 6.5 ADC clock cycles,2: 12.5 ADC clock cycles,3: 24.5 ADC clock cycles,4: 47.5 ADC clock cycles,5: 92.5 ADC clock cycles,6: 247.5 ADC clock cycles,7: 640.5 ADC clock cycles" bitfld.long 0x18 3.--5. "SMP11,Channel x sampling time selection" "0: 2.5 ADC clock cycles,1: 6.5 ADC clock cycles,2: 12.5 ADC clock cycles,3: 24.5 ADC clock cycles,4: 47.5 ADC clock cycles,5: 92.5 ADC clock cycles,6: 247.5 ADC clock cycles,7: 640.5 ADC clock cycles" newline bitfld.long 0x18 0.--2. "SMP10,Channel x sampling time selection" "0: 2.5 ADC clock cycles,1: 6.5 ADC clock cycles,2: 12.5 ADC clock cycles,3: 24.5 ADC clock cycles,4: 47.5 ADC clock cycles,5: 92.5 ADC clock cycles,6: 247.5 ADC clock cycles,7: 640.5 ADC clock cycles" group.long 0x20++0xB line.long 0x0 "ADC_TR1,ADC watchdog threshold register 1" hexmask.long.word 0x0 16.--27. 1. "HT1,Analog watchdog 1 higher threshold" bitfld.long 0x0 12.--14. "AWDFILT,Analog watchdog filtering parameter" "0: No filtering,1: two consecutive detection generates an AWDx flag..,?,?,?,?,?,7: Eight consecutive detection generates an AWDx.." newline hexmask.long.word 0x0 0.--11. 1. "LT1,Analog watchdog 1 lower threshold" line.long 0x4 "ADC_TR2,ADC watchdog threshold register 2" hexmask.long.byte 0x4 16.--23. 1. "HT2,Analog watchdog 2 higher threshold" hexmask.long.byte 0x4 0.--7. 1. "LT2,Analog watchdog 2 lower threshold" line.long 0x8 "ADC_TR3,ADC watchdog threshold register 3" hexmask.long.byte 0x8 16.--23. 1. "HT3,Analog watchdog 3 higher threshold" hexmask.long.byte 0x8 0.--7. 1. "LT3,Analog watchdog 3 lower threshold" group.long 0x30++0xF line.long 0x0 "ADC_SQR1,ADC regular sequence register 1" hexmask.long.byte 0x0 24.--28. 1. "SQ4,4th conversion in regular sequence" hexmask.long.byte 0x0 18.--22. 1. "SQ3,3rd conversion in regular sequence" newline hexmask.long.byte 0x0 12.--16. 1. "SQ2,2nd conversion in regular sequence" hexmask.long.byte 0x0 6.--10. 1. "SQ1,1st conversion in regular sequence" newline hexmask.long.byte 0x0 0.--3. 1. "L,Regular channel sequence length" line.long 0x4 "ADC_SQR2,ADC regular sequence register 2" hexmask.long.byte 0x4 24.--28. 1. "SQ9,9th conversion in regular sequence" hexmask.long.byte 0x4 18.--22. 1. "SQ8,8th conversion in regular sequence" newline hexmask.long.byte 0x4 12.--16. 1. "SQ7,7th conversion in regular sequence" hexmask.long.byte 0x4 6.--10. 1. "SQ6,6th conversion in regular sequence" newline hexmask.long.byte 0x4 0.--4. 1. "SQ5,5th conversion in regular sequence" line.long 0x8 "ADC_SQR3,ADC regular sequence register 3" hexmask.long.byte 0x8 24.--28. 1. "SQ14,14th conversion in regular sequence" hexmask.long.byte 0x8 18.--22. 1. "SQ13,13th conversion in regular sequence" newline hexmask.long.byte 0x8 12.--16. 1. "SQ12,12th conversion in regular sequence" hexmask.long.byte 0x8 6.--10. 1. "SQ11,11th conversion in regular sequence" newline hexmask.long.byte 0x8 0.--4. 1. "SQ10,10th conversion in regular sequence" line.long 0xC "ADC_SQR4,ADC regular sequence register 4" hexmask.long.byte 0xC 6.--10. 1. "SQ16,16th conversion in regular sequence" hexmask.long.byte 0xC 0.--4. 1. "SQ15,15th conversion in regular sequence" rgroup.long 0x40++0x3 line.long 0x0 "ADC_DR,ADC regular data register" hexmask.long.word 0x0 0.--15. 1. "RDATA,Regular data converted" group.long 0x4C++0x3 line.long 0x0 "ADC_JSQR,ADC injected sequence register" hexmask.long.byte 0x0 27.--31. 1. "JSQ4,4th conversion in the injected sequence" hexmask.long.byte 0x0 21.--25. 1. "JSQ3,3rd conversion in the injected sequence" newline hexmask.long.byte 0x0 15.--19. 1. "JSQ2,2nd conversion in the injected sequence" hexmask.long.byte 0x0 9.--13. 1. "JSQ1,1st conversion in the injected sequence" newline bitfld.long 0x0 7.--8. "JEXTEN,External trigger enable and polarity selection for injected channels" "0: If JQDIS = 0 (queue enabled) hardware and..,1: Hardware trigger detection on the rising edge,2: Hardware trigger detection on the falling edge,3: Hardware trigger detection on both the rising.." hexmask.long.byte 0x0 2.--6. 1. "JEXTSEL,External Trigger Selection for injected group" newline bitfld.long 0x0 0.--1. "JL,Injected channel sequence length" "0: 1 conversion,1: 2 conversions,2: 3 conversions,3: 4 conversions" group.long 0x60++0xF line.long 0x0 "ADC_OFR1,ADC offset 1 register" bitfld.long 0x0 31. "OFFSET_EN,Offset y enable" "0,1" hexmask.long.byte 0x0 26.--30. 1. "OFFSET_CH,Channel selection for the data offset y" newline bitfld.long 0x0 25. "SATEN,Saturation enable" "0: No saturation control offset result can be signed,1: Saturation enabled offset result unsigned and.." bitfld.long 0x0 24. "OFFSETPOS,Positive offset" "0: Negative offset,1: Positive offset" newline hexmask.long.word 0x0 0.--11. 1. "OFFSET,Data offset y for the channel programmed into bits OFFSET_CH[4:0]" line.long 0x4 "ADC_OFR2,ADC offset 2 register" bitfld.long 0x4 31. "OFFSET_EN,Offset y enable" "0,1" hexmask.long.byte 0x4 26.--30. 1. "OFFSET_CH,Channel selection for the data offset y" newline bitfld.long 0x4 25. "SATEN,Saturation enable" "0: No saturation control offset result can be signed,1: Saturation enabled offset result unsigned and.." bitfld.long 0x4 24. "OFFSETPOS,Positive offset" "0: Negative offset,1: Positive offset" newline hexmask.long.word 0x4 0.--11. 1. "OFFSET,Data offset y for the channel programmed into bits OFFSET_CH[4:0]" line.long 0x8 "ADC_OFR3,ADC offset 3 register" bitfld.long 0x8 31. "OFFSET_EN,Offset y enable" "0,1" hexmask.long.byte 0x8 26.--30. 1. "OFFSET_CH,Channel selection for the data offset y" newline bitfld.long 0x8 25. "SATEN,Saturation enable" "0: No saturation control offset result can be signed,1: Saturation enabled offset result unsigned and.." bitfld.long 0x8 24. "OFFSETPOS,Positive offset" "0: Negative offset,1: Positive offset" newline hexmask.long.word 0x8 0.--11. 1. "OFFSET,Data offset y for the channel programmed into bits OFFSET_CH[4:0]" line.long 0xC "ADC_OFR4,ADC offset 4 register" bitfld.long 0xC 31. "OFFSET_EN,Offset y enable" "0,1" hexmask.long.byte 0xC 26.--30. 1. "OFFSET_CH,Channel selection for the data offset y" newline bitfld.long 0xC 25. "SATEN,Saturation enable" "0: No saturation control offset result can be signed,1: Saturation enabled offset result unsigned and.." bitfld.long 0xC 24. "OFFSETPOS,Positive offset" "0: Negative offset,1: Positive offset" newline hexmask.long.word 0xC 0.--11. 1. "OFFSET,Data offset y for the channel programmed into bits OFFSET_CH[4:0]" rgroup.long 0x80++0xF line.long 0x0 "ADC_JDR1,ADC injected channel 1 data register" hexmask.long.word 0x0 0.--15. 1. "JDATA,Injected data" line.long 0x4 "ADC_JDR2,ADC injected channel 2 data register" hexmask.long.word 0x4 0.--15. 1. "JDATA,Injected data" line.long 0x8 "ADC_JDR3,ADC injected channel 3 data register" hexmask.long.word 0x8 0.--15. 1. "JDATA,Injected data" line.long 0xC "ADC_JDR4,ADC injected channel 4 data register" hexmask.long.word 0xC 0.--15. 1. "JDATA,Injected data" group.long 0xA0++0x7 line.long 0x0 "ADC_AWD2CR,ADC Analog Watchdog 2 Configuration Register" hexmask.long.tbyte 0x0 0.--18. 1. "AWD2CH,Analog watchdog 2 channel selection" line.long 0x4 "ADC_AWD3CR,ADC Analog Watchdog 3 Configuration Register" hexmask.long.tbyte 0x4 0.--18. 1. "AWD3CH,Analog watchdog 3 channel selection" group.long 0xB0++0x7 line.long 0x0 "ADC_DIFSEL,ADC Differential mode Selection Register" hexmask.long.tbyte 0x0 0.--18. 1. "DIFSEL,Differential mode for channels 18 to 0." line.long 0x4 "ADC_CALFACT,ADC Calibration Factors" hexmask.long.byte 0x4 16.--22. 1. "CALFACT_D,Calibration Factors in differential mode" hexmask.long.byte 0x4 0.--6. 1. "CALFACT_S,Calibration Factors In Single-ended mode" group.long 0xC8++0x3 line.long 0x0 "ADC_OR,ADC option register" bitfld.long 0x0 2. "OP2,VDDQ_DDR channel enable" "0: VDDQ_DDR channel disabled,1: VDDQ_DDR channel enabled" bitfld.long 0x0 1. "OP1,VDDCPU channel enable" "0: VDDCPU channel disabled,1: VDDCPU channel enabled" newline bitfld.long 0x0 0. "OP0,VDDCORE channel enable" "0: VDDCORE channel disabled,1: VDDCORE channel enabled" rgroup.long 0x300++0x3 line.long 0x0 "ADC_CSR,ADC common status register" bitfld.long 0x0 10. "JQOVF_MST,Injected Context Queue Overflow flag of the master ADC" "0,1" bitfld.long 0x0 9. "AWD3_MST,Analog watchdog 3 flag of the master ADC" "0,1" newline bitfld.long 0x0 8. "AWD2_MST,Analog watchdog 2 flag of the master ADC" "0,1" bitfld.long 0x0 7. "AWD1_MST,Analog watchdog 1 flag of the master ADC" "0,1" newline bitfld.long 0x0 6. "JEOS_MST,End of injected sequence flag of the master ADC" "0,1" bitfld.long 0x0 5. "JEOC_MST,End of injected conversion flag of the master ADC" "0,1" newline bitfld.long 0x0 4. "OVR_MST,Overrun flag of the master ADC" "0,1" bitfld.long 0x0 3. "EOS_MST,End of regular sequence flag of the master ADC" "0,1" newline bitfld.long 0x0 2. "EOC_MST,End of regular conversion of the master ADC" "0,1" bitfld.long 0x0 1. "EOSMP_MST,End of Sampling phase flag of the master ADC" "0,1" newline bitfld.long 0x0 0. "ADRDY_MST,Master ADC ready" "0,1" group.long 0x308++0x3 line.long 0x0 "ADC_CCR,ADC common control register" bitfld.long 0x0 24. "VBATEN,VBAT enable" "0: VBAT channel disabled,1: VBAT channel enabled" bitfld.long 0x0 23. "TSEN,VSENSE enable" "0: Temperature sensor channel disabled,1: Temperature sensor channel enabled" newline bitfld.long 0x0 22. "VREFEN,VREFINT enable" "0: VREFINT channel disabled,1: VREFINT channel enabled" hexmask.long.byte 0x0 18.--21. 1. "PRESC,ADC prescaler" newline bitfld.long 0x0 16.--17. "CKMODE,ADC clock mode" "0: adc_ker_ck (x = 1/2) (Asynchronous clock mode)..,1: adc_hclk/1 (Synchronous clock mode). This..,2: adc_hclk/2 (Synchronous clock mode),3: adc_hclk/4 (Synchronous clock mode)" rgroup.long 0x3F0++0xF line.long 0x0 "ADC_HWCFGR0,ADC hardware configuration register" hexmask.long.byte 0x0 12.--15. 1. "IDLEVALUE,Idle value for non-selected channels" hexmask.long.byte 0x0 8.--11. 1. "OPBITS,Number of option bits" newline hexmask.long.byte 0x0 4.--7. 1. "MULPIPE,Number of pipeline stages" hexmask.long.byte 0x0 0.--3. 1. "ADCNUM,Number of ADCs implemented" line.long 0x4 "ADC_VERR,ADC version register" hexmask.long.byte 0x4 4.--7. 1. "MAJREV,Major revision" hexmask.long.byte 0x4 0.--3. 1. "MINREV,Minor revision" line.long 0x8 "ADC_IPDR,ADC identification register" hexmask.long 0x8 0.--31. 1. "ID,Peripheral identifier" line.long 0xC "ADC_SIDR,ADC size identification register" hexmask.long 0xC 0.--31. 1. "SID,Size Identification" tree.end endif sif (cpuis("STM32MP13*")) tree "ADC2" base ad:0x48004000 group.long 0x0++0x1B line.long 0x0 "ADC_ISR,ADC interrupt and status register" bitfld.long 0x0 10. "JQOVF,Injected context queue overflow" "0: No injected context queue overflow occurred (or..,1: Injected context queue overflow has occurred" bitfld.long 0x0 9. "AWD3,Analog watchdog 3 flag" "0: No analog watchdog 3 event occurred (or the flag..,1: Analog watchdog 3 event occurred" newline bitfld.long 0x0 8. "AWD2,Analog watchdog 2 flag" "0: No analog watchdog 2 event occurred (or the flag..,1: Analog watchdog 2 event occurred" bitfld.long 0x0 7. "AWD1,Analog watchdog 1 flag" "0: No analog watchdog 1 event occurred (or the flag..,1: Analog watchdog 1 event occurred" newline bitfld.long 0x0 6. "JEOS,Injected channel end of sequence flag" "0: Injected conversion sequence not complete (or..,1: Injected conversions complete" bitfld.long 0x0 5. "JEOC,Injected channel end of conversion flag" "0: Injected channel conversion not complete (or the..,1: Injected channel conversion complete" newline bitfld.long 0x0 4. "OVR,ADC overrun" "0: No overrun occurred (or the flag event was..,1: Overrun has occurred" bitfld.long 0x0 3. "EOS,End of regular sequence flag" "0: Regular Conversions sequence not complete (or..,1: Regular Conversions sequence complete" newline bitfld.long 0x0 2. "EOC,End of conversion flag" "0: Regular channel conversion not complete (or the..,1: Regular channel conversion complete" bitfld.long 0x0 1. "EOSMP,End of sampling flag" "0: not at the end of the sampling phase (or the..,1: End of sampling phase reached" newline bitfld.long 0x0 0. "ADRDY,ADC ready" "0: ADC not yet ready to start conversion (or the..,1: ADC is ready to start conversion" line.long 0x4 "ADC_IER,ADC interrupt enable register" bitfld.long 0x4 10. "JQOVFIE,Injected context queue overflow interrupt enable" "0: Injected Context Queue Overflow interrupt disabled,1: Injected Context Queue Overflow interrupt.." bitfld.long 0x4 9. "AWD3IE,Analog watchdog 3 interrupt enable" "0: Analog watchdog 3 interrupt disabled,1: Analog watchdog 3 interrupt enabled" newline bitfld.long 0x4 8. "AWD2IE,Analog watchdog 2 interrupt enable" "0: Analog watchdog 2 interrupt disabled,1: Analog watchdog 2 interrupt enabled" bitfld.long 0x4 7. "AWD1IE,Analog watchdog 1 interrupt enable" "0: Analog watchdog 1 interrupt disabled,1: Analog watchdog 1 interrupt enabled" newline bitfld.long 0x4 6. "JEOSIE,End of injected sequence of conversions interrupt enable" "0: JEOS interrupt disabled,1: JEOS interrupt enabled. An interrupt is.." bitfld.long 0x4 5. "JEOCIE,End of injected conversion interrupt enable" "0: JEOC interrupt disabled.,1: JEOC interrupt enabled. An interrupt is.." newline bitfld.long 0x4 4. "OVRIE,Overrun interrupt enable" "0: Overrun interrupt disabled,1: Overrun interrupt enabled. An interrupt is.." bitfld.long 0x4 3. "EOSIE,End of regular sequence of conversions interrupt enable" "0: EOS interrupt disabled,1: EOS interrupt enabled. An interrupt is generated.." newline bitfld.long 0x4 2. "EOCIE,End of regular conversion interrupt enable" "0: EOC interrupt disabled.,1: EOC interrupt enabled. An interrupt is generated.." bitfld.long 0x4 1. "EOSMPIE,End of sampling flag interrupt enable for regular conversions" "0: EOSMP interrupt disabled.,1: EOSMP interrupt enabled. An interrupt is.." newline bitfld.long 0x4 0. "ADRDYIE,ADC ready interrupt enable" "0: ADRDY interrupt disabled,1: ADRDY interrupt enabled. An interrupt is.." line.long 0x8 "ADC_CR,ADC control register" bitfld.long 0x8 31. "ADCAL,ADC calibration" "0: Calibration complete,1: Write 1 to calibrate the ADC. Read at 1 means.." bitfld.long 0x8 30. "ADCALDIF,Differential mode for calibration" "0: Writing ADCAL launches a calibration in..,1: Writing ADCAL launches a calibration in.." newline bitfld.long 0x8 29. "DEEPPWD,Deep-power-down enable" "0: ADC not in Deep-power down,1: ADC in Deep-power-down (default reset state)" bitfld.long 0x8 28. "ADVREGEN,ADC voltage regulator enable" "0: ADC Voltage regulator disabled,1: ADC Voltage regulator enabled." newline bitfld.long 0x8 5. "JADSTP,ADC stop of injected conversion command" "0: No ADC stop injected conversion command ongoing,1: Write 1 to stop injected conversions ongoing." bitfld.long 0x8 4. "ADSTP,ADC stop of regular conversion command" "0: No ADC stop regular conversion command ongoing,1: Write 1 to stop regular conversions ongoing." newline bitfld.long 0x8 3. "JADSTART,ADC start of injected conversion" "0: No ADC injected conversion is ongoing.,1: Write 1 to start injected conversions. Read 1.." bitfld.long 0x8 2. "ADSTART,ADC start of regular conversion" "0: No ADC regular conversion is ongoing.,1: Write 1 to start regular conversions. Read 1.." newline bitfld.long 0x8 1. "ADDIS,ADC disable command" "0: no ADDIS command ongoing,1: Write 1 to disable the ADC. Read 1 means that an.." bitfld.long 0x8 0. "ADEN,ADC enable control" "0: ADC is disabled (OFF state),1: Write 1 to enable the ADC." line.long 0xC "ADC_CFGR,ADC configuration register" bitfld.long 0xC 31. "JQDIS,Injected Queue disable" "0: Injected Queue enabled,1: Injected Queue disabled" hexmask.long.byte 0xC 26.--30. 1. "AWD1CH,Analog watchdog 1 channel selection" newline bitfld.long 0xC 25. "JAUTO,Automatic injected group conversion" "0: Automatic injected group conversion disabled,1: Automatic injected group conversion enabled" bitfld.long 0xC 24. "JAWD1EN,Analog watchdog 1 enable on injected channels" "0: Analog watchdog 1 disabled on injected channels,1: Analog watchdog 1 enabled on injected channels" newline bitfld.long 0xC 23. "AWD1EN,Analog watchdog 1 enable on regular channels" "0: Analog watchdog 1 disabled on regular channels,1: Analog watchdog 1 enabled on regular channels" bitfld.long 0xC 22. "AWD1SGL,Enable the watchdog 1 on a single channel or on all channels" "0: Analog watchdog 1 enabled on all channels,1: Analog watchdog 1 enabled on a single channel" newline bitfld.long 0xC 21. "JQM,JSQR queue mode" "0: JSQR mode 0: The Queue is never empty and..,1: JSQR mode 1: The Queue can be empty and when.." bitfld.long 0xC 20. "JDISCEN,Discontinuous mode on injected channels" "0: Discontinuous mode on injected channels disabled,1: Discontinuous mode on injected channels enabled" newline bitfld.long 0xC 17.--19. "DISCNUM,Discontinuous mode channel count" "0: 1 channel,1: 2 channels,?,?,?,?,?,7: 8 channels" bitfld.long 0xC 16. "DISCEN,Discontinuous mode for regular channels" "0: Discontinuous mode for regular channels disabled,1: Discontinuous mode for regular channels enabled" newline bitfld.long 0xC 15. "ALIGN,Data alignment" "0: Right alignment,1: Left alignment" bitfld.long 0xC 14. "AUTDLY,Delayed conversion mode" "0: Auto-delayed conversion mode off,1: Auto-delayed conversion mode on" newline bitfld.long 0xC 13. "CONT,Single / Continuous conversion mode for regular conversions" "0: Single conversion mode,1: Continuous conversion mode" bitfld.long 0xC 12. "OVRMOD,Overrun mode" "0: ADC_DR register is preserved with the old data..,1: ADC_DR register is overwritten with the last.." newline bitfld.long 0xC 10.--11. "EXTEN,External trigger enable and polarity selection for regular channels" "0,1,2,3" bitfld.long 0xC 9. "EXTSEL4,External trigger selection for regular group" "0,1" newline bitfld.long 0xC 8. "EXTSEL3,External trigger selection for regular group" "0,1" bitfld.long 0xC 7. "EXTSEL2,External trigger selection for regular group" "0,1" newline bitfld.long 0xC 6. "EXTSEL1,External trigger selection for regular group" "0,1" bitfld.long 0xC 5. "EXTSEL0,External trigger selection for regular group" "0,1" newline bitfld.long 0xC 3.--4. "RES,Data resolution" "0: 12-bit,1: 10-bit,2: 8-bit,3: 6-bit" bitfld.long 0xC 2. "DFSDMCFG,DFSDM mode configuration" "0: DFSDM mode disabled,1: DFSDM mode enabled" newline bitfld.long 0xC 1. "DMACFG,Direct memory access configuration" "0: DMA One Shot mode selected,1: DMA Circular mode selected" bitfld.long 0xC 0. "DMAEN,Direct memory access enable" "0: DMA disabled,1: DMA enabled" line.long 0x10 "ADC_CFGR2,ADC configuration register 2" bitfld.long 0x10 27. "SMPTRIG,Sampling time control trigger mode" "0: Sampling time control trigger mode disabled,1: Sampling time control trigger mode enabled" bitfld.long 0x10 26. "BULB,Bulb sampling mode" "0: Bulb sampling mode disabled,1: Bulb sampling mode enabled. The sampling period.." newline bitfld.long 0x10 25. "SWTRIG,Software trigger bit for sampling time control trigger mode" "0: Software trigger starts the conversion for..,1: Software trigger starts the sampling for.." bitfld.long 0x10 10. "ROVSM,Regular Oversampling mode" "0: Continued mode: When injected conversions are..,1: Resumed mode: When injected conversions are.." newline bitfld.long 0x10 9. "TROVS,Triggered Regular Oversampling" "0: All oversampled conversions for a channel are..,1: Each oversampled conversion for a channel needs.." hexmask.long.byte 0x10 5.--8. 1. "OVSS,Oversampling shift" newline bitfld.long 0x10 2.--4. "OVSR,Oversampling ratio" "0: 2x,1: 4x,2: 8x,3: 16x,4: 32x,5: 64x,6: 128x,7: 256x" bitfld.long 0x10 1. "JOVSE,Injected Oversampling Enable" "0: Injected Oversampling disabled,1: Injected Oversampling enabled" newline bitfld.long 0x10 0. "ROVSE,Regular Oversampling Enable" "0: Regular Oversampling disabled,1: Regular Oversampling enabled" line.long 0x14 "ADC_SMPR1,ADC sample time register 1" bitfld.long 0x14 31. "SMPPLUS,Addition of one clock cycle to the sampling time." "0: The sampling time remains set to 2.5 ADC clock..,1: 2.5 ADC clock cycle sampling time becomes 3.5.." bitfld.long 0x14 27.--29. "SMP9,Channel x sampling time selection" "0: 2.5 ADC clock cycles,1: 6.5 ADC clock cycles,2: 12.5 ADC clock cycles,3: 24.5 ADC clock cycles,4: 47.5 ADC clock cycles,5: 92.5 ADC clock cycles,6: 247.5 ADC clock cycles,7: 640.5 ADC clock cycles" newline bitfld.long 0x14 24.--26. "SMP8,Channel x sampling time selection" "0: 2.5 ADC clock cycles,1: 6.5 ADC clock cycles,2: 12.5 ADC clock cycles,3: 24.5 ADC clock cycles,4: 47.5 ADC clock cycles,5: 92.5 ADC clock cycles,6: 247.5 ADC clock cycles,7: 640.5 ADC clock cycles" bitfld.long 0x14 21.--23. "SMP7,Channel x sampling time selection" "0: 2.5 ADC clock cycles,1: 6.5 ADC clock cycles,2: 12.5 ADC clock cycles,3: 24.5 ADC clock cycles,4: 47.5 ADC clock cycles,5: 92.5 ADC clock cycles,6: 247.5 ADC clock cycles,7: 640.5 ADC clock cycles" newline bitfld.long 0x14 18.--20. "SMP6,Channel x sampling time selection" "0: 2.5 ADC clock cycles,1: 6.5 ADC clock cycles,2: 12.5 ADC clock cycles,3: 24.5 ADC clock cycles,4: 47.5 ADC clock cycles,5: 92.5 ADC clock cycles,6: 247.5 ADC clock cycles,7: 640.5 ADC clock cycles" bitfld.long 0x14 15.--17. "SMP5,Channel x sampling time selection" "0: 2.5 ADC clock cycles,1: 6.5 ADC clock cycles,2: 12.5 ADC clock cycles,3: 24.5 ADC clock cycles,4: 47.5 ADC clock cycles,5: 92.5 ADC clock cycles,6: 247.5 ADC clock cycles,7: 640.5 ADC clock cycles" newline bitfld.long 0x14 12.--14. "SMP4,Channel x sampling time selection" "0: 2.5 ADC clock cycles,1: 6.5 ADC clock cycles,2: 12.5 ADC clock cycles,3: 24.5 ADC clock cycles,4: 47.5 ADC clock cycles,5: 92.5 ADC clock cycles,6: 247.5 ADC clock cycles,7: 640.5 ADC clock cycles" bitfld.long 0x14 9.--11. "SMP3,Channel x sampling time selection" "0: 2.5 ADC clock cycles,1: 6.5 ADC clock cycles,2: 12.5 ADC clock cycles,3: 24.5 ADC clock cycles,4: 47.5 ADC clock cycles,5: 92.5 ADC clock cycles,6: 247.5 ADC clock cycles,7: 640.5 ADC clock cycles" newline bitfld.long 0x14 6.--8. "SMP2,Channel x sampling time selection" "0: 2.5 ADC clock cycles,1: 6.5 ADC clock cycles,2: 12.5 ADC clock cycles,3: 24.5 ADC clock cycles,4: 47.5 ADC clock cycles,5: 92.5 ADC clock cycles,6: 247.5 ADC clock cycles,7: 640.5 ADC clock cycles" bitfld.long 0x14 3.--5. "SMP1,Channel x sampling time selection" "0: 2.5 ADC clock cycles,1: 6.5 ADC clock cycles,2: 12.5 ADC clock cycles,3: 24.5 ADC clock cycles,4: 47.5 ADC clock cycles,5: 92.5 ADC clock cycles,6: 247.5 ADC clock cycles,7: 640.5 ADC clock cycles" newline bitfld.long 0x14 0.--2. "SMP0,Channel x sampling time selection" "0: 2.5 ADC clock cycles,1: 6.5 ADC clock cycles,2: 12.5 ADC clock cycles,3: 24.5 ADC clock cycles,4: 47.5 ADC clock cycles,5: 92.5 ADC clock cycles,6: 247.5 ADC clock cycles,7: 640.5 ADC clock cycles" line.long 0x18 "ADC_SMPR2,ADC sample time register 2" bitfld.long 0x18 24.--26. "SMP18,Channel x sampling time selection" "0: 2.5 ADC clock cycles,1: 6.5 ADC clock cycles,2: 12.5 ADC clock cycles,3: 24.5 ADC clock cycles,4: 47.5 ADC clock cycles,5: 92.5 ADC clock cycles,6: 247.5 ADC clock cycles,7: 640.5 ADC clock cycles" bitfld.long 0x18 21.--23. "SMP17,Channel x sampling time selection" "0: 2.5 ADC clock cycles,1: 6.5 ADC clock cycles,2: 12.5 ADC clock cycles,3: 24.5 ADC clock cycles,4: 47.5 ADC clock cycles,5: 92.5 ADC clock cycles,6: 247.5 ADC clock cycles,7: 640.5 ADC clock cycles" newline bitfld.long 0x18 18.--20. "SMP16,Channel x sampling time selection" "0: 2.5 ADC clock cycles,1: 6.5 ADC clock cycles,2: 12.5 ADC clock cycles,3: 24.5 ADC clock cycles,4: 47.5 ADC clock cycles,5: 92.5 ADC clock cycles,6: 247.5 ADC clock cycles,7: 640.5 ADC clock cycles" bitfld.long 0x18 15.--17. "SMP15,Channel x sampling time selection" "0: 2.5 ADC clock cycles,1: 6.5 ADC clock cycles,2: 12.5 ADC clock cycles,3: 24.5 ADC clock cycles,4: 47.5 ADC clock cycles,5: 92.5 ADC clock cycles,6: 247.5 ADC clock cycles,7: 640.5 ADC clock cycles" newline bitfld.long 0x18 12.--14. "SMP14,Channel x sampling time selection" "0: 2.5 ADC clock cycles,1: 6.5 ADC clock cycles,2: 12.5 ADC clock cycles,3: 24.5 ADC clock cycles,4: 47.5 ADC clock cycles,5: 92.5 ADC clock cycles,6: 247.5 ADC clock cycles,7: 640.5 ADC clock cycles" bitfld.long 0x18 9.--11. "SMP13,Channel x sampling time selection" "0: 2.5 ADC clock cycles,1: 6.5 ADC clock cycles,2: 12.5 ADC clock cycles,3: 24.5 ADC clock cycles,4: 47.5 ADC clock cycles,5: 92.5 ADC clock cycles,6: 247.5 ADC clock cycles,7: 640.5 ADC clock cycles" newline bitfld.long 0x18 6.--8. "SMP12,Channel x sampling time selection" "0: 2.5 ADC clock cycles,1: 6.5 ADC clock cycles,2: 12.5 ADC clock cycles,3: 24.5 ADC clock cycles,4: 47.5 ADC clock cycles,5: 92.5 ADC clock cycles,6: 247.5 ADC clock cycles,7: 640.5 ADC clock cycles" bitfld.long 0x18 3.--5. "SMP11,Channel x sampling time selection" "0: 2.5 ADC clock cycles,1: 6.5 ADC clock cycles,2: 12.5 ADC clock cycles,3: 24.5 ADC clock cycles,4: 47.5 ADC clock cycles,5: 92.5 ADC clock cycles,6: 247.5 ADC clock cycles,7: 640.5 ADC clock cycles" newline bitfld.long 0x18 0.--2. "SMP10,Channel x sampling time selection" "0: 2.5 ADC clock cycles,1: 6.5 ADC clock cycles,2: 12.5 ADC clock cycles,3: 24.5 ADC clock cycles,4: 47.5 ADC clock cycles,5: 92.5 ADC clock cycles,6: 247.5 ADC clock cycles,7: 640.5 ADC clock cycles" group.long 0x20++0xB line.long 0x0 "ADC_TR1,ADC watchdog threshold register 1" hexmask.long.word 0x0 16.--27. 1. "HT1,Analog watchdog 1 higher threshold" bitfld.long 0x0 12.--14. "AWDFILT,Analog watchdog filtering parameter" "0: No filtering,1: two consecutive detection generates an AWDx flag..,?,?,?,?,?,7: Eight consecutive detection generates an AWDx.." newline hexmask.long.word 0x0 0.--11. 1. "LT1,Analog watchdog 1 lower threshold" line.long 0x4 "ADC_TR2,ADC watchdog threshold register 2" hexmask.long.byte 0x4 16.--23. 1. "HT2,Analog watchdog 2 higher threshold" hexmask.long.byte 0x4 0.--7. 1. "LT2,Analog watchdog 2 lower threshold" line.long 0x8 "ADC_TR3,ADC watchdog threshold register 3" hexmask.long.byte 0x8 16.--23. 1. "HT3,Analog watchdog 3 higher threshold" hexmask.long.byte 0x8 0.--7. 1. "LT3,Analog watchdog 3 lower threshold" group.long 0x30++0xF line.long 0x0 "ADC_SQR1,ADC regular sequence register 1" hexmask.long.byte 0x0 24.--28. 1. "SQ4,4th conversion in regular sequence" hexmask.long.byte 0x0 18.--22. 1. "SQ3,3rd conversion in regular sequence" newline hexmask.long.byte 0x0 12.--16. 1. "SQ2,2nd conversion in regular sequence" hexmask.long.byte 0x0 6.--10. 1. "SQ1,1st conversion in regular sequence" newline hexmask.long.byte 0x0 0.--3. 1. "L,Regular channel sequence length" line.long 0x4 "ADC_SQR2,ADC regular sequence register 2" hexmask.long.byte 0x4 24.--28. 1. "SQ9,9th conversion in regular sequence" hexmask.long.byte 0x4 18.--22. 1. "SQ8,8th conversion in regular sequence" newline hexmask.long.byte 0x4 12.--16. 1. "SQ7,7th conversion in regular sequence" hexmask.long.byte 0x4 6.--10. 1. "SQ6,6th conversion in regular sequence" newline hexmask.long.byte 0x4 0.--4. 1. "SQ5,5th conversion in regular sequence" line.long 0x8 "ADC_SQR3,ADC regular sequence register 3" hexmask.long.byte 0x8 24.--28. 1. "SQ14,14th conversion in regular sequence" hexmask.long.byte 0x8 18.--22. 1. "SQ13,13th conversion in regular sequence" newline hexmask.long.byte 0x8 12.--16. 1. "SQ12,12th conversion in regular sequence" hexmask.long.byte 0x8 6.--10. 1. "SQ11,11th conversion in regular sequence" newline hexmask.long.byte 0x8 0.--4. 1. "SQ10,10th conversion in regular sequence" line.long 0xC "ADC_SQR4,ADC regular sequence register 4" hexmask.long.byte 0xC 6.--10. 1. "SQ16,16th conversion in regular sequence" hexmask.long.byte 0xC 0.--4. 1. "SQ15,15th conversion in regular sequence" rgroup.long 0x40++0x3 line.long 0x0 "ADC_DR,ADC regular data register" hexmask.long.word 0x0 0.--15. 1. "RDATA,Regular data converted" group.long 0x4C++0x3 line.long 0x0 "ADC_JSQR,ADC injected sequence register" hexmask.long.byte 0x0 27.--31. 1. "JSQ4,4th conversion in the injected sequence" hexmask.long.byte 0x0 21.--25. 1. "JSQ3,3rd conversion in the injected sequence" newline hexmask.long.byte 0x0 15.--19. 1. "JSQ2,2nd conversion in the injected sequence" hexmask.long.byte 0x0 9.--13. 1. "JSQ1,1st conversion in the injected sequence" newline bitfld.long 0x0 7.--8. "JEXTEN,External trigger enable and polarity selection for injected channels" "0: If JQDIS = 0 (queue enabled) hardware and..,1: Hardware trigger detection on the rising edge,2: Hardware trigger detection on the falling edge,3: Hardware trigger detection on both the rising.." hexmask.long.byte 0x0 2.--6. 1. "JEXTSEL,External Trigger Selection for injected group" newline bitfld.long 0x0 0.--1. "JL,Injected channel sequence length" "0: 1 conversion,1: 2 conversions,2: 3 conversions,3: 4 conversions" group.long 0x60++0xF line.long 0x0 "ADC_OFR1,ADC offset 1 register" bitfld.long 0x0 31. "OFFSET_EN,Offset y enable" "0,1" hexmask.long.byte 0x0 26.--30. 1. "OFFSET_CH,Channel selection for the data offset y" newline bitfld.long 0x0 25. "SATEN,Saturation enable" "0: No saturation control offset result can be signed,1: Saturation enabled offset result unsigned and.." bitfld.long 0x0 24. "OFFSETPOS,Positive offset" "0: Negative offset,1: Positive offset" newline hexmask.long.word 0x0 0.--11. 1. "OFFSET,Data offset y for the channel programmed into bits OFFSET_CH[4:0]" line.long 0x4 "ADC_OFR2,ADC offset 2 register" bitfld.long 0x4 31. "OFFSET_EN,Offset y enable" "0,1" hexmask.long.byte 0x4 26.--30. 1. "OFFSET_CH,Channel selection for the data offset y" newline bitfld.long 0x4 25. "SATEN,Saturation enable" "0: No saturation control offset result can be signed,1: Saturation enabled offset result unsigned and.." bitfld.long 0x4 24. "OFFSETPOS,Positive offset" "0: Negative offset,1: Positive offset" newline hexmask.long.word 0x4 0.--11. 1. "OFFSET,Data offset y for the channel programmed into bits OFFSET_CH[4:0]" line.long 0x8 "ADC_OFR3,ADC offset 3 register" bitfld.long 0x8 31. "OFFSET_EN,Offset y enable" "0,1" hexmask.long.byte 0x8 26.--30. 1. "OFFSET_CH,Channel selection for the data offset y" newline bitfld.long 0x8 25. "SATEN,Saturation enable" "0: No saturation control offset result can be signed,1: Saturation enabled offset result unsigned and.." bitfld.long 0x8 24. "OFFSETPOS,Positive offset" "0: Negative offset,1: Positive offset" newline hexmask.long.word 0x8 0.--11. 1. "OFFSET,Data offset y for the channel programmed into bits OFFSET_CH[4:0]" line.long 0xC "ADC_OFR4,ADC offset 4 register" bitfld.long 0xC 31. "OFFSET_EN,Offset y enable" "0,1" hexmask.long.byte 0xC 26.--30. 1. "OFFSET_CH,Channel selection for the data offset y" newline bitfld.long 0xC 25. "SATEN,Saturation enable" "0: No saturation control offset result can be signed,1: Saturation enabled offset result unsigned and.." bitfld.long 0xC 24. "OFFSETPOS,Positive offset" "0: Negative offset,1: Positive offset" newline hexmask.long.word 0xC 0.--11. 1. "OFFSET,Data offset y for the channel programmed into bits OFFSET_CH[4:0]" rgroup.long 0x80++0xF line.long 0x0 "ADC_JDR1,ADC injected channel 1 data register" hexmask.long.word 0x0 0.--15. 1. "JDATA,Injected data" line.long 0x4 "ADC_JDR2,ADC injected channel 2 data register" hexmask.long.word 0x4 0.--15. 1. "JDATA,Injected data" line.long 0x8 "ADC_JDR3,ADC injected channel 3 data register" hexmask.long.word 0x8 0.--15. 1. "JDATA,Injected data" line.long 0xC "ADC_JDR4,ADC injected channel 4 data register" hexmask.long.word 0xC 0.--15. 1. "JDATA,Injected data" group.long 0xA0++0x7 line.long 0x0 "ADC_AWD2CR,ADC Analog Watchdog 2 Configuration Register" hexmask.long.tbyte 0x0 0.--18. 1. "AWD2CH,Analog watchdog 2 channel selection" line.long 0x4 "ADC_AWD3CR,ADC Analog Watchdog 3 Configuration Register" hexmask.long.tbyte 0x4 0.--18. 1. "AWD3CH,Analog watchdog 3 channel selection" group.long 0xB0++0x7 line.long 0x0 "ADC_DIFSEL,ADC Differential mode Selection Register" hexmask.long.tbyte 0x0 0.--18. 1. "DIFSEL,Differential mode for channels 18 to 0." line.long 0x4 "ADC_CALFACT,ADC Calibration Factors" hexmask.long.byte 0x4 16.--22. 1. "CALFACT_D,Calibration Factors in differential mode" hexmask.long.byte 0x4 0.--6. 1. "CALFACT_S,Calibration Factors In Single-ended mode" group.long 0xC8++0x3 line.long 0x0 "ADC_OR,ADC option register" bitfld.long 0x0 2. "OP2,VDDQ_DDR channel enable" "0: VDDQ_DDR channel disabled,1: VDDQ_DDR channel enabled" bitfld.long 0x0 1. "OP1,VDDCPU channel enable" "0: VDDCPU channel disabled,1: VDDCPU channel enabled" newline bitfld.long 0x0 0. "OP0,VDDCORE channel enable" "0: VDDCORE channel disabled,1: VDDCORE channel enabled" rgroup.long 0x300++0x3 line.long 0x0 "ADC_CSR,ADC common status register" bitfld.long 0x0 10. "JQOVF_MST,Injected Context Queue Overflow flag of the master ADC" "0,1" bitfld.long 0x0 9. "AWD3_MST,Analog watchdog 3 flag of the master ADC" "0,1" newline bitfld.long 0x0 8. "AWD2_MST,Analog watchdog 2 flag of the master ADC" "0,1" bitfld.long 0x0 7. "AWD1_MST,Analog watchdog 1 flag of the master ADC" "0,1" newline bitfld.long 0x0 6. "JEOS_MST,End of injected sequence flag of the master ADC" "0,1" bitfld.long 0x0 5. "JEOC_MST,End of injected conversion flag of the master ADC" "0,1" newline bitfld.long 0x0 4. "OVR_MST,Overrun flag of the master ADC" "0,1" bitfld.long 0x0 3. "EOS_MST,End of regular sequence flag of the master ADC" "0,1" newline bitfld.long 0x0 2. "EOC_MST,End of regular conversion of the master ADC" "0,1" bitfld.long 0x0 1. "EOSMP_MST,End of Sampling phase flag of the master ADC" "0,1" newline bitfld.long 0x0 0. "ADRDY_MST,Master ADC ready" "0,1" group.long 0x308++0x3 line.long 0x0 "ADC_CCR,ADC common control register" bitfld.long 0x0 24. "VBATEN,VBAT enable" "0: VBAT channel disabled,1: VBAT channel enabled" bitfld.long 0x0 23. "TSEN,VSENSE enable" "0: Temperature sensor channel disabled,1: Temperature sensor channel enabled" newline bitfld.long 0x0 22. "VREFEN,VREFINT enable" "0: VREFINT channel disabled,1: VREFINT channel enabled" hexmask.long.byte 0x0 18.--21. 1. "PRESC,ADC prescaler" newline bitfld.long 0x0 16.--17. "CKMODE,ADC clock mode" "0: adc_ker_ck (x = 1/2) (Asynchronous clock mode)..,1: adc_hclk/1 (Synchronous clock mode). This..,2: adc_hclk/2 (Synchronous clock mode),3: adc_hclk/4 (Synchronous clock mode)" rgroup.long 0x3F0++0xF line.long 0x0 "ADC_HWCFGR0,ADC hardware configuration register" hexmask.long.byte 0x0 12.--15. 1. "IDLEVALUE,Idle value for non-selected channels" hexmask.long.byte 0x0 8.--11. 1. "OPBITS,Number of option bits" newline hexmask.long.byte 0x0 4.--7. 1. "MULPIPE,Number of pipeline stages" hexmask.long.byte 0x0 0.--3. 1. "ADCNUM,Number of ADCs implemented" line.long 0x4 "ADC_VERR,ADC version register" hexmask.long.byte 0x4 4.--7. 1. "MAJREV,Major revision" hexmask.long.byte 0x4 0.--3. 1. "MINREV,Minor revision" line.long 0x8 "ADC_IPDR,ADC identification register" hexmask.long 0x8 0.--31. 1. "ID,Peripheral identifier" line.long 0xC "ADC_SIDR,ADC size identification register" hexmask.long 0xC 0.--31. 1. "SID,Size Identification" tree.end endif sif (cpuis("STM32MP151*")||cpuis("STM32MP153*")||cpuis("STM32MP157*")) tree "ADC2" base ad:0x48003100 group.long 0x0++0x27 line.long 0x0 "ADC_ISR,ADC interrupt and status register" bitfld.long 0x0 10. "JQOVF,JQOVF" "0,1" bitfld.long 0x0 9. "AWD3,AWD3" "0,1" bitfld.long 0x0 8. "AWD2,AWD2" "0,1" bitfld.long 0x0 7. "AWD1,AWD1" "0,1" bitfld.long 0x0 6. "JEOS,JEOS" "0,1" bitfld.long 0x0 5. "JEOC,JEOC" "0,1" bitfld.long 0x0 4. "OVR,OVR" "0,1" newline bitfld.long 0x0 3. "EOS,EOS" "0,1" bitfld.long 0x0 2. "EOC,EOC" "0,1" bitfld.long 0x0 1. "EOSMP,EOSMP" "0,1" bitfld.long 0x0 0. "ADRDY,ADRDY" "0,1" line.long 0x4 "ADC_IER,ADC interrupt enable register" bitfld.long 0x4 10. "JQOVFIE,JQOVFIE" "0,1" bitfld.long 0x4 9. "AWD3IE,AWD3IE" "0,1" bitfld.long 0x4 8. "AWD2IE,AWD2IE" "0,1" bitfld.long 0x4 7. "AWD1IE,AWD1IE" "0,1" bitfld.long 0x4 6. "JEOSIE,JEOSIE" "0,1" bitfld.long 0x4 5. "JEOCIE,JEOCIE" "0,1" bitfld.long 0x4 4. "OVRIE,OVRIE" "0,1" newline bitfld.long 0x4 3. "EOSIE,EOSIE" "0,1" bitfld.long 0x4 2. "EOCIE,EOCIE" "0,1" bitfld.long 0x4 1. "EOSMPIE,EOSMPIE" "0,1" bitfld.long 0x4 0. "ADRDYIE,ADRDYIE" "0,1" line.long 0x8 "ADC_CR,ADC control register" bitfld.long 0x8 31. "ADCAL,ADCAL" "0,1" bitfld.long 0x8 30. "ADCALDIF,ADCALDIF" "0,1" bitfld.long 0x8 29. "DEEPPWD,DEEPPWD" "0,1" bitfld.long 0x8 28. "ADVREGEN,ADVREGEN" "0,1" bitfld.long 0x8 27. "LINCALRDYW6,LINCALRDYW6" "0,1" bitfld.long 0x8 26. "LINCALRDYW5,LINCALRDYW5" "0,1" bitfld.long 0x8 25. "LINCALRDYW4,LINCALRDYW4" "0,1" newline bitfld.long 0x8 24. "LINCALRDYW3,LINCALRDYW3" "0,1" bitfld.long 0x8 23. "LINCALRDYW2,LINCALRDYW2" "0,1" bitfld.long 0x8 22. "LINCALRDYW1,LINCALRDYW1" "0,1" bitfld.long 0x8 16. "ADCALLIN,ADCALLIN" "0,1" bitfld.long 0x8 8. "BOOST,BOOST" "0,1" bitfld.long 0x8 5. "JADSTP,JADSTP" "0,1" bitfld.long 0x8 4. "ADSTP,ADSTP" "0,1" newline bitfld.long 0x8 3. "JADSTART,JADSTART" "0,1" bitfld.long 0x8 2. "ADSTART,ADSTART" "0,1" bitfld.long 0x8 1. "ADDIS,ADDIS" "0,1" bitfld.long 0x8 0. "ADEN,ADEN" "0,1" line.long 0xC "ADC_CFGR,ADC configuration register" bitfld.long 0xC 31. "JQDIS,JQDIS" "0,1" hexmask.long.byte 0xC 26.--30. 1. "AWD1CH,AWD1CH" bitfld.long 0xC 25. "JAUTO,JAUTO" "0,1" bitfld.long 0xC 24. "JAWD1EN,JAWD1EN" "0,1" bitfld.long 0xC 23. "AWD1EN,AWD1EN" "0,1" bitfld.long 0xC 22. "AWD1SGL,AWD1SGL" "0,1" bitfld.long 0xC 21. "JQM,JQM" "0,1" newline bitfld.long 0xC 20. "JDISCEN,JDISCEN" "0,1" bitfld.long 0xC 17.--19. "DISCNUM,DISCNUM" "0,1,2,3,4,5,6,7" bitfld.long 0xC 16. "DISCEN,DISCEN" "0,1" bitfld.long 0xC 14. "AUTDLY,AUTDLY" "0,1" bitfld.long 0xC 13. "CONT,CONT" "0,1" bitfld.long 0xC 12. "OVRMOD,OVRMOD" "0,1" bitfld.long 0xC 10.--11. "EXTEN,EXTEN" "0,1,2,3" newline hexmask.long.byte 0xC 5.--9. 1. "EXTSEL,EXTSEL" bitfld.long 0xC 2.--4. "RES,RES" "0,1,2,3,4,5,6,7" bitfld.long 0xC 0.--1. "DMNGT,DMNGT" "0,1,2,3" line.long 0x10 "ADC_CFGR2,ADC configuration register 2" hexmask.long.byte 0x10 28.--31. 1. "LSHIFT,LSHIFT" hexmask.long.word 0x10 16.--25. 1. "OSVR,OSVR" bitfld.long 0x10 14. "RSHIFT4,RSHIFT4" "0,1" bitfld.long 0x10 13. "RSHIFT3,RSHIFT3" "0,1" bitfld.long 0x10 12. "RSHIFT2,RSHIFT2" "0,1" bitfld.long 0x10 11. "RSHIFT1,RSHIFT1" "0,1" bitfld.long 0x10 10. "ROVSM,ROVSM" "0,1" newline bitfld.long 0x10 9. "TROVS,TROVS" "0,1" hexmask.long.byte 0x10 5.--8. 1. "OVSS,OVSS" bitfld.long 0x10 1. "JOVSE,JOVSE" "0,1" bitfld.long 0x10 0. "ROVSE,ROVSE" "0,1" line.long 0x14 "ADC_SMPR1,ADC sample time register 1" bitfld.long 0x14 27.--29. "SMP9,SMP9" "0,1,2,3,4,5,6,7" bitfld.long 0x14 24.--26. "SMP8,SMP8" "0,1,2,3,4,5,6,7" bitfld.long 0x14 21.--23. "SMP7,SMP7" "0,1,2,3,4,5,6,7" bitfld.long 0x14 18.--20. "SMP6,SMP6" "0,1,2,3,4,5,6,7" bitfld.long 0x14 15.--17. "SMP5,SMP5" "0,1,2,3,4,5,6,7" bitfld.long 0x14 12.--14. "SMP4,SMP4" "0,1,2,3,4,5,6,7" bitfld.long 0x14 9.--11. "SMP3,SMP3" "0,1,2,3,4,5,6,7" newline bitfld.long 0x14 6.--8. "SMP2,SMP2" "0,1,2,3,4,5,6,7" bitfld.long 0x14 3.--5. "SMP1,SMP1" "0,1,2,3,4,5,6,7" bitfld.long 0x14 0.--2. "SMP0,SMP0" "0,1,2,3,4,5,6,7" line.long 0x18 "ADC_SMPR2,ADC sample time register 2" bitfld.long 0x18 27.--29. "SMP19,SMP19" "0,1,2,3,4,5,6,7" bitfld.long 0x18 24.--26. "SMP18,SMP18" "0,1,2,3,4,5,6,7" bitfld.long 0x18 21.--23. "SMP17,SMP17" "0,1,2,3,4,5,6,7" bitfld.long 0x18 18.--20. "SMP16,SMP16" "0,1,2,3,4,5,6,7" bitfld.long 0x18 15.--17. "SMP15,SMP15" "0,1,2,3,4,5,6,7" bitfld.long 0x18 12.--14. "SMP14,SMP14" "0,1,2,3,4,5,6,7" bitfld.long 0x18 9.--11. "SMP13,SMP13" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 6.--8. "SMP12,SMP12" "0,1,2,3,4,5,6,7" bitfld.long 0x18 3.--5. "SMP11,SMP11" "0,1,2,3,4,5,6,7" bitfld.long 0x18 0.--2. "SMP10,SMP10" "0,1,2,3,4,5,6,7" line.long 0x1C "ADC_PCSEL,ADC channel preselection register" bitfld.long 0x1C 19. "PCSEL19,PCSEL19" "0,1" bitfld.long 0x1C 18. "PCSEL18,PCSEL18" "0,1" bitfld.long 0x1C 17. "PCSEL17,PCSEL17" "0,1" bitfld.long 0x1C 16. "PCSEL16,PCSEL16" "0,1" bitfld.long 0x1C 15. "PCSEL15,PCSEL15" "0,1" bitfld.long 0x1C 14. "PCSEL14,PCSEL14" "0,1" bitfld.long 0x1C 13. "PCSEL13,PCSEL13" "0,1" newline bitfld.long 0x1C 12. "PCSEL12,PCSEL12" "0,1" bitfld.long 0x1C 11. "PCSEL11,PCSEL11" "0,1" bitfld.long 0x1C 10. "PCSEL10,PCSEL10" "0,1" bitfld.long 0x1C 9. "PCSEL9,PCSEL9" "0,1" bitfld.long 0x1C 8. "PCSEL8,PCSEL8" "0,1" bitfld.long 0x1C 7. "PCSEL7,PCSEL7" "0,1" bitfld.long 0x1C 6. "PCSEL6,PCSEL6" "0,1" newline bitfld.long 0x1C 5. "PCSEL5,PCSEL5" "0,1" bitfld.long 0x1C 4. "PCSEL4,PCSEL4" "0,1" bitfld.long 0x1C 3. "PCSEL3,PCSEL3" "0,1" bitfld.long 0x1C 2. "PCSEL2,PCSEL2" "0,1" bitfld.long 0x1C 1. "PCSEL1,PCSEL1" "0,1" bitfld.long 0x1C 0. "PCSEL0,PCSEL0" "0,1" line.long 0x20 "ADC_LTR1,ADC watchdog threshold register 1" hexmask.long 0x20 0.--25. 1. "LTR1,LTR1" line.long 0x24 "ADC_HTR1,ADC watchdog threshold register 1" hexmask.long 0x24 0.--25. 1. "HTR1,HTR1" group.long 0x30++0xF line.long 0x0 "ADC_SQR1,ADC regular sequence register 1" hexmask.long.byte 0x0 24.--28. 1. "SQ4,SQ4" hexmask.long.byte 0x0 18.--22. 1. "SQ3,SQ3" hexmask.long.byte 0x0 12.--16. 1. "SQ2,SQ2" hexmask.long.byte 0x0 6.--10. 1. "SQ1,SQ1" hexmask.long.byte 0x0 0.--3. 1. "L,L" line.long 0x4 "ADC_SQR2,ADC regular sequence register 2" hexmask.long.byte 0x4 24.--28. 1. "SQ9,SQ9" hexmask.long.byte 0x4 18.--22. 1. "SQ8,SQ8" hexmask.long.byte 0x4 12.--16. 1. "SQ7,SQ7" hexmask.long.byte 0x4 6.--10. 1. "SQ6,SQ6" hexmask.long.byte 0x4 0.--4. 1. "SQ5,SQ5" line.long 0x8 "ADC_SQR3,ADC regular sequence register 3" hexmask.long.byte 0x8 24.--28. 1. "SQ14,SQ14" hexmask.long.byte 0x8 18.--22. 1. "SQ13,SQ13" hexmask.long.byte 0x8 12.--16. 1. "SQ12,SQ12" hexmask.long.byte 0x8 6.--10. 1. "SQ11,SQ11" hexmask.long.byte 0x8 0.--4. 1. "SQ10,SQ10" line.long 0xC "ADC_SQR4,ADC regular sequence register 4" hexmask.long.byte 0xC 6.--10. 1. "SQ16,SQ16" hexmask.long.byte 0xC 0.--4. 1. "SQ15,SQ15" rgroup.long 0x40++0x3 line.long 0x0 "ADC_DR,ADC regular Data Register" hexmask.long 0x0 0.--31. 1. "RDATA,RDATA" group.long 0x4C++0x3 line.long 0x0 "ADC_JSQR,ADC injected sequence register" hexmask.long.byte 0x0 27.--31. 1. "JSQ4,JSQ4" hexmask.long.byte 0x0 21.--25. 1. "JSQ3,JSQ3" hexmask.long.byte 0x0 15.--19. 1. "JSQ2,JSQ2" hexmask.long.byte 0x0 9.--13. 1. "JSQ1,JSQ1" bitfld.long 0x0 7.--8. "JEXTEN,JEXTEN" "0,1,2,3" hexmask.long.byte 0x0 2.--6. 1. "JEXTSEL,JEXTSEL" bitfld.long 0x0 0.--1. "JL,JL" "0,1,2,3" group.long 0x60++0xF line.long 0x0 "ADC_OFR1,ADC offset register" bitfld.long 0x0 31. "SSATE,SSATE" "0,1" hexmask.long.byte 0x0 26.--30. 1. "OFFSET1_CH,OFFSET1_CH" hexmask.long 0x0 0.--25. 1. "OFFSET1,OFFSET1" line.long 0x4 "ADC_OFR2,ADC offset register" bitfld.long 0x4 31. "SSATE,SSATE" "0,1" hexmask.long.byte 0x4 26.--30. 1. "OFFSET2_CH,OFFSET2_CH" hexmask.long 0x4 0.--25. 1. "OFFSET2,OFFSET2" line.long 0x8 "ADC_OFR3,ADC offset register" bitfld.long 0x8 31. "SSATE,SSATE" "0,1" hexmask.long.byte 0x8 26.--30. 1. "OFFSET3_CH,OFFSET3_CH" hexmask.long 0x8 0.--25. 1. "OFFSET3,OFFSET3" line.long 0xC "ADC_OFR4,ADC offset register" bitfld.long 0xC 31. "SSATE,SSATE" "0,1" hexmask.long.byte 0xC 26.--30. 1. "OFFSET4_CH,OFFSET4_CH" hexmask.long 0xC 0.--25. 1. "OFFSET4,OFFSET4" rgroup.long 0x80++0xF line.long 0x0 "ADC_JDR1,ADC injected data register" hexmask.long 0x0 0.--31. 1. "JDATA,JDATA" line.long 0x4 "ADC_JDR2,ADC injected data register" hexmask.long 0x4 0.--31. 1. "JDATA,JDATA" line.long 0x8 "ADC_JDR3,ADC injected data register" hexmask.long 0x8 0.--31. 1. "JDATA,JDATA" line.long 0xC "ADC_JDR4,ADC injected data register" hexmask.long 0xC 0.--31. 1. "JDATA,JDATA" group.long 0xA0++0x7 line.long 0x0 "ADC_AWD2CR,ADC analog watchdog 2 configuration register" hexmask.long.tbyte 0x0 0.--19. 1. "AWD2CH,AWD2CH" line.long 0x4 "ADC_AWD3CR,ADC analog watchdog 3 configuration register" hexmask.long.tbyte 0x4 0.--19. 1. "AWD3CH,AWD3CH" group.long 0xB0++0x1B line.long 0x0 "ADC_LTR2,ADC watchdog lower threshold register 2" hexmask.long 0x0 0.--25. 1. "LTR2,LTR2" line.long 0x4 "ADC_HTR2,ADC watchdog higher threshold register 2" hexmask.long 0x4 0.--25. 1. "HTR2,HTR2" line.long 0x8 "ADC_LTR3,ADC watchdog lower threshold register 3" hexmask.long 0x8 0.--25. 1. "LTR3,LTR3" line.long 0xC "ADC_HTR3,ADC watchdog higher threshold register 3" hexmask.long 0xC 0.--25. 1. "HTR3,HTR3" line.long 0x10 "ADC_DIFSEL,ADC differential mode selection register" hexmask.long.tbyte 0x10 0.--19. 1. "DIFSEL,DIFSEL" line.long 0x14 "ADC_CALFACT,ADC calibration factors register" hexmask.long.word 0x14 16.--26. 1. "CALFACT_D,CALFACT_D" hexmask.long.word 0x14 0.--10. 1. "CALFACT_S,CALFACT_S" line.long 0x18 "ADC_CALFACT2,ADC calibration factor register 2" hexmask.long 0x18 0.--29. 1. "LINCALFACT,LINCALFACT" group.long 0xD0++0x3 line.long 0x0 "ADC2_OR,ADC2 option register" bitfld.long 0x0 0. "VDDCOREEN,VDDCOREEN" "0,1" tree.end endif sif (cpuis("STM32MP151*")||cpuis("STM32MP153*")||cpuis("STM32MP157*")) tree "ADC" base ad:0x48003000 group.long 0x0++0x27 line.long 0x0 "ADC_ISR,ADC interrupt and status register" bitfld.long 0x0 10. "JQOVF,JQOVF" "0,1" bitfld.long 0x0 9. "AWD3,AWD3" "0,1" bitfld.long 0x0 8. "AWD2,AWD2" "0,1" bitfld.long 0x0 7. "AWD1,AWD1" "0,1" bitfld.long 0x0 6. "JEOS,JEOS" "0,1" bitfld.long 0x0 5. "JEOC,JEOC" "0,1" bitfld.long 0x0 4. "OVR,OVR" "0,1" newline bitfld.long 0x0 3. "EOS,EOS" "0,1" bitfld.long 0x0 2. "EOC,EOC" "0,1" bitfld.long 0x0 1. "EOSMP,EOSMP" "0,1" bitfld.long 0x0 0. "ADRDY,ADRDY" "0,1" line.long 0x4 "ADC_IER,ADC interrupt enable register" bitfld.long 0x4 10. "JQOVFIE,JQOVFIE" "0,1" bitfld.long 0x4 9. "AWD3IE,AWD3IE" "0,1" bitfld.long 0x4 8. "AWD2IE,AWD2IE" "0,1" bitfld.long 0x4 7. "AWD1IE,AWD1IE" "0,1" bitfld.long 0x4 6. "JEOSIE,JEOSIE" "0,1" bitfld.long 0x4 5. "JEOCIE,JEOCIE" "0,1" bitfld.long 0x4 4. "OVRIE,OVRIE" "0,1" newline bitfld.long 0x4 3. "EOSIE,EOSIE" "0,1" bitfld.long 0x4 2. "EOCIE,EOCIE" "0,1" bitfld.long 0x4 1. "EOSMPIE,EOSMPIE" "0,1" bitfld.long 0x4 0. "ADRDYIE,ADRDYIE" "0,1" line.long 0x8 "ADC_CR,ADC control register" bitfld.long 0x8 31. "ADCAL,ADCAL" "0,1" bitfld.long 0x8 30. "ADCALDIF,ADCALDIF" "0,1" bitfld.long 0x8 29. "DEEPPWD,DEEPPWD" "0,1" bitfld.long 0x8 28. "ADVREGEN,ADVREGEN" "0,1" bitfld.long 0x8 27. "LINCALRDYW6,LINCALRDYW6" "0,1" bitfld.long 0x8 26. "LINCALRDYW5,LINCALRDYW5" "0,1" bitfld.long 0x8 25. "LINCALRDYW4,LINCALRDYW4" "0,1" newline bitfld.long 0x8 24. "LINCALRDYW3,LINCALRDYW3" "0,1" bitfld.long 0x8 23. "LINCALRDYW2,LINCALRDYW2" "0,1" bitfld.long 0x8 22. "LINCALRDYW1,LINCALRDYW1" "0,1" bitfld.long 0x8 16. "ADCALLIN,ADCALLIN" "0,1" bitfld.long 0x8 8. "BOOST,BOOST" "0,1" bitfld.long 0x8 5. "JADSTP,JADSTP" "0,1" bitfld.long 0x8 4. "ADSTP,ADSTP" "0,1" newline bitfld.long 0x8 3. "JADSTART,JADSTART" "0,1" bitfld.long 0x8 2. "ADSTART,ADSTART" "0,1" bitfld.long 0x8 1. "ADDIS,ADDIS" "0,1" bitfld.long 0x8 0. "ADEN,ADEN" "0,1" line.long 0xC "ADC_CFGR,ADC configuration register" bitfld.long 0xC 31. "JQDIS,JQDIS" "0,1" hexmask.long.byte 0xC 26.--30. 1. "AWD1CH,AWD1CH" bitfld.long 0xC 25. "JAUTO,JAUTO" "0,1" bitfld.long 0xC 24. "JAWD1EN,JAWD1EN" "0,1" bitfld.long 0xC 23. "AWD1EN,AWD1EN" "0,1" bitfld.long 0xC 22. "AWD1SGL,AWD1SGL" "0,1" bitfld.long 0xC 21. "JQM,JQM" "0,1" newline bitfld.long 0xC 20. "JDISCEN,JDISCEN" "0,1" bitfld.long 0xC 17.--19. "DISCNUM,DISCNUM" "0,1,2,3,4,5,6,7" bitfld.long 0xC 16. "DISCEN,DISCEN" "0,1" bitfld.long 0xC 14. "AUTDLY,AUTDLY" "0,1" bitfld.long 0xC 13. "CONT,CONT" "0,1" bitfld.long 0xC 12. "OVRMOD,OVRMOD" "0,1" bitfld.long 0xC 10.--11. "EXTEN,EXTEN" "0,1,2,3" newline hexmask.long.byte 0xC 5.--9. 1. "EXTSEL,EXTSEL" bitfld.long 0xC 2.--4. "RES,RES" "0,1,2,3,4,5,6,7" bitfld.long 0xC 0.--1. "DMNGT,DMNGT" "0,1,2,3" line.long 0x10 "ADC_CFGR2,ADC configuration register 2" hexmask.long.byte 0x10 28.--31. 1. "LSHIFT,LSHIFT" hexmask.long.word 0x10 16.--25. 1. "OSVR,OSVR" bitfld.long 0x10 14. "RSHIFT4,RSHIFT4" "0,1" bitfld.long 0x10 13. "RSHIFT3,RSHIFT3" "0,1" bitfld.long 0x10 12. "RSHIFT2,RSHIFT2" "0,1" bitfld.long 0x10 11. "RSHIFT1,RSHIFT1" "0,1" bitfld.long 0x10 10. "ROVSM,ROVSM" "0,1" newline bitfld.long 0x10 9. "TROVS,TROVS" "0,1" hexmask.long.byte 0x10 5.--8. 1. "OVSS,OVSS" bitfld.long 0x10 1. "JOVSE,JOVSE" "0,1" bitfld.long 0x10 0. "ROVSE,ROVSE" "0,1" line.long 0x14 "ADC_SMPR1,ADC sample time register 1" bitfld.long 0x14 27.--29. "SMP9,SMP9" "0,1,2,3,4,5,6,7" bitfld.long 0x14 24.--26. "SMP8,SMP8" "0,1,2,3,4,5,6,7" bitfld.long 0x14 21.--23. "SMP7,SMP7" "0,1,2,3,4,5,6,7" bitfld.long 0x14 18.--20. "SMP6,SMP6" "0,1,2,3,4,5,6,7" bitfld.long 0x14 15.--17. "SMP5,SMP5" "0,1,2,3,4,5,6,7" bitfld.long 0x14 12.--14. "SMP4,SMP4" "0,1,2,3,4,5,6,7" bitfld.long 0x14 9.--11. "SMP3,SMP3" "0,1,2,3,4,5,6,7" newline bitfld.long 0x14 6.--8. "SMP2,SMP2" "0,1,2,3,4,5,6,7" bitfld.long 0x14 3.--5. "SMP1,SMP1" "0,1,2,3,4,5,6,7" bitfld.long 0x14 0.--2. "SMP0,SMP0" "0,1,2,3,4,5,6,7" line.long 0x18 "ADC_SMPR2,ADC sample time register 2" bitfld.long 0x18 27.--29. "SMP19,SMP19" "0,1,2,3,4,5,6,7" bitfld.long 0x18 24.--26. "SMP18,SMP18" "0,1,2,3,4,5,6,7" bitfld.long 0x18 21.--23. "SMP17,SMP17" "0,1,2,3,4,5,6,7" bitfld.long 0x18 18.--20. "SMP16,SMP16" "0,1,2,3,4,5,6,7" bitfld.long 0x18 15.--17. "SMP15,SMP15" "0,1,2,3,4,5,6,7" bitfld.long 0x18 12.--14. "SMP14,SMP14" "0,1,2,3,4,5,6,7" bitfld.long 0x18 9.--11. "SMP13,SMP13" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 6.--8. "SMP12,SMP12" "0,1,2,3,4,5,6,7" bitfld.long 0x18 3.--5. "SMP11,SMP11" "0,1,2,3,4,5,6,7" bitfld.long 0x18 0.--2. "SMP10,SMP10" "0,1,2,3,4,5,6,7" line.long 0x1C "ADC_PCSEL,ADC channel preselection register" bitfld.long 0x1C 19. "PCSEL19,PCSEL19" "0,1" bitfld.long 0x1C 18. "PCSEL18,PCSEL18" "0,1" bitfld.long 0x1C 17. "PCSEL17,PCSEL17" "0,1" bitfld.long 0x1C 16. "PCSEL16,PCSEL16" "0,1" bitfld.long 0x1C 15. "PCSEL15,PCSEL15" "0,1" bitfld.long 0x1C 14. "PCSEL14,PCSEL14" "0,1" bitfld.long 0x1C 13. "PCSEL13,PCSEL13" "0,1" newline bitfld.long 0x1C 12. "PCSEL12,PCSEL12" "0,1" bitfld.long 0x1C 11. "PCSEL11,PCSEL11" "0,1" bitfld.long 0x1C 10. "PCSEL10,PCSEL10" "0,1" bitfld.long 0x1C 9. "PCSEL9,PCSEL9" "0,1" bitfld.long 0x1C 8. "PCSEL8,PCSEL8" "0,1" bitfld.long 0x1C 7. "PCSEL7,PCSEL7" "0,1" bitfld.long 0x1C 6. "PCSEL6,PCSEL6" "0,1" newline bitfld.long 0x1C 5. "PCSEL5,PCSEL5" "0,1" bitfld.long 0x1C 4. "PCSEL4,PCSEL4" "0,1" bitfld.long 0x1C 3. "PCSEL3,PCSEL3" "0,1" bitfld.long 0x1C 2. "PCSEL2,PCSEL2" "0,1" bitfld.long 0x1C 1. "PCSEL1,PCSEL1" "0,1" bitfld.long 0x1C 0. "PCSEL0,PCSEL0" "0,1" line.long 0x20 "ADC_LTR1,ADC watchdog threshold register 1" hexmask.long 0x20 0.--25. 1. "LTR1,LTR1" line.long 0x24 "ADC_HTR1,ADC watchdog threshold register 1" hexmask.long 0x24 0.--25. 1. "HTR1,HTR1" group.long 0x30++0xF line.long 0x0 "ADC_SQR1,ADC regular sequence register 1" hexmask.long.byte 0x0 24.--28. 1. "SQ4,SQ4" hexmask.long.byte 0x0 18.--22. 1. "SQ3,SQ3" hexmask.long.byte 0x0 12.--16. 1. "SQ2,SQ2" hexmask.long.byte 0x0 6.--10. 1. "SQ1,SQ1" hexmask.long.byte 0x0 0.--3. 1. "L,L" line.long 0x4 "ADC_SQR2,ADC regular sequence register 2" hexmask.long.byte 0x4 24.--28. 1. "SQ9,SQ9" hexmask.long.byte 0x4 18.--22. 1. "SQ8,SQ8" hexmask.long.byte 0x4 12.--16. 1. "SQ7,SQ7" hexmask.long.byte 0x4 6.--10. 1. "SQ6,SQ6" hexmask.long.byte 0x4 0.--4. 1. "SQ5,SQ5" line.long 0x8 "ADC_SQR3,ADC regular sequence register 3" hexmask.long.byte 0x8 24.--28. 1. "SQ14,SQ14" hexmask.long.byte 0x8 18.--22. 1. "SQ13,SQ13" hexmask.long.byte 0x8 12.--16. 1. "SQ12,SQ12" hexmask.long.byte 0x8 6.--10. 1. "SQ11,SQ11" hexmask.long.byte 0x8 0.--4. 1. "SQ10,SQ10" line.long 0xC "ADC_SQR4,ADC regular sequence register 4" hexmask.long.byte 0xC 6.--10. 1. "SQ16,SQ16" hexmask.long.byte 0xC 0.--4. 1. "SQ15,SQ15" rgroup.long 0x40++0x3 line.long 0x0 "ADC_DR,ADC regular Data Register" hexmask.long 0x0 0.--31. 1. "RDATA,RDATA" group.long 0x4C++0x3 line.long 0x0 "ADC_JSQR,ADC injected sequence register" hexmask.long.byte 0x0 27.--31. 1. "JSQ4,JSQ4" hexmask.long.byte 0x0 21.--25. 1. "JSQ3,JSQ3" hexmask.long.byte 0x0 15.--19. 1. "JSQ2,JSQ2" hexmask.long.byte 0x0 9.--13. 1. "JSQ1,JSQ1" bitfld.long 0x0 7.--8. "JEXTEN,JEXTEN" "0,1,2,3" hexmask.long.byte 0x0 2.--6. 1. "JEXTSEL,JEXTSEL" bitfld.long 0x0 0.--1. "JL,JL" "0,1,2,3" group.long 0x60++0xF line.long 0x0 "ADC_OFR1,ADC offset register" bitfld.long 0x0 31. "SSATE,SSATE" "0,1" hexmask.long.byte 0x0 26.--30. 1. "OFFSET1_CH,OFFSET1_CH" hexmask.long 0x0 0.--25. 1. "OFFSET1,OFFSET1" line.long 0x4 "ADC_OFR2,ADC offset register" bitfld.long 0x4 31. "SSATE,SSATE" "0,1" hexmask.long.byte 0x4 26.--30. 1. "OFFSET2_CH,OFFSET2_CH" hexmask.long 0x4 0.--25. 1. "OFFSET2,OFFSET2" line.long 0x8 "ADC_OFR3,ADC offset register" bitfld.long 0x8 31. "SSATE,SSATE" "0,1" hexmask.long.byte 0x8 26.--30. 1. "OFFSET3_CH,OFFSET3_CH" hexmask.long 0x8 0.--25. 1. "OFFSET3,OFFSET3" line.long 0xC "ADC_OFR4,ADC offset register" bitfld.long 0xC 31. "SSATE,SSATE" "0,1" hexmask.long.byte 0xC 26.--30. 1. "OFFSET4_CH,OFFSET4_CH" hexmask.long 0xC 0.--25. 1. "OFFSET4,OFFSET4" rgroup.long 0x80++0xF line.long 0x0 "ADC_JDR1,ADC injected data register" hexmask.long 0x0 0.--31. 1. "JDATA,JDATA" line.long 0x4 "ADC_JDR2,ADC injected data register" hexmask.long 0x4 0.--31. 1. "JDATA,JDATA" line.long 0x8 "ADC_JDR3,ADC injected data register" hexmask.long 0x8 0.--31. 1. "JDATA,JDATA" line.long 0xC "ADC_JDR4,ADC injected data register" hexmask.long 0xC 0.--31. 1. "JDATA,JDATA" group.long 0xA0++0x7 line.long 0x0 "ADC_AWD2CR,ADC analog watchdog 2 configuration register" hexmask.long.tbyte 0x0 0.--19. 1. "AWD2CH,AWD2CH" line.long 0x4 "ADC_AWD3CR,ADC analog watchdog 3 configuration register" hexmask.long.tbyte 0x4 0.--19. 1. "AWD3CH,AWD3CH" group.long 0xB0++0x1B line.long 0x0 "ADC_LTR2,ADC watchdog lower threshold register 2" hexmask.long 0x0 0.--25. 1. "LTR2,LTR2" line.long 0x4 "ADC_HTR2,ADC watchdog higher threshold register 2" hexmask.long 0x4 0.--25. 1. "HTR2,HTR2" line.long 0x8 "ADC_LTR3,ADC watchdog lower threshold register 3" hexmask.long 0x8 0.--25. 1. "LTR3,LTR3" line.long 0xC "ADC_HTR3,ADC watchdog higher threshold register 3" hexmask.long 0xC 0.--25. 1. "HTR3,HTR3" line.long 0x10 "ADC_DIFSEL,ADC differential mode selection register" hexmask.long.tbyte 0x10 0.--19. 1. "DIFSEL,DIFSEL" line.long 0x14 "ADC_CALFACT,ADC calibration factors register" hexmask.long.word 0x14 16.--26. 1. "CALFACT_D,CALFACT_D" hexmask.long.word 0x14 0.--10. 1. "CALFACT_S,CALFACT_S" line.long 0x18 "ADC_CALFACT2,ADC calibration factor register 2" hexmask.long 0x18 0.--29. 1. "LINCALFACT,LINCALFACT" tree.end endif sif (cpuis("STM32MP151*")||cpuis("STM32MP153*")||cpuis("STM32MP157*")) tree "ADC_common" base ad:0x48003300 rgroup.long 0x0++0x3 line.long 0x0 "CSR,ADC Common status register" bitfld.long 0x0 26. "JQOVF_SLV,JQOVF_SLV" "0,1" bitfld.long 0x0 25. "AWD3_SLV,AWD3_SLV" "0,1" bitfld.long 0x0 24. "AWD2_SLV,AWD2_SLV" "0,1" bitfld.long 0x0 23. "AWD1_SLV,AWD1_SLV" "0,1" bitfld.long 0x0 22. "JEOS_SLV,JEOS_SLV" "0,1" bitfld.long 0x0 21. "JEOC_SLV,JEOC_SLV" "0,1" bitfld.long 0x0 20. "OVR_SLV,OVR_SLV" "0,1" bitfld.long 0x0 19. "EOS_SLV,EOS_SLV" "0,1" bitfld.long 0x0 18. "EOC_SLV,EOC_SLV" "0,1" newline bitfld.long 0x0 17. "EOSMP_SLV,EOSMP_SLV" "0,1" bitfld.long 0x0 16. "ADRDY_SLV,ADRDY_SLV" "0,1" bitfld.long 0x0 10. "JQOVF_MST,JQOVF_MST" "0,1" bitfld.long 0x0 9. "AWD3_MST,AWD3_MST" "0,1" bitfld.long 0x0 8. "AWD2_MST,AWD2_MST" "0,1" bitfld.long 0x0 7. "AWD1_MST,AWD1_MST" "0,1" bitfld.long 0x0 6. "JEOS_MST,JEOS_MST" "0,1" bitfld.long 0x0 5. "JEOC_MST,JEOC_MST" "0,1" bitfld.long 0x0 4. "OVR_MST,OVR_MST" "0,1" newline bitfld.long 0x0 3. "EOS_MST,EOS_MST" "0,1" bitfld.long 0x0 2. "EOC_MST,EOC_MST" "0,1" bitfld.long 0x0 1. "EOSMP_MST,EOSMP_MST" "0,1" bitfld.long 0x0 0. "ADDRDY_MST,ADDRDY_MST" "0,1" group.long 0x8++0x3 line.long 0x0 "CCR,ADC common control register" bitfld.long 0x0 24. "CH18SEL,CH18SEL" "0,1" bitfld.long 0x0 23. "CH17SEL,CH17SEL" "0,1" bitfld.long 0x0 22. "VREFEN,VREFINT enable" "0,1" hexmask.long.byte 0x0 18.--21. 1. "PRESC,ADC prescaler" bitfld.long 0x0 16.--17. "CKMODE,ADC clock mode" "0,1,2,3" bitfld.long 0x0 14.--15. "MDMA,MDMA" "0,1,2,3" bitfld.long 0x0 13. "DMACFG,DMACFG" "0,1" bitfld.long 0x0 8.--10. "DELAY,DELAY" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 0.--4. 1. "DUAL,DUAL" rgroup.long 0xC++0x7 line.long 0x0 "CDR,Common regular data register for dual mode" hexmask.long.word 0x0 16.--31. 1. "RDATA_SLV,RDATA_SLV" hexmask.long.word 0x0 0.--15. 1. "RDATA_MST,RDATA_MST" line.long 0x4 "CDR2,Common regular data register for dual mode" hexmask.long 0x4 0.--31. 1. "RDATA_ALT,RDATA_ALT" tree.end endif tree.end tree "AXIMC (AXI Interconnect Matrix Control)" base ad:0x0 sif (cpuis("STM32MP13*")) tree "AXIMC" base ad:0x57000000 rgroup.long 0x1FD0++0x2F line.long 0x0 "AXIMC_PERIPH_ID_4,AXIMC peripheral ID4 register" hexmask.long.byte 0x0 4.--7. 1. "K4COUNT,register file size" hexmask.long.byte 0x0 0.--3. 1. "JEP106CON,JEP106 continuation code" line.long 0x4 "AXIMC_PERIPH_ID_5,AXIMC peripheral ID5 register" hexmask.long.byte 0x4 0.--7. 1. "PERIPH_ID_5,reserved not used." line.long 0x8 "AXIMC_PERIPH_ID_6,AXIMC peripheral ID6 register" hexmask.long.byte 0x8 0.--7. 1. "PERIPH_ID_6,reserved not used." line.long 0xC "AXIMC_PERIPH_ID_7,AXIMC peripheral ID7 register" hexmask.long.byte 0xC 0.--7. 1. "PERIPH_ID_7,reserved not used." line.long 0x10 "AXIMC_PERIPH_ID_0,AXIMC peripheral ID0 register" hexmask.long.byte 0x10 0.--7. 1. "PERIPH_ID_0,part number [7:0]" line.long 0x14 "AXIMC_PERIPH_ID_1,AXIMC peripheral ID1 register" hexmask.long.byte 0x14 0.--7. 1. "PERIPH_ID_1,JEP106 identity [3:0] part number [11:8]" line.long 0x18 "AXIMC_PERIPH_ID_2,AXIMC peripheral ID2 register" hexmask.long.byte 0x18 0.--7. 1. "PERIPH_ID_2,part revision JEP106 code flag JEP106 identity [6:4]" line.long 0x1C "AXIMC_PERIPH_ID_3,AXIMC peripheral ID3 register" hexmask.long.byte 0x1C 4.--7. 1. "REV_AND,customer version" hexmask.long.byte 0x1C 0.--3. 1. "CUST_MOD_NUM,customer modification" line.long 0x20 "AXIMC_COMP_ID_0,AXIMC component ID0 register" hexmask.long.byte 0x20 0.--7. 1. "PREAMBLE,preamble bits [7:0]" line.long 0x24 "AXIMC_COMP_ID_1,AXIMC component ID1 register" hexmask.long.byte 0x24 4.--7. 1. "CLASS,Component class" hexmask.long.byte 0x24 0.--3. 1. "PREAMBLE,preamble bits [11:8]" line.long 0x28 "AXIMC_COMP_ID_2,AXIMC component ID2 register" hexmask.long.byte 0x28 0.--7. 1. "PREAMBLE,preamble bits [19:12]" line.long 0x2C "AXIMC_COMP_ID_3,AXIMC component ID3 register" hexmask.long.byte 0x2C 0.--7. 1. "PREAMBLE,preamble bits [27:20]" group.long 0x42024++0x7 line.long 0x0 "AXIMC_M0_FN_MOD2,AXIMC master 0 packing functionality register" bitfld.long 0x0 0. "BYPASS_MERGE,Disable packing of beats to match the output data width" "0: normal operation,1: disable packing" line.long 0x4 "AXIMC_M0_FN_MOD_AHB,AXIMC master 0 AHB conversion override functionality register" bitfld.long 0x4 1. "WR_INC_OVERRIDE,Converts all AHB-Lite read transactions to a series of single beat AXI transactions" "0: override disabled,1: override enabled" bitfld.long 0x4 0. "RD_INC_OVERRIDE,Converts all AHB-Lite write transactions to a series of single beat AXI transactions and each AHB-Lite write beat is acknowledged with the AXI buffered write response." "0: override disabled,1: override enabled" group.long 0x42100++0xB line.long 0x0 "AXIMC_M0_READ_QOS,AXIMC master 0 read priority register" hexmask.long.byte 0x0 0.--3. 1. "AR_QOS,read channel QoS setting" line.long 0x4 "AXIMC_M0_WRITE_QOS,AXIMC master 0 write priority register" hexmask.long.byte 0x4 0.--3. 1. "AW_QOS,write channel QoS setting" line.long 0x8 "AXIMC_M0_FN_MOD,AXIMC master 0 issuing capability override functionality register" bitfld.long 0x8 1. "WRITE_ISS_OVERRIDE,override AMIB write issuing capability" "0: normal issuing capability,1: force issuing capability to 1" bitfld.long 0x8 0. "READ_ISS_OVERRIDE,override AMIB read issuing capability" "0: normal issuing capability,1: force issuing capability to 1" group.long 0x43024++0x7 line.long 0x0 "AXIMC_M1_FN_MOD2,AXIMC master 1 packing functionality register" bitfld.long 0x0 0. "BYPASS_MERGE,Disable packing of beats to match the output data width" "0: normal operation,1: disable packing" line.long 0x4 "AXIMC_M1_FN_MOD_AHB,AXIMC master 1 AHB conversion override functionality register" bitfld.long 0x4 1. "WR_INC_OVERRIDE,Converts all AHB-Lite read transactions to a series of single beat AXI transactions" "0: override disabled,1: override enabled" bitfld.long 0x4 0. "RD_INC_OVERRIDE,Converts all AHB-Lite write transactions to a series of single beat AXI transactions and each AHB-Lite write beat is acknowledged with the AXI buffered write response." "0: override disabled,1: override enabled" group.long 0x43100++0xB line.long 0x0 "AXIMC_M1_READ_QOS,AXIMC master 1 read priority register" hexmask.long.byte 0x0 0.--3. 1. "AR_QOS,read channel QoS setting" line.long 0x4 "AXIMC_M1_WRITE_QOS,AXIMC master 1 write priority register" hexmask.long.byte 0x4 0.--3. 1. "AW_QOS,write channel QoS setting" line.long 0x8 "AXIMC_M1_FN_MOD,AXIMC master 1 issuing capability override functionality register" bitfld.long 0x8 1. "WRITE_ISS_OVERRIDE,override AMIB write issuing capability" "0: normal issuing capability,1: force issuing capability to 1" bitfld.long 0x8 0. "READ_ISS_OVERRIDE,override AMIB read issuing capability" "0: normal issuing capability,1: force issuing capability to 1" group.long 0x44024++0x7 line.long 0x0 "AXIMC_M2_FN_MOD2,AXIMC master 2 packing functionality register" bitfld.long 0x0 0. "BYPASS_MERGE,Disable packing of beats to match the output data width" "0: normal operation,1: disable packing" line.long 0x4 "AXIMC_M2_FN_MOD_AHB,AXIMC master 2 AHB conversion override functionality register" bitfld.long 0x4 1. "WR_INC_OVERRIDE,Converts all AHB-Lite read transactions to a series of single beat AXI transactions" "0: override disabled,1: override enabled" bitfld.long 0x4 0. "RD_INC_OVERRIDE,Converts all AHB-Lite write transactions to a series of single beat AXI transactions and each AHB-Lite write beat is acknowledged with the AXI buffered write response." "0: override disabled,1: override enabled" group.long 0x44100++0xB line.long 0x0 "AXIMC_M2_READ_QOS,AXIMC master 2 read priority register" hexmask.long.byte 0x0 0.--3. 1. "AR_QOS,read channel QoS setting" line.long 0x4 "AXIMC_M2_WRITE_QOS,AXIMC master 2 write priority register" hexmask.long.byte 0x4 0.--3. 1. "AW_QOS,write channel QoS setting" line.long 0x8 "AXIMC_M2_FN_MOD,AXIMC master 2 issuing capability override functionality register" bitfld.long 0x8 1. "WRITE_ISS_OVERRIDE,override AMIB write issuing capability" "0: normal issuing capability,1: force issuing capability to 1" bitfld.long 0x8 0. "READ_ISS_OVERRIDE,override AMIB read issuing capability" "0: normal issuing capability,1: force issuing capability to 1" group.long 0x45100++0xB line.long 0x0 "AXIMC_M3_READ_QOS,AXIMC master 3 read priority register" hexmask.long.byte 0x0 0.--3. 1. "AR_QOS,read channel QoS setting" line.long 0x4 "AXIMC_M3_WRITE_QOS,AXIMC master 3 write priority register" hexmask.long.byte 0x4 0.--3. 1. "AW_QOS,write channel QoS setting" line.long 0x8 "AXIMC_M3_FN_MOD,AXIMC master 3 packing functionality register" bitfld.long 0x8 1. "WRITE_ISS_OVERRIDE,override AMIB write issuing capability" "0: normal issuing capability,1: force issuing capability to 1" bitfld.long 0x8 0. "READ_ISS_OVERRIDE,override AMIB read issuing capability" "0: normal issuing capability,1: force issuing capability to 1" group.long 0x4602C++0x3 line.long 0x0 "AXIMC_M4_FN_MOD_LB,AXIMC long burst capability inhibition register" bitfld.long 0x0 0. "FN_MOD_LB,controls burst breaking of long bursts" "0: long bursts can not be generated at the output..,1: long bursts can be generated at the output of.." group.long 0x46100++0xB line.long 0x0 "AXIMC_M4_READ_QOS,AXIMC master 4 read priority register" hexmask.long.byte 0x0 0.--3. 1. "AR_QOS,read channel QoS setting" line.long 0x4 "AXIMC_M4_WRITE_QOS,AXIMC master 4 write priority register" hexmask.long.byte 0x4 0.--3. 1. "AW_QOS,write channel QoS setting" line.long 0x8 "AXIMC_M4_FN_MOD,AXIMC master 4 packing functionality register" bitfld.long 0x8 1. "WRITE_ISS_OVERRIDE,override AMIB write issuing capability" "0: normal issuing capability,1: force issuing capability to 1" bitfld.long 0x8 0. "READ_ISS_OVERRIDE,override AMIB read issuing capability" "0: normal issuing capability,1: force issuing capability to 1" group.long 0x47024++0x7 line.long 0x0 "AXIMC_M5_FN_MOD2,AXIMC master 5 packing functionality register" bitfld.long 0x0 0. "BYPASS_MERGE,Disable packing of beats to match the output data width" "0: normal operation,1: disable packing" line.long 0x4 "AXIMC_M5_FN_MOD_AHB,AXIMC master 5 AHB conversion override functionality register" bitfld.long 0x4 1. "WR_INC_OVERRIDE,converts all AHB-Lite read transactions to a series of single beat AXI transactions" "0: override disabled,1: override enabled" bitfld.long 0x4 0. "RD_INC_OVERRIDE,converts all AHB-Lite write transactions to a series of single beat AXI transactions and each AHB-Lite write beat is acknowledged with the AXI buffered write response." "0: override disabled,1: override enabled" group.long 0x47100++0xB line.long 0x0 "AXIMC_M5_READ_QOS,AXIMC master 5 read priority register" hexmask.long.byte 0x0 0.--3. 1. "AR_QOS,read channel QoS setting" line.long 0x4 "AXIMC_M5_WRITE_QOS,AXIMC master 5 write priority register" hexmask.long.byte 0x4 0.--3. 1. "AW_QOS,write channel QoS setting" line.long 0x8 "AXIMC_M5_FN_MOD,AXIMC master 5 issuing capability override functionality register" bitfld.long 0x8 1. "WRITE_ISS_OVERRIDE,override AMIB write issuing capability" "0: normal issuing capability,1: force issuing capability to 1" bitfld.long 0x8 0. "READ_ISS_OVERRIDE,override AMIB read issuing capability" "0: normal issuing capability,1: force issuing capability to 1" group.long 0x48024++0x7 line.long 0x0 "AXIMC_M6_FN_MOD2,AXIMC master 6 packing functionality register" bitfld.long 0x0 0. "BYPASS_MERGE,Disable packing of beats to match the output data width" "0: normal operation,1: disable packing" line.long 0x4 "AXIMC_M6_FN_MOD_AHB,AXIMC master 6 AHB conversion override functionality register" bitfld.long 0x4 1. "WR_INC_OVERRIDE,converts all AHB-Lite read transactions to a series of single beat AXI transactions" "0: override disabled,1: override enabled" bitfld.long 0x4 0. "RD_INC_OVERRIDE,converts all AHB-Lite write transactions to a series of single beat AXI transactions and each AHB-Lite write beat is acknowledged with the AXI buffered write response." "0: override disabled,1: override enabled" group.long 0x48100++0xB line.long 0x0 "AXIMC_M6_READ_QOS,AXIMC master 6 read priority register" hexmask.long.byte 0x0 0.--3. 1. "AR_QOS,read channel QoS setting" line.long 0x4 "AXIMC_M6_WRITE_QOS,AXIMC master 6 write priority register" hexmask.long.byte 0x4 0.--3. 1. "AW_QOS,write channel QoS setting" line.long 0x8 "AXIMC_M6_FN_MOD,AXIMC master 6 issuing capability override functionality register" bitfld.long 0x8 1. "WRITE_ISS_OVERRIDE,override AMIB write issuing capability" "0: normal issuing capability,1: force issuing capability to 1" bitfld.long 0x8 0. "READ_ISS_OVERRIDE,override AMIB read issuing capability" "0: normal issuing capability,1: force issuing capability to 1" group.long 0x49100++0xB line.long 0x0 "AXIMC_M7_READ_QOS,AXIMC master 7 read priority register" hexmask.long.byte 0x0 0.--3. 1. "AR_QOS,read channel QoS setting" line.long 0x4 "AXIMC_M7_WRITE_QOS,AXIMC master 7 write priority register" hexmask.long.byte 0x4 0.--3. 1. "AW_QOS,write channel QoS setting" line.long 0x8 "AXIMC_M7_FN_MOD,AXIMC master 7 issuing capability override functionality register" bitfld.long 0x8 1. "WRITE_ISS_OVERRIDE,override AMIB write issuing capability" "0: normal issuing capability,1: force issuing capability to 1" bitfld.long 0x8 0. "READ_ISS_OVERRIDE,override AMIB read issuing capability" "0: normal issuing capability,1: force issuing capability to 1" group.long 0x4A100++0xB line.long 0x0 "AXIMC_M8_READ_QOS,AXIMC master 8 read priority register" hexmask.long.byte 0x0 0.--3. 1. "AR_QOS,read channel QoS setting" line.long 0x4 "AXIMC_M8_WRITE_QOS,AXIMC master 8 write priority register" hexmask.long.byte 0x4 0.--3. 1. "AW_QOS,write channel QoS setting" line.long 0x8 "AXIMC_M8_FN_MOD,AXIMC master 8 issuing capability override functionality register" bitfld.long 0x8 1. "WRITE_ISS_OVERRIDE,override AMIB write issuing capability" "0: normal issuing capability,1: force issuing capability to 1" bitfld.long 0x8 0. "READ_ISS_OVERRIDE,override AMIB read issuing capability" "0: normal issuing capability,1: force issuing capability to 1" group.long 0x4B100++0xB line.long 0x0 "AXIMC_M9_READ_QOS,AXIMC master 9 read priority register" hexmask.long.byte 0x0 0.--3. 1. "AR_QOS,read channel QoS setting" line.long 0x4 "AXIMC_M9_WRITE_QOS,AXIMC master 9 write priority register" hexmask.long.byte 0x4 0.--3. 1. "AW_QOS,write channel QoS setting" line.long 0x8 "AXIMC_M9_FN_MOD,AXIMC master 9 issuing capability override functionality register" bitfld.long 0x8 1. "WRITE_ISS_OVERRIDE,override AMIB write issuing capability" "0: normal issuing capability,1: force issuing capability to 1" bitfld.long 0x8 0. "READ_ISS_OVERRIDE,override AMIB read issuing capability" "0: normal issuing capability,1: force issuing capability to 1" group.long 0x4C100++0xB line.long 0x0 "AXIMC_M10_READ_QOS,AXIMC master 10 read priority register" hexmask.long.byte 0x0 0.--3. 1. "AR_QOS,read channel QoS setting" line.long 0x4 "AXIMC_M10_WRITE_QOS,AXIMC master 10 write priority register" hexmask.long.byte 0x4 0.--3. 1. "AW_QOS,write channel QoS setting" line.long 0x8 "AXIMC_M10_FN_MOD,AXIMC master 10 issuing capability override functionality register" bitfld.long 0x8 1. "WRITE_ISS_OVERRIDE,override AMIB write issuing capability" "0: normal issuing capability,1: force issuing capability to 1" bitfld.long 0x8 0. "READ_ISS_OVERRIDE,override AMIB read issuing capability" "0: normal issuing capability,1: force issuing capability to 1" group.long 0x4D100++0xB line.long 0x0 "AXIMC_M11_READ_QOS,AXIMC master 11 read priority register" hexmask.long.byte 0x0 0.--3. 1. "AR_QOS,read channel QoS setting" line.long 0x4 "AXIMC_M11_WRITE_QOS,AXIMC master 11 write priority register" hexmask.long.byte 0x4 0.--3. 1. "AW_QOS,write channel QoS setting" line.long 0x8 "AXIMC_M11_FN_MOD,AXIMC master 11 issuing capability override functionality register" bitfld.long 0x8 1. "WRITE_ISS_OVERRIDE,override AMIB write issuing capability" "0: normal issuing capability,1: force issuing capability to 1" bitfld.long 0x8 0. "READ_ISS_OVERRIDE,override AMIB read issuing capability" "0: normal issuing capability,1: force issuing capability to 1" tree.end endif sif (cpuis("STM32MP151*")||cpuis("STM32MP153*")||cpuis("STM32MP157*")) tree "AXIMC_MX" base ad:0x57042024 group.long 0x0++0x3 line.long 0x0 "AXIMC_M0_FN_MOD2,AXIMC master 0 packing functionality register" bitfld.long 0x0 0. "BYPASS_MERGE,BYPASS_MERGE" "0,1" group.long 0xDC++0x3 line.long 0x0 "AXIMC_M0_READ_QOS,AXIMC master 0 read priority register" hexmask.long.byte 0x0 0.--3. 1. "AR_QOS,AR_QOS" group.long 0xE4++0x3 line.long 0x0 "AXIMC_M0_WRITE_QOS,AXIMC master 0 write priority register" hexmask.long.byte 0x0 0.--3. 1. "AW_QOS,AW_QOS" group.long 0xE0++0x3 line.long 0x0 "AXIMC_M0_FN_MOD,AXIMC master 0 issuing capability override functionality register" bitfld.long 0x0 1. "WRITE_ISS_OVERRIDE,WRITE_ISS_OVERRIDE" "0,1" bitfld.long 0x0 0. "READ_ISS_OVERRIDE,READ_ISS_OVERRIDE" "0,1" group.long 0x1000++0x3 line.long 0x0 "AXIMC_M1_FN_MOD2,AXIMC master 1 packing functionality register" bitfld.long 0x0 0. "BYPASS_MERGE,BYPASS_MERGE" "0,1" group.long 0x10DC++0xB line.long 0x0 "AXIMC_M1_READ_QOS,AXIMC master 1 read priority register" hexmask.long.byte 0x0 0.--3. 1. "AR_QOS,AR_QOS" line.long 0x4 "AXIMC_M1_WRITE_QOS,AXIMC master 1 write priority register" hexmask.long.byte 0x4 0.--3. 1. "AW_QOS,AW_QOS" line.long 0x8 "AXIMC_M1_FN_MOD,AXIMC master 1 issuing capability override functionality register" bitfld.long 0x8 1. "WRITE_ISS_OVERRIDE,WRITE_ISS_OVERRIDE" "0,1" bitfld.long 0x8 0. "READ_ISS_OVERRIDE,READ_ISS_OVERRIDE" "0,1" group.long 0x2000++0x3 line.long 0x0 "AXIMC_M2_FN_MOD2,AXIMC master 2 packing functionality register" bitfld.long 0x0 0. "BYPASS_MERGE,BYPASS_MERGE" "0,1" group.long 0x20DC++0xB line.long 0x0 "AXIMC_M2_READ_QOS,AXIMC master 2 read priority register" hexmask.long.byte 0x0 0.--3. 1. "AR_QOS,AR_QOS" line.long 0x4 "AXIMC_M2_WRITE_QOS,AXIMC master 2 write priority register" hexmask.long.byte 0x4 0.--3. 1. "AW_QOS,AW_QOS" line.long 0x8 "AXIMC_M2_FN_MOD,AXIMC master 2 issuing capability override functionality register" bitfld.long 0x8 1. "WRITE_ISS_OVERRIDE,WRITE_ISS_OVERRIDE" "0,1" bitfld.long 0x8 0. "READ_ISS_OVERRIDE,READ_ISS_OVERRIDE" "0,1" group.long 0x3000++0x3 line.long 0x0 "AXIMC_M5_FN_MOD2,AXIMC master 5 packing functionality register" bitfld.long 0x0 0. "BYPASS_MERGE,BYPASS_MERGE" "0,1" group.long 0x30DC++0xB line.long 0x0 "AXIMC_M5_READ_QOS,AXIMC master 5 read priority register" hexmask.long.byte 0x0 0.--3. 1. "AR_QOS,AR_QOS" line.long 0x4 "AXIMC_M5_WRITE_QOS,AXIMC master 5 write priority register" hexmask.long.byte 0x4 0.--3. 1. "AW_QOS,AW_QOS" line.long 0x8 "AXIMC_M5_FN_MOD,AXIMC master 5 issuing capability override functionality register" bitfld.long 0x8 1. "WRITE_ISS_OVERRIDE,WRITE_ISS_OVERRIDE" "0,1" bitfld.long 0x8 0. "READ_ISS_OVERRIDE,READ_ISS_OVERRIDE" "0,1" group.long 0x40DC++0xB line.long 0x0 "AXIMC_M3_READ_QOS,AXIMC master 3 read priority register" hexmask.long.byte 0x0 0.--3. 1. "AR_QOS,AR_QOS" line.long 0x4 "AXIMC_M3_WRITE_QOS,AXIMC master 3 write priority register" hexmask.long.byte 0x4 0.--3. 1. "AW_QOS,AW_QOS" line.long 0x8 "AXIMC_M3_FN_MOD,AXIMC master 3 packing functionality register" bitfld.long 0x8 1. "WRITE_ISS_OVERRIDE,WRITE_ISS_OVERRIDE" "0,1" bitfld.long 0x8 0. "READ_ISS_OVERRIDE,READ_ISS_OVERRIDE" "0,1" group.long 0x50DC++0xB line.long 0x0 "AXIMC_M7_READ_QOS,AXIMC master 7 read priority register" hexmask.long.byte 0x0 0.--3. 1. "AR_QOS,AR_QOS" line.long 0x4 "AXIMC_M7_WRITE_QOS,AXIMC master 7 write priority register" hexmask.long.byte 0x4 0.--3. 1. "AW_QOS,AW_QOS" line.long 0x8 "AXIMC_M7_FN_MOD,AXIMC master 7 issuing capability override functionality register" bitfld.long 0x8 1. "WRITE_ISS_OVERRIDE,WRITE_ISS_OVERRIDE" "0,1" bitfld.long 0x8 0. "READ_ISS_OVERRIDE,READ_ISS_OVERRIDE" "0,1" group.long 0x60DC++0xB line.long 0x0 "AXIMC_M8_READ_QOS,AXIMC master 8 read priority register" hexmask.long.byte 0x0 0.--3. 1. "AR_QOS,AR_QOS" line.long 0x4 "AXIMC_M8_WRITE_QOS,AXIMC master 8 write priority register" hexmask.long.byte 0x4 0.--3. 1. "AW_QOS,AW_QOS" line.long 0x8 "AXIMC_M8_FN_MOD,AXIMC master 8 issuing capability override functionality register" bitfld.long 0x8 1. "WRITE_ISS_OVERRIDE,WRITE_ISS_OVERRIDE" "0,1" bitfld.long 0x8 0. "READ_ISS_OVERRIDE,READ_ISS_OVERRIDE" "0,1" group.long 0x8000++0x3 line.long 0x0 "AXIMC_M4_FN_MOD2,AXIMC master 4 packing functionality register" bitfld.long 0x0 0. "BYPASS_MERGE,BYPASS_MERGE" "0,1" group.long 0x80DC++0xB line.long 0x0 "AXIMC_M4_READ_QOS,AXIMC master 4 read priority register" hexmask.long.byte 0x0 0.--3. 1. "AR_QOS,AR_QOS" line.long 0x4 "AXIMC_M4_WRITE_QOS,AXIMC master 4 write priority register" hexmask.long.byte 0x4 0.--3. 1. "AW_QOS,AW_QOS" line.long 0x8 "AXIMC_M4_FN_MOD,AXIMC master 4 packing functionality register" bitfld.long 0x8 1. "WRITE_ISS_OVERRIDE,WRITE_ISS_OVERRIDE" "0,1" bitfld.long 0x8 0. "READ_ISS_OVERRIDE,READ_ISS_OVERRIDE" "0,1" group.long 0x90DC++0xB line.long 0x0 "AXIMC_M9_READ_QOS,AXIMC master 9 read priority register" hexmask.long.byte 0x0 0.--3. 1. "AR_QOS,AR_QOS" line.long 0x4 "AXIMC_M9_WRITE_QOS,AXIMC master 9 write priority register" hexmask.long.byte 0x4 0.--3. 1. "AW_QOS,AW_QOS" line.long 0x8 "AXIMC_M9_FN_MOD,AXIMC master 9 issuing capability override functionality register" bitfld.long 0x8 1. "WRITE_ISS_OVERRIDE,WRITE_ISS_OVERRIDE" "0,1" bitfld.long 0x8 0. "READ_ISS_OVERRIDE,READ_ISS_OVERRIDE" "0,1" group.long 0xA0DC++0xB line.long 0x0 "AXIMC_M10_READ_QOS,AXIMC master 10 read priority register" hexmask.long.byte 0x0 0.--3. 1. "AR_QOS,AR_QOS" line.long 0x4 "AXIMC_M10_WRITE_QOS,AXIMC master 10 write priority register" hexmask.long.byte 0x4 0.--3. 1. "AW_QOS,AW_QOS" line.long 0x8 "AXIMC_M10_FN_MOD,AXIMC master 10 issuing capability override functionality register" bitfld.long 0x8 1. "WRITE_ISS_OVERRIDE,WRITE_ISS_OVERRIDE" "0,1" bitfld.long 0x8 0. "READ_ISS_OVERRIDE,READ_ISS_OVERRIDE" "0,1" group.long 0xB000++0x3 line.long 0x0 "AXIMC_M6_FN_MOD2,AXIMC master 6 packing functionality register" bitfld.long 0x0 0. "BYPASS_MERGE,BYPASS_MERGE" "0,1" group.long 0xB0DC++0xB line.long 0x0 "AXIMC_M6_READ_QOS,AXIMC master 6 read priority register" hexmask.long.byte 0x0 0.--3. 1. "AR_QOS,AR_QOS" line.long 0x4 "AXIMC_M6_WRITE_QOS,AXIMC master 6 write priority register" hexmask.long.byte 0x4 0.--3. 1. "AW_QOS,AW_QOS" line.long 0x8 "AXIMC_M6_FN_MOD,AXIMC master 6 issuing capability override functionality register" bitfld.long 0x8 1. "WRITE_ISS_OVERRIDE,WRITE_ISS_OVERRIDE" "0,1" bitfld.long 0x8 0. "READ_ISS_OVERRIDE,READ_ISS_OVERRIDE" "0,1" rgroup.long 0x1FD0++0x2F line.long 0x0 "AXIMC_PERIPH_ID_4,AXIMC peripheral ID4 register" hexmask.long.byte 0x0 4.--7. 1. "K4COUNT,K4COUNT" hexmask.long.byte 0x0 0.--3. 1. "JEP106CON,JEP106CON" line.long 0x4 "AXIMC_PERIPH_ID_5,AXIMC peripheral ID5 register" hexmask.long.byte 0x4 0.--7. 1. "PERIPH_ID_5,PERIPH_ID_5" line.long 0x8 "AXIMC_PERIPH_ID_6,AXIMC peripheral ID6 register" hexmask.long.byte 0x8 0.--7. 1. "PERIPH_ID_6,PERIPH_ID_6" line.long 0xC "AXIMC_PERIPH_ID_7,AXIMC peripheral ID7 register" hexmask.long.byte 0xC 0.--7. 1. "PERIPH_ID_7,PERIPH_ID_7" line.long 0x10 "AXIMC_PERIPH_ID_0,AXIMC peripheral ID0 register" hexmask.long.byte 0x10 0.--7. 1. "PERIPH_ID_0,PERIPH_ID_0" line.long 0x14 "AXIMC_PERIPH_ID_1,AXIMC peripheral ID1 register" hexmask.long.byte 0x14 0.--7. 1. "PERIPH_ID_1,PERIPH_ID_1" line.long 0x18 "AXIMC_PERIPH_ID_2,AXIMC peripheral ID2 register" hexmask.long.byte 0x18 0.--7. 1. "PERIPH_ID_2,PERIPH_ID_2" line.long 0x1C "AXIMC_PERIPH_ID_3,AXIMC peripheral ID3 register" hexmask.long.byte 0x1C 4.--7. 1. "REV_AND,REV_AND" hexmask.long.byte 0x1C 0.--3. 1. "CUST_MOD_NUM,CUST_MOD_NUM" line.long 0x20 "AXIMC_COMP_ID_0,AXIMC component ID0 register" hexmask.long.byte 0x20 0.--7. 1. "PREAMBLE,PREAMBLE" line.long 0x24 "AXIMC_COMP_ID_1,AXIMC component ID1 register" hexmask.long.byte 0x24 4.--7. 1. "CLASS,CLASS" hexmask.long.byte 0x24 0.--3. 1. "PREAMBLE,PREAMBLE" line.long 0x28 "AXIMC_COMP_ID_2,AXIMC component ID2 register" hexmask.long.byte 0x28 0.--7. 1. "PREAMBLE,PREAMBLE" line.long 0x2C "AXIMC_COMP_ID_3,AXIMC component ID3 register" hexmask.long.byte 0x2C 0.--7. 1. "PREAMBLE,PREAMBLE" group.long 0x42028++0x3 line.long 0x0 "AXIMC_M0_FN_MOD_AHB,AXIMC master 0 AHB conversion override functionality register" bitfld.long 0x0 1. "WR_INC_OVERRIDE,WR_INC_OVERRIDE" "0,1" bitfld.long 0x0 0. "RD_INC_OVERRIDE,RD_INC_OVERRIDE" "0,1" group.long 0x43028++0x3 line.long 0x0 "AXIMC_M1_FN_MOD_AHB,AXIMC master 1 AHB conversion override functionality register" bitfld.long 0x0 1. "WR_INC_OVERRIDE,WR_INC_OVERRIDE" "0,1" bitfld.long 0x0 0. "RD_INC_OVERRIDE,RD_INC_OVERRIDE" "0,1" group.long 0x44028++0x3 line.long 0x0 "AXIMC_M2_FN_MOD_AHB,AXIMC master 2 AHB conversion override functionality register" bitfld.long 0x0 1. "WR_INC_OVERRIDE,WR_INC_OVERRIDE" "0,1" bitfld.long 0x0 0. "RD_INC_OVERRIDE,RD_INC_OVERRIDE" "0,1" group.long 0x45028++0x3 line.long 0x0 "AXIMC_M5_FN_MOD_AHB,AXIMC master 5 AHB conversion override functionality register" bitfld.long 0x0 1. "WR_INC_OVERRIDE,WR_INC_OVERRIDE" "0,1" bitfld.long 0x0 0. "RD_INC_OVERRIDE,RD_INC_OVERRIDE" "0,1" group.long 0x4D028++0x3 line.long 0x0 "AXIMC_M6_FN_MOD_AHB,AXIMC master 6 AHB conversion override functionality register" bitfld.long 0x0 1. "WR_INC_OVERRIDE,WR_INC_OVERRIDE" "0,1" bitfld.long 0x0 0. "RD_INC_OVERRIDE,RD_INC_OVERRIDE" "0,1" group.long 0x4A02C++0x3 line.long 0x0 "AXIMC_FN_MOD_LB,AXIMC long burst capability inhibition register" bitfld.long 0x0 0. "FN_MOD_LB,FN_MOD_LB" "0,1" tree.end endif tree.end tree "BSEC (Boot and Security and OTP Control)" base ad:0x5C005000 group.long 0x0++0x17 line.long 0x0 "BSEC_OTP_CONFIG,BSEC OTP configuration register" bitfld.long 0x0 7.--8. "TREAD,set OTP reading current level (default = 0b00)" "0,1,2,3" hexmask.long.byte 0x0 3.--6. 1. "PRGWIDTH,OTP programming pulse width (default = 0b0001)" newline sif (cpuis("STM32MP13*")) bitfld.long 0x0 1.--2. "FRC,OTP clock frequency range selection" "0: 10 MHz ≤ frequency ≤ 20 MHz,1: 20 MHz ≤ frequency ≤ 30 MHz,2: 30 MHz ≤ frequency ≤ 45 MHz,3: 45 MHz ≤ frequency ≤ 67 MHz" bitfld.long 0x0 0. "PWRUP,OTP power-up control" "0: OTP powered down,1: OTP powered up" newline endif sif (cpuis("STM32MP151*")) bitfld.long 0x0 1.--2. "FRC,FRC" "0,1,2,3" endif sif (cpuis("STM32MP153*")) bitfld.long 0x0 1.--2. "FRC,FRC" "0,1,2,3" newline bitfld.long 0x0 0. "PWRUP,PWRUP" "0,1" endif sif (cpuis("STM32MP157*")) bitfld.long 0x0 1.--2. "FRC,FRC" "0,1,2,3" newline bitfld.long 0x0 0. "PWRUP,PWRUP" "0,1" endif line.long 0x4 "BSEC_OTP_CONTROL,BSEC OTP control register" sif (cpuis("STM32MP13*")) bitfld.long 0x4 9. "LOCK,OTP permanent word lock control" "0: OTP normal word programing,1: OTP permanent write lock word programming" bitfld.long 0x4 8. "PROG,OTP operation control" "0: OTP read operation,1: OTP program operation" newline endif sif (cpuis("STM32MP151*")) bitfld.long 0x4 9. "LOCK,LOCK" "0,1" bitfld.long 0x4 8. "PROG,PROG" "0,1" newline endif sif (cpuis("STM32MP153*")) bitfld.long 0x4 9. "LOCK,LOCK" "0,1" bitfld.long 0x4 8. "PROG,PROG" "0,1" newline endif sif (cpuis("STM32MP157*")) bitfld.long 0x4 9. "LOCK,LOCK" "0,1" bitfld.long 0x4 8. "PROG,PROG" "0,1" newline endif hexmask.long.byte 0x4 0.--6. 1. "ADDR,OTP word address" line.long 0x8 "BSEC_OTP_WRDATA,BSEC OTP write data register" hexmask.long 0x8 0.--31. 1. "WRDATA,OTP write data" line.long 0xC "BSEC_OTP_STATUS,BSEC OTP status register" sif (cpuis("STM32MP13*")) rbitfld.long 0xC 10. "JTAGDIS,JTAG port status" "0: JTAG Port is not disabled,1: JTAG Port is disabled except for accessing.." rbitfld.long 0xC 9. "BSCANDIS,Boundary Scan status" "0: Boundary Scan is not disabled,1: Boundary Scan is disabled" newline rbitfld.long 0xC 8. "CLOSED,OTP_SECURED mode" "0: OTP-SECURED open device,1: OTP-SECURED closed device" rbitfld.long 0xC 5. "PWRON,OTP power status" "0: OTP in power off,1: OTP in power on" newline rbitfld.long 0xC 4. "PROGFAIL,last programming status" "0: OTP successful last programming,1: OTP failed last programming" rbitfld.long 0xC 3. "BUSY,OTP operation status" "0: OTP idle,1: OTP operation on going" newline rbitfld.long 0xC 2. "INVALID,OTP invalid mode" "0: OTP mode is not OTP-INVALID,1: OTP mode is OTP-INVALID" rbitfld.long 0xC 0. "SECURE,OTP secured mode" "0: OTP mode is not OTP-SECURED,1: OTP mode is OTP-SECURED" newline endif sif (cpuis("STM32MP151*")) bitfld.long 0xC 7. "BIST2LOCK,BIST2LOCK" "0,1" bitfld.long 0xC 6. "BIST1LOCK,BIST1LOCK" "0,1" newline bitfld.long 0xC 5. "PWRON,PWRON" "0,1" bitfld.long 0xC 4. "PROGFAIL,PROGFAIL" "0,1" newline bitfld.long 0xC 3. "BUSY,BUSY" "0,1" bitfld.long 0xC 2. "INVALID,INVALID" "0,1" newline bitfld.long 0xC 1. "FULLDBG,FULLDBG" "0,1" bitfld.long 0xC 0. "SECURE,SECURE" "0,1" newline endif sif (cpuis("STM32MP153*")) bitfld.long 0xC 7. "BIST2LOCK,BIST2LOCK" "0,1" bitfld.long 0xC 6. "BIST1LOCK,BIST1LOCK" "0,1" newline bitfld.long 0xC 5. "PWRON,PWRON" "0,1" bitfld.long 0xC 4. "PROGFAIL,PROGFAIL" "0,1" newline bitfld.long 0xC 3. "BUSY,BUSY" "0,1" bitfld.long 0xC 2. "INVALID,INVALID" "0,1" newline bitfld.long 0xC 1. "FULLDBG,FULLDBG" "0,1" bitfld.long 0xC 0. "SECURE,SECURE" "0,1" newline endif sif (cpuis("STM32MP157*")) bitfld.long 0xC 7. "BIST2LOCK,BIST2LOCK" "0,1" bitfld.long 0xC 6. "BIST1LOCK,BIST1LOCK" "0,1" newline bitfld.long 0xC 5. "PWRON,PWRON" "0,1" bitfld.long 0xC 4. "PROGFAIL,PROGFAIL" "0,1" newline bitfld.long 0xC 3. "BUSY,BUSY" "0,1" bitfld.long 0xC 2. "INVALID,INVALID" "0,1" newline bitfld.long 0xC 1. "FULLDBG,FULLDBG" "0,1" bitfld.long 0xC 0. "SECURE,SECURE" "0,1" endif line.long 0x10 "BSEC_OTP_LOCK,BSEC OTP lock configuration register" sif (cpuis("STM32MP13*")) bitfld.long 0x10 4. "GPLOCK,programming sticky lock" "0: programming allowed,1: programming disabled until next system reset" bitfld.long 0x10 2. "DENREG,debug enable register sticky lock" "0: BSEC_DENABLE register not locked,1: BSEC_DENABLE register locked until next system.." newline bitfld.long 0x10 1. "ROMLOCK,Upper ROM region read lock" "0: Upper ROM region is accessible,1: Upper ROM region is no more accessible until.." bitfld.long 0x10 0. "OTP,upper OTP read lock" "0: upper OTP not locked,1: upper OTP cannot be reloaded until next system.." newline endif sif (cpuis("STM32MP151*")) bitfld.long 0x10 4. "GPLOCK,GPLOCK" "0,1" endif sif (cpuis("STM32MP153*")) bitfld.long 0x10 4. "GPLOCK,GPLOCK" "0,1" newline endif sif (cpuis("STM32MP157*")) bitfld.long 0x10 4. "GPLOCK,GPLOCK" "0,1" endif sif (cpuis("STM32MP151*")) bitfld.long 0x10 2. "DENREG,DENREG" "0,1" newline bitfld.long 0x10 1. "ROMLOCK,ROMLOCK" "0,1" endif sif (cpuis("STM32MP153*")) bitfld.long 0x10 2. "DENREG,DENREG" "0,1" newline bitfld.long 0x10 1. "ROMLOCK,ROMLOCK" "0,1" bitfld.long 0x10 0. "OTP,OTP" "0,1" newline endif sif (cpuis("STM32MP157*")) bitfld.long 0x10 2. "DENREG,DENREG" "0,1" bitfld.long 0x10 1. "ROMLOCK,ROMLOCK" "0,1" newline bitfld.long 0x10 0. "OTP,OTP" "0,1" endif line.long 0x14 "BSEC_DENABLE,BSEC debug configuration register" sif (cpuis("STM32MP151*")) bitfld.long 0x14 10. "DBGSWENABLE,DBGSWENABLE" "0,1" bitfld.long 0x14 9. "CFGSDISABLE,CFGSDISABLE" "0,1" newline bitfld.long 0x14 7.--8. "CP15SDISABLE,CP15SDISABLE" "0,1,2,3" bitfld.long 0x14 6. "SPNIDEN,SPNIDEN" "0,1" newline bitfld.long 0x14 5. "SPIDEN,SPIDEN" "0,1" bitfld.long 0x14 4. "HDPEN,HDPEN" "0,1" newline bitfld.long 0x14 3. "DEVICEEN,DEVICEEN" "0,1" bitfld.long 0x14 2. "NIDEN,NIDEN" "0,1" newline bitfld.long 0x14 1. "DBGEN,DBGEN" "0,1" bitfld.long 0x14 0. "DFTEN,DFTEN" "0,1" newline endif sif (cpuis("STM32MP13*")) bitfld.long 0x14 10. "DBGSWENABLE,control self hosted debug enable with signal dbgswenable" "0: Software access to all debug components is..,1: Software access to all debug components is enabled" bitfld.long 0x14 9. "CFGSDISABLE,write access to secure GIC registers disable with signal cfgsdisable" "0: no effect all GIC registers are accessible,1: Disable write access to some secure GIC registers" newline bitfld.long 0x14 7. "CP15SDISABLE,write access to some secure Cortex®-A7 CP15 registers disable" "0: All CP15 registers are accessible,1: Disable write access to some secure CP15.." bitfld.long 0x14 6. "SPNIDEN,secure privilege non-invasive debug enable with signal spiden" "0: secure privilege non-invasive debug disabled,1: secure privilege non-invasive debug enabled" newline bitfld.long 0x14 5. "SPIDEN,secure privilege invasive debug enable with signal spniden" "0: secure privilege invasive debug disabled,1: secure privilege invasive debug enabled" bitfld.long 0x14 4. "HDPEN,hardware debug port enable with signal hdpen" "0: hardware debug port disabled,1: hardware debug port enabled" newline bitfld.long 0x14 3. "DEVICEEN,controls access to debug component via external debug port by signal deviceen" "0: disabled,1: enabled" bitfld.long 0x14 2. "NIDEN,non-invasive debug enable with signal niden" "0: non-invasive debug disabled,1: non-invasive debug enabled" newline bitfld.long 0x14 1. "DBGEN,debug enable with signal dbgen" "0: disabled,1: enabled" endif sif (cpuis("STM32MP153*")) bitfld.long 0x14 10. "DBGSWENABLE,DBGSWENABLE" "0,1" newline bitfld.long 0x14 9. "CFGSDISABLE,CFGSDISABLE" "0,1" bitfld.long 0x14 7.--8. "CP15SDISABLE,CP15SDISABLE" "0,1,2,3" newline bitfld.long 0x14 6. "SPNIDEN,SPNIDEN" "0,1" bitfld.long 0x14 5. "SPIDEN,SPIDEN" "0,1" newline bitfld.long 0x14 4. "HDPEN,HDPEN" "0,1" bitfld.long 0x14 3. "DEVICEEN,DEVICEEN" "0,1" newline bitfld.long 0x14 2. "NIDEN,NIDEN" "0,1" bitfld.long 0x14 1. "DBGEN,DBGEN" "0,1" newline bitfld.long 0x14 0. "DFTEN,DFTEN" "0,1" endif sif (cpuis("STM32MP157*")) bitfld.long 0x14 10. "DBGSWENABLE,DBGSWENABLE" "0,1" newline bitfld.long 0x14 9. "CFGSDISABLE,CFGSDISABLE" "0,1" bitfld.long 0x14 7.--8. "CP15SDISABLE,CP15SDISABLE" "0,1,2,3" newline bitfld.long 0x14 6. "SPNIDEN,SPNIDEN" "0,1" bitfld.long 0x14 5. "SPIDEN,SPIDEN" "0,1" newline bitfld.long 0x14 4. "HDPEN,HDPEN" "0,1" bitfld.long 0x14 3. "DEVICEEN,DEVICEEN" "0,1" newline bitfld.long 0x14 2. "NIDEN,NIDEN" "0,1" bitfld.long 0x14 1. "DBGEN,DBGEN" "0,1" newline bitfld.long 0x14 0. "DFTEN,DFTEN" "0,1" endif group.long 0x1C++0xB line.long 0x0 "BSEC_OTP_DISTURBED0,BSEC OTP disturbed status register 0" sif (cpuis("STM32MP13*")) hexmask.long 0x0 0.--31. 1. "DIS,disturbed status of the corresponding OTP word" endif sif (cpuis("STM32MP151*")) hexmask.long 0x0 0.--31. 1. "DIS,DIS" newline endif sif (cpuis("STM32MP153*")) hexmask.long 0x0 0.--31. 1. "DIS,DIS" endif sif (cpuis("STM32MP157*")) hexmask.long 0x0 0.--31. 1. "DIS,DIS" endif line.long 0x4 "BSEC_OTP_DISTURBED1,BSEC OTP disturbed status register 1" sif (cpuis("STM32MP13*")) hexmask.long 0x4 0.--31. 1. "DIS,disturbed status of the corresponding OTP word" endif sif (cpuis("STM32MP151*")) hexmask.long 0x4 0.--31. 1. "DIS,DIS" newline endif sif (cpuis("STM32MP153*")) hexmask.long 0x4 0.--31. 1. "DIS,DIS" endif sif (cpuis("STM32MP157*")) hexmask.long 0x4 0.--31. 1. "DIS,DIS" endif line.long 0x8 "BSEC_OTP_DISTURBED2,BSEC OTP disturbed status register 2" sif (cpuis("STM32MP13*")) hexmask.long 0x8 0.--31. 1. "DIS,disturbed status of the corresponding OTP word" endif sif (cpuis("STM32MP151*")) hexmask.long 0x8 0.--31. 1. "DIS,DIS" newline endif sif (cpuis("STM32MP153*")) hexmask.long 0x8 0.--31. 1. "DIS,DIS" endif sif (cpuis("STM32MP157*")) hexmask.long 0x8 0.--31. 1. "DIS,DIS" endif group.long 0x34++0xB line.long 0x0 "BSEC_OTP_ERROR0,BSEC OTP error status register 0" sif (cpuis("STM32MP13*")) hexmask.long 0x0 0.--31. 1. "ERR,error status of the correspond OTP word" endif sif (cpuis("STM32MP151*")) hexmask.long 0x0 0.--31. 1. "ERR,ERR" newline endif sif (cpuis("STM32MP153*")) hexmask.long 0x0 0.--31. 1. "ERR,ERR" endif sif (cpuis("STM32MP157*")) hexmask.long 0x0 0.--31. 1. "ERR,ERR" endif line.long 0x4 "BSEC_OTP_ERROR1,BSEC OTP error status register 1" sif (cpuis("STM32MP13*")) hexmask.long 0x4 0.--31. 1. "ERR,error status of the correspond OTP word" endif sif (cpuis("STM32MP151*")) hexmask.long 0x4 0.--31. 1. "ERR,ERR" newline endif sif (cpuis("STM32MP153*")) hexmask.long 0x4 0.--31. 1. "ERR,ERR" endif sif (cpuis("STM32MP157*")) hexmask.long 0x4 0.--31. 1. "ERR,ERR" endif line.long 0x8 "BSEC_OTP_ERROR2,BSEC OTP error status register 2" sif (cpuis("STM32MP13*")) hexmask.long 0x8 0.--31. 1. "ERR,error status of the correspond OTP word" endif sif (cpuis("STM32MP151*")) hexmask.long 0x8 0.--31. 1. "ERR,ERR" newline endif sif (cpuis("STM32MP153*")) hexmask.long 0x8 0.--31. 1. "ERR,ERR" endif sif (cpuis("STM32MP157*")) hexmask.long 0x8 0.--31. 1. "ERR,ERR" endif group.long 0x4C++0xB line.long 0x0 "BSEC_OTP_WRLOCK0,BSEC OTP lock status register 0" sif (cpuis("STM32MP13*")) hexmask.long 0x0 0.--31. 1. "WRLOCK,permanent word lock status of the correspond OTP word" endif sif (cpuis("STM32MP151*")) hexmask.long 0x0 0.--31. 1. "WRLOCK,WRLOCK" newline endif sif (cpuis("STM32MP153*")) hexmask.long 0x0 0.--31. 1. "WRLOCK,WRLOCK" endif sif (cpuis("STM32MP157*")) hexmask.long 0x0 0.--31. 1. "WRLOCK,WRLOCK" endif line.long 0x4 "BSEC_OTP_WRLOCK1,BSEC OTP lock status register 1" sif (cpuis("STM32MP13*")) hexmask.long 0x4 0.--31. 1. "WRLOCK,permanent word lock status of the correspond OTP word" endif sif (cpuis("STM32MP151*")) hexmask.long 0x4 0.--31. 1. "WRLOCK,WRLOCK" newline endif sif (cpuis("STM32MP153*")) hexmask.long 0x4 0.--31. 1. "WRLOCK,WRLOCK" endif sif (cpuis("STM32MP157*")) hexmask.long 0x4 0.--31. 1. "WRLOCK,WRLOCK" endif line.long 0x8 "BSEC_OTP_WRLOCK2,BSEC OTP lock status register 2" sif (cpuis("STM32MP13*")) hexmask.long 0x8 0.--31. 1. "WRLOCK,permanent word lock status of the correspond OTP word" endif sif (cpuis("STM32MP151*")) hexmask.long 0x8 0.--31. 1. "WRLOCK,WRLOCK" newline endif sif (cpuis("STM32MP153*")) hexmask.long 0x8 0.--31. 1. "WRLOCK,WRLOCK" endif sif (cpuis("STM32MP157*")) hexmask.long 0x8 0.--31. 1. "WRLOCK,WRLOCK" endif group.long 0x64++0xB line.long 0x0 "BSEC_OTP_SPLOCK0,BSEC OTP sticky programming lock register 0" sif (cpuis("STM32MP13*")) hexmask.long 0x0 0.--31. 1. "SPLOCK,lock programming for the OTP word until next power-on reset" endif sif (cpuis("STM32MP153*")) hexmask.long 0x0 0.--31. 1. "SPLOCK,SPLOCK" newline endif sif (cpuis("STM32MP157*")) hexmask.long 0x0 0.--31. 1. "SPLOCK,SPLOCK" endif line.long 0x4 "BSEC_OTP_SPLOCK1,BSEC OTP sticky programming lock register 1" sif (cpuis("STM32MP13*")) hexmask.long 0x4 0.--31. 1. "SPLOCK,lock programming for the OTP word until next power-on reset" endif sif (cpuis("STM32MP153*")) hexmask.long 0x4 0.--31. 1. "SPLOCK,SPLOCK" newline endif sif (cpuis("STM32MP157*")) hexmask.long 0x4 0.--31. 1. "SPLOCK,SPLOCK" endif line.long 0x8 "BSEC_OTP_SPLOCK2,BSEC OTP sticky programming lock register 2" sif (cpuis("STM32MP13*")) hexmask.long 0x8 0.--31. 1. "SPLOCK,lock programming for the OTP word until next power-on reset" endif sif (cpuis("STM32MP153*")) hexmask.long 0x8 0.--31. 1. "SPLOCK,SPLOCK" newline endif sif (cpuis("STM32MP157*")) hexmask.long 0x8 0.--31. 1. "SPLOCK,SPLOCK" endif group.long 0x7C++0xB line.long 0x0 "BSEC_OTP_SWLOCK0,BSEC OTP shadow write sticky lock register 0" sif (cpuis("STM32MP13*")) hexmask.long 0x0 0.--31. 1. "SWLOCK,lock the writing for the OTP shadow word until next power-on reset." endif sif (cpuis("STM32MP153*")) hexmask.long 0x0 0.--31. 1. "SWLOCK,SWLOCK" newline endif sif (cpuis("STM32MP157*")) hexmask.long 0x0 0.--31. 1. "SWLOCK,SWLOCK" endif line.long 0x4 "BSEC_OTP_SWLOCK1,BSEC OTP shadow write sticky lock register 1" sif (cpuis("STM32MP13*")) hexmask.long 0x4 0.--31. 1. "SWLOCK,lock the writing for the OTP shadow word until next power-on reset." endif sif (cpuis("STM32MP153*")) hexmask.long 0x4 0.--31. 1. "SWLOCK,SWLOCK" newline endif sif (cpuis("STM32MP157*")) hexmask.long 0x4 0.--31. 1. "SWLOCK,SWLOCK" endif line.long 0x8 "BSEC_OTP_SWLOCK2,BSEC OTP shadow write sticky lock register 2" sif (cpuis("STM32MP13*")) hexmask.long 0x8 0.--31. 1. "SWLOCK,lock the writing for the OTP shadow word until next power-on reset." endif sif (cpuis("STM32MP153*")) hexmask.long 0x8 0.--31. 1. "SWLOCK,SWLOCK" newline endif sif (cpuis("STM32MP157*")) hexmask.long 0x8 0.--31. 1. "SWLOCK,SWLOCK" endif group.long 0x94++0xB line.long 0x0 "BSEC_OTP_SRLOCK0,BSEC OTP shadow read sticky lock register 0" sif (cpuis("STM32MP13*")) hexmask.long 0x0 0.--31. 1. "SRLOCK,prevent reloading of the shadow word from OTP until next power-on reset." endif sif (cpuis("STM32MP153*")) hexmask.long 0x0 0.--31. 1. "SRLOCK,SRLOCK" newline endif sif (cpuis("STM32MP157*")) hexmask.long 0x0 0.--31. 1. "SRLOCK,SRLOCK" endif line.long 0x4 "BSEC_OTP_SRLOCK1,BSEC OTP shadow read sticky lock register 1" sif (cpuis("STM32MP13*")) hexmask.long 0x4 0.--31. 1. "SRLOCK,prevent reloading of the shadow word from OTP until next power-on reset." endif sif (cpuis("STM32MP153*")) hexmask.long 0x4 0.--31. 1. "SRLOCK,SRLOCK" newline endif sif (cpuis("STM32MP157*")) hexmask.long 0x4 0.--31. 1. "SRLOCK,SRLOCK" endif line.long 0x8 "BSEC_OTP_SRLOCK2,BSEC OTP shadow read sticky lock register 2" sif (cpuis("STM32MP13*")) hexmask.long 0x8 0.--31. 1. "SRLOCK,prevent reloading of the shadow word from OTP until next power-on reset." endif sif (cpuis("STM32MP153*")) hexmask.long 0x8 0.--31. 1. "SRLOCK,SRLOCK" newline endif sif (cpuis("STM32MP157*")) hexmask.long 0x8 0.--31. 1. "SRLOCK,SRLOCK" endif group.long 0xAC++0xB line.long 0x0 "BSEC_JTAGIN,BSEC JTAG input register" sif (cpuis("STM32MP13*")) hexmask.long 0x0 0.--31. 1. "DATA,JTAG input data" endif sif (cpuis("STM32MP151*")) hexmask.long.word 0x0 0.--15. 1. "DATA,DATA" newline endif sif (cpuis("STM32MP153*")) hexmask.long.word 0x0 0.--15. 1. "DATA,DATA" endif sif (cpuis("STM32MP157*")) hexmask.long.word 0x0 0.--15. 1. "DATA,DATA" endif line.long 0x4 "BSEC_JTAGOUT,BSEC JTAG output register" sif (cpuis("STM32MP13*")) hexmask.long 0x4 0.--31. 1. "DATA,JTAG output data" endif sif (cpuis("STM32MP151*")) hexmask.long.word 0x4 0.--15. 1. "DATA,DATA" newline endif sif (cpuis("STM32MP153*")) hexmask.long.word 0x4 0.--15. 1. "DATA,DATA" endif sif (cpuis("STM32MP157*")) hexmask.long.word 0x4 0.--15. 1. "DATA,DATA" endif line.long 0x8 "BSEC_SCRATCH,BSEC scratch register" hexmask.long 0x8 0.--31. 1. "DATA,scratch data" group.long 0x200++0x17F line.long 0x0 "BSEC_OTP_DATA0,BSEC shadow register 0" hexmask.long 0x0 0.--31. 1. "DATA,shadow register read from OTP or written by software (OTP emulation mode)" line.long 0x4 "BSEC_OTP_DATA1,BSEC shadow register 1" hexmask.long 0x4 0.--31. 1. "DATA,shadow register read from OTP or written by software (OTP emulation mode)" line.long 0x8 "BSEC_OTP_DATA2,BSEC shadow register 2" hexmask.long 0x8 0.--31. 1. "DATA,shadow register read from OTP or written by software (OTP emulation mode)" line.long 0xC "BSEC_OTP_DATA3,BSEC shadow register 3" hexmask.long 0xC 0.--31. 1. "DATA,shadow register read from OTP or written by software (OTP emulation mode)" line.long 0x10 "BSEC_OTP_DATA4,BSEC shadow register 4" hexmask.long 0x10 0.--31. 1. "DATA,shadow register read from OTP or written by software (OTP emulation mode)" line.long 0x14 "BSEC_OTP_DATA5,BSEC shadow register 5" hexmask.long 0x14 0.--31. 1. "DATA,shadow register read from OTP or written by software (OTP emulation mode)" line.long 0x18 "BSEC_OTP_DATA6,BSEC shadow register 6" hexmask.long 0x18 0.--31. 1. "DATA,shadow register read from OTP or written by software (OTP emulation mode)" line.long 0x1C "BSEC_OTP_DATA7,BSEC shadow register 7" hexmask.long 0x1C 0.--31. 1. "DATA,shadow register read from OTP or written by software (OTP emulation mode)" line.long 0x20 "BSEC_OTP_DATA8,BSEC shadow register 8" hexmask.long 0x20 0.--31. 1. "DATA,shadow register read from OTP or written by software (OTP emulation mode)" line.long 0x24 "BSEC_OTP_DATA9,BSEC shadow register 9" hexmask.long 0x24 0.--31. 1. "DATA,shadow register read from OTP or written by software (OTP emulation mode)" line.long 0x28 "BSEC_OTP_DATA10,BSEC shadow register 10" hexmask.long 0x28 0.--31. 1. "DATA,shadow register read from OTP or written by software (OTP emulation mode)" line.long 0x2C "BSEC_OTP_DATA11,BSEC shadow register 11" hexmask.long 0x2C 0.--31. 1. "DATA,shadow register read from OTP or written by software (OTP emulation mode)" line.long 0x30 "BSEC_OTP_DATA12,BSEC shadow register 12" hexmask.long 0x30 0.--31. 1. "DATA,shadow register read from OTP or written by software (OTP emulation mode)" line.long 0x34 "BSEC_OTP_DATA13,BSEC shadow register 13" hexmask.long 0x34 0.--31. 1. "DATA,shadow register read from OTP or written by software (OTP emulation mode)" line.long 0x38 "BSEC_OTP_DATA14,BSEC shadow register 14" hexmask.long 0x38 0.--31. 1. "DATA,shadow register read from OTP or written by software (OTP emulation mode)" line.long 0x3C "BSEC_OTP_DATA15,BSEC shadow register 15" hexmask.long 0x3C 0.--31. 1. "DATA,shadow register read from OTP or written by software (OTP emulation mode)" line.long 0x40 "BSEC_OTP_DATA16,BSEC shadow register 16" hexmask.long 0x40 0.--31. 1. "DATA,shadow register read from OTP or written by software (OTP emulation mode)" line.long 0x44 "BSEC_OTP_DATA17,BSEC shadow register 17" hexmask.long 0x44 0.--31. 1. "DATA,shadow register read from OTP or written by software (OTP emulation mode)" line.long 0x48 "BSEC_OTP_DATA18,BSEC shadow register 18" hexmask.long 0x48 0.--31. 1. "DATA,shadow register read from OTP or written by software (OTP emulation mode)" line.long 0x4C "BSEC_OTP_DATA19,BSEC shadow register 19" hexmask.long 0x4C 0.--31. 1. "DATA,shadow register read from OTP or written by software (OTP emulation mode)" line.long 0x50 "BSEC_OTP_DATA20,BSEC shadow register 20" hexmask.long 0x50 0.--31. 1. "DATA,shadow register read from OTP or written by software (OTP emulation mode)" line.long 0x54 "BSEC_OTP_DATA21,BSEC shadow register 21" hexmask.long 0x54 0.--31. 1. "DATA,shadow register read from OTP or written by software (OTP emulation mode)" line.long 0x58 "BSEC_OTP_DATA22,BSEC shadow register 22" hexmask.long 0x58 0.--31. 1. "DATA,shadow register read from OTP or written by software (OTP emulation mode)" line.long 0x5C "BSEC_OTP_DATA23,BSEC shadow register 23" hexmask.long 0x5C 0.--31. 1. "DATA,shadow register read from OTP or written by software (OTP emulation mode)" line.long 0x60 "BSEC_OTP_DATA24,BSEC shadow register 24" hexmask.long 0x60 0.--31. 1. "DATA,shadow register read from OTP or written by software (OTP emulation mode)" line.long 0x64 "BSEC_OTP_DATA25,BSEC shadow register 25" hexmask.long 0x64 0.--31. 1. "DATA,shadow register read from OTP or written by software (OTP emulation mode)" line.long 0x68 "BSEC_OTP_DATA26,BSEC shadow register 26" hexmask.long 0x68 0.--31. 1. "DATA,shadow register read from OTP or written by software (OTP emulation mode)" line.long 0x6C "BSEC_OTP_DATA27,BSEC shadow register 27" hexmask.long 0x6C 0.--31. 1. "DATA,shadow register read from OTP or written by software (OTP emulation mode)" line.long 0x70 "BSEC_OTP_DATA28,BSEC shadow register 28" hexmask.long 0x70 0.--31. 1. "DATA,shadow register read from OTP or written by software (OTP emulation mode)" line.long 0x74 "BSEC_OTP_DATA29,BSEC shadow register 29" hexmask.long 0x74 0.--31. 1. "DATA,shadow register read from OTP or written by software (OTP emulation mode)" line.long 0x78 "BSEC_OTP_DATA30,BSEC shadow register 30" hexmask.long 0x78 0.--31. 1. "DATA,shadow register read from OTP or written by software (OTP emulation mode)" line.long 0x7C "BSEC_OTP_DATA31,BSEC shadow register 31" hexmask.long 0x7C 0.--31. 1. "DATA,shadow register read from OTP or written by software (OTP emulation mode)" line.long 0x80 "BSEC_OTP_DATA32,BSEC shadow register 32" hexmask.long 0x80 0.--31. 1. "DATA,shadow register read from OTP or written by software (OTP emulation mode)" line.long 0x84 "BSEC_OTP_DATA33,BSEC shadow register 33" hexmask.long 0x84 0.--31. 1. "DATA,shadow register read from OTP or written by software (OTP emulation mode)" line.long 0x88 "BSEC_OTP_DATA34,BSEC shadow register 34" hexmask.long 0x88 0.--31. 1. "DATA,shadow register read from OTP or written by software (OTP emulation mode)" line.long 0x8C "BSEC_OTP_DATA35,BSEC shadow register 35" hexmask.long 0x8C 0.--31. 1. "DATA,shadow register read from OTP or written by software (OTP emulation mode)" line.long 0x90 "BSEC_OTP_DATA36,BSEC shadow register 36" hexmask.long 0x90 0.--31. 1. "DATA,shadow register read from OTP or written by software (OTP emulation mode)" line.long 0x94 "BSEC_OTP_DATA37,BSEC shadow register 37" hexmask.long 0x94 0.--31. 1. "DATA,shadow register read from OTP or written by software (OTP emulation mode)" line.long 0x98 "BSEC_OTP_DATA38,BSEC shadow register 38" hexmask.long 0x98 0.--31. 1. "DATA,shadow register read from OTP or written by software (OTP emulation mode)" line.long 0x9C "BSEC_OTP_DATA39,BSEC shadow register 39" hexmask.long 0x9C 0.--31. 1. "DATA,shadow register read from OTP or written by software (OTP emulation mode)" line.long 0xA0 "BSEC_OTP_DATA40,BSEC shadow register 40" hexmask.long 0xA0 0.--31. 1. "DATA,shadow register read from OTP or written by software (OTP emulation mode)" line.long 0xA4 "BSEC_OTP_DATA41,BSEC shadow register 41" hexmask.long 0xA4 0.--31. 1. "DATA,shadow register read from OTP or written by software (OTP emulation mode)" line.long 0xA8 "BSEC_OTP_DATA42,BSEC shadow register 42" hexmask.long 0xA8 0.--31. 1. "DATA,shadow register read from OTP or written by software (OTP emulation mode)" line.long 0xAC "BSEC_OTP_DATA43,BSEC shadow register 43" hexmask.long 0xAC 0.--31. 1. "DATA,shadow register read from OTP or written by software (OTP emulation mode)" line.long 0xB0 "BSEC_OTP_DATA44,BSEC shadow register 44" hexmask.long 0xB0 0.--31. 1. "DATA,shadow register read from OTP or written by software (OTP emulation mode)" line.long 0xB4 "BSEC_OTP_DATA45,BSEC shadow register 45" hexmask.long 0xB4 0.--31. 1. "DATA,shadow register read from OTP or written by software (OTP emulation mode)" line.long 0xB8 "BSEC_OTP_DATA46,BSEC shadow register 46" hexmask.long 0xB8 0.--31. 1. "DATA,shadow register read from OTP or written by software (OTP emulation mode)" line.long 0xBC "BSEC_OTP_DATA47,BSEC shadow register 47" hexmask.long 0xBC 0.--31. 1. "DATA,shadow register read from OTP or written by software (OTP emulation mode)" line.long 0xC0 "BSEC_OTP_DATA48,BSEC shadow register 48" hexmask.long 0xC0 0.--31. 1. "DATA,shadow register read from OTP or written by software (OTP emulation mode)" line.long 0xC4 "BSEC_OTP_DATA49,BSEC shadow register 49" hexmask.long 0xC4 0.--31. 1. "DATA,shadow register read from OTP or written by software (OTP emulation mode)" line.long 0xC8 "BSEC_OTP_DATA50,BSEC shadow register 50" hexmask.long 0xC8 0.--31. 1. "DATA,shadow register read from OTP or written by software (OTP emulation mode)" line.long 0xCC "BSEC_OTP_DATA51,BSEC shadow register 51" hexmask.long 0xCC 0.--31. 1. "DATA,shadow register read from OTP or written by software (OTP emulation mode)" line.long 0xD0 "BSEC_OTP_DATA52,BSEC shadow register 52" hexmask.long 0xD0 0.--31. 1. "DATA,shadow register read from OTP or written by software (OTP emulation mode)" line.long 0xD4 "BSEC_OTP_DATA53,BSEC shadow register 53" hexmask.long 0xD4 0.--31. 1. "DATA,shadow register read from OTP or written by software (OTP emulation mode)" line.long 0xD8 "BSEC_OTP_DATA54,BSEC shadow register 54" hexmask.long 0xD8 0.--31. 1. "DATA,shadow register read from OTP or written by software (OTP emulation mode)" line.long 0xDC "BSEC_OTP_DATA55,BSEC shadow register 55" hexmask.long 0xDC 0.--31. 1. "DATA,shadow register read from OTP or written by software (OTP emulation mode)" line.long 0xE0 "BSEC_OTP_DATA56,BSEC shadow register 56" hexmask.long 0xE0 0.--31. 1. "DATA,shadow register read from OTP or written by software (OTP emulation mode)" line.long 0xE4 "BSEC_OTP_DATA57,BSEC shadow register 57" hexmask.long 0xE4 0.--31. 1. "DATA,shadow register read from OTP or written by software (OTP emulation mode)" line.long 0xE8 "BSEC_OTP_DATA58,BSEC shadow register 58" hexmask.long 0xE8 0.--31. 1. "DATA,shadow register read from OTP or written by software (OTP emulation mode)" line.long 0xEC "BSEC_OTP_DATA59,BSEC shadow register 59" hexmask.long 0xEC 0.--31. 1. "DATA,shadow register read from OTP or written by software (OTP emulation mode)" line.long 0xF0 "BSEC_OTP_DATA60,BSEC shadow register 60" hexmask.long 0xF0 0.--31. 1. "DATA,shadow register read from OTP or written by software (OTP emulation mode)" line.long 0xF4 "BSEC_OTP_DATA61,BSEC shadow register 61" hexmask.long 0xF4 0.--31. 1. "DATA,shadow register read from OTP or written by software (OTP emulation mode)" line.long 0xF8 "BSEC_OTP_DATA62,BSEC shadow register 62" hexmask.long 0xF8 0.--31. 1. "DATA,shadow register read from OTP or written by software (OTP emulation mode)" line.long 0xFC "BSEC_OTP_DATA63,BSEC shadow register 63" hexmask.long 0xFC 0.--31. 1. "DATA,shadow register read from OTP or written by software (OTP emulation mode)" line.long 0x100 "BSEC_OTP_DATA64,BSEC shadow register 64" hexmask.long 0x100 0.--31. 1. "DATA,shadow register read from OTP or written by software (OTP emulation mode)" line.long 0x104 "BSEC_OTP_DATA65,BSEC shadow register 65" hexmask.long 0x104 0.--31. 1. "DATA,shadow register read from OTP or written by software (OTP emulation mode)" line.long 0x108 "BSEC_OTP_DATA66,BSEC shadow register 66" hexmask.long 0x108 0.--31. 1. "DATA,shadow register read from OTP or written by software (OTP emulation mode)" line.long 0x10C "BSEC_OTP_DATA67,BSEC shadow register 67" hexmask.long 0x10C 0.--31. 1. "DATA,shadow register read from OTP or written by software (OTP emulation mode)" line.long 0x110 "BSEC_OTP_DATA68,BSEC shadow register 68" hexmask.long 0x110 0.--31. 1. "DATA,shadow register read from OTP or written by software (OTP emulation mode)" line.long 0x114 "BSEC_OTP_DATA69,BSEC shadow register 69" hexmask.long 0x114 0.--31. 1. "DATA,shadow register read from OTP or written by software (OTP emulation mode)" line.long 0x118 "BSEC_OTP_DATA70,BSEC shadow register 70" hexmask.long 0x118 0.--31. 1. "DATA,shadow register read from OTP or written by software (OTP emulation mode)" line.long 0x11C "BSEC_OTP_DATA71,BSEC shadow register 71" hexmask.long 0x11C 0.--31. 1. "DATA,shadow register read from OTP or written by software (OTP emulation mode)" line.long 0x120 "BSEC_OTP_DATA72,BSEC shadow register 72" hexmask.long 0x120 0.--31. 1. "DATA,shadow register read from OTP or written by software (OTP emulation mode)" line.long 0x124 "BSEC_OTP_DATA73,BSEC shadow register 73" hexmask.long 0x124 0.--31. 1. "DATA,shadow register read from OTP or written by software (OTP emulation mode)" line.long 0x128 "BSEC_OTP_DATA74,BSEC shadow register 74" hexmask.long 0x128 0.--31. 1. "DATA,shadow register read from OTP or written by software (OTP emulation mode)" line.long 0x12C "BSEC_OTP_DATA75,BSEC shadow register 75" hexmask.long 0x12C 0.--31. 1. "DATA,shadow register read from OTP or written by software (OTP emulation mode)" line.long 0x130 "BSEC_OTP_DATA76,BSEC shadow register 76" hexmask.long 0x130 0.--31. 1. "DATA,shadow register read from OTP or written by software (OTP emulation mode)" line.long 0x134 "BSEC_OTP_DATA77,BSEC shadow register 77" hexmask.long 0x134 0.--31. 1. "DATA,shadow register read from OTP or written by software (OTP emulation mode)" line.long 0x138 "BSEC_OTP_DATA78,BSEC shadow register 78" hexmask.long 0x138 0.--31. 1. "DATA,shadow register read from OTP or written by software (OTP emulation mode)" line.long 0x13C "BSEC_OTP_DATA79,BSEC shadow register 79" hexmask.long 0x13C 0.--31. 1. "DATA,shadow register read from OTP or written by software (OTP emulation mode)" line.long 0x140 "BSEC_OTP_DATA80,BSEC shadow register 80" hexmask.long 0x140 0.--31. 1. "DATA,shadow register read from OTP or written by software (OTP emulation mode)" line.long 0x144 "BSEC_OTP_DATA81,BSEC shadow register 81" hexmask.long 0x144 0.--31. 1. "DATA,shadow register read from OTP or written by software (OTP emulation mode)" line.long 0x148 "BSEC_OTP_DATA82,BSEC shadow register 82" hexmask.long 0x148 0.--31. 1. "DATA,shadow register read from OTP or written by software (OTP emulation mode)" line.long 0x14C "BSEC_OTP_DATA83,BSEC shadow register 83" hexmask.long 0x14C 0.--31. 1. "DATA,shadow register read from OTP or written by software (OTP emulation mode)" line.long 0x150 "BSEC_OTP_DATA84,BSEC shadow register 84" hexmask.long 0x150 0.--31. 1. "DATA,shadow register read from OTP or written by software (OTP emulation mode)" line.long 0x154 "BSEC_OTP_DATA85,BSEC shadow register 85" hexmask.long 0x154 0.--31. 1. "DATA,shadow register read from OTP or written by software (OTP emulation mode)" line.long 0x158 "BSEC_OTP_DATA86,BSEC shadow register 86" hexmask.long 0x158 0.--31. 1. "DATA,shadow register read from OTP or written by software (OTP emulation mode)" line.long 0x15C "BSEC_OTP_DATA87,BSEC shadow register 87" hexmask.long 0x15C 0.--31. 1. "DATA,shadow register read from OTP or written by software (OTP emulation mode)" line.long 0x160 "BSEC_OTP_DATA88,BSEC shadow register 88" hexmask.long 0x160 0.--31. 1. "DATA,shadow register read from OTP or written by software (OTP emulation mode)" line.long 0x164 "BSEC_OTP_DATA89,BSEC shadow register 89" hexmask.long 0x164 0.--31. 1. "DATA,shadow register read from OTP or written by software (OTP emulation mode)" line.long 0x168 "BSEC_OTP_DATA90,BSEC shadow register 90" hexmask.long 0x168 0.--31. 1. "DATA,shadow register read from OTP or written by software (OTP emulation mode)" line.long 0x16C "BSEC_OTP_DATA91,BSEC shadow register 91" hexmask.long 0x16C 0.--31. 1. "DATA,shadow register read from OTP or written by software (OTP emulation mode)" line.long 0x170 "BSEC_OTP_DATA92,BSEC shadow register 92" hexmask.long 0x170 0.--31. 1. "DATA,shadow register read from OTP or written by software (OTP emulation mode)" line.long 0x174 "BSEC_OTP_DATA93,BSEC shadow register 93" hexmask.long 0x174 0.--31. 1. "DATA,shadow register read from OTP or written by software (OTP emulation mode)" line.long 0x178 "BSEC_OTP_DATA94,BSEC shadow register 94" hexmask.long 0x178 0.--31. 1. "DATA,shadow register read from OTP or written by software (OTP emulation mode)" line.long 0x17C "BSEC_OTP_DATA95,BSEC shadow register 95" hexmask.long 0x17C 0.--31. 1. "DATA,shadow register read from OTP or written by software (OTP emulation mode)" group.long 0xFF0++0xF line.long 0x0 "BSEC_HWCFGR,BSEC hardware configuration register" sif (cpuis("STM32MP13*")) hexmask.long.byte 0x0 4.--7. 1. "ECC_USE,protection / redundancy scheme used" hexmask.long.byte 0x0 0.--3. 1. "SIZE,OTP block size" newline endif sif (cpuis("STM32MP151*")) hexmask.long.byte 0x0 4.--7. 1. "ECC_USE,ECC_USE" hexmask.long.byte 0x0 0.--3. 1. "SIZE,SIZE" newline endif sif (cpuis("STM32MP153*")) hexmask.long.byte 0x0 4.--7. 1. "ECC_USE,ECC_USE" hexmask.long.byte 0x0 0.--3. 1. "SIZE,SIZE" newline endif sif (cpuis("STM32MP157*")) hexmask.long.byte 0x0 4.--7. 1. "ECC_USE,ECC_USE" hexmask.long.byte 0x0 0.--3. 1. "SIZE,SIZE" endif line.long 0x4 "BSEC_VERR,BSEC version register" sif (cpuis("STM32MP13*")) hexmask.long.byte 0x4 4.--7. 1. "MAJREV,major revision information" hexmask.long.byte 0x4 0.--3. 1. "MINREV,minor revision information" newline endif sif (cpuis("STM32MP151*")) hexmask.long.byte 0x4 4.--7. 1. "MAJREV,MAJREV" hexmask.long.byte 0x4 0.--3. 1. "MINREV,MINREV" newline endif sif (cpuis("STM32MP153*")) hexmask.long.byte 0x4 4.--7. 1. "MAJREV,MAJREV" hexmask.long.byte 0x4 0.--3. 1. "MINREV,MINREV" newline endif sif (cpuis("STM32MP157*")) hexmask.long.byte 0x4 4.--7. 1. "MAJREV,MAJREV" hexmask.long.byte 0x4 0.--3. 1. "MINREV,MINREV" endif line.long 0x8 "BSEC_IPIDR,BSEC identification register" sif (cpuis("STM32MP13*")) hexmask.long 0x8 0.--31. 1. "ID,BSEC identification" endif sif (cpuis("STM32MP151*")) hexmask.long 0x8 0.--31. 1. "ID,ID" newline endif sif (cpuis("STM32MP153*")) hexmask.long 0x8 0.--31. 1. "ID,ID" endif sif (cpuis("STM32MP157*")) hexmask.long 0x8 0.--31. 1. "ID,ID" endif line.long 0xC "BSEC_SIDR,BSEC size identification register" sif (cpuis("STM32MP13*")) hexmask.long 0xC 0.--31. 1. "SID,BSEC size identification" endif sif (cpuis("STM32MP151*")) hexmask.long 0xC 0.--31. 1. "SID,SID" newline endif sif (cpuis("STM32MP153*")) hexmask.long 0xC 0.--31. 1. "SID,SID" endif sif (cpuis("STM32MP157*")) hexmask.long 0xC 0.--31. 1. "SID,SID" endif sif (cpuis("STM32MP151*")) rgroup.long 0xC++0x3 line.long 0x0 "BSEC_OTP_STATUS,BSEC OTP status register" endif sif (cpuis("STM32MP151*")) rgroup.long 0x1C++0x3 line.long 0x0 "BSEC_OTP_DISTURBED0,BSEC_OTP_DISTURBED0 is used to report disturbed state of BSEC_OTP_DATA0 to BSEC_OTP_DATA31 (lower 1Kbits OTP). BSEC_OTP_DISTURBED1 is used to report disturbed state of BSEC_OTP_DATA32 to BSEC_OTP_DATA63. BSEC_OTP_DISTURBED2 is used to.." endif sif (cpuis("STM32MP151*")) rgroup.long 0x20++0x3 line.long 0x0 "BSEC_OTP_DISTURBED1,BSEC_OTP_DISTURBED0 is used to report disturbed state of BSEC_OTP_DATA0 to BSEC_OTP_DATA31 (lower 1Kbits OTP). BSEC_OTP_DISTURBED1 is used to report disturbed state of BSEC_OTP_DATA32 to BSEC_OTP_DATA63. BSEC_OTP_DISTURBED2 is used to.." endif sif (cpuis("STM32MP151*")) rgroup.long 0x24++0x3 line.long 0x0 "BSEC_OTP_DISTURBED2,BSEC_OTP_DISTURBED0 is used to report disturbed state of BSEC_OTP_DATA0 to BSEC_OTP_DATA31 (lower 1Kbits OTP). BSEC_OTP_DISTURBED1 is used to report disturbed state of BSEC_OTP_DATA32 to BSEC_OTP_DATA63. BSEC_OTP_DISTURBED2 is used to.." endif sif (cpuis("STM32MP151*")) rgroup.long 0x34++0x3 line.long 0x0 "BSEC_OTP_ERROR0,BSEC_OTP_ERROR0 is used to report error state of BSEC_OTP_DATA0 to BSEC_OTP_DATA31 (lower 1Kbits OTP which are protected by 2:1 redundancy). BSEC_OTP_ERROR1 is used to report error state of BSEC_OTP_DATA32 to BSEC_OTP_DATA63 which are.." endif sif (cpuis("STM32MP151*")) rgroup.long 0x38++0x3 line.long 0x0 "BSEC_OTP_ERROR1,BSEC_OTP_ERROR0 is used to report error state of BSEC_OTP_DATA0 to BSEC_OTP_DATA31 (lower 1Kbits OTP which are protected by 2:1 redundancy). BSEC_OTP_ERROR1 is used to report error state of BSEC_OTP_DATA32 to BSEC_OTP_DATA63 which are.." endif sif (cpuis("STM32MP151*")) rgroup.long 0x3C++0x3 line.long 0x0 "BSEC_OTP_ERROR2,BSEC_OTP_ERROR0 is used to report error state of BSEC_OTP_DATA0 to BSEC_OTP_DATA31 (lower 1Kbits OTP which are protected by 2:1 redundancy). BSEC_OTP_ERROR1 is used to report error state of BSEC_OTP_DATA32 to BSEC_OTP_DATA63 which are.." endif sif (cpuis("STM32MP151*")) rgroup.long 0x4C++0x3 line.long 0x0 "BSEC_OTP_WRLOCK0,BSEC_OTP_WLOCK0 is used to report permanent write lock of BSEC_OTP_DATA0 to BSEC_OTP_DATA31. BSEC_OTP_WLOCK1 is used to report permanent write lock of BSEC_OTP_DATA32 to BSEC_OTP_DATA63. BSEC_OTP_WLOCK2 is used to report permanent write.." endif sif (cpuis("STM32MP151*")) rgroup.long 0x50++0x3 line.long 0x0 "BSEC_OTP_WRLOCK1,BSEC_OTP_WLOCK0 is used to report permanent write lock of BSEC_OTP_DATA0 to BSEC_OTP_DATA31. BSEC_OTP_WLOCK1 is used to report permanent write lock of BSEC_OTP_DATA32 to BSEC_OTP_DATA63. BSEC_OTP_WLOCK2 is used to report permanent write.." endif sif (cpuis("STM32MP151*")) rgroup.long 0x54++0x3 line.long 0x0 "BSEC_OTP_WRLOCK2,BSEC_OTP_WLOCK0 is used to report permanent write lock of BSEC_OTP_DATA0 to BSEC_OTP_DATA31. BSEC_OTP_WLOCK1 is used to report permanent write lock of BSEC_OTP_DATA32 to BSEC_OTP_DATA63. BSEC_OTP_WLOCK2 is used to report permanent write.." endif sif (cpuis("STM32MP151*")) rgroup.long 0xAC++0x3 line.long 0x0 "BSEC_JTAGIN,BSEC JTAG input register" endif sif (cpuis("STM32MP151*")) rgroup.long 0xFF0++0x3 line.long 0x0 "BSEC_HWCFGR,BSEC hardware configuration register" endif sif (cpuis("STM32MP151*")) rgroup.long 0xFF4++0x3 line.long 0x0 "BSEC_VERR,BSEC version register" endif sif (cpuis("STM32MP151*")) rgroup.long 0xFF8++0x3 line.long 0x0 "BSEC_IPIDR,BSEC identification register" endif sif (cpuis("STM32MP151*")) rgroup.long 0xFFC++0x3 line.long 0x0 "BSEC_SIDR,BSEC size identification register" endif sif (cpuis("STM32MP153*")) rgroup.long 0xC++0x3 line.long 0x0 "BSEC_OTP_STATUS,BSEC OTP status register" endif sif (cpuis("STM32MP153*")) rgroup.long 0x1C++0x3 line.long 0x0 "BSEC_OTP_DISTURBED0,BSEC_OTP_DISTURBED0 is used to report disturbed state of BSEC_OTP_DATA0 to BSEC_OTP_DATA31 (lower 1Kbits OTP). BSEC_OTP_DISTURBED1 is used to report disturbed state of BSEC_OTP_DATA32 to BSEC_OTP_DATA63. BSEC_OTP_DISTURBED2 is used to.." endif sif (cpuis("STM32MP153*")) rgroup.long 0x20++0x3 line.long 0x0 "BSEC_OTP_DISTURBED1,BSEC_OTP_DISTURBED0 is used to report disturbed state of BSEC_OTP_DATA0 to BSEC_OTP_DATA31 (lower 1Kbits OTP). BSEC_OTP_DISTURBED1 is used to report disturbed state of BSEC_OTP_DATA32 to BSEC_OTP_DATA63. BSEC_OTP_DISTURBED2 is used to.." endif sif (cpuis("STM32MP153*")) rgroup.long 0x24++0x3 line.long 0x0 "BSEC_OTP_DISTURBED2,BSEC_OTP_DISTURBED0 is used to report disturbed state of BSEC_OTP_DATA0 to BSEC_OTP_DATA31 (lower 1Kbits OTP). BSEC_OTP_DISTURBED1 is used to report disturbed state of BSEC_OTP_DATA32 to BSEC_OTP_DATA63. BSEC_OTP_DISTURBED2 is used to.." endif sif (cpuis("STM32MP153*")) rgroup.long 0x34++0x3 line.long 0x0 "BSEC_OTP_ERROR0,BSEC_OTP_ERROR0 is used to report error state of BSEC_OTP_DATA0 to BSEC_OTP_DATA31 (lower 1Kbits OTP which are protected by 2:1 redundancy). BSEC_OTP_ERROR1 is used to report error state of BSEC_OTP_DATA32 to BSEC_OTP_DATA63 which are.." endif sif (cpuis("STM32MP153*")) rgroup.long 0x38++0x3 line.long 0x0 "BSEC_OTP_ERROR1,BSEC_OTP_ERROR0 is used to report error state of BSEC_OTP_DATA0 to BSEC_OTP_DATA31 (lower 1Kbits OTP which are protected by 2:1 redundancy). BSEC_OTP_ERROR1 is used to report error state of BSEC_OTP_DATA32 to BSEC_OTP_DATA63 which are.." endif sif (cpuis("STM32MP153*")) rgroup.long 0x3C++0x3 line.long 0x0 "BSEC_OTP_ERROR2,BSEC_OTP_ERROR0 is used to report error state of BSEC_OTP_DATA0 to BSEC_OTP_DATA31 (lower 1Kbits OTP which are protected by 2:1 redundancy). BSEC_OTP_ERROR1 is used to report error state of BSEC_OTP_DATA32 to BSEC_OTP_DATA63 which are.." endif sif (cpuis("STM32MP153*")) rgroup.long 0x4C++0x3 line.long 0x0 "BSEC_OTP_WRLOCK0,BSEC_OTP_WLOCK0 is used to report permanent write lock of BSEC_OTP_DATA0 to BSEC_OTP_DATA31. BSEC_OTP_WLOCK1 is used to report permanent write lock of BSEC_OTP_DATA32 to BSEC_OTP_DATA63. BSEC_OTP_WLOCK2 is used to report permanent write.." endif sif (cpuis("STM32MP153*")) rgroup.long 0x50++0x3 line.long 0x0 "BSEC_OTP_WRLOCK1,BSEC_OTP_WLOCK0 is used to report permanent write lock of BSEC_OTP_DATA0 to BSEC_OTP_DATA31. BSEC_OTP_WLOCK1 is used to report permanent write lock of BSEC_OTP_DATA32 to BSEC_OTP_DATA63. BSEC_OTP_WLOCK2 is used to report permanent write.." endif sif (cpuis("STM32MP153*")) rgroup.long 0x54++0x3 line.long 0x0 "BSEC_OTP_WRLOCK2,BSEC_OTP_WLOCK0 is used to report permanent write lock of BSEC_OTP_DATA0 to BSEC_OTP_DATA31. BSEC_OTP_WLOCK1 is used to report permanent write lock of BSEC_OTP_DATA32 to BSEC_OTP_DATA63. BSEC_OTP_WLOCK2 is used to report permanent write.." endif sif (cpuis("STM32MP153*")) rgroup.long 0xAC++0x3 line.long 0x0 "BSEC_JTAGIN,BSEC JTAG input register" endif sif (cpuis("STM32MP153*")) rgroup.long 0xFF0++0x3 line.long 0x0 "BSEC_HWCFGR,BSEC hardware configuration register" endif sif (cpuis("STM32MP153*")) rgroup.long 0xFF4++0x3 line.long 0x0 "BSEC_VERR,BSEC version register" endif sif (cpuis("STM32MP153*")) rgroup.long 0xFF8++0x3 line.long 0x0 "BSEC_IPIDR,BSEC identification register" endif sif (cpuis("STM32MP153*")) rgroup.long 0xFFC++0x3 line.long 0x0 "BSEC_SIDR,BSEC size identification register" endif sif (cpuis("STM32MP157*")) rgroup.long 0xC++0x3 line.long 0x0 "BSEC_OTP_STATUS,BSEC OTP status register" endif sif (cpuis("STM32MP157*")) rgroup.long 0x1C++0x3 line.long 0x0 "BSEC_OTP_DISTURBED0,BSEC_OTP_DISTURBED0 is used to report disturbed state of BSEC_OTP_DATA0 to BSEC_OTP_DATA31 (lower 1Kbits OTP). BSEC_OTP_DISTURBED1 is used to report disturbed state of BSEC_OTP_DATA32 to BSEC_OTP_DATA63. BSEC_OTP_DISTURBED2 is used to.." endif sif (cpuis("STM32MP157*")) rgroup.long 0x20++0x3 line.long 0x0 "BSEC_OTP_DISTURBED1,BSEC_OTP_DISTURBED0 is used to report disturbed state of BSEC_OTP_DATA0 to BSEC_OTP_DATA31 (lower 1Kbits OTP). BSEC_OTP_DISTURBED1 is used to report disturbed state of BSEC_OTP_DATA32 to BSEC_OTP_DATA63. BSEC_OTP_DISTURBED2 is used to.." endif sif (cpuis("STM32MP157*")) rgroup.long 0x24++0x3 line.long 0x0 "BSEC_OTP_DISTURBED2,BSEC_OTP_DISTURBED0 is used to report disturbed state of BSEC_OTP_DATA0 to BSEC_OTP_DATA31 (lower 1Kbits OTP). BSEC_OTP_DISTURBED1 is used to report disturbed state of BSEC_OTP_DATA32 to BSEC_OTP_DATA63. BSEC_OTP_DISTURBED2 is used to.." endif sif (cpuis("STM32MP157*")) rgroup.long 0x34++0x3 line.long 0x0 "BSEC_OTP_ERROR0,BSEC_OTP_ERROR0 is used to report error state of BSEC_OTP_DATA0 to BSEC_OTP_DATA31 (lower 1Kbits OTP which are protected by 2:1 redundancy). BSEC_OTP_ERROR1 is used to report error state of BSEC_OTP_DATA32 to BSEC_OTP_DATA63 which are.." endif sif (cpuis("STM32MP157*")) rgroup.long 0x38++0x3 line.long 0x0 "BSEC_OTP_ERROR1,BSEC_OTP_ERROR0 is used to report error state of BSEC_OTP_DATA0 to BSEC_OTP_DATA31 (lower 1Kbits OTP which are protected by 2:1 redundancy). BSEC_OTP_ERROR1 is used to report error state of BSEC_OTP_DATA32 to BSEC_OTP_DATA63 which are.." endif sif (cpuis("STM32MP157*")) rgroup.long 0x3C++0x3 line.long 0x0 "BSEC_OTP_ERROR2,BSEC_OTP_ERROR0 is used to report error state of BSEC_OTP_DATA0 to BSEC_OTP_DATA31 (lower 1Kbits OTP which are protected by 2:1 redundancy). BSEC_OTP_ERROR1 is used to report error state of BSEC_OTP_DATA32 to BSEC_OTP_DATA63 which are.." endif sif (cpuis("STM32MP157*")) rgroup.long 0x4C++0x3 line.long 0x0 "BSEC_OTP_WRLOCK0,BSEC_OTP_WLOCK0 is used to report permanent write lock of BSEC_OTP_DATA0 to BSEC_OTP_DATA31. BSEC_OTP_WLOCK1 is used to report permanent write lock of BSEC_OTP_DATA32 to BSEC_OTP_DATA63. BSEC_OTP_WLOCK2 is used to report permanent write.." endif sif (cpuis("STM32MP157*")) rgroup.long 0x50++0x3 line.long 0x0 "BSEC_OTP_WRLOCK1,BSEC_OTP_WLOCK0 is used to report permanent write lock of BSEC_OTP_DATA0 to BSEC_OTP_DATA31. BSEC_OTP_WLOCK1 is used to report permanent write lock of BSEC_OTP_DATA32 to BSEC_OTP_DATA63. BSEC_OTP_WLOCK2 is used to report permanent write.." endif sif (cpuis("STM32MP157*")) rgroup.long 0x54++0x3 line.long 0x0 "BSEC_OTP_WRLOCK2,BSEC_OTP_WLOCK0 is used to report permanent write lock of BSEC_OTP_DATA0 to BSEC_OTP_DATA31. BSEC_OTP_WLOCK1 is used to report permanent write lock of BSEC_OTP_DATA32 to BSEC_OTP_DATA63. BSEC_OTP_WLOCK2 is used to report permanent write.." endif sif (cpuis("STM32MP157*")) rgroup.long 0xAC++0x3 line.long 0x0 "BSEC_JTAGIN,BSEC JTAG input register" endif sif (cpuis("STM32MP157*")) rgroup.long 0xFF0++0x3 line.long 0x0 "BSEC_HWCFGR,BSEC hardware configuration register" endif sif (cpuis("STM32MP157*")) rgroup.long 0xFF4++0x3 line.long 0x0 "BSEC_VERR,BSEC version register" endif sif (cpuis("STM32MP157*")) rgroup.long 0xFF8++0x3 line.long 0x0 "BSEC_IPIDR,BSEC identification register" endif sif (cpuis("STM32MP157*")) rgroup.long 0xFFC++0x3 line.long 0x0 "BSEC_SIDR,BSEC size identification register" endif tree.end tree "CCU (Clock Calibration Unit)" base ad:0x44010000 sif (cpuis("STM32MP13*")) rgroup.long 0x0++0x3 line.long 0x0 "CCU_CREL,Clock calibration unit core release register" hexmask.long.byte 0x0 28.--31. 1. "REL,Core release = 1" hexmask.long.byte 0x0 24.--27. 1. "STEP,Step of core release = 1" newline hexmask.long.byte 0x0 20.--23. 1. "SUBSTEP,Sub-step of core release = 1" hexmask.long.byte 0x0 16.--19. 1. "YEAR,Timestamp year =" newline hexmask.long.byte 0x0 8.--15. 1. "MON,Timestamp month = 12" hexmask.long.byte 0x0 0.--7. 1. "DAY,Timestamp day = 18" group.long 0x4++0x3 line.long 0x0 "CCU_CCFG,Calibration configuration register" bitfld.long 0x0 31. "SWR,Software reset" "0,1" hexmask.long.byte 0x0 16.--19. 1. "CDIV,Clock divider" newline hexmask.long.byte 0x0 8.--15. 1. "OCPM,Oscillator clock periods minimum" bitfld.long 0x0 7. "CFL,Calibration field length" "0: Calibration field length is 32 bits,1: Calibration field length is 64 bits" newline bitfld.long 0x0 6. "BCC,Bypass clock calibration" "0: Clock calibration unit generates time quanta clock,1: Clock calibration unit bypassed (default.." hexmask.long.byte 0x0 0.--4. 1. "TQBT,Time quanta per bit time" rgroup.long 0x8++0x3 line.long 0x0 "CCU_CSTAT,Calibration status register" bitfld.long 0x0 30.--31. "CALS,Calibration state" "0: Not_Calibrated,1: Basic_Calibrated,2: Precision_Calibrated,?" hexmask.long.word 0x0 18.--28. 1. "TQC,Time quanta counter" newline hexmask.long.tbyte 0x0 0.--17. 1. "OCPC,Oscillator clock period counter" group.long 0xC++0xB line.long 0x0 "CCU_CWD,Calibration watchdog register" hexmask.long.word 0x0 16.--31. 1. "WDV,Watchdog value" hexmask.long.word 0x0 0.--15. 1. "WDC,WDC" line.long 0x4 "CCU_IR,Clock calibration unit interrupt register" bitfld.long 0x4 1. "CSC,Calibration state changed" "0: Calibration state unchanged,1: Calibration state has changed" bitfld.long 0x4 0. "CWE,Calibration watchdog event" "0: No calibration watchdog event,1: Calibration watchdog event occurred" line.long 0x8 "CCU_IE,Clock calibration unit interrupt enable register" bitfld.long 0x8 1. "CSCE,Calibration state changed enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x8 0. "CWEE,Calibration watchdog event enable" "0: Interrupt disabled,1: Interrupt enabled" endif sif (cpuis("STM32MP151*")) rgroup.long 0x0++0x3 line.long 0x0 "FCCAN_CCU_CREL,Clock calibration unit core release register" hexmask.long.byte 0x0 28.--31. 1. "REL,REL" hexmask.long.byte 0x0 24.--27. 1. "STEP,STEP" newline hexmask.long.byte 0x0 20.--23. 1. "SUBSTEP,SUBSTEP" hexmask.long.byte 0x0 16.--19. 1. "YEAR,YEAR" newline hexmask.long.byte 0x0 8.--15. 1. "MON,MON" hexmask.long.byte 0x0 0.--7. 1. "DAY,DAY" group.long 0x4++0x3 line.long 0x0 "FCCAN_CCU_CCFG,Calibration configuration register" bitfld.long 0x0 31. "SWR,SWR" "0,1" hexmask.long.byte 0x0 16.--19. 1. "CDIV,CDIV" newline hexmask.long.byte 0x0 8.--15. 1. "OCPM,OCPM" bitfld.long 0x0 7. "CFL,CFL" "0,1" newline bitfld.long 0x0 6. "BCC,BCC" "0,1" hexmask.long.byte 0x0 0.--4. 1. "TQBT,TQBT" rgroup.long 0x8++0x3 line.long 0x0 "FCCAN_CCU_CSTAT,Calibration status register" bitfld.long 0x0 30.--31. "CALS,CALS" "0,1,2,3" hexmask.long.word 0x0 18.--28. 1. "TQC,TQC" newline hexmask.long.tbyte 0x0 0.--17. 1. "OCPC,OCPC" group.long 0xC++0xB line.long 0x0 "FCCAN_CCU_CWD,The calibration watchdog is started after the first falling edge when the calibration FSM is in state Not_Calibrated (CCU_CSTAT.CALS = 00). In this state the calibration watchdog monitors the message received. In case no message was.." hexmask.long.word 0x0 16.--31. 1. "WDV,WDV" hexmask.long.word 0x0 0.--15. 1. "WDC,WDC" line.long 0x4 "FCCAN_CCU_IR,The flags are set when one of the listed conditions is detected (edge-sensitive). The flags remain set until the Host clears them. A flag is cleared by writing a 1 to the corresponding bit position. Writing a 0 has no effect. A hard reset.." bitfld.long 0x4 1. "CSC,CSC" "0,1" bitfld.long 0x4 0. "CWE,CWE" "0,1" line.long 0x8 "FCCAN_CCU_IE,The settings in the CU interrupt enable register determine whether a status change in the CU interrupt register will be signaled on an interrupt line." bitfld.long 0x8 1. "CSCE,CSCE" "0,1" bitfld.long 0x8 0. "CWEE,CWEE" "0,1" endif sif (cpuis("STM32MP153*")) rgroup.long 0x0++0x3 line.long 0x0 "FCCAN_CCU_CREL,Clock calibration unit core release register" hexmask.long.byte 0x0 28.--31. 1. "REL,REL" hexmask.long.byte 0x0 24.--27. 1. "STEP,STEP" newline hexmask.long.byte 0x0 20.--23. 1. "SUBSTEP,SUBSTEP" hexmask.long.byte 0x0 16.--19. 1. "YEAR,YEAR" newline hexmask.long.byte 0x0 8.--15. 1. "MON,MON" hexmask.long.byte 0x0 0.--7. 1. "DAY,DAY" group.long 0x4++0x3 line.long 0x0 "FCCAN_CCU_CCFG,Calibration configuration register" bitfld.long 0x0 31. "SWR,SWR" "0,1" hexmask.long.byte 0x0 16.--19. 1. "CDIV,CDIV" newline hexmask.long.byte 0x0 8.--15. 1. "OCPM,OCPM" bitfld.long 0x0 7. "CFL,CFL" "0,1" newline bitfld.long 0x0 6. "BCC,BCC" "0,1" hexmask.long.byte 0x0 0.--4. 1. "TQBT,TQBT" rgroup.long 0x8++0x3 line.long 0x0 "FCCAN_CCU_CSTAT,Calibration status register" bitfld.long 0x0 30.--31. "CALS,CALS" "0,1,2,3" hexmask.long.word 0x0 18.--28. 1. "TQC,TQC" newline hexmask.long.tbyte 0x0 0.--17. 1. "OCPC,OCPC" group.long 0xC++0xB line.long 0x0 "FCCAN_CCU_CWD,The calibration watchdog is started after the first falling edge when the calibration FSM is in state Not_Calibrated (CCU_CSTAT.CALS = 00). In this state the calibration watchdog monitors the message received. In case no message was.." hexmask.long.word 0x0 16.--31. 1. "WDV,WDV" hexmask.long.word 0x0 0.--15. 1. "WDC,WDC" line.long 0x4 "FCCAN_CCU_IR,The flags are set when one of the listed conditions is detected (edge-sensitive). The flags remain set until the Host clears them. A flag is cleared by writing a 1 to the corresponding bit position. Writing a 0 has no effect. A hard reset.." bitfld.long 0x4 1. "CSC,CSC" "0,1" bitfld.long 0x4 0. "CWE,CWE" "0,1" line.long 0x8 "FCCAN_CCU_IE,The settings in the CU interrupt enable register determine whether a status change in the CU interrupt register will be signaled on an interrupt line." bitfld.long 0x8 1. "CSCE,CSCE" "0,1" bitfld.long 0x8 0. "CWEE,CWEE" "0,1" endif sif (cpuis("STM32MP157*")) rgroup.long 0x0++0x3 line.long 0x0 "FCCAN_CCU_CREL,Clock calibration unit core release register" hexmask.long.byte 0x0 28.--31. 1. "REL,REL" hexmask.long.byte 0x0 24.--27. 1. "STEP,STEP" newline hexmask.long.byte 0x0 20.--23. 1. "SUBSTEP,SUBSTEP" hexmask.long.byte 0x0 16.--19. 1. "YEAR,YEAR" newline hexmask.long.byte 0x0 8.--15. 1. "MON,MON" hexmask.long.byte 0x0 0.--7. 1. "DAY,DAY" group.long 0x4++0x3 line.long 0x0 "FCCAN_CCU_CCFG,Calibration configuration register" bitfld.long 0x0 31. "SWR,SWR" "0,1" hexmask.long.byte 0x0 16.--19. 1. "CDIV,CDIV" newline hexmask.long.byte 0x0 8.--15. 1. "OCPM,OCPM" bitfld.long 0x0 7. "CFL,CFL" "0,1" newline bitfld.long 0x0 6. "BCC,BCC" "0,1" hexmask.long.byte 0x0 0.--4. 1. "TQBT,TQBT" rgroup.long 0x8++0x3 line.long 0x0 "FCCAN_CCU_CSTAT,Calibration status register" bitfld.long 0x0 30.--31. "CALS,CALS" "0,1,2,3" hexmask.long.word 0x0 18.--28. 1. "TQC,TQC" newline hexmask.long.tbyte 0x0 0.--17. 1. "OCPC,OCPC" group.long 0xC++0xB line.long 0x0 "FCCAN_CCU_CWD,The calibration watchdog is started after the first falling edge when the calibration FSM is in state Not_Calibrated (CCU_CSTAT.CALS = 00). In this state the calibration watchdog monitors the message received. In case no message was.." hexmask.long.word 0x0 16.--31. 1. "WDV,WDV" hexmask.long.word 0x0 0.--15. 1. "WDC,WDC" line.long 0x4 "FCCAN_CCU_IR,The flags are set when one of the listed conditions is detected (edge-sensitive). The flags remain set until the Host clears them. A flag is cleared by writing a 1 to the corresponding bit position. Writing a 0 has no effect. A hard reset.." bitfld.long 0x4 1. "CSC,CSC" "0,1" bitfld.long 0x4 0. "CWE,CWE" "0,1" line.long 0x8 "FCCAN_CCU_IE,The settings in the CU interrupt enable register determine whether a status change in the CU interrupt register will be signaled on an interrupt line." bitfld.long 0x8 1. "CSCE,CSCE" "0,1" bitfld.long 0x8 0. "CWEE,CWEE" "0,1" endif tree.end tree "CRC (Cyclic Redundancy Check Calculation Unit)" base ad:0x0 sif (cpuis("STM32MP13*")) tree "CRC" base ad:0x58009000 group.long 0x0++0xB line.long 0x0 "CRC_DR,CRC data register" hexmask.long 0x0 0.--31. 1. "DR,Data register bits" line.long 0x4 "CRC_IDR,CRC independent data register" hexmask.long 0x4 0.--31. 1. "IDR,General-purpose 32-bit data register bits" line.long 0x8 "CRC_CR,CRC control register" bitfld.long 0x8 7. "REV_OUT,Reverse output data" "0: Bit order not affected,1: Bit-reversed output format" bitfld.long 0x8 5.--6. "REV_IN,Reverse input data" "0: Bit order not affected,1: Bit reversal done by byte,2: Bit reversal done by half-word,3: Bit reversal done by word" bitfld.long 0x8 3.--4. "POLYSIZE,Polynomial size" "0: 32 bit polynomial,1: 16 bit polynomial,2: 8 bit polynomial,3: 7 bit polynomial" bitfld.long 0x8 0. "RESET,RESET bit" "0,1" group.long 0x10++0x7 line.long 0x0 "CRC_INIT,CRC initial value" hexmask.long 0x0 0.--31. 1. "CRC_INIT,Programmable initial CRC value" line.long 0x4 "CRC_POL,CRC polynomial" hexmask.long 0x4 0.--31. 1. "POL,Programmable polynomial" tree.end endif sif (cpuis("STM32MP151*")||cpuis("STM32MP153*")||cpuis("STM32MP157*")) tree "CRC1" base ad:0x58009000 group.long 0x0++0xB line.long 0x0 "CRC_DR,CRC data register" hexmask.long 0x0 0.--31. 1. "DR,DR" line.long 0x4 "CRC_IDR,CRC independent data register" hexmask.long 0x4 0.--31. 1. "IDR,IDR" line.long 0x8 "CRC_CR,CRC control register" bitfld.long 0x8 7. "REV_OUT,REV_OUT" "0,1" bitfld.long 0x8 5.--6. "REV_IN,REV_IN" "0,1,2,3" bitfld.long 0x8 3.--4. "POLYSIZE,POLYSIZE" "0,1,2,3" bitfld.long 0x8 0. "RESET,RESET" "0,1" group.long 0x10++0x7 line.long 0x0 "CRC_INIT,CRC initial value" hexmask.long 0x0 0.--31. 1. "CRC_INIT,CRC_INIT" line.long 0x4 "CRC_POL,CRC polynomial" hexmask.long 0x4 0.--31. 1. "POL,POL" tree.end endif sif (cpuis("STM32MP151*")||cpuis("STM32MP153*")||cpuis("STM32MP157*")) tree "CRC2" base ad:0x4C004000 group.long 0x0++0xB line.long 0x0 "CRC_DR,CRC data register" hexmask.long 0x0 0.--31. 1. "DR,DR" line.long 0x4 "CRC_IDR,CRC independent data register" hexmask.long 0x4 0.--31. 1. "IDR,IDR" line.long 0x8 "CRC_CR,CRC control register" bitfld.long 0x8 7. "REV_OUT,REV_OUT" "0,1" bitfld.long 0x8 5.--6. "REV_IN,REV_IN" "0,1,2,3" bitfld.long 0x8 3.--4. "POLYSIZE,POLYSIZE" "0,1,2,3" bitfld.long 0x8 0. "RESET,RESET" "0,1" group.long 0x10++0x7 line.long 0x0 "CRC_INIT,CRC initial value" hexmask.long 0x0 0.--31. 1. "CRC_INIT,CRC_INIT" line.long 0x4 "CRC_POL,CRC polynomial" hexmask.long 0x4 0.--31. 1. "POL,POL" tree.end endif tree.end tree "CRYP (Cryptographic Processor)" base ad:0x0 sif (cpuis("STM32MP13*")) tree "CRYP" base ad:0x54002000 group.long 0x0++0x3 line.long 0x0 "CRYP_CR," bitfld.long 0x0 31. "IPRST,CRYP software reset" "0,1" bitfld.long 0x0 25. "KMOD1,Key mode selection" "0,1" newline bitfld.long 0x0 24. "KMOD0,Key mode selection" "0,1" hexmask.long.byte 0x0 20.--23. 1. "NPBLB,Number of Padding Bytes in Last Block of payload." newline bitfld.long 0x0 19. "ALGOMODE3,Algorithm mode" "0,1" bitfld.long 0x0 16.--17. "GCM_CCMPH,GCM or CCM Phase selection" "0: Initialization phase,1: Header phase,2: Payload phase,3: Final phase" newline bitfld.long 0x0 15. "CRYPEN,CRYP processor Enable" "0: Cryptographic processor peripheral is disabled,1: Cryptographic processor peripheral is enabled" bitfld.long 0x0 14. "FFLUSH,CRYP FIFO Flush" "0: No FIFO flush,1: FIFO flush enabled" newline bitfld.long 0x0 8.--9. "KEYSIZE,Key size selection (AES mode only)" "0: 128-bit key length,1: 192-bit key length,2: 256-bit key length,3: Reserved do not use this value" bitfld.long 0x0 6.--7. "DATATYPE,Data Type selection" "0: 32-bit data. No swapping for each word. First..,1: 16-bit data or half-word. Each word pushed into..,2: 8-bit data or bytes. Each word pushed into the..,3: bit data or bit-string. Each word pushed into.." newline bitfld.long 0x0 3.--5. "ALGOMODE,Algorithm mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 2. "ALGODIR,Algorithm Direction" "0: Encrypt,1: Decrypt" rgroup.long 0x4++0x3 line.long 0x0 "CRYP_SR," bitfld.long 0x0 7. "KEYVALID,Key valid" "0: No valid key information is available in key..,1: Valid key information defined by KEYSIZE in.." bitfld.long 0x0 6. "KERF,Key error flag" "0: No key error detected,1: Key information failed to load into key registers" newline bitfld.long 0x0 4. "BUSY,Busy bit" "0: The CRYP core is not processing any data. The..,1: The CRYP core is currently processing a block of.." bitfld.long 0x0 3. "OFFU,Output FIFO full flag" "0: Output FIFO is not full,1: Output FIFO is full" newline bitfld.long 0x0 2. "OFNE,Output FIFO not empty flag" "0: Output FIFO is empty,1: Output FIFO is not empty" bitfld.long 0x0 1. "IFNF,Input FIFO not full flag" "0: Input FIFO is full,1: Input FIFO is not full" newline bitfld.long 0x0 0. "IFEM,Input FIFO empty flag" "0: Input FIFO is not empty,1: Input FIFO is empty" group.long 0x8++0x3 line.long 0x0 "CRYP_DIN,CRYP data input register" hexmask.long 0x0 0.--31. 1. "DATAIN,Data Input" rgroup.long 0xC++0x3 line.long 0x0 "CRYP_DOUT,CRYP data output register" hexmask.long 0x0 0.--31. 1. "DATAOUT,Data Output" group.long 0x10++0x7 line.long 0x0 "CRYP_DMACR," bitfld.long 0x0 1. "DOEN,DMA Output Enable" "0: DMA for outgoing data transfer is disabled,1: DMA for outgoing data transfer is enabled" bitfld.long 0x0 0. "DIEN,DMA Input Enable" "0: DMA for incoming data transfer is disabled,1: DMA for incoming data transfer is enabled" line.long 0x4 "CRYP_IMSCR,CRYP interrupt mask set/clear register" bitfld.long 0x4 1. "OUTIM,Output FIFO service interrupt mask" "0: Output FIFO service interrupt is masked,1: Output FIFO service interrupt is not masked" bitfld.long 0x4 0. "INIM,Input FIFO service interrupt mask" "0: Input FIFO service interrupt is masked,1: Input FIFO service interrupt is not masked" rgroup.long 0x18++0x7 line.long 0x0 "CRYP_RISR,CRYP raw interrupt status register" bitfld.long 0x0 1. "OUTRIS,Output FIFO service raw interrupt status" "0: Raw interrupt not pending,1: Raw interrupt pending" bitfld.long 0x0 0. "INRIS,Input FIFO service raw interrupt status" "0: Raw interrupt not pending,1: Raw interrupt pending" line.long 0x4 "CRYP_MISR,CRYP masked interrupt status register" bitfld.long 0x4 1. "OUTMIS,Output FIFO service masked interrupt status" "0: Interrupt not pending,1: Interrupt pending" bitfld.long 0x4 0. "INMIS,Input FIFO service masked interrupt status" "0: Interrupt not pending,1: Interrupt pending when CRYPEN = 1" wgroup.long 0x20++0x1F line.long 0x0 "CRYP_K0LR,CRYP key register 0L" hexmask.long 0x0 0.--31. 1. "K,Key bit x (x =  255 to 224)" line.long 0x4 "CRYP_K0RR,CRYP key register 0R" hexmask.long 0x4 0.--31. 1. "K,Key bit x (x =  223 to 192)" line.long 0x8 "CRYP_K1LR,CRYP key register 1L" hexmask.long 0x8 0.--31. 1. "K,Key bit x (x =  191 to 160)" line.long 0xC "CRYP_K1RR,CRYP key register 1R" hexmask.long 0xC 0.--31. 1. "K,Key bit x (x =  159 to 128)" line.long 0x10 "CRYP_K2LR,CRYP key register 2L" hexmask.long 0x10 0.--31. 1. "K,Key bit x (x =  127 to 96)" line.long 0x14 "CRYP_K2RR,CRYP key register 2R" hexmask.long 0x14 0.--31. 1. "K,Key bit x (x =  95 to 64)" line.long 0x18 "CRYP_K3LR,CRYP key register 3L" hexmask.long 0x18 0.--31. 1. "K,Key bit x (x =  63 to 32)" line.long 0x1C "CRYP_K3RR,CRYP key register 3R" hexmask.long 0x1C 0.--31. 1. "K,Key bit x (x =  31 to 0)" group.long 0x40++0x4F line.long 0x0 "CRYP_IV0LR,CRYP initialization vector register 0L" hexmask.long 0x0 0.--31. 1. "IV,Initialization vector bit x (x =  127 to 96)" line.long 0x4 "CRYP_IV0RR,CRYP initialization vector register 0R" hexmask.long 0x4 0.--31. 1. "IV,Initialization vector bit x (x =  95 to 64)" line.long 0x8 "CRYP_IV1LR,CRYP initialization vector register 1L" hexmask.long 0x8 0.--31. 1. "IV,Initialization vector bit x (x =  63 to 32)" line.long 0xC "CRYP_IV1RR,CRYP initialization vector register 1R" hexmask.long 0xC 0.--31. 1. "IV,Initialization vector bit x (x =  31 to 16)" line.long 0x10 "CRYP_CSGCMCCM0R,CRYP context swap GCM-CCM registers" hexmask.long 0x10 0.--31. 1. "CSGCMCCM0,CRYP processor internal register states for GCM GMAC and CCM modes." line.long 0x14 "CRYP_CSGCMCCM1R,CRYP context swap GCM-CCM registers" hexmask.long 0x14 0.--31. 1. "CSGCMCCM1,CRYP processor internal register states for GCM GMAC and CCM modes." line.long 0x18 "CRYP_CSGCMCCM2R,CRYP context swap GCM-CCM registers" hexmask.long 0x18 0.--31. 1. "CSGCMCCM2,CRYP processor internal register states for GCM GMAC and CCM modes." line.long 0x1C "CRYP_CSGCMCCM3R,CRYP context swap GCM-CCM registers" hexmask.long 0x1C 0.--31. 1. "CSGCMCCM3,CRYP processor internal register states for GCM GMAC and CCM modes." line.long 0x20 "CRYP_CSGCMCCM4R,CRYP context swap GCM-CCM registers" hexmask.long 0x20 0.--31. 1. "CSGCMCCM4,CRYP processor internal register states for GCM GMAC and CCM modes." line.long 0x24 "CRYP_CSGCMCCM5R,CRYP context swap GCM-CCM registers" hexmask.long 0x24 0.--31. 1. "CSGCMCCM5,CRYP processor internal register states for GCM GMAC and CCM modes." line.long 0x28 "CRYP_CSGCMCCM6R,CRYP context swap GCM-CCM registers" hexmask.long 0x28 0.--31. 1. "CSGCMCCM6,CRYP processor internal register states for GCM GMAC and CCM modes." line.long 0x2C "CRYP_CSGCMCCM7R,CRYP context swap GCM-CCM registers" hexmask.long 0x2C 0.--31. 1. "CSGCMCCM7,CRYP processor internal register states for GCM GMAC and CCM modes." line.long 0x30 "CRYP_CSGCM0R,CRYP context swap GCM registers" hexmask.long 0x30 0.--31. 1. "CSGCM0,CRYP processor internal register states for GCM and GMAC modes." line.long 0x34 "CRYP_CSGCM1R,CRYP context swap GCM registers" hexmask.long 0x34 0.--31. 1. "CSGCM1,CRYP processor internal register states for GCM and GMAC modes." line.long 0x38 "CRYP_CSGCM2R,CRYP context swap GCM registers" hexmask.long 0x38 0.--31. 1. "CSGCM2,CRYP processor internal register states for GCM and GMAC modes." line.long 0x3C "CRYP_CSGCM3R,CRYP context swap GCM registers" hexmask.long 0x3C 0.--31. 1. "CSGCM3,CRYP processor internal register states for GCM and GMAC modes." line.long 0x40 "CRYP_CSGCM4R,CRYP context swap GCM registers" hexmask.long 0x40 0.--31. 1. "CSGCM4,CRYP processor internal register states for GCM and GMAC modes." line.long 0x44 "CRYP_CSGCM5R,CRYP context swap GCM registers" hexmask.long 0x44 0.--31. 1. "CSGCM5,CRYP processor internal register states for GCM and GMAC modes." line.long 0x48 "CRYP_CSGCM6R,CRYP context swap GCM registers" hexmask.long 0x48 0.--31. 1. "CSGCM6,CRYP processor internal register states for GCM and GMAC modes." line.long 0x4C "CRYP_CSGCM7R,CRYP context swap GCM registers" hexmask.long 0x4C 0.--31. 1. "CSGCM7,CRYP processor internal register states for GCM and GMAC modes." rgroup.long 0x3F0++0xF line.long 0x0 "CRYP_HWCFGR," hexmask.long.byte 0x0 12.--15. 1. "CFG4,HW Generic 4" hexmask.long.byte 0x0 8.--11. 1. "CFG3,HW Generic 3" newline hexmask.long.byte 0x0 4.--7. 1. "CFG2,HW Generic 2" hexmask.long.byte 0x0 0.--3. 1. "CFG1,HW Generic 1" line.long 0x4 "CRYP_VERR," hexmask.long.byte 0x4 4.--7. 1. "MAJVER,CRYP processor major version" hexmask.long.byte 0x4 0.--3. 1. "MINVER,CRYP processor minor version" line.long 0x8 "CRYP_IPIDR," hexmask.long 0x8 0.--31. 1. "ID,Identification Code" line.long 0xC "CRYP_SIDR," hexmask.long 0xC 0.--31. 1. "SID,Size identification code" tree.end endif sif (cpuis("STM32MP151*")||cpuis("STM32MP153*")||cpuis("STM32MP157*")) tree "CRYP1" base ad:0x54001000 group.long 0x0++0x3 line.long 0x0 "CRYP_CR,CRYP control register" hexmask.long.byte 0x0 20.--23. 1. "NPBLB,NPBLB" bitfld.long 0x0 19. "ALGOMODE3,ALGOMODE3" "0,1" bitfld.long 0x0 16.--17. "GCM_CCMPH,GCM_CCMPH" "0,1,2,3" bitfld.long 0x0 15. "CRYPEN,CRYPEN" "0,1" bitfld.long 0x0 14. "FFLUSH,FFLUSH" "0,1" bitfld.long 0x0 8.--9. "KEYSIZE,KEYSIZE" "0,1,2,3" bitfld.long 0x0 6.--7. "DATATYPE,DATATYPE" "0,1,2,3" bitfld.long 0x0 3.--5. "ALGOMODE,ALGOMODE" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 2. "ALGODIR,ALGODIR" "0,1" rgroup.long 0x4++0x3 line.long 0x0 "CRYP_SR,CRYP status register" bitfld.long 0x0 4. "BUSY,BUSY" "0,1" bitfld.long 0x0 3. "OFFU,OFFU" "0,1" bitfld.long 0x0 2. "OFNE,OFNE" "0,1" bitfld.long 0x0 1. "IFNF,IFNF" "0,1" bitfld.long 0x0 0. "IFEM,IFEM" "0,1" group.long 0x8++0x3 line.long 0x0 "CRYP_DIN,The CRYP_DIN register is the data input register. It is 32-bit wide. It is used to enter into the input FIFO up to four 64-bit blocks (TDES) or two 128-bit blocks (AES) of plaintext (when encrypting) or ciphertext (when decrypting). one 32-bit.." hexmask.long 0x0 0.--31. 1. "DATAIN,DATAIN" rgroup.long 0xC++0x3 line.long 0x0 "CRYP_DOUT,The CRYP_DOUT register is the data output register. It is read-only and 32-bit wide. It is used to retrieve from the output FIFO up to four 64-bit blocks (TDES) or two 128-bit blocks (AES) of plaintext (when encrypting) or ciphertext (when.." hexmask.long 0x0 0.--31. 1. "DATAOUT,DATAOUT" group.long 0x10++0x7 line.long 0x0 "CRYP_DMACR,CRYP DMA control register" bitfld.long 0x0 1. "DOEN,DOEN" "0,1" bitfld.long 0x0 0. "DIEN,DIEN" "0,1" line.long 0x4 "CRYP_IMSCR,The CRYP_IMSCR register is the interrupt mask set or clear register. It is a read/write register. When a read operation is performed. this register gives the current value of the mask applied to the relevant interrupt. Writing 1 to the.." bitfld.long 0x4 1. "OUTIM,OUTIM" "0,1" bitfld.long 0x4 0. "INIM,INIM" "0,1" rgroup.long 0x18++0x7 line.long 0x0 "CRYP_RISR,The CRYP_RISR register is the raw interrupt status register. It is a read-only register. When a read operation is performed. this register gives the current raw status of the corresponding interrupt. i.e. the interrupt information without.." bitfld.long 0x0 1. "OUTRIS,OUTRIS" "0,1" bitfld.long 0x0 0. "INRIS,INRIS" "0,1" line.long 0x4 "CRYP_MISR,The CRYP_MISR register is the masked interrupt status register. It is a read-only register. When a read operation is performed. this register gives the current masked status of the corresponding interrupt. i.e. the interrupt information taking.." bitfld.long 0x4 1. "OUTMIS,OUTMIS" "0,1" bitfld.long 0x4 0. "INMIS,INMIS" "0,1" wgroup.long 0x20++0x1F line.long 0x0 "CRYP_K0LR,CRYP key registers contain the cryptographic keys. In DES/TDES mode. the keys are 64-bit binary values (number from left to right. that is the leftmost bit is bit 1) and named K1. K2 and K3 (K0 is not used). Each key consists of 56 information.." hexmask.long 0x0 0.--31. 1. "K,K" line.long 0x4 "CRYP_K0RR,Refer to Section39.6.9: CRYP key register 0L (CRYP_K0LR) for details." hexmask.long 0x4 0.--31. 1. "K,K" line.long 0x8 "CRYP_K1LR,Refer to Section39.6.9: CRYP key register 0L (CRYP_K0LR) for details." hexmask.long 0x8 0.--31. 1. "K,K" line.long 0xC "CRYP_K1RR,Refer to Section39.6.9: CRYP key register 0L (CRYP_K0LR) for details." hexmask.long 0xC 0.--31. 1. "K,K" line.long 0x10 "CRYP_K2LR,Refer to Section39.6.9: CRYP key register 0L (CRYP_K0LR) for details." hexmask.long 0x10 0.--31. 1. "K,K" line.long 0x14 "CRYP_K2RR,Refer to Section39.6.9: CRYP key register 0L (CRYP_K0LR) for details." hexmask.long 0x14 0.--31. 1. "K,K" line.long 0x18 "CRYP_K3LR,Refer to Section39.6.9: CRYP key register 0L (CRYP_K0LR) for details." hexmask.long 0x18 0.--31. 1. "K,K" line.long 0x1C "CRYP_K3RR,Refer to Section39.6.9: CRYP key register 0L (CRYP_K0LR) for details." hexmask.long 0x1C 0.--31. 1. "K,K" group.long 0x40++0x4F line.long 0x0 "CRYP_IV0LR,The CRYP_IV0...1(L/R)R are the left-word and right-word registers for the initialization vector (64 bits for DES/TDES and 128 bits for AES). For more information refer to Section39.3.18: CRYP initialization vector registers. IV0 is the.." bitfld.long 0x0 31. "IV0,IV0" "0,1" bitfld.long 0x0 30. "IV1,IV1" "0,1" bitfld.long 0x0 29. "IV2,IV2" "0,1" bitfld.long 0x0 28. "IV3,IV3" "0,1" bitfld.long 0x0 27. "IV4,IV4" "0,1" bitfld.long 0x0 26. "IV5,IV5" "0,1" bitfld.long 0x0 25. "IV6,IV6" "0,1" bitfld.long 0x0 24. "IV7,IV7" "0,1" newline bitfld.long 0x0 23. "IV8,IV8" "0,1" bitfld.long 0x0 22. "IV9,IV9" "0,1" bitfld.long 0x0 21. "IV10,IV10" "0,1" bitfld.long 0x0 20. "IV11,IV11" "0,1" bitfld.long 0x0 19. "IV12,IV12" "0,1" bitfld.long 0x0 18. "IV13,IV13" "0,1" bitfld.long 0x0 17. "IV14,IV14" "0,1" bitfld.long 0x0 16. "IV15,IV15" "0,1" newline bitfld.long 0x0 15. "IV16,IV16" "0,1" bitfld.long 0x0 14. "IV17,IV17" "0,1" bitfld.long 0x0 13. "IV18,IV18" "0,1" bitfld.long 0x0 12. "IV19,IV19" "0,1" bitfld.long 0x0 11. "IV20,IV20" "0,1" bitfld.long 0x0 10. "IV21,IV21" "0,1" bitfld.long 0x0 9. "IV22,IV22" "0,1" bitfld.long 0x0 8. "IV23,IV23" "0,1" newline bitfld.long 0x0 7. "IV24,IV24" "0,1" bitfld.long 0x0 6. "IV25,IV25" "0,1" bitfld.long 0x0 5. "IV26,IV26" "0,1" bitfld.long 0x0 4. "IV27,IV27" "0,1" bitfld.long 0x0 3. "IV28,IV28" "0,1" bitfld.long 0x0 2. "IV29,IV29" "0,1" bitfld.long 0x0 1. "IV30,IV30" "0,1" bitfld.long 0x0 0. "IV31,IV31" "0,1" line.long 0x4 "CRYP_IV0RR,Refer to Section39.6.17: CRYP initialization vector register 0L (CRYP_IV0LR) for details." bitfld.long 0x4 31. "IV32,IV32" "0,1" bitfld.long 0x4 30. "IV33,IV33" "0,1" bitfld.long 0x4 29. "IV34,IV34" "0,1" bitfld.long 0x4 28. "IV35,IV35" "0,1" bitfld.long 0x4 27. "IV36,IV36" "0,1" bitfld.long 0x4 26. "IV37,IV37" "0,1" bitfld.long 0x4 25. "IV38,IV38" "0,1" bitfld.long 0x4 24. "IV39,IV39" "0,1" newline bitfld.long 0x4 23. "IV40,IV40" "0,1" bitfld.long 0x4 22. "IV41,IV41" "0,1" bitfld.long 0x4 21. "IV42,IV42" "0,1" bitfld.long 0x4 20. "IV43,IV43" "0,1" bitfld.long 0x4 19. "IV44,IV44" "0,1" bitfld.long 0x4 18. "IV45,IV45" "0,1" bitfld.long 0x4 17. "IV46,IV46" "0,1" bitfld.long 0x4 16. "IV47,IV47" "0,1" newline bitfld.long 0x4 15. "IV48,IV48" "0,1" bitfld.long 0x4 14. "IV49,IV49" "0,1" bitfld.long 0x4 13. "IV50,IV50" "0,1" bitfld.long 0x4 12. "IV51,IV51" "0,1" bitfld.long 0x4 11. "IV52,IV52" "0,1" bitfld.long 0x4 10. "IV53,IV53" "0,1" bitfld.long 0x4 9. "IV54,IV54" "0,1" bitfld.long 0x4 8. "IV55,IV55" "0,1" newline bitfld.long 0x4 7. "IV56,IV56" "0,1" bitfld.long 0x4 6. "IV57,IV57" "0,1" bitfld.long 0x4 5. "IV58,IV58" "0,1" bitfld.long 0x4 4. "IV59,IV59" "0,1" bitfld.long 0x4 3. "IV60,IV60" "0,1" bitfld.long 0x4 2. "IV61,IV61" "0,1" bitfld.long 0x4 1. "IV62,IV62" "0,1" bitfld.long 0x4 0. "IV63,IV63" "0,1" line.long 0x8 "CRYP_IV1LR,Refer to Section39.6.17: CRYP initialization vector register 0L (CRYP_IV0LR) for details." bitfld.long 0x8 31. "IV64,IV64" "0,1" bitfld.long 0x8 30. "IV65,IV65" "0,1" bitfld.long 0x8 29. "IV66,IV66" "0,1" bitfld.long 0x8 28. "IV67,IV67" "0,1" bitfld.long 0x8 27. "IV68,IV68" "0,1" bitfld.long 0x8 26. "IV69,IV69" "0,1" bitfld.long 0x8 25. "IV70,IV70" "0,1" bitfld.long 0x8 24. "IV71,IV71" "0,1" newline bitfld.long 0x8 23. "IV72,IV72" "0,1" bitfld.long 0x8 22. "IV73,IV73" "0,1" bitfld.long 0x8 21. "IV74,IV74" "0,1" bitfld.long 0x8 20. "IV75,IV75" "0,1" bitfld.long 0x8 19. "IV76,IV76" "0,1" bitfld.long 0x8 18. "IV77,IV77" "0,1" bitfld.long 0x8 17. "IV78,IV78" "0,1" bitfld.long 0x8 16. "IV79,IV79" "0,1" newline bitfld.long 0x8 15. "IV80,IV80" "0,1" bitfld.long 0x8 14. "IV81,IV81" "0,1" bitfld.long 0x8 13. "IV82,IV82" "0,1" bitfld.long 0x8 12. "IV83,IV83" "0,1" bitfld.long 0x8 11. "IV84,IV84" "0,1" bitfld.long 0x8 10. "IV85,IV85" "0,1" bitfld.long 0x8 9. "IV86,IV86" "0,1" bitfld.long 0x8 8. "IV87,IV87" "0,1" newline bitfld.long 0x8 7. "IV88,IV88" "0,1" bitfld.long 0x8 6. "IV89,IV89" "0,1" bitfld.long 0x8 5. "IV90,IV90" "0,1" bitfld.long 0x8 4. "IV91,IV91" "0,1" bitfld.long 0x8 3. "IV92,IV92" "0,1" bitfld.long 0x8 2. "IV93,IV93" "0,1" bitfld.long 0x8 1. "IV94,IV94" "0,1" bitfld.long 0x8 0. "IV95,IV95" "0,1" line.long 0xC "CRYP_IV1RR,Refer to Section39.6.17: CRYP initialization vector register 0L (CRYP_IV0LR) for details." bitfld.long 0xC 31. "IV96,IV96" "0,1" bitfld.long 0xC 30. "IV97,IV97" "0,1" bitfld.long 0xC 29. "IV98,IV98" "0,1" bitfld.long 0xC 28. "IV99,IV99" "0,1" bitfld.long 0xC 27. "IV100,IV100" "0,1" bitfld.long 0xC 26. "IV101,IV101" "0,1" bitfld.long 0xC 25. "IV102,IV102" "0,1" bitfld.long 0xC 24. "IV103,IV103" "0,1" newline bitfld.long 0xC 23. "IV104,IV104" "0,1" bitfld.long 0xC 22. "IV105,IV105" "0,1" bitfld.long 0xC 21. "IV106,IV106" "0,1" bitfld.long 0xC 20. "IV107,IV107" "0,1" bitfld.long 0xC 19. "IV108,IV108" "0,1" bitfld.long 0xC 18. "IV109,IV109" "0,1" bitfld.long 0xC 17. "IV110,IV110" "0,1" bitfld.long 0xC 16. "IV111,IV111" "0,1" newline bitfld.long 0xC 15. "IV112,IV112" "0,1" bitfld.long 0xC 14. "IV113,IV113" "0,1" bitfld.long 0xC 13. "IV114,IV114" "0,1" bitfld.long 0xC 12. "IV115,IV115" "0,1" bitfld.long 0xC 11. "IV116,IV116" "0,1" bitfld.long 0xC 10. "IV117,IV117" "0,1" bitfld.long 0xC 9. "IV118,IV118" "0,1" bitfld.long 0xC 8. "IV119,IV119" "0,1" newline bitfld.long 0xC 7. "IV120,IV120" "0,1" bitfld.long 0xC 6. "IV121,IV121" "0,1" bitfld.long 0xC 5. "IV122,IV122" "0,1" bitfld.long 0xC 4. "IV123,IV123" "0,1" bitfld.long 0xC 3. "IV124,IV124" "0,1" bitfld.long 0xC 2. "IV125,IV125" "0,1" bitfld.long 0xC 1. "IV126,IV126" "0,1" bitfld.long 0xC 0. "IV127,IV127" "0,1" line.long 0x10 "CRYP_CSGCMCCM0R,These registers contain the complete internal register states of the CRYP processor when the GCM/GMAC or CCM algorithm is selected. They are useful when a context swap has to be performed because a high-priority task needs the.." hexmask.long 0x10 0.--31. 1. "CSGCMCCM0,CSGCMCCM0" line.long 0x14 "CRYP_CSGCMCCM1R,These registers contain the complete internal register states of the CRYP processor when the GCM/GMAC or CCM algorithm is selected. They are useful when a context swap has to be performed because a high-priority task needs the.." hexmask.long 0x14 0.--31. 1. "CSGCMCCM1,CSGCMCCM1" line.long 0x18 "CRYP_CSGCMCCM2R,These registers contain the complete internal register states of the CRYP processor when the GCM/GMAC or CCM algorithm is selected. They are useful when a context swap has to be performed because a high-priority task needs the.." hexmask.long 0x18 0.--31. 1. "CSGCMCCM2,CSGCMCCM2" line.long 0x1C "CRYP_CSGCMCCM3R,These registers contain the complete internal register states of the CRYP processor when the GCM/GMAC or CCM algorithm is selected. They are useful when a context swap has to be performed because a high-priority task needs the.." hexmask.long 0x1C 0.--31. 1. "CSGCMCCM3,CSGCMCCM3" line.long 0x20 "CRYP_CSGCMCCM4R,These registers contain the complete internal register states of the CRYP processor when the GCM/GMAC or CCM algorithm is selected. They are useful when a context swap has to be performed because a high-priority task needs the.." hexmask.long 0x20 0.--31. 1. "CSGCMCCM4,CSGCMCCM4" line.long 0x24 "CRYP_CSGCMCCM5R,These registers contain the complete internal register states of the CRYP processor when the GCM/GMAC or CCM algorithm is selected. They are useful when a context swap has to be performed because a high-priority task needs the.." hexmask.long 0x24 0.--31. 1. "CSGCMCCM5,CSGCMCCM5" line.long 0x28 "CRYP_CSGCMCCM6R,These registers contain the complete internal register states of the CRYP processor when the GCM/GMAC or CCM algorithm is selected. They are useful when a context swap has to be performed because a high-priority task needs the.." hexmask.long 0x28 0.--31. 1. "CSGCMCCM6,CSGCMCCM6" line.long 0x2C "CRYP_CSGCMCCM7R,These registers contain the complete internal register states of the CRYP processor when the GCM/GMAC or CCM algorithm is selected. They are useful when a context swap has to be performed because a high-priority task needs the.." hexmask.long 0x2C 0.--31. 1. "CSGCMCCM7,CSGCMCCM7" line.long 0x30 "CRYP_CSGCM0R,Please refer to Section39.6.21: CRYP context swap GCM-CCM registers (CRYP_CSGCMCCMxR) for details." hexmask.long 0x30 0.--31. 1. "CSGCM0,CSGCM0" line.long 0x34 "CRYP_CSGCM1R,Please refer to Section39.6.21: CRYP context swap GCM-CCM registers (CRYP_CSGCMCCMxR) for details." hexmask.long 0x34 0.--31. 1. "CSGCM1,CSGCM1" line.long 0x38 "CRYP_CSGCM2R,Please refer to Section39.6.21: CRYP context swap GCM-CCM registers (CRYP_CSGCMCCMxR) for details." hexmask.long 0x38 0.--31. 1. "CSGCM2,CSGCM2" line.long 0x3C "CRYP_CSGCM3R,Please refer to Section39.6.21: CRYP context swap GCM-CCM registers (CRYP_CSGCMCCMxR) for details." hexmask.long 0x3C 0.--31. 1. "CSGCM3,CSGCM3" line.long 0x40 "CRYP_CSGCM4R,Please refer to Section39.6.21: CRYP context swap GCM-CCM registers (CRYP_CSGCMCCMxR) for details." hexmask.long 0x40 0.--31. 1. "CSGCM4,CSGCM4" line.long 0x44 "CRYP_CSGCM5R,Please refer to Section39.6.21: CRYP context swap GCM-CCM registers (CRYP_CSGCMCCMxR) for details." hexmask.long 0x44 0.--31. 1. "CSGCM5,CSGCM5" line.long 0x48 "CRYP_CSGCM6R,Please refer to Section39.6.21: CRYP context swap GCM-CCM registers (CRYP_CSGCMCCMxR) for details." hexmask.long 0x48 0.--31. 1. "CSGCM6,CSGCM6" line.long 0x4C "CRYP_CSGCM7R,Please refer to Section39.6.21: CRYP context swap GCM-CCM registers (CRYP_CSGCMCCMxR) for details." hexmask.long 0x4C 0.--31. 1. "CSGCM7,CSGCM7" rgroup.long 0x3F0++0xF line.long 0x0 "CRYP_HWCFGR,CRYP hardware configuration register" hexmask.long.byte 0x0 12.--15. 1. "CFG4,CFG4" hexmask.long.byte 0x0 8.--11. 1. "CFG3,CFG3" hexmask.long.byte 0x0 4.--7. 1. "CFG2,CFG2" hexmask.long.byte 0x0 0.--3. 1. "CFG1,CFG1" line.long 0x4 "CRYP_VERR,CRYP HW Version Register" hexmask.long.byte 0x4 0.--7. 1. "VER,VER" line.long 0x8 "CRYP_IPIDR,CRYP Identification" hexmask.long 0x8 0.--31. 1. "ID,ID" line.long 0xC "CRYP_MID,CRYP HW Magic ID" hexmask.long 0xC 0.--31. 1. "MID,MID" tree.end endif sif (cpuis("STM32MP151*")||cpuis("STM32MP153*")||cpuis("STM32MP157*")) tree "CRYP2" base ad:0x4C005000 group.long 0x0++0x3 line.long 0x0 "CRYP_CR,CRYP control register" hexmask.long.byte 0x0 20.--23. 1. "NPBLB,NPBLB" bitfld.long 0x0 19. "ALGOMODE3,ALGOMODE3" "0,1" bitfld.long 0x0 16.--17. "GCM_CCMPH,GCM_CCMPH" "0,1,2,3" bitfld.long 0x0 15. "CRYPEN,CRYPEN" "0,1" bitfld.long 0x0 14. "FFLUSH,FFLUSH" "0,1" bitfld.long 0x0 8.--9. "KEYSIZE,KEYSIZE" "0,1,2,3" bitfld.long 0x0 6.--7. "DATATYPE,DATATYPE" "0,1,2,3" bitfld.long 0x0 3.--5. "ALGOMODE,ALGOMODE" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 2. "ALGODIR,ALGODIR" "0,1" rgroup.long 0x4++0x3 line.long 0x0 "CRYP_SR,CRYP status register" bitfld.long 0x0 4. "BUSY,BUSY" "0,1" bitfld.long 0x0 3. "OFFU,OFFU" "0,1" bitfld.long 0x0 2. "OFNE,OFNE" "0,1" bitfld.long 0x0 1. "IFNF,IFNF" "0,1" bitfld.long 0x0 0. "IFEM,IFEM" "0,1" group.long 0x8++0x3 line.long 0x0 "CRYP_DIN,The CRYP_DIN register is the data input register. It is 32-bit wide. It is used to enter into the input FIFO up to four 64-bit blocks (TDES) or two 128-bit blocks (AES) of plaintext (when encrypting) or ciphertext (when decrypting). one 32-bit.." hexmask.long 0x0 0.--31. 1. "DATAIN,DATAIN" rgroup.long 0xC++0x3 line.long 0x0 "CRYP_DOUT,The CRYP_DOUT register is the data output register. It is read-only and 32-bit wide. It is used to retrieve from the output FIFO up to four 64-bit blocks (TDES) or two 128-bit blocks (AES) of plaintext (when encrypting) or ciphertext (when.." hexmask.long 0x0 0.--31. 1. "DATAOUT,DATAOUT" group.long 0x10++0x7 line.long 0x0 "CRYP_DMACR,CRYP DMA control register" bitfld.long 0x0 1. "DOEN,DOEN" "0,1" bitfld.long 0x0 0. "DIEN,DIEN" "0,1" line.long 0x4 "CRYP_IMSCR,The CRYP_IMSCR register is the interrupt mask set or clear register. It is a read/write register. When a read operation is performed. this register gives the current value of the mask applied to the relevant interrupt. Writing 1 to the.." bitfld.long 0x4 1. "OUTIM,OUTIM" "0,1" bitfld.long 0x4 0. "INIM,INIM" "0,1" rgroup.long 0x18++0x7 line.long 0x0 "CRYP_RISR,The CRYP_RISR register is the raw interrupt status register. It is a read-only register. When a read operation is performed. this register gives the current raw status of the corresponding interrupt. i.e. the interrupt information without.." bitfld.long 0x0 1. "OUTRIS,OUTRIS" "0,1" bitfld.long 0x0 0. "INRIS,INRIS" "0,1" line.long 0x4 "CRYP_MISR,The CRYP_MISR register is the masked interrupt status register. It is a read-only register. When a read operation is performed. this register gives the current masked status of the corresponding interrupt. i.e. the interrupt information taking.." bitfld.long 0x4 1. "OUTMIS,OUTMIS" "0,1" bitfld.long 0x4 0. "INMIS,INMIS" "0,1" wgroup.long 0x20++0x1F line.long 0x0 "CRYP_K0LR,CRYP key registers contain the cryptographic keys. In DES/TDES mode. the keys are 64-bit binary values (number from left to right. that is the leftmost bit is bit 1) and named K1. K2 and K3 (K0 is not used). Each key consists of 56 information.." hexmask.long 0x0 0.--31. 1. "K,K" line.long 0x4 "CRYP_K0RR,Refer to Section39.6.9: CRYP key register 0L (CRYP_K0LR) for details." hexmask.long 0x4 0.--31. 1. "K,K" line.long 0x8 "CRYP_K1LR,Refer to Section39.6.9: CRYP key register 0L (CRYP_K0LR) for details." hexmask.long 0x8 0.--31. 1. "K,K" line.long 0xC "CRYP_K1RR,Refer to Section39.6.9: CRYP key register 0L (CRYP_K0LR) for details." hexmask.long 0xC 0.--31. 1. "K,K" line.long 0x10 "CRYP_K2LR,Refer to Section39.6.9: CRYP key register 0L (CRYP_K0LR) for details." hexmask.long 0x10 0.--31. 1. "K,K" line.long 0x14 "CRYP_K2RR,Refer to Section39.6.9: CRYP key register 0L (CRYP_K0LR) for details." hexmask.long 0x14 0.--31. 1. "K,K" line.long 0x18 "CRYP_K3LR,Refer to Section39.6.9: CRYP key register 0L (CRYP_K0LR) for details." hexmask.long 0x18 0.--31. 1. "K,K" line.long 0x1C "CRYP_K3RR,Refer to Section39.6.9: CRYP key register 0L (CRYP_K0LR) for details." hexmask.long 0x1C 0.--31. 1. "K,K" group.long 0x40++0x4F line.long 0x0 "CRYP_IV0LR,The CRYP_IV0...1(L/R)R are the left-word and right-word registers for the initialization vector (64 bits for DES/TDES and 128 bits for AES). For more information refer to Section39.3.18: CRYP initialization vector registers. IV0 is the.." bitfld.long 0x0 31. "IV0,IV0" "0,1" bitfld.long 0x0 30. "IV1,IV1" "0,1" bitfld.long 0x0 29. "IV2,IV2" "0,1" bitfld.long 0x0 28. "IV3,IV3" "0,1" bitfld.long 0x0 27. "IV4,IV4" "0,1" bitfld.long 0x0 26. "IV5,IV5" "0,1" bitfld.long 0x0 25. "IV6,IV6" "0,1" bitfld.long 0x0 24. "IV7,IV7" "0,1" newline bitfld.long 0x0 23. "IV8,IV8" "0,1" bitfld.long 0x0 22. "IV9,IV9" "0,1" bitfld.long 0x0 21. "IV10,IV10" "0,1" bitfld.long 0x0 20. "IV11,IV11" "0,1" bitfld.long 0x0 19. "IV12,IV12" "0,1" bitfld.long 0x0 18. "IV13,IV13" "0,1" bitfld.long 0x0 17. "IV14,IV14" "0,1" bitfld.long 0x0 16. "IV15,IV15" "0,1" newline bitfld.long 0x0 15. "IV16,IV16" "0,1" bitfld.long 0x0 14. "IV17,IV17" "0,1" bitfld.long 0x0 13. "IV18,IV18" "0,1" bitfld.long 0x0 12. "IV19,IV19" "0,1" bitfld.long 0x0 11. "IV20,IV20" "0,1" bitfld.long 0x0 10. "IV21,IV21" "0,1" bitfld.long 0x0 9. "IV22,IV22" "0,1" bitfld.long 0x0 8. "IV23,IV23" "0,1" newline bitfld.long 0x0 7. "IV24,IV24" "0,1" bitfld.long 0x0 6. "IV25,IV25" "0,1" bitfld.long 0x0 5. "IV26,IV26" "0,1" bitfld.long 0x0 4. "IV27,IV27" "0,1" bitfld.long 0x0 3. "IV28,IV28" "0,1" bitfld.long 0x0 2. "IV29,IV29" "0,1" bitfld.long 0x0 1. "IV30,IV30" "0,1" bitfld.long 0x0 0. "IV31,IV31" "0,1" line.long 0x4 "CRYP_IV0RR,Refer to Section39.6.17: CRYP initialization vector register 0L (CRYP_IV0LR) for details." bitfld.long 0x4 31. "IV32,IV32" "0,1" bitfld.long 0x4 30. "IV33,IV33" "0,1" bitfld.long 0x4 29. "IV34,IV34" "0,1" bitfld.long 0x4 28. "IV35,IV35" "0,1" bitfld.long 0x4 27. "IV36,IV36" "0,1" bitfld.long 0x4 26. "IV37,IV37" "0,1" bitfld.long 0x4 25. "IV38,IV38" "0,1" bitfld.long 0x4 24. "IV39,IV39" "0,1" newline bitfld.long 0x4 23. "IV40,IV40" "0,1" bitfld.long 0x4 22. "IV41,IV41" "0,1" bitfld.long 0x4 21. "IV42,IV42" "0,1" bitfld.long 0x4 20. "IV43,IV43" "0,1" bitfld.long 0x4 19. "IV44,IV44" "0,1" bitfld.long 0x4 18. "IV45,IV45" "0,1" bitfld.long 0x4 17. "IV46,IV46" "0,1" bitfld.long 0x4 16. "IV47,IV47" "0,1" newline bitfld.long 0x4 15. "IV48,IV48" "0,1" bitfld.long 0x4 14. "IV49,IV49" "0,1" bitfld.long 0x4 13. "IV50,IV50" "0,1" bitfld.long 0x4 12. "IV51,IV51" "0,1" bitfld.long 0x4 11. "IV52,IV52" "0,1" bitfld.long 0x4 10. "IV53,IV53" "0,1" bitfld.long 0x4 9. "IV54,IV54" "0,1" bitfld.long 0x4 8. "IV55,IV55" "0,1" newline bitfld.long 0x4 7. "IV56,IV56" "0,1" bitfld.long 0x4 6. "IV57,IV57" "0,1" bitfld.long 0x4 5. "IV58,IV58" "0,1" bitfld.long 0x4 4. "IV59,IV59" "0,1" bitfld.long 0x4 3. "IV60,IV60" "0,1" bitfld.long 0x4 2. "IV61,IV61" "0,1" bitfld.long 0x4 1. "IV62,IV62" "0,1" bitfld.long 0x4 0. "IV63,IV63" "0,1" line.long 0x8 "CRYP_IV1LR,Refer to Section39.6.17: CRYP initialization vector register 0L (CRYP_IV0LR) for details." bitfld.long 0x8 31. "IV64,IV64" "0,1" bitfld.long 0x8 30. "IV65,IV65" "0,1" bitfld.long 0x8 29. "IV66,IV66" "0,1" bitfld.long 0x8 28. "IV67,IV67" "0,1" bitfld.long 0x8 27. "IV68,IV68" "0,1" bitfld.long 0x8 26. "IV69,IV69" "0,1" bitfld.long 0x8 25. "IV70,IV70" "0,1" bitfld.long 0x8 24. "IV71,IV71" "0,1" newline bitfld.long 0x8 23. "IV72,IV72" "0,1" bitfld.long 0x8 22. "IV73,IV73" "0,1" bitfld.long 0x8 21. "IV74,IV74" "0,1" bitfld.long 0x8 20. "IV75,IV75" "0,1" bitfld.long 0x8 19. "IV76,IV76" "0,1" bitfld.long 0x8 18. "IV77,IV77" "0,1" bitfld.long 0x8 17. "IV78,IV78" "0,1" bitfld.long 0x8 16. "IV79,IV79" "0,1" newline bitfld.long 0x8 15. "IV80,IV80" "0,1" bitfld.long 0x8 14. "IV81,IV81" "0,1" bitfld.long 0x8 13. "IV82,IV82" "0,1" bitfld.long 0x8 12. "IV83,IV83" "0,1" bitfld.long 0x8 11. "IV84,IV84" "0,1" bitfld.long 0x8 10. "IV85,IV85" "0,1" bitfld.long 0x8 9. "IV86,IV86" "0,1" bitfld.long 0x8 8. "IV87,IV87" "0,1" newline bitfld.long 0x8 7. "IV88,IV88" "0,1" bitfld.long 0x8 6. "IV89,IV89" "0,1" bitfld.long 0x8 5. "IV90,IV90" "0,1" bitfld.long 0x8 4. "IV91,IV91" "0,1" bitfld.long 0x8 3. "IV92,IV92" "0,1" bitfld.long 0x8 2. "IV93,IV93" "0,1" bitfld.long 0x8 1. "IV94,IV94" "0,1" bitfld.long 0x8 0. "IV95,IV95" "0,1" line.long 0xC "CRYP_IV1RR,Refer to Section39.6.17: CRYP initialization vector register 0L (CRYP_IV0LR) for details." bitfld.long 0xC 31. "IV96,IV96" "0,1" bitfld.long 0xC 30. "IV97,IV97" "0,1" bitfld.long 0xC 29. "IV98,IV98" "0,1" bitfld.long 0xC 28. "IV99,IV99" "0,1" bitfld.long 0xC 27. "IV100,IV100" "0,1" bitfld.long 0xC 26. "IV101,IV101" "0,1" bitfld.long 0xC 25. "IV102,IV102" "0,1" bitfld.long 0xC 24. "IV103,IV103" "0,1" newline bitfld.long 0xC 23. "IV104,IV104" "0,1" bitfld.long 0xC 22. "IV105,IV105" "0,1" bitfld.long 0xC 21. "IV106,IV106" "0,1" bitfld.long 0xC 20. "IV107,IV107" "0,1" bitfld.long 0xC 19. "IV108,IV108" "0,1" bitfld.long 0xC 18. "IV109,IV109" "0,1" bitfld.long 0xC 17. "IV110,IV110" "0,1" bitfld.long 0xC 16. "IV111,IV111" "0,1" newline bitfld.long 0xC 15. "IV112,IV112" "0,1" bitfld.long 0xC 14. "IV113,IV113" "0,1" bitfld.long 0xC 13. "IV114,IV114" "0,1" bitfld.long 0xC 12. "IV115,IV115" "0,1" bitfld.long 0xC 11. "IV116,IV116" "0,1" bitfld.long 0xC 10. "IV117,IV117" "0,1" bitfld.long 0xC 9. "IV118,IV118" "0,1" bitfld.long 0xC 8. "IV119,IV119" "0,1" newline bitfld.long 0xC 7. "IV120,IV120" "0,1" bitfld.long 0xC 6. "IV121,IV121" "0,1" bitfld.long 0xC 5. "IV122,IV122" "0,1" bitfld.long 0xC 4. "IV123,IV123" "0,1" bitfld.long 0xC 3. "IV124,IV124" "0,1" bitfld.long 0xC 2. "IV125,IV125" "0,1" bitfld.long 0xC 1. "IV126,IV126" "0,1" bitfld.long 0xC 0. "IV127,IV127" "0,1" line.long 0x10 "CRYP_CSGCMCCM0R,These registers contain the complete internal register states of the CRYP processor when the GCM/GMAC or CCM algorithm is selected. They are useful when a context swap has to be performed because a high-priority task needs the.." hexmask.long 0x10 0.--31. 1. "CSGCMCCM0,CSGCMCCM0" line.long 0x14 "CRYP_CSGCMCCM1R,These registers contain the complete internal register states of the CRYP processor when the GCM/GMAC or CCM algorithm is selected. They are useful when a context swap has to be performed because a high-priority task needs the.." hexmask.long 0x14 0.--31. 1. "CSGCMCCM1,CSGCMCCM1" line.long 0x18 "CRYP_CSGCMCCM2R,These registers contain the complete internal register states of the CRYP processor when the GCM/GMAC or CCM algorithm is selected. They are useful when a context swap has to be performed because a high-priority task needs the.." hexmask.long 0x18 0.--31. 1. "CSGCMCCM2,CSGCMCCM2" line.long 0x1C "CRYP_CSGCMCCM3R,These registers contain the complete internal register states of the CRYP processor when the GCM/GMAC or CCM algorithm is selected. They are useful when a context swap has to be performed because a high-priority task needs the.." hexmask.long 0x1C 0.--31. 1. "CSGCMCCM3,CSGCMCCM3" line.long 0x20 "CRYP_CSGCMCCM4R,These registers contain the complete internal register states of the CRYP processor when the GCM/GMAC or CCM algorithm is selected. They are useful when a context swap has to be performed because a high-priority task needs the.." hexmask.long 0x20 0.--31. 1. "CSGCMCCM4,CSGCMCCM4" line.long 0x24 "CRYP_CSGCMCCM5R,These registers contain the complete internal register states of the CRYP processor when the GCM/GMAC or CCM algorithm is selected. They are useful when a context swap has to be performed because a high-priority task needs the.." hexmask.long 0x24 0.--31. 1. "CSGCMCCM5,CSGCMCCM5" line.long 0x28 "CRYP_CSGCMCCM6R,These registers contain the complete internal register states of the CRYP processor when the GCM/GMAC or CCM algorithm is selected. They are useful when a context swap has to be performed because a high-priority task needs the.." hexmask.long 0x28 0.--31. 1. "CSGCMCCM6,CSGCMCCM6" line.long 0x2C "CRYP_CSGCMCCM7R,These registers contain the complete internal register states of the CRYP processor when the GCM/GMAC or CCM algorithm is selected. They are useful when a context swap has to be performed because a high-priority task needs the.." hexmask.long 0x2C 0.--31. 1. "CSGCMCCM7,CSGCMCCM7" line.long 0x30 "CRYP_CSGCM0R,Please refer to Section39.6.21: CRYP context swap GCM-CCM registers (CRYP_CSGCMCCMxR) for details." hexmask.long 0x30 0.--31. 1. "CSGCM0,CSGCM0" line.long 0x34 "CRYP_CSGCM1R,Please refer to Section39.6.21: CRYP context swap GCM-CCM registers (CRYP_CSGCMCCMxR) for details." hexmask.long 0x34 0.--31. 1. "CSGCM1,CSGCM1" line.long 0x38 "CRYP_CSGCM2R,Please refer to Section39.6.21: CRYP context swap GCM-CCM registers (CRYP_CSGCMCCMxR) for details." hexmask.long 0x38 0.--31. 1. "CSGCM2,CSGCM2" line.long 0x3C "CRYP_CSGCM3R,Please refer to Section39.6.21: CRYP context swap GCM-CCM registers (CRYP_CSGCMCCMxR) for details." hexmask.long 0x3C 0.--31. 1. "CSGCM3,CSGCM3" line.long 0x40 "CRYP_CSGCM4R,Please refer to Section39.6.21: CRYP context swap GCM-CCM registers (CRYP_CSGCMCCMxR) for details." hexmask.long 0x40 0.--31. 1. "CSGCM4,CSGCM4" line.long 0x44 "CRYP_CSGCM5R,Please refer to Section39.6.21: CRYP context swap GCM-CCM registers (CRYP_CSGCMCCMxR) for details." hexmask.long 0x44 0.--31. 1. "CSGCM5,CSGCM5" line.long 0x48 "CRYP_CSGCM6R,Please refer to Section39.6.21: CRYP context swap GCM-CCM registers (CRYP_CSGCMCCMxR) for details." hexmask.long 0x48 0.--31. 1. "CSGCM6,CSGCM6" line.long 0x4C "CRYP_CSGCM7R,Please refer to Section39.6.21: CRYP context swap GCM-CCM registers (CRYP_CSGCMCCMxR) for details." hexmask.long 0x4C 0.--31. 1. "CSGCM7,CSGCM7" rgroup.long 0x3F0++0xF line.long 0x0 "CRYP_HWCFGR,CRYP hardware configuration register" hexmask.long.byte 0x0 12.--15. 1. "CFG4,CFG4" hexmask.long.byte 0x0 8.--11. 1. "CFG3,CFG3" hexmask.long.byte 0x0 4.--7. 1. "CFG2,CFG2" hexmask.long.byte 0x0 0.--3. 1. "CFG1,CFG1" line.long 0x4 "CRYP_VERR,CRYP HW Version Register" hexmask.long.byte 0x4 0.--7. 1. "VER,VER" line.long 0x8 "CRYP_IPIDR,CRYP Identification" hexmask.long 0x8 0.--31. 1. "ID,ID" line.long 0xC "CRYP_MID,CRYP HW Magic ID" hexmask.long 0xC 0.--31. 1. "MID,MID" tree.end endif tree.end sif (cpuis("STM32MP151*")||cpuis("STM32MP153*")||cpuis("STM32MP157*")) tree "DAC (Digital-to-Analog Converter)" base ad:0x40017000 group.long 0x0++0x3 line.long 0x0 "DAC_CR,DAC control register" bitfld.long 0x0 30. "CEN2,CEN2" "0,1" bitfld.long 0x0 29. "DMAUDRIE2,DMAUDRIE2" "0,1" bitfld.long 0x0 28. "DMAEN2,DMAEN2" "0,1" hexmask.long.byte 0x0 24.--27. 1. "MAMP2,MAMP2" bitfld.long 0x0 22.--23. "WAVE2,WAVE2" "0,1,2,3" bitfld.long 0x0 21. "TSEL23,TSEL23" "0,1" bitfld.long 0x0 20. "TSEL22,TSEL22" "0,1" bitfld.long 0x0 19. "TSEL21,TSEL21" "0,1" newline bitfld.long 0x0 18. "TSEL20,TSEL20" "0,1" bitfld.long 0x0 17. "TEN2,TEN2" "0,1" bitfld.long 0x0 16. "EN2,EN2" "0,1" bitfld.long 0x0 15. "HFSEL,HFSEL" "0,1" bitfld.long 0x0 14. "CEN1,CEN1" "0,1" bitfld.long 0x0 13. "DMAUDRIE1,DMAUDRIE1" "0,1" bitfld.long 0x0 12. "DMAEN1,DMAEN1" "0,1" hexmask.long.byte 0x0 8.--11. 1. "MAMP1,MAMP1" newline bitfld.long 0x0 6.--7. "WAVE1,WAVE1" "0,1,2,3" bitfld.long 0x0 5. "TSEL13,TSEL13" "0,1" bitfld.long 0x0 4. "TSEL12,TSEL12" "0,1" bitfld.long 0x0 3. "TSEL11,TSEL11" "0,1" bitfld.long 0x0 2. "TSEL10,TSEL10" "0,1" bitfld.long 0x0 1. "TEN1,TEN1" "0,1" bitfld.long 0x0 0. "EN1,EN1" "0,1" wgroup.long 0x4++0x3 line.long 0x0 "DAC_SWTRGR,DAC software trigger register" bitfld.long 0x0 1. "SWTRIG2,SWTRIG2" "0,1" bitfld.long 0x0 0. "SWTRIG1,SWTRIG1" "0,1" group.long 0x8++0x23 line.long 0x0 "DAC_DHR12R1,DAC channel1 12-bit right-aligned data holding register" hexmask.long.word 0x0 0.--11. 1. "DACC1DHR,DACC1DHR" line.long 0x4 "DAC_DHR12L1,DAC channel1 12-bit left aligned data holding register" hexmask.long.word 0x4 4.--15. 1. "DACC1DHR,DACC1DHR" line.long 0x8 "DAC_DHR8R1,DAC channel1 8-bit right aligned data holding register" hexmask.long.byte 0x8 0.--7. 1. "DACC1DHR,DACC1DHR" line.long 0xC "DAC_DHR12R2,This register is available only on dual-channel DACs. Refer to Section29.3: DAC implementation." hexmask.long.word 0xC 0.--11. 1. "DACC2DHR,DACC2DHR" line.long 0x10 "DAC_DHR12L2,This register is available only on dual-channel DACs. Refer to Section29.3: DAC implementation." hexmask.long.word 0x10 4.--15. 1. "DACC2DHR,DACC2DHR" line.long 0x14 "DAC_DHR8R2,This register is available only on dual-channel DACs. Refer to Section29.3: DAC implementation." hexmask.long.byte 0x14 0.--7. 1. "DACC2DHR,DACC2DHR" line.long 0x18 "DAC_DHR12RD,Dual DAC 12-bit right-aligned data holding register" hexmask.long.word 0x18 16.--27. 1. "DACC2DHR,DACC2DHR" hexmask.long.word 0x18 0.--11. 1. "DACC1DHR,DACC1DHR" line.long 0x1C "DAC_DHR12LD,Dual DAC 12-bit left aligned data holding register" hexmask.long.word 0x1C 20.--31. 1. "DACC2DHR,DACC2DHR" hexmask.long.word 0x1C 4.--15. 1. "DACC1DHR,DACC1DHR" line.long 0x20 "DAC_DHR8RD,Dual DAC 8-bit right aligned data holding register" hexmask.long.byte 0x20 8.--15. 1. "DACC2DHR,DACC2DHR" hexmask.long.byte 0x20 0.--7. 1. "DACC1DHR,DACC1DHR" rgroup.long 0x2C++0x7 line.long 0x0 "DAC_DOR1,DAC channel1 data output register" hexmask.long.word 0x0 0.--11. 1. "DACC1DOR,DACC1DOR" line.long 0x4 "DAC_DOR2,This register is available only on dual-channel DACs. Refer to Section29.3: DAC implementation." hexmask.long.word 0x4 0.--11. 1. "DACC2DOR,DACC2DOR" group.long 0x34++0x1B line.long 0x0 "DAC_SR,DAC status register" rbitfld.long 0x0 31. "BWST2,BWST2" "0,1" rbitfld.long 0x0 30. "CAL_FLAG2,CAL_FLAG2" "0,1" bitfld.long 0x0 29. "DMAUDR2,DMAUDR2" "0,1" rbitfld.long 0x0 15. "BWST1,BWST1" "0,1" rbitfld.long 0x0 14. "CAL_FLAG1,CAL_FLAG1" "0,1" bitfld.long 0x0 13. "DMAUDR1,DMAUDR1" "0,1" line.long 0x4 "DAC_CCR,DAC calibration control register" hexmask.long.byte 0x4 16.--20. 1. "OTRIM2,OTRIM2" hexmask.long.byte 0x4 0.--4. 1. "OTRIM1,OTRIM1" line.long 0x8 "DAC_MCR,DAC mode control register" bitfld.long 0x8 16.--18. "MODE2,MODE2" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "MODE1,MODE1" "0,1,2,3,4,5,6,7" line.long 0xC "DAC_SHSR1,DAC channel 1 sample and hold sample time register" hexmask.long.word 0xC 0.--9. 1. "TSAMPLE1,TSAMPLE1" line.long 0x10 "DAC_SHSR2,This register is available only on dual-channel DACs. Refer to Section29.3: DAC implementation." hexmask.long.word 0x10 0.--9. 1. "TSAMPLE2,TSAMPLE2" line.long 0x14 "DAC_SHHR,DAC sample and hold time register" hexmask.long.word 0x14 16.--25. 1. "THOLD2,THOLD2" hexmask.long.word 0x14 0.--9. 1. "THOLD1,THOLD1" line.long 0x18 "DAC_SHRR,DAC sample and hold refresh time register" hexmask.long.byte 0x18 16.--23. 1. "TREFRESH2,TREFRESH2" hexmask.long.byte 0x18 0.--7. 1. "TREFRESH1,TREFRESH1" rgroup.long 0x3F0++0xF line.long 0x0 "DAC_HWCFGR0,DAC IP hardware configuration register" hexmask.long.byte 0x0 16.--23. 1. "OR_CFG,OR_CFG" hexmask.long.byte 0x0 12.--15. 1. "SAMPLE,SAMPLE" hexmask.long.byte 0x0 8.--11. 1. "TRIANGLE,TRIANGLE" hexmask.long.byte 0x0 4.--7. 1. "LFSR,LFSR" hexmask.long.byte 0x0 0.--3. 1. "DUAL,DUAL" line.long 0x4 "DAC_VERR,No" hexmask.long.byte 0x4 4.--7. 1. "MAJREV,MAJREV" hexmask.long.byte 0x4 0.--3. 1. "MINREV,MINREV" line.long 0x8 "DAC_IPIDR,No" hexmask.long 0x8 0.--31. 1. "ID,ID" line.long 0xC "DAC_SIDR,No" hexmask.long 0xC 0.--31. 1. "SID,SID" tree.end endif sif (cpuis("STM32MP13*")) tree "DBGMCU (Microcontroller Debug Unit)" base ad:0x50081000 rgroup.long 0x0++0x3 line.long 0x0 "DBGMCU_IDC,DBGMCU identity code register" hexmask.long.word 0x0 16.--31. 1. "REV_ID,revision" hexmask.long.word 0x0 0.--11. 1. "DEV_ID,device ID" group.long 0x4++0x3 line.long 0x0 "DBGMCU_CR,DBGMCU configuration register" bitfld.long 0x0 2. "DBGLP,Low power mode debug enable" "0: normal operation. In Stop LP-Stop LPLV-Stop..,1: automatic clock stop/power down disabled. All.." group.long 0x2C++0x3 line.long 0x0 "DBGMCU_APB4FZ,DBGMCU APB4 peripheral freeze register" bitfld.long 0x0 2. "IWDG2,IWDG2 stop in debug" "0: normal operation. IWDG2 continues to operate..,1: stop in debug. IWDG2 is frozen while.." group.long 0x34++0x3 line.long 0x0 "DBGMCU_APB1FZ,DBGMCU APB1 peripheral freeze register" bitfld.long 0x0 19. "I2C2,I2C2 SMBUS timeout stop in debug" "0: normal operation. I2C2 SMBUS timeout continues..,1: stop in debug. I2C2 SMBUS timeout is frozen.." bitfld.long 0x0 18. "I2C1,I2C1 SMBUS timeout stop in debug" "0: normal operation. I2C1 SMBUS timeout continues..,1: stop in debug. I2C1 SMBUS timeout is frozen.." newline bitfld.long 0x0 9. "LPTIM1,LPTIM1 stop in debug" "0: normal operation. LPTIM1 continues to operate..,1: stop in debug. LPTIM1 is frozen while the.." bitfld.long 0x0 5. "TIM7,TIM7 stop in debug" "0: normal operation. TIM7 continues to operate..,1: stop in debug. TIM7 is frozen while the.." newline bitfld.long 0x0 4. "TIM6,TIM6 stop in debug" "0: normal operation. TIM6 continues to operate..,1: stop in debug. TIM6 is frozen while the.." bitfld.long 0x0 3. "TIM5,TIM5 stop in debug" "0: normal operation. TIM5 continues to operate..,1: stop in debug. TIM5 is frozen while the.." newline bitfld.long 0x0 2. "TIM4,TIM4 stop in debug" "0: normal operation. TIM4 continues to operate..,1: stop in debug. TIM4 is frozen while the.." bitfld.long 0x0 1. "TIM3,TIM3 stop in debug" "0: normal operation. TIM3 continues to operate..,1: stop in debug. TIM3 is frozen while the.." newline bitfld.long 0x0 0. "TIM2,TIM2 stop in debug" "0: Normal operation. TIM2 continues to operate..,1: Stop in debug. TIM2 is frozen while the.." group.long 0x3C++0x3 line.long 0x0 "DBGMCU_APB2FZ,DBGMCU APB2 peripheral freeze register" bitfld.long 0x0 15. "FDCAN,FDCAN stop in debug" "0: normal operation. FDCAN continues to operate..,1: stop in debug. FDCAN is frozen while.." bitfld.long 0x0 1. "TIM8,TIM8 stop in debug" "0: normal operation. TIM8 continues to operate..,1: stop in debug. TIM8 is frozen while the.." newline bitfld.long 0x0 0. "TIM1,TIM1 stop in debug" "0: normal operation. TIM1 continues to operate..,1: stop in debug. TIM1 is frozen while the.." group.long 0x44++0x3 line.long 0x0 "DBGMCU_APB3FZ,DBGMCU APB3 peripheral freeze register" bitfld.long 0x0 4. "LPTIM5,LPTIM5 stop in debug" "0: normal operation. LPTIM5 continues to operate..,1: stop in debug. LPTIM5 is frozen while the.." bitfld.long 0x0 3. "LPTIM4,LPTIM4 stop in debug" "0: normal operation. LPTIM4 continues to operate..,1: stop in debug. LPTIM4 is frozen while the.." newline bitfld.long 0x0 2. "LPTIM3,LPTIM3 stop in debug" "0: normal operation. LPTIM3 continues to operate..,1: stop in debug. LPTIM3 is frozen while the.." bitfld.long 0x0 1. "LPTIM2,LPTIM2 stop in debug" "0: normal operation. LPTIM2 continues to operate..,1: stop in debug. LPTIM2 is frozen while the.." group.long 0x4C++0x3 line.long 0x0 "DBGMCU_APB5FZ,DBGMCU APB5 peripheral freeze register" bitfld.long 0x0 4. "RTC,RTC stop in debug" "0: normal operation. RTC continues to operate while..,1: stop in debug. RTC is frozen while the.." bitfld.long 0x0 3. "IWDG1,independent watchdog 1 stop in debug" "0: normal operation. Watchdog continues to count..,1: stop in debug. IWGD1 is frozen while the.." group.long 0x54++0x3 line.long 0x0 "DBGMCU_APB6FZ,DBGMCU APB6 peripheral freeze register" bitfld.long 0x0 12. "TIM17,TIM17 stop in debug" "0: normal operation. TIM17 continues to operate..,1: stop in debug. TIM17 is frozen while.." bitfld.long 0x0 11. "TIM16,TIM16 stop in debug" "0: normal operation. TIM16 continues to operate..,1: stop in debug. TIM16 is frozen while.." newline bitfld.long 0x0 10. "TIM15,TIM15 stop in debug" "0: normal operation. TIM15 continues to operate..,1: stop in debug. TIM15 is frozen while.." bitfld.long 0x0 9. "TIM14,TIM14 stop in debug" "0: normal operation. TIM14 continues to operate..,1: stop in debug. TIM14 is frozen while.." newline bitfld.long 0x0 8. "TIM13,TIM13 stop in debug" "0: normal operation. TIM13 continues to operate..,1: stop in debug. TIM13 is frozen while.." bitfld.long 0x0 7. "TIM12,TIM12 stop in debug" "0: normal operation. TIM12 continues to operate..,1: stop in debug. TIM12 is frozen while.." newline bitfld.long 0x0 6. "I2C5,I2C5 SMBUS stop in debug" "0: normal operation. I2C5 SMBUS timeout continues..,1: stop in debug. I2C5 SMBUS timeout is frozen.." bitfld.long 0x0 5. "I2C4,I2C4 SMBUS stop in debug" "0: normal operation. I2C4 SMBUS timeout continues..,1: stop in debug. I2C4 SMBUS timeout is frozen.." newline bitfld.long 0x0 4. "I2C3,I2C3 SMBUS stop in debug" "0: normal operation. I2C3 SMBUS timeout continues..,1: stop in debug. I2C3 SMBUS timeout is frozen.." rgroup.long 0xFD0++0x3 line.long 0x0 "DBGMCU_PIDR4,DBGMCU peripheral ID4 register" hexmask.long.byte 0x0 4.--7. 1. "SIZE,component memory size indicator" hexmask.long.byte 0x0 0.--3. 1. "DES_2,JEDEC continuation code" rgroup.long 0xFE0++0x1F line.long 0x0 "DBGMCU_PIDR0,DBGMCU peripheral ID0 register" hexmask.long.byte 0x0 0.--7. 1. "PART_0,bits [7:0] of the component part number" line.long 0x4 "DBGMCU_PIDR1,DBGMCU peripheral ID1 register" hexmask.long.byte 0x4 4.--7. 1. "DES_0,bits [3:0] of the JEDEC identity code" hexmask.long.byte 0x4 0.--3. 1. "PART_1,bits [11:8] of the component part number" line.long 0x8 "DBGMCU_PIDR2,DBGMCU peripheral ID2 register" hexmask.long.byte 0x8 4.--7. 1. "REVISION,incremental component design version" bitfld.long 0x8 3. "JEDEC,JEDEC assigned value usage" "?,1: the designer ID is specified by JEDEC (refer to.." newline bitfld.long 0x8 0.--2. "DES_1,bits [6:4] of the JEDEC identity code" "?,?,2: most significant three bits of the JEP106..,?,?,?,?,?" line.long 0xC "DBGMCU_PIDR3,DBGMCU peripheral ID3 register" hexmask.long.byte 0xC 4.--7. 1. "REVAND,minor fix indicator" hexmask.long.byte 0xC 0.--3. 1. "CMOD,customer modification indicator" line.long 0x10 "DBGMCU_CIDR0,DBGMCU component ID0 register" hexmask.long.byte 0x10 0.--7. 1. "PRMBL_0,bits [31:24] of component identification" line.long 0x14 "DBGMCU_CIDR1,DBGMCU component ID1 register" hexmask.long.byte 0x14 4.--7. 1. "CLASS,component class" hexmask.long.byte 0x14 0.--3. 1. "PRMBL_1,bits [19:16] of component identification." line.long 0x18 "DBGMCU_CIDR2,DBGMCU component ID2 register" hexmask.long.byte 0x18 0.--7. 1. "PRMBL_2,bits [15:8] of component identification" line.long 0x1C "DBGMCU_CIDR3,DBGMCU component ID3 register" hexmask.long.byte 0x1C 0.--7. 1. "PRMBL_3,bits [7:0] of component identification" tree.end endif sif (cpuis("STM32MP151*")||cpuis("STM32MP153*")||cpuis("STM32MP157*")) tree "DCMI (Digital Camera Interface)" base ad:0x4C006000 group.long 0x0++0x3 line.long 0x0 "DCMI_CR,DCMI control register" bitfld.long 0x0 20. "OELS,OELS" "0,1" bitfld.long 0x0 19. "LSM,LSM" "0,1" bitfld.long 0x0 18. "OEBS,OEBS" "0,1" bitfld.long 0x0 16.--17. "BSM,BSM" "0,1,2,3" bitfld.long 0x0 14. "ENABLE,ENABLE" "0,1" bitfld.long 0x0 10.--11. "EDM,EDM" "0,1,2,3" bitfld.long 0x0 8.--9. "FCRC,FCRC" "0,1,2,3" bitfld.long 0x0 7. "VSPOL,VSPOL" "0,1" bitfld.long 0x0 6. "HSPOL,HSPOL" "0,1" newline bitfld.long 0x0 5. "PCKPOL,PCKPOL" "0,1" bitfld.long 0x0 4. "ESS,ESS" "0,1" bitfld.long 0x0 3. "JPEG,JPEG" "0,1" bitfld.long 0x0 2. "CROP,CROP" "0,1" bitfld.long 0x0 1. "CM,CM" "0,1" bitfld.long 0x0 0. "CAPTURE,CAPTURE" "0,1" rgroup.long 0x4++0x7 line.long 0x0 "DCMI_SR,DCMI status register" bitfld.long 0x0 2. "FNE,FNE" "0,1" bitfld.long 0x0 1. "VSYNC,VSYNC" "0,1" bitfld.long 0x0 0. "HSYNC,HSYNC" "0,1" line.long 0x4 "DCMI_RIS,DCMI_RIS gives the raw interrupt status and is accessible in read only. When read. this register returns the status of the corresponding interrupt before masking with the DCMI_IER register value." bitfld.long 0x4 4. "LINE_RIS,LINE_RIS" "0,1" bitfld.long 0x4 3. "VSYNC_RIS,VSYNC_RIS" "0,1" bitfld.long 0x4 2. "ERR_RIS,ERR_RIS" "0,1" bitfld.long 0x4 1. "OVR_RIS,OVR_RIS" "0,1" bitfld.long 0x4 0. "FRAME_RIS,FRAME_RIS" "0,1" group.long 0xC++0x3 line.long 0x0 "DCMI_IER,The DCMI_IER register is used to enable interrupts. When one of the DCMI_IER bits is set. the corresponding interrupt is enabled. This register is accessible in both read and write." bitfld.long 0x0 4. "LINE_IE,LINE_IE" "0,1" bitfld.long 0x0 3. "VSYNC_IE,VSYNC_IE" "0,1" bitfld.long 0x0 2. "ERR_IE,ERR_IE" "0,1" bitfld.long 0x0 1. "OVR_IE,OVR_IE" "0,1" bitfld.long 0x0 0. "FRAME_IE,FRAME_IE" "0,1" rgroup.long 0x10++0x3 line.long 0x0 "DCMI_MIS,This DCMI_MIS register is a read-only register. When read. it returns the current masked status value (depending on the value in DCMI_IER) of the corresponding interrupt. A bit in this register is set if the corresponding enable bit in DCMI_IER.." bitfld.long 0x0 4. "LINE_MIS,LINE_MIS" "0,1" bitfld.long 0x0 3. "VSYNC_MIS,VSYNC_MIS" "0,1" bitfld.long 0x0 2. "ERR_MIS,ERR_MIS" "0,1" bitfld.long 0x0 1. "OVR_MIS,OVR_MIS" "0,1" bitfld.long 0x0 0. "FRAME_MIS,FRAME_MIS" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "DCMI_ICR,The DCMI_ICR register is write-only." bitfld.long 0x0 4. "LINE_ISC,LINE_ISC" "0,1" bitfld.long 0x0 3. "VSYNC_ISC,VSYNC_ISC" "0,1" bitfld.long 0x0 2. "ERR_ISC,ERR_ISC" "0,1" bitfld.long 0x0 1. "OVR_ISC,OVR_ISC" "0,1" bitfld.long 0x0 0. "FRAME_ISC,FRAME_ISC" "0,1" group.long 0x18++0xF line.long 0x0 "DCMI_ESCR,DCMI embedded synchronization code register" hexmask.long.byte 0x0 24.--31. 1. "FEC,FEC" hexmask.long.byte 0x0 16.--23. 1. "LEC,LEC" hexmask.long.byte 0x0 8.--15. 1. "LSC,LSC" hexmask.long.byte 0x0 0.--7. 1. "FSC,FSC" line.long 0x4 "DCMI_ESUR,DCMI embedded synchronization unmask register" hexmask.long.byte 0x4 24.--31. 1. "FEU,FEU" hexmask.long.byte 0x4 16.--23. 1. "LEU,LEU" hexmask.long.byte 0x4 8.--15. 1. "LSU,LSU" hexmask.long.byte 0x4 0.--7. 1. "FSU,FSU" line.long 0x8 "DCMI_CWSTRT,DCMI crop window start" hexmask.long.word 0x8 16.--28. 1. "VST,VST" hexmask.long.word 0x8 0.--13. 1. "HOFFCNT,HOFFCNT" line.long 0xC "DCMI_CWSIZE,DCMI crop window size" hexmask.long.word 0xC 16.--29. 1. "VLINE,VLINE" hexmask.long.word 0xC 0.--13. 1. "CAPCNT,CAPCNT" rgroup.long 0x28++0x3 line.long 0x0 "DCMI_DR,DCMI data register" hexmask.long.byte 0x0 24.--31. 1. "Byte3,Byte3" hexmask.long.byte 0x0 16.--23. 1. "Byte2,Byte2" hexmask.long.byte 0x0 8.--15. 1. "Byte1,Byte1" hexmask.long.byte 0x0 0.--7. 1. "Byte0,Byte0" tree.end endif tree "DDRCTRL (DDR3/LPDDR2/LPDDR3 Controller)" base ad:0x5A003000 group.long 0x0++0x7 line.long 0x0 "DDRCTRL_MSTR,DDRCTRL master register 0" hexmask.long.byte 0x0 16.--19. 1. "BURST_RDWR,SDRAM burst length used:" bitfld.long 0x0 15. "DLL_OFF_MODE,Set to 1 when the DDRCTRL and DRAM has to be put in DLL-off mode for low frequency operation." "0,1" newline bitfld.long 0x0 12.--13. "DATA_BUS_WIDTH,Selects proportion of DQ bus width that is used by the SDRAM" "0,1,2,3" bitfld.long 0x0 10. "EN_2T_TIMING_MODE,If 1 then the DDRCTRL uses 2T timing. Otherwise uses 1T timing. In 2T timing all command signals (except chip select) are held for 2 clocks on the SDRAM bus. The chip select is asserted on the second cycle of the command" "0,1" newline bitfld.long 0x0 9. "BURSTCHOP,When set enable burst-chop (BC4 or 8 on-the-fly) in DDR3/DDR4. The burst-chop for Reads is exercised only in HIF configurations (UMCTL2_INCL_ARB not set) and if in full bus width mode (MSTR.data_bus_width = 00) and if MEMC_BURST_LENGTH=8 or.." "0,1" bitfld.long 0x0 3. "LPDDR3,Selects LPDDR3 SDRAM" "0,1" newline bitfld.long 0x0 2. "LPDDR2,Selects LPDDR2 SDRAM" "0,1" bitfld.long 0x0 0. "DDR3,Selects DDR3 SDRAM" "0,1" line.long 0x4 "DDRCTRL_STAT,DDRCTRL operating mode status register" sif (cpuis("STM32MP13*")) rbitfld.long 0x4 12. "SELFREF_CAM_NOT_EMPTY,Self refresh with CAMs not empty. Set to 1 when Self Refresh is entered but CAMs are not drained. Cleared after exiting Self Refresh." "0,1" rbitfld.long 0x4 4.--5. "SELFREF_TYPE,Flags if Self Refresh (except LPDDR4) or SR-Powerdown (LPDDR4) is entered and if it was under Automatic Self Refresh control only or not." "0,1,2,3" newline rbitfld.long 0x4 0.--2. "OPERATING_MODE,Operating mode. This is 3-bits wide in configurations with mDDR/LPDDR2/LPDDR3/LPDDR4/DDR4 support and 2-bits in all other configurations." "0,1,2,3,4,5,6,7" endif sif (cpuis("STM32MP151*")) bitfld.long 0x4 12. "SELFREF_CAM_NOT_EMPTY,SELFREF_CAM_NOT_EMPTY" "0,1" newline endif sif (cpuis("STM32MP153*")) bitfld.long 0x4 12. "SELFREF_CAM_NOT_EMPTY,SELFREF_CAM_NOT_EMPTY" "0,1" endif sif (cpuis("STM32MP157*")) bitfld.long 0x4 12. "SELFREF_CAM_NOT_EMPTY,SELFREF_CAM_NOT_EMPTY" "0,1" newline endif sif (cpuis("STM32MP151*")) bitfld.long 0x4 4.--5. "SELFREF_TYPE,SELFREF_TYPE" "0,1,2,3" endif sif (cpuis("STM32MP153*")) bitfld.long 0x4 4.--5. "SELFREF_TYPE,SELFREF_TYPE" "0,1,2,3" newline endif sif (cpuis("STM32MP157*")) bitfld.long 0x4 4.--5. "SELFREF_TYPE,SELFREF_TYPE" "0,1,2,3" endif sif (cpuis("STM32MP151*")) bitfld.long 0x4 0.--2. "OPERATING_MODE,OPERATING_MODE" "0,1,2,3,4,5,6,7" newline endif sif (cpuis("STM32MP153*")) bitfld.long 0x4 0.--2. "OPERATING_MODE,OPERATING_MODE" "0,1,2,3,4,5,6,7" endif sif (cpuis("STM32MP157*")) bitfld.long 0x4 0.--2. "OPERATING_MODE,OPERATING_MODE" "0,1,2,3,4,5,6,7" endif group.long 0x10++0xB line.long 0x0 "DDRCTRL_MRCTRL0,DDRCTRL mode register read/write control register 0" bitfld.long 0x0 31. "MR_WR,Setting this register bit to 1 triggers a mode register read or write operation. When the MR operation is complete the DDRCTRL automatically clears this bit. The other register fields of this register must be written in a separate APB transaction .." "0,1" hexmask.long.byte 0x0 12.--15. 1. "MR_ADDR,Address of the mode register that is to be written to." newline sif (cpuis("STM32MP151*")) bitfld.long 0x0 4. "MR_RANK,MR_RANK" "0,1" endif sif (cpuis("STM32MP153*")) bitfld.long 0x0 4. "MR_RANK,MR_RANK" "0,1" newline endif sif (cpuis("STM32MP157*")) bitfld.long 0x0 4. "MR_RANK,MR_RANK" "0,1" endif bitfld.long 0x0 0. "MR_TYPE,Indicates whether the mode register operation is read or write. Only used for LPDDR2/LPDDR3/LPDDR4/DDR4." "0,1" line.long 0x4 "DDRCTRL_MRCTRL1,DDRCTRL mode register read/write control register 1" hexmask.long.word 0x4 0.--15. 1. "MR_DATA,Mode register write data for all non-LPDDR2/non-LPDDR3/non-LPDDR4 modes." line.long 0x8 "DDRCTRL_MRSTAT,DDRCTRL mode register read/write status register" sif (cpuis("STM32MP13*")) rbitfld.long 0x8 0. "MR_WR_BUSY,The SoC core may initiate a MR write operation only if this signal is low. This signal goes high in the clock after the DDRCTRL accepts the MRW/MRR request. It goes low when the MRW/MRR command is issued to the SDRAM. It is recommended not to.." "0,1" endif sif (cpuis("STM32MP151*")) bitfld.long 0x8 0. "MR_WR_BUSY,MR_WR_BUSY" "0,1" newline endif sif (cpuis("STM32MP153*")) bitfld.long 0x8 0. "MR_WR_BUSY,MR_WR_BUSY" "0,1" endif sif (cpuis("STM32MP157*")) bitfld.long 0x8 0. "MR_WR_BUSY,MR_WR_BUSY" "0,1" endif group.long 0x20++0x7 line.long 0x0 "DDRCTRL_DERATEEN,DDRCTRL temperature derate enable register" hexmask.long.byte 0x0 4.--7. 1. "DERATE_BYTE,Derate byte" bitfld.long 0x0 1.--2. "DERATE_VALUE,Derate value" "0,1,2,3" newline bitfld.long 0x0 0. "DERATE_ENABLE,Enables derating" "0,1" line.long 0x4 "DDRCTRL_DERATEINT,DDRCTRL temperature derate interval register" hexmask.long 0x4 0.--31. 1. "MR4_READ_INTERVAL,Interval between two MR4 reads used to derate the timing parameters." group.long 0x30++0xB line.long 0x0 "DDRCTRL_PWRCTL,DDRCTRL low power control register" bitfld.long 0x0 7. "DIS_CAM_DRAIN_SELFREF,Indicates whether skipping CAM draining is allowed when entering Self-Refresh." "0,1" bitfld.long 0x0 5. "SELFREF_SW,A value of 1 to this register causes system to move to Self Refresh state immediately as long as it is not in INIT or DPD/MPSM operating_mode. This is referred to as Software Entry/Exit to Self Refresh." "0,1" newline bitfld.long 0x0 3. "EN_DFI_DRAM_CLK_DISABLE,Enable the assertion of dfi_dram_clk_disable whenever a clock is not required by the SDRAM." "0,1" bitfld.long 0x0 2. "DEEPPOWERDOWN_EN,When this is 1 DDRCTRL puts the SDRAM into deep power-down mode when the transaction store is empty." "0,1" newline bitfld.long 0x0 1. "POWERDOWN_EN,If true then the DDRCTRL goes into power-down after a programmable number of cycles 'maximum idle clocks before power down' (PWRTMG.powerdown_to_x32)." "0,1" bitfld.long 0x0 0. "SELFREF_EN,If true then the DDRCTRL puts the SDRAM into Self Refresh after a programmable number of cycles 'maximum idle clocks before Self Refresh (PWRTMG.selfref_to_x32)'. This register bit may be re-programmed during the course of normal operation." "0,1" line.long 0x4 "DDRCTRL_PWRTMG,DDRCTRL low power timing register" hexmask.long.byte 0x4 16.--23. 1. "SELFREF_TO_X32,After this many clocks of the DDRC command channel being idle the DDRCTRL automatically puts the SDRAM into Self Refresh. The DDRC command channel is considered idle when there are no HIF commands outstanding. This must be enabled in the.." hexmask.long.byte 0x4 8.--15. 1. "T_DPD_X4096,Minimum deep power-down time." newline hexmask.long.byte 0x4 0.--4. 1. "POWERDOWN_TO_X32,After this many clocks of the DDRC command channel being idle the DDRCTRL automatically puts the SDRAM into power-down. The DDRC command channel is considered idle when there are no HIF commands outstanding. This must be enabled in the.." line.long 0x8 "DDRCTRL_HWLPCTL,DDRCTRL hardware low power control register" hexmask.long.word 0x8 16.--27. 1. "HW_LP_IDLE_X32,Hardware idle period. The cactive_ddrc output is driven low if the DDRC command channel is idle for hw_lp_idle * 32 cycles if not in INIT or DPD/MPSM operating_mode. The DDRC command channel is considered idle when there are no HIF.." bitfld.long 0x8 1. "HW_LP_EXIT_IDLE_EN,When this bit is programmed to 1 the cactive_in_ddrc pin of the DDRC can be used to exit from the automatic clock stop automatic power down or automatic self-refresh modes. Note it does not cause exit of Self-Refresh that is caused.." "0,1" newline bitfld.long 0x8 0. "HW_LP_EN,Enable for hardware low power interface." "0,1" group.long 0x50++0x3 line.long 0x0 "DDRCTRL_RFSHCTL0,DDRCTRL refresh control register 0" hexmask.long.byte 0x0 20.--23. 1. "REFRESH_MARGIN,Threshold value in number of DFI clock cycles before the critical refresh or page timer expires. A critical refresh is to be issued before this threshold is reached. It is recommended that this not be changed from the default value .." hexmask.long.byte 0x0 12.--16. 1. "REFRESH_TO_X32,If the refresh timer (tRFCnom also known as tREFI) has expired at least once but it has not expired (RFSHCTL0.refresh_burst+1) times yet then a speculative refresh may be performed. A speculative refresh is a refresh performed at a time.." newline hexmask.long.byte 0x0 4.--8. 1. "REFRESH_BURST,The programmed value + 1 is the number of refresh timeouts that is allowed to accumulate before traffic is blocked and the refreshes are forced to execute. Closing pages to perform a refresh is a one-time penalty that must be paid for each.." bitfld.long 0x0 2. "PER_BANK_REFRESH,- 1 - Per bank refresh;" "0,1" group.long 0x60++0x7 line.long 0x0 "DDRCTRL_RFSHCTL3,DDRCTRL refresh control register 3" bitfld.long 0x0 1. "REFRESH_UPDATE_LEVEL,Toggles this signal (either from 0 to 1 or from 1 to 0) to indicate that the refresh register(s) have been updated." "0,1" bitfld.long 0x0 0. "DIS_AUTO_REFRESH,When '1' disable auto-refresh generated by the DDRCTRL. When auto-refresh is disabled the SoC core must generate refreshes using the registers DBGCMD.rankn_refresh." "0,1" line.long 0x4 "DDRCTRL_RFSHTMG,DDRCTRL refresh timing register" bitfld.long 0x4 31. "T_RFC_NOM_X1_SEL,Specifies whether the t_rfc_nom_x1_x32 register value is x1 or x32." "0,1" hexmask.long.word 0x4 16.--27. 1. "T_RFC_NOM_X1_X32,tREFI: Average time interval between refreshes per rank (Specification: 7.8us for DDR2 DDR3 and DDR4. See JEDEC specification for mDDR LPDDR2 LPDDR3 and LPDDR4)." newline bitfld.long 0x4 15. "LPDDR3_TREFBW_EN,Used only when LPDDR3 memory type is connected. Should only be changed when DDRCTRL is in reset. Specifies whether to use the tREFBW parameter (required by some LPDDR3 devices which comply with earlier versions of the LPDDR3 JEDEC.." "0,1" hexmask.long.word 0x4 0.--9. 1. "T_RFC_MIN,tRFC (min): Minimum time from refresh to refresh or activate." group.long 0xC0++0x3 line.long 0x0 "DDRCTRL_CRCPARCTL0,DDRCTRL CRC parity control register 0" bitfld.long 0x0 2. "DFI_ALERT_ERR_CNT_CLR,DFI alert error count clear. Clear bit for DFI alert error counter. Asserting this bit clears the DFI alert error counter CRCPARSTAT.dfi_alert_err_cnt. When the clear operation is complete the DDRCTRL automatically clears this bit." "0,1" bitfld.long 0x0 1. "DFI_ALERT_ERR_INT_CLR,Interrupt clear bit for DFI alert error. If this bit is set the alert error interrupt on CRCPARSTAT.dfi_alert_err_int is cleared. When the clear operation is complete the DDRCTRL automatically clears this bit." "0,1" newline bitfld.long 0x0 0. "DFI_ALERT_ERR_INT_EN,Interrupt enable bit for DFI alert error. If this bit is set any parity/CRC error detected on the dfi_alert_n input results in an interrupt being set on CRCPARSTAT.dfi_alert_err_int." "0,1" group.long 0xCC++0x1B line.long 0x0 "DDRCTRL_CRCPARSTAT,DDRCTRL CRC parity status register" sif (cpuis("STM32MP13*")) rbitfld.long 0x0 16. "DFI_ALERT_ERR_INT,DFI alert error interrupt." "0,1" hexmask.long.word 0x0 0.--15. 1. "DFI_ALERT_ERR_CNT,DFI alert error count." newline endif sif (cpuis("STM32MP151*")) bitfld.long 0x0 16. "DFI_ALERT_ERR_INT,DFI_ALERT_ERR_INT" "0,1" hexmask.long.word 0x0 0.--15. 1. "DFI_ALERT_ERR_CNT,DFI_ALERT_ERR_CNT" newline endif sif (cpuis("STM32MP153*")) bitfld.long 0x0 16. "DFI_ALERT_ERR_INT,DFI_ALERT_ERR_INT" "0,1" hexmask.long.word 0x0 0.--15. 1. "DFI_ALERT_ERR_CNT,DFI_ALERT_ERR_CNT" newline endif sif (cpuis("STM32MP157*")) bitfld.long 0x0 16. "DFI_ALERT_ERR_INT,DFI_ALERT_ERR_INT" "0,1" hexmask.long.word 0x0 0.--15. 1. "DFI_ALERT_ERR_CNT,DFI_ALERT_ERR_CNT" endif line.long 0x4 "DDRCTRL_INIT0,DDRCTRL SDRAM initialization register 0" bitfld.long 0x4 30.--31. "SKIP_DRAM_INIT,If lower bit is enabled the SDRAM initialization routine is skipped. The upper bit decides what state the controller starts up in when reset is removed" "0,1,2,3" hexmask.long.word 0x4 16.--25. 1. "POST_CKE_X1024,Cycles to wait after driving CKE high to start the SDRAM initialization sequence." newline hexmask.long.word 0x4 0.--11. 1. "PRE_CKE_X1024,Cycles to wait after reset before driving CKE high to start the SDRAM initialization sequence." line.long 0x8 "DDRCTRL_INIT1,DDRCTRL SDRAM initialization register 1" hexmask.long.word 0x8 16.--24. 1. "DRAM_RSTN_X1024,Number of cycles to assert SDRAM reset signal during init sequence." hexmask.long.byte 0x8 0.--3. 1. "PRE_OCD_X32,Wait period before driving the OCD complete command to SDRAM." line.long 0xC "DDRCTRL_INIT2,DDRCTRL SDRAM initialization register 2" hexmask.long.byte 0xC 8.--15. 1. "IDLE_AFTER_RESET_X32,Idle time after the reset command tINIT4. Present only in designs configured to support LPDDR2." hexmask.long.byte 0xC 0.--3. 1. "MIN_STABLE_CLOCK_X1,Time to wait after the first CKE high tINIT2. Present only in designs configured to support LPDDR2/LPDDR3." line.long 0x10 "DDRCTRL_INIT3,DDRCTRL SDRAM initialization register 3" hexmask.long.word 0x10 16.--31. 1. "MR,DDR2: Value to write to MR register. Bit 8 is for DLL and the setting here is ignored. The DDRCTRL sets this bit appropriately." hexmask.long.word 0x10 0.--15. 1. "EMR,DDR2: Value to write to EMR register. Bits 9:7 are for OCD and the setting in this register is ignored. The DDRCTRL sets those bits appropriately." line.long 0x14 "DDRCTRL_INIT4,DDRCTRL SDRAM initialization register 4" hexmask.long.word 0x14 16.--31. 1. "EMR2,DDR2: Value to write to EMR2 register." hexmask.long.word 0x14 0.--15. 1. "EMR3,DDR2: Value to write to EMR3 register." line.long 0x18 "DDRCTRL_INIT5,DDRCTRL SDRAM initialization register 5" hexmask.long.byte 0x18 16.--23. 1. "DEV_ZQINIT_X32,ZQ initial calibration tZQINIT. Present only in designs configured to support DDR3 or DDR4 or LPDDR2/LPDDR3." hexmask.long.word 0x18 0.--9. 1. "MAX_AUTO_INIT_X1024,Maximum duration of the auto initialization tINIT5. Present only in designs configured to support LPDDR2/LPDDR3." group.long 0xF0++0x3 line.long 0x0 "DDRCTRL_DIMMCTL,DDRCTRL DIMM control register" bitfld.long 0x0 1. "DIMM_ADDR_MIRR_EN,Address Mirroring Enable (for multi-rank UDIMM implementations and multi-rank DDR4 RDIMM/LRDIMM implementations)." "0,1" bitfld.long 0x0 0. "DIMM_STAGGER_CS_EN,Staggering enable for multi-rank accesses (for multi-rank UDIMM RDIMM and LRDIMM implementations only). This is not supported for mDDR LPDDR2 LPDDR3 or LPDDR4 SDRAMs." "0,1" group.long 0x100++0x23 line.long 0x0 "DDRCTRL_DRAMTMG0,DDRCTRL SDRAM timing register 0" hexmask.long.byte 0x0 24.--30. 1. "WR2PRE,Minimum time between write and precharge to same bank." hexmask.long.byte 0x0 16.--21. 1. "T_FAW,tFAW Valid only when 8 or more banks(or banks x bank groups) are present." newline hexmask.long.byte 0x0 8.--14. 1. "T_RAS_MAX,tRAS(max): Maximum time between activate and precharge to same bank. This is the maximum time that a page can be kept open" hexmask.long.byte 0x0 0.--5. 1. "T_RAS_MIN,tRAS(min): Minimum time between activate and precharge to the same bank." line.long 0x4 "DDRCTRL_DRAMTMG1,DDRCTRL SDRAM timing register 1" hexmask.long.byte 0x4 16.--20. 1. "T_XP,tXP: Minimum time after power-down exit to any operation. For DDR3 this should be programmed to tXPDLL if slow powerdown exit is selected in MR0[12]." hexmask.long.byte 0x4 8.--13. 1. "RD2PRE,tRTP: Minimum time from read to precharge of same bank." newline hexmask.long.byte 0x4 0.--6. 1. "T_RC,tRC: Minimum time between activates to same bank." line.long 0x8 "DDRCTRL_DRAMTMG2,DDRCTRL SDRAM timing register 2" hexmask.long.byte 0x8 24.--29. 1. "WRITE_LATENCY,Set to WL" hexmask.long.byte 0x8 16.--21. 1. "READ_LATENCY,Set to RL" newline hexmask.long.byte 0x8 8.--13. 1. "RD2WR,DDR2/3/mDDR: RL + BL/2 + 2 - WL" hexmask.long.byte 0x8 0.--5. 1. "WR2RD,DDR4: CWL + PL + BL/2 + tWTR_L" line.long 0xC "DDRCTRL_DRAMTMG3,DDRCTRL SDRAM timing register 3" hexmask.long.word 0xC 20.--29. 1. "T_MRW,Time to wait after a mode register write or read (MRW or MRR)." hexmask.long.byte 0xC 12.--17. 1. "T_MRD,tMRD: Cycles to wait after a mode register write or read. Depending on the connected SDRAM tMRD represents:" newline hexmask.long.word 0xC 0.--9. 1. "T_MOD,tMOD: Parameter used only in DDR3 and DDR4. Cycles between load mode command and following non-load mode command." line.long 0x10 "DDRCTRL_DRAMTMG4,DDRCTRL SDRAM timing register 4" hexmask.long.byte 0x10 24.--28. 1. "T_RCD,tRCD - tAL: Minimum time from activate to read or write command to same bank." hexmask.long.byte 0x10 16.--19. 1. "T_CCD,DDR4: tCCD_L: This is the minimum time between two reads or two writes for same bank group." newline hexmask.long.byte 0x10 8.--11. 1. "T_RRD,DDR4: tRRD_L: Minimum time between activates from bank 'a' to bank 'b' for same bank group." hexmask.long.byte 0x10 0.--4. 1. "T_RP,tRP: Minimum time from precharge to activate of same bank." line.long 0x14 "DDRCTRL_DRAMTMG5,DDRCTRL SDRAM timing register 5" hexmask.long.byte 0x14 24.--27. 1. "T_CKSRX,This is the time before Self Refresh Exit that CK is maintained as a valid clock before issuing SRX. Specifies the clock stable time before SRX." hexmask.long.byte 0x14 16.--19. 1. "T_CKSRE,This is the time after Self Refresh Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after SRE." newline hexmask.long.byte 0x14 8.--13. 1. "T_CKESR,Minimum CKE low width for Self refresh or Self refresh power down entry to exit timing in memory clock cycles." hexmask.long.byte 0x14 0.--4. 1. "T_CKE,Minimum number of cycles of CKE HIGH/LOW during power-down and self refresh." line.long 0x18 "DDRCTRL_DRAMTMG6,DDRCTRL SDRAM timing register 6" hexmask.long.byte 0x18 24.--27. 1. "T_CKDPDE,This is the time after Deep Power Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after DPDE." hexmask.long.byte 0x18 16.--19. 1. "T_CKDPDX,This is the time before Deep Power Down Exit that CK is maintained as a valid clock before issuing DPDX. Specifies the clock stable time before DPDX." newline hexmask.long.byte 0x18 0.--3. 1. "T_CKCSX,This is the time before Clock Stop Exit that CK is maintained as a valid clock before issuing Clock Stop Exit. Specifies the clock stable time before next command after Clock Stop Exit." line.long 0x1C "DDRCTRL_DRAMTMG7,DDRCTRL SDRAM timing register 7" hexmask.long.byte 0x1C 8.--11. 1. "T_CKPDE,This is the time after Power Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after PDE." hexmask.long.byte 0x1C 0.--3. 1. "T_CKPDX,This is the time before Power Down Exit that CK is maintained as a valid clock before issuing PDX. Specifies the clock stable time before PDX." line.long 0x20 "DDRCTRL_DRAMTMG8,DDRCTRL SDRAM timing register 8" hexmask.long.byte 0x20 8.--14. 1. "T_XS_DLL_X32,tXSDLL: Exit Self Refresh to the commands requiring a locked DLL." hexmask.long.byte 0x20 0.--6. 1. "T_XS_X32,tXS: Exit Self Refresh to commands not requiring a locked DLL." group.long 0x138++0x7 line.long 0x0 "DDRCTRL_DRAMTMG14,DDRCTRL SDRAM timing register 14" hexmask.long.word 0x0 0.--11. 1. "T_XSR,tXSR: Exit Self Refresh to any command." line.long 0x4 "DDRCTRL_DRAMTMG15,DDRCTRL SDRAM timing register 15" bitfld.long 0x4 31. "EN_DFI_LP_T_STAB,- 1 - Enable using tSTAB when exiting DFI LP. Needs to be set when the PHY is stopping the clock during DFI LP to save maximum power." "0,1" hexmask.long.byte 0x4 0.--7. 1. "T_STAB_X32,tSTAB: Stabilization time." group.long 0x180++0x1B line.long 0x0 "DDRCTRL_ZQCTL0,DDRCTRL ZQ control register 0" bitfld.long 0x0 31. "DIS_AUTO_ZQ,- 1 - Disable DDRCTRL generation of ZQCS/MPC(ZQ calibration) command. Register DBGCMD.zq_calib_short can be used instead to issue ZQ calibration request from APB module." "0,1" bitfld.long 0x0 30. "DIS_SRX_ZQCL,- 1 - Disable issuing of ZQCL/MPC(ZQ calibration) command at Self-Refresh/SR-Powerdown exit. Only applicable when run in DDR3 or DDR4 or LPDDR2 or LPDDR3 or LPDDR4 mode." "0,1" newline bitfld.long 0x0 29. "ZQ_RESISTOR_SHARED,- 1 - Denotes that ZQ resistor is shared between ranks. Means ZQinit/ZQCL/ZQCS/MPC(ZQ calibration) commands are sent to one rank at a time with tZQinit/tZQCL/tZQCS/tZQCAL/tZQLAT timing met between commands so that commands to different.." "0,1" hexmask.long.word 0x0 16.--26. 1. "T_ZQ_LONG_NOP,tZQoper for DDR3/DDR4 tZQCL for LPDDR2/LPDDR3 tZQCAL for LPDDR4: Number of DFI clock cycles of NOP required after a ZQCL (ZQ calibration long)/MPC(ZQ Start) command is issued to SDRAM." newline hexmask.long.word 0x0 0.--9. 1. "T_ZQ_SHORT_NOP,tZQCS for DDR3/DD4/LPDDR2/LPDDR3 tZQLAT for LPDDR4: Number of DFI clock cycles of NOP required after a ZQCS (ZQ calibration short)/MPC(ZQ Latch) command is issued to SDRAM." line.long 0x4 "DDRCTRL_ZQCTL1,DDRCTRL ZQ control register 1" hexmask.long.word 0x4 20.--29. 1. "T_ZQ_RESET_NOP,tZQReset: Number of DFI clock cycles of NOP required after a ZQReset (ZQ calibration Reset) command is issued to SDRAM." hexmask.long.tbyte 0x4 0.--19. 1. "T_ZQ_SHORT_INTERVAL_X1024,Average interval to wait between automatically issuing ZQCS (ZQ calibration short)/MPC(ZQ calibration) commands to DDR3/DDR4/LPDDR2/LPDDR3/LPDDR4 devices." line.long 0x8 "DDRCTRL_ZQCTL2,DDRCTRL ZQ control register 2" bitfld.long 0x8 0. "ZQ_RESET,Setting this register bit to 1 triggers a ZQ Reset operation. When the ZQ Reset operation is complete the DDRCTRL automatically clears this bit. It is recommended NOT to set this register bit if in Init in Self-Refresh(except LPDDR4) or.." "0,1" line.long 0xC "DDRCTRL_ZQSTAT,DDRCTRL ZQ status register" sif (cpuis("STM32MP13*")) rbitfld.long 0xC 0. "ZQ_RESET_BUSY,SoC core may initiate a ZQ Reset operation only if this signal is low. This signal goes high in the clock after the DDRCTRL accepts the ZQ Reset request. It goes low when the ZQ Reset command is issued to the SDRAM and the associated NOP.." "0,1" endif sif (cpuis("STM32MP151*")) bitfld.long 0xC 0. "ZQ_RESET_BUSY,ZQ_RESET_BUSY" "0,1" newline endif sif (cpuis("STM32MP153*")) bitfld.long 0xC 0. "ZQ_RESET_BUSY,ZQ_RESET_BUSY" "0,1" endif sif (cpuis("STM32MP157*")) bitfld.long 0xC 0. "ZQ_RESET_BUSY,ZQ_RESET_BUSY" "0,1" endif line.long 0x10 "DDRCTRL_DFITMG0,DDRCTRL DFI timing register 0" hexmask.long.byte 0x10 24.--28. 1. "DFI_T_CTRL_DELAY,Specifies the number of DFI clock cycles after an assertion or de-assertion of the DFI control signals that the control signals at the PHY-DRAM interface reflect the assertion or de-assertion. If the DFI clock and the memory clock are.." hexmask.long.byte 0x10 16.--22. 1. "DFI_T_RDDATA_EN,Time from the assertion of a read command on the DFI interface to the assertion of the dfi_rddata_en signal." newline hexmask.long.byte 0x10 8.--13. 1. "DFI_TPHY_WRDATA,Specifies the number of clock cycles between when dfi_wrdata_en is asserted to when the associated write data is driven on the dfi_wrdata signal. This corresponds to the DFI timing parameter tphy_wrdata. Refer to PHY specification for.." hexmask.long.byte 0x10 0.--5. 1. "DFI_TPHY_WRLAT,Write latency" line.long 0x14 "DDRCTRL_DFITMG1,DDRCTRL DFI timing register 1" hexmask.long.byte 0x14 16.--20. 1. "DFI_T_WRDATA_DELAY,Specifies the number of DFI clock cycles between when the dfi_wrdata_en" hexmask.long.byte 0x14 8.--12. 1. "DFI_T_DRAM_CLK_DISABLE,Specifies the number of DFI clock cycles from the assertion of the dfi_dram_clk_disable signal on the DFI until the clock to the DRAM memory devices at the PHY-DRAM boundary maintains a low value. If the DFI clock and the memory.." newline hexmask.long.byte 0x14 0.--4. 1. "DFI_T_DRAM_CLK_ENABLE,Specifies the number of DFI clock cycles from the de-assertion of the dfi_dram_clk_disable signal on the DFI until the first valid rising edge of the clock to the DRAM memory devices at the PHY-DRAM boundary. If the DFI clock and.." line.long 0x18 "DDRCTRL_DFILPCFG0,DDRCTRL low power configuration register 0" hexmask.long.byte 0x18 24.--28. 1. "DFI_TLP_RESP,Setting in DFI clock cycles for DFI's tlp_resp time." hexmask.long.byte 0x18 20.--23. 1. "DFI_LP_WAKEUP_DPD,Value in DFI clock cycles to drive on dfi_lp_wakeup signal when Deep Power Down mode is entered." newline bitfld.long 0x18 16. "DFI_LP_EN_DPD,Enables DFI Low-power interface handshaking during Deep Power Down Entry/Exit." "0,1" hexmask.long.byte 0x18 12.--15. 1. "DFI_LP_WAKEUP_SR,Value in DFI clpck cycles to drive on dfi_lp_wakeup signal when Self Refresh mode is entered." newline bitfld.long 0x18 8. "DFI_LP_EN_SR,Enables DFI Low Power interface handshaking during Self Refresh Entry/Exit." "0,1" hexmask.long.byte 0x18 4.--7. 1. "DFI_LP_WAKEUP_PD,Value in DFI clock cycles to drive on dfi_lp_wakeup signal when Power Down mode is entered." newline bitfld.long 0x18 0. "DFI_LP_EN_PD,Enables DFI Low Power interface handshaking during Power Down Entry/Exit." "0,1" group.long 0x1A0++0xB line.long 0x0 "DDRCTRL_DFIUPD0,DDRCTRL DFI update register 0" bitfld.long 0x0 31. "DIS_AUTO_CTRLUPD,When '1' disable the automatic dfi_ctrlupd_req generation by the DDRCTRL. The core must issue the dfi_ctrlupd_req signal using register DBGCMD.ctrlupd." "0,1" bitfld.long 0x0 30. "DIS_AUTO_CTRLUPD_SRX,When '1' disable the automatic dfi_ctrlupd_req generation by the DDRCTRL at self-refresh exit." "0,1" newline bitfld.long 0x0 29. "CTRLUPD_PRE_SRX,Selects dfi_ctrlupd_req requirements at SRX:" "0,1" hexmask.long.word 0x0 16.--25. 1. "DFI_T_CTRLUP_MAX,Specifies the maximum number of DFI clock cycles that the dfi_ctrlupd_req signal can assert. Lowest value to assign to this variable is 0x40." newline hexmask.long.word 0x0 0.--9. 1. "DFI_T_CTRLUP_MIN,Specifies the minimum number of DFI clock cycles that the dfi_ctrlupd_req signal must be asserted. The DDRCTRL expects the PHY to respond within this time. If the PHY does not respond the DDRCTRL de-asserts dfi_ctrlupd_req after.." line.long 0x4 "DDRCTRL_DFIUPD1,DDRCTRL DFI update register 1" hexmask.long.byte 0x4 16.--23. 1. "DFI_T_CTRLUPD_INTERVAL_MIN_X1024,This is the minimum amount of time between DDRCTRL initiated DFI update requests (which is executed whenever the DDRCTRL is idle). Set this number higher to reduce the frequency of update requests which can have a small.." hexmask.long.byte 0x4 0.--7. 1. "DFI_T_CTRLUPD_INTERVAL_MAX_X1024,This is the maximum amount of time between DDRCTRL initiated DFI update requests. This timer resets with each update request; when the timer expires dfi_ctrlupd_req is sent and traffic is blocked until the.." line.long 0x8 "DDRCTRL_DFIUPD2,DDRCTRL DFI update register 2" bitfld.long 0x8 31. "DFI_PHYUPD_EN,Enables the support for acknowledging PHY-initiated updates:" "0,1" group.long 0x1B0++0x3 line.long 0x0 "DDRCTRL_DFIMISC,DDRCTRL DFI miscellaneous control register" hexmask.long.byte 0x0 8.--12. 1. "DFI_FREQUENCY,Indicates the operating frequency of the system. The number of supported frequencies and the mapping of signal values to clock frequencies are defined by the PHY." bitfld.long 0x0 5. "DFI_INIT_START,PHY init start request signal.When asserted it triggers the PHY init start request" "0,1" newline bitfld.long 0x0 4. "CTL_IDLE_EN,Enables support of ctl_idle signal" "0,1" bitfld.long 0x0 0. "DFI_INIT_COMPLETE_EN,PHY initialization complete enable signal." "0,1" group.long 0x1BC++0x3 line.long 0x0 "DDRCTRL_DFISTAT,DDRCTRL DFI status register" sif (cpuis("STM32MP13*")) rbitfld.long 0x0 1. "DFI_LP_ACK,Stores the value of the dfi_lp_ack input to the controller." "0,1" rbitfld.long 0x0 0. "DFI_INIT_COMPLETE,The status flag register which announces when the DFI initialization has been completed. The DFI INIT triggered by dfi_init_start signal and then the dfi_init_complete flag is polled to know when the initialization is done." "0,1" newline endif sif (cpuis("STM32MP151*")) bitfld.long 0x0 1. "DFI_LP_ACK,DFI_LP_ACK" "0,1" bitfld.long 0x0 0. "DFI_INIT_COMPLETE,DFI_INIT_COMPLETE" "0,1" newline endif sif (cpuis("STM32MP153*")) bitfld.long 0x0 1. "DFI_LP_ACK,DFI_LP_ACK" "0,1" bitfld.long 0x0 0. "DFI_INIT_COMPLETE,DFI_INIT_COMPLETE" "0,1" newline endif sif (cpuis("STM32MP157*")) bitfld.long 0x0 1. "DFI_LP_ACK,DFI_LP_ACK" "0,1" bitfld.long 0x0 0. "DFI_INIT_COMPLETE,DFI_INIT_COMPLETE" "0,1" endif group.long 0x1C4++0x3 line.long 0x0 "DDRCTRL_DFIPHYMSTR,DDRCTRL DFI PHY master register" bitfld.long 0x0 0. "DFI_PHYMSTR_EN,Enables the PHY Master Interface:" "0,1" group.long 0x204++0x17 line.long 0x0 "DDRCTRL_ADDRMAP1,DDRCTRL address map register 1" hexmask.long.byte 0x0 16.--21. 1. "ADDRMAP_BANK_B2,Selects the HIF address bit used as bank address bit 2." hexmask.long.byte 0x0 8.--13. 1. "ADDRMAP_BANK_B1,Selects the HIF address bits used as bank address bit 1." newline hexmask.long.byte 0x0 0.--5. 1. "ADDRMAP_BANK_B0,Selects the HIF address bits used as bank address bit 0." line.long 0x4 "DDRCTRL_ADDRMAP2,DDRCTRL address map register 2" hexmask.long.byte 0x4 24.--27. 1. "ADDRMAP_COL_B5,- Full bus width mode: Selects the HIF address bit used as column address bit 5." hexmask.long.byte 0x4 16.--19. 1. "ADDRMAP_COL_B4,- Full bus width mode: Selects the HIF address bit used as column address bit 4." newline hexmask.long.byte 0x4 8.--11. 1. "ADDRMAP_COL_B3,- Full bus width mode: Selects the HIF address bit used as column address bit 3." hexmask.long.byte 0x4 0.--3. 1. "ADDRMAP_COL_B2,- Full bus width mode: Selects the HIF address bit used as column address bit 2." line.long 0x8 "DDRCTRL_ADDRMAP3,DDRCTRL address map register 3" hexmask.long.byte 0x8 24.--28. 1. "ADDRMAP_COL_B9,- Full bus width mode: Selects the HIF address bit used as column address bit 9." hexmask.long.byte 0x8 16.--20. 1. "ADDRMAP_COL_B8,- Full bus width mode: Selects the HIF address bit used as column address bit 8." newline hexmask.long.byte 0x8 8.--12. 1. "ADDRMAP_COL_B7,- Full bus width mode: Selects the HIF address bit used as column address bit 7." hexmask.long.byte 0x8 0.--3. 1. "ADDRMAP_COL_B6,- Full bus width mode: Selects the HIF address bit used as column address bit 6." line.long 0xC "DDRCTRL_ADDRMAP4,DDRCTRL address map register 4" hexmask.long.byte 0xC 8.--12. 1. "ADDRMAP_COL_B11,- Full bus width mode: Selects the HIF address bit used as column address bit 13 (11 in LPDDR2/LPDDR3 mode)." hexmask.long.byte 0xC 0.--4. 1. "ADDRMAP_COL_B10,- Full bus width mode: Selects the HIF address bit used as column address bit 11 (10 in LPDDR2/LPDDR3 mode)." line.long 0x10 "DDRCTRL_ADDRMAP5,DDRCTRL address map register 5" hexmask.long.byte 0x10 24.--27. 1. "ADDRMAP_ROW_B11,Selects the HIF address bit used as row address bit 11." hexmask.long.byte 0x10 16.--19. 1. "ADDRMAP_ROW_B2_10,Selects the HIF address bits used as row address bits 2 to 10." newline hexmask.long.byte 0x10 8.--11. 1. "ADDRMAP_ROW_B1,Selects the HIF address bits used as row address bit 1." hexmask.long.byte 0x10 0.--3. 1. "ADDRMAP_ROW_B0,Selects the HIF address bits used as row address bit 0." line.long 0x14 "DDRCTRL_ADDRMAP6,DDRCTRL address register 6" bitfld.long 0x14 31. "LPDDR3_6GB_12GB,Set this to 1 if there is an LPDDR3 SDRAM 6Gb or 12Gb device in use." "0,1" hexmask.long.byte 0x14 24.--27. 1. "ADDRMAP_ROW_B15,Selects the HIF address bit used as row address bit 15." newline hexmask.long.byte 0x14 16.--19. 1. "ADDRMAP_ROW_B14,Selects the HIF address bit used as row address bit 14." hexmask.long.byte 0x14 8.--11. 1. "ADDRMAP_ROW_B13,Selects the HIF address bit used as row address bit 13." newline hexmask.long.byte 0x14 0.--3. 1. "ADDRMAP_ROW_B12,Selects the HIF address bit used as row address bit 12." group.long 0x224++0xB line.long 0x0 "DDRCTRL_ADDRMAP9,DDRCTRL address map register 9" hexmask.long.byte 0x0 24.--27. 1. "ADDRMAP_ROW_B5,Selects the HIF address bits used as row address bit 5." hexmask.long.byte 0x0 16.--19. 1. "ADDRMAP_ROW_B4,Selects the HIF address bits used as row address bit 4." newline hexmask.long.byte 0x0 8.--11. 1. "ADDRMAP_ROW_B3,Selects the HIF address bits used as row address bit 3." hexmask.long.byte 0x0 0.--3. 1. "ADDRMAP_ROW_B2,Selects the HIF address bits used as row address bit 2." line.long 0x4 "DDRCTRL_ADDRMAP10,DDRCTRL address map register 10" hexmask.long.byte 0x4 24.--27. 1. "ADDRMAP_ROW_B9,Selects the HIF address bits used as row address bit 9." hexmask.long.byte 0x4 16.--19. 1. "ADDRMAP_ROW_B8,Selects the HIF address bits used as row address bit 8." newline hexmask.long.byte 0x4 8.--11. 1. "ADDRMAP_ROW_B7,Selects the HIF address bits used as row address bit 7." hexmask.long.byte 0x4 0.--3. 1. "ADDRMAP_ROW_B6,Selects the HIF address bits used as row address bit 6." line.long 0x8 "DDRCTRL_ADDRMAP11,DDRCTRL address map register 11" hexmask.long.byte 0x8 0.--3. 1. "ADDRMAP_ROW_B10,Selects the HIF address bits used as row address bit 10." group.long 0x240++0x7 line.long 0x0 "DDRCTRL_ODTCFG,DDRCTRL ODT configuration register" hexmask.long.byte 0x0 24.--27. 1. "WR_ODT_HOLD,DFI PHY clock cycles to hold ODT for a write command. The minimum supported value is 2." hexmask.long.byte 0x0 16.--20. 1. "WR_ODT_DELAY,The delay in DFI PHY clock cycles from issuing a write command to setting ODT values associated with that command. ODT setting must remain constant for the entire time that DQS is driven by the DDRCTRL." newline hexmask.long.byte 0x0 8.--11. 1. "RD_ODT_HOLD,DFI PHY clock cycles to hold ODT for a read command. The minimum supported value is 2." hexmask.long.byte 0x0 2.--6. 1. "RD_ODT_DELAY,The delay in DFI PHY clock cycles from issuing a read command to setting ODT values associated with that command. ODT setting must remain constant for the entire time that DQS is driven by the DDRCTRL." line.long 0x4 "DDRCTRL_ODTMAP,DDRCTRL ODT/Rank map register" bitfld.long 0x4 4. "RANK0_RD_ODT,Indicates which remote ODTs must be turned on during a read from rank 0." "0,1" bitfld.long 0x4 0. "RANK0_WR_ODT,Indicates which remote ODTs must be turned on during a write to rank 0." "0,1" group.long 0x250++0x7 line.long 0x0 "DDRCTRL_SCHED,DDRCTRL scheduler control register" hexmask.long.byte 0x0 24.--30. 1. "RDWR_IDLE_GAP,When the preferred transaction store is empty for these many clock cycles switch to the alternate transaction store if it is non-empty." hexmask.long.byte 0x0 16.--23. 1. "GO2CRITICAL_HYSTERESIS,UNUSED" newline hexmask.long.byte 0x0 8.--11. 1. "LPR_NUM_ENTRIES,Number of entries in the low priority transaction store is this value + 1." bitfld.long 0x0 2. "PAGECLOSE,If true bank is kept open only while there are page hit transactions available in the CAM to that bank. The last read or write command in the CAM with a bank and page hit is executed with auto-precharge if SCHED1.pageclose_timer=0. Even if.." "0,1" newline bitfld.long 0x0 1. "PREFER_WRITE,If set then the bank selector prefers writes over reads." "0,1" bitfld.long 0x0 0. "FORCE_LOW_PRI_N,Active low signal. When asserted ('0') all incoming transactions are forced to low priority. This implies that all high priority read (HPR) and variable priority read commands (VPR) are treated as low priority read (LPR) commands. On the.." "0,1" line.long 0x4 "DDRCTRL_SCHED1,DDRCTRL scheduler control register 1" hexmask.long.byte 0x4 0.--7. 1. "PAGECLOSE_TIMER,This field works in conjunction with SCHED.pageclose." group.long 0x25C++0x3 line.long 0x0 "DDRCTRL_PERFHPR1,DDRCTRL high priority read CAM register 1" hexmask.long.byte 0x0 24.--31. 1. "HPR_XACT_RUN_LENGTH,Number of transactions that are serviced once the HPR queue goes critical is the smaller of:" hexmask.long.word 0x0 0.--15. 1. "HPR_MAX_STARVE,Number of DFI clocks that the HPR queue can be starved before it goes critical. The minimum valid functional value for this register is 0x1. Programming it to 0x0 disables the starvation functionality; during normal operation this.." group.long 0x264++0x3 line.long 0x0 "DDRCTRL_PERFLPR1,DDRCTRL low priority read CAM register 1" hexmask.long.byte 0x0 24.--31. 1. "LPR_XACT_RUN_LENGTH,Number of transactions that are serviced once the LPR queue goes critical is the smaller of:" hexmask.long.word 0x0 0.--15. 1. "LPR_MAX_STARVE,Number of DFI clocks that the LPR queue can be starved before it goes critical. The minimum valid functional value for this register is 0x1. Programming it to 0x0 disables the starvation functionality; during normal operation this.." group.long 0x26C++0x3 line.long 0x0 "DDRCTRL_PERFWR1,DDRCTRL write CAM register 1" hexmask.long.byte 0x0 24.--31. 1. "W_XACT_RUN_LENGTH,Number of transactions that are serviced once the WR queue goes critical is the smaller of:" hexmask.long.word 0x0 0.--15. 1. "W_MAX_STARVE,Number of DFI clocks that the WR queue can be starved before it goes critical. The minimum valid functional value for this register is 0x1. Programming it to 0x0 disables the starvation functionality; during normal operation this function.." group.long 0x300++0x13 line.long 0x0 "DDRCTRL_DBG0,DDRCTRL debug register 0" bitfld.long 0x0 4. "DIS_COLLISION_PAGE_OPT,When this is set to '0' auto-precharge is disabled for the flushed command in a collision case. Collision cases are write followed by read to same address read followed by write to same address or write followed by write to same.." "0,1" bitfld.long 0x0 0. "DIS_WC,When 1 disable write combine." "0,1" line.long 0x4 "DDRCTRL_DBG1,DDRCTRL debug register 1" bitfld.long 0x4 1. "DIS_HIF,When 1 DDRCTRL asserts the HIF command signal hif_cmd_stall. DDRCTRL ignores the hif_cmd_valid and all other associated request signals." "0,1" bitfld.long 0x4 0. "DIS_DQ,When 1 DDRCTRL does not de-queue any transactions from the CAM. Bypass is also disabled. All transactions are queued in the CAM. No reads or writes are issued to SDRAM as long as this is asserted." "0,1" line.long 0x8 "DDRCTRL_DBGCAM,DDRCTRL CAM debug register" sif (cpuis("STM32MP13*")) rbitfld.long 0x8 29. "WR_DATA_PIPELINE_EMPTY,This bit indicates that the write data pipeline on the DFI interface is empty. This register is intended to be polled at least twice after setting DBG1.dis_dq to ensure that all remaining commands/data have completed." "0,1" rbitfld.long 0x8 28. "RD_DATA_PIPELINE_EMPTY,This bit indicates that the read data pipeline on the DFI interface is empty. This register is intended to be polled at least twice after setting DBG1.dis_dq to ensure that all remaining commands/data have completed." "0,1" newline rbitfld.long 0x8 26. "DBG_WR_Q_EMPTY,When 1 all the Write command queues and Write data buffers inside DDRC are empty. This register is to be used for debug purpose." "0,1" rbitfld.long 0x8 25. "DBG_RD_Q_EMPTY,When 1 all the Read command queues and Read data buffers inside DDRC are empty. This register is to be used for debug purpose." "0,1" newline rbitfld.long 0x8 24. "DBG_STALL,Stall" "0,1" hexmask.long.byte 0x8 16.--20. 1. "DBG_W_Q_DEPTH,Write queue depth" newline hexmask.long.byte 0x8 8.--12. 1. "DBG_LPR_Q_DEPTH,Low priority read queue depth" hexmask.long.byte 0x8 0.--4. 1. "DBG_HPR_Q_DEPTH,High priority read queue depth" newline endif sif (cpuis("STM32MP151*")) bitfld.long 0x8 29. "WR_DATA_PIPELINE_EMPTY,WR_DATA_PIPELINE_EMPTY" "0,1" bitfld.long 0x8 28. "RD_DATA_PIPELINE_EMPTY,RD_DATA_PIPELINE_EMPTY" "0,1" newline endif sif (cpuis("STM32MP153*")) bitfld.long 0x8 29. "WR_DATA_PIPELINE_EMPTY,WR_DATA_PIPELINE_EMPTY" "0,1" bitfld.long 0x8 28. "RD_DATA_PIPELINE_EMPTY,RD_DATA_PIPELINE_EMPTY" "0,1" newline endif sif (cpuis("STM32MP157*")) bitfld.long 0x8 29. "WR_DATA_PIPELINE_EMPTY,WR_DATA_PIPELINE_EMPTY" "0,1" bitfld.long 0x8 28. "RD_DATA_PIPELINE_EMPTY,RD_DATA_PIPELINE_EMPTY" "0,1" newline endif sif (cpuis("STM32MP151*")) bitfld.long 0x8 26. "DBG_WR_Q_EMPTY,DBG_WR_Q_EMPTY" "0,1" bitfld.long 0x8 25. "DBG_RD_Q_EMPTY,DBG_RD_Q_EMPTY" "0,1" newline bitfld.long 0x8 24. "DBG_STALL,DBG_STALL" "0,1" endif sif (cpuis("STM32MP153*")) bitfld.long 0x8 26. "DBG_WR_Q_EMPTY,DBG_WR_Q_EMPTY" "0,1" newline bitfld.long 0x8 25. "DBG_RD_Q_EMPTY,DBG_RD_Q_EMPTY" "0,1" bitfld.long 0x8 24. "DBG_STALL,DBG_STALL" "0,1" newline endif sif (cpuis("STM32MP157*")) bitfld.long 0x8 26. "DBG_WR_Q_EMPTY,DBG_WR_Q_EMPTY" "0,1" bitfld.long 0x8 25. "DBG_RD_Q_EMPTY,DBG_RD_Q_EMPTY" "0,1" newline bitfld.long 0x8 24. "DBG_STALL,DBG_STALL" "0,1" endif sif (cpuis("STM32MP151*")) hexmask.long.byte 0x8 16.--20. 1. "DBG_W_Q_DEPTH,DBG_W_Q_DEPTH" newline endif sif (cpuis("STM32MP153*")) hexmask.long.byte 0x8 16.--20. 1. "DBG_W_Q_DEPTH,DBG_W_Q_DEPTH" endif sif (cpuis("STM32MP157*")) hexmask.long.byte 0x8 16.--20. 1. "DBG_W_Q_DEPTH,DBG_W_Q_DEPTH" newline endif sif (cpuis("STM32MP151*")) hexmask.long.byte 0x8 8.--12. 1. "DBG_LPR_Q_DEPTH,DBG_LPR_Q_DEPTH" endif sif (cpuis("STM32MP153*")) hexmask.long.byte 0x8 8.--12. 1. "DBG_LPR_Q_DEPTH,DBG_LPR_Q_DEPTH" newline endif sif (cpuis("STM32MP157*")) hexmask.long.byte 0x8 8.--12. 1. "DBG_LPR_Q_DEPTH,DBG_LPR_Q_DEPTH" endif sif (cpuis("STM32MP151*")) hexmask.long.byte 0x8 0.--4. 1. "DBG_HPR_Q_DEPTH,DBG_HPR_Q_DEPTH" newline endif sif (cpuis("STM32MP153*")) hexmask.long.byte 0x8 0.--4. 1. "DBG_HPR_Q_DEPTH,DBG_HPR_Q_DEPTH" endif sif (cpuis("STM32MP157*")) hexmask.long.byte 0x8 0.--4. 1. "DBG_HPR_Q_DEPTH,DBG_HPR_Q_DEPTH" endif line.long 0xC "DDRCTRL_DBGCMD,DDRCTRL command debug register" bitfld.long 0xC 5. "CTRLUPD,Setting this register bit to 1 indicates to the DDRCTRL to issue a dfi_ctrlupd_req to the PHY. When this request is stored in the DDRCTRL the bit is automatically cleared. This operation must only be performed when DFIUPD0.dis_auto_ctrlupd=1." "0,1" bitfld.long 0xC 4. "ZQ_CALIB_SHORT,Setting this register bit to 1 indicates to the DDRCTRL to issue a ZQCS (ZQ calibration short)/MPC(ZQ calibration) command to the SDRAM. When this request is stored in the DDRCTRL the bit is automatically cleared. This operation can be.." "0,1" newline bitfld.long 0xC 0. "RANK0_REFRESH,Setting this register bit to 1 indicates to the DDRCTRL to issue a refresh to rank 0. Writing to this bit causes DBGSTAT.rank0_refresh_busy to be set. When DBGSTAT.rank0_refresh_busy is cleared the command has been stored in DDRCTRL." "0,1" line.long 0x10 "DDRCTRL_DBGSTAT,DDRCTRL status debug register" sif (cpuis("STM32MP13*")) rbitfld.long 0x10 5. "CTRLUPD_BUSY,SoC core may initiate a ctrlupd operation only if this signal is low. This signal goes high in the clock after the DDRCTRL accepts the ctrlupd request. It goes low when the ctrlupd operation is initiated in the DDRCTRL. It is recommended not.." "0,1" rbitfld.long 0x10 4. "ZQ_CALIB_SHORT_BUSY,SoC core may initiate a ZQCS (ZQ calibration short) operation only if this signal is low. This signal goes high in the clock after the DDRCTRL accepts the ZQCS request. It goes low when the ZQCS operation is initiated in the DDRCTRL." "0,1" newline rbitfld.long 0x10 0. "RANK0_REFRESH_BUSY,SoC core may initiate a rank0_refresh operation (refresh operation to rank 0) only if this signal is low. This signal goes high in the clock after DBGCMD.rank0_refresh is set to one. It goes low when the rank0_refresh operation is.." "0,1" endif sif (cpuis("STM32MP151*")) bitfld.long 0x10 5. "CTRLUPD_BUSY,CTRLUPD_BUSY" "0,1" newline bitfld.long 0x10 4. "ZQ_CALIB_SHORT_BUSY,ZQ_CALIB_SHORT_BUSY" "0,1" endif sif (cpuis("STM32MP153*")) bitfld.long 0x10 5. "CTRLUPD_BUSY,CTRLUPD_BUSY" "0,1" newline bitfld.long 0x10 4. "ZQ_CALIB_SHORT_BUSY,ZQ_CALIB_SHORT_BUSY" "0,1" endif sif (cpuis("STM32MP157*")) bitfld.long 0x10 5. "CTRLUPD_BUSY,CTRLUPD_BUSY" "0,1" newline bitfld.long 0x10 4. "ZQ_CALIB_SHORT_BUSY,ZQ_CALIB_SHORT_BUSY" "0,1" endif sif (cpuis("STM32MP151*")) bitfld.long 0x10 0. "RANK0_REFRESH_BUSY,RANK0_REFRESH_BUSY" "0,1" newline endif sif (cpuis("STM32MP153*")) bitfld.long 0x10 0. "RANK0_REFRESH_BUSY,RANK0_REFRESH_BUSY" "0,1" endif sif (cpuis("STM32MP157*")) bitfld.long 0x10 0. "RANK0_REFRESH_BUSY,RANK0_REFRESH_BUSY" "0,1" endif group.long 0x320++0x7 line.long 0x0 "DDRCTRL_SWCTL,DDRCTRL software register programming control enable" bitfld.long 0x0 0. "SW_DONE,Enable quasi-dynamic register programming outside reset. Program register to 0 to enable quasi-dynamic programming. Set back register to 1 once programming is done." "0,1" line.long 0x4 "DDRCTRL_SWSTAT,DDRCTRL software register programming control status" sif (cpuis("STM32MP13*")) rbitfld.long 0x4 0. "SW_DONE_ACK,Register programming done. This register is the echo of SWCTL.sw_done. Wait for sw_done value 1 to propagate to sw_done_ack at the end of the programming sequence to ensure that the correct registers values are propagated to the destination.." "0,1" endif sif (cpuis("STM32MP151*")) bitfld.long 0x4 0. "SW_DONE_ACK,SW_DONE_ACK" "0,1" newline endif sif (cpuis("STM32MP153*")) bitfld.long 0x4 0. "SW_DONE_ACK,SW_DONE_ACK" "0,1" endif sif (cpuis("STM32MP157*")) bitfld.long 0x4 0. "SW_DONE_ACK,SW_DONE_ACK" "0,1" endif group.long 0x36C++0x7 line.long 0x0 "DDRCTRL_POISONCFG,DDRCTRL AXI Poison configuration register" bitfld.long 0x0 24. "RD_POISON_INTR_CLR,Interrupt clear for read transaction poisoning. Allow 2/3 clock cycles for correct value to propagate to core logic and clear the interrupts." "0,1" bitfld.long 0x0 20. "RD_POISON_INTR_EN,If set to 1 enables interrupts for read transaction poisoning" "0,1" newline bitfld.long 0x0 16. "RD_POISON_SLVERR_EN,If set to 1 enables SLVERR response for read transaction poisoning" "0,1" bitfld.long 0x0 8. "WR_POISON_INTR_CLR,Interrupt clear for write transaction poisoning. Allow 2/3 clock cycles for correct value to propagate to core logic and clear the interrupts." "0,1" newline bitfld.long 0x0 4. "WR_POISON_INTR_EN,If set to 1 enables interrupts for write transaction poisoning" "0,1" bitfld.long 0x0 0. "WR_POISON_SLVERR_EN,If set to 1 enables SLVERR response for write transaction poisoning" "0,1" line.long 0x4 "DDRCTRL_POISONSTAT,DDRCTRL AXI Poison status register" sif (cpuis("STM32MP151*")) bitfld.long 0x4 17. "RD_POISON_INTR_1,RD_POISON_INTR_1" "0,1" bitfld.long 0x4 16. "RD_POISON_INTR_0,RD_POISON_INTR_0" "0,1" newline endif sif (cpuis("STM32MP153*")) bitfld.long 0x4 17. "RD_POISON_INTR_1,RD_POISON_INTR_1" "0,1" bitfld.long 0x4 16. "RD_POISON_INTR_0,RD_POISON_INTR_0" "0,1" newline endif sif (cpuis("STM32MP157*")) bitfld.long 0x4 17. "RD_POISON_INTR_1,RD_POISON_INTR_1" "0,1" bitfld.long 0x4 16. "RD_POISON_INTR_0,RD_POISON_INTR_0" "0,1" newline endif sif (cpuis("STM32MP13*")) rbitfld.long 0x4 16. "RD_POISON_INTR_0,Read transaction poisoning error interrupt for port 0. This register is a APB clock copy (double register synchronizer) of the interrupt asserted when a transaction is poisoned on the corresponding AXI port's read address channel. Bit 0.." "0,1" rbitfld.long 0x4 0. "WR_POISON_INTR_0,Write transaction poisoning error interrupt for port 0. This register is a APB clock copy (double register synchronizer) of the interrupt asserted when a transaction is poisoned on the corresponding AXI port's write address channel. Bit.." "0,1" newline endif sif (cpuis("STM32MP151*")) bitfld.long 0x4 1. "WR_POISON_INTR_1,WR_POISON_INTR_1" "0,1" bitfld.long 0x4 0. "WR_POISON_INTR_0,WR_POISON_INTR_0" "0,1" newline endif sif (cpuis("STM32MP153*")) bitfld.long 0x4 1. "WR_POISON_INTR_1,WR_POISON_INTR_1" "0,1" bitfld.long 0x4 0. "WR_POISON_INTR_0,WR_POISON_INTR_0" "0,1" newline endif sif (cpuis("STM32MP157*")) bitfld.long 0x4 1. "WR_POISON_INTR_1,WR_POISON_INTR_1" "0,1" bitfld.long 0x4 0. "WR_POISON_INTR_0,WR_POISON_INTR_0" "0,1" endif group.long 0x3FC++0xF line.long 0x0 "DDRCTRL_PSTAT,DDRCTRL port status register" sif (cpuis("STM32MP151*")) bitfld.long 0x0 17. "WR_PORT_BUSY_1,WR_PORT_BUSY_1" "0,1" bitfld.long 0x0 16. "WR_PORT_BUSY_0,WR_PORT_BUSY_0" "0,1" newline endif sif (cpuis("STM32MP153*")) bitfld.long 0x0 17. "WR_PORT_BUSY_1,WR_PORT_BUSY_1" "0,1" bitfld.long 0x0 16. "WR_PORT_BUSY_0,WR_PORT_BUSY_0" "0,1" newline endif sif (cpuis("STM32MP157*")) bitfld.long 0x0 17. "WR_PORT_BUSY_1,WR_PORT_BUSY_1" "0,1" bitfld.long 0x0 16. "WR_PORT_BUSY_0,WR_PORT_BUSY_0" "0,1" newline endif sif (cpuis("STM32MP13*")) rbitfld.long 0x0 16. "WR_PORT_BUSY_0,Indicates if there are outstanding writes for AXI port 0." "0,1" rbitfld.long 0x0 0. "RD_PORT_BUSY_0,Indicates if there are outstanding reads for AXI port 0." "0,1" newline endif sif (cpuis("STM32MP151*")) bitfld.long 0x0 1. "RD_PORT_BUSY_1,RD_PORT_BUSY_1" "0,1" bitfld.long 0x0 0. "RD_PORT_BUSY_0,RD_PORT_BUSY_0" "0,1" newline endif sif (cpuis("STM32MP153*")) bitfld.long 0x0 1. "RD_PORT_BUSY_1,RD_PORT_BUSY_1" "0,1" bitfld.long 0x0 0. "RD_PORT_BUSY_0,RD_PORT_BUSY_0" "0,1" newline endif sif (cpuis("STM32MP157*")) bitfld.long 0x0 1. "RD_PORT_BUSY_1,RD_PORT_BUSY_1" "0,1" bitfld.long 0x0 0. "RD_PORT_BUSY_0,RD_PORT_BUSY_0" "0,1" endif line.long 0x4 "DDRCTRL_PCCFG,DDRCTRL port common configuration register" bitfld.long 0x4 8. "BL_EXP_MODE,Burst length expansion mode. By default (i.e. bl_exp_mode==0) XPI expands every AXI burst into multiple HIF commands using the memory burst length as a unit. If set to 1 then XPI uses half of the memory burst length as a unit." "0,1" bitfld.long 0x4 4. "PAGEMATCH_LIMIT,Page match four limit. If set to 1 limits the number of consecutive same page DDRC transactions that can be granted by the Port Arbiter to four when Page Match feature is enabled. If set to 0 there is no limit imposed on number of.." "0,1" newline bitfld.long 0x4 0. "GO2CRITICAL_EN,If set to 1 (enabled) sets co_gs_go2critical_wr and co_gs_go2critical_lpr/co_gs_go2critical_hpr signals going to DDRC based on urgent input (awurgent arurgent) coming from AXI master. If set to 0 (disabled) co_gs_go2critical_wr and.." "0,1" line.long 0x8 "DDRCTRL_PCFGR_0,DDRCTRL port x configuration read register" bitfld.long 0x8 16. "RDWR_ORDERED_EN,Enables ordered read/writes. If set to 1 preserves the ordering between read transaction and write transaction issued to the same address on a given port. In other words the controller ensures that all same address read and write.." "0,1" bitfld.long 0x8 14. "RD_PORT_PAGEMATCH_EN,If set to 1 enables the Page Match feature. If enabled once a requesting port is granted the port is continued to be granted if the following immediate commands are to the same memory page (same bank and same row). See also.." "0,1" newline bitfld.long 0x8 13. "RD_PORT_URGENT_EN,If set to 1 enables the AXI urgent sideband signal (arurgent). When enabled and arurgent is asserted by the master that port becomes the highest priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DDRC is asserted if.." "0,1" bitfld.long 0x8 12. "RD_PORT_AGING_EN,If set to 1 enables aging function for the read channel of the port." "0,1" newline hexmask.long.word 0x8 0.--9. 1. "RD_PORT_PRIORITY,Determines the initial load value of read aging counters. These counters are parallel loaded after reset or after each grant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but.." line.long 0xC "DDRCTRL_PCFGW_0,DDRCTRL port x configuration write register" bitfld.long 0xC 14. "WR_PORT_PAGEMATCH_EN,If set to 1 enables the Page Match feature. If enabled once a requesting port is granted the port is continued to be granted if the following immediate commands are to the same memory page (same bank and same row). See also.." "0,1" bitfld.long 0xC 13. "WR_PORT_URGENT_EN,If set to 1 enables the AXI urgent sideband signal (awurgent). When enabled and awurgent is asserted by the master that port becomes the highest priority and co_gs_go2critical_wr signal to DDRC is asserted if enabled in.." "0,1" newline bitfld.long 0xC 12. "WR_PORT_AGING_EN,If set to 1 enables aging function for the write channel of the port." "0,1" hexmask.long.word 0xC 0.--9. 1. "WR_PORT_PRIORITY,Determines the initial load value of write aging counters. These counters are parallel loaded after reset or after each grant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but.." group.long 0x490++0x13 line.long 0x0 "DDRCTRL_PCTRL_0,DDRCTRL port x control register" bitfld.long 0x0 0. "PORT_EN,Enables AXI port n." "0,1" line.long 0x4 "DDRCTRL_PCFGQOS0_0,DDRCTRL port x read Q0S configuration register 0" sif (cpuis("STM32MP151*")) bitfld.long 0x4 24.--25. "RQOS_MAP_REGION2,RQOS_MAP_REGION2" "0,1,2,3" endif sif (cpuis("STM32MP153*")) bitfld.long 0x4 24.--25. "RQOS_MAP_REGION2,RQOS_MAP_REGION2" "0,1,2,3" newline endif sif (cpuis("STM32MP157*")) bitfld.long 0x4 24.--25. "RQOS_MAP_REGION2,RQOS_MAP_REGION2" "0,1,2,3" endif bitfld.long 0x4 20.--21. "RQOS_MAP_REGION1,This bitfield indicates the traffic class of region 1." "?,?,2: HPR,?" newline bitfld.long 0x4 16.--17. "RQOS_MAP_REGION0,This bitfield indicates the traffic class of region 0." "?,1: VPR only,2: HPR,?" sif (cpuis("STM32MP151*")) hexmask.long.byte 0x4 8.--11. 1. "RQOS_MAP_LEVEL2,RQOS_MAP_LEVEL2" newline endif sif (cpuis("STM32MP153*")) hexmask.long.byte 0x4 8.--11. 1. "RQOS_MAP_LEVEL2,RQOS_MAP_LEVEL2" endif sif (cpuis("STM32MP157*")) hexmask.long.byte 0x4 8.--11. 1. "RQOS_MAP_LEVEL2,RQOS_MAP_LEVEL2" newline endif hexmask.long.byte 0x4 0.--3. 1. "RQOS_MAP_LEVEL1,Separation level1 indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 13 (for dual RAQ) or 0 to 14 (for single RAQ) which corresponds to arqos." line.long 0x8 "DDRCTRL_PCFGQOS1_0,DDRCTRL port x read Q0S configuration register 1" hexmask.long.word 0x8 16.--26. 1. "RQOS_MAP_TIMEOUTR,Specifies the timeout value for transactions mapped to the red address queue. With single read address queue there is no red queue and this value has no effect." hexmask.long.word 0x8 0.--10. 1. "RQOS_MAP_TIMEOUTB,Specifies the timeout value for transactions mapped to the blue address queue." line.long 0xC "DDRCTRL_PCFGWQOS0_0,DDRCTRL port x write Q0S configuration register 0" sif (cpuis("STM32MP13*")) bitfld.long 0xC 24.--25. "WQOS_MAP_REGION2,This bitfield indicates the traffic class of region 2." "0: NPW 1: VPW.,?,?,?" bitfld.long 0xC 20.--21. "WQOS_MAP_REGION1,This bitfield indicates the traffic class of region 1." "0: NPW 1: VPW.,?,?,?" newline bitfld.long 0xC 16.--17. "WQOS_MAP_REGION0,This bitfield indicates the traffic class of region 0." "0: NPW 1: VPW.,?,?,?" endif sif (cpuis("STM32MP151*")) bitfld.long 0xC 24.--25. "WQOS_MAP_REGION2,WQOS_MAP_REGION2" "0,1,2,3" newline endif sif (cpuis("STM32MP153*")) bitfld.long 0xC 24.--25. "WQOS_MAP_REGION2,WQOS_MAP_REGION2" "0,1,2,3" endif sif (cpuis("STM32MP157*")) bitfld.long 0xC 24.--25. "WQOS_MAP_REGION2,WQOS_MAP_REGION2" "0,1,2,3" newline endif sif (cpuis("STM32MP151*")) bitfld.long 0xC 20.--21. "WQOS_MAP_REGION1,WQOS_MAP_REGION1" "0,1,2,3" endif sif (cpuis("STM32MP153*")) bitfld.long 0xC 20.--21. "WQOS_MAP_REGION1,WQOS_MAP_REGION1" "0,1,2,3" newline endif sif (cpuis("STM32MP157*")) bitfld.long 0xC 20.--21. "WQOS_MAP_REGION1,WQOS_MAP_REGION1" "0,1,2,3" endif sif (cpuis("STM32MP151*")) bitfld.long 0xC 16.--17. "WQOS_MAP_REGION0,WQOS_MAP_REGION0" "0,1,2,3" newline endif sif (cpuis("STM32MP153*")) bitfld.long 0xC 16.--17. "WQOS_MAP_REGION0,WQOS_MAP_REGION0" "0,1,2,3" endif sif (cpuis("STM32MP157*")) bitfld.long 0xC 16.--17. "WQOS_MAP_REGION0,WQOS_MAP_REGION0" "0,1,2,3" newline endif hexmask.long.byte 0xC 8.--11. 1. "WQOS_MAP_LEVEL2,Separation level2 indicating the end of region1 mapping; start of region1 is (level1 + 1). Possible values for level2 are (level1 + 1) to 14 which corresponds to awqos." hexmask.long.byte 0xC 0.--3. 1. "WQOS_MAP_LEVEL1,Separation level indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 13 which corresponds to awqos." line.long 0x10 "DDRCTRL_PCFGWQOS1_0,DDRCTRL port x write Q0S configuration register 1" hexmask.long.word 0x10 16.--26. 1. "WQOS_MAP_TIMEOUT2,Specifies the timeout value for write transactions in region 2." hexmask.long.word 0x10 0.--10. 1. "WQOS_MAP_TIMEOUT1,Specifies the timeout value for write transactions in region 0 and 1." sif (cpuis("STM32MP151*")) rgroup.long 0x4++0x3 line.long 0x0 "DDRCTRL_STAT,DDRCTRL operating mode status register" endif sif (cpuis("STM32MP151*")) rgroup.long 0x18++0x3 line.long 0x0 "DDRCTRL_MRSTAT,DDRCTRL mode register read/write status register" endif sif (cpuis("STM32MP151*")) rgroup.long 0xCC++0x3 line.long 0x0 "DDRCTRL_CRCPARSTAT,DDRCTRL CRC parity status register" endif sif (cpuis("STM32MP151*")) rgroup.long 0x18C++0x3 line.long 0x0 "DDRCTRL_ZQSTAT,DDRCTRL ZQ status register" endif sif (cpuis("STM32MP151*")) rgroup.long 0x1BC++0x3 line.long 0x0 "DDRCTRL_DFISTAT,DDRCTRL DFI status register" endif sif (cpuis("STM32MP151*")) rgroup.long 0x308++0x3 line.long 0x0 "DDRCTRL_DBGCAM,DDRCTRL CAM debug register" endif sif (cpuis("STM32MP151*")) rgroup.long 0x310++0x3 line.long 0x0 "DDRCTRL_DBGSTAT,DDRCTRL status debug register" endif sif (cpuis("STM32MP151*")) rgroup.long 0x324++0x3 line.long 0x0 "DDRCTRL_SWSTAT,DDRCTRL software register programming control status" endif sif (cpuis("STM32MP151*")) rgroup.long 0x370++0x3 line.long 0x0 "DDRCTRL_POISONSTAT,DDRCTRL AXI Poison status register" endif sif (cpuis("STM32MP151*")) rgroup.long 0x3FC++0x3 line.long 0x0 "DDRCTRL_PSTAT,DDRCTRL port status register" group.long 0x4B4++0x7 line.long 0x0 "DDRCTRL_PCFGR_1,DDRCTRL port 1 configuration read register" bitfld.long 0x0 16. "RDWR_ORDERED_EN,RDWR_ORDERED_EN" "0,1" bitfld.long 0x0 14. "RD_PORT_PAGEMATCH_EN,RD_PORT_PAGEMATCH_EN" "0,1" newline bitfld.long 0x0 13. "RD_PORT_URGENT_EN,RD_PORT_URGENT_EN" "0,1" bitfld.long 0x0 12. "RD_PORT_AGING_EN,RD_PORT_AGING_EN" "0,1" newline hexmask.long.word 0x0 0.--9. 1. "RD_PORT_PRIORITY,RD_PORT_PRIORITY" line.long 0x4 "DDRCTRL_PCFGW_1,DDRCTRL port 1 configuration write register" bitfld.long 0x4 14. "WR_PORT_PAGEMATCH_EN,WR_PORT_PAGEMATCH_EN" "0,1" bitfld.long 0x4 13. "WR_PORT_URGENT_EN,WR_PORT_URGENT_EN" "0,1" newline bitfld.long 0x4 12. "WR_PORT_AGING_EN,WR_PORT_AGING_EN" "0,1" hexmask.long.word 0x4 0.--9. 1. "WR_PORT_PRIORITY,WR_PORT_PRIORITY" group.long 0x540++0x13 line.long 0x0 "DDRCTRL_PCTRL_1,DDRCTRL port 1 control register" bitfld.long 0x0 0. "PORT_EN,PORT_EN" "0,1" line.long 0x4 "DDRCTRL_PCFGQOS0_1,DDRCTRL port 1 read Q0S configuration register 0" bitfld.long 0x4 24.--25. "RQOS_MAP_REGION2,RQOS_MAP_REGION2" "0,1,2,3" bitfld.long 0x4 20.--21. "RQOS_MAP_REGION1,RQOS_MAP_REGION1" "0,1,2,3" newline bitfld.long 0x4 16.--17. "RQOS_MAP_REGION0,RQOS_MAP_REGION0" "0,1,2,3" hexmask.long.byte 0x4 8.--11. 1. "RQOS_MAP_LEVEL2,RQOS_MAP_LEVEL2" newline hexmask.long.byte 0x4 0.--3. 1. "RQOS_MAP_LEVEL1,RQOS_MAP_LEVEL1" line.long 0x8 "DDRCTRL_PCFGQOS1_1,DDRCTRL port 1 read Q0S configuration register 1" hexmask.long.word 0x8 16.--26. 1. "RQOS_MAP_TIMEOUTR,RQOS_MAP_TIMEOUTR" hexmask.long.word 0x8 0.--10. 1. "RQOS_MAP_TIMEOUTB,RQOS_MAP_TIMEOUTB" line.long 0xC "DDRCTRL_PCFGWQOS0_1,DDRCTRL port 1 write Q0S configuration register 0" bitfld.long 0xC 24.--25. "WQOS_MAP_REGION2,WQOS_MAP_REGION2" "0,1,2,3" bitfld.long 0xC 20.--21. "WQOS_MAP_REGION1,WQOS_MAP_REGION1" "0,1,2,3" newline bitfld.long 0xC 16.--17. "WQOS_MAP_REGION0,WQOS_MAP_REGION0" "0,1,2,3" hexmask.long.byte 0xC 8.--11. 1. "WQOS_MAP_LEVEL2,WQOS_MAP_LEVEL2" newline hexmask.long.byte 0xC 0.--3. 1. "WQOS_MAP_LEVEL1,WQOS_MAP_LEVEL1" line.long 0x10 "DDRCTRL_PCFGWQOS1_1,DDRCTRL port 1 write Q0S configuration register 1" hexmask.long.word 0x10 16.--26. 1. "WQOS_MAP_TIMEOUT2,WQOS_MAP_TIMEOUT2" hexmask.long.word 0x10 0.--10. 1. "WQOS_MAP_TIMEOUT1,WQOS_MAP_TIMEOUT1" endif sif (cpuis("STM32MP153*")) rgroup.long 0x4++0x3 line.long 0x0 "DDRCTRL_STAT,DDRCTRL operating mode status register" endif sif (cpuis("STM32MP153*")) rgroup.long 0x18++0x3 line.long 0x0 "DDRCTRL_MRSTAT,DDRCTRL mode register read/write status register" endif sif (cpuis("STM32MP153*")) rgroup.long 0xCC++0x3 line.long 0x0 "DDRCTRL_CRCPARSTAT,DDRCTRL CRC parity status register" endif sif (cpuis("STM32MP153*")) rgroup.long 0x18C++0x3 line.long 0x0 "DDRCTRL_ZQSTAT,DDRCTRL ZQ status register" endif sif (cpuis("STM32MP153*")) rgroup.long 0x1BC++0x3 line.long 0x0 "DDRCTRL_DFISTAT,DDRCTRL DFI status register" endif sif (cpuis("STM32MP153*")) rgroup.long 0x308++0x3 line.long 0x0 "DDRCTRL_DBGCAM,DDRCTRL CAM debug register" endif sif (cpuis("STM32MP153*")) rgroup.long 0x310++0x3 line.long 0x0 "DDRCTRL_DBGSTAT,DDRCTRL status debug register" endif sif (cpuis("STM32MP153*")) rgroup.long 0x324++0x3 line.long 0x0 "DDRCTRL_SWSTAT,DDRCTRL software register programming control status" endif sif (cpuis("STM32MP153*")) rgroup.long 0x370++0x3 line.long 0x0 "DDRCTRL_POISONSTAT,DDRCTRL AXI Poison status register" endif sif (cpuis("STM32MP153*")) rgroup.long 0x3FC++0x3 line.long 0x0 "DDRCTRL_PSTAT,DDRCTRL port status register" group.long 0x4B4++0x7 line.long 0x0 "DDRCTRL_PCFGR_1,DDRCTRL port 1 configuration read register" bitfld.long 0x0 16. "RDWR_ORDERED_EN,RDWR_ORDERED_EN" "0,1" bitfld.long 0x0 14. "RD_PORT_PAGEMATCH_EN,RD_PORT_PAGEMATCH_EN" "0,1" newline bitfld.long 0x0 13. "RD_PORT_URGENT_EN,RD_PORT_URGENT_EN" "0,1" bitfld.long 0x0 12. "RD_PORT_AGING_EN,RD_PORT_AGING_EN" "0,1" newline hexmask.long.word 0x0 0.--9. 1. "RD_PORT_PRIORITY,RD_PORT_PRIORITY" line.long 0x4 "DDRCTRL_PCFGW_1,DDRCTRL port 1 configuration write register" bitfld.long 0x4 14. "WR_PORT_PAGEMATCH_EN,WR_PORT_PAGEMATCH_EN" "0,1" bitfld.long 0x4 13. "WR_PORT_URGENT_EN,WR_PORT_URGENT_EN" "0,1" newline bitfld.long 0x4 12. "WR_PORT_AGING_EN,WR_PORT_AGING_EN" "0,1" hexmask.long.word 0x4 0.--9. 1. "WR_PORT_PRIORITY,WR_PORT_PRIORITY" group.long 0x540++0x13 line.long 0x0 "DDRCTRL_PCTRL_1,DDRCTRL port 1 control register" bitfld.long 0x0 0. "PORT_EN,PORT_EN" "0,1" line.long 0x4 "DDRCTRL_PCFGQOS0_1,DDRCTRL port 1 read Q0S configuration register 0" bitfld.long 0x4 24.--25. "RQOS_MAP_REGION2,RQOS_MAP_REGION2" "0,1,2,3" bitfld.long 0x4 20.--21. "RQOS_MAP_REGION1,RQOS_MAP_REGION1" "0,1,2,3" newline bitfld.long 0x4 16.--17. "RQOS_MAP_REGION0,RQOS_MAP_REGION0" "0,1,2,3" hexmask.long.byte 0x4 8.--11. 1. "RQOS_MAP_LEVEL2,RQOS_MAP_LEVEL2" newline hexmask.long.byte 0x4 0.--3. 1. "RQOS_MAP_LEVEL1,RQOS_MAP_LEVEL1" line.long 0x8 "DDRCTRL_PCFGQOS1_1,DDRCTRL port 1 read Q0S configuration register 1" hexmask.long.word 0x8 16.--26. 1. "RQOS_MAP_TIMEOUTR,RQOS_MAP_TIMEOUTR" hexmask.long.word 0x8 0.--10. 1. "RQOS_MAP_TIMEOUTB,RQOS_MAP_TIMEOUTB" line.long 0xC "DDRCTRL_PCFGWQOS0_1,DDRCTRL port 1 write Q0S configuration register 0" bitfld.long 0xC 24.--25. "WQOS_MAP_REGION2,WQOS_MAP_REGION2" "0,1,2,3" bitfld.long 0xC 20.--21. "WQOS_MAP_REGION1,WQOS_MAP_REGION1" "0,1,2,3" newline bitfld.long 0xC 16.--17. "WQOS_MAP_REGION0,WQOS_MAP_REGION0" "0,1,2,3" hexmask.long.byte 0xC 8.--11. 1. "WQOS_MAP_LEVEL2,WQOS_MAP_LEVEL2" newline hexmask.long.byte 0xC 0.--3. 1. "WQOS_MAP_LEVEL1,WQOS_MAP_LEVEL1" line.long 0x10 "DDRCTRL_PCFGWQOS1_1,DDRCTRL port 1 write Q0S configuration register 1" hexmask.long.word 0x10 16.--26. 1. "WQOS_MAP_TIMEOUT2,WQOS_MAP_TIMEOUT2" hexmask.long.word 0x10 0.--10. 1. "WQOS_MAP_TIMEOUT1,WQOS_MAP_TIMEOUT1" endif sif (cpuis("STM32MP157*")) rgroup.long 0x4++0x3 line.long 0x0 "DDRCTRL_STAT,DDRCTRL operating mode status register" endif sif (cpuis("STM32MP157*")) rgroup.long 0x18++0x3 line.long 0x0 "DDRCTRL_MRSTAT,DDRCTRL mode register read/write status register" endif sif (cpuis("STM32MP157*")) rgroup.long 0xCC++0x3 line.long 0x0 "DDRCTRL_CRCPARSTAT,DDRCTRL CRC parity status register" endif sif (cpuis("STM32MP157*")) rgroup.long 0x18C++0x3 line.long 0x0 "DDRCTRL_ZQSTAT,DDRCTRL ZQ status register" endif sif (cpuis("STM32MP157*")) rgroup.long 0x1BC++0x3 line.long 0x0 "DDRCTRL_DFISTAT,DDRCTRL DFI status register" endif sif (cpuis("STM32MP157*")) rgroup.long 0x308++0x3 line.long 0x0 "DDRCTRL_DBGCAM,DDRCTRL CAM debug register" endif sif (cpuis("STM32MP157*")) rgroup.long 0x310++0x3 line.long 0x0 "DDRCTRL_DBGSTAT,DDRCTRL status debug register" endif sif (cpuis("STM32MP157*")) rgroup.long 0x324++0x3 line.long 0x0 "DDRCTRL_SWSTAT,DDRCTRL software register programming control status" endif sif (cpuis("STM32MP157*")) rgroup.long 0x370++0x3 line.long 0x0 "DDRCTRL_POISONSTAT,DDRCTRL AXI Poison status register" endif sif (cpuis("STM32MP157*")) rgroup.long 0x3FC++0x3 line.long 0x0 "DDRCTRL_PSTAT,DDRCTRL port status register" group.long 0x4B4++0x7 line.long 0x0 "DDRCTRL_PCFGR_1,DDRCTRL port 1 configuration read register" bitfld.long 0x0 16. "RDWR_ORDERED_EN,RDWR_ORDERED_EN" "0,1" bitfld.long 0x0 14. "RD_PORT_PAGEMATCH_EN,RD_PORT_PAGEMATCH_EN" "0,1" newline bitfld.long 0x0 13. "RD_PORT_URGENT_EN,RD_PORT_URGENT_EN" "0,1" bitfld.long 0x0 12. "RD_PORT_AGING_EN,RD_PORT_AGING_EN" "0,1" newline hexmask.long.word 0x0 0.--9. 1. "RD_PORT_PRIORITY,RD_PORT_PRIORITY" line.long 0x4 "DDRCTRL_PCFGW_1,DDRCTRL port 1 configuration write register" bitfld.long 0x4 14. "WR_PORT_PAGEMATCH_EN,WR_PORT_PAGEMATCH_EN" "0,1" bitfld.long 0x4 13. "WR_PORT_URGENT_EN,WR_PORT_URGENT_EN" "0,1" newline bitfld.long 0x4 12. "WR_PORT_AGING_EN,WR_PORT_AGING_EN" "0,1" hexmask.long.word 0x4 0.--9. 1. "WR_PORT_PRIORITY,WR_PORT_PRIORITY" group.long 0x540++0x13 line.long 0x0 "DDRCTRL_PCTRL_1,DDRCTRL port 1 control register" bitfld.long 0x0 0. "PORT_EN,PORT_EN" "0,1" line.long 0x4 "DDRCTRL_PCFGQOS0_1,DDRCTRL port 1 read Q0S configuration register 0" bitfld.long 0x4 24.--25. "RQOS_MAP_REGION2,RQOS_MAP_REGION2" "0,1,2,3" bitfld.long 0x4 20.--21. "RQOS_MAP_REGION1,RQOS_MAP_REGION1" "0,1,2,3" newline bitfld.long 0x4 16.--17. "RQOS_MAP_REGION0,RQOS_MAP_REGION0" "0,1,2,3" hexmask.long.byte 0x4 8.--11. 1. "RQOS_MAP_LEVEL2,RQOS_MAP_LEVEL2" newline hexmask.long.byte 0x4 0.--3. 1. "RQOS_MAP_LEVEL1,RQOS_MAP_LEVEL1" line.long 0x8 "DDRCTRL_PCFGQOS1_1,DDRCTRL port 1 read Q0S configuration register 1" hexmask.long.word 0x8 16.--26. 1. "RQOS_MAP_TIMEOUTR,RQOS_MAP_TIMEOUTR" hexmask.long.word 0x8 0.--10. 1. "RQOS_MAP_TIMEOUTB,RQOS_MAP_TIMEOUTB" line.long 0xC "DDRCTRL_PCFGWQOS0_1,DDRCTRL port 1 write Q0S configuration register 0" bitfld.long 0xC 24.--25. "WQOS_MAP_REGION2,WQOS_MAP_REGION2" "0,1,2,3" bitfld.long 0xC 20.--21. "WQOS_MAP_REGION1,WQOS_MAP_REGION1" "0,1,2,3" newline bitfld.long 0xC 16.--17. "WQOS_MAP_REGION0,WQOS_MAP_REGION0" "0,1,2,3" hexmask.long.byte 0xC 8.--11. 1. "WQOS_MAP_LEVEL2,WQOS_MAP_LEVEL2" newline hexmask.long.byte 0xC 0.--3. 1. "WQOS_MAP_LEVEL1,WQOS_MAP_LEVEL1" line.long 0x10 "DDRCTRL_PCFGWQOS1_1,DDRCTRL port 1 write Q0S configuration register 1" hexmask.long.word 0x10 16.--26. 1. "WQOS_MAP_TIMEOUT2,WQOS_MAP_TIMEOUT2" hexmask.long.word 0x10 0.--10. 1. "WQOS_MAP_TIMEOUT1,WQOS_MAP_TIMEOUT1" endif tree.end tree "DDRPERFM (DDR Performance Monitor)" base ad:0x5A007000 group.long 0x0++0x1B line.long 0x0 "DDRPERFM_CTL,DDRPERFM control register" sif (cpuis("STM32MP13*")) bitfld.long 0x0 1. "STOP,stop all the counters." "0: writing a '0’ has no effect.,1: writing a '1’ stops all the counters" bitfld.long 0x0 0. "START,Start counters which are enabled the time counter (TCNT) is always enabled." "0: writing a '0’ has no effect.,1: writing a '1’ Starts counters which are.." endif sif (cpuis("STM32MP151*")) bitfld.long 0x0 1. "STOP,STOP" "0,1" newline bitfld.long 0x0 0. "START,START" "0,1" endif sif (cpuis("STM32MP153*")) bitfld.long 0x0 1. "STOP,STOP" "0,1" bitfld.long 0x0 0. "START,START" "0,1" newline endif sif (cpuis("STM32MP157*")) bitfld.long 0x0 1. "STOP,STOP" "0,1" bitfld.long 0x0 0. "START,START" "0,1" endif line.long 0x4 "DDRPERFM_CFG,DDRPERFM configurationl register" bitfld.long 0x4 16.--17. "SEL,select set of signals to be monitored (from 0 to 3) (see signal set description in ) and counters to be enabled" "0,1,2,3" sif (cpuis("STM32MP13*")) hexmask.long.byte 0x4 0.--3. 1. "EN,enable counter x (from 0 to 3)" endif sif (cpuis("STM32MP153*")) hexmask.long.byte 0x4 0.--3. 1. "EN,EN" newline endif sif (cpuis("STM32MP157*")) hexmask.long.byte 0x4 0.--3. 1. "EN,EN" endif line.long 0x8 "DDRPERFM_STATUS,DDRPERFM status register" sif (cpuis("STM32MP13*")) rbitfld.long 0x8 31. "TOVF,total counter overflow" "0: no overflow,1: counter overflow" rbitfld.long 0x8 16. "BUSY,Busy Status" "0: DDRPERFM is stopped or a counter is in overflow,1: DDRPERFM is counting (at least TCNT is counting)" hexmask.long.byte 0x8 0.--3. 1. "COVF,Counter x Overflow (with x from 0 to 3)" newline endif sif (cpuis("STM32MP151*")) bitfld.long 0x8 31. "TOVF,TOVF" "0,1" endif sif (cpuis("STM32MP153*")) bitfld.long 0x8 31. "TOVF,TOVF" "0,1" endif sif (cpuis("STM32MP157*")) bitfld.long 0x8 31. "TOVF,TOVF" "0,1" newline endif sif (cpuis("STM32MP151*")) bitfld.long 0x8 16. "BUSY,BUSY" "0,1" endif sif (cpuis("STM32MP153*")) bitfld.long 0x8 16. "BUSY,BUSY" "0,1" endif sif (cpuis("STM32MP157*")) bitfld.long 0x8 16. "BUSY,BUSY" "0,1" newline endif sif (cpuis("STM32MP151*")) hexmask.long.byte 0x8 0.--3. 1. "COVF,COVF" endif sif (cpuis("STM32MP153*")) hexmask.long.byte 0x8 0.--3. 1. "COVF,COVF" endif sif (cpuis("STM32MP157*")) hexmask.long.byte 0x8 0.--3. 1. "COVF,COVF" endif line.long 0xC "DDRPERFM_CCR,DDRPERFM counter clear register" sif (cpuis("STM32MP13*")) bitfld.long 0xC 31. "TCLR,time counter clear" "0: writing a '0’ has no effect,1: writing a '1’ clears the time counter" hexmask.long.byte 0xC 0.--3. 1. "CCLR,counter x Clear (with x from 0 to 3)" endif sif (cpuis("STM32MP151*")) bitfld.long 0xC 31. "TCLR,TCLR" "0,1" newline endif sif (cpuis("STM32MP153*")) bitfld.long 0xC 31. "TCLR,TCLR" "0,1" endif sif (cpuis("STM32MP157*")) bitfld.long 0xC 31. "TCLR,TCLR" "0,1" endif sif (cpuis("STM32MP151*")) hexmask.long.byte 0xC 0.--3. 1. "CCLR,CCLR" newline endif sif (cpuis("STM32MP153*")) hexmask.long.byte 0xC 0.--3. 1. "CCLR,CCLR" endif sif (cpuis("STM32MP157*")) hexmask.long.byte 0xC 0.--3. 1. "CCLR,CCLR" endif line.long 0x10 "DDRPERFM_IER,DDRPERFM interrupt enable register" sif (cpuis("STM32MP13*")) bitfld.long 0x10 0. "OVFIE,overflow interrupt enable" "0: overflow interrupt disabled,1: overflow interrupt enabled" endif sif (cpuis("STM32MP153*")) bitfld.long 0x10 0. "OVFIE,OVFIE" "0,1" endif sif (cpuis("STM32MP157*")) bitfld.long 0x10 0. "OVFIE,OVFIE" "0,1" endif line.long 0x14 "DDRPERFM_ISR,DDRPERFM interrupt status register" sif (cpuis("STM32MP13*")) rbitfld.long 0x14 0. "OVFF,overflow flag" "0,1" endif sif (cpuis("STM32MP151*")) bitfld.long 0x14 0. "OVFF,OVFF" "0,1" endif sif (cpuis("STM32MP153*")) bitfld.long 0x14 0. "OVFF,OVFF" "0,1" newline endif sif (cpuis("STM32MP157*")) bitfld.long 0x14 0. "OVFF,OVFF" "0,1" endif line.long 0x18 "DDRPERFM_ICR,DDRPERFM interrupt clear register" sif (cpuis("STM32MP13*")) bitfld.long 0x18 0. "OVF,overflow flag" "0: no action,1: clears the overflow flag" endif sif (cpuis("STM32MP151*")) bitfld.long 0x18 0. "OVF,OVF" "0,1" endif sif (cpuis("STM32MP153*")) bitfld.long 0x18 0. "OVF,OVF" "0,1" newline endif sif (cpuis("STM32MP157*")) bitfld.long 0x18 0. "OVF,OVF" "0,1" endif group.long 0x20++0x3 line.long 0x0 "DDRPERFM_TCNT,DDRPERFM time counter register" sif (cpuis("STM32MP13*")) hexmask.long 0x0 0.--31. 1. "CNT,total time this is number of DDR controller clocks elapsed while DDRPERFM has been running." endif sif (cpuis("STM32MP151*")) hexmask.long 0x0 0.--31. 1. "CNT,CNT" endif sif (cpuis("STM32MP153*")) hexmask.long 0x0 0.--31. 1. "CNT,CNT" newline endif sif (cpuis("STM32MP157*")) hexmask.long 0x0 0.--31. 1. "CNT,CNT" endif group.long 0x3F0++0xF line.long 0x0 "DDRPERFM_HWCFG,DDRPERFM hardware configuration register" sif (cpuis("STM32MP13*")) hexmask.long.byte 0x0 0.--3. 1. "NCNT,number of counters for this configuration (4)" endif sif (cpuis("STM32MP151*")) hexmask.long.byte 0x0 0.--3. 1. "NCNT,NCNT" endif sif (cpuis("STM32MP153*")) hexmask.long.byte 0x0 0.--3. 1. "NCNT,NCNT" newline endif sif (cpuis("STM32MP157*")) hexmask.long.byte 0x0 0.--3. 1. "NCNT,NCNT" endif line.long 0x4 "DDRPERFM_VER,DDRPERFM version register" sif (cpuis("STM32MP13*")) hexmask.long.byte 0x4 4.--7. 1. "MAJREV,Major revision number." hexmask.long.byte 0x4 0.--3. 1. "MINREV,Minor revision number." endif sif (cpuis("STM32MP151*")) hexmask.long.byte 0x4 4.--7. 1. "MAJREV,MAJREV" newline hexmask.long.byte 0x4 0.--3. 1. "MINREV,MINREV" endif sif (cpuis("STM32MP153*")) hexmask.long.byte 0x4 4.--7. 1. "MAJREV,MAJREV" hexmask.long.byte 0x4 0.--3. 1. "MINREV,MINREV" newline endif sif (cpuis("STM32MP157*")) hexmask.long.byte 0x4 4.--7. 1. "MAJREV,MAJREV" hexmask.long.byte 0x4 0.--3. 1. "MINREV,MINREV" endif line.long 0x8 "DDRPERFM_ID,DDRPERFM ID register" sif (cpuis("STM32MP13*")) hexmask.long 0x8 0.--31. 1. "ID,DDRPERFM unique identification." endif sif (cpuis("STM32MP151*")) hexmask.long 0x8 0.--31. 1. "ID,ID" endif sif (cpuis("STM32MP153*")) hexmask.long 0x8 0.--31. 1. "ID,ID" newline endif sif (cpuis("STM32MP157*")) hexmask.long 0x8 0.--31. 1. "ID,ID" endif line.long 0xC "DDRPERFM_SID,DDRPERFM magic ID register" sif (cpuis("STM32MP13*")) hexmask.long 0xC 0.--31. 1. "SID,magic ID for automatic IP discovery." endif sif (cpuis("STM32MP151*")) hexmask.long 0xC 0.--31. 1. "SID,SID" endif sif (cpuis("STM32MP153*")) hexmask.long 0xC 0.--31. 1. "SID,SID" newline endif sif (cpuis("STM32MP157*")) hexmask.long 0xC 0.--31. 1. "SID,SID" endif sif (cpuis("STM32MP13*")) rgroup.long 0x30++0x3 line.long 0x0 "DDRPERFM_CNT0,DDRPERFM event counter 0 register" hexmask.long 0x0 0.--31. 1. "CNT,event counter value." rgroup.long 0x38++0x3 line.long 0x0 "DDRPERFM_CNT1,DDRPERFM event counter 1 register" hexmask.long 0x0 0.--31. 1. "CNT,event counter value." rgroup.long 0x40++0x3 line.long 0x0 "DDRPERFM_CNT2,DDRPERFM event counter 2 register" hexmask.long 0x0 0.--31. 1. "CNT,event counter value." rgroup.long 0x48++0x3 line.long 0x0 "DDRPERFM_CNT3,DDRPERFM event counter 3 register" hexmask.long 0x0 0.--31. 1. "CNT,event counter value." endif sif (cpuis("STM32MP151*")) wgroup.long 0x0++0x3 line.long 0x0 "DDRPERFM_CTL,Write-only register. A read request returns all zeros." endif sif (cpuis("STM32MP151*")) rgroup.long 0x8++0x3 line.long 0x0 "DDRPERFM_STATUS,DDRPERFM status register" endif sif (cpuis("STM32MP151*")) wgroup.long 0xC++0x3 line.long 0x0 "DDRPERFM_CCR,Write-only register. A read request returns all zeros" endif sif (cpuis("STM32MP151*")) rgroup.long 0x14++0x3 line.long 0x0 "DDRPERFM_ISR,DDRPERFM interrupt status register" endif sif (cpuis("STM32MP151*")) wgroup.long 0x18++0x3 line.long 0x0 "DDRPERFM_ICR,Write-only register. A read request returns all zeros" endif sif (cpuis("STM32MP151*")) rgroup.long 0x20++0x3 line.long 0x0 "DDRPERFM_TCNT,DDRPERFM time counter register" rgroup.long 0x60++0x3 line.long 0x0 "DDRPERFM_CNT0,DDRPERFM event counter 0 register" hexmask.long 0x0 0.--31. 1. "CNT,CNT" rgroup.long 0x68++0x3 line.long 0x0 "DDRPERFM_CNT1,DDRPERFM event counter 1 register" hexmask.long 0x0 0.--31. 1. "CNT,CNT" rgroup.long 0x70++0x3 line.long 0x0 "DDRPERFM_CNT2,DDRPERFM event counter 2 register" hexmask.long 0x0 0.--31. 1. "CNT,CNT" rgroup.long 0x78++0x3 line.long 0x0 "DDRPERFM_CNT3,DDRPERFM event counter 3 register" hexmask.long 0x0 0.--31. 1. "CNT,CNT" endif sif (cpuis("STM32MP151*")) rgroup.long 0x3F0++0x3 line.long 0x0 "DDRPERFM_HWCFG,DDRPERFM hardware configuration register" endif sif (cpuis("STM32MP151*")) rgroup.long 0x3F4++0x3 line.long 0x0 "DDRPERFM_VER,DDRPERFM version register" endif sif (cpuis("STM32MP151*")) rgroup.long 0x3F8++0x3 line.long 0x0 "DDRPERFM_ID,DDRPERFM ID register" endif sif (cpuis("STM32MP151*")) rgroup.long 0x3FC++0x3 line.long 0x0 "DDRPERFM_SID,DDRPERFM magic ID register" endif sif (cpuis("STM32MP153*")) wgroup.long 0x0++0x3 line.long 0x0 "DDRPERFM_CTL,Write-only register. A read request returns all zeros." endif sif (cpuis("STM32MP153*")) rgroup.long 0x8++0x3 line.long 0x0 "DDRPERFM_STATUS,DDRPERFM status register" endif sif (cpuis("STM32MP153*")) wgroup.long 0xC++0x3 line.long 0x0 "DDRPERFM_CCR,Write-only register. A read request returns all zeros" endif sif (cpuis("STM32MP153*")) rgroup.long 0x14++0x3 line.long 0x0 "DDRPERFM_ISR,DDRPERFM interrupt status register" endif sif (cpuis("STM32MP153*")) wgroup.long 0x18++0x3 line.long 0x0 "DDRPERFM_ICR,Write-only register. A read request returns all zeros" endif sif (cpuis("STM32MP153*")) rgroup.long 0x20++0x3 line.long 0x0 "DDRPERFM_TCNT,DDRPERFM time counter register" rgroup.long 0x60++0x3 line.long 0x0 "DDRPERFM_CNT0,DDRPERFM event counter 0 register" hexmask.long 0x0 0.--31. 1. "CNT,CNT" rgroup.long 0x68++0x3 line.long 0x0 "DDRPERFM_CNT1,DDRPERFM event counter 1 register" hexmask.long 0x0 0.--31. 1. "CNT,CNT" rgroup.long 0x70++0x3 line.long 0x0 "DDRPERFM_CNT2,DDRPERFM event counter 2 register" hexmask.long 0x0 0.--31. 1. "CNT,CNT" rgroup.long 0x78++0x3 line.long 0x0 "DDRPERFM_CNT3,DDRPERFM event counter 3 register" hexmask.long 0x0 0.--31. 1. "CNT,CNT" endif sif (cpuis("STM32MP153*")) rgroup.long 0x3F0++0x3 line.long 0x0 "DDRPERFM_HWCFG,DDRPERFM hardware configuration register" endif sif (cpuis("STM32MP153*")) rgroup.long 0x3F4++0x3 line.long 0x0 "DDRPERFM_VER,DDRPERFM version register" endif sif (cpuis("STM32MP153*")) rgroup.long 0x3F8++0x3 line.long 0x0 "DDRPERFM_ID,DDRPERFM ID register" endif sif (cpuis("STM32MP153*")) rgroup.long 0x3FC++0x3 line.long 0x0 "DDRPERFM_SID,DDRPERFM magic ID register" endif sif (cpuis("STM32MP157*")) wgroup.long 0x0++0x3 line.long 0x0 "DDRPERFM_CTL,Write-only register. A read request returns all zeros." endif sif (cpuis("STM32MP157*")) rgroup.long 0x8++0x3 line.long 0x0 "DDRPERFM_STATUS,DDRPERFM status register" endif sif (cpuis("STM32MP157*")) wgroup.long 0xC++0x3 line.long 0x0 "DDRPERFM_CCR,Write-only register. A read request returns all zeros" endif sif (cpuis("STM32MP157*")) rgroup.long 0x14++0x3 line.long 0x0 "DDRPERFM_ISR,DDRPERFM interrupt status register" endif sif (cpuis("STM32MP157*")) wgroup.long 0x18++0x3 line.long 0x0 "DDRPERFM_ICR,Write-only register. A read request returns all zeros" endif sif (cpuis("STM32MP157*")) rgroup.long 0x20++0x3 line.long 0x0 "DDRPERFM_TCNT,DDRPERFM time counter register" rgroup.long 0x60++0x3 line.long 0x0 "DDRPERFM_CNT0,DDRPERFM event counter 0 register" hexmask.long 0x0 0.--31. 1. "CNT,CNT" rgroup.long 0x68++0x3 line.long 0x0 "DDRPERFM_CNT1,DDRPERFM event counter 1 register" hexmask.long 0x0 0.--31. 1. "CNT,CNT" rgroup.long 0x70++0x3 line.long 0x0 "DDRPERFM_CNT2,DDRPERFM event counter 2 register" hexmask.long 0x0 0.--31. 1. "CNT,CNT" rgroup.long 0x78++0x3 line.long 0x0 "DDRPERFM_CNT3,DDRPERFM event counter 3 register" hexmask.long 0x0 0.--31. 1. "CNT,CNT" endif sif (cpuis("STM32MP157*")) rgroup.long 0x3F0++0x3 line.long 0x0 "DDRPERFM_HWCFG,DDRPERFM hardware configuration register" endif sif (cpuis("STM32MP157*")) rgroup.long 0x3F4++0x3 line.long 0x0 "DDRPERFM_VER,DDRPERFM version register" endif sif (cpuis("STM32MP157*")) rgroup.long 0x3F8++0x3 line.long 0x0 "DDRPERFM_ID,DDRPERFM ID register" endif sif (cpuis("STM32MP157*")) rgroup.long 0x3FC++0x3 line.long 0x0 "DDRPERFM_SID,DDRPERFM magic ID register" endif tree.end tree "DDRPHYC (DDR Physical Interface Control)" base ad:0x5A004000 group.long 0x0++0x3F line.long 0x0 "DDRPHYC_RIDR,DDRPHYC revision ID register" sif (cpuis("STM32MP13*")) hexmask.long.byte 0x0 24.--31. 1. "UDRID,User-defined rev ID" hexmask.long.byte 0x0 20.--23. 1. "PHYMJR,PHY maj rev" newline hexmask.long.byte 0x0 16.--19. 1. "PHYMDR,PHY moderate rev" hexmask.long.byte 0x0 12.--15. 1. "PHYMNR,PHY minor rev" newline hexmask.long.byte 0x0 8.--11. 1. "PUBMJR,PUB maj rev" hexmask.long.byte 0x0 4.--7. 1. "PUBMDR,PUB moderate rev" newline hexmask.long.byte 0x0 0.--3. 1. "PUBMNR,PUB minor rev" endif sif (cpuis("STM32MP151*")) hexmask.long.byte 0x0 24.--31. 1. "UDRID,UDRID" newline hexmask.long.byte 0x0 20.--23. 1. "PHYMJR,PHYMJR" hexmask.long.byte 0x0 16.--19. 1. "PHYMDR,PHYMDR" newline hexmask.long.byte 0x0 12.--15. 1. "PHYMNR,PHYMNR" hexmask.long.byte 0x0 8.--11. 1. "PUBMJR,PUBMJR" newline hexmask.long.byte 0x0 4.--7. 1. "PUBMDR,PUBMDR" hexmask.long.byte 0x0 0.--3. 1. "PUBMNR,PUBMNR" newline endif sif (cpuis("STM32MP153*")) hexmask.long.byte 0x0 24.--31. 1. "UDRID,UDRID" hexmask.long.byte 0x0 20.--23. 1. "PHYMJR,PHYMJR" newline hexmask.long.byte 0x0 16.--19. 1. "PHYMDR,PHYMDR" hexmask.long.byte 0x0 12.--15. 1. "PHYMNR,PHYMNR" newline hexmask.long.byte 0x0 8.--11. 1. "PUBMJR,PUBMJR" hexmask.long.byte 0x0 4.--7. 1. "PUBMDR,PUBMDR" newline hexmask.long.byte 0x0 0.--3. 1. "PUBMNR,PUBMNR" endif sif (cpuis("STM32MP157*")) hexmask.long.byte 0x0 24.--31. 1. "UDRID,UDRID" newline hexmask.long.byte 0x0 20.--23. 1. "PHYMJR,PHYMJR" hexmask.long.byte 0x0 16.--19. 1. "PHYMDR,PHYMDR" newline hexmask.long.byte 0x0 12.--15. 1. "PHYMNR,PHYMNR" hexmask.long.byte 0x0 8.--11. 1. "PUBMJR,PUBMJR" newline hexmask.long.byte 0x0 4.--7. 1. "PUBMDR,PUBMDR" hexmask.long.byte 0x0 0.--3. 1. "PUBMNR,PUBMNR" endif line.long 0x4 "DDRPHYC_PIR,DDRPHYC PHY initialization register" sif (cpuis("STM32MP13*")) bitfld.long 0x4 31. "INITBYP,Initialization bypass" "0,1" bitfld.long 0x4 30. "ZCALBYP,zcal bypass" "0,1" newline bitfld.long 0x4 29. "LOCKBYP,DLL lock bypass" "0,1" bitfld.long 0x4 28. "CLRSR,clear status register" "0,1" newline bitfld.long 0x4 18. "CTLDINIT,Controller DRAM initialization" "0,1" bitfld.long 0x4 17. "DLLBYP,DLL bypass" "0,1" newline bitfld.long 0x4 16. "ICPC,Initialization complete pin configuration" "0: Asserted after PHY initialization (DLL locking..,1: Asserted after PHY initialization is complete.." bitfld.long 0x4 8. "RVTRN,Read DQS gate training DQSTRN) and RV training (RVTRN) should normally be run" "0,1" newline bitfld.long 0x4 7. "QSTRN,Read DQS training" "0,1" bitfld.long 0x4 6. "DRAMINIT,DRAM initialization" "0,1" newline bitfld.long 0x4 5. "DRAMRST,DRAM reset (DDR3 only)" "0,1" bitfld.long 0x4 4. "ITMSRST,ITM reset" "0,1" newline bitfld.long 0x4 3. "ZCAL,Impedance calibration (Driver and ODT)" "0,1" bitfld.long 0x4 2. "DLLLOCK,DLL lock" "0,1" newline bitfld.long 0x4 1. "DLLSRST,DLL soft reset" "0,1" bitfld.long 0x4 0. "INIT,Initialization trigger" "0,1" newline endif sif (cpuis("STM32MP151*")) bitfld.long 0x4 31. "INITBYP,INITBYP" "0,1" bitfld.long 0x4 30. "ZCALBYP,ZCALBYP" "0,1" newline bitfld.long 0x4 29. "LOCKBYP,LOCKBYP" "0,1" bitfld.long 0x4 28. "CLRSR,CLRSR" "0,1" newline endif sif (cpuis("STM32MP153*")) bitfld.long 0x4 31. "INITBYP,INITBYP" "0,1" bitfld.long 0x4 30. "ZCALBYP,ZCALBYP" "0,1" newline bitfld.long 0x4 29. "LOCKBYP,LOCKBYP" "0,1" bitfld.long 0x4 28. "CLRSR,CLRSR" "0,1" newline endif sif (cpuis("STM32MP157*")) bitfld.long 0x4 31. "INITBYP,INITBYP" "0,1" bitfld.long 0x4 30. "ZCALBYP,ZCALBYP" "0,1" newline bitfld.long 0x4 29. "LOCKBYP,LOCKBYP" "0,1" bitfld.long 0x4 28. "CLRSR,CLRSR" "0,1" newline endif sif (cpuis("STM32MP151*")) bitfld.long 0x4 18. "CTLDINIT,CTLDINIT" "0,1" bitfld.long 0x4 17. "DLLBYP,DLLBYP" "0,1" newline bitfld.long 0x4 16. "ICPC,ICPC" "0,1" endif sif (cpuis("STM32MP153*")) bitfld.long 0x4 18. "CTLDINIT,CTLDINIT" "0,1" newline bitfld.long 0x4 17. "DLLBYP,DLLBYP" "0,1" bitfld.long 0x4 16. "ICPC,ICPC" "0,1" newline endif sif (cpuis("STM32MP157*")) bitfld.long 0x4 18. "CTLDINIT,CTLDINIT" "0,1" bitfld.long 0x4 17. "DLLBYP,DLLBYP" "0,1" newline bitfld.long 0x4 16. "ICPC,ICPC" "0,1" endif sif (cpuis("STM32MP151*")) bitfld.long 0x4 8. "RVTRN,RVTRN" "0,1" newline bitfld.long 0x4 7. "QSTRN,QSTRN" "0,1" bitfld.long 0x4 6. "DRAMINIT,DRAMINIT" "0,1" newline bitfld.long 0x4 5. "DRAMRST,DRAMRST" "0,1" bitfld.long 0x4 4. "ITMSRST,ITMSRST" "0,1" newline bitfld.long 0x4 3. "ZCAL,ZCAL" "0,1" bitfld.long 0x4 2. "DLLLOCK,DLLLOCK" "0,1" newline bitfld.long 0x4 1. "DLLSRST,DLLSRST" "0,1" bitfld.long 0x4 0. "INIT,INIT" "0,1" newline endif sif (cpuis("STM32MP153*")) bitfld.long 0x4 8. "RVTRN,RVTRN" "0,1" bitfld.long 0x4 7. "QSTRN,QSTRN" "0,1" newline bitfld.long 0x4 6. "DRAMINIT,DRAMINIT" "0,1" bitfld.long 0x4 5. "DRAMRST,DRAMRST" "0,1" newline bitfld.long 0x4 4. "ITMSRST,ITMSRST" "0,1" bitfld.long 0x4 3. "ZCAL,ZCAL" "0,1" newline bitfld.long 0x4 2. "DLLLOCK,DLLLOCK" "0,1" bitfld.long 0x4 1. "DLLSRST,DLLSRST" "0,1" newline bitfld.long 0x4 0. "INIT,INIT" "0,1" endif sif (cpuis("STM32MP157*")) bitfld.long 0x4 8. "RVTRN,RVTRN" "0,1" newline bitfld.long 0x4 7. "QSTRN,QSTRN" "0,1" bitfld.long 0x4 6. "DRAMINIT,DRAMINIT" "0,1" newline bitfld.long 0x4 5. "DRAMRST,DRAMRST" "0,1" bitfld.long 0x4 4. "ITMSRST,ITMSRST" "0,1" newline bitfld.long 0x4 3. "ZCAL,ZCAL" "0,1" bitfld.long 0x4 2. "DLLLOCK,DLLLOCK" "0,1" newline bitfld.long 0x4 1. "DLLSRST,DLLSRST" "0,1" bitfld.long 0x4 0. "INIT,INIT" "0,1" endif line.long 0x8 "DDRPHYC_PGCR,DDRPHYC PHY global control register" bitfld.long 0x8 31. "LBMODE,Loop back mode" "0,1" sif (cpuis("STM32MP13*")) bitfld.long 0x8 30. "LBGDQS,Loop back DQS gating" "0: DQS gate training is triggered on the PUB,1: DQS gate is set manually using software" newline bitfld.long 0x8 29. "LBDQSS,Loop back DQS shift" "0: PUB sets the read DQS delay to 0; DQS is already..,1: The read DQS shift is set manually through.." bitfld.long 0x8 22.--23. "ZKSEL,Impedance clock divider selection" "0: Divide by 2,1: Divide by 8,2: Divide by 32,3: Divide by 64" newline bitfld.long 0x8 15. "IOLB,I/O loop back select" "0: Loopback is after output buffer; output enable..,1: Loopback is before output buffer; output enable.." hexmask.long.byte 0x8 5.--8. 1. "DTOSEL,Digital test output select" newline bitfld.long 0x8 3.--4. "DFTLMT,DQS drift limit" "0: No limit (no error reported),1: 90° drift,2: 180° drift,3: 270° or more drift" bitfld.long 0x8 2. "DFTCMP,DQS drift compensation" "0: Disables data strobe drift compensation,1: Enables data strobe drift compensation" newline bitfld.long 0x8 1. "DQSCFG,DQS gating configuration" "0: DQS gating is shut off using the rising edge of..,1: DQS gating blankets the whole burst (passive.." bitfld.long 0x8 0. "ITMDMD,ITM DDR mode" "0: ITMS uses DQS and DQS#,1: ITMS uses DQS only" newline endif sif (cpuis("STM32MP151*")) bitfld.long 0x8 30. "LBGDQS,LBGDQS" "0,1" bitfld.long 0x8 29. "LBDQSS,LBDQSS" "0,1" newline endif sif (cpuis("STM32MP153*")) bitfld.long 0x8 30. "LBGDQS,LBGDQS" "0,1" bitfld.long 0x8 29. "LBDQSS,LBDQSS" "0,1" newline endif sif (cpuis("STM32MP157*")) bitfld.long 0x8 30. "LBGDQS,LBGDQS" "0,1" bitfld.long 0x8 29. "LBDQSS,LBDQSS" "0,1" newline endif hexmask.long.byte 0x8 25.--28. 1. "RFSHDT,Refresh during training" bitfld.long 0x8 24. "PDDISDX,Power down disabled byte" "0,1" newline sif (cpuis("STM32MP151*")) bitfld.long 0x8 22.--23. "ZKSEL,ZKSEL" "0,1,2,3" endif sif (cpuis("STM32MP153*")) bitfld.long 0x8 22.--23. "ZKSEL,ZKSEL" "0,1,2,3" newline endif sif (cpuis("STM32MP157*")) bitfld.long 0x8 22.--23. "ZKSEL,ZKSEL" "0,1,2,3" endif hexmask.long.byte 0x8 18.--21. 1. "RANKEN,Rank enable" newline bitfld.long 0x8 16.--17. "IODDRM,I/O DDR mode" "0,1,2,3" sif (cpuis("STM32MP151*")) bitfld.long 0x8 15. "IOLB,IOLB" "0,1" newline endif sif (cpuis("STM32MP153*")) bitfld.long 0x8 15. "IOLB,IOLB" "0,1" endif sif (cpuis("STM32MP157*")) bitfld.long 0x8 15. "IOLB,IOLB" "0,1" newline endif bitfld.long 0x8 14. "CKINV,CK invert" "0,1" bitfld.long 0x8 12.--13. "CKDV,CK disable value" "0,1,2,3" newline bitfld.long 0x8 9.--11. "CKEN,CK enable" "0,1,2,3,4,5,6,7" sif (cpuis("STM32MP151*")) hexmask.long.byte 0x8 5.--8. 1. "DTOSEL,DTOSEL" newline bitfld.long 0x8 3.--4. "DFTLMT,DFTLMT" "0,1,2,3" bitfld.long 0x8 2. "DFTCMP,DFTCMP" "0,1" newline bitfld.long 0x8 1. "DQSCFG,DQSCFG" "0,1" endif sif (cpuis("STM32MP153*")) hexmask.long.byte 0x8 5.--8. 1. "DTOSEL,DTOSEL" newline bitfld.long 0x8 3.--4. "DFTLMT,DFTLMT" "0,1,2,3" bitfld.long 0x8 2. "DFTCMP,DFTCMP" "0,1" newline bitfld.long 0x8 1. "DQSCFG,DQSCFG" "0,1" bitfld.long 0x8 0. "ITMDMD,ITMDMD" "0,1" newline endif sif (cpuis("STM32MP157*")) hexmask.long.byte 0x8 5.--8. 1. "DTOSEL,DTOSEL" bitfld.long 0x8 3.--4. "DFTLMT,DFTLMT" "0,1,2,3" newline bitfld.long 0x8 2. "DFTCMP,DFTCMP" "0,1" bitfld.long 0x8 1. "DQSCFG,DQSCFG" "0,1" newline bitfld.long 0x8 0. "ITMDMD,ITMDMD" "0,1" endif line.long 0xC "DDRPHYC_PGSR,DDRPHYC PHY global status register" sif (cpuis("STM32MP13*")) rbitfld.long 0xC 31. "TQ,Temperature output (LPDDR only) N/A" "0,1" rbitfld.long 0xC 9. "RVEIRR,Read valid training intermittent error" "0,1" newline rbitfld.long 0xC 8. "RVERR,Read valid training error" "0,1" rbitfld.long 0xC 7. "DFTERR,DQS drift error" "0,1" newline rbitfld.long 0xC 6. "DTIERR,DQS gate training intermittent error" "0,1" rbitfld.long 0xC 5. "DTERR,DQS gate training error" "0,1" newline rbitfld.long 0xC 4. "DTDONE,Data training done" "0,1" rbitfld.long 0xC 3. "DIDONE,DRAM initialization done" "0,1" newline rbitfld.long 0xC 2. "ZCDDONE,zcal done" "0,1" rbitfld.long 0xC 1. "DLDONE,DLL lock done" "0,1" newline rbitfld.long 0xC 0. "IDONE,Initialization done" "0,1" endif sif (cpuis("STM32MP151*")) bitfld.long 0xC 31. "TQ,TQ" "0,1" newline endif sif (cpuis("STM32MP153*")) bitfld.long 0xC 31. "TQ,TQ" "0,1" endif sif (cpuis("STM32MP157*")) bitfld.long 0xC 31. "TQ,TQ" "0,1" newline endif sif (cpuis("STM32MP151*")) bitfld.long 0xC 9. "RVEIRR,RVEIRR" "0,1" bitfld.long 0xC 8. "RVERR,RVERR" "0,1" newline bitfld.long 0xC 7. "DFTERR,DFTERR" "0,1" bitfld.long 0xC 6. "DTIERR,DTIERR" "0,1" newline bitfld.long 0xC 5. "DTERR,DTERR" "0,1" bitfld.long 0xC 4. "DTDONE,DTDONE" "0,1" newline bitfld.long 0xC 3. "DIDONE,DIDONE" "0,1" bitfld.long 0xC 2. "ZCDDONE,ZCDDONE" "0,1" newline bitfld.long 0xC 1. "DLDONE,DLDONE" "0,1" bitfld.long 0xC 0. "IDONE,IDONE" "0,1" newline endif sif (cpuis("STM32MP153*")) bitfld.long 0xC 9. "RVEIRR,RVEIRR" "0,1" bitfld.long 0xC 8. "RVERR,RVERR" "0,1" newline bitfld.long 0xC 7. "DFTERR,DFTERR" "0,1" bitfld.long 0xC 6. "DTIERR,DTIERR" "0,1" newline bitfld.long 0xC 5. "DTERR,DTERR" "0,1" bitfld.long 0xC 4. "DTDONE,DTDONE" "0,1" newline bitfld.long 0xC 3. "DIDONE,DIDONE" "0,1" bitfld.long 0xC 2. "ZCDDONE,ZCDDONE" "0,1" newline bitfld.long 0xC 1. "DLDONE,DLDONE" "0,1" bitfld.long 0xC 0. "IDONE,IDONE" "0,1" newline endif sif (cpuis("STM32MP157*")) bitfld.long 0xC 9. "RVEIRR,RVEIRR" "0,1" bitfld.long 0xC 8. "RVERR,RVERR" "0,1" newline bitfld.long 0xC 7. "DFTERR,DFTERR" "0,1" bitfld.long 0xC 6. "DTIERR,DTIERR" "0,1" newline bitfld.long 0xC 5. "DTERR,DTERR" "0,1" bitfld.long 0xC 4. "DTDONE,DTDONE" "0,1" newline bitfld.long 0xC 3. "DIDONE,DIDONE" "0,1" bitfld.long 0xC 2. "ZCDDONE,ZCDDONE" "0,1" newline bitfld.long 0xC 1. "DLDONE,DLDONE" "0,1" bitfld.long 0xC 0. "IDONE,IDONE" "0,1" endif line.long 0x10 "DDRPHYC_DLLGCR,DDRPHYC DDR DLL global control register" bitfld.long 0x10 30.--31. "DLLRSVD2,These bit are connected to the DLL control bus and reserved for future use." "0,1,2,3" bitfld.long 0x10 29. "LOCKDET,Master lock detect enable" "0,1" newline sif (cpuis("STM32MP13*")) bitfld.long 0x10 27.--28. "FDTRMSL,Slave bypass fixed delay trim" "0: Nominal delay,1: Nominal delay – 10%,2: Nominal delay + 10%,3: Nominal delay + 20%" bitfld.long 0x10 23. "BPS200,Bypass mode frequency range" "0: 0 to 100 MHz,1: 0 to 200 MHz" newline bitfld.long 0x10 9.--10. "ATC,Analog test control" "0: Replica bias output for PMOS (Vbp),1: Replica bias output for NMOS (Vbn),2: Filter output (Vc),3: VDDCORE" bitfld.long 0x10 2.--4. "IPUMP,Charge pump current trim" "0: maximum current,?,?,?,?,?,?,7: minimum current" newline bitfld.long 0x10 0.--1. "DRES,Trim reference current versus resistor value variation" "0: Rnom,1: Rnom - 20%,?,?" endif sif (cpuis("STM32MP151*")) bitfld.long 0x10 27.--28. "FDTRMSL,FDTRMSL" "0,1,2,3" newline endif sif (cpuis("STM32MP153*")) bitfld.long 0x10 27.--28. "FDTRMSL,FDTRMSL" "0,1,2,3" endif sif (cpuis("STM32MP157*")) bitfld.long 0x10 27.--28. "FDTRMSL,FDTRMSL" "0,1,2,3" newline endif bitfld.long 0x10 24.--26. "SBIAS5_3,Slave bias trim" "0,1,2,3,4,5,6,7" sif (cpuis("STM32MP151*")) bitfld.long 0x10 23. "BPS200,BPS200" "0,1" newline endif sif (cpuis("STM32MP153*")) bitfld.long 0x10 23. "BPS200,BPS200" "0,1" endif sif (cpuis("STM32MP157*")) bitfld.long 0x10 23. "BPS200,BPS200" "0,1" newline endif bitfld.long 0x10 20.--22. "SBIAS2_0,Slave bias trim" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x10 12.--19. 1. "MBIAS,Master bias trim" newline bitfld.long 0x10 11. "TESTSW,Test switch" "0,1" sif (cpuis("STM32MP151*")) bitfld.long 0x10 9.--10. "ATC,ATC" "0,1,2,3" newline endif sif (cpuis("STM32MP153*")) bitfld.long 0x10 9.--10. "ATC,ATC" "0,1,2,3" endif sif (cpuis("STM32MP157*")) bitfld.long 0x10 9.--10. "ATC,ATC" "0,1,2,3" newline endif bitfld.long 0x10 6.--8. "DTC,Digital test control" "0,1,2,3,4,5,6,7" bitfld.long 0x10 5. "TESTEN,Test enable" "0,1" newline sif (cpuis("STM32MP151*")) bitfld.long 0x10 2.--4. "IPUMP,IPUMP" "0,1,2,3,4,5,6,7" endif sif (cpuis("STM32MP153*")) bitfld.long 0x10 2.--4. "IPUMP,IPUMP" "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 0.--1. "DRES,DRES" "0,1,2,3" endif sif (cpuis("STM32MP157*")) bitfld.long 0x10 2.--4. "IPUMP,IPUMP" "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 0.--1. "DRES,DRES" "0,1,2,3" endif line.long 0x14 "DDRPHYC_ACDLLCR,DDRPHYC AC DLL control register" bitfld.long 0x14 31. "DLLDIS,DLL disable" "0,1" bitfld.long 0x14 30. "DLLSRST,DLL soft reset" "0,1" newline bitfld.long 0x14 18. "ATESTEN,Analog test enable" "0,1" sif (cpuis("STM32MP13*")) bitfld.long 0x14 9.--11. "MFWDLY,Master DLL feed-forward delay trim" "0: minimum delay,?,?,?,?,?,?,7: maximum delay" newline bitfld.long 0x14 6.--8. "MFBDLY,Master DLL feed-back delay trim" "0: minimum delay,?,?,?,?,?,?,7: maximum delay" endif sif (cpuis("STM32MP151*")) bitfld.long 0x14 9.--11. "MFWDLY,MFWDLY" "0,1,2,3,4,5,6,7" newline endif sif (cpuis("STM32MP153*")) bitfld.long 0x14 9.--11. "MFWDLY,MFWDLY" "0,1,2,3,4,5,6,7" bitfld.long 0x14 6.--8. "MFBDLY,MFBDLY" "0,1,2,3,4,5,6,7" newline endif sif (cpuis("STM32MP157*")) bitfld.long 0x14 9.--11. "MFWDLY,MFWDLY" "0,1,2,3,4,5,6,7" bitfld.long 0x14 6.--8. "MFBDLY,MFBDLY" "0,1,2,3,4,5,6,7" endif line.long 0x18 "DDRPHYC_PTR0,DDRPHYC PT register 0" hexmask.long.byte 0x18 18.--21. 1. "TITMSRST,ITM soft reset" hexmask.long.word 0x18 6.--17. 1. "TDLLLOCK,DLL lock time" newline hexmask.long.byte 0x18 0.--5. 1. "TDLLSRST,DLL soft reset" line.long 0x1C "DDRPHYC_PTR1,DDRPHYC PT register 1" hexmask.long.byte 0x1C 19.--26. 1. "TDINIT1,tDINIT1" hexmask.long.tbyte 0x1C 0.--18. 1. "TDINIT0,tDINIT0" line.long 0x20 "DDRPHYC_PTR2,DDRPHYC PT register 2" hexmask.long.word 0x20 17.--26. 1. "TDINIT3,tDINIT3" hexmask.long.tbyte 0x20 0.--16. 1. "TDINIT2,tDINIT2" line.long 0x24 "DDRPHYC_ACIOCR,DDRPHYC ACIOC register" bitfld.long 0x24 30.--31. "ACSR,AC slew rate" "0,1,2,3" bitfld.long 0x24 29. "RSTIOM,Reset I/O mode" "0,1" newline bitfld.long 0x24 28. "RSTPDR,RST pin power down receiver" "0,1" bitfld.long 0x24 27. "RSTPDD,RST pin power down driver" "0,1" newline bitfld.long 0x24 26. "RSTODT,RST pin ODT" "0,1" bitfld.long 0x24 22. "RANKPDR,Rank power down receiver" "0,1" newline bitfld.long 0x24 18. "CSPDD,CS power down driver" "0,1" bitfld.long 0x24 14. "RANKODT,Rank ODT" "0,1" newline bitfld.long 0x24 11.--13. "CKPDR,CK pin power down receiver" "0,1,2,3,4,5,6,7" bitfld.long 0x24 8.--10. "CKPDD,CK pin power down driver" "0,1,2,3,4,5,6,7" newline bitfld.long 0x24 5.--7. "CKODT,CK pin ODT" "0,1,2,3,4,5,6,7" bitfld.long 0x24 4. "ACPDR,AC pins power down receivers" "0,1" newline bitfld.long 0x24 3. "ACPDD,AC pins power down drivers" "0,1" bitfld.long 0x24 2. "ACODT,AC pins ODT" "0,1" newline bitfld.long 0x24 1. "ACOE,AC pins output enable" "0,1" bitfld.long 0x24 0. "ACIOM,AC pins I/O mode" "0,1" line.long 0x28 "DDRPHYC_DXCCR,DDRPHYC DXCC register" bitfld.long 0x28 16. "AWDT,Active window data train" "0,1" sif (cpuis("STM32MP13*")) bitfld.long 0x28 15. "RVSEL,ITMD read valid select" "0: ITMD read valid signal is generated by delayed..,1: ITMD read valid is generated by the ITMD itself.." newline hexmask.long.byte 0x28 4.--7. 1. "DQSRES,DQS resistor" endif sif (cpuis("STM32MP151*")) bitfld.long 0x28 15. "RVSEL,RVSEL" "0,1" newline endif sif (cpuis("STM32MP153*")) bitfld.long 0x28 15. "RVSEL,RVSEL" "0,1" endif sif (cpuis("STM32MP157*")) bitfld.long 0x28 15. "RVSEL,RVSEL" "0,1" newline endif bitfld.long 0x28 14. "DQSNRST,DQS reset" "0,1" hexmask.long.byte 0x28 8.--11. 1. "DQSNRES,DQS# resistor" newline sif (cpuis("STM32MP151*")) hexmask.long.byte 0x28 4.--7. 1. "DQSRES,DQSRES" endif sif (cpuis("STM32MP153*")) hexmask.long.byte 0x28 4.--7. 1. "DQSRES,DQSRES" newline endif sif (cpuis("STM32MP157*")) hexmask.long.byte 0x28 4.--7. 1. "DQSRES,DQSRES" endif bitfld.long 0x28 3. "DXPDR,Data power down receiver" "0,1" newline bitfld.long 0x28 2. "DXPDD,Data power down driver" "0,1" bitfld.long 0x28 1. "DXIOM,Data I/O mode" "0,1" newline bitfld.long 0x28 0. "DXODT,Data on die termination" "0,1" line.long 0x2C "DDRPHYC_DSGCR,DDRPHYC DSGC register" bitfld.long 0x2C 31. "CKEOE,CKE output enable" "0,1" bitfld.long 0x2C 30. "RSTOE,RST output enable" "0,1" newline bitfld.long 0x2C 29. "ODTOE,ODT output enable" "0,1" bitfld.long 0x2C 28. "CKOE,CK output enable" "0,1" newline bitfld.long 0x2C 27. "TPDOE,TPD output enable (N/A LPDDR only)" "0,1" bitfld.long 0x2C 26. "TPDPD,TPD power down driver (N/A LPDDR only)" "0,1" newline bitfld.long 0x2C 25. "NL2OE,Non LPDDR2 output enable" "0,1" bitfld.long 0x2C 24. "NL2PD,Non LPDDR2 power down" "0,1" newline bitfld.long 0x2C 20. "ODTPDD,ODT power down driver" "0,1" bitfld.long 0x2C 16. "CKEPDD,CKE power down driver" "0,1" newline sif (cpuis("STM32MP13*")) bitfld.long 0x2C 12. "FXDLAT,Fixed latency" "0: Disable fixed read latency,1: Enable fixed read latency" bitfld.long 0x2C 11. "NOBUB,No bubble" "0: Bubbles are allowed during reads,1: Bubbles are not allowed during reads" newline endif sif (cpuis("STM32MP151*")) bitfld.long 0x2C 12. "FXDLAT,FXDLAT" "0,1" bitfld.long 0x2C 11. "NOBUB,NOBUB" "0,1" newline endif sif (cpuis("STM32MP153*")) bitfld.long 0x2C 12. "FXDLAT,FXDLAT" "0,1" bitfld.long 0x2C 11. "NOBUB,NOBUB" "0,1" newline endif sif (cpuis("STM32MP157*")) bitfld.long 0x2C 12. "FXDLAT,FXDLAT" "0,1" bitfld.long 0x2C 11. "NOBUB,NOBUB" "0,1" newline endif bitfld.long 0x2C 8.--10. "DQSGE,DQS gate early" "0,1,2,3,4,5,6,7" bitfld.long 0x2C 5.--7. "DQSGX,DQS gate extension" "0,1,2,3,4,5,6,7" newline bitfld.long 0x2C 4. "LPDLLPD,Low power DLL power down" "0,1" bitfld.long 0x2C 3. "LPIOPD,Low power I/O power down" "0,1" newline bitfld.long 0x2C 2. "ZUEN,zcal on DFI update request" "0,1" bitfld.long 0x2C 1. "BDISEN,Byte disable enable" "0,1" newline bitfld.long 0x2C 0. "PUREN,PHY update request enable" "0,1" line.long 0x30 "DDRPHYC_DCR,DDRPHYC DC register" bitfld.long 0x30 31. "TPD,Test power down (N/A LPDDR only)" "0,1" bitfld.long 0x30 30. "RDIMM,Registered DIMM" "0,1" newline bitfld.long 0x30 29. "UDIMM,Unbuffered DIMM" "0,1" bitfld.long 0x30 28. "DDR2T,2T timing" "0,1" newline bitfld.long 0x30 27. "NOSRA,No simultaneous rank access" "0,1" sif (cpuis("STM32MP13*")) bitfld.long 0x30 8.--9. "DDRTYPE,DDR type (LPDDR2 S4)" "0: LPDDR2-S4,1: LPDDR2-S2,?,?" newline bitfld.long 0x30 7. "MPRDQ,MPR DQ" "0: Primary DQ drives out the data from MPR..,1: Primary DQ and non-primary DQs all drive the.." bitfld.long 0x30 0.--2. "DDRMD,SDRAM DDR mode" "?,?,?,3: DDR3,4: LPDDR2 (Mobile DDR2),5: LPDDR3 (Mobile DDR3),?,?" newline endif sif (cpuis("STM32MP151*")) bitfld.long 0x30 8.--9. "DDRTYPE,DDRTYPE" "0,1,2,3" bitfld.long 0x30 7. "MPRDQ,MPRDQ" "0,1" newline endif sif (cpuis("STM32MP153*")) bitfld.long 0x30 8.--9. "DDRTYPE,DDRTYPE" "0,1,2,3" bitfld.long 0x30 7. "MPRDQ,MPRDQ" "0,1" newline endif sif (cpuis("STM32MP157*")) bitfld.long 0x30 8.--9. "DDRTYPE,DDRTYPE" "0,1,2,3" bitfld.long 0x30 7. "MPRDQ,MPRDQ" "0,1" newline endif bitfld.long 0x30 4.--6. "PDQ,Primary DQ(DDR3 Only)" "0,1,2,3,4,5,6,7" bitfld.long 0x30 3. "DDR8BNK,DDR 8 banks" "0,1" newline sif (cpuis("STM32MP153*")) bitfld.long 0x30 0.--2. "DDRMD,DDRMD" "0,1,2,3,4,5,6,7" endif sif (cpuis("STM32MP157*")) bitfld.long 0x30 0.--2. "DDRMD,DDRMD" "0,1,2,3,4,5,6,7" endif line.long 0x34 "DDRPHYC_DTPR0,DDRPHYC DTP register 0" sif (cpuis("STM32MP13*")) bitfld.long 0x34 31. "TCCD,tCCDRead to read and write to write command delay" "0: BL/2 for DDR2 and 4 for DDR3,1: BL/2 + 1 for DDR2 and 5 for DDR3" endif sif (cpuis("STM32MP151*")) bitfld.long 0x34 31. "TCCD,TCCD" "0,1" newline endif sif (cpuis("STM32MP153*")) bitfld.long 0x34 31. "TCCD,TCCD" "0,1" endif sif (cpuis("STM32MP157*")) bitfld.long 0x34 31. "TCCD,TCCD" "0,1" newline endif hexmask.long.byte 0x34 25.--30. 1. "TRC,tRC" hexmask.long.byte 0x34 21.--24. 1. "TRRD,tRRD" newline hexmask.long.byte 0x34 16.--20. 1. "TRAS,tRAS" hexmask.long.byte 0x34 12.--15. 1. "TRCD,tRCD" newline hexmask.long.byte 0x34 8.--11. 1. "TRP,tRP" bitfld.long 0x34 5.--7. "TWTR,tWTR" "0,1,2,3,4,5,6,7" newline bitfld.long 0x34 2.--4. "TRTP,tRTP" "0,1,2,3,4,5,6,7" bitfld.long 0x34 0.--1. "TMRD,tMRD" "0,1,2,3" line.long 0x38 "DDRPHYC_DTPR1,DDRPHYC DTP register 1" bitfld.long 0x38 27.--29. "TDQSCKMAX,tDQSCKmax" "0,1,2,3,4,5,6,7" bitfld.long 0x38 24.--26. "TDQSCKMIN,tDQSCKmin" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x38 16.--23. 1. "TRFC,tRFC" sif (cpuis("STM32MP13*")) bitfld.long 0x38 11. "TRTODT,tRTODT" "0: ODT may be turned on immediately after read..,1: ODT may not be turned on until one clock after.." newline bitfld.long 0x38 9.--10. "TMOD,tMOD" "0: 12,1: 13,2: 14,3: 15" bitfld.long 0x38 2. "TRTW,tRTW" "0: standard bus turn around delay,1: add 1 clock to standard bus turn around delay" newline bitfld.long 0x38 0.--1. "TAOND,tAOND/tAOFD" "0: 2/2.5,1: 3/3.5,2: 4/4.5,3: 5/5.5" endif sif (cpuis("STM32MP151*")) bitfld.long 0x38 11. "TRTODT,TRTODT" "0,1" newline bitfld.long 0x38 9.--10. "TMOD,TMOD" "0,1,2,3" endif sif (cpuis("STM32MP153*")) bitfld.long 0x38 11. "TRTODT,TRTODT" "0,1" newline bitfld.long 0x38 9.--10. "TMOD,TMOD" "0,1,2,3" endif sif (cpuis("STM32MP157*")) bitfld.long 0x38 11. "TRTODT,TRTODT" "0,1" newline bitfld.long 0x38 9.--10. "TMOD,TMOD" "0,1,2,3" endif hexmask.long.byte 0x38 3.--8. 1. "TFAW,tFAW" newline sif (cpuis("STM32MP151*")) bitfld.long 0x38 2. "TRTW,TRTW" "0,1" endif sif (cpuis("STM32MP153*")) bitfld.long 0x38 2. "TRTW,TRTW" "0,1" newline bitfld.long 0x38 0.--1. "TAOND,TAOND" "0,1,2,3" endif sif (cpuis("STM32MP157*")) bitfld.long 0x38 2. "TRTW,TRTW" "0,1" newline bitfld.long 0x38 0.--1. "TAOND,TAOND" "0,1,2,3" endif line.long 0x3C "DDRPHYC_DTPR2,DDRPHYC DTP register 2" hexmask.long.word 0x3C 19.--28. 1. "TDLLK,tDLLK" hexmask.long.byte 0x3C 15.--18. 1. "TCKE,tCKE" newline hexmask.long.byte 0x3C 10.--14. 1. "TXP,tXP" hexmask.long.word 0x3C 0.--9. 1. "TXS,tXS" group.word 0x40++0x1 line.word 0x0 "DDRPHYC_DDR3_MR0,DDRPHYC MR0 register for DDR3" bitfld.word 0x0 13.--15. "RSVD,JEDEC reserved." "0,1,2,3,4,5,6,7" sif (cpuis("STM32MP13*")) bitfld.word 0x0 12. "PD,Power-down control" "0: Slow exit (DLL off),1: Fast exit (DLL on)" newline bitfld.word 0x0 9.--11. "WR,Write recovery" "?,1: 5,2: 6,3: 7,4: 8,5: 10,6: 12,?" bitfld.word 0x0 0.--1. "BL,Burst length" "0: 8 (Fixed),1: 4 or 8 (On the fly),2: 4 (Fixed),?" newline endif sif (cpuis("STM32MP151*")) bitfld.word 0x0 12. "PD,PD" "0,1" bitfld.word 0x0 9.--11. "WR,WR" "0,1,2,3,4,5,6,7" newline endif sif (cpuis("STM32MP153*")) bitfld.word 0x0 12. "PD,PD" "0,1" bitfld.word 0x0 9.--11. "WR,WR" "0,1,2,3,4,5,6,7" newline endif sif (cpuis("STM32MP157*")) bitfld.word 0x0 12. "PD,PD" "0,1" bitfld.word 0x0 9.--11. "WR,WR" "0,1,2,3,4,5,6,7" newline endif bitfld.word 0x0 8. "DR,DLL reset (autoclear)" "0,1" bitfld.word 0x0 7. "TM,Operating mode" "0,1" newline bitfld.word 0x0 4.--6. "CL,CAS latency" "0,1,2,3,4,5,6,7" bitfld.word 0x0 3. "BT,Burst type" "0,1" newline bitfld.word 0x0 2. "CL0,CAS latency" "0,1" sif (cpuis("STM32MP153*")) bitfld.word 0x0 0.--1. "BL,BL" "0,1,2,3" newline endif sif (cpuis("STM32MP157*")) bitfld.word 0x0 0.--1. "BL,BL" "0,1,2,3" endif group.word 0x44++0x1 line.word 0x0 "DDRPHYC_DDR3_MR1,DDRPHYC MR1 register for DDR3" sif (cpuis("STM32MP13*")) bitfld.word 0x0 12. "QOFF,Output enable/disable" "0: all outputs function as normal,1: all SDRAM outputs are disabled removing output.." bitfld.word 0x0 5. "DIC1,Output driver impedance control" "0: RZQ/6,1: RZQ/7" newline bitfld.word 0x0 3.--4. "AL,Posted CAS Additive Latency:" "0: 0 (AL disabled),1: CL - 1,2: CL - 2,?" bitfld.word 0x0 1. "DIC0,Output driver impedance control" "0: RZQ/6,1: RZQ/7" newline endif sif (cpuis("STM32MP151*")) bitfld.word 0x0 12. "QOFF,QOFF" "0,1" endif sif (cpuis("STM32MP153*")) bitfld.word 0x0 12. "QOFF,QOFF" "0,1" newline endif sif (cpuis("STM32MP157*")) bitfld.word 0x0 12. "QOFF,QOFF" "0,1" endif bitfld.word 0x0 11. "TDQS,Termination data strobe" "0,1" newline bitfld.word 0x0 9. "RTT2,On die termination" "0,1" bitfld.word 0x0 7. "LEVEL,Write leveling enable (N/A)" "0,1" newline bitfld.word 0x0 6. "RTT1,On die termination" "0,1" sif (cpuis("STM32MP151*")) bitfld.word 0x0 5. "DIC1,DIC1" "0,1" newline bitfld.word 0x0 3.--4. "AL,AL" "0,1,2,3" endif sif (cpuis("STM32MP153*")) bitfld.word 0x0 5. "DIC1,DIC1" "0,1" newline bitfld.word 0x0 3.--4. "AL,AL" "0,1,2,3" endif sif (cpuis("STM32MP157*")) bitfld.word 0x0 5. "DIC1,DIC1" "0,1" newline bitfld.word 0x0 3.--4. "AL,AL" "0,1,2,3" endif bitfld.word 0x0 2. "RTT0,On die termination" "0,1" newline sif (cpuis("STM32MP151*")) bitfld.word 0x0 1. "DIC0,DIC0" "0,1" endif sif (cpuis("STM32MP153*")) bitfld.word 0x0 1. "DIC0,DIC0" "0,1" newline endif sif (cpuis("STM32MP157*")) bitfld.word 0x0 1. "DIC0,DIC0" "0,1" endif bitfld.word 0x0 0. "DE,DLL enable/disable" "0,1" group.word 0x48++0x1 line.word 0x0 "DDRPHYC_DDR3_MR2,DDRPHYC MR2 register for DDR3" sif (cpuis("STM32MP13*")) bitfld.word 0x0 9.--10. "RTTWR,Dynamic ODT" "0: Dynamic ODT off,1: RZQ/4,2: RZQ/2,?" bitfld.word 0x0 3.--5. "CWL,CAS write latency" "0: 5 (tCK = 2.5ns),1: 6 (2.5ns > tCK = 1.875ns),2: 7 (1.875ns > tCK = 1.5ns),3: 8 (1.5ns > tCK = 1.25ns),?,?,?,?" newline bitfld.word 0x0 0.--2. "PASR,Partial array self-refresh" "0: Full Array,1: Half Array (BA[2:0] = 000 001 010 & 011),2: Quarter Array (BA[2:0] = 000 001),3: 1/8 Array (BA[2:0] = 000),4: 3/4 Array (BA[2:0] = 010 011 100 101 110 & 111),5: Half Array (BA[2:0] = 100 101 110 & 111),6: Quarter Array (BA[2:0] = 110 & 111),7: 1/8 Array (BA[2:0] 111)" endif sif (cpuis("STM32MP151*")) bitfld.word 0x0 9.--10. "RTTWR,RTTWR" "0,1,2,3" newline endif sif (cpuis("STM32MP153*")) bitfld.word 0x0 9.--10. "RTTWR,RTTWR" "0,1,2,3" endif sif (cpuis("STM32MP157*")) bitfld.word 0x0 9.--10. "RTTWR,RTTWR" "0,1,2,3" newline endif bitfld.word 0x0 7. "SRT,Self-refresh temperature range" "0,1" bitfld.word 0x0 6. "ASR,Auto self-refresh" "0,1" newline sif (cpuis("STM32MP151*")) bitfld.word 0x0 3.--5. "CWL,CWL" "0,1,2,3,4,5,6,7" endif sif (cpuis("STM32MP153*")) bitfld.word 0x0 3.--5. "CWL,CWL" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 0.--2. "PASR,PASR" "0,1,2,3,4,5,6,7" endif sif (cpuis("STM32MP157*")) bitfld.word 0x0 3.--5. "CWL,CWL" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 0.--2. "PASR,PASR" "0,1,2,3,4,5,6,7" endif group.byte 0x4C++0x0 line.byte 0x0 "DDRPHYC_DDR3_MR3,DDRPHYC MR3 register for DDR3" bitfld.byte 0x0 2. "MPR,Multi-purpose register enable" "0,1" sif (cpuis("STM32MP13*")) bitfld.byte 0x0 0.--1. "MPRLOC,Multi-purpose register (MPR) location" "0: Predefined pattern for system calibration,?,?,?" newline endif sif (cpuis("STM32MP153*")) bitfld.byte 0x0 0.--1. "MPRLOC,MPRLOC" "0,1,2,3" endif sif (cpuis("STM32MP157*")) bitfld.byte 0x0 0.--1. "MPRLOC,MPRLOC" "0,1,2,3" endif group.long 0x50++0xF line.long 0x0 "DDRPHYC_ODTCR,DDRPHYC ODTC register" bitfld.long 0x0 16. "WRODT,Specifies whether ODT should be enabled ('1’) or disabled ('0’) on write" "0,1" bitfld.long 0x0 0. "RDODT,Specifies whether ODT should be enabled ('1’) or disabled ('0’) on read" "0,1" line.long 0x4 "DDRPHYC_DTAR,DDRPHYC DTA register" bitfld.long 0x4 31. "DTMPR,Data training using MPR (DDR3 Only):" "0,1" bitfld.long 0x4 28.--30. "DTBANK,Data training bank address:" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x4 12.--27. 1. "DTROW,Data training row address:" hexmask.long.word 0x4 0.--11. 1. "DTCOL,Data training column address:" line.long 0x8 "DDRPHYC_DTDR0,DDRPHYC DTD register 0" hexmask.long.byte 0x8 24.--31. 1. "DTBYTE3,Data training data" hexmask.long.byte 0x8 16.--23. 1. "DTBYTE2,Data Training Data" newline hexmask.long.byte 0x8 8.--15. 1. "DTBYTE1,Data Training Data" hexmask.long.byte 0x8 0.--7. 1. "DTBYTE0,Data Training Data" line.long 0xC "DDRPHYC_DTDR1,DDRPHYC DTD register 1" hexmask.long.byte 0xC 24.--31. 1. "DTBYTE7,Data training data:" hexmask.long.byte 0xC 16.--23. 1. "DTBYTE6,Data Training Data" newline hexmask.long.byte 0xC 8.--15. 1. "DTBYTE5,Data Training Data" hexmask.long.byte 0xC 0.--7. 1. "DTBYTE4,Data Training Data" group.long 0x178++0xB line.long 0x0 "DDRPHYC_GPR0,DDRPHYC general purpose register 0" hexmask.long 0x0 0.--31. 1. "GPR0,General purpose register 0 bits" line.long 0x4 "DDRPHYC_GPR1,DDRPHYC general purpose register 1" hexmask.long 0x4 0.--31. 1. "GPR1,General purpose register 1 bits" line.long 0x8 "DDRPHYC_ZQ0CR0,DDRPHYC ZQ0C register 0" bitfld.long 0x8 31. "ZQPD,ZCAL power down" "0,1" bitfld.long 0x8 30. "ZCAL,ZCAL trigger" "0,1" newline bitfld.long 0x8 29. "ZCALBYP,Impedance calibration bypass" "0,1" bitfld.long 0x8 28. "ZDEN,Impedance override enable" "0,1" newline hexmask.long.tbyte 0x8 0.--19. 1. "ZDATA,Impedance override" group.byte 0x184++0x0 line.byte 0x0 "DDRPHYC_ZQ0CR1,DDRPHYC ZQ0CR1 register" hexmask.byte 0x0 0.--7. 1. "ZPROG,Impedance divide ratio to ext R" group.long 0x188++0x3 line.long 0x0 "DDRPHYC_ZQ0SR0,DDRPHYC ZQ0S register 0" sif (cpuis("STM32MP13*")) rbitfld.long 0x0 31. "ZDONE,Impedance calibration done" "0,1" rbitfld.long 0x0 30. "ZERR,Impedance calibration error" "0,1" newline hexmask.long.tbyte 0x0 0.--19. 1. "ZCTRL,Impedance control" endif sif (cpuis("STM32MP151*")) bitfld.long 0x0 31. "ZDONE,ZDONE" "0,1" newline bitfld.long 0x0 30. "ZERR,ZERR" "0,1" endif sif (cpuis("STM32MP153*")) bitfld.long 0x0 31. "ZDONE,ZDONE" "0,1" newline bitfld.long 0x0 30. "ZERR,ZERR" "0,1" endif sif (cpuis("STM32MP157*")) bitfld.long 0x0 31. "ZDONE,ZDONE" "0,1" newline bitfld.long 0x0 30. "ZERR,ZERR" "0,1" endif sif (cpuis("STM32MP151*")) hexmask.long.tbyte 0x0 0.--19. 1. "ZCTRL,ZCTRL" newline endif sif (cpuis("STM32MP153*")) hexmask.long.tbyte 0x0 0.--19. 1. "ZCTRL,ZCTRL" endif sif (cpuis("STM32MP157*")) hexmask.long.tbyte 0x0 0.--19. 1. "ZCTRL,ZCTRL" endif rgroup.byte 0x18C++0x0 line.byte 0x0 "DDRPHYC_ZQ0SR1,DDRPHYC ZQ0S register 1" sif (cpuis("STM32MP13*")) bitfld.byte 0x0 6.--7. "OPU,opu calibration status" "0: Completed with no errors,1: Overflow error,2: Underflow error,3: Calibration in progress" bitfld.byte 0x0 4.--5. "OPD,opd calibration status" "0: Completed with no errors,1: Overflow error,2: Underflow error,3: Calibration in progress" newline bitfld.byte 0x0 2.--3. "ZPU,zpu calibration status" "0: Completed with no errors,1: Overflow error,2: Underflow error,3: Calibration in progress" bitfld.byte 0x0 0.--1. "ZPD,zpd calibration status" "0: Completed with no errors,1: Overflow error,2: Underflow error,3: Calibration in progress" newline endif sif (cpuis("STM32MP151*")) bitfld.byte 0x0 6.--7. "OPU,OPU" "0,1,2,3" bitfld.byte 0x0 4.--5. "OPD,OPD" "0,1,2,3" newline bitfld.byte 0x0 2.--3. "ZPU,ZPU" "0,1,2,3" bitfld.byte 0x0 0.--1. "ZPD,ZPD" "0,1,2,3" newline endif sif (cpuis("STM32MP153*")) bitfld.byte 0x0 6.--7. "OPU,OPU" "0,1,2,3" bitfld.byte 0x0 4.--5. "OPD,OPD" "0,1,2,3" newline bitfld.byte 0x0 2.--3. "ZPU,ZPU" "0,1,2,3" bitfld.byte 0x0 0.--1. "ZPD,ZPD" "0,1,2,3" newline endif sif (cpuis("STM32MP157*")) bitfld.byte 0x0 6.--7. "OPU,OPU" "0,1,2,3" bitfld.byte 0x0 4.--5. "OPD,OPD" "0,1,2,3" newline bitfld.byte 0x0 2.--3. "ZPU,ZPU" "0,1,2,3" bitfld.byte 0x0 0.--1. "ZPD,ZPD" "0,1,2,3" endif group.long 0x1C0++0x3 line.long 0x0 "DDRPHYC_DX0GCR,DDRPHYC byte lane 0 GC register" sif (cpuis("STM32MP13*")) bitfld.long 0x0 14.--16. "R0RVSL,Read valid system latency in steps" "0: read valid system latency = ideal placement - 3,1: read valid system latency = ideal placement - 2,2: read valid system latency = ideal placement - 1,3: read valid system latency = ideal placement,4: read valid system latency = ideal placement + 1,5: read valid system latency = ideal placement + 2,6: read valid system latency = ideal placement + 3,?" bitfld.long 0x0 13. "RTTOAL,RTT ON additive latency" "0: ODT control is set to DQSODT/DQODT almost two..,1: ODT control is set to DQSODT/DQODT almost one.." newline bitfld.long 0x0 7.--8. "DSEN,Write DQS enable" "0: DQS disabled (Driven to constant 0),1: DQS toggling with normal polarity (This should..,2: DQS toggling with inverted polarity,3: DQS disabled (Driven to constant 1)" endif sif (cpuis("STM32MP151*")) bitfld.long 0x0 14.--16. "R0RVSL,R0RVSL" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 13. "RTTOAL,RTTOAL" "0,1" endif sif (cpuis("STM32MP153*")) bitfld.long 0x0 14.--16. "R0RVSL,R0RVSL" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 13. "RTTOAL,RTTOAL" "0,1" endif sif (cpuis("STM32MP157*")) bitfld.long 0x0 14.--16. "R0RVSL,R0RVSL" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 13. "RTTOAL,RTTOAL" "0,1" endif bitfld.long 0x0 11.--12. "RTTOH,RTT output hold" "0,1,2,3" newline bitfld.long 0x0 10. "DQRTT,DQ dynamic RTT control" "0,1" bitfld.long 0x0 9. "DQSRTT,DQS dynamic RTT control" "0,1" newline sif (cpuis("STM32MP151*")) bitfld.long 0x0 7.--8. "DSEN,DSEN" "0,1,2,3" endif sif (cpuis("STM32MP153*")) bitfld.long 0x0 7.--8. "DSEN,DSEN" "0,1,2,3" newline endif sif (cpuis("STM32MP157*")) bitfld.long 0x0 7.--8. "DSEN,DSEN" "0,1,2,3" endif bitfld.long 0x0 6. "DQSRPD,DQSR power-down" "0,1" newline bitfld.long 0x0 5. "DXPDR,Data power-down receiver" "0,1" bitfld.long 0x0 4. "DXPDD,Data power-down driver" "0,1" newline bitfld.long 0x0 3. "DXIOM,Data I/O mode" "0,1" bitfld.long 0x0 2. "DQODT,DQ ODT enable" "0,1" newline bitfld.long 0x0 1. "DQSODT,DQS ODT enable" "0,1" bitfld.long 0x0 0. "DXEN,DATA byte enable" "0,1" group.word 0x1C4++0x1 line.word 0x0 "DDRPHYC_DX0GSR0,DDRPHYC byte lane 0 GS register 0" sif (cpuis("STM32MP13*")) rbitfld.word 0x0 13.--15. "DTPASS,DQS training pass count" "0,1,2,3,4,5,6,7" rbitfld.word 0x0 8. "DTIERR,DQS gate training intermittent error" "0,1" newline rbitfld.word 0x0 4. "DTERR,DQS gate training error" "0,1" rbitfld.word 0x0 0. "DTDONE,Data training done" "0,1" newline endif sif (cpuis("STM32MP151*")) bitfld.word 0x0 13.--15. "DTPASS,DTPASS" "0,1,2,3,4,5,6,7" endif sif (cpuis("STM32MP153*")) bitfld.word 0x0 13.--15. "DTPASS,DTPASS" "0,1,2,3,4,5,6,7" newline endif sif (cpuis("STM32MP157*")) bitfld.word 0x0 13.--15. "DTPASS,DTPASS" "0,1,2,3,4,5,6,7" endif sif (cpuis("STM32MP151*")) bitfld.word 0x0 8. "DTIERR,DTIERR" "0,1" newline endif sif (cpuis("STM32MP153*")) bitfld.word 0x0 8. "DTIERR,DTIERR" "0,1" endif sif (cpuis("STM32MP157*")) bitfld.word 0x0 8. "DTIERR,DTIERR" "0,1" newline endif sif (cpuis("STM32MP151*")) bitfld.word 0x0 4. "DTERR,DTERR" "0,1" endif sif (cpuis("STM32MP153*")) bitfld.word 0x0 4. "DTERR,DTERR" "0,1" newline endif sif (cpuis("STM32MP157*")) bitfld.word 0x0 4. "DTERR,DTERR" "0,1" endif sif (cpuis("STM32MP151*")) bitfld.word 0x0 0. "DTDONE,DTDONE" "0,1" newline endif sif (cpuis("STM32MP153*")) bitfld.word 0x0 0. "DTDONE,DTDONE" "0,1" endif sif (cpuis("STM32MP157*")) bitfld.word 0x0 0. "DTDONE,DTDONE" "0,1" endif group.long 0x1C8++0xF line.long 0x0 "DDRPHYC_DX0GSR1,DDRPHYC byte lane 0 GS register 1" sif (cpuis("STM32MP13*")) rbitfld.long 0x0 20.--22. "RVPASS,Read valid training pass count" "0,1,2,3,4,5,6,7" rbitfld.long 0x0 16. "RVIERR,RV intermittent error for rank" "0,1" newline rbitfld.long 0x0 12. "RVERR,RV training error" "0,1" rbitfld.long 0x0 4.--5. "DQSDFT,DQS drift value" "0: No drift,1: 90° drift,2: 180° drift,3: 270° drift or more" newline rbitfld.long 0x0 0. "DFTERR,DQS drift error" "0,1" endif sif (cpuis("STM32MP151*")) bitfld.long 0x0 20.--22. "RVPASS,RVPASS" "0,1,2,3,4,5,6,7" newline endif sif (cpuis("STM32MP153*")) bitfld.long 0x0 20.--22. "RVPASS,RVPASS" "0,1,2,3,4,5,6,7" endif sif (cpuis("STM32MP157*")) bitfld.long 0x0 20.--22. "RVPASS,RVPASS" "0,1,2,3,4,5,6,7" newline endif sif (cpuis("STM32MP151*")) bitfld.long 0x0 16. "RVIERR,RVIERR" "0,1" endif sif (cpuis("STM32MP153*")) bitfld.long 0x0 16. "RVIERR,RVIERR" "0,1" newline endif sif (cpuis("STM32MP157*")) bitfld.long 0x0 16. "RVIERR,RVIERR" "0,1" endif sif (cpuis("STM32MP151*")) bitfld.long 0x0 12. "RVERR,RVERR" "0,1" newline endif sif (cpuis("STM32MP153*")) bitfld.long 0x0 12. "RVERR,RVERR" "0,1" endif sif (cpuis("STM32MP157*")) bitfld.long 0x0 12. "RVERR,RVERR" "0,1" newline endif sif (cpuis("STM32MP151*")) bitfld.long 0x0 4.--5. "DQSDFT,DQSDFT" "0,1,2,3" endif sif (cpuis("STM32MP153*")) bitfld.long 0x0 4.--5. "DQSDFT,DQSDFT" "0,1,2,3" newline endif sif (cpuis("STM32MP157*")) bitfld.long 0x0 4.--5. "DQSDFT,DQSDFT" "0,1,2,3" endif sif (cpuis("STM32MP151*")) bitfld.long 0x0 0. "DFTERR,DFTERR" "0,1" newline endif sif (cpuis("STM32MP153*")) bitfld.long 0x0 0. "DFTERR,DFTERR" "0,1" endif sif (cpuis("STM32MP157*")) bitfld.long 0x0 0. "DFTERR,DFTERR" "0,1" endif line.long 0x4 "DDRPHYC_DX0DLLCR,DDRPHYC byte lane 0 DLLC register" bitfld.long 0x4 31. "DLLDIS,DLL bypass" "0,1" bitfld.long 0x4 30. "DLLSRST,DLL reset" "0,1" newline bitfld.long 0x4 19. "SDLBMODE,Bypass slave DLL during loopback" "0,1" bitfld.long 0x4 18. "ATESTEN,Enable path to pin 'ATO'" "0,1" newline sif (cpuis("STM32MP13*")) hexmask.long.byte 0x4 14.--17. 1. "SDPHASE,Slave DLL phase" bitfld.long 0x4 12.--13. "SSTART,Slave DLL autostart" "?,?,2: The automatic startup of the slave DLL is..,3: The automatic startup of the slave DLL is.." newline bitfld.long 0x4 9.--11. "MFWDLY,Master DLL feed-forward trim" "0: minimum delay,?,?,?,?,?,?,7: maximum delay" bitfld.long 0x4 6.--8. "MFBDLY,Master DLL feed-back trim" "0: minimum delay,?,?,?,?,?,?,7: maximum delay" newline bitfld.long 0x4 3.--5. "SFWDLY,Slave DLL feed-forward trim" "0: minimum delay,?,?,?,?,?,?,7: maximum delay" bitfld.long 0x4 0.--2. "SFBDLY,Slave DLL feed-back trim" "0: minimum delay,?,?,?,?,?,?,7: maximum delay" newline endif sif (cpuis("STM32MP151*")) hexmask.long.byte 0x4 14.--17. 1. "SDPHASE,SDPHASE" bitfld.long 0x4 12.--13. "SSTART,SSTART" "0,1,2,3" newline bitfld.long 0x4 9.--11. "MFWDLY,MFWDLY" "0,1,2,3,4,5,6,7" bitfld.long 0x4 6.--8. "MFBDLY,MFBDLY" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 3.--5. "SFWDLY,SFWDLY" "0,1,2,3,4,5,6,7" endif sif (cpuis("STM32MP153*")) hexmask.long.byte 0x4 14.--17. 1. "SDPHASE,SDPHASE" newline bitfld.long 0x4 12.--13. "SSTART,SSTART" "0,1,2,3" bitfld.long 0x4 9.--11. "MFWDLY,MFWDLY" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 6.--8. "MFBDLY,MFBDLY" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3.--5. "SFWDLY,SFWDLY" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 0.--2. "SFBDLY,SFBDLY" "0,1,2,3,4,5,6,7" endif sif (cpuis("STM32MP157*")) hexmask.long.byte 0x4 14.--17. 1. "SDPHASE,SDPHASE" newline bitfld.long 0x4 12.--13. "SSTART,SSTART" "0,1,2,3" bitfld.long 0x4 9.--11. "MFWDLY,MFWDLY" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 6.--8. "MFBDLY,MFBDLY" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3.--5. "SFWDLY,SFWDLY" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 0.--2. "SFBDLY,SFBDLY" "0,1,2,3,4,5,6,7" endif line.long 0x8 "DDRPHYC_DX0DQTR,DDRPHYC byte lane 0 DQT register" sif (cpuis("STM32MP13*")) hexmask.long.byte 0x8 28.--31. 1. "DQDLY7,DQ delay for bit 7" endif sif (cpuis("STM32MP151*")) hexmask.long.byte 0x8 28.--31. 1. "DQDLY7,DQDLY7" newline endif sif (cpuis("STM32MP153*")) hexmask.long.byte 0x8 28.--31. 1. "DQDLY7,DQDLY7" endif sif (cpuis("STM32MP157*")) hexmask.long.byte 0x8 28.--31. 1. "DQDLY7,DQDLY7" newline endif hexmask.long.byte 0x8 24.--27. 1. "DQDLY6,DQ delay for bit 6" hexmask.long.byte 0x8 20.--23. 1. "DQDLY5,DQ delay for bit 5" newline hexmask.long.byte 0x8 16.--19. 1. "DQDLY4,DQ delay for bit 4" hexmask.long.byte 0x8 12.--15. 1. "DQDLY3,DQ delay for bit 3" newline hexmask.long.byte 0x8 8.--11. 1. "DQDLY2,DQ delay for bit 2" hexmask.long.byte 0x8 4.--7. 1. "DQDLY1,DQ delay for bit 1" newline hexmask.long.byte 0x8 0.--3. 1. "DQDLY0,DQ delay for bit 0" line.long 0xC "DDRPHYC_DX0DQSTR,DDRPHYC byte lane 0 DQST register" sif (cpuis("STM32MP13*")) hexmask.long.byte 0xC 26.--29. 1. "DMDLY,DM delay" bitfld.long 0xC 23.--25. "DQSNDLY,DQS# delay" "0: nominal delay - 3 steps,1: nominal delay - 2 steps,2: nominal delay - 1 step,3: nominal delay,4: nominal delay + 1 step,5: nominal delay + 2 steps,6: nominal delay + 3 steps,7: nominal delay + 4 steps" newline bitfld.long 0xC 20.--22. "DQSDLY,DQS delay" "0: nominal delay - 3 steps,1: nominal delay - 2 steps,2: nominal delay - 1 step,3: nominal delay,4: nominal delay + 1 step,5: nominal delay + 2 steps,6: nominal delay + 3 steps,7: nominal delay + 4 steps" bitfld.long 0xC 12.--13. "R0DGPS,Rank 0 DQS gating phase select" "0: 180 clock (clk180),1: 270 clock (clk270),2: 360 clock (clk0),3: 450 clock (next clk90)" newline bitfld.long 0xC 0.--2. "R0DGSL,Rank 0 DQS gating system latency" "0: No extra clock cycles,1: 1 extra clock cycle,2: 2 extra clock cycles,3: 3 extra clock cycles,4: 4 extra clock cycles,5: 5 extra clock cycles,?,?" endif sif (cpuis("STM32MP151*")) hexmask.long.byte 0xC 26.--29. 1. "DMDLY,DMDLY" newline bitfld.long 0xC 23.--25. "DQSNDLY,DQSNDLY" "0,1,2,3,4,5,6,7" bitfld.long 0xC 20.--22. "DQSDLY,DQSDLY" "0,1,2,3,4,5,6,7" newline endif sif (cpuis("STM32MP153*")) hexmask.long.byte 0xC 26.--29. 1. "DMDLY,DMDLY" bitfld.long 0xC 23.--25. "DQSNDLY,DQSNDLY" "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 20.--22. "DQSDLY,DQSDLY" "0,1,2,3,4,5,6,7" endif sif (cpuis("STM32MP157*")) hexmask.long.byte 0xC 26.--29. 1. "DMDLY,DMDLY" newline bitfld.long 0xC 23.--25. "DQSNDLY,DQSNDLY" "0,1,2,3,4,5,6,7" bitfld.long 0xC 20.--22. "DQSDLY,DQSDLY" "0,1,2,3,4,5,6,7" newline endif sif (cpuis("STM32MP151*")) bitfld.long 0xC 12.--13. "R0DGPS,R0DGPS" "0,1,2,3" endif sif (cpuis("STM32MP153*")) bitfld.long 0xC 12.--13. "R0DGPS,R0DGPS" "0,1,2,3" newline endif sif (cpuis("STM32MP157*")) bitfld.long 0xC 12.--13. "R0DGPS,R0DGPS" "0,1,2,3" endif sif (cpuis("STM32MP153*")) bitfld.long 0xC 0.--2. "R0DGSL,R0DGSL" "0,1,2,3,4,5,6,7" newline endif sif (cpuis("STM32MP157*")) bitfld.long 0xC 0.--2. "R0DGSL,R0DGSL" "0,1,2,3,4,5,6,7" endif group.long 0x200++0x3 line.long 0x0 "DDRPHYC_DX1GCR,DDRPHYC byte lane 1 GC register" sif (cpuis("STM32MP13*")) bitfld.long 0x0 14.--16. "R0RVSL,Read valid system latency in steps" "0: read valid system latency = ideal placement - 3,1: read valid system latency = ideal placement - 2,2: read valid system latency = ideal placement - 1,3: read valid system latency = ideal placement,4: read valid system latency = ideal placement + 1,5: read valid system latency = ideal placement + 2,6: read valid system latency = ideal placement + 3,?" bitfld.long 0x0 13. "RTTOAL,RTT ON additive latency" "0: ODT control is set to DQSODT/DQODT almost two..,1: ODT control is set to DQSODT/DQODT almost one.." newline bitfld.long 0x0 7.--8. "DSEN,Write DQS enable" "0: DQS disabled (Driven to constant 0),1: DQS toggling with normal polarity (This should..,2: DQS toggling with inverted polarity,3: DQS disabled (Driven to constant 1)" endif sif (cpuis("STM32MP151*")) bitfld.long 0x0 14.--16. "R0RVSL,R0RVSL" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 13. "RTTOAL,RTTOAL" "0,1" endif sif (cpuis("STM32MP153*")) bitfld.long 0x0 14.--16. "R0RVSL,R0RVSL" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 13. "RTTOAL,RTTOAL" "0,1" endif sif (cpuis("STM32MP157*")) bitfld.long 0x0 14.--16. "R0RVSL,R0RVSL" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 13. "RTTOAL,RTTOAL" "0,1" endif bitfld.long 0x0 11.--12. "RTTOH,RTT output hold" "0,1,2,3" newline bitfld.long 0x0 10. "DQRTT,DQ dynamic RTT control" "0,1" bitfld.long 0x0 9. "DQSRTT,DQS dynamic RTT control" "0,1" newline sif (cpuis("STM32MP151*")) bitfld.long 0x0 7.--8. "DSEN,DSEN" "0,1,2,3" endif sif (cpuis("STM32MP153*")) bitfld.long 0x0 7.--8. "DSEN,DSEN" "0,1,2,3" newline endif sif (cpuis("STM32MP157*")) bitfld.long 0x0 7.--8. "DSEN,DSEN" "0,1,2,3" endif bitfld.long 0x0 6. "DQSRPD,DQSR power-down" "0,1" newline bitfld.long 0x0 5. "DXPDR,Data power-down receiver" "0,1" bitfld.long 0x0 4. "DXPDD,Data power-down driver" "0,1" newline bitfld.long 0x0 3. "DXIOM,Data I/O mode" "0,1" bitfld.long 0x0 2. "DQODT,DQ ODT enable" "0,1" newline bitfld.long 0x0 1. "DQSODT,DQS ODT enable" "0,1" bitfld.long 0x0 0. "DXEN,DATA byte enable" "0,1" group.word 0x204++0x1 line.word 0x0 "DDRPHYC_DX1GSR0,DDRPHYC byte lane 1 GS register 0" sif (cpuis("STM32MP13*")) rbitfld.word 0x0 13.--15. "DTPASS,DQS training pass count" "0,1,2,3,4,5,6,7" rbitfld.word 0x0 8. "DTIERR,DQS gate training intermittent error" "0,1" newline rbitfld.word 0x0 4. "DTERR,DQS gate training error" "0,1" rbitfld.word 0x0 0. "DTDONE,Data training done" "0,1" newline endif sif (cpuis("STM32MP151*")) bitfld.word 0x0 13.--15. "DTPASS,DTPASS" "0,1,2,3,4,5,6,7" endif sif (cpuis("STM32MP153*")) bitfld.word 0x0 13.--15. "DTPASS,DTPASS" "0,1,2,3,4,5,6,7" newline endif sif (cpuis("STM32MP157*")) bitfld.word 0x0 13.--15. "DTPASS,DTPASS" "0,1,2,3,4,5,6,7" endif sif (cpuis("STM32MP151*")) bitfld.word 0x0 8. "DTIERR,DTIERR" "0,1" newline endif sif (cpuis("STM32MP153*")) bitfld.word 0x0 8. "DTIERR,DTIERR" "0,1" endif sif (cpuis("STM32MP157*")) bitfld.word 0x0 8. "DTIERR,DTIERR" "0,1" newline endif sif (cpuis("STM32MP151*")) bitfld.word 0x0 4. "DTERR,DTERR" "0,1" endif sif (cpuis("STM32MP153*")) bitfld.word 0x0 4. "DTERR,DTERR" "0,1" newline endif sif (cpuis("STM32MP157*")) bitfld.word 0x0 4. "DTERR,DTERR" "0,1" endif sif (cpuis("STM32MP151*")) bitfld.word 0x0 0. "DTDONE,DTDONE" "0,1" newline endif sif (cpuis("STM32MP153*")) bitfld.word 0x0 0. "DTDONE,DTDONE" "0,1" endif sif (cpuis("STM32MP157*")) bitfld.word 0x0 0. "DTDONE,DTDONE" "0,1" endif group.long 0x208++0xF line.long 0x0 "DDRPHYC_DX1GSR1,DDRPHYC byte lane 1 GS register 1" sif (cpuis("STM32MP13*")) rbitfld.long 0x0 20.--22. "RVPASS,Read valid training pass count" "0,1,2,3,4,5,6,7" rbitfld.long 0x0 16. "RVIERR,RV intermittent error for rank" "0,1" newline rbitfld.long 0x0 12. "RVERR,RV training error" "0,1" rbitfld.long 0x0 4.--5. "DQSDFT,DQS drift value" "0: No drift,1: 90° drift,2: 180° drift,3: 270° drift or more" newline rbitfld.long 0x0 0. "DFTERR,DQS drift error" "0,1" endif sif (cpuis("STM32MP151*")) bitfld.long 0x0 20.--22. "RVPASS,RVPASS" "0,1,2,3,4,5,6,7" newline endif sif (cpuis("STM32MP153*")) bitfld.long 0x0 20.--22. "RVPASS,RVPASS" "0,1,2,3,4,5,6,7" endif sif (cpuis("STM32MP157*")) bitfld.long 0x0 20.--22. "RVPASS,RVPASS" "0,1,2,3,4,5,6,7" newline endif sif (cpuis("STM32MP151*")) bitfld.long 0x0 16. "RVIERR,RVIERR" "0,1" endif sif (cpuis("STM32MP153*")) bitfld.long 0x0 16. "RVIERR,RVIERR" "0,1" newline endif sif (cpuis("STM32MP157*")) bitfld.long 0x0 16. "RVIERR,RVIERR" "0,1" endif sif (cpuis("STM32MP151*")) bitfld.long 0x0 12. "RVERR,RVERR" "0,1" newline endif sif (cpuis("STM32MP153*")) bitfld.long 0x0 12. "RVERR,RVERR" "0,1" endif sif (cpuis("STM32MP157*")) bitfld.long 0x0 12. "RVERR,RVERR" "0,1" newline endif sif (cpuis("STM32MP151*")) bitfld.long 0x0 4.--5. "DQSDFT,DQSDFT" "0,1,2,3" endif sif (cpuis("STM32MP153*")) bitfld.long 0x0 4.--5. "DQSDFT,DQSDFT" "0,1,2,3" newline endif sif (cpuis("STM32MP157*")) bitfld.long 0x0 4.--5. "DQSDFT,DQSDFT" "0,1,2,3" endif sif (cpuis("STM32MP151*")) bitfld.long 0x0 0. "DFTERR,DFTERR" "0,1" newline endif sif (cpuis("STM32MP153*")) bitfld.long 0x0 0. "DFTERR,DFTERR" "0,1" endif sif (cpuis("STM32MP157*")) bitfld.long 0x0 0. "DFTERR,DFTERR" "0,1" endif line.long 0x4 "DDRPHYC_DX1DLLCR,DDRPHYC byte lane 1 DLLC register" bitfld.long 0x4 31. "DLLDIS,DLL bypass" "0,1" bitfld.long 0x4 30. "DLLSRST,DLL reset" "0,1" newline bitfld.long 0x4 19. "SDLBMODE,Bypass slave DLL during loopback" "0,1" bitfld.long 0x4 18. "ATESTEN,Enable path to pin 'ATO'" "0,1" newline sif (cpuis("STM32MP13*")) hexmask.long.byte 0x4 14.--17. 1. "SDPHASE,Slave DLL phase" bitfld.long 0x4 12.--13. "SSTART,Slave DLL autostart" "?,?,2: The automatic startup of the slave DLL is..,3: The automatic startup of the slave DLL is.." newline bitfld.long 0x4 9.--11. "MFWDLY,Master DLL feed-forward trim" "0: minimum delay,?,?,?,?,?,?,7: maximum delay" bitfld.long 0x4 6.--8. "MFBDLY,Master DLL feed-back trim" "0: minimum delay,?,?,?,?,?,?,7: maximum delay" newline bitfld.long 0x4 3.--5. "SFWDLY,Slave DLL feed-forward trim" "0: minimum delay,?,?,?,?,?,?,7: maximum delay" bitfld.long 0x4 0.--2. "SFBDLY,Slave DLL feed-back trim" "0: minimum delay,?,?,?,?,?,?,7: maximum delay" newline endif sif (cpuis("STM32MP151*")) hexmask.long.byte 0x4 14.--17. 1. "SDPHASE,SDPHASE" bitfld.long 0x4 12.--13. "SSTART,SSTART" "0,1,2,3" newline bitfld.long 0x4 9.--11. "MFWDLY,MFWDLY" "0,1,2,3,4,5,6,7" bitfld.long 0x4 6.--8. "MFBDLY,MFBDLY" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 3.--5. "SFWDLY,SFWDLY" "0,1,2,3,4,5,6,7" endif sif (cpuis("STM32MP153*")) hexmask.long.byte 0x4 14.--17. 1. "SDPHASE,SDPHASE" newline bitfld.long 0x4 12.--13. "SSTART,SSTART" "0,1,2,3" bitfld.long 0x4 9.--11. "MFWDLY,MFWDLY" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 6.--8. "MFBDLY,MFBDLY" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3.--5. "SFWDLY,SFWDLY" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 0.--2. "SFBDLY,SFBDLY" "0,1,2,3,4,5,6,7" endif sif (cpuis("STM32MP157*")) hexmask.long.byte 0x4 14.--17. 1. "SDPHASE,SDPHASE" newline bitfld.long 0x4 12.--13. "SSTART,SSTART" "0,1,2,3" bitfld.long 0x4 9.--11. "MFWDLY,MFWDLY" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 6.--8. "MFBDLY,MFBDLY" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3.--5. "SFWDLY,SFWDLY" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 0.--2. "SFBDLY,SFBDLY" "0,1,2,3,4,5,6,7" endif line.long 0x8 "DDRPHYC_DX1DQTR,DDRPHYC byte lane 1 DQT register" sif (cpuis("STM32MP13*")) hexmask.long.byte 0x8 28.--31. 1. "DQDLY7,DQ delay for bit 7" endif sif (cpuis("STM32MP151*")) hexmask.long.byte 0x8 28.--31. 1. "DQDLY7,DQDLY7" newline endif sif (cpuis("STM32MP153*")) hexmask.long.byte 0x8 28.--31. 1. "DQDLY7,DQDLY7" endif sif (cpuis("STM32MP157*")) hexmask.long.byte 0x8 28.--31. 1. "DQDLY7,DQDLY7" newline endif hexmask.long.byte 0x8 24.--27. 1. "DQDLY6,DQ delay for bit 6" hexmask.long.byte 0x8 20.--23. 1. "DQDLY5,DQ delay for bit 5" newline hexmask.long.byte 0x8 16.--19. 1. "DQDLY4,DQ delay for bit 4" hexmask.long.byte 0x8 12.--15. 1. "DQDLY3,DQ delay for bit 3" newline hexmask.long.byte 0x8 8.--11. 1. "DQDLY2,DQ delay for bit 2" hexmask.long.byte 0x8 4.--7. 1. "DQDLY1,DQ delay for bit 1" newline hexmask.long.byte 0x8 0.--3. 1. "DQDLY0,DQ delay for bit 0" line.long 0xC "DDRPHYC_DX1DQSTR,DDRPHYC byte lane 1 DQST register" sif (cpuis("STM32MP13*")) hexmask.long.byte 0xC 26.--29. 1. "DMDLY,DM delay" bitfld.long 0xC 23.--25. "DQSNDLY,DQS# delay" "0: nominal delay - 3 steps,1: nominal delay - 2 steps,2: nominal delay - 1 step,3: nominal delay,4: nominal delay + 1 step,5: nominal delay + 2 steps,6: nominal delay + 3 steps,7: nominal delay + 4 steps" newline bitfld.long 0xC 20.--22. "DQSDLY,DQS delay" "0: nominal delay - 3 steps,1: nominal delay - 2 steps,2: nominal delay - 1 step,3: nominal delay,4: nominal delay + 1 step,5: nominal delay + 2 steps,6: nominal delay + 3 steps,7: nominal delay + 4 steps" bitfld.long 0xC 12.--13. "R0DGPS,Rank 0 DQS gating phase select" "0: 180 clock (clk180),1: 270 clock (clk270),2: 360 clock (clk0),3: 450 clock (next clk90)" newline bitfld.long 0xC 0.--2. "R0DGSL,Rank 0 DQS gating system latency" "0: No extra clock cycles,1: 1 extra clock cycle,2: 2 extra clock cycles,3: 3 extra clock cycles,4: 4 extra clock cycles,5: 5 extra clock cycles,?,?" endif sif (cpuis("STM32MP151*")) hexmask.long.byte 0xC 26.--29. 1. "DMDLY,DMDLY" newline bitfld.long 0xC 23.--25. "DQSNDLY,DQSNDLY" "0,1,2,3,4,5,6,7" bitfld.long 0xC 20.--22. "DQSDLY,DQSDLY" "0,1,2,3,4,5,6,7" newline endif sif (cpuis("STM32MP153*")) hexmask.long.byte 0xC 26.--29. 1. "DMDLY,DMDLY" bitfld.long 0xC 23.--25. "DQSNDLY,DQSNDLY" "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 20.--22. "DQSDLY,DQSDLY" "0,1,2,3,4,5,6,7" endif sif (cpuis("STM32MP157*")) hexmask.long.byte 0xC 26.--29. 1. "DMDLY,DMDLY" newline bitfld.long 0xC 23.--25. "DQSNDLY,DQSNDLY" "0,1,2,3,4,5,6,7" bitfld.long 0xC 20.--22. "DQSDLY,DQSDLY" "0,1,2,3,4,5,6,7" newline endif sif (cpuis("STM32MP151*")) bitfld.long 0xC 12.--13. "R0DGPS,R0DGPS" "0,1,2,3" endif sif (cpuis("STM32MP153*")) bitfld.long 0xC 12.--13. "R0DGPS,R0DGPS" "0,1,2,3" newline endif sif (cpuis("STM32MP157*")) bitfld.long 0xC 12.--13. "R0DGPS,R0DGPS" "0,1,2,3" endif sif (cpuis("STM32MP153*")) bitfld.long 0xC 0.--2. "R0DGSL,R0DGSL" "0,1,2,3,4,5,6,7" newline endif sif (cpuis("STM32MP157*")) bitfld.long 0xC 0.--2. "R0DGSL,R0DGSL" "0,1,2,3,4,5,6,7" endif sif (cpuis("STM32MP13*")) group.long 0x44++0x3 line.long 0x0 "DDRPHYC_LPDDR2_MR1,DDRPHYC_LPDDR2_MR1" bitfld.long 0x0 5.--7. "NWR,Write recovery" "?,1: nWR=3,?,?,4: nWR=6,?,6: nWR=8,7: nWR=9" bitfld.long 0x0 4. "WC,Wrap control" "0: wrap,1: no wrap" newline bitfld.long 0x0 3. "BT,Burst Type: Indicates whether a burst is sequential (0) or interleaved (1). " "0,1" bitfld.long 0x0 0.--2. "BL,Burst length" "?,?,2: 4,3: 8,4: 16,?,?,?" group.long 0x44++0x7 line.long 0x0 "DDRPHYC_LPDDR3_MR1,DDRPHYC_LPDDR3_MR1" bitfld.long 0x0 5.--7. "NWR,Write recovery" "0: -001: nWR=3,1: -000: nWR=10,?,?,?,?,?,?" bitfld.long 0x0 0.--2. "BL,Burst length" "?,?,?,3: 8,?,?,?,?" line.long 0x4 "DDRPHYC_LPDDR2_MR2,DDRPHYC MR2 register for LPDDR2" bitfld.long 0x4 0.--2. "RLWL,Read and write latency" "?,1: RL = 3 /WL = 1,2: RL = 4 / WL = 2,3: RL = 5 / WL = 2,4: RL = 6 / WL = 3,5: RL = 7 / WL = 4,6: RL = 8 / WL = 4,?" group.long 0x48++0x3 line.long 0x0 "DDRPHYC_LPDDR3_MR2,DDRPHYC MR2 register for LPDDR3" bitfld.long 0x0 7. "WR,New for LPDDR3 (not used by this PHY leave at zero)" "0,1" bitfld.long 0x0 6. "WL,New for LPDDR3 (not used by this PHY leave at zero)" "0,1" newline bitfld.long 0x0 4. "NWRE,New for LPDDR3 (not used by this PHY leave at zero)" "0,1" bitfld.long 0x0 0.--2. "RLWL,Read and write latency" "?,1: RL = 3 /WL = 1,2: RL = 4 / WL = 2,3: RL = 5 / WL = 2,4: RL = 6 / WL = 3,5: RL = 7 / WL = 4,6: RL = 8 / WL = 4,?" endif sif (cpuis("STM32MP151*")) rgroup.long 0x0++0x3 line.long 0x0 "DDRPHYC_RIDR,DDRPHYC revision ID register" endif sif (cpuis("STM32MP151*")) wgroup.long 0x4++0x3 line.long 0x0 "DDRPHYC_PIR,DDRPHYC PHY initialization register" endif sif (cpuis("STM32MP151*")) rgroup.long 0xC++0x3 line.long 0x0 "DDRPHYC_PGSR,DDRPHYC PHY global status register" endif sif (cpuis("STM32MP151*")) rgroup.long 0x188++0x3 line.long 0x0 "DDRPHYC_ZQ0SR0,DDRPHYC ZQ0S register 0" endif sif (cpuis("STM32MP151*")) rgroup.byte 0x18C++0x0 line.byte 0x0 "DDRPHYC_ZQ0SR1,DDRPHYC ZQ0S register 1" endif sif (cpuis("STM32MP151*")) rgroup.word 0x1C4++0x1 line.word 0x0 "DDRPHYC_DX0GSR0,DDRPHYC byte lane 0 GS register 0" endif sif (cpuis("STM32MP151*")) rgroup.long 0x1C8++0x3 line.long 0x0 "DDRPHYC_DX0GSR1,DDRPHYC byte lane 0 GS register 1" endif sif (cpuis("STM32MP151*")) rgroup.word 0x204++0x1 line.word 0x0 "DDRPHYC_DX1GSR0,DDRPHYC byte lane 1 GS register 0" endif sif (cpuis("STM32MP151*")) rgroup.long 0x208++0x3 line.long 0x0 "DDRPHYC_DX1GSR1,DDRPHYC byte lane 1 GS register 1" group.long 0x240++0x3 line.long 0x0 "DDRPHYC_DX2GCR,DDRPHYC byte lane 2 GC register" bitfld.long 0x0 14.--16. "R0RVSL,R0RVSL" "0,1,2,3,4,5,6,7" bitfld.long 0x0 13. "RTTOAL,RTTOAL" "0,1" newline bitfld.long 0x0 11.--12. "RTTOH,RTTOH" "0,1,2,3" bitfld.long 0x0 10. "DQRTT,DQRTT" "0,1" newline bitfld.long 0x0 9. "DQSRTT,DQSRTT" "0,1" bitfld.long 0x0 7.--8. "DSEN,DSEN" "0,1,2,3" newline bitfld.long 0x0 6. "DQSRPD,DQSRPD" "0,1" bitfld.long 0x0 5. "DXPDR,DXPDR" "0,1" newline bitfld.long 0x0 4. "DXPDD,DXPDD" "0,1" bitfld.long 0x0 3. "DXIOM,DXIOM" "0,1" newline bitfld.long 0x0 2. "DQODT,DQODT" "0,1" bitfld.long 0x0 1. "DQSODT,DQSODT" "0,1" newline bitfld.long 0x0 0. "DXEN,DXEN" "0,1" rgroup.word 0x244++0x1 line.word 0x0 "DDRPHYC_DX2GSR0,DDRPHYC byte lane 2 GS register 0" bitfld.word 0x0 13.--15. "DTPASS,DTPASS" "0,1,2,3,4,5,6,7" bitfld.word 0x0 8. "DTIERR,DTIERR" "0,1" newline bitfld.word 0x0 4. "DTERR,DTERR" "0,1" bitfld.word 0x0 0. "DTDONE,DTDONE" "0,1" rgroup.long 0x248++0x3 line.long 0x0 "DDRPHYC_DX2GSR1,DDRPHYC byte lane 2 GS register 1" bitfld.long 0x0 20.--22. "RVPASS,RVPASS" "0,1,2,3,4,5,6,7" bitfld.long 0x0 16. "RVIERR,RVIERR" "0,1" newline bitfld.long 0x0 12. "RVERR,RVERR" "0,1" bitfld.long 0x0 4.--5. "DQSDFT,DQSDFT" "0,1,2,3" newline bitfld.long 0x0 0. "DFTERR,DFTERR" "0,1" group.long 0x24C++0xB line.long 0x0 "DDRPHYC_DX2DLLCR,DDRPHYC byte lane 2 DLLC register" bitfld.long 0x0 31. "DLLDIS,DLLDIS" "0,1" bitfld.long 0x0 30. "DLLSRST,DLLSRST" "0,1" newline bitfld.long 0x0 19. "SDLBMODE,SDLBMODE" "0,1" bitfld.long 0x0 18. "ATESTEN,ATESTEN" "0,1" newline hexmask.long.byte 0x0 14.--17. 1. "SDPHASE,SDPHASE" bitfld.long 0x0 12.--13. "SSTART,SSTART" "0,1,2,3" newline bitfld.long 0x0 9.--11. "MFWDLY,MFWDLY" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--8. "MFBDLY,MFBDLY" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3.--5. "SFWDLY,SFWDLY" "0,1,2,3,4,5,6,7" bitfld.long 0x0 0.--2. "SFBDLY,SFBDLY" "0,1,2,3,4,5,6,7" line.long 0x4 "DDRPHYC_DX2DQTR,DDRPHYC byte lane 2 DQT register" hexmask.long.byte 0x4 28.--31. 1. "DQDLY7,DQDLY7" hexmask.long.byte 0x4 24.--27. 1. "DQDLY6,DQDLY6" newline hexmask.long.byte 0x4 20.--23. 1. "DQDLY5,DQDLY5" hexmask.long.byte 0x4 16.--19. 1. "DQDLY4,DQDLY4" newline hexmask.long.byte 0x4 12.--15. 1. "DQDLY3,DQDLY3" hexmask.long.byte 0x4 8.--11. 1. "DQDLY2,DQDLY2" newline hexmask.long.byte 0x4 4.--7. 1. "DQDLY1,DQDLY1" hexmask.long.byte 0x4 0.--3. 1. "DQDLY0,DQDLY0" line.long 0x8 "DDRPHYC_DX2DQSTR,DDRPHYC byte lane 2 DQST register" hexmask.long.byte 0x8 26.--29. 1. "DMDLY,DMDLY" bitfld.long 0x8 23.--25. "DQSNDLY,DQSNDLY" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 20.--22. "DQSDLY,DQSDLY" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--13. "R0DGPS,R0DGPS" "0,1,2,3" newline bitfld.long 0x8 0.--2. "R0DGSL,R0DGSL" "0,1,2,3,4,5,6,7" group.long 0x280++0x3 line.long 0x0 "DDRPHYC_DX3GCR,DDRPHYC byte lane 3 GC register" bitfld.long 0x0 14.--16. "R0RVSL,R0RVSL" "0,1,2,3,4,5,6,7" bitfld.long 0x0 13. "RTTOAL,RTTOAL" "0,1" newline bitfld.long 0x0 11.--12. "RTTOH,RTTOH" "0,1,2,3" bitfld.long 0x0 10. "DQRTT,DQRTT" "0,1" newline bitfld.long 0x0 9. "DQSRTT,DQSRTT" "0,1" bitfld.long 0x0 7.--8. "DSEN,DSEN" "0,1,2,3" newline bitfld.long 0x0 6. "DQSRPD,DQSRPD" "0,1" bitfld.long 0x0 5. "DXPDR,DXPDR" "0,1" newline bitfld.long 0x0 4. "DXPDD,DXPDD" "0,1" bitfld.long 0x0 3. "DXIOM,DXIOM" "0,1" newline bitfld.long 0x0 2. "DQODT,DQODT" "0,1" bitfld.long 0x0 1. "DQSODT,DQSODT" "0,1" newline bitfld.long 0x0 0. "DXEN,DXEN" "0,1" rgroup.word 0x284++0x1 line.word 0x0 "DDRPHYC_DX3GSR0,DDRPHYC byte lane 3 GS register 0" bitfld.word 0x0 13.--15. "DTPASS,DTPASS" "0,1,2,3,4,5,6,7" bitfld.word 0x0 8. "DTIERR,DTIERR" "0,1" newline bitfld.word 0x0 4. "DTERR,DTERR" "0,1" bitfld.word 0x0 0. "DTDONE,DTDONE" "0,1" rgroup.long 0x288++0x3 line.long 0x0 "DDRPHYC_DX3GSR1,DDRPHYC byte lane 3 GS register 1" bitfld.long 0x0 20.--22. "RVPASS,RVPASS" "0,1,2,3,4,5,6,7" bitfld.long 0x0 16. "RVIERR,RVIERR" "0,1" newline bitfld.long 0x0 12. "RVERR,RVERR" "0,1" bitfld.long 0x0 4.--5. "DQSDFT,DQSDFT" "0,1,2,3" newline bitfld.long 0x0 0. "DFTERR,DFTERR" "0,1" group.long 0x28C++0xB line.long 0x0 "DDRPHYC_DX3DLLCR,DDRPHYC byte lane 3 DLLC register" bitfld.long 0x0 31. "DLLDIS,DLLDIS" "0,1" bitfld.long 0x0 30. "DLLSRST,DLLSRST" "0,1" newline bitfld.long 0x0 19. "SDLBMODE,SDLBMODE" "0,1" bitfld.long 0x0 18. "ATESTEN,ATESTEN" "0,1" newline hexmask.long.byte 0x0 14.--17. 1. "SDPHASE,SDPHASE" bitfld.long 0x0 12.--13. "SSTART,SSTART" "0,1,2,3" newline bitfld.long 0x0 9.--11. "MFWDLY,MFWDLY" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--8. "MFBDLY,MFBDLY" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3.--5. "SFWDLY,SFWDLY" "0,1,2,3,4,5,6,7" bitfld.long 0x0 0.--2. "SFBDLY,SFBDLY" "0,1,2,3,4,5,6,7" line.long 0x4 "DDRPHYC_DX3DQTR,DDRPHYC byte lane 3 DQT register" hexmask.long.byte 0x4 28.--31. 1. "DQDLY7,DQDLY7" hexmask.long.byte 0x4 24.--27. 1. "DQDLY6,DQDLY6" newline hexmask.long.byte 0x4 20.--23. 1. "DQDLY5,DQDLY5" hexmask.long.byte 0x4 16.--19. 1. "DQDLY4,DQDLY4" newline hexmask.long.byte 0x4 12.--15. 1. "DQDLY3,DQDLY3" hexmask.long.byte 0x4 8.--11. 1. "DQDLY2,DQDLY2" newline hexmask.long.byte 0x4 4.--7. 1. "DQDLY1,DQDLY1" hexmask.long.byte 0x4 0.--3. 1. "DQDLY0,DQDLY0" line.long 0x8 "DDRPHYC_DX3DQSTR,DDRPHYC byte lane 3 DQST register" hexmask.long.byte 0x8 26.--29. 1. "DMDLY,DMDLY" bitfld.long 0x8 23.--25. "DQSNDLY,DQSNDLY" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 20.--22. "DQSDLY,DQSDLY" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--13. "R0DGPS,R0DGPS" "0,1,2,3" newline bitfld.long 0x8 0.--2. "R0DGSL,R0DGSL" "0,1,2,3,4,5,6,7" endif sif (cpuis("STM32MP153*")) rgroup.long 0x0++0x3 line.long 0x0 "DDRPHYC_RIDR,DDRPHYC revision ID register" endif sif (cpuis("STM32MP153*")) wgroup.long 0x4++0x3 line.long 0x0 "DDRPHYC_PIR,DDRPHYC PHY initialization register" endif sif (cpuis("STM32MP153*")) rgroup.long 0xC++0x3 line.long 0x0 "DDRPHYC_PGSR,DDRPHYC PHY global status register" endif sif (cpuis("STM32MP153*")) rgroup.long 0x188++0x3 line.long 0x0 "DDRPHYC_ZQ0SR0,DDRPHYC ZQ0S register 0" endif sif (cpuis("STM32MP153*")) rgroup.byte 0x18C++0x0 line.byte 0x0 "DDRPHYC_ZQ0SR1,DDRPHYC ZQ0S register 1" endif sif (cpuis("STM32MP153*")) rgroup.word 0x1C4++0x1 line.word 0x0 "DDRPHYC_DX0GSR0,DDRPHYC byte lane 0 GS register 0" endif sif (cpuis("STM32MP153*")) rgroup.long 0x1C8++0x3 line.long 0x0 "DDRPHYC_DX0GSR1,DDRPHYC byte lane 0 GS register 1" endif sif (cpuis("STM32MP153*")) rgroup.word 0x204++0x1 line.word 0x0 "DDRPHYC_DX1GSR0,DDRPHYC byte lane 1 GS register 0" endif sif (cpuis("STM32MP153*")) rgroup.long 0x208++0x3 line.long 0x0 "DDRPHYC_DX1GSR1,DDRPHYC byte lane 1 GS register 1" group.long 0x240++0x3 line.long 0x0 "DDRPHYC_DX2GCR,DDRPHYC byte lane 2 GC register" bitfld.long 0x0 14.--16. "R0RVSL,R0RVSL" "0,1,2,3,4,5,6,7" bitfld.long 0x0 13. "RTTOAL,RTTOAL" "0,1" newline bitfld.long 0x0 11.--12. "RTTOH,RTTOH" "0,1,2,3" bitfld.long 0x0 10. "DQRTT,DQRTT" "0,1" newline bitfld.long 0x0 9. "DQSRTT,DQSRTT" "0,1" bitfld.long 0x0 7.--8. "DSEN,DSEN" "0,1,2,3" newline bitfld.long 0x0 6. "DQSRPD,DQSRPD" "0,1" bitfld.long 0x0 5. "DXPDR,DXPDR" "0,1" newline bitfld.long 0x0 4. "DXPDD,DXPDD" "0,1" bitfld.long 0x0 3. "DXIOM,DXIOM" "0,1" newline bitfld.long 0x0 2. "DQODT,DQODT" "0,1" bitfld.long 0x0 1. "DQSODT,DQSODT" "0,1" newline bitfld.long 0x0 0. "DXEN,DXEN" "0,1" rgroup.word 0x244++0x1 line.word 0x0 "DDRPHYC_DX2GSR0,DDRPHYC byte lane 2 GS register 0" bitfld.word 0x0 13.--15. "DTPASS,DTPASS" "0,1,2,3,4,5,6,7" bitfld.word 0x0 8. "DTIERR,DTIERR" "0,1" newline bitfld.word 0x0 4. "DTERR,DTERR" "0,1" bitfld.word 0x0 0. "DTDONE,DTDONE" "0,1" rgroup.long 0x248++0x3 line.long 0x0 "DDRPHYC_DX2GSR1,DDRPHYC byte lane 2 GS register 1" bitfld.long 0x0 20.--22. "RVPASS,RVPASS" "0,1,2,3,4,5,6,7" bitfld.long 0x0 16. "RVIERR,RVIERR" "0,1" newline bitfld.long 0x0 12. "RVERR,RVERR" "0,1" bitfld.long 0x0 4.--5. "DQSDFT,DQSDFT" "0,1,2,3" newline bitfld.long 0x0 0. "DFTERR,DFTERR" "0,1" group.long 0x24C++0xB line.long 0x0 "DDRPHYC_DX2DLLCR,DDRPHYC byte lane 2 DLLC register" bitfld.long 0x0 31. "DLLDIS,DLLDIS" "0,1" bitfld.long 0x0 30. "DLLSRST,DLLSRST" "0,1" newline bitfld.long 0x0 19. "SDLBMODE,SDLBMODE" "0,1" bitfld.long 0x0 18. "ATESTEN,ATESTEN" "0,1" newline hexmask.long.byte 0x0 14.--17. 1. "SDPHASE,SDPHASE" bitfld.long 0x0 12.--13. "SSTART,SSTART" "0,1,2,3" newline bitfld.long 0x0 9.--11. "MFWDLY,MFWDLY" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--8. "MFBDLY,MFBDLY" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3.--5. "SFWDLY,SFWDLY" "0,1,2,3,4,5,6,7" bitfld.long 0x0 0.--2. "SFBDLY,SFBDLY" "0,1,2,3,4,5,6,7" line.long 0x4 "DDRPHYC_DX2DQTR,DDRPHYC byte lane 2 DQT register" hexmask.long.byte 0x4 28.--31. 1. "DQDLY7,DQDLY7" hexmask.long.byte 0x4 24.--27. 1. "DQDLY6,DQDLY6" newline hexmask.long.byte 0x4 20.--23. 1. "DQDLY5,DQDLY5" hexmask.long.byte 0x4 16.--19. 1. "DQDLY4,DQDLY4" newline hexmask.long.byte 0x4 12.--15. 1. "DQDLY3,DQDLY3" hexmask.long.byte 0x4 8.--11. 1. "DQDLY2,DQDLY2" newline hexmask.long.byte 0x4 4.--7. 1. "DQDLY1,DQDLY1" hexmask.long.byte 0x4 0.--3. 1. "DQDLY0,DQDLY0" line.long 0x8 "DDRPHYC_DX2DQSTR,DDRPHYC byte lane 2 DQST register" hexmask.long.byte 0x8 26.--29. 1. "DMDLY,DMDLY" bitfld.long 0x8 23.--25. "DQSNDLY,DQSNDLY" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 20.--22. "DQSDLY,DQSDLY" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--13. "R0DGPS,R0DGPS" "0,1,2,3" newline bitfld.long 0x8 0.--2. "R0DGSL,R0DGSL" "0,1,2,3,4,5,6,7" group.long 0x280++0x3 line.long 0x0 "DDRPHYC_DX3GCR,DDRPHYC byte lane 3 GC register" bitfld.long 0x0 14.--16. "R0RVSL,R0RVSL" "0,1,2,3,4,5,6,7" bitfld.long 0x0 13. "RTTOAL,RTTOAL" "0,1" newline bitfld.long 0x0 11.--12. "RTTOH,RTTOH" "0,1,2,3" bitfld.long 0x0 10. "DQRTT,DQRTT" "0,1" newline bitfld.long 0x0 9. "DQSRTT,DQSRTT" "0,1" bitfld.long 0x0 7.--8. "DSEN,DSEN" "0,1,2,3" newline bitfld.long 0x0 6. "DQSRPD,DQSRPD" "0,1" bitfld.long 0x0 5. "DXPDR,DXPDR" "0,1" newline bitfld.long 0x0 4. "DXPDD,DXPDD" "0,1" bitfld.long 0x0 3. "DXIOM,DXIOM" "0,1" newline bitfld.long 0x0 2. "DQODT,DQODT" "0,1" bitfld.long 0x0 1. "DQSODT,DQSODT" "0,1" newline bitfld.long 0x0 0. "DXEN,DXEN" "0,1" rgroup.word 0x284++0x1 line.word 0x0 "DDRPHYC_DX3GSR0,DDRPHYC byte lane 3 GS register 0" bitfld.word 0x0 13.--15. "DTPASS,DTPASS" "0,1,2,3,4,5,6,7" bitfld.word 0x0 8. "DTIERR,DTIERR" "0,1" newline bitfld.word 0x0 4. "DTERR,DTERR" "0,1" bitfld.word 0x0 0. "DTDONE,DTDONE" "0,1" rgroup.long 0x288++0x3 line.long 0x0 "DDRPHYC_DX3GSR1,DDRPHYC byte lane 3 GS register 1" bitfld.long 0x0 20.--22. "RVPASS,RVPASS" "0,1,2,3,4,5,6,7" bitfld.long 0x0 16. "RVIERR,RVIERR" "0,1" newline bitfld.long 0x0 12. "RVERR,RVERR" "0,1" bitfld.long 0x0 4.--5. "DQSDFT,DQSDFT" "0,1,2,3" newline bitfld.long 0x0 0. "DFTERR,DFTERR" "0,1" group.long 0x28C++0xB line.long 0x0 "DDRPHYC_DX3DLLCR,DDRPHYC byte lane 3 DLLC register" bitfld.long 0x0 31. "DLLDIS,DLLDIS" "0,1" bitfld.long 0x0 30. "DLLSRST,DLLSRST" "0,1" newline bitfld.long 0x0 19. "SDLBMODE,SDLBMODE" "0,1" bitfld.long 0x0 18. "ATESTEN,ATESTEN" "0,1" newline hexmask.long.byte 0x0 14.--17. 1. "SDPHASE,SDPHASE" bitfld.long 0x0 12.--13. "SSTART,SSTART" "0,1,2,3" newline bitfld.long 0x0 9.--11. "MFWDLY,MFWDLY" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--8. "MFBDLY,MFBDLY" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3.--5. "SFWDLY,SFWDLY" "0,1,2,3,4,5,6,7" bitfld.long 0x0 0.--2. "SFBDLY,SFBDLY" "0,1,2,3,4,5,6,7" line.long 0x4 "DDRPHYC_DX3DQTR,DDRPHYC byte lane 3 DQT register" hexmask.long.byte 0x4 28.--31. 1. "DQDLY7,DQDLY7" hexmask.long.byte 0x4 24.--27. 1. "DQDLY6,DQDLY6" newline hexmask.long.byte 0x4 20.--23. 1. "DQDLY5,DQDLY5" hexmask.long.byte 0x4 16.--19. 1. "DQDLY4,DQDLY4" newline hexmask.long.byte 0x4 12.--15. 1. "DQDLY3,DQDLY3" hexmask.long.byte 0x4 8.--11. 1. "DQDLY2,DQDLY2" newline hexmask.long.byte 0x4 4.--7. 1. "DQDLY1,DQDLY1" hexmask.long.byte 0x4 0.--3. 1. "DQDLY0,DQDLY0" line.long 0x8 "DDRPHYC_DX3DQSTR,DDRPHYC byte lane 3 DQST register" hexmask.long.byte 0x8 26.--29. 1. "DMDLY,DMDLY" bitfld.long 0x8 23.--25. "DQSNDLY,DQSNDLY" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 20.--22. "DQSDLY,DQSDLY" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--13. "R0DGPS,R0DGPS" "0,1,2,3" newline bitfld.long 0x8 0.--2. "R0DGSL,R0DGSL" "0,1,2,3,4,5,6,7" endif sif (cpuis("STM32MP157*")) rgroup.long 0x0++0x3 line.long 0x0 "DDRPHYC_RIDR,DDRPHYC revision ID register" endif sif (cpuis("STM32MP157*")) wgroup.long 0x4++0x3 line.long 0x0 "DDRPHYC_PIR,DDRPHYC PHY initialization register" endif sif (cpuis("STM32MP157*")) rgroup.long 0xC++0x3 line.long 0x0 "DDRPHYC_PGSR,DDRPHYC PHY global status register" endif sif (cpuis("STM32MP157*")) rgroup.long 0x188++0x3 line.long 0x0 "DDRPHYC_ZQ0SR0,DDRPHYC ZQ0S register 0" endif sif (cpuis("STM32MP157*")) rgroup.byte 0x18C++0x0 line.byte 0x0 "DDRPHYC_ZQ0SR1,DDRPHYC ZQ0S register 1" endif sif (cpuis("STM32MP157*")) rgroup.word 0x1C4++0x1 line.word 0x0 "DDRPHYC_DX0GSR0,DDRPHYC byte lane 0 GS register 0" endif sif (cpuis("STM32MP157*")) rgroup.long 0x1C8++0x3 line.long 0x0 "DDRPHYC_DX0GSR1,DDRPHYC byte lane 0 GS register 1" endif sif (cpuis("STM32MP157*")) rgroup.word 0x204++0x1 line.word 0x0 "DDRPHYC_DX1GSR0,DDRPHYC byte lane 1 GS register 0" endif sif (cpuis("STM32MP157*")) rgroup.long 0x208++0x3 line.long 0x0 "DDRPHYC_DX1GSR1,DDRPHYC byte lane 1 GS register 1" group.long 0x240++0x3 line.long 0x0 "DDRPHYC_DX2GCR,DDRPHYC byte lane 2 GC register" bitfld.long 0x0 14.--16. "R0RVSL,R0RVSL" "0,1,2,3,4,5,6,7" bitfld.long 0x0 13. "RTTOAL,RTTOAL" "0,1" newline bitfld.long 0x0 11.--12. "RTTOH,RTTOH" "0,1,2,3" bitfld.long 0x0 10. "DQRTT,DQRTT" "0,1" newline bitfld.long 0x0 9. "DQSRTT,DQSRTT" "0,1" bitfld.long 0x0 7.--8. "DSEN,DSEN" "0,1,2,3" newline bitfld.long 0x0 6. "DQSRPD,DQSRPD" "0,1" bitfld.long 0x0 5. "DXPDR,DXPDR" "0,1" newline bitfld.long 0x0 4. "DXPDD,DXPDD" "0,1" bitfld.long 0x0 3. "DXIOM,DXIOM" "0,1" newline bitfld.long 0x0 2. "DQODT,DQODT" "0,1" bitfld.long 0x0 1. "DQSODT,DQSODT" "0,1" newline bitfld.long 0x0 0. "DXEN,DXEN" "0,1" rgroup.word 0x244++0x1 line.word 0x0 "DDRPHYC_DX2GSR0,DDRPHYC byte lane 2 GS register 0" bitfld.word 0x0 13.--15. "DTPASS,DTPASS" "0,1,2,3,4,5,6,7" bitfld.word 0x0 8. "DTIERR,DTIERR" "0,1" newline bitfld.word 0x0 4. "DTERR,DTERR" "0,1" bitfld.word 0x0 0. "DTDONE,DTDONE" "0,1" rgroup.long 0x248++0x3 line.long 0x0 "DDRPHYC_DX2GSR1,DDRPHYC byte lane 2 GS register 1" bitfld.long 0x0 20.--22. "RVPASS,RVPASS" "0,1,2,3,4,5,6,7" bitfld.long 0x0 16. "RVIERR,RVIERR" "0,1" newline bitfld.long 0x0 12. "RVERR,RVERR" "0,1" bitfld.long 0x0 4.--5. "DQSDFT,DQSDFT" "0,1,2,3" newline bitfld.long 0x0 0. "DFTERR,DFTERR" "0,1" group.long 0x24C++0xB line.long 0x0 "DDRPHYC_DX2DLLCR,DDRPHYC byte lane 2 DLLC register" bitfld.long 0x0 31. "DLLDIS,DLLDIS" "0,1" bitfld.long 0x0 30. "DLLSRST,DLLSRST" "0,1" newline bitfld.long 0x0 19. "SDLBMODE,SDLBMODE" "0,1" bitfld.long 0x0 18. "ATESTEN,ATESTEN" "0,1" newline hexmask.long.byte 0x0 14.--17. 1. "SDPHASE,SDPHASE" bitfld.long 0x0 12.--13. "SSTART,SSTART" "0,1,2,3" newline bitfld.long 0x0 9.--11. "MFWDLY,MFWDLY" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--8. "MFBDLY,MFBDLY" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3.--5. "SFWDLY,SFWDLY" "0,1,2,3,4,5,6,7" bitfld.long 0x0 0.--2. "SFBDLY,SFBDLY" "0,1,2,3,4,5,6,7" line.long 0x4 "DDRPHYC_DX2DQTR,DDRPHYC byte lane 2 DQT register" hexmask.long.byte 0x4 28.--31. 1. "DQDLY7,DQDLY7" hexmask.long.byte 0x4 24.--27. 1. "DQDLY6,DQDLY6" newline hexmask.long.byte 0x4 20.--23. 1. "DQDLY5,DQDLY5" hexmask.long.byte 0x4 16.--19. 1. "DQDLY4,DQDLY4" newline hexmask.long.byte 0x4 12.--15. 1. "DQDLY3,DQDLY3" hexmask.long.byte 0x4 8.--11. 1. "DQDLY2,DQDLY2" newline hexmask.long.byte 0x4 4.--7. 1. "DQDLY1,DQDLY1" hexmask.long.byte 0x4 0.--3. 1. "DQDLY0,DQDLY0" line.long 0x8 "DDRPHYC_DX2DQSTR,DDRPHYC byte lane 2 DQST register" hexmask.long.byte 0x8 26.--29. 1. "DMDLY,DMDLY" bitfld.long 0x8 23.--25. "DQSNDLY,DQSNDLY" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 20.--22. "DQSDLY,DQSDLY" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--13. "R0DGPS,R0DGPS" "0,1,2,3" newline bitfld.long 0x8 0.--2. "R0DGSL,R0DGSL" "0,1,2,3,4,5,6,7" group.long 0x280++0x3 line.long 0x0 "DDRPHYC_DX3GCR,DDRPHYC byte lane 3 GC register" bitfld.long 0x0 14.--16. "R0RVSL,R0RVSL" "0,1,2,3,4,5,6,7" bitfld.long 0x0 13. "RTTOAL,RTTOAL" "0,1" newline bitfld.long 0x0 11.--12. "RTTOH,RTTOH" "0,1,2,3" bitfld.long 0x0 10. "DQRTT,DQRTT" "0,1" newline bitfld.long 0x0 9. "DQSRTT,DQSRTT" "0,1" bitfld.long 0x0 7.--8. "DSEN,DSEN" "0,1,2,3" newline bitfld.long 0x0 6. "DQSRPD,DQSRPD" "0,1" bitfld.long 0x0 5. "DXPDR,DXPDR" "0,1" newline bitfld.long 0x0 4. "DXPDD,DXPDD" "0,1" bitfld.long 0x0 3. "DXIOM,DXIOM" "0,1" newline bitfld.long 0x0 2. "DQODT,DQODT" "0,1" bitfld.long 0x0 1. "DQSODT,DQSODT" "0,1" newline bitfld.long 0x0 0. "DXEN,DXEN" "0,1" rgroup.word 0x284++0x1 line.word 0x0 "DDRPHYC_DX3GSR0,DDRPHYC byte lane 3 GS register 0" bitfld.word 0x0 13.--15. "DTPASS,DTPASS" "0,1,2,3,4,5,6,7" bitfld.word 0x0 8. "DTIERR,DTIERR" "0,1" newline bitfld.word 0x0 4. "DTERR,DTERR" "0,1" bitfld.word 0x0 0. "DTDONE,DTDONE" "0,1" rgroup.long 0x288++0x3 line.long 0x0 "DDRPHYC_DX3GSR1,DDRPHYC byte lane 3 GS register 1" bitfld.long 0x0 20.--22. "RVPASS,RVPASS" "0,1,2,3,4,5,6,7" bitfld.long 0x0 16. "RVIERR,RVIERR" "0,1" newline bitfld.long 0x0 12. "RVERR,RVERR" "0,1" bitfld.long 0x0 4.--5. "DQSDFT,DQSDFT" "0,1,2,3" newline bitfld.long 0x0 0. "DFTERR,DFTERR" "0,1" group.long 0x28C++0xB line.long 0x0 "DDRPHYC_DX3DLLCR,DDRPHYC byte lane 3 DLLC register" bitfld.long 0x0 31. "DLLDIS,DLLDIS" "0,1" bitfld.long 0x0 30. "DLLSRST,DLLSRST" "0,1" newline bitfld.long 0x0 19. "SDLBMODE,SDLBMODE" "0,1" bitfld.long 0x0 18. "ATESTEN,ATESTEN" "0,1" newline hexmask.long.byte 0x0 14.--17. 1. "SDPHASE,SDPHASE" bitfld.long 0x0 12.--13. "SSTART,SSTART" "0,1,2,3" newline bitfld.long 0x0 9.--11. "MFWDLY,MFWDLY" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--8. "MFBDLY,MFBDLY" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3.--5. "SFWDLY,SFWDLY" "0,1,2,3,4,5,6,7" bitfld.long 0x0 0.--2. "SFBDLY,SFBDLY" "0,1,2,3,4,5,6,7" line.long 0x4 "DDRPHYC_DX3DQTR,DDRPHYC byte lane 3 DQT register" hexmask.long.byte 0x4 28.--31. 1. "DQDLY7,DQDLY7" hexmask.long.byte 0x4 24.--27. 1. "DQDLY6,DQDLY6" newline hexmask.long.byte 0x4 20.--23. 1. "DQDLY5,DQDLY5" hexmask.long.byte 0x4 16.--19. 1. "DQDLY4,DQDLY4" newline hexmask.long.byte 0x4 12.--15. 1. "DQDLY3,DQDLY3" hexmask.long.byte 0x4 8.--11. 1. "DQDLY2,DQDLY2" newline hexmask.long.byte 0x4 4.--7. 1. "DQDLY1,DQDLY1" hexmask.long.byte 0x4 0.--3. 1. "DQDLY0,DQDLY0" line.long 0x8 "DDRPHYC_DX3DQSTR,DDRPHYC byte lane 3 DQST register" hexmask.long.byte 0x8 26.--29. 1. "DMDLY,DMDLY" bitfld.long 0x8 23.--25. "DQSNDLY,DQSNDLY" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 20.--22. "DQSDLY,DQSDLY" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--13. "R0DGPS,R0DGPS" "0,1,2,3" newline bitfld.long 0x8 0.--2. "R0DGSL,R0DGSL" "0,1,2,3,4,5,6,7" endif tree.end tree "DFSDM (Digital Filter for Sigma Delta Modulators)" base ad:0x0 sif (cpuis("STM32MP13*")) tree "DFSDM" base ad:0x4400D000 group.long 0x0++0xB line.long 0x0 "DFSDM_CH0CFGR1,DFSDM channel 0 configuration register" bitfld.long 0x0 31. "DFSDMEN,Global enable for DFSDM interface" "0: all registers DFSDM_FLTxISR are set to reset..,1: DFSDM interface enabled" bitfld.long 0x0 30. "CKOUTSRC,Output serial clock source selection" "0: Source for output clock is from system clock,1: Source for output clock is from audio clock" newline hexmask.long.byte 0x0 16.--23. 1. "CKOUTDIV,Output serial clock divider" bitfld.long 0x0 14.--15. "DATPACK,Data packing mode in DFSDM_CHyDATINR register." "0: Standard: input data in DFSDM_CHyDATINR register..,1: Interleaved: input data in DFSDM_CHyDATINR..,2: Dual: input data in DFSDM_CHyDATINR register are..,3: Reserved" newline bitfld.long 0x0 12.--13. "DATMPX,Input data multiplexer for channel y" "0: Data to channel y are taken from external serial..,1: Data to channel y are taken from internal analog..,2: Data to channel y are taken from internal..,3: Reserved" bitfld.long 0x0 8. "CHINSEL,Channel inputs selection" "0: Channel inputs are taken from pins of the same..,1: Channel inputs are taken from pins of the.." newline bitfld.long 0x0 7. "CHEN,Channel y enable" "0: Channel y disabled,1: Channel y enabled" bitfld.long 0x0 6. "CKABEN,Clock absence detector enable on channel y" "0: Clock absence detector disabled on channel y,1: Clock absence detector enabled on channel y" newline bitfld.long 0x0 5. "SCDEN,Short-circuit detector enable on channel y" "0: Input channel y will not be guarded by the..,1: Input channel y will be continuously guarded by.." bitfld.long 0x0 2.--3. "SPICKSEL,SPI clock select for channel y" "0: clock coming from external CKINy input -..,1: clock coming from internal CKOUT output -..,2: clock coming from internal CKOUT,3: clock coming from internal CKOUT output" newline bitfld.long 0x0 0.--1. "SITP,Serial interface type for channel y" "0: SPI with rising edge to strobe data,1: SPI with falling edge to strobe data,2: Manchester coded input on DATINy pin: rising..,3: Manchester coded input on DATINy pin: rising.." line.long 0x4 "DFSDM_CH0CFGR2,DFSDM channel 0 configuration register" hexmask.long.tbyte 0x4 8.--31. 1. "OFFSET,24-bit calibration offset for channel y" hexmask.long.byte 0x4 3.--7. 1. "DTRBS,Data right bit-shift for channel y" line.long 0x8 "DFSDM_CH0AWSCDR,DFSDM channel 0 analog watchdog and short-circuit detector register" bitfld.long 0x8 22.--23. "AWFORD,Analog watchdog Sinc filter order on channel y" "0: FastSinc filter type,1: Sinc1 filter type,2: Sinc2 filter type,3: Sinc3 filter type" hexmask.long.byte 0x8 16.--20. 1. "AWFOSR,Analog watchdog filter oversampling ratio (decimation rate) on channel y" newline hexmask.long.byte 0x8 12.--15. 1. "BKSCD,Break signal assignment for short-circuit detector on channel y" hexmask.long.byte 0x8 0.--7. 1. "SCDT,short-circuit detector threshold for channel y" rgroup.long 0xC++0x3 line.long 0x0 "DFSDM_CH0WDATR,DFSDM channel 0 watchdog filter data register" hexmask.long.word 0x0 0.--15. 1. "WDATA,Input channel y watchdog data" group.long 0x10++0x7 line.long 0x0 "DFSDM_CH0DATINR,DFSDM channel 0 data input register" hexmask.long.word 0x0 16.--31. 1. "INDAT1,Input data for channel y or channel y+1" hexmask.long.word 0x0 0.--15. 1. "INDAT0,Input data for channel y" line.long 0x4 "DFSDM_CH0DLYR," hexmask.long.byte 0x4 0.--5. 1. "PLSSKP,Pulses to skip for input data skipping function" group.long 0x20++0xB line.long 0x0 "DFSDM_CH1CFGR1,DFSDM channel 1 configuration register" bitfld.long 0x0 31. "DFSDMEN,Global enable for DFSDM interface" "0: all registers DFSDM_FLTxISR are set to reset..,1: DFSDM interface enabled" bitfld.long 0x0 30. "CKOUTSRC,Output serial clock source selection" "0: Source for output clock is from system clock,1: Source for output clock is from audio clock" newline hexmask.long.byte 0x0 16.--23. 1. "CKOUTDIV,Output serial clock divider" bitfld.long 0x0 14.--15. "DATPACK,Data packing mode in DFSDM_CHyDATINR register." "0: Standard: input data in DFSDM_CHyDATINR register..,1: Interleaved: input data in DFSDM_CHyDATINR..,2: Dual: input data in DFSDM_CHyDATINR register are..,3: Reserved" newline bitfld.long 0x0 12.--13. "DATMPX,Input data multiplexer for channel y" "0: Data to channel y are taken from external serial..,1: Data to channel y are taken from internal analog..,2: Data to channel y are taken from internal..,3: Reserved" bitfld.long 0x0 8. "CHINSEL,Channel inputs selection" "0: Channel inputs are taken from pins of the same..,1: Channel inputs are taken from pins of the.." newline bitfld.long 0x0 7. "CHEN,Channel y enable" "0: Channel y disabled,1: Channel y enabled" bitfld.long 0x0 6. "CKABEN,Clock absence detector enable on channel y" "0: Clock absence detector disabled on channel y,1: Clock absence detector enabled on channel y" newline bitfld.long 0x0 5. "SCDEN,Short-circuit detector enable on channel y" "0: Input channel y will not be guarded by the..,1: Input channel y will be continuously guarded by.." bitfld.long 0x0 2.--3. "SPICKSEL,SPI clock select for channel y" "0: clock coming from external CKINy input -..,1: clock coming from internal CKOUT output -..,2: clock coming from internal CKOUT,3: clock coming from internal CKOUT output" newline bitfld.long 0x0 0.--1. "SITP,Serial interface type for channel y" "0: SPI with rising edge to strobe data,1: SPI with falling edge to strobe data,2: Manchester coded input on DATINy pin: rising..,3: Manchester coded input on DATINy pin: rising.." line.long 0x4 "DFSDM_CH1CFGR2,DFSDM channel 1 configuration register" hexmask.long.tbyte 0x4 8.--31. 1. "OFFSET,24-bit calibration offset for channel y" hexmask.long.byte 0x4 3.--7. 1. "DTRBS,Data right bit-shift for channel y" line.long 0x8 "DFSDM_CH1AWSCDR,DFSDM channel 1 analog watchdog and short-circuit detector register" bitfld.long 0x8 22.--23. "AWFORD,Analog watchdog Sinc filter order on channel y" "0: FastSinc filter type,1: Sinc1 filter type,2: Sinc2 filter type,3: Sinc3 filter type" hexmask.long.byte 0x8 16.--20. 1. "AWFOSR,Analog watchdog filter oversampling ratio (decimation rate) on channel y" newline hexmask.long.byte 0x8 12.--15. 1. "BKSCD,Break signal assignment for short-circuit detector on channel y" hexmask.long.byte 0x8 0.--7. 1. "SCDT,short-circuit detector threshold for channel y" rgroup.long 0x2C++0x3 line.long 0x0 "DFSDM_CH1WDATR,DFSDM channel 1 watchdog filter data register" hexmask.long.word 0x0 0.--15. 1. "WDATA,Input channel y watchdog data" group.long 0x30++0x7 line.long 0x0 "DFSDM_CH1DATINR,DFSDM channel 1 data input register" hexmask.long.word 0x0 16.--31. 1. "INDAT1,Input data for channel y or channel y+1" hexmask.long.word 0x0 0.--15. 1. "INDAT0,Input data for channel y" line.long 0x4 "DFSDM_CH1DLYR," hexmask.long.byte 0x4 0.--5. 1. "PLSSKP,Pulses to skip for input data skipping function" group.long 0x40++0xB line.long 0x0 "DFSDM_CH2CFGR1,DFSDM channel 2 configuration register" bitfld.long 0x0 31. "DFSDMEN,Global enable for DFSDM interface" "0: all registers DFSDM_FLTxISR are set to reset..,1: DFSDM interface enabled" bitfld.long 0x0 30. "CKOUTSRC,Output serial clock source selection" "0: Source for output clock is from system clock,1: Source for output clock is from audio clock" newline hexmask.long.byte 0x0 16.--23. 1. "CKOUTDIV,Output serial clock divider" bitfld.long 0x0 14.--15. "DATPACK,Data packing mode in DFSDM_CHyDATINR register." "0: Standard: input data in DFSDM_CHyDATINR register..,1: Interleaved: input data in DFSDM_CHyDATINR..,2: Dual: input data in DFSDM_CHyDATINR register are..,3: Reserved" newline bitfld.long 0x0 12.--13. "DATMPX,Input data multiplexer for channel y" "0: Data to channel y are taken from external serial..,1: Data to channel y are taken from internal analog..,2: Data to channel y are taken from internal..,3: Reserved" bitfld.long 0x0 8. "CHINSEL,Channel inputs selection" "0: Channel inputs are taken from pins of the same..,1: Channel inputs are taken from pins of the.." newline bitfld.long 0x0 7. "CHEN,Channel y enable" "0: Channel y disabled,1: Channel y enabled" bitfld.long 0x0 6. "CKABEN,Clock absence detector enable on channel y" "0: Clock absence detector disabled on channel y,1: Clock absence detector enabled on channel y" newline bitfld.long 0x0 5. "SCDEN,Short-circuit detector enable on channel y" "0: Input channel y will not be guarded by the..,1: Input channel y will be continuously guarded by.." bitfld.long 0x0 2.--3. "SPICKSEL,SPI clock select for channel y" "0: clock coming from external CKINy input -..,1: clock coming from internal CKOUT output -..,2: clock coming from internal CKOUT,3: clock coming from internal CKOUT output" newline bitfld.long 0x0 0.--1. "SITP,Serial interface type for channel y" "0: SPI with rising edge to strobe data,1: SPI with falling edge to strobe data,2: Manchester coded input on DATINy pin: rising..,3: Manchester coded input on DATINy pin: rising.." line.long 0x4 "DFSDM_CH2CFGR2,DFSDM channel 2 configuration register" hexmask.long.tbyte 0x4 8.--31. 1. "OFFSET,24-bit calibration offset for channel y" hexmask.long.byte 0x4 3.--7. 1. "DTRBS,Data right bit-shift for channel y" line.long 0x8 "DFSDM_CH2AWSCDR,DFSDM channel 2 analog watchdog and short-circuit detector register" bitfld.long 0x8 22.--23. "AWFORD,Analog watchdog Sinc filter order on channel y" "0: FastSinc filter type,1: Sinc1 filter type,2: Sinc2 filter type,3: Sinc3 filter type" hexmask.long.byte 0x8 16.--20. 1. "AWFOSR,Analog watchdog filter oversampling ratio (decimation rate) on channel y" newline hexmask.long.byte 0x8 12.--15. 1. "BKSCD,Break signal assignment for short-circuit detector on channel y" hexmask.long.byte 0x8 0.--7. 1. "SCDT,short-circuit detector threshold for channel y" rgroup.long 0x4C++0x3 line.long 0x0 "DFSDM_CH2WDATR,DFSDM channel 2 watchdog filter data register" hexmask.long.word 0x0 0.--15. 1. "WDATA,Input channel y watchdog data" group.long 0x50++0x7 line.long 0x0 "DFSDM_CH2DATINR,DFSDM channel 2 data input register" hexmask.long.word 0x0 16.--31. 1. "INDAT1,Input data for channel y or channel y+1" hexmask.long.word 0x0 0.--15. 1. "INDAT0,Input data for channel y" line.long 0x4 "DFSDM_CH2DLYR," hexmask.long.byte 0x4 0.--5. 1. "PLSSKP,Pulses to skip for input data skipping function" group.long 0x60++0xB line.long 0x0 "DFSDM_CH3CFGR1,DFSDM channel 3 configuration register" bitfld.long 0x0 31. "DFSDMEN,Global enable for DFSDM interface" "0: all registers DFSDM_FLTxISR are set to reset..,1: DFSDM interface enabled" bitfld.long 0x0 30. "CKOUTSRC,Output serial clock source selection" "0: Source for output clock is from system clock,1: Source for output clock is from audio clock" newline hexmask.long.byte 0x0 16.--23. 1. "CKOUTDIV,Output serial clock divider" bitfld.long 0x0 14.--15. "DATPACK,Data packing mode in DFSDM_CHyDATINR register." "0: Standard: input data in DFSDM_CHyDATINR register..,1: Interleaved: input data in DFSDM_CHyDATINR..,2: Dual: input data in DFSDM_CHyDATINR register are..,3: Reserved" newline bitfld.long 0x0 12.--13. "DATMPX,Input data multiplexer for channel y" "0: Data to channel y are taken from external serial..,1: Data to channel y are taken from internal analog..,2: Data to channel y are taken from internal..,3: Reserved" bitfld.long 0x0 8. "CHINSEL,Channel inputs selection" "0: Channel inputs are taken from pins of the same..,1: Channel inputs are taken from pins of the.." newline bitfld.long 0x0 7. "CHEN,Channel y enable" "0: Channel y disabled,1: Channel y enabled" bitfld.long 0x0 6. "CKABEN,Clock absence detector enable on channel y" "0: Clock absence detector disabled on channel y,1: Clock absence detector enabled on channel y" newline bitfld.long 0x0 5. "SCDEN,Short-circuit detector enable on channel y" "0: Input channel y will not be guarded by the..,1: Input channel y will be continuously guarded by.." bitfld.long 0x0 2.--3. "SPICKSEL,SPI clock select for channel y" "0: clock coming from external CKINy input -..,1: clock coming from internal CKOUT output -..,2: clock coming from internal CKOUT,3: clock coming from internal CKOUT output" newline bitfld.long 0x0 0.--1. "SITP,Serial interface type for channel y" "0: SPI with rising edge to strobe data,1: SPI with falling edge to strobe data,2: Manchester coded input on DATINy pin: rising..,3: Manchester coded input on DATINy pin: rising.." line.long 0x4 "DFSDM_CH3CFGR2,DFSDM channel 3 configuration register" hexmask.long.tbyte 0x4 8.--31. 1. "OFFSET,24-bit calibration offset for channel y" hexmask.long.byte 0x4 3.--7. 1. "DTRBS,Data right bit-shift for channel y" line.long 0x8 "DFSDM_CH3AWSCDR,DFSDM channel 3 analog watchdog and short-circuit detector register" bitfld.long 0x8 22.--23. "AWFORD,Analog watchdog Sinc filter order on channel y" "0: FastSinc filter type,1: Sinc1 filter type,2: Sinc2 filter type,3: Sinc3 filter type" hexmask.long.byte 0x8 16.--20. 1. "AWFOSR,Analog watchdog filter oversampling ratio (decimation rate) on channel y" newline hexmask.long.byte 0x8 12.--15. 1. "BKSCD,Break signal assignment for short-circuit detector on channel y" hexmask.long.byte 0x8 0.--7. 1. "SCDT,short-circuit detector threshold for channel y" rgroup.long 0x6C++0x3 line.long 0x0 "DFSDM_CH3WDATR,DFSDM channel 3 watchdog filter data register" hexmask.long.word 0x0 0.--15. 1. "WDATA,Input channel y watchdog data" group.long 0x70++0x7 line.long 0x0 "DFSDM_CH3DATINR,DFSDM channel 3 data input register" hexmask.long.word 0x0 16.--31. 1. "INDAT1,Input data for channel y or channel y+1" hexmask.long.word 0x0 0.--15. 1. "INDAT0,Input data for channel y" line.long 0x4 "DFSDM_CH3DLYR," hexmask.long.byte 0x4 0.--5. 1. "PLSSKP,Pulses to skip for input data skipping function" group.long 0x94++0x3 line.long 0x0 "DFSDM_CH4DLYR," hexmask.long.byte 0x0 0.--5. 1. "PLSSKP,Pulses to skip for input data skipping function" group.long 0xB4++0x3 line.long 0x0 "DFSDM_CH5DLYR," hexmask.long.byte 0x0 0.--5. 1. "PLSSKP,Pulses to skip for input data skipping function" group.long 0xD4++0x3 line.long 0x0 "DFSDM_CH6DLYR," hexmask.long.byte 0x0 0.--5. 1. "PLSSKP,Pulses to skip for input data skipping function" group.long 0xF4++0x3 line.long 0x0 "DFSDM_CH7DLYR," hexmask.long.byte 0x0 0.--5. 1. "PLSSKP,Pulses to skip for input data skipping function" group.long 0x100++0x7 line.long 0x0 "DFSDM_FLT0CR1," bitfld.long 0x0 30. "AWFSEL,Analog watchdog fast mode select" "0: Analog watchdog on data output value (after the..,1: Analog watchdog on channel transceivers value.." bitfld.long 0x0 29. "FAST,Fast conversion mode selection for regular conversions" "0: Fast conversion mode disabled,1: Fast conversion mode enabled" newline bitfld.long 0x0 24.--25. "RCH,Regular channel selection" "0: Channel 0 is selected as the regular channel,1: Channel 1 is selected as the regular channel,?,3: Chanel 3 is selected as the regular channel" bitfld.long 0x0 21. "RDMAEN,DMA channel enabled to read data for the regular conversion" "0: The DMA channel is not enabled to read regular..,1: The DMA channel is enabled to read regular data" newline bitfld.long 0x0 19. "RSYNC,Launch regular conversion synchronously with DFSDM_FLT0" "0: Do not launch a regular conversion synchronously..,1: Launch a regular conversion in this DFSDM_FLTx.." bitfld.long 0x0 18. "RCONT,Continuous mode selection for regular conversions" "0: The regular channel is converted just once for..,1: The regular channel is converted repeatedly.." newline bitfld.long 0x0 17. "RSWSTART,Software start of a conversion on the regular channel" "0: Writing '0’ has no effect,1: Writing '1’ makes a request to start a.." bitfld.long 0x0 13.--14. "JEXTEN,Trigger enable and trigger edge selection for injected conversions" "0: Trigger detection is disabled,1: Each rising edge on the selected trigger makes a..,2: Each falling edge on the selected trigger makes..,3: Both rising edges and falling edges on the.." newline hexmask.long.byte 0x0 8.--12. 1. "JEXTSEL,Trigger signal selection for launching injected conversions" bitfld.long 0x0 5. "JDMAEN,DMA channel enabled to read data for the injected channel group" "0: The DMA channel is not enabled to read injected..,1: The DMA channel is enabled to read injected data" newline bitfld.long 0x0 4. "JSCAN,Scanning conversion mode for injected conversions" "0: One channel conversion is performed from the..,1: The series of conversions for the injected group.." bitfld.long 0x0 3. "JSYNC,Launch an injected conversion synchronously with the DFSDM_FLT0 JSWSTART trigger" "0: Do not launch an injected conversion..,1: Launch an injected conversion in this DFSDM_FLTx.." newline bitfld.long 0x0 1. "JSWSTART,Start a conversion of the injected group of channels" "0: Writing '0’ has no effect.,1: Writing '1’ makes a request to convert the.." bitfld.long 0x0 0. "DFEN,DFSDM_FLTx enable" "0: register DFSDM_FLTxISR is set to the reset state,1: DFSDM_FLTx is enabled. If DFSDM_FLTx is enabled.." line.long 0x4 "DFSDM_FLT0CR2," hexmask.long.byte 0x4 16.--19. 1. "AWDCH,Analog watchdog channel selection" hexmask.long.byte 0x4 8.--11. 1. "EXCH,Extremes detector channel selection" newline bitfld.long 0x4 6. "CKABIE,Clock absence interrupt enable" "0: Detection of channel input clock absence..,1: Detection of channel input clock absence.." bitfld.long 0x4 5. "SCDIE,Short-circuit detector interrupt enable" "0: short-circuit detector interrupt is disabled,1: short-circuit detector interrupt is enabled" newline bitfld.long 0x4 4. "AWDIE,Analog watchdog interrupt enable" "0: Analog watchdog interrupt is disabled,1: Analog watchdog interrupt is enabled" bitfld.long 0x4 3. "ROVRIE,Regular data overrun interrupt enable" "0: Regular data overrun interrupt is disabled,1: Regular data overrun interrupt is enabled" newline bitfld.long 0x4 2. "JOVRIE,Injected data overrun interrupt enable" "0: Injected data overrun interrupt is disabled,1: Injected data overrun interrupt is enabled" bitfld.long 0x4 1. "REOCIE,Regular end of conversion interrupt enable" "0: Regular end of conversion interrupt is disabled,1: Regular end of conversion interrupt is enabled" newline bitfld.long 0x4 0. "JEOCIE,Injected end of conversion interrupt enable" "0: Injected end of conversion interrupt is disabled,1: Injected end of conversion interrupt is enabled" rgroup.long 0x108++0x3 line.long 0x0 "DFSDM_FLT0ISR," hexmask.long.byte 0x0 24.--27. 1. "SCDF,short-circuit detector flag" hexmask.long.byte 0x0 16.--19. 1. "CKABF,Clock absence flag" newline bitfld.long 0x0 14. "RCIP,Regular conversion in progress status" "0: No request to convert the regular channel has..,1: The conversion of the regular channel is in.." bitfld.long 0x0 13. "JCIP,Injected conversion in progress status" "0: No request to convert the injected channel group..,1: The conversion of the injected channel group is.." newline bitfld.long 0x0 4. "AWDF,Analog watchdog" "0: No Analog watchdog event occurred,1: The analog watchdog block detected voltage which.." bitfld.long 0x0 3. "ROVRF,Regular conversion overrun flag" "0: No regular conversion overrun has occurred,1: A regular conversion overrun has occurred which.." newline bitfld.long 0x0 2. "JOVRF,Injected conversion overrun flag" "0: No injected conversion overrun has occurred,1: An injected conversion overrun has occurred.." bitfld.long 0x0 1. "REOCF,End of regular conversion flag" "0: No regular conversion has completed,1: A regular conversion has completed and its data.." newline bitfld.long 0x0 0. "JEOCF,End of injected conversion flag" "0: No injected conversion has completed,1: An injected conversion has completed and its.." group.long 0x10C++0xB line.long 0x0 "DFSDM_FLT0ICR," hexmask.long.byte 0x0 24.--27. 1. "CLRSCDF,Clear the short-circuit detector flag" hexmask.long.byte 0x0 16.--19. 1. "CLRCKABF,Clear the clock absence flag" newline bitfld.long 0x0 3. "CLRROVRF,Clear the regular conversion overrun flag" "0: Writing '0’ has no effect,1: Writing '1’ clears the ROVRF bit in the.." bitfld.long 0x0 2. "CLRJOVRF,Clear the injected conversion overrun flag" "0: Writing '0’ has no effect,1: Writing '1’ clears the JOVRF bit in the.." line.long 0x4 "DFSDM_FLT0JCHGR," hexmask.long.byte 0x4 0.--3. 1. "JCHG,Injected channel group selection" line.long 0x8 "DFSDM_FLT0FCR," bitfld.long 0x8 29.--31. "FORD,Sinc filter order" "0: FastSinc filter type,1: Sinc1 filter type,2: Sinc2 filter type,3: Sinc3 filter type,4: Sinc4 filter type,5: Sinc5 filter type,?,?" hexmask.long.word 0x8 16.--25. 1. "FOSR,Sinc filter oversampling ratio (decimation rate)" newline hexmask.long.byte 0x8 0.--7. 1. "IOSR,Integrator oversampling ratio (averaging length)" rgroup.long 0x118++0x7 line.long 0x0 "DFSDM_FLT0JDATAR," hexmask.long.tbyte 0x0 8.--31. 1. "JDATA,Injected group conversion data" bitfld.long 0x0 0.--1. "JDATACH,Injected channel most recently converted" "0,1,2,3" line.long 0x4 "DFSDM_FLT0RDATAR," hexmask.long.tbyte 0x4 8.--31. 1. "RDATA,Regular channel conversion data" bitfld.long 0x4 4. "RPEND,Regular channel pending data" "0,1" newline bitfld.long 0x4 0.--1. "RDATACH,Regular channel most recently converted" "0,1,2,3" group.long 0x120++0x7 line.long 0x0 "DFSDM_FLT0AWHTR," hexmask.long.tbyte 0x0 8.--31. 1. "AWHT,Analog watchdog high threshold" hexmask.long.byte 0x0 0.--3. 1. "BKAWH,Break signal assignment to analog watchdog high threshold event" line.long 0x4 "DFSDM_FLT0AWLTR," hexmask.long.tbyte 0x4 8.--31. 1. "AWLT,Analog watchdog low threshold" hexmask.long.byte 0x4 0.--3. 1. "BKAWL,Break signal assignment to analog watchdog low threshold event" rgroup.long 0x128++0x3 line.long 0x0 "DFSDM_FLT0AWSR," hexmask.long.byte 0x0 8.--11. 1. "AWHTF,Analog watchdog high threshold flag" hexmask.long.byte 0x0 0.--3. 1. "AWLTF,Analog watchdog low threshold flag" group.long 0x12C++0x3 line.long 0x0 "DFSDM_FLT0AWCFR," hexmask.long.byte 0x0 8.--11. 1. "CLRAWHTF,Clear the analog watchdog high threshold flag" hexmask.long.byte 0x0 0.--3. 1. "CLRAWLTF,Clear the analog watchdog low threshold flag" rgroup.long 0x130++0x3 line.long 0x0 "DFSDM_FLT0EXMAX," hexmask.long.tbyte 0x0 8.--31. 1. "EXMAX,Extremes detector maximum value" bitfld.long 0x0 0.--1. "EXMAXCH,Extremes detector maximum data channel." "0,1,2,3" group.long 0x134++0x3 line.long 0x0 "DFSDM_FLT0EXMIN," hexmask.long.tbyte 0x0 8.--31. 1. "EXMIN,Extremes detector minimum value" rbitfld.long 0x0 0.--1. "EXMINCH,Extremes detector minimum data channel" "0,1,2,3" rgroup.long 0x138++0x3 line.long 0x0 "DFSDM_FLT0CNVTIMR," hexmask.long 0x0 4.--31. 1. "CNVCNT,28-bit timer counting conversion time t = CNVCNT[27:0] / fDFSDMCLK" group.long 0x180++0x7 line.long 0x0 "DFSDM_FLT1CR1," bitfld.long 0x0 30. "AWFSEL,Analog watchdog fast mode select" "0: Analog watchdog on data output value (after the..,1: Analog watchdog on channel transceivers value.." bitfld.long 0x0 29. "FAST,Fast conversion mode selection for regular conversions" "0: Fast conversion mode disabled,1: Fast conversion mode enabled" newline bitfld.long 0x0 24.--25. "RCH,Regular channel selection" "0: Channel 0 is selected as the regular channel,1: Channel 1 is selected as the regular channel,?,3: Chanel 3 is selected as the regular channel" bitfld.long 0x0 21. "RDMAEN,DMA channel enabled to read data for the regular conversion" "0: The DMA channel is not enabled to read regular..,1: The DMA channel is enabled to read regular data" newline bitfld.long 0x0 19. "RSYNC,Launch regular conversion synchronously with DFSDM_FLT0" "0: Do not launch a regular conversion synchronously..,1: Launch a regular conversion in this DFSDM_FLTx.." bitfld.long 0x0 18. "RCONT,Continuous mode selection for regular conversions" "0: The regular channel is converted just once for..,1: The regular channel is converted repeatedly.." newline bitfld.long 0x0 17. "RSWSTART,Software start of a conversion on the regular channel" "0: Writing '0’ has no effect,1: Writing '1’ makes a request to start a.." bitfld.long 0x0 13.--14. "JEXTEN,Trigger enable and trigger edge selection for injected conversions" "0: Trigger detection is disabled,1: Each rising edge on the selected trigger makes a..,2: Each falling edge on the selected trigger makes..,3: Both rising edges and falling edges on the.." newline hexmask.long.byte 0x0 8.--12. 1. "JEXTSEL,Trigger signal selection for launching injected conversions" bitfld.long 0x0 5. "JDMAEN,DMA channel enabled to read data for the injected channel group" "0: The DMA channel is not enabled to read injected..,1: The DMA channel is enabled to read injected data" newline bitfld.long 0x0 4. "JSCAN,Scanning conversion mode for injected conversions" "0: One channel conversion is performed from the..,1: The series of conversions for the injected group.." bitfld.long 0x0 3. "JSYNC,Launch an injected conversion synchronously with the DFSDM_FLT0 JSWSTART trigger" "0: Do not launch an injected conversion..,1: Launch an injected conversion in this DFSDM_FLTx.." newline bitfld.long 0x0 1. "JSWSTART,Start a conversion of the injected group of channels" "0: Writing '0’ has no effect.,1: Writing '1’ makes a request to convert the.." bitfld.long 0x0 0. "DFEN,DFSDM_FLTx enable" "0: register DFSDM_FLTxISR is set to the reset state,1: DFSDM_FLTx is enabled. If DFSDM_FLTx is enabled.." line.long 0x4 "DFSDM_FLT1CR2," hexmask.long.byte 0x4 16.--19. 1. "AWDCH,Analog watchdog channel selection" hexmask.long.byte 0x4 8.--11. 1. "EXCH,Extremes detector channel selection" newline bitfld.long 0x4 6. "CKABIE,Clock absence interrupt enable" "0: Detection of channel input clock absence..,1: Detection of channel input clock absence.." bitfld.long 0x4 5. "SCDIE,Short-circuit detector interrupt enable" "0: short-circuit detector interrupt is disabled,1: short-circuit detector interrupt is enabled" newline bitfld.long 0x4 4. "AWDIE,Analog watchdog interrupt enable" "0: Analog watchdog interrupt is disabled,1: Analog watchdog interrupt is enabled" bitfld.long 0x4 3. "ROVRIE,Regular data overrun interrupt enable" "0: Regular data overrun interrupt is disabled,1: Regular data overrun interrupt is enabled" newline bitfld.long 0x4 2. "JOVRIE,Injected data overrun interrupt enable" "0: Injected data overrun interrupt is disabled,1: Injected data overrun interrupt is enabled" bitfld.long 0x4 1. "REOCIE,Regular end of conversion interrupt enable" "0: Regular end of conversion interrupt is disabled,1: Regular end of conversion interrupt is enabled" newline bitfld.long 0x4 0. "JEOCIE,Injected end of conversion interrupt enable" "0: Injected end of conversion interrupt is disabled,1: Injected end of conversion interrupt is enabled" rgroup.long 0x188++0x3 line.long 0x0 "DFSDM_FLT1ISR," hexmask.long.byte 0x0 24.--27. 1. "SCDF,short-circuit detector flag" hexmask.long.byte 0x0 16.--19. 1. "CKABF,Clock absence flag" newline bitfld.long 0x0 14. "RCIP,Regular conversion in progress status" "0: No request to convert the regular channel has..,1: The conversion of the regular channel is in.." bitfld.long 0x0 13. "JCIP,Injected conversion in progress status" "0: No request to convert the injected channel group..,1: The conversion of the injected channel group is.." newline bitfld.long 0x0 4. "AWDF,Analog watchdog" "0: No Analog watchdog event occurred,1: The analog watchdog block detected voltage which.." bitfld.long 0x0 3. "ROVRF,Regular conversion overrun flag" "0: No regular conversion overrun has occurred,1: A regular conversion overrun has occurred which.." newline bitfld.long 0x0 2. "JOVRF,Injected conversion overrun flag" "0: No injected conversion overrun has occurred,1: An injected conversion overrun has occurred.." bitfld.long 0x0 1. "REOCF,End of regular conversion flag" "0: No regular conversion has completed,1: A regular conversion has completed and its data.." newline bitfld.long 0x0 0. "JEOCF,End of injected conversion flag" "0: No injected conversion has completed,1: An injected conversion has completed and its.." group.long 0x18C++0xB line.long 0x0 "DFSDM_FLT1ICR," hexmask.long.byte 0x0 24.--27. 1. "CLRSCDF,Clear the short-circuit detector flag" hexmask.long.byte 0x0 16.--19. 1. "CLRCKABF,Clear the clock absence flag" newline bitfld.long 0x0 3. "CLRROVRF,Clear the regular conversion overrun flag" "0: Writing '0’ has no effect,1: Writing '1’ clears the ROVRF bit in the.." bitfld.long 0x0 2. "CLRJOVRF,Clear the injected conversion overrun flag" "0: Writing '0’ has no effect,1: Writing '1’ clears the JOVRF bit in the.." line.long 0x4 "DFSDM_FLT1JCHGR," hexmask.long.byte 0x4 0.--3. 1. "JCHG,Injected channel group selection" line.long 0x8 "DFSDM_FLT1FCR," bitfld.long 0x8 29.--31. "FORD,Sinc filter order" "0: FastSinc filter type,1: Sinc1 filter type,2: Sinc2 filter type,3: Sinc3 filter type,4: Sinc4 filter type,5: Sinc5 filter type,?,?" hexmask.long.word 0x8 16.--25. 1. "FOSR,Sinc filter oversampling ratio (decimation rate)" newline hexmask.long.byte 0x8 0.--7. 1. "IOSR,Integrator oversampling ratio (averaging length)" rgroup.long 0x198++0x7 line.long 0x0 "DFSDM_FLT1JDATAR," hexmask.long.tbyte 0x0 8.--31. 1. "JDATA,Injected group conversion data" bitfld.long 0x0 0.--1. "JDATACH,Injected channel most recently converted" "0,1,2,3" line.long 0x4 "DFSDM_FLT1RDATAR," hexmask.long.tbyte 0x4 8.--31. 1. "RDATA,Regular channel conversion data" bitfld.long 0x4 4. "RPEND,Regular channel pending data" "0,1" newline bitfld.long 0x4 0.--1. "RDATACH,Regular channel most recently converted" "0,1,2,3" group.long 0x1A0++0x7 line.long 0x0 "DFSDM_FLT1AWHTR," hexmask.long.tbyte 0x0 8.--31. 1. "AWHT,Analog watchdog high threshold" hexmask.long.byte 0x0 0.--3. 1. "BKAWH,Break signal assignment to analog watchdog high threshold event" line.long 0x4 "DFSDM_FLT1AWLTR," hexmask.long.tbyte 0x4 8.--31. 1. "AWLT,Analog watchdog low threshold" hexmask.long.byte 0x4 0.--3. 1. "BKAWL,Break signal assignment to analog watchdog low threshold event" rgroup.long 0x1A8++0x3 line.long 0x0 "DFSDM_FLT1AWSR," hexmask.long.byte 0x0 8.--11. 1. "AWHTF,Analog watchdog high threshold flag" hexmask.long.byte 0x0 0.--3. 1. "AWLTF,Analog watchdog low threshold flag" group.long 0x1AC++0x3 line.long 0x0 "DFSDM_FLT1AWCFR," hexmask.long.byte 0x0 8.--11. 1. "CLRAWHTF,Clear the analog watchdog high threshold flag" hexmask.long.byte 0x0 0.--3. 1. "CLRAWLTF,Clear the analog watchdog low threshold flag" rgroup.long 0x1B0++0x3 line.long 0x0 "DFSDM_FLT1EXMAX," hexmask.long.tbyte 0x0 8.--31. 1. "EXMAX,Extremes detector maximum value" bitfld.long 0x0 0.--1. "EXMAXCH,Extremes detector maximum data channel." "0,1,2,3" group.long 0x1B4++0x3 line.long 0x0 "DFSDM_FLT1EXMIN," hexmask.long.tbyte 0x0 8.--31. 1. "EXMIN,Extremes detector minimum value" rbitfld.long 0x0 0.--1. "EXMINCH,Extremes detector minimum data channel" "0,1,2,3" rgroup.long 0x1B8++0x3 line.long 0x0 "DFSDM_FLT1CNVTIMR," hexmask.long 0x0 4.--31. 1. "CNVCNT,28-bit timer counting conversion time t = CNVCNT[27:0] / fDFSDMCLK" rgroup.long 0x7F0++0xF line.long 0x0 "DFSDM_HWCFGR,DFSDM hardware configuration register" hexmask.long.byte 0x0 8.--15. 1. "NBF,Number of implemented filters" hexmask.long.byte 0x0 0.--7. 1. "NBT,Number of implemented transceivers" line.long 0x4 "DFSDM_VERR,DFSDM version register" hexmask.long.byte 0x4 4.--7. 1. "MAJREV,Major revision of the DFSDM peripheral" hexmask.long.byte 0x4 0.--3. 1. "MINREV,Minor revision of the DFSDM peripheral" line.long 0x8 "DFSDM_IPIDR,DFSDM identification register" hexmask.long 0x8 0.--31. 1. "ID,Peripheral identifier" line.long 0xC "DFSDM_SIDR,DFSDM size identification register" hexmask.long 0xC 0.--31. 1. "SID,Size identification of DFSDM peripheral" tree.end endif sif (cpuis("STM32MP151*")||cpuis("STM32MP153*")||cpuis("STM32MP157*")) tree "DFSDM1" base ad:0x4400D000 group.long 0x0++0xB line.long 0x0 "DFSDM_CH0CFGR1,This register specifies the parameters used by channel y." bitfld.long 0x0 31. "DFSDMEN,DFSDMEN" "0,1" bitfld.long 0x0 30. "CKOUTSRC,CKOUTSRC" "0,1" hexmask.long.byte 0x0 16.--23. 1. "CKOUTDIV,CKOUTDIV" bitfld.long 0x0 14.--15. "DATPACK,DATPACK" "0,1,2,3" bitfld.long 0x0 12.--13. "DATMPX,DATMPX" "0,1,2,3" bitfld.long 0x0 8. "CHINSEL,CHINSEL" "0,1" bitfld.long 0x0 7. "CHEN,CHEN" "0,1" bitfld.long 0x0 6. "CKABEN,CKABEN" "0,1" newline bitfld.long 0x0 5. "SCDEN,SCDEN" "0,1" bitfld.long 0x0 2.--3. "SPICKSEL,SPICKSEL" "0,1,2,3" bitfld.long 0x0 0.--1. "SITP,SITP" "0,1,2,3" line.long 0x4 "DFSDM_CH0CFGR2,This register specifies the parameters used by channel y." hexmask.long.tbyte 0x4 8.--31. 1. "OFFSET,OFFSET" hexmask.long.byte 0x4 3.--7. 1. "DTRBS,DTRBS" line.long 0x8 "DFSDM_CH0AWSCDR,Short-circuit detector and analog watchdog settings for channel y." bitfld.long 0x8 22.--23. "AWFORD,AWFORD" "0,1,2,3" hexmask.long.byte 0x8 16.--20. 1. "AWFOSR,AWFOSR" hexmask.long.byte 0x8 12.--15. 1. "BKSCD,BKSCD" hexmask.long.byte 0x8 0.--7. 1. "SCDT,SCDT" rgroup.long 0xC++0x3 line.long 0x0 "DFSDM_CH0WDATR,This register contains the data resulting from the analog watchdog filter associated to the input channel y." hexmask.long.word 0x0 0.--15. 1. "WDATA,WDATA" group.long 0x10++0x7 line.long 0x0 "DFSDM_CH0DATINR,This register contains 16-bit input data to be processed by DFSDM filter module." hexmask.long.word 0x0 16.--31. 1. "INDAT1,INDAT1" hexmask.long.word 0x0 0.--15. 1. "INDAT0,INDAT0" line.long 0x4 "DFSDM_CH0DLYR,DFSDM channel 0 delay register" hexmask.long.byte 0x4 0.--5. 1. "PLSSKP,PLSSKP" group.long 0x20++0xB line.long 0x0 "DFSDM_CH1CFGR1,This register specifies the parameters used by channel y." bitfld.long 0x0 31. "DFSDMEN,DFSDMEN" "0,1" bitfld.long 0x0 30. "CKOUTSRC,CKOUTSRC" "0,1" hexmask.long.byte 0x0 16.--23. 1. "CKOUTDIV,CKOUTDIV" bitfld.long 0x0 14.--15. "DATPACK,DATPACK" "0,1,2,3" bitfld.long 0x0 12.--13. "DATMPX,DATMPX" "0,1,2,3" bitfld.long 0x0 8. "CHINSEL,CHINSEL" "0,1" bitfld.long 0x0 7. "CHEN,CHEN" "0,1" bitfld.long 0x0 6. "CKABEN,CKABEN" "0,1" newline bitfld.long 0x0 5. "SCDEN,SCDEN" "0,1" bitfld.long 0x0 2.--3. "SPICKSEL,SPICKSEL" "0,1,2,3" bitfld.long 0x0 0.--1. "SITP,SITP" "0,1,2,3" line.long 0x4 "DFSDM_CH1CFGR2,This register specifies the parameters used by channel y." hexmask.long.tbyte 0x4 8.--31. 1. "OFFSET,OFFSET" hexmask.long.byte 0x4 3.--7. 1. "DTRBS,DTRBS" line.long 0x8 "DFSDM_CH1AWSCDR,Short-circuit detector and analog watchdog settings for channel y." bitfld.long 0x8 22.--23. "AWFORD,AWFORD" "0,1,2,3" hexmask.long.byte 0x8 16.--20. 1. "AWFOSR,AWFOSR" hexmask.long.byte 0x8 12.--15. 1. "BKSCD,BKSCD" hexmask.long.byte 0x8 0.--7. 1. "SCDT,SCDT" rgroup.long 0x2C++0x3 line.long 0x0 "DFSDM_CH1WDATR,This register contains the data resulting from the analog watchdog filter associated to the input channel y." hexmask.long.word 0x0 0.--15. 1. "WDATA,WDATA" group.long 0x30++0x7 line.long 0x0 "DFSDM_CH1DATINR,This register contains 16-bit input data to be processed by DFSDM filter module." hexmask.long.word 0x0 16.--31. 1. "INDAT1,INDAT1" hexmask.long.word 0x0 0.--15. 1. "INDAT0,INDAT0" line.long 0x4 "DFSDM_CH1DLYR,DFSDM channel 1 delay register" hexmask.long.byte 0x4 0.--5. 1. "PLSSKP,PLSSKP" group.long 0x40++0xB line.long 0x0 "DFSDM_CH2CFGR1,This register specifies the parameters used by channel y." bitfld.long 0x0 31. "DFSDMEN,DFSDMEN" "0,1" bitfld.long 0x0 30. "CKOUTSRC,CKOUTSRC" "0,1" hexmask.long.byte 0x0 16.--23. 1. "CKOUTDIV,CKOUTDIV" bitfld.long 0x0 14.--15. "DATPACK,DATPACK" "0,1,2,3" bitfld.long 0x0 12.--13. "DATMPX,DATMPX" "0,1,2,3" bitfld.long 0x0 8. "CHINSEL,CHINSEL" "0,1" bitfld.long 0x0 7. "CHEN,CHEN" "0,1" bitfld.long 0x0 6. "CKABEN,CKABEN" "0,1" newline bitfld.long 0x0 5. "SCDEN,SCDEN" "0,1" bitfld.long 0x0 2.--3. "SPICKSEL,SPICKSEL" "0,1,2,3" bitfld.long 0x0 0.--1. "SITP,SITP" "0,1,2,3" line.long 0x4 "DFSDM_CH2CFGR2,This register specifies the parameters used by channel y." hexmask.long.tbyte 0x4 8.--31. 1. "OFFSET,OFFSET" hexmask.long.byte 0x4 3.--7. 1. "DTRBS,DTRBS" line.long 0x8 "DFSDM_CH2AWSCDR,Short-circuit detector and analog watchdog settings for channel y." bitfld.long 0x8 22.--23. "AWFORD,AWFORD" "0,1,2,3" hexmask.long.byte 0x8 16.--20. 1. "AWFOSR,AWFOSR" hexmask.long.byte 0x8 12.--15. 1. "BKSCD,BKSCD" hexmask.long.byte 0x8 0.--7. 1. "SCDT,SCDT" rgroup.long 0x4C++0x3 line.long 0x0 "DFSDM_CH2WDATR,This register contains the data resulting from the analog watchdog filter associated to the input channel y." hexmask.long.word 0x0 0.--15. 1. "WDATA,WDATA" group.long 0x50++0x7 line.long 0x0 "DFSDM_CH2DATINR,This register contains 16-bit input data to be processed by DFSDM filter module." hexmask.long.word 0x0 16.--31. 1. "INDAT1,INDAT1" hexmask.long.word 0x0 0.--15. 1. "INDAT0,INDAT0" line.long 0x4 "DFSDM_CH2DLYR,DFSDM channel 2 delay register" hexmask.long.byte 0x4 0.--5. 1. "PLSSKP,PLSSKP" group.long 0x60++0xB line.long 0x0 "DFSDM_CH3CFGR1,This register specifies the parameters used by channel y." bitfld.long 0x0 31. "DFSDMEN,DFSDMEN" "0,1" bitfld.long 0x0 30. "CKOUTSRC,CKOUTSRC" "0,1" hexmask.long.byte 0x0 16.--23. 1. "CKOUTDIV,CKOUTDIV" bitfld.long 0x0 14.--15. "DATPACK,DATPACK" "0,1,2,3" bitfld.long 0x0 12.--13. "DATMPX,DATMPX" "0,1,2,3" bitfld.long 0x0 8. "CHINSEL,CHINSEL" "0,1" bitfld.long 0x0 7. "CHEN,CHEN" "0,1" bitfld.long 0x0 6. "CKABEN,CKABEN" "0,1" newline bitfld.long 0x0 5. "SCDEN,SCDEN" "0,1" bitfld.long 0x0 2.--3. "SPICKSEL,SPICKSEL" "0,1,2,3" bitfld.long 0x0 0.--1. "SITP,SITP" "0,1,2,3" line.long 0x4 "DFSDM_CH3CFGR2,This register specifies the parameters used by channel y." hexmask.long.tbyte 0x4 8.--31. 1. "OFFSET,OFFSET" hexmask.long.byte 0x4 3.--7. 1. "DTRBS,DTRBS" line.long 0x8 "DFSDM_CH3AWSCDR,Short-circuit detector and analog watchdog settings for channel y." bitfld.long 0x8 22.--23. "AWFORD,AWFORD" "0,1,2,3" hexmask.long.byte 0x8 16.--20. 1. "AWFOSR,AWFOSR" hexmask.long.byte 0x8 12.--15. 1. "BKSCD,BKSCD" hexmask.long.byte 0x8 0.--7. 1. "SCDT,SCDT" rgroup.long 0x6C++0x3 line.long 0x0 "DFSDM_CH3WDATR,This register contains the data resulting from the analog watchdog filter associated to the input channel y." hexmask.long.word 0x0 0.--15. 1. "WDATA,WDATA" group.long 0x70++0x7 line.long 0x0 "DFSDM_CH3DATINR,This register contains 16-bit input data to be processed by DFSDM filter module." hexmask.long.word 0x0 16.--31. 1. "INDAT1,INDAT1" hexmask.long.word 0x0 0.--15. 1. "INDAT0,INDAT0" line.long 0x4 "DFSDM_CH3DLYR,DFSDM channel 3 delay register" hexmask.long.byte 0x4 0.--5. 1. "PLSSKP,PLSSKP" group.long 0x80++0xB line.long 0x0 "DFSDM_CH4CFGR1,This register specifies the parameters used by channel y." bitfld.long 0x0 31. "DFSDMEN,DFSDMEN" "0,1" bitfld.long 0x0 30. "CKOUTSRC,CKOUTSRC" "0,1" hexmask.long.byte 0x0 16.--23. 1. "CKOUTDIV,CKOUTDIV" bitfld.long 0x0 14.--15. "DATPACK,DATPACK" "0,1,2,3" bitfld.long 0x0 12.--13. "DATMPX,DATMPX" "0,1,2,3" bitfld.long 0x0 8. "CHINSEL,CHINSEL" "0,1" bitfld.long 0x0 7. "CHEN,CHEN" "0,1" bitfld.long 0x0 6. "CKABEN,CKABEN" "0,1" newline bitfld.long 0x0 5. "SCDEN,SCDEN" "0,1" bitfld.long 0x0 2.--3. "SPICKSEL,SPICKSEL" "0,1,2,3" bitfld.long 0x0 0.--1. "SITP,SITP" "0,1,2,3" line.long 0x4 "DFSDM_CH4CFGR2,This register specifies the parameters used by channel y." hexmask.long.tbyte 0x4 8.--31. 1. "OFFSET,OFFSET" hexmask.long.byte 0x4 3.--7. 1. "DTRBS,DTRBS" line.long 0x8 "DFSDM_CH4AWSCDR,Short-circuit detector and analog watchdog settings for channel y." bitfld.long 0x8 22.--23. "AWFORD,AWFORD" "0,1,2,3" hexmask.long.byte 0x8 16.--20. 1. "AWFOSR,AWFOSR" hexmask.long.byte 0x8 12.--15. 1. "BKSCD,BKSCD" hexmask.long.byte 0x8 0.--7. 1. "SCDT,SCDT" rgroup.long 0x8C++0x3 line.long 0x0 "DFSDM_CH4WDATR,This register contains the data resulting from the analog watchdog filter associated to the input channel y." hexmask.long.word 0x0 0.--15. 1. "WDATA,WDATA" group.long 0x90++0x7 line.long 0x0 "DFSDM_CH4DATINR,This register contains 16-bit input data to be processed by DFSDM filter module." hexmask.long.word 0x0 16.--31. 1. "INDAT1,INDAT1" hexmask.long.word 0x0 0.--15. 1. "INDAT0,INDAT0" line.long 0x4 "DFSDM_CH4DLYR,DFSDM channel 4 delay register" hexmask.long.byte 0x4 0.--5. 1. "PLSSKP,PLSSKP" group.long 0xA0++0xB line.long 0x0 "DFSDM_CH5CFGR1,This register specifies the parameters used by channel y." bitfld.long 0x0 31. "DFSDMEN,DFSDMEN" "0,1" bitfld.long 0x0 30. "CKOUTSRC,CKOUTSRC" "0,1" hexmask.long.byte 0x0 16.--23. 1. "CKOUTDIV,CKOUTDIV" bitfld.long 0x0 14.--15. "DATPACK,DATPACK" "0,1,2,3" bitfld.long 0x0 12.--13. "DATMPX,DATMPX" "0,1,2,3" bitfld.long 0x0 8. "CHINSEL,CHINSEL" "0,1" bitfld.long 0x0 7. "CHEN,CHEN" "0,1" bitfld.long 0x0 6. "CKABEN,CKABEN" "0,1" newline bitfld.long 0x0 5. "SCDEN,SCDEN" "0,1" bitfld.long 0x0 2.--3. "SPICKSEL,SPICKSEL" "0,1,2,3" bitfld.long 0x0 0.--1. "SITP,SITP" "0,1,2,3" line.long 0x4 "DFSDM_CH5CFGR2,This register specifies the parameters used by channel y." hexmask.long.tbyte 0x4 8.--31. 1. "OFFSET,OFFSET" hexmask.long.byte 0x4 3.--7. 1. "DTRBS,DTRBS" line.long 0x8 "DFSDM_CH5AWSCDR,Short-circuit detector and analog watchdog settings for channel y." bitfld.long 0x8 22.--23. "AWFORD,AWFORD" "0,1,2,3" hexmask.long.byte 0x8 16.--20. 1. "AWFOSR,AWFOSR" hexmask.long.byte 0x8 12.--15. 1. "BKSCD,BKSCD" hexmask.long.byte 0x8 0.--7. 1. "SCDT,SCDT" rgroup.long 0xAC++0x3 line.long 0x0 "DFSDM_CH5WDATR,This register contains the data resulting from the analog watchdog filter associated to the input channel y." hexmask.long.word 0x0 0.--15. 1. "WDATA,WDATA" group.long 0xB0++0x7 line.long 0x0 "DFSDM_CH5DATINR,This register contains 16-bit input data to be processed by DFSDM filter module." hexmask.long.word 0x0 16.--31. 1. "INDAT1,INDAT1" hexmask.long.word 0x0 0.--15. 1. "INDAT0,INDAT0" line.long 0x4 "DFSDM_CH5DLYR,DFSDM channel 5 delay register" hexmask.long.byte 0x4 0.--5. 1. "PLSSKP,PLSSKP" group.long 0xC0++0xB line.long 0x0 "DFSDM_CH6CFGR1,This register specifies the parameters used by channel y." bitfld.long 0x0 31. "DFSDMEN,DFSDMEN" "0,1" bitfld.long 0x0 30. "CKOUTSRC,CKOUTSRC" "0,1" hexmask.long.byte 0x0 16.--23. 1. "CKOUTDIV,CKOUTDIV" bitfld.long 0x0 14.--15. "DATPACK,DATPACK" "0,1,2,3" bitfld.long 0x0 12.--13. "DATMPX,DATMPX" "0,1,2,3" bitfld.long 0x0 8. "CHINSEL,CHINSEL" "0,1" bitfld.long 0x0 7. "CHEN,CHEN" "0,1" bitfld.long 0x0 6. "CKABEN,CKABEN" "0,1" newline bitfld.long 0x0 5. "SCDEN,SCDEN" "0,1" bitfld.long 0x0 2.--3. "SPICKSEL,SPICKSEL" "0,1,2,3" bitfld.long 0x0 0.--1. "SITP,SITP" "0,1,2,3" line.long 0x4 "DFSDM_CH6CFGR2,This register specifies the parameters used by channel y." hexmask.long.tbyte 0x4 8.--31. 1. "OFFSET,OFFSET" hexmask.long.byte 0x4 3.--7. 1. "DTRBS,DTRBS" line.long 0x8 "DFSDM_CH6AWSCDR,Short-circuit detector and analog watchdog settings for channel y." bitfld.long 0x8 22.--23. "AWFORD,AWFORD" "0,1,2,3" hexmask.long.byte 0x8 16.--20. 1. "AWFOSR,AWFOSR" hexmask.long.byte 0x8 12.--15. 1. "BKSCD,BKSCD" hexmask.long.byte 0x8 0.--7. 1. "SCDT,SCDT" rgroup.long 0xCC++0x3 line.long 0x0 "DFSDM_CH6WDATR,This register contains the data resulting from the analog watchdog filter associated to the input channel y." hexmask.long.word 0x0 0.--15. 1. "WDATA,WDATA" group.long 0xD0++0x7 line.long 0x0 "DFSDM_CH6DATINR,This register contains 16-bit input data to be processed by DFSDM filter module." hexmask.long.word 0x0 16.--31. 1. "INDAT1,INDAT1" hexmask.long.word 0x0 0.--15. 1. "INDAT0,INDAT0" line.long 0x4 "DFSDM_CH6DLYR,DFSDM channel 6 delay register" hexmask.long.byte 0x4 0.--5. 1. "PLSSKP,PLSSKP" group.long 0xE0++0xB line.long 0x0 "DFSDM_CH7CFGR1,This register specifies the parameters used by channel y." bitfld.long 0x0 31. "DFSDMEN,DFSDMEN" "0,1" bitfld.long 0x0 30. "CKOUTSRC,CKOUTSRC" "0,1" hexmask.long.byte 0x0 16.--23. 1. "CKOUTDIV,CKOUTDIV" bitfld.long 0x0 14.--15. "DATPACK,DATPACK" "0,1,2,3" bitfld.long 0x0 12.--13. "DATMPX,DATMPX" "0,1,2,3" bitfld.long 0x0 8. "CHINSEL,CHINSEL" "0,1" bitfld.long 0x0 7. "CHEN,CHEN" "0,1" bitfld.long 0x0 6. "CKABEN,CKABEN" "0,1" newline bitfld.long 0x0 5. "SCDEN,SCDEN" "0,1" bitfld.long 0x0 2.--3. "SPICKSEL,SPICKSEL" "0,1,2,3" bitfld.long 0x0 0.--1. "SITP,SITP" "0,1,2,3" line.long 0x4 "DFSDM_CH7CFGR2,This register specifies the parameters used by channel y." hexmask.long.tbyte 0x4 8.--31. 1. "OFFSET,OFFSET" hexmask.long.byte 0x4 3.--7. 1. "DTRBS,DTRBS" line.long 0x8 "DFSDM_CH7AWSCDR,Short-circuit detector and analog watchdog settings for channel y." bitfld.long 0x8 22.--23. "AWFORD,AWFORD" "0,1,2,3" hexmask.long.byte 0x8 16.--20. 1. "AWFOSR,AWFOSR" hexmask.long.byte 0x8 12.--15. 1. "BKSCD,BKSCD" hexmask.long.byte 0x8 0.--7. 1. "SCDT,SCDT" rgroup.long 0xEC++0x3 line.long 0x0 "DFSDM_CH7WDATR,This register contains the data resulting from the analog watchdog filter associated to the input channel y." hexmask.long.word 0x0 0.--15. 1. "WDATA,WDATA" group.long 0xF0++0x7 line.long 0x0 "DFSDM_CH7DATINR,This register contains 16-bit input data to be processed by DFSDM filter module." hexmask.long.word 0x0 16.--31. 1. "INDAT1,INDAT1" hexmask.long.word 0x0 0.--15. 1. "INDAT0,INDAT0" line.long 0x4 "DFSDM_CH7DLYR,DFSDM channel 7 delay register" hexmask.long.byte 0x4 0.--5. 1. "PLSSKP,PLSSKP" group.long 0x100++0x7 line.long 0x0 "DFSDM_FLT0CR1,DFSDM filter 0 control register 1" bitfld.long 0x0 30. "AWFSEL,AWFSEL" "0,1" bitfld.long 0x0 29. "FAST,FAST" "0,1" bitfld.long 0x0 24.--26. "RCH,RCH" "0,1,2,3,4,5,6,7" bitfld.long 0x0 21. "RDMAEN,RDMAEN" "0,1" bitfld.long 0x0 19. "RSYNC,RSYNC" "0,1" bitfld.long 0x0 18. "RCONT,RCONT" "0,1" bitfld.long 0x0 17. "RSWSTART,RSWSTART" "0,1" bitfld.long 0x0 13.--14. "JEXTEN,JEXTEN" "0,1,2,3" newline hexmask.long.byte 0x0 8.--12. 1. "JEXTSEL,JEXTSEL" bitfld.long 0x0 5. "JDMAEN,JDMAEN" "0,1" bitfld.long 0x0 4. "JSCAN,JSCAN" "0,1" bitfld.long 0x0 3. "JSYNC,JSYNC" "0,1" bitfld.long 0x0 1. "JSWSTART,JSWSTART" "0,1" bitfld.long 0x0 0. "DFEN,DFEN" "0,1" line.long 0x4 "DFSDM_FLT0CR2,DFSDM filter 0 control register 2" hexmask.long.byte 0x4 16.--23. 1. "AWDCH,AWDCH" hexmask.long.byte 0x4 8.--15. 1. "EXCH,EXCH" bitfld.long 0x4 6. "CKABIE,CKABIE" "0,1" bitfld.long 0x4 5. "SCDIE,SCDIE" "0,1" bitfld.long 0x4 4. "AWDIE,AWDIE" "0,1" bitfld.long 0x4 3. "ROVRIE,ROVRIE" "0,1" bitfld.long 0x4 2. "JOVRIE,JOVRIE" "0,1" bitfld.long 0x4 1. "REOCIE,REOCIE" "0,1" newline bitfld.long 0x4 0. "JEOCIE,JEOCIE" "0,1" rgroup.long 0x108++0x3 line.long 0x0 "DFSDM_FLT0ISR,DFSDM filter 0 interrupt and status register" hexmask.long.byte 0x0 24.--31. 1. "SCDF,SCDF" hexmask.long.byte 0x0 16.--23. 1. "CKABF,CKABF" bitfld.long 0x0 14. "RCIP,RCIP" "0,1" bitfld.long 0x0 13. "JCIP,JCIP" "0,1" bitfld.long 0x0 4. "AWDF,AWDF" "0,1" bitfld.long 0x0 3. "ROVRF,ROVRF" "0,1" bitfld.long 0x0 2. "JOVRF,JOVRF" "0,1" bitfld.long 0x0 1. "REOCF,REOCF" "0,1" newline bitfld.long 0x0 0. "JEOCF,JEOCF" "0,1" group.long 0x10C++0xB line.long 0x0 "DFSDM_FLT0ICR,DFSDM filter 0 interrupt flag clear register" hexmask.long.byte 0x0 24.--31. 1. "CLRSCDF,CLRSCDF" hexmask.long.byte 0x0 16.--23. 1. "CLRCKABF,CLRCKABF" bitfld.long 0x0 3. "CLRROVRF,CLRROVRF" "0,1" bitfld.long 0x0 2. "CLRJOVRF,CLRJOVRF" "0,1" line.long 0x4 "DFSDM_FLT0JCHGR,DFSDM filter 0 injected channel group selection register" hexmask.long.byte 0x4 0.--7. 1. "JCHG,JCHG" line.long 0x8 "DFSDM_FLT0FCR,DFSDM filter 0 control register" bitfld.long 0x8 29.--31. "FORD,FORD" "0,1,2,3,4,5,6,7" hexmask.long.word 0x8 16.--25. 1. "FOSR,FOSR" hexmask.long.byte 0x8 0.--7. 1. "IOSR,IOSR" rgroup.long 0x118++0x7 line.long 0x0 "DFSDM_FLT0JDATAR,DFSDM filter 0 data register for injected group" hexmask.long.tbyte 0x0 8.--31. 1. "JDATA,JDATA" bitfld.long 0x0 0.--2. "JDATACH,JDATACH" "0,1,2,3,4,5,6,7" line.long 0x4 "DFSDM_FLT0RDATAR,DFSDM filter 0 data register for the regular channel" hexmask.long.tbyte 0x4 8.--31. 1. "RDATA,RDATA" bitfld.long 0x4 4. "RPEND,RPEND" "0,1" bitfld.long 0x4 0.--2. "RDATACH,RDATACH" "0,1,2,3,4,5,6,7" group.long 0x120++0x7 line.long 0x0 "DFSDM_FLT0AWHTR,DFSDM filter 0 analog watchdog high threshold register" hexmask.long.tbyte 0x0 8.--31. 1. "AWHT,AWHT" hexmask.long.byte 0x0 0.--3. 1. "BKAWH,BKAWH" line.long 0x4 "DFSDM_FLT0AWLTR,DFSDM filter 0 analog watchdog low threshold register" hexmask.long.tbyte 0x4 8.--31. 1. "AWLT,AWLT" hexmask.long.byte 0x4 0.--3. 1. "BKAWL,BKAWL" rgroup.long 0x128++0x3 line.long 0x0 "DFSDM_FLT0AWSR,DFSDM filter 0 analog watchdog status register" hexmask.long.byte 0x0 8.--15. 1. "AWHTF,AWHTF" hexmask.long.byte 0x0 0.--7. 1. "AWLTF,AWLTF" group.long 0x12C++0x3 line.long 0x0 "DFSDM_FLT0AWCFR,DFSDM filter 0 analog watchdog clear flag register" hexmask.long.byte 0x0 8.--15. 1. "CLRAWHTF,CLRAWHTF" hexmask.long.byte 0x0 0.--7. 1. "CLRAWLTF,CLRAWLTF" rgroup.long 0x130++0x3 line.long 0x0 "DFSDM_FLT0EXMAX,DFSDM filter 0 extremes detector maximum register" hexmask.long.tbyte 0x0 8.--31. 1. "EXMAX,EXMAX" bitfld.long 0x0 0.--2. "EXMAXCH,EXMAXCH" "0,1,2,3,4,5,6,7" group.long 0x134++0x3 line.long 0x0 "DFSDM_FLT0EXMIN,DFSDM filter 0 extremes detector minimum register" hexmask.long.tbyte 0x0 8.--31. 1. "EXMIN,EXMIN" rbitfld.long 0x0 0.--2. "EXMINCH,EXMINCH" "0,1,2,3,4,5,6,7" rgroup.long 0x138++0x3 line.long 0x0 "DFSDM_FLT0CNVTIMR,DFSDM filter 0 conversion timer register" hexmask.long 0x0 4.--31. 1. "CNVCNT,CNVCNT" group.long 0x180++0x7 line.long 0x0 "DFSDM_FLT1CR1,DFSDM filter 1 control register 1" bitfld.long 0x0 30. "AWFSEL,AWFSEL" "0,1" bitfld.long 0x0 29. "FAST,FAST" "0,1" bitfld.long 0x0 24.--26. "RCH,RCH" "0,1,2,3,4,5,6,7" bitfld.long 0x0 21. "RDMAEN,RDMAEN" "0,1" bitfld.long 0x0 19. "RSYNC,RSYNC" "0,1" bitfld.long 0x0 18. "RCONT,RCONT" "0,1" bitfld.long 0x0 17. "RSWSTART,RSWSTART" "0,1" bitfld.long 0x0 13.--14. "JEXTEN,JEXTEN" "0,1,2,3" newline hexmask.long.byte 0x0 8.--12. 1. "JEXTSEL,JEXTSEL" bitfld.long 0x0 5. "JDMAEN,JDMAEN" "0,1" bitfld.long 0x0 4. "JSCAN,JSCAN" "0,1" bitfld.long 0x0 3. "JSYNC,JSYNC" "0,1" bitfld.long 0x0 1. "JSWSTART,JSWSTART" "0,1" bitfld.long 0x0 0. "DFEN,DFEN" "0,1" line.long 0x4 "DFSDM_FLT1CR2,DFSDM filter 1 control register 2" hexmask.long.byte 0x4 16.--23. 1. "AWDCH,AWDCH" hexmask.long.byte 0x4 8.--15. 1. "EXCH,EXCH" bitfld.long 0x4 6. "CKABIE,CKABIE" "0,1" bitfld.long 0x4 5. "SCDIE,SCDIE" "0,1" bitfld.long 0x4 4. "AWDIE,AWDIE" "0,1" bitfld.long 0x4 3. "ROVRIE,ROVRIE" "0,1" bitfld.long 0x4 2. "JOVRIE,JOVRIE" "0,1" bitfld.long 0x4 1. "REOCIE,REOCIE" "0,1" newline bitfld.long 0x4 0. "JEOCIE,JEOCIE" "0,1" rgroup.long 0x188++0x3 line.long 0x0 "DFSDM_FLT1ISR,DFSDM filter 1 interrupt and status register" hexmask.long.byte 0x0 24.--31. 1. "SCDF,SCDF" hexmask.long.byte 0x0 16.--23. 1. "CKABF,CKABF" bitfld.long 0x0 14. "RCIP,RCIP" "0,1" bitfld.long 0x0 13. "JCIP,JCIP" "0,1" bitfld.long 0x0 4. "AWDF,AWDF" "0,1" bitfld.long 0x0 3. "ROVRF,ROVRF" "0,1" bitfld.long 0x0 2. "JOVRF,JOVRF" "0,1" bitfld.long 0x0 1. "REOCF,REOCF" "0,1" newline bitfld.long 0x0 0. "JEOCF,JEOCF" "0,1" group.long 0x18C++0xB line.long 0x0 "DFSDM_FLT1ICR,DFSDM filter 1 interrupt flag clear register" hexmask.long.byte 0x0 24.--31. 1. "CLRSCDF,CLRSCDF" hexmask.long.byte 0x0 16.--23. 1. "CLRCKABF,CLRCKABF" bitfld.long 0x0 3. "CLRROVRF,CLRROVRF" "0,1" bitfld.long 0x0 2. "CLRJOVRF,CLRJOVRF" "0,1" line.long 0x4 "DFSDM_FLT1JCHGR,DFSDM filter 1 injected channel group selection register" hexmask.long.byte 0x4 0.--7. 1. "JCHG,JCHG" line.long 0x8 "DFSDM_FLT1FCR,DFSDM filter 1 control register" bitfld.long 0x8 29.--31. "FORD,FORD" "0,1,2,3,4,5,6,7" hexmask.long.word 0x8 16.--25. 1. "FOSR,FOSR" hexmask.long.byte 0x8 0.--7. 1. "IOSR,IOSR" rgroup.long 0x198++0x7 line.long 0x0 "DFSDM_FLT1JDATAR,DFSDM filter 1 data register for injected group" hexmask.long.tbyte 0x0 8.--31. 1. "JDATA,JDATA" bitfld.long 0x0 0.--2. "JDATACH,JDATACH" "0,1,2,3,4,5,6,7" line.long 0x4 "DFSDM_FLT1RDATAR,DFSDM filter 1 data register for the regular channel" hexmask.long.tbyte 0x4 8.--31. 1. "RDATA,RDATA" bitfld.long 0x4 4. "RPEND,RPEND" "0,1" bitfld.long 0x4 0.--2. "RDATACH,RDATACH" "0,1,2,3,4,5,6,7" group.long 0x1A0++0x7 line.long 0x0 "DFSDM_FLT1AWHTR,DFSDM filter 1 analog watchdog high threshold register" hexmask.long.tbyte 0x0 8.--31. 1. "AWHT,AWHT" hexmask.long.byte 0x0 0.--3. 1. "BKAWH,BKAWH" line.long 0x4 "DFSDM_FLT1AWLTR,DFSDM filter 1 analog watchdog low threshold register" hexmask.long.tbyte 0x4 8.--31. 1. "AWLT,AWLT" hexmask.long.byte 0x4 0.--3. 1. "BKAWL,BKAWL" rgroup.long 0x1A8++0x3 line.long 0x0 "DFSDM_FLT1AWSR,DFSDM filter 1 analog watchdog status register" hexmask.long.byte 0x0 8.--15. 1. "AWHTF,AWHTF" hexmask.long.byte 0x0 0.--7. 1. "AWLTF,AWLTF" group.long 0x1AC++0x3 line.long 0x0 "DFSDM_FLT1AWCFR,DFSDM filter 1 analog watchdog clear flag register" hexmask.long.byte 0x0 8.--15. 1. "CLRAWHTF,CLRAWHTF" hexmask.long.byte 0x0 0.--7. 1. "CLRAWLTF,CLRAWLTF" rgroup.long 0x1B0++0x3 line.long 0x0 "DFSDM_FLT1EXMAX,DFSDM filter 1 extremes detector maximum register" hexmask.long.tbyte 0x0 8.--31. 1. "EXMAX,EXMAX" bitfld.long 0x0 0.--2. "EXMAXCH,EXMAXCH" "0,1,2,3,4,5,6,7" group.long 0x1B4++0x3 line.long 0x0 "DFSDM_FLT1EXMIN,DFSDM filter 1 extremes detector minimum register" hexmask.long.tbyte 0x0 8.--31. 1. "EXMIN,EXMIN" rbitfld.long 0x0 0.--2. "EXMINCH,EXMINCH" "0,1,2,3,4,5,6,7" rgroup.long 0x1B8++0x3 line.long 0x0 "DFSDM_FLT1CNVTIMR,DFSDM filter 1 conversion timer register" hexmask.long 0x0 4.--31. 1. "CNVCNT,CNVCNT" group.long 0x200++0x7 line.long 0x0 "DFSDM_FLT2CR1,DFSDM filter 2 control register 1" bitfld.long 0x0 30. "AWFSEL,AWFSEL" "0,1" bitfld.long 0x0 29. "FAST,FAST" "0,1" bitfld.long 0x0 24.--26. "RCH,RCH" "0,1,2,3,4,5,6,7" bitfld.long 0x0 21. "RDMAEN,RDMAEN" "0,1" bitfld.long 0x0 19. "RSYNC,RSYNC" "0,1" bitfld.long 0x0 18. "RCONT,RCONT" "0,1" bitfld.long 0x0 17. "RSWSTART,RSWSTART" "0,1" bitfld.long 0x0 13.--14. "JEXTEN,JEXTEN" "0,1,2,3" newline hexmask.long.byte 0x0 8.--12. 1. "JEXTSEL,JEXTSEL" bitfld.long 0x0 5. "JDMAEN,JDMAEN" "0,1" bitfld.long 0x0 4. "JSCAN,JSCAN" "0,1" bitfld.long 0x0 3. "JSYNC,JSYNC" "0,1" bitfld.long 0x0 1. "JSWSTART,JSWSTART" "0,1" bitfld.long 0x0 0. "DFEN,DFEN" "0,1" line.long 0x4 "DFSDM_FLT2CR2,DFSDM filter 2 control register 2" hexmask.long.byte 0x4 16.--23. 1. "AWDCH,AWDCH" hexmask.long.byte 0x4 8.--15. 1. "EXCH,EXCH" bitfld.long 0x4 6. "CKABIE,CKABIE" "0,1" bitfld.long 0x4 5. "SCDIE,SCDIE" "0,1" bitfld.long 0x4 4. "AWDIE,AWDIE" "0,1" bitfld.long 0x4 3. "ROVRIE,ROVRIE" "0,1" bitfld.long 0x4 2. "JOVRIE,JOVRIE" "0,1" bitfld.long 0x4 1. "REOCIE,REOCIE" "0,1" newline bitfld.long 0x4 0. "JEOCIE,JEOCIE" "0,1" rgroup.long 0x208++0x3 line.long 0x0 "DFSDM_FLT2ISR,DFSDM filter 2 interrupt and status register" hexmask.long.byte 0x0 24.--31. 1. "SCDF,SCDF" hexmask.long.byte 0x0 16.--23. 1. "CKABF,CKABF" bitfld.long 0x0 14. "RCIP,RCIP" "0,1" bitfld.long 0x0 13. "JCIP,JCIP" "0,1" bitfld.long 0x0 4. "AWDF,AWDF" "0,1" bitfld.long 0x0 3. "ROVRF,ROVRF" "0,1" bitfld.long 0x0 2. "JOVRF,JOVRF" "0,1" bitfld.long 0x0 1. "REOCF,REOCF" "0,1" newline bitfld.long 0x0 0. "JEOCF,JEOCF" "0,1" group.long 0x20C++0xB line.long 0x0 "DFSDM_FLT2ICR,DFSDM filter 2 interrupt flag clear register" hexmask.long.byte 0x0 24.--31. 1. "CLRSCDF,CLRSCDF" hexmask.long.byte 0x0 16.--23. 1. "CLRCKABF,CLRCKABF" bitfld.long 0x0 3. "CLRROVRF,CLRROVRF" "0,1" bitfld.long 0x0 2. "CLRJOVRF,CLRJOVRF" "0,1" line.long 0x4 "DFSDM_FLT2JCHGR,DFSDM filter 2 injected channel group selection register" hexmask.long.byte 0x4 0.--7. 1. "JCHG,JCHG" line.long 0x8 "DFSDM_FLT2FCR,DFSDM filter 2 control register" bitfld.long 0x8 29.--31. "FORD,FORD" "0,1,2,3,4,5,6,7" hexmask.long.word 0x8 16.--25. 1. "FOSR,FOSR" hexmask.long.byte 0x8 0.--7. 1. "IOSR,IOSR" rgroup.long 0x218++0x7 line.long 0x0 "DFSDM_FLT2JDATAR,DFSDM filter 2 data register for injected group" hexmask.long.tbyte 0x0 8.--31. 1. "JDATA,JDATA" bitfld.long 0x0 0.--2. "JDATACH,JDATACH" "0,1,2,3,4,5,6,7" line.long 0x4 "DFSDM_FLT2RDATAR,DFSDM filter 2 data register for the regular channel" hexmask.long.tbyte 0x4 8.--31. 1. "RDATA,RDATA" bitfld.long 0x4 4. "RPEND,RPEND" "0,1" bitfld.long 0x4 0.--2. "RDATACH,RDATACH" "0,1,2,3,4,5,6,7" group.long 0x220++0x7 line.long 0x0 "DFSDM_FLT2AWHTR,DFSDM filter 2 analog watchdog high threshold register" hexmask.long.tbyte 0x0 8.--31. 1. "AWHT,AWHT" hexmask.long.byte 0x0 0.--3. 1. "BKAWH,BKAWH" line.long 0x4 "DFSDM_FLT2AWLTR,DFSDM filter 2 analog watchdog low threshold register" hexmask.long.tbyte 0x4 8.--31. 1. "AWLT,AWLT" hexmask.long.byte 0x4 0.--3. 1. "BKAWL,BKAWL" rgroup.long 0x228++0x3 line.long 0x0 "DFSDM_FLT2AWSR,DFSDM filter 2 analog watchdog status register" hexmask.long.byte 0x0 8.--15. 1. "AWHTF,AWHTF" hexmask.long.byte 0x0 0.--7. 1. "AWLTF,AWLTF" group.long 0x22C++0x3 line.long 0x0 "DFSDM_FLT2AWCFR,DFSDM filter 2 analog watchdog clear flag register" hexmask.long.byte 0x0 8.--15. 1. "CLRAWHTF,CLRAWHTF" hexmask.long.byte 0x0 0.--7. 1. "CLRAWLTF,CLRAWLTF" rgroup.long 0x230++0x3 line.long 0x0 "DFSDM_FLT2EXMAX,DFSDM filter 2 extremes detector maximum register" hexmask.long.tbyte 0x0 8.--31. 1. "EXMAX,EXMAX" bitfld.long 0x0 0.--2. "EXMAXCH,EXMAXCH" "0,1,2,3,4,5,6,7" group.long 0x234++0x3 line.long 0x0 "DFSDM_FLT2EXMIN,DFSDM filter 2 extremes detector minimum register" hexmask.long.tbyte 0x0 8.--31. 1. "EXMIN,EXMIN" rbitfld.long 0x0 0.--2. "EXMINCH,EXMINCH" "0,1,2,3,4,5,6,7" rgroup.long 0x238++0x3 line.long 0x0 "DFSDM_FLT2CNVTIMR,DFSDM filter 2 conversion timer register" hexmask.long 0x0 4.--31. 1. "CNVCNT,CNVCNT" group.long 0x280++0x7 line.long 0x0 "DFSDM_FLT3CR1,DFSDM filter 3 control register 1" bitfld.long 0x0 30. "AWFSEL,AWFSEL" "0,1" bitfld.long 0x0 29. "FAST,FAST" "0,1" bitfld.long 0x0 24.--26. "RCH,RCH" "0,1,2,3,4,5,6,7" bitfld.long 0x0 21. "RDMAEN,RDMAEN" "0,1" bitfld.long 0x0 19. "RSYNC,RSYNC" "0,1" bitfld.long 0x0 18. "RCONT,RCONT" "0,1" bitfld.long 0x0 17. "RSWSTART,RSWSTART" "0,1" bitfld.long 0x0 13.--14. "JEXTEN,JEXTEN" "0,1,2,3" newline hexmask.long.byte 0x0 8.--12. 1. "JEXTSEL,JEXTSEL" bitfld.long 0x0 5. "JDMAEN,JDMAEN" "0,1" bitfld.long 0x0 4. "JSCAN,JSCAN" "0,1" bitfld.long 0x0 3. "JSYNC,JSYNC" "0,1" bitfld.long 0x0 1. "JSWSTART,JSWSTART" "0,1" bitfld.long 0x0 0. "DFEN,DFEN" "0,1" line.long 0x4 "DFSDM_FLT3CR2,DFSDM filter 3 control register 2" hexmask.long.byte 0x4 16.--23. 1. "AWDCH,AWDCH" hexmask.long.byte 0x4 8.--15. 1. "EXCH,EXCH" bitfld.long 0x4 6. "CKABIE,CKABIE" "0,1" bitfld.long 0x4 5. "SCDIE,SCDIE" "0,1" bitfld.long 0x4 4. "AWDIE,AWDIE" "0,1" bitfld.long 0x4 3. "ROVRIE,ROVRIE" "0,1" bitfld.long 0x4 2. "JOVRIE,JOVRIE" "0,1" bitfld.long 0x4 1. "REOCIE,REOCIE" "0,1" newline bitfld.long 0x4 0. "JEOCIE,JEOCIE" "0,1" rgroup.long 0x288++0x3 line.long 0x0 "DFSDM_FLT3ISR,DFSDM filter 3 interrupt and status register" hexmask.long.byte 0x0 24.--31. 1. "SCDF,SCDF" hexmask.long.byte 0x0 16.--23. 1. "CKABF,CKABF" bitfld.long 0x0 14. "RCIP,RCIP" "0,1" bitfld.long 0x0 13. "JCIP,JCIP" "0,1" bitfld.long 0x0 4. "AWDF,AWDF" "0,1" bitfld.long 0x0 3. "ROVRF,ROVRF" "0,1" bitfld.long 0x0 2. "JOVRF,JOVRF" "0,1" bitfld.long 0x0 1. "REOCF,REOCF" "0,1" newline bitfld.long 0x0 0. "JEOCF,JEOCF" "0,1" group.long 0x28C++0xB line.long 0x0 "DFSDM_FLT3ICR,DFSDM filter 3 interrupt flag clear register" hexmask.long.byte 0x0 24.--31. 1. "CLRSCDF,CLRSCDF" hexmask.long.byte 0x0 16.--23. 1. "CLRCKABF,CLRCKABF" bitfld.long 0x0 3. "CLRROVRF,CLRROVRF" "0,1" bitfld.long 0x0 2. "CLRJOVRF,CLRJOVRF" "0,1" line.long 0x4 "DFSDM_FLT3JCHGR,DFSDM filter 3 injected channel group selection register" hexmask.long.byte 0x4 0.--7. 1. "JCHG,JCHG" line.long 0x8 "DFSDM_FLT3FCR,DFSDM filter 3 control register" bitfld.long 0x8 29.--31. "FORD,FORD" "0,1,2,3,4,5,6,7" hexmask.long.word 0x8 16.--25. 1. "FOSR,FOSR" hexmask.long.byte 0x8 0.--7. 1. "IOSR,IOSR" rgroup.long 0x298++0x7 line.long 0x0 "DFSDM_FLT3JDATAR,DFSDM filter 3 data register for injected group" hexmask.long.tbyte 0x0 8.--31. 1. "JDATA,JDATA" bitfld.long 0x0 0.--2. "JDATACH,JDATACH" "0,1,2,3,4,5,6,7" line.long 0x4 "DFSDM_FLT3RDATAR,DFSDM filter 3 data register for the regular channel" hexmask.long.tbyte 0x4 8.--31. 1. "RDATA,RDATA" bitfld.long 0x4 4. "RPEND,RPEND" "0,1" bitfld.long 0x4 0.--2. "RDATACH,RDATACH" "0,1,2,3,4,5,6,7" group.long 0x2A0++0x7 line.long 0x0 "DFSDM_FLT3AWHTR,DFSDM filter 3 analog watchdog high threshold register" hexmask.long.tbyte 0x0 8.--31. 1. "AWHT,AWHT" hexmask.long.byte 0x0 0.--3. 1. "BKAWH,BKAWH" line.long 0x4 "DFSDM_FLT3AWLTR,DFSDM filter 3 analog watchdog low threshold register" hexmask.long.tbyte 0x4 8.--31. 1. "AWLT,AWLT" hexmask.long.byte 0x4 0.--3. 1. "BKAWL,BKAWL" rgroup.long 0x2A8++0x3 line.long 0x0 "DFSDM_FLT3AWSR,DFSDM filter 3 analog watchdog status register" hexmask.long.byte 0x0 8.--15. 1. "AWHTF,AWHTF" hexmask.long.byte 0x0 0.--7. 1. "AWLTF,AWLTF" group.long 0x2AC++0x3 line.long 0x0 "DFSDM_FLT3AWCFR,DFSDM filter 3 analog watchdog clear flag register" hexmask.long.byte 0x0 8.--15. 1. "CLRAWHTF,CLRAWHTF" hexmask.long.byte 0x0 0.--7. 1. "CLRAWLTF,CLRAWLTF" rgroup.long 0x2B0++0x3 line.long 0x0 "DFSDM_FLT3EXMAX,DFSDM filter 3 extremes detector maximum register" hexmask.long.tbyte 0x0 8.--31. 1. "EXMAX,EXMAX" bitfld.long 0x0 0.--2. "EXMAXCH,EXMAXCH" "0,1,2,3,4,5,6,7" group.long 0x2B4++0x3 line.long 0x0 "DFSDM_FLT3EXMIN,DFSDM filter 3 extremes detector minimum register" hexmask.long.tbyte 0x0 8.--31. 1. "EXMIN,EXMIN" rbitfld.long 0x0 0.--2. "EXMINCH,EXMINCH" "0,1,2,3,4,5,6,7" rgroup.long 0x2B8++0x3 line.long 0x0 "DFSDM_FLT3CNVTIMR,DFSDM filter 3 conversion timer register" hexmask.long 0x0 4.--31. 1. "CNVCNT,CNVCNT" group.long 0x300++0x7 line.long 0x0 "DFSDM_FLT4CR1,DFSDM filter 4 control register 1" bitfld.long 0x0 30. "AWFSEL,AWFSEL" "0,1" bitfld.long 0x0 29. "FAST,FAST" "0,1" bitfld.long 0x0 24.--26. "RCH,RCH" "0,1,2,3,4,5,6,7" bitfld.long 0x0 21. "RDMAEN,RDMAEN" "0,1" bitfld.long 0x0 19. "RSYNC,RSYNC" "0,1" bitfld.long 0x0 18. "RCONT,RCONT" "0,1" bitfld.long 0x0 17. "RSWSTART,RSWSTART" "0,1" bitfld.long 0x0 13.--14. "JEXTEN,JEXTEN" "0,1,2,3" newline hexmask.long.byte 0x0 8.--12. 1. "JEXTSEL,JEXTSEL" bitfld.long 0x0 5. "JDMAEN,JDMAEN" "0,1" bitfld.long 0x0 4. "JSCAN,JSCAN" "0,1" bitfld.long 0x0 3. "JSYNC,JSYNC" "0,1" bitfld.long 0x0 1. "JSWSTART,JSWSTART" "0,1" bitfld.long 0x0 0. "DFEN,DFEN" "0,1" line.long 0x4 "DFSDM_FLT4CR2,DFSDM filter 4 control register 2" hexmask.long.byte 0x4 16.--23. 1. "AWDCH,AWDCH" hexmask.long.byte 0x4 8.--15. 1. "EXCH,EXCH" bitfld.long 0x4 6. "CKABIE,CKABIE" "0,1" bitfld.long 0x4 5. "SCDIE,SCDIE" "0,1" bitfld.long 0x4 4. "AWDIE,AWDIE" "0,1" bitfld.long 0x4 3. "ROVRIE,ROVRIE" "0,1" bitfld.long 0x4 2. "JOVRIE,JOVRIE" "0,1" bitfld.long 0x4 1. "REOCIE,REOCIE" "0,1" newline bitfld.long 0x4 0. "JEOCIE,JEOCIE" "0,1" rgroup.long 0x308++0x3 line.long 0x0 "DFSDM_FLT4ISR,DFSDM filter 4 interrupt and status register" hexmask.long.byte 0x0 24.--31. 1. "SCDF,SCDF" hexmask.long.byte 0x0 16.--23. 1. "CKABF,CKABF" bitfld.long 0x0 14. "RCIP,RCIP" "0,1" bitfld.long 0x0 13. "JCIP,JCIP" "0,1" bitfld.long 0x0 4. "AWDF,AWDF" "0,1" bitfld.long 0x0 3. "ROVRF,ROVRF" "0,1" bitfld.long 0x0 2. "JOVRF,JOVRF" "0,1" bitfld.long 0x0 1. "REOCF,REOCF" "0,1" newline bitfld.long 0x0 0. "JEOCF,JEOCF" "0,1" group.long 0x30C++0xB line.long 0x0 "DFSDM_FLT4ICR,DFSDM filter 4 interrupt flag clear register" hexmask.long.byte 0x0 24.--31. 1. "CLRSCDF,CLRSCDF" hexmask.long.byte 0x0 16.--23. 1. "CLRCKABF,CLRCKABF" bitfld.long 0x0 3. "CLRROVRF,CLRROVRF" "0,1" bitfld.long 0x0 2. "CLRJOVRF,CLRJOVRF" "0,1" line.long 0x4 "DFSDM_FLT4JCHGR,DFSDM filter 4 injected channel group selection register" hexmask.long.byte 0x4 0.--7. 1. "JCHG,JCHG" line.long 0x8 "DFSDM_FLT4FCR,DFSDM filter 4 control register" bitfld.long 0x8 29.--31. "FORD,FORD" "0,1,2,3,4,5,6,7" hexmask.long.word 0x8 16.--25. 1. "FOSR,FOSR" hexmask.long.byte 0x8 0.--7. 1. "IOSR,IOSR" rgroup.long 0x318++0x7 line.long 0x0 "DFSDM_FLT4JDATAR,DFSDM filter 4 data register for injected group" hexmask.long.tbyte 0x0 8.--31. 1. "JDATA,JDATA" bitfld.long 0x0 0.--2. "JDATACH,JDATACH" "0,1,2,3,4,5,6,7" line.long 0x4 "DFSDM_FLT4RDATAR,DFSDM filter 4 data register for the regular channel" hexmask.long.tbyte 0x4 8.--31. 1. "RDATA,RDATA" bitfld.long 0x4 4. "RPEND,RPEND" "0,1" bitfld.long 0x4 0.--2. "RDATACH,RDATACH" "0,1,2,3,4,5,6,7" group.long 0x320++0x7 line.long 0x0 "DFSDM_FLT4AWHTR,DFSDM filter 4 analog watchdog high threshold register" hexmask.long.tbyte 0x0 8.--31. 1. "AWHT,AWHT" hexmask.long.byte 0x0 0.--3. 1. "BKAWH,BKAWH" line.long 0x4 "DFSDM_FLT4AWLTR,DFSDM filter 4 analog watchdog low threshold register" hexmask.long.tbyte 0x4 8.--31. 1. "AWLT,AWLT" hexmask.long.byte 0x4 0.--3. 1. "BKAWL,BKAWL" rgroup.long 0x328++0x3 line.long 0x0 "DFSDM_FLT4AWSR,DFSDM filter 4 analog watchdog status register" hexmask.long.byte 0x0 8.--15. 1. "AWHTF,AWHTF" hexmask.long.byte 0x0 0.--7. 1. "AWLTF,AWLTF" group.long 0x32C++0x3 line.long 0x0 "DFSDM_FLT4AWCFR,DFSDM filter 4 analog watchdog clear flag register" hexmask.long.byte 0x0 8.--15. 1. "CLRAWHTF,CLRAWHTF" hexmask.long.byte 0x0 0.--7. 1. "CLRAWLTF,CLRAWLTF" rgroup.long 0x330++0x3 line.long 0x0 "DFSDM_FLT4EXMAX,DFSDM filter 4 extremes detector maximum register" hexmask.long.tbyte 0x0 8.--31. 1. "EXMAX,EXMAX" bitfld.long 0x0 0.--2. "EXMAXCH,EXMAXCH" "0,1,2,3,4,5,6,7" group.long 0x334++0x3 line.long 0x0 "DFSDM_FLT4EXMIN,DFSDM filter 4 extremes detector minimum register" hexmask.long.tbyte 0x0 8.--31. 1. "EXMIN,EXMIN" rbitfld.long 0x0 0.--2. "EXMINCH,EXMINCH" "0,1,2,3,4,5,6,7" rgroup.long 0x338++0x3 line.long 0x0 "DFSDM_FLT4CNVTIMR,DFSDM filter 4 conversion timer register" hexmask.long 0x0 4.--31. 1. "CNVCNT,CNVCNT" group.long 0x380++0x7 line.long 0x0 "DFSDM_FLT5CR1,DFSDM filter 5 control register 1" bitfld.long 0x0 30. "AWFSEL,AWFSEL" "0,1" bitfld.long 0x0 29. "FAST,FAST" "0,1" bitfld.long 0x0 24.--26. "RCH,RCH" "0,1,2,3,4,5,6,7" bitfld.long 0x0 21. "RDMAEN,RDMAEN" "0,1" bitfld.long 0x0 19. "RSYNC,RSYNC" "0,1" bitfld.long 0x0 18. "RCONT,RCONT" "0,1" bitfld.long 0x0 17. "RSWSTART,RSWSTART" "0,1" bitfld.long 0x0 13.--14. "JEXTEN,JEXTEN" "0,1,2,3" newline hexmask.long.byte 0x0 8.--12. 1. "JEXTSEL,JEXTSEL" bitfld.long 0x0 5. "JDMAEN,JDMAEN" "0,1" bitfld.long 0x0 4. "JSCAN,JSCAN" "0,1" bitfld.long 0x0 3. "JSYNC,JSYNC" "0,1" bitfld.long 0x0 1. "JSWSTART,JSWSTART" "0,1" bitfld.long 0x0 0. "DFEN,DFEN" "0,1" line.long 0x4 "DFSDM_FLT5CR2,DFSDM filter 5 control register 2" hexmask.long.byte 0x4 16.--23. 1. "AWDCH,AWDCH" hexmask.long.byte 0x4 8.--15. 1. "EXCH,EXCH" bitfld.long 0x4 6. "CKABIE,CKABIE" "0,1" bitfld.long 0x4 5. "SCDIE,SCDIE" "0,1" bitfld.long 0x4 4. "AWDIE,AWDIE" "0,1" bitfld.long 0x4 3. "ROVRIE,ROVRIE" "0,1" bitfld.long 0x4 2. "JOVRIE,JOVRIE" "0,1" bitfld.long 0x4 1. "REOCIE,REOCIE" "0,1" newline bitfld.long 0x4 0. "JEOCIE,JEOCIE" "0,1" rgroup.long 0x388++0x3 line.long 0x0 "DFSDM_FLT5ISR,DFSDM filter 5 interrupt and status register" hexmask.long.byte 0x0 24.--31. 1. "SCDF,SCDF" hexmask.long.byte 0x0 16.--23. 1. "CKABF,CKABF" bitfld.long 0x0 14. "RCIP,RCIP" "0,1" bitfld.long 0x0 13. "JCIP,JCIP" "0,1" bitfld.long 0x0 4. "AWDF,AWDF" "0,1" bitfld.long 0x0 3. "ROVRF,ROVRF" "0,1" bitfld.long 0x0 2. "JOVRF,JOVRF" "0,1" bitfld.long 0x0 1. "REOCF,REOCF" "0,1" newline bitfld.long 0x0 0. "JEOCF,JEOCF" "0,1" group.long 0x38C++0xB line.long 0x0 "DFSDM_FLT5ICR,DFSDM filter 5 interrupt flag clear register" hexmask.long.byte 0x0 24.--31. 1. "CLRSCDF,CLRSCDF" hexmask.long.byte 0x0 16.--23. 1. "CLRCKABF,CLRCKABF" bitfld.long 0x0 3. "CLRROVRF,CLRROVRF" "0,1" bitfld.long 0x0 2. "CLRJOVRF,CLRJOVRF" "0,1" line.long 0x4 "DFSDM_FLT5JCHGR,DFSDM filter 5 injected channel group selection register" hexmask.long.byte 0x4 0.--7. 1. "JCHG,JCHG" line.long 0x8 "DFSDM_FLT5FCR,DFSDM filter 5 control register" bitfld.long 0x8 29.--31. "FORD,FORD" "0,1,2,3,4,5,6,7" hexmask.long.word 0x8 16.--25. 1. "FOSR,FOSR" hexmask.long.byte 0x8 0.--7. 1. "IOSR,IOSR" rgroup.long 0x398++0x7 line.long 0x0 "DFSDM_FLT5JDATAR,DFSDM filter 5 data register for injected group" hexmask.long.tbyte 0x0 8.--31. 1. "JDATA,JDATA" bitfld.long 0x0 0.--2. "JDATACH,JDATACH" "0,1,2,3,4,5,6,7" line.long 0x4 "DFSDM_FLT5RDATAR,DFSDM filter 5 data register for the regular channel" hexmask.long.tbyte 0x4 8.--31. 1. "RDATA,RDATA" bitfld.long 0x4 4. "RPEND,RPEND" "0,1" bitfld.long 0x4 0.--2. "RDATACH,RDATACH" "0,1,2,3,4,5,6,7" group.long 0x3A0++0x7 line.long 0x0 "DFSDM_FLT5AWHTR,DFSDM filter 5 analog watchdog high threshold register" hexmask.long.tbyte 0x0 8.--31. 1. "AWHT,AWHT" hexmask.long.byte 0x0 0.--3. 1. "BKAWH,BKAWH" line.long 0x4 "DFSDM_FLT5AWLTR,DFSDM filter 5 analog watchdog low threshold register" hexmask.long.tbyte 0x4 8.--31. 1. "AWLT,AWLT" hexmask.long.byte 0x4 0.--3. 1. "BKAWL,BKAWL" rgroup.long 0x3A8++0x3 line.long 0x0 "DFSDM_FLT5AWSR,DFSDM filter 5 analog watchdog status register" hexmask.long.byte 0x0 8.--15. 1. "AWHTF,AWHTF" hexmask.long.byte 0x0 0.--7. 1. "AWLTF,AWLTF" group.long 0x3AC++0x3 line.long 0x0 "DFSDM_FLT5AWCFR,DFSDM filter 5 analog watchdog clear flag register" hexmask.long.byte 0x0 8.--15. 1. "CLRAWHTF,CLRAWHTF" hexmask.long.byte 0x0 0.--7. 1. "CLRAWLTF,CLRAWLTF" rgroup.long 0x3B0++0x3 line.long 0x0 "DFSDM_FLT5EXMAX,DFSDM filter 5 extremes detector maximum register" hexmask.long.tbyte 0x0 8.--31. 1. "EXMAX,EXMAX" bitfld.long 0x0 0.--2. "EXMAXCH,EXMAXCH" "0,1,2,3,4,5,6,7" group.long 0x3B4++0x3 line.long 0x0 "DFSDM_FLT5EXMIN,DFSDM filter 5 extremes detector minimum register" hexmask.long.tbyte 0x0 8.--31. 1. "EXMIN,EXMIN" rbitfld.long 0x0 0.--2. "EXMINCH,EXMINCH" "0,1,2,3,4,5,6,7" rgroup.long 0x3B8++0x3 line.long 0x0 "DFSDM_FLT5CNVTIMR,DFSDM filter 5 conversion timer register" hexmask.long 0x0 4.--31. 1. "CNVCNT,CNVCNT" rgroup.long 0x7F0++0xF line.long 0x0 "DFSDM_HWCFGR,This register specifies the hardware configuration of DFSDM peripheral." hexmask.long.byte 0x0 8.--15. 1. "NBF,NBF" hexmask.long.byte 0x0 0.--7. 1. "NBT,NBT" line.long 0x4 "DFSDM_VERR,This register specifies the version of DFSDM peripheral." hexmask.long.byte 0x4 4.--7. 1. "MAJREV,MAJREV" hexmask.long.byte 0x4 0.--3. 1. "MINREV,MINREV" line.long 0x8 "DFSDM_IPIDR,This register specifies the identification of DFSDM peripheral." hexmask.long 0x8 0.--31. 1. "ID,ID" line.long 0xC "DFSDM_SIDR,This register specifies the size allocated to DFSDM registers." hexmask.long 0xC 0.--31. 1. "SID,SID" tree.end endif tree.end tree "DLYB (Delay Block)" base ad:0x0 sif (cpuis("STM32MP13*")) tree "DLYBSD1" base ad:0x58006000 group.long 0x0++0x7 line.long 0x0 "DLYB_CR,DLYB control register" bitfld.long 0x0 1. "SEN,Sampler length enable bit" "0: Sampler length and register access to UNIT[6:0]..,1: Sampler length and register access to UNIT[6:0].." bitfld.long 0x0 0. "DEN,Delay block enable bit" "0: DLYB disabled.,1: DLYB enabled." line.long 0x4 "DLYB_CFGR,DLYB configuration register" rbitfld.long 0x4 31. "LNGF,Length valid flag" "0: Length value in LNG is not valid.,1: Length value in LNG is valid." hexmask.long.word 0x4 16.--27. 1. "LNG,Delay line length value" hexmask.long.byte 0x4 8.--14. 1. "UNIT,Delay of a unit delay cell." hexmask.long.byte 0x4 0.--3. 1. "SEL,Phase for the output clock." tree.end endif sif (cpuis("STM32MP13*")) tree "DLYBSD2" base ad:0x58008000 group.long 0x0++0x7 line.long 0x0 "DLYB_CR,DLYB control register" bitfld.long 0x0 1. "SEN,Sampler length enable bit" "0: Sampler length and register access to UNIT[6:0]..,1: Sampler length and register access to UNIT[6:0].." bitfld.long 0x0 0. "DEN,Delay block enable bit" "0: DLYB disabled.,1: DLYB enabled." line.long 0x4 "DLYB_CFGR,DLYB configuration register" rbitfld.long 0x4 31. "LNGF,Length valid flag" "0: Length value in LNG is not valid.,1: Length value in LNG is valid." hexmask.long.word 0x4 16.--27. 1. "LNG,Delay line length value" hexmask.long.byte 0x4 8.--14. 1. "UNIT,Delay of a unit delay cell." hexmask.long.byte 0x4 0.--3. 1. "SEL,Phase for the output clock." tree.end endif sif (cpuis("STM32MP13*")) tree "DLYBQS" base ad:0x58004000 group.long 0x0++0x7 line.long 0x0 "DLYB_CR,DLYB control register" bitfld.long 0x0 1. "SEN,Sampler length enable bit" "0: Sampler length and register access to UNIT[6:0]..,1: Sampler length and register access to UNIT[6:0].." bitfld.long 0x0 0. "DEN,Delay block enable bit" "0: DLYB disabled.,1: DLYB enabled." line.long 0x4 "DLYB_CFGR,DLYB configuration register" rbitfld.long 0x4 31. "LNGF,Length valid flag" "0: Length value in LNG is not valid.,1: Length value in LNG is valid." hexmask.long.word 0x4 16.--27. 1. "LNG,Delay line length value" hexmask.long.byte 0x4 8.--14. 1. "UNIT,Delay of a unit delay cell." hexmask.long.byte 0x4 0.--3. 1. "SEL,Phase for the output clock." tree.end endif sif (cpuis("STM32MP151*")||cpuis("STM32MP153*")||cpuis("STM32MP157*")) tree "DLYBSD1" base ad:0x58006000 group.long 0x0++0x7 line.long 0x0 "DLYB_CR,DLYB control register" bitfld.long 0x0 1. "SEN,SEN" "0,1" bitfld.long 0x0 0. "DEN,DEN" "0,1" line.long 0x4 "DLYB_CFGR,DLYB configuration register" rbitfld.long 0x4 31. "LNGF,LNGF" "0,1" hexmask.long.word 0x4 16.--27. 1. "LNG,LNG" hexmask.long.byte 0x4 8.--14. 1. "UNIT,UNIT" hexmask.long.byte 0x4 0.--3. 1. "SEL,SEL" rgroup.long 0x3F4++0xB line.long 0x0 "DLYB_VERR,DLYB IP version register" hexmask.long.byte 0x0 4.--7. 1. "MAJREV,MAJREV" hexmask.long.byte 0x0 0.--3. 1. "MINREV,MINREV" line.long 0x4 "DLYB_IPIDR,DLYB IP identification register" hexmask.long 0x4 0.--31. 1. "ID,ID" line.long 0x8 "DLYB_SIDR,DLYB size ID register" hexmask.long 0x8 0.--31. 1. "SID,SID" tree.end endif sif (cpuis("STM32MP151*")||cpuis("STM32MP153*")||cpuis("STM32MP157*")) tree "DLYBSD2" base ad:0x58008000 group.long 0x0++0x7 line.long 0x0 "DLYB_CR,DLYB control register" bitfld.long 0x0 1. "SEN,SEN" "0,1" bitfld.long 0x0 0. "DEN,DEN" "0,1" line.long 0x4 "DLYB_CFGR,DLYB configuration register" rbitfld.long 0x4 31. "LNGF,LNGF" "0,1" hexmask.long.word 0x4 16.--27. 1. "LNG,LNG" hexmask.long.byte 0x4 8.--14. 1. "UNIT,UNIT" hexmask.long.byte 0x4 0.--3. 1. "SEL,SEL" rgroup.long 0x3F4++0xB line.long 0x0 "DLYB_VERR,DLYB IP version register" hexmask.long.byte 0x0 4.--7. 1. "MAJREV,MAJREV" hexmask.long.byte 0x0 0.--3. 1. "MINREV,MINREV" line.long 0x4 "DLYB_IPIDR,DLYB IP identification register" hexmask.long 0x4 0.--31. 1. "ID,ID" line.long 0x8 "DLYB_SIDR,DLYB size ID register" hexmask.long 0x8 0.--31. 1. "SID,SID" tree.end endif sif (cpuis("STM32MP151*")||cpuis("STM32MP153*")||cpuis("STM32MP157*")) tree "DLYBSD3" base ad:0x48005000 group.long 0x0++0x7 line.long 0x0 "DLYB_CR,DLYB control register" bitfld.long 0x0 1. "SEN,SEN" "0,1" bitfld.long 0x0 0. "DEN,DEN" "0,1" line.long 0x4 "DLYB_CFGR,DLYB configuration register" rbitfld.long 0x4 31. "LNGF,LNGF" "0,1" hexmask.long.word 0x4 16.--27. 1. "LNG,LNG" hexmask.long.byte 0x4 8.--14. 1. "UNIT,UNIT" hexmask.long.byte 0x4 0.--3. 1. "SEL,SEL" rgroup.long 0x3F4++0xB line.long 0x0 "DLYB_VERR,DLYB IP version register" hexmask.long.byte 0x0 4.--7. 1. "MAJREV,MAJREV" hexmask.long.byte 0x0 0.--3. 1. "MINREV,MINREV" line.long 0x4 "DLYB_IPIDR,DLYB IP identification register" hexmask.long 0x4 0.--31. 1. "ID,ID" line.long 0x8 "DLYB_SIDR,DLYB size ID register" hexmask.long 0x8 0.--31. 1. "SID,SID" tree.end endif sif (cpuis("STM32MP151*")||cpuis("STM32MP153*")||cpuis("STM32MP157*")) tree "DLYBQS" base ad:0x58004000 group.long 0x0++0x7 line.long 0x0 "DLYB_CR,DLYB control register" bitfld.long 0x0 1. "SEN,SEN" "0,1" bitfld.long 0x0 0. "DEN,DEN" "0,1" line.long 0x4 "DLYB_CFGR,DLYB configuration register" rbitfld.long 0x4 31. "LNGF,LNGF" "0,1" hexmask.long.word 0x4 16.--27. 1. "LNG,LNG" hexmask.long.byte 0x4 8.--14. 1. "UNIT,UNIT" hexmask.long.byte 0x4 0.--3. 1. "SEL,SEL" rgroup.long 0x3F4++0xB line.long 0x0 "DLYB_VERR,DLYB IP version register" hexmask.long.byte 0x0 4.--7. 1. "MAJREV,MAJREV" hexmask.long.byte 0x0 0.--3. 1. "MINREV,MINREV" line.long 0x4 "DLYB_IPIDR,DLYB IP identification" hexmask.long 0x4 0.--31. 1. "ID,ID" line.long 0x8 "DLYB_SIDR,DLYB size ID register" hexmask.long 0x8 0.--31. 1. "SID,SID" tree.end endif tree.end tree "DMA (Direct Memory Access Controller)" base ad:0x0 sif (cpuis("STM32MP13*")) tree "DMA1" base ad:0x48000000 rgroup.long 0x0++0x7 line.long 0x0 "DMA_LISR,DMA low interrupt status register" bitfld.long 0x0 27. "TCIF3,stream x transfer complete interrupt flag (x = 3 to 0)" "0: no transfer complete event on stream x,1: a transfer complete event occurred on stream x" bitfld.long 0x0 26. "HTIF3,stream x half transfer interrupt flag (x = 3 to 0)" "0: no half transfer event on stream x,1: a half transfer event occurred on stream x" newline bitfld.long 0x0 25. "TEIF3,stream x transfer error interrupt flag (x = 3 to 0)" "0: no transfer error on stream x,1: a transfer error occurred on stream x" bitfld.long 0x0 24. "DMEIF3,stream x direct mode error interrupt flag (x = 3 to 0)" "0: No direct mode error on stream x,1: a direct mode error occurred on stream x" newline bitfld.long 0x0 22. "FEIF3,stream x FIFO error interrupt flag (x = 3 to 0)" "0: no FIFO error event on stream x,1: a FIFO error event occurred on stream x" bitfld.long 0x0 21. "TCIF2,stream x transfer complete interrupt flag (x = 3 to 0)" "0: no transfer complete event on stream x,1: a transfer complete event occurred on stream x" newline bitfld.long 0x0 20. "HTIF2,stream x half transfer interrupt flag (x = 3 to 0)" "0: no half transfer event on stream x,1: a half transfer event occurred on stream x" bitfld.long 0x0 19. "TEIF2,stream x transfer error interrupt flag (x = 3 to 0)" "0: no transfer error on stream x,1: a transfer error occurred on stream x" newline bitfld.long 0x0 18. "DMEIF2,stream x direct mode error interrupt flag (x = 3 to 0)" "0: No direct mode error on stream x,1: a direct mode error occurred on stream x" bitfld.long 0x0 16. "FEIF2,stream x FIFO error interrupt flag (x = 3 to 0)" "0: no FIFO error event on stream x,1: a FIFO error event occurred on stream x" newline bitfld.long 0x0 11. "TCIF1,stream x transfer complete interrupt flag (x = 3 to 0)" "0: no transfer complete event on stream x,1: a transfer complete event occurred on stream x" bitfld.long 0x0 10. "HTIF1,stream x half transfer interrupt flag (x = 3 to 0)" "0: no half transfer event on stream x,1: a half transfer event occurred on stream x" newline bitfld.long 0x0 9. "TEIF1,stream x transfer error interrupt flag (x = 3 to 0)" "0: no transfer error on stream x,1: a transfer error occurred on stream x" bitfld.long 0x0 8. "DMEIF1,stream x direct mode error interrupt flag (x = 3 to 0)" "0: No direct mode error on stream x,1: a direct mode error occurred on stream x" newline bitfld.long 0x0 6. "FEIF1,stream x FIFO error interrupt flag (x = 3 to 0)" "0: no FIFO error event on stream x,1: a FIFO error event occurred on stream x" bitfld.long 0x0 5. "TCIF0,stream x transfer complete interrupt flag (x = 3 to 0)" "0: no transfer complete event on stream x,1: a transfer complete event occurred on stream x" newline bitfld.long 0x0 4. "HTIF0,stream x half transfer interrupt flag (x = 3 to 0)" "0: no half transfer event on stream x,1: a half transfer event occurred on stream x" bitfld.long 0x0 3. "TEIF0,stream x transfer error interrupt flag (x = 3 to 0)" "0: no transfer error on stream x,1: a transfer error occurred on stream x" newline bitfld.long 0x0 2. "DMEIF0,stream x direct mode error interrupt flag (x = 3 to 0)" "0: No direct mode error on stream x,1: a direct mode error occurred on stream x" bitfld.long 0x0 0. "FEIF0,stream x FIFO error interrupt flag (x = 3 to 0)" "0: no FIFO error event on stream x,1: a FIFO error event occurred on stream x" line.long 0x4 "DMA_HISR,DMA high interrupt status register" bitfld.long 0x4 27. "TCIF7,stream x transfer complete interrupt flag (x = 7 to 4)" "0: no transfer complete event on stream x,1: a transfer complete event occurred on stream x" bitfld.long 0x4 26. "HTIF7,stream x half transfer interrupt flag (x = 7 to 4)" "0: no half transfer event on stream x,1: a half transfer event occurred on stream x" newline bitfld.long 0x4 25. "TEIF7,stream x transfer error interrupt flag (x = 7 to 4)" "0: no transfer error on stream x,1: a transfer error occurred on stream x" bitfld.long 0x4 24. "DMEIF7,stream x direct mode error interrupt flag (x = 7 to 4)" "0: no direct mode error on stream x,1: a direct mode error occurred on stream x" newline bitfld.long 0x4 22. "FEIF7,stream x FIFO error interrupt flag (x = 7 to 4)" "0: no FIFO error event on stream x,1: a FIFO error event occurred on stream x" bitfld.long 0x4 21. "TCIF6,stream x transfer complete interrupt flag (x = 7 to 4)" "0: no transfer complete event on stream x,1: a transfer complete event occurred on stream x" newline bitfld.long 0x4 20. "HTIF6,stream x half transfer interrupt flag (x = 7 to 4)" "0: no half transfer event on stream x,1: a half transfer event occurred on stream x" bitfld.long 0x4 19. "TEIF6,stream x transfer error interrupt flag (x = 7 to 4)" "0: no transfer error on stream x,1: a transfer error occurred on stream x" newline bitfld.long 0x4 18. "DMEIF6,stream x direct mode error interrupt flag (x = 7 to 4)" "0: no direct mode error on stream x,1: a direct mode error occurred on stream x" bitfld.long 0x4 16. "FEIF6,stream x FIFO error interrupt flag (x = 7 to 4)" "0: no FIFO error event on stream x,1: a FIFO error event occurred on stream x" newline bitfld.long 0x4 11. "TCIF5,stream x transfer complete interrupt flag (x = 7 to 4)" "0: no transfer complete event on stream x,1: a transfer complete event occurred on stream x" bitfld.long 0x4 10. "HTIF5,stream x half transfer interrupt flag (x = 7 to 4)" "0: no half transfer event on stream x,1: a half transfer event occurred on stream x" newline bitfld.long 0x4 9. "TEIF5,stream x transfer error interrupt flag (x = 7 to 4)" "0: no transfer error on stream x,1: a transfer error occurred on stream x" bitfld.long 0x4 8. "DMEIF5,stream x direct mode error interrupt flag (x = 7 to 4)" "0: no direct mode error on stream x,1: a direct mode error occurred on stream x" newline bitfld.long 0x4 6. "FEIF5,stream x FIFO error interrupt flag (x = 7 to 4)" "0: no FIFO error event on stream x,1: a FIFO error event occurred on stream x" bitfld.long 0x4 5. "TCIF4,stream x transfer complete interrupt flag (x = 7 to 4)" "0: no transfer complete event on stream x,1: a transfer complete event occurred on stream x" newline bitfld.long 0x4 4. "HTIF4,stream x half transfer interrupt flag (x = 7 to 4)" "0: no half transfer event on stream x,1: a half transfer event occurred on stream x" bitfld.long 0x4 3. "TEIF4,stream x transfer error interrupt flag (x = 7 to 4)" "0: no transfer error on stream x,1: a transfer error occurred on stream x" newline bitfld.long 0x4 2. "DMEIF4,stream x direct mode error interrupt flag (x = 7 to 4)" "0: no direct mode error on stream x,1: a direct mode error occurred on stream x" bitfld.long 0x4 0. "FEIF4,stream x FIFO error interrupt flag (x = 7 to 4)" "0: no FIFO error event on stream x,1: a FIFO error event occurred on stream x" wgroup.long 0x8++0x7 line.long 0x0 "DMA_LIFCR,DMA low interrupt flag clear register" bitfld.long 0x0 27. "CTCIF3,stream x clear transfer complete interrupt flag (x = 3 to 0)" "0,1" bitfld.long 0x0 26. "CHTIF3,stream x clear half transfer interrupt flag (x = 3 to 0)" "0,1" newline bitfld.long 0x0 25. "CTEIF3,Stream x clear transfer error interrupt flag (x = 3 to 0)" "0,1" bitfld.long 0x0 24. "CDMEIF3,stream x clear direct mode error interrupt flag (x = 3 to 0)" "0,1" newline bitfld.long 0x0 22. "CFEIF3,stream x clear FIFO error interrupt flag (x = 3 to 0)" "0,1" bitfld.long 0x0 21. "CTCIF2,stream x clear transfer complete interrupt flag (x = 3 to 0)" "0,1" newline bitfld.long 0x0 20. "CHTIF2,stream x clear half transfer interrupt flag (x = 3 to 0)" "0,1" bitfld.long 0x0 19. "CTEIF2,Stream x clear transfer error interrupt flag (x = 3 to 0)" "0,1" newline bitfld.long 0x0 18. "CDMEIF2,stream x clear direct mode error interrupt flag (x = 3 to 0)" "0,1" bitfld.long 0x0 16. "CFEIF2,stream x clear FIFO error interrupt flag (x = 3 to 0)" "0,1" newline bitfld.long 0x0 11. "CTCIF1,stream x clear transfer complete interrupt flag (x = 3 to 0)" "0,1" bitfld.long 0x0 10. "CHTIF1,stream x clear half transfer interrupt flag (x = 3 to 0)" "0,1" newline bitfld.long 0x0 9. "CTEIF1,Stream x clear transfer error interrupt flag (x = 3 to 0)" "0,1" bitfld.long 0x0 8. "CDMEIF1,stream x clear direct mode error interrupt flag (x = 3 to 0)" "0,1" newline bitfld.long 0x0 6. "CFEIF1,stream x clear FIFO error interrupt flag (x = 3 to 0)" "0,1" bitfld.long 0x0 5. "CTCIF0,stream x clear transfer complete interrupt flag (x = 3 to 0)" "0,1" newline bitfld.long 0x0 4. "CHTIF0,stream x clear half transfer interrupt flag (x = 3 to 0)" "0,1" bitfld.long 0x0 3. "CTEIF0,Stream x clear transfer error interrupt flag (x = 3 to 0)" "0,1" newline bitfld.long 0x0 2. "CDMEIF0,stream x clear direct mode error interrupt flag (x = 3 to 0)" "0,1" bitfld.long 0x0 0. "CFEIF0,stream x clear FIFO error interrupt flag (x = 3 to 0)" "0,1" line.long 0x4 "DMA_HIFCR,DMA high interrupt flag clear register" bitfld.long 0x4 27. "CTCIF7,stream x clear transfer complete interrupt flag (x = 7 to 4)" "0,1" bitfld.long 0x4 26. "CHTIF7,stream x clear half transfer interrupt flag (x = 7 to 4)" "0,1" newline bitfld.long 0x4 25. "CTEIF7,stream x clear transfer error interrupt flag (x = 7 to 4)" "0,1" bitfld.long 0x4 24. "CDMEIF7,stream x clear direct mode error interrupt flag (x = 7 to 4)" "0,1" newline bitfld.long 0x4 22. "CFEIF7,stream x clear FIFO error interrupt flag (x = 7 to 4)" "0,1" bitfld.long 0x4 21. "CTCIF6,stream x clear transfer complete interrupt flag (x = 7 to 4)" "0,1" newline bitfld.long 0x4 20. "CHTIF6,stream x clear half transfer interrupt flag (x = 7 to 4)" "0,1" bitfld.long 0x4 19. "CTEIF6,stream x clear transfer error interrupt flag (x = 7 to 4)" "0,1" newline bitfld.long 0x4 18. "CDMEIF6,stream x clear direct mode error interrupt flag (x = 7 to 4)" "0,1" bitfld.long 0x4 16. "CFEIF6,stream x clear FIFO error interrupt flag (x = 7 to 4)" "0,1" newline bitfld.long 0x4 11. "CTCIF5,stream x clear transfer complete interrupt flag (x = 7 to 4)" "0,1" bitfld.long 0x4 10. "CHTIF5,stream x clear half transfer interrupt flag (x = 7 to 4)" "0,1" newline bitfld.long 0x4 9. "CTEIF5,stream x clear transfer error interrupt flag (x = 7 to 4)" "0,1" bitfld.long 0x4 8. "CDMEIF5,stream x clear direct mode error interrupt flag (x = 7 to 4)" "0,1" newline bitfld.long 0x4 6. "CFEIF5,stream x clear FIFO error interrupt flag (x = 7 to 4)" "0,1" bitfld.long 0x4 5. "CTCIF4,stream x clear transfer complete interrupt flag (x = 7 to 4)" "0,1" newline bitfld.long 0x4 4. "CHTIF4,stream x clear half transfer interrupt flag (x = 7 to 4)" "0,1" bitfld.long 0x4 3. "CTEIF4,stream x clear transfer error interrupt flag (x = 7 to 4)" "0,1" newline bitfld.long 0x4 2. "CDMEIF4,stream x clear direct mode error interrupt flag (x = 7 to 4)" "0,1" bitfld.long 0x4 0. "CFEIF4,stream x clear FIFO error interrupt flag (x = 7 to 4)" "0,1" group.long 0x10++0xBF line.long 0x0 "DMA_S0CR,DMA stream 0 configuration register" bitfld.long 0x0 23.--24. "MBURST,memory burst transfer configuration" "0: single transfer,1: INCR4 (incremental burst of 4 beats),2: INCR8 (incremental burst of 8 beats),3: INCR16 (incremental burst of 16 beats)" bitfld.long 0x0 21.--22. "PBURST,peripheral burst transfer configuration" "0: single transfer,1: INCR4 (incremental burst of 4 beats),2: INCR8 (incremental burst of 8 beats),3: INCR16 (incremental burst of 16 beats)" newline bitfld.long 0x0 20. "TRBUFF,Enable the DMA to handle bufferable transfers." "0: bufferable transfers not enabled,1: bufferable transfers enabled" bitfld.long 0x0 19. "CT,current target (only in double-buffer mode)" "0: current target memory is Memory 0 (addressed by..,1: current target memory is Memory 1 (addressed by.." newline bitfld.long 0x0 18. "DBM,double-buffer mode" "0: no buffer switching at the end of transfer,1: memory target switched at the end of the DMA.." bitfld.long 0x0 16.--17. "PL,priority level" "0: low,1: medium,2: high,3: very high" newline bitfld.long 0x0 15. "PINCOS,peripheral increment offset size" "0: The offset size for the peripheral address..,1: The offset size for the peripheral address.." bitfld.long 0x0 13.--14. "MSIZE,memory data size" "0: byte (8-bit),1: half-word (16-bit),2: word (32-bit),?" newline bitfld.long 0x0 11.--12. "PSIZE,peripheral data size" "0: byte (8-bit),1: half-word (16-bit),2: word (32-bit),?" bitfld.long 0x0 10. "MINC,memory increment mode" "0: memory address pointer is fixed,1: memory address pointer is incremented after each.." newline bitfld.long 0x0 9. "PINC,peripheral increment mode" "0: peripheral address pointer fixed,1: peripheral address pointer incremented after.." bitfld.long 0x0 8. "CIRC,circular mode" "0: circular mode disabled,1: circular mode enabled" newline bitfld.long 0x0 6.--7. "DIR,data transfer direction" "0: peripheral-to-memory,1: memory-to-peripheral,2: memory-to-memory,?" bitfld.long 0x0 5. "PFCTRL,peripheral flow controller" "0: DMA is the flow controller.,1: The peripheral is the flow controller." newline bitfld.long 0x0 4. "TCIE,transfer complete interrupt enable" "0: TC interrupt disabled,1: TC interrupt enabled" bitfld.long 0x0 3. "HTIE,half transfer interrupt enable" "0: HT interrupt disabled,1: HT interrupt enabled" newline bitfld.long 0x0 2. "TEIE,transfer error interrupt enable" "0: TE interrupt disabled,1: TE interrupt enabled" bitfld.long 0x0 1. "DMEIE,direct mode error interrupt enable" "0: DME interrupt disabled,1: DME interrupt enabled" newline bitfld.long 0x0 0. "EN,stream enable / flag stream ready when read low" "0: stream disabled,1: stream enabled" line.long 0x4 "DMA_S0NDTR,DMA stream 0 number of data register" hexmask.long.word 0x4 0.--15. 1. "NDT,number of data items to transfer (0 up to 65535)" line.long 0x8 "DMA_S0PAR,DMA stream 0 peripheral address register" hexmask.long 0x8 0.--31. 1. "PAR,peripheral address" line.long 0xC "DMA_S0M0AR,DMA stream 0 memory 0 address register" hexmask.long 0xC 0.--31. 1. "M0A,memory 0 address" line.long 0x10 "DMA_S0M1AR,DMA stream 0 memory 1 address register" hexmask.long 0x10 0.--31. 1. "M1A,memory 1 address (used in case of double-buffer mode)" line.long 0x14 "DMA_S0FCR,DMA stream 0 FIFO control register" bitfld.long 0x14 7. "FEIE,FIFO error interrupt enable" "0: FE interrupt disabled,1: FE interrupt enabled" rbitfld.long 0x14 3.--5. "FS,FIFO status" "0: 0 < fifo_level < 1/4,1: 1/4 ≤ fifo_level < 1/2,2: 1/2 ≤ fifo_level < 3/4,3: 3/4 ≤ fifo_level < full,4: FIFO is empty,5: FIFO is full,?,?" newline bitfld.long 0x14 2. "DMDIS,direct mode disable" "0: direct mode enabled,1: direct mode disabled" bitfld.long 0x14 0.--1. "FTH,FIFO threshold selection" "0: 1/4 full FIFO,1: 1/2 full FIFO,2: 3/4 full FIFO,3: full FIFO" line.long 0x18 "DMA_S1CR,DMA stream 1 configuration register" bitfld.long 0x18 23.--24. "MBURST,memory burst transfer configuration" "0: single transfer,1: INCR4 (incremental burst of 4 beats),2: INCR8 (incremental burst of 8 beats),3: INCR16 (incremental burst of 16 beats)" bitfld.long 0x18 21.--22. "PBURST,peripheral burst transfer configuration" "0: single transfer,1: INCR4 (incremental burst of 4 beats),2: INCR8 (incremental burst of 8 beats),3: INCR16 (incremental burst of 16 beats)" newline bitfld.long 0x18 20. "TRBUFF,Enable the DMA to handle bufferable transfers." "0: bufferable transfers not enabled,1: bufferable transfers enabled" bitfld.long 0x18 19. "CT,current target (only in double-buffer mode)" "0: current target memory is Memory 0 (addressed by..,1: current target memory is Memory 1 (addressed by.." newline bitfld.long 0x18 18. "DBM,double-buffer mode" "0: no buffer switching at the end of transfer,1: memory target switched at the end of the DMA.." bitfld.long 0x18 16.--17. "PL,priority level" "0: low,1: medium,2: high,3: very high" newline bitfld.long 0x18 15. "PINCOS,peripheral increment offset size" "0: The offset size for the peripheral address..,1: The offset size for the peripheral address.." bitfld.long 0x18 13.--14. "MSIZE,memory data size" "0: byte (8-bit),1: half-word (16-bit),2: word (32-bit),?" newline bitfld.long 0x18 11.--12. "PSIZE,peripheral data size" "0: byte (8-bit),1: half-word (16-bit),2: word (32-bit),?" bitfld.long 0x18 10. "MINC,memory increment mode" "0: memory address pointer is fixed,1: memory address pointer is incremented after each.." newline bitfld.long 0x18 9. "PINC,peripheral increment mode" "0: peripheral address pointer fixed,1: peripheral address pointer incremented after.." bitfld.long 0x18 8. "CIRC,circular mode" "0: circular mode disabled,1: circular mode enabled" newline bitfld.long 0x18 6.--7. "DIR,data transfer direction" "0: peripheral-to-memory,1: memory-to-peripheral,2: memory-to-memory,?" bitfld.long 0x18 5. "PFCTRL,peripheral flow controller" "0: DMA is the flow controller.,1: The peripheral is the flow controller." newline bitfld.long 0x18 4. "TCIE,transfer complete interrupt enable" "0: TC interrupt disabled,1: TC interrupt enabled" bitfld.long 0x18 3. "HTIE,half transfer interrupt enable" "0: HT interrupt disabled,1: HT interrupt enabled" newline bitfld.long 0x18 2. "TEIE,transfer error interrupt enable" "0: TE interrupt disabled,1: TE interrupt enabled" bitfld.long 0x18 1. "DMEIE,direct mode error interrupt enable" "0: DME interrupt disabled,1: DME interrupt enabled" newline bitfld.long 0x18 0. "EN,stream enable / flag stream ready when read low" "0: stream disabled,1: stream enabled" line.long 0x1C "DMA_S1NDTR,DMA stream 1 number of data register" hexmask.long.word 0x1C 0.--15. 1. "NDT,number of data items to transfer (0 up to 65535)" line.long 0x20 "DMA_S1PAR,DMA stream 1 peripheral address register" hexmask.long 0x20 0.--31. 1. "PAR,peripheral address" line.long 0x24 "DMA_S1M0AR,DMA stream 1 memory 0 address register" hexmask.long 0x24 0.--31. 1. "M0A,memory 0 address" line.long 0x28 "DMA_S1M1AR,DMA stream 1 memory 1 address register" hexmask.long 0x28 0.--31. 1. "M1A,memory 1 address (used in case of double-buffer mode)" line.long 0x2C "DMA_S1FCR,DMA stream 1 FIFO control register" bitfld.long 0x2C 7. "FEIE,FIFO error interrupt enable" "0: FE interrupt disabled,1: FE interrupt enabled" rbitfld.long 0x2C 3.--5. "FS,FIFO status" "0: 0 < fifo_level < 1/4,1: 1/4 ≤ fifo_level < 1/2,2: 1/2 ≤ fifo_level < 3/4,3: 3/4 ≤ fifo_level < full,4: FIFO is empty,5: FIFO is full,?,?" newline bitfld.long 0x2C 2. "DMDIS,direct mode disable" "0: direct mode enabled,1: direct mode disabled" bitfld.long 0x2C 0.--1. "FTH,FIFO threshold selection" "0: 1/4 full FIFO,1: 1/2 full FIFO,2: 3/4 full FIFO,3: full FIFO" line.long 0x30 "DMA_S2CR,DMA stream 2 configuration register" bitfld.long 0x30 23.--24. "MBURST,memory burst transfer configuration" "0: single transfer,1: INCR4 (incremental burst of 4 beats),2: INCR8 (incremental burst of 8 beats),3: INCR16 (incremental burst of 16 beats)" bitfld.long 0x30 21.--22. "PBURST,peripheral burst transfer configuration" "0: single transfer,1: INCR4 (incremental burst of 4 beats),2: INCR8 (incremental burst of 8 beats),3: INCR16 (incremental burst of 16 beats)" newline bitfld.long 0x30 20. "TRBUFF,Enable the DMA to handle bufferable transfers." "0: bufferable transfers not enabled,1: bufferable transfers enabled" bitfld.long 0x30 19. "CT,current target (only in double-buffer mode)" "0: current target memory is Memory 0 (addressed by..,1: current target memory is Memory 1 (addressed by.." newline bitfld.long 0x30 18. "DBM,double-buffer mode" "0: no buffer switching at the end of transfer,1: memory target switched at the end of the DMA.." bitfld.long 0x30 16.--17. "PL,priority level" "0: low,1: medium,2: high,3: very high" newline bitfld.long 0x30 15. "PINCOS,peripheral increment offset size" "0: The offset size for the peripheral address..,1: The offset size for the peripheral address.." bitfld.long 0x30 13.--14. "MSIZE,memory data size" "0: byte (8-bit),1: half-word (16-bit),2: word (32-bit),?" newline bitfld.long 0x30 11.--12. "PSIZE,peripheral data size" "0: byte (8-bit),1: half-word (16-bit),2: word (32-bit),?" bitfld.long 0x30 10. "MINC,memory increment mode" "0: memory address pointer is fixed,1: memory address pointer is incremented after each.." newline bitfld.long 0x30 9. "PINC,peripheral increment mode" "0: peripheral address pointer fixed,1: peripheral address pointer incremented after.." bitfld.long 0x30 8. "CIRC,circular mode" "0: circular mode disabled,1: circular mode enabled" newline bitfld.long 0x30 6.--7. "DIR,data transfer direction" "0: peripheral-to-memory,1: memory-to-peripheral,2: memory-to-memory,?" bitfld.long 0x30 5. "PFCTRL,peripheral flow controller" "0: DMA is the flow controller.,1: The peripheral is the flow controller." newline bitfld.long 0x30 4. "TCIE,transfer complete interrupt enable" "0: TC interrupt disabled,1: TC interrupt enabled" bitfld.long 0x30 3. "HTIE,half transfer interrupt enable" "0: HT interrupt disabled,1: HT interrupt enabled" newline bitfld.long 0x30 2. "TEIE,transfer error interrupt enable" "0: TE interrupt disabled,1: TE interrupt enabled" bitfld.long 0x30 1. "DMEIE,direct mode error interrupt enable" "0: DME interrupt disabled,1: DME interrupt enabled" newline bitfld.long 0x30 0. "EN,stream enable / flag stream ready when read low" "0: stream disabled,1: stream enabled" line.long 0x34 "DMA_S2NDTR,DMA stream 2 number of data register" hexmask.long.word 0x34 0.--15. 1. "NDT,number of data items to transfer (0 up to 65535)" line.long 0x38 "DMA_S2PAR,DMA stream 2 peripheral address register" hexmask.long 0x38 0.--31. 1. "PAR,peripheral address" line.long 0x3C "DMA_S2M0AR,DMA stream 2 memory 0 address register" hexmask.long 0x3C 0.--31. 1. "M0A,memory 0 address" line.long 0x40 "DMA_S2M1AR,DMA stream 2 memory 1 address register" hexmask.long 0x40 0.--31. 1. "M1A,memory 1 address (used in case of double-buffer mode)" line.long 0x44 "DMA_S2FCR,DMA stream 2 FIFO control register" bitfld.long 0x44 7. "FEIE,FIFO error interrupt enable" "0: FE interrupt disabled,1: FE interrupt enabled" rbitfld.long 0x44 3.--5. "FS,FIFO status" "0: 0 < fifo_level < 1/4,1: 1/4 ≤ fifo_level < 1/2,2: 1/2 ≤ fifo_level < 3/4,3: 3/4 ≤ fifo_level < full,4: FIFO is empty,5: FIFO is full,?,?" newline bitfld.long 0x44 2. "DMDIS,direct mode disable" "0: direct mode enabled,1: direct mode disabled" bitfld.long 0x44 0.--1. "FTH,FIFO threshold selection" "0: 1/4 full FIFO,1: 1/2 full FIFO,2: 3/4 full FIFO,3: full FIFO" line.long 0x48 "DMA_S3CR,DMA stream 3 configuration register" bitfld.long 0x48 23.--24. "MBURST,memory burst transfer configuration" "0: single transfer,1: INCR4 (incremental burst of 4 beats),2: INCR8 (incremental burst of 8 beats),3: INCR16 (incremental burst of 16 beats)" bitfld.long 0x48 21.--22. "PBURST,peripheral burst transfer configuration" "0: single transfer,1: INCR4 (incremental burst of 4 beats),2: INCR8 (incremental burst of 8 beats),3: INCR16 (incremental burst of 16 beats)" newline bitfld.long 0x48 20. "TRBUFF,Enable the DMA to handle bufferable transfers." "0: bufferable transfers not enabled,1: bufferable transfers enabled" bitfld.long 0x48 19. "CT,current target (only in double-buffer mode)" "0: current target memory is Memory 0 (addressed by..,1: current target memory is Memory 1 (addressed by.." newline bitfld.long 0x48 18. "DBM,double-buffer mode" "0: no buffer switching at the end of transfer,1: memory target switched at the end of the DMA.." bitfld.long 0x48 16.--17. "PL,priority level" "0: low,1: medium,2: high,3: very high" newline bitfld.long 0x48 15. "PINCOS,peripheral increment offset size" "0: The offset size for the peripheral address..,1: The offset size for the peripheral address.." bitfld.long 0x48 13.--14. "MSIZE,memory data size" "0: byte (8-bit),1: half-word (16-bit),2: word (32-bit),?" newline bitfld.long 0x48 11.--12. "PSIZE,peripheral data size" "0: byte (8-bit),1: half-word (16-bit),2: word (32-bit),?" bitfld.long 0x48 10. "MINC,memory increment mode" "0: memory address pointer is fixed,1: memory address pointer is incremented after each.." newline bitfld.long 0x48 9. "PINC,peripheral increment mode" "0: peripheral address pointer fixed,1: peripheral address pointer incremented after.." bitfld.long 0x48 8. "CIRC,circular mode" "0: circular mode disabled,1: circular mode enabled" newline bitfld.long 0x48 6.--7. "DIR,data transfer direction" "0: peripheral-to-memory,1: memory-to-peripheral,2: memory-to-memory,?" bitfld.long 0x48 5. "PFCTRL,peripheral flow controller" "0: DMA is the flow controller.,1: The peripheral is the flow controller." newline bitfld.long 0x48 4. "TCIE,transfer complete interrupt enable" "0: TC interrupt disabled,1: TC interrupt enabled" bitfld.long 0x48 3. "HTIE,half transfer interrupt enable" "0: HT interrupt disabled,1: HT interrupt enabled" newline bitfld.long 0x48 2. "TEIE,transfer error interrupt enable" "0: TE interrupt disabled,1: TE interrupt enabled" bitfld.long 0x48 1. "DMEIE,direct mode error interrupt enable" "0: DME interrupt disabled,1: DME interrupt enabled" newline bitfld.long 0x48 0. "EN,stream enable / flag stream ready when read low" "0: stream disabled,1: stream enabled" line.long 0x4C "DMA_S3NDTR,DMA stream 3 number of data register" hexmask.long.word 0x4C 0.--15. 1. "NDT,number of data items to transfer (0 up to 65535)" line.long 0x50 "DMA_S3PAR,DMA stream 3 peripheral address register" hexmask.long 0x50 0.--31. 1. "PAR,peripheral address" line.long 0x54 "DMA_S3M0AR,DMA stream 3 memory 0 address register" hexmask.long 0x54 0.--31. 1. "M0A,memory 0 address" line.long 0x58 "DMA_S3M1AR,DMA stream 3 memory 1 address register" hexmask.long 0x58 0.--31. 1. "M1A,memory 1 address (used in case of double-buffer mode)" line.long 0x5C "DMA_S3FCR,DMA stream 3 FIFO control register" bitfld.long 0x5C 7. "FEIE,FIFO error interrupt enable" "0: FE interrupt disabled,1: FE interrupt enabled" rbitfld.long 0x5C 3.--5. "FS,FIFO status" "0: 0 < fifo_level < 1/4,1: 1/4 ≤ fifo_level < 1/2,2: 1/2 ≤ fifo_level < 3/4,3: 3/4 ≤ fifo_level < full,4: FIFO is empty,5: FIFO is full,?,?" newline bitfld.long 0x5C 2. "DMDIS,direct mode disable" "0: direct mode enabled,1: direct mode disabled" bitfld.long 0x5C 0.--1. "FTH,FIFO threshold selection" "0: 1/4 full FIFO,1: 1/2 full FIFO,2: 3/4 full FIFO,3: full FIFO" line.long 0x60 "DMA_S4CR,DMA stream 4 configuration register" bitfld.long 0x60 23.--24. "MBURST,memory burst transfer configuration" "0: single transfer,1: INCR4 (incremental burst of 4 beats),2: INCR8 (incremental burst of 8 beats),3: INCR16 (incremental burst of 16 beats)" bitfld.long 0x60 21.--22. "PBURST,peripheral burst transfer configuration" "0: single transfer,1: INCR4 (incremental burst of 4 beats),2: INCR8 (incremental burst of 8 beats),3: INCR16 (incremental burst of 16 beats)" newline bitfld.long 0x60 20. "TRBUFF,Enable the DMA to handle bufferable transfers." "0: bufferable transfers not enabled,1: bufferable transfers enabled" bitfld.long 0x60 19. "CT,current target (only in double-buffer mode)" "0: current target memory is Memory 0 (addressed by..,1: current target memory is Memory 1 (addressed by.." newline bitfld.long 0x60 18. "DBM,double-buffer mode" "0: no buffer switching at the end of transfer,1: memory target switched at the end of the DMA.." bitfld.long 0x60 16.--17. "PL,priority level" "0: low,1: medium,2: high,3: very high" newline bitfld.long 0x60 15. "PINCOS,peripheral increment offset size" "0: The offset size for the peripheral address..,1: The offset size for the peripheral address.." bitfld.long 0x60 13.--14. "MSIZE,memory data size" "0: byte (8-bit),1: half-word (16-bit),2: word (32-bit),?" newline bitfld.long 0x60 11.--12. "PSIZE,peripheral data size" "0: byte (8-bit),1: half-word (16-bit),2: word (32-bit),?" bitfld.long 0x60 10. "MINC,memory increment mode" "0: memory address pointer is fixed,1: memory address pointer is incremented after each.." newline bitfld.long 0x60 9. "PINC,peripheral increment mode" "0: peripheral address pointer fixed,1: peripheral address pointer incremented after.." bitfld.long 0x60 8. "CIRC,circular mode" "0: circular mode disabled,1: circular mode enabled" newline bitfld.long 0x60 6.--7. "DIR,data transfer direction" "0: peripheral-to-memory,1: memory-to-peripheral,2: memory-to-memory,?" bitfld.long 0x60 5. "PFCTRL,peripheral flow controller" "0: DMA is the flow controller.,1: The peripheral is the flow controller." newline bitfld.long 0x60 4. "TCIE,transfer complete interrupt enable" "0: TC interrupt disabled,1: TC interrupt enabled" bitfld.long 0x60 3. "HTIE,half transfer interrupt enable" "0: HT interrupt disabled,1: HT interrupt enabled" newline bitfld.long 0x60 2. "TEIE,transfer error interrupt enable" "0: TE interrupt disabled,1: TE interrupt enabled" bitfld.long 0x60 1. "DMEIE,direct mode error interrupt enable" "0: DME interrupt disabled,1: DME interrupt enabled" newline bitfld.long 0x60 0. "EN,stream enable / flag stream ready when read low" "0: stream disabled,1: stream enabled" line.long 0x64 "DMA_S4NDTR,DMA stream 4 number of data register" hexmask.long.word 0x64 0.--15. 1. "NDT,number of data items to transfer (0 up to 65535)" line.long 0x68 "DMA_S4PAR,DMA stream 4 peripheral address register" hexmask.long 0x68 0.--31. 1. "PAR,peripheral address" line.long 0x6C "DMA_S4M0AR,DMA stream 4 memory 0 address register" hexmask.long 0x6C 0.--31. 1. "M0A,memory 0 address" line.long 0x70 "DMA_S4M1AR,DMA stream 4 memory 1 address register" hexmask.long 0x70 0.--31. 1. "M1A,memory 1 address (used in case of double-buffer mode)" line.long 0x74 "DMA_S4FCR,DMA stream 4 FIFO control register" bitfld.long 0x74 7. "FEIE,FIFO error interrupt enable" "0: FE interrupt disabled,1: FE interrupt enabled" rbitfld.long 0x74 3.--5. "FS,FIFO status" "0: 0 < fifo_level < 1/4,1: 1/4 ≤ fifo_level < 1/2,2: 1/2 ≤ fifo_level < 3/4,3: 3/4 ≤ fifo_level < full,4: FIFO is empty,5: FIFO is full,?,?" newline bitfld.long 0x74 2. "DMDIS,direct mode disable" "0: direct mode enabled,1: direct mode disabled" bitfld.long 0x74 0.--1. "FTH,FIFO threshold selection" "0: 1/4 full FIFO,1: 1/2 full FIFO,2: 3/4 full FIFO,3: full FIFO" line.long 0x78 "DMA_S5CR,DMA stream 5 configuration register" bitfld.long 0x78 23.--24. "MBURST,memory burst transfer configuration" "0: single transfer,1: INCR4 (incremental burst of 4 beats),2: INCR8 (incremental burst of 8 beats),3: INCR16 (incremental burst of 16 beats)" bitfld.long 0x78 21.--22. "PBURST,peripheral burst transfer configuration" "0: single transfer,1: INCR4 (incremental burst of 4 beats),2: INCR8 (incremental burst of 8 beats),3: INCR16 (incremental burst of 16 beats)" newline bitfld.long 0x78 20. "TRBUFF,Enable the DMA to handle bufferable transfers." "0: bufferable transfers not enabled,1: bufferable transfers enabled" bitfld.long 0x78 19. "CT,current target (only in double-buffer mode)" "0: current target memory is Memory 0 (addressed by..,1: current target memory is Memory 1 (addressed by.." newline bitfld.long 0x78 18. "DBM,double-buffer mode" "0: no buffer switching at the end of transfer,1: memory target switched at the end of the DMA.." bitfld.long 0x78 16.--17. "PL,priority level" "0: low,1: medium,2: high,3: very high" newline bitfld.long 0x78 15. "PINCOS,peripheral increment offset size" "0: The offset size for the peripheral address..,1: The offset size for the peripheral address.." bitfld.long 0x78 13.--14. "MSIZE,memory data size" "0: byte (8-bit),1: half-word (16-bit),2: word (32-bit),?" newline bitfld.long 0x78 11.--12. "PSIZE,peripheral data size" "0: byte (8-bit),1: half-word (16-bit),2: word (32-bit),?" bitfld.long 0x78 10. "MINC,memory increment mode" "0: memory address pointer is fixed,1: memory address pointer is incremented after each.." newline bitfld.long 0x78 9. "PINC,peripheral increment mode" "0: peripheral address pointer fixed,1: peripheral address pointer incremented after.." bitfld.long 0x78 8. "CIRC,circular mode" "0: circular mode disabled,1: circular mode enabled" newline bitfld.long 0x78 6.--7. "DIR,data transfer direction" "0: peripheral-to-memory,1: memory-to-peripheral,2: memory-to-memory,?" bitfld.long 0x78 5. "PFCTRL,peripheral flow controller" "0: DMA is the flow controller.,1: The peripheral is the flow controller." newline bitfld.long 0x78 4. "TCIE,transfer complete interrupt enable" "0: TC interrupt disabled,1: TC interrupt enabled" bitfld.long 0x78 3. "HTIE,half transfer interrupt enable" "0: HT interrupt disabled,1: HT interrupt enabled" newline bitfld.long 0x78 2. "TEIE,transfer error interrupt enable" "0: TE interrupt disabled,1: TE interrupt enabled" bitfld.long 0x78 1. "DMEIE,direct mode error interrupt enable" "0: DME interrupt disabled,1: DME interrupt enabled" newline bitfld.long 0x78 0. "EN,stream enable / flag stream ready when read low" "0: stream disabled,1: stream enabled" line.long 0x7C "DMA_S5NDTR,DMA stream 5 number of data register" hexmask.long.word 0x7C 0.--15. 1. "NDT,number of data items to transfer (0 up to 65535)" line.long 0x80 "DMA_S5PAR,DMA stream 5 peripheral address register" hexmask.long 0x80 0.--31. 1. "PAR,peripheral address" line.long 0x84 "DMA_S5M0AR,DMA stream 5 memory 0 address register" hexmask.long 0x84 0.--31. 1. "M0A,memory 0 address" line.long 0x88 "DMA_S5M1AR,DMA stream 5 memory 1 address register" hexmask.long 0x88 0.--31. 1. "M1A,memory 1 address (used in case of double-buffer mode)" line.long 0x8C "DMA_S5FCR,DMA stream 5 FIFO control register" bitfld.long 0x8C 7. "FEIE,FIFO error interrupt enable" "0: FE interrupt disabled,1: FE interrupt enabled" rbitfld.long 0x8C 3.--5. "FS,FIFO status" "0: 0 < fifo_level < 1/4,1: 1/4 ≤ fifo_level < 1/2,2: 1/2 ≤ fifo_level < 3/4,3: 3/4 ≤ fifo_level < full,4: FIFO is empty,5: FIFO is full,?,?" newline bitfld.long 0x8C 2. "DMDIS,direct mode disable" "0: direct mode enabled,1: direct mode disabled" bitfld.long 0x8C 0.--1. "FTH,FIFO threshold selection" "0: 1/4 full FIFO,1: 1/2 full FIFO,2: 3/4 full FIFO,3: full FIFO" line.long 0x90 "DMA_S6CR,DMA stream 6 configuration register" bitfld.long 0x90 23.--24. "MBURST,memory burst transfer configuration" "0: single transfer,1: INCR4 (incremental burst of 4 beats),2: INCR8 (incremental burst of 8 beats),3: INCR16 (incremental burst of 16 beats)" bitfld.long 0x90 21.--22. "PBURST,peripheral burst transfer configuration" "0: single transfer,1: INCR4 (incremental burst of 4 beats),2: INCR8 (incremental burst of 8 beats),3: INCR16 (incremental burst of 16 beats)" newline bitfld.long 0x90 20. "TRBUFF,Enable the DMA to handle bufferable transfers." "0: bufferable transfers not enabled,1: bufferable transfers enabled" bitfld.long 0x90 19. "CT,current target (only in double-buffer mode)" "0: current target memory is Memory 0 (addressed by..,1: current target memory is Memory 1 (addressed by.." newline bitfld.long 0x90 18. "DBM,double-buffer mode" "0: no buffer switching at the end of transfer,1: memory target switched at the end of the DMA.." bitfld.long 0x90 16.--17. "PL,priority level" "0: low,1: medium,2: high,3: very high" newline bitfld.long 0x90 15. "PINCOS,peripheral increment offset size" "0: The offset size for the peripheral address..,1: The offset size for the peripheral address.." bitfld.long 0x90 13.--14. "MSIZE,memory data size" "0: byte (8-bit),1: half-word (16-bit),2: word (32-bit),?" newline bitfld.long 0x90 11.--12. "PSIZE,peripheral data size" "0: byte (8-bit),1: half-word (16-bit),2: word (32-bit),?" bitfld.long 0x90 10. "MINC,memory increment mode" "0: memory address pointer is fixed,1: memory address pointer is incremented after each.." newline bitfld.long 0x90 9. "PINC,peripheral increment mode" "0: peripheral address pointer fixed,1: peripheral address pointer incremented after.." bitfld.long 0x90 8. "CIRC,circular mode" "0: circular mode disabled,1: circular mode enabled" newline bitfld.long 0x90 6.--7. "DIR,data transfer direction" "0: peripheral-to-memory,1: memory-to-peripheral,2: memory-to-memory,?" bitfld.long 0x90 5. "PFCTRL,peripheral flow controller" "0: DMA is the flow controller.,1: The peripheral is the flow controller." newline bitfld.long 0x90 4. "TCIE,transfer complete interrupt enable" "0: TC interrupt disabled,1: TC interrupt enabled" bitfld.long 0x90 3. "HTIE,half transfer interrupt enable" "0: HT interrupt disabled,1: HT interrupt enabled" newline bitfld.long 0x90 2. "TEIE,transfer error interrupt enable" "0: TE interrupt disabled,1: TE interrupt enabled" bitfld.long 0x90 1. "DMEIE,direct mode error interrupt enable" "0: DME interrupt disabled,1: DME interrupt enabled" newline bitfld.long 0x90 0. "EN,stream enable / flag stream ready when read low" "0: stream disabled,1: stream enabled" line.long 0x94 "DMA_S6NDTR,DMA stream 6 number of data register" hexmask.long.word 0x94 0.--15. 1. "NDT,number of data items to transfer (0 up to 65535)" line.long 0x98 "DMA_S6PAR,DMA stream 6 peripheral address register" hexmask.long 0x98 0.--31. 1. "PAR,peripheral address" line.long 0x9C "DMA_S6M0AR,DMA stream 6 memory 0 address register" hexmask.long 0x9C 0.--31. 1. "M0A,memory 0 address" line.long 0xA0 "DMA_S6M1AR,DMA stream 6 memory 1 address register" hexmask.long 0xA0 0.--31. 1. "M1A,memory 1 address (used in case of double-buffer mode)" line.long 0xA4 "DMA_S6FCR,DMA stream 6 FIFO control register" bitfld.long 0xA4 7. "FEIE,FIFO error interrupt enable" "0: FE interrupt disabled,1: FE interrupt enabled" rbitfld.long 0xA4 3.--5. "FS,FIFO status" "0: 0 < fifo_level < 1/4,1: 1/4 ≤ fifo_level < 1/2,2: 1/2 ≤ fifo_level < 3/4,3: 3/4 ≤ fifo_level < full,4: FIFO is empty,5: FIFO is full,?,?" newline bitfld.long 0xA4 2. "DMDIS,direct mode disable" "0: direct mode enabled,1: direct mode disabled" bitfld.long 0xA4 0.--1. "FTH,FIFO threshold selection" "0: 1/4 full FIFO,1: 1/2 full FIFO,2: 3/4 full FIFO,3: full FIFO" line.long 0xA8 "DMA_S7CR,DMA stream 7 configuration register" bitfld.long 0xA8 23.--24. "MBURST,memory burst transfer configuration" "0: single transfer,1: INCR4 (incremental burst of 4 beats),2: INCR8 (incremental burst of 8 beats),3: INCR16 (incremental burst of 16 beats)" bitfld.long 0xA8 21.--22. "PBURST,peripheral burst transfer configuration" "0: single transfer,1: INCR4 (incremental burst of 4 beats),2: INCR8 (incremental burst of 8 beats),3: INCR16 (incremental burst of 16 beats)" newline bitfld.long 0xA8 20. "TRBUFF,Enable the DMA to handle bufferable transfers." "0: bufferable transfers not enabled,1: bufferable transfers enabled" bitfld.long 0xA8 19. "CT,current target (only in double-buffer mode)" "0: current target memory is Memory 0 (addressed by..,1: current target memory is Memory 1 (addressed by.." newline bitfld.long 0xA8 18. "DBM,double-buffer mode" "0: no buffer switching at the end of transfer,1: memory target switched at the end of the DMA.." bitfld.long 0xA8 16.--17. "PL,priority level" "0: low,1: medium,2: high,3: very high" newline bitfld.long 0xA8 15. "PINCOS,peripheral increment offset size" "0: The offset size for the peripheral address..,1: The offset size for the peripheral address.." bitfld.long 0xA8 13.--14. "MSIZE,memory data size" "0: byte (8-bit),1: half-word (16-bit),2: word (32-bit),?" newline bitfld.long 0xA8 11.--12. "PSIZE,peripheral data size" "0: byte (8-bit),1: half-word (16-bit),2: word (32-bit),?" bitfld.long 0xA8 10. "MINC,memory increment mode" "0: memory address pointer is fixed,1: memory address pointer is incremented after each.." newline bitfld.long 0xA8 9. "PINC,peripheral increment mode" "0: peripheral address pointer fixed,1: peripheral address pointer incremented after.." bitfld.long 0xA8 8. "CIRC,circular mode" "0: circular mode disabled,1: circular mode enabled" newline bitfld.long 0xA8 6.--7. "DIR,data transfer direction" "0: peripheral-to-memory,1: memory-to-peripheral,2: memory-to-memory,?" bitfld.long 0xA8 5. "PFCTRL,peripheral flow controller" "0: DMA is the flow controller.,1: The peripheral is the flow controller." newline bitfld.long 0xA8 4. "TCIE,transfer complete interrupt enable" "0: TC interrupt disabled,1: TC interrupt enabled" bitfld.long 0xA8 3. "HTIE,half transfer interrupt enable" "0: HT interrupt disabled,1: HT interrupt enabled" newline bitfld.long 0xA8 2. "TEIE,transfer error interrupt enable" "0: TE interrupt disabled,1: TE interrupt enabled" bitfld.long 0xA8 1. "DMEIE,direct mode error interrupt enable" "0: DME interrupt disabled,1: DME interrupt enabled" newline bitfld.long 0xA8 0. "EN,stream enable / flag stream ready when read low" "0: stream disabled,1: stream enabled" line.long 0xAC "DMA_S7NDTR,DMA stream 7 number of data register" hexmask.long.word 0xAC 0.--15. 1. "NDT,number of data items to transfer (0 up to 65535)" line.long 0xB0 "DMA_S7PAR,DMA stream 7 peripheral address register" hexmask.long 0xB0 0.--31. 1. "PAR,peripheral address" line.long 0xB4 "DMA_S7M0AR,DMA stream 7 memory 0 address register" hexmask.long 0xB4 0.--31. 1. "M0A,memory 0 address" line.long 0xB8 "DMA_S7M1AR,DMA stream 7 memory 1 address register" hexmask.long 0xB8 0.--31. 1. "M1A,memory 1 address (used in case of double-buffer mode)" line.long 0xBC "DMA_S7FCR,DMA stream 7 FIFO control register" bitfld.long 0xBC 7. "FEIE,FIFO error interrupt enable" "0: FE interrupt disabled,1: FE interrupt enabled" rbitfld.long 0xBC 3.--5. "FS,FIFO status" "0: 0 < fifo_level < 1/4,1: 1/4 ≤ fifo_level < 1/2,2: 1/2 ≤ fifo_level < 3/4,3: 3/4 ≤ fifo_level < full,4: FIFO is empty,5: FIFO is full,?,?" newline bitfld.long 0xBC 2. "DMDIS,direct mode disable" "0: direct mode enabled,1: direct mode disabled" bitfld.long 0xBC 0.--1. "FTH,FIFO threshold selection" "0: 1/4 full FIFO,1: 1/2 full FIFO,2: 3/4 full FIFO,3: full FIFO" rgroup.long 0x3EC++0x13 line.long 0x0 "DMA_HWCFGR2,DMA hardware configuration 2 register" bitfld.long 0x0 8.--10. "CHSEL_WIDTH,bit width of the CHSEL field of any DMA_SxCR register common to all streams" "0: no programmable selection,1: 2 channels programmable selection,2: up to 8 channels programmable selection,3: up to 16 channels programmable selection,4: up to 32 channels programmable selection,5: up to 64 channels programmable selection,6: up to 128 channels programmable selection,?" bitfld.long 0x0 4. "WRITE_BUFFERABLE,In any case DMA acknowledge signal is asserted one cycle after the address phase of the bus access on its AHB peripheral master port." "0: DMA acknowledge signal is de-asserted one cycle..,1: DMA acknowledge signal is de-asserted exactly.." newline bitfld.long 0x0 0.--1. "FIFO_SIZE,FIFO size common to all streams" "0: 2-word FIFO,1: 4-word FIFO,2: 8-word FIFO,3: 16-word FIFO" line.long 0x4 "DMA_HWCFGR1,DMA hardware configuration 1 register" bitfld.long 0x4 28.--29. "DMA_DEF7,type of the stream 7" "0: none,1: regular,2: double-buffer,3: Reserved" bitfld.long 0x4 24.--25. "DMA_DEF6,type of the stream 6" "0: none,1: regular,2: double-buffer,3: Reserved" newline bitfld.long 0x4 20.--21. "DMA_DEF5,type of the stream 5" "0: none,1: regular,2: double-buffer,3: Reserved" bitfld.long 0x4 16.--17. "DMA_DEF4,type of the stream 4" "0: none,1: regular,2: double-buffer,3: Reserved" newline bitfld.long 0x4 12.--13. "DMA_DEF3,type of the stream 3" "0: none,1: regular,2: double-buffer,3: Reserved" bitfld.long 0x4 8.--9. "DMA_DEF2,type of the stream 2" "0: none,1: regular,2: double-buffer,3: Reserved" newline bitfld.long 0x4 4.--5. "DMA_DEF1,type of the stream 1" "0: none,1: regular,2: double-buffer,3: Reserved" bitfld.long 0x4 0.--1. "DMA_DEF0,type of the stream 0" "0: none,1: regular,2: double-buffer,3: Reserved" line.long 0x8 "DMA_VERR,DMA version register" hexmask.long.byte 0x8 4.--7. 1. "MAJREV,major IP revision" hexmask.long.byte 0x8 0.--3. 1. "MINREV,minor IP revision" line.long 0xC "DMA_IPDR,DMA identification register" hexmask.long 0xC 0.--31. 1. "ID,size identification" line.long 0x10 "DMA_SIDR,DMA size identification register" hexmask.long 0x10 0.--31. 1. "SID,size identification" tree.end endif sif (cpuis("STM32MP13*")) tree "DMA2" base ad:0x48001000 rgroup.long 0x0++0x7 line.long 0x0 "DMA_LISR,DMA low interrupt status register" bitfld.long 0x0 27. "TCIF3,stream x transfer complete interrupt flag (x = 3 to 0)" "0: no transfer complete event on stream x,1: a transfer complete event occurred on stream x" bitfld.long 0x0 26. "HTIF3,stream x half transfer interrupt flag (x = 3 to 0)" "0: no half transfer event on stream x,1: a half transfer event occurred on stream x" newline bitfld.long 0x0 25. "TEIF3,stream x transfer error interrupt flag (x = 3 to 0)" "0: no transfer error on stream x,1: a transfer error occurred on stream x" bitfld.long 0x0 24. "DMEIF3,stream x direct mode error interrupt flag (x = 3 to 0)" "0: No direct mode error on stream x,1: a direct mode error occurred on stream x" newline bitfld.long 0x0 22. "FEIF3,stream x FIFO error interrupt flag (x = 3 to 0)" "0: no FIFO error event on stream x,1: a FIFO error event occurred on stream x" bitfld.long 0x0 21. "TCIF2,stream x transfer complete interrupt flag (x = 3 to 0)" "0: no transfer complete event on stream x,1: a transfer complete event occurred on stream x" newline bitfld.long 0x0 20. "HTIF2,stream x half transfer interrupt flag (x = 3 to 0)" "0: no half transfer event on stream x,1: a half transfer event occurred on stream x" bitfld.long 0x0 19. "TEIF2,stream x transfer error interrupt flag (x = 3 to 0)" "0: no transfer error on stream x,1: a transfer error occurred on stream x" newline bitfld.long 0x0 18. "DMEIF2,stream x direct mode error interrupt flag (x = 3 to 0)" "0: No direct mode error on stream x,1: a direct mode error occurred on stream x" bitfld.long 0x0 16. "FEIF2,stream x FIFO error interrupt flag (x = 3 to 0)" "0: no FIFO error event on stream x,1: a FIFO error event occurred on stream x" newline bitfld.long 0x0 11. "TCIF1,stream x transfer complete interrupt flag (x = 3 to 0)" "0: no transfer complete event on stream x,1: a transfer complete event occurred on stream x" bitfld.long 0x0 10. "HTIF1,stream x half transfer interrupt flag (x = 3 to 0)" "0: no half transfer event on stream x,1: a half transfer event occurred on stream x" newline bitfld.long 0x0 9. "TEIF1,stream x transfer error interrupt flag (x = 3 to 0)" "0: no transfer error on stream x,1: a transfer error occurred on stream x" bitfld.long 0x0 8. "DMEIF1,stream x direct mode error interrupt flag (x = 3 to 0)" "0: No direct mode error on stream x,1: a direct mode error occurred on stream x" newline bitfld.long 0x0 6. "FEIF1,stream x FIFO error interrupt flag (x = 3 to 0)" "0: no FIFO error event on stream x,1: a FIFO error event occurred on stream x" bitfld.long 0x0 5. "TCIF0,stream x transfer complete interrupt flag (x = 3 to 0)" "0: no transfer complete event on stream x,1: a transfer complete event occurred on stream x" newline bitfld.long 0x0 4. "HTIF0,stream x half transfer interrupt flag (x = 3 to 0)" "0: no half transfer event on stream x,1: a half transfer event occurred on stream x" bitfld.long 0x0 3. "TEIF0,stream x transfer error interrupt flag (x = 3 to 0)" "0: no transfer error on stream x,1: a transfer error occurred on stream x" newline bitfld.long 0x0 2. "DMEIF0,stream x direct mode error interrupt flag (x = 3 to 0)" "0: No direct mode error on stream x,1: a direct mode error occurred on stream x" bitfld.long 0x0 0. "FEIF0,stream x FIFO error interrupt flag (x = 3 to 0)" "0: no FIFO error event on stream x,1: a FIFO error event occurred on stream x" line.long 0x4 "DMA_HISR,DMA high interrupt status register" bitfld.long 0x4 27. "TCIF7,stream x transfer complete interrupt flag (x = 7 to 4)" "0: no transfer complete event on stream x,1: a transfer complete event occurred on stream x" bitfld.long 0x4 26. "HTIF7,stream x half transfer interrupt flag (x = 7 to 4)" "0: no half transfer event on stream x,1: a half transfer event occurred on stream x" newline bitfld.long 0x4 25. "TEIF7,stream x transfer error interrupt flag (x = 7 to 4)" "0: no transfer error on stream x,1: a transfer error occurred on stream x" bitfld.long 0x4 24. "DMEIF7,stream x direct mode error interrupt flag (x = 7 to 4)" "0: no direct mode error on stream x,1: a direct mode error occurred on stream x" newline bitfld.long 0x4 22. "FEIF7,stream x FIFO error interrupt flag (x = 7 to 4)" "0: no FIFO error event on stream x,1: a FIFO error event occurred on stream x" bitfld.long 0x4 21. "TCIF6,stream x transfer complete interrupt flag (x = 7 to 4)" "0: no transfer complete event on stream x,1: a transfer complete event occurred on stream x" newline bitfld.long 0x4 20. "HTIF6,stream x half transfer interrupt flag (x = 7 to 4)" "0: no half transfer event on stream x,1: a half transfer event occurred on stream x" bitfld.long 0x4 19. "TEIF6,stream x transfer error interrupt flag (x = 7 to 4)" "0: no transfer error on stream x,1: a transfer error occurred on stream x" newline bitfld.long 0x4 18. "DMEIF6,stream x direct mode error interrupt flag (x = 7 to 4)" "0: no direct mode error on stream x,1: a direct mode error occurred on stream x" bitfld.long 0x4 16. "FEIF6,stream x FIFO error interrupt flag (x = 7 to 4)" "0: no FIFO error event on stream x,1: a FIFO error event occurred on stream x" newline bitfld.long 0x4 11. "TCIF5,stream x transfer complete interrupt flag (x = 7 to 4)" "0: no transfer complete event on stream x,1: a transfer complete event occurred on stream x" bitfld.long 0x4 10. "HTIF5,stream x half transfer interrupt flag (x = 7 to 4)" "0: no half transfer event on stream x,1: a half transfer event occurred on stream x" newline bitfld.long 0x4 9. "TEIF5,stream x transfer error interrupt flag (x = 7 to 4)" "0: no transfer error on stream x,1: a transfer error occurred on stream x" bitfld.long 0x4 8. "DMEIF5,stream x direct mode error interrupt flag (x = 7 to 4)" "0: no direct mode error on stream x,1: a direct mode error occurred on stream x" newline bitfld.long 0x4 6. "FEIF5,stream x FIFO error interrupt flag (x = 7 to 4)" "0: no FIFO error event on stream x,1: a FIFO error event occurred on stream x" bitfld.long 0x4 5. "TCIF4,stream x transfer complete interrupt flag (x = 7 to 4)" "0: no transfer complete event on stream x,1: a transfer complete event occurred on stream x" newline bitfld.long 0x4 4. "HTIF4,stream x half transfer interrupt flag (x = 7 to 4)" "0: no half transfer event on stream x,1: a half transfer event occurred on stream x" bitfld.long 0x4 3. "TEIF4,stream x transfer error interrupt flag (x = 7 to 4)" "0: no transfer error on stream x,1: a transfer error occurred on stream x" newline bitfld.long 0x4 2. "DMEIF4,stream x direct mode error interrupt flag (x = 7 to 4)" "0: no direct mode error on stream x,1: a direct mode error occurred on stream x" bitfld.long 0x4 0. "FEIF4,stream x FIFO error interrupt flag (x = 7 to 4)" "0: no FIFO error event on stream x,1: a FIFO error event occurred on stream x" wgroup.long 0x8++0x7 line.long 0x0 "DMA_LIFCR,DMA low interrupt flag clear register" bitfld.long 0x0 27. "CTCIF3,stream x clear transfer complete interrupt flag (x = 3 to 0)" "0,1" bitfld.long 0x0 26. "CHTIF3,stream x clear half transfer interrupt flag (x = 3 to 0)" "0,1" newline bitfld.long 0x0 25. "CTEIF3,Stream x clear transfer error interrupt flag (x = 3 to 0)" "0,1" bitfld.long 0x0 24. "CDMEIF3,stream x clear direct mode error interrupt flag (x = 3 to 0)" "0,1" newline bitfld.long 0x0 22. "CFEIF3,stream x clear FIFO error interrupt flag (x = 3 to 0)" "0,1" bitfld.long 0x0 21. "CTCIF2,stream x clear transfer complete interrupt flag (x = 3 to 0)" "0,1" newline bitfld.long 0x0 20. "CHTIF2,stream x clear half transfer interrupt flag (x = 3 to 0)" "0,1" bitfld.long 0x0 19. "CTEIF2,Stream x clear transfer error interrupt flag (x = 3 to 0)" "0,1" newline bitfld.long 0x0 18. "CDMEIF2,stream x clear direct mode error interrupt flag (x = 3 to 0)" "0,1" bitfld.long 0x0 16. "CFEIF2,stream x clear FIFO error interrupt flag (x = 3 to 0)" "0,1" newline bitfld.long 0x0 11. "CTCIF1,stream x clear transfer complete interrupt flag (x = 3 to 0)" "0,1" bitfld.long 0x0 10. "CHTIF1,stream x clear half transfer interrupt flag (x = 3 to 0)" "0,1" newline bitfld.long 0x0 9. "CTEIF1,Stream x clear transfer error interrupt flag (x = 3 to 0)" "0,1" bitfld.long 0x0 8. "CDMEIF1,stream x clear direct mode error interrupt flag (x = 3 to 0)" "0,1" newline bitfld.long 0x0 6. "CFEIF1,stream x clear FIFO error interrupt flag (x = 3 to 0)" "0,1" bitfld.long 0x0 5. "CTCIF0,stream x clear transfer complete interrupt flag (x = 3 to 0)" "0,1" newline bitfld.long 0x0 4. "CHTIF0,stream x clear half transfer interrupt flag (x = 3 to 0)" "0,1" bitfld.long 0x0 3. "CTEIF0,Stream x clear transfer error interrupt flag (x = 3 to 0)" "0,1" newline bitfld.long 0x0 2. "CDMEIF0,stream x clear direct mode error interrupt flag (x = 3 to 0)" "0,1" bitfld.long 0x0 0. "CFEIF0,stream x clear FIFO error interrupt flag (x = 3 to 0)" "0,1" line.long 0x4 "DMA_HIFCR,DMA high interrupt flag clear register" bitfld.long 0x4 27. "CTCIF7,stream x clear transfer complete interrupt flag (x = 7 to 4)" "0,1" bitfld.long 0x4 26. "CHTIF7,stream x clear half transfer interrupt flag (x = 7 to 4)" "0,1" newline bitfld.long 0x4 25. "CTEIF7,stream x clear transfer error interrupt flag (x = 7 to 4)" "0,1" bitfld.long 0x4 24. "CDMEIF7,stream x clear direct mode error interrupt flag (x = 7 to 4)" "0,1" newline bitfld.long 0x4 22. "CFEIF7,stream x clear FIFO error interrupt flag (x = 7 to 4)" "0,1" bitfld.long 0x4 21. "CTCIF6,stream x clear transfer complete interrupt flag (x = 7 to 4)" "0,1" newline bitfld.long 0x4 20. "CHTIF6,stream x clear half transfer interrupt flag (x = 7 to 4)" "0,1" bitfld.long 0x4 19. "CTEIF6,stream x clear transfer error interrupt flag (x = 7 to 4)" "0,1" newline bitfld.long 0x4 18. "CDMEIF6,stream x clear direct mode error interrupt flag (x = 7 to 4)" "0,1" bitfld.long 0x4 16. "CFEIF6,stream x clear FIFO error interrupt flag (x = 7 to 4)" "0,1" newline bitfld.long 0x4 11. "CTCIF5,stream x clear transfer complete interrupt flag (x = 7 to 4)" "0,1" bitfld.long 0x4 10. "CHTIF5,stream x clear half transfer interrupt flag (x = 7 to 4)" "0,1" newline bitfld.long 0x4 9. "CTEIF5,stream x clear transfer error interrupt flag (x = 7 to 4)" "0,1" bitfld.long 0x4 8. "CDMEIF5,stream x clear direct mode error interrupt flag (x = 7 to 4)" "0,1" newline bitfld.long 0x4 6. "CFEIF5,stream x clear FIFO error interrupt flag (x = 7 to 4)" "0,1" bitfld.long 0x4 5. "CTCIF4,stream x clear transfer complete interrupt flag (x = 7 to 4)" "0,1" newline bitfld.long 0x4 4. "CHTIF4,stream x clear half transfer interrupt flag (x = 7 to 4)" "0,1" bitfld.long 0x4 3. "CTEIF4,stream x clear transfer error interrupt flag (x = 7 to 4)" "0,1" newline bitfld.long 0x4 2. "CDMEIF4,stream x clear direct mode error interrupt flag (x = 7 to 4)" "0,1" bitfld.long 0x4 0. "CFEIF4,stream x clear FIFO error interrupt flag (x = 7 to 4)" "0,1" group.long 0x10++0xBF line.long 0x0 "DMA_S0CR,DMA stream 0 configuration register" bitfld.long 0x0 23.--24. "MBURST,memory burst transfer configuration" "0: single transfer,1: INCR4 (incremental burst of 4 beats),2: INCR8 (incremental burst of 8 beats),3: INCR16 (incremental burst of 16 beats)" bitfld.long 0x0 21.--22. "PBURST,peripheral burst transfer configuration" "0: single transfer,1: INCR4 (incremental burst of 4 beats),2: INCR8 (incremental burst of 8 beats),3: INCR16 (incremental burst of 16 beats)" newline bitfld.long 0x0 20. "TRBUFF,Enable the DMA to handle bufferable transfers." "0: bufferable transfers not enabled,1: bufferable transfers enabled" bitfld.long 0x0 19. "CT,current target (only in double-buffer mode)" "0: current target memory is Memory 0 (addressed by..,1: current target memory is Memory 1 (addressed by.." newline bitfld.long 0x0 18. "DBM,double-buffer mode" "0: no buffer switching at the end of transfer,1: memory target switched at the end of the DMA.." bitfld.long 0x0 16.--17. "PL,priority level" "0: low,1: medium,2: high,3: very high" newline bitfld.long 0x0 15. "PINCOS,peripheral increment offset size" "0: The offset size for the peripheral address..,1: The offset size for the peripheral address.." bitfld.long 0x0 13.--14. "MSIZE,memory data size" "0: byte (8-bit),1: half-word (16-bit),2: word (32-bit),?" newline bitfld.long 0x0 11.--12. "PSIZE,peripheral data size" "0: byte (8-bit),1: half-word (16-bit),2: word (32-bit),?" bitfld.long 0x0 10. "MINC,memory increment mode" "0: memory address pointer is fixed,1: memory address pointer is incremented after each.." newline bitfld.long 0x0 9. "PINC,peripheral increment mode" "0: peripheral address pointer fixed,1: peripheral address pointer incremented after.." bitfld.long 0x0 8. "CIRC,circular mode" "0: circular mode disabled,1: circular mode enabled" newline bitfld.long 0x0 6.--7. "DIR,data transfer direction" "0: peripheral-to-memory,1: memory-to-peripheral,2: memory-to-memory,?" bitfld.long 0x0 5. "PFCTRL,peripheral flow controller" "0: DMA is the flow controller.,1: The peripheral is the flow controller." newline bitfld.long 0x0 4. "TCIE,transfer complete interrupt enable" "0: TC interrupt disabled,1: TC interrupt enabled" bitfld.long 0x0 3. "HTIE,half transfer interrupt enable" "0: HT interrupt disabled,1: HT interrupt enabled" newline bitfld.long 0x0 2. "TEIE,transfer error interrupt enable" "0: TE interrupt disabled,1: TE interrupt enabled" bitfld.long 0x0 1. "DMEIE,direct mode error interrupt enable" "0: DME interrupt disabled,1: DME interrupt enabled" newline bitfld.long 0x0 0. "EN,stream enable / flag stream ready when read low" "0: stream disabled,1: stream enabled" line.long 0x4 "DMA_S0NDTR,DMA stream 0 number of data register" hexmask.long.word 0x4 0.--15. 1. "NDT,number of data items to transfer (0 up to 65535)" line.long 0x8 "DMA_S0PAR,DMA stream 0 peripheral address register" hexmask.long 0x8 0.--31. 1. "PAR,peripheral address" line.long 0xC "DMA_S0M0AR,DMA stream 0 memory 0 address register" hexmask.long 0xC 0.--31. 1. "M0A,memory 0 address" line.long 0x10 "DMA_S0M1AR,DMA stream 0 memory 1 address register" hexmask.long 0x10 0.--31. 1. "M1A,memory 1 address (used in case of double-buffer mode)" line.long 0x14 "DMA_S0FCR,DMA stream 0 FIFO control register" bitfld.long 0x14 7. "FEIE,FIFO error interrupt enable" "0: FE interrupt disabled,1: FE interrupt enabled" rbitfld.long 0x14 3.--5. "FS,FIFO status" "0: 0 < fifo_level < 1/4,1: 1/4 ≤ fifo_level < 1/2,2: 1/2 ≤ fifo_level < 3/4,3: 3/4 ≤ fifo_level < full,4: FIFO is empty,5: FIFO is full,?,?" newline bitfld.long 0x14 2. "DMDIS,direct mode disable" "0: direct mode enabled,1: direct mode disabled" bitfld.long 0x14 0.--1. "FTH,FIFO threshold selection" "0: 1/4 full FIFO,1: 1/2 full FIFO,2: 3/4 full FIFO,3: full FIFO" line.long 0x18 "DMA_S1CR,DMA stream 1 configuration register" bitfld.long 0x18 23.--24. "MBURST,memory burst transfer configuration" "0: single transfer,1: INCR4 (incremental burst of 4 beats),2: INCR8 (incremental burst of 8 beats),3: INCR16 (incremental burst of 16 beats)" bitfld.long 0x18 21.--22. "PBURST,peripheral burst transfer configuration" "0: single transfer,1: INCR4 (incremental burst of 4 beats),2: INCR8 (incremental burst of 8 beats),3: INCR16 (incremental burst of 16 beats)" newline bitfld.long 0x18 20. "TRBUFF,Enable the DMA to handle bufferable transfers." "0: bufferable transfers not enabled,1: bufferable transfers enabled" bitfld.long 0x18 19. "CT,current target (only in double-buffer mode)" "0: current target memory is Memory 0 (addressed by..,1: current target memory is Memory 1 (addressed by.." newline bitfld.long 0x18 18. "DBM,double-buffer mode" "0: no buffer switching at the end of transfer,1: memory target switched at the end of the DMA.." bitfld.long 0x18 16.--17. "PL,priority level" "0: low,1: medium,2: high,3: very high" newline bitfld.long 0x18 15. "PINCOS,peripheral increment offset size" "0: The offset size for the peripheral address..,1: The offset size for the peripheral address.." bitfld.long 0x18 13.--14. "MSIZE,memory data size" "0: byte (8-bit),1: half-word (16-bit),2: word (32-bit),?" newline bitfld.long 0x18 11.--12. "PSIZE,peripheral data size" "0: byte (8-bit),1: half-word (16-bit),2: word (32-bit),?" bitfld.long 0x18 10. "MINC,memory increment mode" "0: memory address pointer is fixed,1: memory address pointer is incremented after each.." newline bitfld.long 0x18 9. "PINC,peripheral increment mode" "0: peripheral address pointer fixed,1: peripheral address pointer incremented after.." bitfld.long 0x18 8. "CIRC,circular mode" "0: circular mode disabled,1: circular mode enabled" newline bitfld.long 0x18 6.--7. "DIR,data transfer direction" "0: peripheral-to-memory,1: memory-to-peripheral,2: memory-to-memory,?" bitfld.long 0x18 5. "PFCTRL,peripheral flow controller" "0: DMA is the flow controller.,1: The peripheral is the flow controller." newline bitfld.long 0x18 4. "TCIE,transfer complete interrupt enable" "0: TC interrupt disabled,1: TC interrupt enabled" bitfld.long 0x18 3. "HTIE,half transfer interrupt enable" "0: HT interrupt disabled,1: HT interrupt enabled" newline bitfld.long 0x18 2. "TEIE,transfer error interrupt enable" "0: TE interrupt disabled,1: TE interrupt enabled" bitfld.long 0x18 1. "DMEIE,direct mode error interrupt enable" "0: DME interrupt disabled,1: DME interrupt enabled" newline bitfld.long 0x18 0. "EN,stream enable / flag stream ready when read low" "0: stream disabled,1: stream enabled" line.long 0x1C "DMA_S1NDTR,DMA stream 1 number of data register" hexmask.long.word 0x1C 0.--15. 1. "NDT,number of data items to transfer (0 up to 65535)" line.long 0x20 "DMA_S1PAR,DMA stream 1 peripheral address register" hexmask.long 0x20 0.--31. 1. "PAR,peripheral address" line.long 0x24 "DMA_S1M0AR,DMA stream 1 memory 0 address register" hexmask.long 0x24 0.--31. 1. "M0A,memory 0 address" line.long 0x28 "DMA_S1M1AR,DMA stream 1 memory 1 address register" hexmask.long 0x28 0.--31. 1. "M1A,memory 1 address (used in case of double-buffer mode)" line.long 0x2C "DMA_S1FCR,DMA stream 1 FIFO control register" bitfld.long 0x2C 7. "FEIE,FIFO error interrupt enable" "0: FE interrupt disabled,1: FE interrupt enabled" rbitfld.long 0x2C 3.--5. "FS,FIFO status" "0: 0 < fifo_level < 1/4,1: 1/4 ≤ fifo_level < 1/2,2: 1/2 ≤ fifo_level < 3/4,3: 3/4 ≤ fifo_level < full,4: FIFO is empty,5: FIFO is full,?,?" newline bitfld.long 0x2C 2. "DMDIS,direct mode disable" "0: direct mode enabled,1: direct mode disabled" bitfld.long 0x2C 0.--1. "FTH,FIFO threshold selection" "0: 1/4 full FIFO,1: 1/2 full FIFO,2: 3/4 full FIFO,3: full FIFO" line.long 0x30 "DMA_S2CR,DMA stream 2 configuration register" bitfld.long 0x30 23.--24. "MBURST,memory burst transfer configuration" "0: single transfer,1: INCR4 (incremental burst of 4 beats),2: INCR8 (incremental burst of 8 beats),3: INCR16 (incremental burst of 16 beats)" bitfld.long 0x30 21.--22. "PBURST,peripheral burst transfer configuration" "0: single transfer,1: INCR4 (incremental burst of 4 beats),2: INCR8 (incremental burst of 8 beats),3: INCR16 (incremental burst of 16 beats)" newline bitfld.long 0x30 20. "TRBUFF,Enable the DMA to handle bufferable transfers." "0: bufferable transfers not enabled,1: bufferable transfers enabled" bitfld.long 0x30 19. "CT,current target (only in double-buffer mode)" "0: current target memory is Memory 0 (addressed by..,1: current target memory is Memory 1 (addressed by.." newline bitfld.long 0x30 18. "DBM,double-buffer mode" "0: no buffer switching at the end of transfer,1: memory target switched at the end of the DMA.." bitfld.long 0x30 16.--17. "PL,priority level" "0: low,1: medium,2: high,3: very high" newline bitfld.long 0x30 15. "PINCOS,peripheral increment offset size" "0: The offset size for the peripheral address..,1: The offset size for the peripheral address.." bitfld.long 0x30 13.--14. "MSIZE,memory data size" "0: byte (8-bit),1: half-word (16-bit),2: word (32-bit),?" newline bitfld.long 0x30 11.--12. "PSIZE,peripheral data size" "0: byte (8-bit),1: half-word (16-bit),2: word (32-bit),?" bitfld.long 0x30 10. "MINC,memory increment mode" "0: memory address pointer is fixed,1: memory address pointer is incremented after each.." newline bitfld.long 0x30 9. "PINC,peripheral increment mode" "0: peripheral address pointer fixed,1: peripheral address pointer incremented after.." bitfld.long 0x30 8. "CIRC,circular mode" "0: circular mode disabled,1: circular mode enabled" newline bitfld.long 0x30 6.--7. "DIR,data transfer direction" "0: peripheral-to-memory,1: memory-to-peripheral,2: memory-to-memory,?" bitfld.long 0x30 5. "PFCTRL,peripheral flow controller" "0: DMA is the flow controller.,1: The peripheral is the flow controller." newline bitfld.long 0x30 4. "TCIE,transfer complete interrupt enable" "0: TC interrupt disabled,1: TC interrupt enabled" bitfld.long 0x30 3. "HTIE,half transfer interrupt enable" "0: HT interrupt disabled,1: HT interrupt enabled" newline bitfld.long 0x30 2. "TEIE,transfer error interrupt enable" "0: TE interrupt disabled,1: TE interrupt enabled" bitfld.long 0x30 1. "DMEIE,direct mode error interrupt enable" "0: DME interrupt disabled,1: DME interrupt enabled" newline bitfld.long 0x30 0. "EN,stream enable / flag stream ready when read low" "0: stream disabled,1: stream enabled" line.long 0x34 "DMA_S2NDTR,DMA stream 2 number of data register" hexmask.long.word 0x34 0.--15. 1. "NDT,number of data items to transfer (0 up to 65535)" line.long 0x38 "DMA_S2PAR,DMA stream 2 peripheral address register" hexmask.long 0x38 0.--31. 1. "PAR,peripheral address" line.long 0x3C "DMA_S2M0AR,DMA stream 2 memory 0 address register" hexmask.long 0x3C 0.--31. 1. "M0A,memory 0 address" line.long 0x40 "DMA_S2M1AR,DMA stream 2 memory 1 address register" hexmask.long 0x40 0.--31. 1. "M1A,memory 1 address (used in case of double-buffer mode)" line.long 0x44 "DMA_S2FCR,DMA stream 2 FIFO control register" bitfld.long 0x44 7. "FEIE,FIFO error interrupt enable" "0: FE interrupt disabled,1: FE interrupt enabled" rbitfld.long 0x44 3.--5. "FS,FIFO status" "0: 0 < fifo_level < 1/4,1: 1/4 ≤ fifo_level < 1/2,2: 1/2 ≤ fifo_level < 3/4,3: 3/4 ≤ fifo_level < full,4: FIFO is empty,5: FIFO is full,?,?" newline bitfld.long 0x44 2. "DMDIS,direct mode disable" "0: direct mode enabled,1: direct mode disabled" bitfld.long 0x44 0.--1. "FTH,FIFO threshold selection" "0: 1/4 full FIFO,1: 1/2 full FIFO,2: 3/4 full FIFO,3: full FIFO" line.long 0x48 "DMA_S3CR,DMA stream 3 configuration register" bitfld.long 0x48 23.--24. "MBURST,memory burst transfer configuration" "0: single transfer,1: INCR4 (incremental burst of 4 beats),2: INCR8 (incremental burst of 8 beats),3: INCR16 (incremental burst of 16 beats)" bitfld.long 0x48 21.--22. "PBURST,peripheral burst transfer configuration" "0: single transfer,1: INCR4 (incremental burst of 4 beats),2: INCR8 (incremental burst of 8 beats),3: INCR16 (incremental burst of 16 beats)" newline bitfld.long 0x48 20. "TRBUFF,Enable the DMA to handle bufferable transfers." "0: bufferable transfers not enabled,1: bufferable transfers enabled" bitfld.long 0x48 19. "CT,current target (only in double-buffer mode)" "0: current target memory is Memory 0 (addressed by..,1: current target memory is Memory 1 (addressed by.." newline bitfld.long 0x48 18. "DBM,double-buffer mode" "0: no buffer switching at the end of transfer,1: memory target switched at the end of the DMA.." bitfld.long 0x48 16.--17. "PL,priority level" "0: low,1: medium,2: high,3: very high" newline bitfld.long 0x48 15. "PINCOS,peripheral increment offset size" "0: The offset size for the peripheral address..,1: The offset size for the peripheral address.." bitfld.long 0x48 13.--14. "MSIZE,memory data size" "0: byte (8-bit),1: half-word (16-bit),2: word (32-bit),?" newline bitfld.long 0x48 11.--12. "PSIZE,peripheral data size" "0: byte (8-bit),1: half-word (16-bit),2: word (32-bit),?" bitfld.long 0x48 10. "MINC,memory increment mode" "0: memory address pointer is fixed,1: memory address pointer is incremented after each.." newline bitfld.long 0x48 9. "PINC,peripheral increment mode" "0: peripheral address pointer fixed,1: peripheral address pointer incremented after.." bitfld.long 0x48 8. "CIRC,circular mode" "0: circular mode disabled,1: circular mode enabled" newline bitfld.long 0x48 6.--7. "DIR,data transfer direction" "0: peripheral-to-memory,1: memory-to-peripheral,2: memory-to-memory,?" bitfld.long 0x48 5. "PFCTRL,peripheral flow controller" "0: DMA is the flow controller.,1: The peripheral is the flow controller." newline bitfld.long 0x48 4. "TCIE,transfer complete interrupt enable" "0: TC interrupt disabled,1: TC interrupt enabled" bitfld.long 0x48 3. "HTIE,half transfer interrupt enable" "0: HT interrupt disabled,1: HT interrupt enabled" newline bitfld.long 0x48 2. "TEIE,transfer error interrupt enable" "0: TE interrupt disabled,1: TE interrupt enabled" bitfld.long 0x48 1. "DMEIE,direct mode error interrupt enable" "0: DME interrupt disabled,1: DME interrupt enabled" newline bitfld.long 0x48 0. "EN,stream enable / flag stream ready when read low" "0: stream disabled,1: stream enabled" line.long 0x4C "DMA_S3NDTR,DMA stream 3 number of data register" hexmask.long.word 0x4C 0.--15. 1. "NDT,number of data items to transfer (0 up to 65535)" line.long 0x50 "DMA_S3PAR,DMA stream 3 peripheral address register" hexmask.long 0x50 0.--31. 1. "PAR,peripheral address" line.long 0x54 "DMA_S3M0AR,DMA stream 3 memory 0 address register" hexmask.long 0x54 0.--31. 1. "M0A,memory 0 address" line.long 0x58 "DMA_S3M1AR,DMA stream 3 memory 1 address register" hexmask.long 0x58 0.--31. 1. "M1A,memory 1 address (used in case of double-buffer mode)" line.long 0x5C "DMA_S3FCR,DMA stream 3 FIFO control register" bitfld.long 0x5C 7. "FEIE,FIFO error interrupt enable" "0: FE interrupt disabled,1: FE interrupt enabled" rbitfld.long 0x5C 3.--5. "FS,FIFO status" "0: 0 < fifo_level < 1/4,1: 1/4 ≤ fifo_level < 1/2,2: 1/2 ≤ fifo_level < 3/4,3: 3/4 ≤ fifo_level < full,4: FIFO is empty,5: FIFO is full,?,?" newline bitfld.long 0x5C 2. "DMDIS,direct mode disable" "0: direct mode enabled,1: direct mode disabled" bitfld.long 0x5C 0.--1. "FTH,FIFO threshold selection" "0: 1/4 full FIFO,1: 1/2 full FIFO,2: 3/4 full FIFO,3: full FIFO" line.long 0x60 "DMA_S4CR,DMA stream 4 configuration register" bitfld.long 0x60 23.--24. "MBURST,memory burst transfer configuration" "0: single transfer,1: INCR4 (incremental burst of 4 beats),2: INCR8 (incremental burst of 8 beats),3: INCR16 (incremental burst of 16 beats)" bitfld.long 0x60 21.--22. "PBURST,peripheral burst transfer configuration" "0: single transfer,1: INCR4 (incremental burst of 4 beats),2: INCR8 (incremental burst of 8 beats),3: INCR16 (incremental burst of 16 beats)" newline bitfld.long 0x60 20. "TRBUFF,Enable the DMA to handle bufferable transfers." "0: bufferable transfers not enabled,1: bufferable transfers enabled" bitfld.long 0x60 19. "CT,current target (only in double-buffer mode)" "0: current target memory is Memory 0 (addressed by..,1: current target memory is Memory 1 (addressed by.." newline bitfld.long 0x60 18. "DBM,double-buffer mode" "0: no buffer switching at the end of transfer,1: memory target switched at the end of the DMA.." bitfld.long 0x60 16.--17. "PL,priority level" "0: low,1: medium,2: high,3: very high" newline bitfld.long 0x60 15. "PINCOS,peripheral increment offset size" "0: The offset size for the peripheral address..,1: The offset size for the peripheral address.." bitfld.long 0x60 13.--14. "MSIZE,memory data size" "0: byte (8-bit),1: half-word (16-bit),2: word (32-bit),?" newline bitfld.long 0x60 11.--12. "PSIZE,peripheral data size" "0: byte (8-bit),1: half-word (16-bit),2: word (32-bit),?" bitfld.long 0x60 10. "MINC,memory increment mode" "0: memory address pointer is fixed,1: memory address pointer is incremented after each.." newline bitfld.long 0x60 9. "PINC,peripheral increment mode" "0: peripheral address pointer fixed,1: peripheral address pointer incremented after.." bitfld.long 0x60 8. "CIRC,circular mode" "0: circular mode disabled,1: circular mode enabled" newline bitfld.long 0x60 6.--7. "DIR,data transfer direction" "0: peripheral-to-memory,1: memory-to-peripheral,2: memory-to-memory,?" bitfld.long 0x60 5. "PFCTRL,peripheral flow controller" "0: DMA is the flow controller.,1: The peripheral is the flow controller." newline bitfld.long 0x60 4. "TCIE,transfer complete interrupt enable" "0: TC interrupt disabled,1: TC interrupt enabled" bitfld.long 0x60 3. "HTIE,half transfer interrupt enable" "0: HT interrupt disabled,1: HT interrupt enabled" newline bitfld.long 0x60 2. "TEIE,transfer error interrupt enable" "0: TE interrupt disabled,1: TE interrupt enabled" bitfld.long 0x60 1. "DMEIE,direct mode error interrupt enable" "0: DME interrupt disabled,1: DME interrupt enabled" newline bitfld.long 0x60 0. "EN,stream enable / flag stream ready when read low" "0: stream disabled,1: stream enabled" line.long 0x64 "DMA_S4NDTR,DMA stream 4 number of data register" hexmask.long.word 0x64 0.--15. 1. "NDT,number of data items to transfer (0 up to 65535)" line.long 0x68 "DMA_S4PAR,DMA stream 4 peripheral address register" hexmask.long 0x68 0.--31. 1. "PAR,peripheral address" line.long 0x6C "DMA_S4M0AR,DMA stream 4 memory 0 address register" hexmask.long 0x6C 0.--31. 1. "M0A,memory 0 address" line.long 0x70 "DMA_S4M1AR,DMA stream 4 memory 1 address register" hexmask.long 0x70 0.--31. 1. "M1A,memory 1 address (used in case of double-buffer mode)" line.long 0x74 "DMA_S4FCR,DMA stream 4 FIFO control register" bitfld.long 0x74 7. "FEIE,FIFO error interrupt enable" "0: FE interrupt disabled,1: FE interrupt enabled" rbitfld.long 0x74 3.--5. "FS,FIFO status" "0: 0 < fifo_level < 1/4,1: 1/4 ≤ fifo_level < 1/2,2: 1/2 ≤ fifo_level < 3/4,3: 3/4 ≤ fifo_level < full,4: FIFO is empty,5: FIFO is full,?,?" newline bitfld.long 0x74 2. "DMDIS,direct mode disable" "0: direct mode enabled,1: direct mode disabled" bitfld.long 0x74 0.--1. "FTH,FIFO threshold selection" "0: 1/4 full FIFO,1: 1/2 full FIFO,2: 3/4 full FIFO,3: full FIFO" line.long 0x78 "DMA_S5CR,DMA stream 5 configuration register" bitfld.long 0x78 23.--24. "MBURST,memory burst transfer configuration" "0: single transfer,1: INCR4 (incremental burst of 4 beats),2: INCR8 (incremental burst of 8 beats),3: INCR16 (incremental burst of 16 beats)" bitfld.long 0x78 21.--22. "PBURST,peripheral burst transfer configuration" "0: single transfer,1: INCR4 (incremental burst of 4 beats),2: INCR8 (incremental burst of 8 beats),3: INCR16 (incremental burst of 16 beats)" newline bitfld.long 0x78 20. "TRBUFF,Enable the DMA to handle bufferable transfers." "0: bufferable transfers not enabled,1: bufferable transfers enabled" bitfld.long 0x78 19. "CT,current target (only in double-buffer mode)" "0: current target memory is Memory 0 (addressed by..,1: current target memory is Memory 1 (addressed by.." newline bitfld.long 0x78 18. "DBM,double-buffer mode" "0: no buffer switching at the end of transfer,1: memory target switched at the end of the DMA.." bitfld.long 0x78 16.--17. "PL,priority level" "0: low,1: medium,2: high,3: very high" newline bitfld.long 0x78 15. "PINCOS,peripheral increment offset size" "0: The offset size for the peripheral address..,1: The offset size for the peripheral address.." bitfld.long 0x78 13.--14. "MSIZE,memory data size" "0: byte (8-bit),1: half-word (16-bit),2: word (32-bit),?" newline bitfld.long 0x78 11.--12. "PSIZE,peripheral data size" "0: byte (8-bit),1: half-word (16-bit),2: word (32-bit),?" bitfld.long 0x78 10. "MINC,memory increment mode" "0: memory address pointer is fixed,1: memory address pointer is incremented after each.." newline bitfld.long 0x78 9. "PINC,peripheral increment mode" "0: peripheral address pointer fixed,1: peripheral address pointer incremented after.." bitfld.long 0x78 8. "CIRC,circular mode" "0: circular mode disabled,1: circular mode enabled" newline bitfld.long 0x78 6.--7. "DIR,data transfer direction" "0: peripheral-to-memory,1: memory-to-peripheral,2: memory-to-memory,?" bitfld.long 0x78 5. "PFCTRL,peripheral flow controller" "0: DMA is the flow controller.,1: The peripheral is the flow controller." newline bitfld.long 0x78 4. "TCIE,transfer complete interrupt enable" "0: TC interrupt disabled,1: TC interrupt enabled" bitfld.long 0x78 3. "HTIE,half transfer interrupt enable" "0: HT interrupt disabled,1: HT interrupt enabled" newline bitfld.long 0x78 2. "TEIE,transfer error interrupt enable" "0: TE interrupt disabled,1: TE interrupt enabled" bitfld.long 0x78 1. "DMEIE,direct mode error interrupt enable" "0: DME interrupt disabled,1: DME interrupt enabled" newline bitfld.long 0x78 0. "EN,stream enable / flag stream ready when read low" "0: stream disabled,1: stream enabled" line.long 0x7C "DMA_S5NDTR,DMA stream 5 number of data register" hexmask.long.word 0x7C 0.--15. 1. "NDT,number of data items to transfer (0 up to 65535)" line.long 0x80 "DMA_S5PAR,DMA stream 5 peripheral address register" hexmask.long 0x80 0.--31. 1. "PAR,peripheral address" line.long 0x84 "DMA_S5M0AR,DMA stream 5 memory 0 address register" hexmask.long 0x84 0.--31. 1. "M0A,memory 0 address" line.long 0x88 "DMA_S5M1AR,DMA stream 5 memory 1 address register" hexmask.long 0x88 0.--31. 1. "M1A,memory 1 address (used in case of double-buffer mode)" line.long 0x8C "DMA_S5FCR,DMA stream 5 FIFO control register" bitfld.long 0x8C 7. "FEIE,FIFO error interrupt enable" "0: FE interrupt disabled,1: FE interrupt enabled" rbitfld.long 0x8C 3.--5. "FS,FIFO status" "0: 0 < fifo_level < 1/4,1: 1/4 ≤ fifo_level < 1/2,2: 1/2 ≤ fifo_level < 3/4,3: 3/4 ≤ fifo_level < full,4: FIFO is empty,5: FIFO is full,?,?" newline bitfld.long 0x8C 2. "DMDIS,direct mode disable" "0: direct mode enabled,1: direct mode disabled" bitfld.long 0x8C 0.--1. "FTH,FIFO threshold selection" "0: 1/4 full FIFO,1: 1/2 full FIFO,2: 3/4 full FIFO,3: full FIFO" line.long 0x90 "DMA_S6CR,DMA stream 6 configuration register" bitfld.long 0x90 23.--24. "MBURST,memory burst transfer configuration" "0: single transfer,1: INCR4 (incremental burst of 4 beats),2: INCR8 (incremental burst of 8 beats),3: INCR16 (incremental burst of 16 beats)" bitfld.long 0x90 21.--22. "PBURST,peripheral burst transfer configuration" "0: single transfer,1: INCR4 (incremental burst of 4 beats),2: INCR8 (incremental burst of 8 beats),3: INCR16 (incremental burst of 16 beats)" newline bitfld.long 0x90 20. "TRBUFF,Enable the DMA to handle bufferable transfers." "0: bufferable transfers not enabled,1: bufferable transfers enabled" bitfld.long 0x90 19. "CT,current target (only in double-buffer mode)" "0: current target memory is Memory 0 (addressed by..,1: current target memory is Memory 1 (addressed by.." newline bitfld.long 0x90 18. "DBM,double-buffer mode" "0: no buffer switching at the end of transfer,1: memory target switched at the end of the DMA.." bitfld.long 0x90 16.--17. "PL,priority level" "0: low,1: medium,2: high,3: very high" newline bitfld.long 0x90 15. "PINCOS,peripheral increment offset size" "0: The offset size for the peripheral address..,1: The offset size for the peripheral address.." bitfld.long 0x90 13.--14. "MSIZE,memory data size" "0: byte (8-bit),1: half-word (16-bit),2: word (32-bit),?" newline bitfld.long 0x90 11.--12. "PSIZE,peripheral data size" "0: byte (8-bit),1: half-word (16-bit),2: word (32-bit),?" bitfld.long 0x90 10. "MINC,memory increment mode" "0: memory address pointer is fixed,1: memory address pointer is incremented after each.." newline bitfld.long 0x90 9. "PINC,peripheral increment mode" "0: peripheral address pointer fixed,1: peripheral address pointer incremented after.." bitfld.long 0x90 8. "CIRC,circular mode" "0: circular mode disabled,1: circular mode enabled" newline bitfld.long 0x90 6.--7. "DIR,data transfer direction" "0: peripheral-to-memory,1: memory-to-peripheral,2: memory-to-memory,?" bitfld.long 0x90 5. "PFCTRL,peripheral flow controller" "0: DMA is the flow controller.,1: The peripheral is the flow controller." newline bitfld.long 0x90 4. "TCIE,transfer complete interrupt enable" "0: TC interrupt disabled,1: TC interrupt enabled" bitfld.long 0x90 3. "HTIE,half transfer interrupt enable" "0: HT interrupt disabled,1: HT interrupt enabled" newline bitfld.long 0x90 2. "TEIE,transfer error interrupt enable" "0: TE interrupt disabled,1: TE interrupt enabled" bitfld.long 0x90 1. "DMEIE,direct mode error interrupt enable" "0: DME interrupt disabled,1: DME interrupt enabled" newline bitfld.long 0x90 0. "EN,stream enable / flag stream ready when read low" "0: stream disabled,1: stream enabled" line.long 0x94 "DMA_S6NDTR,DMA stream 6 number of data register" hexmask.long.word 0x94 0.--15. 1. "NDT,number of data items to transfer (0 up to 65535)" line.long 0x98 "DMA_S6PAR,DMA stream 6 peripheral address register" hexmask.long 0x98 0.--31. 1. "PAR,peripheral address" line.long 0x9C "DMA_S6M0AR,DMA stream 6 memory 0 address register" hexmask.long 0x9C 0.--31. 1. "M0A,memory 0 address" line.long 0xA0 "DMA_S6M1AR,DMA stream 6 memory 1 address register" hexmask.long 0xA0 0.--31. 1. "M1A,memory 1 address (used in case of double-buffer mode)" line.long 0xA4 "DMA_S6FCR,DMA stream 6 FIFO control register" bitfld.long 0xA4 7. "FEIE,FIFO error interrupt enable" "0: FE interrupt disabled,1: FE interrupt enabled" rbitfld.long 0xA4 3.--5. "FS,FIFO status" "0: 0 < fifo_level < 1/4,1: 1/4 ≤ fifo_level < 1/2,2: 1/2 ≤ fifo_level < 3/4,3: 3/4 ≤ fifo_level < full,4: FIFO is empty,5: FIFO is full,?,?" newline bitfld.long 0xA4 2. "DMDIS,direct mode disable" "0: direct mode enabled,1: direct mode disabled" bitfld.long 0xA4 0.--1. "FTH,FIFO threshold selection" "0: 1/4 full FIFO,1: 1/2 full FIFO,2: 3/4 full FIFO,3: full FIFO" line.long 0xA8 "DMA_S7CR,DMA stream 7 configuration register" bitfld.long 0xA8 23.--24. "MBURST,memory burst transfer configuration" "0: single transfer,1: INCR4 (incremental burst of 4 beats),2: INCR8 (incremental burst of 8 beats),3: INCR16 (incremental burst of 16 beats)" bitfld.long 0xA8 21.--22. "PBURST,peripheral burst transfer configuration" "0: single transfer,1: INCR4 (incremental burst of 4 beats),2: INCR8 (incremental burst of 8 beats),3: INCR16 (incremental burst of 16 beats)" newline bitfld.long 0xA8 20. "TRBUFF,Enable the DMA to handle bufferable transfers." "0: bufferable transfers not enabled,1: bufferable transfers enabled" bitfld.long 0xA8 19. "CT,current target (only in double-buffer mode)" "0: current target memory is Memory 0 (addressed by..,1: current target memory is Memory 1 (addressed by.." newline bitfld.long 0xA8 18. "DBM,double-buffer mode" "0: no buffer switching at the end of transfer,1: memory target switched at the end of the DMA.." bitfld.long 0xA8 16.--17. "PL,priority level" "0: low,1: medium,2: high,3: very high" newline bitfld.long 0xA8 15. "PINCOS,peripheral increment offset size" "0: The offset size for the peripheral address..,1: The offset size for the peripheral address.." bitfld.long 0xA8 13.--14. "MSIZE,memory data size" "0: byte (8-bit),1: half-word (16-bit),2: word (32-bit),?" newline bitfld.long 0xA8 11.--12. "PSIZE,peripheral data size" "0: byte (8-bit),1: half-word (16-bit),2: word (32-bit),?" bitfld.long 0xA8 10. "MINC,memory increment mode" "0: memory address pointer is fixed,1: memory address pointer is incremented after each.." newline bitfld.long 0xA8 9. "PINC,peripheral increment mode" "0: peripheral address pointer fixed,1: peripheral address pointer incremented after.." bitfld.long 0xA8 8. "CIRC,circular mode" "0: circular mode disabled,1: circular mode enabled" newline bitfld.long 0xA8 6.--7. "DIR,data transfer direction" "0: peripheral-to-memory,1: memory-to-peripheral,2: memory-to-memory,?" bitfld.long 0xA8 5. "PFCTRL,peripheral flow controller" "0: DMA is the flow controller.,1: The peripheral is the flow controller." newline bitfld.long 0xA8 4. "TCIE,transfer complete interrupt enable" "0: TC interrupt disabled,1: TC interrupt enabled" bitfld.long 0xA8 3. "HTIE,half transfer interrupt enable" "0: HT interrupt disabled,1: HT interrupt enabled" newline bitfld.long 0xA8 2. "TEIE,transfer error interrupt enable" "0: TE interrupt disabled,1: TE interrupt enabled" bitfld.long 0xA8 1. "DMEIE,direct mode error interrupt enable" "0: DME interrupt disabled,1: DME interrupt enabled" newline bitfld.long 0xA8 0. "EN,stream enable / flag stream ready when read low" "0: stream disabled,1: stream enabled" line.long 0xAC "DMA_S7NDTR,DMA stream 7 number of data register" hexmask.long.word 0xAC 0.--15. 1. "NDT,number of data items to transfer (0 up to 65535)" line.long 0xB0 "DMA_S7PAR,DMA stream 7 peripheral address register" hexmask.long 0xB0 0.--31. 1. "PAR,peripheral address" line.long 0xB4 "DMA_S7M0AR,DMA stream 7 memory 0 address register" hexmask.long 0xB4 0.--31. 1. "M0A,memory 0 address" line.long 0xB8 "DMA_S7M1AR,DMA stream 7 memory 1 address register" hexmask.long 0xB8 0.--31. 1. "M1A,memory 1 address (used in case of double-buffer mode)" line.long 0xBC "DMA_S7FCR,DMA stream 7 FIFO control register" bitfld.long 0xBC 7. "FEIE,FIFO error interrupt enable" "0: FE interrupt disabled,1: FE interrupt enabled" rbitfld.long 0xBC 3.--5. "FS,FIFO status" "0: 0 < fifo_level < 1/4,1: 1/4 ≤ fifo_level < 1/2,2: 1/2 ≤ fifo_level < 3/4,3: 3/4 ≤ fifo_level < full,4: FIFO is empty,5: FIFO is full,?,?" newline bitfld.long 0xBC 2. "DMDIS,direct mode disable" "0: direct mode enabled,1: direct mode disabled" bitfld.long 0xBC 0.--1. "FTH,FIFO threshold selection" "0: 1/4 full FIFO,1: 1/2 full FIFO,2: 3/4 full FIFO,3: full FIFO" rgroup.long 0x3EC++0x13 line.long 0x0 "DMA_HWCFGR2,DMA hardware configuration 2 register" bitfld.long 0x0 8.--10. "CHSEL_WIDTH,bit width of the CHSEL field of any DMA_SxCR register common to all streams" "0: no programmable selection,1: 2 channels programmable selection,2: up to 8 channels programmable selection,3: up to 16 channels programmable selection,4: up to 32 channels programmable selection,5: up to 64 channels programmable selection,6: up to 128 channels programmable selection,?" bitfld.long 0x0 4. "WRITE_BUFFERABLE,In any case DMA acknowledge signal is asserted one cycle after the address phase of the bus access on its AHB peripheral master port." "0: DMA acknowledge signal is de-asserted one cycle..,1: DMA acknowledge signal is de-asserted exactly.." newline bitfld.long 0x0 0.--1. "FIFO_SIZE,FIFO size common to all streams" "0: 2-word FIFO,1: 4-word FIFO,2: 8-word FIFO,3: 16-word FIFO" line.long 0x4 "DMA_HWCFGR1,DMA hardware configuration 1 register" bitfld.long 0x4 28.--29. "DMA_DEF7,type of the stream 7" "0: none,1: regular,2: double-buffer,3: Reserved" bitfld.long 0x4 24.--25. "DMA_DEF6,type of the stream 6" "0: none,1: regular,2: double-buffer,3: Reserved" newline bitfld.long 0x4 20.--21. "DMA_DEF5,type of the stream 5" "0: none,1: regular,2: double-buffer,3: Reserved" bitfld.long 0x4 16.--17. "DMA_DEF4,type of the stream 4" "0: none,1: regular,2: double-buffer,3: Reserved" newline bitfld.long 0x4 12.--13. "DMA_DEF3,type of the stream 3" "0: none,1: regular,2: double-buffer,3: Reserved" bitfld.long 0x4 8.--9. "DMA_DEF2,type of the stream 2" "0: none,1: regular,2: double-buffer,3: Reserved" newline bitfld.long 0x4 4.--5. "DMA_DEF1,type of the stream 1" "0: none,1: regular,2: double-buffer,3: Reserved" bitfld.long 0x4 0.--1. "DMA_DEF0,type of the stream 0" "0: none,1: regular,2: double-buffer,3: Reserved" line.long 0x8 "DMA_VERR,DMA version register" hexmask.long.byte 0x8 4.--7. 1. "MAJREV,major IP revision" hexmask.long.byte 0x8 0.--3. 1. "MINREV,minor IP revision" line.long 0xC "DMA_IPDR,DMA identification register" hexmask.long 0xC 0.--31. 1. "ID,size identification" line.long 0x10 "DMA_SIDR,DMA size identification register" hexmask.long 0x10 0.--31. 1. "SID,size identification" tree.end endif sif (cpuis("STM32MP13*")) tree "DMA3" base ad:0x48005000 rgroup.long 0x0++0x7 line.long 0x0 "DMA_LISR,DMA low interrupt status register" bitfld.long 0x0 27. "TCIF3,stream x transfer complete interrupt flag (x = 3 to 0)" "0: no transfer complete event on stream x,1: a transfer complete event occurred on stream x" bitfld.long 0x0 26. "HTIF3,stream x half transfer interrupt flag (x = 3 to 0)" "0: no half transfer event on stream x,1: a half transfer event occurred on stream x" newline bitfld.long 0x0 25. "TEIF3,stream x transfer error interrupt flag (x = 3 to 0)" "0: no transfer error on stream x,1: a transfer error occurred on stream x" bitfld.long 0x0 24. "DMEIF3,stream x direct mode error interrupt flag (x = 3 to 0)" "0: No direct mode error on stream x,1: a direct mode error occurred on stream x" newline bitfld.long 0x0 22. "FEIF3,stream x FIFO error interrupt flag (x = 3 to 0)" "0: no FIFO error event on stream x,1: a FIFO error event occurred on stream x" bitfld.long 0x0 21. "TCIF2,stream x transfer complete interrupt flag (x = 3 to 0)" "0: no transfer complete event on stream x,1: a transfer complete event occurred on stream x" newline bitfld.long 0x0 20. "HTIF2,stream x half transfer interrupt flag (x = 3 to 0)" "0: no half transfer event on stream x,1: a half transfer event occurred on stream x" bitfld.long 0x0 19. "TEIF2,stream x transfer error interrupt flag (x = 3 to 0)" "0: no transfer error on stream x,1: a transfer error occurred on stream x" newline bitfld.long 0x0 18. "DMEIF2,stream x direct mode error interrupt flag (x = 3 to 0)" "0: No direct mode error on stream x,1: a direct mode error occurred on stream x" bitfld.long 0x0 16. "FEIF2,stream x FIFO error interrupt flag (x = 3 to 0)" "0: no FIFO error event on stream x,1: a FIFO error event occurred on stream x" newline bitfld.long 0x0 11. "TCIF1,stream x transfer complete interrupt flag (x = 3 to 0)" "0: no transfer complete event on stream x,1: a transfer complete event occurred on stream x" bitfld.long 0x0 10. "HTIF1,stream x half transfer interrupt flag (x = 3 to 0)" "0: no half transfer event on stream x,1: a half transfer event occurred on stream x" newline bitfld.long 0x0 9. "TEIF1,stream x transfer error interrupt flag (x = 3 to 0)" "0: no transfer error on stream x,1: a transfer error occurred on stream x" bitfld.long 0x0 8. "DMEIF1,stream x direct mode error interrupt flag (x = 3 to 0)" "0: No direct mode error on stream x,1: a direct mode error occurred on stream x" newline bitfld.long 0x0 6. "FEIF1,stream x FIFO error interrupt flag (x = 3 to 0)" "0: no FIFO error event on stream x,1: a FIFO error event occurred on stream x" bitfld.long 0x0 5. "TCIF0,stream x transfer complete interrupt flag (x = 3 to 0)" "0: no transfer complete event on stream x,1: a transfer complete event occurred on stream x" newline bitfld.long 0x0 4. "HTIF0,stream x half transfer interrupt flag (x = 3 to 0)" "0: no half transfer event on stream x,1: a half transfer event occurred on stream x" bitfld.long 0x0 3. "TEIF0,stream x transfer error interrupt flag (x = 3 to 0)" "0: no transfer error on stream x,1: a transfer error occurred on stream x" newline bitfld.long 0x0 2. "DMEIF0,stream x direct mode error interrupt flag (x = 3 to 0)" "0: No direct mode error on stream x,1: a direct mode error occurred on stream x" bitfld.long 0x0 0. "FEIF0,stream x FIFO error interrupt flag (x = 3 to 0)" "0: no FIFO error event on stream x,1: a FIFO error event occurred on stream x" line.long 0x4 "DMA_HISR,DMA high interrupt status register" bitfld.long 0x4 27. "TCIF7,stream x transfer complete interrupt flag (x = 7 to 4)" "0: no transfer complete event on stream x,1: a transfer complete event occurred on stream x" bitfld.long 0x4 26. "HTIF7,stream x half transfer interrupt flag (x = 7 to 4)" "0: no half transfer event on stream x,1: a half transfer event occurred on stream x" newline bitfld.long 0x4 25. "TEIF7,stream x transfer error interrupt flag (x = 7 to 4)" "0: no transfer error on stream x,1: a transfer error occurred on stream x" bitfld.long 0x4 24. "DMEIF7,stream x direct mode error interrupt flag (x = 7 to 4)" "0: no direct mode error on stream x,1: a direct mode error occurred on stream x" newline bitfld.long 0x4 22. "FEIF7,stream x FIFO error interrupt flag (x = 7 to 4)" "0: no FIFO error event on stream x,1: a FIFO error event occurred on stream x" bitfld.long 0x4 21. "TCIF6,stream x transfer complete interrupt flag (x = 7 to 4)" "0: no transfer complete event on stream x,1: a transfer complete event occurred on stream x" newline bitfld.long 0x4 20. "HTIF6,stream x half transfer interrupt flag (x = 7 to 4)" "0: no half transfer event on stream x,1: a half transfer event occurred on stream x" bitfld.long 0x4 19. "TEIF6,stream x transfer error interrupt flag (x = 7 to 4)" "0: no transfer error on stream x,1: a transfer error occurred on stream x" newline bitfld.long 0x4 18. "DMEIF6,stream x direct mode error interrupt flag (x = 7 to 4)" "0: no direct mode error on stream x,1: a direct mode error occurred on stream x" bitfld.long 0x4 16. "FEIF6,stream x FIFO error interrupt flag (x = 7 to 4)" "0: no FIFO error event on stream x,1: a FIFO error event occurred on stream x" newline bitfld.long 0x4 11. "TCIF5,stream x transfer complete interrupt flag (x = 7 to 4)" "0: no transfer complete event on stream x,1: a transfer complete event occurred on stream x" bitfld.long 0x4 10. "HTIF5,stream x half transfer interrupt flag (x = 7 to 4)" "0: no half transfer event on stream x,1: a half transfer event occurred on stream x" newline bitfld.long 0x4 9. "TEIF5,stream x transfer error interrupt flag (x = 7 to 4)" "0: no transfer error on stream x,1: a transfer error occurred on stream x" bitfld.long 0x4 8. "DMEIF5,stream x direct mode error interrupt flag (x = 7 to 4)" "0: no direct mode error on stream x,1: a direct mode error occurred on stream x" newline bitfld.long 0x4 6. "FEIF5,stream x FIFO error interrupt flag (x = 7 to 4)" "0: no FIFO error event on stream x,1: a FIFO error event occurred on stream x" bitfld.long 0x4 5. "TCIF4,stream x transfer complete interrupt flag (x = 7 to 4)" "0: no transfer complete event on stream x,1: a transfer complete event occurred on stream x" newline bitfld.long 0x4 4. "HTIF4,stream x half transfer interrupt flag (x = 7 to 4)" "0: no half transfer event on stream x,1: a half transfer event occurred on stream x" bitfld.long 0x4 3. "TEIF4,stream x transfer error interrupt flag (x = 7 to 4)" "0: no transfer error on stream x,1: a transfer error occurred on stream x" newline bitfld.long 0x4 2. "DMEIF4,stream x direct mode error interrupt flag (x = 7 to 4)" "0: no direct mode error on stream x,1: a direct mode error occurred on stream x" bitfld.long 0x4 0. "FEIF4,stream x FIFO error interrupt flag (x = 7 to 4)" "0: no FIFO error event on stream x,1: a FIFO error event occurred on stream x" wgroup.long 0x8++0x7 line.long 0x0 "DMA_LIFCR,DMA low interrupt flag clear register" bitfld.long 0x0 27. "CTCIF3,stream x clear transfer complete interrupt flag (x = 3 to 0)" "0,1" bitfld.long 0x0 26. "CHTIF3,stream x clear half transfer interrupt flag (x = 3 to 0)" "0,1" newline bitfld.long 0x0 25. "CTEIF3,Stream x clear transfer error interrupt flag (x = 3 to 0)" "0,1" bitfld.long 0x0 24. "CDMEIF3,stream x clear direct mode error interrupt flag (x = 3 to 0)" "0,1" newline bitfld.long 0x0 22. "CFEIF3,stream x clear FIFO error interrupt flag (x = 3 to 0)" "0,1" bitfld.long 0x0 21. "CTCIF2,stream x clear transfer complete interrupt flag (x = 3 to 0)" "0,1" newline bitfld.long 0x0 20. "CHTIF2,stream x clear half transfer interrupt flag (x = 3 to 0)" "0,1" bitfld.long 0x0 19. "CTEIF2,Stream x clear transfer error interrupt flag (x = 3 to 0)" "0,1" newline bitfld.long 0x0 18. "CDMEIF2,stream x clear direct mode error interrupt flag (x = 3 to 0)" "0,1" bitfld.long 0x0 16. "CFEIF2,stream x clear FIFO error interrupt flag (x = 3 to 0)" "0,1" newline bitfld.long 0x0 11. "CTCIF1,stream x clear transfer complete interrupt flag (x = 3 to 0)" "0,1" bitfld.long 0x0 10. "CHTIF1,stream x clear half transfer interrupt flag (x = 3 to 0)" "0,1" newline bitfld.long 0x0 9. "CTEIF1,Stream x clear transfer error interrupt flag (x = 3 to 0)" "0,1" bitfld.long 0x0 8. "CDMEIF1,stream x clear direct mode error interrupt flag (x = 3 to 0)" "0,1" newline bitfld.long 0x0 6. "CFEIF1,stream x clear FIFO error interrupt flag (x = 3 to 0)" "0,1" bitfld.long 0x0 5. "CTCIF0,stream x clear transfer complete interrupt flag (x = 3 to 0)" "0,1" newline bitfld.long 0x0 4. "CHTIF0,stream x clear half transfer interrupt flag (x = 3 to 0)" "0,1" bitfld.long 0x0 3. "CTEIF0,Stream x clear transfer error interrupt flag (x = 3 to 0)" "0,1" newline bitfld.long 0x0 2. "CDMEIF0,stream x clear direct mode error interrupt flag (x = 3 to 0)" "0,1" bitfld.long 0x0 0. "CFEIF0,stream x clear FIFO error interrupt flag (x = 3 to 0)" "0,1" line.long 0x4 "DMA_HIFCR,DMA high interrupt flag clear register" bitfld.long 0x4 27. "CTCIF7,stream x clear transfer complete interrupt flag (x = 7 to 4)" "0,1" bitfld.long 0x4 26. "CHTIF7,stream x clear half transfer interrupt flag (x = 7 to 4)" "0,1" newline bitfld.long 0x4 25. "CTEIF7,stream x clear transfer error interrupt flag (x = 7 to 4)" "0,1" bitfld.long 0x4 24. "CDMEIF7,stream x clear direct mode error interrupt flag (x = 7 to 4)" "0,1" newline bitfld.long 0x4 22. "CFEIF7,stream x clear FIFO error interrupt flag (x = 7 to 4)" "0,1" bitfld.long 0x4 21. "CTCIF6,stream x clear transfer complete interrupt flag (x = 7 to 4)" "0,1" newline bitfld.long 0x4 20. "CHTIF6,stream x clear half transfer interrupt flag (x = 7 to 4)" "0,1" bitfld.long 0x4 19. "CTEIF6,stream x clear transfer error interrupt flag (x = 7 to 4)" "0,1" newline bitfld.long 0x4 18. "CDMEIF6,stream x clear direct mode error interrupt flag (x = 7 to 4)" "0,1" bitfld.long 0x4 16. "CFEIF6,stream x clear FIFO error interrupt flag (x = 7 to 4)" "0,1" newline bitfld.long 0x4 11. "CTCIF5,stream x clear transfer complete interrupt flag (x = 7 to 4)" "0,1" bitfld.long 0x4 10. "CHTIF5,stream x clear half transfer interrupt flag (x = 7 to 4)" "0,1" newline bitfld.long 0x4 9. "CTEIF5,stream x clear transfer error interrupt flag (x = 7 to 4)" "0,1" bitfld.long 0x4 8. "CDMEIF5,stream x clear direct mode error interrupt flag (x = 7 to 4)" "0,1" newline bitfld.long 0x4 6. "CFEIF5,stream x clear FIFO error interrupt flag (x = 7 to 4)" "0,1" bitfld.long 0x4 5. "CTCIF4,stream x clear transfer complete interrupt flag (x = 7 to 4)" "0,1" newline bitfld.long 0x4 4. "CHTIF4,stream x clear half transfer interrupt flag (x = 7 to 4)" "0,1" bitfld.long 0x4 3. "CTEIF4,stream x clear transfer error interrupt flag (x = 7 to 4)" "0,1" newline bitfld.long 0x4 2. "CDMEIF4,stream x clear direct mode error interrupt flag (x = 7 to 4)" "0,1" bitfld.long 0x4 0. "CFEIF4,stream x clear FIFO error interrupt flag (x = 7 to 4)" "0,1" group.long 0x10++0xBF line.long 0x0 "DMA_S0CR,DMA stream 0 configuration register" bitfld.long 0x0 23.--24. "MBURST,memory burst transfer configuration" "0: single transfer,1: INCR4 (incremental burst of 4 beats),2: INCR8 (incremental burst of 8 beats),3: INCR16 (incremental burst of 16 beats)" bitfld.long 0x0 21.--22. "PBURST,peripheral burst transfer configuration" "0: single transfer,1: INCR4 (incremental burst of 4 beats),2: INCR8 (incremental burst of 8 beats),3: INCR16 (incremental burst of 16 beats)" newline bitfld.long 0x0 20. "TRBUFF,Enable the DMA to handle bufferable transfers." "0: bufferable transfers not enabled,1: bufferable transfers enabled" bitfld.long 0x0 19. "CT,current target (only in double-buffer mode)" "0: current target memory is Memory 0 (addressed by..,1: current target memory is Memory 1 (addressed by.." newline bitfld.long 0x0 18. "DBM,double-buffer mode" "0: no buffer switching at the end of transfer,1: memory target switched at the end of the DMA.." bitfld.long 0x0 16.--17. "PL,priority level" "0: low,1: medium,2: high,3: very high" newline bitfld.long 0x0 15. "PINCOS,peripheral increment offset size" "0: The offset size for the peripheral address..,1: The offset size for the peripheral address.." bitfld.long 0x0 13.--14. "MSIZE,memory data size" "0: byte (8-bit),1: half-word (16-bit),2: word (32-bit),?" newline bitfld.long 0x0 11.--12. "PSIZE,peripheral data size" "0: byte (8-bit),1: half-word (16-bit),2: word (32-bit),?" bitfld.long 0x0 10. "MINC,memory increment mode" "0: memory address pointer is fixed,1: memory address pointer is incremented after each.." newline bitfld.long 0x0 9. "PINC,peripheral increment mode" "0: peripheral address pointer fixed,1: peripheral address pointer incremented after.." bitfld.long 0x0 8. "CIRC,circular mode" "0: circular mode disabled,1: circular mode enabled" newline bitfld.long 0x0 6.--7. "DIR,data transfer direction" "0: peripheral-to-memory,1: memory-to-peripheral,2: memory-to-memory,?" bitfld.long 0x0 5. "PFCTRL,peripheral flow controller" "0: DMA is the flow controller.,1: The peripheral is the flow controller." newline bitfld.long 0x0 4. "TCIE,transfer complete interrupt enable" "0: TC interrupt disabled,1: TC interrupt enabled" bitfld.long 0x0 3. "HTIE,half transfer interrupt enable" "0: HT interrupt disabled,1: HT interrupt enabled" newline bitfld.long 0x0 2. "TEIE,transfer error interrupt enable" "0: TE interrupt disabled,1: TE interrupt enabled" bitfld.long 0x0 1. "DMEIE,direct mode error interrupt enable" "0: DME interrupt disabled,1: DME interrupt enabled" newline bitfld.long 0x0 0. "EN,stream enable / flag stream ready when read low" "0: stream disabled,1: stream enabled" line.long 0x4 "DMA_S0NDTR,DMA stream 0 number of data register" hexmask.long.word 0x4 0.--15. 1. "NDT,number of data items to transfer (0 up to 65535)" line.long 0x8 "DMA_S0PAR,DMA stream 0 peripheral address register" hexmask.long 0x8 0.--31. 1. "PAR,peripheral address" line.long 0xC "DMA_S0M0AR,DMA stream 0 memory 0 address register" hexmask.long 0xC 0.--31. 1. "M0A,memory 0 address" line.long 0x10 "DMA_S0M1AR,DMA stream 0 memory 1 address register" hexmask.long 0x10 0.--31. 1. "M1A,memory 1 address (used in case of double-buffer mode)" line.long 0x14 "DMA_S0FCR,DMA stream 0 FIFO control register" bitfld.long 0x14 7. "FEIE,FIFO error interrupt enable" "0: FE interrupt disabled,1: FE interrupt enabled" rbitfld.long 0x14 3.--5. "FS,FIFO status" "0: 0 < fifo_level < 1/4,1: 1/4 ≤ fifo_level < 1/2,2: 1/2 ≤ fifo_level < 3/4,3: 3/4 ≤ fifo_level < full,4: FIFO is empty,5: FIFO is full,?,?" newline bitfld.long 0x14 2. "DMDIS,direct mode disable" "0: direct mode enabled,1: direct mode disabled" bitfld.long 0x14 0.--1. "FTH,FIFO threshold selection" "0: 1/4 full FIFO,1: 1/2 full FIFO,2: 3/4 full FIFO,3: full FIFO" line.long 0x18 "DMA_S1CR,DMA stream 1 configuration register" bitfld.long 0x18 23.--24. "MBURST,memory burst transfer configuration" "0: single transfer,1: INCR4 (incremental burst of 4 beats),2: INCR8 (incremental burst of 8 beats),3: INCR16 (incremental burst of 16 beats)" bitfld.long 0x18 21.--22. "PBURST,peripheral burst transfer configuration" "0: single transfer,1: INCR4 (incremental burst of 4 beats),2: INCR8 (incremental burst of 8 beats),3: INCR16 (incremental burst of 16 beats)" newline bitfld.long 0x18 20. "TRBUFF,Enable the DMA to handle bufferable transfers." "0: bufferable transfers not enabled,1: bufferable transfers enabled" bitfld.long 0x18 19. "CT,current target (only in double-buffer mode)" "0: current target memory is Memory 0 (addressed by..,1: current target memory is Memory 1 (addressed by.." newline bitfld.long 0x18 18. "DBM,double-buffer mode" "0: no buffer switching at the end of transfer,1: memory target switched at the end of the DMA.." bitfld.long 0x18 16.--17. "PL,priority level" "0: low,1: medium,2: high,3: very high" newline bitfld.long 0x18 15. "PINCOS,peripheral increment offset size" "0: The offset size for the peripheral address..,1: The offset size for the peripheral address.." bitfld.long 0x18 13.--14. "MSIZE,memory data size" "0: byte (8-bit),1: half-word (16-bit),2: word (32-bit),?" newline bitfld.long 0x18 11.--12. "PSIZE,peripheral data size" "0: byte (8-bit),1: half-word (16-bit),2: word (32-bit),?" bitfld.long 0x18 10. "MINC,memory increment mode" "0: memory address pointer is fixed,1: memory address pointer is incremented after each.." newline bitfld.long 0x18 9. "PINC,peripheral increment mode" "0: peripheral address pointer fixed,1: peripheral address pointer incremented after.." bitfld.long 0x18 8. "CIRC,circular mode" "0: circular mode disabled,1: circular mode enabled" newline bitfld.long 0x18 6.--7. "DIR,data transfer direction" "0: peripheral-to-memory,1: memory-to-peripheral,2: memory-to-memory,?" bitfld.long 0x18 5. "PFCTRL,peripheral flow controller" "0: DMA is the flow controller.,1: The peripheral is the flow controller." newline bitfld.long 0x18 4. "TCIE,transfer complete interrupt enable" "0: TC interrupt disabled,1: TC interrupt enabled" bitfld.long 0x18 3. "HTIE,half transfer interrupt enable" "0: HT interrupt disabled,1: HT interrupt enabled" newline bitfld.long 0x18 2. "TEIE,transfer error interrupt enable" "0: TE interrupt disabled,1: TE interrupt enabled" bitfld.long 0x18 1. "DMEIE,direct mode error interrupt enable" "0: DME interrupt disabled,1: DME interrupt enabled" newline bitfld.long 0x18 0. "EN,stream enable / flag stream ready when read low" "0: stream disabled,1: stream enabled" line.long 0x1C "DMA_S1NDTR,DMA stream 1 number of data register" hexmask.long.word 0x1C 0.--15. 1. "NDT,number of data items to transfer (0 up to 65535)" line.long 0x20 "DMA_S1PAR,DMA stream 1 peripheral address register" hexmask.long 0x20 0.--31. 1. "PAR,peripheral address" line.long 0x24 "DMA_S1M0AR,DMA stream 1 memory 0 address register" hexmask.long 0x24 0.--31. 1. "M0A,memory 0 address" line.long 0x28 "DMA_S1M1AR,DMA stream 1 memory 1 address register" hexmask.long 0x28 0.--31. 1. "M1A,memory 1 address (used in case of double-buffer mode)" line.long 0x2C "DMA_S1FCR,DMA stream 1 FIFO control register" bitfld.long 0x2C 7. "FEIE,FIFO error interrupt enable" "0: FE interrupt disabled,1: FE interrupt enabled" rbitfld.long 0x2C 3.--5. "FS,FIFO status" "0: 0 < fifo_level < 1/4,1: 1/4 ≤ fifo_level < 1/2,2: 1/2 ≤ fifo_level < 3/4,3: 3/4 ≤ fifo_level < full,4: FIFO is empty,5: FIFO is full,?,?" newline bitfld.long 0x2C 2. "DMDIS,direct mode disable" "0: direct mode enabled,1: direct mode disabled" bitfld.long 0x2C 0.--1. "FTH,FIFO threshold selection" "0: 1/4 full FIFO,1: 1/2 full FIFO,2: 3/4 full FIFO,3: full FIFO" line.long 0x30 "DMA_S2CR,DMA stream 2 configuration register" bitfld.long 0x30 23.--24. "MBURST,memory burst transfer configuration" "0: single transfer,1: INCR4 (incremental burst of 4 beats),2: INCR8 (incremental burst of 8 beats),3: INCR16 (incremental burst of 16 beats)" bitfld.long 0x30 21.--22. "PBURST,peripheral burst transfer configuration" "0: single transfer,1: INCR4 (incremental burst of 4 beats),2: INCR8 (incremental burst of 8 beats),3: INCR16 (incremental burst of 16 beats)" newline bitfld.long 0x30 20. "TRBUFF,Enable the DMA to handle bufferable transfers." "0: bufferable transfers not enabled,1: bufferable transfers enabled" bitfld.long 0x30 19. "CT,current target (only in double-buffer mode)" "0: current target memory is Memory 0 (addressed by..,1: current target memory is Memory 1 (addressed by.." newline bitfld.long 0x30 18. "DBM,double-buffer mode" "0: no buffer switching at the end of transfer,1: memory target switched at the end of the DMA.." bitfld.long 0x30 16.--17. "PL,priority level" "0: low,1: medium,2: high,3: very high" newline bitfld.long 0x30 15. "PINCOS,peripheral increment offset size" "0: The offset size for the peripheral address..,1: The offset size for the peripheral address.." bitfld.long 0x30 13.--14. "MSIZE,memory data size" "0: byte (8-bit),1: half-word (16-bit),2: word (32-bit),?" newline bitfld.long 0x30 11.--12. "PSIZE,peripheral data size" "0: byte (8-bit),1: half-word (16-bit),2: word (32-bit),?" bitfld.long 0x30 10. "MINC,memory increment mode" "0: memory address pointer is fixed,1: memory address pointer is incremented after each.." newline bitfld.long 0x30 9. "PINC,peripheral increment mode" "0: peripheral address pointer fixed,1: peripheral address pointer incremented after.." bitfld.long 0x30 8. "CIRC,circular mode" "0: circular mode disabled,1: circular mode enabled" newline bitfld.long 0x30 6.--7. "DIR,data transfer direction" "0: peripheral-to-memory,1: memory-to-peripheral,2: memory-to-memory,?" bitfld.long 0x30 5. "PFCTRL,peripheral flow controller" "0: DMA is the flow controller.,1: The peripheral is the flow controller." newline bitfld.long 0x30 4. "TCIE,transfer complete interrupt enable" "0: TC interrupt disabled,1: TC interrupt enabled" bitfld.long 0x30 3. "HTIE,half transfer interrupt enable" "0: HT interrupt disabled,1: HT interrupt enabled" newline bitfld.long 0x30 2. "TEIE,transfer error interrupt enable" "0: TE interrupt disabled,1: TE interrupt enabled" bitfld.long 0x30 1. "DMEIE,direct mode error interrupt enable" "0: DME interrupt disabled,1: DME interrupt enabled" newline bitfld.long 0x30 0. "EN,stream enable / flag stream ready when read low" "0: stream disabled,1: stream enabled" line.long 0x34 "DMA_S2NDTR,DMA stream 2 number of data register" hexmask.long.word 0x34 0.--15. 1. "NDT,number of data items to transfer (0 up to 65535)" line.long 0x38 "DMA_S2PAR,DMA stream 2 peripheral address register" hexmask.long 0x38 0.--31. 1. "PAR,peripheral address" line.long 0x3C "DMA_S2M0AR,DMA stream 2 memory 0 address register" hexmask.long 0x3C 0.--31. 1. "M0A,memory 0 address" line.long 0x40 "DMA_S2M1AR,DMA stream 2 memory 1 address register" hexmask.long 0x40 0.--31. 1. "M1A,memory 1 address (used in case of double-buffer mode)" line.long 0x44 "DMA_S2FCR,DMA stream 2 FIFO control register" bitfld.long 0x44 7. "FEIE,FIFO error interrupt enable" "0: FE interrupt disabled,1: FE interrupt enabled" rbitfld.long 0x44 3.--5. "FS,FIFO status" "0: 0 < fifo_level < 1/4,1: 1/4 ≤ fifo_level < 1/2,2: 1/2 ≤ fifo_level < 3/4,3: 3/4 ≤ fifo_level < full,4: FIFO is empty,5: FIFO is full,?,?" newline bitfld.long 0x44 2. "DMDIS,direct mode disable" "0: direct mode enabled,1: direct mode disabled" bitfld.long 0x44 0.--1. "FTH,FIFO threshold selection" "0: 1/4 full FIFO,1: 1/2 full FIFO,2: 3/4 full FIFO,3: full FIFO" line.long 0x48 "DMA_S3CR,DMA stream 3 configuration register" bitfld.long 0x48 23.--24. "MBURST,memory burst transfer configuration" "0: single transfer,1: INCR4 (incremental burst of 4 beats),2: INCR8 (incremental burst of 8 beats),3: INCR16 (incremental burst of 16 beats)" bitfld.long 0x48 21.--22. "PBURST,peripheral burst transfer configuration" "0: single transfer,1: INCR4 (incremental burst of 4 beats),2: INCR8 (incremental burst of 8 beats),3: INCR16 (incremental burst of 16 beats)" newline bitfld.long 0x48 20. "TRBUFF,Enable the DMA to handle bufferable transfers." "0: bufferable transfers not enabled,1: bufferable transfers enabled" bitfld.long 0x48 19. "CT,current target (only in double-buffer mode)" "0: current target memory is Memory 0 (addressed by..,1: current target memory is Memory 1 (addressed by.." newline bitfld.long 0x48 18. "DBM,double-buffer mode" "0: no buffer switching at the end of transfer,1: memory target switched at the end of the DMA.." bitfld.long 0x48 16.--17. "PL,priority level" "0: low,1: medium,2: high,3: very high" newline bitfld.long 0x48 15. "PINCOS,peripheral increment offset size" "0: The offset size for the peripheral address..,1: The offset size for the peripheral address.." bitfld.long 0x48 13.--14. "MSIZE,memory data size" "0: byte (8-bit),1: half-word (16-bit),2: word (32-bit),?" newline bitfld.long 0x48 11.--12. "PSIZE,peripheral data size" "0: byte (8-bit),1: half-word (16-bit),2: word (32-bit),?" bitfld.long 0x48 10. "MINC,memory increment mode" "0: memory address pointer is fixed,1: memory address pointer is incremented after each.." newline bitfld.long 0x48 9. "PINC,peripheral increment mode" "0: peripheral address pointer fixed,1: peripheral address pointer incremented after.." bitfld.long 0x48 8. "CIRC,circular mode" "0: circular mode disabled,1: circular mode enabled" newline bitfld.long 0x48 6.--7. "DIR,data transfer direction" "0: peripheral-to-memory,1: memory-to-peripheral,2: memory-to-memory,?" bitfld.long 0x48 5. "PFCTRL,peripheral flow controller" "0: DMA is the flow controller.,1: The peripheral is the flow controller." newline bitfld.long 0x48 4. "TCIE,transfer complete interrupt enable" "0: TC interrupt disabled,1: TC interrupt enabled" bitfld.long 0x48 3. "HTIE,half transfer interrupt enable" "0: HT interrupt disabled,1: HT interrupt enabled" newline bitfld.long 0x48 2. "TEIE,transfer error interrupt enable" "0: TE interrupt disabled,1: TE interrupt enabled" bitfld.long 0x48 1. "DMEIE,direct mode error interrupt enable" "0: DME interrupt disabled,1: DME interrupt enabled" newline bitfld.long 0x48 0. "EN,stream enable / flag stream ready when read low" "0: stream disabled,1: stream enabled" line.long 0x4C "DMA_S3NDTR,DMA stream 3 number of data register" hexmask.long.word 0x4C 0.--15. 1. "NDT,number of data items to transfer (0 up to 65535)" line.long 0x50 "DMA_S3PAR,DMA stream 3 peripheral address register" hexmask.long 0x50 0.--31. 1. "PAR,peripheral address" line.long 0x54 "DMA_S3M0AR,DMA stream 3 memory 0 address register" hexmask.long 0x54 0.--31. 1. "M0A,memory 0 address" line.long 0x58 "DMA_S3M1AR,DMA stream 3 memory 1 address register" hexmask.long 0x58 0.--31. 1. "M1A,memory 1 address (used in case of double-buffer mode)" line.long 0x5C "DMA_S3FCR,DMA stream 3 FIFO control register" bitfld.long 0x5C 7. "FEIE,FIFO error interrupt enable" "0: FE interrupt disabled,1: FE interrupt enabled" rbitfld.long 0x5C 3.--5. "FS,FIFO status" "0: 0 < fifo_level < 1/4,1: 1/4 ≤ fifo_level < 1/2,2: 1/2 ≤ fifo_level < 3/4,3: 3/4 ≤ fifo_level < full,4: FIFO is empty,5: FIFO is full,?,?" newline bitfld.long 0x5C 2. "DMDIS,direct mode disable" "0: direct mode enabled,1: direct mode disabled" bitfld.long 0x5C 0.--1. "FTH,FIFO threshold selection" "0: 1/4 full FIFO,1: 1/2 full FIFO,2: 3/4 full FIFO,3: full FIFO" line.long 0x60 "DMA_S4CR,DMA stream 4 configuration register" bitfld.long 0x60 23.--24. "MBURST,memory burst transfer configuration" "0: single transfer,1: INCR4 (incremental burst of 4 beats),2: INCR8 (incremental burst of 8 beats),3: INCR16 (incremental burst of 16 beats)" bitfld.long 0x60 21.--22. "PBURST,peripheral burst transfer configuration" "0: single transfer,1: INCR4 (incremental burst of 4 beats),2: INCR8 (incremental burst of 8 beats),3: INCR16 (incremental burst of 16 beats)" newline bitfld.long 0x60 20. "TRBUFF,Enable the DMA to handle bufferable transfers." "0: bufferable transfers not enabled,1: bufferable transfers enabled" bitfld.long 0x60 19. "CT,current target (only in double-buffer mode)" "0: current target memory is Memory 0 (addressed by..,1: current target memory is Memory 1 (addressed by.." newline bitfld.long 0x60 18. "DBM,double-buffer mode" "0: no buffer switching at the end of transfer,1: memory target switched at the end of the DMA.." bitfld.long 0x60 16.--17. "PL,priority level" "0: low,1: medium,2: high,3: very high" newline bitfld.long 0x60 15. "PINCOS,peripheral increment offset size" "0: The offset size for the peripheral address..,1: The offset size for the peripheral address.." bitfld.long 0x60 13.--14. "MSIZE,memory data size" "0: byte (8-bit),1: half-word (16-bit),2: word (32-bit),?" newline bitfld.long 0x60 11.--12. "PSIZE,peripheral data size" "0: byte (8-bit),1: half-word (16-bit),2: word (32-bit),?" bitfld.long 0x60 10. "MINC,memory increment mode" "0: memory address pointer is fixed,1: memory address pointer is incremented after each.." newline bitfld.long 0x60 9. "PINC,peripheral increment mode" "0: peripheral address pointer fixed,1: peripheral address pointer incremented after.." bitfld.long 0x60 8. "CIRC,circular mode" "0: circular mode disabled,1: circular mode enabled" newline bitfld.long 0x60 6.--7. "DIR,data transfer direction" "0: peripheral-to-memory,1: memory-to-peripheral,2: memory-to-memory,?" bitfld.long 0x60 5. "PFCTRL,peripheral flow controller" "0: DMA is the flow controller.,1: The peripheral is the flow controller." newline bitfld.long 0x60 4. "TCIE,transfer complete interrupt enable" "0: TC interrupt disabled,1: TC interrupt enabled" bitfld.long 0x60 3. "HTIE,half transfer interrupt enable" "0: HT interrupt disabled,1: HT interrupt enabled" newline bitfld.long 0x60 2. "TEIE,transfer error interrupt enable" "0: TE interrupt disabled,1: TE interrupt enabled" bitfld.long 0x60 1. "DMEIE,direct mode error interrupt enable" "0: DME interrupt disabled,1: DME interrupt enabled" newline bitfld.long 0x60 0. "EN,stream enable / flag stream ready when read low" "0: stream disabled,1: stream enabled" line.long 0x64 "DMA_S4NDTR,DMA stream 4 number of data register" hexmask.long.word 0x64 0.--15. 1. "NDT,number of data items to transfer (0 up to 65535)" line.long 0x68 "DMA_S4PAR,DMA stream 4 peripheral address register" hexmask.long 0x68 0.--31. 1. "PAR,peripheral address" line.long 0x6C "DMA_S4M0AR,DMA stream 4 memory 0 address register" hexmask.long 0x6C 0.--31. 1. "M0A,memory 0 address" line.long 0x70 "DMA_S4M1AR,DMA stream 4 memory 1 address register" hexmask.long 0x70 0.--31. 1. "M1A,memory 1 address (used in case of double-buffer mode)" line.long 0x74 "DMA_S4FCR,DMA stream 4 FIFO control register" bitfld.long 0x74 7. "FEIE,FIFO error interrupt enable" "0: FE interrupt disabled,1: FE interrupt enabled" rbitfld.long 0x74 3.--5. "FS,FIFO status" "0: 0 < fifo_level < 1/4,1: 1/4 ≤ fifo_level < 1/2,2: 1/2 ≤ fifo_level < 3/4,3: 3/4 ≤ fifo_level < full,4: FIFO is empty,5: FIFO is full,?,?" newline bitfld.long 0x74 2. "DMDIS,direct mode disable" "0: direct mode enabled,1: direct mode disabled" bitfld.long 0x74 0.--1. "FTH,FIFO threshold selection" "0: 1/4 full FIFO,1: 1/2 full FIFO,2: 3/4 full FIFO,3: full FIFO" line.long 0x78 "DMA_S5CR,DMA stream 5 configuration register" bitfld.long 0x78 23.--24. "MBURST,memory burst transfer configuration" "0: single transfer,1: INCR4 (incremental burst of 4 beats),2: INCR8 (incremental burst of 8 beats),3: INCR16 (incremental burst of 16 beats)" bitfld.long 0x78 21.--22. "PBURST,peripheral burst transfer configuration" "0: single transfer,1: INCR4 (incremental burst of 4 beats),2: INCR8 (incremental burst of 8 beats),3: INCR16 (incremental burst of 16 beats)" newline bitfld.long 0x78 20. "TRBUFF,Enable the DMA to handle bufferable transfers." "0: bufferable transfers not enabled,1: bufferable transfers enabled" bitfld.long 0x78 19. "CT,current target (only in double-buffer mode)" "0: current target memory is Memory 0 (addressed by..,1: current target memory is Memory 1 (addressed by.." newline bitfld.long 0x78 18. "DBM,double-buffer mode" "0: no buffer switching at the end of transfer,1: memory target switched at the end of the DMA.." bitfld.long 0x78 16.--17. "PL,priority level" "0: low,1: medium,2: high,3: very high" newline bitfld.long 0x78 15. "PINCOS,peripheral increment offset size" "0: The offset size for the peripheral address..,1: The offset size for the peripheral address.." bitfld.long 0x78 13.--14. "MSIZE,memory data size" "0: byte (8-bit),1: half-word (16-bit),2: word (32-bit),?" newline bitfld.long 0x78 11.--12. "PSIZE,peripheral data size" "0: byte (8-bit),1: half-word (16-bit),2: word (32-bit),?" bitfld.long 0x78 10. "MINC,memory increment mode" "0: memory address pointer is fixed,1: memory address pointer is incremented after each.." newline bitfld.long 0x78 9. "PINC,peripheral increment mode" "0: peripheral address pointer fixed,1: peripheral address pointer incremented after.." bitfld.long 0x78 8. "CIRC,circular mode" "0: circular mode disabled,1: circular mode enabled" newline bitfld.long 0x78 6.--7. "DIR,data transfer direction" "0: peripheral-to-memory,1: memory-to-peripheral,2: memory-to-memory,?" bitfld.long 0x78 5. "PFCTRL,peripheral flow controller" "0: DMA is the flow controller.,1: The peripheral is the flow controller." newline bitfld.long 0x78 4. "TCIE,transfer complete interrupt enable" "0: TC interrupt disabled,1: TC interrupt enabled" bitfld.long 0x78 3. "HTIE,half transfer interrupt enable" "0: HT interrupt disabled,1: HT interrupt enabled" newline bitfld.long 0x78 2. "TEIE,transfer error interrupt enable" "0: TE interrupt disabled,1: TE interrupt enabled" bitfld.long 0x78 1. "DMEIE,direct mode error interrupt enable" "0: DME interrupt disabled,1: DME interrupt enabled" newline bitfld.long 0x78 0. "EN,stream enable / flag stream ready when read low" "0: stream disabled,1: stream enabled" line.long 0x7C "DMA_S5NDTR,DMA stream 5 number of data register" hexmask.long.word 0x7C 0.--15. 1. "NDT,number of data items to transfer (0 up to 65535)" line.long 0x80 "DMA_S5PAR,DMA stream 5 peripheral address register" hexmask.long 0x80 0.--31. 1. "PAR,peripheral address" line.long 0x84 "DMA_S5M0AR,DMA stream 5 memory 0 address register" hexmask.long 0x84 0.--31. 1. "M0A,memory 0 address" line.long 0x88 "DMA_S5M1AR,DMA stream 5 memory 1 address register" hexmask.long 0x88 0.--31. 1. "M1A,memory 1 address (used in case of double-buffer mode)" line.long 0x8C "DMA_S5FCR,DMA stream 5 FIFO control register" bitfld.long 0x8C 7. "FEIE,FIFO error interrupt enable" "0: FE interrupt disabled,1: FE interrupt enabled" rbitfld.long 0x8C 3.--5. "FS,FIFO status" "0: 0 < fifo_level < 1/4,1: 1/4 ≤ fifo_level < 1/2,2: 1/2 ≤ fifo_level < 3/4,3: 3/4 ≤ fifo_level < full,4: FIFO is empty,5: FIFO is full,?,?" newline bitfld.long 0x8C 2. "DMDIS,direct mode disable" "0: direct mode enabled,1: direct mode disabled" bitfld.long 0x8C 0.--1. "FTH,FIFO threshold selection" "0: 1/4 full FIFO,1: 1/2 full FIFO,2: 3/4 full FIFO,3: full FIFO" line.long 0x90 "DMA_S6CR,DMA stream 6 configuration register" bitfld.long 0x90 23.--24. "MBURST,memory burst transfer configuration" "0: single transfer,1: INCR4 (incremental burst of 4 beats),2: INCR8 (incremental burst of 8 beats),3: INCR16 (incremental burst of 16 beats)" bitfld.long 0x90 21.--22. "PBURST,peripheral burst transfer configuration" "0: single transfer,1: INCR4 (incremental burst of 4 beats),2: INCR8 (incremental burst of 8 beats),3: INCR16 (incremental burst of 16 beats)" newline bitfld.long 0x90 20. "TRBUFF,Enable the DMA to handle bufferable transfers." "0: bufferable transfers not enabled,1: bufferable transfers enabled" bitfld.long 0x90 19. "CT,current target (only in double-buffer mode)" "0: current target memory is Memory 0 (addressed by..,1: current target memory is Memory 1 (addressed by.." newline bitfld.long 0x90 18. "DBM,double-buffer mode" "0: no buffer switching at the end of transfer,1: memory target switched at the end of the DMA.." bitfld.long 0x90 16.--17. "PL,priority level" "0: low,1: medium,2: high,3: very high" newline bitfld.long 0x90 15. "PINCOS,peripheral increment offset size" "0: The offset size for the peripheral address..,1: The offset size for the peripheral address.." bitfld.long 0x90 13.--14. "MSIZE,memory data size" "0: byte (8-bit),1: half-word (16-bit),2: word (32-bit),?" newline bitfld.long 0x90 11.--12. "PSIZE,peripheral data size" "0: byte (8-bit),1: half-word (16-bit),2: word (32-bit),?" bitfld.long 0x90 10. "MINC,memory increment mode" "0: memory address pointer is fixed,1: memory address pointer is incremented after each.." newline bitfld.long 0x90 9. "PINC,peripheral increment mode" "0: peripheral address pointer fixed,1: peripheral address pointer incremented after.." bitfld.long 0x90 8. "CIRC,circular mode" "0: circular mode disabled,1: circular mode enabled" newline bitfld.long 0x90 6.--7. "DIR,data transfer direction" "0: peripheral-to-memory,1: memory-to-peripheral,2: memory-to-memory,?" bitfld.long 0x90 5. "PFCTRL,peripheral flow controller" "0: DMA is the flow controller.,1: The peripheral is the flow controller." newline bitfld.long 0x90 4. "TCIE,transfer complete interrupt enable" "0: TC interrupt disabled,1: TC interrupt enabled" bitfld.long 0x90 3. "HTIE,half transfer interrupt enable" "0: HT interrupt disabled,1: HT interrupt enabled" newline bitfld.long 0x90 2. "TEIE,transfer error interrupt enable" "0: TE interrupt disabled,1: TE interrupt enabled" bitfld.long 0x90 1. "DMEIE,direct mode error interrupt enable" "0: DME interrupt disabled,1: DME interrupt enabled" newline bitfld.long 0x90 0. "EN,stream enable / flag stream ready when read low" "0: stream disabled,1: stream enabled" line.long 0x94 "DMA_S6NDTR,DMA stream 6 number of data register" hexmask.long.word 0x94 0.--15. 1. "NDT,number of data items to transfer (0 up to 65535)" line.long 0x98 "DMA_S6PAR,DMA stream 6 peripheral address register" hexmask.long 0x98 0.--31. 1. "PAR,peripheral address" line.long 0x9C "DMA_S6M0AR,DMA stream 6 memory 0 address register" hexmask.long 0x9C 0.--31. 1. "M0A,memory 0 address" line.long 0xA0 "DMA_S6M1AR,DMA stream 6 memory 1 address register" hexmask.long 0xA0 0.--31. 1. "M1A,memory 1 address (used in case of double-buffer mode)" line.long 0xA4 "DMA_S6FCR,DMA stream 6 FIFO control register" bitfld.long 0xA4 7. "FEIE,FIFO error interrupt enable" "0: FE interrupt disabled,1: FE interrupt enabled" rbitfld.long 0xA4 3.--5. "FS,FIFO status" "0: 0 < fifo_level < 1/4,1: 1/4 ≤ fifo_level < 1/2,2: 1/2 ≤ fifo_level < 3/4,3: 3/4 ≤ fifo_level < full,4: FIFO is empty,5: FIFO is full,?,?" newline bitfld.long 0xA4 2. "DMDIS,direct mode disable" "0: direct mode enabled,1: direct mode disabled" bitfld.long 0xA4 0.--1. "FTH,FIFO threshold selection" "0: 1/4 full FIFO,1: 1/2 full FIFO,2: 3/4 full FIFO,3: full FIFO" line.long 0xA8 "DMA_S7CR,DMA stream 7 configuration register" bitfld.long 0xA8 23.--24. "MBURST,memory burst transfer configuration" "0: single transfer,1: INCR4 (incremental burst of 4 beats),2: INCR8 (incremental burst of 8 beats),3: INCR16 (incremental burst of 16 beats)" bitfld.long 0xA8 21.--22. "PBURST,peripheral burst transfer configuration" "0: single transfer,1: INCR4 (incremental burst of 4 beats),2: INCR8 (incremental burst of 8 beats),3: INCR16 (incremental burst of 16 beats)" newline bitfld.long 0xA8 20. "TRBUFF,Enable the DMA to handle bufferable transfers." "0: bufferable transfers not enabled,1: bufferable transfers enabled" bitfld.long 0xA8 19. "CT,current target (only in double-buffer mode)" "0: current target memory is Memory 0 (addressed by..,1: current target memory is Memory 1 (addressed by.." newline bitfld.long 0xA8 18. "DBM,double-buffer mode" "0: no buffer switching at the end of transfer,1: memory target switched at the end of the DMA.." bitfld.long 0xA8 16.--17. "PL,priority level" "0: low,1: medium,2: high,3: very high" newline bitfld.long 0xA8 15. "PINCOS,peripheral increment offset size" "0: The offset size for the peripheral address..,1: The offset size for the peripheral address.." bitfld.long 0xA8 13.--14. "MSIZE,memory data size" "0: byte (8-bit),1: half-word (16-bit),2: word (32-bit),?" newline bitfld.long 0xA8 11.--12. "PSIZE,peripheral data size" "0: byte (8-bit),1: half-word (16-bit),2: word (32-bit),?" bitfld.long 0xA8 10. "MINC,memory increment mode" "0: memory address pointer is fixed,1: memory address pointer is incremented after each.." newline bitfld.long 0xA8 9. "PINC,peripheral increment mode" "0: peripheral address pointer fixed,1: peripheral address pointer incremented after.." bitfld.long 0xA8 8. "CIRC,circular mode" "0: circular mode disabled,1: circular mode enabled" newline bitfld.long 0xA8 6.--7. "DIR,data transfer direction" "0: peripheral-to-memory,1: memory-to-peripheral,2: memory-to-memory,?" bitfld.long 0xA8 5. "PFCTRL,peripheral flow controller" "0: DMA is the flow controller.,1: The peripheral is the flow controller." newline bitfld.long 0xA8 4. "TCIE,transfer complete interrupt enable" "0: TC interrupt disabled,1: TC interrupt enabled" bitfld.long 0xA8 3. "HTIE,half transfer interrupt enable" "0: HT interrupt disabled,1: HT interrupt enabled" newline bitfld.long 0xA8 2. "TEIE,transfer error interrupt enable" "0: TE interrupt disabled,1: TE interrupt enabled" bitfld.long 0xA8 1. "DMEIE,direct mode error interrupt enable" "0: DME interrupt disabled,1: DME interrupt enabled" newline bitfld.long 0xA8 0. "EN,stream enable / flag stream ready when read low" "0: stream disabled,1: stream enabled" line.long 0xAC "DMA_S7NDTR,DMA stream 7 number of data register" hexmask.long.word 0xAC 0.--15. 1. "NDT,number of data items to transfer (0 up to 65535)" line.long 0xB0 "DMA_S7PAR,DMA stream 7 peripheral address register" hexmask.long 0xB0 0.--31. 1. "PAR,peripheral address" line.long 0xB4 "DMA_S7M0AR,DMA stream 7 memory 0 address register" hexmask.long 0xB4 0.--31. 1. "M0A,memory 0 address" line.long 0xB8 "DMA_S7M1AR,DMA stream 7 memory 1 address register" hexmask.long 0xB8 0.--31. 1. "M1A,memory 1 address (used in case of double-buffer mode)" line.long 0xBC "DMA_S7FCR,DMA stream 7 FIFO control register" bitfld.long 0xBC 7. "FEIE,FIFO error interrupt enable" "0: FE interrupt disabled,1: FE interrupt enabled" rbitfld.long 0xBC 3.--5. "FS,FIFO status" "0: 0 < fifo_level < 1/4,1: 1/4 ≤ fifo_level < 1/2,2: 1/2 ≤ fifo_level < 3/4,3: 3/4 ≤ fifo_level < full,4: FIFO is empty,5: FIFO is full,?,?" newline bitfld.long 0xBC 2. "DMDIS,direct mode disable" "0: direct mode enabled,1: direct mode disabled" bitfld.long 0xBC 0.--1. "FTH,FIFO threshold selection" "0: 1/4 full FIFO,1: 1/2 full FIFO,2: 3/4 full FIFO,3: full FIFO" rgroup.long 0x3EC++0x13 line.long 0x0 "DMA_HWCFGR2,DMA hardware configuration 2 register" bitfld.long 0x0 8.--10. "CHSEL_WIDTH,bit width of the CHSEL field of any DMA_SxCR register common to all streams" "0: no programmable selection,1: 2 channels programmable selection,2: up to 8 channels programmable selection,3: up to 16 channels programmable selection,4: up to 32 channels programmable selection,5: up to 64 channels programmable selection,6: up to 128 channels programmable selection,?" bitfld.long 0x0 4. "WRITE_BUFFERABLE,In any case DMA acknowledge signal is asserted one cycle after the address phase of the bus access on its AHB peripheral master port." "0: DMA acknowledge signal is de-asserted one cycle..,1: DMA acknowledge signal is de-asserted exactly.." newline bitfld.long 0x0 0.--1. "FIFO_SIZE,FIFO size common to all streams" "0: 2-word FIFO,1: 4-word FIFO,2: 8-word FIFO,3: 16-word FIFO" line.long 0x4 "DMA_HWCFGR1,DMA hardware configuration 1 register" bitfld.long 0x4 28.--29. "DMA_DEF7,type of the stream 7" "0: none,1: regular,2: double-buffer,3: Reserved" bitfld.long 0x4 24.--25. "DMA_DEF6,type of the stream 6" "0: none,1: regular,2: double-buffer,3: Reserved" newline bitfld.long 0x4 20.--21. "DMA_DEF5,type of the stream 5" "0: none,1: regular,2: double-buffer,3: Reserved" bitfld.long 0x4 16.--17. "DMA_DEF4,type of the stream 4" "0: none,1: regular,2: double-buffer,3: Reserved" newline bitfld.long 0x4 12.--13. "DMA_DEF3,type of the stream 3" "0: none,1: regular,2: double-buffer,3: Reserved" bitfld.long 0x4 8.--9. "DMA_DEF2,type of the stream 2" "0: none,1: regular,2: double-buffer,3: Reserved" newline bitfld.long 0x4 4.--5. "DMA_DEF1,type of the stream 1" "0: none,1: regular,2: double-buffer,3: Reserved" bitfld.long 0x4 0.--1. "DMA_DEF0,type of the stream 0" "0: none,1: regular,2: double-buffer,3: Reserved" line.long 0x8 "DMA_VERR,DMA version register" hexmask.long.byte 0x8 4.--7. 1. "MAJREV,major IP revision" hexmask.long.byte 0x8 0.--3. 1. "MINREV,minor IP revision" line.long 0xC "DMA_IPDR,DMA identification register" hexmask.long 0xC 0.--31. 1. "ID,size identification" line.long 0x10 "DMA_SIDR,DMA size identification register" hexmask.long 0x10 0.--31. 1. "SID,size identification" tree.end endif sif (cpuis("STM32MP151*")||cpuis("STM32MP153*")||cpuis("STM32MP157*")) tree "DMA1" base ad:0x48000000 rgroup.long 0x0++0x7 line.long 0x0 "DMA_LISR,DMA low interrupt status register" bitfld.long 0x0 27. "TCIF3,TCIF3" "0,1" bitfld.long 0x0 26. "HTIF3,HTIF3" "0,1" bitfld.long 0x0 25. "TEIF3,TEIF3" "0,1" bitfld.long 0x0 24. "DMEIF3,DMEIF3" "0,1" bitfld.long 0x0 22. "FEIF3,FEIF3" "0,1" bitfld.long 0x0 21. "TCIF2,TCIF2" "0,1" newline bitfld.long 0x0 20. "HTIF2,HTIF2" "0,1" bitfld.long 0x0 19. "TEIF2,TEIF2" "0,1" bitfld.long 0x0 18. "DMEIF2,DMEIF2" "0,1" bitfld.long 0x0 16. "FEIF2,FEIF2" "0,1" bitfld.long 0x0 11. "TCIF1,TCIF1" "0,1" bitfld.long 0x0 10. "HTIF1,HTIF1" "0,1" newline bitfld.long 0x0 9. "TEIF1,TEIF1" "0,1" bitfld.long 0x0 8. "DMEIF1,DMEIF1" "0,1" bitfld.long 0x0 6. "FEIF1,FEIF1" "0,1" bitfld.long 0x0 5. "TCIF0,TCIF0" "0,1" bitfld.long 0x0 4. "HTIF0,HTIF0" "0,1" bitfld.long 0x0 3. "TEIF0,TEIF0" "0,1" newline bitfld.long 0x0 2. "DMEIF0,DMEIF0" "0,1" bitfld.long 0x0 0. "FEIF0,FEIF0" "0,1" line.long 0x4 "DMA_HISR,DMA high interrupt status register" bitfld.long 0x4 27. "TCIF7,TCIF7" "0,1" bitfld.long 0x4 26. "HTIF7,HTIF7" "0,1" bitfld.long 0x4 25. "TEIF7,TEIF7" "0,1" bitfld.long 0x4 24. "DMEIF7,DMEIF7" "0,1" bitfld.long 0x4 22. "FEIF7,FEIF7" "0,1" bitfld.long 0x4 21. "TCIF6,TCIF6" "0,1" newline bitfld.long 0x4 20. "HTIF6,HTIF6" "0,1" bitfld.long 0x4 19. "TEIF6,TEIF6" "0,1" bitfld.long 0x4 18. "DMEIF6,DMEIF6" "0,1" bitfld.long 0x4 16. "FEIF6,FEIF6" "0,1" bitfld.long 0x4 11. "TCIF5,TCIF5" "0,1" bitfld.long 0x4 10. "HTIF5,HTIF5" "0,1" newline bitfld.long 0x4 9. "TEIF5,TEIF5" "0,1" bitfld.long 0x4 8. "DMEIF5,DMEIF5" "0,1" bitfld.long 0x4 6. "FEIF5,FEIF5" "0,1" bitfld.long 0x4 5. "TCIF4,TCIF4" "0,1" bitfld.long 0x4 4. "HTIF4,HTIF4" "0,1" bitfld.long 0x4 3. "TEIF4,TEIF4" "0,1" newline bitfld.long 0x4 2. "DMEIF4,DMEIF4" "0,1" bitfld.long 0x4 0. "FEIF4,FEIF4" "0,1" wgroup.long 0x8++0x7 line.long 0x0 "DMA_LIFCR,DMA low interrupt flag clear register" bitfld.long 0x0 27. "CTCIF3,CTCIF3" "0,1" bitfld.long 0x0 26. "CHTIF3,CHTIF3" "0,1" bitfld.long 0x0 25. "CTEIF3,CTEIF3" "0,1" bitfld.long 0x0 24. "CDMEIF3,CDMEIF3" "0,1" bitfld.long 0x0 22. "CFEIF3,CFEIF3" "0,1" bitfld.long 0x0 21. "CTCIF2,CTCIF2" "0,1" newline bitfld.long 0x0 20. "CHTIF2,CHTIF2" "0,1" bitfld.long 0x0 19. "CTEIF2,CTEIF2" "0,1" bitfld.long 0x0 18. "CDMEIF2,CDMEIF2" "0,1" bitfld.long 0x0 16. "CFEIF2,CFEIF2" "0,1" bitfld.long 0x0 11. "CTCIF1,CTCIF1" "0,1" bitfld.long 0x0 10. "CHTIF1,CHTIF1" "0,1" newline bitfld.long 0x0 9. "CTEIF1,CTEIF1" "0,1" bitfld.long 0x0 8. "CDMEIF1,CDMEIF1" "0,1" bitfld.long 0x0 6. "CFEIF1,CFEIF1" "0,1" bitfld.long 0x0 5. "CTCIF0,CTCIF0" "0,1" bitfld.long 0x0 4. "CHTIF0,CHTIF0" "0,1" bitfld.long 0x0 3. "CTEIF0,CTEIF0" "0,1" newline bitfld.long 0x0 2. "CDMEIF0,CDMEIF0" "0,1" bitfld.long 0x0 0. "CFEIF0,CFEIF0" "0,1" line.long 0x4 "DMA_HIFCR,DMA high interrupt flag clear register" bitfld.long 0x4 27. "CTCIF7,CTCIF7" "0,1" bitfld.long 0x4 26. "CHTIF7,CHTIF7" "0,1" bitfld.long 0x4 25. "CTEIF7,CTEIF7" "0,1" bitfld.long 0x4 24. "CDMEIF7,CDMEIF7" "0,1" bitfld.long 0x4 22. "CFEIF7,CFEIF7" "0,1" bitfld.long 0x4 21. "CTCIF6,CTCIF6" "0,1" newline bitfld.long 0x4 20. "CHTIF6,CHTIF6" "0,1" bitfld.long 0x4 19. "CTEIF6,CTEIF6" "0,1" bitfld.long 0x4 18. "CDMEIF6,CDMEIF6" "0,1" bitfld.long 0x4 16. "CFEIF6,CFEIF6" "0,1" bitfld.long 0x4 11. "CTCIF5,CTCIF5" "0,1" bitfld.long 0x4 10. "CHTIF5,CHTIF5" "0,1" newline bitfld.long 0x4 9. "CTEIF5,CTEIF5" "0,1" bitfld.long 0x4 8. "CDMEIF5,CDMEIF5" "0,1" bitfld.long 0x4 6. "CFEIF5,CFEIF5" "0,1" bitfld.long 0x4 5. "CTCIF4,CTCIF4" "0,1" bitfld.long 0x4 4. "CHTIF4,CHTIF4" "0,1" bitfld.long 0x4 3. "CTEIF4,CTEIF4" "0,1" newline bitfld.long 0x4 2. "CDMEIF4,CDMEIF4" "0,1" bitfld.long 0x4 0. "CFEIF4,CFEIF4" "0,1" group.long 0x10++0xBF line.long 0x0 "DMA_S0CR,This register is used to configure the concerned stream." bitfld.long 0x0 23.--24. "MBURST,MBURST" "0,1,2,3" bitfld.long 0x0 21.--22. "PBURST,PBURST" "0,1,2,3" bitfld.long 0x0 19. "CT,CT" "0,1" bitfld.long 0x0 18. "DBM,DBM" "0,1" bitfld.long 0x0 16.--17. "PL,PL" "0,1,2,3" bitfld.long 0x0 15. "PINCOS,PINCOS" "0,1" newline bitfld.long 0x0 13.--14. "MSIZE,MSIZE" "0,1,2,3" bitfld.long 0x0 11.--12. "PSIZE,PSIZE" "0,1,2,3" bitfld.long 0x0 10. "MINC,MINC" "0,1" bitfld.long 0x0 9. "PINC,PINC" "0,1" bitfld.long 0x0 8. "CIRC,CIRC" "0,1" bitfld.long 0x0 6.--7. "DIR,DIR" "0,1,2,3" newline bitfld.long 0x0 5. "PFCTRL,PFCTRL" "0,1" bitfld.long 0x0 4. "TCIE,TCIE" "0,1" bitfld.long 0x0 3. "HTIE,HTIE" "0,1" bitfld.long 0x0 2. "TEIE,TEIE" "0,1" bitfld.long 0x0 1. "DMEIE,DMEIE" "0,1" bitfld.long 0x0 0. "EN,EN" "0,1" line.long 0x4 "DMA_S0NDTR,DMA stream 0 number of data register" hexmask.long.word 0x4 0.--15. 1. "NDT,NDT" line.long 0x8 "DMA_S0PAR,DMA stream 0 peripheral address register" hexmask.long 0x8 0.--31. 1. "PAR,PAR" line.long 0xC "DMA_S0M0AR,DMA stream 0 memory 0 address register" hexmask.long 0xC 0.--31. 1. "M0A,M0A" line.long 0x10 "DMA_S0M1AR,DMA stream 0 memory 1 address register" hexmask.long 0x10 0.--31. 1. "M1A,M1A" line.long 0x14 "DMA_S0FCR,DMA stream 0 FIFO control register" bitfld.long 0x14 7. "FEIE,FEIE" "0,1" rbitfld.long 0x14 3.--5. "FS,FS" "0,1,2,3,4,5,6,7" bitfld.long 0x14 2. "DMDIS,DMDIS" "0,1" bitfld.long 0x14 0.--1. "FTH,FTH" "0,1,2,3" line.long 0x18 "DMA_S1CR,This register is used to configure the concerned stream." bitfld.long 0x18 23.--24. "MBURST,MBURST" "0,1,2,3" bitfld.long 0x18 21.--22. "PBURST,PBURST" "0,1,2,3" bitfld.long 0x18 19. "CT,CT" "0,1" bitfld.long 0x18 18. "DBM,DBM" "0,1" bitfld.long 0x18 16.--17. "PL,PL" "0,1,2,3" bitfld.long 0x18 15. "PINCOS,PINCOS" "0,1" newline bitfld.long 0x18 13.--14. "MSIZE,MSIZE" "0,1,2,3" bitfld.long 0x18 11.--12. "PSIZE,PSIZE" "0,1,2,3" bitfld.long 0x18 10. "MINC,MINC" "0,1" bitfld.long 0x18 9. "PINC,PINC" "0,1" bitfld.long 0x18 8. "CIRC,CIRC" "0,1" bitfld.long 0x18 6.--7. "DIR,DIR" "0,1,2,3" newline bitfld.long 0x18 5. "PFCTRL,PFCTRL" "0,1" bitfld.long 0x18 4. "TCIE,TCIE" "0,1" bitfld.long 0x18 3. "HTIE,HTIE" "0,1" bitfld.long 0x18 2. "TEIE,TEIE" "0,1" bitfld.long 0x18 1. "DMEIE,DMEIE" "0,1" bitfld.long 0x18 0. "EN,EN" "0,1" line.long 0x1C "DMA_S1NDTR,DMA stream 1 number of data register" hexmask.long.word 0x1C 0.--15. 1. "NDT,NDT" line.long 0x20 "DMA_S1PAR,DMA stream 1 peripheral address register" hexmask.long 0x20 0.--31. 1. "PAR,PAR" line.long 0x24 "DMA_S1M0AR,DMA stream 1 memory 0 address register" hexmask.long 0x24 0.--31. 1. "M0A,M0A" line.long 0x28 "DMA_S1M1AR,DMA stream 1 memory 1 address register" hexmask.long 0x28 0.--31. 1. "M1A,M1A" line.long 0x2C "DMA_S1FCR,DMA stream 1 FIFO control register" bitfld.long 0x2C 7. "FEIE,FEIE" "0,1" rbitfld.long 0x2C 3.--5. "FS,FS" "0,1,2,3,4,5,6,7" bitfld.long 0x2C 2. "DMDIS,DMDIS" "0,1" bitfld.long 0x2C 0.--1. "FTH,FTH" "0,1,2,3" line.long 0x30 "DMA_S2CR,This register is used to configure the concerned stream." bitfld.long 0x30 23.--24. "MBURST,MBURST" "0,1,2,3" bitfld.long 0x30 21.--22. "PBURST,PBURST" "0,1,2,3" bitfld.long 0x30 19. "CT,CT" "0,1" bitfld.long 0x30 18. "DBM,DBM" "0,1" bitfld.long 0x30 16.--17. "PL,PL" "0,1,2,3" bitfld.long 0x30 15. "PINCOS,PINCOS" "0,1" newline bitfld.long 0x30 13.--14. "MSIZE,MSIZE" "0,1,2,3" bitfld.long 0x30 11.--12. "PSIZE,PSIZE" "0,1,2,3" bitfld.long 0x30 10. "MINC,MINC" "0,1" bitfld.long 0x30 9. "PINC,PINC" "0,1" bitfld.long 0x30 8. "CIRC,CIRC" "0,1" bitfld.long 0x30 6.--7. "DIR,DIR" "0,1,2,3" newline bitfld.long 0x30 5. "PFCTRL,PFCTRL" "0,1" bitfld.long 0x30 4. "TCIE,TCIE" "0,1" bitfld.long 0x30 3. "HTIE,HTIE" "0,1" bitfld.long 0x30 2. "TEIE,TEIE" "0,1" bitfld.long 0x30 1. "DMEIE,DMEIE" "0,1" bitfld.long 0x30 0. "EN,EN" "0,1" line.long 0x34 "DMA_S2NDTR,DMA stream 2 number of data register" hexmask.long.word 0x34 0.--15. 1. "NDT,NDT" line.long 0x38 "DMA_S2PAR,DMA stream 2 peripheral address register" hexmask.long 0x38 0.--31. 1. "PAR,PAR" line.long 0x3C "DMA_S2M0AR,DMA stream 2 memory 0 address register" hexmask.long 0x3C 0.--31. 1. "M0A,M0A" line.long 0x40 "DMA_S2M1AR,DMA stream 2 memory 1 address register" hexmask.long 0x40 0.--31. 1. "M1A,M1A" line.long 0x44 "DMA_S2FCR,DMA stream 2 FIFO control register" bitfld.long 0x44 7. "FEIE,FEIE" "0,1" rbitfld.long 0x44 3.--5. "FS,FS" "0,1,2,3,4,5,6,7" bitfld.long 0x44 2. "DMDIS,DMDIS" "0,1" bitfld.long 0x44 0.--1. "FTH,FTH" "0,1,2,3" line.long 0x48 "DMA_S3CR,This register is used to configure the concerned stream." bitfld.long 0x48 23.--24. "MBURST,MBURST" "0,1,2,3" bitfld.long 0x48 21.--22. "PBURST,PBURST" "0,1,2,3" bitfld.long 0x48 19. "CT,CT" "0,1" bitfld.long 0x48 18. "DBM,DBM" "0,1" bitfld.long 0x48 16.--17. "PL,PL" "0,1,2,3" bitfld.long 0x48 15. "PINCOS,PINCOS" "0,1" newline bitfld.long 0x48 13.--14. "MSIZE,MSIZE" "0,1,2,3" bitfld.long 0x48 11.--12. "PSIZE,PSIZE" "0,1,2,3" bitfld.long 0x48 10. "MINC,MINC" "0,1" bitfld.long 0x48 9. "PINC,PINC" "0,1" bitfld.long 0x48 8. "CIRC,CIRC" "0,1" bitfld.long 0x48 6.--7. "DIR,DIR" "0,1,2,3" newline bitfld.long 0x48 5. "PFCTRL,PFCTRL" "0,1" bitfld.long 0x48 4. "TCIE,TCIE" "0,1" bitfld.long 0x48 3. "HTIE,HTIE" "0,1" bitfld.long 0x48 2. "TEIE,TEIE" "0,1" bitfld.long 0x48 1. "DMEIE,DMEIE" "0,1" bitfld.long 0x48 0. "EN,EN" "0,1" line.long 0x4C "DMA_S3NDTR,DMA stream 3 number of data register" hexmask.long.word 0x4C 0.--15. 1. "NDT,NDT" line.long 0x50 "DMA_S3PAR,DMA stream 3 peripheral address register" hexmask.long 0x50 0.--31. 1. "PAR,PAR" line.long 0x54 "DMA_S3M0AR,DMA stream 3 memory 0 address register" hexmask.long 0x54 0.--31. 1. "M0A,M0A" line.long 0x58 "DMA_S3M1AR,DMA stream 3 memory 1 address register" hexmask.long 0x58 0.--31. 1. "M1A,M1A" line.long 0x5C "DMA_S3FCR,DMA stream 3 FIFO control register" bitfld.long 0x5C 7. "FEIE,FEIE" "0,1" rbitfld.long 0x5C 3.--5. "FS,FS" "0,1,2,3,4,5,6,7" bitfld.long 0x5C 2. "DMDIS,DMDIS" "0,1" bitfld.long 0x5C 0.--1. "FTH,FTH" "0,1,2,3" line.long 0x60 "DMA_S4CR,This register is used to configure the concerned stream." bitfld.long 0x60 23.--24. "MBURST,MBURST" "0,1,2,3" bitfld.long 0x60 21.--22. "PBURST,PBURST" "0,1,2,3" bitfld.long 0x60 19. "CT,CT" "0,1" bitfld.long 0x60 18. "DBM,DBM" "0,1" bitfld.long 0x60 16.--17. "PL,PL" "0,1,2,3" bitfld.long 0x60 15. "PINCOS,PINCOS" "0,1" newline bitfld.long 0x60 13.--14. "MSIZE,MSIZE" "0,1,2,3" bitfld.long 0x60 11.--12. "PSIZE,PSIZE" "0,1,2,3" bitfld.long 0x60 10. "MINC,MINC" "0,1" bitfld.long 0x60 9. "PINC,PINC" "0,1" bitfld.long 0x60 8. "CIRC,CIRC" "0,1" bitfld.long 0x60 6.--7. "DIR,DIR" "0,1,2,3" newline bitfld.long 0x60 5. "PFCTRL,PFCTRL" "0,1" bitfld.long 0x60 4. "TCIE,TCIE" "0,1" bitfld.long 0x60 3. "HTIE,HTIE" "0,1" bitfld.long 0x60 2. "TEIE,TEIE" "0,1" bitfld.long 0x60 1. "DMEIE,DMEIE" "0,1" bitfld.long 0x60 0. "EN,EN" "0,1" line.long 0x64 "DMA_S4NDTR,DMA stream 4 number of data register" hexmask.long.word 0x64 0.--15. 1. "NDT,NDT" line.long 0x68 "DMA_S4PAR,DMA stream 4 peripheral address register" hexmask.long 0x68 0.--31. 1. "PAR,PAR" line.long 0x6C "DMA_S4M0AR,DMA stream 4 memory 0 address register" hexmask.long 0x6C 0.--31. 1. "M0A,M0A" line.long 0x70 "DMA_S4M1AR,DMA stream 4 memory 1 address register" hexmask.long 0x70 0.--31. 1. "M1A,M1A" line.long 0x74 "DMA_S4FCR,DMA stream 4 FIFO control register" bitfld.long 0x74 7. "FEIE,FEIE" "0,1" rbitfld.long 0x74 3.--5. "FS,FS" "0,1,2,3,4,5,6,7" bitfld.long 0x74 2. "DMDIS,DMDIS" "0,1" bitfld.long 0x74 0.--1. "FTH,FTH" "0,1,2,3" line.long 0x78 "DMA_S5CR,This register is used to configure the concerned stream." bitfld.long 0x78 23.--24. "MBURST,MBURST" "0,1,2,3" bitfld.long 0x78 21.--22. "PBURST,PBURST" "0,1,2,3" bitfld.long 0x78 19. "CT,CT" "0,1" bitfld.long 0x78 18. "DBM,DBM" "0,1" bitfld.long 0x78 16.--17. "PL,PL" "0,1,2,3" bitfld.long 0x78 15. "PINCOS,PINCOS" "0,1" newline bitfld.long 0x78 13.--14. "MSIZE,MSIZE" "0,1,2,3" bitfld.long 0x78 11.--12. "PSIZE,PSIZE" "0,1,2,3" bitfld.long 0x78 10. "MINC,MINC" "0,1" bitfld.long 0x78 9. "PINC,PINC" "0,1" bitfld.long 0x78 8. "CIRC,CIRC" "0,1" bitfld.long 0x78 6.--7. "DIR,DIR" "0,1,2,3" newline bitfld.long 0x78 5. "PFCTRL,PFCTRL" "0,1" bitfld.long 0x78 4. "TCIE,TCIE" "0,1" bitfld.long 0x78 3. "HTIE,HTIE" "0,1" bitfld.long 0x78 2. "TEIE,TEIE" "0,1" bitfld.long 0x78 1. "DMEIE,DMEIE" "0,1" bitfld.long 0x78 0. "EN,EN" "0,1" line.long 0x7C "DMA_S5NDTR,DMA stream 5 number of data register" hexmask.long.word 0x7C 0.--15. 1. "NDT,NDT" line.long 0x80 "DMA_S5PAR,DMA stream 5 peripheral address register" hexmask.long 0x80 0.--31. 1. "PAR,PAR" line.long 0x84 "DMA_S5M0AR,DMA stream 5 memory 0 address register" hexmask.long 0x84 0.--31. 1. "M0A,M0A" line.long 0x88 "DMA_S5M1AR,DMA stream 5 memory 1 address register" hexmask.long 0x88 0.--31. 1. "M1A,M1A" line.long 0x8C "DMA_S5FCR,DMA stream 5 FIFO control register" bitfld.long 0x8C 7. "FEIE,FEIE" "0,1" rbitfld.long 0x8C 3.--5. "FS,FS" "0,1,2,3,4,5,6,7" bitfld.long 0x8C 2. "DMDIS,DMDIS" "0,1" bitfld.long 0x8C 0.--1. "FTH,FTH" "0,1,2,3" line.long 0x90 "DMA_S6CR,This register is used to configure the concerned stream." bitfld.long 0x90 23.--24. "MBURST,MBURST" "0,1,2,3" bitfld.long 0x90 21.--22. "PBURST,PBURST" "0,1,2,3" bitfld.long 0x90 19. "CT,CT" "0,1" bitfld.long 0x90 18. "DBM,DBM" "0,1" bitfld.long 0x90 16.--17. "PL,PL" "0,1,2,3" bitfld.long 0x90 15. "PINCOS,PINCOS" "0,1" newline bitfld.long 0x90 13.--14. "MSIZE,MSIZE" "0,1,2,3" bitfld.long 0x90 11.--12. "PSIZE,PSIZE" "0,1,2,3" bitfld.long 0x90 10. "MINC,MINC" "0,1" bitfld.long 0x90 9. "PINC,PINC" "0,1" bitfld.long 0x90 8. "CIRC,CIRC" "0,1" bitfld.long 0x90 6.--7. "DIR,DIR" "0,1,2,3" newline bitfld.long 0x90 5. "PFCTRL,PFCTRL" "0,1" bitfld.long 0x90 4. "TCIE,TCIE" "0,1" bitfld.long 0x90 3. "HTIE,HTIE" "0,1" bitfld.long 0x90 2. "TEIE,TEIE" "0,1" bitfld.long 0x90 1. "DMEIE,DMEIE" "0,1" bitfld.long 0x90 0. "EN,EN" "0,1" line.long 0x94 "DMA_S6NDTR,DMA stream 6 number of data register" hexmask.long.word 0x94 0.--15. 1. "NDT,NDT" line.long 0x98 "DMA_S6PAR,DMA stream 6 peripheral address register" hexmask.long 0x98 0.--31. 1. "PAR,PAR" line.long 0x9C "DMA_S6M0AR,DMA stream 6 memory 0 address register" hexmask.long 0x9C 0.--31. 1. "M0A,M0A" line.long 0xA0 "DMA_S6M1AR,DMA stream 6 memory 1 address register" hexmask.long 0xA0 0.--31. 1. "M1A,M1A" line.long 0xA4 "DMA_S6FCR,DMA stream 6 FIFO control register" bitfld.long 0xA4 7. "FEIE,FEIE" "0,1" rbitfld.long 0xA4 3.--5. "FS,FS" "0,1,2,3,4,5,6,7" bitfld.long 0xA4 2. "DMDIS,DMDIS" "0,1" bitfld.long 0xA4 0.--1. "FTH,FTH" "0,1,2,3" line.long 0xA8 "DMA_S7CR,This register is used to configure the concerned stream." bitfld.long 0xA8 23.--24. "MBURST,MBURST" "0,1,2,3" bitfld.long 0xA8 21.--22. "PBURST,PBURST" "0,1,2,3" bitfld.long 0xA8 19. "CT,CT" "0,1" bitfld.long 0xA8 18. "DBM,DBM" "0,1" bitfld.long 0xA8 16.--17. "PL,PL" "0,1,2,3" bitfld.long 0xA8 15. "PINCOS,PINCOS" "0,1" newline bitfld.long 0xA8 13.--14. "MSIZE,MSIZE" "0,1,2,3" bitfld.long 0xA8 11.--12. "PSIZE,PSIZE" "0,1,2,3" bitfld.long 0xA8 10. "MINC,MINC" "0,1" bitfld.long 0xA8 9. "PINC,PINC" "0,1" bitfld.long 0xA8 8. "CIRC,CIRC" "0,1" bitfld.long 0xA8 6.--7. "DIR,DIR" "0,1,2,3" newline bitfld.long 0xA8 5. "PFCTRL,PFCTRL" "0,1" bitfld.long 0xA8 4. "TCIE,TCIE" "0,1" bitfld.long 0xA8 3. "HTIE,HTIE" "0,1" bitfld.long 0xA8 2. "TEIE,TEIE" "0,1" bitfld.long 0xA8 1. "DMEIE,DMEIE" "0,1" bitfld.long 0xA8 0. "EN,EN" "0,1" line.long 0xAC "DMA_S7NDTR,DMA stream 7 number of data register" hexmask.long.word 0xAC 0.--15. 1. "NDT,NDT" line.long 0xB0 "DMA_S7PAR,DMA stream 7 peripheral address register" hexmask.long 0xB0 0.--31. 1. "PAR,PAR" line.long 0xB4 "DMA_S7M0AR,DMA stream 7 memory 0 address register" hexmask.long 0xB4 0.--31. 1. "M0A,M0A" line.long 0xB8 "DMA_S7M1AR,DMA stream 7 memory 1 address register" hexmask.long 0xB8 0.--31. 1. "M1A,M1A" line.long 0xBC "DMA_S7FCR,DMA stream 7 FIFO control register" bitfld.long 0xBC 7. "FEIE,FEIE" "0,1" rbitfld.long 0xBC 3.--5. "FS,FS" "0,1,2,3,4,5,6,7" bitfld.long 0xBC 2. "DMDIS,DMDIS" "0,1" bitfld.long 0xBC 0.--1. "FTH,FTH" "0,1,2,3" rgroup.long 0x3EC++0x13 line.long 0x0 "DMA_HWCFGR2,DMA hardware configuration 2register" bitfld.long 0x0 8.--10. "CHSEL_WIDTH,CHSEL_WIDTH" "0,1,2,3,4,5,6,7" bitfld.long 0x0 4. "WRITE_BUFFERABLE,WRITE_BUFFERABLE" "0,1" bitfld.long 0x0 0.--1. "FIFO_SIZE,FIFO_SIZE" "0,1,2,3" line.long 0x4 "DMA_HWCFGR1,DMA hardware configuration 1 register" bitfld.long 0x4 28.--29. "DMA_DEF7,DMA_DEF7" "0,1,2,3" bitfld.long 0x4 24.--25. "DMA_DEF6,DMA_DEF6" "0,1,2,3" bitfld.long 0x4 20.--21. "DMA_DEF5,DMA_DEF5" "0,1,2,3" bitfld.long 0x4 16.--17. "DMA_DEF4,DMA_DEF4" "0,1,2,3" bitfld.long 0x4 12.--13. "DMA_DEF3,DMA_DEF3" "0,1,2,3" bitfld.long 0x4 8.--9. "DMA_DEF2,DMA_DEF2" "0,1,2,3" newline bitfld.long 0x4 4.--5. "DMA_DEF1,DMA_DEF1" "0,1,2,3" bitfld.long 0x4 0.--1. "DMA_DEF0,DMA_DEF0" "0,1,2,3" line.long 0x8 "DMA_VERR,This register identifies the version of the IP." hexmask.long.byte 0x8 4.--7. 1. "MAJREV,MAJREV" hexmask.long.byte 0x8 0.--3. 1. "MINREV,MINREV" line.long 0xC "DMA_IPDR,DMA IP identification register" hexmask.long 0xC 0.--31. 1. "ID,ID" line.long 0x10 "DMA_SIDR,DMA size identification register" hexmask.long 0x10 0.--31. 1. "SID,SID" tree.end endif sif (cpuis("STM32MP151*")||cpuis("STM32MP153*")||cpuis("STM32MP157*")) tree "DMA2" base ad:0x48001000 rgroup.long 0x0++0x7 line.long 0x0 "DMA_LISR,DMA low interrupt status register" bitfld.long 0x0 27. "TCIF3,TCIF3" "0,1" bitfld.long 0x0 26. "HTIF3,HTIF3" "0,1" bitfld.long 0x0 25. "TEIF3,TEIF3" "0,1" bitfld.long 0x0 24. "DMEIF3,DMEIF3" "0,1" bitfld.long 0x0 22. "FEIF3,FEIF3" "0,1" bitfld.long 0x0 21. "TCIF2,TCIF2" "0,1" newline bitfld.long 0x0 20. "HTIF2,HTIF2" "0,1" bitfld.long 0x0 19. "TEIF2,TEIF2" "0,1" bitfld.long 0x0 18. "DMEIF2,DMEIF2" "0,1" bitfld.long 0x0 16. "FEIF2,FEIF2" "0,1" bitfld.long 0x0 11. "TCIF1,TCIF1" "0,1" bitfld.long 0x0 10. "HTIF1,HTIF1" "0,1" newline bitfld.long 0x0 9. "TEIF1,TEIF1" "0,1" bitfld.long 0x0 8. "DMEIF1,DMEIF1" "0,1" bitfld.long 0x0 6. "FEIF1,FEIF1" "0,1" bitfld.long 0x0 5. "TCIF0,TCIF0" "0,1" bitfld.long 0x0 4. "HTIF0,HTIF0" "0,1" bitfld.long 0x0 3. "TEIF0,TEIF0" "0,1" newline bitfld.long 0x0 2. "DMEIF0,DMEIF0" "0,1" bitfld.long 0x0 0. "FEIF0,FEIF0" "0,1" line.long 0x4 "DMA_HISR,DMA high interrupt status register" bitfld.long 0x4 27. "TCIF7,TCIF7" "0,1" bitfld.long 0x4 26. "HTIF7,HTIF7" "0,1" bitfld.long 0x4 25. "TEIF7,TEIF7" "0,1" bitfld.long 0x4 24. "DMEIF7,DMEIF7" "0,1" bitfld.long 0x4 22. "FEIF7,FEIF7" "0,1" bitfld.long 0x4 21. "TCIF6,TCIF6" "0,1" newline bitfld.long 0x4 20. "HTIF6,HTIF6" "0,1" bitfld.long 0x4 19. "TEIF6,TEIF6" "0,1" bitfld.long 0x4 18. "DMEIF6,DMEIF6" "0,1" bitfld.long 0x4 16. "FEIF6,FEIF6" "0,1" bitfld.long 0x4 11. "TCIF5,TCIF5" "0,1" bitfld.long 0x4 10. "HTIF5,HTIF5" "0,1" newline bitfld.long 0x4 9. "TEIF5,TEIF5" "0,1" bitfld.long 0x4 8. "DMEIF5,DMEIF5" "0,1" bitfld.long 0x4 6. "FEIF5,FEIF5" "0,1" bitfld.long 0x4 5. "TCIF4,TCIF4" "0,1" bitfld.long 0x4 4. "HTIF4,HTIF4" "0,1" bitfld.long 0x4 3. "TEIF4,TEIF4" "0,1" newline bitfld.long 0x4 2. "DMEIF4,DMEIF4" "0,1" bitfld.long 0x4 0. "FEIF4,FEIF4" "0,1" wgroup.long 0x8++0x7 line.long 0x0 "DMA_LIFCR,DMA low interrupt flag clear register" bitfld.long 0x0 27. "CTCIF3,CTCIF3" "0,1" bitfld.long 0x0 26. "CHTIF3,CHTIF3" "0,1" bitfld.long 0x0 25. "CTEIF3,CTEIF3" "0,1" bitfld.long 0x0 24. "CDMEIF3,CDMEIF3" "0,1" bitfld.long 0x0 22. "CFEIF3,CFEIF3" "0,1" bitfld.long 0x0 21. "CTCIF2,CTCIF2" "0,1" newline bitfld.long 0x0 20. "CHTIF2,CHTIF2" "0,1" bitfld.long 0x0 19. "CTEIF2,CTEIF2" "0,1" bitfld.long 0x0 18. "CDMEIF2,CDMEIF2" "0,1" bitfld.long 0x0 16. "CFEIF2,CFEIF2" "0,1" bitfld.long 0x0 11. "CTCIF1,CTCIF1" "0,1" bitfld.long 0x0 10. "CHTIF1,CHTIF1" "0,1" newline bitfld.long 0x0 9. "CTEIF1,CTEIF1" "0,1" bitfld.long 0x0 8. "CDMEIF1,CDMEIF1" "0,1" bitfld.long 0x0 6. "CFEIF1,CFEIF1" "0,1" bitfld.long 0x0 5. "CTCIF0,CTCIF0" "0,1" bitfld.long 0x0 4. "CHTIF0,CHTIF0" "0,1" bitfld.long 0x0 3. "CTEIF0,CTEIF0" "0,1" newline bitfld.long 0x0 2. "CDMEIF0,CDMEIF0" "0,1" bitfld.long 0x0 0. "CFEIF0,CFEIF0" "0,1" line.long 0x4 "DMA_HIFCR,DMA high interrupt flag clear register" bitfld.long 0x4 27. "CTCIF7,CTCIF7" "0,1" bitfld.long 0x4 26. "CHTIF7,CHTIF7" "0,1" bitfld.long 0x4 25. "CTEIF7,CTEIF7" "0,1" bitfld.long 0x4 24. "CDMEIF7,CDMEIF7" "0,1" bitfld.long 0x4 22. "CFEIF7,CFEIF7" "0,1" bitfld.long 0x4 21. "CTCIF6,CTCIF6" "0,1" newline bitfld.long 0x4 20. "CHTIF6,CHTIF6" "0,1" bitfld.long 0x4 19. "CTEIF6,CTEIF6" "0,1" bitfld.long 0x4 18. "CDMEIF6,CDMEIF6" "0,1" bitfld.long 0x4 16. "CFEIF6,CFEIF6" "0,1" bitfld.long 0x4 11. "CTCIF5,CTCIF5" "0,1" bitfld.long 0x4 10. "CHTIF5,CHTIF5" "0,1" newline bitfld.long 0x4 9. "CTEIF5,CTEIF5" "0,1" bitfld.long 0x4 8. "CDMEIF5,CDMEIF5" "0,1" bitfld.long 0x4 6. "CFEIF5,CFEIF5" "0,1" bitfld.long 0x4 5. "CTCIF4,CTCIF4" "0,1" bitfld.long 0x4 4. "CHTIF4,CHTIF4" "0,1" bitfld.long 0x4 3. "CTEIF4,CTEIF4" "0,1" newline bitfld.long 0x4 2. "CDMEIF4,CDMEIF4" "0,1" bitfld.long 0x4 0. "CFEIF4,CFEIF4" "0,1" group.long 0x10++0xBF line.long 0x0 "DMA_S0CR,This register is used to configure the concerned stream." bitfld.long 0x0 23.--24. "MBURST,MBURST" "0,1,2,3" bitfld.long 0x0 21.--22. "PBURST,PBURST" "0,1,2,3" bitfld.long 0x0 19. "CT,CT" "0,1" bitfld.long 0x0 18. "DBM,DBM" "0,1" bitfld.long 0x0 16.--17. "PL,PL" "0,1,2,3" bitfld.long 0x0 15. "PINCOS,PINCOS" "0,1" newline bitfld.long 0x0 13.--14. "MSIZE,MSIZE" "0,1,2,3" bitfld.long 0x0 11.--12. "PSIZE,PSIZE" "0,1,2,3" bitfld.long 0x0 10. "MINC,MINC" "0,1" bitfld.long 0x0 9. "PINC,PINC" "0,1" bitfld.long 0x0 8. "CIRC,CIRC" "0,1" bitfld.long 0x0 6.--7. "DIR,DIR" "0,1,2,3" newline bitfld.long 0x0 5. "PFCTRL,PFCTRL" "0,1" bitfld.long 0x0 4. "TCIE,TCIE" "0,1" bitfld.long 0x0 3. "HTIE,HTIE" "0,1" bitfld.long 0x0 2. "TEIE,TEIE" "0,1" bitfld.long 0x0 1. "DMEIE,DMEIE" "0,1" bitfld.long 0x0 0. "EN,EN" "0,1" line.long 0x4 "DMA_S0NDTR,DMA stream 0 number of data register" hexmask.long.word 0x4 0.--15. 1. "NDT,NDT" line.long 0x8 "DMA_S0PAR,DMA stream 0 peripheral address register" hexmask.long 0x8 0.--31. 1. "PAR,PAR" line.long 0xC "DMA_S0M0AR,DMA stream 0 memory 0 address register" hexmask.long 0xC 0.--31. 1. "M0A,M0A" line.long 0x10 "DMA_S0M1AR,DMA stream 0 memory 1 address register" hexmask.long 0x10 0.--31. 1. "M1A,M1A" line.long 0x14 "DMA_S0FCR,DMA stream 0 FIFO control register" bitfld.long 0x14 7. "FEIE,FEIE" "0,1" rbitfld.long 0x14 3.--5. "FS,FS" "0,1,2,3,4,5,6,7" bitfld.long 0x14 2. "DMDIS,DMDIS" "0,1" bitfld.long 0x14 0.--1. "FTH,FTH" "0,1,2,3" line.long 0x18 "DMA_S1CR,This register is used to configure the concerned stream." bitfld.long 0x18 23.--24. "MBURST,MBURST" "0,1,2,3" bitfld.long 0x18 21.--22. "PBURST,PBURST" "0,1,2,3" bitfld.long 0x18 19. "CT,CT" "0,1" bitfld.long 0x18 18. "DBM,DBM" "0,1" bitfld.long 0x18 16.--17. "PL,PL" "0,1,2,3" bitfld.long 0x18 15. "PINCOS,PINCOS" "0,1" newline bitfld.long 0x18 13.--14. "MSIZE,MSIZE" "0,1,2,3" bitfld.long 0x18 11.--12. "PSIZE,PSIZE" "0,1,2,3" bitfld.long 0x18 10. "MINC,MINC" "0,1" bitfld.long 0x18 9. "PINC,PINC" "0,1" bitfld.long 0x18 8. "CIRC,CIRC" "0,1" bitfld.long 0x18 6.--7. "DIR,DIR" "0,1,2,3" newline bitfld.long 0x18 5. "PFCTRL,PFCTRL" "0,1" bitfld.long 0x18 4. "TCIE,TCIE" "0,1" bitfld.long 0x18 3. "HTIE,HTIE" "0,1" bitfld.long 0x18 2. "TEIE,TEIE" "0,1" bitfld.long 0x18 1. "DMEIE,DMEIE" "0,1" bitfld.long 0x18 0. "EN,EN" "0,1" line.long 0x1C "DMA_S1NDTR,DMA stream 1 number of data register" hexmask.long.word 0x1C 0.--15. 1. "NDT,NDT" line.long 0x20 "DMA_S1PAR,DMA stream 1 peripheral address register" hexmask.long 0x20 0.--31. 1. "PAR,PAR" line.long 0x24 "DMA_S1M0AR,DMA stream 1 memory 0 address register" hexmask.long 0x24 0.--31. 1. "M0A,M0A" line.long 0x28 "DMA_S1M1AR,DMA stream 1 memory 1 address register" hexmask.long 0x28 0.--31. 1. "M1A,M1A" line.long 0x2C "DMA_S1FCR,DMA stream 1 FIFO control register" bitfld.long 0x2C 7. "FEIE,FEIE" "0,1" rbitfld.long 0x2C 3.--5. "FS,FS" "0,1,2,3,4,5,6,7" bitfld.long 0x2C 2. "DMDIS,DMDIS" "0,1" bitfld.long 0x2C 0.--1. "FTH,FTH" "0,1,2,3" line.long 0x30 "DMA_S2CR,This register is used to configure the concerned stream." bitfld.long 0x30 23.--24. "MBURST,MBURST" "0,1,2,3" bitfld.long 0x30 21.--22. "PBURST,PBURST" "0,1,2,3" bitfld.long 0x30 19. "CT,CT" "0,1" bitfld.long 0x30 18. "DBM,DBM" "0,1" bitfld.long 0x30 16.--17. "PL,PL" "0,1,2,3" bitfld.long 0x30 15. "PINCOS,PINCOS" "0,1" newline bitfld.long 0x30 13.--14. "MSIZE,MSIZE" "0,1,2,3" bitfld.long 0x30 11.--12. "PSIZE,PSIZE" "0,1,2,3" bitfld.long 0x30 10. "MINC,MINC" "0,1" bitfld.long 0x30 9. "PINC,PINC" "0,1" bitfld.long 0x30 8. "CIRC,CIRC" "0,1" bitfld.long 0x30 6.--7. "DIR,DIR" "0,1,2,3" newline bitfld.long 0x30 5. "PFCTRL,PFCTRL" "0,1" bitfld.long 0x30 4. "TCIE,TCIE" "0,1" bitfld.long 0x30 3. "HTIE,HTIE" "0,1" bitfld.long 0x30 2. "TEIE,TEIE" "0,1" bitfld.long 0x30 1. "DMEIE,DMEIE" "0,1" bitfld.long 0x30 0. "EN,EN" "0,1" line.long 0x34 "DMA_S2NDTR,DMA stream 2 number of data register" hexmask.long.word 0x34 0.--15. 1. "NDT,NDT" line.long 0x38 "DMA_S2PAR,DMA stream 2 peripheral address register" hexmask.long 0x38 0.--31. 1. "PAR,PAR" line.long 0x3C "DMA_S2M0AR,DMA stream 2 memory 0 address register" hexmask.long 0x3C 0.--31. 1. "M0A,M0A" line.long 0x40 "DMA_S2M1AR,DMA stream 2 memory 1 address register" hexmask.long 0x40 0.--31. 1. "M1A,M1A" line.long 0x44 "DMA_S2FCR,DMA stream 2 FIFO control register" bitfld.long 0x44 7. "FEIE,FEIE" "0,1" rbitfld.long 0x44 3.--5. "FS,FS" "0,1,2,3,4,5,6,7" bitfld.long 0x44 2. "DMDIS,DMDIS" "0,1" bitfld.long 0x44 0.--1. "FTH,FTH" "0,1,2,3" line.long 0x48 "DMA_S3CR,This register is used to configure the concerned stream." bitfld.long 0x48 23.--24. "MBURST,MBURST" "0,1,2,3" bitfld.long 0x48 21.--22. "PBURST,PBURST" "0,1,2,3" bitfld.long 0x48 19. "CT,CT" "0,1" bitfld.long 0x48 18. "DBM,DBM" "0,1" bitfld.long 0x48 16.--17. "PL,PL" "0,1,2,3" bitfld.long 0x48 15. "PINCOS,PINCOS" "0,1" newline bitfld.long 0x48 13.--14. "MSIZE,MSIZE" "0,1,2,3" bitfld.long 0x48 11.--12. "PSIZE,PSIZE" "0,1,2,3" bitfld.long 0x48 10. "MINC,MINC" "0,1" bitfld.long 0x48 9. "PINC,PINC" "0,1" bitfld.long 0x48 8. "CIRC,CIRC" "0,1" bitfld.long 0x48 6.--7. "DIR,DIR" "0,1,2,3" newline bitfld.long 0x48 5. "PFCTRL,PFCTRL" "0,1" bitfld.long 0x48 4. "TCIE,TCIE" "0,1" bitfld.long 0x48 3. "HTIE,HTIE" "0,1" bitfld.long 0x48 2. "TEIE,TEIE" "0,1" bitfld.long 0x48 1. "DMEIE,DMEIE" "0,1" bitfld.long 0x48 0. "EN,EN" "0,1" line.long 0x4C "DMA_S3NDTR,DMA stream 3 number of data register" hexmask.long.word 0x4C 0.--15. 1. "NDT,NDT" line.long 0x50 "DMA_S3PAR,DMA stream 3 peripheral address register" hexmask.long 0x50 0.--31. 1. "PAR,PAR" line.long 0x54 "DMA_S3M0AR,DMA stream 3 memory 0 address register" hexmask.long 0x54 0.--31. 1. "M0A,M0A" line.long 0x58 "DMA_S3M1AR,DMA stream 3 memory 1 address register" hexmask.long 0x58 0.--31. 1. "M1A,M1A" line.long 0x5C "DMA_S3FCR,DMA stream 3 FIFO control register" bitfld.long 0x5C 7. "FEIE,FEIE" "0,1" rbitfld.long 0x5C 3.--5. "FS,FS" "0,1,2,3,4,5,6,7" bitfld.long 0x5C 2. "DMDIS,DMDIS" "0,1" bitfld.long 0x5C 0.--1. "FTH,FTH" "0,1,2,3" line.long 0x60 "DMA_S4CR,This register is used to configure the concerned stream." bitfld.long 0x60 23.--24. "MBURST,MBURST" "0,1,2,3" bitfld.long 0x60 21.--22. "PBURST,PBURST" "0,1,2,3" bitfld.long 0x60 19. "CT,CT" "0,1" bitfld.long 0x60 18. "DBM,DBM" "0,1" bitfld.long 0x60 16.--17. "PL,PL" "0,1,2,3" bitfld.long 0x60 15. "PINCOS,PINCOS" "0,1" newline bitfld.long 0x60 13.--14. "MSIZE,MSIZE" "0,1,2,3" bitfld.long 0x60 11.--12. "PSIZE,PSIZE" "0,1,2,3" bitfld.long 0x60 10. "MINC,MINC" "0,1" bitfld.long 0x60 9. "PINC,PINC" "0,1" bitfld.long 0x60 8. "CIRC,CIRC" "0,1" bitfld.long 0x60 6.--7. "DIR,DIR" "0,1,2,3" newline bitfld.long 0x60 5. "PFCTRL,PFCTRL" "0,1" bitfld.long 0x60 4. "TCIE,TCIE" "0,1" bitfld.long 0x60 3. "HTIE,HTIE" "0,1" bitfld.long 0x60 2. "TEIE,TEIE" "0,1" bitfld.long 0x60 1. "DMEIE,DMEIE" "0,1" bitfld.long 0x60 0. "EN,EN" "0,1" line.long 0x64 "DMA_S4NDTR,DMA stream 4 number of data register" hexmask.long.word 0x64 0.--15. 1. "NDT,NDT" line.long 0x68 "DMA_S4PAR,DMA stream 4 peripheral address register" hexmask.long 0x68 0.--31. 1. "PAR,PAR" line.long 0x6C "DMA_S4M0AR,DMA stream 4 memory 0 address register" hexmask.long 0x6C 0.--31. 1. "M0A,M0A" line.long 0x70 "DMA_S4M1AR,DMA stream 4 memory 1 address register" hexmask.long 0x70 0.--31. 1. "M1A,M1A" line.long 0x74 "DMA_S4FCR,DMA stream 4 FIFO control register" bitfld.long 0x74 7. "FEIE,FEIE" "0,1" rbitfld.long 0x74 3.--5. "FS,FS" "0,1,2,3,4,5,6,7" bitfld.long 0x74 2. "DMDIS,DMDIS" "0,1" bitfld.long 0x74 0.--1. "FTH,FTH" "0,1,2,3" line.long 0x78 "DMA_S5CR,This register is used to configure the concerned stream." bitfld.long 0x78 23.--24. "MBURST,MBURST" "0,1,2,3" bitfld.long 0x78 21.--22. "PBURST,PBURST" "0,1,2,3" bitfld.long 0x78 19. "CT,CT" "0,1" bitfld.long 0x78 18. "DBM,DBM" "0,1" bitfld.long 0x78 16.--17. "PL,PL" "0,1,2,3" bitfld.long 0x78 15. "PINCOS,PINCOS" "0,1" newline bitfld.long 0x78 13.--14. "MSIZE,MSIZE" "0,1,2,3" bitfld.long 0x78 11.--12. "PSIZE,PSIZE" "0,1,2,3" bitfld.long 0x78 10. "MINC,MINC" "0,1" bitfld.long 0x78 9. "PINC,PINC" "0,1" bitfld.long 0x78 8. "CIRC,CIRC" "0,1" bitfld.long 0x78 6.--7. "DIR,DIR" "0,1,2,3" newline bitfld.long 0x78 5. "PFCTRL,PFCTRL" "0,1" bitfld.long 0x78 4. "TCIE,TCIE" "0,1" bitfld.long 0x78 3. "HTIE,HTIE" "0,1" bitfld.long 0x78 2. "TEIE,TEIE" "0,1" bitfld.long 0x78 1. "DMEIE,DMEIE" "0,1" bitfld.long 0x78 0. "EN,EN" "0,1" line.long 0x7C "DMA_S5NDTR,DMA stream 5 number of data register" hexmask.long.word 0x7C 0.--15. 1. "NDT,NDT" line.long 0x80 "DMA_S5PAR,DMA stream 5 peripheral address register" hexmask.long 0x80 0.--31. 1. "PAR,PAR" line.long 0x84 "DMA_S5M0AR,DMA stream 5 memory 0 address register" hexmask.long 0x84 0.--31. 1. "M0A,M0A" line.long 0x88 "DMA_S5M1AR,DMA stream 5 memory 1 address register" hexmask.long 0x88 0.--31. 1. "M1A,M1A" line.long 0x8C "DMA_S5FCR,DMA stream 5 FIFO control register" bitfld.long 0x8C 7. "FEIE,FEIE" "0,1" rbitfld.long 0x8C 3.--5. "FS,FS" "0,1,2,3,4,5,6,7" bitfld.long 0x8C 2. "DMDIS,DMDIS" "0,1" bitfld.long 0x8C 0.--1. "FTH,FTH" "0,1,2,3" line.long 0x90 "DMA_S6CR,This register is used to configure the concerned stream." bitfld.long 0x90 23.--24. "MBURST,MBURST" "0,1,2,3" bitfld.long 0x90 21.--22. "PBURST,PBURST" "0,1,2,3" bitfld.long 0x90 19. "CT,CT" "0,1" bitfld.long 0x90 18. "DBM,DBM" "0,1" bitfld.long 0x90 16.--17. "PL,PL" "0,1,2,3" bitfld.long 0x90 15. "PINCOS,PINCOS" "0,1" newline bitfld.long 0x90 13.--14. "MSIZE,MSIZE" "0,1,2,3" bitfld.long 0x90 11.--12. "PSIZE,PSIZE" "0,1,2,3" bitfld.long 0x90 10. "MINC,MINC" "0,1" bitfld.long 0x90 9. "PINC,PINC" "0,1" bitfld.long 0x90 8. "CIRC,CIRC" "0,1" bitfld.long 0x90 6.--7. "DIR,DIR" "0,1,2,3" newline bitfld.long 0x90 5. "PFCTRL,PFCTRL" "0,1" bitfld.long 0x90 4. "TCIE,TCIE" "0,1" bitfld.long 0x90 3. "HTIE,HTIE" "0,1" bitfld.long 0x90 2. "TEIE,TEIE" "0,1" bitfld.long 0x90 1. "DMEIE,DMEIE" "0,1" bitfld.long 0x90 0. "EN,EN" "0,1" line.long 0x94 "DMA_S6NDTR,DMA stream 6 number of data register" hexmask.long.word 0x94 0.--15. 1. "NDT,NDT" line.long 0x98 "DMA_S6PAR,DMA stream 6 peripheral address register" hexmask.long 0x98 0.--31. 1. "PAR,PAR" line.long 0x9C "DMA_S6M0AR,DMA stream 6 memory 0 address register" hexmask.long 0x9C 0.--31. 1. "M0A,M0A" line.long 0xA0 "DMA_S6M1AR,DMA stream 6 memory 1 address register" hexmask.long 0xA0 0.--31. 1. "M1A,M1A" line.long 0xA4 "DMA_S6FCR,DMA stream 6 FIFO control register" bitfld.long 0xA4 7. "FEIE,FEIE" "0,1" rbitfld.long 0xA4 3.--5. "FS,FS" "0,1,2,3,4,5,6,7" bitfld.long 0xA4 2. "DMDIS,DMDIS" "0,1" bitfld.long 0xA4 0.--1. "FTH,FTH" "0,1,2,3" line.long 0xA8 "DMA_S7CR,This register is used to configure the concerned stream." bitfld.long 0xA8 23.--24. "MBURST,MBURST" "0,1,2,3" bitfld.long 0xA8 21.--22. "PBURST,PBURST" "0,1,2,3" bitfld.long 0xA8 19. "CT,CT" "0,1" bitfld.long 0xA8 18. "DBM,DBM" "0,1" bitfld.long 0xA8 16.--17. "PL,PL" "0,1,2,3" bitfld.long 0xA8 15. "PINCOS,PINCOS" "0,1" newline bitfld.long 0xA8 13.--14. "MSIZE,MSIZE" "0,1,2,3" bitfld.long 0xA8 11.--12. "PSIZE,PSIZE" "0,1,2,3" bitfld.long 0xA8 10. "MINC,MINC" "0,1" bitfld.long 0xA8 9. "PINC,PINC" "0,1" bitfld.long 0xA8 8. "CIRC,CIRC" "0,1" bitfld.long 0xA8 6.--7. "DIR,DIR" "0,1,2,3" newline bitfld.long 0xA8 5. "PFCTRL,PFCTRL" "0,1" bitfld.long 0xA8 4. "TCIE,TCIE" "0,1" bitfld.long 0xA8 3. "HTIE,HTIE" "0,1" bitfld.long 0xA8 2. "TEIE,TEIE" "0,1" bitfld.long 0xA8 1. "DMEIE,DMEIE" "0,1" bitfld.long 0xA8 0. "EN,EN" "0,1" line.long 0xAC "DMA_S7NDTR,DMA stream 7 number of data register" hexmask.long.word 0xAC 0.--15. 1. "NDT,NDT" line.long 0xB0 "DMA_S7PAR,DMA stream 7 peripheral address register" hexmask.long 0xB0 0.--31. 1. "PAR,PAR" line.long 0xB4 "DMA_S7M0AR,DMA stream 7 memory 0 address register" hexmask.long 0xB4 0.--31. 1. "M0A,M0A" line.long 0xB8 "DMA_S7M1AR,DMA stream 7 memory 1 address register" hexmask.long 0xB8 0.--31. 1. "M1A,M1A" line.long 0xBC "DMA_S7FCR,DMA stream 7 FIFO control register" bitfld.long 0xBC 7. "FEIE,FEIE" "0,1" rbitfld.long 0xBC 3.--5. "FS,FS" "0,1,2,3,4,5,6,7" bitfld.long 0xBC 2. "DMDIS,DMDIS" "0,1" bitfld.long 0xBC 0.--1. "FTH,FTH" "0,1,2,3" rgroup.long 0x3EC++0x13 line.long 0x0 "DMA_HWCFGR2,DMA hardware configuration 2register" bitfld.long 0x0 8.--10. "CHSEL_WIDTH,CHSEL_WIDTH" "0,1,2,3,4,5,6,7" bitfld.long 0x0 4. "WRITE_BUFFERABLE,WRITE_BUFFERABLE" "0,1" bitfld.long 0x0 0.--1. "FIFO_SIZE,FIFO_SIZE" "0,1,2,3" line.long 0x4 "DMA_HWCFGR1,DMA hardware configuration 1 register" bitfld.long 0x4 28.--29. "DMA_DEF7,DMA_DEF7" "0,1,2,3" bitfld.long 0x4 24.--25. "DMA_DEF6,DMA_DEF6" "0,1,2,3" bitfld.long 0x4 20.--21. "DMA_DEF5,DMA_DEF5" "0,1,2,3" bitfld.long 0x4 16.--17. "DMA_DEF4,DMA_DEF4" "0,1,2,3" bitfld.long 0x4 12.--13. "DMA_DEF3,DMA_DEF3" "0,1,2,3" bitfld.long 0x4 8.--9. "DMA_DEF2,DMA_DEF2" "0,1,2,3" newline bitfld.long 0x4 4.--5. "DMA_DEF1,DMA_DEF1" "0,1,2,3" bitfld.long 0x4 0.--1. "DMA_DEF0,DMA_DEF0" "0,1,2,3" line.long 0x8 "DMA_VERR,This register identifies the version of the IP." hexmask.long.byte 0x8 4.--7. 1. "MAJREV,MAJREV" hexmask.long.byte 0x8 0.--3. 1. "MINREV,MINREV" line.long 0xC "DMA_IPDR,DMA IP identification register" hexmask.long 0xC 0.--31. 1. "ID,ID" line.long 0x10 "DMA_SIDR,DMA size identification register" hexmask.long 0x10 0.--31. 1. "SID,SID" tree.end endif tree.end tree "DMAMUX (DMA Request Multiplexer)" base ad:0x0 tree "DMAMUX1" base ad:0x48002000 group.long 0x0++0x3F line.long 0x0 "DMAMUX_C0CR,DMAMUX request line multiplexer channel 0 configuration register" bitfld.long 0x0 24.--26. "SYNC_ID,SYNC_ID" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 19.--23. 1. "NBREQ,NBREQ" bitfld.long 0x0 17.--18. "SPOL,SPOL" "0,1,2,3" bitfld.long 0x0 16. "SE,SE" "0,1" bitfld.long 0x0 9. "EGE,EGE" "0,1" newline bitfld.long 0x0 8. "SOIE,SOIE" "0,1" hexmask.long.byte 0x0 0.--6. 1. "DMAREQ_ID,DMAREQ_ID" line.long 0x4 "DMAMUX_C1CR,DMAMUX request line multiplexer channel 1 configuration register" bitfld.long 0x4 24.--26. "SYNC_ID,SYNC_ID" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 19.--23. 1. "NBREQ,NBREQ" bitfld.long 0x4 17.--18. "SPOL,SPOL" "0,1,2,3" bitfld.long 0x4 16. "SE,SE" "0,1" bitfld.long 0x4 9. "EGE,EGE" "0,1" newline bitfld.long 0x4 8. "SOIE,SOIE" "0,1" hexmask.long.byte 0x4 0.--6. 1. "DMAREQ_ID,DMAREQ_ID" line.long 0x8 "DMAMUX_C2CR,DMAMUX request line multiplexer channel 2 configuration register" bitfld.long 0x8 24.--26. "SYNC_ID,SYNC_ID" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x8 19.--23. 1. "NBREQ,NBREQ" bitfld.long 0x8 17.--18. "SPOL,SPOL" "0,1,2,3" bitfld.long 0x8 16. "SE,SE" "0,1" bitfld.long 0x8 9. "EGE,EGE" "0,1" newline bitfld.long 0x8 8. "SOIE,SOIE" "0,1" hexmask.long.byte 0x8 0.--6. 1. "DMAREQ_ID,DMAREQ_ID" line.long 0xC "DMAMUX_C3CR,DMAMUX request line multiplexer channel 3 configuration register" bitfld.long 0xC 24.--26. "SYNC_ID,SYNC_ID" "0,1,2,3,4,5,6,7" hexmask.long.byte 0xC 19.--23. 1. "NBREQ,NBREQ" bitfld.long 0xC 17.--18. "SPOL,SPOL" "0,1,2,3" bitfld.long 0xC 16. "SE,SE" "0,1" bitfld.long 0xC 9. "EGE,EGE" "0,1" newline bitfld.long 0xC 8. "SOIE,SOIE" "0,1" hexmask.long.byte 0xC 0.--6. 1. "DMAREQ_ID,DMAREQ_ID" line.long 0x10 "DMAMUX_C4CR,DMAMUX request line multiplexer channel 4 configuration register" bitfld.long 0x10 24.--26. "SYNC_ID,SYNC_ID" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x10 19.--23. 1. "NBREQ,NBREQ" bitfld.long 0x10 17.--18. "SPOL,SPOL" "0,1,2,3" bitfld.long 0x10 16. "SE,SE" "0,1" bitfld.long 0x10 9. "EGE,EGE" "0,1" newline bitfld.long 0x10 8. "SOIE,SOIE" "0,1" hexmask.long.byte 0x10 0.--6. 1. "DMAREQ_ID,DMAREQ_ID" line.long 0x14 "DMAMUX_C5CR,DMAMUX request line multiplexer channel 5 configuration register" bitfld.long 0x14 24.--26. "SYNC_ID,SYNC_ID" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x14 19.--23. 1. "NBREQ,NBREQ" bitfld.long 0x14 17.--18. "SPOL,SPOL" "0,1,2,3" bitfld.long 0x14 16. "SE,SE" "0,1" bitfld.long 0x14 9. "EGE,EGE" "0,1" newline bitfld.long 0x14 8. "SOIE,SOIE" "0,1" hexmask.long.byte 0x14 0.--6. 1. "DMAREQ_ID,DMAREQ_ID" line.long 0x18 "DMAMUX_C6CR,DMAMUX request line multiplexer channel 6 configuration register" bitfld.long 0x18 24.--26. "SYNC_ID,SYNC_ID" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x18 19.--23. 1. "NBREQ,NBREQ" bitfld.long 0x18 17.--18. "SPOL,SPOL" "0,1,2,3" bitfld.long 0x18 16. "SE,SE" "0,1" bitfld.long 0x18 9. "EGE,EGE" "0,1" newline bitfld.long 0x18 8. "SOIE,SOIE" "0,1" hexmask.long.byte 0x18 0.--6. 1. "DMAREQ_ID,DMAREQ_ID" line.long 0x1C "DMAMUX_C7CR,DMAMUX request line multiplexer channel 7 configuration register" bitfld.long 0x1C 24.--26. "SYNC_ID,SYNC_ID" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x1C 19.--23. 1. "NBREQ,NBREQ" bitfld.long 0x1C 17.--18. "SPOL,SPOL" "0,1,2,3" bitfld.long 0x1C 16. "SE,SE" "0,1" bitfld.long 0x1C 9. "EGE,EGE" "0,1" newline bitfld.long 0x1C 8. "SOIE,SOIE" "0,1" hexmask.long.byte 0x1C 0.--6. 1. "DMAREQ_ID,DMAREQ_ID" line.long 0x20 "DMAMUX_C8CR,DMAMUX request line multiplexer channel 8 configuration register" bitfld.long 0x20 24.--26. "SYNC_ID,SYNC_ID" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x20 19.--23. 1. "NBREQ,NBREQ" bitfld.long 0x20 17.--18. "SPOL,SPOL" "0,1,2,3" bitfld.long 0x20 16. "SE,SE" "0,1" bitfld.long 0x20 9. "EGE,EGE" "0,1" newline bitfld.long 0x20 8. "SOIE,SOIE" "0,1" hexmask.long.byte 0x20 0.--6. 1. "DMAREQ_ID,DMAREQ_ID" line.long 0x24 "DMAMUX_C9CR,DMAMUX request line multiplexer channel 9 configuration register" bitfld.long 0x24 24.--26. "SYNC_ID,SYNC_ID" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x24 19.--23. 1. "NBREQ,NBREQ" bitfld.long 0x24 17.--18. "SPOL,SPOL" "0,1,2,3" bitfld.long 0x24 16. "SE,SE" "0,1" bitfld.long 0x24 9. "EGE,EGE" "0,1" newline bitfld.long 0x24 8. "SOIE,SOIE" "0,1" hexmask.long.byte 0x24 0.--6. 1. "DMAREQ_ID,DMAREQ_ID" line.long 0x28 "DMAMUX_C10CR,DMAMUX request line multiplexer channel 10 configuration register" bitfld.long 0x28 24.--26. "SYNC_ID,SYNC_ID" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x28 19.--23. 1. "NBREQ,NBREQ" bitfld.long 0x28 17.--18. "SPOL,SPOL" "0,1,2,3" bitfld.long 0x28 16. "SE,SE" "0,1" bitfld.long 0x28 9. "EGE,EGE" "0,1" newline bitfld.long 0x28 8. "SOIE,SOIE" "0,1" hexmask.long.byte 0x28 0.--6. 1. "DMAREQ_ID,DMAREQ_ID" line.long 0x2C "DMAMUX_C11CR,DMAMUX request line multiplexer channel 11 configuration register" bitfld.long 0x2C 24.--26. "SYNC_ID,SYNC_ID" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x2C 19.--23. 1. "NBREQ,NBREQ" bitfld.long 0x2C 17.--18. "SPOL,SPOL" "0,1,2,3" bitfld.long 0x2C 16. "SE,SE" "0,1" bitfld.long 0x2C 9. "EGE,EGE" "0,1" newline bitfld.long 0x2C 8. "SOIE,SOIE" "0,1" hexmask.long.byte 0x2C 0.--6. 1. "DMAREQ_ID,DMAREQ_ID" line.long 0x30 "DMAMUX_C12CR,DMAMUX request line multiplexer channel 12 configuration register" bitfld.long 0x30 24.--26. "SYNC_ID,SYNC_ID" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x30 19.--23. 1. "NBREQ,NBREQ" bitfld.long 0x30 17.--18. "SPOL,SPOL" "0,1,2,3" bitfld.long 0x30 16. "SE,SE" "0,1" bitfld.long 0x30 9. "EGE,EGE" "0,1" newline bitfld.long 0x30 8. "SOIE,SOIE" "0,1" hexmask.long.byte 0x30 0.--6. 1. "DMAREQ_ID,DMAREQ_ID" line.long 0x34 "DMAMUX_C13CR,DMAMUX request line multiplexer channel 13 configuration register" bitfld.long 0x34 24.--26. "SYNC_ID,SYNC_ID" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x34 19.--23. 1. "NBREQ,NBREQ" bitfld.long 0x34 17.--18. "SPOL,SPOL" "0,1,2,3" bitfld.long 0x34 16. "SE,SE" "0,1" bitfld.long 0x34 9. "EGE,EGE" "0,1" newline bitfld.long 0x34 8. "SOIE,SOIE" "0,1" hexmask.long.byte 0x34 0.--6. 1. "DMAREQ_ID,DMAREQ_ID" line.long 0x38 "DMAMUX_C14CR,DMAMUX request line multiplexer channel 14 configuration register" bitfld.long 0x38 24.--26. "SYNC_ID,SYNC_ID" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x38 19.--23. 1. "NBREQ,NBREQ" bitfld.long 0x38 17.--18. "SPOL,SPOL" "0,1,2,3" bitfld.long 0x38 16. "SE,SE" "0,1" bitfld.long 0x38 9. "EGE,EGE" "0,1" newline bitfld.long 0x38 8. "SOIE,SOIE" "0,1" hexmask.long.byte 0x38 0.--6. 1. "DMAREQ_ID,DMAREQ_ID" line.long 0x3C "DMAMUX_C15CR,DMAMUX request line multiplexer channel 15 configuration register" bitfld.long 0x3C 24.--26. "SYNC_ID,SYNC_ID" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x3C 19.--23. 1. "NBREQ,NBREQ" bitfld.long 0x3C 17.--18. "SPOL,SPOL" "0,1,2,3" bitfld.long 0x3C 16. "SE,SE" "0,1" bitfld.long 0x3C 9. "EGE,EGE" "0,1" newline bitfld.long 0x3C 8. "SOIE,SOIE" "0,1" hexmask.long.byte 0x3C 0.--6. 1. "DMAREQ_ID,DMAREQ_ID" rgroup.long 0x80++0x3 line.long 0x0 "DMAMUX_CSR,DMAMUX request line multiplexer interrupt channel status register" bitfld.long 0x0 15. "SOF15,SOF15" "0,1" bitfld.long 0x0 14. "SOF14,SOF14" "0,1" bitfld.long 0x0 13. "SOF13,SOF13" "0,1" bitfld.long 0x0 12. "SOF12,SOF12" "0,1" bitfld.long 0x0 11. "SOF11,SOF11" "0,1" newline bitfld.long 0x0 10. "SOF10,SOF10" "0,1" bitfld.long 0x0 9. "SOF9,SOF9" "0,1" bitfld.long 0x0 8. "SOF8,SOF8" "0,1" bitfld.long 0x0 7. "SOF7,SOF7" "0,1" bitfld.long 0x0 6. "SOF6,SOF6" "0,1" newline bitfld.long 0x0 5. "SOF5,SOF5" "0,1" bitfld.long 0x0 4. "SOF4,SOF4" "0,1" bitfld.long 0x0 3. "SOF3,SOF3" "0,1" bitfld.long 0x0 2. "SOF2,SOF2" "0,1" bitfld.long 0x0 1. "SOF1,SOF1" "0,1" newline bitfld.long 0x0 0. "SOF0,SOF0" "0,1" wgroup.long 0x84++0x3 line.long 0x0 "DMAMUX_CFR,DMAMUX request line multiplexer interrupt clear flag register" bitfld.long 0x0 15. "CSOF15,CSOF15" "0,1" bitfld.long 0x0 14. "CSOF14,CSOF14" "0,1" bitfld.long 0x0 13. "CSOF13,CSOF13" "0,1" bitfld.long 0x0 12. "CSOF12,CSOF12" "0,1" bitfld.long 0x0 11. "CSOF11,CSOF11" "0,1" newline bitfld.long 0x0 10. "CSOF10,CSOF10" "0,1" bitfld.long 0x0 9. "CSOF9,CSOF9" "0,1" bitfld.long 0x0 8. "CSOF8,CSOF8" "0,1" bitfld.long 0x0 7. "CSOF7,CSOF7" "0,1" bitfld.long 0x0 6. "CSOF6,CSOF6" "0,1" newline bitfld.long 0x0 5. "CSOF5,CSOF5" "0,1" bitfld.long 0x0 4. "CSOF4,CSOF4" "0,1" bitfld.long 0x0 3. "CSOF3,CSOF3" "0,1" bitfld.long 0x0 2. "CSOF2,CSOF2" "0,1" bitfld.long 0x0 1. "CSOF1,CSOF1" "0,1" newline bitfld.long 0x0 0. "CSOF0,CSOF0" "0,1" group.long 0x100++0x1F line.long 0x0 "DMAMUX_RG0CR,DMAMUX request generator channel 0 configuration register" hexmask.long.byte 0x0 19.--23. 1. "GNBREQ,GNBREQ" bitfld.long 0x0 17.--18. "GPOL,GPOL" "0,1,2,3" bitfld.long 0x0 16. "GE,GE" "0,1" bitfld.long 0x0 8. "OIE,OIE" "0,1" bitfld.long 0x0 0.--2. "SIG_ID,SIG_ID" "0,1,2,3,4,5,6,7" line.long 0x4 "DMAMUX_RG1CR,DMAMUX request generator channel 1 configuration register" hexmask.long.byte 0x4 19.--23. 1. "GNBREQ,GNBREQ" bitfld.long 0x4 17.--18. "GPOL,GPOL" "0,1,2,3" bitfld.long 0x4 16. "GE,GE" "0,1" bitfld.long 0x4 8. "OIE,OIE" "0,1" bitfld.long 0x4 0.--2. "SIG_ID,SIG_ID" "0,1,2,3,4,5,6,7" line.long 0x8 "DMAMUX_RG2CR,DMAMUX request generator channel 2 configuration register" hexmask.long.byte 0x8 19.--23. 1. "GNBREQ,GNBREQ" bitfld.long 0x8 17.--18. "GPOL,GPOL" "0,1,2,3" bitfld.long 0x8 16. "GE,GE" "0,1" bitfld.long 0x8 8. "OIE,OIE" "0,1" bitfld.long 0x8 0.--2. "SIG_ID,SIG_ID" "0,1,2,3,4,5,6,7" line.long 0xC "DMAMUX_RG3CR,DMAMUX request generator channel 3 configuration register" hexmask.long.byte 0xC 19.--23. 1. "GNBREQ,GNBREQ" bitfld.long 0xC 17.--18. "GPOL,GPOL" "0,1,2,3" bitfld.long 0xC 16. "GE,GE" "0,1" bitfld.long 0xC 8. "OIE,OIE" "0,1" bitfld.long 0xC 0.--2. "SIG_ID,SIG_ID" "0,1,2,3,4,5,6,7" line.long 0x10 "DMAMUX_RG4CR,DMAMUX request generator channel 4 configuration register" hexmask.long.byte 0x10 19.--23. 1. "GNBREQ,GNBREQ" bitfld.long 0x10 17.--18. "GPOL,GPOL" "0,1,2,3" bitfld.long 0x10 16. "GE,GE" "0,1" bitfld.long 0x10 8. "OIE,OIE" "0,1" bitfld.long 0x10 0.--2. "SIG_ID,SIG_ID" "0,1,2,3,4,5,6,7" line.long 0x14 "DMAMUX_RG5CR,DMAMUX request generator channel 5 configuration register" hexmask.long.byte 0x14 19.--23. 1. "GNBREQ,GNBREQ" bitfld.long 0x14 17.--18. "GPOL,GPOL" "0,1,2,3" bitfld.long 0x14 16. "GE,GE" "0,1" bitfld.long 0x14 8. "OIE,OIE" "0,1" bitfld.long 0x14 0.--2. "SIG_ID,SIG_ID" "0,1,2,3,4,5,6,7" line.long 0x18 "DMAMUX_RG6CR,DMAMUX request generator channel 6 configuration register" hexmask.long.byte 0x18 19.--23. 1. "GNBREQ,GNBREQ" bitfld.long 0x18 17.--18. "GPOL,GPOL" "0,1,2,3" bitfld.long 0x18 16. "GE,GE" "0,1" bitfld.long 0x18 8. "OIE,OIE" "0,1" bitfld.long 0x18 0.--2. "SIG_ID,SIG_ID" "0,1,2,3,4,5,6,7" line.long 0x1C "DMAMUX_RG7CR,DMAMUX request generator channel 7 configuration register" hexmask.long.byte 0x1C 19.--23. 1. "GNBREQ,GNBREQ" bitfld.long 0x1C 17.--18. "GPOL,GPOL" "0,1,2,3" bitfld.long 0x1C 16. "GE,GE" "0,1" bitfld.long 0x1C 8. "OIE,OIE" "0,1" bitfld.long 0x1C 0.--2. "SIG_ID,SIG_ID" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "DMAMUX_RGSR,DMAMUX request generator interrupt status register" bitfld.long 0x0 7. "OF7,OF7" "0,1" bitfld.long 0x0 6. "OF6,OF6" "0,1" bitfld.long 0x0 5. "OF5,OF5" "0,1" bitfld.long 0x0 4. "OF4,OF4" "0,1" bitfld.long 0x0 3. "OF3,OF3" "0,1" newline bitfld.long 0x0 2. "OF2,OF2" "0,1" bitfld.long 0x0 1. "OF1,OF1" "0,1" bitfld.long 0x0 0. "OF0,OF0" "0,1" wgroup.long 0x144++0x3 line.long 0x0 "DMAMUX_RGCFR,DMAMUX request generator interrupt clear flag register" bitfld.long 0x0 7. "COF7,COF7" "0,1" bitfld.long 0x0 6. "COF6,COF6" "0,1" bitfld.long 0x0 5. "COF5,COF5" "0,1" bitfld.long 0x0 4. "COF4,COF4" "0,1" bitfld.long 0x0 3. "COF3,COF3" "0,1" newline bitfld.long 0x0 2. "COF2,COF2" "0,1" bitfld.long 0x0 1. "COF1,COF1" "0,1" bitfld.long 0x0 0. "COF0,COF0" "0,1" rgroup.long 0x3EC++0x13 line.long 0x0 "DMAMUX_HWCFGR2,DMAMUX hardware configuration 2 register" hexmask.long.byte 0x0 0.--7. 1. "NUM_DMA_EXT_REQ,NUM_DMA_EXT_REQ" line.long 0x4 "DMAMUX_HWCFGR1,DMAMUX hardware configuration 1 register" hexmask.long.byte 0x4 24.--31. 1. "NUM_DMA_REQGEN,NUM_DMA_REQGEN" hexmask.long.byte 0x4 16.--23. 1. "NUM_DMA_TRIG,NUM_DMA_TRIG" hexmask.long.byte 0x4 8.--15. 1. "NUM_DMA_PERIPH_REQ,NUM_DMA_PERIPH_REQ" hexmask.long.byte 0x4 0.--7. 1. "NUM_DMA_STREAMS,NUM_DMA_STREAMS" line.long 0x8 "DMAMUX_VERR,This register identifies the IP version." hexmask.long.byte 0x8 4.--7. 1. "MAJREV,MAJREV" hexmask.long.byte 0x8 0.--3. 1. "MINREV,MINREV" line.long 0xC "DMAMUX_IPIDR,This register identifies the IP." hexmask.long 0xC 0.--31. 1. "ID,ID" line.long 0x10 "DMAMUX_SIDR,DMAMUX size identification register" hexmask.long 0x10 0.--31. 1. "SID,SID" tree.end sif (cpuis("STM32MP13*")) tree "DMAMUX2" base ad:0x48006000 group.long 0x0++0x1F line.long 0x0 "DMAMUX_C0CR,DMAMUX request line multiplexer channel 0 configuration register" bitfld.long 0x0 24.--26. "SYNC_ID,SYNC_ID" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 19.--23. 1. "NBREQ,NBREQ" bitfld.long 0x0 17.--18. "SPOL,SPOL" "0,1,2,3" bitfld.long 0x0 16. "SE,SE" "0,1" bitfld.long 0x0 9. "EGE,EGE" "0,1" newline bitfld.long 0x0 8. "SOIE,SOIE" "0,1" line.long 0x4 "DMAMUX_C1CR,DMAMUX request line multiplexer channel 1 configuration register" bitfld.long 0x4 24.--26. "SYNC_ID,SYNC_ID" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 19.--23. 1. "NBREQ,NBREQ" bitfld.long 0x4 17.--18. "SPOL,SPOL" "0,1,2,3" bitfld.long 0x4 16. "SE,SE" "0,1" bitfld.long 0x4 9. "EGE,EGE" "0,1" newline bitfld.long 0x4 8. "SOIE,SOIE" "0,1" line.long 0x8 "DMAMUX_C2CR,DMAMUX request line multiplexer channel 2 configuration register" bitfld.long 0x8 24.--26. "SYNC_ID,SYNC_ID" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x8 19.--23. 1. "NBREQ,NBREQ" bitfld.long 0x8 17.--18. "SPOL,SPOL" "0,1,2,3" bitfld.long 0x8 16. "SE,SE" "0,1" bitfld.long 0x8 9. "EGE,EGE" "0,1" newline bitfld.long 0x8 8. "SOIE,SOIE" "0,1" line.long 0xC "DMAMUX_C3CR,DMAMUX request line multiplexer channel 3 configuration register" bitfld.long 0xC 24.--26. "SYNC_ID,SYNC_ID" "0,1,2,3,4,5,6,7" hexmask.long.byte 0xC 19.--23. 1. "NBREQ,NBREQ" bitfld.long 0xC 17.--18. "SPOL,SPOL" "0,1,2,3" bitfld.long 0xC 16. "SE,SE" "0,1" bitfld.long 0xC 9. "EGE,EGE" "0,1" newline bitfld.long 0xC 8. "SOIE,SOIE" "0,1" line.long 0x10 "DMAMUX_C4CR,DMAMUX request line multiplexer channel 4 configuration register" bitfld.long 0x10 24.--26. "SYNC_ID,SYNC_ID" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x10 19.--23. 1. "NBREQ,NBREQ" bitfld.long 0x10 17.--18. "SPOL,SPOL" "0,1,2,3" bitfld.long 0x10 16. "SE,SE" "0,1" bitfld.long 0x10 9. "EGE,EGE" "0,1" newline bitfld.long 0x10 8. "SOIE,SOIE" "0,1" line.long 0x14 "DMAMUX_C5CR,DMAMUX request line multiplexer channel 5 configuration register" bitfld.long 0x14 24.--26. "SYNC_ID,SYNC_ID" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x14 19.--23. 1. "NBREQ,NBREQ" bitfld.long 0x14 17.--18. "SPOL,SPOL" "0,1,2,3" bitfld.long 0x14 16. "SE,SE" "0,1" bitfld.long 0x14 9. "EGE,EGE" "0,1" newline bitfld.long 0x14 8. "SOIE,SOIE" "0,1" line.long 0x18 "DMAMUX_C6CR,DMAMUX request line multiplexer channel 6 configuration register" bitfld.long 0x18 24.--26. "SYNC_ID,SYNC_ID" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x18 19.--23. 1. "NBREQ,NBREQ" bitfld.long 0x18 17.--18. "SPOL,SPOL" "0,1,2,3" bitfld.long 0x18 16. "SE,SE" "0,1" bitfld.long 0x18 9. "EGE,EGE" "0,1" newline bitfld.long 0x18 8. "SOIE,SOIE" "0,1" line.long 0x1C "DMAMUX_C7CR,DMAMUX request line multiplexer channel 7 configuration register" bitfld.long 0x1C 24.--26. "SYNC_ID,SYNC_ID" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x1C 19.--23. 1. "NBREQ,NBREQ" bitfld.long 0x1C 17.--18. "SPOL,SPOL" "0,1,2,3" bitfld.long 0x1C 16. "SE,SE" "0,1" bitfld.long 0x1C 9. "EGE,EGE" "0,1" newline bitfld.long 0x1C 8. "SOIE,SOIE" "0,1" rgroup.long 0x80++0x3 line.long 0x0 "DMAMUX_CSR,DMAMUX request line multiplexer interrupt channel status register" bitfld.long 0x0 15. "SOF15,SOF15" "0,1" bitfld.long 0x0 14. "SOF14,SOF14" "0,1" bitfld.long 0x0 13. "SOF13,SOF13" "0,1" bitfld.long 0x0 12. "SOF12,SOF12" "0,1" bitfld.long 0x0 11. "SOF11,SOF11" "0,1" newline bitfld.long 0x0 10. "SOF10,SOF10" "0,1" bitfld.long 0x0 9. "SOF9,SOF9" "0,1" bitfld.long 0x0 8. "SOF8,SOF8" "0,1" bitfld.long 0x0 7. "SOF7,SOF7" "0,1" bitfld.long 0x0 6. "SOF6,SOF6" "0,1" newline bitfld.long 0x0 5. "SOF5,SOF5" "0,1" bitfld.long 0x0 4. "SOF4,SOF4" "0,1" bitfld.long 0x0 3. "SOF3,SOF3" "0,1" bitfld.long 0x0 2. "SOF2,SOF2" "0,1" bitfld.long 0x0 1. "SOF1,SOF1" "0,1" newline bitfld.long 0x0 0. "SOF0,SOF0" "0,1" wgroup.long 0x84++0x3 line.long 0x0 "DMAMUX_CFR,DMAMUX request line multiplexer interrupt clear flag register" bitfld.long 0x0 15. "CSOF15,CSOF15" "0,1" bitfld.long 0x0 14. "CSOF14,CSOF14" "0,1" bitfld.long 0x0 13. "CSOF13,CSOF13" "0,1" bitfld.long 0x0 12. "CSOF12,CSOF12" "0,1" bitfld.long 0x0 11. "CSOF11,CSOF11" "0,1" newline bitfld.long 0x0 10. "CSOF10,CSOF10" "0,1" bitfld.long 0x0 9. "CSOF9,CSOF9" "0,1" bitfld.long 0x0 8. "CSOF8,CSOF8" "0,1" bitfld.long 0x0 7. "CSOF7,CSOF7" "0,1" bitfld.long 0x0 6. "CSOF6,CSOF6" "0,1" newline bitfld.long 0x0 5. "CSOF5,CSOF5" "0,1" bitfld.long 0x0 4. "CSOF4,CSOF4" "0,1" bitfld.long 0x0 3. "CSOF3,CSOF3" "0,1" bitfld.long 0x0 2. "CSOF2,CSOF2" "0,1" bitfld.long 0x0 1. "CSOF1,CSOF1" "0,1" newline bitfld.long 0x0 0. "CSOF0,CSOF0" "0,1" group.long 0x100++0x1F line.long 0x0 "DMAMUX_RG0CR,DMAMUX request generator channel 0 configuration register" hexmask.long.byte 0x0 19.--23. 1. "GNBREQ,GNBREQ" bitfld.long 0x0 17.--18. "GPOL,GPOL" "0,1,2,3" bitfld.long 0x0 16. "GE,GE" "0,1" bitfld.long 0x0 8. "OIE,OIE" "0,1" bitfld.long 0x0 0.--2. "SIG_ID,SIG_ID" "0,1,2,3,4,5,6,7" line.long 0x4 "DMAMUX_RG1CR,DMAMUX request generator channel 1 configuration register" hexmask.long.byte 0x4 19.--23. 1. "GNBREQ,GNBREQ" bitfld.long 0x4 17.--18. "GPOL,GPOL" "0,1,2,3" bitfld.long 0x4 16. "GE,GE" "0,1" bitfld.long 0x4 8. "OIE,OIE" "0,1" bitfld.long 0x4 0.--2. "SIG_ID,SIG_ID" "0,1,2,3,4,5,6,7" line.long 0x8 "DMAMUX_RG2CR,DMAMUX request generator channel 2 configuration register" hexmask.long.byte 0x8 19.--23. 1. "GNBREQ,GNBREQ" bitfld.long 0x8 17.--18. "GPOL,GPOL" "0,1,2,3" bitfld.long 0x8 16. "GE,GE" "0,1" bitfld.long 0x8 8. "OIE,OIE" "0,1" bitfld.long 0x8 0.--2. "SIG_ID,SIG_ID" "0,1,2,3,4,5,6,7" line.long 0xC "DMAMUX_RG3CR,DMAMUX request generator channel 3 configuration register" hexmask.long.byte 0xC 19.--23. 1. "GNBREQ,GNBREQ" bitfld.long 0xC 17.--18. "GPOL,GPOL" "0,1,2,3" bitfld.long 0xC 16. "GE,GE" "0,1" bitfld.long 0xC 8. "OIE,OIE" "0,1" bitfld.long 0xC 0.--2. "SIG_ID,SIG_ID" "0,1,2,3,4,5,6,7" line.long 0x10 "DMAMUX_RG4CR,DMAMUX request generator channel 4 configuration register" hexmask.long.byte 0x10 19.--23. 1. "GNBREQ,GNBREQ" bitfld.long 0x10 17.--18. "GPOL,GPOL" "0,1,2,3" bitfld.long 0x10 16. "GE,GE" "0,1" bitfld.long 0x10 8. "OIE,OIE" "0,1" bitfld.long 0x10 0.--2. "SIG_ID,SIG_ID" "0,1,2,3,4,5,6,7" line.long 0x14 "DMAMUX_RG5CR,DMAMUX request generator channel 5 configuration register" hexmask.long.byte 0x14 19.--23. 1. "GNBREQ,GNBREQ" bitfld.long 0x14 17.--18. "GPOL,GPOL" "0,1,2,3" bitfld.long 0x14 16. "GE,GE" "0,1" bitfld.long 0x14 8. "OIE,OIE" "0,1" bitfld.long 0x14 0.--2. "SIG_ID,SIG_ID" "0,1,2,3,4,5,6,7" line.long 0x18 "DMAMUX_RG6CR,DMAMUX request generator channel 6 configuration register" hexmask.long.byte 0x18 19.--23. 1. "GNBREQ,GNBREQ" bitfld.long 0x18 17.--18. "GPOL,GPOL" "0,1,2,3" bitfld.long 0x18 16. "GE,GE" "0,1" bitfld.long 0x18 8. "OIE,OIE" "0,1" bitfld.long 0x18 0.--2. "SIG_ID,SIG_ID" "0,1,2,3,4,5,6,7" line.long 0x1C "DMAMUX_RG7CR,DMAMUX request generator channel 7 configuration register" hexmask.long.byte 0x1C 19.--23. 1. "GNBREQ,GNBREQ" bitfld.long 0x1C 17.--18. "GPOL,GPOL" "0,1,2,3" bitfld.long 0x1C 16. "GE,GE" "0,1" bitfld.long 0x1C 8. "OIE,OIE" "0,1" bitfld.long 0x1C 0.--2. "SIG_ID,SIG_ID" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "DMAMUX_RGSR,DMAMUX request generator interrupt status register" bitfld.long 0x0 7. "OF7,OF7" "0,1" bitfld.long 0x0 6. "OF6,OF6" "0,1" bitfld.long 0x0 5. "OF5,OF5" "0,1" bitfld.long 0x0 4. "OF4,OF4" "0,1" bitfld.long 0x0 3. "OF3,OF3" "0,1" newline bitfld.long 0x0 2. "OF2,OF2" "0,1" bitfld.long 0x0 1. "OF1,OF1" "0,1" bitfld.long 0x0 0. "OF0,OF0" "0,1" wgroup.long 0x144++0x3 line.long 0x0 "DMAMUX_RGCFR,DMAMUX request generator interrupt clear flag register" bitfld.long 0x0 7. "COF7,COF7" "0,1" bitfld.long 0x0 6. "COF6,COF6" "0,1" bitfld.long 0x0 5. "COF5,COF5" "0,1" bitfld.long 0x0 4. "COF4,COF4" "0,1" bitfld.long 0x0 3. "COF3,COF3" "0,1" newline bitfld.long 0x0 2. "COF2,COF2" "0,1" bitfld.long 0x0 1. "COF1,COF1" "0,1" bitfld.long 0x0 0. "COF0,COF0" "0,1" rgroup.long 0x3EC++0x13 line.long 0x0 "DMAMUX_HWCFGR2,DMAMUX hardware configuration 2 register" hexmask.long.byte 0x0 0.--7. 1. "NUM_DMA_EXT_REQ,NUM_DMA_EXT_REQ" line.long 0x4 "DMAMUX_HWCFGR1,DMAMUX hardware configuration 1 register" hexmask.long.byte 0x4 24.--31. 1. "NUM_DMA_REQGEN,NUM_DMA_REQGEN" hexmask.long.byte 0x4 16.--23. 1. "NUM_DMA_TRIG,NUM_DMA_TRIG" hexmask.long.byte 0x4 8.--15. 1. "NUM_DMA_PERIPH_REQ,NUM_DMA_PERIPH_REQ" hexmask.long.byte 0x4 0.--7. 1. "NUM_DMA_STREAMS,NUM_DMA_STREAMS" line.long 0x8 "DMAMUX_VERR,This register identifies the IP version." hexmask.long.byte 0x8 4.--7. 1. "MAJREV,MAJREV" hexmask.long.byte 0x8 0.--3. 1. "MINREV,MINREV" line.long 0xC "DMAMUX_IPIDR,This register identifies the IP." hexmask.long 0xC 0.--31. 1. "ID,ID" line.long 0x10 "DMAMUX_SIDR,DMAMUX size identification register" hexmask.long 0x10 0.--31. 1. "SID,SID" tree.end endif tree.end sif (cpuis("STM32MP157*")) tree "DSI (DSI Host)" base ad:0x5A000000 rgroup.long 0x0++0x3 line.long 0x0 "DSI_VR,DSI Host version register" hexmask.long 0x0 0.--31. 1. "VERSION,VERSION" group.long 0x4++0x17 line.long 0x0 "DSI_CR,DSI Host control register" bitfld.long 0x0 0. "EN,EN" "0,1" line.long 0x4 "DSI_CCR,DSI Host clock control register" hexmask.long.byte 0x4 8.--15. 1. "TOCKDIV,TOCKDIV" hexmask.long.byte 0x4 0.--7. 1. "TXECKDIV,TXECKDIV" line.long 0x8 "DSI_LVCIDR,DSI Host LTDC VCID register" bitfld.long 0x8 0.--1. "VCID,VCID" "0,1,2,3" line.long 0xC "DSI_LCOLCR,DSI Host LTDC color coding register" bitfld.long 0xC 8. "LPE,LPE" "0,1" hexmask.long.byte 0xC 0.--3. 1. "COLC,COLC" line.long 0x10 "DSI_LPCR,DSI Host LTDC polarity configuration register" bitfld.long 0x10 2. "HSP,HSP" "0,1" bitfld.long 0x10 1. "VSP,VSP" "0,1" bitfld.long 0x10 0. "DEP,DEP" "0,1" line.long 0x14 "DSI_LPMCR,DSI Host low-power mode configuration register" hexmask.long.byte 0x14 16.--23. 1. "LPSIZE,LPSIZE" hexmask.long.byte 0x14 0.--7. 1. "VLPSIZE,VLPSIZE" group.long 0x2C++0x3 line.long 0x0 "DSI_PCR,DSI Host protocol configuration register" bitfld.long 0x0 4. "CRCRXE,CRCRXE" "0,1" bitfld.long 0x0 3. "ECCRXE,ECCRXE" "0,1" bitfld.long 0x0 2. "BTAE,BTAE" "0,1" bitfld.long 0x0 1. "ETRXE,ETRXE" "0,1" bitfld.long 0x0 0. "ETTXE,ETTXE" "0,1" rgroup.long 0x30++0x3 line.long 0x0 "DSI_GVCIDR,DSI Host generic VCID register" bitfld.long 0x0 0.--1. "VCID,VCID" "0,1,2,3" group.long 0x34++0x3F line.long 0x0 "DSI_MCR,DSI Host mode configuration register" bitfld.long 0x0 0. "CMDM,CMDM" "0,1" line.long 0x4 "DSI_VMCR,DSI Host video mode configuration register" bitfld.long 0x4 24. "PGO,PGO" "0,1" bitfld.long 0x4 20. "PGM,PGM" "0,1" bitfld.long 0x4 16. "PGE,PGE" "0,1" bitfld.long 0x4 15. "LPCE,LPCE" "0,1" bitfld.long 0x4 14. "FBTAAE,FBTAAE" "0,1" bitfld.long 0x4 13. "LPHFPE,LPHFPE" "0,1" bitfld.long 0x4 12. "LPHBPE,LPHBPE" "0,1" newline bitfld.long 0x4 11. "LPVAE,LPVAE" "0,1" bitfld.long 0x4 10. "LPVFPE,LPVFPE" "0,1" bitfld.long 0x4 9. "LPVBPE,LPVBPE" "0,1" bitfld.long 0x4 8. "LPVSAE,LPVSAE" "0,1" bitfld.long 0x4 0.--1. "VMT,VMT" "0,1,2,3" line.long 0x8 "DSI_VPCR,DSI Host video packet configuration register" hexmask.long.word 0x8 0.--13. 1. "VPSIZE,VPSIZE" line.long 0xC "DSI_VCCR,DSI Host video chunks configuration register" hexmask.long.word 0xC 0.--12. 1. "NUMC,NUMC" line.long 0x10 "DSI_VNPCR,DSI Host video null packet configuration register" hexmask.long.word 0x10 0.--12. 1. "NPSIZE,NPSIZE" line.long 0x14 "DSI_VHSACR,DSI Host video HSA configuration register" hexmask.long.word 0x14 0.--11. 1. "HSA,HSA" line.long 0x18 "DSI_VHBPCR,DSI Host video HBP configuration register" hexmask.long.word 0x18 0.--11. 1. "HBP,HBP" line.long 0x1C "DSI_VLCR,DSI Host video line configuration register" hexmask.long.word 0x1C 0.--14. 1. "HLINE,HLINE" line.long 0x20 "DSI_VVSACR,DSI Host video VSA configuration register" hexmask.long.word 0x20 0.--9. 1. "VSA,VSA" line.long 0x24 "DSI_VVBPCR,DSI Host video VBP configuration register" hexmask.long.word 0x24 0.--9. 1. "VBP,VBP" line.long 0x28 "DSI_VVFPCR,DSI Host video VFP configuration register" hexmask.long.word 0x28 0.--9. 1. "VFP,VFP" line.long 0x2C "DSI_VVACR,DSI Host video VA configuration register" hexmask.long.word 0x2C 0.--13. 1. "VA,VA" line.long 0x30 "DSI_LCCR,DSI Host LTDC command configuration register" hexmask.long.word 0x30 0.--15. 1. "CMDSIZE,CMDSIZE" line.long 0x34 "DSI_CMCR,DSI Host command mode configuration register" bitfld.long 0x34 24. "MRDPS,MRDPS" "0,1" bitfld.long 0x34 19. "DLWTX,DLWTX" "0,1" bitfld.long 0x34 18. "DSR0TX,DSR0TX" "0,1" bitfld.long 0x34 17. "DSW1TX,DSW1TX" "0,1" bitfld.long 0x34 16. "DSW0TX,DSW0TX" "0,1" bitfld.long 0x34 14. "GLWTX,GLWTX" "0,1" bitfld.long 0x34 13. "GSR2TX,GSR2TX" "0,1" newline bitfld.long 0x34 12. "GSR1TX,GSR1TX" "0,1" bitfld.long 0x34 11. "GSR0TX,GSR0TX" "0,1" bitfld.long 0x34 10. "GSW2TX,GSW2TX" "0,1" bitfld.long 0x34 9. "GSW1TX,GSW1TX" "0,1" bitfld.long 0x34 8. "GSW0TX,GSW0TX" "0,1" bitfld.long 0x34 1. "ARE,ARE" "0,1" bitfld.long 0x34 0. "TEARE,TEARE" "0,1" line.long 0x38 "DSI_GHCR,DSI Host generic header configuration register" hexmask.long.byte 0x38 16.--23. 1. "WCMSB,WCMSB" hexmask.long.byte 0x38 8.--15. 1. "WCLSB,WCLSB" bitfld.long 0x38 6.--7. "VCID,VCID" "0,1,2,3" hexmask.long.byte 0x38 0.--5. 1. "DT,DT" line.long 0x3C "DSI_GPDR,DSI Host generic payload data register" hexmask.long.byte 0x3C 24.--31. 1. "DATA4,DATA4" hexmask.long.byte 0x3C 16.--23. 1. "DATA3,DATA3" hexmask.long.byte 0x3C 8.--15. 1. "DATA2,DATA2" hexmask.long.byte 0x3C 0.--7. 1. "DATA1,DATA1" rgroup.long 0x74++0x3 line.long 0x0 "DSI_GPSR,DSI Host generic packet status register" bitfld.long 0x0 6. "RCB,RCB" "0,1" bitfld.long 0x0 5. "PRDFF,PRDFF" "0,1" bitfld.long 0x0 4. "PRDFE,PRDFE" "0,1" bitfld.long 0x0 3. "PWRFF,PWRFF" "0,1" bitfld.long 0x0 2. "PWRFE,PWRFE" "0,1" bitfld.long 0x0 1. "CMDFF,CMDFF" "0,1" bitfld.long 0x0 0. "CMDFE,CMDFE" "0,1" group.long 0x78++0x17 line.long 0x0 "DSI_TCCR0,DSI Host timeout counter configuration register 0" hexmask.long.word 0x0 16.--31. 1. "HSTX_TOCNT,HSTX_TOCNT" hexmask.long.word 0x0 0.--15. 1. "LPRX_TOCNT,LPRX_TOCNT" line.long 0x4 "DSI_TCCR1,DSI Host timeout counter configuration register 1" hexmask.long.word 0x4 0.--15. 1. "HSRD_TOCNT,HSRD_TOCNT" line.long 0x8 "DSI_TCCR2,DSI Host timeout counter configuration register 2" hexmask.long.word 0x8 0.--15. 1. "LPRD_TOCNT,LPRD_TOCNT" line.long 0xC "DSI_TCCR3,DSI Host timeout counter configuration register 3" bitfld.long 0xC 24. "PM,PM" "0,1" hexmask.long.word 0xC 0.--15. 1. "HSWR_TOCNT,HSWR_TOCNT" line.long 0x10 "DSI_TCCR4,DSI Host timeout counter configuration register 4" hexmask.long.word 0x10 0.--15. 1. "LPWR_TOCNT,LPWR_TOCNT" line.long 0x14 "DSI_TCCR5,DSI Host timeout counter configuration register 5" hexmask.long.word 0x14 0.--15. 1. "BTA_TOCNT,BTA_TOCNT" group.long 0x94++0x1B line.long 0x0 "DSI_CLCR,DSI Host clock lane configuration register" bitfld.long 0x0 1. "ACR,ACR" "0,1" bitfld.long 0x0 0. "DPCC,DPCC" "0,1" line.long 0x4 "DSI_CLTCR,DSI Host clock lane timer configuration register" hexmask.long.word 0x4 16.--25. 1. "HS2LP_TIME,HS2LP_TIME" hexmask.long.word 0x4 0.--9. 1. "LP2HS_TIME,LP2HS_TIME" line.long 0x8 "DSI_DLTCR,DSI Host data lane timer configuration register" hexmask.long.word 0x8 16.--25. 1. "HS2LP_TIME,HS2LP_TIME" hexmask.long.word 0x8 0.--9. 1. "LP2HS_TIME,LP2HS_TIME" line.long 0xC "DSI_PCTLR,DSI Host PHY control register" bitfld.long 0xC 2. "CKE,CKE" "0,1" bitfld.long 0xC 1. "DEN,DEN" "0,1" line.long 0x10 "DSI_PCONFR,DSI Host PHY configuration register" hexmask.long.byte 0x10 8.--15. 1. "SW_TIME,SW_TIME" bitfld.long 0x10 0.--1. "NL,NL" "0,1,2,3" line.long 0x14 "DSI_PUCR,DSI Host PHY ULPS control register" bitfld.long 0x14 3. "UEDL,UEDL" "0,1" bitfld.long 0x14 2. "URDL,URDL" "0,1" bitfld.long 0x14 1. "UECL,UECL" "0,1" bitfld.long 0x14 0. "URCL,URCL" "0,1" line.long 0x18 "DSI_PTTCR,DSI Host PHY TX triggers configuration register" hexmask.long.byte 0x18 0.--3. 1. "TX_TRIG,TX_TRIG" rgroup.long 0xB0++0x3 line.long 0x0 "DSI_PSR,DSI Host PHY status register" bitfld.long 0x0 8. "UAN1,UAN1" "0,1" bitfld.long 0x0 7. "PSS1,PSS1" "0,1" bitfld.long 0x0 6. "RUE0,RUE0" "0,1" bitfld.long 0x0 5. "UAN0,UAN0" "0,1" bitfld.long 0x0 4. "PSS0,PSS0" "0,1" bitfld.long 0x0 3. "UANC,UANC" "0,1" bitfld.long 0x0 2. "PSSC,PSSC" "0,1" newline bitfld.long 0x0 1. "PD,PD" "0,1" rgroup.long 0xBC++0x7 line.long 0x0 "DSI_ISR0,DSI Host interrupt and status register 0" bitfld.long 0x0 20. "PE4,PE4" "0,1" bitfld.long 0x0 19. "PE3,PE3" "0,1" bitfld.long 0x0 18. "PE2,PE2" "0,1" bitfld.long 0x0 17. "PE1,PE1" "0,1" bitfld.long 0x0 16. "PE0,PE0" "0,1" bitfld.long 0x0 15. "AE15,AE15" "0,1" bitfld.long 0x0 14. "AE14,AE14" "0,1" newline bitfld.long 0x0 13. "AE13,AE13" "0,1" bitfld.long 0x0 12. "AE12,AE12" "0,1" bitfld.long 0x0 11. "AE11,AE11" "0,1" bitfld.long 0x0 10. "AE10,AE10" "0,1" bitfld.long 0x0 9. "AE9,AE9" "0,1" bitfld.long 0x0 8. "AE8,AE8" "0,1" bitfld.long 0x0 7. "AE7,AE7" "0,1" newline bitfld.long 0x0 6. "AE6,AE6" "0,1" bitfld.long 0x0 5. "AE5,AE5" "0,1" bitfld.long 0x0 4. "AE4,AE4" "0,1" bitfld.long 0x0 3. "AE3,AE3" "0,1" bitfld.long 0x0 2. "AE2,AE2" "0,1" bitfld.long 0x0 1. "AE1,AE1" "0,1" bitfld.long 0x0 0. "AE0,AE0" "0,1" line.long 0x4 "DSI_ISR1,DSI Host interrupt and status register 1" bitfld.long 0x4 12. "GPRXE,GPRXE" "0,1" bitfld.long 0x4 11. "GPRDE,GPRDE" "0,1" bitfld.long 0x4 10. "GPTXE,GPTXE" "0,1" bitfld.long 0x4 9. "GPWRE,GPWRE" "0,1" bitfld.long 0x4 8. "GCWRE,GCWRE" "0,1" bitfld.long 0x4 7. "LPWRE,LPWRE" "0,1" bitfld.long 0x4 6. "EOTPE,EOTPE" "0,1" newline bitfld.long 0x4 5. "PSE,PSE" "0,1" bitfld.long 0x4 4. "CRCE,CRCE" "0,1" bitfld.long 0x4 3. "ECCME,ECCME" "0,1" bitfld.long 0x4 2. "ECCSE,ECCSE" "0,1" bitfld.long 0x4 1. "TOLPRX,TOLPRX" "0,1" bitfld.long 0x4 0. "TOHSTX,TOHSTX" "0,1" group.long 0xC4++0x7 line.long 0x0 "DSI_IER0,DSI Host interrupt enable register 0" bitfld.long 0x0 20. "PE4IE,PE4IE" "0,1" bitfld.long 0x0 19. "PE3IE,PE3IE" "0,1" bitfld.long 0x0 18. "PE2IE,PE2IE" "0,1" bitfld.long 0x0 17. "PE1IE,PE1IE" "0,1" bitfld.long 0x0 16. "PE0IE,PE0IE" "0,1" bitfld.long 0x0 15. "AE15IE,AE15IE" "0,1" bitfld.long 0x0 14. "AE14IE,AE14IE" "0,1" newline bitfld.long 0x0 13. "AE13IE,AE13IE" "0,1" bitfld.long 0x0 12. "AE12IE,AE12IE" "0,1" bitfld.long 0x0 11. "AE11IE,AE11IE" "0,1" bitfld.long 0x0 10. "AE10IE,AE10IE" "0,1" bitfld.long 0x0 9. "AE9IE,AE9IE" "0,1" bitfld.long 0x0 8. "AE8IE,AE8IE" "0,1" bitfld.long 0x0 7. "AE7IE,AE7IE" "0,1" newline bitfld.long 0x0 6. "AE6IE,AE6IE" "0,1" bitfld.long 0x0 5. "AE5IE,AE5IE" "0,1" bitfld.long 0x0 4. "AE4IE,AE4IE" "0,1" bitfld.long 0x0 3. "AE3IE,AE3IE" "0,1" bitfld.long 0x0 2. "AE2IE,AE2IE" "0,1" bitfld.long 0x0 1. "AE1IE,AE1IE" "0,1" bitfld.long 0x0 0. "AE0IE,AE0IE" "0,1" line.long 0x4 "DSI_IER1,DSI Host interrupt enable register 1" bitfld.long 0x4 12. "GPRXEIE,GPRXEIE" "0,1" bitfld.long 0x4 11. "GPRDEIE,GPRDEIE" "0,1" bitfld.long 0x4 10. "GPTXEIE,GPTXEIE" "0,1" bitfld.long 0x4 9. "GPWREIE,GPWREIE" "0,1" bitfld.long 0x4 8. "GCWREIE,GCWREIE" "0,1" bitfld.long 0x4 7. "LPWREIE,LPWREIE" "0,1" bitfld.long 0x4 6. "EOTPEIE,EOTPEIE" "0,1" newline bitfld.long 0x4 5. "PSEIE,PSEIE" "0,1" bitfld.long 0x4 4. "CRCEIE,CRCEIE" "0,1" bitfld.long 0x4 3. "ECCMEIE,ECCMEIE" "0,1" bitfld.long 0x4 2. "ECCSEIE,ECCSEIE" "0,1" bitfld.long 0x4 1. "TOLPRXIE,TOLPRXIE" "0,1" bitfld.long 0x4 0. "TOHSTXIE,TOHSTXIE" "0,1" wgroup.long 0xD8++0x7 line.long 0x0 "DSI_FIR0,DSI Host force interrupt register 0" bitfld.long 0x0 20. "FPE4,FPE4" "0,1" bitfld.long 0x0 19. "FPE3,FPE3" "0,1" bitfld.long 0x0 18. "FPE2,FPE2" "0,1" bitfld.long 0x0 17. "FPE1,FPE1" "0,1" bitfld.long 0x0 16. "FPE0,FPE0" "0,1" bitfld.long 0x0 15. "FAE15,FAE15" "0,1" bitfld.long 0x0 14. "FAE14,FAE14" "0,1" newline bitfld.long 0x0 13. "FAE13,FAE13" "0,1" bitfld.long 0x0 12. "FAE12,FAE12" "0,1" bitfld.long 0x0 11. "FAE11,FAE11" "0,1" bitfld.long 0x0 10. "FAE10,FAE10" "0,1" bitfld.long 0x0 9. "FAE9,FAE9" "0,1" bitfld.long 0x0 8. "FAE8,FAE8" "0,1" bitfld.long 0x0 7. "FAE7,FAE7" "0,1" newline bitfld.long 0x0 6. "FAE6,FAE6" "0,1" bitfld.long 0x0 5. "FAE5,FAE5" "0,1" bitfld.long 0x0 4. "FAE4,FAE4" "0,1" bitfld.long 0x0 3. "FAE3,FAE3" "0,1" bitfld.long 0x0 2. "FAE2,FAE2" "0,1" bitfld.long 0x0 1. "FAE1,FAE1" "0,1" bitfld.long 0x0 0. "FAE0,FAE0" "0,1" line.long 0x4 "DSI_FIR1,DSI Host force interrupt register 1" bitfld.long 0x4 12. "FGPRXE,FGPRXE" "0,1" bitfld.long 0x4 11. "FGPRDE,FGPRDE" "0,1" bitfld.long 0x4 10. "FGPTXE,FGPTXE" "0,1" bitfld.long 0x4 9. "FGPWRE,FGPWRE" "0,1" bitfld.long 0x4 8. "FGCWRE,FGCWRE" "0,1" bitfld.long 0x4 7. "FLPWRE,FLPWRE" "0,1" bitfld.long 0x4 6. "FEOTPE,FEOTPE" "0,1" newline bitfld.long 0x4 5. "FPSE,FPSE" "0,1" bitfld.long 0x4 4. "FCRCE,FCRCE" "0,1" bitfld.long 0x4 3. "FECCME,FECCME" "0,1" bitfld.long 0x4 2. "FECCSE,FECCSE" "0,1" bitfld.long 0x4 1. "FTOLPRX,FTOLPRX" "0,1" bitfld.long 0x4 0. "FTOHSTX,FTOHSTX" "0,1" group.long 0xF4++0x3 line.long 0x0 "DSI_DLTRCR,DSI Host data lane timer read configuration register" hexmask.long.word 0x0 0.--14. 1. "MRD_TIME,MRD_TIME" group.long 0x100++0x3 line.long 0x0 "DSI_VSCR,DSI Host video shadow control register" bitfld.long 0x0 8. "UR,UR" "0,1" bitfld.long 0x0 0. "EN,EN" "0,1" group.long 0x10C++0x3 line.long 0x0 "DSI_LCVCIDR,DSI Host LTDC current VCID register" bitfld.long 0x0 0.--1. "VCID,VCID" "0,1,2,3" rgroup.long 0x110++0x3 line.long 0x0 "DSI_LCCCR,DSI Host LTDC current color coding register" bitfld.long 0x0 8. "LPE,LPE" "0,1" hexmask.long.byte 0x0 0.--3. 1. "COLC,COLC" rgroup.long 0x118++0x3 line.long 0x0 "DSI_LPMCCR,DSI Host low-power mode current configuration register" hexmask.long.byte 0x0 16.--23. 1. "LPSIZE,LPSIZE" hexmask.long.byte 0x0 0.--7. 1. "VLPSIZE,VLPSIZE" rgroup.long 0x138++0x2B line.long 0x0 "DSI_VMCCR,DSI Host video mode current configuration register" bitfld.long 0x0 9. "LPCE,LPCE" "0,1" bitfld.long 0x0 8. "FBTAAE,FBTAAE" "0,1" bitfld.long 0x0 7. "LPHFE,LPHFE" "0,1" bitfld.long 0x0 6. "LPHBPE,LPHBPE" "0,1" bitfld.long 0x0 5. "LPVAE,LPVAE" "0,1" bitfld.long 0x0 4. "LPVFPE,LPVFPE" "0,1" bitfld.long 0x0 3. "LPVBPE,LPVBPE" "0,1" newline bitfld.long 0x0 2. "LPVSAE,LPVSAE" "0,1" bitfld.long 0x0 0.--1. "VMT,VMT" "0,1,2,3" line.long 0x4 "DSI_VPCCR,DSI Host video packet current configuration register" hexmask.long.word 0x4 0.--13. 1. "VPSIZE,VPSIZE" line.long 0x8 "DSI_VCCCR,DSI Host video chunks current configuration register" hexmask.long.word 0x8 0.--12. 1. "NUMC,NUMC" line.long 0xC "DSI_VNPCCR,DSI Host video null packet current configuration register" hexmask.long.word 0xC 0.--12. 1. "NPSIZE,NPSIZE" line.long 0x10 "DSI_VHSACCR,DSI Host video HSA current configuration register" hexmask.long.word 0x10 0.--11. 1. "HSA,HSA" line.long 0x14 "DSI_VHBPCCR,DSI Host video HBP current configuration register" hexmask.long.word 0x14 0.--11. 1. "HBP,HBP" line.long 0x18 "DSI_VLCCR,DSI Host video line current configuration register" hexmask.long.word 0x18 0.--14. 1. "HLINE,HLINE" line.long 0x1C "DSI_VVSACCR,DSI Host video VSA current configuration register" hexmask.long.word 0x1C 0.--9. 1. "VSA,VSA" line.long 0x20 "DSI_VVBPCCR,DSI Host video VBP current configuration register" hexmask.long.word 0x20 0.--9. 1. "VBP,VBP" line.long 0x24 "DSI_VVFPCCR,DSI Host video VFP current configuration register" hexmask.long.word 0x24 0.--9. 1. "VFP,VFP" line.long 0x28 "DSI_VVACCR,DSI Host video VA current configuration register" hexmask.long.word 0x28 0.--13. 1. "VA,VA" group.long 0x400++0xB line.long 0x0 "DSI_WCFGR,DSI wrapper configuration register" bitfld.long 0x0 7. "VSPOL,VSPOL" "0,1" bitfld.long 0x0 6. "AR,AR" "0,1" bitfld.long 0x0 5. "TEPOL,TEPOL" "0,1" bitfld.long 0x0 4. "TESRC,TESRC" "0,1" bitfld.long 0x0 1.--3. "COLMUX,COLMUX" "0,1,2,3,4,5,6,7" bitfld.long 0x0 0. "DSIM,DSIM" "0,1" line.long 0x4 "DSI_WCR,DSI wrapper control register" bitfld.long 0x4 3. "DSIEN,DSIEN" "0,1" bitfld.long 0x4 2. "LTDCEN,LTDCEN" "0,1" bitfld.long 0x4 1. "SHTDN,SHTDN" "0,1" bitfld.long 0x4 0. "COLM,COLM" "0,1" line.long 0x8 "DSI_WIER,DSI wrapper interrupt enable register" bitfld.long 0x8 13. "RRIE,RRIE" "0,1" bitfld.long 0x8 10. "PLLUIE,PLLUIE" "0,1" bitfld.long 0x8 9. "PLLLIE,PLLLIE" "0,1" bitfld.long 0x8 1. "ERIE,ERIE" "0,1" bitfld.long 0x8 0. "TEIE,TEIE" "0,1" rgroup.long 0x40C++0x3 line.long 0x0 "DSI_WISR,DSI wrapper interrupt and status register" bitfld.long 0x0 13. "RRIF,RRIF" "0,1" bitfld.long 0x0 12. "RRS,RRS" "0,1" bitfld.long 0x0 10. "PLLUIF,PLLUIF" "0,1" bitfld.long 0x0 9. "PLLLIF,PLLLIF" "0,1" bitfld.long 0x0 8. "PLLLS,PLLLS" "0,1" bitfld.long 0x0 2. "BUSY,BUSY" "0,1" bitfld.long 0x0 1. "ERIF,ERIF" "0,1" newline bitfld.long 0x0 0. "TEIF,TEIF" "0,1" wgroup.long 0x410++0x3 line.long 0x0 "DSI_WIFCR,DSI wrapper interrupt flag clear register" bitfld.long 0x0 13. "CRRIF,CRRIF" "0,1" bitfld.long 0x0 10. "CPLLUIF,CPLLUIF" "0,1" bitfld.long 0x0 9. "CPLLLIF,CPLLLIF" "0,1" bitfld.long 0x0 1. "CERIF,CERIF" "0,1" bitfld.long 0x0 0. "CTEIF,CTEIF" "0,1" group.long 0x418++0x7 line.long 0x0 "DSI_WPCR0,DSI wrapper PHY configuration register 0" bitfld.long 0x0 16. "TDDL,TDDL" "0,1" bitfld.long 0x0 14. "CDOFFDL,CDOFFDL" "0,1" bitfld.long 0x0 13. "FTXSMDL,FTXSMDL" "0,1" bitfld.long 0x0 12. "FTXSMCL,FTXSMCL" "0,1" bitfld.long 0x0 11. "HSIDL1,HSIDL1" "0,1" bitfld.long 0x0 10. "HSIDL0,HSIDL0" "0,1" bitfld.long 0x0 9. "HSICL,HSICL" "0,1" newline bitfld.long 0x0 8. "SWDL1,SWDL1" "0,1" bitfld.long 0x0 7. "SWDL0,SWDL0" "0,1" bitfld.long 0x0 6. "SWCL,SWCL" "0,1" hexmask.long.byte 0x0 0.--5. 1. "UIX4,UIX4" line.long 0x4 "DSI_WPCR1,This register shall be programmed only when DSI is stopped (CR. DSIEN=0 and CR.EN = 0)." bitfld.long 0x4 19. "HSTXSRDDL,HSTXSRDDL" "0,1" bitfld.long 0x4 18. "HSTXSRUDL,HSTXSRUDL" "0,1" bitfld.long 0x4 17. "HSTXSRDCL,HSTXSRDCL" "0,1" bitfld.long 0x4 16. "HSTXSRUCL,HSTXSRUCL" "0,1" bitfld.long 0x4 13. "SDDCDL,SDDCDL" "0,1" bitfld.long 0x4 12. "SDDCCL,SDDCCL" "0,1" bitfld.long 0x4 8.--9. "LPTXSRDL,LPTXSRDL" "0,1,2,3" newline bitfld.long 0x4 6.--7. "LPTXSRCL,LPTXSRCL" "0,1,2,3" bitfld.long 0x4 2.--3. "SKEWDL,SKEWDL" "0,1,2,3" bitfld.long 0x4 0.--1. "SKEWCL,SKEWCL" "0,1,2,3" group.long 0x430++0x3 line.long 0x0 "DSI_WRPCR,DSI wrapper regulator and PLL control register" bitfld.long 0x0 28. "BGREN,BGREN" "0,1" bitfld.long 0x0 24. "REGEN,REGEN" "0,1" bitfld.long 0x0 16.--17. "ODF,ODF" "0,1,2,3" hexmask.long.byte 0x0 11.--14. 1. "IDF,IDF" hexmask.long.byte 0x0 2.--8. 1. "NDIV,NDIV" bitfld.long 0x0 0. "PLLEN,PLLEN" "0,1" rgroup.long 0x7F0++0xF line.long 0x0 "DSI_HWCFGR,DSI Host hardware configuration register" hexmask.long.word 0x0 4.--15. 1. "FIFOSIZE,FIFOSIZE" hexmask.long.byte 0x0 0.--3. 1. "TECHNO,TECHNO" line.long 0x4 "DSI_VERR,DSI Host version register" hexmask.long.byte 0x4 4.--7. 1. "MAJREV,MAJREV" hexmask.long.byte 0x4 0.--3. 1. "MINREV,MINREV" line.long 0x8 "DSI_IPIDR,DSI Host identification register" hexmask.long 0x8 0.--31. 1. "ID,ID" line.long 0xC "DSI_SIDR,DSI Host size identification register" hexmask.long 0xC 0.--31. 1. "SID,SID" tree.end endif tree "DTS (Digital Temperature Sensor)" base ad:0x50028000 group.long 0x0++0x3 line.long 0x0 "DTS_CFGR1,DTS_CFGR1 is the configuration register for temperature sensor 1." hexmask.long.byte 0x0 24.--30. 1. "HSREF_CLK_DIV,HSREF_CLK_DIV" bitfld.long 0x0 21. "Q_MEAS_opt,Q_MEAS_opt" "0,1" bitfld.long 0x0 20. "REFCLK_SEL,REFCLK_SEL" "0,1" hexmask.long.byte 0x0 16.--19. 1. "TS1_SMP_TIME,TS1_SMP_TIME" hexmask.long.byte 0x0 8.--11. 1. "TS1_INTRIG_SEL,TS1_INTRIG_SEL" bitfld.long 0x0 4. "TS1_START,TS1_START" "0,1" newline bitfld.long 0x0 0. "TS1_EN,TS1_EN" "0,1" rgroup.long 0x8++0x3 line.long 0x0 "DTS_T0VALR1,DTS_T0VALR1 contains the value of the factory calibration temperature (T0) for temperature sensor 1. The system reset value is factory trimmed." bitfld.long 0x0 16.--17. "TS1_T0,TS1_T0" "0,1,2,3" hexmask.long.word 0x0 0.--15. 1. "TS1_FMT0,TS1_FMT0" rgroup.long 0x10++0x3 line.long 0x0 "DTS_RAMPVALR,The DTS_RAMPVALR is the ramp coefficient for the temperature sensor. The system reset value is factory trimmed." hexmask.long.word 0x0 0.--15. 1. "TS1_RAMP_COEFF,TS1_RAMP_COEFF" group.long 0x14++0x3 line.long 0x0 "DTS_ITR1,DTS_ITR1 contains the threshold values for sensor 1." hexmask.long.word 0x0 16.--31. 1. "TS1_HITTHD,TS1_HITTHD" hexmask.long.word 0x0 0.--15. 1. "TS1_LITTHD,TS1_LITTHD" group.long 0x1C++0x3 line.long 0x0 "DTS_DR,The DTS_DR contains the number of REF_CLK cycles used to compute the FM(T) frequency." hexmask.long.word 0x0 0.--15. 1. "TS1_MFREQ,TS1_MFREQ" rgroup.long 0x20++0x3 line.long 0x0 "DTS_SR,Temperature sensor status register" bitfld.long 0x0 15. "TS1_RDY,TS1_RDY" "0,1" bitfld.long 0x0 6. "TS1_AITHF,TS1_AITHF" "0,1" bitfld.long 0x0 5. "TS1_AITLF,TS1_AITLF" "0,1" bitfld.long 0x0 4. "TS1_AITEF,TS1_AITEF" "0,1" bitfld.long 0x0 2. "TS1_ITHF,TS1_ITHF" "0,1" bitfld.long 0x0 1. "TS1_ITLF,TS1_ITLF" "0,1" newline bitfld.long 0x0 0. "TS1_ITEF,TS1_ITEF" "0,1" group.long 0x24++0xB line.long 0x0 "DTS_ITENR,Temperature sensor interrupt enable register" bitfld.long 0x0 6. "TS1_AITHEN,TS1_AITHEN" "0,1" bitfld.long 0x0 5. "TS1_AITLEN,TS1_AITLEN" "0,1" bitfld.long 0x0 4. "TS1_AITEEN,TS1_AITEEN" "0,1" bitfld.long 0x0 2. "TS1_ITHEN,TS1_ITHEN" "0,1" bitfld.long 0x0 1. "TS1_ITLEN,TS1_ITLEN" "0,1" bitfld.long 0x0 0. "TS1_ITEEN,TS1_ITEEN" "0,1" line.long 0x4 "DTS_ICIFR,DTS_ICIFR is the control register for the interrupt flags." bitfld.long 0x4 6. "TS1_CAITHF,TS1_CAITHF" "0,1" bitfld.long 0x4 5. "TS1_CAITLF,TS1_CAITLF" "0,1" bitfld.long 0x4 4. "TS1_CAITEF,TS1_CAITEF" "0,1" bitfld.long 0x4 2. "TS1_CITHF,TS1_CITHF" "0,1" bitfld.long 0x4 1. "TS1_CITLF,TS1_CITLF" "0,1" bitfld.long 0x4 0. "TS1_CITEF,TS1_CITEF" "0,1" line.long 0x8 "DTS_OR,The DTS_OR contains general-purpose option bits." bitfld.long 0x8 31. "TS_Op31,TS_Op31" "0,1" bitfld.long 0x8 30. "TS_Op30,TS_Op30" "0,1" bitfld.long 0x8 29. "TS_Op29,TS_Op29" "0,1" bitfld.long 0x8 28. "TS_Op28,TS_Op28" "0,1" bitfld.long 0x8 27. "TS_Op27,TS_Op27" "0,1" bitfld.long 0x8 26. "TS_Op26,TS_Op26" "0,1" newline bitfld.long 0x8 25. "TS_Op25,TS_Op25" "0,1" bitfld.long 0x8 24. "TS_Op24,TS_Op24" "0,1" bitfld.long 0x8 23. "TS_Op23,TS_Op23" "0,1" bitfld.long 0x8 22. "TS_Op22,TS_Op22" "0,1" bitfld.long 0x8 21. "TS_Op21,TS_Op21" "0,1" bitfld.long 0x8 20. "TS_Op20,TS_Op20" "0,1" newline bitfld.long 0x8 19. "TS_Op19,TS_Op19" "0,1" bitfld.long 0x8 18. "TS_Op18,TS_Op18" "0,1" bitfld.long 0x8 17. "TS_Op17,TS_Op17" "0,1" bitfld.long 0x8 16. "TS_Op16,TS_Op16" "0,1" bitfld.long 0x8 15. "TS_Op15,TS_Op15" "0,1" bitfld.long 0x8 14. "TS_Op14,TS_Op14" "0,1" newline bitfld.long 0x8 13. "TS_Op13,TS_Op13" "0,1" bitfld.long 0x8 12. "TS_Op12,TS_Op12" "0,1" bitfld.long 0x8 11. "TS_Op11,TS_Op11" "0,1" bitfld.long 0x8 10. "TS_Op10,TS_Op10" "0,1" bitfld.long 0x8 9. "TS_Op9,TS_Op9" "0,1" bitfld.long 0x8 8. "TS_Op8,TS_Op8" "0,1" newline bitfld.long 0x8 7. "TS_Op7,TS_Op7" "0,1" bitfld.long 0x8 6. "TS_Op6,TS_Op6" "0,1" bitfld.long 0x8 5. "TS_Op5,TS_Op5" "0,1" bitfld.long 0x8 4. "TS_Op4,TS_Op4" "0,1" bitfld.long 0x8 3. "TS_Op3,TS_Op3" "0,1" bitfld.long 0x8 2. "TS_Op2,TS_Op2" "0,1" newline bitfld.long 0x8 1. "TS_Op1,TS_Op1" "0,1" bitfld.long 0x8 0. "TS_Op0,TS_Op0" "0,1" tree.end tree "ETH (Ethernet)" base ad:0x0 sif (cpuis("STM32MP13*")) tree "ETH1" base ad:0x5800A000 group.long 0x0++0x17 line.long 0x0 "ETH_MACCR,Operating mode configuration register" bitfld.long 0x0 31. "ARPEN,ARP Offload Enable" "0,1" newline bitfld.long 0x0 28.--30. "SARC,Source Address Insertion or Replacement Control" "0: Reserved must not be used,1: Reserved must not be used.,2: the MAC inserts the content of the MAC Address 0..,3: the MAC replaces the content of the MAC Address..,4: Reserved must not be used,5: Reserved must not be used.,6: the MAC inserts the content of the MAC Address 1..,7: the MAC replaces the content of the MAC Address.." newline bitfld.long 0x0 27. "IPC,Checksum Offload" "0,1" newline bitfld.long 0x0 24.--26. "IPG,Inter-Packet Gap" "0: 96 bit times,1: 88 bit times,2: 80 bit times,?,?,?,?,7: 40 bit times" newline bitfld.long 0x0 23. "GPSLCE,Giant Packet Size Limit Control Enable" "0,1" newline bitfld.long 0x0 22. "S2KP,IEEE 802.3as Support for 2K Packets" "0,1" newline bitfld.long 0x0 21. "CST,CRC stripping for Type packets" "0,1" newline bitfld.long 0x0 20. "ACS,Automatic Pad or CRC Stripping" "0,1" newline bitfld.long 0x0 19. "WD,Watchdog Disable" "0,1" newline bitfld.long 0x0 18. "BE,Packet Burst Enable" "0,1" newline bitfld.long 0x0 17. "JD,Jabber Disable" "0,1" newline bitfld.long 0x0 16. "JE,Jumbo Packet Enable" "0,1" newline bitfld.long 0x0 15. "PS,Port Select" "0: For 1000 Mbps operations,1: For 10 or 100 Mbps operations" newline bitfld.long 0x0 14. "FES,MAC Speed" "0: 10 Mbps,1: 100 Mbps" newline bitfld.long 0x0 13. "DM,Duplex Mode" "0,1" newline bitfld.long 0x0 12. "LM,Loopback Mode" "0,1" newline bitfld.long 0x0 11. "ECRSFD,Enable Carrier Sense Before Transmission in Full-Duplex Mode" "0,1" newline bitfld.long 0x0 10. "DO,Disable Receive Own" "0,1" newline bitfld.long 0x0 9. "DCRS,Disable Carrier Sense During Transmission" "0,1" newline bitfld.long 0x0 8. "DR,Disable Retry" "0,1" newline bitfld.long 0x0 5.--6. "BL,Back-Off Limit" "0: k= min (n 10),1: k = min (n 8),2: k = min (n 4),3: k = min (n 1)" newline bitfld.long 0x0 4. "DC,Deferral Check" "0,1" newline bitfld.long 0x0 2.--3. "PRELEN,Preamble Length for Transmit packets" "0: 7 bytes of preamble,1: 5 bytes of preamble,2: 3 bytes of preamble,3: Reserved must not be used" newline bitfld.long 0x0 1. "TE,Transmitter Enable" "0,1" newline bitfld.long 0x0 0. "RE,Receiver Enable" "0,1" line.long 0x4 "ETH_MACECR,Extended operating mode configuration register" hexmask.long.byte 0x4 25.--29. 1. "EIPG,Extended Inter-Packet Gap" newline bitfld.long 0x4 24. "EIPGEN,Extended Inter-Packet Gap Enable" "0,1" newline bitfld.long 0x4 18. "USP,Unicast Slow Protocol Packet Detect" "0,1" newline bitfld.long 0x4 17. "SPEN,Slow Protocol Detection Enable" "0,1" newline bitfld.long 0x4 16. "DCRCC,Disable CRC Checking for Received Packets" "0,1" newline hexmask.long.word 0x4 0.--13. 1. "GPSL,Giant Packet Size Limit" line.long 0x8 "ETH_MACPFR,Packet filtering control register" bitfld.long 0x8 31. "RA,Receive All" "0,1" newline bitfld.long 0x8 21. "DNTU,Drop Non-TCP/UDP over IP Packets" "0,1" newline bitfld.long 0x8 20. "IPFE,Layer 3 and Layer 4 Filter Enable" "0,1" newline bitfld.long 0x8 16. "VTFE,VLAN Tag Filter Enable" "0,1" newline bitfld.long 0x8 10. "HPF,Hash or Perfect Filter" "0,1" newline bitfld.long 0x8 9. "SAF,Source Address Filter Enable" "0,1" newline bitfld.long 0x8 8. "SAIF,SA Inverse Filtering" "0,1" newline bitfld.long 0x8 6.--7. "PCF,Pass Control Packets" "0: The MAC filters all control packets from..,1: The MAC forwards all control packets except..,2: The MAC forwards all control packets to the..,3: The MAC forwards the control packets that pass.." newline bitfld.long 0x8 5. "DBF,Disable Broadcast Packets" "0,1" newline bitfld.long 0x8 4. "PM,Pass All Multicast" "0,1" newline bitfld.long 0x8 3. "DAIF,DA Inverse Filtering" "0,1" newline bitfld.long 0x8 2. "HMC,Hash Multicast" "0,1" newline bitfld.long 0x8 1. "HUC,Hash Unicast" "0,1" newline bitfld.long 0x8 0. "PR,Promiscuous Mode" "0,1" line.long 0xC "ETH_MACWTR,Watchdog timeout register" bitfld.long 0xC 8. "PWE,Programmable Watchdog Enable" "0,1" newline hexmask.long.byte 0xC 0.--3. 1. "WTO,Watchdog Timeout" line.long 0x10 "ETH_MACHT0R,Hash Table 0 register" hexmask.long 0x10 0.--31. 1. "HT31T0,MAC Hash Table First 32 Bits" line.long 0x14 "ETH_MACHT1R,Hash Table 1 register" hexmask.long 0x14 0.--31. 1. "HT63T32,MAC Hash Table Second 32 Bits" group.long 0x50++0x3 line.long 0x0 "ETH_MACVTR,VLAN tag register" bitfld.long 0x0 31. "EIVLRXS,Enable Inner VLAN Tag in Rx Status" "0,1" newline bitfld.long 0x0 28.--29. "EIVLS,Enable Inner VLAN Tag Stripping on Receive" "0: Do not strip,1: Strip if VLAN filter passes,2: Strip if VLAN filter fails,3: Always strip" newline bitfld.long 0x0 27. "ERIVLT,Enable Inner VLAN Tag" "0,1" newline bitfld.long 0x0 26. "EDVLP,Enable Double VLAN Processing" "0,1" newline bitfld.long 0x0 25. "VTHM,VLAN Tag Hash Table Match Enable" "0,1" newline bitfld.long 0x0 24. "EVLRXS,Enable VLAN Tag in Rx status" "0,1" newline bitfld.long 0x0 21.--22. "EVLS,Enable VLAN Tag Stripping on Receive" "0: Do not strip,1: Strip if VLAN filter passes,2: Strip if VLAN filter fails,3: Always strip" newline bitfld.long 0x0 20. "DOVLTC,Disable VLAN Type Check" "0,1" newline bitfld.long 0x0 19. "ERSVLM,Enable Receive S-VLAN Match" "0,1" newline bitfld.long 0x0 18. "ESVL,Enable S-VLAN" "0,1" newline bitfld.long 0x0 17. "VTIM,VLAN Tag Inverse Match Enable" "0,1" newline bitfld.long 0x0 16. "ETV,Enable 12-Bit VLAN Tag Comparison" "0,1" newline hexmask.long.word 0x0 0.--15. 1. "VL,VLAN Tag Identifier for Receive Packets" group.long 0x58++0x3 line.long 0x0 "ETH_MACVHTR,VLAN Hash table register" hexmask.long.word 0x0 0.--15. 1. "VLHT,VLAN Hash Table" group.long 0x60++0x7 line.long 0x0 "ETH_MACVIR,VLAN inclusion register" bitfld.long 0x0 20. "VLTI,VLAN Tag Input" "0,1" newline bitfld.long 0x0 19. "CSVL,C-VLAN or S-VLAN" "0,1" newline bitfld.long 0x0 18. "VLP,VLAN Priority Control" "0,1" newline bitfld.long 0x0 16.--17. "VLC,VLAN Tag Control in Transmit Packets" "0: No VLAN tag deletion insertion or replacement,1: VLAN tag deletion. The MAC removes the VLAN type..,2: VLAN tag insertion. The MAC inserts VLT in bytes..,3: VLAN tag replacement. The MAC replaces VLT in.." newline hexmask.long.word 0x0 0.--15. 1. "VLT,VLAN Tag for Transmit Packets" line.long 0x4 "ETH_MACIVIR,Inner VLAN inclusion register" bitfld.long 0x4 20. "VLTI,VLAN Tag Input" "0,1" newline bitfld.long 0x4 19. "CSVL,C-VLAN or S-VLAN" "0,1" newline bitfld.long 0x4 18. "VLP,VLAN Priority Control" "0,1" newline bitfld.long 0x4 16.--17. "VLC,VLAN Tag Control in Transmit Packets" "0: No VLAN tag deletion insertion or replacement,1: VLAN tag deletion,2: VLAN tag insertion,3: VLAN tag replacement" newline hexmask.long.word 0x4 0.--15. 1. "VLT,VLAN Tag for Transmit Packets" group.long 0x70++0x3 line.long 0x0 "ETH_MACQ0TXFCR,Tx Queue 0 flow control register" hexmask.long.word 0x0 16.--31. 1. "PT,Pause Time" newline bitfld.long 0x0 7. "DZPQ,Disable Zero-Quanta Pause" "0,1" newline bitfld.long 0x0 4.--6. "PLT,Pause Low Threshold" "0: Pause Time minus 4 Slot Times (PT -4 slot times),1: Pause Time minus 28 Slot Times (PT -28 slot times),2: Pause Time minus 36 Slot Times (PT -36 slot times),3: Pause Time minus 144 Slot Times (PT -144 slot..,4: Pause Time minus 256 Slot Times (PT -256 slot..,5: Pause Time minus 512 Slot Times (PT -512 slot..,6: Reserved must not be used,7: Reserved must not be used" newline bitfld.long 0x0 1. "TFE,Transmit Flow Control Enable" "0,1" newline bitfld.long 0x0 0. "FCB_BPA,Flow Control Busy or Backpressure Activate" "0,1" group.long 0x90++0x3 line.long 0x0 "ETH_MACRXFCR,Rx flow control register" bitfld.long 0x0 1. "UP,Unicast Pause Packet Detect" "0,1" newline bitfld.long 0x0 0. "RFE,Receive Flow Control Enable" "0,1" rgroup.long 0x98++0x3 line.long 0x0 "ETH_MACTXQPMR,Tx queue priority mapping 0 register" hexmask.long.byte 0x0 8.--15. 1. "PSTQ1,Priorities Selected in Transmit Queue 1" newline hexmask.long.byte 0x0 0.--7. 1. "PSTQ0,Priorities Selected in Transmit Queue 0" group.long 0xA8++0x3 line.long 0x0 "ETH_MACRXQC2R,Rx queue control 2 register" hexmask.long.byte 0x0 8.--15. 1. "PSRQ1,Priorities Selected in the Receive Queue 1" newline hexmask.long.byte 0x0 0.--7. 1. "PSRQ0,Priorities Selected in the Receive Queue 0" rgroup.long 0xB0++0x3 line.long 0x0 "ETH_MACISR,Interrupt status register" bitfld.long 0x0 14. "RXSTSIS,Receive Status Interrupt" "0,1" newline bitfld.long 0x0 13. "TXSTSIS,Transmit Status Interrupt" "0,1" newline bitfld.long 0x0 12. "TSIS,Timestamp Interrupt Status" "0,1" newline bitfld.long 0x0 10. "MMCTXIS,MMC Transmit Interrupt Status" "0,1" newline bitfld.long 0x0 9. "MMCRXIS,MMC Receive Interrupt Status" "0,1" newline bitfld.long 0x0 8. "MMCIS,MMC Interrupt Status" "0,1" newline bitfld.long 0x0 5. "LPIIS,LPI Interrupt Status" "0,1" newline bitfld.long 0x0 4. "PMTIS,PMT Interrupt Status" "0,1" newline bitfld.long 0x0 3. "PHYIS,PHY Interrupt" "0,1" newline bitfld.long 0x0 0. "RGSMIIIS,RGMII or SMII Interrupt Status" "0,1" group.long 0xB4++0x3 line.long 0x0 "ETH_MACIER,Interrupt enable register" bitfld.long 0x0 14. "RXSTSIE,Receive Status Interrupt Enable" "0,1" newline bitfld.long 0x0 13. "TXSTSIE,Transmit Status Interrupt Enable" "0,1" newline bitfld.long 0x0 12. "TSIE,Timestamp Interrupt Enable" "0,1" newline bitfld.long 0x0 5. "LPIIE,LPI Interrupt Enable" "0,1" newline bitfld.long 0x0 4. "PMTIE,PMT Interrupt Enable" "0,1" newline bitfld.long 0x0 3. "PHYIE,PHY Interrupt Enable" "0,1" newline bitfld.long 0x0 0. "RGSMIIIE,RGMII or SMII Interrupt Enable" "0,1" rgroup.long 0xB8++0x3 line.long 0x0 "ETH_MACRXTXSR,Rx Tx status register" bitfld.long 0x0 8. "RWT,Receive Watchdog Timeout" "0,1" newline bitfld.long 0x0 5. "EXCOL,Excessive Collisions" "0,1" newline bitfld.long 0x0 4. "LCOL,Late Collision" "0,1" newline bitfld.long 0x0 3. "EXDEF,Excessive Deferral" "0,1" newline bitfld.long 0x0 2. "LCARR,Loss of Carrier" "0,1" newline bitfld.long 0x0 1. "NCARR,No Carrier" "0,1" newline bitfld.long 0x0 0. "TJT,Transmit Jabber Timeout" "0,1" group.long 0xC0++0x7 line.long 0x0 "ETH_MACPCSR," bitfld.long 0x0 31. "RWKFILTRST,Remote wakeup Packet Filter Register Pointer Reset" "0,1" newline hexmask.long.byte 0x0 24.--28. 1. "RWKPTR,Remote wakeup FIFO Pointer" newline bitfld.long 0x0 10. "RWKPFE,Remote wakeup Packet Forwarding Enable" "0,1" newline bitfld.long 0x0 9. "GLBLUCAST,Global Unicast" "0,1" newline rbitfld.long 0x0 6. "RWKPRCVD,Remote wakeup Packet Received" "0,1" newline rbitfld.long 0x0 5. "MGKPRCVD,Magic Packet Received" "0,1" newline bitfld.long 0x0 2. "RWKPKTEN,Remote wakeup Packet Enable" "0,1" newline bitfld.long 0x0 1. "MGKPKTEN,Magic Packet Enable" "0,1" newline bitfld.long 0x0 0. "PWRDWN,Power Down" "0,1" line.long 0x4 "ETH_MACRWKPFR," hexmask.long 0x4 0.--31. 1. "MACRWKPFR,Remote wakeup packet filter" group.long 0xD0++0xF line.long 0x0 "ETH_MACLCSR,LPI control status register" bitfld.long 0x0 20. "LPITE,LPI Timer Enable" "0,1" newline bitfld.long 0x0 19. "LPITXA,LPI Tx Automate" "0,1" newline bitfld.long 0x0 18. "PLSEN,PHY Link Status Enable" "0,1" newline bitfld.long 0x0 17. "PLS,PHY Link Status" "0,1" newline bitfld.long 0x0 16. "LPIEN,LPI Enable" "0,1" newline rbitfld.long 0x0 9. "RLPIST,Receive LPI State" "0,1" newline rbitfld.long 0x0 8. "TLPIST,Transmit LPI State" "0,1" newline rbitfld.long 0x0 3. "RLPIEX,Receive LPI Exit" "0,1" newline rbitfld.long 0x0 2. "RLPIEN,Receive LPI Entry" "0,1" newline rbitfld.long 0x0 1. "TLPIEX,Transmit LPI Exit" "0,1" newline rbitfld.long 0x0 0. "TLPIEN,Transmit LPI Entry" "0,1" line.long 0x4 "ETH_MACLTCR,LPI timers control register" hexmask.long.word 0x4 16.--25. 1. "LST,LPI LS Timer" newline hexmask.long.word 0x4 0.--15. 1. "TWT,LPI TW Timer" line.long 0x8 "ETH_MACLETR,LPI entry timer register" hexmask.long.tbyte 0x8 3.--19. 1. "LPIET,LPI Entry Timer" line.long 0xC "ETH_MAC1USTCR,FIXME 1-microsecond-tick counter register" hexmask.long.word 0xC 0.--11. 1. "TIC_1US_CNTR,1 µs tick Counter" group.long 0xF8++0x3 line.long 0x0 "ETH_MACPHYCSR,PHYIF control status register" rbitfld.long 0x0 20. "JABTO,Jabber Timeout" "0,1" newline rbitfld.long 0x0 19. "LNKSTS,Link Status" "0,1" newline rbitfld.long 0x0 17.--18. "LNKSPEED,Link Speed" "0: 2.5 MHz,1: 25 MHz,2: 125 MHz,?" newline rbitfld.long 0x0 16. "LNKMOD,Link Mode" "0: Half-duplex mode,1: Full-duplex mode" newline bitfld.long 0x0 1. "LUD,Link Up or Down" "0: Link Down,1: Link Up" newline bitfld.long 0x0 0. "TC,Transmit Configuration in RGMII" "0,1" rgroup.long 0x110++0x7 line.long 0x0 "ETH_MACVR,Version register" hexmask.long.byte 0x0 8.--15. 1. "USERVER,ST-defined version" newline hexmask.long.byte 0x0 0.--7. 1. "SNPSVER,IP version" line.long 0x4 "ETH_MACDR,Debug register" bitfld.long 0x4 17.--18. "TFCSTS,MAC Transmit Packet Controller Status" "0: Idle state,1: Waiting for one of the following:,2: Generating and transmitting a Pause control..,3: Transferring input packet for transmission" newline bitfld.long 0x4 16. "TPESTS,MAC GMII or MII Transmit Protocol Engine Status" "0,1" newline bitfld.long 0x4 1.--2. "RFCFCSTS,MAC Receive Packet Controller FIFO Status" "0,1,2,3" newline bitfld.long 0x4 0. "RPESTS,MAC GMII or MII Receive Protocol Engine Status" "0,1" rgroup.long 0x11C++0xB line.long 0x0 "ETH_MACHWF0R,HW feature 0 register" bitfld.long 0x0 28.--30. "ACTPHYSEL,Active PHY Selected" "0: GMII or MII,1: RGMII,2: SGMII,3: TBI,4: RMII,5: RTBI,6: SMII,?" newline bitfld.long 0x0 27. "SAVLANINS,Source Address or VLAN Insertion Enable" "0,1" newline bitfld.long 0x0 25.--26. "TSSTSSEL,Timestamp System Time Source" "0: Reserved must not be used,1: Internal,2: External,3: Both" newline bitfld.long 0x0 24. "MACADR64SEL,MAC Addresses 64-127 Selected" "0,1" newline bitfld.long 0x0 23. "MACADR32SEL,MAC Addresses 32-63 Selected" "0,1" newline hexmask.long.byte 0x0 18.--22. 1. "ADDMACADRSEL,MAC Addresses 1-31 Selected" newline bitfld.long 0x0 16. "RXCOESEL,Receive Checksum Offload Enabled" "0,1" newline bitfld.long 0x0 14. "TXCOESEL,Transmit Checksum Offload Enabled" "0,1" newline bitfld.long 0x0 13. "EEESEL,Energy Efficient Ethernet Enabled" "0,1" newline bitfld.long 0x0 12. "TSSEL,IEEE 1588-2008 Timestamp Enabled" "0,1" newline bitfld.long 0x0 9. "ARPOFFSEL,ARP Offload Enabled" "0,1" newline bitfld.long 0x0 8. "MMCSEL,RMON Module Enable" "0,1" newline bitfld.long 0x0 7. "MGKSEL,PMT Magic Packet Enable" "0,1" newline bitfld.long 0x0 6. "RWKSEL,PMT Remote Wakeup Packet Enable" "0,1" newline bitfld.long 0x0 5. "SMASEL,SMA (MDIO) Interface" "0,1" newline bitfld.long 0x0 4. "VLHASH,VLAN Hash Filter Selected" "0,1" newline bitfld.long 0x0 3. "PCSSEL,PCS Registers (TBI SGMII or RTBI PHY interface)" "0,1" newline bitfld.long 0x0 2. "HDSEL,Half-duplex Support" "0,1" newline bitfld.long 0x0 1. "GMIISEL,1000 Mbps Support" "0,1" newline bitfld.long 0x0 0. "MIISEL,10 or 100 Mbps Support" "0,1" line.long 0x4 "ETH_MACHWF1R,HW feature 1 register" hexmask.long.byte 0x4 27.--30. 1. "L3L4FNUM,Total number of L3 or L4 Filters" newline bitfld.long 0x4 24.--25. "HASHTBLSZ,Hash Table Size" "0: No Hash table,1: 64,2: 128,3: 256" newline bitfld.long 0x4 20. "AVSEL,AV Feature Enable" "0,1" newline bitfld.long 0x4 19. "DBGMEMA,DMA Debug Registers Enable" "0,1" newline bitfld.long 0x4 18. "TSOEN,TCP Segmentation Offload Enable" "0,1" newline bitfld.long 0x4 17. "SPHEN,Split Header Feature Enable" "0,1" newline bitfld.long 0x4 16. "DCBEN,DCB Feature Enable" "0,1" newline bitfld.long 0x4 14.--15. "ADDR64,Address width" "0: 32 bits,?,?,?" newline bitfld.long 0x4 13. "ADVTHWORD,IEEE 1588 High Word Register Enable" "0,1" newline bitfld.long 0x4 12. "PTOEN,PTP Offload Enable" "0,1" newline bitfld.long 0x4 11. "OSTEN,One-Step Timestamping Enable" "0,1" newline hexmask.long.byte 0x4 6.--10. 1. "TXFIFOSIZE,MTL Transmit FIFO Size" newline hexmask.long.byte 0x4 0.--4. 1. "RXFIFOSIZE,MTL Receive FIFO Size" line.long 0x8 "ETH_MACHWF2R,HW feature 2 register" bitfld.long 0x8 28.--30. "AUXSNAPNUM,Number of Auxiliary Snapshot Inputs" "0: No auxiliary input,1: 1 auxiliary input,2: 2 auxiliary inputs,3: 3 auxiliary inputs,4: 4 auxiliary inputs,5: Reserved must not be used,6: Reserved must not be used,7: Reserved must not be used" newline bitfld.long 0x8 24.--26. "PPSOUTNUM,Number of PPS Outputs" "0: No PPS output,1: 1 PPS output,2: 2 PPS outputs,3: 3 PPS outputs,4: 4 PPS outputs,5: Reserved must not be used,6: Reserved must not be used,7: Reserved must not be used" newline hexmask.long.byte 0x8 18.--21. 1. "TXCHCNT,Number of DMA Transmit Channels" newline hexmask.long.byte 0x8 12.--15. 1. "RXCHCNT,Number of DMA Receive Channels" newline hexmask.long.byte 0x8 6.--9. 1. "TXQCNT,Number of MTL Transmit Queues" newline hexmask.long.byte 0x8 0.--3. 1. "RXQCNT,Number of MTL Receive Queues" group.long 0x128++0x3 line.long 0x0 "ETH_MACHWF3R,HW feature 3 register" bitfld.long 0x0 5. "DVLAN,Number of auxiliary snapshot inputs" "0,1" newline bitfld.long 0x0 4. "CBTISEL,Queue/Channel based VLAN tag insertion on Tx enable" "0,1" newline rbitfld.long 0x0 0.--2. "NRVF,Number of Extended VLAN Tag Filters Enabled" "0: No Extended Rx VLAN Filters,1: 4 Extended Rx VLAN Filters,2: 8 Extended Rx VLAN Filters,3: 16 Extended Rx VLAN Filters,4: 24 Extended Rx VLAN Filters,5: 32 Extended Rx VLAN Filters,6: Reserved must not be used,7: Reserved must not be used" group.long 0x200++0x7 line.long 0x0 "ETH_MACMDIOAR,MDIO address register" bitfld.long 0x0 27. "PSE,Preamble Suppression Enable" "0,1" newline bitfld.long 0x0 26. "BTB,Back to Back transactions" "0,1" newline hexmask.long.byte 0x0 21.--25. 1. "PA,Physical Layer Address" newline hexmask.long.byte 0x0 16.--20. 1. "RDA,Register/Device Address" newline bitfld.long 0x0 12.--14. "NTC,Number of Training Clocks" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 8.--11. 1. "CR,CSR Clock Range" newline bitfld.long 0x0 4. "SKAP,Skip Address Packet" "0,1" newline bitfld.long 0x0 2.--3. "GOC,GMII Operation Command" "0: Reserved must not be used,1: Write,2: Post Read Increment Address for Clause 45 PHY,3: Read" newline bitfld.long 0x0 1. "C45E,Clause 45 PHY Enable" "0,1" newline bitfld.long 0x0 0. "GB,GMII Busy" "0,1" line.long 0x4 "ETH_MACMDIODR,MDIO data register" hexmask.long.word 0x4 16.--31. 1. "RA,Register Address" newline hexmask.long.word 0x4 0.--15. 1. "GD,GMII Data" group.long 0x210++0x3 line.long 0x0 "ETH_MACARPAR,ARP address register" hexmask.long 0x0 0.--31. 1. "ARPPA,ARP Protocol Address" group.long 0x230++0x3 line.long 0x0 "ETH_MACCSRSWCR,CSR software control register" bitfld.long 0x0 8. "SEEN,Slave Error Response Enable" "0,1" newline bitfld.long 0x0 0. "RCWE,Register Clear on Write 1 Enable" "0,1" group.long 0x300++0x1F line.long 0x0 "ETH_MACA0HR,Address 0 high register" rbitfld.long 0x0 31. "AE,Address Enable" "0,1" newline hexmask.long.word 0x0 0.--15. 1. "ADDRHI,MAC Address0[47:32]" line.long 0x4 "ETH_MACA0LR,Address 0 low register" hexmask.long 0x4 0.--31. 1. "ADDRLO,MAC Address x [31:0] (x = 0 to 3)" line.long 0x8 "ETH_MACA1HR,Address 1 high register" bitfld.long 0x8 31. "AE,Address Enable" "0,1" newline bitfld.long 0x8 30. "SA,Source Address" "0,1" newline hexmask.long.byte 0x8 24.--29. 1. "MBC,Mask Byte Control" newline hexmask.long.word 0x8 0.--15. 1. "ADDRHI,MAC Address1 [47:32]" line.long 0xC "ETH_MACA1LR,Address 1 low register" hexmask.long 0xC 0.--31. 1. "ADDRLO,MAC Address x [31:0] (x = 0 to 3)" line.long 0x10 "ETH_MACA2HR,Address 2 high register" bitfld.long 0x10 31. "AE,Address Enable" "0,1" newline bitfld.long 0x10 30. "SA,Source Address" "0,1" newline hexmask.long.byte 0x10 24.--29. 1. "MBC,Mask Byte Control" newline hexmask.long.word 0x10 0.--15. 1. "ADDRHI,MAC Address1 [47:32]" line.long 0x14 "ETH_MACA2LR,Address 2 low register" hexmask.long 0x14 0.--31. 1. "ADDRLO,MAC Address x [31:0] (x = 0 to 3)" line.long 0x18 "ETH_MACA3HR,Address 3 high register" bitfld.long 0x18 31. "AE,Address Enable" "0,1" newline bitfld.long 0x18 30. "SA,Source Address" "0,1" newline hexmask.long.byte 0x18 24.--29. 1. "MBC,Mask Byte Control" newline hexmask.long.word 0x18 0.--15. 1. "ADDRHI,MAC Address1 [47:32]" line.long 0x1C "ETH_MACA3LR,Address 3 low register" hexmask.long 0x1C 0.--31. 1. "ADDRLO,MAC Address x [31:0] (x = 0 to 3)" group.long 0x700++0x3 line.long 0x0 "ETH_MMC_CONTROL,MMC control register" bitfld.long 0x0 8. "UCDBC,Update MMC Counters for Dropped Broadcast Packets" "0,1" newline bitfld.long 0x0 5. "CNTPRSTLVL,Full-Half Preset" "0,1" newline bitfld.long 0x0 4. "CNTPRST,Counters Preset" "0,1" newline bitfld.long 0x0 3. "CNTFREEZ,MMC Counter Freeze" "0,1" newline bitfld.long 0x0 2. "RSTONRD,Reset on Read" "0,1" newline bitfld.long 0x0 1. "CNTSTOPRO,Counter Stop Rollover" "0,1" newline bitfld.long 0x0 0. "CNTRST,Counters Reset" "0,1" rgroup.long 0x704++0x7 line.long 0x0 "ETH_MMC_RX_INTERRUPT,MMC Rx interrupt register" bitfld.long 0x0 27. "RXLPITRCIS,MMC Receive LPI transition counter interrupt status" "0,1" newline bitfld.long 0x0 26. "RXLPIUSCIS,MMC Receive LPI microsecond counter interrupt status" "0,1" newline bitfld.long 0x0 17. "RXUCGPIS,MMC Receive Unicast Good Packet Counter Interrupt Status" "0,1" newline bitfld.long 0x0 6. "RXALGNERPIS,MMC Receive Alignment Error Packet Counter Interrupt Status" "0,1" newline bitfld.long 0x0 5. "RXCRCERPIS,MMC Receive CRC Error Packet Counter Interrupt Status" "0,1" line.long 0x4 "ETH_MMC_TX_INTERRUPT,MMC Tx interrupt register" bitfld.long 0x4 27. "TXLPITRCIS,MMC Transmit LPI transition counter interrupt status" "0,1" newline bitfld.long 0x4 26. "TXLPIUSCIS,MMC Transmit LPI microsecond counter interrupt status" "0,1" newline bitfld.long 0x4 21. "TXGPKTIS,MMC Transmit Good Packet Counter Interrupt Status" "0,1" newline bitfld.long 0x4 15. "TXMCOLGPIS,MMC Transmit Multiple Collision Good Packet Counter Interrupt Status" "0,1" newline bitfld.long 0x4 14. "TXSCOLGPIS,MMC Transmit Single Collision Good Packet Counter Interrupt Status" "0,1" group.long 0x70C++0x7 line.long 0x0 "ETH_MMC_RX_INTERRUPT_MASK,MMC Rx interrupt mask register" rbitfld.long 0x0 27. "RXLPITRCIM,MMC Receive LPI transition counter interrupt Mask" "0,1" newline bitfld.long 0x0 26. "RXLPIUSCIM,MMC Receive LPI microsecond counter interrupt Mask" "0,1" newline bitfld.long 0x0 17. "RXUCGPIM,MMC Receive Unicast Good Packet Counter Interrupt Mask" "0,1" newline bitfld.long 0x0 6. "RXALGNERPIM,MMC Receive Alignment Error Packet Counter Interrupt Mask" "0,1" newline bitfld.long 0x0 5. "RXCRCERPIM,MMC Receive CRC Error Packet Counter Interrupt Mask" "0,1" line.long 0x4 "ETH_MMC_TX_INTERRUPT_MASK,MMC Tx interrupt mask register" rbitfld.long 0x4 27. "TXLPITRCIM,MMC Transmit LPI transition counter interrupt Mask" "0,1" newline bitfld.long 0x4 26. "TXLPIUSCIM,MMC Transmit LPI microsecond counter interrupt Mask" "0,1" newline bitfld.long 0x4 21. "TXGPKTIM,MMC Transmit Good Packet Counter Interrupt Mask" "0,1" newline bitfld.long 0x4 15. "TXMCOLGPIM,MMC Transmit Multiple Collision Good Packet Counter Interrupt Mask" "0,1" newline bitfld.long 0x4 14. "TXSCOLGPIM,MMC Transmit Single Collision Good Packet Counter Interrupt Mask" "0,1" rgroup.long 0x74C++0x7 line.long 0x0 "ETH_TX_SINGLE_COLLISION_GOOD_PACKETS,Tx single collision good packets register" hexmask.long 0x0 0.--31. 1. "TXSNGLCOLG,Tx Single Collision Good Packets" line.long 0x4 "ETH_TX_MULTIPLE_COLLISION_GOOD_PACKETS,Tx multiple collision good packets register" hexmask.long 0x4 0.--31. 1. "TXMULTCOLG,Tx Multiple Collision Good Packets" rgroup.long 0x768++0x3 line.long 0x0 "ETH_TX_PACKET_COUNT_GOOD,Tx packet count good register" hexmask.long 0x0 0.--31. 1. "TXPKTG,Tx Packet Count Good" rgroup.long 0x794++0x7 line.long 0x0 "ETH_RX_CRC_ERROR_PACKETS,Rx CRC error packets register" hexmask.long 0x0 0.--31. 1. "RXCRCERR,Rx CRC Error Packets" line.long 0x4 "ETH_RX_ALIGNMENT_ERROR_PACKETS,Rx alignment error packets register" hexmask.long 0x4 0.--31. 1. "RXALGNERR,Rx Alignment Error Packets" rgroup.long 0x7C4++0x3 line.long 0x0 "ETH_RX_UNICAST_PACKETS_GOOD,Rx unicast packets good register" hexmask.long 0x0 0.--31. 1. "RXUCASTG,Rx Unicast Packets Good" rgroup.long 0x7EC++0xF line.long 0x0 "ETH_TX_LPI_USEC_CNTR,Tx LPI microsecond timer register" hexmask.long 0x0 0.--31. 1. "TXLPIUSC,Tx LPI Microseconds Counter" line.long 0x4 "ETH_TX_LPI_TRAN_CNTR,Tx LPI transition counter register" hexmask.long 0x4 0.--31. 1. "TXLPITRC,Tx LPI Transition counter" line.long 0x8 "ETH_RX_LPI_USEC_CNTR,Rx LPI microsecond counter register" hexmask.long 0x8 0.--31. 1. "RXLPIUSC,Rx LPI Microseconds Counter" line.long 0xC "ETH_RX_LPI_TRAN_CNTR,Rx LPI transition counter register" hexmask.long 0xC 0.--31. 1. "RXLPITRC,Rx LPI Transition counter" group.long 0x900++0x7 line.long 0x0 "ETH_MACL3L4C0R,L3 and L4 control 0 register" bitfld.long 0x0 21. "L4DPIM0,Layer 4 Destination Port Inverse Match Enable" "0,1" newline bitfld.long 0x0 20. "L4DPM0,Layer 4 Destination Port Match Enable" "0,1" newline bitfld.long 0x0 19. "L4SPIM0,Layer 4 Source Port Inverse Match Enable" "0,1" newline bitfld.long 0x0 18. "L4SPM0,Layer 4 Source Port Match Enable" "0,1" newline bitfld.long 0x0 16. "L4PEN0,Layer 4 Protocol Enable" "0,1" newline hexmask.long.byte 0x0 11.--15. 1. "L3HDBM0,Layer 3 IP DA higher bits match" newline hexmask.long.byte 0x0 6.--10. 1. "L3HSBM0,Layer 3 IP SA higher bits match" newline bitfld.long 0x0 5. "L3DAIM0,Layer 3 IP DA Inverse Match Enable" "0,1" newline bitfld.long 0x0 4. "L3DAM0,Layer 3 IP DA Match Enable" "0,1" newline bitfld.long 0x0 3. "L3SAIM0,Layer 3 IP SA Inverse Match Enable" "0,1" newline bitfld.long 0x0 2. "L3SAM0,Layer 3 IP SA Match Enable" "0,1" newline bitfld.long 0x0 0. "L3PEN0,Layer 3 Protocol Enable" "0,1" line.long 0x4 "ETH_MACL4A0R," hexmask.long.word 0x4 16.--31. 1. "L4DP0,Layer 4 Destination Port Number Field" newline hexmask.long.word 0x4 0.--15. 1. "L4SP0,Layer 4 Source Port Number Field" group.long 0x910++0xF line.long 0x0 "ETH_MACL3A00R,Layer 3 Address 0 filter 0 register" hexmask.long 0x0 0.--31. 1. "L3A00,Layer 3 Address 0 Field" line.long 0x4 "ETH_MACL3A10R,Layer3 address 1 filter 0 register" hexmask.long 0x4 0.--31. 1. "L3A10,Layer 3 Address 1 Field" line.long 0x8 "ETH_MACL3A20R,Layer3 Address 2 filter 0 register" hexmask.long 0x8 0.--31. 1. "L3A20,Layer 3 Address 2 Field" line.long 0xC "ETH_MACL3A30R,Layer3 Address 3 filter 0 register" hexmask.long 0xC 0.--31. 1. "L3A30,Layer 3 Address 3 Field" group.long 0x930++0x7 line.long 0x0 "ETH_MACL3L4C1R,L3 and L4 control 1 register" bitfld.long 0x0 21. "L4DPIM1,Layer 4 Destination Port Inverse Match Enable" "0,1" newline bitfld.long 0x0 20. "L4DPM1,Layer 4 Destination Port Match Enable" "0,1" newline bitfld.long 0x0 19. "L4SPIM1,Layer 4 Source Port Inverse Match Enable" "0,1" newline bitfld.long 0x0 18. "L4SPM1,Layer 4 Source Port Match Enable" "0,1" newline bitfld.long 0x0 16. "L4PEN1,Layer 4 Protocol Enable" "0,1" newline hexmask.long.byte 0x0 11.--15. 1. "L3HDBM1,Layer 3 IP DA higher bits match" newline hexmask.long.byte 0x0 6.--10. 1. "L3HSBM1,Layer 3 IP SA Higher Bits Match" newline bitfld.long 0x0 5. "L3DAIM1,Layer 3 IP DA Inverse Match Enable" "0,1" newline bitfld.long 0x0 4. "L3DAM1,Layer 3 IP DA Match Enable" "0,1" newline bitfld.long 0x0 3. "L3SAIM1,Layer 3 IP SA Inverse Match Enable" "0,1" newline bitfld.long 0x0 2. "L3SAM1,Layer 3 IP SA Match Enable" "0,1" newline bitfld.long 0x0 0. "L3PEN1,Layer 3 Protocol Enable" "0,1" line.long 0x4 "ETH_MACL4A1R," hexmask.long.word 0x4 16.--31. 1. "L4DP1,Layer 4 Destination Port Number Field" newline hexmask.long.word 0x4 0.--15. 1. "L4SP1,Layer 4 Source Port Number Field" group.long 0x940++0xF line.long 0x0 "ETH_MACL3A01R,Layer3 address 0 filter 1 Register" hexmask.long 0x0 0.--31. 1. "L3A01,Layer 3 Address 0 Field" line.long 0x4 "ETH_MACL3A11R,Layer3 address 1 filter 1 register" hexmask.long 0x4 0.--31. 1. "L3A11,Layer 3 Address 1 Field" line.long 0x8 "ETH_MACL3A21R,Layer3 address 2 filter 1 Register" hexmask.long 0x8 0.--31. 1. "L3A21,Layer 3 Address 2 Field" line.long 0xC "ETH_MACL3A31R,Layer3 address 3 filter 1 register" hexmask.long 0xC 0.--31. 1. "L3A31,Layer 3 Address 3 Field" group.long 0xB00++0x7 line.long 0x0 "ETH_MACTSCR,Timestamp control Register" bitfld.long 0x0 24. "TXTSSTSM,Transmit Timestamp Status Mode" "0,1" newline rbitfld.long 0x0 19. "CSC,Enable checksum correction during OST for PTP over UDP/IPv4 packets" "0,1" newline bitfld.long 0x0 18. "TSENMACADDR,Enable MAC Address for PTP Packet Filtering" "0,1" newline bitfld.long 0x0 16.--17. "SNAPTYPSEL,Select PTP packets for Taking Snapshots" "0,1,2,3" newline bitfld.long 0x0 15. "TSMSTRENA,Enable Snapshot for Messages Relevant to Master" "0,1" newline bitfld.long 0x0 14. "TSEVNTENA,Enable Timestamp Snapshot for Event Messages" "0,1" newline bitfld.long 0x0 13. "TSIPV4ENA,Enable Processing of PTP Packets Sent over IPv4-UDP" "0,1" newline bitfld.long 0x0 12. "TSIPV6ENA,Enable Processing of PTP Packets Sent over IPv6-UDP" "0,1" newline bitfld.long 0x0 11. "TSIPENA,Enable Processing of PTP over Ethernet Packets" "0,1" newline bitfld.long 0x0 10. "TSVER2ENA,Enable PTP Packet Processing for Version 2 Format" "0,1" newline bitfld.long 0x0 9. "TSCTRLSSR,Timestamp Digital or Binary Rollover Control" "0,1" newline bitfld.long 0x0 8. "TSENALL,Enable Timestamp for All Packets" "0,1" newline bitfld.long 0x0 5. "TSADDREG,Update Addend Register" "0,1" newline bitfld.long 0x0 3. "TSUPDT,Update Timestamp" "0,1" newline bitfld.long 0x0 2. "TSINIT,Initialize Timestamp" "0,1" newline bitfld.long 0x0 1. "TSCFUPDT,Fine or Coarse Timestamp Update" "0,1" newline bitfld.long 0x0 0. "TSENA,Enable Timestamp" "0,1" line.long 0x4 "ETH_MACSSIR,Sub-second increment register" hexmask.long.byte 0x4 16.--23. 1. "SSINC,Sub-second Increment Value" rgroup.long 0xB08++0x7 line.long 0x0 "ETH_MACSTSR,System time seconds register" hexmask.long 0x0 0.--31. 1. "TSS,Timestamp Second" line.long 0x4 "ETH_MACSTNR,System time nanoseconds register" hexmask.long 0x4 0.--30. 1. "TSSS,Timestamp Sub-seconds" group.long 0xB10++0xB line.long 0x0 "ETH_MACSTSUR,System time seconds update register" hexmask.long 0x0 0.--31. 1. "TSS,Timestamp Seconds" line.long 0x4 "ETH_MACSTNUR," bitfld.long 0x4 31. "ADDSUB,Add or Subtract Time" "0,1" newline hexmask.long 0x4 0.--30. 1. "TSSS,Timestamp Sub-seconds" line.long 0x8 "ETH_MACTSAR,Timestamp addend register" hexmask.long 0x8 0.--31. 1. "TSAR,Timestamp Addend Register" rgroup.long 0xB20++0x3 line.long 0x0 "ETH_MACTSSR,Timestamp status register" hexmask.long.byte 0x0 25.--29. 1. "ATSNS,Number of Auxiliary Timestamp Snapshots" newline bitfld.long 0x0 24. "ATSSTM,Auxiliary Timestamp Snapshot Trigger Missed" "0,1" newline hexmask.long.byte 0x0 16.--19. 1. "ATSSTN,Auxiliary Timestamp Snapshot Trigger Identifier" newline bitfld.long 0x0 15. "TXTSSIS,Tx Timestamp Status Interrupt Status" "0,1" newline bitfld.long 0x0 3. "TSTRGTERR0,Timestamp Target Time Error" "0,1" newline bitfld.long 0x0 2. "AUXTSTRIG,Auxiliary Timestamp Trigger Snapshot" "0,1" newline bitfld.long 0x0 1. "TSTARGT0,Timestamp Target Time Reached" "0,1" newline bitfld.long 0x0 0. "TSSOVF,Timestamp Seconds Overflow" "0,1" rgroup.long 0xB30++0x7 line.long 0x0 "ETH_MACTXTSSNR,Tx timestamp status nanoseconds register" bitfld.long 0x0 31. "TXTSSMIS,Transmit Timestamp Status Missed" "0,1" newline hexmask.long 0x0 0.--30. 1. "TXTSSLO,Transmit Timestamp Status Low" line.long 0x4 "ETH_MACTXTSSSR,Tx timestamp status seconds register" hexmask.long 0x4 0.--31. 1. "TXTSSHI,Transmit Timestamp Status High" group.long 0xB40++0x3 line.long 0x0 "ETH_MACACR,Auxiliary control register" bitfld.long 0x0 7. "ATSEN3,Auxiliary Snapshot 3 Enable" "0,1" newline bitfld.long 0x0 6. "ATSEN2,Auxiliary Snapshot 2 Enable" "0,1" newline bitfld.long 0x0 5. "ATSEN1,Auxiliary Snapshot 1 Enable" "0,1" newline bitfld.long 0x0 4. "ATSEN0,Auxiliary Snapshot 0 Enable" "0,1" newline bitfld.long 0x0 0. "ATSFC,Auxiliary Snapshot FIFO Clear" "0,1" rgroup.long 0xB48++0x7 line.long 0x0 "ETH_MACATSNR,Auxiliary timestamp nanoseconds register" hexmask.long 0x0 0.--30. 1. "AUXTSLO,Auxiliary Timestamp" line.long 0x4 "ETH_MACATSSR,Auxiliary timestamp seconds register" hexmask.long 0x4 0.--31. 1. "AUXTSHI,Auxiliary Timestamp" group.long 0xB50++0xF line.long 0x0 "ETH_MACTSIACR,Timestamp Ingress asymmetric correction register" hexmask.long 0x0 0.--31. 1. "OSTIAC,One-Step Timestamp Ingress Asymmetry Correction" line.long 0x4 "ETH_MACTSEACR,Timestamp Egress asymmetric correction register" hexmask.long 0x4 0.--31. 1. "OSTEAC,One-Step Timestamp Egress Asymmetry Correction" line.long 0x8 "ETH_MACTSICNR,Timestamp Ingress correction nanosecond register" hexmask.long 0x8 0.--31. 1. "TSIC,Timestamp Ingress Correction" line.long 0xC "ETH_MACTSECNR,Timestamp Egress correction nanosecond register" hexmask.long 0xC 0.--31. 1. "TSEC,Timestamp Egress Correction" group.long 0xB70++0x3 line.long 0x0 "ETH_MACPPSCR,PPS control register" bitfld.long 0x0 5.--6. "TRGTMODSEL0,Target Time Register Mode for PPS Output" "0: Target Time registers are programmed only for..,1: Reserved must not be used,2: Target Time registers are programmed for..,3: Target Time registers are programmed only for.." newline bitfld.long 0x0 4. "PPSEN0,Flexible PPS Output Mode Enable" "0,1" newline hexmask.long.byte 0x0 0.--3. 1. "PPSCTRL,PPS Output Frequency Control" group.long 0xB70++0x3 line.long 0x0 "ETH_MACPPSCR_alternate,PPS control register" bitfld.long 0x0 5.--6. "TRGTMODSEL0,Target Time Register Mode for PPS Output" "0: Target Time registers are programmed only for..,1: Reserved must not be used,2: Target Time registers are programmed for..,3: Target Time registers are programmed only for.." newline bitfld.long 0x0 4. "PPSEN0,Flexible PPS Output Mode Enable" "0,1" newline hexmask.long.byte 0x0 0.--3. 1. "PPSCMD,Flexible PPS Output (eth_ptp_pps_out[0]) Control" group.long 0xB80++0xF line.long 0x0 "ETH_MACPPSTTSR,PPS target time seconds register" hexmask.long 0x0 0.--31. 1. "TSTRH0,PPS Target Time Seconds Register" line.long 0x4 "ETH_MACPPSTTNR,PPS target time nanoseconds register" bitfld.long 0x4 31. "TRGTBUSY0,PPS Target Time Register Busy" "0,1" newline hexmask.long 0x4 0.--30. 1. "TTSL0,Target Time Low for PPS Register" line.long 0x8 "ETH_MACPPSIR,PPS interval register" hexmask.long 0x8 0.--31. 1. "PPSINT0,PPS Output Signal Interval" line.long 0xC "ETH_MACPPSWR,PPS width register" hexmask.long 0xC 0.--31. 1. "PPSWIDTH0,PPS Output Signal Width" group.long 0xBC0++0x13 line.long 0x0 "ETH_MACPOCR,PTP Offload control register" hexmask.long.byte 0x0 8.--15. 1. "DN,Domain Number" newline bitfld.long 0x0 6. "DRRDIS,Disable PTO Delay Request/Response response generation" "0,1" newline bitfld.long 0x0 5. "APDREQTRIG,Automatic PTP Pdelay_Req message Trigger" "0,1" newline bitfld.long 0x0 4. "ASYNCTRIG,Automatic PTP SYNC message Trigger" "0,1" newline bitfld.long 0x0 2. "APDREQEN,Automatic PTP Pdelay_Req message Enable" "0,1" newline bitfld.long 0x0 1. "ASYNCEN,Automatic PTP SYNC message Enable" "0,1" newline bitfld.long 0x0 0. "PTOEN,PTP Offload Enable" "0,1" line.long 0x4 "ETH_MACSPI0R,PTP Source Port Identity 0 Register" hexmask.long 0x4 0.--31. 1. "SPI0,Source Port Identity 0" line.long 0x8 "ETH_MACSPI1R,PTP Source port identity 1 register" hexmask.long 0x8 0.--31. 1. "SPI1,Source Port Identity 1" line.long 0xC "ETH_MACSPI2R,PTP Source port identity 2 register" hexmask.long.word 0xC 0.--15. 1. "SPI2,Source Port Identity 2" line.long 0x10 "ETH_MACLMIR,Log message interval register" hexmask.long.byte 0x10 24.--31. 1. "LMPDRI,Log Min Pdelay_Req Interval" newline bitfld.long 0x10 8.--10. "DRSYNCR,Delay_Req to SYNC Ratio" "0: DelayReq generated for every received SYNC,1: DelayReq generated every alternate reception of..,2: for every 4 SYNC messages,3: for every 8 SYNC messages,4: for every 16 SYNC messages,5: for every 32 SYNC messages,?,?" newline hexmask.long.byte 0x10 0.--7. 1. "LSI,Log Sync Interval" group.long 0xC00++0x3 line.long 0x0 "ETH_MTLOMR,Operating mode Register" bitfld.long 0x0 9. "CNTCLR,Counters Reset" "0,1" newline bitfld.long 0x0 8. "CNTPRST,Counters Preset" "0,1" newline bitfld.long 0x0 5.--6. "SCHALG,Tx Scheduling Algorithm" "0: WRR algorithm,1: Reserved must not be used.,2: Reserved must not be used.,3: Strict priority algorithm." newline bitfld.long 0x0 2. "RAA,Receive Arbitration Algorithm" "0: Strict priority (SP),1: Weighted Strict Priority (WSP)" newline bitfld.long 0x0 1. "DTXSTS,Drop Transmit Status" "0,1" rgroup.long 0xC20++0x3 line.long 0x0 "ETH_MTLISR,Interrupt status Register" bitfld.long 0x0 1. "Q1IS,Queue 1 interrupt status" "0,1" newline bitfld.long 0x0 0. "Q0IS,Queue 0 interrupt status" "0,1" group.long 0xD00++0x3 line.long 0x0 "ETH_MTLTXQ0OMR,Tx queue 0 operating mode Register" hexmask.long.byte 0x0 16.--19. 1. "TQS,Transmit queue size" newline bitfld.long 0x0 4.--6. "TTC,Transmit Threshold Control" "0: 32,1: 64,2: 96,3: 128,4: 192,5: 256,6: 384,7: 512" newline bitfld.long 0x0 2.--3. "TXQEN,Transmit Queue Enable" "0: Not enabled,?,2: Enabled,?" newline bitfld.long 0x0 1. "TSF,Transmit Store and Forward" "0,1" newline bitfld.long 0x0 0. "FTQ,Flush Transmit Queue" "0,1" rgroup.long 0xD04++0x7 line.long 0x0 "ETH_MTLTXQ0UR,Tx queue 0 underflow register" bitfld.long 0x0 11. "UFCNTOVF,Overflow Bit for Underflow Packet Counter" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "UFFRMCNT,Underflow Packet Counter" line.long 0x4 "ETH_MTLTXQ0DR,Tx queue 0 debug Register" bitfld.long 0x4 20.--22. "STXSTSF,Number of Status Words in Tx Status FIFO of Queue" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 16.--18. "PTXQ,Number of Packets in the Transmit Queue" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 5. "TXSTSFSTS,MTL Tx Status FIFO Full Status" "0,1" newline bitfld.long 0x4 4. "TXQSTS,MTL Tx Queue Not Empty Status" "0,1" newline bitfld.long 0x4 3. "TWCSTS,MTL Tx Queue Write Controller Status" "0,1" newline bitfld.long 0x4 1.--2. "TRCSTS,MTL Tx Queue Read Controller Status" "0: Idle state,1: Read state (transferring data to the MAC..,2: Waiting for pending Tx Status from the MAC..,3: Flushing the Tx queue because of the Packet.." newline bitfld.long 0x4 0. "TXQPAUSED,Transmit Queue in Pause" "0,1" rgroup.long 0xD14++0x3 line.long 0x0 "ETH_MTLTXQ0ESR,Tx queue x ETS status Register" hexmask.long.tbyte 0x0 0.--23. 1. "ABS,Average Bits per Slot" group.long 0xD18++0x3 line.long 0x0 "ETH_MTLTXQ0QWR,Tx queue 0 quantum weight register" hexmask.long.byte 0x0 0.--6. 1. "ISCQW,Quantum weight" group.long 0xD2C++0x7 line.long 0x0 "ETH_MTLQ0ICSR,Queue 0 interrupt control status Register" bitfld.long 0x0 24. "RXOIE,Receive Queue Overflow Interrupt Enable" "0,1" newline bitfld.long 0x0 16. "RXOVFIS,Receive Queue Overflow Interrupt Status" "0,1" newline bitfld.long 0x0 8. "TXUIE,Transmit Queue Underflow Interrupt Enable" "0,1" newline bitfld.long 0x0 0. "TXUNFIS,Transmit Queue Underflow Interrupt Status" "0,1" line.long 0x4 "ETH_MTLRXQ0OMR,Rx queue 0 operating mode register" rbitfld.long 0x4 20.--22. "RQS,Receive Queue Size" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 14.--16. "RFD,Threshold for Deactivating Flow Control (in half-duplex and full-duplex modes)" "0: Full minus 1 Kbyte that is FULL 1 Kbyte,1: Full minus 1.5 Kbyte that is FULL 1.5 Kbyte,2: Full minus 2 Kbytes,3: Full minus 2,4: Full minus 2,5: Full minus 2,6: Full minus 4 Kbytes,7: Full minus 4" newline bitfld.long 0x4 8.--10. "RFA,Threshold for Activating Flow Control (in half-duplex and full-duplex" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 7. "EHFC,Enable Hardware Flow Control" "0,1" newline bitfld.long 0x4 6. "DIS_TCP_EF,Disable Dropping of TCP/IP Checksum Error Packets" "0,1" newline bitfld.long 0x4 5. "RSF,Receive Queue Store and Forward" "0,1" newline bitfld.long 0x4 4. "FEP,Forward Error Packets" "0,1" newline bitfld.long 0x4 3. "FUP,Forward Undersized Good Packets" "0,1" newline bitfld.long 0x4 0.--1. "RTC,Receive Queue Threshold Control" "0: 64,1: 32,2: 96,3: 128" rgroup.long 0xD34++0x7 line.long 0x0 "ETH_MTLRXQ0MPOCR,Rx queue 0 missed packet and overflow counter register" bitfld.long 0x0 27. "MISCNTOVF,Missed Packet Counter Overflow Bit" "0,1" newline hexmask.long.word 0x0 16.--26. 1. "MISPKTCNT,Missed Packet Counter" newline bitfld.long 0x0 11. "OVFCNTOVF,Overflow Counter Overflow Bit" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "OVFPKTCNT,Overflow Packet Counter" line.long 0x4 "ETH_MTLRXQ0DR,Rx queue 0 debug register" hexmask.long.word 0x4 16.--29. 1. "PRXQ,Number of Packets in Receive Queue" newline bitfld.long 0x4 4.--5. "RXQSTS,MTL Rx Queue Fill-Level Status" "0: Rx queue empty,1: Rx queue fill-level below flow-control..,2: Rx queue fill-level above flow-control activate..,3: Rx queue full" newline bitfld.long 0x4 1.--2. "RRCSTS,MTL Rx Queue Read Controller State" "0: Idle state,1: Reading packet data,2: Reading packet status (or timestamp),3: Flushing the packet data and status" newline bitfld.long 0x4 0. "RWCSTS,MTL Rx Queue Write Controller Active Status" "0,1" group.long 0xD3C++0x7 line.long 0x0 "ETH_MTLRXQ0CR,Rx queue 0 control register" rbitfld.long 0x0 3. "RXQ_FRM_ARBIT,Receive Queue Packet Arbitration" "0,1" newline bitfld.long 0x0 0.--2. "RXQ_WEGT,Receive Queue Weight" "0,1,2,3,4,5,6,7" line.long 0x4 "ETH_MTLTXQ1OMR,Tx queue 1 operating mode Register" hexmask.long.byte 0x4 16.--19. 1. "TQS,Transmit queue size" newline bitfld.long 0x4 4.--6. "TTC,Transmit Threshold Control" "0: 32,1: 64,2: 96,3: 128,4: 192,5: 256,6: 384,7: 512" newline bitfld.long 0x4 2.--3. "TXQEN,Transmit Queue Enable" "0: Not enabled,?,2: Enabled,?" newline bitfld.long 0x4 1. "TSF,Transmit Store and Forward" "0,1" newline bitfld.long 0x4 0. "FTQ,Flush Transmit Queue" "0,1" rgroup.long 0xD44++0x7 line.long 0x0 "ETH_MTLTXQ1UR,Tx queue 1 underflow register" bitfld.long 0x0 11. "UFCNTOVF,Overflow Bit for Underflow Packet Counter" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "UFFRMCNT,Underflow Packet Counter" line.long 0x4 "ETH_MTLTXQ1DR,Tx queue 1 debug Register" bitfld.long 0x4 20.--22. "STXSTSF,Number of Status Words in Tx Status FIFO of Queue" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 16.--18. "PTXQ,Number of Packets in the Transmit Queue" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 5. "TXSTSFSTS,MTL Tx Status FIFO Full Status" "0,1" newline bitfld.long 0x4 4. "TXQSTS,MTL Tx Queue Not Empty Status" "0,1" newline bitfld.long 0x4 3. "TWCSTS,MTL Tx Queue Write Controller Status" "0,1" newline bitfld.long 0x4 1.--2. "TRCSTS,MTL Tx Queue Read Controller Status" "0: Idle state,1: Read state (transferring data to the MAC..,2: Waiting for pending Tx Status from the MAC..,3: Flushing the Tx queue because of the Packet.." newline bitfld.long 0x4 0. "TXQPAUSED,Transmit Queue in Pause" "0,1" group.long 0xD50++0x3 line.long 0x0 "ETH_MTLTXQ1ECR,Tx queue 1 ETS control Register" bitfld.long 0x0 3. "CC,Credit Control" "0,1" rgroup.long 0xD54++0x3 line.long 0x0 "ETH_MTLTXQ1ESR,Tx queue x ETS status Register" hexmask.long.tbyte 0x0 0.--23. 1. "ABS,Average Bits per Slot" group.long 0xD58++0x3 line.long 0x0 "ETH_MTLTXQ1QWR,Tx queue 1 quantum weight register" hexmask.long.byte 0x0 0.--6. 1. "ISCQW,quantum weight" group.long 0xD60++0x3 line.long 0x0 "ETH_MTLTXQ1HCR,Tx Queue 1 hiCredit register" hexmask.long 0x0 0.--28. 1. "HC,hiCredit Value" group.long 0xD6C++0x7 line.long 0x0 "ETH_MTLQ1ICSR,Queue 1 interrupt control status Register" bitfld.long 0x0 24. "RXOIE,Receive Queue Overflow Interrupt Enable" "0,1" newline bitfld.long 0x0 16. "RXOVFIS,Receive Queue Overflow Interrupt Status" "0,1" newline bitfld.long 0x0 8. "TXUIE,Transmit Queue Underflow Interrupt Enable" "0,1" newline bitfld.long 0x0 0. "TXUNFIS,Transmit Queue Underflow Interrupt Status" "0,1" line.long 0x4 "ETH_MTLRXQ1OMR,Rx queue 1 operating mode register" rbitfld.long 0x4 20.--22. "RQS,Receive Queue Size" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 14.--16. "RFD,Threshold for Deactivating Flow Control (in half-duplex and full-duplex modes)" "0: Full minus 1 Kbyte that is FULL 1 Kbyte,1: Full minus 1.5 Kbyte that is FULL 1.5 Kbyte,2: Full minus 2 Kbytes,3: Full minus 2,4: Full minus 2,5: Full minus 2,6: Full minus 4 Kbytes,7: Full minus 4" newline bitfld.long 0x4 8.--10. "RFA,Threshold for Activating Flow Control (in half-duplex and full-duplex" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 7. "EHFC,Enable Hardware Flow Control" "0,1" newline bitfld.long 0x4 6. "DIS_TCP_EF,Disable Dropping of TCP/IP Checksum Error Packets" "0,1" newline bitfld.long 0x4 5. "RSF,Receive Queue Store and Forward" "0,1" newline bitfld.long 0x4 4. "FEP,Forward Error Packets" "0,1" newline bitfld.long 0x4 3. "FUP,Forward Undersized Good Packets" "0,1" newline bitfld.long 0x4 0.--1. "RTC,Receive Queue Threshold Control" "0: 64,1: 32,2: 96,3: 128" rgroup.long 0xD74++0x7 line.long 0x0 "ETH_MTLRXQ1MPOCR,Rx queue 1 missed packet and overflow counter register" bitfld.long 0x0 27. "MISCNTOVF,Missed Packet Counter Overflow Bit" "0,1" newline hexmask.long.word 0x0 16.--26. 1. "MISPKTCNT,Missed Packet Counter" newline bitfld.long 0x0 11. "OVFCNTOVF,Overflow Counter Overflow Bit" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "OVFPKTCNT,Overflow Packet Counter" line.long 0x4 "ETH_MTLRXQ1DR,Rx queue 1 debug register" hexmask.long.word 0x4 16.--29. 1. "PRXQ,Number of Packets in Receive Queue" newline bitfld.long 0x4 4.--5. "RXQSTS,MTL Rx Queue Fill-Level Status" "0: Rx queue empty,1: Rx queue fill-level below flow-control..,2: Rx queue fill-level above flow-control activate..,3: Rx queue full" newline bitfld.long 0x4 1.--2. "RRCSTS,MTL Rx Queue Read Controller State" "0: Idle state,1: Reading packet data,2: Reading packet status (or timestamp),3: Flushing the packet data and status" newline bitfld.long 0x4 0. "RWCSTS,MTL Rx Queue Write Controller Active Status" "0,1" group.long 0xD7C++0x3 line.long 0x0 "ETH_MTLRXQ1CR,Rx queue 1 control register" rbitfld.long 0x0 3. "RXQ_FRM_ARBIT,Receive Queue Packet Arbitration" "0,1" newline bitfld.long 0x0 0.--2. "RXQ_WEGT,Receive Queue Weight" "0,1,2,3,4,5,6,7" group.long 0x1000++0x7 line.long 0x0 "ETH_DMAMR,DMA mode register" bitfld.long 0x0 16.--17. "INTM,Interrupt Mode" "0,1,2,3" newline bitfld.long 0x0 12.--14. "PR,Priority ratio" "0: The priority ratio is 1:1,1: The priority ratio is 2:1,2: The priority ratio is 3:1,3: The priority ratio is 4:1,4: The priority ratio is 5:1,5: The priority ratio is 6:1,6: The priority ratio is 7:1,7: The priority ratio is 8:1" newline bitfld.long 0x0 11. "TXPR,Transmit priority" "0,1" newline rbitfld.long 0x0 2.--4. "TAA,Transmit Arbitration Algorithm" "0: Fixed priority. In fixed priority Channel 0 has..,1: Weighted Strict Priority (WSP),2: Weighted Round-Robin (WRR),3: Reserved must not be used.,4: Reserved must not be used.,5: Reserved must not be used.,6: Reserved must not be used.,7: Reserved must not be used." newline bitfld.long 0x0 0. "SWR,Software Reset" "0,1" line.long 0x4 "ETH_DMASBMR,System bus mode register" bitfld.long 0x4 31. "EN_LPI,Enable Low Power Interface (LPI)" "0,1" newline bitfld.long 0x4 30. "LPI_XIT_PKT,Unlock on Magic Packet or Remote wakeup Packet" "0,1" newline bitfld.long 0x4 24.--25. "WR_OSR_LMT,AXI Maximum Write Outstanding Request Limit" "0,1,2,3" newline bitfld.long 0x4 16.--17. "RD_OSR_LMT,AXI Maximum Read Outstanding Request Limit" "0,1,2,3" newline bitfld.long 0x4 13. "ONEKBBE,1 Kbyte Boundary Crossing Enable for the AXI Master" "0,1" newline bitfld.long 0x4 12. "AAL,Address-Aligned Beats" "0,1" newline bitfld.long 0x4 7. "BLEN256,AXI Burst Length 256" "0,1" newline bitfld.long 0x4 6. "BLEN128,AXI Burst Length 128" "0,1" newline bitfld.long 0x4 5. "BLEN64,AXI Burst Length 64" "0,1" newline bitfld.long 0x4 4. "BLEN32,AXI Burst Length 32" "0,1" newline bitfld.long 0x4 3. "BLEN16,AXI Burst Length 16" "0,1" newline bitfld.long 0x4 2. "BLEN8,AXI Burst Length 8" "0,1" newline bitfld.long 0x4 1. "BLEN4,AXI Burst Length 4" "0,1" newline bitfld.long 0x4 0. "FB,Fixed Burst Length" "?,1: when this bit is set to 0" rgroup.long 0x1008++0x7 line.long 0x0 "ETH_DMAISR,Interrupt status register" bitfld.long 0x0 17. "MACIS,MAC Interrupt Status" "0,1" newline bitfld.long 0x0 16. "MTLIS,MTL Interrupt Status" "0,1" newline bitfld.long 0x0 1. "DC1IS,DMA Channel 1 Interrupt Status" "0,1" newline bitfld.long 0x0 0. "DC0IS,DMA Channel 0 Interrupt Status" "0,1" line.long 0x4 "ETH_DMADSR,Debug status register" hexmask.long.byte 0x4 20.--23. 1. "TPS1,DMA Channel 1 Transmit Process State" newline hexmask.long.byte 0x4 16.--19. 1. "RPS1,DMA Channel 1 Receive Process State" newline hexmask.long.byte 0x4 12.--15. 1. "TPS0,DMA Channel 0 Transmit Process State" newline hexmask.long.byte 0x4 8.--11. 1. "RPS0,DMA Channel 0 Receive Process State" newline bitfld.long 0x4 1. "AXRHSTS,AXI Master Read Channel Status" "0,1" newline bitfld.long 0x4 0. "AXWHSTS,AXI Master Write Channel" "0,1" group.long 0x1020++0xB line.long 0x0 "ETH_DMAA4TXACR,AXI4 transmit channel ACE control register" hexmask.long.byte 0x0 16.--19. 1. "THC,Transmit DMA First Packet Buffer or TSO Header Cache Control" newline hexmask.long.byte 0x0 8.--11. 1. "TEC,Transmit DMA Extended Packet Buffer or TSO Payload Cache Control" newline hexmask.long.byte 0x0 0.--3. 1. "TDRC,Transmit DMA Read Descriptor Cache Control" line.long 0x4 "ETH_DMAA4RXACR,AXI4 receive channel ACE control register" hexmask.long.byte 0x4 24.--27. 1. "RDC,Receive DMA Buffer Cache Control" newline hexmask.long.byte 0x4 16.--19. 1. "RHC,Receive DMA Header Cache Control" newline hexmask.long.byte 0x4 8.--11. 1. "RPC,Receive DMA Payload Cache Control" newline hexmask.long.byte 0x4 0.--3. 1. "RDWC,Receive DMA Write Descriptor Cache Control" line.long 0x8 "ETH_DMAA4DACR,AXI4 descriptor ACE control register" hexmask.long.byte 0x8 8.--11. 1. "RDRC,Receive DMA Read Descriptor Cache control" newline bitfld.long 0x8 4.--5. "TDWD,Transmit DMA Write Descriptor Domain control" "0,1,2,3" newline hexmask.long.byte 0x8 0.--3. 1. "TDWC,Transmit DMA Write Descriptor Cache control" group.long 0x1100++0xB line.long 0x0 "ETH_DMAC0CR,Channel 0 control register" bitfld.long 0x0 18.--20. "DSL,Descriptor Skip Length" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 16. "PBLX8,8xPBL mode" "0,1" newline hexmask.long.word 0x0 0.--13. 1. "MSS,Maximum Segment Size" line.long 0x4 "ETH_DMAC0TXCR,Channel 0 transmit control register" hexmask.long.byte 0x4 24.--27. 1. "TQOS,Transmit QOS." newline hexmask.long.byte 0x4 16.--21. 1. "TXPBL,Transmit Programmable Burst Length" newline bitfld.long 0x4 12. "TSE,TCP Segmentation Enabled" "0,1" newline bitfld.long 0x4 4. "OSF,Operate on Second Packet" "0,1" newline rbitfld.long 0x4 1.--3. "TCW,Transmit Channel Weight" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 0. "ST,Start or Stop Transmission Command" "0,1" line.long 0x8 "ETH_DMAC0RXCR,Channel 0 receive control register" bitfld.long 0x8 31. "RPF,DMA Rx Channel0 Packet Flush" "0,1" newline hexmask.long.byte 0x8 24.--27. 1. "RQOS,Rx AXI4 QOS." newline hexmask.long.byte 0x8 16.--21. 1. "RXPBL,Receive Programmable Burst Length" newline hexmask.long.word 0x8 1.--14. 1. "RBSZ,Receive Buffer size" newline bitfld.long 0x8 0. "SR,Start or Stop Receive" "0,1" group.long 0x1114++0x3 line.long 0x0 "ETH_DMAC0TXDLAR,Channel 0 Tx descriptor list address register" hexmask.long 0x0 2.--31. 1. "TDESLA,Start of Transmit List" group.long 0x111C++0x7 line.long 0x0 "ETH_DMAC0RXDLAR,Channel 0 Rx descriptor list address register" hexmask.long 0x0 2.--31. 1. "RDESLA,Start of Receive List" line.long 0x4 "ETH_DMAC0TXDTPR,Channel 0 Tx descriptor tail pointer register" hexmask.long 0x4 2.--31. 1. "TDT,Transmit Descriptor Tail Pointer" group.long 0x1128++0x13 line.long 0x0 "ETH_DMAC0RXDTPR,Channel 0 Rx descriptor tail pointer register" hexmask.long 0x0 2.--31. 1. "RDT,Receive Descriptor Tail Pointer" line.long 0x4 "ETH_DMAC0TXRLR,Channel 0 Tx descriptor ring length register" hexmask.long.word 0x4 0.--9. 1. "TDRL,Transmit Descriptor Ring Length" line.long 0x8 "ETH_DMAC0RXRLR,Channel 0 Rx descriptor ring length register" hexmask.long.word 0x8 0.--9. 1. "RDRL,Receive Descriptor Ring Length" line.long 0xC "ETH_DMAC0IER,Channel 0 interrupt enable register" bitfld.long 0xC 15. "NIE,Normal Interrupt Summary Enable" "0: Transmit Interrupt,?" newline bitfld.long 0xC 14. "AIE,Abnormal Interrupt Summary Enable" "?,1: Transmit Process Stopped" newline bitfld.long 0xC 13. "CDEE,Context Descriptor Error Enable" "0,1" newline bitfld.long 0xC 12. "FBEE,Fatal Bus Error Enable" "0,1" newline bitfld.long 0xC 11. "ERIE,Early Receive Interrupt Enable" "0,1" newline bitfld.long 0xC 10. "ETIE,Early Transmit Interrupt Enable" "0,1" newline bitfld.long 0xC 9. "RWTE,Receive Watchdog Timeout Enable" "0,1" newline bitfld.long 0xC 8. "RSE,Receive Stopped Enable" "0,1" newline bitfld.long 0xC 7. "RBUE,Receive Buffer Unavailable Enable" "0,1" newline bitfld.long 0xC 6. "RIE,Receive Interrupt Enable" "0,1" newline bitfld.long 0xC 2. "TBUE,Transmit Buffer Unavailable Enable" "0,1" newline bitfld.long 0xC 1. "TXSE,Transmit Stopped Enable" "0,1" newline bitfld.long 0xC 0. "TIE,Transmit Interrupt Enable" "0,1" line.long 0x10 "ETH_DMAC0RXIWTR,Channel 0 Rx interrupt watchdog timer register" bitfld.long 0x10 16.--17. "RWTU,Receive Interrupt Watchdog Timer Count Units" "0: 256,1: 512,2: 1024,3: 2048" newline hexmask.long.byte 0x10 0.--7. 1. "RWT,Receive Interrupt Watchdog Timer Count" rgroup.long 0x1144++0x3 line.long 0x0 "ETH_DMAC0CATXDR,Channel 0 current application transmit descriptor register" hexmask.long 0x0 0.--31. 1. "CURTDESAPTR,Application Transmit Descriptor Address Pointer" rgroup.long 0x114C++0x3 line.long 0x0 "ETH_DMAC0CARXDR,Channel 0 current application receive descriptor register" hexmask.long 0x0 0.--31. 1. "CURRDESAPTR,Application Receive Descriptor Address Pointer" rgroup.long 0x1154++0x3 line.long 0x0 "ETH_DMAC0CATXBR,Channel 0 current application transmit buffer register" hexmask.long 0x0 0.--31. 1. "CURTBUFAPTR,Application Transmit Buffer Address Pointer" rgroup.long 0x115C++0x3 line.long 0x0 "ETH_DMAC0CARXBR,Channel 0 current application receive buffer register" hexmask.long 0x0 0.--31. 1. "CURRBUFAPTR,Application Receive Buffer Address Pointer" group.long 0x1160++0x3 line.long 0x0 "ETH_DMAC0SR,Channel 0 status register" rbitfld.long 0x0 19.--21. "REB,Rx DMA Error Bits" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 16.--18. "TEB,Tx DMA Error Bits" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 15. "NIS,Normal Interrupt Summary" "0: Transmit Interrupt,?" newline bitfld.long 0x0 14. "AIS,Abnormal Interrupt Summary" "?,1: Transmit Process Stopped" newline bitfld.long 0x0 13. "CDE,Context Descriptor Error" "0,1" newline bitfld.long 0x0 12. "FBE,Fatal Bus Error" "0,1" newline bitfld.long 0x0 11. "ERI,Early Receive Interrupt" "0,1" newline bitfld.long 0x0 10. "ETI,Early Transmit Interrupt" "0,1" newline bitfld.long 0x0 9. "RWT,Receive Watchdog Timeout" "0,1" newline bitfld.long 0x0 8. "RPS,Receive Process Stopped" "0,1" newline bitfld.long 0x0 7. "RBU,Receive Buffer Unavailable" "0,1" newline bitfld.long 0x0 6. "RI,Receive Interrupt" "0,1" newline bitfld.long 0x0 2. "TBU,Transmit Buffer Unavailable" "0,1" newline bitfld.long 0x0 1. "TPS,Transmit Process Stopped" "0,1" newline bitfld.long 0x0 0. "TI,Transmit Interrupt" "0,1" rgroup.long 0x116C++0x3 line.long 0x0 "ETH_DMAC0MFCR,Channel 0 missed frame count register" bitfld.long 0x0 15. "MFCO,Overflow status of the MFC Counter" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "MFC,Dropped Packet Counters" group.long 0x1180++0x7 line.long 0x0 "ETH_DMAC1CR,Channel 1 control register" bitfld.long 0x0 18.--20. "DSL,Descriptor Skip Length" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 16. "PBLX8,8xPBL mode" "0,1" newline hexmask.long.word 0x0 0.--13. 1. "MSS,Maximum Segment Size" line.long 0x4 "ETH_DMAC1TXCR,Channel 1 transmit control register" hexmask.long.byte 0x4 24.--27. 1. "TQOS,Transmit QOS." newline hexmask.long.byte 0x4 16.--21. 1. "TXPBL,Transmit Programmable Burst Length" newline bitfld.long 0x4 12. "TSE,TCP Segmentation Enabled" "0,1" newline bitfld.long 0x4 4. "OSF,Operate on Second Packet" "0,1" newline rbitfld.long 0x4 1.--3. "TCW,Transmit Channel Weight" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 0. "ST,Start or Stop Transmission Command" "0,1" group.long 0x1194++0x3 line.long 0x0 "ETH_DMAC1TXDLAR,Channel 1 Tx descriptor list address register" hexmask.long 0x0 2.--31. 1. "TDESLA,Start of Transmit List" group.long 0x11A0++0x3 line.long 0x0 "ETH_DMAC1TXDTPR,Channel 1 Tx descriptor tail pointer register" hexmask.long 0x0 2.--31. 1. "TDT,Transmit Descriptor Tail Pointer" group.long 0x11AC++0x3 line.long 0x0 "ETH_DMAC1TXRLR,Channel 1 Tx descriptor ring length register" hexmask.long.word 0x0 0.--9. 1. "TDRL,Transmit Descriptor Ring Length" group.long 0x11B4++0x3 line.long 0x0 "ETH_DMAC1IER,Channel 1 interrupt enable register" bitfld.long 0x0 15. "NIE,Normal Interrupt Summary Enable" "0: Transmit Interrupt,?" newline bitfld.long 0x0 14. "AIE,Abnormal Interrupt Summary Enable" "?,1: Transmit Process Stopped" newline bitfld.long 0x0 13. "CDEE,Context Descriptor Error Enable" "0,1" newline bitfld.long 0x0 12. "FBEE,Fatal Bus Error Enable" "0,1" newline bitfld.long 0x0 11. "ERIE,Early Receive Interrupt Enable" "0,1" newline bitfld.long 0x0 10. "ETIE,Early Transmit Interrupt Enable" "0,1" newline bitfld.long 0x0 9. "RWTE,Receive Watchdog Timeout Enable" "0,1" newline bitfld.long 0x0 8. "RSE,Receive Stopped Enable" "0,1" newline bitfld.long 0x0 7. "RBUE,Receive Buffer Unavailable Enable" "0,1" newline bitfld.long 0x0 6. "RIE,Receive Interrupt Enable" "0,1" newline bitfld.long 0x0 2. "TBUE,Transmit Buffer Unavailable Enable" "0,1" newline bitfld.long 0x0 1. "TXSE,Transmit Stopped Enable" "0,1" newline bitfld.long 0x0 0. "TIE,Transmit Interrupt Enable" "0,1" rgroup.long 0x11C4++0x3 line.long 0x0 "ETH_DMAC1CATXDR,Channel 1 current application transmit descriptor register" hexmask.long 0x0 0.--31. 1. "CURTDESAPTR,Application Transmit Descriptor Address Pointer" rgroup.long 0x11D4++0x3 line.long 0x0 "ETH_DMAC1CATXBR,Channel 1 current application transmit buffer register" hexmask.long 0x0 0.--31. 1. "CURTBUFAPTR,Application Transmit Buffer Address Pointer" group.long 0x11E0++0x3 line.long 0x0 "ETH_DMAC1SR,Channel 1 status register" rbitfld.long 0x0 19.--21. "REB,Rx DMA Error Bits" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 16.--18. "TEB,Tx DMA Error Bits" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 15. "NIS,Normal Interrupt Summary" "0: Transmit Interrupt,?" newline bitfld.long 0x0 14. "AIS,Abnormal Interrupt Summary" "?,1: Transmit Process Stopped" newline bitfld.long 0x0 13. "CDE,Context Descriptor Error" "0,1" newline bitfld.long 0x0 12. "FBE,Fatal Bus Error" "0,1" newline bitfld.long 0x0 11. "ERI,Early Receive Interrupt" "0,1" newline bitfld.long 0x0 10. "ETI,Early Transmit Interrupt" "0,1" newline bitfld.long 0x0 9. "RWT,Receive Watchdog Timeout" "0,1" newline bitfld.long 0x0 8. "RPS,Receive Process Stopped" "0,1" newline bitfld.long 0x0 7. "RBU,Receive Buffer Unavailable" "0,1" newline bitfld.long 0x0 6. "RI,Receive Interrupt" "0,1" newline bitfld.long 0x0 2. "TBU,Transmit Buffer Unavailable" "0,1" newline bitfld.long 0x0 1. "TPS,Transmit Process Stopped" "0,1" newline bitfld.long 0x0 0. "TI,Transmit Interrupt" "0,1" rgroup.long 0x11EC++0x3 line.long 0x0 "ETH_DMAC1MFCR,Channel 1 missed frame count register" bitfld.long 0x0 15. "MFCO,Overflow status of the MFC Counter" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "MFC,Dropped Packet Counters" tree.end endif sif (cpuis("STM32MP13*")) tree "ETH2" base ad:0x5800E000 group.long 0x0++0x17 line.long 0x0 "ETH_MACCR,Operating mode configuration register" bitfld.long 0x0 31. "ARPEN,ARP Offload Enable" "0,1" newline bitfld.long 0x0 28.--30. "SARC,Source Address Insertion or Replacement Control" "0: Reserved must not be used,1: Reserved must not be used.,2: the MAC inserts the content of the MAC Address 0..,3: the MAC replaces the content of the MAC Address..,4: Reserved must not be used,5: Reserved must not be used.,6: the MAC inserts the content of the MAC Address 1..,7: the MAC replaces the content of the MAC Address.." newline bitfld.long 0x0 27. "IPC,Checksum Offload" "0,1" newline bitfld.long 0x0 24.--26. "IPG,Inter-Packet Gap" "0: 96 bit times,1: 88 bit times,2: 80 bit times,?,?,?,?,7: 40 bit times" newline bitfld.long 0x0 23. "GPSLCE,Giant Packet Size Limit Control Enable" "0,1" newline bitfld.long 0x0 22. "S2KP,IEEE 802.3as Support for 2K Packets" "0,1" newline bitfld.long 0x0 21. "CST,CRC stripping for Type packets" "0,1" newline bitfld.long 0x0 20. "ACS,Automatic Pad or CRC Stripping" "0,1" newline bitfld.long 0x0 19. "WD,Watchdog Disable" "0,1" newline bitfld.long 0x0 18. "BE,Packet Burst Enable" "0,1" newline bitfld.long 0x0 17. "JD,Jabber Disable" "0,1" newline bitfld.long 0x0 16. "JE,Jumbo Packet Enable" "0,1" newline bitfld.long 0x0 15. "PS,Port Select" "0: For 1000 Mbps operations,1: For 10 or 100 Mbps operations" newline bitfld.long 0x0 14. "FES,MAC Speed" "0: 10 Mbps,1: 100 Mbps" newline bitfld.long 0x0 13. "DM,Duplex Mode" "0,1" newline bitfld.long 0x0 12. "LM,Loopback Mode" "0,1" newline bitfld.long 0x0 11. "ECRSFD,Enable Carrier Sense Before Transmission in Full-Duplex Mode" "0,1" newline bitfld.long 0x0 10. "DO,Disable Receive Own" "0,1" newline bitfld.long 0x0 9. "DCRS,Disable Carrier Sense During Transmission" "0,1" newline bitfld.long 0x0 8. "DR,Disable Retry" "0,1" newline bitfld.long 0x0 5.--6. "BL,Back-Off Limit" "0: k= min (n 10),1: k = min (n 8),2: k = min (n 4),3: k = min (n 1)" newline bitfld.long 0x0 4. "DC,Deferral Check" "0,1" newline bitfld.long 0x0 2.--3. "PRELEN,Preamble Length for Transmit packets" "0: 7 bytes of preamble,1: 5 bytes of preamble,2: 3 bytes of preamble,3: Reserved must not be used" newline bitfld.long 0x0 1. "TE,Transmitter Enable" "0,1" newline bitfld.long 0x0 0. "RE,Receiver Enable" "0,1" line.long 0x4 "ETH_MACECR,Extended operating mode configuration register" hexmask.long.byte 0x4 25.--29. 1. "EIPG,Extended Inter-Packet Gap" newline bitfld.long 0x4 24. "EIPGEN,Extended Inter-Packet Gap Enable" "0,1" newline bitfld.long 0x4 18. "USP,Unicast Slow Protocol Packet Detect" "0,1" newline bitfld.long 0x4 17. "SPEN,Slow Protocol Detection Enable" "0,1" newline bitfld.long 0x4 16. "DCRCC,Disable CRC Checking for Received Packets" "0,1" newline hexmask.long.word 0x4 0.--13. 1. "GPSL,Giant Packet Size Limit" line.long 0x8 "ETH_MACPFR,Packet filtering control register" bitfld.long 0x8 31. "RA,Receive All" "0,1" newline bitfld.long 0x8 21. "DNTU,Drop Non-TCP/UDP over IP Packets" "0,1" newline bitfld.long 0x8 20. "IPFE,Layer 3 and Layer 4 Filter Enable" "0,1" newline bitfld.long 0x8 16. "VTFE,VLAN Tag Filter Enable" "0,1" newline bitfld.long 0x8 10. "HPF,Hash or Perfect Filter" "0,1" newline bitfld.long 0x8 9. "SAF,Source Address Filter Enable" "0,1" newline bitfld.long 0x8 8. "SAIF,SA Inverse Filtering" "0,1" newline bitfld.long 0x8 6.--7. "PCF,Pass Control Packets" "0: The MAC filters all control packets from..,1: The MAC forwards all control packets except..,2: The MAC forwards all control packets to the..,3: The MAC forwards the control packets that pass.." newline bitfld.long 0x8 5. "DBF,Disable Broadcast Packets" "0,1" newline bitfld.long 0x8 4. "PM,Pass All Multicast" "0,1" newline bitfld.long 0x8 3. "DAIF,DA Inverse Filtering" "0,1" newline bitfld.long 0x8 2. "HMC,Hash Multicast" "0,1" newline bitfld.long 0x8 1. "HUC,Hash Unicast" "0,1" newline bitfld.long 0x8 0. "PR,Promiscuous Mode" "0,1" line.long 0xC "ETH_MACWTR,Watchdog timeout register" bitfld.long 0xC 8. "PWE,Programmable Watchdog Enable" "0,1" newline hexmask.long.byte 0xC 0.--3. 1. "WTO,Watchdog Timeout" line.long 0x10 "ETH_MACHT0R,Hash Table 0 register" hexmask.long 0x10 0.--31. 1. "HT31T0,MAC Hash Table First 32 Bits" line.long 0x14 "ETH_MACHT1R,Hash Table 1 register" hexmask.long 0x14 0.--31. 1. "HT63T32,MAC Hash Table Second 32 Bits" group.long 0x50++0x3 line.long 0x0 "ETH_MACVTR,VLAN tag register" bitfld.long 0x0 31. "EIVLRXS,Enable Inner VLAN Tag in Rx Status" "0,1" newline bitfld.long 0x0 28.--29. "EIVLS,Enable Inner VLAN Tag Stripping on Receive" "0: Do not strip,1: Strip if VLAN filter passes,2: Strip if VLAN filter fails,3: Always strip" newline bitfld.long 0x0 27. "ERIVLT,Enable Inner VLAN Tag" "0,1" newline bitfld.long 0x0 26. "EDVLP,Enable Double VLAN Processing" "0,1" newline bitfld.long 0x0 25. "VTHM,VLAN Tag Hash Table Match Enable" "0,1" newline bitfld.long 0x0 24. "EVLRXS,Enable VLAN Tag in Rx status" "0,1" newline bitfld.long 0x0 21.--22. "EVLS,Enable VLAN Tag Stripping on Receive" "0: Do not strip,1: Strip if VLAN filter passes,2: Strip if VLAN filter fails,3: Always strip" newline bitfld.long 0x0 20. "DOVLTC,Disable VLAN Type Check" "0,1" newline bitfld.long 0x0 19. "ERSVLM,Enable Receive S-VLAN Match" "0,1" newline bitfld.long 0x0 18. "ESVL,Enable S-VLAN" "0,1" newline bitfld.long 0x0 17. "VTIM,VLAN Tag Inverse Match Enable" "0,1" newline bitfld.long 0x0 16. "ETV,Enable 12-Bit VLAN Tag Comparison" "0,1" newline hexmask.long.word 0x0 0.--15. 1. "VL,VLAN Tag Identifier for Receive Packets" group.long 0x58++0x3 line.long 0x0 "ETH_MACVHTR,VLAN Hash table register" hexmask.long.word 0x0 0.--15. 1. "VLHT,VLAN Hash Table" group.long 0x60++0x7 line.long 0x0 "ETH_MACVIR,VLAN inclusion register" bitfld.long 0x0 20. "VLTI,VLAN Tag Input" "0,1" newline bitfld.long 0x0 19. "CSVL,C-VLAN or S-VLAN" "0,1" newline bitfld.long 0x0 18. "VLP,VLAN Priority Control" "0,1" newline bitfld.long 0x0 16.--17. "VLC,VLAN Tag Control in Transmit Packets" "0: No VLAN tag deletion insertion or replacement,1: VLAN tag deletion. The MAC removes the VLAN type..,2: VLAN tag insertion. The MAC inserts VLT in bytes..,3: VLAN tag replacement. The MAC replaces VLT in.." newline hexmask.long.word 0x0 0.--15. 1. "VLT,VLAN Tag for Transmit Packets" line.long 0x4 "ETH_MACIVIR,Inner VLAN inclusion register" bitfld.long 0x4 20. "VLTI,VLAN Tag Input" "0,1" newline bitfld.long 0x4 19. "CSVL,C-VLAN or S-VLAN" "0,1" newline bitfld.long 0x4 18. "VLP,VLAN Priority Control" "0,1" newline bitfld.long 0x4 16.--17. "VLC,VLAN Tag Control in Transmit Packets" "0: No VLAN tag deletion insertion or replacement,1: VLAN tag deletion,2: VLAN tag insertion,3: VLAN tag replacement" newline hexmask.long.word 0x4 0.--15. 1. "VLT,VLAN Tag for Transmit Packets" group.long 0x70++0x3 line.long 0x0 "ETH_MACQ0TXFCR,Tx Queue 0 flow control register" hexmask.long.word 0x0 16.--31. 1. "PT,Pause Time" newline bitfld.long 0x0 7. "DZPQ,Disable Zero-Quanta Pause" "0,1" newline bitfld.long 0x0 4.--6. "PLT,Pause Low Threshold" "0: Pause Time minus 4 Slot Times (PT -4 slot times),1: Pause Time minus 28 Slot Times (PT -28 slot times),2: Pause Time minus 36 Slot Times (PT -36 slot times),3: Pause Time minus 144 Slot Times (PT -144 slot..,4: Pause Time minus 256 Slot Times (PT -256 slot..,5: Pause Time minus 512 Slot Times (PT -512 slot..,6: Reserved must not be used,7: Reserved must not be used" newline bitfld.long 0x0 1. "TFE,Transmit Flow Control Enable" "0,1" newline bitfld.long 0x0 0. "FCB_BPA,Flow Control Busy or Backpressure Activate" "0,1" group.long 0x90++0x3 line.long 0x0 "ETH_MACRXFCR,Rx flow control register" bitfld.long 0x0 1. "UP,Unicast Pause Packet Detect" "0,1" newline bitfld.long 0x0 0. "RFE,Receive Flow Control Enable" "0,1" rgroup.long 0x98++0x3 line.long 0x0 "ETH_MACTXQPMR,Tx queue priority mapping 0 register" hexmask.long.byte 0x0 8.--15. 1. "PSTQ1,Priorities Selected in Transmit Queue 1" newline hexmask.long.byte 0x0 0.--7. 1. "PSTQ0,Priorities Selected in Transmit Queue 0" group.long 0xA8++0x3 line.long 0x0 "ETH_MACRXQC2R,Rx queue control 2 register" hexmask.long.byte 0x0 8.--15. 1. "PSRQ1,Priorities Selected in the Receive Queue 1" newline hexmask.long.byte 0x0 0.--7. 1. "PSRQ0,Priorities Selected in the Receive Queue 0" rgroup.long 0xB0++0x3 line.long 0x0 "ETH_MACISR,Interrupt status register" bitfld.long 0x0 14. "RXSTSIS,Receive Status Interrupt" "0,1" newline bitfld.long 0x0 13. "TXSTSIS,Transmit Status Interrupt" "0,1" newline bitfld.long 0x0 12. "TSIS,Timestamp Interrupt Status" "0,1" newline bitfld.long 0x0 10. "MMCTXIS,MMC Transmit Interrupt Status" "0,1" newline bitfld.long 0x0 9. "MMCRXIS,MMC Receive Interrupt Status" "0,1" newline bitfld.long 0x0 8. "MMCIS,MMC Interrupt Status" "0,1" newline bitfld.long 0x0 5. "LPIIS,LPI Interrupt Status" "0,1" newline bitfld.long 0x0 4. "PMTIS,PMT Interrupt Status" "0,1" newline bitfld.long 0x0 3. "PHYIS,PHY Interrupt" "0,1" newline bitfld.long 0x0 0. "RGSMIIIS,RGMII or SMII Interrupt Status" "0,1" group.long 0xB4++0x3 line.long 0x0 "ETH_MACIER,Interrupt enable register" bitfld.long 0x0 14. "RXSTSIE,Receive Status Interrupt Enable" "0,1" newline bitfld.long 0x0 13. "TXSTSIE,Transmit Status Interrupt Enable" "0,1" newline bitfld.long 0x0 12. "TSIE,Timestamp Interrupt Enable" "0,1" newline bitfld.long 0x0 5. "LPIIE,LPI Interrupt Enable" "0,1" newline bitfld.long 0x0 4. "PMTIE,PMT Interrupt Enable" "0,1" newline bitfld.long 0x0 3. "PHYIE,PHY Interrupt Enable" "0,1" newline bitfld.long 0x0 0. "RGSMIIIE,RGMII or SMII Interrupt Enable" "0,1" rgroup.long 0xB8++0x3 line.long 0x0 "ETH_MACRXTXSR,Rx Tx status register" bitfld.long 0x0 8. "RWT,Receive Watchdog Timeout" "0,1" newline bitfld.long 0x0 5. "EXCOL,Excessive Collisions" "0,1" newline bitfld.long 0x0 4. "LCOL,Late Collision" "0,1" newline bitfld.long 0x0 3. "EXDEF,Excessive Deferral" "0,1" newline bitfld.long 0x0 2. "LCARR,Loss of Carrier" "0,1" newline bitfld.long 0x0 1. "NCARR,No Carrier" "0,1" newline bitfld.long 0x0 0. "TJT,Transmit Jabber Timeout" "0,1" group.long 0xC0++0x7 line.long 0x0 "ETH_MACPCSR," bitfld.long 0x0 31. "RWKFILTRST,Remote wakeup Packet Filter Register Pointer Reset" "0,1" newline hexmask.long.byte 0x0 24.--28. 1. "RWKPTR,Remote wakeup FIFO Pointer" newline bitfld.long 0x0 10. "RWKPFE,Remote wakeup Packet Forwarding Enable" "0,1" newline bitfld.long 0x0 9. "GLBLUCAST,Global Unicast" "0,1" newline rbitfld.long 0x0 6. "RWKPRCVD,Remote wakeup Packet Received" "0,1" newline rbitfld.long 0x0 5. "MGKPRCVD,Magic Packet Received" "0,1" newline bitfld.long 0x0 2. "RWKPKTEN,Remote wakeup Packet Enable" "0,1" newline bitfld.long 0x0 1. "MGKPKTEN,Magic Packet Enable" "0,1" newline bitfld.long 0x0 0. "PWRDWN,Power Down" "0,1" line.long 0x4 "ETH_MACRWKPFR," hexmask.long 0x4 0.--31. 1. "MACRWKPFR,Remote wakeup packet filter" group.long 0xD0++0xF line.long 0x0 "ETH_MACLCSR,LPI control status register" bitfld.long 0x0 20. "LPITE,LPI Timer Enable" "0,1" newline bitfld.long 0x0 19. "LPITXA,LPI Tx Automate" "0,1" newline bitfld.long 0x0 18. "PLSEN,PHY Link Status Enable" "0,1" newline bitfld.long 0x0 17. "PLS,PHY Link Status" "0,1" newline bitfld.long 0x0 16. "LPIEN,LPI Enable" "0,1" newline rbitfld.long 0x0 9. "RLPIST,Receive LPI State" "0,1" newline rbitfld.long 0x0 8. "TLPIST,Transmit LPI State" "0,1" newline rbitfld.long 0x0 3. "RLPIEX,Receive LPI Exit" "0,1" newline rbitfld.long 0x0 2. "RLPIEN,Receive LPI Entry" "0,1" newline rbitfld.long 0x0 1. "TLPIEX,Transmit LPI Exit" "0,1" newline rbitfld.long 0x0 0. "TLPIEN,Transmit LPI Entry" "0,1" line.long 0x4 "ETH_MACLTCR,LPI timers control register" hexmask.long.word 0x4 16.--25. 1. "LST,LPI LS Timer" newline hexmask.long.word 0x4 0.--15. 1. "TWT,LPI TW Timer" line.long 0x8 "ETH_MACLETR,LPI entry timer register" hexmask.long.tbyte 0x8 3.--19. 1. "LPIET,LPI Entry Timer" line.long 0xC "ETH_MAC1USTCR,FIXME 1-microsecond-tick counter register" hexmask.long.word 0xC 0.--11. 1. "TIC_1US_CNTR,1 µs tick Counter" group.long 0xF8++0x3 line.long 0x0 "ETH_MACPHYCSR,PHYIF control status register" rbitfld.long 0x0 20. "JABTO,Jabber Timeout" "0,1" newline rbitfld.long 0x0 19. "LNKSTS,Link Status" "0,1" newline rbitfld.long 0x0 17.--18. "LNKSPEED,Link Speed" "0: 2.5 MHz,1: 25 MHz,2: 125 MHz,?" newline rbitfld.long 0x0 16. "LNKMOD,Link Mode" "0: Half-duplex mode,1: Full-duplex mode" newline bitfld.long 0x0 1. "LUD,Link Up or Down" "0: Link Down,1: Link Up" newline bitfld.long 0x0 0. "TC,Transmit Configuration in RGMII" "0,1" rgroup.long 0x110++0x7 line.long 0x0 "ETH_MACVR,Version register" hexmask.long.byte 0x0 8.--15. 1. "USERVER,ST-defined version" newline hexmask.long.byte 0x0 0.--7. 1. "SNPSVER,IP version" line.long 0x4 "ETH_MACDR,Debug register" bitfld.long 0x4 17.--18. "TFCSTS,MAC Transmit Packet Controller Status" "0: Idle state,1: Waiting for one of the following:,2: Generating and transmitting a Pause control..,3: Transferring input packet for transmission" newline bitfld.long 0x4 16. "TPESTS,MAC GMII or MII Transmit Protocol Engine Status" "0,1" newline bitfld.long 0x4 1.--2. "RFCFCSTS,MAC Receive Packet Controller FIFO Status" "0,1,2,3" newline bitfld.long 0x4 0. "RPESTS,MAC GMII or MII Receive Protocol Engine Status" "0,1" rgroup.long 0x11C++0xB line.long 0x0 "ETH_MACHWF0R,HW feature 0 register" bitfld.long 0x0 28.--30. "ACTPHYSEL,Active PHY Selected" "0: GMII or MII,1: RGMII,2: SGMII,3: TBI,4: RMII,5: RTBI,6: SMII,?" newline bitfld.long 0x0 27. "SAVLANINS,Source Address or VLAN Insertion Enable" "0,1" newline bitfld.long 0x0 25.--26. "TSSTSSEL,Timestamp System Time Source" "0: Reserved must not be used,1: Internal,2: External,3: Both" newline bitfld.long 0x0 24. "MACADR64SEL,MAC Addresses 64-127 Selected" "0,1" newline bitfld.long 0x0 23. "MACADR32SEL,MAC Addresses 32-63 Selected" "0,1" newline hexmask.long.byte 0x0 18.--22. 1. "ADDMACADRSEL,MAC Addresses 1-31 Selected" newline bitfld.long 0x0 16. "RXCOESEL,Receive Checksum Offload Enabled" "0,1" newline bitfld.long 0x0 14. "TXCOESEL,Transmit Checksum Offload Enabled" "0,1" newline bitfld.long 0x0 13. "EEESEL,Energy Efficient Ethernet Enabled" "0,1" newline bitfld.long 0x0 12. "TSSEL,IEEE 1588-2008 Timestamp Enabled" "0,1" newline bitfld.long 0x0 9. "ARPOFFSEL,ARP Offload Enabled" "0,1" newline bitfld.long 0x0 8. "MMCSEL,RMON Module Enable" "0,1" newline bitfld.long 0x0 7. "MGKSEL,PMT Magic Packet Enable" "0,1" newline bitfld.long 0x0 6. "RWKSEL,PMT Remote Wakeup Packet Enable" "0,1" newline bitfld.long 0x0 5. "SMASEL,SMA (MDIO) Interface" "0,1" newline bitfld.long 0x0 4. "VLHASH,VLAN Hash Filter Selected" "0,1" newline bitfld.long 0x0 3. "PCSSEL,PCS Registers (TBI SGMII or RTBI PHY interface)" "0,1" newline bitfld.long 0x0 2. "HDSEL,Half-duplex Support" "0,1" newline bitfld.long 0x0 1. "GMIISEL,1000 Mbps Support" "0,1" newline bitfld.long 0x0 0. "MIISEL,10 or 100 Mbps Support" "0,1" line.long 0x4 "ETH_MACHWF1R,HW feature 1 register" hexmask.long.byte 0x4 27.--30. 1. "L3L4FNUM,Total number of L3 or L4 Filters" newline bitfld.long 0x4 24.--25. "HASHTBLSZ,Hash Table Size" "0: No Hash table,1: 64,2: 128,3: 256" newline bitfld.long 0x4 20. "AVSEL,AV Feature Enable" "0,1" newline bitfld.long 0x4 19. "DBGMEMA,DMA Debug Registers Enable" "0,1" newline bitfld.long 0x4 18. "TSOEN,TCP Segmentation Offload Enable" "0,1" newline bitfld.long 0x4 17. "SPHEN,Split Header Feature Enable" "0,1" newline bitfld.long 0x4 16. "DCBEN,DCB Feature Enable" "0,1" newline bitfld.long 0x4 14.--15. "ADDR64,Address width" "0: 32 bits,?,?,?" newline bitfld.long 0x4 13. "ADVTHWORD,IEEE 1588 High Word Register Enable" "0,1" newline bitfld.long 0x4 12. "PTOEN,PTP Offload Enable" "0,1" newline bitfld.long 0x4 11. "OSTEN,One-Step Timestamping Enable" "0,1" newline hexmask.long.byte 0x4 6.--10. 1. "TXFIFOSIZE,MTL Transmit FIFO Size" newline hexmask.long.byte 0x4 0.--4. 1. "RXFIFOSIZE,MTL Receive FIFO Size" line.long 0x8 "ETH_MACHWF2R,HW feature 2 register" bitfld.long 0x8 28.--30. "AUXSNAPNUM,Number of Auxiliary Snapshot Inputs" "0: No auxiliary input,1: 1 auxiliary input,2: 2 auxiliary inputs,3: 3 auxiliary inputs,4: 4 auxiliary inputs,5: Reserved must not be used,6: Reserved must not be used,7: Reserved must not be used" newline bitfld.long 0x8 24.--26. "PPSOUTNUM,Number of PPS Outputs" "0: No PPS output,1: 1 PPS output,2: 2 PPS outputs,3: 3 PPS outputs,4: 4 PPS outputs,5: Reserved must not be used,6: Reserved must not be used,7: Reserved must not be used" newline hexmask.long.byte 0x8 18.--21. 1. "TXCHCNT,Number of DMA Transmit Channels" newline hexmask.long.byte 0x8 12.--15. 1. "RXCHCNT,Number of DMA Receive Channels" newline hexmask.long.byte 0x8 6.--9. 1. "TXQCNT,Number of MTL Transmit Queues" newline hexmask.long.byte 0x8 0.--3. 1. "RXQCNT,Number of MTL Receive Queues" group.long 0x128++0x3 line.long 0x0 "ETH_MACHWF3R,HW feature 3 register" bitfld.long 0x0 5. "DVLAN,Number of auxiliary snapshot inputs" "0,1" newline bitfld.long 0x0 4. "CBTISEL,Queue/Channel based VLAN tag insertion on Tx enable" "0,1" newline rbitfld.long 0x0 0.--2. "NRVF,Number of Extended VLAN Tag Filters Enabled" "0: No Extended Rx VLAN Filters,1: 4 Extended Rx VLAN Filters,2: 8 Extended Rx VLAN Filters,3: 16 Extended Rx VLAN Filters,4: 24 Extended Rx VLAN Filters,5: 32 Extended Rx VLAN Filters,6: Reserved must not be used,7: Reserved must not be used" group.long 0x200++0x7 line.long 0x0 "ETH_MACMDIOAR,MDIO address register" bitfld.long 0x0 27. "PSE,Preamble Suppression Enable" "0,1" newline bitfld.long 0x0 26. "BTB,Back to Back transactions" "0,1" newline hexmask.long.byte 0x0 21.--25. 1. "PA,Physical Layer Address" newline hexmask.long.byte 0x0 16.--20. 1. "RDA,Register/Device Address" newline bitfld.long 0x0 12.--14. "NTC,Number of Training Clocks" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 8.--11. 1. "CR,CSR Clock Range" newline bitfld.long 0x0 4. "SKAP,Skip Address Packet" "0,1" newline bitfld.long 0x0 2.--3. "GOC,GMII Operation Command" "0: Reserved must not be used,1: Write,2: Post Read Increment Address for Clause 45 PHY,3: Read" newline bitfld.long 0x0 1. "C45E,Clause 45 PHY Enable" "0,1" newline bitfld.long 0x0 0. "GB,GMII Busy" "0,1" line.long 0x4 "ETH_MACMDIODR,MDIO data register" hexmask.long.word 0x4 16.--31. 1. "RA,Register Address" newline hexmask.long.word 0x4 0.--15. 1. "GD,GMII Data" group.long 0x210++0x3 line.long 0x0 "ETH_MACARPAR,ARP address register" hexmask.long 0x0 0.--31. 1. "ARPPA,ARP Protocol Address" group.long 0x230++0x3 line.long 0x0 "ETH_MACCSRSWCR,CSR software control register" bitfld.long 0x0 8. "SEEN,Slave Error Response Enable" "0,1" newline bitfld.long 0x0 0. "RCWE,Register Clear on Write 1 Enable" "0,1" group.long 0x300++0x1F line.long 0x0 "ETH_MACA0HR,Address 0 high register" rbitfld.long 0x0 31. "AE,Address Enable" "0,1" newline hexmask.long.word 0x0 0.--15. 1. "ADDRHI,MAC Address0[47:32]" line.long 0x4 "ETH_MACA0LR,Address 0 low register" hexmask.long 0x4 0.--31. 1. "ADDRLO,MAC Address x [31:0] (x = 0 to 3)" line.long 0x8 "ETH_MACA1HR,Address 1 high register" bitfld.long 0x8 31. "AE,Address Enable" "0,1" newline bitfld.long 0x8 30. "SA,Source Address" "0,1" newline hexmask.long.byte 0x8 24.--29. 1. "MBC,Mask Byte Control" newline hexmask.long.word 0x8 0.--15. 1. "ADDRHI,MAC Address1 [47:32]" line.long 0xC "ETH_MACA1LR,Address 1 low register" hexmask.long 0xC 0.--31. 1. "ADDRLO,MAC Address x [31:0] (x = 0 to 3)" line.long 0x10 "ETH_MACA2HR,Address 2 high register" bitfld.long 0x10 31. "AE,Address Enable" "0,1" newline bitfld.long 0x10 30. "SA,Source Address" "0,1" newline hexmask.long.byte 0x10 24.--29. 1. "MBC,Mask Byte Control" newline hexmask.long.word 0x10 0.--15. 1. "ADDRHI,MAC Address1 [47:32]" line.long 0x14 "ETH_MACA2LR,Address 2 low register" hexmask.long 0x14 0.--31. 1. "ADDRLO,MAC Address x [31:0] (x = 0 to 3)" line.long 0x18 "ETH_MACA3HR,Address 3 high register" bitfld.long 0x18 31. "AE,Address Enable" "0,1" newline bitfld.long 0x18 30. "SA,Source Address" "0,1" newline hexmask.long.byte 0x18 24.--29. 1. "MBC,Mask Byte Control" newline hexmask.long.word 0x18 0.--15. 1. "ADDRHI,MAC Address1 [47:32]" line.long 0x1C "ETH_MACA3LR,Address 3 low register" hexmask.long 0x1C 0.--31. 1. "ADDRLO,MAC Address x [31:0] (x = 0 to 3)" group.long 0x700++0x3 line.long 0x0 "ETH_MMC_CONTROL,MMC control register" bitfld.long 0x0 8. "UCDBC,Update MMC Counters for Dropped Broadcast Packets" "0,1" newline bitfld.long 0x0 5. "CNTPRSTLVL,Full-Half Preset" "0,1" newline bitfld.long 0x0 4. "CNTPRST,Counters Preset" "0,1" newline bitfld.long 0x0 3. "CNTFREEZ,MMC Counter Freeze" "0,1" newline bitfld.long 0x0 2. "RSTONRD,Reset on Read" "0,1" newline bitfld.long 0x0 1. "CNTSTOPRO,Counter Stop Rollover" "0,1" newline bitfld.long 0x0 0. "CNTRST,Counters Reset" "0,1" rgroup.long 0x704++0x7 line.long 0x0 "ETH_MMC_RX_INTERRUPT,MMC Rx interrupt register" bitfld.long 0x0 27. "RXLPITRCIS,MMC Receive LPI transition counter interrupt status" "0,1" newline bitfld.long 0x0 26. "RXLPIUSCIS,MMC Receive LPI microsecond counter interrupt status" "0,1" newline bitfld.long 0x0 17. "RXUCGPIS,MMC Receive Unicast Good Packet Counter Interrupt Status" "0,1" newline bitfld.long 0x0 6. "RXALGNERPIS,MMC Receive Alignment Error Packet Counter Interrupt Status" "0,1" newline bitfld.long 0x0 5. "RXCRCERPIS,MMC Receive CRC Error Packet Counter Interrupt Status" "0,1" line.long 0x4 "ETH_MMC_TX_INTERRUPT,MMC Tx interrupt register" bitfld.long 0x4 27. "TXLPITRCIS,MMC Transmit LPI transition counter interrupt status" "0,1" newline bitfld.long 0x4 26. "TXLPIUSCIS,MMC Transmit LPI microsecond counter interrupt status" "0,1" newline bitfld.long 0x4 21. "TXGPKTIS,MMC Transmit Good Packet Counter Interrupt Status" "0,1" newline bitfld.long 0x4 15. "TXMCOLGPIS,MMC Transmit Multiple Collision Good Packet Counter Interrupt Status" "0,1" newline bitfld.long 0x4 14. "TXSCOLGPIS,MMC Transmit Single Collision Good Packet Counter Interrupt Status" "0,1" group.long 0x70C++0x7 line.long 0x0 "ETH_MMC_RX_INTERRUPT_MASK,MMC Rx interrupt mask register" rbitfld.long 0x0 27. "RXLPITRCIM,MMC Receive LPI transition counter interrupt Mask" "0,1" newline bitfld.long 0x0 26. "RXLPIUSCIM,MMC Receive LPI microsecond counter interrupt Mask" "0,1" newline bitfld.long 0x0 17. "RXUCGPIM,MMC Receive Unicast Good Packet Counter Interrupt Mask" "0,1" newline bitfld.long 0x0 6. "RXALGNERPIM,MMC Receive Alignment Error Packet Counter Interrupt Mask" "0,1" newline bitfld.long 0x0 5. "RXCRCERPIM,MMC Receive CRC Error Packet Counter Interrupt Mask" "0,1" line.long 0x4 "ETH_MMC_TX_INTERRUPT_MASK,MMC Tx interrupt mask register" rbitfld.long 0x4 27. "TXLPITRCIM,MMC Transmit LPI transition counter interrupt Mask" "0,1" newline bitfld.long 0x4 26. "TXLPIUSCIM,MMC Transmit LPI microsecond counter interrupt Mask" "0,1" newline bitfld.long 0x4 21. "TXGPKTIM,MMC Transmit Good Packet Counter Interrupt Mask" "0,1" newline bitfld.long 0x4 15. "TXMCOLGPIM,MMC Transmit Multiple Collision Good Packet Counter Interrupt Mask" "0,1" newline bitfld.long 0x4 14. "TXSCOLGPIM,MMC Transmit Single Collision Good Packet Counter Interrupt Mask" "0,1" rgroup.long 0x74C++0x7 line.long 0x0 "ETH_TX_SINGLE_COLLISION_GOOD_PACKETS,Tx single collision good packets register" hexmask.long 0x0 0.--31. 1. "TXSNGLCOLG,Tx Single Collision Good Packets" line.long 0x4 "ETH_TX_MULTIPLE_COLLISION_GOOD_PACKETS,Tx multiple collision good packets register" hexmask.long 0x4 0.--31. 1. "TXMULTCOLG,Tx Multiple Collision Good Packets" rgroup.long 0x768++0x3 line.long 0x0 "ETH_TX_PACKET_COUNT_GOOD,Tx packet count good register" hexmask.long 0x0 0.--31. 1. "TXPKTG,Tx Packet Count Good" rgroup.long 0x794++0x7 line.long 0x0 "ETH_RX_CRC_ERROR_PACKETS,Rx CRC error packets register" hexmask.long 0x0 0.--31. 1. "RXCRCERR,Rx CRC Error Packets" line.long 0x4 "ETH_RX_ALIGNMENT_ERROR_PACKETS,Rx alignment error packets register" hexmask.long 0x4 0.--31. 1. "RXALGNERR,Rx Alignment Error Packets" rgroup.long 0x7C4++0x3 line.long 0x0 "ETH_RX_UNICAST_PACKETS_GOOD,Rx unicast packets good register" hexmask.long 0x0 0.--31. 1. "RXUCASTG,Rx Unicast Packets Good" rgroup.long 0x7EC++0xF line.long 0x0 "ETH_TX_LPI_USEC_CNTR,Tx LPI microsecond timer register" hexmask.long 0x0 0.--31. 1. "TXLPIUSC,Tx LPI Microseconds Counter" line.long 0x4 "ETH_TX_LPI_TRAN_CNTR,Tx LPI transition counter register" hexmask.long 0x4 0.--31. 1. "TXLPITRC,Tx LPI Transition counter" line.long 0x8 "ETH_RX_LPI_USEC_CNTR,Rx LPI microsecond counter register" hexmask.long 0x8 0.--31. 1. "RXLPIUSC,Rx LPI Microseconds Counter" line.long 0xC "ETH_RX_LPI_TRAN_CNTR,Rx LPI transition counter register" hexmask.long 0xC 0.--31. 1. "RXLPITRC,Rx LPI Transition counter" group.long 0x900++0x7 line.long 0x0 "ETH_MACL3L4C0R,L3 and L4 control 0 register" bitfld.long 0x0 21. "L4DPIM0,Layer 4 Destination Port Inverse Match Enable" "0,1" newline bitfld.long 0x0 20. "L4DPM0,Layer 4 Destination Port Match Enable" "0,1" newline bitfld.long 0x0 19. "L4SPIM0,Layer 4 Source Port Inverse Match Enable" "0,1" newline bitfld.long 0x0 18. "L4SPM0,Layer 4 Source Port Match Enable" "0,1" newline bitfld.long 0x0 16. "L4PEN0,Layer 4 Protocol Enable" "0,1" newline hexmask.long.byte 0x0 11.--15. 1. "L3HDBM0,Layer 3 IP DA higher bits match" newline hexmask.long.byte 0x0 6.--10. 1. "L3HSBM0,Layer 3 IP SA higher bits match" newline bitfld.long 0x0 5. "L3DAIM0,Layer 3 IP DA Inverse Match Enable" "0,1" newline bitfld.long 0x0 4. "L3DAM0,Layer 3 IP DA Match Enable" "0,1" newline bitfld.long 0x0 3. "L3SAIM0,Layer 3 IP SA Inverse Match Enable" "0,1" newline bitfld.long 0x0 2. "L3SAM0,Layer 3 IP SA Match Enable" "0,1" newline bitfld.long 0x0 0. "L3PEN0,Layer 3 Protocol Enable" "0,1" line.long 0x4 "ETH_MACL4A0R," hexmask.long.word 0x4 16.--31. 1. "L4DP0,Layer 4 Destination Port Number Field" newline hexmask.long.word 0x4 0.--15. 1. "L4SP0,Layer 4 Source Port Number Field" group.long 0x910++0xF line.long 0x0 "ETH_MACL3A00R,Layer 3 Address 0 filter 0 register" hexmask.long 0x0 0.--31. 1. "L3A00,Layer 3 Address 0 Field" line.long 0x4 "ETH_MACL3A10R,Layer3 address 1 filter 0 register" hexmask.long 0x4 0.--31. 1. "L3A10,Layer 3 Address 1 Field" line.long 0x8 "ETH_MACL3A20R,Layer3 Address 2 filter 0 register" hexmask.long 0x8 0.--31. 1. "L3A20,Layer 3 Address 2 Field" line.long 0xC "ETH_MACL3A30R,Layer3 Address 3 filter 0 register" hexmask.long 0xC 0.--31. 1. "L3A30,Layer 3 Address 3 Field" group.long 0x930++0x7 line.long 0x0 "ETH_MACL3L4C1R,L3 and L4 control 1 register" bitfld.long 0x0 21. "L4DPIM1,Layer 4 Destination Port Inverse Match Enable" "0,1" newline bitfld.long 0x0 20. "L4DPM1,Layer 4 Destination Port Match Enable" "0,1" newline bitfld.long 0x0 19. "L4SPIM1,Layer 4 Source Port Inverse Match Enable" "0,1" newline bitfld.long 0x0 18. "L4SPM1,Layer 4 Source Port Match Enable" "0,1" newline bitfld.long 0x0 16. "L4PEN1,Layer 4 Protocol Enable" "0,1" newline hexmask.long.byte 0x0 11.--15. 1. "L3HDBM1,Layer 3 IP DA higher bits match" newline hexmask.long.byte 0x0 6.--10. 1. "L3HSBM1,Layer 3 IP SA Higher Bits Match" newline bitfld.long 0x0 5. "L3DAIM1,Layer 3 IP DA Inverse Match Enable" "0,1" newline bitfld.long 0x0 4. "L3DAM1,Layer 3 IP DA Match Enable" "0,1" newline bitfld.long 0x0 3. "L3SAIM1,Layer 3 IP SA Inverse Match Enable" "0,1" newline bitfld.long 0x0 2. "L3SAM1,Layer 3 IP SA Match Enable" "0,1" newline bitfld.long 0x0 0. "L3PEN1,Layer 3 Protocol Enable" "0,1" line.long 0x4 "ETH_MACL4A1R," hexmask.long.word 0x4 16.--31. 1. "L4DP1,Layer 4 Destination Port Number Field" newline hexmask.long.word 0x4 0.--15. 1. "L4SP1,Layer 4 Source Port Number Field" group.long 0x940++0xF line.long 0x0 "ETH_MACL3A01R,Layer3 address 0 filter 1 Register" hexmask.long 0x0 0.--31. 1. "L3A01,Layer 3 Address 0 Field" line.long 0x4 "ETH_MACL3A11R,Layer3 address 1 filter 1 register" hexmask.long 0x4 0.--31. 1. "L3A11,Layer 3 Address 1 Field" line.long 0x8 "ETH_MACL3A21R,Layer3 address 2 filter 1 Register" hexmask.long 0x8 0.--31. 1. "L3A21,Layer 3 Address 2 Field" line.long 0xC "ETH_MACL3A31R,Layer3 address 3 filter 1 register" hexmask.long 0xC 0.--31. 1. "L3A31,Layer 3 Address 3 Field" group.long 0xB00++0x7 line.long 0x0 "ETH_MACTSCR,Timestamp control Register" bitfld.long 0x0 24. "TXTSSTSM,Transmit Timestamp Status Mode" "0,1" newline rbitfld.long 0x0 19. "CSC,Enable checksum correction during OST for PTP over UDP/IPv4 packets" "0,1" newline bitfld.long 0x0 18. "TSENMACADDR,Enable MAC Address for PTP Packet Filtering" "0,1" newline bitfld.long 0x0 16.--17. "SNAPTYPSEL,Select PTP packets for Taking Snapshots" "0,1,2,3" newline bitfld.long 0x0 15. "TSMSTRENA,Enable Snapshot for Messages Relevant to Master" "0,1" newline bitfld.long 0x0 14. "TSEVNTENA,Enable Timestamp Snapshot for Event Messages" "0,1" newline bitfld.long 0x0 13. "TSIPV4ENA,Enable Processing of PTP Packets Sent over IPv4-UDP" "0,1" newline bitfld.long 0x0 12. "TSIPV6ENA,Enable Processing of PTP Packets Sent over IPv6-UDP" "0,1" newline bitfld.long 0x0 11. "TSIPENA,Enable Processing of PTP over Ethernet Packets" "0,1" newline bitfld.long 0x0 10. "TSVER2ENA,Enable PTP Packet Processing for Version 2 Format" "0,1" newline bitfld.long 0x0 9. "TSCTRLSSR,Timestamp Digital or Binary Rollover Control" "0,1" newline bitfld.long 0x0 8. "TSENALL,Enable Timestamp for All Packets" "0,1" newline bitfld.long 0x0 5. "TSADDREG,Update Addend Register" "0,1" newline bitfld.long 0x0 3. "TSUPDT,Update Timestamp" "0,1" newline bitfld.long 0x0 2. "TSINIT,Initialize Timestamp" "0,1" newline bitfld.long 0x0 1. "TSCFUPDT,Fine or Coarse Timestamp Update" "0,1" newline bitfld.long 0x0 0. "TSENA,Enable Timestamp" "0,1" line.long 0x4 "ETH_MACSSIR,Sub-second increment register" hexmask.long.byte 0x4 16.--23. 1. "SSINC,Sub-second Increment Value" rgroup.long 0xB08++0x7 line.long 0x0 "ETH_MACSTSR,System time seconds register" hexmask.long 0x0 0.--31. 1. "TSS,Timestamp Second" line.long 0x4 "ETH_MACSTNR,System time nanoseconds register" hexmask.long 0x4 0.--30. 1. "TSSS,Timestamp Sub-seconds" group.long 0xB10++0xB line.long 0x0 "ETH_MACSTSUR,System time seconds update register" hexmask.long 0x0 0.--31. 1. "TSS,Timestamp Seconds" line.long 0x4 "ETH_MACSTNUR," bitfld.long 0x4 31. "ADDSUB,Add or Subtract Time" "0,1" newline hexmask.long 0x4 0.--30. 1. "TSSS,Timestamp Sub-seconds" line.long 0x8 "ETH_MACTSAR,Timestamp addend register" hexmask.long 0x8 0.--31. 1. "TSAR,Timestamp Addend Register" rgroup.long 0xB20++0x3 line.long 0x0 "ETH_MACTSSR,Timestamp status register" hexmask.long.byte 0x0 25.--29. 1. "ATSNS,Number of Auxiliary Timestamp Snapshots" newline bitfld.long 0x0 24. "ATSSTM,Auxiliary Timestamp Snapshot Trigger Missed" "0,1" newline hexmask.long.byte 0x0 16.--19. 1. "ATSSTN,Auxiliary Timestamp Snapshot Trigger Identifier" newline bitfld.long 0x0 15. "TXTSSIS,Tx Timestamp Status Interrupt Status" "0,1" newline bitfld.long 0x0 3. "TSTRGTERR0,Timestamp Target Time Error" "0,1" newline bitfld.long 0x0 2. "AUXTSTRIG,Auxiliary Timestamp Trigger Snapshot" "0,1" newline bitfld.long 0x0 1. "TSTARGT0,Timestamp Target Time Reached" "0,1" newline bitfld.long 0x0 0. "TSSOVF,Timestamp Seconds Overflow" "0,1" rgroup.long 0xB30++0x7 line.long 0x0 "ETH_MACTXTSSNR,Tx timestamp status nanoseconds register" bitfld.long 0x0 31. "TXTSSMIS,Transmit Timestamp Status Missed" "0,1" newline hexmask.long 0x0 0.--30. 1. "TXTSSLO,Transmit Timestamp Status Low" line.long 0x4 "ETH_MACTXTSSSR,Tx timestamp status seconds register" hexmask.long 0x4 0.--31. 1. "TXTSSHI,Transmit Timestamp Status High" group.long 0xB40++0x3 line.long 0x0 "ETH_MACACR,Auxiliary control register" bitfld.long 0x0 7. "ATSEN3,Auxiliary Snapshot 3 Enable" "0,1" newline bitfld.long 0x0 6. "ATSEN2,Auxiliary Snapshot 2 Enable" "0,1" newline bitfld.long 0x0 5. "ATSEN1,Auxiliary Snapshot 1 Enable" "0,1" newline bitfld.long 0x0 4. "ATSEN0,Auxiliary Snapshot 0 Enable" "0,1" newline bitfld.long 0x0 0. "ATSFC,Auxiliary Snapshot FIFO Clear" "0,1" rgroup.long 0xB48++0x7 line.long 0x0 "ETH_MACATSNR,Auxiliary timestamp nanoseconds register" hexmask.long 0x0 0.--30. 1. "AUXTSLO,Auxiliary Timestamp" line.long 0x4 "ETH_MACATSSR,Auxiliary timestamp seconds register" hexmask.long 0x4 0.--31. 1. "AUXTSHI,Auxiliary Timestamp" group.long 0xB50++0xF line.long 0x0 "ETH_MACTSIACR,Timestamp Ingress asymmetric correction register" hexmask.long 0x0 0.--31. 1. "OSTIAC,One-Step Timestamp Ingress Asymmetry Correction" line.long 0x4 "ETH_MACTSEACR,Timestamp Egress asymmetric correction register" hexmask.long 0x4 0.--31. 1. "OSTEAC,One-Step Timestamp Egress Asymmetry Correction" line.long 0x8 "ETH_MACTSICNR,Timestamp Ingress correction nanosecond register" hexmask.long 0x8 0.--31. 1. "TSIC,Timestamp Ingress Correction" line.long 0xC "ETH_MACTSECNR,Timestamp Egress correction nanosecond register" hexmask.long 0xC 0.--31. 1. "TSEC,Timestamp Egress Correction" group.long 0xB70++0x3 line.long 0x0 "ETH_MACPPSCR,PPS control register" bitfld.long 0x0 5.--6. "TRGTMODSEL0,Target Time Register Mode for PPS Output" "0: Target Time registers are programmed only for..,1: Reserved must not be used,2: Target Time registers are programmed for..,3: Target Time registers are programmed only for.." newline bitfld.long 0x0 4. "PPSEN0,Flexible PPS Output Mode Enable" "0,1" newline hexmask.long.byte 0x0 0.--3. 1. "PPSCTRL,PPS Output Frequency Control" group.long 0xB70++0x3 line.long 0x0 "ETH_MACPPSCR_alternate,PPS control register" bitfld.long 0x0 5.--6. "TRGTMODSEL0,Target Time Register Mode for PPS Output" "0: Target Time registers are programmed only for..,1: Reserved must not be used,2: Target Time registers are programmed for..,3: Target Time registers are programmed only for.." newline bitfld.long 0x0 4. "PPSEN0,Flexible PPS Output Mode Enable" "0,1" newline hexmask.long.byte 0x0 0.--3. 1. "PPSCMD,Flexible PPS Output (eth_ptp_pps_out[0]) Control" group.long 0xB80++0xF line.long 0x0 "ETH_MACPPSTTSR,PPS target time seconds register" hexmask.long 0x0 0.--31. 1. "TSTRH0,PPS Target Time Seconds Register" line.long 0x4 "ETH_MACPPSTTNR,PPS target time nanoseconds register" bitfld.long 0x4 31. "TRGTBUSY0,PPS Target Time Register Busy" "0,1" newline hexmask.long 0x4 0.--30. 1. "TTSL0,Target Time Low for PPS Register" line.long 0x8 "ETH_MACPPSIR,PPS interval register" hexmask.long 0x8 0.--31. 1. "PPSINT0,PPS Output Signal Interval" line.long 0xC "ETH_MACPPSWR,PPS width register" hexmask.long 0xC 0.--31. 1. "PPSWIDTH0,PPS Output Signal Width" group.long 0xBC0++0x13 line.long 0x0 "ETH_MACPOCR,PTP Offload control register" hexmask.long.byte 0x0 8.--15. 1. "DN,Domain Number" newline bitfld.long 0x0 6. "DRRDIS,Disable PTO Delay Request/Response response generation" "0,1" newline bitfld.long 0x0 5. "APDREQTRIG,Automatic PTP Pdelay_Req message Trigger" "0,1" newline bitfld.long 0x0 4. "ASYNCTRIG,Automatic PTP SYNC message Trigger" "0,1" newline bitfld.long 0x0 2. "APDREQEN,Automatic PTP Pdelay_Req message Enable" "0,1" newline bitfld.long 0x0 1. "ASYNCEN,Automatic PTP SYNC message Enable" "0,1" newline bitfld.long 0x0 0. "PTOEN,PTP Offload Enable" "0,1" line.long 0x4 "ETH_MACSPI0R,PTP Source Port Identity 0 Register" hexmask.long 0x4 0.--31. 1. "SPI0,Source Port Identity 0" line.long 0x8 "ETH_MACSPI1R,PTP Source port identity 1 register" hexmask.long 0x8 0.--31. 1. "SPI1,Source Port Identity 1" line.long 0xC "ETH_MACSPI2R,PTP Source port identity 2 register" hexmask.long.word 0xC 0.--15. 1. "SPI2,Source Port Identity 2" line.long 0x10 "ETH_MACLMIR,Log message interval register" hexmask.long.byte 0x10 24.--31. 1. "LMPDRI,Log Min Pdelay_Req Interval" newline bitfld.long 0x10 8.--10. "DRSYNCR,Delay_Req to SYNC Ratio" "0: DelayReq generated for every received SYNC,1: DelayReq generated every alternate reception of..,2: for every 4 SYNC messages,3: for every 8 SYNC messages,4: for every 16 SYNC messages,5: for every 32 SYNC messages,?,?" newline hexmask.long.byte 0x10 0.--7. 1. "LSI,Log Sync Interval" group.long 0xC00++0x3 line.long 0x0 "ETH_MTLOMR,Operating mode Register" bitfld.long 0x0 9. "CNTCLR,Counters Reset" "0,1" newline bitfld.long 0x0 8. "CNTPRST,Counters Preset" "0,1" newline bitfld.long 0x0 5.--6. "SCHALG,Tx Scheduling Algorithm" "0: WRR algorithm,1: Reserved must not be used.,2: Reserved must not be used.,3: Strict priority algorithm." newline bitfld.long 0x0 2. "RAA,Receive Arbitration Algorithm" "0: Strict priority (SP),1: Weighted Strict Priority (WSP)" newline bitfld.long 0x0 1. "DTXSTS,Drop Transmit Status" "0,1" rgroup.long 0xC20++0x3 line.long 0x0 "ETH_MTLISR,Interrupt status Register" bitfld.long 0x0 1. "Q1IS,Queue 1 interrupt status" "0,1" newline bitfld.long 0x0 0. "Q0IS,Queue 0 interrupt status" "0,1" group.long 0xD00++0x3 line.long 0x0 "ETH_MTLTXQ0OMR,Tx queue 0 operating mode Register" hexmask.long.byte 0x0 16.--19. 1. "TQS,Transmit queue size" newline bitfld.long 0x0 4.--6. "TTC,Transmit Threshold Control" "0: 32,1: 64,2: 96,3: 128,4: 192,5: 256,6: 384,7: 512" newline bitfld.long 0x0 2.--3. "TXQEN,Transmit Queue Enable" "0: Not enabled,?,2: Enabled,?" newline bitfld.long 0x0 1. "TSF,Transmit Store and Forward" "0,1" newline bitfld.long 0x0 0. "FTQ,Flush Transmit Queue" "0,1" rgroup.long 0xD04++0x7 line.long 0x0 "ETH_MTLTXQ0UR,Tx queue 0 underflow register" bitfld.long 0x0 11. "UFCNTOVF,Overflow Bit for Underflow Packet Counter" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "UFFRMCNT,Underflow Packet Counter" line.long 0x4 "ETH_MTLTXQ0DR,Tx queue 0 debug Register" bitfld.long 0x4 20.--22. "STXSTSF,Number of Status Words in Tx Status FIFO of Queue" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 16.--18. "PTXQ,Number of Packets in the Transmit Queue" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 5. "TXSTSFSTS,MTL Tx Status FIFO Full Status" "0,1" newline bitfld.long 0x4 4. "TXQSTS,MTL Tx Queue Not Empty Status" "0,1" newline bitfld.long 0x4 3. "TWCSTS,MTL Tx Queue Write Controller Status" "0,1" newline bitfld.long 0x4 1.--2. "TRCSTS,MTL Tx Queue Read Controller Status" "0: Idle state,1: Read state (transferring data to the MAC..,2: Waiting for pending Tx Status from the MAC..,3: Flushing the Tx queue because of the Packet.." newline bitfld.long 0x4 0. "TXQPAUSED,Transmit Queue in Pause" "0,1" rgroup.long 0xD14++0x3 line.long 0x0 "ETH_MTLTXQ0ESR,Tx queue x ETS status Register" hexmask.long.tbyte 0x0 0.--23. 1. "ABS,Average Bits per Slot" group.long 0xD18++0x3 line.long 0x0 "ETH_MTLTXQ0QWR,Tx queue 0 quantum weight register" hexmask.long.byte 0x0 0.--6. 1. "ISCQW,Quantum weight" group.long 0xD2C++0x7 line.long 0x0 "ETH_MTLQ0ICSR,Queue 0 interrupt control status Register" bitfld.long 0x0 24. "RXOIE,Receive Queue Overflow Interrupt Enable" "0,1" newline bitfld.long 0x0 16. "RXOVFIS,Receive Queue Overflow Interrupt Status" "0,1" newline bitfld.long 0x0 8. "TXUIE,Transmit Queue Underflow Interrupt Enable" "0,1" newline bitfld.long 0x0 0. "TXUNFIS,Transmit Queue Underflow Interrupt Status" "0,1" line.long 0x4 "ETH_MTLRXQ0OMR,Rx queue 0 operating mode register" rbitfld.long 0x4 20.--22. "RQS,Receive Queue Size" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 14.--16. "RFD,Threshold for Deactivating Flow Control (in half-duplex and full-duplex modes)" "0: Full minus 1 Kbyte that is FULL 1 Kbyte,1: Full minus 1.5 Kbyte that is FULL 1.5 Kbyte,2: Full minus 2 Kbytes,3: Full minus 2,4: Full minus 2,5: Full minus 2,6: Full minus 4 Kbytes,7: Full minus 4" newline bitfld.long 0x4 8.--10. "RFA,Threshold for Activating Flow Control (in half-duplex and full-duplex" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 7. "EHFC,Enable Hardware Flow Control" "0,1" newline bitfld.long 0x4 6. "DIS_TCP_EF,Disable Dropping of TCP/IP Checksum Error Packets" "0,1" newline bitfld.long 0x4 5. "RSF,Receive Queue Store and Forward" "0,1" newline bitfld.long 0x4 4. "FEP,Forward Error Packets" "0,1" newline bitfld.long 0x4 3. "FUP,Forward Undersized Good Packets" "0,1" newline bitfld.long 0x4 0.--1. "RTC,Receive Queue Threshold Control" "0: 64,1: 32,2: 96,3: 128" rgroup.long 0xD34++0x7 line.long 0x0 "ETH_MTLRXQ0MPOCR,Rx queue 0 missed packet and overflow counter register" bitfld.long 0x0 27. "MISCNTOVF,Missed Packet Counter Overflow Bit" "0,1" newline hexmask.long.word 0x0 16.--26. 1. "MISPKTCNT,Missed Packet Counter" newline bitfld.long 0x0 11. "OVFCNTOVF,Overflow Counter Overflow Bit" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "OVFPKTCNT,Overflow Packet Counter" line.long 0x4 "ETH_MTLRXQ0DR,Rx queue 0 debug register" hexmask.long.word 0x4 16.--29. 1. "PRXQ,Number of Packets in Receive Queue" newline bitfld.long 0x4 4.--5. "RXQSTS,MTL Rx Queue Fill-Level Status" "0: Rx queue empty,1: Rx queue fill-level below flow-control..,2: Rx queue fill-level above flow-control activate..,3: Rx queue full" newline bitfld.long 0x4 1.--2. "RRCSTS,MTL Rx Queue Read Controller State" "0: Idle state,1: Reading packet data,2: Reading packet status (or timestamp),3: Flushing the packet data and status" newline bitfld.long 0x4 0. "RWCSTS,MTL Rx Queue Write Controller Active Status" "0,1" group.long 0xD3C++0x7 line.long 0x0 "ETH_MTLRXQ0CR,Rx queue 0 control register" rbitfld.long 0x0 3. "RXQ_FRM_ARBIT,Receive Queue Packet Arbitration" "0,1" newline bitfld.long 0x0 0.--2. "RXQ_WEGT,Receive Queue Weight" "0,1,2,3,4,5,6,7" line.long 0x4 "ETH_MTLTXQ1OMR,Tx queue 1 operating mode Register" hexmask.long.byte 0x4 16.--19. 1. "TQS,Transmit queue size" newline bitfld.long 0x4 4.--6. "TTC,Transmit Threshold Control" "0: 32,1: 64,2: 96,3: 128,4: 192,5: 256,6: 384,7: 512" newline bitfld.long 0x4 2.--3. "TXQEN,Transmit Queue Enable" "0: Not enabled,?,2: Enabled,?" newline bitfld.long 0x4 1. "TSF,Transmit Store and Forward" "0,1" newline bitfld.long 0x4 0. "FTQ,Flush Transmit Queue" "0,1" rgroup.long 0xD44++0x7 line.long 0x0 "ETH_MTLTXQ1UR,Tx queue 1 underflow register" bitfld.long 0x0 11. "UFCNTOVF,Overflow Bit for Underflow Packet Counter" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "UFFRMCNT,Underflow Packet Counter" line.long 0x4 "ETH_MTLTXQ1DR,Tx queue 1 debug Register" bitfld.long 0x4 20.--22. "STXSTSF,Number of Status Words in Tx Status FIFO of Queue" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 16.--18. "PTXQ,Number of Packets in the Transmit Queue" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 5. "TXSTSFSTS,MTL Tx Status FIFO Full Status" "0,1" newline bitfld.long 0x4 4. "TXQSTS,MTL Tx Queue Not Empty Status" "0,1" newline bitfld.long 0x4 3. "TWCSTS,MTL Tx Queue Write Controller Status" "0,1" newline bitfld.long 0x4 1.--2. "TRCSTS,MTL Tx Queue Read Controller Status" "0: Idle state,1: Read state (transferring data to the MAC..,2: Waiting for pending Tx Status from the MAC..,3: Flushing the Tx queue because of the Packet.." newline bitfld.long 0x4 0. "TXQPAUSED,Transmit Queue in Pause" "0,1" group.long 0xD50++0x3 line.long 0x0 "ETH_MTLTXQ1ECR,Tx queue 1 ETS control Register" bitfld.long 0x0 3. "CC,Credit Control" "0,1" rgroup.long 0xD54++0x3 line.long 0x0 "ETH_MTLTXQ1ESR,Tx queue x ETS status Register" hexmask.long.tbyte 0x0 0.--23. 1. "ABS,Average Bits per Slot" group.long 0xD58++0x3 line.long 0x0 "ETH_MTLTXQ1QWR,Tx queue 1 quantum weight register" hexmask.long.byte 0x0 0.--6. 1. "ISCQW,quantum weight" group.long 0xD60++0x3 line.long 0x0 "ETH_MTLTXQ1HCR,Tx Queue 1 hiCredit register" hexmask.long 0x0 0.--28. 1. "HC,hiCredit Value" group.long 0xD6C++0x7 line.long 0x0 "ETH_MTLQ1ICSR,Queue 1 interrupt control status Register" bitfld.long 0x0 24. "RXOIE,Receive Queue Overflow Interrupt Enable" "0,1" newline bitfld.long 0x0 16. "RXOVFIS,Receive Queue Overflow Interrupt Status" "0,1" newline bitfld.long 0x0 8. "TXUIE,Transmit Queue Underflow Interrupt Enable" "0,1" newline bitfld.long 0x0 0. "TXUNFIS,Transmit Queue Underflow Interrupt Status" "0,1" line.long 0x4 "ETH_MTLRXQ1OMR,Rx queue 1 operating mode register" rbitfld.long 0x4 20.--22. "RQS,Receive Queue Size" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 14.--16. "RFD,Threshold for Deactivating Flow Control (in half-duplex and full-duplex modes)" "0: Full minus 1 Kbyte that is FULL 1 Kbyte,1: Full minus 1.5 Kbyte that is FULL 1.5 Kbyte,2: Full minus 2 Kbytes,3: Full minus 2,4: Full minus 2,5: Full minus 2,6: Full minus 4 Kbytes,7: Full minus 4" newline bitfld.long 0x4 8.--10. "RFA,Threshold for Activating Flow Control (in half-duplex and full-duplex" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 7. "EHFC,Enable Hardware Flow Control" "0,1" newline bitfld.long 0x4 6. "DIS_TCP_EF,Disable Dropping of TCP/IP Checksum Error Packets" "0,1" newline bitfld.long 0x4 5. "RSF,Receive Queue Store and Forward" "0,1" newline bitfld.long 0x4 4. "FEP,Forward Error Packets" "0,1" newline bitfld.long 0x4 3. "FUP,Forward Undersized Good Packets" "0,1" newline bitfld.long 0x4 0.--1. "RTC,Receive Queue Threshold Control" "0: 64,1: 32,2: 96,3: 128" rgroup.long 0xD74++0x7 line.long 0x0 "ETH_MTLRXQ1MPOCR,Rx queue 1 missed packet and overflow counter register" bitfld.long 0x0 27. "MISCNTOVF,Missed Packet Counter Overflow Bit" "0,1" newline hexmask.long.word 0x0 16.--26. 1. "MISPKTCNT,Missed Packet Counter" newline bitfld.long 0x0 11. "OVFCNTOVF,Overflow Counter Overflow Bit" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "OVFPKTCNT,Overflow Packet Counter" line.long 0x4 "ETH_MTLRXQ1DR,Rx queue 1 debug register" hexmask.long.word 0x4 16.--29. 1. "PRXQ,Number of Packets in Receive Queue" newline bitfld.long 0x4 4.--5. "RXQSTS,MTL Rx Queue Fill-Level Status" "0: Rx queue empty,1: Rx queue fill-level below flow-control..,2: Rx queue fill-level above flow-control activate..,3: Rx queue full" newline bitfld.long 0x4 1.--2. "RRCSTS,MTL Rx Queue Read Controller State" "0: Idle state,1: Reading packet data,2: Reading packet status (or timestamp),3: Flushing the packet data and status" newline bitfld.long 0x4 0. "RWCSTS,MTL Rx Queue Write Controller Active Status" "0,1" group.long 0xD7C++0x3 line.long 0x0 "ETH_MTLRXQ1CR,Rx queue 1 control register" rbitfld.long 0x0 3. "RXQ_FRM_ARBIT,Receive Queue Packet Arbitration" "0,1" newline bitfld.long 0x0 0.--2. "RXQ_WEGT,Receive Queue Weight" "0,1,2,3,4,5,6,7" group.long 0x1000++0x7 line.long 0x0 "ETH_DMAMR,DMA mode register" bitfld.long 0x0 16.--17. "INTM,Interrupt Mode" "0,1,2,3" newline bitfld.long 0x0 12.--14. "PR,Priority ratio" "0: The priority ratio is 1:1,1: The priority ratio is 2:1,2: The priority ratio is 3:1,3: The priority ratio is 4:1,4: The priority ratio is 5:1,5: The priority ratio is 6:1,6: The priority ratio is 7:1,7: The priority ratio is 8:1" newline bitfld.long 0x0 11. "TXPR,Transmit priority" "0,1" newline rbitfld.long 0x0 2.--4. "TAA,Transmit Arbitration Algorithm" "0: Fixed priority. In fixed priority Channel 0 has..,1: Weighted Strict Priority (WSP),2: Weighted Round-Robin (WRR),3: Reserved must not be used.,4: Reserved must not be used.,5: Reserved must not be used.,6: Reserved must not be used.,7: Reserved must not be used." newline bitfld.long 0x0 0. "SWR,Software Reset" "0,1" line.long 0x4 "ETH_DMASBMR,System bus mode register" bitfld.long 0x4 31. "EN_LPI,Enable Low Power Interface (LPI)" "0,1" newline bitfld.long 0x4 30. "LPI_XIT_PKT,Unlock on Magic Packet or Remote wakeup Packet" "0,1" newline bitfld.long 0x4 24.--25. "WR_OSR_LMT,AXI Maximum Write Outstanding Request Limit" "0,1,2,3" newline bitfld.long 0x4 16.--17. "RD_OSR_LMT,AXI Maximum Read Outstanding Request Limit" "0,1,2,3" newline bitfld.long 0x4 13. "ONEKBBE,1 Kbyte Boundary Crossing Enable for the AXI Master" "0,1" newline bitfld.long 0x4 12. "AAL,Address-Aligned Beats" "0,1" newline bitfld.long 0x4 7. "BLEN256,AXI Burst Length 256" "0,1" newline bitfld.long 0x4 6. "BLEN128,AXI Burst Length 128" "0,1" newline bitfld.long 0x4 5. "BLEN64,AXI Burst Length 64" "0,1" newline bitfld.long 0x4 4. "BLEN32,AXI Burst Length 32" "0,1" newline bitfld.long 0x4 3. "BLEN16,AXI Burst Length 16" "0,1" newline bitfld.long 0x4 2. "BLEN8,AXI Burst Length 8" "0,1" newline bitfld.long 0x4 1. "BLEN4,AXI Burst Length 4" "0,1" newline bitfld.long 0x4 0. "FB,Fixed Burst Length" "?,1: when this bit is set to 0" rgroup.long 0x1008++0x7 line.long 0x0 "ETH_DMAISR,Interrupt status register" bitfld.long 0x0 17. "MACIS,MAC Interrupt Status" "0,1" newline bitfld.long 0x0 16. "MTLIS,MTL Interrupt Status" "0,1" newline bitfld.long 0x0 1. "DC1IS,DMA Channel 1 Interrupt Status" "0,1" newline bitfld.long 0x0 0. "DC0IS,DMA Channel 0 Interrupt Status" "0,1" line.long 0x4 "ETH_DMADSR,Debug status register" hexmask.long.byte 0x4 20.--23. 1. "TPS1,DMA Channel 1 Transmit Process State" newline hexmask.long.byte 0x4 16.--19. 1. "RPS1,DMA Channel 1 Receive Process State" newline hexmask.long.byte 0x4 12.--15. 1. "TPS0,DMA Channel 0 Transmit Process State" newline hexmask.long.byte 0x4 8.--11. 1. "RPS0,DMA Channel 0 Receive Process State" newline bitfld.long 0x4 1. "AXRHSTS,AXI Master Read Channel Status" "0,1" newline bitfld.long 0x4 0. "AXWHSTS,AXI Master Write Channel" "0,1" group.long 0x1020++0xB line.long 0x0 "ETH_DMAA4TXACR,AXI4 transmit channel ACE control register" hexmask.long.byte 0x0 16.--19. 1. "THC,Transmit DMA First Packet Buffer or TSO Header Cache Control" newline hexmask.long.byte 0x0 8.--11. 1. "TEC,Transmit DMA Extended Packet Buffer or TSO Payload Cache Control" newline hexmask.long.byte 0x0 0.--3. 1. "TDRC,Transmit DMA Read Descriptor Cache Control" line.long 0x4 "ETH_DMAA4RXACR,AXI4 receive channel ACE control register" hexmask.long.byte 0x4 24.--27. 1. "RDC,Receive DMA Buffer Cache Control" newline hexmask.long.byte 0x4 16.--19. 1. "RHC,Receive DMA Header Cache Control" newline hexmask.long.byte 0x4 8.--11. 1. "RPC,Receive DMA Payload Cache Control" newline hexmask.long.byte 0x4 0.--3. 1. "RDWC,Receive DMA Write Descriptor Cache Control" line.long 0x8 "ETH_DMAA4DACR,AXI4 descriptor ACE control register" hexmask.long.byte 0x8 8.--11. 1. "RDRC,Receive DMA Read Descriptor Cache control" newline bitfld.long 0x8 4.--5. "TDWD,Transmit DMA Write Descriptor Domain control" "0,1,2,3" newline hexmask.long.byte 0x8 0.--3. 1. "TDWC,Transmit DMA Write Descriptor Cache control" group.long 0x1100++0xB line.long 0x0 "ETH_DMAC0CR,Channel 0 control register" bitfld.long 0x0 18.--20. "DSL,Descriptor Skip Length" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 16. "PBLX8,8xPBL mode" "0,1" newline hexmask.long.word 0x0 0.--13. 1. "MSS,Maximum Segment Size" line.long 0x4 "ETH_DMAC0TXCR,Channel 0 transmit control register" hexmask.long.byte 0x4 24.--27. 1. "TQOS,Transmit QOS." newline hexmask.long.byte 0x4 16.--21. 1. "TXPBL,Transmit Programmable Burst Length" newline bitfld.long 0x4 12. "TSE,TCP Segmentation Enabled" "0,1" newline bitfld.long 0x4 4. "OSF,Operate on Second Packet" "0,1" newline rbitfld.long 0x4 1.--3. "TCW,Transmit Channel Weight" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 0. "ST,Start or Stop Transmission Command" "0,1" line.long 0x8 "ETH_DMAC0RXCR,Channel 0 receive control register" bitfld.long 0x8 31. "RPF,DMA Rx Channel0 Packet Flush" "0,1" newline hexmask.long.byte 0x8 24.--27. 1. "RQOS,Rx AXI4 QOS." newline hexmask.long.byte 0x8 16.--21. 1. "RXPBL,Receive Programmable Burst Length" newline hexmask.long.word 0x8 1.--14. 1. "RBSZ,Receive Buffer size" newline bitfld.long 0x8 0. "SR,Start or Stop Receive" "0,1" group.long 0x1114++0x3 line.long 0x0 "ETH_DMAC0TXDLAR,Channel 0 Tx descriptor list address register" hexmask.long 0x0 2.--31. 1. "TDESLA,Start of Transmit List" group.long 0x111C++0x7 line.long 0x0 "ETH_DMAC0RXDLAR,Channel 0 Rx descriptor list address register" hexmask.long 0x0 2.--31. 1. "RDESLA,Start of Receive List" line.long 0x4 "ETH_DMAC0TXDTPR,Channel 0 Tx descriptor tail pointer register" hexmask.long 0x4 2.--31. 1. "TDT,Transmit Descriptor Tail Pointer" group.long 0x1128++0x13 line.long 0x0 "ETH_DMAC0RXDTPR,Channel 0 Rx descriptor tail pointer register" hexmask.long 0x0 2.--31. 1. "RDT,Receive Descriptor Tail Pointer" line.long 0x4 "ETH_DMAC0TXRLR,Channel 0 Tx descriptor ring length register" hexmask.long.word 0x4 0.--9. 1. "TDRL,Transmit Descriptor Ring Length" line.long 0x8 "ETH_DMAC0RXRLR,Channel 0 Rx descriptor ring length register" hexmask.long.word 0x8 0.--9. 1. "RDRL,Receive Descriptor Ring Length" line.long 0xC "ETH_DMAC0IER,Channel 0 interrupt enable register" bitfld.long 0xC 15. "NIE,Normal Interrupt Summary Enable" "0: Transmit Interrupt,?" newline bitfld.long 0xC 14. "AIE,Abnormal Interrupt Summary Enable" "?,1: Transmit Process Stopped" newline bitfld.long 0xC 13. "CDEE,Context Descriptor Error Enable" "0,1" newline bitfld.long 0xC 12. "FBEE,Fatal Bus Error Enable" "0,1" newline bitfld.long 0xC 11. "ERIE,Early Receive Interrupt Enable" "0,1" newline bitfld.long 0xC 10. "ETIE,Early Transmit Interrupt Enable" "0,1" newline bitfld.long 0xC 9. "RWTE,Receive Watchdog Timeout Enable" "0,1" newline bitfld.long 0xC 8. "RSE,Receive Stopped Enable" "0,1" newline bitfld.long 0xC 7. "RBUE,Receive Buffer Unavailable Enable" "0,1" newline bitfld.long 0xC 6. "RIE,Receive Interrupt Enable" "0,1" newline bitfld.long 0xC 2. "TBUE,Transmit Buffer Unavailable Enable" "0,1" newline bitfld.long 0xC 1. "TXSE,Transmit Stopped Enable" "0,1" newline bitfld.long 0xC 0. "TIE,Transmit Interrupt Enable" "0,1" line.long 0x10 "ETH_DMAC0RXIWTR,Channel 0 Rx interrupt watchdog timer register" bitfld.long 0x10 16.--17. "RWTU,Receive Interrupt Watchdog Timer Count Units" "0: 256,1: 512,2: 1024,3: 2048" newline hexmask.long.byte 0x10 0.--7. 1. "RWT,Receive Interrupt Watchdog Timer Count" rgroup.long 0x1144++0x3 line.long 0x0 "ETH_DMAC0CATXDR,Channel 0 current application transmit descriptor register" hexmask.long 0x0 0.--31. 1. "CURTDESAPTR,Application Transmit Descriptor Address Pointer" rgroup.long 0x114C++0x3 line.long 0x0 "ETH_DMAC0CARXDR,Channel 0 current application receive descriptor register" hexmask.long 0x0 0.--31. 1. "CURRDESAPTR,Application Receive Descriptor Address Pointer" rgroup.long 0x1154++0x3 line.long 0x0 "ETH_DMAC0CATXBR,Channel 0 current application transmit buffer register" hexmask.long 0x0 0.--31. 1. "CURTBUFAPTR,Application Transmit Buffer Address Pointer" rgroup.long 0x115C++0x3 line.long 0x0 "ETH_DMAC0CARXBR,Channel 0 current application receive buffer register" hexmask.long 0x0 0.--31. 1. "CURRBUFAPTR,Application Receive Buffer Address Pointer" group.long 0x1160++0x3 line.long 0x0 "ETH_DMAC0SR,Channel 0 status register" rbitfld.long 0x0 19.--21. "REB,Rx DMA Error Bits" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 16.--18. "TEB,Tx DMA Error Bits" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 15. "NIS,Normal Interrupt Summary" "0: Transmit Interrupt,?" newline bitfld.long 0x0 14. "AIS,Abnormal Interrupt Summary" "?,1: Transmit Process Stopped" newline bitfld.long 0x0 13. "CDE,Context Descriptor Error" "0,1" newline bitfld.long 0x0 12. "FBE,Fatal Bus Error" "0,1" newline bitfld.long 0x0 11. "ERI,Early Receive Interrupt" "0,1" newline bitfld.long 0x0 10. "ETI,Early Transmit Interrupt" "0,1" newline bitfld.long 0x0 9. "RWT,Receive Watchdog Timeout" "0,1" newline bitfld.long 0x0 8. "RPS,Receive Process Stopped" "0,1" newline bitfld.long 0x0 7. "RBU,Receive Buffer Unavailable" "0,1" newline bitfld.long 0x0 6. "RI,Receive Interrupt" "0,1" newline bitfld.long 0x0 2. "TBU,Transmit Buffer Unavailable" "0,1" newline bitfld.long 0x0 1. "TPS,Transmit Process Stopped" "0,1" newline bitfld.long 0x0 0. "TI,Transmit Interrupt" "0,1" rgroup.long 0x116C++0x3 line.long 0x0 "ETH_DMAC0MFCR,Channel 0 missed frame count register" bitfld.long 0x0 15. "MFCO,Overflow status of the MFC Counter" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "MFC,Dropped Packet Counters" group.long 0x1180++0x7 line.long 0x0 "ETH_DMAC1CR,Channel 1 control register" bitfld.long 0x0 18.--20. "DSL,Descriptor Skip Length" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 16. "PBLX8,8xPBL mode" "0,1" newline hexmask.long.word 0x0 0.--13. 1. "MSS,Maximum Segment Size" line.long 0x4 "ETH_DMAC1TXCR,Channel 1 transmit control register" hexmask.long.byte 0x4 24.--27. 1. "TQOS,Transmit QOS." newline hexmask.long.byte 0x4 16.--21. 1. "TXPBL,Transmit Programmable Burst Length" newline bitfld.long 0x4 12. "TSE,TCP Segmentation Enabled" "0,1" newline bitfld.long 0x4 4. "OSF,Operate on Second Packet" "0,1" newline rbitfld.long 0x4 1.--3. "TCW,Transmit Channel Weight" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 0. "ST,Start or Stop Transmission Command" "0,1" group.long 0x1194++0x3 line.long 0x0 "ETH_DMAC1TXDLAR,Channel 1 Tx descriptor list address register" hexmask.long 0x0 2.--31. 1. "TDESLA,Start of Transmit List" group.long 0x11A0++0x3 line.long 0x0 "ETH_DMAC1TXDTPR,Channel 1 Tx descriptor tail pointer register" hexmask.long 0x0 2.--31. 1. "TDT,Transmit Descriptor Tail Pointer" group.long 0x11AC++0x3 line.long 0x0 "ETH_DMAC1TXRLR,Channel 1 Tx descriptor ring length register" hexmask.long.word 0x0 0.--9. 1. "TDRL,Transmit Descriptor Ring Length" group.long 0x11B4++0x3 line.long 0x0 "ETH_DMAC1IER,Channel 1 interrupt enable register" bitfld.long 0x0 15. "NIE,Normal Interrupt Summary Enable" "0: Transmit Interrupt,?" newline bitfld.long 0x0 14. "AIE,Abnormal Interrupt Summary Enable" "?,1: Transmit Process Stopped" newline bitfld.long 0x0 13. "CDEE,Context Descriptor Error Enable" "0,1" newline bitfld.long 0x0 12. "FBEE,Fatal Bus Error Enable" "0,1" newline bitfld.long 0x0 11. "ERIE,Early Receive Interrupt Enable" "0,1" newline bitfld.long 0x0 10. "ETIE,Early Transmit Interrupt Enable" "0,1" newline bitfld.long 0x0 9. "RWTE,Receive Watchdog Timeout Enable" "0,1" newline bitfld.long 0x0 8. "RSE,Receive Stopped Enable" "0,1" newline bitfld.long 0x0 7. "RBUE,Receive Buffer Unavailable Enable" "0,1" newline bitfld.long 0x0 6. "RIE,Receive Interrupt Enable" "0,1" newline bitfld.long 0x0 2. "TBUE,Transmit Buffer Unavailable Enable" "0,1" newline bitfld.long 0x0 1. "TXSE,Transmit Stopped Enable" "0,1" newline bitfld.long 0x0 0. "TIE,Transmit Interrupt Enable" "0,1" rgroup.long 0x11C4++0x3 line.long 0x0 "ETH_DMAC1CATXDR,Channel 1 current application transmit descriptor register" hexmask.long 0x0 0.--31. 1. "CURTDESAPTR,Application Transmit Descriptor Address Pointer" rgroup.long 0x11D4++0x3 line.long 0x0 "ETH_DMAC1CATXBR,Channel 1 current application transmit buffer register" hexmask.long 0x0 0.--31. 1. "CURTBUFAPTR,Application Transmit Buffer Address Pointer" group.long 0x11E0++0x3 line.long 0x0 "ETH_DMAC1SR,Channel 1 status register" rbitfld.long 0x0 19.--21. "REB,Rx DMA Error Bits" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 16.--18. "TEB,Tx DMA Error Bits" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 15. "NIS,Normal Interrupt Summary" "0: Transmit Interrupt,?" newline bitfld.long 0x0 14. "AIS,Abnormal Interrupt Summary" "?,1: Transmit Process Stopped" newline bitfld.long 0x0 13. "CDE,Context Descriptor Error" "0,1" newline bitfld.long 0x0 12. "FBE,Fatal Bus Error" "0,1" newline bitfld.long 0x0 11. "ERI,Early Receive Interrupt" "0,1" newline bitfld.long 0x0 10. "ETI,Early Transmit Interrupt" "0,1" newline bitfld.long 0x0 9. "RWT,Receive Watchdog Timeout" "0,1" newline bitfld.long 0x0 8. "RPS,Receive Process Stopped" "0,1" newline bitfld.long 0x0 7. "RBU,Receive Buffer Unavailable" "0,1" newline bitfld.long 0x0 6. "RI,Receive Interrupt" "0,1" newline bitfld.long 0x0 2. "TBU,Transmit Buffer Unavailable" "0,1" newline bitfld.long 0x0 1. "TPS,Transmit Process Stopped" "0,1" newline bitfld.long 0x0 0. "TI,Transmit Interrupt" "0,1" rgroup.long 0x11EC++0x3 line.long 0x0 "ETH_DMAC1MFCR,Channel 1 missed frame count register" bitfld.long 0x0 15. "MFCO,Overflow status of the MFC Counter" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "MFC,Dropped Packet Counters" tree.end endif sif (cpuis("STM32MP151*")||cpuis("STM32MP153*")||cpuis("STM32MP157*")) tree "ETH_MAC_MMC" base ad:0x5800A000 group.long 0x0++0x17 line.long 0x0 "ETH_MACCR,The MAC Configuration Register establishes" bitfld.long 0x0 31. "ARPEN,ARPEN" "0,1" bitfld.long 0x0 28.--30. "SARC,SARC" "0,1,2,3,4,5,6,7" bitfld.long 0x0 27. "IPC,IPC" "0,1" bitfld.long 0x0 24.--26. "IPG,IPG" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 23. "GPSLCE,GPSLCE" "0,1" bitfld.long 0x0 22. "S2KP,S2KP" "0,1" bitfld.long 0x0 21. "CST,CST" "0,1" bitfld.long 0x0 20. "ACS,ACS" "0,1" newline bitfld.long 0x0 19. "WD,WD" "0,1" bitfld.long 0x0 18. "BE,BE" "0,1" bitfld.long 0x0 17. "JD,JD" "0,1" bitfld.long 0x0 16. "JE,JE" "0,1" newline bitfld.long 0x0 15. "PS,PS" "0,1" bitfld.long 0x0 14. "FES,FES" "0,1" bitfld.long 0x0 13. "DM,DM" "0,1" bitfld.long 0x0 12. "LM,LM" "0,1" newline bitfld.long 0x0 11. "ECRSFD,ECRSFD" "0,1" bitfld.long 0x0 10. "DO,DO" "0,1" bitfld.long 0x0 9. "DCRS,DCRS" "0,1" bitfld.long 0x0 8. "DR,DR" "0,1" newline bitfld.long 0x0 5.--6. "BL,BL" "0,1,2,3" bitfld.long 0x0 4. "DC,DC" "0,1" bitfld.long 0x0 2.--3. "PRELEN,PRELEN" "0,1,2,3" bitfld.long 0x0 1. "TE,TE" "0,1" newline bitfld.long 0x0 0. "RE,RE" "0,1" line.long 0x4 "ETH_MACECR,The MAC Extended Configuration Register" hexmask.long.byte 0x4 25.--29. 1. "EIPG,EIPG" bitfld.long 0x4 24. "EIPGEN,EIPGEN" "0,1" bitfld.long 0x4 18. "USP,USP" "0,1" bitfld.long 0x4 17. "SPEN,SPEN" "0,1" newline bitfld.long 0x4 16. "DCRCC,DCRCC" "0,1" hexmask.long.word 0x4 0.--13. 1. "GPSL,GPSL" line.long 0x8 "ETH_MACPFR,The MAC Packet Filter register contains the" bitfld.long 0x8 31. "RA,RA" "0,1" bitfld.long 0x8 21. "DNTU,DNTU" "0,1" bitfld.long 0x8 20. "IPFE,IPFE" "0,1" bitfld.long 0x8 16. "VTFE,VTFE" "0,1" newline bitfld.long 0x8 10. "HPF,HPF" "0,1" bitfld.long 0x8 9. "SAF,SAF" "0,1" bitfld.long 0x8 8. "SAIF,SAIF" "0,1" bitfld.long 0x8 6.--7. "PCF,PCF" "0,1,2,3" newline bitfld.long 0x8 5. "DBF,DBF" "0,1" bitfld.long 0x8 4. "PM,PM" "0,1" bitfld.long 0x8 3. "DAIF,DAIF" "0,1" bitfld.long 0x8 2. "HMC,HMC" "0,1" newline bitfld.long 0x8 1. "HUC,HUC" "0,1" bitfld.long 0x8 0. "PR,PR" "0,1" line.long 0xC "ETH_MACWTR,The Watchdog Timeout register controls the" bitfld.long 0xC 8. "PWE,PWE" "0,1" hexmask.long.byte 0xC 0.--3. 1. "WTO,WTO" line.long 0x10 "ETH_MACHT0R,The Hash Table Register 0 contains the first" hexmask.long 0x10 0.--31. 1. "HT31T0,HT31T0" line.long 0x14 "ETH_MACHT1R,The Hash Table Register 1contains the last" hexmask.long 0x14 0.--31. 1. "HT63T32,HT63T32" group.long 0x50++0x3 line.long 0x0 "ETH_MACVTR,The VLAN Tag register identifies the IEEE" bitfld.long 0x0 31. "EIVLRXS,EIVLRXS" "0,1" bitfld.long 0x0 28.--29. "EIVLS,EIVLS" "0,1,2,3" bitfld.long 0x0 27. "ERIVLT,ERIVLT" "0,1" bitfld.long 0x0 26. "EDVLP,EDVLP" "0,1" newline bitfld.long 0x0 25. "VTHM,VTHM" "0,1" bitfld.long 0x0 24. "EVLRXS,EVLRXS" "0,1" bitfld.long 0x0 21.--22. "EVLS,EVLS" "0,1,2,3" bitfld.long 0x0 20. "DOVLTC,DOVLTC" "0,1" newline bitfld.long 0x0 19. "ERSVLM,ERSVLM" "0,1" bitfld.long 0x0 18. "ESVL,ESVL" "0,1" bitfld.long 0x0 17. "VTIM,VTIM" "0,1" bitfld.long 0x0 16. "ETV,ETV" "0,1" newline hexmask.long.word 0x0 0.--15. 1. "VL,VL" group.long 0x58++0x3 line.long 0x0 "ETH_MACVHTR,When the ERSVLM bit of ETH_MACHT1R register" hexmask.long.word 0x0 0.--15. 1. "VLHT,VLHT" group.long 0x60++0x7 line.long 0x0 "ETH_MACVIR,The VLAN Tag Inclusion or Replacement" bitfld.long 0x0 20. "VLTI,VLTI" "0,1" bitfld.long 0x0 19. "CSVL,CSVL" "0,1" bitfld.long 0x0 18. "VLP,VLP" "0,1" bitfld.long 0x0 16.--17. "VLC,VLC" "0,1,2,3" newline hexmask.long.word 0x0 0.--15. 1. "VLT,VLT" line.long 0x4 "ETH_MACIVIR,The Inner VLAN Tag Inclusion or Replacement" bitfld.long 0x4 20. "VLTI,VLTI" "0,1" bitfld.long 0x4 19. "CSVL,CSVL" "0,1" bitfld.long 0x4 18. "VLP,VLP" "0,1" bitfld.long 0x4 16.--17. "VLC,VLC" "0,1,2,3" newline hexmask.long.word 0x4 0.--15. 1. "VLT,VLT" group.long 0x70++0x3 line.long 0x0 "ETH_MACQ0TxFCR,The Flow Control register controls the" hexmask.long.word 0x0 16.--31. 1. "PT,PT" bitfld.long 0x0 7. "DZPQ,DZPQ" "0,1" bitfld.long 0x0 4.--6. "PLT,PLT" "0,1,2,3,4,5,6,7" bitfld.long 0x0 1. "TFE,TFE" "0,1" newline bitfld.long 0x0 0. "FCB_BPA,FCB_BPA" "0,1" group.long 0x90++0x3 line.long 0x0 "ETH_MACRxFCR,The Receive Flow Control register controls" bitfld.long 0x0 1. "UP,UP" "0,1" bitfld.long 0x0 0. "RFE,RFE" "0,1" rgroup.long 0x98++0x3 line.long 0x0 "ETH_MACTxQPMR,The transmit queue priority mapping 0" hexmask.long.byte 0x0 8.--15. 1. "PSTQ1,PSTQ1" hexmask.long.byte 0x0 0.--7. 1. "PSTQ0,PSTQ0" group.long 0xA0++0xB line.long 0x0 "ETH_MACRxQC0R,The Receive Queue Control 0 register" bitfld.long 0x0 2.--3. "RXQ1EN,RXQ1EN" "0,1,2,3" bitfld.long 0x0 0.--1. "RXQ0EN,RXQ0EN" "0,1,2,3" line.long 0x4 "ETH_MACRxQC1R,The Receive Queue Control 1 register" bitfld.long 0x4 21. "TACPQE,TACPQE" "0,1" bitfld.long 0x4 20. "MCBCQEN,MCBCQEN" "0,1" bitfld.long 0x4 16.--18. "MCBCQ,MCBCQ" "0,1,2,3,4,5,6,7" bitfld.long 0x4 12.--14. "UPQ,UPQ" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 4.--6. "AVPTPQ,AVPTPQ" "0,1,2,3,4,5,6,7" bitfld.long 0x4 0.--2. "AVCPQ,AVCPQ" "0,1,2,3,4,5,6,7" line.long 0x8 "ETH_MACRxQC2R,This register controls the routing of tagged" hexmask.long.byte 0x8 8.--15. 1. "PSRQ1,PSRQ1" hexmask.long.byte 0x8 0.--7. 1. "PSRQ0,PSRQ0" rgroup.long 0xB0++0x3 line.long 0x0 "ETH_MACISR,The Interrupt Status register contains the" bitfld.long 0x0 14. "RXSTSIS,RXSTSIS" "0,1" bitfld.long 0x0 13. "TXSTSIS,TXSTSIS" "0,1" bitfld.long 0x0 12. "TSIS,TSIS" "0,1" bitfld.long 0x0 10. "MMCTXIS,MMCTXIS" "0,1" newline bitfld.long 0x0 9. "MMCRXIS,MMCRXIS" "0,1" bitfld.long 0x0 8. "MMCIS,MMCIS" "0,1" bitfld.long 0x0 5. "LPIIS,LPIIS" "0,1" bitfld.long 0x0 4. "PMTIS,PMTIS" "0,1" newline bitfld.long 0x0 3. "PHYIS,PHYIS" "0,1" bitfld.long 0x0 0. "RGSMIIIS,RGSMIIIS" "0,1" group.long 0xB4++0x3 line.long 0x0 "ETH_MACIER,The Interrupt Enable register contains the" bitfld.long 0x0 14. "RXSTSIE,RXSTSIE" "0,1" bitfld.long 0x0 13. "TXSTSIE,TXSTSIE" "0,1" bitfld.long 0x0 12. "TSIE,TSIE" "0,1" bitfld.long 0x0 5. "LPIIE,LPIIE" "0,1" newline bitfld.long 0x0 4. "PMTIE,PMTIE" "0,1" bitfld.long 0x0 3. "PHYIE,PHYIE" "0,1" bitfld.long 0x0 0. "RGSMIIIE,RGSMIIIE" "0,1" rgroup.long 0xB8++0x3 line.long 0x0 "ETH_MACRxTxSR,The Receive Transmit Status register" bitfld.long 0x0 8. "RWT,RWT" "0,1" bitfld.long 0x0 5. "EXCOL,EXCOL" "0,1" bitfld.long 0x0 4. "LCOL,LCOL" "0,1" bitfld.long 0x0 3. "EXDEF,EXDEF" "0,1" newline bitfld.long 0x0 2. "LCARR,LCARR" "0,1" bitfld.long 0x0 1. "NCARR,NCARR" "0,1" bitfld.long 0x0 0. "TJT,TJT" "0,1" group.long 0xC0++0x7 line.long 0x0 "ETH_MACPCSR,The PMT Control and Status Register is" bitfld.long 0x0 31. "RWKFILTRST,RWKFILTRST" "0,1" hexmask.long.byte 0x0 24.--28. 1. "RWKPTR,RWKPTR" bitfld.long 0x0 10. "RWKPFE,RWKPFE" "0,1" bitfld.long 0x0 9. "GLBLUCAST,GLBLUCAST" "0,1" newline rbitfld.long 0x0 6. "RWKPRCVD,RWKPRCVD" "0,1" rbitfld.long 0x0 5. "MGKPRCVD,MGKPRCVD" "0,1" bitfld.long 0x0 2. "RWKPKTEN,RWKPKTEN" "0,1" bitfld.long 0x0 1. "MGKPKTEN,MGKPKTEN" "0,1" newline bitfld.long 0x0 0. "PWRDWN,PWRDWN" "0,1" line.long 0x4 "ETH_MACRWKPFR,The LPI Control and Status Register controls" bitfld.long 0x4 20. "LPITE,LPITE" "0,1" bitfld.long 0x4 19. "LPITXA,LPITXA" "0,1" bitfld.long 0x4 18. "PLSEN,PLSEN" "0,1" bitfld.long 0x4 17. "PLS,PLS" "0,1" newline bitfld.long 0x4 16. "LPIEN,LPIEN" "0,1" rbitfld.long 0x4 9. "RLPIST,RLPIST" "0,1" rbitfld.long 0x4 8. "TLPIST,TLPIST" "0,1" rbitfld.long 0x4 3. "RLPIEX,RLPIEX" "0,1" newline rbitfld.long 0x4 2. "RLPIEN,RLPIEN" "0,1" rbitfld.long 0x4 1. "TLPIEX,TLPIEX" "0,1" rbitfld.long 0x4 0. "TLPIEN,TLPIEN" "0,1" group.long 0xD0++0xF line.long 0x0 "ETH_MACLCSR,The LPI Control and Status Register controls" bitfld.long 0x0 20. "LPITE,LPITE" "0,1" bitfld.long 0x0 19. "LPITXA,LPITXA" "0,1" bitfld.long 0x0 18. "PLSEN,PLSEN" "0,1" bitfld.long 0x0 17. "PLS,PLS" "0,1" newline bitfld.long 0x0 16. "LPIEN,LPIEN" "0,1" rbitfld.long 0x0 9. "RLPIST,RLPIST" "0,1" rbitfld.long 0x0 8. "TLPIST,TLPIST" "0,1" rbitfld.long 0x0 3. "RLPIEX,RLPIEX" "0,1" newline rbitfld.long 0x0 2. "RLPIEN,RLPIEN" "0,1" rbitfld.long 0x0 1. "TLPIEX,TLPIEX" "0,1" rbitfld.long 0x0 0. "TLPIEN,TLPIEN" "0,1" line.long 0x4 "ETH_MACLTCR,The LPI Timers Control register controls the" hexmask.long.word 0x4 16.--25. 1. "LST,LST" hexmask.long.word 0x4 0.--15. 1. "TWT,TWT" line.long 0x8 "ETH_MACLETR,The LPI Entry Timer Register is used to" hexmask.long.tbyte 0x8 3.--19. 1. "LPIET,LPIET" line.long 0xC "ETH_MAC1USTCR,This register controls the generation of the" hexmask.long.word 0xC 0.--11. 1. "TIC_1US_CNTR,TIC_1US_CNTR" group.long 0xF8++0x3 line.long 0x0 "ETH_MACPHYCSR,The PHY Interface Control and Status" rbitfld.long 0x0 21. "FALSCARDET,FALSCARDET" "0,1" rbitfld.long 0x0 20. "JABTO,JABTO" "0,1" rbitfld.long 0x0 19. "LNKSTS,LNKSTS" "0,1" rbitfld.long 0x0 17.--18. "LNKSPEED,LNKSPEED" "0,1,2,3" newline rbitfld.long 0x0 16. "LNKMOD,LNKMOD" "0,1" bitfld.long 0x0 1. "LUD,LUD" "0,1" bitfld.long 0x0 0. "TC,TC" "0,1" rgroup.long 0x110++0x7 line.long 0x0 "ETH_MACVR,The version register identifies the version" hexmask.long.byte 0x0 8.--15. 1. "USERVER,USERVER" hexmask.long.byte 0x0 0.--7. 1. "SNPSVER,SNPSVER" line.long 0x4 "ETH_MACDR,The Debug register provides the debug status" bitfld.long 0x4 17.--18. "TFCSTS,TFCSTS" "0,1,2,3" bitfld.long 0x4 16. "TPESTS,TPESTS" "0,1" bitfld.long 0x4 1.--2. "RFCFCSTS,RFCFCSTS" "0,1,2,3" bitfld.long 0x4 0. "RPESTS,RPESTS" "0,1" rgroup.long 0x120++0x7 line.long 0x0 "ETH_MACHWF1R,This register indicates the presence of" hexmask.long.byte 0x0 27.--30. 1. "L3L4FNUM,L3L4FNUM" bitfld.long 0x0 24.--25. "HASHTBLSZ,HASHTBLSZ" "0,1,2,3" bitfld.long 0x0 20. "AVSEL,AVSEL" "0,1" bitfld.long 0x0 19. "DBGMEMA,DBGMEMA" "0,1" newline bitfld.long 0x0 18. "TSOEN,TSOEN" "0,1" bitfld.long 0x0 17. "SPHEN,SPHEN" "0,1" bitfld.long 0x0 16. "DCBEN,DCBEN" "0,1" bitfld.long 0x0 14.--15. "ADDR64,ADDR64" "0,1,2,3" newline bitfld.long 0x0 13. "ADVTHWORD,ADVTHWORD" "0,1" bitfld.long 0x0 12. "PTOEN,PTOEN" "0,1" bitfld.long 0x0 11. "OSTEN,OSTEN" "0,1" hexmask.long.byte 0x0 6.--10. 1. "TXFIFOSIZE,TXFIFOSIZE" newline hexmask.long.byte 0x0 0.--4. 1. "RXFIFOSIZE,RXFIFOSIZE" line.long 0x4 "ETH_MACHWF2R,This register indicates the presence of" bitfld.long 0x4 28.--30. "AUXSNAPNUM,AUXSNAPNUM" "0,1,2,3,4,5,6,7" bitfld.long 0x4 24.--26. "PPSOUTNUM,PPSOUTNUM" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 18.--21. 1. "TXCHCNT,TXCHCNT" hexmask.long.byte 0x4 12.--15. 1. "RXCHCNT,RXCHCNT" newline hexmask.long.byte 0x4 6.--9. 1. "TXQCNT,TXQCNT" hexmask.long.byte 0x4 0.--3. 1. "RXQCNT,RXQCNT" group.long 0x200++0x7 line.long 0x0 "ETH_MACMDIOAR,The MDIO Address register controls the" bitfld.long 0x0 27. "PSE,PSE" "0,1" bitfld.long 0x0 26. "BTB,BTB" "0,1" hexmask.long.byte 0x0 21.--25. 1. "PA,PA" hexmask.long.byte 0x0 16.--20. 1. "RDA,RDA" newline bitfld.long 0x0 12.--14. "NTC,NTC" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 8.--11. 1. "CR,CR" bitfld.long 0x0 4. "SKAP,SKAP" "0,1" bitfld.long 0x0 2.--3. "GOC,GOC" "0,1,2,3" newline bitfld.long 0x0 1. "C45E,C45E" "0,1" bitfld.long 0x0 0. "GB,GB" "0,1" line.long 0x4 "ETH_MACMDIODR,The MDIO Data register stores the Write data" hexmask.long.word 0x4 16.--31. 1. "RA,RA" hexmask.long.word 0x4 0.--15. 1. "GD,GD" group.long 0x300++0x1F line.long 0x0 "ETH_MACA0HR,The MAC Address0 High register holds the" rbitfld.long 0x0 31. "AE,AE" "0,1" hexmask.long.word 0x0 0.--15. 1. "ADDRHI,ADDRHI" line.long 0x4 "ETH_MACA0LR,The MAC Address x Low register holds the" hexmask.long 0x4 0.--31. 1. "ADDRLO,ADDRLO" line.long 0x8 "ETH_MACA1HR,The MAC Address x High register holds the" bitfld.long 0x8 31. "AE,AE" "0,1" bitfld.long 0x8 30. "SA,SA" "0,1" hexmask.long.byte 0x8 24.--29. 1. "MBC,MBC" hexmask.long.word 0x8 0.--15. 1. "ADDRHI,ADDRHI" line.long 0xC "ETH_MACA1LR,The MAC Address x Low register holds the" hexmask.long 0xC 0.--31. 1. "ADDRLO,ADDRLO" line.long 0x10 "ETH_MACA2HR,The MAC Address x High register holds the" bitfld.long 0x10 31. "AE,AE" "0,1" bitfld.long 0x10 30. "SA,SA" "0,1" hexmask.long.byte 0x10 24.--29. 1. "MBC,MBC" hexmask.long.word 0x10 0.--15. 1. "ADDRHI,ADDRHI" line.long 0x14 "ETH_MACA2LR,The MAC Address x Low register holds the" hexmask.long 0x14 0.--31. 1. "ADDRLO,ADDRLO" line.long 0x18 "ETH_MACA3HR,The MAC Address x High register holds the" bitfld.long 0x18 31. "AE,AE" "0,1" bitfld.long 0x18 30. "SA,SA" "0,1" hexmask.long.byte 0x18 24.--29. 1. "MBC,MBC" hexmask.long.word 0x18 0.--15. 1. "ADDRHI,ADDRHI" line.long 0x1C "ETH_MACA3LR,The MAC Address x Low register holds the" hexmask.long 0x1C 0.--31. 1. "ADDRLO,ADDRLO" group.long 0x700++0x3 line.long 0x0 "MMC_CONTROL,This register configures the MMC operating" bitfld.long 0x0 8. "UCDBC,UCDBC" "0,1" bitfld.long 0x0 5. "CNTPRSTLVL,CNTPRSTLVL" "0,1" bitfld.long 0x0 4. "CNTPRST,CNTPRST" "0,1" bitfld.long 0x0 3. "CNTFREEZ,CNTFREEZ" "0,1" newline bitfld.long 0x0 2. "RSTONRD,RSTONRD" "0,1" bitfld.long 0x0 1. "CNTSTOPRO,CNTSTOPRO" "0,1" bitfld.long 0x0 0. "CNTRST,CNTRST" "0,1" rgroup.long 0x704++0x7 line.long 0x0 "MMC_RX_INTERRUPT,This register maintains the interrupts" bitfld.long 0x0 27. "RXLPITRCIS,RXLPITRCIS" "0,1" bitfld.long 0x0 26. "RXLPIUSCIS,RXLPIUSCIS" "0,1" bitfld.long 0x0 17. "RXUCGPIS,RXUCGPIS" "0,1" bitfld.long 0x0 6. "RXALGNERPIS,RXALGNERPIS" "0,1" newline bitfld.long 0x0 5. "RXCRCERPIS,RXCRCERPIS" "0,1" line.long 0x4 "MMC_TX_INTERRUPT,This register maintains the interrupts" bitfld.long 0x4 27. "TXLPITRCIS,TXLPITRCIS" "0,1" bitfld.long 0x4 26. "TXLPIUSCIS,TXLPIUSCIS" "0,1" bitfld.long 0x4 21. "TXGPKTIS,TXGPKTIS" "0,1" bitfld.long 0x4 15. "TXMCOLGPIS,TXMCOLGPIS" "0,1" newline bitfld.long 0x4 14. "TXSCOLGPIS,TXSCOLGPIS" "0,1" group.long 0x70C++0x7 line.long 0x0 "MMC_RX_INTERRUPT_MASK,The MMC Receive Interrupt Mask register" rbitfld.long 0x0 27. "RXLPITRCIM,RXLPITRCIM" "0,1" bitfld.long 0x0 26. "RXLPIUSCIM,RXLPIUSCIM" "0,1" bitfld.long 0x0 17. "RXUCGPIM,RXUCGPIM" "0,1" bitfld.long 0x0 6. "RXALGNERPIM,RXALGNERPIM" "0,1" newline bitfld.long 0x0 5. "RXCRCERPIM,RXCRCERPIM" "0,1" line.long 0x4 "MMC_TX_INTERRUPT_MASK,This register maintains the masks for" rbitfld.long 0x4 27. "TXLPITRCIM,TXLPITRCIM" "0,1" bitfld.long 0x4 26. "TXLPIUSCIM,TXLPIUSCIM" "0,1" bitfld.long 0x4 21. "TXGPKTIM,TXGPKTIM" "0,1" bitfld.long 0x4 15. "TXMCOLGPIM,TXMCOLGPIM" "0,1" newline bitfld.long 0x4 14. "TXSCOLGPIM,TXSCOLGPIM" "0,1" rgroup.long 0x74C++0x7 line.long 0x0 "TX_SINGLE_COLLISION_GOOD_PACKETS,This register provides the number of" hexmask.long 0x0 0.--31. 1. "TXSNGLCOLG,TXSNGLCOLG" line.long 0x4 "TX_MULTIPLE_COLLISION_GOOD_PACKETS,This register provides the number of" hexmask.long 0x4 0.--31. 1. "TXMULTCOLG,TXMULTCOLG" rgroup.long 0x768++0x3 line.long 0x0 "TX_PACKET_COUNT_GOOD,This register provides the number of good" hexmask.long 0x0 0.--31. 1. "TXPKTG,TXPKTG" rgroup.long 0x794++0x7 line.long 0x0 "RX_CRC_ERROR_PACKETS,This register provides the number of packets" hexmask.long 0x0 0.--31. 1. "RXCRCERR,RXCRCERR" line.long 0x4 "RX_ALIGNMENT_ERROR_PACKETS,This register provides the number of packets" hexmask.long 0x4 0.--31. 1. "RXALGNERR,RXALGNERR" rgroup.long 0x7C4++0x3 line.long 0x0 "RX_UNICAST_PACKETS_GOOD,This register provides the number of good" hexmask.long 0x0 0.--31. 1. "RXUCASTG,RXUCASTG" rgroup.long 0x7EC++0xF line.long 0x0 "TX_LPI_USEC_CNTR,This register provides the number of" hexmask.long 0x0 0.--31. 1. "TXLPIUSC,TXLPIUSC" line.long 0x4 "TX_LPI_TRAN_CNTR,This register provides the number of times" hexmask.long 0x4 0.--31. 1. "TXLPITRC,TXLPITRC" line.long 0x8 "RX_LPI_USEC_CNTR,This register provides the number of" hexmask.long 0x8 0.--31. 1. "RXLPIUSC,RXLPIUSC" line.long 0xC "RX_LPI_TRAN_CNTR,This register provides the number of times" hexmask.long 0xC 0.--31. 1. "RXLPITRC,RXLPITRC" group.long 0x900++0x7 line.long 0x0 "ETH_MACL3L4C0R,The Layer 3 and Layer 4 Control register" bitfld.long 0x0 21. "L4DPIM0,L4DPIM0" "0,1" bitfld.long 0x0 20. "L4DPM0,L4DPM0" "0,1" bitfld.long 0x0 19. "L4SPIM0,L4SPIM0" "0,1" bitfld.long 0x0 18. "L4SPM0,L4SPM0" "0,1" newline bitfld.long 0x0 16. "L4PEN0,L4PEN0" "0,1" hexmask.long.byte 0x0 11.--15. 1. "L3HDBM0,L3HDBM0" hexmask.long.byte 0x0 6.--10. 1. "L3HSBM0,L3HSBM0" bitfld.long 0x0 5. "L3DAIM0,L3DAIM0" "0,1" newline bitfld.long 0x0 4. "L3DAM0,L3DAM0" "0,1" bitfld.long 0x0 3. "L3SAIM0,L3SAIM0" "0,1" bitfld.long 0x0 2. "L3SAM0,L3SAM0" "0,1" bitfld.long 0x0 0. "L3PEN0,L3PEN0" "0,1" line.long 0x4 "ETH_MACL4A0R,Layer4 address filter 0" hexmask.long.word 0x4 16.--31. 1. "L4DP0,L4DP0" hexmask.long.word 0x4 0.--15. 1. "L4SP0,L4SP0" group.long 0x910++0xF line.long 0x0 "ETH_MACL3A00R,For IPv4 packets. the Layer 3 Address 0" hexmask.long 0x0 0.--31. 1. "L3A00,L3A00" line.long 0x4 "ETH_MACL3A10R,For IPv4 packets. the Layer 3 Address 1" hexmask.long 0x4 0.--31. 1. "L3A10,L3A10" line.long 0x8 "ETH_MACL3A20,The Layer 3 Address 2 Register 0 register is" hexmask.long 0x8 0.--31. 1. "L3A20,L3A20" line.long 0xC "ETH_MACL3A30,The Layer 3 Address 3 Register 0 register is" hexmask.long 0xC 0.--31. 1. "L3A30,L3A30" group.long 0x930++0x7 line.long 0x0 "ETH_MACL3L4C1R,The Layer 3 and Layer 4 Control register" bitfld.long 0x0 21. "L4DPIM1,L4DPIM1" "0,1" bitfld.long 0x0 20. "L4DPM1,L4DPM1" "0,1" bitfld.long 0x0 19. "L4SPIM1,L4SPIM1" "0,1" bitfld.long 0x0 18. "L4SPM1,L4SPM1" "0,1" newline bitfld.long 0x0 16. "L4PEN1,L4PEN1" "0,1" hexmask.long.byte 0x0 11.--15. 1. "L3HDBM1,L3HDBM1" hexmask.long.byte 0x0 6.--10. 1. "L3HSBM1,L3HSBM1" bitfld.long 0x0 5. "L3DAIM1,L3DAIM1" "0,1" newline bitfld.long 0x0 4. "L3DAM1,L3DAM1" "0,1" bitfld.long 0x0 3. "L3SAIM1,L3SAIM1" "0,1" bitfld.long 0x0 2. "L3SAM1,L3SAM1" "0,1" bitfld.long 0x0 0. "L3PEN1,L3PEN1" "0,1" line.long 0x4 "ETH_MACL4A1R,The Layer 4 Address 0 register and registers" hexmask.long.word 0x4 16.--31. 1. "L4DP1,L4DP1" hexmask.long.word 0x4 0.--15. 1. "L4SP1,L4SP1" group.long 0x940++0xF line.long 0x0 "ETH_MACL3A01R,For IPv4 packets. the Layer 3 Address 0" hexmask.long 0x0 0.--31. 1. "L3A01,L3A01" line.long 0x4 "ETH_MACL3A11R,For IPv4 packets. the Layer 3 Address 1" hexmask.long 0x4 0.--31. 1. "L3A11,L3A11" line.long 0x8 "ETH_MACL3A21R,The Layer 3 Address 2 Register 0 register is" hexmask.long 0x8 0.--31. 1. "L3A21,L3A21" line.long 0xC "ETH_MACL3A31R,The Layer 3 Address 3 Register 0 register is" hexmask.long 0xC 0.--31. 1. "L3A31,L3A31" group.long 0xAE0++0x3 line.long 0x0 "ETH_MACARPAR,The ARP Address register contains the IPv4" hexmask.long 0x0 0.--31. 1. "ARPPA,ARPPA" group.long 0xB00++0x7 line.long 0x0 "ETH_MACTSCR,This register controls the operation of the" bitfld.long 0x0 28. "AV8021ASMEN,AV8021ASMEN" "0,1" bitfld.long 0x0 24. "TXTSSTSM,TXTSSTSM" "0,1" rbitfld.long 0x0 19. "CSC,CSC" "0,1" bitfld.long 0x0 18. "TSENMACADDR,TSENMACADDR" "0,1" newline bitfld.long 0x0 16.--17. "SNAPTYPSEL,SNAPTYPSEL" "0,1,2,3" bitfld.long 0x0 15. "TSMSTRENA,TSMSTRENA" "0,1" bitfld.long 0x0 14. "TSEVNTENA,TSEVNTENA" "0,1" bitfld.long 0x0 13. "TSIPV4ENA,TSIPV4ENA" "0,1" newline bitfld.long 0x0 12. "TSIPV6ENA,TSIPV6ENA" "0,1" bitfld.long 0x0 11. "TSIPENA,TSIPENA" "0,1" bitfld.long 0x0 10. "TSVER2ENA,TSVER2ENA" "0,1" bitfld.long 0x0 9. "TSCTRLSSR,TSCTRLSSR" "0,1" newline bitfld.long 0x0 8. "TSENALL,TSENALL" "0,1" bitfld.long 0x0 5. "TSADDREG,TSADDREG" "0,1" bitfld.long 0x0 3. "TSUPDT,TSUPDT" "0,1" bitfld.long 0x0 2. "TSINIT,TSINIT" "0,1" newline bitfld.long 0x0 1. "TSCFUPDT,TSCFUPDT" "0,1" bitfld.long 0x0 0. "TSENA,TSENA" "0,1" line.long 0x4 "ETH_MACSSIR,The Sub-second Increment register is present" hexmask.long.byte 0x4 16.--23. 1. "SSINC,SSINC" hexmask.long.byte 0x4 8.--15. 1. "SNSINC,SNSINC" rgroup.long 0xB08++0x7 line.long 0x0 "ETH_MACSTSR,The System Time Seconds register. along with" hexmask.long 0x0 0.--31. 1. "TSS,TSS" line.long 0x4 "ETH_MACSTNR,The System Time Nanoseconds register. along" hexmask.long 0x4 0.--30. 1. "TSSS,TSSS" group.long 0xB10++0xB line.long 0x0 "ETH_MACSTSUR,The System Time Seconds Update register." hexmask.long 0x0 0.--31. 1. "TSS,TSS" line.long 0x4 "ETH_MACSTNUR,This register is present only when the IEEE" bitfld.long 0x4 31. "ADDSUB,ADDSUB" "0,1" hexmask.long 0x4 0.--30. 1. "TSSS,TSSS" line.long 0x8 "ETH_MACTSAR,The Timestamp Addend register is present" hexmask.long 0x8 0.--31. 1. "TSAR,TSAR" rgroup.long 0xB20++0x3 line.long 0x0 "ETH_MACTSSR,The Timestamp Status register is present" hexmask.long.byte 0x0 25.--29. 1. "ATSNS,ATSNS" bitfld.long 0x0 24. "ATSSTM,ATSSTM" "0,1" hexmask.long.byte 0x0 16.--19. 1. "ATSSTN,ATSSTN" bitfld.long 0x0 15. "TXTSSIS,TXTSSIS" "0,1" newline bitfld.long 0x0 3. "TSTRGTERR0,TSTRGTERR0" "0,1" bitfld.long 0x0 2. "AUXTSTRIG,AUXTSTRIG" "0,1" bitfld.long 0x0 1. "TSTARGT0,TSTARGT0" "0,1" bitfld.long 0x0 0. "TSSOVF,TSSOVF" "0,1" rgroup.long 0xB30++0x7 line.long 0x0 "ETH_MACTxTSSNR,This register contains the nanosecond part" bitfld.long 0x0 31. "TXTSSMIS,TXTSSMIS" "0,1" hexmask.long 0x0 0.--30. 1. "TXTSSLO,TXTSSLO" line.long 0x4 "ETH_MACTxTSSSR,The register contains the higher 32 bits of" hexmask.long 0x4 0.--31. 1. "TXTSSHI,TXTSSHI" group.long 0xB40++0x3 line.long 0x0 "ETH_MACACR,The Auxiliary Timestamp Control register" bitfld.long 0x0 7. "ATSEN3,ATSEN3" "0,1" bitfld.long 0x0 6. "ATSEN2,ATSEN2" "0,1" bitfld.long 0x0 5. "ATSEN1,ATSEN1" "0,1" bitfld.long 0x0 4. "ATSEN0,ATSEN0" "0,1" newline bitfld.long 0x0 0. "ATSFC,ATSFC" "0,1" rgroup.long 0xB48++0x7 line.long 0x0 "ETH_MACATSNR,The Auxiliary Timestamp Nanoseconds" hexmask.long 0x0 0.--30. 1. "AUXTSLO,AUXTSLO" line.long 0x4 "ETH_MACATSSR,The Auxiliary Timestamp - Seconds register" hexmask.long 0x4 0.--31. 1. "AUXTSHI,AUXTSHI" group.long 0xB50++0xF line.long 0x0 "ETH_MACTSIACR,The MAC Timestamp Ingress Asymmetry" hexmask.long 0x0 0.--31. 1. "OSTIAC,OSTIAC" line.long 0x4 "ETH_MACTSEACR,The MAC Timestamp Egress Asymmetry" hexmask.long 0x4 0.--31. 1. "OSTEAC,OSTEAC" line.long 0x8 "ETH_MACTSICNR,This register contains the correction value" hexmask.long 0x8 0.--31. 1. "TSIC,TSIC" line.long 0xC "ETH_MACTSECNR,This register contains the correction value" hexmask.long 0xC 0.--31. 1. "TSEC,TSEC" group.long 0xB70++0x3 line.long 0x0 "ETH_MACPPSCR,The PPS Control register is present only" bitfld.long 0x0 5.--6. "TRGTMODSEL0,TRGTMODSEL0" "0,1,2,3" bitfld.long 0x0 4. "PPSEN0,PPSEN0" "0,1" hexmask.long.byte 0x0 0.--3. 1. "PPSCTRL,PPSCTRL" group.long 0xB80++0xF line.long 0x0 "ETH_MACPPSTTSR,The PPS Target Time Seconds register. along" hexmask.long 0x0 0.--31. 1. "TSTRH0,TSTRH0" line.long 0x4 "ETH_MACPPSTTNR,The PPS Target Time Nanoseconds register is" bitfld.long 0x4 31. "TRGTBUSY0,TRGTBUSY0" "0,1" hexmask.long 0x4 0.--30. 1. "TTSL0,TTSL0" line.long 0x8 "ETH_MACPPSIR,The PPS Interval register contains the" hexmask.long 0x8 0.--31. 1. "PPSINT0,PPSINT0" line.long 0xC "ETH_MACPPSWR,The PPS Width register contains the number" hexmask.long 0xC 0.--31. 1. "PPSWIDTH0,PPSWIDTH0" group.long 0xBC0++0x13 line.long 0x0 "ETH_MACPOCR,This register controls the PTP Offload" hexmask.long.byte 0x0 8.--15. 1. "DN,DN" bitfld.long 0x0 6. "DRRDIS,DRRDIS" "0,1" bitfld.long 0x0 5. "APDREQTRIG,APDREQTRIG" "0,1" bitfld.long 0x0 4. "ASYNCTRIG,ASYNCTRIG" "0,1" newline bitfld.long 0x0 2. "APDREQEN,APDREQEN" "0,1" bitfld.long 0x0 1. "ASYNCEN,ASYNCEN" "0,1" bitfld.long 0x0 0. "PTOEN,PTOEN" "0,1" line.long 0x4 "ETH_MACSPI0R,This register contains Bits[31:0] of the" hexmask.long 0x4 0.--31. 1. "SPI0,SPI0" line.long 0x8 "ETH_MACSPI1R,This register contains Bits[63:32] of the" hexmask.long 0x8 0.--31. 1. "SPI1,SPI1" line.long 0xC "ETH_MACSPI2R,This register contains Bits[79:64] of the" hexmask.long.word 0xC 0.--15. 1. "SPI2,SPI2" line.long 0x10 "ETH_MACLMIR,This register contains the periodic" hexmask.long.byte 0x10 24.--31. 1. "LMPDRI,LMPDRI" bitfld.long 0x10 8.--10. "DRSYNCR,DRSYNCR" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x10 0.--7. 1. "LSI,LSI" tree.end endif sif (cpuis("STM32MP151*")||cpuis("STM32MP153*")||cpuis("STM32MP157*")) tree "ETH_MTL" base ad:0x5800AC00 group.long 0x0++0x3 line.long 0x0 "ETH_MTLOMR,The Operating Mode register establishes the" bitfld.long 0x0 9. "CNTCLR,CNTCLR" "0,1" bitfld.long 0x0 8. "CNTPRST,CNTPRST" "0,1" bitfld.long 0x0 5.--6. "SCHALG,SCHALG" "0,1,2,3" bitfld.long 0x0 2. "RAA,RAA" "0,1" bitfld.long 0x0 1. "DTXSTS,DTXSTS" "0,1" rgroup.long 0x20++0x3 line.long 0x0 "ETH_MTLISR,The software driver (application) reads this" bitfld.long 0x0 1. "Q1IS,Q1IS" "0,1" bitfld.long 0x0 0. "Q0IS,Q0IS" "0,1" group.long 0x100++0x3 line.long 0x0 "ETH_MTLTxQ0OMR,Tx queue 0 operating mode" hexmask.long.word 0x0 16.--24. 1. "TQS,TQS" bitfld.long 0x0 4.--5. "TTC,TTC" "0,1,2,3" bitfld.long 0x0 2.--3. "TXQEN,TXQEN" "0,1,2,3" bitfld.long 0x0 1. "TSF,TSF" "0,1" bitfld.long 0x0 0. "FTQ,FTQ" "0,1" group.long 0x140++0x3 line.long 0x0 "ETH_MTLTxQ1OMR,Tx queue 1 operating mode" hexmask.long.word 0x0 16.--24. 1. "TQS,TQS" bitfld.long 0x0 4.--5. "TTC,TTC" "0,1,2,3" bitfld.long 0x0 2.--3. "TXQEN,TXQEN" "0,1,2,3" bitfld.long 0x0 1. "TSF,TSF" "0,1" bitfld.long 0x0 0. "FTQ,FTQ" "0,1" rgroup.long 0x104++0x3 line.long 0x0 "ETH_MTLTxQ0UR,Tx queue 0 underflow register" bitfld.long 0x0 11. "UFCNTOVF,UFCNTOVF" "0,1" hexmask.long.word 0x0 0.--10. 1. "UFFRMCNT,UFFRMCNT" rgroup.long 0x144++0x3 line.long 0x0 "ETH_MTLTxQ1UR,Tx queue 1 underflow register" bitfld.long 0x0 11. "UFCNTOVF,UFCNTOVF" "0,1" hexmask.long.word 0x0 0.--10. 1. "UFFRMCNT,UFFRMCNT" rgroup.long 0x108++0x3 line.long 0x0 "ETH_MTLTxQ0DR,Tx queue 0 underflow register" bitfld.long 0x0 20.--22. "STXSTSF,STXSTSF" "0,1,2,3,4,5,6,7" bitfld.long 0x0 16.--18. "PTXQ,PTXQ" "0,1,2,3,4,5,6,7" bitfld.long 0x0 5. "TXSTSFSTS,TXSTSFSTS" "0,1" bitfld.long 0x0 4. "TXQSTS,TXQSTS" "0,1" bitfld.long 0x0 3. "TWCSTS,TWCSTS" "0,1" bitfld.long 0x0 1.--2. "TRCSTS,TRCSTS" "0,1,2,3" newline bitfld.long 0x0 0. "TXQPAUSED,TXQPAUSED" "0,1" rgroup.long 0x148++0x3 line.long 0x0 "ETH_MTLTxQ1DR,Tx queue 1 underflow register" bitfld.long 0x0 20.--22. "STXSTSF,STXSTSF" "0,1,2,3,4,5,6,7" bitfld.long 0x0 16.--18. "PTXQ,PTXQ" "0,1,2,3,4,5,6,7" bitfld.long 0x0 5. "TXSTSFSTS,TXSTSFSTS" "0,1" bitfld.long 0x0 4. "TXQSTS,TXQSTS" "0,1" bitfld.long 0x0 3. "TWCSTS,TWCSTS" "0,1" bitfld.long 0x0 1.--2. "TRCSTS,TRCSTS" "0,1,2,3" newline bitfld.long 0x0 0. "TXQPAUSED,TXQPAUSED" "0,1" rgroup.long 0x114++0x3 line.long 0x0 "ETH_MTLTxQ0ESR,Tx queue x ETS status Register" hexmask.long.tbyte 0x0 0.--23. 1. "ABS,ABS" rgroup.long 0x154++0x3 line.long 0x0 "ETH_MTLTxQ1ESR,Tx queue x ETS status Register" hexmask.long.tbyte 0x0 0.--23. 1. "ABS,ABS" group.long 0x12C++0x3 line.long 0x0 "ETH_MTLQ0ICSR,Queue 0 interrupt control status" bitfld.long 0x0 24. "RXOIE,RXOIE" "0,1" bitfld.long 0x0 16. "RXOVFIS,RXOVFIS" "0,1" bitfld.long 0x0 9. "ABPSIE,ABPSIE" "0,1" bitfld.long 0x0 8. "TXUIE,TXUIE" "0,1" bitfld.long 0x0 1. "ABPSIS,ABPSIS" "0,1" rbitfld.long 0x0 0. "TXUNFIS,TXUNFIS" "0,1" group.long 0x16C++0x3 line.long 0x0 "ETH_MTLQ1ICSR,Queue 1 interrupt control status" bitfld.long 0x0 24. "RXOIE,RXOIE" "0,1" bitfld.long 0x0 16. "RXOVFIS,RXOVFIS" "0,1" bitfld.long 0x0 9. "ABPSIE,ABPSIE" "0,1" bitfld.long 0x0 8. "TXUIE,TXUIE" "0,1" bitfld.long 0x0 1. "ABPSIS,ABPSIS" "0,1" rbitfld.long 0x0 0. "TXUNFIS,TXUNFIS" "0,1" group.long 0x130++0x3 line.long 0x0 "ETH_MTLRxQ0OMR,Rx queue 0 operating mode" hexmask.long.byte 0x0 20.--23. 1. "RQS,RQS" bitfld.long 0x0 14.--16. "RFD,RFD" "0,1,2,3,4,5,6,7" bitfld.long 0x0 8.--10. "RFA,RFA" "0,1,2,3,4,5,6,7" bitfld.long 0x0 7. "EHFC,EHFC" "0,1" bitfld.long 0x0 6. "DIS_TCP_EF,DIS_TCP_EF" "0,1" bitfld.long 0x0 5. "RSF,RSF" "0,1" newline bitfld.long 0x0 4. "FEP,FEP" "0,1" bitfld.long 0x0 3. "FUP,FUP" "0,1" bitfld.long 0x0 0.--1. "RTC,RTC" "0,1,2,3" group.long 0x170++0x3 line.long 0x0 "ETH_MTLRxQ1OMR,Rx queue 1 operating mode" hexmask.long.byte 0x0 20.--23. 1. "RQS,RQS" bitfld.long 0x0 14.--16. "RFD,RFD" "0,1,2,3,4,5,6,7" bitfld.long 0x0 8.--10. "RFA,RFA" "0,1,2,3,4,5,6,7" bitfld.long 0x0 7. "EHFC,EHFC" "0,1" bitfld.long 0x0 6. "DIS_TCP_EF,DIS_TCP_EF" "0,1" bitfld.long 0x0 5. "RSF,RSF" "0,1" newline bitfld.long 0x0 4. "FEP,FEP" "0,1" bitfld.long 0x0 3. "FUP,FUP" "0,1" bitfld.long 0x0 0.--1. "RTC,RTC" "0,1,2,3" rgroup.long 0x134++0x3 line.long 0x0 "ETH_MTLRxQ0MPOCR,Rx queue 0 missed packet and overflow" bitfld.long 0x0 27. "MISCNTOVF,MISCNTOVF" "0,1" hexmask.long.word 0x0 16.--26. 1. "MISPKTCNT,MISPKTCNT" bitfld.long 0x0 11. "OVFCNTOVF,OVFCNTOVF" "0,1" hexmask.long.word 0x0 0.--10. 1. "OVFPKTCNT,OVFPKTCNT" rgroup.long 0x174++0x3 line.long 0x0 "ETH_MTLRxQ1MPOCR,Rx queue 1 missed packet and overflow" bitfld.long 0x0 27. "MISCNTOVF,MISCNTOVF" "0,1" hexmask.long.word 0x0 16.--26. 1. "MISPKTCNT,MISPKTCNT" bitfld.long 0x0 11. "OVFCNTOVF,OVFCNTOVF" "0,1" hexmask.long.word 0x0 0.--10. 1. "OVFPKTCNT,OVFPKTCNT" rgroup.long 0x138++0x3 line.long 0x0 "ETH_MTLRxQ0DR,Rx queue i debug register" hexmask.long.word 0x0 16.--29. 1. "PRXQ,PRXQ" bitfld.long 0x0 4.--5. "RXQSTS,RXQSTS" "0,1,2,3" bitfld.long 0x0 1.--2. "RRCSTS,RRCSTS" "0,1,2,3" bitfld.long 0x0 0. "RWCSTS,RWCSTS" "0,1" rgroup.long 0x178++0x3 line.long 0x0 "ETH_MTLRxQ1DR,Rx queue i debug register" hexmask.long.word 0x0 16.--29. 1. "PRXQ,PRXQ" bitfld.long 0x0 4.--5. "RXQSTS,RXQSTS" "0,1,2,3" bitfld.long 0x0 1.--2. "RRCSTS,RRCSTS" "0,1,2,3" bitfld.long 0x0 0. "RWCSTS,RWCSTS" "0,1" rgroup.long 0x13C++0x3 line.long 0x0 "ETH_MTLRxQ0CR,Rx queue 0 control register" bitfld.long 0x0 3. "RXQ_FRM_ARBIT,RXQ_FRM_ARBIT" "0,1" bitfld.long 0x0 0.--2. "RXQ_WEGT,RXQ_WEGT" "0,1,2,3,4,5,6,7" rgroup.long 0x17C++0x3 line.long 0x0 "ETH_MTLRxQ1CR,Rx queue 1 control register" bitfld.long 0x0 3. "RXQ_FRM_ARBIT,RXQ_FRM_ARBIT" "0,1" bitfld.long 0x0 0.--2. "RXQ_WEGT,RXQ_WEGT" "0,1,2,3,4,5,6,7" group.long 0x150++0x3 line.long 0x0 "ETH_MTLTxQ1ECR,The Queue ETS Control register controls the" bitfld.long 0x0 4.--6. "SLC,SLC" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "CC,CC" "0,1" bitfld.long 0x0 2. "AVALG,AVALG" "0,1" group.long 0x158++0xF line.long 0x0 "ETH_MTLTxQ1QWR,This register provides the average traffic" hexmask.long.tbyte 0x0 0.--20. 1. "ISCQW,ISCQW" line.long 0x4 "ETH_MTLTxQ1SSCR,The sendSlopeCredit register contains the" hexmask.long.word 0x4 0.--13. 1. "SSC,SSC" line.long 0x8 "ETH_MTLTxQ1HCR,The hiCredit register contains the hiCredit" hexmask.long 0x8 0.--28. 1. "HC,HC" line.long 0xC "ETH_MTLTxQ1LCR,The loCredit register contains the loCredit" hexmask.long 0xC 0.--28. 1. "LC,LC" tree.end endif sif (cpuis("STM32MP151*")||cpuis("STM32MP153*")||cpuis("STM32MP157*")) tree "ETH_DMA" base ad:0x5800B000 group.long 0x0++0x7 line.long 0x0 "ETH_DMAMR,DMA mode register" bitfld.long 0x0 16.--17. "INTM,Interrupt Mode" "0,1,2,3" bitfld.long 0x0 12.--14. "PR,Priority ratio" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "TXPR,Transmit priority" "0,1" bitfld.long 0x0 2.--4. "TAA,TAA" "0,1,2,3,4,5,6,7" bitfld.long 0x0 0. "SWR,Software Reset" "0,1" line.long 0x4 "ETH_DMASBMR,System bus mode register" bitfld.long 0x4 31. "EN_LPI,EN_LPI" "0,1" bitfld.long 0x4 30. "LPI_XIT_PKT,LPI_XIT_PKT" "0,1" bitfld.long 0x4 24.--25. "WR_OSR_LMT,WR_OSR_LMT" "0,1,2,3" bitfld.long 0x4 16.--17. "RD_OSR_LMT,RD_OSR_LMT" "0,1,2,3" bitfld.long 0x4 13. "ONEKBBE,ONEKBBE" "0,1" bitfld.long 0x4 12. "AAL,Address-Aligned Beats" "0,1" newline bitfld.long 0x4 7. "BLEN256,BLEN256" "0,1" bitfld.long 0x4 6. "BLEN128,BLEN128" "0,1" bitfld.long 0x4 5. "BLEN64,BLEN64" "0,1" bitfld.long 0x4 4. "BLEN32,BLEN32" "0,1" bitfld.long 0x4 3. "BLEN16,BLEN16" "0,1" bitfld.long 0x4 2. "BLEN8,BLEN8" "0,1" newline bitfld.long 0x4 1. "BLEN4,BLEN4" "0,1" bitfld.long 0x4 0. "FB,Fixed Burst Length" "0,1" rgroup.long 0x8++0x7 line.long 0x0 "ETH_DMAISR,Interrupt status register" bitfld.long 0x0 17. "MACIS,MAC Interrupt Status" "0,1" bitfld.long 0x0 16. "MTLIS,MTL Interrupt Status" "0,1" bitfld.long 0x0 1. "DC1IS,DC1IS" "0,1" bitfld.long 0x0 0. "DC0IS,DMA Channel Interrupt" "0,1" line.long 0x4 "ETH_DMADSR,Debug status register" hexmask.long.byte 0x4 20.--23. 1. "TPS1,TPS1" hexmask.long.byte 0x4 16.--19. 1. "RPS1,RPS1" hexmask.long.byte 0x4 12.--15. 1. "TPS0,TPS0" hexmask.long.byte 0x4 8.--11. 1. "RPS0,RPS0" bitfld.long 0x4 1. "AXRHSTS,AXRHSTS" "0,1" bitfld.long 0x4 0. "AXWHSTS,AHB Master Write Channel" "0,1" group.long 0x20++0xB line.long 0x0 "ETH_DMAA4TxACR,AXI4 transmit channel ACE control" hexmask.long.byte 0x0 16.--19. 1. "THC,THC" hexmask.long.byte 0x0 8.--11. 1. "TEC,TEC" hexmask.long.byte 0x0 0.--3. 1. "TDRC,TDRC" line.long 0x4 "ETH_DMAA4RxACR,AXI4 receive channel ACE control" bitfld.long 0x4 24.--25. "RDC,RDC" "0,1,2,3" hexmask.long.byte 0x4 16.--19. 1. "RHC,RHC" hexmask.long.byte 0x4 8.--11. 1. "RPC,RPC" hexmask.long.byte 0x4 0.--3. 1. "RDWC,RDWC" line.long 0x8 "ETH_DMAA4DACR,AXI4 descriptor ACE control" bitfld.long 0x8 20.--22. "WRP,WRP" "0,1,2,3,4,5,6,7" bitfld.long 0x8 16.--18. "RDP,RDP" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x8 8.--11. 1. "RDRC,RDRC" bitfld.long 0x8 4.--5. "TDWD,TDWD" "0,1,2,3" hexmask.long.byte 0x8 0.--3. 1. "TDWC,TDWC" group.long 0x100++0x3 line.long 0x0 "ETH_DMAC0CR,Channel 0 control register" bitfld.long 0x0 18.--20. "DSL,DSL" "0,1,2,3,4,5,6,7" bitfld.long 0x0 16. "PBLX8,PBLX8" "0,1" hexmask.long.word 0x0 0.--13. 1. "MSS,MSS" group.long 0x180++0x3 line.long 0x0 "ETH_DMAC1CR,Channel 1 control register" bitfld.long 0x0 18.--20. "DSL,DSL" "0,1,2,3,4,5,6,7" bitfld.long 0x0 16. "PBLX8,PBLX8" "0,1" hexmask.long.word 0x0 0.--13. 1. "MSS,MSS" group.long 0x104++0x3 line.long 0x0 "ETH_DMAC0TxCR,Channel 0 transmit control" hexmask.long.byte 0x0 24.--27. 1. "TQOS,TQOS" hexmask.long.byte 0x0 16.--21. 1. "TXPBL,TXPBL" bitfld.long 0x0 12. "TSE,TSE" "0,1" bitfld.long 0x0 4. "OSF,OSF" "0,1" bitfld.long 0x0 1.--3. "TCW,TCW" "0,1,2,3,4,5,6,7" bitfld.long 0x0 0. "ST,ST" "0,1" group.long 0x184++0x3 line.long 0x0 "ETH_DMAC1TxCR,Channel 1 transmit control" hexmask.long.byte 0x0 24.--27. 1. "TQOS,TQOS" hexmask.long.byte 0x0 16.--21. 1. "TXPBL,TXPBL" bitfld.long 0x0 12. "TSE,TSE" "0,1" bitfld.long 0x0 4. "OSF,OSF" "0,1" bitfld.long 0x0 1.--3. "TCW,TCW" "0,1,2,3,4,5,6,7" bitfld.long 0x0 0. "ST,ST" "0,1" group.long 0x108++0x3 line.long 0x0 "ETH_DMAC0RxCR,Channel receive control" bitfld.long 0x0 31. "RPF,DMA Rx Channel Packet" "0,1" hexmask.long.byte 0x0 24.--27. 1. "RQOS,RQOS" hexmask.long.byte 0x0 16.--21. 1. "RXPBL,RXPBL" hexmask.long.word 0x0 1.--14. 1. "RBSZ,Receive Buffer size" bitfld.long 0x0 0. "SR,Start or Stop Receive" "0,1" group.long 0x114++0x3 line.long 0x0 "ETH_DMAC0TxDLAR,Channel i Tx descriptor list address" hexmask.long 0x0 3.--31. 1. "TDESLA,Start of Transmit List" group.long 0x194++0x3 line.long 0x0 "ETH_DMAC1TxDLAR,Channel i Tx descriptor list address" hexmask.long 0x0 3.--31. 1. "TDESLA,Start of Transmit List" group.long 0x11C++0x7 line.long 0x0 "ETH_DMAC0RxDLAR,Channel Rx descriptor list address" hexmask.long 0x0 3.--31. 1. "RDESLA,Start of Receive List" line.long 0x4 "ETH_DMAC0TxDTPR,Channel Tx descriptor tail pointer" hexmask.long 0x4 3.--31. 1. "TDT,Transmit Descriptor Tail" group.long 0x1A0++0x3 line.long 0x0 "ETH_DMAC1TxDTPR,Channel Tx descriptor tail pointer" hexmask.long 0x0 3.--31. 1. "TDT,Transmit Descriptor Tail" group.long 0x128++0x7 line.long 0x0 "ETH_DMAC0RxDTPR,Channel Rx descriptor tail pointer" hexmask.long 0x0 3.--31. 1. "RDT,Receive Descriptor Tail" line.long 0x4 "ETH_DMAC0TxRLR,Channel Tx descriptor ring length" hexmask.long.word 0x4 0.--9. 1. "TDRL,Transmit Descriptor Ring" group.long 0x1AC++0x3 line.long 0x0 "ETH_DMAC1TxRLR,Channel Tx descriptor ring length" hexmask.long.word 0x0 0.--9. 1. "TDRL,Transmit Descriptor Ring" group.long 0x130++0x7 line.long 0x0 "ETH_DMAC0RxRLR,Channel Rx descriptor ring length" hexmask.long.word 0x0 0.--9. 1. "RDRL,Receive Descriptor Ring" line.long 0x4 "ETH_DMAC0IER,Channel interrupt enable" bitfld.long 0x4 15. "NIE,Normal Interrupt Summary" "0,1" bitfld.long 0x4 14. "AIE,Abnormal Interrupt Summary" "0,1" bitfld.long 0x4 13. "CDEE,Context Descriptor Error" "0,1" bitfld.long 0x4 12. "FBEE,Fatal Bus Error Enable" "0,1" bitfld.long 0x4 11. "ERIE,Early Receive Interrupt" "0,1" bitfld.long 0x4 10. "ETIE,Early Transmit Interrupt" "0,1" newline bitfld.long 0x4 9. "RWTE,Receive Watchdog Timeout" "0,1" bitfld.long 0x4 8. "RSE,Receive Stopped Enable" "0,1" bitfld.long 0x4 7. "RBUE,Receive Buffer Unavailable" "0,1" bitfld.long 0x4 6. "RIE,Receive Interrupt Enable" "0,1" bitfld.long 0x4 2. "TBUE,Transmit Buffer Unavailable" "0,1" bitfld.long 0x4 1. "TXSE,Transmit Stopped Enable" "0,1" newline bitfld.long 0x4 0. "TIE,Transmit Interrupt Enable" "0,1" group.long 0x1B4++0x3 line.long 0x0 "ETH_DMAC1IER,Channel interrupt enable" bitfld.long 0x0 15. "NIE,Normal Interrupt Summary" "0,1" bitfld.long 0x0 14. "AIE,Abnormal Interrupt Summary" "0,1" bitfld.long 0x0 13. "CDEE,Context Descriptor Error" "0,1" bitfld.long 0x0 12. "FBEE,Fatal Bus Error Enable" "0,1" bitfld.long 0x0 11. "ERIE,Early Receive Interrupt" "0,1" bitfld.long 0x0 10. "ETIE,Early Transmit Interrupt" "0,1" newline bitfld.long 0x0 9. "RWTE,Receive Watchdog Timeout" "0,1" bitfld.long 0x0 8. "RSE,Receive Stopped Enable" "0,1" bitfld.long 0x0 7. "RBUE,Receive Buffer Unavailable" "0,1" bitfld.long 0x0 6. "RIE,Receive Interrupt Enable" "0,1" bitfld.long 0x0 2. "TBUE,Transmit Buffer Unavailable" "0,1" bitfld.long 0x0 1. "TXSE,Transmit Stopped Enable" "0,1" newline bitfld.long 0x0 0. "TIE,Transmit Interrupt Enable" "0,1" group.long 0x138++0x7 line.long 0x0 "ETH_DMAC0RxIWTR,Channel Rx interrupt watchdog timer" hexmask.long.byte 0x0 0.--7. 1. "RWT,Receive Interrupt Watchdog Timer" line.long 0x4 "ETH_DMAC0SFCSR,Channel i slot function control status" hexmask.long.byte 0x4 16.--19. 1. "RSN,RSN" bitfld.long 0x4 1. "ASC,ASC" "0,1" bitfld.long 0x4 0. "ESC,ESC" "0,1" group.long 0x1BC++0x3 line.long 0x0 "ETH_DMAC1SFCSR,Channel i slot function control status" hexmask.long.byte 0x0 16.--19. 1. "RSN,RSN" bitfld.long 0x0 1. "ASC,ASC" "0,1" bitfld.long 0x0 0. "ESC,ESC" "0,1" rgroup.long 0x144++0x3 line.long 0x0 "ETH_DMAC0CATxDR,Channel current application transmit" hexmask.long 0x0 0.--31. 1. "CURTDESAPTR,Application Transmit Descriptor Address" rgroup.long 0x1C4++0x3 line.long 0x0 "ETH_DMAC1CATxDR,Channel current application transmit" hexmask.long 0x0 0.--31. 1. "CURTDESAPTR,Application Transmit Descriptor Address" rgroup.long 0x14C++0x3 line.long 0x0 "ETH_DMAC0CARxDR,Channel 0 current application receive" hexmask.long 0x0 0.--31. 1. "CURRDESAPTR,Application Transmit Descriptor Address" rgroup.long 0x154++0x3 line.long 0x0 "ETH_DMAC0CATxBR,Channel 0 current application transmit" hexmask.long 0x0 0.--31. 1. "CURTBUFAPTR,Application Transmit Buffer Address" rgroup.long 0x1D4++0x3 line.long 0x0 "ETH_DMAC1CATxBR,Channel 0 current application transmit" hexmask.long 0x0 0.--31. 1. "CURTBUFAPTR,Application Transmit Buffer Address" rgroup.long 0x15C++0x3 line.long 0x0 "ETH_DMAC0CARxBR,Channel current application receive buffer" hexmask.long 0x0 0.--31. 1. "CURRBUFAPTR,Application Receive Buffer Address" group.long 0x160++0x3 line.long 0x0 "ETH_DMAC0SR,Channel status register" bitfld.long 0x0 19.--21. "REB,Rx DMA Error Bits" "0,1,2,3,4,5,6,7" bitfld.long 0x0 16.--18. "TEB,Tx DMA Error Bits" "0,1,2,3,4,5,6,7" bitfld.long 0x0 15. "NIS,Normal Interrupt Summary" "0,1" bitfld.long 0x0 14. "AIS,Abnormal Interrupt Summary" "0,1" bitfld.long 0x0 13. "CDE,Context Descriptor Error" "0,1" bitfld.long 0x0 12. "FBE,Fatal Bus Error" "0,1" newline bitfld.long 0x0 11. "ERI,Early Receive Interrupt" "0,1" bitfld.long 0x0 10. "ETI,Early Transmit Interrupt" "0,1" bitfld.long 0x0 9. "RWT,Receive Watchdog Timeout" "0,1" bitfld.long 0x0 8. "RPS,Receive Process Stopped" "0,1" bitfld.long 0x0 7. "RBU,Receive Buffer Unavailable" "0,1" bitfld.long 0x0 6. "RI,Receive Interrupt" "0,1" newline bitfld.long 0x0 2. "TBU,Transmit Buffer" "0,1" bitfld.long 0x0 1. "TPS,Transmit Process Stopped" "0,1" bitfld.long 0x0 0. "TI,Transmit Interrupt" "0,1" group.long 0x1E0++0x3 line.long 0x0 "ETH_DMAC1SR,Channel status register" bitfld.long 0x0 19.--21. "REB,Rx DMA Error Bits" "0,1,2,3,4,5,6,7" bitfld.long 0x0 16.--18. "TEB,Tx DMA Error Bits" "0,1,2,3,4,5,6,7" bitfld.long 0x0 15. "NIS,Normal Interrupt Summary" "0,1" bitfld.long 0x0 14. "AIS,Abnormal Interrupt Summary" "0,1" bitfld.long 0x0 13. "CDE,Context Descriptor Error" "0,1" bitfld.long 0x0 12. "FBE,Fatal Bus Error" "0,1" newline bitfld.long 0x0 11. "ERI,Early Receive Interrupt" "0,1" bitfld.long 0x0 10. "ETI,Early Transmit Interrupt" "0,1" bitfld.long 0x0 9. "RWT,Receive Watchdog Timeout" "0,1" bitfld.long 0x0 8. "RPS,Receive Process Stopped" "0,1" bitfld.long 0x0 7. "RBU,Receive Buffer Unavailable" "0,1" bitfld.long 0x0 6. "RI,Receive Interrupt" "0,1" newline bitfld.long 0x0 2. "TBU,Transmit Buffer" "0,1" bitfld.long 0x0 1. "TPS,Transmit Process Stopped" "0,1" bitfld.long 0x0 0. "TI,Transmit Interrupt" "0,1" rgroup.long 0x16C++0x3 line.long 0x0 "ETH_DMAC0MFCR,Channel missed frame count" bitfld.long 0x0 15. "MFCO,Overflow status of the MFC" "0,1" hexmask.long.word 0x0 0.--10. 1. "MFC,Dropped Packet Counters" rgroup.long 0x1EC++0x3 line.long 0x0 "ETH_DMAC1MFCR,Channel missed frame count" bitfld.long 0x0 15. "MFCO,Overflow status of the MFC" "0,1" hexmask.long.word 0x0 0.--10. 1. "MFC,Dropped Packet Counters" tree.end endif tree.end tree "ETZPC (Extended TrustZone Protection Controller)" base ad:0x5C007000 group.long 0x0++0x7 line.long 0x0 "ETZPC_TZMA0_SIZE,ETZPC ROM secure size definition" bitfld.long 0x0 31. "LOCK,LOCK" "0,1" hexmask.long.word 0x0 0.--9. 1. "R0SIZE,R0SIZE" line.long 0x4 "ETZPC_TZMA1_SIZE,ETZPC RAM secure size definition" bitfld.long 0x4 31. "LOCK,LOCK" "0,1" hexmask.long.word 0x4 0.--9. 1. "R0SIZE,R0SIZE" group.long 0x10++0x17 line.long 0x0 "ETZPC_DECPROT0,Register reset values" bitfld.long 0x0 30.--31. "DECPROT15,DECPROT15" "0,1,2,3" bitfld.long 0x0 28.--29. "DECPROT14,DECPROT14" "0,1,2,3" bitfld.long 0x0 26.--27. "DECPROT13,DECPROT13" "0,1,2,3" bitfld.long 0x0 24.--25. "DECPROT12,DECPROT12" "0,1,2,3" bitfld.long 0x0 22.--23. "DECPROT11,DECPROT11" "0,1,2,3" bitfld.long 0x0 20.--21. "DECPROT10,DECPROT10" "0,1,2,3" bitfld.long 0x0 18.--19. "DECPROT9,DECPROT9" "0,1,2,3" newline bitfld.long 0x0 16.--17. "DECPROT8,DECPROT8" "0,1,2,3" bitfld.long 0x0 14.--15. "DECPROT7,DECPROT7" "0,1,2,3" bitfld.long 0x0 12.--13. "DECPROT6,DECPROT6" "0,1,2,3" bitfld.long 0x0 10.--11. "DECPROT5,DECPROT5" "0,1,2,3" bitfld.long 0x0 8.--9. "DECPROT4,DECPROT4" "0,1,2,3" bitfld.long 0x0 6.--7. "DECPROT3,DECPROT3" "0,1,2,3" bitfld.long 0x0 4.--5. "DECPROT2,DECPROT2" "0,1,2,3" newline bitfld.long 0x0 2.--3. "DECPROT1,DECPROT1" "0,1,2,3" bitfld.long 0x0 0.--1. "DECPROT0,DECPROT0" "0,1,2,3" line.long 0x4 "ETZPC_DECPROT1,Register reset values" bitfld.long 0x4 30.--31. "DECPROT15,DECPROT15" "0,1,2,3" bitfld.long 0x4 28.--29. "DECPROT14,DECPROT14" "0,1,2,3" bitfld.long 0x4 26.--27. "DECPROT13,DECPROT13" "0,1,2,3" bitfld.long 0x4 24.--25. "DECPROT12,DECPROT12" "0,1,2,3" bitfld.long 0x4 22.--23. "DECPROT11,DECPROT11" "0,1,2,3" bitfld.long 0x4 20.--21. "DECPROT10,DECPROT10" "0,1,2,3" bitfld.long 0x4 18.--19. "DECPROT9,DECPROT9" "0,1,2,3" newline bitfld.long 0x4 16.--17. "DECPROT8,DECPROT8" "0,1,2,3" bitfld.long 0x4 14.--15. "DECPROT7,DECPROT7" "0,1,2,3" bitfld.long 0x4 12.--13. "DECPROT6,DECPROT6" "0,1,2,3" bitfld.long 0x4 10.--11. "DECPROT5,DECPROT5" "0,1,2,3" bitfld.long 0x4 8.--9. "DECPROT4,DECPROT4" "0,1,2,3" bitfld.long 0x4 6.--7. "DECPROT3,DECPROT3" "0,1,2,3" bitfld.long 0x4 4.--5. "DECPROT2,DECPROT2" "0,1,2,3" newline bitfld.long 0x4 2.--3. "DECPROT1,DECPROT1" "0,1,2,3" bitfld.long 0x4 0.--1. "DECPROT0,DECPROT0" "0,1,2,3" line.long 0x8 "ETZPC_DECPROT2,Register reset values" bitfld.long 0x8 30.--31. "DECPROT15,DECPROT15" "0,1,2,3" bitfld.long 0x8 28.--29. "DECPROT14,DECPROT14" "0,1,2,3" bitfld.long 0x8 26.--27. "DECPROT13,DECPROT13" "0,1,2,3" bitfld.long 0x8 24.--25. "DECPROT12,DECPROT12" "0,1,2,3" bitfld.long 0x8 22.--23. "DECPROT11,DECPROT11" "0,1,2,3" bitfld.long 0x8 20.--21. "DECPROT10,DECPROT10" "0,1,2,3" bitfld.long 0x8 18.--19. "DECPROT9,DECPROT9" "0,1,2,3" newline bitfld.long 0x8 16.--17. "DECPROT8,DECPROT8" "0,1,2,3" bitfld.long 0x8 14.--15. "DECPROT7,DECPROT7" "0,1,2,3" bitfld.long 0x8 12.--13. "DECPROT6,DECPROT6" "0,1,2,3" bitfld.long 0x8 10.--11. "DECPROT5,DECPROT5" "0,1,2,3" bitfld.long 0x8 8.--9. "DECPROT4,DECPROT4" "0,1,2,3" bitfld.long 0x8 6.--7. "DECPROT3,DECPROT3" "0,1,2,3" bitfld.long 0x8 4.--5. "DECPROT2,DECPROT2" "0,1,2,3" newline bitfld.long 0x8 2.--3. "DECPROT1,DECPROT1" "0,1,2,3" bitfld.long 0x8 0.--1. "DECPROT0,DECPROT0" "0,1,2,3" line.long 0xC "ETZPC_DECPROT3,Register reset values" bitfld.long 0xC 30.--31. "DECPROT15,DECPROT15" "0,1,2,3" bitfld.long 0xC 28.--29. "DECPROT14,DECPROT14" "0,1,2,3" bitfld.long 0xC 26.--27. "DECPROT13,DECPROT13" "0,1,2,3" bitfld.long 0xC 24.--25. "DECPROT12,DECPROT12" "0,1,2,3" bitfld.long 0xC 22.--23. "DECPROT11,DECPROT11" "0,1,2,3" bitfld.long 0xC 20.--21. "DECPROT10,DECPROT10" "0,1,2,3" bitfld.long 0xC 18.--19. "DECPROT9,DECPROT9" "0,1,2,3" newline bitfld.long 0xC 16.--17. "DECPROT8,DECPROT8" "0,1,2,3" bitfld.long 0xC 14.--15. "DECPROT7,DECPROT7" "0,1,2,3" bitfld.long 0xC 12.--13. "DECPROT6,DECPROT6" "0,1,2,3" bitfld.long 0xC 10.--11. "DECPROT5,DECPROT5" "0,1,2,3" bitfld.long 0xC 8.--9. "DECPROT4,DECPROT4" "0,1,2,3" bitfld.long 0xC 6.--7. "DECPROT3,DECPROT3" "0,1,2,3" bitfld.long 0xC 4.--5. "DECPROT2,DECPROT2" "0,1,2,3" newline bitfld.long 0xC 2.--3. "DECPROT1,DECPROT1" "0,1,2,3" bitfld.long 0xC 0.--1. "DECPROT0,DECPROT0" "0,1,2,3" line.long 0x10 "ETZPC_DECPROT4,Register reset values" bitfld.long 0x10 30.--31. "DECPROT15,DECPROT15" "0,1,2,3" bitfld.long 0x10 28.--29. "DECPROT14,DECPROT14" "0,1,2,3" bitfld.long 0x10 26.--27. "DECPROT13,DECPROT13" "0,1,2,3" bitfld.long 0x10 24.--25. "DECPROT12,DECPROT12" "0,1,2,3" bitfld.long 0x10 22.--23. "DECPROT11,DECPROT11" "0,1,2,3" bitfld.long 0x10 20.--21. "DECPROT10,DECPROT10" "0,1,2,3" bitfld.long 0x10 18.--19. "DECPROT9,DECPROT9" "0,1,2,3" newline bitfld.long 0x10 16.--17. "DECPROT8,DECPROT8" "0,1,2,3" bitfld.long 0x10 14.--15. "DECPROT7,DECPROT7" "0,1,2,3" bitfld.long 0x10 12.--13. "DECPROT6,DECPROT6" "0,1,2,3" bitfld.long 0x10 10.--11. "DECPROT5,DECPROT5" "0,1,2,3" bitfld.long 0x10 8.--9. "DECPROT4,DECPROT4" "0,1,2,3" bitfld.long 0x10 6.--7. "DECPROT3,DECPROT3" "0,1,2,3" bitfld.long 0x10 4.--5. "DECPROT2,DECPROT2" "0,1,2,3" newline bitfld.long 0x10 2.--3. "DECPROT1,DECPROT1" "0,1,2,3" bitfld.long 0x10 0.--1. "DECPROT0,DECPROT0" "0,1,2,3" line.long 0x14 "ETZPC_DECPROT5,Register reset values" bitfld.long 0x14 30.--31. "DECPROT15,DECPROT15" "0,1,2,3" bitfld.long 0x14 28.--29. "DECPROT14,DECPROT14" "0,1,2,3" bitfld.long 0x14 26.--27. "DECPROT13,DECPROT13" "0,1,2,3" bitfld.long 0x14 24.--25. "DECPROT12,DECPROT12" "0,1,2,3" bitfld.long 0x14 22.--23. "DECPROT11,DECPROT11" "0,1,2,3" bitfld.long 0x14 20.--21. "DECPROT10,DECPROT10" "0,1,2,3" bitfld.long 0x14 18.--19. "DECPROT9,DECPROT9" "0,1,2,3" newline bitfld.long 0x14 16.--17. "DECPROT8,DECPROT8" "0,1,2,3" bitfld.long 0x14 14.--15. "DECPROT7,DECPROT7" "0,1,2,3" bitfld.long 0x14 12.--13. "DECPROT6,DECPROT6" "0,1,2,3" bitfld.long 0x14 10.--11. "DECPROT5,DECPROT5" "0,1,2,3" bitfld.long 0x14 8.--9. "DECPROT4,DECPROT4" "0,1,2,3" bitfld.long 0x14 6.--7. "DECPROT3,DECPROT3" "0,1,2,3" bitfld.long 0x14 4.--5. "DECPROT2,DECPROT2" "0,1,2,3" newline bitfld.long 0x14 2.--3. "DECPROT1,DECPROT1" "0,1,2,3" bitfld.long 0x14 0.--1. "DECPROT0,DECPROT0" "0,1,2,3" group.long 0x30++0xB line.long 0x0 "ETZPC_DECPROT_LOCK0,ETZPC decprot lock 0 register" bitfld.long 0x0 31. "LOCK31,LOCK31" "0,1" bitfld.long 0x0 30. "LOCK30,LOCK30" "0,1" bitfld.long 0x0 29. "LOCK29,LOCK29" "0,1" bitfld.long 0x0 28. "LOCK28,LOCK28" "0,1" bitfld.long 0x0 27. "LOCK27,LOCK27" "0,1" bitfld.long 0x0 26. "LOCK26,LOCK26" "0,1" bitfld.long 0x0 25. "LOCK25,LOCK25" "0,1" newline bitfld.long 0x0 24. "LOCK24,LOCK24" "0,1" bitfld.long 0x0 23. "LOCK23,LOCK23" "0,1" bitfld.long 0x0 22. "LOCK22,LOCK22" "0,1" bitfld.long 0x0 21. "LOCK21,LOCK21" "0,1" bitfld.long 0x0 20. "LOCK20,LOCK20" "0,1" bitfld.long 0x0 19. "LOCK19,LOCK19" "0,1" bitfld.long 0x0 18. "LOCK18,LOCK18" "0,1" newline bitfld.long 0x0 17. "LOCK17,LOCK17" "0,1" bitfld.long 0x0 16. "LOCK16,LOCK16" "0,1" bitfld.long 0x0 15. "LOCK15,LOCK15" "0,1" bitfld.long 0x0 14. "LOCK14,LOCK14" "0,1" bitfld.long 0x0 13. "LOCK13,LOCK13" "0,1" bitfld.long 0x0 12. "LOCK12,LOCK12" "0,1" bitfld.long 0x0 11. "LOCK11,LOCK11" "0,1" newline bitfld.long 0x0 10. "LOCK10,LOCK10" "0,1" bitfld.long 0x0 9. "LOCK9,LOCK9" "0,1" bitfld.long 0x0 8. "LOCK8,LOCK8" "0,1" bitfld.long 0x0 7. "LOCK7,LOCK7" "0,1" bitfld.long 0x0 6. "LOCK6,LOCK6" "0,1" bitfld.long 0x0 5. "LOCK5,LOCK5" "0,1" bitfld.long 0x0 4. "LOCK4,LOCK4" "0,1" newline bitfld.long 0x0 3. "LOCK3,LOCK3" "0,1" bitfld.long 0x0 2. "LOCK2,LOCK2" "0,1" bitfld.long 0x0 1. "LOCK1,LOCK1" "0,1" bitfld.long 0x0 0. "LOCK0,LOCK0" "0,1" line.long 0x4 "ETZPC_DECPROT_LOCK1,ETZPC decprot lock 1 register" bitfld.long 0x4 31. "LOCK31,LOCK31" "0,1" bitfld.long 0x4 30. "LOCK30,LOCK30" "0,1" bitfld.long 0x4 29. "LOCK29,LOCK29" "0,1" bitfld.long 0x4 28. "LOCK28,LOCK28" "0,1" bitfld.long 0x4 27. "LOCK27,LOCK27" "0,1" bitfld.long 0x4 26. "LOCK26,LOCK26" "0,1" bitfld.long 0x4 25. "LOCK25,LOCK25" "0,1" newline bitfld.long 0x4 24. "LOCK24,LOCK24" "0,1" bitfld.long 0x4 23. "LOCK23,LOCK23" "0,1" bitfld.long 0x4 22. "LOCK22,LOCK22" "0,1" bitfld.long 0x4 21. "LOCK21,LOCK21" "0,1" bitfld.long 0x4 20. "LOCK20,LOCK20" "0,1" bitfld.long 0x4 19. "LOCK19,LOCK19" "0,1" bitfld.long 0x4 18. "LOCK18,LOCK18" "0,1" newline bitfld.long 0x4 17. "LOCK17,LOCK17" "0,1" bitfld.long 0x4 16. "LOCK16,LOCK16" "0,1" bitfld.long 0x4 15. "LOCK15,LOCK15" "0,1" bitfld.long 0x4 14. "LOCK14,LOCK14" "0,1" bitfld.long 0x4 13. "LOCK13,LOCK13" "0,1" bitfld.long 0x4 12. "LOCK12,LOCK12" "0,1" bitfld.long 0x4 11. "LOCK11,LOCK11" "0,1" newline bitfld.long 0x4 10. "LOCK10,LOCK10" "0,1" bitfld.long 0x4 9. "LOCK9,LOCK9" "0,1" bitfld.long 0x4 8. "LOCK8,LOCK8" "0,1" bitfld.long 0x4 7. "LOCK7,LOCK7" "0,1" bitfld.long 0x4 6. "LOCK6,LOCK6" "0,1" bitfld.long 0x4 5. "LOCK5,LOCK5" "0,1" bitfld.long 0x4 4. "LOCK4,LOCK4" "0,1" newline bitfld.long 0x4 3. "LOCK3,LOCK3" "0,1" bitfld.long 0x4 2. "LOCK2,LOCK2" "0,1" bitfld.long 0x4 1. "LOCK1,LOCK1" "0,1" bitfld.long 0x4 0. "LOCK0,LOCK0" "0,1" line.long 0x8 "ETZPC_DECPROT_LOCK2,ETZPC decprot lock 2 register" bitfld.long 0x8 31. "LOCK31,LOCK31" "0,1" bitfld.long 0x8 30. "LOCK30,LOCK30" "0,1" bitfld.long 0x8 29. "LOCK29,LOCK29" "0,1" bitfld.long 0x8 28. "LOCK28,LOCK28" "0,1" bitfld.long 0x8 27. "LOCK27,LOCK27" "0,1" bitfld.long 0x8 26. "LOCK26,LOCK26" "0,1" bitfld.long 0x8 25. "LOCK25,LOCK25" "0,1" newline bitfld.long 0x8 24. "LOCK24,LOCK24" "0,1" bitfld.long 0x8 23. "LOCK23,LOCK23" "0,1" bitfld.long 0x8 22. "LOCK22,LOCK22" "0,1" bitfld.long 0x8 21. "LOCK21,LOCK21" "0,1" bitfld.long 0x8 20. "LOCK20,LOCK20" "0,1" bitfld.long 0x8 19. "LOCK19,LOCK19" "0,1" bitfld.long 0x8 18. "LOCK18,LOCK18" "0,1" newline bitfld.long 0x8 17. "LOCK17,LOCK17" "0,1" bitfld.long 0x8 16. "LOCK16,LOCK16" "0,1" bitfld.long 0x8 15. "LOCK15,LOCK15" "0,1" bitfld.long 0x8 14. "LOCK14,LOCK14" "0,1" bitfld.long 0x8 13. "LOCK13,LOCK13" "0,1" bitfld.long 0x8 12. "LOCK12,LOCK12" "0,1" bitfld.long 0x8 11. "LOCK11,LOCK11" "0,1" newline bitfld.long 0x8 10. "LOCK10,LOCK10" "0,1" bitfld.long 0x8 9. "LOCK9,LOCK9" "0,1" bitfld.long 0x8 8. "LOCK8,LOCK8" "0,1" bitfld.long 0x8 7. "LOCK7,LOCK7" "0,1" bitfld.long 0x8 6. "LOCK6,LOCK6" "0,1" bitfld.long 0x8 5. "LOCK5,LOCK5" "0,1" bitfld.long 0x8 4. "LOCK4,LOCK4" "0,1" newline bitfld.long 0x8 3. "LOCK3,LOCK3" "0,1" bitfld.long 0x8 2. "LOCK2,LOCK2" "0,1" bitfld.long 0x8 1. "LOCK1,LOCK1" "0,1" bitfld.long 0x8 0. "LOCK0,LOCK0" "0,1" rgroup.long 0x3F0++0xF line.long 0x0 "ETZPC_HWCFGR,ETZPC IP HW configuration register" hexmask.long.byte 0x0 24.--31. 1. "CHUNKS1N4,CHUNKS1N4" hexmask.long.byte 0x0 16.--23. 1. "NUM_AHB_SEC,NUM_AHB_SEC" hexmask.long.byte 0x0 8.--15. 1. "NUM_PER_SEC,NUM_PER_SEC" hexmask.long.byte 0x0 0.--7. 1. "NUM_TZMA,NUM_TZMA" line.long 0x4 "ETZPC_VERR,ETZPC IP version register" hexmask.long.byte 0x4 4.--7. 1. "MAJREV,MAJREV" hexmask.long.byte 0x4 0.--3. 1. "MINREV,MINREV" line.long 0x8 "ETZPC_IDR,ETZPC IP version register" hexmask.long 0x8 0.--31. 1. "ID,ID" line.long 0xC "ETZPC_SIDR,ETZPC IP version register" hexmask.long 0xC 0.--31. 1. "SID,SID" tree.end tree "EXTI (Extended Interrupt and Event Controller)" base ad:0x5000D000 group.long 0x0++0x17 line.long 0x0 "EXTI_RTSR1,Contains only register bits for configurable events." bitfld.long 0x0 16. "RT16,RT16" "0,1" bitfld.long 0x0 15. "RT15,RT15" "0,1" bitfld.long 0x0 14. "RT14,RT14" "0,1" bitfld.long 0x0 13. "RT13,RT13" "0,1" bitfld.long 0x0 12. "RT12,RT12" "0,1" bitfld.long 0x0 11. "RT11,RT11" "0,1" bitfld.long 0x0 10. "RT10,RT10" "0,1" bitfld.long 0x0 9. "RT9,RT9" "0,1" newline bitfld.long 0x0 8. "RT8,RT8" "0,1" bitfld.long 0x0 7. "RT7,RT7" "0,1" bitfld.long 0x0 6. "RT6,RT6" "0,1" bitfld.long 0x0 5. "RT5,RT5" "0,1" bitfld.long 0x0 4. "RT4,RT4" "0,1" bitfld.long 0x0 3. "RT3,RT3" "0,1" bitfld.long 0x0 2. "RT2,RT2" "0,1" bitfld.long 0x0 1. "RT1,RT1" "0,1" newline bitfld.long 0x0 0. "RT0,RT0" "0,1" line.long 0x4 "EXTI_FTSR1,Contains only register bits for configurable events." bitfld.long 0x4 16. "FT16,FT16" "0,1" bitfld.long 0x4 15. "FT15,FT15" "0,1" bitfld.long 0x4 14. "FT14,FT14" "0,1" bitfld.long 0x4 13. "FT13,FT13" "0,1" bitfld.long 0x4 12. "FT12,FT12" "0,1" bitfld.long 0x4 11. "FT11,FT11" "0,1" bitfld.long 0x4 10. "FT10,FT10" "0,1" bitfld.long 0x4 9. "FT9,FT9" "0,1" newline bitfld.long 0x4 8. "FT8,FT8" "0,1" bitfld.long 0x4 7. "FT7,FT7" "0,1" bitfld.long 0x4 6. "FT6,FT6" "0,1" bitfld.long 0x4 5. "FT5,FT5" "0,1" bitfld.long 0x4 4. "FT4,FT4" "0,1" bitfld.long 0x4 3. "FT3,FT3" "0,1" bitfld.long 0x4 2. "FT2,FT2" "0,1" bitfld.long 0x4 1. "FT1,FT1" "0,1" newline bitfld.long 0x4 0. "FT0,FT0" "0,1" line.long 0x8 "EXTI_SWIER1,Contains only register bits for configurable events." bitfld.long 0x8 16. "SWI16,SWI16" "0,1" bitfld.long 0x8 15. "SWI15,SWI15" "0,1" bitfld.long 0x8 14. "SWI14,SWI14" "0,1" bitfld.long 0x8 13. "SWI13,SWI13" "0,1" bitfld.long 0x8 12. "SWI12,SWI12" "0,1" bitfld.long 0x8 11. "SWI11,SWI11" "0,1" bitfld.long 0x8 10. "SWI10,SWI10" "0,1" bitfld.long 0x8 9. "SWI9,SWI9" "0,1" newline bitfld.long 0x8 8. "SWI8,SWI8" "0,1" bitfld.long 0x8 7. "SWI7,SWI7" "0,1" bitfld.long 0x8 6. "SWI6,SWI6" "0,1" bitfld.long 0x8 5. "SWI5,SWI5" "0,1" bitfld.long 0x8 4. "SWI4,SWI4" "0,1" bitfld.long 0x8 3. "SWI3,SWI3" "0,1" bitfld.long 0x8 2. "SWI2,SWI2" "0,1" bitfld.long 0x8 1. "SWI1,SWI1" "0,1" newline bitfld.long 0x8 0. "SWI0,SWI0" "0,1" line.long 0xC "EXTI_RPR1,Contains only register bits for configurable events." bitfld.long 0xC 16. "RPIF16,RPIF16" "0,1" bitfld.long 0xC 15. "RPIF15,RPIF15" "0,1" bitfld.long 0xC 14. "RPIF14,RPIF14" "0,1" bitfld.long 0xC 13. "RPIF13,RPIF13" "0,1" bitfld.long 0xC 12. "RPIF12,RPIF12" "0,1" bitfld.long 0xC 11. "RPIF11,RPIF11" "0,1" bitfld.long 0xC 10. "RPIF10,RPIF10" "0,1" bitfld.long 0xC 9. "RPIF9,RPIF9" "0,1" newline bitfld.long 0xC 8. "RPIF8,RPIF8" "0,1" bitfld.long 0xC 7. "RPIF7,RPIF7" "0,1" bitfld.long 0xC 6. "RPIF6,RPIF6" "0,1" bitfld.long 0xC 5. "RPIF5,RPIF5" "0,1" bitfld.long 0xC 4. "RPIF4,RPIF4" "0,1" bitfld.long 0xC 3. "RPIF3,RPIF3" "0,1" bitfld.long 0xC 2. "RPIF2,RPIF2" "0,1" bitfld.long 0xC 1. "RPIF1,RPIF1" "0,1" newline bitfld.long 0xC 0. "RPIF0,RPIF0" "0,1" line.long 0x10 "EXTI_FPR1,Contains only register bits for configurable events." bitfld.long 0x10 16. "FPIF16,FPIF16" "0,1" bitfld.long 0x10 15. "FPIF15,FPIF15" "0,1" bitfld.long 0x10 14. "FPIF14,FPIF14" "0,1" bitfld.long 0x10 13. "FPIF13,FPIF13" "0,1" bitfld.long 0x10 12. "FPIF12,FPIF12" "0,1" bitfld.long 0x10 11. "FPIF11,FPIF11" "0,1" bitfld.long 0x10 10. "FPIF10,FPIF10" "0,1" bitfld.long 0x10 9. "FPIF9,FPIF9" "0,1" newline bitfld.long 0x10 8. "FPIF8,FPIF8" "0,1" bitfld.long 0x10 7. "FPIF7,FPIF7" "0,1" bitfld.long 0x10 6. "FPIF6,FPIF6" "0,1" bitfld.long 0x10 5. "FPIF5,FPIF5" "0,1" bitfld.long 0x10 4. "FPIF4,FPIF4" "0,1" bitfld.long 0x10 3. "FPIF3,FPIF3" "0,1" bitfld.long 0x10 2. "FPIF2,FPIF2" "0,1" bitfld.long 0x10 1. "FPIF1,FPIF1" "0,1" newline bitfld.long 0x10 0. "FPIF0,FPIF0" "0,1" line.long 0x14 "EXTI_TZENR1,This register provides TrustZone Write access security. a non-secure write access will generate a bus error. A non-secure read will return the register data. Contains only register bits for TrustZone capable Input events." bitfld.long 0x14 26. "TZEN26,TZEN26" "0,1" bitfld.long 0x14 24. "TZEN24,TZEN24" "0,1" bitfld.long 0x14 19. "TZEN19,TZEN19" "0,1" bitfld.long 0x14 18. "TZEN18,TZEN18" "0,1" bitfld.long 0x14 17. "TZEN17,TZEN17" "0,1" bitfld.long 0x14 15. "TZEN15,TZEN15" "0,1" bitfld.long 0x14 14. "TZEN14,TZEN14" "0,1" bitfld.long 0x14 13. "TZEN13,TZEN13" "0,1" newline bitfld.long 0x14 12. "TZEN12,TZEN12" "0,1" bitfld.long 0x14 11. "TZEN11,TZEN11" "0,1" bitfld.long 0x14 10. "TZEN10,TZEN10" "0,1" bitfld.long 0x14 9. "TZEN9,TZEN9" "0,1" bitfld.long 0x14 8. "TZEN8,TZEN8" "0,1" bitfld.long 0x14 7. "TZEN7,TZEN7" "0,1" bitfld.long 0x14 6. "TZEN6,TZEN6" "0,1" bitfld.long 0x14 5. "TZEN5,TZEN5" "0,1" newline bitfld.long 0x14 4. "TZEN4,TZEN4" "0,1" bitfld.long 0x14 3. "TZEN3,TZEN3" "0,1" bitfld.long 0x14 2. "TZEN2,TZEN2" "0,1" bitfld.long 0x14 1. "TZEN1,TZEN1" "0,1" bitfld.long 0x14 0. "TZEN0,TZEN0" "0,1" group.long 0x20++0x17 line.long 0x0 "EXTI_RTSR2,Contains only register bits for configurable events." line.long 0x4 "EXTI_FTSR2,Contains only register bits for configurable events." line.long 0x8 "EXTI_SWIER2,Contains only register bits for configurable events." line.long 0xC "EXTI_RPR2,Contains only register bits for configurable events." line.long 0x10 "EXTI_FPR2,Contains only register bits for configurable events." line.long 0x14 "EXTI_TZENR2,This register provides TrustZone Write access security. a non-secure write access will generate a bus error. A non-secure read will return the register data. Contains only register bits for TrustZone capable Input events." bitfld.long 0x14 28. "TZEN60,TZEN60" "0,1" bitfld.long 0x14 27. "TZEN59,TZEN59" "0,1" bitfld.long 0x14 26. "TZEN58,TZEN58" "0,1" bitfld.long 0x14 25. "TZEN57,TZEN57" "0,1" bitfld.long 0x14 24. "TZEN56,TZEN56" "0,1" bitfld.long 0x14 23. "TZEN55,TZEN55" "0,1" bitfld.long 0x14 22. "TZEN54,TZEN54" "0,1" bitfld.long 0x14 9. "TZEN41,TZEN41" "0,1" group.long 0x40++0x17 line.long 0x0 "EXTI_RTSR3,Contains only register bits for configurable events." bitfld.long 0x0 10. "RT74,RT74" "0,1" bitfld.long 0x0 9. "RT73,RT73" "0,1" bitfld.long 0x0 4. "RT68,RT68" "0,1" bitfld.long 0x0 2. "RT66,RT66" "0,1" bitfld.long 0x0 1. "RT65,RT65" "0,1" line.long 0x4 "EXTI_FTSR3,Contains only register bits for configurable events." bitfld.long 0x4 10. "FT74,FT74" "0,1" bitfld.long 0x4 9. "FT73,FT73" "0,1" bitfld.long 0x4 4. "FT68,FT68" "0,1" bitfld.long 0x4 2. "FT66,FT66" "0,1" bitfld.long 0x4 1. "FT65,FT65" "0,1" line.long 0x8 "EXTI_SWIER3,Contains only register bits for configurable events." bitfld.long 0x8 10. "SWI74,SWI74" "0,1" bitfld.long 0x8 9. "SWI73,SWI73" "0,1" bitfld.long 0x8 4. "SWI68,SWI68" "0,1" bitfld.long 0x8 2. "SWI66,SWI66" "0,1" bitfld.long 0x8 1. "SWI65,SWI65" "0,1" line.long 0xC "EXTI_RPR3,Contains only register bits for configurable events." bitfld.long 0xC 10. "RPIF74,RPIF74" "0,1" bitfld.long 0xC 9. "RPIF73,RPIF73" "0,1" bitfld.long 0xC 4. "RPIF68,RPIF68" "0,1" bitfld.long 0xC 2. "RPIF66,RPIF66" "0,1" bitfld.long 0xC 1. "RPIF65,RPIF65" "0,1" line.long 0x10 "EXTI_FPR3,Contains only register bits for configurable events." bitfld.long 0x10 10. "FPIF74,FPIF74" "0,1" bitfld.long 0x10 9. "FPIF73,FPIF73" "0,1" bitfld.long 0x10 4. "FPIF68,FPIF68" "0,1" bitfld.long 0x10 2. "FPIF66,FPIF66" "0,1" bitfld.long 0x10 1. "FPIF65,FPIF65" "0,1" line.long 0x14 "EXTI_TZENR3,This register provides TrustZone Write access security. a non-secure write access will generate a bus error. A non-secure read will return the register data. Contains only register bits for TrustZone capable Input events." group.long 0x60++0xF line.long 0x0 "EXTI_EXTICR1,EXTIm fields contain only the number of bits in line with the nb_ioport configuration." hexmask.long.byte 0x0 24.--31. 1. "EXTI3,EXTI3" hexmask.long.byte 0x0 16.--23. 1. "EXTI2,EXTI2" hexmask.long.byte 0x0 8.--15. 1. "EXTI1,EXTI1" hexmask.long.byte 0x0 0.--7. 1. "EXTI0,EXTI0" line.long 0x4 "EXTI_EXTICR2,EXTIm fields contain only the number of bits in line with the nb_ioport configuration." hexmask.long.byte 0x4 24.--31. 1. "EXTI7,EXTI7" hexmask.long.byte 0x4 16.--23. 1. "EXTI6,EXTI6" hexmask.long.byte 0x4 8.--15. 1. "EXTI5,EXTI5" hexmask.long.byte 0x4 0.--7. 1. "EXTI4,EXTI4" line.long 0x8 "EXTI_EXTICR3,EXTIm fields contain only the number of bits in line with the nb_ioport configuration." hexmask.long.byte 0x8 24.--31. 1. "EXTI11,EXTI11" hexmask.long.byte 0x8 16.--23. 1. "EXTI10,EXTI10" hexmask.long.byte 0x8 8.--15. 1. "EXTI9,EXTI9" hexmask.long.byte 0x8 0.--7. 1. "EXTI8,EXTI8" line.long 0xC "EXTI_EXTICR4,EXTIm fields contain only the number of bits in line with the nb_ioport configuration." hexmask.long.byte 0xC 24.--31. 1. "EXTI15,EXTI15" hexmask.long.byte 0xC 16.--23. 1. "EXTI14,EXTI14" hexmask.long.byte 0xC 8.--15. 1. "EXTI13,EXTI13" hexmask.long.byte 0xC 0.--7. 1. "EXTI12,EXTI12" group.long 0x80++0x7 line.long 0x0 "EXTI_IMR1,Contains register bits for configurable events and Direct events." bitfld.long 0x0 31. "IM31,IM31" "0,1" bitfld.long 0x0 30. "IM30,IM30" "0,1" bitfld.long 0x0 29. "IM29,IM29" "0,1" bitfld.long 0x0 28. "IM28,IM28" "0,1" bitfld.long 0x0 27. "IM27,IM27" "0,1" bitfld.long 0x0 26. "IM26,IM26" "0,1" bitfld.long 0x0 25. "IM25,IM25" "0,1" bitfld.long 0x0 24. "IM24,IM24" "0,1" newline bitfld.long 0x0 23. "IM23,IM23" "0,1" bitfld.long 0x0 22. "IM22,IM22" "0,1" bitfld.long 0x0 21. "IM21,IM21" "0,1" bitfld.long 0x0 20. "IM20,IM20" "0,1" bitfld.long 0x0 19. "IM19,IM19" "0,1" bitfld.long 0x0 18. "IM18,IM18" "0,1" bitfld.long 0x0 17. "IM17,IM17" "0,1" bitfld.long 0x0 16. "IM16,IM16" "0,1" newline bitfld.long 0x0 15. "IM15,IM15" "0,1" bitfld.long 0x0 14. "IM14,IM14" "0,1" bitfld.long 0x0 13. "IM13,IM13" "0,1" bitfld.long 0x0 12. "IM12,IM12" "0,1" bitfld.long 0x0 11. "IM11,IM11" "0,1" bitfld.long 0x0 10. "IM10,IM10" "0,1" bitfld.long 0x0 9. "IM9,IM9" "0,1" bitfld.long 0x0 8. "IM8,IM8" "0,1" newline bitfld.long 0x0 7. "IM7,IM7" "0,1" bitfld.long 0x0 6. "IM6,IM6" "0,1" bitfld.long 0x0 5. "IM5,IM5" "0,1" bitfld.long 0x0 4. "IM4,IM4" "0,1" bitfld.long 0x0 3. "IM3,IM3" "0,1" bitfld.long 0x0 2. "IM2,IM2" "0,1" bitfld.long 0x0 1. "IM1,IM1" "0,1" bitfld.long 0x0 0. "IM0,IM0" "0,1" line.long 0x4 "EXTI_EMR1,EXTI CPU wakeup with event mask register" bitfld.long 0x4 19. "EM19,EM19" "0,1" bitfld.long 0x4 18. "EM18,EM18" "0,1" bitfld.long 0x4 17. "EM17,EM17" "0,1" bitfld.long 0x4 15. "EM15,EM15" "0,1" bitfld.long 0x4 14. "EM14,EM14" "0,1" bitfld.long 0x4 13. "EM13,EM13" "0,1" bitfld.long 0x4 12. "EM12,EM12" "0,1" bitfld.long 0x4 11. "EM11,EM11" "0,1" newline bitfld.long 0x4 10. "EM10,EM10" "0,1" bitfld.long 0x4 9. "EM9,EM9" "0,1" bitfld.long 0x4 8. "EM8,EM8" "0,1" bitfld.long 0x4 7. "EM7,EM7" "0,1" bitfld.long 0x4 6. "EM6,EM6" "0,1" bitfld.long 0x4 5. "EM5,EM5" "0,1" bitfld.long 0x4 4. "EM4,EM4" "0,1" bitfld.long 0x4 3. "EM3,EM3" "0,1" newline bitfld.long 0x4 2. "EM2,EM2" "0,1" bitfld.long 0x4 1. "EM1,EM1" "0,1" bitfld.long 0x4 0. "EM0,EM0" "0,1" group.long 0x90++0x7 line.long 0x0 "EXTI_IMR2,Contains register bits for configurable events and direct events." bitfld.long 0x0 31. "IM63,IM63" "0,1" bitfld.long 0x0 30. "IM62,IM62" "0,1" bitfld.long 0x0 29. "IM61,IM61" "0,1" bitfld.long 0x0 28. "IM60,IM60" "0,1" bitfld.long 0x0 27. "IM59,IM59" "0,1" bitfld.long 0x0 26. "IM58,IM58" "0,1" bitfld.long 0x0 25. "IM57,IM57" "0,1" bitfld.long 0x0 24. "IM56,IM56" "0,1" newline bitfld.long 0x0 23. "IM55,IM55" "0,1" bitfld.long 0x0 22. "IM54,IM54" "0,1" bitfld.long 0x0 21. "IM53,IM53" "0,1" bitfld.long 0x0 20. "IM52,IM52" "0,1" bitfld.long 0x0 19. "IM51,IM51" "0,1" bitfld.long 0x0 18. "IM50,IM50" "0,1" bitfld.long 0x0 17. "IM49,IM49" "0,1" bitfld.long 0x0 16. "IM48,IM48" "0,1" newline bitfld.long 0x0 15. "IM47,IM47" "0,1" bitfld.long 0x0 14. "IM46,IM46" "0,1" bitfld.long 0x0 13. "IM45,IM45" "0,1" bitfld.long 0x0 12. "IM44,IM44" "0,1" bitfld.long 0x0 11. "IM43,IM43" "0,1" bitfld.long 0x0 10. "IM42,IM42" "0,1" bitfld.long 0x0 9. "IM41,IM41" "0,1" bitfld.long 0x0 8. "IM40,IM40" "0,1" newline bitfld.long 0x0 7. "IM39,IM39" "0,1" bitfld.long 0x0 6. "IM38,IM38" "0,1" bitfld.long 0x0 5. "IM37,IM37" "0,1" bitfld.long 0x0 4. "IM36,IM36" "0,1" bitfld.long 0x0 3. "IM35,IM35" "0,1" bitfld.long 0x0 2. "IM34,IM34" "0,1" bitfld.long 0x0 1. "IM33,IM33" "0,1" bitfld.long 0x0 0. "IM32,IM32" "0,1" line.long 0x4 "EXTI_EMR2,EXTI CPU wakeup with event mask register" group.long 0xA0++0x7 line.long 0x0 "EXTI_IMR3,Contains register bits for configurable events and direct events." bitfld.long 0x0 11. "IM75,IM75" "0,1" bitfld.long 0x0 10. "IM74,IM74" "0,1" bitfld.long 0x0 9. "IM73,IM73" "0,1" bitfld.long 0x0 8. "IM72,IM72" "0,1" bitfld.long 0x0 7. "IM71,IM71" "0,1" bitfld.long 0x0 6. "IM70,IM70" "0,1" bitfld.long 0x0 5. "IM69,IM69" "0,1" bitfld.long 0x0 4. "IM68,IM68" "0,1" newline bitfld.long 0x0 3. "IM67,IM67" "0,1" bitfld.long 0x0 2. "IM66,IM66" "0,1" bitfld.long 0x0 1. "IM65,IM65" "0,1" bitfld.long 0x0 0. "IM64,IM64" "0,1" line.long 0x4 "EXTI_EMR3,EXTI CPU wakeup with event mask register" bitfld.long 0x4 2. "EM66,EM66" "0,1" group.long 0xC0++0x7 line.long 0x0 "EXTI_C2IMR1,Contains register bits for configurable events and Direct events." bitfld.long 0x0 31. "IM31,IM31" "0,1" bitfld.long 0x0 30. "IM30,IM30" "0,1" bitfld.long 0x0 29. "IM29,IM29" "0,1" bitfld.long 0x0 28. "IM28,IM28" "0,1" bitfld.long 0x0 27. "IM27,IM27" "0,1" bitfld.long 0x0 26. "IM26,IM26" "0,1" bitfld.long 0x0 25. "IM25,IM25" "0,1" bitfld.long 0x0 24. "IM24,IM24" "0,1" newline bitfld.long 0x0 23. "IM23,IM23" "0,1" bitfld.long 0x0 22. "IM22,IM22" "0,1" bitfld.long 0x0 21. "IM21,IM21" "0,1" bitfld.long 0x0 20. "IM20,IM20" "0,1" bitfld.long 0x0 19. "IM19,IM19" "0,1" bitfld.long 0x0 18. "IM18,IM18" "0,1" bitfld.long 0x0 17. "IM17,IM17" "0,1" bitfld.long 0x0 16. "IM16,IM16" "0,1" newline bitfld.long 0x0 15. "IM15,IM15" "0,1" bitfld.long 0x0 14. "IM14,IM14" "0,1" bitfld.long 0x0 13. "IM13,IM13" "0,1" bitfld.long 0x0 12. "IM12,IM12" "0,1" bitfld.long 0x0 11. "IM11,IM11" "0,1" bitfld.long 0x0 10. "IM10,IM10" "0,1" bitfld.long 0x0 9. "IM9,IM9" "0,1" bitfld.long 0x0 8. "IM8,IM8" "0,1" newline bitfld.long 0x0 7. "IM7,IM7" "0,1" bitfld.long 0x0 6. "IM6,IM6" "0,1" bitfld.long 0x0 5. "IM5,IM5" "0,1" bitfld.long 0x0 4. "IM4,IM4" "0,1" bitfld.long 0x0 3. "IM3,IM3" "0,1" bitfld.long 0x0 2. "IM2,IM2" "0,1" bitfld.long 0x0 1. "IM1,IM1" "0,1" bitfld.long 0x0 0. "IM0,IM0" "0,1" line.long 0x4 "EXTI_C2EMR1,EXTI CPU2 wakeup with event mask register" bitfld.long 0x4 19. "EM19,EM19" "0,1" bitfld.long 0x4 18. "EM18,EM18" "0,1" bitfld.long 0x4 17. "EM17,EM17" "0,1" bitfld.long 0x4 15. "EM15,EM15" "0,1" bitfld.long 0x4 14. "EM14,EM14" "0,1" bitfld.long 0x4 13. "EM13,EM13" "0,1" bitfld.long 0x4 12. "EM12,EM12" "0,1" bitfld.long 0x4 11. "EM11,EM11" "0,1" newline bitfld.long 0x4 10. "EM10,EM10" "0,1" bitfld.long 0x4 9. "EM9,EM9" "0,1" bitfld.long 0x4 8. "EM8,EM8" "0,1" bitfld.long 0x4 7. "EM7,EM7" "0,1" bitfld.long 0x4 6. "EM6,EM6" "0,1" bitfld.long 0x4 5. "EM5,EM5" "0,1" bitfld.long 0x4 4. "EM4,EM4" "0,1" bitfld.long 0x4 3. "EM3,EM3" "0,1" newline bitfld.long 0x4 2. "EM2,EM2" "0,1" bitfld.long 0x4 1. "EM1,EM1" "0,1" bitfld.long 0x4 0. "EM0,EM0" "0,1" group.long 0xD0++0x7 line.long 0x0 "EXTI_C2IMR2,Contains register bits for configurable events and direct events." bitfld.long 0x0 31. "IM63,IM63" "0,1" bitfld.long 0x0 30. "IM62,IM62" "0,1" bitfld.long 0x0 29. "IM61,IM61" "0,1" bitfld.long 0x0 28. "IM60,IM60" "0,1" bitfld.long 0x0 27. "IM59,IM59" "0,1" bitfld.long 0x0 26. "IM58,IM58" "0,1" bitfld.long 0x0 25. "IM57,IM57" "0,1" bitfld.long 0x0 24. "IM56,IM56" "0,1" newline bitfld.long 0x0 23. "IM55,IM55" "0,1" bitfld.long 0x0 22. "IM54,IM54" "0,1" bitfld.long 0x0 21. "IM53,IM53" "0,1" bitfld.long 0x0 20. "IM52,IM52" "0,1" bitfld.long 0x0 19. "IM51,IM51" "0,1" bitfld.long 0x0 18. "IM50,IM50" "0,1" bitfld.long 0x0 17. "IM49,IM49" "0,1" bitfld.long 0x0 16. "IM48,IM48" "0,1" newline bitfld.long 0x0 15. "IM47,IM47" "0,1" bitfld.long 0x0 14. "IM46,IM46" "0,1" bitfld.long 0x0 13. "IM45,IM45" "0,1" bitfld.long 0x0 12. "IM44,IM44" "0,1" bitfld.long 0x0 11. "IM43,IM43" "0,1" bitfld.long 0x0 10. "IM42,IM42" "0,1" bitfld.long 0x0 9. "IM41,IM41" "0,1" bitfld.long 0x0 8. "IM40,IM40" "0,1" newline bitfld.long 0x0 7. "IM39,IM39" "0,1" bitfld.long 0x0 6. "IM38,IM38" "0,1" bitfld.long 0x0 5. "IM37,IM37" "0,1" bitfld.long 0x0 4. "IM36,IM36" "0,1" bitfld.long 0x0 3. "IM35,IM35" "0,1" bitfld.long 0x0 2. "IM34,IM34" "0,1" bitfld.long 0x0 1. "IM33,IM33" "0,1" bitfld.long 0x0 0. "IM32,IM32" "0,1" line.long 0x4 "EXTI_C2EMR2,EXTI CPU2 wakeup with event mask register" group.long 0xE0++0x7 line.long 0x0 "EXTI_C2IMR3,Contains register bits for configurable events and direct events." bitfld.long 0x0 11. "IM75,IM75" "0,1" bitfld.long 0x0 10. "IM74,IM74" "0,1" bitfld.long 0x0 9. "IM73,IM73" "0,1" bitfld.long 0x0 8. "IM72,IM72" "0,1" bitfld.long 0x0 7. "IM71,IM71" "0,1" bitfld.long 0x0 6. "IM70,IM70" "0,1" bitfld.long 0x0 5. "IM69,IM69" "0,1" bitfld.long 0x0 4. "IM68,IM68" "0,1" newline bitfld.long 0x0 3. "IM67,IM67" "0,1" bitfld.long 0x0 2. "IM66,IM66" "0,1" bitfld.long 0x0 1. "IM65,IM65" "0,1" bitfld.long 0x0 0. "IM64,IM64" "0,1" line.long 0x4 "EXTI_C2EMR3,EXTI CPU2 wakeup with event mask register" bitfld.long 0x4 2. "EM66,EM66" "0,1" rgroup.long 0x3C0++0x3F line.long 0x0 "EXTI_HWCFGR13,EXTI hardware configuration register 13" hexmask.long 0x0 0.--31. 1. "TZ,TZ" line.long 0x4 "EXTI_HWCFGR12,EXTI hardware configuration register 12" hexmask.long 0x4 0.--31. 1. "TZ,TZ" line.long 0x8 "EXTI_HWCFGR11,EXTI hardware configuration register 11" hexmask.long 0x8 0.--31. 1. "TZ,TZ" line.long 0xC "EXTI_HWCFGR10,EXTI hardware configuration register 10" line.long 0x10 "EXTI_HWCFGR9,EXTI hardware configuration register 9" line.long 0x14 "EXTI_HWCFGR8,EXTI hardware configuration register 8" line.long 0x18 "EXTI_HWCFGR7,EXTI hardware configuration register 7" hexmask.long 0x18 0.--31. 1. "CPUEVENT,CPUEVENT" line.long 0x1C "EXTI_HWCFGR6,EXTI hardware configuration register 6" hexmask.long 0x1C 0.--31. 1. "CPUEVENT,CPUEVENT" line.long 0x20 "EXTI_HWCFGR5,EXTI hardware configuration register 5" hexmask.long 0x20 0.--31. 1. "CPUEVENT,CPUEVENT" line.long 0x24 "EXTI_HWCFGR4,EXTI hardware configuration register 4" hexmask.long 0x24 0.--31. 1. "EVENT_TRG,EVENT_TRG" line.long 0x28 "EXTI_HWCFGR3,EXTI hardware configuration register 3" hexmask.long 0x28 0.--31. 1. "EVENT_TRG,EVENT_TRG" line.long 0x2C "EXTI_HWCFGR2,EXTI hardware configuration register 2" hexmask.long 0x2C 0.--31. 1. "EVENT_TRG,EVENT_TRG" line.long 0x30 "EXTI_HWCFGR1,EXTI hardware configuration register 1" hexmask.long.byte 0x30 16.--23. 1. "NBIOPORT,NBIOPORT" hexmask.long.byte 0x30 12.--15. 1. "CPUEVTEN,CPUEVTEN" hexmask.long.byte 0x30 8.--11. 1. "NBCPUS,NBCPUS" hexmask.long.byte 0x30 0.--7. 1. "NBEVENTS,NBEVENTS" line.long 0x34 "EXTI_VERR,EXTI IP version register" hexmask.long.byte 0x34 4.--7. 1. "MAJREV,MAJREV" hexmask.long.byte 0x34 0.--3. 1. "MINREV,MINREV" line.long 0x38 "EXTI_IPIDR,EXTI identification register" hexmask.long 0x38 0.--31. 1. "IPID,IPID" line.long 0x3C "EXTI_SIDR,EXTI size ID register" hexmask.long 0x3C 0.--31. 1. "SID,SID" tree.end sif (cpuis("STM32MP13*")||cpuis("STM32MP153*")||cpuis("STM32MP157*")) tree "FDCAN (Controller Area Network with Flexible Data Rate)" base ad:0x0 tree "FDCAN1" base ad:0x4400E000 rgroup.long 0x0++0x7 line.long 0x0 "FDCAN_CREL,FDCAN core release register" hexmask.long.byte 0x0 28.--31. 1. "REL,REL" hexmask.long.byte 0x0 24.--27. 1. "STEP,STEP" hexmask.long.byte 0x0 20.--23. 1. "SUBSTEP,SUBSTEP" hexmask.long.byte 0x0 16.--19. 1. "YEAR,YEAR" hexmask.long.byte 0x0 8.--15. 1. "MON,MON" hexmask.long.byte 0x0 0.--7. 1. "DAY,DAY" line.long 0x4 "FDCAN_ENDN,FDCAN Endian register" hexmask.long 0x4 0.--31. 1. "ETV,ETV" group.long 0xC++0x23 line.long 0x0 "FDCAN_DBTP,This register is dedicated to data bit timing phase and only writable if bits FDCAN_CCCR.CCE and FDCAN_CCCR.INIT are set. The CAN time quantum may be programmed in the range from 1 to 32 FDCAN clock periods. tq = (DBRP + 1) FDCAN clock.." bitfld.long 0x0 23. "TDC,TDC" "0,1" hexmask.long.byte 0x0 16.--20. 1. "DBRP,DBRP" hexmask.long.byte 0x0 8.--12. 1. "DTSEG1,DTSEG1" hexmask.long.byte 0x0 4.--7. 1. "DTSEG2,DTSEG2" hexmask.long.byte 0x0 0.--3. 1. "DSJW,DSJW" line.long 0x4 "FDCAN_TEST,Write access to this register has to be enabled by setting bit FDCAN_CCCR.TEST to 1. All register functions are set to their reset values when bit FDCAN_CCCR.TEST is reset. Loop back mode and software control of Tx pin FDCANx_TX are hardware.." rbitfld.long 0x4 7. "RX,RX" "0,1" bitfld.long 0x4 5.--6. "TX,TX" "0,1,2,3" bitfld.long 0x4 4. "LBCK,LBCK" "0,1" line.long 0x8 "FDCAN_RWD,The RAM watchdog monitors the READY output of the message RAM. A message RAM access starts the message RAM watchdog counter with the value configured by the FDCAN_RWD.WDC bits. The counter is reloaded with FDCAN_RWD.WDC bits when the message.." hexmask.long.byte 0x8 8.--15. 1. "WDV,WDV" hexmask.long.byte 0x8 0.--7. 1. "WDC,WDC" line.long 0xC "FDCAN_CCCR,For details about setting and resetting of single bits see Software initialization." bitfld.long 0xC 15. "NISO,NISO" "0,1" bitfld.long 0xC 14. "TXP,TXP" "0,1" bitfld.long 0xC 13. "EFBI,EFBI" "0,1" bitfld.long 0xC 12. "PXHD,PXHD" "0,1" bitfld.long 0xC 9. "BRSE,BRSE" "0,1" bitfld.long 0xC 8. "FDOE,FDOE" "0,1" bitfld.long 0xC 7. "TEST,TEST" "0,1" bitfld.long 0xC 6. "DAR,DAR" "0,1" newline bitfld.long 0xC 5. "MON,MON" "0,1" bitfld.long 0xC 4. "CSR,CSR" "0,1" rbitfld.long 0xC 3. "CSA,CSA" "0,1" bitfld.long 0xC 2. "ASM,ASM" "0,1" bitfld.long 0xC 1. "CCE,CCE" "0,1" bitfld.long 0xC 0. "INIT,INIT" "0,1" line.long 0x10 "FDCAN_NBTP,This register is dedicated to the nominal bit timing used during the arbitration phase." hexmask.long.byte 0x10 25.--31. 1. "NSJW,NSJW" hexmask.long.word 0x10 16.--24. 1. "NBRP,NBRP" hexmask.long.byte 0x10 8.--15. 1. "NTSEG1,NTSEG1" hexmask.long.byte 0x10 0.--6. 1. "NTSEG2,NTSEG2" line.long 0x14 "FDCAN_TSCC,FDCAN timestamp counter configuration register" hexmask.long.byte 0x14 16.--19. 1. "TCP,TCP" bitfld.long 0x14 0.--1. "TSS,TSS" "0,1,2,3" line.long 0x18 "FDCAN_TSCV,FDCAN timestamp counter value register" hexmask.long.word 0x18 0.--15. 1. "TSC,TSC" line.long 0x1C "FDCAN_TOCC,FDCAN timeout counter configuration register" hexmask.long.word 0x1C 16.--31. 1. "TOP,TOP" bitfld.long 0x1C 1.--2. "TOS,TOS" "0,1,2,3" bitfld.long 0x1C 0. "ETOC,ETOC" "0,1" line.long 0x20 "FDCAN_TOCV,FDCAN timeout counter value register" hexmask.long.word 0x20 0.--15. 1. "TOC,TOC" group.long 0x40++0xB line.long 0x0 "FDCAN_ECR,FDCAN error counter register" hexmask.long.byte 0x0 16.--23. 1. "CEL,CEL" rbitfld.long 0x0 15. "RP,RP" "0,1" hexmask.long.byte 0x0 8.--14. 1. "TREC,TREC" hexmask.long.byte 0x0 0.--7. 1. "TEC,TEC" line.long 0x4 "FDCAN_PSR,FDCAN protocol status register" hexmask.long.byte 0x4 16.--22. 1. "TDCV,TDCV" bitfld.long 0x4 14. "PXE,PXE" "0,1" bitfld.long 0x4 13. "REDL,REDL" "0,1" bitfld.long 0x4 12. "RBRS,RBRS" "0,1" bitfld.long 0x4 11. "RESI,RESI" "0,1" rbitfld.long 0x4 8.--10. "DLEC,DLEC" "0,1,2,3,4,5,6,7" rbitfld.long 0x4 7. "BO,BO" "0,1" rbitfld.long 0x4 6. "EW,EW" "0,1" newline rbitfld.long 0x4 5. "EP,EP" "0,1" rbitfld.long 0x4 3.--4. "ACT,ACT" "0,1,2,3" rbitfld.long 0x4 0.--2. "LEC,LEC" "0,1,2,3,4,5,6,7" line.long 0x8 "FDCAN_TDCR,FDCAN transmitter delay compensation register" hexmask.long.byte 0x8 8.--14. 1. "TDCO,TDCO" hexmask.long.byte 0x8 0.--6. 1. "TDCF,TDCF" group.long 0x50++0xF line.long 0x0 "FDCAN_IR,The flags are set when one of the listed conditions is detected (edge-sensitive). The flags remain set until the Host clears them. A flag is cleared by writing a 1 to the corresponding bit position. Writing a 0 has no effect. A hard reset will.." bitfld.long 0x0 29. "ARA,ARA" "0,1" bitfld.long 0x0 28. "PED,PED" "0,1" bitfld.long 0x0 27. "PEA,PEA" "0,1" bitfld.long 0x0 26. "WDI,WDI" "0,1" bitfld.long 0x0 25. "BO,BO" "0,1" bitfld.long 0x0 24. "EW,EW" "0,1" bitfld.long 0x0 23. "EP,EP" "0,1" bitfld.long 0x0 22. "ELO,ELO" "0,1" newline bitfld.long 0x0 19. "DRX,DRX" "0,1" bitfld.long 0x0 18. "TOO,TOO" "0,1" bitfld.long 0x0 17. "MRAF,MRAF" "0,1" bitfld.long 0x0 16. "TSW,TSW" "0,1" bitfld.long 0x0 15. "TEFL,TEFL" "0,1" bitfld.long 0x0 14. "TEFF,TEFF" "0,1" bitfld.long 0x0 13. "TEFW,TEFW" "0,1" bitfld.long 0x0 12. "TEFN,TEFN" "0,1" newline bitfld.long 0x0 11. "TFE,TFE" "0,1" bitfld.long 0x0 10. "TCF,TCF" "0,1" bitfld.long 0x0 9. "TC,TC" "0,1" bitfld.long 0x0 8. "HPM,HPM" "0,1" bitfld.long 0x0 7. "RF1L,RF1L" "0,1" bitfld.long 0x0 6. "RF1F,RF1F" "0,1" bitfld.long 0x0 5. "RF1W,RF1W" "0,1" bitfld.long 0x0 4. "RF1N,RF1N" "0,1" newline bitfld.long 0x0 3. "RF0L,RF0L" "0,1" bitfld.long 0x0 2. "RF0F,RF0F" "0,1" bitfld.long 0x0 1. "RF0W,RF0W" "0,1" bitfld.long 0x0 0. "RF0N,RF0N" "0,1" line.long 0x4 "FDCAN_IE,The settings in the interrupt enable register determine which status changes in the interrupt register will be signaled on an interrupt line." bitfld.long 0x4 29. "ARAE,ARAE" "0,1" bitfld.long 0x4 28. "PEDE,PEDE" "0,1" bitfld.long 0x4 27. "PEAE,PEAE" "0,1" bitfld.long 0x4 26. "WDIE,WDIE" "0,1" bitfld.long 0x4 25. "BOE,BOE" "0,1" bitfld.long 0x4 24. "EWE,EWE" "0,1" bitfld.long 0x4 23. "EPE,EPE" "0,1" bitfld.long 0x4 22. "ELOE,ELOE" "0,1" newline bitfld.long 0x4 21. "BEUE,BEUE" "0,1" bitfld.long 0x4 20. "BECE,BECE" "0,1" bitfld.long 0x4 19. "DRXE,DRXE" "0,1" bitfld.long 0x4 18. "TOOE,TOOE" "0,1" bitfld.long 0x4 17. "MRAFE,MRAFE" "0,1" bitfld.long 0x4 16. "TSWE,TSWE" "0,1" bitfld.long 0x4 15. "TEFLE,TEFLE" "0,1" bitfld.long 0x4 14. "TEFFE,TEFFE" "0,1" newline bitfld.long 0x4 13. "TEFWE,TEFWE" "0,1" bitfld.long 0x4 12. "TEFNE,TEFNE" "0,1" bitfld.long 0x4 11. "TFEE,TFEE" "0,1" bitfld.long 0x4 10. "TCFE,TCFE" "0,1" bitfld.long 0x4 9. "TCE,TCE" "0,1" bitfld.long 0x4 8. "HPME,HPME" "0,1" bitfld.long 0x4 7. "RF1LE,RF1LE" "0,1" bitfld.long 0x4 6. "RF1FE,RF1FE" "0,1" newline bitfld.long 0x4 5. "RF1WE,RF1WE" "0,1" bitfld.long 0x4 4. "RF1NE,RF1NE" "0,1" bitfld.long 0x4 3. "RF0LE,RF0LE" "0,1" bitfld.long 0x4 2. "RF0FE,RF0FE" "0,1" bitfld.long 0x4 1. "RF0WE,RF0WE" "0,1" bitfld.long 0x4 0. "RF0NE,RF0NE" "0,1" line.long 0x8 "FDCAN_ILS,This register assigns an interrupt generated by a specific interrupt flag from the interrupt register to one of the two module interrupt lines. For interrupt generation the respective interrupt line has to be enabled via FDCAN_ILE.EINT0 and.." bitfld.long 0x8 29. "ARAL,ARAL" "0,1" bitfld.long 0x8 28. "PEDL,PEDL" "0,1" bitfld.long 0x8 27. "PEAL,PEAL" "0,1" bitfld.long 0x8 26. "WDIL,WDIL" "0,1" bitfld.long 0x8 25. "BOL,BOL" "0,1" bitfld.long 0x8 24. "EWL,EWL" "0,1" bitfld.long 0x8 23. "EPL,EPL" "0,1" bitfld.long 0x8 22. "ELOL,ELOL" "0,1" newline bitfld.long 0x8 21. "BEUL,BEUL" "0,1" bitfld.long 0x8 20. "BECL,BECL" "0,1" bitfld.long 0x8 19. "DRXL,DRXL" "0,1" bitfld.long 0x8 18. "TOOL,TOOL" "0,1" bitfld.long 0x8 17. "MRAFL,MRAFL" "0,1" bitfld.long 0x8 16. "TSWL,TSWL" "0,1" bitfld.long 0x8 15. "TEFLL,TEFLL" "0,1" bitfld.long 0x8 14. "TEFFL,TEFFL" "0,1" newline bitfld.long 0x8 13. "TEFWL,TEFWL" "0,1" bitfld.long 0x8 12. "TEFNL,TEFNL" "0,1" bitfld.long 0x8 11. "TFEL,TFEL" "0,1" bitfld.long 0x8 10. "TCFL,TCFL" "0,1" bitfld.long 0x8 9. "TCL,TCL" "0,1" bitfld.long 0x8 8. "HPML,HPML" "0,1" bitfld.long 0x8 7. "RF1LL,RF1LL" "0,1" bitfld.long 0x8 6. "RF1FL,RF1FL" "0,1" newline bitfld.long 0x8 5. "RF1WL,RF1WL" "0,1" bitfld.long 0x8 4. "RF1NL,RF1NL" "0,1" bitfld.long 0x8 3. "RF0LL,RF0LL" "0,1" bitfld.long 0x8 2. "RF0FL,RF0FL" "0,1" bitfld.long 0x8 1. "RF0WL,RF0WL" "0,1" bitfld.long 0x8 0. "RF0NL,RF0NL" "0,1" line.long 0xC "FDCAN_ILE,Each of the two interrupt lines to the CPU can be enabled/disabled separately by programming bits EINT0 and EINT1." bitfld.long 0xC 1. "EINT1,EINT1" "0,1" bitfld.long 0xC 0. "EINT0,EINT0" "0,1" group.long 0x80++0xB line.long 0x0 "FDCAN_GFC,Global settings for message ID filtering. The global filter configuration register controls the filter path for standard and extended messages as described in Figure708: Standard message ID filter path and Figure709: Extended message ID filter.." bitfld.long 0x0 4.--5. "ANFS,ANFS" "0,1,2,3" bitfld.long 0x0 2.--3. "ANFE,ANFE" "0,1,2,3" bitfld.long 0x0 1. "RRFS,RRFS" "0,1" bitfld.long 0x0 0. "RRFE,RRFE" "0,1" line.long 0x4 "FDCAN_SIDFC,Settings for 11-bit standard message ID filtering.The standard ID filter configuration register controls the filter path for standard messages as described in Figure708." hexmask.long.byte 0x4 16.--23. 1. "LSS,LSS" hexmask.long.word 0x4 2.--15. 1. "FLSSA,FLSSA" line.long 0x8 "FDCAN_XIDFC,Settings for 29-bit extended message ID filtering. The FDCAN extended ID filter configuration register controls the filter path for standard messages as described in Figure709: Extended message ID filter path." hexmask.long.byte 0x8 16.--23. 1. "LSE,LSE" hexmask.long.word 0x8 2.--15. 1. "FLESA,FLESA" group.long 0x90++0x3 line.long 0x0 "FDCAN_XIDAM,FDCAN extended ID and mask register" hexmask.long 0x0 0.--28. 1. "EIDM,EIDM" rgroup.long 0x94++0x3 line.long 0x0 "FDCAN_HPMS,This register is updated every time a message ID filter element configured to generate a priority event match. This can be used to monitor the status of incoming high priority messages and to enable fast access to these messages." bitfld.long 0x0 15. "FLST,FLST" "0,1" hexmask.long.byte 0x0 8.--14. 1. "FIDX,FIDX" bitfld.long 0x0 6.--7. "MSI,MSI" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "BIDX,BIDX" group.long 0x98++0x1B line.long 0x0 "FDCAN_NDAT1,FDCAN new data 1 register" bitfld.long 0x0 31. "ND31,ND31" "0,1" bitfld.long 0x0 30. "ND30,ND30" "0,1" bitfld.long 0x0 29. "ND29,ND29" "0,1" bitfld.long 0x0 28. "ND28,ND28" "0,1" bitfld.long 0x0 27. "ND27,ND27" "0,1" bitfld.long 0x0 26. "ND26,ND26" "0,1" bitfld.long 0x0 25. "ND25,ND25" "0,1" bitfld.long 0x0 24. "ND24,ND24" "0,1" newline bitfld.long 0x0 23. "ND23,ND23" "0,1" bitfld.long 0x0 22. "ND22,ND22" "0,1" bitfld.long 0x0 21. "ND21,ND21" "0,1" bitfld.long 0x0 20. "ND20,ND20" "0,1" bitfld.long 0x0 19. "ND19,ND19" "0,1" bitfld.long 0x0 18. "ND18,ND18" "0,1" bitfld.long 0x0 17. "ND17,ND17" "0,1" bitfld.long 0x0 16. "ND16,ND16" "0,1" newline bitfld.long 0x0 15. "ND15,ND15" "0,1" bitfld.long 0x0 14. "ND14,ND14" "0,1" bitfld.long 0x0 13. "ND13,ND13" "0,1" bitfld.long 0x0 12. "ND12,ND12" "0,1" bitfld.long 0x0 11. "ND11,ND11" "0,1" bitfld.long 0x0 10. "ND10,ND10" "0,1" bitfld.long 0x0 9. "ND9,ND9" "0,1" bitfld.long 0x0 8. "ND8,ND8" "0,1" newline bitfld.long 0x0 7. "ND7,ND7" "0,1" bitfld.long 0x0 6. "ND6,ND6" "0,1" bitfld.long 0x0 5. "ND5,ND5" "0,1" bitfld.long 0x0 4. "ND4,ND4" "0,1" bitfld.long 0x0 3. "ND3,ND3" "0,1" bitfld.long 0x0 2. "ND2,ND2" "0,1" bitfld.long 0x0 1. "ND1,ND1" "0,1" bitfld.long 0x0 0. "ND0,ND0" "0,1" line.long 0x4 "FDCAN_NDAT2,FDCAN new data 2 register" bitfld.long 0x4 31. "ND63,ND63" "0,1" bitfld.long 0x4 30. "ND62,ND62" "0,1" bitfld.long 0x4 29. "ND61,ND61" "0,1" bitfld.long 0x4 28. "ND60,ND60" "0,1" bitfld.long 0x4 27. "ND59,ND59" "0,1" bitfld.long 0x4 26. "ND58,ND58" "0,1" bitfld.long 0x4 25. "ND57,ND57" "0,1" bitfld.long 0x4 24. "ND56,ND56" "0,1" newline bitfld.long 0x4 23. "ND55,ND55" "0,1" bitfld.long 0x4 22. "ND54,ND54" "0,1" bitfld.long 0x4 21. "ND53,ND53" "0,1" bitfld.long 0x4 20. "ND52,ND52" "0,1" bitfld.long 0x4 19. "ND51,ND51" "0,1" bitfld.long 0x4 18. "ND50,ND50" "0,1" bitfld.long 0x4 17. "ND49,ND49" "0,1" bitfld.long 0x4 16. "ND48,ND48" "0,1" newline bitfld.long 0x4 15. "ND47,ND47" "0,1" bitfld.long 0x4 14. "ND46,ND46" "0,1" bitfld.long 0x4 13. "ND45,ND45" "0,1" bitfld.long 0x4 12. "ND44,ND44" "0,1" bitfld.long 0x4 11. "ND43,ND43" "0,1" bitfld.long 0x4 10. "ND42,ND42" "0,1" bitfld.long 0x4 9. "ND41,ND41" "0,1" bitfld.long 0x4 8. "ND40,ND40" "0,1" newline bitfld.long 0x4 7. "ND39,ND39" "0,1" bitfld.long 0x4 6. "ND38,ND38" "0,1" bitfld.long 0x4 5. "ND37,ND37" "0,1" bitfld.long 0x4 4. "ND36,ND36" "0,1" bitfld.long 0x4 3. "ND35,ND35" "0,1" bitfld.long 0x4 2. "ND34,ND34" "0,1" bitfld.long 0x4 1. "ND33,ND33" "0,1" bitfld.long 0x4 0. "ND32,ND32" "0,1" line.long 0x8 "FDCAN_RXF0C,FDCAN Rx FIFO 0 configuration register" bitfld.long 0x8 31. "F0OM,F0OM" "0,1" hexmask.long.byte 0x8 24.--30. 1. "F0WM,F0WM" hexmask.long.byte 0x8 16.--22. 1. "F0S,F0S" hexmask.long.word 0x8 2.--15. 1. "F0SA,F0SA" line.long 0xC "FDCAN_RXF0S,FDCAN Rx FIFO 0 status register" bitfld.long 0xC 25. "RF0L,RF0L" "0,1" bitfld.long 0xC 24. "F0F,F0F" "0,1" hexmask.long.byte 0xC 16.--21. 1. "F0PI,F0PI" hexmask.long.byte 0xC 8.--13. 1. "F0GI,F0GI" hexmask.long.byte 0xC 0.--6. 1. "F0FL,F0FL" line.long 0x10 "FDCAN_RXF0A,FDCAN Rx FIFO 0 acknowledge register" hexmask.long.byte 0x10 0.--5. 1. "F0AI,F0AI" line.long 0x14 "FDCAN_RXBC,FDCAN Rx buffer configuration register" hexmask.long.word 0x14 2.--15. 1. "RBSA,RBSA" line.long 0x18 "FDCAN_RXF1C,FDCAN Rx FIFO 1 configuration register" bitfld.long 0x18 31. "F1OM,F1OM" "0,1" hexmask.long.byte 0x18 24.--30. 1. "F1WM,F1WM" hexmask.long.byte 0x18 16.--22. 1. "F1S,F1S" hexmask.long.word 0x18 2.--15. 1. "F1SA,F1SA" rgroup.long 0xB4++0x3 line.long 0x0 "FDCAN_RXF1S,FDCAN Rx FIFO 1 status register" bitfld.long 0x0 30.--31. "DMS,DMS" "0,1,2,3" bitfld.long 0x0 25. "RF1L,RF1L" "0,1" bitfld.long 0x0 24. "F1F,F1F" "0,1" hexmask.long.byte 0x0 16.--21. 1. "F1PI,F1PI" hexmask.long.byte 0x0 8.--13. 1. "F1GI,F1GI" hexmask.long.byte 0x0 0.--6. 1. "F1FL,F1FL" group.long 0xB8++0x3 line.long 0x0 "FDCAN_RXF1A,FDCAN Rx FIFO 1 acknowledge register" hexmask.long.byte 0x0 0.--5. 1. "F1AI,F1AI" rgroup.long 0xBC++0x3 line.long 0x0 "FDCAN_RXESC,Configures the number of data bytes belonging to an Rx buffer / Rx FIFO element. Data field sizes higher than 8 bytes are intended for CAN FD operation only." bitfld.long 0x0 8.--10. "RBDS,RBDS" "0,1,2,3,4,5,6,7" bitfld.long 0x0 4.--6. "F1DS,F1DS" "0,1,2,3,4,5,6,7" bitfld.long 0x0 0.--2. "F0DS,F0DS" "0,1,2,3,4,5,6,7" group.long 0xC0++0x3 line.long 0x0 "FDCAN_TXBC,FDCAN Tx buffer configuration register" bitfld.long 0x0 30. "TFQM,TFQM" "0,1" hexmask.long.byte 0x0 24.--29. 1. "TFQS,TFQS" hexmask.long.byte 0x0 16.--21. 1. "NDTB,NDTB" hexmask.long.word 0x0 2.--15. 1. "TBSA,TBSA" rgroup.long 0xC4++0x7 line.long 0x0 "FDCAN_TXFQS,The Tx FIFO/queue status is related to the pending Tx requests listed in register FDCAN_TXBRP. Therefore the effect of add/cancellation requests may be delayed due to a running Tx scan (FDCAN_TXBRP not yet updated)." bitfld.long 0x0 21. "TFQF,TFQF" "0,1" hexmask.long.byte 0x0 16.--20. 1. "TFQPI,TFQPI" hexmask.long.byte 0x0 8.--12. 1. "TFGI,TFGI" hexmask.long.byte 0x0 0.--5. 1. "TFFL,TFFL" line.long 0x4 "FDCAN_TXESC,Configures the number of data bytes belonging to a Tx buffer element. Data field sizes >8 bytes are intended for CAN FD operation only." bitfld.long 0x4 0.--2. "TBDS,TBDS" "0,1,2,3,4,5,6,7" group.long 0xD0++0x7 line.long 0x0 "FDCAN_TXBAR,FDCAN Tx buffer add request register" hexmask.long 0x0 0.--31. 1. "AR,AR" line.long 0x4 "FDCAN_TXBCR,FDCAN Tx buffer cancellation request register" hexmask.long 0x4 0.--31. 1. "CR,CR" rgroup.long 0xD8++0x7 line.long 0x0 "FDCAN_TXBTO,FDCAN Tx buffer transmission occurred register" hexmask.long 0x0 0.--31. 1. "TO,TO" line.long 0x4 "FDCAN_TXBCF,FDCAN Tx buffer cancellation finished register" hexmask.long 0x4 0.--31. 1. "CF,CF" group.long 0xE0++0x7 line.long 0x0 "FDCAN_TXBTIE,FDCAN Tx buffer transmission interrupt enable register" hexmask.long 0x0 0.--31. 1. "TIE,TIE" line.long 0x4 "FDCAN_TXBCIE,FDCAN Tx buffer cancellation finished interrupt enable register" hexmask.long 0x4 0.--31. 1. "CFIE,CFIE" group.long 0xF0++0x3 line.long 0x0 "FDCAN_TXEFC,FDCAN Tx event FIFO configuration register" hexmask.long.byte 0x0 24.--29. 1. "EFWM,EFWM" hexmask.long.byte 0x0 16.--21. 1. "EFS,EFS" hexmask.long.word 0x0 2.--15. 1. "EFSA,EFSA" rgroup.long 0xF4++0x3 line.long 0x0 "FDCAN_TXEFS,FDCAN Tx event FIFO status register" bitfld.long 0x0 25. "TEFL,TEFL" "0,1" bitfld.long 0x0 24. "EFF,EFF" "0,1" hexmask.long.byte 0x0 16.--20. 1. "EFPI,EFPI" hexmask.long.byte 0x0 8.--12. 1. "EFGI,EFGI" hexmask.long.byte 0x0 0.--5. 1. "EFFL,EFFL" group.long 0xF8++0x3 line.long 0x0 "FDCAN_TXEFA,FDCAN Tx event FIFO acknowledge register" hexmask.long.byte 0x0 0.--4. 1. "EFAI,EFAI" group.long 0x100++0x2B line.long 0x0 "FDCAN_TTTMC,FDCAN TT trigger memory configuration register" hexmask.long.byte 0x0 16.--22. 1. "TME,TME" hexmask.long.word 0x0 2.--15. 1. "TMSA,TMSA" line.long 0x4 "FDCAN_TTRMC,FDCAN TT reference message configuration register" bitfld.long 0x4 31. "RMPS,RMPS" "0,1" bitfld.long 0x4 30. "XTD,XTD" "0,1" hexmask.long 0x4 0.--28. 1. "RID,RID" line.long 0x8 "FDCAN_TTOCF,FDCAN TT operation configuration register" bitfld.long 0x8 26. "EVTP,EVTP" "0,1" bitfld.long 0x8 25. "ECC,ECC" "0,1" bitfld.long 0x8 24. "EGTF,EGTF" "0,1" hexmask.long.byte 0x8 16.--23. 1. "AWL,AWL" bitfld.long 0x8 15. "EECS,EECS" "0,1" hexmask.long.byte 0x8 8.--14. 1. "IRTO,IRTO" bitfld.long 0x8 5.--7. "LDSDL,LDSDL" "0,1,2,3,4,5,6,7" bitfld.long 0x8 4. "TM,TM" "0,1" newline bitfld.long 0x8 3. "GEN,GEN" "0,1" bitfld.long 0x8 0.--1. "OM,OM" "0,1,2,3" line.long 0xC "FDCAN_TTMLM,FDCAN TT matrix limits register" hexmask.long.word 0xC 16.--27. 1. "ENTT,ENTT" hexmask.long.byte 0xC 8.--11. 1. "TXEW,TXEW" bitfld.long 0xC 6.--7. "CSS,CSS" "0,1,2,3" hexmask.long.byte 0xC 0.--5. 1. "CCM,CCM" line.long 0x10 "FDCAN_TURCF,The length of the NTU is given by: NTU = CAN clock period x NC/DC. NC is an 18-bit value. Its high part. NCH[17:16] is hard wired to 0b01. Therefore the range of NC extends from 0x10000 to 0x1FFFF. The value configured by NCL is the initial.." bitfld.long 0x10 31. "ELT,ELT" "0,1" hexmask.long.word 0x10 16.--29. 1. "DC,DC" hexmask.long.word 0x10 0.--15. 1. "NCL,NCL" line.long 0x14 "FDCAN_TTOCN,FDCAN TT operation control register" rbitfld.long 0x14 15. "LCKC,LCKC" "0,1" bitfld.long 0x14 13. "ESCN,ESCN" "0,1" bitfld.long 0x14 12. "NIG,NIG" "0,1" bitfld.long 0x14 11. "TMG,TMG" "0,1" bitfld.long 0x14 10. "FGP,FGP" "0,1" bitfld.long 0x14 9. "GCS,GCS" "0,1" bitfld.long 0x14 8. "TTIE,TTIE" "0,1" bitfld.long 0x14 6.--7. "TMC,TMC" "0,1,2,3" newline bitfld.long 0x14 5. "RTIE,RTIE" "0,1" bitfld.long 0x14 3.--4. "SWS,SWS" "0,1,2,3" bitfld.long 0x14 2. "SWP,SWP" "0,1" bitfld.long 0x14 1. "ECS,ECS" "0,1" bitfld.long 0x14 0. "SGT,SGT" "0,1" line.long 0x18 "FDCAN_TTGTP,If TTOST.WGDT is set. the next reference message will be transmitted with the Master_Ref_Mark modified by the preset value and with Disc_Bit = 1. presetting the global time in all nodes simultaneously. TP is reset to 0x0000 each time a.." hexmask.long.word 0x18 16.--31. 1. "CTP,CTP" hexmask.long.word 0x18 0.--15. 1. "TP,TP" line.long 0x1C "FDCAN_TTTMK,A time mark interrupt (FDCAN_TTIR.TMI = 1) is generated when the time base indicated by FDCAN_TTOCN.TMC (cycle time. local time. or global time) has the same value as TM." rbitfld.long 0x1C 31. "LCKM,LCKM" "0,1" hexmask.long.byte 0x1C 16.--22. 1. "TICC,TICC" hexmask.long.word 0x1C 0.--15. 1. "TM,TM" line.long 0x20 "FDCAN_TTIR,The flags are set when one of the listed conditions is detected (edge-sensitive). The flags remain set until the Host clears them. A flag is cleared by writing a 1 to the corresponding bit position. Writing a 0 has no effect. A hard reset will.." bitfld.long 0x20 18. "CER,CER" "0,1" bitfld.long 0x20 17. "AW,AW" "0,1" bitfld.long 0x20 16. "WT,WT" "0,1" bitfld.long 0x20 15. "IWTG,IWTG" "0,1" bitfld.long 0x20 14. "ELC,ELC" "0,1" bitfld.long 0x20 13. "SE2,SE2" "0,1" bitfld.long 0x20 12. "SE1,SE1" "0,1" bitfld.long 0x20 11. "TXO,TXO" "0,1" newline bitfld.long 0x20 10. "TXU,TXU" "0,1" bitfld.long 0x20 9. "GTE,GTE" "0,1" bitfld.long 0x20 8. "GTD,GTD" "0,1" bitfld.long 0x20 7. "GTW,GTW" "0,1" bitfld.long 0x20 6. "SWE,SWE" "0,1" bitfld.long 0x20 5. "TTMI,TTMI" "0,1" bitfld.long 0x20 4. "RTMI,RTMI" "0,1" bitfld.long 0x20 3. "SOG,SOG" "0,1" newline bitfld.long 0x20 2. "CSM,CSM" "0,1" bitfld.long 0x20 1. "SMC,SMC" "0,1" bitfld.long 0x20 0. "SBC,SBC" "0,1" line.long 0x24 "FDCAN_TTIE,The settings in the TT interrupt enable register determine which status changes in the TT interrupt register will result in an interrupt." bitfld.long 0x24 18. "CERE,CERE" "0,1" bitfld.long 0x24 17. "AWE,AWE" "0,1" bitfld.long 0x24 16. "WTE,WTE" "0,1" bitfld.long 0x24 15. "IWTE,IWTE" "0,1" bitfld.long 0x24 14. "ELCE,ELCE" "0,1" bitfld.long 0x24 13. "SE2E,SE2E" "0,1" bitfld.long 0x24 12. "SE1E,SE1E" "0,1" bitfld.long 0x24 11. "TXOE,TXOE" "0,1" newline bitfld.long 0x24 10. "TXUE,TXUE" "0,1" bitfld.long 0x24 9. "GTEE,GTEE" "0,1" bitfld.long 0x24 8. "GTDE,GTDE" "0,1" bitfld.long 0x24 7. "GTWE,GTWE" "0,1" bitfld.long 0x24 6. "SWEE,SWEE" "0,1" bitfld.long 0x24 5. "TTMIE,TTMIE" "0,1" bitfld.long 0x24 4. "RTMIE,RTMIE" "0,1" bitfld.long 0x24 3. "SOGE,SOGE" "0,1" newline bitfld.long 0x24 2. "CSME,CSME" "0,1" bitfld.long 0x24 1. "SMCE,SMCE" "0,1" bitfld.long 0x24 0. "SBCE,SBCE" "0,1" line.long 0x28 "FDCAN_TTILS,The TT interrupt Line select register assigns an interrupt generated by a specific interrupt flag from the TT interrupt register to one of the two module interrupt lines. For interrupt generation the respective interrupt line has to be.." bitfld.long 0x28 18. "CERL,CERL" "0,1" bitfld.long 0x28 17. "AWL,AWL" "0,1" bitfld.long 0x28 16. "WTL,WTL" "0,1" bitfld.long 0x28 15. "IWTL,IWTL" "0,1" bitfld.long 0x28 14. "ELCL,ELCL" "0,1" bitfld.long 0x28 13. "SE2L,SE2L" "0,1" bitfld.long 0x28 12. "SE1L,SE1L" "0,1" bitfld.long 0x28 11. "TXOL,TXOL" "0,1" newline bitfld.long 0x28 10. "TXUL,TXUL" "0,1" bitfld.long 0x28 9. "GTEL,GTEL" "0,1" bitfld.long 0x28 8. "GTDL,GTDL" "0,1" bitfld.long 0x28 7. "GTWL,GTWL" "0,1" bitfld.long 0x28 6. "SWEL,SWEL" "0,1" bitfld.long 0x28 5. "TTMIL,TTMIL" "0,1" bitfld.long 0x28 4. "RTMIL,RTMIL" "0,1" bitfld.long 0x28 3. "SOGL,SOGL" "0,1" newline bitfld.long 0x28 2. "CSML,CSML" "0,1" bitfld.long 0x28 1. "SMCL,SMCL" "0,1" bitfld.long 0x28 0. "SBCL,SBCL" "0,1" rgroup.long 0x12C++0x17 line.long 0x0 "FDCAN_TTOST,FDCAN TT operation status register" bitfld.long 0x0 31. "SPL,SPL" "0,1" bitfld.long 0x0 30. "WECS,WECS" "0,1" bitfld.long 0x0 29. "AWE,AWE" "0,1" bitfld.long 0x0 28. "WFE,WFE" "0,1" bitfld.long 0x0 27. "GSI,GSI" "0,1" bitfld.long 0x0 24.--26. "TMP,TMP" "0,1,2,3,4,5,6,7" bitfld.long 0x0 23. "GFI,GFI" "0,1" bitfld.long 0x0 22. "WGTD,WGTD" "0,1" newline hexmask.long.byte 0x0 8.--15. 1. "RTO,RTO" bitfld.long 0x0 7. "QCS,QCS" "0,1" bitfld.long 0x0 6. "QGTP,QGTP" "0,1" bitfld.long 0x0 4.--5. "SYS,SYS" "0,1,2,3" bitfld.long 0x0 2.--3. "MS,MS" "0,1,2,3" bitfld.long 0x0 0.--1. "EL,EL" "0,1,2,3" line.long 0x4 "FDCAN_TURNA,There is no drift compensation in TTCAN level 1." hexmask.long.tbyte 0x4 0.--17. 1. "NAV,NAV" line.long 0x8 "FDCAN_TTLGT,FDCAN TT local and global time register" hexmask.long.word 0x8 16.--31. 1. "GT,GT" hexmask.long.word 0x8 0.--15. 1. "LT,LT" line.long 0xC "FDCAN_TTCTC,FDCAN TT cycle time and count register" hexmask.long.byte 0xC 16.--21. 1. "CC,CC" hexmask.long.word 0xC 0.--15. 1. "CT,CT" line.long 0x10 "FDCAN_TTCPT,FDCAN TT capture time register" hexmask.long.word 0x10 16.--31. 1. "SWV,SWV" hexmask.long.byte 0x10 0.--5. 1. "CCV,CCV" line.long 0x14 "FDCAN_TTCSM,FDCAN TT cycle sync mark register" hexmask.long.word 0x14 0.--15. 1. "CSM,CSM" group.long 0x300++0x3 line.long 0x0 "FDCAN_TTTS,The settings in the FDCAN_TTTS register select the input to be used as event trigger and stop watch trigger." bitfld.long 0x0 4.--5. "EVTSEL,EVTSEL" "0,1,2,3" bitfld.long 0x0 0.--1. "SWTDEL,SWTDEL" "0,1,2,3" tree.end tree "FDCAN2" base ad:0x4400F000 rgroup.long 0x0++0x7 line.long 0x0 "FDCAN_CREL,FDCAN core release register" hexmask.long.byte 0x0 28.--31. 1. "REL,REL" hexmask.long.byte 0x0 24.--27. 1. "STEP,STEP" hexmask.long.byte 0x0 20.--23. 1. "SUBSTEP,SUBSTEP" hexmask.long.byte 0x0 16.--19. 1. "YEAR,YEAR" hexmask.long.byte 0x0 8.--15. 1. "MON,MON" hexmask.long.byte 0x0 0.--7. 1. "DAY,DAY" line.long 0x4 "FDCAN_ENDN,FDCAN Endian register" hexmask.long 0x4 0.--31. 1. "ETV,ETV" group.long 0xC++0x23 line.long 0x0 "FDCAN_DBTP,This register is dedicated to data bit timing phase and only writable if bits FDCAN_CCCR.CCE and FDCAN_CCCR.INIT are set. The CAN time quantum may be programmed in the range from 1 to 32 FDCAN clock periods. tq = (DBRP + 1) FDCAN clock.." bitfld.long 0x0 23. "TDC,TDC" "0,1" hexmask.long.byte 0x0 16.--20. 1. "DBRP,DBRP" hexmask.long.byte 0x0 8.--12. 1. "DTSEG1,DTSEG1" hexmask.long.byte 0x0 4.--7. 1. "DTSEG2,DTSEG2" hexmask.long.byte 0x0 0.--3. 1. "DSJW,DSJW" line.long 0x4 "FDCAN_TEST,Write access to this register has to be enabled by setting bit FDCAN_CCCR.TEST to 1. All register functions are set to their reset values when bit FDCAN_CCCR.TEST is reset. Loop back mode and software control of Tx pin FDCANx_TX are hardware.." rbitfld.long 0x4 7. "RX,RX" "0,1" bitfld.long 0x4 5.--6. "TX,TX" "0,1,2,3" bitfld.long 0x4 4. "LBCK,LBCK" "0,1" line.long 0x8 "FDCAN_RWD,The RAM watchdog monitors the READY output of the message RAM. A message RAM access starts the message RAM watchdog counter with the value configured by the FDCAN_RWD.WDC bits. The counter is reloaded with FDCAN_RWD.WDC bits when the message.." hexmask.long.byte 0x8 8.--15. 1. "WDV,WDV" hexmask.long.byte 0x8 0.--7. 1. "WDC,WDC" line.long 0xC "FDCAN_CCCR,For details about setting and resetting of single bits see Software initialization." bitfld.long 0xC 15. "NISO,NISO" "0,1" bitfld.long 0xC 14. "TXP,TXP" "0,1" bitfld.long 0xC 13. "EFBI,EFBI" "0,1" bitfld.long 0xC 12. "PXHD,PXHD" "0,1" bitfld.long 0xC 9. "BRSE,BRSE" "0,1" bitfld.long 0xC 8. "FDOE,FDOE" "0,1" bitfld.long 0xC 7. "TEST,TEST" "0,1" bitfld.long 0xC 6. "DAR,DAR" "0,1" newline bitfld.long 0xC 5. "MON,MON" "0,1" bitfld.long 0xC 4. "CSR,CSR" "0,1" rbitfld.long 0xC 3. "CSA,CSA" "0,1" bitfld.long 0xC 2. "ASM,ASM" "0,1" bitfld.long 0xC 1. "CCE,CCE" "0,1" bitfld.long 0xC 0. "INIT,INIT" "0,1" line.long 0x10 "FDCAN_NBTP,This register is dedicated to the nominal bit timing used during the arbitration phase." hexmask.long.byte 0x10 25.--31. 1. "NSJW,NSJW" hexmask.long.word 0x10 16.--24. 1. "NBRP,NBRP" hexmask.long.byte 0x10 8.--15. 1. "NTSEG1,NTSEG1" hexmask.long.byte 0x10 0.--6. 1. "NTSEG2,NTSEG2" line.long 0x14 "FDCAN_TSCC,FDCAN timestamp counter configuration register" hexmask.long.byte 0x14 16.--19. 1. "TCP,TCP" bitfld.long 0x14 0.--1. "TSS,TSS" "0,1,2,3" line.long 0x18 "FDCAN_TSCV,FDCAN timestamp counter value register" hexmask.long.word 0x18 0.--15. 1. "TSC,TSC" line.long 0x1C "FDCAN_TOCC,FDCAN timeout counter configuration register" hexmask.long.word 0x1C 16.--31. 1. "TOP,TOP" bitfld.long 0x1C 1.--2. "TOS,TOS" "0,1,2,3" bitfld.long 0x1C 0. "ETOC,ETOC" "0,1" line.long 0x20 "FDCAN_TOCV,FDCAN timeout counter value register" hexmask.long.word 0x20 0.--15. 1. "TOC,TOC" group.long 0x40++0xB line.long 0x0 "FDCAN_ECR,FDCAN error counter register" hexmask.long.byte 0x0 16.--23. 1. "CEL,CEL" rbitfld.long 0x0 15. "RP,RP" "0,1" hexmask.long.byte 0x0 8.--14. 1. "TREC,TREC" hexmask.long.byte 0x0 0.--7. 1. "TEC,TEC" line.long 0x4 "FDCAN_PSR,FDCAN protocol status register" hexmask.long.byte 0x4 16.--22. 1. "TDCV,TDCV" bitfld.long 0x4 14. "PXE,PXE" "0,1" bitfld.long 0x4 13. "REDL,REDL" "0,1" bitfld.long 0x4 12. "RBRS,RBRS" "0,1" bitfld.long 0x4 11. "RESI,RESI" "0,1" rbitfld.long 0x4 8.--10. "DLEC,DLEC" "0,1,2,3,4,5,6,7" rbitfld.long 0x4 7. "BO,BO" "0,1" rbitfld.long 0x4 6. "EW,EW" "0,1" newline rbitfld.long 0x4 5. "EP,EP" "0,1" rbitfld.long 0x4 3.--4. "ACT,ACT" "0,1,2,3" rbitfld.long 0x4 0.--2. "LEC,LEC" "0,1,2,3,4,5,6,7" line.long 0x8 "FDCAN_TDCR,FDCAN transmitter delay compensation register" hexmask.long.byte 0x8 8.--14. 1. "TDCO,TDCO" hexmask.long.byte 0x8 0.--6. 1. "TDCF,TDCF" group.long 0x50++0xF line.long 0x0 "FDCAN_IR,The flags are set when one of the listed conditions is detected (edge-sensitive). The flags remain set until the Host clears them. A flag is cleared by writing a 1 to the corresponding bit position. Writing a 0 has no effect. A hard reset will.." bitfld.long 0x0 29. "ARA,ARA" "0,1" bitfld.long 0x0 28. "PED,PED" "0,1" bitfld.long 0x0 27. "PEA,PEA" "0,1" bitfld.long 0x0 26. "WDI,WDI" "0,1" bitfld.long 0x0 25. "BO,BO" "0,1" bitfld.long 0x0 24. "EW,EW" "0,1" bitfld.long 0x0 23. "EP,EP" "0,1" bitfld.long 0x0 22. "ELO,ELO" "0,1" newline bitfld.long 0x0 19. "DRX,DRX" "0,1" bitfld.long 0x0 18. "TOO,TOO" "0,1" bitfld.long 0x0 17. "MRAF,MRAF" "0,1" bitfld.long 0x0 16. "TSW,TSW" "0,1" bitfld.long 0x0 15. "TEFL,TEFL" "0,1" bitfld.long 0x0 14. "TEFF,TEFF" "0,1" bitfld.long 0x0 13. "TEFW,TEFW" "0,1" bitfld.long 0x0 12. "TEFN,TEFN" "0,1" newline bitfld.long 0x0 11. "TFE,TFE" "0,1" bitfld.long 0x0 10. "TCF,TCF" "0,1" bitfld.long 0x0 9. "TC,TC" "0,1" bitfld.long 0x0 8. "HPM,HPM" "0,1" bitfld.long 0x0 7. "RF1L,RF1L" "0,1" bitfld.long 0x0 6. "RF1F,RF1F" "0,1" bitfld.long 0x0 5. "RF1W,RF1W" "0,1" bitfld.long 0x0 4. "RF1N,RF1N" "0,1" newline bitfld.long 0x0 3. "RF0L,RF0L" "0,1" bitfld.long 0x0 2. "RF0F,RF0F" "0,1" bitfld.long 0x0 1. "RF0W,RF0W" "0,1" bitfld.long 0x0 0. "RF0N,RF0N" "0,1" line.long 0x4 "FDCAN_IE,The settings in the interrupt enable register determine which status changes in the interrupt register will be signaled on an interrupt line." bitfld.long 0x4 29. "ARAE,ARAE" "0,1" bitfld.long 0x4 28. "PEDE,PEDE" "0,1" bitfld.long 0x4 27. "PEAE,PEAE" "0,1" bitfld.long 0x4 26. "WDIE,WDIE" "0,1" bitfld.long 0x4 25. "BOE,BOE" "0,1" bitfld.long 0x4 24. "EWE,EWE" "0,1" bitfld.long 0x4 23. "EPE,EPE" "0,1" bitfld.long 0x4 22. "ELOE,ELOE" "0,1" newline bitfld.long 0x4 21. "BEUE,BEUE" "0,1" bitfld.long 0x4 20. "BECE,BECE" "0,1" bitfld.long 0x4 19. "DRXE,DRXE" "0,1" bitfld.long 0x4 18. "TOOE,TOOE" "0,1" bitfld.long 0x4 17. "MRAFE,MRAFE" "0,1" bitfld.long 0x4 16. "TSWE,TSWE" "0,1" bitfld.long 0x4 15. "TEFLE,TEFLE" "0,1" bitfld.long 0x4 14. "TEFFE,TEFFE" "0,1" newline bitfld.long 0x4 13. "TEFWE,TEFWE" "0,1" bitfld.long 0x4 12. "TEFNE,TEFNE" "0,1" bitfld.long 0x4 11. "TFEE,TFEE" "0,1" bitfld.long 0x4 10. "TCFE,TCFE" "0,1" bitfld.long 0x4 9. "TCE,TCE" "0,1" bitfld.long 0x4 8. "HPME,HPME" "0,1" bitfld.long 0x4 7. "RF1LE,RF1LE" "0,1" bitfld.long 0x4 6. "RF1FE,RF1FE" "0,1" newline bitfld.long 0x4 5. "RF1WE,RF1WE" "0,1" bitfld.long 0x4 4. "RF1NE,RF1NE" "0,1" bitfld.long 0x4 3. "RF0LE,RF0LE" "0,1" bitfld.long 0x4 2. "RF0FE,RF0FE" "0,1" bitfld.long 0x4 1. "RF0WE,RF0WE" "0,1" bitfld.long 0x4 0. "RF0NE,RF0NE" "0,1" line.long 0x8 "FDCAN_ILS,This register assigns an interrupt generated by a specific interrupt flag from the interrupt register to one of the two module interrupt lines. For interrupt generation the respective interrupt line has to be enabled via FDCAN_ILE.EINT0 and.." bitfld.long 0x8 29. "ARAL,ARAL" "0,1" bitfld.long 0x8 28. "PEDL,PEDL" "0,1" bitfld.long 0x8 27. "PEAL,PEAL" "0,1" bitfld.long 0x8 26. "WDIL,WDIL" "0,1" bitfld.long 0x8 25. "BOL,BOL" "0,1" bitfld.long 0x8 24. "EWL,EWL" "0,1" bitfld.long 0x8 23. "EPL,EPL" "0,1" bitfld.long 0x8 22. "ELOL,ELOL" "0,1" newline bitfld.long 0x8 21. "BEUL,BEUL" "0,1" bitfld.long 0x8 20. "BECL,BECL" "0,1" bitfld.long 0x8 19. "DRXL,DRXL" "0,1" bitfld.long 0x8 18. "TOOL,TOOL" "0,1" bitfld.long 0x8 17. "MRAFL,MRAFL" "0,1" bitfld.long 0x8 16. "TSWL,TSWL" "0,1" bitfld.long 0x8 15. "TEFLL,TEFLL" "0,1" bitfld.long 0x8 14. "TEFFL,TEFFL" "0,1" newline bitfld.long 0x8 13. "TEFWL,TEFWL" "0,1" bitfld.long 0x8 12. "TEFNL,TEFNL" "0,1" bitfld.long 0x8 11. "TFEL,TFEL" "0,1" bitfld.long 0x8 10. "TCFL,TCFL" "0,1" bitfld.long 0x8 9. "TCL,TCL" "0,1" bitfld.long 0x8 8. "HPML,HPML" "0,1" bitfld.long 0x8 7. "RF1LL,RF1LL" "0,1" bitfld.long 0x8 6. "RF1FL,RF1FL" "0,1" newline bitfld.long 0x8 5. "RF1WL,RF1WL" "0,1" bitfld.long 0x8 4. "RF1NL,RF1NL" "0,1" bitfld.long 0x8 3. "RF0LL,RF0LL" "0,1" bitfld.long 0x8 2. "RF0FL,RF0FL" "0,1" bitfld.long 0x8 1. "RF0WL,RF0WL" "0,1" bitfld.long 0x8 0. "RF0NL,RF0NL" "0,1" line.long 0xC "FDCAN_ILE,Each of the two interrupt lines to the CPU can be enabled/disabled separately by programming bits EINT0 and EINT1." bitfld.long 0xC 1. "EINT1,EINT1" "0,1" bitfld.long 0xC 0. "EINT0,EINT0" "0,1" group.long 0x80++0xB line.long 0x0 "FDCAN_GFC,Global settings for message ID filtering. The global filter configuration register controls the filter path for standard and extended messages as described in Figure708: Standard message ID filter path and Figure709: Extended message ID filter.." bitfld.long 0x0 4.--5. "ANFS,ANFS" "0,1,2,3" bitfld.long 0x0 2.--3. "ANFE,ANFE" "0,1,2,3" bitfld.long 0x0 1. "RRFS,RRFS" "0,1" bitfld.long 0x0 0. "RRFE,RRFE" "0,1" line.long 0x4 "FDCAN_SIDFC,Settings for 11-bit standard message ID filtering.The standard ID filter configuration register controls the filter path for standard messages as described in Figure708." hexmask.long.byte 0x4 16.--23. 1. "LSS,LSS" hexmask.long.word 0x4 2.--15. 1. "FLSSA,FLSSA" line.long 0x8 "FDCAN_XIDFC,Settings for 29-bit extended message ID filtering. The FDCAN extended ID filter configuration register controls the filter path for standard messages as described in Figure709: Extended message ID filter path." hexmask.long.byte 0x8 16.--23. 1. "LSE,LSE" hexmask.long.word 0x8 2.--15. 1. "FLESA,FLESA" group.long 0x90++0x3 line.long 0x0 "FDCAN_XIDAM,FDCAN extended ID and mask register" hexmask.long 0x0 0.--28. 1. "EIDM,EIDM" rgroup.long 0x94++0x3 line.long 0x0 "FDCAN_HPMS,This register is updated every time a message ID filter element configured to generate a priority event match. This can be used to monitor the status of incoming high priority messages and to enable fast access to these messages." bitfld.long 0x0 15. "FLST,FLST" "0,1" hexmask.long.byte 0x0 8.--14. 1. "FIDX,FIDX" bitfld.long 0x0 6.--7. "MSI,MSI" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "BIDX,BIDX" group.long 0x98++0x1B line.long 0x0 "FDCAN_NDAT1,FDCAN new data 1 register" bitfld.long 0x0 31. "ND31,ND31" "0,1" bitfld.long 0x0 30. "ND30,ND30" "0,1" bitfld.long 0x0 29. "ND29,ND29" "0,1" bitfld.long 0x0 28. "ND28,ND28" "0,1" bitfld.long 0x0 27. "ND27,ND27" "0,1" bitfld.long 0x0 26. "ND26,ND26" "0,1" bitfld.long 0x0 25. "ND25,ND25" "0,1" bitfld.long 0x0 24. "ND24,ND24" "0,1" newline bitfld.long 0x0 23. "ND23,ND23" "0,1" bitfld.long 0x0 22. "ND22,ND22" "0,1" bitfld.long 0x0 21. "ND21,ND21" "0,1" bitfld.long 0x0 20. "ND20,ND20" "0,1" bitfld.long 0x0 19. "ND19,ND19" "0,1" bitfld.long 0x0 18. "ND18,ND18" "0,1" bitfld.long 0x0 17. "ND17,ND17" "0,1" bitfld.long 0x0 16. "ND16,ND16" "0,1" newline bitfld.long 0x0 15. "ND15,ND15" "0,1" bitfld.long 0x0 14. "ND14,ND14" "0,1" bitfld.long 0x0 13. "ND13,ND13" "0,1" bitfld.long 0x0 12. "ND12,ND12" "0,1" bitfld.long 0x0 11. "ND11,ND11" "0,1" bitfld.long 0x0 10. "ND10,ND10" "0,1" bitfld.long 0x0 9. "ND9,ND9" "0,1" bitfld.long 0x0 8. "ND8,ND8" "0,1" newline bitfld.long 0x0 7. "ND7,ND7" "0,1" bitfld.long 0x0 6. "ND6,ND6" "0,1" bitfld.long 0x0 5. "ND5,ND5" "0,1" bitfld.long 0x0 4. "ND4,ND4" "0,1" bitfld.long 0x0 3. "ND3,ND3" "0,1" bitfld.long 0x0 2. "ND2,ND2" "0,1" bitfld.long 0x0 1. "ND1,ND1" "0,1" bitfld.long 0x0 0. "ND0,ND0" "0,1" line.long 0x4 "FDCAN_NDAT2,FDCAN new data 2 register" bitfld.long 0x4 31. "ND63,ND63" "0,1" bitfld.long 0x4 30. "ND62,ND62" "0,1" bitfld.long 0x4 29. "ND61,ND61" "0,1" bitfld.long 0x4 28. "ND60,ND60" "0,1" bitfld.long 0x4 27. "ND59,ND59" "0,1" bitfld.long 0x4 26. "ND58,ND58" "0,1" bitfld.long 0x4 25. "ND57,ND57" "0,1" bitfld.long 0x4 24. "ND56,ND56" "0,1" newline bitfld.long 0x4 23. "ND55,ND55" "0,1" bitfld.long 0x4 22. "ND54,ND54" "0,1" bitfld.long 0x4 21. "ND53,ND53" "0,1" bitfld.long 0x4 20. "ND52,ND52" "0,1" bitfld.long 0x4 19. "ND51,ND51" "0,1" bitfld.long 0x4 18. "ND50,ND50" "0,1" bitfld.long 0x4 17. "ND49,ND49" "0,1" bitfld.long 0x4 16. "ND48,ND48" "0,1" newline bitfld.long 0x4 15. "ND47,ND47" "0,1" bitfld.long 0x4 14. "ND46,ND46" "0,1" bitfld.long 0x4 13. "ND45,ND45" "0,1" bitfld.long 0x4 12. "ND44,ND44" "0,1" bitfld.long 0x4 11. "ND43,ND43" "0,1" bitfld.long 0x4 10. "ND42,ND42" "0,1" bitfld.long 0x4 9. "ND41,ND41" "0,1" bitfld.long 0x4 8. "ND40,ND40" "0,1" newline bitfld.long 0x4 7. "ND39,ND39" "0,1" bitfld.long 0x4 6. "ND38,ND38" "0,1" bitfld.long 0x4 5. "ND37,ND37" "0,1" bitfld.long 0x4 4. "ND36,ND36" "0,1" bitfld.long 0x4 3. "ND35,ND35" "0,1" bitfld.long 0x4 2. "ND34,ND34" "0,1" bitfld.long 0x4 1. "ND33,ND33" "0,1" bitfld.long 0x4 0. "ND32,ND32" "0,1" line.long 0x8 "FDCAN_RXF0C,FDCAN Rx FIFO 0 configuration register" bitfld.long 0x8 31. "F0OM,F0OM" "0,1" hexmask.long.byte 0x8 24.--30. 1. "F0WM,F0WM" hexmask.long.byte 0x8 16.--22. 1. "F0S,F0S" hexmask.long.word 0x8 2.--15. 1. "F0SA,F0SA" line.long 0xC "FDCAN_RXF0S,FDCAN Rx FIFO 0 status register" bitfld.long 0xC 25. "RF0L,RF0L" "0,1" bitfld.long 0xC 24. "F0F,F0F" "0,1" hexmask.long.byte 0xC 16.--21. 1. "F0PI,F0PI" hexmask.long.byte 0xC 8.--13. 1. "F0GI,F0GI" hexmask.long.byte 0xC 0.--6. 1. "F0FL,F0FL" line.long 0x10 "FDCAN_RXF0A,FDCAN Rx FIFO 0 acknowledge register" hexmask.long.byte 0x10 0.--5. 1. "F0AI,F0AI" line.long 0x14 "FDCAN_RXBC,FDCAN Rx buffer configuration register" hexmask.long.word 0x14 2.--15. 1. "RBSA,RBSA" line.long 0x18 "FDCAN_RXF1C,FDCAN Rx FIFO 1 configuration register" bitfld.long 0x18 31. "F1OM,F1OM" "0,1" hexmask.long.byte 0x18 24.--30. 1. "F1WM,F1WM" hexmask.long.byte 0x18 16.--22. 1. "F1S,F1S" hexmask.long.word 0x18 2.--15. 1. "F1SA,F1SA" rgroup.long 0xB4++0x3 line.long 0x0 "FDCAN_RXF1S,FDCAN Rx FIFO 1 status register" bitfld.long 0x0 30.--31. "DMS,DMS" "0,1,2,3" bitfld.long 0x0 25. "RF1L,RF1L" "0,1" bitfld.long 0x0 24. "F1F,F1F" "0,1" hexmask.long.byte 0x0 16.--21. 1. "F1PI,F1PI" hexmask.long.byte 0x0 8.--13. 1. "F1GI,F1GI" hexmask.long.byte 0x0 0.--6. 1. "F1FL,F1FL" group.long 0xB8++0x3 line.long 0x0 "FDCAN_RXF1A,FDCAN Rx FIFO 1 acknowledge register" hexmask.long.byte 0x0 0.--5. 1. "F1AI,F1AI" rgroup.long 0xBC++0x3 line.long 0x0 "FDCAN_RXESC,Configures the number of data bytes belonging to an Rx buffer / Rx FIFO element. Data field sizes higher than 8 bytes are intended for CAN FD operation only." bitfld.long 0x0 8.--10. "RBDS,RBDS" "0,1,2,3,4,5,6,7" bitfld.long 0x0 4.--6. "F1DS,F1DS" "0,1,2,3,4,5,6,7" bitfld.long 0x0 0.--2. "F0DS,F0DS" "0,1,2,3,4,5,6,7" group.long 0xC0++0x3 line.long 0x0 "FDCAN_TXBC,FDCAN Tx buffer configuration register" bitfld.long 0x0 30. "TFQM,TFQM" "0,1" hexmask.long.byte 0x0 24.--29. 1. "TFQS,TFQS" hexmask.long.byte 0x0 16.--21. 1. "NDTB,NDTB" hexmask.long.word 0x0 2.--15. 1. "TBSA,TBSA" rgroup.long 0xC4++0x7 line.long 0x0 "FDCAN_TXFQS,The Tx FIFO/queue status is related to the pending Tx requests listed in register FDCAN_TXBRP. Therefore the effect of add/cancellation requests may be delayed due to a running Tx scan (FDCAN_TXBRP not yet updated)." bitfld.long 0x0 21. "TFQF,TFQF" "0,1" hexmask.long.byte 0x0 16.--20. 1. "TFQPI,TFQPI" hexmask.long.byte 0x0 8.--12. 1. "TFGI,TFGI" hexmask.long.byte 0x0 0.--5. 1. "TFFL,TFFL" line.long 0x4 "FDCAN_TXESC,Configures the number of data bytes belonging to a Tx buffer element. Data field sizes >8 bytes are intended for CAN FD operation only." bitfld.long 0x4 0.--2. "TBDS,TBDS" "0,1,2,3,4,5,6,7" group.long 0xD0++0x7 line.long 0x0 "FDCAN_TXBAR,FDCAN Tx buffer add request register" hexmask.long 0x0 0.--31. 1. "AR,AR" line.long 0x4 "FDCAN_TXBCR,FDCAN Tx buffer cancellation request register" hexmask.long 0x4 0.--31. 1. "CR,CR" rgroup.long 0xD8++0x7 line.long 0x0 "FDCAN_TXBTO,FDCAN Tx buffer transmission occurred register" hexmask.long 0x0 0.--31. 1. "TO,TO" line.long 0x4 "FDCAN_TXBCF,FDCAN Tx buffer cancellation finished register" hexmask.long 0x4 0.--31. 1. "CF,CF" group.long 0xE0++0x7 line.long 0x0 "FDCAN_TXBTIE,FDCAN Tx buffer transmission interrupt enable register" hexmask.long 0x0 0.--31. 1. "TIE,TIE" line.long 0x4 "FDCAN_TXBCIE,FDCAN Tx buffer cancellation finished interrupt enable register" hexmask.long 0x4 0.--31. 1. "CFIE,CFIE" group.long 0xF0++0x3 line.long 0x0 "FDCAN_TXEFC,FDCAN Tx event FIFO configuration register" hexmask.long.byte 0x0 24.--29. 1. "EFWM,EFWM" hexmask.long.byte 0x0 16.--21. 1. "EFS,EFS" hexmask.long.word 0x0 2.--15. 1. "EFSA,EFSA" rgroup.long 0xF4++0x3 line.long 0x0 "FDCAN_TXEFS,FDCAN Tx event FIFO status register" bitfld.long 0x0 25. "TEFL,TEFL" "0,1" bitfld.long 0x0 24. "EFF,EFF" "0,1" hexmask.long.byte 0x0 16.--20. 1. "EFPI,EFPI" hexmask.long.byte 0x0 8.--12. 1. "EFGI,EFGI" hexmask.long.byte 0x0 0.--5. 1. "EFFL,EFFL" group.long 0xF8++0x3 line.long 0x0 "FDCAN_TXEFA,FDCAN Tx event FIFO acknowledge register" hexmask.long.byte 0x0 0.--4. 1. "EFAI,EFAI" group.long 0x100++0x2B line.long 0x0 "FDCAN_TTTMC,FDCAN TT trigger memory configuration register" hexmask.long.byte 0x0 16.--22. 1. "TME,TME" hexmask.long.word 0x0 2.--15. 1. "TMSA,TMSA" line.long 0x4 "FDCAN_TTRMC,FDCAN TT reference message configuration register" bitfld.long 0x4 31. "RMPS,RMPS" "0,1" bitfld.long 0x4 30. "XTD,XTD" "0,1" hexmask.long 0x4 0.--28. 1. "RID,RID" line.long 0x8 "FDCAN_TTOCF,FDCAN TT operation configuration register" bitfld.long 0x8 26. "EVTP,EVTP" "0,1" bitfld.long 0x8 25. "ECC,ECC" "0,1" bitfld.long 0x8 24. "EGTF,EGTF" "0,1" hexmask.long.byte 0x8 16.--23. 1. "AWL,AWL" bitfld.long 0x8 15. "EECS,EECS" "0,1" hexmask.long.byte 0x8 8.--14. 1. "IRTO,IRTO" bitfld.long 0x8 5.--7. "LDSDL,LDSDL" "0,1,2,3,4,5,6,7" bitfld.long 0x8 4. "TM,TM" "0,1" newline bitfld.long 0x8 3. "GEN,GEN" "0,1" bitfld.long 0x8 0.--1. "OM,OM" "0,1,2,3" line.long 0xC "FDCAN_TTMLM,FDCAN TT matrix limits register" hexmask.long.word 0xC 16.--27. 1. "ENTT,ENTT" hexmask.long.byte 0xC 8.--11. 1. "TXEW,TXEW" bitfld.long 0xC 6.--7. "CSS,CSS" "0,1,2,3" hexmask.long.byte 0xC 0.--5. 1. "CCM,CCM" line.long 0x10 "FDCAN_TURCF,The length of the NTU is given by: NTU = CAN clock period x NC/DC. NC is an 18-bit value. Its high part. NCH[17:16] is hard wired to 0b01. Therefore the range of NC extends from 0x10000 to 0x1FFFF. The value configured by NCL is the initial.." bitfld.long 0x10 31. "ELT,ELT" "0,1" hexmask.long.word 0x10 16.--29. 1. "DC,DC" hexmask.long.word 0x10 0.--15. 1. "NCL,NCL" line.long 0x14 "FDCAN_TTOCN,FDCAN TT operation control register" rbitfld.long 0x14 15. "LCKC,LCKC" "0,1" bitfld.long 0x14 13. "ESCN,ESCN" "0,1" bitfld.long 0x14 12. "NIG,NIG" "0,1" bitfld.long 0x14 11. "TMG,TMG" "0,1" bitfld.long 0x14 10. "FGP,FGP" "0,1" bitfld.long 0x14 9. "GCS,GCS" "0,1" bitfld.long 0x14 8. "TTIE,TTIE" "0,1" bitfld.long 0x14 6.--7. "TMC,TMC" "0,1,2,3" newline bitfld.long 0x14 5. "RTIE,RTIE" "0,1" bitfld.long 0x14 3.--4. "SWS,SWS" "0,1,2,3" bitfld.long 0x14 2. "SWP,SWP" "0,1" bitfld.long 0x14 1. "ECS,ECS" "0,1" bitfld.long 0x14 0. "SGT,SGT" "0,1" line.long 0x18 "FDCAN_TTGTP,If TTOST.WGDT is set. the next reference message will be transmitted with the Master_Ref_Mark modified by the preset value and with Disc_Bit = 1. presetting the global time in all nodes simultaneously. TP is reset to 0x0000 each time a.." hexmask.long.word 0x18 16.--31. 1. "CTP,CTP" hexmask.long.word 0x18 0.--15. 1. "TP,TP" line.long 0x1C "FDCAN_TTTMK,A time mark interrupt (FDCAN_TTIR.TMI = 1) is generated when the time base indicated by FDCAN_TTOCN.TMC (cycle time. local time. or global time) has the same value as TM." rbitfld.long 0x1C 31. "LCKM,LCKM" "0,1" hexmask.long.byte 0x1C 16.--22. 1. "TICC,TICC" hexmask.long.word 0x1C 0.--15. 1. "TM,TM" line.long 0x20 "FDCAN_TTIR,The flags are set when one of the listed conditions is detected (edge-sensitive). The flags remain set until the Host clears them. A flag is cleared by writing a 1 to the corresponding bit position. Writing a 0 has no effect. A hard reset will.." bitfld.long 0x20 18. "CER,CER" "0,1" bitfld.long 0x20 17. "AW,AW" "0,1" bitfld.long 0x20 16. "WT,WT" "0,1" bitfld.long 0x20 15. "IWTG,IWTG" "0,1" bitfld.long 0x20 14. "ELC,ELC" "0,1" bitfld.long 0x20 13. "SE2,SE2" "0,1" bitfld.long 0x20 12. "SE1,SE1" "0,1" bitfld.long 0x20 11. "TXO,TXO" "0,1" newline bitfld.long 0x20 10. "TXU,TXU" "0,1" bitfld.long 0x20 9. "GTE,GTE" "0,1" bitfld.long 0x20 8. "GTD,GTD" "0,1" bitfld.long 0x20 7. "GTW,GTW" "0,1" bitfld.long 0x20 6. "SWE,SWE" "0,1" bitfld.long 0x20 5. "TTMI,TTMI" "0,1" bitfld.long 0x20 4. "RTMI,RTMI" "0,1" bitfld.long 0x20 3. "SOG,SOG" "0,1" newline bitfld.long 0x20 2. "CSM,CSM" "0,1" bitfld.long 0x20 1. "SMC,SMC" "0,1" bitfld.long 0x20 0. "SBC,SBC" "0,1" line.long 0x24 "FDCAN_TTIE,The settings in the TT interrupt enable register determine which status changes in the TT interrupt register will result in an interrupt." bitfld.long 0x24 18. "CERE,CERE" "0,1" bitfld.long 0x24 17. "AWE,AWE" "0,1" bitfld.long 0x24 16. "WTE,WTE" "0,1" bitfld.long 0x24 15. "IWTE,IWTE" "0,1" bitfld.long 0x24 14. "ELCE,ELCE" "0,1" bitfld.long 0x24 13. "SE2E,SE2E" "0,1" bitfld.long 0x24 12. "SE1E,SE1E" "0,1" bitfld.long 0x24 11. "TXOE,TXOE" "0,1" newline bitfld.long 0x24 10. "TXUE,TXUE" "0,1" bitfld.long 0x24 9. "GTEE,GTEE" "0,1" bitfld.long 0x24 8. "GTDE,GTDE" "0,1" bitfld.long 0x24 7. "GTWE,GTWE" "0,1" bitfld.long 0x24 6. "SWEE,SWEE" "0,1" bitfld.long 0x24 5. "TTMIE,TTMIE" "0,1" bitfld.long 0x24 4. "RTMIE,RTMIE" "0,1" bitfld.long 0x24 3. "SOGE,SOGE" "0,1" newline bitfld.long 0x24 2. "CSME,CSME" "0,1" bitfld.long 0x24 1. "SMCE,SMCE" "0,1" bitfld.long 0x24 0. "SBCE,SBCE" "0,1" line.long 0x28 "FDCAN_TTILS,The TT interrupt Line select register assigns an interrupt generated by a specific interrupt flag from the TT interrupt register to one of the two module interrupt lines. For interrupt generation the respective interrupt line has to be.." bitfld.long 0x28 18. "CERL,CERL" "0,1" bitfld.long 0x28 17. "AWL,AWL" "0,1" bitfld.long 0x28 16. "WTL,WTL" "0,1" bitfld.long 0x28 15. "IWTL,IWTL" "0,1" bitfld.long 0x28 14. "ELCL,ELCL" "0,1" bitfld.long 0x28 13. "SE2L,SE2L" "0,1" bitfld.long 0x28 12. "SE1L,SE1L" "0,1" bitfld.long 0x28 11. "TXOL,TXOL" "0,1" newline bitfld.long 0x28 10. "TXUL,TXUL" "0,1" bitfld.long 0x28 9. "GTEL,GTEL" "0,1" bitfld.long 0x28 8. "GTDL,GTDL" "0,1" bitfld.long 0x28 7. "GTWL,GTWL" "0,1" bitfld.long 0x28 6. "SWEL,SWEL" "0,1" bitfld.long 0x28 5. "TTMIL,TTMIL" "0,1" bitfld.long 0x28 4. "RTMIL,RTMIL" "0,1" bitfld.long 0x28 3. "SOGL,SOGL" "0,1" newline bitfld.long 0x28 2. "CSML,CSML" "0,1" bitfld.long 0x28 1. "SMCL,SMCL" "0,1" bitfld.long 0x28 0. "SBCL,SBCL" "0,1" rgroup.long 0x12C++0x17 line.long 0x0 "FDCAN_TTOST,FDCAN TT operation status register" bitfld.long 0x0 31. "SPL,SPL" "0,1" bitfld.long 0x0 30. "WECS,WECS" "0,1" bitfld.long 0x0 29. "AWE,AWE" "0,1" bitfld.long 0x0 28. "WFE,WFE" "0,1" bitfld.long 0x0 27. "GSI,GSI" "0,1" bitfld.long 0x0 24.--26. "TMP,TMP" "0,1,2,3,4,5,6,7" bitfld.long 0x0 23. "GFI,GFI" "0,1" bitfld.long 0x0 22. "WGTD,WGTD" "0,1" newline hexmask.long.byte 0x0 8.--15. 1. "RTO,RTO" bitfld.long 0x0 7. "QCS,QCS" "0,1" bitfld.long 0x0 6. "QGTP,QGTP" "0,1" bitfld.long 0x0 4.--5. "SYS,SYS" "0,1,2,3" bitfld.long 0x0 2.--3. "MS,MS" "0,1,2,3" bitfld.long 0x0 0.--1. "EL,EL" "0,1,2,3" line.long 0x4 "FDCAN_TURNA,There is no drift compensation in TTCAN level 1." hexmask.long.tbyte 0x4 0.--17. 1. "NAV,NAV" line.long 0x8 "FDCAN_TTLGT,FDCAN TT local and global time register" hexmask.long.word 0x8 16.--31. 1. "GT,GT" hexmask.long.word 0x8 0.--15. 1. "LT,LT" line.long 0xC "FDCAN_TTCTC,FDCAN TT cycle time and count register" hexmask.long.byte 0xC 16.--21. 1. "CC,CC" hexmask.long.word 0xC 0.--15. 1. "CT,CT" line.long 0x10 "FDCAN_TTCPT,FDCAN TT capture time register" hexmask.long.word 0x10 16.--31. 1. "SWV,SWV" hexmask.long.byte 0x10 0.--5. 1. "CCV,CCV" line.long 0x14 "FDCAN_TTCSM,FDCAN TT cycle sync mark register" hexmask.long.word 0x14 0.--15. 1. "CSM,CSM" group.long 0x300++0x3 line.long 0x0 "FDCAN_TTTS,The settings in the FDCAN_TTTS register select the input to be used as event trigger and stop watch trigger." bitfld.long 0x0 4.--5. "EVTSEL,EVTSEL" "0,1,2,3" bitfld.long 0x0 0.--1. "SWTDEL,SWTDEL" "0,1,2,3" tree.end tree.end endif tree "FMC (Flexible Memory Controller)" base ad:0x58002000 group.long 0x0++0x23 line.long 0x0 "FMC_BCR1,This register contains the control information of each memory bank. used for SRAMs. PSRAM. FRAM and NOR Flash memories." bitfld.long 0x0 31. "FMCEN,FMCEN" "0,1" bitfld.long 0x0 22.--23. "NBLSET,NBLSET" "0,1,2,3" bitfld.long 0x0 20. "CCLKEN,CCLKEN" "0,1" bitfld.long 0x0 19. "CBURSTRW,CBURSTRW" "0,1" bitfld.long 0x0 16.--18. "CPSIZE,CPSIZE" "0,1,2,3,4,5,6,7" bitfld.long 0x0 15. "ASYNCWAIT,ASYNCWAIT" "0,1" newline bitfld.long 0x0 14. "EXTMOD,EXTMOD" "0,1" bitfld.long 0x0 13. "WAITEN,WAITEN" "0,1" bitfld.long 0x0 12. "WREN,WREN" "0,1" bitfld.long 0x0 11. "WAITCFG,WAITCFG" "0,1" bitfld.long 0x0 9. "WAITPOL,WAITPOL" "0,1" bitfld.long 0x0 8. "BURSTEN,BURSTEN" "0,1" newline bitfld.long 0x0 6. "FACCEN,FACCEN" "0,1" bitfld.long 0x0 4.--5. "MWID,MWID" "0,1,2,3" bitfld.long 0x0 2.--3. "MTYP,MTYP" "0,1,2,3" bitfld.long 0x0 1. "MUXEN,MUXEN" "0,1" bitfld.long 0x0 0. "MBKEN,MBKEN" "0,1" line.long 0x4 "FMC_BTR1,This register contains the control information of each memory bank. used for SRAMs. PSRAM and NOR Flash memories.If the EXTMOD bit is set in the FMC_BCRx register. then this register is partitioned for write and read access. that is. two.." bitfld.long 0x4 30.--31. "DATAHLD,DATAHLD" "0,1,2,3" bitfld.long 0x4 28.--29. "ACCMOD,ACCMOD" "0,1,2,3" hexmask.long.byte 0x4 24.--27. 1. "DATLAT,DATLAT" hexmask.long.byte 0x4 20.--23. 1. "CLKDIV,CLKDIV" hexmask.long.byte 0x4 16.--19. 1. "BUSTURN,BUSTURN" hexmask.long.byte 0x4 8.--15. 1. "DATAST,DATAST" newline hexmask.long.byte 0x4 4.--7. 1. "ADDHLD,ADDHLD" hexmask.long.byte 0x4 0.--3. 1. "ADDSET,ADDSET" line.long 0x8 "FMC_BCR2,This register contains the control information of each memory bank. used for SRAMs. PSRAM. FRAM and NOR Flash memories." bitfld.long 0x8 31. "FMCEN,FMCEN" "0,1" bitfld.long 0x8 22.--23. "NBLSET,NBLSET" "0,1,2,3" bitfld.long 0x8 20. "CCLKEN,CCLKEN" "0,1" bitfld.long 0x8 19. "CBURSTRW,CBURSTRW" "0,1" bitfld.long 0x8 16.--18. "CPSIZE,CPSIZE" "0,1,2,3,4,5,6,7" bitfld.long 0x8 15. "ASYNCWAIT,ASYNCWAIT" "0,1" newline bitfld.long 0x8 14. "EXTMOD,EXTMOD" "0,1" bitfld.long 0x8 13. "WAITEN,WAITEN" "0,1" bitfld.long 0x8 12. "WREN,WREN" "0,1" bitfld.long 0x8 11. "WAITCFG,WAITCFG" "0,1" bitfld.long 0x8 9. "WAITPOL,WAITPOL" "0,1" bitfld.long 0x8 8. "BURSTEN,BURSTEN" "0,1" newline bitfld.long 0x8 6. "FACCEN,FACCEN" "0,1" bitfld.long 0x8 4.--5. "MWID,MWID" "0,1,2,3" bitfld.long 0x8 2.--3. "MTYP,MTYP" "0,1,2,3" bitfld.long 0x8 1. "MUXEN,MUXEN" "0,1" bitfld.long 0x8 0. "MBKEN,MBKEN" "0,1" line.long 0xC "FMC_BTR2,This register contains the control information of each memory bank. used for SRAMs. PSRAM and NOR Flash memories.If the EXTMOD bit is set in the FMC_BCRx register. then this register is partitioned for write and read access. that is. two.." bitfld.long 0xC 30.--31. "DATAHLD,DATAHLD" "0,1,2,3" bitfld.long 0xC 28.--29. "ACCMOD,ACCMOD" "0,1,2,3" hexmask.long.byte 0xC 24.--27. 1. "DATLAT,DATLAT" hexmask.long.byte 0xC 20.--23. 1. "CLKDIV,CLKDIV" hexmask.long.byte 0xC 16.--19. 1. "BUSTURN,BUSTURN" hexmask.long.byte 0xC 8.--15. 1. "DATAST,DATAST" newline hexmask.long.byte 0xC 4.--7. 1. "ADDHLD,ADDHLD" hexmask.long.byte 0xC 0.--3. 1. "ADDSET,ADDSET" line.long 0x10 "FMC_BCR3,This register contains the control information of each memory bank. used for SRAMs. PSRAM. FRAM and NOR Flash memories." bitfld.long 0x10 31. "FMCEN,FMCEN" "0,1" bitfld.long 0x10 22.--23. "NBLSET,NBLSET" "0,1,2,3" bitfld.long 0x10 20. "CCLKEN,CCLKEN" "0,1" bitfld.long 0x10 19. "CBURSTRW,CBURSTRW" "0,1" bitfld.long 0x10 16.--18. "CPSIZE,CPSIZE" "0,1,2,3,4,5,6,7" bitfld.long 0x10 15. "ASYNCWAIT,ASYNCWAIT" "0,1" newline bitfld.long 0x10 14. "EXTMOD,EXTMOD" "0,1" bitfld.long 0x10 13. "WAITEN,WAITEN" "0,1" bitfld.long 0x10 12. "WREN,WREN" "0,1" bitfld.long 0x10 11. "WAITCFG,WAITCFG" "0,1" bitfld.long 0x10 9. "WAITPOL,WAITPOL" "0,1" bitfld.long 0x10 8. "BURSTEN,BURSTEN" "0,1" newline bitfld.long 0x10 6. "FACCEN,FACCEN" "0,1" bitfld.long 0x10 4.--5. "MWID,MWID" "0,1,2,3" bitfld.long 0x10 2.--3. "MTYP,MTYP" "0,1,2,3" bitfld.long 0x10 1. "MUXEN,MUXEN" "0,1" bitfld.long 0x10 0. "MBKEN,MBKEN" "0,1" line.long 0x14 "FMC_BTR3,This register contains the control information of each memory bank. used for SRAMs. PSRAM and NOR Flash memories.If the EXTMOD bit is set in the FMC_BCRx register. then this register is partitioned for write and read access. that is. two.." bitfld.long 0x14 30.--31. "DATAHLD,DATAHLD" "0,1,2,3" bitfld.long 0x14 28.--29. "ACCMOD,ACCMOD" "0,1,2,3" hexmask.long.byte 0x14 24.--27. 1. "DATLAT,DATLAT" hexmask.long.byte 0x14 20.--23. 1. "CLKDIV,CLKDIV" hexmask.long.byte 0x14 16.--19. 1. "BUSTURN,BUSTURN" hexmask.long.byte 0x14 8.--15. 1. "DATAST,DATAST" newline hexmask.long.byte 0x14 4.--7. 1. "ADDHLD,ADDHLD" hexmask.long.byte 0x14 0.--3. 1. "ADDSET,ADDSET" line.long 0x18 "FMC_BCR4,This register contains the control information of each memory bank. used for SRAMs. PSRAM. FRAM and NOR Flash memories." bitfld.long 0x18 31. "FMCEN,FMCEN" "0,1" bitfld.long 0x18 22.--23. "NBLSET,NBLSET" "0,1,2,3" bitfld.long 0x18 20. "CCLKEN,CCLKEN" "0,1" bitfld.long 0x18 19. "CBURSTRW,CBURSTRW" "0,1" bitfld.long 0x18 16.--18. "CPSIZE,CPSIZE" "0,1,2,3,4,5,6,7" bitfld.long 0x18 15. "ASYNCWAIT,ASYNCWAIT" "0,1" newline bitfld.long 0x18 14. "EXTMOD,EXTMOD" "0,1" bitfld.long 0x18 13. "WAITEN,WAITEN" "0,1" bitfld.long 0x18 12. "WREN,WREN" "0,1" bitfld.long 0x18 11. "WAITCFG,WAITCFG" "0,1" bitfld.long 0x18 9. "WAITPOL,WAITPOL" "0,1" bitfld.long 0x18 8. "BURSTEN,BURSTEN" "0,1" newline bitfld.long 0x18 6. "FACCEN,FACCEN" "0,1" bitfld.long 0x18 4.--5. "MWID,MWID" "0,1,2,3" bitfld.long 0x18 2.--3. "MTYP,MTYP" "0,1,2,3" bitfld.long 0x18 1. "MUXEN,MUXEN" "0,1" bitfld.long 0x18 0. "MBKEN,MBKEN" "0,1" line.long 0x1C "FMC_BTR4,This register contains the control information of each memory bank. used for SRAMs. PSRAM and NOR Flash memories.If the EXTMOD bit is set in the FMC_BCRx register. then this register is partitioned for write and read access. that is. two.." bitfld.long 0x1C 30.--31. "DATAHLD,DATAHLD" "0,1,2,3" bitfld.long 0x1C 28.--29. "ACCMOD,ACCMOD" "0,1,2,3" hexmask.long.byte 0x1C 24.--27. 1. "DATLAT,DATLAT" hexmask.long.byte 0x1C 20.--23. 1. "CLKDIV,CLKDIV" hexmask.long.byte 0x1C 16.--19. 1. "BUSTURN,BUSTURN" hexmask.long.byte 0x1C 8.--15. 1. "DATAST,DATAST" newline hexmask.long.byte 0x1C 4.--7. 1. "ADDHLD,ADDHLD" hexmask.long.byte 0x1C 0.--3. 1. "ADDSET,ADDSET" line.long 0x20 "FMC_PCSCNTR,This register contains the PSRAM chip select counter value for synchronous mode. The chip select counter is common to all banks and can be enabled separately on each bank. During PSRAM read or write accesses. this value is loaded into a timer.." bitfld.long 0x20 19. "CNTB4EN,CNTB4EN" "0,1" bitfld.long 0x20 18. "CNTB3EN,CNTB3EN" "0,1" bitfld.long 0x20 17. "CNTB2EN,CNTB2EN" "0,1" bitfld.long 0x20 16. "CNTB1EN,CNTB1EN" "0,1" hexmask.long.word 0x20 0.--15. 1. "CSCOUNT,CSCOUNT" group.long 0x80++0x3 line.long 0x0 "FMC_PCR,NAND Flash Programmable control register" bitfld.long 0x0 25. "WEN,WEN" "0,1" bitfld.long 0x0 24. "BCHECC,BCHECC" "0,1" hexmask.long.byte 0x0 20.--23. 1. "TCEH,TCEH" bitfld.long 0x0 17.--19. "ECCSS,ECCSS" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 13.--16. 1. "TAR,TAR" hexmask.long.byte 0x0 9.--12. 1. "TCLR,TCLR" newline bitfld.long 0x0 8. "ECCALG,ECCALG" "0,1" bitfld.long 0x0 6. "ECCEN,ECCEN" "0,1" bitfld.long 0x0 4.--5. "PWID,PWID" "0,1,2,3" bitfld.long 0x0 2. "PBKEN,PBKEN" "0,1" bitfld.long 0x0 1. "PWAITEN,PWAITEN" "0,1" rgroup.long 0x84++0x3 line.long 0x0 "FMC_SR,This register contains information about the AXI interface isolation status and the NAND write requests status. The FMC has to be disabled before modifying some registers. As requests might be pending. it is necessary to wait till the AXI.." bitfld.long 0x0 6. "NWRF,NWRF" "0,1" bitfld.long 0x0 4. "PEF,PEF" "0,1" bitfld.long 0x0 0.--1. "ISOST,ISOST" "0,1,2,3" group.long 0x88++0x7 line.long 0x0 "FMC_PMEM,The FMC_PMEM read/write register contains NAND Flash memory bank timing information. This information is used to access the NAND Flash common memory space for command. address write accesses or data read/write accesses." hexmask.long.byte 0x0 24.--31. 1. "MEMHIZ,MEMHIZ" hexmask.long.byte 0x0 16.--23. 1. "MEMHOLD,MEMHOLD" hexmask.long.byte 0x0 8.--15. 1. "MEMWAIT,MEMWAIT" hexmask.long.byte 0x0 0.--7. 1. "MEMSET,MEMSET" line.long 0x4 "FMC_PATT,The FMC_PATT read/write register contains NAND Flash memory bank timing information. It is used for 8-bit accesses to the NAND Flash attribute memory space during the last address write access when the timing differs from previous accesses (for.." hexmask.long.byte 0x4 24.--31. 1. "ATTHIZ,ATTHIZ" hexmask.long.byte 0x4 16.--23. 1. "ATTHOLD,ATTHOLD" hexmask.long.byte 0x4 8.--15. 1. "ATTWAIT,ATTWAIT" hexmask.long.byte 0x4 0.--7. 1. "ATTSET,ATTSET" rgroup.long 0x90++0x7 line.long 0x0 "FMC_HPR,This register is used during read accesses in conjunction with the FMC sequencer. It contains the current error correction code value computed by the FMC NAND controller Hamming module. When the FMC sequencer reads data from a NAND Flash memory.." hexmask.long 0x0 0.--31. 1. "HPR,HPR" line.long 0x4 "FMC_HECCR,This register contain the current error correction code value computed by the FMC NAND controller Hamming module.When the CPU reads/writes data from/to a NAND Flash memory page at the correct address (refer to Section25.8.6: NAND ECC.." hexmask.long 0x4 0.--31. 1. "HECC,HECC" group.long 0x104++0x3 line.long 0x0 "FMC_BWTR1,This register contains the control information of each memory bank. It is used for SRAMs. FRAMs. PSRAMs and NOR Flash memories. When the EXTMOD bit is set in the FMC_BCRx register. then this register is active for write access." bitfld.long 0x0 30.--31. "DATAHLD,DATAHLD" "0,1,2,3" bitfld.long 0x0 28.--29. "ACCMOD,ACCMOD" "0,1,2,3" hexmask.long.byte 0x0 16.--19. 1. "BUSTURN,BUSTURN" hexmask.long.byte 0x0 8.--15. 1. "DATAST,DATAST" hexmask.long.byte 0x0 4.--7. 1. "ADDHLD,ADDHLD" hexmask.long.byte 0x0 0.--3. 1. "ADDSET,ADDSET" group.long 0x10C++0x3 line.long 0x0 "FMC_BWTR2,This register contains the control information of each memory bank. It is used for SRAMs. FRAMs. PSRAMs and NOR Flash memories. When the EXTMOD bit is set in the FMC_BCRx register. then this register is active for write access." bitfld.long 0x0 30.--31. "DATAHLD,DATAHLD" "0,1,2,3" bitfld.long 0x0 28.--29. "ACCMOD,ACCMOD" "0,1,2,3" hexmask.long.byte 0x0 16.--19. 1. "BUSTURN,BUSTURN" hexmask.long.byte 0x0 8.--15. 1. "DATAST,DATAST" hexmask.long.byte 0x0 4.--7. 1. "ADDHLD,ADDHLD" hexmask.long.byte 0x0 0.--3. 1. "ADDSET,ADDSET" group.long 0x114++0x3 line.long 0x0 "FMC_BWTR3,This register contains the control information of each memory bank. It is used for SRAMs. FRAMs. PSRAMs and NOR Flash memories. When the EXTMOD bit is set in the FMC_BCRx register. then this register is active for write access." bitfld.long 0x0 30.--31. "DATAHLD,DATAHLD" "0,1,2,3" bitfld.long 0x0 28.--29. "ACCMOD,ACCMOD" "0,1,2,3" hexmask.long.byte 0x0 16.--19. 1. "BUSTURN,BUSTURN" hexmask.long.byte 0x0 8.--15. 1. "DATAST,DATAST" hexmask.long.byte 0x0 4.--7. 1. "ADDHLD,ADDHLD" hexmask.long.byte 0x0 0.--3. 1. "ADDSET,ADDSET" group.long 0x11C++0x3 line.long 0x0 "FMC_BWTR4,This register contains the control information of each memory bank. It is used for SRAMs. FRAMs. PSRAMs and NOR Flash memories. When the EXTMOD bit is set in the FMC_BCRx register. then this register is active for write access." bitfld.long 0x0 30.--31. "DATAHLD,DATAHLD" "0,1,2,3" bitfld.long 0x0 28.--29. "ACCMOD,ACCMOD" "0,1,2,3" hexmask.long.byte 0x0 16.--19. 1. "BUSTURN,BUSTURN" hexmask.long.byte 0x0 8.--15. 1. "DATAST,DATAST" hexmask.long.byte 0x0 4.--7. 1. "ADDHLD,ADDHLD" hexmask.long.byte 0x0 0.--3. 1. "ADDSET,ADDSET" wgroup.long 0x200++0x3 line.long 0x0 "FMC_CSQCR,FMC NAND Command Sequencer Control Register" bitfld.long 0x0 0. "CSQSTART,CSQSTART" "0,1" group.long 0x204++0x13 line.long 0x0 "FMC_CSQCFGR1,FMC NAND Command Sequencer Configuration Register 1" bitfld.long 0x0 25. "CMD2T,CMD2T" "0,1" bitfld.long 0x0 24. "CMD1T,CMD1T" "0,1" hexmask.long.byte 0x0 16.--23. 1. "CMD2,CMD2" hexmask.long.byte 0x0 8.--15. 1. "CMD1,CMD1" bitfld.long 0x0 4.--6. "ACYNBR,ACYNBR" "0,1,2,3,4,5,6,7" bitfld.long 0x0 2. "DMADEN,DMADEN" "0,1" newline bitfld.long 0x0 1. "CMD2EN,CMD2EN" "0,1" line.long 0x4 "FMC_CSQCFGR2,This register is used to configure the command sequencer to issue random read/ write commands to read/ write data by sector and automatically read/write data from NAND Flash memory at a programmable address offset. This is useful when.." bitfld.long 0x4 25. "RCMD2T,RCMD2T" "0,1" bitfld.long 0x4 24. "RCMD1T,RCMD1T" "0,1" hexmask.long.byte 0x4 16.--23. 1. "RCMD2,RCMD2" hexmask.long.byte 0x4 8.--15. 1. "RCMD1,RCMD1" bitfld.long 0x4 2. "DMASEN,DMASEN" "0,1" bitfld.long 0x4 1. "RCMD2EN,RCMD2EN" "0,1" newline bitfld.long 0x4 0. "SQSDTEN,SQSDTEN" "0,1" line.long 0x8 "FMC_CSQCFGR3,FMC NAND sequencer configuration register 3" bitfld.long 0x8 23. "RAC2T,RAC2T" "0,1" bitfld.long 0x8 22. "RAC1T,RAC1T" "0,1" bitfld.long 0x8 21. "SDT,SDT" "0,1" bitfld.long 0x8 20. "AC5T,AC5T" "0,1" bitfld.long 0x8 19. "AC4T,AC4T" "0,1" bitfld.long 0x8 18. "AC3T,AC3T" "0,1" newline bitfld.long 0x8 17. "AC2T,AC2T" "0,1" bitfld.long 0x8 16. "AC1T,AC1T" "0,1" hexmask.long.byte 0x8 8.--13. 1. "SNBR,SNBR" line.long 0xC "FMC_CSQAR1,This register is used to define the value of address cycles 1 to 4 to be issued by the command sequencer." hexmask.long.byte 0xC 24.--31. 1. "ADDC4,ADDC4" hexmask.long.byte 0xC 16.--23. 1. "ADDC3,ADDC3" hexmask.long.byte 0xC 8.--15. 1. "ADDC2,ADDC2" hexmask.long.byte 0xC 0.--7. 1. "ADDC1,ADDC1" line.long 0x10 "FMC_CSQAR2,This register is used to program the fifth address cycle and the address offset in spare area. It also selects the chip enable." hexmask.long.word 0x10 16.--31. 1. "SAO,SAO" bitfld.long 0x10 11. "NANDCEN1,NANDCEN1" "0,1" bitfld.long 0x10 10. "NANDCEN0,NANDCEN0" "0,1" hexmask.long.byte 0x10 0.--7. 1. "ADDC5,ADDC5" group.long 0x220++0x7 line.long 0x0 "FMC_CSQIER,FMC NAND Command Sequencer Interrupt Enable Register" bitfld.long 0x0 4. "CMDTCIE,CMDTCIE" "0,1" bitfld.long 0x0 3. "SUEIE,SUEIE" "0,1" bitfld.long 0x0 2. "SEIE,SEIE" "0,1" bitfld.long 0x0 1. "SCIE,SCIE" "0,1" bitfld.long 0x0 0. "TCIE,TCIE" "0,1" line.long 0x4 "FMC_CSQISR,FMC NAND Command Sequencer Interrupt Status Register" bitfld.long 0x4 4. "CMDTCF,CMDTCF" "0,1" bitfld.long 0x4 3. "SUEF,SUEF" "0,1" bitfld.long 0x4 2. "SEF,SEF" "0,1" bitfld.long 0x4 1. "SCF,SCF" "0,1" bitfld.long 0x4 0. "TCF,TCF" "0,1" wgroup.long 0x228++0x3 line.long 0x0 "FMC_CSQICR,FMC NAND Command Sequencer Interrupt Clear Register" bitfld.long 0x0 4. "CCMDTCF,CCMDTCF" "0,1" bitfld.long 0x0 3. "CSUEF,CSUEF" "0,1" bitfld.long 0x0 2. "CSEF,CSEF" "0,1" bitfld.long 0x0 1. "CSCF,CSCF" "0,1" bitfld.long 0x0 0. "CTCF,CTCF" "0,1" rgroup.long 0x230++0x3 line.long 0x0 "FMC_CSQEMSR,This register holds a sector error mapping status when the whole transfer is complete." hexmask.long.word 0x0 0.--15. 1. "SEM,SEM" group.long 0x250++0x3 line.long 0x0 "FMC_BCHIER,FMC BCH Interrupt enable register" bitfld.long 0x0 4. "EPBRIE,EPBRIE" "0,1" bitfld.long 0x0 3. "DSRIE,DSRIE" "0,1" bitfld.long 0x0 2. "DEFIE,DEFIE" "0,1" bitfld.long 0x0 1. "DERIE,DERIE" "0,1" bitfld.long 0x0 0. "DUEIE,DUEIE" "0,1" rgroup.long 0x254++0x3 line.long 0x0 "FMC_BCHISR,This register holds the status of BCH encoder/decoder after processing each sector. When the sequencer is used. this register is automatically cleared." bitfld.long 0x0 4. "EPBRF,EPBRF" "0,1" bitfld.long 0x0 3. "DSRF,DSRF" "0,1" bitfld.long 0x0 2. "DEFF,DEFF" "0,1" bitfld.long 0x0 1. "DERF,DERF" "0,1" bitfld.long 0x0 0. "DUEF,DUEF" "0,1" wgroup.long 0x258++0x3 line.long 0x0 "FMC_BCHICR,FMC BCH Interrupt Clear Register" bitfld.long 0x0 4. "CEPBRF,CEPBRF" "0,1" bitfld.long 0x0 3. "CDSRF,CDSRF" "0,1" bitfld.long 0x0 2. "CDEFF,CDEFF" "0,1" bitfld.long 0x0 1. "CDERF,CDERF" "0,1" bitfld.long 0x0 0. "CDUEF,CDUEF" "0,1" rgroup.long 0x260++0xF line.long 0x0 "FMC_BCHPBR1,These registers contain the BCH parity bits (BCHPB). For the BCH 4-bit. only BCHPB[51:0] are significant and for the BCH 8-bit BCHPB[103:0] are significant." hexmask.long 0x0 0.--31. 1. "BCHPB,BCHPB" line.long 0x4 "FMC_BCHPBR2,FMC BCH Parity Bits Register 2" hexmask.long 0x4 0.--31. 1. "BCHPB,BCHPB" line.long 0x8 "FMC_BCHPBR3,FMC BCH Parity Bits Register 3" hexmask.long 0x8 0.--31. 1. "BCHPB,BCHPB" line.long 0xC "FMC_BCHPBR4,FMC BCH Parity Bits Register 4" hexmask.long.byte 0xC 0.--7. 1. "BCHPB,BCHPB" rgroup.long 0x27C++0x13 line.long 0x0 "FMC_BCHDSR0,This register contains some fields already available in other registers but that require to be saved when error correction is performed on several sectors at a time (for example a whole NAND Flash page). This allows a DMA channel to transfer.." hexmask.long.byte 0x0 4.--7. 1. "DEN,DEN" bitfld.long 0x0 1. "DEF,DEF" "0,1" bitfld.long 0x0 0. "DUE,DUE" "0,1" line.long 0x4 "FMC_BCHDSR1,The maximum error correction capability of the BCH block embedded in the FMC is 8 errors" hexmask.long.word 0x4 16.--28. 1. "EBP2,EBP2" hexmask.long.word 0x4 0.--12. 1. "EBP1,EBP1" line.long 0x8 "FMC_BCHDSR2,The maximum error correction capability of the BCH block embedded in the FMC is 8 errors. This register contains the positions of the 3rd and 4th error bits in EBP3 and EPB4 fields. respectively." hexmask.long.word 0x8 16.--28. 1. "EBP4,EBP4" hexmask.long.word 0x8 0.--12. 1. "EBP3,EBP3" line.long 0xC "FMC_BCHDSR3,The maximum error correction capability of the BCH block embedded in the FMC is 8 errors." hexmask.long.word 0xC 16.--28. 1. "EBP6,EBP6" hexmask.long.word 0xC 0.--12. 1. "EBP5,EBP5" line.long 0x10 "FMC_BCHDSR4,The maximum error correction capability of the BCH block embedded in the FMC is 8 errors. This register contains the positions of the 7th and 8th error bits in EBP7 and EPB8 fields. respectively. ." hexmask.long.word 0x10 16.--28. 1. "EBP8,EBP8" hexmask.long.word 0x10 0.--12. 1. "EBP7,EBP7" rgroup.long 0x3EC++0x13 line.long 0x0 "FMC_HWCFGR2,FMC Hardware configuration register 2" hexmask.long.byte 0x0 20.--23. 1. "SDRAM2_BASE,SDRAM2_BASE" hexmask.long.byte 0x0 16.--19. 1. "SDRAM1_BASE,SDRAM1_BASE" hexmask.long.byte 0x0 12.--15. 1. "NAND_BASE,NAND_BASE" hexmask.long.byte 0x0 8.--11. 1. "SDRAM_RBASE,SDRAM_RBASE" hexmask.long.byte 0x0 4.--7. 1. "NOR_BASE,NOR_BASE" hexmask.long.byte 0x0 0.--3. 1. "RD_LN2DPTH,RD_LN2DPTH" line.long 0x4 "FMC_HWCFGR1,FMC Hardware configuration register 1" hexmask.long.byte 0x4 28.--31. 1. "RA_LN2DPTH,RA_LN2DPTH" hexmask.long.byte 0x4 24.--27. 1. "WR_LN2DPTH,WR_LN2DPTH" hexmask.long.byte 0x4 20.--23. 1. "WD_LN2DPTH,WD_LN2DPTH" hexmask.long.byte 0x4 16.--19. 1. "WA_LN2DPTH,WA_LN2DPTH" hexmask.long.byte 0x4 12.--15. 1. "ID_SIZE,ID_SIZE" bitfld.long 0x4 8. "SDRAM_SEL,SDRAM_SEL" "0,1" newline bitfld.long 0x4 4. "NAND_ECC,NAND_ECC" "0,1" bitfld.long 0x4 0. "NAND_SEL,NAND_SEL" "0,1" line.long 0x8 "FMC_VERR,FMC Version register" hexmask.long.byte 0x8 4.--7. 1. "MAJREV,MAJREV" hexmask.long.byte 0x8 0.--3. 1. "MINREV,MINREV" line.long 0xC "FMC_IPIDR,FMC Identification register" hexmask.long 0xC 0.--31. 1. "ID,ID" line.long 0x10 "FMC_SIDR,FMC Size Identification register" hexmask.long 0x10 0.--31. 1. "SID,SID" tree.end tree "GIC (Global Interrupt Controller)" base ad:0x0 sif (cpuis("STM32MP13*")) tree "GICD" base ad:0xA0021000 group.long 0x0++0x3 line.long 0x0 "GICD_CTLR,GICD_CTLR" bitfld.long 0x0 1. "ENABLEGRP1,enable group 1 interrupts" "0,1" bitfld.long 0x0 0. "ENABLEGRP0,enable group 1 interrupts" "0,1" group.long 0x0++0x3 line.long 0x0 "GICD_CTLRNS,GICD_CTLRNS" bitfld.long 0x0 1. "ENABLEGRP1,enable group 1 interrupts" "0,1" bitfld.long 0x0 0. "ENABLE,Global enable for forwarding pending group 1 interrupts from the GICD to the CPU interfaces" "0,1" rgroup.long 0x4++0x7 line.long 0x0 "GICD_TYPER," hexmask.long.byte 0x0 11.--15. 1. "LSPI,lockable shared peripheral interrupt" bitfld.long 0x0 10. "SECURITYEXTN,security extension" "0,1" bitfld.long 0x0 5.--7. "CPUNUMBER,number of processors interfaces" "0: 1 processor,?,?,?,?,?,?,?" newline hexmask.long.byte 0x0 0.--4. 1. "ITLINESNUMBER,number of interrupt lines" line.long 0x4 "GICD_IIDR," hexmask.long.byte 0x4 24.--31. 1. "PRODUCTID,product ID of the GIC" hexmask.long.byte 0x4 16.--19. 1. "VARIANT,Indicates the major revision number of the GIC" hexmask.long.byte 0x4 12.--15. 1. "REVISION,Indicates the minor revision number of the GIC" newline hexmask.long.word 0x4 0.--11. 1. "IMPLEMENTER,GIC implementer (0x43B Arm implementation)" group.long 0x80++0x17 line.long 0x0 "GICD_IGROUPR0,GICD interrupt group register 0" hexmask.long 0x0 0.--31. 1. "IGROUPRx,group of interrupts" line.long 0x4 "GICD_IGROUPR1,GICD interrupt group register 1" hexmask.long 0x4 0.--31. 1. "IGROUPRx,group of interrupts" line.long 0x8 "GICD_IGROUPR2,GICD interrupt group register 2" hexmask.long 0x8 0.--31. 1. "IGROUPRx,group of interrupts" line.long 0xC "GICD_IGROUPR3,GICD interrupt group register 3" hexmask.long 0xC 0.--31. 1. "IGROUPRx,group of interrupts" line.long 0x10 "GICD_IGROUPR4,GICD interrupt group register 4" hexmask.long 0x10 0.--31. 1. "IGROUPRx,group of interrupts" line.long 0x14 "GICD_IGROUPR5,GICD interrupt group register 5" hexmask.long 0x14 0.--31. 1. "IGROUPRx,group of interrupts" group.long 0x100++0x17 line.long 0x0 "GICD_ISENABLER0,GICD interrupt set-enable register" hexmask.long 0x0 0.--31. 1. "ISENABLER0,interrupt set-enable 0" line.long 0x4 "GICD_ISENABLER1,GICD interrupt set-enable register 1" hexmask.long 0x4 0.--31. 1. "ISENABLERx,interrupt set-enable x" line.long 0x8 "GICD_ISENABLER2,GICD interrupt set-enable register 2" hexmask.long 0x8 0.--31. 1. "ISENABLERx,interrupt set-enable x" line.long 0xC "GICD_ISENABLER3,GICD interrupt set-enable register 3" hexmask.long 0xC 0.--31. 1. "ISENABLERx,interrupt set-enable x" line.long 0x10 "GICD_ISENABLER4,GICD interrupt set-enable register 4" hexmask.long 0x10 0.--31. 1. "ISENABLERx,interrupt set-enable x" line.long 0x14 "GICD_ISENABLER5,GICD interrupt set-enable register 5" hexmask.long 0x14 0.--31. 1. "ISENABLERx,interrupt set-enable x" group.long 0x180++0x17 line.long 0x0 "GICD_ICENABLER0,GICD interrupt clear-enable register" hexmask.long 0x0 0.--31. 1. "ICENABLER0,interrupt clear-enable 0" line.long 0x4 "GICD_ICENABLER1,GICD interrupt clear-enable register 1" hexmask.long 0x4 0.--31. 1. "ICENABLERx,interrupt clear-enable x" line.long 0x8 "GICD_ICENABLER2,GICD interrupt clear-enable register 2" hexmask.long 0x8 0.--31. 1. "ICENABLERx,interrupt clear-enable x" line.long 0xC "GICD_ICENABLER3,GICD interrupt clear-enable register 3" hexmask.long 0xC 0.--31. 1. "ICENABLERx,interrupt clear-enable x" line.long 0x10 "GICD_ICENABLER4,GICD interrupt clear-enable register 4" hexmask.long 0x10 0.--31. 1. "ICENABLERx,interrupt clear-enable x" line.long 0x14 "GICD_ICENABLER5,GICD interrupt clear-enable register 5" hexmask.long 0x14 0.--31. 1. "ICENABLERx,interrupt clear-enable x" group.long 0x200++0x17 line.long 0x0 "GICD_ISPENDR0,GICD interrupt set-pending register 0" hexmask.long 0x0 0.--31. 1. "ISPENDRx,interrupt set-pending x" line.long 0x4 "GICD_ISPENDR1,GICD interrupt set-pending register 1" hexmask.long 0x4 0.--31. 1. "ISPENDRx,interrupt set-pending x" line.long 0x8 "GICD_ISPENDR2,GICD interrupt set-pending register 2" hexmask.long 0x8 0.--31. 1. "ISPENDRx,interrupt set-pending x" line.long 0xC "GICD_ISPENDR3,GICD interrupt set-pending register 3" hexmask.long 0xC 0.--31. 1. "ISPENDRx,interrupt set-pending x" line.long 0x10 "GICD_ISPENDR4,GICD interrupt set-pending register 4" hexmask.long 0x10 0.--31. 1. "ISPENDRx,interrupt set-pending x" line.long 0x14 "GICD_ISPENDR5,GICD interrupt set-pending register 5" hexmask.long 0x14 0.--31. 1. "ISPENDRx,interrupt set-pending x" group.long 0x280++0x17 line.long 0x0 "GICD_ICPENDR0,GICD interrupt clear-pending register 0" hexmask.long 0x0 0.--31. 1. "ICPENDRx,interrupt clear-pending x" line.long 0x4 "GICD_ICPENDR1,GICD interrupt clear-pending register 1" hexmask.long 0x4 0.--31. 1. "ICPENDRx,interrupt clear-pending x" line.long 0x8 "GICD_ICPENDR2,GICD interrupt clear-pending register 2" hexmask.long 0x8 0.--31. 1. "ICPENDRx,interrupt clear-pending x" line.long 0xC "GICD_ICPENDR3,GICD interrupt clear-pending register 3" hexmask.long 0xC 0.--31. 1. "ICPENDRx,interrupt clear-pending x" line.long 0x10 "GICD_ICPENDR4,GICD interrupt clear-pending register 4" hexmask.long 0x10 0.--31. 1. "ICPENDRx,interrupt clear-pending x" line.long 0x14 "GICD_ICPENDR5,GICD interrupt clear-pending register 5" hexmask.long 0x14 0.--31. 1. "ICPENDRx,interrupt clear-pending x" group.long 0x300++0x17 line.long 0x0 "GICD_ISACTIVER0,GICD interrupt set-active register 0" hexmask.long 0x0 0.--31. 1. "ISACTIVERx,interrupt set-active x" line.long 0x4 "GICD_ISACTIVER1,GICD interrupt set-active register 1" hexmask.long 0x4 0.--31. 1. "ISACTIVERx,interrupt set-active x" line.long 0x8 "GICD_ISACTIVER2,GICD interrupt set-active register 2" hexmask.long 0x8 0.--31. 1. "ISACTIVERx,interrupt set-active x" line.long 0xC "GICD_ISACTIVER3,GICD interrupt set-active register 3" hexmask.long 0xC 0.--31. 1. "ISACTIVERx,interrupt set-active x" line.long 0x10 "GICD_ISACTIVER4,GICD interrupt set-active register 4" hexmask.long 0x10 0.--31. 1. "ISACTIVERx,interrupt set-active x" line.long 0x14 "GICD_ISACTIVER5,GICD interrupt set-active register 5" hexmask.long 0x14 0.--31. 1. "ISACTIVERx,interrupt set-active x" group.long 0x380++0x17 line.long 0x0 "GICD_ICACTIVER0,GICD interrupt clear-active register 0" hexmask.long 0x0 0.--31. 1. "ICACTIVERx,interrupt clear-active x" line.long 0x4 "GICD_ICACTIVER1,GICD interrupt clear-active register 1" hexmask.long 0x4 0.--31. 1. "ICACTIVERx,interrupt clear-active x" line.long 0x8 "GICD_ICACTIVER2,GICD interrupt clear-active register 2" hexmask.long 0x8 0.--31. 1. "ICACTIVERx,interrupt clear-active x" line.long 0xC "GICD_ICACTIVER3,GICD interrupt clear-active register 3" hexmask.long 0xC 0.--31. 1. "ICACTIVERx,interrupt clear-active x" line.long 0x10 "GICD_ICACTIVER4,GICD interrupt clear-active register 4" hexmask.long 0x10 0.--31. 1. "ICACTIVERx,interrupt clear-active x" line.long 0x14 "GICD_ICACTIVER5,GICD interrupt clear-active register 5" hexmask.long 0x14 0.--31. 1. "ICACTIVERx,interrupt clear-active x" group.long 0x400++0xBF line.long 0x0 "GICD_IPRIORITYR0," hexmask.long.byte 0x0 27.--31. 1. "PRIORITY3,priority for interrupt ID = x * 4 + 3" hexmask.long.byte 0x0 19.--23. 1. "PRIORITY2,priority for interrupt ID = x * 4 + 2" hexmask.long.byte 0x0 11.--15. 1. "PRIORITY1,priority for interrupt ID = x * 4 + 1" newline hexmask.long.byte 0x0 3.--7. 1. "PRIORITY0,priority for interrupt ID = x * 4" line.long 0x4 "GICD_IPRIORITYR1," hexmask.long.byte 0x4 27.--31. 1. "PRIORITY3,priority for interrupt ID = x * 4 + 3" hexmask.long.byte 0x4 19.--23. 1. "PRIORITY2,priority for interrupt ID = x * 4 + 2" hexmask.long.byte 0x4 11.--15. 1. "PRIORITY1,priority for interrupt ID = x * 4 + 1" newline hexmask.long.byte 0x4 3.--7. 1. "PRIORITY0,priority for interrupt ID = x * 4" line.long 0x8 "GICD_IPRIORITYR2," hexmask.long.byte 0x8 27.--31. 1. "PRIORITY3,priority for interrupt ID = x * 4 + 3" hexmask.long.byte 0x8 19.--23. 1. "PRIORITY2,priority for interrupt ID = x * 4 + 2" hexmask.long.byte 0x8 11.--15. 1. "PRIORITY1,priority for interrupt ID = x * 4 + 1" newline hexmask.long.byte 0x8 3.--7. 1. "PRIORITY0,priority for interrupt ID = x * 4" line.long 0xC "GICD_IPRIORITYR3," hexmask.long.byte 0xC 27.--31. 1. "PRIORITY3,priority for interrupt ID = x * 4 + 3" hexmask.long.byte 0xC 19.--23. 1. "PRIORITY2,priority for interrupt ID = x * 4 + 2" hexmask.long.byte 0xC 11.--15. 1. "PRIORITY1,priority for interrupt ID = x * 4 + 1" newline hexmask.long.byte 0xC 3.--7. 1. "PRIORITY0,priority for interrupt ID = x * 4" line.long 0x10 "GICD_IPRIORITYR4," hexmask.long.byte 0x10 27.--31. 1. "PRIORITY3,priority for interrupt ID = x * 4 + 3" hexmask.long.byte 0x10 19.--23. 1. "PRIORITY2,priority for interrupt ID = x * 4 + 2" hexmask.long.byte 0x10 11.--15. 1. "PRIORITY1,priority for interrupt ID = x * 4 + 1" newline hexmask.long.byte 0x10 3.--7. 1. "PRIORITY0,priority for interrupt ID = x * 4" line.long 0x14 "GICD_IPRIORITYR5," hexmask.long.byte 0x14 27.--31. 1. "PRIORITY3,priority for interrupt ID = x * 4 + 3" hexmask.long.byte 0x14 19.--23. 1. "PRIORITY2,priority for interrupt ID = x * 4 + 2" hexmask.long.byte 0x14 11.--15. 1. "PRIORITY1,priority for interrupt ID = x * 4 + 1" newline hexmask.long.byte 0x14 3.--7. 1. "PRIORITY0,priority for interrupt ID = x * 4" line.long 0x18 "GICD_IPRIORITYR6," hexmask.long.byte 0x18 27.--31. 1. "PRIORITY3,priority for interrupt ID = x * 4 + 3" hexmask.long.byte 0x18 19.--23. 1. "PRIORITY2,priority for interrupt ID = x * 4 + 2" hexmask.long.byte 0x18 11.--15. 1. "PRIORITY1,priority for interrupt ID = x * 4 + 1" newline hexmask.long.byte 0x18 3.--7. 1. "PRIORITY0,priority for interrupt ID = x * 4" line.long 0x1C "GICD_IPRIORITYR7," hexmask.long.byte 0x1C 27.--31. 1. "PRIORITY3,priority for interrupt ID = x * 4 + 3" hexmask.long.byte 0x1C 19.--23. 1. "PRIORITY2,priority for interrupt ID = x * 4 + 2" hexmask.long.byte 0x1C 11.--15. 1. "PRIORITY1,priority for interrupt ID = x * 4 + 1" newline hexmask.long.byte 0x1C 3.--7. 1. "PRIORITY0,priority for interrupt ID = x * 4" line.long 0x20 "GICD_IPRIORITYR8," hexmask.long.byte 0x20 27.--31. 1. "PRIORITY3,priority for interrupt ID = x * 4 + 3" hexmask.long.byte 0x20 19.--23. 1. "PRIORITY2,priority for interrupt ID = x * 4 + 2" hexmask.long.byte 0x20 11.--15. 1. "PRIORITY1,priority for interrupt ID = x * 4 + 1" newline hexmask.long.byte 0x20 3.--7. 1. "PRIORITY0,priority for interrupt ID = x * 4" line.long 0x24 "GICD_IPRIORITYR9," hexmask.long.byte 0x24 27.--31. 1. "PRIORITY3,priority for interrupt ID = x * 4 + 3" hexmask.long.byte 0x24 19.--23. 1. "PRIORITY2,priority for interrupt ID = x * 4 + 2" hexmask.long.byte 0x24 11.--15. 1. "PRIORITY1,priority for interrupt ID = x * 4 + 1" newline hexmask.long.byte 0x24 3.--7. 1. "PRIORITY0,priority for interrupt ID = x * 4" line.long 0x28 "GICD_IPRIORITYR10," hexmask.long.byte 0x28 27.--31. 1. "PRIORITY3,priority for interrupt ID = x * 4 + 3" hexmask.long.byte 0x28 19.--23. 1. "PRIORITY2,priority for interrupt ID = x * 4 + 2" hexmask.long.byte 0x28 11.--15. 1. "PRIORITY1,priority for interrupt ID = x * 4 + 1" newline hexmask.long.byte 0x28 3.--7. 1. "PRIORITY0,priority for interrupt ID = x * 4" line.long 0x2C "GICD_IPRIORITYR11," hexmask.long.byte 0x2C 27.--31. 1. "PRIORITY3,priority for interrupt ID = x * 4 + 3" hexmask.long.byte 0x2C 19.--23. 1. "PRIORITY2,priority for interrupt ID = x * 4 + 2" hexmask.long.byte 0x2C 11.--15. 1. "PRIORITY1,priority for interrupt ID = x * 4 + 1" newline hexmask.long.byte 0x2C 3.--7. 1. "PRIORITY0,priority for interrupt ID = x * 4" line.long 0x30 "GICD_IPRIORITYR12," hexmask.long.byte 0x30 27.--31. 1. "PRIORITY3,priority for interrupt ID = x * 4 + 3" hexmask.long.byte 0x30 19.--23. 1. "PRIORITY2,priority for interrupt ID = x * 4 + 2" hexmask.long.byte 0x30 11.--15. 1. "PRIORITY1,priority for interrupt ID = x * 4 + 1" newline hexmask.long.byte 0x30 3.--7. 1. "PRIORITY0,priority for interrupt ID = x * 4" line.long 0x34 "GICD_IPRIORITYR13," hexmask.long.byte 0x34 27.--31. 1. "PRIORITY3,priority for interrupt ID = x * 4 + 3" hexmask.long.byte 0x34 19.--23. 1. "PRIORITY2,priority for interrupt ID = x * 4 + 2" hexmask.long.byte 0x34 11.--15. 1. "PRIORITY1,priority for interrupt ID = x * 4 + 1" newline hexmask.long.byte 0x34 3.--7. 1. "PRIORITY0,priority for interrupt ID = x * 4" line.long 0x38 "GICD_IPRIORITYR14," hexmask.long.byte 0x38 27.--31. 1. "PRIORITY3,priority for interrupt ID = x * 4 + 3" hexmask.long.byte 0x38 19.--23. 1. "PRIORITY2,priority for interrupt ID = x * 4 + 2" hexmask.long.byte 0x38 11.--15. 1. "PRIORITY1,priority for interrupt ID = x * 4 + 1" newline hexmask.long.byte 0x38 3.--7. 1. "PRIORITY0,priority for interrupt ID = x * 4" line.long 0x3C "GICD_IPRIORITYR15," hexmask.long.byte 0x3C 27.--31. 1. "PRIORITY3,priority for interrupt ID = x * 4 + 3" hexmask.long.byte 0x3C 19.--23. 1. "PRIORITY2,priority for interrupt ID = x * 4 + 2" hexmask.long.byte 0x3C 11.--15. 1. "PRIORITY1,priority for interrupt ID = x * 4 + 1" newline hexmask.long.byte 0x3C 3.--7. 1. "PRIORITY0,priority for interrupt ID = x * 4" line.long 0x40 "GICD_IPRIORITYR16," hexmask.long.byte 0x40 27.--31. 1. "PRIORITY3,priority for interrupt ID = x * 4 + 3" hexmask.long.byte 0x40 19.--23. 1. "PRIORITY2,priority for interrupt ID = x * 4 + 2" hexmask.long.byte 0x40 11.--15. 1. "PRIORITY1,priority for interrupt ID = x * 4 + 1" newline hexmask.long.byte 0x40 3.--7. 1. "PRIORITY0,priority for interrupt ID = x * 4" line.long 0x44 "GICD_IPRIORITYR17," hexmask.long.byte 0x44 27.--31. 1. "PRIORITY3,priority for interrupt ID = x * 4 + 3" hexmask.long.byte 0x44 19.--23. 1. "PRIORITY2,priority for interrupt ID = x * 4 + 2" hexmask.long.byte 0x44 11.--15. 1. "PRIORITY1,priority for interrupt ID = x * 4 + 1" newline hexmask.long.byte 0x44 3.--7. 1. "PRIORITY0,priority for interrupt ID = x * 4" line.long 0x48 "GICD_IPRIORITYR18," hexmask.long.byte 0x48 27.--31. 1. "PRIORITY3,priority for interrupt ID = x * 4 + 3" hexmask.long.byte 0x48 19.--23. 1. "PRIORITY2,priority for interrupt ID = x * 4 + 2" hexmask.long.byte 0x48 11.--15. 1. "PRIORITY1,priority for interrupt ID = x * 4 + 1" newline hexmask.long.byte 0x48 3.--7. 1. "PRIORITY0,priority for interrupt ID = x * 4" line.long 0x4C "GICD_IPRIORITYR19," hexmask.long.byte 0x4C 27.--31. 1. "PRIORITY3,priority for interrupt ID = x * 4 + 3" hexmask.long.byte 0x4C 19.--23. 1. "PRIORITY2,priority for interrupt ID = x * 4 + 2" hexmask.long.byte 0x4C 11.--15. 1. "PRIORITY1,priority for interrupt ID = x * 4 + 1" newline hexmask.long.byte 0x4C 3.--7. 1. "PRIORITY0,priority for interrupt ID = x * 4" line.long 0x50 "GICD_IPRIORITYR20," hexmask.long.byte 0x50 27.--31. 1. "PRIORITY3,priority for interrupt ID = x * 4 + 3" hexmask.long.byte 0x50 19.--23. 1. "PRIORITY2,priority for interrupt ID = x * 4 + 2" hexmask.long.byte 0x50 11.--15. 1. "PRIORITY1,priority for interrupt ID = x * 4 + 1" newline hexmask.long.byte 0x50 3.--7. 1. "PRIORITY0,priority for interrupt ID = x * 4" line.long 0x54 "GICD_IPRIORITYR21," hexmask.long.byte 0x54 27.--31. 1. "PRIORITY3,priority for interrupt ID = x * 4 + 3" hexmask.long.byte 0x54 19.--23. 1. "PRIORITY2,priority for interrupt ID = x * 4 + 2" hexmask.long.byte 0x54 11.--15. 1. "PRIORITY1,priority for interrupt ID = x * 4 + 1" newline hexmask.long.byte 0x54 3.--7. 1. "PRIORITY0,priority for interrupt ID = x * 4" line.long 0x58 "GICD_IPRIORITYR22," hexmask.long.byte 0x58 27.--31. 1. "PRIORITY3,priority for interrupt ID = x * 4 + 3" hexmask.long.byte 0x58 19.--23. 1. "PRIORITY2,priority for interrupt ID = x * 4 + 2" hexmask.long.byte 0x58 11.--15. 1. "PRIORITY1,priority for interrupt ID = x * 4 + 1" newline hexmask.long.byte 0x58 3.--7. 1. "PRIORITY0,priority for interrupt ID = x * 4" line.long 0x5C "GICD_IPRIORITYR23," hexmask.long.byte 0x5C 27.--31. 1. "PRIORITY3,priority for interrupt ID = x * 4 + 3" hexmask.long.byte 0x5C 19.--23. 1. "PRIORITY2,priority for interrupt ID = x * 4 + 2" hexmask.long.byte 0x5C 11.--15. 1. "PRIORITY1,priority for interrupt ID = x * 4 + 1" newline hexmask.long.byte 0x5C 3.--7. 1. "PRIORITY0,priority for interrupt ID = x * 4" line.long 0x60 "GICD_IPRIORITYR24," hexmask.long.byte 0x60 27.--31. 1. "PRIORITY3,priority for interrupt ID = x * 4 + 3" hexmask.long.byte 0x60 19.--23. 1. "PRIORITY2,priority for interrupt ID = x * 4 + 2" hexmask.long.byte 0x60 11.--15. 1. "PRIORITY1,priority for interrupt ID = x * 4 + 1" newline hexmask.long.byte 0x60 3.--7. 1. "PRIORITY0,priority for interrupt ID = x * 4" line.long 0x64 "GICD_IPRIORITYR25," hexmask.long.byte 0x64 27.--31. 1. "PRIORITY3,priority for interrupt ID = x * 4 + 3" hexmask.long.byte 0x64 19.--23. 1. "PRIORITY2,priority for interrupt ID = x * 4 + 2" hexmask.long.byte 0x64 11.--15. 1. "PRIORITY1,priority for interrupt ID = x * 4 + 1" newline hexmask.long.byte 0x64 3.--7. 1. "PRIORITY0,priority for interrupt ID = x * 4" line.long 0x68 "GICD_IPRIORITYR26," hexmask.long.byte 0x68 27.--31. 1. "PRIORITY3,priority for interrupt ID = x * 4 + 3" hexmask.long.byte 0x68 19.--23. 1. "PRIORITY2,priority for interrupt ID = x * 4 + 2" hexmask.long.byte 0x68 11.--15. 1. "PRIORITY1,priority for interrupt ID = x * 4 + 1" newline hexmask.long.byte 0x68 3.--7. 1. "PRIORITY0,priority for interrupt ID = x * 4" line.long 0x6C "GICD_IPRIORITYR27," hexmask.long.byte 0x6C 27.--31. 1. "PRIORITY3,priority for interrupt ID = x * 4 + 3" hexmask.long.byte 0x6C 19.--23. 1. "PRIORITY2,priority for interrupt ID = x * 4 + 2" hexmask.long.byte 0x6C 11.--15. 1. "PRIORITY1,priority for interrupt ID = x * 4 + 1" newline hexmask.long.byte 0x6C 3.--7. 1. "PRIORITY0,priority for interrupt ID = x * 4" line.long 0x70 "GICD_IPRIORITYR28," hexmask.long.byte 0x70 27.--31. 1. "PRIORITY3,priority for interrupt ID = x * 4 + 3" hexmask.long.byte 0x70 19.--23. 1. "PRIORITY2,priority for interrupt ID = x * 4 + 2" hexmask.long.byte 0x70 11.--15. 1. "PRIORITY1,priority for interrupt ID = x * 4 + 1" newline hexmask.long.byte 0x70 3.--7. 1. "PRIORITY0,priority for interrupt ID = x * 4" line.long 0x74 "GICD_IPRIORITYR29," hexmask.long.byte 0x74 27.--31. 1. "PRIORITY3,priority for interrupt ID = x * 4 + 3" hexmask.long.byte 0x74 19.--23. 1. "PRIORITY2,priority for interrupt ID = x * 4 + 2" hexmask.long.byte 0x74 11.--15. 1. "PRIORITY1,priority for interrupt ID = x * 4 + 1" newline hexmask.long.byte 0x74 3.--7. 1. "PRIORITY0,priority for interrupt ID = x * 4" line.long 0x78 "GICD_IPRIORITYR30," hexmask.long.byte 0x78 27.--31. 1. "PRIORITY3,priority for interrupt ID = x * 4 + 3" hexmask.long.byte 0x78 19.--23. 1. "PRIORITY2,priority for interrupt ID = x * 4 + 2" hexmask.long.byte 0x78 11.--15. 1. "PRIORITY1,priority for interrupt ID = x * 4 + 1" newline hexmask.long.byte 0x78 3.--7. 1. "PRIORITY0,priority for interrupt ID = x * 4" line.long 0x7C "GICD_IPRIORITYR31," hexmask.long.byte 0x7C 27.--31. 1. "PRIORITY3,priority for interrupt ID = x * 4 + 3" hexmask.long.byte 0x7C 19.--23. 1. "PRIORITY2,priority for interrupt ID = x * 4 + 2" hexmask.long.byte 0x7C 11.--15. 1. "PRIORITY1,priority for interrupt ID = x * 4 + 1" newline hexmask.long.byte 0x7C 3.--7. 1. "PRIORITY0,priority for interrupt ID = x * 4" line.long 0x80 "GICD_IPRIORITYR32," hexmask.long.byte 0x80 27.--31. 1. "PRIORITY3,priority for interrupt ID = x * 4 + 3" hexmask.long.byte 0x80 19.--23. 1. "PRIORITY2,priority for interrupt ID = x * 4 + 2" hexmask.long.byte 0x80 11.--15. 1. "PRIORITY1,priority for interrupt ID = x * 4 + 1" newline hexmask.long.byte 0x80 3.--7. 1. "PRIORITY0,priority for interrupt ID = x * 4" line.long 0x84 "GICD_IPRIORITYR33," hexmask.long.byte 0x84 27.--31. 1. "PRIORITY3,priority for interrupt ID = x * 4 + 3" hexmask.long.byte 0x84 19.--23. 1. "PRIORITY2,priority for interrupt ID = x * 4 + 2" hexmask.long.byte 0x84 11.--15. 1. "PRIORITY1,priority for interrupt ID = x * 4 + 1" newline hexmask.long.byte 0x84 3.--7. 1. "PRIORITY0,priority for interrupt ID = x * 4" line.long 0x88 "GICD_IPRIORITYR34," hexmask.long.byte 0x88 27.--31. 1. "PRIORITY3,priority for interrupt ID = x * 4 + 3" hexmask.long.byte 0x88 19.--23. 1. "PRIORITY2,priority for interrupt ID = x * 4 + 2" hexmask.long.byte 0x88 11.--15. 1. "PRIORITY1,priority for interrupt ID = x * 4 + 1" newline hexmask.long.byte 0x88 3.--7. 1. "PRIORITY0,priority for interrupt ID = x * 4" line.long 0x8C "GICD_IPRIORITYR35," hexmask.long.byte 0x8C 27.--31. 1. "PRIORITY3,priority for interrupt ID = x * 4 + 3" hexmask.long.byte 0x8C 19.--23. 1. "PRIORITY2,priority for interrupt ID = x * 4 + 2" hexmask.long.byte 0x8C 11.--15. 1. "PRIORITY1,priority for interrupt ID = x * 4 + 1" newline hexmask.long.byte 0x8C 3.--7. 1. "PRIORITY0,priority for interrupt ID = x * 4" line.long 0x90 "GICD_IPRIORITYR36," hexmask.long.byte 0x90 27.--31. 1. "PRIORITY3,priority for interrupt ID = x * 4 + 3" hexmask.long.byte 0x90 19.--23. 1. "PRIORITY2,priority for interrupt ID = x * 4 + 2" hexmask.long.byte 0x90 11.--15. 1. "PRIORITY1,priority for interrupt ID = x * 4 + 1" newline hexmask.long.byte 0x90 3.--7. 1. "PRIORITY0,priority for interrupt ID = x * 4" line.long 0x94 "GICD_IPRIORITYR37," hexmask.long.byte 0x94 27.--31. 1. "PRIORITY3,priority for interrupt ID = x * 4 + 3" hexmask.long.byte 0x94 19.--23. 1. "PRIORITY2,priority for interrupt ID = x * 4 + 2" hexmask.long.byte 0x94 11.--15. 1. "PRIORITY1,priority for interrupt ID = x * 4 + 1" newline hexmask.long.byte 0x94 3.--7. 1. "PRIORITY0,priority for interrupt ID = x * 4" line.long 0x98 "GICD_IPRIORITYR38," hexmask.long.byte 0x98 27.--31. 1. "PRIORITY3,priority for interrupt ID = x * 4 + 3" hexmask.long.byte 0x98 19.--23. 1. "PRIORITY2,priority for interrupt ID = x * 4 + 2" hexmask.long.byte 0x98 11.--15. 1. "PRIORITY1,priority for interrupt ID = x * 4 + 1" newline hexmask.long.byte 0x98 3.--7. 1. "PRIORITY0,priority for interrupt ID = x * 4" line.long 0x9C "GICD_IPRIORITYR39," hexmask.long.byte 0x9C 27.--31. 1. "PRIORITY3,priority for interrupt ID = x * 4 + 3" hexmask.long.byte 0x9C 19.--23. 1. "PRIORITY2,priority for interrupt ID = x * 4 + 2" hexmask.long.byte 0x9C 11.--15. 1. "PRIORITY1,priority for interrupt ID = x * 4 + 1" newline hexmask.long.byte 0x9C 3.--7. 1. "PRIORITY0,priority for interrupt ID = x * 4" line.long 0xA0 "GICD_IPRIORITYR40," hexmask.long.byte 0xA0 27.--31. 1. "PRIORITY3,priority for interrupt ID = x * 4 + 3" hexmask.long.byte 0xA0 19.--23. 1. "PRIORITY2,priority for interrupt ID = x * 4 + 2" hexmask.long.byte 0xA0 11.--15. 1. "PRIORITY1,priority for interrupt ID = x * 4 + 1" newline hexmask.long.byte 0xA0 3.--7. 1. "PRIORITY0,priority for interrupt ID = x * 4" line.long 0xA4 "GICD_IPRIORITYR41," hexmask.long.byte 0xA4 27.--31. 1. "PRIORITY3,priority for interrupt ID = x * 4 + 3" hexmask.long.byte 0xA4 19.--23. 1. "PRIORITY2,priority for interrupt ID = x * 4 + 2" hexmask.long.byte 0xA4 11.--15. 1. "PRIORITY1,priority for interrupt ID = x * 4 + 1" newline hexmask.long.byte 0xA4 3.--7. 1. "PRIORITY0,priority for interrupt ID = x * 4" line.long 0xA8 "GICD_IPRIORITYR42," hexmask.long.byte 0xA8 27.--31. 1. "PRIORITY3,priority for interrupt ID = x * 4 + 3" hexmask.long.byte 0xA8 19.--23. 1. "PRIORITY2,priority for interrupt ID = x * 4 + 2" hexmask.long.byte 0xA8 11.--15. 1. "PRIORITY1,priority for interrupt ID = x * 4 + 1" newline hexmask.long.byte 0xA8 3.--7. 1. "PRIORITY0,priority for interrupt ID = x * 4" line.long 0xAC "GICD_IPRIORITYR43," hexmask.long.byte 0xAC 27.--31. 1. "PRIORITY3,priority for interrupt ID = x * 4 + 3" hexmask.long.byte 0xAC 19.--23. 1. "PRIORITY2,priority for interrupt ID = x * 4 + 2" hexmask.long.byte 0xAC 11.--15. 1. "PRIORITY1,priority for interrupt ID = x * 4 + 1" newline hexmask.long.byte 0xAC 3.--7. 1. "PRIORITY0,priority for interrupt ID = x * 4" line.long 0xB0 "GICD_IPRIORITYR44," hexmask.long.byte 0xB0 27.--31. 1. "PRIORITY3,priority for interrupt ID = x * 4 + 3" hexmask.long.byte 0xB0 19.--23. 1. "PRIORITY2,priority for interrupt ID = x * 4 + 2" hexmask.long.byte 0xB0 11.--15. 1. "PRIORITY1,priority for interrupt ID = x * 4 + 1" newline hexmask.long.byte 0xB0 3.--7. 1. "PRIORITY0,priority for interrupt ID = x * 4" line.long 0xB4 "GICD_IPRIORITYR45," hexmask.long.byte 0xB4 27.--31. 1. "PRIORITY3,priority for interrupt ID = x * 4 + 3" hexmask.long.byte 0xB4 19.--23. 1. "PRIORITY2,priority for interrupt ID = x * 4 + 2" hexmask.long.byte 0xB4 11.--15. 1. "PRIORITY1,priority for interrupt ID = x * 4 + 1" newline hexmask.long.byte 0xB4 3.--7. 1. "PRIORITY0,priority for interrupt ID = x * 4" line.long 0xB8 "GICD_IPRIORITYR46," hexmask.long.byte 0xB8 27.--31. 1. "PRIORITY3,priority for interrupt ID = x * 4 + 3" hexmask.long.byte 0xB8 19.--23. 1. "PRIORITY2,priority for interrupt ID = x * 4 + 2" hexmask.long.byte 0xB8 11.--15. 1. "PRIORITY1,priority for interrupt ID = x * 4 + 1" newline hexmask.long.byte 0xB8 3.--7. 1. "PRIORITY0,priority for interrupt ID = x * 4" line.long 0xBC "GICD_IPRIORITYR47," hexmask.long.byte 0xBC 27.--31. 1. "PRIORITY3,priority for interrupt ID = x * 4 + 3" hexmask.long.byte 0xBC 19.--23. 1. "PRIORITY2,priority for interrupt ID = x * 4 + 2" hexmask.long.byte 0xBC 11.--15. 1. "PRIORITY1,priority for interrupt ID = x * 4 + 1" newline hexmask.long.byte 0xBC 3.--7. 1. "PRIORITY0,priority for interrupt ID = x * 4" rgroup.long 0x800++0x1F line.long 0x0 "GICD_ITARGETSR0,GICD interrupt processor target register 0" bitfld.long 0x0 24.--25. "CPU_TARGETS3,CPU(s) target for interrupt ID = x * 4 + 3" "0,1,2,3" bitfld.long 0x0 16.--17. "CPU_TARGETS2,CPU(s) target for interrupt ID = x * 4 + 2" "0,1,2,3" bitfld.long 0x0 8.--9. "CPU_TARGETS1,CPU(s) target for interrupt ID = x * 4 + 1" "0,1,2,3" newline bitfld.long 0x0 0.--1. "CPU_TARGETS0,CPU(s) target for interrupt ID = x * 4" "0,1,2,3" line.long 0x4 "GICD_ITARGETSR1,GICD interrupt processor target register 1" bitfld.long 0x4 24.--25. "CPU_TARGETS3,CPU(s) target for interrupt ID = x * 4 + 3" "0,1,2,3" bitfld.long 0x4 16.--17. "CPU_TARGETS2,CPU(s) target for interrupt ID = x * 4 + 2" "0,1,2,3" bitfld.long 0x4 8.--9. "CPU_TARGETS1,CPU(s) target for interrupt ID = x * 4 + 1" "0,1,2,3" newline bitfld.long 0x4 0.--1. "CPU_TARGETS0,CPU(s) target for interrupt ID = x * 4" "0,1,2,3" line.long 0x8 "GICD_ITARGETSR2,GICD interrupt processor target register 2" bitfld.long 0x8 24.--25. "CPU_TARGETS3,CPU(s) target for interrupt ID = x * 4 + 3" "0,1,2,3" bitfld.long 0x8 16.--17. "CPU_TARGETS2,CPU(s) target for interrupt ID = x * 4 + 2" "0,1,2,3" bitfld.long 0x8 8.--9. "CPU_TARGETS1,CPU(s) target for interrupt ID = x * 4 + 1" "0,1,2,3" newline bitfld.long 0x8 0.--1. "CPU_TARGETS0,CPU(s) target for interrupt ID = x * 4" "0,1,2,3" line.long 0xC "GICD_ITARGETSR3,GICD interrupt processor target register 3" bitfld.long 0xC 24.--25. "CPU_TARGETS3,CPU(s) target for interrupt ID = x * 4 + 3" "0,1,2,3" bitfld.long 0xC 16.--17. "CPU_TARGETS2,CPU(s) target for interrupt ID = x * 4 + 2" "0,1,2,3" bitfld.long 0xC 8.--9. "CPU_TARGETS1,CPU(s) target for interrupt ID = x * 4 + 1" "0,1,2,3" newline bitfld.long 0xC 0.--1. "CPU_TARGETS0,CPU(s) target for interrupt ID = x * 4" "0,1,2,3" line.long 0x10 "GICD_ITARGETSR4,GICD interrupt processor target register 4" bitfld.long 0x10 24.--25. "CPU_TARGETS3,CPU(s) target for interrupt ID = x * 4 + 3" "0,1,2,3" bitfld.long 0x10 16.--17. "CPU_TARGETS2,CPU(s) target for interrupt ID = x * 4 + 2" "0,1,2,3" bitfld.long 0x10 8.--9. "CPU_TARGETS1,CPU(s) target for interrupt ID = x * 4 + 1" "0,1,2,3" newline bitfld.long 0x10 0.--1. "CPU_TARGETS0,CPU(s) target for interrupt ID = x * 4" "0,1,2,3" line.long 0x14 "GICD_ITARGETSR5,GICD interrupt processor target register 5" bitfld.long 0x14 24.--25. "CPU_TARGETS3,CPU(s) target for interrupt ID = x * 4 + 3" "0,1,2,3" bitfld.long 0x14 16.--17. "CPU_TARGETS2,CPU(s) target for interrupt ID = x * 4 + 2" "0,1,2,3" bitfld.long 0x14 8.--9. "CPU_TARGETS1,CPU(s) target for interrupt ID = x * 4 + 1" "0,1,2,3" newline bitfld.long 0x14 0.--1. "CPU_TARGETS0,CPU(s) target for interrupt ID = x * 4" "0,1,2,3" line.long 0x18 "GICD_ITARGETSR6,GICD interrupt processor target register 6" bitfld.long 0x18 24.--25. "CPU_TARGETS3,CPU(s) target for interrupt ID = x * 4 + 3" "0,1,2,3" bitfld.long 0x18 16.--17. "CPU_TARGETS2,CPU(s) target for interrupt ID = x * 4 + 2" "0,1,2,3" bitfld.long 0x18 8.--9. "CPU_TARGETS1,CPU(s) target for interrupt ID = x * 4 + 1" "0,1,2,3" newline bitfld.long 0x18 0.--1. "CPU_TARGETS0,CPU(s) target for interrupt ID = x * 4" "0,1,2,3" line.long 0x1C "GICD_ITARGETSR7,GICD interrupt processor target register 7" bitfld.long 0x1C 24.--25. "CPU_TARGETS3,CPU(s) target for interrupt ID = x * 4 + 3" "0,1,2,3" bitfld.long 0x1C 16.--17. "CPU_TARGETS2,CPU(s) target for interrupt ID = x * 4 + 2" "0,1,2,3" bitfld.long 0x1C 8.--9. "CPU_TARGETS1,CPU(s) target for interrupt ID = x * 4 + 1" "0,1,2,3" newline bitfld.long 0x1C 0.--1. "CPU_TARGETS0,CPU(s) target for interrupt ID = x * 4" "0,1,2,3" group.long 0x820++0x9F line.long 0x0 "GICD_ITARGETSR8," bitfld.long 0x0 24.--25. "CPU_TARGETS3,CPU(s) target for interrupt ID = x * 4 + 3" "0,1,2,3" bitfld.long 0x0 16.--17. "CPU_TARGETS2,CPU(s) target for interrupt ID = x * 4 + 2" "0,1,2,3" bitfld.long 0x0 8.--9. "CPU_TARGETS1,CPU(s) target for interrupt ID = x * 4 + 1" "0,1,2,3" newline bitfld.long 0x0 0.--1. "CPU_TARGETS0,CPU(s) target for interrupt ID = x * 4" "0,1,2,3" line.long 0x4 "GICD_ITARGETSR9," bitfld.long 0x4 24.--25. "CPU_TARGETS3,CPU(s) target for interrupt ID = x * 4 + 3" "0,1,2,3" bitfld.long 0x4 16.--17. "CPU_TARGETS2,CPU(s) target for interrupt ID = x * 4 + 2" "0,1,2,3" bitfld.long 0x4 8.--9. "CPU_TARGETS1,CPU(s) target for interrupt ID = x * 4 + 1" "0,1,2,3" newline bitfld.long 0x4 0.--1. "CPU_TARGETS0,CPU(s) target for interrupt ID = x * 4" "0,1,2,3" line.long 0x8 "GICD_ITARGETSR10," bitfld.long 0x8 24.--25. "CPU_TARGETS3,CPU(s) target for interrupt ID = x * 4 + 3" "0,1,2,3" bitfld.long 0x8 16.--17. "CPU_TARGETS2,CPU(s) target for interrupt ID = x * 4 + 2" "0,1,2,3" bitfld.long 0x8 8.--9. "CPU_TARGETS1,CPU(s) target for interrupt ID = x * 4 + 1" "0,1,2,3" newline bitfld.long 0x8 0.--1. "CPU_TARGETS0,CPU(s) target for interrupt ID = x * 4" "0,1,2,3" line.long 0xC "GICD_ITARGETSR11," bitfld.long 0xC 24.--25. "CPU_TARGETS3,CPU(s) target for interrupt ID = x * 4 + 3" "0,1,2,3" bitfld.long 0xC 16.--17. "CPU_TARGETS2,CPU(s) target for interrupt ID = x * 4 + 2" "0,1,2,3" bitfld.long 0xC 8.--9. "CPU_TARGETS1,CPU(s) target for interrupt ID = x * 4 + 1" "0,1,2,3" newline bitfld.long 0xC 0.--1. "CPU_TARGETS0,CPU(s) target for interrupt ID = x * 4" "0,1,2,3" line.long 0x10 "GICD_ITARGETSR12," bitfld.long 0x10 24.--25. "CPU_TARGETS3,CPU(s) target for interrupt ID = x * 4 + 3" "0,1,2,3" bitfld.long 0x10 16.--17. "CPU_TARGETS2,CPU(s) target for interrupt ID = x * 4 + 2" "0,1,2,3" bitfld.long 0x10 8.--9. "CPU_TARGETS1,CPU(s) target for interrupt ID = x * 4 + 1" "0,1,2,3" newline bitfld.long 0x10 0.--1. "CPU_TARGETS0,CPU(s) target for interrupt ID = x * 4" "0,1,2,3" line.long 0x14 "GICD_ITARGETSR13," bitfld.long 0x14 24.--25. "CPU_TARGETS3,CPU(s) target for interrupt ID = x * 4 + 3" "0,1,2,3" bitfld.long 0x14 16.--17. "CPU_TARGETS2,CPU(s) target for interrupt ID = x * 4 + 2" "0,1,2,3" bitfld.long 0x14 8.--9. "CPU_TARGETS1,CPU(s) target for interrupt ID = x * 4 + 1" "0,1,2,3" newline bitfld.long 0x14 0.--1. "CPU_TARGETS0,CPU(s) target for interrupt ID = x * 4" "0,1,2,3" line.long 0x18 "GICD_ITARGETSR14," bitfld.long 0x18 24.--25. "CPU_TARGETS3,CPU(s) target for interrupt ID = x * 4 + 3" "0,1,2,3" bitfld.long 0x18 16.--17. "CPU_TARGETS2,CPU(s) target for interrupt ID = x * 4 + 2" "0,1,2,3" bitfld.long 0x18 8.--9. "CPU_TARGETS1,CPU(s) target for interrupt ID = x * 4 + 1" "0,1,2,3" newline bitfld.long 0x18 0.--1. "CPU_TARGETS0,CPU(s) target for interrupt ID = x * 4" "0,1,2,3" line.long 0x1C "GICD_ITARGETSR15," bitfld.long 0x1C 24.--25. "CPU_TARGETS3,CPU(s) target for interrupt ID = x * 4 + 3" "0,1,2,3" bitfld.long 0x1C 16.--17. "CPU_TARGETS2,CPU(s) target for interrupt ID = x * 4 + 2" "0,1,2,3" bitfld.long 0x1C 8.--9. "CPU_TARGETS1,CPU(s) target for interrupt ID = x * 4 + 1" "0,1,2,3" newline bitfld.long 0x1C 0.--1. "CPU_TARGETS0,CPU(s) target for interrupt ID = x * 4" "0,1,2,3" line.long 0x20 "GICD_ITARGETSR16," bitfld.long 0x20 24.--25. "CPU_TARGETS3,CPU(s) target for interrupt ID = x * 4 + 3" "0,1,2,3" bitfld.long 0x20 16.--17. "CPU_TARGETS2,CPU(s) target for interrupt ID = x * 4 + 2" "0,1,2,3" bitfld.long 0x20 8.--9. "CPU_TARGETS1,CPU(s) target for interrupt ID = x * 4 + 1" "0,1,2,3" newline bitfld.long 0x20 0.--1. "CPU_TARGETS0,CPU(s) target for interrupt ID = x * 4" "0,1,2,3" line.long 0x24 "GICD_ITARGETSR17," bitfld.long 0x24 24.--25. "CPU_TARGETS3,CPU(s) target for interrupt ID = x * 4 + 3" "0,1,2,3" bitfld.long 0x24 16.--17. "CPU_TARGETS2,CPU(s) target for interrupt ID = x * 4 + 2" "0,1,2,3" bitfld.long 0x24 8.--9. "CPU_TARGETS1,CPU(s) target for interrupt ID = x * 4 + 1" "0,1,2,3" newline bitfld.long 0x24 0.--1. "CPU_TARGETS0,CPU(s) target for interrupt ID = x * 4" "0,1,2,3" line.long 0x28 "GICD_ITARGETSR18," bitfld.long 0x28 24.--25. "CPU_TARGETS3,CPU(s) target for interrupt ID = x * 4 + 3" "0,1,2,3" bitfld.long 0x28 16.--17. "CPU_TARGETS2,CPU(s) target for interrupt ID = x * 4 + 2" "0,1,2,3" bitfld.long 0x28 8.--9. "CPU_TARGETS1,CPU(s) target for interrupt ID = x * 4 + 1" "0,1,2,3" newline bitfld.long 0x28 0.--1. "CPU_TARGETS0,CPU(s) target for interrupt ID = x * 4" "0,1,2,3" line.long 0x2C "GICD_ITARGETSR19," bitfld.long 0x2C 24.--25. "CPU_TARGETS3,CPU(s) target for interrupt ID = x * 4 + 3" "0,1,2,3" bitfld.long 0x2C 16.--17. "CPU_TARGETS2,CPU(s) target for interrupt ID = x * 4 + 2" "0,1,2,3" bitfld.long 0x2C 8.--9. "CPU_TARGETS1,CPU(s) target for interrupt ID = x * 4 + 1" "0,1,2,3" newline bitfld.long 0x2C 0.--1. "CPU_TARGETS0,CPU(s) target for interrupt ID = x * 4" "0,1,2,3" line.long 0x30 "GICD_ITARGETSR20," bitfld.long 0x30 24.--25. "CPU_TARGETS3,CPU(s) target for interrupt ID = x * 4 + 3" "0,1,2,3" bitfld.long 0x30 16.--17. "CPU_TARGETS2,CPU(s) target for interrupt ID = x * 4 + 2" "0,1,2,3" bitfld.long 0x30 8.--9. "CPU_TARGETS1,CPU(s) target for interrupt ID = x * 4 + 1" "0,1,2,3" newline bitfld.long 0x30 0.--1. "CPU_TARGETS0,CPU(s) target for interrupt ID = x * 4" "0,1,2,3" line.long 0x34 "GICD_ITARGETSR21," bitfld.long 0x34 24.--25. "CPU_TARGETS3,CPU(s) target for interrupt ID = x * 4 + 3" "0,1,2,3" bitfld.long 0x34 16.--17. "CPU_TARGETS2,CPU(s) target for interrupt ID = x * 4 + 2" "0,1,2,3" bitfld.long 0x34 8.--9. "CPU_TARGETS1,CPU(s) target for interrupt ID = x * 4 + 1" "0,1,2,3" newline bitfld.long 0x34 0.--1. "CPU_TARGETS0,CPU(s) target for interrupt ID = x * 4" "0,1,2,3" line.long 0x38 "GICD_ITARGETSR22," bitfld.long 0x38 24.--25. "CPU_TARGETS3,CPU(s) target for interrupt ID = x * 4 + 3" "0,1,2,3" bitfld.long 0x38 16.--17. "CPU_TARGETS2,CPU(s) target for interrupt ID = x * 4 + 2" "0,1,2,3" bitfld.long 0x38 8.--9. "CPU_TARGETS1,CPU(s) target for interrupt ID = x * 4 + 1" "0,1,2,3" newline bitfld.long 0x38 0.--1. "CPU_TARGETS0,CPU(s) target for interrupt ID = x * 4" "0,1,2,3" line.long 0x3C "GICD_ITARGETSR23," bitfld.long 0x3C 24.--25. "CPU_TARGETS3,CPU(s) target for interrupt ID = x * 4 + 3" "0,1,2,3" bitfld.long 0x3C 16.--17. "CPU_TARGETS2,CPU(s) target for interrupt ID = x * 4 + 2" "0,1,2,3" bitfld.long 0x3C 8.--9. "CPU_TARGETS1,CPU(s) target for interrupt ID = x * 4 + 1" "0,1,2,3" newline bitfld.long 0x3C 0.--1. "CPU_TARGETS0,CPU(s) target for interrupt ID = x * 4" "0,1,2,3" line.long 0x40 "GICD_ITARGETSR24," bitfld.long 0x40 24.--25. "CPU_TARGETS3,CPU(s) target for interrupt ID = x * 4 + 3" "0,1,2,3" bitfld.long 0x40 16.--17. "CPU_TARGETS2,CPU(s) target for interrupt ID = x * 4 + 2" "0,1,2,3" bitfld.long 0x40 8.--9. "CPU_TARGETS1,CPU(s) target for interrupt ID = x * 4 + 1" "0,1,2,3" newline bitfld.long 0x40 0.--1. "CPU_TARGETS0,CPU(s) target for interrupt ID = x * 4" "0,1,2,3" line.long 0x44 "GICD_ITARGETSR25," bitfld.long 0x44 24.--25. "CPU_TARGETS3,CPU(s) target for interrupt ID = x * 4 + 3" "0,1,2,3" bitfld.long 0x44 16.--17. "CPU_TARGETS2,CPU(s) target for interrupt ID = x * 4 + 2" "0,1,2,3" bitfld.long 0x44 8.--9. "CPU_TARGETS1,CPU(s) target for interrupt ID = x * 4 + 1" "0,1,2,3" newline bitfld.long 0x44 0.--1. "CPU_TARGETS0,CPU(s) target for interrupt ID = x * 4" "0,1,2,3" line.long 0x48 "GICD_ITARGETSR26," bitfld.long 0x48 24.--25. "CPU_TARGETS3,CPU(s) target for interrupt ID = x * 4 + 3" "0,1,2,3" bitfld.long 0x48 16.--17. "CPU_TARGETS2,CPU(s) target for interrupt ID = x * 4 + 2" "0,1,2,3" bitfld.long 0x48 8.--9. "CPU_TARGETS1,CPU(s) target for interrupt ID = x * 4 + 1" "0,1,2,3" newline bitfld.long 0x48 0.--1. "CPU_TARGETS0,CPU(s) target for interrupt ID = x * 4" "0,1,2,3" line.long 0x4C "GICD_ITARGETSR27," bitfld.long 0x4C 24.--25. "CPU_TARGETS3,CPU(s) target for interrupt ID = x * 4 + 3" "0,1,2,3" bitfld.long 0x4C 16.--17. "CPU_TARGETS2,CPU(s) target for interrupt ID = x * 4 + 2" "0,1,2,3" bitfld.long 0x4C 8.--9. "CPU_TARGETS1,CPU(s) target for interrupt ID = x * 4 + 1" "0,1,2,3" newline bitfld.long 0x4C 0.--1. "CPU_TARGETS0,CPU(s) target for interrupt ID = x * 4" "0,1,2,3" line.long 0x50 "GICD_ITARGETSR28," bitfld.long 0x50 24.--25. "CPU_TARGETS3,CPU(s) target for interrupt ID = x * 4 + 3" "0,1,2,3" bitfld.long 0x50 16.--17. "CPU_TARGETS2,CPU(s) target for interrupt ID = x * 4 + 2" "0,1,2,3" bitfld.long 0x50 8.--9. "CPU_TARGETS1,CPU(s) target for interrupt ID = x * 4 + 1" "0,1,2,3" newline bitfld.long 0x50 0.--1. "CPU_TARGETS0,CPU(s) target for interrupt ID = x * 4" "0,1,2,3" line.long 0x54 "GICD_ITARGETSR29," bitfld.long 0x54 24.--25. "CPU_TARGETS3,CPU(s) target for interrupt ID = x * 4 + 3" "0,1,2,3" bitfld.long 0x54 16.--17. "CPU_TARGETS2,CPU(s) target for interrupt ID = x * 4 + 2" "0,1,2,3" bitfld.long 0x54 8.--9. "CPU_TARGETS1,CPU(s) target for interrupt ID = x * 4 + 1" "0,1,2,3" newline bitfld.long 0x54 0.--1. "CPU_TARGETS0,CPU(s) target for interrupt ID = x * 4" "0,1,2,3" line.long 0x58 "GICD_ITARGETSR30," bitfld.long 0x58 24.--25. "CPU_TARGETS3,CPU(s) target for interrupt ID = x * 4 + 3" "0,1,2,3" bitfld.long 0x58 16.--17. "CPU_TARGETS2,CPU(s) target for interrupt ID = x * 4 + 2" "0,1,2,3" bitfld.long 0x58 8.--9. "CPU_TARGETS1,CPU(s) target for interrupt ID = x * 4 + 1" "0,1,2,3" newline bitfld.long 0x58 0.--1. "CPU_TARGETS0,CPU(s) target for interrupt ID = x * 4" "0,1,2,3" line.long 0x5C "GICD_ITARGETSR31," bitfld.long 0x5C 24.--25. "CPU_TARGETS3,CPU(s) target for interrupt ID = x * 4 + 3" "0,1,2,3" bitfld.long 0x5C 16.--17. "CPU_TARGETS2,CPU(s) target for interrupt ID = x * 4 + 2" "0,1,2,3" bitfld.long 0x5C 8.--9. "CPU_TARGETS1,CPU(s) target for interrupt ID = x * 4 + 1" "0,1,2,3" newline bitfld.long 0x5C 0.--1. "CPU_TARGETS0,CPU(s) target for interrupt ID = x * 4" "0,1,2,3" line.long 0x60 "GICD_ITARGETSR32," bitfld.long 0x60 24.--25. "CPU_TARGETS3,CPU(s) target for interrupt ID = x * 4 + 3" "0,1,2,3" bitfld.long 0x60 16.--17. "CPU_TARGETS2,CPU(s) target for interrupt ID = x * 4 + 2" "0,1,2,3" bitfld.long 0x60 8.--9. "CPU_TARGETS1,CPU(s) target for interrupt ID = x * 4 + 1" "0,1,2,3" newline bitfld.long 0x60 0.--1. "CPU_TARGETS0,CPU(s) target for interrupt ID = x * 4" "0,1,2,3" line.long 0x64 "GICD_ITARGETSR33," bitfld.long 0x64 24.--25. "CPU_TARGETS3,CPU(s) target for interrupt ID = x * 4 + 3" "0,1,2,3" bitfld.long 0x64 16.--17. "CPU_TARGETS2,CPU(s) target for interrupt ID = x * 4 + 2" "0,1,2,3" bitfld.long 0x64 8.--9. "CPU_TARGETS1,CPU(s) target for interrupt ID = x * 4 + 1" "0,1,2,3" newline bitfld.long 0x64 0.--1. "CPU_TARGETS0,CPU(s) target for interrupt ID = x * 4" "0,1,2,3" line.long 0x68 "GICD_ITARGETSR34," bitfld.long 0x68 24.--25. "CPU_TARGETS3,CPU(s) target for interrupt ID = x * 4 + 3" "0,1,2,3" bitfld.long 0x68 16.--17. "CPU_TARGETS2,CPU(s) target for interrupt ID = x * 4 + 2" "0,1,2,3" bitfld.long 0x68 8.--9. "CPU_TARGETS1,CPU(s) target for interrupt ID = x * 4 + 1" "0,1,2,3" newline bitfld.long 0x68 0.--1. "CPU_TARGETS0,CPU(s) target for interrupt ID = x * 4" "0,1,2,3" line.long 0x6C "GICD_ITARGETSR35," bitfld.long 0x6C 24.--25. "CPU_TARGETS3,CPU(s) target for interrupt ID = x * 4 + 3" "0,1,2,3" bitfld.long 0x6C 16.--17. "CPU_TARGETS2,CPU(s) target for interrupt ID = x * 4 + 2" "0,1,2,3" bitfld.long 0x6C 8.--9. "CPU_TARGETS1,CPU(s) target for interrupt ID = x * 4 + 1" "0,1,2,3" newline bitfld.long 0x6C 0.--1. "CPU_TARGETS0,CPU(s) target for interrupt ID = x * 4" "0,1,2,3" line.long 0x70 "GICD_ITARGETSR36," bitfld.long 0x70 24.--25. "CPU_TARGETS3,CPU(s) target for interrupt ID = x * 4 + 3" "0,1,2,3" bitfld.long 0x70 16.--17. "CPU_TARGETS2,CPU(s) target for interrupt ID = x * 4 + 2" "0,1,2,3" bitfld.long 0x70 8.--9. "CPU_TARGETS1,CPU(s) target for interrupt ID = x * 4 + 1" "0,1,2,3" newline bitfld.long 0x70 0.--1. "CPU_TARGETS0,CPU(s) target for interrupt ID = x * 4" "0,1,2,3" line.long 0x74 "GICD_ITARGETSR37," bitfld.long 0x74 24.--25. "CPU_TARGETS3,CPU(s) target for interrupt ID = x * 4 + 3" "0,1,2,3" bitfld.long 0x74 16.--17. "CPU_TARGETS2,CPU(s) target for interrupt ID = x * 4 + 2" "0,1,2,3" bitfld.long 0x74 8.--9. "CPU_TARGETS1,CPU(s) target for interrupt ID = x * 4 + 1" "0,1,2,3" newline bitfld.long 0x74 0.--1. "CPU_TARGETS0,CPU(s) target for interrupt ID = x * 4" "0,1,2,3" line.long 0x78 "GICD_ITARGETSR38," bitfld.long 0x78 24.--25. "CPU_TARGETS3,CPU(s) target for interrupt ID = x * 4 + 3" "0,1,2,3" bitfld.long 0x78 16.--17. "CPU_TARGETS2,CPU(s) target for interrupt ID = x * 4 + 2" "0,1,2,3" bitfld.long 0x78 8.--9. "CPU_TARGETS1,CPU(s) target for interrupt ID = x * 4 + 1" "0,1,2,3" newline bitfld.long 0x78 0.--1. "CPU_TARGETS0,CPU(s) target for interrupt ID = x * 4" "0,1,2,3" line.long 0x7C "GICD_ITARGETSR39," bitfld.long 0x7C 24.--25. "CPU_TARGETS3,CPU(s) target for interrupt ID = x * 4 + 3" "0,1,2,3" bitfld.long 0x7C 16.--17. "CPU_TARGETS2,CPU(s) target for interrupt ID = x * 4 + 2" "0,1,2,3" bitfld.long 0x7C 8.--9. "CPU_TARGETS1,CPU(s) target for interrupt ID = x * 4 + 1" "0,1,2,3" newline bitfld.long 0x7C 0.--1. "CPU_TARGETS0,CPU(s) target for interrupt ID = x * 4" "0,1,2,3" line.long 0x80 "GICD_ITARGETSR40," bitfld.long 0x80 24.--25. "CPU_TARGETS3,CPU(s) target for interrupt ID = x * 4 + 3" "0,1,2,3" bitfld.long 0x80 16.--17. "CPU_TARGETS2,CPU(s) target for interrupt ID = x * 4 + 2" "0,1,2,3" bitfld.long 0x80 8.--9. "CPU_TARGETS1,CPU(s) target for interrupt ID = x * 4 + 1" "0,1,2,3" newline bitfld.long 0x80 0.--1. "CPU_TARGETS0,CPU(s) target for interrupt ID = x * 4" "0,1,2,3" line.long 0x84 "GICD_ITARGETSR41," bitfld.long 0x84 24.--25. "CPU_TARGETS3,CPU(s) target for interrupt ID = x * 4 + 3" "0,1,2,3" bitfld.long 0x84 16.--17. "CPU_TARGETS2,CPU(s) target for interrupt ID = x * 4 + 2" "0,1,2,3" bitfld.long 0x84 8.--9. "CPU_TARGETS1,CPU(s) target for interrupt ID = x * 4 + 1" "0,1,2,3" newline bitfld.long 0x84 0.--1. "CPU_TARGETS0,CPU(s) target for interrupt ID = x * 4" "0,1,2,3" line.long 0x88 "GICD_ITARGETSR42," bitfld.long 0x88 24.--25. "CPU_TARGETS3,CPU(s) target for interrupt ID = x * 4 + 3" "0,1,2,3" bitfld.long 0x88 16.--17. "CPU_TARGETS2,CPU(s) target for interrupt ID = x * 4 + 2" "0,1,2,3" bitfld.long 0x88 8.--9. "CPU_TARGETS1,CPU(s) target for interrupt ID = x * 4 + 1" "0,1,2,3" newline bitfld.long 0x88 0.--1. "CPU_TARGETS0,CPU(s) target for interrupt ID = x * 4" "0,1,2,3" line.long 0x8C "GICD_ITARGETSR43," bitfld.long 0x8C 24.--25. "CPU_TARGETS3,CPU(s) target for interrupt ID = x * 4 + 3" "0,1,2,3" bitfld.long 0x8C 16.--17. "CPU_TARGETS2,CPU(s) target for interrupt ID = x * 4 + 2" "0,1,2,3" bitfld.long 0x8C 8.--9. "CPU_TARGETS1,CPU(s) target for interrupt ID = x * 4 + 1" "0,1,2,3" newline bitfld.long 0x8C 0.--1. "CPU_TARGETS0,CPU(s) target for interrupt ID = x * 4" "0,1,2,3" line.long 0x90 "GICD_ITARGETSR44," bitfld.long 0x90 24.--25. "CPU_TARGETS3,CPU(s) target for interrupt ID = x * 4 + 3" "0,1,2,3" bitfld.long 0x90 16.--17. "CPU_TARGETS2,CPU(s) target for interrupt ID = x * 4 + 2" "0,1,2,3" bitfld.long 0x90 8.--9. "CPU_TARGETS1,CPU(s) target for interrupt ID = x * 4 + 1" "0,1,2,3" newline bitfld.long 0x90 0.--1. "CPU_TARGETS0,CPU(s) target for interrupt ID = x * 4" "0,1,2,3" line.long 0x94 "GICD_ITARGETSR45," bitfld.long 0x94 24.--25. "CPU_TARGETS3,CPU(s) target for interrupt ID = x * 4 + 3" "0,1,2,3" bitfld.long 0x94 16.--17. "CPU_TARGETS2,CPU(s) target for interrupt ID = x * 4 + 2" "0,1,2,3" bitfld.long 0x94 8.--9. "CPU_TARGETS1,CPU(s) target for interrupt ID = x * 4 + 1" "0,1,2,3" newline bitfld.long 0x94 0.--1. "CPU_TARGETS0,CPU(s) target for interrupt ID = x * 4" "0,1,2,3" line.long 0x98 "GICD_ITARGETSR46," bitfld.long 0x98 24.--25. "CPU_TARGETS3,CPU(s) target for interrupt ID = x * 4 + 3" "0,1,2,3" bitfld.long 0x98 16.--17. "CPU_TARGETS2,CPU(s) target for interrupt ID = x * 4 + 2" "0,1,2,3" bitfld.long 0x98 8.--9. "CPU_TARGETS1,CPU(s) target for interrupt ID = x * 4 + 1" "0,1,2,3" newline bitfld.long 0x98 0.--1. "CPU_TARGETS0,CPU(s) target for interrupt ID = x * 4" "0,1,2,3" line.long 0x9C "GICD_ITARGETSR47," bitfld.long 0x9C 24.--25. "CPU_TARGETS3,CPU(s) target for interrupt ID = x * 4 + 3" "0,1,2,3" bitfld.long 0x9C 16.--17. "CPU_TARGETS2,CPU(s) target for interrupt ID = x * 4 + 2" "0,1,2,3" bitfld.long 0x9C 8.--9. "CPU_TARGETS1,CPU(s) target for interrupt ID = x * 4 + 1" "0,1,2,3" newline bitfld.long 0x9C 0.--1. "CPU_TARGETS0,CPU(s) target for interrupt ID = x * 4" "0,1,2,3" group.long 0xC00++0x2F line.long 0x0 "GICD_ICFGR0," bitfld.long 0x0 30.--31. "INT_CONFIG15,interrupt config for interrupt ID = 15" "0,1,2,3" bitfld.long 0x0 28.--29. "INT_CONFIG14,interrupt config for interrupt ID = 14" "0,1,2,3" bitfld.long 0x0 26.--27. "INT_CONFIG13,interrupt config for interrupt ID = 13" "0,1,2,3" newline bitfld.long 0x0 24.--25. "INT_CONFIG12,interrupt config for interrupt ID = 12" "0,1,2,3" bitfld.long 0x0 22.--23. "INT_CONFIG11,interrupt config for interrupt ID = 11" "0,1,2,3" bitfld.long 0x0 20.--21. "INT_CONFIG10,interrupt config for interrupt ID = 10" "0,1,2,3" newline bitfld.long 0x0 18.--19. "INT_CONFIG9,interrupt config for interrupt ID = 9" "0,1,2,3" bitfld.long 0x0 16.--17. "INT_CONFIG8,interrupt config for interrupt ID = 8" "0,1,2,3" bitfld.long 0x0 14.--15. "INT_CONFIG7,interrupt config for interrupt ID = 7" "0,1,2,3" newline bitfld.long 0x0 12.--13. "INT_CONFIG6,interrupt config for interrupt ID = 6" "0,1,2,3" bitfld.long 0x0 10.--11. "INT_CONFIG5,interrupt config for interrupt ID = 5" "0,1,2,3" bitfld.long 0x0 8.--9. "INT_CONFIG4,interrupt config for interrupt ID = 4" "0,1,2,3" newline bitfld.long 0x0 6.--7. "INT_CONFIG3,interrupt config for interrupt ID = 3" "0,1,2,3" bitfld.long 0x0 4.--5. "INT_CONFIG2,interrupt config for interrupt ID = 2" "0,1,2,3" bitfld.long 0x0 2.--3. "INT_CONFIG1,interrupt config for interrupt ID = 1" "0,1,2,3" newline bitfld.long 0x0 0.--1. "INT_CONFIG0,interrupt config for interrupt ID = 0" "0,1,2,3" line.long 0x4 "GICD_ICFGR1,GICD interrupt configuration register" bitfld.long 0x4 30.--31. "INT_CONFIG15,interrupt config for interrupt ID = 31" "0,1,2,3" bitfld.long 0x4 28.--29. "INT_CONFIG14,interrupt config for interrupt ID = 30" "0,1,2,3" bitfld.long 0x4 26.--27. "INT_CONFIG13,interrupt config for interrupt ID = 29" "0,1,2,3" newline bitfld.long 0x4 24.--25. "INT_CONFIG12,interrupt config for interrupt ID = 28" "0,1,2,3" bitfld.long 0x4 22.--23. "INT_CONFIG11,interrupt config for interrupt ID = 27" "0,1,2,3" bitfld.long 0x4 20.--21. "INT_CONFIG10,interrupt config for interrupt ID = 26" "0,1,2,3" newline bitfld.long 0x4 18.--19. "INT_CONFIG9,interrupt config for interrupt ID = 25" "0,1,2,3" bitfld.long 0x4 16.--17. "INT_CONFIG8,interrupt config for interrupt ID = 24" "0,1,2,3" bitfld.long 0x4 14.--15. "INT_CONFIG7,interrupt config for interrupt ID = 23" "0,1,2,3" newline bitfld.long 0x4 12.--13. "INT_CONFIG6,interrupt config for interrupt ID = 22" "0,1,2,3" bitfld.long 0x4 10.--11. "INT_CONFIG5,interrupt config for interrupt ID = 21" "0,1,2,3" bitfld.long 0x4 8.--9. "INT_CONFIG4,interrupt config for interrupt ID = 20" "0,1,2,3" newline bitfld.long 0x4 6.--7. "INT_CONFIG3,interrupt config for interrupt ID = 19" "0,1,2,3" bitfld.long 0x4 4.--5. "INT_CONFIG2,interrupt config for interrupt ID = 18" "0,1,2,3" bitfld.long 0x4 2.--3. "INT_CONFIG1,interrupt config for interrupt ID = 17" "0,1,2,3" newline bitfld.long 0x4 0.--1. "INT_CONFIG0,interrupt config for interrupt ID = 16" "0,1,2,3" line.long 0x8 "GICD_ICFGR2," bitfld.long 0x8 30.--31. "INT_CONFIG15,interrupt config for interrupt ID = x * 16 + 15" "0,1,2,3" bitfld.long 0x8 28.--29. "INT_CONFIG14,interrupt config for interrupt ID = x * 16 + 14" "0,1,2,3" bitfld.long 0x8 26.--27. "INT_CONFIG13,interrupt config for interrupt ID = x * 16 + 13" "0,1,2,3" newline bitfld.long 0x8 24.--25. "INT_CONFIG12,interrupt config for interrupt ID = x * 16 + 12" "0,1,2,3" bitfld.long 0x8 22.--23. "INT_CONFIG11,interrupt config for interrupt ID = x * 16 + 11" "0,1,2,3" bitfld.long 0x8 20.--21. "INT_CONFIG10,interrupt config for interrupt ID = x * 16 + 10" "0,1,2,3" newline bitfld.long 0x8 18.--19. "INT_CONFIG9,interrupt config for interrupt ID = x * 16 + 9" "0,1,2,3" bitfld.long 0x8 16.--17. "INT_CONFIG8,interrupt config for interrupt ID = x * 16 + 8" "0,1,2,3" bitfld.long 0x8 14.--15. "INT_CONFIG7,interrupt config for interrupt ID = x * 16 + 7" "0,1,2,3" newline bitfld.long 0x8 12.--13. "INT_CONFIG6,interrupt config for interrupt ID = x * 16 + 6" "0,1,2,3" bitfld.long 0x8 10.--11. "INT_CONFIG5,interrupt config for interrupt ID = x * 16 + 5" "0,1,2,3" bitfld.long 0x8 8.--9. "INT_CONFIG4,interrupt config for interrupt ID = x * 16 + 4" "0,1,2,3" newline bitfld.long 0x8 6.--7. "INT_CONFIG3,interrupt config for interrupt ID = x * 16 + 3" "0,1,2,3" bitfld.long 0x8 4.--5. "INT_CONFIG2,interrupt config for interrupt ID = x * 16 + 2" "0,1,2,3" bitfld.long 0x8 2.--3. "INT_CONFIG1,interrupt config for interrupt ID = x * 16 + 1" "0,1,2,3" newline bitfld.long 0x8 0.--1. "INT_CONFIG0,interrupt config for interrupt ID = x * 16" "0,1,2,3" line.long 0xC "GICD_ICFGR3," bitfld.long 0xC 30.--31. "INT_CONFIG15,interrupt config for interrupt ID = x * 16 + 15" "0,1,2,3" bitfld.long 0xC 28.--29. "INT_CONFIG14,interrupt config for interrupt ID = x * 16 + 14" "0,1,2,3" bitfld.long 0xC 26.--27. "INT_CONFIG13,interrupt config for interrupt ID = x * 16 + 13" "0,1,2,3" newline bitfld.long 0xC 24.--25. "INT_CONFIG12,interrupt config for interrupt ID = x * 16 + 12" "0,1,2,3" bitfld.long 0xC 22.--23. "INT_CONFIG11,interrupt config for interrupt ID = x * 16 + 11" "0,1,2,3" bitfld.long 0xC 20.--21. "INT_CONFIG10,interrupt config for interrupt ID = x * 16 + 10" "0,1,2,3" newline bitfld.long 0xC 18.--19. "INT_CONFIG9,interrupt config for interrupt ID = x * 16 + 9" "0,1,2,3" bitfld.long 0xC 16.--17. "INT_CONFIG8,interrupt config for interrupt ID = x * 16 + 8" "0,1,2,3" bitfld.long 0xC 14.--15. "INT_CONFIG7,interrupt config for interrupt ID = x * 16 + 7" "0,1,2,3" newline bitfld.long 0xC 12.--13. "INT_CONFIG6,interrupt config for interrupt ID = x * 16 + 6" "0,1,2,3" bitfld.long 0xC 10.--11. "INT_CONFIG5,interrupt config for interrupt ID = x * 16 + 5" "0,1,2,3" bitfld.long 0xC 8.--9. "INT_CONFIG4,interrupt config for interrupt ID = x * 16 + 4" "0,1,2,3" newline bitfld.long 0xC 6.--7. "INT_CONFIG3,interrupt config for interrupt ID = x * 16 + 3" "0,1,2,3" bitfld.long 0xC 4.--5. "INT_CONFIG2,interrupt config for interrupt ID = x * 16 + 2" "0,1,2,3" bitfld.long 0xC 2.--3. "INT_CONFIG1,interrupt config for interrupt ID = x * 16 + 1" "0,1,2,3" newline bitfld.long 0xC 0.--1. "INT_CONFIG0,interrupt config for interrupt ID = x * 16" "0,1,2,3" line.long 0x10 "GICD_ICFGR4," bitfld.long 0x10 30.--31. "INT_CONFIG15,interrupt config for interrupt ID = x * 16 + 15" "0,1,2,3" bitfld.long 0x10 28.--29. "INT_CONFIG14,interrupt config for interrupt ID = x * 16 + 14" "0,1,2,3" bitfld.long 0x10 26.--27. "INT_CONFIG13,interrupt config for interrupt ID = x * 16 + 13" "0,1,2,3" newline bitfld.long 0x10 24.--25. "INT_CONFIG12,interrupt config for interrupt ID = x * 16 + 12" "0,1,2,3" bitfld.long 0x10 22.--23. "INT_CONFIG11,interrupt config for interrupt ID = x * 16 + 11" "0,1,2,3" bitfld.long 0x10 20.--21. "INT_CONFIG10,interrupt config for interrupt ID = x * 16 + 10" "0,1,2,3" newline bitfld.long 0x10 18.--19. "INT_CONFIG9,interrupt config for interrupt ID = x * 16 + 9" "0,1,2,3" bitfld.long 0x10 16.--17. "INT_CONFIG8,interrupt config for interrupt ID = x * 16 + 8" "0,1,2,3" bitfld.long 0x10 14.--15. "INT_CONFIG7,interrupt config for interrupt ID = x * 16 + 7" "0,1,2,3" newline bitfld.long 0x10 12.--13. "INT_CONFIG6,interrupt config for interrupt ID = x * 16 + 6" "0,1,2,3" bitfld.long 0x10 10.--11. "INT_CONFIG5,interrupt config for interrupt ID = x * 16 + 5" "0,1,2,3" bitfld.long 0x10 8.--9. "INT_CONFIG4,interrupt config for interrupt ID = x * 16 + 4" "0,1,2,3" newline bitfld.long 0x10 6.--7. "INT_CONFIG3,interrupt config for interrupt ID = x * 16 + 3" "0,1,2,3" bitfld.long 0x10 4.--5. "INT_CONFIG2,interrupt config for interrupt ID = x * 16 + 2" "0,1,2,3" bitfld.long 0x10 2.--3. "INT_CONFIG1,interrupt config for interrupt ID = x * 16 + 1" "0,1,2,3" newline bitfld.long 0x10 0.--1. "INT_CONFIG0,interrupt config for interrupt ID = x * 16" "0,1,2,3" line.long 0x14 "GICD_ICFGR5," bitfld.long 0x14 30.--31. "INT_CONFIG15,interrupt config for interrupt ID = x * 16 + 15" "0,1,2,3" bitfld.long 0x14 28.--29. "INT_CONFIG14,interrupt config for interrupt ID = x * 16 + 14" "0,1,2,3" bitfld.long 0x14 26.--27. "INT_CONFIG13,interrupt config for interrupt ID = x * 16 + 13" "0,1,2,3" newline bitfld.long 0x14 24.--25. "INT_CONFIG12,interrupt config for interrupt ID = x * 16 + 12" "0,1,2,3" bitfld.long 0x14 22.--23. "INT_CONFIG11,interrupt config for interrupt ID = x * 16 + 11" "0,1,2,3" bitfld.long 0x14 20.--21. "INT_CONFIG10,interrupt config for interrupt ID = x * 16 + 10" "0,1,2,3" newline bitfld.long 0x14 18.--19. "INT_CONFIG9,interrupt config for interrupt ID = x * 16 + 9" "0,1,2,3" bitfld.long 0x14 16.--17. "INT_CONFIG8,interrupt config for interrupt ID = x * 16 + 8" "0,1,2,3" bitfld.long 0x14 14.--15. "INT_CONFIG7,interrupt config for interrupt ID = x * 16 + 7" "0,1,2,3" newline bitfld.long 0x14 12.--13. "INT_CONFIG6,interrupt config for interrupt ID = x * 16 + 6" "0,1,2,3" bitfld.long 0x14 10.--11. "INT_CONFIG5,interrupt config for interrupt ID = x * 16 + 5" "0,1,2,3" bitfld.long 0x14 8.--9. "INT_CONFIG4,interrupt config for interrupt ID = x * 16 + 4" "0,1,2,3" newline bitfld.long 0x14 6.--7. "INT_CONFIG3,interrupt config for interrupt ID = x * 16 + 3" "0,1,2,3" bitfld.long 0x14 4.--5. "INT_CONFIG2,interrupt config for interrupt ID = x * 16 + 2" "0,1,2,3" bitfld.long 0x14 2.--3. "INT_CONFIG1,interrupt config for interrupt ID = x * 16 + 1" "0,1,2,3" newline bitfld.long 0x14 0.--1. "INT_CONFIG0,interrupt config for interrupt ID = x * 16" "0,1,2,3" line.long 0x18 "GICD_ICFGR6," bitfld.long 0x18 30.--31. "INT_CONFIG15,interrupt config for interrupt ID = x * 16 + 15" "0,1,2,3" bitfld.long 0x18 28.--29. "INT_CONFIG14,interrupt config for interrupt ID = x * 16 + 14" "0,1,2,3" bitfld.long 0x18 26.--27. "INT_CONFIG13,interrupt config for interrupt ID = x * 16 + 13" "0,1,2,3" newline bitfld.long 0x18 24.--25. "INT_CONFIG12,interrupt config for interrupt ID = x * 16 + 12" "0,1,2,3" bitfld.long 0x18 22.--23. "INT_CONFIG11,interrupt config for interrupt ID = x * 16 + 11" "0,1,2,3" bitfld.long 0x18 20.--21. "INT_CONFIG10,interrupt config for interrupt ID = x * 16 + 10" "0,1,2,3" newline bitfld.long 0x18 18.--19. "INT_CONFIG9,interrupt config for interrupt ID = x * 16 + 9" "0,1,2,3" bitfld.long 0x18 16.--17. "INT_CONFIG8,interrupt config for interrupt ID = x * 16 + 8" "0,1,2,3" bitfld.long 0x18 14.--15. "INT_CONFIG7,interrupt config for interrupt ID = x * 16 + 7" "0,1,2,3" newline bitfld.long 0x18 12.--13. "INT_CONFIG6,interrupt config for interrupt ID = x * 16 + 6" "0,1,2,3" bitfld.long 0x18 10.--11. "INT_CONFIG5,interrupt config for interrupt ID = x * 16 + 5" "0,1,2,3" bitfld.long 0x18 8.--9. "INT_CONFIG4,interrupt config for interrupt ID = x * 16 + 4" "0,1,2,3" newline bitfld.long 0x18 6.--7. "INT_CONFIG3,interrupt config for interrupt ID = x * 16 + 3" "0,1,2,3" bitfld.long 0x18 4.--5. "INT_CONFIG2,interrupt config for interrupt ID = x * 16 + 2" "0,1,2,3" bitfld.long 0x18 2.--3. "INT_CONFIG1,interrupt config for interrupt ID = x * 16 + 1" "0,1,2,3" newline bitfld.long 0x18 0.--1. "INT_CONFIG0,interrupt config for interrupt ID = x * 16" "0,1,2,3" line.long 0x1C "GICD_ICFGR7," bitfld.long 0x1C 30.--31. "INT_CONFIG15,interrupt config for interrupt ID = x * 16 + 15" "0,1,2,3" bitfld.long 0x1C 28.--29. "INT_CONFIG14,interrupt config for interrupt ID = x * 16 + 14" "0,1,2,3" bitfld.long 0x1C 26.--27. "INT_CONFIG13,interrupt config for interrupt ID = x * 16 + 13" "0,1,2,3" newline bitfld.long 0x1C 24.--25. "INT_CONFIG12,interrupt config for interrupt ID = x * 16 + 12" "0,1,2,3" bitfld.long 0x1C 22.--23. "INT_CONFIG11,interrupt config for interrupt ID = x * 16 + 11" "0,1,2,3" bitfld.long 0x1C 20.--21. "INT_CONFIG10,interrupt config for interrupt ID = x * 16 + 10" "0,1,2,3" newline bitfld.long 0x1C 18.--19. "INT_CONFIG9,interrupt config for interrupt ID = x * 16 + 9" "0,1,2,3" bitfld.long 0x1C 16.--17. "INT_CONFIG8,interrupt config for interrupt ID = x * 16 + 8" "0,1,2,3" bitfld.long 0x1C 14.--15. "INT_CONFIG7,interrupt config for interrupt ID = x * 16 + 7" "0,1,2,3" newline bitfld.long 0x1C 12.--13. "INT_CONFIG6,interrupt config for interrupt ID = x * 16 + 6" "0,1,2,3" bitfld.long 0x1C 10.--11. "INT_CONFIG5,interrupt config for interrupt ID = x * 16 + 5" "0,1,2,3" bitfld.long 0x1C 8.--9. "INT_CONFIG4,interrupt config for interrupt ID = x * 16 + 4" "0,1,2,3" newline bitfld.long 0x1C 6.--7. "INT_CONFIG3,interrupt config for interrupt ID = x * 16 + 3" "0,1,2,3" bitfld.long 0x1C 4.--5. "INT_CONFIG2,interrupt config for interrupt ID = x * 16 + 2" "0,1,2,3" bitfld.long 0x1C 2.--3. "INT_CONFIG1,interrupt config for interrupt ID = x * 16 + 1" "0,1,2,3" newline bitfld.long 0x1C 0.--1. "INT_CONFIG0,interrupt config for interrupt ID = x * 16" "0,1,2,3" line.long 0x20 "GICD_ICFGR8," bitfld.long 0x20 30.--31. "INT_CONFIG15,interrupt config for interrupt ID = x * 16 + 15" "0,1,2,3" bitfld.long 0x20 28.--29. "INT_CONFIG14,interrupt config for interrupt ID = x * 16 + 14" "0,1,2,3" bitfld.long 0x20 26.--27. "INT_CONFIG13,interrupt config for interrupt ID = x * 16 + 13" "0,1,2,3" newline bitfld.long 0x20 24.--25. "INT_CONFIG12,interrupt config for interrupt ID = x * 16 + 12" "0,1,2,3" bitfld.long 0x20 22.--23. "INT_CONFIG11,interrupt config for interrupt ID = x * 16 + 11" "0,1,2,3" bitfld.long 0x20 20.--21. "INT_CONFIG10,interrupt config for interrupt ID = x * 16 + 10" "0,1,2,3" newline bitfld.long 0x20 18.--19. "INT_CONFIG9,interrupt config for interrupt ID = x * 16 + 9" "0,1,2,3" bitfld.long 0x20 16.--17. "INT_CONFIG8,interrupt config for interrupt ID = x * 16 + 8" "0,1,2,3" bitfld.long 0x20 14.--15. "INT_CONFIG7,interrupt config for interrupt ID = x * 16 + 7" "0,1,2,3" newline bitfld.long 0x20 12.--13. "INT_CONFIG6,interrupt config for interrupt ID = x * 16 + 6" "0,1,2,3" bitfld.long 0x20 10.--11. "INT_CONFIG5,interrupt config for interrupt ID = x * 16 + 5" "0,1,2,3" bitfld.long 0x20 8.--9. "INT_CONFIG4,interrupt config for interrupt ID = x * 16 + 4" "0,1,2,3" newline bitfld.long 0x20 6.--7. "INT_CONFIG3,interrupt config for interrupt ID = x * 16 + 3" "0,1,2,3" bitfld.long 0x20 4.--5. "INT_CONFIG2,interrupt config for interrupt ID = x * 16 + 2" "0,1,2,3" bitfld.long 0x20 2.--3. "INT_CONFIG1,interrupt config for interrupt ID = x * 16 + 1" "0,1,2,3" newline bitfld.long 0x20 0.--1. "INT_CONFIG0,interrupt config for interrupt ID = x * 16" "0,1,2,3" line.long 0x24 "GICD_ICFGR9," bitfld.long 0x24 30.--31. "INT_CONFIG15,interrupt config for interrupt ID = x * 16 + 15" "0,1,2,3" bitfld.long 0x24 28.--29. "INT_CONFIG14,interrupt config for interrupt ID = x * 16 + 14" "0,1,2,3" bitfld.long 0x24 26.--27. "INT_CONFIG13,interrupt config for interrupt ID = x * 16 + 13" "0,1,2,3" newline bitfld.long 0x24 24.--25. "INT_CONFIG12,interrupt config for interrupt ID = x * 16 + 12" "0,1,2,3" bitfld.long 0x24 22.--23. "INT_CONFIG11,interrupt config for interrupt ID = x * 16 + 11" "0,1,2,3" bitfld.long 0x24 20.--21. "INT_CONFIG10,interrupt config for interrupt ID = x * 16 + 10" "0,1,2,3" newline bitfld.long 0x24 18.--19. "INT_CONFIG9,interrupt config for interrupt ID = x * 16 + 9" "0,1,2,3" bitfld.long 0x24 16.--17. "INT_CONFIG8,interrupt config for interrupt ID = x * 16 + 8" "0,1,2,3" bitfld.long 0x24 14.--15. "INT_CONFIG7,interrupt config for interrupt ID = x * 16 + 7" "0,1,2,3" newline bitfld.long 0x24 12.--13. "INT_CONFIG6,interrupt config for interrupt ID = x * 16 + 6" "0,1,2,3" bitfld.long 0x24 10.--11. "INT_CONFIG5,interrupt config for interrupt ID = x * 16 + 5" "0,1,2,3" bitfld.long 0x24 8.--9. "INT_CONFIG4,interrupt config for interrupt ID = x * 16 + 4" "0,1,2,3" newline bitfld.long 0x24 6.--7. "INT_CONFIG3,interrupt config for interrupt ID = x * 16 + 3" "0,1,2,3" bitfld.long 0x24 4.--5. "INT_CONFIG2,interrupt config for interrupt ID = x * 16 + 2" "0,1,2,3" bitfld.long 0x24 2.--3. "INT_CONFIG1,interrupt config for interrupt ID = x * 16 + 1" "0,1,2,3" newline bitfld.long 0x24 0.--1. "INT_CONFIG0,interrupt config for interrupt ID = x * 16" "0,1,2,3" line.long 0x28 "GICD_ICFGR10," bitfld.long 0x28 30.--31. "INT_CONFIG15,interrupt config for interrupt ID = x * 16 + 15" "0,1,2,3" bitfld.long 0x28 28.--29. "INT_CONFIG14,interrupt config for interrupt ID = x * 16 + 14" "0,1,2,3" bitfld.long 0x28 26.--27. "INT_CONFIG13,interrupt config for interrupt ID = x * 16 + 13" "0,1,2,3" newline bitfld.long 0x28 24.--25. "INT_CONFIG12,interrupt config for interrupt ID = x * 16 + 12" "0,1,2,3" bitfld.long 0x28 22.--23. "INT_CONFIG11,interrupt config for interrupt ID = x * 16 + 11" "0,1,2,3" bitfld.long 0x28 20.--21. "INT_CONFIG10,interrupt config for interrupt ID = x * 16 + 10" "0,1,2,3" newline bitfld.long 0x28 18.--19. "INT_CONFIG9,interrupt config for interrupt ID = x * 16 + 9" "0,1,2,3" bitfld.long 0x28 16.--17. "INT_CONFIG8,interrupt config for interrupt ID = x * 16 + 8" "0,1,2,3" bitfld.long 0x28 14.--15. "INT_CONFIG7,interrupt config for interrupt ID = x * 16 + 7" "0,1,2,3" newline bitfld.long 0x28 12.--13. "INT_CONFIG6,interrupt config for interrupt ID = x * 16 + 6" "0,1,2,3" bitfld.long 0x28 10.--11. "INT_CONFIG5,interrupt config for interrupt ID = x * 16 + 5" "0,1,2,3" bitfld.long 0x28 8.--9. "INT_CONFIG4,interrupt config for interrupt ID = x * 16 + 4" "0,1,2,3" newline bitfld.long 0x28 6.--7. "INT_CONFIG3,interrupt config for interrupt ID = x * 16 + 3" "0,1,2,3" bitfld.long 0x28 4.--5. "INT_CONFIG2,interrupt config for interrupt ID = x * 16 + 2" "0,1,2,3" bitfld.long 0x28 2.--3. "INT_CONFIG1,interrupt config for interrupt ID = x * 16 + 1" "0,1,2,3" newline bitfld.long 0x28 0.--1. "INT_CONFIG0,interrupt config for interrupt ID = x * 16" "0,1,2,3" line.long 0x2C "GICD_ICFGR11," bitfld.long 0x2C 30.--31. "INT_CONFIG15,interrupt config for interrupt ID = x * 16 + 15" "0,1,2,3" bitfld.long 0x2C 28.--29. "INT_CONFIG14,interrupt config for interrupt ID = x * 16 + 14" "0,1,2,3" bitfld.long 0x2C 26.--27. "INT_CONFIG13,interrupt config for interrupt ID = x * 16 + 13" "0,1,2,3" newline bitfld.long 0x2C 24.--25. "INT_CONFIG12,interrupt config for interrupt ID = x * 16 + 12" "0,1,2,3" bitfld.long 0x2C 22.--23. "INT_CONFIG11,interrupt config for interrupt ID = x * 16 + 11" "0,1,2,3" bitfld.long 0x2C 20.--21. "INT_CONFIG10,interrupt config for interrupt ID = x * 16 + 10" "0,1,2,3" newline bitfld.long 0x2C 18.--19. "INT_CONFIG9,interrupt config for interrupt ID = x * 16 + 9" "0,1,2,3" bitfld.long 0x2C 16.--17. "INT_CONFIG8,interrupt config for interrupt ID = x * 16 + 8" "0,1,2,3" bitfld.long 0x2C 14.--15. "INT_CONFIG7,interrupt config for interrupt ID = x * 16 + 7" "0,1,2,3" newline bitfld.long 0x2C 12.--13. "INT_CONFIG6,interrupt config for interrupt ID = x * 16 + 6" "0,1,2,3" bitfld.long 0x2C 10.--11. "INT_CONFIG5,interrupt config for interrupt ID = x * 16 + 5" "0,1,2,3" bitfld.long 0x2C 8.--9. "INT_CONFIG4,interrupt config for interrupt ID = x * 16 + 4" "0,1,2,3" newline bitfld.long 0x2C 6.--7. "INT_CONFIG3,interrupt config for interrupt ID = x * 16 + 3" "0,1,2,3" bitfld.long 0x2C 4.--5. "INT_CONFIG2,interrupt config for interrupt ID = x * 16 + 2" "0,1,2,3" bitfld.long 0x2C 2.--3. "INT_CONFIG1,interrupt config for interrupt ID = x * 16 + 1" "0,1,2,3" newline bitfld.long 0x2C 0.--1. "INT_CONFIG0,interrupt config for interrupt ID = x * 16" "0,1,2,3" rgroup.long 0xD00++0x17 line.long 0x0 "GICD_PPISR," bitfld.long 0x0 15. "PPI3,nIRQ (not used)" "0,1" bitfld.long 0x0 14. "PPI2,secure physical timer event" "0,1" bitfld.long 0x0 13. "PPI1,secure physical timer event" "0,1" newline bitfld.long 0x0 12. "PPI0,nFIQ (not used)" "0,1" bitfld.long 0x0 11. "PPI4,virtual timer event" "0,1" bitfld.long 0x0 10. "PPI5,hypervisor timer event" "0,1" newline bitfld.long 0x0 9. "PPI6,virtual maintenance interrupt" "0,1" line.long 0x4 "GICD_SPISR0,GICD shared peripheral interrupt register 0" hexmask.long 0x4 0.--31. 1. "SPISRx,shared peripheral interrupt" line.long 0x8 "GICD_SPISR1,GICD shared peripheral interrupt register 1" hexmask.long 0x8 0.--31. 1. "SPISRx,shared peripheral interrupt" line.long 0xC "GICD_SPISR2,GICD shared peripheral interrupt register 2" hexmask.long 0xC 0.--31. 1. "SPISRx,shared peripheral interrupt" line.long 0x10 "GICD_SPISR3,GICD shared peripheral interrupt register 3" hexmask.long 0x10 0.--31. 1. "SPISRx,shared peripheral interrupt" line.long 0x14 "GICD_SPISR4,GICD shared peripheral interrupt register 4" hexmask.long 0x14 0.--31. 1. "SPISRx,shared peripheral interrupt" wgroup.long 0xF00++0x3 line.long 0x0 "GICD_SGIR," bitfld.long 0x0 24.--25. "TARGETLISTFILTER,target list filter" "0: Forward the interrupt to the CPU interfaces..,1: Forward the interrupt to all CPU interfaces..,2: Forward the interrupt only to the CPU interface..,3: Reserved" bitfld.long 0x0 16.--17. "CPUTARGETLIST,CPU target list" "0,1,2,3" bitfld.long 0x0 15. "NSATT,non-secure attribute" "0,1" newline hexmask.long.byte 0x0 0.--3. 1. "SGIINTID,SGI interrupt ID" group.long 0xF10++0x1F line.long 0x0 "GICD_CPENDSGIR0,GICD SGI clear-pending register 0" bitfld.long 0x0 24.--25. "SGI_CLEAR_PENDING3,clear-pending state for SGI [x * 4 + 3]" "0,1,2,3" bitfld.long 0x0 16.--17. "SGI_CLEAR_PENDING2,clear-pending state for SGI [x * 4 + 2]" "0,1,2,3" bitfld.long 0x0 8.--9. "SGI_CLEAR_PENDING1,clear-pending state for SGI [x * 4 + 1]" "0,1,2,3" newline bitfld.long 0x0 0.--1. "SGI_CLEAR_PENDING0,clear-pending state for SGI [x * 4]" "0,1,2,3" line.long 0x4 "GICD_CPENDSGIR1,GICD SGI clear-pending register 1" bitfld.long 0x4 24.--25. "SGI_CLEAR_PENDING3,clear-pending state for SGI [x * 4 + 3]" "0,1,2,3" bitfld.long 0x4 16.--17. "SGI_CLEAR_PENDING2,clear-pending state for SGI [x * 4 + 2]" "0,1,2,3" bitfld.long 0x4 8.--9. "SGI_CLEAR_PENDING1,clear-pending state for SGI [x * 4 + 1]" "0,1,2,3" newline bitfld.long 0x4 0.--1. "SGI_CLEAR_PENDING0,clear-pending state for SGI [x * 4]" "0,1,2,3" line.long 0x8 "GICD_CPENDSGIR2,GICD SGI clear-pending register 2" bitfld.long 0x8 24.--25. "SGI_CLEAR_PENDING3,clear-pending state for SGI [x * 4 + 3]" "0,1,2,3" bitfld.long 0x8 16.--17. "SGI_CLEAR_PENDING2,clear-pending state for SGI [x * 4 + 2]" "0,1,2,3" bitfld.long 0x8 8.--9. "SGI_CLEAR_PENDING1,clear-pending state for SGI [x * 4 + 1]" "0,1,2,3" newline bitfld.long 0x8 0.--1. "SGI_CLEAR_PENDING0,clear-pending state for SGI [x * 4]" "0,1,2,3" line.long 0xC "GICD_CPENDSGIR3,GICD SGI clear-pending register 3" bitfld.long 0xC 24.--25. "SGI_CLEAR_PENDING3,clear-pending state for SGI [x * 4 + 3]" "0,1,2,3" bitfld.long 0xC 16.--17. "SGI_CLEAR_PENDING2,clear-pending state for SGI [x * 4 + 2]" "0,1,2,3" bitfld.long 0xC 8.--9. "SGI_CLEAR_PENDING1,clear-pending state for SGI [x * 4 + 1]" "0,1,2,3" newline bitfld.long 0xC 0.--1. "SGI_CLEAR_PENDING0,clear-pending state for SGI [x * 4]" "0,1,2,3" line.long 0x10 "GICD_SPENDSGIR0,GICD SGI set-pending register 0" bitfld.long 0x10 24.--25. "SGI_SET_PENDING3,set-pending state for SGI [x * 4 + 3]" "0,1,2,3" bitfld.long 0x10 16.--17. "SGI_SET_PENDING2,set-pending state for SGI [x * 4 + 2]" "0,1,2,3" bitfld.long 0x10 8.--9. "SGI_SET_PENDING1,set-pending state for SGI [x * 4 + 1]" "0,1,2,3" newline bitfld.long 0x10 0.--1. "SGI_SET_PENDING0,set-pending state for SGI [x * 4]" "0,1,2,3" line.long 0x14 "GICD_SPENDSGIR1,GICD SGI set-pending register 1" bitfld.long 0x14 24.--25. "SGI_SET_PENDING3,set-pending state for SGI [x * 4 + 3]" "0,1,2,3" bitfld.long 0x14 16.--17. "SGI_SET_PENDING2,set-pending state for SGI [x * 4 + 2]" "0,1,2,3" bitfld.long 0x14 8.--9. "SGI_SET_PENDING1,set-pending state for SGI [x * 4 + 1]" "0,1,2,3" newline bitfld.long 0x14 0.--1. "SGI_SET_PENDING0,set-pending state for SGI [x * 4]" "0,1,2,3" line.long 0x18 "GICD_SPENDSGIR2,GICD SGI set-pending register 2" bitfld.long 0x18 24.--25. "SGI_SET_PENDING3,set-pending state for SGI [x * 4 + 3]" "0,1,2,3" bitfld.long 0x18 16.--17. "SGI_SET_PENDING2,set-pending state for SGI [x * 4 + 2]" "0,1,2,3" bitfld.long 0x18 8.--9. "SGI_SET_PENDING1,set-pending state for SGI [x * 4 + 1]" "0,1,2,3" newline bitfld.long 0x18 0.--1. "SGI_SET_PENDING0,set-pending state for SGI [x * 4]" "0,1,2,3" line.long 0x1C "GICD_SPENDSGIR3,GICD SGI set-pending register 3" bitfld.long 0x1C 24.--25. "SGI_SET_PENDING3,set-pending state for SGI [x * 4 + 3]" "0,1,2,3" bitfld.long 0x1C 16.--17. "SGI_SET_PENDING2,set-pending state for SGI [x * 4 + 2]" "0,1,2,3" bitfld.long 0x1C 8.--9. "SGI_SET_PENDING1,set-pending state for SGI [x * 4 + 1]" "0,1,2,3" newline bitfld.long 0x1C 0.--1. "SGI_SET_PENDING0,set-pending state for SGI [x * 4]" "0,1,2,3" rgroup.long 0xFD0++0x2F line.long 0x0 "GICD_PIDR4," hexmask.long 0x0 0.--31. 1. "PIDR4,peripheral ID4" line.long 0x4 "GICD_PIDR5," hexmask.long 0x4 0.--31. 1. "PIDRx,peripheral ID5 to ID7" line.long 0x8 "GICD_PIDR6," hexmask.long 0x8 0.--31. 1. "PIDRx,peripheral ID5 to ID7" line.long 0xC "GICD_PIDR7," hexmask.long 0xC 0.--31. 1. "PIDRx,peripheral ID5 to ID7" line.long 0x10 "GICD_PIDR0," hexmask.long 0x10 0.--31. 1. "PIDR0,peripheral ID0" line.long 0x14 "GICD_PIDR1," hexmask.long 0x14 0.--31. 1. "PIDR1,peripheral ID1" line.long 0x18 "GICD_PIDR2," hexmask.long 0x18 0.--31. 1. "PIDR2,peripheral ID2" line.long 0x1C "GICD_PIDR3," hexmask.long 0x1C 0.--31. 1. "PIDR3,peripheral ID3" line.long 0x20 "GICD_CIDR0," hexmask.long 0x20 0.--31. 1. "CIDR0,component ID0" line.long 0x24 "GICD_CIDR1," hexmask.long 0x24 0.--31. 1. "CIDR1,component ID1" line.long 0x28 "GICD_CIDR2," hexmask.long 0x28 0.--31. 1. "CIDR2,component ID2" line.long 0x2C "GICD_CIDR3," hexmask.long 0x2C 0.--31. 1. "CIDR3,component ID3" tree.end endif sif (cpuis("STM32MP13*")) tree "GICC" base ad:0xA0022000 group.long 0x0++0x3 line.long 0x0 "GICC_CTLR,GICC control register" bitfld.long 0x0 10. "EOIMODENS,Alias of EOIMODENS from the non-secure copy of this register." "0,1" bitfld.long 0x0 9. "EOIMODES,EOI mode for secure accesses" "0,1" bitfld.long 0x0 8. "IRQBYPDISGRP1,Alias of IRQBYPDISGRP1 from the non-secure copy of this register." "0,1" bitfld.long 0x0 7. "FIQBYPDISGRP1,Alias of FIQBYPDISGRP1 from the non-secure copy of this register." "0,1" bitfld.long 0x0 6. "IRQBYPDISGRP0,IRQ bypass disable for group 0 interrupts" "0,1" bitfld.long 0x0 5. "FIQBYPDISGRP0,FIQ bypass disable for group 0 interrupts" "0,1" newline bitfld.long 0x0 4. "CBPR,BPR control" "0,1" bitfld.long 0x0 3. "FIQEN,FIQ enable for group 0 interrupts" "0,1" bitfld.long 0x0 2. "ACKCTL,Acknowledge control" "0,1" bitfld.long 0x0 1. "ENABLEGRP1,Enable group 1 interrupts" "0,1" bitfld.long 0x0 0. "ENABLEGRP0,Enable group 0 interrupts" "0,1" group.long 0x0++0xB line.long 0x0 "GICC_CTLRNS,GICC control register" bitfld.long 0x0 9. "EOIMODENS,EOI mode for non- secure accesses" "0,1" bitfld.long 0x0 6. "IRQBYPDISGRP1,IRQBYPDISGRP1" "0,1" bitfld.long 0x0 5. "FIQBYPDISGRP1,FIQBYPDISGRP1" "0,1" bitfld.long 0x0 0. "ENABLEGRP1,ENABLEGRP1" "0,1" line.long 0x4 "GICC_PMR,GICC input priority mask register" hexmask.long.byte 0x4 3.--7. 1. "PRIORITY,priority mask level for the CPU interface" line.long 0x8 "GICC_BPR,GICC binary point register" bitfld.long 0x8 0.--2. "BINARY_POINT,The value of this field controls how the 8-bit interrupt priority field is split into a group priority field. It is used to determine interrupt preemption and a sub-priority field. Minimum value is 2." "0,1,2,3,4,5,6,7" group.long 0x8++0x3 line.long 0x0 "GICC_BPRNS,GICC_BPRNS" bitfld.long 0x0 0.--2. "BINARY_POINT,The value of this field controls how the 8-bit interrupt priority field is split into a group priority field. It is used to determine interrupt preemption and a sub-priority field. Minimum value is 2." "0,1,2,3,4,5,6,7" rgroup.long 0xC++0x3 line.long 0x0 "GICC_IAR,GICC interrupt acknowledge register" bitfld.long 0x0 10. "CPUID,For SGIs in a multiprocessor implementation this field identifies the processor that requested the interrupt. It returns the number of the CPU interface that made the request." "0,1" hexmask.long.word 0x0 0.--9. 1. "INTERRUPT_ID,The interrupt ID" wgroup.long 0x10++0x3 line.long 0x0 "GICC_EOIR," bitfld.long 0x0 10. "CPUID,On a multiprocessor implementation if the write refers to an SGI this field contains the CPUID value from the corresponding GICC_IAR access." "0,1" hexmask.long.word 0x0 0.--9. 1. "EOIINTID,It contains the interrupt ID value from the corresponding GICC_IAR access." rgroup.long 0x14++0x7 line.long 0x0 "GICC_RPR,GICC running priority register" hexmask.long.byte 0x0 3.--7. 1. "PRIORITY,current running priority on the CPU interface" line.long 0x4 "GICC_HPPIR,GICC highest priority pending interrupt register" bitfld.long 0x4 10. "CPUID,On a multiprocessor implementation if the PENDINTID field returns the ID of an SGI this field contains the CPUID value for that interrupt. This identifies the processor that generated the interrupt." "0,1" hexmask.long.word 0x4 0.--9. 1. "PENDINTID,interrupt ID of the highest-priority pending interrupt" group.long 0x1C++0x3 line.long 0x0 "GICC_ABPR,GICC aliased binary point register" bitfld.long 0x0 0.--2. "BINARY_POINT,The value of this field controls how the 8-bit interrupt priority field is split into a group priority field. It is used to determine interrupt preemption and a subpriority field. Minimun value is 3." "0,1,2,3,4,5,6,7" rgroup.long 0x20++0x3 line.long 0x0 "GICC_AIAR,GICC aliased interrupt acknowledge register" bitfld.long 0x0 10. "CPUID,For SGIs in a multiprocessor implementation this field identifies the processor that requested the interrupt. It returns the number of the CPU interface that made the request." "0,1" hexmask.long.word 0x0 0.--9. 1. "INTERRUPT_ID,interrupt ID" wgroup.long 0x24++0x3 line.long 0x0 "GICC_AEOIR,GICC aliased end of interrupt register" bitfld.long 0x0 10. "CPUID,On a multiprocessor implementation when processing an SGI this field must contain the CPUID value from the corresponding GICC_AIAR or non-secure GICC_IAR access." "0,1" hexmask.long.word 0x0 0.--9. 1. "EOIINTID,It contains the interrupt ID value from the corresponding GICC_AIAR or non-secure GICC_IAR access." rgroup.long 0x28++0x3 line.long 0x0 "GICC_AHPPIR,GICC aliased highest priority pending interrupt register" bitfld.long 0x0 10. "CPUID,On a multiprocessor implementation if the PENDINTID field returns the ID of an SGI this field contains the CPUID value for that interrupt. This identifies the processor that generated the interrupt." "0,1" hexmask.long.word 0x0 0.--9. 1. "PENDINTID,interrupt ID of the highest-priority pending interrupt" group.long 0xD0++0x3 line.long 0x0 "GICC_APR0," hexmask.long 0x0 0.--31. 1. "APR0,active priority" group.long 0xE0++0x3 line.long 0x0 "GICC_NSAPR0," hexmask.long 0x0 0.--31. 1. "NSAPR0,non-secure active priority" rgroup.long 0xFC++0x3 line.long 0x0 "GICC_IIDR," hexmask.long.word 0x0 20.--31. 1. "PRODUCTID,product ID" hexmask.long.byte 0x0 16.--19. 1. "ARCH,architecture version of the GIC" hexmask.long.byte 0x0 12.--15. 1. "REVISION,revision number for the CPU interface" hexmask.long.word 0x0 0.--11. 1. "IMPLEMENTER,GIC implementer (0x43B Arm implementation)" wgroup.long 0x1000++0x3 line.long 0x0 "GICC_DIR," bitfld.long 0x0 10. "CPUID,CPU ID" "0,1" hexmask.long.word 0x0 0.--9. 1. "INTERRUPT_ID,interrupt ID" tree.end endif sif (cpuis("STM32MP13*")) tree "GICH" base ad:0xA0024000 group.long 0x0++0x3 line.long 0x0 "GICH_HCR,GICH hypervisor control register" hexmask.long.byte 0x0 27.--31. 1. "EOICOUNT,end-of-interrupt counter" bitfld.long 0x0 7. "VGRP1DIE,virtual machine disable group 1 interrupt enable" "0,1" bitfld.long 0x0 6. "VGRP1EIE,virtual machine enable group 1 interrupt enable" "0,1" bitfld.long 0x0 5. "VGRP0DIE,virtual machine disable group 0interrupt enable" "0,1" bitfld.long 0x0 4. "VGRP0EIE,virtual machine enable group 0interrupt enable" "0,1" bitfld.long 0x0 3. "NPIE,no pending interrupt enable" "0,1" bitfld.long 0x0 2. "LRENPIE,list register entry not present interrupt enable" "0,1" bitfld.long 0x0 1. "UIE,underflow interrupt enable." "0,1" newline bitfld.long 0x0 0. "EN,global enable bit for the virtual CPU interface" "0,1" rgroup.long 0x4++0x3 line.long 0x0 "GICH_VTR," bitfld.long 0x0 29.--31. "PRIBITS,priority bits" "0,1,2,3,4,5,6,7" bitfld.long 0x0 26.--28. "PREBITS,preemption bits" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 0.--4. 1. "LISTREGS,list registers" group.long 0x8++0x3 line.long 0x0 "GICH_VMCR,GICH virtual machine control register" hexmask.long.byte 0x0 27.--31. 1. "VMPRIMASK,alias of GICV_PMR.PRIORITY" bitfld.long 0x0 21.--23. "VMBP,alias of GICV_BPR.BINARY_POINT" "0,1,2,3,4,5,6,7" bitfld.long 0x0 18.--20. "VMABP,alias of GICV_ABPR.BINARY_POINT." "0,1,2,3,4,5,6,7" bitfld.long 0x0 9. "VEM,alias of GICV_CTLR.EOIMODE" "0,1" bitfld.long 0x0 4. "VMCBPR,alias of GICV_CTLR.CBPR" "0,1" bitfld.long 0x0 3. "VMFIQEN,alias of GICV_CTLR.FIQEN" "0,1" bitfld.long 0x0 2. "VMACKCTL,alias of GICV_CTLR.ACKCTL" "0,1" bitfld.long 0x0 1. "VMGRP1EN,alias of GICV_CTLR.ENABLEGRP1" "0,1" newline bitfld.long 0x0 0. "VMGRP0EN,alias of GICV_CTLR.ENABLEGRP0" "0,1" rgroup.long 0x10++0x3 line.long 0x0 "GICH_MISR,GICH maintenance interrupt status register" bitfld.long 0x0 7. "VGRP1D,disabled group 1 maintenance interrupt" "0,1" bitfld.long 0x0 6. "VGRP1E,enabled group 1 maintenance interrupt" "0,1" bitfld.long 0x0 5. "VGRP0D,disabled group 0 maintenance interrupt" "0,1" bitfld.long 0x0 4. "VGRP0E,enabled group 0 maintenance interrupt" "0,1" bitfld.long 0x0 3. "NP,no pending maintenance interrupt" "0,1" bitfld.long 0x0 2. "LRENP,list register entry not present maintenance interrupt" "0,1" bitfld.long 0x0 1. "U,underflow maintenance interrupt" "0,1" bitfld.long 0x0 0. "EOI,End of interrupt maintenance interrupt" "0,1" rgroup.long 0x20++0x3 line.long 0x0 "GICH_EISR0,GICH end of interrupt status register" hexmask.long 0x0 0.--31. 1. "EISR0,end of interrupt status" rgroup.long 0x30++0x3 line.long 0x0 "GICH_ELSR0,GICH empty list status register" hexmask.long 0x0 0.--31. 1. "ELSR0,empty list status" group.long 0xF0++0x3 line.long 0x0 "GICH_APR0," hexmask.long 0x0 0.--31. 1. "APR0,active priority" group.long 0x100++0xF line.long 0x0 "GICH_LR0," bitfld.long 0x0 31. "HW,hardware interrupt" "0,1" bitfld.long 0x0 30. "GRP1,Indicates whether this virtual interrupt is a group 1 virtual interrupt" "0,1" bitfld.long 0x0 28.--29. "STATE,state of the interrupt" "0,1,2,3" hexmask.long.byte 0x0 23.--27. 1. "PRIORITY,priority of the interrupt" hexmask.long.word 0x0 10.--19. 1. "PHYSICALID,physical ID" hexmask.long.word 0x0 0.--9. 1. "VIRTUALID,virtual ID" line.long 0x4 "GICH_LR1," bitfld.long 0x4 31. "HW,hardware interrupt" "0,1" bitfld.long 0x4 30. "GRP1,Indicates whether this virtual interrupt is a group 1 virtual interrupt" "0,1" bitfld.long 0x4 28.--29. "STATE,state of the interrupt" "0,1,2,3" hexmask.long.byte 0x4 23.--27. 1. "PRIORITY,priority of the interrupt" hexmask.long.word 0x4 10.--19. 1. "PHYSICALID,physical ID" hexmask.long.word 0x4 0.--9. 1. "VIRTUALID,virtual ID" line.long 0x8 "GICH_LR2," bitfld.long 0x8 31. "HW,hardware interrupt" "0,1" bitfld.long 0x8 30. "GRP1,Indicates whether this virtual interrupt is a group 1 virtual interrupt" "0,1" bitfld.long 0x8 28.--29. "STATE,state of the interrupt" "0,1,2,3" hexmask.long.byte 0x8 23.--27. 1. "PRIORITY,priority of the interrupt" hexmask.long.word 0x8 10.--19. 1. "PHYSICALID,physical ID" hexmask.long.word 0x8 0.--9. 1. "VIRTUALID,virtual ID" line.long 0xC "GICH_LR3," bitfld.long 0xC 31. "HW,hardware interrupt" "0,1" bitfld.long 0xC 30. "GRP1,Indicates whether this virtual interrupt is a group 1 virtual interrupt" "0,1" bitfld.long 0xC 28.--29. "STATE,state of the interrupt" "0,1,2,3" hexmask.long.byte 0xC 23.--27. 1. "PRIORITY,priority of the interrupt" hexmask.long.word 0xC 10.--19. 1. "PHYSICALID,physical ID" hexmask.long.word 0xC 0.--9. 1. "VIRTUALID,virtual ID" tree.end endif sif (cpuis("STM32MP13*")) tree "GICV" base ad:0xA0026000 group.long 0x0++0xB line.long 0x0 "GICV_CTLR,GICV virtual machine control register" bitfld.long 0x0 9. "EOIMODE,end of interrupt mode" "0,1" bitfld.long 0x0 4. "CBPR,BPR control" "0,1" bitfld.long 0x0 3. "FIQEN,FIQ enable for group 0 interrupts" "0,1" bitfld.long 0x0 2. "ACKCTL,acknowledge control" "0,1" bitfld.long 0x0 1. "ENABLEGRP1,Enables the signaling of group 1 virtual interrupts by the virtual CPU interface to the virtual machine." "0,1" bitfld.long 0x0 0. "ENABLEGRP0,Enables the signaling of group 0 virtual interrupts by the virtual CPU interface to the virtual machine." "0,1" line.long 0x4 "GICV_PMR,GICV VM priority mask register" hexmask.long.byte 0x4 3.--7. 1. "PRIORITY,priority mask level for the virtual CPU interface" line.long 0x8 "GICV_BPR,GICV VM binary point register" bitfld.long 0x8 0.--2. "BINARY_POINT,The value of this field controls how the 8-bit virtual interrupt priority field is split into a group priority field used to determine virtual interrupt preemption and a subpriority field. Minimun value is 2." "0,1,2,3,4,5,6,7" rgroup.long 0xC++0x3 line.long 0x0 "GICV_IAR,GICV VM interrupt acknowledge register" bitfld.long 0x0 10. "CPUID,If the GICH_LRx.HW bit is set to 0 indicating that the interrupt is triggered in software then CPUID of the GICH_LRx that indicate the CPU ID are returned in the GICV_IAR.CPUID field. Otherwise GICV_IAR.CPUID field reads as zero." "0,1" hexmask.long.word 0x0 0.--9. 1. "INTERRUPT_ID,The interrupt ID" wgroup.long 0x10++0x3 line.long 0x0 "GICV_EOIR," bitfld.long 0x0 10. "CPUID,On a multiprocessor implementation if the write refers to an SGI this field contains the CPUID value from the corresponding GICV_IAR access." "0,1" hexmask.long.word 0x0 0.--9. 1. "EOIINTID,If the GICH_LRx.HW bit in the matching list register is set to 1 indicating a hardware interrupt then a deactivate request is sent to the physical Distributor identifying the Physical ID from the corresponding field in the list register." rgroup.long 0x14++0x7 line.long 0x0 "GICV_RPR,GICV VM running priority register" hexmask.long.byte 0x0 3.--7. 1. "PRIORITY,current running priority on the virtual CPU interface" line.long 0x4 "GICV_HPPIR,GICV VM highest priority pending interrupt register" bitfld.long 0x4 10. "CPUID,On a multiprocessor implementation if GICH_LRx.HW bit=0 this field contains the CPUID value for that virtual interrupt. This identifies the virtual processor that generated the virtual interrupt." "0,1" hexmask.long.word 0x4 0.--9. 1. "PENDINTID,The virtual interrupt ID of the highest priority pending virtual interrupt" group.long 0x1C++0x3 line.long 0x0 "GICV_ABPR,GICV VM aliased binary point register" bitfld.long 0x0 0.--2. "BINARY_POINT,The value of this field controls how the 8-bit virtual interrupt priority field is split into a group priority field used to determine virtual interrupt preemption and a subpriority field. Minimun value is 3." "0,1,2,3,4,5,6,7" rgroup.long 0x20++0x3 line.long 0x0 "GICV_AIAR,GICV VM aliased interrupt register" bitfld.long 0x0 10. "CPUID,If the GICH_LRx.HW bit is set to 0 indicating that the interrupt is triggered in software then CPUID of the GICH_LRx that indicate the CPU ID are returned in the GICV_AIAR.CPUID field. Otherwise GICV_AIAR.CPUID field reads as zero.." "0,1" hexmask.long.word 0x0 0.--9. 1. "INTERRUPT_ID,The interrupt ID. If the GICH_LRx.Grp1 bit is 0 the interrupt is Group 0. The spurious interrupt ID 1023 is returned and the interrupt is not acknowledged." wgroup.long 0x24++0x3 line.long 0x0 "GICV_AEOIR," bitfld.long 0x0 10. "CPUID,On a multiprocessor implementation if the write refers to an SGI this field contains the CPUID value from the corresponding GICV_IAR access." "0,1" hexmask.long.word 0x0 0.--9. 1. "EOIINTID,If the GICH_LRx.HW bit in the matching list register is set to 1 indicating a hardware interrupt then a deactivate request is sent to the physical Distributor identifying the Physical ID from the corresponding field in the list register." rgroup.long 0x28++0x3 line.long 0x0 "GICV_AHPPIR,GICV VM aliased highest priority pending interrupt register" bitfld.long 0x0 10. "CPUID,If the GICH_LRx.HW bit in the matching List register is set to 1 indicating a hardware interrupt then a deactivate request is sent to the physical Distributor identifying the physical ID from the corresponding field in the List register." "0,1" hexmask.long.word 0x0 0.--9. 1. "PENDINTID,The virtual interrupt ID of the highest-priority pending virtual interrupt if that virtual interrupt is a group 1 virtual interrupt. Otherwise the spurious virtual interrupt ID 1023." group.long 0xD0++0x3 line.long 0x0 "GICV_APR0,GICV VM active priority register" hexmask.long 0x0 0.--31. 1. "APR0,active priority" rgroup.long 0xFC++0x3 line.long 0x0 "GICV_IIDR,GICV VM CPU interface identification register" hexmask.long 0x0 0.--31. 1. "IIDR,see description of GICC_IIDR register" wgroup.long 0x1000++0x3 line.long 0x0 "GICV_DIR," bitfld.long 0x0 10. "CPUID,This field identifies the processor that requested the interrupt." "0,1" hexmask.long.word 0x0 0.--9. 1. "INTERRUPT_ID,The interrupt ID" tree.end endif sif (cpuis("STM32MP151*")||cpuis("STM32MP153*")||cpuis("STM32MP157*")) tree "GICC" base ad:0xA0022000 group.long 0x0++0xB line.long 0x0 "GICC_CTLR,GICC control register" bitfld.long 0x0 10. "EOIMODENS,EOIMODENS" "0,1" bitfld.long 0x0 9. "EOIMODES,EOIMODES" "0,1" bitfld.long 0x0 8. "IRQBYPDISGRP1,IRQBYPDISGRP1" "0,1" bitfld.long 0x0 7. "FIQBYPDISGRP1,FIQBYPDISGRP1" "0,1" bitfld.long 0x0 6. "IRQBYPDISGRP0,IRQBYPDISGRP0" "0,1" bitfld.long 0x0 5. "FIQBYPDISGRP0,FIQBYPDISGRP0" "0,1" newline bitfld.long 0x0 4. "CBPR,CBPR" "0,1" bitfld.long 0x0 3. "FIQEN,FIQEN" "0,1" bitfld.long 0x0 2. "ACKCTL,ACKCTL" "0,1" bitfld.long 0x0 1. "ENABLEGRP1,ENABLEGRP1" "0,1" bitfld.long 0x0 0. "ENABLEGRP0,ENABLEGRP0" "0,1" line.long 0x4 "GICC_PMR,GICC input priority mask register" hexmask.long.byte 0x4 3.--7. 1. "PRIORITY,PRIORITY" line.long 0x8 "GICC_BPR,GICC binary point register" bitfld.long 0x8 0.--2. "BINARY_POINT,BINARY_POINT" "0,1,2,3,4,5,6,7" rgroup.long 0xC++0x3 line.long 0x0 "GICC_IAR,GICC interrupt acknowledge register" bitfld.long 0x0 10. "CPUID,CPUID" "0,1" hexmask.long.word 0x0 0.--9. 1. "INTERRUPT_ID,INTERRUPT_ID" wgroup.long 0x10++0x3 line.long 0x0 "GICC_EOIR,GICC end of interrupt register" bitfld.long 0x0 10. "CPUID,CPUID" "0,1" hexmask.long.word 0x0 0.--9. 1. "EOIINTID,EOIINTID" rgroup.long 0x14++0x7 line.long 0x0 "GICC_RPR,GICC running priority register" hexmask.long.byte 0x0 3.--7. 1. "PRIORITY,PRIORITY" line.long 0x4 "GICC_HPPIR,GICC highest priority pending interrupt register" bitfld.long 0x4 10. "CPUID,CPUID" "0,1" hexmask.long.word 0x4 0.--9. 1. "PENDINTID,PENDINTID" group.long 0x1C++0x3 line.long 0x0 "GICC_ABPR,GICC_ABPR is an alias of the non-secure GICC_BPR. When GICC_CTLR.CBPR is set to 0. a secure access to this register is equivalent to a non-secure access to GICC_BPR." bitfld.long 0x0 0.--2. "BINARY_POINT,BINARY_POINT" "0,1,2,3,4,5,6,7" rgroup.long 0x20++0x3 line.long 0x0 "GICC_AIAR,GICC_AIAR is an alias of the non-secure view of GICC_IAR. A secure access to this register is identical to a non-secure access to GICC_IAR." bitfld.long 0x0 10. "CPUID,CPUID" "0,1" hexmask.long.word 0x0 0.--9. 1. "INTERRUPT_ID,INTERRUPT_ID" wgroup.long 0x24++0x3 line.long 0x0 "GICC_AEOIR,GICC_AEOIR is an alias of the Non-secure GICC_EOIR. A secure access to this register is similar to a non-secure access to GICC_EOIR. except that the GICC_CTLR.EOImodeS bit is used." bitfld.long 0x0 10. "CPUID,CPUID" "0,1" hexmask.long.word 0x0 0.--9. 1. "EOIINTID,EOIINTID" rgroup.long 0x28++0x3 line.long 0x0 "GICC_AHPPIR,ICC_AHPPIR is an alias of the non-secure GICC_HPPIR. A secure access to this register is equivalent to a non-secure access to GICC_HPPIR." bitfld.long 0x0 10. "CPUID,CPUID" "0,1" hexmask.long.word 0x0 0.--9. 1. "PENDINTID,PENDINTID" group.long 0xD0++0x3 line.long 0x0 "GICC_APR0,GICC active priority register" hexmask.long 0x0 0.--31. 1. "APR0,APR0" group.long 0xE0++0x3 line.long 0x0 "GICC_NSAPR0,GICC non-secure active priority register" hexmask.long 0x0 0.--31. 1. "NSAPR0,NSAPR0" rgroup.long 0xFC++0x3 line.long 0x0 "GICC_IIDR,GICC interface identification register" hexmask.long.word 0x0 20.--31. 1. "PRODUCTID,PRODUCTID" hexmask.long.byte 0x0 16.--19. 1. "ARCH,ARCH" hexmask.long.byte 0x0 12.--15. 1. "REVISION,REVISION" hexmask.long.word 0x0 0.--11. 1. "IMPLEMENTER,IMPLEMENTER" wgroup.long 0x1000++0x3 line.long 0x0 "GICC_DIR,GICC deactivate interrupt register" bitfld.long 0x0 10. "CPUID,CPUID" "0,1" hexmask.long.word 0x0 0.--9. 1. "INTERRUPT_ID,INTERRUPT_ID" tree.end endif sif (cpuis("STM32MP151*")||cpuis("STM32MP153*")||cpuis("STM32MP157*")) tree "GICD" base ad:0xA0021000 group.long 0x0++0x3 line.long 0x0 "GICD_CTLR,GICD control register" bitfld.long 0x0 1. "ENABLEGRP1,ENABLEGRP1" "0,1" bitfld.long 0x0 0. "ENABLEGRP0,ENABLEGRP0" "0,1" rgroup.long 0x4++0x7 line.long 0x0 "GICD_TYPER,GICD interrupt controller type register" hexmask.long.byte 0x0 11.--15. 1. "LSPI,LSPI" bitfld.long 0x0 10. "SECURITYEXTN,SECURITYEXTN" "0,1" bitfld.long 0x0 5.--7. "CPUNUMBER,CPUNUMBER" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 0.--4. 1. "ITLINESNUMBER,ITLINESNUMBER" line.long 0x4 "GICD_IIDR,GICD implementer identification register" hexmask.long.byte 0x4 24.--31. 1. "PRODUCTID,PRODUCTID" hexmask.long.byte 0x4 16.--19. 1. "REVISION,REVISION" hexmask.long.byte 0x4 12.--15. 1. "VARIANT,VARIANT" hexmask.long.word 0x4 0.--11. 1. "IMPLEMENTER,IMPLEMENTER" group.long 0x80++0x23 line.long 0x0 "GICD_IGROUPR0,For interrupts ID" hexmask.long 0x0 0.--31. 1. "IGROUPR0,IGROUPR0" line.long 0x4 "GICD_IGROUPR1,For interrupts ID" hexmask.long 0x4 0.--31. 1. "IGROUPR1,IGROUPR1" line.long 0x8 "GICD_IGROUPR2,For interrupts ID" hexmask.long 0x8 0.--31. 1. "IGROUPR2,IGROUPR2" line.long 0xC "GICD_IGROUPR3,For interrupts ID = x*32 to ID = x*32+31" hexmask.long 0xC 0.--31. 1. "IGROUPR3,IGROUPR3" line.long 0x10 "GICD_IGROUPR4,For interrupts ID = x*32 to ID = x*32+31" hexmask.long 0x10 0.--31. 1. "IGROUPR4,IGROUPR4" line.long 0x14 "GICD_IGROUPR5,For interrupts ID" hexmask.long 0x14 0.--31. 1. "IGROUPR5,IGROUPR5" line.long 0x18 "GICD_IGROUPR6,For interrupts ID" hexmask.long 0x18 0.--31. 1. "IGROUPR6,IGROUPR6" line.long 0x1C "GICD_IGROUPR7,For interrupts ID" hexmask.long 0x1C 0.--31. 1. "IGROUPR7,IGROUPR7" line.long 0x20 "GICD_IGROUPR8,For interrupts ID" hexmask.long 0x20 0.--31. 1. "IGROUPR8,IGROUPR8" group.long 0x100++0x23 line.long 0x0 "GICD_ISENABLER0,For interrupts ID = 0 to ID = 31" hexmask.long 0x0 0.--31. 1. "ISENABLER0,ISENABLER0" line.long 0x4 "GICD_ISENABLER1,For interrupts ID" hexmask.long 0x4 0.--31. 1. "ISENABLER1,ISENABLER1" line.long 0x8 "GICD_ISENABLER2,For interrupts ID" hexmask.long 0x8 0.--31. 1. "ISENABLER2,ISENABLER2" line.long 0xC "GICD_ISENABLER3,For interrupts ID" hexmask.long 0xC 0.--31. 1. "ISENABLER3,ISENABLER3" line.long 0x10 "GICD_ISENABLER4,For interrupts ID" hexmask.long 0x10 0.--31. 1. "ISENABLER4,ISENABLER4" line.long 0x14 "GICD_ISENABLER5,For interrupts ID" hexmask.long 0x14 0.--31. 1. "ISENABLER5,ISENABLER5" line.long 0x18 "GICD_ISENABLER6,For interrupts ID" hexmask.long 0x18 0.--31. 1. "ISENABLER6,ISENABLER6" line.long 0x1C "GICD_ISENABLER7,For interrupts ID" hexmask.long 0x1C 0.--31. 1. "ISENABLER7,ISENABLER7" line.long 0x20 "GICD_ISENABLER8,For interrupts ID" hexmask.long 0x20 0.--31. 1. "ISENABLER8,ISENABLER8" group.long 0x180++0x23 line.long 0x0 "GICD_ICENABLER0,For interrupts ID = 0 to ID = 31" hexmask.long 0x0 0.--31. 1. "ICENABLER0,ICENABLER0" line.long 0x4 "GICD_ICENABLER1,For interrupts ID" hexmask.long 0x4 0.--31. 1. "ICENABLER1,ICENABLER1" line.long 0x8 "GICD_ICENABLER2,For interrupts ID" hexmask.long 0x8 0.--31. 1. "ICENABLER2,ICENABLER2" line.long 0xC "GICD_ICENABLER3,For interrupts ID" hexmask.long 0xC 0.--31. 1. "ICENABLER3,ICENABLER3" line.long 0x10 "GICD_ICENABLER4,For interrupts ID" hexmask.long 0x10 0.--31. 1. "ICENABLER4,ICENABLER4" line.long 0x14 "GICD_ICENABLER5,For interrupts ID" hexmask.long 0x14 0.--31. 1. "ICENABLER5,ICENABLER5" line.long 0x18 "GICD_ICENABLER6,For interrupts ID" hexmask.long 0x18 0.--31. 1. "ICENABLER6,ICENABLER6" line.long 0x1C "GICD_ICENABLER7,For interrupts ID" hexmask.long 0x1C 0.--31. 1. "ICENABLER7,ICENABLER7" line.long 0x20 "GICD_ICENABLER8,For interrupts ID" hexmask.long 0x20 0.--31. 1. "ICENABLER8,ICENABLER8" group.long 0x200++0x23 line.long 0x0 "GICD_ISPENDR0,For interrupts ID" hexmask.long 0x0 0.--31. 1. "ISPENDR0,ISPENDR0" line.long 0x4 "GICD_ISPENDR1,For interrupts ID" hexmask.long 0x4 0.--31. 1. "ISPENDR1,ISPENDR1" line.long 0x8 "GICD_ISPENDR2,For interrupts ID" hexmask.long 0x8 0.--31. 1. "ISPENDR2,ISPENDR2" line.long 0xC "GICD_ISPENDR3,For interrupts ID" hexmask.long 0xC 0.--31. 1. "ISPENDR3,ISPENDR3" line.long 0x10 "GICD_ISPENDR4,For interrupts ID" hexmask.long 0x10 0.--31. 1. "ISPENDR4,ISPENDR4" line.long 0x14 "GICD_ISPENDR5,For interrupts ID" hexmask.long 0x14 0.--31. 1. "ISPENDR5,ISPENDR5" line.long 0x18 "GICD_ISPENDR6,For interrupts ID" hexmask.long 0x18 0.--31. 1. "ISPENDR6,ISPENDR6" line.long 0x1C "GICD_ISPENDR7,For interrupts ID" hexmask.long 0x1C 0.--31. 1. "ISPENDR7,ISPENDR7" line.long 0x20 "GICD_ISPENDR8,For interrupts ID" hexmask.long 0x20 0.--31. 1. "ISPENDR8,ISPENDR8" group.long 0x280++0x23 line.long 0x0 "GICD_ICPENDR0,For interrupts ID" hexmask.long 0x0 0.--31. 1. "ICPENDR0,ICPENDR0" line.long 0x4 "GICD_ICPENDR1,For interrupts ID" hexmask.long 0x4 0.--31. 1. "ICPENDR1,ICPENDR1" line.long 0x8 "GICD_ICPENDR2,For interrupts ID" hexmask.long 0x8 0.--31. 1. "ICPENDR2,ICPENDR2" line.long 0xC "GICD_ICPENDR3,For interrupts ID" hexmask.long 0xC 0.--31. 1. "ICPENDR3,ICPENDR3" line.long 0x10 "GICD_ICPENDR4,For interrupts ID" hexmask.long 0x10 0.--31. 1. "ICPENDR4,ICPENDR4" line.long 0x14 "GICD_ICPENDR5,For interrupts ID" hexmask.long 0x14 0.--31. 1. "ICPENDR5,ICPENDR5" line.long 0x18 "GICD_ICPENDR6,For interrupts ID" hexmask.long 0x18 0.--31. 1. "ICPENDR6,ICPENDR6" line.long 0x1C "GICD_ICPENDR7,For interrupts ID" hexmask.long 0x1C 0.--31. 1. "ICPENDR7,ICPENDR7" line.long 0x20 "GICD_ICPENDR8,For interrupts ID" hexmask.long 0x20 0.--31. 1. "ICPENDR8,ICPENDR8" group.long 0x300++0x23 line.long 0x0 "GICD_ISACTIVER0,For interrupts ID" hexmask.long 0x0 0.--31. 1. "ISACTIVER0,ISACTIVER0" line.long 0x4 "GICD_ISACTIVER1,For interrupts ID" hexmask.long 0x4 0.--31. 1. "ISACTIVER1,ISACTIVER1" line.long 0x8 "GICD_ISACTIVER2,For interrupts ID" hexmask.long 0x8 0.--31. 1. "ISACTIVER2,ISACTIVER2" line.long 0xC "GICD_ISACTIVER3,For interrupts ID" hexmask.long 0xC 0.--31. 1. "ISACTIVER3,ISACTIVER3" line.long 0x10 "GICD_ISACTIVER4,For interrupts ID" hexmask.long 0x10 0.--31. 1. "ISACTIVER4,ISACTIVER4" line.long 0x14 "GICD_ISACTIVER5,For interrupts ID" hexmask.long 0x14 0.--31. 1. "ISACTIVER5,ISACTIVER5" line.long 0x18 "GICD_ISACTIVER6,For interrupts ID" hexmask.long 0x18 0.--31. 1. "ISACTIVER6,ISACTIVER6" line.long 0x1C "GICD_ISACTIVER7,For interrupts ID" hexmask.long 0x1C 0.--31. 1. "ISACTIVER7,ISACTIVER7" line.long 0x20 "GICD_ISACTIVER8,For interrupts ID" hexmask.long 0x20 0.--31. 1. "ISACTIVER8,ISACTIVER8" group.long 0x380++0x23 line.long 0x0 "GICD_ICACTIVER0,For interrupts ID" hexmask.long 0x0 0.--31. 1. "ICACTIVER0,ICACTIVER0" line.long 0x4 "GICD_ICACTIVER1,For interrupts ID" hexmask.long 0x4 0.--31. 1. "ICACTIVER1,ICACTIVER1" line.long 0x8 "GICD_ICACTIVER2,For interrupts ID" hexmask.long 0x8 0.--31. 1. "ICACTIVER2,ICACTIVER2" line.long 0xC "GICD_ICACTIVER3,For interrupts ID" hexmask.long 0xC 0.--31. 1. "ICACTIVER3,ICACTIVER3" line.long 0x10 "GICD_ICACTIVER4,For interrupts ID" hexmask.long 0x10 0.--31. 1. "ICACTIVER4,ICACTIVER4" line.long 0x14 "GICD_ICACTIVER5,For interrupts ID" hexmask.long 0x14 0.--31. 1. "ICACTIVER5,ICACTIVER5" line.long 0x18 "GICD_ICACTIVER6,For interrupts ID" hexmask.long 0x18 0.--31. 1. "ICACTIVER6,ICACTIVER6" line.long 0x1C "GICD_ICACTIVER7,For interrupts ID" hexmask.long 0x1C 0.--31. 1. "ICACTIVER7,ICACTIVER7" line.long 0x20 "GICD_ICACTIVER8,For interrupts ID" hexmask.long 0x20 0.--31. 1. "ICACTIVER8,ICACTIVER8" group.long 0x400++0x11F line.long 0x0 "GICD_IPRIORITYR0,GICD interrupt priority register 0" hexmask.long.byte 0x0 27.--31. 1. "PRIORITY3,PRIORITY3" hexmask.long.byte 0x0 19.--23. 1. "PRIORITY2,PRIORITY2" hexmask.long.byte 0x0 11.--15. 1. "PRIORITY1,PRIORITY1" hexmask.long.byte 0x0 3.--7. 1. "PRIORITY0,PRIORITY0" line.long 0x4 "GICD_IPRIORITYR1,GICD interrupt priority register 1" hexmask.long.byte 0x4 27.--31. 1. "PRIORITY3,PRIORITY3" hexmask.long.byte 0x4 19.--23. 1. "PRIORITY2,PRIORITY2" hexmask.long.byte 0x4 11.--15. 1. "PRIORITY1,PRIORITY1" hexmask.long.byte 0x4 3.--7. 1. "PRIORITY0,PRIORITY0" line.long 0x8 "GICD_IPRIORITYR2,GICD interrupt priority register 2" hexmask.long.byte 0x8 27.--31. 1. "PRIORITY3,PRIORITY3" hexmask.long.byte 0x8 19.--23. 1. "PRIORITY2,PRIORITY2" hexmask.long.byte 0x8 11.--15. 1. "PRIORITY1,PRIORITY1" hexmask.long.byte 0x8 3.--7. 1. "PRIORITY0,PRIORITY0" line.long 0xC "GICD_IPRIORITYR3,GICD interrupt priority register 3" hexmask.long.byte 0xC 27.--31. 1. "PRIORITY3,PRIORITY3" hexmask.long.byte 0xC 19.--23. 1. "PRIORITY2,PRIORITY2" hexmask.long.byte 0xC 11.--15. 1. "PRIORITY1,PRIORITY1" hexmask.long.byte 0xC 3.--7. 1. "PRIORITY0,PRIORITY0" line.long 0x10 "GICD_IPRIORITYR4,GICD interrupt priority register 4" hexmask.long.byte 0x10 27.--31. 1. "PRIORITY3,PRIORITY3" hexmask.long.byte 0x10 19.--23. 1. "PRIORITY2,PRIORITY2" hexmask.long.byte 0x10 11.--15. 1. "PRIORITY1,PRIORITY1" hexmask.long.byte 0x10 3.--7. 1. "PRIORITY0,PRIORITY0" line.long 0x14 "GICD_IPRIORITYR5,GICD interrupt priority register 5" hexmask.long.byte 0x14 27.--31. 1. "PRIORITY3,PRIORITY3" hexmask.long.byte 0x14 19.--23. 1. "PRIORITY2,PRIORITY2" hexmask.long.byte 0x14 11.--15. 1. "PRIORITY1,PRIORITY1" hexmask.long.byte 0x14 3.--7. 1. "PRIORITY0,PRIORITY0" line.long 0x18 "GICD_IPRIORITYR6,GICD interrupt priority register 6" hexmask.long.byte 0x18 27.--31. 1. "PRIORITY3,PRIORITY3" hexmask.long.byte 0x18 19.--23. 1. "PRIORITY2,PRIORITY2" hexmask.long.byte 0x18 11.--15. 1. "PRIORITY1,PRIORITY1" hexmask.long.byte 0x18 3.--7. 1. "PRIORITY0,PRIORITY0" line.long 0x1C "GICD_IPRIORITYR7,GICD interrupt priority register 7" hexmask.long.byte 0x1C 27.--31. 1. "PRIORITY3,PRIORITY3" hexmask.long.byte 0x1C 19.--23. 1. "PRIORITY2,PRIORITY2" hexmask.long.byte 0x1C 11.--15. 1. "PRIORITY1,PRIORITY1" hexmask.long.byte 0x1C 3.--7. 1. "PRIORITY0,PRIORITY0" line.long 0x20 "GICD_IPRIORITYR8,GICD interrupt priority register 8" hexmask.long.byte 0x20 27.--31. 1. "PRIORITY3,PRIORITY3" hexmask.long.byte 0x20 19.--23. 1. "PRIORITY2,PRIORITY2" hexmask.long.byte 0x20 11.--15. 1. "PRIORITY1,PRIORITY1" hexmask.long.byte 0x20 3.--7. 1. "PRIORITY0,PRIORITY0" line.long 0x24 "GICD_IPRIORITYR9,GICD interrupt priority register 9" hexmask.long.byte 0x24 27.--31. 1. "PRIORITY3,PRIORITY3" hexmask.long.byte 0x24 19.--23. 1. "PRIORITY2,PRIORITY2" hexmask.long.byte 0x24 11.--15. 1. "PRIORITY1,PRIORITY1" hexmask.long.byte 0x24 3.--7. 1. "PRIORITY0,PRIORITY0" line.long 0x28 "GICD_IPRIORITYR10,GICD interrupt priority register 10" hexmask.long.byte 0x28 27.--31. 1. "PRIORITY3,PRIORITY3" hexmask.long.byte 0x28 19.--23. 1. "PRIORITY2,PRIORITY2" hexmask.long.byte 0x28 11.--15. 1. "PRIORITY1,PRIORITY1" hexmask.long.byte 0x28 3.--7. 1. "PRIORITY0,PRIORITY0" line.long 0x2C "GICD_IPRIORITYR11,GICD interrupt priority register 11" hexmask.long.byte 0x2C 27.--31. 1. "PRIORITY3,PRIORITY3" hexmask.long.byte 0x2C 19.--23. 1. "PRIORITY2,PRIORITY2" hexmask.long.byte 0x2C 11.--15. 1. "PRIORITY1,PRIORITY1" hexmask.long.byte 0x2C 3.--7. 1. "PRIORITY0,PRIORITY0" line.long 0x30 "GICD_IPRIORITYR12,GICD interrupt priority register 12" hexmask.long.byte 0x30 27.--31. 1. "PRIORITY3,PRIORITY3" hexmask.long.byte 0x30 19.--23. 1. "PRIORITY2,PRIORITY2" hexmask.long.byte 0x30 11.--15. 1. "PRIORITY1,PRIORITY1" hexmask.long.byte 0x30 3.--7. 1. "PRIORITY0,PRIORITY0" line.long 0x34 "GICD_IPRIORITYR13,GICD interrupt priority register 13" hexmask.long.byte 0x34 27.--31. 1. "PRIORITY3,PRIORITY3" hexmask.long.byte 0x34 19.--23. 1. "PRIORITY2,PRIORITY2" hexmask.long.byte 0x34 11.--15. 1. "PRIORITY1,PRIORITY1" hexmask.long.byte 0x34 3.--7. 1. "PRIORITY0,PRIORITY0" line.long 0x38 "GICD_IPRIORITYR14,GICD interrupt priority register 14" hexmask.long.byte 0x38 27.--31. 1. "PRIORITY3,PRIORITY3" hexmask.long.byte 0x38 19.--23. 1. "PRIORITY2,PRIORITY2" hexmask.long.byte 0x38 11.--15. 1. "PRIORITY1,PRIORITY1" hexmask.long.byte 0x38 3.--7. 1. "PRIORITY0,PRIORITY0" line.long 0x3C "GICD_IPRIORITYR15,GICD interrupt priority register 15" hexmask.long.byte 0x3C 27.--31. 1. "PRIORITY3,PRIORITY3" hexmask.long.byte 0x3C 19.--23. 1. "PRIORITY2,PRIORITY2" hexmask.long.byte 0x3C 11.--15. 1. "PRIORITY1,PRIORITY1" hexmask.long.byte 0x3C 3.--7. 1. "PRIORITY0,PRIORITY0" line.long 0x40 "GICD_IPRIORITYR16,GICD interrupt priority register 16" hexmask.long.byte 0x40 27.--31. 1. "PRIORITY3,PRIORITY3" hexmask.long.byte 0x40 19.--23. 1. "PRIORITY2,PRIORITY2" hexmask.long.byte 0x40 11.--15. 1. "PRIORITY1,PRIORITY1" hexmask.long.byte 0x40 3.--7. 1. "PRIORITY0,PRIORITY0" line.long 0x44 "GICD_IPRIORITYR17,GICD interrupt priority register 17" hexmask.long.byte 0x44 27.--31. 1. "PRIORITY3,PRIORITY3" hexmask.long.byte 0x44 19.--23. 1. "PRIORITY2,PRIORITY2" hexmask.long.byte 0x44 11.--15. 1. "PRIORITY1,PRIORITY1" hexmask.long.byte 0x44 3.--7. 1. "PRIORITY0,PRIORITY0" line.long 0x48 "GICD_IPRIORITYR18,GICD interrupt priority register 18" hexmask.long.byte 0x48 27.--31. 1. "PRIORITY3,PRIORITY3" hexmask.long.byte 0x48 19.--23. 1. "PRIORITY2,PRIORITY2" hexmask.long.byte 0x48 11.--15. 1. "PRIORITY1,PRIORITY1" hexmask.long.byte 0x48 3.--7. 1. "PRIORITY0,PRIORITY0" line.long 0x4C "GICD_IPRIORITYR19,GICD interrupt priority register 19" hexmask.long.byte 0x4C 27.--31. 1. "PRIORITY3,PRIORITY3" hexmask.long.byte 0x4C 19.--23. 1. "PRIORITY2,PRIORITY2" hexmask.long.byte 0x4C 11.--15. 1. "PRIORITY1,PRIORITY1" hexmask.long.byte 0x4C 3.--7. 1. "PRIORITY0,PRIORITY0" line.long 0x50 "GICD_IPRIORITYR20,GICD interrupt priority register 20" hexmask.long.byte 0x50 27.--31. 1. "PRIORITY3,PRIORITY3" hexmask.long.byte 0x50 19.--23. 1. "PRIORITY2,PRIORITY2" hexmask.long.byte 0x50 11.--15. 1. "PRIORITY1,PRIORITY1" hexmask.long.byte 0x50 3.--7. 1. "PRIORITY0,PRIORITY0" line.long 0x54 "GICD_IPRIORITYR21,GICD interrupt priority register 21" hexmask.long.byte 0x54 27.--31. 1. "PRIORITY3,PRIORITY3" hexmask.long.byte 0x54 19.--23. 1. "PRIORITY2,PRIORITY2" hexmask.long.byte 0x54 11.--15. 1. "PRIORITY1,PRIORITY1" hexmask.long.byte 0x54 3.--7. 1. "PRIORITY0,PRIORITY0" line.long 0x58 "GICD_IPRIORITYR22,GICD interrupt priority register 22" hexmask.long.byte 0x58 27.--31. 1. "PRIORITY3,PRIORITY3" hexmask.long.byte 0x58 19.--23. 1. "PRIORITY2,PRIORITY2" hexmask.long.byte 0x58 11.--15. 1. "PRIORITY1,PRIORITY1" hexmask.long.byte 0x58 3.--7. 1. "PRIORITY0,PRIORITY0" line.long 0x5C "GICD_IPRIORITYR23,GICD interrupt priority register 23" hexmask.long.byte 0x5C 27.--31. 1. "PRIORITY3,PRIORITY3" hexmask.long.byte 0x5C 19.--23. 1. "PRIORITY2,PRIORITY2" hexmask.long.byte 0x5C 11.--15. 1. "PRIORITY1,PRIORITY1" hexmask.long.byte 0x5C 3.--7. 1. "PRIORITY0,PRIORITY0" line.long 0x60 "GICD_IPRIORITYR24,GICD interrupt priority register 24" hexmask.long.byte 0x60 27.--31. 1. "PRIORITY3,PRIORITY3" hexmask.long.byte 0x60 19.--23. 1. "PRIORITY2,PRIORITY2" hexmask.long.byte 0x60 11.--15. 1. "PRIORITY1,PRIORITY1" hexmask.long.byte 0x60 3.--7. 1. "PRIORITY0,PRIORITY0" line.long 0x64 "GICD_IPRIORITYR25,GICD interrupt priority register 25" hexmask.long.byte 0x64 27.--31. 1. "PRIORITY3,PRIORITY3" hexmask.long.byte 0x64 19.--23. 1. "PRIORITY2,PRIORITY2" hexmask.long.byte 0x64 11.--15. 1. "PRIORITY1,PRIORITY1" hexmask.long.byte 0x64 3.--7. 1. "PRIORITY0,PRIORITY0" line.long 0x68 "GICD_IPRIORITYR26,GICD interrupt priority register 26" hexmask.long.byte 0x68 27.--31. 1. "PRIORITY3,PRIORITY3" hexmask.long.byte 0x68 19.--23. 1. "PRIORITY2,PRIORITY2" hexmask.long.byte 0x68 11.--15. 1. "PRIORITY1,PRIORITY1" hexmask.long.byte 0x68 3.--7. 1. "PRIORITY0,PRIORITY0" line.long 0x6C "GICD_IPRIORITYR27,GICD interrupt priority register 27" hexmask.long.byte 0x6C 27.--31. 1. "PRIORITY3,PRIORITY3" hexmask.long.byte 0x6C 19.--23. 1. "PRIORITY2,PRIORITY2" hexmask.long.byte 0x6C 11.--15. 1. "PRIORITY1,PRIORITY1" hexmask.long.byte 0x6C 3.--7. 1. "PRIORITY0,PRIORITY0" line.long 0x70 "GICD_IPRIORITYR28,GICD interrupt priority register 28" hexmask.long.byte 0x70 27.--31. 1. "PRIORITY3,PRIORITY3" hexmask.long.byte 0x70 19.--23. 1. "PRIORITY2,PRIORITY2" hexmask.long.byte 0x70 11.--15. 1. "PRIORITY1,PRIORITY1" hexmask.long.byte 0x70 3.--7. 1. "PRIORITY0,PRIORITY0" line.long 0x74 "GICD_IPRIORITYR29,GICD interrupt priority register 29" hexmask.long.byte 0x74 27.--31. 1. "PRIORITY3,PRIORITY3" hexmask.long.byte 0x74 19.--23. 1. "PRIORITY2,PRIORITY2" hexmask.long.byte 0x74 11.--15. 1. "PRIORITY1,PRIORITY1" hexmask.long.byte 0x74 3.--7. 1. "PRIORITY0,PRIORITY0" line.long 0x78 "GICD_IPRIORITYR30,GICD interrupt priority register 30" hexmask.long.byte 0x78 27.--31. 1. "PRIORITY3,PRIORITY3" hexmask.long.byte 0x78 19.--23. 1. "PRIORITY2,PRIORITY2" hexmask.long.byte 0x78 11.--15. 1. "PRIORITY1,PRIORITY1" hexmask.long.byte 0x78 3.--7. 1. "PRIORITY0,PRIORITY0" line.long 0x7C "GICD_IPRIORITYR31,GICD interrupt priority register 31" hexmask.long.byte 0x7C 27.--31. 1. "PRIORITY3,PRIORITY3" hexmask.long.byte 0x7C 19.--23. 1. "PRIORITY2,PRIORITY2" hexmask.long.byte 0x7C 11.--15. 1. "PRIORITY1,PRIORITY1" hexmask.long.byte 0x7C 3.--7. 1. "PRIORITY0,PRIORITY0" line.long 0x80 "GICD_IPRIORITYR32,GICD interrupt priority register 32" hexmask.long.byte 0x80 27.--31. 1. "PRIORITY3,PRIORITY3" hexmask.long.byte 0x80 19.--23. 1. "PRIORITY2,PRIORITY2" hexmask.long.byte 0x80 11.--15. 1. "PRIORITY1,PRIORITY1" hexmask.long.byte 0x80 3.--7. 1. "PRIORITY0,PRIORITY0" line.long 0x84 "GICD_IPRIORITYR33,GICD interrupt priority register 33" hexmask.long.byte 0x84 27.--31. 1. "PRIORITY3,PRIORITY3" hexmask.long.byte 0x84 19.--23. 1. "PRIORITY2,PRIORITY2" hexmask.long.byte 0x84 11.--15. 1. "PRIORITY1,PRIORITY1" hexmask.long.byte 0x84 3.--7. 1. "PRIORITY0,PRIORITY0" line.long 0x88 "GICD_IPRIORITYR34,GICD interrupt priority register 34" hexmask.long.byte 0x88 27.--31. 1. "PRIORITY3,PRIORITY3" hexmask.long.byte 0x88 19.--23. 1. "PRIORITY2,PRIORITY2" hexmask.long.byte 0x88 11.--15. 1. "PRIORITY1,PRIORITY1" hexmask.long.byte 0x88 3.--7. 1. "PRIORITY0,PRIORITY0" line.long 0x8C "GICD_IPRIORITYR35,GICD interrupt priority register 35" hexmask.long.byte 0x8C 27.--31. 1. "PRIORITY3,PRIORITY3" hexmask.long.byte 0x8C 19.--23. 1. "PRIORITY2,PRIORITY2" hexmask.long.byte 0x8C 11.--15. 1. "PRIORITY1,PRIORITY1" hexmask.long.byte 0x8C 3.--7. 1. "PRIORITY0,PRIORITY0" line.long 0x90 "GICD_IPRIORITYR36,GICD interrupt priority register 36" hexmask.long.byte 0x90 27.--31. 1. "PRIORITY3,PRIORITY3" hexmask.long.byte 0x90 19.--23. 1. "PRIORITY2,PRIORITY2" hexmask.long.byte 0x90 11.--15. 1. "PRIORITY1,PRIORITY1" hexmask.long.byte 0x90 3.--7. 1. "PRIORITY0,PRIORITY0" line.long 0x94 "GICD_IPRIORITYR37,GICD interrupt priority register 37" hexmask.long.byte 0x94 27.--31. 1. "PRIORITY3,PRIORITY3" hexmask.long.byte 0x94 19.--23. 1. "PRIORITY2,PRIORITY2" hexmask.long.byte 0x94 11.--15. 1. "PRIORITY1,PRIORITY1" hexmask.long.byte 0x94 3.--7. 1. "PRIORITY0,PRIORITY0" line.long 0x98 "GICD_IPRIORITYR38,GICD interrupt priority register 38" hexmask.long.byte 0x98 27.--31. 1. "PRIORITY3,PRIORITY3" hexmask.long.byte 0x98 19.--23. 1. "PRIORITY2,PRIORITY2" hexmask.long.byte 0x98 11.--15. 1. "PRIORITY1,PRIORITY1" hexmask.long.byte 0x98 3.--7. 1. "PRIORITY0,PRIORITY0" line.long 0x9C "GICD_IPRIORITYR39,GICD interrupt priority register 39" hexmask.long.byte 0x9C 27.--31. 1. "PRIORITY3,PRIORITY3" hexmask.long.byte 0x9C 19.--23. 1. "PRIORITY2,PRIORITY2" hexmask.long.byte 0x9C 11.--15. 1. "PRIORITY1,PRIORITY1" hexmask.long.byte 0x9C 3.--7. 1. "PRIORITY0,PRIORITY0" line.long 0xA0 "GICD_IPRIORITYR40,GICD interrupt priority register 40" hexmask.long.byte 0xA0 27.--31. 1. "PRIORITY3,PRIORITY3" hexmask.long.byte 0xA0 19.--23. 1. "PRIORITY2,PRIORITY2" hexmask.long.byte 0xA0 11.--15. 1. "PRIORITY1,PRIORITY1" hexmask.long.byte 0xA0 3.--7. 1. "PRIORITY0,PRIORITY0" line.long 0xA4 "GICD_IPRIORITYR41,GICD interrupt priority register 41" hexmask.long.byte 0xA4 27.--31. 1. "PRIORITY3,PRIORITY3" hexmask.long.byte 0xA4 19.--23. 1. "PRIORITY2,PRIORITY2" hexmask.long.byte 0xA4 11.--15. 1. "PRIORITY1,PRIORITY1" hexmask.long.byte 0xA4 3.--7. 1. "PRIORITY0,PRIORITY0" line.long 0xA8 "GICD_IPRIORITYR42,GICD interrupt priority register 42" hexmask.long.byte 0xA8 27.--31. 1. "PRIORITY3,PRIORITY3" hexmask.long.byte 0xA8 19.--23. 1. "PRIORITY2,PRIORITY2" hexmask.long.byte 0xA8 11.--15. 1. "PRIORITY1,PRIORITY1" hexmask.long.byte 0xA8 3.--7. 1. "PRIORITY0,PRIORITY0" line.long 0xAC "GICD_IPRIORITYR43,GICD interrupt priority register 43" hexmask.long.byte 0xAC 27.--31. 1. "PRIORITY3,PRIORITY3" hexmask.long.byte 0xAC 19.--23. 1. "PRIORITY2,PRIORITY2" hexmask.long.byte 0xAC 11.--15. 1. "PRIORITY1,PRIORITY1" hexmask.long.byte 0xAC 3.--7. 1. "PRIORITY0,PRIORITY0" line.long 0xB0 "GICD_IPRIORITYR44,GICD interrupt priority register 44" hexmask.long.byte 0xB0 27.--31. 1. "PRIORITY3,PRIORITY3" hexmask.long.byte 0xB0 19.--23. 1. "PRIORITY2,PRIORITY2" hexmask.long.byte 0xB0 11.--15. 1. "PRIORITY1,PRIORITY1" hexmask.long.byte 0xB0 3.--7. 1. "PRIORITY0,PRIORITY0" line.long 0xB4 "GICD_IPRIORITYR45,GICD interrupt priority register 45" hexmask.long.byte 0xB4 27.--31. 1. "PRIORITY3,PRIORITY3" hexmask.long.byte 0xB4 19.--23. 1. "PRIORITY2,PRIORITY2" hexmask.long.byte 0xB4 11.--15. 1. "PRIORITY1,PRIORITY1" hexmask.long.byte 0xB4 3.--7. 1. "PRIORITY0,PRIORITY0" line.long 0xB8 "GICD_IPRIORITYR46,GICD interrupt priority register 46" hexmask.long.byte 0xB8 27.--31. 1. "PRIORITY3,PRIORITY3" hexmask.long.byte 0xB8 19.--23. 1. "PRIORITY2,PRIORITY2" hexmask.long.byte 0xB8 11.--15. 1. "PRIORITY1,PRIORITY1" hexmask.long.byte 0xB8 3.--7. 1. "PRIORITY0,PRIORITY0" line.long 0xBC "GICD_IPRIORITYR47,GICD interrupt priority register 47" hexmask.long.byte 0xBC 27.--31. 1. "PRIORITY3,PRIORITY3" hexmask.long.byte 0xBC 19.--23. 1. "PRIORITY2,PRIORITY2" hexmask.long.byte 0xBC 11.--15. 1. "PRIORITY1,PRIORITY1" hexmask.long.byte 0xBC 3.--7. 1. "PRIORITY0,PRIORITY0" line.long 0xC0 "GICD_IPRIORITYR48,GICD interrupt priority register 48" hexmask.long.byte 0xC0 27.--31. 1. "PRIORITY3,PRIORITY3" hexmask.long.byte 0xC0 19.--23. 1. "PRIORITY2,PRIORITY2" hexmask.long.byte 0xC0 11.--15. 1. "PRIORITY1,PRIORITY1" hexmask.long.byte 0xC0 3.--7. 1. "PRIORITY0,PRIORITY0" line.long 0xC4 "GICD_IPRIORITYR49,GICD interrupt priority register 49" hexmask.long.byte 0xC4 27.--31. 1. "PRIORITY3,PRIORITY3" hexmask.long.byte 0xC4 19.--23. 1. "PRIORITY2,PRIORITY2" hexmask.long.byte 0xC4 11.--15. 1. "PRIORITY1,PRIORITY1" hexmask.long.byte 0xC4 3.--7. 1. "PRIORITY0,PRIORITY0" line.long 0xC8 "GICD_IPRIORITYR50,GICD interrupt priority register 50" hexmask.long.byte 0xC8 27.--31. 1. "PRIORITY3,PRIORITY3" hexmask.long.byte 0xC8 19.--23. 1. "PRIORITY2,PRIORITY2" hexmask.long.byte 0xC8 11.--15. 1. "PRIORITY1,PRIORITY1" hexmask.long.byte 0xC8 3.--7. 1. "PRIORITY0,PRIORITY0" line.long 0xCC "GICD_IPRIORITYR51,GICD interrupt priority register 51" hexmask.long.byte 0xCC 27.--31. 1. "PRIORITY3,PRIORITY3" hexmask.long.byte 0xCC 19.--23. 1. "PRIORITY2,PRIORITY2" hexmask.long.byte 0xCC 11.--15. 1. "PRIORITY1,PRIORITY1" hexmask.long.byte 0xCC 3.--7. 1. "PRIORITY0,PRIORITY0" line.long 0xD0 "GICD_IPRIORITYR52,GICD interrupt priority register 52" hexmask.long.byte 0xD0 27.--31. 1. "PRIORITY3,PRIORITY3" hexmask.long.byte 0xD0 19.--23. 1. "PRIORITY2,PRIORITY2" hexmask.long.byte 0xD0 11.--15. 1. "PRIORITY1,PRIORITY1" hexmask.long.byte 0xD0 3.--7. 1. "PRIORITY0,PRIORITY0" line.long 0xD4 "GICD_IPRIORITYR53,GICD interrupt priority register 53" hexmask.long.byte 0xD4 27.--31. 1. "PRIORITY3,PRIORITY3" hexmask.long.byte 0xD4 19.--23. 1. "PRIORITY2,PRIORITY2" hexmask.long.byte 0xD4 11.--15. 1. "PRIORITY1,PRIORITY1" hexmask.long.byte 0xD4 3.--7. 1. "PRIORITY0,PRIORITY0" line.long 0xD8 "GICD_IPRIORITYR54,GICD interrupt priority register 54" hexmask.long.byte 0xD8 27.--31. 1. "PRIORITY3,PRIORITY3" hexmask.long.byte 0xD8 19.--23. 1. "PRIORITY2,PRIORITY2" hexmask.long.byte 0xD8 11.--15. 1. "PRIORITY1,PRIORITY1" hexmask.long.byte 0xD8 3.--7. 1. "PRIORITY0,PRIORITY0" line.long 0xDC "GICD_IPRIORITYR55,GICD interrupt priority register 55" hexmask.long.byte 0xDC 27.--31. 1. "PRIORITY3,PRIORITY3" hexmask.long.byte 0xDC 19.--23. 1. "PRIORITY2,PRIORITY2" hexmask.long.byte 0xDC 11.--15. 1. "PRIORITY1,PRIORITY1" hexmask.long.byte 0xDC 3.--7. 1. "PRIORITY0,PRIORITY0" line.long 0xE0 "GICD_IPRIORITYR56,GICD interrupt priority register 56" hexmask.long.byte 0xE0 27.--31. 1. "PRIORITY3,PRIORITY3" hexmask.long.byte 0xE0 19.--23. 1. "PRIORITY2,PRIORITY2" hexmask.long.byte 0xE0 11.--15. 1. "PRIORITY1,PRIORITY1" hexmask.long.byte 0xE0 3.--7. 1. "PRIORITY0,PRIORITY0" line.long 0xE4 "GICD_IPRIORITYR57,GICD interrupt priority register 57" hexmask.long.byte 0xE4 27.--31. 1. "PRIORITY3,PRIORITY3" hexmask.long.byte 0xE4 19.--23. 1. "PRIORITY2,PRIORITY2" hexmask.long.byte 0xE4 11.--15. 1. "PRIORITY1,PRIORITY1" hexmask.long.byte 0xE4 3.--7. 1. "PRIORITY0,PRIORITY0" line.long 0xE8 "GICD_IPRIORITYR58,GICD interrupt priority register 58" hexmask.long.byte 0xE8 27.--31. 1. "PRIORITY3,PRIORITY3" hexmask.long.byte 0xE8 19.--23. 1. "PRIORITY2,PRIORITY2" hexmask.long.byte 0xE8 11.--15. 1. "PRIORITY1,PRIORITY1" hexmask.long.byte 0xE8 3.--7. 1. "PRIORITY0,PRIORITY0" line.long 0xEC "GICD_IPRIORITYR59,GICD interrupt priority register 59" hexmask.long.byte 0xEC 27.--31. 1. "PRIORITY3,PRIORITY3" hexmask.long.byte 0xEC 19.--23. 1. "PRIORITY2,PRIORITY2" hexmask.long.byte 0xEC 11.--15. 1. "PRIORITY1,PRIORITY1" hexmask.long.byte 0xEC 3.--7. 1. "PRIORITY0,PRIORITY0" line.long 0xF0 "GICD_IPRIORITYR60,GICD interrupt priority register 60" hexmask.long.byte 0xF0 27.--31. 1. "PRIORITY3,PRIORITY3" hexmask.long.byte 0xF0 19.--23. 1. "PRIORITY2,PRIORITY2" hexmask.long.byte 0xF0 11.--15. 1. "PRIORITY1,PRIORITY1" hexmask.long.byte 0xF0 3.--7. 1. "PRIORITY0,PRIORITY0" line.long 0xF4 "GICD_IPRIORITYR61,GICD interrupt priority register 61" hexmask.long.byte 0xF4 27.--31. 1. "PRIORITY3,PRIORITY3" hexmask.long.byte 0xF4 19.--23. 1. "PRIORITY2,PRIORITY2" hexmask.long.byte 0xF4 11.--15. 1. "PRIORITY1,PRIORITY1" hexmask.long.byte 0xF4 3.--7. 1. "PRIORITY0,PRIORITY0" line.long 0xF8 "GICD_IPRIORITYR62,GICD interrupt priority register 62" hexmask.long.byte 0xF8 27.--31. 1. "PRIORITY3,PRIORITY3" hexmask.long.byte 0xF8 19.--23. 1. "PRIORITY2,PRIORITY2" hexmask.long.byte 0xF8 11.--15. 1. "PRIORITY1,PRIORITY1" hexmask.long.byte 0xF8 3.--7. 1. "PRIORITY0,PRIORITY0" line.long 0xFC "GICD_IPRIORITYR63,GICD interrupt priority register 63" hexmask.long.byte 0xFC 27.--31. 1. "PRIORITY3,PRIORITY3" hexmask.long.byte 0xFC 19.--23. 1. "PRIORITY2,PRIORITY2" hexmask.long.byte 0xFC 11.--15. 1. "PRIORITY1,PRIORITY1" hexmask.long.byte 0xFC 3.--7. 1. "PRIORITY0,PRIORITY0" line.long 0x100 "GICD_IPRIORITYR64,GICD interrupt priority register 64" hexmask.long.byte 0x100 27.--31. 1. "PRIORITY3,PRIORITY3" hexmask.long.byte 0x100 19.--23. 1. "PRIORITY2,PRIORITY2" hexmask.long.byte 0x100 11.--15. 1. "PRIORITY1,PRIORITY1" hexmask.long.byte 0x100 3.--7. 1. "PRIORITY0,PRIORITY0" line.long 0x104 "GICD_IPRIORITYR65,GICD interrupt priority register 65" hexmask.long.byte 0x104 27.--31. 1. "PRIORITY3,PRIORITY3" hexmask.long.byte 0x104 19.--23. 1. "PRIORITY2,PRIORITY2" hexmask.long.byte 0x104 11.--15. 1. "PRIORITY1,PRIORITY1" hexmask.long.byte 0x104 3.--7. 1. "PRIORITY0,PRIORITY0" line.long 0x108 "GICD_IPRIORITYR66,GICD interrupt priority register 66" hexmask.long.byte 0x108 27.--31. 1. "PRIORITY3,PRIORITY3" hexmask.long.byte 0x108 19.--23. 1. "PRIORITY2,PRIORITY2" hexmask.long.byte 0x108 11.--15. 1. "PRIORITY1,PRIORITY1" hexmask.long.byte 0x108 3.--7. 1. "PRIORITY0,PRIORITY0" line.long 0x10C "GICD_IPRIORITYR67,GICD interrupt priority register 67" hexmask.long.byte 0x10C 27.--31. 1. "PRIORITY3,PRIORITY3" hexmask.long.byte 0x10C 19.--23. 1. "PRIORITY2,PRIORITY2" hexmask.long.byte 0x10C 11.--15. 1. "PRIORITY1,PRIORITY1" hexmask.long.byte 0x10C 3.--7. 1. "PRIORITY0,PRIORITY0" line.long 0x110 "GICD_IPRIORITYR68,GICD interrupt priority register 68" hexmask.long.byte 0x110 27.--31. 1. "PRIORITY3,PRIORITY3" hexmask.long.byte 0x110 19.--23. 1. "PRIORITY2,PRIORITY2" hexmask.long.byte 0x110 11.--15. 1. "PRIORITY1,PRIORITY1" hexmask.long.byte 0x110 3.--7. 1. "PRIORITY0,PRIORITY0" line.long 0x114 "GICD_IPRIORITYR69,GICD interrupt priority register 69" hexmask.long.byte 0x114 27.--31. 1. "PRIORITY3,PRIORITY3" hexmask.long.byte 0x114 19.--23. 1. "PRIORITY2,PRIORITY2" hexmask.long.byte 0x114 11.--15. 1. "PRIORITY1,PRIORITY1" hexmask.long.byte 0x114 3.--7. 1. "PRIORITY0,PRIORITY0" line.long 0x118 "GICD_IPRIORITYR70,GICD interrupt priority register 70" hexmask.long.byte 0x118 27.--31. 1. "PRIORITY3,PRIORITY3" hexmask.long.byte 0x118 19.--23. 1. "PRIORITY2,PRIORITY2" hexmask.long.byte 0x118 11.--15. 1. "PRIORITY1,PRIORITY1" hexmask.long.byte 0x118 3.--7. 1. "PRIORITY0,PRIORITY0" line.long 0x11C "GICD_IPRIORITYR71,GICD interrupt priority register 71" hexmask.long.byte 0x11C 27.--31. 1. "PRIORITY3,PRIORITY3" hexmask.long.byte 0x11C 19.--23. 1. "PRIORITY2,PRIORITY2" hexmask.long.byte 0x11C 11.--15. 1. "PRIORITY1,PRIORITY1" hexmask.long.byte 0x11C 3.--7. 1. "PRIORITY0,PRIORITY0" rgroup.long 0x800++0x1F line.long 0x0 "GICD_ITARGETSR0,For existing SGIs and PPIs. read of CPU targets field returns the number of the processor performing the read." bitfld.long 0x0 24.--25. "CPU_TARGETS3,CPU_TARGETS3" "0,1,2,3" bitfld.long 0x0 16.--17. "CPU_TARGETS2,CPU_TARGETS2" "0,1,2,3" bitfld.long 0x0 8.--9. "CPU_TARGETS1,CPU_TARGETS1" "0,1,2,3" bitfld.long 0x0 0.--1. "CPU_TARGETS0,CPU_TARGETS0" "0,1,2,3" line.long 0x4 "GICD_ITARGETSR1,For existing SGIs and PPIs. read of CPU targets field returns the number of the processor performing the read." bitfld.long 0x4 24.--25. "CPU_TARGETS3,CPU_TARGETS3" "0,1,2,3" bitfld.long 0x4 16.--17. "CPU_TARGETS2,CPU_TARGETS2" "0,1,2,3" bitfld.long 0x4 8.--9. "CPU_TARGETS1,CPU_TARGETS1" "0,1,2,3" bitfld.long 0x4 0.--1. "CPU_TARGETS0,CPU_TARGETS0" "0,1,2,3" line.long 0x8 "GICD_ITARGETSR2,For existing SGIs and PPIs. read of CPU targets field returns the number of the processor performing the read." bitfld.long 0x8 24.--25. "CPU_TARGETS3,CPU_TARGETS3" "0,1,2,3" bitfld.long 0x8 16.--17. "CPU_TARGETS2,CPU_TARGETS2" "0,1,2,3" bitfld.long 0x8 8.--9. "CPU_TARGETS1,CPU_TARGETS1" "0,1,2,3" bitfld.long 0x8 0.--1. "CPU_TARGETS0,CPU_TARGETS0" "0,1,2,3" line.long 0xC "GICD_ITARGETSR3,For existing SGIs and PPIs. read of CPU targets field returns the number of the processor performing the read." bitfld.long 0xC 24.--25. "CPU_TARGETS3,CPU_TARGETS3" "0,1,2,3" bitfld.long 0xC 16.--17. "CPU_TARGETS2,CPU_TARGETS2" "0,1,2,3" bitfld.long 0xC 8.--9. "CPU_TARGETS1,CPU_TARGETS1" "0,1,2,3" bitfld.long 0xC 0.--1. "CPU_TARGETS0,CPU_TARGETS0" "0,1,2,3" line.long 0x10 "GICD_ITARGETSR4,For existing SGIs and PPIs. read of CPU targets field returns the number of the processor performing the read." bitfld.long 0x10 24.--25. "CPU_TARGETS3,CPU_TARGETS3" "0,1,2,3" bitfld.long 0x10 16.--17. "CPU_TARGETS2,CPU_TARGETS2" "0,1,2,3" bitfld.long 0x10 8.--9. "CPU_TARGETS1,CPU_TARGETS1" "0,1,2,3" bitfld.long 0x10 0.--1. "CPU_TARGETS0,CPU_TARGETS0" "0,1,2,3" line.long 0x14 "GICD_ITARGETSR5,For existing SGIs and PPIs. read of CPU targets field returns the number of the processor performing the read." bitfld.long 0x14 24.--25. "CPU_TARGETS3,CPU_TARGETS3" "0,1,2,3" bitfld.long 0x14 16.--17. "CPU_TARGETS2,CPU_TARGETS2" "0,1,2,3" bitfld.long 0x14 8.--9. "CPU_TARGETS1,CPU_TARGETS1" "0,1,2,3" bitfld.long 0x14 0.--1. "CPU_TARGETS0,CPU_TARGETS0" "0,1,2,3" line.long 0x18 "GICD_ITARGETSR6,For existing SGIs and PPIs. read of CPU targets field returns the number of the processor performing the read." bitfld.long 0x18 24.--25. "CPU_TARGETS3,CPU_TARGETS3" "0,1,2,3" bitfld.long 0x18 16.--17. "CPU_TARGETS2,CPU_TARGETS2" "0,1,2,3" bitfld.long 0x18 8.--9. "CPU_TARGETS1,CPU_TARGETS1" "0,1,2,3" bitfld.long 0x18 0.--1. "CPU_TARGETS0,CPU_TARGETS0" "0,1,2,3" line.long 0x1C "GICD_ITARGETSR7,For existing SGIs and PPIs. read of CPU targets field returns the number of the processor performing the read." bitfld.long 0x1C 24.--25. "CPU_TARGETS3,CPU_TARGETS3" "0,1,2,3" bitfld.long 0x1C 16.--17. "CPU_TARGETS2,CPU_TARGETS2" "0,1,2,3" bitfld.long 0x1C 8.--9. "CPU_TARGETS1,CPU_TARGETS1" "0,1,2,3" bitfld.long 0x1C 0.--1. "CPU_TARGETS0,CPU_TARGETS0" "0,1,2,3" group.long 0x820++0xFF line.long 0x0 "GICD_ITARGETSR8,GICD interrupt processor target register 8" bitfld.long 0x0 24.--25. "CPU_TARGETS3,CPU_TARGETS3" "0,1,2,3" bitfld.long 0x0 16.--17. "CPU_TARGETS2,CPU_TARGETS2" "0,1,2,3" bitfld.long 0x0 8.--9. "CPU_TARGETS1,CPU_TARGETS1" "0,1,2,3" bitfld.long 0x0 0.--1. "CPU_TARGETS0,CPU_TARGETS0" "0,1,2,3" line.long 0x4 "GICD_ITARGETSR9,GICD interrupt processor target register 9" bitfld.long 0x4 24.--25. "CPU_TARGETS3,CPU_TARGETS3" "0,1,2,3" bitfld.long 0x4 16.--17. "CPU_TARGETS2,CPU_TARGETS2" "0,1,2,3" bitfld.long 0x4 8.--9. "CPU_TARGETS1,CPU_TARGETS1" "0,1,2,3" bitfld.long 0x4 0.--1. "CPU_TARGETS0,CPU_TARGETS0" "0,1,2,3" line.long 0x8 "GICD_ITARGETSR10,GICD interrupt processor target register 10" bitfld.long 0x8 24.--25. "CPU_TARGETS3,CPU_TARGETS3" "0,1,2,3" bitfld.long 0x8 16.--17. "CPU_TARGETS2,CPU_TARGETS2" "0,1,2,3" bitfld.long 0x8 8.--9. "CPU_TARGETS1,CPU_TARGETS1" "0,1,2,3" bitfld.long 0x8 0.--1. "CPU_TARGETS0,CPU_TARGETS0" "0,1,2,3" line.long 0xC "GICD_ITARGETSR11,GICD interrupt processor target register 11" bitfld.long 0xC 24.--25. "CPU_TARGETS3,CPU_TARGETS3" "0,1,2,3" bitfld.long 0xC 16.--17. "CPU_TARGETS2,CPU_TARGETS2" "0,1,2,3" bitfld.long 0xC 8.--9. "CPU_TARGETS1,CPU_TARGETS1" "0,1,2,3" bitfld.long 0xC 0.--1. "CPU_TARGETS0,CPU_TARGETS0" "0,1,2,3" line.long 0x10 "GICD_ITARGETSR12,GICD interrupt processor target register 12" bitfld.long 0x10 24.--25. "CPU_TARGETS3,CPU_TARGETS3" "0,1,2,3" bitfld.long 0x10 16.--17. "CPU_TARGETS2,CPU_TARGETS2" "0,1,2,3" bitfld.long 0x10 8.--9. "CPU_TARGETS1,CPU_TARGETS1" "0,1,2,3" bitfld.long 0x10 0.--1. "CPU_TARGETS0,CPU_TARGETS0" "0,1,2,3" line.long 0x14 "GICD_ITARGETSR13,GICD interrupt processor target register 13" bitfld.long 0x14 24.--25. "CPU_TARGETS3,CPU_TARGETS3" "0,1,2,3" bitfld.long 0x14 16.--17. "CPU_TARGETS2,CPU_TARGETS2" "0,1,2,3" bitfld.long 0x14 8.--9. "CPU_TARGETS1,CPU_TARGETS1" "0,1,2,3" bitfld.long 0x14 0.--1. "CPU_TARGETS0,CPU_TARGETS0" "0,1,2,3" line.long 0x18 "GICD_ITARGETSR14,GICD interrupt processor target register 14" bitfld.long 0x18 24.--25. "CPU_TARGETS3,CPU_TARGETS3" "0,1,2,3" bitfld.long 0x18 16.--17. "CPU_TARGETS2,CPU_TARGETS2" "0,1,2,3" bitfld.long 0x18 8.--9. "CPU_TARGETS1,CPU_TARGETS1" "0,1,2,3" bitfld.long 0x18 0.--1. "CPU_TARGETS0,CPU_TARGETS0" "0,1,2,3" line.long 0x1C "GICD_ITARGETSR15,GICD interrupt processor target register 15" bitfld.long 0x1C 24.--25. "CPU_TARGETS3,CPU_TARGETS3" "0,1,2,3" bitfld.long 0x1C 16.--17. "CPU_TARGETS2,CPU_TARGETS2" "0,1,2,3" bitfld.long 0x1C 8.--9. "CPU_TARGETS1,CPU_TARGETS1" "0,1,2,3" bitfld.long 0x1C 0.--1. "CPU_TARGETS0,CPU_TARGETS0" "0,1,2,3" line.long 0x20 "GICD_ITARGETSR16,GICD interrupt processor target register 16" bitfld.long 0x20 24.--25. "CPU_TARGETS3,CPU_TARGETS3" "0,1,2,3" bitfld.long 0x20 16.--17. "CPU_TARGETS2,CPU_TARGETS2" "0,1,2,3" bitfld.long 0x20 8.--9. "CPU_TARGETS1,CPU_TARGETS1" "0,1,2,3" bitfld.long 0x20 0.--1. "CPU_TARGETS0,CPU_TARGETS0" "0,1,2,3" line.long 0x24 "GICD_ITARGETSR17,GICD interrupt processor target register 17" bitfld.long 0x24 24.--25. "CPU_TARGETS3,CPU_TARGETS3" "0,1,2,3" bitfld.long 0x24 16.--17. "CPU_TARGETS2,CPU_TARGETS2" "0,1,2,3" bitfld.long 0x24 8.--9. "CPU_TARGETS1,CPU_TARGETS1" "0,1,2,3" bitfld.long 0x24 0.--1. "CPU_TARGETS0,CPU_TARGETS0" "0,1,2,3" line.long 0x28 "GICD_ITARGETSR18,GICD interrupt processor target register 18" bitfld.long 0x28 24.--25. "CPU_TARGETS3,CPU_TARGETS3" "0,1,2,3" bitfld.long 0x28 16.--17. "CPU_TARGETS2,CPU_TARGETS2" "0,1,2,3" bitfld.long 0x28 8.--9. "CPU_TARGETS1,CPU_TARGETS1" "0,1,2,3" bitfld.long 0x28 0.--1. "CPU_TARGETS0,CPU_TARGETS0" "0,1,2,3" line.long 0x2C "GICD_ITARGETSR19,GICD interrupt processor target register 19" bitfld.long 0x2C 24.--25. "CPU_TARGETS3,CPU_TARGETS3" "0,1,2,3" bitfld.long 0x2C 16.--17. "CPU_TARGETS2,CPU_TARGETS2" "0,1,2,3" bitfld.long 0x2C 8.--9. "CPU_TARGETS1,CPU_TARGETS1" "0,1,2,3" bitfld.long 0x2C 0.--1. "CPU_TARGETS0,CPU_TARGETS0" "0,1,2,3" line.long 0x30 "GICD_ITARGETSR20,GICD interrupt processor target register 20" bitfld.long 0x30 24.--25. "CPU_TARGETS3,CPU_TARGETS3" "0,1,2,3" bitfld.long 0x30 16.--17. "CPU_TARGETS2,CPU_TARGETS2" "0,1,2,3" bitfld.long 0x30 8.--9. "CPU_TARGETS1,CPU_TARGETS1" "0,1,2,3" bitfld.long 0x30 0.--1. "CPU_TARGETS0,CPU_TARGETS0" "0,1,2,3" line.long 0x34 "GICD_ITARGETSR21,GICD interrupt processor target register 21" bitfld.long 0x34 24.--25. "CPU_TARGETS3,CPU_TARGETS3" "0,1,2,3" bitfld.long 0x34 16.--17. "CPU_TARGETS2,CPU_TARGETS2" "0,1,2,3" bitfld.long 0x34 8.--9. "CPU_TARGETS1,CPU_TARGETS1" "0,1,2,3" bitfld.long 0x34 0.--1. "CPU_TARGETS0,CPU_TARGETS0" "0,1,2,3" line.long 0x38 "GICD_ITARGETSR22,GICD interrupt processor target register 22" bitfld.long 0x38 24.--25. "CPU_TARGETS3,CPU_TARGETS3" "0,1,2,3" bitfld.long 0x38 16.--17. "CPU_TARGETS2,CPU_TARGETS2" "0,1,2,3" bitfld.long 0x38 8.--9. "CPU_TARGETS1,CPU_TARGETS1" "0,1,2,3" bitfld.long 0x38 0.--1. "CPU_TARGETS0,CPU_TARGETS0" "0,1,2,3" line.long 0x3C "GICD_ITARGETSR23,GICD interrupt processor target register 23" bitfld.long 0x3C 24.--25. "CPU_TARGETS3,CPU_TARGETS3" "0,1,2,3" bitfld.long 0x3C 16.--17. "CPU_TARGETS2,CPU_TARGETS2" "0,1,2,3" bitfld.long 0x3C 8.--9. "CPU_TARGETS1,CPU_TARGETS1" "0,1,2,3" bitfld.long 0x3C 0.--1. "CPU_TARGETS0,CPU_TARGETS0" "0,1,2,3" line.long 0x40 "GICD_ITARGETSR24,GICD interrupt processor target register 24" bitfld.long 0x40 24.--25. "CPU_TARGETS3,CPU_TARGETS3" "0,1,2,3" bitfld.long 0x40 16.--17. "CPU_TARGETS2,CPU_TARGETS2" "0,1,2,3" bitfld.long 0x40 8.--9. "CPU_TARGETS1,CPU_TARGETS1" "0,1,2,3" bitfld.long 0x40 0.--1. "CPU_TARGETS0,CPU_TARGETS0" "0,1,2,3" line.long 0x44 "GICD_ITARGETSR25,GICD interrupt processor target register 25" bitfld.long 0x44 24.--25. "CPU_TARGETS3,CPU_TARGETS3" "0,1,2,3" bitfld.long 0x44 16.--17. "CPU_TARGETS2,CPU_TARGETS2" "0,1,2,3" bitfld.long 0x44 8.--9. "CPU_TARGETS1,CPU_TARGETS1" "0,1,2,3" bitfld.long 0x44 0.--1. "CPU_TARGETS0,CPU_TARGETS0" "0,1,2,3" line.long 0x48 "GICD_ITARGETSR26,GICD interrupt processor target register 26" bitfld.long 0x48 24.--25. "CPU_TARGETS3,CPU_TARGETS3" "0,1,2,3" bitfld.long 0x48 16.--17. "CPU_TARGETS2,CPU_TARGETS2" "0,1,2,3" bitfld.long 0x48 8.--9. "CPU_TARGETS1,CPU_TARGETS1" "0,1,2,3" bitfld.long 0x48 0.--1. "CPU_TARGETS0,CPU_TARGETS0" "0,1,2,3" line.long 0x4C "GICD_ITARGETSR27,GICD interrupt processor target register 27" bitfld.long 0x4C 24.--25. "CPU_TARGETS3,CPU_TARGETS3" "0,1,2,3" bitfld.long 0x4C 16.--17. "CPU_TARGETS2,CPU_TARGETS2" "0,1,2,3" bitfld.long 0x4C 8.--9. "CPU_TARGETS1,CPU_TARGETS1" "0,1,2,3" bitfld.long 0x4C 0.--1. "CPU_TARGETS0,CPU_TARGETS0" "0,1,2,3" line.long 0x50 "GICD_ITARGETSR28,GICD interrupt processor target register 28" bitfld.long 0x50 24.--25. "CPU_TARGETS3,CPU_TARGETS3" "0,1,2,3" bitfld.long 0x50 16.--17. "CPU_TARGETS2,CPU_TARGETS2" "0,1,2,3" bitfld.long 0x50 8.--9. "CPU_TARGETS1,CPU_TARGETS1" "0,1,2,3" bitfld.long 0x50 0.--1. "CPU_TARGETS0,CPU_TARGETS0" "0,1,2,3" line.long 0x54 "GICD_ITARGETSR29,GICD interrupt processor target register 29" bitfld.long 0x54 24.--25. "CPU_TARGETS3,CPU_TARGETS3" "0,1,2,3" bitfld.long 0x54 16.--17. "CPU_TARGETS2,CPU_TARGETS2" "0,1,2,3" bitfld.long 0x54 8.--9. "CPU_TARGETS1,CPU_TARGETS1" "0,1,2,3" bitfld.long 0x54 0.--1. "CPU_TARGETS0,CPU_TARGETS0" "0,1,2,3" line.long 0x58 "GICD_ITARGETSR30,GICD interrupt processor target register 30" bitfld.long 0x58 24.--25. "CPU_TARGETS3,CPU_TARGETS3" "0,1,2,3" bitfld.long 0x58 16.--17. "CPU_TARGETS2,CPU_TARGETS2" "0,1,2,3" bitfld.long 0x58 8.--9. "CPU_TARGETS1,CPU_TARGETS1" "0,1,2,3" bitfld.long 0x58 0.--1. "CPU_TARGETS0,CPU_TARGETS0" "0,1,2,3" line.long 0x5C "GICD_ITARGETSR31,GICD interrupt processor target register 31" bitfld.long 0x5C 24.--25. "CPU_TARGETS3,CPU_TARGETS3" "0,1,2,3" bitfld.long 0x5C 16.--17. "CPU_TARGETS2,CPU_TARGETS2" "0,1,2,3" bitfld.long 0x5C 8.--9. "CPU_TARGETS1,CPU_TARGETS1" "0,1,2,3" bitfld.long 0x5C 0.--1. "CPU_TARGETS0,CPU_TARGETS0" "0,1,2,3" line.long 0x60 "GICD_ITARGETSR32,GICD interrupt processor target register 32" bitfld.long 0x60 24.--25. "CPU_TARGETS3,CPU_TARGETS3" "0,1,2,3" bitfld.long 0x60 16.--17. "CPU_TARGETS2,CPU_TARGETS2" "0,1,2,3" bitfld.long 0x60 8.--9. "CPU_TARGETS1,CPU_TARGETS1" "0,1,2,3" bitfld.long 0x60 0.--1. "CPU_TARGETS0,CPU_TARGETS0" "0,1,2,3" line.long 0x64 "GICD_ITARGETSR33,GICD interrupt processor target register 33" bitfld.long 0x64 24.--25. "CPU_TARGETS3,CPU_TARGETS3" "0,1,2,3" bitfld.long 0x64 16.--17. "CPU_TARGETS2,CPU_TARGETS2" "0,1,2,3" bitfld.long 0x64 8.--9. "CPU_TARGETS1,CPU_TARGETS1" "0,1,2,3" bitfld.long 0x64 0.--1. "CPU_TARGETS0,CPU_TARGETS0" "0,1,2,3" line.long 0x68 "GICD_ITARGETSR34,GICD interrupt processor target register 34" bitfld.long 0x68 24.--25. "CPU_TARGETS3,CPU_TARGETS3" "0,1,2,3" bitfld.long 0x68 16.--17. "CPU_TARGETS2,CPU_TARGETS2" "0,1,2,3" bitfld.long 0x68 8.--9. "CPU_TARGETS1,CPU_TARGETS1" "0,1,2,3" bitfld.long 0x68 0.--1. "CPU_TARGETS0,CPU_TARGETS0" "0,1,2,3" line.long 0x6C "GICD_ITARGETSR35,GICD interrupt processor target register 35" bitfld.long 0x6C 24.--25. "CPU_TARGETS3,CPU_TARGETS3" "0,1,2,3" bitfld.long 0x6C 16.--17. "CPU_TARGETS2,CPU_TARGETS2" "0,1,2,3" bitfld.long 0x6C 8.--9. "CPU_TARGETS1,CPU_TARGETS1" "0,1,2,3" bitfld.long 0x6C 0.--1. "CPU_TARGETS0,CPU_TARGETS0" "0,1,2,3" line.long 0x70 "GICD_ITARGETSR36,GICD interrupt processor target register 36" bitfld.long 0x70 24.--25. "CPU_TARGETS3,CPU_TARGETS3" "0,1,2,3" bitfld.long 0x70 16.--17. "CPU_TARGETS2,CPU_TARGETS2" "0,1,2,3" bitfld.long 0x70 8.--9. "CPU_TARGETS1,CPU_TARGETS1" "0,1,2,3" bitfld.long 0x70 0.--1. "CPU_TARGETS0,CPU_TARGETS0" "0,1,2,3" line.long 0x74 "GICD_ITARGETSR37,GICD interrupt processor target register 37" bitfld.long 0x74 24.--25. "CPU_TARGETS3,CPU_TARGETS3" "0,1,2,3" bitfld.long 0x74 16.--17. "CPU_TARGETS2,CPU_TARGETS2" "0,1,2,3" bitfld.long 0x74 8.--9. "CPU_TARGETS1,CPU_TARGETS1" "0,1,2,3" bitfld.long 0x74 0.--1. "CPU_TARGETS0,CPU_TARGETS0" "0,1,2,3" line.long 0x78 "GICD_ITARGETSR38,GICD interrupt processor target register 38" bitfld.long 0x78 24.--25. "CPU_TARGETS3,CPU_TARGETS3" "0,1,2,3" bitfld.long 0x78 16.--17. "CPU_TARGETS2,CPU_TARGETS2" "0,1,2,3" bitfld.long 0x78 8.--9. "CPU_TARGETS1,CPU_TARGETS1" "0,1,2,3" bitfld.long 0x78 0.--1. "CPU_TARGETS0,CPU_TARGETS0" "0,1,2,3" line.long 0x7C "GICD_ITARGETSR39,GICD interrupt processor target register 39" bitfld.long 0x7C 24.--25. "CPU_TARGETS3,CPU_TARGETS3" "0,1,2,3" bitfld.long 0x7C 16.--17. "CPU_TARGETS2,CPU_TARGETS2" "0,1,2,3" bitfld.long 0x7C 8.--9. "CPU_TARGETS1,CPU_TARGETS1" "0,1,2,3" bitfld.long 0x7C 0.--1. "CPU_TARGETS0,CPU_TARGETS0" "0,1,2,3" line.long 0x80 "GICD_ITARGETSR40,GICD interrupt processor target register 40" bitfld.long 0x80 24.--25. "CPU_TARGETS3,CPU_TARGETS3" "0,1,2,3" bitfld.long 0x80 16.--17. "CPU_TARGETS2,CPU_TARGETS2" "0,1,2,3" bitfld.long 0x80 8.--9. "CPU_TARGETS1,CPU_TARGETS1" "0,1,2,3" bitfld.long 0x80 0.--1. "CPU_TARGETS0,CPU_TARGETS0" "0,1,2,3" line.long 0x84 "GICD_ITARGETSR41,GICD interrupt processor target register 41" bitfld.long 0x84 24.--25. "CPU_TARGETS3,CPU_TARGETS3" "0,1,2,3" bitfld.long 0x84 16.--17. "CPU_TARGETS2,CPU_TARGETS2" "0,1,2,3" bitfld.long 0x84 8.--9. "CPU_TARGETS1,CPU_TARGETS1" "0,1,2,3" bitfld.long 0x84 0.--1. "CPU_TARGETS0,CPU_TARGETS0" "0,1,2,3" line.long 0x88 "GICD_ITARGETSR42,GICD interrupt processor target register 42" bitfld.long 0x88 24.--25. "CPU_TARGETS3,CPU_TARGETS3" "0,1,2,3" bitfld.long 0x88 16.--17. "CPU_TARGETS2,CPU_TARGETS2" "0,1,2,3" bitfld.long 0x88 8.--9. "CPU_TARGETS1,CPU_TARGETS1" "0,1,2,3" bitfld.long 0x88 0.--1. "CPU_TARGETS0,CPU_TARGETS0" "0,1,2,3" line.long 0x8C "GICD_ITARGETSR43,GICD interrupt processor target register 43" bitfld.long 0x8C 24.--25. "CPU_TARGETS3,CPU_TARGETS3" "0,1,2,3" bitfld.long 0x8C 16.--17. "CPU_TARGETS2,CPU_TARGETS2" "0,1,2,3" bitfld.long 0x8C 8.--9. "CPU_TARGETS1,CPU_TARGETS1" "0,1,2,3" bitfld.long 0x8C 0.--1. "CPU_TARGETS0,CPU_TARGETS0" "0,1,2,3" line.long 0x90 "GICD_ITARGETSR44,GICD interrupt processor target register 44" bitfld.long 0x90 24.--25. "CPU_TARGETS3,CPU_TARGETS3" "0,1,2,3" bitfld.long 0x90 16.--17. "CPU_TARGETS2,CPU_TARGETS2" "0,1,2,3" bitfld.long 0x90 8.--9. "CPU_TARGETS1,CPU_TARGETS1" "0,1,2,3" bitfld.long 0x90 0.--1. "CPU_TARGETS0,CPU_TARGETS0" "0,1,2,3" line.long 0x94 "GICD_ITARGETSR45,GICD interrupt processor target register 45" bitfld.long 0x94 24.--25. "CPU_TARGETS3,CPU_TARGETS3" "0,1,2,3" bitfld.long 0x94 16.--17. "CPU_TARGETS2,CPU_TARGETS2" "0,1,2,3" bitfld.long 0x94 8.--9. "CPU_TARGETS1,CPU_TARGETS1" "0,1,2,3" bitfld.long 0x94 0.--1. "CPU_TARGETS0,CPU_TARGETS0" "0,1,2,3" line.long 0x98 "GICD_ITARGETSR46,GICD interrupt processor target register 46" bitfld.long 0x98 24.--25. "CPU_TARGETS3,CPU_TARGETS3" "0,1,2,3" bitfld.long 0x98 16.--17. "CPU_TARGETS2,CPU_TARGETS2" "0,1,2,3" bitfld.long 0x98 8.--9. "CPU_TARGETS1,CPU_TARGETS1" "0,1,2,3" bitfld.long 0x98 0.--1. "CPU_TARGETS0,CPU_TARGETS0" "0,1,2,3" line.long 0x9C "GICD_ITARGETSR47,GICD interrupt processor target register 47" bitfld.long 0x9C 24.--25. "CPU_TARGETS3,CPU_TARGETS3" "0,1,2,3" bitfld.long 0x9C 16.--17. "CPU_TARGETS2,CPU_TARGETS2" "0,1,2,3" bitfld.long 0x9C 8.--9. "CPU_TARGETS1,CPU_TARGETS1" "0,1,2,3" bitfld.long 0x9C 0.--1. "CPU_TARGETS0,CPU_TARGETS0" "0,1,2,3" line.long 0xA0 "GICD_ITARGETSR48,GICD interrupt processor target register 48" bitfld.long 0xA0 24.--25. "CPU_TARGETS3,CPU_TARGETS3" "0,1,2,3" bitfld.long 0xA0 16.--17. "CPU_TARGETS2,CPU_TARGETS2" "0,1,2,3" bitfld.long 0xA0 8.--9. "CPU_TARGETS1,CPU_TARGETS1" "0,1,2,3" bitfld.long 0xA0 0.--1. "CPU_TARGETS0,CPU_TARGETS0" "0,1,2,3" line.long 0xA4 "GICD_ITARGETSR49,GICD interrupt processor target register 49" bitfld.long 0xA4 24.--25. "CPU_TARGETS3,CPU_TARGETS3" "0,1,2,3" bitfld.long 0xA4 16.--17. "CPU_TARGETS2,CPU_TARGETS2" "0,1,2,3" bitfld.long 0xA4 8.--9. "CPU_TARGETS1,CPU_TARGETS1" "0,1,2,3" bitfld.long 0xA4 0.--1. "CPU_TARGETS0,CPU_TARGETS0" "0,1,2,3" line.long 0xA8 "GICD_ITARGETSR50,GICD interrupt processor target register 50" bitfld.long 0xA8 24.--25. "CPU_TARGETS3,CPU_TARGETS3" "0,1,2,3" bitfld.long 0xA8 16.--17. "CPU_TARGETS2,CPU_TARGETS2" "0,1,2,3" bitfld.long 0xA8 8.--9. "CPU_TARGETS1,CPU_TARGETS1" "0,1,2,3" bitfld.long 0xA8 0.--1. "CPU_TARGETS0,CPU_TARGETS0" "0,1,2,3" line.long 0xAC "GICD_ITARGETSR51,GICD interrupt processor target register 51" bitfld.long 0xAC 24.--25. "CPU_TARGETS3,CPU_TARGETS3" "0,1,2,3" bitfld.long 0xAC 16.--17. "CPU_TARGETS2,CPU_TARGETS2" "0,1,2,3" bitfld.long 0xAC 8.--9. "CPU_TARGETS1,CPU_TARGETS1" "0,1,2,3" bitfld.long 0xAC 0.--1. "CPU_TARGETS0,CPU_TARGETS0" "0,1,2,3" line.long 0xB0 "GICD_ITARGETSR52,GICD interrupt processor target register 52" bitfld.long 0xB0 24.--25. "CPU_TARGETS3,CPU_TARGETS3" "0,1,2,3" bitfld.long 0xB0 16.--17. "CPU_TARGETS2,CPU_TARGETS2" "0,1,2,3" bitfld.long 0xB0 8.--9. "CPU_TARGETS1,CPU_TARGETS1" "0,1,2,3" bitfld.long 0xB0 0.--1. "CPU_TARGETS0,CPU_TARGETS0" "0,1,2,3" line.long 0xB4 "GICD_ITARGETSR53,GICD interrupt processor target register 53" bitfld.long 0xB4 24.--25. "CPU_TARGETS3,CPU_TARGETS3" "0,1,2,3" bitfld.long 0xB4 16.--17. "CPU_TARGETS2,CPU_TARGETS2" "0,1,2,3" bitfld.long 0xB4 8.--9. "CPU_TARGETS1,CPU_TARGETS1" "0,1,2,3" bitfld.long 0xB4 0.--1. "CPU_TARGETS0,CPU_TARGETS0" "0,1,2,3" line.long 0xB8 "GICD_ITARGETSR54,GICD interrupt processor target register 54" bitfld.long 0xB8 24.--25. "CPU_TARGETS3,CPU_TARGETS3" "0,1,2,3" bitfld.long 0xB8 16.--17. "CPU_TARGETS2,CPU_TARGETS2" "0,1,2,3" bitfld.long 0xB8 8.--9. "CPU_TARGETS1,CPU_TARGETS1" "0,1,2,3" bitfld.long 0xB8 0.--1. "CPU_TARGETS0,CPU_TARGETS0" "0,1,2,3" line.long 0xBC "GICD_ITARGETSR55,GICD interrupt processor target register 55" bitfld.long 0xBC 24.--25. "CPU_TARGETS3,CPU_TARGETS3" "0,1,2,3" bitfld.long 0xBC 16.--17. "CPU_TARGETS2,CPU_TARGETS2" "0,1,2,3" bitfld.long 0xBC 8.--9. "CPU_TARGETS1,CPU_TARGETS1" "0,1,2,3" bitfld.long 0xBC 0.--1. "CPU_TARGETS0,CPU_TARGETS0" "0,1,2,3" line.long 0xC0 "GICD_ITARGETSR56,GICD interrupt processor target register 56" bitfld.long 0xC0 24.--25. "CPU_TARGETS3,CPU_TARGETS3" "0,1,2,3" bitfld.long 0xC0 16.--17. "CPU_TARGETS2,CPU_TARGETS2" "0,1,2,3" bitfld.long 0xC0 8.--9. "CPU_TARGETS1,CPU_TARGETS1" "0,1,2,3" bitfld.long 0xC0 0.--1. "CPU_TARGETS0,CPU_TARGETS0" "0,1,2,3" line.long 0xC4 "GICD_ITARGETSR57,GICD interrupt processor target register 57" bitfld.long 0xC4 24.--25. "CPU_TARGETS3,CPU_TARGETS3" "0,1,2,3" bitfld.long 0xC4 16.--17. "CPU_TARGETS2,CPU_TARGETS2" "0,1,2,3" bitfld.long 0xC4 8.--9. "CPU_TARGETS1,CPU_TARGETS1" "0,1,2,3" bitfld.long 0xC4 0.--1. "CPU_TARGETS0,CPU_TARGETS0" "0,1,2,3" line.long 0xC8 "GICD_ITARGETSR58,GICD interrupt processor target register 58" bitfld.long 0xC8 24.--25. "CPU_TARGETS3,CPU_TARGETS3" "0,1,2,3" bitfld.long 0xC8 16.--17. "CPU_TARGETS2,CPU_TARGETS2" "0,1,2,3" bitfld.long 0xC8 8.--9. "CPU_TARGETS1,CPU_TARGETS1" "0,1,2,3" bitfld.long 0xC8 0.--1. "CPU_TARGETS0,CPU_TARGETS0" "0,1,2,3" line.long 0xCC "GICD_ITARGETSR59,GICD interrupt processor target register 59" bitfld.long 0xCC 24.--25. "CPU_TARGETS3,CPU_TARGETS3" "0,1,2,3" bitfld.long 0xCC 16.--17. "CPU_TARGETS2,CPU_TARGETS2" "0,1,2,3" bitfld.long 0xCC 8.--9. "CPU_TARGETS1,CPU_TARGETS1" "0,1,2,3" bitfld.long 0xCC 0.--1. "CPU_TARGETS0,CPU_TARGETS0" "0,1,2,3" line.long 0xD0 "GICD_ITARGETSR60,GICD interrupt processor target register 60" bitfld.long 0xD0 24.--25. "CPU_TARGETS3,CPU_TARGETS3" "0,1,2,3" bitfld.long 0xD0 16.--17. "CPU_TARGETS2,CPU_TARGETS2" "0,1,2,3" bitfld.long 0xD0 8.--9. "CPU_TARGETS1,CPU_TARGETS1" "0,1,2,3" bitfld.long 0xD0 0.--1. "CPU_TARGETS0,CPU_TARGETS0" "0,1,2,3" line.long 0xD4 "GICD_ITARGETSR61,GICD interrupt processor target register 61" bitfld.long 0xD4 24.--25. "CPU_TARGETS3,CPU_TARGETS3" "0,1,2,3" bitfld.long 0xD4 16.--17. "CPU_TARGETS2,CPU_TARGETS2" "0,1,2,3" bitfld.long 0xD4 8.--9. "CPU_TARGETS1,CPU_TARGETS1" "0,1,2,3" bitfld.long 0xD4 0.--1. "CPU_TARGETS0,CPU_TARGETS0" "0,1,2,3" line.long 0xD8 "GICD_ITARGETSR62,GICD interrupt processor target register 62" bitfld.long 0xD8 24.--25. "CPU_TARGETS3,CPU_TARGETS3" "0,1,2,3" bitfld.long 0xD8 16.--17. "CPU_TARGETS2,CPU_TARGETS2" "0,1,2,3" bitfld.long 0xD8 8.--9. "CPU_TARGETS1,CPU_TARGETS1" "0,1,2,3" bitfld.long 0xD8 0.--1. "CPU_TARGETS0,CPU_TARGETS0" "0,1,2,3" line.long 0xDC "GICD_ITARGETSR63,GICD interrupt processor target register 63" bitfld.long 0xDC 24.--25. "CPU_TARGETS3,CPU_TARGETS3" "0,1,2,3" bitfld.long 0xDC 16.--17. "CPU_TARGETS2,CPU_TARGETS2" "0,1,2,3" bitfld.long 0xDC 8.--9. "CPU_TARGETS1,CPU_TARGETS1" "0,1,2,3" bitfld.long 0xDC 0.--1. "CPU_TARGETS0,CPU_TARGETS0" "0,1,2,3" line.long 0xE0 "GICD_ITARGETSR64,GICD interrupt processor target register 64" bitfld.long 0xE0 24.--25. "CPU_TARGETS3,CPU_TARGETS3" "0,1,2,3" bitfld.long 0xE0 16.--17. "CPU_TARGETS2,CPU_TARGETS2" "0,1,2,3" bitfld.long 0xE0 8.--9. "CPU_TARGETS1,CPU_TARGETS1" "0,1,2,3" bitfld.long 0xE0 0.--1. "CPU_TARGETS0,CPU_TARGETS0" "0,1,2,3" line.long 0xE4 "GICD_ITARGETSR65,GICD interrupt processor target register 65" bitfld.long 0xE4 24.--25. "CPU_TARGETS3,CPU_TARGETS3" "0,1,2,3" bitfld.long 0xE4 16.--17. "CPU_TARGETS2,CPU_TARGETS2" "0,1,2,3" bitfld.long 0xE4 8.--9. "CPU_TARGETS1,CPU_TARGETS1" "0,1,2,3" bitfld.long 0xE4 0.--1. "CPU_TARGETS0,CPU_TARGETS0" "0,1,2,3" line.long 0xE8 "GICD_ITARGETSR66,GICD interrupt processor target register 66" bitfld.long 0xE8 24.--25. "CPU_TARGETS3,CPU_TARGETS3" "0,1,2,3" bitfld.long 0xE8 16.--17. "CPU_TARGETS2,CPU_TARGETS2" "0,1,2,3" bitfld.long 0xE8 8.--9. "CPU_TARGETS1,CPU_TARGETS1" "0,1,2,3" bitfld.long 0xE8 0.--1. "CPU_TARGETS0,CPU_TARGETS0" "0,1,2,3" line.long 0xEC "GICD_ITARGETSR67,GICD interrupt processor target register 67" bitfld.long 0xEC 24.--25. "CPU_TARGETS3,CPU_TARGETS3" "0,1,2,3" bitfld.long 0xEC 16.--17. "CPU_TARGETS2,CPU_TARGETS2" "0,1,2,3" bitfld.long 0xEC 8.--9. "CPU_TARGETS1,CPU_TARGETS1" "0,1,2,3" bitfld.long 0xEC 0.--1. "CPU_TARGETS0,CPU_TARGETS0" "0,1,2,3" line.long 0xF0 "GICD_ITARGETSR68,GICD interrupt processor target register 68" bitfld.long 0xF0 24.--25. "CPU_TARGETS3,CPU_TARGETS3" "0,1,2,3" bitfld.long 0xF0 16.--17. "CPU_TARGETS2,CPU_TARGETS2" "0,1,2,3" bitfld.long 0xF0 8.--9. "CPU_TARGETS1,CPU_TARGETS1" "0,1,2,3" bitfld.long 0xF0 0.--1. "CPU_TARGETS0,CPU_TARGETS0" "0,1,2,3" line.long 0xF4 "GICD_ITARGETSR69,GICD interrupt processor target register 69" bitfld.long 0xF4 24.--25. "CPU_TARGETS3,CPU_TARGETS3" "0,1,2,3" bitfld.long 0xF4 16.--17. "CPU_TARGETS2,CPU_TARGETS2" "0,1,2,3" bitfld.long 0xF4 8.--9. "CPU_TARGETS1,CPU_TARGETS1" "0,1,2,3" bitfld.long 0xF4 0.--1. "CPU_TARGETS0,CPU_TARGETS0" "0,1,2,3" line.long 0xF8 "GICD_ITARGETSR70,GICD interrupt processor target register 70" bitfld.long 0xF8 24.--25. "CPU_TARGETS3,CPU_TARGETS3" "0,1,2,3" bitfld.long 0xF8 16.--17. "CPU_TARGETS2,CPU_TARGETS2" "0,1,2,3" bitfld.long 0xF8 8.--9. "CPU_TARGETS1,CPU_TARGETS1" "0,1,2,3" bitfld.long 0xF8 0.--1. "CPU_TARGETS0,CPU_TARGETS0" "0,1,2,3" line.long 0xFC "GICD_ITARGETSR71,GICD interrupt processor target register 71" bitfld.long 0xFC 24.--25. "CPU_TARGETS3,CPU_TARGETS3" "0,1,2,3" bitfld.long 0xFC 16.--17. "CPU_TARGETS2,CPU_TARGETS2" "0,1,2,3" bitfld.long 0xFC 8.--9. "CPU_TARGETS1,CPU_TARGETS1" "0,1,2,3" bitfld.long 0xFC 0.--1. "CPU_TARGETS0,CPU_TARGETS0" "0,1,2,3" group.long 0xC00++0x47 line.long 0x0 "GICD_ICFGR0,GICD interrupt configuration register" bitfld.long 0x0 30.--31. "INT_CONFIG15,INT_CONFIG15" "0,1,2,3" bitfld.long 0x0 28.--29. "INT_CONFIG14,INT_CONFIG14" "0,1,2,3" bitfld.long 0x0 26.--27. "INT_CONFIG13,INT_CONFIG13" "0,1,2,3" bitfld.long 0x0 24.--25. "INT_CONFIG12,INT_CONFIG12" "0,1,2,3" bitfld.long 0x0 22.--23. "INT_CONFIG11,INT_CONFIG11" "0,1,2,3" newline bitfld.long 0x0 20.--21. "INT_CONFIG10,INT_CONFIG10" "0,1,2,3" bitfld.long 0x0 18.--19. "INT_CONFIG9,INT_CONFIG9" "0,1,2,3" bitfld.long 0x0 16.--17. "INT_CONFIG8,INT_CONFIG8" "0,1,2,3" bitfld.long 0x0 14.--15. "INT_CONFIG7,INT_CONFIG7" "0,1,2,3" bitfld.long 0x0 12.--13. "INT_CONFIG6,INT_CONFIG6" "0,1,2,3" newline bitfld.long 0x0 10.--11. "INT_CONFIG5,INT_CONFIG5" "0,1,2,3" bitfld.long 0x0 8.--9. "INT_CONFIG4,INT_CONFIG4" "0,1,2,3" bitfld.long 0x0 6.--7. "INT_CONFIG3,INT_CONFIG3" "0,1,2,3" bitfld.long 0x0 4.--5. "INT_CONFIG2,INT_CONFIG2" "0,1,2,3" bitfld.long 0x0 2.--3. "INT_CONFIG1,INT_CONFIG1" "0,1,2,3" newline bitfld.long 0x0 0.--1. "INT_CONFIG0,INT_CONFIG0" "0,1,2,3" line.long 0x4 "GICD_ICFGR1,GICD interrupt configuration register" bitfld.long 0x4 30.--31. "INT_CONFIG15,INT_CONFIG15" "0,1,2,3" bitfld.long 0x4 28.--29. "INT_CONFIG14,INT_CONFIG14" "0,1,2,3" bitfld.long 0x4 26.--27. "INT_CONFIG13,INT_CONFIG13" "0,1,2,3" bitfld.long 0x4 24.--25. "INT_CONFIG12,INT_CONFIG12" "0,1,2,3" bitfld.long 0x4 22.--23. "INT_CONFIG11,INT_CONFIG11" "0,1,2,3" newline bitfld.long 0x4 20.--21. "INT_CONFIG10,INT_CONFIG10" "0,1,2,3" bitfld.long 0x4 18.--19. "INT_CONFIG9,INT_CONFIG9" "0,1,2,3" bitfld.long 0x4 16.--17. "INT_CONFIG8,INT_CONFIG8" "0,1,2,3" bitfld.long 0x4 14.--15. "INT_CONFIG7,INT_CONFIG7" "0,1,2,3" bitfld.long 0x4 12.--13. "INT_CONFIG6,INT_CONFIG6" "0,1,2,3" newline bitfld.long 0x4 10.--11. "INT_CONFIG5,INT_CONFIG5" "0,1,2,3" bitfld.long 0x4 8.--9. "INT_CONFIG4,INT_CONFIG4" "0,1,2,3" bitfld.long 0x4 6.--7. "INT_CONFIG3,INT_CONFIG3" "0,1,2,3" bitfld.long 0x4 4.--5. "INT_CONFIG2,INT_CONFIG2" "0,1,2,3" bitfld.long 0x4 2.--3. "INT_CONFIG1,INT_CONFIG1" "0,1,2,3" newline bitfld.long 0x4 0.--1. "INT_CONFIG0,INT_CONFIG0" "0,1,2,3" line.long 0x8 "GICD_ICFGR2,GICD interrupt configuration register 2" bitfld.long 0x8 30.--31. "INT_CONFIG15,INT_CONFIG15" "0,1,2,3" bitfld.long 0x8 28.--29. "INT_CONFIG14,INT_CONFIG14" "0,1,2,3" bitfld.long 0x8 26.--27. "INT_CONFIG13,INT_CONFIG13" "0,1,2,3" bitfld.long 0x8 24.--25. "INT_CONFIG12,INT_CONFIG12" "0,1,2,3" bitfld.long 0x8 22.--23. "INT_CONFIG11,INT_CONFIG11" "0,1,2,3" newline bitfld.long 0x8 20.--21. "INT_CONFIG10,INT_CONFIG10" "0,1,2,3" bitfld.long 0x8 18.--19. "INT_CONFIG9,INT_CONFIG9" "0,1,2,3" bitfld.long 0x8 16.--17. "INT_CONFIG8,INT_CONFIG8" "0,1,2,3" bitfld.long 0x8 14.--15. "INT_CONFIG7,INT_CONFIG7" "0,1,2,3" bitfld.long 0x8 12.--13. "INT_CONFIG6,INT_CONFIG6" "0,1,2,3" newline bitfld.long 0x8 10.--11. "INT_CONFIG5,INT_CONFIG5" "0,1,2,3" bitfld.long 0x8 8.--9. "INT_CONFIG4,INT_CONFIG4" "0,1,2,3" bitfld.long 0x8 6.--7. "INT_CONFIG3,INT_CONFIG3" "0,1,2,3" bitfld.long 0x8 4.--5. "INT_CONFIG2,INT_CONFIG2" "0,1,2,3" bitfld.long 0x8 2.--3. "INT_CONFIG1,INT_CONFIG1" "0,1,2,3" newline bitfld.long 0x8 0.--1. "INT_CONFIG0,INT_CONFIG0" "0,1,2,3" line.long 0xC "GICD_ICFGR3,GICD interrupt configuration register 3" bitfld.long 0xC 30.--31. "INT_CONFIG15,INT_CONFIG15" "0,1,2,3" bitfld.long 0xC 28.--29. "INT_CONFIG14,INT_CONFIG14" "0,1,2,3" bitfld.long 0xC 26.--27. "INT_CONFIG13,INT_CONFIG13" "0,1,2,3" bitfld.long 0xC 24.--25. "INT_CONFIG12,INT_CONFIG12" "0,1,2,3" bitfld.long 0xC 22.--23. "INT_CONFIG11,INT_CONFIG11" "0,1,2,3" newline bitfld.long 0xC 20.--21. "INT_CONFIG10,INT_CONFIG10" "0,1,2,3" bitfld.long 0xC 18.--19. "INT_CONFIG9,INT_CONFIG9" "0,1,2,3" bitfld.long 0xC 16.--17. "INT_CONFIG8,INT_CONFIG8" "0,1,2,3" bitfld.long 0xC 14.--15. "INT_CONFIG7,INT_CONFIG7" "0,1,2,3" bitfld.long 0xC 12.--13. "INT_CONFIG6,INT_CONFIG6" "0,1,2,3" newline bitfld.long 0xC 10.--11. "INT_CONFIG5,INT_CONFIG5" "0,1,2,3" bitfld.long 0xC 8.--9. "INT_CONFIG4,INT_CONFIG4" "0,1,2,3" bitfld.long 0xC 6.--7. "INT_CONFIG3,INT_CONFIG3" "0,1,2,3" bitfld.long 0xC 4.--5. "INT_CONFIG2,INT_CONFIG2" "0,1,2,3" bitfld.long 0xC 2.--3. "INT_CONFIG1,INT_CONFIG1" "0,1,2,3" newline bitfld.long 0xC 0.--1. "INT_CONFIG0,INT_CONFIG0" "0,1,2,3" line.long 0x10 "GICD_ICFGR4,GICD interrupt configuration register 4" bitfld.long 0x10 30.--31. "INT_CONFIG15,INT_CONFIG15" "0,1,2,3" bitfld.long 0x10 28.--29. "INT_CONFIG14,INT_CONFIG14" "0,1,2,3" bitfld.long 0x10 26.--27. "INT_CONFIG13,INT_CONFIG13" "0,1,2,3" bitfld.long 0x10 24.--25. "INT_CONFIG12,INT_CONFIG12" "0,1,2,3" bitfld.long 0x10 22.--23. "INT_CONFIG11,INT_CONFIG11" "0,1,2,3" newline bitfld.long 0x10 20.--21. "INT_CONFIG10,INT_CONFIG10" "0,1,2,3" bitfld.long 0x10 18.--19. "INT_CONFIG9,INT_CONFIG9" "0,1,2,3" bitfld.long 0x10 16.--17. "INT_CONFIG8,INT_CONFIG8" "0,1,2,3" bitfld.long 0x10 14.--15. "INT_CONFIG7,INT_CONFIG7" "0,1,2,3" bitfld.long 0x10 12.--13. "INT_CONFIG6,INT_CONFIG6" "0,1,2,3" newline bitfld.long 0x10 10.--11. "INT_CONFIG5,INT_CONFIG5" "0,1,2,3" bitfld.long 0x10 8.--9. "INT_CONFIG4,INT_CONFIG4" "0,1,2,3" bitfld.long 0x10 6.--7. "INT_CONFIG3,INT_CONFIG3" "0,1,2,3" bitfld.long 0x10 4.--5. "INT_CONFIG2,INT_CONFIG2" "0,1,2,3" bitfld.long 0x10 2.--3. "INT_CONFIG1,INT_CONFIG1" "0,1,2,3" newline bitfld.long 0x10 0.--1. "INT_CONFIG0,INT_CONFIG0" "0,1,2,3" line.long 0x14 "GICD_ICFGR5,GICD interrupt configuration register 5" bitfld.long 0x14 30.--31. "INT_CONFIG15,INT_CONFIG15" "0,1,2,3" bitfld.long 0x14 28.--29. "INT_CONFIG14,INT_CONFIG14" "0,1,2,3" bitfld.long 0x14 26.--27. "INT_CONFIG13,INT_CONFIG13" "0,1,2,3" bitfld.long 0x14 24.--25. "INT_CONFIG12,INT_CONFIG12" "0,1,2,3" bitfld.long 0x14 22.--23. "INT_CONFIG11,INT_CONFIG11" "0,1,2,3" newline bitfld.long 0x14 20.--21. "INT_CONFIG10,INT_CONFIG10" "0,1,2,3" bitfld.long 0x14 18.--19. "INT_CONFIG9,INT_CONFIG9" "0,1,2,3" bitfld.long 0x14 16.--17. "INT_CONFIG8,INT_CONFIG8" "0,1,2,3" bitfld.long 0x14 14.--15. "INT_CONFIG7,INT_CONFIG7" "0,1,2,3" bitfld.long 0x14 12.--13. "INT_CONFIG6,INT_CONFIG6" "0,1,2,3" newline bitfld.long 0x14 10.--11. "INT_CONFIG5,INT_CONFIG5" "0,1,2,3" bitfld.long 0x14 8.--9. "INT_CONFIG4,INT_CONFIG4" "0,1,2,3" bitfld.long 0x14 6.--7. "INT_CONFIG3,INT_CONFIG3" "0,1,2,3" bitfld.long 0x14 4.--5. "INT_CONFIG2,INT_CONFIG2" "0,1,2,3" bitfld.long 0x14 2.--3. "INT_CONFIG1,INT_CONFIG1" "0,1,2,3" newline bitfld.long 0x14 0.--1. "INT_CONFIG0,INT_CONFIG0" "0,1,2,3" line.long 0x18 "GICD_ICFGR6,GICD interrupt configuration register 6" bitfld.long 0x18 30.--31. "INT_CONFIG15,INT_CONFIG15" "0,1,2,3" bitfld.long 0x18 28.--29. "INT_CONFIG14,INT_CONFIG14" "0,1,2,3" bitfld.long 0x18 26.--27. "INT_CONFIG13,INT_CONFIG13" "0,1,2,3" bitfld.long 0x18 24.--25. "INT_CONFIG12,INT_CONFIG12" "0,1,2,3" bitfld.long 0x18 22.--23. "INT_CONFIG11,INT_CONFIG11" "0,1,2,3" newline bitfld.long 0x18 20.--21. "INT_CONFIG10,INT_CONFIG10" "0,1,2,3" bitfld.long 0x18 18.--19. "INT_CONFIG9,INT_CONFIG9" "0,1,2,3" bitfld.long 0x18 16.--17. "INT_CONFIG8,INT_CONFIG8" "0,1,2,3" bitfld.long 0x18 14.--15. "INT_CONFIG7,INT_CONFIG7" "0,1,2,3" bitfld.long 0x18 12.--13. "INT_CONFIG6,INT_CONFIG6" "0,1,2,3" newline bitfld.long 0x18 10.--11. "INT_CONFIG5,INT_CONFIG5" "0,1,2,3" bitfld.long 0x18 8.--9. "INT_CONFIG4,INT_CONFIG4" "0,1,2,3" bitfld.long 0x18 6.--7. "INT_CONFIG3,INT_CONFIG3" "0,1,2,3" bitfld.long 0x18 4.--5. "INT_CONFIG2,INT_CONFIG2" "0,1,2,3" bitfld.long 0x18 2.--3. "INT_CONFIG1,INT_CONFIG1" "0,1,2,3" newline bitfld.long 0x18 0.--1. "INT_CONFIG0,INT_CONFIG0" "0,1,2,3" line.long 0x1C "GICD_ICFGR7,GICD interrupt configuration register 7" bitfld.long 0x1C 30.--31. "INT_CONFIG15,INT_CONFIG15" "0,1,2,3" bitfld.long 0x1C 28.--29. "INT_CONFIG14,INT_CONFIG14" "0,1,2,3" bitfld.long 0x1C 26.--27. "INT_CONFIG13,INT_CONFIG13" "0,1,2,3" bitfld.long 0x1C 24.--25. "INT_CONFIG12,INT_CONFIG12" "0,1,2,3" bitfld.long 0x1C 22.--23. "INT_CONFIG11,INT_CONFIG11" "0,1,2,3" newline bitfld.long 0x1C 20.--21. "INT_CONFIG10,INT_CONFIG10" "0,1,2,3" bitfld.long 0x1C 18.--19. "INT_CONFIG9,INT_CONFIG9" "0,1,2,3" bitfld.long 0x1C 16.--17. "INT_CONFIG8,INT_CONFIG8" "0,1,2,3" bitfld.long 0x1C 14.--15. "INT_CONFIG7,INT_CONFIG7" "0,1,2,3" bitfld.long 0x1C 12.--13. "INT_CONFIG6,INT_CONFIG6" "0,1,2,3" newline bitfld.long 0x1C 10.--11. "INT_CONFIG5,INT_CONFIG5" "0,1,2,3" bitfld.long 0x1C 8.--9. "INT_CONFIG4,INT_CONFIG4" "0,1,2,3" bitfld.long 0x1C 6.--7. "INT_CONFIG3,INT_CONFIG3" "0,1,2,3" bitfld.long 0x1C 4.--5. "INT_CONFIG2,INT_CONFIG2" "0,1,2,3" bitfld.long 0x1C 2.--3. "INT_CONFIG1,INT_CONFIG1" "0,1,2,3" newline bitfld.long 0x1C 0.--1. "INT_CONFIG0,INT_CONFIG0" "0,1,2,3" line.long 0x20 "GICD_ICFGR8,GICD interrupt configuration register 8" bitfld.long 0x20 30.--31. "INT_CONFIG15,INT_CONFIG15" "0,1,2,3" bitfld.long 0x20 28.--29. "INT_CONFIG14,INT_CONFIG14" "0,1,2,3" bitfld.long 0x20 26.--27. "INT_CONFIG13,INT_CONFIG13" "0,1,2,3" bitfld.long 0x20 24.--25. "INT_CONFIG12,INT_CONFIG12" "0,1,2,3" bitfld.long 0x20 22.--23. "INT_CONFIG11,INT_CONFIG11" "0,1,2,3" newline bitfld.long 0x20 20.--21. "INT_CONFIG10,INT_CONFIG10" "0,1,2,3" bitfld.long 0x20 18.--19. "INT_CONFIG9,INT_CONFIG9" "0,1,2,3" bitfld.long 0x20 16.--17. "INT_CONFIG8,INT_CONFIG8" "0,1,2,3" bitfld.long 0x20 14.--15. "INT_CONFIG7,INT_CONFIG7" "0,1,2,3" bitfld.long 0x20 12.--13. "INT_CONFIG6,INT_CONFIG6" "0,1,2,3" newline bitfld.long 0x20 10.--11. "INT_CONFIG5,INT_CONFIG5" "0,1,2,3" bitfld.long 0x20 8.--9. "INT_CONFIG4,INT_CONFIG4" "0,1,2,3" bitfld.long 0x20 6.--7. "INT_CONFIG3,INT_CONFIG3" "0,1,2,3" bitfld.long 0x20 4.--5. "INT_CONFIG2,INT_CONFIG2" "0,1,2,3" bitfld.long 0x20 2.--3. "INT_CONFIG1,INT_CONFIG1" "0,1,2,3" newline bitfld.long 0x20 0.--1. "INT_CONFIG0,INT_CONFIG0" "0,1,2,3" line.long 0x24 "GICD_ICFGR9,GICD interrupt configuration register 9" bitfld.long 0x24 30.--31. "INT_CONFIG15,INT_CONFIG15" "0,1,2,3" bitfld.long 0x24 28.--29. "INT_CONFIG14,INT_CONFIG14" "0,1,2,3" bitfld.long 0x24 26.--27. "INT_CONFIG13,INT_CONFIG13" "0,1,2,3" bitfld.long 0x24 24.--25. "INT_CONFIG12,INT_CONFIG12" "0,1,2,3" bitfld.long 0x24 22.--23. "INT_CONFIG11,INT_CONFIG11" "0,1,2,3" newline bitfld.long 0x24 20.--21. "INT_CONFIG10,INT_CONFIG10" "0,1,2,3" bitfld.long 0x24 18.--19. "INT_CONFIG9,INT_CONFIG9" "0,1,2,3" bitfld.long 0x24 16.--17. "INT_CONFIG8,INT_CONFIG8" "0,1,2,3" bitfld.long 0x24 14.--15. "INT_CONFIG7,INT_CONFIG7" "0,1,2,3" bitfld.long 0x24 12.--13. "INT_CONFIG6,INT_CONFIG6" "0,1,2,3" newline bitfld.long 0x24 10.--11. "INT_CONFIG5,INT_CONFIG5" "0,1,2,3" bitfld.long 0x24 8.--9. "INT_CONFIG4,INT_CONFIG4" "0,1,2,3" bitfld.long 0x24 6.--7. "INT_CONFIG3,INT_CONFIG3" "0,1,2,3" bitfld.long 0x24 4.--5. "INT_CONFIG2,INT_CONFIG2" "0,1,2,3" bitfld.long 0x24 2.--3. "INT_CONFIG1,INT_CONFIG1" "0,1,2,3" newline bitfld.long 0x24 0.--1. "INT_CONFIG0,INT_CONFIG0" "0,1,2,3" line.long 0x28 "GICD_ICFGR10,GICD interrupt configuration register 10" bitfld.long 0x28 30.--31. "INT_CONFIG15,INT_CONFIG15" "0,1,2,3" bitfld.long 0x28 28.--29. "INT_CONFIG14,INT_CONFIG14" "0,1,2,3" bitfld.long 0x28 26.--27. "INT_CONFIG13,INT_CONFIG13" "0,1,2,3" bitfld.long 0x28 24.--25. "INT_CONFIG12,INT_CONFIG12" "0,1,2,3" bitfld.long 0x28 22.--23. "INT_CONFIG11,INT_CONFIG11" "0,1,2,3" newline bitfld.long 0x28 20.--21. "INT_CONFIG10,INT_CONFIG10" "0,1,2,3" bitfld.long 0x28 18.--19. "INT_CONFIG9,INT_CONFIG9" "0,1,2,3" bitfld.long 0x28 16.--17. "INT_CONFIG8,INT_CONFIG8" "0,1,2,3" bitfld.long 0x28 14.--15. "INT_CONFIG7,INT_CONFIG7" "0,1,2,3" bitfld.long 0x28 12.--13. "INT_CONFIG6,INT_CONFIG6" "0,1,2,3" newline bitfld.long 0x28 10.--11. "INT_CONFIG5,INT_CONFIG5" "0,1,2,3" bitfld.long 0x28 8.--9. "INT_CONFIG4,INT_CONFIG4" "0,1,2,3" bitfld.long 0x28 6.--7. "INT_CONFIG3,INT_CONFIG3" "0,1,2,3" bitfld.long 0x28 4.--5. "INT_CONFIG2,INT_CONFIG2" "0,1,2,3" bitfld.long 0x28 2.--3. "INT_CONFIG1,INT_CONFIG1" "0,1,2,3" newline bitfld.long 0x28 0.--1. "INT_CONFIG0,INT_CONFIG0" "0,1,2,3" line.long 0x2C "GICD_ICFGR11,GICD interrupt configuration register 11" bitfld.long 0x2C 30.--31. "INT_CONFIG15,INT_CONFIG15" "0,1,2,3" bitfld.long 0x2C 28.--29. "INT_CONFIG14,INT_CONFIG14" "0,1,2,3" bitfld.long 0x2C 26.--27. "INT_CONFIG13,INT_CONFIG13" "0,1,2,3" bitfld.long 0x2C 24.--25. "INT_CONFIG12,INT_CONFIG12" "0,1,2,3" bitfld.long 0x2C 22.--23. "INT_CONFIG11,INT_CONFIG11" "0,1,2,3" newline bitfld.long 0x2C 20.--21. "INT_CONFIG10,INT_CONFIG10" "0,1,2,3" bitfld.long 0x2C 18.--19. "INT_CONFIG9,INT_CONFIG9" "0,1,2,3" bitfld.long 0x2C 16.--17. "INT_CONFIG8,INT_CONFIG8" "0,1,2,3" bitfld.long 0x2C 14.--15. "INT_CONFIG7,INT_CONFIG7" "0,1,2,3" bitfld.long 0x2C 12.--13. "INT_CONFIG6,INT_CONFIG6" "0,1,2,3" newline bitfld.long 0x2C 10.--11. "INT_CONFIG5,INT_CONFIG5" "0,1,2,3" bitfld.long 0x2C 8.--9. "INT_CONFIG4,INT_CONFIG4" "0,1,2,3" bitfld.long 0x2C 6.--7. "INT_CONFIG3,INT_CONFIG3" "0,1,2,3" bitfld.long 0x2C 4.--5. "INT_CONFIG2,INT_CONFIG2" "0,1,2,3" bitfld.long 0x2C 2.--3. "INT_CONFIG1,INT_CONFIG1" "0,1,2,3" newline bitfld.long 0x2C 0.--1. "INT_CONFIG0,INT_CONFIG0" "0,1,2,3" line.long 0x30 "GICD_ICFGR12,GICD interrupt configuration register 12" bitfld.long 0x30 30.--31. "INT_CONFIG15,INT_CONFIG15" "0,1,2,3" bitfld.long 0x30 28.--29. "INT_CONFIG14,INT_CONFIG14" "0,1,2,3" bitfld.long 0x30 26.--27. "INT_CONFIG13,INT_CONFIG13" "0,1,2,3" bitfld.long 0x30 24.--25. "INT_CONFIG12,INT_CONFIG12" "0,1,2,3" bitfld.long 0x30 22.--23. "INT_CONFIG11,INT_CONFIG11" "0,1,2,3" newline bitfld.long 0x30 20.--21. "INT_CONFIG10,INT_CONFIG10" "0,1,2,3" bitfld.long 0x30 18.--19. "INT_CONFIG9,INT_CONFIG9" "0,1,2,3" bitfld.long 0x30 16.--17. "INT_CONFIG8,INT_CONFIG8" "0,1,2,3" bitfld.long 0x30 14.--15. "INT_CONFIG7,INT_CONFIG7" "0,1,2,3" bitfld.long 0x30 12.--13. "INT_CONFIG6,INT_CONFIG6" "0,1,2,3" newline bitfld.long 0x30 10.--11. "INT_CONFIG5,INT_CONFIG5" "0,1,2,3" bitfld.long 0x30 8.--9. "INT_CONFIG4,INT_CONFIG4" "0,1,2,3" bitfld.long 0x30 6.--7. "INT_CONFIG3,INT_CONFIG3" "0,1,2,3" bitfld.long 0x30 4.--5. "INT_CONFIG2,INT_CONFIG2" "0,1,2,3" bitfld.long 0x30 2.--3. "INT_CONFIG1,INT_CONFIG1" "0,1,2,3" newline bitfld.long 0x30 0.--1. "INT_CONFIG0,INT_CONFIG0" "0,1,2,3" line.long 0x34 "GICD_ICFGR13,GICD interrupt configuration register 13" bitfld.long 0x34 30.--31. "INT_CONFIG15,INT_CONFIG15" "0,1,2,3" bitfld.long 0x34 28.--29. "INT_CONFIG14,INT_CONFIG14" "0,1,2,3" bitfld.long 0x34 26.--27. "INT_CONFIG13,INT_CONFIG13" "0,1,2,3" bitfld.long 0x34 24.--25. "INT_CONFIG12,INT_CONFIG12" "0,1,2,3" bitfld.long 0x34 22.--23. "INT_CONFIG11,INT_CONFIG11" "0,1,2,3" newline bitfld.long 0x34 20.--21. "INT_CONFIG10,INT_CONFIG10" "0,1,2,3" bitfld.long 0x34 18.--19. "INT_CONFIG9,INT_CONFIG9" "0,1,2,3" bitfld.long 0x34 16.--17. "INT_CONFIG8,INT_CONFIG8" "0,1,2,3" bitfld.long 0x34 14.--15. "INT_CONFIG7,INT_CONFIG7" "0,1,2,3" bitfld.long 0x34 12.--13. "INT_CONFIG6,INT_CONFIG6" "0,1,2,3" newline bitfld.long 0x34 10.--11. "INT_CONFIG5,INT_CONFIG5" "0,1,2,3" bitfld.long 0x34 8.--9. "INT_CONFIG4,INT_CONFIG4" "0,1,2,3" bitfld.long 0x34 6.--7. "INT_CONFIG3,INT_CONFIG3" "0,1,2,3" bitfld.long 0x34 4.--5. "INT_CONFIG2,INT_CONFIG2" "0,1,2,3" bitfld.long 0x34 2.--3. "INT_CONFIG1,INT_CONFIG1" "0,1,2,3" newline bitfld.long 0x34 0.--1. "INT_CONFIG0,INT_CONFIG0" "0,1,2,3" line.long 0x38 "GICD_ICFGR14,GICD interrupt configuration register 14" bitfld.long 0x38 30.--31. "INT_CONFIG15,INT_CONFIG15" "0,1,2,3" bitfld.long 0x38 28.--29. "INT_CONFIG14,INT_CONFIG14" "0,1,2,3" bitfld.long 0x38 26.--27. "INT_CONFIG13,INT_CONFIG13" "0,1,2,3" bitfld.long 0x38 24.--25. "INT_CONFIG12,INT_CONFIG12" "0,1,2,3" bitfld.long 0x38 22.--23. "INT_CONFIG11,INT_CONFIG11" "0,1,2,3" newline bitfld.long 0x38 20.--21. "INT_CONFIG10,INT_CONFIG10" "0,1,2,3" bitfld.long 0x38 18.--19. "INT_CONFIG9,INT_CONFIG9" "0,1,2,3" bitfld.long 0x38 16.--17. "INT_CONFIG8,INT_CONFIG8" "0,1,2,3" bitfld.long 0x38 14.--15. "INT_CONFIG7,INT_CONFIG7" "0,1,2,3" bitfld.long 0x38 12.--13. "INT_CONFIG6,INT_CONFIG6" "0,1,2,3" newline bitfld.long 0x38 10.--11. "INT_CONFIG5,INT_CONFIG5" "0,1,2,3" bitfld.long 0x38 8.--9. "INT_CONFIG4,INT_CONFIG4" "0,1,2,3" bitfld.long 0x38 6.--7. "INT_CONFIG3,INT_CONFIG3" "0,1,2,3" bitfld.long 0x38 4.--5. "INT_CONFIG2,INT_CONFIG2" "0,1,2,3" bitfld.long 0x38 2.--3. "INT_CONFIG1,INT_CONFIG1" "0,1,2,3" newline bitfld.long 0x38 0.--1. "INT_CONFIG0,INT_CONFIG0" "0,1,2,3" line.long 0x3C "GICD_ICFGR15,GICD interrupt configuration register 15" bitfld.long 0x3C 30.--31. "INT_CONFIG15,INT_CONFIG15" "0,1,2,3" bitfld.long 0x3C 28.--29. "INT_CONFIG14,INT_CONFIG14" "0,1,2,3" bitfld.long 0x3C 26.--27. "INT_CONFIG13,INT_CONFIG13" "0,1,2,3" bitfld.long 0x3C 24.--25. "INT_CONFIG12,INT_CONFIG12" "0,1,2,3" bitfld.long 0x3C 22.--23. "INT_CONFIG11,INT_CONFIG11" "0,1,2,3" newline bitfld.long 0x3C 20.--21. "INT_CONFIG10,INT_CONFIG10" "0,1,2,3" bitfld.long 0x3C 18.--19. "INT_CONFIG9,INT_CONFIG9" "0,1,2,3" bitfld.long 0x3C 16.--17. "INT_CONFIG8,INT_CONFIG8" "0,1,2,3" bitfld.long 0x3C 14.--15. "INT_CONFIG7,INT_CONFIG7" "0,1,2,3" bitfld.long 0x3C 12.--13. "INT_CONFIG6,INT_CONFIG6" "0,1,2,3" newline bitfld.long 0x3C 10.--11. "INT_CONFIG5,INT_CONFIG5" "0,1,2,3" bitfld.long 0x3C 8.--9. "INT_CONFIG4,INT_CONFIG4" "0,1,2,3" bitfld.long 0x3C 6.--7. "INT_CONFIG3,INT_CONFIG3" "0,1,2,3" bitfld.long 0x3C 4.--5. "INT_CONFIG2,INT_CONFIG2" "0,1,2,3" bitfld.long 0x3C 2.--3. "INT_CONFIG1,INT_CONFIG1" "0,1,2,3" newline bitfld.long 0x3C 0.--1. "INT_CONFIG0,INT_CONFIG0" "0,1,2,3" line.long 0x40 "GICD_ICFGR16,GICD interrupt configuration register 16" bitfld.long 0x40 30.--31. "INT_CONFIG15,INT_CONFIG15" "0,1,2,3" bitfld.long 0x40 28.--29. "INT_CONFIG14,INT_CONFIG14" "0,1,2,3" bitfld.long 0x40 26.--27. "INT_CONFIG13,INT_CONFIG13" "0,1,2,3" bitfld.long 0x40 24.--25. "INT_CONFIG12,INT_CONFIG12" "0,1,2,3" bitfld.long 0x40 22.--23. "INT_CONFIG11,INT_CONFIG11" "0,1,2,3" newline bitfld.long 0x40 20.--21. "INT_CONFIG10,INT_CONFIG10" "0,1,2,3" bitfld.long 0x40 18.--19. "INT_CONFIG9,INT_CONFIG9" "0,1,2,3" bitfld.long 0x40 16.--17. "INT_CONFIG8,INT_CONFIG8" "0,1,2,3" bitfld.long 0x40 14.--15. "INT_CONFIG7,INT_CONFIG7" "0,1,2,3" bitfld.long 0x40 12.--13. "INT_CONFIG6,INT_CONFIG6" "0,1,2,3" newline bitfld.long 0x40 10.--11. "INT_CONFIG5,INT_CONFIG5" "0,1,2,3" bitfld.long 0x40 8.--9. "INT_CONFIG4,INT_CONFIG4" "0,1,2,3" bitfld.long 0x40 6.--7. "INT_CONFIG3,INT_CONFIG3" "0,1,2,3" bitfld.long 0x40 4.--5. "INT_CONFIG2,INT_CONFIG2" "0,1,2,3" bitfld.long 0x40 2.--3. "INT_CONFIG1,INT_CONFIG1" "0,1,2,3" newline bitfld.long 0x40 0.--1. "INT_CONFIG0,INT_CONFIG0" "0,1,2,3" line.long 0x44 "GICD_ICFGR17,GICD interrupt configuration register 17" bitfld.long 0x44 30.--31. "INT_CONFIG15,INT_CONFIG15" "0,1,2,3" bitfld.long 0x44 28.--29. "INT_CONFIG14,INT_CONFIG14" "0,1,2,3" bitfld.long 0x44 26.--27. "INT_CONFIG13,INT_CONFIG13" "0,1,2,3" bitfld.long 0x44 24.--25. "INT_CONFIG12,INT_CONFIG12" "0,1,2,3" bitfld.long 0x44 22.--23. "INT_CONFIG11,INT_CONFIG11" "0,1,2,3" newline bitfld.long 0x44 20.--21. "INT_CONFIG10,INT_CONFIG10" "0,1,2,3" bitfld.long 0x44 18.--19. "INT_CONFIG9,INT_CONFIG9" "0,1,2,3" bitfld.long 0x44 16.--17. "INT_CONFIG8,INT_CONFIG8" "0,1,2,3" bitfld.long 0x44 14.--15. "INT_CONFIG7,INT_CONFIG7" "0,1,2,3" bitfld.long 0x44 12.--13. "INT_CONFIG6,INT_CONFIG6" "0,1,2,3" newline bitfld.long 0x44 10.--11. "INT_CONFIG5,INT_CONFIG5" "0,1,2,3" bitfld.long 0x44 8.--9. "INT_CONFIG4,INT_CONFIG4" "0,1,2,3" bitfld.long 0x44 6.--7. "INT_CONFIG3,INT_CONFIG3" "0,1,2,3" bitfld.long 0x44 4.--5. "INT_CONFIG2,INT_CONFIG2" "0,1,2,3" bitfld.long 0x44 2.--3. "INT_CONFIG1,INT_CONFIG1" "0,1,2,3" newline bitfld.long 0x44 0.--1. "INT_CONFIG0,INT_CONFIG0" "0,1,2,3" rgroup.long 0xD00++0x3 line.long 0x0 "GICD_PPISR,GICD private peripheral interrupt status register" bitfld.long 0x0 15. "PPI3,PPI3" "0,1" bitfld.long 0x0 14. "PPI2,PPI2" "0,1" bitfld.long 0x0 13. "PPI1,PPI1" "0,1" bitfld.long 0x0 12. "PPI0,PPI0" "0,1" bitfld.long 0x0 11. "PPI4,PPI4" "0,1" newline bitfld.long 0x0 10. "PPI5,PPI5" "0,1" bitfld.long 0x0 9. "PPI6,PPI6" "0,1" rgroup.long 0xD08++0x1B line.long 0x0 "GICD_SPISR1,For interrupts ID = SPI number+32. from SPI [x*32+31] to SPI [x*32]" hexmask.long 0x0 0.--31. 1. "SPISR1,SPISR1" line.long 0x4 "GICD_SPISR2,For interrupts ID" hexmask.long 0x4 0.--31. 1. "SPISR2,SPISR2" line.long 0x8 "GICD_SPISR3,For interrupts ID" hexmask.long 0x8 0.--31. 1. "SPISR3,SPISR3" line.long 0xC "GICD_SPISR4,For interrupts ID" hexmask.long 0xC 0.--31. 1. "SPISR4,SPISR4" line.long 0x10 "GICD_SPISR5,For interrupts ID" hexmask.long 0x10 0.--31. 1. "SPISR5,SPISR5" line.long 0x14 "GICD_SPISR6,For interrupts ID" hexmask.long 0x14 0.--31. 1. "SPISR6,SPISR6" line.long 0x18 "GICD_SPISR7,For interrupts ID" hexmask.long 0x18 0.--31. 1. "SPISR7,SPISR7" wgroup.long 0xF00++0x3 line.long 0x0 "GICD_SGIR,GICD software generated interrupt register" bitfld.long 0x0 24.--25. "TARGETLISTFILTER,TARGETLISTFILTER" "0,1,2,3" bitfld.long 0x0 16.--17. "CPUTARGETLIST,CPUTARGETLIST" "0,1,2,3" bitfld.long 0x0 15. "NSATT,NSATT" "0,1" hexmask.long.byte 0x0 0.--3. 1. "SGIINTID,SGIINTID" group.long 0xF10++0x1F line.long 0x0 "GICD_CPENDSGIR0,For SGI x*4 to SGI x*4+3" bitfld.long 0x0 24.--25. "SGI_CLEAR_PENDING3,SGI_CLEAR_PENDING3" "0,1,2,3" bitfld.long 0x0 16.--17. "SGI_CLEAR_PENDING2,SGI_CLEAR_PENDING2" "0,1,2,3" bitfld.long 0x0 8.--9. "SGI_CLEAR_PENDING1,SGI_CLEAR_PENDING1" "0,1,2,3" bitfld.long 0x0 0.--1. "SGI_CLEAR_PENDING0,SGI_CLEAR_PENDING0" "0,1,2,3" line.long 0x4 "GICD_CPENDSGIR1,For SGI x*4 to SGI x*4+3" bitfld.long 0x4 24.--25. "SGI_CLEAR_PENDING3,SGI_CLEAR_PENDING3" "0,1,2,3" bitfld.long 0x4 16.--17. "SGI_CLEAR_PENDING2,SGI_CLEAR_PENDING2" "0,1,2,3" bitfld.long 0x4 8.--9. "SGI_CLEAR_PENDING1,SGI_CLEAR_PENDING1" "0,1,2,3" bitfld.long 0x4 0.--1. "SGI_CLEAR_PENDING0,SGI_CLEAR_PENDING0" "0,1,2,3" line.long 0x8 "GICD_CPENDSGIR2,For SGI x*4 to SGI x*4+3" bitfld.long 0x8 24.--25. "SGI_CLEAR_PENDING3,SGI_CLEAR_PENDING3" "0,1,2,3" bitfld.long 0x8 16.--17. "SGI_CLEAR_PENDING2,SGI_CLEAR_PENDING2" "0,1,2,3" bitfld.long 0x8 8.--9. "SGI_CLEAR_PENDING1,SGI_CLEAR_PENDING1" "0,1,2,3" bitfld.long 0x8 0.--1. "SGI_CLEAR_PENDING0,SGI_CLEAR_PENDING0" "0,1,2,3" line.long 0xC "GICD_CPENDSGIR3,For SGI x*4 to SGI x*4+3" bitfld.long 0xC 24.--25. "SGI_CLEAR_PENDING3,SGI_CLEAR_PENDING3" "0,1,2,3" bitfld.long 0xC 16.--17. "SGI_CLEAR_PENDING2,SGI_CLEAR_PENDING2" "0,1,2,3" bitfld.long 0xC 8.--9. "SGI_CLEAR_PENDING1,SGI_CLEAR_PENDING1" "0,1,2,3" bitfld.long 0xC 0.--1. "SGI_CLEAR_PENDING0,SGI_CLEAR_PENDING0" "0,1,2,3" line.long 0x10 "GICD_SPENDSGIR0,For SGI x*4 to SGI x*4+3" bitfld.long 0x10 24.--25. "SGI_SET_PENDING3,SGI_SET_PENDING3" "0,1,2,3" bitfld.long 0x10 16.--17. "SGI_SET_PENDING2,SGI_SET_PENDING2" "0,1,2,3" bitfld.long 0x10 8.--9. "SGI_SET_PENDING1,SGI_SET_PENDING1" "0,1,2,3" bitfld.long 0x10 0.--1. "SGI_SET_PENDING0,SGI_SET_PENDING0" "0,1,2,3" line.long 0x14 "GICD_SPENDSGIR1,For SGI x*4 to SGI x*4+3" bitfld.long 0x14 24.--25. "SGI_SET_PENDING3,SGI_SET_PENDING3" "0,1,2,3" bitfld.long 0x14 16.--17. "SGI_SET_PENDING2,SGI_SET_PENDING2" "0,1,2,3" bitfld.long 0x14 8.--9. "SGI_SET_PENDING1,SGI_SET_PENDING1" "0,1,2,3" bitfld.long 0x14 0.--1. "SGI_SET_PENDING0,SGI_SET_PENDING0" "0,1,2,3" line.long 0x18 "GICD_SPENDSGIR2,For SGI x*4 to SGI x*4+3" bitfld.long 0x18 24.--25. "SGI_SET_PENDING3,SGI_SET_PENDING3" "0,1,2,3" bitfld.long 0x18 16.--17. "SGI_SET_PENDING2,SGI_SET_PENDING2" "0,1,2,3" bitfld.long 0x18 8.--9. "SGI_SET_PENDING1,SGI_SET_PENDING1" "0,1,2,3" bitfld.long 0x18 0.--1. "SGI_SET_PENDING0,SGI_SET_PENDING0" "0,1,2,3" line.long 0x1C "GICD_SPENDSGIR3,For SGI x*4 to SGI x*4+3" bitfld.long 0x1C 24.--25. "SGI_SET_PENDING3,SGI_SET_PENDING3" "0,1,2,3" bitfld.long 0x1C 16.--17. "SGI_SET_PENDING2,SGI_SET_PENDING2" "0,1,2,3" bitfld.long 0x1C 8.--9. "SGI_SET_PENDING1,SGI_SET_PENDING1" "0,1,2,3" bitfld.long 0x1C 0.--1. "SGI_SET_PENDING0,SGI_SET_PENDING0" "0,1,2,3" rgroup.long 0xFD0++0x2F line.long 0x0 "GICD_PIDR4,GICD peripheral ID4 register" hexmask.long 0x0 0.--31. 1. "PIDR4,PIDR4" line.long 0x4 "GICD_PIDR5,GICD peripheral ID5 to ID7 register 5" hexmask.long 0x4 0.--31. 1. "PIDR5,PIDR5" line.long 0x8 "GICD_PIDR6,GICD peripheral ID5 to ID7 register 6" hexmask.long 0x8 0.--31. 1. "PIDR6,PIDR6" line.long 0xC "GICD_PIDR7,GICD peripheral ID5 to ID7 register 7" hexmask.long 0xC 0.--31. 1. "PIDR7,PIDR7" line.long 0x10 "GICD_PIDR0,GICD peripheral ID0 register" hexmask.long 0x10 0.--31. 1. "PIDR0,PIDR0" line.long 0x14 "GICD_PIDR1,GICD peripheral ID1 register" hexmask.long 0x14 0.--31. 1. "PIDR1,PIDR1" line.long 0x18 "GICD_PIDR2,GICD peripheral ID2 register" hexmask.long 0x18 0.--31. 1. "PIDR2,PIDR2" line.long 0x1C "GICD_PIDR3,GICD peripheral ID3 register" hexmask.long 0x1C 0.--31. 1. "PIDR3,PIDR3" line.long 0x20 "GICD_CIDR0,GICD component ID0 register" hexmask.long 0x20 0.--31. 1. "CIDR0,CIDR0" line.long 0x24 "GICD_CIDR1,GICD component ID1 register" hexmask.long 0x24 0.--31. 1. "CIDR1,CIDR1" line.long 0x28 "GICD_CIDR2,GICD component ID2 register" hexmask.long 0x28 0.--31. 1. "CIDR2,CIDR2" line.long 0x2C "GICD_CIDR3,GICD component ID3 register" hexmask.long 0x2C 0.--31. 1. "CIDR3,CIDR3" tree.end endif sif (cpuis("STM32MP151*")||cpuis("STM32MP153*")||cpuis("STM32MP157*")) tree "GICH" base ad:0xA0024000 group.long 0x0++0x3 line.long 0x0 "GICH_HCR,GICH hypervisor control register" hexmask.long.byte 0x0 27.--31. 1. "EOICOUNT,EOICOUNT" bitfld.long 0x0 7. "VGRP1DIE,VGRP1DIE" "0,1" bitfld.long 0x0 6. "VGRP1EIE,VGRP1EIE" "0,1" bitfld.long 0x0 5. "VGRP0DIE,VGRP0DIE" "0,1" bitfld.long 0x0 4. "VGRP0EIE,VGRP0EIE" "0,1" bitfld.long 0x0 3. "NPIE,NPIE" "0,1" bitfld.long 0x0 2. "LRENPIE,LRENPIE" "0,1" bitfld.long 0x0 1. "UIE,UIE" "0,1" newline bitfld.long 0x0 0. "EN,EN" "0,1" rgroup.long 0x4++0x3 line.long 0x0 "GICH_VTR,GICH VGIC type register" bitfld.long 0x0 29.--31. "PRIBITS,PRIBITS" "0,1,2,3,4,5,6,7" bitfld.long 0x0 26.--28. "PREBITS,PREBITS" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 0.--4. 1. "LISTREGS,LISTREGS" group.long 0x8++0x3 line.long 0x0 "GICH_VMCR,GICH virtual machine control register" hexmask.long.byte 0x0 27.--31. 1. "VMPRIMASK,VMPRIMASK" bitfld.long 0x0 21.--23. "VMBP,VMBP" "0,1,2,3,4,5,6,7" bitfld.long 0x0 18.--20. "VMABP,VMABP" "0,1,2,3,4,5,6,7" bitfld.long 0x0 9. "VEM,VEM" "0,1" bitfld.long 0x0 4. "VMCBPR,VMCBPR" "0,1" bitfld.long 0x0 3. "VMFIQEN,VMFIQEN" "0,1" bitfld.long 0x0 2. "VMACKCTL,VMACKCTL" "0,1" bitfld.long 0x0 1. "VMGRP1EN,VMGRP1EN" "0,1" newline bitfld.long 0x0 0. "VMGRP0EN,VMGRP0EN" "0,1" rgroup.long 0x10++0x3 line.long 0x0 "GICH_MISR,GICH maintenance interrupt status register" bitfld.long 0x0 7. "VGRP1D,VGRP1D" "0,1" bitfld.long 0x0 6. "VGRP1E,VGRP1E" "0,1" bitfld.long 0x0 5. "VGRP0D,VGRP0D" "0,1" bitfld.long 0x0 4. "VGRP0E,VGRP0E" "0,1" bitfld.long 0x0 3. "NP,NP" "0,1" bitfld.long 0x0 2. "LRENP,LRENP" "0,1" bitfld.long 0x0 1. "U,U" "0,1" bitfld.long 0x0 0. "EOI,EOI" "0,1" rgroup.long 0x20++0x3 line.long 0x0 "GICH_EISR0,GICH end of interrupt status register" hexmask.long 0x0 0.--31. 1. "EISR0,EISR0" rgroup.long 0x30++0x3 line.long 0x0 "GICH_ELSR0,GICH empty list status register" hexmask.long 0x0 0.--31. 1. "ELSR0,ELSR0" group.long 0xF0++0x3 line.long 0x0 "GICH_APR0,GICH active priority register" hexmask.long 0x0 0.--31. 1. "APR0,APR0" group.long 0x100++0xF line.long 0x0 "GICH_LR0,GICH list register 0" bitfld.long 0x0 31. "HW,HW" "0,1" bitfld.long 0x0 30. "GRP1,GRP1" "0,1" bitfld.long 0x0 28.--29. "STATE,STATE" "0,1,2,3" hexmask.long.byte 0x0 23.--27. 1. "PRIORITY,PRIORITY" hexmask.long.word 0x0 10.--19. 1. "PHYSICALID,PHYSICALID" hexmask.long.word 0x0 0.--9. 1. "VIRTUALID,VIRTUALID" line.long 0x4 "GICH_LR1,GICH list register 1" bitfld.long 0x4 31. "HW,HW" "0,1" bitfld.long 0x4 30. "GRP1,GRP1" "0,1" bitfld.long 0x4 28.--29. "STATE,STATE" "0,1,2,3" hexmask.long.byte 0x4 23.--27. 1. "PRIORITY,PRIORITY" hexmask.long.word 0x4 10.--19. 1. "PHYSICALID,PHYSICALID" hexmask.long.word 0x4 0.--9. 1. "VIRTUALID,VIRTUALID" line.long 0x8 "GICH_LR2,GICH list register 2" bitfld.long 0x8 31. "HW,HW" "0,1" bitfld.long 0x8 30. "GRP1,GRP1" "0,1" bitfld.long 0x8 28.--29. "STATE,STATE" "0,1,2,3" hexmask.long.byte 0x8 23.--27. 1. "PRIORITY,PRIORITY" hexmask.long.word 0x8 10.--19. 1. "PHYSICALID,PHYSICALID" hexmask.long.word 0x8 0.--9. 1. "VIRTUALID,VIRTUALID" line.long 0xC "GICH_LR3,GICH list register 3" bitfld.long 0xC 31. "HW,HW" "0,1" bitfld.long 0xC 30. "GRP1,GRP1" "0,1" bitfld.long 0xC 28.--29. "STATE,STATE" "0,1,2,3" hexmask.long.byte 0xC 23.--27. 1. "PRIORITY,PRIORITY" hexmask.long.word 0xC 10.--19. 1. "PHYSICALID,PHYSICALID" hexmask.long.word 0xC 0.--9. 1. "VIRTUALID,VIRTUALID" tree.end endif sif (cpuis("STM32MP151*")||cpuis("STM32MP153*")||cpuis("STM32MP157*")) tree "GICV" base ad:0xA0026000 group.long 0x0++0xB line.long 0x0 "GICV_CTLR,GICV virtual machine control register" bitfld.long 0x0 9. "EOIMODE,EOIMODE" "0,1" bitfld.long 0x0 4. "CBPR,CBPR" "0,1" bitfld.long 0x0 3. "FIQEN,FIQEN" "0,1" bitfld.long 0x0 2. "ACKCTL,ACKCTL" "0,1" bitfld.long 0x0 1. "ENABLEGRP1,ENABLEGRP1" "0,1" bitfld.long 0x0 0. "ENABLEGRP0,ENABLEGRP0" "0,1" line.long 0x4 "GICV_PMR,GICV VM priority mask register" hexmask.long.byte 0x4 3.--7. 1. "PRIORITY,PRIORITY" line.long 0x8 "GICV_BPR,GICV VM binary point register" bitfld.long 0x8 0.--2. "BINARY_POINT,BINARY_POINT" "0,1,2,3,4,5,6,7" rgroup.long 0xC++0x3 line.long 0x0 "GICV_IAR,GICV VM interrupt acknowledge register" bitfld.long 0x0 10. "CPUID,CPUID" "0,1" hexmask.long.word 0x0 0.--9. 1. "INTERRUPT_ID,INTERRUPT_ID" wgroup.long 0x10++0x3 line.long 0x0 "GICV_EOIR,GICV VM end of interrupt register" bitfld.long 0x0 10. "CPUID,CPUID" "0,1" hexmask.long.word 0x0 0.--9. 1. "EOIINTID,EOIINTID" rgroup.long 0x14++0x7 line.long 0x0 "GICV_RPR,GICV VM running priority register" hexmask.long.byte 0x0 3.--7. 1. "PRIORITY,PRIORITY" line.long 0x4 "GICV_HPPIR,GICV VM highest priority pending interrupt register" bitfld.long 0x4 10. "CPUID,CPUID" "0,1" hexmask.long.word 0x4 0.--9. 1. "PENDINTID,PENDINTID" group.long 0x1C++0x3 line.long 0x0 "GICV_ABPR,GICV VM aliased binary point register" bitfld.long 0x0 0.--2. "BINARY_POINT,BINARY_POINT" "0,1,2,3,4,5,6,7" rgroup.long 0x20++0x3 line.long 0x0 "GICV_AIAR,GICV VM aliased interrupt register" bitfld.long 0x0 10. "CPUID,CPUID" "0,1" hexmask.long.word 0x0 0.--9. 1. "INTERRUPT_ID,INTERRUPT_ID" wgroup.long 0x24++0x3 line.long 0x0 "GICV_AEOIR,GICV VM aliased end of interrupt register" bitfld.long 0x0 10. "CPUID,CPUID" "0,1" hexmask.long.word 0x0 0.--9. 1. "EOIINTID,EOIINTID" rgroup.long 0x28++0x3 line.long 0x0 "GICV_AHPPIR,GICV VM aliased highest priority pending interrupt register" bitfld.long 0x0 10. "CPUID,CPUID" "0,1" hexmask.long.word 0x0 0.--9. 1. "PENDINTID,PENDINTID" group.long 0xD0++0x3 line.long 0x0 "GICV_APR0,The GICV_APR0 is an alias of GICH_APR." hexmask.long 0x0 0.--31. 1. "APR0,APR0" rgroup.long 0xFC++0x3 line.long 0x0 "GICV_IIDR,The GICV_IIDR is an alias of GICC_IIDR." hexmask.long 0x0 0.--31. 1. "IIDR,IIDR" wgroup.long 0x1000++0x3 line.long 0x0 "GICV_DIR,GICV VM deactivate interrupt register" bitfld.long 0x0 10. "CPUID,CPUID" "0,1" hexmask.long.word 0x0 0.--9. 1. "INTERRUPT_ID,INTERRUPT_ID" tree.end endif tree.end tree "GPIO (General Purpose I/Os)" base ad:0x0 sif (cpuis("STM32MP13*")) tree "GPIOA" base ad:0x50002000 group.long 0x0++0xF line.long 0x0 "GPIOA_MODER,GPIO port mode register" bitfld.long 0x0 30.--31. "MODER15,MODER15" "0,1,2,3" bitfld.long 0x0 28.--29. "MODER14,MODER14" "0,1,2,3" bitfld.long 0x0 26.--27. "MODER13,MODER13" "0,1,2,3" bitfld.long 0x0 24.--25. "MODER12,MODER12" "0,1,2,3" bitfld.long 0x0 22.--23. "MODER11,MODER11" "0,1,2,3" bitfld.long 0x0 20.--21. "MODER10,MODER10" "0,1,2,3" bitfld.long 0x0 18.--19. "MODER9,MODER9" "0,1,2,3" newline bitfld.long 0x0 16.--17. "MODER8,MODER8" "0,1,2,3" bitfld.long 0x0 14.--15. "MODER7,MODER7" "0,1,2,3" bitfld.long 0x0 12.--13. "MODER6,MODER6" "0,1,2,3" bitfld.long 0x0 10.--11. "MODER5,MODER5" "0,1,2,3" bitfld.long 0x0 8.--9. "MODER4,MODER4" "0,1,2,3" bitfld.long 0x0 6.--7. "MODER3,MODER3" "0,1,2,3" bitfld.long 0x0 4.--5. "MODER2,MODER2" "0,1,2,3" newline bitfld.long 0x0 2.--3. "MODER1,MODER1" "0,1,2,3" bitfld.long 0x0 0.--1. "MODER0,MODER0" "0,1,2,3" line.long 0x4 "GPIOA_OTYPER,GPIO port output type register" bitfld.long 0x4 15. "OT15,OT15" "0,1" bitfld.long 0x4 14. "OT14,OT14" "0,1" bitfld.long 0x4 13. "OT13,OT13" "0,1" bitfld.long 0x4 12. "OT12,OT12" "0,1" bitfld.long 0x4 11. "OT11,OT11" "0,1" bitfld.long 0x4 10. "OT10,OT10" "0,1" bitfld.long 0x4 9. "OT9,OT9" "0,1" newline bitfld.long 0x4 8. "OT8,OT8" "0,1" bitfld.long 0x4 7. "OT7,OT7" "0,1" bitfld.long 0x4 6. "OT6,OT6" "0,1" bitfld.long 0x4 5. "OT5,OT5" "0,1" bitfld.long 0x4 4. "OT4,OT4" "0,1" bitfld.long 0x4 3. "OT3,OT3" "0,1" bitfld.long 0x4 2. "OT2,OT2" "0,1" newline bitfld.long 0x4 1. "OT1,OT1" "0,1" bitfld.long 0x4 0. "OT0,OT0" "0,1" line.long 0x8 "GPIOA_OSPEEDR,GPIO port output speed register" bitfld.long 0x8 30.--31. "OSPEEDR15,OSPEEDR15" "0,1,2,3" bitfld.long 0x8 28.--29. "OSPEEDR14,OSPEEDR14" "0,1,2,3" bitfld.long 0x8 26.--27. "OSPEEDR13,OSPEEDR13" "0,1,2,3" bitfld.long 0x8 24.--25. "OSPEEDR12,OSPEEDR12" "0,1,2,3" bitfld.long 0x8 22.--23. "OSPEEDR11,OSPEEDR11" "0,1,2,3" bitfld.long 0x8 20.--21. "OSPEEDR10,OSPEEDR10" "0,1,2,3" bitfld.long 0x8 18.--19. "OSPEEDR9,OSPEEDR9" "0,1,2,3" newline bitfld.long 0x8 16.--17. "OSPEEDR8,OSPEEDR8" "0,1,2,3" bitfld.long 0x8 14.--15. "OSPEEDR7,OSPEEDR7" "0,1,2,3" bitfld.long 0x8 12.--13. "OSPEEDR6,OSPEEDR6" "0,1,2,3" bitfld.long 0x8 10.--11. "OSPEEDR5,OSPEEDR5" "0,1,2,3" bitfld.long 0x8 8.--9. "OSPEEDR4,OSPEEDR4" "0,1,2,3" bitfld.long 0x8 6.--7. "OSPEEDR3,OSPEEDR3" "0,1,2,3" bitfld.long 0x8 4.--5. "OSPEEDR2,OSPEEDR2" "0,1,2,3" newline bitfld.long 0x8 2.--3. "OSPEEDR1,OSPEEDR1" "0,1,2,3" bitfld.long 0x8 0.--1. "OSPEEDR0,OSPEEDR0" "0,1,2,3" line.long 0xC "GPIOA_PUPDR,GPIO port pull-up/pull-down register" bitfld.long 0xC 30.--31. "PUPDR15,PUPDR15" "0,1,2,3" bitfld.long 0xC 28.--29. "PUPDR14,PUPDR14" "0,1,2,3" bitfld.long 0xC 26.--27. "PUPDR13,PUPDR13" "0,1,2,3" bitfld.long 0xC 24.--25. "PUPDR12,PUPDR12" "0,1,2,3" bitfld.long 0xC 22.--23. "PUPDR11,PUPDR11" "0,1,2,3" bitfld.long 0xC 20.--21. "PUPDR10,PUPDR10" "0,1,2,3" bitfld.long 0xC 18.--19. "PUPDR9,PUPDR9" "0,1,2,3" newline bitfld.long 0xC 16.--17. "PUPDR8,PUPDR8" "0,1,2,3" bitfld.long 0xC 14.--15. "PUPDR7,PUPDR7" "0,1,2,3" bitfld.long 0xC 12.--13. "PUPDR6,PUPDR6" "0,1,2,3" bitfld.long 0xC 10.--11. "PUPDR5,PUPDR5" "0,1,2,3" bitfld.long 0xC 8.--9. "PUPDR4,PUPDR4" "0,1,2,3" bitfld.long 0xC 6.--7. "PUPDR3,PUPDR3" "0,1,2,3" bitfld.long 0xC 4.--5. "PUPDR2,PUPDR2" "0,1,2,3" newline bitfld.long 0xC 2.--3. "PUPDR1,PUPDR1" "0,1,2,3" bitfld.long 0xC 0.--1. "PUPDR0,PUPDR0" "0,1,2,3" rgroup.long 0x10++0x3 line.long 0x0 "GPIOA_IDR,GPIO port input data register" bitfld.long 0x0 15. "IDR15,IDR15" "0,1" bitfld.long 0x0 14. "IDR14,IDR14" "0,1" bitfld.long 0x0 13. "IDR13,IDR13" "0,1" bitfld.long 0x0 12. "IDR12,IDR12" "0,1" bitfld.long 0x0 11. "IDR11,IDR11" "0,1" bitfld.long 0x0 10. "IDR10,IDR10" "0,1" bitfld.long 0x0 9. "IDR9,IDR9" "0,1" newline bitfld.long 0x0 8. "IDR8,IDR8" "0,1" bitfld.long 0x0 7. "IDR7,IDR7" "0,1" bitfld.long 0x0 6. "IDR6,IDR6" "0,1" bitfld.long 0x0 5. "IDR5,IDR5" "0,1" bitfld.long 0x0 4. "IDR4,IDR4" "0,1" bitfld.long 0x0 3. "IDR3,IDR3" "0,1" bitfld.long 0x0 2. "IDR2,IDR2" "0,1" newline bitfld.long 0x0 1. "IDR1,IDR1" "0,1" bitfld.long 0x0 0. "IDR0,IDR0" "0,1" group.long 0x14++0x3 line.long 0x0 "GPIOA_ODR,GPIO port output data register" bitfld.long 0x0 15. "ODR15,ODR15" "0,1" bitfld.long 0x0 14. "ODR14,ODR14" "0,1" bitfld.long 0x0 13. "ODR13,ODR13" "0,1" bitfld.long 0x0 12. "ODR12,ODR12" "0,1" bitfld.long 0x0 11. "ODR11,ODR11" "0,1" bitfld.long 0x0 10. "ODR10,ODR10" "0,1" bitfld.long 0x0 9. "ODR9,ODR9" "0,1" newline bitfld.long 0x0 8. "ODR8,ODR8" "0,1" bitfld.long 0x0 7. "ODR7,ODR7" "0,1" bitfld.long 0x0 6. "ODR6,ODR6" "0,1" bitfld.long 0x0 5. "ODR5,ODR5" "0,1" bitfld.long 0x0 4. "ODR4,ODR4" "0,1" bitfld.long 0x0 3. "ODR3,ODR3" "0,1" bitfld.long 0x0 2. "ODR2,ODR2" "0,1" newline bitfld.long 0x0 1. "ODR1,ODR1" "0,1" bitfld.long 0x0 0. "ODR0,ODR0" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "GPIOA_BSRR,GPIO port bit set/reset register" bitfld.long 0x0 31. "BR15,BR15" "0,1" bitfld.long 0x0 30. "BR14,BR14" "0,1" bitfld.long 0x0 29. "BR13,BR13" "0,1" bitfld.long 0x0 28. "BR12,BR12" "0,1" bitfld.long 0x0 27. "BR11,BR11" "0,1" bitfld.long 0x0 26. "BR10,BR10" "0,1" bitfld.long 0x0 25. "BR9,BR9" "0,1" newline bitfld.long 0x0 24. "BR8,BR8" "0,1" bitfld.long 0x0 23. "BR7,BR7" "0,1" bitfld.long 0x0 22. "BR6,BR6" "0,1" bitfld.long 0x0 21. "BR5,BR5" "0,1" bitfld.long 0x0 20. "BR4,BR4" "0,1" bitfld.long 0x0 19. "BR3,BR3" "0,1" bitfld.long 0x0 18. "BR2,BR2" "0,1" newline bitfld.long 0x0 17. "BR1,BR1" "0,1" bitfld.long 0x0 16. "BR0,BR0" "0,1" bitfld.long 0x0 15. "BS15,BS15" "0,1" bitfld.long 0x0 14. "BS14,BS14" "0,1" bitfld.long 0x0 13. "BS13,BS13" "0,1" bitfld.long 0x0 12. "BS12,BS12" "0,1" bitfld.long 0x0 11. "BS11,BS11" "0,1" newline bitfld.long 0x0 10. "BS10,BS10" "0,1" bitfld.long 0x0 9. "BS9,BS9" "0,1" bitfld.long 0x0 8. "BS8,BS8" "0,1" bitfld.long 0x0 7. "BS7,BS7" "0,1" bitfld.long 0x0 6. "BS6,BS6" "0,1" bitfld.long 0x0 5. "BS5,BS5" "0,1" bitfld.long 0x0 4. "BS4,BS4" "0,1" newline bitfld.long 0x0 3. "BS3,BS3" "0,1" bitfld.long 0x0 2. "BS2,BS2" "0,1" bitfld.long 0x0 1. "BS1,BS1" "0,1" bitfld.long 0x0 0. "BS0,BS0" "0,1" group.long 0x1C++0xB line.long 0x0 "GPIOA_LCKR,This register is used to lock the configuration of the port bits when a correct write sequence is applied to bit 16 (LCKK). The value of bits [15:0] is used to lock the configuration of the GPIO. During the write sequence. the value of.." bitfld.long 0x0 16. "LCKK,LCKK" "0,1" bitfld.long 0x0 15. "LCK15,LCK15" "0,1" bitfld.long 0x0 14. "LCK14,LCK14" "0,1" bitfld.long 0x0 13. "LCK13,LCK13" "0,1" bitfld.long 0x0 12. "LCK12,LCK12" "0,1" bitfld.long 0x0 11. "LCK11,LCK11" "0,1" bitfld.long 0x0 10. "LCK10,LCK10" "0,1" newline bitfld.long 0x0 9. "LCK9,LCK9" "0,1" bitfld.long 0x0 8. "LCK8,LCK8" "0,1" bitfld.long 0x0 7. "LCK7,LCK7" "0,1" bitfld.long 0x0 6. "LCK6,LCK6" "0,1" bitfld.long 0x0 5. "LCK5,LCK5" "0,1" bitfld.long 0x0 4. "LCK4,LCK4" "0,1" bitfld.long 0x0 3. "LCK3,LCK3" "0,1" newline bitfld.long 0x0 2. "LCK2,LCK2" "0,1" bitfld.long 0x0 1. "LCK1,LCK1" "0,1" bitfld.long 0x0 0. "LCK0,LCK0" "0,1" line.long 0x4 "GPIOA_AFRL,GPIO alternate function low register" hexmask.long.byte 0x4 28.--31. 1. "AFR7,AFR7" hexmask.long.byte 0x4 24.--27. 1. "AFR6,AFR6" hexmask.long.byte 0x4 20.--23. 1. "AFR5,AFR5" hexmask.long.byte 0x4 16.--19. 1. "AFR4,AFR4" hexmask.long.byte 0x4 12.--15. 1. "AFR3,AFR3" hexmask.long.byte 0x4 8.--11. 1. "AFR2,AFR2" hexmask.long.byte 0x4 4.--7. 1. "AFR1,AFR1" newline hexmask.long.byte 0x4 0.--3. 1. "AFR0,AFR0" line.long 0x8 "GPIOA_AFRH,GPIO alternate function high register" hexmask.long.byte 0x8 28.--31. 1. "AFR15,AFR15" hexmask.long.byte 0x8 24.--27. 1. "AFR14,AFR14" hexmask.long.byte 0x8 20.--23. 1. "AFR13,AFR13" hexmask.long.byte 0x8 16.--19. 1. "AFR12,AFR12" hexmask.long.byte 0x8 12.--15. 1. "AFR11,AFR11" hexmask.long.byte 0x8 8.--11. 1. "AFR10,AFR10" hexmask.long.byte 0x8 4.--7. 1. "AFR9,AFR9" newline hexmask.long.byte 0x8 0.--3. 1. "AFR8,AFR8" wgroup.long 0x28++0x3 line.long 0x0 "GPIOA_BRR,GPIO port bit reset register" bitfld.long 0x0 15. "BR15,BR15" "0,1" bitfld.long 0x0 14. "BR14,BR14" "0,1" bitfld.long 0x0 13. "BR13,BR13" "0,1" bitfld.long 0x0 12. "BR12,BR12" "0,1" bitfld.long 0x0 11. "BR11,BR11" "0,1" bitfld.long 0x0 10. "BR10,BR10" "0,1" bitfld.long 0x0 9. "BR9,BR9" "0,1" newline bitfld.long 0x0 8. "BR8,BR8" "0,1" bitfld.long 0x0 7. "BR7,BR7" "0,1" bitfld.long 0x0 6. "BR6,BR6" "0,1" bitfld.long 0x0 5. "BR5,BR5" "0,1" bitfld.long 0x0 4. "BR4,BR4" "0,1" bitfld.long 0x0 3. "BR3,BR3" "0,1" bitfld.long 0x0 2. "BR2,BR2" "0,1" newline bitfld.long 0x0 1. "BR1,BR1" "0,1" bitfld.long 0x0 0. "BR0,BR0" "0,1" group.long 0x30++0x3 line.long 0x0 "GPIOA_SECCFGR,GPIO secure configuration register" bitfld.long 0x0 15. "SEC15,SEC15" "0,1" bitfld.long 0x0 14. "SEC14,SEC14" "0,1" bitfld.long 0x0 13. "SEC13,SEC13" "0,1" bitfld.long 0x0 12. "SEC12,SEC12" "0,1" bitfld.long 0x0 11. "SEC11,SEC11" "0,1" bitfld.long 0x0 10. "SEC10,SEC10" "0,1" bitfld.long 0x0 9. "SEC9,SEC9" "0,1" newline bitfld.long 0x0 8. "SEC8,SEC8" "0,1" bitfld.long 0x0 7. "SEC7,SEC7" "0,1" bitfld.long 0x0 6. "SEC6,SEC6" "0,1" bitfld.long 0x0 5. "SEC5,SEC5" "0,1" bitfld.long 0x0 4. "SEC4,SEC4" "0,1" bitfld.long 0x0 3. "SEC3,SEC3" "0,1" bitfld.long 0x0 2. "SEC2,SEC2" "0,1" newline bitfld.long 0x0 1. "SEC1,SEC1" "0,1" bitfld.long 0x0 0. "SEC0,SEC0" "0,1" rgroup.long 0x3C8++0x37 line.long 0x0 "GPIOA_HWCFGR10,For GPIOA. B. C. D. E. F. G. H. I. J and GPIOK: For GPIOZ:" hexmask.long.byte 0x0 20.--23. 1. "OR_CFG,OR_CFG" hexmask.long.byte 0x0 16.--19. 1. "SEC_CFG,SEC_CFG" hexmask.long.byte 0x0 12.--15. 1. "LOCK_CFG,LOCK_CFG" hexmask.long.byte 0x0 8.--11. 1. "SPEED_CFG,SPEED_CFG" hexmask.long.byte 0x0 4.--7. 1. "AF_SIZE,AF_SIZE" hexmask.long.byte 0x0 0.--3. 1. "AHB_IOP,AHB_IOP" line.long 0x4 "GPIOA_HWCFGR9,For GPIOA. B. C. D. E. F. G. H. I. and GPIOJ: For GPIOK and GPIOZ:" hexmask.long.word 0x4 0.--15. 1. "EN_IO,EN_IO" line.long 0x8 "GPIOA_HWCFGR8,For GPIOA. B. C. D. E. F. G. H. I. and GPIOJ: For GPIOK and GPIOZ:" hexmask.long.byte 0x8 28.--31. 1. "AF_PRIO15,AF_PRIO15" hexmask.long.byte 0x8 24.--27. 1. "AF_PRIO14,AF_PRIO14" hexmask.long.byte 0x8 20.--23. 1. "AF_PRIO13,AF_PRIO13" hexmask.long.byte 0x8 16.--19. 1. "AF_PRIO12,AF_PRIO12" hexmask.long.byte 0x8 12.--15. 1. "AF_PRIO11,AF_PRIO11" hexmask.long.byte 0x8 8.--11. 1. "AF_PRIO10,AF_PRIO10" hexmask.long.byte 0x8 4.--7. 1. "AF_PRIO9,AF_PRIO9" newline hexmask.long.byte 0x8 0.--3. 1. "AF_PRIO8,AF_PRIO8" line.long 0xC "GPIOA_HWCFGR7,GPIO hardware configuration register 7" hexmask.long.byte 0xC 28.--31. 1. "AF_PRIO7,AF_PRIO7" hexmask.long.byte 0xC 24.--27. 1. "AF_PRIO6,AF_PRIO6" hexmask.long.byte 0xC 20.--23. 1. "AF_PRIO5,AF_PRIO5" hexmask.long.byte 0xC 16.--19. 1. "AF_PRIO4,AF_PRIO4" hexmask.long.byte 0xC 12.--15. 1. "AF_PRIO3,AF_PRIO3" hexmask.long.byte 0xC 8.--11. 1. "AF_PRIO2,AF_PRIO2" hexmask.long.byte 0xC 4.--7. 1. "AF_PRIO1,AF_PRIO1" newline hexmask.long.byte 0xC 0.--3. 1. "AF_PRIO0,AF_PRIO0" line.long 0x10 "GPIOA_HWCFGR6,GPIO hardware configuration register 6" hexmask.long 0x10 0.--31. 1. "MODER_RES,MODER_RES" line.long 0x14 "GPIOA_HWCFGR5,GPIO hardware configuration register 5" hexmask.long 0x14 0.--31. 1. "PUPDR_RES,PUPDR_RES" line.long 0x18 "GPIOA_HWCFGR4,GPIO hardware configuration register 4" hexmask.long 0x18 0.--31. 1. "OSPEED_RES,OSPEED_RES" line.long 0x1C "GPIOA_HWCFGR3,GPIO hardware configuration register 3" hexmask.long.word 0x1C 16.--31. 1. "OTYPER_RES,OTYPER_RES" hexmask.long.word 0x1C 0.--15. 1. "ODR_RES,ODR_RES" line.long 0x20 "GPIOA_HWCFGR2,GPIO hardware configuration register 2" hexmask.long 0x20 0.--31. 1. "AFRL_RES,AFRL_RES" line.long 0x24 "GPIOA_HWCFGR1,GPIO hardware configuration register 1" hexmask.long 0x24 0.--31. 1. "AFRH_RES,AFRH_RES" line.long 0x28 "GPIOA_HWCFGR0,GPIO hardware configuration register 0" hexmask.long.word 0x28 0.--15. 1. "OR_RES,OR_RES" line.long 0x2C "GPIOA_VERR,GPIO version register" hexmask.long.byte 0x2C 4.--7. 1. "MAJREV,MAJREV" hexmask.long.byte 0x2C 0.--3. 1. "MINREV,MINREV" line.long 0x30 "GPIOA_IPIDR,GPIO identification register" hexmask.long 0x30 0.--31. 1. "IPIDR,IPIDR" line.long 0x34 "GPIOA_SIDR,GPIO size identification register" hexmask.long 0x34 0.--31. 1. "SIDR,SIDR" tree.end endif sif (cpuis("STM32MP13*")) tree "GPIOB" base ad:0x50003000 group.long 0x0++0xF line.long 0x0 "GPIOB_MODER,GPIO port mode register" bitfld.long 0x0 30.--31. "MODER15,MODER15" "0,1,2,3" bitfld.long 0x0 28.--29. "MODER14,MODER14" "0,1,2,3" bitfld.long 0x0 26.--27. "MODER13,MODER13" "0,1,2,3" bitfld.long 0x0 24.--25. "MODER12,MODER12" "0,1,2,3" bitfld.long 0x0 22.--23. "MODER11,MODER11" "0,1,2,3" bitfld.long 0x0 20.--21. "MODER10,MODER10" "0,1,2,3" bitfld.long 0x0 18.--19. "MODER9,MODER9" "0,1,2,3" newline bitfld.long 0x0 16.--17. "MODER8,MODER8" "0,1,2,3" bitfld.long 0x0 14.--15. "MODER7,MODER7" "0,1,2,3" bitfld.long 0x0 12.--13. "MODER6,MODER6" "0,1,2,3" bitfld.long 0x0 10.--11. "MODER5,MODER5" "0,1,2,3" bitfld.long 0x0 8.--9. "MODER4,MODER4" "0,1,2,3" bitfld.long 0x0 6.--7. "MODER3,MODER3" "0,1,2,3" bitfld.long 0x0 4.--5. "MODER2,MODER2" "0,1,2,3" newline bitfld.long 0x0 2.--3. "MODER1,MODER1" "0,1,2,3" bitfld.long 0x0 0.--1. "MODER0,MODER0" "0,1,2,3" line.long 0x4 "GPIOB_OTYPER,GPIO port output type register" bitfld.long 0x4 15. "OT15,OT15" "0,1" bitfld.long 0x4 14. "OT14,OT14" "0,1" bitfld.long 0x4 13. "OT13,OT13" "0,1" bitfld.long 0x4 12. "OT12,OT12" "0,1" bitfld.long 0x4 11. "OT11,OT11" "0,1" bitfld.long 0x4 10. "OT10,OT10" "0,1" bitfld.long 0x4 9. "OT9,OT9" "0,1" newline bitfld.long 0x4 8. "OT8,OT8" "0,1" bitfld.long 0x4 7. "OT7,OT7" "0,1" bitfld.long 0x4 6. "OT6,OT6" "0,1" bitfld.long 0x4 5. "OT5,OT5" "0,1" bitfld.long 0x4 4. "OT4,OT4" "0,1" bitfld.long 0x4 3. "OT3,OT3" "0,1" bitfld.long 0x4 2. "OT2,OT2" "0,1" newline bitfld.long 0x4 1. "OT1,OT1" "0,1" bitfld.long 0x4 0. "OT0,OT0" "0,1" line.long 0x8 "GPIOB_OSPEEDR,GPIO port output speed register" bitfld.long 0x8 30.--31. "OSPEEDR15,OSPEEDR15" "0,1,2,3" bitfld.long 0x8 28.--29. "OSPEEDR14,OSPEEDR14" "0,1,2,3" bitfld.long 0x8 26.--27. "OSPEEDR13,OSPEEDR13" "0,1,2,3" bitfld.long 0x8 24.--25. "OSPEEDR12,OSPEEDR12" "0,1,2,3" bitfld.long 0x8 22.--23. "OSPEEDR11,OSPEEDR11" "0,1,2,3" bitfld.long 0x8 20.--21. "OSPEEDR10,OSPEEDR10" "0,1,2,3" bitfld.long 0x8 18.--19. "OSPEEDR9,OSPEEDR9" "0,1,2,3" newline bitfld.long 0x8 16.--17. "OSPEEDR8,OSPEEDR8" "0,1,2,3" bitfld.long 0x8 14.--15. "OSPEEDR7,OSPEEDR7" "0,1,2,3" bitfld.long 0x8 12.--13. "OSPEEDR6,OSPEEDR6" "0,1,2,3" bitfld.long 0x8 10.--11. "OSPEEDR5,OSPEEDR5" "0,1,2,3" bitfld.long 0x8 8.--9. "OSPEEDR4,OSPEEDR4" "0,1,2,3" bitfld.long 0x8 6.--7. "OSPEEDR3,OSPEEDR3" "0,1,2,3" bitfld.long 0x8 4.--5. "OSPEEDR2,OSPEEDR2" "0,1,2,3" newline bitfld.long 0x8 2.--3. "OSPEEDR1,OSPEEDR1" "0,1,2,3" bitfld.long 0x8 0.--1. "OSPEEDR0,OSPEEDR0" "0,1,2,3" line.long 0xC "GPIOB_PUPDR,GPIO port pull-up/pull-down register" bitfld.long 0xC 30.--31. "PUPDR15,PUPDR15" "0,1,2,3" bitfld.long 0xC 28.--29. "PUPDR14,PUPDR14" "0,1,2,3" bitfld.long 0xC 26.--27. "PUPDR13,PUPDR13" "0,1,2,3" bitfld.long 0xC 24.--25. "PUPDR12,PUPDR12" "0,1,2,3" bitfld.long 0xC 22.--23. "PUPDR11,PUPDR11" "0,1,2,3" bitfld.long 0xC 20.--21. "PUPDR10,PUPDR10" "0,1,2,3" bitfld.long 0xC 18.--19. "PUPDR9,PUPDR9" "0,1,2,3" newline bitfld.long 0xC 16.--17. "PUPDR8,PUPDR8" "0,1,2,3" bitfld.long 0xC 14.--15. "PUPDR7,PUPDR7" "0,1,2,3" bitfld.long 0xC 12.--13. "PUPDR6,PUPDR6" "0,1,2,3" bitfld.long 0xC 10.--11. "PUPDR5,PUPDR5" "0,1,2,3" bitfld.long 0xC 8.--9. "PUPDR4,PUPDR4" "0,1,2,3" bitfld.long 0xC 6.--7. "PUPDR3,PUPDR3" "0,1,2,3" bitfld.long 0xC 4.--5. "PUPDR2,PUPDR2" "0,1,2,3" newline bitfld.long 0xC 2.--3. "PUPDR1,PUPDR1" "0,1,2,3" bitfld.long 0xC 0.--1. "PUPDR0,PUPDR0" "0,1,2,3" rgroup.long 0x10++0x3 line.long 0x0 "GPIOB_IDR,GPIO port input data register" bitfld.long 0x0 15. "IDR15,IDR15" "0,1" bitfld.long 0x0 14. "IDR14,IDR14" "0,1" bitfld.long 0x0 13. "IDR13,IDR13" "0,1" bitfld.long 0x0 12. "IDR12,IDR12" "0,1" bitfld.long 0x0 11. "IDR11,IDR11" "0,1" bitfld.long 0x0 10. "IDR10,IDR10" "0,1" bitfld.long 0x0 9. "IDR9,IDR9" "0,1" newline bitfld.long 0x0 8. "IDR8,IDR8" "0,1" bitfld.long 0x0 7. "IDR7,IDR7" "0,1" bitfld.long 0x0 6. "IDR6,IDR6" "0,1" bitfld.long 0x0 5. "IDR5,IDR5" "0,1" bitfld.long 0x0 4. "IDR4,IDR4" "0,1" bitfld.long 0x0 3. "IDR3,IDR3" "0,1" bitfld.long 0x0 2. "IDR2,IDR2" "0,1" newline bitfld.long 0x0 1. "IDR1,IDR1" "0,1" bitfld.long 0x0 0. "IDR0,IDR0" "0,1" group.long 0x14++0x3 line.long 0x0 "GPIOB_ODR,GPIO port output data register" bitfld.long 0x0 15. "ODR15,ODR15" "0,1" bitfld.long 0x0 14. "ODR14,ODR14" "0,1" bitfld.long 0x0 13. "ODR13,ODR13" "0,1" bitfld.long 0x0 12. "ODR12,ODR12" "0,1" bitfld.long 0x0 11. "ODR11,ODR11" "0,1" bitfld.long 0x0 10. "ODR10,ODR10" "0,1" bitfld.long 0x0 9. "ODR9,ODR9" "0,1" newline bitfld.long 0x0 8. "ODR8,ODR8" "0,1" bitfld.long 0x0 7. "ODR7,ODR7" "0,1" bitfld.long 0x0 6. "ODR6,ODR6" "0,1" bitfld.long 0x0 5. "ODR5,ODR5" "0,1" bitfld.long 0x0 4. "ODR4,ODR4" "0,1" bitfld.long 0x0 3. "ODR3,ODR3" "0,1" bitfld.long 0x0 2. "ODR2,ODR2" "0,1" newline bitfld.long 0x0 1. "ODR1,ODR1" "0,1" bitfld.long 0x0 0. "ODR0,ODR0" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "GPIOB_BSRR,GPIO port bit set/reset register" bitfld.long 0x0 31. "BR15,BR15" "0,1" bitfld.long 0x0 30. "BR14,BR14" "0,1" bitfld.long 0x0 29. "BR13,BR13" "0,1" bitfld.long 0x0 28. "BR12,BR12" "0,1" bitfld.long 0x0 27. "BR11,BR11" "0,1" bitfld.long 0x0 26. "BR10,BR10" "0,1" bitfld.long 0x0 25. "BR9,BR9" "0,1" newline bitfld.long 0x0 24. "BR8,BR8" "0,1" bitfld.long 0x0 23. "BR7,BR7" "0,1" bitfld.long 0x0 22. "BR6,BR6" "0,1" bitfld.long 0x0 21. "BR5,BR5" "0,1" bitfld.long 0x0 20. "BR4,BR4" "0,1" bitfld.long 0x0 19. "BR3,BR3" "0,1" bitfld.long 0x0 18. "BR2,BR2" "0,1" newline bitfld.long 0x0 17. "BR1,BR1" "0,1" bitfld.long 0x0 16. "BR0,BR0" "0,1" bitfld.long 0x0 15. "BS15,BS15" "0,1" bitfld.long 0x0 14. "BS14,BS14" "0,1" bitfld.long 0x0 13. "BS13,BS13" "0,1" bitfld.long 0x0 12. "BS12,BS12" "0,1" bitfld.long 0x0 11. "BS11,BS11" "0,1" newline bitfld.long 0x0 10. "BS10,BS10" "0,1" bitfld.long 0x0 9. "BS9,BS9" "0,1" bitfld.long 0x0 8. "BS8,BS8" "0,1" bitfld.long 0x0 7. "BS7,BS7" "0,1" bitfld.long 0x0 6. "BS6,BS6" "0,1" bitfld.long 0x0 5. "BS5,BS5" "0,1" bitfld.long 0x0 4. "BS4,BS4" "0,1" newline bitfld.long 0x0 3. "BS3,BS3" "0,1" bitfld.long 0x0 2. "BS2,BS2" "0,1" bitfld.long 0x0 1. "BS1,BS1" "0,1" bitfld.long 0x0 0. "BS0,BS0" "0,1" group.long 0x1C++0xB line.long 0x0 "GPIOB_LCKR,This register is used to lock the configuration of the port bits when a correct write sequence is applied to bit 16 (LCKK). The value of bits [15:0] is used to lock the configuration of the GPIO. During the write sequence. the value of.." bitfld.long 0x0 16. "LCKK,LCKK" "0,1" bitfld.long 0x0 15. "LCK15,LCK15" "0,1" bitfld.long 0x0 14. "LCK14,LCK14" "0,1" bitfld.long 0x0 13. "LCK13,LCK13" "0,1" bitfld.long 0x0 12. "LCK12,LCK12" "0,1" bitfld.long 0x0 11. "LCK11,LCK11" "0,1" bitfld.long 0x0 10. "LCK10,LCK10" "0,1" newline bitfld.long 0x0 9. "LCK9,LCK9" "0,1" bitfld.long 0x0 8. "LCK8,LCK8" "0,1" bitfld.long 0x0 7. "LCK7,LCK7" "0,1" bitfld.long 0x0 6. "LCK6,LCK6" "0,1" bitfld.long 0x0 5. "LCK5,LCK5" "0,1" bitfld.long 0x0 4. "LCK4,LCK4" "0,1" bitfld.long 0x0 3. "LCK3,LCK3" "0,1" newline bitfld.long 0x0 2. "LCK2,LCK2" "0,1" bitfld.long 0x0 1. "LCK1,LCK1" "0,1" bitfld.long 0x0 0. "LCK0,LCK0" "0,1" line.long 0x4 "GPIOB_AFRL,GPIO alternate function low register" hexmask.long.byte 0x4 28.--31. 1. "AFR7,AFR7" hexmask.long.byte 0x4 24.--27. 1. "AFR6,AFR6" hexmask.long.byte 0x4 20.--23. 1. "AFR5,AFR5" hexmask.long.byte 0x4 16.--19. 1. "AFR4,AFR4" hexmask.long.byte 0x4 12.--15. 1. "AFR3,AFR3" hexmask.long.byte 0x4 8.--11. 1. "AFR2,AFR2" hexmask.long.byte 0x4 4.--7. 1. "AFR1,AFR1" newline hexmask.long.byte 0x4 0.--3. 1. "AFR0,AFR0" line.long 0x8 "GPIOB_AFRH,GPIO alternate function high register" hexmask.long.byte 0x8 28.--31. 1. "AFR15,AFR15" hexmask.long.byte 0x8 24.--27. 1. "AFR14,AFR14" hexmask.long.byte 0x8 20.--23. 1. "AFR13,AFR13" hexmask.long.byte 0x8 16.--19. 1. "AFR12,AFR12" hexmask.long.byte 0x8 12.--15. 1. "AFR11,AFR11" hexmask.long.byte 0x8 8.--11. 1. "AFR10,AFR10" hexmask.long.byte 0x8 4.--7. 1. "AFR9,AFR9" newline hexmask.long.byte 0x8 0.--3. 1. "AFR8,AFR8" wgroup.long 0x28++0x3 line.long 0x0 "GPIOB_BRR,GPIO port bit reset register" bitfld.long 0x0 15. "BR15,BR15" "0,1" bitfld.long 0x0 14. "BR14,BR14" "0,1" bitfld.long 0x0 13. "BR13,BR13" "0,1" bitfld.long 0x0 12. "BR12,BR12" "0,1" bitfld.long 0x0 11. "BR11,BR11" "0,1" bitfld.long 0x0 10. "BR10,BR10" "0,1" bitfld.long 0x0 9. "BR9,BR9" "0,1" newline bitfld.long 0x0 8. "BR8,BR8" "0,1" bitfld.long 0x0 7. "BR7,BR7" "0,1" bitfld.long 0x0 6. "BR6,BR6" "0,1" bitfld.long 0x0 5. "BR5,BR5" "0,1" bitfld.long 0x0 4. "BR4,BR4" "0,1" bitfld.long 0x0 3. "BR3,BR3" "0,1" bitfld.long 0x0 2. "BR2,BR2" "0,1" newline bitfld.long 0x0 1. "BR1,BR1" "0,1" bitfld.long 0x0 0. "BR0,BR0" "0,1" group.long 0x30++0x3 line.long 0x0 "GPIOB_SECCFGR,GPIO secure configuration register" bitfld.long 0x0 15. "SEC15,SEC15" "0,1" bitfld.long 0x0 14. "SEC14,SEC14" "0,1" bitfld.long 0x0 13. "SEC13,SEC13" "0,1" bitfld.long 0x0 12. "SEC12,SEC12" "0,1" bitfld.long 0x0 11. "SEC11,SEC11" "0,1" bitfld.long 0x0 10. "SEC10,SEC10" "0,1" bitfld.long 0x0 9. "SEC9,SEC9" "0,1" newline bitfld.long 0x0 8. "SEC8,SEC8" "0,1" bitfld.long 0x0 7. "SEC7,SEC7" "0,1" bitfld.long 0x0 6. "SEC6,SEC6" "0,1" bitfld.long 0x0 5. "SEC5,SEC5" "0,1" bitfld.long 0x0 4. "SEC4,SEC4" "0,1" bitfld.long 0x0 3. "SEC3,SEC3" "0,1" bitfld.long 0x0 2. "SEC2,SEC2" "0,1" newline bitfld.long 0x0 1. "SEC1,SEC1" "0,1" bitfld.long 0x0 0. "SEC0,SEC0" "0,1" rgroup.long 0x3C8++0x37 line.long 0x0 "GPIOB_HWCFGR10,For GPIOA. B. C. D. E. F. G. H. I. J and GPIOK: For GPIOZ:" hexmask.long.byte 0x0 20.--23. 1. "OR_CFG,OR_CFG" hexmask.long.byte 0x0 16.--19. 1. "SEC_CFG,SEC_CFG" hexmask.long.byte 0x0 12.--15. 1. "LOCK_CFG,LOCK_CFG" hexmask.long.byte 0x0 8.--11. 1. "SPEED_CFG,SPEED_CFG" hexmask.long.byte 0x0 4.--7. 1. "AF_SIZE,AF_SIZE" hexmask.long.byte 0x0 0.--3. 1. "AHB_IOP,AHB_IOP" line.long 0x4 "GPIOB_HWCFGR9,For GPIOA. B. C. D. E. F. G. H. I. and GPIOJ: For GPIOK and GPIOZ:" hexmask.long.word 0x4 0.--15. 1. "EN_IO,EN_IO" line.long 0x8 "GPIOB_HWCFGR8,For GPIOA. B. C. D. E. F. G. H. I. and GPIOJ: For GPIOK and GPIOZ:" hexmask.long.byte 0x8 28.--31. 1. "AF_PRIO15,AF_PRIO15" hexmask.long.byte 0x8 24.--27. 1. "AF_PRIO14,AF_PRIO14" hexmask.long.byte 0x8 20.--23. 1. "AF_PRIO13,AF_PRIO13" hexmask.long.byte 0x8 16.--19. 1. "AF_PRIO12,AF_PRIO12" hexmask.long.byte 0x8 12.--15. 1. "AF_PRIO11,AF_PRIO11" hexmask.long.byte 0x8 8.--11. 1. "AF_PRIO10,AF_PRIO10" hexmask.long.byte 0x8 4.--7. 1. "AF_PRIO9,AF_PRIO9" newline hexmask.long.byte 0x8 0.--3. 1. "AF_PRIO8,AF_PRIO8" line.long 0xC "GPIOB_HWCFGR7,GPIO hardware configuration register 7" hexmask.long.byte 0xC 28.--31. 1. "AF_PRIO7,AF_PRIO7" hexmask.long.byte 0xC 24.--27. 1. "AF_PRIO6,AF_PRIO6" hexmask.long.byte 0xC 20.--23. 1. "AF_PRIO5,AF_PRIO5" hexmask.long.byte 0xC 16.--19. 1. "AF_PRIO4,AF_PRIO4" hexmask.long.byte 0xC 12.--15. 1. "AF_PRIO3,AF_PRIO3" hexmask.long.byte 0xC 8.--11. 1. "AF_PRIO2,AF_PRIO2" hexmask.long.byte 0xC 4.--7. 1. "AF_PRIO1,AF_PRIO1" newline hexmask.long.byte 0xC 0.--3. 1. "AF_PRIO0,AF_PRIO0" line.long 0x10 "GPIOB_HWCFGR6,GPIO hardware configuration register 6" hexmask.long 0x10 0.--31. 1. "MODER_RES,MODER_RES" line.long 0x14 "GPIOB_HWCFGR5,GPIO hardware configuration register 5" hexmask.long 0x14 0.--31. 1. "PUPDR_RES,PUPDR_RES" line.long 0x18 "GPIOB_HWCFGR4,GPIO hardware configuration register 4" hexmask.long 0x18 0.--31. 1. "OSPEED_RES,OSPEED_RES" line.long 0x1C "GPIOB_HWCFGR3,GPIO hardware configuration register 3" hexmask.long.word 0x1C 16.--31. 1. "OTYPER_RES,OTYPER_RES" hexmask.long.word 0x1C 0.--15. 1. "ODR_RES,ODR_RES" line.long 0x20 "GPIOB_HWCFGR2,GPIO hardware configuration register 2" hexmask.long 0x20 0.--31. 1. "AFRL_RES,AFRL_RES" line.long 0x24 "GPIOB_HWCFGR1,GPIO hardware configuration register 1" hexmask.long 0x24 0.--31. 1. "AFRH_RES,AFRH_RES" line.long 0x28 "GPIOB_HWCFGR0,GPIO hardware configuration register 0" hexmask.long.word 0x28 0.--15. 1. "OR_RES,OR_RES" line.long 0x2C "GPIOB_VERR,GPIO version register" hexmask.long.byte 0x2C 4.--7. 1. "MAJREV,MAJREV" hexmask.long.byte 0x2C 0.--3. 1. "MINREV,MINREV" line.long 0x30 "GPIOB_IPIDR,GPIO identification register" hexmask.long 0x30 0.--31. 1. "IPIDR,IPIDR" line.long 0x34 "GPIOB_SIDR,GPIO size identification register" hexmask.long 0x34 0.--31. 1. "SIDR,SIDR" tree.end endif sif (cpuis("STM32MP13*")) tree "GPIOC" base ad:0x50004000 group.long 0x0++0xF line.long 0x0 "GPIOC_MODER,GPIO port mode register" bitfld.long 0x0 30.--31. "MODER15,MODER15" "0,1,2,3" bitfld.long 0x0 28.--29. "MODER14,MODER14" "0,1,2,3" bitfld.long 0x0 26.--27. "MODER13,MODER13" "0,1,2,3" bitfld.long 0x0 24.--25. "MODER12,MODER12" "0,1,2,3" bitfld.long 0x0 22.--23. "MODER11,MODER11" "0,1,2,3" bitfld.long 0x0 20.--21. "MODER10,MODER10" "0,1,2,3" bitfld.long 0x0 18.--19. "MODER9,MODER9" "0,1,2,3" newline bitfld.long 0x0 16.--17. "MODER8,MODER8" "0,1,2,3" bitfld.long 0x0 14.--15. "MODER7,MODER7" "0,1,2,3" bitfld.long 0x0 12.--13. "MODER6,MODER6" "0,1,2,3" bitfld.long 0x0 10.--11. "MODER5,MODER5" "0,1,2,3" bitfld.long 0x0 8.--9. "MODER4,MODER4" "0,1,2,3" bitfld.long 0x0 6.--7. "MODER3,MODER3" "0,1,2,3" bitfld.long 0x0 4.--5. "MODER2,MODER2" "0,1,2,3" newline bitfld.long 0x0 2.--3. "MODER1,MODER1" "0,1,2,3" bitfld.long 0x0 0.--1. "MODER0,MODER0" "0,1,2,3" line.long 0x4 "GPIOC_OTYPER,GPIO port output type register" bitfld.long 0x4 15. "OT15,OT15" "0,1" bitfld.long 0x4 14. "OT14,OT14" "0,1" bitfld.long 0x4 13. "OT13,OT13" "0,1" bitfld.long 0x4 12. "OT12,OT12" "0,1" bitfld.long 0x4 11. "OT11,OT11" "0,1" bitfld.long 0x4 10. "OT10,OT10" "0,1" bitfld.long 0x4 9. "OT9,OT9" "0,1" newline bitfld.long 0x4 8. "OT8,OT8" "0,1" bitfld.long 0x4 7. "OT7,OT7" "0,1" bitfld.long 0x4 6. "OT6,OT6" "0,1" bitfld.long 0x4 5. "OT5,OT5" "0,1" bitfld.long 0x4 4. "OT4,OT4" "0,1" bitfld.long 0x4 3. "OT3,OT3" "0,1" bitfld.long 0x4 2. "OT2,OT2" "0,1" newline bitfld.long 0x4 1. "OT1,OT1" "0,1" bitfld.long 0x4 0. "OT0,OT0" "0,1" line.long 0x8 "GPIOC_OSPEEDR,GPIO port output speed register" bitfld.long 0x8 30.--31. "OSPEEDR15,OSPEEDR15" "0,1,2,3" bitfld.long 0x8 28.--29. "OSPEEDR14,OSPEEDR14" "0,1,2,3" bitfld.long 0x8 26.--27. "OSPEEDR13,OSPEEDR13" "0,1,2,3" bitfld.long 0x8 24.--25. "OSPEEDR12,OSPEEDR12" "0,1,2,3" bitfld.long 0x8 22.--23. "OSPEEDR11,OSPEEDR11" "0,1,2,3" bitfld.long 0x8 20.--21. "OSPEEDR10,OSPEEDR10" "0,1,2,3" bitfld.long 0x8 18.--19. "OSPEEDR9,OSPEEDR9" "0,1,2,3" newline bitfld.long 0x8 16.--17. "OSPEEDR8,OSPEEDR8" "0,1,2,3" bitfld.long 0x8 14.--15. "OSPEEDR7,OSPEEDR7" "0,1,2,3" bitfld.long 0x8 12.--13. "OSPEEDR6,OSPEEDR6" "0,1,2,3" bitfld.long 0x8 10.--11. "OSPEEDR5,OSPEEDR5" "0,1,2,3" bitfld.long 0x8 8.--9. "OSPEEDR4,OSPEEDR4" "0,1,2,3" bitfld.long 0x8 6.--7. "OSPEEDR3,OSPEEDR3" "0,1,2,3" bitfld.long 0x8 4.--5. "OSPEEDR2,OSPEEDR2" "0,1,2,3" newline bitfld.long 0x8 2.--3. "OSPEEDR1,OSPEEDR1" "0,1,2,3" bitfld.long 0x8 0.--1. "OSPEEDR0,OSPEEDR0" "0,1,2,3" line.long 0xC "GPIOC_PUPDR,GPIO port pull-up/pull-down register" bitfld.long 0xC 30.--31. "PUPDR15,PUPDR15" "0,1,2,3" bitfld.long 0xC 28.--29. "PUPDR14,PUPDR14" "0,1,2,3" bitfld.long 0xC 26.--27. "PUPDR13,PUPDR13" "0,1,2,3" bitfld.long 0xC 24.--25. "PUPDR12,PUPDR12" "0,1,2,3" bitfld.long 0xC 22.--23. "PUPDR11,PUPDR11" "0,1,2,3" bitfld.long 0xC 20.--21. "PUPDR10,PUPDR10" "0,1,2,3" bitfld.long 0xC 18.--19. "PUPDR9,PUPDR9" "0,1,2,3" newline bitfld.long 0xC 16.--17. "PUPDR8,PUPDR8" "0,1,2,3" bitfld.long 0xC 14.--15. "PUPDR7,PUPDR7" "0,1,2,3" bitfld.long 0xC 12.--13. "PUPDR6,PUPDR6" "0,1,2,3" bitfld.long 0xC 10.--11. "PUPDR5,PUPDR5" "0,1,2,3" bitfld.long 0xC 8.--9. "PUPDR4,PUPDR4" "0,1,2,3" bitfld.long 0xC 6.--7. "PUPDR3,PUPDR3" "0,1,2,3" bitfld.long 0xC 4.--5. "PUPDR2,PUPDR2" "0,1,2,3" newline bitfld.long 0xC 2.--3. "PUPDR1,PUPDR1" "0,1,2,3" bitfld.long 0xC 0.--1. "PUPDR0,PUPDR0" "0,1,2,3" rgroup.long 0x10++0x3 line.long 0x0 "GPIOC_IDR,GPIO port input data register" bitfld.long 0x0 15. "IDR15,IDR15" "0,1" bitfld.long 0x0 14. "IDR14,IDR14" "0,1" bitfld.long 0x0 13. "IDR13,IDR13" "0,1" bitfld.long 0x0 12. "IDR12,IDR12" "0,1" bitfld.long 0x0 11. "IDR11,IDR11" "0,1" bitfld.long 0x0 10. "IDR10,IDR10" "0,1" bitfld.long 0x0 9. "IDR9,IDR9" "0,1" newline bitfld.long 0x0 8. "IDR8,IDR8" "0,1" bitfld.long 0x0 7. "IDR7,IDR7" "0,1" bitfld.long 0x0 6. "IDR6,IDR6" "0,1" bitfld.long 0x0 5. "IDR5,IDR5" "0,1" bitfld.long 0x0 4. "IDR4,IDR4" "0,1" bitfld.long 0x0 3. "IDR3,IDR3" "0,1" bitfld.long 0x0 2. "IDR2,IDR2" "0,1" newline bitfld.long 0x0 1. "IDR1,IDR1" "0,1" bitfld.long 0x0 0. "IDR0,IDR0" "0,1" group.long 0x14++0x3 line.long 0x0 "GPIOC_ODR,GPIO port output data register" bitfld.long 0x0 15. "ODR15,ODR15" "0,1" bitfld.long 0x0 14. "ODR14,ODR14" "0,1" bitfld.long 0x0 13. "ODR13,ODR13" "0,1" bitfld.long 0x0 12. "ODR12,ODR12" "0,1" bitfld.long 0x0 11. "ODR11,ODR11" "0,1" bitfld.long 0x0 10. "ODR10,ODR10" "0,1" bitfld.long 0x0 9. "ODR9,ODR9" "0,1" newline bitfld.long 0x0 8. "ODR8,ODR8" "0,1" bitfld.long 0x0 7. "ODR7,ODR7" "0,1" bitfld.long 0x0 6. "ODR6,ODR6" "0,1" bitfld.long 0x0 5. "ODR5,ODR5" "0,1" bitfld.long 0x0 4. "ODR4,ODR4" "0,1" bitfld.long 0x0 3. "ODR3,ODR3" "0,1" bitfld.long 0x0 2. "ODR2,ODR2" "0,1" newline bitfld.long 0x0 1. "ODR1,ODR1" "0,1" bitfld.long 0x0 0. "ODR0,ODR0" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "GPIOC_BSRR,GPIO port bit set/reset register" bitfld.long 0x0 31. "BR15,BR15" "0,1" bitfld.long 0x0 30. "BR14,BR14" "0,1" bitfld.long 0x0 29. "BR13,BR13" "0,1" bitfld.long 0x0 28. "BR12,BR12" "0,1" bitfld.long 0x0 27. "BR11,BR11" "0,1" bitfld.long 0x0 26. "BR10,BR10" "0,1" bitfld.long 0x0 25. "BR9,BR9" "0,1" newline bitfld.long 0x0 24. "BR8,BR8" "0,1" bitfld.long 0x0 23. "BR7,BR7" "0,1" bitfld.long 0x0 22. "BR6,BR6" "0,1" bitfld.long 0x0 21. "BR5,BR5" "0,1" bitfld.long 0x0 20. "BR4,BR4" "0,1" bitfld.long 0x0 19. "BR3,BR3" "0,1" bitfld.long 0x0 18. "BR2,BR2" "0,1" newline bitfld.long 0x0 17. "BR1,BR1" "0,1" bitfld.long 0x0 16. "BR0,BR0" "0,1" bitfld.long 0x0 15. "BS15,BS15" "0,1" bitfld.long 0x0 14. "BS14,BS14" "0,1" bitfld.long 0x0 13. "BS13,BS13" "0,1" bitfld.long 0x0 12. "BS12,BS12" "0,1" bitfld.long 0x0 11. "BS11,BS11" "0,1" newline bitfld.long 0x0 10. "BS10,BS10" "0,1" bitfld.long 0x0 9. "BS9,BS9" "0,1" bitfld.long 0x0 8. "BS8,BS8" "0,1" bitfld.long 0x0 7. "BS7,BS7" "0,1" bitfld.long 0x0 6. "BS6,BS6" "0,1" bitfld.long 0x0 5. "BS5,BS5" "0,1" bitfld.long 0x0 4. "BS4,BS4" "0,1" newline bitfld.long 0x0 3. "BS3,BS3" "0,1" bitfld.long 0x0 2. "BS2,BS2" "0,1" bitfld.long 0x0 1. "BS1,BS1" "0,1" bitfld.long 0x0 0. "BS0,BS0" "0,1" group.long 0x1C++0xB line.long 0x0 "GPIOC_LCKR,This register is used to lock the configuration of the port bits when a correct write sequence is applied to bit 16 (LCKK). The value of bits [15:0] is used to lock the configuration of the GPIO. During the write sequence. the value of.." bitfld.long 0x0 16. "LCKK,LCKK" "0,1" bitfld.long 0x0 15. "LCK15,LCK15" "0,1" bitfld.long 0x0 14. "LCK14,LCK14" "0,1" bitfld.long 0x0 13. "LCK13,LCK13" "0,1" bitfld.long 0x0 12. "LCK12,LCK12" "0,1" bitfld.long 0x0 11. "LCK11,LCK11" "0,1" bitfld.long 0x0 10. "LCK10,LCK10" "0,1" newline bitfld.long 0x0 9. "LCK9,LCK9" "0,1" bitfld.long 0x0 8. "LCK8,LCK8" "0,1" bitfld.long 0x0 7. "LCK7,LCK7" "0,1" bitfld.long 0x0 6. "LCK6,LCK6" "0,1" bitfld.long 0x0 5. "LCK5,LCK5" "0,1" bitfld.long 0x0 4. "LCK4,LCK4" "0,1" bitfld.long 0x0 3. "LCK3,LCK3" "0,1" newline bitfld.long 0x0 2. "LCK2,LCK2" "0,1" bitfld.long 0x0 1. "LCK1,LCK1" "0,1" bitfld.long 0x0 0. "LCK0,LCK0" "0,1" line.long 0x4 "GPIOC_AFRL,GPIO alternate function low register" hexmask.long.byte 0x4 28.--31. 1. "AFR7,AFR7" hexmask.long.byte 0x4 24.--27. 1. "AFR6,AFR6" hexmask.long.byte 0x4 20.--23. 1. "AFR5,AFR5" hexmask.long.byte 0x4 16.--19. 1. "AFR4,AFR4" hexmask.long.byte 0x4 12.--15. 1. "AFR3,AFR3" hexmask.long.byte 0x4 8.--11. 1. "AFR2,AFR2" hexmask.long.byte 0x4 4.--7. 1. "AFR1,AFR1" newline hexmask.long.byte 0x4 0.--3. 1. "AFR0,AFR0" line.long 0x8 "GPIOC_AFRH,GPIO alternate function high register" hexmask.long.byte 0x8 28.--31. 1. "AFR15,AFR15" hexmask.long.byte 0x8 24.--27. 1. "AFR14,AFR14" hexmask.long.byte 0x8 20.--23. 1. "AFR13,AFR13" hexmask.long.byte 0x8 16.--19. 1. "AFR12,AFR12" hexmask.long.byte 0x8 12.--15. 1. "AFR11,AFR11" hexmask.long.byte 0x8 8.--11. 1. "AFR10,AFR10" hexmask.long.byte 0x8 4.--7. 1. "AFR9,AFR9" newline hexmask.long.byte 0x8 0.--3. 1. "AFR8,AFR8" wgroup.long 0x28++0x3 line.long 0x0 "GPIOC_BRR,GPIO port bit reset register" bitfld.long 0x0 15. "BR15,BR15" "0,1" bitfld.long 0x0 14. "BR14,BR14" "0,1" bitfld.long 0x0 13. "BR13,BR13" "0,1" bitfld.long 0x0 12. "BR12,BR12" "0,1" bitfld.long 0x0 11. "BR11,BR11" "0,1" bitfld.long 0x0 10. "BR10,BR10" "0,1" bitfld.long 0x0 9. "BR9,BR9" "0,1" newline bitfld.long 0x0 8. "BR8,BR8" "0,1" bitfld.long 0x0 7. "BR7,BR7" "0,1" bitfld.long 0x0 6. "BR6,BR6" "0,1" bitfld.long 0x0 5. "BR5,BR5" "0,1" bitfld.long 0x0 4. "BR4,BR4" "0,1" bitfld.long 0x0 3. "BR3,BR3" "0,1" bitfld.long 0x0 2. "BR2,BR2" "0,1" newline bitfld.long 0x0 1. "BR1,BR1" "0,1" bitfld.long 0x0 0. "BR0,BR0" "0,1" group.long 0x30++0x3 line.long 0x0 "GPIOC_SECCFGR,GPIO secure configuration register" bitfld.long 0x0 15. "SEC15,SEC15" "0,1" bitfld.long 0x0 14. "SEC14,SEC14" "0,1" bitfld.long 0x0 13. "SEC13,SEC13" "0,1" bitfld.long 0x0 12. "SEC12,SEC12" "0,1" bitfld.long 0x0 11. "SEC11,SEC11" "0,1" bitfld.long 0x0 10. "SEC10,SEC10" "0,1" bitfld.long 0x0 9. "SEC9,SEC9" "0,1" newline bitfld.long 0x0 8. "SEC8,SEC8" "0,1" bitfld.long 0x0 7. "SEC7,SEC7" "0,1" bitfld.long 0x0 6. "SEC6,SEC6" "0,1" bitfld.long 0x0 5. "SEC5,SEC5" "0,1" bitfld.long 0x0 4. "SEC4,SEC4" "0,1" bitfld.long 0x0 3. "SEC3,SEC3" "0,1" bitfld.long 0x0 2. "SEC2,SEC2" "0,1" newline bitfld.long 0x0 1. "SEC1,SEC1" "0,1" bitfld.long 0x0 0. "SEC0,SEC0" "0,1" rgroup.long 0x3C8++0x37 line.long 0x0 "GPIOC_HWCFGR10,For GPIOA. B. C. D. E. F. G. H. I. J and GPIOK: For GPIOZ:" hexmask.long.byte 0x0 20.--23. 1. "OR_CFG,OR_CFG" hexmask.long.byte 0x0 16.--19. 1. "SEC_CFG,SEC_CFG" hexmask.long.byte 0x0 12.--15. 1. "LOCK_CFG,LOCK_CFG" hexmask.long.byte 0x0 8.--11. 1. "SPEED_CFG,SPEED_CFG" hexmask.long.byte 0x0 4.--7. 1. "AF_SIZE,AF_SIZE" hexmask.long.byte 0x0 0.--3. 1. "AHB_IOP,AHB_IOP" line.long 0x4 "GPIOC_HWCFGR9,For GPIOA. B. C. D. E. F. G. H. I. and GPIOJ: For GPIOK and GPIOZ:" hexmask.long.word 0x4 0.--15. 1. "EN_IO,EN_IO" line.long 0x8 "GPIOC_HWCFGR8,For GPIOA. B. C. D. E. F. G. H. I. and GPIOJ: For GPIOK and GPIOZ:" hexmask.long.byte 0x8 28.--31. 1. "AF_PRIO15,AF_PRIO15" hexmask.long.byte 0x8 24.--27. 1. "AF_PRIO14,AF_PRIO14" hexmask.long.byte 0x8 20.--23. 1. "AF_PRIO13,AF_PRIO13" hexmask.long.byte 0x8 16.--19. 1. "AF_PRIO12,AF_PRIO12" hexmask.long.byte 0x8 12.--15. 1. "AF_PRIO11,AF_PRIO11" hexmask.long.byte 0x8 8.--11. 1. "AF_PRIO10,AF_PRIO10" hexmask.long.byte 0x8 4.--7. 1. "AF_PRIO9,AF_PRIO9" newline hexmask.long.byte 0x8 0.--3. 1. "AF_PRIO8,AF_PRIO8" line.long 0xC "GPIOC_HWCFGR7,GPIO hardware configuration register 7" hexmask.long.byte 0xC 28.--31. 1. "AF_PRIO7,AF_PRIO7" hexmask.long.byte 0xC 24.--27. 1. "AF_PRIO6,AF_PRIO6" hexmask.long.byte 0xC 20.--23. 1. "AF_PRIO5,AF_PRIO5" hexmask.long.byte 0xC 16.--19. 1. "AF_PRIO4,AF_PRIO4" hexmask.long.byte 0xC 12.--15. 1. "AF_PRIO3,AF_PRIO3" hexmask.long.byte 0xC 8.--11. 1. "AF_PRIO2,AF_PRIO2" hexmask.long.byte 0xC 4.--7. 1. "AF_PRIO1,AF_PRIO1" newline hexmask.long.byte 0xC 0.--3. 1. "AF_PRIO0,AF_PRIO0" line.long 0x10 "GPIOC_HWCFGR6,GPIO hardware configuration register 6" hexmask.long 0x10 0.--31. 1. "MODER_RES,MODER_RES" line.long 0x14 "GPIOC_HWCFGR5,GPIO hardware configuration register 5" hexmask.long 0x14 0.--31. 1. "PUPDR_RES,PUPDR_RES" line.long 0x18 "GPIOC_HWCFGR4,GPIO hardware configuration register 4" hexmask.long 0x18 0.--31. 1. "OSPEED_RES,OSPEED_RES" line.long 0x1C "GPIOC_HWCFGR3,GPIO hardware configuration register 3" hexmask.long.word 0x1C 16.--31. 1. "OTYPER_RES,OTYPER_RES" hexmask.long.word 0x1C 0.--15. 1. "ODR_RES,ODR_RES" line.long 0x20 "GPIOC_HWCFGR2,GPIO hardware configuration register 2" hexmask.long 0x20 0.--31. 1. "AFRL_RES,AFRL_RES" line.long 0x24 "GPIOC_HWCFGR1,GPIO hardware configuration register 1" hexmask.long 0x24 0.--31. 1. "AFRH_RES,AFRH_RES" line.long 0x28 "GPIOC_HWCFGR0,GPIO hardware configuration register 0" hexmask.long.word 0x28 0.--15. 1. "OR_RES,OR_RES" line.long 0x2C "GPIOC_VERR,GPIO version register" hexmask.long.byte 0x2C 4.--7. 1. "MAJREV,MAJREV" hexmask.long.byte 0x2C 0.--3. 1. "MINREV,MINREV" line.long 0x30 "GPIOC_IPIDR,GPIO identification register" hexmask.long 0x30 0.--31. 1. "IPIDR,IPIDR" line.long 0x34 "GPIOC_SIDR,GPIO size identification register" hexmask.long 0x34 0.--31. 1. "SIDR,SIDR" tree.end endif sif (cpuis("STM32MP13*")) tree "GPIOD" base ad:0x50005000 group.long 0x0++0xF line.long 0x0 "GPIOD_MODER,GPIO port mode register" bitfld.long 0x0 30.--31. "MODER15,MODER15" "0,1,2,3" bitfld.long 0x0 28.--29. "MODER14,MODER14" "0,1,2,3" bitfld.long 0x0 26.--27. "MODER13,MODER13" "0,1,2,3" bitfld.long 0x0 24.--25. "MODER12,MODER12" "0,1,2,3" bitfld.long 0x0 22.--23. "MODER11,MODER11" "0,1,2,3" bitfld.long 0x0 20.--21. "MODER10,MODER10" "0,1,2,3" bitfld.long 0x0 18.--19. "MODER9,MODER9" "0,1,2,3" newline bitfld.long 0x0 16.--17. "MODER8,MODER8" "0,1,2,3" bitfld.long 0x0 14.--15. "MODER7,MODER7" "0,1,2,3" bitfld.long 0x0 12.--13. "MODER6,MODER6" "0,1,2,3" bitfld.long 0x0 10.--11. "MODER5,MODER5" "0,1,2,3" bitfld.long 0x0 8.--9. "MODER4,MODER4" "0,1,2,3" bitfld.long 0x0 6.--7. "MODER3,MODER3" "0,1,2,3" bitfld.long 0x0 4.--5. "MODER2,MODER2" "0,1,2,3" newline bitfld.long 0x0 2.--3. "MODER1,MODER1" "0,1,2,3" bitfld.long 0x0 0.--1. "MODER0,MODER0" "0,1,2,3" line.long 0x4 "GPIOD_OTYPER,GPIO port output type register" bitfld.long 0x4 15. "OT15,OT15" "0,1" bitfld.long 0x4 14. "OT14,OT14" "0,1" bitfld.long 0x4 13. "OT13,OT13" "0,1" bitfld.long 0x4 12. "OT12,OT12" "0,1" bitfld.long 0x4 11. "OT11,OT11" "0,1" bitfld.long 0x4 10. "OT10,OT10" "0,1" bitfld.long 0x4 9. "OT9,OT9" "0,1" newline bitfld.long 0x4 8. "OT8,OT8" "0,1" bitfld.long 0x4 7. "OT7,OT7" "0,1" bitfld.long 0x4 6. "OT6,OT6" "0,1" bitfld.long 0x4 5. "OT5,OT5" "0,1" bitfld.long 0x4 4. "OT4,OT4" "0,1" bitfld.long 0x4 3. "OT3,OT3" "0,1" bitfld.long 0x4 2. "OT2,OT2" "0,1" newline bitfld.long 0x4 1. "OT1,OT1" "0,1" bitfld.long 0x4 0. "OT0,OT0" "0,1" line.long 0x8 "GPIOD_OSPEEDR,GPIO port output speed register" bitfld.long 0x8 30.--31. "OSPEEDR15,OSPEEDR15" "0,1,2,3" bitfld.long 0x8 28.--29. "OSPEEDR14,OSPEEDR14" "0,1,2,3" bitfld.long 0x8 26.--27. "OSPEEDR13,OSPEEDR13" "0,1,2,3" bitfld.long 0x8 24.--25. "OSPEEDR12,OSPEEDR12" "0,1,2,3" bitfld.long 0x8 22.--23. "OSPEEDR11,OSPEEDR11" "0,1,2,3" bitfld.long 0x8 20.--21. "OSPEEDR10,OSPEEDR10" "0,1,2,3" bitfld.long 0x8 18.--19. "OSPEEDR9,OSPEEDR9" "0,1,2,3" newline bitfld.long 0x8 16.--17. "OSPEEDR8,OSPEEDR8" "0,1,2,3" bitfld.long 0x8 14.--15. "OSPEEDR7,OSPEEDR7" "0,1,2,3" bitfld.long 0x8 12.--13. "OSPEEDR6,OSPEEDR6" "0,1,2,3" bitfld.long 0x8 10.--11. "OSPEEDR5,OSPEEDR5" "0,1,2,3" bitfld.long 0x8 8.--9. "OSPEEDR4,OSPEEDR4" "0,1,2,3" bitfld.long 0x8 6.--7. "OSPEEDR3,OSPEEDR3" "0,1,2,3" bitfld.long 0x8 4.--5. "OSPEEDR2,OSPEEDR2" "0,1,2,3" newline bitfld.long 0x8 2.--3. "OSPEEDR1,OSPEEDR1" "0,1,2,3" bitfld.long 0x8 0.--1. "OSPEEDR0,OSPEEDR0" "0,1,2,3" line.long 0xC "GPIOD_PUPDR,GPIO port pull-up/pull-down register" bitfld.long 0xC 30.--31. "PUPDR15,PUPDR15" "0,1,2,3" bitfld.long 0xC 28.--29. "PUPDR14,PUPDR14" "0,1,2,3" bitfld.long 0xC 26.--27. "PUPDR13,PUPDR13" "0,1,2,3" bitfld.long 0xC 24.--25. "PUPDR12,PUPDR12" "0,1,2,3" bitfld.long 0xC 22.--23. "PUPDR11,PUPDR11" "0,1,2,3" bitfld.long 0xC 20.--21. "PUPDR10,PUPDR10" "0,1,2,3" bitfld.long 0xC 18.--19. "PUPDR9,PUPDR9" "0,1,2,3" newline bitfld.long 0xC 16.--17. "PUPDR8,PUPDR8" "0,1,2,3" bitfld.long 0xC 14.--15. "PUPDR7,PUPDR7" "0,1,2,3" bitfld.long 0xC 12.--13. "PUPDR6,PUPDR6" "0,1,2,3" bitfld.long 0xC 10.--11. "PUPDR5,PUPDR5" "0,1,2,3" bitfld.long 0xC 8.--9. "PUPDR4,PUPDR4" "0,1,2,3" bitfld.long 0xC 6.--7. "PUPDR3,PUPDR3" "0,1,2,3" bitfld.long 0xC 4.--5. "PUPDR2,PUPDR2" "0,1,2,3" newline bitfld.long 0xC 2.--3. "PUPDR1,PUPDR1" "0,1,2,3" bitfld.long 0xC 0.--1. "PUPDR0,PUPDR0" "0,1,2,3" rgroup.long 0x10++0x3 line.long 0x0 "GPIOD_IDR,GPIO port input data register" bitfld.long 0x0 15. "IDR15,IDR15" "0,1" bitfld.long 0x0 14. "IDR14,IDR14" "0,1" bitfld.long 0x0 13. "IDR13,IDR13" "0,1" bitfld.long 0x0 12. "IDR12,IDR12" "0,1" bitfld.long 0x0 11. "IDR11,IDR11" "0,1" bitfld.long 0x0 10. "IDR10,IDR10" "0,1" bitfld.long 0x0 9. "IDR9,IDR9" "0,1" newline bitfld.long 0x0 8. "IDR8,IDR8" "0,1" bitfld.long 0x0 7. "IDR7,IDR7" "0,1" bitfld.long 0x0 6. "IDR6,IDR6" "0,1" bitfld.long 0x0 5. "IDR5,IDR5" "0,1" bitfld.long 0x0 4. "IDR4,IDR4" "0,1" bitfld.long 0x0 3. "IDR3,IDR3" "0,1" bitfld.long 0x0 2. "IDR2,IDR2" "0,1" newline bitfld.long 0x0 1. "IDR1,IDR1" "0,1" bitfld.long 0x0 0. "IDR0,IDR0" "0,1" group.long 0x14++0x3 line.long 0x0 "GPIOD_ODR,GPIO port output data register" bitfld.long 0x0 15. "ODR15,ODR15" "0,1" bitfld.long 0x0 14. "ODR14,ODR14" "0,1" bitfld.long 0x0 13. "ODR13,ODR13" "0,1" bitfld.long 0x0 12. "ODR12,ODR12" "0,1" bitfld.long 0x0 11. "ODR11,ODR11" "0,1" bitfld.long 0x0 10. "ODR10,ODR10" "0,1" bitfld.long 0x0 9. "ODR9,ODR9" "0,1" newline bitfld.long 0x0 8. "ODR8,ODR8" "0,1" bitfld.long 0x0 7. "ODR7,ODR7" "0,1" bitfld.long 0x0 6. "ODR6,ODR6" "0,1" bitfld.long 0x0 5. "ODR5,ODR5" "0,1" bitfld.long 0x0 4. "ODR4,ODR4" "0,1" bitfld.long 0x0 3. "ODR3,ODR3" "0,1" bitfld.long 0x0 2. "ODR2,ODR2" "0,1" newline bitfld.long 0x0 1. "ODR1,ODR1" "0,1" bitfld.long 0x0 0. "ODR0,ODR0" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "GPIOD_BSRR,GPIO port bit set/reset register" bitfld.long 0x0 31. "BR15,BR15" "0,1" bitfld.long 0x0 30. "BR14,BR14" "0,1" bitfld.long 0x0 29. "BR13,BR13" "0,1" bitfld.long 0x0 28. "BR12,BR12" "0,1" bitfld.long 0x0 27. "BR11,BR11" "0,1" bitfld.long 0x0 26. "BR10,BR10" "0,1" bitfld.long 0x0 25. "BR9,BR9" "0,1" newline bitfld.long 0x0 24. "BR8,BR8" "0,1" bitfld.long 0x0 23. "BR7,BR7" "0,1" bitfld.long 0x0 22. "BR6,BR6" "0,1" bitfld.long 0x0 21. "BR5,BR5" "0,1" bitfld.long 0x0 20. "BR4,BR4" "0,1" bitfld.long 0x0 19. "BR3,BR3" "0,1" bitfld.long 0x0 18. "BR2,BR2" "0,1" newline bitfld.long 0x0 17. "BR1,BR1" "0,1" bitfld.long 0x0 16. "BR0,BR0" "0,1" bitfld.long 0x0 15. "BS15,BS15" "0,1" bitfld.long 0x0 14. "BS14,BS14" "0,1" bitfld.long 0x0 13. "BS13,BS13" "0,1" bitfld.long 0x0 12. "BS12,BS12" "0,1" bitfld.long 0x0 11. "BS11,BS11" "0,1" newline bitfld.long 0x0 10. "BS10,BS10" "0,1" bitfld.long 0x0 9. "BS9,BS9" "0,1" bitfld.long 0x0 8. "BS8,BS8" "0,1" bitfld.long 0x0 7. "BS7,BS7" "0,1" bitfld.long 0x0 6. "BS6,BS6" "0,1" bitfld.long 0x0 5. "BS5,BS5" "0,1" bitfld.long 0x0 4. "BS4,BS4" "0,1" newline bitfld.long 0x0 3. "BS3,BS3" "0,1" bitfld.long 0x0 2. "BS2,BS2" "0,1" bitfld.long 0x0 1. "BS1,BS1" "0,1" bitfld.long 0x0 0. "BS0,BS0" "0,1" group.long 0x1C++0xB line.long 0x0 "GPIOD_LCKR,This register is used to lock the configuration of the port bits when a correct write sequence is applied to bit 16 (LCKK). The value of bits [15:0] is used to lock the configuration of the GPIO. During the write sequence. the value of.." bitfld.long 0x0 16. "LCKK,LCKK" "0,1" bitfld.long 0x0 15. "LCK15,LCK15" "0,1" bitfld.long 0x0 14. "LCK14,LCK14" "0,1" bitfld.long 0x0 13. "LCK13,LCK13" "0,1" bitfld.long 0x0 12. "LCK12,LCK12" "0,1" bitfld.long 0x0 11. "LCK11,LCK11" "0,1" bitfld.long 0x0 10. "LCK10,LCK10" "0,1" newline bitfld.long 0x0 9. "LCK9,LCK9" "0,1" bitfld.long 0x0 8. "LCK8,LCK8" "0,1" bitfld.long 0x0 7. "LCK7,LCK7" "0,1" bitfld.long 0x0 6. "LCK6,LCK6" "0,1" bitfld.long 0x0 5. "LCK5,LCK5" "0,1" bitfld.long 0x0 4. "LCK4,LCK4" "0,1" bitfld.long 0x0 3. "LCK3,LCK3" "0,1" newline bitfld.long 0x0 2. "LCK2,LCK2" "0,1" bitfld.long 0x0 1. "LCK1,LCK1" "0,1" bitfld.long 0x0 0. "LCK0,LCK0" "0,1" line.long 0x4 "GPIOD_AFRL,GPIO alternate function low register" hexmask.long.byte 0x4 28.--31. 1. "AFR7,AFR7" hexmask.long.byte 0x4 24.--27. 1. "AFR6,AFR6" hexmask.long.byte 0x4 20.--23. 1. "AFR5,AFR5" hexmask.long.byte 0x4 16.--19. 1. "AFR4,AFR4" hexmask.long.byte 0x4 12.--15. 1. "AFR3,AFR3" hexmask.long.byte 0x4 8.--11. 1. "AFR2,AFR2" hexmask.long.byte 0x4 4.--7. 1. "AFR1,AFR1" newline hexmask.long.byte 0x4 0.--3. 1. "AFR0,AFR0" line.long 0x8 "GPIOD_AFRH,GPIO alternate function high register" hexmask.long.byte 0x8 28.--31. 1. "AFR15,AFR15" hexmask.long.byte 0x8 24.--27. 1. "AFR14,AFR14" hexmask.long.byte 0x8 20.--23. 1. "AFR13,AFR13" hexmask.long.byte 0x8 16.--19. 1. "AFR12,AFR12" hexmask.long.byte 0x8 12.--15. 1. "AFR11,AFR11" hexmask.long.byte 0x8 8.--11. 1. "AFR10,AFR10" hexmask.long.byte 0x8 4.--7. 1. "AFR9,AFR9" newline hexmask.long.byte 0x8 0.--3. 1. "AFR8,AFR8" wgroup.long 0x28++0x3 line.long 0x0 "GPIOD_BRR,GPIO port bit reset register" bitfld.long 0x0 15. "BR15,BR15" "0,1" bitfld.long 0x0 14. "BR14,BR14" "0,1" bitfld.long 0x0 13. "BR13,BR13" "0,1" bitfld.long 0x0 12. "BR12,BR12" "0,1" bitfld.long 0x0 11. "BR11,BR11" "0,1" bitfld.long 0x0 10. "BR10,BR10" "0,1" bitfld.long 0x0 9. "BR9,BR9" "0,1" newline bitfld.long 0x0 8. "BR8,BR8" "0,1" bitfld.long 0x0 7. "BR7,BR7" "0,1" bitfld.long 0x0 6. "BR6,BR6" "0,1" bitfld.long 0x0 5. "BR5,BR5" "0,1" bitfld.long 0x0 4. "BR4,BR4" "0,1" bitfld.long 0x0 3. "BR3,BR3" "0,1" bitfld.long 0x0 2. "BR2,BR2" "0,1" newline bitfld.long 0x0 1. "BR1,BR1" "0,1" bitfld.long 0x0 0. "BR0,BR0" "0,1" group.long 0x30++0x3 line.long 0x0 "GPIOD_SECCFGR,GPIO secure configuration register" bitfld.long 0x0 15. "SEC15,SEC15" "0,1" bitfld.long 0x0 14. "SEC14,SEC14" "0,1" bitfld.long 0x0 13. "SEC13,SEC13" "0,1" bitfld.long 0x0 12. "SEC12,SEC12" "0,1" bitfld.long 0x0 11. "SEC11,SEC11" "0,1" bitfld.long 0x0 10. "SEC10,SEC10" "0,1" bitfld.long 0x0 9. "SEC9,SEC9" "0,1" newline bitfld.long 0x0 8. "SEC8,SEC8" "0,1" bitfld.long 0x0 7. "SEC7,SEC7" "0,1" bitfld.long 0x0 6. "SEC6,SEC6" "0,1" bitfld.long 0x0 5. "SEC5,SEC5" "0,1" bitfld.long 0x0 4. "SEC4,SEC4" "0,1" bitfld.long 0x0 3. "SEC3,SEC3" "0,1" bitfld.long 0x0 2. "SEC2,SEC2" "0,1" newline bitfld.long 0x0 1. "SEC1,SEC1" "0,1" bitfld.long 0x0 0. "SEC0,SEC0" "0,1" rgroup.long 0x3C8++0x37 line.long 0x0 "GPIOD_HWCFGR10,For GPIOA. B. C. D. E. F. G. H. I. J and GPIOK: For GPIOZ:" hexmask.long.byte 0x0 20.--23. 1. "OR_CFG,OR_CFG" hexmask.long.byte 0x0 16.--19. 1. "SEC_CFG,SEC_CFG" hexmask.long.byte 0x0 12.--15. 1. "LOCK_CFG,LOCK_CFG" hexmask.long.byte 0x0 8.--11. 1. "SPEED_CFG,SPEED_CFG" hexmask.long.byte 0x0 4.--7. 1. "AF_SIZE,AF_SIZE" hexmask.long.byte 0x0 0.--3. 1. "AHB_IOP,AHB_IOP" line.long 0x4 "GPIOD_HWCFGR9,For GPIOA. B. C. D. E. F. G. H. I. and GPIOJ: For GPIOK and GPIOZ:" hexmask.long.word 0x4 0.--15. 1. "EN_IO,EN_IO" line.long 0x8 "GPIOD_HWCFGR8,For GPIOA. B. C. D. E. F. G. H. I. and GPIOJ: For GPIOK and GPIOZ:" hexmask.long.byte 0x8 28.--31. 1. "AF_PRIO15,AF_PRIO15" hexmask.long.byte 0x8 24.--27. 1. "AF_PRIO14,AF_PRIO14" hexmask.long.byte 0x8 20.--23. 1. "AF_PRIO13,AF_PRIO13" hexmask.long.byte 0x8 16.--19. 1. "AF_PRIO12,AF_PRIO12" hexmask.long.byte 0x8 12.--15. 1. "AF_PRIO11,AF_PRIO11" hexmask.long.byte 0x8 8.--11. 1. "AF_PRIO10,AF_PRIO10" hexmask.long.byte 0x8 4.--7. 1. "AF_PRIO9,AF_PRIO9" newline hexmask.long.byte 0x8 0.--3. 1. "AF_PRIO8,AF_PRIO8" line.long 0xC "GPIOD_HWCFGR7,GPIO hardware configuration register 7" hexmask.long.byte 0xC 28.--31. 1. "AF_PRIO7,AF_PRIO7" hexmask.long.byte 0xC 24.--27. 1. "AF_PRIO6,AF_PRIO6" hexmask.long.byte 0xC 20.--23. 1. "AF_PRIO5,AF_PRIO5" hexmask.long.byte 0xC 16.--19. 1. "AF_PRIO4,AF_PRIO4" hexmask.long.byte 0xC 12.--15. 1. "AF_PRIO3,AF_PRIO3" hexmask.long.byte 0xC 8.--11. 1. "AF_PRIO2,AF_PRIO2" hexmask.long.byte 0xC 4.--7. 1. "AF_PRIO1,AF_PRIO1" newline hexmask.long.byte 0xC 0.--3. 1. "AF_PRIO0,AF_PRIO0" line.long 0x10 "GPIOD_HWCFGR6,GPIO hardware configuration register 6" hexmask.long 0x10 0.--31. 1. "MODER_RES,MODER_RES" line.long 0x14 "GPIOD_HWCFGR5,GPIO hardware configuration register 5" hexmask.long 0x14 0.--31. 1. "PUPDR_RES,PUPDR_RES" line.long 0x18 "GPIOD_HWCFGR4,GPIO hardware configuration register 4" hexmask.long 0x18 0.--31. 1. "OSPEED_RES,OSPEED_RES" line.long 0x1C "GPIOD_HWCFGR3,GPIO hardware configuration register 3" hexmask.long.word 0x1C 16.--31. 1. "OTYPER_RES,OTYPER_RES" hexmask.long.word 0x1C 0.--15. 1. "ODR_RES,ODR_RES" line.long 0x20 "GPIOD_HWCFGR2,GPIO hardware configuration register 2" hexmask.long 0x20 0.--31. 1. "AFRL_RES,AFRL_RES" line.long 0x24 "GPIOD_HWCFGR1,GPIO hardware configuration register 1" hexmask.long 0x24 0.--31. 1. "AFRH_RES,AFRH_RES" line.long 0x28 "GPIOD_HWCFGR0,GPIO hardware configuration register 0" hexmask.long.word 0x28 0.--15. 1. "OR_RES,OR_RES" line.long 0x2C "GPIOD_VERR,GPIO version register" hexmask.long.byte 0x2C 4.--7. 1. "MAJREV,MAJREV" hexmask.long.byte 0x2C 0.--3. 1. "MINREV,MINREV" line.long 0x30 "GPIOD_IPIDR,GPIO identification register" hexmask.long 0x30 0.--31. 1. "IPIDR,IPIDR" line.long 0x34 "GPIOD_SIDR,GPIO size identification register" hexmask.long 0x34 0.--31. 1. "SIDR,SIDR" tree.end endif sif (cpuis("STM32MP13*")) tree "GPIOE" base ad:0x50006000 group.long 0x0++0xF line.long 0x0 "GPIOE_MODER,GPIO port mode register" bitfld.long 0x0 30.--31. "MODER15,MODER15" "0,1,2,3" bitfld.long 0x0 28.--29. "MODER14,MODER14" "0,1,2,3" bitfld.long 0x0 26.--27. "MODER13,MODER13" "0,1,2,3" bitfld.long 0x0 24.--25. "MODER12,MODER12" "0,1,2,3" bitfld.long 0x0 22.--23. "MODER11,MODER11" "0,1,2,3" bitfld.long 0x0 20.--21. "MODER10,MODER10" "0,1,2,3" bitfld.long 0x0 18.--19. "MODER9,MODER9" "0,1,2,3" newline bitfld.long 0x0 16.--17. "MODER8,MODER8" "0,1,2,3" bitfld.long 0x0 14.--15. "MODER7,MODER7" "0,1,2,3" bitfld.long 0x0 12.--13. "MODER6,MODER6" "0,1,2,3" bitfld.long 0x0 10.--11. "MODER5,MODER5" "0,1,2,3" bitfld.long 0x0 8.--9. "MODER4,MODER4" "0,1,2,3" bitfld.long 0x0 6.--7. "MODER3,MODER3" "0,1,2,3" bitfld.long 0x0 4.--5. "MODER2,MODER2" "0,1,2,3" newline bitfld.long 0x0 2.--3. "MODER1,MODER1" "0,1,2,3" bitfld.long 0x0 0.--1. "MODER0,MODER0" "0,1,2,3" line.long 0x4 "GPIOE_OTYPER,GPIO port output type register" bitfld.long 0x4 15. "OT15,OT15" "0,1" bitfld.long 0x4 14. "OT14,OT14" "0,1" bitfld.long 0x4 13. "OT13,OT13" "0,1" bitfld.long 0x4 12. "OT12,OT12" "0,1" bitfld.long 0x4 11. "OT11,OT11" "0,1" bitfld.long 0x4 10. "OT10,OT10" "0,1" bitfld.long 0x4 9. "OT9,OT9" "0,1" newline bitfld.long 0x4 8. "OT8,OT8" "0,1" bitfld.long 0x4 7. "OT7,OT7" "0,1" bitfld.long 0x4 6. "OT6,OT6" "0,1" bitfld.long 0x4 5. "OT5,OT5" "0,1" bitfld.long 0x4 4. "OT4,OT4" "0,1" bitfld.long 0x4 3. "OT3,OT3" "0,1" bitfld.long 0x4 2. "OT2,OT2" "0,1" newline bitfld.long 0x4 1. "OT1,OT1" "0,1" bitfld.long 0x4 0. "OT0,OT0" "0,1" line.long 0x8 "GPIOE_OSPEEDR,GPIO port output speed register" bitfld.long 0x8 30.--31. "OSPEEDR15,OSPEEDR15" "0,1,2,3" bitfld.long 0x8 28.--29. "OSPEEDR14,OSPEEDR14" "0,1,2,3" bitfld.long 0x8 26.--27. "OSPEEDR13,OSPEEDR13" "0,1,2,3" bitfld.long 0x8 24.--25. "OSPEEDR12,OSPEEDR12" "0,1,2,3" bitfld.long 0x8 22.--23. "OSPEEDR11,OSPEEDR11" "0,1,2,3" bitfld.long 0x8 20.--21. "OSPEEDR10,OSPEEDR10" "0,1,2,3" bitfld.long 0x8 18.--19. "OSPEEDR9,OSPEEDR9" "0,1,2,3" newline bitfld.long 0x8 16.--17. "OSPEEDR8,OSPEEDR8" "0,1,2,3" bitfld.long 0x8 14.--15. "OSPEEDR7,OSPEEDR7" "0,1,2,3" bitfld.long 0x8 12.--13. "OSPEEDR6,OSPEEDR6" "0,1,2,3" bitfld.long 0x8 10.--11. "OSPEEDR5,OSPEEDR5" "0,1,2,3" bitfld.long 0x8 8.--9. "OSPEEDR4,OSPEEDR4" "0,1,2,3" bitfld.long 0x8 6.--7. "OSPEEDR3,OSPEEDR3" "0,1,2,3" bitfld.long 0x8 4.--5. "OSPEEDR2,OSPEEDR2" "0,1,2,3" newline bitfld.long 0x8 2.--3. "OSPEEDR1,OSPEEDR1" "0,1,2,3" bitfld.long 0x8 0.--1. "OSPEEDR0,OSPEEDR0" "0,1,2,3" line.long 0xC "GPIOE_PUPDR,GPIO port pull-up/pull-down register" bitfld.long 0xC 30.--31. "PUPDR15,PUPDR15" "0,1,2,3" bitfld.long 0xC 28.--29. "PUPDR14,PUPDR14" "0,1,2,3" bitfld.long 0xC 26.--27. "PUPDR13,PUPDR13" "0,1,2,3" bitfld.long 0xC 24.--25. "PUPDR12,PUPDR12" "0,1,2,3" bitfld.long 0xC 22.--23. "PUPDR11,PUPDR11" "0,1,2,3" bitfld.long 0xC 20.--21. "PUPDR10,PUPDR10" "0,1,2,3" bitfld.long 0xC 18.--19. "PUPDR9,PUPDR9" "0,1,2,3" newline bitfld.long 0xC 16.--17. "PUPDR8,PUPDR8" "0,1,2,3" bitfld.long 0xC 14.--15. "PUPDR7,PUPDR7" "0,1,2,3" bitfld.long 0xC 12.--13. "PUPDR6,PUPDR6" "0,1,2,3" bitfld.long 0xC 10.--11. "PUPDR5,PUPDR5" "0,1,2,3" bitfld.long 0xC 8.--9. "PUPDR4,PUPDR4" "0,1,2,3" bitfld.long 0xC 6.--7. "PUPDR3,PUPDR3" "0,1,2,3" bitfld.long 0xC 4.--5. "PUPDR2,PUPDR2" "0,1,2,3" newline bitfld.long 0xC 2.--3. "PUPDR1,PUPDR1" "0,1,2,3" bitfld.long 0xC 0.--1. "PUPDR0,PUPDR0" "0,1,2,3" rgroup.long 0x10++0x3 line.long 0x0 "GPIOE_IDR,GPIO port input data register" bitfld.long 0x0 15. "IDR15,IDR15" "0,1" bitfld.long 0x0 14. "IDR14,IDR14" "0,1" bitfld.long 0x0 13. "IDR13,IDR13" "0,1" bitfld.long 0x0 12. "IDR12,IDR12" "0,1" bitfld.long 0x0 11. "IDR11,IDR11" "0,1" bitfld.long 0x0 10. "IDR10,IDR10" "0,1" bitfld.long 0x0 9. "IDR9,IDR9" "0,1" newline bitfld.long 0x0 8. "IDR8,IDR8" "0,1" bitfld.long 0x0 7. "IDR7,IDR7" "0,1" bitfld.long 0x0 6. "IDR6,IDR6" "0,1" bitfld.long 0x0 5. "IDR5,IDR5" "0,1" bitfld.long 0x0 4. "IDR4,IDR4" "0,1" bitfld.long 0x0 3. "IDR3,IDR3" "0,1" bitfld.long 0x0 2. "IDR2,IDR2" "0,1" newline bitfld.long 0x0 1. "IDR1,IDR1" "0,1" bitfld.long 0x0 0. "IDR0,IDR0" "0,1" group.long 0x14++0x3 line.long 0x0 "GPIOE_ODR,GPIO port output data register" bitfld.long 0x0 15. "ODR15,ODR15" "0,1" bitfld.long 0x0 14. "ODR14,ODR14" "0,1" bitfld.long 0x0 13. "ODR13,ODR13" "0,1" bitfld.long 0x0 12. "ODR12,ODR12" "0,1" bitfld.long 0x0 11. "ODR11,ODR11" "0,1" bitfld.long 0x0 10. "ODR10,ODR10" "0,1" bitfld.long 0x0 9. "ODR9,ODR9" "0,1" newline bitfld.long 0x0 8. "ODR8,ODR8" "0,1" bitfld.long 0x0 7. "ODR7,ODR7" "0,1" bitfld.long 0x0 6. "ODR6,ODR6" "0,1" bitfld.long 0x0 5. "ODR5,ODR5" "0,1" bitfld.long 0x0 4. "ODR4,ODR4" "0,1" bitfld.long 0x0 3. "ODR3,ODR3" "0,1" bitfld.long 0x0 2. "ODR2,ODR2" "0,1" newline bitfld.long 0x0 1. "ODR1,ODR1" "0,1" bitfld.long 0x0 0. "ODR0,ODR0" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "GPIOE_BSRR,GPIO port bit set/reset register" bitfld.long 0x0 31. "BR15,BR15" "0,1" bitfld.long 0x0 30. "BR14,BR14" "0,1" bitfld.long 0x0 29. "BR13,BR13" "0,1" bitfld.long 0x0 28. "BR12,BR12" "0,1" bitfld.long 0x0 27. "BR11,BR11" "0,1" bitfld.long 0x0 26. "BR10,BR10" "0,1" bitfld.long 0x0 25. "BR9,BR9" "0,1" newline bitfld.long 0x0 24. "BR8,BR8" "0,1" bitfld.long 0x0 23. "BR7,BR7" "0,1" bitfld.long 0x0 22. "BR6,BR6" "0,1" bitfld.long 0x0 21. "BR5,BR5" "0,1" bitfld.long 0x0 20. "BR4,BR4" "0,1" bitfld.long 0x0 19. "BR3,BR3" "0,1" bitfld.long 0x0 18. "BR2,BR2" "0,1" newline bitfld.long 0x0 17. "BR1,BR1" "0,1" bitfld.long 0x0 16. "BR0,BR0" "0,1" bitfld.long 0x0 15. "BS15,BS15" "0,1" bitfld.long 0x0 14. "BS14,BS14" "0,1" bitfld.long 0x0 13. "BS13,BS13" "0,1" bitfld.long 0x0 12. "BS12,BS12" "0,1" bitfld.long 0x0 11. "BS11,BS11" "0,1" newline bitfld.long 0x0 10. "BS10,BS10" "0,1" bitfld.long 0x0 9. "BS9,BS9" "0,1" bitfld.long 0x0 8. "BS8,BS8" "0,1" bitfld.long 0x0 7. "BS7,BS7" "0,1" bitfld.long 0x0 6. "BS6,BS6" "0,1" bitfld.long 0x0 5. "BS5,BS5" "0,1" bitfld.long 0x0 4. "BS4,BS4" "0,1" newline bitfld.long 0x0 3. "BS3,BS3" "0,1" bitfld.long 0x0 2. "BS2,BS2" "0,1" bitfld.long 0x0 1. "BS1,BS1" "0,1" bitfld.long 0x0 0. "BS0,BS0" "0,1" group.long 0x1C++0xB line.long 0x0 "GPIOE_LCKR,This register is used to lock the configuration of the port bits when a correct write sequence is applied to bit 16 (LCKK). The value of bits [15:0] is used to lock the configuration of the GPIO. During the write sequence. the value of.." bitfld.long 0x0 16. "LCKK,LCKK" "0,1" bitfld.long 0x0 15. "LCK15,LCK15" "0,1" bitfld.long 0x0 14. "LCK14,LCK14" "0,1" bitfld.long 0x0 13. "LCK13,LCK13" "0,1" bitfld.long 0x0 12. "LCK12,LCK12" "0,1" bitfld.long 0x0 11. "LCK11,LCK11" "0,1" bitfld.long 0x0 10. "LCK10,LCK10" "0,1" newline bitfld.long 0x0 9. "LCK9,LCK9" "0,1" bitfld.long 0x0 8. "LCK8,LCK8" "0,1" bitfld.long 0x0 7. "LCK7,LCK7" "0,1" bitfld.long 0x0 6. "LCK6,LCK6" "0,1" bitfld.long 0x0 5. "LCK5,LCK5" "0,1" bitfld.long 0x0 4. "LCK4,LCK4" "0,1" bitfld.long 0x0 3. "LCK3,LCK3" "0,1" newline bitfld.long 0x0 2. "LCK2,LCK2" "0,1" bitfld.long 0x0 1. "LCK1,LCK1" "0,1" bitfld.long 0x0 0. "LCK0,LCK0" "0,1" line.long 0x4 "GPIOE_AFRL,GPIO alternate function low register" hexmask.long.byte 0x4 28.--31. 1. "AFR7,AFR7" hexmask.long.byte 0x4 24.--27. 1. "AFR6,AFR6" hexmask.long.byte 0x4 20.--23. 1. "AFR5,AFR5" hexmask.long.byte 0x4 16.--19. 1. "AFR4,AFR4" hexmask.long.byte 0x4 12.--15. 1. "AFR3,AFR3" hexmask.long.byte 0x4 8.--11. 1. "AFR2,AFR2" hexmask.long.byte 0x4 4.--7. 1. "AFR1,AFR1" newline hexmask.long.byte 0x4 0.--3. 1. "AFR0,AFR0" line.long 0x8 "GPIOE_AFRH,GPIO alternate function high register" hexmask.long.byte 0x8 28.--31. 1. "AFR15,AFR15" hexmask.long.byte 0x8 24.--27. 1. "AFR14,AFR14" hexmask.long.byte 0x8 20.--23. 1. "AFR13,AFR13" hexmask.long.byte 0x8 16.--19. 1. "AFR12,AFR12" hexmask.long.byte 0x8 12.--15. 1. "AFR11,AFR11" hexmask.long.byte 0x8 8.--11. 1. "AFR10,AFR10" hexmask.long.byte 0x8 4.--7. 1. "AFR9,AFR9" newline hexmask.long.byte 0x8 0.--3. 1. "AFR8,AFR8" wgroup.long 0x28++0x3 line.long 0x0 "GPIOE_BRR,GPIO port bit reset register" bitfld.long 0x0 15. "BR15,BR15" "0,1" bitfld.long 0x0 14. "BR14,BR14" "0,1" bitfld.long 0x0 13. "BR13,BR13" "0,1" bitfld.long 0x0 12. "BR12,BR12" "0,1" bitfld.long 0x0 11. "BR11,BR11" "0,1" bitfld.long 0x0 10. "BR10,BR10" "0,1" bitfld.long 0x0 9. "BR9,BR9" "0,1" newline bitfld.long 0x0 8. "BR8,BR8" "0,1" bitfld.long 0x0 7. "BR7,BR7" "0,1" bitfld.long 0x0 6. "BR6,BR6" "0,1" bitfld.long 0x0 5. "BR5,BR5" "0,1" bitfld.long 0x0 4. "BR4,BR4" "0,1" bitfld.long 0x0 3. "BR3,BR3" "0,1" bitfld.long 0x0 2. "BR2,BR2" "0,1" newline bitfld.long 0x0 1. "BR1,BR1" "0,1" bitfld.long 0x0 0. "BR0,BR0" "0,1" group.long 0x30++0x3 line.long 0x0 "GPIOE_SECCFGR,GPIO secure configuration register" bitfld.long 0x0 15. "SEC15,SEC15" "0,1" bitfld.long 0x0 14. "SEC14,SEC14" "0,1" bitfld.long 0x0 13. "SEC13,SEC13" "0,1" bitfld.long 0x0 12. "SEC12,SEC12" "0,1" bitfld.long 0x0 11. "SEC11,SEC11" "0,1" bitfld.long 0x0 10. "SEC10,SEC10" "0,1" bitfld.long 0x0 9. "SEC9,SEC9" "0,1" newline bitfld.long 0x0 8. "SEC8,SEC8" "0,1" bitfld.long 0x0 7. "SEC7,SEC7" "0,1" bitfld.long 0x0 6. "SEC6,SEC6" "0,1" bitfld.long 0x0 5. "SEC5,SEC5" "0,1" bitfld.long 0x0 4. "SEC4,SEC4" "0,1" bitfld.long 0x0 3. "SEC3,SEC3" "0,1" bitfld.long 0x0 2. "SEC2,SEC2" "0,1" newline bitfld.long 0x0 1. "SEC1,SEC1" "0,1" bitfld.long 0x0 0. "SEC0,SEC0" "0,1" rgroup.long 0x3C8++0x37 line.long 0x0 "GPIOE_HWCFGR10,For GPIOA. B. C. D. E. F. G. H. I. J and GPIOK: For GPIOZ:" hexmask.long.byte 0x0 20.--23. 1. "OR_CFG,OR_CFG" hexmask.long.byte 0x0 16.--19. 1. "SEC_CFG,SEC_CFG" hexmask.long.byte 0x0 12.--15. 1. "LOCK_CFG,LOCK_CFG" hexmask.long.byte 0x0 8.--11. 1. "SPEED_CFG,SPEED_CFG" hexmask.long.byte 0x0 4.--7. 1. "AF_SIZE,AF_SIZE" hexmask.long.byte 0x0 0.--3. 1. "AHB_IOP,AHB_IOP" line.long 0x4 "GPIOE_HWCFGR9,For GPIOA. B. C. D. E. F. G. H. I. and GPIOJ: For GPIOK and GPIOZ:" hexmask.long.word 0x4 0.--15. 1. "EN_IO,EN_IO" line.long 0x8 "GPIOE_HWCFGR8,For GPIOA. B. C. D. E. F. G. H. I. and GPIOJ: For GPIOK and GPIOZ:" hexmask.long.byte 0x8 28.--31. 1. "AF_PRIO15,AF_PRIO15" hexmask.long.byte 0x8 24.--27. 1. "AF_PRIO14,AF_PRIO14" hexmask.long.byte 0x8 20.--23. 1. "AF_PRIO13,AF_PRIO13" hexmask.long.byte 0x8 16.--19. 1. "AF_PRIO12,AF_PRIO12" hexmask.long.byte 0x8 12.--15. 1. "AF_PRIO11,AF_PRIO11" hexmask.long.byte 0x8 8.--11. 1. "AF_PRIO10,AF_PRIO10" hexmask.long.byte 0x8 4.--7. 1. "AF_PRIO9,AF_PRIO9" newline hexmask.long.byte 0x8 0.--3. 1. "AF_PRIO8,AF_PRIO8" line.long 0xC "GPIOE_HWCFGR7,GPIO hardware configuration register 7" hexmask.long.byte 0xC 28.--31. 1. "AF_PRIO7,AF_PRIO7" hexmask.long.byte 0xC 24.--27. 1. "AF_PRIO6,AF_PRIO6" hexmask.long.byte 0xC 20.--23. 1. "AF_PRIO5,AF_PRIO5" hexmask.long.byte 0xC 16.--19. 1. "AF_PRIO4,AF_PRIO4" hexmask.long.byte 0xC 12.--15. 1. "AF_PRIO3,AF_PRIO3" hexmask.long.byte 0xC 8.--11. 1. "AF_PRIO2,AF_PRIO2" hexmask.long.byte 0xC 4.--7. 1. "AF_PRIO1,AF_PRIO1" newline hexmask.long.byte 0xC 0.--3. 1. "AF_PRIO0,AF_PRIO0" line.long 0x10 "GPIOE_HWCFGR6,GPIO hardware configuration register 6" hexmask.long 0x10 0.--31. 1. "MODER_RES,MODER_RES" line.long 0x14 "GPIOE_HWCFGR5,GPIO hardware configuration register 5" hexmask.long 0x14 0.--31. 1. "PUPDR_RES,PUPDR_RES" line.long 0x18 "GPIOE_HWCFGR4,GPIO hardware configuration register 4" hexmask.long 0x18 0.--31. 1. "OSPEED_RES,OSPEED_RES" line.long 0x1C "GPIOE_HWCFGR3,GPIO hardware configuration register 3" hexmask.long.word 0x1C 16.--31. 1. "OTYPER_RES,OTYPER_RES" hexmask.long.word 0x1C 0.--15. 1. "ODR_RES,ODR_RES" line.long 0x20 "GPIOE_HWCFGR2,GPIO hardware configuration register 2" hexmask.long 0x20 0.--31. 1. "AFRL_RES,AFRL_RES" line.long 0x24 "GPIOE_HWCFGR1,GPIO hardware configuration register 1" hexmask.long 0x24 0.--31. 1. "AFRH_RES,AFRH_RES" line.long 0x28 "GPIOE_HWCFGR0,GPIO hardware configuration register 0" hexmask.long.word 0x28 0.--15. 1. "OR_RES,OR_RES" line.long 0x2C "GPIOE_VERR,GPIO version register" hexmask.long.byte 0x2C 4.--7. 1. "MAJREV,MAJREV" hexmask.long.byte 0x2C 0.--3. 1. "MINREV,MINREV" line.long 0x30 "GPIOE_IPIDR,GPIO identification register" hexmask.long 0x30 0.--31. 1. "IPIDR,IPIDR" line.long 0x34 "GPIOE_SIDR,GPIO size identification register" hexmask.long 0x34 0.--31. 1. "SIDR,SIDR" tree.end endif sif (cpuis("STM32MP13*")) tree "GPIOF" base ad:0x50007000 group.long 0x0++0xF line.long 0x0 "GPIOF_MODER,GPIO port mode register" bitfld.long 0x0 30.--31. "MODER15,MODER15" "0,1,2,3" bitfld.long 0x0 28.--29. "MODER14,MODER14" "0,1,2,3" bitfld.long 0x0 26.--27. "MODER13,MODER13" "0,1,2,3" bitfld.long 0x0 24.--25. "MODER12,MODER12" "0,1,2,3" bitfld.long 0x0 22.--23. "MODER11,MODER11" "0,1,2,3" bitfld.long 0x0 20.--21. "MODER10,MODER10" "0,1,2,3" bitfld.long 0x0 18.--19. "MODER9,MODER9" "0,1,2,3" newline bitfld.long 0x0 16.--17. "MODER8,MODER8" "0,1,2,3" bitfld.long 0x0 14.--15. "MODER7,MODER7" "0,1,2,3" bitfld.long 0x0 12.--13. "MODER6,MODER6" "0,1,2,3" bitfld.long 0x0 10.--11. "MODER5,MODER5" "0,1,2,3" bitfld.long 0x0 8.--9. "MODER4,MODER4" "0,1,2,3" bitfld.long 0x0 6.--7. "MODER3,MODER3" "0,1,2,3" bitfld.long 0x0 4.--5. "MODER2,MODER2" "0,1,2,3" newline bitfld.long 0x0 2.--3. "MODER1,MODER1" "0,1,2,3" bitfld.long 0x0 0.--1. "MODER0,MODER0" "0,1,2,3" line.long 0x4 "GPIOF_OTYPER,GPIO port output type register" bitfld.long 0x4 15. "OT15,OT15" "0,1" bitfld.long 0x4 14. "OT14,OT14" "0,1" bitfld.long 0x4 13. "OT13,OT13" "0,1" bitfld.long 0x4 12. "OT12,OT12" "0,1" bitfld.long 0x4 11. "OT11,OT11" "0,1" bitfld.long 0x4 10. "OT10,OT10" "0,1" bitfld.long 0x4 9. "OT9,OT9" "0,1" newline bitfld.long 0x4 8. "OT8,OT8" "0,1" bitfld.long 0x4 7. "OT7,OT7" "0,1" bitfld.long 0x4 6. "OT6,OT6" "0,1" bitfld.long 0x4 5. "OT5,OT5" "0,1" bitfld.long 0x4 4. "OT4,OT4" "0,1" bitfld.long 0x4 3. "OT3,OT3" "0,1" bitfld.long 0x4 2. "OT2,OT2" "0,1" newline bitfld.long 0x4 1. "OT1,OT1" "0,1" bitfld.long 0x4 0. "OT0,OT0" "0,1" line.long 0x8 "GPIOF_OSPEEDR,GPIO port output speed register" bitfld.long 0x8 30.--31. "OSPEEDR15,OSPEEDR15" "0,1,2,3" bitfld.long 0x8 28.--29. "OSPEEDR14,OSPEEDR14" "0,1,2,3" bitfld.long 0x8 26.--27. "OSPEEDR13,OSPEEDR13" "0,1,2,3" bitfld.long 0x8 24.--25. "OSPEEDR12,OSPEEDR12" "0,1,2,3" bitfld.long 0x8 22.--23. "OSPEEDR11,OSPEEDR11" "0,1,2,3" bitfld.long 0x8 20.--21. "OSPEEDR10,OSPEEDR10" "0,1,2,3" bitfld.long 0x8 18.--19. "OSPEEDR9,OSPEEDR9" "0,1,2,3" newline bitfld.long 0x8 16.--17. "OSPEEDR8,OSPEEDR8" "0,1,2,3" bitfld.long 0x8 14.--15. "OSPEEDR7,OSPEEDR7" "0,1,2,3" bitfld.long 0x8 12.--13. "OSPEEDR6,OSPEEDR6" "0,1,2,3" bitfld.long 0x8 10.--11. "OSPEEDR5,OSPEEDR5" "0,1,2,3" bitfld.long 0x8 8.--9. "OSPEEDR4,OSPEEDR4" "0,1,2,3" bitfld.long 0x8 6.--7. "OSPEEDR3,OSPEEDR3" "0,1,2,3" bitfld.long 0x8 4.--5. "OSPEEDR2,OSPEEDR2" "0,1,2,3" newline bitfld.long 0x8 2.--3. "OSPEEDR1,OSPEEDR1" "0,1,2,3" bitfld.long 0x8 0.--1. "OSPEEDR0,OSPEEDR0" "0,1,2,3" line.long 0xC "GPIOF_PUPDR,GPIO port pull-up/pull-down register" bitfld.long 0xC 30.--31. "PUPDR15,PUPDR15" "0,1,2,3" bitfld.long 0xC 28.--29. "PUPDR14,PUPDR14" "0,1,2,3" bitfld.long 0xC 26.--27. "PUPDR13,PUPDR13" "0,1,2,3" bitfld.long 0xC 24.--25. "PUPDR12,PUPDR12" "0,1,2,3" bitfld.long 0xC 22.--23. "PUPDR11,PUPDR11" "0,1,2,3" bitfld.long 0xC 20.--21. "PUPDR10,PUPDR10" "0,1,2,3" bitfld.long 0xC 18.--19. "PUPDR9,PUPDR9" "0,1,2,3" newline bitfld.long 0xC 16.--17. "PUPDR8,PUPDR8" "0,1,2,3" bitfld.long 0xC 14.--15. "PUPDR7,PUPDR7" "0,1,2,3" bitfld.long 0xC 12.--13. "PUPDR6,PUPDR6" "0,1,2,3" bitfld.long 0xC 10.--11. "PUPDR5,PUPDR5" "0,1,2,3" bitfld.long 0xC 8.--9. "PUPDR4,PUPDR4" "0,1,2,3" bitfld.long 0xC 6.--7. "PUPDR3,PUPDR3" "0,1,2,3" bitfld.long 0xC 4.--5. "PUPDR2,PUPDR2" "0,1,2,3" newline bitfld.long 0xC 2.--3. "PUPDR1,PUPDR1" "0,1,2,3" bitfld.long 0xC 0.--1. "PUPDR0,PUPDR0" "0,1,2,3" rgroup.long 0x10++0x3 line.long 0x0 "GPIOF_IDR,GPIO port input data register" bitfld.long 0x0 15. "IDR15,IDR15" "0,1" bitfld.long 0x0 14. "IDR14,IDR14" "0,1" bitfld.long 0x0 13. "IDR13,IDR13" "0,1" bitfld.long 0x0 12. "IDR12,IDR12" "0,1" bitfld.long 0x0 11. "IDR11,IDR11" "0,1" bitfld.long 0x0 10. "IDR10,IDR10" "0,1" bitfld.long 0x0 9. "IDR9,IDR9" "0,1" newline bitfld.long 0x0 8. "IDR8,IDR8" "0,1" bitfld.long 0x0 7. "IDR7,IDR7" "0,1" bitfld.long 0x0 6. "IDR6,IDR6" "0,1" bitfld.long 0x0 5. "IDR5,IDR5" "0,1" bitfld.long 0x0 4. "IDR4,IDR4" "0,1" bitfld.long 0x0 3. "IDR3,IDR3" "0,1" bitfld.long 0x0 2. "IDR2,IDR2" "0,1" newline bitfld.long 0x0 1. "IDR1,IDR1" "0,1" bitfld.long 0x0 0. "IDR0,IDR0" "0,1" group.long 0x14++0x3 line.long 0x0 "GPIOF_ODR,GPIO port output data register" bitfld.long 0x0 15. "ODR15,ODR15" "0,1" bitfld.long 0x0 14. "ODR14,ODR14" "0,1" bitfld.long 0x0 13. "ODR13,ODR13" "0,1" bitfld.long 0x0 12. "ODR12,ODR12" "0,1" bitfld.long 0x0 11. "ODR11,ODR11" "0,1" bitfld.long 0x0 10. "ODR10,ODR10" "0,1" bitfld.long 0x0 9. "ODR9,ODR9" "0,1" newline bitfld.long 0x0 8. "ODR8,ODR8" "0,1" bitfld.long 0x0 7. "ODR7,ODR7" "0,1" bitfld.long 0x0 6. "ODR6,ODR6" "0,1" bitfld.long 0x0 5. "ODR5,ODR5" "0,1" bitfld.long 0x0 4. "ODR4,ODR4" "0,1" bitfld.long 0x0 3. "ODR3,ODR3" "0,1" bitfld.long 0x0 2. "ODR2,ODR2" "0,1" newline bitfld.long 0x0 1. "ODR1,ODR1" "0,1" bitfld.long 0x0 0. "ODR0,ODR0" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "GPIOF_BSRR,GPIO port bit set/reset register" bitfld.long 0x0 31. "BR15,BR15" "0,1" bitfld.long 0x0 30. "BR14,BR14" "0,1" bitfld.long 0x0 29. "BR13,BR13" "0,1" bitfld.long 0x0 28. "BR12,BR12" "0,1" bitfld.long 0x0 27. "BR11,BR11" "0,1" bitfld.long 0x0 26. "BR10,BR10" "0,1" bitfld.long 0x0 25. "BR9,BR9" "0,1" newline bitfld.long 0x0 24. "BR8,BR8" "0,1" bitfld.long 0x0 23. "BR7,BR7" "0,1" bitfld.long 0x0 22. "BR6,BR6" "0,1" bitfld.long 0x0 21. "BR5,BR5" "0,1" bitfld.long 0x0 20. "BR4,BR4" "0,1" bitfld.long 0x0 19. "BR3,BR3" "0,1" bitfld.long 0x0 18. "BR2,BR2" "0,1" newline bitfld.long 0x0 17. "BR1,BR1" "0,1" bitfld.long 0x0 16. "BR0,BR0" "0,1" bitfld.long 0x0 15. "BS15,BS15" "0,1" bitfld.long 0x0 14. "BS14,BS14" "0,1" bitfld.long 0x0 13. "BS13,BS13" "0,1" bitfld.long 0x0 12. "BS12,BS12" "0,1" bitfld.long 0x0 11. "BS11,BS11" "0,1" newline bitfld.long 0x0 10. "BS10,BS10" "0,1" bitfld.long 0x0 9. "BS9,BS9" "0,1" bitfld.long 0x0 8. "BS8,BS8" "0,1" bitfld.long 0x0 7. "BS7,BS7" "0,1" bitfld.long 0x0 6. "BS6,BS6" "0,1" bitfld.long 0x0 5. "BS5,BS5" "0,1" bitfld.long 0x0 4. "BS4,BS4" "0,1" newline bitfld.long 0x0 3. "BS3,BS3" "0,1" bitfld.long 0x0 2. "BS2,BS2" "0,1" bitfld.long 0x0 1. "BS1,BS1" "0,1" bitfld.long 0x0 0. "BS0,BS0" "0,1" group.long 0x1C++0xB line.long 0x0 "GPIOF_LCKR,This register is used to lock the configuration of the port bits when a correct write sequence is applied to bit 16 (LCKK). The value of bits [15:0] is used to lock the configuration of the GPIO. During the write sequence. the value of.." bitfld.long 0x0 16. "LCKK,LCKK" "0,1" bitfld.long 0x0 15. "LCK15,LCK15" "0,1" bitfld.long 0x0 14. "LCK14,LCK14" "0,1" bitfld.long 0x0 13. "LCK13,LCK13" "0,1" bitfld.long 0x0 12. "LCK12,LCK12" "0,1" bitfld.long 0x0 11. "LCK11,LCK11" "0,1" bitfld.long 0x0 10. "LCK10,LCK10" "0,1" newline bitfld.long 0x0 9. "LCK9,LCK9" "0,1" bitfld.long 0x0 8. "LCK8,LCK8" "0,1" bitfld.long 0x0 7. "LCK7,LCK7" "0,1" bitfld.long 0x0 6. "LCK6,LCK6" "0,1" bitfld.long 0x0 5. "LCK5,LCK5" "0,1" bitfld.long 0x0 4. "LCK4,LCK4" "0,1" bitfld.long 0x0 3. "LCK3,LCK3" "0,1" newline bitfld.long 0x0 2. "LCK2,LCK2" "0,1" bitfld.long 0x0 1. "LCK1,LCK1" "0,1" bitfld.long 0x0 0. "LCK0,LCK0" "0,1" line.long 0x4 "GPIOF_AFRL,GPIO alternate function low register" hexmask.long.byte 0x4 28.--31. 1. "AFR7,AFR7" hexmask.long.byte 0x4 24.--27. 1. "AFR6,AFR6" hexmask.long.byte 0x4 20.--23. 1. "AFR5,AFR5" hexmask.long.byte 0x4 16.--19. 1. "AFR4,AFR4" hexmask.long.byte 0x4 12.--15. 1. "AFR3,AFR3" hexmask.long.byte 0x4 8.--11. 1. "AFR2,AFR2" hexmask.long.byte 0x4 4.--7. 1. "AFR1,AFR1" newline hexmask.long.byte 0x4 0.--3. 1. "AFR0,AFR0" line.long 0x8 "GPIOF_AFRH,GPIO alternate function high register" hexmask.long.byte 0x8 28.--31. 1. "AFR15,AFR15" hexmask.long.byte 0x8 24.--27. 1. "AFR14,AFR14" hexmask.long.byte 0x8 20.--23. 1. "AFR13,AFR13" hexmask.long.byte 0x8 16.--19. 1. "AFR12,AFR12" hexmask.long.byte 0x8 12.--15. 1. "AFR11,AFR11" hexmask.long.byte 0x8 8.--11. 1. "AFR10,AFR10" hexmask.long.byte 0x8 4.--7. 1. "AFR9,AFR9" newline hexmask.long.byte 0x8 0.--3. 1. "AFR8,AFR8" wgroup.long 0x28++0x3 line.long 0x0 "GPIOF_BRR,GPIO port bit reset register" bitfld.long 0x0 15. "BR15,BR15" "0,1" bitfld.long 0x0 14. "BR14,BR14" "0,1" bitfld.long 0x0 13. "BR13,BR13" "0,1" bitfld.long 0x0 12. "BR12,BR12" "0,1" bitfld.long 0x0 11. "BR11,BR11" "0,1" bitfld.long 0x0 10. "BR10,BR10" "0,1" bitfld.long 0x0 9. "BR9,BR9" "0,1" newline bitfld.long 0x0 8. "BR8,BR8" "0,1" bitfld.long 0x0 7. "BR7,BR7" "0,1" bitfld.long 0x0 6. "BR6,BR6" "0,1" bitfld.long 0x0 5. "BR5,BR5" "0,1" bitfld.long 0x0 4. "BR4,BR4" "0,1" bitfld.long 0x0 3. "BR3,BR3" "0,1" bitfld.long 0x0 2. "BR2,BR2" "0,1" newline bitfld.long 0x0 1. "BR1,BR1" "0,1" bitfld.long 0x0 0. "BR0,BR0" "0,1" group.long 0x30++0x3 line.long 0x0 "GPIOF_SECCFGR,GPIO secure configuration register" bitfld.long 0x0 15. "SEC15,SEC15" "0,1" bitfld.long 0x0 14. "SEC14,SEC14" "0,1" bitfld.long 0x0 13. "SEC13,SEC13" "0,1" bitfld.long 0x0 12. "SEC12,SEC12" "0,1" bitfld.long 0x0 11. "SEC11,SEC11" "0,1" bitfld.long 0x0 10. "SEC10,SEC10" "0,1" bitfld.long 0x0 9. "SEC9,SEC9" "0,1" newline bitfld.long 0x0 8. "SEC8,SEC8" "0,1" bitfld.long 0x0 7. "SEC7,SEC7" "0,1" bitfld.long 0x0 6. "SEC6,SEC6" "0,1" bitfld.long 0x0 5. "SEC5,SEC5" "0,1" bitfld.long 0x0 4. "SEC4,SEC4" "0,1" bitfld.long 0x0 3. "SEC3,SEC3" "0,1" bitfld.long 0x0 2. "SEC2,SEC2" "0,1" newline bitfld.long 0x0 1. "SEC1,SEC1" "0,1" bitfld.long 0x0 0. "SEC0,SEC0" "0,1" rgroup.long 0x3C8++0x37 line.long 0x0 "GPIOF_HWCFGR10,For GPIOA. B. C. D. E. F. G. H. I. J and GPIOK: For GPIOZ:" hexmask.long.byte 0x0 20.--23. 1. "OR_CFG,OR_CFG" hexmask.long.byte 0x0 16.--19. 1. "SEC_CFG,SEC_CFG" hexmask.long.byte 0x0 12.--15. 1. "LOCK_CFG,LOCK_CFG" hexmask.long.byte 0x0 8.--11. 1. "SPEED_CFG,SPEED_CFG" hexmask.long.byte 0x0 4.--7. 1. "AF_SIZE,AF_SIZE" hexmask.long.byte 0x0 0.--3. 1. "AHB_IOP,AHB_IOP" line.long 0x4 "GPIOF_HWCFGR9,For GPIOA. B. C. D. E. F. G. H. I. and GPIOJ: For GPIOK and GPIOZ:" hexmask.long.word 0x4 0.--15. 1. "EN_IO,EN_IO" line.long 0x8 "GPIOF_HWCFGR8,For GPIOA. B. C. D. E. F. G. H. I. and GPIOJ: For GPIOK and GPIOZ:" hexmask.long.byte 0x8 28.--31. 1. "AF_PRIO15,AF_PRIO15" hexmask.long.byte 0x8 24.--27. 1. "AF_PRIO14,AF_PRIO14" hexmask.long.byte 0x8 20.--23. 1. "AF_PRIO13,AF_PRIO13" hexmask.long.byte 0x8 16.--19. 1. "AF_PRIO12,AF_PRIO12" hexmask.long.byte 0x8 12.--15. 1. "AF_PRIO11,AF_PRIO11" hexmask.long.byte 0x8 8.--11. 1. "AF_PRIO10,AF_PRIO10" hexmask.long.byte 0x8 4.--7. 1. "AF_PRIO9,AF_PRIO9" newline hexmask.long.byte 0x8 0.--3. 1. "AF_PRIO8,AF_PRIO8" line.long 0xC "GPIOF_HWCFGR7,GPIO hardware configuration register 7" hexmask.long.byte 0xC 28.--31. 1. "AF_PRIO7,AF_PRIO7" hexmask.long.byte 0xC 24.--27. 1. "AF_PRIO6,AF_PRIO6" hexmask.long.byte 0xC 20.--23. 1. "AF_PRIO5,AF_PRIO5" hexmask.long.byte 0xC 16.--19. 1. "AF_PRIO4,AF_PRIO4" hexmask.long.byte 0xC 12.--15. 1. "AF_PRIO3,AF_PRIO3" hexmask.long.byte 0xC 8.--11. 1. "AF_PRIO2,AF_PRIO2" hexmask.long.byte 0xC 4.--7. 1. "AF_PRIO1,AF_PRIO1" newline hexmask.long.byte 0xC 0.--3. 1. "AF_PRIO0,AF_PRIO0" line.long 0x10 "GPIOF_HWCFGR6,GPIO hardware configuration register 6" hexmask.long 0x10 0.--31. 1. "MODER_RES,MODER_RES" line.long 0x14 "GPIOF_HWCFGR5,GPIO hardware configuration register 5" hexmask.long 0x14 0.--31. 1. "PUPDR_RES,PUPDR_RES" line.long 0x18 "GPIOF_HWCFGR4,GPIO hardware configuration register 4" hexmask.long 0x18 0.--31. 1. "OSPEED_RES,OSPEED_RES" line.long 0x1C "GPIOF_HWCFGR3,GPIO hardware configuration register 3" hexmask.long.word 0x1C 16.--31. 1. "OTYPER_RES,OTYPER_RES" hexmask.long.word 0x1C 0.--15. 1. "ODR_RES,ODR_RES" line.long 0x20 "GPIOF_HWCFGR2,GPIO hardware configuration register 2" hexmask.long 0x20 0.--31. 1. "AFRL_RES,AFRL_RES" line.long 0x24 "GPIOF_HWCFGR1,GPIO hardware configuration register 1" hexmask.long 0x24 0.--31. 1. "AFRH_RES,AFRH_RES" line.long 0x28 "GPIOF_HWCFGR0,GPIO hardware configuration register 0" hexmask.long.word 0x28 0.--15. 1. "OR_RES,OR_RES" line.long 0x2C "GPIOF_VERR,GPIO version register" hexmask.long.byte 0x2C 4.--7. 1. "MAJREV,MAJREV" hexmask.long.byte 0x2C 0.--3. 1. "MINREV,MINREV" line.long 0x30 "GPIOF_IPIDR,GPIO identification register" hexmask.long 0x30 0.--31. 1. "IPIDR,IPIDR" line.long 0x34 "GPIOF_SIDR,GPIO size identification register" hexmask.long 0x34 0.--31. 1. "SIDR,SIDR" tree.end endif sif (cpuis("STM32MP13*")) tree "GPIOG" base ad:0x50008000 group.long 0x0++0xF line.long 0x0 "GPIOG_MODER,GPIO port mode register" bitfld.long 0x0 30.--31. "MODER15,MODER15" "0,1,2,3" bitfld.long 0x0 28.--29. "MODER14,MODER14" "0,1,2,3" bitfld.long 0x0 26.--27. "MODER13,MODER13" "0,1,2,3" bitfld.long 0x0 24.--25. "MODER12,MODER12" "0,1,2,3" bitfld.long 0x0 22.--23. "MODER11,MODER11" "0,1,2,3" bitfld.long 0x0 20.--21. "MODER10,MODER10" "0,1,2,3" bitfld.long 0x0 18.--19. "MODER9,MODER9" "0,1,2,3" newline bitfld.long 0x0 16.--17. "MODER8,MODER8" "0,1,2,3" bitfld.long 0x0 14.--15. "MODER7,MODER7" "0,1,2,3" bitfld.long 0x0 12.--13. "MODER6,MODER6" "0,1,2,3" bitfld.long 0x0 10.--11. "MODER5,MODER5" "0,1,2,3" bitfld.long 0x0 8.--9. "MODER4,MODER4" "0,1,2,3" bitfld.long 0x0 6.--7. "MODER3,MODER3" "0,1,2,3" bitfld.long 0x0 4.--5. "MODER2,MODER2" "0,1,2,3" newline bitfld.long 0x0 2.--3. "MODER1,MODER1" "0,1,2,3" bitfld.long 0x0 0.--1. "MODER0,MODER0" "0,1,2,3" line.long 0x4 "GPIOG_OTYPER,GPIO port output type register" bitfld.long 0x4 15. "OT15,OT15" "0,1" bitfld.long 0x4 14. "OT14,OT14" "0,1" bitfld.long 0x4 13. "OT13,OT13" "0,1" bitfld.long 0x4 12. "OT12,OT12" "0,1" bitfld.long 0x4 11. "OT11,OT11" "0,1" bitfld.long 0x4 10. "OT10,OT10" "0,1" bitfld.long 0x4 9. "OT9,OT9" "0,1" newline bitfld.long 0x4 8. "OT8,OT8" "0,1" bitfld.long 0x4 7. "OT7,OT7" "0,1" bitfld.long 0x4 6. "OT6,OT6" "0,1" bitfld.long 0x4 5. "OT5,OT5" "0,1" bitfld.long 0x4 4. "OT4,OT4" "0,1" bitfld.long 0x4 3. "OT3,OT3" "0,1" bitfld.long 0x4 2. "OT2,OT2" "0,1" newline bitfld.long 0x4 1. "OT1,OT1" "0,1" bitfld.long 0x4 0. "OT0,OT0" "0,1" line.long 0x8 "GPIOG_OSPEEDR,GPIO port output speed register" bitfld.long 0x8 30.--31. "OSPEEDR15,OSPEEDR15" "0,1,2,3" bitfld.long 0x8 28.--29. "OSPEEDR14,OSPEEDR14" "0,1,2,3" bitfld.long 0x8 26.--27. "OSPEEDR13,OSPEEDR13" "0,1,2,3" bitfld.long 0x8 24.--25. "OSPEEDR12,OSPEEDR12" "0,1,2,3" bitfld.long 0x8 22.--23. "OSPEEDR11,OSPEEDR11" "0,1,2,3" bitfld.long 0x8 20.--21. "OSPEEDR10,OSPEEDR10" "0,1,2,3" bitfld.long 0x8 18.--19. "OSPEEDR9,OSPEEDR9" "0,1,2,3" newline bitfld.long 0x8 16.--17. "OSPEEDR8,OSPEEDR8" "0,1,2,3" bitfld.long 0x8 14.--15. "OSPEEDR7,OSPEEDR7" "0,1,2,3" bitfld.long 0x8 12.--13. "OSPEEDR6,OSPEEDR6" "0,1,2,3" bitfld.long 0x8 10.--11. "OSPEEDR5,OSPEEDR5" "0,1,2,3" bitfld.long 0x8 8.--9. "OSPEEDR4,OSPEEDR4" "0,1,2,3" bitfld.long 0x8 6.--7. "OSPEEDR3,OSPEEDR3" "0,1,2,3" bitfld.long 0x8 4.--5. "OSPEEDR2,OSPEEDR2" "0,1,2,3" newline bitfld.long 0x8 2.--3. "OSPEEDR1,OSPEEDR1" "0,1,2,3" bitfld.long 0x8 0.--1. "OSPEEDR0,OSPEEDR0" "0,1,2,3" line.long 0xC "GPIOG_PUPDR,GPIO port pull-up/pull-down register" bitfld.long 0xC 30.--31. "PUPDR15,PUPDR15" "0,1,2,3" bitfld.long 0xC 28.--29. "PUPDR14,PUPDR14" "0,1,2,3" bitfld.long 0xC 26.--27. "PUPDR13,PUPDR13" "0,1,2,3" bitfld.long 0xC 24.--25. "PUPDR12,PUPDR12" "0,1,2,3" bitfld.long 0xC 22.--23. "PUPDR11,PUPDR11" "0,1,2,3" bitfld.long 0xC 20.--21. "PUPDR10,PUPDR10" "0,1,2,3" bitfld.long 0xC 18.--19. "PUPDR9,PUPDR9" "0,1,2,3" newline bitfld.long 0xC 16.--17. "PUPDR8,PUPDR8" "0,1,2,3" bitfld.long 0xC 14.--15. "PUPDR7,PUPDR7" "0,1,2,3" bitfld.long 0xC 12.--13. "PUPDR6,PUPDR6" "0,1,2,3" bitfld.long 0xC 10.--11. "PUPDR5,PUPDR5" "0,1,2,3" bitfld.long 0xC 8.--9. "PUPDR4,PUPDR4" "0,1,2,3" bitfld.long 0xC 6.--7. "PUPDR3,PUPDR3" "0,1,2,3" bitfld.long 0xC 4.--5. "PUPDR2,PUPDR2" "0,1,2,3" newline bitfld.long 0xC 2.--3. "PUPDR1,PUPDR1" "0,1,2,3" bitfld.long 0xC 0.--1. "PUPDR0,PUPDR0" "0,1,2,3" rgroup.long 0x10++0x3 line.long 0x0 "GPIOG_IDR,GPIO port input data register" bitfld.long 0x0 15. "IDR15,IDR15" "0,1" bitfld.long 0x0 14. "IDR14,IDR14" "0,1" bitfld.long 0x0 13. "IDR13,IDR13" "0,1" bitfld.long 0x0 12. "IDR12,IDR12" "0,1" bitfld.long 0x0 11. "IDR11,IDR11" "0,1" bitfld.long 0x0 10. "IDR10,IDR10" "0,1" bitfld.long 0x0 9. "IDR9,IDR9" "0,1" newline bitfld.long 0x0 8. "IDR8,IDR8" "0,1" bitfld.long 0x0 7. "IDR7,IDR7" "0,1" bitfld.long 0x0 6. "IDR6,IDR6" "0,1" bitfld.long 0x0 5. "IDR5,IDR5" "0,1" bitfld.long 0x0 4. "IDR4,IDR4" "0,1" bitfld.long 0x0 3. "IDR3,IDR3" "0,1" bitfld.long 0x0 2. "IDR2,IDR2" "0,1" newline bitfld.long 0x0 1. "IDR1,IDR1" "0,1" bitfld.long 0x0 0. "IDR0,IDR0" "0,1" group.long 0x14++0x3 line.long 0x0 "GPIOG_ODR,GPIO port output data register" bitfld.long 0x0 15. "ODR15,ODR15" "0,1" bitfld.long 0x0 14. "ODR14,ODR14" "0,1" bitfld.long 0x0 13. "ODR13,ODR13" "0,1" bitfld.long 0x0 12. "ODR12,ODR12" "0,1" bitfld.long 0x0 11. "ODR11,ODR11" "0,1" bitfld.long 0x0 10. "ODR10,ODR10" "0,1" bitfld.long 0x0 9. "ODR9,ODR9" "0,1" newline bitfld.long 0x0 8. "ODR8,ODR8" "0,1" bitfld.long 0x0 7. "ODR7,ODR7" "0,1" bitfld.long 0x0 6. "ODR6,ODR6" "0,1" bitfld.long 0x0 5. "ODR5,ODR5" "0,1" bitfld.long 0x0 4. "ODR4,ODR4" "0,1" bitfld.long 0x0 3. "ODR3,ODR3" "0,1" bitfld.long 0x0 2. "ODR2,ODR2" "0,1" newline bitfld.long 0x0 1. "ODR1,ODR1" "0,1" bitfld.long 0x0 0. "ODR0,ODR0" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "GPIOG_BSRR,GPIO port bit set/reset register" bitfld.long 0x0 31. "BR15,BR15" "0,1" bitfld.long 0x0 30. "BR14,BR14" "0,1" bitfld.long 0x0 29. "BR13,BR13" "0,1" bitfld.long 0x0 28. "BR12,BR12" "0,1" bitfld.long 0x0 27. "BR11,BR11" "0,1" bitfld.long 0x0 26. "BR10,BR10" "0,1" bitfld.long 0x0 25. "BR9,BR9" "0,1" newline bitfld.long 0x0 24. "BR8,BR8" "0,1" bitfld.long 0x0 23. "BR7,BR7" "0,1" bitfld.long 0x0 22. "BR6,BR6" "0,1" bitfld.long 0x0 21. "BR5,BR5" "0,1" bitfld.long 0x0 20. "BR4,BR4" "0,1" bitfld.long 0x0 19. "BR3,BR3" "0,1" bitfld.long 0x0 18. "BR2,BR2" "0,1" newline bitfld.long 0x0 17. "BR1,BR1" "0,1" bitfld.long 0x0 16. "BR0,BR0" "0,1" bitfld.long 0x0 15. "BS15,BS15" "0,1" bitfld.long 0x0 14. "BS14,BS14" "0,1" bitfld.long 0x0 13. "BS13,BS13" "0,1" bitfld.long 0x0 12. "BS12,BS12" "0,1" bitfld.long 0x0 11. "BS11,BS11" "0,1" newline bitfld.long 0x0 10. "BS10,BS10" "0,1" bitfld.long 0x0 9. "BS9,BS9" "0,1" bitfld.long 0x0 8. "BS8,BS8" "0,1" bitfld.long 0x0 7. "BS7,BS7" "0,1" bitfld.long 0x0 6. "BS6,BS6" "0,1" bitfld.long 0x0 5. "BS5,BS5" "0,1" bitfld.long 0x0 4. "BS4,BS4" "0,1" newline bitfld.long 0x0 3. "BS3,BS3" "0,1" bitfld.long 0x0 2. "BS2,BS2" "0,1" bitfld.long 0x0 1. "BS1,BS1" "0,1" bitfld.long 0x0 0. "BS0,BS0" "0,1" group.long 0x1C++0xB line.long 0x0 "GPIOG_LCKR,This register is used to lock the configuration of the port bits when a correct write sequence is applied to bit 16 (LCKK). The value of bits [15:0] is used to lock the configuration of the GPIO. During the write sequence. the value of.." bitfld.long 0x0 16. "LCKK,LCKK" "0,1" bitfld.long 0x0 15. "LCK15,LCK15" "0,1" bitfld.long 0x0 14. "LCK14,LCK14" "0,1" bitfld.long 0x0 13. "LCK13,LCK13" "0,1" bitfld.long 0x0 12. "LCK12,LCK12" "0,1" bitfld.long 0x0 11. "LCK11,LCK11" "0,1" bitfld.long 0x0 10. "LCK10,LCK10" "0,1" newline bitfld.long 0x0 9. "LCK9,LCK9" "0,1" bitfld.long 0x0 8. "LCK8,LCK8" "0,1" bitfld.long 0x0 7. "LCK7,LCK7" "0,1" bitfld.long 0x0 6. "LCK6,LCK6" "0,1" bitfld.long 0x0 5. "LCK5,LCK5" "0,1" bitfld.long 0x0 4. "LCK4,LCK4" "0,1" bitfld.long 0x0 3. "LCK3,LCK3" "0,1" newline bitfld.long 0x0 2. "LCK2,LCK2" "0,1" bitfld.long 0x0 1. "LCK1,LCK1" "0,1" bitfld.long 0x0 0. "LCK0,LCK0" "0,1" line.long 0x4 "GPIOG_AFRL,GPIO alternate function low register" hexmask.long.byte 0x4 28.--31. 1. "AFR7,AFR7" hexmask.long.byte 0x4 24.--27. 1. "AFR6,AFR6" hexmask.long.byte 0x4 20.--23. 1. "AFR5,AFR5" hexmask.long.byte 0x4 16.--19. 1. "AFR4,AFR4" hexmask.long.byte 0x4 12.--15. 1. "AFR3,AFR3" hexmask.long.byte 0x4 8.--11. 1. "AFR2,AFR2" hexmask.long.byte 0x4 4.--7. 1. "AFR1,AFR1" newline hexmask.long.byte 0x4 0.--3. 1. "AFR0,AFR0" line.long 0x8 "GPIOG_AFRH,GPIO alternate function high register" hexmask.long.byte 0x8 28.--31. 1. "AFR15,AFR15" hexmask.long.byte 0x8 24.--27. 1. "AFR14,AFR14" hexmask.long.byte 0x8 20.--23. 1. "AFR13,AFR13" hexmask.long.byte 0x8 16.--19. 1. "AFR12,AFR12" hexmask.long.byte 0x8 12.--15. 1. "AFR11,AFR11" hexmask.long.byte 0x8 8.--11. 1. "AFR10,AFR10" hexmask.long.byte 0x8 4.--7. 1. "AFR9,AFR9" newline hexmask.long.byte 0x8 0.--3. 1. "AFR8,AFR8" wgroup.long 0x28++0x3 line.long 0x0 "GPIOG_BRR,GPIO port bit reset register" bitfld.long 0x0 15. "BR15,BR15" "0,1" bitfld.long 0x0 14. "BR14,BR14" "0,1" bitfld.long 0x0 13. "BR13,BR13" "0,1" bitfld.long 0x0 12. "BR12,BR12" "0,1" bitfld.long 0x0 11. "BR11,BR11" "0,1" bitfld.long 0x0 10. "BR10,BR10" "0,1" bitfld.long 0x0 9. "BR9,BR9" "0,1" newline bitfld.long 0x0 8. "BR8,BR8" "0,1" bitfld.long 0x0 7. "BR7,BR7" "0,1" bitfld.long 0x0 6. "BR6,BR6" "0,1" bitfld.long 0x0 5. "BR5,BR5" "0,1" bitfld.long 0x0 4. "BR4,BR4" "0,1" bitfld.long 0x0 3. "BR3,BR3" "0,1" bitfld.long 0x0 2. "BR2,BR2" "0,1" newline bitfld.long 0x0 1. "BR1,BR1" "0,1" bitfld.long 0x0 0. "BR0,BR0" "0,1" group.long 0x30++0x3 line.long 0x0 "GPIOG_SECCFGR,GPIO secure configuration register" bitfld.long 0x0 15. "SEC15,SEC15" "0,1" bitfld.long 0x0 14. "SEC14,SEC14" "0,1" bitfld.long 0x0 13. "SEC13,SEC13" "0,1" bitfld.long 0x0 12. "SEC12,SEC12" "0,1" bitfld.long 0x0 11. "SEC11,SEC11" "0,1" bitfld.long 0x0 10. "SEC10,SEC10" "0,1" bitfld.long 0x0 9. "SEC9,SEC9" "0,1" newline bitfld.long 0x0 8. "SEC8,SEC8" "0,1" bitfld.long 0x0 7. "SEC7,SEC7" "0,1" bitfld.long 0x0 6. "SEC6,SEC6" "0,1" bitfld.long 0x0 5. "SEC5,SEC5" "0,1" bitfld.long 0x0 4. "SEC4,SEC4" "0,1" bitfld.long 0x0 3. "SEC3,SEC3" "0,1" bitfld.long 0x0 2. "SEC2,SEC2" "0,1" newline bitfld.long 0x0 1. "SEC1,SEC1" "0,1" bitfld.long 0x0 0. "SEC0,SEC0" "0,1" rgroup.long 0x3C8++0x37 line.long 0x0 "GPIOG_HWCFGR10,For GPIOA. B. C. D. E. F. G. H. I. J and GPIOK: For GPIOZ:" hexmask.long.byte 0x0 20.--23. 1. "OR_CFG,OR_CFG" hexmask.long.byte 0x0 16.--19. 1. "SEC_CFG,SEC_CFG" hexmask.long.byte 0x0 12.--15. 1. "LOCK_CFG,LOCK_CFG" hexmask.long.byte 0x0 8.--11. 1. "SPEED_CFG,SPEED_CFG" hexmask.long.byte 0x0 4.--7. 1. "AF_SIZE,AF_SIZE" hexmask.long.byte 0x0 0.--3. 1. "AHB_IOP,AHB_IOP" line.long 0x4 "GPIOG_HWCFGR9,For GPIOA. B. C. D. E. F. G. H. I. and GPIOJ: For GPIOK and GPIOZ:" hexmask.long.word 0x4 0.--15. 1. "EN_IO,EN_IO" line.long 0x8 "GPIOG_HWCFGR8,For GPIOA. B. C. D. E. F. G. H. I. and GPIOJ: For GPIOK and GPIOZ:" hexmask.long.byte 0x8 28.--31. 1. "AF_PRIO15,AF_PRIO15" hexmask.long.byte 0x8 24.--27. 1. "AF_PRIO14,AF_PRIO14" hexmask.long.byte 0x8 20.--23. 1. "AF_PRIO13,AF_PRIO13" hexmask.long.byte 0x8 16.--19. 1. "AF_PRIO12,AF_PRIO12" hexmask.long.byte 0x8 12.--15. 1. "AF_PRIO11,AF_PRIO11" hexmask.long.byte 0x8 8.--11. 1. "AF_PRIO10,AF_PRIO10" hexmask.long.byte 0x8 4.--7. 1. "AF_PRIO9,AF_PRIO9" newline hexmask.long.byte 0x8 0.--3. 1. "AF_PRIO8,AF_PRIO8" line.long 0xC "GPIOG_HWCFGR7,GPIO hardware configuration register 7" hexmask.long.byte 0xC 28.--31. 1. "AF_PRIO7,AF_PRIO7" hexmask.long.byte 0xC 24.--27. 1. "AF_PRIO6,AF_PRIO6" hexmask.long.byte 0xC 20.--23. 1. "AF_PRIO5,AF_PRIO5" hexmask.long.byte 0xC 16.--19. 1. "AF_PRIO4,AF_PRIO4" hexmask.long.byte 0xC 12.--15. 1. "AF_PRIO3,AF_PRIO3" hexmask.long.byte 0xC 8.--11. 1. "AF_PRIO2,AF_PRIO2" hexmask.long.byte 0xC 4.--7. 1. "AF_PRIO1,AF_PRIO1" newline hexmask.long.byte 0xC 0.--3. 1. "AF_PRIO0,AF_PRIO0" line.long 0x10 "GPIOG_HWCFGR6,GPIO hardware configuration register 6" hexmask.long 0x10 0.--31. 1. "MODER_RES,MODER_RES" line.long 0x14 "GPIOG_HWCFGR5,GPIO hardware configuration register 5" hexmask.long 0x14 0.--31. 1. "PUPDR_RES,PUPDR_RES" line.long 0x18 "GPIOG_HWCFGR4,GPIO hardware configuration register 4" hexmask.long 0x18 0.--31. 1. "OSPEED_RES,OSPEED_RES" line.long 0x1C "GPIOG_HWCFGR3,GPIO hardware configuration register 3" hexmask.long.word 0x1C 16.--31. 1. "OTYPER_RES,OTYPER_RES" hexmask.long.word 0x1C 0.--15. 1. "ODR_RES,ODR_RES" line.long 0x20 "GPIOG_HWCFGR2,GPIO hardware configuration register 2" hexmask.long 0x20 0.--31. 1. "AFRL_RES,AFRL_RES" line.long 0x24 "GPIOG_HWCFGR1,GPIO hardware configuration register 1" hexmask.long 0x24 0.--31. 1. "AFRH_RES,AFRH_RES" line.long 0x28 "GPIOG_HWCFGR0,GPIO hardware configuration register 0" hexmask.long.word 0x28 0.--15. 1. "OR_RES,OR_RES" line.long 0x2C "GPIOG_VERR,GPIO version register" hexmask.long.byte 0x2C 4.--7. 1. "MAJREV,MAJREV" hexmask.long.byte 0x2C 0.--3. 1. "MINREV,MINREV" line.long 0x30 "GPIOG_IPIDR,GPIO identification register" hexmask.long 0x30 0.--31. 1. "IPIDR,IPIDR" line.long 0x34 "GPIOG_SIDR,GPIO size identification register" hexmask.long 0x34 0.--31. 1. "SIDR,SIDR" tree.end endif sif (cpuis("STM32MP13*")) tree "GPIOH" base ad:0x50009000 group.long 0x0++0xF line.long 0x0 "GPIOH_MODER,GPIO port mode register" bitfld.long 0x0 30.--31. "MODER15,MODER15" "0,1,2,3" bitfld.long 0x0 28.--29. "MODER14,MODER14" "0,1,2,3" bitfld.long 0x0 26.--27. "MODER13,MODER13" "0,1,2,3" bitfld.long 0x0 24.--25. "MODER12,MODER12" "0,1,2,3" bitfld.long 0x0 22.--23. "MODER11,MODER11" "0,1,2,3" bitfld.long 0x0 20.--21. "MODER10,MODER10" "0,1,2,3" bitfld.long 0x0 18.--19. "MODER9,MODER9" "0,1,2,3" newline bitfld.long 0x0 16.--17. "MODER8,MODER8" "0,1,2,3" bitfld.long 0x0 14.--15. "MODER7,MODER7" "0,1,2,3" bitfld.long 0x0 12.--13. "MODER6,MODER6" "0,1,2,3" bitfld.long 0x0 10.--11. "MODER5,MODER5" "0,1,2,3" bitfld.long 0x0 8.--9. "MODER4,MODER4" "0,1,2,3" bitfld.long 0x0 6.--7. "MODER3,MODER3" "0,1,2,3" bitfld.long 0x0 4.--5. "MODER2,MODER2" "0,1,2,3" newline bitfld.long 0x0 2.--3. "MODER1,MODER1" "0,1,2,3" bitfld.long 0x0 0.--1. "MODER0,MODER0" "0,1,2,3" line.long 0x4 "GPIOH_OTYPER,GPIO port output type register" bitfld.long 0x4 15. "OT15,OT15" "0,1" bitfld.long 0x4 14. "OT14,OT14" "0,1" bitfld.long 0x4 13. "OT13,OT13" "0,1" bitfld.long 0x4 12. "OT12,OT12" "0,1" bitfld.long 0x4 11. "OT11,OT11" "0,1" bitfld.long 0x4 10. "OT10,OT10" "0,1" bitfld.long 0x4 9. "OT9,OT9" "0,1" newline bitfld.long 0x4 8. "OT8,OT8" "0,1" bitfld.long 0x4 7. "OT7,OT7" "0,1" bitfld.long 0x4 6. "OT6,OT6" "0,1" bitfld.long 0x4 5. "OT5,OT5" "0,1" bitfld.long 0x4 4. "OT4,OT4" "0,1" bitfld.long 0x4 3. "OT3,OT3" "0,1" bitfld.long 0x4 2. "OT2,OT2" "0,1" newline bitfld.long 0x4 1. "OT1,OT1" "0,1" bitfld.long 0x4 0. "OT0,OT0" "0,1" line.long 0x8 "GPIOH_OSPEEDR,GPIO port output speed register" bitfld.long 0x8 30.--31. "OSPEEDR15,OSPEEDR15" "0,1,2,3" bitfld.long 0x8 28.--29. "OSPEEDR14,OSPEEDR14" "0,1,2,3" bitfld.long 0x8 26.--27. "OSPEEDR13,OSPEEDR13" "0,1,2,3" bitfld.long 0x8 24.--25. "OSPEEDR12,OSPEEDR12" "0,1,2,3" bitfld.long 0x8 22.--23. "OSPEEDR11,OSPEEDR11" "0,1,2,3" bitfld.long 0x8 20.--21. "OSPEEDR10,OSPEEDR10" "0,1,2,3" bitfld.long 0x8 18.--19. "OSPEEDR9,OSPEEDR9" "0,1,2,3" newline bitfld.long 0x8 16.--17. "OSPEEDR8,OSPEEDR8" "0,1,2,3" bitfld.long 0x8 14.--15. "OSPEEDR7,OSPEEDR7" "0,1,2,3" bitfld.long 0x8 12.--13. "OSPEEDR6,OSPEEDR6" "0,1,2,3" bitfld.long 0x8 10.--11. "OSPEEDR5,OSPEEDR5" "0,1,2,3" bitfld.long 0x8 8.--9. "OSPEEDR4,OSPEEDR4" "0,1,2,3" bitfld.long 0x8 6.--7. "OSPEEDR3,OSPEEDR3" "0,1,2,3" bitfld.long 0x8 4.--5. "OSPEEDR2,OSPEEDR2" "0,1,2,3" newline bitfld.long 0x8 2.--3. "OSPEEDR1,OSPEEDR1" "0,1,2,3" bitfld.long 0x8 0.--1. "OSPEEDR0,OSPEEDR0" "0,1,2,3" line.long 0xC "GPIOH_PUPDR,GPIO port pull-up/pull-down register" bitfld.long 0xC 30.--31. "PUPDR15,PUPDR15" "0,1,2,3" bitfld.long 0xC 28.--29. "PUPDR14,PUPDR14" "0,1,2,3" bitfld.long 0xC 26.--27. "PUPDR13,PUPDR13" "0,1,2,3" bitfld.long 0xC 24.--25. "PUPDR12,PUPDR12" "0,1,2,3" bitfld.long 0xC 22.--23. "PUPDR11,PUPDR11" "0,1,2,3" bitfld.long 0xC 20.--21. "PUPDR10,PUPDR10" "0,1,2,3" bitfld.long 0xC 18.--19. "PUPDR9,PUPDR9" "0,1,2,3" newline bitfld.long 0xC 16.--17. "PUPDR8,PUPDR8" "0,1,2,3" bitfld.long 0xC 14.--15. "PUPDR7,PUPDR7" "0,1,2,3" bitfld.long 0xC 12.--13. "PUPDR6,PUPDR6" "0,1,2,3" bitfld.long 0xC 10.--11. "PUPDR5,PUPDR5" "0,1,2,3" bitfld.long 0xC 8.--9. "PUPDR4,PUPDR4" "0,1,2,3" bitfld.long 0xC 6.--7. "PUPDR3,PUPDR3" "0,1,2,3" bitfld.long 0xC 4.--5. "PUPDR2,PUPDR2" "0,1,2,3" newline bitfld.long 0xC 2.--3. "PUPDR1,PUPDR1" "0,1,2,3" bitfld.long 0xC 0.--1. "PUPDR0,PUPDR0" "0,1,2,3" rgroup.long 0x10++0x3 line.long 0x0 "GPIOH_IDR,GPIO port input data register" bitfld.long 0x0 15. "IDR15,IDR15" "0,1" bitfld.long 0x0 14. "IDR14,IDR14" "0,1" bitfld.long 0x0 13. "IDR13,IDR13" "0,1" bitfld.long 0x0 12. "IDR12,IDR12" "0,1" bitfld.long 0x0 11. "IDR11,IDR11" "0,1" bitfld.long 0x0 10. "IDR10,IDR10" "0,1" bitfld.long 0x0 9. "IDR9,IDR9" "0,1" newline bitfld.long 0x0 8. "IDR8,IDR8" "0,1" bitfld.long 0x0 7. "IDR7,IDR7" "0,1" bitfld.long 0x0 6. "IDR6,IDR6" "0,1" bitfld.long 0x0 5. "IDR5,IDR5" "0,1" bitfld.long 0x0 4. "IDR4,IDR4" "0,1" bitfld.long 0x0 3. "IDR3,IDR3" "0,1" bitfld.long 0x0 2. "IDR2,IDR2" "0,1" newline bitfld.long 0x0 1. "IDR1,IDR1" "0,1" bitfld.long 0x0 0. "IDR0,IDR0" "0,1" group.long 0x14++0x3 line.long 0x0 "GPIOH_ODR,GPIO port output data register" bitfld.long 0x0 15. "ODR15,ODR15" "0,1" bitfld.long 0x0 14. "ODR14,ODR14" "0,1" bitfld.long 0x0 13. "ODR13,ODR13" "0,1" bitfld.long 0x0 12. "ODR12,ODR12" "0,1" bitfld.long 0x0 11. "ODR11,ODR11" "0,1" bitfld.long 0x0 10. "ODR10,ODR10" "0,1" bitfld.long 0x0 9. "ODR9,ODR9" "0,1" newline bitfld.long 0x0 8. "ODR8,ODR8" "0,1" bitfld.long 0x0 7. "ODR7,ODR7" "0,1" bitfld.long 0x0 6. "ODR6,ODR6" "0,1" bitfld.long 0x0 5. "ODR5,ODR5" "0,1" bitfld.long 0x0 4. "ODR4,ODR4" "0,1" bitfld.long 0x0 3. "ODR3,ODR3" "0,1" bitfld.long 0x0 2. "ODR2,ODR2" "0,1" newline bitfld.long 0x0 1. "ODR1,ODR1" "0,1" bitfld.long 0x0 0. "ODR0,ODR0" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "GPIOH_BSRR,GPIO port bit set/reset register" bitfld.long 0x0 31. "BR15,BR15" "0,1" bitfld.long 0x0 30. "BR14,BR14" "0,1" bitfld.long 0x0 29. "BR13,BR13" "0,1" bitfld.long 0x0 28. "BR12,BR12" "0,1" bitfld.long 0x0 27. "BR11,BR11" "0,1" bitfld.long 0x0 26. "BR10,BR10" "0,1" bitfld.long 0x0 25. "BR9,BR9" "0,1" newline bitfld.long 0x0 24. "BR8,BR8" "0,1" bitfld.long 0x0 23. "BR7,BR7" "0,1" bitfld.long 0x0 22. "BR6,BR6" "0,1" bitfld.long 0x0 21. "BR5,BR5" "0,1" bitfld.long 0x0 20. "BR4,BR4" "0,1" bitfld.long 0x0 19. "BR3,BR3" "0,1" bitfld.long 0x0 18. "BR2,BR2" "0,1" newline bitfld.long 0x0 17. "BR1,BR1" "0,1" bitfld.long 0x0 16. "BR0,BR0" "0,1" bitfld.long 0x0 15. "BS15,BS15" "0,1" bitfld.long 0x0 14. "BS14,BS14" "0,1" bitfld.long 0x0 13. "BS13,BS13" "0,1" bitfld.long 0x0 12. "BS12,BS12" "0,1" bitfld.long 0x0 11. "BS11,BS11" "0,1" newline bitfld.long 0x0 10. "BS10,BS10" "0,1" bitfld.long 0x0 9. "BS9,BS9" "0,1" bitfld.long 0x0 8. "BS8,BS8" "0,1" bitfld.long 0x0 7. "BS7,BS7" "0,1" bitfld.long 0x0 6. "BS6,BS6" "0,1" bitfld.long 0x0 5. "BS5,BS5" "0,1" bitfld.long 0x0 4. "BS4,BS4" "0,1" newline bitfld.long 0x0 3. "BS3,BS3" "0,1" bitfld.long 0x0 2. "BS2,BS2" "0,1" bitfld.long 0x0 1. "BS1,BS1" "0,1" bitfld.long 0x0 0. "BS0,BS0" "0,1" group.long 0x1C++0xB line.long 0x0 "GPIOH_LCKR,This register is used to lock the configuration of the port bits when a correct write sequence is applied to bit 16 (LCKK). The value of bits [15:0] is used to lock the configuration of the GPIO. During the write sequence. the value of.." bitfld.long 0x0 16. "LCKK,LCKK" "0,1" bitfld.long 0x0 15. "LCK15,LCK15" "0,1" bitfld.long 0x0 14. "LCK14,LCK14" "0,1" bitfld.long 0x0 13. "LCK13,LCK13" "0,1" bitfld.long 0x0 12. "LCK12,LCK12" "0,1" bitfld.long 0x0 11. "LCK11,LCK11" "0,1" bitfld.long 0x0 10. "LCK10,LCK10" "0,1" newline bitfld.long 0x0 9. "LCK9,LCK9" "0,1" bitfld.long 0x0 8. "LCK8,LCK8" "0,1" bitfld.long 0x0 7. "LCK7,LCK7" "0,1" bitfld.long 0x0 6. "LCK6,LCK6" "0,1" bitfld.long 0x0 5. "LCK5,LCK5" "0,1" bitfld.long 0x0 4. "LCK4,LCK4" "0,1" bitfld.long 0x0 3. "LCK3,LCK3" "0,1" newline bitfld.long 0x0 2. "LCK2,LCK2" "0,1" bitfld.long 0x0 1. "LCK1,LCK1" "0,1" bitfld.long 0x0 0. "LCK0,LCK0" "0,1" line.long 0x4 "GPIOH_AFRL,GPIO alternate function low register" hexmask.long.byte 0x4 28.--31. 1. "AFR7,AFR7" hexmask.long.byte 0x4 24.--27. 1. "AFR6,AFR6" hexmask.long.byte 0x4 20.--23. 1. "AFR5,AFR5" hexmask.long.byte 0x4 16.--19. 1. "AFR4,AFR4" hexmask.long.byte 0x4 12.--15. 1. "AFR3,AFR3" hexmask.long.byte 0x4 8.--11. 1. "AFR2,AFR2" hexmask.long.byte 0x4 4.--7. 1. "AFR1,AFR1" newline hexmask.long.byte 0x4 0.--3. 1. "AFR0,AFR0" line.long 0x8 "GPIOH_AFRH,GPIO alternate function high register" hexmask.long.byte 0x8 28.--31. 1. "AFR15,AFR15" hexmask.long.byte 0x8 24.--27. 1. "AFR14,AFR14" hexmask.long.byte 0x8 20.--23. 1. "AFR13,AFR13" hexmask.long.byte 0x8 16.--19. 1. "AFR12,AFR12" hexmask.long.byte 0x8 12.--15. 1. "AFR11,AFR11" hexmask.long.byte 0x8 8.--11. 1. "AFR10,AFR10" hexmask.long.byte 0x8 4.--7. 1. "AFR9,AFR9" newline hexmask.long.byte 0x8 0.--3. 1. "AFR8,AFR8" wgroup.long 0x28++0x3 line.long 0x0 "GPIOH_BRR,GPIO port bit reset register" bitfld.long 0x0 15. "BR15,BR15" "0,1" bitfld.long 0x0 14. "BR14,BR14" "0,1" bitfld.long 0x0 13. "BR13,BR13" "0,1" bitfld.long 0x0 12. "BR12,BR12" "0,1" bitfld.long 0x0 11. "BR11,BR11" "0,1" bitfld.long 0x0 10. "BR10,BR10" "0,1" bitfld.long 0x0 9. "BR9,BR9" "0,1" newline bitfld.long 0x0 8. "BR8,BR8" "0,1" bitfld.long 0x0 7. "BR7,BR7" "0,1" bitfld.long 0x0 6. "BR6,BR6" "0,1" bitfld.long 0x0 5. "BR5,BR5" "0,1" bitfld.long 0x0 4. "BR4,BR4" "0,1" bitfld.long 0x0 3. "BR3,BR3" "0,1" bitfld.long 0x0 2. "BR2,BR2" "0,1" newline bitfld.long 0x0 1. "BR1,BR1" "0,1" bitfld.long 0x0 0. "BR0,BR0" "0,1" group.long 0x30++0x3 line.long 0x0 "GPIOH_SECCFGR,GPIO secure configuration register" bitfld.long 0x0 15. "SEC15,SEC15" "0,1" bitfld.long 0x0 14. "SEC14,SEC14" "0,1" bitfld.long 0x0 13. "SEC13,SEC13" "0,1" bitfld.long 0x0 12. "SEC12,SEC12" "0,1" bitfld.long 0x0 11. "SEC11,SEC11" "0,1" bitfld.long 0x0 10. "SEC10,SEC10" "0,1" bitfld.long 0x0 9. "SEC9,SEC9" "0,1" newline bitfld.long 0x0 8. "SEC8,SEC8" "0,1" bitfld.long 0x0 7. "SEC7,SEC7" "0,1" bitfld.long 0x0 6. "SEC6,SEC6" "0,1" bitfld.long 0x0 5. "SEC5,SEC5" "0,1" bitfld.long 0x0 4. "SEC4,SEC4" "0,1" bitfld.long 0x0 3. "SEC3,SEC3" "0,1" bitfld.long 0x0 2. "SEC2,SEC2" "0,1" newline bitfld.long 0x0 1. "SEC1,SEC1" "0,1" bitfld.long 0x0 0. "SEC0,SEC0" "0,1" rgroup.long 0x3C8++0x37 line.long 0x0 "GPIOH_HWCFGR10,For GPIOA. B. C. D. E. F. G. H. I. J and GPIOK: For GPIOZ:" hexmask.long.byte 0x0 20.--23. 1. "OR_CFG,OR_CFG" hexmask.long.byte 0x0 16.--19. 1. "SEC_CFG,SEC_CFG" hexmask.long.byte 0x0 12.--15. 1. "LOCK_CFG,LOCK_CFG" hexmask.long.byte 0x0 8.--11. 1. "SPEED_CFG,SPEED_CFG" hexmask.long.byte 0x0 4.--7. 1. "AF_SIZE,AF_SIZE" hexmask.long.byte 0x0 0.--3. 1. "AHB_IOP,AHB_IOP" line.long 0x4 "GPIOH_HWCFGR9,For GPIOA. B. C. D. E. F. G. H. I. and GPIOJ: For GPIOK and GPIOZ:" hexmask.long.word 0x4 0.--15. 1. "EN_IO,EN_IO" line.long 0x8 "GPIOH_HWCFGR8,For GPIOA. B. C. D. E. F. G. H. I. and GPIOJ: For GPIOK and GPIOZ:" hexmask.long.byte 0x8 28.--31. 1. "AF_PRIO15,AF_PRIO15" hexmask.long.byte 0x8 24.--27. 1. "AF_PRIO14,AF_PRIO14" hexmask.long.byte 0x8 20.--23. 1. "AF_PRIO13,AF_PRIO13" hexmask.long.byte 0x8 16.--19. 1. "AF_PRIO12,AF_PRIO12" hexmask.long.byte 0x8 12.--15. 1. "AF_PRIO11,AF_PRIO11" hexmask.long.byte 0x8 8.--11. 1. "AF_PRIO10,AF_PRIO10" hexmask.long.byte 0x8 4.--7. 1. "AF_PRIO9,AF_PRIO9" newline hexmask.long.byte 0x8 0.--3. 1. "AF_PRIO8,AF_PRIO8" line.long 0xC "GPIOH_HWCFGR7,GPIO hardware configuration register 7" hexmask.long.byte 0xC 28.--31. 1. "AF_PRIO7,AF_PRIO7" hexmask.long.byte 0xC 24.--27. 1. "AF_PRIO6,AF_PRIO6" hexmask.long.byte 0xC 20.--23. 1. "AF_PRIO5,AF_PRIO5" hexmask.long.byte 0xC 16.--19. 1. "AF_PRIO4,AF_PRIO4" hexmask.long.byte 0xC 12.--15. 1. "AF_PRIO3,AF_PRIO3" hexmask.long.byte 0xC 8.--11. 1. "AF_PRIO2,AF_PRIO2" hexmask.long.byte 0xC 4.--7. 1. "AF_PRIO1,AF_PRIO1" newline hexmask.long.byte 0xC 0.--3. 1. "AF_PRIO0,AF_PRIO0" line.long 0x10 "GPIOH_HWCFGR6,GPIO hardware configuration register 6" hexmask.long 0x10 0.--31. 1. "MODER_RES,MODER_RES" line.long 0x14 "GPIOH_HWCFGR5,GPIO hardware configuration register 5" hexmask.long 0x14 0.--31. 1. "PUPDR_RES,PUPDR_RES" line.long 0x18 "GPIOH_HWCFGR4,GPIO hardware configuration register 4" hexmask.long 0x18 0.--31. 1. "OSPEED_RES,OSPEED_RES" line.long 0x1C "GPIOH_HWCFGR3,GPIO hardware configuration register 3" hexmask.long.word 0x1C 16.--31. 1. "OTYPER_RES,OTYPER_RES" hexmask.long.word 0x1C 0.--15. 1. "ODR_RES,ODR_RES" line.long 0x20 "GPIOH_HWCFGR2,GPIO hardware configuration register 2" hexmask.long 0x20 0.--31. 1. "AFRL_RES,AFRL_RES" line.long 0x24 "GPIOH_HWCFGR1,GPIO hardware configuration register 1" hexmask.long 0x24 0.--31. 1. "AFRH_RES,AFRH_RES" line.long 0x28 "GPIOH_HWCFGR0,GPIO hardware configuration register 0" hexmask.long.word 0x28 0.--15. 1. "OR_RES,OR_RES" line.long 0x2C "GPIOH_VERR,GPIO version register" hexmask.long.byte 0x2C 4.--7. 1. "MAJREV,MAJREV" hexmask.long.byte 0x2C 0.--3. 1. "MINREV,MINREV" line.long 0x30 "GPIOH_IPIDR,GPIO identification register" hexmask.long 0x30 0.--31. 1. "IPIDR,IPIDR" line.long 0x34 "GPIOH_SIDR,GPIO size identification register" hexmask.long 0x34 0.--31. 1. "SIDR,SIDR" tree.end endif sif (cpuis("STM32MP13*")) tree "GPIOI" base ad:0x5000A000 group.long 0x0++0xF line.long 0x0 "GPIOI_MODER,GPIO port mode register" bitfld.long 0x0 30.--31. "MODER15,MODER15" "0,1,2,3" bitfld.long 0x0 28.--29. "MODER14,MODER14" "0,1,2,3" bitfld.long 0x0 26.--27. "MODER13,MODER13" "0,1,2,3" bitfld.long 0x0 24.--25. "MODER12,MODER12" "0,1,2,3" bitfld.long 0x0 22.--23. "MODER11,MODER11" "0,1,2,3" bitfld.long 0x0 20.--21. "MODER10,MODER10" "0,1,2,3" bitfld.long 0x0 18.--19. "MODER9,MODER9" "0,1,2,3" newline bitfld.long 0x0 16.--17. "MODER8,MODER8" "0,1,2,3" bitfld.long 0x0 14.--15. "MODER7,MODER7" "0,1,2,3" bitfld.long 0x0 12.--13. "MODER6,MODER6" "0,1,2,3" bitfld.long 0x0 10.--11. "MODER5,MODER5" "0,1,2,3" bitfld.long 0x0 8.--9. "MODER4,MODER4" "0,1,2,3" bitfld.long 0x0 6.--7. "MODER3,MODER3" "0,1,2,3" bitfld.long 0x0 4.--5. "MODER2,MODER2" "0,1,2,3" newline bitfld.long 0x0 2.--3. "MODER1,MODER1" "0,1,2,3" bitfld.long 0x0 0.--1. "MODER0,MODER0" "0,1,2,3" line.long 0x4 "GPIOI_OTYPER,GPIO port output type register" bitfld.long 0x4 15. "OT15,OT15" "0,1" bitfld.long 0x4 14. "OT14,OT14" "0,1" bitfld.long 0x4 13. "OT13,OT13" "0,1" bitfld.long 0x4 12. "OT12,OT12" "0,1" bitfld.long 0x4 11. "OT11,OT11" "0,1" bitfld.long 0x4 10. "OT10,OT10" "0,1" bitfld.long 0x4 9. "OT9,OT9" "0,1" newline bitfld.long 0x4 8. "OT8,OT8" "0,1" bitfld.long 0x4 7. "OT7,OT7" "0,1" bitfld.long 0x4 6. "OT6,OT6" "0,1" bitfld.long 0x4 5. "OT5,OT5" "0,1" bitfld.long 0x4 4. "OT4,OT4" "0,1" bitfld.long 0x4 3. "OT3,OT3" "0,1" bitfld.long 0x4 2. "OT2,OT2" "0,1" newline bitfld.long 0x4 1. "OT1,OT1" "0,1" bitfld.long 0x4 0. "OT0,OT0" "0,1" line.long 0x8 "GPIOI_OSPEEDR,GPIO port output speed register" bitfld.long 0x8 30.--31. "OSPEEDR15,OSPEEDR15" "0,1,2,3" bitfld.long 0x8 28.--29. "OSPEEDR14,OSPEEDR14" "0,1,2,3" bitfld.long 0x8 26.--27. "OSPEEDR13,OSPEEDR13" "0,1,2,3" bitfld.long 0x8 24.--25. "OSPEEDR12,OSPEEDR12" "0,1,2,3" bitfld.long 0x8 22.--23. "OSPEEDR11,OSPEEDR11" "0,1,2,3" bitfld.long 0x8 20.--21. "OSPEEDR10,OSPEEDR10" "0,1,2,3" bitfld.long 0x8 18.--19. "OSPEEDR9,OSPEEDR9" "0,1,2,3" newline bitfld.long 0x8 16.--17. "OSPEEDR8,OSPEEDR8" "0,1,2,3" bitfld.long 0x8 14.--15. "OSPEEDR7,OSPEEDR7" "0,1,2,3" bitfld.long 0x8 12.--13. "OSPEEDR6,OSPEEDR6" "0,1,2,3" bitfld.long 0x8 10.--11. "OSPEEDR5,OSPEEDR5" "0,1,2,3" bitfld.long 0x8 8.--9. "OSPEEDR4,OSPEEDR4" "0,1,2,3" bitfld.long 0x8 6.--7. "OSPEEDR3,OSPEEDR3" "0,1,2,3" bitfld.long 0x8 4.--5. "OSPEEDR2,OSPEEDR2" "0,1,2,3" newline bitfld.long 0x8 2.--3. "OSPEEDR1,OSPEEDR1" "0,1,2,3" bitfld.long 0x8 0.--1. "OSPEEDR0,OSPEEDR0" "0,1,2,3" line.long 0xC "GPIOI_PUPDR,GPIO port pull-up/pull-down register" bitfld.long 0xC 30.--31. "PUPDR15,PUPDR15" "0,1,2,3" bitfld.long 0xC 28.--29. "PUPDR14,PUPDR14" "0,1,2,3" bitfld.long 0xC 26.--27. "PUPDR13,PUPDR13" "0,1,2,3" bitfld.long 0xC 24.--25. "PUPDR12,PUPDR12" "0,1,2,3" bitfld.long 0xC 22.--23. "PUPDR11,PUPDR11" "0,1,2,3" bitfld.long 0xC 20.--21. "PUPDR10,PUPDR10" "0,1,2,3" bitfld.long 0xC 18.--19. "PUPDR9,PUPDR9" "0,1,2,3" newline bitfld.long 0xC 16.--17. "PUPDR8,PUPDR8" "0,1,2,3" bitfld.long 0xC 14.--15. "PUPDR7,PUPDR7" "0,1,2,3" bitfld.long 0xC 12.--13. "PUPDR6,PUPDR6" "0,1,2,3" bitfld.long 0xC 10.--11. "PUPDR5,PUPDR5" "0,1,2,3" bitfld.long 0xC 8.--9. "PUPDR4,PUPDR4" "0,1,2,3" bitfld.long 0xC 6.--7. "PUPDR3,PUPDR3" "0,1,2,3" bitfld.long 0xC 4.--5. "PUPDR2,PUPDR2" "0,1,2,3" newline bitfld.long 0xC 2.--3. "PUPDR1,PUPDR1" "0,1,2,3" bitfld.long 0xC 0.--1. "PUPDR0,PUPDR0" "0,1,2,3" rgroup.long 0x10++0x3 line.long 0x0 "GPIOI_IDR,GPIO port input data register" bitfld.long 0x0 15. "IDR15,IDR15" "0,1" bitfld.long 0x0 14. "IDR14,IDR14" "0,1" bitfld.long 0x0 13. "IDR13,IDR13" "0,1" bitfld.long 0x0 12. "IDR12,IDR12" "0,1" bitfld.long 0x0 11. "IDR11,IDR11" "0,1" bitfld.long 0x0 10. "IDR10,IDR10" "0,1" bitfld.long 0x0 9. "IDR9,IDR9" "0,1" newline bitfld.long 0x0 8. "IDR8,IDR8" "0,1" bitfld.long 0x0 7. "IDR7,IDR7" "0,1" bitfld.long 0x0 6. "IDR6,IDR6" "0,1" bitfld.long 0x0 5. "IDR5,IDR5" "0,1" bitfld.long 0x0 4. "IDR4,IDR4" "0,1" bitfld.long 0x0 3. "IDR3,IDR3" "0,1" bitfld.long 0x0 2. "IDR2,IDR2" "0,1" newline bitfld.long 0x0 1. "IDR1,IDR1" "0,1" bitfld.long 0x0 0. "IDR0,IDR0" "0,1" group.long 0x14++0x3 line.long 0x0 "GPIOI_ODR,GPIO port output data register" bitfld.long 0x0 15. "ODR15,ODR15" "0,1" bitfld.long 0x0 14. "ODR14,ODR14" "0,1" bitfld.long 0x0 13. "ODR13,ODR13" "0,1" bitfld.long 0x0 12. "ODR12,ODR12" "0,1" bitfld.long 0x0 11. "ODR11,ODR11" "0,1" bitfld.long 0x0 10. "ODR10,ODR10" "0,1" bitfld.long 0x0 9. "ODR9,ODR9" "0,1" newline bitfld.long 0x0 8. "ODR8,ODR8" "0,1" bitfld.long 0x0 7. "ODR7,ODR7" "0,1" bitfld.long 0x0 6. "ODR6,ODR6" "0,1" bitfld.long 0x0 5. "ODR5,ODR5" "0,1" bitfld.long 0x0 4. "ODR4,ODR4" "0,1" bitfld.long 0x0 3. "ODR3,ODR3" "0,1" bitfld.long 0x0 2. "ODR2,ODR2" "0,1" newline bitfld.long 0x0 1. "ODR1,ODR1" "0,1" bitfld.long 0x0 0. "ODR0,ODR0" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "GPIOI_BSRR,GPIO port bit set/reset register" bitfld.long 0x0 31. "BR15,BR15" "0,1" bitfld.long 0x0 30. "BR14,BR14" "0,1" bitfld.long 0x0 29. "BR13,BR13" "0,1" bitfld.long 0x0 28. "BR12,BR12" "0,1" bitfld.long 0x0 27. "BR11,BR11" "0,1" bitfld.long 0x0 26. "BR10,BR10" "0,1" bitfld.long 0x0 25. "BR9,BR9" "0,1" newline bitfld.long 0x0 24. "BR8,BR8" "0,1" bitfld.long 0x0 23. "BR7,BR7" "0,1" bitfld.long 0x0 22. "BR6,BR6" "0,1" bitfld.long 0x0 21. "BR5,BR5" "0,1" bitfld.long 0x0 20. "BR4,BR4" "0,1" bitfld.long 0x0 19. "BR3,BR3" "0,1" bitfld.long 0x0 18. "BR2,BR2" "0,1" newline bitfld.long 0x0 17. "BR1,BR1" "0,1" bitfld.long 0x0 16. "BR0,BR0" "0,1" bitfld.long 0x0 15. "BS15,BS15" "0,1" bitfld.long 0x0 14. "BS14,BS14" "0,1" bitfld.long 0x0 13. "BS13,BS13" "0,1" bitfld.long 0x0 12. "BS12,BS12" "0,1" bitfld.long 0x0 11. "BS11,BS11" "0,1" newline bitfld.long 0x0 10. "BS10,BS10" "0,1" bitfld.long 0x0 9. "BS9,BS9" "0,1" bitfld.long 0x0 8. "BS8,BS8" "0,1" bitfld.long 0x0 7. "BS7,BS7" "0,1" bitfld.long 0x0 6. "BS6,BS6" "0,1" bitfld.long 0x0 5. "BS5,BS5" "0,1" bitfld.long 0x0 4. "BS4,BS4" "0,1" newline bitfld.long 0x0 3. "BS3,BS3" "0,1" bitfld.long 0x0 2. "BS2,BS2" "0,1" bitfld.long 0x0 1. "BS1,BS1" "0,1" bitfld.long 0x0 0. "BS0,BS0" "0,1" group.long 0x1C++0xB line.long 0x0 "GPIOI_LCKR,This register is used to lock the configuration of the port bits when a correct write sequence is applied to bit 16 (LCKK). The value of bits [15:0] is used to lock the configuration of the GPIO. During the write sequence. the value of.." bitfld.long 0x0 16. "LCKK,LCKK" "0,1" bitfld.long 0x0 15. "LCK15,LCK15" "0,1" bitfld.long 0x0 14. "LCK14,LCK14" "0,1" bitfld.long 0x0 13. "LCK13,LCK13" "0,1" bitfld.long 0x0 12. "LCK12,LCK12" "0,1" bitfld.long 0x0 11. "LCK11,LCK11" "0,1" bitfld.long 0x0 10. "LCK10,LCK10" "0,1" newline bitfld.long 0x0 9. "LCK9,LCK9" "0,1" bitfld.long 0x0 8. "LCK8,LCK8" "0,1" bitfld.long 0x0 7. "LCK7,LCK7" "0,1" bitfld.long 0x0 6. "LCK6,LCK6" "0,1" bitfld.long 0x0 5. "LCK5,LCK5" "0,1" bitfld.long 0x0 4. "LCK4,LCK4" "0,1" bitfld.long 0x0 3. "LCK3,LCK3" "0,1" newline bitfld.long 0x0 2. "LCK2,LCK2" "0,1" bitfld.long 0x0 1. "LCK1,LCK1" "0,1" bitfld.long 0x0 0. "LCK0,LCK0" "0,1" line.long 0x4 "GPIOI_AFRL,GPIO alternate function low register" hexmask.long.byte 0x4 28.--31. 1. "AFR7,AFR7" hexmask.long.byte 0x4 24.--27. 1. "AFR6,AFR6" hexmask.long.byte 0x4 20.--23. 1. "AFR5,AFR5" hexmask.long.byte 0x4 16.--19. 1. "AFR4,AFR4" hexmask.long.byte 0x4 12.--15. 1. "AFR3,AFR3" hexmask.long.byte 0x4 8.--11. 1. "AFR2,AFR2" hexmask.long.byte 0x4 4.--7. 1. "AFR1,AFR1" newline hexmask.long.byte 0x4 0.--3. 1. "AFR0,AFR0" line.long 0x8 "GPIOI_AFRH,GPIO alternate function high register" hexmask.long.byte 0x8 28.--31. 1. "AFR15,AFR15" hexmask.long.byte 0x8 24.--27. 1. "AFR14,AFR14" hexmask.long.byte 0x8 20.--23. 1. "AFR13,AFR13" hexmask.long.byte 0x8 16.--19. 1. "AFR12,AFR12" hexmask.long.byte 0x8 12.--15. 1. "AFR11,AFR11" hexmask.long.byte 0x8 8.--11. 1. "AFR10,AFR10" hexmask.long.byte 0x8 4.--7. 1. "AFR9,AFR9" newline hexmask.long.byte 0x8 0.--3. 1. "AFR8,AFR8" wgroup.long 0x28++0x3 line.long 0x0 "GPIOI_BRR,GPIO port bit reset register" bitfld.long 0x0 15. "BR15,BR15" "0,1" bitfld.long 0x0 14. "BR14,BR14" "0,1" bitfld.long 0x0 13. "BR13,BR13" "0,1" bitfld.long 0x0 12. "BR12,BR12" "0,1" bitfld.long 0x0 11. "BR11,BR11" "0,1" bitfld.long 0x0 10. "BR10,BR10" "0,1" bitfld.long 0x0 9. "BR9,BR9" "0,1" newline bitfld.long 0x0 8. "BR8,BR8" "0,1" bitfld.long 0x0 7. "BR7,BR7" "0,1" bitfld.long 0x0 6. "BR6,BR6" "0,1" bitfld.long 0x0 5. "BR5,BR5" "0,1" bitfld.long 0x0 4. "BR4,BR4" "0,1" bitfld.long 0x0 3. "BR3,BR3" "0,1" bitfld.long 0x0 2. "BR2,BR2" "0,1" newline bitfld.long 0x0 1. "BR1,BR1" "0,1" bitfld.long 0x0 0. "BR0,BR0" "0,1" group.long 0x30++0x3 line.long 0x0 "GPIOI_SECCFGR,GPIO secure configuration register" bitfld.long 0x0 15. "SEC15,SEC15" "0,1" bitfld.long 0x0 14. "SEC14,SEC14" "0,1" bitfld.long 0x0 13. "SEC13,SEC13" "0,1" bitfld.long 0x0 12. "SEC12,SEC12" "0,1" bitfld.long 0x0 11. "SEC11,SEC11" "0,1" bitfld.long 0x0 10. "SEC10,SEC10" "0,1" bitfld.long 0x0 9. "SEC9,SEC9" "0,1" newline bitfld.long 0x0 8. "SEC8,SEC8" "0,1" bitfld.long 0x0 7. "SEC7,SEC7" "0,1" bitfld.long 0x0 6. "SEC6,SEC6" "0,1" bitfld.long 0x0 5. "SEC5,SEC5" "0,1" bitfld.long 0x0 4. "SEC4,SEC4" "0,1" bitfld.long 0x0 3. "SEC3,SEC3" "0,1" bitfld.long 0x0 2. "SEC2,SEC2" "0,1" newline bitfld.long 0x0 1. "SEC1,SEC1" "0,1" bitfld.long 0x0 0. "SEC0,SEC0" "0,1" rgroup.long 0x3C8++0x37 line.long 0x0 "GPIOI_HWCFGR10,For GPIOA. B. C. D. E. F. G. H. I. J and GPIOK: For GPIOZ:" hexmask.long.byte 0x0 20.--23. 1. "OR_CFG,OR_CFG" hexmask.long.byte 0x0 16.--19. 1. "SEC_CFG,SEC_CFG" hexmask.long.byte 0x0 12.--15. 1. "LOCK_CFG,LOCK_CFG" hexmask.long.byte 0x0 8.--11. 1. "SPEED_CFG,SPEED_CFG" hexmask.long.byte 0x0 4.--7. 1. "AF_SIZE,AF_SIZE" hexmask.long.byte 0x0 0.--3. 1. "AHB_IOP,AHB_IOP" line.long 0x4 "GPIOI_HWCFGR9,For GPIOA. B. C. D. E. F. G. H. I. and GPIOJ: For GPIOK and GPIOZ:" hexmask.long.word 0x4 0.--15. 1. "EN_IO,EN_IO" line.long 0x8 "GPIOI_HWCFGR8,For GPIOA. B. C. D. E. F. G. H. I. and GPIOJ: For GPIOK and GPIOZ:" hexmask.long.byte 0x8 28.--31. 1. "AF_PRIO15,AF_PRIO15" hexmask.long.byte 0x8 24.--27. 1. "AF_PRIO14,AF_PRIO14" hexmask.long.byte 0x8 20.--23. 1. "AF_PRIO13,AF_PRIO13" hexmask.long.byte 0x8 16.--19. 1. "AF_PRIO12,AF_PRIO12" hexmask.long.byte 0x8 12.--15. 1. "AF_PRIO11,AF_PRIO11" hexmask.long.byte 0x8 8.--11. 1. "AF_PRIO10,AF_PRIO10" hexmask.long.byte 0x8 4.--7. 1. "AF_PRIO9,AF_PRIO9" newline hexmask.long.byte 0x8 0.--3. 1. "AF_PRIO8,AF_PRIO8" line.long 0xC "GPIOI_HWCFGR7,GPIO hardware configuration register 7" hexmask.long.byte 0xC 28.--31. 1. "AF_PRIO7,AF_PRIO7" hexmask.long.byte 0xC 24.--27. 1. "AF_PRIO6,AF_PRIO6" hexmask.long.byte 0xC 20.--23. 1. "AF_PRIO5,AF_PRIO5" hexmask.long.byte 0xC 16.--19. 1. "AF_PRIO4,AF_PRIO4" hexmask.long.byte 0xC 12.--15. 1. "AF_PRIO3,AF_PRIO3" hexmask.long.byte 0xC 8.--11. 1. "AF_PRIO2,AF_PRIO2" hexmask.long.byte 0xC 4.--7. 1. "AF_PRIO1,AF_PRIO1" newline hexmask.long.byte 0xC 0.--3. 1. "AF_PRIO0,AF_PRIO0" line.long 0x10 "GPIOI_HWCFGR6,GPIO hardware configuration register 6" hexmask.long 0x10 0.--31. 1. "MODER_RES,MODER_RES" line.long 0x14 "GPIOI_HWCFGR5,GPIO hardware configuration register 5" hexmask.long 0x14 0.--31. 1. "PUPDR_RES,PUPDR_RES" line.long 0x18 "GPIOI_HWCFGR4,GPIO hardware configuration register 4" hexmask.long 0x18 0.--31. 1. "OSPEED_RES,OSPEED_RES" line.long 0x1C "GPIOI_HWCFGR3,GPIO hardware configuration register 3" hexmask.long.word 0x1C 16.--31. 1. "OTYPER_RES,OTYPER_RES" hexmask.long.word 0x1C 0.--15. 1. "ODR_RES,ODR_RES" line.long 0x20 "GPIOI_HWCFGR2,GPIO hardware configuration register 2" hexmask.long 0x20 0.--31. 1. "AFRL_RES,AFRL_RES" line.long 0x24 "GPIOI_HWCFGR1,GPIO hardware configuration register 1" hexmask.long 0x24 0.--31. 1. "AFRH_RES,AFRH_RES" line.long 0x28 "GPIOI_HWCFGR0,GPIO hardware configuration register 0" hexmask.long.word 0x28 0.--15. 1. "OR_RES,OR_RES" line.long 0x2C "GPIOI_VERR,GPIO version register" hexmask.long.byte 0x2C 4.--7. 1. "MAJREV,MAJREV" hexmask.long.byte 0x2C 0.--3. 1. "MINREV,MINREV" line.long 0x30 "GPIOI_IPIDR,GPIO identification register" hexmask.long 0x30 0.--31. 1. "IPIDR,IPIDR" line.long 0x34 "GPIOI_SIDR,GPIO size identification register" hexmask.long 0x34 0.--31. 1. "SIDR,SIDR" tree.end endif sif (cpuis("STM32MP151*")||cpuis("STM32MP153*")||cpuis("STM32MP157*")) tree "GPIOA" base ad:0x50002000 group.long 0x0++0xF line.long 0x0 "GPIOA_MODER,GPIO port mode register" bitfld.long 0x0 30.--31. "MODER15,MODER15" "0,1,2,3" bitfld.long 0x0 28.--29. "MODER14,MODER14" "0,1,2,3" bitfld.long 0x0 26.--27. "MODER13,MODER13" "0,1,2,3" bitfld.long 0x0 24.--25. "MODER12,MODER12" "0,1,2,3" bitfld.long 0x0 22.--23. "MODER11,MODER11" "0,1,2,3" bitfld.long 0x0 20.--21. "MODER10,MODER10" "0,1,2,3" bitfld.long 0x0 18.--19. "MODER9,MODER9" "0,1,2,3" newline bitfld.long 0x0 16.--17. "MODER8,MODER8" "0,1,2,3" bitfld.long 0x0 14.--15. "MODER7,MODER7" "0,1,2,3" bitfld.long 0x0 12.--13. "MODER6,MODER6" "0,1,2,3" bitfld.long 0x0 10.--11. "MODER5,MODER5" "0,1,2,3" bitfld.long 0x0 8.--9. "MODER4,MODER4" "0,1,2,3" bitfld.long 0x0 6.--7. "MODER3,MODER3" "0,1,2,3" bitfld.long 0x0 4.--5. "MODER2,MODER2" "0,1,2,3" newline bitfld.long 0x0 2.--3. "MODER1,MODER1" "0,1,2,3" bitfld.long 0x0 0.--1. "MODER0,MODER0" "0,1,2,3" line.long 0x4 "GPIOA_OTYPER,GPIO port output type register" bitfld.long 0x4 15. "OT15,OT15" "0,1" bitfld.long 0x4 14. "OT14,OT14" "0,1" bitfld.long 0x4 13. "OT13,OT13" "0,1" bitfld.long 0x4 12. "OT12,OT12" "0,1" bitfld.long 0x4 11. "OT11,OT11" "0,1" bitfld.long 0x4 10. "OT10,OT10" "0,1" bitfld.long 0x4 9. "OT9,OT9" "0,1" newline bitfld.long 0x4 8. "OT8,OT8" "0,1" bitfld.long 0x4 7. "OT7,OT7" "0,1" bitfld.long 0x4 6. "OT6,OT6" "0,1" bitfld.long 0x4 5. "OT5,OT5" "0,1" bitfld.long 0x4 4. "OT4,OT4" "0,1" bitfld.long 0x4 3. "OT3,OT3" "0,1" bitfld.long 0x4 2. "OT2,OT2" "0,1" newline bitfld.long 0x4 1. "OT1,OT1" "0,1" bitfld.long 0x4 0. "OT0,OT0" "0,1" line.long 0x8 "GPIOA_OSPEEDR,GPIO port output speed register" bitfld.long 0x8 30.--31. "OSPEEDR15,OSPEEDR15" "0,1,2,3" bitfld.long 0x8 28.--29. "OSPEEDR14,OSPEEDR14" "0,1,2,3" bitfld.long 0x8 26.--27. "OSPEEDR13,OSPEEDR13" "0,1,2,3" bitfld.long 0x8 24.--25. "OSPEEDR12,OSPEEDR12" "0,1,2,3" bitfld.long 0x8 22.--23. "OSPEEDR11,OSPEEDR11" "0,1,2,3" bitfld.long 0x8 20.--21. "OSPEEDR10,OSPEEDR10" "0,1,2,3" bitfld.long 0x8 18.--19. "OSPEEDR9,OSPEEDR9" "0,1,2,3" newline bitfld.long 0x8 16.--17. "OSPEEDR8,OSPEEDR8" "0,1,2,3" bitfld.long 0x8 14.--15. "OSPEEDR7,OSPEEDR7" "0,1,2,3" bitfld.long 0x8 12.--13. "OSPEEDR6,OSPEEDR6" "0,1,2,3" bitfld.long 0x8 10.--11. "OSPEEDR5,OSPEEDR5" "0,1,2,3" bitfld.long 0x8 8.--9. "OSPEEDR4,OSPEEDR4" "0,1,2,3" bitfld.long 0x8 6.--7. "OSPEEDR3,OSPEEDR3" "0,1,2,3" bitfld.long 0x8 4.--5. "OSPEEDR2,OSPEEDR2" "0,1,2,3" newline bitfld.long 0x8 2.--3. "OSPEEDR1,OSPEEDR1" "0,1,2,3" bitfld.long 0x8 0.--1. "OSPEEDR0,OSPEEDR0" "0,1,2,3" line.long 0xC "GPIOA_PUPDR,GPIO port pull-up/pull-down register" bitfld.long 0xC 30.--31. "PUPDR15,PUPDR15" "0,1,2,3" bitfld.long 0xC 28.--29. "PUPDR14,PUPDR14" "0,1,2,3" bitfld.long 0xC 26.--27. "PUPDR13,PUPDR13" "0,1,2,3" bitfld.long 0xC 24.--25. "PUPDR12,PUPDR12" "0,1,2,3" bitfld.long 0xC 22.--23. "PUPDR11,PUPDR11" "0,1,2,3" bitfld.long 0xC 20.--21. "PUPDR10,PUPDR10" "0,1,2,3" bitfld.long 0xC 18.--19. "PUPDR9,PUPDR9" "0,1,2,3" newline bitfld.long 0xC 16.--17. "PUPDR8,PUPDR8" "0,1,2,3" bitfld.long 0xC 14.--15. "PUPDR7,PUPDR7" "0,1,2,3" bitfld.long 0xC 12.--13. "PUPDR6,PUPDR6" "0,1,2,3" bitfld.long 0xC 10.--11. "PUPDR5,PUPDR5" "0,1,2,3" bitfld.long 0xC 8.--9. "PUPDR4,PUPDR4" "0,1,2,3" bitfld.long 0xC 6.--7. "PUPDR3,PUPDR3" "0,1,2,3" bitfld.long 0xC 4.--5. "PUPDR2,PUPDR2" "0,1,2,3" newline bitfld.long 0xC 2.--3. "PUPDR1,PUPDR1" "0,1,2,3" bitfld.long 0xC 0.--1. "PUPDR0,PUPDR0" "0,1,2,3" rgroup.long 0x10++0x3 line.long 0x0 "GPIOA_IDR,GPIO port input data register" bitfld.long 0x0 15. "IDR15,IDR15" "0,1" bitfld.long 0x0 14. "IDR14,IDR14" "0,1" bitfld.long 0x0 13. "IDR13,IDR13" "0,1" bitfld.long 0x0 12. "IDR12,IDR12" "0,1" bitfld.long 0x0 11. "IDR11,IDR11" "0,1" bitfld.long 0x0 10. "IDR10,IDR10" "0,1" bitfld.long 0x0 9. "IDR9,IDR9" "0,1" newline bitfld.long 0x0 8. "IDR8,IDR8" "0,1" bitfld.long 0x0 7. "IDR7,IDR7" "0,1" bitfld.long 0x0 6. "IDR6,IDR6" "0,1" bitfld.long 0x0 5. "IDR5,IDR5" "0,1" bitfld.long 0x0 4. "IDR4,IDR4" "0,1" bitfld.long 0x0 3. "IDR3,IDR3" "0,1" bitfld.long 0x0 2. "IDR2,IDR2" "0,1" newline bitfld.long 0x0 1. "IDR1,IDR1" "0,1" bitfld.long 0x0 0. "IDR0,IDR0" "0,1" group.long 0x14++0x3 line.long 0x0 "GPIOA_ODR,GPIO port output data register" bitfld.long 0x0 15. "ODR15,ODR15" "0,1" bitfld.long 0x0 14. "ODR14,ODR14" "0,1" bitfld.long 0x0 13. "ODR13,ODR13" "0,1" bitfld.long 0x0 12. "ODR12,ODR12" "0,1" bitfld.long 0x0 11. "ODR11,ODR11" "0,1" bitfld.long 0x0 10. "ODR10,ODR10" "0,1" bitfld.long 0x0 9. "ODR9,ODR9" "0,1" newline bitfld.long 0x0 8. "ODR8,ODR8" "0,1" bitfld.long 0x0 7. "ODR7,ODR7" "0,1" bitfld.long 0x0 6. "ODR6,ODR6" "0,1" bitfld.long 0x0 5. "ODR5,ODR5" "0,1" bitfld.long 0x0 4. "ODR4,ODR4" "0,1" bitfld.long 0x0 3. "ODR3,ODR3" "0,1" bitfld.long 0x0 2. "ODR2,ODR2" "0,1" newline bitfld.long 0x0 1. "ODR1,ODR1" "0,1" bitfld.long 0x0 0. "ODR0,ODR0" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "GPIOA_BSRR,GPIO port bit set/reset register" bitfld.long 0x0 31. "BR15,BR15" "0,1" bitfld.long 0x0 30. "BR14,BR14" "0,1" bitfld.long 0x0 29. "BR13,BR13" "0,1" bitfld.long 0x0 28. "BR12,BR12" "0,1" bitfld.long 0x0 27. "BR11,BR11" "0,1" bitfld.long 0x0 26. "BR10,BR10" "0,1" bitfld.long 0x0 25. "BR9,BR9" "0,1" newline bitfld.long 0x0 24. "BR8,BR8" "0,1" bitfld.long 0x0 23. "BR7,BR7" "0,1" bitfld.long 0x0 22. "BR6,BR6" "0,1" bitfld.long 0x0 21. "BR5,BR5" "0,1" bitfld.long 0x0 20. "BR4,BR4" "0,1" bitfld.long 0x0 19. "BR3,BR3" "0,1" bitfld.long 0x0 18. "BR2,BR2" "0,1" newline bitfld.long 0x0 17. "BR1,BR1" "0,1" bitfld.long 0x0 16. "BR0,BR0" "0,1" bitfld.long 0x0 15. "BS15,BS15" "0,1" bitfld.long 0x0 14. "BS14,BS14" "0,1" bitfld.long 0x0 13. "BS13,BS13" "0,1" bitfld.long 0x0 12. "BS12,BS12" "0,1" bitfld.long 0x0 11. "BS11,BS11" "0,1" newline bitfld.long 0x0 10. "BS10,BS10" "0,1" bitfld.long 0x0 9. "BS9,BS9" "0,1" bitfld.long 0x0 8. "BS8,BS8" "0,1" bitfld.long 0x0 7. "BS7,BS7" "0,1" bitfld.long 0x0 6. "BS6,BS6" "0,1" bitfld.long 0x0 5. "BS5,BS5" "0,1" bitfld.long 0x0 4. "BS4,BS4" "0,1" newline bitfld.long 0x0 3. "BS3,BS3" "0,1" bitfld.long 0x0 2. "BS2,BS2" "0,1" bitfld.long 0x0 1. "BS1,BS1" "0,1" bitfld.long 0x0 0. "BS0,BS0" "0,1" group.long 0x1C++0xB line.long 0x0 "GPIOA_LCKR,This register is used to lock the configuration of the port bits when a correct write sequence is applied to bit 16 (LCKK). The value of bits [15:0] is used to lock the configuration of the GPIO. During the write sequence. the value of.." bitfld.long 0x0 16. "LCKK,LCKK" "0,1" bitfld.long 0x0 15. "LCK15,LCK15" "0,1" bitfld.long 0x0 14. "LCK14,LCK14" "0,1" bitfld.long 0x0 13. "LCK13,LCK13" "0,1" bitfld.long 0x0 12. "LCK12,LCK12" "0,1" bitfld.long 0x0 11. "LCK11,LCK11" "0,1" bitfld.long 0x0 10. "LCK10,LCK10" "0,1" newline bitfld.long 0x0 9. "LCK9,LCK9" "0,1" bitfld.long 0x0 8. "LCK8,LCK8" "0,1" bitfld.long 0x0 7. "LCK7,LCK7" "0,1" bitfld.long 0x0 6. "LCK6,LCK6" "0,1" bitfld.long 0x0 5. "LCK5,LCK5" "0,1" bitfld.long 0x0 4. "LCK4,LCK4" "0,1" bitfld.long 0x0 3. "LCK3,LCK3" "0,1" newline bitfld.long 0x0 2. "LCK2,LCK2" "0,1" bitfld.long 0x0 1. "LCK1,LCK1" "0,1" bitfld.long 0x0 0. "LCK0,LCK0" "0,1" line.long 0x4 "GPIOA_AFRL,GPIO alternate function low register" hexmask.long.byte 0x4 28.--31. 1. "AFR7,AFR7" hexmask.long.byte 0x4 24.--27. 1. "AFR6,AFR6" hexmask.long.byte 0x4 20.--23. 1. "AFR5,AFR5" hexmask.long.byte 0x4 16.--19. 1. "AFR4,AFR4" hexmask.long.byte 0x4 12.--15. 1. "AFR3,AFR3" hexmask.long.byte 0x4 8.--11. 1. "AFR2,AFR2" hexmask.long.byte 0x4 4.--7. 1. "AFR1,AFR1" newline hexmask.long.byte 0x4 0.--3. 1. "AFR0,AFR0" line.long 0x8 "GPIOA_AFRH,GPIO alternate function high register" hexmask.long.byte 0x8 28.--31. 1. "AFR15,AFR15" hexmask.long.byte 0x8 24.--27. 1. "AFR14,AFR14" hexmask.long.byte 0x8 20.--23. 1. "AFR13,AFR13" hexmask.long.byte 0x8 16.--19. 1. "AFR12,AFR12" hexmask.long.byte 0x8 12.--15. 1. "AFR11,AFR11" hexmask.long.byte 0x8 8.--11. 1. "AFR10,AFR10" hexmask.long.byte 0x8 4.--7. 1. "AFR9,AFR9" newline hexmask.long.byte 0x8 0.--3. 1. "AFR8,AFR8" wgroup.long 0x28++0x3 line.long 0x0 "GPIOA_BRR,GPIO port bit reset register" bitfld.long 0x0 15. "BR15,BR15" "0,1" bitfld.long 0x0 14. "BR14,BR14" "0,1" bitfld.long 0x0 13. "BR13,BR13" "0,1" bitfld.long 0x0 12. "BR12,BR12" "0,1" bitfld.long 0x0 11. "BR11,BR11" "0,1" bitfld.long 0x0 10. "BR10,BR10" "0,1" bitfld.long 0x0 9. "BR9,BR9" "0,1" newline bitfld.long 0x0 8. "BR8,BR8" "0,1" bitfld.long 0x0 7. "BR7,BR7" "0,1" bitfld.long 0x0 6. "BR6,BR6" "0,1" bitfld.long 0x0 5. "BR5,BR5" "0,1" bitfld.long 0x0 4. "BR4,BR4" "0,1" bitfld.long 0x0 3. "BR3,BR3" "0,1" bitfld.long 0x0 2. "BR2,BR2" "0,1" newline bitfld.long 0x0 1. "BR1,BR1" "0,1" bitfld.long 0x0 0. "BR0,BR0" "0,1" rgroup.long 0x3C8++0x37 line.long 0x0 "GPIOA_HWCFGR10,For GPIOA. B. C. D. E. F. G. H. I. J and GPIOK: For GPIOZ:" hexmask.long.byte 0x0 20.--23. 1. "OR_CFG,OR_CFG" hexmask.long.byte 0x0 16.--19. 1. "SEC_CFG,SEC_CFG" hexmask.long.byte 0x0 12.--15. 1. "LOCK_CFG,LOCK_CFG" hexmask.long.byte 0x0 8.--11. 1. "SPEED_CFG,SPEED_CFG" hexmask.long.byte 0x0 4.--7. 1. "AF_SIZE,AF_SIZE" hexmask.long.byte 0x0 0.--3. 1. "AHB_IOP,AHB_IOP" line.long 0x4 "GPIOA_HWCFGR9,For GPIOA. B. C. D. E. F. G. H. I. and GPIOJ: For GPIOK and GPIOZ:" hexmask.long.word 0x4 0.--15. 1. "EN_IO,EN_IO" line.long 0x8 "GPIOA_HWCFGR8,For GPIOA. B. C. D. E. F. G. H. I. and GPIOJ: For GPIOK and GPIOZ:" hexmask.long.byte 0x8 28.--31. 1. "AF_PRIO15,AF_PRIO15" hexmask.long.byte 0x8 24.--27. 1. "AF_PRIO14,AF_PRIO14" hexmask.long.byte 0x8 20.--23. 1. "AF_PRIO13,AF_PRIO13" hexmask.long.byte 0x8 16.--19. 1. "AF_PRIO12,AF_PRIO12" hexmask.long.byte 0x8 12.--15. 1. "AF_PRIO11,AF_PRIO11" hexmask.long.byte 0x8 8.--11. 1. "AF_PRIO10,AF_PRIO10" hexmask.long.byte 0x8 4.--7. 1. "AF_PRIO9,AF_PRIO9" newline hexmask.long.byte 0x8 0.--3. 1. "AF_PRIO8,AF_PRIO8" line.long 0xC "GPIOA_HWCFGR7,GPIO hardware configuration register 7" hexmask.long.byte 0xC 28.--31. 1. "AF_PRIO7,AF_PRIO7" hexmask.long.byte 0xC 24.--27. 1. "AF_PRIO6,AF_PRIO6" hexmask.long.byte 0xC 20.--23. 1. "AF_PRIO5,AF_PRIO5" hexmask.long.byte 0xC 16.--19. 1. "AF_PRIO4,AF_PRIO4" hexmask.long.byte 0xC 12.--15. 1. "AF_PRIO3,AF_PRIO3" hexmask.long.byte 0xC 8.--11. 1. "AF_PRIO2,AF_PRIO2" hexmask.long.byte 0xC 4.--7. 1. "AF_PRIO1,AF_PRIO1" newline hexmask.long.byte 0xC 0.--3. 1. "AF_PRIO0,AF_PRIO0" line.long 0x10 "GPIOA_HWCFGR6,GPIO hardware configuration register 6" hexmask.long 0x10 0.--31. 1. "MODER_RES,MODER_RES" line.long 0x14 "GPIOA_HWCFGR5,GPIO hardware configuration register 5" hexmask.long 0x14 0.--31. 1. "PUPDR_RES,PUPDR_RES" line.long 0x18 "GPIOA_HWCFGR4,GPIO hardware configuration register 4" hexmask.long 0x18 0.--31. 1. "OSPEED_RES,OSPEED_RES" line.long 0x1C "GPIOA_HWCFGR3,GPIO hardware configuration register 3" hexmask.long.word 0x1C 16.--31. 1. "OTYPER_RES,OTYPER_RES" hexmask.long.word 0x1C 0.--15. 1. "ODR_RES,ODR_RES" line.long 0x20 "GPIOA_HWCFGR2,GPIO hardware configuration register 2" hexmask.long 0x20 0.--31. 1. "AFRL_RES,AFRL_RES" line.long 0x24 "GPIOA_HWCFGR1,GPIO hardware configuration register 1" hexmask.long 0x24 0.--31. 1. "AFRH_RES,AFRH_RES" line.long 0x28 "GPIOA_HWCFGR0,GPIO hardware configuration register 0" hexmask.long.word 0x28 0.--15. 1. "OR_RES,OR_RES" line.long 0x2C "GPIOA_VERR,GPIO version register" hexmask.long.byte 0x2C 4.--7. 1. "MAJREV,MAJREV" hexmask.long.byte 0x2C 0.--3. 1. "MINREV,MINREV" line.long 0x30 "GPIOA_IPIDR,GPIO identification register" hexmask.long 0x30 0.--31. 1. "IPIDR,IPIDR" line.long 0x34 "GPIOA_SIDR,GPIO size identification register" hexmask.long 0x34 0.--31. 1. "SIDR,SIDR" tree.end endif sif (cpuis("STM32MP151*")||cpuis("STM32MP153*")||cpuis("STM32MP157*")) tree "GPIOB" base ad:0x50003000 group.long 0x0++0xF line.long 0x0 "GPIOB_MODER,GPIO port mode register" bitfld.long 0x0 30.--31. "MODER15,MODER15" "0,1,2,3" bitfld.long 0x0 28.--29. "MODER14,MODER14" "0,1,2,3" bitfld.long 0x0 26.--27. "MODER13,MODER13" "0,1,2,3" bitfld.long 0x0 24.--25. "MODER12,MODER12" "0,1,2,3" bitfld.long 0x0 22.--23. "MODER11,MODER11" "0,1,2,3" bitfld.long 0x0 20.--21. "MODER10,MODER10" "0,1,2,3" bitfld.long 0x0 18.--19. "MODER9,MODER9" "0,1,2,3" newline bitfld.long 0x0 16.--17. "MODER8,MODER8" "0,1,2,3" bitfld.long 0x0 14.--15. "MODER7,MODER7" "0,1,2,3" bitfld.long 0x0 12.--13. "MODER6,MODER6" "0,1,2,3" bitfld.long 0x0 10.--11. "MODER5,MODER5" "0,1,2,3" bitfld.long 0x0 8.--9. "MODER4,MODER4" "0,1,2,3" bitfld.long 0x0 6.--7. "MODER3,MODER3" "0,1,2,3" bitfld.long 0x0 4.--5. "MODER2,MODER2" "0,1,2,3" newline bitfld.long 0x0 2.--3. "MODER1,MODER1" "0,1,2,3" bitfld.long 0x0 0.--1. "MODER0,MODER0" "0,1,2,3" line.long 0x4 "GPIOB_OTYPER,GPIO port output type register" bitfld.long 0x4 15. "OT15,OT15" "0,1" bitfld.long 0x4 14. "OT14,OT14" "0,1" bitfld.long 0x4 13. "OT13,OT13" "0,1" bitfld.long 0x4 12. "OT12,OT12" "0,1" bitfld.long 0x4 11. "OT11,OT11" "0,1" bitfld.long 0x4 10. "OT10,OT10" "0,1" bitfld.long 0x4 9. "OT9,OT9" "0,1" newline bitfld.long 0x4 8. "OT8,OT8" "0,1" bitfld.long 0x4 7. "OT7,OT7" "0,1" bitfld.long 0x4 6. "OT6,OT6" "0,1" bitfld.long 0x4 5. "OT5,OT5" "0,1" bitfld.long 0x4 4. "OT4,OT4" "0,1" bitfld.long 0x4 3. "OT3,OT3" "0,1" bitfld.long 0x4 2. "OT2,OT2" "0,1" newline bitfld.long 0x4 1. "OT1,OT1" "0,1" bitfld.long 0x4 0. "OT0,OT0" "0,1" line.long 0x8 "GPIOB_OSPEEDR,GPIO port output speed register" bitfld.long 0x8 30.--31. "OSPEEDR15,OSPEEDR15" "0,1,2,3" bitfld.long 0x8 28.--29. "OSPEEDR14,OSPEEDR14" "0,1,2,3" bitfld.long 0x8 26.--27. "OSPEEDR13,OSPEEDR13" "0,1,2,3" bitfld.long 0x8 24.--25. "OSPEEDR12,OSPEEDR12" "0,1,2,3" bitfld.long 0x8 22.--23. "OSPEEDR11,OSPEEDR11" "0,1,2,3" bitfld.long 0x8 20.--21. "OSPEEDR10,OSPEEDR10" "0,1,2,3" bitfld.long 0x8 18.--19. "OSPEEDR9,OSPEEDR9" "0,1,2,3" newline bitfld.long 0x8 16.--17. "OSPEEDR8,OSPEEDR8" "0,1,2,3" bitfld.long 0x8 14.--15. "OSPEEDR7,OSPEEDR7" "0,1,2,3" bitfld.long 0x8 12.--13. "OSPEEDR6,OSPEEDR6" "0,1,2,3" bitfld.long 0x8 10.--11. "OSPEEDR5,OSPEEDR5" "0,1,2,3" bitfld.long 0x8 8.--9. "OSPEEDR4,OSPEEDR4" "0,1,2,3" bitfld.long 0x8 6.--7. "OSPEEDR3,OSPEEDR3" "0,1,2,3" bitfld.long 0x8 4.--5. "OSPEEDR2,OSPEEDR2" "0,1,2,3" newline bitfld.long 0x8 2.--3. "OSPEEDR1,OSPEEDR1" "0,1,2,3" bitfld.long 0x8 0.--1. "OSPEEDR0,OSPEEDR0" "0,1,2,3" line.long 0xC "GPIOB_PUPDR,GPIO port pull-up/pull-down register" bitfld.long 0xC 30.--31. "PUPDR15,PUPDR15" "0,1,2,3" bitfld.long 0xC 28.--29. "PUPDR14,PUPDR14" "0,1,2,3" bitfld.long 0xC 26.--27. "PUPDR13,PUPDR13" "0,1,2,3" bitfld.long 0xC 24.--25. "PUPDR12,PUPDR12" "0,1,2,3" bitfld.long 0xC 22.--23. "PUPDR11,PUPDR11" "0,1,2,3" bitfld.long 0xC 20.--21. "PUPDR10,PUPDR10" "0,1,2,3" bitfld.long 0xC 18.--19. "PUPDR9,PUPDR9" "0,1,2,3" newline bitfld.long 0xC 16.--17. "PUPDR8,PUPDR8" "0,1,2,3" bitfld.long 0xC 14.--15. "PUPDR7,PUPDR7" "0,1,2,3" bitfld.long 0xC 12.--13. "PUPDR6,PUPDR6" "0,1,2,3" bitfld.long 0xC 10.--11. "PUPDR5,PUPDR5" "0,1,2,3" bitfld.long 0xC 8.--9. "PUPDR4,PUPDR4" "0,1,2,3" bitfld.long 0xC 6.--7. "PUPDR3,PUPDR3" "0,1,2,3" bitfld.long 0xC 4.--5. "PUPDR2,PUPDR2" "0,1,2,3" newline bitfld.long 0xC 2.--3. "PUPDR1,PUPDR1" "0,1,2,3" bitfld.long 0xC 0.--1. "PUPDR0,PUPDR0" "0,1,2,3" rgroup.long 0x10++0x3 line.long 0x0 "GPIOB_IDR,GPIO port input data register" bitfld.long 0x0 15. "IDR15,IDR15" "0,1" bitfld.long 0x0 14. "IDR14,IDR14" "0,1" bitfld.long 0x0 13. "IDR13,IDR13" "0,1" bitfld.long 0x0 12. "IDR12,IDR12" "0,1" bitfld.long 0x0 11. "IDR11,IDR11" "0,1" bitfld.long 0x0 10. "IDR10,IDR10" "0,1" bitfld.long 0x0 9. "IDR9,IDR9" "0,1" newline bitfld.long 0x0 8. "IDR8,IDR8" "0,1" bitfld.long 0x0 7. "IDR7,IDR7" "0,1" bitfld.long 0x0 6. "IDR6,IDR6" "0,1" bitfld.long 0x0 5. "IDR5,IDR5" "0,1" bitfld.long 0x0 4. "IDR4,IDR4" "0,1" bitfld.long 0x0 3. "IDR3,IDR3" "0,1" bitfld.long 0x0 2. "IDR2,IDR2" "0,1" newline bitfld.long 0x0 1. "IDR1,IDR1" "0,1" bitfld.long 0x0 0. "IDR0,IDR0" "0,1" group.long 0x14++0x3 line.long 0x0 "GPIOB_ODR,GPIO port output data register" bitfld.long 0x0 15. "ODR15,ODR15" "0,1" bitfld.long 0x0 14. "ODR14,ODR14" "0,1" bitfld.long 0x0 13. "ODR13,ODR13" "0,1" bitfld.long 0x0 12. "ODR12,ODR12" "0,1" bitfld.long 0x0 11. "ODR11,ODR11" "0,1" bitfld.long 0x0 10. "ODR10,ODR10" "0,1" bitfld.long 0x0 9. "ODR9,ODR9" "0,1" newline bitfld.long 0x0 8. "ODR8,ODR8" "0,1" bitfld.long 0x0 7. "ODR7,ODR7" "0,1" bitfld.long 0x0 6. "ODR6,ODR6" "0,1" bitfld.long 0x0 5. "ODR5,ODR5" "0,1" bitfld.long 0x0 4. "ODR4,ODR4" "0,1" bitfld.long 0x0 3. "ODR3,ODR3" "0,1" bitfld.long 0x0 2. "ODR2,ODR2" "0,1" newline bitfld.long 0x0 1. "ODR1,ODR1" "0,1" bitfld.long 0x0 0. "ODR0,ODR0" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "GPIOB_BSRR,GPIO port bit set/reset register" bitfld.long 0x0 31. "BR15,BR15" "0,1" bitfld.long 0x0 30. "BR14,BR14" "0,1" bitfld.long 0x0 29. "BR13,BR13" "0,1" bitfld.long 0x0 28. "BR12,BR12" "0,1" bitfld.long 0x0 27. "BR11,BR11" "0,1" bitfld.long 0x0 26. "BR10,BR10" "0,1" bitfld.long 0x0 25. "BR9,BR9" "0,1" newline bitfld.long 0x0 24. "BR8,BR8" "0,1" bitfld.long 0x0 23. "BR7,BR7" "0,1" bitfld.long 0x0 22. "BR6,BR6" "0,1" bitfld.long 0x0 21. "BR5,BR5" "0,1" bitfld.long 0x0 20. "BR4,BR4" "0,1" bitfld.long 0x0 19. "BR3,BR3" "0,1" bitfld.long 0x0 18. "BR2,BR2" "0,1" newline bitfld.long 0x0 17. "BR1,BR1" "0,1" bitfld.long 0x0 16. "BR0,BR0" "0,1" bitfld.long 0x0 15. "BS15,BS15" "0,1" bitfld.long 0x0 14. "BS14,BS14" "0,1" bitfld.long 0x0 13. "BS13,BS13" "0,1" bitfld.long 0x0 12. "BS12,BS12" "0,1" bitfld.long 0x0 11. "BS11,BS11" "0,1" newline bitfld.long 0x0 10. "BS10,BS10" "0,1" bitfld.long 0x0 9. "BS9,BS9" "0,1" bitfld.long 0x0 8. "BS8,BS8" "0,1" bitfld.long 0x0 7. "BS7,BS7" "0,1" bitfld.long 0x0 6. "BS6,BS6" "0,1" bitfld.long 0x0 5. "BS5,BS5" "0,1" bitfld.long 0x0 4. "BS4,BS4" "0,1" newline bitfld.long 0x0 3. "BS3,BS3" "0,1" bitfld.long 0x0 2. "BS2,BS2" "0,1" bitfld.long 0x0 1. "BS1,BS1" "0,1" bitfld.long 0x0 0. "BS0,BS0" "0,1" group.long 0x1C++0xB line.long 0x0 "GPIOB_LCKR,This register is used to lock the configuration of the port bits when a correct write sequence is applied to bit 16 (LCKK). The value of bits [15:0] is used to lock the configuration of the GPIO. During the write sequence. the value of.." bitfld.long 0x0 16. "LCKK,LCKK" "0,1" bitfld.long 0x0 15. "LCK15,LCK15" "0,1" bitfld.long 0x0 14. "LCK14,LCK14" "0,1" bitfld.long 0x0 13. "LCK13,LCK13" "0,1" bitfld.long 0x0 12. "LCK12,LCK12" "0,1" bitfld.long 0x0 11. "LCK11,LCK11" "0,1" bitfld.long 0x0 10. "LCK10,LCK10" "0,1" newline bitfld.long 0x0 9. "LCK9,LCK9" "0,1" bitfld.long 0x0 8. "LCK8,LCK8" "0,1" bitfld.long 0x0 7. "LCK7,LCK7" "0,1" bitfld.long 0x0 6. "LCK6,LCK6" "0,1" bitfld.long 0x0 5. "LCK5,LCK5" "0,1" bitfld.long 0x0 4. "LCK4,LCK4" "0,1" bitfld.long 0x0 3. "LCK3,LCK3" "0,1" newline bitfld.long 0x0 2. "LCK2,LCK2" "0,1" bitfld.long 0x0 1. "LCK1,LCK1" "0,1" bitfld.long 0x0 0. "LCK0,LCK0" "0,1" line.long 0x4 "GPIOB_AFRL,GPIO alternate function low register" hexmask.long.byte 0x4 28.--31. 1. "AFR7,AFR7" hexmask.long.byte 0x4 24.--27. 1. "AFR6,AFR6" hexmask.long.byte 0x4 20.--23. 1. "AFR5,AFR5" hexmask.long.byte 0x4 16.--19. 1. "AFR4,AFR4" hexmask.long.byte 0x4 12.--15. 1. "AFR3,AFR3" hexmask.long.byte 0x4 8.--11. 1. "AFR2,AFR2" hexmask.long.byte 0x4 4.--7. 1. "AFR1,AFR1" newline hexmask.long.byte 0x4 0.--3. 1. "AFR0,AFR0" line.long 0x8 "GPIOB_AFRH,GPIO alternate function high register" hexmask.long.byte 0x8 28.--31. 1. "AFR15,AFR15" hexmask.long.byte 0x8 24.--27. 1. "AFR14,AFR14" hexmask.long.byte 0x8 20.--23. 1. "AFR13,AFR13" hexmask.long.byte 0x8 16.--19. 1. "AFR12,AFR12" hexmask.long.byte 0x8 12.--15. 1. "AFR11,AFR11" hexmask.long.byte 0x8 8.--11. 1. "AFR10,AFR10" hexmask.long.byte 0x8 4.--7. 1. "AFR9,AFR9" newline hexmask.long.byte 0x8 0.--3. 1. "AFR8,AFR8" wgroup.long 0x28++0x3 line.long 0x0 "GPIOB_BRR,GPIO port bit reset register" bitfld.long 0x0 15. "BR15,BR15" "0,1" bitfld.long 0x0 14. "BR14,BR14" "0,1" bitfld.long 0x0 13. "BR13,BR13" "0,1" bitfld.long 0x0 12. "BR12,BR12" "0,1" bitfld.long 0x0 11. "BR11,BR11" "0,1" bitfld.long 0x0 10. "BR10,BR10" "0,1" bitfld.long 0x0 9. "BR9,BR9" "0,1" newline bitfld.long 0x0 8. "BR8,BR8" "0,1" bitfld.long 0x0 7. "BR7,BR7" "0,1" bitfld.long 0x0 6. "BR6,BR6" "0,1" bitfld.long 0x0 5. "BR5,BR5" "0,1" bitfld.long 0x0 4. "BR4,BR4" "0,1" bitfld.long 0x0 3. "BR3,BR3" "0,1" bitfld.long 0x0 2. "BR2,BR2" "0,1" newline bitfld.long 0x0 1. "BR1,BR1" "0,1" bitfld.long 0x0 0. "BR0,BR0" "0,1" rgroup.long 0x3C8++0x37 line.long 0x0 "GPIOB_HWCFGR10,For GPIOA. B. C. D. E. F. G. H. I. J and GPIOK: For GPIOZ:" hexmask.long.byte 0x0 20.--23. 1. "OR_CFG,OR_CFG" hexmask.long.byte 0x0 16.--19. 1. "SEC_CFG,SEC_CFG" hexmask.long.byte 0x0 12.--15. 1. "LOCK_CFG,LOCK_CFG" hexmask.long.byte 0x0 8.--11. 1. "SPEED_CFG,SPEED_CFG" hexmask.long.byte 0x0 4.--7. 1. "AF_SIZE,AF_SIZE" hexmask.long.byte 0x0 0.--3. 1. "AHB_IOP,AHB_IOP" line.long 0x4 "GPIOB_HWCFGR9,For GPIOA. B. C. D. E. F. G. H. I. and GPIOJ: For GPIOK and GPIOZ:" hexmask.long.word 0x4 0.--15. 1. "EN_IO,EN_IO" line.long 0x8 "GPIOB_HWCFGR8,For GPIOA. B. C. D. E. F. G. H. I. and GPIOJ: For GPIOK and GPIOZ:" hexmask.long.byte 0x8 28.--31. 1. "AF_PRIO15,AF_PRIO15" hexmask.long.byte 0x8 24.--27. 1. "AF_PRIO14,AF_PRIO14" hexmask.long.byte 0x8 20.--23. 1. "AF_PRIO13,AF_PRIO13" hexmask.long.byte 0x8 16.--19. 1. "AF_PRIO12,AF_PRIO12" hexmask.long.byte 0x8 12.--15. 1. "AF_PRIO11,AF_PRIO11" hexmask.long.byte 0x8 8.--11. 1. "AF_PRIO10,AF_PRIO10" hexmask.long.byte 0x8 4.--7. 1. "AF_PRIO9,AF_PRIO9" newline hexmask.long.byte 0x8 0.--3. 1. "AF_PRIO8,AF_PRIO8" line.long 0xC "GPIOB_HWCFGR7,GPIO hardware configuration register 7" hexmask.long.byte 0xC 28.--31. 1. "AF_PRIO7,AF_PRIO7" hexmask.long.byte 0xC 24.--27. 1. "AF_PRIO6,AF_PRIO6" hexmask.long.byte 0xC 20.--23. 1. "AF_PRIO5,AF_PRIO5" hexmask.long.byte 0xC 16.--19. 1. "AF_PRIO4,AF_PRIO4" hexmask.long.byte 0xC 12.--15. 1. "AF_PRIO3,AF_PRIO3" hexmask.long.byte 0xC 8.--11. 1. "AF_PRIO2,AF_PRIO2" hexmask.long.byte 0xC 4.--7. 1. "AF_PRIO1,AF_PRIO1" newline hexmask.long.byte 0xC 0.--3. 1. "AF_PRIO0,AF_PRIO0" line.long 0x10 "GPIOB_HWCFGR6,GPIO hardware configuration register 6" hexmask.long 0x10 0.--31. 1. "MODER_RES,MODER_RES" line.long 0x14 "GPIOB_HWCFGR5,GPIO hardware configuration register 5" hexmask.long 0x14 0.--31. 1. "PUPDR_RES,PUPDR_RES" line.long 0x18 "GPIOB_HWCFGR4,GPIO hardware configuration register 4" hexmask.long 0x18 0.--31. 1. "OSPEED_RES,OSPEED_RES" line.long 0x1C "GPIOB_HWCFGR3,GPIO hardware configuration register 3" hexmask.long.word 0x1C 16.--31. 1. "OTYPER_RES,OTYPER_RES" hexmask.long.word 0x1C 0.--15. 1. "ODR_RES,ODR_RES" line.long 0x20 "GPIOB_HWCFGR2,GPIO hardware configuration register 2" hexmask.long 0x20 0.--31. 1. "AFRL_RES,AFRL_RES" line.long 0x24 "GPIOB_HWCFGR1,GPIO hardware configuration register 1" hexmask.long 0x24 0.--31. 1. "AFRH_RES,AFRH_RES" line.long 0x28 "GPIOB_HWCFGR0,GPIO hardware configuration register 0" hexmask.long.word 0x28 0.--15. 1. "OR_RES,OR_RES" line.long 0x2C "GPIOB_VERR,GPIO version register" hexmask.long.byte 0x2C 4.--7. 1. "MAJREV,MAJREV" hexmask.long.byte 0x2C 0.--3. 1. "MINREV,MINREV" line.long 0x30 "GPIOB_IPIDR,GPIO identification register" hexmask.long 0x30 0.--31. 1. "IPIDR,IPIDR" line.long 0x34 "GPIOB_SIDR,GPIO size identification register" hexmask.long 0x34 0.--31. 1. "SIDR,SIDR" tree.end endif sif (cpuis("STM32MP151*")||cpuis("STM32MP153*")||cpuis("STM32MP157*")) tree "GPIOC" base ad:0x50004000 group.long 0x0++0xF line.long 0x0 "GPIOC_MODER,GPIO port mode register" bitfld.long 0x0 30.--31. "MODER15,MODER15" "0,1,2,3" bitfld.long 0x0 28.--29. "MODER14,MODER14" "0,1,2,3" bitfld.long 0x0 26.--27. "MODER13,MODER13" "0,1,2,3" bitfld.long 0x0 24.--25. "MODER12,MODER12" "0,1,2,3" bitfld.long 0x0 22.--23. "MODER11,MODER11" "0,1,2,3" bitfld.long 0x0 20.--21. "MODER10,MODER10" "0,1,2,3" bitfld.long 0x0 18.--19. "MODER9,MODER9" "0,1,2,3" newline bitfld.long 0x0 16.--17. "MODER8,MODER8" "0,1,2,3" bitfld.long 0x0 14.--15. "MODER7,MODER7" "0,1,2,3" bitfld.long 0x0 12.--13. "MODER6,MODER6" "0,1,2,3" bitfld.long 0x0 10.--11. "MODER5,MODER5" "0,1,2,3" bitfld.long 0x0 8.--9. "MODER4,MODER4" "0,1,2,3" bitfld.long 0x0 6.--7. "MODER3,MODER3" "0,1,2,3" bitfld.long 0x0 4.--5. "MODER2,MODER2" "0,1,2,3" newline bitfld.long 0x0 2.--3. "MODER1,MODER1" "0,1,2,3" bitfld.long 0x0 0.--1. "MODER0,MODER0" "0,1,2,3" line.long 0x4 "GPIOC_OTYPER,GPIO port output type register" bitfld.long 0x4 15. "OT15,OT15" "0,1" bitfld.long 0x4 14. "OT14,OT14" "0,1" bitfld.long 0x4 13. "OT13,OT13" "0,1" bitfld.long 0x4 12. "OT12,OT12" "0,1" bitfld.long 0x4 11. "OT11,OT11" "0,1" bitfld.long 0x4 10. "OT10,OT10" "0,1" bitfld.long 0x4 9. "OT9,OT9" "0,1" newline bitfld.long 0x4 8. "OT8,OT8" "0,1" bitfld.long 0x4 7. "OT7,OT7" "0,1" bitfld.long 0x4 6. "OT6,OT6" "0,1" bitfld.long 0x4 5. "OT5,OT5" "0,1" bitfld.long 0x4 4. "OT4,OT4" "0,1" bitfld.long 0x4 3. "OT3,OT3" "0,1" bitfld.long 0x4 2. "OT2,OT2" "0,1" newline bitfld.long 0x4 1. "OT1,OT1" "0,1" bitfld.long 0x4 0. "OT0,OT0" "0,1" line.long 0x8 "GPIOC_OSPEEDR,GPIO port output speed register" bitfld.long 0x8 30.--31. "OSPEEDR15,OSPEEDR15" "0,1,2,3" bitfld.long 0x8 28.--29. "OSPEEDR14,OSPEEDR14" "0,1,2,3" bitfld.long 0x8 26.--27. "OSPEEDR13,OSPEEDR13" "0,1,2,3" bitfld.long 0x8 24.--25. "OSPEEDR12,OSPEEDR12" "0,1,2,3" bitfld.long 0x8 22.--23. "OSPEEDR11,OSPEEDR11" "0,1,2,3" bitfld.long 0x8 20.--21. "OSPEEDR10,OSPEEDR10" "0,1,2,3" bitfld.long 0x8 18.--19. "OSPEEDR9,OSPEEDR9" "0,1,2,3" newline bitfld.long 0x8 16.--17. "OSPEEDR8,OSPEEDR8" "0,1,2,3" bitfld.long 0x8 14.--15. "OSPEEDR7,OSPEEDR7" "0,1,2,3" bitfld.long 0x8 12.--13. "OSPEEDR6,OSPEEDR6" "0,1,2,3" bitfld.long 0x8 10.--11. "OSPEEDR5,OSPEEDR5" "0,1,2,3" bitfld.long 0x8 8.--9. "OSPEEDR4,OSPEEDR4" "0,1,2,3" bitfld.long 0x8 6.--7. "OSPEEDR3,OSPEEDR3" "0,1,2,3" bitfld.long 0x8 4.--5. "OSPEEDR2,OSPEEDR2" "0,1,2,3" newline bitfld.long 0x8 2.--3. "OSPEEDR1,OSPEEDR1" "0,1,2,3" bitfld.long 0x8 0.--1. "OSPEEDR0,OSPEEDR0" "0,1,2,3" line.long 0xC "GPIOC_PUPDR,GPIO port pull-up/pull-down register" bitfld.long 0xC 30.--31. "PUPDR15,PUPDR15" "0,1,2,3" bitfld.long 0xC 28.--29. "PUPDR14,PUPDR14" "0,1,2,3" bitfld.long 0xC 26.--27. "PUPDR13,PUPDR13" "0,1,2,3" bitfld.long 0xC 24.--25. "PUPDR12,PUPDR12" "0,1,2,3" bitfld.long 0xC 22.--23. "PUPDR11,PUPDR11" "0,1,2,3" bitfld.long 0xC 20.--21. "PUPDR10,PUPDR10" "0,1,2,3" bitfld.long 0xC 18.--19. "PUPDR9,PUPDR9" "0,1,2,3" newline bitfld.long 0xC 16.--17. "PUPDR8,PUPDR8" "0,1,2,3" bitfld.long 0xC 14.--15. "PUPDR7,PUPDR7" "0,1,2,3" bitfld.long 0xC 12.--13. "PUPDR6,PUPDR6" "0,1,2,3" bitfld.long 0xC 10.--11. "PUPDR5,PUPDR5" "0,1,2,3" bitfld.long 0xC 8.--9. "PUPDR4,PUPDR4" "0,1,2,3" bitfld.long 0xC 6.--7. "PUPDR3,PUPDR3" "0,1,2,3" bitfld.long 0xC 4.--5. "PUPDR2,PUPDR2" "0,1,2,3" newline bitfld.long 0xC 2.--3. "PUPDR1,PUPDR1" "0,1,2,3" bitfld.long 0xC 0.--1. "PUPDR0,PUPDR0" "0,1,2,3" rgroup.long 0x10++0x3 line.long 0x0 "GPIOC_IDR,GPIO port input data register" bitfld.long 0x0 15. "IDR15,IDR15" "0,1" bitfld.long 0x0 14. "IDR14,IDR14" "0,1" bitfld.long 0x0 13. "IDR13,IDR13" "0,1" bitfld.long 0x0 12. "IDR12,IDR12" "0,1" bitfld.long 0x0 11. "IDR11,IDR11" "0,1" bitfld.long 0x0 10. "IDR10,IDR10" "0,1" bitfld.long 0x0 9. "IDR9,IDR9" "0,1" newline bitfld.long 0x0 8. "IDR8,IDR8" "0,1" bitfld.long 0x0 7. "IDR7,IDR7" "0,1" bitfld.long 0x0 6. "IDR6,IDR6" "0,1" bitfld.long 0x0 5. "IDR5,IDR5" "0,1" bitfld.long 0x0 4. "IDR4,IDR4" "0,1" bitfld.long 0x0 3. "IDR3,IDR3" "0,1" bitfld.long 0x0 2. "IDR2,IDR2" "0,1" newline bitfld.long 0x0 1. "IDR1,IDR1" "0,1" bitfld.long 0x0 0. "IDR0,IDR0" "0,1" group.long 0x14++0x3 line.long 0x0 "GPIOC_ODR,GPIO port output data register" bitfld.long 0x0 15. "ODR15,ODR15" "0,1" bitfld.long 0x0 14. "ODR14,ODR14" "0,1" bitfld.long 0x0 13. "ODR13,ODR13" "0,1" bitfld.long 0x0 12. "ODR12,ODR12" "0,1" bitfld.long 0x0 11. "ODR11,ODR11" "0,1" bitfld.long 0x0 10. "ODR10,ODR10" "0,1" bitfld.long 0x0 9. "ODR9,ODR9" "0,1" newline bitfld.long 0x0 8. "ODR8,ODR8" "0,1" bitfld.long 0x0 7. "ODR7,ODR7" "0,1" bitfld.long 0x0 6. "ODR6,ODR6" "0,1" bitfld.long 0x0 5. "ODR5,ODR5" "0,1" bitfld.long 0x0 4. "ODR4,ODR4" "0,1" bitfld.long 0x0 3. "ODR3,ODR3" "0,1" bitfld.long 0x0 2. "ODR2,ODR2" "0,1" newline bitfld.long 0x0 1. "ODR1,ODR1" "0,1" bitfld.long 0x0 0. "ODR0,ODR0" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "GPIOC_BSRR,GPIO port bit set/reset register" bitfld.long 0x0 31. "BR15,BR15" "0,1" bitfld.long 0x0 30. "BR14,BR14" "0,1" bitfld.long 0x0 29. "BR13,BR13" "0,1" bitfld.long 0x0 28. "BR12,BR12" "0,1" bitfld.long 0x0 27. "BR11,BR11" "0,1" bitfld.long 0x0 26. "BR10,BR10" "0,1" bitfld.long 0x0 25. "BR9,BR9" "0,1" newline bitfld.long 0x0 24. "BR8,BR8" "0,1" bitfld.long 0x0 23. "BR7,BR7" "0,1" bitfld.long 0x0 22. "BR6,BR6" "0,1" bitfld.long 0x0 21. "BR5,BR5" "0,1" bitfld.long 0x0 20. "BR4,BR4" "0,1" bitfld.long 0x0 19. "BR3,BR3" "0,1" bitfld.long 0x0 18. "BR2,BR2" "0,1" newline bitfld.long 0x0 17. "BR1,BR1" "0,1" bitfld.long 0x0 16. "BR0,BR0" "0,1" bitfld.long 0x0 15. "BS15,BS15" "0,1" bitfld.long 0x0 14. "BS14,BS14" "0,1" bitfld.long 0x0 13. "BS13,BS13" "0,1" bitfld.long 0x0 12. "BS12,BS12" "0,1" bitfld.long 0x0 11. "BS11,BS11" "0,1" newline bitfld.long 0x0 10. "BS10,BS10" "0,1" bitfld.long 0x0 9. "BS9,BS9" "0,1" bitfld.long 0x0 8. "BS8,BS8" "0,1" bitfld.long 0x0 7. "BS7,BS7" "0,1" bitfld.long 0x0 6. "BS6,BS6" "0,1" bitfld.long 0x0 5. "BS5,BS5" "0,1" bitfld.long 0x0 4. "BS4,BS4" "0,1" newline bitfld.long 0x0 3. "BS3,BS3" "0,1" bitfld.long 0x0 2. "BS2,BS2" "0,1" bitfld.long 0x0 1. "BS1,BS1" "0,1" bitfld.long 0x0 0. "BS0,BS0" "0,1" group.long 0x1C++0xB line.long 0x0 "GPIOC_LCKR,This register is used to lock the configuration of the port bits when a correct write sequence is applied to bit 16 (LCKK). The value of bits [15:0] is used to lock the configuration of the GPIO. During the write sequence. the value of.." bitfld.long 0x0 16. "LCKK,LCKK" "0,1" bitfld.long 0x0 15. "LCK15,LCK15" "0,1" bitfld.long 0x0 14. "LCK14,LCK14" "0,1" bitfld.long 0x0 13. "LCK13,LCK13" "0,1" bitfld.long 0x0 12. "LCK12,LCK12" "0,1" bitfld.long 0x0 11. "LCK11,LCK11" "0,1" bitfld.long 0x0 10. "LCK10,LCK10" "0,1" newline bitfld.long 0x0 9. "LCK9,LCK9" "0,1" bitfld.long 0x0 8. "LCK8,LCK8" "0,1" bitfld.long 0x0 7. "LCK7,LCK7" "0,1" bitfld.long 0x0 6. "LCK6,LCK6" "0,1" bitfld.long 0x0 5. "LCK5,LCK5" "0,1" bitfld.long 0x0 4. "LCK4,LCK4" "0,1" bitfld.long 0x0 3. "LCK3,LCK3" "0,1" newline bitfld.long 0x0 2. "LCK2,LCK2" "0,1" bitfld.long 0x0 1. "LCK1,LCK1" "0,1" bitfld.long 0x0 0. "LCK0,LCK0" "0,1" line.long 0x4 "GPIOC_AFRL,GPIO alternate function low register" hexmask.long.byte 0x4 28.--31. 1. "AFR7,AFR7" hexmask.long.byte 0x4 24.--27. 1. "AFR6,AFR6" hexmask.long.byte 0x4 20.--23. 1. "AFR5,AFR5" hexmask.long.byte 0x4 16.--19. 1. "AFR4,AFR4" hexmask.long.byte 0x4 12.--15. 1. "AFR3,AFR3" hexmask.long.byte 0x4 8.--11. 1. "AFR2,AFR2" hexmask.long.byte 0x4 4.--7. 1. "AFR1,AFR1" newline hexmask.long.byte 0x4 0.--3. 1. "AFR0,AFR0" line.long 0x8 "GPIOC_AFRH,GPIO alternate function high register" hexmask.long.byte 0x8 28.--31. 1. "AFR15,AFR15" hexmask.long.byte 0x8 24.--27. 1. "AFR14,AFR14" hexmask.long.byte 0x8 20.--23. 1. "AFR13,AFR13" hexmask.long.byte 0x8 16.--19. 1. "AFR12,AFR12" hexmask.long.byte 0x8 12.--15. 1. "AFR11,AFR11" hexmask.long.byte 0x8 8.--11. 1. "AFR10,AFR10" hexmask.long.byte 0x8 4.--7. 1. "AFR9,AFR9" newline hexmask.long.byte 0x8 0.--3. 1. "AFR8,AFR8" wgroup.long 0x28++0x3 line.long 0x0 "GPIOC_BRR,GPIO port bit reset register" bitfld.long 0x0 15. "BR15,BR15" "0,1" bitfld.long 0x0 14. "BR14,BR14" "0,1" bitfld.long 0x0 13. "BR13,BR13" "0,1" bitfld.long 0x0 12. "BR12,BR12" "0,1" bitfld.long 0x0 11. "BR11,BR11" "0,1" bitfld.long 0x0 10. "BR10,BR10" "0,1" bitfld.long 0x0 9. "BR9,BR9" "0,1" newline bitfld.long 0x0 8. "BR8,BR8" "0,1" bitfld.long 0x0 7. "BR7,BR7" "0,1" bitfld.long 0x0 6. "BR6,BR6" "0,1" bitfld.long 0x0 5. "BR5,BR5" "0,1" bitfld.long 0x0 4. "BR4,BR4" "0,1" bitfld.long 0x0 3. "BR3,BR3" "0,1" bitfld.long 0x0 2. "BR2,BR2" "0,1" newline bitfld.long 0x0 1. "BR1,BR1" "0,1" bitfld.long 0x0 0. "BR0,BR0" "0,1" rgroup.long 0x3C8++0x37 line.long 0x0 "GPIOC_HWCFGR10,For GPIOA. B. C. D. E. F. G. H. I. J and GPIOK: For GPIOZ:" hexmask.long.byte 0x0 20.--23. 1. "OR_CFG,OR_CFG" hexmask.long.byte 0x0 16.--19. 1. "SEC_CFG,SEC_CFG" hexmask.long.byte 0x0 12.--15. 1. "LOCK_CFG,LOCK_CFG" hexmask.long.byte 0x0 8.--11. 1. "SPEED_CFG,SPEED_CFG" hexmask.long.byte 0x0 4.--7. 1. "AF_SIZE,AF_SIZE" hexmask.long.byte 0x0 0.--3. 1. "AHB_IOP,AHB_IOP" line.long 0x4 "GPIOC_HWCFGR9,For GPIOA. B. C. D. E. F. G. H. I. and GPIOJ: For GPIOK and GPIOZ:" hexmask.long.word 0x4 0.--15. 1. "EN_IO,EN_IO" line.long 0x8 "GPIOC_HWCFGR8,For GPIOA. B. C. D. E. F. G. H. I. and GPIOJ: For GPIOK and GPIOZ:" hexmask.long.byte 0x8 28.--31. 1. "AF_PRIO15,AF_PRIO15" hexmask.long.byte 0x8 24.--27. 1. "AF_PRIO14,AF_PRIO14" hexmask.long.byte 0x8 20.--23. 1. "AF_PRIO13,AF_PRIO13" hexmask.long.byte 0x8 16.--19. 1. "AF_PRIO12,AF_PRIO12" hexmask.long.byte 0x8 12.--15. 1. "AF_PRIO11,AF_PRIO11" hexmask.long.byte 0x8 8.--11. 1. "AF_PRIO10,AF_PRIO10" hexmask.long.byte 0x8 4.--7. 1. "AF_PRIO9,AF_PRIO9" newline hexmask.long.byte 0x8 0.--3. 1. "AF_PRIO8,AF_PRIO8" line.long 0xC "GPIOC_HWCFGR7,GPIO hardware configuration register 7" hexmask.long.byte 0xC 28.--31. 1. "AF_PRIO7,AF_PRIO7" hexmask.long.byte 0xC 24.--27. 1. "AF_PRIO6,AF_PRIO6" hexmask.long.byte 0xC 20.--23. 1. "AF_PRIO5,AF_PRIO5" hexmask.long.byte 0xC 16.--19. 1. "AF_PRIO4,AF_PRIO4" hexmask.long.byte 0xC 12.--15. 1. "AF_PRIO3,AF_PRIO3" hexmask.long.byte 0xC 8.--11. 1. "AF_PRIO2,AF_PRIO2" hexmask.long.byte 0xC 4.--7. 1. "AF_PRIO1,AF_PRIO1" newline hexmask.long.byte 0xC 0.--3. 1. "AF_PRIO0,AF_PRIO0" line.long 0x10 "GPIOC_HWCFGR6,GPIO hardware configuration register 6" hexmask.long 0x10 0.--31. 1. "MODER_RES,MODER_RES" line.long 0x14 "GPIOC_HWCFGR5,GPIO hardware configuration register 5" hexmask.long 0x14 0.--31. 1. "PUPDR_RES,PUPDR_RES" line.long 0x18 "GPIOC_HWCFGR4,GPIO hardware configuration register 4" hexmask.long 0x18 0.--31. 1. "OSPEED_RES,OSPEED_RES" line.long 0x1C "GPIOC_HWCFGR3,GPIO hardware configuration register 3" hexmask.long.word 0x1C 16.--31. 1. "OTYPER_RES,OTYPER_RES" hexmask.long.word 0x1C 0.--15. 1. "ODR_RES,ODR_RES" line.long 0x20 "GPIOC_HWCFGR2,GPIO hardware configuration register 2" hexmask.long 0x20 0.--31. 1. "AFRL_RES,AFRL_RES" line.long 0x24 "GPIOC_HWCFGR1,GPIO hardware configuration register 1" hexmask.long 0x24 0.--31. 1. "AFRH_RES,AFRH_RES" line.long 0x28 "GPIOC_HWCFGR0,GPIO hardware configuration register 0" hexmask.long.word 0x28 0.--15. 1. "OR_RES,OR_RES" line.long 0x2C "GPIOC_VERR,GPIO version register" hexmask.long.byte 0x2C 4.--7. 1. "MAJREV,MAJREV" hexmask.long.byte 0x2C 0.--3. 1. "MINREV,MINREV" line.long 0x30 "GPIOC_IPIDR,GPIO identification register" hexmask.long 0x30 0.--31. 1. "IPIDR,IPIDR" line.long 0x34 "GPIOC_SIDR,GPIO size identification register" hexmask.long 0x34 0.--31. 1. "SIDR,SIDR" tree.end endif sif (cpuis("STM32MP151*")||cpuis("STM32MP153*")||cpuis("STM32MP157*")) tree "GPIOD" base ad:0x50005000 group.long 0x0++0xF line.long 0x0 "GPIOD_MODER,GPIO port mode register" bitfld.long 0x0 30.--31. "MODER15,MODER15" "0,1,2,3" bitfld.long 0x0 28.--29. "MODER14,MODER14" "0,1,2,3" bitfld.long 0x0 26.--27. "MODER13,MODER13" "0,1,2,3" bitfld.long 0x0 24.--25. "MODER12,MODER12" "0,1,2,3" bitfld.long 0x0 22.--23. "MODER11,MODER11" "0,1,2,3" bitfld.long 0x0 20.--21. "MODER10,MODER10" "0,1,2,3" bitfld.long 0x0 18.--19. "MODER9,MODER9" "0,1,2,3" newline bitfld.long 0x0 16.--17. "MODER8,MODER8" "0,1,2,3" bitfld.long 0x0 14.--15. "MODER7,MODER7" "0,1,2,3" bitfld.long 0x0 12.--13. "MODER6,MODER6" "0,1,2,3" bitfld.long 0x0 10.--11. "MODER5,MODER5" "0,1,2,3" bitfld.long 0x0 8.--9. "MODER4,MODER4" "0,1,2,3" bitfld.long 0x0 6.--7. "MODER3,MODER3" "0,1,2,3" bitfld.long 0x0 4.--5. "MODER2,MODER2" "0,1,2,3" newline bitfld.long 0x0 2.--3. "MODER1,MODER1" "0,1,2,3" bitfld.long 0x0 0.--1. "MODER0,MODER0" "0,1,2,3" line.long 0x4 "GPIOD_OTYPER,GPIO port output type register" bitfld.long 0x4 15. "OT15,OT15" "0,1" bitfld.long 0x4 14. "OT14,OT14" "0,1" bitfld.long 0x4 13. "OT13,OT13" "0,1" bitfld.long 0x4 12. "OT12,OT12" "0,1" bitfld.long 0x4 11. "OT11,OT11" "0,1" bitfld.long 0x4 10. "OT10,OT10" "0,1" bitfld.long 0x4 9. "OT9,OT9" "0,1" newline bitfld.long 0x4 8. "OT8,OT8" "0,1" bitfld.long 0x4 7. "OT7,OT7" "0,1" bitfld.long 0x4 6. "OT6,OT6" "0,1" bitfld.long 0x4 5. "OT5,OT5" "0,1" bitfld.long 0x4 4. "OT4,OT4" "0,1" bitfld.long 0x4 3. "OT3,OT3" "0,1" bitfld.long 0x4 2. "OT2,OT2" "0,1" newline bitfld.long 0x4 1. "OT1,OT1" "0,1" bitfld.long 0x4 0. "OT0,OT0" "0,1" line.long 0x8 "GPIOD_OSPEEDR,GPIO port output speed register" bitfld.long 0x8 30.--31. "OSPEEDR15,OSPEEDR15" "0,1,2,3" bitfld.long 0x8 28.--29. "OSPEEDR14,OSPEEDR14" "0,1,2,3" bitfld.long 0x8 26.--27. "OSPEEDR13,OSPEEDR13" "0,1,2,3" bitfld.long 0x8 24.--25. "OSPEEDR12,OSPEEDR12" "0,1,2,3" bitfld.long 0x8 22.--23. "OSPEEDR11,OSPEEDR11" "0,1,2,3" bitfld.long 0x8 20.--21. "OSPEEDR10,OSPEEDR10" "0,1,2,3" bitfld.long 0x8 18.--19. "OSPEEDR9,OSPEEDR9" "0,1,2,3" newline bitfld.long 0x8 16.--17. "OSPEEDR8,OSPEEDR8" "0,1,2,3" bitfld.long 0x8 14.--15. "OSPEEDR7,OSPEEDR7" "0,1,2,3" bitfld.long 0x8 12.--13. "OSPEEDR6,OSPEEDR6" "0,1,2,3" bitfld.long 0x8 10.--11. "OSPEEDR5,OSPEEDR5" "0,1,2,3" bitfld.long 0x8 8.--9. "OSPEEDR4,OSPEEDR4" "0,1,2,3" bitfld.long 0x8 6.--7. "OSPEEDR3,OSPEEDR3" "0,1,2,3" bitfld.long 0x8 4.--5. "OSPEEDR2,OSPEEDR2" "0,1,2,3" newline bitfld.long 0x8 2.--3. "OSPEEDR1,OSPEEDR1" "0,1,2,3" bitfld.long 0x8 0.--1. "OSPEEDR0,OSPEEDR0" "0,1,2,3" line.long 0xC "GPIOD_PUPDR,GPIO port pull-up/pull-down register" bitfld.long 0xC 30.--31. "PUPDR15,PUPDR15" "0,1,2,3" bitfld.long 0xC 28.--29. "PUPDR14,PUPDR14" "0,1,2,3" bitfld.long 0xC 26.--27. "PUPDR13,PUPDR13" "0,1,2,3" bitfld.long 0xC 24.--25. "PUPDR12,PUPDR12" "0,1,2,3" bitfld.long 0xC 22.--23. "PUPDR11,PUPDR11" "0,1,2,3" bitfld.long 0xC 20.--21. "PUPDR10,PUPDR10" "0,1,2,3" bitfld.long 0xC 18.--19. "PUPDR9,PUPDR9" "0,1,2,3" newline bitfld.long 0xC 16.--17. "PUPDR8,PUPDR8" "0,1,2,3" bitfld.long 0xC 14.--15. "PUPDR7,PUPDR7" "0,1,2,3" bitfld.long 0xC 12.--13. "PUPDR6,PUPDR6" "0,1,2,3" bitfld.long 0xC 10.--11. "PUPDR5,PUPDR5" "0,1,2,3" bitfld.long 0xC 8.--9. "PUPDR4,PUPDR4" "0,1,2,3" bitfld.long 0xC 6.--7. "PUPDR3,PUPDR3" "0,1,2,3" bitfld.long 0xC 4.--5. "PUPDR2,PUPDR2" "0,1,2,3" newline bitfld.long 0xC 2.--3. "PUPDR1,PUPDR1" "0,1,2,3" bitfld.long 0xC 0.--1. "PUPDR0,PUPDR0" "0,1,2,3" rgroup.long 0x10++0x3 line.long 0x0 "GPIOD_IDR,GPIO port input data register" bitfld.long 0x0 15. "IDR15,IDR15" "0,1" bitfld.long 0x0 14. "IDR14,IDR14" "0,1" bitfld.long 0x0 13. "IDR13,IDR13" "0,1" bitfld.long 0x0 12. "IDR12,IDR12" "0,1" bitfld.long 0x0 11. "IDR11,IDR11" "0,1" bitfld.long 0x0 10. "IDR10,IDR10" "0,1" bitfld.long 0x0 9. "IDR9,IDR9" "0,1" newline bitfld.long 0x0 8. "IDR8,IDR8" "0,1" bitfld.long 0x0 7. "IDR7,IDR7" "0,1" bitfld.long 0x0 6. "IDR6,IDR6" "0,1" bitfld.long 0x0 5. "IDR5,IDR5" "0,1" bitfld.long 0x0 4. "IDR4,IDR4" "0,1" bitfld.long 0x0 3. "IDR3,IDR3" "0,1" bitfld.long 0x0 2. "IDR2,IDR2" "0,1" newline bitfld.long 0x0 1. "IDR1,IDR1" "0,1" bitfld.long 0x0 0. "IDR0,IDR0" "0,1" group.long 0x14++0x3 line.long 0x0 "GPIOD_ODR,GPIO port output data register" bitfld.long 0x0 15. "ODR15,ODR15" "0,1" bitfld.long 0x0 14. "ODR14,ODR14" "0,1" bitfld.long 0x0 13. "ODR13,ODR13" "0,1" bitfld.long 0x0 12. "ODR12,ODR12" "0,1" bitfld.long 0x0 11. "ODR11,ODR11" "0,1" bitfld.long 0x0 10. "ODR10,ODR10" "0,1" bitfld.long 0x0 9. "ODR9,ODR9" "0,1" newline bitfld.long 0x0 8. "ODR8,ODR8" "0,1" bitfld.long 0x0 7. "ODR7,ODR7" "0,1" bitfld.long 0x0 6. "ODR6,ODR6" "0,1" bitfld.long 0x0 5. "ODR5,ODR5" "0,1" bitfld.long 0x0 4. "ODR4,ODR4" "0,1" bitfld.long 0x0 3. "ODR3,ODR3" "0,1" bitfld.long 0x0 2. "ODR2,ODR2" "0,1" newline bitfld.long 0x0 1. "ODR1,ODR1" "0,1" bitfld.long 0x0 0. "ODR0,ODR0" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "GPIOD_BSRR,GPIO port bit set/reset register" bitfld.long 0x0 31. "BR15,BR15" "0,1" bitfld.long 0x0 30. "BR14,BR14" "0,1" bitfld.long 0x0 29. "BR13,BR13" "0,1" bitfld.long 0x0 28. "BR12,BR12" "0,1" bitfld.long 0x0 27. "BR11,BR11" "0,1" bitfld.long 0x0 26. "BR10,BR10" "0,1" bitfld.long 0x0 25. "BR9,BR9" "0,1" newline bitfld.long 0x0 24. "BR8,BR8" "0,1" bitfld.long 0x0 23. "BR7,BR7" "0,1" bitfld.long 0x0 22. "BR6,BR6" "0,1" bitfld.long 0x0 21. "BR5,BR5" "0,1" bitfld.long 0x0 20. "BR4,BR4" "0,1" bitfld.long 0x0 19. "BR3,BR3" "0,1" bitfld.long 0x0 18. "BR2,BR2" "0,1" newline bitfld.long 0x0 17. "BR1,BR1" "0,1" bitfld.long 0x0 16. "BR0,BR0" "0,1" bitfld.long 0x0 15. "BS15,BS15" "0,1" bitfld.long 0x0 14. "BS14,BS14" "0,1" bitfld.long 0x0 13. "BS13,BS13" "0,1" bitfld.long 0x0 12. "BS12,BS12" "0,1" bitfld.long 0x0 11. "BS11,BS11" "0,1" newline bitfld.long 0x0 10. "BS10,BS10" "0,1" bitfld.long 0x0 9. "BS9,BS9" "0,1" bitfld.long 0x0 8. "BS8,BS8" "0,1" bitfld.long 0x0 7. "BS7,BS7" "0,1" bitfld.long 0x0 6. "BS6,BS6" "0,1" bitfld.long 0x0 5. "BS5,BS5" "0,1" bitfld.long 0x0 4. "BS4,BS4" "0,1" newline bitfld.long 0x0 3. "BS3,BS3" "0,1" bitfld.long 0x0 2. "BS2,BS2" "0,1" bitfld.long 0x0 1. "BS1,BS1" "0,1" bitfld.long 0x0 0. "BS0,BS0" "0,1" group.long 0x1C++0xB line.long 0x0 "GPIOD_LCKR,This register is used to lock the configuration of the port bits when a correct write sequence is applied to bit 16 (LCKK). The value of bits [15:0] is used to lock the configuration of the GPIO. During the write sequence. the value of.." bitfld.long 0x0 16. "LCKK,LCKK" "0,1" bitfld.long 0x0 15. "LCK15,LCK15" "0,1" bitfld.long 0x0 14. "LCK14,LCK14" "0,1" bitfld.long 0x0 13. "LCK13,LCK13" "0,1" bitfld.long 0x0 12. "LCK12,LCK12" "0,1" bitfld.long 0x0 11. "LCK11,LCK11" "0,1" bitfld.long 0x0 10. "LCK10,LCK10" "0,1" newline bitfld.long 0x0 9. "LCK9,LCK9" "0,1" bitfld.long 0x0 8. "LCK8,LCK8" "0,1" bitfld.long 0x0 7. "LCK7,LCK7" "0,1" bitfld.long 0x0 6. "LCK6,LCK6" "0,1" bitfld.long 0x0 5. "LCK5,LCK5" "0,1" bitfld.long 0x0 4. "LCK4,LCK4" "0,1" bitfld.long 0x0 3. "LCK3,LCK3" "0,1" newline bitfld.long 0x0 2. "LCK2,LCK2" "0,1" bitfld.long 0x0 1. "LCK1,LCK1" "0,1" bitfld.long 0x0 0. "LCK0,LCK0" "0,1" line.long 0x4 "GPIOD_AFRL,GPIO alternate function low register" hexmask.long.byte 0x4 28.--31. 1. "AFR7,AFR7" hexmask.long.byte 0x4 24.--27. 1. "AFR6,AFR6" hexmask.long.byte 0x4 20.--23. 1. "AFR5,AFR5" hexmask.long.byte 0x4 16.--19. 1. "AFR4,AFR4" hexmask.long.byte 0x4 12.--15. 1. "AFR3,AFR3" hexmask.long.byte 0x4 8.--11. 1. "AFR2,AFR2" hexmask.long.byte 0x4 4.--7. 1. "AFR1,AFR1" newline hexmask.long.byte 0x4 0.--3. 1. "AFR0,AFR0" line.long 0x8 "GPIOD_AFRH,GPIO alternate function high register" hexmask.long.byte 0x8 28.--31. 1. "AFR15,AFR15" hexmask.long.byte 0x8 24.--27. 1. "AFR14,AFR14" hexmask.long.byte 0x8 20.--23. 1. "AFR13,AFR13" hexmask.long.byte 0x8 16.--19. 1. "AFR12,AFR12" hexmask.long.byte 0x8 12.--15. 1. "AFR11,AFR11" hexmask.long.byte 0x8 8.--11. 1. "AFR10,AFR10" hexmask.long.byte 0x8 4.--7. 1. "AFR9,AFR9" newline hexmask.long.byte 0x8 0.--3. 1. "AFR8,AFR8" wgroup.long 0x28++0x3 line.long 0x0 "GPIOD_BRR,GPIO port bit reset register" bitfld.long 0x0 15. "BR15,BR15" "0,1" bitfld.long 0x0 14. "BR14,BR14" "0,1" bitfld.long 0x0 13. "BR13,BR13" "0,1" bitfld.long 0x0 12. "BR12,BR12" "0,1" bitfld.long 0x0 11. "BR11,BR11" "0,1" bitfld.long 0x0 10. "BR10,BR10" "0,1" bitfld.long 0x0 9. "BR9,BR9" "0,1" newline bitfld.long 0x0 8. "BR8,BR8" "0,1" bitfld.long 0x0 7. "BR7,BR7" "0,1" bitfld.long 0x0 6. "BR6,BR6" "0,1" bitfld.long 0x0 5. "BR5,BR5" "0,1" bitfld.long 0x0 4. "BR4,BR4" "0,1" bitfld.long 0x0 3. "BR3,BR3" "0,1" bitfld.long 0x0 2. "BR2,BR2" "0,1" newline bitfld.long 0x0 1. "BR1,BR1" "0,1" bitfld.long 0x0 0. "BR0,BR0" "0,1" rgroup.long 0x3C8++0x37 line.long 0x0 "GPIOD_HWCFGR10,For GPIOA. B. C. D. E. F. G. H. I. J and GPIOK: For GPIOZ:" hexmask.long.byte 0x0 20.--23. 1. "OR_CFG,OR_CFG" hexmask.long.byte 0x0 16.--19. 1. "SEC_CFG,SEC_CFG" hexmask.long.byte 0x0 12.--15. 1. "LOCK_CFG,LOCK_CFG" hexmask.long.byte 0x0 8.--11. 1. "SPEED_CFG,SPEED_CFG" hexmask.long.byte 0x0 4.--7. 1. "AF_SIZE,AF_SIZE" hexmask.long.byte 0x0 0.--3. 1. "AHB_IOP,AHB_IOP" line.long 0x4 "GPIOD_HWCFGR9,For GPIOA. B. C. D. E. F. G. H. I. and GPIOJ: For GPIOK and GPIOZ:" hexmask.long.word 0x4 0.--15. 1. "EN_IO,EN_IO" line.long 0x8 "GPIOD_HWCFGR8,For GPIOA. B. C. D. E. F. G. H. I. and GPIOJ: For GPIOK and GPIOZ:" hexmask.long.byte 0x8 28.--31. 1. "AF_PRIO15,AF_PRIO15" hexmask.long.byte 0x8 24.--27. 1. "AF_PRIO14,AF_PRIO14" hexmask.long.byte 0x8 20.--23. 1. "AF_PRIO13,AF_PRIO13" hexmask.long.byte 0x8 16.--19. 1. "AF_PRIO12,AF_PRIO12" hexmask.long.byte 0x8 12.--15. 1. "AF_PRIO11,AF_PRIO11" hexmask.long.byte 0x8 8.--11. 1. "AF_PRIO10,AF_PRIO10" hexmask.long.byte 0x8 4.--7. 1. "AF_PRIO9,AF_PRIO9" newline hexmask.long.byte 0x8 0.--3. 1. "AF_PRIO8,AF_PRIO8" line.long 0xC "GPIOD_HWCFGR7,GPIO hardware configuration register 7" hexmask.long.byte 0xC 28.--31. 1. "AF_PRIO7,AF_PRIO7" hexmask.long.byte 0xC 24.--27. 1. "AF_PRIO6,AF_PRIO6" hexmask.long.byte 0xC 20.--23. 1. "AF_PRIO5,AF_PRIO5" hexmask.long.byte 0xC 16.--19. 1. "AF_PRIO4,AF_PRIO4" hexmask.long.byte 0xC 12.--15. 1. "AF_PRIO3,AF_PRIO3" hexmask.long.byte 0xC 8.--11. 1. "AF_PRIO2,AF_PRIO2" hexmask.long.byte 0xC 4.--7. 1. "AF_PRIO1,AF_PRIO1" newline hexmask.long.byte 0xC 0.--3. 1. "AF_PRIO0,AF_PRIO0" line.long 0x10 "GPIOD_HWCFGR6,GPIO hardware configuration register 6" hexmask.long 0x10 0.--31. 1. "MODER_RES,MODER_RES" line.long 0x14 "GPIOD_HWCFGR5,GPIO hardware configuration register 5" hexmask.long 0x14 0.--31. 1. "PUPDR_RES,PUPDR_RES" line.long 0x18 "GPIOD_HWCFGR4,GPIO hardware configuration register 4" hexmask.long 0x18 0.--31. 1. "OSPEED_RES,OSPEED_RES" line.long 0x1C "GPIOD_HWCFGR3,GPIO hardware configuration register 3" hexmask.long.word 0x1C 16.--31. 1. "OTYPER_RES,OTYPER_RES" hexmask.long.word 0x1C 0.--15. 1. "ODR_RES,ODR_RES" line.long 0x20 "GPIOD_HWCFGR2,GPIO hardware configuration register 2" hexmask.long 0x20 0.--31. 1. "AFRL_RES,AFRL_RES" line.long 0x24 "GPIOD_HWCFGR1,GPIO hardware configuration register 1" hexmask.long 0x24 0.--31. 1. "AFRH_RES,AFRH_RES" line.long 0x28 "GPIOD_HWCFGR0,GPIO hardware configuration register 0" hexmask.long.word 0x28 0.--15. 1. "OR_RES,OR_RES" line.long 0x2C "GPIOD_VERR,GPIO version register" hexmask.long.byte 0x2C 4.--7. 1. "MAJREV,MAJREV" hexmask.long.byte 0x2C 0.--3. 1. "MINREV,MINREV" line.long 0x30 "GPIOD_IPIDR,GPIO identification register" hexmask.long 0x30 0.--31. 1. "IPIDR,IPIDR" line.long 0x34 "GPIOD_SIDR,GPIO size identification register" hexmask.long 0x34 0.--31. 1. "SIDR,SIDR" tree.end endif sif (cpuis("STM32MP151*")||cpuis("STM32MP153*")||cpuis("STM32MP157*")) tree "GPIOE" base ad:0x50006000 group.long 0x0++0xF line.long 0x0 "GPIOE_MODER,GPIO port mode register" bitfld.long 0x0 30.--31. "MODER15,MODER15" "0,1,2,3" bitfld.long 0x0 28.--29. "MODER14,MODER14" "0,1,2,3" bitfld.long 0x0 26.--27. "MODER13,MODER13" "0,1,2,3" bitfld.long 0x0 24.--25. "MODER12,MODER12" "0,1,2,3" bitfld.long 0x0 22.--23. "MODER11,MODER11" "0,1,2,3" bitfld.long 0x0 20.--21. "MODER10,MODER10" "0,1,2,3" bitfld.long 0x0 18.--19. "MODER9,MODER9" "0,1,2,3" newline bitfld.long 0x0 16.--17. "MODER8,MODER8" "0,1,2,3" bitfld.long 0x0 14.--15. "MODER7,MODER7" "0,1,2,3" bitfld.long 0x0 12.--13. "MODER6,MODER6" "0,1,2,3" bitfld.long 0x0 10.--11. "MODER5,MODER5" "0,1,2,3" bitfld.long 0x0 8.--9. "MODER4,MODER4" "0,1,2,3" bitfld.long 0x0 6.--7. "MODER3,MODER3" "0,1,2,3" bitfld.long 0x0 4.--5. "MODER2,MODER2" "0,1,2,3" newline bitfld.long 0x0 2.--3. "MODER1,MODER1" "0,1,2,3" bitfld.long 0x0 0.--1. "MODER0,MODER0" "0,1,2,3" line.long 0x4 "GPIOE_OTYPER,GPIO port output type register" bitfld.long 0x4 15. "OT15,OT15" "0,1" bitfld.long 0x4 14. "OT14,OT14" "0,1" bitfld.long 0x4 13. "OT13,OT13" "0,1" bitfld.long 0x4 12. "OT12,OT12" "0,1" bitfld.long 0x4 11. "OT11,OT11" "0,1" bitfld.long 0x4 10. "OT10,OT10" "0,1" bitfld.long 0x4 9. "OT9,OT9" "0,1" newline bitfld.long 0x4 8. "OT8,OT8" "0,1" bitfld.long 0x4 7. "OT7,OT7" "0,1" bitfld.long 0x4 6. "OT6,OT6" "0,1" bitfld.long 0x4 5. "OT5,OT5" "0,1" bitfld.long 0x4 4. "OT4,OT4" "0,1" bitfld.long 0x4 3. "OT3,OT3" "0,1" bitfld.long 0x4 2. "OT2,OT2" "0,1" newline bitfld.long 0x4 1. "OT1,OT1" "0,1" bitfld.long 0x4 0. "OT0,OT0" "0,1" line.long 0x8 "GPIOE_OSPEEDR,GPIO port output speed register" bitfld.long 0x8 30.--31. "OSPEEDR15,OSPEEDR15" "0,1,2,3" bitfld.long 0x8 28.--29. "OSPEEDR14,OSPEEDR14" "0,1,2,3" bitfld.long 0x8 26.--27. "OSPEEDR13,OSPEEDR13" "0,1,2,3" bitfld.long 0x8 24.--25. "OSPEEDR12,OSPEEDR12" "0,1,2,3" bitfld.long 0x8 22.--23. "OSPEEDR11,OSPEEDR11" "0,1,2,3" bitfld.long 0x8 20.--21. "OSPEEDR10,OSPEEDR10" "0,1,2,3" bitfld.long 0x8 18.--19. "OSPEEDR9,OSPEEDR9" "0,1,2,3" newline bitfld.long 0x8 16.--17. "OSPEEDR8,OSPEEDR8" "0,1,2,3" bitfld.long 0x8 14.--15. "OSPEEDR7,OSPEEDR7" "0,1,2,3" bitfld.long 0x8 12.--13. "OSPEEDR6,OSPEEDR6" "0,1,2,3" bitfld.long 0x8 10.--11. "OSPEEDR5,OSPEEDR5" "0,1,2,3" bitfld.long 0x8 8.--9. "OSPEEDR4,OSPEEDR4" "0,1,2,3" bitfld.long 0x8 6.--7. "OSPEEDR3,OSPEEDR3" "0,1,2,3" bitfld.long 0x8 4.--5. "OSPEEDR2,OSPEEDR2" "0,1,2,3" newline bitfld.long 0x8 2.--3. "OSPEEDR1,OSPEEDR1" "0,1,2,3" bitfld.long 0x8 0.--1. "OSPEEDR0,OSPEEDR0" "0,1,2,3" line.long 0xC "GPIOE_PUPDR,GPIO port pull-up/pull-down register" bitfld.long 0xC 30.--31. "PUPDR15,PUPDR15" "0,1,2,3" bitfld.long 0xC 28.--29. "PUPDR14,PUPDR14" "0,1,2,3" bitfld.long 0xC 26.--27. "PUPDR13,PUPDR13" "0,1,2,3" bitfld.long 0xC 24.--25. "PUPDR12,PUPDR12" "0,1,2,3" bitfld.long 0xC 22.--23. "PUPDR11,PUPDR11" "0,1,2,3" bitfld.long 0xC 20.--21. "PUPDR10,PUPDR10" "0,1,2,3" bitfld.long 0xC 18.--19. "PUPDR9,PUPDR9" "0,1,2,3" newline bitfld.long 0xC 16.--17. "PUPDR8,PUPDR8" "0,1,2,3" bitfld.long 0xC 14.--15. "PUPDR7,PUPDR7" "0,1,2,3" bitfld.long 0xC 12.--13. "PUPDR6,PUPDR6" "0,1,2,3" bitfld.long 0xC 10.--11. "PUPDR5,PUPDR5" "0,1,2,3" bitfld.long 0xC 8.--9. "PUPDR4,PUPDR4" "0,1,2,3" bitfld.long 0xC 6.--7. "PUPDR3,PUPDR3" "0,1,2,3" bitfld.long 0xC 4.--5. "PUPDR2,PUPDR2" "0,1,2,3" newline bitfld.long 0xC 2.--3. "PUPDR1,PUPDR1" "0,1,2,3" bitfld.long 0xC 0.--1. "PUPDR0,PUPDR0" "0,1,2,3" rgroup.long 0x10++0x3 line.long 0x0 "GPIOE_IDR,GPIO port input data register" bitfld.long 0x0 15. "IDR15,IDR15" "0,1" bitfld.long 0x0 14. "IDR14,IDR14" "0,1" bitfld.long 0x0 13. "IDR13,IDR13" "0,1" bitfld.long 0x0 12. "IDR12,IDR12" "0,1" bitfld.long 0x0 11. "IDR11,IDR11" "0,1" bitfld.long 0x0 10. "IDR10,IDR10" "0,1" bitfld.long 0x0 9. "IDR9,IDR9" "0,1" newline bitfld.long 0x0 8. "IDR8,IDR8" "0,1" bitfld.long 0x0 7. "IDR7,IDR7" "0,1" bitfld.long 0x0 6. "IDR6,IDR6" "0,1" bitfld.long 0x0 5. "IDR5,IDR5" "0,1" bitfld.long 0x0 4. "IDR4,IDR4" "0,1" bitfld.long 0x0 3. "IDR3,IDR3" "0,1" bitfld.long 0x0 2. "IDR2,IDR2" "0,1" newline bitfld.long 0x0 1. "IDR1,IDR1" "0,1" bitfld.long 0x0 0. "IDR0,IDR0" "0,1" group.long 0x14++0x3 line.long 0x0 "GPIOE_ODR,GPIO port output data register" bitfld.long 0x0 15. "ODR15,ODR15" "0,1" bitfld.long 0x0 14. "ODR14,ODR14" "0,1" bitfld.long 0x0 13. "ODR13,ODR13" "0,1" bitfld.long 0x0 12. "ODR12,ODR12" "0,1" bitfld.long 0x0 11. "ODR11,ODR11" "0,1" bitfld.long 0x0 10. "ODR10,ODR10" "0,1" bitfld.long 0x0 9. "ODR9,ODR9" "0,1" newline bitfld.long 0x0 8. "ODR8,ODR8" "0,1" bitfld.long 0x0 7. "ODR7,ODR7" "0,1" bitfld.long 0x0 6. "ODR6,ODR6" "0,1" bitfld.long 0x0 5. "ODR5,ODR5" "0,1" bitfld.long 0x0 4. "ODR4,ODR4" "0,1" bitfld.long 0x0 3. "ODR3,ODR3" "0,1" bitfld.long 0x0 2. "ODR2,ODR2" "0,1" newline bitfld.long 0x0 1. "ODR1,ODR1" "0,1" bitfld.long 0x0 0. "ODR0,ODR0" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "GPIOE_BSRR,GPIO port bit set/reset register" bitfld.long 0x0 31. "BR15,BR15" "0,1" bitfld.long 0x0 30. "BR14,BR14" "0,1" bitfld.long 0x0 29. "BR13,BR13" "0,1" bitfld.long 0x0 28. "BR12,BR12" "0,1" bitfld.long 0x0 27. "BR11,BR11" "0,1" bitfld.long 0x0 26. "BR10,BR10" "0,1" bitfld.long 0x0 25. "BR9,BR9" "0,1" newline bitfld.long 0x0 24. "BR8,BR8" "0,1" bitfld.long 0x0 23. "BR7,BR7" "0,1" bitfld.long 0x0 22. "BR6,BR6" "0,1" bitfld.long 0x0 21. "BR5,BR5" "0,1" bitfld.long 0x0 20. "BR4,BR4" "0,1" bitfld.long 0x0 19. "BR3,BR3" "0,1" bitfld.long 0x0 18. "BR2,BR2" "0,1" newline bitfld.long 0x0 17. "BR1,BR1" "0,1" bitfld.long 0x0 16. "BR0,BR0" "0,1" bitfld.long 0x0 15. "BS15,BS15" "0,1" bitfld.long 0x0 14. "BS14,BS14" "0,1" bitfld.long 0x0 13. "BS13,BS13" "0,1" bitfld.long 0x0 12. "BS12,BS12" "0,1" bitfld.long 0x0 11. "BS11,BS11" "0,1" newline bitfld.long 0x0 10. "BS10,BS10" "0,1" bitfld.long 0x0 9. "BS9,BS9" "0,1" bitfld.long 0x0 8. "BS8,BS8" "0,1" bitfld.long 0x0 7. "BS7,BS7" "0,1" bitfld.long 0x0 6. "BS6,BS6" "0,1" bitfld.long 0x0 5. "BS5,BS5" "0,1" bitfld.long 0x0 4. "BS4,BS4" "0,1" newline bitfld.long 0x0 3. "BS3,BS3" "0,1" bitfld.long 0x0 2. "BS2,BS2" "0,1" bitfld.long 0x0 1. "BS1,BS1" "0,1" bitfld.long 0x0 0. "BS0,BS0" "0,1" group.long 0x1C++0xB line.long 0x0 "GPIOE_LCKR,This register is used to lock the configuration of the port bits when a correct write sequence is applied to bit 16 (LCKK). The value of bits [15:0] is used to lock the configuration of the GPIO. During the write sequence. the value of.." bitfld.long 0x0 16. "LCKK,LCKK" "0,1" bitfld.long 0x0 15. "LCK15,LCK15" "0,1" bitfld.long 0x0 14. "LCK14,LCK14" "0,1" bitfld.long 0x0 13. "LCK13,LCK13" "0,1" bitfld.long 0x0 12. "LCK12,LCK12" "0,1" bitfld.long 0x0 11. "LCK11,LCK11" "0,1" bitfld.long 0x0 10. "LCK10,LCK10" "0,1" newline bitfld.long 0x0 9. "LCK9,LCK9" "0,1" bitfld.long 0x0 8. "LCK8,LCK8" "0,1" bitfld.long 0x0 7. "LCK7,LCK7" "0,1" bitfld.long 0x0 6. "LCK6,LCK6" "0,1" bitfld.long 0x0 5. "LCK5,LCK5" "0,1" bitfld.long 0x0 4. "LCK4,LCK4" "0,1" bitfld.long 0x0 3. "LCK3,LCK3" "0,1" newline bitfld.long 0x0 2. "LCK2,LCK2" "0,1" bitfld.long 0x0 1. "LCK1,LCK1" "0,1" bitfld.long 0x0 0. "LCK0,LCK0" "0,1" line.long 0x4 "GPIOE_AFRL,GPIO alternate function low register" hexmask.long.byte 0x4 28.--31. 1. "AFR7,AFR7" hexmask.long.byte 0x4 24.--27. 1. "AFR6,AFR6" hexmask.long.byte 0x4 20.--23. 1. "AFR5,AFR5" hexmask.long.byte 0x4 16.--19. 1. "AFR4,AFR4" hexmask.long.byte 0x4 12.--15. 1. "AFR3,AFR3" hexmask.long.byte 0x4 8.--11. 1. "AFR2,AFR2" hexmask.long.byte 0x4 4.--7. 1. "AFR1,AFR1" newline hexmask.long.byte 0x4 0.--3. 1. "AFR0,AFR0" line.long 0x8 "GPIOE_AFRH,GPIO alternate function high register" hexmask.long.byte 0x8 28.--31. 1. "AFR15,AFR15" hexmask.long.byte 0x8 24.--27. 1. "AFR14,AFR14" hexmask.long.byte 0x8 20.--23. 1. "AFR13,AFR13" hexmask.long.byte 0x8 16.--19. 1. "AFR12,AFR12" hexmask.long.byte 0x8 12.--15. 1. "AFR11,AFR11" hexmask.long.byte 0x8 8.--11. 1. "AFR10,AFR10" hexmask.long.byte 0x8 4.--7. 1. "AFR9,AFR9" newline hexmask.long.byte 0x8 0.--3. 1. "AFR8,AFR8" wgroup.long 0x28++0x3 line.long 0x0 "GPIOE_BRR,GPIO port bit reset register" bitfld.long 0x0 15. "BR15,BR15" "0,1" bitfld.long 0x0 14. "BR14,BR14" "0,1" bitfld.long 0x0 13. "BR13,BR13" "0,1" bitfld.long 0x0 12. "BR12,BR12" "0,1" bitfld.long 0x0 11. "BR11,BR11" "0,1" bitfld.long 0x0 10. "BR10,BR10" "0,1" bitfld.long 0x0 9. "BR9,BR9" "0,1" newline bitfld.long 0x0 8. "BR8,BR8" "0,1" bitfld.long 0x0 7. "BR7,BR7" "0,1" bitfld.long 0x0 6. "BR6,BR6" "0,1" bitfld.long 0x0 5. "BR5,BR5" "0,1" bitfld.long 0x0 4. "BR4,BR4" "0,1" bitfld.long 0x0 3. "BR3,BR3" "0,1" bitfld.long 0x0 2. "BR2,BR2" "0,1" newline bitfld.long 0x0 1. "BR1,BR1" "0,1" bitfld.long 0x0 0. "BR0,BR0" "0,1" rgroup.long 0x3C8++0x37 line.long 0x0 "GPIOE_HWCFGR10,For GPIOA. B. C. D. E. F. G. H. I. J and GPIOK: For GPIOZ:" hexmask.long.byte 0x0 20.--23. 1. "OR_CFG,OR_CFG" hexmask.long.byte 0x0 16.--19. 1. "SEC_CFG,SEC_CFG" hexmask.long.byte 0x0 12.--15. 1. "LOCK_CFG,LOCK_CFG" hexmask.long.byte 0x0 8.--11. 1. "SPEED_CFG,SPEED_CFG" hexmask.long.byte 0x0 4.--7. 1. "AF_SIZE,AF_SIZE" hexmask.long.byte 0x0 0.--3. 1. "AHB_IOP,AHB_IOP" line.long 0x4 "GPIOE_HWCFGR9,For GPIOA. B. C. D. E. F. G. H. I. and GPIOJ: For GPIOK and GPIOZ:" hexmask.long.word 0x4 0.--15. 1. "EN_IO,EN_IO" line.long 0x8 "GPIOE_HWCFGR8,For GPIOA. B. C. D. E. F. G. H. I. and GPIOJ: For GPIOK and GPIOZ:" hexmask.long.byte 0x8 28.--31. 1. "AF_PRIO15,AF_PRIO15" hexmask.long.byte 0x8 24.--27. 1. "AF_PRIO14,AF_PRIO14" hexmask.long.byte 0x8 20.--23. 1. "AF_PRIO13,AF_PRIO13" hexmask.long.byte 0x8 16.--19. 1. "AF_PRIO12,AF_PRIO12" hexmask.long.byte 0x8 12.--15. 1. "AF_PRIO11,AF_PRIO11" hexmask.long.byte 0x8 8.--11. 1. "AF_PRIO10,AF_PRIO10" hexmask.long.byte 0x8 4.--7. 1. "AF_PRIO9,AF_PRIO9" newline hexmask.long.byte 0x8 0.--3. 1. "AF_PRIO8,AF_PRIO8" line.long 0xC "GPIOE_HWCFGR7,GPIO hardware configuration register 7" hexmask.long.byte 0xC 28.--31. 1. "AF_PRIO7,AF_PRIO7" hexmask.long.byte 0xC 24.--27. 1. "AF_PRIO6,AF_PRIO6" hexmask.long.byte 0xC 20.--23. 1. "AF_PRIO5,AF_PRIO5" hexmask.long.byte 0xC 16.--19. 1. "AF_PRIO4,AF_PRIO4" hexmask.long.byte 0xC 12.--15. 1. "AF_PRIO3,AF_PRIO3" hexmask.long.byte 0xC 8.--11. 1. "AF_PRIO2,AF_PRIO2" hexmask.long.byte 0xC 4.--7. 1. "AF_PRIO1,AF_PRIO1" newline hexmask.long.byte 0xC 0.--3. 1. "AF_PRIO0,AF_PRIO0" line.long 0x10 "GPIOE_HWCFGR6,GPIO hardware configuration register 6" hexmask.long 0x10 0.--31. 1. "MODER_RES,MODER_RES" line.long 0x14 "GPIOE_HWCFGR5,GPIO hardware configuration register 5" hexmask.long 0x14 0.--31. 1. "PUPDR_RES,PUPDR_RES" line.long 0x18 "GPIOE_HWCFGR4,GPIO hardware configuration register 4" hexmask.long 0x18 0.--31. 1. "OSPEED_RES,OSPEED_RES" line.long 0x1C "GPIOE_HWCFGR3,GPIO hardware configuration register 3" hexmask.long.word 0x1C 16.--31. 1. "OTYPER_RES,OTYPER_RES" hexmask.long.word 0x1C 0.--15. 1. "ODR_RES,ODR_RES" line.long 0x20 "GPIOE_HWCFGR2,GPIO hardware configuration register 2" hexmask.long 0x20 0.--31. 1. "AFRL_RES,AFRL_RES" line.long 0x24 "GPIOE_HWCFGR1,GPIO hardware configuration register 1" hexmask.long 0x24 0.--31. 1. "AFRH_RES,AFRH_RES" line.long 0x28 "GPIOE_HWCFGR0,GPIO hardware configuration register 0" hexmask.long.word 0x28 0.--15. 1. "OR_RES,OR_RES" line.long 0x2C "GPIOE_VERR,GPIO version register" hexmask.long.byte 0x2C 4.--7. 1. "MAJREV,MAJREV" hexmask.long.byte 0x2C 0.--3. 1. "MINREV,MINREV" line.long 0x30 "GPIOE_IPIDR,GPIO identification register" hexmask.long 0x30 0.--31. 1. "IPIDR,IPIDR" line.long 0x34 "GPIOE_SIDR,GPIO size identification register" hexmask.long 0x34 0.--31. 1. "SIDR,SIDR" tree.end endif sif (cpuis("STM32MP151*")||cpuis("STM32MP153*")||cpuis("STM32MP157*")) tree "GPIOF" base ad:0x50007000 group.long 0x0++0xF line.long 0x0 "GPIOF_MODER,GPIO port mode register" bitfld.long 0x0 30.--31. "MODER15,MODER15" "0,1,2,3" bitfld.long 0x0 28.--29. "MODER14,MODER14" "0,1,2,3" bitfld.long 0x0 26.--27. "MODER13,MODER13" "0,1,2,3" bitfld.long 0x0 24.--25. "MODER12,MODER12" "0,1,2,3" bitfld.long 0x0 22.--23. "MODER11,MODER11" "0,1,2,3" bitfld.long 0x0 20.--21. "MODER10,MODER10" "0,1,2,3" bitfld.long 0x0 18.--19. "MODER9,MODER9" "0,1,2,3" newline bitfld.long 0x0 16.--17. "MODER8,MODER8" "0,1,2,3" bitfld.long 0x0 14.--15. "MODER7,MODER7" "0,1,2,3" bitfld.long 0x0 12.--13. "MODER6,MODER6" "0,1,2,3" bitfld.long 0x0 10.--11. "MODER5,MODER5" "0,1,2,3" bitfld.long 0x0 8.--9. "MODER4,MODER4" "0,1,2,3" bitfld.long 0x0 6.--7. "MODER3,MODER3" "0,1,2,3" bitfld.long 0x0 4.--5. "MODER2,MODER2" "0,1,2,3" newline bitfld.long 0x0 2.--3. "MODER1,MODER1" "0,1,2,3" bitfld.long 0x0 0.--1. "MODER0,MODER0" "0,1,2,3" line.long 0x4 "GPIOF_OTYPER,GPIO port output type register" bitfld.long 0x4 15. "OT15,OT15" "0,1" bitfld.long 0x4 14. "OT14,OT14" "0,1" bitfld.long 0x4 13. "OT13,OT13" "0,1" bitfld.long 0x4 12. "OT12,OT12" "0,1" bitfld.long 0x4 11. "OT11,OT11" "0,1" bitfld.long 0x4 10. "OT10,OT10" "0,1" bitfld.long 0x4 9. "OT9,OT9" "0,1" newline bitfld.long 0x4 8. "OT8,OT8" "0,1" bitfld.long 0x4 7. "OT7,OT7" "0,1" bitfld.long 0x4 6. "OT6,OT6" "0,1" bitfld.long 0x4 5. "OT5,OT5" "0,1" bitfld.long 0x4 4. "OT4,OT4" "0,1" bitfld.long 0x4 3. "OT3,OT3" "0,1" bitfld.long 0x4 2. "OT2,OT2" "0,1" newline bitfld.long 0x4 1. "OT1,OT1" "0,1" bitfld.long 0x4 0. "OT0,OT0" "0,1" line.long 0x8 "GPIOF_OSPEEDR,GPIO port output speed register" bitfld.long 0x8 30.--31. "OSPEEDR15,OSPEEDR15" "0,1,2,3" bitfld.long 0x8 28.--29. "OSPEEDR14,OSPEEDR14" "0,1,2,3" bitfld.long 0x8 26.--27. "OSPEEDR13,OSPEEDR13" "0,1,2,3" bitfld.long 0x8 24.--25. "OSPEEDR12,OSPEEDR12" "0,1,2,3" bitfld.long 0x8 22.--23. "OSPEEDR11,OSPEEDR11" "0,1,2,3" bitfld.long 0x8 20.--21. "OSPEEDR10,OSPEEDR10" "0,1,2,3" bitfld.long 0x8 18.--19. "OSPEEDR9,OSPEEDR9" "0,1,2,3" newline bitfld.long 0x8 16.--17. "OSPEEDR8,OSPEEDR8" "0,1,2,3" bitfld.long 0x8 14.--15. "OSPEEDR7,OSPEEDR7" "0,1,2,3" bitfld.long 0x8 12.--13. "OSPEEDR6,OSPEEDR6" "0,1,2,3" bitfld.long 0x8 10.--11. "OSPEEDR5,OSPEEDR5" "0,1,2,3" bitfld.long 0x8 8.--9. "OSPEEDR4,OSPEEDR4" "0,1,2,3" bitfld.long 0x8 6.--7. "OSPEEDR3,OSPEEDR3" "0,1,2,3" bitfld.long 0x8 4.--5. "OSPEEDR2,OSPEEDR2" "0,1,2,3" newline bitfld.long 0x8 2.--3. "OSPEEDR1,OSPEEDR1" "0,1,2,3" bitfld.long 0x8 0.--1. "OSPEEDR0,OSPEEDR0" "0,1,2,3" line.long 0xC "GPIOF_PUPDR,GPIO port pull-up/pull-down register" bitfld.long 0xC 30.--31. "PUPDR15,PUPDR15" "0,1,2,3" bitfld.long 0xC 28.--29. "PUPDR14,PUPDR14" "0,1,2,3" bitfld.long 0xC 26.--27. "PUPDR13,PUPDR13" "0,1,2,3" bitfld.long 0xC 24.--25. "PUPDR12,PUPDR12" "0,1,2,3" bitfld.long 0xC 22.--23. "PUPDR11,PUPDR11" "0,1,2,3" bitfld.long 0xC 20.--21. "PUPDR10,PUPDR10" "0,1,2,3" bitfld.long 0xC 18.--19. "PUPDR9,PUPDR9" "0,1,2,3" newline bitfld.long 0xC 16.--17. "PUPDR8,PUPDR8" "0,1,2,3" bitfld.long 0xC 14.--15. "PUPDR7,PUPDR7" "0,1,2,3" bitfld.long 0xC 12.--13. "PUPDR6,PUPDR6" "0,1,2,3" bitfld.long 0xC 10.--11. "PUPDR5,PUPDR5" "0,1,2,3" bitfld.long 0xC 8.--9. "PUPDR4,PUPDR4" "0,1,2,3" bitfld.long 0xC 6.--7. "PUPDR3,PUPDR3" "0,1,2,3" bitfld.long 0xC 4.--5. "PUPDR2,PUPDR2" "0,1,2,3" newline bitfld.long 0xC 2.--3. "PUPDR1,PUPDR1" "0,1,2,3" bitfld.long 0xC 0.--1. "PUPDR0,PUPDR0" "0,1,2,3" rgroup.long 0x10++0x3 line.long 0x0 "GPIOF_IDR,GPIO port input data register" bitfld.long 0x0 15. "IDR15,IDR15" "0,1" bitfld.long 0x0 14. "IDR14,IDR14" "0,1" bitfld.long 0x0 13. "IDR13,IDR13" "0,1" bitfld.long 0x0 12. "IDR12,IDR12" "0,1" bitfld.long 0x0 11. "IDR11,IDR11" "0,1" bitfld.long 0x0 10. "IDR10,IDR10" "0,1" bitfld.long 0x0 9. "IDR9,IDR9" "0,1" newline bitfld.long 0x0 8. "IDR8,IDR8" "0,1" bitfld.long 0x0 7. "IDR7,IDR7" "0,1" bitfld.long 0x0 6. "IDR6,IDR6" "0,1" bitfld.long 0x0 5. "IDR5,IDR5" "0,1" bitfld.long 0x0 4. "IDR4,IDR4" "0,1" bitfld.long 0x0 3. "IDR3,IDR3" "0,1" bitfld.long 0x0 2. "IDR2,IDR2" "0,1" newline bitfld.long 0x0 1. "IDR1,IDR1" "0,1" bitfld.long 0x0 0. "IDR0,IDR0" "0,1" group.long 0x14++0x3 line.long 0x0 "GPIOF_ODR,GPIO port output data register" bitfld.long 0x0 15. "ODR15,ODR15" "0,1" bitfld.long 0x0 14. "ODR14,ODR14" "0,1" bitfld.long 0x0 13. "ODR13,ODR13" "0,1" bitfld.long 0x0 12. "ODR12,ODR12" "0,1" bitfld.long 0x0 11. "ODR11,ODR11" "0,1" bitfld.long 0x0 10. "ODR10,ODR10" "0,1" bitfld.long 0x0 9. "ODR9,ODR9" "0,1" newline bitfld.long 0x0 8. "ODR8,ODR8" "0,1" bitfld.long 0x0 7. "ODR7,ODR7" "0,1" bitfld.long 0x0 6. "ODR6,ODR6" "0,1" bitfld.long 0x0 5. "ODR5,ODR5" "0,1" bitfld.long 0x0 4. "ODR4,ODR4" "0,1" bitfld.long 0x0 3. "ODR3,ODR3" "0,1" bitfld.long 0x0 2. "ODR2,ODR2" "0,1" newline bitfld.long 0x0 1. "ODR1,ODR1" "0,1" bitfld.long 0x0 0. "ODR0,ODR0" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "GPIOF_BSRR,GPIO port bit set/reset register" bitfld.long 0x0 31. "BR15,BR15" "0,1" bitfld.long 0x0 30. "BR14,BR14" "0,1" bitfld.long 0x0 29. "BR13,BR13" "0,1" bitfld.long 0x0 28. "BR12,BR12" "0,1" bitfld.long 0x0 27. "BR11,BR11" "0,1" bitfld.long 0x0 26. "BR10,BR10" "0,1" bitfld.long 0x0 25. "BR9,BR9" "0,1" newline bitfld.long 0x0 24. "BR8,BR8" "0,1" bitfld.long 0x0 23. "BR7,BR7" "0,1" bitfld.long 0x0 22. "BR6,BR6" "0,1" bitfld.long 0x0 21. "BR5,BR5" "0,1" bitfld.long 0x0 20. "BR4,BR4" "0,1" bitfld.long 0x0 19. "BR3,BR3" "0,1" bitfld.long 0x0 18. "BR2,BR2" "0,1" newline bitfld.long 0x0 17. "BR1,BR1" "0,1" bitfld.long 0x0 16. "BR0,BR0" "0,1" bitfld.long 0x0 15. "BS15,BS15" "0,1" bitfld.long 0x0 14. "BS14,BS14" "0,1" bitfld.long 0x0 13. "BS13,BS13" "0,1" bitfld.long 0x0 12. "BS12,BS12" "0,1" bitfld.long 0x0 11. "BS11,BS11" "0,1" newline bitfld.long 0x0 10. "BS10,BS10" "0,1" bitfld.long 0x0 9. "BS9,BS9" "0,1" bitfld.long 0x0 8. "BS8,BS8" "0,1" bitfld.long 0x0 7. "BS7,BS7" "0,1" bitfld.long 0x0 6. "BS6,BS6" "0,1" bitfld.long 0x0 5. "BS5,BS5" "0,1" bitfld.long 0x0 4. "BS4,BS4" "0,1" newline bitfld.long 0x0 3. "BS3,BS3" "0,1" bitfld.long 0x0 2. "BS2,BS2" "0,1" bitfld.long 0x0 1. "BS1,BS1" "0,1" bitfld.long 0x0 0. "BS0,BS0" "0,1" group.long 0x1C++0xB line.long 0x0 "GPIOF_LCKR,This register is used to lock the configuration of the port bits when a correct write sequence is applied to bit 16 (LCKK). The value of bits [15:0] is used to lock the configuration of the GPIO. During the write sequence. the value of.." bitfld.long 0x0 16. "LCKK,LCKK" "0,1" bitfld.long 0x0 15. "LCK15,LCK15" "0,1" bitfld.long 0x0 14. "LCK14,LCK14" "0,1" bitfld.long 0x0 13. "LCK13,LCK13" "0,1" bitfld.long 0x0 12. "LCK12,LCK12" "0,1" bitfld.long 0x0 11. "LCK11,LCK11" "0,1" bitfld.long 0x0 10. "LCK10,LCK10" "0,1" newline bitfld.long 0x0 9. "LCK9,LCK9" "0,1" bitfld.long 0x0 8. "LCK8,LCK8" "0,1" bitfld.long 0x0 7. "LCK7,LCK7" "0,1" bitfld.long 0x0 6. "LCK6,LCK6" "0,1" bitfld.long 0x0 5. "LCK5,LCK5" "0,1" bitfld.long 0x0 4. "LCK4,LCK4" "0,1" bitfld.long 0x0 3. "LCK3,LCK3" "0,1" newline bitfld.long 0x0 2. "LCK2,LCK2" "0,1" bitfld.long 0x0 1. "LCK1,LCK1" "0,1" bitfld.long 0x0 0. "LCK0,LCK0" "0,1" line.long 0x4 "GPIOF_AFRL,GPIO alternate function low register" hexmask.long.byte 0x4 28.--31. 1. "AFR7,AFR7" hexmask.long.byte 0x4 24.--27. 1. "AFR6,AFR6" hexmask.long.byte 0x4 20.--23. 1. "AFR5,AFR5" hexmask.long.byte 0x4 16.--19. 1. "AFR4,AFR4" hexmask.long.byte 0x4 12.--15. 1. "AFR3,AFR3" hexmask.long.byte 0x4 8.--11. 1. "AFR2,AFR2" hexmask.long.byte 0x4 4.--7. 1. "AFR1,AFR1" newline hexmask.long.byte 0x4 0.--3. 1. "AFR0,AFR0" line.long 0x8 "GPIOF_AFRH,GPIO alternate function high register" hexmask.long.byte 0x8 28.--31. 1. "AFR15,AFR15" hexmask.long.byte 0x8 24.--27. 1. "AFR14,AFR14" hexmask.long.byte 0x8 20.--23. 1. "AFR13,AFR13" hexmask.long.byte 0x8 16.--19. 1. "AFR12,AFR12" hexmask.long.byte 0x8 12.--15. 1. "AFR11,AFR11" hexmask.long.byte 0x8 8.--11. 1. "AFR10,AFR10" hexmask.long.byte 0x8 4.--7. 1. "AFR9,AFR9" newline hexmask.long.byte 0x8 0.--3. 1. "AFR8,AFR8" wgroup.long 0x28++0x3 line.long 0x0 "GPIOF_BRR,GPIO port bit reset register" bitfld.long 0x0 15. "BR15,BR15" "0,1" bitfld.long 0x0 14. "BR14,BR14" "0,1" bitfld.long 0x0 13. "BR13,BR13" "0,1" bitfld.long 0x0 12. "BR12,BR12" "0,1" bitfld.long 0x0 11. "BR11,BR11" "0,1" bitfld.long 0x0 10. "BR10,BR10" "0,1" bitfld.long 0x0 9. "BR9,BR9" "0,1" newline bitfld.long 0x0 8. "BR8,BR8" "0,1" bitfld.long 0x0 7. "BR7,BR7" "0,1" bitfld.long 0x0 6. "BR6,BR6" "0,1" bitfld.long 0x0 5. "BR5,BR5" "0,1" bitfld.long 0x0 4. "BR4,BR4" "0,1" bitfld.long 0x0 3. "BR3,BR3" "0,1" bitfld.long 0x0 2. "BR2,BR2" "0,1" newline bitfld.long 0x0 1. "BR1,BR1" "0,1" bitfld.long 0x0 0. "BR0,BR0" "0,1" rgroup.long 0x3C8++0x37 line.long 0x0 "GPIOF_HWCFGR10,For GPIOA. B. C. D. E. F. G. H. I. J and GPIOK: For GPIOZ:" hexmask.long.byte 0x0 20.--23. 1. "OR_CFG,OR_CFG" hexmask.long.byte 0x0 16.--19. 1. "SEC_CFG,SEC_CFG" hexmask.long.byte 0x0 12.--15. 1. "LOCK_CFG,LOCK_CFG" hexmask.long.byte 0x0 8.--11. 1. "SPEED_CFG,SPEED_CFG" hexmask.long.byte 0x0 4.--7. 1. "AF_SIZE,AF_SIZE" hexmask.long.byte 0x0 0.--3. 1. "AHB_IOP,AHB_IOP" line.long 0x4 "GPIOF_HWCFGR9,For GPIOA. B. C. D. E. F. G. H. I. and GPIOJ: For GPIOK and GPIOZ:" hexmask.long.word 0x4 0.--15. 1. "EN_IO,EN_IO" line.long 0x8 "GPIOF_HWCFGR8,For GPIOA. B. C. D. E. F. G. H. I. and GPIOJ: For GPIOK and GPIOZ:" hexmask.long.byte 0x8 28.--31. 1. "AF_PRIO15,AF_PRIO15" hexmask.long.byte 0x8 24.--27. 1. "AF_PRIO14,AF_PRIO14" hexmask.long.byte 0x8 20.--23. 1. "AF_PRIO13,AF_PRIO13" hexmask.long.byte 0x8 16.--19. 1. "AF_PRIO12,AF_PRIO12" hexmask.long.byte 0x8 12.--15. 1. "AF_PRIO11,AF_PRIO11" hexmask.long.byte 0x8 8.--11. 1. "AF_PRIO10,AF_PRIO10" hexmask.long.byte 0x8 4.--7. 1. "AF_PRIO9,AF_PRIO9" newline hexmask.long.byte 0x8 0.--3. 1. "AF_PRIO8,AF_PRIO8" line.long 0xC "GPIOF_HWCFGR7,GPIO hardware configuration register 7" hexmask.long.byte 0xC 28.--31. 1. "AF_PRIO7,AF_PRIO7" hexmask.long.byte 0xC 24.--27. 1. "AF_PRIO6,AF_PRIO6" hexmask.long.byte 0xC 20.--23. 1. "AF_PRIO5,AF_PRIO5" hexmask.long.byte 0xC 16.--19. 1. "AF_PRIO4,AF_PRIO4" hexmask.long.byte 0xC 12.--15. 1. "AF_PRIO3,AF_PRIO3" hexmask.long.byte 0xC 8.--11. 1. "AF_PRIO2,AF_PRIO2" hexmask.long.byte 0xC 4.--7. 1. "AF_PRIO1,AF_PRIO1" newline hexmask.long.byte 0xC 0.--3. 1. "AF_PRIO0,AF_PRIO0" line.long 0x10 "GPIOF_HWCFGR6,GPIO hardware configuration register 6" hexmask.long 0x10 0.--31. 1. "MODER_RES,MODER_RES" line.long 0x14 "GPIOF_HWCFGR5,GPIO hardware configuration register 5" hexmask.long 0x14 0.--31. 1. "PUPDR_RES,PUPDR_RES" line.long 0x18 "GPIOF_HWCFGR4,GPIO hardware configuration register 4" hexmask.long 0x18 0.--31. 1. "OSPEED_RES,OSPEED_RES" line.long 0x1C "GPIOF_HWCFGR3,GPIO hardware configuration register 3" hexmask.long.word 0x1C 16.--31. 1. "OTYPER_RES,OTYPER_RES" hexmask.long.word 0x1C 0.--15. 1. "ODR_RES,ODR_RES" line.long 0x20 "GPIOF_HWCFGR2,GPIO hardware configuration register 2" hexmask.long 0x20 0.--31. 1. "AFRL_RES,AFRL_RES" line.long 0x24 "GPIOF_HWCFGR1,GPIO hardware configuration register 1" hexmask.long 0x24 0.--31. 1. "AFRH_RES,AFRH_RES" line.long 0x28 "GPIOF_HWCFGR0,GPIO hardware configuration register 0" hexmask.long.word 0x28 0.--15. 1. "OR_RES,OR_RES" line.long 0x2C "GPIOF_VERR,GPIO version register" hexmask.long.byte 0x2C 4.--7. 1. "MAJREV,MAJREV" hexmask.long.byte 0x2C 0.--3. 1. "MINREV,MINREV" line.long 0x30 "GPIOF_IPIDR,GPIO identification register" hexmask.long 0x30 0.--31. 1. "IPIDR,IPIDR" line.long 0x34 "GPIOF_SIDR,GPIO size identification register" hexmask.long 0x34 0.--31. 1. "SIDR,SIDR" tree.end endif sif (cpuis("STM32MP151*")||cpuis("STM32MP153*")||cpuis("STM32MP157*")) tree "GPIOG" base ad:0x50008000 group.long 0x0++0xF line.long 0x0 "GPIOG_MODER,GPIO port mode register" bitfld.long 0x0 30.--31. "MODER15,MODER15" "0,1,2,3" bitfld.long 0x0 28.--29. "MODER14,MODER14" "0,1,2,3" bitfld.long 0x0 26.--27. "MODER13,MODER13" "0,1,2,3" bitfld.long 0x0 24.--25. "MODER12,MODER12" "0,1,2,3" bitfld.long 0x0 22.--23. "MODER11,MODER11" "0,1,2,3" bitfld.long 0x0 20.--21. "MODER10,MODER10" "0,1,2,3" bitfld.long 0x0 18.--19. "MODER9,MODER9" "0,1,2,3" newline bitfld.long 0x0 16.--17. "MODER8,MODER8" "0,1,2,3" bitfld.long 0x0 14.--15. "MODER7,MODER7" "0,1,2,3" bitfld.long 0x0 12.--13. "MODER6,MODER6" "0,1,2,3" bitfld.long 0x0 10.--11. "MODER5,MODER5" "0,1,2,3" bitfld.long 0x0 8.--9. "MODER4,MODER4" "0,1,2,3" bitfld.long 0x0 6.--7. "MODER3,MODER3" "0,1,2,3" bitfld.long 0x0 4.--5. "MODER2,MODER2" "0,1,2,3" newline bitfld.long 0x0 2.--3. "MODER1,MODER1" "0,1,2,3" bitfld.long 0x0 0.--1. "MODER0,MODER0" "0,1,2,3" line.long 0x4 "GPIOG_OTYPER,GPIO port output type register" bitfld.long 0x4 15. "OT15,OT15" "0,1" bitfld.long 0x4 14. "OT14,OT14" "0,1" bitfld.long 0x4 13. "OT13,OT13" "0,1" bitfld.long 0x4 12. "OT12,OT12" "0,1" bitfld.long 0x4 11. "OT11,OT11" "0,1" bitfld.long 0x4 10. "OT10,OT10" "0,1" bitfld.long 0x4 9. "OT9,OT9" "0,1" newline bitfld.long 0x4 8. "OT8,OT8" "0,1" bitfld.long 0x4 7. "OT7,OT7" "0,1" bitfld.long 0x4 6. "OT6,OT6" "0,1" bitfld.long 0x4 5. "OT5,OT5" "0,1" bitfld.long 0x4 4. "OT4,OT4" "0,1" bitfld.long 0x4 3. "OT3,OT3" "0,1" bitfld.long 0x4 2. "OT2,OT2" "0,1" newline bitfld.long 0x4 1. "OT1,OT1" "0,1" bitfld.long 0x4 0. "OT0,OT0" "0,1" line.long 0x8 "GPIOG_OSPEEDR,GPIO port output speed register" bitfld.long 0x8 30.--31. "OSPEEDR15,OSPEEDR15" "0,1,2,3" bitfld.long 0x8 28.--29. "OSPEEDR14,OSPEEDR14" "0,1,2,3" bitfld.long 0x8 26.--27. "OSPEEDR13,OSPEEDR13" "0,1,2,3" bitfld.long 0x8 24.--25. "OSPEEDR12,OSPEEDR12" "0,1,2,3" bitfld.long 0x8 22.--23. "OSPEEDR11,OSPEEDR11" "0,1,2,3" bitfld.long 0x8 20.--21. "OSPEEDR10,OSPEEDR10" "0,1,2,3" bitfld.long 0x8 18.--19. "OSPEEDR9,OSPEEDR9" "0,1,2,3" newline bitfld.long 0x8 16.--17. "OSPEEDR8,OSPEEDR8" "0,1,2,3" bitfld.long 0x8 14.--15. "OSPEEDR7,OSPEEDR7" "0,1,2,3" bitfld.long 0x8 12.--13. "OSPEEDR6,OSPEEDR6" "0,1,2,3" bitfld.long 0x8 10.--11. "OSPEEDR5,OSPEEDR5" "0,1,2,3" bitfld.long 0x8 8.--9. "OSPEEDR4,OSPEEDR4" "0,1,2,3" bitfld.long 0x8 6.--7. "OSPEEDR3,OSPEEDR3" "0,1,2,3" bitfld.long 0x8 4.--5. "OSPEEDR2,OSPEEDR2" "0,1,2,3" newline bitfld.long 0x8 2.--3. "OSPEEDR1,OSPEEDR1" "0,1,2,3" bitfld.long 0x8 0.--1. "OSPEEDR0,OSPEEDR0" "0,1,2,3" line.long 0xC "GPIOG_PUPDR,GPIO port pull-up/pull-down register" bitfld.long 0xC 30.--31. "PUPDR15,PUPDR15" "0,1,2,3" bitfld.long 0xC 28.--29. "PUPDR14,PUPDR14" "0,1,2,3" bitfld.long 0xC 26.--27. "PUPDR13,PUPDR13" "0,1,2,3" bitfld.long 0xC 24.--25. "PUPDR12,PUPDR12" "0,1,2,3" bitfld.long 0xC 22.--23. "PUPDR11,PUPDR11" "0,1,2,3" bitfld.long 0xC 20.--21. "PUPDR10,PUPDR10" "0,1,2,3" bitfld.long 0xC 18.--19. "PUPDR9,PUPDR9" "0,1,2,3" newline bitfld.long 0xC 16.--17. "PUPDR8,PUPDR8" "0,1,2,3" bitfld.long 0xC 14.--15. "PUPDR7,PUPDR7" "0,1,2,3" bitfld.long 0xC 12.--13. "PUPDR6,PUPDR6" "0,1,2,3" bitfld.long 0xC 10.--11. "PUPDR5,PUPDR5" "0,1,2,3" bitfld.long 0xC 8.--9. "PUPDR4,PUPDR4" "0,1,2,3" bitfld.long 0xC 6.--7. "PUPDR3,PUPDR3" "0,1,2,3" bitfld.long 0xC 4.--5. "PUPDR2,PUPDR2" "0,1,2,3" newline bitfld.long 0xC 2.--3. "PUPDR1,PUPDR1" "0,1,2,3" bitfld.long 0xC 0.--1. "PUPDR0,PUPDR0" "0,1,2,3" rgroup.long 0x10++0x3 line.long 0x0 "GPIOG_IDR,GPIO port input data register" bitfld.long 0x0 15. "IDR15,IDR15" "0,1" bitfld.long 0x0 14. "IDR14,IDR14" "0,1" bitfld.long 0x0 13. "IDR13,IDR13" "0,1" bitfld.long 0x0 12. "IDR12,IDR12" "0,1" bitfld.long 0x0 11. "IDR11,IDR11" "0,1" bitfld.long 0x0 10. "IDR10,IDR10" "0,1" bitfld.long 0x0 9. "IDR9,IDR9" "0,1" newline bitfld.long 0x0 8. "IDR8,IDR8" "0,1" bitfld.long 0x0 7. "IDR7,IDR7" "0,1" bitfld.long 0x0 6. "IDR6,IDR6" "0,1" bitfld.long 0x0 5. "IDR5,IDR5" "0,1" bitfld.long 0x0 4. "IDR4,IDR4" "0,1" bitfld.long 0x0 3. "IDR3,IDR3" "0,1" bitfld.long 0x0 2. "IDR2,IDR2" "0,1" newline bitfld.long 0x0 1. "IDR1,IDR1" "0,1" bitfld.long 0x0 0. "IDR0,IDR0" "0,1" group.long 0x14++0x3 line.long 0x0 "GPIOG_ODR,GPIO port output data register" bitfld.long 0x0 15. "ODR15,ODR15" "0,1" bitfld.long 0x0 14. "ODR14,ODR14" "0,1" bitfld.long 0x0 13. "ODR13,ODR13" "0,1" bitfld.long 0x0 12. "ODR12,ODR12" "0,1" bitfld.long 0x0 11. "ODR11,ODR11" "0,1" bitfld.long 0x0 10. "ODR10,ODR10" "0,1" bitfld.long 0x0 9. "ODR9,ODR9" "0,1" newline bitfld.long 0x0 8. "ODR8,ODR8" "0,1" bitfld.long 0x0 7. "ODR7,ODR7" "0,1" bitfld.long 0x0 6. "ODR6,ODR6" "0,1" bitfld.long 0x0 5. "ODR5,ODR5" "0,1" bitfld.long 0x0 4. "ODR4,ODR4" "0,1" bitfld.long 0x0 3. "ODR3,ODR3" "0,1" bitfld.long 0x0 2. "ODR2,ODR2" "0,1" newline bitfld.long 0x0 1. "ODR1,ODR1" "0,1" bitfld.long 0x0 0. "ODR0,ODR0" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "GPIOG_BSRR,GPIO port bit set/reset register" bitfld.long 0x0 31. "BR15,BR15" "0,1" bitfld.long 0x0 30. "BR14,BR14" "0,1" bitfld.long 0x0 29. "BR13,BR13" "0,1" bitfld.long 0x0 28. "BR12,BR12" "0,1" bitfld.long 0x0 27. "BR11,BR11" "0,1" bitfld.long 0x0 26. "BR10,BR10" "0,1" bitfld.long 0x0 25. "BR9,BR9" "0,1" newline bitfld.long 0x0 24. "BR8,BR8" "0,1" bitfld.long 0x0 23. "BR7,BR7" "0,1" bitfld.long 0x0 22. "BR6,BR6" "0,1" bitfld.long 0x0 21. "BR5,BR5" "0,1" bitfld.long 0x0 20. "BR4,BR4" "0,1" bitfld.long 0x0 19. "BR3,BR3" "0,1" bitfld.long 0x0 18. "BR2,BR2" "0,1" newline bitfld.long 0x0 17. "BR1,BR1" "0,1" bitfld.long 0x0 16. "BR0,BR0" "0,1" bitfld.long 0x0 15. "BS15,BS15" "0,1" bitfld.long 0x0 14. "BS14,BS14" "0,1" bitfld.long 0x0 13. "BS13,BS13" "0,1" bitfld.long 0x0 12. "BS12,BS12" "0,1" bitfld.long 0x0 11. "BS11,BS11" "0,1" newline bitfld.long 0x0 10. "BS10,BS10" "0,1" bitfld.long 0x0 9. "BS9,BS9" "0,1" bitfld.long 0x0 8. "BS8,BS8" "0,1" bitfld.long 0x0 7. "BS7,BS7" "0,1" bitfld.long 0x0 6. "BS6,BS6" "0,1" bitfld.long 0x0 5. "BS5,BS5" "0,1" bitfld.long 0x0 4. "BS4,BS4" "0,1" newline bitfld.long 0x0 3. "BS3,BS3" "0,1" bitfld.long 0x0 2. "BS2,BS2" "0,1" bitfld.long 0x0 1. "BS1,BS1" "0,1" bitfld.long 0x0 0. "BS0,BS0" "0,1" group.long 0x1C++0xB line.long 0x0 "GPIOG_LCKR,This register is used to lock the configuration of the port bits when a correct write sequence is applied to bit 16 (LCKK). The value of bits [15:0] is used to lock the configuration of the GPIO. During the write sequence. the value of.." bitfld.long 0x0 16. "LCKK,LCKK" "0,1" bitfld.long 0x0 15. "LCK15,LCK15" "0,1" bitfld.long 0x0 14. "LCK14,LCK14" "0,1" bitfld.long 0x0 13. "LCK13,LCK13" "0,1" bitfld.long 0x0 12. "LCK12,LCK12" "0,1" bitfld.long 0x0 11. "LCK11,LCK11" "0,1" bitfld.long 0x0 10. "LCK10,LCK10" "0,1" newline bitfld.long 0x0 9. "LCK9,LCK9" "0,1" bitfld.long 0x0 8. "LCK8,LCK8" "0,1" bitfld.long 0x0 7. "LCK7,LCK7" "0,1" bitfld.long 0x0 6. "LCK6,LCK6" "0,1" bitfld.long 0x0 5. "LCK5,LCK5" "0,1" bitfld.long 0x0 4. "LCK4,LCK4" "0,1" bitfld.long 0x0 3. "LCK3,LCK3" "0,1" newline bitfld.long 0x0 2. "LCK2,LCK2" "0,1" bitfld.long 0x0 1. "LCK1,LCK1" "0,1" bitfld.long 0x0 0. "LCK0,LCK0" "0,1" line.long 0x4 "GPIOG_AFRL,GPIO alternate function low register" hexmask.long.byte 0x4 28.--31. 1. "AFR7,AFR7" hexmask.long.byte 0x4 24.--27. 1. "AFR6,AFR6" hexmask.long.byte 0x4 20.--23. 1. "AFR5,AFR5" hexmask.long.byte 0x4 16.--19. 1. "AFR4,AFR4" hexmask.long.byte 0x4 12.--15. 1. "AFR3,AFR3" hexmask.long.byte 0x4 8.--11. 1. "AFR2,AFR2" hexmask.long.byte 0x4 4.--7. 1. "AFR1,AFR1" newline hexmask.long.byte 0x4 0.--3. 1. "AFR0,AFR0" line.long 0x8 "GPIOG_AFRH,GPIO alternate function high register" hexmask.long.byte 0x8 28.--31. 1. "AFR15,AFR15" hexmask.long.byte 0x8 24.--27. 1. "AFR14,AFR14" hexmask.long.byte 0x8 20.--23. 1. "AFR13,AFR13" hexmask.long.byte 0x8 16.--19. 1. "AFR12,AFR12" hexmask.long.byte 0x8 12.--15. 1. "AFR11,AFR11" hexmask.long.byte 0x8 8.--11. 1. "AFR10,AFR10" hexmask.long.byte 0x8 4.--7. 1. "AFR9,AFR9" newline hexmask.long.byte 0x8 0.--3. 1. "AFR8,AFR8" wgroup.long 0x28++0x3 line.long 0x0 "GPIOG_BRR,GPIO port bit reset register" bitfld.long 0x0 15. "BR15,BR15" "0,1" bitfld.long 0x0 14. "BR14,BR14" "0,1" bitfld.long 0x0 13. "BR13,BR13" "0,1" bitfld.long 0x0 12. "BR12,BR12" "0,1" bitfld.long 0x0 11. "BR11,BR11" "0,1" bitfld.long 0x0 10. "BR10,BR10" "0,1" bitfld.long 0x0 9. "BR9,BR9" "0,1" newline bitfld.long 0x0 8. "BR8,BR8" "0,1" bitfld.long 0x0 7. "BR7,BR7" "0,1" bitfld.long 0x0 6. "BR6,BR6" "0,1" bitfld.long 0x0 5. "BR5,BR5" "0,1" bitfld.long 0x0 4. "BR4,BR4" "0,1" bitfld.long 0x0 3. "BR3,BR3" "0,1" bitfld.long 0x0 2. "BR2,BR2" "0,1" newline bitfld.long 0x0 1. "BR1,BR1" "0,1" bitfld.long 0x0 0. "BR0,BR0" "0,1" rgroup.long 0x3C8++0x37 line.long 0x0 "GPIOG_HWCFGR10,For GPIOA. B. C. D. E. F. G. H. I. J and GPIOK: For GPIOZ:" hexmask.long.byte 0x0 20.--23. 1. "OR_CFG,OR_CFG" hexmask.long.byte 0x0 16.--19. 1. "SEC_CFG,SEC_CFG" hexmask.long.byte 0x0 12.--15. 1. "LOCK_CFG,LOCK_CFG" hexmask.long.byte 0x0 8.--11. 1. "SPEED_CFG,SPEED_CFG" hexmask.long.byte 0x0 4.--7. 1. "AF_SIZE,AF_SIZE" hexmask.long.byte 0x0 0.--3. 1. "AHB_IOP,AHB_IOP" line.long 0x4 "GPIOG_HWCFGR9,For GPIOA. B. C. D. E. F. G. H. I. and GPIOJ: For GPIOK and GPIOZ:" hexmask.long.word 0x4 0.--15. 1. "EN_IO,EN_IO" line.long 0x8 "GPIOG_HWCFGR8,For GPIOA. B. C. D. E. F. G. H. I. and GPIOJ: For GPIOK and GPIOZ:" hexmask.long.byte 0x8 28.--31. 1. "AF_PRIO15,AF_PRIO15" hexmask.long.byte 0x8 24.--27. 1. "AF_PRIO14,AF_PRIO14" hexmask.long.byte 0x8 20.--23. 1. "AF_PRIO13,AF_PRIO13" hexmask.long.byte 0x8 16.--19. 1. "AF_PRIO12,AF_PRIO12" hexmask.long.byte 0x8 12.--15. 1. "AF_PRIO11,AF_PRIO11" hexmask.long.byte 0x8 8.--11. 1. "AF_PRIO10,AF_PRIO10" hexmask.long.byte 0x8 4.--7. 1. "AF_PRIO9,AF_PRIO9" newline hexmask.long.byte 0x8 0.--3. 1. "AF_PRIO8,AF_PRIO8" line.long 0xC "GPIOG_HWCFGR7,GPIO hardware configuration register 7" hexmask.long.byte 0xC 28.--31. 1. "AF_PRIO7,AF_PRIO7" hexmask.long.byte 0xC 24.--27. 1. "AF_PRIO6,AF_PRIO6" hexmask.long.byte 0xC 20.--23. 1. "AF_PRIO5,AF_PRIO5" hexmask.long.byte 0xC 16.--19. 1. "AF_PRIO4,AF_PRIO4" hexmask.long.byte 0xC 12.--15. 1. "AF_PRIO3,AF_PRIO3" hexmask.long.byte 0xC 8.--11. 1. "AF_PRIO2,AF_PRIO2" hexmask.long.byte 0xC 4.--7. 1. "AF_PRIO1,AF_PRIO1" newline hexmask.long.byte 0xC 0.--3. 1. "AF_PRIO0,AF_PRIO0" line.long 0x10 "GPIOG_HWCFGR6,GPIO hardware configuration register 6" hexmask.long 0x10 0.--31. 1. "MODER_RES,MODER_RES" line.long 0x14 "GPIOG_HWCFGR5,GPIO hardware configuration register 5" hexmask.long 0x14 0.--31. 1. "PUPDR_RES,PUPDR_RES" line.long 0x18 "GPIOG_HWCFGR4,GPIO hardware configuration register 4" hexmask.long 0x18 0.--31. 1. "OSPEED_RES,OSPEED_RES" line.long 0x1C "GPIOG_HWCFGR3,GPIO hardware configuration register 3" hexmask.long.word 0x1C 16.--31. 1. "OTYPER_RES,OTYPER_RES" hexmask.long.word 0x1C 0.--15. 1. "ODR_RES,ODR_RES" line.long 0x20 "GPIOG_HWCFGR2,GPIO hardware configuration register 2" hexmask.long 0x20 0.--31. 1. "AFRL_RES,AFRL_RES" line.long 0x24 "GPIOG_HWCFGR1,GPIO hardware configuration register 1" hexmask.long 0x24 0.--31. 1. "AFRH_RES,AFRH_RES" line.long 0x28 "GPIOG_HWCFGR0,GPIO hardware configuration register 0" hexmask.long.word 0x28 0.--15. 1. "OR_RES,OR_RES" line.long 0x2C "GPIOG_VERR,GPIO version register" hexmask.long.byte 0x2C 4.--7. 1. "MAJREV,MAJREV" hexmask.long.byte 0x2C 0.--3. 1. "MINREV,MINREV" line.long 0x30 "GPIOG_IPIDR,GPIO identification register" hexmask.long 0x30 0.--31. 1. "IPIDR,IPIDR" line.long 0x34 "GPIOG_SIDR,GPIO size identification register" hexmask.long 0x34 0.--31. 1. "SIDR,SIDR" tree.end endif sif (cpuis("STM32MP151*")||cpuis("STM32MP153*")||cpuis("STM32MP157*")) tree "GPIOH" base ad:0x50009000 group.long 0x0++0xF line.long 0x0 "GPIOH_MODER,GPIO port mode register" bitfld.long 0x0 30.--31. "MODER15,MODER15" "0,1,2,3" bitfld.long 0x0 28.--29. "MODER14,MODER14" "0,1,2,3" bitfld.long 0x0 26.--27. "MODER13,MODER13" "0,1,2,3" bitfld.long 0x0 24.--25. "MODER12,MODER12" "0,1,2,3" bitfld.long 0x0 22.--23. "MODER11,MODER11" "0,1,2,3" bitfld.long 0x0 20.--21. "MODER10,MODER10" "0,1,2,3" bitfld.long 0x0 18.--19. "MODER9,MODER9" "0,1,2,3" newline bitfld.long 0x0 16.--17. "MODER8,MODER8" "0,1,2,3" bitfld.long 0x0 14.--15. "MODER7,MODER7" "0,1,2,3" bitfld.long 0x0 12.--13. "MODER6,MODER6" "0,1,2,3" bitfld.long 0x0 10.--11. "MODER5,MODER5" "0,1,2,3" bitfld.long 0x0 8.--9. "MODER4,MODER4" "0,1,2,3" bitfld.long 0x0 6.--7. "MODER3,MODER3" "0,1,2,3" bitfld.long 0x0 4.--5. "MODER2,MODER2" "0,1,2,3" newline bitfld.long 0x0 2.--3. "MODER1,MODER1" "0,1,2,3" bitfld.long 0x0 0.--1. "MODER0,MODER0" "0,1,2,3" line.long 0x4 "GPIOH_OTYPER,GPIO port output type register" bitfld.long 0x4 15. "OT15,OT15" "0,1" bitfld.long 0x4 14. "OT14,OT14" "0,1" bitfld.long 0x4 13. "OT13,OT13" "0,1" bitfld.long 0x4 12. "OT12,OT12" "0,1" bitfld.long 0x4 11. "OT11,OT11" "0,1" bitfld.long 0x4 10. "OT10,OT10" "0,1" bitfld.long 0x4 9. "OT9,OT9" "0,1" newline bitfld.long 0x4 8. "OT8,OT8" "0,1" bitfld.long 0x4 7. "OT7,OT7" "0,1" bitfld.long 0x4 6. "OT6,OT6" "0,1" bitfld.long 0x4 5. "OT5,OT5" "0,1" bitfld.long 0x4 4. "OT4,OT4" "0,1" bitfld.long 0x4 3. "OT3,OT3" "0,1" bitfld.long 0x4 2. "OT2,OT2" "0,1" newline bitfld.long 0x4 1. "OT1,OT1" "0,1" bitfld.long 0x4 0. "OT0,OT0" "0,1" line.long 0x8 "GPIOH_OSPEEDR,GPIO port output speed register" bitfld.long 0x8 30.--31. "OSPEEDR15,OSPEEDR15" "0,1,2,3" bitfld.long 0x8 28.--29. "OSPEEDR14,OSPEEDR14" "0,1,2,3" bitfld.long 0x8 26.--27. "OSPEEDR13,OSPEEDR13" "0,1,2,3" bitfld.long 0x8 24.--25. "OSPEEDR12,OSPEEDR12" "0,1,2,3" bitfld.long 0x8 22.--23. "OSPEEDR11,OSPEEDR11" "0,1,2,3" bitfld.long 0x8 20.--21. "OSPEEDR10,OSPEEDR10" "0,1,2,3" bitfld.long 0x8 18.--19. "OSPEEDR9,OSPEEDR9" "0,1,2,3" newline bitfld.long 0x8 16.--17. "OSPEEDR8,OSPEEDR8" "0,1,2,3" bitfld.long 0x8 14.--15. "OSPEEDR7,OSPEEDR7" "0,1,2,3" bitfld.long 0x8 12.--13. "OSPEEDR6,OSPEEDR6" "0,1,2,3" bitfld.long 0x8 10.--11. "OSPEEDR5,OSPEEDR5" "0,1,2,3" bitfld.long 0x8 8.--9. "OSPEEDR4,OSPEEDR4" "0,1,2,3" bitfld.long 0x8 6.--7. "OSPEEDR3,OSPEEDR3" "0,1,2,3" bitfld.long 0x8 4.--5. "OSPEEDR2,OSPEEDR2" "0,1,2,3" newline bitfld.long 0x8 2.--3. "OSPEEDR1,OSPEEDR1" "0,1,2,3" bitfld.long 0x8 0.--1. "OSPEEDR0,OSPEEDR0" "0,1,2,3" line.long 0xC "GPIOH_PUPDR,GPIO port pull-up/pull-down register" bitfld.long 0xC 30.--31. "PUPDR15,PUPDR15" "0,1,2,3" bitfld.long 0xC 28.--29. "PUPDR14,PUPDR14" "0,1,2,3" bitfld.long 0xC 26.--27. "PUPDR13,PUPDR13" "0,1,2,3" bitfld.long 0xC 24.--25. "PUPDR12,PUPDR12" "0,1,2,3" bitfld.long 0xC 22.--23. "PUPDR11,PUPDR11" "0,1,2,3" bitfld.long 0xC 20.--21. "PUPDR10,PUPDR10" "0,1,2,3" bitfld.long 0xC 18.--19. "PUPDR9,PUPDR9" "0,1,2,3" newline bitfld.long 0xC 16.--17. "PUPDR8,PUPDR8" "0,1,2,3" bitfld.long 0xC 14.--15. "PUPDR7,PUPDR7" "0,1,2,3" bitfld.long 0xC 12.--13. "PUPDR6,PUPDR6" "0,1,2,3" bitfld.long 0xC 10.--11. "PUPDR5,PUPDR5" "0,1,2,3" bitfld.long 0xC 8.--9. "PUPDR4,PUPDR4" "0,1,2,3" bitfld.long 0xC 6.--7. "PUPDR3,PUPDR3" "0,1,2,3" bitfld.long 0xC 4.--5. "PUPDR2,PUPDR2" "0,1,2,3" newline bitfld.long 0xC 2.--3. "PUPDR1,PUPDR1" "0,1,2,3" bitfld.long 0xC 0.--1. "PUPDR0,PUPDR0" "0,1,2,3" rgroup.long 0x10++0x3 line.long 0x0 "GPIOH_IDR,GPIO port input data register" bitfld.long 0x0 15. "IDR15,IDR15" "0,1" bitfld.long 0x0 14. "IDR14,IDR14" "0,1" bitfld.long 0x0 13. "IDR13,IDR13" "0,1" bitfld.long 0x0 12. "IDR12,IDR12" "0,1" bitfld.long 0x0 11. "IDR11,IDR11" "0,1" bitfld.long 0x0 10. "IDR10,IDR10" "0,1" bitfld.long 0x0 9. "IDR9,IDR9" "0,1" newline bitfld.long 0x0 8. "IDR8,IDR8" "0,1" bitfld.long 0x0 7. "IDR7,IDR7" "0,1" bitfld.long 0x0 6. "IDR6,IDR6" "0,1" bitfld.long 0x0 5. "IDR5,IDR5" "0,1" bitfld.long 0x0 4. "IDR4,IDR4" "0,1" bitfld.long 0x0 3. "IDR3,IDR3" "0,1" bitfld.long 0x0 2. "IDR2,IDR2" "0,1" newline bitfld.long 0x0 1. "IDR1,IDR1" "0,1" bitfld.long 0x0 0. "IDR0,IDR0" "0,1" group.long 0x14++0x3 line.long 0x0 "GPIOH_ODR,GPIO port output data register" bitfld.long 0x0 15. "ODR15,ODR15" "0,1" bitfld.long 0x0 14. "ODR14,ODR14" "0,1" bitfld.long 0x0 13. "ODR13,ODR13" "0,1" bitfld.long 0x0 12. "ODR12,ODR12" "0,1" bitfld.long 0x0 11. "ODR11,ODR11" "0,1" bitfld.long 0x0 10. "ODR10,ODR10" "0,1" bitfld.long 0x0 9. "ODR9,ODR9" "0,1" newline bitfld.long 0x0 8. "ODR8,ODR8" "0,1" bitfld.long 0x0 7. "ODR7,ODR7" "0,1" bitfld.long 0x0 6. "ODR6,ODR6" "0,1" bitfld.long 0x0 5. "ODR5,ODR5" "0,1" bitfld.long 0x0 4. "ODR4,ODR4" "0,1" bitfld.long 0x0 3. "ODR3,ODR3" "0,1" bitfld.long 0x0 2. "ODR2,ODR2" "0,1" newline bitfld.long 0x0 1. "ODR1,ODR1" "0,1" bitfld.long 0x0 0. "ODR0,ODR0" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "GPIOH_BSRR,GPIO port bit set/reset register" bitfld.long 0x0 31. "BR15,BR15" "0,1" bitfld.long 0x0 30. "BR14,BR14" "0,1" bitfld.long 0x0 29. "BR13,BR13" "0,1" bitfld.long 0x0 28. "BR12,BR12" "0,1" bitfld.long 0x0 27. "BR11,BR11" "0,1" bitfld.long 0x0 26. "BR10,BR10" "0,1" bitfld.long 0x0 25. "BR9,BR9" "0,1" newline bitfld.long 0x0 24. "BR8,BR8" "0,1" bitfld.long 0x0 23. "BR7,BR7" "0,1" bitfld.long 0x0 22. "BR6,BR6" "0,1" bitfld.long 0x0 21. "BR5,BR5" "0,1" bitfld.long 0x0 20. "BR4,BR4" "0,1" bitfld.long 0x0 19. "BR3,BR3" "0,1" bitfld.long 0x0 18. "BR2,BR2" "0,1" newline bitfld.long 0x0 17. "BR1,BR1" "0,1" bitfld.long 0x0 16. "BR0,BR0" "0,1" bitfld.long 0x0 15. "BS15,BS15" "0,1" bitfld.long 0x0 14. "BS14,BS14" "0,1" bitfld.long 0x0 13. "BS13,BS13" "0,1" bitfld.long 0x0 12. "BS12,BS12" "0,1" bitfld.long 0x0 11. "BS11,BS11" "0,1" newline bitfld.long 0x0 10. "BS10,BS10" "0,1" bitfld.long 0x0 9. "BS9,BS9" "0,1" bitfld.long 0x0 8. "BS8,BS8" "0,1" bitfld.long 0x0 7. "BS7,BS7" "0,1" bitfld.long 0x0 6. "BS6,BS6" "0,1" bitfld.long 0x0 5. "BS5,BS5" "0,1" bitfld.long 0x0 4. "BS4,BS4" "0,1" newline bitfld.long 0x0 3. "BS3,BS3" "0,1" bitfld.long 0x0 2. "BS2,BS2" "0,1" bitfld.long 0x0 1. "BS1,BS1" "0,1" bitfld.long 0x0 0. "BS0,BS0" "0,1" group.long 0x1C++0xB line.long 0x0 "GPIOH_LCKR,This register is used to lock the configuration of the port bits when a correct write sequence is applied to bit 16 (LCKK). The value of bits [15:0] is used to lock the configuration of the GPIO. During the write sequence. the value of.." bitfld.long 0x0 16. "LCKK,LCKK" "0,1" bitfld.long 0x0 15. "LCK15,LCK15" "0,1" bitfld.long 0x0 14. "LCK14,LCK14" "0,1" bitfld.long 0x0 13. "LCK13,LCK13" "0,1" bitfld.long 0x0 12. "LCK12,LCK12" "0,1" bitfld.long 0x0 11. "LCK11,LCK11" "0,1" bitfld.long 0x0 10. "LCK10,LCK10" "0,1" newline bitfld.long 0x0 9. "LCK9,LCK9" "0,1" bitfld.long 0x0 8. "LCK8,LCK8" "0,1" bitfld.long 0x0 7. "LCK7,LCK7" "0,1" bitfld.long 0x0 6. "LCK6,LCK6" "0,1" bitfld.long 0x0 5. "LCK5,LCK5" "0,1" bitfld.long 0x0 4. "LCK4,LCK4" "0,1" bitfld.long 0x0 3. "LCK3,LCK3" "0,1" newline bitfld.long 0x0 2. "LCK2,LCK2" "0,1" bitfld.long 0x0 1. "LCK1,LCK1" "0,1" bitfld.long 0x0 0. "LCK0,LCK0" "0,1" line.long 0x4 "GPIOH_AFRL,GPIO alternate function low register" hexmask.long.byte 0x4 28.--31. 1. "AFR7,AFR7" hexmask.long.byte 0x4 24.--27. 1. "AFR6,AFR6" hexmask.long.byte 0x4 20.--23. 1. "AFR5,AFR5" hexmask.long.byte 0x4 16.--19. 1. "AFR4,AFR4" hexmask.long.byte 0x4 12.--15. 1. "AFR3,AFR3" hexmask.long.byte 0x4 8.--11. 1. "AFR2,AFR2" hexmask.long.byte 0x4 4.--7. 1. "AFR1,AFR1" newline hexmask.long.byte 0x4 0.--3. 1. "AFR0,AFR0" line.long 0x8 "GPIOH_AFRH,GPIO alternate function high register" hexmask.long.byte 0x8 28.--31. 1. "AFR15,AFR15" hexmask.long.byte 0x8 24.--27. 1. "AFR14,AFR14" hexmask.long.byte 0x8 20.--23. 1. "AFR13,AFR13" hexmask.long.byte 0x8 16.--19. 1. "AFR12,AFR12" hexmask.long.byte 0x8 12.--15. 1. "AFR11,AFR11" hexmask.long.byte 0x8 8.--11. 1. "AFR10,AFR10" hexmask.long.byte 0x8 4.--7. 1. "AFR9,AFR9" newline hexmask.long.byte 0x8 0.--3. 1. "AFR8,AFR8" wgroup.long 0x28++0x3 line.long 0x0 "GPIOH_BRR,GPIO port bit reset register" bitfld.long 0x0 15. "BR15,BR15" "0,1" bitfld.long 0x0 14. "BR14,BR14" "0,1" bitfld.long 0x0 13. "BR13,BR13" "0,1" bitfld.long 0x0 12. "BR12,BR12" "0,1" bitfld.long 0x0 11. "BR11,BR11" "0,1" bitfld.long 0x0 10. "BR10,BR10" "0,1" bitfld.long 0x0 9. "BR9,BR9" "0,1" newline bitfld.long 0x0 8. "BR8,BR8" "0,1" bitfld.long 0x0 7. "BR7,BR7" "0,1" bitfld.long 0x0 6. "BR6,BR6" "0,1" bitfld.long 0x0 5. "BR5,BR5" "0,1" bitfld.long 0x0 4. "BR4,BR4" "0,1" bitfld.long 0x0 3. "BR3,BR3" "0,1" bitfld.long 0x0 2. "BR2,BR2" "0,1" newline bitfld.long 0x0 1. "BR1,BR1" "0,1" bitfld.long 0x0 0. "BR0,BR0" "0,1" rgroup.long 0x3C8++0x37 line.long 0x0 "GPIOH_HWCFGR10,For GPIOA. B. C. D. E. F. G. H. I. J and GPIOK: For GPIOZ:" hexmask.long.byte 0x0 20.--23. 1. "OR_CFG,OR_CFG" hexmask.long.byte 0x0 16.--19. 1. "SEC_CFG,SEC_CFG" hexmask.long.byte 0x0 12.--15. 1. "LOCK_CFG,LOCK_CFG" hexmask.long.byte 0x0 8.--11. 1. "SPEED_CFG,SPEED_CFG" hexmask.long.byte 0x0 4.--7. 1. "AF_SIZE,AF_SIZE" hexmask.long.byte 0x0 0.--3. 1. "AHB_IOP,AHB_IOP" line.long 0x4 "GPIOH_HWCFGR9,For GPIOA. B. C. D. E. F. G. H. I. and GPIOJ: For GPIOK and GPIOZ:" hexmask.long.word 0x4 0.--15. 1. "EN_IO,EN_IO" line.long 0x8 "GPIOH_HWCFGR8,For GPIOA. B. C. D. E. F. G. H. I. and GPIOJ: For GPIOK and GPIOZ:" hexmask.long.byte 0x8 28.--31. 1. "AF_PRIO15,AF_PRIO15" hexmask.long.byte 0x8 24.--27. 1. "AF_PRIO14,AF_PRIO14" hexmask.long.byte 0x8 20.--23. 1. "AF_PRIO13,AF_PRIO13" hexmask.long.byte 0x8 16.--19. 1. "AF_PRIO12,AF_PRIO12" hexmask.long.byte 0x8 12.--15. 1. "AF_PRIO11,AF_PRIO11" hexmask.long.byte 0x8 8.--11. 1. "AF_PRIO10,AF_PRIO10" hexmask.long.byte 0x8 4.--7. 1. "AF_PRIO9,AF_PRIO9" newline hexmask.long.byte 0x8 0.--3. 1. "AF_PRIO8,AF_PRIO8" line.long 0xC "GPIOH_HWCFGR7,GPIO hardware configuration register 7" hexmask.long.byte 0xC 28.--31. 1. "AF_PRIO7,AF_PRIO7" hexmask.long.byte 0xC 24.--27. 1. "AF_PRIO6,AF_PRIO6" hexmask.long.byte 0xC 20.--23. 1. "AF_PRIO5,AF_PRIO5" hexmask.long.byte 0xC 16.--19. 1. "AF_PRIO4,AF_PRIO4" hexmask.long.byte 0xC 12.--15. 1. "AF_PRIO3,AF_PRIO3" hexmask.long.byte 0xC 8.--11. 1. "AF_PRIO2,AF_PRIO2" hexmask.long.byte 0xC 4.--7. 1. "AF_PRIO1,AF_PRIO1" newline hexmask.long.byte 0xC 0.--3. 1. "AF_PRIO0,AF_PRIO0" line.long 0x10 "GPIOH_HWCFGR6,GPIO hardware configuration register 6" hexmask.long 0x10 0.--31. 1. "MODER_RES,MODER_RES" line.long 0x14 "GPIOH_HWCFGR5,GPIO hardware configuration register 5" hexmask.long 0x14 0.--31. 1. "PUPDR_RES,PUPDR_RES" line.long 0x18 "GPIOH_HWCFGR4,GPIO hardware configuration register 4" hexmask.long 0x18 0.--31. 1. "OSPEED_RES,OSPEED_RES" line.long 0x1C "GPIOH_HWCFGR3,GPIO hardware configuration register 3" hexmask.long.word 0x1C 16.--31. 1. "OTYPER_RES,OTYPER_RES" hexmask.long.word 0x1C 0.--15. 1. "ODR_RES,ODR_RES" line.long 0x20 "GPIOH_HWCFGR2,GPIO hardware configuration register 2" hexmask.long 0x20 0.--31. 1. "AFRL_RES,AFRL_RES" line.long 0x24 "GPIOH_HWCFGR1,GPIO hardware configuration register 1" hexmask.long 0x24 0.--31. 1. "AFRH_RES,AFRH_RES" line.long 0x28 "GPIOH_HWCFGR0,GPIO hardware configuration register 0" hexmask.long.word 0x28 0.--15. 1. "OR_RES,OR_RES" line.long 0x2C "GPIOH_VERR,GPIO version register" hexmask.long.byte 0x2C 4.--7. 1. "MAJREV,MAJREV" hexmask.long.byte 0x2C 0.--3. 1. "MINREV,MINREV" line.long 0x30 "GPIOH_IPIDR,GPIO identification register" hexmask.long 0x30 0.--31. 1. "IPIDR,IPIDR" line.long 0x34 "GPIOH_SIDR,GPIO size identification register" hexmask.long 0x34 0.--31. 1. "SIDR,SIDR" tree.end endif sif (cpuis("STM32MP151*")||cpuis("STM32MP153*")||cpuis("STM32MP157*")) tree "GPIOI" base ad:0x5000A000 group.long 0x0++0xF line.long 0x0 "GPIOI_MODER,GPIO port mode register" bitfld.long 0x0 30.--31. "MODER15,MODER15" "0,1,2,3" bitfld.long 0x0 28.--29. "MODER14,MODER14" "0,1,2,3" bitfld.long 0x0 26.--27. "MODER13,MODER13" "0,1,2,3" bitfld.long 0x0 24.--25. "MODER12,MODER12" "0,1,2,3" bitfld.long 0x0 22.--23. "MODER11,MODER11" "0,1,2,3" bitfld.long 0x0 20.--21. "MODER10,MODER10" "0,1,2,3" bitfld.long 0x0 18.--19. "MODER9,MODER9" "0,1,2,3" newline bitfld.long 0x0 16.--17. "MODER8,MODER8" "0,1,2,3" bitfld.long 0x0 14.--15. "MODER7,MODER7" "0,1,2,3" bitfld.long 0x0 12.--13. "MODER6,MODER6" "0,1,2,3" bitfld.long 0x0 10.--11. "MODER5,MODER5" "0,1,2,3" bitfld.long 0x0 8.--9. "MODER4,MODER4" "0,1,2,3" bitfld.long 0x0 6.--7. "MODER3,MODER3" "0,1,2,3" bitfld.long 0x0 4.--5. "MODER2,MODER2" "0,1,2,3" newline bitfld.long 0x0 2.--3. "MODER1,MODER1" "0,1,2,3" bitfld.long 0x0 0.--1. "MODER0,MODER0" "0,1,2,3" line.long 0x4 "GPIOI_OTYPER,GPIO port output type register" bitfld.long 0x4 15. "OT15,OT15" "0,1" bitfld.long 0x4 14. "OT14,OT14" "0,1" bitfld.long 0x4 13. "OT13,OT13" "0,1" bitfld.long 0x4 12. "OT12,OT12" "0,1" bitfld.long 0x4 11. "OT11,OT11" "0,1" bitfld.long 0x4 10. "OT10,OT10" "0,1" bitfld.long 0x4 9. "OT9,OT9" "0,1" newline bitfld.long 0x4 8. "OT8,OT8" "0,1" bitfld.long 0x4 7. "OT7,OT7" "0,1" bitfld.long 0x4 6. "OT6,OT6" "0,1" bitfld.long 0x4 5. "OT5,OT5" "0,1" bitfld.long 0x4 4. "OT4,OT4" "0,1" bitfld.long 0x4 3. "OT3,OT3" "0,1" bitfld.long 0x4 2. "OT2,OT2" "0,1" newline bitfld.long 0x4 1. "OT1,OT1" "0,1" bitfld.long 0x4 0. "OT0,OT0" "0,1" line.long 0x8 "GPIOI_OSPEEDR,GPIO port output speed register" bitfld.long 0x8 30.--31. "OSPEEDR15,OSPEEDR15" "0,1,2,3" bitfld.long 0x8 28.--29. "OSPEEDR14,OSPEEDR14" "0,1,2,3" bitfld.long 0x8 26.--27. "OSPEEDR13,OSPEEDR13" "0,1,2,3" bitfld.long 0x8 24.--25. "OSPEEDR12,OSPEEDR12" "0,1,2,3" bitfld.long 0x8 22.--23. "OSPEEDR11,OSPEEDR11" "0,1,2,3" bitfld.long 0x8 20.--21. "OSPEEDR10,OSPEEDR10" "0,1,2,3" bitfld.long 0x8 18.--19. "OSPEEDR9,OSPEEDR9" "0,1,2,3" newline bitfld.long 0x8 16.--17. "OSPEEDR8,OSPEEDR8" "0,1,2,3" bitfld.long 0x8 14.--15. "OSPEEDR7,OSPEEDR7" "0,1,2,3" bitfld.long 0x8 12.--13. "OSPEEDR6,OSPEEDR6" "0,1,2,3" bitfld.long 0x8 10.--11. "OSPEEDR5,OSPEEDR5" "0,1,2,3" bitfld.long 0x8 8.--9. "OSPEEDR4,OSPEEDR4" "0,1,2,3" bitfld.long 0x8 6.--7. "OSPEEDR3,OSPEEDR3" "0,1,2,3" bitfld.long 0x8 4.--5. "OSPEEDR2,OSPEEDR2" "0,1,2,3" newline bitfld.long 0x8 2.--3. "OSPEEDR1,OSPEEDR1" "0,1,2,3" bitfld.long 0x8 0.--1. "OSPEEDR0,OSPEEDR0" "0,1,2,3" line.long 0xC "GPIOI_PUPDR,GPIO port pull-up/pull-down register" bitfld.long 0xC 30.--31. "PUPDR15,PUPDR15" "0,1,2,3" bitfld.long 0xC 28.--29. "PUPDR14,PUPDR14" "0,1,2,3" bitfld.long 0xC 26.--27. "PUPDR13,PUPDR13" "0,1,2,3" bitfld.long 0xC 24.--25. "PUPDR12,PUPDR12" "0,1,2,3" bitfld.long 0xC 22.--23. "PUPDR11,PUPDR11" "0,1,2,3" bitfld.long 0xC 20.--21. "PUPDR10,PUPDR10" "0,1,2,3" bitfld.long 0xC 18.--19. "PUPDR9,PUPDR9" "0,1,2,3" newline bitfld.long 0xC 16.--17. "PUPDR8,PUPDR8" "0,1,2,3" bitfld.long 0xC 14.--15. "PUPDR7,PUPDR7" "0,1,2,3" bitfld.long 0xC 12.--13. "PUPDR6,PUPDR6" "0,1,2,3" bitfld.long 0xC 10.--11. "PUPDR5,PUPDR5" "0,1,2,3" bitfld.long 0xC 8.--9. "PUPDR4,PUPDR4" "0,1,2,3" bitfld.long 0xC 6.--7. "PUPDR3,PUPDR3" "0,1,2,3" bitfld.long 0xC 4.--5. "PUPDR2,PUPDR2" "0,1,2,3" newline bitfld.long 0xC 2.--3. "PUPDR1,PUPDR1" "0,1,2,3" bitfld.long 0xC 0.--1. "PUPDR0,PUPDR0" "0,1,2,3" rgroup.long 0x10++0x3 line.long 0x0 "GPIOI_IDR,GPIO port input data register" bitfld.long 0x0 15. "IDR15,IDR15" "0,1" bitfld.long 0x0 14. "IDR14,IDR14" "0,1" bitfld.long 0x0 13. "IDR13,IDR13" "0,1" bitfld.long 0x0 12. "IDR12,IDR12" "0,1" bitfld.long 0x0 11. "IDR11,IDR11" "0,1" bitfld.long 0x0 10. "IDR10,IDR10" "0,1" bitfld.long 0x0 9. "IDR9,IDR9" "0,1" newline bitfld.long 0x0 8. "IDR8,IDR8" "0,1" bitfld.long 0x0 7. "IDR7,IDR7" "0,1" bitfld.long 0x0 6. "IDR6,IDR6" "0,1" bitfld.long 0x0 5. "IDR5,IDR5" "0,1" bitfld.long 0x0 4. "IDR4,IDR4" "0,1" bitfld.long 0x0 3. "IDR3,IDR3" "0,1" bitfld.long 0x0 2. "IDR2,IDR2" "0,1" newline bitfld.long 0x0 1. "IDR1,IDR1" "0,1" bitfld.long 0x0 0. "IDR0,IDR0" "0,1" group.long 0x14++0x3 line.long 0x0 "GPIOI_ODR,GPIO port output data register" bitfld.long 0x0 15. "ODR15,ODR15" "0,1" bitfld.long 0x0 14. "ODR14,ODR14" "0,1" bitfld.long 0x0 13. "ODR13,ODR13" "0,1" bitfld.long 0x0 12. "ODR12,ODR12" "0,1" bitfld.long 0x0 11. "ODR11,ODR11" "0,1" bitfld.long 0x0 10. "ODR10,ODR10" "0,1" bitfld.long 0x0 9. "ODR9,ODR9" "0,1" newline bitfld.long 0x0 8. "ODR8,ODR8" "0,1" bitfld.long 0x0 7. "ODR7,ODR7" "0,1" bitfld.long 0x0 6. "ODR6,ODR6" "0,1" bitfld.long 0x0 5. "ODR5,ODR5" "0,1" bitfld.long 0x0 4. "ODR4,ODR4" "0,1" bitfld.long 0x0 3. "ODR3,ODR3" "0,1" bitfld.long 0x0 2. "ODR2,ODR2" "0,1" newline bitfld.long 0x0 1. "ODR1,ODR1" "0,1" bitfld.long 0x0 0. "ODR0,ODR0" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "GPIOI_BSRR,GPIO port bit set/reset register" bitfld.long 0x0 31. "BR15,BR15" "0,1" bitfld.long 0x0 30. "BR14,BR14" "0,1" bitfld.long 0x0 29. "BR13,BR13" "0,1" bitfld.long 0x0 28. "BR12,BR12" "0,1" bitfld.long 0x0 27. "BR11,BR11" "0,1" bitfld.long 0x0 26. "BR10,BR10" "0,1" bitfld.long 0x0 25. "BR9,BR9" "0,1" newline bitfld.long 0x0 24. "BR8,BR8" "0,1" bitfld.long 0x0 23. "BR7,BR7" "0,1" bitfld.long 0x0 22. "BR6,BR6" "0,1" bitfld.long 0x0 21. "BR5,BR5" "0,1" bitfld.long 0x0 20. "BR4,BR4" "0,1" bitfld.long 0x0 19. "BR3,BR3" "0,1" bitfld.long 0x0 18. "BR2,BR2" "0,1" newline bitfld.long 0x0 17. "BR1,BR1" "0,1" bitfld.long 0x0 16. "BR0,BR0" "0,1" bitfld.long 0x0 15. "BS15,BS15" "0,1" bitfld.long 0x0 14. "BS14,BS14" "0,1" bitfld.long 0x0 13. "BS13,BS13" "0,1" bitfld.long 0x0 12. "BS12,BS12" "0,1" bitfld.long 0x0 11. "BS11,BS11" "0,1" newline bitfld.long 0x0 10. "BS10,BS10" "0,1" bitfld.long 0x0 9. "BS9,BS9" "0,1" bitfld.long 0x0 8. "BS8,BS8" "0,1" bitfld.long 0x0 7. "BS7,BS7" "0,1" bitfld.long 0x0 6. "BS6,BS6" "0,1" bitfld.long 0x0 5. "BS5,BS5" "0,1" bitfld.long 0x0 4. "BS4,BS4" "0,1" newline bitfld.long 0x0 3. "BS3,BS3" "0,1" bitfld.long 0x0 2. "BS2,BS2" "0,1" bitfld.long 0x0 1. "BS1,BS1" "0,1" bitfld.long 0x0 0. "BS0,BS0" "0,1" group.long 0x1C++0xB line.long 0x0 "GPIOI_LCKR,This register is used to lock the configuration of the port bits when a correct write sequence is applied to bit 16 (LCKK). The value of bits [15:0] is used to lock the configuration of the GPIO. During the write sequence. the value of.." bitfld.long 0x0 16. "LCKK,LCKK" "0,1" bitfld.long 0x0 15. "LCK15,LCK15" "0,1" bitfld.long 0x0 14. "LCK14,LCK14" "0,1" bitfld.long 0x0 13. "LCK13,LCK13" "0,1" bitfld.long 0x0 12. "LCK12,LCK12" "0,1" bitfld.long 0x0 11. "LCK11,LCK11" "0,1" bitfld.long 0x0 10. "LCK10,LCK10" "0,1" newline bitfld.long 0x0 9. "LCK9,LCK9" "0,1" bitfld.long 0x0 8. "LCK8,LCK8" "0,1" bitfld.long 0x0 7. "LCK7,LCK7" "0,1" bitfld.long 0x0 6. "LCK6,LCK6" "0,1" bitfld.long 0x0 5. "LCK5,LCK5" "0,1" bitfld.long 0x0 4. "LCK4,LCK4" "0,1" bitfld.long 0x0 3. "LCK3,LCK3" "0,1" newline bitfld.long 0x0 2. "LCK2,LCK2" "0,1" bitfld.long 0x0 1. "LCK1,LCK1" "0,1" bitfld.long 0x0 0. "LCK0,LCK0" "0,1" line.long 0x4 "GPIOI_AFRL,GPIO alternate function low register" hexmask.long.byte 0x4 28.--31. 1. "AFR7,AFR7" hexmask.long.byte 0x4 24.--27. 1. "AFR6,AFR6" hexmask.long.byte 0x4 20.--23. 1. "AFR5,AFR5" hexmask.long.byte 0x4 16.--19. 1. "AFR4,AFR4" hexmask.long.byte 0x4 12.--15. 1. "AFR3,AFR3" hexmask.long.byte 0x4 8.--11. 1. "AFR2,AFR2" hexmask.long.byte 0x4 4.--7. 1. "AFR1,AFR1" newline hexmask.long.byte 0x4 0.--3. 1. "AFR0,AFR0" line.long 0x8 "GPIOI_AFRH,GPIO alternate function high register" hexmask.long.byte 0x8 28.--31. 1. "AFR15,AFR15" hexmask.long.byte 0x8 24.--27. 1. "AFR14,AFR14" hexmask.long.byte 0x8 20.--23. 1. "AFR13,AFR13" hexmask.long.byte 0x8 16.--19. 1. "AFR12,AFR12" hexmask.long.byte 0x8 12.--15. 1. "AFR11,AFR11" hexmask.long.byte 0x8 8.--11. 1. "AFR10,AFR10" hexmask.long.byte 0x8 4.--7. 1. "AFR9,AFR9" newline hexmask.long.byte 0x8 0.--3. 1. "AFR8,AFR8" wgroup.long 0x28++0x3 line.long 0x0 "GPIOI_BRR,GPIO port bit reset register" bitfld.long 0x0 15. "BR15,BR15" "0,1" bitfld.long 0x0 14. "BR14,BR14" "0,1" bitfld.long 0x0 13. "BR13,BR13" "0,1" bitfld.long 0x0 12. "BR12,BR12" "0,1" bitfld.long 0x0 11. "BR11,BR11" "0,1" bitfld.long 0x0 10. "BR10,BR10" "0,1" bitfld.long 0x0 9. "BR9,BR9" "0,1" newline bitfld.long 0x0 8. "BR8,BR8" "0,1" bitfld.long 0x0 7. "BR7,BR7" "0,1" bitfld.long 0x0 6. "BR6,BR6" "0,1" bitfld.long 0x0 5. "BR5,BR5" "0,1" bitfld.long 0x0 4. "BR4,BR4" "0,1" bitfld.long 0x0 3. "BR3,BR3" "0,1" bitfld.long 0x0 2. "BR2,BR2" "0,1" newline bitfld.long 0x0 1. "BR1,BR1" "0,1" bitfld.long 0x0 0. "BR0,BR0" "0,1" rgroup.long 0x3C8++0x37 line.long 0x0 "GPIOI_HWCFGR10,For GPIOA. B. C. D. E. F. G. H. I. J and GPIOK: For GPIOZ:" hexmask.long.byte 0x0 20.--23. 1. "OR_CFG,OR_CFG" hexmask.long.byte 0x0 16.--19. 1. "SEC_CFG,SEC_CFG" hexmask.long.byte 0x0 12.--15. 1. "LOCK_CFG,LOCK_CFG" hexmask.long.byte 0x0 8.--11. 1. "SPEED_CFG,SPEED_CFG" hexmask.long.byte 0x0 4.--7. 1. "AF_SIZE,AF_SIZE" hexmask.long.byte 0x0 0.--3. 1. "AHB_IOP,AHB_IOP" line.long 0x4 "GPIOI_HWCFGR9,For GPIOA. B. C. D. E. F. G. H. I. and GPIOJ: For GPIOK and GPIOZ:" hexmask.long.word 0x4 0.--15. 1. "EN_IO,EN_IO" line.long 0x8 "GPIOI_HWCFGR8,For GPIOA. B. C. D. E. F. G. H. I. and GPIOJ: For GPIOK and GPIOZ:" hexmask.long.byte 0x8 28.--31. 1. "AF_PRIO15,AF_PRIO15" hexmask.long.byte 0x8 24.--27. 1. "AF_PRIO14,AF_PRIO14" hexmask.long.byte 0x8 20.--23. 1. "AF_PRIO13,AF_PRIO13" hexmask.long.byte 0x8 16.--19. 1. "AF_PRIO12,AF_PRIO12" hexmask.long.byte 0x8 12.--15. 1. "AF_PRIO11,AF_PRIO11" hexmask.long.byte 0x8 8.--11. 1. "AF_PRIO10,AF_PRIO10" hexmask.long.byte 0x8 4.--7. 1. "AF_PRIO9,AF_PRIO9" newline hexmask.long.byte 0x8 0.--3. 1. "AF_PRIO8,AF_PRIO8" line.long 0xC "GPIOI_HWCFGR7,GPIO hardware configuration register 7" hexmask.long.byte 0xC 28.--31. 1. "AF_PRIO7,AF_PRIO7" hexmask.long.byte 0xC 24.--27. 1. "AF_PRIO6,AF_PRIO6" hexmask.long.byte 0xC 20.--23. 1. "AF_PRIO5,AF_PRIO5" hexmask.long.byte 0xC 16.--19. 1. "AF_PRIO4,AF_PRIO4" hexmask.long.byte 0xC 12.--15. 1. "AF_PRIO3,AF_PRIO3" hexmask.long.byte 0xC 8.--11. 1. "AF_PRIO2,AF_PRIO2" hexmask.long.byte 0xC 4.--7. 1. "AF_PRIO1,AF_PRIO1" newline hexmask.long.byte 0xC 0.--3. 1. "AF_PRIO0,AF_PRIO0" line.long 0x10 "GPIOI_HWCFGR6,GPIO hardware configuration register 6" hexmask.long 0x10 0.--31. 1. "MODER_RES,MODER_RES" line.long 0x14 "GPIOI_HWCFGR5,GPIO hardware configuration register 5" hexmask.long 0x14 0.--31. 1. "PUPDR_RES,PUPDR_RES" line.long 0x18 "GPIOI_HWCFGR4,GPIO hardware configuration register 4" hexmask.long 0x18 0.--31. 1. "OSPEED_RES,OSPEED_RES" line.long 0x1C "GPIOI_HWCFGR3,GPIO hardware configuration register 3" hexmask.long.word 0x1C 16.--31. 1. "OTYPER_RES,OTYPER_RES" hexmask.long.word 0x1C 0.--15. 1. "ODR_RES,ODR_RES" line.long 0x20 "GPIOI_HWCFGR2,GPIO hardware configuration register 2" hexmask.long 0x20 0.--31. 1. "AFRL_RES,AFRL_RES" line.long 0x24 "GPIOI_HWCFGR1,GPIO hardware configuration register 1" hexmask.long 0x24 0.--31. 1. "AFRH_RES,AFRH_RES" line.long 0x28 "GPIOI_HWCFGR0,GPIO hardware configuration register 0" hexmask.long.word 0x28 0.--15. 1. "OR_RES,OR_RES" line.long 0x2C "GPIOI_VERR,GPIO version register" hexmask.long.byte 0x2C 4.--7. 1. "MAJREV,MAJREV" hexmask.long.byte 0x2C 0.--3. 1. "MINREV,MINREV" line.long 0x30 "GPIOI_IPIDR,GPIO identification register" hexmask.long 0x30 0.--31. 1. "IPIDR,IPIDR" line.long 0x34 "GPIOI_SIDR,GPIO size identification register" hexmask.long 0x34 0.--31. 1. "SIDR,SIDR" tree.end endif sif (cpuis("STM32MP151*")||cpuis("STM32MP153*")||cpuis("STM32MP157*")) tree "GPIOJ" base ad:0x5000B000 group.long 0x0++0xF line.long 0x0 "GPIOJ_MODER,GPIO port mode register" bitfld.long 0x0 30.--31. "MODER15,MODER15" "0,1,2,3" bitfld.long 0x0 28.--29. "MODER14,MODER14" "0,1,2,3" bitfld.long 0x0 26.--27. "MODER13,MODER13" "0,1,2,3" bitfld.long 0x0 24.--25. "MODER12,MODER12" "0,1,2,3" bitfld.long 0x0 22.--23. "MODER11,MODER11" "0,1,2,3" bitfld.long 0x0 20.--21. "MODER10,MODER10" "0,1,2,3" bitfld.long 0x0 18.--19. "MODER9,MODER9" "0,1,2,3" newline bitfld.long 0x0 16.--17. "MODER8,MODER8" "0,1,2,3" bitfld.long 0x0 14.--15. "MODER7,MODER7" "0,1,2,3" bitfld.long 0x0 12.--13. "MODER6,MODER6" "0,1,2,3" bitfld.long 0x0 10.--11. "MODER5,MODER5" "0,1,2,3" bitfld.long 0x0 8.--9. "MODER4,MODER4" "0,1,2,3" bitfld.long 0x0 6.--7. "MODER3,MODER3" "0,1,2,3" bitfld.long 0x0 4.--5. "MODER2,MODER2" "0,1,2,3" newline bitfld.long 0x0 2.--3. "MODER1,MODER1" "0,1,2,3" bitfld.long 0x0 0.--1. "MODER0,MODER0" "0,1,2,3" line.long 0x4 "GPIOJ_OTYPER,GPIO port output type register" bitfld.long 0x4 15. "OT15,OT15" "0,1" bitfld.long 0x4 14. "OT14,OT14" "0,1" bitfld.long 0x4 13. "OT13,OT13" "0,1" bitfld.long 0x4 12. "OT12,OT12" "0,1" bitfld.long 0x4 11. "OT11,OT11" "0,1" bitfld.long 0x4 10. "OT10,OT10" "0,1" bitfld.long 0x4 9. "OT9,OT9" "0,1" newline bitfld.long 0x4 8. "OT8,OT8" "0,1" bitfld.long 0x4 7. "OT7,OT7" "0,1" bitfld.long 0x4 6. "OT6,OT6" "0,1" bitfld.long 0x4 5. "OT5,OT5" "0,1" bitfld.long 0x4 4. "OT4,OT4" "0,1" bitfld.long 0x4 3. "OT3,OT3" "0,1" bitfld.long 0x4 2. "OT2,OT2" "0,1" newline bitfld.long 0x4 1. "OT1,OT1" "0,1" bitfld.long 0x4 0. "OT0,OT0" "0,1" line.long 0x8 "GPIOJ_OSPEEDR,GPIO port output speed register" bitfld.long 0x8 30.--31. "OSPEEDR15,OSPEEDR15" "0,1,2,3" bitfld.long 0x8 28.--29. "OSPEEDR14,OSPEEDR14" "0,1,2,3" bitfld.long 0x8 26.--27. "OSPEEDR13,OSPEEDR13" "0,1,2,3" bitfld.long 0x8 24.--25. "OSPEEDR12,OSPEEDR12" "0,1,2,3" bitfld.long 0x8 22.--23. "OSPEEDR11,OSPEEDR11" "0,1,2,3" bitfld.long 0x8 20.--21. "OSPEEDR10,OSPEEDR10" "0,1,2,3" bitfld.long 0x8 18.--19. "OSPEEDR9,OSPEEDR9" "0,1,2,3" newline bitfld.long 0x8 16.--17. "OSPEEDR8,OSPEEDR8" "0,1,2,3" bitfld.long 0x8 14.--15. "OSPEEDR7,OSPEEDR7" "0,1,2,3" bitfld.long 0x8 12.--13. "OSPEEDR6,OSPEEDR6" "0,1,2,3" bitfld.long 0x8 10.--11. "OSPEEDR5,OSPEEDR5" "0,1,2,3" bitfld.long 0x8 8.--9. "OSPEEDR4,OSPEEDR4" "0,1,2,3" bitfld.long 0x8 6.--7. "OSPEEDR3,OSPEEDR3" "0,1,2,3" bitfld.long 0x8 4.--5. "OSPEEDR2,OSPEEDR2" "0,1,2,3" newline bitfld.long 0x8 2.--3. "OSPEEDR1,OSPEEDR1" "0,1,2,3" bitfld.long 0x8 0.--1. "OSPEEDR0,OSPEEDR0" "0,1,2,3" line.long 0xC "GPIOJ_PUPDR,GPIO port pull-up/pull-down register" bitfld.long 0xC 30.--31. "PUPDR15,PUPDR15" "0,1,2,3" bitfld.long 0xC 28.--29. "PUPDR14,PUPDR14" "0,1,2,3" bitfld.long 0xC 26.--27. "PUPDR13,PUPDR13" "0,1,2,3" bitfld.long 0xC 24.--25. "PUPDR12,PUPDR12" "0,1,2,3" bitfld.long 0xC 22.--23. "PUPDR11,PUPDR11" "0,1,2,3" bitfld.long 0xC 20.--21. "PUPDR10,PUPDR10" "0,1,2,3" bitfld.long 0xC 18.--19. "PUPDR9,PUPDR9" "0,1,2,3" newline bitfld.long 0xC 16.--17. "PUPDR8,PUPDR8" "0,1,2,3" bitfld.long 0xC 14.--15. "PUPDR7,PUPDR7" "0,1,2,3" bitfld.long 0xC 12.--13. "PUPDR6,PUPDR6" "0,1,2,3" bitfld.long 0xC 10.--11. "PUPDR5,PUPDR5" "0,1,2,3" bitfld.long 0xC 8.--9. "PUPDR4,PUPDR4" "0,1,2,3" bitfld.long 0xC 6.--7. "PUPDR3,PUPDR3" "0,1,2,3" bitfld.long 0xC 4.--5. "PUPDR2,PUPDR2" "0,1,2,3" newline bitfld.long 0xC 2.--3. "PUPDR1,PUPDR1" "0,1,2,3" bitfld.long 0xC 0.--1. "PUPDR0,PUPDR0" "0,1,2,3" rgroup.long 0x10++0x3 line.long 0x0 "GPIOJ_IDR,GPIO port input data register" bitfld.long 0x0 15. "IDR15,IDR15" "0,1" bitfld.long 0x0 14. "IDR14,IDR14" "0,1" bitfld.long 0x0 13. "IDR13,IDR13" "0,1" bitfld.long 0x0 12. "IDR12,IDR12" "0,1" bitfld.long 0x0 11. "IDR11,IDR11" "0,1" bitfld.long 0x0 10. "IDR10,IDR10" "0,1" bitfld.long 0x0 9. "IDR9,IDR9" "0,1" newline bitfld.long 0x0 8. "IDR8,IDR8" "0,1" bitfld.long 0x0 7. "IDR7,IDR7" "0,1" bitfld.long 0x0 6. "IDR6,IDR6" "0,1" bitfld.long 0x0 5. "IDR5,IDR5" "0,1" bitfld.long 0x0 4. "IDR4,IDR4" "0,1" bitfld.long 0x0 3. "IDR3,IDR3" "0,1" bitfld.long 0x0 2. "IDR2,IDR2" "0,1" newline bitfld.long 0x0 1. "IDR1,IDR1" "0,1" bitfld.long 0x0 0. "IDR0,IDR0" "0,1" group.long 0x14++0x3 line.long 0x0 "GPIOJ_ODR,GPIO port output data register" bitfld.long 0x0 15. "ODR15,ODR15" "0,1" bitfld.long 0x0 14. "ODR14,ODR14" "0,1" bitfld.long 0x0 13. "ODR13,ODR13" "0,1" bitfld.long 0x0 12. "ODR12,ODR12" "0,1" bitfld.long 0x0 11. "ODR11,ODR11" "0,1" bitfld.long 0x0 10. "ODR10,ODR10" "0,1" bitfld.long 0x0 9. "ODR9,ODR9" "0,1" newline bitfld.long 0x0 8. "ODR8,ODR8" "0,1" bitfld.long 0x0 7. "ODR7,ODR7" "0,1" bitfld.long 0x0 6. "ODR6,ODR6" "0,1" bitfld.long 0x0 5. "ODR5,ODR5" "0,1" bitfld.long 0x0 4. "ODR4,ODR4" "0,1" bitfld.long 0x0 3. "ODR3,ODR3" "0,1" bitfld.long 0x0 2. "ODR2,ODR2" "0,1" newline bitfld.long 0x0 1. "ODR1,ODR1" "0,1" bitfld.long 0x0 0. "ODR0,ODR0" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "GPIOJ_BSRR,GPIO port bit set/reset register" bitfld.long 0x0 31. "BR15,BR15" "0,1" bitfld.long 0x0 30. "BR14,BR14" "0,1" bitfld.long 0x0 29. "BR13,BR13" "0,1" bitfld.long 0x0 28. "BR12,BR12" "0,1" bitfld.long 0x0 27. "BR11,BR11" "0,1" bitfld.long 0x0 26. "BR10,BR10" "0,1" bitfld.long 0x0 25. "BR9,BR9" "0,1" newline bitfld.long 0x0 24. "BR8,BR8" "0,1" bitfld.long 0x0 23. "BR7,BR7" "0,1" bitfld.long 0x0 22. "BR6,BR6" "0,1" bitfld.long 0x0 21. "BR5,BR5" "0,1" bitfld.long 0x0 20. "BR4,BR4" "0,1" bitfld.long 0x0 19. "BR3,BR3" "0,1" bitfld.long 0x0 18. "BR2,BR2" "0,1" newline bitfld.long 0x0 17. "BR1,BR1" "0,1" bitfld.long 0x0 16. "BR0,BR0" "0,1" bitfld.long 0x0 15. "BS15,BS15" "0,1" bitfld.long 0x0 14. "BS14,BS14" "0,1" bitfld.long 0x0 13. "BS13,BS13" "0,1" bitfld.long 0x0 12. "BS12,BS12" "0,1" bitfld.long 0x0 11. "BS11,BS11" "0,1" newline bitfld.long 0x0 10. "BS10,BS10" "0,1" bitfld.long 0x0 9. "BS9,BS9" "0,1" bitfld.long 0x0 8. "BS8,BS8" "0,1" bitfld.long 0x0 7. "BS7,BS7" "0,1" bitfld.long 0x0 6. "BS6,BS6" "0,1" bitfld.long 0x0 5. "BS5,BS5" "0,1" bitfld.long 0x0 4. "BS4,BS4" "0,1" newline bitfld.long 0x0 3. "BS3,BS3" "0,1" bitfld.long 0x0 2. "BS2,BS2" "0,1" bitfld.long 0x0 1. "BS1,BS1" "0,1" bitfld.long 0x0 0. "BS0,BS0" "0,1" group.long 0x1C++0xB line.long 0x0 "GPIOJ_LCKR,This register is used to lock the configuration of the port bits when a correct write sequence is applied to bit 16 (LCKK). The value of bits [15:0] is used to lock the configuration of the GPIO. During the write sequence. the value of.." bitfld.long 0x0 16. "LCKK,LCKK" "0,1" bitfld.long 0x0 15. "LCK15,LCK15" "0,1" bitfld.long 0x0 14. "LCK14,LCK14" "0,1" bitfld.long 0x0 13. "LCK13,LCK13" "0,1" bitfld.long 0x0 12. "LCK12,LCK12" "0,1" bitfld.long 0x0 11. "LCK11,LCK11" "0,1" bitfld.long 0x0 10. "LCK10,LCK10" "0,1" newline bitfld.long 0x0 9. "LCK9,LCK9" "0,1" bitfld.long 0x0 8. "LCK8,LCK8" "0,1" bitfld.long 0x0 7. "LCK7,LCK7" "0,1" bitfld.long 0x0 6. "LCK6,LCK6" "0,1" bitfld.long 0x0 5. "LCK5,LCK5" "0,1" bitfld.long 0x0 4. "LCK4,LCK4" "0,1" bitfld.long 0x0 3. "LCK3,LCK3" "0,1" newline bitfld.long 0x0 2. "LCK2,LCK2" "0,1" bitfld.long 0x0 1. "LCK1,LCK1" "0,1" bitfld.long 0x0 0. "LCK0,LCK0" "0,1" line.long 0x4 "GPIOJ_AFRL,GPIO alternate function low register" hexmask.long.byte 0x4 28.--31. 1. "AFR7,AFR7" hexmask.long.byte 0x4 24.--27. 1. "AFR6,AFR6" hexmask.long.byte 0x4 20.--23. 1. "AFR5,AFR5" hexmask.long.byte 0x4 16.--19. 1. "AFR4,AFR4" hexmask.long.byte 0x4 12.--15. 1. "AFR3,AFR3" hexmask.long.byte 0x4 8.--11. 1. "AFR2,AFR2" hexmask.long.byte 0x4 4.--7. 1. "AFR1,AFR1" newline hexmask.long.byte 0x4 0.--3. 1. "AFR0,AFR0" line.long 0x8 "GPIOJ_AFRH,GPIO alternate function high register" hexmask.long.byte 0x8 28.--31. 1. "AFR15,AFR15" hexmask.long.byte 0x8 24.--27. 1. "AFR14,AFR14" hexmask.long.byte 0x8 20.--23. 1. "AFR13,AFR13" hexmask.long.byte 0x8 16.--19. 1. "AFR12,AFR12" hexmask.long.byte 0x8 12.--15. 1. "AFR11,AFR11" hexmask.long.byte 0x8 8.--11. 1. "AFR10,AFR10" hexmask.long.byte 0x8 4.--7. 1. "AFR9,AFR9" newline hexmask.long.byte 0x8 0.--3. 1. "AFR8,AFR8" wgroup.long 0x28++0x3 line.long 0x0 "GPIOJ_BRR,GPIO port bit reset register" bitfld.long 0x0 15. "BR15,BR15" "0,1" bitfld.long 0x0 14. "BR14,BR14" "0,1" bitfld.long 0x0 13. "BR13,BR13" "0,1" bitfld.long 0x0 12. "BR12,BR12" "0,1" bitfld.long 0x0 11. "BR11,BR11" "0,1" bitfld.long 0x0 10. "BR10,BR10" "0,1" bitfld.long 0x0 9. "BR9,BR9" "0,1" newline bitfld.long 0x0 8. "BR8,BR8" "0,1" bitfld.long 0x0 7. "BR7,BR7" "0,1" bitfld.long 0x0 6. "BR6,BR6" "0,1" bitfld.long 0x0 5. "BR5,BR5" "0,1" bitfld.long 0x0 4. "BR4,BR4" "0,1" bitfld.long 0x0 3. "BR3,BR3" "0,1" bitfld.long 0x0 2. "BR2,BR2" "0,1" newline bitfld.long 0x0 1. "BR1,BR1" "0,1" bitfld.long 0x0 0. "BR0,BR0" "0,1" rgroup.long 0x3C8++0x37 line.long 0x0 "GPIOJ_HWCFGR10,For GPIOA. B. C. D. E. F. G. H. I. J and GPIOK: For GPIOZ:" hexmask.long.byte 0x0 20.--23. 1. "OR_CFG,OR_CFG" hexmask.long.byte 0x0 16.--19. 1. "SEC_CFG,SEC_CFG" hexmask.long.byte 0x0 12.--15. 1. "LOCK_CFG,LOCK_CFG" hexmask.long.byte 0x0 8.--11. 1. "SPEED_CFG,SPEED_CFG" hexmask.long.byte 0x0 4.--7. 1. "AF_SIZE,AF_SIZE" hexmask.long.byte 0x0 0.--3. 1. "AHB_IOP,AHB_IOP" line.long 0x4 "GPIOJ_HWCFGR9,For GPIOA. B. C. D. E. F. G. H. I. and GPIOJ: For GPIOK and GPIOZ:" hexmask.long.word 0x4 0.--15. 1. "EN_IO,EN_IO" line.long 0x8 "GPIOJ_HWCFGR8,For GPIOA. B. C. D. E. F. G. H. I. and GPIOJ: For GPIOK and GPIOZ:" hexmask.long.byte 0x8 28.--31. 1. "AF_PRIO15,AF_PRIO15" hexmask.long.byte 0x8 24.--27. 1. "AF_PRIO14,AF_PRIO14" hexmask.long.byte 0x8 20.--23. 1. "AF_PRIO13,AF_PRIO13" hexmask.long.byte 0x8 16.--19. 1. "AF_PRIO12,AF_PRIO12" hexmask.long.byte 0x8 12.--15. 1. "AF_PRIO11,AF_PRIO11" hexmask.long.byte 0x8 8.--11. 1. "AF_PRIO10,AF_PRIO10" hexmask.long.byte 0x8 4.--7. 1. "AF_PRIO9,AF_PRIO9" newline hexmask.long.byte 0x8 0.--3. 1. "AF_PRIO8,AF_PRIO8" line.long 0xC "GPIOJ_HWCFGR7,GPIO hardware configuration register 7" hexmask.long.byte 0xC 28.--31. 1. "AF_PRIO7,AF_PRIO7" hexmask.long.byte 0xC 24.--27. 1. "AF_PRIO6,AF_PRIO6" hexmask.long.byte 0xC 20.--23. 1. "AF_PRIO5,AF_PRIO5" hexmask.long.byte 0xC 16.--19. 1. "AF_PRIO4,AF_PRIO4" hexmask.long.byte 0xC 12.--15. 1. "AF_PRIO3,AF_PRIO3" hexmask.long.byte 0xC 8.--11. 1. "AF_PRIO2,AF_PRIO2" hexmask.long.byte 0xC 4.--7. 1. "AF_PRIO1,AF_PRIO1" newline hexmask.long.byte 0xC 0.--3. 1. "AF_PRIO0,AF_PRIO0" line.long 0x10 "GPIOJ_HWCFGR6,GPIO hardware configuration register 6" hexmask.long 0x10 0.--31. 1. "MODER_RES,MODER_RES" line.long 0x14 "GPIOJ_HWCFGR5,GPIO hardware configuration register 5" hexmask.long 0x14 0.--31. 1. "PUPDR_RES,PUPDR_RES" line.long 0x18 "GPIOJ_HWCFGR4,GPIO hardware configuration register 4" hexmask.long 0x18 0.--31. 1. "OSPEED_RES,OSPEED_RES" line.long 0x1C "GPIOJ_HWCFGR3,GPIO hardware configuration register 3" hexmask.long.word 0x1C 16.--31. 1. "OTYPER_RES,OTYPER_RES" hexmask.long.word 0x1C 0.--15. 1. "ODR_RES,ODR_RES" line.long 0x20 "GPIOJ_HWCFGR2,GPIO hardware configuration register 2" hexmask.long 0x20 0.--31. 1. "AFRL_RES,AFRL_RES" line.long 0x24 "GPIOJ_HWCFGR1,GPIO hardware configuration register 1" hexmask.long 0x24 0.--31. 1. "AFRH_RES,AFRH_RES" line.long 0x28 "GPIOJ_HWCFGR0,GPIO hardware configuration register 0" hexmask.long.word 0x28 0.--15. 1. "OR_RES,OR_RES" line.long 0x2C "GPIOJ_VERR,GPIO version register" hexmask.long.byte 0x2C 4.--7. 1. "MAJREV,MAJREV" hexmask.long.byte 0x2C 0.--3. 1. "MINREV,MINREV" line.long 0x30 "GPIOJ_IPIDR,GPIO identification register" hexmask.long 0x30 0.--31. 1. "IPIDR,IPIDR" line.long 0x34 "GPIOJ_SIDR,GPIO size identification register" hexmask.long 0x34 0.--31. 1. "SIDR,SIDR" tree.end endif sif (cpuis("STM32MP151*")||cpuis("STM32MP153*")||cpuis("STM32MP157*")) tree "GPIOK" base ad:0x5000C000 group.long 0x0++0xF line.long 0x0 "GPIOK_MODER,GPIO port mode register" bitfld.long 0x0 30.--31. "MODER15,MODER15" "0,1,2,3" bitfld.long 0x0 28.--29. "MODER14,MODER14" "0,1,2,3" bitfld.long 0x0 26.--27. "MODER13,MODER13" "0,1,2,3" bitfld.long 0x0 24.--25. "MODER12,MODER12" "0,1,2,3" bitfld.long 0x0 22.--23. "MODER11,MODER11" "0,1,2,3" bitfld.long 0x0 20.--21. "MODER10,MODER10" "0,1,2,3" bitfld.long 0x0 18.--19. "MODER9,MODER9" "0,1,2,3" newline bitfld.long 0x0 16.--17. "MODER8,MODER8" "0,1,2,3" bitfld.long 0x0 14.--15. "MODER7,MODER7" "0,1,2,3" bitfld.long 0x0 12.--13. "MODER6,MODER6" "0,1,2,3" bitfld.long 0x0 10.--11. "MODER5,MODER5" "0,1,2,3" bitfld.long 0x0 8.--9. "MODER4,MODER4" "0,1,2,3" bitfld.long 0x0 6.--7. "MODER3,MODER3" "0,1,2,3" bitfld.long 0x0 4.--5. "MODER2,MODER2" "0,1,2,3" newline bitfld.long 0x0 2.--3. "MODER1,MODER1" "0,1,2,3" bitfld.long 0x0 0.--1. "MODER0,MODER0" "0,1,2,3" line.long 0x4 "GPIOK_OTYPER,GPIO port output type register" bitfld.long 0x4 15. "OT15,OT15" "0,1" bitfld.long 0x4 14. "OT14,OT14" "0,1" bitfld.long 0x4 13. "OT13,OT13" "0,1" bitfld.long 0x4 12. "OT12,OT12" "0,1" bitfld.long 0x4 11. "OT11,OT11" "0,1" bitfld.long 0x4 10. "OT10,OT10" "0,1" bitfld.long 0x4 9. "OT9,OT9" "0,1" newline bitfld.long 0x4 8. "OT8,OT8" "0,1" bitfld.long 0x4 7. "OT7,OT7" "0,1" bitfld.long 0x4 6. "OT6,OT6" "0,1" bitfld.long 0x4 5. "OT5,OT5" "0,1" bitfld.long 0x4 4. "OT4,OT4" "0,1" bitfld.long 0x4 3. "OT3,OT3" "0,1" bitfld.long 0x4 2. "OT2,OT2" "0,1" newline bitfld.long 0x4 1. "OT1,OT1" "0,1" bitfld.long 0x4 0. "OT0,OT0" "0,1" line.long 0x8 "GPIOK_OSPEEDR,GPIO port output speed register" bitfld.long 0x8 30.--31. "OSPEEDR15,OSPEEDR15" "0,1,2,3" bitfld.long 0x8 28.--29. "OSPEEDR14,OSPEEDR14" "0,1,2,3" bitfld.long 0x8 26.--27. "OSPEEDR13,OSPEEDR13" "0,1,2,3" bitfld.long 0x8 24.--25. "OSPEEDR12,OSPEEDR12" "0,1,2,3" bitfld.long 0x8 22.--23. "OSPEEDR11,OSPEEDR11" "0,1,2,3" bitfld.long 0x8 20.--21. "OSPEEDR10,OSPEEDR10" "0,1,2,3" bitfld.long 0x8 18.--19. "OSPEEDR9,OSPEEDR9" "0,1,2,3" newline bitfld.long 0x8 16.--17. "OSPEEDR8,OSPEEDR8" "0,1,2,3" bitfld.long 0x8 14.--15. "OSPEEDR7,OSPEEDR7" "0,1,2,3" bitfld.long 0x8 12.--13. "OSPEEDR6,OSPEEDR6" "0,1,2,3" bitfld.long 0x8 10.--11. "OSPEEDR5,OSPEEDR5" "0,1,2,3" bitfld.long 0x8 8.--9. "OSPEEDR4,OSPEEDR4" "0,1,2,3" bitfld.long 0x8 6.--7. "OSPEEDR3,OSPEEDR3" "0,1,2,3" bitfld.long 0x8 4.--5. "OSPEEDR2,OSPEEDR2" "0,1,2,3" newline bitfld.long 0x8 2.--3. "OSPEEDR1,OSPEEDR1" "0,1,2,3" bitfld.long 0x8 0.--1. "OSPEEDR0,OSPEEDR0" "0,1,2,3" line.long 0xC "GPIOK_PUPDR,GPIO port pull-up/pull-down register" bitfld.long 0xC 30.--31. "PUPDR15,PUPDR15" "0,1,2,3" bitfld.long 0xC 28.--29. "PUPDR14,PUPDR14" "0,1,2,3" bitfld.long 0xC 26.--27. "PUPDR13,PUPDR13" "0,1,2,3" bitfld.long 0xC 24.--25. "PUPDR12,PUPDR12" "0,1,2,3" bitfld.long 0xC 22.--23. "PUPDR11,PUPDR11" "0,1,2,3" bitfld.long 0xC 20.--21. "PUPDR10,PUPDR10" "0,1,2,3" bitfld.long 0xC 18.--19. "PUPDR9,PUPDR9" "0,1,2,3" newline bitfld.long 0xC 16.--17. "PUPDR8,PUPDR8" "0,1,2,3" bitfld.long 0xC 14.--15. "PUPDR7,PUPDR7" "0,1,2,3" bitfld.long 0xC 12.--13. "PUPDR6,PUPDR6" "0,1,2,3" bitfld.long 0xC 10.--11. "PUPDR5,PUPDR5" "0,1,2,3" bitfld.long 0xC 8.--9. "PUPDR4,PUPDR4" "0,1,2,3" bitfld.long 0xC 6.--7. "PUPDR3,PUPDR3" "0,1,2,3" bitfld.long 0xC 4.--5. "PUPDR2,PUPDR2" "0,1,2,3" newline bitfld.long 0xC 2.--3. "PUPDR1,PUPDR1" "0,1,2,3" bitfld.long 0xC 0.--1. "PUPDR0,PUPDR0" "0,1,2,3" rgroup.long 0x10++0x3 line.long 0x0 "GPIOK_IDR,GPIO port input data register" bitfld.long 0x0 15. "IDR15,IDR15" "0,1" bitfld.long 0x0 14. "IDR14,IDR14" "0,1" bitfld.long 0x0 13. "IDR13,IDR13" "0,1" bitfld.long 0x0 12. "IDR12,IDR12" "0,1" bitfld.long 0x0 11. "IDR11,IDR11" "0,1" bitfld.long 0x0 10. "IDR10,IDR10" "0,1" bitfld.long 0x0 9. "IDR9,IDR9" "0,1" newline bitfld.long 0x0 8. "IDR8,IDR8" "0,1" bitfld.long 0x0 7. "IDR7,IDR7" "0,1" bitfld.long 0x0 6. "IDR6,IDR6" "0,1" bitfld.long 0x0 5. "IDR5,IDR5" "0,1" bitfld.long 0x0 4. "IDR4,IDR4" "0,1" bitfld.long 0x0 3. "IDR3,IDR3" "0,1" bitfld.long 0x0 2. "IDR2,IDR2" "0,1" newline bitfld.long 0x0 1. "IDR1,IDR1" "0,1" bitfld.long 0x0 0. "IDR0,IDR0" "0,1" group.long 0x14++0x3 line.long 0x0 "GPIOK_ODR,GPIO port output data register" bitfld.long 0x0 15. "ODR15,ODR15" "0,1" bitfld.long 0x0 14. "ODR14,ODR14" "0,1" bitfld.long 0x0 13. "ODR13,ODR13" "0,1" bitfld.long 0x0 12. "ODR12,ODR12" "0,1" bitfld.long 0x0 11. "ODR11,ODR11" "0,1" bitfld.long 0x0 10. "ODR10,ODR10" "0,1" bitfld.long 0x0 9. "ODR9,ODR9" "0,1" newline bitfld.long 0x0 8. "ODR8,ODR8" "0,1" bitfld.long 0x0 7. "ODR7,ODR7" "0,1" bitfld.long 0x0 6. "ODR6,ODR6" "0,1" bitfld.long 0x0 5. "ODR5,ODR5" "0,1" bitfld.long 0x0 4. "ODR4,ODR4" "0,1" bitfld.long 0x0 3. "ODR3,ODR3" "0,1" bitfld.long 0x0 2. "ODR2,ODR2" "0,1" newline bitfld.long 0x0 1. "ODR1,ODR1" "0,1" bitfld.long 0x0 0. "ODR0,ODR0" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "GPIOK_BSRR,GPIO port bit set/reset register" bitfld.long 0x0 31. "BR15,BR15" "0,1" bitfld.long 0x0 30. "BR14,BR14" "0,1" bitfld.long 0x0 29. "BR13,BR13" "0,1" bitfld.long 0x0 28. "BR12,BR12" "0,1" bitfld.long 0x0 27. "BR11,BR11" "0,1" bitfld.long 0x0 26. "BR10,BR10" "0,1" bitfld.long 0x0 25. "BR9,BR9" "0,1" newline bitfld.long 0x0 24. "BR8,BR8" "0,1" bitfld.long 0x0 23. "BR7,BR7" "0,1" bitfld.long 0x0 22. "BR6,BR6" "0,1" bitfld.long 0x0 21. "BR5,BR5" "0,1" bitfld.long 0x0 20. "BR4,BR4" "0,1" bitfld.long 0x0 19. "BR3,BR3" "0,1" bitfld.long 0x0 18. "BR2,BR2" "0,1" newline bitfld.long 0x0 17. "BR1,BR1" "0,1" bitfld.long 0x0 16. "BR0,BR0" "0,1" bitfld.long 0x0 15. "BS15,BS15" "0,1" bitfld.long 0x0 14. "BS14,BS14" "0,1" bitfld.long 0x0 13. "BS13,BS13" "0,1" bitfld.long 0x0 12. "BS12,BS12" "0,1" bitfld.long 0x0 11. "BS11,BS11" "0,1" newline bitfld.long 0x0 10. "BS10,BS10" "0,1" bitfld.long 0x0 9. "BS9,BS9" "0,1" bitfld.long 0x0 8. "BS8,BS8" "0,1" bitfld.long 0x0 7. "BS7,BS7" "0,1" bitfld.long 0x0 6. "BS6,BS6" "0,1" bitfld.long 0x0 5. "BS5,BS5" "0,1" bitfld.long 0x0 4. "BS4,BS4" "0,1" newline bitfld.long 0x0 3. "BS3,BS3" "0,1" bitfld.long 0x0 2. "BS2,BS2" "0,1" bitfld.long 0x0 1. "BS1,BS1" "0,1" bitfld.long 0x0 0. "BS0,BS0" "0,1" group.long 0x1C++0xB line.long 0x0 "GPIOK_LCKR,This register is used to lock the configuration of the port bits when a correct write sequence is applied to bit 16 (LCKK). The value of bits [15:0] is used to lock the configuration of the GPIO. During the write sequence. the value of.." bitfld.long 0x0 16. "LCKK,LCKK" "0,1" bitfld.long 0x0 15. "LCK15,LCK15" "0,1" bitfld.long 0x0 14. "LCK14,LCK14" "0,1" bitfld.long 0x0 13. "LCK13,LCK13" "0,1" bitfld.long 0x0 12. "LCK12,LCK12" "0,1" bitfld.long 0x0 11. "LCK11,LCK11" "0,1" bitfld.long 0x0 10. "LCK10,LCK10" "0,1" newline bitfld.long 0x0 9. "LCK9,LCK9" "0,1" bitfld.long 0x0 8. "LCK8,LCK8" "0,1" bitfld.long 0x0 7. "LCK7,LCK7" "0,1" bitfld.long 0x0 6. "LCK6,LCK6" "0,1" bitfld.long 0x0 5. "LCK5,LCK5" "0,1" bitfld.long 0x0 4. "LCK4,LCK4" "0,1" bitfld.long 0x0 3. "LCK3,LCK3" "0,1" newline bitfld.long 0x0 2. "LCK2,LCK2" "0,1" bitfld.long 0x0 1. "LCK1,LCK1" "0,1" bitfld.long 0x0 0. "LCK0,LCK0" "0,1" line.long 0x4 "GPIOK_AFRL,GPIO alternate function low register" hexmask.long.byte 0x4 28.--31. 1. "AFR7,AFR7" hexmask.long.byte 0x4 24.--27. 1. "AFR6,AFR6" hexmask.long.byte 0x4 20.--23. 1. "AFR5,AFR5" hexmask.long.byte 0x4 16.--19. 1. "AFR4,AFR4" hexmask.long.byte 0x4 12.--15. 1. "AFR3,AFR3" hexmask.long.byte 0x4 8.--11. 1. "AFR2,AFR2" hexmask.long.byte 0x4 4.--7. 1. "AFR1,AFR1" newline hexmask.long.byte 0x4 0.--3. 1. "AFR0,AFR0" line.long 0x8 "GPIOK_AFRH,GPIO alternate function high register" hexmask.long.byte 0x8 28.--31. 1. "AFR15,AFR15" hexmask.long.byte 0x8 24.--27. 1. "AFR14,AFR14" hexmask.long.byte 0x8 20.--23. 1. "AFR13,AFR13" hexmask.long.byte 0x8 16.--19. 1. "AFR12,AFR12" hexmask.long.byte 0x8 12.--15. 1. "AFR11,AFR11" hexmask.long.byte 0x8 8.--11. 1. "AFR10,AFR10" hexmask.long.byte 0x8 4.--7. 1. "AFR9,AFR9" newline hexmask.long.byte 0x8 0.--3. 1. "AFR8,AFR8" wgroup.long 0x28++0x3 line.long 0x0 "GPIOK_BRR,GPIO port bit reset register" bitfld.long 0x0 15. "BR15,BR15" "0,1" bitfld.long 0x0 14. "BR14,BR14" "0,1" bitfld.long 0x0 13. "BR13,BR13" "0,1" bitfld.long 0x0 12. "BR12,BR12" "0,1" bitfld.long 0x0 11. "BR11,BR11" "0,1" bitfld.long 0x0 10. "BR10,BR10" "0,1" bitfld.long 0x0 9. "BR9,BR9" "0,1" newline bitfld.long 0x0 8. "BR8,BR8" "0,1" bitfld.long 0x0 7. "BR7,BR7" "0,1" bitfld.long 0x0 6. "BR6,BR6" "0,1" bitfld.long 0x0 5. "BR5,BR5" "0,1" bitfld.long 0x0 4. "BR4,BR4" "0,1" bitfld.long 0x0 3. "BR3,BR3" "0,1" bitfld.long 0x0 2. "BR2,BR2" "0,1" newline bitfld.long 0x0 1. "BR1,BR1" "0,1" bitfld.long 0x0 0. "BR0,BR0" "0,1" rgroup.long 0x3C8++0x37 line.long 0x0 "GPIOK_HWCFGR10,For GPIOA. B. C. D. E. F. G. H. I. J and GPIOK: For GPIOZ:" hexmask.long.byte 0x0 20.--23. 1. "OR_CFG,OR_CFG" hexmask.long.byte 0x0 16.--19. 1. "SEC_CFG,SEC_CFG" hexmask.long.byte 0x0 12.--15. 1. "LOCK_CFG,LOCK_CFG" hexmask.long.byte 0x0 8.--11. 1. "SPEED_CFG,SPEED_CFG" hexmask.long.byte 0x0 4.--7. 1. "AF_SIZE,AF_SIZE" hexmask.long.byte 0x0 0.--3. 1. "AHB_IOP,AHB_IOP" line.long 0x4 "GPIOK_HWCFGR9,For GPIOA. B. C. D. E. F. G. H. I. and GPIOJ: For GPIOK and GPIOZ:" hexmask.long.word 0x4 0.--15. 1. "EN_IO,EN_IO" line.long 0x8 "GPIOK_HWCFGR8,For GPIOA. B. C. D. E. F. G. H. I. and GPIOJ: For GPIOK and GPIOZ:" hexmask.long.byte 0x8 28.--31. 1. "AF_PRIO15,AF_PRIO15" hexmask.long.byte 0x8 24.--27. 1. "AF_PRIO14,AF_PRIO14" hexmask.long.byte 0x8 20.--23. 1. "AF_PRIO13,AF_PRIO13" hexmask.long.byte 0x8 16.--19. 1. "AF_PRIO12,AF_PRIO12" hexmask.long.byte 0x8 12.--15. 1. "AF_PRIO11,AF_PRIO11" hexmask.long.byte 0x8 8.--11. 1. "AF_PRIO10,AF_PRIO10" hexmask.long.byte 0x8 4.--7. 1. "AF_PRIO9,AF_PRIO9" newline hexmask.long.byte 0x8 0.--3. 1. "AF_PRIO8,AF_PRIO8" line.long 0xC "GPIOK_HWCFGR7,GPIO hardware configuration register 7" hexmask.long.byte 0xC 28.--31. 1. "AF_PRIO7,AF_PRIO7" hexmask.long.byte 0xC 24.--27. 1. "AF_PRIO6,AF_PRIO6" hexmask.long.byte 0xC 20.--23. 1. "AF_PRIO5,AF_PRIO5" hexmask.long.byte 0xC 16.--19. 1. "AF_PRIO4,AF_PRIO4" hexmask.long.byte 0xC 12.--15. 1. "AF_PRIO3,AF_PRIO3" hexmask.long.byte 0xC 8.--11. 1. "AF_PRIO2,AF_PRIO2" hexmask.long.byte 0xC 4.--7. 1. "AF_PRIO1,AF_PRIO1" newline hexmask.long.byte 0xC 0.--3. 1. "AF_PRIO0,AF_PRIO0" line.long 0x10 "GPIOK_HWCFGR6,GPIO hardware configuration register 6" hexmask.long 0x10 0.--31. 1. "MODER_RES,MODER_RES" line.long 0x14 "GPIOK_HWCFGR5,GPIO hardware configuration register 5" hexmask.long 0x14 0.--31. 1. "PUPDR_RES,PUPDR_RES" line.long 0x18 "GPIOK_HWCFGR4,GPIO hardware configuration register 4" hexmask.long 0x18 0.--31. 1. "OSPEED_RES,OSPEED_RES" line.long 0x1C "GPIOK_HWCFGR3,GPIO hardware configuration register 3" hexmask.long.word 0x1C 16.--31. 1. "OTYPER_RES,OTYPER_RES" hexmask.long.word 0x1C 0.--15. 1. "ODR_RES,ODR_RES" line.long 0x20 "GPIOK_HWCFGR2,GPIO hardware configuration register 2" hexmask.long 0x20 0.--31. 1. "AFRL_RES,AFRL_RES" line.long 0x24 "GPIOK_HWCFGR1,GPIO hardware configuration register 1" hexmask.long 0x24 0.--31. 1. "AFRH_RES,AFRH_RES" line.long 0x28 "GPIOK_HWCFGR0,GPIO hardware configuration register 0" hexmask.long.word 0x28 0.--15. 1. "OR_RES,OR_RES" line.long 0x2C "GPIOK_VERR,GPIO version register" hexmask.long.byte 0x2C 4.--7. 1. "MAJREV,MAJREV" hexmask.long.byte 0x2C 0.--3. 1. "MINREV,MINREV" line.long 0x30 "GPIOK_IPIDR,GPIO identification register" hexmask.long 0x30 0.--31. 1. "IPIDR,IPIDR" line.long 0x34 "GPIOK_SIDR,GPIO size identification register" hexmask.long 0x34 0.--31. 1. "SIDR,SIDR" tree.end endif sif (cpuis("STM32MP151*")||cpuis("STM32MP153*")||cpuis("STM32MP157*")) tree "GPIOZ" base ad:0x54004000 group.long 0x0++0xF line.long 0x0 "GPIOZ_MODER,GPIO port mode register" bitfld.long 0x0 30.--31. "MODER15,MODER15" "0,1,2,3" bitfld.long 0x0 28.--29. "MODER14,MODER14" "0,1,2,3" bitfld.long 0x0 26.--27. "MODER13,MODER13" "0,1,2,3" bitfld.long 0x0 24.--25. "MODER12,MODER12" "0,1,2,3" bitfld.long 0x0 22.--23. "MODER11,MODER11" "0,1,2,3" bitfld.long 0x0 20.--21. "MODER10,MODER10" "0,1,2,3" bitfld.long 0x0 18.--19. "MODER9,MODER9" "0,1,2,3" newline bitfld.long 0x0 16.--17. "MODER8,MODER8" "0,1,2,3" bitfld.long 0x0 14.--15. "MODER7,MODER7" "0,1,2,3" bitfld.long 0x0 12.--13. "MODER6,MODER6" "0,1,2,3" bitfld.long 0x0 10.--11. "MODER5,MODER5" "0,1,2,3" bitfld.long 0x0 8.--9. "MODER4,MODER4" "0,1,2,3" bitfld.long 0x0 6.--7. "MODER3,MODER3" "0,1,2,3" bitfld.long 0x0 4.--5. "MODER2,MODER2" "0,1,2,3" newline bitfld.long 0x0 2.--3. "MODER1,MODER1" "0,1,2,3" bitfld.long 0x0 0.--1. "MODER0,MODER0" "0,1,2,3" line.long 0x4 "GPIOZ_OTYPER,GPIO port output type register" bitfld.long 0x4 15. "OT15,OT15" "0,1" bitfld.long 0x4 14. "OT14,OT14" "0,1" bitfld.long 0x4 13. "OT13,OT13" "0,1" bitfld.long 0x4 12. "OT12,OT12" "0,1" bitfld.long 0x4 11. "OT11,OT11" "0,1" bitfld.long 0x4 10. "OT10,OT10" "0,1" bitfld.long 0x4 9. "OT9,OT9" "0,1" newline bitfld.long 0x4 8. "OT8,OT8" "0,1" bitfld.long 0x4 7. "OT7,OT7" "0,1" bitfld.long 0x4 6. "OT6,OT6" "0,1" bitfld.long 0x4 5. "OT5,OT5" "0,1" bitfld.long 0x4 4. "OT4,OT4" "0,1" bitfld.long 0x4 3. "OT3,OT3" "0,1" bitfld.long 0x4 2. "OT2,OT2" "0,1" newline bitfld.long 0x4 1. "OT1,OT1" "0,1" bitfld.long 0x4 0. "OT0,OT0" "0,1" line.long 0x8 "GPIOZ_OSPEEDR,GPIO port output speed register" bitfld.long 0x8 30.--31. "OSPEEDR15,OSPEEDR15" "0,1,2,3" bitfld.long 0x8 28.--29. "OSPEEDR14,OSPEEDR14" "0,1,2,3" bitfld.long 0x8 26.--27. "OSPEEDR13,OSPEEDR13" "0,1,2,3" bitfld.long 0x8 24.--25. "OSPEEDR12,OSPEEDR12" "0,1,2,3" bitfld.long 0x8 22.--23. "OSPEEDR11,OSPEEDR11" "0,1,2,3" bitfld.long 0x8 20.--21. "OSPEEDR10,OSPEEDR10" "0,1,2,3" bitfld.long 0x8 18.--19. "OSPEEDR9,OSPEEDR9" "0,1,2,3" newline bitfld.long 0x8 16.--17. "OSPEEDR8,OSPEEDR8" "0,1,2,3" bitfld.long 0x8 14.--15. "OSPEEDR7,OSPEEDR7" "0,1,2,3" bitfld.long 0x8 12.--13. "OSPEEDR6,OSPEEDR6" "0,1,2,3" bitfld.long 0x8 10.--11. "OSPEEDR5,OSPEEDR5" "0,1,2,3" bitfld.long 0x8 8.--9. "OSPEEDR4,OSPEEDR4" "0,1,2,3" bitfld.long 0x8 6.--7. "OSPEEDR3,OSPEEDR3" "0,1,2,3" bitfld.long 0x8 4.--5. "OSPEEDR2,OSPEEDR2" "0,1,2,3" newline bitfld.long 0x8 2.--3. "OSPEEDR1,OSPEEDR1" "0,1,2,3" bitfld.long 0x8 0.--1. "OSPEEDR0,OSPEEDR0" "0,1,2,3" line.long 0xC "GPIOZ_PUPDR,GPIO port pull-up/pull-down register" bitfld.long 0xC 30.--31. "PUPDR15,PUPDR15" "0,1,2,3" bitfld.long 0xC 28.--29. "PUPDR14,PUPDR14" "0,1,2,3" bitfld.long 0xC 26.--27. "PUPDR13,PUPDR13" "0,1,2,3" bitfld.long 0xC 24.--25. "PUPDR12,PUPDR12" "0,1,2,3" bitfld.long 0xC 22.--23. "PUPDR11,PUPDR11" "0,1,2,3" bitfld.long 0xC 20.--21. "PUPDR10,PUPDR10" "0,1,2,3" bitfld.long 0xC 18.--19. "PUPDR9,PUPDR9" "0,1,2,3" newline bitfld.long 0xC 16.--17. "PUPDR8,PUPDR8" "0,1,2,3" bitfld.long 0xC 14.--15. "PUPDR7,PUPDR7" "0,1,2,3" bitfld.long 0xC 12.--13. "PUPDR6,PUPDR6" "0,1,2,3" bitfld.long 0xC 10.--11. "PUPDR5,PUPDR5" "0,1,2,3" bitfld.long 0xC 8.--9. "PUPDR4,PUPDR4" "0,1,2,3" bitfld.long 0xC 6.--7. "PUPDR3,PUPDR3" "0,1,2,3" bitfld.long 0xC 4.--5. "PUPDR2,PUPDR2" "0,1,2,3" newline bitfld.long 0xC 2.--3. "PUPDR1,PUPDR1" "0,1,2,3" bitfld.long 0xC 0.--1. "PUPDR0,PUPDR0" "0,1,2,3" rgroup.long 0x10++0x3 line.long 0x0 "GPIOZ_IDR,GPIO port input data register" bitfld.long 0x0 15. "IDR15,IDR15" "0,1" bitfld.long 0x0 14. "IDR14,IDR14" "0,1" bitfld.long 0x0 13. "IDR13,IDR13" "0,1" bitfld.long 0x0 12. "IDR12,IDR12" "0,1" bitfld.long 0x0 11. "IDR11,IDR11" "0,1" bitfld.long 0x0 10. "IDR10,IDR10" "0,1" bitfld.long 0x0 9. "IDR9,IDR9" "0,1" newline bitfld.long 0x0 8. "IDR8,IDR8" "0,1" bitfld.long 0x0 7. "IDR7,IDR7" "0,1" bitfld.long 0x0 6. "IDR6,IDR6" "0,1" bitfld.long 0x0 5. "IDR5,IDR5" "0,1" bitfld.long 0x0 4. "IDR4,IDR4" "0,1" bitfld.long 0x0 3. "IDR3,IDR3" "0,1" bitfld.long 0x0 2. "IDR2,IDR2" "0,1" newline bitfld.long 0x0 1. "IDR1,IDR1" "0,1" bitfld.long 0x0 0. "IDR0,IDR0" "0,1" group.long 0x14++0x3 line.long 0x0 "GPIOZ_ODR,GPIO port output data register" bitfld.long 0x0 15. "ODR15,ODR15" "0,1" bitfld.long 0x0 14. "ODR14,ODR14" "0,1" bitfld.long 0x0 13. "ODR13,ODR13" "0,1" bitfld.long 0x0 12. "ODR12,ODR12" "0,1" bitfld.long 0x0 11. "ODR11,ODR11" "0,1" bitfld.long 0x0 10. "ODR10,ODR10" "0,1" bitfld.long 0x0 9. "ODR9,ODR9" "0,1" newline bitfld.long 0x0 8. "ODR8,ODR8" "0,1" bitfld.long 0x0 7. "ODR7,ODR7" "0,1" bitfld.long 0x0 6. "ODR6,ODR6" "0,1" bitfld.long 0x0 5. "ODR5,ODR5" "0,1" bitfld.long 0x0 4. "ODR4,ODR4" "0,1" bitfld.long 0x0 3. "ODR3,ODR3" "0,1" bitfld.long 0x0 2. "ODR2,ODR2" "0,1" newline bitfld.long 0x0 1. "ODR1,ODR1" "0,1" bitfld.long 0x0 0. "ODR0,ODR0" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "GPIOZ_BSRR,GPIO port bit set/reset register" bitfld.long 0x0 31. "BR15,BR15" "0,1" bitfld.long 0x0 30. "BR14,BR14" "0,1" bitfld.long 0x0 29. "BR13,BR13" "0,1" bitfld.long 0x0 28. "BR12,BR12" "0,1" bitfld.long 0x0 27. "BR11,BR11" "0,1" bitfld.long 0x0 26. "BR10,BR10" "0,1" bitfld.long 0x0 25. "BR9,BR9" "0,1" newline bitfld.long 0x0 24. "BR8,BR8" "0,1" bitfld.long 0x0 23. "BR7,BR7" "0,1" bitfld.long 0x0 22. "BR6,BR6" "0,1" bitfld.long 0x0 21. "BR5,BR5" "0,1" bitfld.long 0x0 20. "BR4,BR4" "0,1" bitfld.long 0x0 19. "BR3,BR3" "0,1" bitfld.long 0x0 18. "BR2,BR2" "0,1" newline bitfld.long 0x0 17. "BR1,BR1" "0,1" bitfld.long 0x0 16. "BR0,BR0" "0,1" bitfld.long 0x0 15. "BS15,BS15" "0,1" bitfld.long 0x0 14. "BS14,BS14" "0,1" bitfld.long 0x0 13. "BS13,BS13" "0,1" bitfld.long 0x0 12. "BS12,BS12" "0,1" bitfld.long 0x0 11. "BS11,BS11" "0,1" newline bitfld.long 0x0 10. "BS10,BS10" "0,1" bitfld.long 0x0 9. "BS9,BS9" "0,1" bitfld.long 0x0 8. "BS8,BS8" "0,1" bitfld.long 0x0 7. "BS7,BS7" "0,1" bitfld.long 0x0 6. "BS6,BS6" "0,1" bitfld.long 0x0 5. "BS5,BS5" "0,1" bitfld.long 0x0 4. "BS4,BS4" "0,1" newline bitfld.long 0x0 3. "BS3,BS3" "0,1" bitfld.long 0x0 2. "BS2,BS2" "0,1" bitfld.long 0x0 1. "BS1,BS1" "0,1" bitfld.long 0x0 0. "BS0,BS0" "0,1" group.long 0x1C++0xB line.long 0x0 "GPIOZ_LCKR,This register is used to lock the configuration of the port bits when a correct write sequence is applied to bit 16 (LCKK). The value of bits [15:0] is used to lock the configuration of the GPIO. During the write sequence. the value of.." bitfld.long 0x0 16. "LCKK,LCKK" "0,1" bitfld.long 0x0 15. "LCK15,LCK15" "0,1" bitfld.long 0x0 14. "LCK14,LCK14" "0,1" bitfld.long 0x0 13. "LCK13,LCK13" "0,1" bitfld.long 0x0 12. "LCK12,LCK12" "0,1" bitfld.long 0x0 11. "LCK11,LCK11" "0,1" bitfld.long 0x0 10. "LCK10,LCK10" "0,1" newline bitfld.long 0x0 9. "LCK9,LCK9" "0,1" bitfld.long 0x0 8. "LCK8,LCK8" "0,1" bitfld.long 0x0 7. "LCK7,LCK7" "0,1" bitfld.long 0x0 6. "LCK6,LCK6" "0,1" bitfld.long 0x0 5. "LCK5,LCK5" "0,1" bitfld.long 0x0 4. "LCK4,LCK4" "0,1" bitfld.long 0x0 3. "LCK3,LCK3" "0,1" newline bitfld.long 0x0 2. "LCK2,LCK2" "0,1" bitfld.long 0x0 1. "LCK1,LCK1" "0,1" bitfld.long 0x0 0. "LCK0,LCK0" "0,1" line.long 0x4 "GPIOZ_AFRL,GPIO alternate function low register" hexmask.long.byte 0x4 28.--31. 1. "AFR7,AFR7" hexmask.long.byte 0x4 24.--27. 1. "AFR6,AFR6" hexmask.long.byte 0x4 20.--23. 1. "AFR5,AFR5" hexmask.long.byte 0x4 16.--19. 1. "AFR4,AFR4" hexmask.long.byte 0x4 12.--15. 1. "AFR3,AFR3" hexmask.long.byte 0x4 8.--11. 1. "AFR2,AFR2" hexmask.long.byte 0x4 4.--7. 1. "AFR1,AFR1" newline hexmask.long.byte 0x4 0.--3. 1. "AFR0,AFR0" line.long 0x8 "GPIOZ_AFRH,GPIO alternate function high register" hexmask.long.byte 0x8 28.--31. 1. "AFR15,AFR15" hexmask.long.byte 0x8 24.--27. 1. "AFR14,AFR14" hexmask.long.byte 0x8 20.--23. 1. "AFR13,AFR13" hexmask.long.byte 0x8 16.--19. 1. "AFR12,AFR12" hexmask.long.byte 0x8 12.--15. 1. "AFR11,AFR11" hexmask.long.byte 0x8 8.--11. 1. "AFR10,AFR10" hexmask.long.byte 0x8 4.--7. 1. "AFR9,AFR9" newline hexmask.long.byte 0x8 0.--3. 1. "AFR8,AFR8" wgroup.long 0x28++0x3 line.long 0x0 "GPIOZ_BRR,GPIO port bit reset register" bitfld.long 0x0 15. "BR15,BR15" "0,1" bitfld.long 0x0 14. "BR14,BR14" "0,1" bitfld.long 0x0 13. "BR13,BR13" "0,1" bitfld.long 0x0 12. "BR12,BR12" "0,1" bitfld.long 0x0 11. "BR11,BR11" "0,1" bitfld.long 0x0 10. "BR10,BR10" "0,1" bitfld.long 0x0 9. "BR9,BR9" "0,1" newline bitfld.long 0x0 8. "BR8,BR8" "0,1" bitfld.long 0x0 7. "BR7,BR7" "0,1" bitfld.long 0x0 6. "BR6,BR6" "0,1" bitfld.long 0x0 5. "BR5,BR5" "0,1" bitfld.long 0x0 4. "BR4,BR4" "0,1" bitfld.long 0x0 3. "BR3,BR3" "0,1" bitfld.long 0x0 2. "BR2,BR2" "0,1" newline bitfld.long 0x0 1. "BR1,BR1" "0,1" bitfld.long 0x0 0. "BR0,BR0" "0,1" wgroup.long 0x30++0x3 line.long 0x0 "GPIOZ_SECCFGR,This register provides write access security and can be written only by a secure access. It is used to configure a selected I/O as secure. A non-secure write access to this register is discarded." bitfld.long 0x0 7. "SEC7,SEC7" "0,1" bitfld.long 0x0 6. "SEC6,SEC6" "0,1" bitfld.long 0x0 5. "SEC5,SEC5" "0,1" bitfld.long 0x0 4. "SEC4,SEC4" "0,1" bitfld.long 0x0 3. "SEC3,SEC3" "0,1" bitfld.long 0x0 2. "SEC2,SEC2" "0,1" bitfld.long 0x0 1. "SEC1,SEC1" "0,1" newline bitfld.long 0x0 0. "SEC0,SEC0" "0,1" rgroup.long 0x3C8++0x37 line.long 0x0 "GPIOZ_HWCFGR10,For GPIOA. B. C. D. E. F. G. H. I. J and GPIOK: For GPIOZ:" hexmask.long.byte 0x0 20.--23. 1. "OR_CFG,OR_CFG" hexmask.long.byte 0x0 16.--19. 1. "SEC_CFG,SEC_CFG" hexmask.long.byte 0x0 12.--15. 1. "LOCK_CFG,LOCK_CFG" hexmask.long.byte 0x0 8.--11. 1. "SPEED_CFG,SPEED_CFG" hexmask.long.byte 0x0 4.--7. 1. "AF_SIZE,AF_SIZE" hexmask.long.byte 0x0 0.--3. 1. "AHB_IOP,AHB_IOP" line.long 0x4 "GPIOZ_HWCFGR9,For GPIOA. B. C. D. E. F. G. H. I. and GPIOJ: For GPIOK and GPIOZ:" hexmask.long.word 0x4 0.--15. 1. "EN_IO,EN_IO" line.long 0x8 "GPIOZ_HWCFGR8,For GPIOA. B. C. D. E. F. G. H. I. and GPIOJ: For GPIOK and GPIOZ:" hexmask.long.byte 0x8 28.--31. 1. "AF_PRIO15,AF_PRIO15" hexmask.long.byte 0x8 24.--27. 1. "AF_PRIO14,AF_PRIO14" hexmask.long.byte 0x8 20.--23. 1. "AF_PRIO13,AF_PRIO13" hexmask.long.byte 0x8 16.--19. 1. "AF_PRIO12,AF_PRIO12" hexmask.long.byte 0x8 12.--15. 1. "AF_PRIO11,AF_PRIO11" hexmask.long.byte 0x8 8.--11. 1. "AF_PRIO10,AF_PRIO10" hexmask.long.byte 0x8 4.--7. 1. "AF_PRIO9,AF_PRIO9" newline hexmask.long.byte 0x8 0.--3. 1. "AF_PRIO8,AF_PRIO8" line.long 0xC "GPIOZ_HWCFGR7,GPIO hardware configuration register 7" hexmask.long.byte 0xC 28.--31. 1. "AF_PRIO7,AF_PRIO7" hexmask.long.byte 0xC 24.--27. 1. "AF_PRIO6,AF_PRIO6" hexmask.long.byte 0xC 20.--23. 1. "AF_PRIO5,AF_PRIO5" hexmask.long.byte 0xC 16.--19. 1. "AF_PRIO4,AF_PRIO4" hexmask.long.byte 0xC 12.--15. 1. "AF_PRIO3,AF_PRIO3" hexmask.long.byte 0xC 8.--11. 1. "AF_PRIO2,AF_PRIO2" hexmask.long.byte 0xC 4.--7. 1. "AF_PRIO1,AF_PRIO1" newline hexmask.long.byte 0xC 0.--3. 1. "AF_PRIO0,AF_PRIO0" line.long 0x10 "GPIOZ_HWCFGR6,GPIO hardware configuration register 6" hexmask.long 0x10 0.--31. 1. "MODER_RES,MODER_RES" line.long 0x14 "GPIOZ_HWCFGR5,GPIO hardware configuration register 5" hexmask.long 0x14 0.--31. 1. "PUPDR_RES,PUPDR_RES" line.long 0x18 "GPIOZ_HWCFGR4,GPIO hardware configuration register 4" hexmask.long 0x18 0.--31. 1. "OSPEED_RES,OSPEED_RES" line.long 0x1C "GPIOZ_HWCFGR3,GPIO hardware configuration register 3" hexmask.long.word 0x1C 16.--31. 1. "OTYPER_RES,OTYPER_RES" hexmask.long.word 0x1C 0.--15. 1. "ODR_RES,ODR_RES" line.long 0x20 "GPIOZ_HWCFGR2,GPIO hardware configuration register 2" hexmask.long 0x20 0.--31. 1. "AFRL_RES,AFRL_RES" line.long 0x24 "GPIOZ_HWCFGR1,GPIO hardware configuration register 1" hexmask.long 0x24 0.--31. 1. "AFRH_RES,AFRH_RES" line.long 0x28 "GPIOZ_HWCFGR0,GPIO hardware configuration register 0" hexmask.long.word 0x28 0.--15. 1. "OR_RES,OR_RES" line.long 0x2C "GPIOZ_VERR,GPIO version register" hexmask.long.byte 0x2C 4.--7. 1. "MAJREV,MAJREV" hexmask.long.byte 0x2C 0.--3. 1. "MINREV,MINREV" line.long 0x30 "GPIOZ_IPIDR,GPIO identification register" hexmask.long 0x30 0.--31. 1. "IPIDR,IPIDR" line.long 0x34 "GPIOZ_SIDR,GPIO size identification register" hexmask.long 0x34 0.--31. 1. "SIDR,SIDR" tree.end endif tree.end tree "HASH (Hash Processor)" base ad:0x0 sif (cpuis("STM32MP13*")) tree "HASH" base ad:0x54003000 group.long 0x0++0x3 line.long 0x0 "HASH_CR,HASH control register" hexmask.long.byte 0x0 17.--20. 1. "ALGO,Algorithm selection" bitfld.long 0x0 16. "LKEY,Long key selection" "0: HMAC key is shorter or equal to the block size..,1: HMAC key is longer than the block size (long.." newline bitfld.long 0x0 14. "DMAA,DMA Abort" "0,1" bitfld.long 0x0 13. "MDMAT,Multiple DMA transfers" "0: DCAL is automatically set at the end of a DMA..,1: DCAL is not automatically set at the end of a.." newline rbitfld.long 0x0 12. "DINNE,DIN not empty" "0,1" hexmask.long.byte 0x0 8.--11. 1. "NBW,Number of words already pushed" newline bitfld.long 0x0 6. "MODE,Mode selection" "0: Hash mode selected,1: HMAC mode selected. LKEY bit must be set if the.." bitfld.long 0x0 4.--5. "DATATYPE,Data type selection" "0: 32-bit data. The data written into HASH_DIN are..,1: 16-bit data or half-word. The data written into..,2: 8-bit data or bytes. The data written into..,3: bit data or bit string. The data written into.." newline bitfld.long 0x0 3. "DMAE,DMA enable" "0: DMA transfers disabled,1: DMA transfers enabled. A DMA request is sent as.." bitfld.long 0x0 2. "INIT,Initialize message digest calculation" "0,1" wgroup.long 0x4++0x3 line.long 0x0 "HASH_DIN,HASH data input register" hexmask.long 0x0 0.--31. 1. "DATAIN,Data input" group.long 0x8++0x3 line.long 0x0 "HASH_STR,HASH start register" bitfld.long 0x0 8. "DCAL,Digest calculation" "0,1" hexmask.long.byte 0x0 0.--4. 1. "NBLW,Number of valid bits in the last word" rgroup.long 0xC++0x13 line.long 0x0 "HASH_HRA0,HASH aliased digest register 0" hexmask.long 0x0 0.--31. 1. "H,Hash data" line.long 0x4 "HASH_HRA1,HASH aliased digest register 1" hexmask.long 0x4 0.--31. 1. "H,Hash data" line.long 0x8 "HASH_HRA2,HASH aliased digest register 2" hexmask.long 0x8 0.--31. 1. "H,Hash data" line.long 0xC "HASH_HRA3,HASH aliased digest register 3" hexmask.long 0xC 0.--31. 1. "H,Hash data" line.long 0x10 "HASH_HRA4,HASH aliased digest register 4" hexmask.long 0x10 0.--31. 1. "H,Hash data" group.long 0x20++0x7 line.long 0x0 "HASH_IMR," bitfld.long 0x0 1. "DCIE,Digest calculation completion interrupt enable" "0: Digest calculation completion interrupt disabled,1: Digest calculation completion interrupt enabled." bitfld.long 0x0 0. "DINIE,Data input interrupt enable" "0: Data input interrupt disabled,1: Data input interrupt enabled" line.long 0x4 "HASH_SR," hexmask.long.byte 0x4 16.--21. 1. "NBWE,Number of words expected" rbitfld.long 0x4 15. "DINNE,DIN not empty" "0: No data are present in the data input buffer,1: The input buffer contains at least one word of.." newline hexmask.long.byte 0x4 9.--14. 1. "NBWP,Number of words already pushed" rbitfld.long 0x4 3. "BUSY,Busy bit" "0: No block is currently being processed,1: The hash core is processing a block of data" newline rbitfld.long 0x4 2. "DMAS,DMA Status" "0: DMA interface is disabled (DMAE = 0) and no..,1: DMA interface is enabled (DMAE = 1) or a.." bitfld.long 0x4 1. "DCIS,Digest calculation completion interrupt status" "0: No digest available in the HASH_HRx registers..,1: Digest calculation complete a digest is.." newline bitfld.long 0x4 0. "DINIS,Data input interrupt status" "0: Less than 16 locations are free in the input..,1: A new block can be entered into the input.." group.long 0xF8++0x19B line.long 0x0 "HASH_CSR0,HASH context swap register 0" hexmask.long 0x0 0.--31. 1. "CS0,Context swap x (x = 0 to 102)" line.long 0x4 "HASH_CSR1,HASH context swap register 1" hexmask.long 0x4 0.--31. 1. "CS1,Context swap x (x = 0 to 102)" line.long 0x8 "HASH_CSR2,HASH context swap register 2" hexmask.long 0x8 0.--31. 1. "CS2,Context swap x (x = 0 to 102)" line.long 0xC "HASH_CSR3,HASH context swap register 3" hexmask.long 0xC 0.--31. 1. "CS3,Context swap x (x = 0 to 102)" line.long 0x10 "HASH_CSR4,HASH context swap register 4" hexmask.long 0x10 0.--31. 1. "CS4,Context swap x (x = 0 to 102)" line.long 0x14 "HASH_CSR5,HASH context swap register 5" hexmask.long 0x14 0.--31. 1. "CS5,Context swap x (x = 0 to 102)" line.long 0x18 "HASH_CSR6,HASH context swap register 6" hexmask.long 0x18 0.--31. 1. "CS6,Context swap x (x = 0 to 102)" line.long 0x1C "HASH_CSR7,HASH context swap register 7" hexmask.long 0x1C 0.--31. 1. "CS7,Context swap x (x = 0 to 102)" line.long 0x20 "HASH_CSR8,HASH context swap register 8" hexmask.long 0x20 0.--31. 1. "CS8,Context swap x (x = 0 to 102)" line.long 0x24 "HASH_CSR9,HASH context swap register 9" hexmask.long 0x24 0.--31. 1. "CS9,Context swap x (x = 0 to 102)" line.long 0x28 "HASH_CSR10,HASH context swap register 10" hexmask.long 0x28 0.--31. 1. "CS10,Context swap x (x = 0 to 102)" line.long 0x2C "HASH_CSR11,HASH context swap register 11" hexmask.long 0x2C 0.--31. 1. "CS11,Context swap x (x = 0 to 102)" line.long 0x30 "HASH_CSR12,HASH context swap register 12" hexmask.long 0x30 0.--31. 1. "CS12,Context swap x (x = 0 to 102)" line.long 0x34 "HASH_CSR13,HASH context swap register 13" hexmask.long 0x34 0.--31. 1. "CS13,Context swap x (x = 0 to 102)" line.long 0x38 "HASH_CSR14,HASH context swap register 14" hexmask.long 0x38 0.--31. 1. "CS14,Context swap x (x = 0 to 102)" line.long 0x3C "HASH_CSR15,HASH context swap register 15" hexmask.long 0x3C 0.--31. 1. "CS15,Context swap x (x = 0 to 102)" line.long 0x40 "HASH_CSR16,HASH context swap register 16" hexmask.long 0x40 0.--31. 1. "CS16,Context swap x (x = 0 to 102)" line.long 0x44 "HASH_CSR17,HASH context swap register 17" hexmask.long 0x44 0.--31. 1. "CS17,Context swap x (x = 0 to 102)" line.long 0x48 "HASH_CSR18,HASH context swap register 18" hexmask.long 0x48 0.--31. 1. "CS18,Context swap x (x = 0 to 102)" line.long 0x4C "HASH_CSR19,HASH context swap register 19" hexmask.long 0x4C 0.--31. 1. "CS19,Context swap x (x = 0 to 102)" line.long 0x50 "HASH_CSR20,HASH context swap register 20" hexmask.long 0x50 0.--31. 1. "CS20,Context swap x (x = 0 to 102)" line.long 0x54 "HASH_CSR21,HASH context swap register 21" hexmask.long 0x54 0.--31. 1. "CS21,Context swap x (x = 0 to 102)" line.long 0x58 "HASH_CSR22,HASH context swap register 22" hexmask.long 0x58 0.--31. 1. "CS22,Context swap x (x = 0 to 102)" line.long 0x5C "HASH_CSR23,HASH context swap register 23" hexmask.long 0x5C 0.--31. 1. "CS23,Context swap x (x = 0 to 102)" line.long 0x60 "HASH_CSR24,HASH context swap register 24" hexmask.long 0x60 0.--31. 1. "CS24,Context swap x (x = 0 to 102)" line.long 0x64 "HASH_CSR25,HASH context swap register 25" hexmask.long 0x64 0.--31. 1. "CS25,Context swap x (x = 0 to 102)" line.long 0x68 "HASH_CSR26,HASH context swap register 26" hexmask.long 0x68 0.--31. 1. "CS26,Context swap x (x = 0 to 102)" line.long 0x6C "HASH_CSR27,HASH context swap register 27" hexmask.long 0x6C 0.--31. 1. "CS27,Context swap x (x = 0 to 102)" line.long 0x70 "HASH_CSR28,HASH context swap register 28" hexmask.long 0x70 0.--31. 1. "CS28,Context swap x (x = 0 to 102)" line.long 0x74 "HASH_CSR29,HASH context swap register 29" hexmask.long 0x74 0.--31. 1. "CS29,Context swap x (x = 0 to 102)" line.long 0x78 "HASH_CSR30,HASH context swap register 30" hexmask.long 0x78 0.--31. 1. "CS30,Context swap x (x = 0 to 102)" line.long 0x7C "HASH_CSR31,HASH context swap register 31" hexmask.long 0x7C 0.--31. 1. "CS31,Context swap x (x = 0 to 102)" line.long 0x80 "HASH_CSR32,HASH context swap register 32" hexmask.long 0x80 0.--31. 1. "CS32,Context swap x (x = 0 to 102)" line.long 0x84 "HASH_CSR33,HASH context swap register 33" hexmask.long 0x84 0.--31. 1. "CS33,Context swap x (x = 0 to 102)" line.long 0x88 "HASH_CSR34,HASH context swap register 34" hexmask.long 0x88 0.--31. 1. "CS34,Context swap x (x = 0 to 102)" line.long 0x8C "HASH_CSR35,HASH context swap register 35" hexmask.long 0x8C 0.--31. 1. "CS35,Context swap x (x = 0 to 102)" line.long 0x90 "HASH_CSR36,HASH context swap register 36" hexmask.long 0x90 0.--31. 1. "CS36,Context swap x (x = 0 to 102)" line.long 0x94 "HASH_CSR37,HASH context swap register 37" hexmask.long 0x94 0.--31. 1. "CS37,Context swap x (x = 0 to 102)" line.long 0x98 "HASH_CSR38,HASH context swap register 38" hexmask.long 0x98 0.--31. 1. "CS38,Context swap x (x = 0 to 102)" line.long 0x9C "HASH_CSR39,HASH context swap register 39" hexmask.long 0x9C 0.--31. 1. "CS39,Context swap x (x = 0 to 102)" line.long 0xA0 "HASH_CSR40,HASH context swap register 40" hexmask.long 0xA0 0.--31. 1. "CS40,Context swap x (x = 0 to 102)" line.long 0xA4 "HASH_CSR41,HASH context swap register 41" hexmask.long 0xA4 0.--31. 1. "CS41,Context swap x (x = 0 to 102)" line.long 0xA8 "HASH_CSR42,HASH context swap register 42" hexmask.long 0xA8 0.--31. 1. "CS42,Context swap x (x = 0 to 102)" line.long 0xAC "HASH_CSR43,HASH context swap register 43" hexmask.long 0xAC 0.--31. 1. "CS43,Context swap x (x = 0 to 102)" line.long 0xB0 "HASH_CSR44,HASH context swap register 44" hexmask.long 0xB0 0.--31. 1. "CS44,Context swap x (x = 0 to 102)" line.long 0xB4 "HASH_CSR45,HASH context swap register 45" hexmask.long 0xB4 0.--31. 1. "CS45,Context swap x (x = 0 to 102)" line.long 0xB8 "HASH_CSR46,HASH context swap register 46" hexmask.long 0xB8 0.--31. 1. "CS46,Context swap x (x = 0 to 102)" line.long 0xBC "HASH_CSR47,HASH context swap register 47" hexmask.long 0xBC 0.--31. 1. "CS47,Context swap x (x = 0 to 102)" line.long 0xC0 "HASH_CSR48,HASH context swap register 48" hexmask.long 0xC0 0.--31. 1. "CS48,Context swap x (x = 0 to 102)" line.long 0xC4 "HASH_CSR49,HASH context swap register 49" hexmask.long 0xC4 0.--31. 1. "CS49,Context swap x (x = 0 to 102)" line.long 0xC8 "HASH_CSR50,HASH context swap register 50" hexmask.long 0xC8 0.--31. 1. "CS50,Context swap x (x = 0 to 102)" line.long 0xCC "HASH_CSR51,HASH context swap register 51" hexmask.long 0xCC 0.--31. 1. "CS51,Context swap x (x = 0 to 102)" line.long 0xD0 "HASH_CSR52,HASH context swap register 52" hexmask.long 0xD0 0.--31. 1. "CS52,Context swap x (x = 0 to 102)" line.long 0xD4 "HASH_CSR53,HASH context swap register 53" hexmask.long 0xD4 0.--31. 1. "CS53,Context swap x (x = 0 to 102)" line.long 0xD8 "HASH_CSR54,HASH context swap register 54" hexmask.long 0xD8 0.--31. 1. "CS54,Context swap x (x = 0 to 102)" line.long 0xDC "HASH_CSR55,HASH context swap register 55" hexmask.long 0xDC 0.--31. 1. "CS55,Context swap x (x = 0 to 102)" line.long 0xE0 "HASH_CSR56,HASH context swap register 56" hexmask.long 0xE0 0.--31. 1. "CS56,Context swap x (x = 0 to 102)" line.long 0xE4 "HASH_CSR57,HASH context swap register 57" hexmask.long 0xE4 0.--31. 1. "CS57,Context swap x (x = 0 to 102)" line.long 0xE8 "HASH_CSR58,HASH context swap register 58" hexmask.long 0xE8 0.--31. 1. "CS58,Context swap x (x = 0 to 102)" line.long 0xEC "HASH_CSR59,HASH context swap register 59" hexmask.long 0xEC 0.--31. 1. "CS59,Context swap x (x = 0 to 102)" line.long 0xF0 "HASH_CSR60,HASH context swap register 60" hexmask.long 0xF0 0.--31. 1. "CS60,Context swap x (x = 0 to 102)" line.long 0xF4 "HASH_CSR61,HASH context swap register 61" hexmask.long 0xF4 0.--31. 1. "CS61,Context swap x (x = 0 to 102)" line.long 0xF8 "HASH_CSR62,HASH context swap register 62" hexmask.long 0xF8 0.--31. 1. "CS62,Context swap x (x = 0 to 102)" line.long 0xFC "HASH_CSR63,HASH context swap register 63" hexmask.long 0xFC 0.--31. 1. "CS63,Context swap x (x = 0 to 102)" line.long 0x100 "HASH_CSR64,HASH context swap register 64" hexmask.long 0x100 0.--31. 1. "CS64,Context swap x (x = 0 to 102)" line.long 0x104 "HASH_CSR65,HASH context swap register 65" hexmask.long 0x104 0.--31. 1. "CS65,Context swap x (x = 0 to 102)" line.long 0x108 "HASH_CSR66,HASH context swap register 66" hexmask.long 0x108 0.--31. 1. "CS66,Context swap x (x = 0 to 102)" line.long 0x10C "HASH_CSR67,HASH context swap register 67" hexmask.long 0x10C 0.--31. 1. "CS67,Context swap x (x = 0 to 102)" line.long 0x110 "HASH_CSR68,HASH context swap register 68" hexmask.long 0x110 0.--31. 1. "CS68,Context swap x (x = 0 to 102)" line.long 0x114 "HASH_CSR69,HASH context swap register 69" hexmask.long 0x114 0.--31. 1. "CS69,Context swap x (x = 0 to 102)" line.long 0x118 "HASH_CSR70,HASH context swap register 70" hexmask.long 0x118 0.--31. 1. "CS70,Context swap x (x = 0 to 102)" line.long 0x11C "HASH_CSR71,HASH context swap register 71" hexmask.long 0x11C 0.--31. 1. "CS71,Context swap x (x = 0 to 102)" line.long 0x120 "HASH_CSR72,HASH context swap register 72" hexmask.long 0x120 0.--31. 1. "CS72,Context swap x (x = 0 to 102)" line.long 0x124 "HASH_CSR73,HASH context swap register 73" hexmask.long 0x124 0.--31. 1. "CS73,Context swap x (x = 0 to 102)" line.long 0x128 "HASH_CSR74,HASH context swap register 74" hexmask.long 0x128 0.--31. 1. "CS74,Context swap x (x = 0 to 102)" line.long 0x12C "HASH_CSR75,HASH context swap register 75" hexmask.long 0x12C 0.--31. 1. "CS75,Context swap x (x = 0 to 102)" line.long 0x130 "HASH_CSR76,HASH context swap register 76" hexmask.long 0x130 0.--31. 1. "CS76,Context swap x (x = 0 to 102)" line.long 0x134 "HASH_CSR77,HASH context swap register 77" hexmask.long 0x134 0.--31. 1. "CS77,Context swap x (x = 0 to 102)" line.long 0x138 "HASH_CSR78,HASH context swap register 78" hexmask.long 0x138 0.--31. 1. "CS78,Context swap x (x = 0 to 102)" line.long 0x13C "HASH_CSR79,HASH context swap register 79" hexmask.long 0x13C 0.--31. 1. "CS79,Context swap x (x = 0 to 102)" line.long 0x140 "HASH_CSR80,HASH context swap register 80" hexmask.long 0x140 0.--31. 1. "CS80,Context swap x (x = 0 to 102)" line.long 0x144 "HASH_CSR81,HASH context swap register 81" hexmask.long 0x144 0.--31. 1. "CSx,Context swap x (x = 0 to 102)" line.long 0x148 "HASH_CSR82,HASH context swap register 82" hexmask.long 0x148 0.--31. 1. "CSx,Context swap x (x = 0 to 102)" line.long 0x14C "HASH_CSR83,HASH context swap register 83" hexmask.long 0x14C 0.--31. 1. "CSx,Context swap x (x = 0 to 102)" line.long 0x150 "HASH_CSR84,HASH context swap register 84" hexmask.long 0x150 0.--31. 1. "CSx,Context swap x (x = 0 to 102)" line.long 0x154 "HASH_CSR85,HASH context swap register 85" hexmask.long 0x154 0.--31. 1. "CSx,Context swap x (x = 0 to 102)" line.long 0x158 "HASH_CSR86,HASH context swap register 86" hexmask.long 0x158 0.--31. 1. "CSx,Context swap x (x = 0 to 102)" line.long 0x15C "HASH_CSR87,HASH context swap register 87" hexmask.long 0x15C 0.--31. 1. "CSx,Context swap x (x = 0 to 102)" line.long 0x160 "HASH_CSR88,HASH context swap register 88" hexmask.long 0x160 0.--31. 1. "CSx,Context swap x (x = 0 to 102)" line.long 0x164 "HASH_CSR89,HASH context swap register 89" hexmask.long 0x164 0.--31. 1. "CSx,Context swap x (x = 0 to 102)" line.long 0x168 "HASH_CSR90,HASH context swap register 90" hexmask.long 0x168 0.--31. 1. "CSx,Context swap x (x = 0 to 102)" line.long 0x16C "HASH_CSR91,HASH context swap register 91" hexmask.long 0x16C 0.--31. 1. "CSx,Context swap x (x = 0 to 102)" line.long 0x170 "HASH_CSR92,HASH context swap register 92" hexmask.long 0x170 0.--31. 1. "CSx,Context swap x (x = 0 to 102)" line.long 0x174 "HASH_CSR93,HASH context swap register 93" hexmask.long 0x174 0.--31. 1. "CSx,Context swap x (x = 0 to 102)" line.long 0x178 "HASH_CSR94,HASH context swap register 94" hexmask.long 0x178 0.--31. 1. "CSx,Context swap x (x = 0 to 102)" line.long 0x17C "HASH_CSR95,HASH context swap register 95" hexmask.long 0x17C 0.--31. 1. "CSx,Context swap x (x = 0 to 102)" line.long 0x180 "HASH_CSR96,HASH context swap register 96" hexmask.long 0x180 0.--31. 1. "CSx,Context swap x (x = 0 to 102)" line.long 0x184 "HASH_CSR97,HASH context swap register 97" hexmask.long 0x184 0.--31. 1. "CSx,Context swap x (x = 0 to 102)" line.long 0x188 "HASH_CSR98,HASH context swap register 98" hexmask.long 0x188 0.--31. 1. "CSx,Context swap x (x = 0 to 102)" line.long 0x18C "HASH_CSR99,HASH context swap register 99" hexmask.long 0x18C 0.--31. 1. "CSx,Context swap x (x = 0 to 102)" line.long 0x190 "HASH_CSR100,HASH context swap register 100" hexmask.long 0x190 0.--31. 1. "CSx,Context swap x (x = 0 to 102)" line.long 0x194 "HASH_CSR101,HASH context swap register 101" hexmask.long 0x194 0.--31. 1. "CSx,Context swap x (x = 0 to 102)" line.long 0x198 "HASH_CSR102,HASH context swap register 102" hexmask.long 0x198 0.--31. 1. "CSx,Context swap x (x = 0 to 102)" rgroup.long 0x310++0xC7 line.long 0x0 "HASH_HR0," hexmask.long 0x0 0.--31. 1. "Hx,Hash data x (x = 0 to 4)" line.long 0x4 "HASH_HR1," hexmask.long 0x4 0.--31. 1. "Hx,Hash data x (x = 0 to 4)" line.long 0x8 "HASH_HR2," hexmask.long 0x8 0.--31. 1. "Hx,Hash data x (x = 0 to 4)" line.long 0xC "HASH_HR3," hexmask.long 0xC 0.--31. 1. "Hx,Hash data x (x = 0 to 4)" line.long 0x10 "HASH_HR4," hexmask.long 0x10 0.--31. 1. "Hx,Hash data x (x = 0 to 4)" line.long 0x14 "HASH_HR5," hexmask.long 0x14 0.--31. 1. "Hx,Hash data x (x = 5 to 49)" line.long 0x18 "HASH_HR6," hexmask.long 0x18 0.--31. 1. "Hx,Hash data x (x = 5 to 49)" line.long 0x1C "HASH_HR7," hexmask.long 0x1C 0.--31. 1. "Hx,Hash data x (x = 5 to 49)" line.long 0x20 "HASH_HR8," hexmask.long 0x20 0.--31. 1. "Hx,Hash data x (x = 5 to 49)" line.long 0x24 "HASH_HR9," hexmask.long 0x24 0.--31. 1. "Hx,Hash data x (x = 5 to 49)" line.long 0x28 "HASH_HR10," hexmask.long 0x28 0.--31. 1. "Hx,Hash data x (x = 5 to 49)" line.long 0x2C "HASH_HR11," hexmask.long 0x2C 0.--31. 1. "Hx,Hash data x (x = 5 to 49)" line.long 0x30 "HASH_HR12," hexmask.long 0x30 0.--31. 1. "Hx,Hash data x (x = 5 to 49)" line.long 0x34 "HASH_HR13," hexmask.long 0x34 0.--31. 1. "Hx,Hash data x (x = 5 to 49)" line.long 0x38 "HASH_HR14," hexmask.long 0x38 0.--31. 1. "Hx,Hash data x (x = 5 to 49)" line.long 0x3C "HASH_HR15," hexmask.long 0x3C 0.--31. 1. "Hx,Hash data x (x = 5 to 49)" line.long 0x40 "HASH_HR16," hexmask.long 0x40 0.--31. 1. "Hx,Hash data x (x = 5 to 49)" line.long 0x44 "HASH_HR17," hexmask.long 0x44 0.--31. 1. "Hx,Hash data x (x = 5 to 49)" line.long 0x48 "HASH_HR18," hexmask.long 0x48 0.--31. 1. "Hx,Hash data x (x = 5 to 49)" line.long 0x4C "HASH_HR19," hexmask.long 0x4C 0.--31. 1. "Hx,Hash data x (x = 5 to 49)" line.long 0x50 "HASH_HR20," hexmask.long 0x50 0.--31. 1. "Hx,Hash data x (x = 5 to 49)" line.long 0x54 "HASH_HR21," hexmask.long 0x54 0.--31. 1. "Hx,Hash data x (x = 5 to 49)" line.long 0x58 "HASH_HR22," hexmask.long 0x58 0.--31. 1. "Hx,Hash data x (x = 5 to 49)" line.long 0x5C "HASH_HR23," hexmask.long 0x5C 0.--31. 1. "Hx,Hash data x (x = 5 to 49)" line.long 0x60 "HASH_HR24," hexmask.long 0x60 0.--31. 1. "Hx,Hash data x (x = 5 to 49)" line.long 0x64 "HASH_HR25," hexmask.long 0x64 0.--31. 1. "Hx,Hash data x (x = 5 to 49)" line.long 0x68 "HASH_HR26," hexmask.long 0x68 0.--31. 1. "Hx,Hash data x (x = 5 to 49)" line.long 0x6C "HASH_HR27," hexmask.long 0x6C 0.--31. 1. "Hx,Hash data x (x = 5 to 49)" line.long 0x70 "HASH_HR28," hexmask.long 0x70 0.--31. 1. "Hx,Hash data x (x = 5 to 49)" line.long 0x74 "HASH_HR29," hexmask.long 0x74 0.--31. 1. "Hx,Hash data x (x = 5 to 49)" line.long 0x78 "HASH_HR30," hexmask.long 0x78 0.--31. 1. "Hx,Hash data x (x = 5 to 49)" line.long 0x7C "HASH_HR31," hexmask.long 0x7C 0.--31. 1. "Hx,Hash data x (x = 5 to 49)" line.long 0x80 "HASH_HR32," hexmask.long 0x80 0.--31. 1. "Hx,Hash data x (x = 5 to 49)" line.long 0x84 "HASH_HR33," hexmask.long 0x84 0.--31. 1. "Hx,Hash data x (x = 5 to 49)" line.long 0x88 "HASH_HR34," hexmask.long 0x88 0.--31. 1. "Hx,Hash data x (x = 5 to 49)" line.long 0x8C "HASH_HR35," hexmask.long 0x8C 0.--31. 1. "Hx,Hash data x (x = 5 to 49)" line.long 0x90 "HASH_HR36," hexmask.long 0x90 0.--31. 1. "Hx,Hash data x (x = 5 to 49)" line.long 0x94 "HASH_HR37," hexmask.long 0x94 0.--31. 1. "Hx,Hash data x (x = 5 to 49)" line.long 0x98 "HASH_HR38," hexmask.long 0x98 0.--31. 1. "Hx,Hash data x (x = 5 to 49)" line.long 0x9C "HASH_HR39," hexmask.long 0x9C 0.--31. 1. "Hx,Hash data x (x = 5 to 49)" line.long 0xA0 "HASH_HR40," hexmask.long 0xA0 0.--31. 1. "Hx,Hash data x (x = 5 to 49)" line.long 0xA4 "HASH_HR41," hexmask.long 0xA4 0.--31. 1. "Hx,Hash data x (x = 5 to 49)" line.long 0xA8 "HASH_HR42," hexmask.long 0xA8 0.--31. 1. "Hx,Hash data x (x = 5 to 49)" line.long 0xAC "HASH_HR43," hexmask.long 0xAC 0.--31. 1. "Hx,Hash data x (x = 5 to 49)" line.long 0xB0 "HASH_HR44," hexmask.long 0xB0 0.--31. 1. "Hx,Hash data x (x = 5 to 49)" line.long 0xB4 "HASH_HR45," hexmask.long 0xB4 0.--31. 1. "Hx,Hash data x (x = 5 to 49)" line.long 0xB8 "HASH_HR46," hexmask.long 0xB8 0.--31. 1. "Hx,Hash data x (x = 5 to 49)" line.long 0xBC "HASH_HR47," hexmask.long 0xBC 0.--31. 1. "Hx,Hash data x (x = 5 to 49)" line.long 0xC0 "HASH_HR48," hexmask.long 0xC0 0.--31. 1. "Hx,Hash data x (x = 5 to 49)" line.long 0xC4 "HASH_HR49," hexmask.long 0xC4 0.--31. 1. "Hx,Hash data x (x = 5 to 49)" rgroup.long 0x3F0++0xF line.long 0x0 "HASH_HWCFGR," hexmask.long.byte 0x0 16.--19. 1. "CFG5,HW generic 5" hexmask.long.byte 0x0 12.--15. 1. "CFG4,HW generic 4" newline hexmask.long.byte 0x0 8.--11. 1. "CFG3,HW generic 3" hexmask.long.byte 0x0 4.--7. 1. "CFG2,HW generic 2" newline hexmask.long.byte 0x0 0.--3. 1. "CFG1,HW generic 1" line.long 0x4 "HASH_VERR," hexmask.long.byte 0x4 4.--7. 1. "MAJREV,Major revision" hexmask.long.byte 0x4 0.--3. 1. "MINREV,Minor revision" line.long 0x8 "HASH_IPIDR," hexmask.long 0x8 0.--31. 1. "ID,[31: 0]: Identifier" line.long 0xC "HASH_SIDR," hexmask.long 0xC 0.--31. 1. "SID,Size identification code" tree.end endif sif (cpuis("STM32MP151*")||cpuis("STM32MP153*")||cpuis("STM32MP157*")) tree "HASH1" base ad:0x54002000 group.long 0x0++0xB line.long 0x0 "HASH_CR,HASH control register" bitfld.long 0x0 18. "ALGO1,ALGO1" "0,1" bitfld.long 0x0 16. "LKEY,LKEY" "0,1" bitfld.long 0x0 14. "DMAA,DMAA" "0,1" bitfld.long 0x0 13. "MDMAT,MDMAT" "0,1" rbitfld.long 0x0 12. "DINNE,DINNE" "0,1" hexmask.long.byte 0x0 8.--11. 1. "NBW,NBW" bitfld.long 0x0 7. "ALGO0,ALGO0" "0,1" bitfld.long 0x0 6. "MODE,MODE" "0,1" bitfld.long 0x0 4.--5. "DATATYPE,DATATYPE" "0,1,2,3" bitfld.long 0x0 3. "DMAE,DMAE" "0,1" bitfld.long 0x0 2. "INIT,INIT" "0,1" line.long 0x4 "HASH_DIN,HASH_DIN is the data input register." hexmask.long 0x4 0.--31. 1. "DATAIN,DATAIN" line.long 0x8 "HASH_STR,The HASH_STR register has two functions: It is used to define the number of valid bits in the last word of the message entered in the hash processor (that is the number of valid least significant bits in the last data written to the HASH_DIN.." bitfld.long 0x8 8. "DCAL,DCAL" "0,1" hexmask.long.byte 0x8 0.--4. 1. "NBLW,NBLW" rgroup.long 0xC++0x13 line.long 0x0 "HASH_HR0,HASH digest register 0" hexmask.long 0x0 0.--31. 1. "H0,H0" line.long 0x4 "HASH_HR1,HASH digest register 1" hexmask.long 0x4 0.--31. 1. "H1,H1" line.long 0x8 "HASH_HR2,HASH digest register 2" hexmask.long 0x8 0.--31. 1. "H2,H2" line.long 0xC "HASH_HR3,HASH digest register 3" hexmask.long 0xC 0.--31. 1. "H3,H3" line.long 0x10 "HASH_HR4,HASH digest register 4" hexmask.long 0x10 0.--31. 1. "H4,H4" group.long 0x20++0x7 line.long 0x0 "HASH_IMR,HASH interrupt enable register" bitfld.long 0x0 1. "DCIE,DCIE" "0,1" bitfld.long 0x0 0. "DINIE,DINIE" "0,1" line.long 0x4 "HASH_SR,HASH status register" rbitfld.long 0x4 3. "BUSY,BUSY" "0,1" rbitfld.long 0x4 2. "DMAS,DMAS" "0,1" bitfld.long 0x4 1. "DCIS,DCIS" "0,1" bitfld.long 0x4 0. "DINIS,DINIS" "0,1" group.long 0xF8++0xD7 line.long 0x0 "HASH_CSR0,These registers contain the complete internal register states of the hash processor. They are useful when a context swap has to be done because a high-priority task needs to use the hash processor while it is already used by another task. When.." hexmask.long 0x0 0.--31. 1. "CS0,CS0" line.long 0x4 "HASH_CSR1,HASH context swap registers" hexmask.long 0x4 0.--31. 1. "CS1,CS1" line.long 0x8 "HASH_CSR2,HASH context swap registers" hexmask.long 0x8 0.--31. 1. "CS2,CS2" line.long 0xC "HASH_CSR3,HASH context swap registers" hexmask.long 0xC 0.--31. 1. "CS3,CS3" line.long 0x10 "HASH_CSR4,HASH context swap registers" hexmask.long 0x10 0.--31. 1. "CS4,CS4" line.long 0x14 "HASH_CSR5,HASH context swap registers" hexmask.long 0x14 0.--31. 1. "CS5,CS5" line.long 0x18 "HASH_CSR6,HASH context swap registers" hexmask.long 0x18 0.--31. 1. "CS6,CS6" line.long 0x1C "HASH_CSR7,HASH context swap registers" hexmask.long 0x1C 0.--31. 1. "CS7,CS7" line.long 0x20 "HASH_CSR8,HASH context swap registers" hexmask.long 0x20 0.--31. 1. "CS8,CS8" line.long 0x24 "HASH_CSR9,HASH context swap registers" hexmask.long 0x24 0.--31. 1. "CS9,CS9" line.long 0x28 "HASH_CSR10,HASH context swap registers" hexmask.long 0x28 0.--31. 1. "CS10,CS10" line.long 0x2C "HASH_CSR11,HASH context swap registers" hexmask.long 0x2C 0.--31. 1. "CS11,CS11" line.long 0x30 "HASH_CSR12,HASH context swap registers" hexmask.long 0x30 0.--31. 1. "CS12,CS12" line.long 0x34 "HASH_CSR13,HASH context swap registers" hexmask.long 0x34 0.--31. 1. "CS13,CS13" line.long 0x38 "HASH_CSR14,HASH context swap registers" hexmask.long 0x38 0.--31. 1. "CS14,CS14" line.long 0x3C "HASH_CSR15,HASH context swap registers" hexmask.long 0x3C 0.--31. 1. "CS15,CS15" line.long 0x40 "HASH_CSR16,HASH context swap registers" hexmask.long 0x40 0.--31. 1. "CS16,CS16" line.long 0x44 "HASH_CSR17,HASH context swap registers" hexmask.long 0x44 0.--31. 1. "CS17,CS17" line.long 0x48 "HASH_CSR18,HASH context swap registers" hexmask.long 0x48 0.--31. 1. "CS18,CS18" line.long 0x4C "HASH_CSR19,HASH context swap registers" hexmask.long 0x4C 0.--31. 1. "CS19,CS19" line.long 0x50 "HASH_CSR20,HASH context swap registers" hexmask.long 0x50 0.--31. 1. "CS20,CS20" line.long 0x54 "HASH_CSR21,HASH context swap registers" hexmask.long 0x54 0.--31. 1. "CS21,CS21" line.long 0x58 "HASH_CSR22,HASH context swap registers" hexmask.long 0x58 0.--31. 1. "CS22,CS22" line.long 0x5C "HASH_CSR23,HASH context swap registers" hexmask.long 0x5C 0.--31. 1. "CS23,CS23" line.long 0x60 "HASH_CSR24,HASH context swap registers" hexmask.long 0x60 0.--31. 1. "CS24,CS24" line.long 0x64 "HASH_CSR25,HASH context swap registers" hexmask.long 0x64 0.--31. 1. "CS25,CS25" line.long 0x68 "HASH_CSR26,HASH context swap registers" hexmask.long 0x68 0.--31. 1. "CS26,CS26" line.long 0x6C "HASH_CSR27,HASH context swap registers" hexmask.long 0x6C 0.--31. 1. "CS27,CS27" line.long 0x70 "HASH_CSR28,HASH context swap registers" hexmask.long 0x70 0.--31. 1. "CS28,CS28" line.long 0x74 "HASH_CSR29,HASH context swap registers" hexmask.long 0x74 0.--31. 1. "CS29,CS29" line.long 0x78 "HASH_CSR30,HASH context swap registers" hexmask.long 0x78 0.--31. 1. "CS30,CS30" line.long 0x7C "HASH_CSR31,HASH context swap registers" hexmask.long 0x7C 0.--31. 1. "CS31,CS31" line.long 0x80 "HASH_CSR32,HASH context swap registers" hexmask.long 0x80 0.--31. 1. "CS32,CS32" line.long 0x84 "HASH_CSR33,HASH context swap registers" hexmask.long 0x84 0.--31. 1. "CS33,CS33" line.long 0x88 "HASH_CSR34,HASH context swap registers" hexmask.long 0x88 0.--31. 1. "CS34,CS34" line.long 0x8C "HASH_CSR35,HASH context swap registers" hexmask.long 0x8C 0.--31. 1. "CS35,CS35" line.long 0x90 "HASH_CSR36,HASH context swap registers" hexmask.long 0x90 0.--31. 1. "CS36,CS36" line.long 0x94 "HASH_CSR37,HASH context swap registers" hexmask.long 0x94 0.--31. 1. "CS37,CS37" line.long 0x98 "HASH_CSR38,HASH context swap registers" hexmask.long 0x98 0.--31. 1. "CS38,CS38" line.long 0x9C "HASH_CSR39,HASH context swap registers" hexmask.long 0x9C 0.--31. 1. "CS39,CS39" line.long 0xA0 "HASH_CSR40,HASH context swap registers" hexmask.long 0xA0 0.--31. 1. "CS40,CS40" line.long 0xA4 "HASH_CSR41,HASH context swap registers" hexmask.long 0xA4 0.--31. 1. "CS41,CS41" line.long 0xA8 "HASH_CSR42,HASH context swap registers" hexmask.long 0xA8 0.--31. 1. "CS42,CS42" line.long 0xAC "HASH_CSR43,HASH context swap registers" hexmask.long 0xAC 0.--31. 1. "CS43,CS43" line.long 0xB0 "HASH_CSR44,HASH context swap registers" hexmask.long 0xB0 0.--31. 1. "CS44,CS44" line.long 0xB4 "HASH_CSR45,HASH context swap registers" hexmask.long 0xB4 0.--31. 1. "CS45,CS45" line.long 0xB8 "HASH_CSR46,HASH context swap registers" hexmask.long 0xB8 0.--31. 1. "CS46,CS46" line.long 0xBC "HASH_CSR47,HASH context swap registers" hexmask.long 0xBC 0.--31. 1. "CS47,CS47" line.long 0xC0 "HASH_CSR48,HASH context swap registers" hexmask.long 0xC0 0.--31. 1. "CS48,CS48" line.long 0xC4 "HASH_CSR49,HASH context swap registers" hexmask.long 0xC4 0.--31. 1. "CS49,CS49" line.long 0xC8 "HASH_CSR50,HASH context swap registers" hexmask.long 0xC8 0.--31. 1. "CS50,CS50" line.long 0xCC "HASH_CSR51,HASH context swap registers" hexmask.long 0xCC 0.--31. 1. "CS51,CS51" line.long 0xD0 "HASH_CSR52,HASH context swap registers" hexmask.long 0xD0 0.--31. 1. "CS52,CS52" line.long 0xD4 "HASH_CSR53,HASH context swap registers" hexmask.long 0xD4 0.--31. 1. "CS53,CS53" rgroup.long 0x324++0xB line.long 0x0 "HASH_HR5,HASH digest register 5" hexmask.long 0x0 0.--31. 1. "H5,H5" line.long 0x4 "HASH_HR6,HASH digest register 6" hexmask.long 0x4 0.--31. 1. "H6,H6" line.long 0x8 "HASH_HR7,HASH digest register 7" hexmask.long 0x8 0.--31. 1. "H7,H7" rgroup.long 0x3F0++0xF line.long 0x0 "HASH_HWCFGR,HASH Hardware Configuration Register" hexmask.long.byte 0x0 0.--3. 1. "CFG1,CFG1" line.long 0x4 "HASH_VERR,HASH Version Register" hexmask.long.byte 0x4 0.--7. 1. "VER,VER" line.long 0x8 "HASH_IPIDR,HASH Identification" hexmask.long 0x8 0.--31. 1. "ID,ID" line.long 0xC "HASH_MID,HASH Hardware Magic ID" hexmask.long 0xC 0.--31. 1. "MID,MID" tree.end endif sif (cpuis("STM32MP151*")||cpuis("STM32MP153*")||cpuis("STM32MP157*")) tree "HASH2" base ad:0x4C002000 group.long 0x0++0xB line.long 0x0 "HASH_CR,HASH control register" bitfld.long 0x0 18. "ALGO1,ALGO1" "0,1" bitfld.long 0x0 16. "LKEY,LKEY" "0,1" bitfld.long 0x0 14. "DMAA,DMAA" "0,1" bitfld.long 0x0 13. "MDMAT,MDMAT" "0,1" rbitfld.long 0x0 12. "DINNE,DINNE" "0,1" hexmask.long.byte 0x0 8.--11. 1. "NBW,NBW" bitfld.long 0x0 7. "ALGO0,ALGO0" "0,1" bitfld.long 0x0 6. "MODE,MODE" "0,1" bitfld.long 0x0 4.--5. "DATATYPE,DATATYPE" "0,1,2,3" bitfld.long 0x0 3. "DMAE,DMAE" "0,1" bitfld.long 0x0 2. "INIT,INIT" "0,1" line.long 0x4 "HASH_DIN,HASH_DIN is the data input register." hexmask.long 0x4 0.--31. 1. "DATAIN,DATAIN" line.long 0x8 "HASH_STR,The HASH_STR register has two functions: It is used to define the number of valid bits in the last word of the message entered in the hash processor (that is the number of valid least significant bits in the last data written to the HASH_DIN.." bitfld.long 0x8 8. "DCAL,DCAL" "0,1" hexmask.long.byte 0x8 0.--4. 1. "NBLW,NBLW" rgroup.long 0xC++0x13 line.long 0x0 "HASH_HR0,HASH digest register 0" hexmask.long 0x0 0.--31. 1. "H0,H0" line.long 0x4 "HASH_HR1,HASH digest register 1" hexmask.long 0x4 0.--31. 1. "H1,H1" line.long 0x8 "HASH_HR2,HASH digest register 2" hexmask.long 0x8 0.--31. 1. "H2,H2" line.long 0xC "HASH_HR3,HASH digest register 3" hexmask.long 0xC 0.--31. 1. "H3,H3" line.long 0x10 "HASH_HR4,HASH digest register 4" hexmask.long 0x10 0.--31. 1. "H4,H4" group.long 0x20++0x7 line.long 0x0 "HASH_IMR,HASH interrupt enable register" bitfld.long 0x0 1. "DCIE,DCIE" "0,1" bitfld.long 0x0 0. "DINIE,DINIE" "0,1" line.long 0x4 "HASH_SR,HASH status register" rbitfld.long 0x4 3. "BUSY,BUSY" "0,1" rbitfld.long 0x4 2. "DMAS,DMAS" "0,1" bitfld.long 0x4 1. "DCIS,DCIS" "0,1" bitfld.long 0x4 0. "DINIS,DINIS" "0,1" group.long 0xF8++0xD7 line.long 0x0 "HASH_CSR0,These registers contain the complete internal register states of the hash processor. They are useful when a context swap has to be done because a high-priority task needs to use the hash processor while it is already used by another task. When.." hexmask.long 0x0 0.--31. 1. "CS0,CS0" line.long 0x4 "HASH_CSR1,HASH context swap registers" hexmask.long 0x4 0.--31. 1. "CS1,CS1" line.long 0x8 "HASH_CSR2,HASH context swap registers" hexmask.long 0x8 0.--31. 1. "CS2,CS2" line.long 0xC "HASH_CSR3,HASH context swap registers" hexmask.long 0xC 0.--31. 1. "CS3,CS3" line.long 0x10 "HASH_CSR4,HASH context swap registers" hexmask.long 0x10 0.--31. 1. "CS4,CS4" line.long 0x14 "HASH_CSR5,HASH context swap registers" hexmask.long 0x14 0.--31. 1. "CS5,CS5" line.long 0x18 "HASH_CSR6,HASH context swap registers" hexmask.long 0x18 0.--31. 1. "CS6,CS6" line.long 0x1C "HASH_CSR7,HASH context swap registers" hexmask.long 0x1C 0.--31. 1. "CS7,CS7" line.long 0x20 "HASH_CSR8,HASH context swap registers" hexmask.long 0x20 0.--31. 1. "CS8,CS8" line.long 0x24 "HASH_CSR9,HASH context swap registers" hexmask.long 0x24 0.--31. 1. "CS9,CS9" line.long 0x28 "HASH_CSR10,HASH context swap registers" hexmask.long 0x28 0.--31. 1. "CS10,CS10" line.long 0x2C "HASH_CSR11,HASH context swap registers" hexmask.long 0x2C 0.--31. 1. "CS11,CS11" line.long 0x30 "HASH_CSR12,HASH context swap registers" hexmask.long 0x30 0.--31. 1. "CS12,CS12" line.long 0x34 "HASH_CSR13,HASH context swap registers" hexmask.long 0x34 0.--31. 1. "CS13,CS13" line.long 0x38 "HASH_CSR14,HASH context swap registers" hexmask.long 0x38 0.--31. 1. "CS14,CS14" line.long 0x3C "HASH_CSR15,HASH context swap registers" hexmask.long 0x3C 0.--31. 1. "CS15,CS15" line.long 0x40 "HASH_CSR16,HASH context swap registers" hexmask.long 0x40 0.--31. 1. "CS16,CS16" line.long 0x44 "HASH_CSR17,HASH context swap registers" hexmask.long 0x44 0.--31. 1. "CS17,CS17" line.long 0x48 "HASH_CSR18,HASH context swap registers" hexmask.long 0x48 0.--31. 1. "CS18,CS18" line.long 0x4C "HASH_CSR19,HASH context swap registers" hexmask.long 0x4C 0.--31. 1. "CS19,CS19" line.long 0x50 "HASH_CSR20,HASH context swap registers" hexmask.long 0x50 0.--31. 1. "CS20,CS20" line.long 0x54 "HASH_CSR21,HASH context swap registers" hexmask.long 0x54 0.--31. 1. "CS21,CS21" line.long 0x58 "HASH_CSR22,HASH context swap registers" hexmask.long 0x58 0.--31. 1. "CS22,CS22" line.long 0x5C "HASH_CSR23,HASH context swap registers" hexmask.long 0x5C 0.--31. 1. "CS23,CS23" line.long 0x60 "HASH_CSR24,HASH context swap registers" hexmask.long 0x60 0.--31. 1. "CS24,CS24" line.long 0x64 "HASH_CSR25,HASH context swap registers" hexmask.long 0x64 0.--31. 1. "CS25,CS25" line.long 0x68 "HASH_CSR26,HASH context swap registers" hexmask.long 0x68 0.--31. 1. "CS26,CS26" line.long 0x6C "HASH_CSR27,HASH context swap registers" hexmask.long 0x6C 0.--31. 1. "CS27,CS27" line.long 0x70 "HASH_CSR28,HASH context swap registers" hexmask.long 0x70 0.--31. 1. "CS28,CS28" line.long 0x74 "HASH_CSR29,HASH context swap registers" hexmask.long 0x74 0.--31. 1. "CS29,CS29" line.long 0x78 "HASH_CSR30,HASH context swap registers" hexmask.long 0x78 0.--31. 1. "CS30,CS30" line.long 0x7C "HASH_CSR31,HASH context swap registers" hexmask.long 0x7C 0.--31. 1. "CS31,CS31" line.long 0x80 "HASH_CSR32,HASH context swap registers" hexmask.long 0x80 0.--31. 1. "CS32,CS32" line.long 0x84 "HASH_CSR33,HASH context swap registers" hexmask.long 0x84 0.--31. 1. "CS33,CS33" line.long 0x88 "HASH_CSR34,HASH context swap registers" hexmask.long 0x88 0.--31. 1. "CS34,CS34" line.long 0x8C "HASH_CSR35,HASH context swap registers" hexmask.long 0x8C 0.--31. 1. "CS35,CS35" line.long 0x90 "HASH_CSR36,HASH context swap registers" hexmask.long 0x90 0.--31. 1. "CS36,CS36" line.long 0x94 "HASH_CSR37,HASH context swap registers" hexmask.long 0x94 0.--31. 1. "CS37,CS37" line.long 0x98 "HASH_CSR38,HASH context swap registers" hexmask.long 0x98 0.--31. 1. "CS38,CS38" line.long 0x9C "HASH_CSR39,HASH context swap registers" hexmask.long 0x9C 0.--31. 1. "CS39,CS39" line.long 0xA0 "HASH_CSR40,HASH context swap registers" hexmask.long 0xA0 0.--31. 1. "CS40,CS40" line.long 0xA4 "HASH_CSR41,HASH context swap registers" hexmask.long 0xA4 0.--31. 1. "CS41,CS41" line.long 0xA8 "HASH_CSR42,HASH context swap registers" hexmask.long 0xA8 0.--31. 1. "CS42,CS42" line.long 0xAC "HASH_CSR43,HASH context swap registers" hexmask.long 0xAC 0.--31. 1. "CS43,CS43" line.long 0xB0 "HASH_CSR44,HASH context swap registers" hexmask.long 0xB0 0.--31. 1. "CS44,CS44" line.long 0xB4 "HASH_CSR45,HASH context swap registers" hexmask.long 0xB4 0.--31. 1. "CS45,CS45" line.long 0xB8 "HASH_CSR46,HASH context swap registers" hexmask.long 0xB8 0.--31. 1. "CS46,CS46" line.long 0xBC "HASH_CSR47,HASH context swap registers" hexmask.long 0xBC 0.--31. 1. "CS47,CS47" line.long 0xC0 "HASH_CSR48,HASH context swap registers" hexmask.long 0xC0 0.--31. 1. "CS48,CS48" line.long 0xC4 "HASH_CSR49,HASH context swap registers" hexmask.long 0xC4 0.--31. 1. "CS49,CS49" line.long 0xC8 "HASH_CSR50,HASH context swap registers" hexmask.long 0xC8 0.--31. 1. "CS50,CS50" line.long 0xCC "HASH_CSR51,HASH context swap registers" hexmask.long 0xCC 0.--31. 1. "CS51,CS51" line.long 0xD0 "HASH_CSR52,HASH context swap registers" hexmask.long 0xD0 0.--31. 1. "CS52,CS52" line.long 0xD4 "HASH_CSR53,HASH context swap registers" hexmask.long 0xD4 0.--31. 1. "CS53,CS53" rgroup.long 0x324++0xB line.long 0x0 "HASH_HR5,HASH digest register 5" hexmask.long 0x0 0.--31. 1. "H5,H5" line.long 0x4 "HASH_HR6,HASH digest register 6" hexmask.long 0x4 0.--31. 1. "H6,H6" line.long 0x8 "HASH_HR7,HASH digest register 7" hexmask.long 0x8 0.--31. 1. "H7,H7" rgroup.long 0x3F0++0xF line.long 0x0 "HASH_HWCFGR,HASH Hardware Configuration Register" hexmask.long.byte 0x0 0.--3. 1. "CFG1,CFG1" line.long 0x4 "HASH_VERR,HASH Version Register" hexmask.long.byte 0x4 0.--7. 1. "VER,VER" line.long 0x8 "HASH_IPIDR,HASH Identification" hexmask.long 0x8 0.--31. 1. "ID,ID" line.long 0xC "HASH_MID,HASH Hardware Magic ID" hexmask.long 0xC 0.--31. 1. "MID,MID" tree.end endif tree.end sif (cpuis("STM32MP151*")||cpuis("STM32MP153*")||cpuis("STM32MP157*")) tree "HDMI_CEC" base ad:0x0 tree "HDMI_CEC (HDMI_CEC)" base ad:0x40016000 group.long 0x0++0x7 line.long 0x0 "CEC_CR,CEC control register" bitfld.long 0x0 2. "TXEOM,TXEOM" "0,1" bitfld.long 0x0 1. "TXSOM,TXSOM" "0,1" bitfld.long 0x0 0. "CECEN,CECEN" "0,1" line.long 0x4 "CEC_CFGR,This register is used to configure the HDMI-CEC controller." bitfld.long 0x4 31. "LSTN,LSTN" "0,1" hexmask.long.word 0x4 16.--30. 1. "OAR,OAR" bitfld.long 0x4 8. "SFTOP,SFTOP" "0,1" bitfld.long 0x4 7. "BRDNOGEN,BRDNOGEN" "0,1" bitfld.long 0x4 6. "LBPEGEN,LBPEGEN" "0,1" bitfld.long 0x4 5. "BREGEN,BREGEN" "0,1" bitfld.long 0x4 4. "BRESTP,BRESTP" "0,1" bitfld.long 0x4 3. "RXTOL,RXTOL" "0,1" bitfld.long 0x4 0.--2. "SFT,SFT" "0,1,2,3,4,5,6,7" wgroup.long 0x8++0x3 line.long 0x0 "CEC_TXDR,CEC Tx data register" hexmask.long.byte 0x0 0.--7. 1. "TXD,TXD" rgroup.long 0xC++0x3 line.long 0x0 "CEC_RXDR,CEC Rx data register" hexmask.long.byte 0x0 0.--7. 1. "RXD,RXD" group.long 0x10++0x7 line.long 0x0 "CEC_ISR,CEC Interrupt and Status Register" bitfld.long 0x0 12. "TXACKE,TXACKE" "0,1" bitfld.long 0x0 11. "TXERR,TXERR" "0,1" bitfld.long 0x0 10. "TXUDR,TXUDR" "0,1" bitfld.long 0x0 9. "TXEND,TXEND" "0,1" bitfld.long 0x0 8. "TXBR,TXBR" "0,1" bitfld.long 0x0 7. "ARBLST,ARBLST" "0,1" bitfld.long 0x0 6. "RXACKE,RXACKE" "0,1" bitfld.long 0x0 5. "LBPE,LBPE" "0,1" bitfld.long 0x0 4. "SBPE,SBPE" "0,1" bitfld.long 0x0 3. "BRE,BRE" "0,1" newline bitfld.long 0x0 2. "RXOVR,RXOVR" "0,1" bitfld.long 0x0 1. "RXEND,RXEND" "0,1" bitfld.long 0x0 0. "RXBR,RXBR" "0,1" line.long 0x4 "CEC_IER,CEC interrupt enable register" bitfld.long 0x4 12. "TXACKIE,TXACKIE" "0,1" bitfld.long 0x4 11. "TXERRIE,TXERRIE" "0,1" bitfld.long 0x4 10. "TXUDRIE,TXUDRIE" "0,1" bitfld.long 0x4 9. "TXENDIE,TXENDIE" "0,1" bitfld.long 0x4 8. "TXBRIE,TXBRIE" "0,1" bitfld.long 0x4 7. "ARBLSTIE,ARBLSTIE" "0,1" bitfld.long 0x4 6. "RXACKIE,RXACKIE" "0,1" bitfld.long 0x4 5. "LBPEIE,LBPEIE" "0,1" bitfld.long 0x4 4. "SBPEIE,SBPEIE" "0,1" bitfld.long 0x4 3. "BREIE,BREIE" "0,1" newline bitfld.long 0x4 2. "RXOVRIE,RXOVRIE" "0,1" bitfld.long 0x4 1. "RXENDIE,RXENDIE" "0,1" bitfld.long 0x4 0. "RXBRIE,RXBRIE" "0,1" tree.end tree.end endif tree "HDP (Hardware Debug Port)" base ad:0x5002A000 group.long 0x0++0x7 line.long 0x0 "HDP_CTRL,HDP control register" bitfld.long 0x0 0. "EN,Enable HDP" "0,1" line.long 0x4 "HDP_MUX,HDP multiplexers control register" hexmask.long.byte 0x4 28.--31. 1. "MUX7,Select the HDP7 output among the 16 available signals" hexmask.long.byte 0x4 24.--27. 1. "MUX6,Select the HDP6 output among the 16 available signals" hexmask.long.byte 0x4 20.--23. 1. "MUX5,Select the HDP5 output among the 16 available signals" hexmask.long.byte 0x4 16.--19. 1. "MUX4,Select the HDP4 output among the 16 available signals" hexmask.long.byte 0x4 12.--15. 1. "MUX3,Select the HDP3 output among the 16 available signals" hexmask.long.byte 0x4 8.--11. 1. "MUX2,Select the HDP2 output among the 16 available signals" newline hexmask.long.byte 0x4 4.--7. 1. "MUX1,Select the HDP1 output among the 16 available signals" hexmask.long.byte 0x4 0.--3. 1. "MUX0,Select the HDP0 output among the 16 available signals" group.long 0x10++0xF line.long 0x0 "HDP_VAL,HDP read back value register" sif (cpuis("STM32MP13*")) hexmask.long.byte 0x0 0.--7. 1. "HDPVAL,HDP read back value" endif sif (cpuis("STM32MP151*")) hexmask.long.byte 0x0 0.--7. 1. "HDPVAL,HDPVAL" endif sif (cpuis("STM32MP153*")) hexmask.long.byte 0x0 0.--7. 1. "HDPVAL,HDPVAL" endif sif (cpuis("STM32MP157*")) hexmask.long.byte 0x0 0.--7. 1. "HDPVAL,HDPVAL" endif line.long 0x4 "HDP_GPOSET,HDP general purpose output set register" sif (cpuis("STM32MP13*")) hexmask.long.byte 0x4 0.--7. 1. "HDPGPOSET,HDP general purpose output set" endif sif (cpuis("STM32MP151*")) hexmask.long.byte 0x4 0.--7. 1. "HDPGPOSET,HDPGPOSET" endif sif (cpuis("STM32MP153*")) hexmask.long.byte 0x4 0.--7. 1. "HDPGPOSET,HDPGPOSET" endif sif (cpuis("STM32MP157*")) hexmask.long.byte 0x4 0.--7. 1. "HDPGPOSET,HDPGPOSET" endif line.long 0x8 "HDP_GPOCLR,HDP general purpose output clear register" sif (cpuis("STM32MP13*")) hexmask.long.byte 0x8 0.--7. 1. "HDPGPOCLR,HDP general purpose output clear" endif sif (cpuis("STM32MP151*")) hexmask.long.byte 0x8 0.--7. 1. "HDPGPOCLR,HDPGPOCLR" endif sif (cpuis("STM32MP153*")) hexmask.long.byte 0x8 0.--7. 1. "HDPGPOCLR,HDPGPOCLR" endif sif (cpuis("STM32MP157*")) hexmask.long.byte 0x8 0.--7. 1. "HDPGPOCLR,HDPGPOCLR" endif line.long 0xC "HDP_GPOVAL,HDP general purpose output value register" hexmask.long.byte 0xC 0.--7. 1. "HDPGPOVAL,HDP general purpose output value" group.long 0x3F4++0xB line.long 0x0 "HDP_VERR,HDP version register" sif (cpuis("STM32MP13*")) hexmask.long.byte 0x0 4.--7. 1. "MAJREV,Major revision of the IP" hexmask.long.byte 0x0 0.--3. 1. "MINREV,Minor revision of the IP" endif sif (cpuis("STM32MP151*")) hexmask.long.byte 0x0 4.--7. 1. "MAJREV,MAJREV" hexmask.long.byte 0x0 0.--3. 1. "MINREV,MINREV" endif sif (cpuis("STM32MP153*")) hexmask.long.byte 0x0 4.--7. 1. "MAJREV,MAJREV" hexmask.long.byte 0x0 0.--3. 1. "MINREV,MINREV" newline endif sif (cpuis("STM32MP157*")) hexmask.long.byte 0x0 4.--7. 1. "MAJREV,MAJREV" hexmask.long.byte 0x0 0.--3. 1. "MINREV,MINREV" endif line.long 0x4 "HDP_IPIDR,HDP IP identification register" sif (cpuis("STM32MP13*")) hexmask.long 0x4 0.--31. 1. "ID,IP Identifier" endif sif (cpuis("STM32MP151*")) hexmask.long 0x4 0.--31. 1. "ID,ID" endif sif (cpuis("STM32MP153*")) hexmask.long 0x4 0.--31. 1. "ID,ID" endif sif (cpuis("STM32MP157*")) hexmask.long 0x4 0.--31. 1. "ID,ID" endif line.long 0x8 "HDP_SIDR,HDP size identification register" sif (cpuis("STM32MP13*")) hexmask.long 0x8 0.--31. 1. "SID,Size identifier" endif sif (cpuis("STM32MP151*")) hexmask.long 0x8 0.--31. 1. "SID,SID" endif sif (cpuis("STM32MP153*")) hexmask.long 0x8 0.--31. 1. "SID,SID" endif sif (cpuis("STM32MP157*")) hexmask.long 0x8 0.--31. 1. "SID,SID" endif sif (cpuis("STM32MP151*")) rgroup.long 0x10++0x3 line.long 0x0 "HDP_VAL,HDP value" endif sif (cpuis("STM32MP151*")) wgroup.long 0x14++0x3 line.long 0x0 "HDP_GPOSET,HDP GPO set" endif sif (cpuis("STM32MP151*")) wgroup.long 0x18++0x3 line.long 0x0 "HDP_GPOCLR,HDP GPO clear" endif sif (cpuis("STM32MP151*")) rgroup.long 0x3F4++0x3 line.long 0x0 "HDP_VERR,HDP version register" endif sif (cpuis("STM32MP151*")) rgroup.long 0x3F8++0x3 line.long 0x0 "HDP_IPIDR,HDP IP identification register" endif sif (cpuis("STM32MP151*")) rgroup.long 0x3FC++0x3 line.long 0x0 "HDP_SIDR,HDP size identification register" endif sif (cpuis("STM32MP153*")) rgroup.long 0x10++0x3 line.long 0x0 "HDP_VAL,HDP value" endif sif (cpuis("STM32MP153*")) wgroup.long 0x14++0x3 line.long 0x0 "HDP_GPOSET,HDP GPO set" endif sif (cpuis("STM32MP153*")) wgroup.long 0x18++0x3 line.long 0x0 "HDP_GPOCLR,HDP GPO clear" endif sif (cpuis("STM32MP153*")) rgroup.long 0x3F4++0x3 line.long 0x0 "HDP_VERR,HDP version register" endif sif (cpuis("STM32MP153*")) rgroup.long 0x3F8++0x3 line.long 0x0 "HDP_IPIDR,HDP IP identification register" endif sif (cpuis("STM32MP153*")) rgroup.long 0x3FC++0x3 line.long 0x0 "HDP_SIDR,HDP size identification register" endif sif (cpuis("STM32MP157*")) rgroup.long 0x10++0x3 line.long 0x0 "HDP_VAL,HDP value" endif sif (cpuis("STM32MP157*")) wgroup.long 0x14++0x3 line.long 0x0 "HDP_GPOSET,HDP GPO set" endif sif (cpuis("STM32MP157*")) wgroup.long 0x18++0x3 line.long 0x0 "HDP_GPOCLR,HDP GPO clear" endif sif (cpuis("STM32MP157*")) rgroup.long 0x3F4++0x3 line.long 0x0 "HDP_VERR,HDP version register" endif sif (cpuis("STM32MP157*")) rgroup.long 0x3F8++0x3 line.long 0x0 "HDP_IPIDR,HDP IP identification register" endif sif (cpuis("STM32MP157*")) rgroup.long 0x3FC++0x3 line.long 0x0 "HDP_SIDR,HDP size identification register" endif tree.end sif (cpuis("STM32MP151*")||cpuis("STM32MP153*")||cpuis("STM32MP157*")) tree "HSEM (Hardware Semaphore)" base ad:0x4C000000 group.long 0x0++0x7F line.long 0x0 "HSEM_R0,The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded." bitfld.long 0x0 31. "LOCK,LOCK" "0,1" hexmask.long.byte 0x0 8.--11. 1. "COREID,COREID" hexmask.long.byte 0x0 0.--7. 1. "PROCID,PROCID" line.long 0x4 "HSEM_R1,The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded." bitfld.long 0x4 31. "LOCK,LOCK" "0,1" hexmask.long.byte 0x4 8.--11. 1. "COREID,COREID" hexmask.long.byte 0x4 0.--7. 1. "PROCID,PROCID" line.long 0x8 "HSEM_R2,The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded." bitfld.long 0x8 31. "LOCK,LOCK" "0,1" hexmask.long.byte 0x8 8.--11. 1. "COREID,COREID" hexmask.long.byte 0x8 0.--7. 1. "PROCID,PROCID" line.long 0xC "HSEM_R3,The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded." bitfld.long 0xC 31. "LOCK,LOCK" "0,1" hexmask.long.byte 0xC 8.--11. 1. "COREID,COREID" hexmask.long.byte 0xC 0.--7. 1. "PROCID,PROCID" line.long 0x10 "HSEM_R4,The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded." bitfld.long 0x10 31. "LOCK,LOCK" "0,1" hexmask.long.byte 0x10 8.--11. 1. "COREID,COREID" hexmask.long.byte 0x10 0.--7. 1. "PROCID,PROCID" line.long 0x14 "HSEM_R5,The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded." bitfld.long 0x14 31. "LOCK,LOCK" "0,1" hexmask.long.byte 0x14 8.--11. 1. "COREID,COREID" hexmask.long.byte 0x14 0.--7. 1. "PROCID,PROCID" line.long 0x18 "HSEM_R6,The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded." bitfld.long 0x18 31. "LOCK,LOCK" "0,1" hexmask.long.byte 0x18 8.--11. 1. "COREID,COREID" hexmask.long.byte 0x18 0.--7. 1. "PROCID,PROCID" line.long 0x1C "HSEM_R7,The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded." bitfld.long 0x1C 31. "LOCK,LOCK" "0,1" hexmask.long.byte 0x1C 8.--11. 1. "COREID,COREID" hexmask.long.byte 0x1C 0.--7. 1. "PROCID,PROCID" line.long 0x20 "HSEM_R8,The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded." bitfld.long 0x20 31. "LOCK,LOCK" "0,1" hexmask.long.byte 0x20 8.--11. 1. "COREID,COREID" hexmask.long.byte 0x20 0.--7. 1. "PROCID,PROCID" line.long 0x24 "HSEM_R9,The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded." bitfld.long 0x24 31. "LOCK,LOCK" "0,1" hexmask.long.byte 0x24 8.--11. 1. "COREID,COREID" hexmask.long.byte 0x24 0.--7. 1. "PROCID,PROCID" line.long 0x28 "HSEM_R10,The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded." bitfld.long 0x28 31. "LOCK,LOCK" "0,1" hexmask.long.byte 0x28 8.--11. 1. "COREID,COREID" hexmask.long.byte 0x28 0.--7. 1. "PROCID,PROCID" line.long 0x2C "HSEM_R11,The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded." bitfld.long 0x2C 31. "LOCK,LOCK" "0,1" hexmask.long.byte 0x2C 8.--11. 1. "COREID,COREID" hexmask.long.byte 0x2C 0.--7. 1. "PROCID,PROCID" line.long 0x30 "HSEM_R12,The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded." bitfld.long 0x30 31. "LOCK,LOCK" "0,1" hexmask.long.byte 0x30 8.--11. 1. "COREID,COREID" hexmask.long.byte 0x30 0.--7. 1. "PROCID,PROCID" line.long 0x34 "HSEM_R13,The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded." bitfld.long 0x34 31. "LOCK,LOCK" "0,1" hexmask.long.byte 0x34 8.--11. 1. "COREID,COREID" hexmask.long.byte 0x34 0.--7. 1. "PROCID,PROCID" line.long 0x38 "HSEM_R14,The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded." bitfld.long 0x38 31. "LOCK,LOCK" "0,1" hexmask.long.byte 0x38 8.--11. 1. "COREID,COREID" hexmask.long.byte 0x38 0.--7. 1. "PROCID,PROCID" line.long 0x3C "HSEM_R15,The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded." bitfld.long 0x3C 31. "LOCK,LOCK" "0,1" hexmask.long.byte 0x3C 8.--11. 1. "COREID,COREID" hexmask.long.byte 0x3C 0.--7. 1. "PROCID,PROCID" line.long 0x40 "HSEM_R16,The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded." bitfld.long 0x40 31. "LOCK,LOCK" "0,1" hexmask.long.byte 0x40 8.--11. 1. "COREID,COREID" hexmask.long.byte 0x40 0.--7. 1. "PROCID,PROCID" line.long 0x44 "HSEM_R17,The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded." bitfld.long 0x44 31. "LOCK,LOCK" "0,1" hexmask.long.byte 0x44 8.--11. 1. "COREID,COREID" hexmask.long.byte 0x44 0.--7. 1. "PROCID,PROCID" line.long 0x48 "HSEM_R18,The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded." bitfld.long 0x48 31. "LOCK,LOCK" "0,1" hexmask.long.byte 0x48 8.--11. 1. "COREID,COREID" hexmask.long.byte 0x48 0.--7. 1. "PROCID,PROCID" line.long 0x4C "HSEM_R19,The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded." bitfld.long 0x4C 31. "LOCK,LOCK" "0,1" hexmask.long.byte 0x4C 8.--11. 1. "COREID,COREID" hexmask.long.byte 0x4C 0.--7. 1. "PROCID,PROCID" line.long 0x50 "HSEM_R20,The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded." bitfld.long 0x50 31. "LOCK,LOCK" "0,1" hexmask.long.byte 0x50 8.--11. 1. "COREID,COREID" hexmask.long.byte 0x50 0.--7. 1. "PROCID,PROCID" line.long 0x54 "HSEM_R21,The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded." bitfld.long 0x54 31. "LOCK,LOCK" "0,1" hexmask.long.byte 0x54 8.--11. 1. "COREID,COREID" hexmask.long.byte 0x54 0.--7. 1. "PROCID,PROCID" line.long 0x58 "HSEM_R22,The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded." bitfld.long 0x58 31. "LOCK,LOCK" "0,1" hexmask.long.byte 0x58 8.--11. 1. "COREID,COREID" hexmask.long.byte 0x58 0.--7. 1. "PROCID,PROCID" line.long 0x5C "HSEM_R23,The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded." bitfld.long 0x5C 31. "LOCK,LOCK" "0,1" hexmask.long.byte 0x5C 8.--11. 1. "COREID,COREID" hexmask.long.byte 0x5C 0.--7. 1. "PROCID,PROCID" line.long 0x60 "HSEM_R24,The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded." bitfld.long 0x60 31. "LOCK,LOCK" "0,1" hexmask.long.byte 0x60 8.--11. 1. "COREID,COREID" hexmask.long.byte 0x60 0.--7. 1. "PROCID,PROCID" line.long 0x64 "HSEM_R25,The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded." bitfld.long 0x64 31. "LOCK,LOCK" "0,1" hexmask.long.byte 0x64 8.--11. 1. "COREID,COREID" hexmask.long.byte 0x64 0.--7. 1. "PROCID,PROCID" line.long 0x68 "HSEM_R26,The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded." bitfld.long 0x68 31. "LOCK,LOCK" "0,1" hexmask.long.byte 0x68 8.--11. 1. "COREID,COREID" hexmask.long.byte 0x68 0.--7. 1. "PROCID,PROCID" line.long 0x6C "HSEM_R27,The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded." bitfld.long 0x6C 31. "LOCK,LOCK" "0,1" hexmask.long.byte 0x6C 8.--11. 1. "COREID,COREID" hexmask.long.byte 0x6C 0.--7. 1. "PROCID,PROCID" line.long 0x70 "HSEM_R28,The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded." bitfld.long 0x70 31. "LOCK,LOCK" "0,1" hexmask.long.byte 0x70 8.--11. 1. "COREID,COREID" hexmask.long.byte 0x70 0.--7. 1. "PROCID,PROCID" line.long 0x74 "HSEM_R29,The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded." bitfld.long 0x74 31. "LOCK,LOCK" "0,1" hexmask.long.byte 0x74 8.--11. 1. "COREID,COREID" hexmask.long.byte 0x74 0.--7. 1. "PROCID,PROCID" line.long 0x78 "HSEM_R30,The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded." bitfld.long 0x78 31. "LOCK,LOCK" "0,1" hexmask.long.byte 0x78 8.--11. 1. "COREID,COREID" hexmask.long.byte 0x78 0.--7. 1. "PROCID,PROCID" line.long 0x7C "HSEM_R31,The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded." bitfld.long 0x7C 31. "LOCK,LOCK" "0,1" hexmask.long.byte 0x7C 8.--11. 1. "COREID,COREID" hexmask.long.byte 0x7C 0.--7. 1. "PROCID,PROCID" rgroup.long 0x80++0x7F line.long 0x0 "HSEM_RLR0,Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded." bitfld.long 0x0 31. "LOCK,LOCK" "0,1" hexmask.long.byte 0x0 8.--11. 1. "COREID,COREID" hexmask.long.byte 0x0 0.--7. 1. "PROCID,PROCID" line.long 0x4 "HSEM_RLR1,Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded." bitfld.long 0x4 31. "LOCK,LOCK" "0,1" hexmask.long.byte 0x4 8.--11. 1. "COREID,COREID" hexmask.long.byte 0x4 0.--7. 1. "PROCID,PROCID" line.long 0x8 "HSEM_RLR2,Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded." bitfld.long 0x8 31. "LOCK,LOCK" "0,1" hexmask.long.byte 0x8 8.--11. 1. "COREID,COREID" hexmask.long.byte 0x8 0.--7. 1. "PROCID,PROCID" line.long 0xC "HSEM_RLR3,Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded." bitfld.long 0xC 31. "LOCK,LOCK" "0,1" hexmask.long.byte 0xC 8.--11. 1. "COREID,COREID" hexmask.long.byte 0xC 0.--7. 1. "PROCID,PROCID" line.long 0x10 "HSEM_RLR4,Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded." bitfld.long 0x10 31. "LOCK,LOCK" "0,1" hexmask.long.byte 0x10 8.--11. 1. "COREID,COREID" hexmask.long.byte 0x10 0.--7. 1. "PROCID,PROCID" line.long 0x14 "HSEM_RLR5,Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded." bitfld.long 0x14 31. "LOCK,LOCK" "0,1" hexmask.long.byte 0x14 8.--11. 1. "COREID,COREID" hexmask.long.byte 0x14 0.--7. 1. "PROCID,PROCID" line.long 0x18 "HSEM_RLR6,Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded." bitfld.long 0x18 31. "LOCK,LOCK" "0,1" hexmask.long.byte 0x18 8.--11. 1. "COREID,COREID" hexmask.long.byte 0x18 0.--7. 1. "PROCID,PROCID" line.long 0x1C "HSEM_RLR7,Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded." bitfld.long 0x1C 31. "LOCK,LOCK" "0,1" hexmask.long.byte 0x1C 8.--11. 1. "COREID,COREID" hexmask.long.byte 0x1C 0.--7. 1. "PROCID,PROCID" line.long 0x20 "HSEM_RLR8,Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded." bitfld.long 0x20 31. "LOCK,LOCK" "0,1" hexmask.long.byte 0x20 8.--11. 1. "COREID,COREID" hexmask.long.byte 0x20 0.--7. 1. "PROCID,PROCID" line.long 0x24 "HSEM_RLR9,Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded." bitfld.long 0x24 31. "LOCK,LOCK" "0,1" hexmask.long.byte 0x24 8.--11. 1. "COREID,COREID" hexmask.long.byte 0x24 0.--7. 1. "PROCID,PROCID" line.long 0x28 "HSEM_RLR10,Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded." bitfld.long 0x28 31. "LOCK,LOCK" "0,1" hexmask.long.byte 0x28 8.--11. 1. "COREID,COREID" hexmask.long.byte 0x28 0.--7. 1. "PROCID,PROCID" line.long 0x2C "HSEM_RLR11,Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded." bitfld.long 0x2C 31. "LOCK,LOCK" "0,1" hexmask.long.byte 0x2C 8.--11. 1. "COREID,COREID" hexmask.long.byte 0x2C 0.--7. 1. "PROCID,PROCID" line.long 0x30 "HSEM_RLR12,Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded." bitfld.long 0x30 31. "LOCK,LOCK" "0,1" hexmask.long.byte 0x30 8.--11. 1. "COREID,COREID" hexmask.long.byte 0x30 0.--7. 1. "PROCID,PROCID" line.long 0x34 "HSEM_RLR13,Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded." bitfld.long 0x34 31. "LOCK,LOCK" "0,1" hexmask.long.byte 0x34 8.--11. 1. "COREID,COREID" hexmask.long.byte 0x34 0.--7. 1. "PROCID,PROCID" line.long 0x38 "HSEM_RLR14,Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded." bitfld.long 0x38 31. "LOCK,LOCK" "0,1" hexmask.long.byte 0x38 8.--11. 1. "COREID,COREID" hexmask.long.byte 0x38 0.--7. 1. "PROCID,PROCID" line.long 0x3C "HSEM_RLR15,Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded." bitfld.long 0x3C 31. "LOCK,LOCK" "0,1" hexmask.long.byte 0x3C 8.--11. 1. "COREID,COREID" hexmask.long.byte 0x3C 0.--7. 1. "PROCID,PROCID" line.long 0x40 "HSEM_RLR16,Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded." bitfld.long 0x40 31. "LOCK,LOCK" "0,1" hexmask.long.byte 0x40 8.--11. 1. "COREID,COREID" hexmask.long.byte 0x40 0.--7. 1. "PROCID,PROCID" line.long 0x44 "HSEM_RLR17,Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded." bitfld.long 0x44 31. "LOCK,LOCK" "0,1" hexmask.long.byte 0x44 8.--11. 1. "COREID,COREID" hexmask.long.byte 0x44 0.--7. 1. "PROCID,PROCID" line.long 0x48 "HSEM_RLR18,Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded." bitfld.long 0x48 31. "LOCK,LOCK" "0,1" hexmask.long.byte 0x48 8.--11. 1. "COREID,COREID" hexmask.long.byte 0x48 0.--7. 1. "PROCID,PROCID" line.long 0x4C "HSEM_RLR19,Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded." bitfld.long 0x4C 31. "LOCK,LOCK" "0,1" hexmask.long.byte 0x4C 8.--11. 1. "COREID,COREID" hexmask.long.byte 0x4C 0.--7. 1. "PROCID,PROCID" line.long 0x50 "HSEM_RLR20,Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded." bitfld.long 0x50 31. "LOCK,LOCK" "0,1" hexmask.long.byte 0x50 8.--11. 1. "COREID,COREID" hexmask.long.byte 0x50 0.--7. 1. "PROCID,PROCID" line.long 0x54 "HSEM_RLR21,Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded." bitfld.long 0x54 31. "LOCK,LOCK" "0,1" hexmask.long.byte 0x54 8.--11. 1. "COREID,COREID" hexmask.long.byte 0x54 0.--7. 1. "PROCID,PROCID" line.long 0x58 "HSEM_RLR22,Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded." bitfld.long 0x58 31. "LOCK,LOCK" "0,1" hexmask.long.byte 0x58 8.--11. 1. "COREID,COREID" hexmask.long.byte 0x58 0.--7. 1. "PROCID,PROCID" line.long 0x5C "HSEM_RLR23,Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded." bitfld.long 0x5C 31. "LOCK,LOCK" "0,1" hexmask.long.byte 0x5C 8.--11. 1. "COREID,COREID" hexmask.long.byte 0x5C 0.--7. 1. "PROCID,PROCID" line.long 0x60 "HSEM_RLR24,Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded." bitfld.long 0x60 31. "LOCK,LOCK" "0,1" hexmask.long.byte 0x60 8.--11. 1. "COREID,COREID" hexmask.long.byte 0x60 0.--7. 1. "PROCID,PROCID" line.long 0x64 "HSEM_RLR25,Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded." bitfld.long 0x64 31. "LOCK,LOCK" "0,1" hexmask.long.byte 0x64 8.--11. 1. "COREID,COREID" hexmask.long.byte 0x64 0.--7. 1. "PROCID,PROCID" line.long 0x68 "HSEM_RLR26,Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded." bitfld.long 0x68 31. "LOCK,LOCK" "0,1" hexmask.long.byte 0x68 8.--11. 1. "COREID,COREID" hexmask.long.byte 0x68 0.--7. 1. "PROCID,PROCID" line.long 0x6C "HSEM_RLR27,Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded." bitfld.long 0x6C 31. "LOCK,LOCK" "0,1" hexmask.long.byte 0x6C 8.--11. 1. "COREID,COREID" hexmask.long.byte 0x6C 0.--7. 1. "PROCID,PROCID" line.long 0x70 "HSEM_RLR28,Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded." bitfld.long 0x70 31. "LOCK,LOCK" "0,1" hexmask.long.byte 0x70 8.--11. 1. "COREID,COREID" hexmask.long.byte 0x70 0.--7. 1. "PROCID,PROCID" line.long 0x74 "HSEM_RLR29,Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded." bitfld.long 0x74 31. "LOCK,LOCK" "0,1" hexmask.long.byte 0x74 8.--11. 1. "COREID,COREID" hexmask.long.byte 0x74 0.--7. 1. "PROCID,PROCID" line.long 0x78 "HSEM_RLR30,Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded." bitfld.long 0x78 31. "LOCK,LOCK" "0,1" hexmask.long.byte 0x78 8.--11. 1. "COREID,COREID" hexmask.long.byte 0x78 0.--7. 1. "PROCID,PROCID" line.long 0x7C "HSEM_RLR31,Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded." bitfld.long 0x7C 31. "LOCK,LOCK" "0,1" hexmask.long.byte 0x7C 8.--11. 1. "COREID,COREID" hexmask.long.byte 0x7C 0.--7. 1. "PROCID,PROCID" group.long 0x100++0x7 line.long 0x0 "HSEM_C1IER,HSEM i1terrupt enable register" hexmask.long 0x0 0.--31. 1. "ISE,ISE" line.long 0x4 "HSEM_C1ICR,HSEM i1terrupt clear register" hexmask.long 0x4 0.--31. 1. "ISC,ISC" rgroup.long 0x108++0x7 line.long 0x0 "HSEM_C1ISR,HSEM i1terrupt status register" hexmask.long 0x0 0.--31. 1. "ISF,ISF" line.long 0x4 "HSEM_C1MISR,HSEM i1terrupt status register" hexmask.long 0x4 0.--31. 1. "MISF,MISF" group.long 0x110++0x7 line.long 0x0 "HSEM_C2IER,HSEM i2terrupt enable register" hexmask.long 0x0 0.--31. 1. "ISE,ISE" line.long 0x4 "HSEM_C2ICR,HSEM i2terrupt clear register" hexmask.long 0x4 0.--31. 1. "ISC,ISC" rgroup.long 0x118++0x7 line.long 0x0 "HSEM_C2ISR,HSEM i2terrupt status register" hexmask.long 0x0 0.--31. 1. "ISF,ISF" line.long 0x4 "HSEM_C2MISR,HSEM i2terrupt status register" hexmask.long 0x4 0.--31. 1. "MISF,MISF" wgroup.long 0x140++0x3 line.long 0x0 "HSEM_CR,Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded." hexmask.long.word 0x0 16.--31. 1. "KEY,KEY" hexmask.long.byte 0x0 8.--11. 1. "COREID,COREID" group.long 0x144++0x3 line.long 0x0 "HSEM_KEYR,HSEM interrupt clear register" hexmask.long.word 0x0 16.--31. 1. "KEY,KEY" rgroup.long 0x3EC++0x13 line.long 0x0 "HSEM_HWCFGR2,HSEM hardware configuration register 2" hexmask.long.byte 0x0 12.--15. 1. "MASTERID4,MASTERID4" hexmask.long.byte 0x0 8.--11. 1. "MASTERID3,MASTERID3" hexmask.long.byte 0x0 4.--7. 1. "MASTERID2,MASTERID2" hexmask.long.byte 0x0 0.--3. 1. "MASTERID1,MASTERID1" line.long 0x4 "HSEM_HWCFGR1,HSEM hardware configuration register 1" hexmask.long.byte 0x4 8.--11. 1. "NBINT,NBINT" hexmask.long.byte 0x4 0.--7. 1. "NBSEM,NBSEM" line.long 0x8 "HSEM_VERR,HSEM IP version register" hexmask.long.byte 0x8 4.--7. 1. "MAJREV,MAJREV" hexmask.long.byte 0x8 0.--3. 1. "MINREV,MINREV" line.long 0xC "HSEM_IPIDR,HSEM IP identification register" hexmask.long 0xC 0.--31. 1. "IPID,IPID" line.long 0x10 "HSEM_SIDR,HSEM size identification register" hexmask.long 0x10 0.--31. 1. "SID,SID" tree.end endif tree "I2C (Inter-integrated Circuit Interface)" base ad:0x0 sif (cpuis("STM32MP13*")) tree "I2C1" base ad:0x40012000 group.long 0x0++0x1B line.long 0x0 "I2C_CR1,I2C control register 1" bitfld.long 0x0 23. "PECEN,PEC enable" "0: PEC calculation disabled,1: PEC calculation enabled" bitfld.long 0x0 22. "ALERTEN,SMBus alert enable" "0: The SMBus alert pin (SMBA) is not supported in..,1: The SMBus alert pin is supported in host mode.." newline bitfld.long 0x0 21. "SMBDEN,SMBus device default address enable" "0: Device default address disabled. Address..,1: Device default address enabled. Address.." bitfld.long 0x0 20. "SMBHEN,SMBus host address enable" "0: Host address disabled. Address 0b0001000x is..,1: Host address enabled. Address 0b0001000x is ACKed." newline bitfld.long 0x0 19. "GCEN,General call enable" "0: General call disabled. Address 0b00000000 is..,1: General call enabled. Address 0b00000000 is ACKed." bitfld.long 0x0 18. "WUPEN,Wakeup from Stop mode enable" "0: Wakeup from Stop mode disable.,1: Wakeup from Stop mode enable." newline bitfld.long 0x0 17. "NOSTRETCH,Clock stretching disable" "0: Clock stretching enabled,1: Clock stretching disabled" bitfld.long 0x0 16. "SBC,Slave byte control" "0: Slave byte control disabled,1: Slave byte control enabled" newline bitfld.long 0x0 15. "RXDMAEN,DMA reception requests enable" "0: DMA mode disabled for reception,1: DMA mode enabled for reception" bitfld.long 0x0 14. "TXDMAEN,DMA transmission requests enable" "0: DMA mode disabled for transmission,1: DMA mode enabled for transmission" newline bitfld.long 0x0 12. "ANFOFF,Analog noise filter OFF" "0: Analog noise filter enabled,1: Analog noise filter disabled" hexmask.long.byte 0x0 8.--11. 1. "DNF,Digital noise filter" newline bitfld.long 0x0 7. "ERRIE,Error interrupts enable" "0: Error detection interrupts disabled,1: Error detection interrupts enabled" bitfld.long 0x0 6. "TCIE,Transfer Complete interrupt enable" "0: Transfer Complete interrupt disabled,1: Transfer Complete interrupt enabled" newline bitfld.long 0x0 5. "STOPIE,Stop detection Interrupt enable" "0: Stop detection (STOPF) interrupt disabled,1: Stop detection (STOPF) interrupt enabled" bitfld.long 0x0 4. "NACKIE,Not acknowledge received Interrupt enable" "0: Not acknowledge (NACKF) received interrupts..,1: Not acknowledge (NACKF) received interrupts.." newline bitfld.long 0x0 3. "ADDRIE,Address match Interrupt enable (slave only)" "0: Address match (ADDR) interrupts disabled,1: Address match (ADDR) interrupts enabled" bitfld.long 0x0 2. "RXIE,RX Interrupt enable" "0: Receive (RXNE) interrupt disabled,1: Receive (RXNE) interrupt enabled" newline bitfld.long 0x0 1. "TXIE,TX Interrupt enable" "0: Transmit (TXIS) interrupt disabled,1: Transmit (TXIS) interrupt enabled" bitfld.long 0x0 0. "PE,Peripheral enable" "0: Peripheral disable,1: Peripheral enable" line.long 0x4 "I2C_CR2,I2C control register 2" bitfld.long 0x4 26. "PECBYTE,Packet error checking byte" "0: No PEC transfer.,1: PEC transmission/reception is requested" bitfld.long 0x4 25. "AUTOEND,Automatic end mode (master mode)" "0: software end mode: TC flag is set when NBYTES..,1: Automatic end mode: a STOP condition is.." newline bitfld.long 0x4 24. "RELOAD,NBYTES reload mode" "0: The transfer is completed after the NBYTES data..,1: The transfer is not completed after the NBYTES.." hexmask.long.byte 0x4 16.--23. 1. "NBYTES,Number of bytes" newline bitfld.long 0x4 15. "NACK,NACK generation (slave mode)" "0: an ACK is sent after current received byte.,1: a NACK is sent after current received byte." bitfld.long 0x4 14. "STOP,Stop generation (master mode)" "0: No Stop generation.,1: Stop generation after current byte transfer." newline bitfld.long 0x4 13. "START,Start generation" "0: No Start generation.,1: Restart/Start generation:" bitfld.long 0x4 12. "HEAD10R,10-bit address header only read direction (master receiver mode)" "0: The master sends the complete 10 bit slave..,1: The master only sends the 1st 7 bits of the 10.." newline bitfld.long 0x4 11. "ADD10,10-bit addressing mode (master mode)" "0: The master operates in 7-bit addressing mode,1: The master operates in 10-bit addressing mode" bitfld.long 0x4 10. "RD_WRN,Transfer direction (master mode)" "0: Master requests a write transfer.,1: Master requests a read transfer." newline hexmask.long.word 0x4 0.--9. 1. "SADD,Slave address (master mode)" line.long 0x8 "I2C_OAR1,I2C own address 1 register" bitfld.long 0x8 15. "OA1EN,Own Address 1 enable" "0: Own address 1 disabled. The received slave..,1: Own address 1 enabled. The received slave.." bitfld.long 0x8 10. "OA1MODE,Own Address 1 10-bit mode" "0: Own address 1 is a 7-bit address.,1: Own address 1 is a 10-bit address." newline hexmask.long.word 0x8 0.--9. 1. "OA1,Interface own slave address" line.long 0xC "I2C_OAR2,I2C own address 2 register" bitfld.long 0xC 15. "OA2EN,Own Address 2 enable" "0: Own address 2 disabled. The received slave..,1: Own address 2 enabled. The received slave.." bitfld.long 0xC 8.--10. "OA2MSK,Own Address 2 masks" "0: No mask,1: OA2[1] is masked and don’t care. Only OA2[7:2]..,2: OA2[2:1] are masked and don’t care. Only..,3: OA2[3:1] are masked and don’t care. Only..,4: OA2[4:1] are masked and don’t care. Only..,5: OA2[5:1] are masked and don’t care. Only..,6: OA2[6:1] are masked and don’t care. Only..,7: OA2[7:1] are masked and don’t care. No.." newline hexmask.long.byte 0xC 1.--7. 1. "OA2,Interface address" line.long 0x10 "I2C_TIMINGR,I2C timing register" hexmask.long.byte 0x10 28.--31. 1. "PRESC,Timing prescaler" hexmask.long.byte 0x10 20.--23. 1. "SCLDEL,Data setup time" newline hexmask.long.byte 0x10 16.--19. 1. "SDADEL,Data hold time" hexmask.long.byte 0x10 8.--15. 1. "SCLH,SCL high period (master mode)" newline hexmask.long.byte 0x10 0.--7. 1. "SCLL,SCL low period (master mode)" line.long 0x14 "I2C_TIMEOUTR,I2C timeout register" bitfld.long 0x14 31. "TEXTEN,Extended clock timeout enable" "0: Extended clock timeout detection is disabled,1: Extended clock timeout detection is enabled." hexmask.long.word 0x14 16.--27. 1. "TIMEOUTB,Bus timeout B" newline bitfld.long 0x14 15. "TIMOUTEN,Clock timeout enable" "0: SCL timeout detection is disabled,1: SCL timeout detection is enabled: when SCL is.." bitfld.long 0x14 12. "TIDLE,Idle clock timeout detection" "0: TIMEOUTA is used to detect SCL low timeout,1: TIMEOUTA is used to detect both SCL and SDA high.." newline hexmask.long.word 0x14 0.--11. 1. "TIMEOUTA,Bus Timeout A" line.long 0x18 "I2C_ISR,I2C interrupt and status register" hexmask.long.byte 0x18 17.--23. 1. "ADDCODE,Address match code (Slave mode)" rbitfld.long 0x18 16. "DIR,Transfer direction (Slave mode)" "0: Write transfer slave enters receiver mode.,1: Read transfer slave enters transmitter mode." newline rbitfld.long 0x18 15. "BUSY,Bus busy" "0,1" rbitfld.long 0x18 13. "ALERT,SMBus alert" "0,1" newline rbitfld.long 0x18 12. "TIMEOUT,Timeout or tLOW detection flag" "0,1" rbitfld.long 0x18 11. "PECERR,PEC Error in reception" "0,1" newline rbitfld.long 0x18 10. "OVR,Overrun/Underrun (slave mode)" "0,1" rbitfld.long 0x18 9. "ARLO,Arbitration lost" "0,1" newline rbitfld.long 0x18 8. "BERR,Bus error" "0,1" rbitfld.long 0x18 7. "TCR,Transfer Complete Reload" "0,1" newline rbitfld.long 0x18 6. "TC,Transfer Complete (master mode)" "0,1" rbitfld.long 0x18 5. "STOPF,Stop detection flag" "0,1" newline rbitfld.long 0x18 4. "NACKF,Not Acknowledge received flag" "0,1" rbitfld.long 0x18 3. "ADDR,Address matched (slave mode)" "0,1" newline rbitfld.long 0x18 2. "RXNE,Receive data register not empty (receivers)" "0,1" bitfld.long 0x18 1. "TXIS,Transmit interrupt status (transmitters)" "0,1" newline bitfld.long 0x18 0. "TXE,Transmit data register empty (transmitters)" "0,1" wgroup.long 0x1C++0x3 line.long 0x0 "I2C_ICR,I2C interrupt clear register" bitfld.long 0x0 13. "ALERTCF,Alert flag clear" "0,1" bitfld.long 0x0 12. "TIMOUTCF,Timeout detection flag clear" "0,1" newline bitfld.long 0x0 11. "PECCF,PEC Error flag clear" "0,1" bitfld.long 0x0 10. "OVRCF,Overrun/Underrun flag clear" "0,1" newline bitfld.long 0x0 9. "ARLOCF,Arbitration lost flag clear" "0,1" bitfld.long 0x0 8. "BERRCF,Bus error flag clear" "0,1" newline bitfld.long 0x0 5. "STOPCF,STOP detection flag clear" "0,1" bitfld.long 0x0 4. "NACKCF,Not Acknowledge flag clear" "0,1" newline bitfld.long 0x0 3. "ADDRCF,Address matched flag clear" "0,1" rgroup.long 0x20++0x7 line.long 0x0 "I2C_PECR,I2C PEC register" hexmask.long.byte 0x0 0.--7. 1. "PEC,Packet error checking register" line.long 0x4 "I2C_RXDR,I2C receive data register" hexmask.long.byte 0x4 0.--7. 1. "RXDATA,8-bit receive data" group.long 0x28++0x3 line.long 0x0 "I2C_TXDR,I2C transmit data register" hexmask.long.byte 0x0 0.--7. 1. "TXDATA,8-bit transmit data" rgroup.long 0x3F0++0xF line.long 0x0 "I2C_HWCFGR,I2C hardware configuration register" hexmask.long.byte 0x0 8.--11. 1. "WKP,Wakeup from Stop mode" hexmask.long.byte 0x0 4.--7. 1. "ASYN,Independent kernel clock" newline hexmask.long.byte 0x0 0.--3. 1. "SMBUS,SMBus mode" line.long 0x4 "I2C_VERR,I2C version register" hexmask.long.byte 0x4 4.--7. 1. "MAJREV,Major revision" hexmask.long.byte 0x4 0.--3. 1. "MINREV,Minor revision" line.long 0x8 "I2C_IPIDR,I2C identification register" hexmask.long 0x8 0.--31. 1. "ID,Identifier." line.long 0xC "I2C_SIDR,I2C size identification register" hexmask.long 0xC 0.--31. 1. "SID,Size identifier." tree.end endif sif (cpuis("STM32MP13*")) tree "I2C2" base ad:0x40013000 group.long 0x0++0x1B line.long 0x0 "I2C_CR1,I2C control register 1" bitfld.long 0x0 23. "PECEN,PEC enable" "0: PEC calculation disabled,1: PEC calculation enabled" bitfld.long 0x0 22. "ALERTEN,SMBus alert enable" "0: The SMBus alert pin (SMBA) is not supported in..,1: The SMBus alert pin is supported in host mode.." newline bitfld.long 0x0 21. "SMBDEN,SMBus device default address enable" "0: Device default address disabled. Address..,1: Device default address enabled. Address.." bitfld.long 0x0 20. "SMBHEN,SMBus host address enable" "0: Host address disabled. Address 0b0001000x is..,1: Host address enabled. Address 0b0001000x is ACKed." newline bitfld.long 0x0 19. "GCEN,General call enable" "0: General call disabled. Address 0b00000000 is..,1: General call enabled. Address 0b00000000 is ACKed." bitfld.long 0x0 18. "WUPEN,Wakeup from Stop mode enable" "0: Wakeup from Stop mode disable.,1: Wakeup from Stop mode enable." newline bitfld.long 0x0 17. "NOSTRETCH,Clock stretching disable" "0: Clock stretching enabled,1: Clock stretching disabled" bitfld.long 0x0 16. "SBC,Slave byte control" "0: Slave byte control disabled,1: Slave byte control enabled" newline bitfld.long 0x0 15. "RXDMAEN,DMA reception requests enable" "0: DMA mode disabled for reception,1: DMA mode enabled for reception" bitfld.long 0x0 14. "TXDMAEN,DMA transmission requests enable" "0: DMA mode disabled for transmission,1: DMA mode enabled for transmission" newline bitfld.long 0x0 12. "ANFOFF,Analog noise filter OFF" "0: Analog noise filter enabled,1: Analog noise filter disabled" hexmask.long.byte 0x0 8.--11. 1. "DNF,Digital noise filter" newline bitfld.long 0x0 7. "ERRIE,Error interrupts enable" "0: Error detection interrupts disabled,1: Error detection interrupts enabled" bitfld.long 0x0 6. "TCIE,Transfer Complete interrupt enable" "0: Transfer Complete interrupt disabled,1: Transfer Complete interrupt enabled" newline bitfld.long 0x0 5. "STOPIE,Stop detection Interrupt enable" "0: Stop detection (STOPF) interrupt disabled,1: Stop detection (STOPF) interrupt enabled" bitfld.long 0x0 4. "NACKIE,Not acknowledge received Interrupt enable" "0: Not acknowledge (NACKF) received interrupts..,1: Not acknowledge (NACKF) received interrupts.." newline bitfld.long 0x0 3. "ADDRIE,Address match Interrupt enable (slave only)" "0: Address match (ADDR) interrupts disabled,1: Address match (ADDR) interrupts enabled" bitfld.long 0x0 2. "RXIE,RX Interrupt enable" "0: Receive (RXNE) interrupt disabled,1: Receive (RXNE) interrupt enabled" newline bitfld.long 0x0 1. "TXIE,TX Interrupt enable" "0: Transmit (TXIS) interrupt disabled,1: Transmit (TXIS) interrupt enabled" bitfld.long 0x0 0. "PE,Peripheral enable" "0: Peripheral disable,1: Peripheral enable" line.long 0x4 "I2C_CR2,I2C control register 2" bitfld.long 0x4 26. "PECBYTE,Packet error checking byte" "0: No PEC transfer.,1: PEC transmission/reception is requested" bitfld.long 0x4 25. "AUTOEND,Automatic end mode (master mode)" "0: software end mode: TC flag is set when NBYTES..,1: Automatic end mode: a STOP condition is.." newline bitfld.long 0x4 24. "RELOAD,NBYTES reload mode" "0: The transfer is completed after the NBYTES data..,1: The transfer is not completed after the NBYTES.." hexmask.long.byte 0x4 16.--23. 1. "NBYTES,Number of bytes" newline bitfld.long 0x4 15. "NACK,NACK generation (slave mode)" "0: an ACK is sent after current received byte.,1: a NACK is sent after current received byte." bitfld.long 0x4 14. "STOP,Stop generation (master mode)" "0: No Stop generation.,1: Stop generation after current byte transfer." newline bitfld.long 0x4 13. "START,Start generation" "0: No Start generation.,1: Restart/Start generation:" bitfld.long 0x4 12. "HEAD10R,10-bit address header only read direction (master receiver mode)" "0: The master sends the complete 10 bit slave..,1: The master only sends the 1st 7 bits of the 10.." newline bitfld.long 0x4 11. "ADD10,10-bit addressing mode (master mode)" "0: The master operates in 7-bit addressing mode,1: The master operates in 10-bit addressing mode" bitfld.long 0x4 10. "RD_WRN,Transfer direction (master mode)" "0: Master requests a write transfer.,1: Master requests a read transfer." newline hexmask.long.word 0x4 0.--9. 1. "SADD,Slave address (master mode)" line.long 0x8 "I2C_OAR1,I2C own address 1 register" bitfld.long 0x8 15. "OA1EN,Own Address 1 enable" "0: Own address 1 disabled. The received slave..,1: Own address 1 enabled. The received slave.." bitfld.long 0x8 10. "OA1MODE,Own Address 1 10-bit mode" "0: Own address 1 is a 7-bit address.,1: Own address 1 is a 10-bit address." newline hexmask.long.word 0x8 0.--9. 1. "OA1,Interface own slave address" line.long 0xC "I2C_OAR2,I2C own address 2 register" bitfld.long 0xC 15. "OA2EN,Own Address 2 enable" "0: Own address 2 disabled. The received slave..,1: Own address 2 enabled. The received slave.." bitfld.long 0xC 8.--10. "OA2MSK,Own Address 2 masks" "0: No mask,1: OA2[1] is masked and don’t care. Only OA2[7:2]..,2: OA2[2:1] are masked and don’t care. Only..,3: OA2[3:1] are masked and don’t care. Only..,4: OA2[4:1] are masked and don’t care. Only..,5: OA2[5:1] are masked and don’t care. Only..,6: OA2[6:1] are masked and don’t care. Only..,7: OA2[7:1] are masked and don’t care. No.." newline hexmask.long.byte 0xC 1.--7. 1. "OA2,Interface address" line.long 0x10 "I2C_TIMINGR,I2C timing register" hexmask.long.byte 0x10 28.--31. 1. "PRESC,Timing prescaler" hexmask.long.byte 0x10 20.--23. 1. "SCLDEL,Data setup time" newline hexmask.long.byte 0x10 16.--19. 1. "SDADEL,Data hold time" hexmask.long.byte 0x10 8.--15. 1. "SCLH,SCL high period (master mode)" newline hexmask.long.byte 0x10 0.--7. 1. "SCLL,SCL low period (master mode)" line.long 0x14 "I2C_TIMEOUTR,I2C timeout register" bitfld.long 0x14 31. "TEXTEN,Extended clock timeout enable" "0: Extended clock timeout detection is disabled,1: Extended clock timeout detection is enabled." hexmask.long.word 0x14 16.--27. 1. "TIMEOUTB,Bus timeout B" newline bitfld.long 0x14 15. "TIMOUTEN,Clock timeout enable" "0: SCL timeout detection is disabled,1: SCL timeout detection is enabled: when SCL is.." bitfld.long 0x14 12. "TIDLE,Idle clock timeout detection" "0: TIMEOUTA is used to detect SCL low timeout,1: TIMEOUTA is used to detect both SCL and SDA high.." newline hexmask.long.word 0x14 0.--11. 1. "TIMEOUTA,Bus Timeout A" line.long 0x18 "I2C_ISR,I2C interrupt and status register" hexmask.long.byte 0x18 17.--23. 1. "ADDCODE,Address match code (Slave mode)" rbitfld.long 0x18 16. "DIR,Transfer direction (Slave mode)" "0: Write transfer slave enters receiver mode.,1: Read transfer slave enters transmitter mode." newline rbitfld.long 0x18 15. "BUSY,Bus busy" "0,1" rbitfld.long 0x18 13. "ALERT,SMBus alert" "0,1" newline rbitfld.long 0x18 12. "TIMEOUT,Timeout or tLOW detection flag" "0,1" rbitfld.long 0x18 11. "PECERR,PEC Error in reception" "0,1" newline rbitfld.long 0x18 10. "OVR,Overrun/Underrun (slave mode)" "0,1" rbitfld.long 0x18 9. "ARLO,Arbitration lost" "0,1" newline rbitfld.long 0x18 8. "BERR,Bus error" "0,1" rbitfld.long 0x18 7. "TCR,Transfer Complete Reload" "0,1" newline rbitfld.long 0x18 6. "TC,Transfer Complete (master mode)" "0,1" rbitfld.long 0x18 5. "STOPF,Stop detection flag" "0,1" newline rbitfld.long 0x18 4. "NACKF,Not Acknowledge received flag" "0,1" rbitfld.long 0x18 3. "ADDR,Address matched (slave mode)" "0,1" newline rbitfld.long 0x18 2. "RXNE,Receive data register not empty (receivers)" "0,1" bitfld.long 0x18 1. "TXIS,Transmit interrupt status (transmitters)" "0,1" newline bitfld.long 0x18 0. "TXE,Transmit data register empty (transmitters)" "0,1" wgroup.long 0x1C++0x3 line.long 0x0 "I2C_ICR,I2C interrupt clear register" bitfld.long 0x0 13. "ALERTCF,Alert flag clear" "0,1" bitfld.long 0x0 12. "TIMOUTCF,Timeout detection flag clear" "0,1" newline bitfld.long 0x0 11. "PECCF,PEC Error flag clear" "0,1" bitfld.long 0x0 10. "OVRCF,Overrun/Underrun flag clear" "0,1" newline bitfld.long 0x0 9. "ARLOCF,Arbitration lost flag clear" "0,1" bitfld.long 0x0 8. "BERRCF,Bus error flag clear" "0,1" newline bitfld.long 0x0 5. "STOPCF,STOP detection flag clear" "0,1" bitfld.long 0x0 4. "NACKCF,Not Acknowledge flag clear" "0,1" newline bitfld.long 0x0 3. "ADDRCF,Address matched flag clear" "0,1" rgroup.long 0x20++0x7 line.long 0x0 "I2C_PECR,I2C PEC register" hexmask.long.byte 0x0 0.--7. 1. "PEC,Packet error checking register" line.long 0x4 "I2C_RXDR,I2C receive data register" hexmask.long.byte 0x4 0.--7. 1. "RXDATA,8-bit receive data" group.long 0x28++0x3 line.long 0x0 "I2C_TXDR,I2C transmit data register" hexmask.long.byte 0x0 0.--7. 1. "TXDATA,8-bit transmit data" rgroup.long 0x3F0++0xF line.long 0x0 "I2C_HWCFGR,I2C hardware configuration register" hexmask.long.byte 0x0 8.--11. 1. "WKP,Wakeup from Stop mode" hexmask.long.byte 0x0 4.--7. 1. "ASYN,Independent kernel clock" newline hexmask.long.byte 0x0 0.--3. 1. "SMBUS,SMBus mode" line.long 0x4 "I2C_VERR,I2C version register" hexmask.long.byte 0x4 4.--7. 1. "MAJREV,Major revision" hexmask.long.byte 0x4 0.--3. 1. "MINREV,Minor revision" line.long 0x8 "I2C_IPIDR,I2C identification register" hexmask.long 0x8 0.--31. 1. "ID,Identifier." line.long 0xC "I2C_SIDR,I2C size identification register" hexmask.long 0xC 0.--31. 1. "SID,Size identifier." tree.end endif sif (cpuis("STM32MP13*")) tree "I2C3" base ad:0x4C004000 group.long 0x0++0x1B line.long 0x0 "I2C_CR1,I2C control register 1" bitfld.long 0x0 23. "PECEN,PEC enable" "0: PEC calculation disabled,1: PEC calculation enabled" bitfld.long 0x0 22. "ALERTEN,SMBus alert enable" "0: The SMBus alert pin (SMBA) is not supported in..,1: The SMBus alert pin is supported in host mode.." newline bitfld.long 0x0 21. "SMBDEN,SMBus device default address enable" "0: Device default address disabled. Address..,1: Device default address enabled. Address.." bitfld.long 0x0 20. "SMBHEN,SMBus host address enable" "0: Host address disabled. Address 0b0001000x is..,1: Host address enabled. Address 0b0001000x is ACKed." newline bitfld.long 0x0 19. "GCEN,General call enable" "0: General call disabled. Address 0b00000000 is..,1: General call enabled. Address 0b00000000 is ACKed." bitfld.long 0x0 18. "WUPEN,Wakeup from Stop mode enable" "0: Wakeup from Stop mode disable.,1: Wakeup from Stop mode enable." newline bitfld.long 0x0 17. "NOSTRETCH,Clock stretching disable" "0: Clock stretching enabled,1: Clock stretching disabled" bitfld.long 0x0 16. "SBC,Slave byte control" "0: Slave byte control disabled,1: Slave byte control enabled" newline bitfld.long 0x0 15. "RXDMAEN,DMA reception requests enable" "0: DMA mode disabled for reception,1: DMA mode enabled for reception" bitfld.long 0x0 14. "TXDMAEN,DMA transmission requests enable" "0: DMA mode disabled for transmission,1: DMA mode enabled for transmission" newline bitfld.long 0x0 12. "ANFOFF,Analog noise filter OFF" "0: Analog noise filter enabled,1: Analog noise filter disabled" hexmask.long.byte 0x0 8.--11. 1. "DNF,Digital noise filter" newline bitfld.long 0x0 7. "ERRIE,Error interrupts enable" "0: Error detection interrupts disabled,1: Error detection interrupts enabled" bitfld.long 0x0 6. "TCIE,Transfer Complete interrupt enable" "0: Transfer Complete interrupt disabled,1: Transfer Complete interrupt enabled" newline bitfld.long 0x0 5. "STOPIE,Stop detection Interrupt enable" "0: Stop detection (STOPF) interrupt disabled,1: Stop detection (STOPF) interrupt enabled" bitfld.long 0x0 4. "NACKIE,Not acknowledge received Interrupt enable" "0: Not acknowledge (NACKF) received interrupts..,1: Not acknowledge (NACKF) received interrupts.." newline bitfld.long 0x0 3. "ADDRIE,Address match Interrupt enable (slave only)" "0: Address match (ADDR) interrupts disabled,1: Address match (ADDR) interrupts enabled" bitfld.long 0x0 2. "RXIE,RX Interrupt enable" "0: Receive (RXNE) interrupt disabled,1: Receive (RXNE) interrupt enabled" newline bitfld.long 0x0 1. "TXIE,TX Interrupt enable" "0: Transmit (TXIS) interrupt disabled,1: Transmit (TXIS) interrupt enabled" bitfld.long 0x0 0. "PE,Peripheral enable" "0: Peripheral disable,1: Peripheral enable" line.long 0x4 "I2C_CR2,I2C control register 2" bitfld.long 0x4 26. "PECBYTE,Packet error checking byte" "0: No PEC transfer.,1: PEC transmission/reception is requested" bitfld.long 0x4 25. "AUTOEND,Automatic end mode (master mode)" "0: software end mode: TC flag is set when NBYTES..,1: Automatic end mode: a STOP condition is.." newline bitfld.long 0x4 24. "RELOAD,NBYTES reload mode" "0: The transfer is completed after the NBYTES data..,1: The transfer is not completed after the NBYTES.." hexmask.long.byte 0x4 16.--23. 1. "NBYTES,Number of bytes" newline bitfld.long 0x4 15. "NACK,NACK generation (slave mode)" "0: an ACK is sent after current received byte.,1: a NACK is sent after current received byte." bitfld.long 0x4 14. "STOP,Stop generation (master mode)" "0: No Stop generation.,1: Stop generation after current byte transfer." newline bitfld.long 0x4 13. "START,Start generation" "0: No Start generation.,1: Restart/Start generation:" bitfld.long 0x4 12. "HEAD10R,10-bit address header only read direction (master receiver mode)" "0: The master sends the complete 10 bit slave..,1: The master only sends the 1st 7 bits of the 10.." newline bitfld.long 0x4 11. "ADD10,10-bit addressing mode (master mode)" "0: The master operates in 7-bit addressing mode,1: The master operates in 10-bit addressing mode" bitfld.long 0x4 10. "RD_WRN,Transfer direction (master mode)" "0: Master requests a write transfer.,1: Master requests a read transfer." newline hexmask.long.word 0x4 0.--9. 1. "SADD,Slave address (master mode)" line.long 0x8 "I2C_OAR1,I2C own address 1 register" bitfld.long 0x8 15. "OA1EN,Own Address 1 enable" "0: Own address 1 disabled. The received slave..,1: Own address 1 enabled. The received slave.." bitfld.long 0x8 10. "OA1MODE,Own Address 1 10-bit mode" "0: Own address 1 is a 7-bit address.,1: Own address 1 is a 10-bit address." newline hexmask.long.word 0x8 0.--9. 1. "OA1,Interface own slave address" line.long 0xC "I2C_OAR2,I2C own address 2 register" bitfld.long 0xC 15. "OA2EN,Own Address 2 enable" "0: Own address 2 disabled. The received slave..,1: Own address 2 enabled. The received slave.." bitfld.long 0xC 8.--10. "OA2MSK,Own Address 2 masks" "0: No mask,1: OA2[1] is masked and don’t care. Only OA2[7:2]..,2: OA2[2:1] are masked and don’t care. Only..,3: OA2[3:1] are masked and don’t care. Only..,4: OA2[4:1] are masked and don’t care. Only..,5: OA2[5:1] are masked and don’t care. Only..,6: OA2[6:1] are masked and don’t care. Only..,7: OA2[7:1] are masked and don’t care. No.." newline hexmask.long.byte 0xC 1.--7. 1. "OA2,Interface address" line.long 0x10 "I2C_TIMINGR,I2C timing register" hexmask.long.byte 0x10 28.--31. 1. "PRESC,Timing prescaler" hexmask.long.byte 0x10 20.--23. 1. "SCLDEL,Data setup time" newline hexmask.long.byte 0x10 16.--19. 1. "SDADEL,Data hold time" hexmask.long.byte 0x10 8.--15. 1. "SCLH,SCL high period (master mode)" newline hexmask.long.byte 0x10 0.--7. 1. "SCLL,SCL low period (master mode)" line.long 0x14 "I2C_TIMEOUTR,I2C timeout register" bitfld.long 0x14 31. "TEXTEN,Extended clock timeout enable" "0: Extended clock timeout detection is disabled,1: Extended clock timeout detection is enabled." hexmask.long.word 0x14 16.--27. 1. "TIMEOUTB,Bus timeout B" newline bitfld.long 0x14 15. "TIMOUTEN,Clock timeout enable" "0: SCL timeout detection is disabled,1: SCL timeout detection is enabled: when SCL is.." bitfld.long 0x14 12. "TIDLE,Idle clock timeout detection" "0: TIMEOUTA is used to detect SCL low timeout,1: TIMEOUTA is used to detect both SCL and SDA high.." newline hexmask.long.word 0x14 0.--11. 1. "TIMEOUTA,Bus Timeout A" line.long 0x18 "I2C_ISR,I2C interrupt and status register" hexmask.long.byte 0x18 17.--23. 1. "ADDCODE,Address match code (Slave mode)" rbitfld.long 0x18 16. "DIR,Transfer direction (Slave mode)" "0: Write transfer slave enters receiver mode.,1: Read transfer slave enters transmitter mode." newline rbitfld.long 0x18 15. "BUSY,Bus busy" "0,1" rbitfld.long 0x18 13. "ALERT,SMBus alert" "0,1" newline rbitfld.long 0x18 12. "TIMEOUT,Timeout or tLOW detection flag" "0,1" rbitfld.long 0x18 11. "PECERR,PEC Error in reception" "0,1" newline rbitfld.long 0x18 10. "OVR,Overrun/Underrun (slave mode)" "0,1" rbitfld.long 0x18 9. "ARLO,Arbitration lost" "0,1" newline rbitfld.long 0x18 8. "BERR,Bus error" "0,1" rbitfld.long 0x18 7. "TCR,Transfer Complete Reload" "0,1" newline rbitfld.long 0x18 6. "TC,Transfer Complete (master mode)" "0,1" rbitfld.long 0x18 5. "STOPF,Stop detection flag" "0,1" newline rbitfld.long 0x18 4. "NACKF,Not Acknowledge received flag" "0,1" rbitfld.long 0x18 3. "ADDR,Address matched (slave mode)" "0,1" newline rbitfld.long 0x18 2. "RXNE,Receive data register not empty (receivers)" "0,1" bitfld.long 0x18 1. "TXIS,Transmit interrupt status (transmitters)" "0,1" newline bitfld.long 0x18 0. "TXE,Transmit data register empty (transmitters)" "0,1" wgroup.long 0x1C++0x3 line.long 0x0 "I2C_ICR,I2C interrupt clear register" bitfld.long 0x0 13. "ALERTCF,Alert flag clear" "0,1" bitfld.long 0x0 12. "TIMOUTCF,Timeout detection flag clear" "0,1" newline bitfld.long 0x0 11. "PECCF,PEC Error flag clear" "0,1" bitfld.long 0x0 10. "OVRCF,Overrun/Underrun flag clear" "0,1" newline bitfld.long 0x0 9. "ARLOCF,Arbitration lost flag clear" "0,1" bitfld.long 0x0 8. "BERRCF,Bus error flag clear" "0,1" newline bitfld.long 0x0 5. "STOPCF,STOP detection flag clear" "0,1" bitfld.long 0x0 4. "NACKCF,Not Acknowledge flag clear" "0,1" newline bitfld.long 0x0 3. "ADDRCF,Address matched flag clear" "0,1" rgroup.long 0x20++0x7 line.long 0x0 "I2C_PECR,I2C PEC register" hexmask.long.byte 0x0 0.--7. 1. "PEC,Packet error checking register" line.long 0x4 "I2C_RXDR,I2C receive data register" hexmask.long.byte 0x4 0.--7. 1. "RXDATA,8-bit receive data" group.long 0x28++0x3 line.long 0x0 "I2C_TXDR,I2C transmit data register" hexmask.long.byte 0x0 0.--7. 1. "TXDATA,8-bit transmit data" rgroup.long 0x3F0++0xF line.long 0x0 "I2C_HWCFGR,I2C hardware configuration register" hexmask.long.byte 0x0 8.--11. 1. "WKP,Wakeup from Stop mode" hexmask.long.byte 0x0 4.--7. 1. "ASYN,Independent kernel clock" newline hexmask.long.byte 0x0 0.--3. 1. "SMBUS,SMBus mode" line.long 0x4 "I2C_VERR,I2C version register" hexmask.long.byte 0x4 4.--7. 1. "MAJREV,Major revision" hexmask.long.byte 0x4 0.--3. 1. "MINREV,Minor revision" line.long 0x8 "I2C_IPIDR,I2C identification register" hexmask.long 0x8 0.--31. 1. "ID,Identifier." line.long 0xC "I2C_SIDR,I2C size identification register" hexmask.long 0xC 0.--31. 1. "SID,Size identifier." tree.end endif sif (cpuis("STM32MP13*")) tree "I2C4" base ad:0x4C005000 group.long 0x0++0x1B line.long 0x0 "I2C_CR1,I2C control register 1" bitfld.long 0x0 23. "PECEN,PEC enable" "0: PEC calculation disabled,1: PEC calculation enabled" bitfld.long 0x0 22. "ALERTEN,SMBus alert enable" "0: The SMBus alert pin (SMBA) is not supported in..,1: The SMBus alert pin is supported in host mode.." newline bitfld.long 0x0 21. "SMBDEN,SMBus device default address enable" "0: Device default address disabled. Address..,1: Device default address enabled. Address.." bitfld.long 0x0 20. "SMBHEN,SMBus host address enable" "0: Host address disabled. Address 0b0001000x is..,1: Host address enabled. Address 0b0001000x is ACKed." newline bitfld.long 0x0 19. "GCEN,General call enable" "0: General call disabled. Address 0b00000000 is..,1: General call enabled. Address 0b00000000 is ACKed." bitfld.long 0x0 18. "WUPEN,Wakeup from Stop mode enable" "0: Wakeup from Stop mode disable.,1: Wakeup from Stop mode enable." newline bitfld.long 0x0 17. "NOSTRETCH,Clock stretching disable" "0: Clock stretching enabled,1: Clock stretching disabled" bitfld.long 0x0 16. "SBC,Slave byte control" "0: Slave byte control disabled,1: Slave byte control enabled" newline bitfld.long 0x0 15. "RXDMAEN,DMA reception requests enable" "0: DMA mode disabled for reception,1: DMA mode enabled for reception" bitfld.long 0x0 14. "TXDMAEN,DMA transmission requests enable" "0: DMA mode disabled for transmission,1: DMA mode enabled for transmission" newline bitfld.long 0x0 12. "ANFOFF,Analog noise filter OFF" "0: Analog noise filter enabled,1: Analog noise filter disabled" hexmask.long.byte 0x0 8.--11. 1. "DNF,Digital noise filter" newline bitfld.long 0x0 7. "ERRIE,Error interrupts enable" "0: Error detection interrupts disabled,1: Error detection interrupts enabled" bitfld.long 0x0 6. "TCIE,Transfer Complete interrupt enable" "0: Transfer Complete interrupt disabled,1: Transfer Complete interrupt enabled" newline bitfld.long 0x0 5. "STOPIE,Stop detection Interrupt enable" "0: Stop detection (STOPF) interrupt disabled,1: Stop detection (STOPF) interrupt enabled" bitfld.long 0x0 4. "NACKIE,Not acknowledge received Interrupt enable" "0: Not acknowledge (NACKF) received interrupts..,1: Not acknowledge (NACKF) received interrupts.." newline bitfld.long 0x0 3. "ADDRIE,Address match Interrupt enable (slave only)" "0: Address match (ADDR) interrupts disabled,1: Address match (ADDR) interrupts enabled" bitfld.long 0x0 2. "RXIE,RX Interrupt enable" "0: Receive (RXNE) interrupt disabled,1: Receive (RXNE) interrupt enabled" newline bitfld.long 0x0 1. "TXIE,TX Interrupt enable" "0: Transmit (TXIS) interrupt disabled,1: Transmit (TXIS) interrupt enabled" bitfld.long 0x0 0. "PE,Peripheral enable" "0: Peripheral disable,1: Peripheral enable" line.long 0x4 "I2C_CR2,I2C control register 2" bitfld.long 0x4 26. "PECBYTE,Packet error checking byte" "0: No PEC transfer.,1: PEC transmission/reception is requested" bitfld.long 0x4 25. "AUTOEND,Automatic end mode (master mode)" "0: software end mode: TC flag is set when NBYTES..,1: Automatic end mode: a STOP condition is.." newline bitfld.long 0x4 24. "RELOAD,NBYTES reload mode" "0: The transfer is completed after the NBYTES data..,1: The transfer is not completed after the NBYTES.." hexmask.long.byte 0x4 16.--23. 1. "NBYTES,Number of bytes" newline bitfld.long 0x4 15. "NACK,NACK generation (slave mode)" "0: an ACK is sent after current received byte.,1: a NACK is sent after current received byte." bitfld.long 0x4 14. "STOP,Stop generation (master mode)" "0: No Stop generation.,1: Stop generation after current byte transfer." newline bitfld.long 0x4 13. "START,Start generation" "0: No Start generation.,1: Restart/Start generation:" bitfld.long 0x4 12. "HEAD10R,10-bit address header only read direction (master receiver mode)" "0: The master sends the complete 10 bit slave..,1: The master only sends the 1st 7 bits of the 10.." newline bitfld.long 0x4 11. "ADD10,10-bit addressing mode (master mode)" "0: The master operates in 7-bit addressing mode,1: The master operates in 10-bit addressing mode" bitfld.long 0x4 10. "RD_WRN,Transfer direction (master mode)" "0: Master requests a write transfer.,1: Master requests a read transfer." newline hexmask.long.word 0x4 0.--9. 1. "SADD,Slave address (master mode)" line.long 0x8 "I2C_OAR1,I2C own address 1 register" bitfld.long 0x8 15. "OA1EN,Own Address 1 enable" "0: Own address 1 disabled. The received slave..,1: Own address 1 enabled. The received slave.." bitfld.long 0x8 10. "OA1MODE,Own Address 1 10-bit mode" "0: Own address 1 is a 7-bit address.,1: Own address 1 is a 10-bit address." newline hexmask.long.word 0x8 0.--9. 1. "OA1,Interface own slave address" line.long 0xC "I2C_OAR2,I2C own address 2 register" bitfld.long 0xC 15. "OA2EN,Own Address 2 enable" "0: Own address 2 disabled. The received slave..,1: Own address 2 enabled. The received slave.." bitfld.long 0xC 8.--10. "OA2MSK,Own Address 2 masks" "0: No mask,1: OA2[1] is masked and don’t care. Only OA2[7:2]..,2: OA2[2:1] are masked and don’t care. Only..,3: OA2[3:1] are masked and don’t care. Only..,4: OA2[4:1] are masked and don’t care. Only..,5: OA2[5:1] are masked and don’t care. Only..,6: OA2[6:1] are masked and don’t care. Only..,7: OA2[7:1] are masked and don’t care. No.." newline hexmask.long.byte 0xC 1.--7. 1. "OA2,Interface address" line.long 0x10 "I2C_TIMINGR,I2C timing register" hexmask.long.byte 0x10 28.--31. 1. "PRESC,Timing prescaler" hexmask.long.byte 0x10 20.--23. 1. "SCLDEL,Data setup time" newline hexmask.long.byte 0x10 16.--19. 1. "SDADEL,Data hold time" hexmask.long.byte 0x10 8.--15. 1. "SCLH,SCL high period (master mode)" newline hexmask.long.byte 0x10 0.--7. 1. "SCLL,SCL low period (master mode)" line.long 0x14 "I2C_TIMEOUTR,I2C timeout register" bitfld.long 0x14 31. "TEXTEN,Extended clock timeout enable" "0: Extended clock timeout detection is disabled,1: Extended clock timeout detection is enabled." hexmask.long.word 0x14 16.--27. 1. "TIMEOUTB,Bus timeout B" newline bitfld.long 0x14 15. "TIMOUTEN,Clock timeout enable" "0: SCL timeout detection is disabled,1: SCL timeout detection is enabled: when SCL is.." bitfld.long 0x14 12. "TIDLE,Idle clock timeout detection" "0: TIMEOUTA is used to detect SCL low timeout,1: TIMEOUTA is used to detect both SCL and SDA high.." newline hexmask.long.word 0x14 0.--11. 1. "TIMEOUTA,Bus Timeout A" line.long 0x18 "I2C_ISR,I2C interrupt and status register" hexmask.long.byte 0x18 17.--23. 1. "ADDCODE,Address match code (Slave mode)" rbitfld.long 0x18 16. "DIR,Transfer direction (Slave mode)" "0: Write transfer slave enters receiver mode.,1: Read transfer slave enters transmitter mode." newline rbitfld.long 0x18 15. "BUSY,Bus busy" "0,1" rbitfld.long 0x18 13. "ALERT,SMBus alert" "0,1" newline rbitfld.long 0x18 12. "TIMEOUT,Timeout or tLOW detection flag" "0,1" rbitfld.long 0x18 11. "PECERR,PEC Error in reception" "0,1" newline rbitfld.long 0x18 10. "OVR,Overrun/Underrun (slave mode)" "0,1" rbitfld.long 0x18 9. "ARLO,Arbitration lost" "0,1" newline rbitfld.long 0x18 8. "BERR,Bus error" "0,1" rbitfld.long 0x18 7. "TCR,Transfer Complete Reload" "0,1" newline rbitfld.long 0x18 6. "TC,Transfer Complete (master mode)" "0,1" rbitfld.long 0x18 5. "STOPF,Stop detection flag" "0,1" newline rbitfld.long 0x18 4. "NACKF,Not Acknowledge received flag" "0,1" rbitfld.long 0x18 3. "ADDR,Address matched (slave mode)" "0,1" newline rbitfld.long 0x18 2. "RXNE,Receive data register not empty (receivers)" "0,1" bitfld.long 0x18 1. "TXIS,Transmit interrupt status (transmitters)" "0,1" newline bitfld.long 0x18 0. "TXE,Transmit data register empty (transmitters)" "0,1" wgroup.long 0x1C++0x3 line.long 0x0 "I2C_ICR,I2C interrupt clear register" bitfld.long 0x0 13. "ALERTCF,Alert flag clear" "0,1" bitfld.long 0x0 12. "TIMOUTCF,Timeout detection flag clear" "0,1" newline bitfld.long 0x0 11. "PECCF,PEC Error flag clear" "0,1" bitfld.long 0x0 10. "OVRCF,Overrun/Underrun flag clear" "0,1" newline bitfld.long 0x0 9. "ARLOCF,Arbitration lost flag clear" "0,1" bitfld.long 0x0 8. "BERRCF,Bus error flag clear" "0,1" newline bitfld.long 0x0 5. "STOPCF,STOP detection flag clear" "0,1" bitfld.long 0x0 4. "NACKCF,Not Acknowledge flag clear" "0,1" newline bitfld.long 0x0 3. "ADDRCF,Address matched flag clear" "0,1" rgroup.long 0x20++0x7 line.long 0x0 "I2C_PECR,I2C PEC register" hexmask.long.byte 0x0 0.--7. 1. "PEC,Packet error checking register" line.long 0x4 "I2C_RXDR,I2C receive data register" hexmask.long.byte 0x4 0.--7. 1. "RXDATA,8-bit receive data" group.long 0x28++0x3 line.long 0x0 "I2C_TXDR,I2C transmit data register" hexmask.long.byte 0x0 0.--7. 1. "TXDATA,8-bit transmit data" rgroup.long 0x3F0++0xF line.long 0x0 "I2C_HWCFGR,I2C hardware configuration register" hexmask.long.byte 0x0 8.--11. 1. "WKP,Wakeup from Stop mode" hexmask.long.byte 0x0 4.--7. 1. "ASYN,Independent kernel clock" newline hexmask.long.byte 0x0 0.--3. 1. "SMBUS,SMBus mode" line.long 0x4 "I2C_VERR,I2C version register" hexmask.long.byte 0x4 4.--7. 1. "MAJREV,Major revision" hexmask.long.byte 0x4 0.--3. 1. "MINREV,Minor revision" line.long 0x8 "I2C_IPIDR,I2C identification register" hexmask.long 0x8 0.--31. 1. "ID,Identifier." line.long 0xC "I2C_SIDR,I2C size identification register" hexmask.long 0xC 0.--31. 1. "SID,Size identifier." tree.end endif sif (cpuis("STM32MP13*")) tree "I2C5" base ad:0x4C006000 group.long 0x0++0x1B line.long 0x0 "I2C_CR1,I2C control register 1" bitfld.long 0x0 23. "PECEN,PEC enable" "0: PEC calculation disabled,1: PEC calculation enabled" bitfld.long 0x0 22. "ALERTEN,SMBus alert enable" "0: The SMBus alert pin (SMBA) is not supported in..,1: The SMBus alert pin is supported in host mode.." newline bitfld.long 0x0 21. "SMBDEN,SMBus device default address enable" "0: Device default address disabled. Address..,1: Device default address enabled. Address.." bitfld.long 0x0 20. "SMBHEN,SMBus host address enable" "0: Host address disabled. Address 0b0001000x is..,1: Host address enabled. Address 0b0001000x is ACKed." newline bitfld.long 0x0 19. "GCEN,General call enable" "0: General call disabled. Address 0b00000000 is..,1: General call enabled. Address 0b00000000 is ACKed." bitfld.long 0x0 18. "WUPEN,Wakeup from Stop mode enable" "0: Wakeup from Stop mode disable.,1: Wakeup from Stop mode enable." newline bitfld.long 0x0 17. "NOSTRETCH,Clock stretching disable" "0: Clock stretching enabled,1: Clock stretching disabled" bitfld.long 0x0 16. "SBC,Slave byte control" "0: Slave byte control disabled,1: Slave byte control enabled" newline bitfld.long 0x0 15. "RXDMAEN,DMA reception requests enable" "0: DMA mode disabled for reception,1: DMA mode enabled for reception" bitfld.long 0x0 14. "TXDMAEN,DMA transmission requests enable" "0: DMA mode disabled for transmission,1: DMA mode enabled for transmission" newline bitfld.long 0x0 12. "ANFOFF,Analog noise filter OFF" "0: Analog noise filter enabled,1: Analog noise filter disabled" hexmask.long.byte 0x0 8.--11. 1. "DNF,Digital noise filter" newline bitfld.long 0x0 7. "ERRIE,Error interrupts enable" "0: Error detection interrupts disabled,1: Error detection interrupts enabled" bitfld.long 0x0 6. "TCIE,Transfer Complete interrupt enable" "0: Transfer Complete interrupt disabled,1: Transfer Complete interrupt enabled" newline bitfld.long 0x0 5. "STOPIE,Stop detection Interrupt enable" "0: Stop detection (STOPF) interrupt disabled,1: Stop detection (STOPF) interrupt enabled" bitfld.long 0x0 4. "NACKIE,Not acknowledge received Interrupt enable" "0: Not acknowledge (NACKF) received interrupts..,1: Not acknowledge (NACKF) received interrupts.." newline bitfld.long 0x0 3. "ADDRIE,Address match Interrupt enable (slave only)" "0: Address match (ADDR) interrupts disabled,1: Address match (ADDR) interrupts enabled" bitfld.long 0x0 2. "RXIE,RX Interrupt enable" "0: Receive (RXNE) interrupt disabled,1: Receive (RXNE) interrupt enabled" newline bitfld.long 0x0 1. "TXIE,TX Interrupt enable" "0: Transmit (TXIS) interrupt disabled,1: Transmit (TXIS) interrupt enabled" bitfld.long 0x0 0. "PE,Peripheral enable" "0: Peripheral disable,1: Peripheral enable" line.long 0x4 "I2C_CR2,I2C control register 2" bitfld.long 0x4 26. "PECBYTE,Packet error checking byte" "0: No PEC transfer.,1: PEC transmission/reception is requested" bitfld.long 0x4 25. "AUTOEND,Automatic end mode (master mode)" "0: software end mode: TC flag is set when NBYTES..,1: Automatic end mode: a STOP condition is.." newline bitfld.long 0x4 24. "RELOAD,NBYTES reload mode" "0: The transfer is completed after the NBYTES data..,1: The transfer is not completed after the NBYTES.." hexmask.long.byte 0x4 16.--23. 1. "NBYTES,Number of bytes" newline bitfld.long 0x4 15. "NACK,NACK generation (slave mode)" "0: an ACK is sent after current received byte.,1: a NACK is sent after current received byte." bitfld.long 0x4 14. "STOP,Stop generation (master mode)" "0: No Stop generation.,1: Stop generation after current byte transfer." newline bitfld.long 0x4 13. "START,Start generation" "0: No Start generation.,1: Restart/Start generation:" bitfld.long 0x4 12. "HEAD10R,10-bit address header only read direction (master receiver mode)" "0: The master sends the complete 10 bit slave..,1: The master only sends the 1st 7 bits of the 10.." newline bitfld.long 0x4 11. "ADD10,10-bit addressing mode (master mode)" "0: The master operates in 7-bit addressing mode,1: The master operates in 10-bit addressing mode" bitfld.long 0x4 10. "RD_WRN,Transfer direction (master mode)" "0: Master requests a write transfer.,1: Master requests a read transfer." newline hexmask.long.word 0x4 0.--9. 1. "SADD,Slave address (master mode)" line.long 0x8 "I2C_OAR1,I2C own address 1 register" bitfld.long 0x8 15. "OA1EN,Own Address 1 enable" "0: Own address 1 disabled. The received slave..,1: Own address 1 enabled. The received slave.." bitfld.long 0x8 10. "OA1MODE,Own Address 1 10-bit mode" "0: Own address 1 is a 7-bit address.,1: Own address 1 is a 10-bit address." newline hexmask.long.word 0x8 0.--9. 1. "OA1,Interface own slave address" line.long 0xC "I2C_OAR2,I2C own address 2 register" bitfld.long 0xC 15. "OA2EN,Own Address 2 enable" "0: Own address 2 disabled. The received slave..,1: Own address 2 enabled. The received slave.." bitfld.long 0xC 8.--10. "OA2MSK,Own Address 2 masks" "0: No mask,1: OA2[1] is masked and don’t care. Only OA2[7:2]..,2: OA2[2:1] are masked and don’t care. Only..,3: OA2[3:1] are masked and don’t care. Only..,4: OA2[4:1] are masked and don’t care. Only..,5: OA2[5:1] are masked and don’t care. Only..,6: OA2[6:1] are masked and don’t care. Only..,7: OA2[7:1] are masked and don’t care. No.." newline hexmask.long.byte 0xC 1.--7. 1. "OA2,Interface address" line.long 0x10 "I2C_TIMINGR,I2C timing register" hexmask.long.byte 0x10 28.--31. 1. "PRESC,Timing prescaler" hexmask.long.byte 0x10 20.--23. 1. "SCLDEL,Data setup time" newline hexmask.long.byte 0x10 16.--19. 1. "SDADEL,Data hold time" hexmask.long.byte 0x10 8.--15. 1. "SCLH,SCL high period (master mode)" newline hexmask.long.byte 0x10 0.--7. 1. "SCLL,SCL low period (master mode)" line.long 0x14 "I2C_TIMEOUTR,I2C timeout register" bitfld.long 0x14 31. "TEXTEN,Extended clock timeout enable" "0: Extended clock timeout detection is disabled,1: Extended clock timeout detection is enabled." hexmask.long.word 0x14 16.--27. 1. "TIMEOUTB,Bus timeout B" newline bitfld.long 0x14 15. "TIMOUTEN,Clock timeout enable" "0: SCL timeout detection is disabled,1: SCL timeout detection is enabled: when SCL is.." bitfld.long 0x14 12. "TIDLE,Idle clock timeout detection" "0: TIMEOUTA is used to detect SCL low timeout,1: TIMEOUTA is used to detect both SCL and SDA high.." newline hexmask.long.word 0x14 0.--11. 1. "TIMEOUTA,Bus Timeout A" line.long 0x18 "I2C_ISR,I2C interrupt and status register" hexmask.long.byte 0x18 17.--23. 1. "ADDCODE,Address match code (Slave mode)" rbitfld.long 0x18 16. "DIR,Transfer direction (Slave mode)" "0: Write transfer slave enters receiver mode.,1: Read transfer slave enters transmitter mode." newline rbitfld.long 0x18 15. "BUSY,Bus busy" "0,1" rbitfld.long 0x18 13. "ALERT,SMBus alert" "0,1" newline rbitfld.long 0x18 12. "TIMEOUT,Timeout or tLOW detection flag" "0,1" rbitfld.long 0x18 11. "PECERR,PEC Error in reception" "0,1" newline rbitfld.long 0x18 10. "OVR,Overrun/Underrun (slave mode)" "0,1" rbitfld.long 0x18 9. "ARLO,Arbitration lost" "0,1" newline rbitfld.long 0x18 8. "BERR,Bus error" "0,1" rbitfld.long 0x18 7. "TCR,Transfer Complete Reload" "0,1" newline rbitfld.long 0x18 6. "TC,Transfer Complete (master mode)" "0,1" rbitfld.long 0x18 5. "STOPF,Stop detection flag" "0,1" newline rbitfld.long 0x18 4. "NACKF,Not Acknowledge received flag" "0,1" rbitfld.long 0x18 3. "ADDR,Address matched (slave mode)" "0,1" newline rbitfld.long 0x18 2. "RXNE,Receive data register not empty (receivers)" "0,1" bitfld.long 0x18 1. "TXIS,Transmit interrupt status (transmitters)" "0,1" newline bitfld.long 0x18 0. "TXE,Transmit data register empty (transmitters)" "0,1" wgroup.long 0x1C++0x3 line.long 0x0 "I2C_ICR,I2C interrupt clear register" bitfld.long 0x0 13. "ALERTCF,Alert flag clear" "0,1" bitfld.long 0x0 12. "TIMOUTCF,Timeout detection flag clear" "0,1" newline bitfld.long 0x0 11. "PECCF,PEC Error flag clear" "0,1" bitfld.long 0x0 10. "OVRCF,Overrun/Underrun flag clear" "0,1" newline bitfld.long 0x0 9. "ARLOCF,Arbitration lost flag clear" "0,1" bitfld.long 0x0 8. "BERRCF,Bus error flag clear" "0,1" newline bitfld.long 0x0 5. "STOPCF,STOP detection flag clear" "0,1" bitfld.long 0x0 4. "NACKCF,Not Acknowledge flag clear" "0,1" newline bitfld.long 0x0 3. "ADDRCF,Address matched flag clear" "0,1" rgroup.long 0x20++0x7 line.long 0x0 "I2C_PECR,I2C PEC register" hexmask.long.byte 0x0 0.--7. 1. "PEC,Packet error checking register" line.long 0x4 "I2C_RXDR,I2C receive data register" hexmask.long.byte 0x4 0.--7. 1. "RXDATA,8-bit receive data" group.long 0x28++0x3 line.long 0x0 "I2C_TXDR,I2C transmit data register" hexmask.long.byte 0x0 0.--7. 1. "TXDATA,8-bit transmit data" rgroup.long 0x3F0++0xF line.long 0x0 "I2C_HWCFGR,I2C hardware configuration register" hexmask.long.byte 0x0 8.--11. 1. "WKP,Wakeup from Stop mode" hexmask.long.byte 0x0 4.--7. 1. "ASYN,Independent kernel clock" newline hexmask.long.byte 0x0 0.--3. 1. "SMBUS,SMBus mode" line.long 0x4 "I2C_VERR,I2C version register" hexmask.long.byte 0x4 4.--7. 1. "MAJREV,Major revision" hexmask.long.byte 0x4 0.--3. 1. "MINREV,Minor revision" line.long 0x8 "I2C_IPIDR,I2C identification register" hexmask.long 0x8 0.--31. 1. "ID,Identifier." line.long 0xC "I2C_SIDR,I2C size identification register" hexmask.long 0xC 0.--31. 1. "SID,Size identifier." tree.end endif sif (cpuis("STM32MP151*")||cpuis("STM32MP153*")||cpuis("STM32MP157*")) tree "I2C1" base ad:0x40012000 group.long 0x0++0x1B line.long 0x0 "I2C_CR1,Access: No wait states. except if a write access occurs while a write access to this register is ongoing. In this case. wait states are inserted in the second write access until the previous one is completed. The latency of the second write.." bitfld.long 0x0 23. "PECEN,PECEN" "0,1" bitfld.long 0x0 22. "ALERTEN,ALERTEN" "0,1" bitfld.long 0x0 21. "SMBDEN,SMBDEN" "0,1" bitfld.long 0x0 20. "SMBHEN,SMBHEN" "0,1" bitfld.long 0x0 19. "GCEN,GCEN" "0,1" bitfld.long 0x0 18. "WUPEN,WUPEN" "0,1" bitfld.long 0x0 17. "NOSTRETCH,NOSTRETCH" "0,1" bitfld.long 0x0 16. "SBC,SBC" "0,1" newline bitfld.long 0x0 15. "RXDMAEN,RXDMAEN" "0,1" bitfld.long 0x0 14. "TXDMAEN,TXDMAEN" "0,1" bitfld.long 0x0 12. "ANFOFF,ANFOFF" "0,1" hexmask.long.byte 0x0 8.--11. 1. "DNF,DNF" bitfld.long 0x0 7. "ERRIE,ERRIE" "0,1" bitfld.long 0x0 6. "TCIE,TCIE" "0,1" bitfld.long 0x0 5. "STOPIE,STOPIE" "0,1" bitfld.long 0x0 4. "NACKIE,NACKIE" "0,1" newline bitfld.long 0x0 3. "ADDRIE,ADDRIE" "0,1" bitfld.long 0x0 2. "RXIE,RXIE" "0,1" bitfld.long 0x0 1. "TXIE,TXIE" "0,1" bitfld.long 0x0 0. "PE,PE" "0,1" line.long 0x4 "I2C_CR2,Access: No wait states. except if a write access occurs while a write access to this register is ongoing. In this case. wait states are inserted in the second write access until the previous one is completed. The latency of the second write.." bitfld.long 0x4 26. "PECBYTE,PECBYTE" "0,1" bitfld.long 0x4 25. "AUTOEND,AUTOEND" "0,1" bitfld.long 0x4 24. "RELOAD,RELOAD" "0,1" hexmask.long.byte 0x4 16.--23. 1. "NBYTES,NBYTES" bitfld.long 0x4 15. "NACK,NACK" "0,1" bitfld.long 0x4 14. "STOP,STOP" "0,1" bitfld.long 0x4 13. "START,START" "0,1" bitfld.long 0x4 12. "HEAD10R,HEAD10R" "0,1" newline bitfld.long 0x4 11. "ADD10,ADD10" "0,1" bitfld.long 0x4 10. "RD_WRN,RD_WRN" "0,1" hexmask.long.word 0x4 0.--9. 1. "SADD,SADD" line.long 0x8 "I2C_OAR1,Access: No wait states. except if a write access occurs while a write access to this register is ongoing. In this case. wait states are inserted in the second write access until the previous one is completed. The latency of the second write.." bitfld.long 0x8 15. "OA1EN,OA1EN" "0,1" bitfld.long 0x8 10. "OA1MODE,OA1MODE" "0,1" hexmask.long.word 0x8 0.--9. 1. "OA1,OA1" line.long 0xC "I2C_OAR2,Access: No wait states. except if a write access occurs while a write access to this register is ongoing. In this case. wait states are inserted in the second write access until the previous one is completed. The latency of the second write.." bitfld.long 0xC 15. "OA2EN,OA2EN" "0,1" bitfld.long 0xC 8.--10. "OA2MSK,OA2MSK" "0,1,2,3,4,5,6,7" hexmask.long.byte 0xC 1.--7. 1. "OA2,OA2" line.long 0x10 "I2C_TIMINGR,Access: No wait states" hexmask.long.byte 0x10 28.--31. 1. "PRESC,PRESC" hexmask.long.byte 0x10 20.--23. 1. "SCLDEL,SCLDEL" hexmask.long.byte 0x10 16.--19. 1. "SDADEL,SDADEL" hexmask.long.byte 0x10 8.--15. 1. "SCLH,SCLH" hexmask.long.byte 0x10 0.--7. 1. "SCLL,SCLL" line.long 0x14 "I2C_TIMEOUTR,Access: No wait states. except if a write access occurs while a write access to this register is ongoing. In this case. wait states are inserted in the second write access until the previous one is completed. The latency of the second write.." bitfld.long 0x14 31. "TEXTEN,TEXTEN" "0,1" hexmask.long.word 0x14 16.--27. 1. "TIMEOUTB,TIMEOUTB" bitfld.long 0x14 15. "TIMOUTEN,TIMOUTEN" "0,1" bitfld.long 0x14 12. "TIDLE,TIDLE" "0,1" hexmask.long.word 0x14 0.--11. 1. "TIMEOUTA,TIMEOUTA" line.long 0x18 "I2C_ISR,Access: No wait states" hexmask.long.byte 0x18 17.--23. 1. "ADDCODE,ADDCODE" rbitfld.long 0x18 16. "DIR,DIR" "0,1" rbitfld.long 0x18 15. "BUSY,BUSY" "0,1" rbitfld.long 0x18 13. "ALERT,ALERT" "0,1" rbitfld.long 0x18 12. "TIMEOUT,TIMEOUT" "0,1" rbitfld.long 0x18 11. "PECERR,PECERR" "0,1" rbitfld.long 0x18 10. "OVR,OVR" "0,1" rbitfld.long 0x18 9. "ARLO,ARLO" "0,1" newline rbitfld.long 0x18 8. "BERR,BERR" "0,1" rbitfld.long 0x18 7. "TCR,TCR" "0,1" rbitfld.long 0x18 6. "TC,TC" "0,1" rbitfld.long 0x18 5. "STOPF,STOPF" "0,1" rbitfld.long 0x18 4. "NACKF,NACKF" "0,1" rbitfld.long 0x18 3. "ADDR,ADDR" "0,1" rbitfld.long 0x18 2. "RXNE,RXNE" "0,1" bitfld.long 0x18 1. "TXIS,TXIS" "0,1" newline bitfld.long 0x18 0. "TXE,TXE" "0,1" wgroup.long 0x1C++0x3 line.long 0x0 "I2C_ICR,Access: No wait states" bitfld.long 0x0 13. "ALERTCF,ALERTCF" "0,1" bitfld.long 0x0 12. "TIMOUTCF,TIMOUTCF" "0,1" bitfld.long 0x0 11. "PECCF,PECCF" "0,1" bitfld.long 0x0 10. "OVRCF,OVRCF" "0,1" bitfld.long 0x0 9. "ARLOCF,ARLOCF" "0,1" bitfld.long 0x0 8. "BERRCF,BERRCF" "0,1" bitfld.long 0x0 5. "STOPCF,STOPCF" "0,1" bitfld.long 0x0 4. "NACKCF,NACKCF" "0,1" newline bitfld.long 0x0 3. "ADDRCF,ADDRCF" "0,1" rgroup.long 0x20++0x7 line.long 0x0 "I2C_PECR,Access: No wait states" hexmask.long.byte 0x0 0.--7. 1. "PEC,PEC" line.long 0x4 "I2C_RXDR,Access: No wait states" hexmask.long.byte 0x4 0.--7. 1. "RXDATA,RXDATA" group.long 0x28++0x3 line.long 0x0 "I2C_TXDR,Access: No wait states" hexmask.long.byte 0x0 0.--7. 1. "TXDATA,TXDATA" rgroup.long 0x3F0++0xF line.long 0x0 "I2C_HWCFGR,I2C hardware configuration register" hexmask.long.byte 0x0 8.--11. 1. "WKP,WKP" hexmask.long.byte 0x0 4.--7. 1. "ASYN,ASYN" hexmask.long.byte 0x0 0.--3. 1. "SMBUS,SMBUS" line.long 0x4 "I2C_VERR,I2C version register" hexmask.long.byte 0x4 4.--7. 1. "MAJREV,MAJREV" hexmask.long.byte 0x4 0.--3. 1. "MINREV,MINREV" line.long 0x8 "I2C_IPIDR,I2C identification register" hexmask.long 0x8 0.--31. 1. "ID,ID" line.long 0xC "I2C_SIDR,I2C size identification register" hexmask.long 0xC 0.--31. 1. "SID,SID" tree.end endif sif (cpuis("STM32MP151*")||cpuis("STM32MP153*")||cpuis("STM32MP157*")) tree "I2C2" base ad:0x40013000 group.long 0x0++0x1B line.long 0x0 "I2C_CR1,Access: No wait states. except if a write access occurs while a write access to this register is ongoing. In this case. wait states are inserted in the second write access until the previous one is completed. The latency of the second write.." bitfld.long 0x0 23. "PECEN,PECEN" "0,1" bitfld.long 0x0 22. "ALERTEN,ALERTEN" "0,1" bitfld.long 0x0 21. "SMBDEN,SMBDEN" "0,1" bitfld.long 0x0 20. "SMBHEN,SMBHEN" "0,1" bitfld.long 0x0 19. "GCEN,GCEN" "0,1" bitfld.long 0x0 18. "WUPEN,WUPEN" "0,1" bitfld.long 0x0 17. "NOSTRETCH,NOSTRETCH" "0,1" bitfld.long 0x0 16. "SBC,SBC" "0,1" newline bitfld.long 0x0 15. "RXDMAEN,RXDMAEN" "0,1" bitfld.long 0x0 14. "TXDMAEN,TXDMAEN" "0,1" bitfld.long 0x0 12. "ANFOFF,ANFOFF" "0,1" hexmask.long.byte 0x0 8.--11. 1. "DNF,DNF" bitfld.long 0x0 7. "ERRIE,ERRIE" "0,1" bitfld.long 0x0 6. "TCIE,TCIE" "0,1" bitfld.long 0x0 5. "STOPIE,STOPIE" "0,1" bitfld.long 0x0 4. "NACKIE,NACKIE" "0,1" newline bitfld.long 0x0 3. "ADDRIE,ADDRIE" "0,1" bitfld.long 0x0 2. "RXIE,RXIE" "0,1" bitfld.long 0x0 1. "TXIE,TXIE" "0,1" bitfld.long 0x0 0. "PE,PE" "0,1" line.long 0x4 "I2C_CR2,Access: No wait states. except if a write access occurs while a write access to this register is ongoing. In this case. wait states are inserted in the second write access until the previous one is completed. The latency of the second write.." bitfld.long 0x4 26. "PECBYTE,PECBYTE" "0,1" bitfld.long 0x4 25. "AUTOEND,AUTOEND" "0,1" bitfld.long 0x4 24. "RELOAD,RELOAD" "0,1" hexmask.long.byte 0x4 16.--23. 1. "NBYTES,NBYTES" bitfld.long 0x4 15. "NACK,NACK" "0,1" bitfld.long 0x4 14. "STOP,STOP" "0,1" bitfld.long 0x4 13. "START,START" "0,1" bitfld.long 0x4 12. "HEAD10R,HEAD10R" "0,1" newline bitfld.long 0x4 11. "ADD10,ADD10" "0,1" bitfld.long 0x4 10. "RD_WRN,RD_WRN" "0,1" hexmask.long.word 0x4 0.--9. 1. "SADD,SADD" line.long 0x8 "I2C_OAR1,Access: No wait states. except if a write access occurs while a write access to this register is ongoing. In this case. wait states are inserted in the second write access until the previous one is completed. The latency of the second write.." bitfld.long 0x8 15. "OA1EN,OA1EN" "0,1" bitfld.long 0x8 10. "OA1MODE,OA1MODE" "0,1" hexmask.long.word 0x8 0.--9. 1. "OA1,OA1" line.long 0xC "I2C_OAR2,Access: No wait states. except if a write access occurs while a write access to this register is ongoing. In this case. wait states are inserted in the second write access until the previous one is completed. The latency of the second write.." bitfld.long 0xC 15. "OA2EN,OA2EN" "0,1" bitfld.long 0xC 8.--10. "OA2MSK,OA2MSK" "0,1,2,3,4,5,6,7" hexmask.long.byte 0xC 1.--7. 1. "OA2,OA2" line.long 0x10 "I2C_TIMINGR,Access: No wait states" hexmask.long.byte 0x10 28.--31. 1. "PRESC,PRESC" hexmask.long.byte 0x10 20.--23. 1. "SCLDEL,SCLDEL" hexmask.long.byte 0x10 16.--19. 1. "SDADEL,SDADEL" hexmask.long.byte 0x10 8.--15. 1. "SCLH,SCLH" hexmask.long.byte 0x10 0.--7. 1. "SCLL,SCLL" line.long 0x14 "I2C_TIMEOUTR,Access: No wait states. except if a write access occurs while a write access to this register is ongoing. In this case. wait states are inserted in the second write access until the previous one is completed. The latency of the second write.." bitfld.long 0x14 31. "TEXTEN,TEXTEN" "0,1" hexmask.long.word 0x14 16.--27. 1. "TIMEOUTB,TIMEOUTB" bitfld.long 0x14 15. "TIMOUTEN,TIMOUTEN" "0,1" bitfld.long 0x14 12. "TIDLE,TIDLE" "0,1" hexmask.long.word 0x14 0.--11. 1. "TIMEOUTA,TIMEOUTA" line.long 0x18 "I2C_ISR,Access: No wait states" hexmask.long.byte 0x18 17.--23. 1. "ADDCODE,ADDCODE" rbitfld.long 0x18 16. "DIR,DIR" "0,1" rbitfld.long 0x18 15. "BUSY,BUSY" "0,1" rbitfld.long 0x18 13. "ALERT,ALERT" "0,1" rbitfld.long 0x18 12. "TIMEOUT,TIMEOUT" "0,1" rbitfld.long 0x18 11. "PECERR,PECERR" "0,1" rbitfld.long 0x18 10. "OVR,OVR" "0,1" rbitfld.long 0x18 9. "ARLO,ARLO" "0,1" newline rbitfld.long 0x18 8. "BERR,BERR" "0,1" rbitfld.long 0x18 7. "TCR,TCR" "0,1" rbitfld.long 0x18 6. "TC,TC" "0,1" rbitfld.long 0x18 5. "STOPF,STOPF" "0,1" rbitfld.long 0x18 4. "NACKF,NACKF" "0,1" rbitfld.long 0x18 3. "ADDR,ADDR" "0,1" rbitfld.long 0x18 2. "RXNE,RXNE" "0,1" bitfld.long 0x18 1. "TXIS,TXIS" "0,1" newline bitfld.long 0x18 0. "TXE,TXE" "0,1" wgroup.long 0x1C++0x3 line.long 0x0 "I2C_ICR,Access: No wait states" bitfld.long 0x0 13. "ALERTCF,ALERTCF" "0,1" bitfld.long 0x0 12. "TIMOUTCF,TIMOUTCF" "0,1" bitfld.long 0x0 11. "PECCF,PECCF" "0,1" bitfld.long 0x0 10. "OVRCF,OVRCF" "0,1" bitfld.long 0x0 9. "ARLOCF,ARLOCF" "0,1" bitfld.long 0x0 8. "BERRCF,BERRCF" "0,1" bitfld.long 0x0 5. "STOPCF,STOPCF" "0,1" bitfld.long 0x0 4. "NACKCF,NACKCF" "0,1" newline bitfld.long 0x0 3. "ADDRCF,ADDRCF" "0,1" rgroup.long 0x20++0x7 line.long 0x0 "I2C_PECR,Access: No wait states" hexmask.long.byte 0x0 0.--7. 1. "PEC,PEC" line.long 0x4 "I2C_RXDR,Access: No wait states" hexmask.long.byte 0x4 0.--7. 1. "RXDATA,RXDATA" group.long 0x28++0x3 line.long 0x0 "I2C_TXDR,Access: No wait states" hexmask.long.byte 0x0 0.--7. 1. "TXDATA,TXDATA" rgroup.long 0x3F0++0xF line.long 0x0 "I2C_HWCFGR,I2C hardware configuration register" hexmask.long.byte 0x0 8.--11. 1. "WKP,WKP" hexmask.long.byte 0x0 4.--7. 1. "ASYN,ASYN" hexmask.long.byte 0x0 0.--3. 1. "SMBUS,SMBUS" line.long 0x4 "I2C_VERR,I2C version register" hexmask.long.byte 0x4 4.--7. 1. "MAJREV,MAJREV" hexmask.long.byte 0x4 0.--3. 1. "MINREV,MINREV" line.long 0x8 "I2C_IPIDR,I2C identification register" hexmask.long 0x8 0.--31. 1. "ID,ID" line.long 0xC "I2C_SIDR,I2C size identification register" hexmask.long 0xC 0.--31. 1. "SID,SID" tree.end endif sif (cpuis("STM32MP151*")||cpuis("STM32MP153*")||cpuis("STM32MP157*")) tree "I2C3" base ad:0x40014000 group.long 0x0++0x1B line.long 0x0 "I2C_CR1,Access: No wait states. except if a write access occurs while a write access to this register is ongoing. In this case. wait states are inserted in the second write access until the previous one is completed. The latency of the second write.." bitfld.long 0x0 23. "PECEN,PECEN" "0,1" bitfld.long 0x0 22. "ALERTEN,ALERTEN" "0,1" bitfld.long 0x0 21. "SMBDEN,SMBDEN" "0,1" bitfld.long 0x0 20. "SMBHEN,SMBHEN" "0,1" bitfld.long 0x0 19. "GCEN,GCEN" "0,1" bitfld.long 0x0 18. "WUPEN,WUPEN" "0,1" bitfld.long 0x0 17. "NOSTRETCH,NOSTRETCH" "0,1" bitfld.long 0x0 16. "SBC,SBC" "0,1" newline bitfld.long 0x0 15. "RXDMAEN,RXDMAEN" "0,1" bitfld.long 0x0 14. "TXDMAEN,TXDMAEN" "0,1" bitfld.long 0x0 12. "ANFOFF,ANFOFF" "0,1" hexmask.long.byte 0x0 8.--11. 1. "DNF,DNF" bitfld.long 0x0 7. "ERRIE,ERRIE" "0,1" bitfld.long 0x0 6. "TCIE,TCIE" "0,1" bitfld.long 0x0 5. "STOPIE,STOPIE" "0,1" bitfld.long 0x0 4. "NACKIE,NACKIE" "0,1" newline bitfld.long 0x0 3. "ADDRIE,ADDRIE" "0,1" bitfld.long 0x0 2. "RXIE,RXIE" "0,1" bitfld.long 0x0 1. "TXIE,TXIE" "0,1" bitfld.long 0x0 0. "PE,PE" "0,1" line.long 0x4 "I2C_CR2,Access: No wait states. except if a write access occurs while a write access to this register is ongoing. In this case. wait states are inserted in the second write access until the previous one is completed. The latency of the second write.." bitfld.long 0x4 26. "PECBYTE,PECBYTE" "0,1" bitfld.long 0x4 25. "AUTOEND,AUTOEND" "0,1" bitfld.long 0x4 24. "RELOAD,RELOAD" "0,1" hexmask.long.byte 0x4 16.--23. 1. "NBYTES,NBYTES" bitfld.long 0x4 15. "NACK,NACK" "0,1" bitfld.long 0x4 14. "STOP,STOP" "0,1" bitfld.long 0x4 13. "START,START" "0,1" bitfld.long 0x4 12. "HEAD10R,HEAD10R" "0,1" newline bitfld.long 0x4 11. "ADD10,ADD10" "0,1" bitfld.long 0x4 10. "RD_WRN,RD_WRN" "0,1" hexmask.long.word 0x4 0.--9. 1. "SADD,SADD" line.long 0x8 "I2C_OAR1,Access: No wait states. except if a write access occurs while a write access to this register is ongoing. In this case. wait states are inserted in the second write access until the previous one is completed. The latency of the second write.." bitfld.long 0x8 15. "OA1EN,OA1EN" "0,1" bitfld.long 0x8 10. "OA1MODE,OA1MODE" "0,1" hexmask.long.word 0x8 0.--9. 1. "OA1,OA1" line.long 0xC "I2C_OAR2,Access: No wait states. except if a write access occurs while a write access to this register is ongoing. In this case. wait states are inserted in the second write access until the previous one is completed. The latency of the second write.." bitfld.long 0xC 15. "OA2EN,OA2EN" "0,1" bitfld.long 0xC 8.--10. "OA2MSK,OA2MSK" "0,1,2,3,4,5,6,7" hexmask.long.byte 0xC 1.--7. 1. "OA2,OA2" line.long 0x10 "I2C_TIMINGR,Access: No wait states" hexmask.long.byte 0x10 28.--31. 1. "PRESC,PRESC" hexmask.long.byte 0x10 20.--23. 1. "SCLDEL,SCLDEL" hexmask.long.byte 0x10 16.--19. 1. "SDADEL,SDADEL" hexmask.long.byte 0x10 8.--15. 1. "SCLH,SCLH" hexmask.long.byte 0x10 0.--7. 1. "SCLL,SCLL" line.long 0x14 "I2C_TIMEOUTR,Access: No wait states. except if a write access occurs while a write access to this register is ongoing. In this case. wait states are inserted in the second write access until the previous one is completed. The latency of the second write.." bitfld.long 0x14 31. "TEXTEN,TEXTEN" "0,1" hexmask.long.word 0x14 16.--27. 1. "TIMEOUTB,TIMEOUTB" bitfld.long 0x14 15. "TIMOUTEN,TIMOUTEN" "0,1" bitfld.long 0x14 12. "TIDLE,TIDLE" "0,1" hexmask.long.word 0x14 0.--11. 1. "TIMEOUTA,TIMEOUTA" line.long 0x18 "I2C_ISR,Access: No wait states" hexmask.long.byte 0x18 17.--23. 1. "ADDCODE,ADDCODE" rbitfld.long 0x18 16. "DIR,DIR" "0,1" rbitfld.long 0x18 15. "BUSY,BUSY" "0,1" rbitfld.long 0x18 13. "ALERT,ALERT" "0,1" rbitfld.long 0x18 12. "TIMEOUT,TIMEOUT" "0,1" rbitfld.long 0x18 11. "PECERR,PECERR" "0,1" rbitfld.long 0x18 10. "OVR,OVR" "0,1" rbitfld.long 0x18 9. "ARLO,ARLO" "0,1" newline rbitfld.long 0x18 8. "BERR,BERR" "0,1" rbitfld.long 0x18 7. "TCR,TCR" "0,1" rbitfld.long 0x18 6. "TC,TC" "0,1" rbitfld.long 0x18 5. "STOPF,STOPF" "0,1" rbitfld.long 0x18 4. "NACKF,NACKF" "0,1" rbitfld.long 0x18 3. "ADDR,ADDR" "0,1" rbitfld.long 0x18 2. "RXNE,RXNE" "0,1" bitfld.long 0x18 1. "TXIS,TXIS" "0,1" newline bitfld.long 0x18 0. "TXE,TXE" "0,1" wgroup.long 0x1C++0x3 line.long 0x0 "I2C_ICR,Access: No wait states" bitfld.long 0x0 13. "ALERTCF,ALERTCF" "0,1" bitfld.long 0x0 12. "TIMOUTCF,TIMOUTCF" "0,1" bitfld.long 0x0 11. "PECCF,PECCF" "0,1" bitfld.long 0x0 10. "OVRCF,OVRCF" "0,1" bitfld.long 0x0 9. "ARLOCF,ARLOCF" "0,1" bitfld.long 0x0 8. "BERRCF,BERRCF" "0,1" bitfld.long 0x0 5. "STOPCF,STOPCF" "0,1" bitfld.long 0x0 4. "NACKCF,NACKCF" "0,1" newline bitfld.long 0x0 3. "ADDRCF,ADDRCF" "0,1" rgroup.long 0x20++0x7 line.long 0x0 "I2C_PECR,Access: No wait states" hexmask.long.byte 0x0 0.--7. 1. "PEC,PEC" line.long 0x4 "I2C_RXDR,Access: No wait states" hexmask.long.byte 0x4 0.--7. 1. "RXDATA,RXDATA" group.long 0x28++0x3 line.long 0x0 "I2C_TXDR,Access: No wait states" hexmask.long.byte 0x0 0.--7. 1. "TXDATA,TXDATA" rgroup.long 0x3F0++0xF line.long 0x0 "I2C_HWCFGR,I2C hardware configuration register" hexmask.long.byte 0x0 8.--11. 1. "WKP,WKP" hexmask.long.byte 0x0 4.--7. 1. "ASYN,ASYN" hexmask.long.byte 0x0 0.--3. 1. "SMBUS,SMBUS" line.long 0x4 "I2C_VERR,I2C version register" hexmask.long.byte 0x4 4.--7. 1. "MAJREV,MAJREV" hexmask.long.byte 0x4 0.--3. 1. "MINREV,MINREV" line.long 0x8 "I2C_IPIDR,I2C identification register" hexmask.long 0x8 0.--31. 1. "ID,ID" line.long 0xC "I2C_SIDR,I2C size identification register" hexmask.long 0xC 0.--31. 1. "SID,SID" tree.end endif sif (cpuis("STM32MP151*")||cpuis("STM32MP153*")||cpuis("STM32MP157*")) tree "I2C4" base ad:0x5C002000 group.long 0x0++0x1B line.long 0x0 "I2C_CR1,Access: No wait states. except if a write access occurs while a write access to this register is ongoing. In this case. wait states are inserted in the second write access until the previous one is completed. The latency of the second write.." bitfld.long 0x0 23. "PECEN,PECEN" "0,1" bitfld.long 0x0 22. "ALERTEN,ALERTEN" "0,1" bitfld.long 0x0 21. "SMBDEN,SMBDEN" "0,1" bitfld.long 0x0 20. "SMBHEN,SMBHEN" "0,1" bitfld.long 0x0 19. "GCEN,GCEN" "0,1" bitfld.long 0x0 18. "WUPEN,WUPEN" "0,1" bitfld.long 0x0 17. "NOSTRETCH,NOSTRETCH" "0,1" bitfld.long 0x0 16. "SBC,SBC" "0,1" newline bitfld.long 0x0 15. "RXDMAEN,RXDMAEN" "0,1" bitfld.long 0x0 14. "TXDMAEN,TXDMAEN" "0,1" bitfld.long 0x0 12. "ANFOFF,ANFOFF" "0,1" hexmask.long.byte 0x0 8.--11. 1. "DNF,DNF" bitfld.long 0x0 7. "ERRIE,ERRIE" "0,1" bitfld.long 0x0 6. "TCIE,TCIE" "0,1" bitfld.long 0x0 5. "STOPIE,STOPIE" "0,1" bitfld.long 0x0 4. "NACKIE,NACKIE" "0,1" newline bitfld.long 0x0 3. "ADDRIE,ADDRIE" "0,1" bitfld.long 0x0 2. "RXIE,RXIE" "0,1" bitfld.long 0x0 1. "TXIE,TXIE" "0,1" bitfld.long 0x0 0. "PE,PE" "0,1" line.long 0x4 "I2C_CR2,Access: No wait states. except if a write access occurs while a write access to this register is ongoing. In this case. wait states are inserted in the second write access until the previous one is completed. The latency of the second write.." bitfld.long 0x4 26. "PECBYTE,PECBYTE" "0,1" bitfld.long 0x4 25. "AUTOEND,AUTOEND" "0,1" bitfld.long 0x4 24. "RELOAD,RELOAD" "0,1" hexmask.long.byte 0x4 16.--23. 1. "NBYTES,NBYTES" bitfld.long 0x4 15. "NACK,NACK" "0,1" bitfld.long 0x4 14. "STOP,STOP" "0,1" bitfld.long 0x4 13. "START,START" "0,1" bitfld.long 0x4 12. "HEAD10R,HEAD10R" "0,1" newline bitfld.long 0x4 11. "ADD10,ADD10" "0,1" bitfld.long 0x4 10. "RD_WRN,RD_WRN" "0,1" hexmask.long.word 0x4 0.--9. 1. "SADD,SADD" line.long 0x8 "I2C_OAR1,Access: No wait states. except if a write access occurs while a write access to this register is ongoing. In this case. wait states are inserted in the second write access until the previous one is completed. The latency of the second write.." bitfld.long 0x8 15. "OA1EN,OA1EN" "0,1" bitfld.long 0x8 10. "OA1MODE,OA1MODE" "0,1" hexmask.long.word 0x8 0.--9. 1. "OA1,OA1" line.long 0xC "I2C_OAR2,Access: No wait states. except if a write access occurs while a write access to this register is ongoing. In this case. wait states are inserted in the second write access until the previous one is completed. The latency of the second write.." bitfld.long 0xC 15. "OA2EN,OA2EN" "0,1" bitfld.long 0xC 8.--10. "OA2MSK,OA2MSK" "0,1,2,3,4,5,6,7" hexmask.long.byte 0xC 1.--7. 1. "OA2,OA2" line.long 0x10 "I2C_TIMINGR,Access: No wait states" hexmask.long.byte 0x10 28.--31. 1. "PRESC,PRESC" hexmask.long.byte 0x10 20.--23. 1. "SCLDEL,SCLDEL" hexmask.long.byte 0x10 16.--19. 1. "SDADEL,SDADEL" hexmask.long.byte 0x10 8.--15. 1. "SCLH,SCLH" hexmask.long.byte 0x10 0.--7. 1. "SCLL,SCLL" line.long 0x14 "I2C_TIMEOUTR,Access: No wait states. except if a write access occurs while a write access to this register is ongoing. In this case. wait states are inserted in the second write access until the previous one is completed. The latency of the second write.." bitfld.long 0x14 31. "TEXTEN,TEXTEN" "0,1" hexmask.long.word 0x14 16.--27. 1. "TIMEOUTB,TIMEOUTB" bitfld.long 0x14 15. "TIMOUTEN,TIMOUTEN" "0,1" bitfld.long 0x14 12. "TIDLE,TIDLE" "0,1" hexmask.long.word 0x14 0.--11. 1. "TIMEOUTA,TIMEOUTA" line.long 0x18 "I2C_ISR,Access: No wait states" hexmask.long.byte 0x18 17.--23. 1. "ADDCODE,ADDCODE" rbitfld.long 0x18 16. "DIR,DIR" "0,1" rbitfld.long 0x18 15. "BUSY,BUSY" "0,1" rbitfld.long 0x18 13. "ALERT,ALERT" "0,1" rbitfld.long 0x18 12. "TIMEOUT,TIMEOUT" "0,1" rbitfld.long 0x18 11. "PECERR,PECERR" "0,1" rbitfld.long 0x18 10. "OVR,OVR" "0,1" rbitfld.long 0x18 9. "ARLO,ARLO" "0,1" newline rbitfld.long 0x18 8. "BERR,BERR" "0,1" rbitfld.long 0x18 7. "TCR,TCR" "0,1" rbitfld.long 0x18 6. "TC,TC" "0,1" rbitfld.long 0x18 5. "STOPF,STOPF" "0,1" rbitfld.long 0x18 4. "NACKF,NACKF" "0,1" rbitfld.long 0x18 3. "ADDR,ADDR" "0,1" rbitfld.long 0x18 2. "RXNE,RXNE" "0,1" bitfld.long 0x18 1. "TXIS,TXIS" "0,1" newline bitfld.long 0x18 0. "TXE,TXE" "0,1" wgroup.long 0x1C++0x3 line.long 0x0 "I2C_ICR,Access: No wait states" bitfld.long 0x0 13. "ALERTCF,ALERTCF" "0,1" bitfld.long 0x0 12. "TIMOUTCF,TIMOUTCF" "0,1" bitfld.long 0x0 11. "PECCF,PECCF" "0,1" bitfld.long 0x0 10. "OVRCF,OVRCF" "0,1" bitfld.long 0x0 9. "ARLOCF,ARLOCF" "0,1" bitfld.long 0x0 8. "BERRCF,BERRCF" "0,1" bitfld.long 0x0 5. "STOPCF,STOPCF" "0,1" bitfld.long 0x0 4. "NACKCF,NACKCF" "0,1" newline bitfld.long 0x0 3. "ADDRCF,ADDRCF" "0,1" rgroup.long 0x20++0x7 line.long 0x0 "I2C_PECR,Access: No wait states" hexmask.long.byte 0x0 0.--7. 1. "PEC,PEC" line.long 0x4 "I2C_RXDR,Access: No wait states" hexmask.long.byte 0x4 0.--7. 1. "RXDATA,RXDATA" group.long 0x28++0x3 line.long 0x0 "I2C_TXDR,Access: No wait states" hexmask.long.byte 0x0 0.--7. 1. "TXDATA,TXDATA" rgroup.long 0x3F0++0xF line.long 0x0 "I2C_HWCFGR,I2C hardware configuration register" hexmask.long.byte 0x0 8.--11. 1. "WKP,WKP" hexmask.long.byte 0x0 4.--7. 1. "ASYN,ASYN" hexmask.long.byte 0x0 0.--3. 1. "SMBUS,SMBUS" line.long 0x4 "I2C_VERR,I2C version register" hexmask.long.byte 0x4 4.--7. 1. "MAJREV,MAJREV" hexmask.long.byte 0x4 0.--3. 1. "MINREV,MINREV" line.long 0x8 "I2C_IPIDR,I2C identification register" hexmask.long 0x8 0.--31. 1. "ID,ID" line.long 0xC "I2C_SIDR,I2C size identification register" hexmask.long 0xC 0.--31. 1. "SID,SID" tree.end endif sif (cpuis("STM32MP151*")||cpuis("STM32MP153*")||cpuis("STM32MP157*")) tree "I2C5" base ad:0x40015000 group.long 0x0++0x1B line.long 0x0 "I2C_CR1,Access: No wait states. except if a write access occurs while a write access to this register is ongoing. In this case. wait states are inserted in the second write access until the previous one is completed. The latency of the second write.." bitfld.long 0x0 23. "PECEN,PECEN" "0,1" bitfld.long 0x0 22. "ALERTEN,ALERTEN" "0,1" bitfld.long 0x0 21. "SMBDEN,SMBDEN" "0,1" bitfld.long 0x0 20. "SMBHEN,SMBHEN" "0,1" bitfld.long 0x0 19. "GCEN,GCEN" "0,1" bitfld.long 0x0 18. "WUPEN,WUPEN" "0,1" bitfld.long 0x0 17. "NOSTRETCH,NOSTRETCH" "0,1" bitfld.long 0x0 16. "SBC,SBC" "0,1" newline bitfld.long 0x0 15. "RXDMAEN,RXDMAEN" "0,1" bitfld.long 0x0 14. "TXDMAEN,TXDMAEN" "0,1" bitfld.long 0x0 12. "ANFOFF,ANFOFF" "0,1" hexmask.long.byte 0x0 8.--11. 1. "DNF,DNF" bitfld.long 0x0 7. "ERRIE,ERRIE" "0,1" bitfld.long 0x0 6. "TCIE,TCIE" "0,1" bitfld.long 0x0 5. "STOPIE,STOPIE" "0,1" bitfld.long 0x0 4. "NACKIE,NACKIE" "0,1" newline bitfld.long 0x0 3. "ADDRIE,ADDRIE" "0,1" bitfld.long 0x0 2. "RXIE,RXIE" "0,1" bitfld.long 0x0 1. "TXIE,TXIE" "0,1" bitfld.long 0x0 0. "PE,PE" "0,1" line.long 0x4 "I2C_CR2,Access: No wait states. except if a write access occurs while a write access to this register is ongoing. In this case. wait states are inserted in the second write access until the previous one is completed. The latency of the second write.." bitfld.long 0x4 26. "PECBYTE,PECBYTE" "0,1" bitfld.long 0x4 25. "AUTOEND,AUTOEND" "0,1" bitfld.long 0x4 24. "RELOAD,RELOAD" "0,1" hexmask.long.byte 0x4 16.--23. 1. "NBYTES,NBYTES" bitfld.long 0x4 15. "NACK,NACK" "0,1" bitfld.long 0x4 14. "STOP,STOP" "0,1" bitfld.long 0x4 13. "START,START" "0,1" bitfld.long 0x4 12. "HEAD10R,HEAD10R" "0,1" newline bitfld.long 0x4 11. "ADD10,ADD10" "0,1" bitfld.long 0x4 10. "RD_WRN,RD_WRN" "0,1" hexmask.long.word 0x4 0.--9. 1. "SADD,SADD" line.long 0x8 "I2C_OAR1,Access: No wait states. except if a write access occurs while a write access to this register is ongoing. In this case. wait states are inserted in the second write access until the previous one is completed. The latency of the second write.." bitfld.long 0x8 15. "OA1EN,OA1EN" "0,1" bitfld.long 0x8 10. "OA1MODE,OA1MODE" "0,1" hexmask.long.word 0x8 0.--9. 1. "OA1,OA1" line.long 0xC "I2C_OAR2,Access: No wait states. except if a write access occurs while a write access to this register is ongoing. In this case. wait states are inserted in the second write access until the previous one is completed. The latency of the second write.." bitfld.long 0xC 15. "OA2EN,OA2EN" "0,1" bitfld.long 0xC 8.--10. "OA2MSK,OA2MSK" "0,1,2,3,4,5,6,7" hexmask.long.byte 0xC 1.--7. 1. "OA2,OA2" line.long 0x10 "I2C_TIMINGR,Access: No wait states" hexmask.long.byte 0x10 28.--31. 1. "PRESC,PRESC" hexmask.long.byte 0x10 20.--23. 1. "SCLDEL,SCLDEL" hexmask.long.byte 0x10 16.--19. 1. "SDADEL,SDADEL" hexmask.long.byte 0x10 8.--15. 1. "SCLH,SCLH" hexmask.long.byte 0x10 0.--7. 1. "SCLL,SCLL" line.long 0x14 "I2C_TIMEOUTR,Access: No wait states. except if a write access occurs while a write access to this register is ongoing. In this case. wait states are inserted in the second write access until the previous one is completed. The latency of the second write.." bitfld.long 0x14 31. "TEXTEN,TEXTEN" "0,1" hexmask.long.word 0x14 16.--27. 1. "TIMEOUTB,TIMEOUTB" bitfld.long 0x14 15. "TIMOUTEN,TIMOUTEN" "0,1" bitfld.long 0x14 12. "TIDLE,TIDLE" "0,1" hexmask.long.word 0x14 0.--11. 1. "TIMEOUTA,TIMEOUTA" line.long 0x18 "I2C_ISR,Access: No wait states" hexmask.long.byte 0x18 17.--23. 1. "ADDCODE,ADDCODE" rbitfld.long 0x18 16. "DIR,DIR" "0,1" rbitfld.long 0x18 15. "BUSY,BUSY" "0,1" rbitfld.long 0x18 13. "ALERT,ALERT" "0,1" rbitfld.long 0x18 12. "TIMEOUT,TIMEOUT" "0,1" rbitfld.long 0x18 11. "PECERR,PECERR" "0,1" rbitfld.long 0x18 10. "OVR,OVR" "0,1" rbitfld.long 0x18 9. "ARLO,ARLO" "0,1" newline rbitfld.long 0x18 8. "BERR,BERR" "0,1" rbitfld.long 0x18 7. "TCR,TCR" "0,1" rbitfld.long 0x18 6. "TC,TC" "0,1" rbitfld.long 0x18 5. "STOPF,STOPF" "0,1" rbitfld.long 0x18 4. "NACKF,NACKF" "0,1" rbitfld.long 0x18 3. "ADDR,ADDR" "0,1" rbitfld.long 0x18 2. "RXNE,RXNE" "0,1" bitfld.long 0x18 1. "TXIS,TXIS" "0,1" newline bitfld.long 0x18 0. "TXE,TXE" "0,1" wgroup.long 0x1C++0x3 line.long 0x0 "I2C_ICR,Access: No wait states" bitfld.long 0x0 13. "ALERTCF,ALERTCF" "0,1" bitfld.long 0x0 12. "TIMOUTCF,TIMOUTCF" "0,1" bitfld.long 0x0 11. "PECCF,PECCF" "0,1" bitfld.long 0x0 10. "OVRCF,OVRCF" "0,1" bitfld.long 0x0 9. "ARLOCF,ARLOCF" "0,1" bitfld.long 0x0 8. "BERRCF,BERRCF" "0,1" bitfld.long 0x0 5. "STOPCF,STOPCF" "0,1" bitfld.long 0x0 4. "NACKCF,NACKCF" "0,1" newline bitfld.long 0x0 3. "ADDRCF,ADDRCF" "0,1" rgroup.long 0x20++0x7 line.long 0x0 "I2C_PECR,Access: No wait states" hexmask.long.byte 0x0 0.--7. 1. "PEC,PEC" line.long 0x4 "I2C_RXDR,Access: No wait states" hexmask.long.byte 0x4 0.--7. 1. "RXDATA,RXDATA" group.long 0x28++0x3 line.long 0x0 "I2C_TXDR,Access: No wait states" hexmask.long.byte 0x0 0.--7. 1. "TXDATA,TXDATA" rgroup.long 0x3F0++0xF line.long 0x0 "I2C_HWCFGR,I2C hardware configuration register" hexmask.long.byte 0x0 8.--11. 1. "WKP,WKP" hexmask.long.byte 0x0 4.--7. 1. "ASYN,ASYN" hexmask.long.byte 0x0 0.--3. 1. "SMBUS,SMBUS" line.long 0x4 "I2C_VERR,I2C version register" hexmask.long.byte 0x4 4.--7. 1. "MAJREV,MAJREV" hexmask.long.byte 0x4 0.--3. 1. "MINREV,MINREV" line.long 0x8 "I2C_IPIDR,I2C identification register" hexmask.long 0x8 0.--31. 1. "ID,ID" line.long 0xC "I2C_SIDR,I2C size identification register" hexmask.long 0xC 0.--31. 1. "SID,SID" tree.end endif sif (cpuis("STM32MP151*")||cpuis("STM32MP153*")||cpuis("STM32MP157*")) tree "I2C6" base ad:0x5C009000 group.long 0x0++0x1B line.long 0x0 "I2C_CR1,Access: No wait states. except if a write access occurs while a write access to this register is ongoing. In this case. wait states are inserted in the second write access until the previous one is completed. The latency of the second write.." bitfld.long 0x0 23. "PECEN,PECEN" "0,1" bitfld.long 0x0 22. "ALERTEN,ALERTEN" "0,1" bitfld.long 0x0 21. "SMBDEN,SMBDEN" "0,1" bitfld.long 0x0 20. "SMBHEN,SMBHEN" "0,1" bitfld.long 0x0 19. "GCEN,GCEN" "0,1" bitfld.long 0x0 18. "WUPEN,WUPEN" "0,1" bitfld.long 0x0 17. "NOSTRETCH,NOSTRETCH" "0,1" bitfld.long 0x0 16. "SBC,SBC" "0,1" newline bitfld.long 0x0 15. "RXDMAEN,RXDMAEN" "0,1" bitfld.long 0x0 14. "TXDMAEN,TXDMAEN" "0,1" bitfld.long 0x0 12. "ANFOFF,ANFOFF" "0,1" hexmask.long.byte 0x0 8.--11. 1. "DNF,DNF" bitfld.long 0x0 7. "ERRIE,ERRIE" "0,1" bitfld.long 0x0 6. "TCIE,TCIE" "0,1" bitfld.long 0x0 5. "STOPIE,STOPIE" "0,1" bitfld.long 0x0 4. "NACKIE,NACKIE" "0,1" newline bitfld.long 0x0 3. "ADDRIE,ADDRIE" "0,1" bitfld.long 0x0 2. "RXIE,RXIE" "0,1" bitfld.long 0x0 1. "TXIE,TXIE" "0,1" bitfld.long 0x0 0. "PE,PE" "0,1" line.long 0x4 "I2C_CR2,Access: No wait states. except if a write access occurs while a write access to this register is ongoing. In this case. wait states are inserted in the second write access until the previous one is completed. The latency of the second write.." bitfld.long 0x4 26. "PECBYTE,PECBYTE" "0,1" bitfld.long 0x4 25. "AUTOEND,AUTOEND" "0,1" bitfld.long 0x4 24. "RELOAD,RELOAD" "0,1" hexmask.long.byte 0x4 16.--23. 1. "NBYTES,NBYTES" bitfld.long 0x4 15. "NACK,NACK" "0,1" bitfld.long 0x4 14. "STOP,STOP" "0,1" bitfld.long 0x4 13. "START,START" "0,1" bitfld.long 0x4 12. "HEAD10R,HEAD10R" "0,1" newline bitfld.long 0x4 11. "ADD10,ADD10" "0,1" bitfld.long 0x4 10. "RD_WRN,RD_WRN" "0,1" hexmask.long.word 0x4 0.--9. 1. "SADD,SADD" line.long 0x8 "I2C_OAR1,Access: No wait states. except if a write access occurs while a write access to this register is ongoing. In this case. wait states are inserted in the second write access until the previous one is completed. The latency of the second write.." bitfld.long 0x8 15. "OA1EN,OA1EN" "0,1" bitfld.long 0x8 10. "OA1MODE,OA1MODE" "0,1" hexmask.long.word 0x8 0.--9. 1. "OA1,OA1" line.long 0xC "I2C_OAR2,Access: No wait states. except if a write access occurs while a write access to this register is ongoing. In this case. wait states are inserted in the second write access until the previous one is completed. The latency of the second write.." bitfld.long 0xC 15. "OA2EN,OA2EN" "0,1" bitfld.long 0xC 8.--10. "OA2MSK,OA2MSK" "0,1,2,3,4,5,6,7" hexmask.long.byte 0xC 1.--7. 1. "OA2,OA2" line.long 0x10 "I2C_TIMINGR,Access: No wait states" hexmask.long.byte 0x10 28.--31. 1. "PRESC,PRESC" hexmask.long.byte 0x10 20.--23. 1. "SCLDEL,SCLDEL" hexmask.long.byte 0x10 16.--19. 1. "SDADEL,SDADEL" hexmask.long.byte 0x10 8.--15. 1. "SCLH,SCLH" hexmask.long.byte 0x10 0.--7. 1. "SCLL,SCLL" line.long 0x14 "I2C_TIMEOUTR,Access: No wait states. except if a write access occurs while a write access to this register is ongoing. In this case. wait states are inserted in the second write access until the previous one is completed. The latency of the second write.." bitfld.long 0x14 31. "TEXTEN,TEXTEN" "0,1" hexmask.long.word 0x14 16.--27. 1. "TIMEOUTB,TIMEOUTB" bitfld.long 0x14 15. "TIMOUTEN,TIMOUTEN" "0,1" bitfld.long 0x14 12. "TIDLE,TIDLE" "0,1" hexmask.long.word 0x14 0.--11. 1. "TIMEOUTA,TIMEOUTA" line.long 0x18 "I2C_ISR,Access: No wait states" hexmask.long.byte 0x18 17.--23. 1. "ADDCODE,ADDCODE" rbitfld.long 0x18 16. "DIR,DIR" "0,1" rbitfld.long 0x18 15. "BUSY,BUSY" "0,1" rbitfld.long 0x18 13. "ALERT,ALERT" "0,1" rbitfld.long 0x18 12. "TIMEOUT,TIMEOUT" "0,1" rbitfld.long 0x18 11. "PECERR,PECERR" "0,1" rbitfld.long 0x18 10. "OVR,OVR" "0,1" rbitfld.long 0x18 9. "ARLO,ARLO" "0,1" newline rbitfld.long 0x18 8. "BERR,BERR" "0,1" rbitfld.long 0x18 7. "TCR,TCR" "0,1" rbitfld.long 0x18 6. "TC,TC" "0,1" rbitfld.long 0x18 5. "STOPF,STOPF" "0,1" rbitfld.long 0x18 4. "NACKF,NACKF" "0,1" rbitfld.long 0x18 3. "ADDR,ADDR" "0,1" rbitfld.long 0x18 2. "RXNE,RXNE" "0,1" bitfld.long 0x18 1. "TXIS,TXIS" "0,1" newline bitfld.long 0x18 0. "TXE,TXE" "0,1" wgroup.long 0x1C++0x3 line.long 0x0 "I2C_ICR,Access: No wait states" bitfld.long 0x0 13. "ALERTCF,ALERTCF" "0,1" bitfld.long 0x0 12. "TIMOUTCF,TIMOUTCF" "0,1" bitfld.long 0x0 11. "PECCF,PECCF" "0,1" bitfld.long 0x0 10. "OVRCF,OVRCF" "0,1" bitfld.long 0x0 9. "ARLOCF,ARLOCF" "0,1" bitfld.long 0x0 8. "BERRCF,BERRCF" "0,1" bitfld.long 0x0 5. "STOPCF,STOPCF" "0,1" bitfld.long 0x0 4. "NACKCF,NACKCF" "0,1" newline bitfld.long 0x0 3. "ADDRCF,ADDRCF" "0,1" rgroup.long 0x20++0x7 line.long 0x0 "I2C_PECR,Access: No wait states" hexmask.long.byte 0x0 0.--7. 1. "PEC,PEC" line.long 0x4 "I2C_RXDR,Access: No wait states" hexmask.long.byte 0x4 0.--7. 1. "RXDATA,RXDATA" group.long 0x28++0x3 line.long 0x0 "I2C_TXDR,Access: No wait states" hexmask.long.byte 0x0 0.--7. 1. "TXDATA,TXDATA" rgroup.long 0x3F0++0xF line.long 0x0 "I2C_HWCFGR,I2C hardware configuration register" hexmask.long.byte 0x0 8.--11. 1. "WKP,WKP" hexmask.long.byte 0x0 4.--7. 1. "ASYN,ASYN" hexmask.long.byte 0x0 0.--3. 1. "SMBUS,SMBUS" line.long 0x4 "I2C_VERR,I2C version register" hexmask.long.byte 0x4 4.--7. 1. "MAJREV,MAJREV" hexmask.long.byte 0x4 0.--3. 1. "MINREV,MINREV" line.long 0x8 "I2C_IPIDR,I2C identification register" hexmask.long 0x8 0.--31. 1. "ID,ID" line.long 0xC "I2C_SIDR,I2C size identification register" hexmask.long 0xC 0.--31. 1. "SID,SID" tree.end endif tree.end sif (cpuis("STM32MP151*")||cpuis("STM32MP153*")||cpuis("STM32MP157*")) tree "IPCC (Inter-Processor Communication Controller)" base ad:0x4C001000 group.long 0x0++0xB line.long 0x0 "IPCC_C1CR,IPCC Processor 1 control register" bitfld.long 0x0 16. "TXFIE,TXFIE" "0,1" bitfld.long 0x0 0. "RXOIE,RXOIE" "0,1" line.long 0x4 "IPCC_C1MR,IPCC Processor 1 mask register" hexmask.long.byte 0x4 16.--21. 1. "CHxFM,CHxFM" hexmask.long.byte 0x4 0.--5. 1. "CHxOM,CHxOM" line.long 0x8 "IPCC_C1SCR,Reading this register will always return 0x0000 0000." hexmask.long.byte 0x8 16.--21. 1. "CHxS,CHxS" hexmask.long.byte 0x8 0.--5. 1. "CHxC,CHxC" rgroup.long 0xC++0x3 line.long 0x0 "IPCC_C1TOC2SR,IPCC processor 1 to processor 2 status register" hexmask.long.byte 0x0 0.--5. 1. "CHxF,CHxF" group.long 0x10++0xB line.long 0x0 "IPCC_C2CR,IPCC Processor 2 control register" bitfld.long 0x0 16. "TXFIE,TXFIE" "0,1" bitfld.long 0x0 0. "RXOIE,RXOIE" "0,1" line.long 0x4 "IPCC_C2MR,IPCC Processor 2 mask register" hexmask.long.byte 0x4 16.--21. 1. "CHxFM,CHxFM" hexmask.long.byte 0x4 0.--5. 1. "CHxOM,CHxOM" line.long 0x8 "IPCC_C2SCR,Reading this register will always return 0x0000 0000." hexmask.long.byte 0x8 16.--21. 1. "CHxS,CHxS" hexmask.long.byte 0x8 0.--5. 1. "CHxC,CHxC" rgroup.long 0x1C++0x3 line.long 0x0 "IPCC_C2TOC1SR,IPCC processor 2 to processor 1 status register" hexmask.long.byte 0x0 0.--5. 1. "CHxF,CHxF" rgroup.long 0x3F0++0xF line.long 0x0 "IPCC_HWCFGR,IPCC Hardware configuration register" hexmask.long.byte 0x0 0.--7. 1. "CHANNELS,CHANNELS" line.long 0x4 "IPCC_VER,IPCC IP Version register" hexmask.long.byte 0x4 4.--7. 1. "MAJREV,MAJREV" hexmask.long.byte 0x4 0.--3. 1. "MINREV,MINREV" line.long 0x8 "IPCC_ID,IPCC IP Identification register" hexmask.long 0x8 0.--31. 1. "IPID,IPID" line.long 0xC "IPCC_SID,IPCC Size ID register" hexmask.long 0xC 0.--31. 1. "SID,SID" tree.end endif tree "IWDG (Independent Watchdog)" base ad:0x0 sif (cpuis("STM32MP13*")||cpuis("STM32MP151*")) tree "IWDG1" base ad:0x5C003000 wgroup.long 0x0++0x3 line.long 0x0 "IWDG_KR,Key register" hexmask.long.word 0x0 0.--15. 1. "KEY,KEY" group.long 0x4++0x7 line.long 0x0 "IWDG_PR,Prescaler register" bitfld.long 0x0 0.--2. "PR,PR" "0,1,2,3,4,5,6,7" line.long 0x4 "IWDG_RLR,Reload register" hexmask.long.word 0x4 0.--11. 1. "RL,RL" rgroup.long 0xC++0x3 line.long 0x0 "IWDG_SR,Status register" bitfld.long 0x0 2. "WVU,WVU" "0,1" bitfld.long 0x0 1. "RVU,RVU" "0,1" bitfld.long 0x0 0. "PVU,PVU" "0,1" group.long 0x10++0x3 line.long 0x0 "IWDG_WINR,Window register" hexmask.long.word 0x0 0.--11. 1. "WIN,WIN" rgroup.long 0x3F0++0x3 line.long 0x0 "IWDG_HWCFGR,IWDG hardware configuration register" hexmask.long.byte 0x0 4.--7. 1. "PR_DEFAULT,PR_DEFAULT" hexmask.long.byte 0x0 0.--3. 1. "WINDOW,WINDOW" group.long 0x14++0x3 line.long 0x0 "IWDG_EWCR,IWDG early wake-up interrupt register" bitfld.long 0x0 15. "EWIE,EWIE" "0,1" bitfld.long 0x0 14. "EWIC,EWIC" "0,1" hexmask.long.word 0x0 0.--11. 1. "EWIT,EWIT" rgroup.long 0x3F4++0xB line.long 0x0 "IWDG_VERR,IWDG version register" hexmask.long.byte 0x0 4.--7. 1. "MAJREV,MAJREV" hexmask.long.byte 0x0 0.--3. 1. "MINREV,MINREV" line.long 0x4 "IWDG_IDR,IWDG identification register" hexmask.long 0x4 0.--31. 1. "ID,ID" line.long 0x8 "IWDG_SIDR,IWDG size identification register" hexmask.long 0x8 0.--31. 1. "SID,SID" tree.end endif sif (cpuis("STM32MP13*")||cpuis("STM32MP151*")) tree "IWDG2" base ad:0x5A002000 wgroup.long 0x0++0x3 line.long 0x0 "IWDG_KR,Key register" hexmask.long.word 0x0 0.--15. 1. "KEY,KEY" group.long 0x4++0x7 line.long 0x0 "IWDG_PR,Prescaler register" bitfld.long 0x0 0.--2. "PR,PR" "0,1,2,3,4,5,6,7" line.long 0x4 "IWDG_RLR,Reload register" hexmask.long.word 0x4 0.--11. 1. "RL,RL" rgroup.long 0xC++0x3 line.long 0x0 "IWDG_SR,Status register" bitfld.long 0x0 2. "WVU,WVU" "0,1" bitfld.long 0x0 1. "RVU,RVU" "0,1" bitfld.long 0x0 0. "PVU,PVU" "0,1" group.long 0x10++0x3 line.long 0x0 "IWDG_WINR,Window register" hexmask.long.word 0x0 0.--11. 1. "WIN,WIN" rgroup.long 0x3F0++0x3 line.long 0x0 "IWDG_HWCFGR,IWDG hardware configuration register" hexmask.long.byte 0x0 4.--7. 1. "PR_DEFAULT,PR_DEFAULT" hexmask.long.byte 0x0 0.--3. 1. "WINDOW,WINDOW" group.long 0x14++0x3 line.long 0x0 "IWDG_EWCR,IWDG early wake-up interrupt register" bitfld.long 0x0 15. "EWIE,EWIE" "0,1" bitfld.long 0x0 14. "EWIC,EWIC" "0,1" hexmask.long.word 0x0 0.--11. 1. "EWIT,EWIT" rgroup.long 0x3F4++0xB line.long 0x0 "IWDG_VERR,IWDG version register" hexmask.long.byte 0x0 4.--7. 1. "MAJREV,MAJREV" hexmask.long.byte 0x0 0.--3. 1. "MINREV,MINREV" line.long 0x4 "IWDG_IDR,IWDG identification register" hexmask.long 0x4 0.--31. 1. "ID,ID" line.long 0x8 "IWDG_SIDR,IWDG size identification register" hexmask.long 0x8 0.--31. 1. "SID,SID" tree.end endif sif (cpuis("STM32MP153*")) tree "IWDG1" base ad:0x5C003000 wgroup.long 0x0++0x3 line.long 0x0 "IWDG_KR,Key register" hexmask.long.word 0x0 0.--15. 1. "KEY,KEY" group.long 0x4++0x7 line.long 0x0 "IWDG_PR,Prescaler register" bitfld.long 0x0 0.--2. "PR,PR" "0,1,2,3,4,5,6,7" line.long 0x4 "IWDG_RLR,Reload register" hexmask.long.word 0x4 0.--11. 1. "RL,RL" rgroup.long 0xC++0x3 line.long 0x0 "IWDG_SR,Status register" bitfld.long 0x0 2. "WVU,WVU" "0,1" bitfld.long 0x0 1. "RVU,RVU" "0,1" bitfld.long 0x0 0. "PVU,PVU" "0,1" group.long 0x10++0x3 line.long 0x0 "IWDG_WINR,Window register" hexmask.long.word 0x0 0.--11. 1. "WIN,WIN" rgroup.long 0x3F0++0x3 line.long 0x0 "IWDG_HWCFGR,IWDG hardware configuration register" hexmask.long.byte 0x0 4.--7. 1. "PR_DEFAULT,PR_DEFAULT" hexmask.long.byte 0x0 0.--3. 1. "WINDOW,WINDOW" group.long 0x14++0x3 line.long 0x0 "IWDG_EWCR,IWDG early wake-up interrupt register" bitfld.long 0x0 15. "EWIE,EWIE" "0,1" bitfld.long 0x0 14. "EWIC,EWIC" "0,1" hexmask.long.word 0x0 0.--11. 1. "EWIT,EWIT" rgroup.long 0x3F4++0xB line.long 0x0 "IWDG_VERR,IWDG version register" hexmask.long.byte 0x0 4.--7. 1. "MAJREV,MAJREV" hexmask.long.byte 0x0 0.--3. 1. "MINREV,MINREV" line.long 0x4 "IWDG_IDR,IWDG identification register" hexmask.long 0x4 0.--31. 1. "ID,ID" line.long 0x8 "IWDG_SIDR,IWDG size identification register" hexmask.long 0x8 0.--31. 1. "SID,SID" tree.end endif sif (cpuis("STM32MP153*")) tree "IWDG2" base ad:0x5A002000 wgroup.long 0x0++0x3 line.long 0x0 "IWDG_KR,Key register" hexmask.long.word 0x0 0.--15. 1. "KEY,KEY" group.long 0x4++0x7 line.long 0x0 "IWDG_PR,Prescaler register" bitfld.long 0x0 0.--2. "PR,PR" "0,1,2,3,4,5,6,7" line.long 0x4 "IWDG_RLR,Reload register" hexmask.long.word 0x4 0.--11. 1. "RL,RL" rgroup.long 0xC++0x3 line.long 0x0 "IWDG_SR,Status register" bitfld.long 0x0 2. "WVU,WVU" "0,1" bitfld.long 0x0 1. "RVU,RVU" "0,1" bitfld.long 0x0 0. "PVU,PVU" "0,1" group.long 0x10++0x3 line.long 0x0 "IWDG_WINR,Window register" hexmask.long.word 0x0 0.--11. 1. "WIN,WIN" rgroup.long 0x3F0++0x3 line.long 0x0 "IWDG_HWCFGR,IWDG hardware configuration register" hexmask.long.byte 0x0 4.--7. 1. "PR_DEFAULT,PR_DEFAULT" hexmask.long.byte 0x0 0.--3. 1. "WINDOW,WINDOW" group.long 0x14++0x3 line.long 0x0 "IWDG_EWCR,IWDG early wake-up interrupt register" bitfld.long 0x0 15. "EWIE,EWIE" "0,1" bitfld.long 0x0 14. "EWIC,EWIC" "0,1" hexmask.long.word 0x0 0.--11. 1. "EWIT,EWIT" rgroup.long 0x3F4++0xB line.long 0x0 "IWDG_VERR,IWDG version register" hexmask.long.byte 0x0 4.--7. 1. "MAJREV,MAJREV" hexmask.long.byte 0x0 0.--3. 1. "MINREV,MINREV" line.long 0x4 "IWDG_IDR,IWDG identification register" hexmask.long 0x4 0.--31. 1. "ID,ID" line.long 0x8 "IWDG_SIDR,IWDG size identification register" hexmask.long 0x8 0.--31. 1. "SID,SID" tree.end endif sif (cpuis("STM32MP157*")) tree "IWDG1" base ad:0x5C003000 wgroup.long 0x0++0x3 line.long 0x0 "IWDG_KR,Key register" hexmask.long.word 0x0 0.--15. 1. "KEY,KEY" group.long 0x4++0x7 line.long 0x0 "IWDG_PR,Prescaler register" bitfld.long 0x0 0.--2. "PR,PR" "0,1,2,3,4,5,6,7" line.long 0x4 "IWDG_RLR,Reload register" hexmask.long.word 0x4 0.--11. 1. "RL,RL" rgroup.long 0xC++0x3 line.long 0x0 "IWDG_SR,Status register" bitfld.long 0x0 2. "WVU,WVU" "0,1" bitfld.long 0x0 1. "RVU,RVU" "0,1" bitfld.long 0x0 0. "PVU,PVU" "0,1" group.long 0x10++0x7 line.long 0x0 "IWDG_WINR,Window register" hexmask.long.word 0x0 0.--11. 1. "WIN,WIN" line.long 0x4 "IWDG_EWCR,IWDG early wake-up interrupt register" bitfld.long 0x4 15. "EWIE,EWIE" "0,1" bitfld.long 0x4 14. "EWIC,EWIC" "0,1" hexmask.long.word 0x4 0.--11. 1. "EWIT,EWIT" rgroup.long 0x3F0++0xF line.long 0x0 "IWDG_HWCFGR,IWDG hardware configuration register" hexmask.long.byte 0x0 4.--7. 1. "PR_DEFAULT,PR_DEFAULT" hexmask.long.byte 0x0 0.--3. 1. "WINDOW,WINDOW" line.long 0x4 "IWDG_VERR,IWDG version register" hexmask.long.byte 0x4 4.--7. 1. "MAJREV,MAJREV" hexmask.long.byte 0x4 0.--3. 1. "MINREV,MINREV" line.long 0x8 "IWDG_IDR,IWDG identification register" hexmask.long 0x8 0.--31. 1. "ID,ID" line.long 0xC "IWDG_SIDR,IWDG size identification register" hexmask.long 0xC 0.--31. 1. "SID,SID" tree.end endif sif (cpuis("STM32MP157*")) tree "IWDG2" base ad:0x5A002000 wgroup.long 0x0++0x3 line.long 0x0 "IWDG_KR,Key register" hexmask.long.word 0x0 0.--15. 1. "KEY,KEY" group.long 0x4++0x7 line.long 0x0 "IWDG_PR,Prescaler register" bitfld.long 0x0 0.--2. "PR,PR" "0,1,2,3,4,5,6,7" line.long 0x4 "IWDG_RLR,Reload register" hexmask.long.word 0x4 0.--11. 1. "RL,RL" rgroup.long 0xC++0x3 line.long 0x0 "IWDG_SR,Status register" bitfld.long 0x0 2. "WVU,WVU" "0,1" bitfld.long 0x0 1. "RVU,RVU" "0,1" bitfld.long 0x0 0. "PVU,PVU" "0,1" group.long 0x10++0x7 line.long 0x0 "IWDG_WINR,Window register" hexmask.long.word 0x0 0.--11. 1. "WIN,WIN" line.long 0x4 "IWDG_EWCR,IWDG early wake-up interrupt register" bitfld.long 0x4 15. "EWIE,EWIE" "0,1" bitfld.long 0x4 14. "EWIC,EWIC" "0,1" hexmask.long.word 0x4 0.--11. 1. "EWIT,EWIT" rgroup.long 0x3F0++0xF line.long 0x0 "IWDG_HWCFGR,IWDG hardware configuration register" hexmask.long.byte 0x0 4.--7. 1. "PR_DEFAULT,PR_DEFAULT" hexmask.long.byte 0x0 0.--3. 1. "WINDOW,WINDOW" line.long 0x4 "IWDG_VERR,IWDG version register" hexmask.long.byte 0x4 4.--7. 1. "MAJREV,MAJREV" hexmask.long.byte 0x4 0.--3. 1. "MINREV,MINREV" line.long 0x8 "IWDG_IDR,IWDG identification register" hexmask.long 0x8 0.--31. 1. "ID,ID" line.long 0xC "IWDG_SIDR,IWDG size identification register" hexmask.long 0xC 0.--31. 1. "SID,SID" tree.end endif tree.end tree "LPTIM (Low-Power Timer)" base ad:0x0 sif (cpuis("STM32MP13*")) tree "LPTIM1" base ad:0x40009000 rgroup.long 0x0++0x3 line.long 0x0 "LPTIM_ISR,LPTIM interrupt and status register" bitfld.long 0x0 6. "DOWN,Counter direction change up to down" "0,1" bitfld.long 0x0 5. "UP,Counter direction change down to up" "0,1" newline bitfld.long 0x0 4. "ARROK,Autoreload register update OK" "0,1" bitfld.long 0x0 3. "CMPOK,Compare register update OK" "0,1" newline bitfld.long 0x0 2. "EXTTRIG,External trigger edge event" "0,1" bitfld.long 0x0 1. "ARRM,Autoreload match" "0,1" newline bitfld.long 0x0 0. "CMPM,Compare match" "0,1" wgroup.long 0x4++0x3 line.long 0x0 "LPTIM_ICR,LPTIM interrupt clear register" bitfld.long 0x0 6. "DOWNCF,Direction change to down clear flag" "0,1" bitfld.long 0x0 5. "UPCF,Direction change to UP clear flag" "0,1" newline bitfld.long 0x0 4. "ARROKCF,Autoreload register update OK clear flag" "0,1" bitfld.long 0x0 3. "CMPOKCF,Compare register update OK clear flag" "0,1" newline bitfld.long 0x0 2. "EXTTRIGCF,External trigger valid edge clear flag" "0,1" bitfld.long 0x0 1. "ARRMCF,Autoreload match clear flag" "0,1" newline bitfld.long 0x0 0. "CMPMCF,Compare match clear flag" "0,1" group.long 0x8++0x13 line.long 0x0 "LPTIM_IER,LPTIM interrupt enable register" bitfld.long 0x0 6. "DOWNIE,Direction change to down Interrupt Enable" "0: DOWN interrupt disabled,1: DOWN interrupt enabled" bitfld.long 0x0 5. "UPIE,Direction change to UP Interrupt Enable" "0: UP interrupt disabled,1: UP interrupt enabled" newline bitfld.long 0x0 4. "ARROKIE,Autoreload register update OK Interrupt Enable" "0: ARROK interrupt disabled,1: ARROK interrupt enabled" bitfld.long 0x0 3. "CMPOKIE,Compare register update OK Interrupt Enable" "0: CMPOK interrupt disabled,1: CMPOK interrupt enabled" newline bitfld.long 0x0 2. "EXTTRIGIE,External trigger valid edge Interrupt Enable" "0: EXTTRIG interrupt disabled,1: EXTTRIG interrupt enabled" bitfld.long 0x0 1. "ARRMIE,Autoreload match Interrupt Enable" "0: ARRM interrupt disabled,1: ARRM interrupt enabled" newline bitfld.long 0x0 0. "CMPMIE,Compare match Interrupt Enable" "0: CMPM interrupt disabled,1: CMPM interrupt enabled" line.long 0x4 "LPTIM_CFGR,LPTIM configuration register" bitfld.long 0x4 24. "ENC,Encoder mode enable" "0: Encoder mode disabled,1: Encoder mode enabled" bitfld.long 0x4 23. "COUNTMODE,counter mode enabled" "0: the counter is incremented following each..,1: the counter is incremented following each valid.." newline bitfld.long 0x4 22. "PRELOAD,Registers update mode" "0: Registers are updated after each APB bus write..,1: Registers are updated at the end of the current.." bitfld.long 0x4 21. "WAVPOL,Waveform shape polarity" "0: The LPTIM output reflects the compare results..,1: The LPTIM output reflects the inverse of the.." newline bitfld.long 0x4 20. "WAVE,Waveform shape" "0: Deactivate Set-once mode PWM or One Pulse..,1: Activate the Set-once mode" bitfld.long 0x4 19. "TIMOUT,Timeout enable" "0: A trigger event arriving when the timer is..,1: A trigger event arriving when the timer is.." newline bitfld.long 0x4 17.--18. "TRIGEN,Trigger enable and polarity" "0: software trigger (counting start is initiated by..,1: rising edge is the active edge,2: falling edge is the active edge,3: both edges are active edges" bitfld.long 0x4 13.--15. "TRIGSEL,Trigger selector" "0: lptim_ext_trig0,1: lptim_ext_trig1,2: lptim_ext_trig2,3: lptim_ext_trig3,4: lptim_ext_trig4,5: lptim_ext_trig5,6: lptim_ext_trig6,7: lptim_ext_trig7" newline bitfld.long 0x4 9.--11. "PRESC,Clock prescaler" "0: /1,1: /2,2: /4,3: /8,4: /16,5: /32,6: /64,7: /128" bitfld.long 0x4 6.--7. "TRGFLT,Configurable digital filter for trigger" "0: any trigger active level change is considered as..,1: trigger active level change must be stable for..,2: trigger active level change must be stable for..,3: trigger active level change must be stable for.." newline bitfld.long 0x4 3.--4. "CKFLT,Configurable digital filter for external clock" "0: any external clock signal level change is..,1: external clock signal level change must be..,2: external clock signal level change must be..,3: external clock signal level change must be.." bitfld.long 0x4 1.--2. "CKPOL,Clock Polarity" "0: the rising edge is the active edge used for..,1: the falling edge is the active edge used for..,2: both edges are active edges. When both external..,3: not allowed" newline bitfld.long 0x4 0. "CKSEL,Clock selector" "0: LPTIM is clocked by internal clock source (APB..,1: LPTIM is clocked by an external clock source.." line.long 0x8 "LPTIM_CR,LPTIM control register" bitfld.long 0x8 4. "RSTARE,Reset after read enable" "0,1" bitfld.long 0x8 3. "COUNTRST,Counter reset" "0,1" newline bitfld.long 0x8 2. "CNTSTRT,Timer start in Continuous mode" "0,1" bitfld.long 0x8 1. "SNGSTRT,LPTIM start in Single mode" "0,1" newline bitfld.long 0x8 0. "ENABLE,LPTIM enable" "0: LPTIM is disabled,1: LPTIM is enabled" line.long 0xC "LPTIM_CMP,LPTIM compare register" hexmask.long.word 0xC 0.--15. 1. "CMP,Compare value" line.long 0x10 "LPTIM_ARR,LPTIM autoreload register" hexmask.long.word 0x10 0.--15. 1. "ARR,Auto reload value" rgroup.long 0x1C++0x3 line.long 0x0 "LPTIM_CNT,LPTIM counter register" hexmask.long.word 0x0 0.--15. 1. "CNT,Counter value" group.long 0x24++0x3 line.long 0x0 "LPTIM_CFGR2,LPTIM configuration register 2" bitfld.long 0x0 4.--5. "IN2SEL,LPTIM input 2 selection" "0: lptim_in2_mux0,1: lptim_in2_mux1,2: lptim_in2_mux2,3: lptim_in2_mux3" bitfld.long 0x0 0.--1. "IN1SEL,LPTIM input 1 selection" "0: lptim_in1_mux0,1: lptim_in1_mux1,2: lptim_in1_mux2,3: lptim_in1_mux3" rgroup.long 0x3F4++0xB line.long 0x0 "LPTIM_VERR,LPTIM peripheral version identification register" hexmask.long.byte 0x0 4.--7. 1. "MAJREV,Major revision" hexmask.long.byte 0x0 0.--3. 1. "MINREV,Minor revision" line.long 0x4 "LPTIM_PIDR,LPTIM peripheral type identification register" hexmask.long 0x4 0.--31. 1. "P_ID,Peripheral type identifier" line.long 0x8 "LPTIM_SIDR,LPTIM registers map size identification register" hexmask.long 0x8 0.--31. 1. "S_ID,Registers map size identifier" tree.end endif sif (cpuis("STM32MP13*")) tree "LPTIM2" base ad:0x50021000 rgroup.long 0x0++0x3 line.long 0x0 "LPTIM_ISR,LPTIM interrupt and status register" bitfld.long 0x0 6. "DOWN,Counter direction change up to down" "0,1" bitfld.long 0x0 5. "UP,Counter direction change down to up" "0,1" newline bitfld.long 0x0 4. "ARROK,Autoreload register update OK" "0,1" bitfld.long 0x0 3. "CMPOK,Compare register update OK" "0,1" newline bitfld.long 0x0 2. "EXTTRIG,External trigger edge event" "0,1" bitfld.long 0x0 1. "ARRM,Autoreload match" "0,1" newline bitfld.long 0x0 0. "CMPM,Compare match" "0,1" wgroup.long 0x4++0x3 line.long 0x0 "LPTIM_ICR,LPTIM interrupt clear register" bitfld.long 0x0 6. "DOWNCF,Direction change to down clear flag" "0,1" bitfld.long 0x0 5. "UPCF,Direction change to UP clear flag" "0,1" newline bitfld.long 0x0 4. "ARROKCF,Autoreload register update OK clear flag" "0,1" bitfld.long 0x0 3. "CMPOKCF,Compare register update OK clear flag" "0,1" newline bitfld.long 0x0 2. "EXTTRIGCF,External trigger valid edge clear flag" "0,1" bitfld.long 0x0 1. "ARRMCF,Autoreload match clear flag" "0,1" newline bitfld.long 0x0 0. "CMPMCF,Compare match clear flag" "0,1" group.long 0x8++0x13 line.long 0x0 "LPTIM_IER,LPTIM interrupt enable register" bitfld.long 0x0 6. "DOWNIE,Direction change to down Interrupt Enable" "0: DOWN interrupt disabled,1: DOWN interrupt enabled" bitfld.long 0x0 5. "UPIE,Direction change to UP Interrupt Enable" "0: UP interrupt disabled,1: UP interrupt enabled" newline bitfld.long 0x0 4. "ARROKIE,Autoreload register update OK Interrupt Enable" "0: ARROK interrupt disabled,1: ARROK interrupt enabled" bitfld.long 0x0 3. "CMPOKIE,Compare register update OK Interrupt Enable" "0: CMPOK interrupt disabled,1: CMPOK interrupt enabled" newline bitfld.long 0x0 2. "EXTTRIGIE,External trigger valid edge Interrupt Enable" "0: EXTTRIG interrupt disabled,1: EXTTRIG interrupt enabled" bitfld.long 0x0 1. "ARRMIE,Autoreload match Interrupt Enable" "0: ARRM interrupt disabled,1: ARRM interrupt enabled" newline bitfld.long 0x0 0. "CMPMIE,Compare match Interrupt Enable" "0: CMPM interrupt disabled,1: CMPM interrupt enabled" line.long 0x4 "LPTIM_CFGR,LPTIM configuration register" bitfld.long 0x4 24. "ENC,Encoder mode enable" "0: Encoder mode disabled,1: Encoder mode enabled" bitfld.long 0x4 23. "COUNTMODE,counter mode enabled" "0: the counter is incremented following each..,1: the counter is incremented following each valid.." newline bitfld.long 0x4 22. "PRELOAD,Registers update mode" "0: Registers are updated after each APB bus write..,1: Registers are updated at the end of the current.." bitfld.long 0x4 21. "WAVPOL,Waveform shape polarity" "0: The LPTIM output reflects the compare results..,1: The LPTIM output reflects the inverse of the.." newline bitfld.long 0x4 20. "WAVE,Waveform shape" "0: Deactivate Set-once mode PWM or One Pulse..,1: Activate the Set-once mode" bitfld.long 0x4 19. "TIMOUT,Timeout enable" "0: A trigger event arriving when the timer is..,1: A trigger event arriving when the timer is.." newline bitfld.long 0x4 17.--18. "TRIGEN,Trigger enable and polarity" "0: software trigger (counting start is initiated by..,1: rising edge is the active edge,2: falling edge is the active edge,3: both edges are active edges" bitfld.long 0x4 13.--15. "TRIGSEL,Trigger selector" "0: lptim_ext_trig0,1: lptim_ext_trig1,2: lptim_ext_trig2,3: lptim_ext_trig3,4: lptim_ext_trig4,5: lptim_ext_trig5,6: lptim_ext_trig6,7: lptim_ext_trig7" newline bitfld.long 0x4 9.--11. "PRESC,Clock prescaler" "0: /1,1: /2,2: /4,3: /8,4: /16,5: /32,6: /64,7: /128" bitfld.long 0x4 6.--7. "TRGFLT,Configurable digital filter for trigger" "0: any trigger active level change is considered as..,1: trigger active level change must be stable for..,2: trigger active level change must be stable for..,3: trigger active level change must be stable for.." newline bitfld.long 0x4 3.--4. "CKFLT,Configurable digital filter for external clock" "0: any external clock signal level change is..,1: external clock signal level change must be..,2: external clock signal level change must be..,3: external clock signal level change must be.." bitfld.long 0x4 1.--2. "CKPOL,Clock Polarity" "0: the rising edge is the active edge used for..,1: the falling edge is the active edge used for..,2: both edges are active edges. When both external..,3: not allowed" newline bitfld.long 0x4 0. "CKSEL,Clock selector" "0: LPTIM is clocked by internal clock source (APB..,1: LPTIM is clocked by an external clock source.." line.long 0x8 "LPTIM_CR,LPTIM control register" bitfld.long 0x8 4. "RSTARE,Reset after read enable" "0,1" bitfld.long 0x8 3. "COUNTRST,Counter reset" "0,1" newline bitfld.long 0x8 2. "CNTSTRT,Timer start in Continuous mode" "0,1" bitfld.long 0x8 1. "SNGSTRT,LPTIM start in Single mode" "0,1" newline bitfld.long 0x8 0. "ENABLE,LPTIM enable" "0: LPTIM is disabled,1: LPTIM is enabled" line.long 0xC "LPTIM_CMP,LPTIM compare register" hexmask.long.word 0xC 0.--15. 1. "CMP,Compare value" line.long 0x10 "LPTIM_ARR,LPTIM autoreload register" hexmask.long.word 0x10 0.--15. 1. "ARR,Auto reload value" rgroup.long 0x1C++0x3 line.long 0x0 "LPTIM_CNT,LPTIM counter register" hexmask.long.word 0x0 0.--15. 1. "CNT,Counter value" group.long 0x24++0x3 line.long 0x0 "LPTIM_CFGR2,LPTIM configuration register 2" bitfld.long 0x0 4.--5. "IN2SEL,LPTIM input 2 selection" "0: lptim_in2_mux0,1: lptim_in2_mux1,2: lptim_in2_mux2,3: lptim_in2_mux3" bitfld.long 0x0 0.--1. "IN1SEL,LPTIM input 1 selection" "0: lptim_in1_mux0,1: lptim_in1_mux1,2: lptim_in1_mux2,3: lptim_in1_mux3" rgroup.long 0x3F4++0xB line.long 0x0 "LPTIM_VERR,LPTIM peripheral version identification register" hexmask.long.byte 0x0 4.--7. 1. "MAJREV,Major revision" hexmask.long.byte 0x0 0.--3. 1. "MINREV,Minor revision" line.long 0x4 "LPTIM_PIDR,LPTIM peripheral type identification register" hexmask.long 0x4 0.--31. 1. "P_ID,Peripheral type identifier" line.long 0x8 "LPTIM_SIDR,LPTIM registers map size identification register" hexmask.long 0x8 0.--31. 1. "S_ID,Registers map size identifier" tree.end endif sif (cpuis("STM32MP13*")) tree "LPTIM3" base ad:0x50022000 rgroup.long 0x0++0x3 line.long 0x0 "LPTIM_ISR,LPTIM interrupt and status register" bitfld.long 0x0 6. "DOWN,Counter direction change up to down" "0,1" bitfld.long 0x0 5. "UP,Counter direction change down to up" "0,1" newline bitfld.long 0x0 4. "ARROK,Autoreload register update OK" "0,1" bitfld.long 0x0 3. "CMPOK,Compare register update OK" "0,1" newline bitfld.long 0x0 2. "EXTTRIG,External trigger edge event" "0,1" bitfld.long 0x0 1. "ARRM,Autoreload match" "0,1" newline bitfld.long 0x0 0. "CMPM,Compare match" "0,1" wgroup.long 0x4++0x3 line.long 0x0 "LPTIM_ICR,LPTIM interrupt clear register" bitfld.long 0x0 6. "DOWNCF,Direction change to down clear flag" "0,1" bitfld.long 0x0 5. "UPCF,Direction change to UP clear flag" "0,1" newline bitfld.long 0x0 4. "ARROKCF,Autoreload register update OK clear flag" "0,1" bitfld.long 0x0 3. "CMPOKCF,Compare register update OK clear flag" "0,1" newline bitfld.long 0x0 2. "EXTTRIGCF,External trigger valid edge clear flag" "0,1" bitfld.long 0x0 1. "ARRMCF,Autoreload match clear flag" "0,1" newline bitfld.long 0x0 0. "CMPMCF,Compare match clear flag" "0,1" group.long 0x8++0x13 line.long 0x0 "LPTIM_IER,LPTIM interrupt enable register" bitfld.long 0x0 6. "DOWNIE,Direction change to down Interrupt Enable" "0: DOWN interrupt disabled,1: DOWN interrupt enabled" bitfld.long 0x0 5. "UPIE,Direction change to UP Interrupt Enable" "0: UP interrupt disabled,1: UP interrupt enabled" newline bitfld.long 0x0 4. "ARROKIE,Autoreload register update OK Interrupt Enable" "0: ARROK interrupt disabled,1: ARROK interrupt enabled" bitfld.long 0x0 3. "CMPOKIE,Compare register update OK Interrupt Enable" "0: CMPOK interrupt disabled,1: CMPOK interrupt enabled" newline bitfld.long 0x0 2. "EXTTRIGIE,External trigger valid edge Interrupt Enable" "0: EXTTRIG interrupt disabled,1: EXTTRIG interrupt enabled" bitfld.long 0x0 1. "ARRMIE,Autoreload match Interrupt Enable" "0: ARRM interrupt disabled,1: ARRM interrupt enabled" newline bitfld.long 0x0 0. "CMPMIE,Compare match Interrupt Enable" "0: CMPM interrupt disabled,1: CMPM interrupt enabled" line.long 0x4 "LPTIM_CFGR,LPTIM configuration register" bitfld.long 0x4 24. "ENC,Encoder mode enable" "0: Encoder mode disabled,1: Encoder mode enabled" bitfld.long 0x4 23. "COUNTMODE,counter mode enabled" "0: the counter is incremented following each..,1: the counter is incremented following each valid.." newline bitfld.long 0x4 22. "PRELOAD,Registers update mode" "0: Registers are updated after each APB bus write..,1: Registers are updated at the end of the current.." bitfld.long 0x4 21. "WAVPOL,Waveform shape polarity" "0: The LPTIM output reflects the compare results..,1: The LPTIM output reflects the inverse of the.." newline bitfld.long 0x4 20. "WAVE,Waveform shape" "0: Deactivate Set-once mode PWM or One Pulse..,1: Activate the Set-once mode" bitfld.long 0x4 19. "TIMOUT,Timeout enable" "0: A trigger event arriving when the timer is..,1: A trigger event arriving when the timer is.." newline bitfld.long 0x4 17.--18. "TRIGEN,Trigger enable and polarity" "0: software trigger (counting start is initiated by..,1: rising edge is the active edge,2: falling edge is the active edge,3: both edges are active edges" bitfld.long 0x4 13.--15. "TRIGSEL,Trigger selector" "0: lptim_ext_trig0,1: lptim_ext_trig1,2: lptim_ext_trig2,3: lptim_ext_trig3,4: lptim_ext_trig4,5: lptim_ext_trig5,6: lptim_ext_trig6,7: lptim_ext_trig7" newline bitfld.long 0x4 9.--11. "PRESC,Clock prescaler" "0: /1,1: /2,2: /4,3: /8,4: /16,5: /32,6: /64,7: /128" bitfld.long 0x4 6.--7. "TRGFLT,Configurable digital filter for trigger" "0: any trigger active level change is considered as..,1: trigger active level change must be stable for..,2: trigger active level change must be stable for..,3: trigger active level change must be stable for.." newline bitfld.long 0x4 3.--4. "CKFLT,Configurable digital filter for external clock" "0: any external clock signal level change is..,1: external clock signal level change must be..,2: external clock signal level change must be..,3: external clock signal level change must be.." bitfld.long 0x4 1.--2. "CKPOL,Clock Polarity" "0: the rising edge is the active edge used for..,1: the falling edge is the active edge used for..,2: both edges are active edges. When both external..,3: not allowed" newline bitfld.long 0x4 0. "CKSEL,Clock selector" "0: LPTIM is clocked by internal clock source (APB..,1: LPTIM is clocked by an external clock source.." line.long 0x8 "LPTIM_CR,LPTIM control register" bitfld.long 0x8 4. "RSTARE,Reset after read enable" "0,1" bitfld.long 0x8 3. "COUNTRST,Counter reset" "0,1" newline bitfld.long 0x8 2. "CNTSTRT,Timer start in Continuous mode" "0,1" bitfld.long 0x8 1. "SNGSTRT,LPTIM start in Single mode" "0,1" newline bitfld.long 0x8 0. "ENABLE,LPTIM enable" "0: LPTIM is disabled,1: LPTIM is enabled" line.long 0xC "LPTIM_CMP,LPTIM compare register" hexmask.long.word 0xC 0.--15. 1. "CMP,Compare value" line.long 0x10 "LPTIM_ARR,LPTIM autoreload register" hexmask.long.word 0x10 0.--15. 1. "ARR,Auto reload value" rgroup.long 0x1C++0x3 line.long 0x0 "LPTIM_CNT,LPTIM counter register" hexmask.long.word 0x0 0.--15. 1. "CNT,Counter value" group.long 0x24++0x3 line.long 0x0 "LPTIM_CFGR2,LPTIM configuration register 2" bitfld.long 0x0 4.--5. "IN2SEL,LPTIM input 2 selection" "0: lptim_in2_mux0,1: lptim_in2_mux1,2: lptim_in2_mux2,3: lptim_in2_mux3" bitfld.long 0x0 0.--1. "IN1SEL,LPTIM input 1 selection" "0: lptim_in1_mux0,1: lptim_in1_mux1,2: lptim_in1_mux2,3: lptim_in1_mux3" rgroup.long 0x3F4++0xB line.long 0x0 "LPTIM_VERR,LPTIM peripheral version identification register" hexmask.long.byte 0x0 4.--7. 1. "MAJREV,Major revision" hexmask.long.byte 0x0 0.--3. 1. "MINREV,Minor revision" line.long 0x4 "LPTIM_PIDR,LPTIM peripheral type identification register" hexmask.long 0x4 0.--31. 1. "P_ID,Peripheral type identifier" line.long 0x8 "LPTIM_SIDR,LPTIM registers map size identification register" hexmask.long 0x8 0.--31. 1. "S_ID,Registers map size identifier" tree.end endif sif (cpuis("STM32MP13*")) tree "LPTIM4" base ad:0x50023000 rgroup.long 0x0++0x3 line.long 0x0 "LPTIM_ISR,LPTIM interrupt and status register" bitfld.long 0x0 6. "DOWN,Counter direction change up to down" "0,1" bitfld.long 0x0 5. "UP,Counter direction change down to up" "0,1" newline bitfld.long 0x0 4. "ARROK,Autoreload register update OK" "0,1" bitfld.long 0x0 3. "CMPOK,Compare register update OK" "0,1" newline bitfld.long 0x0 2. "EXTTRIG,External trigger edge event" "0,1" bitfld.long 0x0 1. "ARRM,Autoreload match" "0,1" newline bitfld.long 0x0 0. "CMPM,Compare match" "0,1" wgroup.long 0x4++0x3 line.long 0x0 "LPTIM_ICR,LPTIM interrupt clear register" bitfld.long 0x0 6. "DOWNCF,Direction change to down clear flag" "0,1" bitfld.long 0x0 5. "UPCF,Direction change to UP clear flag" "0,1" newline bitfld.long 0x0 4. "ARROKCF,Autoreload register update OK clear flag" "0,1" bitfld.long 0x0 3. "CMPOKCF,Compare register update OK clear flag" "0,1" newline bitfld.long 0x0 2. "EXTTRIGCF,External trigger valid edge clear flag" "0,1" bitfld.long 0x0 1. "ARRMCF,Autoreload match clear flag" "0,1" newline bitfld.long 0x0 0. "CMPMCF,Compare match clear flag" "0,1" group.long 0x8++0x13 line.long 0x0 "LPTIM_IER,LPTIM interrupt enable register" bitfld.long 0x0 6. "DOWNIE,Direction change to down Interrupt Enable" "0: DOWN interrupt disabled,1: DOWN interrupt enabled" bitfld.long 0x0 5. "UPIE,Direction change to UP Interrupt Enable" "0: UP interrupt disabled,1: UP interrupt enabled" newline bitfld.long 0x0 4. "ARROKIE,Autoreload register update OK Interrupt Enable" "0: ARROK interrupt disabled,1: ARROK interrupt enabled" bitfld.long 0x0 3. "CMPOKIE,Compare register update OK Interrupt Enable" "0: CMPOK interrupt disabled,1: CMPOK interrupt enabled" newline bitfld.long 0x0 2. "EXTTRIGIE,External trigger valid edge Interrupt Enable" "0: EXTTRIG interrupt disabled,1: EXTTRIG interrupt enabled" bitfld.long 0x0 1. "ARRMIE,Autoreload match Interrupt Enable" "0: ARRM interrupt disabled,1: ARRM interrupt enabled" newline bitfld.long 0x0 0. "CMPMIE,Compare match Interrupt Enable" "0: CMPM interrupt disabled,1: CMPM interrupt enabled" line.long 0x4 "LPTIM_CFGR,LPTIM configuration register" bitfld.long 0x4 24. "ENC,Encoder mode enable" "0: Encoder mode disabled,1: Encoder mode enabled" bitfld.long 0x4 23. "COUNTMODE,counter mode enabled" "0: the counter is incremented following each..,1: the counter is incremented following each valid.." newline bitfld.long 0x4 22. "PRELOAD,Registers update mode" "0: Registers are updated after each APB bus write..,1: Registers are updated at the end of the current.." bitfld.long 0x4 21. "WAVPOL,Waveform shape polarity" "0: The LPTIM output reflects the compare results..,1: The LPTIM output reflects the inverse of the.." newline bitfld.long 0x4 20. "WAVE,Waveform shape" "0: Deactivate Set-once mode PWM or One Pulse..,1: Activate the Set-once mode" bitfld.long 0x4 19. "TIMOUT,Timeout enable" "0: A trigger event arriving when the timer is..,1: A trigger event arriving when the timer is.." newline bitfld.long 0x4 17.--18. "TRIGEN,Trigger enable and polarity" "0: software trigger (counting start is initiated by..,1: rising edge is the active edge,2: falling edge is the active edge,3: both edges are active edges" bitfld.long 0x4 13.--15. "TRIGSEL,Trigger selector" "0: lptim_ext_trig0,1: lptim_ext_trig1,2: lptim_ext_trig2,3: lptim_ext_trig3,4: lptim_ext_trig4,5: lptim_ext_trig5,6: lptim_ext_trig6,7: lptim_ext_trig7" newline bitfld.long 0x4 9.--11. "PRESC,Clock prescaler" "0: /1,1: /2,2: /4,3: /8,4: /16,5: /32,6: /64,7: /128" bitfld.long 0x4 6.--7. "TRGFLT,Configurable digital filter for trigger" "0: any trigger active level change is considered as..,1: trigger active level change must be stable for..,2: trigger active level change must be stable for..,3: trigger active level change must be stable for.." newline bitfld.long 0x4 3.--4. "CKFLT,Configurable digital filter for external clock" "0: any external clock signal level change is..,1: external clock signal level change must be..,2: external clock signal level change must be..,3: external clock signal level change must be.." bitfld.long 0x4 1.--2. "CKPOL,Clock Polarity" "0: the rising edge is the active edge used for..,1: the falling edge is the active edge used for..,2: both edges are active edges. When both external..,3: not allowed" newline bitfld.long 0x4 0. "CKSEL,Clock selector" "0: LPTIM is clocked by internal clock source (APB..,1: LPTIM is clocked by an external clock source.." line.long 0x8 "LPTIM_CR,LPTIM control register" bitfld.long 0x8 4. "RSTARE,Reset after read enable" "0,1" bitfld.long 0x8 3. "COUNTRST,Counter reset" "0,1" newline bitfld.long 0x8 2. "CNTSTRT,Timer start in Continuous mode" "0,1" bitfld.long 0x8 1. "SNGSTRT,LPTIM start in Single mode" "0,1" newline bitfld.long 0x8 0. "ENABLE,LPTIM enable" "0: LPTIM is disabled,1: LPTIM is enabled" line.long 0xC "LPTIM_CMP,LPTIM compare register" hexmask.long.word 0xC 0.--15. 1. "CMP,Compare value" line.long 0x10 "LPTIM_ARR,LPTIM autoreload register" hexmask.long.word 0x10 0.--15. 1. "ARR,Auto reload value" rgroup.long 0x1C++0x3 line.long 0x0 "LPTIM_CNT,LPTIM counter register" hexmask.long.word 0x0 0.--15. 1. "CNT,Counter value" group.long 0x24++0x3 line.long 0x0 "LPTIM_CFGR2,LPTIM configuration register 2" bitfld.long 0x0 4.--5. "IN2SEL,LPTIM input 2 selection" "0: lptim_in2_mux0,1: lptim_in2_mux1,2: lptim_in2_mux2,3: lptim_in2_mux3" bitfld.long 0x0 0.--1. "IN1SEL,LPTIM input 1 selection" "0: lptim_in1_mux0,1: lptim_in1_mux1,2: lptim_in1_mux2,3: lptim_in1_mux3" rgroup.long 0x3F4++0xB line.long 0x0 "LPTIM_VERR,LPTIM peripheral version identification register" hexmask.long.byte 0x0 4.--7. 1. "MAJREV,Major revision" hexmask.long.byte 0x0 0.--3. 1. "MINREV,Minor revision" line.long 0x4 "LPTIM_PIDR,LPTIM peripheral type identification register" hexmask.long 0x4 0.--31. 1. "P_ID,Peripheral type identifier" line.long 0x8 "LPTIM_SIDR,LPTIM registers map size identification register" hexmask.long 0x8 0.--31. 1. "S_ID,Registers map size identifier" tree.end endif sif (cpuis("STM32MP13*")) tree "LPTIM5" base ad:0x50024000 rgroup.long 0x0++0x3 line.long 0x0 "LPTIM_ISR,LPTIM interrupt and status register" bitfld.long 0x0 6. "DOWN,Counter direction change up to down" "0,1" bitfld.long 0x0 5. "UP,Counter direction change down to up" "0,1" newline bitfld.long 0x0 4. "ARROK,Autoreload register update OK" "0,1" bitfld.long 0x0 3. "CMPOK,Compare register update OK" "0,1" newline bitfld.long 0x0 2. "EXTTRIG,External trigger edge event" "0,1" bitfld.long 0x0 1. "ARRM,Autoreload match" "0,1" newline bitfld.long 0x0 0. "CMPM,Compare match" "0,1" wgroup.long 0x4++0x3 line.long 0x0 "LPTIM_ICR,LPTIM interrupt clear register" bitfld.long 0x0 6. "DOWNCF,Direction change to down clear flag" "0,1" bitfld.long 0x0 5. "UPCF,Direction change to UP clear flag" "0,1" newline bitfld.long 0x0 4. "ARROKCF,Autoreload register update OK clear flag" "0,1" bitfld.long 0x0 3. "CMPOKCF,Compare register update OK clear flag" "0,1" newline bitfld.long 0x0 2. "EXTTRIGCF,External trigger valid edge clear flag" "0,1" bitfld.long 0x0 1. "ARRMCF,Autoreload match clear flag" "0,1" newline bitfld.long 0x0 0. "CMPMCF,Compare match clear flag" "0,1" group.long 0x8++0x13 line.long 0x0 "LPTIM_IER,LPTIM interrupt enable register" bitfld.long 0x0 6. "DOWNIE,Direction change to down Interrupt Enable" "0: DOWN interrupt disabled,1: DOWN interrupt enabled" bitfld.long 0x0 5. "UPIE,Direction change to UP Interrupt Enable" "0: UP interrupt disabled,1: UP interrupt enabled" newline bitfld.long 0x0 4. "ARROKIE,Autoreload register update OK Interrupt Enable" "0: ARROK interrupt disabled,1: ARROK interrupt enabled" bitfld.long 0x0 3. "CMPOKIE,Compare register update OK Interrupt Enable" "0: CMPOK interrupt disabled,1: CMPOK interrupt enabled" newline bitfld.long 0x0 2. "EXTTRIGIE,External trigger valid edge Interrupt Enable" "0: EXTTRIG interrupt disabled,1: EXTTRIG interrupt enabled" bitfld.long 0x0 1. "ARRMIE,Autoreload match Interrupt Enable" "0: ARRM interrupt disabled,1: ARRM interrupt enabled" newline bitfld.long 0x0 0. "CMPMIE,Compare match Interrupt Enable" "0: CMPM interrupt disabled,1: CMPM interrupt enabled" line.long 0x4 "LPTIM_CFGR,LPTIM configuration register" bitfld.long 0x4 24. "ENC,Encoder mode enable" "0: Encoder mode disabled,1: Encoder mode enabled" bitfld.long 0x4 23. "COUNTMODE,counter mode enabled" "0: the counter is incremented following each..,1: the counter is incremented following each valid.." newline bitfld.long 0x4 22. "PRELOAD,Registers update mode" "0: Registers are updated after each APB bus write..,1: Registers are updated at the end of the current.." bitfld.long 0x4 21. "WAVPOL,Waveform shape polarity" "0: The LPTIM output reflects the compare results..,1: The LPTIM output reflects the inverse of the.." newline bitfld.long 0x4 20. "WAVE,Waveform shape" "0: Deactivate Set-once mode PWM or One Pulse..,1: Activate the Set-once mode" bitfld.long 0x4 19. "TIMOUT,Timeout enable" "0: A trigger event arriving when the timer is..,1: A trigger event arriving when the timer is.." newline bitfld.long 0x4 17.--18. "TRIGEN,Trigger enable and polarity" "0: software trigger (counting start is initiated by..,1: rising edge is the active edge,2: falling edge is the active edge,3: both edges are active edges" bitfld.long 0x4 13.--15. "TRIGSEL,Trigger selector" "0: lptim_ext_trig0,1: lptim_ext_trig1,2: lptim_ext_trig2,3: lptim_ext_trig3,4: lptim_ext_trig4,5: lptim_ext_trig5,6: lptim_ext_trig6,7: lptim_ext_trig7" newline bitfld.long 0x4 9.--11. "PRESC,Clock prescaler" "0: /1,1: /2,2: /4,3: /8,4: /16,5: /32,6: /64,7: /128" bitfld.long 0x4 6.--7. "TRGFLT,Configurable digital filter for trigger" "0: any trigger active level change is considered as..,1: trigger active level change must be stable for..,2: trigger active level change must be stable for..,3: trigger active level change must be stable for.." newline bitfld.long 0x4 3.--4. "CKFLT,Configurable digital filter for external clock" "0: any external clock signal level change is..,1: external clock signal level change must be..,2: external clock signal level change must be..,3: external clock signal level change must be.." bitfld.long 0x4 1.--2. "CKPOL,Clock Polarity" "0: the rising edge is the active edge used for..,1: the falling edge is the active edge used for..,2: both edges are active edges. When both external..,3: not allowed" newline bitfld.long 0x4 0. "CKSEL,Clock selector" "0: LPTIM is clocked by internal clock source (APB..,1: LPTIM is clocked by an external clock source.." line.long 0x8 "LPTIM_CR,LPTIM control register" bitfld.long 0x8 4. "RSTARE,Reset after read enable" "0,1" bitfld.long 0x8 3. "COUNTRST,Counter reset" "0,1" newline bitfld.long 0x8 2. "CNTSTRT,Timer start in Continuous mode" "0,1" bitfld.long 0x8 1. "SNGSTRT,LPTIM start in Single mode" "0,1" newline bitfld.long 0x8 0. "ENABLE,LPTIM enable" "0: LPTIM is disabled,1: LPTIM is enabled" line.long 0xC "LPTIM_CMP,LPTIM compare register" hexmask.long.word 0xC 0.--15. 1. "CMP,Compare value" line.long 0x10 "LPTIM_ARR,LPTIM autoreload register" hexmask.long.word 0x10 0.--15. 1. "ARR,Auto reload value" rgroup.long 0x1C++0x3 line.long 0x0 "LPTIM_CNT,LPTIM counter register" hexmask.long.word 0x0 0.--15. 1. "CNT,Counter value" group.long 0x24++0x3 line.long 0x0 "LPTIM_CFGR2,LPTIM configuration register 2" bitfld.long 0x0 4.--5. "IN2SEL,LPTIM input 2 selection" "0: lptim_in2_mux0,1: lptim_in2_mux1,2: lptim_in2_mux2,3: lptim_in2_mux3" bitfld.long 0x0 0.--1. "IN1SEL,LPTIM input 1 selection" "0: lptim_in1_mux0,1: lptim_in1_mux1,2: lptim_in1_mux2,3: lptim_in1_mux3" rgroup.long 0x3F4++0xB line.long 0x0 "LPTIM_VERR,LPTIM peripheral version identification register" hexmask.long.byte 0x0 4.--7. 1. "MAJREV,Major revision" hexmask.long.byte 0x0 0.--3. 1. "MINREV,Minor revision" line.long 0x4 "LPTIM_PIDR,LPTIM peripheral type identification register" hexmask.long 0x4 0.--31. 1. "P_ID,Peripheral type identifier" line.long 0x8 "LPTIM_SIDR,LPTIM registers map size identification register" hexmask.long 0x8 0.--31. 1. "S_ID,Registers map size identifier" tree.end endif sif (cpuis("STM32MP151*")||cpuis("STM32MP153*")||cpuis("STM32MP157*")) tree "LPTIM1" base ad:0x40009000 rgroup.long 0x0++0x3 line.long 0x0 "LPTIM_ISR,LPTIM interrupt and status register" bitfld.long 0x0 6. "DOWN,DOWN" "0,1" bitfld.long 0x0 5. "UP,UP" "0,1" bitfld.long 0x0 4. "ARROK,ARROK" "0,1" bitfld.long 0x0 3. "CMPOK,CMPOK" "0,1" bitfld.long 0x0 2. "EXTTRIG,EXTTRIG" "0,1" bitfld.long 0x0 1. "ARRM,ARRM" "0,1" bitfld.long 0x0 0. "CMPM,CMPM" "0,1" wgroup.long 0x4++0x3 line.long 0x0 "LPTIM_ICR,LPTIM interrupt clear register" bitfld.long 0x0 6. "DOWNCF,DOWNCF" "0,1" bitfld.long 0x0 5. "UPCF,UPCF" "0,1" bitfld.long 0x0 4. "ARROKCF,ARROKCF" "0,1" bitfld.long 0x0 3. "CMPOKCF,CMPOKCF" "0,1" bitfld.long 0x0 2. "EXTTRIGCF,EXTTRIGCF" "0,1" bitfld.long 0x0 1. "ARRMCF,ARRMCF" "0,1" bitfld.long 0x0 0. "CMPMCF,CMPMCF" "0,1" group.long 0x8++0x13 line.long 0x0 "LPTIM_IER,LPTIM interrupt enable register" bitfld.long 0x0 6. "DOWNIE,DOWNIE" "0,1" bitfld.long 0x0 5. "UPIE,UPIE" "0,1" bitfld.long 0x0 4. "ARROKIE,ARROKIE" "0,1" bitfld.long 0x0 3. "CMPOKIE,CMPOKIE" "0,1" bitfld.long 0x0 2. "EXTTRIGIE,EXTTRIGIE" "0,1" bitfld.long 0x0 1. "ARRMIE,ARRMIE" "0,1" bitfld.long 0x0 0. "CMPMIE,CMPMIE" "0,1" line.long 0x4 "LPTIM_CFGR,LPTIM configuration register" bitfld.long 0x4 24. "ENC,ENC" "0,1" bitfld.long 0x4 23. "COUNTMODE,COUNTMODE" "0,1" bitfld.long 0x4 22. "PRELOAD,PRELOAD" "0,1" bitfld.long 0x4 21. "WAVPOL,WAVPOL" "0,1" bitfld.long 0x4 20. "WAVE,WAVE" "0,1" bitfld.long 0x4 19. "TIMOUT,TIMOUT" "0,1" bitfld.long 0x4 17.--18. "TRIGEN,TRIGEN" "0,1,2,3" bitfld.long 0x4 13.--15. "TRIGSEL,TRIGSEL" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 9.--11. "PRESC,PRESC" "0,1,2,3,4,5,6,7" bitfld.long 0x4 6.--7. "TRGFLT,TRGFLT" "0,1,2,3" bitfld.long 0x4 3.--4. "CKFLT,CKFLT" "0,1,2,3" bitfld.long 0x4 1.--2. "CKPOL,CKPOL" "0,1,2,3" bitfld.long 0x4 0. "CKSEL,CKSEL" "0,1" line.long 0x8 "LPTIM_CR,LPTIM control register" bitfld.long 0x8 4. "RSTARE,RSTARE" "0,1" bitfld.long 0x8 3. "COUNTRST,COUNTRST" "0,1" bitfld.long 0x8 2. "CNTSTRT,CNTSTRT" "0,1" bitfld.long 0x8 1. "SNGSTRT,SNGSTRT" "0,1" bitfld.long 0x8 0. "ENABLE,ENABLE" "0,1" line.long 0xC "LPTIM_CMP,LPTIM compare register" hexmask.long.word 0xC 0.--15. 1. "CMP,CMP" line.long 0x10 "LPTIM_ARR,LPTIM autoreload register" hexmask.long.word 0x10 0.--15. 1. "ARR,ARR" rgroup.long 0x1C++0x3 line.long 0x0 "LPTIM_CNT,LPTIM counter register" hexmask.long.word 0x0 0.--15. 1. "CNT,CNT" group.long 0x24++0x3 line.long 0x0 "LPTIM_CFGR2,LPTIM configuration register 2" bitfld.long 0x0 4.--5. "IN2SEL,IN2SEL" "0,1,2,3" bitfld.long 0x0 0.--1. "IN1SEL,IN1SEL" "0,1,2,3" rgroup.long 0x3F0++0xF line.long 0x0 "LPTIM1_HWCFGR,LPTIM 1 peripheral hardware configuration register" hexmask.long.byte 0x0 24.--31. 1. "CFG4,CFG4" hexmask.long.byte 0x0 16.--19. 1. "CFG3,CFG3" hexmask.long.byte 0x0 8.--15. 1. "CFG2,CFG2" hexmask.long.byte 0x0 0.--7. 1. "CFG1,CFG1" line.long 0x4 "LPTIM_VERR,LPTIM peripheral version identification register" hexmask.long.byte 0x4 4.--7. 1. "MAJREV,MAJREV" hexmask.long.byte 0x4 0.--3. 1. "MINREV,MINREV" line.long 0x8 "LPTIM_PIDR,LPTIM peripheral type identification register" hexmask.long 0x8 0.--31. 1. "P_ID,P_ID" line.long 0xC "LPTIM_SIDR,LPTIM registers map size identification register" hexmask.long 0xC 0.--31. 1. "S_ID,S_ID" tree.end endif sif (cpuis("STM32MP151*")||cpuis("STM32MP153*")||cpuis("STM32MP157*")) tree "LPTIM2" base ad:0x50021000 rgroup.long 0x0++0x3 line.long 0x0 "LPTIM_ISR,LPTIM interrupt and status register" bitfld.long 0x0 6. "DOWN,DOWN" "0,1" bitfld.long 0x0 5. "UP,UP" "0,1" bitfld.long 0x0 4. "ARROK,ARROK" "0,1" bitfld.long 0x0 3. "CMPOK,CMPOK" "0,1" bitfld.long 0x0 2. "EXTTRIG,EXTTRIG" "0,1" bitfld.long 0x0 1. "ARRM,ARRM" "0,1" bitfld.long 0x0 0. "CMPM,CMPM" "0,1" wgroup.long 0x4++0x3 line.long 0x0 "LPTIM_ICR,LPTIM interrupt clear register" bitfld.long 0x0 6. "DOWNCF,DOWNCF" "0,1" bitfld.long 0x0 5. "UPCF,UPCF" "0,1" bitfld.long 0x0 4. "ARROKCF,ARROKCF" "0,1" bitfld.long 0x0 3. "CMPOKCF,CMPOKCF" "0,1" bitfld.long 0x0 2. "EXTTRIGCF,EXTTRIGCF" "0,1" bitfld.long 0x0 1. "ARRMCF,ARRMCF" "0,1" bitfld.long 0x0 0. "CMPMCF,CMPMCF" "0,1" group.long 0x8++0x13 line.long 0x0 "LPTIM_IER,LPTIM interrupt enable register" bitfld.long 0x0 6. "DOWNIE,DOWNIE" "0,1" bitfld.long 0x0 5. "UPIE,UPIE" "0,1" bitfld.long 0x0 4. "ARROKIE,ARROKIE" "0,1" bitfld.long 0x0 3. "CMPOKIE,CMPOKIE" "0,1" bitfld.long 0x0 2. "EXTTRIGIE,EXTTRIGIE" "0,1" bitfld.long 0x0 1. "ARRMIE,ARRMIE" "0,1" bitfld.long 0x0 0. "CMPMIE,CMPMIE" "0,1" line.long 0x4 "LPTIM_CFGR,LPTIM configuration register" bitfld.long 0x4 24. "ENC,ENC" "0,1" bitfld.long 0x4 23. "COUNTMODE,COUNTMODE" "0,1" bitfld.long 0x4 22. "PRELOAD,PRELOAD" "0,1" bitfld.long 0x4 21. "WAVPOL,WAVPOL" "0,1" bitfld.long 0x4 20. "WAVE,WAVE" "0,1" bitfld.long 0x4 19. "TIMOUT,TIMOUT" "0,1" bitfld.long 0x4 17.--18. "TRIGEN,TRIGEN" "0,1,2,3" bitfld.long 0x4 13.--15. "TRIGSEL,TRIGSEL" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 9.--11. "PRESC,PRESC" "0,1,2,3,4,5,6,7" bitfld.long 0x4 6.--7. "TRGFLT,TRGFLT" "0,1,2,3" bitfld.long 0x4 3.--4. "CKFLT,CKFLT" "0,1,2,3" bitfld.long 0x4 1.--2. "CKPOL,CKPOL" "0,1,2,3" bitfld.long 0x4 0. "CKSEL,CKSEL" "0,1" line.long 0x8 "LPTIM_CR,LPTIM control register" bitfld.long 0x8 4. "RSTARE,RSTARE" "0,1" bitfld.long 0x8 3. "COUNTRST,COUNTRST" "0,1" bitfld.long 0x8 2. "CNTSTRT,CNTSTRT" "0,1" bitfld.long 0x8 1. "SNGSTRT,SNGSTRT" "0,1" bitfld.long 0x8 0. "ENABLE,ENABLE" "0,1" line.long 0xC "LPTIM_CMP,LPTIM compare register" hexmask.long.word 0xC 0.--15. 1. "CMP,CMP" line.long 0x10 "LPTIM_ARR,LPTIM autoreload register" hexmask.long.word 0x10 0.--15. 1. "ARR,ARR" rgroup.long 0x1C++0x3 line.long 0x0 "LPTIM_CNT,LPTIM counter register" hexmask.long.word 0x0 0.--15. 1. "CNT,CNT" group.long 0x24++0x3 line.long 0x0 "LPTIM_CFGR2,LPTIM configuration register 2" bitfld.long 0x0 4.--5. "IN2SEL,IN2SEL" "0,1,2,3" bitfld.long 0x0 0.--1. "IN1SEL,IN1SEL" "0,1,2,3" rgroup.long 0x3F0++0xF line.long 0x0 "LPTIM1_HWCFGR,LPTIM 1 peripheral hardware configuration register" hexmask.long.byte 0x0 24.--31. 1. "CFG4,CFG4" hexmask.long.byte 0x0 16.--19. 1. "CFG3,CFG3" hexmask.long.byte 0x0 8.--15. 1. "CFG2,CFG2" hexmask.long.byte 0x0 0.--7. 1. "CFG1,CFG1" line.long 0x4 "LPTIM_VERR,LPTIM peripheral version identification register" hexmask.long.byte 0x4 4.--7. 1. "MAJREV,MAJREV" hexmask.long.byte 0x4 0.--3. 1. "MINREV,MINREV" line.long 0x8 "LPTIM_PIDR,LPTIM peripheral type identification register" hexmask.long 0x8 0.--31. 1. "P_ID,P_ID" line.long 0xC "LPTIM_SIDR,LPTIM registers map size identification register" hexmask.long 0xC 0.--31. 1. "S_ID,S_ID" tree.end endif sif (cpuis("STM32MP151*")||cpuis("STM32MP153*")||cpuis("STM32MP157*")) tree "LPTIM3" base ad:0x50022000 rgroup.long 0x0++0x3 line.long 0x0 "LPTIM_ISR,LPTIM interrupt and status register" bitfld.long 0x0 6. "DOWN,DOWN" "0,1" bitfld.long 0x0 5. "UP,UP" "0,1" bitfld.long 0x0 4. "ARROK,ARROK" "0,1" bitfld.long 0x0 3. "CMPOK,CMPOK" "0,1" bitfld.long 0x0 2. "EXTTRIG,EXTTRIG" "0,1" bitfld.long 0x0 1. "ARRM,ARRM" "0,1" bitfld.long 0x0 0. "CMPM,CMPM" "0,1" wgroup.long 0x4++0x3 line.long 0x0 "LPTIM_ICR,LPTIM interrupt clear register" bitfld.long 0x0 6. "DOWNCF,DOWNCF" "0,1" bitfld.long 0x0 5. "UPCF,UPCF" "0,1" bitfld.long 0x0 4. "ARROKCF,ARROKCF" "0,1" bitfld.long 0x0 3. "CMPOKCF,CMPOKCF" "0,1" bitfld.long 0x0 2. "EXTTRIGCF,EXTTRIGCF" "0,1" bitfld.long 0x0 1. "ARRMCF,ARRMCF" "0,1" bitfld.long 0x0 0. "CMPMCF,CMPMCF" "0,1" group.long 0x8++0x13 line.long 0x0 "LPTIM_IER,LPTIM interrupt enable register" bitfld.long 0x0 6. "DOWNIE,DOWNIE" "0,1" bitfld.long 0x0 5. "UPIE,UPIE" "0,1" bitfld.long 0x0 4. "ARROKIE,ARROKIE" "0,1" bitfld.long 0x0 3. "CMPOKIE,CMPOKIE" "0,1" bitfld.long 0x0 2. "EXTTRIGIE,EXTTRIGIE" "0,1" bitfld.long 0x0 1. "ARRMIE,ARRMIE" "0,1" bitfld.long 0x0 0. "CMPMIE,CMPMIE" "0,1" line.long 0x4 "LPTIM_CFGR,LPTIM configuration register" bitfld.long 0x4 24. "ENC,ENC" "0,1" bitfld.long 0x4 23. "COUNTMODE,COUNTMODE" "0,1" bitfld.long 0x4 22. "PRELOAD,PRELOAD" "0,1" bitfld.long 0x4 21. "WAVPOL,WAVPOL" "0,1" bitfld.long 0x4 20. "WAVE,WAVE" "0,1" bitfld.long 0x4 19. "TIMOUT,TIMOUT" "0,1" bitfld.long 0x4 17.--18. "TRIGEN,TRIGEN" "0,1,2,3" bitfld.long 0x4 13.--15. "TRIGSEL,TRIGSEL" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 9.--11. "PRESC,PRESC" "0,1,2,3,4,5,6,7" bitfld.long 0x4 6.--7. "TRGFLT,TRGFLT" "0,1,2,3" bitfld.long 0x4 3.--4. "CKFLT,CKFLT" "0,1,2,3" bitfld.long 0x4 1.--2. "CKPOL,CKPOL" "0,1,2,3" bitfld.long 0x4 0. "CKSEL,CKSEL" "0,1" line.long 0x8 "LPTIM_CR,LPTIM control register" bitfld.long 0x8 4. "RSTARE,RSTARE" "0,1" bitfld.long 0x8 3. "COUNTRST,COUNTRST" "0,1" bitfld.long 0x8 2. "CNTSTRT,CNTSTRT" "0,1" bitfld.long 0x8 1. "SNGSTRT,SNGSTRT" "0,1" bitfld.long 0x8 0. "ENABLE,ENABLE" "0,1" line.long 0xC "LPTIM_CMP,LPTIM compare register" hexmask.long.word 0xC 0.--15. 1. "CMP,CMP" line.long 0x10 "LPTIM_ARR,LPTIM autoreload register" hexmask.long.word 0x10 0.--15. 1. "ARR,ARR" rgroup.long 0x1C++0x3 line.long 0x0 "LPTIM_CNT,LPTIM counter register" hexmask.long.word 0x0 0.--15. 1. "CNT,CNT" group.long 0x24++0x3 line.long 0x0 "LPTIM_CFGR2,LPTIM configuration register 2" bitfld.long 0x0 4.--5. "IN2SEL,IN2SEL" "0,1,2,3" bitfld.long 0x0 0.--1. "IN1SEL,IN1SEL" "0,1,2,3" rgroup.long 0x3F0++0xF line.long 0x0 "LPTIM1_HWCFGR,LPTIM 1 peripheral hardware configuration register" hexmask.long.byte 0x0 24.--31. 1. "CFG4,CFG4" hexmask.long.byte 0x0 16.--19. 1. "CFG3,CFG3" hexmask.long.byte 0x0 8.--15. 1. "CFG2,CFG2" hexmask.long.byte 0x0 0.--7. 1. "CFG1,CFG1" line.long 0x4 "LPTIM_VERR,LPTIM peripheral version identification register" hexmask.long.byte 0x4 4.--7. 1. "MAJREV,MAJREV" hexmask.long.byte 0x4 0.--3. 1. "MINREV,MINREV" line.long 0x8 "LPTIM_PIDR,LPTIM peripheral type identification register" hexmask.long 0x8 0.--31. 1. "P_ID,P_ID" line.long 0xC "LPTIM_SIDR,LPTIM registers map size identification register" hexmask.long 0xC 0.--31. 1. "S_ID,S_ID" tree.end endif sif (cpuis("STM32MP151*")||cpuis("STM32MP153*")||cpuis("STM32MP157*")) tree "LPTIM4" base ad:0x50023000 rgroup.long 0x0++0x3 line.long 0x0 "LPTIM_ISR,LPTIM interrupt and status register" bitfld.long 0x0 6. "DOWN,DOWN" "0,1" bitfld.long 0x0 5. "UP,UP" "0,1" bitfld.long 0x0 4. "ARROK,ARROK" "0,1" bitfld.long 0x0 3. "CMPOK,CMPOK" "0,1" bitfld.long 0x0 2. "EXTTRIG,EXTTRIG" "0,1" bitfld.long 0x0 1. "ARRM,ARRM" "0,1" bitfld.long 0x0 0. "CMPM,CMPM" "0,1" wgroup.long 0x4++0x3 line.long 0x0 "LPTIM_ICR,LPTIM interrupt clear register" bitfld.long 0x0 6. "DOWNCF,DOWNCF" "0,1" bitfld.long 0x0 5. "UPCF,UPCF" "0,1" bitfld.long 0x0 4. "ARROKCF,ARROKCF" "0,1" bitfld.long 0x0 3. "CMPOKCF,CMPOKCF" "0,1" bitfld.long 0x0 2. "EXTTRIGCF,EXTTRIGCF" "0,1" bitfld.long 0x0 1. "ARRMCF,ARRMCF" "0,1" bitfld.long 0x0 0. "CMPMCF,CMPMCF" "0,1" group.long 0x8++0x13 line.long 0x0 "LPTIM_IER,LPTIM interrupt enable register" bitfld.long 0x0 6. "DOWNIE,DOWNIE" "0,1" bitfld.long 0x0 5. "UPIE,UPIE" "0,1" bitfld.long 0x0 4. "ARROKIE,ARROKIE" "0,1" bitfld.long 0x0 3. "CMPOKIE,CMPOKIE" "0,1" bitfld.long 0x0 2. "EXTTRIGIE,EXTTRIGIE" "0,1" bitfld.long 0x0 1. "ARRMIE,ARRMIE" "0,1" bitfld.long 0x0 0. "CMPMIE,CMPMIE" "0,1" line.long 0x4 "LPTIM_CFGR,LPTIM configuration register" bitfld.long 0x4 24. "ENC,ENC" "0,1" bitfld.long 0x4 23. "COUNTMODE,COUNTMODE" "0,1" bitfld.long 0x4 22. "PRELOAD,PRELOAD" "0,1" bitfld.long 0x4 21. "WAVPOL,WAVPOL" "0,1" bitfld.long 0x4 20. "WAVE,WAVE" "0,1" bitfld.long 0x4 19. "TIMOUT,TIMOUT" "0,1" bitfld.long 0x4 17.--18. "TRIGEN,TRIGEN" "0,1,2,3" bitfld.long 0x4 13.--15. "TRIGSEL,TRIGSEL" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 9.--11. "PRESC,PRESC" "0,1,2,3,4,5,6,7" bitfld.long 0x4 6.--7. "TRGFLT,TRGFLT" "0,1,2,3" bitfld.long 0x4 3.--4. "CKFLT,CKFLT" "0,1,2,3" bitfld.long 0x4 1.--2. "CKPOL,CKPOL" "0,1,2,3" bitfld.long 0x4 0. "CKSEL,CKSEL" "0,1" line.long 0x8 "LPTIM_CR,LPTIM control register" bitfld.long 0x8 4. "RSTARE,RSTARE" "0,1" bitfld.long 0x8 3. "COUNTRST,COUNTRST" "0,1" bitfld.long 0x8 2. "CNTSTRT,CNTSTRT" "0,1" bitfld.long 0x8 1. "SNGSTRT,SNGSTRT" "0,1" bitfld.long 0x8 0. "ENABLE,ENABLE" "0,1" line.long 0xC "LPTIM_CMP,LPTIM compare register" hexmask.long.word 0xC 0.--15. 1. "CMP,CMP" line.long 0x10 "LPTIM_ARR,LPTIM autoreload register" hexmask.long.word 0x10 0.--15. 1. "ARR,ARR" rgroup.long 0x1C++0x3 line.long 0x0 "LPTIM_CNT,LPTIM counter register" hexmask.long.word 0x0 0.--15. 1. "CNT,CNT" group.long 0x24++0x3 line.long 0x0 "LPTIM_CFGR2,LPTIM configuration register 2" bitfld.long 0x0 4.--5. "IN2SEL,IN2SEL" "0,1,2,3" bitfld.long 0x0 0.--1. "IN1SEL,IN1SEL" "0,1,2,3" rgroup.long 0x3F0++0xF line.long 0x0 "LPTIM1_HWCFGR,LPTIM 1 peripheral hardware configuration register" hexmask.long.byte 0x0 24.--31. 1. "CFG4,CFG4" hexmask.long.byte 0x0 16.--19. 1. "CFG3,CFG3" hexmask.long.byte 0x0 8.--15. 1. "CFG2,CFG2" hexmask.long.byte 0x0 0.--7. 1. "CFG1,CFG1" line.long 0x4 "LPTIM_VERR,LPTIM peripheral version identification register" hexmask.long.byte 0x4 4.--7. 1. "MAJREV,MAJREV" hexmask.long.byte 0x4 0.--3. 1. "MINREV,MINREV" line.long 0x8 "LPTIM_PIDR,LPTIM peripheral type identification register" hexmask.long 0x8 0.--31. 1. "P_ID,P_ID" line.long 0xC "LPTIM_SIDR,LPTIM registers map size identification register" hexmask.long 0xC 0.--31. 1. "S_ID,S_ID" tree.end endif sif (cpuis("STM32MP151*")||cpuis("STM32MP153*")||cpuis("STM32MP157*")) tree "LPTIM5" base ad:0x50024000 rgroup.long 0x0++0x3 line.long 0x0 "LPTIM_ISR,LPTIM interrupt and status register" bitfld.long 0x0 6. "DOWN,DOWN" "0,1" bitfld.long 0x0 5. "UP,UP" "0,1" bitfld.long 0x0 4. "ARROK,ARROK" "0,1" bitfld.long 0x0 3. "CMPOK,CMPOK" "0,1" bitfld.long 0x0 2. "EXTTRIG,EXTTRIG" "0,1" bitfld.long 0x0 1. "ARRM,ARRM" "0,1" bitfld.long 0x0 0. "CMPM,CMPM" "0,1" wgroup.long 0x4++0x3 line.long 0x0 "LPTIM_ICR,LPTIM interrupt clear register" bitfld.long 0x0 6. "DOWNCF,DOWNCF" "0,1" bitfld.long 0x0 5. "UPCF,UPCF" "0,1" bitfld.long 0x0 4. "ARROKCF,ARROKCF" "0,1" bitfld.long 0x0 3. "CMPOKCF,CMPOKCF" "0,1" bitfld.long 0x0 2. "EXTTRIGCF,EXTTRIGCF" "0,1" bitfld.long 0x0 1. "ARRMCF,ARRMCF" "0,1" bitfld.long 0x0 0. "CMPMCF,CMPMCF" "0,1" group.long 0x8++0x13 line.long 0x0 "LPTIM_IER,LPTIM interrupt enable register" bitfld.long 0x0 6. "DOWNIE,DOWNIE" "0,1" bitfld.long 0x0 5. "UPIE,UPIE" "0,1" bitfld.long 0x0 4. "ARROKIE,ARROKIE" "0,1" bitfld.long 0x0 3. "CMPOKIE,CMPOKIE" "0,1" bitfld.long 0x0 2. "EXTTRIGIE,EXTTRIGIE" "0,1" bitfld.long 0x0 1. "ARRMIE,ARRMIE" "0,1" bitfld.long 0x0 0. "CMPMIE,CMPMIE" "0,1" line.long 0x4 "LPTIM_CFGR,LPTIM configuration register" bitfld.long 0x4 24. "ENC,ENC" "0,1" bitfld.long 0x4 23. "COUNTMODE,COUNTMODE" "0,1" bitfld.long 0x4 22. "PRELOAD,PRELOAD" "0,1" bitfld.long 0x4 21. "WAVPOL,WAVPOL" "0,1" bitfld.long 0x4 20. "WAVE,WAVE" "0,1" bitfld.long 0x4 19. "TIMOUT,TIMOUT" "0,1" bitfld.long 0x4 17.--18. "TRIGEN,TRIGEN" "0,1,2,3" bitfld.long 0x4 13.--15. "TRIGSEL,TRIGSEL" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 9.--11. "PRESC,PRESC" "0,1,2,3,4,5,6,7" bitfld.long 0x4 6.--7. "TRGFLT,TRGFLT" "0,1,2,3" bitfld.long 0x4 3.--4. "CKFLT,CKFLT" "0,1,2,3" bitfld.long 0x4 1.--2. "CKPOL,CKPOL" "0,1,2,3" bitfld.long 0x4 0. "CKSEL,CKSEL" "0,1" line.long 0x8 "LPTIM_CR,LPTIM control register" bitfld.long 0x8 4. "RSTARE,RSTARE" "0,1" bitfld.long 0x8 3. "COUNTRST,COUNTRST" "0,1" bitfld.long 0x8 2. "CNTSTRT,CNTSTRT" "0,1" bitfld.long 0x8 1. "SNGSTRT,SNGSTRT" "0,1" bitfld.long 0x8 0. "ENABLE,ENABLE" "0,1" line.long 0xC "LPTIM_CMP,LPTIM compare register" hexmask.long.word 0xC 0.--15. 1. "CMP,CMP" line.long 0x10 "LPTIM_ARR,LPTIM autoreload register" hexmask.long.word 0x10 0.--15. 1. "ARR,ARR" rgroup.long 0x1C++0x3 line.long 0x0 "LPTIM_CNT,LPTIM counter register" hexmask.long.word 0x0 0.--15. 1. "CNT,CNT" group.long 0x24++0x3 line.long 0x0 "LPTIM_CFGR2,LPTIM configuration register 2" bitfld.long 0x0 4.--5. "IN2SEL,IN2SEL" "0,1,2,3" bitfld.long 0x0 0.--1. "IN1SEL,IN1SEL" "0,1,2,3" rgroup.long 0x3F0++0xF line.long 0x0 "LPTIM1_HWCFGR,LPTIM 1 peripheral hardware configuration register" hexmask.long.byte 0x0 24.--31. 1. "CFG4,CFG4" hexmask.long.byte 0x0 16.--19. 1. "CFG3,CFG3" hexmask.long.byte 0x0 8.--15. 1. "CFG2,CFG2" hexmask.long.byte 0x0 0.--7. 1. "CFG1,CFG1" line.long 0x4 "LPTIM_VERR,LPTIM peripheral version identification register" hexmask.long.byte 0x4 4.--7. 1. "MAJREV,MAJREV" hexmask.long.byte 0x4 0.--3. 1. "MINREV,MINREV" line.long 0x8 "LPTIM_PIDR,LPTIM peripheral type identification register" hexmask.long 0x8 0.--31. 1. "P_ID,P_ID" line.long 0xC "LPTIM_SIDR,LPTIM registers map size identification register" hexmask.long 0xC 0.--31. 1. "S_ID,S_ID" tree.end endif tree.end tree "LTDC (LCD-TFT Display Controller)" base ad:0x5A001000 group.long 0x0++0x1B line.long 0x0 "LTDC_IDR,LTDC identification register" sif (cpuis("STM32MP13*")) hexmask.long.byte 0x0 16.--23. 1. "MAJVER,major version" hexmask.long.byte 0x0 8.--15. 1. "MINVER,minor version" newline hexmask.long.byte 0x0 0.--7. 1. "REV,revision" endif sif (cpuis("STM32MP151*")) hexmask.long.byte 0x0 16.--23. 1. "MAJVER,MAJVER" newline hexmask.long.byte 0x0 8.--15. 1. "MINVER,MINVER" hexmask.long.byte 0x0 0.--7. 1. "REV,REV" newline endif sif (cpuis("STM32MP153*")) hexmask.long.byte 0x0 16.--23. 1. "MAJVER,MAJVER" hexmask.long.byte 0x0 8.--15. 1. "MINVER,MINVER" newline hexmask.long.byte 0x0 0.--7. 1. "REV,REV" endif sif (cpuis("STM32MP157*")) hexmask.long.byte 0x0 16.--23. 1. "MAJVER,MAJVER" newline hexmask.long.byte 0x0 8.--15. 1. "MINVER,MINVER" hexmask.long.byte 0x0 0.--7. 1. "REV,REV" endif line.long 0x4 "LTDC_LCR,LDTC layer count register" sif (cpuis("STM32MP13*")) hexmask.long.byte 0x4 0.--7. 1. "LNBR,number of layers" endif sif (cpuis("STM32MP151*")) hexmask.long.byte 0x4 0.--7. 1. "LNBR,LNBR" newline endif sif (cpuis("STM32MP153*")) hexmask.long.byte 0x4 0.--7. 1. "LNBR,LNBR" endif sif (cpuis("STM32MP157*")) hexmask.long.byte 0x4 0.--7. 1. "LNBR,LNBR" endif line.long 0x8 "LTDC_SSCR,LTDC synchronization size configuration register" sif (cpuis("STM32MP13*")) hexmask.long.word 0x8 16.--31. 1. "HSW,horizontal synchronization width (in units of pixel clock period)" hexmask.long.word 0x8 0.--15. 1. "VSH,vertical synchronization height (in units of horizontal scan line)" newline endif sif (cpuis("STM32MP151*")) hexmask.long.word 0x8 16.--27. 1. "HSW,HSW" endif sif (cpuis("STM32MP153*")) hexmask.long.word 0x8 16.--27. 1. "HSW,HSW" newline endif sif (cpuis("STM32MP157*")) hexmask.long.word 0x8 16.--27. 1. "HSW,HSW" endif sif (cpuis("STM32MP151*")) hexmask.long.word 0x8 0.--11. 1. "VSH,VSH" newline endif sif (cpuis("STM32MP153*")) hexmask.long.word 0x8 0.--11. 1. "VSH,VSH" endif sif (cpuis("STM32MP157*")) hexmask.long.word 0x8 0.--11. 1. "VSH,VSH" endif line.long 0xC "LTDC_BPCR,LTDC back porch configuration register" sif (cpuis("STM32MP13*")) hexmask.long.word 0xC 16.--31. 1. "AHBP,accumulated horizontal back porch (in units of pixel clock period)" hexmask.long.word 0xC 0.--15. 1. "AVBP,accumulated Vertical back porch (in units of horizontal scan line)" newline endif sif (cpuis("STM32MP151*")) hexmask.long.word 0xC 16.--27. 1. "AHBP,AHBP" endif sif (cpuis("STM32MP153*")) hexmask.long.word 0xC 16.--27. 1. "AHBP,AHBP" newline endif sif (cpuis("STM32MP157*")) hexmask.long.word 0xC 16.--27. 1. "AHBP,AHBP" endif sif (cpuis("STM32MP151*")) hexmask.long.word 0xC 0.--11. 1. "AVBP,AVBP" newline endif sif (cpuis("STM32MP153*")) hexmask.long.word 0xC 0.--11. 1. "AVBP,AVBP" endif sif (cpuis("STM32MP157*")) hexmask.long.word 0xC 0.--11. 1. "AVBP,AVBP" endif line.long 0x10 "LTDC_AWCR,LTDC active width configuration register" sif (cpuis("STM32MP13*")) hexmask.long.word 0x10 16.--31. 1. "AAW,accumulated active width (in units of pixel clock period)" hexmask.long.word 0x10 0.--15. 1. "AAH,accumulated active height (in units of horizontal scan line)" newline endif sif (cpuis("STM32MP151*")) hexmask.long.word 0x10 16.--27. 1. "AAW,AAW" endif sif (cpuis("STM32MP153*")) hexmask.long.word 0x10 16.--27. 1. "AAW,AAW" newline endif sif (cpuis("STM32MP157*")) hexmask.long.word 0x10 16.--27. 1. "AAW,AAW" endif sif (cpuis("STM32MP151*")) hexmask.long.word 0x10 0.--11. 1. "AAH,AAH" newline endif sif (cpuis("STM32MP153*")) hexmask.long.word 0x10 0.--11. 1. "AAH,AAH" endif sif (cpuis("STM32MP157*")) hexmask.long.word 0x10 0.--11. 1. "AAH,AAH" endif line.long 0x14 "LTDC_TWCR,LTDC total width configuration register" sif (cpuis("STM32MP13*")) hexmask.long.word 0x14 16.--31. 1. "TOTALW,total width (in units of pixel clock period)" hexmask.long.word 0x14 0.--15. 1. "TOTALH,total height (in units of horizontal scan line)" newline endif sif (cpuis("STM32MP151*")) hexmask.long.word 0x14 16.--27. 1. "TOTALW,TOTALW" endif sif (cpuis("STM32MP153*")) hexmask.long.word 0x14 16.--27. 1. "TOTALW,TOTALW" newline endif sif (cpuis("STM32MP157*")) hexmask.long.word 0x14 16.--27. 1. "TOTALW,TOTALW" endif sif (cpuis("STM32MP151*")) hexmask.long.word 0x14 0.--11. 1. "TOTALH,TOTALH" newline endif sif (cpuis("STM32MP153*")) hexmask.long.word 0x14 0.--11. 1. "TOTALH,TOTALH" endif sif (cpuis("STM32MP157*")) hexmask.long.word 0x14 0.--11. 1. "TOTALH,TOTALH" endif line.long 0x18 "LTDC_GCR,LTDC global control register" sif (cpuis("STM32MP13*")) bitfld.long 0x18 31. "HSPOL,horizontal synchronization polarity" "0: horizontal synchronization polarity is active low.,1: horizontal synchronization polarity is active.." bitfld.long 0x18 30. "VSPOL,vertical synchronization polarity" "0: vertical synchronization is active low.,1: vertical synchronization is active high." newline bitfld.long 0x18 29. "DEPOL,blanking (no data/pixel) polarity" "0: blanking (no data/pixel) polarity is active low.,1: blanking (no data/pixel) polarity is active high." bitfld.long 0x18 28. "PCPOL,pixel clock polarity" "0: the pixel and sync data are generated at the..,1: the pixel and sync data are generated at the.." newline bitfld.long 0x18 25. "SFSWTR,single-frame mode: software trigger" "0: no action,1: triggers one frame" bitfld.long 0x18 24. "SFEN,single-frame mode: mode enable" "0: single-frame disabled: a trigger (on SFSWTR)..,1: single-frame enabled: a trigger (on SFSWTR).." newline bitfld.long 0x18 19. "CRCEN,CRC enable" "0: CRC disabled,1: CRC enabled" bitfld.long 0x18 16. "DEN,dither enable" "0: dither disabled,1: dither enabled" newline bitfld.long 0x18 1. "GAMEN,Gamma correction enable" "0: Gamma correction disabled (pixels bypass the..,1: Gamma correction enabled" bitfld.long 0x18 0. "LTDCEN,LTDC global enable" "0: LTDC disabled,1: LTDC enabled" newline endif sif (cpuis("STM32MP151*")) bitfld.long 0x18 31. "HSPOL,HSPOL" "0,1" bitfld.long 0x18 30. "VSPOL,VSPOL" "0,1" newline bitfld.long 0x18 29. "DEPOL,DEPOL" "0,1" bitfld.long 0x18 28. "PCPOL,PCPOL" "0,1" newline endif sif (cpuis("STM32MP153*")) bitfld.long 0x18 31. "HSPOL,HSPOL" "0,1" bitfld.long 0x18 30. "VSPOL,VSPOL" "0,1" newline bitfld.long 0x18 29. "DEPOL,DEPOL" "0,1" bitfld.long 0x18 28. "PCPOL,PCPOL" "0,1" newline endif sif (cpuis("STM32MP157*")) bitfld.long 0x18 31. "HSPOL,HSPOL" "0,1" bitfld.long 0x18 30. "VSPOL,VSPOL" "0,1" newline bitfld.long 0x18 29. "DEPOL,DEPOL" "0,1" bitfld.long 0x18 28. "PCPOL,PCPOL" "0,1" newline endif sif (cpuis("STM32MP151*")) bitfld.long 0x18 16. "DEN,DEN" "0,1" endif sif (cpuis("STM32MP153*")) bitfld.long 0x18 16. "DEN,DEN" "0,1" newline endif sif (cpuis("STM32MP157*")) bitfld.long 0x18 16. "DEN,DEN" "0,1" endif rbitfld.long 0x18 12.--14. "DRW,dither red width" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x18 8.--10. "DGW,dither green width" "0,1,2,3,4,5,6,7" rbitfld.long 0x18 4.--6. "DBW,dither blue width" "0,1,2,3,4,5,6,7" newline sif (cpuis("STM32MP153*")) bitfld.long 0x18 0. "LTDCEN,LTDCEN" "0,1" endif sif (cpuis("STM32MP157*")) bitfld.long 0x18 0. "LTDCEN,LTDCEN" "0,1" endif rgroup.long 0x1C++0x3 line.long 0x0 "LTDC_GC1R,LTDC global configuration 1 register" sif (cpuis("STM32MP13*")) bitfld.long 0x0 31. "BMA,blind mode ability" "0,1" bitfld.long 0x0 30. "CRMA,configuration reading mode ability" "0,1" newline bitfld.long 0x0 29. "STRA,status register ability" "0,1" bitfld.long 0x0 28. "DWP,dither width programmability" "0,1" newline bitfld.long 0x0 27. "SPP,sync polarity programmability" "0,1" bitfld.long 0x0 25. "TP,timing programmability" "0,1" newline bitfld.long 0x0 24. "LNIP,line-IRQ: line position programmability" "0,1" bitfld.long 0x0 23. "BBA,background blending ability" "0,1" newline bitfld.long 0x0 22. "BCP,background color programmability (unique color blended as background)" "0,1" bitfld.long 0x0 21. "SHRA,shadow registers ability" "0,1" newline bitfld.long 0x0 17.--19. "GCT,gamma correction technique implemented" "0: no gamma,1: gamma with 256 samples,2: gamma with 8 interpolated segments,?,?,?,?,?" bitfld.long 0x0 14.--15. "DT,dithering technique implemented" "0: no dithering,1: ordered 4x4 Bayer,?,3: pseudo-random LFSR" newline bitfld.long 0x0 12. "PRBA,precise blending ability" "0,1" hexmask.long.byte 0x0 8.--11. 1. "WRCH,width of red channel output" newline hexmask.long.byte 0x0 4.--7. 1. "WGCH,width of green channel output" hexmask.long.byte 0x0 0.--3. 1. "WBCH,width of blue channel output" newline endif sif (cpuis("STM32MP151*")) bitfld.long 0x0 31. "BMEN,BMEN" "0,1" endif sif (cpuis("STM32MP153*")) bitfld.long 0x0 31. "BMEN,BMEN" "0,1" newline endif sif (cpuis("STM32MP157*")) bitfld.long 0x0 31. "BMEN,BMEN" "0,1" endif sif (cpuis("STM32MP151*")) bitfld.long 0x0 29. "STREN,STREN" "0,1" newline bitfld.long 0x0 28. "DWP,DWP" "0,1" bitfld.long 0x0 27. "SPP,SPP" "0,1" newline bitfld.long 0x0 26. "IPP,IPP" "0,1" bitfld.long 0x0 25. "TP,TP" "0,1" newline bitfld.long 0x0 24. "LNIP,LNIP" "0,1" bitfld.long 0x0 23. "BBEN,BBEN" "0,1" newline bitfld.long 0x0 22. "BCP,BCP" "0,1" bitfld.long 0x0 21. "SHREN,SHREN" "0,1" newline endif sif (cpuis("STM32MP153*")) bitfld.long 0x0 29. "STREN,STREN" "0,1" bitfld.long 0x0 28. "DWP,DWP" "0,1" newline bitfld.long 0x0 27. "SPP,SPP" "0,1" bitfld.long 0x0 26. "IPP,IPP" "0,1" newline bitfld.long 0x0 25. "TP,TP" "0,1" bitfld.long 0x0 24. "LNIP,LNIP" "0,1" newline bitfld.long 0x0 23. "BBEN,BBEN" "0,1" bitfld.long 0x0 22. "BCP,BCP" "0,1" newline bitfld.long 0x0 21. "SHREN,SHREN" "0,1" endif sif (cpuis("STM32MP157*")) bitfld.long 0x0 29. "STREN,STREN" "0,1" newline bitfld.long 0x0 28. "DWP,DWP" "0,1" bitfld.long 0x0 27. "SPP,SPP" "0,1" newline bitfld.long 0x0 26. "IPP,IPP" "0,1" bitfld.long 0x0 25. "TP,TP" "0,1" newline bitfld.long 0x0 24. "LNIP,LNIP" "0,1" bitfld.long 0x0 23. "BBEN,BBEN" "0,1" newline bitfld.long 0x0 22. "BCP,BCP" "0,1" bitfld.long 0x0 21. "SHREN,SHREN" "0,1" newline endif sif (cpuis("STM32MP151*")) bitfld.long 0x0 17.--19. "GCT,GCT" "0,1,2,3,4,5,6,7" endif sif (cpuis("STM32MP153*")) bitfld.long 0x0 17.--19. "GCT,GCT" "0,1,2,3,4,5,6,7" newline endif sif (cpuis("STM32MP157*")) bitfld.long 0x0 17.--19. "GCT,GCT" "0,1,2,3,4,5,6,7" endif sif (cpuis("STM32MP151*")) bitfld.long 0x0 14.--15. "DT,DT" "0,1,2,3" newline endif sif (cpuis("STM32MP153*")) bitfld.long 0x0 14.--15. "DT,DT" "0,1,2,3" endif sif (cpuis("STM32MP157*")) bitfld.long 0x0 14.--15. "DT,DT" "0,1,2,3" newline endif sif (cpuis("STM32MP151*")) bitfld.long 0x0 12. "PRBEN,PRBEN" "0,1" hexmask.long.byte 0x0 8.--11. 1. "WRCH,WRCH" newline hexmask.long.byte 0x0 4.--7. 1. "WGCH,WGCH" hexmask.long.byte 0x0 0.--3. 1. "WBCH,WBCH" newline endif sif (cpuis("STM32MP153*")) bitfld.long 0x0 12. "PRBEN,PRBEN" "0,1" hexmask.long.byte 0x0 8.--11. 1. "WRCH,WRCH" newline hexmask.long.byte 0x0 4.--7. 1. "WGCH,WGCH" hexmask.long.byte 0x0 0.--3. 1. "WBCH,WBCH" newline endif sif (cpuis("STM32MP157*")) bitfld.long 0x0 12. "PRBEN,PRBEN" "0,1" hexmask.long.byte 0x0 8.--11. 1. "WRCH,WRCH" newline hexmask.long.byte 0x0 4.--7. 1. "WGCH,WGCH" hexmask.long.byte 0x0 0.--3. 1. "WBCH,WBCH" endif group.long 0x20++0x7 line.long 0x0 "LTDC_GC2R,LTDC global configuration 2 register" sif (cpuis("STM32MP13*")) rbitfld.long 0x0 15. "BOA,blending order ability" "0: blending order fixed,1: blending order configurable" rbitfld.long 0x0 13. "CRCA,CRC ability" "0: CRC no computation available,1: CRC computation available" newline rbitfld.long 0x0 12. "SFA,single frame mode ability" "0: single frame not available,1: single frame available" rbitfld.long 0x0 11. "SISA,second interrupt set ability" "0: second interrupt set not available,1: second interrupt set available" newline rbitfld.long 0x0 10. "ROTA,rotation support ability" "0,1" rbitfld.long 0x0 9. "AXIIDA,AXIID ability" "0,1" newline rbitfld.long 0x0 8. "OCA,output conversion ability (RGB to YCbCr)" "0,1" rbitfld.long 0x0 7. "EDCA,external display control ability" "0,1" newline rbitfld.long 0x0 4.--6. "BW,bus width (log2 of number of bytes)" "?,?,2: 32-bit bus,3: 64-bit bus,4: 128-bit bus,?,?,?" rbitfld.long 0x0 3. "DPA,secondary RGB output port ability" "0,1" newline rbitfld.long 0x0 2. "DVA,dual-view ability" "0,1" rbitfld.long 0x0 1. "STSA,slave timings synchronization ability" "0,1" newline rbitfld.long 0x0 0. "BLA,background layer ability (pixels of background layer are read from memory)" "0,1" endif sif (cpuis("STM32MP151*")) bitfld.long 0x0 7. "EDCA,EDCA" "0,1" newline bitfld.long 0x0 4.--6. "BW,BW" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "DPAEN,DPAEN" "0,1" newline bitfld.long 0x0 2. "DVAEN,DVAEN" "0,1" bitfld.long 0x0 1. "STSAEN,STSAEN" "0,1" newline bitfld.long 0x0 0. "EDCEN,EDCEN" "0,1" endif sif (cpuis("STM32MP153*")) bitfld.long 0x0 7. "EDCA,EDCA" "0,1" newline bitfld.long 0x0 4.--6. "BW,BW" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "DPAEN,DPAEN" "0,1" newline bitfld.long 0x0 2. "DVAEN,DVAEN" "0,1" bitfld.long 0x0 1. "STSAEN,STSAEN" "0,1" newline bitfld.long 0x0 0. "EDCEN,EDCEN" "0,1" endif sif (cpuis("STM32MP157*")) bitfld.long 0x0 7. "EDCA,EDCA" "0,1" newline bitfld.long 0x0 4.--6. "BW,BW" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "DPAEN,DPAEN" "0,1" newline bitfld.long 0x0 2. "DVAEN,DVAEN" "0,1" bitfld.long 0x0 1. "STSAEN,STSAEN" "0,1" newline bitfld.long 0x0 0. "EDCEN,EDCEN" "0,1" endif line.long 0x4 "LTDC_SRCR,LTDC shadow reload configuration register" sif (cpuis("STM32MP13*")) bitfld.long 0x4 1. "VBR,vertical blanking reload request" "0: no effect,1: The shadow registers are reloaded during the.." bitfld.long 0x4 0. "IMR,immediate reload trigger" "0: no effect,1: The shadow registers are reloaded immediately." newline endif sif (cpuis("STM32MP151*")) bitfld.long 0x4 1. "VBR,VBR" "0,1" endif sif (cpuis("STM32MP153*")) bitfld.long 0x4 1. "VBR,VBR" "0,1" newline bitfld.long 0x4 0. "IMR,IMR" "0,1" endif sif (cpuis("STM32MP157*")) bitfld.long 0x4 1. "VBR,VBR" "0,1" newline bitfld.long 0x4 0. "IMR,IMR" "0,1" endif group.long 0x2C++0x3 line.long 0x0 "LTDC_BCCR,LTDC background color configuration register" hexmask.long.byte 0x0 16.--23. 1. "BCRED,background color red value" hexmask.long.byte 0x0 8.--15. 1. "BCGREEN,background color green value" newline hexmask.long.byte 0x0 0.--7. 1. "BCBLUE,background color blue value" group.long 0x34++0x13 line.long 0x0 "LTDC_IER,LTDC interrupt enable register" sif (cpuis("STM32MP13*")) bitfld.long 0x0 7. "CRCIE,CRC error interrupt enable" "0: CRC error disabled,1: CRC error interrupt enabled" bitfld.long 0x0 6. "FUIE,FIFO underrun interrupt enable" "0: FIFO underrun interrupt disabled,1: FIFO underrun Interrupt enabled" newline bitfld.long 0x0 3. "RRIE,Register reload interrupt enable" "0: register reload interrupt disabled,1: register reload interrupt enabled" bitfld.long 0x0 2. "TERRIE,Transfer Error interrupt enable" "0: transfer error interrupt disabled,1: transfer error interrupt enabled" newline bitfld.long 0x0 1. "FUWIE,FIFO underrun warning interrupt enable" "0: FIFO underrun interrupt disabled,1: FIFO underrun Interrupt enabled" bitfld.long 0x0 0. "LIE,Line interrupt enable" "0: line interrupt disabled,1: line interrupt enabled" newline endif sif (cpuis("STM32MP151*")) bitfld.long 0x0 3. "RRIE,RRIE" "0,1" bitfld.long 0x0 2. "TERRIE,TERRIE" "0,1" newline bitfld.long 0x0 1. "FUIE,FUIE" "0,1" endif sif (cpuis("STM32MP153*")) bitfld.long 0x0 3. "RRIE,RRIE" "0,1" newline bitfld.long 0x0 2. "TERRIE,TERRIE" "0,1" bitfld.long 0x0 1. "FUIE,FUIE" "0,1" newline bitfld.long 0x0 0. "LIE,LIE" "0,1" endif sif (cpuis("STM32MP157*")) bitfld.long 0x0 3. "RRIE,RRIE" "0,1" newline bitfld.long 0x0 2. "TERRIE,TERRIE" "0,1" bitfld.long 0x0 1. "FUIE,FUIE" "0,1" newline bitfld.long 0x0 0. "LIE,LIE" "0,1" endif line.long 0x4 "LTDC_ISR,LTDC interrupt status register" sif (cpuis("STM32MP13*")) rbitfld.long 0x4 7. "CRCIF,CRC error interrupt flag" "0: no CRC error interrupt generated,1: CRC error interrupt generated when a bus error.." rbitfld.long 0x4 6. "FUIF,FIFO underrun interrupt flag" "0: no FIFO underrun interrupt generated,1: FIFO underrun interrupt generated if one of the.." newline rbitfld.long 0x4 3. "RRIF,Register reload interrupt flag" "0: no register reload interrupt generated,1: register reload interrupt generated when a.." rbitfld.long 0x4 2. "TERRIF,Transfer error interrupt flag" "0: no transfer error interrupt generated,1: transfer error interrupt generated when a bus.." newline rbitfld.long 0x4 1. "FUWIF,FIFO underrun warning interrupt flag" "0: no FIFO underrun warning interrupt generated,1: FIFO underrun warning interrupt generated if one.." rbitfld.long 0x4 0. "LIF,Line interrupt flag" "0: no line interrupt generated,1: line interrupt generated when a programmed line.." newline endif sif (cpuis("STM32MP151*")) bitfld.long 0x4 3. "RRIF,RRIF" "0,1" bitfld.long 0x4 2. "TERRIF,TERRIF" "0,1" newline bitfld.long 0x4 1. "FUIF,FUIF" "0,1" bitfld.long 0x4 0. "LIF,LIF" "0,1" newline endif sif (cpuis("STM32MP153*")) bitfld.long 0x4 3. "RRIF,RRIF" "0,1" bitfld.long 0x4 2. "TERRIF,TERRIF" "0,1" newline bitfld.long 0x4 1. "FUIF,FUIF" "0,1" bitfld.long 0x4 0. "LIF,LIF" "0,1" newline endif sif (cpuis("STM32MP157*")) bitfld.long 0x4 3. "RRIF,RRIF" "0,1" bitfld.long 0x4 2. "TERRIF,TERRIF" "0,1" newline bitfld.long 0x4 1. "FUIF,FUIF" "0,1" bitfld.long 0x4 0. "LIF,LIF" "0,1" endif line.long 0x8 "LTDC_ICR,LTDC interrupt clear register" sif (cpuis("STM32MP13*")) bitfld.long 0x8 7. "CCRCIF,clears the CRC error interrupt flag" "0: no effect,1: clears the CRCIF flag in LTDC_ISR." bitfld.long 0x8 6. "CFUIF,clears the FIFO underrun interrupt flag" "0: no effect,1: clears the FUIF flag in LTDC_ISR." newline bitfld.long 0x8 3. "CRRIF,clears register reload interrupt flag" "0: no effect,1: clears the RRIF flag in LTDC_ISR." bitfld.long 0x8 2. "CTERRIF,clears the transfer error interrupt flag" "0: no effect,1: clears the TERRIF flag in LTDC_ISR." newline bitfld.long 0x8 1. "CFUWIF,clears the FIFO underrun warning interrupt flag" "0: no effect,1: clears the FUWIF flag in LTDC_ISR." bitfld.long 0x8 0. "CLIF,clears the line interrupt flag" "0: no effect,1: clears the LIF flag in LTDC_ISR." newline endif sif (cpuis("STM32MP151*")) bitfld.long 0x8 3. "CRRIF,CRRIF" "0,1" bitfld.long 0x8 2. "CTERRIF,CTERRIF" "0,1" newline bitfld.long 0x8 1. "CFUIF,CFUIF" "0,1" bitfld.long 0x8 0. "CLIF,CLIF" "0,1" newline endif sif (cpuis("STM32MP153*")) bitfld.long 0x8 3. "CRRIF,CRRIF" "0,1" bitfld.long 0x8 2. "CTERRIF,CTERRIF" "0,1" newline bitfld.long 0x8 1. "CFUIF,CFUIF" "0,1" bitfld.long 0x8 0. "CLIF,CLIF" "0,1" newline endif sif (cpuis("STM32MP157*")) bitfld.long 0x8 3. "CRRIF,CRRIF" "0,1" bitfld.long 0x8 2. "CTERRIF,CTERRIF" "0,1" newline bitfld.long 0x8 1. "CFUIF,CFUIF" "0,1" bitfld.long 0x8 0. "CLIF,CLIF" "0,1" endif line.long 0xC "LTDC_LIPCR,LTDC line interrupt position configuration register" sif (cpuis("STM32MP13*")) hexmask.long.word 0xC 0.--15. 1. "LIPOS,line interrupt position" endif sif (cpuis("STM32MP151*")) hexmask.long.word 0xC 0.--11. 1. "LIPOS,LIPOS" newline endif sif (cpuis("STM32MP153*")) hexmask.long.word 0xC 0.--11. 1. "LIPOS,LIPOS" endif sif (cpuis("STM32MP157*")) hexmask.long.word 0xC 0.--11. 1. "LIPOS,LIPOS" endif line.long 0x10 "LTDC_CPSR,LTDC current position status register" sif (cpuis("STM32MP13*")) hexmask.long.word 0x10 16.--31. 1. "CXPOS,current X position" hexmask.long.word 0x10 0.--15. 1. "CYPOS,current Y position" newline endif sif (cpuis("STM32MP151*")) hexmask.long.word 0x10 16.--31. 1. "CXPOS,CXPOS" hexmask.long.word 0x10 0.--15. 1. "CYPOS,CYPOS" newline endif sif (cpuis("STM32MP153*")) hexmask.long.word 0x10 16.--31. 1. "CXPOS,CXPOS" hexmask.long.word 0x10 0.--15. 1. "CYPOS,CYPOS" newline endif sif (cpuis("STM32MP157*")) hexmask.long.word 0x10 16.--31. 1. "CXPOS,CXPOS" hexmask.long.word 0x10 0.--15. 1. "CYPOS,CYPOS" endif rgroup.long 0x48++0x3 line.long 0x0 "LTDC_CDSR,LTDC current display status register" sif (cpuis("STM32MP13*")) bitfld.long 0x0 3. "HSYNCS,horizontal synchronization display status" "0: active low,1: active high" bitfld.long 0x0 2. "VSYNCS,vertical synchronization display status" "0: active low,1: active high" newline bitfld.long 0x0 1. "HDES,horizontal data enable display status" "0: active low,1: active high" bitfld.long 0x0 0. "VDES,vertical data enable display status" "0: active low,1: active high" newline endif sif (cpuis("STM32MP151*")) bitfld.long 0x0 3. "HSYNCS,HSYNCS" "0,1" bitfld.long 0x0 2. "VSYNCS,VSYNCS" "0,1" newline bitfld.long 0x0 1. "HDES,HDES" "0,1" bitfld.long 0x0 0. "VDES,VDES" "0,1" newline endif sif (cpuis("STM32MP153*")) bitfld.long 0x0 3. "HSYNCS,HSYNCS" "0,1" bitfld.long 0x0 2. "VSYNCS,VSYNCS" "0,1" newline bitfld.long 0x0 1. "HDES,HDES" "0,1" bitfld.long 0x0 0. "VDES,VDES" "0,1" newline endif sif (cpuis("STM32MP157*")) bitfld.long 0x0 3. "HSYNCS,HSYNCS" "0,1" bitfld.long 0x0 2. "VSYNCS,VSYNCS" "0,1" newline bitfld.long 0x0 1. "HDES,HDES" "0,1" bitfld.long 0x0 0. "VDES,VDES" "0,1" endif sif (cpuis("STM32MP13*")) wgroup.long 0x28++0x3 line.long 0x0 "LTDC_GCCR,LTDC gamma correction configuration register" bitfld.long 0x0 18. "REN,write trigger to the red table" "0: no action done,1: COMP is written at ADDR in the red table." bitfld.long 0x0 17. "GEN,write trigger to the green table" "0: no action done,1: COMP is written at ADDR in the green table." newline bitfld.long 0x0 16. "BEN,write trigger to the blue table" "0: no action done,1: COMP is written at ADDR in the blue table." hexmask.long.byte 0x0 8.--15. 1. "COMP,color component to be written in either (or all) the R G B tables" newline hexmask.long.byte 0x0 0.--7. 1. "ADDR,address of the R G B table where the COMP component is written" group.long 0x60++0x7 line.long 0x0 "LTDC_EDCR,LTDC external display control register" bitfld.long 0x0 27. "OCYCO,output conversion to YCbCr 422" "0: Cb is output first (Y0Cb then Y1Cr Y2Cb and so..,1: Cr is output first (Y0Cr then Y1Cb Y2Cr and so.." bitfld.long 0x0 26. "OCYSEL,output conversion to YCbCr 422" "0: use ITU-R BT.601 set (for typically SDTV..,1: use ITU-R BT.709 set (for typically HDTV.." newline bitfld.long 0x0 25. "OCYEN,output conversion to YCbCr 422 enable" "0: conversion disabled,1: conversion enabled" line.long 0x4 "LTDC_IER2,LTDC interrupt enable register 2" bitfld.long 0x4 7. "CRCIE,CRC error interrupt enable" "0: CRC error disabled,1: CRC error interrupt enabled" bitfld.long 0x4 6. "FUIE,FIFO underrun interrupt enable" "0: FIFO underrun interrupt disabled,1: FIFO underrun Interrupt enabled" newline bitfld.long 0x4 3. "RRIE,Register reload interrupt enable" "0: register reload interrupt disabled,1: register reload interrupt enabled" bitfld.long 0x4 2. "TERRIE,Transfer error interrupt enable" "0: transfer error interrupt disabled,1: transfer error interrupt enabled" newline bitfld.long 0x4 1. "FUWIE,FIFO underrun warning interrupt enable" "0: FIFO underrun interrupt disabled,1: FIFO underrun Interrupt enabled" bitfld.long 0x4 0. "LIE,Line interrupt enable" "0: line interrupt disabled,1: line interrupt enabled" rgroup.long 0x68++0x3 line.long 0x0 "LTDC_ISR2,LTDC interrupt status register 2" bitfld.long 0x0 7. "CRCIF,CRC Error interrupt flag" "0: no CRC error interrupt generated,1: CRC error interrupt generated when a bus error.." bitfld.long 0x0 6. "FUIF,FIFO underrun interrupt flag" "0: no FIFO underrun interrupt generated.,1: FIFO underrun interrupt generated if one of the.." newline bitfld.long 0x0 3. "RRIF,Register reload interrupt flag" "0: no register reload interrupt generated,1: register reload interrupt generated when a.." bitfld.long 0x0 2. "TERRIF,Transfer error interrupt flag" "0: no transfer error interrupt generated,1: transfer error interrupt generated when a bus.." newline bitfld.long 0x0 1. "FUWIF,FIFO underrun warning interrupt flag" "0: no FIFO underrun warning interrupt generated.,1: FIFO underrun warning interrupt generated if one.." bitfld.long 0x0 0. "LIF,Line interrupt flag" "0: no line interrupt generated,1: line interrupt generated when a programmed line.." wgroup.long 0x6C++0x3 line.long 0x0 "LTDC_ICR2,LTDC interrupt clear register 2" bitfld.long 0x0 7. "CCRCIF,clears the CRC error interrupt flag" "0: no effect,1: clears the CRCIF flag in LTDC_ISR2." bitfld.long 0x0 6. "CFUIF,clears the FIFO underrun interrupt flag" "0: no effect,1: clears the FUIF flag in LTDC_ISR2." newline bitfld.long 0x0 3. "CRRIF,clears register reload interrupt flag" "0: no effect,1: clears the RRIF flag in LTDC_ISR2." bitfld.long 0x0 2. "CTERRIF,clears the Transfer Error interrupt flag" "0: no effect,1: clears the TERRIF flag in LTDC_ISR2." newline bitfld.long 0x0 1. "CFUWIF,clears the FIFO underrun warning interrupt flag" "0: no effect,1: clears the FUWIF flag in LTDC_ISR2." bitfld.long 0x0 0. "CLIF,clears the Line interrupt flag" "0: no effect,1: clears the LIF flag in LTDC_ISR2." group.long 0x70++0x3 line.long 0x0 "LTDC_LIPCR2,LTDC line interrupt position configuration register 2" hexmask.long.word 0x0 0.--15. 1. "LIPOS,line interrupt position" group.long 0x78++0x3 line.long 0x0 "LTDC_ECRCR,LTDC expected CRC register" hexmask.long.word 0x0 0.--15. 1. "ECRC,expected CRC of frame" rgroup.long 0x7C++0x3 line.long 0x0 "LTDC_CCRCR,LTDC computed CRC register" hexmask.long.word 0x0 0.--15. 1. "CCRC,computed CRC of frame" group.long 0x90++0x3 line.long 0x0 "LTDC_FUTR,LTDC FIFO underrun threshold register" hexmask.long.word 0x0 0.--15. 1. "THRE,threshold to trigger a FIFO underrun interrupt (per FIFO word 64 bits)" rgroup.long 0x100++0x3 line.long 0x0 "LTDC_L1C0R,LTDC Layerx configuration 0 register" bitfld.long 0x0 31. "ARGB8888,pixel format ability for argb8888" "0,1" bitfld.long 0x0 30. "ABGR8888,pixel format ability for abgr8888" "0,1" newline bitfld.long 0x0 29. "RGBA8888,pixel format ability for rgba8888" "0,1" bitfld.long 0x0 28. "BGRA888,pixel format ability for bgra8888" "0,1" newline bitfld.long 0x0 27. "RGB565,pixel format ability for rgb565" "0,1" bitfld.long 0x0 26. "BGR565,pixel format ability for bgr565" "0,1" newline bitfld.long 0x0 25. "RGB888,pixel format ability for rgb888" "0,1" bitfld.long 0x0 24. "FF,flexible pixel format ability" "0,1" newline bitfld.long 0x0 23. "F11PC,blending factor 1 ability for: 1.0 - (pixel_alpha * constant_alpha)" "0,1" bitfld.long 0x0 22. "F1PC,blending factor 1 ability for: pixel_alpha * constant_alpha" "0,1" newline bitfld.long 0x0 21. "F11C,blending factor 1 ability for: 1.0 - constant_alpha" "0,1" bitfld.long 0x0 20. "F1C,blending factor 1 ability for: constant_alpha" "0,1" newline bitfld.long 0x0 19. "F11P,blending factor 1 ability for: 1.0 - pixel_alpha" "0,1" bitfld.long 0x0 18. "F1P,blending factor 1 ability for: pixel_alpha" "0,1" newline bitfld.long 0x0 17. "F10,blending factor 1 ability for: 0.0" "0,1" bitfld.long 0x0 16. "F11,blending factor 1 ability for: 1.0" "0,1" newline bitfld.long 0x0 15. "F21PC,blending factor 2 ability for: 1.0 - (pixel_alpha * constant_alpha)" "0,1" bitfld.long 0x0 14. "F2PC,blending factor 2 ability for: pixel_alpha * constant_alpha" "0,1" newline bitfld.long 0x0 13. "F21C,blending factor 2 ability for: 1.0 - constant_alpha" "0,1" bitfld.long 0x0 12. "F2C,blending factor 2 ability for: constant_alpha" "0,1" newline bitfld.long 0x0 11. "F21P,blending factor 2 ability for: 1.0 - pixel_alpha" "0,1" bitfld.long 0x0 10. "F2P,blending factor 2 ability for: pixel_alpha" "0,1" newline bitfld.long 0x0 9. "F20,blending factor 2 ability for: 0.0" "0,1" bitfld.long 0x0 8. "F21,blending factor 2 ability for: 1.0" "0,1" newline bitfld.long 0x0 7. "CKRA,color key replace ability" "0,1" bitfld.long 0x0 6. "CLUTA,CLUT ability" "0,1" newline bitfld.long 0x0 5. "WINA,windowing ability" "0,1" bitfld.long 0x0 4. "DCP,default color programmability" "0,1" newline bitfld.long 0x0 3. "APA,alpha plane ability" "0,1" bitfld.long 0x0 2. "CFBPA,color frame buffer pitch ability" "0,1" newline bitfld.long 0x0 1. "CFBDA,color frame buffer duplication ability" "0,1" bitfld.long 0x0 0. "CKTA,color key transparency ability" "0,1" group.long 0x104++0x4B line.long 0x0 "LTDC_L1C1R,LTDC Layerx configuration 1 register" bitfld.long 0x0 31. "SCA,scaling ability for that layer" "0: scaling not available,1: scaling available" bitfld.long 0x0 2. "YFPA,YCbCr 420 full-planar ability for that layer" "0: full planar not available,1: full planar available" newline bitfld.long 0x0 1. "YSPA,YCbCr 420 semi-planar ability for that layer" "0: semi-planar not available,1: semi-planar available" bitfld.long 0x0 0. "YIA,YCbCr 422 interleaved ability for that layer" "0: interleaved not available,1: interleaved available" line.long 0x4 "LTDC_L1RCR,LTDC Layerx reload control register" bitfld.long 0x4 2. "GRMSK,shadow reload control global (centralized) reload masked" "0: global reload active for this layer (control..,1: global reload masked for this layer (control.." bitfld.long 0x4 1. "VBR,vertical blanking reload request" "0: no effect,1: The shadow registers are reloaded during the.." newline bitfld.long 0x4 0. "IMR,immediate reload trigger" "0: no effect,1: The shadow registers are reloaded immediately." line.long 0x8 "LTDC_L1CR,LTDC Layerx control register" bitfld.long 0x8 9. "DCBEN,default color blending enable" "0: blending disabled,1: blending enabled" bitfld.long 0x8 8. "HMEN,horizontal mirroring enable" "0: mirror disabled,1: mirror enabled (if so the color frame buffer.." newline bitfld.long 0x8 4. "CLUTEN,color look-up table enable" "0: color look-up table disabled,1: color look-up table enabled" bitfld.long 0x8 1. "CKEN,color keying enable" "0: color keying disabled,1: color keying enabled: if RGB matches then the.." newline bitfld.long 0x8 0. "LEN,layer enable: the bit is used to enable/disable the presence of this whole layer." "0: layer disabled,1: layer enabled" line.long 0xC "LTDC_L1WHPCR,LTDC Layerx window horizontal position configuration register" hexmask.long.word 0xC 16.--31. 1. "WHSPPOS,window horizontal stop position" hexmask.long.word 0xC 0.--15. 1. "WHSTPOS,window horizontal start position" line.long 0x10 "LTDC_L1WVPCR,LTDC Layerx window vertical position configuration register" hexmask.long.word 0x10 16.--31. 1. "WVSPPOS,window vertical stop position" hexmask.long.word 0x10 0.--15. 1. "WVSTPOS,window vertical start position" line.long 0x14 "LTDC_L1CKCR,LTDC Layerx color keying configuration register" hexmask.long.byte 0x14 16.--23. 1. "CKRED,color key red value" hexmask.long.byte 0x14 8.--15. 1. "CKGREEN,color key green value" newline hexmask.long.byte 0x14 0.--7. 1. "CKBLUE,color key blue value" line.long 0x18 "LTDC_L1PFCR,LTDC Layerx pixel format configuration register" bitfld.long 0x18 0.--2. "PF,pixel format" "0: ARGB8888 (32 bpp),1: ABGR888 (32 bpp),2: RGBA888 (32 bpp),3: BGRA8888 (32 bpp),4: RGB565 (16 bpp A = 255),5: BGR565 (16 bpp A = 255),6: RGB888 (24 bpp packed A = 255),7: Flexible pixel format selected (see Section.." line.long 0x1C "LTDC_L1CACR,LTDC Layerx constant alpha configuration register" hexmask.long.byte 0x1C 0.--7. 1. "CONSTA,constant alpha" line.long 0x20 "LTDC_L1DCCR,LTDC Layerx default color configuration register" hexmask.long.byte 0x20 24.--31. 1. "DCALPHA,default color alpha" hexmask.long.byte 0x20 16.--23. 1. "DCRED,default color red" newline hexmask.long.byte 0x20 8.--15. 1. "DCGREEN,default color green" hexmask.long.byte 0x20 0.--7. 1. "DCBLUE,default color blue" line.long 0x24 "LTDC_L1BFCR,LTDC Layerx blending factors configuration register" bitfld.long 0x24 16. "BOR,blending order" "0: layer set in background,1: layer set in foreground" bitfld.long 0x24 8.--10. "BF1,blending factor 1" "?,?,?,?,4: constant alpha,?,6: pixel alpha x constant alpha,?" newline bitfld.long 0x24 0.--2. "BF2,blending factor 2" "?,?,?,?,?,5: 1 - constant alpha,?,7: 1 - (pixel alpha x constant alpha)" line.long 0x28 "LTDC_L1BLCR,LTDC Layerx burst length configuration register" hexmask.long.byte 0x28 0.--7. 1. "BL,burst length" line.long 0x2C "LTDC_L1PCR,LTDC Layerx planar configuration register" bitfld.long 0x2C 9. "YREN,Y rescale enable for the color dynamic range" "0: rescaling disabled (input component thus assumed..,1: rescaling enabled (input component thus assumed.." bitfld.long 0x2C 8. "OF,Odd pixel first" "0: odd pixel disabled (thus even pixel on byte 0),1: odd pixel enabled (thus odd pixel on byte 0)" newline bitfld.long 0x2C 7. "CBF,Cb component first" "0: Cb disabled (thus Cr component is on byte 0 and 1),1: Cb enabled (thus Cb component is on byte 0 and 1)" bitfld.long 0x2C 6. "YF,Y component first" "0: Y component disabled (thus Cr or Cb component is..,1: Y component enabled (thus Y component is on byte.." newline bitfld.long 0x2C 4.--5. "YCM,YCbCr conversion mode" "0: interleaved 422 (Cb and Cr component are..,1: semi-Planar 420: (Cb and Cr component are..,2: full-Planar 420: (Cb and Cr component are..,?" bitfld.long 0x2C 3. "YCEN,YCbCr-to-RGB conversion enable" "0: conversion disabled,1: YCbCr conversion enabled using the YCM setting.." line.long 0x30 "LTDC_L1CFBAR,LTDC Layerx color frame buffer address register" hexmask.long 0x30 0.--31. 1. "CFBADD,color frame buffer start address" line.long 0x34 "LTDC_L1CFBLR,LTDC Layerx color frame buffer length register" hexmask.long.word 0x34 16.--31. 1. "CFBP,color frame buffer pitch in bytes" hexmask.long.word 0x34 0.--15. 1. "CFBLL,color frame buffer line length" line.long 0x38 "LTDC_L1CFBLNR,LTDC Layerx color frame buffer line number register" hexmask.long.word 0x38 0.--15. 1. "CFBLNBR,frame buffer line number" line.long 0x3C "LTDC_L1AFBA0R,LTDC Layer1 auxiliary frame buffer address 0 register" hexmask.long 0x3C 0.--31. 1. "AFBADD0,frame buffer start address" line.long 0x40 "LTDC_L1AFBA1R,LTDC Layer1 auxiliary frame buffer address 1 register" hexmask.long 0x40 0.--31. 1. "AFBADD1,auxiliary frame buffer start address" line.long 0x44 "LTDC_L1AFBLR,LTDC Layer1 auxiliary frame buffer length register" hexmask.long.word 0x44 16.--31. 1. "AFBP,auxiliary frame buffer pitch in bytes" hexmask.long.word 0x44 0.--15. 1. "AFBLL,auxiliary frame buffer line length" line.long 0x48 "LTDC_L1AFBLNR,LTDC Layer1 auxiliary frame buffer line number register" hexmask.long.word 0x48 0.--15. 1. "AFBLNBR,auxiliary frame buffer line number" wgroup.long 0x150++0x3 line.long 0x0 "LTDC_L1CLUTWR,LTDC Layerx CLUT write register" hexmask.long.byte 0x0 24.--31. 1. "CLUTADD,CLUT address" hexmask.long.byte 0x0 16.--23. 1. "RED,red value" newline hexmask.long.byte 0x0 8.--15. 1. "GREEN,green value" hexmask.long.byte 0x0 0.--7. 1. "BLUE,blue value" group.long 0x16C++0xF line.long 0x0 "LTDC_L1CYR0R,LTDC Layerx conversion YCbCr RGB 0 register" hexmask.long.word 0x0 16.--25. 1. "CB2B,Cb-to-Blue coefficient with bits 9:8 as positive integer and 7:0 as decimals." hexmask.long.word 0x0 0.--9. 1. "CR2R,Cr-to-Red coefficient with bits 9:8 as positive integer and 7:0 as decimals." line.long 0x4 "LTDC_L1CYR1R,LTDC Layerx conversion YCbCr RGB 1 register" hexmask.long.word 0x4 16.--25. 1. "CB2G,Cb-to-Green coefficient with bits 9:8 as positive integer and 7:0 as decimals." hexmask.long.word 0x4 0.--9. 1. "CR2G,Cr-to-Green coefficient with bits 9:8 as positive integer and 7:0 as decimals." line.long 0x8 "LTDC_L1FPF0R,LTDC Layerx flexible pixel format 0 register" hexmask.long.byte 0x8 14.--17. 1. "RLEN,Width of the Red component (in bits)" hexmask.long.byte 0x8 9.--13. 1. "RPOS,Location of the Red component inside the pixel memory word (in bits)" newline hexmask.long.byte 0x8 5.--8. 1. "ALEN,Width of the Alpha component (in bits)" hexmask.long.byte 0x8 0.--4. 1. "APOS,Location of the Alpha component inside the pixel memory word (in bits)" line.long 0xC "LTDC_L1FPF1R,LTDC Layerx flexible pixel format 1 register" bitfld.long 0xC 18.--20. "PSIZE,Pixel Size (in Bytes)." "0,1,2,3,4,5,6,7" hexmask.long.byte 0xC 14.--17. 1. "BLEN,Width of the Blue Component (in bits)." newline hexmask.long.byte 0xC 9.--13. 1. "BPOS,Location of the Blue Component inside the Pixel Memory Word (in bits)." hexmask.long.byte 0xC 5.--8. 1. "GLEN,Width of the Green Component (in bits)." newline hexmask.long.byte 0xC 0.--4. 1. "GPOS,Location of the Green Component inside the Pixel Memory Word (in bits)." rgroup.long 0x200++0x3 line.long 0x0 "LTDC_L2C0R,LTDC Layerx configuration 0 register" bitfld.long 0x0 31. "ARGB8888,pixel format ability for argb8888" "0,1" bitfld.long 0x0 30. "ABGR8888,pixel format ability for abgr8888" "0,1" newline bitfld.long 0x0 29. "RGBA8888,pixel format ability for rgba8888" "0,1" bitfld.long 0x0 28. "BGRA888,pixel format ability for bgra8888" "0,1" newline bitfld.long 0x0 27. "RGB565,pixel format ability for rgb565" "0,1" bitfld.long 0x0 26. "BGR565,pixel format ability for bgr565" "0,1" newline bitfld.long 0x0 25. "RGB888,pixel format ability for rgb888" "0,1" bitfld.long 0x0 24. "FF,flexible pixel format ability" "0,1" newline bitfld.long 0x0 23. "F11PC,blending factor 1 ability for: 1.0 - (pixel_alpha * constant_alpha)" "0,1" bitfld.long 0x0 22. "F1PC,blending factor 1 ability for: pixel_alpha * constant_alpha" "0,1" newline bitfld.long 0x0 21. "F11C,blending factor 1 ability for: 1.0 - constant_alpha" "0,1" bitfld.long 0x0 20. "F1C,blending factor 1 ability for: constant_alpha" "0,1" newline bitfld.long 0x0 19. "F11P,blending factor 1 ability for: 1.0 - pixel_alpha" "0,1" bitfld.long 0x0 18. "F1P,blending factor 1 ability for: pixel_alpha" "0,1" newline bitfld.long 0x0 17. "F10,blending factor 1 ability for: 0.0" "0,1" bitfld.long 0x0 16. "F11,blending factor 1 ability for: 1.0" "0,1" newline bitfld.long 0x0 15. "F21PC,blending factor 2 ability for: 1.0 - (pixel_alpha * constant_alpha)" "0,1" bitfld.long 0x0 14. "F2PC,blending factor 2 ability for: pixel_alpha * constant_alpha" "0,1" newline bitfld.long 0x0 13. "F21C,blending factor 2 ability for: 1.0 - constant_alpha" "0,1" bitfld.long 0x0 12. "F2C,blending factor 2 ability for: constant_alpha" "0,1" newline bitfld.long 0x0 11. "F21P,blending factor 2 ability for: 1.0 - pixel_alpha" "0,1" bitfld.long 0x0 10. "F2P,blending factor 2 ability for: pixel_alpha" "0,1" newline bitfld.long 0x0 9. "F20,blending factor 2 ability for: 0.0" "0,1" bitfld.long 0x0 8. "F21,blending factor 2 ability for: 1.0" "0,1" newline bitfld.long 0x0 7. "CKRA,color key replace ability" "0,1" bitfld.long 0x0 6. "CLUTA,CLUT ability" "0,1" newline bitfld.long 0x0 5. "WINA,windowing ability" "0,1" bitfld.long 0x0 4. "DCP,default color programmability" "0,1" newline bitfld.long 0x0 3. "APA,alpha plane ability" "0,1" bitfld.long 0x0 2. "CFBPA,color frame buffer pitch ability" "0,1" newline bitfld.long 0x0 1. "CFBDA,color frame buffer duplication ability" "0,1" bitfld.long 0x0 0. "CKTA,color key transparency ability" "0,1" group.long 0x204++0x3B line.long 0x0 "LTDC_L2C1R,LTDC Layerx configuration 1 register" bitfld.long 0x0 31. "SCA,scaling ability for that layer" "0: scaling not available,1: scaling available" bitfld.long 0x0 2. "YFPA,YCbCr 420 full-planar ability for that layer" "0: full planar not available,1: full planar available" newline bitfld.long 0x0 1. "YSPA,YCbCr 420 semi-planar ability for that layer" "0: semi-planar not available,1: semi-planar available" bitfld.long 0x0 0. "YIA,YCbCr 422 interleaved ability for that layer" "0: interleaved not available,1: interleaved available" line.long 0x4 "LTDC_L2RCR,LTDC Layerx reload control register" bitfld.long 0x4 2. "GRMSK,shadow reload control global (centralized) reload masked" "0: global reload active for this layer (control..,1: global reload masked for this layer (control.." bitfld.long 0x4 1. "VBR,vertical blanking reload request" "0: no effect,1: The shadow registers are reloaded during the.." newline bitfld.long 0x4 0. "IMR,immediate reload trigger" "0: no effect,1: The shadow registers are reloaded immediately." line.long 0x8 "LTDC_L2CR,LTDC Layerx control register" bitfld.long 0x8 9. "DCBEN,default color blending enable" "0: blending disabled,1: blending enabled" bitfld.long 0x8 8. "HMEN,horizontal mirroring enable" "0: mirror disabled,1: mirror enabled (if so the color frame buffer.." newline bitfld.long 0x8 4. "CLUTEN,color look-up table enable" "0: color look-up table disabled,1: color look-up table enabled" bitfld.long 0x8 1. "CKEN,color keying enable" "0: color keying disabled,1: color keying enabled: if RGB matches then the.." newline bitfld.long 0x8 0. "LEN,layer enable: the bit is used to enable/disable the presence of this whole layer." "0: layer disabled,1: layer enabled" line.long 0xC "LTDC_L2WHPCR,LTDC Layerx window horizontal position configuration register" hexmask.long.word 0xC 16.--31. 1. "WHSPPOS,window horizontal stop position" hexmask.long.word 0xC 0.--15. 1. "WHSTPOS,window horizontal start position" line.long 0x10 "LTDC_L2WVPCR,LTDC Layerx window vertical position configuration register" hexmask.long.word 0x10 16.--31. 1. "WVSPPOS,window vertical stop position" hexmask.long.word 0x10 0.--15. 1. "WVSTPOS,window vertical start position" line.long 0x14 "LTDC_L2CKCR,LTDC Layerx color keying configuration register" hexmask.long.byte 0x14 16.--23. 1. "CKRED,color key red value" hexmask.long.byte 0x14 8.--15. 1. "CKGREEN,color key green value" newline hexmask.long.byte 0x14 0.--7. 1. "CKBLUE,color key blue value" line.long 0x18 "LTDC_L2PFCR,LTDC Layerx pixel format configuration register" bitfld.long 0x18 0.--2. "PF,pixel format" "0: ARGB8888 (32 bpp),1: ABGR888 (32 bpp),2: RGBA888 (32 bpp),3: BGRA8888 (32 bpp),4: RGB565 (16 bpp A = 255),5: BGR565 (16 bpp A = 255),6: RGB888 (24 bpp packed A = 255),7: Flexible pixel format selected (see Section.." line.long 0x1C "LTDC_L2CACR,LTDC Layerx constant alpha configuration register" hexmask.long.byte 0x1C 0.--7. 1. "CONSTA,constant alpha" line.long 0x20 "LTDC_L2DCCR,LTDC Layerx default color configuration register" hexmask.long.byte 0x20 24.--31. 1. "DCALPHA,default color alpha" hexmask.long.byte 0x20 16.--23. 1. "DCRED,default color red" newline hexmask.long.byte 0x20 8.--15. 1. "DCGREEN,default color green" hexmask.long.byte 0x20 0.--7. 1. "DCBLUE,default color blue" line.long 0x24 "LTDC_L2BFCR,LTDC Layerx blending factors configuration register" bitfld.long 0x24 16. "BOR,blending order" "0: layer set in background,1: layer set in foreground" bitfld.long 0x24 8.--10. "BF1,blending factor 1" "?,?,?,?,4: constant alpha,?,6: pixel alpha x constant alpha,?" newline bitfld.long 0x24 0.--2. "BF2,blending factor 2" "?,?,?,?,?,5: 1 - constant alpha,?,7: 1 - (pixel alpha x constant alpha)" line.long 0x28 "LTDC_L2BLCR,LTDC Layerx burst length configuration register" hexmask.long.byte 0x28 0.--7. 1. "BL,burst length" line.long 0x2C "LTDC_L2PCR,LTDC Layerx planar configuration register" bitfld.long 0x2C 9. "YREN,Y rescale enable for the color dynamic range" "0: rescaling disabled (input component thus assumed..,1: rescaling enabled (input component thus assumed.." bitfld.long 0x2C 8. "OF,Odd pixel first" "0: odd pixel disabled (thus even pixel on byte 0),1: odd pixel enabled (thus odd pixel on byte 0)" newline bitfld.long 0x2C 7. "CBF,Cb component first" "0: Cb disabled (thus Cr component is on byte 0 and 1),1: Cb enabled (thus Cb component is on byte 0 and 1)" bitfld.long 0x2C 6. "YF,Y component first" "0: Y component disabled (thus Cr or Cb component is..,1: Y component enabled (thus Y component is on byte.." newline bitfld.long 0x2C 4.--5. "YCM,YCbCr conversion mode" "0: interleaved 422 (Cb and Cr component are..,1: semi-Planar 420: (Cb and Cr component are..,2: full-Planar 420: (Cb and Cr component are..,?" bitfld.long 0x2C 3. "YCEN,YCbCr-to-RGB conversion enable" "0: conversion disabled,1: YCbCr conversion enabled using the YCM setting.." line.long 0x30 "LTDC_L2CFBAR,LTDC Layerx color frame buffer address register" hexmask.long 0x30 0.--31. 1. "CFBADD,color frame buffer start address" line.long 0x34 "LTDC_L2CFBLR,LTDC Layerx color frame buffer length register" hexmask.long.word 0x34 16.--31. 1. "CFBP,color frame buffer pitch in bytes" hexmask.long.word 0x34 0.--15. 1. "CFBLL,color frame buffer line length" line.long 0x38 "LTDC_L2CFBLNR,LTDC Layerx color frame buffer line number register" hexmask.long.word 0x38 0.--15. 1. "CFBLNBR,frame buffer line number" wgroup.long 0x250++0x3 line.long 0x0 "LTDC_L2CLUTWR,LTDC Layerx CLUT write register" hexmask.long.byte 0x0 24.--31. 1. "CLUTADD,CLUT address" hexmask.long.byte 0x0 16.--23. 1. "RED,red value" newline hexmask.long.byte 0x0 8.--15. 1. "GREEN,green value" hexmask.long.byte 0x0 0.--7. 1. "BLUE,blue value" group.long 0x26C++0xF line.long 0x0 "LTDC_L2CYR0R,LTDC Layerx conversion YCbCr RGB 0 register" hexmask.long.word 0x0 16.--25. 1. "CB2B,Cb-to-Blue coefficient with bits 9:8 as positive integer and 7:0 as decimals." hexmask.long.word 0x0 0.--9. 1. "CR2R,Cr-to-Red coefficient with bits 9:8 as positive integer and 7:0 as decimals." line.long 0x4 "LTDC_L2CYR1R,LTDC Layerx conversion YCbCr RGB 1 register" hexmask.long.word 0x4 16.--25. 1. "CB2G,Cb-to-Green coefficient with bits 9:8 as positive integer and 7:0 as decimals." hexmask.long.word 0x4 0.--9. 1. "CR2G,Cr-to-Green coefficient with bits 9:8 as positive integer and 7:0 as decimals." line.long 0x8 "LTDC_L2FPF0R,LTDC Layerx flexible pixel format 0 register" hexmask.long.byte 0x8 14.--17. 1. "RLEN,Width of the Red component (in bits)" hexmask.long.byte 0x8 9.--13. 1. "RPOS,Location of the Red component inside the pixel memory word (in bits)" newline hexmask.long.byte 0x8 5.--8. 1. "ALEN,Width of the Alpha component (in bits)" hexmask.long.byte 0x8 0.--4. 1. "APOS,Location of the Alpha component inside the pixel memory word (in bits)" line.long 0xC "LTDC_L2FPF1R,LTDC Layerx flexible pixel format 1 register" bitfld.long 0xC 18.--20. "PSIZE,Pixel Size (in Bytes)." "0,1,2,3,4,5,6,7" hexmask.long.byte 0xC 14.--17. 1. "BLEN,Width of the Blue Component (in bits)." newline hexmask.long.byte 0xC 9.--13. 1. "BPOS,Location of the Blue Component inside the Pixel Memory Word (in bits)." hexmask.long.byte 0xC 5.--8. 1. "GLEN,Width of the Green Component (in bits)." newline hexmask.long.byte 0xC 0.--4. 1. "GPOS,Location of the Green Component inside the Pixel Memory Word (in bits)." group.long 0x378++0x3 line.long 0x0 "LTDC_L3FPF1R,LTDC Layerx flexible pixel format 1 register" bitfld.long 0x0 18.--20. "PSIZE,Pixel Size (in Bytes)." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 14.--17. 1. "BLEN,Width of the Blue Component (in bits)." newline hexmask.long.byte 0x0 9.--13. 1. "BPOS,Location of the Blue Component inside the Pixel Memory Word (in bits)." hexmask.long.byte 0x0 5.--8. 1. "GLEN,Width of the Green Component (in bits)." newline hexmask.long.byte 0x0 0.--4. 1. "GPOS,Location of the Green Component inside the Pixel Memory Word (in bits)." endif sif (cpuis("STM32MP151*")) rgroup.long 0x0++0x3 line.long 0x0 "LTDC_IDR,LTDC identification register" endif sif (cpuis("STM32MP151*")) rgroup.long 0x4++0x3 line.long 0x0 "LTDC_LCR,LDTC layer count register" endif sif (cpuis("STM32MP151*")) rgroup.long 0x1C++0x3 line.long 0x0 "LTDC_GC1R,LTDC global configuration 1 register" endif sif (cpuis("STM32MP151*")) rgroup.long 0x20++0x3 line.long 0x0 "LTDC_GC2R,LTDC global configuration 2 register" endif sif (cpuis("STM32MP151*")) rgroup.long 0x38++0x3 line.long 0x0 "LTDC_ISR,This register returns the interrupt status flag." endif sif (cpuis("STM32MP151*")) wgroup.long 0x3C++0x3 line.long 0x0 "LTDC_ICR,LTDC Interrupt Clear Register" endif sif (cpuis("STM32MP151*")) rgroup.long 0x44++0x3 line.long 0x0 "LTDC_CPSR,LTDC current position status register" endif sif (cpuis("STM32MP151*")) rgroup.long 0x48++0x3 line.long 0x0 "LTDC_CDSR,This register returns the status of the current display phase which is controlled by the HSYNC. VSYNC. and horizontal/vertical DE signals. Example: if the current display phase is the vertical synchronization. the VSYNCS bit is set (active.." group.long 0x84++0x1F line.long 0x0 "LTDC_L1CR,LTDC layer 1 control register" bitfld.long 0x0 4. "CLUTEN,CLUTEN" "0,1" bitfld.long 0x0 1. "COLKEN,COLKEN" "0,1" newline bitfld.long 0x0 0. "LEN,LEN" "0,1" line.long 0x4 "LTDC_L1WHPCR,This register defines the horizontal position (first and last pixel) of the layer 1 or 2 window. The first visible pixel of a line is the programmed value of AHBP[11:0] bits + 1 in the LTDC_BPCR register. The last visible pixel of a line is.." hexmask.long.word 0x4 16.--27. 1. "WHSPPOS,WHSPPOS" hexmask.long.word 0x4 0.--11. 1. "WHSTPOS,WHSTPOS" line.long 0x8 "LTDC_L1WVPCR,This register defines the vertical position (first and last line) of the layer1 or 2 window. The first visible line of a frame is the programmed value of AVBP[11:0] bits + 1 in the register LTDC_BPCR register. The last visible line of a.." hexmask.long.word 0x8 16.--27. 1. "WVSPPOS,WVSPPOS" hexmask.long.word 0x8 0.--11. 1. "WVSTPOS,WVSTPOS" line.long 0xC "LTDC_L1CKCR,This register defines the color key value (RGB). that is used by the color keying." hexmask.long.byte 0xC 16.--23. 1. "CKRED,CKRED" hexmask.long.byte 0xC 8.--15. 1. "CKGREEN,CKGREEN" newline hexmask.long.byte 0xC 0.--7. 1. "CKBLUE,CKBLUE" line.long 0x10 "LTDC_L1PFCR,This register defines the pixel format that is used for the stored data in the frame buffer of a layer. The pixel data is read from the frame buffer and then transformed to the internal format 8888 (ARGB)." bitfld.long 0x10 0.--2. "PF,PF" "0,1,2,3,4,5,6,7" line.long 0x14 "LTDC_L1CACR,This register defines the constant alpha value (divided by 255 by hardware). that is used in the alpha blending. Refer to LTDC_LxBFCR register." hexmask.long.byte 0x14 0.--7. 1. "CONSTA,CONSTA" line.long 0x18 "LTDC_L1DCCR,This register defines the default color of a layer in the format ARGB. The default color is used outside the defined layer window or when a layer is disabled. The reset value of 0x00000000 defines a transparent black color." hexmask.long.byte 0x18 24.--31. 1. "DCALPHA,DCALPHA" hexmask.long.byte 0x18 16.--23. 1. "DCRED,DCRED" newline hexmask.long.byte 0x18 8.--15. 1. "DCGREEN,DCGREEN" hexmask.long.byte 0x18 0.--7. 1. "DCBLUE,DCBLUE" line.long 0x1C "LTDC_L1BFCR,This register defines the blending factors F1 and F2. The general blending formula is: BC = BF1 x C + BF2 x Cs BC = blended color BF1 = blend factor 1 C = current layer color BF2 = blend factor 2 Cs = subjacent layers blended color" bitfld.long 0x1C 8.--10. "BF1,BF1" "0,1,2,3,4,5,6,7" bitfld.long 0x1C 0.--2. "BF2,BF2" "0,1,2,3,4,5,6,7" group.long 0xAC++0xB line.long 0x0 "LTDC_L1CFBAR,This register defines the color frame buffer start address which has to point to the address where the pixel data of the top left pixel of a layer is stored in the frame buffer." hexmask.long 0x0 0.--31. 1. "CFBADD,CFBADD" line.long 0x4 "LTDC_L1CFBLR,This register defines the color frame buffer line length and pitch." hexmask.long.word 0x4 16.--29. 1. "CFBP,CFBP" hexmask.long.word 0x4 0.--13. 1. "CFBLL,CFBLL" line.long 0x8 "LTDC_L1CFBLNR,This register defines the number of lines in the color frame buffer." hexmask.long.word 0x8 0.--11. 1. "CFBLNBR,CFBLNBR" wgroup.long 0xC4++0x3 line.long 0x0 "LTDC_L1CLUTWR,This register defines the CLUT address and the RGB value." hexmask.long.byte 0x0 24.--31. 1. "CLUTADD,CLUTADD" hexmask.long.byte 0x0 16.--23. 1. "RED,RED" newline hexmask.long.byte 0x0 8.--15. 1. "GREEN,GREEN" hexmask.long.byte 0x0 0.--7. 1. "BLUE,BLUE" group.long 0x104++0x1F line.long 0x0 "LTDC_L2CR,LTDC layer 2 control register" bitfld.long 0x0 4. "CLUTEN,CLUTEN" "0,1" bitfld.long 0x0 1. "COLKEN,COLKEN" "0,1" newline bitfld.long 0x0 0. "LEN,LEN" "0,1" line.long 0x4 "LTDC_L2WHPCR,This register defines the horizontal position (first and last pixel) of the layer 1 or 2 window. The first visible pixel of a line is the programmed value of AHBP[11:0] bits + 1 in the LTDC_BPCR register. The last visible pixel of a line is.." hexmask.long.word 0x4 16.--27. 1. "WHSPPOS,WHSPPOS" hexmask.long.word 0x4 0.--11. 1. "WHSTPOS,WHSTPOS" line.long 0x8 "LTDC_L2WVPCR,This register defines the vertical position (first and last line) of the layer1 or 2 window. The first visible line of a frame is the programmed value of AVBP[11:0] bits + 1 in the register LTDC_BPCR register. The last visible line of a.." hexmask.long.word 0x8 16.--27. 1. "WVSPPOS,WVSPPOS" hexmask.long.word 0x8 0.--11. 1. "WVSTPOS,WVSTPOS" line.long 0xC "LTDC_L2CKCR,This register defines the color key value (RGB). that is used by the color keying." hexmask.long.byte 0xC 16.--23. 1. "CKRED,CKRED" hexmask.long.byte 0xC 8.--15. 1. "CKGREEN,CKGREEN" newline hexmask.long.byte 0xC 0.--7. 1. "CKBLUE,CKBLUE" line.long 0x10 "LTDC_L2PFCR,This register defines the pixel format that is used for the stored data in the frame buffer of a layer. The pixel data is read from the frame buffer and then transformed to the internal format 8888 (ARGB)." bitfld.long 0x10 0.--2. "PF,PF" "0,1,2,3,4,5,6,7" line.long 0x14 "LTDC_L2CACR,This register defines the constant alpha value (divided by 255 by hardware). that is used in the alpha blending. Refer to LTDC_LxBFCR register." hexmask.long.byte 0x14 0.--7. 1. "CONSTA,CONSTA" line.long 0x18 "LTDC_L2DCCR,This register defines the default color of a layer in the format ARGB. The default color is used outside the defined layer window or when a layer is disabled. The reset value of 0x00000000 defines a transparent black color." hexmask.long.byte 0x18 24.--31. 1. "DCALPHA,DCALPHA" hexmask.long.byte 0x18 16.--23. 1. "DCRED,DCRED" newline hexmask.long.byte 0x18 8.--15. 1. "DCGREEN,DCGREEN" hexmask.long.byte 0x18 0.--7. 1. "DCBLUE,DCBLUE" line.long 0x1C "LTDC_L2BFCR,This register defines the blending factors F1 and F2. The general blending formula is: BC = BF1 x C + BF2 x Cs BC = blended color BF1 = blend factor 1 C = current layer color BF2 = blend factor 2 Cs = subjacent layers blended color" bitfld.long 0x1C 8.--10. "BF1,BF1" "0,1,2,3,4,5,6,7" bitfld.long 0x1C 0.--2. "BF2,BF2" "0,1,2,3,4,5,6,7" group.long 0x12C++0xB line.long 0x0 "LTDC_L2CFBAR,This register defines the color frame buffer start address which has to point to the address where the pixel data of the top left pixel of a layer is stored in the frame buffer." hexmask.long 0x0 0.--31. 1. "CFBADD,CFBADD" line.long 0x4 "LTDC_L2CFBLR,This register defines the color frame buffer line length and pitch." hexmask.long.word 0x4 16.--29. 1. "CFBP,CFBP" hexmask.long.word 0x4 0.--13. 1. "CFBLL,CFBLL" line.long 0x8 "LTDC_L2CFBLNR,This register defines the number of lines in the color frame buffer." hexmask.long.word 0x8 0.--11. 1. "CFBLNBR,CFBLNBR" wgroup.long 0x144++0x3 line.long 0x0 "LTDC_L2CLUTWR,This register defines the CLUT address and the RGB value." hexmask.long.byte 0x0 24.--31. 1. "CLUTADD,CLUTADD" hexmask.long.byte 0x0 16.--23. 1. "RED,RED" newline hexmask.long.byte 0x0 8.--15. 1. "GREEN,GREEN" hexmask.long.byte 0x0 0.--7. 1. "BLUE,BLUE" endif sif (cpuis("STM32MP153*")) rgroup.long 0x0++0x3 line.long 0x0 "LTDC_IDR,LTDC identification register" endif sif (cpuis("STM32MP153*")) rgroup.long 0x4++0x3 line.long 0x0 "LTDC_LCR,LDTC layer count register" endif sif (cpuis("STM32MP153*")) rgroup.long 0x1C++0x3 line.long 0x0 "LTDC_GC1R,LTDC global configuration 1 register" endif sif (cpuis("STM32MP153*")) rgroup.long 0x20++0x3 line.long 0x0 "LTDC_GC2R,LTDC global configuration 2 register" endif sif (cpuis("STM32MP153*")) rgroup.long 0x38++0x3 line.long 0x0 "LTDC_ISR,This register returns the interrupt status flag." endif sif (cpuis("STM32MP153*")) wgroup.long 0x3C++0x3 line.long 0x0 "LTDC_ICR,LTDC Interrupt Clear Register" endif sif (cpuis("STM32MP153*")) rgroup.long 0x44++0x3 line.long 0x0 "LTDC_CPSR,LTDC current position status register" endif sif (cpuis("STM32MP153*")) rgroup.long 0x48++0x3 line.long 0x0 "LTDC_CDSR,This register returns the status of the current display phase which is controlled by the HSYNC. VSYNC. and horizontal/vertical DE signals. Example: if the current display phase is the vertical synchronization. the VSYNCS bit is set (active.." group.long 0x84++0x1F line.long 0x0 "LTDC_L1CR,LTDC layer 1 control register" bitfld.long 0x0 4. "CLUTEN,CLUTEN" "0,1" bitfld.long 0x0 1. "COLKEN,COLKEN" "0,1" newline bitfld.long 0x0 0. "LEN,LEN" "0,1" line.long 0x4 "LTDC_L1WHPCR,This register defines the horizontal position (first and last pixel) of the layer 1 or 2 window. The first visible pixel of a line is the programmed value of AHBP[11:0] bits + 1 in the LTDC_BPCR register. The last visible pixel of a line is.." hexmask.long.word 0x4 16.--27. 1. "WHSPPOS,WHSPPOS" hexmask.long.word 0x4 0.--11. 1. "WHSTPOS,WHSTPOS" line.long 0x8 "LTDC_L1WVPCR,This register defines the vertical position (first and last line) of the layer1 or 2 window. The first visible line of a frame is the programmed value of AVBP[11:0] bits + 1 in the register LTDC_BPCR register. The last visible line of a.." hexmask.long.word 0x8 16.--27. 1. "WVSPPOS,WVSPPOS" hexmask.long.word 0x8 0.--11. 1. "WVSTPOS,WVSTPOS" line.long 0xC "LTDC_L1CKCR,This register defines the color key value (RGB). that is used by the color keying." hexmask.long.byte 0xC 16.--23. 1. "CKRED,CKRED" hexmask.long.byte 0xC 8.--15. 1. "CKGREEN,CKGREEN" newline hexmask.long.byte 0xC 0.--7. 1. "CKBLUE,CKBLUE" line.long 0x10 "LTDC_L1PFCR,This register defines the pixel format that is used for the stored data in the frame buffer of a layer. The pixel data is read from the frame buffer and then transformed to the internal format 8888 (ARGB)." bitfld.long 0x10 0.--2. "PF,PF" "0,1,2,3,4,5,6,7" line.long 0x14 "LTDC_L1CACR,This register defines the constant alpha value (divided by 255 by hardware). that is used in the alpha blending. Refer to LTDC_LxBFCR register." hexmask.long.byte 0x14 0.--7. 1. "CONSTA,CONSTA" line.long 0x18 "LTDC_L1DCCR,This register defines the default color of a layer in the format ARGB. The default color is used outside the defined layer window or when a layer is disabled. The reset value of 0x00000000 defines a transparent black color." hexmask.long.byte 0x18 24.--31. 1. "DCALPHA,DCALPHA" hexmask.long.byte 0x18 16.--23. 1. "DCRED,DCRED" newline hexmask.long.byte 0x18 8.--15. 1. "DCGREEN,DCGREEN" hexmask.long.byte 0x18 0.--7. 1. "DCBLUE,DCBLUE" line.long 0x1C "LTDC_L1BFCR,This register defines the blending factors F1 and F2. The general blending formula is: BC = BF1 x C + BF2 x Cs BC = blended color BF1 = blend factor 1 C = current layer color BF2 = blend factor 2 Cs = subjacent layers blended color" bitfld.long 0x1C 8.--10. "BF1,BF1" "0,1,2,3,4,5,6,7" bitfld.long 0x1C 0.--2. "BF2,BF2" "0,1,2,3,4,5,6,7" group.long 0xAC++0xB line.long 0x0 "LTDC_L1CFBAR,This register defines the color frame buffer start address which has to point to the address where the pixel data of the top left pixel of a layer is stored in the frame buffer." hexmask.long 0x0 0.--31. 1. "CFBADD,CFBADD" line.long 0x4 "LTDC_L1CFBLR,This register defines the color frame buffer line length and pitch." hexmask.long.word 0x4 16.--29. 1. "CFBP,CFBP" hexmask.long.word 0x4 0.--13. 1. "CFBLL,CFBLL" line.long 0x8 "LTDC_L1CFBLNR,This register defines the number of lines in the color frame buffer." hexmask.long.word 0x8 0.--11. 1. "CFBLNBR,CFBLNBR" wgroup.long 0xC4++0x3 line.long 0x0 "LTDC_L1CLUTWR,This register defines the CLUT address and the RGB value." hexmask.long.byte 0x0 24.--31. 1. "CLUTADD,CLUTADD" hexmask.long.byte 0x0 16.--23. 1. "RED,RED" newline hexmask.long.byte 0x0 8.--15. 1. "GREEN,GREEN" hexmask.long.byte 0x0 0.--7. 1. "BLUE,BLUE" group.long 0x104++0x1F line.long 0x0 "LTDC_L2CR,LTDC layer 2 control register" bitfld.long 0x0 4. "CLUTEN,CLUTEN" "0,1" bitfld.long 0x0 1. "COLKEN,COLKEN" "0,1" newline bitfld.long 0x0 0. "LEN,LEN" "0,1" line.long 0x4 "LTDC_L2WHPCR,This register defines the horizontal position (first and last pixel) of the layer 1 or 2 window. The first visible pixel of a line is the programmed value of AHBP[11:0] bits + 1 in the LTDC_BPCR register. The last visible pixel of a line is.." hexmask.long.word 0x4 16.--27. 1. "WHSPPOS,WHSPPOS" hexmask.long.word 0x4 0.--11. 1. "WHSTPOS,WHSTPOS" line.long 0x8 "LTDC_L2WVPCR,This register defines the vertical position (first and last line) of the layer1 or 2 window. The first visible line of a frame is the programmed value of AVBP[11:0] bits + 1 in the register LTDC_BPCR register. The last visible line of a.." hexmask.long.word 0x8 16.--27. 1. "WVSPPOS,WVSPPOS" hexmask.long.word 0x8 0.--11. 1. "WVSTPOS,WVSTPOS" line.long 0xC "LTDC_L2CKCR,This register defines the color key value (RGB). that is used by the color keying." hexmask.long.byte 0xC 16.--23. 1. "CKRED,CKRED" hexmask.long.byte 0xC 8.--15. 1. "CKGREEN,CKGREEN" newline hexmask.long.byte 0xC 0.--7. 1. "CKBLUE,CKBLUE" line.long 0x10 "LTDC_L2PFCR,This register defines the pixel format that is used for the stored data in the frame buffer of a layer. The pixel data is read from the frame buffer and then transformed to the internal format 8888 (ARGB)." bitfld.long 0x10 0.--2. "PF,PF" "0,1,2,3,4,5,6,7" line.long 0x14 "LTDC_L2CACR,This register defines the constant alpha value (divided by 255 by hardware). that is used in the alpha blending. Refer to LTDC_LxBFCR register." hexmask.long.byte 0x14 0.--7. 1. "CONSTA,CONSTA" line.long 0x18 "LTDC_L2DCCR,This register defines the default color of a layer in the format ARGB. The default color is used outside the defined layer window or when a layer is disabled. The reset value of 0x00000000 defines a transparent black color." hexmask.long.byte 0x18 24.--31. 1. "DCALPHA,DCALPHA" hexmask.long.byte 0x18 16.--23. 1. "DCRED,DCRED" newline hexmask.long.byte 0x18 8.--15. 1. "DCGREEN,DCGREEN" hexmask.long.byte 0x18 0.--7. 1. "DCBLUE,DCBLUE" line.long 0x1C "LTDC_L2BFCR,This register defines the blending factors F1 and F2. The general blending formula is: BC = BF1 x C + BF2 x Cs BC = blended color BF1 = blend factor 1 C = current layer color BF2 = blend factor 2 Cs = subjacent layers blended color" bitfld.long 0x1C 8.--10. "BF1,BF1" "0,1,2,3,4,5,6,7" bitfld.long 0x1C 0.--2. "BF2,BF2" "0,1,2,3,4,5,6,7" group.long 0x12C++0xB line.long 0x0 "LTDC_L2CFBAR,This register defines the color frame buffer start address which has to point to the address where the pixel data of the top left pixel of a layer is stored in the frame buffer." hexmask.long 0x0 0.--31. 1. "CFBADD,CFBADD" line.long 0x4 "LTDC_L2CFBLR,This register defines the color frame buffer line length and pitch." hexmask.long.word 0x4 16.--29. 1. "CFBP,CFBP" hexmask.long.word 0x4 0.--13. 1. "CFBLL,CFBLL" line.long 0x8 "LTDC_L2CFBLNR,This register defines the number of lines in the color frame buffer." hexmask.long.word 0x8 0.--11. 1. "CFBLNBR,CFBLNBR" wgroup.long 0x144++0x3 line.long 0x0 "LTDC_L2CLUTWR,This register defines the CLUT address and the RGB value." hexmask.long.byte 0x0 24.--31. 1. "CLUTADD,CLUTADD" hexmask.long.byte 0x0 16.--23. 1. "RED,RED" newline hexmask.long.byte 0x0 8.--15. 1. "GREEN,GREEN" hexmask.long.byte 0x0 0.--7. 1. "BLUE,BLUE" endif sif (cpuis("STM32MP157*")) rgroup.long 0x0++0x3 line.long 0x0 "LTDC_IDR,LTDC identification register" endif sif (cpuis("STM32MP157*")) rgroup.long 0x4++0x3 line.long 0x0 "LTDC_LCR,LDTC layer count register" endif sif (cpuis("STM32MP157*")) rgroup.long 0x1C++0x3 line.long 0x0 "LTDC_GC1R,LTDC global configuration 1 register" endif sif (cpuis("STM32MP157*")) rgroup.long 0x20++0x3 line.long 0x0 "LTDC_GC2R,LTDC global configuration 2 register" endif sif (cpuis("STM32MP157*")) rgroup.long 0x38++0x3 line.long 0x0 "LTDC_ISR,This register returns the interrupt status flag." endif sif (cpuis("STM32MP157*")) wgroup.long 0x3C++0x3 line.long 0x0 "LTDC_ICR,LTDC Interrupt Clear Register" endif sif (cpuis("STM32MP157*")) rgroup.long 0x44++0x3 line.long 0x0 "LTDC_CPSR,LTDC current position status register" endif sif (cpuis("STM32MP157*")) rgroup.long 0x48++0x3 line.long 0x0 "LTDC_CDSR,This register returns the status of the current display phase which is controlled by the HSYNC. VSYNC. and horizontal/vertical DE signals. Example: if the current display phase is the vertical synchronization. the VSYNCS bit is set (active.." group.long 0x84++0x1F line.long 0x0 "LTDC_L1CR,LTDC layer 1 control register" bitfld.long 0x0 4. "CLUTEN,CLUTEN" "0,1" bitfld.long 0x0 1. "COLKEN,COLKEN" "0,1" newline bitfld.long 0x0 0. "LEN,LEN" "0,1" line.long 0x4 "LTDC_L1WHPCR,This register defines the horizontal position (first and last pixel) of the layer 1 or 2 window. The first visible pixel of a line is the programmed value of AHBP[11:0] bits + 1 in the LTDC_BPCR register. The last visible pixel of a line is.." hexmask.long.word 0x4 16.--27. 1. "WHSPPOS,WHSPPOS" hexmask.long.word 0x4 0.--11. 1. "WHSTPOS,WHSTPOS" line.long 0x8 "LTDC_L1WVPCR,This register defines the vertical position (first and last line) of the layer1 or 2 window. The first visible line of a frame is the programmed value of AVBP[11:0] bits + 1 in the register LTDC_BPCR register. The last visible line of a.." hexmask.long.word 0x8 16.--27. 1. "WVSPPOS,WVSPPOS" hexmask.long.word 0x8 0.--11. 1. "WVSTPOS,WVSTPOS" line.long 0xC "LTDC_L1CKCR,This register defines the color key value (RGB). that is used by the color keying." hexmask.long.byte 0xC 16.--23. 1. "CKRED,CKRED" hexmask.long.byte 0xC 8.--15. 1. "CKGREEN,CKGREEN" newline hexmask.long.byte 0xC 0.--7. 1. "CKBLUE,CKBLUE" line.long 0x10 "LTDC_L1PFCR,This register defines the pixel format that is used for the stored data in the frame buffer of a layer. The pixel data is read from the frame buffer and then transformed to the internal format 8888 (ARGB)." bitfld.long 0x10 0.--2. "PF,PF" "0,1,2,3,4,5,6,7" line.long 0x14 "LTDC_L1CACR,This register defines the constant alpha value (divided by 255 by hardware). that is used in the alpha blending. Refer to LTDC_LxBFCR register." hexmask.long.byte 0x14 0.--7. 1. "CONSTA,CONSTA" line.long 0x18 "LTDC_L1DCCR,This register defines the default color of a layer in the format ARGB. The default color is used outside the defined layer window or when a layer is disabled. The reset value of 0x00000000 defines a transparent black color." hexmask.long.byte 0x18 24.--31. 1. "DCALPHA,DCALPHA" hexmask.long.byte 0x18 16.--23. 1. "DCRED,DCRED" newline hexmask.long.byte 0x18 8.--15. 1. "DCGREEN,DCGREEN" hexmask.long.byte 0x18 0.--7. 1. "DCBLUE,DCBLUE" line.long 0x1C "LTDC_L1BFCR,This register defines the blending factors F1 and F2. The general blending formula is: BC = BF1 x C + BF2 x Cs BC = blended color BF1 = blend factor 1 C = current layer color BF2 = blend factor 2 Cs = subjacent layers blended color" bitfld.long 0x1C 8.--10. "BF1,BF1" "0,1,2,3,4,5,6,7" bitfld.long 0x1C 0.--2. "BF2,BF2" "0,1,2,3,4,5,6,7" group.long 0xAC++0xB line.long 0x0 "LTDC_L1CFBAR,This register defines the color frame buffer start address which has to point to the address where the pixel data of the top left pixel of a layer is stored in the frame buffer." hexmask.long 0x0 0.--31. 1. "CFBADD,CFBADD" line.long 0x4 "LTDC_L1CFBLR,This register defines the color frame buffer line length and pitch." hexmask.long.word 0x4 16.--29. 1. "CFBP,CFBP" hexmask.long.word 0x4 0.--13. 1. "CFBLL,CFBLL" line.long 0x8 "LTDC_L1CFBLNR,This register defines the number of lines in the color frame buffer." hexmask.long.word 0x8 0.--11. 1. "CFBLNBR,CFBLNBR" wgroup.long 0xC4++0x3 line.long 0x0 "LTDC_L1CLUTWR,This register defines the CLUT address and the RGB value." hexmask.long.byte 0x0 24.--31. 1. "CLUTADD,CLUTADD" hexmask.long.byte 0x0 16.--23. 1. "RED,RED" newline hexmask.long.byte 0x0 8.--15. 1. "GREEN,GREEN" hexmask.long.byte 0x0 0.--7. 1. "BLUE,BLUE" group.long 0x104++0x1F line.long 0x0 "LTDC_L2CR,LTDC layer 2 control register" bitfld.long 0x0 4. "CLUTEN,CLUTEN" "0,1" bitfld.long 0x0 1. "COLKEN,COLKEN" "0,1" newline bitfld.long 0x0 0. "LEN,LEN" "0,1" line.long 0x4 "LTDC_L2WHPCR,This register defines the horizontal position (first and last pixel) of the layer 1 or 2 window. The first visible pixel of a line is the programmed value of AHBP[11:0] bits + 1 in the LTDC_BPCR register. The last visible pixel of a line is.." hexmask.long.word 0x4 16.--27. 1. "WHSPPOS,WHSPPOS" hexmask.long.word 0x4 0.--11. 1. "WHSTPOS,WHSTPOS" line.long 0x8 "LTDC_L2WVPCR,This register defines the vertical position (first and last line) of the layer1 or 2 window. The first visible line of a frame is the programmed value of AVBP[11:0] bits + 1 in the register LTDC_BPCR register. The last visible line of a.." hexmask.long.word 0x8 16.--27. 1. "WVSPPOS,WVSPPOS" hexmask.long.word 0x8 0.--11. 1. "WVSTPOS,WVSTPOS" line.long 0xC "LTDC_L2CKCR,This register defines the color key value (RGB). that is used by the color keying." hexmask.long.byte 0xC 16.--23. 1. "CKRED,CKRED" hexmask.long.byte 0xC 8.--15. 1. "CKGREEN,CKGREEN" newline hexmask.long.byte 0xC 0.--7. 1. "CKBLUE,CKBLUE" line.long 0x10 "LTDC_L2PFCR,This register defines the pixel format that is used for the stored data in the frame buffer of a layer. The pixel data is read from the frame buffer and then transformed to the internal format 8888 (ARGB)." bitfld.long 0x10 0.--2. "PF,PF" "0,1,2,3,4,5,6,7" line.long 0x14 "LTDC_L2CACR,This register defines the constant alpha value (divided by 255 by hardware). that is used in the alpha blending. Refer to LTDC_LxBFCR register." hexmask.long.byte 0x14 0.--7. 1. "CONSTA,CONSTA" line.long 0x18 "LTDC_L2DCCR,This register defines the default color of a layer in the format ARGB. The default color is used outside the defined layer window or when a layer is disabled. The reset value of 0x00000000 defines a transparent black color." hexmask.long.byte 0x18 24.--31. 1. "DCALPHA,DCALPHA" hexmask.long.byte 0x18 16.--23. 1. "DCRED,DCRED" newline hexmask.long.byte 0x18 8.--15. 1. "DCGREEN,DCGREEN" hexmask.long.byte 0x18 0.--7. 1. "DCBLUE,DCBLUE" line.long 0x1C "LTDC_L2BFCR,This register defines the blending factors F1 and F2. The general blending formula is: BC = BF1 x C + BF2 x Cs BC = blended color BF1 = blend factor 1 C = current layer color BF2 = blend factor 2 Cs = subjacent layers blended color" bitfld.long 0x1C 8.--10. "BF1,BF1" "0,1,2,3,4,5,6,7" bitfld.long 0x1C 0.--2. "BF2,BF2" "0,1,2,3,4,5,6,7" group.long 0x12C++0xB line.long 0x0 "LTDC_L2CFBAR,This register defines the color frame buffer start address which has to point to the address where the pixel data of the top left pixel of a layer is stored in the frame buffer." hexmask.long 0x0 0.--31. 1. "CFBADD,CFBADD" line.long 0x4 "LTDC_L2CFBLR,This register defines the color frame buffer line length and pitch." hexmask.long.word 0x4 16.--29. 1. "CFBP,CFBP" hexmask.long.word 0x4 0.--13. 1. "CFBLL,CFBLL" line.long 0x8 "LTDC_L2CFBLNR,This register defines the number of lines in the color frame buffer." hexmask.long.word 0x8 0.--11. 1. "CFBLNBR,CFBLNBR" wgroup.long 0x144++0x3 line.long 0x0 "LTDC_L2CLUTWR,This register defines the CLUT address and the RGB value." hexmask.long.byte 0x0 24.--31. 1. "CLUTADD,CLUTADD" hexmask.long.byte 0x0 16.--23. 1. "RED,RED" newline hexmask.long.byte 0x0 8.--15. 1. "GREEN,GREEN" hexmask.long.byte 0x0 0.--7. 1. "BLUE,BLUE" endif tree.end sif (cpuis("STM32MP13*")) tree "MCE (Memory Cipher Engine)" base ad:0x58001000 group.long 0x0++0x3 line.long 0x0 "MCE_CR,MCE configuration register" bitfld.long 0x0 1. "MKLOCK,Master keys lock" "0: Writes to MCE_MKEYRx register is allowed,1: Writes to MCE_MKEYRx register is ignored until.." bitfld.long 0x0 0. "GLOCK,Global lock" "0: MCE registers are writable,1: All writes to MCE registers are ignored with the.." rgroup.long 0x4++0x7 line.long 0x0 "MCE_SR,MCE status register" bitfld.long 0x0 4. "ENCDIS,encryption disabled" "0: When ENC bit and BREN are set in MCE_REGCR all..,1: When ENC bit and BREN are set in MCE_REGCR all.." bitfld.long 0x0 0. "MKVALID,Master key valid" "0: A valid key has not been written in MCE_MKEYRx..,1: A valid key has been written in MCE_MKEYRx.." line.long 0x4 "MCE_IASR,MCE illegal access status register" bitfld.long 0x4 0. "CAEF,Configuration access error flag" "0,1" wgroup.long 0xC++0x3 line.long 0x0 "MCE_IACR,MCE illegal access clear register" bitfld.long 0x0 0. "CAEF,Configuration access error flag clear" "0,1" group.long 0x10++0x3 line.long 0x0 "MCE_IAIER,MCE illegal access interrupt enable register" bitfld.long 0x0 0. "CAEIE,Configuration access error interrupt enable" "0: Interrupt generation on configuration access..,1: Interrupt generation when a configuration access.." group.long 0x1C++0x3 line.long 0x0 "MCE_PRIVCFGR,MCE privileged configuration register" bitfld.long 0x0 0. "PRIV,Privileged configuration" "0: Privileged and unprivileged access are granted..,1: Only privileged access are granted to MCE.." group.long 0x40++0xB line.long 0x0 "MCE_REGCR,MCE region x configuration register" bitfld.long 0x0 15. "ENC,Encrypted region" "0: No effects,1: All allowed read (resp. write) requests are.." bitfld.long 0x0 0. "BREN,Base region enable" "0: Region is disabled. Access control of primary..,1: Region is enable. Access controls and encryption.." line.long 0x4 "MCE_SADDR,MCE start address register" hexmask.long.word 0x4 16.--31. 1. "BADDSTART,Region address start" line.long 0x8 "MCE_EADDR,MCE end address register" hexmask.long.word 0x8 16.--31. 1. "BADDEND,Region address end" wgroup.long 0x200++0xF line.long 0x0 "MCE_MKEYR0,MCE master key 0" hexmask.long 0x0 0.--31. 1. "MKEY,Master key bits [31:0]" line.long 0x4 "MCE_MKEYR1,MCE master key 1" hexmask.long 0x4 0.--31. 1. "MKEY,Master key bits [63:32]" line.long 0x8 "MCE_MKEYR2,MCE master key 2" hexmask.long 0x8 0.--31. 1. "MKEY,Master key bits [95:64]" line.long 0xC "MCE_MKEYR3,MCE master key 3" hexmask.long 0xC 0.--31. 1. "MKEY,Master key bits [127:96]" rgroup.long 0x3E8++0x17 line.long 0x0 "MCE_HWCFGR3,MCE version register" hexmask.long.byte 0x0 28.--31. 1. "CFG8,HW Generic 8" hexmask.long.byte 0x0 24.--27. 1. "CFG7,HW Generic 7" newline hexmask.long.byte 0x0 20.--23. 1. "CFG6,HW Generic 6" hexmask.long.byte 0x0 16.--19. 1. "CFG5,HW Generic 5" newline hexmask.long.byte 0x0 12.--15. 1. "CFG4,HW Generic 4" hexmask.long.byte 0x0 8.--11. 1. "CFG3,HW Generic 3" newline hexmask.long.byte 0x0 4.--7. 1. "CFG2,HW Generic 2" hexmask.long.byte 0x0 0.--3. 1. "CFG1,HW Generic 1" line.long 0x4 "MCE_HWCFGR2,MCE version register" hexmask.long.byte 0x4 28.--31. 1. "CFG8,HW Generic 8" hexmask.long.byte 0x4 24.--27. 1. "CFG7,HW Generic 7" newline hexmask.long.byte 0x4 20.--23. 1. "CFG6,HW Generic 6" hexmask.long.byte 0x4 16.--19. 1. "CFG5,HW Generic 5" newline hexmask.long.byte 0x4 12.--15. 1. "CFG4,HW Generic 4" hexmask.long.byte 0x4 8.--11. 1. "CFG3,HW Generic 3" newline hexmask.long.byte 0x4 4.--7. 1. "CFG2,HW Generic 2" hexmask.long.byte 0x4 0.--3. 1. "CFG1,HW Generic 1" line.long 0x8 "MCE_HWCFGR1,MCE version register" hexmask.long.byte 0x8 16.--23. 1. "CFG3,HW Generic 3" hexmask.long.byte 0x8 8.--15. 1. "CFG2,HW Generic 2" newline hexmask.long.byte 0x8 0.--7. 1. "CFG1,HW Generic 1" line.long 0xC "MCE_VERR,MCE version register" hexmask.long.byte 0xC 4.--7. 1. "MAJREV,Major revision" hexmask.long.byte 0xC 0.--3. 1. "MINREV,Minor revision" line.long 0x10 "MCE_IPIDR,MCE identification register" hexmask.long 0x10 0.--31. 1. "ID,Identification Code" line.long 0x14 "MCE_SIDR,MCE size ID register" hexmask.long 0x14 0.--31. 1. "SID,Size Identification Code" tree.end endif sif (cpuis("STM32MP151*")||cpuis("STM32MP153*")||cpuis("STM32MP157*")) tree "MDIOS (Management Data Input/Output)" base ad:0x4001C000 group.long 0x0++0x3 line.long 0x0 "MDIOS_CR,MDIOS configuration register" hexmask.long.byte 0x0 8.--12. 1. "PORT_ADDRESS,PORT_ADDRESS" bitfld.long 0x0 7. "DPC,DPC" "0,1" bitfld.long 0x0 3. "EIE,EIE" "0,1" bitfld.long 0x0 2. "RDIE,RDIE" "0,1" bitfld.long 0x0 1. "WRIE,WRIE" "0,1" bitfld.long 0x0 0. "EN,EN" "0,1" rgroup.long 0x4++0x3 line.long 0x0 "MDIOS_WRFR,MDIOS write flag register" hexmask.long 0x0 0.--31. 1. "WRF,WRF" group.long 0x8++0x3 line.long 0x0 "MDIOS_CWRFR,MDIOS clear write flag" hexmask.long 0x0 0.--31. 1. "CWRF,CWRF" rgroup.long 0xC++0x3 line.long 0x0 "MDIOS_RDFR,MDIOS read flag register" hexmask.long 0x0 0.--31. 1. "RDF,RDF" group.long 0x10++0x3 line.long 0x0 "MDIOS_CRDFR,MDIOS clear read flag register" hexmask.long 0x0 0.--31. 1. "CRDF,CRDF" rgroup.long 0x14++0x3 line.long 0x0 "MDIOS_SR,MDIOS status register" bitfld.long 0x0 2. "TERF,TERF" "0,1" bitfld.long 0x0 1. "SERF,SERF" "0,1" bitfld.long 0x0 0. "PERF,PERF" "0,1" group.long 0x18++0x3 line.long 0x0 "MDIOS_CLRFR,MDIOS clear flag register" bitfld.long 0x0 2. "CTERF,CTERF" "0,1" bitfld.long 0x0 1. "CSERF,CSERF" "0,1" bitfld.long 0x0 0. "CPERF,CPERF" "0,1" rgroup.long 0x100++0xFF line.long 0x0 "MDIOS_DINR0,MDIOS input data register" hexmask.long.word 0x0 0.--15. 1. "DIN,DIN" line.long 0x4 "MDIOS_DINR1,MDIOS input data register" hexmask.long.word 0x4 0.--15. 1. "DIN,DIN" line.long 0x8 "MDIOS_DINR2,MDIOS input data register" hexmask.long.word 0x8 0.--15. 1. "DIN,DIN" line.long 0xC "MDIOS_DINR3,MDIOS input data register" hexmask.long.word 0xC 0.--15. 1. "DIN,DIN" line.long 0x10 "MDIOS_DINR4,MDIOS input data register" hexmask.long.word 0x10 0.--15. 1. "DIN,DIN" line.long 0x14 "MDIOS_DINR5,MDIOS input data register" hexmask.long.word 0x14 0.--15. 1. "DIN,DIN" line.long 0x18 "MDIOS_DINR6,MDIOS input data register" hexmask.long.word 0x18 0.--15. 1. "DIN,DIN" line.long 0x1C "MDIOS_DINR7,MDIOS input data register" hexmask.long.word 0x1C 0.--15. 1. "DIN,DIN" line.long 0x20 "MDIOS_DINR8,MDIOS input data register" hexmask.long.word 0x20 0.--15. 1. "DIN,DIN" line.long 0x24 "MDIOS_DINR9,MDIOS input data register" hexmask.long.word 0x24 0.--15. 1. "DIN,DIN" line.long 0x28 "MDIOS_DINR10,MDIOS input data register" hexmask.long.word 0x28 0.--15. 1. "DIN,DIN" line.long 0x2C "MDIOS_DINR11,MDIOS input data register" hexmask.long.word 0x2C 0.--15. 1. "DIN,DIN" line.long 0x30 "MDIOS_DINR12,MDIOS input data register" hexmask.long.word 0x30 0.--15. 1. "DIN,DIN" line.long 0x34 "MDIOS_DINR13,MDIOS input data register" hexmask.long.word 0x34 0.--15. 1. "DIN,DIN" line.long 0x38 "MDIOS_DINR14,MDIOS input data register" hexmask.long.word 0x38 0.--15. 1. "DIN,DIN" line.long 0x3C "MDIOS_DINR15,MDIOS input data register" hexmask.long.word 0x3C 0.--15. 1. "DIN,DIN" line.long 0x40 "MDIOS_DINR16,MDIOS input data register" hexmask.long.word 0x40 0.--15. 1. "DIN,DIN" line.long 0x44 "MDIOS_DINR17,MDIOS input data register" hexmask.long.word 0x44 0.--15. 1. "DIN,DIN" line.long 0x48 "MDIOS_DINR18,MDIOS input data register" hexmask.long.word 0x48 0.--15. 1. "DIN,DIN" line.long 0x4C "MDIOS_DINR19,MDIOS input data register" hexmask.long.word 0x4C 0.--15. 1. "DIN,DIN" line.long 0x50 "MDIOS_DINR20,MDIOS input data register" hexmask.long.word 0x50 0.--15. 1. "DIN,DIN" line.long 0x54 "MDIOS_DINR21,MDIOS input data register" hexmask.long.word 0x54 0.--15. 1. "DIN,DIN" line.long 0x58 "MDIOS_DINR22,MDIOS input data register" hexmask.long.word 0x58 0.--15. 1. "DIN,DIN" line.long 0x5C "MDIOS_DINR23,MDIOS input data register" hexmask.long.word 0x5C 0.--15. 1. "DIN,DIN" line.long 0x60 "MDIOS_DINR24,MDIOS input data register" hexmask.long.word 0x60 0.--15. 1. "DIN,DIN" line.long 0x64 "MDIOS_DINR25,MDIOS input data register" hexmask.long.word 0x64 0.--15. 1. "DIN,DIN" line.long 0x68 "MDIOS_DINR26,MDIOS input data register" hexmask.long.word 0x68 0.--15. 1. "DIN,DIN" line.long 0x6C "MDIOS_DINR27,MDIOS input data register" hexmask.long.word 0x6C 0.--15. 1. "DIN,DIN" line.long 0x70 "MDIOS_DINR28,MDIOS input data register" hexmask.long.word 0x70 0.--15. 1. "DIN,DIN" line.long 0x74 "MDIOS_DINR29,MDIOS input data register" hexmask.long.word 0x74 0.--15. 1. "DIN,DIN" line.long 0x78 "MDIOS_DINR30,MDIOS input data register" hexmask.long.word 0x78 0.--15. 1. "DIN,DIN" line.long 0x7C "MDIOS_DINR31,MDIOS input data register" hexmask.long.word 0x7C 0.--15. 1. "DIN,DIN" line.long 0x80 "MDIOS_DOUTR0,MDIOS input data register" hexmask.long.word 0x80 0.--15. 1. "DOUT,DOUT" line.long 0x84 "MDIOS_DOUTR1,MDIOS input data register" hexmask.long.word 0x84 0.--15. 1. "DOUT,DOUT" line.long 0x88 "MDIOS_DOUTR2,MDIOS output data register" hexmask.long.word 0x88 0.--15. 1. "DOUT,DOUT" line.long 0x8C "MDIOS_DOUTR3,MDIOS output data register" hexmask.long.word 0x8C 0.--15. 1. "DOUT,DOUT" line.long 0x90 "MDIOS_DOUTR4,MDIOS output data register" hexmask.long.word 0x90 0.--15. 1. "DOUT,DOUT" line.long 0x94 "MDIOS_DOUTR5,MDIOS output data register" hexmask.long.word 0x94 0.--15. 1. "DOUT,DOUT" line.long 0x98 "MDIOS_DOUTR6,MDIOS output data register" hexmask.long.word 0x98 0.--15. 1. "DOUT,DOUT" line.long 0x9C "MDIOS_DOUTR7,MDIOS output data register" hexmask.long.word 0x9C 0.--15. 1. "DOUT,DOUT" line.long 0xA0 "MDIOS_DOUTR8,MDIOS output data register" hexmask.long.word 0xA0 0.--15. 1. "DOUT,DOUT" line.long 0xA4 "MDIOS_DOUTR9,MDIOS output data register" hexmask.long.word 0xA4 0.--15. 1. "DOUT,DOUT" line.long 0xA8 "MDIOS_DOUTR10,MDIOS output data register" hexmask.long.word 0xA8 0.--15. 1. "DOUT,DOUT" line.long 0xAC "MDIOS_DOUTR11,MDIOS output data register" hexmask.long.word 0xAC 0.--15. 1. "DOUT,DOUT" line.long 0xB0 "MDIOS_DOUTR12,MDIOS output data register" hexmask.long.word 0xB0 0.--15. 1. "DOUT,DOUT" line.long 0xB4 "MDIOS_DOUTR13,MDIOS output data register" hexmask.long.word 0xB4 0.--15. 1. "DOUT,DOUT" line.long 0xB8 "MDIOS_DOUTR14,MDIOS output data register" hexmask.long.word 0xB8 0.--15. 1. "DOUT,DOUT" line.long 0xBC "MDIOS_DOUTR15,MDIOS output data register" hexmask.long.word 0xBC 0.--15. 1. "DOUT,DOUT" line.long 0xC0 "MDIOS_DOUTR16,MDIOS output data register" hexmask.long.word 0xC0 0.--15. 1. "DOUT,DOUT" line.long 0xC4 "MDIOS_DOUTR17,MDIOS output data register" hexmask.long.word 0xC4 0.--15. 1. "DOUT,DOUT" line.long 0xC8 "MDIOS_DOUTR18,MDIOS output data register" hexmask.long.word 0xC8 0.--15. 1. "DOUT,DOUT" line.long 0xCC "MDIOS_DOUTR19,MDIOS output data register" hexmask.long.word 0xCC 0.--15. 1. "DOUT,DOUT" line.long 0xD0 "MDIOS_DOUTR20,MDIOS output data register" hexmask.long.word 0xD0 0.--15. 1. "DOUT,DOUT" line.long 0xD4 "MDIOS_DOUTR21,MDIOS output data register" hexmask.long.word 0xD4 0.--15. 1. "DOUT,DOUT" line.long 0xD8 "MDIOS_DOUTR22,MDIOS output data register" hexmask.long.word 0xD8 0.--15. 1. "DOUT,DOUT" line.long 0xDC "MDIOS_DOUTR23,MDIOS output data register" hexmask.long.word 0xDC 0.--15. 1. "DOUT,DOUT" line.long 0xE0 "MDIOS_DOUTR24,MDIOS output data register" hexmask.long.word 0xE0 0.--15. 1. "DOUT,DOUT" line.long 0xE4 "MDIOS_DOUTR25,MDIOS output data register" hexmask.long.word 0xE4 0.--15. 1. "DOUT,DOUT" line.long 0xE8 "MDIOS_DOUTR26,MDIOS output data register" hexmask.long.word 0xE8 0.--15. 1. "DOUT,DOUT" line.long 0xEC "MDIOS_DOUTR27,MDIOS output data register" hexmask.long.word 0xEC 0.--15. 1. "DOUT,DOUT" line.long 0xF0 "MDIOS_DOUTR28,MDIOS output data register" hexmask.long.word 0xF0 0.--15. 1. "DOUT,DOUT" line.long 0xF4 "MDIOS_DOUTR29,MDIOS output data register" hexmask.long.word 0xF4 0.--15. 1. "DOUT,DOUT" line.long 0xF8 "MDIOS_DOUTR30,MDIOS output data register" hexmask.long.word 0xF8 0.--15. 1. "DOUT,DOUT" line.long 0xFC "MDIOS_DOUTR31,MDIOS output data register" hexmask.long.word 0xFC 0.--15. 1. "DOUT,DOUT" rgroup.long 0x3F0++0xF line.long 0x0 "MDIOS_HWCFGR,MDIOS HW configuration" hexmask.long.byte 0x0 0.--7. 1. "NBREG,NBREG" line.long 0x4 "MDIOS_VERR,MDIOS version register" hexmask.long.byte 0x4 4.--7. 1. "MAJREV,MAJREV" hexmask.long.byte 0x4 0.--3. 1. "MINREV,MINREV" line.long 0x8 "MDIOS_IPIDR,MDIOS identification register" hexmask.long 0x8 0.--31. 1. "ID,ID" line.long 0xC "MDIOS_SIDR,MDIOS size identification" hexmask.long 0xC 0.--31. 1. "SID,SID" tree.end endif tree "MDMA (Master Direct Memory Access Controller)" base ad:0x58000000 rgroup.long 0x0++0x3 line.long 0x0 "MDMA_GISR0,MDMA global interrupt/status register" bitfld.long 0x0 31. "GIF31,GIF31" "0,1" bitfld.long 0x0 30. "GIF30,GIF30" "0,1" bitfld.long 0x0 29. "GIF29,GIF29" "0,1" bitfld.long 0x0 28. "GIF28,GIF28" "0,1" bitfld.long 0x0 27. "GIF27,GIF27" "0,1" bitfld.long 0x0 26. "GIF26,GIF26" "0,1" bitfld.long 0x0 25. "GIF25,GIF25" "0,1" bitfld.long 0x0 24. "GIF24,GIF24" "0,1" bitfld.long 0x0 23. "GIF23,GIF23" "0,1" bitfld.long 0x0 22. "GIF22,GIF22" "0,1" newline bitfld.long 0x0 21. "GIF21,GIF21" "0,1" bitfld.long 0x0 20. "GIF20,GIF20" "0,1" bitfld.long 0x0 19. "GIF19,GIF19" "0,1" bitfld.long 0x0 18. "GIF18,GIF18" "0,1" bitfld.long 0x0 17. "GIF17,GIF17" "0,1" bitfld.long 0x0 16. "GIF16,GIF16" "0,1" bitfld.long 0x0 15. "GIF15,GIF15" "0,1" bitfld.long 0x0 14. "GIF14,GIF14" "0,1" bitfld.long 0x0 13. "GIF13,GIF13" "0,1" bitfld.long 0x0 12. "GIF12,GIF12" "0,1" newline bitfld.long 0x0 11. "GIF11,GIF11" "0,1" bitfld.long 0x0 10. "GIF10,GIF10" "0,1" bitfld.long 0x0 9. "GIF9,GIF9" "0,1" bitfld.long 0x0 8. "GIF8,GIF8" "0,1" bitfld.long 0x0 7. "GIF7,GIF7" "0,1" bitfld.long 0x0 6. "GIF6,GIF6" "0,1" bitfld.long 0x0 5. "GIF5,GIF5" "0,1" bitfld.long 0x0 4. "GIF4,GIF4" "0,1" bitfld.long 0x0 3. "GIF3,GIF3" "0,1" bitfld.long 0x0 2. "GIF2,GIF2" "0,1" newline bitfld.long 0x0 1. "GIF1,GIF1" "0,1" bitfld.long 0x0 0. "GIF0,GIF0" "0,1" rgroup.long 0x8++0x3 line.long 0x0 "MDMA_SGISR0,MDMA secure global interrupt/status register" bitfld.long 0x0 31. "GIF31,GIF31" "0,1" bitfld.long 0x0 30. "GIF30,GIF30" "0,1" bitfld.long 0x0 29. "GIF29,GIF29" "0,1" bitfld.long 0x0 28. "GIF28,GIF28" "0,1" bitfld.long 0x0 27. "GIF27,GIF27" "0,1" bitfld.long 0x0 26. "GIF26,GIF26" "0,1" bitfld.long 0x0 25. "GIF25,GIF25" "0,1" bitfld.long 0x0 24. "GIF24,GIF24" "0,1" bitfld.long 0x0 23. "GIF23,GIF23" "0,1" bitfld.long 0x0 22. "GIF22,GIF22" "0,1" newline bitfld.long 0x0 21. "GIF21,GIF21" "0,1" bitfld.long 0x0 20. "GIF20,GIF20" "0,1" bitfld.long 0x0 19. "GIF19,GIF19" "0,1" bitfld.long 0x0 18. "GIF18,GIF18" "0,1" bitfld.long 0x0 17. "GIF17,GIF17" "0,1" bitfld.long 0x0 16. "GIF16,GIF16" "0,1" bitfld.long 0x0 15. "GIF15,GIF15" "0,1" bitfld.long 0x0 14. "GIF14,GIF14" "0,1" bitfld.long 0x0 13. "GIF13,GIF13" "0,1" bitfld.long 0x0 12. "GIF12,GIF12" "0,1" newline bitfld.long 0x0 11. "GIF11,GIF11" "0,1" bitfld.long 0x0 10. "GIF10,GIF10" "0,1" bitfld.long 0x0 9. "GIF9,GIF9" "0,1" bitfld.long 0x0 8. "GIF8,GIF8" "0,1" bitfld.long 0x0 7. "GIF7,GIF7" "0,1" bitfld.long 0x0 6. "GIF6,GIF6" "0,1" bitfld.long 0x0 5. "GIF5,GIF5" "0,1" bitfld.long 0x0 4. "GIF4,GIF4" "0,1" bitfld.long 0x0 3. "GIF3,GIF3" "0,1" bitfld.long 0x0 2. "GIF2,GIF2" "0,1" newline bitfld.long 0x0 1. "GIF1,GIF1" "0,1" bitfld.long 0x0 0. "GIF0,GIF0" "0,1" rgroup.long 0x40++0x3 line.long 0x0 "MDMA_C0ISR,MDMA channel 0 interrupt/status register" bitfld.long 0x0 16. "CRQA,CRQA" "0,1" bitfld.long 0x0 4. "TCIF,TCIF" "0,1" bitfld.long 0x0 3. "BTIF,BTIF" "0,1" bitfld.long 0x0 2. "BRTIF,BRTIF" "0,1" bitfld.long 0x0 1. "CTCIF,CTCIF" "0,1" bitfld.long 0x0 0. "TEIF,TEIF" "0,1" wgroup.long 0x44++0x3 line.long 0x0 "MDMA_C0IFCR,MDMA channel 0 interrupt flag clear register" bitfld.long 0x0 4. "CLTCIF,CLTCIF" "0,1" bitfld.long 0x0 3. "CBTIF,CBTIF" "0,1" bitfld.long 0x0 2. "CBRTIF,CBRTIF" "0,1" bitfld.long 0x0 1. "CCTCIF,CCTCIF" "0,1" bitfld.long 0x0 0. "CTEIF,CTEIF" "0,1" rgroup.long 0x48++0x3 line.long 0x0 "MDMA_C0ESR,MDMA channel 0 error status register" bitfld.long 0x0 11. "BSE,BSE" "0,1" bitfld.long 0x0 10. "ASE,ASE" "0,1" bitfld.long 0x0 9. "TEMD,TEMD" "0,1" bitfld.long 0x0 8. "TELD,TELD" "0,1" bitfld.long 0x0 7. "TED,TED" "0,1" hexmask.long.byte 0x0 0.--6. 1. "TEA,TEA" group.long 0x4C++0x1F line.long 0x0 "MDMA_C0CR,This register is used to control the concerned channel." bitfld.long 0x0 16. "SWRQ,SWRQ" "0,1" bitfld.long 0x0 14. "WEX,WEX" "0,1" bitfld.long 0x0 13. "HEX,HEX" "0,1" bitfld.long 0x0 12. "BEX,BEX" "0,1" bitfld.long 0x0 6.--7. "PL,PL" "0,1,2,3" bitfld.long 0x0 5. "TCIE,TCIE" "0,1" bitfld.long 0x0 4. "BTIE,BTIE" "0,1" bitfld.long 0x0 3. "BRTIE,BRTIE" "0,1" bitfld.long 0x0 2. "CTCIE,CTCIE" "0,1" bitfld.long 0x0 1. "TEIE,TEIE" "0,1" newline bitfld.long 0x0 0. "EN,EN" "0,1" line.long 0x4 "MDMA_C0TCR,This register is used to configure the concerned channel. In Linked List mode. at the end of a block (single or last block in repeated block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] +.." bitfld.long 0x4 31. "BWM,BWM" "0,1" bitfld.long 0x4 30. "SWRM,SWRM" "0,1" bitfld.long 0x4 28.--29. "TRGM,TRGM" "0,1,2,3" bitfld.long 0x4 26.--27. "PAM,PAM" "0,1,2,3" bitfld.long 0x4 25. "PKE,PKE" "0,1" hexmask.long.byte 0x4 18.--24. 1. "TLEN,TLEN" bitfld.long 0x4 15.--17. "DBURST,DBURST" "0,1,2,3,4,5,6,7" bitfld.long 0x4 12.--14. "SBURST,SBURST" "0,1,2,3,4,5,6,7" bitfld.long 0x4 10.--11. "DINCOS,DINCOS" "0,1,2,3" bitfld.long 0x4 8.--9. "SINCOS,SINCOS" "0,1,2,3" newline bitfld.long 0x4 6.--7. "DSIZE,DSIZE" "0,1,2,3" bitfld.long 0x4 4.--5. "SSIZE,SSIZE" "0,1,2,3" bitfld.long 0x4 2.--3. "DINC,DINC" "0,1,2,3" bitfld.long 0x4 0.--1. "SINC,SINC" "0,1,2,3" line.long 0x8 "MDMA_C0BNDTR,In Linked List mode. at the end of a block (single or last block in repeated block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] + 0x04)." hexmask.long.word 0x8 20.--31. 1. "BRC,BRC" bitfld.long 0x8 19. "BRDUM,BRDUM" "0,1" bitfld.long 0x8 18. "BRSUM,BRSUM" "0,1" hexmask.long.tbyte 0x8 0.--16. 1. "BNDT,BNDT" line.long 0xC "MDMA_C0SAR,In Linked List mode. at the end of a Block (single or last Block in repeated Block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] + 0x08)." hexmask.long 0xC 0.--31. 1. "SAR,SAR" line.long 0x10 "MDMA_C0DAR,In Linked List mode. at the end of a block (single or last block in repeated block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M" hexmask.long 0x10 0.--31. 1. "DAR,DAR" line.long 0x14 "MDMA_C0BRUR,In Linked List mode. at the end of a block (single or last block in repeated block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] + 0x10)." hexmask.long.word 0x14 16.--31. 1. "DUV,DUV" hexmask.long.word 0x14 0.--15. 1. "SUV,SUV" line.long 0x18 "MDMA_C0LAR,In Linked List mode. at the end of a block (single or last block in repeated block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all.." hexmask.long 0x18 0.--31. 1. "LAR,LAR" line.long 0x1C "MDMA_C0TBR,In Linked List mode. at the end of a block (single or last block in repeated block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] + 0x18)." bitfld.long 0x1C 17. "DBUS,DBUS" "0,1" bitfld.long 0x1C 16. "SBUS,SBUS" "0,1" hexmask.long.byte 0x1C 0.--5. 1. "TSEL,TSEL" group.long 0x70++0x7 line.long 0x0 "MDMA_C0MAR,In Linked List mode. at the end of a block (single or last block in repeated block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] + 0x20)." hexmask.long 0x0 0.--31. 1. "MAR,MAR" line.long 0x4 "MDMA_C0MDR,In Linked List mode. at the end of a block (single or last block in repeated block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] + 0x24)." hexmask.long 0x4 0.--31. 1. "MDR,MDR" rgroup.long 0x80++0x3 line.long 0x0 "MDMA_C1ISR,MDMA channel 1 interrupt/status register" bitfld.long 0x0 16. "CRQA,CRQA" "0,1" bitfld.long 0x0 4. "TCIF,TCIF" "0,1" bitfld.long 0x0 3. "BTIF,BTIF" "0,1" bitfld.long 0x0 2. "BRTIF,BRTIF" "0,1" bitfld.long 0x0 1. "CTCIF,CTCIF" "0,1" bitfld.long 0x0 0. "TEIF,TEIF" "0,1" wgroup.long 0x84++0x3 line.long 0x0 "MDMA_C1IFCR,MDMA channel 1 interrupt flag clear register" bitfld.long 0x0 4. "CLTCIF,CLTCIF" "0,1" bitfld.long 0x0 3. "CBTIF,CBTIF" "0,1" bitfld.long 0x0 2. "CBRTIF,CBRTIF" "0,1" bitfld.long 0x0 1. "CCTCIF,CCTCIF" "0,1" bitfld.long 0x0 0. "CTEIF,CTEIF" "0,1" rgroup.long 0x88++0x3 line.long 0x0 "MDMA_C1ESR,MDMA channel 1 error status register" bitfld.long 0x0 11. "BSE,BSE" "0,1" bitfld.long 0x0 10. "ASE,ASE" "0,1" bitfld.long 0x0 9. "TEMD,TEMD" "0,1" bitfld.long 0x0 8. "TELD,TELD" "0,1" bitfld.long 0x0 7. "TED,TED" "0,1" hexmask.long.byte 0x0 0.--6. 1. "TEA,TEA" group.long 0x8C++0x1F line.long 0x0 "MDMA_C1CR,This register is used to control the concerned channel." bitfld.long 0x0 16. "SWRQ,SWRQ" "0,1" bitfld.long 0x0 14. "WEX,WEX" "0,1" bitfld.long 0x0 13. "HEX,HEX" "0,1" bitfld.long 0x0 12. "BEX,BEX" "0,1" bitfld.long 0x0 6.--7. "PL,PL" "0,1,2,3" bitfld.long 0x0 5. "TCIE,TCIE" "0,1" bitfld.long 0x0 4. "BTIE,BTIE" "0,1" bitfld.long 0x0 3. "BRTIE,BRTIE" "0,1" bitfld.long 0x0 2. "CTCIE,CTCIE" "0,1" bitfld.long 0x0 1. "TEIE,TEIE" "0,1" newline bitfld.long 0x0 0. "EN,EN" "0,1" line.long 0x4 "MDMA_C1TCR,This register is used to configure the concerned channel. In Linked List mode. at the end of a block (single or last block in repeated block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] +.." bitfld.long 0x4 31. "BWM,BWM" "0,1" bitfld.long 0x4 30. "SWRM,SWRM" "0,1" bitfld.long 0x4 28.--29. "TRGM,TRGM" "0,1,2,3" bitfld.long 0x4 26.--27. "PAM,PAM" "0,1,2,3" bitfld.long 0x4 25. "PKE,PKE" "0,1" hexmask.long.byte 0x4 18.--24. 1. "TLEN,TLEN" bitfld.long 0x4 15.--17. "DBURST,DBURST" "0,1,2,3,4,5,6,7" bitfld.long 0x4 12.--14. "SBURST,SBURST" "0,1,2,3,4,5,6,7" bitfld.long 0x4 10.--11. "DINCOS,DINCOS" "0,1,2,3" bitfld.long 0x4 8.--9. "SINCOS,SINCOS" "0,1,2,3" newline bitfld.long 0x4 6.--7. "DSIZE,DSIZE" "0,1,2,3" bitfld.long 0x4 4.--5. "SSIZE,SSIZE" "0,1,2,3" bitfld.long 0x4 2.--3. "DINC,DINC" "0,1,2,3" bitfld.long 0x4 0.--1. "SINC,SINC" "0,1,2,3" line.long 0x8 "MDMA_C1BNDTR,In Linked List mode. at the end of a block (single or last block in repeated block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] + 0x04)." hexmask.long.word 0x8 20.--31. 1. "BRC,BRC" bitfld.long 0x8 19. "BRDUM,BRDUM" "0,1" bitfld.long 0x8 18. "BRSUM,BRSUM" "0,1" hexmask.long.tbyte 0x8 0.--16. 1. "BNDT,BNDT" line.long 0xC "MDMA_C1SAR,In Linked List mode. at the end of a Block (single or last Block in repeated Block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] + 0x08)." hexmask.long 0xC 0.--31. 1. "SAR,SAR" line.long 0x10 "MDMA_C1DAR,In Linked List mode. at the end of a block (single or last block in repeated block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M" hexmask.long 0x10 0.--31. 1. "DAR,DAR" line.long 0x14 "MDMA_C1BRUR,In Linked List mode. at the end of a block (single or last block in repeated block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] + 0x10)." hexmask.long.word 0x14 16.--31. 1. "DUV,DUV" hexmask.long.word 0x14 0.--15. 1. "SUV,SUV" line.long 0x18 "MDMA_C1LAR,In Linked List mode. at the end of a block (single or last block in repeated block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all.." hexmask.long 0x18 0.--31. 1. "LAR,LAR" line.long 0x1C "MDMA_C1TBR,In Linked List mode. at the end of a block (single or last block in repeated block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] + 0x18)." bitfld.long 0x1C 17. "DBUS,DBUS" "0,1" bitfld.long 0x1C 16. "SBUS,SBUS" "0,1" hexmask.long.byte 0x1C 0.--5. 1. "TSEL,TSEL" group.long 0xB0++0x7 line.long 0x0 "MDMA_C1MAR,In Linked List mode. at the end of a block (single or last block in repeated block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] + 0x20)." hexmask.long 0x0 0.--31. 1. "MAR,MAR" line.long 0x4 "MDMA_C1MDR,In Linked List mode. at the end of a block (single or last block in repeated block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] + 0x24)." hexmask.long 0x4 0.--31. 1. "MDR,MDR" rgroup.long 0xC0++0x3 line.long 0x0 "MDMA_C2ISR,MDMA channel 2 interrupt/status register" bitfld.long 0x0 16. "CRQA,CRQA" "0,1" bitfld.long 0x0 4. "TCIF,TCIF" "0,1" bitfld.long 0x0 3. "BTIF,BTIF" "0,1" bitfld.long 0x0 2. "BRTIF,BRTIF" "0,1" bitfld.long 0x0 1. "CTCIF,CTCIF" "0,1" bitfld.long 0x0 0. "TEIF,TEIF" "0,1" wgroup.long 0xC4++0x3 line.long 0x0 "MDMA_C2IFCR,MDMA channel 2 interrupt flag clear register" bitfld.long 0x0 4. "CLTCIF,CLTCIF" "0,1" bitfld.long 0x0 3. "CBTIF,CBTIF" "0,1" bitfld.long 0x0 2. "CBRTIF,CBRTIF" "0,1" bitfld.long 0x0 1. "CCTCIF,CCTCIF" "0,1" bitfld.long 0x0 0. "CTEIF,CTEIF" "0,1" rgroup.long 0xC8++0x3 line.long 0x0 "MDMA_C2ESR,MDMA channel 2 error status register" bitfld.long 0x0 11. "BSE,BSE" "0,1" bitfld.long 0x0 10. "ASE,ASE" "0,1" bitfld.long 0x0 9. "TEMD,TEMD" "0,1" bitfld.long 0x0 8. "TELD,TELD" "0,1" bitfld.long 0x0 7. "TED,TED" "0,1" hexmask.long.byte 0x0 0.--6. 1. "TEA,TEA" group.long 0xCC++0x1F line.long 0x0 "MDMA_C2CR,This register is used to control the concerned channel." bitfld.long 0x0 16. "SWRQ,SWRQ" "0,1" bitfld.long 0x0 14. "WEX,WEX" "0,1" bitfld.long 0x0 13. "HEX,HEX" "0,1" bitfld.long 0x0 12. "BEX,BEX" "0,1" bitfld.long 0x0 6.--7. "PL,PL" "0,1,2,3" bitfld.long 0x0 5. "TCIE,TCIE" "0,1" bitfld.long 0x0 4. "BTIE,BTIE" "0,1" bitfld.long 0x0 3. "BRTIE,BRTIE" "0,1" bitfld.long 0x0 2. "CTCIE,CTCIE" "0,1" bitfld.long 0x0 1. "TEIE,TEIE" "0,1" newline bitfld.long 0x0 0. "EN,EN" "0,1" line.long 0x4 "MDMA_C2TCR,This register is used to configure the concerned channel. In Linked List mode. at the end of a block (single or last block in repeated block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] +.." bitfld.long 0x4 31. "BWM,BWM" "0,1" bitfld.long 0x4 30. "SWRM,SWRM" "0,1" bitfld.long 0x4 28.--29. "TRGM,TRGM" "0,1,2,3" bitfld.long 0x4 26.--27. "PAM,PAM" "0,1,2,3" bitfld.long 0x4 25. "PKE,PKE" "0,1" hexmask.long.byte 0x4 18.--24. 1. "TLEN,TLEN" bitfld.long 0x4 15.--17. "DBURST,DBURST" "0,1,2,3,4,5,6,7" bitfld.long 0x4 12.--14. "SBURST,SBURST" "0,1,2,3,4,5,6,7" bitfld.long 0x4 10.--11. "DINCOS,DINCOS" "0,1,2,3" bitfld.long 0x4 8.--9. "SINCOS,SINCOS" "0,1,2,3" newline bitfld.long 0x4 6.--7. "DSIZE,DSIZE" "0,1,2,3" bitfld.long 0x4 4.--5. "SSIZE,SSIZE" "0,1,2,3" bitfld.long 0x4 2.--3. "DINC,DINC" "0,1,2,3" bitfld.long 0x4 0.--1. "SINC,SINC" "0,1,2,3" line.long 0x8 "MDMA_C2BNDTR,In Linked List mode. at the end of a block (single or last block in repeated block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] + 0x04)." hexmask.long.word 0x8 20.--31. 1. "BRC,BRC" bitfld.long 0x8 19. "BRDUM,BRDUM" "0,1" bitfld.long 0x8 18. "BRSUM,BRSUM" "0,1" hexmask.long.tbyte 0x8 0.--16. 1. "BNDT,BNDT" line.long 0xC "MDMA_C2SAR,In Linked List mode. at the end of a Block (single or last Block in repeated Block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] + 0x08)." hexmask.long 0xC 0.--31. 1. "SAR,SAR" line.long 0x10 "MDMA_C2DAR,In Linked List mode. at the end of a block (single or last block in repeated block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M" hexmask.long 0x10 0.--31. 1. "DAR,DAR" line.long 0x14 "MDMA_C2BRUR,In Linked List mode. at the end of a block (single or last block in repeated block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] + 0x10)." hexmask.long.word 0x14 16.--31. 1. "DUV,DUV" hexmask.long.word 0x14 0.--15. 1. "SUV,SUV" line.long 0x18 "MDMA_C2LAR,In Linked List mode. at the end of a block (single or last block in repeated block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all.." hexmask.long 0x18 0.--31. 1. "LAR,LAR" line.long 0x1C "MDMA_C2TBR,In Linked List mode. at the end of a block (single or last block in repeated block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] + 0x18)." bitfld.long 0x1C 17. "DBUS,DBUS" "0,1" bitfld.long 0x1C 16. "SBUS,SBUS" "0,1" hexmask.long.byte 0x1C 0.--5. 1. "TSEL,TSEL" group.long 0xF0++0x7 line.long 0x0 "MDMA_C2MAR,In Linked List mode. at the end of a block (single or last block in repeated block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] + 0x20)." hexmask.long 0x0 0.--31. 1. "MAR,MAR" line.long 0x4 "MDMA_C2MDR,In Linked List mode. at the end of a block (single or last block in repeated block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] + 0x24)." hexmask.long 0x4 0.--31. 1. "MDR,MDR" rgroup.long 0x100++0x3 line.long 0x0 "MDMA_C3ISR,MDMA channel 3 interrupt/status register" bitfld.long 0x0 16. "CRQA,CRQA" "0,1" bitfld.long 0x0 4. "TCIF,TCIF" "0,1" bitfld.long 0x0 3. "BTIF,BTIF" "0,1" bitfld.long 0x0 2. "BRTIF,BRTIF" "0,1" bitfld.long 0x0 1. "CTCIF,CTCIF" "0,1" bitfld.long 0x0 0. "TEIF,TEIF" "0,1" wgroup.long 0x104++0x3 line.long 0x0 "MDMA_C3IFCR,MDMA channel 3 interrupt flag clear register" bitfld.long 0x0 4. "CLTCIF,CLTCIF" "0,1" bitfld.long 0x0 3. "CBTIF,CBTIF" "0,1" bitfld.long 0x0 2. "CBRTIF,CBRTIF" "0,1" bitfld.long 0x0 1. "CCTCIF,CCTCIF" "0,1" bitfld.long 0x0 0. "CTEIF,CTEIF" "0,1" rgroup.long 0x108++0x3 line.long 0x0 "MDMA_C3ESR,MDMA channel 3 error status register" bitfld.long 0x0 11. "BSE,BSE" "0,1" bitfld.long 0x0 10. "ASE,ASE" "0,1" bitfld.long 0x0 9. "TEMD,TEMD" "0,1" bitfld.long 0x0 8. "TELD,TELD" "0,1" bitfld.long 0x0 7. "TED,TED" "0,1" hexmask.long.byte 0x0 0.--6. 1. "TEA,TEA" group.long 0x10C++0x1F line.long 0x0 "MDMA_C3CR,This register is used to control the concerned channel." bitfld.long 0x0 16. "SWRQ,SWRQ" "0,1" bitfld.long 0x0 14. "WEX,WEX" "0,1" bitfld.long 0x0 13. "HEX,HEX" "0,1" bitfld.long 0x0 12. "BEX,BEX" "0,1" bitfld.long 0x0 6.--7. "PL,PL" "0,1,2,3" bitfld.long 0x0 5. "TCIE,TCIE" "0,1" bitfld.long 0x0 4. "BTIE,BTIE" "0,1" bitfld.long 0x0 3. "BRTIE,BRTIE" "0,1" bitfld.long 0x0 2. "CTCIE,CTCIE" "0,1" bitfld.long 0x0 1. "TEIE,TEIE" "0,1" newline bitfld.long 0x0 0. "EN,EN" "0,1" line.long 0x4 "MDMA_C3TCR,This register is used to configure the concerned channel. In Linked List mode. at the end of a block (single or last block in repeated block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] +.." bitfld.long 0x4 31. "BWM,BWM" "0,1" bitfld.long 0x4 30. "SWRM,SWRM" "0,1" bitfld.long 0x4 28.--29. "TRGM,TRGM" "0,1,2,3" bitfld.long 0x4 26.--27. "PAM,PAM" "0,1,2,3" bitfld.long 0x4 25. "PKE,PKE" "0,1" hexmask.long.byte 0x4 18.--24. 1. "TLEN,TLEN" bitfld.long 0x4 15.--17. "DBURST,DBURST" "0,1,2,3,4,5,6,7" bitfld.long 0x4 12.--14. "SBURST,SBURST" "0,1,2,3,4,5,6,7" bitfld.long 0x4 10.--11. "DINCOS,DINCOS" "0,1,2,3" bitfld.long 0x4 8.--9. "SINCOS,SINCOS" "0,1,2,3" newline bitfld.long 0x4 6.--7. "DSIZE,DSIZE" "0,1,2,3" bitfld.long 0x4 4.--5. "SSIZE,SSIZE" "0,1,2,3" bitfld.long 0x4 2.--3. "DINC,DINC" "0,1,2,3" bitfld.long 0x4 0.--1. "SINC,SINC" "0,1,2,3" line.long 0x8 "MDMA_C3BNDTR,In Linked List mode. at the end of a block (single or last block in repeated block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] + 0x04)." hexmask.long.word 0x8 20.--31. 1. "BRC,BRC" bitfld.long 0x8 19. "BRDUM,BRDUM" "0,1" bitfld.long 0x8 18. "BRSUM,BRSUM" "0,1" hexmask.long.tbyte 0x8 0.--16. 1. "BNDT,BNDT" line.long 0xC "MDMA_C3SAR,In Linked List mode. at the end of a Block (single or last Block in repeated Block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] + 0x08)." hexmask.long 0xC 0.--31. 1. "SAR,SAR" line.long 0x10 "MDMA_C3DAR,In Linked List mode. at the end of a block (single or last block in repeated block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M" hexmask.long 0x10 0.--31. 1. "DAR,DAR" line.long 0x14 "MDMA_C3BRUR,In Linked List mode. at the end of a block (single or last block in repeated block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] + 0x10)." hexmask.long.word 0x14 16.--31. 1. "DUV,DUV" hexmask.long.word 0x14 0.--15. 1. "SUV,SUV" line.long 0x18 "MDMA_C3LAR,In Linked List mode. at the end of a block (single or last block in repeated block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all.." hexmask.long 0x18 0.--31. 1. "LAR,LAR" line.long 0x1C "MDMA_C3TBR,In Linked List mode. at the end of a block (single or last block in repeated block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] + 0x18)." bitfld.long 0x1C 17. "DBUS,DBUS" "0,1" bitfld.long 0x1C 16. "SBUS,SBUS" "0,1" hexmask.long.byte 0x1C 0.--5. 1. "TSEL,TSEL" group.long 0x130++0x7 line.long 0x0 "MDMA_C3MAR,In Linked List mode. at the end of a block (single or last block in repeated block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] + 0x20)." hexmask.long 0x0 0.--31. 1. "MAR,MAR" line.long 0x4 "MDMA_C3MDR,In Linked List mode. at the end of a block (single or last block in repeated block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] + 0x24)." hexmask.long 0x4 0.--31. 1. "MDR,MDR" rgroup.long 0x140++0x3 line.long 0x0 "MDMA_C4ISR,MDMA channel 4 interrupt/status register" bitfld.long 0x0 16. "CRQA,CRQA" "0,1" bitfld.long 0x0 4. "TCIF,TCIF" "0,1" bitfld.long 0x0 3. "BTIF,BTIF" "0,1" bitfld.long 0x0 2. "BRTIF,BRTIF" "0,1" bitfld.long 0x0 1. "CTCIF,CTCIF" "0,1" bitfld.long 0x0 0. "TEIF,TEIF" "0,1" wgroup.long 0x144++0x3 line.long 0x0 "MDMA_C4IFCR,MDMA channel 4 interrupt flag clear register" bitfld.long 0x0 4. "CLTCIF,CLTCIF" "0,1" bitfld.long 0x0 3. "CBTIF,CBTIF" "0,1" bitfld.long 0x0 2. "CBRTIF,CBRTIF" "0,1" bitfld.long 0x0 1. "CCTCIF,CCTCIF" "0,1" bitfld.long 0x0 0. "CTEIF,CTEIF" "0,1" rgroup.long 0x148++0x3 line.long 0x0 "MDMA_C4ESR,MDMA channel 4 error status register" bitfld.long 0x0 11. "BSE,BSE" "0,1" bitfld.long 0x0 10. "ASE,ASE" "0,1" bitfld.long 0x0 9. "TEMD,TEMD" "0,1" bitfld.long 0x0 8. "TELD,TELD" "0,1" bitfld.long 0x0 7. "TED,TED" "0,1" hexmask.long.byte 0x0 0.--6. 1. "TEA,TEA" group.long 0x14C++0x1F line.long 0x0 "MDMA_C4CR,This register is used to control the concerned channel." bitfld.long 0x0 16. "SWRQ,SWRQ" "0,1" bitfld.long 0x0 14. "WEX,WEX" "0,1" bitfld.long 0x0 13. "HEX,HEX" "0,1" bitfld.long 0x0 12. "BEX,BEX" "0,1" bitfld.long 0x0 6.--7. "PL,PL" "0,1,2,3" bitfld.long 0x0 5. "TCIE,TCIE" "0,1" bitfld.long 0x0 4. "BTIE,BTIE" "0,1" bitfld.long 0x0 3. "BRTIE,BRTIE" "0,1" bitfld.long 0x0 2. "CTCIE,CTCIE" "0,1" bitfld.long 0x0 1. "TEIE,TEIE" "0,1" newline bitfld.long 0x0 0. "EN,EN" "0,1" line.long 0x4 "MDMA_C4TCR,This register is used to configure the concerned channel. In Linked List mode. at the end of a block (single or last block in repeated block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] +.." bitfld.long 0x4 31. "BWM,BWM" "0,1" bitfld.long 0x4 30. "SWRM,SWRM" "0,1" bitfld.long 0x4 28.--29. "TRGM,TRGM" "0,1,2,3" bitfld.long 0x4 26.--27. "PAM,PAM" "0,1,2,3" bitfld.long 0x4 25. "PKE,PKE" "0,1" hexmask.long.byte 0x4 18.--24. 1. "TLEN,TLEN" bitfld.long 0x4 15.--17. "DBURST,DBURST" "0,1,2,3,4,5,6,7" bitfld.long 0x4 12.--14. "SBURST,SBURST" "0,1,2,3,4,5,6,7" bitfld.long 0x4 10.--11. "DINCOS,DINCOS" "0,1,2,3" bitfld.long 0x4 8.--9. "SINCOS,SINCOS" "0,1,2,3" newline bitfld.long 0x4 6.--7. "DSIZE,DSIZE" "0,1,2,3" bitfld.long 0x4 4.--5. "SSIZE,SSIZE" "0,1,2,3" bitfld.long 0x4 2.--3. "DINC,DINC" "0,1,2,3" bitfld.long 0x4 0.--1. "SINC,SINC" "0,1,2,3" line.long 0x8 "MDMA_C4BNDTR,In Linked List mode. at the end of a block (single or last block in repeated block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] + 0x04)." hexmask.long.word 0x8 20.--31. 1. "BRC,BRC" bitfld.long 0x8 19. "BRDUM,BRDUM" "0,1" bitfld.long 0x8 18. "BRSUM,BRSUM" "0,1" hexmask.long.tbyte 0x8 0.--16. 1. "BNDT,BNDT" line.long 0xC "MDMA_C4SAR,In Linked List mode. at the end of a Block (single or last Block in repeated Block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] + 0x08)." hexmask.long 0xC 0.--31. 1. "SAR,SAR" line.long 0x10 "MDMA_C4DAR,In Linked List mode. at the end of a block (single or last block in repeated block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M" hexmask.long 0x10 0.--31. 1. "DAR,DAR" line.long 0x14 "MDMA_C4BRUR,In Linked List mode. at the end of a block (single or last block in repeated block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] + 0x10)." hexmask.long.word 0x14 16.--31. 1. "DUV,DUV" hexmask.long.word 0x14 0.--15. 1. "SUV,SUV" line.long 0x18 "MDMA_C4LAR,In Linked List mode. at the end of a block (single or last block in repeated block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all.." hexmask.long 0x18 0.--31. 1. "LAR,LAR" line.long 0x1C "MDMA_C4TBR,In Linked List mode. at the end of a block (single or last block in repeated block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] + 0x18)." bitfld.long 0x1C 17. "DBUS,DBUS" "0,1" bitfld.long 0x1C 16. "SBUS,SBUS" "0,1" hexmask.long.byte 0x1C 0.--5. 1. "TSEL,TSEL" group.long 0x170++0x7 line.long 0x0 "MDMA_C4MAR,In Linked List mode. at the end of a block (single or last block in repeated block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] + 0x20)." hexmask.long 0x0 0.--31. 1. "MAR,MAR" line.long 0x4 "MDMA_C4MDR,In Linked List mode. at the end of a block (single or last block in repeated block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] + 0x24)." hexmask.long 0x4 0.--31. 1. "MDR,MDR" rgroup.long 0x180++0x3 line.long 0x0 "MDMA_C5ISR,MDMA channel 5 interrupt/status register" bitfld.long 0x0 16. "CRQA,CRQA" "0,1" bitfld.long 0x0 4. "TCIF,TCIF" "0,1" bitfld.long 0x0 3. "BTIF,BTIF" "0,1" bitfld.long 0x0 2. "BRTIF,BRTIF" "0,1" bitfld.long 0x0 1. "CTCIF,CTCIF" "0,1" bitfld.long 0x0 0. "TEIF,TEIF" "0,1" wgroup.long 0x184++0x3 line.long 0x0 "MDMA_C5IFCR,MDMA channel 5 interrupt flag clear register" bitfld.long 0x0 4. "CLTCIF,CLTCIF" "0,1" bitfld.long 0x0 3. "CBTIF,CBTIF" "0,1" bitfld.long 0x0 2. "CBRTIF,CBRTIF" "0,1" bitfld.long 0x0 1. "CCTCIF,CCTCIF" "0,1" bitfld.long 0x0 0. "CTEIF,CTEIF" "0,1" rgroup.long 0x188++0x3 line.long 0x0 "MDMA_C5ESR,MDMA channel 5 error status register" bitfld.long 0x0 11. "BSE,BSE" "0,1" bitfld.long 0x0 10. "ASE,ASE" "0,1" bitfld.long 0x0 9. "TEMD,TEMD" "0,1" bitfld.long 0x0 8. "TELD,TELD" "0,1" bitfld.long 0x0 7. "TED,TED" "0,1" hexmask.long.byte 0x0 0.--6. 1. "TEA,TEA" group.long 0x18C++0x1F line.long 0x0 "MDMA_C5CR,This register is used to control the concerned channel." bitfld.long 0x0 16. "SWRQ,SWRQ" "0,1" bitfld.long 0x0 14. "WEX,WEX" "0,1" bitfld.long 0x0 13. "HEX,HEX" "0,1" bitfld.long 0x0 12. "BEX,BEX" "0,1" bitfld.long 0x0 6.--7. "PL,PL" "0,1,2,3" bitfld.long 0x0 5. "TCIE,TCIE" "0,1" bitfld.long 0x0 4. "BTIE,BTIE" "0,1" bitfld.long 0x0 3. "BRTIE,BRTIE" "0,1" bitfld.long 0x0 2. "CTCIE,CTCIE" "0,1" bitfld.long 0x0 1. "TEIE,TEIE" "0,1" newline bitfld.long 0x0 0. "EN,EN" "0,1" line.long 0x4 "MDMA_C5TCR,This register is used to configure the concerned channel. In Linked List mode. at the end of a block (single or last block in repeated block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] +.." bitfld.long 0x4 31. "BWM,BWM" "0,1" bitfld.long 0x4 30. "SWRM,SWRM" "0,1" bitfld.long 0x4 28.--29. "TRGM,TRGM" "0,1,2,3" bitfld.long 0x4 26.--27. "PAM,PAM" "0,1,2,3" bitfld.long 0x4 25. "PKE,PKE" "0,1" hexmask.long.byte 0x4 18.--24. 1. "TLEN,TLEN" bitfld.long 0x4 15.--17. "DBURST,DBURST" "0,1,2,3,4,5,6,7" bitfld.long 0x4 12.--14. "SBURST,SBURST" "0,1,2,3,4,5,6,7" bitfld.long 0x4 10.--11. "DINCOS,DINCOS" "0,1,2,3" bitfld.long 0x4 8.--9. "SINCOS,SINCOS" "0,1,2,3" newline bitfld.long 0x4 6.--7. "DSIZE,DSIZE" "0,1,2,3" bitfld.long 0x4 4.--5. "SSIZE,SSIZE" "0,1,2,3" bitfld.long 0x4 2.--3. "DINC,DINC" "0,1,2,3" bitfld.long 0x4 0.--1. "SINC,SINC" "0,1,2,3" line.long 0x8 "MDMA_C5BNDTR,In Linked List mode. at the end of a block (single or last block in repeated block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] + 0x04)." hexmask.long.word 0x8 20.--31. 1. "BRC,BRC" bitfld.long 0x8 19. "BRDUM,BRDUM" "0,1" bitfld.long 0x8 18. "BRSUM,BRSUM" "0,1" hexmask.long.tbyte 0x8 0.--16. 1. "BNDT,BNDT" line.long 0xC "MDMA_C5SAR,In Linked List mode. at the end of a Block (single or last Block in repeated Block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] + 0x08)." hexmask.long 0xC 0.--31. 1. "SAR,SAR" line.long 0x10 "MDMA_C5DAR,In Linked List mode. at the end of a block (single or last block in repeated block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M" hexmask.long 0x10 0.--31. 1. "DAR,DAR" line.long 0x14 "MDMA_C5BRUR,In Linked List mode. at the end of a block (single or last block in repeated block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] + 0x10)." hexmask.long.word 0x14 16.--31. 1. "DUV,DUV" hexmask.long.word 0x14 0.--15. 1. "SUV,SUV" line.long 0x18 "MDMA_C5LAR,In Linked List mode. at the end of a block (single or last block in repeated block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all.." hexmask.long 0x18 0.--31. 1. "LAR,LAR" line.long 0x1C "MDMA_C5TBR,In Linked List mode. at the end of a block (single or last block in repeated block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] + 0x18)." bitfld.long 0x1C 17. "DBUS,DBUS" "0,1" bitfld.long 0x1C 16. "SBUS,SBUS" "0,1" hexmask.long.byte 0x1C 0.--5. 1. "TSEL,TSEL" group.long 0x1B0++0x7 line.long 0x0 "MDMA_C5MAR,In Linked List mode. at the end of a block (single or last block in repeated block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] + 0x20)." hexmask.long 0x0 0.--31. 1. "MAR,MAR" line.long 0x4 "MDMA_C5MDR,In Linked List mode. at the end of a block (single or last block in repeated block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] + 0x24)." hexmask.long 0x4 0.--31. 1. "MDR,MDR" rgroup.long 0x1C0++0x3 line.long 0x0 "MDMA_C6ISR,MDMA channel 6 interrupt/status register" bitfld.long 0x0 16. "CRQA,CRQA" "0,1" bitfld.long 0x0 4. "TCIF,TCIF" "0,1" bitfld.long 0x0 3. "BTIF,BTIF" "0,1" bitfld.long 0x0 2. "BRTIF,BRTIF" "0,1" bitfld.long 0x0 1. "CTCIF,CTCIF" "0,1" bitfld.long 0x0 0. "TEIF,TEIF" "0,1" wgroup.long 0x1C4++0x3 line.long 0x0 "MDMA_C6IFCR,MDMA channel 6 interrupt flag clear register" bitfld.long 0x0 4. "CLTCIF,CLTCIF" "0,1" bitfld.long 0x0 3. "CBTIF,CBTIF" "0,1" bitfld.long 0x0 2. "CBRTIF,CBRTIF" "0,1" bitfld.long 0x0 1. "CCTCIF,CCTCIF" "0,1" bitfld.long 0x0 0. "CTEIF,CTEIF" "0,1" rgroup.long 0x1C8++0x3 line.long 0x0 "MDMA_C6ESR,MDMA channel 6 error status register" bitfld.long 0x0 11. "BSE,BSE" "0,1" bitfld.long 0x0 10. "ASE,ASE" "0,1" bitfld.long 0x0 9. "TEMD,TEMD" "0,1" bitfld.long 0x0 8. "TELD,TELD" "0,1" bitfld.long 0x0 7. "TED,TED" "0,1" hexmask.long.byte 0x0 0.--6. 1. "TEA,TEA" group.long 0x1CC++0x1F line.long 0x0 "MDMA_C6CR,This register is used to control the concerned channel." bitfld.long 0x0 16. "SWRQ,SWRQ" "0,1" bitfld.long 0x0 14. "WEX,WEX" "0,1" bitfld.long 0x0 13. "HEX,HEX" "0,1" bitfld.long 0x0 12. "BEX,BEX" "0,1" bitfld.long 0x0 6.--7. "PL,PL" "0,1,2,3" bitfld.long 0x0 5. "TCIE,TCIE" "0,1" bitfld.long 0x0 4. "BTIE,BTIE" "0,1" bitfld.long 0x0 3. "BRTIE,BRTIE" "0,1" bitfld.long 0x0 2. "CTCIE,CTCIE" "0,1" bitfld.long 0x0 1. "TEIE,TEIE" "0,1" newline bitfld.long 0x0 0. "EN,EN" "0,1" line.long 0x4 "MDMA_C6TCR,This register is used to configure the concerned channel. In Linked List mode. at the end of a block (single or last block in repeated block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] +.." bitfld.long 0x4 31. "BWM,BWM" "0,1" bitfld.long 0x4 30. "SWRM,SWRM" "0,1" bitfld.long 0x4 28.--29. "TRGM,TRGM" "0,1,2,3" bitfld.long 0x4 26.--27. "PAM,PAM" "0,1,2,3" bitfld.long 0x4 25. "PKE,PKE" "0,1" hexmask.long.byte 0x4 18.--24. 1. "TLEN,TLEN" bitfld.long 0x4 15.--17. "DBURST,DBURST" "0,1,2,3,4,5,6,7" bitfld.long 0x4 12.--14. "SBURST,SBURST" "0,1,2,3,4,5,6,7" bitfld.long 0x4 10.--11. "DINCOS,DINCOS" "0,1,2,3" bitfld.long 0x4 8.--9. "SINCOS,SINCOS" "0,1,2,3" newline bitfld.long 0x4 6.--7. "DSIZE,DSIZE" "0,1,2,3" bitfld.long 0x4 4.--5. "SSIZE,SSIZE" "0,1,2,3" bitfld.long 0x4 2.--3. "DINC,DINC" "0,1,2,3" bitfld.long 0x4 0.--1. "SINC,SINC" "0,1,2,3" line.long 0x8 "MDMA_C6BNDTR,In Linked List mode. at the end of a block (single or last block in repeated block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] + 0x04)." hexmask.long.word 0x8 20.--31. 1. "BRC,BRC" bitfld.long 0x8 19. "BRDUM,BRDUM" "0,1" bitfld.long 0x8 18. "BRSUM,BRSUM" "0,1" hexmask.long.tbyte 0x8 0.--16. 1. "BNDT,BNDT" line.long 0xC "MDMA_C6SAR,In Linked List mode. at the end of a Block (single or last Block in repeated Block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] + 0x08)." hexmask.long 0xC 0.--31. 1. "SAR,SAR" line.long 0x10 "MDMA_C6DAR,In Linked List mode. at the end of a block (single or last block in repeated block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M" hexmask.long 0x10 0.--31. 1. "DAR,DAR" line.long 0x14 "MDMA_C6BRUR,In Linked List mode. at the end of a block (single or last block in repeated block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] + 0x10)." hexmask.long.word 0x14 16.--31. 1. "DUV,DUV" hexmask.long.word 0x14 0.--15. 1. "SUV,SUV" line.long 0x18 "MDMA_C6LAR,In Linked List mode. at the end of a block (single or last block in repeated block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all.." hexmask.long 0x18 0.--31. 1. "LAR,LAR" line.long 0x1C "MDMA_C6TBR,In Linked List mode. at the end of a block (single or last block in repeated block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] + 0x18)." bitfld.long 0x1C 17. "DBUS,DBUS" "0,1" bitfld.long 0x1C 16. "SBUS,SBUS" "0,1" hexmask.long.byte 0x1C 0.--5. 1. "TSEL,TSEL" group.long 0x1F0++0x7 line.long 0x0 "MDMA_C6MAR,In Linked List mode. at the end of a block (single or last block in repeated block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] + 0x20)." hexmask.long 0x0 0.--31. 1. "MAR,MAR" line.long 0x4 "MDMA_C6MDR,In Linked List mode. at the end of a block (single or last block in repeated block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] + 0x24)." hexmask.long 0x4 0.--31. 1. "MDR,MDR" rgroup.long 0x200++0x3 line.long 0x0 "MDMA_C7ISR,MDMA channel 7 interrupt/status register" bitfld.long 0x0 16. "CRQA,CRQA" "0,1" bitfld.long 0x0 4. "TCIF,TCIF" "0,1" bitfld.long 0x0 3. "BTIF,BTIF" "0,1" bitfld.long 0x0 2. "BRTIF,BRTIF" "0,1" bitfld.long 0x0 1. "CTCIF,CTCIF" "0,1" bitfld.long 0x0 0. "TEIF,TEIF" "0,1" wgroup.long 0x204++0x3 line.long 0x0 "MDMA_C7IFCR,MDMA channel 7 interrupt flag clear register" bitfld.long 0x0 4. "CLTCIF,CLTCIF" "0,1" bitfld.long 0x0 3. "CBTIF,CBTIF" "0,1" bitfld.long 0x0 2. "CBRTIF,CBRTIF" "0,1" bitfld.long 0x0 1. "CCTCIF,CCTCIF" "0,1" bitfld.long 0x0 0. "CTEIF,CTEIF" "0,1" rgroup.long 0x208++0x3 line.long 0x0 "MDMA_C7ESR,MDMA channel 7 error status register" bitfld.long 0x0 11. "BSE,BSE" "0,1" bitfld.long 0x0 10. "ASE,ASE" "0,1" bitfld.long 0x0 9. "TEMD,TEMD" "0,1" bitfld.long 0x0 8. "TELD,TELD" "0,1" bitfld.long 0x0 7. "TED,TED" "0,1" hexmask.long.byte 0x0 0.--6. 1. "TEA,TEA" group.long 0x20C++0x1F line.long 0x0 "MDMA_C7CR,This register is used to control the concerned channel." bitfld.long 0x0 16. "SWRQ,SWRQ" "0,1" bitfld.long 0x0 14. "WEX,WEX" "0,1" bitfld.long 0x0 13. "HEX,HEX" "0,1" bitfld.long 0x0 12. "BEX,BEX" "0,1" bitfld.long 0x0 6.--7. "PL,PL" "0,1,2,3" bitfld.long 0x0 5. "TCIE,TCIE" "0,1" bitfld.long 0x0 4. "BTIE,BTIE" "0,1" bitfld.long 0x0 3. "BRTIE,BRTIE" "0,1" bitfld.long 0x0 2. "CTCIE,CTCIE" "0,1" bitfld.long 0x0 1. "TEIE,TEIE" "0,1" newline bitfld.long 0x0 0. "EN,EN" "0,1" line.long 0x4 "MDMA_C7TCR,This register is used to configure the concerned channel. In Linked List mode. at the end of a block (single or last block in repeated block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] +.." bitfld.long 0x4 31. "BWM,BWM" "0,1" bitfld.long 0x4 30. "SWRM,SWRM" "0,1" bitfld.long 0x4 28.--29. "TRGM,TRGM" "0,1,2,3" bitfld.long 0x4 26.--27. "PAM,PAM" "0,1,2,3" bitfld.long 0x4 25. "PKE,PKE" "0,1" hexmask.long.byte 0x4 18.--24. 1. "TLEN,TLEN" bitfld.long 0x4 15.--17. "DBURST,DBURST" "0,1,2,3,4,5,6,7" bitfld.long 0x4 12.--14. "SBURST,SBURST" "0,1,2,3,4,5,6,7" bitfld.long 0x4 10.--11. "DINCOS,DINCOS" "0,1,2,3" bitfld.long 0x4 8.--9. "SINCOS,SINCOS" "0,1,2,3" newline bitfld.long 0x4 6.--7. "DSIZE,DSIZE" "0,1,2,3" bitfld.long 0x4 4.--5. "SSIZE,SSIZE" "0,1,2,3" bitfld.long 0x4 2.--3. "DINC,DINC" "0,1,2,3" bitfld.long 0x4 0.--1. "SINC,SINC" "0,1,2,3" line.long 0x8 "MDMA_C7BNDTR,In Linked List mode. at the end of a block (single or last block in repeated block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] + 0x04)." hexmask.long.word 0x8 20.--31. 1. "BRC,BRC" bitfld.long 0x8 19. "BRDUM,BRDUM" "0,1" bitfld.long 0x8 18. "BRSUM,BRSUM" "0,1" hexmask.long.tbyte 0x8 0.--16. 1. "BNDT,BNDT" line.long 0xC "MDMA_C7SAR,In Linked List mode. at the end of a Block (single or last Block in repeated Block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] + 0x08)." hexmask.long 0xC 0.--31. 1. "SAR,SAR" line.long 0x10 "MDMA_C7DAR,In Linked List mode. at the end of a block (single or last block in repeated block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M" hexmask.long 0x10 0.--31. 1. "DAR,DAR" line.long 0x14 "MDMA_C7BRUR,In Linked List mode. at the end of a block (single or last block in repeated block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] + 0x10)." hexmask.long.word 0x14 16.--31. 1. "DUV,DUV" hexmask.long.word 0x14 0.--15. 1. "SUV,SUV" line.long 0x18 "MDMA_C7LAR,In Linked List mode. at the end of a block (single or last block in repeated block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all.." hexmask.long 0x18 0.--31. 1. "LAR,LAR" line.long 0x1C "MDMA_C7TBR,In Linked List mode. at the end of a block (single or last block in repeated block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] + 0x18)." bitfld.long 0x1C 17. "DBUS,DBUS" "0,1" bitfld.long 0x1C 16. "SBUS,SBUS" "0,1" hexmask.long.byte 0x1C 0.--5. 1. "TSEL,TSEL" group.long 0x230++0x7 line.long 0x0 "MDMA_C7MAR,In Linked List mode. at the end of a block (single or last block in repeated block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] + 0x20)." hexmask.long 0x0 0.--31. 1. "MAR,MAR" line.long 0x4 "MDMA_C7MDR,In Linked List mode. at the end of a block (single or last block in repeated block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] + 0x24)." hexmask.long 0x4 0.--31. 1. "MDR,MDR" rgroup.long 0x240++0x3 line.long 0x0 "MDMA_C8ISR,MDMA channel 8 interrupt/status register" bitfld.long 0x0 16. "CRQA,CRQA" "0,1" bitfld.long 0x0 4. "TCIF,TCIF" "0,1" bitfld.long 0x0 3. "BTIF,BTIF" "0,1" bitfld.long 0x0 2. "BRTIF,BRTIF" "0,1" bitfld.long 0x0 1. "CTCIF,CTCIF" "0,1" bitfld.long 0x0 0. "TEIF,TEIF" "0,1" wgroup.long 0x244++0x3 line.long 0x0 "MDMA_C8IFCR,MDMA channel 8 interrupt flag clear register" bitfld.long 0x0 4. "CLTCIF,CLTCIF" "0,1" bitfld.long 0x0 3. "CBTIF,CBTIF" "0,1" bitfld.long 0x0 2. "CBRTIF,CBRTIF" "0,1" bitfld.long 0x0 1. "CCTCIF,CCTCIF" "0,1" bitfld.long 0x0 0. "CTEIF,CTEIF" "0,1" rgroup.long 0x248++0x3 line.long 0x0 "MDMA_C8ESR,MDMA channel 8 error status register" bitfld.long 0x0 11. "BSE,BSE" "0,1" bitfld.long 0x0 10. "ASE,ASE" "0,1" bitfld.long 0x0 9. "TEMD,TEMD" "0,1" bitfld.long 0x0 8. "TELD,TELD" "0,1" bitfld.long 0x0 7. "TED,TED" "0,1" hexmask.long.byte 0x0 0.--6. 1. "TEA,TEA" group.long 0x24C++0x1F line.long 0x0 "MDMA_C8CR,This register is used to control the concerned channel." bitfld.long 0x0 16. "SWRQ,SWRQ" "0,1" bitfld.long 0x0 14. "WEX,WEX" "0,1" bitfld.long 0x0 13. "HEX,HEX" "0,1" bitfld.long 0x0 12. "BEX,BEX" "0,1" bitfld.long 0x0 6.--7. "PL,PL" "0,1,2,3" bitfld.long 0x0 5. "TCIE,TCIE" "0,1" bitfld.long 0x0 4. "BTIE,BTIE" "0,1" bitfld.long 0x0 3. "BRTIE,BRTIE" "0,1" bitfld.long 0x0 2. "CTCIE,CTCIE" "0,1" bitfld.long 0x0 1. "TEIE,TEIE" "0,1" newline bitfld.long 0x0 0. "EN,EN" "0,1" line.long 0x4 "MDMA_C8TCR,This register is used to configure the concerned channel. In Linked List mode. at the end of a block (single or last block in repeated block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] +.." bitfld.long 0x4 31. "BWM,BWM" "0,1" bitfld.long 0x4 30. "SWRM,SWRM" "0,1" bitfld.long 0x4 28.--29. "TRGM,TRGM" "0,1,2,3" bitfld.long 0x4 26.--27. "PAM,PAM" "0,1,2,3" bitfld.long 0x4 25. "PKE,PKE" "0,1" hexmask.long.byte 0x4 18.--24. 1. "TLEN,TLEN" bitfld.long 0x4 15.--17. "DBURST,DBURST" "0,1,2,3,4,5,6,7" bitfld.long 0x4 12.--14. "SBURST,SBURST" "0,1,2,3,4,5,6,7" bitfld.long 0x4 10.--11. "DINCOS,DINCOS" "0,1,2,3" bitfld.long 0x4 8.--9. "SINCOS,SINCOS" "0,1,2,3" newline bitfld.long 0x4 6.--7. "DSIZE,DSIZE" "0,1,2,3" bitfld.long 0x4 4.--5. "SSIZE,SSIZE" "0,1,2,3" bitfld.long 0x4 2.--3. "DINC,DINC" "0,1,2,3" bitfld.long 0x4 0.--1. "SINC,SINC" "0,1,2,3" line.long 0x8 "MDMA_C8BNDTR,In Linked List mode. at the end of a block (single or last block in repeated block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] + 0x04)." hexmask.long.word 0x8 20.--31. 1. "BRC,BRC" bitfld.long 0x8 19. "BRDUM,BRDUM" "0,1" bitfld.long 0x8 18. "BRSUM,BRSUM" "0,1" hexmask.long.tbyte 0x8 0.--16. 1. "BNDT,BNDT" line.long 0xC "MDMA_C8SAR,In Linked List mode. at the end of a Block (single or last Block in repeated Block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] + 0x08)." hexmask.long 0xC 0.--31. 1. "SAR,SAR" line.long 0x10 "MDMA_C8DAR,In Linked List mode. at the end of a block (single or last block in repeated block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M" hexmask.long 0x10 0.--31. 1. "DAR,DAR" line.long 0x14 "MDMA_C8BRUR,In Linked List mode. at the end of a block (single or last block in repeated block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] + 0x10)." hexmask.long.word 0x14 16.--31. 1. "DUV,DUV" hexmask.long.word 0x14 0.--15. 1. "SUV,SUV" line.long 0x18 "MDMA_C8LAR,In Linked List mode. at the end of a block (single or last block in repeated block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all.." hexmask.long 0x18 0.--31. 1. "LAR,LAR" line.long 0x1C "MDMA_C8TBR,In Linked List mode. at the end of a block (single or last block in repeated block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] + 0x18)." bitfld.long 0x1C 17. "DBUS,DBUS" "0,1" bitfld.long 0x1C 16. "SBUS,SBUS" "0,1" hexmask.long.byte 0x1C 0.--5. 1. "TSEL,TSEL" group.long 0x270++0x7 line.long 0x0 "MDMA_C8MAR,In Linked List mode. at the end of a block (single or last block in repeated block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] + 0x20)." hexmask.long 0x0 0.--31. 1. "MAR,MAR" line.long 0x4 "MDMA_C8MDR,In Linked List mode. at the end of a block (single or last block in repeated block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] + 0x24)." hexmask.long 0x4 0.--31. 1. "MDR,MDR" rgroup.long 0x280++0x3 line.long 0x0 "MDMA_C9ISR,MDMA channel 9 interrupt/status register" bitfld.long 0x0 16. "CRQA,CRQA" "0,1" bitfld.long 0x0 4. "TCIF,TCIF" "0,1" bitfld.long 0x0 3. "BTIF,BTIF" "0,1" bitfld.long 0x0 2. "BRTIF,BRTIF" "0,1" bitfld.long 0x0 1. "CTCIF,CTCIF" "0,1" bitfld.long 0x0 0. "TEIF,TEIF" "0,1" wgroup.long 0x284++0x3 line.long 0x0 "MDMA_C9IFCR,MDMA channel 9 interrupt flag clear register" bitfld.long 0x0 4. "CLTCIF,CLTCIF" "0,1" bitfld.long 0x0 3. "CBTIF,CBTIF" "0,1" bitfld.long 0x0 2. "CBRTIF,CBRTIF" "0,1" bitfld.long 0x0 1. "CCTCIF,CCTCIF" "0,1" bitfld.long 0x0 0. "CTEIF,CTEIF" "0,1" rgroup.long 0x288++0x3 line.long 0x0 "MDMA_C9ESR,MDMA channel 9 error status register" bitfld.long 0x0 11. "BSE,BSE" "0,1" bitfld.long 0x0 10. "ASE,ASE" "0,1" bitfld.long 0x0 9. "TEMD,TEMD" "0,1" bitfld.long 0x0 8. "TELD,TELD" "0,1" bitfld.long 0x0 7. "TED,TED" "0,1" hexmask.long.byte 0x0 0.--6. 1. "TEA,TEA" group.long 0x28C++0x1F line.long 0x0 "MDMA_C9CR,This register is used to control the concerned channel." bitfld.long 0x0 16. "SWRQ,SWRQ" "0,1" bitfld.long 0x0 14. "WEX,WEX" "0,1" bitfld.long 0x0 13. "HEX,HEX" "0,1" bitfld.long 0x0 12. "BEX,BEX" "0,1" bitfld.long 0x0 6.--7. "PL,PL" "0,1,2,3" bitfld.long 0x0 5. "TCIE,TCIE" "0,1" bitfld.long 0x0 4. "BTIE,BTIE" "0,1" bitfld.long 0x0 3. "BRTIE,BRTIE" "0,1" bitfld.long 0x0 2. "CTCIE,CTCIE" "0,1" bitfld.long 0x0 1. "TEIE,TEIE" "0,1" newline bitfld.long 0x0 0. "EN,EN" "0,1" line.long 0x4 "MDMA_C9TCR,This register is used to configure the concerned channel. In Linked List mode. at the end of a block (single or last block in repeated block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] +.." bitfld.long 0x4 31. "BWM,BWM" "0,1" bitfld.long 0x4 30. "SWRM,SWRM" "0,1" bitfld.long 0x4 28.--29. "TRGM,TRGM" "0,1,2,3" bitfld.long 0x4 26.--27. "PAM,PAM" "0,1,2,3" bitfld.long 0x4 25. "PKE,PKE" "0,1" hexmask.long.byte 0x4 18.--24. 1. "TLEN,TLEN" bitfld.long 0x4 15.--17. "DBURST,DBURST" "0,1,2,3,4,5,6,7" bitfld.long 0x4 12.--14. "SBURST,SBURST" "0,1,2,3,4,5,6,7" bitfld.long 0x4 10.--11. "DINCOS,DINCOS" "0,1,2,3" bitfld.long 0x4 8.--9. "SINCOS,SINCOS" "0,1,2,3" newline bitfld.long 0x4 6.--7. "DSIZE,DSIZE" "0,1,2,3" bitfld.long 0x4 4.--5. "SSIZE,SSIZE" "0,1,2,3" bitfld.long 0x4 2.--3. "DINC,DINC" "0,1,2,3" bitfld.long 0x4 0.--1. "SINC,SINC" "0,1,2,3" line.long 0x8 "MDMA_C9BNDTR,In Linked List mode. at the end of a block (single or last block in repeated block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] + 0x04)." hexmask.long.word 0x8 20.--31. 1. "BRC,BRC" bitfld.long 0x8 19. "BRDUM,BRDUM" "0,1" bitfld.long 0x8 18. "BRSUM,BRSUM" "0,1" hexmask.long.tbyte 0x8 0.--16. 1. "BNDT,BNDT" line.long 0xC "MDMA_C9SAR,In Linked List mode. at the end of a Block (single or last Block in repeated Block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] + 0x08)." hexmask.long 0xC 0.--31. 1. "SAR,SAR" line.long 0x10 "MDMA_C9DAR,In Linked List mode. at the end of a block (single or last block in repeated block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M" hexmask.long 0x10 0.--31. 1. "DAR,DAR" line.long 0x14 "MDMA_C9BRUR,In Linked List mode. at the end of a block (single or last block in repeated block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] + 0x10)." hexmask.long.word 0x14 16.--31. 1. "DUV,DUV" hexmask.long.word 0x14 0.--15. 1. "SUV,SUV" line.long 0x18 "MDMA_C9LAR,In Linked List mode. at the end of a block (single or last block in repeated block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all.." hexmask.long 0x18 0.--31. 1. "LAR,LAR" line.long 0x1C "MDMA_C9TBR,In Linked List mode. at the end of a block (single or last block in repeated block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] + 0x18)." bitfld.long 0x1C 17. "DBUS,DBUS" "0,1" bitfld.long 0x1C 16. "SBUS,SBUS" "0,1" hexmask.long.byte 0x1C 0.--5. 1. "TSEL,TSEL" group.long 0x2B0++0x7 line.long 0x0 "MDMA_C9MAR,In Linked List mode. at the end of a block (single or last block in repeated block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] + 0x20)." hexmask.long 0x0 0.--31. 1. "MAR,MAR" line.long 0x4 "MDMA_C9MDR,In Linked List mode. at the end of a block (single or last block in repeated block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] + 0x24)." hexmask.long 0x4 0.--31. 1. "MDR,MDR" rgroup.long 0x2C0++0x3 line.long 0x0 "MDMA_C10ISR,MDMA channel 10 interrupt/status register" bitfld.long 0x0 16. "CRQA,CRQA" "0,1" bitfld.long 0x0 4. "TCIF,TCIF" "0,1" bitfld.long 0x0 3. "BTIF,BTIF" "0,1" bitfld.long 0x0 2. "BRTIF,BRTIF" "0,1" bitfld.long 0x0 1. "CTCIF,CTCIF" "0,1" bitfld.long 0x0 0. "TEIF,TEIF" "0,1" wgroup.long 0x2C4++0x3 line.long 0x0 "MDMA_C10IFCR,MDMA channel 10 interrupt flag clear register" bitfld.long 0x0 4. "CLTCIF,CLTCIF" "0,1" bitfld.long 0x0 3. "CBTIF,CBTIF" "0,1" bitfld.long 0x0 2. "CBRTIF,CBRTIF" "0,1" bitfld.long 0x0 1. "CCTCIF,CCTCIF" "0,1" bitfld.long 0x0 0. "CTEIF,CTEIF" "0,1" rgroup.long 0x2C8++0x3 line.long 0x0 "MDMA_C10ESR,MDMA channel 10 error status register" bitfld.long 0x0 11. "BSE,BSE" "0,1" bitfld.long 0x0 10. "ASE,ASE" "0,1" bitfld.long 0x0 9. "TEMD,TEMD" "0,1" bitfld.long 0x0 8. "TELD,TELD" "0,1" bitfld.long 0x0 7. "TED,TED" "0,1" hexmask.long.byte 0x0 0.--6. 1. "TEA,TEA" group.long 0x2CC++0x1F line.long 0x0 "MDMA_C10CR,This register is used to control the concerned channel." bitfld.long 0x0 16. "SWRQ,SWRQ" "0,1" bitfld.long 0x0 14. "WEX,WEX" "0,1" bitfld.long 0x0 13. "HEX,HEX" "0,1" bitfld.long 0x0 12. "BEX,BEX" "0,1" bitfld.long 0x0 6.--7. "PL,PL" "0,1,2,3" bitfld.long 0x0 5. "TCIE,TCIE" "0,1" bitfld.long 0x0 4. "BTIE,BTIE" "0,1" bitfld.long 0x0 3. "BRTIE,BRTIE" "0,1" bitfld.long 0x0 2. "CTCIE,CTCIE" "0,1" bitfld.long 0x0 1. "TEIE,TEIE" "0,1" newline bitfld.long 0x0 0. "EN,EN" "0,1" line.long 0x4 "MDMA_C10TCR,This register is used to configure the concerned channel. In Linked List mode. at the end of a block (single or last block in repeated block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] +.." bitfld.long 0x4 31. "BWM,BWM" "0,1" bitfld.long 0x4 30. "SWRM,SWRM" "0,1" bitfld.long 0x4 28.--29. "TRGM,TRGM" "0,1,2,3" bitfld.long 0x4 26.--27. "PAM,PAM" "0,1,2,3" bitfld.long 0x4 25. "PKE,PKE" "0,1" hexmask.long.byte 0x4 18.--24. 1. "TLEN,TLEN" bitfld.long 0x4 15.--17. "DBURST,DBURST" "0,1,2,3,4,5,6,7" bitfld.long 0x4 12.--14. "SBURST,SBURST" "0,1,2,3,4,5,6,7" bitfld.long 0x4 10.--11. "DINCOS,DINCOS" "0,1,2,3" bitfld.long 0x4 8.--9. "SINCOS,SINCOS" "0,1,2,3" newline bitfld.long 0x4 6.--7. "DSIZE,DSIZE" "0,1,2,3" bitfld.long 0x4 4.--5. "SSIZE,SSIZE" "0,1,2,3" bitfld.long 0x4 2.--3. "DINC,DINC" "0,1,2,3" bitfld.long 0x4 0.--1. "SINC,SINC" "0,1,2,3" line.long 0x8 "MDMA_C10BNDTR,In Linked List mode. at the end of a block (single or last block in repeated block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] + 0x04)." hexmask.long.word 0x8 20.--31. 1. "BRC,BRC" bitfld.long 0x8 19. "BRDUM,BRDUM" "0,1" bitfld.long 0x8 18. "BRSUM,BRSUM" "0,1" hexmask.long.tbyte 0x8 0.--16. 1. "BNDT,BNDT" line.long 0xC "MDMA_C10SAR,In Linked List mode. at the end of a Block (single or last Block in repeated Block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] + 0x08)." hexmask.long 0xC 0.--31. 1. "SAR,SAR" line.long 0x10 "MDMA_C10DAR,In Linked List mode. at the end of a block (single or last block in repeated block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M" hexmask.long 0x10 0.--31. 1. "DAR,DAR" line.long 0x14 "MDMA_C10BRUR,In Linked List mode. at the end of a block (single or last block in repeated block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] + 0x10)." hexmask.long.word 0x14 16.--31. 1. "DUV,DUV" hexmask.long.word 0x14 0.--15. 1. "SUV,SUV" line.long 0x18 "MDMA_C10LAR,In Linked List mode. at the end of a block (single or last block in repeated block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all.." hexmask.long 0x18 0.--31. 1. "LAR,LAR" line.long 0x1C "MDMA_C10TBR,In Linked List mode. at the end of a block (single or last block in repeated block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] + 0x18)." bitfld.long 0x1C 17. "DBUS,DBUS" "0,1" bitfld.long 0x1C 16. "SBUS,SBUS" "0,1" hexmask.long.byte 0x1C 0.--5. 1. "TSEL,TSEL" group.long 0x2F0++0x7 line.long 0x0 "MDMA_C10MAR,In Linked List mode. at the end of a block (single or last block in repeated block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] + 0x20)." hexmask.long 0x0 0.--31. 1. "MAR,MAR" line.long 0x4 "MDMA_C10MDR,In Linked List mode. at the end of a block (single or last block in repeated block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] + 0x24)." hexmask.long 0x4 0.--31. 1. "MDR,MDR" rgroup.long 0x300++0x3 line.long 0x0 "MDMA_C11ISR,MDMA channel 11 interrupt/status register" bitfld.long 0x0 16. "CRQA,CRQA" "0,1" bitfld.long 0x0 4. "TCIF,TCIF" "0,1" bitfld.long 0x0 3. "BTIF,BTIF" "0,1" bitfld.long 0x0 2. "BRTIF,BRTIF" "0,1" bitfld.long 0x0 1. "CTCIF,CTCIF" "0,1" bitfld.long 0x0 0. "TEIF,TEIF" "0,1" wgroup.long 0x304++0x3 line.long 0x0 "MDMA_C11IFCR,MDMA channel 11 interrupt flag clear register" bitfld.long 0x0 4. "CLTCIF,CLTCIF" "0,1" bitfld.long 0x0 3. "CBTIF,CBTIF" "0,1" bitfld.long 0x0 2. "CBRTIF,CBRTIF" "0,1" bitfld.long 0x0 1. "CCTCIF,CCTCIF" "0,1" bitfld.long 0x0 0. "CTEIF,CTEIF" "0,1" rgroup.long 0x308++0x3 line.long 0x0 "MDMA_C11ESR,MDMA channel 11 error status register" bitfld.long 0x0 11. "BSE,BSE" "0,1" bitfld.long 0x0 10. "ASE,ASE" "0,1" bitfld.long 0x0 9. "TEMD,TEMD" "0,1" bitfld.long 0x0 8. "TELD,TELD" "0,1" bitfld.long 0x0 7. "TED,TED" "0,1" hexmask.long.byte 0x0 0.--6. 1. "TEA,TEA" group.long 0x30C++0x1F line.long 0x0 "MDMA_C11CR,This register is used to control the concerned channel." bitfld.long 0x0 16. "SWRQ,SWRQ" "0,1" bitfld.long 0x0 14. "WEX,WEX" "0,1" bitfld.long 0x0 13. "HEX,HEX" "0,1" bitfld.long 0x0 12. "BEX,BEX" "0,1" bitfld.long 0x0 6.--7. "PL,PL" "0,1,2,3" bitfld.long 0x0 5. "TCIE,TCIE" "0,1" bitfld.long 0x0 4. "BTIE,BTIE" "0,1" bitfld.long 0x0 3. "BRTIE,BRTIE" "0,1" bitfld.long 0x0 2. "CTCIE,CTCIE" "0,1" bitfld.long 0x0 1. "TEIE,TEIE" "0,1" newline bitfld.long 0x0 0. "EN,EN" "0,1" line.long 0x4 "MDMA_C11TCR,This register is used to configure the concerned channel. In Linked List mode. at the end of a block (single or last block in repeated block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] +.." bitfld.long 0x4 31. "BWM,BWM" "0,1" bitfld.long 0x4 30. "SWRM,SWRM" "0,1" bitfld.long 0x4 28.--29. "TRGM,TRGM" "0,1,2,3" bitfld.long 0x4 26.--27. "PAM,PAM" "0,1,2,3" bitfld.long 0x4 25. "PKE,PKE" "0,1" hexmask.long.byte 0x4 18.--24. 1. "TLEN,TLEN" bitfld.long 0x4 15.--17. "DBURST,DBURST" "0,1,2,3,4,5,6,7" bitfld.long 0x4 12.--14. "SBURST,SBURST" "0,1,2,3,4,5,6,7" bitfld.long 0x4 10.--11. "DINCOS,DINCOS" "0,1,2,3" bitfld.long 0x4 8.--9. "SINCOS,SINCOS" "0,1,2,3" newline bitfld.long 0x4 6.--7. "DSIZE,DSIZE" "0,1,2,3" bitfld.long 0x4 4.--5. "SSIZE,SSIZE" "0,1,2,3" bitfld.long 0x4 2.--3. "DINC,DINC" "0,1,2,3" bitfld.long 0x4 0.--1. "SINC,SINC" "0,1,2,3" line.long 0x8 "MDMA_C11BNDTR,In Linked List mode. at the end of a block (single or last block in repeated block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] + 0x04)." hexmask.long.word 0x8 20.--31. 1. "BRC,BRC" bitfld.long 0x8 19. "BRDUM,BRDUM" "0,1" bitfld.long 0x8 18. "BRSUM,BRSUM" "0,1" hexmask.long.tbyte 0x8 0.--16. 1. "BNDT,BNDT" line.long 0xC "MDMA_C11SAR,In Linked List mode. at the end of a Block (single or last Block in repeated Block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] + 0x08)." hexmask.long 0xC 0.--31. 1. "SAR,SAR" line.long 0x10 "MDMA_C11DAR,In Linked List mode. at the end of a block (single or last block in repeated block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M" hexmask.long 0x10 0.--31. 1. "DAR,DAR" line.long 0x14 "MDMA_C11BRUR,In Linked List mode. at the end of a block (single or last block in repeated block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] + 0x10)." hexmask.long.word 0x14 16.--31. 1. "DUV,DUV" hexmask.long.word 0x14 0.--15. 1. "SUV,SUV" line.long 0x18 "MDMA_C11LAR,In Linked List mode. at the end of a block (single or last block in repeated block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all.." hexmask.long 0x18 0.--31. 1. "LAR,LAR" line.long 0x1C "MDMA_C11TBR,In Linked List mode. at the end of a block (single or last block in repeated block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] + 0x18)." bitfld.long 0x1C 17. "DBUS,DBUS" "0,1" bitfld.long 0x1C 16. "SBUS,SBUS" "0,1" hexmask.long.byte 0x1C 0.--5. 1. "TSEL,TSEL" group.long 0x330++0x7 line.long 0x0 "MDMA_C11MAR,In Linked List mode. at the end of a block (single or last block in repeated block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] + 0x20)." hexmask.long 0x0 0.--31. 1. "MAR,MAR" line.long 0x4 "MDMA_C11MDR,In Linked List mode. at the end of a block (single or last block in repeated block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] + 0x24)." hexmask.long 0x4 0.--31. 1. "MDR,MDR" rgroup.long 0x340++0x3 line.long 0x0 "MDMA_C12ISR,MDMA channel 12 interrupt/status register" bitfld.long 0x0 16. "CRQA,CRQA" "0,1" bitfld.long 0x0 4. "TCIF,TCIF" "0,1" bitfld.long 0x0 3. "BTIF,BTIF" "0,1" bitfld.long 0x0 2. "BRTIF,BRTIF" "0,1" bitfld.long 0x0 1. "CTCIF,CTCIF" "0,1" bitfld.long 0x0 0. "TEIF,TEIF" "0,1" wgroup.long 0x344++0x3 line.long 0x0 "MDMA_C12IFCR,MDMA channel 12 interrupt flag clear register" bitfld.long 0x0 4. "CLTCIF,CLTCIF" "0,1" bitfld.long 0x0 3. "CBTIF,CBTIF" "0,1" bitfld.long 0x0 2. "CBRTIF,CBRTIF" "0,1" bitfld.long 0x0 1. "CCTCIF,CCTCIF" "0,1" bitfld.long 0x0 0. "CTEIF,CTEIF" "0,1" rgroup.long 0x348++0x3 line.long 0x0 "MDMA_C12ESR,MDMA channel 12 error status register" bitfld.long 0x0 11. "BSE,BSE" "0,1" bitfld.long 0x0 10. "ASE,ASE" "0,1" bitfld.long 0x0 9. "TEMD,TEMD" "0,1" bitfld.long 0x0 8. "TELD,TELD" "0,1" bitfld.long 0x0 7. "TED,TED" "0,1" hexmask.long.byte 0x0 0.--6. 1. "TEA,TEA" group.long 0x34C++0x1F line.long 0x0 "MDMA_C12CR,This register is used to control the concerned channel." bitfld.long 0x0 16. "SWRQ,SWRQ" "0,1" bitfld.long 0x0 14. "WEX,WEX" "0,1" bitfld.long 0x0 13. "HEX,HEX" "0,1" bitfld.long 0x0 12. "BEX,BEX" "0,1" bitfld.long 0x0 6.--7. "PL,PL" "0,1,2,3" bitfld.long 0x0 5. "TCIE,TCIE" "0,1" bitfld.long 0x0 4. "BTIE,BTIE" "0,1" bitfld.long 0x0 3. "BRTIE,BRTIE" "0,1" bitfld.long 0x0 2. "CTCIE,CTCIE" "0,1" bitfld.long 0x0 1. "TEIE,TEIE" "0,1" newline bitfld.long 0x0 0. "EN,EN" "0,1" line.long 0x4 "MDMA_C12TCR,This register is used to configure the concerned channel. In Linked List mode. at the end of a block (single or last block in repeated block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] +.." bitfld.long 0x4 31. "BWM,BWM" "0,1" bitfld.long 0x4 30. "SWRM,SWRM" "0,1" bitfld.long 0x4 28.--29. "TRGM,TRGM" "0,1,2,3" bitfld.long 0x4 26.--27. "PAM,PAM" "0,1,2,3" bitfld.long 0x4 25. "PKE,PKE" "0,1" hexmask.long.byte 0x4 18.--24. 1. "TLEN,TLEN" bitfld.long 0x4 15.--17. "DBURST,DBURST" "0,1,2,3,4,5,6,7" bitfld.long 0x4 12.--14. "SBURST,SBURST" "0,1,2,3,4,5,6,7" bitfld.long 0x4 10.--11. "DINCOS,DINCOS" "0,1,2,3" bitfld.long 0x4 8.--9. "SINCOS,SINCOS" "0,1,2,3" newline bitfld.long 0x4 6.--7. "DSIZE,DSIZE" "0,1,2,3" bitfld.long 0x4 4.--5. "SSIZE,SSIZE" "0,1,2,3" bitfld.long 0x4 2.--3. "DINC,DINC" "0,1,2,3" bitfld.long 0x4 0.--1. "SINC,SINC" "0,1,2,3" line.long 0x8 "MDMA_C12BNDTR,In Linked List mode. at the end of a block (single or last block in repeated block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] + 0x04)." hexmask.long.word 0x8 20.--31. 1. "BRC,BRC" bitfld.long 0x8 19. "BRDUM,BRDUM" "0,1" bitfld.long 0x8 18. "BRSUM,BRSUM" "0,1" hexmask.long.tbyte 0x8 0.--16. 1. "BNDT,BNDT" line.long 0xC "MDMA_C12SAR,In Linked List mode. at the end of a Block (single or last Block in repeated Block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] + 0x08)." hexmask.long 0xC 0.--31. 1. "SAR,SAR" line.long 0x10 "MDMA_C12DAR,In Linked List mode. at the end of a block (single or last block in repeated block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M" hexmask.long 0x10 0.--31. 1. "DAR,DAR" line.long 0x14 "MDMA_C12BRUR,In Linked List mode. at the end of a block (single or last block in repeated block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] + 0x10)." hexmask.long.word 0x14 16.--31. 1. "DUV,DUV" hexmask.long.word 0x14 0.--15. 1. "SUV,SUV" line.long 0x18 "MDMA_C12LAR,In Linked List mode. at the end of a block (single or last block in repeated block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all.." hexmask.long 0x18 0.--31. 1. "LAR,LAR" line.long 0x1C "MDMA_C12TBR,In Linked List mode. at the end of a block (single or last block in repeated block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] + 0x18)." bitfld.long 0x1C 17. "DBUS,DBUS" "0,1" bitfld.long 0x1C 16. "SBUS,SBUS" "0,1" hexmask.long.byte 0x1C 0.--5. 1. "TSEL,TSEL" group.long 0x370++0x7 line.long 0x0 "MDMA_C12MAR,In Linked List mode. at the end of a block (single or last block in repeated block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] + 0x20)." hexmask.long 0x0 0.--31. 1. "MAR,MAR" line.long 0x4 "MDMA_C12MDR,In Linked List mode. at the end of a block (single or last block in repeated block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] + 0x24)." hexmask.long 0x4 0.--31. 1. "MDR,MDR" rgroup.long 0x380++0x3 line.long 0x0 "MDMA_C13ISR,MDMA channel 13 interrupt/status register" bitfld.long 0x0 16. "CRQA,CRQA" "0,1" bitfld.long 0x0 4. "TCIF,TCIF" "0,1" bitfld.long 0x0 3. "BTIF,BTIF" "0,1" bitfld.long 0x0 2. "BRTIF,BRTIF" "0,1" bitfld.long 0x0 1. "CTCIF,CTCIF" "0,1" bitfld.long 0x0 0. "TEIF,TEIF" "0,1" wgroup.long 0x384++0x3 line.long 0x0 "MDMA_C13IFCR,MDMA channel 13 interrupt flag clear register" bitfld.long 0x0 4. "CLTCIF,CLTCIF" "0,1" bitfld.long 0x0 3. "CBTIF,CBTIF" "0,1" bitfld.long 0x0 2. "CBRTIF,CBRTIF" "0,1" bitfld.long 0x0 1. "CCTCIF,CCTCIF" "0,1" bitfld.long 0x0 0. "CTEIF,CTEIF" "0,1" rgroup.long 0x388++0x3 line.long 0x0 "MDMA_C13ESR,MDMA channel 13 error status register" bitfld.long 0x0 11. "BSE,BSE" "0,1" bitfld.long 0x0 10. "ASE,ASE" "0,1" bitfld.long 0x0 9. "TEMD,TEMD" "0,1" bitfld.long 0x0 8. "TELD,TELD" "0,1" bitfld.long 0x0 7. "TED,TED" "0,1" hexmask.long.byte 0x0 0.--6. 1. "TEA,TEA" group.long 0x38C++0x1F line.long 0x0 "MDMA_C13CR,This register is used to control the concerned channel." bitfld.long 0x0 16. "SWRQ,SWRQ" "0,1" bitfld.long 0x0 14. "WEX,WEX" "0,1" bitfld.long 0x0 13. "HEX,HEX" "0,1" bitfld.long 0x0 12. "BEX,BEX" "0,1" bitfld.long 0x0 6.--7. "PL,PL" "0,1,2,3" bitfld.long 0x0 5. "TCIE,TCIE" "0,1" bitfld.long 0x0 4. "BTIE,BTIE" "0,1" bitfld.long 0x0 3. "BRTIE,BRTIE" "0,1" bitfld.long 0x0 2. "CTCIE,CTCIE" "0,1" bitfld.long 0x0 1. "TEIE,TEIE" "0,1" newline bitfld.long 0x0 0. "EN,EN" "0,1" line.long 0x4 "MDMA_C13TCR,This register is used to configure the concerned channel. In Linked List mode. at the end of a block (single or last block in repeated block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] +.." bitfld.long 0x4 31. "BWM,BWM" "0,1" bitfld.long 0x4 30. "SWRM,SWRM" "0,1" bitfld.long 0x4 28.--29. "TRGM,TRGM" "0,1,2,3" bitfld.long 0x4 26.--27. "PAM,PAM" "0,1,2,3" bitfld.long 0x4 25. "PKE,PKE" "0,1" hexmask.long.byte 0x4 18.--24. 1. "TLEN,TLEN" bitfld.long 0x4 15.--17. "DBURST,DBURST" "0,1,2,3,4,5,6,7" bitfld.long 0x4 12.--14. "SBURST,SBURST" "0,1,2,3,4,5,6,7" bitfld.long 0x4 10.--11. "DINCOS,DINCOS" "0,1,2,3" bitfld.long 0x4 8.--9. "SINCOS,SINCOS" "0,1,2,3" newline bitfld.long 0x4 6.--7. "DSIZE,DSIZE" "0,1,2,3" bitfld.long 0x4 4.--5. "SSIZE,SSIZE" "0,1,2,3" bitfld.long 0x4 2.--3. "DINC,DINC" "0,1,2,3" bitfld.long 0x4 0.--1. "SINC,SINC" "0,1,2,3" line.long 0x8 "MDMA_C13BNDTR,In Linked List mode. at the end of a block (single or last block in repeated block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] + 0x04)." hexmask.long.word 0x8 20.--31. 1. "BRC,BRC" bitfld.long 0x8 19. "BRDUM,BRDUM" "0,1" bitfld.long 0x8 18. "BRSUM,BRSUM" "0,1" hexmask.long.tbyte 0x8 0.--16. 1. "BNDT,BNDT" line.long 0xC "MDMA_C13SAR,In Linked List mode. at the end of a Block (single or last Block in repeated Block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] + 0x08)." hexmask.long 0xC 0.--31. 1. "SAR,SAR" line.long 0x10 "MDMA_C13DAR,In Linked List mode. at the end of a block (single or last block in repeated block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M" hexmask.long 0x10 0.--31. 1. "DAR,DAR" line.long 0x14 "MDMA_C13BRUR,In Linked List mode. at the end of a block (single or last block in repeated block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] + 0x10)." hexmask.long.word 0x14 16.--31. 1. "DUV,DUV" hexmask.long.word 0x14 0.--15. 1. "SUV,SUV" line.long 0x18 "MDMA_C13LAR,In Linked List mode. at the end of a block (single or last block in repeated block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all.." hexmask.long 0x18 0.--31. 1. "LAR,LAR" line.long 0x1C "MDMA_C13TBR,In Linked List mode. at the end of a block (single or last block in repeated block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] + 0x18)." bitfld.long 0x1C 17. "DBUS,DBUS" "0,1" bitfld.long 0x1C 16. "SBUS,SBUS" "0,1" hexmask.long.byte 0x1C 0.--5. 1. "TSEL,TSEL" group.long 0x3B0++0x7 line.long 0x0 "MDMA_C13MAR,In Linked List mode. at the end of a block (single or last block in repeated block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] + 0x20)." hexmask.long 0x0 0.--31. 1. "MAR,MAR" line.long 0x4 "MDMA_C13MDR,In Linked List mode. at the end of a block (single or last block in repeated block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] + 0x24)." hexmask.long 0x4 0.--31. 1. "MDR,MDR" rgroup.long 0x3C0++0x3 line.long 0x0 "MDMA_C14ISR,MDMA channel 14 interrupt/status register" bitfld.long 0x0 16. "CRQA,CRQA" "0,1" bitfld.long 0x0 4. "TCIF,TCIF" "0,1" bitfld.long 0x0 3. "BTIF,BTIF" "0,1" bitfld.long 0x0 2. "BRTIF,BRTIF" "0,1" bitfld.long 0x0 1. "CTCIF,CTCIF" "0,1" bitfld.long 0x0 0. "TEIF,TEIF" "0,1" wgroup.long 0x3C4++0x3 line.long 0x0 "MDMA_C14IFCR,MDMA channel 14 interrupt flag clear register" bitfld.long 0x0 4. "CLTCIF,CLTCIF" "0,1" bitfld.long 0x0 3. "CBTIF,CBTIF" "0,1" bitfld.long 0x0 2. "CBRTIF,CBRTIF" "0,1" bitfld.long 0x0 1. "CCTCIF,CCTCIF" "0,1" bitfld.long 0x0 0. "CTEIF,CTEIF" "0,1" rgroup.long 0x3C8++0x3 line.long 0x0 "MDMA_C14ESR,MDMA channel 14 error status register" bitfld.long 0x0 11. "BSE,BSE" "0,1" bitfld.long 0x0 10. "ASE,ASE" "0,1" bitfld.long 0x0 9. "TEMD,TEMD" "0,1" bitfld.long 0x0 8. "TELD,TELD" "0,1" bitfld.long 0x0 7. "TED,TED" "0,1" hexmask.long.byte 0x0 0.--6. 1. "TEA,TEA" group.long 0x3CC++0x1F line.long 0x0 "MDMA_C14CR,This register is used to control the concerned channel." bitfld.long 0x0 16. "SWRQ,SWRQ" "0,1" bitfld.long 0x0 14. "WEX,WEX" "0,1" bitfld.long 0x0 13. "HEX,HEX" "0,1" bitfld.long 0x0 12. "BEX,BEX" "0,1" bitfld.long 0x0 6.--7. "PL,PL" "0,1,2,3" bitfld.long 0x0 5. "TCIE,TCIE" "0,1" bitfld.long 0x0 4. "BTIE,BTIE" "0,1" bitfld.long 0x0 3. "BRTIE,BRTIE" "0,1" bitfld.long 0x0 2. "CTCIE,CTCIE" "0,1" bitfld.long 0x0 1. "TEIE,TEIE" "0,1" newline bitfld.long 0x0 0. "EN,EN" "0,1" line.long 0x4 "MDMA_C14TCR,This register is used to configure the concerned channel. In Linked List mode. at the end of a block (single or last block in repeated block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] +.." bitfld.long 0x4 31. "BWM,BWM" "0,1" bitfld.long 0x4 30. "SWRM,SWRM" "0,1" bitfld.long 0x4 28.--29. "TRGM,TRGM" "0,1,2,3" bitfld.long 0x4 26.--27. "PAM,PAM" "0,1,2,3" bitfld.long 0x4 25. "PKE,PKE" "0,1" hexmask.long.byte 0x4 18.--24. 1. "TLEN,TLEN" bitfld.long 0x4 15.--17. "DBURST,DBURST" "0,1,2,3,4,5,6,7" bitfld.long 0x4 12.--14. "SBURST,SBURST" "0,1,2,3,4,5,6,7" bitfld.long 0x4 10.--11. "DINCOS,DINCOS" "0,1,2,3" bitfld.long 0x4 8.--9. "SINCOS,SINCOS" "0,1,2,3" newline bitfld.long 0x4 6.--7. "DSIZE,DSIZE" "0,1,2,3" bitfld.long 0x4 4.--5. "SSIZE,SSIZE" "0,1,2,3" bitfld.long 0x4 2.--3. "DINC,DINC" "0,1,2,3" bitfld.long 0x4 0.--1. "SINC,SINC" "0,1,2,3" line.long 0x8 "MDMA_C14BNDTR,In Linked List mode. at the end of a block (single or last block in repeated block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] + 0x04)." hexmask.long.word 0x8 20.--31. 1. "BRC,BRC" bitfld.long 0x8 19. "BRDUM,BRDUM" "0,1" bitfld.long 0x8 18. "BRSUM,BRSUM" "0,1" hexmask.long.tbyte 0x8 0.--16. 1. "BNDT,BNDT" line.long 0xC "MDMA_C14SAR,In Linked List mode. at the end of a Block (single or last Block in repeated Block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] + 0x08)." hexmask.long 0xC 0.--31. 1. "SAR,SAR" line.long 0x10 "MDMA_C14DAR,In Linked List mode. at the end of a block (single or last block in repeated block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M" hexmask.long 0x10 0.--31. 1. "DAR,DAR" line.long 0x14 "MDMA_C14BRUR,In Linked List mode. at the end of a block (single or last block in repeated block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] + 0x10)." hexmask.long.word 0x14 16.--31. 1. "DUV,DUV" hexmask.long.word 0x14 0.--15. 1. "SUV,SUV" line.long 0x18 "MDMA_C14LAR,In Linked List mode. at the end of a block (single or last block in repeated block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all.." hexmask.long 0x18 0.--31. 1. "LAR,LAR" line.long 0x1C "MDMA_C14TBR,In Linked List mode. at the end of a block (single or last block in repeated block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] + 0x18)." bitfld.long 0x1C 17. "DBUS,DBUS" "0,1" bitfld.long 0x1C 16. "SBUS,SBUS" "0,1" hexmask.long.byte 0x1C 0.--5. 1. "TSEL,TSEL" group.long 0x3F0++0x7 line.long 0x0 "MDMA_C14MAR,In Linked List mode. at the end of a block (single or last block in repeated block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] + 0x20)." hexmask.long 0x0 0.--31. 1. "MAR,MAR" line.long 0x4 "MDMA_C14MDR,In Linked List mode. at the end of a block (single or last block in repeated block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] + 0x24)." hexmask.long 0x4 0.--31. 1. "MDR,MDR" rgroup.long 0x400++0x3 line.long 0x0 "MDMA_C15ISR,MDMA channel 15 interrupt/status register" bitfld.long 0x0 16. "CRQA,CRQA" "0,1" bitfld.long 0x0 4. "TCIF,TCIF" "0,1" bitfld.long 0x0 3. "BTIF,BTIF" "0,1" bitfld.long 0x0 2. "BRTIF,BRTIF" "0,1" bitfld.long 0x0 1. "CTCIF,CTCIF" "0,1" bitfld.long 0x0 0. "TEIF,TEIF" "0,1" wgroup.long 0x404++0x3 line.long 0x0 "MDMA_C15IFCR,MDMA channel 15 interrupt flag clear register" bitfld.long 0x0 4. "CLTCIF,CLTCIF" "0,1" bitfld.long 0x0 3. "CBTIF,CBTIF" "0,1" bitfld.long 0x0 2. "CBRTIF,CBRTIF" "0,1" bitfld.long 0x0 1. "CCTCIF,CCTCIF" "0,1" bitfld.long 0x0 0. "CTEIF,CTEIF" "0,1" rgroup.long 0x408++0x3 line.long 0x0 "MDMA_C15ESR,MDMA channel 15 error status register" bitfld.long 0x0 11. "BSE,BSE" "0,1" bitfld.long 0x0 10. "ASE,ASE" "0,1" bitfld.long 0x0 9. "TEMD,TEMD" "0,1" bitfld.long 0x0 8. "TELD,TELD" "0,1" bitfld.long 0x0 7. "TED,TED" "0,1" hexmask.long.byte 0x0 0.--6. 1. "TEA,TEA" group.long 0x40C++0x1F line.long 0x0 "MDMA_C15CR,This register is used to control the concerned channel." bitfld.long 0x0 16. "SWRQ,SWRQ" "0,1" bitfld.long 0x0 14. "WEX,WEX" "0,1" bitfld.long 0x0 13. "HEX,HEX" "0,1" bitfld.long 0x0 12. "BEX,BEX" "0,1" bitfld.long 0x0 6.--7. "PL,PL" "0,1,2,3" bitfld.long 0x0 5. "TCIE,TCIE" "0,1" bitfld.long 0x0 4. "BTIE,BTIE" "0,1" bitfld.long 0x0 3. "BRTIE,BRTIE" "0,1" bitfld.long 0x0 2. "CTCIE,CTCIE" "0,1" bitfld.long 0x0 1. "TEIE,TEIE" "0,1" newline bitfld.long 0x0 0. "EN,EN" "0,1" line.long 0x4 "MDMA_C15TCR,This register is used to configure the concerned channel. In Linked List mode. at the end of a block (single or last block in repeated block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] +.." bitfld.long 0x4 31. "BWM,BWM" "0,1" bitfld.long 0x4 30. "SWRM,SWRM" "0,1" bitfld.long 0x4 28.--29. "TRGM,TRGM" "0,1,2,3" bitfld.long 0x4 26.--27. "PAM,PAM" "0,1,2,3" bitfld.long 0x4 25. "PKE,PKE" "0,1" hexmask.long.byte 0x4 18.--24. 1. "TLEN,TLEN" bitfld.long 0x4 15.--17. "DBURST,DBURST" "0,1,2,3,4,5,6,7" bitfld.long 0x4 12.--14. "SBURST,SBURST" "0,1,2,3,4,5,6,7" bitfld.long 0x4 10.--11. "DINCOS,DINCOS" "0,1,2,3" bitfld.long 0x4 8.--9. "SINCOS,SINCOS" "0,1,2,3" newline bitfld.long 0x4 6.--7. "DSIZE,DSIZE" "0,1,2,3" bitfld.long 0x4 4.--5. "SSIZE,SSIZE" "0,1,2,3" bitfld.long 0x4 2.--3. "DINC,DINC" "0,1,2,3" bitfld.long 0x4 0.--1. "SINC,SINC" "0,1,2,3" line.long 0x8 "MDMA_C15BNDTR,In Linked List mode. at the end of a block (single or last block in repeated block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] + 0x04)." hexmask.long.word 0x8 20.--31. 1. "BRC,BRC" bitfld.long 0x8 19. "BRDUM,BRDUM" "0,1" bitfld.long 0x8 18. "BRSUM,BRSUM" "0,1" hexmask.long.tbyte 0x8 0.--16. 1. "BNDT,BNDT" line.long 0xC "MDMA_C15SAR,In Linked List mode. at the end of a Block (single or last Block in repeated Block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] + 0x08)." hexmask.long 0xC 0.--31. 1. "SAR,SAR" line.long 0x10 "MDMA_C15DAR,In Linked List mode. at the end of a block (single or last block in repeated block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M" hexmask.long 0x10 0.--31. 1. "DAR,DAR" line.long 0x14 "MDMA_C15BRUR,In Linked List mode. at the end of a block (single or last block in repeated block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] + 0x10)." hexmask.long.word 0x14 16.--31. 1. "DUV,DUV" hexmask.long.word 0x14 0.--15. 1. "SUV,SUV" line.long 0x18 "MDMA_C15LAR,In Linked List mode. at the end of a block (single or last block in repeated block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all.." hexmask.long 0x18 0.--31. 1. "LAR,LAR" line.long 0x1C "MDMA_C15TBR,In Linked List mode. at the end of a block (single or last block in repeated block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] + 0x18)." bitfld.long 0x1C 17. "DBUS,DBUS" "0,1" bitfld.long 0x1C 16. "SBUS,SBUS" "0,1" hexmask.long.byte 0x1C 0.--5. 1. "TSEL,TSEL" group.long 0x430++0x7 line.long 0x0 "MDMA_C15MAR,In Linked List mode. at the end of a block (single or last block in repeated block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] + 0x20)." hexmask.long 0x0 0.--31. 1. "MAR,MAR" line.long 0x4 "MDMA_C15MDR,In Linked List mode. at the end of a block (single or last block in repeated block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] + 0x24)." hexmask.long 0x4 0.--31. 1. "MDR,MDR" rgroup.long 0x440++0x3 line.long 0x0 "MDMA_C16ISR,MDMA channel 16 interrupt/status register" bitfld.long 0x0 16. "CRQA,CRQA" "0,1" bitfld.long 0x0 4. "TCIF,TCIF" "0,1" bitfld.long 0x0 3. "BTIF,BTIF" "0,1" bitfld.long 0x0 2. "BRTIF,BRTIF" "0,1" bitfld.long 0x0 1. "CTCIF,CTCIF" "0,1" bitfld.long 0x0 0. "TEIF,TEIF" "0,1" wgroup.long 0x444++0x3 line.long 0x0 "MDMA_C16IFCR,MDMA channel 16 interrupt flag clear register" bitfld.long 0x0 4. "CLTCIF,CLTCIF" "0,1" bitfld.long 0x0 3. "CBTIF,CBTIF" "0,1" bitfld.long 0x0 2. "CBRTIF,CBRTIF" "0,1" bitfld.long 0x0 1. "CCTCIF,CCTCIF" "0,1" bitfld.long 0x0 0. "CTEIF,CTEIF" "0,1" rgroup.long 0x448++0x3 line.long 0x0 "MDMA_C16ESR,MDMA channel 16 error status register" bitfld.long 0x0 11. "BSE,BSE" "0,1" bitfld.long 0x0 10. "ASE,ASE" "0,1" bitfld.long 0x0 9. "TEMD,TEMD" "0,1" bitfld.long 0x0 8. "TELD,TELD" "0,1" bitfld.long 0x0 7. "TED,TED" "0,1" hexmask.long.byte 0x0 0.--6. 1. "TEA,TEA" group.long 0x44C++0x1F line.long 0x0 "MDMA_C16CR,This register is used to control the concerned channel." bitfld.long 0x0 16. "SWRQ,SWRQ" "0,1" bitfld.long 0x0 14. "WEX,WEX" "0,1" bitfld.long 0x0 13. "HEX,HEX" "0,1" bitfld.long 0x0 12. "BEX,BEX" "0,1" bitfld.long 0x0 6.--7. "PL,PL" "0,1,2,3" bitfld.long 0x0 5. "TCIE,TCIE" "0,1" bitfld.long 0x0 4. "BTIE,BTIE" "0,1" bitfld.long 0x0 3. "BRTIE,BRTIE" "0,1" bitfld.long 0x0 2. "CTCIE,CTCIE" "0,1" bitfld.long 0x0 1. "TEIE,TEIE" "0,1" newline bitfld.long 0x0 0. "EN,EN" "0,1" line.long 0x4 "MDMA_C16TCR,This register is used to configure the concerned channel. In Linked List mode. at the end of a block (single or last block in repeated block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] +.." bitfld.long 0x4 31. "BWM,BWM" "0,1" bitfld.long 0x4 30. "SWRM,SWRM" "0,1" bitfld.long 0x4 28.--29. "TRGM,TRGM" "0,1,2,3" bitfld.long 0x4 26.--27. "PAM,PAM" "0,1,2,3" bitfld.long 0x4 25. "PKE,PKE" "0,1" hexmask.long.byte 0x4 18.--24. 1. "TLEN,TLEN" bitfld.long 0x4 15.--17. "DBURST,DBURST" "0,1,2,3,4,5,6,7" bitfld.long 0x4 12.--14. "SBURST,SBURST" "0,1,2,3,4,5,6,7" bitfld.long 0x4 10.--11. "DINCOS,DINCOS" "0,1,2,3" bitfld.long 0x4 8.--9. "SINCOS,SINCOS" "0,1,2,3" newline bitfld.long 0x4 6.--7. "DSIZE,DSIZE" "0,1,2,3" bitfld.long 0x4 4.--5. "SSIZE,SSIZE" "0,1,2,3" bitfld.long 0x4 2.--3. "DINC,DINC" "0,1,2,3" bitfld.long 0x4 0.--1. "SINC,SINC" "0,1,2,3" line.long 0x8 "MDMA_C16BNDTR,In Linked List mode. at the end of a block (single or last block in repeated block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] + 0x04)." hexmask.long.word 0x8 20.--31. 1. "BRC,BRC" bitfld.long 0x8 19. "BRDUM,BRDUM" "0,1" bitfld.long 0x8 18. "BRSUM,BRSUM" "0,1" hexmask.long.tbyte 0x8 0.--16. 1. "BNDT,BNDT" line.long 0xC "MDMA_C16SAR,In Linked List mode. at the end of a Block (single or last Block in repeated Block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] + 0x08)." hexmask.long 0xC 0.--31. 1. "SAR,SAR" line.long 0x10 "MDMA_C16DAR,In Linked List mode. at the end of a block (single or last block in repeated block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M" hexmask.long 0x10 0.--31. 1. "DAR,DAR" line.long 0x14 "MDMA_C16BRUR,In Linked List mode. at the end of a block (single or last block in repeated block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] + 0x10)." hexmask.long.word 0x14 16.--31. 1. "DUV,DUV" hexmask.long.word 0x14 0.--15. 1. "SUV,SUV" line.long 0x18 "MDMA_C16LAR,In Linked List mode. at the end of a block (single or last block in repeated block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all.." hexmask.long 0x18 0.--31. 1. "LAR,LAR" line.long 0x1C "MDMA_C16TBR,In Linked List mode. at the end of a block (single or last block in repeated block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] + 0x18)." bitfld.long 0x1C 17. "DBUS,DBUS" "0,1" bitfld.long 0x1C 16. "SBUS,SBUS" "0,1" hexmask.long.byte 0x1C 0.--5. 1. "TSEL,TSEL" group.long 0x470++0x7 line.long 0x0 "MDMA_C16MAR,In Linked List mode. at the end of a block (single or last block in repeated block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] + 0x20)." hexmask.long 0x0 0.--31. 1. "MAR,MAR" line.long 0x4 "MDMA_C16MDR,In Linked List mode. at the end of a block (single or last block in repeated block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] + 0x24)." hexmask.long 0x4 0.--31. 1. "MDR,MDR" rgroup.long 0x480++0x3 line.long 0x0 "MDMA_C17ISR,MDMA channel 17 interrupt/status register" bitfld.long 0x0 16. "CRQA,CRQA" "0,1" bitfld.long 0x0 4. "TCIF,TCIF" "0,1" bitfld.long 0x0 3. "BTIF,BTIF" "0,1" bitfld.long 0x0 2. "BRTIF,BRTIF" "0,1" bitfld.long 0x0 1. "CTCIF,CTCIF" "0,1" bitfld.long 0x0 0. "TEIF,TEIF" "0,1" wgroup.long 0x484++0x3 line.long 0x0 "MDMA_C17IFCR,MDMA channel 17 interrupt flag clear register" bitfld.long 0x0 4. "CLTCIF,CLTCIF" "0,1" bitfld.long 0x0 3. "CBTIF,CBTIF" "0,1" bitfld.long 0x0 2. "CBRTIF,CBRTIF" "0,1" bitfld.long 0x0 1. "CCTCIF,CCTCIF" "0,1" bitfld.long 0x0 0. "CTEIF,CTEIF" "0,1" rgroup.long 0x488++0x3 line.long 0x0 "MDMA_C17ESR,MDMA channel 17 error status register" bitfld.long 0x0 11. "BSE,BSE" "0,1" bitfld.long 0x0 10. "ASE,ASE" "0,1" bitfld.long 0x0 9. "TEMD,TEMD" "0,1" bitfld.long 0x0 8. "TELD,TELD" "0,1" bitfld.long 0x0 7. "TED,TED" "0,1" hexmask.long.byte 0x0 0.--6. 1. "TEA,TEA" group.long 0x48C++0x1F line.long 0x0 "MDMA_C17CR,This register is used to control the concerned channel." bitfld.long 0x0 16. "SWRQ,SWRQ" "0,1" bitfld.long 0x0 14. "WEX,WEX" "0,1" bitfld.long 0x0 13. "HEX,HEX" "0,1" bitfld.long 0x0 12. "BEX,BEX" "0,1" bitfld.long 0x0 6.--7. "PL,PL" "0,1,2,3" bitfld.long 0x0 5. "TCIE,TCIE" "0,1" bitfld.long 0x0 4. "BTIE,BTIE" "0,1" bitfld.long 0x0 3. "BRTIE,BRTIE" "0,1" bitfld.long 0x0 2. "CTCIE,CTCIE" "0,1" bitfld.long 0x0 1. "TEIE,TEIE" "0,1" newline bitfld.long 0x0 0. "EN,EN" "0,1" line.long 0x4 "MDMA_C17TCR,This register is used to configure the concerned channel. In Linked List mode. at the end of a block (single or last block in repeated block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] +.." bitfld.long 0x4 31. "BWM,BWM" "0,1" bitfld.long 0x4 30. "SWRM,SWRM" "0,1" bitfld.long 0x4 28.--29. "TRGM,TRGM" "0,1,2,3" bitfld.long 0x4 26.--27. "PAM,PAM" "0,1,2,3" bitfld.long 0x4 25. "PKE,PKE" "0,1" hexmask.long.byte 0x4 18.--24. 1. "TLEN,TLEN" bitfld.long 0x4 15.--17. "DBURST,DBURST" "0,1,2,3,4,5,6,7" bitfld.long 0x4 12.--14. "SBURST,SBURST" "0,1,2,3,4,5,6,7" bitfld.long 0x4 10.--11. "DINCOS,DINCOS" "0,1,2,3" bitfld.long 0x4 8.--9. "SINCOS,SINCOS" "0,1,2,3" newline bitfld.long 0x4 6.--7. "DSIZE,DSIZE" "0,1,2,3" bitfld.long 0x4 4.--5. "SSIZE,SSIZE" "0,1,2,3" bitfld.long 0x4 2.--3. "DINC,DINC" "0,1,2,3" bitfld.long 0x4 0.--1. "SINC,SINC" "0,1,2,3" line.long 0x8 "MDMA_C17BNDTR,In Linked List mode. at the end of a block (single or last block in repeated block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] + 0x04)." hexmask.long.word 0x8 20.--31. 1. "BRC,BRC" bitfld.long 0x8 19. "BRDUM,BRDUM" "0,1" bitfld.long 0x8 18. "BRSUM,BRSUM" "0,1" hexmask.long.tbyte 0x8 0.--16. 1. "BNDT,BNDT" line.long 0xC "MDMA_C17SAR,In Linked List mode. at the end of a Block (single or last Block in repeated Block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] + 0x08)." hexmask.long 0xC 0.--31. 1. "SAR,SAR" line.long 0x10 "MDMA_C17DAR,In Linked List mode. at the end of a block (single or last block in repeated block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M" hexmask.long 0x10 0.--31. 1. "DAR,DAR" line.long 0x14 "MDMA_C17BRUR,In Linked List mode. at the end of a block (single or last block in repeated block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] + 0x10)." hexmask.long.word 0x14 16.--31. 1. "DUV,DUV" hexmask.long.word 0x14 0.--15. 1. "SUV,SUV" line.long 0x18 "MDMA_C17LAR,In Linked List mode. at the end of a block (single or last block in repeated block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all.." hexmask.long 0x18 0.--31. 1. "LAR,LAR" line.long 0x1C "MDMA_C17TBR,In Linked List mode. at the end of a block (single or last block in repeated block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] + 0x18)." bitfld.long 0x1C 17. "DBUS,DBUS" "0,1" bitfld.long 0x1C 16. "SBUS,SBUS" "0,1" hexmask.long.byte 0x1C 0.--5. 1. "TSEL,TSEL" group.long 0x4B0++0x7 line.long 0x0 "MDMA_C17MAR,In Linked List mode. at the end of a block (single or last block in repeated block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] + 0x20)." hexmask.long 0x0 0.--31. 1. "MAR,MAR" line.long 0x4 "MDMA_C17MDR,In Linked List mode. at the end of a block (single or last block in repeated block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] + 0x24)." hexmask.long 0x4 0.--31. 1. "MDR,MDR" rgroup.long 0x4C0++0x3 line.long 0x0 "MDMA_C18ISR,MDMA channel 18 interrupt/status register" bitfld.long 0x0 16. "CRQA,CRQA" "0,1" bitfld.long 0x0 4. "TCIF,TCIF" "0,1" bitfld.long 0x0 3. "BTIF,BTIF" "0,1" bitfld.long 0x0 2. "BRTIF,BRTIF" "0,1" bitfld.long 0x0 1. "CTCIF,CTCIF" "0,1" bitfld.long 0x0 0. "TEIF,TEIF" "0,1" wgroup.long 0x4C4++0x3 line.long 0x0 "MDMA_C18IFCR,MDMA channel 18 interrupt flag clear register" bitfld.long 0x0 4. "CLTCIF,CLTCIF" "0,1" bitfld.long 0x0 3. "CBTIF,CBTIF" "0,1" bitfld.long 0x0 2. "CBRTIF,CBRTIF" "0,1" bitfld.long 0x0 1. "CCTCIF,CCTCIF" "0,1" bitfld.long 0x0 0. "CTEIF,CTEIF" "0,1" rgroup.long 0x4C8++0x3 line.long 0x0 "MDMA_C18ESR,MDMA channel 18 error status register" bitfld.long 0x0 11. "BSE,BSE" "0,1" bitfld.long 0x0 10. "ASE,ASE" "0,1" bitfld.long 0x0 9. "TEMD,TEMD" "0,1" bitfld.long 0x0 8. "TELD,TELD" "0,1" bitfld.long 0x0 7. "TED,TED" "0,1" hexmask.long.byte 0x0 0.--6. 1. "TEA,TEA" group.long 0x4CC++0x1F line.long 0x0 "MDMA_C18CR,This register is used to control the concerned channel." bitfld.long 0x0 16. "SWRQ,SWRQ" "0,1" bitfld.long 0x0 14. "WEX,WEX" "0,1" bitfld.long 0x0 13. "HEX,HEX" "0,1" bitfld.long 0x0 12. "BEX,BEX" "0,1" bitfld.long 0x0 6.--7. "PL,PL" "0,1,2,3" bitfld.long 0x0 5. "TCIE,TCIE" "0,1" bitfld.long 0x0 4. "BTIE,BTIE" "0,1" bitfld.long 0x0 3. "BRTIE,BRTIE" "0,1" bitfld.long 0x0 2. "CTCIE,CTCIE" "0,1" bitfld.long 0x0 1. "TEIE,TEIE" "0,1" newline bitfld.long 0x0 0. "EN,EN" "0,1" line.long 0x4 "MDMA_C18TCR,This register is used to configure the concerned channel. In Linked List mode. at the end of a block (single or last block in repeated block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] +.." bitfld.long 0x4 31. "BWM,BWM" "0,1" bitfld.long 0x4 30. "SWRM,SWRM" "0,1" bitfld.long 0x4 28.--29. "TRGM,TRGM" "0,1,2,3" bitfld.long 0x4 26.--27. "PAM,PAM" "0,1,2,3" bitfld.long 0x4 25. "PKE,PKE" "0,1" hexmask.long.byte 0x4 18.--24. 1. "TLEN,TLEN" bitfld.long 0x4 15.--17. "DBURST,DBURST" "0,1,2,3,4,5,6,7" bitfld.long 0x4 12.--14. "SBURST,SBURST" "0,1,2,3,4,5,6,7" bitfld.long 0x4 10.--11. "DINCOS,DINCOS" "0,1,2,3" bitfld.long 0x4 8.--9. "SINCOS,SINCOS" "0,1,2,3" newline bitfld.long 0x4 6.--7. "DSIZE,DSIZE" "0,1,2,3" bitfld.long 0x4 4.--5. "SSIZE,SSIZE" "0,1,2,3" bitfld.long 0x4 2.--3. "DINC,DINC" "0,1,2,3" bitfld.long 0x4 0.--1. "SINC,SINC" "0,1,2,3" line.long 0x8 "MDMA_C18BNDTR,In Linked List mode. at the end of a block (single or last block in repeated block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] + 0x04)." hexmask.long.word 0x8 20.--31. 1. "BRC,BRC" bitfld.long 0x8 19. "BRDUM,BRDUM" "0,1" bitfld.long 0x8 18. "BRSUM,BRSUM" "0,1" hexmask.long.tbyte 0x8 0.--16. 1. "BNDT,BNDT" line.long 0xC "MDMA_C18SAR,In Linked List mode. at the end of a Block (single or last Block in repeated Block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] + 0x08)." hexmask.long 0xC 0.--31. 1. "SAR,SAR" line.long 0x10 "MDMA_C18DAR,In Linked List mode. at the end of a block (single or last block in repeated block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M" hexmask.long 0x10 0.--31. 1. "DAR,DAR" line.long 0x14 "MDMA_C18BRUR,In Linked List mode. at the end of a block (single or last block in repeated block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] + 0x10)." hexmask.long.word 0x14 16.--31. 1. "DUV,DUV" hexmask.long.word 0x14 0.--15. 1. "SUV,SUV" line.long 0x18 "MDMA_C18LAR,In Linked List mode. at the end of a block (single or last block in repeated block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all.." hexmask.long 0x18 0.--31. 1. "LAR,LAR" line.long 0x1C "MDMA_C18TBR,In Linked List mode. at the end of a block (single or last block in repeated block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] + 0x18)." bitfld.long 0x1C 17. "DBUS,DBUS" "0,1" bitfld.long 0x1C 16. "SBUS,SBUS" "0,1" hexmask.long.byte 0x1C 0.--5. 1. "TSEL,TSEL" group.long 0x4F0++0x7 line.long 0x0 "MDMA_C18MAR,In Linked List mode. at the end of a block (single or last block in repeated block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] + 0x20)." hexmask.long 0x0 0.--31. 1. "MAR,MAR" line.long 0x4 "MDMA_C18MDR,In Linked List mode. at the end of a block (single or last block in repeated block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] + 0x24)." hexmask.long 0x4 0.--31. 1. "MDR,MDR" rgroup.long 0x500++0x3 line.long 0x0 "MDMA_C19ISR,MDMA channel 19 interrupt/status register" bitfld.long 0x0 16. "CRQA,CRQA" "0,1" bitfld.long 0x0 4. "TCIF,TCIF" "0,1" bitfld.long 0x0 3. "BTIF,BTIF" "0,1" bitfld.long 0x0 2. "BRTIF,BRTIF" "0,1" bitfld.long 0x0 1. "CTCIF,CTCIF" "0,1" bitfld.long 0x0 0. "TEIF,TEIF" "0,1" wgroup.long 0x504++0x3 line.long 0x0 "MDMA_C19IFCR,MDMA channel 19 interrupt flag clear register" bitfld.long 0x0 4. "CLTCIF,CLTCIF" "0,1" bitfld.long 0x0 3. "CBTIF,CBTIF" "0,1" bitfld.long 0x0 2. "CBRTIF,CBRTIF" "0,1" bitfld.long 0x0 1. "CCTCIF,CCTCIF" "0,1" bitfld.long 0x0 0. "CTEIF,CTEIF" "0,1" rgroup.long 0x508++0x3 line.long 0x0 "MDMA_C19ESR,MDMA channel 19 error status register" bitfld.long 0x0 11. "BSE,BSE" "0,1" bitfld.long 0x0 10. "ASE,ASE" "0,1" bitfld.long 0x0 9. "TEMD,TEMD" "0,1" bitfld.long 0x0 8. "TELD,TELD" "0,1" bitfld.long 0x0 7. "TED,TED" "0,1" hexmask.long.byte 0x0 0.--6. 1. "TEA,TEA" group.long 0x50C++0x1F line.long 0x0 "MDMA_C19CR,This register is used to control the concerned channel." bitfld.long 0x0 16. "SWRQ,SWRQ" "0,1" bitfld.long 0x0 14. "WEX,WEX" "0,1" bitfld.long 0x0 13. "HEX,HEX" "0,1" bitfld.long 0x0 12. "BEX,BEX" "0,1" bitfld.long 0x0 6.--7. "PL,PL" "0,1,2,3" bitfld.long 0x0 5. "TCIE,TCIE" "0,1" bitfld.long 0x0 4. "BTIE,BTIE" "0,1" bitfld.long 0x0 3. "BRTIE,BRTIE" "0,1" bitfld.long 0x0 2. "CTCIE,CTCIE" "0,1" bitfld.long 0x0 1. "TEIE,TEIE" "0,1" newline bitfld.long 0x0 0. "EN,EN" "0,1" line.long 0x4 "MDMA_C19TCR,This register is used to configure the concerned channel. In Linked List mode. at the end of a block (single or last block in repeated block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] +.." bitfld.long 0x4 31. "BWM,BWM" "0,1" bitfld.long 0x4 30. "SWRM,SWRM" "0,1" bitfld.long 0x4 28.--29. "TRGM,TRGM" "0,1,2,3" bitfld.long 0x4 26.--27. "PAM,PAM" "0,1,2,3" bitfld.long 0x4 25. "PKE,PKE" "0,1" hexmask.long.byte 0x4 18.--24. 1. "TLEN,TLEN" bitfld.long 0x4 15.--17. "DBURST,DBURST" "0,1,2,3,4,5,6,7" bitfld.long 0x4 12.--14. "SBURST,SBURST" "0,1,2,3,4,5,6,7" bitfld.long 0x4 10.--11. "DINCOS,DINCOS" "0,1,2,3" bitfld.long 0x4 8.--9. "SINCOS,SINCOS" "0,1,2,3" newline bitfld.long 0x4 6.--7. "DSIZE,DSIZE" "0,1,2,3" bitfld.long 0x4 4.--5. "SSIZE,SSIZE" "0,1,2,3" bitfld.long 0x4 2.--3. "DINC,DINC" "0,1,2,3" bitfld.long 0x4 0.--1. "SINC,SINC" "0,1,2,3" line.long 0x8 "MDMA_C19BNDTR,In Linked List mode. at the end of a block (single or last block in repeated block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] + 0x04)." hexmask.long.word 0x8 20.--31. 1. "BRC,BRC" bitfld.long 0x8 19. "BRDUM,BRDUM" "0,1" bitfld.long 0x8 18. "BRSUM,BRSUM" "0,1" hexmask.long.tbyte 0x8 0.--16. 1. "BNDT,BNDT" line.long 0xC "MDMA_C19SAR,In Linked List mode. at the end of a Block (single or last Block in repeated Block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] + 0x08)." hexmask.long 0xC 0.--31. 1. "SAR,SAR" line.long 0x10 "MDMA_C19DAR,In Linked List mode. at the end of a block (single or last block in repeated block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M" hexmask.long 0x10 0.--31. 1. "DAR,DAR" line.long 0x14 "MDMA_C19BRUR,In Linked List mode. at the end of a block (single or last block in repeated block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] + 0x10)." hexmask.long.word 0x14 16.--31. 1. "DUV,DUV" hexmask.long.word 0x14 0.--15. 1. "SUV,SUV" line.long 0x18 "MDMA_C19LAR,In Linked List mode. at the end of a block (single or last block in repeated block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all.." hexmask.long 0x18 0.--31. 1. "LAR,LAR" line.long 0x1C "MDMA_C19TBR,In Linked List mode. at the end of a block (single or last block in repeated block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] + 0x18)." bitfld.long 0x1C 17. "DBUS,DBUS" "0,1" bitfld.long 0x1C 16. "SBUS,SBUS" "0,1" hexmask.long.byte 0x1C 0.--5. 1. "TSEL,TSEL" group.long 0x530++0x7 line.long 0x0 "MDMA_C19MAR,In Linked List mode. at the end of a block (single or last block in repeated block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] + 0x20)." hexmask.long 0x0 0.--31. 1. "MAR,MAR" line.long 0x4 "MDMA_C19MDR,In Linked List mode. at the end of a block (single or last block in repeated block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] + 0x24)." hexmask.long 0x4 0.--31. 1. "MDR,MDR" rgroup.long 0x540++0x3 line.long 0x0 "MDMA_C20ISR,MDMA channel 20 interrupt/status register" bitfld.long 0x0 16. "CRQA,CRQA" "0,1" bitfld.long 0x0 4. "TCIF,TCIF" "0,1" bitfld.long 0x0 3. "BTIF,BTIF" "0,1" bitfld.long 0x0 2. "BRTIF,BRTIF" "0,1" bitfld.long 0x0 1. "CTCIF,CTCIF" "0,1" bitfld.long 0x0 0. "TEIF,TEIF" "0,1" wgroup.long 0x544++0x3 line.long 0x0 "MDMA_C20IFCR,MDMA channel 20 interrupt flag clear register" bitfld.long 0x0 4. "CLTCIF,CLTCIF" "0,1" bitfld.long 0x0 3. "CBTIF,CBTIF" "0,1" bitfld.long 0x0 2. "CBRTIF,CBRTIF" "0,1" bitfld.long 0x0 1. "CCTCIF,CCTCIF" "0,1" bitfld.long 0x0 0. "CTEIF,CTEIF" "0,1" rgroup.long 0x548++0x3 line.long 0x0 "MDMA_C20ESR,MDMA channel 20 error status register" bitfld.long 0x0 11. "BSE,BSE" "0,1" bitfld.long 0x0 10. "ASE,ASE" "0,1" bitfld.long 0x0 9. "TEMD,TEMD" "0,1" bitfld.long 0x0 8. "TELD,TELD" "0,1" bitfld.long 0x0 7. "TED,TED" "0,1" hexmask.long.byte 0x0 0.--6. 1. "TEA,TEA" group.long 0x54C++0x1F line.long 0x0 "MDMA_C20CR,This register is used to control the concerned channel." bitfld.long 0x0 16. "SWRQ,SWRQ" "0,1" bitfld.long 0x0 14. "WEX,WEX" "0,1" bitfld.long 0x0 13. "HEX,HEX" "0,1" bitfld.long 0x0 12. "BEX,BEX" "0,1" bitfld.long 0x0 6.--7. "PL,PL" "0,1,2,3" bitfld.long 0x0 5. "TCIE,TCIE" "0,1" bitfld.long 0x0 4. "BTIE,BTIE" "0,1" bitfld.long 0x0 3. "BRTIE,BRTIE" "0,1" bitfld.long 0x0 2. "CTCIE,CTCIE" "0,1" bitfld.long 0x0 1. "TEIE,TEIE" "0,1" newline bitfld.long 0x0 0. "EN,EN" "0,1" line.long 0x4 "MDMA_C20TCR,This register is used to configure the concerned channel. In Linked List mode. at the end of a block (single or last block in repeated block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] +.." bitfld.long 0x4 31. "BWM,BWM" "0,1" bitfld.long 0x4 30. "SWRM,SWRM" "0,1" bitfld.long 0x4 28.--29. "TRGM,TRGM" "0,1,2,3" bitfld.long 0x4 26.--27. "PAM,PAM" "0,1,2,3" bitfld.long 0x4 25. "PKE,PKE" "0,1" hexmask.long.byte 0x4 18.--24. 1. "TLEN,TLEN" bitfld.long 0x4 15.--17. "DBURST,DBURST" "0,1,2,3,4,5,6,7" bitfld.long 0x4 12.--14. "SBURST,SBURST" "0,1,2,3,4,5,6,7" bitfld.long 0x4 10.--11. "DINCOS,DINCOS" "0,1,2,3" bitfld.long 0x4 8.--9. "SINCOS,SINCOS" "0,1,2,3" newline bitfld.long 0x4 6.--7. "DSIZE,DSIZE" "0,1,2,3" bitfld.long 0x4 4.--5. "SSIZE,SSIZE" "0,1,2,3" bitfld.long 0x4 2.--3. "DINC,DINC" "0,1,2,3" bitfld.long 0x4 0.--1. "SINC,SINC" "0,1,2,3" line.long 0x8 "MDMA_C20BNDTR,In Linked List mode. at the end of a block (single or last block in repeated block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] + 0x04)." hexmask.long.word 0x8 20.--31. 1. "BRC,BRC" bitfld.long 0x8 19. "BRDUM,BRDUM" "0,1" bitfld.long 0x8 18. "BRSUM,BRSUM" "0,1" hexmask.long.tbyte 0x8 0.--16. 1. "BNDT,BNDT" line.long 0xC "MDMA_C20SAR,In Linked List mode. at the end of a Block (single or last Block in repeated Block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] + 0x08)." hexmask.long 0xC 0.--31. 1. "SAR,SAR" line.long 0x10 "MDMA_C20DAR,In Linked List mode. at the end of a block (single or last block in repeated block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M" hexmask.long 0x10 0.--31. 1. "DAR,DAR" line.long 0x14 "MDMA_C20BRUR,In Linked List mode. at the end of a block (single or last block in repeated block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] + 0x10)." hexmask.long.word 0x14 16.--31. 1. "DUV,DUV" hexmask.long.word 0x14 0.--15. 1. "SUV,SUV" line.long 0x18 "MDMA_C20LAR,In Linked List mode. at the end of a block (single or last block in repeated block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all.." hexmask.long 0x18 0.--31. 1. "LAR,LAR" line.long 0x1C "MDMA_C20TBR,In Linked List mode. at the end of a block (single or last block in repeated block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] + 0x18)." bitfld.long 0x1C 17. "DBUS,DBUS" "0,1" bitfld.long 0x1C 16. "SBUS,SBUS" "0,1" hexmask.long.byte 0x1C 0.--5. 1. "TSEL,TSEL" group.long 0x570++0x7 line.long 0x0 "MDMA_C20MAR,In Linked List mode. at the end of a block (single or last block in repeated block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] + 0x20)." hexmask.long 0x0 0.--31. 1. "MAR,MAR" line.long 0x4 "MDMA_C20MDR,In Linked List mode. at the end of a block (single or last block in repeated block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] + 0x24)." hexmask.long 0x4 0.--31. 1. "MDR,MDR" rgroup.long 0x580++0x3 line.long 0x0 "MDMA_C21ISR,MDMA channel 21 interrupt/status register" bitfld.long 0x0 16. "CRQA,CRQA" "0,1" bitfld.long 0x0 4. "TCIF,TCIF" "0,1" bitfld.long 0x0 3. "BTIF,BTIF" "0,1" bitfld.long 0x0 2. "BRTIF,BRTIF" "0,1" bitfld.long 0x0 1. "CTCIF,CTCIF" "0,1" bitfld.long 0x0 0. "TEIF,TEIF" "0,1" wgroup.long 0x584++0x3 line.long 0x0 "MDMA_C21IFCR,MDMA channel 21 interrupt flag clear register" bitfld.long 0x0 4. "CLTCIF,CLTCIF" "0,1" bitfld.long 0x0 3. "CBTIF,CBTIF" "0,1" bitfld.long 0x0 2. "CBRTIF,CBRTIF" "0,1" bitfld.long 0x0 1. "CCTCIF,CCTCIF" "0,1" bitfld.long 0x0 0. "CTEIF,CTEIF" "0,1" rgroup.long 0x588++0x3 line.long 0x0 "MDMA_C21ESR,MDMA channel 21 error status register" bitfld.long 0x0 11. "BSE,BSE" "0,1" bitfld.long 0x0 10. "ASE,ASE" "0,1" bitfld.long 0x0 9. "TEMD,TEMD" "0,1" bitfld.long 0x0 8. "TELD,TELD" "0,1" bitfld.long 0x0 7. "TED,TED" "0,1" hexmask.long.byte 0x0 0.--6. 1. "TEA,TEA" group.long 0x58C++0x1F line.long 0x0 "MDMA_C21CR,This register is used to control the concerned channel." bitfld.long 0x0 16. "SWRQ,SWRQ" "0,1" bitfld.long 0x0 14. "WEX,WEX" "0,1" bitfld.long 0x0 13. "HEX,HEX" "0,1" bitfld.long 0x0 12. "BEX,BEX" "0,1" bitfld.long 0x0 6.--7. "PL,PL" "0,1,2,3" bitfld.long 0x0 5. "TCIE,TCIE" "0,1" bitfld.long 0x0 4. "BTIE,BTIE" "0,1" bitfld.long 0x0 3. "BRTIE,BRTIE" "0,1" bitfld.long 0x0 2. "CTCIE,CTCIE" "0,1" bitfld.long 0x0 1. "TEIE,TEIE" "0,1" newline bitfld.long 0x0 0. "EN,EN" "0,1" line.long 0x4 "MDMA_C21TCR,This register is used to configure the concerned channel. In Linked List mode. at the end of a block (single or last block in repeated block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] +.." bitfld.long 0x4 31. "BWM,BWM" "0,1" bitfld.long 0x4 30. "SWRM,SWRM" "0,1" bitfld.long 0x4 28.--29. "TRGM,TRGM" "0,1,2,3" bitfld.long 0x4 26.--27. "PAM,PAM" "0,1,2,3" bitfld.long 0x4 25. "PKE,PKE" "0,1" hexmask.long.byte 0x4 18.--24. 1. "TLEN,TLEN" bitfld.long 0x4 15.--17. "DBURST,DBURST" "0,1,2,3,4,5,6,7" bitfld.long 0x4 12.--14. "SBURST,SBURST" "0,1,2,3,4,5,6,7" bitfld.long 0x4 10.--11. "DINCOS,DINCOS" "0,1,2,3" bitfld.long 0x4 8.--9. "SINCOS,SINCOS" "0,1,2,3" newline bitfld.long 0x4 6.--7. "DSIZE,DSIZE" "0,1,2,3" bitfld.long 0x4 4.--5. "SSIZE,SSIZE" "0,1,2,3" bitfld.long 0x4 2.--3. "DINC,DINC" "0,1,2,3" bitfld.long 0x4 0.--1. "SINC,SINC" "0,1,2,3" line.long 0x8 "MDMA_C21BNDTR,In Linked List mode. at the end of a block (single or last block in repeated block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] + 0x04)." hexmask.long.word 0x8 20.--31. 1. "BRC,BRC" bitfld.long 0x8 19. "BRDUM,BRDUM" "0,1" bitfld.long 0x8 18. "BRSUM,BRSUM" "0,1" hexmask.long.tbyte 0x8 0.--16. 1. "BNDT,BNDT" line.long 0xC "MDMA_C21SAR,In Linked List mode. at the end of a Block (single or last Block in repeated Block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] + 0x08)." hexmask.long 0xC 0.--31. 1. "SAR,SAR" line.long 0x10 "MDMA_C21DAR,In Linked List mode. at the end of a block (single or last block in repeated block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M" hexmask.long 0x10 0.--31. 1. "DAR,DAR" line.long 0x14 "MDMA_C21BRUR,In Linked List mode. at the end of a block (single or last block in repeated block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] + 0x10)." hexmask.long.word 0x14 16.--31. 1. "DUV,DUV" hexmask.long.word 0x14 0.--15. 1. "SUV,SUV" line.long 0x18 "MDMA_C21LAR,In Linked List mode. at the end of a block (single or last block in repeated block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all.." hexmask.long 0x18 0.--31. 1. "LAR,LAR" line.long 0x1C "MDMA_C21TBR,In Linked List mode. at the end of a block (single or last block in repeated block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] + 0x18)." bitfld.long 0x1C 17. "DBUS,DBUS" "0,1" bitfld.long 0x1C 16. "SBUS,SBUS" "0,1" hexmask.long.byte 0x1C 0.--5. 1. "TSEL,TSEL" group.long 0x5B0++0x7 line.long 0x0 "MDMA_C21MAR,In Linked List mode. at the end of a block (single or last block in repeated block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] + 0x20)." hexmask.long 0x0 0.--31. 1. "MAR,MAR" line.long 0x4 "MDMA_C21MDR,In Linked List mode. at the end of a block (single or last block in repeated block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] + 0x24)." hexmask.long 0x4 0.--31. 1. "MDR,MDR" rgroup.long 0x5C0++0x3 line.long 0x0 "MDMA_C22ISR,MDMA channel 22 interrupt/status register" bitfld.long 0x0 16. "CRQA,CRQA" "0,1" bitfld.long 0x0 4. "TCIF,TCIF" "0,1" bitfld.long 0x0 3. "BTIF,BTIF" "0,1" bitfld.long 0x0 2. "BRTIF,BRTIF" "0,1" bitfld.long 0x0 1. "CTCIF,CTCIF" "0,1" bitfld.long 0x0 0. "TEIF,TEIF" "0,1" wgroup.long 0x5C4++0x3 line.long 0x0 "MDMA_C22IFCR,MDMA channel 22 interrupt flag clear register" bitfld.long 0x0 4. "CLTCIF,CLTCIF" "0,1" bitfld.long 0x0 3. "CBTIF,CBTIF" "0,1" bitfld.long 0x0 2. "CBRTIF,CBRTIF" "0,1" bitfld.long 0x0 1. "CCTCIF,CCTCIF" "0,1" bitfld.long 0x0 0. "CTEIF,CTEIF" "0,1" rgroup.long 0x5C8++0x3 line.long 0x0 "MDMA_C22ESR,MDMA channel 22 error status register" bitfld.long 0x0 11. "BSE,BSE" "0,1" bitfld.long 0x0 10. "ASE,ASE" "0,1" bitfld.long 0x0 9. "TEMD,TEMD" "0,1" bitfld.long 0x0 8. "TELD,TELD" "0,1" bitfld.long 0x0 7. "TED,TED" "0,1" hexmask.long.byte 0x0 0.--6. 1. "TEA,TEA" group.long 0x5CC++0x1F line.long 0x0 "MDMA_C22CR,This register is used to control the concerned channel." bitfld.long 0x0 16. "SWRQ,SWRQ" "0,1" bitfld.long 0x0 14. "WEX,WEX" "0,1" bitfld.long 0x0 13. "HEX,HEX" "0,1" bitfld.long 0x0 12. "BEX,BEX" "0,1" bitfld.long 0x0 6.--7. "PL,PL" "0,1,2,3" bitfld.long 0x0 5. "TCIE,TCIE" "0,1" bitfld.long 0x0 4. "BTIE,BTIE" "0,1" bitfld.long 0x0 3. "BRTIE,BRTIE" "0,1" bitfld.long 0x0 2. "CTCIE,CTCIE" "0,1" bitfld.long 0x0 1. "TEIE,TEIE" "0,1" newline bitfld.long 0x0 0. "EN,EN" "0,1" line.long 0x4 "MDMA_C22TCR,This register is used to configure the concerned channel. In Linked List mode. at the end of a block (single or last block in repeated block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] +.." bitfld.long 0x4 31. "BWM,BWM" "0,1" bitfld.long 0x4 30. "SWRM,SWRM" "0,1" bitfld.long 0x4 28.--29. "TRGM,TRGM" "0,1,2,3" bitfld.long 0x4 26.--27. "PAM,PAM" "0,1,2,3" bitfld.long 0x4 25. "PKE,PKE" "0,1" hexmask.long.byte 0x4 18.--24. 1. "TLEN,TLEN" bitfld.long 0x4 15.--17. "DBURST,DBURST" "0,1,2,3,4,5,6,7" bitfld.long 0x4 12.--14. "SBURST,SBURST" "0,1,2,3,4,5,6,7" bitfld.long 0x4 10.--11. "DINCOS,DINCOS" "0,1,2,3" bitfld.long 0x4 8.--9. "SINCOS,SINCOS" "0,1,2,3" newline bitfld.long 0x4 6.--7. "DSIZE,DSIZE" "0,1,2,3" bitfld.long 0x4 4.--5. "SSIZE,SSIZE" "0,1,2,3" bitfld.long 0x4 2.--3. "DINC,DINC" "0,1,2,3" bitfld.long 0x4 0.--1. "SINC,SINC" "0,1,2,3" line.long 0x8 "MDMA_C22BNDTR,In Linked List mode. at the end of a block (single or last block in repeated block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] + 0x04)." hexmask.long.word 0x8 20.--31. 1. "BRC,BRC" bitfld.long 0x8 19. "BRDUM,BRDUM" "0,1" bitfld.long 0x8 18. "BRSUM,BRSUM" "0,1" hexmask.long.tbyte 0x8 0.--16. 1. "BNDT,BNDT" line.long 0xC "MDMA_C22SAR,In Linked List mode. at the end of a Block (single or last Block in repeated Block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] + 0x08)." hexmask.long 0xC 0.--31. 1. "SAR,SAR" line.long 0x10 "MDMA_C22DAR,In Linked List mode. at the end of a block (single or last block in repeated block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M" hexmask.long 0x10 0.--31. 1. "DAR,DAR" line.long 0x14 "MDMA_C22BRUR,In Linked List mode. at the end of a block (single or last block in repeated block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] + 0x10)." hexmask.long.word 0x14 16.--31. 1. "DUV,DUV" hexmask.long.word 0x14 0.--15. 1. "SUV,SUV" line.long 0x18 "MDMA_C22LAR,In Linked List mode. at the end of a block (single or last block in repeated block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all.." hexmask.long 0x18 0.--31. 1. "LAR,LAR" line.long 0x1C "MDMA_C22TBR,In Linked List mode. at the end of a block (single or last block in repeated block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] + 0x18)." bitfld.long 0x1C 17. "DBUS,DBUS" "0,1" bitfld.long 0x1C 16. "SBUS,SBUS" "0,1" hexmask.long.byte 0x1C 0.--5. 1. "TSEL,TSEL" group.long 0x5F0++0x7 line.long 0x0 "MDMA_C22MAR,In Linked List mode. at the end of a block (single or last block in repeated block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] + 0x20)." hexmask.long 0x0 0.--31. 1. "MAR,MAR" line.long 0x4 "MDMA_C22MDR,In Linked List mode. at the end of a block (single or last block in repeated block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] + 0x24)." hexmask.long 0x4 0.--31. 1. "MDR,MDR" rgroup.long 0x600++0x3 line.long 0x0 "MDMA_C23ISR,MDMA channel 23 interrupt/status register" bitfld.long 0x0 16. "CRQA,CRQA" "0,1" bitfld.long 0x0 4. "TCIF,TCIF" "0,1" bitfld.long 0x0 3. "BTIF,BTIF" "0,1" bitfld.long 0x0 2. "BRTIF,BRTIF" "0,1" bitfld.long 0x0 1. "CTCIF,CTCIF" "0,1" bitfld.long 0x0 0. "TEIF,TEIF" "0,1" wgroup.long 0x604++0x3 line.long 0x0 "MDMA_C23IFCR,MDMA channel 23 interrupt flag clear register" bitfld.long 0x0 4. "CLTCIF,CLTCIF" "0,1" bitfld.long 0x0 3. "CBTIF,CBTIF" "0,1" bitfld.long 0x0 2. "CBRTIF,CBRTIF" "0,1" bitfld.long 0x0 1. "CCTCIF,CCTCIF" "0,1" bitfld.long 0x0 0. "CTEIF,CTEIF" "0,1" rgroup.long 0x608++0x3 line.long 0x0 "MDMA_C23ESR,MDMA channel 23 error status register" bitfld.long 0x0 11. "BSE,BSE" "0,1" bitfld.long 0x0 10. "ASE,ASE" "0,1" bitfld.long 0x0 9. "TEMD,TEMD" "0,1" bitfld.long 0x0 8. "TELD,TELD" "0,1" bitfld.long 0x0 7. "TED,TED" "0,1" hexmask.long.byte 0x0 0.--6. 1. "TEA,TEA" group.long 0x60C++0x1F line.long 0x0 "MDMA_C23CR,This register is used to control the concerned channel." bitfld.long 0x0 16. "SWRQ,SWRQ" "0,1" bitfld.long 0x0 14. "WEX,WEX" "0,1" bitfld.long 0x0 13. "HEX,HEX" "0,1" bitfld.long 0x0 12. "BEX,BEX" "0,1" bitfld.long 0x0 6.--7. "PL,PL" "0,1,2,3" bitfld.long 0x0 5. "TCIE,TCIE" "0,1" bitfld.long 0x0 4. "BTIE,BTIE" "0,1" bitfld.long 0x0 3. "BRTIE,BRTIE" "0,1" bitfld.long 0x0 2. "CTCIE,CTCIE" "0,1" bitfld.long 0x0 1. "TEIE,TEIE" "0,1" newline bitfld.long 0x0 0. "EN,EN" "0,1" line.long 0x4 "MDMA_C23TCR,This register is used to configure the concerned channel. In Linked List mode. at the end of a block (single or last block in repeated block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] +.." bitfld.long 0x4 31. "BWM,BWM" "0,1" bitfld.long 0x4 30. "SWRM,SWRM" "0,1" bitfld.long 0x4 28.--29. "TRGM,TRGM" "0,1,2,3" bitfld.long 0x4 26.--27. "PAM,PAM" "0,1,2,3" bitfld.long 0x4 25. "PKE,PKE" "0,1" hexmask.long.byte 0x4 18.--24. 1. "TLEN,TLEN" bitfld.long 0x4 15.--17. "DBURST,DBURST" "0,1,2,3,4,5,6,7" bitfld.long 0x4 12.--14. "SBURST,SBURST" "0,1,2,3,4,5,6,7" bitfld.long 0x4 10.--11. "DINCOS,DINCOS" "0,1,2,3" bitfld.long 0x4 8.--9. "SINCOS,SINCOS" "0,1,2,3" newline bitfld.long 0x4 6.--7. "DSIZE,DSIZE" "0,1,2,3" bitfld.long 0x4 4.--5. "SSIZE,SSIZE" "0,1,2,3" bitfld.long 0x4 2.--3. "DINC,DINC" "0,1,2,3" bitfld.long 0x4 0.--1. "SINC,SINC" "0,1,2,3" line.long 0x8 "MDMA_C23BNDTR,In Linked List mode. at the end of a block (single or last block in repeated block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] + 0x04)." hexmask.long.word 0x8 20.--31. 1. "BRC,BRC" bitfld.long 0x8 19. "BRDUM,BRDUM" "0,1" bitfld.long 0x8 18. "BRSUM,BRSUM" "0,1" hexmask.long.tbyte 0x8 0.--16. 1. "BNDT,BNDT" line.long 0xC "MDMA_C23SAR,In Linked List mode. at the end of a Block (single or last Block in repeated Block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] + 0x08)." hexmask.long 0xC 0.--31. 1. "SAR,SAR" line.long 0x10 "MDMA_C23DAR,In Linked List mode. at the end of a block (single or last block in repeated block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M" hexmask.long 0x10 0.--31. 1. "DAR,DAR" line.long 0x14 "MDMA_C23BRUR,In Linked List mode. at the end of a block (single or last block in repeated block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] + 0x10)." hexmask.long.word 0x14 16.--31. 1. "DUV,DUV" hexmask.long.word 0x14 0.--15. 1. "SUV,SUV" line.long 0x18 "MDMA_C23LAR,In Linked List mode. at the end of a block (single or last block in repeated block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all.." hexmask.long 0x18 0.--31. 1. "LAR,LAR" line.long 0x1C "MDMA_C23TBR,In Linked List mode. at the end of a block (single or last block in repeated block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] + 0x18)." bitfld.long 0x1C 17. "DBUS,DBUS" "0,1" bitfld.long 0x1C 16. "SBUS,SBUS" "0,1" hexmask.long.byte 0x1C 0.--5. 1. "TSEL,TSEL" group.long 0x630++0x7 line.long 0x0 "MDMA_C23MAR,In Linked List mode. at the end of a block (single or last block in repeated block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] + 0x20)." hexmask.long 0x0 0.--31. 1. "MAR,MAR" line.long 0x4 "MDMA_C23MDR,In Linked List mode. at the end of a block (single or last block in repeated block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] + 0x24)." hexmask.long 0x4 0.--31. 1. "MDR,MDR" rgroup.long 0x640++0x3 line.long 0x0 "MDMA_C24ISR,MDMA channel 24 interrupt/status register" bitfld.long 0x0 16. "CRQA,CRQA" "0,1" bitfld.long 0x0 4. "TCIF,TCIF" "0,1" bitfld.long 0x0 3. "BTIF,BTIF" "0,1" bitfld.long 0x0 2. "BRTIF,BRTIF" "0,1" bitfld.long 0x0 1. "CTCIF,CTCIF" "0,1" bitfld.long 0x0 0. "TEIF,TEIF" "0,1" wgroup.long 0x644++0x3 line.long 0x0 "MDMA_C24IFCR,MDMA channel 24 interrupt flag clear register" bitfld.long 0x0 4. "CLTCIF,CLTCIF" "0,1" bitfld.long 0x0 3. "CBTIF,CBTIF" "0,1" bitfld.long 0x0 2. "CBRTIF,CBRTIF" "0,1" bitfld.long 0x0 1. "CCTCIF,CCTCIF" "0,1" bitfld.long 0x0 0. "CTEIF,CTEIF" "0,1" rgroup.long 0x648++0x3 line.long 0x0 "MDMA_C24ESR,MDMA channel 24 error status register" bitfld.long 0x0 11. "BSE,BSE" "0,1" bitfld.long 0x0 10. "ASE,ASE" "0,1" bitfld.long 0x0 9. "TEMD,TEMD" "0,1" bitfld.long 0x0 8. "TELD,TELD" "0,1" bitfld.long 0x0 7. "TED,TED" "0,1" hexmask.long.byte 0x0 0.--6. 1. "TEA,TEA" group.long 0x64C++0x1F line.long 0x0 "MDMA_C24CR,This register is used to control the concerned channel." bitfld.long 0x0 16. "SWRQ,SWRQ" "0,1" bitfld.long 0x0 14. "WEX,WEX" "0,1" bitfld.long 0x0 13. "HEX,HEX" "0,1" bitfld.long 0x0 12. "BEX,BEX" "0,1" bitfld.long 0x0 6.--7. "PL,PL" "0,1,2,3" bitfld.long 0x0 5. "TCIE,TCIE" "0,1" bitfld.long 0x0 4. "BTIE,BTIE" "0,1" bitfld.long 0x0 3. "BRTIE,BRTIE" "0,1" bitfld.long 0x0 2. "CTCIE,CTCIE" "0,1" bitfld.long 0x0 1. "TEIE,TEIE" "0,1" newline bitfld.long 0x0 0. "EN,EN" "0,1" line.long 0x4 "MDMA_C24TCR,This register is used to configure the concerned channel. In Linked List mode. at the end of a block (single or last block in repeated block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] +.." bitfld.long 0x4 31. "BWM,BWM" "0,1" bitfld.long 0x4 30. "SWRM,SWRM" "0,1" bitfld.long 0x4 28.--29. "TRGM,TRGM" "0,1,2,3" bitfld.long 0x4 26.--27. "PAM,PAM" "0,1,2,3" bitfld.long 0x4 25. "PKE,PKE" "0,1" hexmask.long.byte 0x4 18.--24. 1. "TLEN,TLEN" bitfld.long 0x4 15.--17. "DBURST,DBURST" "0,1,2,3,4,5,6,7" bitfld.long 0x4 12.--14. "SBURST,SBURST" "0,1,2,3,4,5,6,7" bitfld.long 0x4 10.--11. "DINCOS,DINCOS" "0,1,2,3" bitfld.long 0x4 8.--9. "SINCOS,SINCOS" "0,1,2,3" newline bitfld.long 0x4 6.--7. "DSIZE,DSIZE" "0,1,2,3" bitfld.long 0x4 4.--5. "SSIZE,SSIZE" "0,1,2,3" bitfld.long 0x4 2.--3. "DINC,DINC" "0,1,2,3" bitfld.long 0x4 0.--1. "SINC,SINC" "0,1,2,3" line.long 0x8 "MDMA_C24BNDTR,In Linked List mode. at the end of a block (single or last block in repeated block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] + 0x04)." hexmask.long.word 0x8 20.--31. 1. "BRC,BRC" bitfld.long 0x8 19. "BRDUM,BRDUM" "0,1" bitfld.long 0x8 18. "BRSUM,BRSUM" "0,1" hexmask.long.tbyte 0x8 0.--16. 1. "BNDT,BNDT" line.long 0xC "MDMA_C24SAR,In Linked List mode. at the end of a Block (single or last Block in repeated Block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] + 0x08)." hexmask.long 0xC 0.--31. 1. "SAR,SAR" line.long 0x10 "MDMA_C24DAR,In Linked List mode. at the end of a block (single or last block in repeated block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M" hexmask.long 0x10 0.--31. 1. "DAR,DAR" line.long 0x14 "MDMA_C24BRUR,In Linked List mode. at the end of a block (single or last block in repeated block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] + 0x10)." hexmask.long.word 0x14 16.--31. 1. "DUV,DUV" hexmask.long.word 0x14 0.--15. 1. "SUV,SUV" line.long 0x18 "MDMA_C24LAR,In Linked List mode. at the end of a block (single or last block in repeated block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all.." hexmask.long 0x18 0.--31. 1. "LAR,LAR" line.long 0x1C "MDMA_C24TBR,In Linked List mode. at the end of a block (single or last block in repeated block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] + 0x18)." bitfld.long 0x1C 17. "DBUS,DBUS" "0,1" bitfld.long 0x1C 16. "SBUS,SBUS" "0,1" hexmask.long.byte 0x1C 0.--5. 1. "TSEL,TSEL" group.long 0x670++0x7 line.long 0x0 "MDMA_C24MAR,In Linked List mode. at the end of a block (single or last block in repeated block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] + 0x20)." hexmask.long 0x0 0.--31. 1. "MAR,MAR" line.long 0x4 "MDMA_C24MDR,In Linked List mode. at the end of a block (single or last block in repeated block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] + 0x24)." hexmask.long 0x4 0.--31. 1. "MDR,MDR" rgroup.long 0x680++0x3 line.long 0x0 "MDMA_C25ISR,MDMA channel 25 interrupt/status register" bitfld.long 0x0 16. "CRQA,CRQA" "0,1" bitfld.long 0x0 4. "TCIF,TCIF" "0,1" bitfld.long 0x0 3. "BTIF,BTIF" "0,1" bitfld.long 0x0 2. "BRTIF,BRTIF" "0,1" bitfld.long 0x0 1. "CTCIF,CTCIF" "0,1" bitfld.long 0x0 0. "TEIF,TEIF" "0,1" wgroup.long 0x684++0x3 line.long 0x0 "MDMA_C25IFCR,MDMA channel 25 interrupt flag clear register" bitfld.long 0x0 4. "CLTCIF,CLTCIF" "0,1" bitfld.long 0x0 3. "CBTIF,CBTIF" "0,1" bitfld.long 0x0 2. "CBRTIF,CBRTIF" "0,1" bitfld.long 0x0 1. "CCTCIF,CCTCIF" "0,1" bitfld.long 0x0 0. "CTEIF,CTEIF" "0,1" rgroup.long 0x688++0x3 line.long 0x0 "MDMA_C25ESR,MDMA channel 25 error status register" bitfld.long 0x0 11. "BSE,BSE" "0,1" bitfld.long 0x0 10. "ASE,ASE" "0,1" bitfld.long 0x0 9. "TEMD,TEMD" "0,1" bitfld.long 0x0 8. "TELD,TELD" "0,1" bitfld.long 0x0 7. "TED,TED" "0,1" hexmask.long.byte 0x0 0.--6. 1. "TEA,TEA" group.long 0x68C++0x1F line.long 0x0 "MDMA_C25CR,This register is used to control the concerned channel." bitfld.long 0x0 16. "SWRQ,SWRQ" "0,1" bitfld.long 0x0 14. "WEX,WEX" "0,1" bitfld.long 0x0 13. "HEX,HEX" "0,1" bitfld.long 0x0 12. "BEX,BEX" "0,1" bitfld.long 0x0 6.--7. "PL,PL" "0,1,2,3" bitfld.long 0x0 5. "TCIE,TCIE" "0,1" bitfld.long 0x0 4. "BTIE,BTIE" "0,1" bitfld.long 0x0 3. "BRTIE,BRTIE" "0,1" bitfld.long 0x0 2. "CTCIE,CTCIE" "0,1" bitfld.long 0x0 1. "TEIE,TEIE" "0,1" newline bitfld.long 0x0 0. "EN,EN" "0,1" line.long 0x4 "MDMA_C25TCR,This register is used to configure the concerned channel. In Linked List mode. at the end of a block (single or last block in repeated block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] +.." bitfld.long 0x4 31. "BWM,BWM" "0,1" bitfld.long 0x4 30. "SWRM,SWRM" "0,1" bitfld.long 0x4 28.--29. "TRGM,TRGM" "0,1,2,3" bitfld.long 0x4 26.--27. "PAM,PAM" "0,1,2,3" bitfld.long 0x4 25. "PKE,PKE" "0,1" hexmask.long.byte 0x4 18.--24. 1. "TLEN,TLEN" bitfld.long 0x4 15.--17. "DBURST,DBURST" "0,1,2,3,4,5,6,7" bitfld.long 0x4 12.--14. "SBURST,SBURST" "0,1,2,3,4,5,6,7" bitfld.long 0x4 10.--11. "DINCOS,DINCOS" "0,1,2,3" bitfld.long 0x4 8.--9. "SINCOS,SINCOS" "0,1,2,3" newline bitfld.long 0x4 6.--7. "DSIZE,DSIZE" "0,1,2,3" bitfld.long 0x4 4.--5. "SSIZE,SSIZE" "0,1,2,3" bitfld.long 0x4 2.--3. "DINC,DINC" "0,1,2,3" bitfld.long 0x4 0.--1. "SINC,SINC" "0,1,2,3" line.long 0x8 "MDMA_C25BNDTR,In Linked List mode. at the end of a block (single or last block in repeated block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] + 0x04)." hexmask.long.word 0x8 20.--31. 1. "BRC,BRC" bitfld.long 0x8 19. "BRDUM,BRDUM" "0,1" bitfld.long 0x8 18. "BRSUM,BRSUM" "0,1" hexmask.long.tbyte 0x8 0.--16. 1. "BNDT,BNDT" line.long 0xC "MDMA_C25SAR,In Linked List mode. at the end of a Block (single or last Block in repeated Block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] + 0x08)." hexmask.long 0xC 0.--31. 1. "SAR,SAR" line.long 0x10 "MDMA_C25DAR,In Linked List mode. at the end of a block (single or last block in repeated block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M" hexmask.long 0x10 0.--31. 1. "DAR,DAR" line.long 0x14 "MDMA_C25BRUR,In Linked List mode. at the end of a block (single or last block in repeated block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] + 0x10)." hexmask.long.word 0x14 16.--31. 1. "DUV,DUV" hexmask.long.word 0x14 0.--15. 1. "SUV,SUV" line.long 0x18 "MDMA_C25LAR,In Linked List mode. at the end of a block (single or last block in repeated block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all.." hexmask.long 0x18 0.--31. 1. "LAR,LAR" line.long 0x1C "MDMA_C25TBR,In Linked List mode. at the end of a block (single or last block in repeated block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] + 0x18)." bitfld.long 0x1C 17. "DBUS,DBUS" "0,1" bitfld.long 0x1C 16. "SBUS,SBUS" "0,1" hexmask.long.byte 0x1C 0.--5. 1. "TSEL,TSEL" group.long 0x6B0++0x7 line.long 0x0 "MDMA_C25MAR,In Linked List mode. at the end of a block (single or last block in repeated block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] + 0x20)." hexmask.long 0x0 0.--31. 1. "MAR,MAR" line.long 0x4 "MDMA_C25MDR,In Linked List mode. at the end of a block (single or last block in repeated block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] + 0x24)." hexmask.long 0x4 0.--31. 1. "MDR,MDR" rgroup.long 0x6C0++0x3 line.long 0x0 "MDMA_C26ISR,MDMA channel 26 interrupt/status register" bitfld.long 0x0 16. "CRQA,CRQA" "0,1" bitfld.long 0x0 4. "TCIF,TCIF" "0,1" bitfld.long 0x0 3. "BTIF,BTIF" "0,1" bitfld.long 0x0 2. "BRTIF,BRTIF" "0,1" bitfld.long 0x0 1. "CTCIF,CTCIF" "0,1" bitfld.long 0x0 0. "TEIF,TEIF" "0,1" wgroup.long 0x6C4++0x3 line.long 0x0 "MDMA_C26IFCR,MDMA channel 26 interrupt flag clear register" bitfld.long 0x0 4. "CLTCIF,CLTCIF" "0,1" bitfld.long 0x0 3. "CBTIF,CBTIF" "0,1" bitfld.long 0x0 2. "CBRTIF,CBRTIF" "0,1" bitfld.long 0x0 1. "CCTCIF,CCTCIF" "0,1" bitfld.long 0x0 0. "CTEIF,CTEIF" "0,1" rgroup.long 0x6C8++0x3 line.long 0x0 "MDMA_C26ESR,MDMA channel 26 error status register" bitfld.long 0x0 11. "BSE,BSE" "0,1" bitfld.long 0x0 10. "ASE,ASE" "0,1" bitfld.long 0x0 9. "TEMD,TEMD" "0,1" bitfld.long 0x0 8. "TELD,TELD" "0,1" bitfld.long 0x0 7. "TED,TED" "0,1" hexmask.long.byte 0x0 0.--6. 1. "TEA,TEA" group.long 0x6CC++0x1F line.long 0x0 "MDMA_C26CR,This register is used to control the concerned channel." bitfld.long 0x0 16. "SWRQ,SWRQ" "0,1" bitfld.long 0x0 14. "WEX,WEX" "0,1" bitfld.long 0x0 13. "HEX,HEX" "0,1" bitfld.long 0x0 12. "BEX,BEX" "0,1" bitfld.long 0x0 6.--7. "PL,PL" "0,1,2,3" bitfld.long 0x0 5. "TCIE,TCIE" "0,1" bitfld.long 0x0 4. "BTIE,BTIE" "0,1" bitfld.long 0x0 3. "BRTIE,BRTIE" "0,1" bitfld.long 0x0 2. "CTCIE,CTCIE" "0,1" bitfld.long 0x0 1. "TEIE,TEIE" "0,1" newline bitfld.long 0x0 0. "EN,EN" "0,1" line.long 0x4 "MDMA_C26TCR,This register is used to configure the concerned channel. In Linked List mode. at the end of a block (single or last block in repeated block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] +.." bitfld.long 0x4 31. "BWM,BWM" "0,1" bitfld.long 0x4 30. "SWRM,SWRM" "0,1" bitfld.long 0x4 28.--29. "TRGM,TRGM" "0,1,2,3" bitfld.long 0x4 26.--27. "PAM,PAM" "0,1,2,3" bitfld.long 0x4 25. "PKE,PKE" "0,1" hexmask.long.byte 0x4 18.--24. 1. "TLEN,TLEN" bitfld.long 0x4 15.--17. "DBURST,DBURST" "0,1,2,3,4,5,6,7" bitfld.long 0x4 12.--14. "SBURST,SBURST" "0,1,2,3,4,5,6,7" bitfld.long 0x4 10.--11. "DINCOS,DINCOS" "0,1,2,3" bitfld.long 0x4 8.--9. "SINCOS,SINCOS" "0,1,2,3" newline bitfld.long 0x4 6.--7. "DSIZE,DSIZE" "0,1,2,3" bitfld.long 0x4 4.--5. "SSIZE,SSIZE" "0,1,2,3" bitfld.long 0x4 2.--3. "DINC,DINC" "0,1,2,3" bitfld.long 0x4 0.--1. "SINC,SINC" "0,1,2,3" line.long 0x8 "MDMA_C26BNDTR,In Linked List mode. at the end of a block (single or last block in repeated block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] + 0x04)." hexmask.long.word 0x8 20.--31. 1. "BRC,BRC" bitfld.long 0x8 19. "BRDUM,BRDUM" "0,1" bitfld.long 0x8 18. "BRSUM,BRSUM" "0,1" hexmask.long.tbyte 0x8 0.--16. 1. "BNDT,BNDT" line.long 0xC "MDMA_C26SAR,In Linked List mode. at the end of a Block (single or last Block in repeated Block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] + 0x08)." hexmask.long 0xC 0.--31. 1. "SAR,SAR" line.long 0x10 "MDMA_C26DAR,In Linked List mode. at the end of a block (single or last block in repeated block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M" hexmask.long 0x10 0.--31. 1. "DAR,DAR" line.long 0x14 "MDMA_C26BRUR,In Linked List mode. at the end of a block (single or last block in repeated block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] + 0x10)." hexmask.long.word 0x14 16.--31. 1. "DUV,DUV" hexmask.long.word 0x14 0.--15. 1. "SUV,SUV" line.long 0x18 "MDMA_C26LAR,In Linked List mode. at the end of a block (single or last block in repeated block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all.." hexmask.long 0x18 0.--31. 1. "LAR,LAR" line.long 0x1C "MDMA_C26TBR,In Linked List mode. at the end of a block (single or last block in repeated block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] + 0x18)." bitfld.long 0x1C 17. "DBUS,DBUS" "0,1" bitfld.long 0x1C 16. "SBUS,SBUS" "0,1" hexmask.long.byte 0x1C 0.--5. 1. "TSEL,TSEL" group.long 0x6F0++0x7 line.long 0x0 "MDMA_C26MAR,In Linked List mode. at the end of a block (single or last block in repeated block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] + 0x20)." hexmask.long 0x0 0.--31. 1. "MAR,MAR" line.long 0x4 "MDMA_C26MDR,In Linked List mode. at the end of a block (single or last block in repeated block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] + 0x24)." hexmask.long 0x4 0.--31. 1. "MDR,MDR" rgroup.long 0x700++0x3 line.long 0x0 "MDMA_C27ISR,MDMA channel 27 interrupt/status register" bitfld.long 0x0 16. "CRQA,CRQA" "0,1" bitfld.long 0x0 4. "TCIF,TCIF" "0,1" bitfld.long 0x0 3. "BTIF,BTIF" "0,1" bitfld.long 0x0 2. "BRTIF,BRTIF" "0,1" bitfld.long 0x0 1. "CTCIF,CTCIF" "0,1" bitfld.long 0x0 0. "TEIF,TEIF" "0,1" wgroup.long 0x704++0x3 line.long 0x0 "MDMA_C27IFCR,MDMA channel 27 interrupt flag clear register" bitfld.long 0x0 4. "CLTCIF,CLTCIF" "0,1" bitfld.long 0x0 3. "CBTIF,CBTIF" "0,1" bitfld.long 0x0 2. "CBRTIF,CBRTIF" "0,1" bitfld.long 0x0 1. "CCTCIF,CCTCIF" "0,1" bitfld.long 0x0 0. "CTEIF,CTEIF" "0,1" rgroup.long 0x708++0x3 line.long 0x0 "MDMA_C27ESR,MDMA channel 27 error status register" bitfld.long 0x0 11. "BSE,BSE" "0,1" bitfld.long 0x0 10. "ASE,ASE" "0,1" bitfld.long 0x0 9. "TEMD,TEMD" "0,1" bitfld.long 0x0 8. "TELD,TELD" "0,1" bitfld.long 0x0 7. "TED,TED" "0,1" hexmask.long.byte 0x0 0.--6. 1. "TEA,TEA" group.long 0x70C++0x1F line.long 0x0 "MDMA_C27CR,This register is used to control the concerned channel." bitfld.long 0x0 16. "SWRQ,SWRQ" "0,1" bitfld.long 0x0 14. "WEX,WEX" "0,1" bitfld.long 0x0 13. "HEX,HEX" "0,1" bitfld.long 0x0 12. "BEX,BEX" "0,1" bitfld.long 0x0 6.--7. "PL,PL" "0,1,2,3" bitfld.long 0x0 5. "TCIE,TCIE" "0,1" bitfld.long 0x0 4. "BTIE,BTIE" "0,1" bitfld.long 0x0 3. "BRTIE,BRTIE" "0,1" bitfld.long 0x0 2. "CTCIE,CTCIE" "0,1" bitfld.long 0x0 1. "TEIE,TEIE" "0,1" newline bitfld.long 0x0 0. "EN,EN" "0,1" line.long 0x4 "MDMA_C27TCR,This register is used to configure the concerned channel. In Linked List mode. at the end of a block (single or last block in repeated block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] +.." bitfld.long 0x4 31. "BWM,BWM" "0,1" bitfld.long 0x4 30. "SWRM,SWRM" "0,1" bitfld.long 0x4 28.--29. "TRGM,TRGM" "0,1,2,3" bitfld.long 0x4 26.--27. "PAM,PAM" "0,1,2,3" bitfld.long 0x4 25. "PKE,PKE" "0,1" hexmask.long.byte 0x4 18.--24. 1. "TLEN,TLEN" bitfld.long 0x4 15.--17. "DBURST,DBURST" "0,1,2,3,4,5,6,7" bitfld.long 0x4 12.--14. "SBURST,SBURST" "0,1,2,3,4,5,6,7" bitfld.long 0x4 10.--11. "DINCOS,DINCOS" "0,1,2,3" bitfld.long 0x4 8.--9. "SINCOS,SINCOS" "0,1,2,3" newline bitfld.long 0x4 6.--7. "DSIZE,DSIZE" "0,1,2,3" bitfld.long 0x4 4.--5. "SSIZE,SSIZE" "0,1,2,3" bitfld.long 0x4 2.--3. "DINC,DINC" "0,1,2,3" bitfld.long 0x4 0.--1. "SINC,SINC" "0,1,2,3" line.long 0x8 "MDMA_C27BNDTR,In Linked List mode. at the end of a block (single or last block in repeated block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] + 0x04)." hexmask.long.word 0x8 20.--31. 1. "BRC,BRC" bitfld.long 0x8 19. "BRDUM,BRDUM" "0,1" bitfld.long 0x8 18. "BRSUM,BRSUM" "0,1" hexmask.long.tbyte 0x8 0.--16. 1. "BNDT,BNDT" line.long 0xC "MDMA_C27SAR,In Linked List mode. at the end of a Block (single or last Block in repeated Block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] + 0x08)." hexmask.long 0xC 0.--31. 1. "SAR,SAR" line.long 0x10 "MDMA_C27DAR,In Linked List mode. at the end of a block (single or last block in repeated block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M" hexmask.long 0x10 0.--31. 1. "DAR,DAR" line.long 0x14 "MDMA_C27BRUR,In Linked List mode. at the end of a block (single or last block in repeated block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] + 0x10)." hexmask.long.word 0x14 16.--31. 1. "DUV,DUV" hexmask.long.word 0x14 0.--15. 1. "SUV,SUV" line.long 0x18 "MDMA_C27LAR,In Linked List mode. at the end of a block (single or last block in repeated block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all.." hexmask.long 0x18 0.--31. 1. "LAR,LAR" line.long 0x1C "MDMA_C27TBR,In Linked List mode. at the end of a block (single or last block in repeated block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] + 0x18)." bitfld.long 0x1C 17. "DBUS,DBUS" "0,1" bitfld.long 0x1C 16. "SBUS,SBUS" "0,1" hexmask.long.byte 0x1C 0.--5. 1. "TSEL,TSEL" group.long 0x730++0x7 line.long 0x0 "MDMA_C27MAR,In Linked List mode. at the end of a block (single or last block in repeated block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] + 0x20)." hexmask.long 0x0 0.--31. 1. "MAR,MAR" line.long 0x4 "MDMA_C27MDR,In Linked List mode. at the end of a block (single or last block in repeated block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] + 0x24)." hexmask.long 0x4 0.--31. 1. "MDR,MDR" rgroup.long 0x740++0x3 line.long 0x0 "MDMA_C28ISR,MDMA channel 28 interrupt/status register" bitfld.long 0x0 16. "CRQA,CRQA" "0,1" bitfld.long 0x0 4. "TCIF,TCIF" "0,1" bitfld.long 0x0 3. "BTIF,BTIF" "0,1" bitfld.long 0x0 2. "BRTIF,BRTIF" "0,1" bitfld.long 0x0 1. "CTCIF,CTCIF" "0,1" bitfld.long 0x0 0. "TEIF,TEIF" "0,1" wgroup.long 0x744++0x3 line.long 0x0 "MDMA_C28IFCR,MDMA channel 28 interrupt flag clear register" bitfld.long 0x0 4. "CLTCIF,CLTCIF" "0,1" bitfld.long 0x0 3. "CBTIF,CBTIF" "0,1" bitfld.long 0x0 2. "CBRTIF,CBRTIF" "0,1" bitfld.long 0x0 1. "CCTCIF,CCTCIF" "0,1" bitfld.long 0x0 0. "CTEIF,CTEIF" "0,1" rgroup.long 0x748++0x3 line.long 0x0 "MDMA_C28ESR,MDMA channel 28 error status register" bitfld.long 0x0 11. "BSE,BSE" "0,1" bitfld.long 0x0 10. "ASE,ASE" "0,1" bitfld.long 0x0 9. "TEMD,TEMD" "0,1" bitfld.long 0x0 8. "TELD,TELD" "0,1" bitfld.long 0x0 7. "TED,TED" "0,1" hexmask.long.byte 0x0 0.--6. 1. "TEA,TEA" group.long 0x74C++0x1F line.long 0x0 "MDMA_C28CR,This register is used to control the concerned channel." bitfld.long 0x0 16. "SWRQ,SWRQ" "0,1" bitfld.long 0x0 14. "WEX,WEX" "0,1" bitfld.long 0x0 13. "HEX,HEX" "0,1" bitfld.long 0x0 12. "BEX,BEX" "0,1" bitfld.long 0x0 6.--7. "PL,PL" "0,1,2,3" bitfld.long 0x0 5. "TCIE,TCIE" "0,1" bitfld.long 0x0 4. "BTIE,BTIE" "0,1" bitfld.long 0x0 3. "BRTIE,BRTIE" "0,1" bitfld.long 0x0 2. "CTCIE,CTCIE" "0,1" bitfld.long 0x0 1. "TEIE,TEIE" "0,1" newline bitfld.long 0x0 0. "EN,EN" "0,1" line.long 0x4 "MDMA_C28TCR,This register is used to configure the concerned channel. In Linked List mode. at the end of a block (single or last block in repeated block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] +.." bitfld.long 0x4 31. "BWM,BWM" "0,1" bitfld.long 0x4 30. "SWRM,SWRM" "0,1" bitfld.long 0x4 28.--29. "TRGM,TRGM" "0,1,2,3" bitfld.long 0x4 26.--27. "PAM,PAM" "0,1,2,3" bitfld.long 0x4 25. "PKE,PKE" "0,1" hexmask.long.byte 0x4 18.--24. 1. "TLEN,TLEN" bitfld.long 0x4 15.--17. "DBURST,DBURST" "0,1,2,3,4,5,6,7" bitfld.long 0x4 12.--14. "SBURST,SBURST" "0,1,2,3,4,5,6,7" bitfld.long 0x4 10.--11. "DINCOS,DINCOS" "0,1,2,3" bitfld.long 0x4 8.--9. "SINCOS,SINCOS" "0,1,2,3" newline bitfld.long 0x4 6.--7. "DSIZE,DSIZE" "0,1,2,3" bitfld.long 0x4 4.--5. "SSIZE,SSIZE" "0,1,2,3" bitfld.long 0x4 2.--3. "DINC,DINC" "0,1,2,3" bitfld.long 0x4 0.--1. "SINC,SINC" "0,1,2,3" line.long 0x8 "MDMA_C28BNDTR,In Linked List mode. at the end of a block (single or last block in repeated block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] + 0x04)." hexmask.long.word 0x8 20.--31. 1. "BRC,BRC" bitfld.long 0x8 19. "BRDUM,BRDUM" "0,1" bitfld.long 0x8 18. "BRSUM,BRSUM" "0,1" hexmask.long.tbyte 0x8 0.--16. 1. "BNDT,BNDT" line.long 0xC "MDMA_C28SAR,In Linked List mode. at the end of a Block (single or last Block in repeated Block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] + 0x08)." hexmask.long 0xC 0.--31. 1. "SAR,SAR" line.long 0x10 "MDMA_C28DAR,In Linked List mode. at the end of a block (single or last block in repeated block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M" hexmask.long 0x10 0.--31. 1. "DAR,DAR" line.long 0x14 "MDMA_C28BRUR,In Linked List mode. at the end of a block (single or last block in repeated block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] + 0x10)." hexmask.long.word 0x14 16.--31. 1. "DUV,DUV" hexmask.long.word 0x14 0.--15. 1. "SUV,SUV" line.long 0x18 "MDMA_C28LAR,In Linked List mode. at the end of a block (single or last block in repeated block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all.." hexmask.long 0x18 0.--31. 1. "LAR,LAR" line.long 0x1C "MDMA_C28TBR,In Linked List mode. at the end of a block (single or last block in repeated block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] + 0x18)." bitfld.long 0x1C 17. "DBUS,DBUS" "0,1" bitfld.long 0x1C 16. "SBUS,SBUS" "0,1" hexmask.long.byte 0x1C 0.--5. 1. "TSEL,TSEL" group.long 0x770++0x7 line.long 0x0 "MDMA_C28MAR,In Linked List mode. at the end of a block (single or last block in repeated block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] + 0x20)." hexmask.long 0x0 0.--31. 1. "MAR,MAR" line.long 0x4 "MDMA_C28MDR,In Linked List mode. at the end of a block (single or last block in repeated block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] + 0x24)." hexmask.long 0x4 0.--31. 1. "MDR,MDR" rgroup.long 0x780++0x3 line.long 0x0 "MDMA_C29ISR,MDMA channel 29 interrupt/status register" bitfld.long 0x0 16. "CRQA,CRQA" "0,1" bitfld.long 0x0 4. "TCIF,TCIF" "0,1" bitfld.long 0x0 3. "BTIF,BTIF" "0,1" bitfld.long 0x0 2. "BRTIF,BRTIF" "0,1" bitfld.long 0x0 1. "CTCIF,CTCIF" "0,1" bitfld.long 0x0 0. "TEIF,TEIF" "0,1" wgroup.long 0x784++0x3 line.long 0x0 "MDMA_C29IFCR,MDMA channel 29 interrupt flag clear register" bitfld.long 0x0 4. "CLTCIF,CLTCIF" "0,1" bitfld.long 0x0 3. "CBTIF,CBTIF" "0,1" bitfld.long 0x0 2. "CBRTIF,CBRTIF" "0,1" bitfld.long 0x0 1. "CCTCIF,CCTCIF" "0,1" bitfld.long 0x0 0. "CTEIF,CTEIF" "0,1" rgroup.long 0x788++0x3 line.long 0x0 "MDMA_C29ESR,MDMA channel 29 error status register" bitfld.long 0x0 11. "BSE,BSE" "0,1" bitfld.long 0x0 10. "ASE,ASE" "0,1" bitfld.long 0x0 9. "TEMD,TEMD" "0,1" bitfld.long 0x0 8. "TELD,TELD" "0,1" bitfld.long 0x0 7. "TED,TED" "0,1" hexmask.long.byte 0x0 0.--6. 1. "TEA,TEA" group.long 0x78C++0x1F line.long 0x0 "MDMA_C29CR,This register is used to control the concerned channel." bitfld.long 0x0 16. "SWRQ,SWRQ" "0,1" bitfld.long 0x0 14. "WEX,WEX" "0,1" bitfld.long 0x0 13. "HEX,HEX" "0,1" bitfld.long 0x0 12. "BEX,BEX" "0,1" bitfld.long 0x0 6.--7. "PL,PL" "0,1,2,3" bitfld.long 0x0 5. "TCIE,TCIE" "0,1" bitfld.long 0x0 4. "BTIE,BTIE" "0,1" bitfld.long 0x0 3. "BRTIE,BRTIE" "0,1" bitfld.long 0x0 2. "CTCIE,CTCIE" "0,1" bitfld.long 0x0 1. "TEIE,TEIE" "0,1" newline bitfld.long 0x0 0. "EN,EN" "0,1" line.long 0x4 "MDMA_C29TCR,This register is used to configure the concerned channel. In Linked List mode. at the end of a block (single or last block in repeated block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] +.." bitfld.long 0x4 31. "BWM,BWM" "0,1" bitfld.long 0x4 30. "SWRM,SWRM" "0,1" bitfld.long 0x4 28.--29. "TRGM,TRGM" "0,1,2,3" bitfld.long 0x4 26.--27. "PAM,PAM" "0,1,2,3" bitfld.long 0x4 25. "PKE,PKE" "0,1" hexmask.long.byte 0x4 18.--24. 1. "TLEN,TLEN" bitfld.long 0x4 15.--17. "DBURST,DBURST" "0,1,2,3,4,5,6,7" bitfld.long 0x4 12.--14. "SBURST,SBURST" "0,1,2,3,4,5,6,7" bitfld.long 0x4 10.--11. "DINCOS,DINCOS" "0,1,2,3" bitfld.long 0x4 8.--9. "SINCOS,SINCOS" "0,1,2,3" newline bitfld.long 0x4 6.--7. "DSIZE,DSIZE" "0,1,2,3" bitfld.long 0x4 4.--5. "SSIZE,SSIZE" "0,1,2,3" bitfld.long 0x4 2.--3. "DINC,DINC" "0,1,2,3" bitfld.long 0x4 0.--1. "SINC,SINC" "0,1,2,3" line.long 0x8 "MDMA_C29BNDTR,In Linked List mode. at the end of a block (single or last block in repeated block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] + 0x04)." hexmask.long.word 0x8 20.--31. 1. "BRC,BRC" bitfld.long 0x8 19. "BRDUM,BRDUM" "0,1" bitfld.long 0x8 18. "BRSUM,BRSUM" "0,1" hexmask.long.tbyte 0x8 0.--16. 1. "BNDT,BNDT" line.long 0xC "MDMA_C29SAR,In Linked List mode. at the end of a Block (single or last Block in repeated Block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] + 0x08)." hexmask.long 0xC 0.--31. 1. "SAR,SAR" line.long 0x10 "MDMA_C29DAR,In Linked List mode. at the end of a block (single or last block in repeated block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M" hexmask.long 0x10 0.--31. 1. "DAR,DAR" line.long 0x14 "MDMA_C29BRUR,In Linked List mode. at the end of a block (single or last block in repeated block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] + 0x10)." hexmask.long.word 0x14 16.--31. 1. "DUV,DUV" hexmask.long.word 0x14 0.--15. 1. "SUV,SUV" line.long 0x18 "MDMA_C29LAR,In Linked List mode. at the end of a block (single or last block in repeated block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all.." hexmask.long 0x18 0.--31. 1. "LAR,LAR" line.long 0x1C "MDMA_C29TBR,In Linked List mode. at the end of a block (single or last block in repeated block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] + 0x18)." bitfld.long 0x1C 17. "DBUS,DBUS" "0,1" bitfld.long 0x1C 16. "SBUS,SBUS" "0,1" hexmask.long.byte 0x1C 0.--5. 1. "TSEL,TSEL" group.long 0x7B0++0x7 line.long 0x0 "MDMA_C29MAR,In Linked List mode. at the end of a block (single or last block in repeated block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] + 0x20)." hexmask.long 0x0 0.--31. 1. "MAR,MAR" line.long 0x4 "MDMA_C29MDR,In Linked List mode. at the end of a block (single or last block in repeated block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] + 0x24)." hexmask.long 0x4 0.--31. 1. "MDR,MDR" rgroup.long 0x7C0++0x3 line.long 0x0 "MDMA_C30ISR,MDMA channel 30 interrupt/status register" bitfld.long 0x0 16. "CRQA,CRQA" "0,1" bitfld.long 0x0 4. "TCIF,TCIF" "0,1" bitfld.long 0x0 3. "BTIF,BTIF" "0,1" bitfld.long 0x0 2. "BRTIF,BRTIF" "0,1" bitfld.long 0x0 1. "CTCIF,CTCIF" "0,1" bitfld.long 0x0 0. "TEIF,TEIF" "0,1" wgroup.long 0x7C4++0x3 line.long 0x0 "MDMA_C30IFCR,MDMA channel 30 interrupt flag clear register" bitfld.long 0x0 4. "CLTCIF,CLTCIF" "0,1" bitfld.long 0x0 3. "CBTIF,CBTIF" "0,1" bitfld.long 0x0 2. "CBRTIF,CBRTIF" "0,1" bitfld.long 0x0 1. "CCTCIF,CCTCIF" "0,1" bitfld.long 0x0 0. "CTEIF,CTEIF" "0,1" rgroup.long 0x7C8++0x3 line.long 0x0 "MDMA_C30ESR,MDMA channel 30 error status register" bitfld.long 0x0 11. "BSE,BSE" "0,1" bitfld.long 0x0 10. "ASE,ASE" "0,1" bitfld.long 0x0 9. "TEMD,TEMD" "0,1" bitfld.long 0x0 8. "TELD,TELD" "0,1" bitfld.long 0x0 7. "TED,TED" "0,1" hexmask.long.byte 0x0 0.--6. 1. "TEA,TEA" group.long 0x7CC++0x1F line.long 0x0 "MDMA_C30CR,This register is used to control the concerned channel." bitfld.long 0x0 16. "SWRQ,SWRQ" "0,1" bitfld.long 0x0 14. "WEX,WEX" "0,1" bitfld.long 0x0 13. "HEX,HEX" "0,1" bitfld.long 0x0 12. "BEX,BEX" "0,1" bitfld.long 0x0 6.--7. "PL,PL" "0,1,2,3" bitfld.long 0x0 5. "TCIE,TCIE" "0,1" bitfld.long 0x0 4. "BTIE,BTIE" "0,1" bitfld.long 0x0 3. "BRTIE,BRTIE" "0,1" bitfld.long 0x0 2. "CTCIE,CTCIE" "0,1" bitfld.long 0x0 1. "TEIE,TEIE" "0,1" newline bitfld.long 0x0 0. "EN,EN" "0,1" line.long 0x4 "MDMA_C30TCR,This register is used to configure the concerned channel. In Linked List mode. at the end of a block (single or last block in repeated block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] +.." bitfld.long 0x4 31. "BWM,BWM" "0,1" bitfld.long 0x4 30. "SWRM,SWRM" "0,1" bitfld.long 0x4 28.--29. "TRGM,TRGM" "0,1,2,3" bitfld.long 0x4 26.--27. "PAM,PAM" "0,1,2,3" bitfld.long 0x4 25. "PKE,PKE" "0,1" hexmask.long.byte 0x4 18.--24. 1. "TLEN,TLEN" bitfld.long 0x4 15.--17. "DBURST,DBURST" "0,1,2,3,4,5,6,7" bitfld.long 0x4 12.--14. "SBURST,SBURST" "0,1,2,3,4,5,6,7" bitfld.long 0x4 10.--11. "DINCOS,DINCOS" "0,1,2,3" bitfld.long 0x4 8.--9. "SINCOS,SINCOS" "0,1,2,3" newline bitfld.long 0x4 6.--7. "DSIZE,DSIZE" "0,1,2,3" bitfld.long 0x4 4.--5. "SSIZE,SSIZE" "0,1,2,3" bitfld.long 0x4 2.--3. "DINC,DINC" "0,1,2,3" bitfld.long 0x4 0.--1. "SINC,SINC" "0,1,2,3" line.long 0x8 "MDMA_C30BNDTR,In Linked List mode. at the end of a block (single or last block in repeated block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] + 0x04)." hexmask.long.word 0x8 20.--31. 1. "BRC,BRC" bitfld.long 0x8 19. "BRDUM,BRDUM" "0,1" bitfld.long 0x8 18. "BRSUM,BRSUM" "0,1" hexmask.long.tbyte 0x8 0.--16. 1. "BNDT,BNDT" line.long 0xC "MDMA_C30SAR,In Linked List mode. at the end of a Block (single or last Block in repeated Block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] + 0x08)." hexmask.long 0xC 0.--31. 1. "SAR,SAR" line.long 0x10 "MDMA_C30DAR,In Linked List mode. at the end of a block (single or last block in repeated block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M" hexmask.long 0x10 0.--31. 1. "DAR,DAR" line.long 0x14 "MDMA_C30BRUR,In Linked List mode. at the end of a block (single or last block in repeated block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] + 0x10)." hexmask.long.word 0x14 16.--31. 1. "DUV,DUV" hexmask.long.word 0x14 0.--15. 1. "SUV,SUV" line.long 0x18 "MDMA_C30LAR,In Linked List mode. at the end of a block (single or last block in repeated block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all.." hexmask.long 0x18 0.--31. 1. "LAR,LAR" line.long 0x1C "MDMA_C30TBR,In Linked List mode. at the end of a block (single or last block in repeated block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] + 0x18)." bitfld.long 0x1C 17. "DBUS,DBUS" "0,1" bitfld.long 0x1C 16. "SBUS,SBUS" "0,1" hexmask.long.byte 0x1C 0.--5. 1. "TSEL,TSEL" group.long 0x7F0++0x7 line.long 0x0 "MDMA_C30MAR,In Linked List mode. at the end of a block (single or last block in repeated block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] + 0x20)." hexmask.long 0x0 0.--31. 1. "MAR,MAR" line.long 0x4 "MDMA_C30MDR,In Linked List mode. at the end of a block (single or last block in repeated block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] + 0x24)." hexmask.long 0x4 0.--31. 1. "MDR,MDR" rgroup.long 0x800++0x3 line.long 0x0 "MDMA_C31ISR,MDMA channel 31 interrupt/status register" bitfld.long 0x0 16. "CRQA,CRQA" "0,1" bitfld.long 0x0 4. "TCIF,TCIF" "0,1" bitfld.long 0x0 3. "BTIF,BTIF" "0,1" bitfld.long 0x0 2. "BRTIF,BRTIF" "0,1" bitfld.long 0x0 1. "CTCIF,CTCIF" "0,1" bitfld.long 0x0 0. "TEIF,TEIF" "0,1" wgroup.long 0x804++0x3 line.long 0x0 "MDMA_C31IFCR,MDMA channel 31 interrupt flag clear register" bitfld.long 0x0 4. "CLTCIF,CLTCIF" "0,1" bitfld.long 0x0 3. "CBTIF,CBTIF" "0,1" bitfld.long 0x0 2. "CBRTIF,CBRTIF" "0,1" bitfld.long 0x0 1. "CCTCIF,CCTCIF" "0,1" bitfld.long 0x0 0. "CTEIF,CTEIF" "0,1" rgroup.long 0x808++0x3 line.long 0x0 "MDMA_C31ESR,MDMA channel 31 error status register" bitfld.long 0x0 11. "BSE,BSE" "0,1" bitfld.long 0x0 10. "ASE,ASE" "0,1" bitfld.long 0x0 9. "TEMD,TEMD" "0,1" bitfld.long 0x0 8. "TELD,TELD" "0,1" bitfld.long 0x0 7. "TED,TED" "0,1" hexmask.long.byte 0x0 0.--6. 1. "TEA,TEA" group.long 0x80C++0x1F line.long 0x0 "MDMA_C31CR,This register is used to control the concerned channel." bitfld.long 0x0 16. "SWRQ,SWRQ" "0,1" bitfld.long 0x0 14. "WEX,WEX" "0,1" bitfld.long 0x0 13. "HEX,HEX" "0,1" bitfld.long 0x0 12. "BEX,BEX" "0,1" bitfld.long 0x0 6.--7. "PL,PL" "0,1,2,3" bitfld.long 0x0 5. "TCIE,TCIE" "0,1" bitfld.long 0x0 4. "BTIE,BTIE" "0,1" bitfld.long 0x0 3. "BRTIE,BRTIE" "0,1" bitfld.long 0x0 2. "CTCIE,CTCIE" "0,1" bitfld.long 0x0 1. "TEIE,TEIE" "0,1" newline bitfld.long 0x0 0. "EN,EN" "0,1" line.long 0x4 "MDMA_C31TCR,This register is used to configure the concerned channel. In Linked List mode. at the end of a block (single or last block in repeated block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] +.." bitfld.long 0x4 31. "BWM,BWM" "0,1" bitfld.long 0x4 30. "SWRM,SWRM" "0,1" bitfld.long 0x4 28.--29. "TRGM,TRGM" "0,1,2,3" bitfld.long 0x4 26.--27. "PAM,PAM" "0,1,2,3" bitfld.long 0x4 25. "PKE,PKE" "0,1" hexmask.long.byte 0x4 18.--24. 1. "TLEN,TLEN" bitfld.long 0x4 15.--17. "DBURST,DBURST" "0,1,2,3,4,5,6,7" bitfld.long 0x4 12.--14. "SBURST,SBURST" "0,1,2,3,4,5,6,7" bitfld.long 0x4 10.--11. "DINCOS,DINCOS" "0,1,2,3" bitfld.long 0x4 8.--9. "SINCOS,SINCOS" "0,1,2,3" newline bitfld.long 0x4 6.--7. "DSIZE,DSIZE" "0,1,2,3" bitfld.long 0x4 4.--5. "SSIZE,SSIZE" "0,1,2,3" bitfld.long 0x4 2.--3. "DINC,DINC" "0,1,2,3" bitfld.long 0x4 0.--1. "SINC,SINC" "0,1,2,3" line.long 0x8 "MDMA_C31BNDTR,In Linked List mode. at the end of a block (single or last block in repeated block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] + 0x04)." hexmask.long.word 0x8 20.--31. 1. "BRC,BRC" bitfld.long 0x8 19. "BRDUM,BRDUM" "0,1" bitfld.long 0x8 18. "BRSUM,BRSUM" "0,1" hexmask.long.tbyte 0x8 0.--16. 1. "BNDT,BNDT" line.long 0xC "MDMA_C31SAR,In Linked List mode. at the end of a Block (single or last Block in repeated Block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] + 0x08)." hexmask.long 0xC 0.--31. 1. "SAR,SAR" line.long 0x10 "MDMA_C31DAR,In Linked List mode. at the end of a block (single or last block in repeated block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M" hexmask.long 0x10 0.--31. 1. "DAR,DAR" line.long 0x14 "MDMA_C31BRUR,In Linked List mode. at the end of a block (single or last block in repeated block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] + 0x10)." hexmask.long.word 0x14 16.--31. 1. "DUV,DUV" hexmask.long.word 0x14 0.--15. 1. "SUV,SUV" line.long 0x18 "MDMA_C31LAR,In Linked List mode. at the end of a block (single or last block in repeated block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all.." hexmask.long 0x18 0.--31. 1. "LAR,LAR" line.long 0x1C "MDMA_C31TBR,In Linked List mode. at the end of a block (single or last block in repeated block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] + 0x18)." bitfld.long 0x1C 17. "DBUS,DBUS" "0,1" bitfld.long 0x1C 16. "SBUS,SBUS" "0,1" hexmask.long.byte 0x1C 0.--5. 1. "TSEL,TSEL" group.long 0x830++0x7 line.long 0x0 "MDMA_C31MAR,In Linked List mode. at the end of a block (single or last block in repeated block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] + 0x20)." hexmask.long 0x0 0.--31. 1. "MAR,MAR" line.long 0x4 "MDMA_C31MDR,In Linked List mode. at the end of a block (single or last block in repeated block transfer mode). this register will be loaded from memory (from address given by current LAR[31:0] + 0x24)." hexmask.long 0x4 0.--31. 1. "MDR,MDR" tree.end sif (cpuis("STM32MP151*")||cpuis("STM32MP153*")||cpuis("STM32MP157*")) tree "NVIC (Nested Vectored Interrupt)" base ad:0xE000E100 group.long 0x0++0xF line.long 0x0 "ISER0,Interrupt Set-Enable Register" hexmask.long 0x0 0.--31. 1. "SETENA,SETENA" line.long 0x4 "ISER1,Interrupt Set-Enable Register" hexmask.long 0x4 0.--31. 1. "SETENA,SETENA" line.long 0x8 "ISER2,Interrupt Set-Enable Register" hexmask.long 0x8 0.--31. 1. "SETENA,SETENA" line.long 0xC "ISER3,Interrupt Set-Enable Register" hexmask.long 0xC 0.--31. 1. "SETENA,SETENA" group.long 0x80++0xF line.long 0x0 "ICER0,Interrupt Clear-Enable" hexmask.long 0x0 0.--31. 1. "CLRENA,CLRENA" line.long 0x4 "ICER1,Interrupt Clear-Enable" hexmask.long 0x4 0.--31. 1. "CLRENA,CLRENA" line.long 0x8 "ICER2,Interrupt Clear-Enable" hexmask.long 0x8 0.--31. 1. "CLRENA,CLRENA" line.long 0xC "ICER3,Interrupt Clear-Enable" hexmask.long 0xC 0.--31. 1. "CLRENA,CLRENA" group.long 0x100++0xF line.long 0x0 "ISPR0,Interrupt Set-Pending Register" hexmask.long 0x0 0.--31. 1. "SETPEND,SETPEND" line.long 0x4 "ISPR1,Interrupt Set-Pending Register" hexmask.long 0x4 0.--31. 1. "SETPEND,SETPEND" line.long 0x8 "ISPR2,Interrupt Set-Pending Register" hexmask.long 0x8 0.--31. 1. "SETPEND,SETPEND" line.long 0xC "ISPR3,Interrupt Set-Pending Register" hexmask.long 0xC 0.--31. 1. "SETPEND,SETPEND" group.long 0x180++0xF line.long 0x0 "ICPR0,Interrupt Clear-Pending" hexmask.long 0x0 0.--31. 1. "CLRPEND,CLRPEND" line.long 0x4 "ICPR1,Interrupt Clear-Pending" hexmask.long 0x4 0.--31. 1. "CLRPEND,CLRPEND" line.long 0x8 "ICPR2,Interrupt Clear-Pending" hexmask.long 0x8 0.--31. 1. "CLRPEND,CLRPEND" line.long 0xC "ICPR3,Interrupt Clear-Pending" hexmask.long 0xC 0.--31. 1. "CLRPEND,CLRPEND" rgroup.long 0x200++0xF line.long 0x0 "IABR0,Interrupt Active Bit Register" hexmask.long 0x0 0.--31. 1. "ACTIVE,ACTIVE" line.long 0x4 "IABR1,Interrupt Active Bit Register" hexmask.long 0x4 0.--31. 1. "ACTIVE,ACTIVE" line.long 0x8 "IABR2,Interrupt Active Bit Register" hexmask.long 0x8 0.--31. 1. "ACTIVE,ACTIVE" line.long 0xC "IABR3,Interrupt Active Bit Register" hexmask.long 0xC 0.--31. 1. "ACTIVE,ACTIVE" group.long 0x300++0x9B line.long 0x0 "IPR0,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. "IPR_N3,IPR_N3" hexmask.long.byte 0x0 16.--23. 1. "IPR_N2,IPR_N2" hexmask.long.byte 0x0 8.--15. 1. "IPR_N1,IPR_N1" hexmask.long.byte 0x0 0.--7. 1. "IPR_N0,IPR_N0" line.long 0x4 "IPR1,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. "IPR_N3,IPR_N3" hexmask.long.byte 0x4 16.--23. 1. "IPR_N2,IPR_N2" hexmask.long.byte 0x4 8.--15. 1. "IPR_N1,IPR_N1" hexmask.long.byte 0x4 0.--7. 1. "IPR_N0,IPR_N0" line.long 0x8 "IPR2,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. "IPR_N3,IPR_N3" hexmask.long.byte 0x8 16.--23. 1. "IPR_N2,IPR_N2" hexmask.long.byte 0x8 8.--15. 1. "IPR_N1,IPR_N1" hexmask.long.byte 0x8 0.--7. 1. "IPR_N0,IPR_N0" line.long 0xC "IPR3,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. "IPR_N3,IPR_N3" hexmask.long.byte 0xC 16.--23. 1. "IPR_N2,IPR_N2" hexmask.long.byte 0xC 8.--15. 1. "IPR_N1,IPR_N1" hexmask.long.byte 0xC 0.--7. 1. "IPR_N0,IPR_N0" line.long 0x10 "IPR4,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. "IPR_N3,IPR_N3" hexmask.long.byte 0x10 16.--23. 1. "IPR_N2,IPR_N2" hexmask.long.byte 0x10 8.--15. 1. "IPR_N1,IPR_N1" hexmask.long.byte 0x10 0.--7. 1. "IPR_N0,IPR_N0" line.long 0x14 "IPR5,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. "IPR_N3,IPR_N3" hexmask.long.byte 0x14 16.--23. 1. "IPR_N2,IPR_N2" hexmask.long.byte 0x14 8.--15. 1. "IPR_N1,IPR_N1" hexmask.long.byte 0x14 0.--7. 1. "IPR_N0,IPR_N0" line.long 0x18 "IPR6,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. "IPR_N3,IPR_N3" hexmask.long.byte 0x18 16.--23. 1. "IPR_N2,IPR_N2" hexmask.long.byte 0x18 8.--15. 1. "IPR_N1,IPR_N1" hexmask.long.byte 0x18 0.--7. 1. "IPR_N0,IPR_N0" line.long 0x1C "IPR7,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. "IPR_N3,IPR_N3" hexmask.long.byte 0x1C 16.--23. 1. "IPR_N2,IPR_N2" hexmask.long.byte 0x1C 8.--15. 1. "IPR_N1,IPR_N1" hexmask.long.byte 0x1C 0.--7. 1. "IPR_N0,IPR_N0" line.long 0x20 "IPR8,Interrupt Priority Register" hexmask.long.byte 0x20 24.--31. 1. "IPR_N3,IPR_N3" hexmask.long.byte 0x20 16.--23. 1. "IPR_N2,IPR_N2" hexmask.long.byte 0x20 8.--15. 1. "IPR_N1,IPR_N1" hexmask.long.byte 0x20 0.--7. 1. "IPR_N0,IPR_N0" line.long 0x24 "IPR9,Interrupt Priority Register" hexmask.long.byte 0x24 24.--31. 1. "IPR_N3,IPR_N3" hexmask.long.byte 0x24 16.--23. 1. "IPR_N2,IPR_N2" hexmask.long.byte 0x24 8.--15. 1. "IPR_N1,IPR_N1" hexmask.long.byte 0x24 0.--7. 1. "IPR_N0,IPR_N0" line.long 0x28 "IPR10,Interrupt Priority Register" hexmask.long.byte 0x28 24.--31. 1. "IPR_N3,IPR_N3" hexmask.long.byte 0x28 16.--23. 1. "IPR_N2,IPR_N2" hexmask.long.byte 0x28 8.--15. 1. "IPR_N1,IPR_N1" hexmask.long.byte 0x28 0.--7. 1. "IPR_N0,IPR_N0" line.long 0x2C "IPR11,Interrupt Priority Register" hexmask.long.byte 0x2C 24.--31. 1. "IPR_N3,IPR_N3" hexmask.long.byte 0x2C 16.--23. 1. "IPR_N2,IPR_N2" hexmask.long.byte 0x2C 8.--15. 1. "IPR_N1,IPR_N1" hexmask.long.byte 0x2C 0.--7. 1. "IPR_N0,IPR_N0" line.long 0x30 "IPR12,Interrupt Priority Register" hexmask.long.byte 0x30 24.--31. 1. "IPR_N3,IPR_N3" hexmask.long.byte 0x30 16.--23. 1. "IPR_N2,IPR_N2" hexmask.long.byte 0x30 8.--15. 1. "IPR_N1,IPR_N1" hexmask.long.byte 0x30 0.--7. 1. "IPR_N0,IPR_N0" line.long 0x34 "IPR13,Interrupt Priority Register" hexmask.long.byte 0x34 24.--31. 1. "IPR_N3,IPR_N3" hexmask.long.byte 0x34 16.--23. 1. "IPR_N2,IPR_N2" hexmask.long.byte 0x34 8.--15. 1. "IPR_N1,IPR_N1" hexmask.long.byte 0x34 0.--7. 1. "IPR_N0,IPR_N0" line.long 0x38 "IPR14,Interrupt Priority Register" hexmask.long.byte 0x38 24.--31. 1. "IPR_N3,IPR_N3" hexmask.long.byte 0x38 16.--23. 1. "IPR_N2,IPR_N2" hexmask.long.byte 0x38 8.--15. 1. "IPR_N1,IPR_N1" hexmask.long.byte 0x38 0.--7. 1. "IPR_N0,IPR_N0" line.long 0x3C "IPR15,Interrupt Priority Register" hexmask.long.byte 0x3C 24.--31. 1. "IPR_N3,IPR_N3" hexmask.long.byte 0x3C 16.--23. 1. "IPR_N2,IPR_N2" hexmask.long.byte 0x3C 8.--15. 1. "IPR_N1,IPR_N1" hexmask.long.byte 0x3C 0.--7. 1. "IPR_N0,IPR_N0" line.long 0x40 "IPR16,Interrupt Priority Register" hexmask.long.byte 0x40 24.--31. 1. "IPR_N3,IPR_N3" hexmask.long.byte 0x40 16.--23. 1. "IPR_N2,IPR_N2" hexmask.long.byte 0x40 8.--15. 1. "IPR_N1,IPR_N1" hexmask.long.byte 0x40 0.--7. 1. "IPR_N0,IPR_N0" line.long 0x44 "IPR17,Interrupt Priority Register" hexmask.long.byte 0x44 24.--31. 1. "IPR_N3,IPR_N3" hexmask.long.byte 0x44 16.--23. 1. "IPR_N2,IPR_N2" hexmask.long.byte 0x44 8.--15. 1. "IPR_N1,IPR_N1" hexmask.long.byte 0x44 0.--7. 1. "IPR_N0,IPR_N0" line.long 0x48 "IPR18,Interrupt Priority Register" hexmask.long.byte 0x48 24.--31. 1. "IPR_N3,IPR_N3" hexmask.long.byte 0x48 16.--23. 1. "IPR_N2,IPR_N2" hexmask.long.byte 0x48 8.--15. 1. "IPR_N1,IPR_N1" hexmask.long.byte 0x48 0.--7. 1. "IPR_N0,IPR_N0" line.long 0x4C "IPR19,Interrupt Priority Register" hexmask.long.byte 0x4C 24.--31. 1. "IPR_N3,IPR_N3" hexmask.long.byte 0x4C 16.--23. 1. "IPR_N2,IPR_N2" hexmask.long.byte 0x4C 8.--15. 1. "IPR_N1,IPR_N1" hexmask.long.byte 0x4C 0.--7. 1. "IPR_N0,IPR_N0" line.long 0x50 "IPR20,Interrupt Priority Register" hexmask.long.byte 0x50 24.--31. 1. "IPR_N3,IPR_N3" hexmask.long.byte 0x50 16.--23. 1. "IPR_N2,IPR_N2" hexmask.long.byte 0x50 8.--15. 1. "IPR_N1,IPR_N1" hexmask.long.byte 0x50 0.--7. 1. "IPR_N0,IPR_N0" line.long 0x54 "IPR21,Interrupt Priority Register" hexmask.long.byte 0x54 24.--31. 1. "IPR_N3,IPR_N3" hexmask.long.byte 0x54 16.--23. 1. "IPR_N2,IPR_N2" hexmask.long.byte 0x54 8.--15. 1. "IPR_N1,IPR_N1" hexmask.long.byte 0x54 0.--7. 1. "IPR_N0,IPR_N0" line.long 0x58 "IPR22,Interrupt Priority Register" hexmask.long.byte 0x58 24.--31. 1. "IPR_N3,IPR_N3" hexmask.long.byte 0x58 16.--23. 1. "IPR_N2,IPR_N2" hexmask.long.byte 0x58 8.--15. 1. "IPR_N1,IPR_N1" hexmask.long.byte 0x58 0.--7. 1. "IPR_N0,IPR_N0" line.long 0x5C "IPR23,Interrupt Priority Register" hexmask.long.byte 0x5C 24.--31. 1. "IPR_N3,IPR_N3" hexmask.long.byte 0x5C 16.--23. 1. "IPR_N2,IPR_N2" hexmask.long.byte 0x5C 8.--15. 1. "IPR_N1,IPR_N1" hexmask.long.byte 0x5C 0.--7. 1. "IPR_N0,IPR_N0" line.long 0x60 "IPR24,Interrupt Priority Register" hexmask.long.byte 0x60 24.--31. 1. "IPR_N3,IPR_N3" hexmask.long.byte 0x60 16.--23. 1. "IPR_N2,IPR_N2" hexmask.long.byte 0x60 8.--15. 1. "IPR_N1,IPR_N1" hexmask.long.byte 0x60 0.--7. 1. "IPR_N0,IPR_N0" line.long 0x64 "IPR25,Interrupt Priority Register" hexmask.long.byte 0x64 24.--31. 1. "IPR_N3,IPR_N3" hexmask.long.byte 0x64 16.--23. 1. "IPR_N2,IPR_N2" hexmask.long.byte 0x64 8.--15. 1. "IPR_N1,IPR_N1" hexmask.long.byte 0x64 0.--7. 1. "IPR_N0,IPR_N0" line.long 0x68 "IPR26,Interrupt Priority Register" hexmask.long.byte 0x68 24.--31. 1. "IPR_N3,IPR_N3" hexmask.long.byte 0x68 16.--23. 1. "IPR_N2,IPR_N2" hexmask.long.byte 0x68 8.--15. 1. "IPR_N1,IPR_N1" hexmask.long.byte 0x68 0.--7. 1. "IPR_N0,IPR_N0" line.long 0x6C "IPR27,Interrupt Priority Register" hexmask.long.byte 0x6C 24.--31. 1. "IPR_N3,IPR_N3" hexmask.long.byte 0x6C 16.--23. 1. "IPR_N2,IPR_N2" hexmask.long.byte 0x6C 8.--15. 1. "IPR_N1,IPR_N1" hexmask.long.byte 0x6C 0.--7. 1. "IPR_N0,IPR_N0" line.long 0x70 "IPR28,Interrupt Priority Register" hexmask.long.byte 0x70 24.--31. 1. "IPR_N3,IPR_N3" hexmask.long.byte 0x70 16.--23. 1. "IPR_N2,IPR_N2" hexmask.long.byte 0x70 8.--15. 1. "IPR_N1,IPR_N1" hexmask.long.byte 0x70 0.--7. 1. "IPR_N0,IPR_N0" line.long 0x74 "IPR29,Interrupt Priority Register" hexmask.long.byte 0x74 24.--31. 1. "IPR_N3,IPR_N3" hexmask.long.byte 0x74 16.--23. 1. "IPR_N2,IPR_N2" hexmask.long.byte 0x74 8.--15. 1. "IPR_N1,IPR_N1" hexmask.long.byte 0x74 0.--7. 1. "IPR_N0,IPR_N0" line.long 0x78 "IPR30,Interrupt Priority Register" hexmask.long.byte 0x78 24.--31. 1. "IPR_N3,IPR_N3" hexmask.long.byte 0x78 16.--23. 1. "IPR_N2,IPR_N2" hexmask.long.byte 0x78 8.--15. 1. "IPR_N1,IPR_N1" hexmask.long.byte 0x78 0.--7. 1. "IPR_N0,IPR_N0" line.long 0x7C "IPR31,Interrupt Priority Register" hexmask.long.byte 0x7C 24.--31. 1. "IPR_N3,IPR_N3" hexmask.long.byte 0x7C 16.--23. 1. "IPR_N2,IPR_N2" hexmask.long.byte 0x7C 8.--15. 1. "IPR_N1,IPR_N1" hexmask.long.byte 0x7C 0.--7. 1. "IPR_N0,IPR_N0" line.long 0x80 "IPR32,Interrupt Priority Register" hexmask.long.byte 0x80 24.--31. 1. "IPR_N3,IPR_N3" hexmask.long.byte 0x80 16.--23. 1. "IPR_N2,IPR_N2" hexmask.long.byte 0x80 8.--15. 1. "IPR_N1,IPR_N1" hexmask.long.byte 0x80 0.--7. 1. "IPR_N0,IPR_N0" line.long 0x84 "IPR33,Interrupt Priority Register" hexmask.long.byte 0x84 24.--31. 1. "IPR_N3,IPR_N3" hexmask.long.byte 0x84 16.--23. 1. "IPR_N2,IPR_N2" hexmask.long.byte 0x84 8.--15. 1. "IPR_N1,IPR_N1" hexmask.long.byte 0x84 0.--7. 1. "IPR_N0,IPR_N0" line.long 0x88 "IPR34,Interrupt Priority Register" hexmask.long.byte 0x88 24.--31. 1. "IPR_N3,IPR_N3" hexmask.long.byte 0x88 16.--23. 1. "IPR_N2,IPR_N2" hexmask.long.byte 0x88 8.--15. 1. "IPR_N1,IPR_N1" hexmask.long.byte 0x88 0.--7. 1. "IPR_N0,IPR_N0" line.long 0x8C "IPR35,Interrupt Priority Register" hexmask.long.byte 0x8C 24.--31. 1. "IPR_N3,IPR_N3" hexmask.long.byte 0x8C 16.--23. 1. "IPR_N2,IPR_N2" hexmask.long.byte 0x8C 8.--15. 1. "IPR_N1,IPR_N1" hexmask.long.byte 0x8C 0.--7. 1. "IPR_N0,IPR_N0" line.long 0x90 "IPR36,Interrupt Priority Register" hexmask.long.byte 0x90 24.--31. 1. "IPR_N3,IPR_N3" hexmask.long.byte 0x90 16.--23. 1. "IPR_N2,IPR_N2" hexmask.long.byte 0x90 8.--15. 1. "IPR_N1,IPR_N1" hexmask.long.byte 0x90 0.--7. 1. "IPR_N0,IPR_N0" line.long 0x94 "IPR37,Interrupt Priority Register" hexmask.long.byte 0x94 24.--31. 1. "IPR_N3,IPR_N3" hexmask.long.byte 0x94 16.--23. 1. "IPR_N2,IPR_N2" hexmask.long.byte 0x94 8.--15. 1. "IPR_N1,IPR_N1" hexmask.long.byte 0x94 0.--7. 1. "IPR_N0,IPR_N0" line.long 0x98 "IPR38,Interrupt Priority Register" hexmask.long.byte 0x98 24.--31. 1. "IPR_N3,IPR_N3" hexmask.long.byte 0x98 16.--23. 1. "IPR_N2,IPR_N2" hexmask.long.byte 0x98 8.--15. 1. "IPR_N1,IPR_N1" hexmask.long.byte 0x98 0.--7. 1. "IPR_N0,IPR_N0" group.long 0x10++0x3 line.long 0x0 "ISER4,Interrupt Set-Enable Register" group.long 0x90++0x3 line.long 0x0 "ICER4,Interrupt Clear-Enable" group.long 0x110++0x3 line.long 0x0 "ISPR4,Interrupt Set-Pending Register" group.long 0x1C4++0x3 line.long 0x0 "ICPR4,Interrupt Clear-Pending" group.long 0x210++0x3 line.long 0x0 "IABR4,Interrupt Active Bit Register" tree.end endif tree "OTG (On-the-Go High-Speed)" base ad:0x49000000 group.long 0x0++0x2F line.long 0x0 "OTG_GOTGCTL,OTG control and status register" sif (cpuis("STM32MP13*")) rbitfld.long 0x0 21. "CURMOD,Current mode of operation" "0: Device mode,1: Host mode" bitfld.long 0x0 20. "OTGVER,OTG version" "0: OTG Version 1.3. OTG1.3 is obsolete for new..,1: OTG Version 2.0. In this version the core.." newline rbitfld.long 0x0 19. "BSVLD,B-session valid" "0: B-session is not valid.,1: B-session is valid." rbitfld.long 0x0 18. "ASVLD,A-session valid" "0: A-session is not valid,1: A-session is valid" newline rbitfld.long 0x0 17. "DBCT,Long/short debounce time" "0: Long debounce time used for physical connections..,1: Short debounce time used for soft connections.." rbitfld.long 0x0 16. "CIDSTS,Connector ID status" "0: The OTG controller is in A-device mode,1: The OTG controller is in B-device mode" newline bitfld.long 0x0 12. "EHEN,Embedded host enable" "0: OTG A device state machine is selected,1: Embedded host state machine is selected" bitfld.long 0x0 11. "DHNPEN,Device HNP enabled" "0: HNP is not enabled in the application,1: HNP is enabled in the application" newline bitfld.long 0x0 10. "HSHNPEN,host set HNP enable" "0: Host Set HNP is not enabled,1: Host Set HNP is enabled" bitfld.long 0x0 9. "HNPRQ,HNP request" "0: No HNP request,1: HNP request" newline rbitfld.long 0x0 8. "HNGSCS,Host negotiation success" "0: Host negotiation failure,1: Host negotiation success" bitfld.long 0x0 7. "BVALOVAL,B-peripheral session valid override value." "0: Bvalid value is '0' when BVALOEN = 1,1: Bvalid value is '1' when BVALOEN = 1" newline bitfld.long 0x0 6. "BVALOEN,B-peripheral session valid override enable." "0: Override is disabled and Bvalid signal from the..,1: Internally Bvalid received from the PHY is.." bitfld.long 0x0 5. "AVALOVAL,A-peripheral session valid override value." "0: Avalid value is '0' when AVALOEN = 1,1: Avalid value is '1' when AVALOEN = 1" newline bitfld.long 0x0 4. "AVALOEN,A-peripheral session valid override enable." "0: Override is disabled and Avalid signal from the..,1: Internally Avalid received from the PHY is.." bitfld.long 0x0 3. "VBVALOVAL,VBUS valid override value." "0: vbusvalid value is '0' when VBVALOEN = 1,1: vbusvalid value is '1' when VBVALOEN = 1" newline bitfld.long 0x0 2. "VBVALOEN,VBUS valid override enable." "0: Override is disabled and vbusvalid signal from..,1: Internally vbusvalid received from the PHY is.." bitfld.long 0x0 1. "SRQ,Session request" "0: No session request,1: Session request" newline rbitfld.long 0x0 0. "SRQSCS,Session request success" "0: Session request failure,1: Session request success" endif sif (cpuis("STM32MP151*")) rbitfld.long 0x0 21. "CURMOD,CURMOD" "0,1" newline bitfld.long 0x0 20. "OTGVER,OTGVER" "0,1" rbitfld.long 0x0 19. "BSVLD,BSVLD" "0,1" newline rbitfld.long 0x0 18. "ASVLD,ASVLD" "0,1" rbitfld.long 0x0 17. "DBCT,DBCT" "0,1" newline rbitfld.long 0x0 16. "CIDSTS,CIDSTS" "0,1" endif sif (cpuis("STM32MP153*")) rbitfld.long 0x0 21. "CURMOD,CURMOD" "0,1" newline bitfld.long 0x0 20. "OTGVER,OTGVER" "0,1" rbitfld.long 0x0 19. "BSVLD,BSVLD" "0,1" newline rbitfld.long 0x0 18. "ASVLD,ASVLD" "0,1" rbitfld.long 0x0 17. "DBCT,DBCT" "0,1" newline rbitfld.long 0x0 16. "CIDSTS,CIDSTS" "0,1" endif sif (cpuis("STM32MP157*")) rbitfld.long 0x0 21. "CURMOD,CURMOD" "0,1" newline bitfld.long 0x0 20. "OTGVER,OTGVER" "0,1" rbitfld.long 0x0 19. "BSVLD,BSVLD" "0,1" newline rbitfld.long 0x0 18. "ASVLD,ASVLD" "0,1" rbitfld.long 0x0 17. "DBCT,DBCT" "0,1" newline rbitfld.long 0x0 16. "CIDSTS,CIDSTS" "0,1" endif sif (cpuis("STM32MP151*")) bitfld.long 0x0 12. "EHEN,EHEN" "0,1" newline bitfld.long 0x0 11. "DHNPEN,DHNPEN" "0,1" bitfld.long 0x0 10. "HSHNPEN,HSHNPEN" "0,1" newline bitfld.long 0x0 9. "HNPRQ,HNPRQ" "0,1" rbitfld.long 0x0 8. "HNGSCS,HNGSCS" "0,1" newline bitfld.long 0x0 7. "BVALOVAL,BVALOVAL" "0,1" bitfld.long 0x0 6. "BVALOEN,BVALOEN" "0,1" newline bitfld.long 0x0 5. "AVALOVAL,AVALOVAL" "0,1" bitfld.long 0x0 4. "AVALOEN,AVALOEN" "0,1" newline bitfld.long 0x0 3. "VBVALOVAL,VBVALOVAL" "0,1" bitfld.long 0x0 2. "VBVALOEN,VBVALOEN" "0,1" newline bitfld.long 0x0 1. "SRQ,SRQ" "0,1" endif sif (cpuis("STM32MP153*")) bitfld.long 0x0 12. "EHEN,EHEN" "0,1" newline bitfld.long 0x0 11. "DHNPEN,DHNPEN" "0,1" bitfld.long 0x0 10. "HSHNPEN,HSHNPEN" "0,1" newline bitfld.long 0x0 9. "HNPRQ,HNPRQ" "0,1" rbitfld.long 0x0 8. "HNGSCS,HNGSCS" "0,1" newline bitfld.long 0x0 7. "BVALOVAL,BVALOVAL" "0,1" bitfld.long 0x0 6. "BVALOEN,BVALOEN" "0,1" newline bitfld.long 0x0 5. "AVALOVAL,AVALOVAL" "0,1" bitfld.long 0x0 4. "AVALOEN,AVALOEN" "0,1" newline bitfld.long 0x0 3. "VBVALOVAL,VBVALOVAL" "0,1" bitfld.long 0x0 2. "VBVALOEN,VBVALOEN" "0,1" newline bitfld.long 0x0 1. "SRQ,SRQ" "0,1" rbitfld.long 0x0 0. "SRQSCS,SRQSCS" "0,1" newline endif sif (cpuis("STM32MP157*")) bitfld.long 0x0 12. "EHEN,EHEN" "0,1" bitfld.long 0x0 11. "DHNPEN,DHNPEN" "0,1" newline bitfld.long 0x0 10. "HSHNPEN,HSHNPEN" "0,1" bitfld.long 0x0 9. "HNPRQ,HNPRQ" "0,1" newline rbitfld.long 0x0 8. "HNGSCS,HNGSCS" "0,1" bitfld.long 0x0 7. "BVALOVAL,BVALOVAL" "0,1" newline bitfld.long 0x0 6. "BVALOEN,BVALOEN" "0,1" bitfld.long 0x0 5. "AVALOVAL,AVALOVAL" "0,1" newline bitfld.long 0x0 4. "AVALOEN,AVALOEN" "0,1" bitfld.long 0x0 3. "VBVALOVAL,VBVALOVAL" "0,1" newline bitfld.long 0x0 2. "VBVALOEN,VBVALOEN" "0,1" bitfld.long 0x0 1. "SRQ,SRQ" "0,1" newline rbitfld.long 0x0 0. "SRQSCS,SRQSCS" "0,1" endif line.long 0x4 "OTG_GOTGINT,OTG interrupt register" sif (cpuis("STM32MP151*")) bitfld.long 0x4 20. "IDCHNG,IDCHNG" "0,1" endif sif (cpuis("STM32MP153*")) bitfld.long 0x4 20. "IDCHNG,IDCHNG" "0,1" newline endif sif (cpuis("STM32MP157*")) bitfld.long 0x4 20. "IDCHNG,IDCHNG" "0,1" endif bitfld.long 0x4 19. "DBCDNE,Debounce done" "0,1" newline bitfld.long 0x4 18. "ADTOCHG,A-device timeout change" "0,1" bitfld.long 0x4 17. "HNGDET,Host negotiation detected" "0,1" newline bitfld.long 0x4 9. "HNSSCHG,Host negotiation success status change" "0,1" bitfld.long 0x4 8. "SRSSCHG,Session request success status change" "0,1" newline bitfld.long 0x4 2. "SEDET,Session end detected" "0,1" line.long 0x8 "OTG_GAHBCFG,OTG AHB configuration register" sif (cpuis("STM32MP13*")) bitfld.long 0x8 8. "PTXFELVL,Periodic Tx FIFO empty level" "0: PTXFE (in OTG_GINTSTS) interrupt indicates that..,1: PTXFE (in OTG_GINTSTS) interrupt indicates that.." bitfld.long 0x8 7. "TXFELVL,Tx FIFO empty level" "0: The NPTXFE (in OTG_GINTSTS) interrupt indicates..,1: The NPTXFE (in OTG_GINTSTS) interrupt indicates.." newline bitfld.long 0x8 5. "DMAEN,DMA enabled" "0: The core operates in slave mode,1: The core operates in DMA mode" bitfld.long 0x8 0. "GINTMSK,Global interrupt mask" "0: Mask the interrupt assertion to the application.,1: Unmask the interrupt assertion to the application." newline endif sif (cpuis("STM32MP151*")) bitfld.long 0x8 8. "PTXFELVL,PTXFELVL" "0,1" bitfld.long 0x8 7. "TXFELVL,TXFELVL" "0,1" newline endif sif (cpuis("STM32MP153*")) bitfld.long 0x8 8. "PTXFELVL,PTXFELVL" "0,1" bitfld.long 0x8 7. "TXFELVL,TXFELVL" "0,1" newline endif sif (cpuis("STM32MP157*")) bitfld.long 0x8 8. "PTXFELVL,PTXFELVL" "0,1" bitfld.long 0x8 7. "TXFELVL,TXFELVL" "0,1" newline endif sif (cpuis("STM32MP151*")) bitfld.long 0x8 5. "DMAEN,DMAEN" "0,1" endif sif (cpuis("STM32MP153*")) bitfld.long 0x8 5. "DMAEN,DMAEN" "0,1" newline endif sif (cpuis("STM32MP157*")) bitfld.long 0x8 5. "DMAEN,DMAEN" "0,1" endif hexmask.long.byte 0x8 1.--4. 1. "HBSTLEN,Burst length/type" newline sif (cpuis("STM32MP153*")) bitfld.long 0x8 0. "GINTMSK,GINTMSK" "0,1" endif sif (cpuis("STM32MP157*")) bitfld.long 0x8 0. "GINTMSK,GINTMSK" "0,1" endif line.long 0xC "OTG_GUSBCFG,OTG USB configuration register" sif (cpuis("STM32MP13*")) bitfld.long 0xC 30. "FDMOD,Force device mode" "0: Normal mode,1: Force device mode" bitfld.long 0xC 29. "FHMOD,Force host mode" "0: Normal mode,1: Force host mode" newline bitfld.long 0xC 22. "TSDPS,TermSel DLine pulsing selection" "0: Data line pulsing using utmi_txvalid (default),1: Data line pulsing using utmi_termsel" bitfld.long 0xC 15. "PHYLPC,PHY Low-power clock select" "0: 480 MHz internal PLL clock,1: 48 MHz external clock" newline bitfld.long 0xC 9. "HNPCAP,HNP-capable" "0: HNP capability is not enabled.,1: HNP capability is enabled." bitfld.long 0xC 8. "SRPCAP,SRP-capable" "0: SRP capability is not enabled.,1: SRP capability is enabled." newline endif sif (cpuis("STM32MP151*")) bitfld.long 0xC 30. "FDMOD,FDMOD" "0,1" bitfld.long 0xC 29. "FHMOD,FHMOD" "0,1" newline endif sif (cpuis("STM32MP153*")) bitfld.long 0xC 30. "FDMOD,FDMOD" "0,1" bitfld.long 0xC 29. "FHMOD,FHMOD" "0,1" newline endif sif (cpuis("STM32MP157*")) bitfld.long 0xC 30. "FDMOD,FDMOD" "0,1" bitfld.long 0xC 29. "FHMOD,FHMOD" "0,1" newline endif sif (cpuis("STM32MP151*")) bitfld.long 0xC 22. "TSDPS,TSDPS" "0,1" endif sif (cpuis("STM32MP153*")) bitfld.long 0xC 22. "TSDPS,TSDPS" "0,1" newline endif sif (cpuis("STM32MP157*")) bitfld.long 0xC 22. "TSDPS,TSDPS" "0,1" endif sif (cpuis("STM32MP151*")) bitfld.long 0xC 15. "PHYLPC,PHYLPC" "0,1" newline endif sif (cpuis("STM32MP153*")) bitfld.long 0xC 15. "PHYLPC,PHYLPC" "0,1" endif sif (cpuis("STM32MP157*")) bitfld.long 0xC 15. "PHYLPC,PHYLPC" "0,1" newline endif hexmask.long.byte 0xC 10.--13. 1. "TRDT,USB turnaround time" sif (cpuis("STM32MP151*")) bitfld.long 0xC 9. "HNPCAP,HNPCAP" "0,1" newline bitfld.long 0xC 8. "SRPCAP,SRPCAP" "0,1" endif sif (cpuis("STM32MP153*")) bitfld.long 0xC 9. "HNPCAP,HNPCAP" "0,1" newline bitfld.long 0xC 8. "SRPCAP,SRPCAP" "0,1" endif sif (cpuis("STM32MP157*")) bitfld.long 0xC 9. "HNPCAP,HNPCAP" "0,1" newline bitfld.long 0xC 8. "SRPCAP,SRPCAP" "0,1" endif sif (cpuis("STM32MP151*")) bitfld.long 0xC 6. "PHYSEL,PHYSEL" "0,1" newline endif sif (cpuis("STM32MP153*")) bitfld.long 0xC 6. "PHYSEL,PHYSEL" "0,1" endif sif (cpuis("STM32MP157*")) bitfld.long 0xC 6. "PHYSEL,PHYSEL" "0,1" newline endif bitfld.long 0xC 0.--2. "TOCAL,FS timeout calibration" "0,1,2,3,4,5,6,7" line.long 0x10 "OTG_GRSTCTL,OTG reset register" rbitfld.long 0x10 31. "AHBIDL,AHB master idle" "0,1" rbitfld.long 0x10 30. "DMAREQ,DMA request signal enabled" "0,1" newline sif (cpuis("STM32MP13*")) hexmask.long.byte 0x10 6.--10. 1. "TXFNUM,Tx FIFO number" bitfld.long 0x10 2. "FCRST,Host frame counter reset" "0,1" newline endif sif (cpuis("STM32MP151*")) hexmask.long.byte 0x10 6.--10. 1. "TXFNUM,TXFNUM" endif sif (cpuis("STM32MP153*")) hexmask.long.byte 0x10 6.--10. 1. "TXFNUM,TXFNUM" newline endif sif (cpuis("STM32MP157*")) hexmask.long.byte 0x10 6.--10. 1. "TXFNUM,TXFNUM" endif bitfld.long 0x10 5. "TXFFLSH,Tx FIFO flush" "0,1" newline bitfld.long 0x10 4. "RXFFLSH,Rx FIFO flush" "0,1" bitfld.long 0x10 1. "PSRST,Partial soft reset" "0,1" newline bitfld.long 0x10 0. "CSRST,Core soft reset" "0,1" line.long 0x14 "OTG_GINTSTS,OTG core interrupt register" bitfld.long 0x14 31. "WKUPINT,Resume/remote wakeup detected interrupt" "0,1" bitfld.long 0x14 30. "SRQINT,Session request/new session detected interrupt" "0,1" newline bitfld.long 0x14 29. "DISCINT,Disconnect detected interrupt" "0,1" bitfld.long 0x14 28. "CIDSCHG,Connector ID status change" "0,1" newline sif (cpuis("STM32MP13*")) bitfld.long 0x14 27. "LPMINT,LPM interrupt" "0,1" bitfld.long 0x14 23. "RSTDET,Reset detected interrupt" "0,1" newline rbitfld.long 0x14 0. "CMOD,Current mode of operation" "0: Device mode,1: Host mode" endif rbitfld.long 0x14 26. "PTXFE,Periodic Tx FIFO empty" "0,1" newline rbitfld.long 0x14 25. "HCINT,Host channels interrupt" "0,1" rbitfld.long 0x14 24. "HPRTINT,Host port interrupt" "0,1" newline bitfld.long 0x14 22. "DATAFSUSP,Data fetch suspended" "0,1" bitfld.long 0x14 21. "IPXFR,Incomplete periodic transfer" "0,1" newline bitfld.long 0x14 20. "IISOIXFR,Incomplete isochronous IN transfer" "0,1" rbitfld.long 0x14 19. "OEPINT,OUT endpoint interrupt" "0,1" newline rbitfld.long 0x14 18. "IEPINT,IN endpoint interrupt" "0,1" bitfld.long 0x14 15. "EOPF,End of periodic frame interrupt" "0,1" newline bitfld.long 0x14 14. "ISOODRP,Isochronous OUT packet dropped interrupt" "0,1" bitfld.long 0x14 13. "ENUMDNE,Enumeration done" "0,1" newline bitfld.long 0x14 12. "USBRST,USB reset" "0,1" bitfld.long 0x14 11. "USBSUSP,USB suspend" "0,1" newline bitfld.long 0x14 10. "ESUSP,Early suspend" "0,1" rbitfld.long 0x14 7. "GONAKEFF,Global OUT NAK effective" "0,1" newline rbitfld.long 0x14 6. "GINAKEFF,Global IN non-periodic NAK effective" "0,1" rbitfld.long 0x14 5. "NPTXFE,Non-periodic Tx FIFO empty" "0,1" newline rbitfld.long 0x14 4. "RXFLVL,Rx FIFO non-empty" "0,1" bitfld.long 0x14 3. "SOF,Start of frame" "0,1" newline rbitfld.long 0x14 2. "OTGINT,OTG interrupt" "0,1" bitfld.long 0x14 1. "MMIS,Mode mismatch interrupt" "0,1" newline sif (cpuis("STM32MP153*")) rbitfld.long 0x14 0. "CMOD,CMOD" "0,1" endif sif (cpuis("STM32MP157*")) rbitfld.long 0x14 0. "CMOD,CMOD" "0,1" endif line.long 0x18 "OTG_GINTMSK,OTG interrupt mask register" sif (cpuis("STM32MP13*")) bitfld.long 0x18 31. "WUIM,Resume/remote wakeup detected interrupt mask" "0: Masked interrupt,1: Unmasked interrupt" bitfld.long 0x18 30. "SRQIM,Session request/new session detected interrupt mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x18 29. "DISCINT,Disconnect detected interrupt mask" "0: Masked interrupt,1: Unmasked interrupt" bitfld.long 0x18 28. "CIDSCHGM,Connector ID status change mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x18 27. "LPMINTM,LPM interrupt mask" "0: Masked interrupt,1: Unmasked interrupt" bitfld.long 0x18 26. "PTXFEM,Periodic Tx FIFO empty mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x18 25. "HCIM,Host channels interrupt mask" "0: Masked interrupt,1: Unmasked interrupt" rbitfld.long 0x18 24. "PRTIM,Host port interrupt mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x18 23. "RSTDETM,Reset detected interrupt mask" "0: Masked interrupt,1: Unmasked interrupt" bitfld.long 0x18 22. "FSUSPM,Data fetch suspended mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x18 21. "IPXFRM,Incomplete periodic transfer mask" "0: Masked interrupt,1: Unmasked interrupt" bitfld.long 0x18 20. "IISOIXFRM,Incomplete isochronous IN transfer mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x18 19. "OEPINT,OUT endpoints interrupt mask" "0: Masked interrupt,1: Unmasked interrupt" bitfld.long 0x18 18. "IEPINT,IN endpoints interrupt mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x18 15. "EOPFM,End of periodic frame interrupt mask" "0: Masked interrupt,1: Unmasked interrupt" bitfld.long 0x18 14. "ISOODRPM,Isochronous OUT packet dropped interrupt mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x18 13. "ENUMDNEM,Enumeration done mask" "0: Masked interrupt,1: Unmasked interrupt" bitfld.long 0x18 12. "USBRST,USB reset mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x18 11. "USBSUSPM,USB suspend mask" "0: Masked interrupt,1: Unmasked interrupt" bitfld.long 0x18 10. "ESUSPM,Early suspend mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x18 7. "GONAKEFFM,Global OUT NAK effective mask" "0: Masked interrupt,1: Unmasked interrupt" bitfld.long 0x18 6. "GINAKEFFM,Global non-periodic IN NAK effective mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x18 5. "NPTXFEM,Non-periodic Tx FIFO empty mask" "0: Masked interrupt,1: Unmasked interrupt" bitfld.long 0x18 4. "RXFLVLM,Receive FIFO non-empty mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x18 3. "SOFM,Start of frame mask" "0: Masked interrupt,1: Unmasked interrupt" bitfld.long 0x18 2. "OTGINT,OTG interrupt mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x18 1. "MMISM,Mode mismatch interrupt mask" "0: Masked interrupt,1: Unmasked interrupt" endif sif (cpuis("STM32MP151*")) bitfld.long 0x18 31. "WUIM,WUIM" "0,1" newline bitfld.long 0x18 30. "SRQIM,SRQIM" "0,1" bitfld.long 0x18 29. "DISCINT,DISCINT" "0,1" newline bitfld.long 0x18 28. "CIDSCHGM,CIDSCHGM" "0,1" bitfld.long 0x18 27. "LPMINTM,LPMINTM" "0,1" newline bitfld.long 0x18 26. "PTXFEM,PTXFEM" "0,1" bitfld.long 0x18 25. "HCIM,HCIM" "0,1" newline rbitfld.long 0x18 24. "PRTIM,PRTIM" "0,1" bitfld.long 0x18 23. "RSTDETM,RSTDETM" "0,1" newline bitfld.long 0x18 22. "FSUSPM,FSUSPM" "0,1" bitfld.long 0x18 21. "IPXFRM,IPXFRM" "0,1" newline bitfld.long 0x18 20. "IISOIXFRM,IISOIXFRM" "0,1" bitfld.long 0x18 19. "OEPINT,OEPINT" "0,1" newline bitfld.long 0x18 18. "IEPINT,IEPINT" "0,1" endif sif (cpuis("STM32MP153*")) bitfld.long 0x18 31. "WUIM,WUIM" "0,1" newline bitfld.long 0x18 30. "SRQIM,SRQIM" "0,1" bitfld.long 0x18 29. "DISCINT,DISCINT" "0,1" newline bitfld.long 0x18 28. "CIDSCHGM,CIDSCHGM" "0,1" bitfld.long 0x18 27. "LPMINTM,LPMINTM" "0,1" newline bitfld.long 0x18 26. "PTXFEM,PTXFEM" "0,1" bitfld.long 0x18 25. "HCIM,HCIM" "0,1" newline rbitfld.long 0x18 24. "PRTIM,PRTIM" "0,1" bitfld.long 0x18 23. "RSTDETM,RSTDETM" "0,1" newline bitfld.long 0x18 22. "FSUSPM,FSUSPM" "0,1" bitfld.long 0x18 21. "IPXFRM,IPXFRM" "0,1" newline bitfld.long 0x18 20. "IISOIXFRM,IISOIXFRM" "0,1" bitfld.long 0x18 19. "OEPINT,OEPINT" "0,1" newline bitfld.long 0x18 18. "IEPINT,IEPINT" "0,1" endif sif (cpuis("STM32MP157*")) bitfld.long 0x18 31. "WUIM,WUIM" "0,1" newline bitfld.long 0x18 30. "SRQIM,SRQIM" "0,1" bitfld.long 0x18 29. "DISCINT,DISCINT" "0,1" newline bitfld.long 0x18 28. "CIDSCHGM,CIDSCHGM" "0,1" bitfld.long 0x18 27. "LPMINTM,LPMINTM" "0,1" newline bitfld.long 0x18 26. "PTXFEM,PTXFEM" "0,1" bitfld.long 0x18 25. "HCIM,HCIM" "0,1" newline rbitfld.long 0x18 24. "PRTIM,PRTIM" "0,1" bitfld.long 0x18 23. "RSTDETM,RSTDETM" "0,1" newline bitfld.long 0x18 22. "FSUSPM,FSUSPM" "0,1" bitfld.long 0x18 21. "IPXFRM,IPXFRM" "0,1" newline bitfld.long 0x18 20. "IISOIXFRM,IISOIXFRM" "0,1" bitfld.long 0x18 19. "OEPINT,OEPINT" "0,1" newline bitfld.long 0x18 18. "IEPINT,IEPINT" "0,1" endif sif (cpuis("STM32MP151*")) bitfld.long 0x18 15. "EOPFM,EOPFM" "0,1" newline bitfld.long 0x18 14. "ISOODRPM,ISOODRPM" "0,1" bitfld.long 0x18 13. "ENUMDNEM,ENUMDNEM" "0,1" newline bitfld.long 0x18 12. "USBRST,USBRST" "0,1" bitfld.long 0x18 11. "USBSUSPM,USBSUSPM" "0,1" newline bitfld.long 0x18 10. "ESUSPM,ESUSPM" "0,1" endif sif (cpuis("STM32MP153*")) bitfld.long 0x18 15. "EOPFM,EOPFM" "0,1" newline bitfld.long 0x18 14. "ISOODRPM,ISOODRPM" "0,1" bitfld.long 0x18 13. "ENUMDNEM,ENUMDNEM" "0,1" newline bitfld.long 0x18 12. "USBRST,USBRST" "0,1" bitfld.long 0x18 11. "USBSUSPM,USBSUSPM" "0,1" newline bitfld.long 0x18 10. "ESUSPM,ESUSPM" "0,1" endif sif (cpuis("STM32MP157*")) bitfld.long 0x18 15. "EOPFM,EOPFM" "0,1" newline bitfld.long 0x18 14. "ISOODRPM,ISOODRPM" "0,1" bitfld.long 0x18 13. "ENUMDNEM,ENUMDNEM" "0,1" newline bitfld.long 0x18 12. "USBRST,USBRST" "0,1" bitfld.long 0x18 11. "USBSUSPM,USBSUSPM" "0,1" newline bitfld.long 0x18 10. "ESUSPM,ESUSPM" "0,1" endif sif (cpuis("STM32MP151*")) bitfld.long 0x18 7. "GONAKEFFM,GONAKEFFM" "0,1" newline bitfld.long 0x18 6. "GINAKEFFM,GINAKEFFM" "0,1" bitfld.long 0x18 5. "NPTXFEM,NPTXFEM" "0,1" newline bitfld.long 0x18 4. "RXFLVLM,RXFLVLM" "0,1" bitfld.long 0x18 3. "SOFM,SOFM" "0,1" newline bitfld.long 0x18 2. "OTGINT,OTGINT" "0,1" endif sif (cpuis("STM32MP153*")) bitfld.long 0x18 7. "GONAKEFFM,GONAKEFFM" "0,1" newline bitfld.long 0x18 6. "GINAKEFFM,GINAKEFFM" "0,1" bitfld.long 0x18 5. "NPTXFEM,NPTXFEM" "0,1" newline bitfld.long 0x18 4. "RXFLVLM,RXFLVLM" "0,1" bitfld.long 0x18 3. "SOFM,SOFM" "0,1" newline bitfld.long 0x18 2. "OTGINT,OTGINT" "0,1" bitfld.long 0x18 1. "MMISM,MMISM" "0,1" newline endif sif (cpuis("STM32MP157*")) bitfld.long 0x18 7. "GONAKEFFM,GONAKEFFM" "0,1" bitfld.long 0x18 6. "GINAKEFFM,GINAKEFFM" "0,1" newline bitfld.long 0x18 5. "NPTXFEM,NPTXFEM" "0,1" bitfld.long 0x18 4. "RXFLVLM,RXFLVLM" "0,1" newline bitfld.long 0x18 3. "SOFM,SOFM" "0,1" bitfld.long 0x18 2. "OTGINT,OTGINT" "0,1" newline bitfld.long 0x18 1. "MMISM,MMISM" "0,1" endif line.long 0x1C "OTG_GRXSTSR,OTG receive status debug read register" sif (cpuis("STM32MP13*")) rbitfld.long 0x1C 27. "STSPHST,Status phase start" "0,1" hexmask.long.byte 0x1C 21.--24. 1. "FRMNUM,Frame number" newline hexmask.long.byte 0x1C 17.--20. 1. "PKTSTS,Packet status" rbitfld.long 0x1C 15.--16. "DPID,Data PID" "0: DATA0,1: DATA2,2: DATA1,3: MDATA" newline hexmask.long.word 0x1C 4.--14. 1. "BCNT,Byte count" hexmask.long.byte 0x1C 0.--3. 1. "EPNUM,Endpoint number" newline endif sif (cpuis("STM32MP151*")) bitfld.long 0x1C 27. "STSPHST,STSPHST" "0,1" endif sif (cpuis("STM32MP153*")) bitfld.long 0x1C 27. "STSPHST,STSPHST" "0,1" newline endif sif (cpuis("STM32MP157*")) bitfld.long 0x1C 27. "STSPHST,STSPHST" "0,1" endif sif (cpuis("STM32MP151*")) hexmask.long.byte 0x1C 21.--24. 1. "FRMNUM,FRMNUM" newline hexmask.long.byte 0x1C 17.--20. 1. "PKTSTS,PKTSTS" bitfld.long 0x1C 15.--16. "DPID,DPID" "0,1,2,3" newline hexmask.long.word 0x1C 4.--14. 1. "BCNT,BCNT" hexmask.long.byte 0x1C 0.--3. 1. "EPNUM,EPNUM" newline endif sif (cpuis("STM32MP153*")) hexmask.long.byte 0x1C 21.--24. 1. "FRMNUM,FRMNUM" hexmask.long.byte 0x1C 17.--20. 1. "PKTSTS,PKTSTS" newline bitfld.long 0x1C 15.--16. "DPID,DPID" "0,1,2,3" hexmask.long.word 0x1C 4.--14. 1. "BCNT,BCNT" newline hexmask.long.byte 0x1C 0.--3. 1. "EPNUM,EPNUM" endif sif (cpuis("STM32MP157*")) hexmask.long.byte 0x1C 21.--24. 1. "FRMNUM,FRMNUM" newline hexmask.long.byte 0x1C 17.--20. 1. "PKTSTS,PKTSTS" bitfld.long 0x1C 15.--16. "DPID,DPID" "0,1,2,3" newline hexmask.long.word 0x1C 4.--14. 1. "BCNT,BCNT" hexmask.long.byte 0x1C 0.--3. 1. "EPNUM,EPNUM" endif line.long 0x20 "OTG_GRXSTSP,OTG status read and pop register" sif (cpuis("STM32MP13*")) rbitfld.long 0x20 27. "STSPHST,Status phase start" "0,1" hexmask.long.byte 0x20 21.--24. 1. "FRMNUM,Frame number" newline hexmask.long.byte 0x20 17.--20. 1. "PKTSTS,Packet status" rbitfld.long 0x20 15.--16. "DPID,Data PID" "0: DATA0,1: DATA2,2: DATA1,3: MDATA" newline hexmask.long.word 0x20 4.--14. 1. "BCNT,Byte count" hexmask.long.byte 0x20 0.--3. 1. "EPNUM,Endpoint number" newline endif sif (cpuis("STM32MP151*")) bitfld.long 0x20 27. "STSPHST,STSPHST" "0,1" endif sif (cpuis("STM32MP153*")) bitfld.long 0x20 27. "STSPHST,STSPHST" "0,1" newline endif sif (cpuis("STM32MP157*")) bitfld.long 0x20 27. "STSPHST,STSPHST" "0,1" endif sif (cpuis("STM32MP151*")) hexmask.long.byte 0x20 21.--24. 1. "FRMNUM,FRMNUM" newline hexmask.long.byte 0x20 17.--20. 1. "PKTSTS,PKTSTS" bitfld.long 0x20 15.--16. "DPID,DPID" "0,1,2,3" newline hexmask.long.word 0x20 4.--14. 1. "BCNT,BCNT" hexmask.long.byte 0x20 0.--3. 1. "EPNUM,EPNUM" newline endif sif (cpuis("STM32MP153*")) hexmask.long.byte 0x20 21.--24. 1. "FRMNUM,FRMNUM" hexmask.long.byte 0x20 17.--20. 1. "PKTSTS,PKTSTS" newline bitfld.long 0x20 15.--16. "DPID,DPID" "0,1,2,3" hexmask.long.word 0x20 4.--14. 1. "BCNT,BCNT" newline hexmask.long.byte 0x20 0.--3. 1. "EPNUM,EPNUM" endif sif (cpuis("STM32MP157*")) hexmask.long.byte 0x20 21.--24. 1. "FRMNUM,FRMNUM" newline hexmask.long.byte 0x20 17.--20. 1. "PKTSTS,PKTSTS" bitfld.long 0x20 15.--16. "DPID,DPID" "0,1,2,3" newline hexmask.long.word 0x20 4.--14. 1. "BCNT,BCNT" hexmask.long.byte 0x20 0.--3. 1. "EPNUM,EPNUM" endif line.long 0x24 "OTG_GRXFSIZ,OTG receive FIFO size register" hexmask.long.word 0x24 0.--15. 1. "RXFD,Rx FIFO depth" line.long 0x28 "OTG_HNPTXFSIZ,OTG host non-periodic transmit FIFO size register" hexmask.long.word 0x28 16.--31. 1. "NPTXFD,Non-periodic Tx FIFO depth" hexmask.long.word 0x28 0.--15. 1. "NPTXFSA,Non-periodic transmit RAM start address" line.long 0x2C "OTG_HNPTXSTS,OTG non-periodic transmit FIFO/queue status register" sif (cpuis("STM32MP13*")) hexmask.long.byte 0x2C 24.--30. 1. "NPTXQTOP,Top of the non-periodic transmit request queue" hexmask.long.byte 0x2C 16.--23. 1. "NPTQXSAV,Non-periodic transmit request queue space available" newline hexmask.long.word 0x2C 0.--15. 1. "NPTXFSAV,Non-periodic Tx FIFO space available" endif sif (cpuis("STM32MP151*")) hexmask.long.byte 0x2C 24.--30. 1. "NPTXQTOP,NPTXQTOP" newline hexmask.long.byte 0x2C 16.--23. 1. "NPTQXSAV,NPTQXSAV" hexmask.long.word 0x2C 0.--15. 1. "NPTXFSAV,NPTXFSAV" newline endif sif (cpuis("STM32MP153*")) hexmask.long.byte 0x2C 24.--30. 1. "NPTXQTOP,NPTXQTOP" hexmask.long.byte 0x2C 16.--23. 1. "NPTQXSAV,NPTQXSAV" newline hexmask.long.word 0x2C 0.--15. 1. "NPTXFSAV,NPTXFSAV" endif sif (cpuis("STM32MP157*")) hexmask.long.byte 0x2C 24.--30. 1. "NPTXQTOP,NPTXQTOP" newline hexmask.long.byte 0x2C 16.--23. 1. "NPTQXSAV,NPTQXSAV" hexmask.long.word 0x2C 0.--15. 1. "NPTXFSAV,NPTXFSAV" endif group.long 0x38++0x7 line.long 0x0 "OTG_GCCFG," sif (cpuis("STM32MP13*")) bitfld.long 0x0 22. "IDEN,USB ID detection enable" "0: Disable ID pin state detection,1: Enable ID pin state detection" endif sif (cpuis("STM32MP151*")) bitfld.long 0x0 22. "IDEN,IDEN" "0,1" newline endif sif (cpuis("STM32MP153*")) bitfld.long 0x0 22. "IDEN,IDEN" "0,1" endif sif (cpuis("STM32MP157*")) bitfld.long 0x0 22. "IDEN,IDEN" "0,1" newline endif bitfld.long 0x0 21. "VBDEN,USB VBUS detection enable" "0: VBUS detection disabled,1: VBUS detection enabled" sif (cpuis("STM32MP151*")) bitfld.long 0x0 20. "SDEN,SDEN" "0,1" newline bitfld.long 0x0 19. "PDEN,PDEN" "0,1" endif sif (cpuis("STM32MP153*")) bitfld.long 0x0 20. "SDEN,SDEN" "0,1" newline bitfld.long 0x0 19. "PDEN,PDEN" "0,1" endif sif (cpuis("STM32MP157*")) bitfld.long 0x0 20. "SDEN,SDEN" "0,1" newline bitfld.long 0x0 19. "PDEN,PDEN" "0,1" endif sif (cpuis("STM32MP151*")) bitfld.long 0x0 17. "BCDEN,BCDEN" "0,1" newline bitfld.long 0x0 16. "PWRDWN,PWRDWN" "0,1" endif sif (cpuis("STM32MP153*")) bitfld.long 0x0 17. "BCDEN,BCDEN" "0,1" newline bitfld.long 0x0 16. "PWRDWN,PWRDWN" "0,1" endif sif (cpuis("STM32MP157*")) bitfld.long 0x0 17. "BCDEN,BCDEN" "0,1" newline bitfld.long 0x0 16. "PWRDWN,PWRDWN" "0,1" endif sif (cpuis("STM32MP151*")) rbitfld.long 0x0 3. "PS2DET,PS2DET" "0,1" newline rbitfld.long 0x0 2. "SDET,SDET" "0,1" rbitfld.long 0x0 1. "PDET,PDET" "0,1" newline endif sif (cpuis("STM32MP153*")) rbitfld.long 0x0 3. "PS2DET,PS2DET" "0,1" rbitfld.long 0x0 2. "SDET,SDET" "0,1" newline rbitfld.long 0x0 1. "PDET,PDET" "0,1" endif sif (cpuis("STM32MP157*")) rbitfld.long 0x0 3. "PS2DET,PS2DET" "0,1" newline rbitfld.long 0x0 2. "SDET,SDET" "0,1" rbitfld.long 0x0 1. "PDET,PDET" "0,1" endif line.long 0x4 "OTG_CID,OTG core ID register" hexmask.long 0x4 0.--31. 1. "PRODUCT_ID,Product ID field" group.long 0x54++0x3 line.long 0x0 "OTG_GLPMCFG," sif (cpuis("STM32MP13*")) bitfld.long 0x0 28. "ENBESL,Enable best effort service latency" "0: The core works as described in the following..,1: The core works as described in the LPM Errata:" rbitfld.long 0x0 16. "L1RSMOK,Sleep state resume OK" "0: The application or host cannot start resume from..,1: The application or host can start resume from.." newline rbitfld.long 0x0 15. "SLPSTS,Port sleep status" "0: Core not in L1,1: Core in L1" rbitfld.long 0x0 13.--14. "LPMRSP,LPM response" "0: ERROR (No handshake response),1: STALL,2: NYET,3: ACK" newline hexmask.long.byte 0x0 8.--11. 1. "BESLTHRS,BESL threshold" hexmask.long.byte 0x0 2.--5. 1. "BESL,Best effort service latency" newline bitfld.long 0x0 1. "LPMACK,LPM token acknowledge enable" "0: NYET,1: ACK" bitfld.long 0x0 0. "LPMEN,LPM support enable" "0: LPM capability is not enabled,1: LPM capability is enabled" newline endif sif (cpuis("STM32MP151*")) bitfld.long 0x0 28. "ENBESL,ENBESL" "0,1" endif sif (cpuis("STM32MP153*")) bitfld.long 0x0 28. "ENBESL,ENBESL" "0,1" newline endif sif (cpuis("STM32MP157*")) bitfld.long 0x0 28. "ENBESL,ENBESL" "0,1" endif rbitfld.long 0x0 25.--27. "LPMRCNTSTS,LPM retry count status" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 24. "SNDLPM,Send LPM transaction" "0,1" bitfld.long 0x0 21.--23. "LPMRCNT,LPM retry count" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 17.--20. 1. "LPMCHIDX,LPM Channel Index" sif (cpuis("STM32MP151*")) rbitfld.long 0x0 16. "L1RSMOK,L1RSMOK" "0,1" newline rbitfld.long 0x0 15. "SLPSTS,SLPSTS" "0,1" rbitfld.long 0x0 13.--14. "LPMRSP,LPMRSP" "0,1,2,3" newline endif sif (cpuis("STM32MP153*")) rbitfld.long 0x0 16. "L1RSMOK,L1RSMOK" "0,1" rbitfld.long 0x0 15. "SLPSTS,SLPSTS" "0,1" newline rbitfld.long 0x0 13.--14. "LPMRSP,LPMRSP" "0,1,2,3" endif sif (cpuis("STM32MP157*")) rbitfld.long 0x0 16. "L1RSMOK,L1RSMOK" "0,1" newline rbitfld.long 0x0 15. "SLPSTS,SLPSTS" "0,1" rbitfld.long 0x0 13.--14. "LPMRSP,LPMRSP" "0,1,2,3" newline endif bitfld.long 0x0 12. "L1DSEN,L1 deep sleep enable" "0,1" sif (cpuis("STM32MP151*")) hexmask.long.byte 0x0 8.--11. 1. "BESLTHRS,BESLTHRS" newline endif sif (cpuis("STM32MP153*")) hexmask.long.byte 0x0 8.--11. 1. "BESLTHRS,BESLTHRS" endif sif (cpuis("STM32MP157*")) hexmask.long.byte 0x0 8.--11. 1. "BESLTHRS,BESLTHRS" newline endif bitfld.long 0x0 7. "L1SSEN,L1 Shallow Sleep enable" "0,1" bitfld.long 0x0 6. "REMWAKE,bRemoteWake value" "0,1" newline sif (cpuis("STM32MP151*")) hexmask.long.byte 0x0 2.--5. 1. "BESL,BESL" bitfld.long 0x0 1. "LPMACK,LPMACK" "0,1" newline endif sif (cpuis("STM32MP153*")) hexmask.long.byte 0x0 2.--5. 1. "BESL,BESL" bitfld.long 0x0 1. "LPMACK,LPMACK" "0,1" newline bitfld.long 0x0 0. "LPMEN,LPMEN" "0,1" endif sif (cpuis("STM32MP157*")) hexmask.long.byte 0x0 2.--5. 1. "BESL,BESL" newline bitfld.long 0x0 1. "LPMACK,LPMACK" "0,1" bitfld.long 0x0 0. "LPMEN,LPMEN" "0,1" endif group.long 0x100++0x23 line.long 0x0 "OTG_HPTXFSIZ," hexmask.long.word 0x0 16.--31. 1. "PTXFSIZ,Host periodic Tx FIFO depth" hexmask.long.word 0x0 0.--15. 1. "PTXSA,Host periodic Tx FIFO start address" line.long 0x4 "OTG_DIEPTXF1," hexmask.long.word 0x4 16.--31. 1. "INEPTXFD,IN endpoint Tx FIFO depth" hexmask.long.word 0x4 0.--15. 1. "INEPTXSA,IN endpoint FIFOx transmit RAM start address" line.long 0x8 "OTG_DIEPTXF2," hexmask.long.word 0x8 16.--31. 1. "INEPTXFD,IN endpoint Tx FIFO depth" hexmask.long.word 0x8 0.--15. 1. "INEPTXSA,IN endpoint FIFOx transmit RAM start address" line.long 0xC "OTG_DIEPTXF3," hexmask.long.word 0xC 16.--31. 1. "INEPTXFD,IN endpoint Tx FIFO depth" hexmask.long.word 0xC 0.--15. 1. "INEPTXSA,IN endpoint FIFOx transmit RAM start address" line.long 0x10 "OTG_DIEPTXF4," hexmask.long.word 0x10 16.--31. 1. "INEPTXFD,IN endpoint Tx FIFO depth" hexmask.long.word 0x10 0.--15. 1. "INEPTXSA,IN endpoint FIFOx transmit RAM start address" line.long 0x14 "OTG_DIEPTXF5," hexmask.long.word 0x14 16.--31. 1. "INEPTXFD,IN endpoint Tx FIFO depth" hexmask.long.word 0x14 0.--15. 1. "INEPTXSA,IN endpoint FIFOx transmit RAM start address" line.long 0x18 "OTG_DIEPTXF6," hexmask.long.word 0x18 16.--31. 1. "INEPTXFD,IN endpoint Tx FIFO depth" hexmask.long.word 0x18 0.--15. 1. "INEPTXSA,IN endpoint FIFOx transmit RAM start address" line.long 0x1C "OTG_DIEPTXF7," hexmask.long.word 0x1C 16.--31. 1. "INEPTXFD,IN endpoint Tx FIFO depth" hexmask.long.word 0x1C 0.--15. 1. "INEPTXSA,IN endpoint FIFOx transmit RAM start address" line.long 0x20 "OTG_DIEPTXF8," hexmask.long.word 0x20 16.--31. 1. "INEPTXFD,IN endpoint Tx FIFO depth" hexmask.long.word 0x20 0.--15. 1. "INEPTXSA,IN endpoint FIFOx transmit RAM start address" group.long 0x400++0xB line.long 0x0 "OTG_HCFG,OTG host configuration register" bitfld.long 0x0 26. "PERSSCHEDENA,Enable periodic scheduling" "0,1" bitfld.long 0x0 24.--25. "FRLSTEN,Frame list entries" "0: Reserved,1: 8 Entries,2: 16 Entries,3: 32 Entries In non-Scatter/Gather" newline bitfld.long 0x0 23. "DESCDMA,Enable scatter/gather DMA in host mode" "0: Buffered DMA mode,1: Scatter/Gather DMA mode" rbitfld.long 0x0 2. "FSLSS,FS- and LS-only support" "0,1" newline sif (cpuis("STM32MP13*")) bitfld.long 0x0 0.--1. "FSLSPCS,FS/LS PHY clock select" "?,1: Select 48 MHz PHY clock frequency,2: Select 6 MHz PHY clock frequency,?" endif sif (cpuis("STM32MP153*")) bitfld.long 0x0 0.--1. "FSLSPCS,FSLSPCS" "0,1,2,3" newline endif sif (cpuis("STM32MP157*")) bitfld.long 0x0 0.--1. "FSLSPCS,FSLSPCS" "0,1,2,3" endif line.long 0x4 "OTG_HFIR,OTG host frame interval register" sif (cpuis("STM32MP13*")) bitfld.long 0x4 16. "RLDCTRL,Reload control" "0: The HFIR cannot be reloaded dynamically,1: The HFIR can be dynamically reloaded during run.." endif sif (cpuis("STM32MP151*")) bitfld.long 0x4 16. "RLDCTRL,RLDCTRL" "0,1" newline endif sif (cpuis("STM32MP153*")) bitfld.long 0x4 16. "RLDCTRL,RLDCTRL" "0,1" endif sif (cpuis("STM32MP157*")) bitfld.long 0x4 16. "RLDCTRL,RLDCTRL" "0,1" newline endif hexmask.long.word 0x4 0.--15. 1. "FRIVL,Frame interval" line.long 0x8 "OTG_HFNUM,OTG host frame number/frame time remaining register" sif (cpuis("STM32MP13*")) hexmask.long.word 0x8 16.--31. 1. "FTREM,Frame time remaining" hexmask.long.word 0x8 0.--15. 1. "FRNUM,Frame number" newline endif sif (cpuis("STM32MP151*")) hexmask.long.word 0x8 16.--31. 1. "FTREM,FTREM" hexmask.long.word 0x8 0.--15. 1. "FRNUM,FRNUM" newline endif sif (cpuis("STM32MP153*")) hexmask.long.word 0x8 16.--31. 1. "FTREM,FTREM" hexmask.long.word 0x8 0.--15. 1. "FRNUM,FRNUM" newline endif sif (cpuis("STM32MP157*")) hexmask.long.word 0x8 16.--31. 1. "FTREM,FTREM" hexmask.long.word 0x8 0.--15. 1. "FRNUM,FRNUM" endif group.long 0x410++0xF line.long 0x0 "OTG_HPTXSTS,OTG_Host periodic transmit FIFO/queue status register" sif (cpuis("STM32MP13*")) hexmask.long.byte 0x0 24.--31. 1. "PTXQTOP,Top of the periodic transmit request queue" hexmask.long.byte 0x0 16.--23. 1. "PTXQSAV,Periodic transmit request queue space available" newline hexmask.long.word 0x0 0.--15. 1. "PTXFSAVL,Periodic transmit data FIFO space available" endif sif (cpuis("STM32MP151*")) hexmask.long.byte 0x0 24.--31. 1. "PTXQTOP,PTXQTOP" newline hexmask.long.byte 0x0 16.--23. 1. "PTXQSAV,PTXQSAV" hexmask.long.word 0x0 0.--15. 1. "PTXFSAVL,PTXFSAVL" newline endif sif (cpuis("STM32MP153*")) hexmask.long.byte 0x0 24.--31. 1. "PTXQTOP,PTXQTOP" hexmask.long.byte 0x0 16.--23. 1. "PTXQSAV,PTXQSAV" newline hexmask.long.word 0x0 0.--15. 1. "PTXFSAVL,PTXFSAVL" endif sif (cpuis("STM32MP157*")) hexmask.long.byte 0x0 24.--31. 1. "PTXQTOP,PTXQTOP" newline hexmask.long.byte 0x0 16.--23. 1. "PTXQSAV,PTXQSAV" hexmask.long.word 0x0 0.--15. 1. "PTXFSAVL,PTXFSAVL" endif line.long 0x4 "OTG_HAINT,OTG host all channels interrupt register" sif (cpuis("STM32MP13*")) hexmask.long.word 0x4 0.--15. 1. "HAINT,Channel interrupts" endif sif (cpuis("STM32MP151*")) hexmask.long.word 0x4 0.--15. 1. "HAINT,HAINT" newline endif sif (cpuis("STM32MP153*")) hexmask.long.word 0x4 0.--15. 1. "HAINT,HAINT" endif sif (cpuis("STM32MP157*")) hexmask.long.word 0x4 0.--15. 1. "HAINT,HAINT" endif line.long 0x8 "OTG_HAINTMSK,OTG host all channels interrupt mask register" sif (cpuis("STM32MP13*")) hexmask.long.word 0x8 0.--15. 1. "HAINTM,Channel interrupt mask" endif sif (cpuis("STM32MP153*")) hexmask.long.word 0x8 0.--15. 1. "HAINTM,HAINTM" newline endif sif (cpuis("STM32MP157*")) hexmask.long.word 0x8 0.--15. 1. "HAINTM,HAINTM" endif line.long 0xC "OTG_HFLBADDR,OTG host frame list base address register" hexmask.long 0xC 0.--31. 1. "HFLBADDR,The starting address of the frame list (scatter/gather mode)." group.long 0x440++0x3 line.long 0x0 "OTG_HPRT,OTG host port control and status register" sif (cpuis("STM32MP13*")) rbitfld.long 0x0 17.--18. "PSPD,Port speed" "0: High speed,1: Full speed,2: Low speed,?" hexmask.long.byte 0x0 13.--16. 1. "PTCTL,Port test control" newline bitfld.long 0x0 12. "PPWR,Port power" "0: Power off,1: Power on" bitfld.long 0x0 8. "PRST,Port reset" "0: Port not in reset,1: Port in reset" newline bitfld.long 0x0 7. "PSUSP,Port suspend" "0: Port not in suspend mode,1: Port in suspend mode" bitfld.long 0x0 6. "PRES,Port resume" "0: No resume driven,1: Resume driven" newline rbitfld.long 0x0 4. "POCA,Port overcurrent active" "0: No overcurrent condition,1: Overcurrent condition" bitfld.long 0x0 2. "PENA,Port enable" "0: Port disabled,1: Port enabled" newline rbitfld.long 0x0 0. "PCSTS,Port connect status" "0: No device is attached to the port,1: A device is attached to the port" endif sif (cpuis("STM32MP151*")) rbitfld.long 0x0 17.--18. "PSPD,PSPD" "0,1,2,3" newline hexmask.long.byte 0x0 13.--16. 1. "PTCTL,PTCTL" bitfld.long 0x0 12. "PPWR,PPWR" "0,1" newline endif sif (cpuis("STM32MP153*")) rbitfld.long 0x0 17.--18. "PSPD,PSPD" "0,1,2,3" hexmask.long.byte 0x0 13.--16. 1. "PTCTL,PTCTL" newline bitfld.long 0x0 12. "PPWR,PPWR" "0,1" endif sif (cpuis("STM32MP157*")) rbitfld.long 0x0 17.--18. "PSPD,PSPD" "0,1,2,3" newline hexmask.long.byte 0x0 13.--16. 1. "PTCTL,PTCTL" bitfld.long 0x0 12. "PPWR,PPWR" "0,1" newline endif rbitfld.long 0x0 10.--11. "PLSTS,Port line status" "0,1,2,3" sif (cpuis("STM32MP151*")) bitfld.long 0x0 8. "PRST,PRST" "0,1" newline bitfld.long 0x0 7. "PSUSP,PSUSP" "0,1" bitfld.long 0x0 6. "PRES,PRES" "0,1" newline endif sif (cpuis("STM32MP153*")) bitfld.long 0x0 8. "PRST,PRST" "0,1" bitfld.long 0x0 7. "PSUSP,PSUSP" "0,1" newline bitfld.long 0x0 6. "PRES,PRES" "0,1" endif sif (cpuis("STM32MP157*")) bitfld.long 0x0 8. "PRST,PRST" "0,1" newline bitfld.long 0x0 7. "PSUSP,PSUSP" "0,1" bitfld.long 0x0 6. "PRES,PRES" "0,1" newline endif bitfld.long 0x0 5. "POCCHNG,Port overcurrent change" "0,1" sif (cpuis("STM32MP151*")) rbitfld.long 0x0 4. "POCA,POCA" "0,1" newline endif sif (cpuis("STM32MP153*")) rbitfld.long 0x0 4. "POCA,POCA" "0,1" endif sif (cpuis("STM32MP157*")) rbitfld.long 0x0 4. "POCA,POCA" "0,1" newline endif bitfld.long 0x0 3. "PENCHNG,Port enable/disable change" "0,1" sif (cpuis("STM32MP151*")) bitfld.long 0x0 2. "PENA,PENA" "0,1" newline endif sif (cpuis("STM32MP153*")) bitfld.long 0x0 2. "PENA,PENA" "0,1" endif sif (cpuis("STM32MP157*")) bitfld.long 0x0 2. "PENA,PENA" "0,1" newline endif bitfld.long 0x0 1. "PCDET,Port connect detected" "0,1" sif (cpuis("STM32MP153*")) rbitfld.long 0x0 0. "PCSTS,PCSTS" "0,1" newline endif sif (cpuis("STM32MP157*")) rbitfld.long 0x0 0. "PCSTS,PCSTS" "0,1" endif group.long 0x500++0x17 line.long 0x0 "OTG_HCCHAR0," sif (cpuis("STM32MP13*")) bitfld.long 0x0 31. "CHENA,Channel enable" "0: Indicates that the descriptor structure is not..,1: Indicates that the descriptor structure and data.." bitfld.long 0x0 29. "ODDFRM,Odd frame" "0: Even frame,1: Odd frame" newline bitfld.long 0x0 20.--21. "MCNT,Multicount" "0: Reserved. This field yields undefined results,1: 1 transaction,2: 2 transactions per frame to be issued for this..,3: 3 transactions per frame to be issued for this.." bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt" newline bitfld.long 0x0 15. "EPDIR,Endpoint direction" "0: OUT,1: IN" endif sif (cpuis("STM32MP151*")) bitfld.long 0x0 31. "CHENA,CHENA" "0,1" newline endif sif (cpuis("STM32MP153*")) bitfld.long 0x0 31. "CHENA,CHENA" "0,1" endif sif (cpuis("STM32MP157*")) bitfld.long 0x0 31. "CHENA,CHENA" "0,1" newline endif bitfld.long 0x0 30. "CHDIS,Channel disable" "0,1" hexmask.long.byte 0x0 22.--28. 1. "DAD,Device address" newline sif (cpuis("STM32MP151*")) bitfld.long 0x0 20.--21. "MCNT,MCNT" "0,1,2,3" bitfld.long 0x0 18.--19. "EPTYP,EPTYP" "0,1,2,3" newline endif sif (cpuis("STM32MP153*")) bitfld.long 0x0 20.--21. "MCNT,MCNT" "0,1,2,3" bitfld.long 0x0 18.--19. "EPTYP,EPTYP" "0,1,2,3" newline endif sif (cpuis("STM32MP157*")) bitfld.long 0x0 20.--21. "MCNT,MCNT" "0,1,2,3" bitfld.long 0x0 18.--19. "EPTYP,EPTYP" "0,1,2,3" newline endif bitfld.long 0x0 17. "LSDEV,Low-speed device" "0,1" sif (cpuis("STM32MP151*")) bitfld.long 0x0 15. "EPDIR,EPDIR" "0,1" newline endif sif (cpuis("STM32MP153*")) bitfld.long 0x0 15. "EPDIR,EPDIR" "0,1" endif sif (cpuis("STM32MP157*")) bitfld.long 0x0 15. "EPDIR,EPDIR" "0,1" newline endif hexmask.long.byte 0x0 11.--14. 1. "EPNUM,Endpoint number" hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" line.long 0x4 "OTG_HCSPLT0," bitfld.long 0x4 31. "SPLITEN,Split enable" "0,1" bitfld.long 0x4 16. "COMPLSPLT,Do complete split" "0,1" newline sif (cpuis("STM32MP13*")) bitfld.long 0x4 14.--15. "XACTPOS,Transaction position" "0: Mid. This is the middle payload of this..,1: End. This is the last payload of this..,2: Begin. This is the first data payload of this..,3: All. This is the entire data payload of this.." endif sif (cpuis("STM32MP151*")) bitfld.long 0x4 14.--15. "XACTPOS,XACTPOS" "0,1,2,3" newline endif sif (cpuis("STM32MP153*")) bitfld.long 0x4 14.--15. "XACTPOS,XACTPOS" "0,1,2,3" endif sif (cpuis("STM32MP157*")) bitfld.long 0x4 14.--15. "XACTPOS,XACTPOS" "0,1,2,3" newline endif hexmask.long.byte 0x4 7.--13. 1. "HUBADDR,Hub address" hexmask.long.byte 0x4 0.--6. 1. "PRTADDR,Port address" line.long 0x8 "OTG_HCINT0,OTG host channel 0 interrupt register" bitfld.long 0x8 13. "DESCLSTROLL,Descriptor rollover interrupt." "0,1" bitfld.long 0x8 12. "XCSXACTERR,Excessive transaction error." "0,1" newline bitfld.long 0x8 11. "BNA,Buffer not available interrupt." "0,1" bitfld.long 0x8 10. "DTERR,Data toggle error. In Scatter/Gather DMA mode the interrupt due to this bit is masked." "0,1" newline bitfld.long 0x8 9. "FRMOR,Frame overrun. In Scatter/Gather DMA mode the interrupt due to this bit is masked." "0,1" bitfld.long 0x8 8. "BBERR,Babble error. In Scatter/Gather DMA mode the interrupt due to this bit is masked." "0,1" newline bitfld.long 0x8 7. "TXERR,Transaction error. In Scatter/Gather DMA mode the interrupt due to this bit is masked." "0,1" bitfld.long 0x8 6. "NYET,Not yet ready response received interrupt. In Scatter/Gather DMA mode the interrupt due to this bit is masked." "0,1" newline bitfld.long 0x8 5. "ACK,ACK response received/transmitted interrupt. In Scatter/Gather DMA mode the interrupt due to this bit is masked." "0,1" bitfld.long 0x8 4. "NAK,NAK response received interrupt. In Scatter/Gather DMA mode the interrupt due to this bit is masked." "0,1" newline bitfld.long 0x8 3. "STALL,STALL response received interrupt. In Scatter/Gather DMA mode the interrupt due to this bit is masked." "0,1" bitfld.long 0x8 2. "AHBERR,AHB error" "0,1" newline bitfld.long 0x8 1. "CHH,Channel halted." "0,1" bitfld.long 0x8 0. "XFRC,Transfer completed." "0,1" line.long 0xC "OTG_HCINTMSK0,OTG host channel 0 interrupt mask register" bitfld.long 0xC 13. "DESCLSTROLLMSK,Descriptor rollover interrupt mask register." "0,1" bitfld.long 0xC 11. "BNAMSK,Buffer not available interrupt mask register." "0,1" newline sif (cpuis("STM32MP13*")) bitfld.long 0xC 10. "DTERRM,Data toggle error mask. In Scatter/Gather DMA mode the interrupt due to this bit is masked." "0: Masked interrupt,1: Unmasked interrupt" bitfld.long 0xC 9. "FRMORM,Frame overrun mask. In Scatter/Gather DMA mode the interrupt due to this bit is masked." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 8. "BBERRM,Babble error mask. In Scatter/Gather DMA mode the interrupt due to this bit is masked." "0: Masked interrupt,1: Unmasked interrupt" bitfld.long 0xC 7. "TXERRM,Transaction error mask. In Scatter/Gather DMA mode the interrupt due to this bit is masked." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 6. "NYET,response received interrupt mask. In Scatter/Gather DMA mode the interrupt due to this bit is masked." "0: Masked interrupt,1: Unmasked interrupt" bitfld.long 0xC 5. "ACKM,ACK response received/transmitted interrupt mask. In Scatter/Gather DMA mode the interrupt due to this bit is masked." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 4. "NAKM,NAK response received interrupt mask. In Scatter/Gather DMA mode the interrupt due to this bit is masked." "0: Masked interrupt,1: Unmasked interrupt" bitfld.long 0xC 3. "STALLM,STALL response received interrupt mask. In Scatter/Gather DMA mode the interrupt due to this bit is masked." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 2. "AHBERRM,AHB error. In scatter/gather DMA mode for host interrupts will not be generated due to the corresponding bits set in OTG_HCINTx." "0: Masked interrupt,1: Unmasked interrupt" bitfld.long 0xC 1. "CHHM,Channel halted mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0xC 0. "XFRCM,Transfer completed mask" "0: Masked interrupt,1: Unmasked interrupt" endif sif (cpuis("STM32MP151*")) bitfld.long 0xC 10. "DTERRM,DTERRM" "0,1" newline bitfld.long 0xC 9. "FRMORM,FRMORM" "0,1" bitfld.long 0xC 8. "BBERRM,BBERRM" "0,1" newline bitfld.long 0xC 7. "TXERRM,TXERRM" "0,1" bitfld.long 0xC 6. "NYET,NYET" "0,1" newline bitfld.long 0xC 5. "ACKM,ACKM" "0,1" bitfld.long 0xC 4. "NAKM,NAKM" "0,1" newline bitfld.long 0xC 3. "STALLM,STALLM" "0,1" bitfld.long 0xC 2. "AHBERRM,AHBERRM" "0,1" newline bitfld.long 0xC 1. "CHHM,CHHM" "0,1" endif sif (cpuis("STM32MP153*")) bitfld.long 0xC 10. "DTERRM,DTERRM" "0,1" newline bitfld.long 0xC 9. "FRMORM,FRMORM" "0,1" bitfld.long 0xC 8. "BBERRM,BBERRM" "0,1" newline bitfld.long 0xC 7. "TXERRM,TXERRM" "0,1" bitfld.long 0xC 6. "NYET,NYET" "0,1" newline bitfld.long 0xC 5. "ACKM,ACKM" "0,1" bitfld.long 0xC 4. "NAKM,NAKM" "0,1" newline bitfld.long 0xC 3. "STALLM,STALLM" "0,1" bitfld.long 0xC 2. "AHBERRM,AHBERRM" "0,1" newline bitfld.long 0xC 1. "CHHM,CHHM" "0,1" bitfld.long 0xC 0. "XFRCM,XFRCM" "0,1" newline endif sif (cpuis("STM32MP157*")) bitfld.long 0xC 10. "DTERRM,DTERRM" "0,1" bitfld.long 0xC 9. "FRMORM,FRMORM" "0,1" newline bitfld.long 0xC 8. "BBERRM,BBERRM" "0,1" bitfld.long 0xC 7. "TXERRM,TXERRM" "0,1" newline bitfld.long 0xC 6. "NYET,NYET" "0,1" bitfld.long 0xC 5. "ACKM,ACKM" "0,1" newline bitfld.long 0xC 4. "NAKM,NAKM" "0,1" bitfld.long 0xC 3. "STALLM,STALLM" "0,1" newline bitfld.long 0xC 2. "AHBERRM,AHBERRM" "0,1" bitfld.long 0xC 1. "CHHM,CHHM" "0,1" newline bitfld.long 0xC 0. "XFRCM,XFRCM" "0,1" endif line.long 0x10 "OTG_HCTSIZ0," sif (cpuis("STM32MP13*")) bitfld.long 0x10 31. "DOPNG,Do Ping" "0,1" bitfld.long 0x10 29.--30. "DPID,Data PID" "0: DATA0,1: DATA2,2: DATA1,3: SETUP (control) / MDATA (non-control)" newline endif sif (cpuis("STM32MP151*")) bitfld.long 0x10 29.--30. "DPID,DPID" "0,1,2,3" endif sif (cpuis("STM32MP153*")) bitfld.long 0x10 29.--30. "DPID,DPID" "0,1,2,3" newline endif sif (cpuis("STM32MP157*")) bitfld.long 0x10 29.--30. "DPID,DPID" "0,1,2,3" endif hexmask.long.word 0x10 19.--28. 1. "PKTCNT,Packet count" newline hexmask.long.tbyte 0x10 0.--18. 1. "XFRSIZ,Transfer size" line.long 0x14 "OTG_HCDMA0," hexmask.long 0x14 0.--31. 1. "DMAADDR,DMA address" group.long 0x51C++0x1B line.long 0x0 "OTG_HCDMAB0," sif (cpuis("STM32MP13*")) hexmask.long 0x0 0.--31. 1. "HCDMAB,DMA address" endif sif (cpuis("STM32MP151*")) hexmask.long 0x0 0.--31. 1. "HCDMAB,HCDMAB" newline endif sif (cpuis("STM32MP153*")) hexmask.long 0x0 0.--31. 1. "HCDMAB,HCDMAB" endif sif (cpuis("STM32MP157*")) hexmask.long 0x0 0.--31. 1. "HCDMAB,HCDMAB" endif line.long 0x4 "OTG_HCCHAR1," sif (cpuis("STM32MP13*")) bitfld.long 0x4 31. "CHENA,Channel enable" "0: Indicates that the descriptor structure is not..,1: Indicates that the descriptor structure and data.." bitfld.long 0x4 29. "ODDFRM,Odd frame" "0: Even frame,1: Odd frame" newline bitfld.long 0x4 20.--21. "MCNT,Multicount" "0: Reserved. This field yields undefined results,1: 1 transaction,2: 2 transactions per frame to be issued for this..,3: 3 transactions per frame to be issued for this.." bitfld.long 0x4 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt" newline bitfld.long 0x4 15. "EPDIR,Endpoint direction" "0: OUT,1: IN" endif sif (cpuis("STM32MP151*")) bitfld.long 0x4 31. "CHENA,CHENA" "0,1" newline endif sif (cpuis("STM32MP153*")) bitfld.long 0x4 31. "CHENA,CHENA" "0,1" endif sif (cpuis("STM32MP157*")) bitfld.long 0x4 31. "CHENA,CHENA" "0,1" newline endif bitfld.long 0x4 30. "CHDIS,Channel disable" "0,1" hexmask.long.byte 0x4 22.--28. 1. "DAD,Device address" newline sif (cpuis("STM32MP151*")) bitfld.long 0x4 20.--21. "MCNT,MCNT" "0,1,2,3" bitfld.long 0x4 18.--19. "EPTYP,EPTYP" "0,1,2,3" newline endif sif (cpuis("STM32MP153*")) bitfld.long 0x4 20.--21. "MCNT,MCNT" "0,1,2,3" bitfld.long 0x4 18.--19. "EPTYP,EPTYP" "0,1,2,3" newline endif sif (cpuis("STM32MP157*")) bitfld.long 0x4 20.--21. "MCNT,MCNT" "0,1,2,3" bitfld.long 0x4 18.--19. "EPTYP,EPTYP" "0,1,2,3" newline endif bitfld.long 0x4 17. "LSDEV,Low-speed device" "0,1" sif (cpuis("STM32MP151*")) bitfld.long 0x4 15. "EPDIR,EPDIR" "0,1" newline endif sif (cpuis("STM32MP153*")) bitfld.long 0x4 15. "EPDIR,EPDIR" "0,1" endif sif (cpuis("STM32MP157*")) bitfld.long 0x4 15. "EPDIR,EPDIR" "0,1" newline endif hexmask.long.byte 0x4 11.--14. 1. "EPNUM,Endpoint number" hexmask.long.word 0x4 0.--10. 1. "MPSIZ,Maximum packet size" line.long 0x8 "OTG_HCSPLT1," bitfld.long 0x8 31. "SPLITEN,Split enable" "0,1" bitfld.long 0x8 16. "COMPLSPLT,Do complete split" "0,1" newline sif (cpuis("STM32MP13*")) bitfld.long 0x8 14.--15. "XACTPOS,Transaction position" "0: Mid. This is the middle payload of this..,1: End. This is the last payload of this..,2: Begin. This is the first data payload of this..,3: All. This is the entire data payload of this.." endif sif (cpuis("STM32MP151*")) bitfld.long 0x8 14.--15. "XACTPOS,XACTPOS" "0,1,2,3" newline endif sif (cpuis("STM32MP153*")) bitfld.long 0x8 14.--15. "XACTPOS,XACTPOS" "0,1,2,3" endif sif (cpuis("STM32MP157*")) bitfld.long 0x8 14.--15. "XACTPOS,XACTPOS" "0,1,2,3" newline endif hexmask.long.byte 0x8 7.--13. 1. "HUBADDR,Hub address" hexmask.long.byte 0x8 0.--6. 1. "PRTADDR,Port address" line.long 0xC "OTG_HCINT1,OTG host channel 1 interrupt register" bitfld.long 0xC 13. "DESCLSTROLL,Descriptor rollover interrupt." "0,1" bitfld.long 0xC 12. "XCSXACTERR,Excessive transaction error." "0,1" newline bitfld.long 0xC 11. "BNA,Buffer not available interrupt." "0,1" bitfld.long 0xC 10. "DTERR,Data toggle error. In Scatter/Gather DMA mode the interrupt due to this bit is masked." "0,1" newline bitfld.long 0xC 9. "FRMOR,Frame overrun. In Scatter/Gather DMA mode the interrupt due to this bit is masked." "0,1" bitfld.long 0xC 8. "BBERR,Babble error. In Scatter/Gather DMA mode the interrupt due to this bit is masked." "0,1" newline bitfld.long 0xC 7. "TXERR,Transaction error. In Scatter/Gather DMA mode the interrupt due to this bit is masked." "0,1" bitfld.long 0xC 6. "NYET,Not yet ready response received interrupt. In Scatter/Gather DMA mode the interrupt due to this bit is masked." "0,1" newline bitfld.long 0xC 5. "ACK,ACK response received/transmitted interrupt. In Scatter/Gather DMA mode the interrupt due to this bit is masked." "0,1" bitfld.long 0xC 4. "NAK,NAK response received interrupt. In Scatter/Gather DMA mode the interrupt due to this bit is masked." "0,1" newline bitfld.long 0xC 3. "STALL,STALL response received interrupt. In Scatter/Gather DMA mode the interrupt due to this bit is masked." "0,1" bitfld.long 0xC 2. "AHBERR,AHB error" "0,1" newline bitfld.long 0xC 1. "CHH,Channel halted." "0,1" bitfld.long 0xC 0. "XFRC,Transfer completed." "0,1" line.long 0x10 "OTG_HCINTMSK1,OTG host channel 1 interrupt mask register" bitfld.long 0x10 13. "DESCLSTROLLMSK,Descriptor rollover interrupt mask register." "0,1" bitfld.long 0x10 11. "BNAMSK,Buffer not available interrupt mask register." "0,1" newline sif (cpuis("STM32MP13*")) bitfld.long 0x10 10. "DTERRM,Data toggle error mask. In Scatter/Gather DMA mode the interrupt due to this bit is masked." "0: Masked interrupt,1: Unmasked interrupt" bitfld.long 0x10 9. "FRMORM,Frame overrun mask. In Scatter/Gather DMA mode the interrupt due to this bit is masked." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x10 8. "BBERRM,Babble error mask. In Scatter/Gather DMA mode the interrupt due to this bit is masked." "0: Masked interrupt,1: Unmasked interrupt" bitfld.long 0x10 7. "TXERRM,Transaction error mask. In Scatter/Gather DMA mode the interrupt due to this bit is masked." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x10 6. "NYET,response received interrupt mask. In Scatter/Gather DMA mode the interrupt due to this bit is masked." "0: Masked interrupt,1: Unmasked interrupt" bitfld.long 0x10 5. "ACKM,ACK response received/transmitted interrupt mask. In Scatter/Gather DMA mode the interrupt due to this bit is masked." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x10 4. "NAKM,NAK response received interrupt mask. In Scatter/Gather DMA mode the interrupt due to this bit is masked." "0: Masked interrupt,1: Unmasked interrupt" bitfld.long 0x10 3. "STALLM,STALL response received interrupt mask. In Scatter/Gather DMA mode the interrupt due to this bit is masked." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x10 2. "AHBERRM,AHB error. In scatter/gather DMA mode for host interrupts will not be generated due to the corresponding bits set in OTG_HCINTx." "0: Masked interrupt,1: Unmasked interrupt" bitfld.long 0x10 1. "CHHM,Channel halted mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x10 0. "XFRCM,Transfer completed mask" "0: Masked interrupt,1: Unmasked interrupt" endif sif (cpuis("STM32MP151*")) bitfld.long 0x10 10. "DTERRM,DTERRM" "0,1" newline bitfld.long 0x10 9. "FRMORM,FRMORM" "0,1" bitfld.long 0x10 8. "BBERRM,BBERRM" "0,1" newline bitfld.long 0x10 7. "TXERRM,TXERRM" "0,1" bitfld.long 0x10 6. "NYET,NYET" "0,1" newline bitfld.long 0x10 5. "ACKM,ACKM" "0,1" bitfld.long 0x10 4. "NAKM,NAKM" "0,1" newline bitfld.long 0x10 3. "STALLM,STALLM" "0,1" bitfld.long 0x10 2. "AHBERRM,AHBERRM" "0,1" newline bitfld.long 0x10 1. "CHHM,CHHM" "0,1" endif sif (cpuis("STM32MP153*")) bitfld.long 0x10 10. "DTERRM,DTERRM" "0,1" newline bitfld.long 0x10 9. "FRMORM,FRMORM" "0,1" bitfld.long 0x10 8. "BBERRM,BBERRM" "0,1" newline bitfld.long 0x10 7. "TXERRM,TXERRM" "0,1" bitfld.long 0x10 6. "NYET,NYET" "0,1" newline bitfld.long 0x10 5. "ACKM,ACKM" "0,1" bitfld.long 0x10 4. "NAKM,NAKM" "0,1" newline bitfld.long 0x10 3. "STALLM,STALLM" "0,1" bitfld.long 0x10 2. "AHBERRM,AHBERRM" "0,1" newline bitfld.long 0x10 1. "CHHM,CHHM" "0,1" bitfld.long 0x10 0. "XFRCM,XFRCM" "0,1" newline endif sif (cpuis("STM32MP157*")) bitfld.long 0x10 10. "DTERRM,DTERRM" "0,1" bitfld.long 0x10 9. "FRMORM,FRMORM" "0,1" newline bitfld.long 0x10 8. "BBERRM,BBERRM" "0,1" bitfld.long 0x10 7. "TXERRM,TXERRM" "0,1" newline bitfld.long 0x10 6. "NYET,NYET" "0,1" bitfld.long 0x10 5. "ACKM,ACKM" "0,1" newline bitfld.long 0x10 4. "NAKM,NAKM" "0,1" bitfld.long 0x10 3. "STALLM,STALLM" "0,1" newline bitfld.long 0x10 2. "AHBERRM,AHBERRM" "0,1" bitfld.long 0x10 1. "CHHM,CHHM" "0,1" newline bitfld.long 0x10 0. "XFRCM,XFRCM" "0,1" endif line.long 0x14 "OTG_HCTSIZ1," sif (cpuis("STM32MP13*")) bitfld.long 0x14 31. "DOPNG,Do Ping" "0,1" bitfld.long 0x14 29.--30. "DPID,Data PID" "0: DATA0,1: DATA2,2: DATA1,3: SETUP (control) / MDATA (non-control)" newline endif sif (cpuis("STM32MP151*")) bitfld.long 0x14 29.--30. "DPID,DPID" "0,1,2,3" endif sif (cpuis("STM32MP153*")) bitfld.long 0x14 29.--30. "DPID,DPID" "0,1,2,3" newline endif sif (cpuis("STM32MP157*")) bitfld.long 0x14 29.--30. "DPID,DPID" "0,1,2,3" endif hexmask.long.word 0x14 19.--28. 1. "PKTCNT,Packet count" newline hexmask.long.tbyte 0x14 0.--18. 1. "XFRSIZ,Transfer size" line.long 0x18 "OTG_HCDMA1," hexmask.long 0x18 0.--31. 1. "DMAADDR,DMA address" group.long 0x53C++0x1B line.long 0x0 "OTG_HCDMAB1," sif (cpuis("STM32MP13*")) hexmask.long 0x0 0.--31. 1. "HCDMAB,DMA address" endif sif (cpuis("STM32MP151*")) hexmask.long 0x0 0.--31. 1. "HCDMAB,HCDMAB" newline endif sif (cpuis("STM32MP153*")) hexmask.long 0x0 0.--31. 1. "HCDMAB,HCDMAB" endif sif (cpuis("STM32MP157*")) hexmask.long 0x0 0.--31. 1. "HCDMAB,HCDMAB" endif line.long 0x4 "OTG_HCCHAR2," sif (cpuis("STM32MP13*")) bitfld.long 0x4 31. "CHENA,Channel enable" "0: Indicates that the descriptor structure is not..,1: Indicates that the descriptor structure and data.." bitfld.long 0x4 29. "ODDFRM,Odd frame" "0: Even frame,1: Odd frame" newline bitfld.long 0x4 20.--21. "MCNT,Multicount" "0: Reserved. This field yields undefined results,1: 1 transaction,2: 2 transactions per frame to be issued for this..,3: 3 transactions per frame to be issued for this.." bitfld.long 0x4 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt" newline bitfld.long 0x4 15. "EPDIR,Endpoint direction" "0: OUT,1: IN" endif sif (cpuis("STM32MP151*")) bitfld.long 0x4 31. "CHENA,CHENA" "0,1" newline endif sif (cpuis("STM32MP153*")) bitfld.long 0x4 31. "CHENA,CHENA" "0,1" endif sif (cpuis("STM32MP157*")) bitfld.long 0x4 31. "CHENA,CHENA" "0,1" newline endif bitfld.long 0x4 30. "CHDIS,Channel disable" "0,1" hexmask.long.byte 0x4 22.--28. 1. "DAD,Device address" newline sif (cpuis("STM32MP151*")) bitfld.long 0x4 20.--21. "MCNT,MCNT" "0,1,2,3" bitfld.long 0x4 18.--19. "EPTYP,EPTYP" "0,1,2,3" newline endif sif (cpuis("STM32MP153*")) bitfld.long 0x4 20.--21. "MCNT,MCNT" "0,1,2,3" bitfld.long 0x4 18.--19. "EPTYP,EPTYP" "0,1,2,3" newline endif sif (cpuis("STM32MP157*")) bitfld.long 0x4 20.--21. "MCNT,MCNT" "0,1,2,3" bitfld.long 0x4 18.--19. "EPTYP,EPTYP" "0,1,2,3" newline endif bitfld.long 0x4 17. "LSDEV,Low-speed device" "0,1" sif (cpuis("STM32MP151*")) bitfld.long 0x4 15. "EPDIR,EPDIR" "0,1" newline endif sif (cpuis("STM32MP153*")) bitfld.long 0x4 15. "EPDIR,EPDIR" "0,1" endif sif (cpuis("STM32MP157*")) bitfld.long 0x4 15. "EPDIR,EPDIR" "0,1" newline endif hexmask.long.byte 0x4 11.--14. 1. "EPNUM,Endpoint number" hexmask.long.word 0x4 0.--10. 1. "MPSIZ,Maximum packet size" line.long 0x8 "OTG_HCSPLT2," bitfld.long 0x8 31. "SPLITEN,Split enable" "0,1" bitfld.long 0x8 16. "COMPLSPLT,Do complete split" "0,1" newline sif (cpuis("STM32MP13*")) bitfld.long 0x8 14.--15. "XACTPOS,Transaction position" "0: Mid. This is the middle payload of this..,1: End. This is the last payload of this..,2: Begin. This is the first data payload of this..,3: All. This is the entire data payload of this.." endif sif (cpuis("STM32MP151*")) bitfld.long 0x8 14.--15. "XACTPOS,XACTPOS" "0,1,2,3" newline endif sif (cpuis("STM32MP153*")) bitfld.long 0x8 14.--15. "XACTPOS,XACTPOS" "0,1,2,3" endif sif (cpuis("STM32MP157*")) bitfld.long 0x8 14.--15. "XACTPOS,XACTPOS" "0,1,2,3" newline endif hexmask.long.byte 0x8 7.--13. 1. "HUBADDR,Hub address" hexmask.long.byte 0x8 0.--6. 1. "PRTADDR,Port address" line.long 0xC "OTG_HCINT2,OTG host channel 2 interrupt register" bitfld.long 0xC 13. "DESCLSTROLL,Descriptor rollover interrupt." "0,1" bitfld.long 0xC 12. "XCSXACTERR,Excessive transaction error." "0,1" newline bitfld.long 0xC 11. "BNA,Buffer not available interrupt." "0,1" bitfld.long 0xC 10. "DTERR,Data toggle error. In Scatter/Gather DMA mode the interrupt due to this bit is masked." "0,1" newline bitfld.long 0xC 9. "FRMOR,Frame overrun. In Scatter/Gather DMA mode the interrupt due to this bit is masked." "0,1" bitfld.long 0xC 8. "BBERR,Babble error. In Scatter/Gather DMA mode the interrupt due to this bit is masked." "0,1" newline bitfld.long 0xC 7. "TXERR,Transaction error. In Scatter/Gather DMA mode the interrupt due to this bit is masked." "0,1" bitfld.long 0xC 6. "NYET,Not yet ready response received interrupt. In Scatter/Gather DMA mode the interrupt due to this bit is masked." "0,1" newline bitfld.long 0xC 5. "ACK,ACK response received/transmitted interrupt. In Scatter/Gather DMA mode the interrupt due to this bit is masked." "0,1" bitfld.long 0xC 4. "NAK,NAK response received interrupt. In Scatter/Gather DMA mode the interrupt due to this bit is masked." "0,1" newline bitfld.long 0xC 3. "STALL,STALL response received interrupt. In Scatter/Gather DMA mode the interrupt due to this bit is masked." "0,1" bitfld.long 0xC 2. "AHBERR,AHB error" "0,1" newline bitfld.long 0xC 1. "CHH,Channel halted." "0,1" bitfld.long 0xC 0. "XFRC,Transfer completed." "0,1" line.long 0x10 "OTG_HCINTMSK2,OTG host channel 2 interrupt mask register" bitfld.long 0x10 13. "DESCLSTROLLMSK,Descriptor rollover interrupt mask register." "0,1" bitfld.long 0x10 11. "BNAMSK,Buffer not available interrupt mask register." "0,1" newline sif (cpuis("STM32MP13*")) bitfld.long 0x10 10. "DTERRM,Data toggle error mask. In Scatter/Gather DMA mode the interrupt due to this bit is masked." "0: Masked interrupt,1: Unmasked interrupt" bitfld.long 0x10 9. "FRMORM,Frame overrun mask. In Scatter/Gather DMA mode the interrupt due to this bit is masked." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x10 8. "BBERRM,Babble error mask. In Scatter/Gather DMA mode the interrupt due to this bit is masked." "0: Masked interrupt,1: Unmasked interrupt" bitfld.long 0x10 7. "TXERRM,Transaction error mask. In Scatter/Gather DMA mode the interrupt due to this bit is masked." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x10 6. "NYET,response received interrupt mask. In Scatter/Gather DMA mode the interrupt due to this bit is masked." "0: Masked interrupt,1: Unmasked interrupt" bitfld.long 0x10 5. "ACKM,ACK response received/transmitted interrupt mask. In Scatter/Gather DMA mode the interrupt due to this bit is masked." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x10 4. "NAKM,NAK response received interrupt mask. In Scatter/Gather DMA mode the interrupt due to this bit is masked." "0: Masked interrupt,1: Unmasked interrupt" bitfld.long 0x10 3. "STALLM,STALL response received interrupt mask. In Scatter/Gather DMA mode the interrupt due to this bit is masked." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x10 2. "AHBERRM,AHB error. In scatter/gather DMA mode for host interrupts will not be generated due to the corresponding bits set in OTG_HCINTx." "0: Masked interrupt,1: Unmasked interrupt" bitfld.long 0x10 1. "CHHM,Channel halted mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x10 0. "XFRCM,Transfer completed mask" "0: Masked interrupt,1: Unmasked interrupt" endif sif (cpuis("STM32MP151*")) bitfld.long 0x10 10. "DTERRM,DTERRM" "0,1" newline bitfld.long 0x10 9. "FRMORM,FRMORM" "0,1" bitfld.long 0x10 8. "BBERRM,BBERRM" "0,1" newline bitfld.long 0x10 7. "TXERRM,TXERRM" "0,1" bitfld.long 0x10 6. "NYET,NYET" "0,1" newline bitfld.long 0x10 5. "ACKM,ACKM" "0,1" bitfld.long 0x10 4. "NAKM,NAKM" "0,1" newline bitfld.long 0x10 3. "STALLM,STALLM" "0,1" bitfld.long 0x10 2. "AHBERRM,AHBERRM" "0,1" newline bitfld.long 0x10 1. "CHHM,CHHM" "0,1" endif sif (cpuis("STM32MP153*")) bitfld.long 0x10 10. "DTERRM,DTERRM" "0,1" newline bitfld.long 0x10 9. "FRMORM,FRMORM" "0,1" bitfld.long 0x10 8. "BBERRM,BBERRM" "0,1" newline bitfld.long 0x10 7. "TXERRM,TXERRM" "0,1" bitfld.long 0x10 6. "NYET,NYET" "0,1" newline bitfld.long 0x10 5. "ACKM,ACKM" "0,1" bitfld.long 0x10 4. "NAKM,NAKM" "0,1" newline bitfld.long 0x10 3. "STALLM,STALLM" "0,1" bitfld.long 0x10 2. "AHBERRM,AHBERRM" "0,1" newline bitfld.long 0x10 1. "CHHM,CHHM" "0,1" bitfld.long 0x10 0. "XFRCM,XFRCM" "0,1" newline endif sif (cpuis("STM32MP157*")) bitfld.long 0x10 10. "DTERRM,DTERRM" "0,1" bitfld.long 0x10 9. "FRMORM,FRMORM" "0,1" newline bitfld.long 0x10 8. "BBERRM,BBERRM" "0,1" bitfld.long 0x10 7. "TXERRM,TXERRM" "0,1" newline bitfld.long 0x10 6. "NYET,NYET" "0,1" bitfld.long 0x10 5. "ACKM,ACKM" "0,1" newline bitfld.long 0x10 4. "NAKM,NAKM" "0,1" bitfld.long 0x10 3. "STALLM,STALLM" "0,1" newline bitfld.long 0x10 2. "AHBERRM,AHBERRM" "0,1" bitfld.long 0x10 1. "CHHM,CHHM" "0,1" newline bitfld.long 0x10 0. "XFRCM,XFRCM" "0,1" endif line.long 0x14 "OTG_HCTSIZ2," sif (cpuis("STM32MP13*")) bitfld.long 0x14 31. "DOPNG,Do Ping" "0,1" bitfld.long 0x14 29.--30. "DPID,Data PID" "0: DATA0,1: DATA2,2: DATA1,3: SETUP (control) / MDATA (non-control)" newline endif sif (cpuis("STM32MP151*")) bitfld.long 0x14 29.--30. "DPID,DPID" "0,1,2,3" endif sif (cpuis("STM32MP153*")) bitfld.long 0x14 29.--30. "DPID,DPID" "0,1,2,3" newline endif sif (cpuis("STM32MP157*")) bitfld.long 0x14 29.--30. "DPID,DPID" "0,1,2,3" endif hexmask.long.word 0x14 19.--28. 1. "PKTCNT,Packet count" newline hexmask.long.tbyte 0x14 0.--18. 1. "XFRSIZ,Transfer size" line.long 0x18 "OTG_HCDMA2," hexmask.long 0x18 0.--31. 1. "DMAADDR,DMA address" group.long 0x55C++0x1B line.long 0x0 "OTG_HCDMAB2," sif (cpuis("STM32MP13*")) hexmask.long 0x0 0.--31. 1. "HCDMAB,DMA address" endif sif (cpuis("STM32MP151*")) hexmask.long 0x0 0.--31. 1. "HCDMAB,HCDMAB" newline endif sif (cpuis("STM32MP153*")) hexmask.long 0x0 0.--31. 1. "HCDMAB,HCDMAB" endif sif (cpuis("STM32MP157*")) hexmask.long 0x0 0.--31. 1. "HCDMAB,HCDMAB" endif line.long 0x4 "OTG_HCCHAR3," sif (cpuis("STM32MP13*")) bitfld.long 0x4 31. "CHENA,Channel enable" "0: Indicates that the descriptor structure is not..,1: Indicates that the descriptor structure and data.." bitfld.long 0x4 29. "ODDFRM,Odd frame" "0: Even frame,1: Odd frame" newline bitfld.long 0x4 20.--21. "MCNT,Multicount" "0: Reserved. This field yields undefined results,1: 1 transaction,2: 2 transactions per frame to be issued for this..,3: 3 transactions per frame to be issued for this.." bitfld.long 0x4 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt" newline bitfld.long 0x4 15. "EPDIR,Endpoint direction" "0: OUT,1: IN" endif sif (cpuis("STM32MP151*")) bitfld.long 0x4 31. "CHENA,CHENA" "0,1" newline endif sif (cpuis("STM32MP153*")) bitfld.long 0x4 31. "CHENA,CHENA" "0,1" endif sif (cpuis("STM32MP157*")) bitfld.long 0x4 31. "CHENA,CHENA" "0,1" newline endif bitfld.long 0x4 30. "CHDIS,Channel disable" "0,1" hexmask.long.byte 0x4 22.--28. 1. "DAD,Device address" newline sif (cpuis("STM32MP151*")) bitfld.long 0x4 20.--21. "MCNT,MCNT" "0,1,2,3" bitfld.long 0x4 18.--19. "EPTYP,EPTYP" "0,1,2,3" newline endif sif (cpuis("STM32MP153*")) bitfld.long 0x4 20.--21. "MCNT,MCNT" "0,1,2,3" bitfld.long 0x4 18.--19. "EPTYP,EPTYP" "0,1,2,3" newline endif sif (cpuis("STM32MP157*")) bitfld.long 0x4 20.--21. "MCNT,MCNT" "0,1,2,3" bitfld.long 0x4 18.--19. "EPTYP,EPTYP" "0,1,2,3" newline endif bitfld.long 0x4 17. "LSDEV,Low-speed device" "0,1" sif (cpuis("STM32MP151*")) bitfld.long 0x4 15. "EPDIR,EPDIR" "0,1" newline endif sif (cpuis("STM32MP153*")) bitfld.long 0x4 15. "EPDIR,EPDIR" "0,1" endif sif (cpuis("STM32MP157*")) bitfld.long 0x4 15. "EPDIR,EPDIR" "0,1" newline endif hexmask.long.byte 0x4 11.--14. 1. "EPNUM,Endpoint number" hexmask.long.word 0x4 0.--10. 1. "MPSIZ,Maximum packet size" line.long 0x8 "OTG_HCSPLT3," bitfld.long 0x8 31. "SPLITEN,Split enable" "0,1" bitfld.long 0x8 16. "COMPLSPLT,Do complete split" "0,1" newline sif (cpuis("STM32MP13*")) bitfld.long 0x8 14.--15. "XACTPOS,Transaction position" "0: Mid. This is the middle payload of this..,1: End. This is the last payload of this..,2: Begin. This is the first data payload of this..,3: All. This is the entire data payload of this.." endif sif (cpuis("STM32MP151*")) bitfld.long 0x8 14.--15. "XACTPOS,XACTPOS" "0,1,2,3" newline endif sif (cpuis("STM32MP153*")) bitfld.long 0x8 14.--15. "XACTPOS,XACTPOS" "0,1,2,3" endif sif (cpuis("STM32MP157*")) bitfld.long 0x8 14.--15. "XACTPOS,XACTPOS" "0,1,2,3" newline endif hexmask.long.byte 0x8 7.--13. 1. "HUBADDR,Hub address" hexmask.long.byte 0x8 0.--6. 1. "PRTADDR,Port address" line.long 0xC "OTG_HCINT3,OTG host channel 3 interrupt register" bitfld.long 0xC 13. "DESCLSTROLL,Descriptor rollover interrupt." "0,1" bitfld.long 0xC 12. "XCSXACTERR,Excessive transaction error." "0,1" newline bitfld.long 0xC 11. "BNA,Buffer not available interrupt." "0,1" bitfld.long 0xC 10. "DTERR,Data toggle error. In Scatter/Gather DMA mode the interrupt due to this bit is masked." "0,1" newline bitfld.long 0xC 9. "FRMOR,Frame overrun. In Scatter/Gather DMA mode the interrupt due to this bit is masked." "0,1" bitfld.long 0xC 8. "BBERR,Babble error. In Scatter/Gather DMA mode the interrupt due to this bit is masked." "0,1" newline bitfld.long 0xC 7. "TXERR,Transaction error. In Scatter/Gather DMA mode the interrupt due to this bit is masked." "0,1" bitfld.long 0xC 6. "NYET,Not yet ready response received interrupt. In Scatter/Gather DMA mode the interrupt due to this bit is masked." "0,1" newline bitfld.long 0xC 5. "ACK,ACK response received/transmitted interrupt. In Scatter/Gather DMA mode the interrupt due to this bit is masked." "0,1" bitfld.long 0xC 4. "NAK,NAK response received interrupt. In Scatter/Gather DMA mode the interrupt due to this bit is masked." "0,1" newline bitfld.long 0xC 3. "STALL,STALL response received interrupt. In Scatter/Gather DMA mode the interrupt due to this bit is masked." "0,1" bitfld.long 0xC 2. "AHBERR,AHB error" "0,1" newline bitfld.long 0xC 1. "CHH,Channel halted." "0,1" bitfld.long 0xC 0. "XFRC,Transfer completed." "0,1" line.long 0x10 "OTG_HCINTMSK3,OTG host channel 3 interrupt mask register" bitfld.long 0x10 13. "DESCLSTROLLMSK,Descriptor rollover interrupt mask register." "0,1" bitfld.long 0x10 11. "BNAMSK,Buffer not available interrupt mask register." "0,1" newline sif (cpuis("STM32MP13*")) bitfld.long 0x10 10. "DTERRM,Data toggle error mask. In Scatter/Gather DMA mode the interrupt due to this bit is masked." "0: Masked interrupt,1: Unmasked interrupt" bitfld.long 0x10 9. "FRMORM,Frame overrun mask. In Scatter/Gather DMA mode the interrupt due to this bit is masked." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x10 8. "BBERRM,Babble error mask. In Scatter/Gather DMA mode the interrupt due to this bit is masked." "0: Masked interrupt,1: Unmasked interrupt" bitfld.long 0x10 7. "TXERRM,Transaction error mask. In Scatter/Gather DMA mode the interrupt due to this bit is masked." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x10 6. "NYET,response received interrupt mask. In Scatter/Gather DMA mode the interrupt due to this bit is masked." "0: Masked interrupt,1: Unmasked interrupt" bitfld.long 0x10 5. "ACKM,ACK response received/transmitted interrupt mask. In Scatter/Gather DMA mode the interrupt due to this bit is masked." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x10 4. "NAKM,NAK response received interrupt mask. In Scatter/Gather DMA mode the interrupt due to this bit is masked." "0: Masked interrupt,1: Unmasked interrupt" bitfld.long 0x10 3. "STALLM,STALL response received interrupt mask. In Scatter/Gather DMA mode the interrupt due to this bit is masked." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x10 2. "AHBERRM,AHB error. In scatter/gather DMA mode for host interrupts will not be generated due to the corresponding bits set in OTG_HCINTx." "0: Masked interrupt,1: Unmasked interrupt" bitfld.long 0x10 1. "CHHM,Channel halted mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x10 0. "XFRCM,Transfer completed mask" "0: Masked interrupt,1: Unmasked interrupt" endif sif (cpuis("STM32MP151*")) bitfld.long 0x10 10. "DTERRM,DTERRM" "0,1" newline bitfld.long 0x10 9. "FRMORM,FRMORM" "0,1" bitfld.long 0x10 8. "BBERRM,BBERRM" "0,1" newline bitfld.long 0x10 7. "TXERRM,TXERRM" "0,1" bitfld.long 0x10 6. "NYET,NYET" "0,1" newline bitfld.long 0x10 5. "ACKM,ACKM" "0,1" bitfld.long 0x10 4. "NAKM,NAKM" "0,1" newline bitfld.long 0x10 3. "STALLM,STALLM" "0,1" bitfld.long 0x10 2. "AHBERRM,AHBERRM" "0,1" newline bitfld.long 0x10 1. "CHHM,CHHM" "0,1" endif sif (cpuis("STM32MP153*")) bitfld.long 0x10 10. "DTERRM,DTERRM" "0,1" newline bitfld.long 0x10 9. "FRMORM,FRMORM" "0,1" bitfld.long 0x10 8. "BBERRM,BBERRM" "0,1" newline bitfld.long 0x10 7. "TXERRM,TXERRM" "0,1" bitfld.long 0x10 6. "NYET,NYET" "0,1" newline bitfld.long 0x10 5. "ACKM,ACKM" "0,1" bitfld.long 0x10 4. "NAKM,NAKM" "0,1" newline bitfld.long 0x10 3. "STALLM,STALLM" "0,1" bitfld.long 0x10 2. "AHBERRM,AHBERRM" "0,1" newline bitfld.long 0x10 1. "CHHM,CHHM" "0,1" bitfld.long 0x10 0. "XFRCM,XFRCM" "0,1" newline endif sif (cpuis("STM32MP157*")) bitfld.long 0x10 10. "DTERRM,DTERRM" "0,1" bitfld.long 0x10 9. "FRMORM,FRMORM" "0,1" newline bitfld.long 0x10 8. "BBERRM,BBERRM" "0,1" bitfld.long 0x10 7. "TXERRM,TXERRM" "0,1" newline bitfld.long 0x10 6. "NYET,NYET" "0,1" bitfld.long 0x10 5. "ACKM,ACKM" "0,1" newline bitfld.long 0x10 4. "NAKM,NAKM" "0,1" bitfld.long 0x10 3. "STALLM,STALLM" "0,1" newline bitfld.long 0x10 2. "AHBERRM,AHBERRM" "0,1" bitfld.long 0x10 1. "CHHM,CHHM" "0,1" newline bitfld.long 0x10 0. "XFRCM,XFRCM" "0,1" endif line.long 0x14 "OTG_HCTSIZ3," sif (cpuis("STM32MP13*")) bitfld.long 0x14 31. "DOPNG,Do Ping" "0,1" bitfld.long 0x14 29.--30. "DPID,Data PID" "0: DATA0,1: DATA2,2: DATA1,3: SETUP (control) / MDATA (non-control)" newline endif sif (cpuis("STM32MP151*")) bitfld.long 0x14 29.--30. "DPID,DPID" "0,1,2,3" endif sif (cpuis("STM32MP153*")) bitfld.long 0x14 29.--30. "DPID,DPID" "0,1,2,3" newline endif sif (cpuis("STM32MP157*")) bitfld.long 0x14 29.--30. "DPID,DPID" "0,1,2,3" endif hexmask.long.word 0x14 19.--28. 1. "PKTCNT,Packet count" newline hexmask.long.tbyte 0x14 0.--18. 1. "XFRSIZ,Transfer size" line.long 0x18 "OTG_HCDMA3," hexmask.long 0x18 0.--31. 1. "DMAADDR,DMA address" group.long 0x57C++0x1B line.long 0x0 "OTG_HCDMAB3," sif (cpuis("STM32MP13*")) hexmask.long 0x0 0.--31. 1. "HCDMAB,DMA address" endif sif (cpuis("STM32MP151*")) hexmask.long 0x0 0.--31. 1. "HCDMAB,HCDMAB" newline endif sif (cpuis("STM32MP153*")) hexmask.long 0x0 0.--31. 1. "HCDMAB,HCDMAB" endif sif (cpuis("STM32MP157*")) hexmask.long 0x0 0.--31. 1. "HCDMAB,HCDMAB" endif line.long 0x4 "OTG_HCCHAR4," sif (cpuis("STM32MP13*")) bitfld.long 0x4 31. "CHENA,Channel enable" "0: Indicates that the descriptor structure is not..,1: Indicates that the descriptor structure and data.." bitfld.long 0x4 29. "ODDFRM,Odd frame" "0: Even frame,1: Odd frame" newline bitfld.long 0x4 20.--21. "MCNT,Multicount" "0: Reserved. This field yields undefined results,1: 1 transaction,2: 2 transactions per frame to be issued for this..,3: 3 transactions per frame to be issued for this.." bitfld.long 0x4 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt" newline bitfld.long 0x4 15. "EPDIR,Endpoint direction" "0: OUT,1: IN" endif sif (cpuis("STM32MP151*")) bitfld.long 0x4 31. "CHENA,CHENA" "0,1" newline endif sif (cpuis("STM32MP153*")) bitfld.long 0x4 31. "CHENA,CHENA" "0,1" endif sif (cpuis("STM32MP157*")) bitfld.long 0x4 31. "CHENA,CHENA" "0,1" newline endif bitfld.long 0x4 30. "CHDIS,Channel disable" "0,1" hexmask.long.byte 0x4 22.--28. 1. "DAD,Device address" newline sif (cpuis("STM32MP151*")) bitfld.long 0x4 20.--21. "MCNT,MCNT" "0,1,2,3" bitfld.long 0x4 18.--19. "EPTYP,EPTYP" "0,1,2,3" newline endif sif (cpuis("STM32MP153*")) bitfld.long 0x4 20.--21. "MCNT,MCNT" "0,1,2,3" bitfld.long 0x4 18.--19. "EPTYP,EPTYP" "0,1,2,3" newline endif sif (cpuis("STM32MP157*")) bitfld.long 0x4 20.--21. "MCNT,MCNT" "0,1,2,3" bitfld.long 0x4 18.--19. "EPTYP,EPTYP" "0,1,2,3" newline endif bitfld.long 0x4 17. "LSDEV,Low-speed device" "0,1" sif (cpuis("STM32MP151*")) bitfld.long 0x4 15. "EPDIR,EPDIR" "0,1" newline endif sif (cpuis("STM32MP153*")) bitfld.long 0x4 15. "EPDIR,EPDIR" "0,1" endif sif (cpuis("STM32MP157*")) bitfld.long 0x4 15. "EPDIR,EPDIR" "0,1" newline endif hexmask.long.byte 0x4 11.--14. 1. "EPNUM,Endpoint number" hexmask.long.word 0x4 0.--10. 1. "MPSIZ,Maximum packet size" line.long 0x8 "OTG_HCSPLT4," bitfld.long 0x8 31. "SPLITEN,Split enable" "0,1" bitfld.long 0x8 16. "COMPLSPLT,Do complete split" "0,1" newline sif (cpuis("STM32MP13*")) bitfld.long 0x8 14.--15. "XACTPOS,Transaction position" "0: Mid. This is the middle payload of this..,1: End. This is the last payload of this..,2: Begin. This is the first data payload of this..,3: All. This is the entire data payload of this.." endif sif (cpuis("STM32MP151*")) bitfld.long 0x8 14.--15. "XACTPOS,XACTPOS" "0,1,2,3" newline endif sif (cpuis("STM32MP153*")) bitfld.long 0x8 14.--15. "XACTPOS,XACTPOS" "0,1,2,3" endif sif (cpuis("STM32MP157*")) bitfld.long 0x8 14.--15. "XACTPOS,XACTPOS" "0,1,2,3" newline endif hexmask.long.byte 0x8 7.--13. 1. "HUBADDR,Hub address" hexmask.long.byte 0x8 0.--6. 1. "PRTADDR,Port address" line.long 0xC "OTG_HCINT4,OTG host channel 4 interrupt register" bitfld.long 0xC 13. "DESCLSTROLL,Descriptor rollover interrupt." "0,1" bitfld.long 0xC 12. "XCSXACTERR,Excessive transaction error." "0,1" newline bitfld.long 0xC 11. "BNA,Buffer not available interrupt." "0,1" bitfld.long 0xC 10. "DTERR,Data toggle error. In Scatter/Gather DMA mode the interrupt due to this bit is masked." "0,1" newline bitfld.long 0xC 9. "FRMOR,Frame overrun. In Scatter/Gather DMA mode the interrupt due to this bit is masked." "0,1" bitfld.long 0xC 8. "BBERR,Babble error. In Scatter/Gather DMA mode the interrupt due to this bit is masked." "0,1" newline bitfld.long 0xC 7. "TXERR,Transaction error. In Scatter/Gather DMA mode the interrupt due to this bit is masked." "0,1" bitfld.long 0xC 6. "NYET,Not yet ready response received interrupt. In Scatter/Gather DMA mode the interrupt due to this bit is masked." "0,1" newline bitfld.long 0xC 5. "ACK,ACK response received/transmitted interrupt. In Scatter/Gather DMA mode the interrupt due to this bit is masked." "0,1" bitfld.long 0xC 4. "NAK,NAK response received interrupt. In Scatter/Gather DMA mode the interrupt due to this bit is masked." "0,1" newline bitfld.long 0xC 3. "STALL,STALL response received interrupt. In Scatter/Gather DMA mode the interrupt due to this bit is masked." "0,1" bitfld.long 0xC 2. "AHBERR,AHB error" "0,1" newline bitfld.long 0xC 1. "CHH,Channel halted." "0,1" bitfld.long 0xC 0. "XFRC,Transfer completed." "0,1" line.long 0x10 "OTG_HCINTMSK4,OTG host channel 4 interrupt mask register" bitfld.long 0x10 13. "DESCLSTROLLMSK,Descriptor rollover interrupt mask register." "0,1" bitfld.long 0x10 11. "BNAMSK,Buffer not available interrupt mask register." "0,1" newline sif (cpuis("STM32MP13*")) bitfld.long 0x10 10. "DTERRM,Data toggle error mask. In Scatter/Gather DMA mode the interrupt due to this bit is masked." "0: Masked interrupt,1: Unmasked interrupt" bitfld.long 0x10 9. "FRMORM,Frame overrun mask. In Scatter/Gather DMA mode the interrupt due to this bit is masked." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x10 8. "BBERRM,Babble error mask. In Scatter/Gather DMA mode the interrupt due to this bit is masked." "0: Masked interrupt,1: Unmasked interrupt" bitfld.long 0x10 7. "TXERRM,Transaction error mask. In Scatter/Gather DMA mode the interrupt due to this bit is masked." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x10 6. "NYET,response received interrupt mask. In Scatter/Gather DMA mode the interrupt due to this bit is masked." "0: Masked interrupt,1: Unmasked interrupt" bitfld.long 0x10 5. "ACKM,ACK response received/transmitted interrupt mask. In Scatter/Gather DMA mode the interrupt due to this bit is masked." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x10 4. "NAKM,NAK response received interrupt mask. In Scatter/Gather DMA mode the interrupt due to this bit is masked." "0: Masked interrupt,1: Unmasked interrupt" bitfld.long 0x10 3. "STALLM,STALL response received interrupt mask. In Scatter/Gather DMA mode the interrupt due to this bit is masked." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x10 2. "AHBERRM,AHB error. In scatter/gather DMA mode for host interrupts will not be generated due to the corresponding bits set in OTG_HCINTx." "0: Masked interrupt,1: Unmasked interrupt" bitfld.long 0x10 1. "CHHM,Channel halted mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x10 0. "XFRCM,Transfer completed mask" "0: Masked interrupt,1: Unmasked interrupt" endif sif (cpuis("STM32MP151*")) bitfld.long 0x10 10. "DTERRM,DTERRM" "0,1" newline bitfld.long 0x10 9. "FRMORM,FRMORM" "0,1" bitfld.long 0x10 8. "BBERRM,BBERRM" "0,1" newline bitfld.long 0x10 7. "TXERRM,TXERRM" "0,1" bitfld.long 0x10 6. "NYET,NYET" "0,1" newline bitfld.long 0x10 5. "ACKM,ACKM" "0,1" bitfld.long 0x10 4. "NAKM,NAKM" "0,1" newline bitfld.long 0x10 3. "STALLM,STALLM" "0,1" bitfld.long 0x10 2. "AHBERRM,AHBERRM" "0,1" newline bitfld.long 0x10 1. "CHHM,CHHM" "0,1" endif sif (cpuis("STM32MP153*")) bitfld.long 0x10 10. "DTERRM,DTERRM" "0,1" newline bitfld.long 0x10 9. "FRMORM,FRMORM" "0,1" bitfld.long 0x10 8. "BBERRM,BBERRM" "0,1" newline bitfld.long 0x10 7. "TXERRM,TXERRM" "0,1" bitfld.long 0x10 6. "NYET,NYET" "0,1" newline bitfld.long 0x10 5. "ACKM,ACKM" "0,1" bitfld.long 0x10 4. "NAKM,NAKM" "0,1" newline bitfld.long 0x10 3. "STALLM,STALLM" "0,1" bitfld.long 0x10 2. "AHBERRM,AHBERRM" "0,1" newline bitfld.long 0x10 1. "CHHM,CHHM" "0,1" bitfld.long 0x10 0. "XFRCM,XFRCM" "0,1" newline endif sif (cpuis("STM32MP157*")) bitfld.long 0x10 10. "DTERRM,DTERRM" "0,1" bitfld.long 0x10 9. "FRMORM,FRMORM" "0,1" newline bitfld.long 0x10 8. "BBERRM,BBERRM" "0,1" bitfld.long 0x10 7. "TXERRM,TXERRM" "0,1" newline bitfld.long 0x10 6. "NYET,NYET" "0,1" bitfld.long 0x10 5. "ACKM,ACKM" "0,1" newline bitfld.long 0x10 4. "NAKM,NAKM" "0,1" bitfld.long 0x10 3. "STALLM,STALLM" "0,1" newline bitfld.long 0x10 2. "AHBERRM,AHBERRM" "0,1" bitfld.long 0x10 1. "CHHM,CHHM" "0,1" newline bitfld.long 0x10 0. "XFRCM,XFRCM" "0,1" endif line.long 0x14 "OTG_HCTSIZ4," sif (cpuis("STM32MP13*")) bitfld.long 0x14 31. "DOPNG,Do Ping" "0,1" bitfld.long 0x14 29.--30. "DPID,Data PID" "0: DATA0,1: DATA2,2: DATA1,3: SETUP (control) / MDATA (non-control)" newline endif sif (cpuis("STM32MP151*")) bitfld.long 0x14 29.--30. "DPID,DPID" "0,1,2,3" endif sif (cpuis("STM32MP153*")) bitfld.long 0x14 29.--30. "DPID,DPID" "0,1,2,3" newline endif sif (cpuis("STM32MP157*")) bitfld.long 0x14 29.--30. "DPID,DPID" "0,1,2,3" endif hexmask.long.word 0x14 19.--28. 1. "PKTCNT,Packet count" newline hexmask.long.tbyte 0x14 0.--18. 1. "XFRSIZ,Transfer size" line.long 0x18 "OTG_HCDMA4," hexmask.long 0x18 0.--31. 1. "DMAADDR,DMA address" group.long 0x59C++0x1B line.long 0x0 "OTG_HCDMAB4," sif (cpuis("STM32MP13*")) hexmask.long 0x0 0.--31. 1. "HCDMAB,DMA address" endif sif (cpuis("STM32MP151*")) hexmask.long 0x0 0.--31. 1. "HCDMAB,HCDMAB" newline endif sif (cpuis("STM32MP153*")) hexmask.long 0x0 0.--31. 1. "HCDMAB,HCDMAB" endif sif (cpuis("STM32MP157*")) hexmask.long 0x0 0.--31. 1. "HCDMAB,HCDMAB" endif line.long 0x4 "OTG_HCCHAR5," sif (cpuis("STM32MP13*")) bitfld.long 0x4 31. "CHENA,Channel enable" "0: Indicates that the descriptor structure is not..,1: Indicates that the descriptor structure and data.." bitfld.long 0x4 29. "ODDFRM,Odd frame" "0: Even frame,1: Odd frame" newline bitfld.long 0x4 20.--21. "MCNT,Multicount" "0: Reserved. This field yields undefined results,1: 1 transaction,2: 2 transactions per frame to be issued for this..,3: 3 transactions per frame to be issued for this.." bitfld.long 0x4 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt" newline bitfld.long 0x4 15. "EPDIR,Endpoint direction" "0: OUT,1: IN" endif sif (cpuis("STM32MP151*")) bitfld.long 0x4 31. "CHENA,CHENA" "0,1" newline endif sif (cpuis("STM32MP153*")) bitfld.long 0x4 31. "CHENA,CHENA" "0,1" endif sif (cpuis("STM32MP157*")) bitfld.long 0x4 31. "CHENA,CHENA" "0,1" newline endif bitfld.long 0x4 30. "CHDIS,Channel disable" "0,1" hexmask.long.byte 0x4 22.--28. 1. "DAD,Device address" newline sif (cpuis("STM32MP151*")) bitfld.long 0x4 20.--21. "MCNT,MCNT" "0,1,2,3" bitfld.long 0x4 18.--19. "EPTYP,EPTYP" "0,1,2,3" newline endif sif (cpuis("STM32MP153*")) bitfld.long 0x4 20.--21. "MCNT,MCNT" "0,1,2,3" bitfld.long 0x4 18.--19. "EPTYP,EPTYP" "0,1,2,3" newline endif sif (cpuis("STM32MP157*")) bitfld.long 0x4 20.--21. "MCNT,MCNT" "0,1,2,3" bitfld.long 0x4 18.--19. "EPTYP,EPTYP" "0,1,2,3" newline endif bitfld.long 0x4 17. "LSDEV,Low-speed device" "0,1" sif (cpuis("STM32MP151*")) bitfld.long 0x4 15. "EPDIR,EPDIR" "0,1" newline endif sif (cpuis("STM32MP153*")) bitfld.long 0x4 15. "EPDIR,EPDIR" "0,1" endif sif (cpuis("STM32MP157*")) bitfld.long 0x4 15. "EPDIR,EPDIR" "0,1" newline endif hexmask.long.byte 0x4 11.--14. 1. "EPNUM,Endpoint number" hexmask.long.word 0x4 0.--10. 1. "MPSIZ,Maximum packet size" line.long 0x8 "OTG_HCSPLT5," bitfld.long 0x8 31. "SPLITEN,Split enable" "0,1" bitfld.long 0x8 16. "COMPLSPLT,Do complete split" "0,1" newline sif (cpuis("STM32MP13*")) bitfld.long 0x8 14.--15. "XACTPOS,Transaction position" "0: Mid. This is the middle payload of this..,1: End. This is the last payload of this..,2: Begin. This is the first data payload of this..,3: All. This is the entire data payload of this.." endif sif (cpuis("STM32MP151*")) bitfld.long 0x8 14.--15. "XACTPOS,XACTPOS" "0,1,2,3" newline endif sif (cpuis("STM32MP153*")) bitfld.long 0x8 14.--15. "XACTPOS,XACTPOS" "0,1,2,3" endif sif (cpuis("STM32MP157*")) bitfld.long 0x8 14.--15. "XACTPOS,XACTPOS" "0,1,2,3" newline endif hexmask.long.byte 0x8 7.--13. 1. "HUBADDR,Hub address" hexmask.long.byte 0x8 0.--6. 1. "PRTADDR,Port address" line.long 0xC "OTG_HCINT5,OTG host channel 5 interrupt register" bitfld.long 0xC 13. "DESCLSTROLL,Descriptor rollover interrupt." "0,1" bitfld.long 0xC 12. "XCSXACTERR,Excessive transaction error." "0,1" newline bitfld.long 0xC 11. "BNA,Buffer not available interrupt." "0,1" bitfld.long 0xC 10. "DTERR,Data toggle error. In Scatter/Gather DMA mode the interrupt due to this bit is masked." "0,1" newline bitfld.long 0xC 9. "FRMOR,Frame overrun. In Scatter/Gather DMA mode the interrupt due to this bit is masked." "0,1" bitfld.long 0xC 8. "BBERR,Babble error. In Scatter/Gather DMA mode the interrupt due to this bit is masked." "0,1" newline bitfld.long 0xC 7. "TXERR,Transaction error. In Scatter/Gather DMA mode the interrupt due to this bit is masked." "0,1" bitfld.long 0xC 6. "NYET,Not yet ready response received interrupt. In Scatter/Gather DMA mode the interrupt due to this bit is masked." "0,1" newline bitfld.long 0xC 5. "ACK,ACK response received/transmitted interrupt. In Scatter/Gather DMA mode the interrupt due to this bit is masked." "0,1" bitfld.long 0xC 4. "NAK,NAK response received interrupt. In Scatter/Gather DMA mode the interrupt due to this bit is masked." "0,1" newline bitfld.long 0xC 3. "STALL,STALL response received interrupt. In Scatter/Gather DMA mode the interrupt due to this bit is masked." "0,1" bitfld.long 0xC 2. "AHBERR,AHB error" "0,1" newline bitfld.long 0xC 1. "CHH,Channel halted." "0,1" bitfld.long 0xC 0. "XFRC,Transfer completed." "0,1" line.long 0x10 "OTG_HCINTMSK5,OTG host channel 5 interrupt mask register" bitfld.long 0x10 13. "DESCLSTROLLMSK,Descriptor rollover interrupt mask register." "0,1" bitfld.long 0x10 11. "BNAMSK,Buffer not available interrupt mask register." "0,1" newline sif (cpuis("STM32MP13*")) bitfld.long 0x10 10. "DTERRM,Data toggle error mask. In Scatter/Gather DMA mode the interrupt due to this bit is masked." "0: Masked interrupt,1: Unmasked interrupt" bitfld.long 0x10 9. "FRMORM,Frame overrun mask. In Scatter/Gather DMA mode the interrupt due to this bit is masked." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x10 8. "BBERRM,Babble error mask. In Scatter/Gather DMA mode the interrupt due to this bit is masked." "0: Masked interrupt,1: Unmasked interrupt" bitfld.long 0x10 7. "TXERRM,Transaction error mask. In Scatter/Gather DMA mode the interrupt due to this bit is masked." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x10 6. "NYET,response received interrupt mask. In Scatter/Gather DMA mode the interrupt due to this bit is masked." "0: Masked interrupt,1: Unmasked interrupt" bitfld.long 0x10 5. "ACKM,ACK response received/transmitted interrupt mask. In Scatter/Gather DMA mode the interrupt due to this bit is masked." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x10 4. "NAKM,NAK response received interrupt mask. In Scatter/Gather DMA mode the interrupt due to this bit is masked." "0: Masked interrupt,1: Unmasked interrupt" bitfld.long 0x10 3. "STALLM,STALL response received interrupt mask. In Scatter/Gather DMA mode the interrupt due to this bit is masked." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x10 2. "AHBERRM,AHB error. In scatter/gather DMA mode for host interrupts will not be generated due to the corresponding bits set in OTG_HCINTx." "0: Masked interrupt,1: Unmasked interrupt" bitfld.long 0x10 1. "CHHM,Channel halted mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x10 0. "XFRCM,Transfer completed mask" "0: Masked interrupt,1: Unmasked interrupt" endif sif (cpuis("STM32MP151*")) bitfld.long 0x10 10. "DTERRM,DTERRM" "0,1" newline bitfld.long 0x10 9. "FRMORM,FRMORM" "0,1" bitfld.long 0x10 8. "BBERRM,BBERRM" "0,1" newline bitfld.long 0x10 7. "TXERRM,TXERRM" "0,1" bitfld.long 0x10 6. "NYET,NYET" "0,1" newline bitfld.long 0x10 5. "ACKM,ACKM" "0,1" bitfld.long 0x10 4. "NAKM,NAKM" "0,1" newline bitfld.long 0x10 3. "STALLM,STALLM" "0,1" bitfld.long 0x10 2. "AHBERRM,AHBERRM" "0,1" newline bitfld.long 0x10 1. "CHHM,CHHM" "0,1" endif sif (cpuis("STM32MP153*")) bitfld.long 0x10 10. "DTERRM,DTERRM" "0,1" newline bitfld.long 0x10 9. "FRMORM,FRMORM" "0,1" bitfld.long 0x10 8. "BBERRM,BBERRM" "0,1" newline bitfld.long 0x10 7. "TXERRM,TXERRM" "0,1" bitfld.long 0x10 6. "NYET,NYET" "0,1" newline bitfld.long 0x10 5. "ACKM,ACKM" "0,1" bitfld.long 0x10 4. "NAKM,NAKM" "0,1" newline bitfld.long 0x10 3. "STALLM,STALLM" "0,1" bitfld.long 0x10 2. "AHBERRM,AHBERRM" "0,1" newline bitfld.long 0x10 1. "CHHM,CHHM" "0,1" bitfld.long 0x10 0. "XFRCM,XFRCM" "0,1" newline endif sif (cpuis("STM32MP157*")) bitfld.long 0x10 10. "DTERRM,DTERRM" "0,1" bitfld.long 0x10 9. "FRMORM,FRMORM" "0,1" newline bitfld.long 0x10 8. "BBERRM,BBERRM" "0,1" bitfld.long 0x10 7. "TXERRM,TXERRM" "0,1" newline bitfld.long 0x10 6. "NYET,NYET" "0,1" bitfld.long 0x10 5. "ACKM,ACKM" "0,1" newline bitfld.long 0x10 4. "NAKM,NAKM" "0,1" bitfld.long 0x10 3. "STALLM,STALLM" "0,1" newline bitfld.long 0x10 2. "AHBERRM,AHBERRM" "0,1" bitfld.long 0x10 1. "CHHM,CHHM" "0,1" newline bitfld.long 0x10 0. "XFRCM,XFRCM" "0,1" endif line.long 0x14 "OTG_HCTSIZ5," sif (cpuis("STM32MP13*")) bitfld.long 0x14 31. "DOPNG,Do Ping" "0,1" bitfld.long 0x14 29.--30. "DPID,Data PID" "0: DATA0,1: DATA2,2: DATA1,3: SETUP (control) / MDATA (non-control)" newline endif sif (cpuis("STM32MP151*")) bitfld.long 0x14 29.--30. "DPID,DPID" "0,1,2,3" endif sif (cpuis("STM32MP153*")) bitfld.long 0x14 29.--30. "DPID,DPID" "0,1,2,3" newline endif sif (cpuis("STM32MP157*")) bitfld.long 0x14 29.--30. "DPID,DPID" "0,1,2,3" endif hexmask.long.word 0x14 19.--28. 1. "PKTCNT,Packet count" newline hexmask.long.tbyte 0x14 0.--18. 1. "XFRSIZ,Transfer size" line.long 0x18 "OTG_HCDMA5," hexmask.long 0x18 0.--31. 1. "DMAADDR,DMA address" group.long 0x5BC++0x1B line.long 0x0 "OTG_HCDMAB5," sif (cpuis("STM32MP13*")) hexmask.long 0x0 0.--31. 1. "HCDMAB,DMA address" endif sif (cpuis("STM32MP151*")) hexmask.long 0x0 0.--31. 1. "HCDMAB,HCDMAB" newline endif sif (cpuis("STM32MP153*")) hexmask.long 0x0 0.--31. 1. "HCDMAB,HCDMAB" endif sif (cpuis("STM32MP157*")) hexmask.long 0x0 0.--31. 1. "HCDMAB,HCDMAB" endif line.long 0x4 "OTG_HCCHAR6," sif (cpuis("STM32MP13*")) bitfld.long 0x4 31. "CHENA,Channel enable" "0: Indicates that the descriptor structure is not..,1: Indicates that the descriptor structure and data.." bitfld.long 0x4 29. "ODDFRM,Odd frame" "0: Even frame,1: Odd frame" newline bitfld.long 0x4 20.--21. "MCNT,Multicount" "0: Reserved. This field yields undefined results,1: 1 transaction,2: 2 transactions per frame to be issued for this..,3: 3 transactions per frame to be issued for this.." bitfld.long 0x4 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt" newline bitfld.long 0x4 15. "EPDIR,Endpoint direction" "0: OUT,1: IN" endif sif (cpuis("STM32MP151*")) bitfld.long 0x4 31. "CHENA,CHENA" "0,1" newline endif sif (cpuis("STM32MP153*")) bitfld.long 0x4 31. "CHENA,CHENA" "0,1" endif sif (cpuis("STM32MP157*")) bitfld.long 0x4 31. "CHENA,CHENA" "0,1" newline endif bitfld.long 0x4 30. "CHDIS,Channel disable" "0,1" hexmask.long.byte 0x4 22.--28. 1. "DAD,Device address" newline sif (cpuis("STM32MP151*")) bitfld.long 0x4 20.--21. "MCNT,MCNT" "0,1,2,3" bitfld.long 0x4 18.--19. "EPTYP,EPTYP" "0,1,2,3" newline endif sif (cpuis("STM32MP153*")) bitfld.long 0x4 20.--21. "MCNT,MCNT" "0,1,2,3" bitfld.long 0x4 18.--19. "EPTYP,EPTYP" "0,1,2,3" newline endif sif (cpuis("STM32MP157*")) bitfld.long 0x4 20.--21. "MCNT,MCNT" "0,1,2,3" bitfld.long 0x4 18.--19. "EPTYP,EPTYP" "0,1,2,3" newline endif bitfld.long 0x4 17. "LSDEV,Low-speed device" "0,1" sif (cpuis("STM32MP151*")) bitfld.long 0x4 15. "EPDIR,EPDIR" "0,1" newline endif sif (cpuis("STM32MP153*")) bitfld.long 0x4 15. "EPDIR,EPDIR" "0,1" endif sif (cpuis("STM32MP157*")) bitfld.long 0x4 15. "EPDIR,EPDIR" "0,1" newline endif hexmask.long.byte 0x4 11.--14. 1. "EPNUM,Endpoint number" hexmask.long.word 0x4 0.--10. 1. "MPSIZ,Maximum packet size" line.long 0x8 "OTG_HCSPLT6," bitfld.long 0x8 31. "SPLITEN,Split enable" "0,1" bitfld.long 0x8 16. "COMPLSPLT,Do complete split" "0,1" newline sif (cpuis("STM32MP13*")) bitfld.long 0x8 14.--15. "XACTPOS,Transaction position" "0: Mid. This is the middle payload of this..,1: End. This is the last payload of this..,2: Begin. This is the first data payload of this..,3: All. This is the entire data payload of this.." endif sif (cpuis("STM32MP151*")) bitfld.long 0x8 14.--15. "XACTPOS,XACTPOS" "0,1,2,3" newline endif sif (cpuis("STM32MP153*")) bitfld.long 0x8 14.--15. "XACTPOS,XACTPOS" "0,1,2,3" endif sif (cpuis("STM32MP157*")) bitfld.long 0x8 14.--15. "XACTPOS,XACTPOS" "0,1,2,3" newline endif hexmask.long.byte 0x8 7.--13. 1. "HUBADDR,Hub address" hexmask.long.byte 0x8 0.--6. 1. "PRTADDR,Port address" line.long 0xC "OTG_HCINT6,OTG host channel 6 interrupt register" bitfld.long 0xC 13. "DESCLSTROLL,Descriptor rollover interrupt." "0,1" bitfld.long 0xC 12. "XCSXACTERR,Excessive transaction error." "0,1" newline bitfld.long 0xC 11. "BNA,Buffer not available interrupt." "0,1" bitfld.long 0xC 10. "DTERR,Data toggle error. In Scatter/Gather DMA mode the interrupt due to this bit is masked." "0,1" newline bitfld.long 0xC 9. "FRMOR,Frame overrun. In Scatter/Gather DMA mode the interrupt due to this bit is masked." "0,1" bitfld.long 0xC 8. "BBERR,Babble error. In Scatter/Gather DMA mode the interrupt due to this bit is masked." "0,1" newline bitfld.long 0xC 7. "TXERR,Transaction error. In Scatter/Gather DMA mode the interrupt due to this bit is masked." "0,1" bitfld.long 0xC 6. "NYET,Not yet ready response received interrupt. In Scatter/Gather DMA mode the interrupt due to this bit is masked." "0,1" newline bitfld.long 0xC 5. "ACK,ACK response received/transmitted interrupt. In Scatter/Gather DMA mode the interrupt due to this bit is masked." "0,1" bitfld.long 0xC 4. "NAK,NAK response received interrupt. In Scatter/Gather DMA mode the interrupt due to this bit is masked." "0,1" newline bitfld.long 0xC 3. "STALL,STALL response received interrupt. In Scatter/Gather DMA mode the interrupt due to this bit is masked." "0,1" bitfld.long 0xC 2. "AHBERR,AHB error" "0,1" newline bitfld.long 0xC 1. "CHH,Channel halted." "0,1" bitfld.long 0xC 0. "XFRC,Transfer completed." "0,1" line.long 0x10 "OTG_HCINTMSK6,OTG host channel 6 interrupt mask register" bitfld.long 0x10 13. "DESCLSTROLLMSK,Descriptor rollover interrupt mask register." "0,1" bitfld.long 0x10 11. "BNAMSK,Buffer not available interrupt mask register." "0,1" newline sif (cpuis("STM32MP13*")) bitfld.long 0x10 10. "DTERRM,Data toggle error mask. In Scatter/Gather DMA mode the interrupt due to this bit is masked." "0: Masked interrupt,1: Unmasked interrupt" bitfld.long 0x10 9. "FRMORM,Frame overrun mask. In Scatter/Gather DMA mode the interrupt due to this bit is masked." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x10 8. "BBERRM,Babble error mask. In Scatter/Gather DMA mode the interrupt due to this bit is masked." "0: Masked interrupt,1: Unmasked interrupt" bitfld.long 0x10 7. "TXERRM,Transaction error mask. In Scatter/Gather DMA mode the interrupt due to this bit is masked." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x10 6. "NYET,response received interrupt mask. In Scatter/Gather DMA mode the interrupt due to this bit is masked." "0: Masked interrupt,1: Unmasked interrupt" bitfld.long 0x10 5. "ACKM,ACK response received/transmitted interrupt mask. In Scatter/Gather DMA mode the interrupt due to this bit is masked." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x10 4. "NAKM,NAK response received interrupt mask. In Scatter/Gather DMA mode the interrupt due to this bit is masked." "0: Masked interrupt,1: Unmasked interrupt" bitfld.long 0x10 3. "STALLM,STALL response received interrupt mask. In Scatter/Gather DMA mode the interrupt due to this bit is masked." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x10 2. "AHBERRM,AHB error. In scatter/gather DMA mode for host interrupts will not be generated due to the corresponding bits set in OTG_HCINTx." "0: Masked interrupt,1: Unmasked interrupt" bitfld.long 0x10 1. "CHHM,Channel halted mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x10 0. "XFRCM,Transfer completed mask" "0: Masked interrupt,1: Unmasked interrupt" endif sif (cpuis("STM32MP151*")) bitfld.long 0x10 10. "DTERRM,DTERRM" "0,1" newline bitfld.long 0x10 9. "FRMORM,FRMORM" "0,1" bitfld.long 0x10 8. "BBERRM,BBERRM" "0,1" newline bitfld.long 0x10 7. "TXERRM,TXERRM" "0,1" bitfld.long 0x10 6. "NYET,NYET" "0,1" newline bitfld.long 0x10 5. "ACKM,ACKM" "0,1" bitfld.long 0x10 4. "NAKM,NAKM" "0,1" newline bitfld.long 0x10 3. "STALLM,STALLM" "0,1" bitfld.long 0x10 2. "AHBERRM,AHBERRM" "0,1" newline bitfld.long 0x10 1. "CHHM,CHHM" "0,1" endif sif (cpuis("STM32MP153*")) bitfld.long 0x10 10. "DTERRM,DTERRM" "0,1" newline bitfld.long 0x10 9. "FRMORM,FRMORM" "0,1" bitfld.long 0x10 8. "BBERRM,BBERRM" "0,1" newline bitfld.long 0x10 7. "TXERRM,TXERRM" "0,1" bitfld.long 0x10 6. "NYET,NYET" "0,1" newline bitfld.long 0x10 5. "ACKM,ACKM" "0,1" bitfld.long 0x10 4. "NAKM,NAKM" "0,1" newline bitfld.long 0x10 3. "STALLM,STALLM" "0,1" bitfld.long 0x10 2. "AHBERRM,AHBERRM" "0,1" newline bitfld.long 0x10 1. "CHHM,CHHM" "0,1" bitfld.long 0x10 0. "XFRCM,XFRCM" "0,1" newline endif sif (cpuis("STM32MP157*")) bitfld.long 0x10 10. "DTERRM,DTERRM" "0,1" bitfld.long 0x10 9. "FRMORM,FRMORM" "0,1" newline bitfld.long 0x10 8. "BBERRM,BBERRM" "0,1" bitfld.long 0x10 7. "TXERRM,TXERRM" "0,1" newline bitfld.long 0x10 6. "NYET,NYET" "0,1" bitfld.long 0x10 5. "ACKM,ACKM" "0,1" newline bitfld.long 0x10 4. "NAKM,NAKM" "0,1" bitfld.long 0x10 3. "STALLM,STALLM" "0,1" newline bitfld.long 0x10 2. "AHBERRM,AHBERRM" "0,1" bitfld.long 0x10 1. "CHHM,CHHM" "0,1" newline bitfld.long 0x10 0. "XFRCM,XFRCM" "0,1" endif line.long 0x14 "OTG_HCTSIZ6," sif (cpuis("STM32MP13*")) bitfld.long 0x14 31. "DOPNG,Do Ping" "0,1" bitfld.long 0x14 29.--30. "DPID,Data PID" "0: DATA0,1: DATA2,2: DATA1,3: SETUP (control) / MDATA (non-control)" newline endif sif (cpuis("STM32MP151*")) bitfld.long 0x14 29.--30. "DPID,DPID" "0,1,2,3" endif sif (cpuis("STM32MP153*")) bitfld.long 0x14 29.--30. "DPID,DPID" "0,1,2,3" newline endif sif (cpuis("STM32MP157*")) bitfld.long 0x14 29.--30. "DPID,DPID" "0,1,2,3" endif hexmask.long.word 0x14 19.--28. 1. "PKTCNT,Packet count" newline hexmask.long.tbyte 0x14 0.--18. 1. "XFRSIZ,Transfer size" line.long 0x18 "OTG_HCDMA6," hexmask.long 0x18 0.--31. 1. "DMAADDR,DMA address" group.long 0x5DC++0x1B line.long 0x0 "OTG_HCDMAB6," sif (cpuis("STM32MP13*")) hexmask.long 0x0 0.--31. 1. "HCDMAB,DMA address" endif sif (cpuis("STM32MP151*")) hexmask.long 0x0 0.--31. 1. "HCDMAB,HCDMAB" newline endif sif (cpuis("STM32MP153*")) hexmask.long 0x0 0.--31. 1. "HCDMAB,HCDMAB" endif sif (cpuis("STM32MP157*")) hexmask.long 0x0 0.--31. 1. "HCDMAB,HCDMAB" endif line.long 0x4 "OTG_HCCHAR7," sif (cpuis("STM32MP13*")) bitfld.long 0x4 31. "CHENA,Channel enable" "0: Indicates that the descriptor structure is not..,1: Indicates that the descriptor structure and data.." bitfld.long 0x4 29. "ODDFRM,Odd frame" "0: Even frame,1: Odd frame" newline bitfld.long 0x4 20.--21. "MCNT,Multicount" "0: Reserved. This field yields undefined results,1: 1 transaction,2: 2 transactions per frame to be issued for this..,3: 3 transactions per frame to be issued for this.." bitfld.long 0x4 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt" newline bitfld.long 0x4 15. "EPDIR,Endpoint direction" "0: OUT,1: IN" endif sif (cpuis("STM32MP151*")) bitfld.long 0x4 31. "CHENA,CHENA" "0,1" newline endif sif (cpuis("STM32MP153*")) bitfld.long 0x4 31. "CHENA,CHENA" "0,1" endif sif (cpuis("STM32MP157*")) bitfld.long 0x4 31. "CHENA,CHENA" "0,1" newline endif bitfld.long 0x4 30. "CHDIS,Channel disable" "0,1" hexmask.long.byte 0x4 22.--28. 1. "DAD,Device address" newline sif (cpuis("STM32MP151*")) bitfld.long 0x4 20.--21. "MCNT,MCNT" "0,1,2,3" bitfld.long 0x4 18.--19. "EPTYP,EPTYP" "0,1,2,3" newline endif sif (cpuis("STM32MP153*")) bitfld.long 0x4 20.--21. "MCNT,MCNT" "0,1,2,3" bitfld.long 0x4 18.--19. "EPTYP,EPTYP" "0,1,2,3" newline endif sif (cpuis("STM32MP157*")) bitfld.long 0x4 20.--21. "MCNT,MCNT" "0,1,2,3" bitfld.long 0x4 18.--19. "EPTYP,EPTYP" "0,1,2,3" newline endif bitfld.long 0x4 17. "LSDEV,Low-speed device" "0,1" sif (cpuis("STM32MP151*")) bitfld.long 0x4 15. "EPDIR,EPDIR" "0,1" newline endif sif (cpuis("STM32MP153*")) bitfld.long 0x4 15. "EPDIR,EPDIR" "0,1" endif sif (cpuis("STM32MP157*")) bitfld.long 0x4 15. "EPDIR,EPDIR" "0,1" newline endif hexmask.long.byte 0x4 11.--14. 1. "EPNUM,Endpoint number" hexmask.long.word 0x4 0.--10. 1. "MPSIZ,Maximum packet size" line.long 0x8 "OTG_HCSPLT7," bitfld.long 0x8 31. "SPLITEN,Split enable" "0,1" bitfld.long 0x8 16. "COMPLSPLT,Do complete split" "0,1" newline sif (cpuis("STM32MP13*")) bitfld.long 0x8 14.--15. "XACTPOS,Transaction position" "0: Mid. This is the middle payload of this..,1: End. This is the last payload of this..,2: Begin. This is the first data payload of this..,3: All. This is the entire data payload of this.." endif sif (cpuis("STM32MP151*")) bitfld.long 0x8 14.--15. "XACTPOS,XACTPOS" "0,1,2,3" newline endif sif (cpuis("STM32MP153*")) bitfld.long 0x8 14.--15. "XACTPOS,XACTPOS" "0,1,2,3" endif sif (cpuis("STM32MP157*")) bitfld.long 0x8 14.--15. "XACTPOS,XACTPOS" "0,1,2,3" newline endif hexmask.long.byte 0x8 7.--13. 1. "HUBADDR,Hub address" hexmask.long.byte 0x8 0.--6. 1. "PRTADDR,Port address" line.long 0xC "OTG_HCINT7,OTG host channel 7 interrupt register" bitfld.long 0xC 13. "DESCLSTROLL,Descriptor rollover interrupt." "0,1" bitfld.long 0xC 12. "XCSXACTERR,Excessive transaction error." "0,1" newline bitfld.long 0xC 11. "BNA,Buffer not available interrupt." "0,1" bitfld.long 0xC 10. "DTERR,Data toggle error. In Scatter/Gather DMA mode the interrupt due to this bit is masked." "0,1" newline bitfld.long 0xC 9. "FRMOR,Frame overrun. In Scatter/Gather DMA mode the interrupt due to this bit is masked." "0,1" bitfld.long 0xC 8. "BBERR,Babble error. In Scatter/Gather DMA mode the interrupt due to this bit is masked." "0,1" newline bitfld.long 0xC 7. "TXERR,Transaction error. In Scatter/Gather DMA mode the interrupt due to this bit is masked." "0,1" bitfld.long 0xC 6. "NYET,Not yet ready response received interrupt. In Scatter/Gather DMA mode the interrupt due to this bit is masked." "0,1" newline bitfld.long 0xC 5. "ACK,ACK response received/transmitted interrupt. In Scatter/Gather DMA mode the interrupt due to this bit is masked." "0,1" bitfld.long 0xC 4. "NAK,NAK response received interrupt. In Scatter/Gather DMA mode the interrupt due to this bit is masked." "0,1" newline bitfld.long 0xC 3. "STALL,STALL response received interrupt. In Scatter/Gather DMA mode the interrupt due to this bit is masked." "0,1" bitfld.long 0xC 2. "AHBERR,AHB error" "0,1" newline bitfld.long 0xC 1. "CHH,Channel halted." "0,1" bitfld.long 0xC 0. "XFRC,Transfer completed." "0,1" line.long 0x10 "OTG_HCINTMSK7,OTG host channel 7 interrupt mask register" bitfld.long 0x10 13. "DESCLSTROLLMSK,Descriptor rollover interrupt mask register." "0,1" bitfld.long 0x10 11. "BNAMSK,Buffer not available interrupt mask register." "0,1" newline sif (cpuis("STM32MP13*")) bitfld.long 0x10 10. "DTERRM,Data toggle error mask. In Scatter/Gather DMA mode the interrupt due to this bit is masked." "0: Masked interrupt,1: Unmasked interrupt" bitfld.long 0x10 9. "FRMORM,Frame overrun mask. In Scatter/Gather DMA mode the interrupt due to this bit is masked." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x10 8. "BBERRM,Babble error mask. In Scatter/Gather DMA mode the interrupt due to this bit is masked." "0: Masked interrupt,1: Unmasked interrupt" bitfld.long 0x10 7. "TXERRM,Transaction error mask. In Scatter/Gather DMA mode the interrupt due to this bit is masked." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x10 6. "NYET,response received interrupt mask. In Scatter/Gather DMA mode the interrupt due to this bit is masked." "0: Masked interrupt,1: Unmasked interrupt" bitfld.long 0x10 5. "ACKM,ACK response received/transmitted interrupt mask. In Scatter/Gather DMA mode the interrupt due to this bit is masked." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x10 4. "NAKM,NAK response received interrupt mask. In Scatter/Gather DMA mode the interrupt due to this bit is masked." "0: Masked interrupt,1: Unmasked interrupt" bitfld.long 0x10 3. "STALLM,STALL response received interrupt mask. In Scatter/Gather DMA mode the interrupt due to this bit is masked." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x10 2. "AHBERRM,AHB error. In scatter/gather DMA mode for host interrupts will not be generated due to the corresponding bits set in OTG_HCINTx." "0: Masked interrupt,1: Unmasked interrupt" bitfld.long 0x10 1. "CHHM,Channel halted mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x10 0. "XFRCM,Transfer completed mask" "0: Masked interrupt,1: Unmasked interrupt" endif sif (cpuis("STM32MP151*")) bitfld.long 0x10 10. "DTERRM,DTERRM" "0,1" newline bitfld.long 0x10 9. "FRMORM,FRMORM" "0,1" bitfld.long 0x10 8. "BBERRM,BBERRM" "0,1" newline bitfld.long 0x10 7. "TXERRM,TXERRM" "0,1" bitfld.long 0x10 6. "NYET,NYET" "0,1" newline bitfld.long 0x10 5. "ACKM,ACKM" "0,1" bitfld.long 0x10 4. "NAKM,NAKM" "0,1" newline bitfld.long 0x10 3. "STALLM,STALLM" "0,1" bitfld.long 0x10 2. "AHBERRM,AHBERRM" "0,1" newline bitfld.long 0x10 1. "CHHM,CHHM" "0,1" endif sif (cpuis("STM32MP153*")) bitfld.long 0x10 10. "DTERRM,DTERRM" "0,1" newline bitfld.long 0x10 9. "FRMORM,FRMORM" "0,1" bitfld.long 0x10 8. "BBERRM,BBERRM" "0,1" newline bitfld.long 0x10 7. "TXERRM,TXERRM" "0,1" bitfld.long 0x10 6. "NYET,NYET" "0,1" newline bitfld.long 0x10 5. "ACKM,ACKM" "0,1" bitfld.long 0x10 4. "NAKM,NAKM" "0,1" newline bitfld.long 0x10 3. "STALLM,STALLM" "0,1" bitfld.long 0x10 2. "AHBERRM,AHBERRM" "0,1" newline bitfld.long 0x10 1. "CHHM,CHHM" "0,1" bitfld.long 0x10 0. "XFRCM,XFRCM" "0,1" newline endif sif (cpuis("STM32MP157*")) bitfld.long 0x10 10. "DTERRM,DTERRM" "0,1" bitfld.long 0x10 9. "FRMORM,FRMORM" "0,1" newline bitfld.long 0x10 8. "BBERRM,BBERRM" "0,1" bitfld.long 0x10 7. "TXERRM,TXERRM" "0,1" newline bitfld.long 0x10 6. "NYET,NYET" "0,1" bitfld.long 0x10 5. "ACKM,ACKM" "0,1" newline bitfld.long 0x10 4. "NAKM,NAKM" "0,1" bitfld.long 0x10 3. "STALLM,STALLM" "0,1" newline bitfld.long 0x10 2. "AHBERRM,AHBERRM" "0,1" bitfld.long 0x10 1. "CHHM,CHHM" "0,1" newline bitfld.long 0x10 0. "XFRCM,XFRCM" "0,1" endif line.long 0x14 "OTG_HCTSIZ7," sif (cpuis("STM32MP13*")) bitfld.long 0x14 31. "DOPNG,Do Ping" "0,1" bitfld.long 0x14 29.--30. "DPID,Data PID" "0: DATA0,1: DATA2,2: DATA1,3: SETUP (control) / MDATA (non-control)" newline endif sif (cpuis("STM32MP151*")) bitfld.long 0x14 29.--30. "DPID,DPID" "0,1,2,3" endif sif (cpuis("STM32MP153*")) bitfld.long 0x14 29.--30. "DPID,DPID" "0,1,2,3" newline endif sif (cpuis("STM32MP157*")) bitfld.long 0x14 29.--30. "DPID,DPID" "0,1,2,3" endif hexmask.long.word 0x14 19.--28. 1. "PKTCNT,Packet count" newline hexmask.long.tbyte 0x14 0.--18. 1. "XFRSIZ,Transfer size" line.long 0x18 "OTG_HCDMA7," hexmask.long 0x18 0.--31. 1. "DMAADDR,DMA address" group.long 0x5FC++0x1B line.long 0x0 "OTG_HCDMAB7," sif (cpuis("STM32MP13*")) hexmask.long 0x0 0.--31. 1. "HCDMAB,DMA address" endif sif (cpuis("STM32MP151*")) hexmask.long 0x0 0.--31. 1. "HCDMAB,HCDMAB" newline endif sif (cpuis("STM32MP153*")) hexmask.long 0x0 0.--31. 1. "HCDMAB,HCDMAB" endif sif (cpuis("STM32MP157*")) hexmask.long 0x0 0.--31. 1. "HCDMAB,HCDMAB" endif line.long 0x4 "OTG_HCCHAR8," sif (cpuis("STM32MP13*")) bitfld.long 0x4 31. "CHENA,Channel enable" "0: Indicates that the descriptor structure is not..,1: Indicates that the descriptor structure and data.." bitfld.long 0x4 29. "ODDFRM,Odd frame" "0: Even frame,1: Odd frame" newline bitfld.long 0x4 20.--21. "MCNT,Multicount" "0: Reserved. This field yields undefined results,1: 1 transaction,2: 2 transactions per frame to be issued for this..,3: 3 transactions per frame to be issued for this.." bitfld.long 0x4 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt" newline bitfld.long 0x4 15. "EPDIR,Endpoint direction" "0: OUT,1: IN" endif sif (cpuis("STM32MP151*")) bitfld.long 0x4 31. "CHENA,CHENA" "0,1" newline endif sif (cpuis("STM32MP153*")) bitfld.long 0x4 31. "CHENA,CHENA" "0,1" endif sif (cpuis("STM32MP157*")) bitfld.long 0x4 31. "CHENA,CHENA" "0,1" newline endif bitfld.long 0x4 30. "CHDIS,Channel disable" "0,1" hexmask.long.byte 0x4 22.--28. 1. "DAD,Device address" newline sif (cpuis("STM32MP151*")) bitfld.long 0x4 20.--21. "MCNT,MCNT" "0,1,2,3" bitfld.long 0x4 18.--19. "EPTYP,EPTYP" "0,1,2,3" newline endif sif (cpuis("STM32MP153*")) bitfld.long 0x4 20.--21. "MCNT,MCNT" "0,1,2,3" bitfld.long 0x4 18.--19. "EPTYP,EPTYP" "0,1,2,3" newline endif sif (cpuis("STM32MP157*")) bitfld.long 0x4 20.--21. "MCNT,MCNT" "0,1,2,3" bitfld.long 0x4 18.--19. "EPTYP,EPTYP" "0,1,2,3" newline endif bitfld.long 0x4 17. "LSDEV,Low-speed device" "0,1" sif (cpuis("STM32MP151*")) bitfld.long 0x4 15. "EPDIR,EPDIR" "0,1" newline endif sif (cpuis("STM32MP153*")) bitfld.long 0x4 15. "EPDIR,EPDIR" "0,1" endif sif (cpuis("STM32MP157*")) bitfld.long 0x4 15. "EPDIR,EPDIR" "0,1" newline endif hexmask.long.byte 0x4 11.--14. 1. "EPNUM,Endpoint number" hexmask.long.word 0x4 0.--10. 1. "MPSIZ,Maximum packet size" line.long 0x8 "OTG_HCSPLT8," bitfld.long 0x8 31. "SPLITEN,Split enable" "0,1" bitfld.long 0x8 16. "COMPLSPLT,Do complete split" "0,1" newline sif (cpuis("STM32MP13*")) bitfld.long 0x8 14.--15. "XACTPOS,Transaction position" "0: Mid. This is the middle payload of this..,1: End. This is the last payload of this..,2: Begin. This is the first data payload of this..,3: All. This is the entire data payload of this.." endif sif (cpuis("STM32MP151*")) bitfld.long 0x8 14.--15. "XACTPOS,XACTPOS" "0,1,2,3" newline endif sif (cpuis("STM32MP153*")) bitfld.long 0x8 14.--15. "XACTPOS,XACTPOS" "0,1,2,3" endif sif (cpuis("STM32MP157*")) bitfld.long 0x8 14.--15. "XACTPOS,XACTPOS" "0,1,2,3" newline endif hexmask.long.byte 0x8 7.--13. 1. "HUBADDR,Hub address" hexmask.long.byte 0x8 0.--6. 1. "PRTADDR,Port address" line.long 0xC "OTG_HCINT8,OTG host channel 8 interrupt register" bitfld.long 0xC 13. "DESCLSTROLL,Descriptor rollover interrupt." "0,1" bitfld.long 0xC 12. "XCSXACTERR,Excessive transaction error." "0,1" newline bitfld.long 0xC 11. "BNA,Buffer not available interrupt." "0,1" bitfld.long 0xC 10. "DTERR,Data toggle error. In Scatter/Gather DMA mode the interrupt due to this bit is masked." "0,1" newline bitfld.long 0xC 9. "FRMOR,Frame overrun. In Scatter/Gather DMA mode the interrupt due to this bit is masked." "0,1" bitfld.long 0xC 8. "BBERR,Babble error. In Scatter/Gather DMA mode the interrupt due to this bit is masked." "0,1" newline bitfld.long 0xC 7. "TXERR,Transaction error. In Scatter/Gather DMA mode the interrupt due to this bit is masked." "0,1" bitfld.long 0xC 6. "NYET,Not yet ready response received interrupt. In Scatter/Gather DMA mode the interrupt due to this bit is masked." "0,1" newline bitfld.long 0xC 5. "ACK,ACK response received/transmitted interrupt. In Scatter/Gather DMA mode the interrupt due to this bit is masked." "0,1" bitfld.long 0xC 4. "NAK,NAK response received interrupt. In Scatter/Gather DMA mode the interrupt due to this bit is masked." "0,1" newline bitfld.long 0xC 3. "STALL,STALL response received interrupt. In Scatter/Gather DMA mode the interrupt due to this bit is masked." "0,1" bitfld.long 0xC 2. "AHBERR,AHB error" "0,1" newline bitfld.long 0xC 1. "CHH,Channel halted." "0,1" bitfld.long 0xC 0. "XFRC,Transfer completed." "0,1" line.long 0x10 "OTG_HCINTMSK8,OTG host channel 8 interrupt mask register" bitfld.long 0x10 13. "DESCLSTROLLMSK,Descriptor rollover interrupt mask register." "0,1" bitfld.long 0x10 11. "BNAMSK,Buffer not available interrupt mask register." "0,1" newline sif (cpuis("STM32MP13*")) bitfld.long 0x10 10. "DTERRM,Data toggle error mask. In Scatter/Gather DMA mode the interrupt due to this bit is masked." "0: Masked interrupt,1: Unmasked interrupt" bitfld.long 0x10 9. "FRMORM,Frame overrun mask. In Scatter/Gather DMA mode the interrupt due to this bit is masked." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x10 8. "BBERRM,Babble error mask. In Scatter/Gather DMA mode the interrupt due to this bit is masked." "0: Masked interrupt,1: Unmasked interrupt" bitfld.long 0x10 7. "TXERRM,Transaction error mask. In Scatter/Gather DMA mode the interrupt due to this bit is masked." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x10 6. "NYET,response received interrupt mask. In Scatter/Gather DMA mode the interrupt due to this bit is masked." "0: Masked interrupt,1: Unmasked interrupt" bitfld.long 0x10 5. "ACKM,ACK response received/transmitted interrupt mask. In Scatter/Gather DMA mode the interrupt due to this bit is masked." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x10 4. "NAKM,NAK response received interrupt mask. In Scatter/Gather DMA mode the interrupt due to this bit is masked." "0: Masked interrupt,1: Unmasked interrupt" bitfld.long 0x10 3. "STALLM,STALL response received interrupt mask. In Scatter/Gather DMA mode the interrupt due to this bit is masked." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x10 2. "AHBERRM,AHB error. In scatter/gather DMA mode for host interrupts will not be generated due to the corresponding bits set in OTG_HCINTx." "0: Masked interrupt,1: Unmasked interrupt" bitfld.long 0x10 1. "CHHM,Channel halted mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x10 0. "XFRCM,Transfer completed mask" "0: Masked interrupt,1: Unmasked interrupt" endif sif (cpuis("STM32MP151*")) bitfld.long 0x10 10. "DTERRM,DTERRM" "0,1" newline bitfld.long 0x10 9. "FRMORM,FRMORM" "0,1" bitfld.long 0x10 8. "BBERRM,BBERRM" "0,1" newline bitfld.long 0x10 7. "TXERRM,TXERRM" "0,1" bitfld.long 0x10 6. "NYET,NYET" "0,1" newline bitfld.long 0x10 5. "ACKM,ACKM" "0,1" bitfld.long 0x10 4. "NAKM,NAKM" "0,1" newline bitfld.long 0x10 3. "STALLM,STALLM" "0,1" bitfld.long 0x10 2. "AHBERRM,AHBERRM" "0,1" newline bitfld.long 0x10 1. "CHHM,CHHM" "0,1" endif sif (cpuis("STM32MP153*")) bitfld.long 0x10 10. "DTERRM,DTERRM" "0,1" newline bitfld.long 0x10 9. "FRMORM,FRMORM" "0,1" bitfld.long 0x10 8. "BBERRM,BBERRM" "0,1" newline bitfld.long 0x10 7. "TXERRM,TXERRM" "0,1" bitfld.long 0x10 6. "NYET,NYET" "0,1" newline bitfld.long 0x10 5. "ACKM,ACKM" "0,1" bitfld.long 0x10 4. "NAKM,NAKM" "0,1" newline bitfld.long 0x10 3. "STALLM,STALLM" "0,1" bitfld.long 0x10 2. "AHBERRM,AHBERRM" "0,1" newline bitfld.long 0x10 1. "CHHM,CHHM" "0,1" bitfld.long 0x10 0. "XFRCM,XFRCM" "0,1" newline endif sif (cpuis("STM32MP157*")) bitfld.long 0x10 10. "DTERRM,DTERRM" "0,1" bitfld.long 0x10 9. "FRMORM,FRMORM" "0,1" newline bitfld.long 0x10 8. "BBERRM,BBERRM" "0,1" bitfld.long 0x10 7. "TXERRM,TXERRM" "0,1" newline bitfld.long 0x10 6. "NYET,NYET" "0,1" bitfld.long 0x10 5. "ACKM,ACKM" "0,1" newline bitfld.long 0x10 4. "NAKM,NAKM" "0,1" bitfld.long 0x10 3. "STALLM,STALLM" "0,1" newline bitfld.long 0x10 2. "AHBERRM,AHBERRM" "0,1" bitfld.long 0x10 1. "CHHM,CHHM" "0,1" newline bitfld.long 0x10 0. "XFRCM,XFRCM" "0,1" endif line.long 0x14 "OTG_HCTSIZ8," sif (cpuis("STM32MP13*")) bitfld.long 0x14 31. "DOPNG,Do Ping" "0,1" bitfld.long 0x14 29.--30. "DPID,Data PID" "0: DATA0,1: DATA2,2: DATA1,3: SETUP (control) / MDATA (non-control)" newline endif sif (cpuis("STM32MP151*")) bitfld.long 0x14 29.--30. "DPID,DPID" "0,1,2,3" endif sif (cpuis("STM32MP153*")) bitfld.long 0x14 29.--30. "DPID,DPID" "0,1,2,3" newline endif sif (cpuis("STM32MP157*")) bitfld.long 0x14 29.--30. "DPID,DPID" "0,1,2,3" endif hexmask.long.word 0x14 19.--28. 1. "PKTCNT,Packet count" newline hexmask.long.tbyte 0x14 0.--18. 1. "XFRSIZ,Transfer size" line.long 0x18 "OTG_HCDMA8," hexmask.long 0x18 0.--31. 1. "DMAADDR,DMA address" group.long 0x61C++0x1B line.long 0x0 "OTG_HCDMAB8," sif (cpuis("STM32MP13*")) hexmask.long 0x0 0.--31. 1. "HCDMAB,DMA address" endif sif (cpuis("STM32MP151*")) hexmask.long 0x0 0.--31. 1. "HCDMAB,HCDMAB" newline endif sif (cpuis("STM32MP153*")) hexmask.long 0x0 0.--31. 1. "HCDMAB,HCDMAB" endif sif (cpuis("STM32MP157*")) hexmask.long 0x0 0.--31. 1. "HCDMAB,HCDMAB" endif line.long 0x4 "OTG_HCCHAR9," sif (cpuis("STM32MP13*")) bitfld.long 0x4 31. "CHENA,Channel enable" "0: Indicates that the descriptor structure is not..,1: Indicates that the descriptor structure and data.." bitfld.long 0x4 29. "ODDFRM,Odd frame" "0: Even frame,1: Odd frame" newline bitfld.long 0x4 20.--21. "MCNT,Multicount" "0: Reserved. This field yields undefined results,1: 1 transaction,2: 2 transactions per frame to be issued for this..,3: 3 transactions per frame to be issued for this.." bitfld.long 0x4 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt" newline bitfld.long 0x4 15. "EPDIR,Endpoint direction" "0: OUT,1: IN" endif sif (cpuis("STM32MP151*")) bitfld.long 0x4 31. "CHENA,CHENA" "0,1" newline endif sif (cpuis("STM32MP153*")) bitfld.long 0x4 31. "CHENA,CHENA" "0,1" endif sif (cpuis("STM32MP157*")) bitfld.long 0x4 31. "CHENA,CHENA" "0,1" newline endif bitfld.long 0x4 30. "CHDIS,Channel disable" "0,1" hexmask.long.byte 0x4 22.--28. 1. "DAD,Device address" newline sif (cpuis("STM32MP151*")) bitfld.long 0x4 20.--21. "MCNT,MCNT" "0,1,2,3" bitfld.long 0x4 18.--19. "EPTYP,EPTYP" "0,1,2,3" newline endif sif (cpuis("STM32MP153*")) bitfld.long 0x4 20.--21. "MCNT,MCNT" "0,1,2,3" bitfld.long 0x4 18.--19. "EPTYP,EPTYP" "0,1,2,3" newline endif sif (cpuis("STM32MP157*")) bitfld.long 0x4 20.--21. "MCNT,MCNT" "0,1,2,3" bitfld.long 0x4 18.--19. "EPTYP,EPTYP" "0,1,2,3" newline endif bitfld.long 0x4 17. "LSDEV,Low-speed device" "0,1" sif (cpuis("STM32MP151*")) bitfld.long 0x4 15. "EPDIR,EPDIR" "0,1" newline endif sif (cpuis("STM32MP153*")) bitfld.long 0x4 15. "EPDIR,EPDIR" "0,1" endif sif (cpuis("STM32MP157*")) bitfld.long 0x4 15. "EPDIR,EPDIR" "0,1" newline endif hexmask.long.byte 0x4 11.--14. 1. "EPNUM,Endpoint number" hexmask.long.word 0x4 0.--10. 1. "MPSIZ,Maximum packet size" line.long 0x8 "OTG_HCSPLT9," bitfld.long 0x8 31. "SPLITEN,Split enable" "0,1" bitfld.long 0x8 16. "COMPLSPLT,Do complete split" "0,1" newline sif (cpuis("STM32MP13*")) bitfld.long 0x8 14.--15. "XACTPOS,Transaction position" "0: Mid. This is the middle payload of this..,1: End. This is the last payload of this..,2: Begin. This is the first data payload of this..,3: All. This is the entire data payload of this.." endif sif (cpuis("STM32MP151*")) bitfld.long 0x8 14.--15. "XACTPOS,XACTPOS" "0,1,2,3" newline endif sif (cpuis("STM32MP153*")) bitfld.long 0x8 14.--15. "XACTPOS,XACTPOS" "0,1,2,3" endif sif (cpuis("STM32MP157*")) bitfld.long 0x8 14.--15. "XACTPOS,XACTPOS" "0,1,2,3" newline endif hexmask.long.byte 0x8 7.--13. 1. "HUBADDR,Hub address" hexmask.long.byte 0x8 0.--6. 1. "PRTADDR,Port address" line.long 0xC "OTG_HCINT9,OTG host channel 9 interrupt register" bitfld.long 0xC 13. "DESCLSTROLL,Descriptor rollover interrupt." "0,1" bitfld.long 0xC 12. "XCSXACTERR,Excessive transaction error." "0,1" newline bitfld.long 0xC 11. "BNA,Buffer not available interrupt." "0,1" bitfld.long 0xC 10. "DTERR,Data toggle error. In Scatter/Gather DMA mode the interrupt due to this bit is masked." "0,1" newline bitfld.long 0xC 9. "FRMOR,Frame overrun. In Scatter/Gather DMA mode the interrupt due to this bit is masked." "0,1" bitfld.long 0xC 8. "BBERR,Babble error. In Scatter/Gather DMA mode the interrupt due to this bit is masked." "0,1" newline bitfld.long 0xC 7. "TXERR,Transaction error. In Scatter/Gather DMA mode the interrupt due to this bit is masked." "0,1" bitfld.long 0xC 6. "NYET,Not yet ready response received interrupt. In Scatter/Gather DMA mode the interrupt due to this bit is masked." "0,1" newline bitfld.long 0xC 5. "ACK,ACK response received/transmitted interrupt. In Scatter/Gather DMA mode the interrupt due to this bit is masked." "0,1" bitfld.long 0xC 4. "NAK,NAK response received interrupt. In Scatter/Gather DMA mode the interrupt due to this bit is masked." "0,1" newline bitfld.long 0xC 3. "STALL,STALL response received interrupt. In Scatter/Gather DMA mode the interrupt due to this bit is masked." "0,1" bitfld.long 0xC 2. "AHBERR,AHB error" "0,1" newline bitfld.long 0xC 1. "CHH,Channel halted." "0,1" bitfld.long 0xC 0. "XFRC,Transfer completed." "0,1" line.long 0x10 "OTG_HCINTMSK9,OTG host channel 9 interrupt mask register" bitfld.long 0x10 13. "DESCLSTROLLMSK,Descriptor rollover interrupt mask register." "0,1" bitfld.long 0x10 11. "BNAMSK,Buffer not available interrupt mask register." "0,1" newline sif (cpuis("STM32MP13*")) bitfld.long 0x10 10. "DTERRM,Data toggle error mask. In Scatter/Gather DMA mode the interrupt due to this bit is masked." "0: Masked interrupt,1: Unmasked interrupt" bitfld.long 0x10 9. "FRMORM,Frame overrun mask. In Scatter/Gather DMA mode the interrupt due to this bit is masked." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x10 8. "BBERRM,Babble error mask. In Scatter/Gather DMA mode the interrupt due to this bit is masked." "0: Masked interrupt,1: Unmasked interrupt" bitfld.long 0x10 7. "TXERRM,Transaction error mask. In Scatter/Gather DMA mode the interrupt due to this bit is masked." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x10 6. "NYET,response received interrupt mask. In Scatter/Gather DMA mode the interrupt due to this bit is masked." "0: Masked interrupt,1: Unmasked interrupt" bitfld.long 0x10 5. "ACKM,ACK response received/transmitted interrupt mask. In Scatter/Gather DMA mode the interrupt due to this bit is masked." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x10 4. "NAKM,NAK response received interrupt mask. In Scatter/Gather DMA mode the interrupt due to this bit is masked." "0: Masked interrupt,1: Unmasked interrupt" bitfld.long 0x10 3. "STALLM,STALL response received interrupt mask. In Scatter/Gather DMA mode the interrupt due to this bit is masked." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x10 2. "AHBERRM,AHB error. In scatter/gather DMA mode for host interrupts will not be generated due to the corresponding bits set in OTG_HCINTx." "0: Masked interrupt,1: Unmasked interrupt" bitfld.long 0x10 1. "CHHM,Channel halted mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x10 0. "XFRCM,Transfer completed mask" "0: Masked interrupt,1: Unmasked interrupt" endif sif (cpuis("STM32MP151*")) bitfld.long 0x10 10. "DTERRM,DTERRM" "0,1" newline bitfld.long 0x10 9. "FRMORM,FRMORM" "0,1" bitfld.long 0x10 8. "BBERRM,BBERRM" "0,1" newline bitfld.long 0x10 7. "TXERRM,TXERRM" "0,1" bitfld.long 0x10 6. "NYET,NYET" "0,1" newline bitfld.long 0x10 5. "ACKM,ACKM" "0,1" bitfld.long 0x10 4. "NAKM,NAKM" "0,1" newline bitfld.long 0x10 3. "STALLM,STALLM" "0,1" bitfld.long 0x10 2. "AHBERRM,AHBERRM" "0,1" newline bitfld.long 0x10 1. "CHHM,CHHM" "0,1" endif sif (cpuis("STM32MP153*")) bitfld.long 0x10 10. "DTERRM,DTERRM" "0,1" newline bitfld.long 0x10 9. "FRMORM,FRMORM" "0,1" bitfld.long 0x10 8. "BBERRM,BBERRM" "0,1" newline bitfld.long 0x10 7. "TXERRM,TXERRM" "0,1" bitfld.long 0x10 6. "NYET,NYET" "0,1" newline bitfld.long 0x10 5. "ACKM,ACKM" "0,1" bitfld.long 0x10 4. "NAKM,NAKM" "0,1" newline bitfld.long 0x10 3. "STALLM,STALLM" "0,1" bitfld.long 0x10 2. "AHBERRM,AHBERRM" "0,1" newline bitfld.long 0x10 1. "CHHM,CHHM" "0,1" bitfld.long 0x10 0. "XFRCM,XFRCM" "0,1" newline endif sif (cpuis("STM32MP157*")) bitfld.long 0x10 10. "DTERRM,DTERRM" "0,1" bitfld.long 0x10 9. "FRMORM,FRMORM" "0,1" newline bitfld.long 0x10 8. "BBERRM,BBERRM" "0,1" bitfld.long 0x10 7. "TXERRM,TXERRM" "0,1" newline bitfld.long 0x10 6. "NYET,NYET" "0,1" bitfld.long 0x10 5. "ACKM,ACKM" "0,1" newline bitfld.long 0x10 4. "NAKM,NAKM" "0,1" bitfld.long 0x10 3. "STALLM,STALLM" "0,1" newline bitfld.long 0x10 2. "AHBERRM,AHBERRM" "0,1" bitfld.long 0x10 1. "CHHM,CHHM" "0,1" newline bitfld.long 0x10 0. "XFRCM,XFRCM" "0,1" endif line.long 0x14 "OTG_HCTSIZ9," sif (cpuis("STM32MP13*")) bitfld.long 0x14 31. "DOPNG,Do Ping" "0,1" bitfld.long 0x14 29.--30. "DPID,Data PID" "0: DATA0,1: DATA2,2: DATA1,3: SETUP (control) / MDATA (non-control)" newline endif sif (cpuis("STM32MP151*")) bitfld.long 0x14 29.--30. "DPID,DPID" "0,1,2,3" endif sif (cpuis("STM32MP153*")) bitfld.long 0x14 29.--30. "DPID,DPID" "0,1,2,3" newline endif sif (cpuis("STM32MP157*")) bitfld.long 0x14 29.--30. "DPID,DPID" "0,1,2,3" endif hexmask.long.word 0x14 19.--28. 1. "PKTCNT,Packet count" newline hexmask.long.tbyte 0x14 0.--18. 1. "XFRSIZ,Transfer size" line.long 0x18 "OTG_HCDMA9," hexmask.long 0x18 0.--31. 1. "DMAADDR,DMA address" group.long 0x63C++0x1B line.long 0x0 "OTG_HCDMAB9," sif (cpuis("STM32MP13*")) hexmask.long 0x0 0.--31. 1. "HCDMAB,DMA address" endif sif (cpuis("STM32MP151*")) hexmask.long 0x0 0.--31. 1. "HCDMAB,HCDMAB" newline endif sif (cpuis("STM32MP153*")) hexmask.long 0x0 0.--31. 1. "HCDMAB,HCDMAB" endif sif (cpuis("STM32MP157*")) hexmask.long 0x0 0.--31. 1. "HCDMAB,HCDMAB" endif line.long 0x4 "OTG_HCCHAR10," sif (cpuis("STM32MP13*")) bitfld.long 0x4 31. "CHENA,Channel enable" "0: Indicates that the descriptor structure is not..,1: Indicates that the descriptor structure and data.." bitfld.long 0x4 29. "ODDFRM,Odd frame" "0: Even frame,1: Odd frame" newline bitfld.long 0x4 20.--21. "MCNT,Multicount" "0: Reserved. This field yields undefined results,1: 1 transaction,2: 2 transactions per frame to be issued for this..,3: 3 transactions per frame to be issued for this.." bitfld.long 0x4 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt" newline bitfld.long 0x4 15. "EPDIR,Endpoint direction" "0: OUT,1: IN" endif sif (cpuis("STM32MP151*")) bitfld.long 0x4 31. "CHENA,CHENA" "0,1" newline endif sif (cpuis("STM32MP153*")) bitfld.long 0x4 31. "CHENA,CHENA" "0,1" endif sif (cpuis("STM32MP157*")) bitfld.long 0x4 31. "CHENA,CHENA" "0,1" newline endif bitfld.long 0x4 30. "CHDIS,Channel disable" "0,1" hexmask.long.byte 0x4 22.--28. 1. "DAD,Device address" newline sif (cpuis("STM32MP151*")) bitfld.long 0x4 20.--21. "MCNT,MCNT" "0,1,2,3" bitfld.long 0x4 18.--19. "EPTYP,EPTYP" "0,1,2,3" newline endif sif (cpuis("STM32MP153*")) bitfld.long 0x4 20.--21. "MCNT,MCNT" "0,1,2,3" bitfld.long 0x4 18.--19. "EPTYP,EPTYP" "0,1,2,3" newline endif sif (cpuis("STM32MP157*")) bitfld.long 0x4 20.--21. "MCNT,MCNT" "0,1,2,3" bitfld.long 0x4 18.--19. "EPTYP,EPTYP" "0,1,2,3" newline endif bitfld.long 0x4 17. "LSDEV,Low-speed device" "0,1" sif (cpuis("STM32MP151*")) bitfld.long 0x4 15. "EPDIR,EPDIR" "0,1" newline endif sif (cpuis("STM32MP153*")) bitfld.long 0x4 15. "EPDIR,EPDIR" "0,1" endif sif (cpuis("STM32MP157*")) bitfld.long 0x4 15. "EPDIR,EPDIR" "0,1" newline endif hexmask.long.byte 0x4 11.--14. 1. "EPNUM,Endpoint number" hexmask.long.word 0x4 0.--10. 1. "MPSIZ,Maximum packet size" line.long 0x8 "OTG_HCSPLT10," bitfld.long 0x8 31. "SPLITEN,Split enable" "0,1" bitfld.long 0x8 16. "COMPLSPLT,Do complete split" "0,1" newline sif (cpuis("STM32MP13*")) bitfld.long 0x8 14.--15. "XACTPOS,Transaction position" "0: Mid. This is the middle payload of this..,1: End. This is the last payload of this..,2: Begin. This is the first data payload of this..,3: All. This is the entire data payload of this.." endif sif (cpuis("STM32MP151*")) bitfld.long 0x8 14.--15. "XACTPOS,XACTPOS" "0,1,2,3" newline endif sif (cpuis("STM32MP153*")) bitfld.long 0x8 14.--15. "XACTPOS,XACTPOS" "0,1,2,3" endif sif (cpuis("STM32MP157*")) bitfld.long 0x8 14.--15. "XACTPOS,XACTPOS" "0,1,2,3" newline endif hexmask.long.byte 0x8 7.--13. 1. "HUBADDR,Hub address" hexmask.long.byte 0x8 0.--6. 1. "PRTADDR,Port address" line.long 0xC "OTG_HCINT10,OTG host channel 10 interrupt register" bitfld.long 0xC 13. "DESCLSTROLL,Descriptor rollover interrupt." "0,1" bitfld.long 0xC 12. "XCSXACTERR,Excessive transaction error." "0,1" newline bitfld.long 0xC 11. "BNA,Buffer not available interrupt." "0,1" bitfld.long 0xC 10. "DTERR,Data toggle error. In Scatter/Gather DMA mode the interrupt due to this bit is masked." "0,1" newline bitfld.long 0xC 9. "FRMOR,Frame overrun. In Scatter/Gather DMA mode the interrupt due to this bit is masked." "0,1" bitfld.long 0xC 8. "BBERR,Babble error. In Scatter/Gather DMA mode the interrupt due to this bit is masked." "0,1" newline bitfld.long 0xC 7. "TXERR,Transaction error. In Scatter/Gather DMA mode the interrupt due to this bit is masked." "0,1" bitfld.long 0xC 6. "NYET,Not yet ready response received interrupt. In Scatter/Gather DMA mode the interrupt due to this bit is masked." "0,1" newline bitfld.long 0xC 5. "ACK,ACK response received/transmitted interrupt. In Scatter/Gather DMA mode the interrupt due to this bit is masked." "0,1" bitfld.long 0xC 4. "NAK,NAK response received interrupt. In Scatter/Gather DMA mode the interrupt due to this bit is masked." "0,1" newline bitfld.long 0xC 3. "STALL,STALL response received interrupt. In Scatter/Gather DMA mode the interrupt due to this bit is masked." "0,1" bitfld.long 0xC 2. "AHBERR,AHB error" "0,1" newline bitfld.long 0xC 1. "CHH,Channel halted." "0,1" bitfld.long 0xC 0. "XFRC,Transfer completed." "0,1" line.long 0x10 "OTG_HCINTMSK10,OTG host channel 10 interrupt mask register" bitfld.long 0x10 13. "DESCLSTROLLMSK,Descriptor rollover interrupt mask register." "0,1" bitfld.long 0x10 11. "BNAMSK,Buffer not available interrupt mask register." "0,1" newline sif (cpuis("STM32MP13*")) bitfld.long 0x10 10. "DTERRM,Data toggle error mask. In Scatter/Gather DMA mode the interrupt due to this bit is masked." "0: Masked interrupt,1: Unmasked interrupt" bitfld.long 0x10 9. "FRMORM,Frame overrun mask. In Scatter/Gather DMA mode the interrupt due to this bit is masked." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x10 8. "BBERRM,Babble error mask. In Scatter/Gather DMA mode the interrupt due to this bit is masked." "0: Masked interrupt,1: Unmasked interrupt" bitfld.long 0x10 7. "TXERRM,Transaction error mask. In Scatter/Gather DMA mode the interrupt due to this bit is masked." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x10 6. "NYET,response received interrupt mask. In Scatter/Gather DMA mode the interrupt due to this bit is masked." "0: Masked interrupt,1: Unmasked interrupt" bitfld.long 0x10 5. "ACKM,ACK response received/transmitted interrupt mask. In Scatter/Gather DMA mode the interrupt due to this bit is masked." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x10 4. "NAKM,NAK response received interrupt mask. In Scatter/Gather DMA mode the interrupt due to this bit is masked." "0: Masked interrupt,1: Unmasked interrupt" bitfld.long 0x10 3. "STALLM,STALL response received interrupt mask. In Scatter/Gather DMA mode the interrupt due to this bit is masked." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x10 2. "AHBERRM,AHB error. In scatter/gather DMA mode for host interrupts will not be generated due to the corresponding bits set in OTG_HCINTx." "0: Masked interrupt,1: Unmasked interrupt" bitfld.long 0x10 1. "CHHM,Channel halted mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x10 0. "XFRCM,Transfer completed mask" "0: Masked interrupt,1: Unmasked interrupt" endif sif (cpuis("STM32MP151*")) bitfld.long 0x10 10. "DTERRM,DTERRM" "0,1" newline bitfld.long 0x10 9. "FRMORM,FRMORM" "0,1" bitfld.long 0x10 8. "BBERRM,BBERRM" "0,1" newline bitfld.long 0x10 7. "TXERRM,TXERRM" "0,1" bitfld.long 0x10 6. "NYET,NYET" "0,1" newline bitfld.long 0x10 5. "ACKM,ACKM" "0,1" bitfld.long 0x10 4. "NAKM,NAKM" "0,1" newline bitfld.long 0x10 3. "STALLM,STALLM" "0,1" bitfld.long 0x10 2. "AHBERRM,AHBERRM" "0,1" newline bitfld.long 0x10 1. "CHHM,CHHM" "0,1" endif sif (cpuis("STM32MP153*")) bitfld.long 0x10 10. "DTERRM,DTERRM" "0,1" newline bitfld.long 0x10 9. "FRMORM,FRMORM" "0,1" bitfld.long 0x10 8. "BBERRM,BBERRM" "0,1" newline bitfld.long 0x10 7. "TXERRM,TXERRM" "0,1" bitfld.long 0x10 6. "NYET,NYET" "0,1" newline bitfld.long 0x10 5. "ACKM,ACKM" "0,1" bitfld.long 0x10 4. "NAKM,NAKM" "0,1" newline bitfld.long 0x10 3. "STALLM,STALLM" "0,1" bitfld.long 0x10 2. "AHBERRM,AHBERRM" "0,1" newline bitfld.long 0x10 1. "CHHM,CHHM" "0,1" bitfld.long 0x10 0. "XFRCM,XFRCM" "0,1" newline endif sif (cpuis("STM32MP157*")) bitfld.long 0x10 10. "DTERRM,DTERRM" "0,1" bitfld.long 0x10 9. "FRMORM,FRMORM" "0,1" newline bitfld.long 0x10 8. "BBERRM,BBERRM" "0,1" bitfld.long 0x10 7. "TXERRM,TXERRM" "0,1" newline bitfld.long 0x10 6. "NYET,NYET" "0,1" bitfld.long 0x10 5. "ACKM,ACKM" "0,1" newline bitfld.long 0x10 4. "NAKM,NAKM" "0,1" bitfld.long 0x10 3. "STALLM,STALLM" "0,1" newline bitfld.long 0x10 2. "AHBERRM,AHBERRM" "0,1" bitfld.long 0x10 1. "CHHM,CHHM" "0,1" newline bitfld.long 0x10 0. "XFRCM,XFRCM" "0,1" endif line.long 0x14 "OTG_HCTSIZ10," sif (cpuis("STM32MP13*")) bitfld.long 0x14 31. "DOPNG,Do Ping" "0,1" bitfld.long 0x14 29.--30. "DPID,Data PID" "0: DATA0,1: DATA2,2: DATA1,3: SETUP (control) / MDATA (non-control)" newline endif sif (cpuis("STM32MP151*")) bitfld.long 0x14 29.--30. "DPID,DPID" "0,1,2,3" endif sif (cpuis("STM32MP153*")) bitfld.long 0x14 29.--30. "DPID,DPID" "0,1,2,3" newline endif sif (cpuis("STM32MP157*")) bitfld.long 0x14 29.--30. "DPID,DPID" "0,1,2,3" endif hexmask.long.word 0x14 19.--28. 1. "PKTCNT,Packet count" newline hexmask.long.tbyte 0x14 0.--18. 1. "XFRSIZ,Transfer size" line.long 0x18 "OTG_HCDMA10," hexmask.long 0x18 0.--31. 1. "DMAADDR,DMA address" group.long 0x65C++0x1B line.long 0x0 "OTG_HCDMAB10," sif (cpuis("STM32MP13*")) hexmask.long 0x0 0.--31. 1. "HCDMAB,DMA address" endif sif (cpuis("STM32MP151*")) hexmask.long 0x0 0.--31. 1. "HCDMAB,HCDMAB" newline endif sif (cpuis("STM32MP153*")) hexmask.long 0x0 0.--31. 1. "HCDMAB,HCDMAB" endif sif (cpuis("STM32MP157*")) hexmask.long 0x0 0.--31. 1. "HCDMAB,HCDMAB" endif line.long 0x4 "OTG_HCCHAR11," sif (cpuis("STM32MP13*")) bitfld.long 0x4 31. "CHENA,Channel enable" "0: Indicates that the descriptor structure is not..,1: Indicates that the descriptor structure and data.." bitfld.long 0x4 29. "ODDFRM,Odd frame" "0: Even frame,1: Odd frame" newline bitfld.long 0x4 20.--21. "MCNT,Multicount" "0: Reserved. This field yields undefined results,1: 1 transaction,2: 2 transactions per frame to be issued for this..,3: 3 transactions per frame to be issued for this.." bitfld.long 0x4 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt" newline bitfld.long 0x4 15. "EPDIR,Endpoint direction" "0: OUT,1: IN" endif sif (cpuis("STM32MP151*")) bitfld.long 0x4 31. "CHENA,CHENA" "0,1" newline endif sif (cpuis("STM32MP153*")) bitfld.long 0x4 31. "CHENA,CHENA" "0,1" endif sif (cpuis("STM32MP157*")) bitfld.long 0x4 31. "CHENA,CHENA" "0,1" newline endif bitfld.long 0x4 30. "CHDIS,Channel disable" "0,1" hexmask.long.byte 0x4 22.--28. 1. "DAD,Device address" newline sif (cpuis("STM32MP151*")) bitfld.long 0x4 20.--21. "MCNT,MCNT" "0,1,2,3" bitfld.long 0x4 18.--19. "EPTYP,EPTYP" "0,1,2,3" newline endif sif (cpuis("STM32MP153*")) bitfld.long 0x4 20.--21. "MCNT,MCNT" "0,1,2,3" bitfld.long 0x4 18.--19. "EPTYP,EPTYP" "0,1,2,3" newline endif sif (cpuis("STM32MP157*")) bitfld.long 0x4 20.--21. "MCNT,MCNT" "0,1,2,3" bitfld.long 0x4 18.--19. "EPTYP,EPTYP" "0,1,2,3" newline endif bitfld.long 0x4 17. "LSDEV,Low-speed device" "0,1" sif (cpuis("STM32MP151*")) bitfld.long 0x4 15. "EPDIR,EPDIR" "0,1" newline endif sif (cpuis("STM32MP153*")) bitfld.long 0x4 15. "EPDIR,EPDIR" "0,1" endif sif (cpuis("STM32MP157*")) bitfld.long 0x4 15. "EPDIR,EPDIR" "0,1" newline endif hexmask.long.byte 0x4 11.--14. 1. "EPNUM,Endpoint number" hexmask.long.word 0x4 0.--10. 1. "MPSIZ,Maximum packet size" line.long 0x8 "OTG_HCSPLT11," bitfld.long 0x8 31. "SPLITEN,Split enable" "0,1" bitfld.long 0x8 16. "COMPLSPLT,Do complete split" "0,1" newline sif (cpuis("STM32MP13*")) bitfld.long 0x8 14.--15. "XACTPOS,Transaction position" "0: Mid. This is the middle payload of this..,1: End. This is the last payload of this..,2: Begin. This is the first data payload of this..,3: All. This is the entire data payload of this.." endif sif (cpuis("STM32MP151*")) bitfld.long 0x8 14.--15. "XACTPOS,XACTPOS" "0,1,2,3" newline endif sif (cpuis("STM32MP153*")) bitfld.long 0x8 14.--15. "XACTPOS,XACTPOS" "0,1,2,3" endif sif (cpuis("STM32MP157*")) bitfld.long 0x8 14.--15. "XACTPOS,XACTPOS" "0,1,2,3" newline endif hexmask.long.byte 0x8 7.--13. 1. "HUBADDR,Hub address" hexmask.long.byte 0x8 0.--6. 1. "PRTADDR,Port address" line.long 0xC "OTG_HCINT11,OTG host channel 11 interrupt register" bitfld.long 0xC 13. "DESCLSTROLL,Descriptor rollover interrupt." "0,1" bitfld.long 0xC 12. "XCSXACTERR,Excessive transaction error." "0,1" newline bitfld.long 0xC 11. "BNA,Buffer not available interrupt." "0,1" bitfld.long 0xC 10. "DTERR,Data toggle error. In Scatter/Gather DMA mode the interrupt due to this bit is masked." "0,1" newline bitfld.long 0xC 9. "FRMOR,Frame overrun. In Scatter/Gather DMA mode the interrupt due to this bit is masked." "0,1" bitfld.long 0xC 8. "BBERR,Babble error. In Scatter/Gather DMA mode the interrupt due to this bit is masked." "0,1" newline bitfld.long 0xC 7. "TXERR,Transaction error. In Scatter/Gather DMA mode the interrupt due to this bit is masked." "0,1" bitfld.long 0xC 6. "NYET,Not yet ready response received interrupt. In Scatter/Gather DMA mode the interrupt due to this bit is masked." "0,1" newline bitfld.long 0xC 5. "ACK,ACK response received/transmitted interrupt. In Scatter/Gather DMA mode the interrupt due to this bit is masked." "0,1" bitfld.long 0xC 4. "NAK,NAK response received interrupt. In Scatter/Gather DMA mode the interrupt due to this bit is masked." "0,1" newline bitfld.long 0xC 3. "STALL,STALL response received interrupt. In Scatter/Gather DMA mode the interrupt due to this bit is masked." "0,1" bitfld.long 0xC 2. "AHBERR,AHB error" "0,1" newline bitfld.long 0xC 1. "CHH,Channel halted." "0,1" bitfld.long 0xC 0. "XFRC,Transfer completed." "0,1" line.long 0x10 "OTG_HCINTMSK11,OTG host channel 11 interrupt mask register" bitfld.long 0x10 13. "DESCLSTROLLMSK,Descriptor rollover interrupt mask register." "0,1" bitfld.long 0x10 11. "BNAMSK,Buffer not available interrupt mask register." "0,1" newline sif (cpuis("STM32MP13*")) bitfld.long 0x10 10. "DTERRM,Data toggle error mask. In Scatter/Gather DMA mode the interrupt due to this bit is masked." "0: Masked interrupt,1: Unmasked interrupt" bitfld.long 0x10 9. "FRMORM,Frame overrun mask. In Scatter/Gather DMA mode the interrupt due to this bit is masked." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x10 8. "BBERRM,Babble error mask. In Scatter/Gather DMA mode the interrupt due to this bit is masked." "0: Masked interrupt,1: Unmasked interrupt" bitfld.long 0x10 7. "TXERRM,Transaction error mask. In Scatter/Gather DMA mode the interrupt due to this bit is masked." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x10 6. "NYET,response received interrupt mask. In Scatter/Gather DMA mode the interrupt due to this bit is masked." "0: Masked interrupt,1: Unmasked interrupt" bitfld.long 0x10 5. "ACKM,ACK response received/transmitted interrupt mask. In Scatter/Gather DMA mode the interrupt due to this bit is masked." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x10 4. "NAKM,NAK response received interrupt mask. In Scatter/Gather DMA mode the interrupt due to this bit is masked." "0: Masked interrupt,1: Unmasked interrupt" bitfld.long 0x10 3. "STALLM,STALL response received interrupt mask. In Scatter/Gather DMA mode the interrupt due to this bit is masked." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x10 2. "AHBERRM,AHB error. In scatter/gather DMA mode for host interrupts will not be generated due to the corresponding bits set in OTG_HCINTx." "0: Masked interrupt,1: Unmasked interrupt" bitfld.long 0x10 1. "CHHM,Channel halted mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x10 0. "XFRCM,Transfer completed mask" "0: Masked interrupt,1: Unmasked interrupt" endif sif (cpuis("STM32MP151*")) bitfld.long 0x10 10. "DTERRM,DTERRM" "0,1" newline bitfld.long 0x10 9. "FRMORM,FRMORM" "0,1" bitfld.long 0x10 8. "BBERRM,BBERRM" "0,1" newline bitfld.long 0x10 7. "TXERRM,TXERRM" "0,1" bitfld.long 0x10 6. "NYET,NYET" "0,1" newline bitfld.long 0x10 5. "ACKM,ACKM" "0,1" bitfld.long 0x10 4. "NAKM,NAKM" "0,1" newline bitfld.long 0x10 3. "STALLM,STALLM" "0,1" bitfld.long 0x10 2. "AHBERRM,AHBERRM" "0,1" newline bitfld.long 0x10 1. "CHHM,CHHM" "0,1" endif sif (cpuis("STM32MP153*")) bitfld.long 0x10 10. "DTERRM,DTERRM" "0,1" newline bitfld.long 0x10 9. "FRMORM,FRMORM" "0,1" bitfld.long 0x10 8. "BBERRM,BBERRM" "0,1" newline bitfld.long 0x10 7. "TXERRM,TXERRM" "0,1" bitfld.long 0x10 6. "NYET,NYET" "0,1" newline bitfld.long 0x10 5. "ACKM,ACKM" "0,1" bitfld.long 0x10 4. "NAKM,NAKM" "0,1" newline bitfld.long 0x10 3. "STALLM,STALLM" "0,1" bitfld.long 0x10 2. "AHBERRM,AHBERRM" "0,1" newline bitfld.long 0x10 1. "CHHM,CHHM" "0,1" bitfld.long 0x10 0. "XFRCM,XFRCM" "0,1" newline endif sif (cpuis("STM32MP157*")) bitfld.long 0x10 10. "DTERRM,DTERRM" "0,1" bitfld.long 0x10 9. "FRMORM,FRMORM" "0,1" newline bitfld.long 0x10 8. "BBERRM,BBERRM" "0,1" bitfld.long 0x10 7. "TXERRM,TXERRM" "0,1" newline bitfld.long 0x10 6. "NYET,NYET" "0,1" bitfld.long 0x10 5. "ACKM,ACKM" "0,1" newline bitfld.long 0x10 4. "NAKM,NAKM" "0,1" bitfld.long 0x10 3. "STALLM,STALLM" "0,1" newline bitfld.long 0x10 2. "AHBERRM,AHBERRM" "0,1" bitfld.long 0x10 1. "CHHM,CHHM" "0,1" newline bitfld.long 0x10 0. "XFRCM,XFRCM" "0,1" endif line.long 0x14 "OTG_HCTSIZ11," sif (cpuis("STM32MP13*")) bitfld.long 0x14 31. "DOPNG,Do Ping" "0,1" bitfld.long 0x14 29.--30. "DPID,Data PID" "0: DATA0,1: DATA2,2: DATA1,3: SETUP (control) / MDATA (non-control)" newline endif sif (cpuis("STM32MP151*")) bitfld.long 0x14 29.--30. "DPID,DPID" "0,1,2,3" endif sif (cpuis("STM32MP153*")) bitfld.long 0x14 29.--30. "DPID,DPID" "0,1,2,3" newline endif sif (cpuis("STM32MP157*")) bitfld.long 0x14 29.--30. "DPID,DPID" "0,1,2,3" endif hexmask.long.word 0x14 19.--28. 1. "PKTCNT,Packet count" newline hexmask.long.tbyte 0x14 0.--18. 1. "XFRSIZ,Transfer size" line.long 0x18 "OTG_HCDMA11," hexmask.long 0x18 0.--31. 1. "DMAADDR,DMA address" group.long 0x67C++0x1B line.long 0x0 "OTG_HCDMAB11," sif (cpuis("STM32MP13*")) hexmask.long 0x0 0.--31. 1. "HCDMAB,DMA address" endif sif (cpuis("STM32MP151*")) hexmask.long 0x0 0.--31. 1. "HCDMAB,HCDMAB" newline endif sif (cpuis("STM32MP153*")) hexmask.long 0x0 0.--31. 1. "HCDMAB,HCDMAB" endif sif (cpuis("STM32MP157*")) hexmask.long 0x0 0.--31. 1. "HCDMAB,HCDMAB" endif line.long 0x4 "OTG_HCCHAR12," sif (cpuis("STM32MP13*")) bitfld.long 0x4 31. "CHENA,Channel enable" "0: Indicates that the descriptor structure is not..,1: Indicates that the descriptor structure and data.." bitfld.long 0x4 29. "ODDFRM,Odd frame" "0: Even frame,1: Odd frame" newline bitfld.long 0x4 20.--21. "MCNT,Multicount" "0: Reserved. This field yields undefined results,1: 1 transaction,2: 2 transactions per frame to be issued for this..,3: 3 transactions per frame to be issued for this.." bitfld.long 0x4 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt" newline bitfld.long 0x4 15. "EPDIR,Endpoint direction" "0: OUT,1: IN" endif sif (cpuis("STM32MP151*")) bitfld.long 0x4 31. "CHENA,CHENA" "0,1" newline endif sif (cpuis("STM32MP153*")) bitfld.long 0x4 31. "CHENA,CHENA" "0,1" endif sif (cpuis("STM32MP157*")) bitfld.long 0x4 31. "CHENA,CHENA" "0,1" newline endif bitfld.long 0x4 30. "CHDIS,Channel disable" "0,1" hexmask.long.byte 0x4 22.--28. 1. "DAD,Device address" newline sif (cpuis("STM32MP151*")) bitfld.long 0x4 20.--21. "MCNT,MCNT" "0,1,2,3" bitfld.long 0x4 18.--19. "EPTYP,EPTYP" "0,1,2,3" newline endif sif (cpuis("STM32MP153*")) bitfld.long 0x4 20.--21. "MCNT,MCNT" "0,1,2,3" bitfld.long 0x4 18.--19. "EPTYP,EPTYP" "0,1,2,3" newline endif sif (cpuis("STM32MP157*")) bitfld.long 0x4 20.--21. "MCNT,MCNT" "0,1,2,3" bitfld.long 0x4 18.--19. "EPTYP,EPTYP" "0,1,2,3" newline endif bitfld.long 0x4 17. "LSDEV,Low-speed device" "0,1" sif (cpuis("STM32MP151*")) bitfld.long 0x4 15. "EPDIR,EPDIR" "0,1" newline endif sif (cpuis("STM32MP153*")) bitfld.long 0x4 15. "EPDIR,EPDIR" "0,1" endif sif (cpuis("STM32MP157*")) bitfld.long 0x4 15. "EPDIR,EPDIR" "0,1" newline endif hexmask.long.byte 0x4 11.--14. 1. "EPNUM,Endpoint number" hexmask.long.word 0x4 0.--10. 1. "MPSIZ,Maximum packet size" line.long 0x8 "OTG_HCSPLT12," bitfld.long 0x8 31. "SPLITEN,Split enable" "0,1" bitfld.long 0x8 16. "COMPLSPLT,Do complete split" "0,1" newline sif (cpuis("STM32MP13*")) bitfld.long 0x8 14.--15. "XACTPOS,Transaction position" "0: Mid. This is the middle payload of this..,1: End. This is the last payload of this..,2: Begin. This is the first data payload of this..,3: All. This is the entire data payload of this.." endif sif (cpuis("STM32MP151*")) bitfld.long 0x8 14.--15. "XACTPOS,XACTPOS" "0,1,2,3" newline endif sif (cpuis("STM32MP153*")) bitfld.long 0x8 14.--15. "XACTPOS,XACTPOS" "0,1,2,3" endif sif (cpuis("STM32MP157*")) bitfld.long 0x8 14.--15. "XACTPOS,XACTPOS" "0,1,2,3" newline endif hexmask.long.byte 0x8 7.--13. 1. "HUBADDR,Hub address" hexmask.long.byte 0x8 0.--6. 1. "PRTADDR,Port address" line.long 0xC "OTG_HCINT12,OTG host channel 12 interrupt register" bitfld.long 0xC 13. "DESCLSTROLL,Descriptor rollover interrupt." "0,1" bitfld.long 0xC 12. "XCSXACTERR,Excessive transaction error." "0,1" newline bitfld.long 0xC 11. "BNA,Buffer not available interrupt." "0,1" bitfld.long 0xC 10. "DTERR,Data toggle error. In Scatter/Gather DMA mode the interrupt due to this bit is masked." "0,1" newline bitfld.long 0xC 9. "FRMOR,Frame overrun. In Scatter/Gather DMA mode the interrupt due to this bit is masked." "0,1" bitfld.long 0xC 8. "BBERR,Babble error. In Scatter/Gather DMA mode the interrupt due to this bit is masked." "0,1" newline bitfld.long 0xC 7. "TXERR,Transaction error. In Scatter/Gather DMA mode the interrupt due to this bit is masked." "0,1" bitfld.long 0xC 6. "NYET,Not yet ready response received interrupt. In Scatter/Gather DMA mode the interrupt due to this bit is masked." "0,1" newline bitfld.long 0xC 5. "ACK,ACK response received/transmitted interrupt. In Scatter/Gather DMA mode the interrupt due to this bit is masked." "0,1" bitfld.long 0xC 4. "NAK,NAK response received interrupt. In Scatter/Gather DMA mode the interrupt due to this bit is masked." "0,1" newline bitfld.long 0xC 3. "STALL,STALL response received interrupt. In Scatter/Gather DMA mode the interrupt due to this bit is masked." "0,1" bitfld.long 0xC 2. "AHBERR,AHB error" "0,1" newline bitfld.long 0xC 1. "CHH,Channel halted." "0,1" bitfld.long 0xC 0. "XFRC,Transfer completed." "0,1" line.long 0x10 "OTG_HCINTMSK12,OTG host channel 12 interrupt mask register" bitfld.long 0x10 13. "DESCLSTROLLMSK,Descriptor rollover interrupt mask register." "0,1" bitfld.long 0x10 11. "BNAMSK,Buffer not available interrupt mask register." "0,1" newline sif (cpuis("STM32MP13*")) bitfld.long 0x10 10. "DTERRM,Data toggle error mask. In Scatter/Gather DMA mode the interrupt due to this bit is masked." "0: Masked interrupt,1: Unmasked interrupt" bitfld.long 0x10 9. "FRMORM,Frame overrun mask. In Scatter/Gather DMA mode the interrupt due to this bit is masked." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x10 8. "BBERRM,Babble error mask. In Scatter/Gather DMA mode the interrupt due to this bit is masked." "0: Masked interrupt,1: Unmasked interrupt" bitfld.long 0x10 7. "TXERRM,Transaction error mask. In Scatter/Gather DMA mode the interrupt due to this bit is masked." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x10 6. "NYET,response received interrupt mask. In Scatter/Gather DMA mode the interrupt due to this bit is masked." "0: Masked interrupt,1: Unmasked interrupt" bitfld.long 0x10 5. "ACKM,ACK response received/transmitted interrupt mask. In Scatter/Gather DMA mode the interrupt due to this bit is masked." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x10 4. "NAKM,NAK response received interrupt mask. In Scatter/Gather DMA mode the interrupt due to this bit is masked." "0: Masked interrupt,1: Unmasked interrupt" bitfld.long 0x10 3. "STALLM,STALL response received interrupt mask. In Scatter/Gather DMA mode the interrupt due to this bit is masked." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x10 2. "AHBERRM,AHB error. In scatter/gather DMA mode for host interrupts will not be generated due to the corresponding bits set in OTG_HCINTx." "0: Masked interrupt,1: Unmasked interrupt" bitfld.long 0x10 1. "CHHM,Channel halted mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x10 0. "XFRCM,Transfer completed mask" "0: Masked interrupt,1: Unmasked interrupt" endif sif (cpuis("STM32MP151*")) bitfld.long 0x10 10. "DTERRM,DTERRM" "0,1" newline bitfld.long 0x10 9. "FRMORM,FRMORM" "0,1" bitfld.long 0x10 8. "BBERRM,BBERRM" "0,1" newline bitfld.long 0x10 7. "TXERRM,TXERRM" "0,1" bitfld.long 0x10 6. "NYET,NYET" "0,1" newline bitfld.long 0x10 5. "ACKM,ACKM" "0,1" bitfld.long 0x10 4. "NAKM,NAKM" "0,1" newline bitfld.long 0x10 3. "STALLM,STALLM" "0,1" bitfld.long 0x10 2. "AHBERRM,AHBERRM" "0,1" newline bitfld.long 0x10 1. "CHHM,CHHM" "0,1" endif sif (cpuis("STM32MP153*")) bitfld.long 0x10 10. "DTERRM,DTERRM" "0,1" newline bitfld.long 0x10 9. "FRMORM,FRMORM" "0,1" bitfld.long 0x10 8. "BBERRM,BBERRM" "0,1" newline bitfld.long 0x10 7. "TXERRM,TXERRM" "0,1" bitfld.long 0x10 6. "NYET,NYET" "0,1" newline bitfld.long 0x10 5. "ACKM,ACKM" "0,1" bitfld.long 0x10 4. "NAKM,NAKM" "0,1" newline bitfld.long 0x10 3. "STALLM,STALLM" "0,1" bitfld.long 0x10 2. "AHBERRM,AHBERRM" "0,1" newline bitfld.long 0x10 1. "CHHM,CHHM" "0,1" bitfld.long 0x10 0. "XFRCM,XFRCM" "0,1" newline endif sif (cpuis("STM32MP157*")) bitfld.long 0x10 10. "DTERRM,DTERRM" "0,1" bitfld.long 0x10 9. "FRMORM,FRMORM" "0,1" newline bitfld.long 0x10 8. "BBERRM,BBERRM" "0,1" bitfld.long 0x10 7. "TXERRM,TXERRM" "0,1" newline bitfld.long 0x10 6. "NYET,NYET" "0,1" bitfld.long 0x10 5. "ACKM,ACKM" "0,1" newline bitfld.long 0x10 4. "NAKM,NAKM" "0,1" bitfld.long 0x10 3. "STALLM,STALLM" "0,1" newline bitfld.long 0x10 2. "AHBERRM,AHBERRM" "0,1" bitfld.long 0x10 1. "CHHM,CHHM" "0,1" newline bitfld.long 0x10 0. "XFRCM,XFRCM" "0,1" endif line.long 0x14 "OTG_HCTSIZ12," sif (cpuis("STM32MP13*")) bitfld.long 0x14 31. "DOPNG,Do Ping" "0,1" bitfld.long 0x14 29.--30. "DPID,Data PID" "0: DATA0,1: DATA2,2: DATA1,3: SETUP (control) / MDATA (non-control)" newline endif sif (cpuis("STM32MP151*")) bitfld.long 0x14 29.--30. "DPID,DPID" "0,1,2,3" endif sif (cpuis("STM32MP153*")) bitfld.long 0x14 29.--30. "DPID,DPID" "0,1,2,3" newline endif sif (cpuis("STM32MP157*")) bitfld.long 0x14 29.--30. "DPID,DPID" "0,1,2,3" endif hexmask.long.word 0x14 19.--28. 1. "PKTCNT,Packet count" newline hexmask.long.tbyte 0x14 0.--18. 1. "XFRSIZ,Transfer size" line.long 0x18 "OTG_HCDMA12," hexmask.long 0x18 0.--31. 1. "DMAADDR,DMA address" group.long 0x69C++0x1B line.long 0x0 "OTG_HCDMAB12," sif (cpuis("STM32MP13*")) hexmask.long 0x0 0.--31. 1. "HCDMAB,DMA address" endif sif (cpuis("STM32MP151*")) hexmask.long 0x0 0.--31. 1. "HCDMAB,HCDMAB" newline endif sif (cpuis("STM32MP153*")) hexmask.long 0x0 0.--31. 1. "HCDMAB,HCDMAB" endif sif (cpuis("STM32MP157*")) hexmask.long 0x0 0.--31. 1. "HCDMAB,HCDMAB" endif line.long 0x4 "OTG_HCCHAR13," sif (cpuis("STM32MP13*")) bitfld.long 0x4 31. "CHENA,Channel enable" "0: Indicates that the descriptor structure is not..,1: Indicates that the descriptor structure and data.." bitfld.long 0x4 29. "ODDFRM,Odd frame" "0: Even frame,1: Odd frame" newline bitfld.long 0x4 20.--21. "MCNT,Multicount" "0: Reserved. This field yields undefined results,1: 1 transaction,2: 2 transactions per frame to be issued for this..,3: 3 transactions per frame to be issued for this.." bitfld.long 0x4 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt" newline bitfld.long 0x4 15. "EPDIR,Endpoint direction" "0: OUT,1: IN" endif sif (cpuis("STM32MP151*")) bitfld.long 0x4 31. "CHENA,CHENA" "0,1" newline endif sif (cpuis("STM32MP153*")) bitfld.long 0x4 31. "CHENA,CHENA" "0,1" endif sif (cpuis("STM32MP157*")) bitfld.long 0x4 31. "CHENA,CHENA" "0,1" newline endif bitfld.long 0x4 30. "CHDIS,Channel disable" "0,1" hexmask.long.byte 0x4 22.--28. 1. "DAD,Device address" newline sif (cpuis("STM32MP151*")) bitfld.long 0x4 20.--21. "MCNT,MCNT" "0,1,2,3" bitfld.long 0x4 18.--19. "EPTYP,EPTYP" "0,1,2,3" newline endif sif (cpuis("STM32MP153*")) bitfld.long 0x4 20.--21. "MCNT,MCNT" "0,1,2,3" bitfld.long 0x4 18.--19. "EPTYP,EPTYP" "0,1,2,3" newline endif sif (cpuis("STM32MP157*")) bitfld.long 0x4 20.--21. "MCNT,MCNT" "0,1,2,3" bitfld.long 0x4 18.--19. "EPTYP,EPTYP" "0,1,2,3" newline endif bitfld.long 0x4 17. "LSDEV,Low-speed device" "0,1" sif (cpuis("STM32MP151*")) bitfld.long 0x4 15. "EPDIR,EPDIR" "0,1" newline endif sif (cpuis("STM32MP153*")) bitfld.long 0x4 15. "EPDIR,EPDIR" "0,1" endif sif (cpuis("STM32MP157*")) bitfld.long 0x4 15. "EPDIR,EPDIR" "0,1" newline endif hexmask.long.byte 0x4 11.--14. 1. "EPNUM,Endpoint number" hexmask.long.word 0x4 0.--10. 1. "MPSIZ,Maximum packet size" line.long 0x8 "OTG_HCSPLT13," bitfld.long 0x8 31. "SPLITEN,Split enable" "0,1" bitfld.long 0x8 16. "COMPLSPLT,Do complete split" "0,1" newline sif (cpuis("STM32MP13*")) bitfld.long 0x8 14.--15. "XACTPOS,Transaction position" "0: Mid. This is the middle payload of this..,1: End. This is the last payload of this..,2: Begin. This is the first data payload of this..,3: All. This is the entire data payload of this.." endif sif (cpuis("STM32MP151*")) bitfld.long 0x8 14.--15. "XACTPOS,XACTPOS" "0,1,2,3" newline endif sif (cpuis("STM32MP153*")) bitfld.long 0x8 14.--15. "XACTPOS,XACTPOS" "0,1,2,3" endif sif (cpuis("STM32MP157*")) bitfld.long 0x8 14.--15. "XACTPOS,XACTPOS" "0,1,2,3" newline endif hexmask.long.byte 0x8 7.--13. 1. "HUBADDR,Hub address" hexmask.long.byte 0x8 0.--6. 1. "PRTADDR,Port address" line.long 0xC "OTG_HCINT13,OTG host channel 13 interrupt register" bitfld.long 0xC 13. "DESCLSTROLL,Descriptor rollover interrupt." "0,1" bitfld.long 0xC 12. "XCSXACTERR,Excessive transaction error." "0,1" newline bitfld.long 0xC 11. "BNA,Buffer not available interrupt." "0,1" bitfld.long 0xC 10. "DTERR,Data toggle error. In Scatter/Gather DMA mode the interrupt due to this bit is masked." "0,1" newline bitfld.long 0xC 9. "FRMOR,Frame overrun. In Scatter/Gather DMA mode the interrupt due to this bit is masked." "0,1" bitfld.long 0xC 8. "BBERR,Babble error. In Scatter/Gather DMA mode the interrupt due to this bit is masked." "0,1" newline bitfld.long 0xC 7. "TXERR,Transaction error. In Scatter/Gather DMA mode the interrupt due to this bit is masked." "0,1" bitfld.long 0xC 6. "NYET,Not yet ready response received interrupt. In Scatter/Gather DMA mode the interrupt due to this bit is masked." "0,1" newline bitfld.long 0xC 5. "ACK,ACK response received/transmitted interrupt. In Scatter/Gather DMA mode the interrupt due to this bit is masked." "0,1" bitfld.long 0xC 4. "NAK,NAK response received interrupt. In Scatter/Gather DMA mode the interrupt due to this bit is masked." "0,1" newline bitfld.long 0xC 3. "STALL,STALL response received interrupt. In Scatter/Gather DMA mode the interrupt due to this bit is masked." "0,1" bitfld.long 0xC 2. "AHBERR,AHB error" "0,1" newline bitfld.long 0xC 1. "CHH,Channel halted." "0,1" bitfld.long 0xC 0. "XFRC,Transfer completed." "0,1" line.long 0x10 "OTG_HCINTMSK13,OTG host channel 13 interrupt mask register" bitfld.long 0x10 13. "DESCLSTROLLMSK,Descriptor rollover interrupt mask register." "0,1" bitfld.long 0x10 11. "BNAMSK,Buffer not available interrupt mask register." "0,1" newline sif (cpuis("STM32MP13*")) bitfld.long 0x10 10. "DTERRM,Data toggle error mask. In Scatter/Gather DMA mode the interrupt due to this bit is masked." "0: Masked interrupt,1: Unmasked interrupt" bitfld.long 0x10 9. "FRMORM,Frame overrun mask. In Scatter/Gather DMA mode the interrupt due to this bit is masked." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x10 8. "BBERRM,Babble error mask. In Scatter/Gather DMA mode the interrupt due to this bit is masked." "0: Masked interrupt,1: Unmasked interrupt" bitfld.long 0x10 7. "TXERRM,Transaction error mask. In Scatter/Gather DMA mode the interrupt due to this bit is masked." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x10 6. "NYET,response received interrupt mask. In Scatter/Gather DMA mode the interrupt due to this bit is masked." "0: Masked interrupt,1: Unmasked interrupt" bitfld.long 0x10 5. "ACKM,ACK response received/transmitted interrupt mask. In Scatter/Gather DMA mode the interrupt due to this bit is masked." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x10 4. "NAKM,NAK response received interrupt mask. In Scatter/Gather DMA mode the interrupt due to this bit is masked." "0: Masked interrupt,1: Unmasked interrupt" bitfld.long 0x10 3. "STALLM,STALL response received interrupt mask. In Scatter/Gather DMA mode the interrupt due to this bit is masked." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x10 2. "AHBERRM,AHB error. In scatter/gather DMA mode for host interrupts will not be generated due to the corresponding bits set in OTG_HCINTx." "0: Masked interrupt,1: Unmasked interrupt" bitfld.long 0x10 1. "CHHM,Channel halted mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x10 0. "XFRCM,Transfer completed mask" "0: Masked interrupt,1: Unmasked interrupt" endif sif (cpuis("STM32MP151*")) bitfld.long 0x10 10. "DTERRM,DTERRM" "0,1" newline bitfld.long 0x10 9. "FRMORM,FRMORM" "0,1" bitfld.long 0x10 8. "BBERRM,BBERRM" "0,1" newline bitfld.long 0x10 7. "TXERRM,TXERRM" "0,1" bitfld.long 0x10 6. "NYET,NYET" "0,1" newline bitfld.long 0x10 5. "ACKM,ACKM" "0,1" bitfld.long 0x10 4. "NAKM,NAKM" "0,1" newline bitfld.long 0x10 3. "STALLM,STALLM" "0,1" bitfld.long 0x10 2. "AHBERRM,AHBERRM" "0,1" newline bitfld.long 0x10 1. "CHHM,CHHM" "0,1" endif sif (cpuis("STM32MP153*")) bitfld.long 0x10 10. "DTERRM,DTERRM" "0,1" newline bitfld.long 0x10 9. "FRMORM,FRMORM" "0,1" bitfld.long 0x10 8. "BBERRM,BBERRM" "0,1" newline bitfld.long 0x10 7. "TXERRM,TXERRM" "0,1" bitfld.long 0x10 6. "NYET,NYET" "0,1" newline bitfld.long 0x10 5. "ACKM,ACKM" "0,1" bitfld.long 0x10 4. "NAKM,NAKM" "0,1" newline bitfld.long 0x10 3. "STALLM,STALLM" "0,1" bitfld.long 0x10 2. "AHBERRM,AHBERRM" "0,1" newline bitfld.long 0x10 1. "CHHM,CHHM" "0,1" bitfld.long 0x10 0. "XFRCM,XFRCM" "0,1" newline endif sif (cpuis("STM32MP157*")) bitfld.long 0x10 10. "DTERRM,DTERRM" "0,1" bitfld.long 0x10 9. "FRMORM,FRMORM" "0,1" newline bitfld.long 0x10 8. "BBERRM,BBERRM" "0,1" bitfld.long 0x10 7. "TXERRM,TXERRM" "0,1" newline bitfld.long 0x10 6. "NYET,NYET" "0,1" bitfld.long 0x10 5. "ACKM,ACKM" "0,1" newline bitfld.long 0x10 4. "NAKM,NAKM" "0,1" bitfld.long 0x10 3. "STALLM,STALLM" "0,1" newline bitfld.long 0x10 2. "AHBERRM,AHBERRM" "0,1" bitfld.long 0x10 1. "CHHM,CHHM" "0,1" newline bitfld.long 0x10 0. "XFRCM,XFRCM" "0,1" endif line.long 0x14 "OTG_HCTSIZ13," sif (cpuis("STM32MP13*")) bitfld.long 0x14 31. "DOPNG,Do Ping" "0,1" bitfld.long 0x14 29.--30. "DPID,Data PID" "0: DATA0,1: DATA2,2: DATA1,3: SETUP (control) / MDATA (non-control)" newline endif sif (cpuis("STM32MP151*")) bitfld.long 0x14 29.--30. "DPID,DPID" "0,1,2,3" endif sif (cpuis("STM32MP153*")) bitfld.long 0x14 29.--30. "DPID,DPID" "0,1,2,3" newline endif sif (cpuis("STM32MP157*")) bitfld.long 0x14 29.--30. "DPID,DPID" "0,1,2,3" endif hexmask.long.word 0x14 19.--28. 1. "PKTCNT,Packet count" newline hexmask.long.tbyte 0x14 0.--18. 1. "XFRSIZ,Transfer size" line.long 0x18 "OTG_HCDMA13," hexmask.long 0x18 0.--31. 1. "DMAADDR,DMA address" group.long 0x6BC++0x1B line.long 0x0 "OTG_HCDMAB13," sif (cpuis("STM32MP13*")) hexmask.long 0x0 0.--31. 1. "HCDMAB,DMA address" endif sif (cpuis("STM32MP151*")) hexmask.long 0x0 0.--31. 1. "HCDMAB,HCDMAB" newline endif sif (cpuis("STM32MP153*")) hexmask.long 0x0 0.--31. 1. "HCDMAB,HCDMAB" endif sif (cpuis("STM32MP157*")) hexmask.long 0x0 0.--31. 1. "HCDMAB,HCDMAB" endif line.long 0x4 "OTG_HCCHAR14," sif (cpuis("STM32MP13*")) bitfld.long 0x4 31. "CHENA,Channel enable" "0: Indicates that the descriptor structure is not..,1: Indicates that the descriptor structure and data.." bitfld.long 0x4 29. "ODDFRM,Odd frame" "0: Even frame,1: Odd frame" newline bitfld.long 0x4 20.--21. "MCNT,Multicount" "0: Reserved. This field yields undefined results,1: 1 transaction,2: 2 transactions per frame to be issued for this..,3: 3 transactions per frame to be issued for this.." bitfld.long 0x4 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt" newline bitfld.long 0x4 15. "EPDIR,Endpoint direction" "0: OUT,1: IN" endif sif (cpuis("STM32MP151*")) bitfld.long 0x4 31. "CHENA,CHENA" "0,1" newline endif sif (cpuis("STM32MP153*")) bitfld.long 0x4 31. "CHENA,CHENA" "0,1" endif sif (cpuis("STM32MP157*")) bitfld.long 0x4 31. "CHENA,CHENA" "0,1" newline endif bitfld.long 0x4 30. "CHDIS,Channel disable" "0,1" hexmask.long.byte 0x4 22.--28. 1. "DAD,Device address" newline sif (cpuis("STM32MP151*")) bitfld.long 0x4 20.--21. "MCNT,MCNT" "0,1,2,3" bitfld.long 0x4 18.--19. "EPTYP,EPTYP" "0,1,2,3" newline endif sif (cpuis("STM32MP153*")) bitfld.long 0x4 20.--21. "MCNT,MCNT" "0,1,2,3" bitfld.long 0x4 18.--19. "EPTYP,EPTYP" "0,1,2,3" newline endif sif (cpuis("STM32MP157*")) bitfld.long 0x4 20.--21. "MCNT,MCNT" "0,1,2,3" bitfld.long 0x4 18.--19. "EPTYP,EPTYP" "0,1,2,3" newline endif bitfld.long 0x4 17. "LSDEV,Low-speed device" "0,1" sif (cpuis("STM32MP151*")) bitfld.long 0x4 15. "EPDIR,EPDIR" "0,1" newline endif sif (cpuis("STM32MP153*")) bitfld.long 0x4 15. "EPDIR,EPDIR" "0,1" endif sif (cpuis("STM32MP157*")) bitfld.long 0x4 15. "EPDIR,EPDIR" "0,1" newline endif hexmask.long.byte 0x4 11.--14. 1. "EPNUM,Endpoint number" hexmask.long.word 0x4 0.--10. 1. "MPSIZ,Maximum packet size" line.long 0x8 "OTG_HCSPLT14," bitfld.long 0x8 31. "SPLITEN,Split enable" "0,1" bitfld.long 0x8 16. "COMPLSPLT,Do complete split" "0,1" newline sif (cpuis("STM32MP13*")) bitfld.long 0x8 14.--15. "XACTPOS,Transaction position" "0: Mid. This is the middle payload of this..,1: End. This is the last payload of this..,2: Begin. This is the first data payload of this..,3: All. This is the entire data payload of this.." endif sif (cpuis("STM32MP151*")) bitfld.long 0x8 14.--15. "XACTPOS,XACTPOS" "0,1,2,3" newline endif sif (cpuis("STM32MP153*")) bitfld.long 0x8 14.--15. "XACTPOS,XACTPOS" "0,1,2,3" endif sif (cpuis("STM32MP157*")) bitfld.long 0x8 14.--15. "XACTPOS,XACTPOS" "0,1,2,3" newline endif hexmask.long.byte 0x8 7.--13. 1. "HUBADDR,Hub address" hexmask.long.byte 0x8 0.--6. 1. "PRTADDR,Port address" line.long 0xC "OTG_HCINT14,OTG host channel 14 interrupt register" bitfld.long 0xC 13. "DESCLSTROLL,Descriptor rollover interrupt." "0,1" bitfld.long 0xC 12. "XCSXACTERR,Excessive transaction error." "0,1" newline bitfld.long 0xC 11. "BNA,Buffer not available interrupt." "0,1" bitfld.long 0xC 10. "DTERR,Data toggle error. In Scatter/Gather DMA mode the interrupt due to this bit is masked." "0,1" newline bitfld.long 0xC 9. "FRMOR,Frame overrun. In Scatter/Gather DMA mode the interrupt due to this bit is masked." "0,1" bitfld.long 0xC 8. "BBERR,Babble error. In Scatter/Gather DMA mode the interrupt due to this bit is masked." "0,1" newline bitfld.long 0xC 7. "TXERR,Transaction error. In Scatter/Gather DMA mode the interrupt due to this bit is masked." "0,1" bitfld.long 0xC 6. "NYET,Not yet ready response received interrupt. In Scatter/Gather DMA mode the interrupt due to this bit is masked." "0,1" newline bitfld.long 0xC 5. "ACK,ACK response received/transmitted interrupt. In Scatter/Gather DMA mode the interrupt due to this bit is masked." "0,1" bitfld.long 0xC 4. "NAK,NAK response received interrupt. In Scatter/Gather DMA mode the interrupt due to this bit is masked." "0,1" newline bitfld.long 0xC 3. "STALL,STALL response received interrupt. In Scatter/Gather DMA mode the interrupt due to this bit is masked." "0,1" bitfld.long 0xC 2. "AHBERR,AHB error" "0,1" newline bitfld.long 0xC 1. "CHH,Channel halted." "0,1" bitfld.long 0xC 0. "XFRC,Transfer completed." "0,1" line.long 0x10 "OTG_HCINTMSK14,OTG host channel 14 interrupt mask register" bitfld.long 0x10 13. "DESCLSTROLLMSK,Descriptor rollover interrupt mask register." "0,1" bitfld.long 0x10 11. "BNAMSK,Buffer not available interrupt mask register." "0,1" newline sif (cpuis("STM32MP13*")) bitfld.long 0x10 10. "DTERRM,Data toggle error mask. In Scatter/Gather DMA mode the interrupt due to this bit is masked." "0: Masked interrupt,1: Unmasked interrupt" bitfld.long 0x10 9. "FRMORM,Frame overrun mask. In Scatter/Gather DMA mode the interrupt due to this bit is masked." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x10 8. "BBERRM,Babble error mask. In Scatter/Gather DMA mode the interrupt due to this bit is masked." "0: Masked interrupt,1: Unmasked interrupt" bitfld.long 0x10 7. "TXERRM,Transaction error mask. In Scatter/Gather DMA mode the interrupt due to this bit is masked." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x10 6. "NYET,response received interrupt mask. In Scatter/Gather DMA mode the interrupt due to this bit is masked." "0: Masked interrupt,1: Unmasked interrupt" bitfld.long 0x10 5. "ACKM,ACK response received/transmitted interrupt mask. In Scatter/Gather DMA mode the interrupt due to this bit is masked." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x10 4. "NAKM,NAK response received interrupt mask. In Scatter/Gather DMA mode the interrupt due to this bit is masked." "0: Masked interrupt,1: Unmasked interrupt" bitfld.long 0x10 3. "STALLM,STALL response received interrupt mask. In Scatter/Gather DMA mode the interrupt due to this bit is masked." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x10 2. "AHBERRM,AHB error. In scatter/gather DMA mode for host interrupts will not be generated due to the corresponding bits set in OTG_HCINTx." "0: Masked interrupt,1: Unmasked interrupt" bitfld.long 0x10 1. "CHHM,Channel halted mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x10 0. "XFRCM,Transfer completed mask" "0: Masked interrupt,1: Unmasked interrupt" endif sif (cpuis("STM32MP151*")) bitfld.long 0x10 10. "DTERRM,DTERRM" "0,1" newline bitfld.long 0x10 9. "FRMORM,FRMORM" "0,1" bitfld.long 0x10 8. "BBERRM,BBERRM" "0,1" newline bitfld.long 0x10 7. "TXERRM,TXERRM" "0,1" bitfld.long 0x10 6. "NYET,NYET" "0,1" newline bitfld.long 0x10 5. "ACKM,ACKM" "0,1" bitfld.long 0x10 4. "NAKM,NAKM" "0,1" newline bitfld.long 0x10 3. "STALLM,STALLM" "0,1" bitfld.long 0x10 2. "AHBERRM,AHBERRM" "0,1" newline bitfld.long 0x10 1. "CHHM,CHHM" "0,1" endif sif (cpuis("STM32MP153*")) bitfld.long 0x10 10. "DTERRM,DTERRM" "0,1" newline bitfld.long 0x10 9. "FRMORM,FRMORM" "0,1" bitfld.long 0x10 8. "BBERRM,BBERRM" "0,1" newline bitfld.long 0x10 7. "TXERRM,TXERRM" "0,1" bitfld.long 0x10 6. "NYET,NYET" "0,1" newline bitfld.long 0x10 5. "ACKM,ACKM" "0,1" bitfld.long 0x10 4. "NAKM,NAKM" "0,1" newline bitfld.long 0x10 3. "STALLM,STALLM" "0,1" bitfld.long 0x10 2. "AHBERRM,AHBERRM" "0,1" newline bitfld.long 0x10 1. "CHHM,CHHM" "0,1" bitfld.long 0x10 0. "XFRCM,XFRCM" "0,1" newline endif sif (cpuis("STM32MP157*")) bitfld.long 0x10 10. "DTERRM,DTERRM" "0,1" bitfld.long 0x10 9. "FRMORM,FRMORM" "0,1" newline bitfld.long 0x10 8. "BBERRM,BBERRM" "0,1" bitfld.long 0x10 7. "TXERRM,TXERRM" "0,1" newline bitfld.long 0x10 6. "NYET,NYET" "0,1" bitfld.long 0x10 5. "ACKM,ACKM" "0,1" newline bitfld.long 0x10 4. "NAKM,NAKM" "0,1" bitfld.long 0x10 3. "STALLM,STALLM" "0,1" newline bitfld.long 0x10 2. "AHBERRM,AHBERRM" "0,1" bitfld.long 0x10 1. "CHHM,CHHM" "0,1" newline bitfld.long 0x10 0. "XFRCM,XFRCM" "0,1" endif line.long 0x14 "OTG_HCTSIZ14," sif (cpuis("STM32MP13*")) bitfld.long 0x14 31. "DOPNG,Do Ping" "0,1" bitfld.long 0x14 29.--30. "DPID,Data PID" "0: DATA0,1: DATA2,2: DATA1,3: SETUP (control) / MDATA (non-control)" newline endif sif (cpuis("STM32MP151*")) bitfld.long 0x14 29.--30. "DPID,DPID" "0,1,2,3" endif sif (cpuis("STM32MP153*")) bitfld.long 0x14 29.--30. "DPID,DPID" "0,1,2,3" newline endif sif (cpuis("STM32MP157*")) bitfld.long 0x14 29.--30. "DPID,DPID" "0,1,2,3" endif hexmask.long.word 0x14 19.--28. 1. "PKTCNT,Packet count" newline hexmask.long.tbyte 0x14 0.--18. 1. "XFRSIZ,Transfer size" line.long 0x18 "OTG_HCDMA14," hexmask.long 0x18 0.--31. 1. "DMAADDR,DMA address" group.long 0x6DC++0x1B line.long 0x0 "OTG_HCDMAB14," sif (cpuis("STM32MP13*")) hexmask.long 0x0 0.--31. 1. "HCDMAB,DMA address" endif sif (cpuis("STM32MP151*")) hexmask.long 0x0 0.--31. 1. "HCDMAB,HCDMAB" newline endif sif (cpuis("STM32MP153*")) hexmask.long 0x0 0.--31. 1. "HCDMAB,HCDMAB" endif sif (cpuis("STM32MP157*")) hexmask.long 0x0 0.--31. 1. "HCDMAB,HCDMAB" endif line.long 0x4 "OTG_HCCHAR15," sif (cpuis("STM32MP13*")) bitfld.long 0x4 31. "CHENA,Channel enable" "0: Indicates that the descriptor structure is not..,1: Indicates that the descriptor structure and data.." bitfld.long 0x4 29. "ODDFRM,Odd frame" "0: Even frame,1: Odd frame" newline bitfld.long 0x4 20.--21. "MCNT,Multicount" "0: Reserved. This field yields undefined results,1: 1 transaction,2: 2 transactions per frame to be issued for this..,3: 3 transactions per frame to be issued for this.." bitfld.long 0x4 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt" newline bitfld.long 0x4 15. "EPDIR,Endpoint direction" "0: OUT,1: IN" endif sif (cpuis("STM32MP151*")) bitfld.long 0x4 31. "CHENA,CHENA" "0,1" newline endif sif (cpuis("STM32MP153*")) bitfld.long 0x4 31. "CHENA,CHENA" "0,1" endif sif (cpuis("STM32MP157*")) bitfld.long 0x4 31. "CHENA,CHENA" "0,1" newline endif bitfld.long 0x4 30. "CHDIS,Channel disable" "0,1" hexmask.long.byte 0x4 22.--28. 1. "DAD,Device address" newline sif (cpuis("STM32MP151*")) bitfld.long 0x4 20.--21. "MCNT,MCNT" "0,1,2,3" bitfld.long 0x4 18.--19. "EPTYP,EPTYP" "0,1,2,3" newline endif sif (cpuis("STM32MP153*")) bitfld.long 0x4 20.--21. "MCNT,MCNT" "0,1,2,3" bitfld.long 0x4 18.--19. "EPTYP,EPTYP" "0,1,2,3" newline endif sif (cpuis("STM32MP157*")) bitfld.long 0x4 20.--21. "MCNT,MCNT" "0,1,2,3" bitfld.long 0x4 18.--19. "EPTYP,EPTYP" "0,1,2,3" newline endif bitfld.long 0x4 17. "LSDEV,Low-speed device" "0,1" sif (cpuis("STM32MP151*")) bitfld.long 0x4 15. "EPDIR,EPDIR" "0,1" newline endif sif (cpuis("STM32MP153*")) bitfld.long 0x4 15. "EPDIR,EPDIR" "0,1" endif sif (cpuis("STM32MP157*")) bitfld.long 0x4 15. "EPDIR,EPDIR" "0,1" newline endif hexmask.long.byte 0x4 11.--14. 1. "EPNUM,Endpoint number" hexmask.long.word 0x4 0.--10. 1. "MPSIZ,Maximum packet size" line.long 0x8 "OTG_HCSPLT15," bitfld.long 0x8 31. "SPLITEN,Split enable" "0,1" bitfld.long 0x8 16. "COMPLSPLT,Do complete split" "0,1" newline sif (cpuis("STM32MP13*")) bitfld.long 0x8 14.--15. "XACTPOS,Transaction position" "0: Mid. This is the middle payload of this..,1: End. This is the last payload of this..,2: Begin. This is the first data payload of this..,3: All. This is the entire data payload of this.." endif sif (cpuis("STM32MP151*")) bitfld.long 0x8 14.--15. "XACTPOS,XACTPOS" "0,1,2,3" newline endif sif (cpuis("STM32MP153*")) bitfld.long 0x8 14.--15. "XACTPOS,XACTPOS" "0,1,2,3" endif sif (cpuis("STM32MP157*")) bitfld.long 0x8 14.--15. "XACTPOS,XACTPOS" "0,1,2,3" newline endif hexmask.long.byte 0x8 7.--13. 1. "HUBADDR,Hub address" hexmask.long.byte 0x8 0.--6. 1. "PRTADDR,Port address" line.long 0xC "OTG_HCINT15,OTG host channel 15 interrupt register" bitfld.long 0xC 13. "DESCLSTROLL,Descriptor rollover interrupt." "0,1" bitfld.long 0xC 12. "XCSXACTERR,Excessive transaction error." "0,1" newline bitfld.long 0xC 11. "BNA,Buffer not available interrupt." "0,1" bitfld.long 0xC 10. "DTERR,Data toggle error. In Scatter/Gather DMA mode the interrupt due to this bit is masked." "0,1" newline bitfld.long 0xC 9. "FRMOR,Frame overrun. In Scatter/Gather DMA mode the interrupt due to this bit is masked." "0,1" bitfld.long 0xC 8. "BBERR,Babble error. In Scatter/Gather DMA mode the interrupt due to this bit is masked." "0,1" newline bitfld.long 0xC 7. "TXERR,Transaction error. In Scatter/Gather DMA mode the interrupt due to this bit is masked." "0,1" bitfld.long 0xC 6. "NYET,Not yet ready response received interrupt. In Scatter/Gather DMA mode the interrupt due to this bit is masked." "0,1" newline bitfld.long 0xC 5. "ACK,ACK response received/transmitted interrupt. In Scatter/Gather DMA mode the interrupt due to this bit is masked." "0,1" bitfld.long 0xC 4. "NAK,NAK response received interrupt. In Scatter/Gather DMA mode the interrupt due to this bit is masked." "0,1" newline bitfld.long 0xC 3. "STALL,STALL response received interrupt. In Scatter/Gather DMA mode the interrupt due to this bit is masked." "0,1" bitfld.long 0xC 2. "AHBERR,AHB error" "0,1" newline bitfld.long 0xC 1. "CHH,Channel halted." "0,1" bitfld.long 0xC 0. "XFRC,Transfer completed." "0,1" line.long 0x10 "OTG_HCINTMSK15,OTG host channel 15 interrupt mask register" bitfld.long 0x10 13. "DESCLSTROLLMSK,Descriptor rollover interrupt mask register." "0,1" bitfld.long 0x10 11. "BNAMSK,Buffer not available interrupt mask register." "0,1" newline sif (cpuis("STM32MP13*")) bitfld.long 0x10 10. "DTERRM,Data toggle error mask. In Scatter/Gather DMA mode the interrupt due to this bit is masked." "0: Masked interrupt,1: Unmasked interrupt" bitfld.long 0x10 9. "FRMORM,Frame overrun mask. In Scatter/Gather DMA mode the interrupt due to this bit is masked." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x10 8. "BBERRM,Babble error mask. In Scatter/Gather DMA mode the interrupt due to this bit is masked." "0: Masked interrupt,1: Unmasked interrupt" bitfld.long 0x10 7. "TXERRM,Transaction error mask. In Scatter/Gather DMA mode the interrupt due to this bit is masked." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x10 6. "NYET,response received interrupt mask. In Scatter/Gather DMA mode the interrupt due to this bit is masked." "0: Masked interrupt,1: Unmasked interrupt" bitfld.long 0x10 5. "ACKM,ACK response received/transmitted interrupt mask. In Scatter/Gather DMA mode the interrupt due to this bit is masked." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x10 4. "NAKM,NAK response received interrupt mask. In Scatter/Gather DMA mode the interrupt due to this bit is masked." "0: Masked interrupt,1: Unmasked interrupt" bitfld.long 0x10 3. "STALLM,STALL response received interrupt mask. In Scatter/Gather DMA mode the interrupt due to this bit is masked." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x10 2. "AHBERRM,AHB error. In scatter/gather DMA mode for host interrupts will not be generated due to the corresponding bits set in OTG_HCINTx." "0: Masked interrupt,1: Unmasked interrupt" bitfld.long 0x10 1. "CHHM,Channel halted mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x10 0. "XFRCM,Transfer completed mask" "0: Masked interrupt,1: Unmasked interrupt" endif sif (cpuis("STM32MP151*")) bitfld.long 0x10 10. "DTERRM,DTERRM" "0,1" newline bitfld.long 0x10 9. "FRMORM,FRMORM" "0,1" bitfld.long 0x10 8. "BBERRM,BBERRM" "0,1" newline bitfld.long 0x10 7. "TXERRM,TXERRM" "0,1" bitfld.long 0x10 6. "NYET,NYET" "0,1" newline bitfld.long 0x10 5. "ACKM,ACKM" "0,1" bitfld.long 0x10 4. "NAKM,NAKM" "0,1" newline bitfld.long 0x10 3. "STALLM,STALLM" "0,1" bitfld.long 0x10 2. "AHBERRM,AHBERRM" "0,1" newline bitfld.long 0x10 1. "CHHM,CHHM" "0,1" endif sif (cpuis("STM32MP153*")) bitfld.long 0x10 10. "DTERRM,DTERRM" "0,1" newline bitfld.long 0x10 9. "FRMORM,FRMORM" "0,1" bitfld.long 0x10 8. "BBERRM,BBERRM" "0,1" newline bitfld.long 0x10 7. "TXERRM,TXERRM" "0,1" bitfld.long 0x10 6. "NYET,NYET" "0,1" newline bitfld.long 0x10 5. "ACKM,ACKM" "0,1" bitfld.long 0x10 4. "NAKM,NAKM" "0,1" newline bitfld.long 0x10 3. "STALLM,STALLM" "0,1" bitfld.long 0x10 2. "AHBERRM,AHBERRM" "0,1" newline bitfld.long 0x10 1. "CHHM,CHHM" "0,1" bitfld.long 0x10 0. "XFRCM,XFRCM" "0,1" newline endif sif (cpuis("STM32MP157*")) bitfld.long 0x10 10. "DTERRM,DTERRM" "0,1" bitfld.long 0x10 9. "FRMORM,FRMORM" "0,1" newline bitfld.long 0x10 8. "BBERRM,BBERRM" "0,1" bitfld.long 0x10 7. "TXERRM,TXERRM" "0,1" newline bitfld.long 0x10 6. "NYET,NYET" "0,1" bitfld.long 0x10 5. "ACKM,ACKM" "0,1" newline bitfld.long 0x10 4. "NAKM,NAKM" "0,1" bitfld.long 0x10 3. "STALLM,STALLM" "0,1" newline bitfld.long 0x10 2. "AHBERRM,AHBERRM" "0,1" bitfld.long 0x10 1. "CHHM,CHHM" "0,1" newline bitfld.long 0x10 0. "XFRCM,XFRCM" "0,1" endif line.long 0x14 "OTG_HCTSIZ15," sif (cpuis("STM32MP13*")) bitfld.long 0x14 31. "DOPNG,Do Ping" "0,1" bitfld.long 0x14 29.--30. "DPID,Data PID" "0: DATA0,1: DATA2,2: DATA1,3: SETUP (control) / MDATA (non-control)" newline endif sif (cpuis("STM32MP151*")) bitfld.long 0x14 29.--30. "DPID,DPID" "0,1,2,3" endif sif (cpuis("STM32MP153*")) bitfld.long 0x14 29.--30. "DPID,DPID" "0,1,2,3" newline endif sif (cpuis("STM32MP157*")) bitfld.long 0x14 29.--30. "DPID,DPID" "0,1,2,3" endif hexmask.long.word 0x14 19.--28. 1. "PKTCNT,Packet count" newline hexmask.long.tbyte 0x14 0.--18. 1. "XFRSIZ,Transfer size" line.long 0x18 "OTG_HCDMA15," hexmask.long 0x18 0.--31. 1. "DMAADDR,DMA address" group.long 0x6FC++0x3 line.long 0x0 "OTG_HCDMAB15," sif (cpuis("STM32MP13*")) hexmask.long 0x0 0.--31. 1. "HCDMAB,DMA address" endif sif (cpuis("STM32MP151*")) hexmask.long 0x0 0.--31. 1. "HCDMAB,HCDMAB" newline endif sif (cpuis("STM32MP153*")) hexmask.long 0x0 0.--31. 1. "HCDMAB,HCDMAB" endif sif (cpuis("STM32MP157*")) hexmask.long 0x0 0.--31. 1. "HCDMAB,HCDMAB" endif group.long 0x800++0xB line.long 0x0 "OTG_DCFG,OTG device configuration register" sif (cpuis("STM32MP13*")) bitfld.long 0x0 24.--25. "PERSCHIVL,Periodic schedule interval" "0: 25% of (micro)frame,1: 50% of (micro)frame,2: 75% of (micro)frame,?" bitfld.long 0x0 23. "DESCDMA,Enable scatter/gather DMA in device mode" "0: Buffer DMA mode,1: Scatter/Gather DMA mode" newline bitfld.long 0x0 15. "ERRATIM,Erratic error interrupt mask" "0: Early suspend interrupt is generated on erratic..,1: Mask early suspend interrupt on erratic error" bitfld.long 0x0 11.--12. "PFIVL,Periodic frame interval" "0: 80% of the frame interval,1: 85% of the frame interval,2: 90% of the frame interval,3: 95% of the frame interval" newline bitfld.long 0x0 2. "NZLSOHSK,Non-zero-length status OUT handshake" "0: Send the received OUT packet to the application..,1: Send a STALL handshake on a nonzero-length.." bitfld.long 0x0 0.--1. "DSPD,Device speed" "0: High speed,1: Full speed,?,?" newline endif sif (cpuis("STM32MP151*")) bitfld.long 0x0 24.--25. "PERSCHIVL,PERSCHIVL" "0,1,2,3" endif sif (cpuis("STM32MP153*")) bitfld.long 0x0 24.--25. "PERSCHIVL,PERSCHIVL" "0,1,2,3" newline endif sif (cpuis("STM32MP157*")) bitfld.long 0x0 24.--25. "PERSCHIVL,PERSCHIVL" "0,1,2,3" endif sif (cpuis("STM32MP151*")) bitfld.long 0x0 15. "ERRATIM,ERRATIM" "0,1" newline bitfld.long 0x0 14. "XCVRDLY,XCVRDLY" "0,1" endif sif (cpuis("STM32MP153*")) bitfld.long 0x0 15. "ERRATIM,ERRATIM" "0,1" newline bitfld.long 0x0 14. "XCVRDLY,XCVRDLY" "0,1" endif sif (cpuis("STM32MP157*")) bitfld.long 0x0 15. "ERRATIM,ERRATIM" "0,1" newline bitfld.long 0x0 14. "XCVRDLY,XCVRDLY" "0,1" endif sif (cpuis("STM32MP151*")) bitfld.long 0x0 11.--12. "PFIVL,PFIVL" "0,1,2,3" newline endif sif (cpuis("STM32MP153*")) bitfld.long 0x0 11.--12. "PFIVL,PFIVL" "0,1,2,3" endif sif (cpuis("STM32MP157*")) bitfld.long 0x0 11.--12. "PFIVL,PFIVL" "0,1,2,3" newline endif hexmask.long.byte 0x0 4.--10. 1. "DAD,Device address" sif (cpuis("STM32MP151*")) bitfld.long 0x0 2. "NZLSOHSK,NZLSOHSK" "0,1" newline endif sif (cpuis("STM32MP153*")) bitfld.long 0x0 2. "NZLSOHSK,NZLSOHSK" "0,1" bitfld.long 0x0 0.--1. "DSPD,DSPD" "0,1,2,3" newline endif sif (cpuis("STM32MP157*")) bitfld.long 0x0 2. "NZLSOHSK,NZLSOHSK" "0,1" bitfld.long 0x0 0.--1. "DSPD,DSPD" "0,1,2,3" endif line.long 0x4 "OTG_DCTL," bitfld.long 0x4 18. "DSBESLRJCT,Deep sleep BESL reject" "0,1" sif (cpuis("STM32MP13*")) bitfld.long 0x4 17. "ENCONTONBNA,Enable continue on BNA" "0: After receiving BNA interrupt the core disables..,1: After receiving BNA interrupt the core disables.." newline bitfld.long 0x4 4.--6. "TCTL,Test control" "0: Test mode disabled,1: Test_J mode,2: Test_K mode,3: Test_SE0_NAK mode,4: Test_Packet mode,5: Test_Force_Enable,?,?" rbitfld.long 0x4 3. "GONSTS,Global OUT NAK status" "0: A handshake is sent based on the FIFO status and..,1: No data is written to the Rx FIFO irrespective.." newline rbitfld.long 0x4 2. "GINSTS,Global IN NAK status" "0: A handshake is sent out based on the data..,1: A NAK handshake is sent out on all non-periodic.." bitfld.long 0x4 1. "SDIS,Soft disconnect" "0: Normal operation. When this bit is cleared after..,1: The core generates a device disconnect event to.." newline endif bitfld.long 0x4 11. "POPRGDNE,Power-on programming done" "0,1" bitfld.long 0x4 10. "CGONAK,Clear global OUT NAK" "0,1" newline bitfld.long 0x4 9. "SGONAK,Set global OUT NAK" "0,1" bitfld.long 0x4 8. "CGINAK,Clear global IN NAK" "0,1" newline bitfld.long 0x4 7. "SGINAK,Set global IN NAK" "0,1" sif (cpuis("STM32MP151*")) bitfld.long 0x4 4.--6. "TCTL,TCTL" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x4 3. "GONSTS,GONSTS" "0,1" rbitfld.long 0x4 2. "GINSTS,GINSTS" "0,1" newline bitfld.long 0x4 1. "SDIS,SDIS" "0,1" endif sif (cpuis("STM32MP153*")) bitfld.long 0x4 4.--6. "TCTL,TCTL" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x4 3. "GONSTS,GONSTS" "0,1" rbitfld.long 0x4 2. "GINSTS,GINSTS" "0,1" newline bitfld.long 0x4 1. "SDIS,SDIS" "0,1" endif sif (cpuis("STM32MP157*")) bitfld.long 0x4 4.--6. "TCTL,TCTL" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x4 3. "GONSTS,GONSTS" "0,1" rbitfld.long 0x4 2. "GINSTS,GINSTS" "0,1" newline bitfld.long 0x4 1. "SDIS,SDIS" "0,1" endif bitfld.long 0x4 0. "RWUSIG,Remote wakeup signaling" "0,1" line.long 0x8 "OTG_DSTS,OTG device status register" sif (cpuis("STM32MP13*")) rbitfld.long 0x8 22.--23. "DEVLNSTS,Device line status" "0,1,2,3" hexmask.long.word 0x8 8.--21. 1. "FNSOF,Frame number of the received SOF" newline rbitfld.long 0x8 3. "EERR,Erratic error" "0,1" rbitfld.long 0x8 1.--2. "ENUMSPD,Enumerated speed" "0: High Speed,1: Full Speed,?,?" newline rbitfld.long 0x8 0. "SUSPSTS,Suspend status" "0,1" endif sif (cpuis("STM32MP151*")) bitfld.long 0x8 22.--23. "DEVLNSTS,DEVLNSTS" "0,1,2,3" newline hexmask.long.word 0x8 8.--21. 1. "FNSOF,FNSOF" endif sif (cpuis("STM32MP153*")) bitfld.long 0x8 22.--23. "DEVLNSTS,DEVLNSTS" "0,1,2,3" newline hexmask.long.word 0x8 8.--21. 1. "FNSOF,FNSOF" endif sif (cpuis("STM32MP157*")) bitfld.long 0x8 22.--23. "DEVLNSTS,DEVLNSTS" "0,1,2,3" newline hexmask.long.word 0x8 8.--21. 1. "FNSOF,FNSOF" endif sif (cpuis("STM32MP151*")) bitfld.long 0x8 3. "EERR,EERR" "0,1" newline bitfld.long 0x8 1.--2. "ENUMSPD,ENUMSPD" "0,1,2,3" bitfld.long 0x8 0. "SUSPSTS,SUSPSTS" "0,1" newline endif sif (cpuis("STM32MP153*")) bitfld.long 0x8 3. "EERR,EERR" "0,1" bitfld.long 0x8 1.--2. "ENUMSPD,ENUMSPD" "0,1,2,3" newline bitfld.long 0x8 0. "SUSPSTS,SUSPSTS" "0,1" endif sif (cpuis("STM32MP157*")) bitfld.long 0x8 3. "EERR,EERR" "0,1" newline bitfld.long 0x8 1.--2. "ENUMSPD,ENUMSPD" "0,1,2,3" bitfld.long 0x8 0. "SUSPSTS,SUSPSTS" "0,1" endif group.long 0x810++0xF line.long 0x0 "OTG_DIEPMSK,OTG device IN endpoint common interrupt mask register" sif (cpuis("STM32MP13*")) bitfld.long 0x0 13. "NAKM,NAK interrupt mask" "0: Masked interrupt,1: Unmasked interrupt" bitfld.long 0x0 9. "BNAM,BNA interrupt mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x0 8. "TXFURM,FIFO underrun mask" "0: Masked interrupt,1: Unmasked interrupt" bitfld.long 0x0 6. "INEPNEM,IN endpoint NAK effective mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x0 5. "INEPNMM,IN token received with EP mismatch mask" "0: Masked interrupt,1: Unmasked interrupt" bitfld.long 0x0 4. "ITTXFEMSK,IN token received when Tx FIFO empty mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x0 3. "TOM,Timeout condition mask (Non-isochronous endpoints)" "0: Masked interrupt,1: Unmasked interrupt" bitfld.long 0x0 2. "AHBERRM,AHB error mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x0 1. "EPDM,Endpoint disabled interrupt mask" "0: Masked interrupt,1: Unmasked interrupt" bitfld.long 0x0 0. "XFRCM,Transfer completed interrupt mask" "0: Masked interrupt,1: Unmasked interrupt" newline endif sif (cpuis("STM32MP151*")) bitfld.long 0x0 13. "NAKM,NAKM" "0,1" endif sif (cpuis("STM32MP153*")) bitfld.long 0x0 13. "NAKM,NAKM" "0,1" newline endif sif (cpuis("STM32MP157*")) bitfld.long 0x0 13. "NAKM,NAKM" "0,1" endif sif (cpuis("STM32MP151*")) bitfld.long 0x0 9. "BNAM,BNAM" "0,1" newline bitfld.long 0x0 8. "TXFURM,TXFURM" "0,1" endif sif (cpuis("STM32MP153*")) bitfld.long 0x0 9. "BNAM,BNAM" "0,1" newline bitfld.long 0x0 8. "TXFURM,TXFURM" "0,1" endif sif (cpuis("STM32MP157*")) bitfld.long 0x0 9. "BNAM,BNAM" "0,1" newline bitfld.long 0x0 8. "TXFURM,TXFURM" "0,1" endif sif (cpuis("STM32MP151*")) bitfld.long 0x0 6. "INEPNEM,INEPNEM" "0,1" newline bitfld.long 0x0 5. "INEPNMM,INEPNMM" "0,1" bitfld.long 0x0 4. "ITTXFEMSK,ITTXFEMSK" "0,1" newline bitfld.long 0x0 3. "TOM,TOM" "0,1" bitfld.long 0x0 2. "AHBERRM,AHBERRM" "0,1" newline bitfld.long 0x0 1. "EPDM,EPDM" "0,1" endif sif (cpuis("STM32MP153*")) bitfld.long 0x0 6. "INEPNEM,INEPNEM" "0,1" newline bitfld.long 0x0 5. "INEPNMM,INEPNMM" "0,1" bitfld.long 0x0 4. "ITTXFEMSK,ITTXFEMSK" "0,1" newline bitfld.long 0x0 3. "TOM,TOM" "0,1" bitfld.long 0x0 2. "AHBERRM,AHBERRM" "0,1" newline bitfld.long 0x0 1. "EPDM,EPDM" "0,1" bitfld.long 0x0 0. "XFRCM,XFRCM" "0,1" newline endif sif (cpuis("STM32MP157*")) bitfld.long 0x0 6. "INEPNEM,INEPNEM" "0,1" bitfld.long 0x0 5. "INEPNMM,INEPNMM" "0,1" newline bitfld.long 0x0 4. "ITTXFEMSK,ITTXFEMSK" "0,1" bitfld.long 0x0 3. "TOM,TOM" "0,1" newline bitfld.long 0x0 2. "AHBERRM,AHBERRM" "0,1" bitfld.long 0x0 1. "EPDM,EPDM" "0,1" newline bitfld.long 0x0 0. "XFRCM,XFRCM" "0,1" endif line.long 0x4 "OTG_DOEPMSK,OTG device OUT endpoint common interrupt mask register" sif (cpuis("STM32MP13*")) bitfld.long 0x4 14. "NYETMSK,NYET interrupt mask" "0: Masked interrupt,1: Unmasked interrupt" bitfld.long 0x4 13. "NAKMSK,NAK interrupt mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x4 12. "BERRM,Babble error interrupt mask" "0: Masked interrupt,1: Unmasked interrupt" bitfld.long 0x4 9. "BNAM,BNA interrupt mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x4 8. "OUTPKTERRM,Out packet error mask" "0: Masked interrupt,1: Unmasked interrupt" bitfld.long 0x4 6. "B2BSTUPM,Back-to-back SETUP packets received mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x4 5. "STSPHSRXM,Status phase received for control write mask" "0: Masked interrupt,1: Unmasked interrupt" bitfld.long 0x4 4. "OTEPDM,OUT token received when endpoint disabled mask. Applies to control OUT endpoints only." "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x4 3. "STUPM,STUPM: SETUP phase done mask. Applies to control endpoints only." "0: Masked interrupt,1: Unmasked interrupt" bitfld.long 0x4 2. "AHBERRM,AHB error mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x4 1. "EPDM,Endpoint disabled interrupt mask" "0: Masked interrupt,1: Unmasked interrupt" bitfld.long 0x4 0. "XFRCM,Transfer completed interrupt mask" "0: Masked interrupt,1: Unmasked interrupt" newline endif sif (cpuis("STM32MP151*")) bitfld.long 0x4 14. "NYETMSK,NYETMSK" "0,1" bitfld.long 0x4 13. "NAKMSK,NAKMSK" "0,1" newline bitfld.long 0x4 12. "BERRM,BERRM" "0,1" endif sif (cpuis("STM32MP153*")) bitfld.long 0x4 14. "NYETMSK,NYETMSK" "0,1" newline bitfld.long 0x4 13. "NAKMSK,NAKMSK" "0,1" bitfld.long 0x4 12. "BERRM,BERRM" "0,1" newline endif sif (cpuis("STM32MP157*")) bitfld.long 0x4 14. "NYETMSK,NYETMSK" "0,1" bitfld.long 0x4 13. "NAKMSK,NAKMSK" "0,1" newline bitfld.long 0x4 12. "BERRM,BERRM" "0,1" endif sif (cpuis("STM32MP151*")) bitfld.long 0x4 9. "BNAM,BNAM" "0,1" newline bitfld.long 0x4 8. "OUTPKTERRM,OUTPKTERRM" "0,1" endif sif (cpuis("STM32MP153*")) bitfld.long 0x4 9. "BNAM,BNAM" "0,1" newline bitfld.long 0x4 8. "OUTPKTERRM,OUTPKTERRM" "0,1" endif sif (cpuis("STM32MP157*")) bitfld.long 0x4 9. "BNAM,BNAM" "0,1" newline bitfld.long 0x4 8. "OUTPKTERRM,OUTPKTERRM" "0,1" endif sif (cpuis("STM32MP151*")) bitfld.long 0x4 6. "B2BSTUPM,B2BSTUPM" "0,1" newline bitfld.long 0x4 5. "STSPHSRXM,STSPHSRXM" "0,1" bitfld.long 0x4 4. "OTEPDM,OTEPDM" "0,1" newline bitfld.long 0x4 3. "STUPM,STUPM" "0,1" bitfld.long 0x4 2. "AHBERRM,AHBERRM" "0,1" newline bitfld.long 0x4 1. "EPDM,EPDM" "0,1" endif sif (cpuis("STM32MP153*")) bitfld.long 0x4 6. "B2BSTUPM,B2BSTUPM" "0,1" newline bitfld.long 0x4 5. "STSPHSRXM,STSPHSRXM" "0,1" bitfld.long 0x4 4. "OTEPDM,OTEPDM" "0,1" newline bitfld.long 0x4 3. "STUPM,STUPM" "0,1" bitfld.long 0x4 2. "AHBERRM,AHBERRM" "0,1" newline bitfld.long 0x4 1. "EPDM,EPDM" "0,1" bitfld.long 0x4 0. "XFRCM,XFRCM" "0,1" newline endif sif (cpuis("STM32MP157*")) bitfld.long 0x4 6. "B2BSTUPM,B2BSTUPM" "0,1" bitfld.long 0x4 5. "STSPHSRXM,STSPHSRXM" "0,1" newline bitfld.long 0x4 4. "OTEPDM,OTEPDM" "0,1" bitfld.long 0x4 3. "STUPM,STUPM" "0,1" newline bitfld.long 0x4 2. "AHBERRM,AHBERRM" "0,1" bitfld.long 0x4 1. "EPDM,EPDM" "0,1" newline bitfld.long 0x4 0. "XFRCM,XFRCM" "0,1" endif line.long 0x8 "OTG_DAINT,OTG device all endpoints interrupt register" sif (cpuis("STM32MP13*")) hexmask.long.word 0x8 16.--31. 1. "OEPINT,OUT endpoint interrupt bits" hexmask.long.word 0x8 0.--15. 1. "IEPINT,IN endpoint interrupt bits" newline endif sif (cpuis("STM32MP151*")) hexmask.long.word 0x8 16.--31. 1. "OEPINT,OEPINT" hexmask.long.word 0x8 0.--15. 1. "IEPINT,IEPINT" newline endif sif (cpuis("STM32MP153*")) hexmask.long.word 0x8 16.--31. 1. "OEPINT,OEPINT" hexmask.long.word 0x8 0.--15. 1. "IEPINT,IEPINT" newline endif sif (cpuis("STM32MP157*")) hexmask.long.word 0x8 16.--31. 1. "OEPINT,OEPINT" hexmask.long.word 0x8 0.--15. 1. "IEPINT,IEPINT" endif line.long 0xC "OTG_DAINTMSK,OTG all endpoints interrupt mask register" sif (cpuis("STM32MP13*")) hexmask.long.word 0xC 16.--31. 1. "OEPM,OUT EP interrupt mask bits" hexmask.long.word 0xC 0.--15. 1. "IEPM,IN EP interrupt mask bits" newline endif sif (cpuis("STM32MP151*")) hexmask.long.word 0xC 16.--31. 1. "OEPM,OEPM" endif sif (cpuis("STM32MP153*")) hexmask.long.word 0xC 16.--31. 1. "OEPM,OEPM" newline hexmask.long.word 0xC 0.--15. 1. "IEPM,IEPM" endif sif (cpuis("STM32MP157*")) hexmask.long.word 0xC 16.--31. 1. "OEPM,OEPM" newline hexmask.long.word 0xC 0.--15. 1. "IEPM,IEPM" endif group.long 0x828++0xF line.long 0x0 "OTG_DVBUSDIS,OTG device VBUS discharge time register" hexmask.long.word 0x0 0.--15. 1. "VBUSDT,Device VBUS discharge time" line.long 0x4 "OTG_DVBUSPULSE,OTG device VBUS pulsing time register" hexmask.long.word 0x4 0.--15. 1. "DVBUSP,Device VBUS pulsing time. This feature is only relevant to OTG1.3." line.long 0x8 "OTG_DTHRCTL," bitfld.long 0x8 27. "ARPEN,Arbiter parking enable" "0,1" hexmask.long.word 0x8 17.--25. 1. "RXTHRLEN,Receive threshold length" newline bitfld.long 0x8 16. "RXTHREN,Receive threshold enable" "0,1" hexmask.long.word 0x8 2.--10. 1. "TXTHRLEN,Transmit threshold length" newline bitfld.long 0x8 1. "ISOTHREN,ISO IN endpoint threshold enable" "0,1" bitfld.long 0x8 0. "NONISOTHREN,Nonisochronous IN endpoints threshold enable" "0,1" line.long 0xC "OTG_DIEPEMPMSK,OTG device IN endpoint FIFO empty interrupt mask register" sif (cpuis("STM32MP13*")) hexmask.long.word 0xC 0.--15. 1. "INEPTXFEM,IN EP Tx FIFO empty interrupt mask bits" endif sif (cpuis("STM32MP153*")) hexmask.long.word 0xC 0.--15. 1. "INEPTXFEM,INEPTXFEM" newline endif sif (cpuis("STM32MP157*")) hexmask.long.word 0xC 0.--15. 1. "INEPTXFEM,INEPTXFEM" endif group.long 0x900++0x3 line.long 0x0 "OTG_DIEPCTL0,OTG device IN endpoint 0 control register" bitfld.long 0x0 31. "EPENA,Endpoint enable" "0,1" bitfld.long 0x0 30. "EPDIS,Endpoint disable" "0,1" newline bitfld.long 0x0 29. "SODDFRM,Set odd frame" "0,1" sif (cpuis("STM32MP13*")) bitfld.long 0x0 28. "SEVNFRM,Set even frame" "0,1" newline bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt" rbitfld.long 0x0 17. "NAKSTS,NAK status" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.." newline rbitfld.long 0x0 16. "EONUM,Even/odd frame" "0: Even frame,1: Odd frame" endif sif (cpuis("STM32MP151*")) bitfld.long 0x0 28. "SD0PID_SEVNFRM,SD0PID_SEVNFRM" "0,1" newline endif sif (cpuis("STM32MP153*")) bitfld.long 0x0 28. "SD0PID_SEVNFRM,SD0PID_SEVNFRM" "0,1" endif sif (cpuis("STM32MP157*")) bitfld.long 0x0 28. "SD0PID_SEVNFRM,SD0PID_SEVNFRM" "0,1" newline endif bitfld.long 0x0 27. "SNAK,Set NAK" "0,1" bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1" newline hexmask.long.byte 0x0 22.--25. 1. "TXFNUM,Tx FIFO number" bitfld.long 0x0 21. "STALL,STALL handshake" "0,1" newline sif (cpuis("STM32MP151*")) bitfld.long 0x0 18.--19. "EPTYP,EPTYP" "0,1,2,3" rbitfld.long 0x0 17. "NAKSTS,NAKSTS" "0,1" newline rbitfld.long 0x0 16. "EONUM_DPIP,EONUM_DPIP" "0,1" endif sif (cpuis("STM32MP153*")) bitfld.long 0x0 18.--19. "EPTYP,EPTYP" "0,1,2,3" newline rbitfld.long 0x0 17. "NAKSTS,NAKSTS" "0,1" rbitfld.long 0x0 16. "EONUM_DPIP,EONUM_DPIP" "0,1" newline endif sif (cpuis("STM32MP157*")) bitfld.long 0x0 18.--19. "EPTYP,EPTYP" "0,1,2,3" rbitfld.long 0x0 17. "NAKSTS,NAKSTS" "0,1" newline rbitfld.long 0x0 16. "EONUM_DPIP,EONUM_DPIP" "0,1" endif bitfld.long 0x0 15. "USBAEP,USB active endpoint" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" group.long 0x908++0x3 line.long 0x0 "OTG_DIEPINT0,OTG device IN endpoint 0 interrupt register" bitfld.long 0x0 13. "NAK,NAK input" "0,1" bitfld.long 0x0 11. "PKTDRPSTS,Packet dropped status" "0,1" newline bitfld.long 0x0 9. "BNA,Buffer not available interrupt" "0,1" bitfld.long 0x0 8. "TXFIFOUDRN,Transmit Fifo Underrun (TxfifoUndrn)" "0,1" newline rbitfld.long 0x0 7. "TXFE,Transmit FIFO empty" "0,1" sif (cpuis("STM32MP13*")) bitfld.long 0x0 6. "INEPNE,IN endpoint NAK effective" "0,1" newline endif sif (cpuis("STM32MP151*")) rbitfld.long 0x0 6. "INEPNE,INEPNE" "0,1" endif sif (cpuis("STM32MP153*")) rbitfld.long 0x0 6. "INEPNE,INEPNE" "0,1" newline endif sif (cpuis("STM32MP157*")) rbitfld.long 0x0 6. "INEPNE,INEPNE" "0,1" endif bitfld.long 0x0 5. "INEPNM,IN token received with EP mismatch" "0,1" newline bitfld.long 0x0 4. "ITTXFE,IN token received when Tx FIFO is empty" "0,1" bitfld.long 0x0 3. "TOC,Timeout condition" "0,1" newline bitfld.long 0x0 2. "AHBERR,AHB error" "0,1" bitfld.long 0x0 1. "EPDISD,Endpoint disabled interrupt" "0,1" newline bitfld.long 0x0 0. "XFRC,Transfer completed interrupt" "0,1" group.long 0x910++0xB line.long 0x0 "OTG_DIEPTSIZ0,OTG device IN endpoint 0 transfer size register" bitfld.long 0x0 19.--20. "PKTCNT,Packet count" "0,1,2,3" hexmask.long.byte 0x0 0.--6. 1. "XFRSIZ,Transfer size" line.long 0x4 "OTG_DIEPDMA0," hexmask.long 0x4 0.--31. 1. "DMAADDR,DMA Address" line.long 0x8 "OTG_DTXFSTS0,OTG device IN endpoint transmit FIFO status register" sif (cpuis("STM32MP13*")) hexmask.long.word 0x8 0.--15. 1. "INEPTFSAV,IN endpoint Tx FIFO space available" endif sif (cpuis("STM32MP151*")) hexmask.long.word 0x8 0.--15. 1. "INEPTFSAV,INEPTFSAV" newline endif sif (cpuis("STM32MP153*")) hexmask.long.word 0x8 0.--15. 1. "INEPTFSAV,INEPTFSAV" endif sif (cpuis("STM32MP157*")) hexmask.long.word 0x8 0.--15. 1. "INEPTFSAV,INEPTFSAV" endif group.long 0x920++0x3 line.long 0x0 "OTG_DIEPCTL1,OTG device IN endpoint 1 control register" bitfld.long 0x0 31. "EPENA,Endpoint enable" "0,1" bitfld.long 0x0 30. "EPDIS,Endpoint disable" "0,1" newline bitfld.long 0x0 29. "SODDFRM,Set odd frame" "0,1" sif (cpuis("STM32MP13*")) bitfld.long 0x0 28. "SEVNFRM,Set even frame" "0,1" newline bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt" rbitfld.long 0x0 17. "NAKSTS,NAK status" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.." newline rbitfld.long 0x0 16. "EONUM,Even/odd frame" "0: Even frame,1: Odd frame" endif sif (cpuis("STM32MP151*")) bitfld.long 0x0 28. "SD0PID_SEVNFRM,SD0PID_SEVNFRM" "0,1" newline endif sif (cpuis("STM32MP153*")) bitfld.long 0x0 28. "SD0PID_SEVNFRM,SD0PID_SEVNFRM" "0,1" endif sif (cpuis("STM32MP157*")) bitfld.long 0x0 28. "SD0PID_SEVNFRM,SD0PID_SEVNFRM" "0,1" newline endif bitfld.long 0x0 27. "SNAK,Set NAK" "0,1" bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1" newline hexmask.long.byte 0x0 22.--25. 1. "TXFNUM,Tx FIFO number" bitfld.long 0x0 21. "STALL,STALL handshake" "0,1" newline sif (cpuis("STM32MP151*")) bitfld.long 0x0 18.--19. "EPTYP,EPTYP" "0,1,2,3" rbitfld.long 0x0 17. "NAKSTS,NAKSTS" "0,1" newline rbitfld.long 0x0 16. "EONUM_DPIP,EONUM_DPIP" "0,1" endif sif (cpuis("STM32MP153*")) bitfld.long 0x0 18.--19. "EPTYP,EPTYP" "0,1,2,3" newline rbitfld.long 0x0 17. "NAKSTS,NAKSTS" "0,1" rbitfld.long 0x0 16. "EONUM_DPIP,EONUM_DPIP" "0,1" newline endif sif (cpuis("STM32MP157*")) bitfld.long 0x0 18.--19. "EPTYP,EPTYP" "0,1,2,3" rbitfld.long 0x0 17. "NAKSTS,NAKSTS" "0,1" newline rbitfld.long 0x0 16. "EONUM_DPIP,EONUM_DPIP" "0,1" endif bitfld.long 0x0 15. "USBAEP,USB active endpoint" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" group.long 0x928++0x3 line.long 0x0 "OTG_DIEPINT1,OTG device IN endpoint 1 interrupt register" bitfld.long 0x0 13. "NAK,NAK input" "0,1" bitfld.long 0x0 11. "PKTDRPSTS,Packet dropped status" "0,1" newline bitfld.long 0x0 9. "BNA,Buffer not available interrupt" "0,1" bitfld.long 0x0 8. "TXFIFOUDRN,Transmit Fifo Underrun (TxfifoUndrn)" "0,1" newline rbitfld.long 0x0 7. "TXFE,Transmit FIFO empty" "0,1" sif (cpuis("STM32MP13*")) bitfld.long 0x0 6. "INEPNE,IN endpoint NAK effective" "0,1" newline endif sif (cpuis("STM32MP151*")) rbitfld.long 0x0 6. "INEPNE,INEPNE" "0,1" endif sif (cpuis("STM32MP153*")) rbitfld.long 0x0 6. "INEPNE,INEPNE" "0,1" newline endif sif (cpuis("STM32MP157*")) rbitfld.long 0x0 6. "INEPNE,INEPNE" "0,1" endif bitfld.long 0x0 5. "INEPNM,IN token received with EP mismatch" "0,1" newline bitfld.long 0x0 4. "ITTXFE,IN token received when Tx FIFO is empty" "0,1" bitfld.long 0x0 3. "TOC,Timeout condition" "0,1" newline bitfld.long 0x0 2. "AHBERR,AHB error" "0,1" bitfld.long 0x0 1. "EPDISD,Endpoint disabled interrupt" "0,1" newline bitfld.long 0x0 0. "XFRC,Transfer completed interrupt" "0,1" group.long 0x930++0xB line.long 0x0 "OTG_DIEPTSIZ1,OTG device IN endpoint 1 transfer size register" sif (cpuis("STM32MP13*")) bitfld.long 0x0 29.--30. "MCNT,Multi count" "?,1: 1 packet,2: 2 packets,3: 3 packets" endif sif (cpuis("STM32MP151*")) bitfld.long 0x0 29.--30. "MCNT,MCNT" "0,1,2,3" newline endif sif (cpuis("STM32MP153*")) bitfld.long 0x0 29.--30. "MCNT,MCNT" "0,1,2,3" endif sif (cpuis("STM32MP157*")) bitfld.long 0x0 29.--30. "MCNT,MCNT" "0,1,2,3" newline endif hexmask.long.word 0x0 19.--28. 1. "PKTCNT,Packet count" hexmask.long.tbyte 0x0 0.--18. 1. "XFRSIZ,Transfer size" line.long 0x4 "OTG_DIEPDMA1," hexmask.long 0x4 0.--31. 1. "DMAADDR,DMA Address" line.long 0x8 "OTG_DTXFSTS1,OTG device IN endpoint transmit FIFO status register" sif (cpuis("STM32MP13*")) hexmask.long.word 0x8 0.--15. 1. "INEPTFSAV,IN endpoint Tx FIFO space available" endif sif (cpuis("STM32MP151*")) hexmask.long.word 0x8 0.--15. 1. "INEPTFSAV,INEPTFSAV" newline endif sif (cpuis("STM32MP153*")) hexmask.long.word 0x8 0.--15. 1. "INEPTFSAV,INEPTFSAV" endif sif (cpuis("STM32MP157*")) hexmask.long.word 0x8 0.--15. 1. "INEPTFSAV,INEPTFSAV" endif group.long 0x940++0x3 line.long 0x0 "OTG_DIEPCTL2,OTG device IN endpoint 2 control register" bitfld.long 0x0 31. "EPENA,Endpoint enable" "0,1" bitfld.long 0x0 30. "EPDIS,Endpoint disable" "0,1" newline bitfld.long 0x0 29. "SODDFRM,Set odd frame" "0,1" sif (cpuis("STM32MP13*")) bitfld.long 0x0 28. "SEVNFRM,Set even frame" "0,1" newline bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt" rbitfld.long 0x0 17. "NAKSTS,NAK status" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.." newline rbitfld.long 0x0 16. "EONUM,Even/odd frame" "0: Even frame,1: Odd frame" endif sif (cpuis("STM32MP151*")) bitfld.long 0x0 28. "SD0PID_SEVNFRM,SD0PID_SEVNFRM" "0,1" newline endif sif (cpuis("STM32MP153*")) bitfld.long 0x0 28. "SD0PID_SEVNFRM,SD0PID_SEVNFRM" "0,1" endif sif (cpuis("STM32MP157*")) bitfld.long 0x0 28. "SD0PID_SEVNFRM,SD0PID_SEVNFRM" "0,1" newline endif bitfld.long 0x0 27. "SNAK,Set NAK" "0,1" bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1" newline hexmask.long.byte 0x0 22.--25. 1. "TXFNUM,Tx FIFO number" bitfld.long 0x0 21. "STALL,STALL handshake" "0,1" newline sif (cpuis("STM32MP151*")) bitfld.long 0x0 18.--19. "EPTYP,EPTYP" "0,1,2,3" rbitfld.long 0x0 17. "NAKSTS,NAKSTS" "0,1" newline rbitfld.long 0x0 16. "EONUM_DPIP,EONUM_DPIP" "0,1" endif sif (cpuis("STM32MP153*")) bitfld.long 0x0 18.--19. "EPTYP,EPTYP" "0,1,2,3" newline rbitfld.long 0x0 17. "NAKSTS,NAKSTS" "0,1" rbitfld.long 0x0 16. "EONUM_DPIP,EONUM_DPIP" "0,1" newline endif sif (cpuis("STM32MP157*")) bitfld.long 0x0 18.--19. "EPTYP,EPTYP" "0,1,2,3" rbitfld.long 0x0 17. "NAKSTS,NAKSTS" "0,1" newline rbitfld.long 0x0 16. "EONUM_DPIP,EONUM_DPIP" "0,1" endif bitfld.long 0x0 15. "USBAEP,USB active endpoint" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" group.long 0x948++0x3 line.long 0x0 "OTG_DIEPINT2,OTG device IN endpoint 2 interrupt register" bitfld.long 0x0 13. "NAK,NAK input" "0,1" bitfld.long 0x0 11. "PKTDRPSTS,Packet dropped status" "0,1" newline bitfld.long 0x0 9. "BNA,Buffer not available interrupt" "0,1" bitfld.long 0x0 8. "TXFIFOUDRN,Transmit Fifo Underrun (TxfifoUndrn)" "0,1" newline rbitfld.long 0x0 7. "TXFE,Transmit FIFO empty" "0,1" sif (cpuis("STM32MP13*")) bitfld.long 0x0 6. "INEPNE,IN endpoint NAK effective" "0,1" newline endif sif (cpuis("STM32MP151*")) rbitfld.long 0x0 6. "INEPNE,INEPNE" "0,1" endif sif (cpuis("STM32MP153*")) rbitfld.long 0x0 6. "INEPNE,INEPNE" "0,1" newline endif sif (cpuis("STM32MP157*")) rbitfld.long 0x0 6. "INEPNE,INEPNE" "0,1" endif bitfld.long 0x0 5. "INEPNM,IN token received with EP mismatch" "0,1" newline bitfld.long 0x0 4. "ITTXFE,IN token received when Tx FIFO is empty" "0,1" bitfld.long 0x0 3. "TOC,Timeout condition" "0,1" newline bitfld.long 0x0 2. "AHBERR,AHB error" "0,1" bitfld.long 0x0 1. "EPDISD,Endpoint disabled interrupt" "0,1" newline bitfld.long 0x0 0. "XFRC,Transfer completed interrupt" "0,1" group.long 0x950++0xB line.long 0x0 "OTG_DIEPTSIZ2,OTG device IN endpoint 2 transfer size register" sif (cpuis("STM32MP13*")) bitfld.long 0x0 29.--30. "MCNT,Multi count" "?,1: 1 packet,2: 2 packets,3: 3 packets" endif sif (cpuis("STM32MP151*")) bitfld.long 0x0 29.--30. "MCNT,MCNT" "0,1,2,3" newline endif sif (cpuis("STM32MP153*")) bitfld.long 0x0 29.--30. "MCNT,MCNT" "0,1,2,3" endif sif (cpuis("STM32MP157*")) bitfld.long 0x0 29.--30. "MCNT,MCNT" "0,1,2,3" newline endif hexmask.long.word 0x0 19.--28. 1. "PKTCNT,Packet count" hexmask.long.tbyte 0x0 0.--18. 1. "XFRSIZ,Transfer size" line.long 0x4 "OTG_DIEPDMA2," hexmask.long 0x4 0.--31. 1. "DMAADDR,DMA Address" line.long 0x8 "OTG_DTXFSTS2,OTG device IN endpoint transmit FIFO status register" sif (cpuis("STM32MP13*")) hexmask.long.word 0x8 0.--15. 1. "INEPTFSAV,IN endpoint Tx FIFO space available" endif sif (cpuis("STM32MP151*")) hexmask.long.word 0x8 0.--15. 1. "INEPTFSAV,INEPTFSAV" newline endif sif (cpuis("STM32MP153*")) hexmask.long.word 0x8 0.--15. 1. "INEPTFSAV,INEPTFSAV" endif sif (cpuis("STM32MP157*")) hexmask.long.word 0x8 0.--15. 1. "INEPTFSAV,INEPTFSAV" endif group.long 0x960++0x3 line.long 0x0 "OTG_DIEPCTL3,OTG device IN endpoint 3 control register" bitfld.long 0x0 31. "EPENA,Endpoint enable" "0,1" bitfld.long 0x0 30. "EPDIS,Endpoint disable" "0,1" newline bitfld.long 0x0 29. "SODDFRM,Set odd frame" "0,1" sif (cpuis("STM32MP13*")) bitfld.long 0x0 28. "SEVNFRM,Set even frame" "0,1" newline bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt" rbitfld.long 0x0 17. "NAKSTS,NAK status" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.." newline rbitfld.long 0x0 16. "EONUM,Even/odd frame" "0: Even frame,1: Odd frame" endif sif (cpuis("STM32MP151*")) bitfld.long 0x0 28. "SD0PID_SEVNFRM,SD0PID_SEVNFRM" "0,1" newline endif sif (cpuis("STM32MP153*")) bitfld.long 0x0 28. "SD0PID_SEVNFRM,SD0PID_SEVNFRM" "0,1" endif sif (cpuis("STM32MP157*")) bitfld.long 0x0 28. "SD0PID_SEVNFRM,SD0PID_SEVNFRM" "0,1" newline endif bitfld.long 0x0 27. "SNAK,Set NAK" "0,1" bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1" newline hexmask.long.byte 0x0 22.--25. 1. "TXFNUM,Tx FIFO number" bitfld.long 0x0 21. "STALL,STALL handshake" "0,1" newline sif (cpuis("STM32MP151*")) bitfld.long 0x0 18.--19. "EPTYP,EPTYP" "0,1,2,3" rbitfld.long 0x0 17. "NAKSTS,NAKSTS" "0,1" newline rbitfld.long 0x0 16. "EONUM_DPIP,EONUM_DPIP" "0,1" endif sif (cpuis("STM32MP153*")) bitfld.long 0x0 18.--19. "EPTYP,EPTYP" "0,1,2,3" newline rbitfld.long 0x0 17. "NAKSTS,NAKSTS" "0,1" rbitfld.long 0x0 16. "EONUM_DPIP,EONUM_DPIP" "0,1" newline endif sif (cpuis("STM32MP157*")) bitfld.long 0x0 18.--19. "EPTYP,EPTYP" "0,1,2,3" rbitfld.long 0x0 17. "NAKSTS,NAKSTS" "0,1" newline rbitfld.long 0x0 16. "EONUM_DPIP,EONUM_DPIP" "0,1" endif bitfld.long 0x0 15. "USBAEP,USB active endpoint" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" group.long 0x968++0x3 line.long 0x0 "OTG_DIEPINT3,OTG device IN endpoint 3 interrupt register" bitfld.long 0x0 13. "NAK,NAK input" "0,1" bitfld.long 0x0 11. "PKTDRPSTS,Packet dropped status" "0,1" newline bitfld.long 0x0 9. "BNA,Buffer not available interrupt" "0,1" bitfld.long 0x0 8. "TXFIFOUDRN,Transmit Fifo Underrun (TxfifoUndrn)" "0,1" newline rbitfld.long 0x0 7. "TXFE,Transmit FIFO empty" "0,1" sif (cpuis("STM32MP13*")) bitfld.long 0x0 6. "INEPNE,IN endpoint NAK effective" "0,1" newline endif sif (cpuis("STM32MP151*")) rbitfld.long 0x0 6. "INEPNE,INEPNE" "0,1" endif sif (cpuis("STM32MP153*")) rbitfld.long 0x0 6. "INEPNE,INEPNE" "0,1" newline endif sif (cpuis("STM32MP157*")) rbitfld.long 0x0 6. "INEPNE,INEPNE" "0,1" endif bitfld.long 0x0 5. "INEPNM,IN token received with EP mismatch" "0,1" newline bitfld.long 0x0 4. "ITTXFE,IN token received when Tx FIFO is empty" "0,1" bitfld.long 0x0 3. "TOC,Timeout condition" "0,1" newline bitfld.long 0x0 2. "AHBERR,AHB error" "0,1" bitfld.long 0x0 1. "EPDISD,Endpoint disabled interrupt" "0,1" newline bitfld.long 0x0 0. "XFRC,Transfer completed interrupt" "0,1" group.long 0x970++0xB line.long 0x0 "OTG_DIEPTSIZ3,OTG device IN endpoint 3 transfer size register" sif (cpuis("STM32MP13*")) bitfld.long 0x0 29.--30. "MCNT,Multi count" "?,1: 1 packet,2: 2 packets,3: 3 packets" endif sif (cpuis("STM32MP151*")) bitfld.long 0x0 29.--30. "MCNT,MCNT" "0,1,2,3" newline endif sif (cpuis("STM32MP153*")) bitfld.long 0x0 29.--30. "MCNT,MCNT" "0,1,2,3" endif sif (cpuis("STM32MP157*")) bitfld.long 0x0 29.--30. "MCNT,MCNT" "0,1,2,3" newline endif hexmask.long.word 0x0 19.--28. 1. "PKTCNT,Packet count" hexmask.long.tbyte 0x0 0.--18. 1. "XFRSIZ,Transfer size" line.long 0x4 "OTG_DIEPDMA3," hexmask.long 0x4 0.--31. 1. "DMAADDR,DMA Address" line.long 0x8 "OTG_DTXFSTS3,OTG device IN endpoint transmit FIFO status register" sif (cpuis("STM32MP13*")) hexmask.long.word 0x8 0.--15. 1. "INEPTFSAV,IN endpoint Tx FIFO space available" endif sif (cpuis("STM32MP151*")) hexmask.long.word 0x8 0.--15. 1. "INEPTFSAV,INEPTFSAV" newline endif sif (cpuis("STM32MP153*")) hexmask.long.word 0x8 0.--15. 1. "INEPTFSAV,INEPTFSAV" endif sif (cpuis("STM32MP157*")) hexmask.long.word 0x8 0.--15. 1. "INEPTFSAV,INEPTFSAV" endif group.long 0x980++0x3 line.long 0x0 "OTG_DIEPCTL4,OTG device IN endpoint 4 control register" bitfld.long 0x0 31. "EPENA,Endpoint enable" "0,1" bitfld.long 0x0 30. "EPDIS,Endpoint disable" "0,1" newline bitfld.long 0x0 29. "SODDFRM,Set odd frame" "0,1" sif (cpuis("STM32MP13*")) bitfld.long 0x0 28. "SEVNFRM,Set even frame" "0,1" newline bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt" rbitfld.long 0x0 17. "NAKSTS,NAK status" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.." newline rbitfld.long 0x0 16. "EONUM,Even/odd frame" "0: Even frame,1: Odd frame" endif sif (cpuis("STM32MP151*")) bitfld.long 0x0 28. "SD0PID_SEVNFRM,SD0PID_SEVNFRM" "0,1" newline endif sif (cpuis("STM32MP153*")) bitfld.long 0x0 28. "SD0PID_SEVNFRM,SD0PID_SEVNFRM" "0,1" endif sif (cpuis("STM32MP157*")) bitfld.long 0x0 28. "SD0PID_SEVNFRM,SD0PID_SEVNFRM" "0,1" newline endif bitfld.long 0x0 27. "SNAK,Set NAK" "0,1" bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1" newline hexmask.long.byte 0x0 22.--25. 1. "TXFNUM,Tx FIFO number" bitfld.long 0x0 21. "STALL,STALL handshake" "0,1" newline sif (cpuis("STM32MP151*")) bitfld.long 0x0 18.--19. "EPTYP,EPTYP" "0,1,2,3" rbitfld.long 0x0 17. "NAKSTS,NAKSTS" "0,1" newline rbitfld.long 0x0 16. "EONUM_DPIP,EONUM_DPIP" "0,1" endif sif (cpuis("STM32MP153*")) bitfld.long 0x0 18.--19. "EPTYP,EPTYP" "0,1,2,3" newline rbitfld.long 0x0 17. "NAKSTS,NAKSTS" "0,1" rbitfld.long 0x0 16. "EONUM_DPIP,EONUM_DPIP" "0,1" newline endif sif (cpuis("STM32MP157*")) bitfld.long 0x0 18.--19. "EPTYP,EPTYP" "0,1,2,3" rbitfld.long 0x0 17. "NAKSTS,NAKSTS" "0,1" newline rbitfld.long 0x0 16. "EONUM_DPIP,EONUM_DPIP" "0,1" endif bitfld.long 0x0 15. "USBAEP,USB active endpoint" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" group.long 0x988++0x3 line.long 0x0 "OTG_DIEPINT4,OTG device IN endpoint 4 interrupt register" bitfld.long 0x0 13. "NAK,NAK input" "0,1" bitfld.long 0x0 11. "PKTDRPSTS,Packet dropped status" "0,1" newline bitfld.long 0x0 9. "BNA,Buffer not available interrupt" "0,1" bitfld.long 0x0 8. "TXFIFOUDRN,Transmit Fifo Underrun (TxfifoUndrn)" "0,1" newline rbitfld.long 0x0 7. "TXFE,Transmit FIFO empty" "0,1" sif (cpuis("STM32MP13*")) bitfld.long 0x0 6. "INEPNE,IN endpoint NAK effective" "0,1" newline endif sif (cpuis("STM32MP151*")) rbitfld.long 0x0 6. "INEPNE,INEPNE" "0,1" endif sif (cpuis("STM32MP153*")) rbitfld.long 0x0 6. "INEPNE,INEPNE" "0,1" newline endif sif (cpuis("STM32MP157*")) rbitfld.long 0x0 6. "INEPNE,INEPNE" "0,1" endif bitfld.long 0x0 5. "INEPNM,IN token received with EP mismatch" "0,1" newline bitfld.long 0x0 4. "ITTXFE,IN token received when Tx FIFO is empty" "0,1" bitfld.long 0x0 3. "TOC,Timeout condition" "0,1" newline bitfld.long 0x0 2. "AHBERR,AHB error" "0,1" bitfld.long 0x0 1. "EPDISD,Endpoint disabled interrupt" "0,1" newline bitfld.long 0x0 0. "XFRC,Transfer completed interrupt" "0,1" group.long 0x990++0xB line.long 0x0 "OTG_DIEPTSIZ4,OTG device IN endpoint 4 transfer size register" sif (cpuis("STM32MP13*")) bitfld.long 0x0 29.--30. "MCNT,Multi count" "?,1: 1 packet,2: 2 packets,3: 3 packets" endif sif (cpuis("STM32MP151*")) bitfld.long 0x0 29.--30. "MCNT,MCNT" "0,1,2,3" newline endif sif (cpuis("STM32MP153*")) bitfld.long 0x0 29.--30. "MCNT,MCNT" "0,1,2,3" endif sif (cpuis("STM32MP157*")) bitfld.long 0x0 29.--30. "MCNT,MCNT" "0,1,2,3" newline endif hexmask.long.word 0x0 19.--28. 1. "PKTCNT,Packet count" hexmask.long.tbyte 0x0 0.--18. 1. "XFRSIZ,Transfer size" line.long 0x4 "OTG_DIEPDMA4," hexmask.long 0x4 0.--31. 1. "DMAADDR,DMA Address" line.long 0x8 "OTG_DTXFSTS4,OTG device IN endpoint transmit FIFO status register" sif (cpuis("STM32MP13*")) hexmask.long.word 0x8 0.--15. 1. "INEPTFSAV,IN endpoint Tx FIFO space available" endif sif (cpuis("STM32MP151*")) hexmask.long.word 0x8 0.--15. 1. "INEPTFSAV,INEPTFSAV" newline endif sif (cpuis("STM32MP153*")) hexmask.long.word 0x8 0.--15. 1. "INEPTFSAV,INEPTFSAV" endif sif (cpuis("STM32MP157*")) hexmask.long.word 0x8 0.--15. 1. "INEPTFSAV,INEPTFSAV" endif group.long 0x9A0++0x3 line.long 0x0 "OTG_DIEPCTL5,OTG device IN endpoint 5 control register" bitfld.long 0x0 31. "EPENA,Endpoint enable" "0,1" bitfld.long 0x0 30. "EPDIS,Endpoint disable" "0,1" newline bitfld.long 0x0 29. "SODDFRM,Set odd frame" "0,1" sif (cpuis("STM32MP13*")) bitfld.long 0x0 28. "SEVNFRM,Set even frame" "0,1" newline bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt" rbitfld.long 0x0 17. "NAKSTS,NAK status" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.." newline rbitfld.long 0x0 16. "EONUM,Even/odd frame" "0: Even frame,1: Odd frame" endif sif (cpuis("STM32MP151*")) bitfld.long 0x0 28. "SD0PID_SEVNFRM,SD0PID_SEVNFRM" "0,1" newline endif sif (cpuis("STM32MP153*")) bitfld.long 0x0 28. "SD0PID_SEVNFRM,SD0PID_SEVNFRM" "0,1" endif sif (cpuis("STM32MP157*")) bitfld.long 0x0 28. "SD0PID_SEVNFRM,SD0PID_SEVNFRM" "0,1" newline endif bitfld.long 0x0 27. "SNAK,Set NAK" "0,1" bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1" newline hexmask.long.byte 0x0 22.--25. 1. "TXFNUM,Tx FIFO number" bitfld.long 0x0 21. "STALL,STALL handshake" "0,1" newline sif (cpuis("STM32MP151*")) bitfld.long 0x0 18.--19. "EPTYP,EPTYP" "0,1,2,3" rbitfld.long 0x0 17. "NAKSTS,NAKSTS" "0,1" newline rbitfld.long 0x0 16. "EONUM_DPIP,EONUM_DPIP" "0,1" endif sif (cpuis("STM32MP153*")) bitfld.long 0x0 18.--19. "EPTYP,EPTYP" "0,1,2,3" newline rbitfld.long 0x0 17. "NAKSTS,NAKSTS" "0,1" rbitfld.long 0x0 16. "EONUM_DPIP,EONUM_DPIP" "0,1" newline endif sif (cpuis("STM32MP157*")) bitfld.long 0x0 18.--19. "EPTYP,EPTYP" "0,1,2,3" rbitfld.long 0x0 17. "NAKSTS,NAKSTS" "0,1" newline rbitfld.long 0x0 16. "EONUM_DPIP,EONUM_DPIP" "0,1" endif bitfld.long 0x0 15. "USBAEP,USB active endpoint" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" group.long 0x9A8++0x3 line.long 0x0 "OTG_DIEPINT5,OTG device IN endpoint 5 interrupt register" bitfld.long 0x0 13. "NAK,NAK input" "0,1" bitfld.long 0x0 11. "PKTDRPSTS,Packet dropped status" "0,1" newline bitfld.long 0x0 9. "BNA,Buffer not available interrupt" "0,1" bitfld.long 0x0 8. "TXFIFOUDRN,Transmit Fifo Underrun (TxfifoUndrn)" "0,1" newline rbitfld.long 0x0 7. "TXFE,Transmit FIFO empty" "0,1" sif (cpuis("STM32MP13*")) bitfld.long 0x0 6. "INEPNE,IN endpoint NAK effective" "0,1" newline endif sif (cpuis("STM32MP151*")) rbitfld.long 0x0 6. "INEPNE,INEPNE" "0,1" endif sif (cpuis("STM32MP153*")) rbitfld.long 0x0 6. "INEPNE,INEPNE" "0,1" newline endif sif (cpuis("STM32MP157*")) rbitfld.long 0x0 6. "INEPNE,INEPNE" "0,1" endif bitfld.long 0x0 5. "INEPNM,IN token received with EP mismatch" "0,1" newline bitfld.long 0x0 4. "ITTXFE,IN token received when Tx FIFO is empty" "0,1" bitfld.long 0x0 3. "TOC,Timeout condition" "0,1" newline bitfld.long 0x0 2. "AHBERR,AHB error" "0,1" bitfld.long 0x0 1. "EPDISD,Endpoint disabled interrupt" "0,1" newline bitfld.long 0x0 0. "XFRC,Transfer completed interrupt" "0,1" group.long 0x9B0++0xB line.long 0x0 "OTG_DIEPTSIZ5,OTG device IN endpoint 5 transfer size register" sif (cpuis("STM32MP13*")) bitfld.long 0x0 29.--30. "MCNT,Multi count" "?,1: 1 packet,2: 2 packets,3: 3 packets" endif sif (cpuis("STM32MP151*")) bitfld.long 0x0 29.--30. "MCNT,MCNT" "0,1,2,3" newline endif sif (cpuis("STM32MP153*")) bitfld.long 0x0 29.--30. "MCNT,MCNT" "0,1,2,3" endif sif (cpuis("STM32MP157*")) bitfld.long 0x0 29.--30. "MCNT,MCNT" "0,1,2,3" newline endif hexmask.long.word 0x0 19.--28. 1. "PKTCNT,Packet count" hexmask.long.tbyte 0x0 0.--18. 1. "XFRSIZ,Transfer size" line.long 0x4 "OTG_DIEPDMA5," hexmask.long 0x4 0.--31. 1. "DMAADDR,DMA Address" line.long 0x8 "OTG_DTXFSTS5,OTG device IN endpoint transmit FIFO status register" sif (cpuis("STM32MP13*")) hexmask.long.word 0x8 0.--15. 1. "INEPTFSAV,IN endpoint Tx FIFO space available" endif sif (cpuis("STM32MP151*")) hexmask.long.word 0x8 0.--15. 1. "INEPTFSAV,INEPTFSAV" newline endif sif (cpuis("STM32MP153*")) hexmask.long.word 0x8 0.--15. 1. "INEPTFSAV,INEPTFSAV" endif sif (cpuis("STM32MP157*")) hexmask.long.word 0x8 0.--15. 1. "INEPTFSAV,INEPTFSAV" endif group.long 0x9C0++0x3 line.long 0x0 "OTG_DIEPCTL6,OTG device IN endpoint 6 control register" bitfld.long 0x0 31. "EPENA,Endpoint enable" "0,1" bitfld.long 0x0 30. "EPDIS,Endpoint disable" "0,1" newline bitfld.long 0x0 29. "SODDFRM,Set odd frame" "0,1" sif (cpuis("STM32MP13*")) bitfld.long 0x0 28. "SEVNFRM,Set even frame" "0,1" newline bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt" rbitfld.long 0x0 17. "NAKSTS,NAK status" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.." newline rbitfld.long 0x0 16. "EONUM,Even/odd frame" "0: Even frame,1: Odd frame" endif sif (cpuis("STM32MP151*")) bitfld.long 0x0 28. "SD0PID_SEVNFRM,SD0PID_SEVNFRM" "0,1" newline endif sif (cpuis("STM32MP153*")) bitfld.long 0x0 28. "SD0PID_SEVNFRM,SD0PID_SEVNFRM" "0,1" endif sif (cpuis("STM32MP157*")) bitfld.long 0x0 28. "SD0PID_SEVNFRM,SD0PID_SEVNFRM" "0,1" newline endif bitfld.long 0x0 27. "SNAK,Set NAK" "0,1" bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1" newline hexmask.long.byte 0x0 22.--25. 1. "TXFNUM,Tx FIFO number" bitfld.long 0x0 21. "STALL,STALL handshake" "0,1" newline sif (cpuis("STM32MP151*")) bitfld.long 0x0 18.--19. "EPTYP,EPTYP" "0,1,2,3" rbitfld.long 0x0 17. "NAKSTS,NAKSTS" "0,1" newline rbitfld.long 0x0 16. "EONUM_DPIP,EONUM_DPIP" "0,1" endif sif (cpuis("STM32MP153*")) bitfld.long 0x0 18.--19. "EPTYP,EPTYP" "0,1,2,3" newline rbitfld.long 0x0 17. "NAKSTS,NAKSTS" "0,1" rbitfld.long 0x0 16. "EONUM_DPIP,EONUM_DPIP" "0,1" newline endif sif (cpuis("STM32MP157*")) bitfld.long 0x0 18.--19. "EPTYP,EPTYP" "0,1,2,3" rbitfld.long 0x0 17. "NAKSTS,NAKSTS" "0,1" newline rbitfld.long 0x0 16. "EONUM_DPIP,EONUM_DPIP" "0,1" endif bitfld.long 0x0 15. "USBAEP,USB active endpoint" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" group.long 0x9C8++0x3 line.long 0x0 "OTG_DIEPINT6,OTG device IN endpoint 6 interrupt register" bitfld.long 0x0 13. "NAK,NAK input" "0,1" bitfld.long 0x0 11. "PKTDRPSTS,Packet dropped status" "0,1" newline bitfld.long 0x0 9. "BNA,Buffer not available interrupt" "0,1" bitfld.long 0x0 8. "TXFIFOUDRN,Transmit Fifo Underrun (TxfifoUndrn)" "0,1" newline rbitfld.long 0x0 7. "TXFE,Transmit FIFO empty" "0,1" sif (cpuis("STM32MP13*")) bitfld.long 0x0 6. "INEPNE,IN endpoint NAK effective" "0,1" newline endif sif (cpuis("STM32MP151*")) rbitfld.long 0x0 6. "INEPNE,INEPNE" "0,1" endif sif (cpuis("STM32MP153*")) rbitfld.long 0x0 6. "INEPNE,INEPNE" "0,1" newline endif sif (cpuis("STM32MP157*")) rbitfld.long 0x0 6. "INEPNE,INEPNE" "0,1" endif bitfld.long 0x0 5. "INEPNM,IN token received with EP mismatch" "0,1" newline bitfld.long 0x0 4. "ITTXFE,IN token received when Tx FIFO is empty" "0,1" bitfld.long 0x0 3. "TOC,Timeout condition" "0,1" newline bitfld.long 0x0 2. "AHBERR,AHB error" "0,1" bitfld.long 0x0 1. "EPDISD,Endpoint disabled interrupt" "0,1" newline bitfld.long 0x0 0. "XFRC,Transfer completed interrupt" "0,1" group.long 0x9D0++0xB line.long 0x0 "OTG_DIEPTSIZ6,OTG device IN endpoint 6 transfer size register" sif (cpuis("STM32MP13*")) bitfld.long 0x0 29.--30. "MCNT,Multi count" "?,1: 1 packet,2: 2 packets,3: 3 packets" endif sif (cpuis("STM32MP151*")) bitfld.long 0x0 29.--30. "MCNT,MCNT" "0,1,2,3" newline endif sif (cpuis("STM32MP153*")) bitfld.long 0x0 29.--30. "MCNT,MCNT" "0,1,2,3" endif sif (cpuis("STM32MP157*")) bitfld.long 0x0 29.--30. "MCNT,MCNT" "0,1,2,3" newline endif hexmask.long.word 0x0 19.--28. 1. "PKTCNT,Packet count" hexmask.long.tbyte 0x0 0.--18. 1. "XFRSIZ,Transfer size" line.long 0x4 "OTG_DIEPDMA6," hexmask.long 0x4 0.--31. 1. "DMAADDR,DMA Address" line.long 0x8 "OTG_DTXFSTS6,OTG device IN endpoint transmit FIFO status register" sif (cpuis("STM32MP13*")) hexmask.long.word 0x8 0.--15. 1. "INEPTFSAV,IN endpoint Tx FIFO space available" endif sif (cpuis("STM32MP151*")) hexmask.long.word 0x8 0.--15. 1. "INEPTFSAV,INEPTFSAV" newline endif sif (cpuis("STM32MP153*")) hexmask.long.word 0x8 0.--15. 1. "INEPTFSAV,INEPTFSAV" endif sif (cpuis("STM32MP157*")) hexmask.long.word 0x8 0.--15. 1. "INEPTFSAV,INEPTFSAV" endif group.long 0x9E0++0x3 line.long 0x0 "OTG_DIEPCTL7,OTG device IN endpoint 7 control register" bitfld.long 0x0 31. "EPENA,Endpoint enable" "0,1" bitfld.long 0x0 30. "EPDIS,Endpoint disable" "0,1" newline bitfld.long 0x0 29. "SODDFRM,Set odd frame" "0,1" sif (cpuis("STM32MP13*")) bitfld.long 0x0 28. "SEVNFRM,Set even frame" "0,1" newline bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt" rbitfld.long 0x0 17. "NAKSTS,NAK status" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.." newline rbitfld.long 0x0 16. "EONUM,Even/odd frame" "0: Even frame,1: Odd frame" endif sif (cpuis("STM32MP151*")) bitfld.long 0x0 28. "SD0PID_SEVNFRM,SD0PID_SEVNFRM" "0,1" newline endif sif (cpuis("STM32MP153*")) bitfld.long 0x0 28. "SD0PID_SEVNFRM,SD0PID_SEVNFRM" "0,1" endif sif (cpuis("STM32MP157*")) bitfld.long 0x0 28. "SD0PID_SEVNFRM,SD0PID_SEVNFRM" "0,1" newline endif bitfld.long 0x0 27. "SNAK,Set NAK" "0,1" bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1" newline hexmask.long.byte 0x0 22.--25. 1. "TXFNUM,Tx FIFO number" bitfld.long 0x0 21. "STALL,STALL handshake" "0,1" newline sif (cpuis("STM32MP151*")) bitfld.long 0x0 18.--19. "EPTYP,EPTYP" "0,1,2,3" rbitfld.long 0x0 17. "NAKSTS,NAKSTS" "0,1" newline rbitfld.long 0x0 16. "EONUM_DPIP,EONUM_DPIP" "0,1" endif sif (cpuis("STM32MP153*")) bitfld.long 0x0 18.--19. "EPTYP,EPTYP" "0,1,2,3" newline rbitfld.long 0x0 17. "NAKSTS,NAKSTS" "0,1" rbitfld.long 0x0 16. "EONUM_DPIP,EONUM_DPIP" "0,1" newline endif sif (cpuis("STM32MP157*")) bitfld.long 0x0 18.--19. "EPTYP,EPTYP" "0,1,2,3" rbitfld.long 0x0 17. "NAKSTS,NAKSTS" "0,1" newline rbitfld.long 0x0 16. "EONUM_DPIP,EONUM_DPIP" "0,1" endif bitfld.long 0x0 15. "USBAEP,USB active endpoint" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" group.long 0x9E8++0x3 line.long 0x0 "OTG_DIEPINT7,OTG device IN endpoint 7 interrupt register" bitfld.long 0x0 13. "NAK,NAK input" "0,1" bitfld.long 0x0 11. "PKTDRPSTS,Packet dropped status" "0,1" newline bitfld.long 0x0 9. "BNA,Buffer not available interrupt" "0,1" bitfld.long 0x0 8. "TXFIFOUDRN,Transmit Fifo Underrun (TxfifoUndrn)" "0,1" newline rbitfld.long 0x0 7. "TXFE,Transmit FIFO empty" "0,1" sif (cpuis("STM32MP13*")) bitfld.long 0x0 6. "INEPNE,IN endpoint NAK effective" "0,1" newline endif sif (cpuis("STM32MP151*")) rbitfld.long 0x0 6. "INEPNE,INEPNE" "0,1" endif sif (cpuis("STM32MP153*")) rbitfld.long 0x0 6. "INEPNE,INEPNE" "0,1" newline endif sif (cpuis("STM32MP157*")) rbitfld.long 0x0 6. "INEPNE,INEPNE" "0,1" endif bitfld.long 0x0 5. "INEPNM,IN token received with EP mismatch" "0,1" newline bitfld.long 0x0 4. "ITTXFE,IN token received when Tx FIFO is empty" "0,1" bitfld.long 0x0 3. "TOC,Timeout condition" "0,1" newline bitfld.long 0x0 2. "AHBERR,AHB error" "0,1" bitfld.long 0x0 1. "EPDISD,Endpoint disabled interrupt" "0,1" newline bitfld.long 0x0 0. "XFRC,Transfer completed interrupt" "0,1" group.long 0x9F0++0xB line.long 0x0 "OTG_DIEPTSIZ7,OTG device IN endpoint 7 transfer size register" sif (cpuis("STM32MP13*")) bitfld.long 0x0 29.--30. "MCNT,Multi count" "?,1: 1 packet,2: 2 packets,3: 3 packets" endif sif (cpuis("STM32MP151*")) bitfld.long 0x0 29.--30. "MCNT,MCNT" "0,1,2,3" newline endif sif (cpuis("STM32MP153*")) bitfld.long 0x0 29.--30. "MCNT,MCNT" "0,1,2,3" endif sif (cpuis("STM32MP157*")) bitfld.long 0x0 29.--30. "MCNT,MCNT" "0,1,2,3" newline endif hexmask.long.word 0x0 19.--28. 1. "PKTCNT,Packet count" hexmask.long.tbyte 0x0 0.--18. 1. "XFRSIZ,Transfer size" line.long 0x4 "OTG_DIEPDMA7," hexmask.long 0x4 0.--31. 1. "DMAADDR,DMA Address" line.long 0x8 "OTG_DTXFSTS7,OTG device IN endpoint transmit FIFO status register" sif (cpuis("STM32MP13*")) hexmask.long.word 0x8 0.--15. 1. "INEPTFSAV,IN endpoint Tx FIFO space available" endif sif (cpuis("STM32MP151*")) hexmask.long.word 0x8 0.--15. 1. "INEPTFSAV,INEPTFSAV" newline endif sif (cpuis("STM32MP153*")) hexmask.long.word 0x8 0.--15. 1. "INEPTFSAV,INEPTFSAV" endif sif (cpuis("STM32MP157*")) hexmask.long.word 0x8 0.--15. 1. "INEPTFSAV,INEPTFSAV" endif group.long 0xA00++0x3 line.long 0x0 "OTG_DIEPCTL8,OTG device IN endpoint 8 control register" bitfld.long 0x0 31. "EPENA,Endpoint enable" "0,1" bitfld.long 0x0 30. "EPDIS,Endpoint disable" "0,1" newline bitfld.long 0x0 29. "SODDFRM,Set odd frame" "0,1" sif (cpuis("STM32MP13*")) bitfld.long 0x0 28. "SEVNFRM,Set even frame" "0,1" newline bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt" rbitfld.long 0x0 17. "NAKSTS,NAK status" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.." newline rbitfld.long 0x0 16. "EONUM,Even/odd frame" "0: Even frame,1: Odd frame" endif sif (cpuis("STM32MP151*")) bitfld.long 0x0 28. "SD0PID_SEVNFRM,SD0PID_SEVNFRM" "0,1" newline endif sif (cpuis("STM32MP153*")) bitfld.long 0x0 28. "SD0PID_SEVNFRM,SD0PID_SEVNFRM" "0,1" endif sif (cpuis("STM32MP157*")) bitfld.long 0x0 28. "SD0PID_SEVNFRM,SD0PID_SEVNFRM" "0,1" newline endif bitfld.long 0x0 27. "SNAK,Set NAK" "0,1" bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1" newline hexmask.long.byte 0x0 22.--25. 1. "TXFNUM,Tx FIFO number" bitfld.long 0x0 21. "STALL,STALL handshake" "0,1" newline sif (cpuis("STM32MP151*")) bitfld.long 0x0 18.--19. "EPTYP,EPTYP" "0,1,2,3" rbitfld.long 0x0 17. "NAKSTS,NAKSTS" "0,1" newline rbitfld.long 0x0 16. "EONUM_DPIP,EONUM_DPIP" "0,1" endif sif (cpuis("STM32MP153*")) bitfld.long 0x0 18.--19. "EPTYP,EPTYP" "0,1,2,3" newline rbitfld.long 0x0 17. "NAKSTS,NAKSTS" "0,1" rbitfld.long 0x0 16. "EONUM_DPIP,EONUM_DPIP" "0,1" newline endif sif (cpuis("STM32MP157*")) bitfld.long 0x0 18.--19. "EPTYP,EPTYP" "0,1,2,3" rbitfld.long 0x0 17. "NAKSTS,NAKSTS" "0,1" newline rbitfld.long 0x0 16. "EONUM_DPIP,EONUM_DPIP" "0,1" endif bitfld.long 0x0 15. "USBAEP,USB active endpoint" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" group.long 0xA08++0x3 line.long 0x0 "OTG_DIEPINT8,OTG device IN endpoint 8 interrupt register" bitfld.long 0x0 13. "NAK,NAK input" "0,1" bitfld.long 0x0 11. "PKTDRPSTS,Packet dropped status" "0,1" newline bitfld.long 0x0 9. "BNA,Buffer not available interrupt" "0,1" bitfld.long 0x0 8. "TXFIFOUDRN,Transmit Fifo Underrun (TxfifoUndrn)" "0,1" newline rbitfld.long 0x0 7. "TXFE,Transmit FIFO empty" "0,1" sif (cpuis("STM32MP13*")) bitfld.long 0x0 6. "INEPNE,IN endpoint NAK effective" "0,1" newline endif sif (cpuis("STM32MP151*")) rbitfld.long 0x0 6. "INEPNE,INEPNE" "0,1" endif sif (cpuis("STM32MP153*")) rbitfld.long 0x0 6. "INEPNE,INEPNE" "0,1" newline endif sif (cpuis("STM32MP157*")) rbitfld.long 0x0 6. "INEPNE,INEPNE" "0,1" endif bitfld.long 0x0 5. "INEPNM,IN token received with EP mismatch" "0,1" newline bitfld.long 0x0 4. "ITTXFE,IN token received when Tx FIFO is empty" "0,1" bitfld.long 0x0 3. "TOC,Timeout condition" "0,1" newline bitfld.long 0x0 2. "AHBERR,AHB error" "0,1" bitfld.long 0x0 1. "EPDISD,Endpoint disabled interrupt" "0,1" newline bitfld.long 0x0 0. "XFRC,Transfer completed interrupt" "0,1" group.long 0xA10++0xB line.long 0x0 "OTG_DIEPTSIZ8,OTG device IN endpoint 8 transfer size register" sif (cpuis("STM32MP13*")) bitfld.long 0x0 29.--30. "MCNT,Multi count" "?,1: 1 packet,2: 2 packets,3: 3 packets" endif sif (cpuis("STM32MP151*")) bitfld.long 0x0 29.--30. "MCNT,MCNT" "0,1,2,3" newline endif sif (cpuis("STM32MP153*")) bitfld.long 0x0 29.--30. "MCNT,MCNT" "0,1,2,3" endif sif (cpuis("STM32MP157*")) bitfld.long 0x0 29.--30. "MCNT,MCNT" "0,1,2,3" newline endif hexmask.long.word 0x0 19.--28. 1. "PKTCNT,Packet count" hexmask.long.tbyte 0x0 0.--18. 1. "XFRSIZ,Transfer size" line.long 0x4 "OTG_DIEPDMA8," hexmask.long 0x4 0.--31. 1. "DMAADDR,DMA Address" line.long 0x8 "OTG_DTXFSTS8,OTG device IN endpoint transmit FIFO status register" sif (cpuis("STM32MP13*")) hexmask.long.word 0x8 0.--15. 1. "INEPTFSAV,IN endpoint Tx FIFO space available" endif sif (cpuis("STM32MP151*")) hexmask.long.word 0x8 0.--15. 1. "INEPTFSAV,INEPTFSAV" newline endif sif (cpuis("STM32MP153*")) hexmask.long.word 0x8 0.--15. 1. "INEPTFSAV,INEPTFSAV" endif sif (cpuis("STM32MP157*")) hexmask.long.word 0x8 0.--15. 1. "INEPTFSAV,INEPTFSAV" endif group.long 0xB00++0x3 line.long 0x0 "OTG_DOEPCTL0,OTG device control OUT endpoint 0 control register" bitfld.long 0x0 31. "EPENA,Endpoint enable" "0,1" rbitfld.long 0x0 30. "EPDIS,Endpoint disable" "0,1" newline bitfld.long 0x0 27. "SNAK,Set NAK" "0,1" bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1" newline bitfld.long 0x0 21. "STALL,STALL handshake" "0,1" bitfld.long 0x0 20. "SNPM,Snoop mode" "0,1" newline rbitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0,1,2,3" sif (cpuis("STM32MP13*")) rbitfld.long 0x0 17. "NAKSTS,NAK status" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.." newline rbitfld.long 0x0 0.--1. "MPSIZ,Maximum packet size" "0: 64 bytes,1: 32 bytes,2: 16 bytes,3: 8 bytes" endif sif (cpuis("STM32MP151*")) rbitfld.long 0x0 17. "NAKSTS,NAKSTS" "0,1" newline endif sif (cpuis("STM32MP153*")) rbitfld.long 0x0 17. "NAKSTS,NAKSTS" "0,1" endif sif (cpuis("STM32MP157*")) rbitfld.long 0x0 17. "NAKSTS,NAKSTS" "0,1" newline endif rbitfld.long 0x0 15. "USBAEP,USB active endpoint" "0,1" sif (cpuis("STM32MP153*")) rbitfld.long 0x0 0.--1. "MPSIZ,MPSIZ" "0,1,2,3" newline endif sif (cpuis("STM32MP157*")) rbitfld.long 0x0 0.--1. "MPSIZ,MPSIZ" "0,1,2,3" endif group.long 0xB08++0x3 line.long 0x0 "OTG_DOEPINT0,OTG device OUT endpoint 0 interrupt register" bitfld.long 0x0 15. "STPKTRX,Setup packet received" "0,1" bitfld.long 0x0 14. "NYET,NYET interrupt" "0,1" newline bitfld.long 0x0 13. "NAK,NAK input" "0,1" bitfld.long 0x0 12. "BERR,Babble error interrupt" "0,1" newline bitfld.long 0x0 9. "BNA,Buffer not available interrupt" "0,1" bitfld.long 0x0 8. "OUTPKTERR,OUT packet error" "0,1" newline bitfld.long 0x0 6. "B2BSTUP,Back-to-back SETUP packets received" "0,1" bitfld.long 0x0 5. "STSPHSRX,Status phase received for control write" "0,1" newline bitfld.long 0x0 4. "OTEPDIS,OUT token received when endpoint disabled" "0,1" bitfld.long 0x0 3. "STUP,SETUP phase done" "0,1" newline bitfld.long 0x0 2. "AHBERR,AHB error" "0,1" bitfld.long 0x0 1. "EPDISD,Endpoint disabled interrupt" "0,1" newline bitfld.long 0x0 0. "XFRC,Transfer completed interrupt" "0,1" group.long 0xB10++0x7 line.long 0x0 "OTG_DOEPTSIZ0,OTG device OUT endpoint 0 transfer size register" sif (cpuis("STM32MP13*")) bitfld.long 0x0 29.--30. "STUPCNT,SETUP packet count" "?,1: 1 packet,2: 2 packets,3: 3 packets" endif sif (cpuis("STM32MP151*")) bitfld.long 0x0 29.--30. "STUPCNT,STUPCNT" "0,1,2,3" newline endif sif (cpuis("STM32MP153*")) bitfld.long 0x0 29.--30. "STUPCNT,STUPCNT" "0,1,2,3" endif sif (cpuis("STM32MP157*")) bitfld.long 0x0 29.--30. "STUPCNT,STUPCNT" "0,1,2,3" newline endif bitfld.long 0x0 19. "PKTCNT,Packet count" "0,1" hexmask.long.byte 0x0 0.--6. 1. "XFRSIZ,Transfer size" line.long 0x4 "OTG_DOEPDMA0," hexmask.long 0x4 0.--31. 1. "DMAADDR,DMA Address" group.long 0xB20++0x3 line.long 0x0 "OTG_DOEPCTL1,OTG device OUT endpoint 1 control register" bitfld.long 0x0 31. "EPENA,Endpoint enable" "0,1" bitfld.long 0x0 30. "EPDIS,Endpoint disable" "0,1" newline sif (cpuis("STM32MP13*")) bitfld.long 0x0 29. "SD1PID,Set DATA1 PID" "0,1" bitfld.long 0x0 28. "SD0PID,Set DATA0 PID" "0,1" newline bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt" rbitfld.long 0x0 17. "NAKSTS,NAK status" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.." newline rbitfld.long 0x0 16. "DPID,Endpoint data PID" "0: DATA0,1: DATA1" endif sif (cpuis("STM32MP151*")) bitfld.long 0x0 29. "SD1PID_SODDFRM,SD1PID_SODDFRM" "0,1" newline bitfld.long 0x0 28. "SD0PID_SEVNFRM,SD0PID_SEVNFRM" "0,1" endif sif (cpuis("STM32MP153*")) bitfld.long 0x0 29. "SD1PID_SODDFRM,SD1PID_SODDFRM" "0,1" newline bitfld.long 0x0 28. "SD0PID_SEVNFRM,SD0PID_SEVNFRM" "0,1" endif sif (cpuis("STM32MP157*")) bitfld.long 0x0 29. "SD1PID_SODDFRM,SD1PID_SODDFRM" "0,1" newline bitfld.long 0x0 28. "SD0PID_SEVNFRM,SD0PID_SEVNFRM" "0,1" endif bitfld.long 0x0 27. "SNAK,Set NAK" "0,1" newline bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1" bitfld.long 0x0 21. "STALL,STALL handshake" "0,1" newline bitfld.long 0x0 20. "SNPM,Snoop mode" "0,1" sif (cpuis("STM32MP151*")) bitfld.long 0x0 18.--19. "EPTYP,EPTYP" "0,1,2,3" newline rbitfld.long 0x0 17. "NAKSTS,NAKSTS" "0,1" rbitfld.long 0x0 16. "EONUM_DPIP,EONUM_DPIP" "0,1" newline endif sif (cpuis("STM32MP153*")) bitfld.long 0x0 18.--19. "EPTYP,EPTYP" "0,1,2,3" rbitfld.long 0x0 17. "NAKSTS,NAKSTS" "0,1" newline rbitfld.long 0x0 16. "EONUM_DPIP,EONUM_DPIP" "0,1" endif sif (cpuis("STM32MP157*")) bitfld.long 0x0 18.--19. "EPTYP,EPTYP" "0,1,2,3" newline rbitfld.long 0x0 17. "NAKSTS,NAKSTS" "0,1" rbitfld.long 0x0 16. "EONUM_DPIP,EONUM_DPIP" "0,1" newline endif bitfld.long 0x0 15. "USBAEP,USB active endpoint" "0,1" hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" group.long 0xB28++0x3 line.long 0x0 "OTG_DOEPINT1,OTG device OUT endpoint 1 interrupt register" bitfld.long 0x0 15. "STPKTRX,Setup packet received" "0,1" bitfld.long 0x0 14. "NYET,NYET interrupt" "0,1" newline bitfld.long 0x0 13. "NAK,NAK input" "0,1" bitfld.long 0x0 12. "BERR,Babble error interrupt" "0,1" newline bitfld.long 0x0 9. "BNA,Buffer not available interrupt" "0,1" bitfld.long 0x0 8. "OUTPKTERR,OUT packet error" "0,1" newline bitfld.long 0x0 6. "B2BSTUP,Back-to-back SETUP packets received" "0,1" bitfld.long 0x0 5. "STSPHSRX,Status phase received for control write" "0,1" newline bitfld.long 0x0 4. "OTEPDIS,OUT token received when endpoint disabled" "0,1" bitfld.long 0x0 3. "STUP,SETUP phase done" "0,1" newline bitfld.long 0x0 2. "AHBERR,AHB error" "0,1" bitfld.long 0x0 1. "EPDISD,Endpoint disabled interrupt" "0,1" newline bitfld.long 0x0 0. "XFRC,Transfer completed interrupt" "0,1" group.long 0xB30++0x7 line.long 0x0 "OTG_DOEPTSIZ1,OTG device OUT endpoint 1 transfer size register" sif (cpuis("STM32MP13*")) bitfld.long 0x0 29.--30. "RXDPID,Received data PID" "0: DATA0,1: DATA2,2: DATA1,3: MDATA" endif sif (cpuis("STM32MP151*")) bitfld.long 0x0 29.--30. "RXDPID_STUPCNT,RXDPID_STUPCNT" "0,1,2,3" newline endif sif (cpuis("STM32MP153*")) bitfld.long 0x0 29.--30. "RXDPID_STUPCNT,RXDPID_STUPCNT" "0,1,2,3" endif sif (cpuis("STM32MP157*")) bitfld.long 0x0 29.--30. "RXDPID_STUPCNT,RXDPID_STUPCNT" "0,1,2,3" newline endif hexmask.long.word 0x0 19.--28. 1. "PKTCNT,Packet count" hexmask.long.tbyte 0x0 0.--18. 1. "XFRSIZ,Transfer size" line.long 0x4 "OTG_DOEPDMA1," hexmask.long 0x4 0.--31. 1. "DMAADDR,DMA Address" group.long 0xB40++0x3 line.long 0x0 "OTG_DOEPCTL2,OTG device OUT endpoint 2 control register" bitfld.long 0x0 31. "EPENA,Endpoint enable" "0,1" bitfld.long 0x0 30. "EPDIS,Endpoint disable" "0,1" newline sif (cpuis("STM32MP13*")) bitfld.long 0x0 29. "SD1PID,Set DATA1 PID" "0,1" bitfld.long 0x0 28. "SD0PID,Set DATA0 PID" "0,1" newline bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt" rbitfld.long 0x0 17. "NAKSTS,NAK status" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.." newline rbitfld.long 0x0 16. "DPID,Endpoint data PID" "0: DATA0,1: DATA1" endif sif (cpuis("STM32MP151*")) bitfld.long 0x0 29. "SD1PID_SODDFRM,SD1PID_SODDFRM" "0,1" newline bitfld.long 0x0 28. "SD0PID_SEVNFRM,SD0PID_SEVNFRM" "0,1" endif sif (cpuis("STM32MP153*")) bitfld.long 0x0 29. "SD1PID_SODDFRM,SD1PID_SODDFRM" "0,1" newline bitfld.long 0x0 28. "SD0PID_SEVNFRM,SD0PID_SEVNFRM" "0,1" endif sif (cpuis("STM32MP157*")) bitfld.long 0x0 29. "SD1PID_SODDFRM,SD1PID_SODDFRM" "0,1" newline bitfld.long 0x0 28. "SD0PID_SEVNFRM,SD0PID_SEVNFRM" "0,1" endif bitfld.long 0x0 27. "SNAK,Set NAK" "0,1" newline bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1" bitfld.long 0x0 21. "STALL,STALL handshake" "0,1" newline bitfld.long 0x0 20. "SNPM,Snoop mode" "0,1" sif (cpuis("STM32MP151*")) bitfld.long 0x0 18.--19. "EPTYP,EPTYP" "0,1,2,3" newline rbitfld.long 0x0 17. "NAKSTS,NAKSTS" "0,1" rbitfld.long 0x0 16. "EONUM_DPIP,EONUM_DPIP" "0,1" newline endif sif (cpuis("STM32MP153*")) bitfld.long 0x0 18.--19. "EPTYP,EPTYP" "0,1,2,3" rbitfld.long 0x0 17. "NAKSTS,NAKSTS" "0,1" newline rbitfld.long 0x0 16. "EONUM_DPIP,EONUM_DPIP" "0,1" endif sif (cpuis("STM32MP157*")) bitfld.long 0x0 18.--19. "EPTYP,EPTYP" "0,1,2,3" newline rbitfld.long 0x0 17. "NAKSTS,NAKSTS" "0,1" rbitfld.long 0x0 16. "EONUM_DPIP,EONUM_DPIP" "0,1" newline endif bitfld.long 0x0 15. "USBAEP,USB active endpoint" "0,1" hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" group.long 0xB48++0x3 line.long 0x0 "OTG_DOEPINT2,OTG device OUT endpoint 2 interrupt register" bitfld.long 0x0 15. "STPKTRX,Setup packet received" "0,1" bitfld.long 0x0 14. "NYET,NYET interrupt" "0,1" newline bitfld.long 0x0 13. "NAK,NAK input" "0,1" bitfld.long 0x0 12. "BERR,Babble error interrupt" "0,1" newline bitfld.long 0x0 9. "BNA,Buffer not available interrupt" "0,1" bitfld.long 0x0 8. "OUTPKTERR,OUT packet error" "0,1" newline bitfld.long 0x0 6. "B2BSTUP,Back-to-back SETUP packets received" "0,1" bitfld.long 0x0 5. "STSPHSRX,Status phase received for control write" "0,1" newline bitfld.long 0x0 4. "OTEPDIS,OUT token received when endpoint disabled" "0,1" bitfld.long 0x0 3. "STUP,SETUP phase done" "0,1" newline bitfld.long 0x0 2. "AHBERR,AHB error" "0,1" bitfld.long 0x0 1. "EPDISD,Endpoint disabled interrupt" "0,1" newline bitfld.long 0x0 0. "XFRC,Transfer completed interrupt" "0,1" group.long 0xB50++0x7 line.long 0x0 "OTG_DOEPTSIZ2,OTG device OUT endpoint 2 transfer size register" sif (cpuis("STM32MP13*")) bitfld.long 0x0 29.--30. "RXDPID,Received data PID" "0: DATA0,1: DATA2,2: DATA1,3: MDATA" endif sif (cpuis("STM32MP151*")) bitfld.long 0x0 29.--30. "RXDPID_STUPCNT,RXDPID_STUPCNT" "0,1,2,3" newline endif sif (cpuis("STM32MP153*")) bitfld.long 0x0 29.--30. "RXDPID_STUPCNT,RXDPID_STUPCNT" "0,1,2,3" endif sif (cpuis("STM32MP157*")) bitfld.long 0x0 29.--30. "RXDPID_STUPCNT,RXDPID_STUPCNT" "0,1,2,3" newline endif hexmask.long.word 0x0 19.--28. 1. "PKTCNT,Packet count" hexmask.long.tbyte 0x0 0.--18. 1. "XFRSIZ,Transfer size" line.long 0x4 "OTG_DOEPDMA2," hexmask.long 0x4 0.--31. 1. "DMAADDR,DMA Address" group.long 0xB60++0x3 line.long 0x0 "OTG_DOEPCTL3,OTG device OUT endpoint 3 control register" bitfld.long 0x0 31. "EPENA,Endpoint enable" "0,1" bitfld.long 0x0 30. "EPDIS,Endpoint disable" "0,1" newline sif (cpuis("STM32MP13*")) bitfld.long 0x0 29. "SD1PID,Set DATA1 PID" "0,1" bitfld.long 0x0 28. "SD0PID,Set DATA0 PID" "0,1" newline bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt" rbitfld.long 0x0 17. "NAKSTS,NAK status" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.." newline rbitfld.long 0x0 16. "DPID,Endpoint data PID" "0: DATA0,1: DATA1" endif sif (cpuis("STM32MP151*")) bitfld.long 0x0 29. "SD1PID_SODDFRM,SD1PID_SODDFRM" "0,1" newline bitfld.long 0x0 28. "SD0PID_SEVNFRM,SD0PID_SEVNFRM" "0,1" endif sif (cpuis("STM32MP153*")) bitfld.long 0x0 29. "SD1PID_SODDFRM,SD1PID_SODDFRM" "0,1" newline bitfld.long 0x0 28. "SD0PID_SEVNFRM,SD0PID_SEVNFRM" "0,1" endif sif (cpuis("STM32MP157*")) bitfld.long 0x0 29. "SD1PID_SODDFRM,SD1PID_SODDFRM" "0,1" newline bitfld.long 0x0 28. "SD0PID_SEVNFRM,SD0PID_SEVNFRM" "0,1" endif bitfld.long 0x0 27. "SNAK,Set NAK" "0,1" newline bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1" bitfld.long 0x0 21. "STALL,STALL handshake" "0,1" newline bitfld.long 0x0 20. "SNPM,Snoop mode" "0,1" sif (cpuis("STM32MP151*")) bitfld.long 0x0 18.--19. "EPTYP,EPTYP" "0,1,2,3" newline rbitfld.long 0x0 17. "NAKSTS,NAKSTS" "0,1" rbitfld.long 0x0 16. "EONUM_DPIP,EONUM_DPIP" "0,1" newline endif sif (cpuis("STM32MP153*")) bitfld.long 0x0 18.--19. "EPTYP,EPTYP" "0,1,2,3" rbitfld.long 0x0 17. "NAKSTS,NAKSTS" "0,1" newline rbitfld.long 0x0 16. "EONUM_DPIP,EONUM_DPIP" "0,1" endif sif (cpuis("STM32MP157*")) bitfld.long 0x0 18.--19. "EPTYP,EPTYP" "0,1,2,3" newline rbitfld.long 0x0 17. "NAKSTS,NAKSTS" "0,1" rbitfld.long 0x0 16. "EONUM_DPIP,EONUM_DPIP" "0,1" newline endif bitfld.long 0x0 15. "USBAEP,USB active endpoint" "0,1" hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" group.long 0xB68++0x3 line.long 0x0 "OTG_DOEPINT3,OTG device OUT endpoint 3 interrupt register" bitfld.long 0x0 15. "STPKTRX,Setup packet received" "0,1" bitfld.long 0x0 14. "NYET,NYET interrupt" "0,1" newline bitfld.long 0x0 13. "NAK,NAK input" "0,1" bitfld.long 0x0 12. "BERR,Babble error interrupt" "0,1" newline bitfld.long 0x0 9. "BNA,Buffer not available interrupt" "0,1" bitfld.long 0x0 8. "OUTPKTERR,OUT packet error" "0,1" newline bitfld.long 0x0 6. "B2BSTUP,Back-to-back SETUP packets received" "0,1" bitfld.long 0x0 5. "STSPHSRX,Status phase received for control write" "0,1" newline bitfld.long 0x0 4. "OTEPDIS,OUT token received when endpoint disabled" "0,1" bitfld.long 0x0 3. "STUP,SETUP phase done" "0,1" newline bitfld.long 0x0 2. "AHBERR,AHB error" "0,1" bitfld.long 0x0 1. "EPDISD,Endpoint disabled interrupt" "0,1" newline bitfld.long 0x0 0. "XFRC,Transfer completed interrupt" "0,1" group.long 0xB70++0x7 line.long 0x0 "OTG_DOEPTSIZ3,OTG device OUT endpoint 3 transfer size register" sif (cpuis("STM32MP13*")) bitfld.long 0x0 29.--30. "RXDPID,Received data PID" "0: DATA0,1: DATA2,2: DATA1,3: MDATA" endif sif (cpuis("STM32MP151*")) bitfld.long 0x0 29.--30. "RXDPID_STUPCNT,RXDPID_STUPCNT" "0,1,2,3" newline endif sif (cpuis("STM32MP153*")) bitfld.long 0x0 29.--30. "RXDPID_STUPCNT,RXDPID_STUPCNT" "0,1,2,3" endif sif (cpuis("STM32MP157*")) bitfld.long 0x0 29.--30. "RXDPID_STUPCNT,RXDPID_STUPCNT" "0,1,2,3" newline endif hexmask.long.word 0x0 19.--28. 1. "PKTCNT,Packet count" hexmask.long.tbyte 0x0 0.--18. 1. "XFRSIZ,Transfer size" line.long 0x4 "OTG_DOEPDMA3," hexmask.long 0x4 0.--31. 1. "DMAADDR,DMA Address" group.long 0xB80++0x3 line.long 0x0 "OTG_DOEPCTL4,OTG device OUT endpoint 4 control register" bitfld.long 0x0 31. "EPENA,Endpoint enable" "0,1" bitfld.long 0x0 30. "EPDIS,Endpoint disable" "0,1" newline sif (cpuis("STM32MP13*")) bitfld.long 0x0 29. "SD1PID,Set DATA1 PID" "0,1" bitfld.long 0x0 28. "SD0PID,Set DATA0 PID" "0,1" newline bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt" rbitfld.long 0x0 17. "NAKSTS,NAK status" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.." newline rbitfld.long 0x0 16. "DPID,Endpoint data PID" "0: DATA0,1: DATA1" endif sif (cpuis("STM32MP151*")) bitfld.long 0x0 29. "SD1PID_SODDFRM,SD1PID_SODDFRM" "0,1" newline bitfld.long 0x0 28. "SD0PID_SEVNFRM,SD0PID_SEVNFRM" "0,1" endif sif (cpuis("STM32MP153*")) bitfld.long 0x0 29. "SD1PID_SODDFRM,SD1PID_SODDFRM" "0,1" newline bitfld.long 0x0 28. "SD0PID_SEVNFRM,SD0PID_SEVNFRM" "0,1" endif sif (cpuis("STM32MP157*")) bitfld.long 0x0 29. "SD1PID_SODDFRM,SD1PID_SODDFRM" "0,1" newline bitfld.long 0x0 28. "SD0PID_SEVNFRM,SD0PID_SEVNFRM" "0,1" endif bitfld.long 0x0 27. "SNAK,Set NAK" "0,1" newline bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1" bitfld.long 0x0 21. "STALL,STALL handshake" "0,1" newline bitfld.long 0x0 20. "SNPM,Snoop mode" "0,1" sif (cpuis("STM32MP151*")) bitfld.long 0x0 18.--19. "EPTYP,EPTYP" "0,1,2,3" newline rbitfld.long 0x0 17. "NAKSTS,NAKSTS" "0,1" rbitfld.long 0x0 16. "EONUM_DPIP,EONUM_DPIP" "0,1" newline endif sif (cpuis("STM32MP153*")) bitfld.long 0x0 18.--19. "EPTYP,EPTYP" "0,1,2,3" rbitfld.long 0x0 17. "NAKSTS,NAKSTS" "0,1" newline rbitfld.long 0x0 16. "EONUM_DPIP,EONUM_DPIP" "0,1" endif sif (cpuis("STM32MP157*")) bitfld.long 0x0 18.--19. "EPTYP,EPTYP" "0,1,2,3" newline rbitfld.long 0x0 17. "NAKSTS,NAKSTS" "0,1" rbitfld.long 0x0 16. "EONUM_DPIP,EONUM_DPIP" "0,1" newline endif bitfld.long 0x0 15. "USBAEP,USB active endpoint" "0,1" hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" group.long 0xB88++0x3 line.long 0x0 "OTG_DOEPINT4,OTG device OUT endpoint 4 interrupt register" bitfld.long 0x0 15. "STPKTRX,Setup packet received" "0,1" bitfld.long 0x0 14. "NYET,NYET interrupt" "0,1" newline bitfld.long 0x0 13. "NAK,NAK input" "0,1" bitfld.long 0x0 12. "BERR,Babble error interrupt" "0,1" newline bitfld.long 0x0 9. "BNA,Buffer not available interrupt" "0,1" bitfld.long 0x0 8. "OUTPKTERR,OUT packet error" "0,1" newline bitfld.long 0x0 6. "B2BSTUP,Back-to-back SETUP packets received" "0,1" bitfld.long 0x0 5. "STSPHSRX,Status phase received for control write" "0,1" newline bitfld.long 0x0 4. "OTEPDIS,OUT token received when endpoint disabled" "0,1" bitfld.long 0x0 3. "STUP,SETUP phase done" "0,1" newline bitfld.long 0x0 2. "AHBERR,AHB error" "0,1" bitfld.long 0x0 1. "EPDISD,Endpoint disabled interrupt" "0,1" newline bitfld.long 0x0 0. "XFRC,Transfer completed interrupt" "0,1" group.long 0xB90++0x7 line.long 0x0 "OTG_DOEPTSIZ4,OTG device OUT endpoint 4 transfer size register" sif (cpuis("STM32MP13*")) bitfld.long 0x0 29.--30. "RXDPID,Received data PID" "0: DATA0,1: DATA2,2: DATA1,3: MDATA" endif sif (cpuis("STM32MP151*")) bitfld.long 0x0 29.--30. "RXDPID_STUPCNT,RXDPID_STUPCNT" "0,1,2,3" newline endif sif (cpuis("STM32MP153*")) bitfld.long 0x0 29.--30. "RXDPID_STUPCNT,RXDPID_STUPCNT" "0,1,2,3" endif sif (cpuis("STM32MP157*")) bitfld.long 0x0 29.--30. "RXDPID_STUPCNT,RXDPID_STUPCNT" "0,1,2,3" newline endif hexmask.long.word 0x0 19.--28. 1. "PKTCNT,Packet count" hexmask.long.tbyte 0x0 0.--18. 1. "XFRSIZ,Transfer size" line.long 0x4 "OTG_DOEPDMA4," hexmask.long 0x4 0.--31. 1. "DMAADDR,DMA Address" group.long 0xBA0++0x3 line.long 0x0 "OTG_DOEPCTL5,OTG device OUT endpoint 5 control register" bitfld.long 0x0 31. "EPENA,Endpoint enable" "0,1" bitfld.long 0x0 30. "EPDIS,Endpoint disable" "0,1" newline sif (cpuis("STM32MP13*")) bitfld.long 0x0 29. "SD1PID,Set DATA1 PID" "0,1" bitfld.long 0x0 28. "SD0PID,Set DATA0 PID" "0,1" newline bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt" rbitfld.long 0x0 17. "NAKSTS,NAK status" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.." newline rbitfld.long 0x0 16. "DPID,Endpoint data PID" "0: DATA0,1: DATA1" endif sif (cpuis("STM32MP151*")) bitfld.long 0x0 29. "SD1PID_SODDFRM,SD1PID_SODDFRM" "0,1" newline bitfld.long 0x0 28. "SD0PID_SEVNFRM,SD0PID_SEVNFRM" "0,1" endif sif (cpuis("STM32MP153*")) bitfld.long 0x0 29. "SD1PID_SODDFRM,SD1PID_SODDFRM" "0,1" newline bitfld.long 0x0 28. "SD0PID_SEVNFRM,SD0PID_SEVNFRM" "0,1" endif sif (cpuis("STM32MP157*")) bitfld.long 0x0 29. "SD1PID_SODDFRM,SD1PID_SODDFRM" "0,1" newline bitfld.long 0x0 28. "SD0PID_SEVNFRM,SD0PID_SEVNFRM" "0,1" endif bitfld.long 0x0 27. "SNAK,Set NAK" "0,1" newline bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1" bitfld.long 0x0 21. "STALL,STALL handshake" "0,1" newline bitfld.long 0x0 20. "SNPM,Snoop mode" "0,1" sif (cpuis("STM32MP151*")) bitfld.long 0x0 18.--19. "EPTYP,EPTYP" "0,1,2,3" newline rbitfld.long 0x0 17. "NAKSTS,NAKSTS" "0,1" rbitfld.long 0x0 16. "EONUM_DPIP,EONUM_DPIP" "0,1" newline endif sif (cpuis("STM32MP153*")) bitfld.long 0x0 18.--19. "EPTYP,EPTYP" "0,1,2,3" rbitfld.long 0x0 17. "NAKSTS,NAKSTS" "0,1" newline rbitfld.long 0x0 16. "EONUM_DPIP,EONUM_DPIP" "0,1" endif sif (cpuis("STM32MP157*")) bitfld.long 0x0 18.--19. "EPTYP,EPTYP" "0,1,2,3" newline rbitfld.long 0x0 17. "NAKSTS,NAKSTS" "0,1" rbitfld.long 0x0 16. "EONUM_DPIP,EONUM_DPIP" "0,1" newline endif bitfld.long 0x0 15. "USBAEP,USB active endpoint" "0,1" hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" group.long 0xBA8++0x3 line.long 0x0 "OTG_DOEPINT5,OTG device OUT endpoint 5 interrupt register" bitfld.long 0x0 15. "STPKTRX,Setup packet received" "0,1" bitfld.long 0x0 14. "NYET,NYET interrupt" "0,1" newline bitfld.long 0x0 13. "NAK,NAK input" "0,1" bitfld.long 0x0 12. "BERR,Babble error interrupt" "0,1" newline bitfld.long 0x0 9. "BNA,Buffer not available interrupt" "0,1" bitfld.long 0x0 8. "OUTPKTERR,OUT packet error" "0,1" newline bitfld.long 0x0 6. "B2BSTUP,Back-to-back SETUP packets received" "0,1" bitfld.long 0x0 5. "STSPHSRX,Status phase received for control write" "0,1" newline bitfld.long 0x0 4. "OTEPDIS,OUT token received when endpoint disabled" "0,1" bitfld.long 0x0 3. "STUP,SETUP phase done" "0,1" newline bitfld.long 0x0 2. "AHBERR,AHB error" "0,1" bitfld.long 0x0 1. "EPDISD,Endpoint disabled interrupt" "0,1" newline bitfld.long 0x0 0. "XFRC,Transfer completed interrupt" "0,1" group.long 0xBB0++0x7 line.long 0x0 "OTG_DOEPTSIZ5,OTG device OUT endpoint 5 transfer size register" sif (cpuis("STM32MP13*")) bitfld.long 0x0 29.--30. "RXDPID,Received data PID" "0: DATA0,1: DATA2,2: DATA1,3: MDATA" endif sif (cpuis("STM32MP151*")) bitfld.long 0x0 29.--30. "RXDPID_STUPCNT,RXDPID_STUPCNT" "0,1,2,3" newline endif sif (cpuis("STM32MP153*")) bitfld.long 0x0 29.--30. "RXDPID_STUPCNT,RXDPID_STUPCNT" "0,1,2,3" endif sif (cpuis("STM32MP157*")) bitfld.long 0x0 29.--30. "RXDPID_STUPCNT,RXDPID_STUPCNT" "0,1,2,3" newline endif hexmask.long.word 0x0 19.--28. 1. "PKTCNT,Packet count" hexmask.long.tbyte 0x0 0.--18. 1. "XFRSIZ,Transfer size" line.long 0x4 "OTG_DOEPDMA5," hexmask.long 0x4 0.--31. 1. "DMAADDR,DMA Address" group.long 0xBC0++0x3 line.long 0x0 "OTG_DOEPCTL6,OTG device OUT endpoint 6 control register" bitfld.long 0x0 31. "EPENA,Endpoint enable" "0,1" bitfld.long 0x0 30. "EPDIS,Endpoint disable" "0,1" newline sif (cpuis("STM32MP13*")) bitfld.long 0x0 29. "SD1PID,Set DATA1 PID" "0,1" bitfld.long 0x0 28. "SD0PID,Set DATA0 PID" "0,1" newline bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt" rbitfld.long 0x0 17. "NAKSTS,NAK status" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.." newline rbitfld.long 0x0 16. "DPID,Endpoint data PID" "0: DATA0,1: DATA1" endif sif (cpuis("STM32MP151*")) bitfld.long 0x0 29. "SD1PID_SODDFRM,SD1PID_SODDFRM" "0,1" newline bitfld.long 0x0 28. "SD0PID_SEVNFRM,SD0PID_SEVNFRM" "0,1" endif sif (cpuis("STM32MP153*")) bitfld.long 0x0 29. "SD1PID_SODDFRM,SD1PID_SODDFRM" "0,1" newline bitfld.long 0x0 28. "SD0PID_SEVNFRM,SD0PID_SEVNFRM" "0,1" endif sif (cpuis("STM32MP157*")) bitfld.long 0x0 29. "SD1PID_SODDFRM,SD1PID_SODDFRM" "0,1" newline bitfld.long 0x0 28. "SD0PID_SEVNFRM,SD0PID_SEVNFRM" "0,1" endif bitfld.long 0x0 27. "SNAK,Set NAK" "0,1" newline bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1" bitfld.long 0x0 21. "STALL,STALL handshake" "0,1" newline bitfld.long 0x0 20. "SNPM,Snoop mode" "0,1" sif (cpuis("STM32MP151*")) bitfld.long 0x0 18.--19. "EPTYP,EPTYP" "0,1,2,3" newline rbitfld.long 0x0 17. "NAKSTS,NAKSTS" "0,1" rbitfld.long 0x0 16. "EONUM_DPIP,EONUM_DPIP" "0,1" newline endif sif (cpuis("STM32MP153*")) bitfld.long 0x0 18.--19. "EPTYP,EPTYP" "0,1,2,3" rbitfld.long 0x0 17. "NAKSTS,NAKSTS" "0,1" newline rbitfld.long 0x0 16. "EONUM_DPIP,EONUM_DPIP" "0,1" endif sif (cpuis("STM32MP157*")) bitfld.long 0x0 18.--19. "EPTYP,EPTYP" "0,1,2,3" newline rbitfld.long 0x0 17. "NAKSTS,NAKSTS" "0,1" rbitfld.long 0x0 16. "EONUM_DPIP,EONUM_DPIP" "0,1" newline endif bitfld.long 0x0 15. "USBAEP,USB active endpoint" "0,1" hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" group.long 0xBC8++0x3 line.long 0x0 "OTG_DOEPINT6,OTG device OUT endpoint 6 interrupt register" bitfld.long 0x0 15. "STPKTRX,Setup packet received" "0,1" bitfld.long 0x0 14. "NYET,NYET interrupt" "0,1" newline bitfld.long 0x0 13. "NAK,NAK input" "0,1" bitfld.long 0x0 12. "BERR,Babble error interrupt" "0,1" newline bitfld.long 0x0 9. "BNA,Buffer not available interrupt" "0,1" bitfld.long 0x0 8. "OUTPKTERR,OUT packet error" "0,1" newline bitfld.long 0x0 6. "B2BSTUP,Back-to-back SETUP packets received" "0,1" bitfld.long 0x0 5. "STSPHSRX,Status phase received for control write" "0,1" newline bitfld.long 0x0 4. "OTEPDIS,OUT token received when endpoint disabled" "0,1" bitfld.long 0x0 3. "STUP,SETUP phase done" "0,1" newline bitfld.long 0x0 2. "AHBERR,AHB error" "0,1" bitfld.long 0x0 1. "EPDISD,Endpoint disabled interrupt" "0,1" newline bitfld.long 0x0 0. "XFRC,Transfer completed interrupt" "0,1" group.long 0xBD0++0x7 line.long 0x0 "OTG_DOEPTSIZ6,OTG device OUT endpoint 6 transfer size register" sif (cpuis("STM32MP13*")) bitfld.long 0x0 29.--30. "RXDPID,Received data PID" "0: DATA0,1: DATA2,2: DATA1,3: MDATA" endif sif (cpuis("STM32MP151*")) bitfld.long 0x0 29.--30. "RXDPID_STUPCNT,RXDPID_STUPCNT" "0,1,2,3" newline endif sif (cpuis("STM32MP153*")) bitfld.long 0x0 29.--30. "RXDPID_STUPCNT,RXDPID_STUPCNT" "0,1,2,3" endif sif (cpuis("STM32MP157*")) bitfld.long 0x0 29.--30. "RXDPID_STUPCNT,RXDPID_STUPCNT" "0,1,2,3" newline endif hexmask.long.word 0x0 19.--28. 1. "PKTCNT,Packet count" hexmask.long.tbyte 0x0 0.--18. 1. "XFRSIZ,Transfer size" line.long 0x4 "OTG_DOEPDMA6," hexmask.long 0x4 0.--31. 1. "DMAADDR,DMA Address" group.long 0xBE0++0x3 line.long 0x0 "OTG_DOEPCTL7,OTG device OUT endpoint 7 control register" bitfld.long 0x0 31. "EPENA,Endpoint enable" "0,1" bitfld.long 0x0 30. "EPDIS,Endpoint disable" "0,1" newline sif (cpuis("STM32MP13*")) bitfld.long 0x0 29. "SD1PID,Set DATA1 PID" "0,1" bitfld.long 0x0 28. "SD0PID,Set DATA0 PID" "0,1" newline bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt" rbitfld.long 0x0 17. "NAKSTS,NAK status" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.." newline rbitfld.long 0x0 16. "DPID,Endpoint data PID" "0: DATA0,1: DATA1" endif sif (cpuis("STM32MP151*")) bitfld.long 0x0 29. "SD1PID_SODDFRM,SD1PID_SODDFRM" "0,1" newline bitfld.long 0x0 28. "SD0PID_SEVNFRM,SD0PID_SEVNFRM" "0,1" endif sif (cpuis("STM32MP153*")) bitfld.long 0x0 29. "SD1PID_SODDFRM,SD1PID_SODDFRM" "0,1" newline bitfld.long 0x0 28. "SD0PID_SEVNFRM,SD0PID_SEVNFRM" "0,1" endif sif (cpuis("STM32MP157*")) bitfld.long 0x0 29. "SD1PID_SODDFRM,SD1PID_SODDFRM" "0,1" newline bitfld.long 0x0 28. "SD0PID_SEVNFRM,SD0PID_SEVNFRM" "0,1" endif bitfld.long 0x0 27. "SNAK,Set NAK" "0,1" newline bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1" bitfld.long 0x0 21. "STALL,STALL handshake" "0,1" newline bitfld.long 0x0 20. "SNPM,Snoop mode" "0,1" sif (cpuis("STM32MP151*")) bitfld.long 0x0 18.--19. "EPTYP,EPTYP" "0,1,2,3" newline rbitfld.long 0x0 17. "NAKSTS,NAKSTS" "0,1" rbitfld.long 0x0 16. "EONUM_DPIP,EONUM_DPIP" "0,1" newline endif sif (cpuis("STM32MP153*")) bitfld.long 0x0 18.--19. "EPTYP,EPTYP" "0,1,2,3" rbitfld.long 0x0 17. "NAKSTS,NAKSTS" "0,1" newline rbitfld.long 0x0 16. "EONUM_DPIP,EONUM_DPIP" "0,1" endif sif (cpuis("STM32MP157*")) bitfld.long 0x0 18.--19. "EPTYP,EPTYP" "0,1,2,3" newline rbitfld.long 0x0 17. "NAKSTS,NAKSTS" "0,1" rbitfld.long 0x0 16. "EONUM_DPIP,EONUM_DPIP" "0,1" newline endif bitfld.long 0x0 15. "USBAEP,USB active endpoint" "0,1" hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" group.long 0xBE8++0x3 line.long 0x0 "OTG_DOEPINT7,OTG device OUT endpoint 7 interrupt register" bitfld.long 0x0 15. "STPKTRX,Setup packet received" "0,1" bitfld.long 0x0 14. "NYET,NYET interrupt" "0,1" newline bitfld.long 0x0 13. "NAK,NAK input" "0,1" bitfld.long 0x0 12. "BERR,Babble error interrupt" "0,1" newline bitfld.long 0x0 9. "BNA,Buffer not available interrupt" "0,1" bitfld.long 0x0 8. "OUTPKTERR,OUT packet error" "0,1" newline bitfld.long 0x0 6. "B2BSTUP,Back-to-back SETUP packets received" "0,1" bitfld.long 0x0 5. "STSPHSRX,Status phase received for control write" "0,1" newline bitfld.long 0x0 4. "OTEPDIS,OUT token received when endpoint disabled" "0,1" bitfld.long 0x0 3. "STUP,SETUP phase done" "0,1" newline bitfld.long 0x0 2. "AHBERR,AHB error" "0,1" bitfld.long 0x0 1. "EPDISD,Endpoint disabled interrupt" "0,1" newline bitfld.long 0x0 0. "XFRC,Transfer completed interrupt" "0,1" group.long 0xBF0++0x7 line.long 0x0 "OTG_DOEPTSIZ7,OTG device OUT endpoint 7 transfer size register" sif (cpuis("STM32MP13*")) bitfld.long 0x0 29.--30. "RXDPID,Received data PID" "0: DATA0,1: DATA2,2: DATA1,3: MDATA" endif sif (cpuis("STM32MP151*")) bitfld.long 0x0 29.--30. "RXDPID_STUPCNT,RXDPID_STUPCNT" "0,1,2,3" newline endif sif (cpuis("STM32MP153*")) bitfld.long 0x0 29.--30. "RXDPID_STUPCNT,RXDPID_STUPCNT" "0,1,2,3" endif sif (cpuis("STM32MP157*")) bitfld.long 0x0 29.--30. "RXDPID_STUPCNT,RXDPID_STUPCNT" "0,1,2,3" newline endif hexmask.long.word 0x0 19.--28. 1. "PKTCNT,Packet count" hexmask.long.tbyte 0x0 0.--18. 1. "XFRSIZ,Transfer size" line.long 0x4 "OTG_DOEPDMA7," hexmask.long 0x4 0.--31. 1. "DMAADDR,DMA Address" group.long 0xC00++0x3 line.long 0x0 "OTG_DOEPCTL8,OTG device OUT endpoint 8 control register" bitfld.long 0x0 31. "EPENA,Endpoint enable" "0,1" bitfld.long 0x0 30. "EPDIS,Endpoint disable" "0,1" newline sif (cpuis("STM32MP13*")) bitfld.long 0x0 29. "SD1PID,Set DATA1 PID" "0,1" bitfld.long 0x0 28. "SD0PID,Set DATA0 PID" "0,1" newline bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt" rbitfld.long 0x0 17. "NAKSTS,NAK status" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.." newline rbitfld.long 0x0 16. "DPID,Endpoint data PID" "0: DATA0,1: DATA1" endif sif (cpuis("STM32MP151*")) bitfld.long 0x0 29. "SD1PID_SODDFRM,SD1PID_SODDFRM" "0,1" newline bitfld.long 0x0 28. "SD0PID_SEVNFRM,SD0PID_SEVNFRM" "0,1" endif sif (cpuis("STM32MP153*")) bitfld.long 0x0 29. "SD1PID_SODDFRM,SD1PID_SODDFRM" "0,1" newline bitfld.long 0x0 28. "SD0PID_SEVNFRM,SD0PID_SEVNFRM" "0,1" endif sif (cpuis("STM32MP157*")) bitfld.long 0x0 29. "SD1PID_SODDFRM,SD1PID_SODDFRM" "0,1" newline bitfld.long 0x0 28. "SD0PID_SEVNFRM,SD0PID_SEVNFRM" "0,1" endif bitfld.long 0x0 27. "SNAK,Set NAK" "0,1" newline bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1" bitfld.long 0x0 21. "STALL,STALL handshake" "0,1" newline bitfld.long 0x0 20. "SNPM,Snoop mode" "0,1" sif (cpuis("STM32MP151*")) bitfld.long 0x0 18.--19. "EPTYP,EPTYP" "0,1,2,3" newline rbitfld.long 0x0 17. "NAKSTS,NAKSTS" "0,1" rbitfld.long 0x0 16. "EONUM_DPIP,EONUM_DPIP" "0,1" newline endif sif (cpuis("STM32MP153*")) bitfld.long 0x0 18.--19. "EPTYP,EPTYP" "0,1,2,3" rbitfld.long 0x0 17. "NAKSTS,NAKSTS" "0,1" newline rbitfld.long 0x0 16. "EONUM_DPIP,EONUM_DPIP" "0,1" endif sif (cpuis("STM32MP157*")) bitfld.long 0x0 18.--19. "EPTYP,EPTYP" "0,1,2,3" newline rbitfld.long 0x0 17. "NAKSTS,NAKSTS" "0,1" rbitfld.long 0x0 16. "EONUM_DPIP,EONUM_DPIP" "0,1" newline endif bitfld.long 0x0 15. "USBAEP,USB active endpoint" "0,1" hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" group.long 0xC08++0x3 line.long 0x0 "OTG_DOEPINT8,OTG device OUT endpoint 8 interrupt register" bitfld.long 0x0 15. "STPKTRX,Setup packet received" "0,1" bitfld.long 0x0 14. "NYET,NYET interrupt" "0,1" newline bitfld.long 0x0 13. "NAK,NAK input" "0,1" bitfld.long 0x0 12. "BERR,Babble error interrupt" "0,1" newline bitfld.long 0x0 9. "BNA,Buffer not available interrupt" "0,1" bitfld.long 0x0 8. "OUTPKTERR,OUT packet error" "0,1" newline bitfld.long 0x0 6. "B2BSTUP,Back-to-back SETUP packets received" "0,1" bitfld.long 0x0 5. "STSPHSRX,Status phase received for control write" "0,1" newline bitfld.long 0x0 4. "OTEPDIS,OUT token received when endpoint disabled" "0,1" bitfld.long 0x0 3. "STUP,SETUP phase done" "0,1" newline bitfld.long 0x0 2. "AHBERR,AHB error" "0,1" bitfld.long 0x0 1. "EPDISD,Endpoint disabled interrupt" "0,1" newline bitfld.long 0x0 0. "XFRC,Transfer completed interrupt" "0,1" group.long 0xC10++0x7 line.long 0x0 "OTG_DOEPTSIZ8,OTG device OUT endpoint 8 transfer size register" sif (cpuis("STM32MP13*")) bitfld.long 0x0 29.--30. "RXDPID,Received data PID" "0: DATA0,1: DATA2,2: DATA1,3: MDATA" endif sif (cpuis("STM32MP151*")) bitfld.long 0x0 29.--30. "RXDPID_STUPCNT,RXDPID_STUPCNT" "0,1,2,3" newline endif sif (cpuis("STM32MP153*")) bitfld.long 0x0 29.--30. "RXDPID_STUPCNT,RXDPID_STUPCNT" "0,1,2,3" endif sif (cpuis("STM32MP157*")) bitfld.long 0x0 29.--30. "RXDPID_STUPCNT,RXDPID_STUPCNT" "0,1,2,3" newline endif hexmask.long.word 0x0 19.--28. 1. "PKTCNT,Packet count" hexmask.long.tbyte 0x0 0.--18. 1. "XFRSIZ,Transfer size" line.long 0x4 "OTG_DOEPDMA8," hexmask.long 0x4 0.--31. 1. "DMAADDR,DMA Address" group.long 0xE00++0x3 line.long 0x0 "OTG_PCGCCTL,OTG power and clock gating control register" rbitfld.long 0x0 7. "SUSP,Deep Sleep" "0,1" rbitfld.long 0x0 6. "PHYSLEEP,PHY in Sleep" "0,1" newline bitfld.long 0x0 5. "ENL1GTG,Enable sleep clock gating" "0,1" rbitfld.long 0x0 4. "PHYSUSP,PHY suspended" "0,1" newline bitfld.long 0x0 1. "GATEHCLK,Gate HCLK" "0,1" bitfld.long 0x0 0. "STPPCLK,Stop PHY clock" "0,1" sif (cpuis("STM32MP151*")) rgroup.long 0x1C++0x3 line.long 0x0 "OTG_GRXSTSR,This description is for register OTG_GRXSTSR in Device mode. A read to the receive status debug read register returns the contents of the top of the receive FIFO. The core ignores the receive status read when the receive FIFO is empty and.." endif sif (cpuis("STM32MP151*")) rgroup.long 0x20++0x3 line.long 0x0 "OTG_GRXSTSP,This description is for register OTG_GRXSTSP in Device mode. Similarly to OTG_GRXSTSR (receive status debug read register) where a read returns the contents of the top of the receive FIFO. a read to OTG_GRXSTSP (receive status read and pop.." endif sif (cpuis("STM32MP151*")) rgroup.long 0x2C++0x3 line.long 0x0 "OTG_HNPTXSTS,In device mode. this register is not valid. This read-only register contains the free space information for the non-periodic Tx FIFO and the non-periodic transmit request queue." endif sif (cpuis("STM32MP151*")) rgroup.long 0x408++0x3 line.long 0x0 "OTG_HFNUM,This register indicates the current frame number. It also indicates the time remaining (in terms of the number of PHY clocks) in the current frame." endif sif (cpuis("STM32MP151*")) rgroup.long 0x410++0x3 line.long 0x0 "OTG_HPTXSTS,This read-only register contains the free space information for the periodic Tx FIFO and the periodic transmit request queue." endif sif (cpuis("STM32MP151*")) rgroup.long 0x414++0x3 line.long 0x0 "OTG_HAINT,When a significant event occurs on a channel. the host all channels interrupt register interrupts the application using the host channels interrupt bit of the core interrupt register (HCINT bit in OTG_GINTSTS). This is shown in Figure724. There.." endif sif (cpuis("STM32MP151*")) rgroup.long 0x51C++0x3 line.long 0x0 "OTG_HCDMAB0,OTG host channel-n DMA address buffer register" endif sif (cpuis("STM32MP151*")) rgroup.long 0x53C++0x3 line.long 0x0 "OTG_HCDMAB1,OTG host channel-n DMA address buffer register" endif sif (cpuis("STM32MP151*")) rgroup.long 0x55C++0x3 line.long 0x0 "OTG_HCDMAB2,OTG host channel-n DMA address buffer register" endif sif (cpuis("STM32MP151*")) rgroup.long 0x57C++0x3 line.long 0x0 "OTG_HCDMAB3,OTG host channel-n DMA address buffer register" endif sif (cpuis("STM32MP151*")) rgroup.long 0x59C++0x3 line.long 0x0 "OTG_HCDMAB4,OTG host channel-n DMA address buffer register" endif sif (cpuis("STM32MP151*")) rgroup.long 0x5BC++0x3 line.long 0x0 "OTG_HCDMAB5,OTG host channel-n DMA address buffer register" endif sif (cpuis("STM32MP151*")) rgroup.long 0x5DC++0x3 line.long 0x0 "OTG_HCDMAB6,OTG host channel-n DMA address buffer register" endif sif (cpuis("STM32MP151*")) rgroup.long 0x5FC++0x3 line.long 0x0 "OTG_HCDMAB7,OTG host channel-n DMA address buffer register" endif sif (cpuis("STM32MP151*")) rgroup.long 0x61C++0x3 line.long 0x0 "OTG_HCDMAB8,OTG host channel-n DMA address buffer register" endif sif (cpuis("STM32MP151*")) rgroup.long 0x63C++0x3 line.long 0x0 "OTG_HCDMAB9,OTG host channel-n DMA address buffer register" endif sif (cpuis("STM32MP151*")) rgroup.long 0x65C++0x3 line.long 0x0 "OTG_HCDMAB10,OTG host channel-n DMA address buffer register" endif sif (cpuis("STM32MP151*")) rgroup.long 0x67C++0x3 line.long 0x0 "OTG_HCDMAB11,OTG host channel-n DMA address buffer register" endif sif (cpuis("STM32MP151*")) rgroup.long 0x69C++0x3 line.long 0x0 "OTG_HCDMAB12,OTG host channel-n DMA address buffer register" endif sif (cpuis("STM32MP151*")) rgroup.long 0x6BC++0x3 line.long 0x0 "OTG_HCDMAB13,OTG host channel-n DMA address buffer register" endif sif (cpuis("STM32MP151*")) rgroup.long 0x6DC++0x3 line.long 0x0 "OTG_HCDMAB14,OTG host channel-n DMA address buffer register" endif sif (cpuis("STM32MP151*")) rgroup.long 0x6FC++0x3 line.long 0x0 "OTG_HCDMAB15,OTG host channel-n DMA address buffer register" endif sif (cpuis("STM32MP151*")) rgroup.long 0x808++0x3 line.long 0x0 "OTG_DSTS,This register indicates the status of the core with respect to USB-related events. It must be read on interrupts from the device all interrupts (OTG_DAINT) register." endif sif (cpuis("STM32MP151*")) rgroup.long 0x818++0x3 line.long 0x0 "OTG_DAINT,When a significant event occurs on an endpoint. a OTG_DAINT register interrupts the application using the device OUT endpoints interrupt bit or device IN endpoints interrupt bit of the OTG_GINTSTS register (OEPINT or IEPINT in OTG_GINTSTS..." rgroup.long 0x838++0x3 line.long 0x0 "OTG_DEACHINT,OTG device each endpoint interrupt register" bitfld.long 0x0 17. "OEP1INT,OEP1INT" "0,1" bitfld.long 0x0 1. "IEP1INT,IEP1INT" "0,1" group.long 0x83C++0x3 line.long 0x0 "OTG_DEACHINTMSK,There is one interrupt bit for endpoint 1 IN and one interrupt bit for endpoint 1 OUT." bitfld.long 0x0 17. "OEP1INTM,OEP1INTM" "0,1" bitfld.long 0x0 1. "IEP1INTM,IEP1INTM" "0,1" group.long 0x844++0x3 line.long 0x0 "OTG_HS_DIEPEACHMSK1,This register works with the OTG_DIEPINT1 register to generate a dedicated interrupt OTG_HS_EP1_IN for endpoint #1. The IN endpoint interrupt for a specific status in the OTG_DOEPINT1 register can be masked by writing into the.." bitfld.long 0x0 13. "NAKM,NAKM" "0,1" bitfld.long 0x0 9. "BNAM,BNAM" "0,1" newline bitfld.long 0x0 8. "TXFURM,TXFURM" "0,1" bitfld.long 0x0 6. "INEPNEM,INEPNEM" "0,1" newline bitfld.long 0x0 4. "ITTXFEMSK,ITTXFEMSK" "0,1" bitfld.long 0x0 3. "TOM,TOM" "0,1" newline bitfld.long 0x0 2. "AHBERRM,AHBERRM" "0,1" bitfld.long 0x0 1. "EPDM,EPDM" "0,1" newline bitfld.long 0x0 0. "XFRCM,XFRCM" "0,1" group.long 0x884++0x3 line.long 0x0 "OTG_HS_DOEPEACHMSK1,This register works with the OTG_DOEPINT1 register to generate a dedicated interrupt OTG_HS_EP1_OUT for endpoint #1. The OUT endpoint interrupt for a specific status in the OTG_DOEPINT1 register can be masked by writing into the.." bitfld.long 0x0 14. "NYETMSK,NYETMSK" "0,1" bitfld.long 0x0 13. "NAKMSK,NAKMSK" "0,1" newline bitfld.long 0x0 12. "BERRM,BERRM" "0,1" bitfld.long 0x0 9. "BNAM,BNAM" "0,1" newline bitfld.long 0x0 8. "OUTPKTERRM,OUTPKTERRM" "0,1" bitfld.long 0x0 6. "B2BSTUPM,B2BSTUPM" "0,1" newline bitfld.long 0x0 4. "OTEPDM,OTEPDM" "0,1" bitfld.long 0x0 3. "STUPM,STUPM" "0,1" newline bitfld.long 0x0 2. "AHBERRM,AHBERRM" "0,1" bitfld.long 0x0 1. "EPDM,EPDM" "0,1" newline bitfld.long 0x0 0. "XFRCM,XFRCM" "0,1" endif sif (cpuis("STM32MP151*")) rgroup.long 0x918++0x3 line.long 0x0 "OTG_DTXFSTS0,This read-only register contains the free space information for the device IN endpoint Tx FIFO." endif sif (cpuis("STM32MP151*")) rgroup.long 0x938++0x3 line.long 0x0 "OTG_DTXFSTS1,This read-only register contains the free space information for the device IN endpoint Tx FIFO." endif sif (cpuis("STM32MP151*")) rgroup.long 0x958++0x3 line.long 0x0 "OTG_DTXFSTS2,This read-only register contains the free space information for the device IN endpoint Tx FIFO." endif sif (cpuis("STM32MP151*")) rgroup.long 0x978++0x3 line.long 0x0 "OTG_DTXFSTS3,This read-only register contains the free space information for the device IN endpoint Tx FIFO." endif sif (cpuis("STM32MP151*")) rgroup.long 0x998++0x3 line.long 0x0 "OTG_DTXFSTS4,This read-only register contains the free space information for the device IN endpoint Tx FIFO." endif sif (cpuis("STM32MP151*")) rgroup.long 0x9B8++0x3 line.long 0x0 "OTG_DTXFSTS5,This read-only register contains the free space information for the device IN endpoint Tx FIFO." endif sif (cpuis("STM32MP151*")) rgroup.long 0x9D8++0x3 line.long 0x0 "OTG_DTXFSTS6,This read-only register contains the free space information for the device IN endpoint Tx FIFO." endif sif (cpuis("STM32MP151*")) rgroup.long 0x9F8++0x3 line.long 0x0 "OTG_DTXFSTS7,This read-only register contains the free space information for the device IN endpoint Tx FIFO." endif sif (cpuis("STM32MP151*")) rgroup.long 0xA18++0x3 line.long 0x0 "OTG_DTXFSTS8,This read-only register contains the free space information for the device IN endpoint Tx FIFO." endif sif (cpuis("STM32MP153*")) rgroup.long 0x1C++0x3 line.long 0x0 "OTG_GRXSTSR,This description is for register OTG_GRXSTSR in Device mode. A read to the receive status debug read register returns the contents of the top of the receive FIFO. The core ignores the receive status read when the receive FIFO is empty and.." endif sif (cpuis("STM32MP153*")) rgroup.long 0x20++0x3 line.long 0x0 "OTG_GRXSTSP,This description is for register OTG_GRXSTSP in Device mode. Similarly to OTG_GRXSTSR (receive status debug read register) where a read returns the contents of the top of the receive FIFO. a read to OTG_GRXSTSP (receive status read and pop.." endif sif (cpuis("STM32MP153*")) rgroup.long 0x2C++0x3 line.long 0x0 "OTG_HNPTXSTS,In device mode. this register is not valid. This read-only register contains the free space information for the non-periodic Tx FIFO and the non-periodic transmit request queue." endif sif (cpuis("STM32MP153*")) rgroup.long 0x408++0x3 line.long 0x0 "OTG_HFNUM,This register indicates the current frame number. It also indicates the time remaining (in terms of the number of PHY clocks) in the current frame." endif sif (cpuis("STM32MP153*")) rgroup.long 0x410++0x3 line.long 0x0 "OTG_HPTXSTS,This read-only register contains the free space information for the periodic Tx FIFO and the periodic transmit request queue." endif sif (cpuis("STM32MP153*")) rgroup.long 0x414++0x3 line.long 0x0 "OTG_HAINT,When a significant event occurs on a channel. the host all channels interrupt register interrupts the application using the host channels interrupt bit of the core interrupt register (HCINT bit in OTG_GINTSTS). This is shown in Figure724. There.." endif sif (cpuis("STM32MP153*")) rgroup.long 0x51C++0x3 line.long 0x0 "OTG_HCDMAB0,OTG host channel-n DMA address buffer register" endif sif (cpuis("STM32MP153*")) rgroup.long 0x53C++0x3 line.long 0x0 "OTG_HCDMAB1,OTG host channel-n DMA address buffer register" endif sif (cpuis("STM32MP153*")) rgroup.long 0x55C++0x3 line.long 0x0 "OTG_HCDMAB2,OTG host channel-n DMA address buffer register" endif sif (cpuis("STM32MP153*")) rgroup.long 0x57C++0x3 line.long 0x0 "OTG_HCDMAB3,OTG host channel-n DMA address buffer register" endif sif (cpuis("STM32MP153*")) rgroup.long 0x59C++0x3 line.long 0x0 "OTG_HCDMAB4,OTG host channel-n DMA address buffer register" endif sif (cpuis("STM32MP153*")) rgroup.long 0x5BC++0x3 line.long 0x0 "OTG_HCDMAB5,OTG host channel-n DMA address buffer register" endif sif (cpuis("STM32MP153*")) rgroup.long 0x5DC++0x3 line.long 0x0 "OTG_HCDMAB6,OTG host channel-n DMA address buffer register" endif sif (cpuis("STM32MP153*")) rgroup.long 0x5FC++0x3 line.long 0x0 "OTG_HCDMAB7,OTG host channel-n DMA address buffer register" endif sif (cpuis("STM32MP153*")) rgroup.long 0x61C++0x3 line.long 0x0 "OTG_HCDMAB8,OTG host channel-n DMA address buffer register" endif sif (cpuis("STM32MP153*")) rgroup.long 0x63C++0x3 line.long 0x0 "OTG_HCDMAB9,OTG host channel-n DMA address buffer register" endif sif (cpuis("STM32MP153*")) rgroup.long 0x65C++0x3 line.long 0x0 "OTG_HCDMAB10,OTG host channel-n DMA address buffer register" endif sif (cpuis("STM32MP153*")) rgroup.long 0x67C++0x3 line.long 0x0 "OTG_HCDMAB11,OTG host channel-n DMA address buffer register" endif sif (cpuis("STM32MP153*")) rgroup.long 0x69C++0x3 line.long 0x0 "OTG_HCDMAB12,OTG host channel-n DMA address buffer register" endif sif (cpuis("STM32MP153*")) rgroup.long 0x6BC++0x3 line.long 0x0 "OTG_HCDMAB13,OTG host channel-n DMA address buffer register" endif sif (cpuis("STM32MP153*")) rgroup.long 0x6DC++0x3 line.long 0x0 "OTG_HCDMAB14,OTG host channel-n DMA address buffer register" endif sif (cpuis("STM32MP153*")) rgroup.long 0x6FC++0x3 line.long 0x0 "OTG_HCDMAB15,OTG host channel-n DMA address buffer register" endif sif (cpuis("STM32MP153*")) rgroup.long 0x808++0x3 line.long 0x0 "OTG_DSTS,This register indicates the status of the core with respect to USB-related events. It must be read on interrupts from the device all interrupts (OTG_DAINT) register." endif sif (cpuis("STM32MP153*")) rgroup.long 0x818++0x3 line.long 0x0 "OTG_DAINT,When a significant event occurs on an endpoint. a OTG_DAINT register interrupts the application using the device OUT endpoints interrupt bit or device IN endpoints interrupt bit of the OTG_GINTSTS register (OEPINT or IEPINT in OTG_GINTSTS..." rgroup.long 0x838++0x3 line.long 0x0 "OTG_DEACHINT,OTG device each endpoint interrupt register" bitfld.long 0x0 17. "OEP1INT,OEP1INT" "0,1" bitfld.long 0x0 1. "IEP1INT,IEP1INT" "0,1" group.long 0x83C++0x3 line.long 0x0 "OTG_DEACHINTMSK,There is one interrupt bit for endpoint 1 IN and one interrupt bit for endpoint 1 OUT." bitfld.long 0x0 17. "OEP1INTM,OEP1INTM" "0,1" bitfld.long 0x0 1. "IEP1INTM,IEP1INTM" "0,1" group.long 0x844++0x3 line.long 0x0 "OTG_HS_DIEPEACHMSK1,This register works with the OTG_DIEPINT1 register to generate a dedicated interrupt OTG_HS_EP1_IN for endpoint #1. The IN endpoint interrupt for a specific status in the OTG_DOEPINT1 register can be masked by writing into the.." bitfld.long 0x0 13. "NAKM,NAKM" "0,1" bitfld.long 0x0 9. "BNAM,BNAM" "0,1" newline bitfld.long 0x0 8. "TXFURM,TXFURM" "0,1" bitfld.long 0x0 6. "INEPNEM,INEPNEM" "0,1" newline bitfld.long 0x0 4. "ITTXFEMSK,ITTXFEMSK" "0,1" bitfld.long 0x0 3. "TOM,TOM" "0,1" newline bitfld.long 0x0 2. "AHBERRM,AHBERRM" "0,1" bitfld.long 0x0 1. "EPDM,EPDM" "0,1" newline bitfld.long 0x0 0. "XFRCM,XFRCM" "0,1" group.long 0x884++0x3 line.long 0x0 "OTG_HS_DOEPEACHMSK1,This register works with the OTG_DOEPINT1 register to generate a dedicated interrupt OTG_HS_EP1_OUT for endpoint #1. The OUT endpoint interrupt for a specific status in the OTG_DOEPINT1 register can be masked by writing into the.." bitfld.long 0x0 14. "NYETMSK,NYETMSK" "0,1" bitfld.long 0x0 13. "NAKMSK,NAKMSK" "0,1" newline bitfld.long 0x0 12. "BERRM,BERRM" "0,1" bitfld.long 0x0 9. "BNAM,BNAM" "0,1" newline bitfld.long 0x0 8. "OUTPKTERRM,OUTPKTERRM" "0,1" bitfld.long 0x0 6. "B2BSTUPM,B2BSTUPM" "0,1" newline bitfld.long 0x0 4. "OTEPDM,OTEPDM" "0,1" bitfld.long 0x0 3. "STUPM,STUPM" "0,1" newline bitfld.long 0x0 2. "AHBERRM,AHBERRM" "0,1" bitfld.long 0x0 1. "EPDM,EPDM" "0,1" newline bitfld.long 0x0 0. "XFRCM,XFRCM" "0,1" endif sif (cpuis("STM32MP153*")) rgroup.long 0x918++0x3 line.long 0x0 "OTG_DTXFSTS0,This read-only register contains the free space information for the device IN endpoint Tx FIFO." endif sif (cpuis("STM32MP153*")) rgroup.long 0x938++0x3 line.long 0x0 "OTG_DTXFSTS1,This read-only register contains the free space information for the device IN endpoint Tx FIFO." endif sif (cpuis("STM32MP153*")) rgroup.long 0x958++0x3 line.long 0x0 "OTG_DTXFSTS2,This read-only register contains the free space information for the device IN endpoint Tx FIFO." endif sif (cpuis("STM32MP153*")) rgroup.long 0x978++0x3 line.long 0x0 "OTG_DTXFSTS3,This read-only register contains the free space information for the device IN endpoint Tx FIFO." endif sif (cpuis("STM32MP153*")) rgroup.long 0x998++0x3 line.long 0x0 "OTG_DTXFSTS4,This read-only register contains the free space information for the device IN endpoint Tx FIFO." endif sif (cpuis("STM32MP153*")) rgroup.long 0x9B8++0x3 line.long 0x0 "OTG_DTXFSTS5,This read-only register contains the free space information for the device IN endpoint Tx FIFO." endif sif (cpuis("STM32MP153*")) rgroup.long 0x9D8++0x3 line.long 0x0 "OTG_DTXFSTS6,This read-only register contains the free space information for the device IN endpoint Tx FIFO." endif sif (cpuis("STM32MP153*")) rgroup.long 0x9F8++0x3 line.long 0x0 "OTG_DTXFSTS7,This read-only register contains the free space information for the device IN endpoint Tx FIFO." endif sif (cpuis("STM32MP153*")) rgroup.long 0xA18++0x3 line.long 0x0 "OTG_DTXFSTS8,This read-only register contains the free space information for the device IN endpoint Tx FIFO." endif sif (cpuis("STM32MP157*")) rgroup.long 0x1C++0x3 line.long 0x0 "OTG_GRXSTSR,This description is for register OTG_GRXSTSR in Device mode. A read to the receive status debug read register returns the contents of the top of the receive FIFO. The core ignores the receive status read when the receive FIFO is empty and.." endif sif (cpuis("STM32MP157*")) rgroup.long 0x20++0x3 line.long 0x0 "OTG_GRXSTSP,This description is for register OTG_GRXSTSP in Device mode. Similarly to OTG_GRXSTSR (receive status debug read register) where a read returns the contents of the top of the receive FIFO. a read to OTG_GRXSTSP (receive status read and pop.." endif sif (cpuis("STM32MP157*")) rgroup.long 0x2C++0x3 line.long 0x0 "OTG_HNPTXSTS,In device mode. this register is not valid. This read-only register contains the free space information for the non-periodic Tx FIFO and the non-periodic transmit request queue." endif sif (cpuis("STM32MP157*")) rgroup.long 0x408++0x3 line.long 0x0 "OTG_HFNUM,This register indicates the current frame number. It also indicates the time remaining (in terms of the number of PHY clocks) in the current frame." endif sif (cpuis("STM32MP157*")) rgroup.long 0x410++0x3 line.long 0x0 "OTG_HPTXSTS,This read-only register contains the free space information for the periodic Tx FIFO and the periodic transmit request queue." endif sif (cpuis("STM32MP157*")) rgroup.long 0x414++0x3 line.long 0x0 "OTG_HAINT,When a significant event occurs on a channel. the host all channels interrupt register interrupts the application using the host channels interrupt bit of the core interrupt register (HCINT bit in OTG_GINTSTS). This is shown in Figure724. There.." endif sif (cpuis("STM32MP157*")) rgroup.long 0x51C++0x3 line.long 0x0 "OTG_HCDMAB0,OTG host channel-n DMA address buffer register" endif sif (cpuis("STM32MP157*")) rgroup.long 0x53C++0x3 line.long 0x0 "OTG_HCDMAB1,OTG host channel-n DMA address buffer register" endif sif (cpuis("STM32MP157*")) rgroup.long 0x55C++0x3 line.long 0x0 "OTG_HCDMAB2,OTG host channel-n DMA address buffer register" endif sif (cpuis("STM32MP157*")) rgroup.long 0x57C++0x3 line.long 0x0 "OTG_HCDMAB3,OTG host channel-n DMA address buffer register" endif sif (cpuis("STM32MP157*")) rgroup.long 0x59C++0x3 line.long 0x0 "OTG_HCDMAB4,OTG host channel-n DMA address buffer register" endif sif (cpuis("STM32MP157*")) rgroup.long 0x5BC++0x3 line.long 0x0 "OTG_HCDMAB5,OTG host channel-n DMA address buffer register" endif sif (cpuis("STM32MP157*")) rgroup.long 0x5DC++0x3 line.long 0x0 "OTG_HCDMAB6,OTG host channel-n DMA address buffer register" endif sif (cpuis("STM32MP157*")) rgroup.long 0x5FC++0x3 line.long 0x0 "OTG_HCDMAB7,OTG host channel-n DMA address buffer register" endif sif (cpuis("STM32MP157*")) rgroup.long 0x61C++0x3 line.long 0x0 "OTG_HCDMAB8,OTG host channel-n DMA address buffer register" endif sif (cpuis("STM32MP157*")) rgroup.long 0x63C++0x3 line.long 0x0 "OTG_HCDMAB9,OTG host channel-n DMA address buffer register" endif sif (cpuis("STM32MP157*")) rgroup.long 0x65C++0x3 line.long 0x0 "OTG_HCDMAB10,OTG host channel-n DMA address buffer register" endif sif (cpuis("STM32MP157*")) rgroup.long 0x67C++0x3 line.long 0x0 "OTG_HCDMAB11,OTG host channel-n DMA address buffer register" endif sif (cpuis("STM32MP157*")) rgroup.long 0x69C++0x3 line.long 0x0 "OTG_HCDMAB12,OTG host channel-n DMA address buffer register" endif sif (cpuis("STM32MP157*")) rgroup.long 0x6BC++0x3 line.long 0x0 "OTG_HCDMAB13,OTG host channel-n DMA address buffer register" endif sif (cpuis("STM32MP157*")) rgroup.long 0x6DC++0x3 line.long 0x0 "OTG_HCDMAB14,OTG host channel-n DMA address buffer register" endif sif (cpuis("STM32MP157*")) rgroup.long 0x6FC++0x3 line.long 0x0 "OTG_HCDMAB15,OTG host channel-n DMA address buffer register" endif sif (cpuis("STM32MP157*")) rgroup.long 0x808++0x3 line.long 0x0 "OTG_DSTS,This register indicates the status of the core with respect to USB-related events. It must be read on interrupts from the device all interrupts (OTG_DAINT) register." endif sif (cpuis("STM32MP157*")) rgroup.long 0x818++0x3 line.long 0x0 "OTG_DAINT,When a significant event occurs on an endpoint. a OTG_DAINT register interrupts the application using the device OUT endpoints interrupt bit or device IN endpoints interrupt bit of the OTG_GINTSTS register (OEPINT or IEPINT in OTG_GINTSTS..." rgroup.long 0x838++0x3 line.long 0x0 "OTG_DEACHINT,OTG device each endpoint interrupt register" bitfld.long 0x0 17. "OEP1INT,OEP1INT" "0,1" bitfld.long 0x0 1. "IEP1INT,IEP1INT" "0,1" group.long 0x83C++0x3 line.long 0x0 "OTG_DEACHINTMSK,There is one interrupt bit for endpoint 1 IN and one interrupt bit for endpoint 1 OUT." bitfld.long 0x0 17. "OEP1INTM,OEP1INTM" "0,1" bitfld.long 0x0 1. "IEP1INTM,IEP1INTM" "0,1" group.long 0x844++0x3 line.long 0x0 "OTG_HS_DIEPEACHMSK1,This register works with the OTG_DIEPINT1 register to generate a dedicated interrupt OTG_HS_EP1_IN for endpoint #1. The IN endpoint interrupt for a specific status in the OTG_DOEPINT1 register can be masked by writing into the.." bitfld.long 0x0 13. "NAKM,NAKM" "0,1" bitfld.long 0x0 9. "BNAM,BNAM" "0,1" newline bitfld.long 0x0 8. "TXFURM,TXFURM" "0,1" bitfld.long 0x0 6. "INEPNEM,INEPNEM" "0,1" newline bitfld.long 0x0 4. "ITTXFEMSK,ITTXFEMSK" "0,1" bitfld.long 0x0 3. "TOM,TOM" "0,1" newline bitfld.long 0x0 2. "AHBERRM,AHBERRM" "0,1" bitfld.long 0x0 1. "EPDM,EPDM" "0,1" newline bitfld.long 0x0 0. "XFRCM,XFRCM" "0,1" group.long 0x884++0x3 line.long 0x0 "OTG_HS_DOEPEACHMSK1,This register works with the OTG_DOEPINT1 register to generate a dedicated interrupt OTG_HS_EP1_OUT for endpoint #1. The OUT endpoint interrupt for a specific status in the OTG_DOEPINT1 register can be masked by writing into the.." bitfld.long 0x0 14. "NYETMSK,NYETMSK" "0,1" bitfld.long 0x0 13. "NAKMSK,NAKMSK" "0,1" newline bitfld.long 0x0 12. "BERRM,BERRM" "0,1" bitfld.long 0x0 9. "BNAM,BNAM" "0,1" newline bitfld.long 0x0 8. "OUTPKTERRM,OUTPKTERRM" "0,1" bitfld.long 0x0 6. "B2BSTUPM,B2BSTUPM" "0,1" newline bitfld.long 0x0 4. "OTEPDM,OTEPDM" "0,1" bitfld.long 0x0 3. "STUPM,STUPM" "0,1" newline bitfld.long 0x0 2. "AHBERRM,AHBERRM" "0,1" bitfld.long 0x0 1. "EPDM,EPDM" "0,1" newline bitfld.long 0x0 0. "XFRCM,XFRCM" "0,1" endif sif (cpuis("STM32MP157*")) rgroup.long 0x918++0x3 line.long 0x0 "OTG_DTXFSTS0,This read-only register contains the free space information for the device IN endpoint Tx FIFO." endif sif (cpuis("STM32MP157*")) rgroup.long 0x938++0x3 line.long 0x0 "OTG_DTXFSTS1,This read-only register contains the free space information for the device IN endpoint Tx FIFO." endif sif (cpuis("STM32MP157*")) rgroup.long 0x958++0x3 line.long 0x0 "OTG_DTXFSTS2,This read-only register contains the free space information for the device IN endpoint Tx FIFO." endif sif (cpuis("STM32MP157*")) rgroup.long 0x978++0x3 line.long 0x0 "OTG_DTXFSTS3,This read-only register contains the free space information for the device IN endpoint Tx FIFO." endif sif (cpuis("STM32MP157*")) rgroup.long 0x998++0x3 line.long 0x0 "OTG_DTXFSTS4,This read-only register contains the free space information for the device IN endpoint Tx FIFO." endif sif (cpuis("STM32MP157*")) rgroup.long 0x9B8++0x3 line.long 0x0 "OTG_DTXFSTS5,This read-only register contains the free space information for the device IN endpoint Tx FIFO." endif sif (cpuis("STM32MP157*")) rgroup.long 0x9D8++0x3 line.long 0x0 "OTG_DTXFSTS6,This read-only register contains the free space information for the device IN endpoint Tx FIFO." endif sif (cpuis("STM32MP157*")) rgroup.long 0x9F8++0x3 line.long 0x0 "OTG_DTXFSTS7,This read-only register contains the free space information for the device IN endpoint Tx FIFO." endif sif (cpuis("STM32MP157*")) rgroup.long 0xA18++0x3 line.long 0x0 "OTG_DTXFSTS8,This read-only register contains the free space information for the device IN endpoint Tx FIFO." endif tree.end sif (cpuis("STM32MP13*")) tree "PKA (Public Key Accelerator)" base ad:0x54006000 group.long 0x0++0x3 line.long 0x0 "PKA_CR,PKA control register" bitfld.long 0x0 21. "OPERRIE,Operation error interrupt enable" "0: No interrupt is generated when OPERRF flag is..,1: An interrupt is generated when OPERRF flag is.." bitfld.long 0x0 20. "ADDRERRIE,Address error interrupt enable" "0: No interrupt is generated when ADDRERRF flag is..,1: An interrupt is generated when ADDRERRF flag is.." newline bitfld.long 0x0 19. "RAMERRIE,RAM error interrupt enable" "0: No interrupt is generated when RAMERRF flag is..,1: An interrupt is generated when RAMERRF flag is.." bitfld.long 0x0 17. "PROCENDIE,End of operation interrupt enable" "0: No interrupt is generated when PROCENDF flag is..,1: An interrupt is generated when PROCENDF flag is.." newline hexmask.long.byte 0x0 8.--13. 1. "MODE,PKA operation code" bitfld.long 0x0 1. "START,start the operation" "0,1" newline bitfld.long 0x0 0. "EN,PKA enable." "0: Disable PKA,1: Enable PKA.PKA becomes functional when INITOK is.." rgroup.long 0x4++0x3 line.long 0x0 "PKA_SR,PKA status register" bitfld.long 0x0 21. "OPERRF,Operation error flag" "0: No event error,1: An illegal or unknown operation has been.." bitfld.long 0x0 20. "ADDRERRF,Address error flag" "0: No address error,1: Address access is out of range (unmapped address)" newline bitfld.long 0x0 19. "RAMERRF,PKA RAM error flag" "0: No PKA RAM access error,1: An AHB access to the PKA RAM occurred while the.." bitfld.long 0x0 17. "PROCENDF,PKA End of Operation flag" "0: Operation in progress,1: PKA operation is completed. This flag is set.." newline bitfld.long 0x0 16. "BUSY,PKA operation is in progress" "0: No operation is in progress (default),1: An operation is in progress" bitfld.long 0x0 1. "LMF,Limited mode flag" "0: All values documented in MODE bitfield can be..,1: Only ECDSA verification (MODE = 0x26) is.." newline bitfld.long 0x0 0. "INITOK,PKA initialization OK" "0: PKA is not initialized correctly. START bit..,1: PKA is initialized correctly and can be used.." wgroup.long 0x8++0x3 line.long 0x0 "PKA_CLRFR,PKA clear flag register" bitfld.long 0x0 21. "OPERRFC,Clear operation error flag" "0: No action,1: Clear the OPERRF flag in PKA_SR" bitfld.long 0x0 20. "ADDRERRFC,Clear address error flag" "0: No action,1: Clear the ADDRERRF flag in PKA_SR" newline bitfld.long 0x0 19. "RAMERRFC,Clear PKA RAM error flag" "0: No action,1: Clear the RAMERRF flag in PKA_SR" bitfld.long 0x0 17. "PROCENDFC,Clear PKA End of Operation flag" "0: No action,1: Clear the PROCENDF flag in PKA_SR" rgroup.long 0x1FF0++0xF line.long 0x0 "PKA_HWCFGR,PKA hardware configuration register" hexmask.long.byte 0x0 4.--7. 1. "CFG2,HW Generic 2" hexmask.long.byte 0x0 0.--3. 1. "CFG1,HW Generic 2" line.long 0x4 "PKA_VERR,PKA version register" hexmask.long.byte 0x4 4.--7. 1. "MAJREV,Major revision" hexmask.long.byte 0x4 0.--3. 1. "MINREV,Minor revision" line.long 0x8 "PKA_IPIDR,PKA identification register" hexmask.long 0x8 0.--31. 1. "ID,Identification Code" line.long 0xC "PKA_SIDR,PKA size ID register" hexmask.long 0xC 0.--31. 1. "SID,Size Identification Code" tree.end endif tree "PWR (Power Control)" base ad:0x50001000 group.long 0x0++0x13 line.long 0x0 "PWR_CR1,PWR control register 1" sif (cpuis("STM32MP13*")) bitfld.long 0x0 17.--18. "ALS,Analog Voltage Detector level selection." "0: 1.7V,1: 2.1V,2: 2.5V,3: 2.8V" newline bitfld.long 0x0 16. "AVDEN,Peripheral Voltage Monitor on VDDA enable." "0: Peripheral Voltage Monitor on VDDA disabled,1: Peripheral Voltage Monitor on VDDA enabled" newline bitfld.long 0x0 9. "MPU_RAM_LOWSPEED,Low speed selection for MPU memories" "0: MPU can operate in High speed mode (VDDCPU > 1.2V),1: MPU can only operate in Low speed mode (VDDCPU.." newline bitfld.long 0x0 8. "DBP,Disable backup domain write protection." "0: Write access to RTC and backup domain registers..,1: Write access to RTC and backup domain registers.." newline bitfld.long 0x0 5.--7. "PLS,Programmable Voltage Detector level selection." "0: 1.95 V,1: 2.1 V,2: 2.25 V,3: 2.4 V,4: 2.55 V,5: 2.7 V,6: 2.85 V,7: External voltage level on PVD_IN (compared to.." newline bitfld.long 0x0 4. "PVDEN,Programmable Voltage detector enable." "0: Programmable Voltage detector disabled.,1: Programmable Voltage detector enabled." newline bitfld.long 0x0 3. "STOP2,System LPLV-Stop2 mode selection" "0: Keeps System Stop mode when PDDS=0 and MPU..,1: Allows System LPLV-Stop2 mode when PDDS = 0" newline bitfld.long 0x0 2. "LVDS,Low Voltage Deepsleep LPLV-Stop mode selection." "0: LP-Stop mode VDDCORE and VDDCPU domains supply..,1: LPLV-Stop mode VDDCORE and VDDCPU domains supply.." newline bitfld.long 0x0 1. "LPCFG,PWR_ON pin configuration." "0: PWR_ON pin signals Standby mode (PWR_ON =1 in..,1: PWR_ON pin signals Standby LP-Stop LPLV-Stop and.." newline bitfld.long 0x0 0. "LPDS,Low Power Deepsleep Stop mode selection." "0: Stop mode selected External regulator kept in..,1: low-power stop mode selected External regulator.." newline endif sif (cpuis("STM32MP151*")) bitfld.long 0x0 17.--18. "ALS,ALS" "0,1,2,3" newline bitfld.long 0x0 16. "AVDEN,AVDEN" "0,1" newline endif sif (cpuis("STM32MP153*")) bitfld.long 0x0 17.--18. "ALS,ALS" "0,1,2,3" newline bitfld.long 0x0 16. "AVDEN,AVDEN" "0,1" newline endif sif (cpuis("STM32MP157*")) bitfld.long 0x0 17.--18. "ALS,ALS" "0,1,2,3" newline bitfld.long 0x0 16. "AVDEN,AVDEN" "0,1" newline endif sif (cpuis("STM32MP151*")) bitfld.long 0x0 8. "DBP,DBP" "0,1" newline bitfld.long 0x0 5.--7. "PLS,PLS" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 4. "PVDEN,PVDEN" "0,1" newline endif sif (cpuis("STM32MP153*")) bitfld.long 0x0 8. "DBP,DBP" "0,1" newline bitfld.long 0x0 5.--7. "PLS,PLS" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 4. "PVDEN,PVDEN" "0,1" newline endif sif (cpuis("STM32MP157*")) bitfld.long 0x0 8. "DBP,DBP" "0,1" newline bitfld.long 0x0 5.--7. "PLS,PLS" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 4. "PVDEN,PVDEN" "0,1" newline endif sif (cpuis("STM32MP151*")) bitfld.long 0x0 2. "LVDS,LVDS" "0,1" newline bitfld.long 0x0 1. "LPCFG,LPCFG" "0,1" newline endif sif (cpuis("STM32MP153*")) bitfld.long 0x0 2. "LVDS,LVDS" "0,1" newline bitfld.long 0x0 1. "LPCFG,LPCFG" "0,1" newline bitfld.long 0x0 0. "LPDS,LPDS" "0,1" newline endif sif (cpuis("STM32MP157*")) bitfld.long 0x0 2. "LVDS,LVDS" "0,1" newline bitfld.long 0x0 1. "LPCFG,LPCFG" "0,1" newline bitfld.long 0x0 0. "LPDS,LPDS" "0,1" endif line.long 0x4 "PWR_CSR1,PWR control status register 1" sif (cpuis("STM32MP13*")) rbitfld.long 0x4 16. "AVDO,Analog Voltage detector Output on VDDA." "0: VDDA is equal or higher than the AVD threshold..,1: VDDA is lower than the AVD threshold selected.." newline rbitfld.long 0x4 4. "PVDO,Programmable Voltage Detect Output" "0: VDD or voltage level on PVD_IN is equal or..,1: VDD or voltage level on PVD_IN is lower than the.." newline endif sif (cpuis("STM32MP151*")) bitfld.long 0x4 16. "AVDO,AVDO" "0,1" newline endif sif (cpuis("STM32MP153*")) bitfld.long 0x4 16. "AVDO,AVDO" "0,1" newline endif sif (cpuis("STM32MP157*")) bitfld.long 0x4 16. "AVDO,AVDO" "0,1" newline endif sif (cpuis("STM32MP151*")) bitfld.long 0x4 4. "PVDO,PVDO" "0,1" newline endif sif (cpuis("STM32MP153*")) bitfld.long 0x4 4. "PVDO,PVDO" "0,1" newline endif sif (cpuis("STM32MP157*")) bitfld.long 0x4 4. "PVDO,PVDO" "0,1" endif line.long 0x8 "PWR_CR2,PWR control register 2" sif (cpuis("STM32MP13*")) rbitfld.long 0x8 23. "TEMPH,Monitored temperature level above high threshold" "0: Temperature below high threshold level or..,1: Temperature equal or above high threshold level." newline rbitfld.long 0x8 22. "TEMPL,Monitored temperature level above low threshold" "0: Temperature above low threshold level or Monitor..,1: Temperature equal or below low threshold level." newline rbitfld.long 0x8 21. "VBATH,Monitored VBAT level above high threshold" "0: VBAT level below high threshold level or Monitor..,1: VBAT level equal or above high threshold level." newline rbitfld.long 0x8 20. "VBATL,Monitored VBAT level above low threshold" "0: VBAT level above low threshold level or Monitor..,1: VBAT level equal or below low threshold level." newline rbitfld.long 0x8 16. "BRRDY,Backup Regulator ready" "0: Backup Regulator not ready.,1: Backup Regulator ready." newline bitfld.long 0x8 4. "MONEN,VBAT and temperature monitoring enable" "0: VBAT and temperature monitoring disabled.,1: VBAT and temperature monitoring enabled." newline bitfld.long 0x8 0. "BREN,Backup regulator enable" "0: Backup regulator disabled,1: Backup regulator enabled" newline endif sif (cpuis("STM32MP151*")) rbitfld.long 0x8 23. "TEMPH,TEMPH" "0,1" newline rbitfld.long 0x8 22. "TEMPL,TEMPL" "0,1" newline rbitfld.long 0x8 21. "VBATH,VBATH" "0,1" newline rbitfld.long 0x8 20. "VBATL,VBATL" "0,1" newline endif sif (cpuis("STM32MP153*")) rbitfld.long 0x8 23. "TEMPH,TEMPH" "0,1" newline rbitfld.long 0x8 22. "TEMPL,TEMPL" "0,1" newline rbitfld.long 0x8 21. "VBATH,VBATH" "0,1" newline rbitfld.long 0x8 20. "VBATL,VBATL" "0,1" newline endif sif (cpuis("STM32MP157*")) rbitfld.long 0x8 23. "TEMPH,TEMPH" "0,1" newline rbitfld.long 0x8 22. "TEMPL,TEMPL" "0,1" newline rbitfld.long 0x8 21. "VBATH,VBATH" "0,1" newline rbitfld.long 0x8 20. "VBATL,VBATL" "0,1" newline endif sif (cpuis("STM32MP151*")) rbitfld.long 0x8 17. "RRRDY,RRRDY" "0,1" newline rbitfld.long 0x8 16. "BRRDY,BRRDY" "0,1" newline endif sif (cpuis("STM32MP153*")) rbitfld.long 0x8 17. "RRRDY,RRRDY" "0,1" newline rbitfld.long 0x8 16. "BRRDY,BRRDY" "0,1" newline endif sif (cpuis("STM32MP157*")) rbitfld.long 0x8 17. "RRRDY,RRRDY" "0,1" newline rbitfld.long 0x8 16. "BRRDY,BRRDY" "0,1" newline endif sif (cpuis("STM32MP151*")) bitfld.long 0x8 4. "MONEN,MONEN" "0,1" newline endif sif (cpuis("STM32MP153*")) bitfld.long 0x8 4. "MONEN,MONEN" "0,1" newline endif sif (cpuis("STM32MP157*")) bitfld.long 0x8 4. "MONEN,MONEN" "0,1" newline endif sif (cpuis("STM32MP151*")) bitfld.long 0x8 1. "RREN,RREN" "0,1" newline endif sif (cpuis("STM32MP153*")) bitfld.long 0x8 1. "RREN,RREN" "0,1" newline bitfld.long 0x8 0. "BREN,BREN" "0,1" newline endif sif (cpuis("STM32MP157*")) bitfld.long 0x8 1. "RREN,RREN" "0,1" newline bitfld.long 0x8 0. "BREN,BREN" "0,1" endif line.long 0xC "PWR_CR3,PWR control register 3" sif (cpuis("STM32MP13*")) rbitfld.long 0xC 31. "REG11RDY,1V1 regulator supply ready" "0: 1V1 supply not ready,1: 1V1 supply ready" newline bitfld.long 0xC 30. "REG11EN,1V1 regulator enable" "0: 1V1 regulator disabled,1: 1V1 regulator enabled (when in Standby mode the.." newline rbitfld.long 0xC 29. "REG18RDY,1V8 regulator supply ready" "0: 1V8 supply not ready,1: 1V8 supply ready" newline bitfld.long 0xC 28. "REG18EN,1V8 regulator enable" "0: 1V8 regulator disabled,1: 1V8 regulator enabled when also pin.." newline rbitfld.long 0xC 26. "USB33RDY,USB 3.3V supply ready" "0: USB 3.3V supply not ready,1: USB 3.3V supply ready" newline bitfld.long 0xC 24. "USB33DEN,USB 3.3V voltage level detector enable" "0: USB 3.3V voltage level detector,1: USB 3.3V voltage level detector" newline bitfld.long 0xC 23. "VDDSD2VALID,Override VDDSD2 voltage detector" "0: I/O enable/disable is controlled by the VDDSD2..,1: I/O enable is forced active" newline bitfld.long 0xC 22. "VDDSD1VALID,Override VDDSD1 voltage detector" "0: I/O enable/disable is controlled by the VDDSD1..,1: I/O enable is forced active" newline hexmask.long.byte 0xC 17.--21. 1. "POPL,PWR_ON PWR_CPU_ON Standby pulse low configuration" newline rbitfld.long 0xC 16. "VDDSD2RDY,VDDSD2 supply ready" "0: VDDSD2 supply not present or voltage detector..,1: VDDSD2 supply present" newline bitfld.long 0xC 15. "VDDSD2DEN,VDDSD2 voltage level detector enable" "0: VDDSD2 level detector switched off. I/Os in..,1: VDDSD2 level detector is active. I/Os in VDDSD2.." newline rbitfld.long 0xC 14. "VDDSD1RDY,VDDSD1 supply ready" "0: VDDSD1 supply not present or voltage detector..,1: VDDSD1 supply present" newline bitfld.long 0xC 13. "VDDSD1DEN,VDDSD1 voltage level detector enable" "0: VDDSD1 level detector switched off. I/Os in..,1: VDDSD1 level detector is active. I/Os in VDDSD1.." newline bitfld.long 0xC 12. "DDRRETEN,DDR retention enable" "0: DDR self-refresh retention disabled.,1: DDR self-refresh retention enabled." newline bitfld.long 0xC 11. "DDRSRDIS,DDR self-refresh retention after standby disable" "0: No action,1: When DDRSREN is 'b1: Disable DDR self-refresh.." newline bitfld.long 0xC 10. "DDRSREN,DDR self-refresh in standby mode enable" "0: DDR self-refresh retention when entering standby..,1: DDR self-refresh retention when entering standby.." newline bitfld.long 0xC 9. "VBRS,VBAT charging resistor selection" "0: Charges VBAT through a 5 kOhm resistor.,1: Charges VBAT through a 1.5 kOhm resistor." newline bitfld.long 0xC 8. "VBE,VBAT charging enable" "0: VBAT battery charging disabled.,1: VBAT battery charging enabled." newline endif sif (cpuis("STM32MP151*")) rbitfld.long 0xC 31. "REG11RDY,REG11RDY" "0,1" newline bitfld.long 0xC 30. "REG11EN,REG11EN" "0,1" newline rbitfld.long 0xC 29. "REG18RDY,REG18RDY" "0,1" newline bitfld.long 0xC 28. "REG18EN,REG18EN" "0,1" newline endif sif (cpuis("STM32MP153*")) rbitfld.long 0xC 31. "REG11RDY,REG11RDY" "0,1" newline bitfld.long 0xC 30. "REG11EN,REG11EN" "0,1" newline rbitfld.long 0xC 29. "REG18RDY,REG18RDY" "0,1" newline bitfld.long 0xC 28. "REG18EN,REG18EN" "0,1" newline endif sif (cpuis("STM32MP157*")) rbitfld.long 0xC 31. "REG11RDY,REG11RDY" "0,1" newline bitfld.long 0xC 30. "REG11EN,REG11EN" "0,1" newline rbitfld.long 0xC 29. "REG18RDY,REG18RDY" "0,1" newline bitfld.long 0xC 28. "REG18EN,REG18EN" "0,1" newline endif sif (cpuis("STM32MP151*")) rbitfld.long 0xC 26. "USB33RDY,USB33RDY" "0,1" newline endif sif (cpuis("STM32MP153*")) rbitfld.long 0xC 26. "USB33RDY,USB33RDY" "0,1" newline endif sif (cpuis("STM32MP157*")) rbitfld.long 0xC 26. "USB33RDY,USB33RDY" "0,1" newline endif sif (cpuis("STM32MP151*")) bitfld.long 0xC 24. "USB33DEN,USB33DEN" "0,1" newline endif sif (cpuis("STM32MP153*")) bitfld.long 0xC 24. "USB33DEN,USB33DEN" "0,1" newline endif sif (cpuis("STM32MP157*")) bitfld.long 0xC 24. "USB33DEN,USB33DEN" "0,1" newline endif sif (cpuis("STM32MP151*")) hexmask.long.byte 0xC 17.--21. 1. "POPL,POPL" newline endif sif (cpuis("STM32MP153*")) hexmask.long.byte 0xC 17.--21. 1. "POPL,POPL" newline endif sif (cpuis("STM32MP157*")) hexmask.long.byte 0xC 17.--21. 1. "POPL,POPL" newline endif sif (cpuis("STM32MP151*")) bitfld.long 0xC 12. "DDRRETEN,DDRRETEN" "0,1" newline bitfld.long 0xC 11. "DDRSRDIS,DDRSRDIS" "0,1" newline bitfld.long 0xC 10. "DDRSREN,DDRSREN" "0,1" newline bitfld.long 0xC 9. "VBRS,VBRS" "0,1" newline endif sif (cpuis("STM32MP153*")) bitfld.long 0xC 12. "DDRRETEN,DDRRETEN" "0,1" newline bitfld.long 0xC 11. "DDRSRDIS,DDRSRDIS" "0,1" newline bitfld.long 0xC 10. "DDRSREN,DDRSREN" "0,1" newline bitfld.long 0xC 9. "VBRS,VBRS" "0,1" newline bitfld.long 0xC 8. "VBE,VBE" "0,1" newline endif sif (cpuis("STM32MP157*")) bitfld.long 0xC 12. "DDRRETEN,DDRRETEN" "0,1" newline bitfld.long 0xC 11. "DDRSRDIS,DDRSRDIS" "0,1" newline bitfld.long 0xC 10. "DDRSREN,DDRSREN" "0,1" newline bitfld.long 0xC 9. "VBRS,VBRS" "0,1" newline bitfld.long 0xC 8. "VBE,VBE" "0,1" endif line.long 0x10 "PWR_MPUCR,PWR MPU control register" sif (cpuis("STM32MP13*")) rbitfld.long 0x10 15. "STANDBYWFIL2,MPU system idle indication" "0: MPU system CRun or CSleep,1: MPU system CStop or CStandby" newline bitfld.long 0x10 9. "CSSF,Clear MPU Standby Stop flags.(Always read as 0)" "0: No effect,1: When written clears the MPU flags (STOPF SBF and.." newline rbitfld.long 0x10 7. "SBFMPU,MPU Standby flag" "0: MPU has not been in CStandby mode.,1: MPU has been in CStandby mode." newline rbitfld.long 0x10 6. "SBF,System Standby flag" "0: System has not been in Standby mode.,1: System has been in Standby mode system contents.." newline rbitfld.long 0x10 5. "STOPF,Stop flag" "0: System has not been in Stop mode,1: System has been in Stop mode clock system has.." newline bitfld.long 0x10 0. "PDDS,System Power Down Deepsleep selection" "0: Keeps System Stop when MPU enters to CStop or..,1: Allows System Standby mode when MPU enters to.." newline endif sif (cpuis("STM32MP151*")) rbitfld.long 0x10 15. "STANDBYWFIL2,STANDBYWFIL2" "0,1" newline endif sif (cpuis("STM32MP153*")) rbitfld.long 0x10 15. "STANDBYWFIL2,STANDBYWFIL2" "0,1" newline endif sif (cpuis("STM32MP157*")) rbitfld.long 0x10 15. "STANDBYWFIL2,STANDBYWFIL2" "0,1" newline endif sif (cpuis("STM32MP151*")) bitfld.long 0x10 9. "CSSF,CSSF" "0,1" newline endif sif (cpuis("STM32MP153*")) bitfld.long 0x10 9. "CSSF,CSSF" "0,1" newline endif sif (cpuis("STM32MP157*")) bitfld.long 0x10 9. "CSSF,CSSF" "0,1" newline endif sif (cpuis("STM32MP151*")) rbitfld.long 0x10 7. "SBFMPU,SBFMPU" "0,1" newline rbitfld.long 0x10 6. "SBF,SBF" "0,1" newline rbitfld.long 0x10 5. "STOPF,STOPF" "0,1" newline endif sif (cpuis("STM32MP153*")) rbitfld.long 0x10 7. "SBFMPU,SBFMPU" "0,1" newline rbitfld.long 0x10 6. "SBF,SBF" "0,1" newline rbitfld.long 0x10 5. "STOPF,STOPF" "0,1" newline endif sif (cpuis("STM32MP157*")) rbitfld.long 0x10 7. "SBFMPU,SBFMPU" "0,1" newline rbitfld.long 0x10 6. "SBF,SBF" "0,1" newline rbitfld.long 0x10 5. "STOPF,STOPF" "0,1" newline endif sif (cpuis("STM32MP151*")) bitfld.long 0x10 3. "CSTBYDIS,CSTBYDIS" "0,1" newline endif sif (cpuis("STM32MP153*")) bitfld.long 0x10 3. "CSTBYDIS,CSTBYDIS" "0,1" newline endif sif (cpuis("STM32MP157*")) bitfld.long 0x10 3. "CSTBYDIS,CSTBYDIS" "0,1" newline endif sif (cpuis("STM32MP153*")) bitfld.long 0x10 0. "PDDS,PDDS" "0,1" newline endif sif (cpuis("STM32MP157*")) bitfld.long 0x10 0. "PDDS,PDDS" "0,1" endif group.long 0x20++0xB line.long 0x0 "PWR_WKUPCR,PWR wakeup control register" sif (cpuis("STM32MP13*")) bitfld.long 0x0 26.--27. "WKUPPUPD6,Wakeup pull configuration for WKUPn pin (n = 6 to 1)" "0: No pulls,1: Pull-up,2: Pull-down,?" newline bitfld.long 0x0 24.--25. "WKUPPUPD5,Wakeup pull configuration for WKUPn pin (n = 6 to 1)" "0: No pulls,1: Pull-up,2: Pull-down,?" newline bitfld.long 0x0 22.--23. "WKUPPUPD4,Wakeup pull configuration for WKUPn pin (n = 6 to 1)" "0: No pulls,1: Pull-up,2: Pull-down,?" newline bitfld.long 0x0 20.--21. "WKUPPUPD3,Wakeup pull configuration for WKUPn pin (n = 6 to 1)" "0: No pulls,1: Pull-up,2: Pull-down,?" newline bitfld.long 0x0 18.--19. "WKUPPUPD2,Wakeup pull configuration for WKUPn pin (n = 6 to 1)" "0: No pulls,1: Pull-up,2: Pull-down,?" newline bitfld.long 0x0 16.--17. "WKUPPUPD1,Wakeup pull configuration for WKUPn pin (n = 6 to 1)" "0: No pulls,1: Pull-up,2: Pull-down,?" newline bitfld.long 0x0 13. "WKUPP6,Wakeup Polarity bit for WKUPn pin n range [6:1]" "0: Detection on high level (rising edge),1: Detection on low level (falling edge)" newline bitfld.long 0x0 12. "WKUPP5,Wakeup Polarity bit for WKUPn pin n range [6:1]" "0: Detection on high level (rising edge),1: Detection on low level (falling edge)" newline bitfld.long 0x0 11. "WKUPP4,Wakeup Polarity bit for WKUPn pin n range [6:1]" "0: Detection on high level (rising edge),1: Detection on low level (falling edge)" newline bitfld.long 0x0 10. "WKUPP3,Wakeup Polarity bit for WKUPn pin n range [6:1]" "0: Detection on high level (rising edge),1: Detection on low level (falling edge)" newline bitfld.long 0x0 9. "WKUPP2,Wakeup Polarity bit for WKUPn pin n range [6:1]" "0: Detection on high level (rising edge),1: Detection on low level (falling edge)" newline bitfld.long 0x0 8. "WKUPP1,Wakeup Polarity bit for WKUPn pin n range [6:1]" "0: Detection on high level (rising edge),1: Detection on low level (falling edge)" newline bitfld.long 0x0 5. "WKUPC6,Clear Wakeup Flag for WKUPn pin n range [6:1]" "0: No effect,1: Writing 1 clears the WKUPFn wakeup flag (the bit.." newline bitfld.long 0x0 4. "WKUPC5,Clear Wakeup Flag for WKUPn pin n range [6:1]" "0: No effect,1: Writing 1 clears the WKUPFn wakeup flag (the bit.." newline bitfld.long 0x0 3. "WKUPC4,Clear Wakeup Flag for WKUPn pin n range [6:1]" "0: No effect,1: Writing 1 clears the WKUPFn wakeup flag (the bit.." newline bitfld.long 0x0 2. "WKUPC3,Clear Wakeup Flag for WKUPn pin n range [6:1]" "0: No effect,1: Writing 1 clears the WKUPFn wakeup flag (the bit.." newline bitfld.long 0x0 1. "WKUPC2,Clear Wakeup Flag for WKUPn pin n range [6:1]" "0: No effect,1: Writing 1 clears the WKUPFn wakeup flag (the bit.." newline bitfld.long 0x0 0. "WKUPC1,Clear Wakeup Flag for WKUPn pin n range [6:1]" "0: No effect,1: Writing 1 clears the WKUPFn wakeup flag (the bit.." newline endif sif (cpuis("STM32MP151*")) bitfld.long 0x0 26.--27. "WKUPPUPD6,WKUPPUPD6" "0,1,2,3" newline bitfld.long 0x0 24.--25. "WKUPPUPD5,WKUPPUPD5" "0,1,2,3" newline bitfld.long 0x0 22.--23. "WKUPPUPD4,WKUPPUPD4" "0,1,2,3" newline bitfld.long 0x0 20.--21. "WKUPPUPD3,WKUPPUPD3" "0,1,2,3" newline bitfld.long 0x0 18.--19. "WKUPPUPD2,WKUPPUPD2" "0,1,2,3" newline bitfld.long 0x0 16.--17. "WKUPPUPD1,WKUPPUPD1" "0,1,2,3" newline endif sif (cpuis("STM32MP153*")) bitfld.long 0x0 26.--27. "WKUPPUPD6,WKUPPUPD6" "0,1,2,3" newline bitfld.long 0x0 24.--25. "WKUPPUPD5,WKUPPUPD5" "0,1,2,3" newline bitfld.long 0x0 22.--23. "WKUPPUPD4,WKUPPUPD4" "0,1,2,3" newline bitfld.long 0x0 20.--21. "WKUPPUPD3,WKUPPUPD3" "0,1,2,3" newline bitfld.long 0x0 18.--19. "WKUPPUPD2,WKUPPUPD2" "0,1,2,3" newline bitfld.long 0x0 16.--17. "WKUPPUPD1,WKUPPUPD1" "0,1,2,3" newline endif sif (cpuis("STM32MP157*")) bitfld.long 0x0 26.--27. "WKUPPUPD6,WKUPPUPD6" "0,1,2,3" newline bitfld.long 0x0 24.--25. "WKUPPUPD5,WKUPPUPD5" "0,1,2,3" newline bitfld.long 0x0 22.--23. "WKUPPUPD4,WKUPPUPD4" "0,1,2,3" newline bitfld.long 0x0 20.--21. "WKUPPUPD3,WKUPPUPD3" "0,1,2,3" newline bitfld.long 0x0 18.--19. "WKUPPUPD2,WKUPPUPD2" "0,1,2,3" newline bitfld.long 0x0 16.--17. "WKUPPUPD1,WKUPPUPD1" "0,1,2,3" newline endif sif (cpuis("STM32MP151*")) bitfld.long 0x0 13. "WKUPP6,WKUPP6" "0,1" newline bitfld.long 0x0 12. "WKUPP5,WKUPP5" "0,1" newline bitfld.long 0x0 11. "WKUPP4,WKUPP4" "0,1" newline bitfld.long 0x0 10. "WKUPP3,WKUPP3" "0,1" newline bitfld.long 0x0 9. "WKUPP2,WKUPP2" "0,1" newline bitfld.long 0x0 8. "WKUPP1,WKUPP1" "0,1" newline endif sif (cpuis("STM32MP153*")) bitfld.long 0x0 13. "WKUPP6,WKUPP6" "0,1" newline bitfld.long 0x0 12. "WKUPP5,WKUPP5" "0,1" newline bitfld.long 0x0 11. "WKUPP4,WKUPP4" "0,1" newline bitfld.long 0x0 10. "WKUPP3,WKUPP3" "0,1" newline bitfld.long 0x0 9. "WKUPP2,WKUPP2" "0,1" newline bitfld.long 0x0 8. "WKUPP1,WKUPP1" "0,1" newline endif sif (cpuis("STM32MP157*")) bitfld.long 0x0 13. "WKUPP6,WKUPP6" "0,1" newline bitfld.long 0x0 12. "WKUPP5,WKUPP5" "0,1" newline bitfld.long 0x0 11. "WKUPP4,WKUPP4" "0,1" newline bitfld.long 0x0 10. "WKUPP3,WKUPP3" "0,1" newline bitfld.long 0x0 9. "WKUPP2,WKUPP2" "0,1" newline bitfld.long 0x0 8. "WKUPP1,WKUPP1" "0,1" newline endif sif (cpuis("STM32MP151*")) bitfld.long 0x0 5. "WKUPC6,WKUPC6" "0,1" newline bitfld.long 0x0 4. "WKUPC5,WKUPC5" "0,1" newline bitfld.long 0x0 3. "WKUPC4,WKUPC4" "0,1" newline bitfld.long 0x0 2. "WKUPC3,WKUPC3" "0,1" newline bitfld.long 0x0 1. "WKUPC2,WKUPC2" "0,1" newline endif sif (cpuis("STM32MP153*")) bitfld.long 0x0 5. "WKUPC6,WKUPC6" "0,1" newline bitfld.long 0x0 4. "WKUPC5,WKUPC5" "0,1" newline bitfld.long 0x0 3. "WKUPC4,WKUPC4" "0,1" newline bitfld.long 0x0 2. "WKUPC3,WKUPC3" "0,1" newline bitfld.long 0x0 1. "WKUPC2,WKUPC2" "0,1" newline bitfld.long 0x0 0. "WKUPC1,WKUPC1" "0,1" newline endif sif (cpuis("STM32MP157*")) bitfld.long 0x0 5. "WKUPC6,WKUPC6" "0,1" newline bitfld.long 0x0 4. "WKUPC5,WKUPC5" "0,1" newline bitfld.long 0x0 3. "WKUPC4,WKUPC4" "0,1" newline bitfld.long 0x0 2. "WKUPC3,WKUPC3" "0,1" newline bitfld.long 0x0 1. "WKUPC2,WKUPC2" "0,1" newline bitfld.long 0x0 0. "WKUPC1,WKUPC1" "0,1" endif line.long 0x4 "PWR_WKUPFR,PWR wakeup flag register" sif (cpuis("STM32MP13*")) rbitfld.long 0x4 5. "WKUPF6,Wakeup flag for WKUPn pin before enable n range [6:1]." "0: No wakeup event occurred,1: A wakeup event was received from WKUPCn pin" newline rbitfld.long 0x4 4. "WKUPF5,Wakeup flag for WKUPn pin before enable n range [6:1]." "0: No wakeup event occurred,1: A wakeup event was received from WKUPCn pin" newline rbitfld.long 0x4 3. "WKUPF4,Wakeup flag for WKUPn pin before enable n range [6:1]." "0: No wakeup event occurred,1: A wakeup event was received from WKUPCn pin" newline rbitfld.long 0x4 2. "WKUPF3,Wakeup flag for WKUPn pin before enable n range [6:1]." "0: No wakeup event occurred,1: A wakeup event was received from WKUPCn pin" newline rbitfld.long 0x4 1. "WKUPF2,Wakeup flag for WKUPn pin before enable n range [6:1]." "0: No wakeup event occurred,1: A wakeup event was received from WKUPCn pin" newline rbitfld.long 0x4 0. "WKUPF1,Wakeup flag for WKUPn pin before enable n range [6:1]." "0: No wakeup event occurred,1: A wakeup event was received from WKUPCn pin" newline endif sif (cpuis("STM32MP151*")) bitfld.long 0x4 5. "WKUPF6,WKUPF6" "0,1" newline bitfld.long 0x4 4. "WKUPF5,WKUPF5" "0,1" newline bitfld.long 0x4 3. "WKUPF4,WKUPF4" "0,1" newline bitfld.long 0x4 2. "WKUPF3,WKUPF3" "0,1" newline bitfld.long 0x4 1. "WKUPF2,WKUPF2" "0,1" newline bitfld.long 0x4 0. "WKUPF1,WKUPF1" "0,1" newline endif sif (cpuis("STM32MP153*")) bitfld.long 0x4 5. "WKUPF6,WKUPF6" "0,1" newline bitfld.long 0x4 4. "WKUPF5,WKUPF5" "0,1" newline bitfld.long 0x4 3. "WKUPF4,WKUPF4" "0,1" newline bitfld.long 0x4 2. "WKUPF3,WKUPF3" "0,1" newline bitfld.long 0x4 1. "WKUPF2,WKUPF2" "0,1" newline bitfld.long 0x4 0. "WKUPF1,WKUPF1" "0,1" newline endif sif (cpuis("STM32MP157*")) bitfld.long 0x4 5. "WKUPF6,WKUPF6" "0,1" newline bitfld.long 0x4 4. "WKUPF5,WKUPF5" "0,1" newline bitfld.long 0x4 3. "WKUPF4,WKUPF4" "0,1" newline bitfld.long 0x4 2. "WKUPF3,WKUPF3" "0,1" newline bitfld.long 0x4 1. "WKUPF2,WKUPF2" "0,1" newline bitfld.long 0x4 0. "WKUPF1,WKUPF1" "0,1" endif line.long 0x8 "PWR_MPUWKUPENR,PWR MPU wakeup enable register" sif (cpuis("STM32MP13*")) bitfld.long 0x8 5. "WKUPEN6,Enable Wakeup WKUPn pin and interrupt for MPU n range [6:1]" "0: An event on WKUPn pin does not wake up the..,1: A rising or falling edge on WKUPn pin wakes up.." newline bitfld.long 0x8 4. "WKUPEN5,Enable Wakeup WKUPn pin and interrupt for MPU n range [6:1]" "0: An event on WKUPn pin does not wake up the..,1: A rising or falling edge on WKUPn pin wakes up.." newline bitfld.long 0x8 3. "WKUPEN4,Enable Wakeup WKUPn pin and interrupt for MPU n range [6:1]" "0: An event on WKUPn pin does not wake up the..,1: A rising or falling edge on WKUPn pin wakes up.." newline bitfld.long 0x8 2. "WKUPEN3,Enable Wakeup WKUPn pin and interrupt for MPU n range [6:1]" "0: An event on WKUPn pin does not wake up the..,1: A rising or falling edge on WKUPn pin wakes up.." newline bitfld.long 0x8 1. "WKUPEN2,Enable Wakeup WKUPn pin and interrupt for MPU n range [6:1]" "0: An event on WKUPn pin does not wake up the..,1: A rising or falling edge on WKUPn pin wakes up.." newline bitfld.long 0x8 0. "WKUPEN1,Enable Wakeup WKUPn pin and interrupt for MPU n range [6:1]" "0: An event on WKUPn pin does not wake up the..,1: A rising or falling edge on WKUPn pin wakes up.." newline endif sif (cpuis("STM32MP151*")) bitfld.long 0x8 5. "WKUPEN6,WKUPEN6" "0,1" newline bitfld.long 0x8 4. "WKUPEN5,WKUPEN5" "0,1" newline bitfld.long 0x8 3. "WKUPEN4,WKUPEN4" "0,1" newline bitfld.long 0x8 2. "WKUPEN3,WKUPEN3" "0,1" newline bitfld.long 0x8 1. "WKUPEN2,WKUPEN2" "0,1" newline endif sif (cpuis("STM32MP153*")) bitfld.long 0x8 5. "WKUPEN6,WKUPEN6" "0,1" newline bitfld.long 0x8 4. "WKUPEN5,WKUPEN5" "0,1" newline bitfld.long 0x8 3. "WKUPEN4,WKUPEN4" "0,1" newline bitfld.long 0x8 2. "WKUPEN3,WKUPEN3" "0,1" newline bitfld.long 0x8 1. "WKUPEN2,WKUPEN2" "0,1" newline bitfld.long 0x8 0. "WKUPEN1,WKUPEN1" "0,1" newline endif sif (cpuis("STM32MP157*")) bitfld.long 0x8 5. "WKUPEN6,WKUPEN6" "0,1" newline bitfld.long 0x8 4. "WKUPEN5,WKUPEN5" "0,1" newline bitfld.long 0x8 3. "WKUPEN4,WKUPEN4" "0,1" newline bitfld.long 0x8 2. "WKUPEN3,WKUPEN3" "0,1" newline bitfld.long 0x8 1. "WKUPEN2,WKUPEN2" "0,1" newline bitfld.long 0x8 0. "WKUPEN1,WKUPEN1" "0,1" endif group.long 0x3F4++0xB line.long 0x0 "PWR_VER,PWR IP version register" sif (cpuis("STM32MP13*")) hexmask.long.byte 0x0 4.--7. 1. "MAJREV,Major revision number" newline hexmask.long.byte 0x0 0.--3. 1. "MINREV,Minor revision number" newline endif sif (cpuis("STM32MP151*")) hexmask.long.byte 0x0 4.--7. 1. "MAJREV,MAJREV" newline hexmask.long.byte 0x0 0.--3. 1. "MINREV,MINREV" newline endif sif (cpuis("STM32MP153*")) hexmask.long.byte 0x0 4.--7. 1. "MAJREV,MAJREV" newline hexmask.long.byte 0x0 0.--3. 1. "MINREV,MINREV" newline endif sif (cpuis("STM32MP157*")) hexmask.long.byte 0x0 4.--7. 1. "MAJREV,MAJREV" newline hexmask.long.byte 0x0 0.--3. 1. "MINREV,MINREV" endif line.long 0x4 "PWR_ID,PWR IP identification register" sif (cpuis("STM32MP13*")) hexmask.long 0x4 0.--31. 1. "IPID,IP identification" newline endif sif (cpuis("STM32MP151*")) hexmask.long 0x4 0.--31. 1. "IPID,IPID" newline endif sif (cpuis("STM32MP153*")) hexmask.long 0x4 0.--31. 1. "IPID,IPID" newline endif sif (cpuis("STM32MP157*")) hexmask.long 0x4 0.--31. 1. "IPID,IPID" endif line.long 0x8 "PWR_SID,PWR size ID register" sif (cpuis("STM32MP13*")) hexmask.long 0x8 0.--31. 1. "SID,Size identification" newline endif sif (cpuis("STM32MP151*")) hexmask.long 0x8 0.--31. 1. "SID,SID" newline endif sif (cpuis("STM32MP153*")) hexmask.long 0x8 0.--31. 1. "SID,SID" newline endif sif (cpuis("STM32MP157*")) hexmask.long 0x8 0.--31. 1. "SID,SID" endif sif (cpuis("STM32MP151*")) rgroup.long 0x4++0x3 line.long 0x0 "PWR_CSR1,Reset on any system reset." group.long 0x14++0x3 line.long 0x0 "PWR_MCUCR,See individual bits for reset condition. Access 6 wait states when writing this register. This register is always non-secure. When a system reset occurs during the register write cycle the written data is not guaranteed." rbitfld.long 0x0 15. "DEEPSLEEP,DEEPSLEEP" "0,1" bitfld.long 0x0 9. "CSSF,CSSF" "0,1" newline rbitfld.long 0x0 6. "SBF,SBF" "0,1" rbitfld.long 0x0 5. "STOPF,STOPF" "0,1" newline bitfld.long 0x0 0. "PDDS,PDDS" "0,1" endif sif (cpuis("STM32MP151*")) rgroup.long 0x24++0x3 line.long 0x0 "PWR_WKUPFR,Not reset by wakeup from Standby mode but by any Application reset (NRST. IWDG. ...)" group.long 0x2C++0x3 line.long 0x0 "PWR_MCUWKUPENR,Not reset by wakeup from Standby mode but by any Application reset (NRST. IWDG. ...) Access 6 wait states when writing this register. When a system reset occurs during the register write cycle the written data is not guaranteed." bitfld.long 0x0 5. "WKUPEN6,WKUPEN6" "0,1" bitfld.long 0x0 4. "WKUPEN5,WKUPEN5" "0,1" newline bitfld.long 0x0 3. "WKUPEN4,WKUPEN4" "0,1" bitfld.long 0x0 2. "WKUPEN3,WKUPEN3" "0,1" newline bitfld.long 0x0 1. "WKUPEN2,WKUPEN2" "0,1" bitfld.long 0x0 0. "WKUPEN1,WKUPEN1" "0,1" endif sif (cpuis("STM32MP151*")) rgroup.long 0x3F4++0x3 line.long 0x0 "PWR_VER,PWR IP version register" endif sif (cpuis("STM32MP151*")) rgroup.long 0x3F8++0x3 line.long 0x0 "PWR_ID,PWR IP identification register" endif sif (cpuis("STM32MP151*")) rgroup.long 0x3FC++0x3 line.long 0x0 "PWR_SID,PWR size ID register" endif sif (cpuis("STM32MP153*")) rgroup.long 0x4++0x3 line.long 0x0 "PWR_CSR1,Reset on any system reset." group.long 0x14++0x3 line.long 0x0 "PWR_MCUCR,See individual bits for reset condition. Access 6 wait states when writing this register. This register is always non-secure. When a system reset occurs during the register write cycle the written data is not guaranteed." rbitfld.long 0x0 15. "DEEPSLEEP,DEEPSLEEP" "0,1" bitfld.long 0x0 9. "CSSF,CSSF" "0,1" newline rbitfld.long 0x0 6. "SBF,SBF" "0,1" rbitfld.long 0x0 5. "STOPF,STOPF" "0,1" newline bitfld.long 0x0 0. "PDDS,PDDS" "0,1" endif sif (cpuis("STM32MP153*")) rgroup.long 0x24++0x3 line.long 0x0 "PWR_WKUPFR,Not reset by wakeup from Standby mode but by any Application reset (NRST. IWDG. ...)" group.long 0x2C++0x3 line.long 0x0 "PWR_MCUWKUPENR,Not reset by wakeup from Standby mode but by any Application reset (NRST. IWDG. ...) Access 6 wait states when writing this register. When a system reset occurs during the register write cycle the written data is not guaranteed." bitfld.long 0x0 5. "WKUPEN6,WKUPEN6" "0,1" bitfld.long 0x0 4. "WKUPEN5,WKUPEN5" "0,1" newline bitfld.long 0x0 3. "WKUPEN4,WKUPEN4" "0,1" bitfld.long 0x0 2. "WKUPEN3,WKUPEN3" "0,1" newline bitfld.long 0x0 1. "WKUPEN2,WKUPEN2" "0,1" bitfld.long 0x0 0. "WKUPEN1,WKUPEN1" "0,1" endif sif (cpuis("STM32MP153*")) rgroup.long 0x3F4++0x3 line.long 0x0 "PWR_VER,PWR IP version register" endif sif (cpuis("STM32MP153*")) rgroup.long 0x3F8++0x3 line.long 0x0 "PWR_ID,PWR IP identification register" endif sif (cpuis("STM32MP153*")) rgroup.long 0x3FC++0x3 line.long 0x0 "PWR_SID,PWR size ID register" endif sif (cpuis("STM32MP157*")) rgroup.long 0x4++0x3 line.long 0x0 "PWR_CSR1,Reset on any system reset." group.long 0x14++0x3 line.long 0x0 "PWR_MCUCR,See individual bits for reset condition. Access 6 wait states when writing this register. This register is always non-secure. When a system reset occurs during the register write cycle the written data is not guaranteed." rbitfld.long 0x0 15. "DEEPSLEEP,DEEPSLEEP" "0,1" bitfld.long 0x0 9. "CSSF,CSSF" "0,1" newline rbitfld.long 0x0 6. "SBF,SBF" "0,1" rbitfld.long 0x0 5. "STOPF,STOPF" "0,1" newline bitfld.long 0x0 0. "PDDS,PDDS" "0,1" endif sif (cpuis("STM32MP157*")) rgroup.long 0x24++0x3 line.long 0x0 "PWR_WKUPFR,Not reset by wakeup from Standby mode but by any Application reset (NRST. IWDG. ...)" group.long 0x2C++0x3 line.long 0x0 "PWR_MCUWKUPENR,Not reset by wakeup from Standby mode but by any Application reset (NRST. IWDG. ...) Access 6 wait states when writing this register. When a system reset occurs during the register write cycle the written data is not guaranteed." bitfld.long 0x0 5. "WKUPEN6,WKUPEN6" "0,1" bitfld.long 0x0 4. "WKUPEN5,WKUPEN5" "0,1" newline bitfld.long 0x0 3. "WKUPEN4,WKUPEN4" "0,1" bitfld.long 0x0 2. "WKUPEN3,WKUPEN3" "0,1" newline bitfld.long 0x0 1. "WKUPEN2,WKUPEN2" "0,1" bitfld.long 0x0 0. "WKUPEN1,WKUPEN1" "0,1" endif sif (cpuis("STM32MP157*")) rgroup.long 0x3F4++0x3 line.long 0x0 "PWR_VER,PWR IP version register" endif sif (cpuis("STM32MP157*")) rgroup.long 0x3F8++0x3 line.long 0x0 "PWR_ID,PWR IP identification register" endif sif (cpuis("STM32MP157*")) rgroup.long 0x3FC++0x3 line.long 0x0 "PWR_SID,PWR size ID register" endif tree.end tree "QUADSPI (Quad-SPI Interface)" base ad:0x58003000 group.long 0x0++0x7 line.long 0x0 "QUADSPI_CR,QUADSPI control register" hexmask.long.byte 0x0 24.--31. 1. "PRESCALER,PRESCALER" bitfld.long 0x0 23. "PMM,PMM" "0,1" bitfld.long 0x0 22. "APMS,APMS" "0,1" bitfld.long 0x0 20. "TOIE,TOIE" "0,1" bitfld.long 0x0 19. "SMIE,SMIE" "0,1" bitfld.long 0x0 18. "FTIE,FTIE" "0,1" bitfld.long 0x0 17. "TCIE,TCIE" "0,1" bitfld.long 0x0 16. "TEIE,TEIE" "0,1" newline hexmask.long.byte 0x0 8.--11. 1. "FTHRES,FTHRES" bitfld.long 0x0 7. "FSEL,FSEL" "0,1" bitfld.long 0x0 6. "DFM,DFM" "0,1" bitfld.long 0x0 4. "SSHIFT,SSHIFT" "0,1" bitfld.long 0x0 3. "TCEN,TCEN" "0,1" bitfld.long 0x0 2. "DMAEN,DMAEN" "0,1" bitfld.long 0x0 1. "ABORT,ABORT" "0,1" bitfld.long 0x0 0. "EN,EN" "0,1" line.long 0x4 "QUADSPI_DCR,QUADSPI device configuration register" hexmask.long.byte 0x4 16.--20. 1. "FSIZE,FSIZE" bitfld.long 0x4 8.--10. "CSHT,CSHT" "0,1,2,3,4,5,6,7" bitfld.long 0x4 0. "CKMODE,CKMODE" "0,1" rgroup.long 0x8++0x3 line.long 0x0 "QUADSPI_SR,QUADSPI status register" hexmask.long.byte 0x0 8.--12. 1. "FLEVEL,FLEVEL" bitfld.long 0x0 5. "BUSY,BUSY" "0,1" bitfld.long 0x0 4. "TOF,TOF" "0,1" bitfld.long 0x0 3. "SMF,SMF" "0,1" bitfld.long 0x0 2. "FTF,FTF" "0,1" bitfld.long 0x0 1. "TCF,TCF" "0,1" bitfld.long 0x0 0. "TEF,TEF" "0,1" wgroup.long 0xC++0x3 line.long 0x0 "QUADSPI_FCR,QUADSPI flag clear register" bitfld.long 0x0 4. "CTOF,CTOF" "0,1" bitfld.long 0x0 3. "CSMF,CSMF" "0,1" bitfld.long 0x0 1. "CTCF,CTCF" "0,1" bitfld.long 0x0 0. "CTEF,CTEF" "0,1" group.long 0x10++0x23 line.long 0x0 "QUADSPI_DLR,QUADSPI data length register" hexmask.long 0x0 0.--31. 1. "DL,DL" line.long 0x4 "QUADSPI_CCR,QUADSPI communication configuration register" bitfld.long 0x4 31. "DDRM,DDRM" "0,1" bitfld.long 0x4 30. "DHHC,DHHC" "0,1" bitfld.long 0x4 29. "FRCM,FRCM" "0,1" bitfld.long 0x4 28. "SIOO,SIOO" "0,1" bitfld.long 0x4 26.--27. "FMODE,FMODE" "0,1,2,3" bitfld.long 0x4 24.--25. "DMODE,DMODE" "0,1,2,3" hexmask.long.byte 0x4 18.--22. 1. "DCYC,DCYC" bitfld.long 0x4 16.--17. "ABSIZE,ABSIZE" "0,1,2,3" newline bitfld.long 0x4 14.--15. "ABMODE,ABMODE" "0,1,2,3" bitfld.long 0x4 12.--13. "ADSIZE,ADSIZE" "0,1,2,3" bitfld.long 0x4 10.--11. "ADMODE,ADMODE" "0,1,2,3" bitfld.long 0x4 8.--9. "IMODE,IMODE" "0,1,2,3" hexmask.long.byte 0x4 0.--7. 1. "INSTRUCTION,INSTRUCTION" line.long 0x8 "QUADSPI_AR,QUADSPI address register" hexmask.long 0x8 0.--31. 1. "ADDRESS,ADDRESS" line.long 0xC "QUADSPI_ABR,QUADSPI alternate bytes registers" hexmask.long 0xC 0.--31. 1. "ALTERNATE,ALTERNATE" line.long 0x10 "QUADSPI_DR,QUADSPI data register" hexmask.long 0x10 0.--31. 1. "DATA,DATA" line.long 0x14 "QUADSPI_PSMKR,QUADSPI polling status mask register" hexmask.long 0x14 0.--31. 1. "MASK,MASK" line.long 0x18 "QUADSPI_PSMAR,QUADSPI polling status match register" hexmask.long 0x18 0.--31. 1. "MATCH,MATCH" line.long 0x1C "QUADSPI_PIR,QUADSPI polling interval register" hexmask.long.word 0x1C 0.--15. 1. "INTERVAL,INTERVAL" line.long 0x20 "QUADSPI_LPTR,QUADSPI low-power timeout register" hexmask.long.word 0x20 0.--15. 1. "TIMEOUT,TIMEOUT" rgroup.long 0x3F0++0xF line.long 0x0 "QUADSPI_HWCFGR,QUADSPI HW configuration register" hexmask.long.byte 0x0 12.--15. 1. "IDLENGTH,IDLENGTH" hexmask.long.byte 0x0 8.--11. 1. "PRESCVAL,PRESCVAL" hexmask.long.byte 0x0 4.--7. 1. "FIFOPTR,FIFOPTR" hexmask.long.byte 0x0 0.--3. 1. "FIFOSIZE,FIFOSIZE" line.long 0x4 "QUADSPI_VERR,QUADSPI version register" hexmask.long.byte 0x4 4.--7. 1. "MAJREV,MAJREV" hexmask.long.byte 0x4 0.--3. 1. "MINREV,MINREV" line.long 0x8 "QUADSPI_IPIDR,QUADSPI identification register" hexmask.long 0x8 0.--31. 1. "ID,ID" line.long 0xC "QUADSPI_SIDR,QUADSPI size identification register" hexmask.long 0xC 0.--31. 1. "SID,SID" tree.end tree "RCC (Reset and Clock Control)" base ad:0x50000000 sif (cpuis("STM32MP13*")) group.long 0x0++0x3 line.long 0x0 "RCC_SECCFGR,RCC secure configuration register" bitfld.long 0x0 31. "PWRSEC,Secure state of the PWR block" "0: non-secure,1: secure (default after reset)" bitfld.long 0x0 25. "RSTSEC,Secure state of the reset" "0: non-secure,1: secure (default after reset)" newline bitfld.long 0x0 24. "STPSEC,Secure state of the Stop modes" "0: non-secure,1: secure (default after reset)" bitfld.long 0x0 23. "MCO2SEC,Secure state of the MCO2 clock" "0: non-secure,1: secure (default after reset)" newline bitfld.long 0x0 22. "MCO1SEC,Secure state of the MCO1 clock" "0: non-secure,1: secure (default after reset)" bitfld.long 0x0 21. "CPERSEC,Secure state of the common peripheral clock" "0: non-secure,1: secure (default after reset)" newline bitfld.long 0x0 20. "TIMG3SEC,Secure state of the TIMG3 prescaler" "0: non-secure,1: secure (default after reset)" bitfld.long 0x0 19. "APB6DIVSEC,Secure state of the APB6DIV divider" "0: non-secure,1: secure (default after reset)" newline bitfld.long 0x0 18. "APB5DIVSEC,Secure state of the APB5DIV divider" "0: non-secure,1: secure (default after reset)" bitfld.long 0x0 17. "APB4DIVSEC,Secure state of the APB4DIV divider" "0: non-secure,1: secure (default after reset)" newline bitfld.long 0x0 16. "APB3DIVSEC,Secure state of the APB3DIV divider" "0: non-secure,1: secure (default after reset)" bitfld.long 0x0 13. "MLAHBSEC,Secure state of the MLAHB sub-system clock" "0: non-secure,1: secure (default after reset)" newline bitfld.long 0x0 12. "AXISEC,Secure state of the AXI sub-system clock" "0: non-secure,1: secure (default after reset)" bitfld.long 0x0 11. "MPUSEC,Secure state of the MPU sub-system clock" "0: non-secure,1: secure (default after reset)" newline bitfld.long 0x0 10. "PLL4SEC,Secure state of the PLL4 clock" "0: non-secure,1: secure (default after reset)" bitfld.long 0x0 9. "PLL3SEC,Secure state of the PLL3 clock" "0: non-secure,1: secure (default after reset)" newline bitfld.long 0x0 8. "PLL12SEC,Secure state of the PLL1 and PLL2 clocks" "0: non-secure,1: secure (default after reset)" bitfld.long 0x0 4. "LSESEC,Secure state of the LSE clock" "0: non-secure,1: secure (default after reset)" newline bitfld.long 0x0 3. "LSISEC,Secure state of the LSI clock" "0: non-secure,1: secure (default after reset)" bitfld.long 0x0 2. "HSESEC,Secure state of the HSE clock" "0: non-secure,1: secure (default after reset)" newline bitfld.long 0x0 1. "CSISEC,Secure state of the CSI clock" "0: non-secure,1: secure (default after reset)" bitfld.long 0x0 0. "HSISEC,Secure state of the HSI clock" "0: non-secure,1: secure (default after reset)" group.long 0x100++0xB line.long 0x0 "RCC_MP_SREQSETR,RCC stop request set register" bitfld.long 0x0 0. "STPREQ_P0,Stop request from MPU processor" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' sets the STPREQ_P0 bit reading '1'.." line.long 0x4 "RCC_MP_SREQCLRR,RCC stop request clear register" bitfld.long 0x4 0. "STPREQ_P0,Stop request from MPU processor" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' clears the STPREQ_P0 bit reading '1'.." line.long 0x8 "RCC_MP_APRSTCR,RCC application reset control register" hexmask.long.byte 0x8 8.--14. 1. "RSTTO,Reset timeout delay adjust" bitfld.long 0x8 0. "RDCTLEN,Reset delay control enable" "0: The RDCTL control block is bypassed (default..,1: The RDCTL control block is enabled." rgroup.long 0x10C++0x3 line.long 0x0 "RCC_MP_APRSTSR,RCC application reset status register" hexmask.long.byte 0x0 8.--14. 1. "RSTTOV,Reset timeout delay value" group.long 0x110++0x1B line.long 0x0 "RCC_PWRLPDLYCR,RCC low-power Stop modes delay control register" hexmask.long.tbyte 0x0 0.--21. 1. "PWRLP_DLY,PWRLP_TEMPO value" line.long 0x4 "RCC_MP_GRSTCSETR,RCC global reset control set register" bitfld.long 0x4 4. "MPUP0RST,MPU processor reset" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' generates a reset of the MPU.." bitfld.long 0x4 0. "MPSYSRST,System reset" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' generates a system reset see Figure 3." line.long 0x8 "RCC_BR_RSTSCLRR,RCC BOOTROM reset status clear register" bitfld.long 0x8 13. "MPUP0RSTF,MPU processor reset flag" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' clears the MPUP0RSTF flag reading.." bitfld.long 0x8 9. "IWDG2RSTF,IWDG2 reset flag" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' clears the IWDG2RSTF flag reading.." newline bitfld.long 0x8 8. "IWDG1RSTF,IWDG1 reset flag" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' clears the IWDG1RSTF flag reading.." bitfld.long 0x8 6. "MPSYSRSTF,MPU System reset flag" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' clears the MPSYSRSTF flag reading.." newline bitfld.long 0x8 5. "VCPURSTF,VDDCPU reset flag" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' clears the VCPURSTF flag reading '1'.." bitfld.long 0x8 4. "VCORERSTF,VDDCORE reset flag" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' clears the VCORERSTF flag reading.." newline bitfld.long 0x8 3. "HCSSRSTF,HSE CSS reset flag" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' clears the HCSSRSTF flag reading '1'.." bitfld.long 0x8 2. "PADRSTF,NRST reset flag" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' clears the PADRSTF flag reading '1'.." newline bitfld.long 0x8 1. "BORRSTF,BOR reset flag" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' clears the BORRSTF flag reading '1'.." bitfld.long 0x8 0. "PORRSTF,POR/PDR reset flag" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' clears the PORRSTF flag reading '1'.." line.long 0xC "RCC_MP_RSTSSETR,RCC reset status set register" bitfld.long 0xC 15. "SPARE,Spare bit" "0,1" bitfld.long 0xC 13. "MPUP0RSTF,MPU processor reset flag" "0: No MPU processor reset occurred (default after..,1: MPU processor reset occurred" newline bitfld.long 0xC 12. "CSTDBYRSTF,MPU CStandby reset flag" "0: MPU has not been in CStandby,1: MPU has been in CStandby" bitfld.long 0xC 11. "STDBYRSTF,System Standby reset flag" "0: System has not been in Standby mode,1: System has been in Standby mode" newline bitfld.long 0xC 10. "STP2RSTF,Stop2 reset flag" "0: System has not been in Stop2 mode,1: System has been in Stop2 mode" bitfld.long 0xC 9. "IWDG2RSTF,IWDG2 reset flag" "0: No IWDG2 reset occurred,1: An IWDG2 reset occurred" newline bitfld.long 0xC 8. "IWDG1RSTF,IWDG1 reset flag" "0: No IWDG1 reset occurred,1: An IWDG1 reset occurred" bitfld.long 0xC 6. "MPSYSRSTF,MPU System reset flag" "0: No system reset generated by the MPU occurred,1: A system reset generated by the MPU occurred" newline bitfld.long 0xC 5. "VCPURSTF,VCPU reset flag" "0: VCPU is not the origin of the reset,1: VCPU is the origin of the reset" bitfld.long 0xC 4. "VCORERSTF,VDDCORE reset flag" "0: VDDCORE is not the origin of the reset,1: VDDCORE is the origin of the reset" newline bitfld.long 0xC 3. "HCSSRSTF,HSE CSS reset flag" "0: No HSE CSS reset occurred,1: A HSE CSS reset occurred" bitfld.long 0xC 2. "PADRSTF,NRST reset flag" "0: No PAD reset occurred,1: A PAD reset occurred" newline bitfld.long 0xC 1. "BORRSTF,BOR reset flag" "0: No BOR reset occurred,1: A BOR reset occurred" bitfld.long 0xC 0. "PORRSTF,POR/PDR reset flag" "0: No POR/PDR reset occurred,1: A POR/PDR reset occurred" line.long 0x10 "RCC_MP_RSTSCLRR,RCC reset status clear register" bitfld.long 0x10 15. "SPARE,Spare bit" "0,1" bitfld.long 0x10 13. "MPUP0RSTF,MPU processor reset flag" "0: No MPU processor reset occurred (default after..,1: MPU processor reset occurred" newline bitfld.long 0x10 12. "CSTDBYRSTF,MPU CStandby reset flag" "0: MPU has not been in CStandby mode,1: MPU has been in CStandby mode" bitfld.long 0x10 11. "STDBYRSTF,System Standby reset flag" "0: System has not been in Standby mode,1: System has been in Standby mode" newline bitfld.long 0x10 10. "STP2RSTF,Stop2 reset flag" "0: System has not been in Stop2 mode,1: System has been in Stop2 mode" bitfld.long 0x10 9. "IWDG2RSTF,IWDG2 reset flag" "0: No IWDG2 reset occurred,1: An IWDG2 reset occurred" newline bitfld.long 0x10 8. "IWDG1RSTF,IWDG1 reset flag" "0: No IWDG1 reset occurred,1: An IWDG1 reset occurred" bitfld.long 0x10 6. "MPSYSRSTF,MPU System reset flag" "0: No system reset generated by the MPU occurred,1: A system reset generated by the MPU occurred" newline bitfld.long 0x10 5. "VCPURSTF,VDDCPU reset flag" "0: VDDCPU is not the origin of the reset,1: VDDCPU is the origin of the reset" bitfld.long 0x10 4. "VCORERSTF,VDDCORE reset flag" "0: VDDCORE is not the origin of the reset,1: VDDCORE is the origin of the reset" newline bitfld.long 0x10 3. "HCSSRSTF,HSE CSS reset flag" "0: No HSE CSS reset occurred,1: A HSE CSS reset occurred" bitfld.long 0x10 2. "PADRSTF,NRST reset flag" "0: No PAD reset occurred,1: A PAD reset occurred" newline bitfld.long 0x10 1. "BORRSTF,BOR reset flag" "0: No BOR reset occurred,1: A BOR reset occurred" bitfld.long 0x10 0. "PORRSTF,POR/PDR reset flag" "0: No POR/PDR reset occurred,1: A POR/PDR reset occurred" line.long 0x14 "RCC_MP_IWDGFZSETR,RCC IWDG clock freeze set register" bitfld.long 0x14 1. "FZ_IWDG2,Freeze the IWDG2 clock" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' freeze the IWDG2 clock reading '1'.." bitfld.long 0x14 0. "FZ_IWDG1,Freeze the IWDG1 clock" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' freeze the IWDG1 clock reading '1'.." line.long 0x18 "RCC_MP_IWDGFZCLRR,RCC IWDG clock freeze clear register" bitfld.long 0x18 1. "FZ_IWDG2,Unfreeze the IWDG2 clock" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' unfreeze the IWDG2 clock reading '1'.." bitfld.long 0x18 0. "FZ_IWDG1,Unfreeze the IWDG1 clock" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' unfreeze the IWDG1 clock reading '1'.." group.long 0x200++0x7 line.long 0x0 "RCC_MP_CIER,RCC clock source interrupt enable register" bitfld.long 0x0 20. "WKUPIE,Wake up from CStop Interrupt Enable" "0: Wakeup interrupt disabled (default after reset),1: Wakeup interrupt enabled" bitfld.long 0x0 16. "LSECSSIE,LSE clock security system Interrupt Enable" "0: LSE CSS interrupt disabled (default after reset),1: LSE CSS interrupt enabled" newline bitfld.long 0x0 11. "PLL4DYIE,PLL4 ready Interrupt Enable" "0: PLL4 lock interrupt disabled (default after reset),1: PLL4 lock interrupt enabled" bitfld.long 0x0 10. "PLL3DYIE,PLL3 ready Interrupt Enable" "0: PLL3 lock interrupt disabled (default after reset),1: PLL3 lock interrupt enabled" newline bitfld.long 0x0 9. "PLL2DYIE,PLL2 ready Interrupt Enable" "0: PLL2 lock interrupt disabled (default after reset),1: PLL2 lock interrupt enabled" bitfld.long 0x0 8. "PLL1DYIE,PLL1 ready Interrupt Enable" "0: PLL1 lock interrupt disabled (default after reset),1: PLL1 lock interrupt enabled" newline bitfld.long 0x0 4. "CSIRDYIE,CSI ready Interrupt Enable" "0: CSI ready interrupt disabled (default after reset),1: CSI ready interrupt enabled" bitfld.long 0x0 3. "HSERDYIE,HSE ready Interrupt Enable" "0: HSE ready interrupt disabled (default after reset),1: HSE ready interrupt enabled" newline bitfld.long 0x0 2. "HSIRDYIE,HSI ready Interrupt Enable" "0: HSI ready interrupt disabled (default after reset),1: HSI ready interrupt enabled" bitfld.long 0x0 1. "LSERDYIE,LSE ready Interrupt Enable" "0: LSE ready interrupt disabled (default after reset),1: LSE ready interrupt enabled" newline bitfld.long 0x0 0. "LSIRDYIE,LSI ready Interrupt Enable" "0: LSI ready interrupt disabled (default after reset),1: LSI ready interrupt enabled" line.long 0x4 "RCC_MP_CIFR,RCC clock source interrupt flag register" bitfld.long 0x4 20. "WKUPF,Wake up from CStop Interrupt Flag" "0: No wakeup interrupt pending (default after reset),1: Wakeup interrupt pending writing '1' clears this.." bitfld.long 0x4 16. "LSECSSF,LSE clock security system Interrupt Flag" "0: No failure detected on the external 32 kHz..,1: A failure is detected on the external 32 kHz.." newline bitfld.long 0x4 11. "PLL4DYF,PLL4 ready Interrupt Flag" "0: No clock ready interrupt caused by PLL4 lock..,1: Clock ready interrupt caused by PLL4 lock.." bitfld.long 0x4 10. "PLL3DYF,PLL3 ready Interrupt Flag" "0: No clock ready interrupt caused by PLL3 lock..,1: Clock ready interrupt caused by PLL3 lock.." newline bitfld.long 0x4 9. "PLL2DYF,PLL2 ready Interrupt Flag" "0: No clock ready interrupt caused by PLL2 lock..,1: Clock ready interrupt caused by PLL2 lock.." bitfld.long 0x4 8. "PLL1DYF,PLL1 ready Interrupt Flag" "0: No clock ready interrupt caused by PLL1 lock..,1: Clock ready interrupt caused by PLL1 lock.." newline bitfld.long 0x4 4. "CSIRDYF,CSI ready Interrupt Flag" "0: No clock ready interrupt caused by the CSI..,1: Clock ready interrupt caused by the CSI writing.." bitfld.long 0x4 3. "HSERDYF,HSE ready Interrupt Flag" "0: No clock ready interrupt caused by the HSE..,1: Clock ready interrupt caused by the HSE writing.." newline bitfld.long 0x4 2. "HSIRDYF,HSI ready Interrupt Flag" "0: No clock ready interrupt caused by the HSI..,1: Clock ready interrupt caused by the HSI writing.." bitfld.long 0x4 1. "LSERDYF,LSE ready Interrupt Flag" "0: No clock ready interrupt caused by the LSE..,1: Clock ready interrupt caused by the LSE writing.." newline bitfld.long 0x4 0. "LSIRDYF,LSI ready Interrupt Flag" "0: No clock ready interrupt caused by the LSI..,1: Clock ready interrupt caused by the LSI writing.." group.long 0x400++0x7 line.long 0x0 "RCC_BDCR,RCC backup domain control register" bitfld.long 0x0 31. "VSWRST,VSW domain software reset" "0: write: release the software reset; read:..,1: write: reset the entire VSW domain; read:.." bitfld.long 0x0 20. "RTCCKEN,RTC clock enable" "0: rtc_ck clock is disabled (default after backup..,1: rtc_ck clock enabled" newline bitfld.long 0x0 16.--17. "RTCSRC,RTC clock source selection" "0: No clock (default after backup domain reset),1: LSE clock used as RTC clock,2: LSI clock used as RTC clock,3: HSE clock divided by RTCDIV value is used as RTC.." rbitfld.long 0x0 9. "LSECSSD,LSE clock security system failure detection" "0: No failure detected on 32 kHz oscillator..,1: Failure detected on 32 kHz oscillator" newline bitfld.long 0x0 8. "LSECSSON,LSE clock security system enable" "0: Clock Security System on 32 kHz oscillator OFF..,1: Clock Security System on 32 kHz oscillator ON" bitfld.long 0x0 4.--5. "LSEDRV,LSE oscillator driving capability" "0: Lowest drive,1: Medium low drive,2: Medium high drive (default after backup domain..,3: Highest drive" newline bitfld.long 0x0 3. "DIGBYP,LSE digital bypass" "0: The LSE is in analog bypass mode (default after..,1: The LSE is in digital bypass mode" rbitfld.long 0x0 2. "LSERDY,LSE oscillator ready" "0: LSE oscillator not ready (default after backup..,1: LSE oscillator ready" newline bitfld.long 0x0 1. "LSEBYP,LSE oscillator bypass" "0: LSE oscillator not bypassed (default after..,1: LSE oscillator bypassed" bitfld.long 0x0 0. "LSEON,LSE oscillator enabled" "0: LSE oscillator OFF (default after backup domain..,1: LSE oscillator ON" line.long 0x4 "RCC_RDLSICR,RCC reset duration and LSI control register" hexmask.long.byte 0x4 27.--31. 1. "SPARE,Spare bits" bitfld.long 0x4 24.--26. "EADLY,External access delays" "0: 10 ms (default after reset),1: No extra delay added by the BOOTROM,2: 100 us,3: 200 us,4: 500 us,5: 1 ms,6: 2 ms,7: 5 ms" newline hexmask.long.byte 0x4 16.--20. 1. "MRD,Minimum reset duration" rbitfld.long 0x4 1. "LSIRDY,LSI oscillator ready" "0: LSI oscillator not ready (default after reset),1: LSI oscillator ready" newline bitfld.long 0x4 0. "LSION,LSI oscillator enabled" "0: LSI oscillator is OFF if no other requester..,1: LSI oscillator ON" group.long 0x420++0x7 line.long 0x0 "RCC_OCENSETR,RCC oscillator clock enable set register" bitfld.long 0x0 11. "HSECSSON,Set the HSECSSON bit" "0: Reading '0' means that the Clock Security System..,1: Writing '1' enables the Clock Security System on.." bitfld.long 0x0 10. "HSEBYP,Set HSEBYP bit" "0: No effect,1: Set the HSEBYP bit" newline bitfld.long 0x0 9. "HSEKERON,Set HSEKERON bit" "0: No effect,1: Set the HSEKERON bit" bitfld.long 0x0 8. "HSEON,Set HSEON bit" "0: No effect,1: Set HSEON bit" newline bitfld.long 0x0 7. "DIGBYP,Set DIGBYP bit" "0: No effect,1: Set DIGBYP bit (digital bypass)" bitfld.long 0x0 5. "CSIKERON,Set CSIKERON bit" "0: No effect,1: Set the CSIKERON bit" newline bitfld.long 0x0 4. "CSION,Set CSION bit" "0: No effect,1: Set the CSION bit" bitfld.long 0x0 1. "HSIKERON,Set HSIKERON bit" "0: No effect,1: Set the HSIKERON bit" newline bitfld.long 0x0 0. "HSION,Set HSION bit" "0: No effect,1: Set the HSION bit" line.long 0x4 "RCC_OCENCLRR,RCC oscillator clock enable clear register" bitfld.long 0x4 10. "HSEBYP,Clear the HSEBYP bit" "0: No effect,1: Clear the HSEBYP bit" bitfld.long 0x4 9. "HSEKERON,Clear HSEKERON bit" "0: No effect,1: Clear the HSEKERON bit" newline bitfld.long 0x4 8. "HSEON,Clear of HSEON bit" "0: No effect,1: Clear the HSEON bit" bitfld.long 0x4 7. "DIGBYP,Clear of DIGBYP bit" "0: No effect,1: Clear the DIGBYP bit (analog bypass)" newline bitfld.long 0x4 5. "CSIKERON,Clear of CSIKERON bit" "0: No effect,1: Clear the CSIKERON bit" bitfld.long 0x4 4. "CSION,Clear of CSION bit" "0: CSI is OFF,1: Clear the CSION bit" newline bitfld.long 0x4 1. "HSIKERON,Clear of HSIKERON bit" "0: No effect,1: Clear the HSIKERON bit" bitfld.long 0x4 0. "HSION,Clear of HSION bit" "0: No effect,1: Clear the HSION bit" rgroup.long 0x428++0x3 line.long 0x0 "RCC_OCRDYR,RCC oscillators and MPU and AXI clock ready register" bitfld.long 0x0 24. "AXICKRDY,AXI sub-system clock ready flag" "0: axiss_ck clock is not available (default after..,1: axiss_ck clock is available" bitfld.long 0x0 23. "MPUCKRDY,MPU clock ready flag" "0: mpuss_ck clock is not available (default after..,1: mpuss_ck clock is available" newline bitfld.long 0x0 8. "HSERDY,HSE clock ready flag" "0: HSE clock is not ready (default after reset),1: HSE clock is ready" bitfld.long 0x0 4. "CSIRDY,CSI clock ready flag" "0: CSI clock is not ready (default after reset),1: CSI clock is ready" newline bitfld.long 0x0 2. "HSIDIVRDY,HSI divider ready flag" "0: the new division ratio is not yet propagated to..,1: the hsi_ck (hsi_ker_ck) clock frequency reflects.." bitfld.long 0x0 0. "HSIRDY,HSI clock ready flag" "0: HSI clock is not ready (default after reset),1: HSI clock is ready" group.long 0x440++0x7 line.long 0x0 "RCC_HSICFGR,RCC HSI configuration register" hexmask.long.word 0x0 16.--27. 1. "HSICAL,HSI clock calibration" hexmask.long.byte 0x0 8.--14. 1. "HSITRIM,HSI clock trimming" newline bitfld.long 0x0 0.--1. "HSIDIV,HSI clock divider" "0: Division by 1 hsi_ck (hsi_ker_ck) = 64 MHz..,1: Division by 2 hsi_ck (hsi_ker_ck) = 32 MHz,2: Division by 4 hsi_ck (hsi_ker_ck) = 16 MHz,3: Division by 8 hsi_ck (hsi_ker_ck) = 8 MHz" line.long 0x4 "RCC_CSICFGR,RCC CSI configuration register" hexmask.long.byte 0x4 16.--23. 1. "CSICAL,CSI clock calibration" hexmask.long.byte 0x4 8.--12. 1. "CSITRIM,CSI clock trimming" group.long 0x460++0xB line.long 0x0 "RCC_MCO1CFGR,RCC MCO1 configuration register" bitfld.long 0x0 12. "MCO1ON,Control of the MCO1 output" "0: The MCO1 output is disabled,1: The MCO1 output is enabled" hexmask.long.byte 0x0 4.--7. 1. "MCO1DIV,MCO1 prescaler" newline bitfld.long 0x0 0.--2. "MCO1SEL,MCO1 clock output selection" "0: HSI clock selected (hsi_ck) (default after reset),1: HSE clock selected (hse_ck),2: CSI clock selected (csi_ck),3: LSI clock selected (lsi_ck),4: LSE oscillator clock selected (lse_ck),?,?,?" line.long 0x4 "RCC_MCO2CFGR,RCC MCO2 configuration register" bitfld.long 0x4 12. "MCO2ON,Control of the MCO2 output" "0: The MCO2 output is disabled,1: The MCO2 output is enabled" hexmask.long.byte 0x4 4.--7. 1. "MCO2DIV,MCO2 prescaler" newline bitfld.long 0x4 0.--2. "MCO2SEL,Micro-controller clock output 2" "0: MPU clock selected (mpuss_ck) (default after..,1: AXI clock selected (axiss_ck),2: MLAHB clock selected (mlahbss_ck),3: PLL4 clock selected (pll4_p_ck),4: HSE clock selected (hse_ck),5: HSI clock selected (hsi_ck),?,?" line.long 0x8 "RCC_DBGCFGR,RCC debug configuration register" bitfld.long 0x8 12. "DBGRST,Reset of the debug function" "0: The trace and debug parts are not reset.,1: The trace and debug parts are under reset." bitfld.long 0x8 9. "TRACECKEN,Clock enable for trace function" "0: The clock for the trace function is disabled..,1: The clock for the trace function is enabled" newline bitfld.long 0x8 8. "DBGCKEN,Clock enable for debug function" "0: The enabling of the clock for the debug function..,1: The clock for the debug function is enabled" bitfld.long 0x8 0.--2. "TRACEDIV,Clock divider for the trace clock (ck_trace)" "0: aclk,1: aclk / 2 (default after reset),2: aclk / 4,3: aclk / 8,?,?,?,?" group.long 0x480++0xB line.long 0x0 "RCC_RCK12SELR,RCC PLL1 and PLL2 reference clock selection register" rbitfld.long 0x0 31. "PLL12SRCRDY,PLL12 source clock switch status" "0: The PLL12 switch is not ready or in position..,1: The PLL12 switch is ready: the clock switch is.." bitfld.long 0x0 0.--1. "PLL12SRC,Source clock selection for PLL12" "0: HSI selected as PLL12 clock (hsi_ck) (default..,1: HSE selected as PLL12 clock (hse_ck),?,?" line.long 0x4 "RCC_RCK3SELR,RCC PLL3 reference clock selection register" rbitfld.long 0x4 31. "PLL3SRCRDY,PLL3 source clock switch status" "0: The PLL3 switch is not ready or in position..,1: The PLL3 switch is ready: the clock switch is.." bitfld.long 0x4 0.--1. "PLL3SRC,Source clock selection for PLL3" "0: HSI selected as PLL clock (hsi_ck) (default..,1: HSE selected as PLL clock (hse_ck),2: CSI selected as PLL clock (csi_ck),3: No clock send to DIVM3 divider and PLL3" line.long 0x8 "RCC_RCK4SELR,RCC PLL4 reference clock selection register" rbitfld.long 0x8 31. "PLL4SRCRDY,PLL4 source clock switch status" "0: The PLL4 switch is not ready or in position..,1: The PLL4 switch is ready: the clock switch is.." bitfld.long 0x8 0.--1. "PLL4SRC,Source clock selection for PLL4" "0: HSI selected as PLL clock (hsi_ck) (default..,1: HSE selected as PLL clock (hse_ck),2: CSI selected as PLL clock (csi_ck),3: Signal I2S_CKIN used as source clock" group.long 0x4A0++0x13 line.long 0x0 "RCC_PLL1CR,RCC PLL1 control register" bitfld.long 0x0 6. "DIVREN,PLL1 DIVR divider output enable" "0: pll1_r_ck output is disabled (default after reset),1: pll1_r_ck output is enabled" bitfld.long 0x0 5. "DIVQEN,PLL1 DIVQ divider output enable" "0: pll1_q_ck output is disabled (default after reset),1: pll1_q_ck output is enabled" newline bitfld.long 0x0 4. "DIVPEN,PLL1 DIVP divider output enable" "0: pll1_p_ck output is disabled (default after reset),1: pll1_p_ck output is enabled" bitfld.long 0x0 2. "SSCG_CTRL,Spread Spectrum Clock Generator of PLL1 enable" "0: Clock Spreading Generator disabled (default..,1: Clock Spreading Generator enabled" newline rbitfld.long 0x0 1. "PLL1RDY,PLL1 clock ready flag" "0: PLL1 unlocked (default after reset),1: PLL1 locked" bitfld.long 0x0 0. "PLLON,PLL1 enable." "0: PLL1 OFF (default after reset),1: PLL1 is ON and ref1_ck is provided to the PLL1" line.long 0x4 "RCC_PLL1CFGR1,RCC PLL1 configuration register 1" hexmask.long.byte 0x4 16.--21. 1. "DIVM1,Prescaler for PLL1" hexmask.long.word 0x4 0.--8. 1. "DIVN,Multiplication factor for PLL1 VCO" line.long 0x8 "RCC_PLL1CFGR2,RCC PLL1 configuration register 2" hexmask.long.byte 0x8 16.--22. 1. "DIVR,PLL1 DIVR division factor" hexmask.long.byte 0x8 8.--14. 1. "DIVQ,PLL1 DIVQ division factor" newline hexmask.long.byte 0x8 0.--6. 1. "DIVP,PLL1 DIVP division factor" line.long 0xC "RCC_PLL1FRACR,RCC PLL1 fractional register" bitfld.long 0xC 16. "FRACLE,PLL1 fractional latch enable" "?,1: the transition 0 to '1' transfers the content of.." hexmask.long.word 0xC 3.--15. 1. "FRACV,Fractional part of the multiplication factor for PLL1 VCO" line.long 0x10 "RCC_PLL1CSGR,RCC PLL1 clock spreading generator register" hexmask.long.word 0x10 16.--30. 1. "INC_STEP,Modulation Depth Adjustment for PLL1" bitfld.long 0x10 15. "SSCG_MODE,Spread spectrum clock generator mode" "0: Center-spread modulation selected (default after..,1: Down-spread modulation selected" newline bitfld.long 0x10 14. "RPDFN_DIS,Dithering RPDF noise control" "0: Dithering noise injection enabled (default after..,1: Dithering noise injection disabled" bitfld.long 0x10 13. "TPDFN_DIS,Dithering TPDF noise control" "0: Dithering noise injection enabled (default after..,1: Dithering noise injection disabled" newline hexmask.long.word 0x10 0.--12. 1. "MOD_PER,Modulation Period Adjustment for PLL1" group.long 0x4D0++0x13 line.long 0x0 "RCC_PLL2CR,RCC PLL2 control register" bitfld.long 0x0 6. "DIVREN,PLL2 DIVR divider output enable" "0: pll2_r_ck output is disabled (default after reset),1: pll2_r_ck output is enabled" bitfld.long 0x0 5. "DIVQEN,PLL2 DIVQ divider output enable" "0: pll2_q_ck output is disabled (default after reset),1: pll2_q_ck output is enabled" newline bitfld.long 0x0 4. "DIVPEN,PLL2 DIVP divider output enable" "0: pll2_p_ck output is disabled (default after reset),1: pll2_p_ck output is enabled" bitfld.long 0x0 2. "SSCG_CTRL,Clock Spreading Generator of PLL2 enable" "0: Clock Spreading Generator disabled (default..,1: Clock Spreading Generator enabled" newline rbitfld.long 0x0 1. "PLL2RDY,PLL2 clock ready flag" "0: PLL2 unlocked (default after reset),1: PLL2 locked" bitfld.long 0x0 0. "PLLON,PLL2 enable" "0: PLL2 OFF (default after reset),1: PLL2 ON and ref2_ck is provided to the PLL2" line.long 0x4 "RCC_PLL2CFGR1,RCC PLL2 configuration register 1" hexmask.long.byte 0x4 16.--21. 1. "DIVM2,Prescaler for PLL2" hexmask.long.word 0x4 0.--8. 1. "DIVN,Multiplication factor for PLL2 VCO" line.long 0x8 "RCC_PLL2CFGR2,RCC PLL2 configuration register 2" hexmask.long.byte 0x8 16.--22. 1. "DIVR,PLL2 DIVR division factor" hexmask.long.byte 0x8 8.--14. 1. "DIVQ,PLL2 DIVQ division factor" newline hexmask.long.byte 0x8 0.--6. 1. "DIVP,PLL2 DIVP division factor" line.long 0xC "RCC_PLL2FRACR,RCC PLL2 fractional register" bitfld.long 0xC 16. "FRACLE,PLL2 fractional latch enable" "?,1: the transition 0 to '1' transfers the content of.." hexmask.long.word 0xC 3.--15. 1. "FRACV,Fractional part of the multiplication factor for PLL2 VCO" line.long 0x10 "RCC_PLL2CSGR,RCC PLL2 clock spreading generator register" hexmask.long.word 0x10 16.--30. 1. "INC_STEP,Modulation Depth Adjustment for PLL2" bitfld.long 0x10 15. "SSCG_MODE,Spread spectrum clock generator mode" "0: Center-spread modulation selected (default after..,1: Down-spread modulation selected" newline bitfld.long 0x10 14. "RPDFN_DIS,Dithering RPDF noise control" "0: Dithering noise injection enabled (default after..,1: Dithering noise injection disabled" bitfld.long 0x10 13. "TPDFN_DIS,Dithering TPDF noise control" "0: Dithering noise injection enabled (default after..,1: Dithering noise injection disabled" newline hexmask.long.word 0x10 0.--12. 1. "MOD_PER,Modulation Period Adjustment for PLL2" group.long 0x500++0x13 line.long 0x0 "RCC_PLL3CR,RCC PLL3 control register" bitfld.long 0x0 6. "DIVREN,PLL3 DIVR divider output enable" "0: pll3_r_ck output is disabled (default after reset),1: pll3_r_ck output is enabled" bitfld.long 0x0 5. "DIVQEN,PLL3 DIVQ divider output enable" "0: pll3_q_ck output is disabled (default after reset),1: pll3_q_ck output is enabled" newline bitfld.long 0x0 4. "DIVPEN,PLL3 DIVP divider output enable" "0: pll3_p_ck output is disabled (default after reset),1: pll3_p_ck output is enabled" bitfld.long 0x0 2. "SSCG_CTRL,Clock Spreading Generator of PLL3 enable" "0: Clock Spreading Generator disabled (default..,1: Clock Spreading Generator enabled" newline rbitfld.long 0x0 1. "PLL3RDY,PLL3 clock ready flag" "0: PLL3 unlocked (default after reset),1: PLL3 locked" bitfld.long 0x0 0. "PLLON,PLL3 enable" "0: PLL3 OFF (default after reset),1: PLL3 ON and ref3_ck is provided to the PLL3" line.long 0x4 "RCC_PLL3CFGR1,RCC PLL3 configuration register 1" bitfld.long 0x4 24.--25. "IFRGE,PLL3 input frequency range" "0,1,2,3" hexmask.long.byte 0x4 16.--21. 1. "DIVM3,Prescaler for PLL3" newline hexmask.long.word 0x4 0.--8. 1. "DIVN,Multiplication factor for PLL3 VCO" line.long 0x8 "RCC_PLL3CFGR2,RCC PLL3 configuration register 2" hexmask.long.byte 0x8 16.--22. 1. "DIVR,PLL3 DIVR division factor" hexmask.long.byte 0x8 8.--14. 1. "DIVQ,PLL3 DIVQ division factor" newline hexmask.long.byte 0x8 0.--6. 1. "DIVP,PLL3 DIVP division factor" line.long 0xC "RCC_PLL3FRACR,RCC PLL3 Fractional register" bitfld.long 0xC 16. "FRACLE,PLL3 fractional latch enable" "?,1: the transition 0 to '1' transfers the content of.." hexmask.long.word 0xC 3.--15. 1. "FRACV,Fractional part of the multiplication factor for PLL3 VCO" line.long 0x10 "RCC_PLL3CSGR,RCC PLL3 clock spreading generator register" hexmask.long.word 0x10 16.--30. 1. "INC_STEP,Modulation Depth Adjustment for PLL3" bitfld.long 0x10 15. "SSCG_MODE,Spread spectrum clock generator mode" "0: Center-spread modulation selected (default after..,1: Down-spread modulation selected" newline bitfld.long 0x10 14. "RPDFN_DIS,Dithering RPDF noise control" "0: Dithering noise injection enabled (default after..,1: Dithering noise injection disabled" bitfld.long 0x10 13. "TPDFN_DIS,Dithering TPDF noise control" "0: Dithering noise injection enabled (default after..,1: Dithering noise injection disabled" newline hexmask.long.word 0x10 0.--12. 1. "MOD_PER,Modulation Period Adjustment for PLL3" group.long 0x520++0x13 line.long 0x0 "RCC_PLL4CR,RCC PLL4 control register" bitfld.long 0x0 6. "DIVREN,PLL4 DIVR divider output enable" "0: pll4_r_ck output is disabled (default after reset),1: pll4_r_ck output is enabled" bitfld.long 0x0 5. "DIVQEN,PLL4 DIVQ divider output enable" "0: pll4_q_ck output is disabled (default after reset),1: pll4_q_ck output is enabled" newline bitfld.long 0x0 4. "DIVPEN,PLL4 DIVP divider output enable" "0: pll4_p_ck output is disabled (default after reset),1: pll4_p_ck output is enabled" bitfld.long 0x0 2. "SSCG_CTRL,Clock Spreading Generator of PLL4 enable" "0: Clock Spreading Generator disabled (default..,1: Clock Spreading Generator enabled" newline rbitfld.long 0x0 1. "PLL4RDY,PLL4 clock ready flag" "0: PLL4 unlocked (default after reset),1: PLL4 locked" bitfld.long 0x0 0. "PLLON,PLL4 enable" "0: PLL4 OFF (default after reset),1: PLL4 ON and ref4_ck is provided to the PLL4" line.long 0x4 "RCC_PLL4CFGR1,RCC PLL4 configuration register 1" bitfld.long 0x4 24.--25. "IFRGE,PLL4 input frequency range" "0,1,2,3" hexmask.long.byte 0x4 16.--21. 1. "DIVM4,Prescaler for PLL4" newline hexmask.long.word 0x4 0.--8. 1. "DIVN,Multiplication factor for PLL4 VCO" line.long 0x8 "RCC_PLL4CFGR2,RCC PLL4 configuration register 2" hexmask.long.byte 0x8 16.--22. 1. "DIVR,PLL4 DIVR division factor" hexmask.long.byte 0x8 8.--14. 1. "DIVQ,PLL4 DIVQ division factor" newline hexmask.long.byte 0x8 0.--6. 1. "DIVP,PLL4 DIVP division factor" line.long 0xC "RCC_PLL4FRACR,RCC PLL4 fractional register" bitfld.long 0xC 16. "FRACLE,PLL4 fractional latch enable" "?,1: the transition 0 to '1' transfers the content of.." hexmask.long.word 0xC 3.--15. 1. "FRACV,Fractional part of the multiplication factor for PLL4 VCO" line.long 0x10 "RCC_PLL4CSGR,RCC PLL4 clock spreading generator register" hexmask.long.word 0x10 16.--30. 1. "INC_STEP,Modulation Depth Adjustment for PLL4" bitfld.long 0x10 15. "SSCG_MODE,Spread spectrum clock generator mode" "0: Center-spread modulation selected (default after..,1: Down-spread modulation selected" newline bitfld.long 0x10 14. "RPDFN_DIS,Dithering RPDF noise control" "0: Dithering noise injection enabled (default after..,1: Dithering noise injection disabled" bitfld.long 0x10 13. "TPDFN_DIS,Dithering TPDF noise control" "0: Dithering noise injection enabled (default after..,1: Dithering noise injection disabled" newline hexmask.long.word 0x10 0.--12. 1. "MOD_PER,Modulation Period Adjustment for PLL4" group.long 0x540++0xF line.long 0x0 "RCC_MPCKSELR,RCC MPU clock selection register" rbitfld.long 0x0 31. "MPUSRCRDY,MPU clock switch status" "0: The MPU switch is not ready: no clock is..,1: The MPU switch is ready: the clock switch is.." bitfld.long 0x0 0.--1. "MPUSRC,MPU clock switch" "0: HSI selected as MPU sub-system clock (hsi_ck)..,1: HSE selected as MPU sub-system clock (hse_ck),2: PLL1 selected as MPU sub-system clock (pll1_p_ck),3: divided PLL1 pll1_p_ck clock is selected as MPU.." line.long 0x4 "RCC_ASSCKSELR,RCC AXI sub-system clock selection register." rbitfld.long 0x4 31. "AXISSRCRDY,AXI sub-system clock switch status" "0: The AXI sub-system switch is not ready or in..,1: The AXI sub-system switch is ready: the clock.." bitfld.long 0x4 0.--2. "AXISSRC,AXI sub-system clock switch" "0: HSI selected as AXI sub-system clock (hsi_ck)..,1: HSE selected as AXI sub-system clock (hse_ck),2: PLL2 selected as AXI sub-system clock (pll2_p_ck),?,?,?,?,?" line.long 0x8 "RCC_MSSCKSELR,RCC MLAHB sub-system clock selection register" rbitfld.long 0x8 31. "MLAHBSSRCRDY,MLAHB sub-system clock switch status" "0: The MLAHB sub-system switch is not ready or in..,1: The MLAHB sub-system switch is ready: the clock.." bitfld.long 0x8 0.--1. "MLAHBSSRC,MLAHB sub-system clock switch" "0: HSI selected as MLAHB sub-system clock (hsi_ck)..,1: HSE selected as MLAHB sub-system clock (hse_ck),2: CSI selected as MLAHB sub-system clock (csi_ck),3: PLL3 selected as MLAHB sub-system clock.." line.long 0xC "RCC_CPERCKSELR,RCC common peripheral kernel clock selection register" bitfld.long 0xC 0.--1. "CKPERSRC,Oscillator selection for kernel clock" "0: hsi_ker_ck clock selected (default after reset),1: csi_ker_ck clock selected,2: hse_ker_ck clock selected,3: Clock disabled" group.long 0x560++0x27 line.long 0x0 "RCC_RTCDIVR,RCC RTC clock division register" hexmask.long.byte 0x0 0.--5. 1. "RTCDIV,HSE division factor for RTC clock" line.long 0x4 "RCC_MPCKDIVR,RCC MPU clock divider register" rbitfld.long 0x4 31. "MPUDIVRDY,MPU sub-system clock divider status" "0: The new division factor is not yet taken into..,1: The new division factor is taken into account." hexmask.long.byte 0x4 0.--3. 1. "MPUDIV,MPU Core clock divider" line.long 0x8 "RCC_AXIDIVR,RCC AXI clock divider register" rbitfld.long 0x8 31. "AXIDIVRDY,AXI sub-system clock divider status" "0: The new division factor is not yet taken into..,1: The new division factor is taken into account." bitfld.long 0x8 0.--2. "AXIDIV,AXI AHB5 and AHB6 clock divider" "0: axiss_ck (default after reset),1: axiss_ck / 2,2: axiss_ck / 3,?,?,?,?,?" line.long 0xC "RCC_MLAHBDIVR,RCC MLAHB clock divider register" rbitfld.long 0xC 31. "MLAHBDIVRDY,MLAHB clock prescaler status" "0: The new division factor is not yet taken into..,1: The new division factor is taken into account." hexmask.long.byte 0xC 0.--3. 1. "MLAHBDIV,MLAHB clock divider" line.long 0x10 "RCC_APB1DIVR,RCC APB1 clock divider register" rbitfld.long 0x10 31. "APB1DIVRDY,APB1 clock prescaler status" "0: The new division factor is not yet taken into..,1: The new division factor is taken into account." bitfld.long 0x10 0.--2. "APB1DIV,APB1 clock divider" "0: mlhclk (default after reset),1: mlhclk / 2,2: mlhclk / 4,3: mlhclk / 8,4: mlhclk / 16,?,?,?" line.long 0x14 "RCC_APB2DIVR,RCC APB2 clock divider register" rbitfld.long 0x14 31. "APB2DIVRDY,APB2 clock prescaler status" "0: The new division factor is not yet taken into..,1: The new division factor is taken into account." bitfld.long 0x14 0.--2. "APB2DIV,APB2 clock divider" "0: mlhclk (default after reset),1: mlhclk / 2,2: mlhclk / 4,3: mlhclk / 8,4: mlhclk / 16,?,?,?" line.long 0x18 "RCC_APB3DIVR,RCC APB3 clock divider register" rbitfld.long 0x18 31. "APB3DIVRDY,APB3 clock prescaler status" "0: The new division factor is not yet taken into..,1: The new division factor is taken into account." bitfld.long 0x18 0.--2. "APB3DIV,APB3 clock divider" "0: hclk (default after reset),1: hclk / 2,2: hclk / 4,3: hclk / 8,?,?,?,?" line.long 0x1C "RCC_APB4DIVR,RCC APB4 clock divider register." rbitfld.long 0x1C 31. "APB4DIVRDY,APB4 clock divider status" "0: The new division factor is not yet taken into..,1: The new division factor is taken into account." bitfld.long 0x1C 0.--2. "APB4DIV,APB4 clock divider" "0: aclk (default after reset),1: aclk / 2,2: aclk / 4,3: aclk / 8,?,?,?,?" line.long 0x20 "RCC_APB5DIVR,RCC APB5 clock divider register" rbitfld.long 0x20 31. "APB5DIVRDY,APB5 clock divider status" "0: The new division factor is not yet taken into..,1: The new division factor is taken into account." bitfld.long 0x20 0.--2. "APB5DIV,APB5 clock divider" "0: aclk (default after reset),1: aclk / 2,2: aclk / 4,3: aclk / 8,?,?,?,?" line.long 0x24 "RCC_APB6DIVR,RCC APB6 clock divider register" rbitfld.long 0x24 31. "APB6DIVRDY,APB6 clock divider status" "0: The new division factor is not yet taken into..,1: The new division factor is taken into account." bitfld.long 0x24 0.--2. "APB6DIV,APB6 clock divider" "0: aclk (default after reset),1: aclk / 2,2: aclk / 4,3: aclk / 8,?,?,?,?" group.long 0x5A0++0xB line.long 0x0 "RCC_TIMG1PRER,RCC APB1 timers group1 prescaler register." rbitfld.long 0x0 31. "TIMG1PRERDY,Timers clocks prescaler status" "0: The new division factor is not yet taken into..,1: The new division factor is taken into account.." bitfld.long 0x0 0. "TIMG1PRE,Timers clocks prescaler selection" "0: The Timers kernel clock is equal to mlhclk if..,1: The Timers kernel clock is equal to mlhclk if.." line.long 0x4 "RCC_TIMG2PRER,RCC APB2 timers group2 prescaler register" rbitfld.long 0x4 31. "TIMG2PRERDY,Timers clocks prescaler status" "0: The new division factor is not yet taken into..,1: The new division factor is taken into account.." bitfld.long 0x4 0. "TIMG2PRE,Timers clocks prescaler selection" "0: The Timers kernel clock is equal to mlhclk if..,1: The Timers kernel clock is equal to mlhclk if.." line.long 0x8 "RCC_TIMG3PRER,RCC APB6 timers group3 prescaler register" rbitfld.long 0x8 31. "TIMG3PRERDY,Timers clocks prescaler status" "0: The new division factor is not yet taken into..,1: The new division factor is taken into account.." bitfld.long 0x8 0. "TIMG3PRE,Timers clocks prescaler selection" "0: The Timers kernel clock is equal to mlhclk if..,1: The Timers kernel clock is equal to mlhclk if.." group.long 0x5C0++0x3 line.long 0x0 "RCC_DDRITFCR,RCC DDR interface control register" hexmask.long.byte 0x0 28.--31. 1. "GSKP_DUR,Glitch skipper duration in automatic mode" bitfld.long 0x0 25.--27. "DFILP_WIDTH,Minimum duration of low-power request command" "0: Bypass delay disabled,1: Forces a delay of 160 x Tdphy_ker_ck to be used..,2: Forces a delay of 224 x Tdphy_ker_ck to be used..,3: Forces a delay of 320 x Tdphy_ker_ck to be used..,4: Forces a delay of 416 x Tdphy_ker_ck to be used..,?,?,?" newline bitfld.long 0x0 24. "GSKPCTRL,Glitch skipper (GSKP) control" "0: The GSKP block is providing the clock phy_out_ck..,1: The GSKP block is providing the clock.." bitfld.long 0x0 23. "GSKPMOD,Glitch Skipper (GSKP) Mode" "0: The GSKP block is controlled by the GSKPCTRL bit,1: The GSKP block is controlled automatically by.." newline bitfld.long 0x0 20.--22. "DDRCKMOD,RCC mode for DDR clock control" "0: Normal mode: the gating of the dphy_ker_ck clock..,1: Automatic Self-Refresh mode (ASR1): the clock..,2: Hardware Self-Refresh mode (HSR1): the gating of..,?,?,5: Full Automatic Self-Refresh mode (ASR2): the..,6: Full Hardware Self-Refresh mode (HSR2): the..,?" bitfld.long 0x0 19. "DPHYCTLRST,DDRPHYC Control reset" "0: does not reset the DDRPHYC Control,1: reset the DDRPHYC Control" newline bitfld.long 0x0 18. "DPHYRST,DDRPHYC reset" "0: does not reset the DDRPHYC,1: reset the DDRPHYC" bitfld.long 0x0 17. "DPHYAPBRST,DDRPHYC APB interface reset" "0: does not reset the DDRPHYC APB interface,1: reset the DDRPHYC APB interface" newline bitfld.long 0x0 16. "DDRCORERST,DDRC core reset" "0: does not reset the DDRC core,1: reset the DDRC core" bitfld.long 0x0 15. "DDRCAXIRST,DDRC AXI interface reset" "0: does not reset the DDRC AXI interface,1: reset the DDRC AXI interface" newline bitfld.long 0x0 14. "DDRCAPBRST,DDRC APB interface reset" "0: does not reset the DDRC APB interface,1: reset the DDRC APB interface" bitfld.long 0x0 11.--13. "KERDCG_DLY,AXIDCG delay" "0: 1 period of ddrc_ker_ck between cactive_ddrc..,1: 3 periods of ddrc_ker_ck between cactive_ddrc..,?,?,?,?,?,7: 15 periods of ddrc_ker_ck between cactive_ddrc.." newline bitfld.long 0x0 10. "DDRPHYCAPBLPEN,DDRPHYC APB clock enable during CSleep mode" "0: means that the APB clock is disabled in CSleep,1: means that the APB clock is enabled in CSleep" bitfld.long 0x0 9. "DDRPHYCAPBEN,DDRPHYC APB clock enable" "0: means that the APB clock is disabled,1: means that the APB clock is enabled" newline bitfld.long 0x0 8. "AXIDCGEN,AXIDCG enable during MPU CRun mode" "0: means that the dynamic clock gating of..,1: means that the dynamic clock gating of.." bitfld.long 0x0 7. "DDRCAPBLPEN,DDRC APB clock enable during CSleep mode" "0: means that the APB clock is disabled in CSleep,1: means that the APB clock is enabled in CSleep" newline bitfld.long 0x0 6. "DDRCAPBEN,DDRC APB clock enable" "0: means that the APB clock is disabled,1: means that the APB clock is enabled" bitfld.long 0x0 5. "DDRPHYCLPEN,DDRPHYC peripheral clocks enable during CSleep mode" "0: means that the peripheral clocks are disabled in..,1: means that the peripheral clocks are enabled in.." newline bitfld.long 0x0 4. "DDRPHYCEN,DDRPHYC peripheral clocks enable" "0: means that the peripheral clocks are disabled,1: means that the peripheral clocks are enabled" bitfld.long 0x0 1. "DDRC1LPEN,DDRC port 1 peripheral clocks enable during CSleep mode" "0: means that the peripheral clocks are disabled in..,1: means that the peripheral clocks are enabled in.." newline bitfld.long 0x0 0. "DDRC1EN,DDRC port 1 peripheral clocks enable" "0: Means that the DDRC peripheral clocks are disabled,1: Means that the DDRC peripheral clocks are enabled" group.long 0x600++0x6B line.long 0x0 "RCC_I2C12CKSELR,RCC I2C1 and I2C2 kernel clock selection register" bitfld.long 0x0 0.--2. "I2C12SRC,I2C1 and I2C2 kernel clock source selection" "0: pclk1 clock selected as kernel peripheral clock..,1: pll4_r_ck clock selected as kernel peripheral..,2: hsi_ker_ck clock selected as kernel peripheral..,3: csi_ker_ck clock selected as kernel peripheral..,?,?,?,?" line.long 0x4 "RCC_I2C345CKSELR,RCC I2C3. I2C4 and I2C5 kernel clock selection register." bitfld.long 0x4 6.--8. "I2C5SRC,I2C5 kernel clock source selection" "0: pclk6 clock selected as kernel peripheral clock..,1: pll4_r_ck clock selected as kernel peripheral..,2: hsi_ker_ck clock selected as kernel peripheral..,3: csi_ker_ck clock selected as kernel peripheral..,?,?,?,?" bitfld.long 0x4 3.--5. "I2C4SRC,I2C4 kernel clock source selection" "0: pclk6 clock selected as kernel peripheral clock..,1: pll4_r_ck clock selected as kernel peripheral..,2: hsi_ker_ck clock selected as kernel peripheral..,3: csi_ker_ck clock selected as kernel peripheral..,?,?,?,?" newline bitfld.long 0x4 0.--2. "I2C3SRC,I2C3 kernel clock source selection" "0: pclk6 clock selected as kernel peripheral clock..,1: pll4_r_ck clock selected as kernel peripheral..,2: hsi_ker_ck clock selected as kernel peripheral..,3: csi_ker_ck clock selected as kernel peripheral..,?,?,?,?" line.long 0x8 "RCC_SPI2S1CKSELR,RCC SPI/I2S1 kernel clock selection register" bitfld.long 0x8 0.--2. "SPI1SRC,SPI/I2S1 kernel clock source selection" "0: pll4_p_ck clock selected as kernel peripheral..,1: pll3_q_ck clock selected as kernel peripheral..,2: I2S_CKIN clock selected as kernel peripheral clock,3: per_ck clock selected as kernel peripheral clock,4: pll3_r_ck clock selected as kernel peripheral..,?,?,?" line.long 0xC "RCC_SPI2S23CKSELR,RCC SPI/I2S2 and SPI/I2S3 kernel clock selection register" bitfld.long 0xC 0.--2. "SPI23SRC,SPI/I2S2 and SPI/I2S3 kernel clock source selection" "0: pll4_p_ck clock selected as kernel peripheral..,1: pll3_q_ck clock selected as kernel peripheral..,2: I2S_CKIN clock selected as kernel peripheral clock,3: per_ck clock selected as kernel peripheral clock,4: pll3_r_ck clock selected as kernel peripheral..,?,?,?" line.long 0x10 "RCC_SPI45CKSELR,RCC SPI/I2S4 and SPI5 kernel clock selection register" bitfld.long 0x10 3.--5. "SPI5SRC,SPI5 kernel clock source selection" "0: pclk6 clock selected as kernel peripheral clock..,1: pll4_q_ck clock selected as kernel peripheral..,2: hsi_ker_ck clock selected as kernel peripheral..,3: csi_ker_ck clock selected as kernel peripheral..,4: hse_ker_ck clock selected as kernel peripheral..,?,?,?" bitfld.long 0x10 0.--2. "SPI4SRC,SPI/I2S4 kernel clock source selection" "0: pclk6 clock selected as kernel peripheral clock..,1: pll4_q_ck clock selected as kernel peripheral..,2: hsi_ker_ck clock selected as kernel peripheral..,3: csi_ker_ck clock selected as kernel peripheral..,4: hse_ker_ck clock selected as kernel peripheral..,5: I2S_CKIN clock selected as kernel peripheral clock,?,?" line.long 0x14 "RCC_UART12CKSELR,RCC USART1 and USART2 kernel clock selection register" bitfld.long 0x14 3.--5. "UART2SRC,USART2 kernel clock source selection" "0: pclk6 clock selected as kernel peripheral clock..,1: pll3_q_ck clock selected as kernel peripheral..,2: hsi_ker_ck clock selected as kernel peripheral..,3: csi_ker_ck clock selected as kernel peripheral..,4: pll4_q_ck clock selected as kernel peripheral..,5: hse_ker_ck clock selected as kernel peripheral..,?,?" bitfld.long 0x14 0.--2. "UART1SRC,USART1 kernel clock source selection" "0: pclk6 clock selected as kernel peripheral clock..,1: pll3_q_ck clock selected as kernel peripheral..,2: hsi_ker_ck clock selected as kernel peripheral..,3: csi_ker_ck clock selected as kernel peripheral..,4: pll4_q_ck clock selected as kernel peripheral..,5: hse_ker_ck clock selected as kernel peripheral..,?,?" line.long 0x18 "RCC_UART35CKSELR,RCC USART3 and UART5 kernel clock selection register" bitfld.long 0x18 0.--2. "UART35SRC,USART3 and UART5 kernel clock source selection" "0: pclk1 clock selected as kernel peripheral clock..,1: pll4_q_ck clock selected as kernel peripheral..,2: hsi_ker_ck clock selected as kernel peripheral..,3: csi_ker_ck clock selected as kernel peripheral..,4: hse_ker_ck clock selected as kernel peripheral..,?,?,?" line.long 0x1C "RCC_UART4CKSELR,RCC UART4 kernel clock selection register" bitfld.long 0x1C 0.--2. "UART4SRC,UART4 kernel clock source selection" "0: pclk1 clock selected as kernel peripheral clock..,1: pll4_q_ck clock selected as kernel peripheral..,2: hsi_ker_ck clock selected as kernel peripheral..,3: csi_ker_ck clock selected as kernel peripheral..,4: hse_ker_ck clock selected as kernel peripheral..,?,?,?" line.long 0x20 "RCC_UART6CKSELR,RCC USART6 kernel clock selection register" bitfld.long 0x20 0.--2. "UART6SRC,USART6 kernel clock source selection" "0: pclk2 clock selected as kernel peripheral clock..,1: pll4_q_ck clock selected as kernel peripheral..,2: hsi_ker_ck clock selected as kernel peripheral..,3: csi_ker_ck clock selected as kernel peripheral..,4: hse_ker_ck clock selected as kernel peripheral..,?,?,?" line.long 0x24 "RCC_UART78CKSELR,RCC UART7 and UART8 kernel clock selection register" bitfld.long 0x24 0.--2. "UART78SRC,UART7 and UART8 kernel clock source selection" "0: pclk1 clock selected as kernel peripheral clock..,1: pll4_q_ck clock selected as kernel peripheral..,2: hsi_ker_ck clock selected as kernel peripheral..,3: csi_ker_ck clock selected as kernel peripheral..,4: hse_ker_ck clock selected as kernel peripheral..,?,?,?" line.long 0x28 "RCC_LPTIM1CKSELR,RCC LPTIM1 kernel clock selection register" bitfld.long 0x28 0.--2. "LPTIM1SRC,LPTIM1 kernel clock source selection" "0: pclk1 clock selected as kernel peripheral clock..,1: pll4_p_ck clock selected as kernel peripheral..,2: pll3_q_ck clock selected as kernel peripheral..,3: lse_ck clock selected as kernel peripheral clock,4: lsi_ck clock selected as kernel peripheral clock,5: per_ck clock selected as kernel peripheral clock,?,?" line.long 0x2C "RCC_LPTIM23CKSELR,RCC LPTIM2 and LPTIM3 kernel clock selection register" bitfld.long 0x2C 3.--5. "LPTIM3SRC,LPTIM3 kernel clock source selection" "0: pclk3 clock selected as kernel peripheral clock..,1: pll4_q_ck clock selected as kernel peripheral..,2: per_ck clock selected as kernel peripheral clock,3: lse_ck clock selected as kernel peripheral clock,4: lsi_ck clock selected as kernel peripheral clock,?,?,?" bitfld.long 0x2C 0.--2. "LPTIM2SRC,LPTIM2 kernel clock source selection" "0: pclk3 clock selected as kernel peripheral clock..,1: pll4_q_ck clock selected as kernel peripheral..,2: per_ck clock selected as kernel peripheral clock,3: lse_ck clock selected as kernel peripheral clock,4: lsi_ck clock selected as kernel peripheral clock,?,?,?" line.long 0x30 "RCC_LPTIM45CKSELR,RCC LPTIM4 and LPTIM5 kernel clock selection register" bitfld.long 0x30 0.--2. "LPTIM45SRC,LPTIM4 and LPTIM5 kernel clock source selection" "0: pclk3 clock selected as kernel peripheral clock..,1: pll4_p_ck clock selected as kernel peripheral..,2: pll3_q_ck clock selected as kernel peripheral..,3: lse_ck clock selected as kernel peripheral clock,4: lsi_ck clock selected as kernel peripheral clock,5: per_ck clock selected as kernel peripheral clock,?,?" line.long 0x34 "RCC_SAI1CKSELR,RCC SAI1 kernel clock selection register" bitfld.long 0x34 0.--2. "SAI1SRC,SAI1 and DFSDM kernel clock source selection" "0: pll4_q_ck clock selected as kernel peripheral..,1: pll3_q_ck clock selected as kernel peripheral..,2: I2S_CKIN clock selected as kernel peripheral clock,3: per_ck clock selected as kernel peripheral clock,4: pll3_r_ck clock selected as kernel peripheral..,?,?,?" line.long 0x38 "RCC_SAI2CKSELR,RCC SAI2 kernel clock selection register" bitfld.long 0x38 0.--2. "SAI2SRC,SAI2 kernel clock source selection" "0: pll4_q_ck clock selected as kernel peripheral..,1: pll3_q_ck clock selected as kernel peripheral..,2: I2S_CKIN clock selected as kernel peripheral clock,3: per_ck clock selected as kernel peripheral clock,4: spdif_ck_symb clock from SPDIFRX selected as..,5: pll3_r_ck clock selected as kernel peripheral..,?,?" line.long 0x3C "RCC_FDCANCKSELR,RCC FDCAN kernel clock selection register" bitfld.long 0x3C 0.--1. "FDCANSRC,FDCAN kernel clock source selection" "0: hse_ker_ck clock selected as kernel peripheral..,1: pll3_q_ck clock selected as kernel peripheral..,2: pll4_q_ck clock selected as kernel peripheral..,3: pll4_r_ck clock selected as kernel peripheral.." line.long 0x40 "RCC_SPDIFCKSELR,RCC SPDIFRX kernel clock selection register" bitfld.long 0x40 0.--1. "SPDIFSRC,SPDIFRX kernel clock source selection" "0: pll4_p_ck clock selected as kernel peripheral..,1: pll3_q_ck clock selected as kernel peripheral..,2: hsi_ker_ck clock selected as kernel peripheral..,?" line.long 0x44 "RCC_ADC12CKSELR,This register may be separately and securely write-protected at a field level depending on" bitfld.long 0x44 2.--3. "ADC2SRC,ADC2 kernel clock source selection" "0: pll4_r_ck clock selected as kernel peripheral..,1: per_ck clock selected as kernel peripheral clock,2: pll3_q_ck clock selected as kernel peripheral..,?" bitfld.long 0x44 0.--1. "ADC1SRC,ADC1 kernel clock source selection" "0: pll4_r_ck clock selected as kernel peripheral..,1: per_ck clock selected as kernel peripheral clock,2: pll3_q_ck clock selected as kernel peripheral..,?" line.long 0x48 "RCC_SDMMC12CKSELR,This register may be separately and securely write-protected at a field level depending on" bitfld.long 0x48 3.--5. "SDMMC2SRC,SDMMC2 kernel clock source selection" "0: hclk6 clock selected as kernel peripheral clock,1: pll3_r_ck clock selected as kernel peripheral..,2: pll4_p_ck clock selected as kernel peripheral..,3: hsi_ker_ck clock selected as kernel peripheral..,?,?,?,?" bitfld.long 0x48 0.--2. "SDMMC1SRC,SDMMC1 kernel clock source selection" "0: hclk6 clock selected as kernel peripheral clock,1: pll3_r_ck clock selected as kernel peripheral..,2: pll4_p_ck clock selected as kernel peripheral..,3: hsi_ker_ck clock selected as kernel peripheral..,?,?,?,?" line.long 0x4C "RCC_ETH12CKSELR,This register may be separately and securely write-protected at a field level depending on" hexmask.long.byte 0x4C 12.--15. 1. "ETH2PTPDIV,ETH2 clock divider for Precision Time Protocol (PTP)" bitfld.long 0x4C 8.--9. "ETH2SRC,ETH2 kernel clock source selection" "0: pll4_p_ck clock selected as kernel peripheral..,1: pll3_q_ck clock selected as kernel peripheral..,?,?" newline hexmask.long.byte 0x4C 4.--7. 1. "ETH1PTPDIV,ETH1 clock divider for Precision Time Protocol (PTP)" bitfld.long 0x4C 0.--1. "ETH1SRC,ETH1 kernel clock source selection" "0: pll4_p_ck clock selected as kernel peripheral..,1: pll3_q_ck clock selected as kernel peripheral..,?,?" line.long 0x50 "RCC_USBCKSELR,This register may be separately and securely write-protected at a field level depending on" bitfld.long 0x50 4. "USBOSRC,USB OTG kernel clock source selection" "0: pll4_r_ck clock selected as kernel peripheral..,1: clock provided by the USB PHY (rcc_ck_usbo_48m).." bitfld.long 0x50 0.--1. "USBPHYSRC,USB PHY kernel clock source selection" "0: hse_ker_ck clock selected as kernel peripheral..,1: pll4_r_ck clock selected as kernel peripheral..,2: hse_ker_ck/2 clock selected as kernel peripheral..,?" line.long 0x54 "RCC_QSPICKSELR,If (AHB6) QUADSPI is configured as secure via the corresponding DECPROT[1] field of the" bitfld.long 0x54 0.--1. "QSPISRC,QUADSPI kernel clock source selection" "0: aclk clock selected as kernel peripheral clock..,1: pll3_r_ck clock selected as kernel peripheral..,2: pll4_p_ck clock selected as kernel peripheral..,3: per_ck clock selected as kernel peripheral clock" line.long 0x58 "RCC_FMCCKSELR,If (AHB6) FMC is configured as secure via the corresponding DECPROT[1] field of the" bitfld.long 0x58 0.--1. "FMCSRC,FMC kernel clock source selection" "0: aclk clock selected as kernel peripheral clock..,1: pll3_r_ck clock selected as kernel peripheral..,2: pll4_p_ck clock selected as kernel peripheral..,3: per_ck clock selected as kernel peripheral clock" line.long 0x5C "RCC_RNG1CKSELR,If (AHB5) RNG1 is configured as secure via the corresponding DECPROT[1] field of the" bitfld.long 0x5C 0.--1. "RNG1SRC,RNG1 kernel clock source selection" "0: csi_ker_ck clock selected as kernel peripheral..,1: pll4_r_ck clock selected as kernel peripheral..,2: lse_ck clock selected as kernel peripheral clock,3: lsi_ck clock selected as kernel peripheral clock" line.long 0x60 "RCC_STGENCKSELR,If (APB5) STGENC is configured as secure via the corresponding DECPROT[1] field of the" bitfld.long 0x60 0.--1. "STGENSRC,Oscillator selection for kernel clock" "0: hsi_ker_ck clock selected (default after reset),1: hse_ker_ck clock selected,?,?" line.long 0x64 "RCC_DCMIPPCKSELR,If (APB4) DCMIPP is configured as secure via the corresponding DECPROT[1] field of the" bitfld.long 0x64 0.--1. "DCMIPPSRC,DCMIPP kernel clock source selection" "0: aclk clock selected as kernel peripheral clock..,1: pll2_q_ck clock selected as kernel peripheral..,2: pll4_p_ck clock selected as kernel peripheral..,3: per_ck clock selected as kernel peripheral clock" line.long 0x68 "RCC_SAESCKSELR,If (AHB5) SAES is configured as secure via the corresponding DECPROT[1] field of the" bitfld.long 0x68 0.--1. "SAESSRC,SAES kernel clock source selection" "0: axiss_ck clock selected as kernel peripheral..,1: per_ck clock selected as kernel peripheral clock,2: pll_4_r_ck clock selected as kernel peripheral..,3: lsi_ck clock selected as kernel peripheral clock" group.long 0x6A0++0x37 line.long 0x0 "RCC_APB1RSTSETR,This register is used to activate the reset of the corresponding peripheral. Writing '0' has no" bitfld.long 0x0 26. "SPDIFRST,SPDIFRX block reset" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' asserts the block reset reading '1'.." bitfld.long 0x0 22. "I2C2RST,I2C2 block reset" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' asserts the block reset reading '1'.." newline bitfld.long 0x0 21. "I2C1RST,I2C1 block reset" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' asserts the block reset reading '1'.." bitfld.long 0x0 19. "UART8RST,UART8 block reset" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' asserts the block reset reading '1'.." newline bitfld.long 0x0 18. "UART7RST,UART7 block reset" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' asserts the block reset reading '1'.." bitfld.long 0x0 17. "UART5RST,UART5 block reset" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' asserts the block reset reading '1'.." newline bitfld.long 0x0 16. "UART4RST,UART4 block reset" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' asserts the block reset reading '1'.." bitfld.long 0x0 15. "USART3RST,USART3 block reset" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' asserts the block reset reading '1'.." newline bitfld.long 0x0 12. "SPI3RST,SPI3 block reset" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' asserts the block reset reading '1'.." bitfld.long 0x0 11. "SPI2RST,SPI/I2S2 block reset" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' asserts the block reset reading '1'.." newline bitfld.long 0x0 9. "LPTIM1RST,LPTIM1 block reset" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' asserts the block reset reading '1'.." bitfld.long 0x0 5. "TIM7RST,TIM7 block reset" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' asserts the block reset reading '1'.." newline bitfld.long 0x0 4. "TIM6RST,TIM6 block reset" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' asserts the block reset reading '1'.." bitfld.long 0x0 3. "TIM5RST,TIM5 block reset" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' asserts the block reset reading '1'.." newline bitfld.long 0x0 2. "TIM4RST,TIM4 block reset" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' asserts the block reset reading '1'.." bitfld.long 0x0 1. "TIM3RST,TIM3 block reset" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' asserts the block reset reading '1'.." newline bitfld.long 0x0 0. "TIM2RST,TIM2 block reset" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' asserts the block reset reading '1'.." line.long 0x4 "RCC_APB1RSTCLRR,This register is used to release the reset of the corresponding peripheral. Writing '0' has no" bitfld.long 0x4 26. "SPDIFRST,SPDIFRX block reset" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' release the block reset reading '1'.." bitfld.long 0x4 22. "I2C2RST,I2C2 block reset" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' release the block reset reading '1'.." newline bitfld.long 0x4 21. "I2C1RST,I2C1 block reset" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' release the block reset reading '1'.." bitfld.long 0x4 19. "UART8RST,UART8 block reset" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' release the block reset reading '1'.." newline bitfld.long 0x4 18. "UART7RST,UART7 block reset" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' release the block reset reading '1'.." bitfld.long 0x4 17. "UART5RST,UART5 block reset" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' release the block reset reading '1'.." newline bitfld.long 0x4 16. "UART4RST,UART4 block reset" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' release the block reset reading '1'.." bitfld.long 0x4 15. "USART3RST,USART3 block reset" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' release the block reset reading '1'.." newline bitfld.long 0x4 12. "SPI3RST,SPI3 block reset" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' release the block reset reading '1'.." bitfld.long 0x4 11. "SPI2RST,SPI2 block reset" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' release the block reset reading '1'.." newline bitfld.long 0x4 9. "LPTIM1RST,LPTIM1 block reset" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' release the block reset reading '1'.." bitfld.long 0x4 5. "TIM7RST,TIM7 block reset" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' release the block reset reading '1'.." newline bitfld.long 0x4 4. "TIM6RST,TIM6 block reset" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' release the block reset reading '1'.." bitfld.long 0x4 3. "TIM5RST,TIM5 block reset" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' release the block reset reading '1'.." newline bitfld.long 0x4 2. "TIM4RST,TIM4 block reset" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' release the block reset reading '1'.." bitfld.long 0x4 1. "TIM3RST,TIM3 block reset" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' release the block reset reading '1'.." newline bitfld.long 0x4 0. "TIM2RST,TIM2 block reset" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' release the block reset reading '1'.." line.long 0x8 "RCC_APB2RSTSETR,This register is used to activate the reset of the corresponding peripheral. Writing '0' has no" bitfld.long 0x8 24. "FDCANRST,FDCAN block reset" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' asserts the block reset reading '1'.." bitfld.long 0x8 20. "DFSDMRST,DFSDM block reset" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' asserts the block reset reading '1'.." newline bitfld.long 0x8 17. "SAI2RST,SAI2 block reset" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' asserts the block reset reading '1'.." bitfld.long 0x8 16. "SAI1RST,SAI1 block reset" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' asserts the block reset reading '1'.." newline bitfld.long 0x8 13. "USART6RST,USART6 block reset" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' asserts the block reset reading '1'.." bitfld.long 0x8 8. "SPI1RST,SPI/I2S1 block reset" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' asserts the block reset reading '1'.." newline bitfld.long 0x8 1. "TIM8RST,TIM8 block reset" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' asserts the block reset reading '1'.." bitfld.long 0x8 0. "TIM1RST,TIM1 block reset" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' asserts the block reset reading '1'.." line.long 0xC "RCC_APB2RSTCLRR,This register is used to release the reset of the corresponding peripheral. Writing '0' has no" bitfld.long 0xC 24. "FDCANRST,FDCAN block reset" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' releases the block reset reading '1'.." bitfld.long 0xC 20. "DFSDMRST,DFSDM block reset" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' releases the block reset reading '1'.." newline bitfld.long 0xC 17. "SAI2RST,SAI2 block reset" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' releases the block reset reading '1'.." bitfld.long 0xC 16. "SAI1RST,SAI1 block reset" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' releases the block reset reading '1'.." newline bitfld.long 0xC 13. "USART6RST,USART6 block reset" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' releases the block reset reading '1'.." bitfld.long 0xC 8. "SPI1RST,SPI/I2S1 block reset" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' releases the block reset reading '1'.." newline bitfld.long 0xC 1. "TIM8RST,TIM8 block reset" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' releases the block reset reading '1'.." bitfld.long 0xC 0. "TIM1RST,TIM1 block reset" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' releases the block reset reading '1'.." line.long 0x10 "RCC_APB3RSTSETR,This register may be separately and securely write-protected at a field level. as detailed in" bitfld.long 0x10 17. "PMBCTRLRST,PMBCTRL block reset" "0,1" bitfld.long 0x10 16. "DTSRST,DTS block reset" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' asserts the block reset reading '1'.." newline bitfld.long 0x10 13. "VREFRST,VREF block reset" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' asserts the block reset reading '1'.." bitfld.long 0x10 11. "SYSCFGRST,SYSCFG block reset" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' asserts the block reset reading '1'.." newline bitfld.long 0x10 3. "LPTIM5RST,LPTIM5 block reset" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' asserts the block reset reading '1'.." bitfld.long 0x10 2. "LPTIM4RST,LPTIM4 block reset" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' asserts the block reset reading '1'.." newline bitfld.long 0x10 1. "LPTIM3RST,LPTIM3 block reset" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' asserts the block reset reading '1'.." bitfld.long 0x10 0. "LPTIM2RST,LPTIM2 block reset" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' asserts the block reset reading '1'.." line.long 0x14 "RCC_APB3RSTCLRR,This register may be separately and securely write-protected at a field level. as detailed in" bitfld.long 0x14 17. "PMBCTRLRST,PMBCTRL block reset" "0,1" bitfld.long 0x14 16. "DTSRST,DTS block reset" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' releases the block reset reading '1'.." newline bitfld.long 0x14 13. "VREFRST,VREF block reset" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' releases the block reset reading '1'.." bitfld.long 0x14 11. "SYSCFGRST,SYSCFG block reset" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' releases the block reset reading '1'.." newline bitfld.long 0x14 3. "LPTIM5RST,LPTIM5 block reset" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' releases the block reset reading '1'.." bitfld.long 0x14 2. "LPTIM4RST,LPTIM4 block reset" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' releases the block reset reading '1'.." newline bitfld.long 0x14 1. "LPTIM3RST,LPTIM3 block reset" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' releases the block reset reading '1'.." bitfld.long 0x14 0. "LPTIM2RST,LPTIM2 block reset" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' releases the block reset reading '1'.." line.long 0x18 "RCC_APB4RSTSETR,This register may be separately and securely write-protected at a field level. as detailed in" bitfld.long 0x18 16. "USBPHYRST,USBPHYC block reset" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' asserts the block reset reading '1'.." bitfld.long 0x18 8. "DDRPERFMRST,DDRPERFM block reset" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' asserts the block reset reading '1'.." newline bitfld.long 0x18 1. "DCMIPPRST,DCMIPP block reset" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' asserts the block reset reading '1'.." bitfld.long 0x18 0. "LTDCRST,LTDC block reset" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' asserts the block reset reading '1'.." line.long 0x1C "RCC_APB4RSTCLRR,This register may be separately and securely write-protected at a field level. as detailed in" bitfld.long 0x1C 16. "USBPHYRST,USBPHYC block reset" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' releases the block reset reading '1'.." bitfld.long 0x1C 8. "DDRPERFMRST,DDRPERFM block reset" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' releases the block reset reading '1'.." newline bitfld.long 0x1C 1. "DCMIPPRST,DCMIPP block reset" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' releases the block reset reading '1'.." bitfld.long 0x1C 0. "LTDCRST,LTDC block reset" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' releases the block reset reading '1'.." line.long 0x20 "RCC_APB5RSTSETR,This register may be separately and securely write-protected at a field level depending on" bitfld.long 0x20 20. "STGENRST,STGEN block reset" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' asserts the block reset reading '1'.." line.long 0x24 "RCC_APB5RSTCLRR,This register may be separately and securely write-protected at a field level depending on" bitfld.long 0x24 20. "STGENRST,STGEN block reset" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' releases the block reset reading '1'.." line.long 0x28 "RCC_APB6RSTSETR,This register may be separately and securely write-protected at a field level depending on" bitfld.long 0x28 12. "TIM17RST,TIM17 block reset" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' asserts the block reset reading '1'.." bitfld.long 0x28 11. "TIM16RST,TIM16 block reset" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' asserts the block reset reading '1'.." newline bitfld.long 0x28 10. "TIM15RST,TIM15 block reset" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' asserts the block reset reading '1'.." bitfld.long 0x28 9. "TIM14RST,TIM14 block reset" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' asserts the block reset reading '1'.." newline bitfld.long 0x28 8. "TIM13RST,TIM13 block reset" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' asserts the block reset reading '1'.." bitfld.long 0x28 7. "TIM12RST,TIM12 block reset" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' asserts the block reset reading '1'.." newline bitfld.long 0x28 6. "I2C5RST,I2C5 block reset" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' asserts the block reset reading '1'.." bitfld.long 0x28 5. "I2C4RST,I2C4 block reset" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' asserts the block reset reading '1'.." newline bitfld.long 0x28 4. "I2C3RST,I2C3 block reset" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' asserts the block reset reading '1'.." bitfld.long 0x28 3. "SPI5RST,SPI5 block reset" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' asserts the block reset reading '1'.." newline bitfld.long 0x28 2. "SPI4RST,SPI4 block reset" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' asserts the block reset reading '1'.." bitfld.long 0x28 1. "USART2RST,USART2 block reset" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' asserts the block reset reading '1'.." newline bitfld.long 0x28 0. "USART1RST,USART1 block reset" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' asserts the block reset reading '1'.." line.long 0x2C "RCC_APB6RSTCLRR,This register may be separately and securely write-protected at a field level depending on" bitfld.long 0x2C 12. "TIM17RST,TIM17 block reset" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' releases the block reset reading '1'.." bitfld.long 0x2C 11. "TIM16RST,TIM16 block reset" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' releases the block reset reading '1'.." newline bitfld.long 0x2C 10. "TIM15RST,TIM15 block reset" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' releases the block reset reading '1'.." bitfld.long 0x2C 9. "TIM14RST,TIM14 block reset" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' releases the block reset reading '1'.." newline bitfld.long 0x2C 8. "TIM13RST,TIM13 block reset" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' releases the block reset reading '1'.." bitfld.long 0x2C 7. "TIM12RST,TIM12 block reset" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' releases the block reset reading '1'.." newline bitfld.long 0x2C 6. "I2C5RST,I2C5 block reset" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' releases the block reset reading '1'.." bitfld.long 0x2C 5. "I2C4RST,I2C4 block reset" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' releases the block reset reading '1'.." newline bitfld.long 0x2C 4. "I2C3RST,I2C3 block reset" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' releases the block reset reading '1'.." bitfld.long 0x2C 3. "SPI5RST,SPI5 block reset" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' releases the block reset reading '1'.." newline bitfld.long 0x2C 2. "SPI4RST,SPI4 block reset" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' releases the block reset reading '1'.." bitfld.long 0x2C 1. "USART2RST,USART2 block reset" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' releases the block reset reading '1'.." newline bitfld.long 0x2C 0. "USART1RST,USART1 block reset" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' releases the block reset reading '1'.." line.long 0x30 "RCC_AHB2RSTSETR,This register may be separately and securely write-protected at a field level depending on" bitfld.long 0x30 8. "USBORST,USBO block reset" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' asserts the block reset reading '1'.." bitfld.long 0x30 6. "ADC2RST,ADC2 block reset" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' asserts the block reset reading '1'.." newline bitfld.long 0x30 5. "ADC1RST,ADC1 block reset" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' asserts the block reset reading '1'.." bitfld.long 0x30 4. "DMAMUX2RST,DMAMUX2 block reset" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' asserts the block reset reading '1'.." newline bitfld.long 0x30 3. "DMA3RST,DMA3 block reset" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' asserts the block reset reading '1'.." bitfld.long 0x30 2. "DMAMUX1RST,DMAMUX1 block reset" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' asserts the block reset reading '1'.." newline bitfld.long 0x30 1. "DMA2RST,DMA2 block reset" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' asserts the block reset reading '1'.." bitfld.long 0x30 0. "DMA1RST,DMA1 block reset" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' asserts the block reset reading '1'.." line.long 0x34 "RCC_AHB2RSTCLRR,This register may be separately and securely write-protected at a field level depending on" bitfld.long 0x34 8. "USBORST,USBO block reset" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' releases the block reset reading '1'.." bitfld.long 0x34 6. "ADC2RST,ADC2 block reset" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' releases the block reset reading '1'.." newline bitfld.long 0x34 5. "ADC1RST,ADC1 block reset" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' releases the block reset reading '1'.." bitfld.long 0x34 4. "DMAMUX2RST,DMAMUX2 block reset" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' releases the block reset reading '1'.." newline bitfld.long 0x34 3. "DMA3RST,DMA3 block reset" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' releases the block reset reading '1'.." bitfld.long 0x34 2. "DMAMUX1RST,DMAMUX1 block reset" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' releases the block reset reading '1'.." newline bitfld.long 0x34 1. "DMA2RST,DMA2 block reset" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' releases the block reset reading '1'.." bitfld.long 0x34 0. "DMA1RST,DMA1 block reset" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' releases the block reset reading '1'.." group.long 0x6E0++0x17 line.long 0x0 "RCC_AHB4RSTSETR,This register may be separately and securely write-protected at a field level. as detailed in" bitfld.long 0x0 15. "TSCRST,TSC block reset" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' asserts the block reset reading '1'.." bitfld.long 0x0 8. "GPIOIRST,GPIOI block reset" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' asserts the block reset reading '1'.." newline bitfld.long 0x0 7. "GPIOHRST,GPIOH block reset" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' asserts the block reset reading '1'.." bitfld.long 0x0 6. "GPIOGRST,GPIOG block reset" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' asserts the block reset reading '1'.." newline bitfld.long 0x0 5. "GPIOFRST,GPIOF block reset" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' asserts the block reset reading '1'.." bitfld.long 0x0 4. "GPIOERST,GPIOE block reset" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' asserts the block reset reading '1'.." newline bitfld.long 0x0 3. "GPIODRST,GPIOD block reset" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' asserts the block reset reading '1'.." bitfld.long 0x0 2. "GPIOCRST,GPIOC block reset" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' asserts the block reset reading '1'.." newline bitfld.long 0x0 1. "GPIOBRST,GPIOB block reset" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' asserts the block reset reading '1'.." bitfld.long 0x0 0. "GPIOARST,GPIOA block reset" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' asserts the block reset reading '1'.." line.long 0x4 "RCC_AHB4RSTCLRR,This register may be separately and securely write-protected at a field level. as detailed in" bitfld.long 0x4 15. "TSCRST,TSC block reset" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' releases the block reset reading '1'.." bitfld.long 0x4 8. "GPIOIRST,GPIOI block reset" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' releases the block reset reading '1'.." newline bitfld.long 0x4 7. "GPIOHRST,GPIOH block reset" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' releases the block reset reading '1'.." bitfld.long 0x4 6. "GPIOGRST,GPIOG block reset" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' releases the block reset reading '1'.." newline bitfld.long 0x4 5. "GPIOFRST,GPIOF block reset" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' releases the block reset reading '1'.." bitfld.long 0x4 4. "GPIOERST,GPIOE block reset" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' releases the block reset reading '1'.." newline bitfld.long 0x4 3. "GPIODRST,GPIOD block reset" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' releases the block reset reading '1'.." bitfld.long 0x4 2. "GPIOCRST,GPIOC block reset" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' releases the block reset reading '1'.." newline bitfld.long 0x4 1. "GPIOBRST,GPIOB block reset" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' releases the block reset reading '1'.." bitfld.long 0x4 0. "GPIOARST,GPIOA block reset" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' releases the block reset reading '1'.." line.long 0x8 "RCC_AHB5RSTSETR,This register may be separately and securely write-protected at a field level. as detailed in" bitfld.long 0x8 16. "AXIMCRST,AXIMC block reset" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' asserts the block reset reading '1'.." bitfld.long 0x8 6. "RNG1RST,RNG1 block reset" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' asserts the block reset reading '1'.." newline bitfld.long 0x8 5. "HASH1RST,HASH block reset" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' asserts the block reset reading '1'.." bitfld.long 0x8 4. "CRYP1RST,CRYP (3DES/AES) block reset" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' asserts the block reset reading '1'.." newline bitfld.long 0x8 3. "SAESRST,SAES block reset" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' asserts the block reset reading '1'.." bitfld.long 0x8 2. "PKARST,PKA block reset" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' asserts the block reset reading '1'.." line.long 0xC "RCC_AHB5RSTCLRR,This register may be separately and securely write-protected at a field level. as detailed in" bitfld.long 0xC 16. "AXIMCRST,AXIMC block reset" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' releases the block reset reading '1'.." bitfld.long 0xC 6. "RNG1RST,RNG1 block reset" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' releases the block reset reading '1'.." newline bitfld.long 0xC 5. "HASH1RST,HASH block reset" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' releases the block reset reading '1'.." bitfld.long 0xC 4. "CRYP1RST,CRYP (3DES/AES) block reset" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' releases the block reset reading '1'.." newline bitfld.long 0xC 3. "SAESRST,SAES block reset" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' releases the block reset reading '1'.." bitfld.long 0xC 2. "PKARST,PKA block reset" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' releases the block reset reading '1'.." line.long 0x10 "RCC_AHB6RSTSETR,This register may be separately and securely write-protected at a field level. as detailed in" bitfld.long 0x10 30. "ETH2MACRST,ETH2 MAC block reset" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' asserts the block reset reading '1'.." bitfld.long 0x10 24. "USBHRST,USBH block reset" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' asserts the block reset reading '1'.." newline bitfld.long 0x10 20. "CRC1RST,CRC block reset" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' asserts the block reset reading '1'.." bitfld.long 0x10 17. "SDMMC2RST,SDMMC2 and the SDMMC2 delay (DLYBSD2) block reset" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' asserts the block reset reading '1'.." newline bitfld.long 0x10 16. "SDMMC1RST,SDMMC1 and the SDMMC1 delay (DLYBSD1) block reset" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' asserts the block reset reading '1'.." bitfld.long 0x10 14. "QSPIRST,QUADSPI and the QUADSPI delay block reset" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' asserts the block reset reading '1'.." newline bitfld.long 0x10 12. "FMCRST,FMC block reset" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' asserts the block reset reading '1'.." bitfld.long 0x10 10. "ETH1MACRST,ETH1 MAC block reset" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' asserts the block reset reading '1'.." newline bitfld.long 0x10 1. "MCERST,MCE block reset" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' asserts the block reset reading '1'.." bitfld.long 0x10 0. "MDMARST,MDMA block reset" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' asserts the block reset reading '1'.." line.long 0x14 "RCC_AHB6RSTCLRR,This register may be separately and securely write-protected at a field level depending on" bitfld.long 0x14 30. "ETH2MACRST,ETH2 MAC block reset" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' releases the block reset reading '1'.." bitfld.long 0x14 24. "USBHRST,USBH block reset" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' releases the block reset reading '1'.." newline bitfld.long 0x14 20. "CRC1RST,CRC block reset" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' releases the block reset reading '1'.." bitfld.long 0x14 17. "SDMMC2RST,SDMMC2 and the SDMMC2 delay (DLYBSD2) block reset" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' releases the block reset reading '1'.." newline bitfld.long 0x14 16. "SDMMC1RST,SDMMC1 and the SDMMC1 delay (DLYBSD1) block reset" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' releases the block reset reading '1'.." bitfld.long 0x14 14. "QSPIRST,QUADSPI and the QUADSPI delay block reset" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' releases the block reset reading '1'.." newline bitfld.long 0x14 12. "FMCRST,FMC block reset" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' releases the block reset reading '1'.." bitfld.long 0x14 10. "ETH1MACRST,ETH1 MAC block reset" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' releases the block reset reading '1'.." newline bitfld.long 0x14 1. "MCERST,MCE block reset" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' releases the block reset reading '1'.." bitfld.long 0x14 0. "MDMARST,MDMA block reset" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' releases the block reset reading '1'.." group.long 0x700++0x57 line.long 0x0 "RCC_MP_APB1ENSETR,This register is used to set the peripheral clock enable bit of the corresponding peripheral. It" bitfld.long 0x0 26. "SPDIFEN,SPDIFRX peripheral clocks enable" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' enables the peripheral clocks.." bitfld.long 0x0 22. "I2C2EN,I2C2 peripheral clocks enable" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' enables the peripheral clocks.." newline bitfld.long 0x0 21. "I2C1EN,I2C1 peripheral clocks enable" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' enables the peripheral clocks.." bitfld.long 0x0 19. "UART8EN,UART8 peripheral clocks enable" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' enables the peripheral clocks.." newline bitfld.long 0x0 18. "UART7EN,UART7 peripheral clocks enable" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' enables the peripheral clocks.." bitfld.long 0x0 17. "UART5EN,UART5 peripheral clocks enable" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' enables the peripheral clocks.." newline bitfld.long 0x0 16. "UART4EN,UART4 peripheral clocks enable" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' enables the peripheral clocks.." bitfld.long 0x0 15. "USART3EN,USART3 peripheral clocks enable" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' enables the peripheral clocks.." newline bitfld.long 0x0 12. "SPI3EN,SPI3 peripheral clocks enable" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' enables the peripheral clocks.." bitfld.long 0x0 11. "SPI2EN,SPI2 peripheral clocks enable" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' enables the peripheral clocks.." newline bitfld.long 0x0 9. "LPTIM1EN,LPTIM1 peripheral clocks enable" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' enables the peripheral clocks.." bitfld.long 0x0 5. "TIM7EN,TIM7 peripheral clocks enable" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' enables the peripheral clocks.." newline bitfld.long 0x0 4. "TIM6EN,TIM6 peripheral clocks enable" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' enables the peripheral clocks.." bitfld.long 0x0 3. "TIM5EN,TIM5 peripheral clocks enable" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' enables the peripheral clocks.." newline bitfld.long 0x0 2. "TIM4EN,TIM4 peripheral clocks enable" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' enables the peripheral clocks.." bitfld.long 0x0 1. "TIM3EN,TIM3 peripheral clocks enable" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' enables the peripheral clocks.." newline bitfld.long 0x0 0. "TIM2EN,TIM2 peripheral clocks enable" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' enables the peripheral clocks.." line.long 0x4 "RCC_MP_APB1ENCLRR,This register is used to clear the peripheral clock enable bit of the corresponding peripheral." bitfld.long 0x4 26. "SPDIFEN,SPDIFRX peripheral clocks enable" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' disables the peripheral clocks.." bitfld.long 0x4 22. "I2C2EN,I2C2 peripheral clocks enable" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' disables the peripheral clocks.." newline bitfld.long 0x4 21. "I2C1EN,I2C1 peripheral clocks enable" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' disables the peripheral clocks.." bitfld.long 0x4 19. "UART8EN,UART8 peripheral clocks enable" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' disables the peripheral clocks.." newline bitfld.long 0x4 18. "UART7EN,UART7 peripheral clocks enable" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' disables the peripheral clocks.." bitfld.long 0x4 17. "UART5EN,UART5 peripheral clocks enable" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' disables the peripheral clocks.." newline bitfld.long 0x4 16. "UART4EN,UART4 peripheral clocks enable" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' disables the peripheral clocks.." bitfld.long 0x4 15. "USART3EN,USART3 peripheral clocks enable" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' disables the peripheral clocks.." newline bitfld.long 0x4 12. "SPI3EN,SPI3 peripheral clocks enable" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' disables the peripheral clocks.." bitfld.long 0x4 11. "SPI2EN,SPI2 peripheral clocks enable" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' disables the peripheral clocks.." newline bitfld.long 0x4 9. "LPTIM1EN,LPTIM1 peripheral clocks enable" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' disables the peripheral clocks.." bitfld.long 0x4 5. "TIM7EN,TIM7 peripheral clocks enable" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' disables the peripheral clocks.." newline bitfld.long 0x4 4. "TIM6EN,TIM6 peripheral clocks enable" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' disables the peripheral clocks.." bitfld.long 0x4 3. "TIM5EN,TIM5 peripheral clocks enable" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' disables the peripheral clocks.." newline bitfld.long 0x4 2. "TIM4EN,TIM4 peripheral clocks enable" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' disables the peripheral clocks.." bitfld.long 0x4 1. "TIM3EN,TIM3 peripheral clocks enable" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' disables the peripheral clocks.." newline bitfld.long 0x4 0. "TIM2EN,TIM2 peripheral clocks enable" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' disables the peripheral clocks.." line.long 0x8 "RCC_MP_APB2ENSETR,This register is used to set the peripheral clock enable bit of the corresponding peripheral. It" bitfld.long 0x8 24. "FDCANEN,FDCAN and CANRAM peripheral clocks enable" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' enables the peripheral clocks.." bitfld.long 0x8 21. "ADFSDMEN,Audio DFSDM peripheral clocks enable" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' enables the peripheral clocks.." newline bitfld.long 0x8 20. "DFSDMEN,DFSDM peripheral clocks enable" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' enables the peripheral clocks.." bitfld.long 0x8 17. "SAI2EN,SAI2 peripheral clocks enable" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' enables the peripheral clocks.." newline bitfld.long 0x8 16. "SAI1EN,SAI1 peripheral clocks enable" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' enables the peripheral clocks.." bitfld.long 0x8 13. "USART6EN,USART6 peripheral clocks enable" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' enables the peripheral clocks.." newline bitfld.long 0x8 8. "SPI1EN,SPI/I2S1 peripheral clocks enable" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' enables the peripheral clocks.." bitfld.long 0x8 1. "TIM8EN,TIM8 peripheral clocks enable" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' enables the peripheral clocks.." newline bitfld.long 0x8 0. "TIM1EN,TIM1 peripheral clocks enable" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' enables the peripheral clocks.." line.long 0xC "RCC_MP_APB2ENCLRR,This register is used to clear the peripheral clock enable bit of the corresponding peripheral." bitfld.long 0xC 24. "FDCANEN,FDCAN and CANRAM peripheral clocks enable" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' disables the peripheral clocks.." bitfld.long 0xC 21. "ADFSDMEN,Audio DFSDM peripheral clocks enable" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' disables the peripheral clocks.." newline bitfld.long 0xC 20. "DFSDMEN,DFSDM peripheral clocks enable" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' disables the peripheral clocks.." bitfld.long 0xC 17. "SAI2EN,SAI2 peripheral clocks enable" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' disables the peripheral clocks.." newline bitfld.long 0xC 16. "SAI1EN,SAI1 peripheral clocks enable" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' disables the peripheral clocks.." bitfld.long 0xC 13. "USART6EN,USART6 peripheral clocks enable" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' disables the peripheral clocks.." newline bitfld.long 0xC 8. "SPI1EN,SPI/I2S1 peripheral clocks enable" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' disables the peripheral clocks.." bitfld.long 0xC 1. "TIM8EN,TIM8 peripheral clocks enable" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' disables the peripheral clocks.." newline bitfld.long 0xC 0. "TIM1EN,TIM1 peripheral clocks enable" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' disables the peripheral clocks.." line.long 0x10 "RCC_MP_APB3ENSETR,This register may be separately and securely write-protected at a field level. as detailed in" bitfld.long 0x10 20. "HDPEN,HDP peripheral clocks enable" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' enables the peripheral clocks.." bitfld.long 0x10 17. "PMBCTRLEN,PMBCTRL peripheral clocks enable" "0,1" newline bitfld.long 0x10 16. "DTSEN,DTS peripheral clocks enable" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' enables the peripheral clocks.." bitfld.long 0x10 13. "VREFEN,VREF peripheral clocks enable" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' enables the peripheral clocks.." newline bitfld.long 0x10 3. "LPTIM5EN,LPTIM5 peripheral clocks enable" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' enables the peripheral clocks.." bitfld.long 0x10 2. "LPTIM4EN,LPTIM4 peripheral clocks enable" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' enables the peripheral clocks.." newline bitfld.long 0x10 1. "LPTIM3EN,LPTIM3 peripheral clocks enable" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' enables the peripheral clocks.." bitfld.long 0x10 0. "LPTIM2EN,LPTIM2 peripheral clocks enable" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' enables the peripheral clocks.." line.long 0x14 "RCC_MP_APB3ENCLRR,This register may be separately and securely write-protected at a field level. as detailed in" bitfld.long 0x14 20. "HDPEN,HDP peripheral clocks enable" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' disables the peripheral clocks.." bitfld.long 0x14 17. "PMBCTRLEN,PMBCTRL peripheral clocks enable" "0,1" newline bitfld.long 0x14 16. "DTSEN,DTS peripheral clocks enable" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' disables the peripheral clocks.." bitfld.long 0x14 13. "VREFEN,VREF peripheral clocks enable" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' disables the peripheral clocks.." newline bitfld.long 0x14 3. "LPTIM5EN,LPTIM5 peripheral clocks enable" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' disables the peripheral clocks.." bitfld.long 0x14 2. "LPTIM4EN,LPTIM4 peripheral clocks enable" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' disables the peripheral clocks.." newline bitfld.long 0x14 1. "LPTIM3EN,LPTIM3 peripheral clocks enable" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' disables the peripheral clocks.." bitfld.long 0x14 0. "LPTIM2EN,LPTIM2 peripheral clocks enable" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' disables the peripheral clocks.." line.long 0x18 "RCC_MP_S_APB3ENSETR,This is a secure register for enabling the clock of the SYSCFG." bitfld.long 0x18 0. "SYSCFGEN,SYSCFG peripheral clocks enable" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' enables the peripheral clocks.." line.long 0x1C "RCC_MP_S_APB3ENCLRR,This is a secure register for disabling the clock of the SYSCFG. A write access to this" bitfld.long 0x1C 0. "SYSCFGEN,SYSCFG peripheral clocks enable" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' enables the peripheral clocks.." line.long 0x20 "RCC_MP_NS_APB3ENSETR,This is a non-secure register. for enabling the clock of the SYSCFG." bitfld.long 0x20 0. "SYSCFGEN,SYSCFG peripheral clocks enable" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' enables the peripheral clocks.." line.long 0x24 "RCC_MP_NS_APB3ENCLRR,This is a non-secure register. for disabling the clock of the SYSCFG." bitfld.long 0x24 0. "SYSCFGEN,SYSCFG peripheral clocks enable" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' disables the peripheral clocks.." line.long 0x28 "RCC_MP_APB4ENSETR,This register may be separately and securely write-protected at a field level. as detailed in" bitfld.long 0x28 20. "STGENROEN,STGEN read-only interface peripheral clocks enable" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' enables the pclk4 and the kernel.." bitfld.long 0x28 16. "USBPHYEN,USBPHYC peripheral clocks enable" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' enables the peripheral clocks.." newline bitfld.long 0x28 15. "IWDG2APBEN,IWDG2 APB clock enable" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' enables the APB clock reading '1'.." bitfld.long 0x28 8. "DDRPERFMEN,DDRPERFM APB clock enable" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' enables the APB clock reading '1'.." newline bitfld.long 0x28 1. "DCMIPPEN,DCMIPP peripheral clocks enable" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' enables the peripheral clocks.." line.long 0x2C "RCC_MP_APB4ENCLRR,This register may be separately and securely write-protected at a field level. as detailed in" bitfld.long 0x2C 20. "STGENROEN,STGEN read-only interface peripheral clocks enable" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' disables the pclk4 and disables the.." bitfld.long 0x2C 16. "USBPHYEN,USBPHYC peripheral clocks enable" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' disables the peripheral clocks.." newline bitfld.long 0x2C 15. "IWDG2APBEN,IWDG2 APB clock enable" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' disables the APB clock reading '1'.." bitfld.long 0x2C 8. "DDRPERFMEN,DDRPERFM APB clock enable" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' disables the APB clock reading '1'.." newline bitfld.long 0x2C 1. "DCMIPPEN,DCMIPP peripheral clocks enable" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' disables the peripheral clocks.." line.long 0x30 "RCC_MP_S_APB4ENSETR,This is a secure register for enabling the clock of the LTDC when it is used with a secure" bitfld.long 0x30 0. "LTDCEN,LTDC peripheral clocks enable" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' enables the peripheral clocks.." line.long 0x34 "RCC_MP_S_APB4ENCLRR,This is a secure register for enabling the clock of the LTDC when it is used with a secure" bitfld.long 0x34 0. "LTDCEN,LTDC peripheral clocks enable" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' disables the peripheral clocks.." line.long 0x38 "RCC_MP_NS_APB4ENSETR,This is a non-secure register. for enabling the clock of the LTDC when it is used with one or" bitfld.long 0x38 0. "LTDCEN,LTDC peripheral clocks enable" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' enables the peripheral clocks.." line.long 0x3C "RCC_MP_NS_APB4ENCLRR,This is a non-secure register. for enabling the clock of the LTDC when it is used with one or" bitfld.long 0x3C 0. "LTDCEN,LTDC peripheral clocks enable" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' disables the peripheral clocks.." line.long 0x40 "RCC_MP_APB5ENSETR,This register may be separately and securely write-protected at a field level. as detailed in" bitfld.long 0x40 20. "STGENCEN,STGEN controller part peripheral clocks enable" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' enables the pclk5 and the kernel.." bitfld.long 0x40 16. "BSECEN,BSEC peripheral clocks enable" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' enables the peripheral clocks.." newline bitfld.long 0x40 15. "IWDG1APBEN,IWDG1 APB clock enable" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' enables the APB clock reading '1'.." bitfld.long 0x40 13. "ETZPCEN,ETZPC peripheral clocks enable" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' enables the peripheral clocks.." newline bitfld.long 0x40 11. "TZCEN,TZC clocks enable" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' enables the pclk5 and aclk_tzc1.." bitfld.long 0x40 8. "RTCAPBEN,RTC APB clock enable" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' enables the peripheral clocks.." line.long 0x44 "RCC_MP_APB5ENCLRR,This register may be separately and securely write-protected at a field level. as detailed in" bitfld.long 0x44 20. "STGENCEN,STGEN controller part peripheral clocks enable" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' enables the pclk5 and disables the.." bitfld.long 0x44 16. "BSECEN,BSEC peripheral clocks enable" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' disables the peripheral clocks.." newline bitfld.long 0x44 15. "IWDG1APBEN,IWDG1 APB clock enable" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' disables the APB clock reading '1'.." bitfld.long 0x44 13. "ETZPCEN,ETZPC peripheral clocks enable" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' disables the peripheral clocks.." newline bitfld.long 0x44 11. "TZCEN,TZC clocks enable" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' disables the pclk5 and aclk_tzc1.." bitfld.long 0x44 8. "RTCAPBEN,RTC APB clock enable" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' disables the peripheral clocks.." line.long 0x48 "RCC_MP_APB6ENSETR,This register may be separately and securely write-protected at a field level depending on" bitfld.long 0x48 12. "TIM17EN,TIM17 peripherals clocks" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' enables the peripherals clocks.." bitfld.long 0x48 11. "TIM16EN,TIM16 peripherals clocks" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' enables the peripherals clocks.." newline bitfld.long 0x48 10. "TIM15EN,TIM15 peripherals clocks" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' enables the peripherals clocks.." bitfld.long 0x48 9. "TIM14EN,TIM14 peripherals clocks" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' enables the peripherals clocks.." newline bitfld.long 0x48 8. "TIM13EN,TIM13 peripherals clocks" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' enables the peripherals clocks.." bitfld.long 0x48 7. "TIM12EN,TIM12 peripherals clocks" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' enables the peripherals clocks.." newline bitfld.long 0x48 6. "I2C5EN,I2C5 peripherals clocks" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' enables the peripherals clocks.." bitfld.long 0x48 5. "I2C4EN,I2C4 peripherals clocks" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' enables the peripherals clocks.." newline bitfld.long 0x48 4. "I2C3EN,I2C3 peripherals clocks" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' enables the peripherals clocks.." bitfld.long 0x48 3. "SPI5EN,SPI5 peripherals clocks" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' enables the peripherals clocks.." newline bitfld.long 0x48 2. "SPI4EN,SPI4 peripherals clocks" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' enables the peripherals clocks.." bitfld.long 0x48 1. "USART2EN,USART2 peripherals clocks" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' enables the peripherals clocks.." newline bitfld.long 0x48 0. "USART1EN,USART1 peripherals clocks" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' enables the peripherals clocks.." line.long 0x4C "RCC_MP_APB6ENCLRR,This register may be separately and securely write-protected at a field level depending on" bitfld.long 0x4C 12. "TIM17EN,TIM17 peripherals clocks" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' disables the peripherals clocks.." bitfld.long 0x4C 11. "TIM16EN,TIM16 peripherals clocks" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' disables the peripherals clocks.." newline bitfld.long 0x4C 10. "TIM15EN,TIM15 peripherals clocks" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' disables the peripherals clocks.." bitfld.long 0x4C 9. "TIM14EN,TIM14 peripherals clocks" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' disables the peripherals clocks.." newline bitfld.long 0x4C 8. "TIM13EN,TIM13 peripherals clocks" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' disables the peripherals clocks.." bitfld.long 0x4C 7. "TIM12EN,TIM12 peripherals clocks" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' disables the peripherals clocks.." newline bitfld.long 0x4C 6. "I2C5EN,I2C5 peripherals clocks" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' disables the peripherals clocks.." bitfld.long 0x4C 5. "I2C4EN,I2C4 peripherals clocks" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' disables the peripherals clocks.." newline bitfld.long 0x4C 4. "I2C3EN,I2C3 peripherals clocks" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' disables the peripherals clocks.." bitfld.long 0x4C 3. "SPI5EN,SPI5 peripherals clocks" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' disables the peripherals clocks.." newline bitfld.long 0x4C 2. "SPI4EN,SPI4 peripherals clocks" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' disables the peripherals clocks.." bitfld.long 0x4C 1. "USART2EN,USART2 peripherals clocks" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' disables the peripherals clocks.." newline bitfld.long 0x4C 0. "USART1EN,USART1 peripherals clocks" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' disables the peripherals clocks.." line.long 0x50 "RCC_MP_AHB2ENSETR,This register may be separately and securely write-protected at a field level depending on" bitfld.long 0x50 8. "USBOEN,USBO peripheral clocks enable" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' enables the peripheral clocks.." bitfld.long 0x50 6. "ADC2EN,ADC2 peripheral clocks enable" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' enables the peripheral clocks.." newline bitfld.long 0x50 5. "ADC1EN,ADC1 peripheral clocks enable" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' enables the peripheral clocks.." bitfld.long 0x50 4. "DMAMUX2EN,DMAMUX2 peripheral clocks enable" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' enables the peripheral clocks.." newline bitfld.long 0x50 3. "DMA3EN,DMA3 peripheral clocks enable" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' enables the peripheral clocks.." bitfld.long 0x50 2. "DMAMUX1EN,DMAMUX1 peripheral clocks enable" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' enables the peripheral clocks.." newline bitfld.long 0x50 1. "DMA2EN,DMA2 peripheral clocks enable" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' enables the peripheral clocks.." bitfld.long 0x50 0. "DMA1EN,DMA1 peripheral clocks enable" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' enables the peripheral clocks.." line.long 0x54 "RCC_MP_AHB2ENCLRR,This register may be separately and securely write-protected at a field level depending on" bitfld.long 0x54 8. "USBOEN,USBO peripheral clocks enable" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' disables the peripheral clocks.." bitfld.long 0x54 6. "ADC2EN,ADC2 peripheral clocks enable" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' disables the peripheral clocks.." newline bitfld.long 0x54 5. "ADC1EN,ADC1 peripheral clocks enable" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' disables the peripheral clocks.." bitfld.long 0x54 4. "DMAMUX2EN,DMAMUX2 peripheral clocks enable" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' disables the peripheral clocks.." newline bitfld.long 0x54 3. "DMA3EN,DMA3 peripheral clocks enable" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' disables the peripheral clocks.." bitfld.long 0x54 2. "DMAMUX1EN,DMAMUX1 peripheral clocks enable" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' disables the peripheral clocks.." newline bitfld.long 0x54 1. "DMA2EN,DMA2 peripheral clocks enable" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' disables the peripheral clocks.." bitfld.long 0x54 0. "DMA1EN,DMA1 peripheral clocks enable" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' disables the peripheral clocks.." group.long 0x760++0x37 line.long 0x0 "RCC_MP_AHB4ENSETR,This register may be write-protected depending on the secure state of the TSC peripheral." bitfld.long 0x0 15. "TSCEN,TSC peripheral clocks enable" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' enables the peripheral clocks.." line.long 0x4 "RCC_MP_AHB4ENCLRR,This register may be write-protected depending on the secure state of the TSC peripheral." bitfld.long 0x4 15. "TSCEN,TSC peripheral clocks enable" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' disables the peripheral clocks.." line.long 0x8 "RCC_MP_S_AHB4ENSETR,This is a secure register. for enabling the clock of the secure (AHB4) GPIO ports. as defined" bitfld.long 0x8 8. "GPIOIEN,GPIOI peripheral clocks enable" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' enables the peripheral clocks.." bitfld.long 0x8 7. "GPIOHEN,GPIOH peripheral clocks enable" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' enables the peripheral clocks.." newline bitfld.long 0x8 6. "GPIOGEN,GPIOG peripheral clocks enable" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' enables the peripheral clocks.." bitfld.long 0x8 5. "GPIOFEN,GPIOF peripheral clocks enable" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' enables the peripheral clocks.." newline bitfld.long 0x8 4. "GPIOEEN,GPIOE peripheral clocks enable" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' enables the peripheral clocks.." bitfld.long 0x8 3. "GPIODEN,GPIOD peripheral clocks enable" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' enables the peripheral clocks.." newline bitfld.long 0x8 2. "GPIOCEN,GPIOC peripheral clocks enable" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' enables the peripheral clocks.." bitfld.long 0x8 1. "GPIOBEN,GPIOB peripheral clocks enable" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' enables the peripheral clocks.." newline bitfld.long 0x8 0. "GPIOAEN,GPIOA peripheral clocks enable" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' enables the peripheral clocks.." line.long 0xC "RCC_MP_S_AHB4ENCLRR,This is a secure register. for disabling of the secure (AHB4) GPIO ports. as defined by the" bitfld.long 0xC 8. "GPIOIEN,GPIOI peripheral clocks enable" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' enables the peripheral clocks.." bitfld.long 0xC 7. "GPIOHEN,GPIOH peripheral clocks enable" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' enables the peripheral clocks.." newline bitfld.long 0xC 6. "GPIOGEN,GPIOG peripheral clocks enable" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' enables the peripheral clocks.." bitfld.long 0xC 5. "GPIOFEN,GPIOF peripheral clocks enable" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' enables the peripheral clocks.." newline bitfld.long 0xC 4. "GPIOEEN,GPIOE peripheral clocks enable" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' enables the peripheral clocks.." bitfld.long 0xC 3. "GPIODEN,GPIOD peripheral clocks enable" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' enables the peripheral clocks.." newline bitfld.long 0xC 2. "GPIOCEN,GPIOC peripheral clocks enable" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' enables the peripheral clocks.." bitfld.long 0xC 1. "GPIOBEN,GPIOB peripheral clocks enable" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' enables the peripheral clocks.." newline bitfld.long 0xC 0. "GPIOAEN,GPIOA peripheral clocks enable" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' enables the peripheral clocks.." line.long 0x10 "RCC_MP_NS_AHB4ENSETR,This is a non-secure register. for enabling the non-secure GPIO ports. as defined by the" bitfld.long 0x10 8. "GPIOIEN,GPIOI peripheral clocks enable" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' enables the peripheral clocks.." bitfld.long 0x10 7. "GPIOHEN,GPIOH peripheral clocks enable" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' enables the peripheral clocks.." newline bitfld.long 0x10 6. "GPIOGEN,GPIOG peripheral clocks enable" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' enables the peripheral clocks.." bitfld.long 0x10 5. "GPIOFEN,GPIOF peripheral clocks enable" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' enables the peripheral clocks.." newline bitfld.long 0x10 4. "GPIOEEN,GPIOE peripheral clocks enable" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' enables the peripheral clocks.." bitfld.long 0x10 3. "GPIODEN,GPIOD peripheral clocks enable" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' enables the peripheral clocks.." newline bitfld.long 0x10 2. "GPIOCEN,GPIOC peripheral clocks enable" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' enables the peripheral clocks.." bitfld.long 0x10 1. "GPIOBEN,GPIOB peripheral clocks enable" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' enables the peripheral clocks.." newline bitfld.long 0x10 0. "GPIOAEN,GPIOA peripheral clocks enable" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' enables the peripheral clocks.." line.long 0x14 "RCC_MP_NS_AHB4ENCLRR,This is a non-secure register. for disabling the non-secure GPIO ports. as defined by the" bitfld.long 0x14 8. "GPIOIEN,GPIOI peripheral clocks enable" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' disables the peripheral clocks.." bitfld.long 0x14 7. "GPIOHEN,GPIOH peripheral clocks enable" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' disables the peripheral clocks.." newline bitfld.long 0x14 6. "GPIOGEN,GPIOG peripheral clocks enable" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' disables the peripheral clocks.." bitfld.long 0x14 5. "GPIOFEN,GPIOF peripheral clocks enable" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' disables the peripheral clocks.." newline bitfld.long 0x14 4. "GPIOEEN,GPIOE peripheral clocks enable" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' disables the peripheral clocks.." bitfld.long 0x14 3. "GPIODEN,GPIOD peripheral clocks enable" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' disables the peripheral clocks.." newline bitfld.long 0x14 2. "GPIOCEN,GPIOC peripheral clocks enable" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' disables the peripheral clocks.." bitfld.long 0x14 1. "GPIOBEN,GPIOB peripheral clocks enable" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' disables the peripheral clocks.." newline bitfld.long 0x14 0. "GPIOAEN,GPIOA peripheral clocks enable" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' disables the peripheral clocks.." line.long 0x18 "RCC_MP_AHB5ENSETR,This register may be separately and securely write-protected at a field level. as detailed in" bitfld.long 0x18 16. "AXIMCEN,AXIMC clocks enable" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' enables the peripheral clocks.." bitfld.long 0x18 8. "BKPSRAMEN,BKPSRAM clocks enable" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' enables the peripheral clocks.." newline bitfld.long 0x18 6. "RNG1EN,RNG1 peripheral clocks enable" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' enables the peripheral clocks.." bitfld.long 0x18 5. "HASH1EN,HASH peripheral clocks enable" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' enables the peripheral clocks.." newline bitfld.long 0x18 4. "CRYP1EN,CRYP (3DES/AES) peripheral clocks enable" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' enables the peripheral clocks.." bitfld.long 0x18 3. "SAESEN,SAES peripheral clocks enable" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' enables the peripheral clocks.." newline bitfld.long 0x18 2. "PKAEN,PKA peripheral clocks enable" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' enables the peripheral clocks.." line.long 0x1C "RCC_MP_AHB5ENCLRR,This register may be separately and securely write-protected at a field level. as detailed in" bitfld.long 0x1C 16. "AXIMCEN,AXIMC clocks enable" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' disables the peripheral clocks.." bitfld.long 0x1C 8. "BKPSRAMEN,BKPSRAM clocks enable" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' disables the peripheral clocks.." newline bitfld.long 0x1C 6. "RNG1EN,RNG1 peripheral clocks enable" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' disables the peripheral clocks.." bitfld.long 0x1C 5. "HASH1EN,HASH peripheral clocks enable" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' disables the peripheral clocks.." newline bitfld.long 0x1C 4. "CRYP1EN,CRYP (3DES/AES) peripheral clocks enable" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' disables the peripheral clocks.." bitfld.long 0x1C 3. "SAESEN,SAES peripheral clocks enable" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' disables the peripheral clocks.." newline bitfld.long 0x1C 2. "PKAEN,PKA peripheral clocks enable" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' disables the peripheral clocks.." line.long 0x20 "RCC_MP_AHB6ENSETR,This register may be separately and securely write-protected at a field level. as detailed in" bitfld.long 0x20 30. "ETH2MACEN,ETH2 MAC bus interface clock enable (hclk6 and aclk)" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' enables the bus interface clock.." bitfld.long 0x20 29. "ETH2RXEN,ETH2 reception clock enable" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' enables the reception clock reading.." newline bitfld.long 0x20 28. "ETH2TXEN,ETH2 transmission clock enable" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' enables the transmission clock.." bitfld.long 0x20 27. "ETH2CKEN,Enable of the ETH2 clock generated by the RCC (eth2_ker_ck)" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' enables the eth2_ker_ck clock.." newline bitfld.long 0x20 24. "USBHEN,USBH peripheral clocks enable" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' enables the peripheral clocks.." bitfld.long 0x20 20. "CRC1EN,CRC peripheral clocks enable" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' enables the peripheral clocks.." newline bitfld.long 0x20 17. "SDMMC2EN,SDMMC2 and SDMMC2 delay (DLYBSD2) block peripheral clocks enable" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' enables the peripheral clocks.." bitfld.long 0x20 16. "SDMMC1EN,SDMMC1 and SDMMC1 delay (DLYBSD1) block peripheral clocks enable" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' enables the peripheral clocks.." newline bitfld.long 0x20 14. "QSPIEN,QUADSPI peripheral clocks enable" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' enables the peripheral clocks.." bitfld.long 0x20 12. "FMCEN,FMC peripheral clocks enable" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' enables the peripheral clocks.." newline bitfld.long 0x20 10. "ETH1MACEN,ETH1 MAC bus interface clock enable (hclk6 and aclk)" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' enables the bus interface clock.." bitfld.long 0x20 9. "ETH1RXEN,ETH1 reception clock enable" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' enables the reception clock reading.." newline bitfld.long 0x20 8. "ETH1TXEN,ETH1 transmission clock enable" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' enables the transmission clock.." bitfld.long 0x20 7. "ETH1CKEN,Enable of the ETH1 clock generated by the RCC (eth1_ker_ck)" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' enables the eth1_ker_ck clock.." newline bitfld.long 0x20 1. "MCEEN,MCE peripheral clocks enable" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' enables the peripheral clocks.." line.long 0x24 "RCC_MP_AHB6ENCLRR,This register may be separately and securely write-protected at a field level. as detailed in" bitfld.long 0x24 30. "ETH2MACEN,ETH2 MAC bus interface clock enable (hclk6 and aclk)" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' disables the bus interface clock.." bitfld.long 0x24 29. "ETH2RXEN,ETH2 reception clock enable" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' disables the reception clock reading.." newline bitfld.long 0x24 28. "ETH2TXEN,ETH2 transmission clock enable" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' disables the transmission clock.." bitfld.long 0x24 27. "ETH2CKEN,Enable of the ETH2 clock generated by the RCC (eth2_ker_ck)" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' disables the eth2_ker_ck clock.." newline bitfld.long 0x24 24. "USBHEN,USBH peripheral clocks enable" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' disables the peripheral clocks.." bitfld.long 0x24 20. "CRC1EN,CRC peripheral clocks enable" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' disables the peripheral clocks.." newline bitfld.long 0x24 17. "SDMMC2EN,SDMMC2 and SDMMC2 delay (DLYBSD2) block peripheral clocks enable" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' disables the peripheral clocks.." bitfld.long 0x24 16. "SDMMC1EN,SDMMC1 and SDMMC1 delay (DLYBSD1) block peripheral clocks enable" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' disables the peripheral clocks.." newline bitfld.long 0x24 14. "QSPIEN,QUADSPI peripheral clocks enable" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' disables the peripheral clocks.." bitfld.long 0x24 12. "FMCEN,FMC peripheral clocks enable" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' disables the peripheral clocks.." newline bitfld.long 0x24 10. "ETH1MACEN,ETH1 MAC bus interface clock enable (hclk6 and aclk)" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' disables the bus interface clock.." bitfld.long 0x24 9. "ETH1RXEN,ETH1 reception clock enable" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' disables the reception clock reading.." newline bitfld.long 0x24 8. "ETH1TXEN,ETH1 transmission clock enable" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' disables the transmission clock.." bitfld.long 0x24 7. "ETH1CKEN,Enable of the ETH1 clock generated by the RCC (eth1_ker_ck)" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' disables the eth1_ker_ck clock.." newline bitfld.long 0x24 1. "MCEEN,MCE peripheral clocks enable" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' disables the peripheral clocks.." line.long 0x28 "RCC_MP_S_AHB6ENSETR,This is a secure register for enabling the clock of the MDMA when it is used as secure. A" bitfld.long 0x28 0. "MDMAEN,MDMA peripheral clocks enable" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' enables the peripheral clocks.." line.long 0x2C "RCC_MP_S_AHB6ENCLRR,This is a secure register for disabling the clock of the MDMA when it is not used as secure." bitfld.long 0x2C 0. "MDMAEN,MDMA peripheral clocks enable" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' disables the peripheral clocks.." line.long 0x30 "RCC_MP_NS_AHB6ENSETR,This is a non-secure register for enabling the clock of the MDMA when it is used as non-" bitfld.long 0x30 0. "MDMAEN,MDMA peripheral clocks enable" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' enables the peripheral clocks.." line.long 0x34 "RCC_MP_NS_AHB6ENCLRR,This is a non-secure register for disabling the clock of the MDMA when it is not used as non-" bitfld.long 0x34 0. "MDMAEN,MDMA peripheral clocks enable" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' enables the peripheral clocks.." group.long 0x800++0x5F line.long 0x0 "RCC_MP_APB1LPENSETR,This register is used in order to set the PERxLPEN bit of the corresponding peripheral." bitfld.long 0x0 26. "SPDIFLPEN,SPDIFRX peripheral clocks enable during CSleep mode" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' enables the peripheral clocks in.." bitfld.long 0x0 22. "I2C2LPEN,I2C2 peripheral clocks enable during CSleep mode" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' enables the peripheral clocks in.." newline bitfld.long 0x0 21. "I2C1LPEN,I2C1 peripheral clocks enable during CSleep mode" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' enables the peripheral clocks in.." bitfld.long 0x0 19. "UART8LPEN,UART8 peripheral clocks enable during CSleep mode" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' enables the peripheral clocks in.." newline bitfld.long 0x0 18. "UART7LPEN,UART7 peripheral clocks enable during CSleep mode" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' enables the peripheral clocks in.." bitfld.long 0x0 17. "UART5LPEN,UART5 peripheral clocks enable during CSleep mode" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' enables the peripheral clocks in.." newline bitfld.long 0x0 16. "UART4LPEN,UART4 peripheral clocks enable during CSleep mode" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' enables the peripheral clocks in.." bitfld.long 0x0 15. "USART3LPEN,USART3 peripheral clocks enable during CSleep mode" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' enables the peripheral clocks in.." newline bitfld.long 0x0 12. "SPI3LPEN,SPI3 peripheral clocks enable during CSleep mode" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' enables the peripheral clocks in.." bitfld.long 0x0 11. "SPI2LPEN,SPI2 peripheral clocks enable during CSleep mode" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' enables the peripheral clocks in.." newline bitfld.long 0x0 9. "LPTIM1LPEN,LPTIM1 peripheral clocks enable during CSleep mode" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' enables the peripheral clocks in.." bitfld.long 0x0 5. "TIM7LPEN,TIM7 peripheral clocks enable during CSleep mode" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' enables the peripheral clocks in.." newline bitfld.long 0x0 4. "TIM6LPEN,TIM6 peripheral clocks enable during CSleep mode" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' enables the peripheral clocks in.." bitfld.long 0x0 3. "TIM5LPEN,TIM5 peripheral clocks enable during CSleep mode" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' enables the peripheral clocks in.." newline bitfld.long 0x0 2. "TIM4LPEN,TIM4 peripheral clocks enable during CSleep mode" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' enables the peripheral clocks in.." bitfld.long 0x0 1. "TIM3LPEN,TIM3 peripheral clocks enable during CSleep mode" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' enables the peripheral clocks in.." newline bitfld.long 0x0 0. "TIM2LPEN,TIM2 peripheral clocks enable during CSleep mode" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' enables the peripheral clocks in.." line.long 0x4 "RCC_MP_APB1LPENCLRR,This register is used in order to clear the PERxLPEN bit of the corresponding peripheral." bitfld.long 0x4 26. "SPDIFLPEN,SPDIFRX peripheral clocks enable during CSleep mode" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' disables the peripheral clocks in.." bitfld.long 0x4 22. "I2C2LPEN,I2C2 peripheral clocks enable during CSleep mode" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' disables the peripheral clocks in.." newline bitfld.long 0x4 21. "I2C1LPEN,I2C1 peripheral clocks enable during CSleep mode" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' disables the peripheral clocks in.." bitfld.long 0x4 19. "UART8LPEN,UART8 peripheral clocks enable during CSleep mode" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' disables the peripheral clocks in.." newline bitfld.long 0x4 18. "UART7LPEN,UART7 peripheral clocks enable during CSleep mode" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' disables the peripheral clocks in.." bitfld.long 0x4 17. "UART5LPEN,UART5 peripheral clocks enable during CSleep mode" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' disables the peripheral clocks in.." newline bitfld.long 0x4 16. "UART4LPEN,UART4 peripheral clocks enable during CSleep mode" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' disables the peripheral clocks in.." bitfld.long 0x4 15. "USART3LPEN,USART3 peripheral clocks enable during CSleep mode" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' disables the peripheral clocks in.." newline bitfld.long 0x4 12. "SPI3LPEN,SPI3 peripheral clocks enable during CSleep mode" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' disables the peripheral clocks in.." bitfld.long 0x4 11. "SPI2LPEN,SPI2 peripheral clocks enable during CSleep mode" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' disables the peripheral clocks in.." newline bitfld.long 0x4 9. "LPTIM1LPEN,LPTIM1 peripheral clocks enable during CSleep mode" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' disables the peripheral clocks in.." bitfld.long 0x4 5. "TIM7LPEN,TIM7 peripheral clocks enable during CSleep mode" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' disables the peripheral clocks in.." newline bitfld.long 0x4 4. "TIM6LPEN,TIM6 peripheral clocks enable during CSleep mode" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' disables the peripheral clocks in.." bitfld.long 0x4 3. "TIM5LPEN,TIM5 peripheral clocks enable during CSleep mode" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' disables the peripheral clocks in.." newline bitfld.long 0x4 2. "TIM4LPEN,TIM4 peripheral clocks enable during CSleep mode" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' disables the peripheral clocks in.." bitfld.long 0x4 1. "TIM3LPEN,TIM3 peripheral clocks enable during CSleep mode" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' disables the peripheral clocks in.." newline bitfld.long 0x4 0. "TIM2LPEN,TIM2 peripheral clocks enable during CSleep mode" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' disables the peripheral clocks in.." line.long 0x8 "RCC_MP_APB2LPENSETR,This register is used in order to set the PERxLPEN bit of the corresponding peripheral." bitfld.long 0x8 24. "FDCANLPEN,FDCAN and CANRAM peripheral clocks enable during CSleep mode" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' enables the peripheral clocks in.." bitfld.long 0x8 21. "ADFSDMLPEN,Audio DFSDM peripheral clocks enable during CSleep mode" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' enables the peripheral clocks in.." newline bitfld.long 0x8 20. "DFSDMLPEN,DFSDM peripheral clocks enable during CSleep mode" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' enables the peripheral clocks in.." bitfld.long 0x8 17. "SAI2LPEN,SAI2 peripheral clocks enable during CSleep mode" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' enables the peripheral clocks in.." newline bitfld.long 0x8 16. "SAI1LPEN,SAI1 peripheral clocks enable during CSleep mode" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' enables the peripheral clocks in.." bitfld.long 0x8 13. "USART6LPEN,USART6 peripheral clocks enable during CSleep mode" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' enables the peripheral clocks in.." newline bitfld.long 0x8 8. "SPI1LPEN,SPI/I2S1 peripheral clocks enable during CSleep mode" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' enables the peripheral clocks in.." bitfld.long 0x8 1. "TIM8LPEN,TIM8 peripheral clocks enable during CSleep mode" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' enables the peripheral clocks in.." newline bitfld.long 0x8 0. "TIM1LPEN,TIM1 peripheral clocks enable during CSleep mode" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' enables the peripheral clocks in.." line.long 0xC "RCC_MP_APB2LPENCLRR,This register is used in order to clear the PERxLPEN bit of the corresponding peripheral." bitfld.long 0xC 24. "FDCANLPEN,FDCAN and CANRAM peripheral clocks enable during CSleep mode" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' disables the peripheral clocks in.." bitfld.long 0xC 21. "ADFSDMLPEN,Audio DFSDM peripheral clocks enable during CSleep mode" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' disables the peripheral clocks in.." newline bitfld.long 0xC 20. "DFSDMLPEN,DFSDM peripheral clocks enable during CSleep mode" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' disables the peripheral clocks in.." bitfld.long 0xC 17. "SAI2LPEN,SAI2 peripheral clocks enable during CSleep mode" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' disables the peripheral clocks in.." newline bitfld.long 0xC 16. "SAI1LPEN,SAI1 peripheral clocks enable during CSleep mode" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' disables the peripheral clocks in.." bitfld.long 0xC 13. "USART6LPEN,USART6 peripheral clocks enable during CSleep mode" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' disables the peripheral clocks in.." newline bitfld.long 0xC 8. "SPI1LPEN,SPI/I2S1 peripheral clocks enable during CSleep mode" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' disables the peripheral clocks in.." bitfld.long 0xC 1. "TIM8LPEN,TIM8 peripheral clocks enable during CSleep mode" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' disables the peripheral clocks in.." newline bitfld.long 0xC 0. "TIM1LPEN,TIM1 peripheral clocks enable during CSleep mode" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' disables the peripheral clocks in.." line.long 0x10 "RCC_MP_APB3LPENSETR,This register may be separately and securely write-protected at a field level. as detailed in" bitfld.long 0x10 17. "PMBCTRLLPEN,PMBCTRL peripheral clocks enable during CSeep mode" "0,1" bitfld.long 0x10 16. "DTSLPEN,DTS peripheral clocks enable during CSleep mode" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' enables the peripheral clocks in.." newline bitfld.long 0x10 13. "VREFLPEN,VREF peripheral clocks enable during CSleep mode" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' enables the peripheral clocks in.." bitfld.long 0x10 3. "LPTIM5LPEN,LPTIM5 peripheral clocks enable during CSleep mode" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' enables the peripheral clocks in.." newline bitfld.long 0x10 2. "LPTIM4LPEN,LPTIM4 peripheral clocks enable during CSleep mode" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' enables the peripheral clocks in.." bitfld.long 0x10 1. "LPTIM3LPEN,LPTIM3 peripheral clocks enable during CSleep mode" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' enables the peripheral clocks in.." newline bitfld.long 0x10 0. "LPTIM2LPEN,LPTIM2 peripheral clocks enable during CSleep mode" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' enables the peripheral clocks in.." line.long 0x14 "RCC_MP_APB3LPENCLRR,This register may be separately and securely write-protected at a field level. as detailed in" bitfld.long 0x14 17. "PMBCTRLLPEN,PMBCTRL peripheral clocks enable during CSeep mode" "0,1" bitfld.long 0x14 16. "DTSLPEN,DTS peripheral clocks enable during CSleep mode" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' disables the peripheral clocks in.." newline bitfld.long 0x14 13. "VREFLPEN,VREF peripheral clocks enable during CSleep mode" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' disables the peripheral clocks in.." bitfld.long 0x14 3. "LPTIM5LPEN,LPTIM5 peripheral clocks enable during CSleep mode" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' disables the peripheral clocks in.." newline bitfld.long 0x14 2. "LPTIM4LPEN,LPTIM4 peripheral clocks enable during CSleep mode" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' disables the peripheral clocks in.." bitfld.long 0x14 1. "LPTIM3LPEN,LPTIM3 peripheral clocks enable during CSleep mode" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' disables the peripheral clocks in.." newline bitfld.long 0x14 0. "LPTIM2LPEN,LPTIM2 peripheral clocks enable during CSleep mode" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' disables the peripheral clocks in.." line.long 0x18 "RCC_MP_S_APB3LPENSETR,This is a secure register for enabling the clock of the SYSCFG. A write access to this" bitfld.long 0x18 0. "SYSCFGLPEN,SYSCFG peripheral clocks enable during CSleep mode" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' enables the peripheral clocks in.." line.long 0x1C "RCC_MP_S_APB3LPENCLRR,This is a secure register for disabling the clock of the SYSCFG. A write access to this" bitfld.long 0x1C 0. "SYSCFGLPEN,SYSCFG peripheral clocks enable during CSleep mode" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' disables the peripheral clocks in.." line.long 0x20 "RCC_MP_NS_APB3LPENSETR,This is a non-secure register. for enabling the clock of the SYSCFG." bitfld.long 0x20 0. "SYSCFGLPEN,SYSCFG peripheral clocks enable during CSleep mode" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' enables the peripheral clocks in.." line.long 0x24 "RCC_MP_NS_APB3LPENCLRR,This is a non-secure register. for disabling the clock of the SYSCFG." bitfld.long 0x24 0. "SYSCFGLPEN,SYSCFG peripheral clocks enable during CSleep mode" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' disables the peripheral clocks in.." line.long 0x28 "RCC_MP_APB4LPENSETR,This register may be separately and securely write-protected at a field level. as detailed in" bitfld.long 0x28 21. "STGENROSTPEN,STGEN read-only interface peripheral clocks enable during CStop mode" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' enables the pclk4 and the kernel.." bitfld.long 0x28 20. "STGENROLPEN,STGEN read-only interface peripheral clocks enable during CSleep mode" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' enables the pclk4 and the kernel.." newline bitfld.long 0x28 16. "USBPHYLPEN,USBPHYC peripheral clocks enable during CSleep mode" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' enables the peripheral clocks in.." bitfld.long 0x28 15. "IWDG2APBLPEN,IWDG2 APB clock enable during CSleep mode" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' enables the APB clock in CSleep.." newline bitfld.long 0x28 8. "DDRPERFMLPEN,DDRPERFM APB clock enable during CSleep mode" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' enables the APB clock in CSleep.." bitfld.long 0x28 1. "DCMIPPLPEN,DCMIPP peripheral clocks enable during CSleep mode" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' enables the peripheral clocks in.." line.long 0x2C "RCC_MP_APB4LPENCLRR,This register may be separately and securely write-protected at a field level. as detailed in" bitfld.long 0x2C 21. "STGENROSTPEN,STGEN read-only interface peripheral clocks enable during CStop mode" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' disables the pclk4 and the kernel.." bitfld.long 0x2C 20. "STGENROLPEN,STGEN read-only interface peripheral clocks enable during CSleep mode" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' disables the pclk4 and the kernel.." newline bitfld.long 0x2C 16. "USBPHYLPEN,USBPHYC peripheral clocks enable during CSleep mode" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' disables the peripheral clocks in.." bitfld.long 0x2C 15. "IWDG2APBLPEN,IWDG2 APB clock enable during CSleep mode" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' disables the APB clock in CSleep.." newline bitfld.long 0x2C 8. "DDRPERFMLPEN,DDRPERFM APB clock enable during CSleep mode" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' disables the APB clock in CSleep.." bitfld.long 0x2C 1. "DCMIPPLPEN,DCMIPP peripheral clocks enable during CSleep mode" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' disables the peripheral clocks in.." line.long 0x30 "RCC_MP_S_APB4LPENSETR,This is a secure register for enabling the clock of the LTDC when it is used with a secure" bitfld.long 0x30 0. "LTDCLPEN,LTDC peripheral clocks enable during CSleep mode" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' enables the peripheral clocks in.." line.long 0x34 "RCC_MP_S_APB4LPENCLRR,This is a secure register for disabling the clock of the LTDC when it is used with a secure" bitfld.long 0x34 0. "LTDCLPEN,LTDC peripheral clocks enable during CSleep mode" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' disables the peripheral clocks in.." line.long 0x38 "RCC_MP_NS_APB4LPENSETR,This is a non-secure register. for enabling the clock of the LTDC when it is used with one or" bitfld.long 0x38 0. "LTDCLPEN,LTDC peripheral clocks enable during CSleep mode" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' enables the peripheral clocks in.." line.long 0x3C "RCC_MP_NS_APB4LPENCLRR,This is a non-secure register. for disabling the clock of the LTDC when it is used with one or" bitfld.long 0x3C 0. "LTDCLPEN,LTDC peripheral clocks enable during CSleep mode" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' disables the peripheral clocks in.." line.long 0x40 "RCC_MP_APB5LPENSETR,This register may be separately and securely write-protected at a field level. as detailed in" bitfld.long 0x40 21. "STGENCSTPEN,STGEN controller part peripheral clocks enable during CStop mode" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' enables the pclk5 and the kernel.." bitfld.long 0x40 20. "STGENCLPEN,STGEN controller part peripheral clocks enable during CSleep mode" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' enables the pclk5 and the kernel.." newline bitfld.long 0x40 16. "BSECLPEN,BSEC peripheral clocks enable during CSleep mode" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' enables the peripheral clocks in.." bitfld.long 0x40 15. "IWDG1APBLPEN,IWDG1 APB clock enable during CSleep mode" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' enables the APB clock in CSleep.." newline bitfld.long 0x40 13. "ETZPCLPEN,ETZPC peripheral clocks enable during CSleep mode" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' enables the peripheral clocks in.." bitfld.long 0x40 11. "TZCLPEN,TZC clocks enable during CSleep mode" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' enables the pclk5 and aclk_tzc1.." newline bitfld.long 0x40 8. "RTCAPBLPEN,RTC APB clock enable during CSleep mode" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' enables the peripheral clocks in.." line.long 0x44 "RCC_MP_APB5LPENCLRR,This register may be separately and securely write-protected at a field level. as detailed in" bitfld.long 0x44 21. "STGENCSTPEN,STGEN controller part peripheral clocks enable during CStop mode" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' disables the pclk5 and the kernel.." bitfld.long 0x44 20. "STGENCLPEN,STGEN controller part peripheral clocks enable during CSleep mode" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' disables the pclk5 and the kernel.." newline bitfld.long 0x44 16. "BSECLPEN,BSEC peripheral clocks enable during CSleep mode" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' disables the peripheral clocks in.." bitfld.long 0x44 15. "IWDG1APBLPEN,IWDG1 APB clock enable during CSleep mode" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' disables the APB clock in CSleep.." newline bitfld.long 0x44 13. "ETZPCLPEN,ETZPC peripheral clocks enable during CSleep mode" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' disables the peripheral clocks in.." bitfld.long 0x44 11. "TZCLPEN,TZC clocks enable during CSleep mode" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' disables the pclk5 and aclk_tzc1.." newline bitfld.long 0x44 8. "RTCAPBLPEN,RTC APB clock enable during CSleep mode" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' disables the peripheral clocks in.." line.long 0x48 "RCC_MP_APB6LPENSETR,This register may be separately and securely write-protected at a field level depending on" bitfld.long 0x48 12. "TIM17LPEN,TIM17 peripherals clocks during CSleep mode" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' enables the peripherals clocks in.." bitfld.long 0x48 11. "TIM16LPEN,TIM16 peripherals clocks during CSleep mode" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' enables the peripherals clocks in.." newline bitfld.long 0x48 10. "TIM15LPEN,TIM15 peripherals clocks during CSleep mode" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' enables the peripherals clocks in.." bitfld.long 0x48 9. "TIM14LPEN,TIM14 peripherals clocks during CSleep mode" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' enables the peripherals clocks in.." newline bitfld.long 0x48 8. "TIM13LPEN,TIM13 peripherals clocks during CSleep mode" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' enables the peripherals clocks in.." bitfld.long 0x48 7. "TIM12LPEN,TIM12 peripherals clocks during CSleep mode" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' enables the peripherals clocks in.." newline bitfld.long 0x48 6. "I2C5LPEN,I2C5 peripherals clocks during CSleep mode" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' enables the peripherals clocks in.." bitfld.long 0x48 5. "I2C4LPEN,I2C4 peripherals clocks during CSleep mode" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' enables the peripherals clocks in.." newline bitfld.long 0x48 4. "I2C3LPEN,I2C3 peripherals clocks during CSleep mode" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' enables the peripherals clocks in.." bitfld.long 0x48 3. "SPI5LPEN,SPI5 peripherals clocks during CSleep mode" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' enables the peripherals clocks in.." newline bitfld.long 0x48 2. "SPI4LPEN,SPI4 peripherals clocks during CSleep mode" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' enables the peripherals clocks in.." bitfld.long 0x48 1. "USART2LPEN,USART2 peripherals clocks during CSleep mode" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' enables the peripherals clocks in.." newline bitfld.long 0x48 0. "USART1LPEN,USART1 peripherals clocks during CSleep mode" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' enables the peripherals clocks in.." line.long 0x4C "RCC_MP_APB6LPENCLRR,This register may be separately and securely write-protected at a field level depending on" bitfld.long 0x4C 12. "TIM17LPEN,TIM17 peripherals clocks during CSleep mode" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' disables the peripherals clocks in.." bitfld.long 0x4C 11. "TIM16LPEN,TIM16 peripherals clocks during CSleep mode" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' disables the peripherals clocks in.." newline bitfld.long 0x4C 10. "TIM15LPEN,TIM15 peripherals clocks during CSleep mode" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' disables the peripherals clocks in.." bitfld.long 0x4C 9. "TIM14LPEN,TIM14 peripherals clocks during CSleep mode" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' disables the peripherals clocks in.." newline bitfld.long 0x4C 8. "TIM13LPEN,TIM13 peripherals clocks during CSleep mode" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' disables the peripherals clocks in.." bitfld.long 0x4C 7. "TIM12LPEN,TIM12 peripherals clocks during CSleep mode" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' disables the peripherals clocks in.." newline bitfld.long 0x4C 6. "I2C5LPEN,I2C5 peripherals clocks during CSleep mode" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' disables the peripherals clocks in.." bitfld.long 0x4C 5. "I2C4LPEN,I2C4 peripherals clocks during CSleep mode" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' disables the peripherals clocks in.." newline bitfld.long 0x4C 4. "I2C3LPEN,I2C3 peripherals clocks during CSleep mode" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' disables the peripherals clocks in.." bitfld.long 0x4C 3. "SPI5LPEN,SPI5 peripherals clocks during CSleep mode" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' disables the peripherals clocks in.." newline bitfld.long 0x4C 2. "SPI4LPEN,SPI4 peripherals clocks during CSleep mode" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' disables the peripherals clocks in.." bitfld.long 0x4C 1. "USART2LPEN,USART2 peripherals clocks during CSleep mode" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' disables the peripherals clocks in.." newline bitfld.long 0x4C 0. "USART1LPEN,USART1 peripherals clocks during CSleep mode" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' disables the peripherals clocks in.." line.long 0x50 "RCC_MP_AHB2LPENSETR,This register may be separately and securely write-protected at a field level depending on" bitfld.long 0x50 8. "USBOLPEN,USBO peripheral clocks enable during Sleep mode" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' enables the peripheral clocks in.." bitfld.long 0x50 6. "ADC2LPEN,ADC2 peripheral clocks enable during Sleep mode" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' enables the peripheral clocks in.." newline bitfld.long 0x50 5. "ADC1LPEN,ADC1 peripheral clocks enable during Sleep mode" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' enables the peripheral clocks in.." bitfld.long 0x50 4. "DMAMUX2LPEN,DMAMUX2 peripheral clocks enable during Sleep mode" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' enables the peripheral clocks in.." newline bitfld.long 0x50 3. "DMA3LPEN,DMA3 peripheral clocks enable during Sleep mode" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' enables the peripheral clocks in.." bitfld.long 0x50 2. "DMAMUX1LPEN,DMAMUX1 peripheral clocks enable during Sleep mode" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' enables the peripheral clocks in.." newline bitfld.long 0x50 1. "DMA2LPEN,DMA2 peripheral clocks enable during Sleep mode" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' enables the peripheral clocks in.." bitfld.long 0x50 0. "DMA1LPEN,DMA1 peripheral clocks enable during Sleep mode" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' enables the peripheral clocks in.." line.long 0x54 "RCC_MP_AHB2LPENCLRR,This register may be separately and securely write-protected at a field level depending on" bitfld.long 0x54 8. "USBOLPEN,USBO peripheral clocks enable during Sleep mode" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' disables the peripheral clocks in.." bitfld.long 0x54 6. "ADC2LPEN,ADC2 peripheral clocks enable during Sleep mode" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' disables the peripheral clocks in.." newline bitfld.long 0x54 5. "ADC1LPEN,ADC1 peripheral clocks enable during Sleep mode" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' disables the peripheral clocks in.." bitfld.long 0x54 4. "DMAMUX2LPEN,DMAMUX2 peripheral clocks enable during Sleep mode" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' disables the peripheral clocks in.." newline bitfld.long 0x54 3. "DMA3LPEN,DMA3 peripheral clocks enable during Sleep mode" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' disables the peripheral clocks in.." bitfld.long 0x54 2. "DMAMUX1LPEN,DMAMUX1 peripheral clocks enable during Sleep mode" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' disables the peripheral clocks in.." newline bitfld.long 0x54 1. "DMA2LPEN,DMA2 peripheral clocks enable during Sleep mode" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' disables the peripheral clocks in.." bitfld.long 0x54 0. "DMA1LPEN,DMA1 peripheral clocks enable during Sleep mode" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' disables the peripheral clocks in.." line.long 0x58 "RCC_MP_AHB4LPENSETR,This register may be write-protected depending on the secure state of the TSC peripheral." bitfld.long 0x58 15. "TSCLPEN,TSC peripheral clocks enable during CSleep mode" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' enables the peripheral clocks in.." line.long 0x5C "RCC_MP_AHB4LPENCLRR,RCC AHB4 Sleep clock enable clear register" bitfld.long 0x5C 15. "TSCLPEN,TSC peripheral clocks enable during CSleep mode" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' disables the peripheral clocks in.." group.long 0x868++0x47 line.long 0x0 "RCC_MP_S_AHB4LPENSETR,This is a secure register. for enabling the clock of the secure (AHB4) GPIO ports. as defined" bitfld.long 0x0 8. "GPIOILPEN,GPIOI peripheral clocks enable during CSleep mode" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' enables the peripheral clocks in.." bitfld.long 0x0 7. "GPIOHLPEN,GPIOH peripheral clocks enable during CSleep mode" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' enables the peripheral clocks in.." newline bitfld.long 0x0 6. "GPIOGLPEN,GPIOG peripheral clocks enable during CSleep mode" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' enables the peripheral clocks in.." bitfld.long 0x0 5. "GPIOFLPEN,GPIOF peripheral clocks enable during CSleep mode" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' enables the peripheral clocks in.." newline bitfld.long 0x0 4. "GPIOELPEN,GPIOE peripheral clocks enable during CSleep mode" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' enables the peripheral clocks in.." bitfld.long 0x0 3. "GPIODLPEN,GPIOD peripheral clocks enable during CSleep mode" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' enables the peripheral clocks in.." newline bitfld.long 0x0 2. "GPIOCLPEN,GPIOC peripheral clocks enable during CSleep mode" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' enables the peripheral clocks in.." bitfld.long 0x0 1. "GPIOBLPEN,GPIOB peripheral clocks enable during CSleep mode" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' enables the peripheral clocks in.." newline bitfld.long 0x0 0. "GPIOALPEN,GPIOA peripheral clocks enable during CSleep mode" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' enables the peripheral clocks in.." line.long 0x4 "RCC_MP_S_AHB4LPENCLRR,This is a secure register. for disabling the clock of the secure (AHB4) GPIO ports" bitfld.long 0x4 8. "GPIOILPEN,GPIOI peripheral clocks enable during CSleep mode" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' disables the peripheral clocks in.." bitfld.long 0x4 7. "GPIOHLPEN,GPIOH peripheral clocks enable during CSleep mode" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' disables the peripheral clocks in.." newline bitfld.long 0x4 6. "GPIOGLPEN,GPIOG peripheral clocks enable during CSleep mode" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' disables the peripheral clocks in.." bitfld.long 0x4 5. "GPIOFLPEN,GPIOF peripheral clocks enable during CSleep mode" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' disables the peripheral clocks in.." newline bitfld.long 0x4 4. "GPIOELPEN,GPIOE peripheral clocks enable during CSleep mode" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' disables the peripheral clocks in.." bitfld.long 0x4 3. "GPIODLPEN,GPIOD peripheral clocks enable during CSleep mode" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' disables the peripheral clocks in.." newline bitfld.long 0x4 2. "GPIOCLPEN,GPIOC peripheral clocks enable during CSleep mode" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' disables the peripheral clocks in.." bitfld.long 0x4 1. "GPIOBLPEN,GPIOB peripheral clocks enable during CSleep mode" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' disables the peripheral clocks in.." newline bitfld.long 0x4 0. "GPIOALPEN,GPIOA peripheral clocks enable during CSleep mode" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' disables the peripheral clocks in.." line.long 0x8 "RCC_MP_NS_AHB4LPENSETR,This is a non-secure register. for enabling the clock of the non-secure (AHB4) GPIO ports." bitfld.long 0x8 8. "GPIOILPEN,GPIOI peripheral clocks enable during CSleep mode" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' enables the peripheral clocks in.." bitfld.long 0x8 7. "GPIOHLPEN,GPIOH peripheral clocks enable during CSleep mode" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' enables the peripheral clocks in.." newline bitfld.long 0x8 6. "GPIOGLPEN,GPIOG peripheral clocks enable during CSleep mode" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' enables the peripheral clocks in.." bitfld.long 0x8 5. "GPIOFLPEN,GPIOF peripheral clocks enable during CSleep mode" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' enables the peripheral clocks in.." newline bitfld.long 0x8 4. "GPIOELPEN,GPIOE peripheral clocks enable during CSleep mode" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' enables the peripheral clocks in.." bitfld.long 0x8 3. "GPIODLPEN,GPIOD peripheral clocks enable during CSleep mode" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' enables the peripheral clocks in.." newline bitfld.long 0x8 2. "GPIOCLPEN,GPIOC peripheral clocks enable during CSleep mode" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' enables the peripheral clocks in.." bitfld.long 0x8 1. "GPIOBLPEN,GPIOB peripheral clocks enable during CSleep mode" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' enables the peripheral clocks in.." newline bitfld.long 0x8 0. "GPIOALPEN,GPIOA peripheral clocks enable during CSleep mode" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' enables the peripheral clocks in.." line.long 0xC "RCC_MP_NS_AHB4LPENCLRR,This is a non-secure register. for disabling the clock of the non-secure (AHB4) GPIO ports." bitfld.long 0xC 8. "GPIOILPEN,GPIOI peripheral clocks enable during CSleep mode" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' disables the peripheral clocks in.." bitfld.long 0xC 7. "GPIOHLPEN,GPIOH peripheral clocks enable during CSleep mode" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' disables the peripheral clocks in.." newline bitfld.long 0xC 6. "GPIOGLPEN,GPIOG peripheral clocks enable during CSleep mode" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' disables the peripheral clocks in.." bitfld.long 0xC 5. "GPIOFLPEN,GPIOF peripheral clocks enable during CSleep mode" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' disables the peripheral clocks in.." newline bitfld.long 0xC 4. "GPIOELPEN,GPIOE peripheral clocks enable during CSleep mode" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' disables the peripheral clocks in.." bitfld.long 0xC 3. "GPIODLPEN,GPIOD peripheral clocks enable during CSleep mode" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' disables the peripheral clocks in.." newline bitfld.long 0xC 2. "GPIOCLPEN,GPIOC peripheral clocks enable during CSleep mode" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' disables the peripheral clocks in.." bitfld.long 0xC 1. "GPIOBLPEN,GPIOB peripheral clocks enable during CSleep mode" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' disables the peripheral clocks in.." newline bitfld.long 0xC 0. "GPIOALPEN,GPIOA peripheral clocks enable during CSleep mode" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' disables the peripheral clocks in.." line.long 0x10 "RCC_MP_AHB5LPENSETR,This register may be separately and securely write-protected at a field level. as detailed in" bitfld.long 0x10 8. "BKPSRAMLPEN,BKPSRAM clocks enable during CSleep mode" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' enables the peripheral clocks in.." bitfld.long 0x10 6. "RNG1LPEN,RNG1 peripheral clocks enable during CSleep mode" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' enables the peripheral clocks in.." newline bitfld.long 0x10 5. "HASH1LPEN,HASH peripheral clocks enable during CSleep mode" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' enables the peripheral clocks in.." bitfld.long 0x10 4. "CRYP1LPEN,CRYP (3DES/AES) peripheral clocks enable during CSleep mode" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' enables the peripheral clocks in.." newline bitfld.long 0x10 3. "SAESLPEN,SAES peripheral clocks enable during CSleep mode" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' enables the peripheral clocks in.." bitfld.long 0x10 2. "PKALPEN,PKA peripheral clocks enable during CSleep mode" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' enables the peripheral clocks in.." line.long 0x14 "RCC_MP_AHB5LPENCLRR,This register may be separately and securely write-protected at a field level. as detailed in" bitfld.long 0x14 8. "BKPSRAMLPEN,BKPSRAM clocks enable during CSleep mode" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' disables the peripheral clocks in.." bitfld.long 0x14 6. "RNG1LPEN,RNG1 peripheral clocks enable during CSleep mode" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' disables the peripheral clocks in.." newline bitfld.long 0x14 5. "HASH1LPEN,HASH peripheral clocks enable during CSleep mode" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' disables the peripheral clocks in.." bitfld.long 0x14 4. "CRYP1LPEN,CRYP (3DES/AES) peripheral clocks enable during CSleep mode" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' disables the peripheral clocks in.." newline bitfld.long 0x14 3. "SAESLPEN,SAES peripheral clocks enable during CSleep mode" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' disables the peripheral clocks in.." bitfld.long 0x14 2. "PKALPEN,PKA peripheral clocks enable during CSleep mode" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' disables the peripheral clocks in.." line.long 0x18 "RCC_MP_AHB6LPENSETR,This register may be separately and securely write-protected at a field level. as detailed in" bitfld.long 0x18 31. "ETH2STPEN,ETH2 peripheral clock enable during CStop mode" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' enables the ETH2_TX_CLK and.." bitfld.long 0x18 30. "ETH2MACLPEN,ETH2 MAC bus interface clock enable during CSleep mode (hclk6 and aclk)" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' enables the bus interface clock in.." newline bitfld.long 0x18 29. "ETH2RXLPEN,ETH2 reception clock enable during CSleep mode" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' enables the reception clock in.." bitfld.long 0x18 28. "ETH2TXLPEN,ETH2 transmission clock enable during CSleep mode" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' enables the transmission clock in.." newline bitfld.long 0x18 27. "ETH2CKLPEN,Enable of the ETH2 clock generated by the RCC (eth2_ker_ck)" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' enables the eth2_ker_ck clock in.." bitfld.long 0x18 24. "USBHLPEN,USBH peripheral clocks enable during CSleep mode" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' enables the peripheral clocks in.." newline bitfld.long 0x18 20. "CRC1LPEN,CRC peripheral clocks enable during CSleep mode" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' enables the peripheral clocks in.." bitfld.long 0x18 17. "SDMMC2LPEN,SDMMC2 and SDMMC2 delay (DLYBSD2) block peripheral clocks enable during CSleep mode" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' enables the peripheral clocks in.." newline bitfld.long 0x18 16. "SDMMC1LPEN,SDMMC1 and SDMMC1 delay (DLYBSD1) block peripheral clocks enable during CSleep mode" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' enables the peripheral clocks in.." bitfld.long 0x18 14. "QSPILPEN,QUADSPI peripheral clocks enable during CSleep mode" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' enables the peripheral clocks in.." newline bitfld.long 0x18 12. "FMCLPEN,FMC peripheral clocks enable during CSleep mode" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' enables the peripheral clocks in.." bitfld.long 0x18 11. "ETH1STPEN,ETH1 peripheral clock enable during CStop mode" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' enables the ETH1_TX_CLK and.." newline bitfld.long 0x18 10. "ETH1MACLPEN,ETH1 MAC bus interface clock enable during CSleep mode (hclk6 and aclk)" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' enables the bus interface clock in.." bitfld.long 0x18 9. "ETH1RXLPEN,ETH1 reception clock enable during CSleep mode" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' enables the reception clock in.." newline bitfld.long 0x18 8. "ETH1TXLPEN,ETH1 transmission clock enable during CSleep mode" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' enables the transmission clock in.." bitfld.long 0x18 7. "ETH1CKLPEN,Enable of the ETH1 clock generated by the RCC (eth1_ker_ck)" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' enables the eth1_ker_ck clock in.." newline bitfld.long 0x18 1. "MCELPEN,MCE peripheral clocks enable during CSleep mode" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' enables the peripheral clocks in.." line.long 0x1C "RCC_MP_AHB6LPENCLRR,This register may be separately and securely write-protected at a field level." bitfld.long 0x1C 31. "ETH2STPEN,ETH2 peripheral clock enable during CStop mode" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' disables the ETH2_TX_CLK and.." bitfld.long 0x1C 30. "ETH2MACLPEN,ETH2 MAC bus interface clock enable during CSleep mode (hclk6 and aclk)" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' disables the bus interface clock in.." newline bitfld.long 0x1C 29. "ETH2RXLPEN,ETH2 reception clock enable during CSleep mode" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' disables the reception clock in.." bitfld.long 0x1C 28. "ETH2TXLPEN,ETH2 transmission clock enable during CSleep mode" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' disables the transmission clock in.." newline bitfld.long 0x1C 27. "ETH2CKLPEN,Enable of the ETH2 clock generated by the RCC (eth2_ker_ck)" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' disables the eth2_ker_ck clock in.." bitfld.long 0x1C 24. "USBHLPEN,USBH peripheral clocks enable during CSleep mode" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' disables the peripheral clocks in.." newline bitfld.long 0x1C 20. "CRC1LPEN,CRC peripheral clocks enable during CSleep mode" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' disables the peripheral clocks in.." bitfld.long 0x1C 17. "SDMMC2LPEN,SDMMC2 and SDMMC2 delay (DLYBSD2) block peripheral clocks enable during CSleep mode" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' disables the peripheral clocks in.." newline bitfld.long 0x1C 16. "SDMMC1LPEN,SDMMC1 and SDMMC1 delay (DLYBSD1) block peripheral clocks enable during CSleep mode" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' disables the peripheral clocks in.." bitfld.long 0x1C 14. "QSPILPEN,QUADSPI peripheral clocks enable during CSleep mode" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' disables the peripheral clocks in.." newline bitfld.long 0x1C 12. "FMCLPEN,FMC peripheral clocks enable during CSleep mode" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' disables the peripheral clocks in.." bitfld.long 0x1C 11. "ETH1STPEN,ETH1 peripheral clock enable during CStop mode" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' disables the ETH1_TX_CLK and.." newline bitfld.long 0x1C 10. "ETH1MACLPEN,ETH1 MAC bus interface clock enable during CSleep mode (hclk6 and aclk)" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' disables the bus interface clock in.." bitfld.long 0x1C 9. "ETH1RXLPEN,ETH1 reception clock enable during CSleep mode" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' disables the reception clock in.." newline bitfld.long 0x1C 8. "ETH1TXLPEN,ETH1 transmission clock enable during CSleep mode" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' disables the transmission clock in.." bitfld.long 0x1C 7. "ETH1CKLPEN,Enable of the ETH1 clock generated by the RCC (eth1_ker_ck)" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' disables the eth1_ker_ck clock in.." newline bitfld.long 0x1C 1. "MCELPEN,MCE peripheral clocks enable during CSleep mode" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' disables the peripheral clocks in.." line.long 0x20 "RCC_MP_S_AHB6LPENSETR,This is a secure register for enabling the clock of the MDMA in Sleep mode when it is used" bitfld.long 0x20 0. "MDMALPEN,MDMA peripheral clocks enable during CSleep mode" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' enables the peripheral clocks in.." line.long 0x24 "RCC_MP_S_AHB6LPENCLRR,This is a secure register for disabling the clock of the MDMA in Sleep mode when it is not" bitfld.long 0x24 0. "MDMALPEN,MDMA peripheral clocks enable during CSleep mode" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' disables the peripheral clocks in.." line.long 0x28 "RCC_MP_NS_AHB6LPENSETR,This is a non-secure register for enabling the clock of the MDMA in Sleep mode when it is" bitfld.long 0x28 0. "MDMALPEN,MDMA peripheral clocks enable during CSleep mode" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' enables the peripheral clocks in.." line.long 0x2C "RCC_MP_NS_AHB6LPENCLRR,This is a non-secure register for disabling the clock of the MDMA in Sleep mode when it is" bitfld.long 0x2C 0. "MDMALPEN,MDMA peripheral clocks enable during CSleep mode" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' disables the peripheral clocks in.." line.long 0x30 "RCC_MP_S_AXIMLPENSETR,This is a secure register. for enabling the clock of the SYSRAM during CSleep mode. A write" bitfld.long 0x30 0. "SYSRAMLPEN,SYSRAM interface clock enable during CSleep mode" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' enables the memory interface clock.." line.long 0x34 "RCC_MP_S_AXIMLPENCLRR,This is a secure register. for disabling the clock of the SYSRAM during CSleep mode." bitfld.long 0x34 0. "SYSRAMLPEN,SYSRAM interface clock enable during CSleep mode" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' disables the memory interface in.." line.long 0x38 "RCC_MP_NS_AXIMLPENSETR,This is a non-secure register. for enabling the clock of the SYSRAM during CSleep mode." bitfld.long 0x38 0. "SYSRAMLPEN,SYSRAM interface clock enable during CSleep mode" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' enables the memory interface clock.." line.long 0x3C "RCC_MP_NS_AXIMLPENCLRR,This is a non-secure register. for disabling the clock of the SYSRAM during CSleep mode." bitfld.long 0x3C 0. "SYSRAMLPEN,SYSRAM interface clock enable during CSleep mode" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' disables the memory interface in.." line.long 0x40 "RCC_MP_MLAHBLPENSETR,This register may be separately and securely write-protected at a field level. as detailed in" bitfld.long 0x40 2. "SRAM3LPEN,SRAM3 interface clock enable during CSleep mode" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' enables the memory interface clock.." bitfld.long 0x40 1. "SRAM2LPEN,SRAM2 interface clock enable during CSleep mode" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' enables the memory interface clock.." newline bitfld.long 0x40 0. "SRAM1LPEN,SRAM1 interface clock enable during CSleep mode" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' enables the memory interface clock.." line.long 0x44 "RCC_MP_MLAHBLPENCLRR,This register may be separately and securely write-protected at a field level" bitfld.long 0x44 2. "SRAM3LPEN,SRAM3 interface clock enable during CSleep mode" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' disables the memory interface clock.." bitfld.long 0x44 1. "SRAM2LPEN,SRAM2 interface clock enable during CSleep mode" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' disables the memory interface clock.." newline bitfld.long 0x44 0. "SRAM1LPEN,SRAM1 interface clock enable during CSleep mode" "0: Writing '0' has no effect reading '0' means that..,1: Writing '1' disables the memory interface clock.." rgroup.long 0x8C0++0x1F line.long 0x0 "RCC_APB3SECSR,This read register reflects at a bit level the secure state of each APB3 securable peripheral." bitfld.long 0x0 13. "VREFSECF,VREF block secure status flag" "0: peripheral is non-secure,1: peripheral is secure" bitfld.long 0x0 1. "LPTIM3SECF,LPTIM3 block secure status flag" "0: peripheral is non-secure,1: peripheral is secure" newline bitfld.long 0x0 0. "LPTIM2SECF,LPTIM2 block secure status flag" "0: peripheral is non-secure,1: peripheral is secure" line.long 0x4 "RCC_APB4SECSR,This read register reflects at a bit level the secure state of each APB4 securable peripheral." bitfld.long 0x4 16. "USBPHYSECF,USBPHY block secure status flag" "0: peripheral is non-secure,1: peripheral is secure" bitfld.long 0x4 1. "DCMIPPSECF,DCMIPP block secure status flag" "0: peripheral is non-secure,1: peripheral is secure" line.long 0x8 "RCC_APB5SECSR,This read register reflects at a bit level the secure state of each APB5 secure or securable" bitfld.long 0x8 20.--21. "STGENCSECF,STGENC block secure status flag" "0: peripheral is non-secure,?,?,3: peripheral is secure" bitfld.long 0x8 16. "BSECSECF,BSEC block secure status flag" "0: peripheral is non-secure,1: peripheral is secure" newline bitfld.long 0x8 15. "IWDG1SECF,IWDG1 block secure status flag" "0: peripheral is non-secure,1: peripheral is secure" bitfld.long 0x8 13. "ETZPCSECF,ETZPC block secure status flag" "0: peripheral is non-secure,1: peripheral is secure" newline bitfld.long 0x8 11. "TZCSECF,TZC block secure status flag" "0: peripheral is non-secure,1: peripheral is secure" bitfld.long 0x8 8. "RTCSECF,RTC block secure status flag" "0: peripheral is non-secure (default),1: peripheral is secure (at least one RTC.." line.long 0xC "RCC_APB6SECSR,This read register reflects at a bit level the secure state of each APB6 securable peripheral." bitfld.long 0xC 12. "TIM17SECF,TIM17 block secure status flag" "0: peripheral is non-secure,1: peripheral is secure" bitfld.long 0xC 11. "TIM16SECF,TIM16 block secure status flag" "0: peripheral is non-secure,1: peripheral is secure" newline bitfld.long 0xC 10. "TIM15SECF,TIM15 block secure status flag" "0: peripheral is non-secure,1: peripheral is secure" bitfld.long 0xC 9. "TIM14SECF,TIM14 block secure status flag" "0: peripheral is non-secure,1: peripheral is secure" newline bitfld.long 0xC 8. "TIM13SECF,TIM13 block secure status flag" "0: peripheral is non-secure,1: peripheral is secure" bitfld.long 0xC 7. "TIM12SECF,TIM12 block secure status flag" "0: peripheral is non-secure,1: peripheral is secure" newline bitfld.long 0xC 6. "I2C5SECF,I2C5 block secure status flag" "0: peripheral is non-secure,1: peripheral is secure" bitfld.long 0xC 5. "I2C4SECF,I2C4 block secure status flag" "0: peripheral is non-secure,1: peripheral is secure" newline bitfld.long 0xC 4. "I2C3SECF,I2C3 block secure status flag" "0: peripheral is non-secure,1: peripheral is secure" bitfld.long 0xC 3. "SPI5SECF,SPI5 block secure status flag" "0: peripheral is non-secure,1: peripheral is secure" newline bitfld.long 0xC 2. "SPI4SECF,SPI4 block secure status flag" "0: peripheral is non-secure,1: peripheral is secure" bitfld.long 0xC 1. "USART2SECF,USART2 block secure status flag" "0: peripheral is non-secure,1: peripheral is secure" newline bitfld.long 0xC 0. "USART1SECF,USART1 block secure status flag" "0: peripheral is non-secure,1: peripheral is secure" line.long 0x10 "RCC_AHB2SECSR,This read register reflects at a bit level the secure state of each AHB2 securable peripheral." bitfld.long 0x10 8. "USBOSECF,USBO block secure status flag" "0: peripheral is non-secure,1: peripheral is secure" bitfld.long 0x10 6. "ADC2SECF,ADC2 block secure status flag" "0: peripheral is non-secure,1: peripheral is secure" newline bitfld.long 0x10 5. "ADC1SECF,ADC1 block secure status flag" "0: peripheral is non-secure,1: peripheral is secure" bitfld.long 0x10 4. "DMAMUX2SECF,DMAMUX2 block secure status flag" "0: peripheral is non-secure,1: peripheral is secure" newline bitfld.long 0x10 3. "DMA3SECF,DMA3 block secure status flag" "0: peripheral is non-secure,1: peripheral is secure" line.long 0x14 "RCC_AHB4SECSR,This read register reflects at a bit level the secure state of each AHB4 securable peripheral." bitfld.long 0x14 15. "TSCSECF,TSC block secure status flag" "0: peripheral is non-secure,1: peripheral is secure" line.long 0x18 "RCC_AHB5SECSR,This read register reflects at a bit level the secure state of each AHB5 securable peripheral." bitfld.long 0x18 8. "BKPSRAMSECF,BKPSRAM block secure status flag" "0: peripheral is non-secure,1: peripheral is secure" bitfld.long 0x18 6. "RNG1SECF,RNG1 block secure status flag" "0: peripheral is non-secure,1: peripheral is secure" newline bitfld.long 0x18 5. "HASH1SECF,HASH1 block secure status flag" "0: peripheral is non-secure,1: peripheral is secure" bitfld.long 0x18 4. "CRYP1SECF,CRYP1 block secure status flag" "0: peripheral is non-secure,1: peripheral is secure" newline bitfld.long 0x18 3. "SAESSECF,SAES block secure status flag" "0: peripheral is non-secure,1: peripheral is secure" bitfld.long 0x18 2. "PKASECF,PKA block secure status flag" "0: peripheral is non-secure,1: peripheral is secure" line.long 0x1C "RCC_AHB6SECSR,This read register reflects at a bit level the secure state of each AHB6 securable peripheral." hexmask.long.byte 0x1C 27.--31. 1. "ETH2SECF,ETH2 block secure status flag" bitfld.long 0x1C 17. "SDMMC2SECF,SDMMC2 block secure status flag" "0: peripheral is non-secure,1: peripheral is secure" newline bitfld.long 0x1C 16. "SDMMC1SECF,SDMMC1 block secure status flag" "0: peripheral is non-secure,1: peripheral is secure" bitfld.long 0x1C 14. "QSPISECF,QSPI block secure status flag" "0: peripheral is non-secure,1: peripheral is secure" newline bitfld.long 0x1C 12. "FMCSECF,FMC block secure status flag" "0: peripheral is non-secure,1: peripheral is secure" hexmask.long.byte 0x1C 7.--11. 1. "ETH1SECF,ETH1 block secure status flag" newline bitfld.long 0x1C 1. "MCESECF,MCE block secure status flag" "0: peripheral is non-secure,1: peripheral is secure" endif sif (cpuis("STM32MP151*")) group.long 0x0++0x3 line.long 0x0 "RCC_TZCR,This register is used to switch the RCC into secure mode. This register can only be accessed in secure mode." bitfld.long 0x0 1. "MCKPROT,MCKPROT" "0,1" bitfld.long 0x0 0. "TZEN,TZEN" "0,1" group.long 0xC++0x7 line.long 0x0 "RCC_OCENSETR,This register is used to control the oscillators.Writing to this register has no effect. writing will set the corresponding bits. Reading will give the effective values of each bit.If TZEN = MCKPROT = . this register can only be modified.." bitfld.long 0x0 11. "HSECSSON,HSECSSON" "0,1" bitfld.long 0x0 10. "HSEBYP,HSEBYP" "0,1" newline bitfld.long 0x0 9. "HSEKERON,HSEKERON" "0,1" bitfld.long 0x0 8. "HSEON,HSEON" "0,1" newline bitfld.long 0x0 7. "DIGBYP,DIGBYP" "0,1" bitfld.long 0x0 5. "CSIKERON,CSIKERON" "0,1" newline bitfld.long 0x0 4. "CSION,CSION" "0,1" bitfld.long 0x0 1. "HSIKERON,HSIKERON" "0,1" newline bitfld.long 0x0 0. "HSION,HSION" "0,1" line.long 0x4 "RCC_OCENCLRR,This register is used to control the oscillators.Writing to this register has no effect. writing will clear the corresponding bits. Reading will give the effective values of the enable bits.If TZEN = . this register can only be modified in.." bitfld.long 0x4 10. "HSEBYP,HSEBYP" "0,1" bitfld.long 0x4 9. "HSEKERON,HSEKERON" "0,1" newline bitfld.long 0x4 8. "HSEON,HSEON" "0,1" bitfld.long 0x4 7. "DIGBYP,DIGBYP" "0,1" newline bitfld.long 0x4 5. "CSIKERON,CSIKERON" "0,1" bitfld.long 0x4 4. "CSION,CSION" "0,1" newline bitfld.long 0x4 1. "HSIKERON,HSIKERON" "0,1" bitfld.long 0x4 0. "HSION,HSION" "0,1" group.long 0x18++0x1B line.long 0x0 "RCC_HSICFGR,This register is used to configure the HSI. If TZEN = . this register can only be modified in secure mode. Write access to this register is not allowed during the clock restore sequence. See Section: The clock restore sequence description for.." hexmask.long.word 0x0 16.--27. 1. "HSICAL,HSICAL" hexmask.long.byte 0x0 8.--14. 1. "HSITRIM,HSITRIM" newline bitfld.long 0x0 0.--1. "HSIDIV,HSIDIV" "0,1,2,3" line.long 0x4 "RCC_CSICFGR,This register is used to fine-tune the CSI frequency. If TZEN = MCKPROT = . this register can only be modified in secure mode. Write access to this register is not allowed during the clock restore sequence. See The clock restore sequence.." hexmask.long.byte 0x4 16.--23. 1. "CSICAL,CSICAL" hexmask.long.byte 0x4 8.--12. 1. "CSITRIM,CSITRIM" line.long 0x8 "RCC_MPCKSELR,This register is used to select the clock source for the MPU. If TZEN = . this register can only be modified in secure mode. Write access to this register is not allowed during the clock restore sequence. See Section: The clock restore.." rbitfld.long 0x8 31. "MPUSRCRDY,MPUSRCRDY" "0,1" bitfld.long 0x8 0.--1. "MPUSRC,MPUSRC" "0,1,2,3" line.long 0xC "RCC_ASSCKSELR,This register is used to select the clock source for the AXI sub-system. If TZEN = . this register can only be modified in secure mode. Write access to this register is not allowed during the clock restore sequence. See Section: The clock.." rbitfld.long 0xC 31. "AXISSRCRDY,AXISSRCRDY" "0,1" bitfld.long 0xC 0.--2. "AXISSRC,AXISSRC" "0,1,2,3,4,5,6,7" line.long 0x10 "RCC_RCK12SELR,This register is used to select the reference clock for PLL1 and PLL2. If TZEN = . this register can only be modified in secure mode. Write access to this register is not allowed during the clock restore sequence. See Section: The clock.." rbitfld.long 0x10 31. "PLL12SRCRDY,PLL12SRCRDY" "0,1" bitfld.long 0x10 0.--1. "PLL12SRC,PLL12SRC" "0,1,2,3" line.long 0x14 "RCC_MPCKDIVR,This register is used to control the MPU clock prescaler. Refer to Section: Sub-system clock generation for additional information. If TZEN = . this register can only be modified in secure mode." rbitfld.long 0x14 31. "MPUDIVRDY,MPUDIVRDY" "0,1" bitfld.long 0x14 0.--2. "MPUDIV,MPUDIV" "0,1,2,3,4,5,6,7" line.long 0x18 "RCC_AXIDIVR,This register is used to control the AXI Matrix clock prescaler. Refer to Section: Sub-system clock generation for additional information. If TZEN = . this register can only be modified in secure mode." rbitfld.long 0x18 31. "AXIDIVRDY,AXIDIVRDY" "0,1" bitfld.long 0x18 0.--2. "AXIDIV,AXIDIV" "0,1,2,3,4,5,6,7" group.long 0x3C++0xF line.long 0x0 "RCC_APB4DIVR,This register is used to control the APB4 clock divider. Refer to Section: Sub-system clock generation for additional information. If TZEN = . this register can only be modified in secure mode." rbitfld.long 0x0 31. "APB4DIVRDY,APB4DIVRDY" "0,1" bitfld.long 0x0 0.--2. "APB4DIV,APB4DIV" "0,1,2,3,4,5,6,7" line.long 0x4 "RCC_APB5DIVR,This register is used to control the APB5 clock divider. Refer to Section: Sub-system clock generation for additional information. If TZEN = . this register can only be modified in secure mode." rbitfld.long 0x4 31. "APB5DIVRDY,APB5DIVRDY" "0,1" bitfld.long 0x4 0.--2. "APB5DIV,APB5DIV" "0,1,2,3,4,5,6,7" line.long 0x8 "RCC_RTCDIVR,This register is used to divide the HSE clock for RTC. If TZEN = . this register can only be modified in secure mode." hexmask.long.byte 0x8 0.--5. 1. "RTCDIV,RTCDIV" line.long 0xC "RCC_MSSCKSELR,This register is used to select the clock source for the MCU sub-system. including the MCU itself. If TZEN = MCKPROT = . this register can only be modified in secure mode. Write access to this register is not allowed during the clock.." rbitfld.long 0xC 31. "MCUSSRCRDY,MCUSSRCRDY" "0,1" bitfld.long 0xC 0.--1. "MCUSSRC,MCUSSRC" "0,1,2,3" group.long 0x80++0x27 line.long 0x0 "RCC_PLL1CR,This register is used to control the PLL1. If TZEN = . this register can only be modified in secure mode. Write access to this register is not allowed during the clock restore sequence. See Section: The clock restore sequence description for.." bitfld.long 0x0 6. "DIVREN,DIVREN" "0,1" bitfld.long 0x0 5. "DIVQEN,DIVQEN" "0,1" newline bitfld.long 0x0 4. "DIVPEN,DIVPEN" "0,1" bitfld.long 0x0 2. "SSCG_CTRL,SSCG_CTRL" "0,1" newline rbitfld.long 0x0 1. "PLL1RDY,PLL1RDY" "0,1" bitfld.long 0x0 0. "PLLON,PLLON" "0,1" line.long 0x4 "RCC_PLL1CFGR1,This register is used to configure the PLL1. If TZEN = . this register can only be modified in secure mode. Write access to this register is not allowed during the clock restore sequence. See Section: The clock restore sequence description.." hexmask.long.byte 0x4 16.--21. 1. "DIVM1,DIVM1" hexmask.long.word 0x4 0.--8. 1. "DIVN,DIVN" line.long 0x8 "RCC_PLL1CFGR2,This register is used to configure the PLL1. If TZEN = . this register can only be modified in secure mode. Write access to this register is not allowed during the clock restore sequence. See Section: The clock restore sequence description.." hexmask.long.byte 0x8 16.--22. 1. "DIVR,DIVR" hexmask.long.byte 0x8 8.--14. 1. "DIVQ,DIVQ" newline hexmask.long.byte 0x8 0.--6. 1. "DIVP,DIVP" line.long 0xC "RCC_PLL1FRACR,This register is used to fine-tune the frequency of the PLL1 VCO. If TZEN = . this register can only be modified in secure mode. Write access to this register is not allowed during the clock restore sequence. See Section: The clock restore.." bitfld.long 0xC 16. "FRACLE,FRACLE" "0,1" hexmask.long.word 0xC 3.--15. 1. "FRACV,FRACV" line.long 0x10 "RCC_PLL1CSGR,This register is used to configure the PLL1.It is not recommended to change the content of this register when the PLL1 is enabled (PLLON = ). Refer to Section: Using the PLLs in spread spectrum mode for details. If TZEN = . this register can.." hexmask.long.word 0x10 16.--30. 1. "INC_STEP,INC_STEP" bitfld.long 0x10 15. "SSCG_MODE,SSCG_MODE" "0,1" newline bitfld.long 0x10 14. "RPDFN_DIS,RPDFN_DIS" "0,1" bitfld.long 0x10 13. "TPDFN_DIS,TPDFN_DIS" "0,1" newline hexmask.long.word 0x10 0.--12. 1. "MOD_PER,MOD_PER" line.long 0x14 "RCC_PLL2CR,This register is used to control the PLL2. If TZEN = . this register can only be modified in secure mode. Write access to this register is not allowed during the clock restore sequence. See Section: The clock restore sequence description for.." bitfld.long 0x14 6. "DIVREN,DIVREN" "0,1" bitfld.long 0x14 5. "DIVQEN,DIVQEN" "0,1" newline bitfld.long 0x14 4. "DIVPEN,DIVPEN" "0,1" bitfld.long 0x14 2. "SSCG_CTRL,SSCG_CTRL" "0,1" newline rbitfld.long 0x14 1. "PLL2RDY,PLL2RDY" "0,1" bitfld.long 0x14 0. "PLLON,PLLON" "0,1" line.long 0x18 "RCC_PLL2CFGR1,This register is used to configure the PLL2. If TZEN = . this register can only be modified in secure mode. Write access to this register is not allowed during the clock restore sequence. See Section: The clock restore sequence description.." hexmask.long.byte 0x18 16.--21. 1. "DIVM2,DIVM2" hexmask.long.word 0x18 0.--8. 1. "DIVN,DIVN" line.long 0x1C "RCC_PLL2CFGR2,This register is used to configure the PLL2. If TZEN = . this register can only be modified in secure mode. Write access to this register is not allowed during the clock restore sequence. See Section: The clock restore sequence description.." hexmask.long.byte 0x1C 16.--22. 1. "DIVR,DIVR" hexmask.long.byte 0x1C 8.--14. 1. "DIVQ,DIVQ" newline hexmask.long.byte 0x1C 0.--6. 1. "DIVP,DIVP" line.long 0x20 "RCC_PLL2FRACR,This register is used to fine-tune the frequency of the PLL2 VCO. If TZEN = . this register can only be modified in secure mode. Write access to this register is not allowed during the clock restore sequence. See Section: The clock restore.." bitfld.long 0x20 16. "FRACLE,FRACLE" "0,1" hexmask.long.word 0x20 3.--15. 1. "FRACV,FRACV" line.long 0x24 "RCC_PLL2CSGR,This register is used to configure the PLL2. It is not recommended to change the content of this register when the PLL2 is enabled (PLLON = ). Refer to Section: Using the PLLs in spread spectrum mode for details. If TZEN = . this register.." hexmask.long.word 0x24 16.--30. 1. "INC_STEP,INC_STEP" bitfld.long 0x24 15. "SSCG_MODE,SSCG_MODE" "0,1" newline bitfld.long 0x24 14. "RPDFN_DIS,RPDFN_DIS" "0,1" bitfld.long 0x24 13. "TPDFN_DIS,TPDFN_DIS" "0,1" newline hexmask.long.word 0x24 0.--12. 1. "MOD_PER,MOD_PER" group.long 0xC0++0x1B line.long 0x0 "RCC_I2C46CKSELR,This register is used to control the selection of the kernel clock for the I2C4 and I2C6. Note that changing the clock source on-the-fly is allowed. and will not generate any timing violation. however the user has to ensure that both the.." bitfld.long 0x0 0.--2. "I2C46SRC,I2C46SRC" "0,1,2,3,4,5,6,7" line.long 0x4 "RCC_SPI6CKSELR,This register is used to control the selection of the kernel clock for the SPI6. Note that changing the clock source on-the-fly is allowed. and will not generate any timing violation. however the user has to ensure that both the previous.." bitfld.long 0x4 0.--2. "SPI6SRC,SPI6SRC" "0,1,2,3,4,5,6,7" line.long 0x8 "RCC_UART1CKSELR,This register is used to control the selection of the kernel clock for the USART1. Note that changing the clock source on-the-fly is allowed. and will not generate any timing violation. however the user has to ensure that both the.." bitfld.long 0x8 0.--2. "UART1SRC,UART1SRC" "0,1,2,3,4,5,6,7" line.long 0xC "RCC_RNG1CKSELR,This register is used to control the selection of the kernel clock for the RNG1. Note that changing the clock source on-the-fly is allowed. and will not generate any timing violation. however the user has to ensure that both the previous.." bitfld.long 0xC 0.--1. "RNG1SRC,RNG1SRC" "0,1,2,3" line.long 0x10 "RCC_CPERCKSELR,This register is used to select an oscillator source as kernel clock for the per_ck clock. The per_ck clock is distributed to several peripherals. Refer to Section: Clock enabling delays." bitfld.long 0x10 0.--1. "CKPERSRC,CKPERSRC" "0,1,2,3" line.long 0x14 "RCC_STGENCKSELR,This register is used to select the peripheral clock for the STGEN block. Note that this clock is used to provide a time reference for the application. Refer to Section: Clock enabling delays. If TZEN = . this register can only be.." bitfld.long 0x14 0.--1. "STGENSRC,STGENSRC" "0,1,2,3" line.long 0x18 "RCC_DDRITFCR,This register is used to control the DDR interface. including the DDRC and DDRPHYC. If TZEN = . this register can only be modified in secure mode." hexmask.long.byte 0x18 28.--31. 1. "GSKP_DUR,GSKP_DUR" bitfld.long 0x18 25.--27. "DFILP_WIDTH,DFILP_WIDTH" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 24. "GSKPCTRL,GSKPCTRL" "0,1" bitfld.long 0x18 23. "GSKPMOD,GSKPMOD" "0,1" newline bitfld.long 0x18 20.--22. "DDRCKMOD,DDRCKMOD" "0,1,2,3,4,5,6,7" bitfld.long 0x18 19. "DPHYCTLRST,DPHYCTLRST" "0,1" newline bitfld.long 0x18 18. "DPHYRST,DPHYRST" "0,1" bitfld.long 0x18 17. "DPHYAPBRST,DPHYAPBRST" "0,1" newline bitfld.long 0x18 16. "DDRCORERST,DDRCORERST" "0,1" bitfld.long 0x18 15. "DDRCAXIRST,DDRCAXIRST" "0,1" newline bitfld.long 0x18 14. "DDRCAPBRST,DDRCAPBRST" "0,1" bitfld.long 0x18 11.--13. "KERDCG_DLY,KERDCG_DLY" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 10. "DDRPHYCAPBLPEN,DDRPHYCAPBLPEN" "0,1" bitfld.long 0x18 9. "DDRPHYCAPBEN,DDRPHYCAPBEN" "0,1" newline bitfld.long 0x18 8. "AXIDCGEN,AXIDCGEN" "0,1" bitfld.long 0x18 7. "DDRCAPBLPEN,DDRCAPBLPEN" "0,1" newline bitfld.long 0x18 6. "DDRCAPBEN,DDRCAPBEN" "0,1" bitfld.long 0x18 5. "DDRPHYCLPEN,DDRPHYCLPEN" "0,1" newline bitfld.long 0x18 4. "DDRPHYCEN,DDRPHYCEN" "0,1" bitfld.long 0x18 3. "DDRC2LPEN,DDRC2LPEN" "0,1" newline bitfld.long 0x18 2. "DDRC2EN,DDRC2EN" "0,1" bitfld.long 0x18 1. "DDRC1LPEN,DDRC1LPEN" "0,1" newline bitfld.long 0x18 0. "DDRC1EN,DDRC1EN" "0,1" group.long 0x100++0x13 line.long 0x0 "RCC_MP_BOOTCR,This register is used to control the HOLD boot function when the system exits from Standby. Refer to Section: MCU HOLD_BOOT after processor reset. This register is reset when a system reset occurs. but not when the circuit exits from.." bitfld.long 0x0 1. "MPU_BEN,MPU_BEN" "0,1" bitfld.long 0x0 0. "MCU_BEN,MCU_BEN" "0,1" line.long 0x4 "RCC_MP_SREQSETR,Writing has no effect. reading will return the values of the bits. Writing a sets the corresponding bit to . The MCU cannot access to this register. If TZEN = . this register can only be modified in secure mode." bitfld.long 0x4 1. "STPREQ_P1,STPREQ_P1" "0,1" bitfld.long 0x4 0. "STPREQ_P0,STPREQ_P0" "0,1" line.long 0x8 "RCC_MP_SREQCLRR,Writing has no effect. reading will return the effective values of the bits. Writing a sets the corresponding bit to . The MCU cannot access to this register. If TZEN = . this register can only be modified in secure mode." bitfld.long 0x8 1. "STPREQ_P1,STPREQ_P1" "0,1" bitfld.long 0x8 0. "STPREQ_P0,STPREQ_P0" "0,1" line.long 0xC "RCC_MP_GCR,The register contains global control bits. If TZEN = . this register can only be modified in secure mode." bitfld.long 0xC 0. "BOOT_MCU,BOOT_MCU" "0,1" line.long 0x10 "RCC_MP_APRSTCR,This register is used to control the behavior of the warm reset. If TZEN = . this register can only be modified in secure mode." hexmask.long.byte 0x10 8.--14. 1. "RSTTO,RSTTO" bitfld.long 0x10 0. "RDCTLEN,RDCTLEN" "0,1" rgroup.long 0x114++0x3 line.long 0x0 "RCC_MP_APRSTSR,This register provides a status of the RDCTL. If TZEN = . this register can only be modified in secure mode." hexmask.long.byte 0x0 8.--14. 1. "RSTTOV,RSTTOV" group.long 0x140++0x7 line.long 0x0 "RCC_BDCR,This register is used to control the LSE function. Wait states are inserted in case of successive write accesses to this register. The number of wait states may be up to 7 cycles of AHB4 clock.After a system reset. the register RCC_BDCR is.." bitfld.long 0x0 31. "VSWRST,VSWRST" "0,1" bitfld.long 0x0 20. "RTCCKEN,RTCCKEN" "0,1" newline rbitfld.long 0x0 16.--17. "RTCSRC,RTCSRC" "0,1,2,3" rbitfld.long 0x0 9. "LSECSSD,LSECSSD" "0,1" newline bitfld.long 0x0 8. "LSECSSON,LSECSSON" "0,1" bitfld.long 0x0 4.--5. "LSEDRV,LSEDRV" "0,1,2,3" newline rbitfld.long 0x0 3. "DIGBYP,DIGBYP" "0,1" rbitfld.long 0x0 2. "LSERDY,LSERDY" "0,1" newline bitfld.long 0x0 1. "LSEBYP,LSEBYP" "0,1" bitfld.long 0x0 0. "LSEON,LSEON" "0,1" line.long 0x4 "RCC_RDLSICR,This register is used to control the minimum NRST active duration and LSI function.0 to 7 wait states are inserted for word. half-word and byte accesses. Wait states are inserted in case of successive accesses to this register.This register.." hexmask.long.byte 0x4 27.--31. 1. "SPARE,SPARE" bitfld.long 0x4 24.--26. "EADLY,EADLY" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x4 16.--20. 1. "MRD,MRD" rbitfld.long 0x4 1. "LSIRDY,LSIRDY" "0,1" newline bitfld.long 0x4 0. "LSION,LSION" "0,1" group.long 0x180++0x27 line.long 0x0 "RCC_APB4RSTSETR,This register is used to activate the reset of the corresponding peripheral. Writing has no effect. reading will return the effective values of the corresponding bits. Writing a activates the reset of the corresponding peripheral." bitfld.long 0x0 16. "USBPHYRST,USBPHYRST" "0,1" bitfld.long 0x0 8. "DDRPERFMRST,DDRPERFMRST" "0,1" newline bitfld.long 0x0 4. "DSIRST,DSIRST" "0,1" bitfld.long 0x0 0. "LTDCRST,LTDCRST" "0,1" line.long 0x4 "RCC_APB4RSTCLRR,This register is used to release the reset of the corresponding peripheral. Writing has no effect. reading will return the effective values of the corresponding bits. Writing a releases the reset of the corresponding peripheral." bitfld.long 0x4 16. "USBPHYRST,USBPHYRST" "0,1" bitfld.long 0x4 8. "DDRPERFMRST,DDRPERFMRST" "0,1" newline bitfld.long 0x4 4. "DSIRST,DSIRST" "0,1" bitfld.long 0x4 0. "LTDCRST,LTDCRST" "0,1" line.long 0x8 "RCC_APB5RSTSETR,This register is used to activate the reset of the corresponding peripheral. Writing has no effect. reading will return the effective values of the corresponding bits. Writing a activates the reset of the corresponding peripheral. If.." bitfld.long 0x8 20. "STGENRST,STGENRST" "0,1" bitfld.long 0x8 4. "USART1RST,USART1RST" "0,1" newline bitfld.long 0x8 3. "I2C6RST,I2C6RST" "0,1" bitfld.long 0x8 2. "I2C4RST,I2C4RST" "0,1" newline bitfld.long 0x8 0. "SPI6RST,SPI6RST" "0,1" line.long 0xC "RCC_APB5RSTCLRR,This register is used to release the reset of the corresponding peripheral. Writing has no effect. reading will return the effective values of the corresponding bits. Writing a releases the reset of the corresponding peripheral. If TZEN.." bitfld.long 0xC 20. "STGENRST,STGENRST" "0,1" bitfld.long 0xC 4. "USART1RST,USART1RST" "0,1" newline bitfld.long 0xC 3. "I2C6RST,I2C6RST" "0,1" bitfld.long 0xC 2. "I2C4RST,I2C4RST" "0,1" newline bitfld.long 0xC 0. "SPI6RST,SPI6RST" "0,1" line.long 0x10 "RCC_AHB5RSTSETR,This register is used to activate the reset of the corresponding peripheral. Writing has no effect. reading will return the effective values of the corresponding bits. Writing a activates the reset of the corresponding peripheral. If.." bitfld.long 0x10 16. "AXIMCRST,AXIMCRST" "0,1" bitfld.long 0x10 6. "RNG1RST,RNG1RST" "0,1" newline bitfld.long 0x10 5. "HASH1RST,HASH1RST" "0,1" bitfld.long 0x10 4. "CRYP1RST,CRYP1RST" "0,1" newline bitfld.long 0x10 0. "GPIOZRST,GPIOZRST" "0,1" line.long 0x14 "RCC_AHB5RSTCLRR,This register is used to release the reset of the corresponding peripheral. Writing has no effect. reading will return the effective values of the corresponding bits. Writing a releases the reset of the corresponding peripheral. If TZEN.." bitfld.long 0x14 16. "AXIMCRST,AXIMCRST" "0,1" bitfld.long 0x14 6. "RNG1RST,RNG1RST" "0,1" newline bitfld.long 0x14 5. "HASH1RST,HASH1RST" "0,1" bitfld.long 0x14 4. "CRYP1RST,CRYP1RST" "0,1" newline bitfld.long 0x14 0. "GPIOZRST,GPIOZRST" "0,1" line.long 0x18 "RCC_AHB6RSTSETR,This register is used to activate the reset of the corresponding peripheral. Writing has no effect. reading will return the effective values of the corresponding bits. Writing a activates the reset of the corresponding peripheral." bitfld.long 0x18 24. "USBHRST,USBHRST" "0,1" bitfld.long 0x18 20. "CRC1RST,CRC1RST" "0,1" newline bitfld.long 0x18 17. "SDMMC2RST,SDMMC2RST" "0,1" bitfld.long 0x18 16. "SDMMC1RST,SDMMC1RST" "0,1" newline bitfld.long 0x18 14. "QSPIRST,QSPIRST" "0,1" bitfld.long 0x18 12. "FMCRST,FMCRST" "0,1" newline bitfld.long 0x18 10. "ETHMACRST,ETHMACRST" "0,1" bitfld.long 0x18 5. "GPURST,GPURST" "0,1" line.long 0x1C "RCC_AHB6RSTCLRR,This register is used to release the reset of the corresponding peripheral. Writing has no effect. reading will return the effective values of the corresponding bits. Writing a releases the reset of the corresponding peripheral." bitfld.long 0x1C 24. "USBHRST,USBHRST" "0,1" bitfld.long 0x1C 20. "CRC1RST,CRC1RST" "0,1" newline bitfld.long 0x1C 17. "SDMMC2RST,SDMMC2RST" "0,1" bitfld.long 0x1C 16. "SDMMC1RST,SDMMC1RST" "0,1" newline bitfld.long 0x1C 14. "QSPIRST,QSPIRST" "0,1" bitfld.long 0x1C 12. "FMCRST,FMCRST" "0,1" newline bitfld.long 0x1C 10. "ETHMACRST,ETHMACRST" "0,1" line.long 0x20 "RCC_TZAHB6RSTSETR,This register is used to activate the reset of the corresponding peripheral. Writing has no effect. reading will return the effective values of the corresponding bits. Writing a activates the reset of the corresponding peripheral. If.." bitfld.long 0x20 0. "MDMARST,MDMARST" "0,1" line.long 0x24 "RCC_TZAHB6RSTCLRR,This register is used to release the reset of the corresponding peripheral. Writing has no effect. reading will return the effective values of the corresponding bits. Writing a releases the reset of the corresponding peripheral. If.." bitfld.long 0x24 0. "MDMARST,MDMARST" "0,1" group.long 0x200++0x27 line.long 0x0 "RCC_MP_APB4ENSETR,This register is used to set the peripheral clock enable bit of the corresponding peripheral to . It shall be used to allocate a peripheral to the MPU. Writing has no effect. reading will return the effective values of the.." bitfld.long 0x0 20. "STGENROEN,STGENROEN" "0,1" bitfld.long 0x0 16. "USBPHYEN,USBPHYEN" "0,1" newline bitfld.long 0x0 15. "IWDG2APBEN,IWDG2APBEN" "0,1" bitfld.long 0x0 8. "DDRPERFMEN,DDRPERFMEN" "0,1" newline bitfld.long 0x0 4. "DSIEN,DSIEN" "0,1" bitfld.long 0x0 0. "LTDCEN,LTDCEN" "0,1" line.long 0x4 "RCC_MP_APB4ENCLRR,This register is used to clear the peripheral clock enable bit of the corresponding peripheral. It shall be used to deallocate a peripheral from MPU. Writing has no effect. reading will return the effective values of the corresponding.." bitfld.long 0x4 20. "STGENROEN,STGENROEN" "0,1" bitfld.long 0x4 16. "USBPHYEN,USBPHYEN" "0,1" newline bitfld.long 0x4 15. "IWDG2APBEN,IWDG2APBEN" "0,1" bitfld.long 0x4 8. "DDRPERFMEN,DDRPERFMEN" "0,1" newline bitfld.long 0x4 4. "DSIEN,DSIEN" "0,1" bitfld.long 0x4 0. "LTDCEN,LTDCEN" "0,1" line.long 0x8 "RCC_MP_APB5ENSETR,This register is used to set the peripheral clock enable bit of the corresponding peripheral to . It shall be used to allocate a peripheral to the MPU. Writing has no effect. reading will return the effective values of the.." bitfld.long 0x8 20. "STGENEN,STGENEN" "0,1" bitfld.long 0x8 16. "BSECEN,BSECEN" "0,1" newline bitfld.long 0x8 15. "IWDG1APBEN,IWDG1APBEN" "0,1" bitfld.long 0x8 13. "TZPCEN,TZPCEN" "0,1" newline bitfld.long 0x8 12. "TZC2EN,TZC2EN" "0,1" bitfld.long 0x8 11. "TZC1EN,TZC1EN" "0,1" newline bitfld.long 0x8 8. "RTCAPBEN,RTCAPBEN" "0,1" bitfld.long 0x8 4. "USART1EN,USART1EN" "0,1" newline bitfld.long 0x8 3. "I2C6EN,I2C6EN" "0,1" bitfld.long 0x8 2. "I2C4EN,I2C4EN" "0,1" newline bitfld.long 0x8 0. "SPI6EN,SPI6EN" "0,1" line.long 0xC "RCC_MP_APB5ENCLRR,This register is used to clear the peripheral clock enable bit of the corresponding peripheral. It shall be used to deallocate a peripheral from MPU. Writing has no effect. reading will return the effective values of the corresponding.." bitfld.long 0xC 20. "STGENEN,STGENEN" "0,1" bitfld.long 0xC 16. "BSECEN,BSECEN" "0,1" newline bitfld.long 0xC 15. "IWDG1APBEN,IWDG1APBEN" "0,1" bitfld.long 0xC 13. "TZPCEN,TZPCEN" "0,1" newline bitfld.long 0xC 12. "TZC2EN,TZC2EN" "0,1" bitfld.long 0xC 11. "TZC1EN,TZC1EN" "0,1" newline bitfld.long 0xC 8. "RTCAPBEN,RTCAPBEN" "0,1" bitfld.long 0xC 4. "USART1EN,USART1EN" "0,1" newline bitfld.long 0xC 3. "I2C6EN,I2C6EN" "0,1" bitfld.long 0xC 2. "I2C4EN,I2C4EN" "0,1" newline bitfld.long 0xC 0. "SPI6EN,SPI6EN" "0,1" line.long 0x10 "RCC_MP_AHB5ENSETR,This register is used to set the peripheral clock enable bit of the corresponding peripheral to . It shall be used to allocate a peripheral to the MPU. Writing has no effect. reading will return the effective values of the.." bitfld.long 0x10 16. "AXIMCEN,AXIMCEN" "0,1" bitfld.long 0x10 8. "BKPSRAMEN,BKPSRAMEN" "0,1" newline bitfld.long 0x10 6. "RNG1EN,RNG1EN" "0,1" bitfld.long 0x10 5. "HASH1EN,HASH1EN" "0,1" newline bitfld.long 0x10 4. "CRYP1EN,CRYP1EN" "0,1" bitfld.long 0x10 0. "GPIOZEN,GPIOZEN" "0,1" line.long 0x14 "RCC_MP_AHB5ENCLRR,This register is used to clear the peripheral clock enable bit of the corresponding peripheral. It shall be used to deallocate a peripheral from MPU. Writing has no effect. reading will return the effective values of the corresponding.." bitfld.long 0x14 16. "AXIMCEN,AXIMCEN" "0,1" bitfld.long 0x14 8. "BKPSRAMEN,BKPSRAMEN" "0,1" newline bitfld.long 0x14 6. "RNG1EN,RNG1EN" "0,1" bitfld.long 0x14 5. "HASH1EN,HASH1EN" "0,1" newline bitfld.long 0x14 4. "CRYP1EN,CRYP1EN" "0,1" bitfld.long 0x14 0. "GPIOZEN,GPIOZEN" "0,1" line.long 0x18 "RCC_MP_AHB6ENSETR,This register is used to set the peripheral clock enable bit of the corresponding peripheral to . It shall be used to allocate a peripheral to the MPU. Writing has no effect. reading will return the effective values of the.." bitfld.long 0x18 24. "USBHEN,USBHEN" "0,1" bitfld.long 0x18 20. "CRC1EN,CRC1EN" "0,1" newline bitfld.long 0x18 17. "SDMMC2EN,SDMMC2EN" "0,1" bitfld.long 0x18 16. "SDMMC1EN,SDMMC1EN" "0,1" newline bitfld.long 0x18 14. "QSPIEN,QSPIEN" "0,1" bitfld.long 0x18 12. "FMCEN,FMCEN" "0,1" newline bitfld.long 0x18 10. "ETHMACEN,ETHMACEN" "0,1" bitfld.long 0x18 9. "ETHRXEN,ETHRXEN" "0,1" newline bitfld.long 0x18 8. "ETHTXEN,ETHTXEN" "0,1" bitfld.long 0x18 7. "ETHCKEN,ETHCKEN" "0,1" newline bitfld.long 0x18 5. "GPUEN,GPUEN" "0,1" bitfld.long 0x18 0. "MDMAEN,MDMAEN" "0,1" line.long 0x1C "RCC_MP_AHB6ENCLRR,This register is used to clear the peripheral clock enable bit of the corresponding peripheral. It shall be used to deallocate a peripheral from MPU. Writing has no effect. reading will return the effective values of the corresponding.." bitfld.long 0x1C 24. "USBHEN,USBHEN" "0,1" bitfld.long 0x1C 20. "CRC1EN,CRC1EN" "0,1" newline bitfld.long 0x1C 17. "SDMMC2EN,SDMMC2EN" "0,1" bitfld.long 0x1C 16. "SDMMC1EN,SDMMC1EN" "0,1" newline bitfld.long 0x1C 14. "QSPIEN,QSPIEN" "0,1" bitfld.long 0x1C 12. "FMCEN,FMCEN" "0,1" newline bitfld.long 0x1C 10. "ETHMACEN,ETHMACEN" "0,1" bitfld.long 0x1C 9. "ETHRXEN,ETHRXEN" "0,1" newline bitfld.long 0x1C 8. "ETHTXEN,ETHTXEN" "0,1" bitfld.long 0x1C 7. "ETHCKEN,ETHCKEN" "0,1" newline bitfld.long 0x1C 5. "GPUEN,GPUEN" "0,1" bitfld.long 0x1C 0. "MDMAEN,MDMAEN" "0,1" line.long 0x20 "RCC_MP_TZAHB6ENSETR,This register is used to set the peripheral clock enable bit of the corresponding peripheral to . It shall be used to allocate a peripheral to the MPU. Writing has no effect. reading will return the effective values of the.." bitfld.long 0x20 0. "MDMAEN,MDMAEN" "0,1" line.long 0x24 "RCC_MP_TZAHB6ENCLRR,This register is used to clear the peripheral clock enable bit of the corresponding peripheral. It shall be used to deallocate a peripheral from MPU. Writing has no effect. reading will return the effective values of the.." bitfld.long 0x24 0. "MDMAEN,MDMAEN" "0,1" group.long 0x280++0x1F line.long 0x0 "RCC_MC_APB4ENSETR,This register is used to set the peripheral clock enable bit" bitfld.long 0x0 20. "STGENROEN,STGENROEN" "0,1" bitfld.long 0x0 16. "USBPHYEN,USBPHYEN" "0,1" newline bitfld.long 0x0 8. "DDRPERFMEN,DDRPERFMEN" "0,1" bitfld.long 0x0 4. "DSIEN,DSIEN" "0,1" newline bitfld.long 0x0 0. "LTDCEN,LTDCEN" "0,1" line.long 0x4 "RCC_MC_APB4ENCLRR,This register is used to clear the peripheral clock enable bit" bitfld.long 0x4 20. "STGENROEN,STGENROEN" "0,1" bitfld.long 0x4 16. "USBPHYEN,USBPHYEN" "0,1" newline bitfld.long 0x4 8. "DDRPERFMEN,DDRPERFMEN" "0,1" bitfld.long 0x4 4. "DSIEN,DSIEN" "0,1" newline bitfld.long 0x4 0. "LTDCEN,LTDCEN" "0,1" line.long 0x8 "RCC_MC_APB5ENSETR,This register is used to set the peripheral clock enable bit" bitfld.long 0x8 20. "STGENEN,STGENEN" "0,1" bitfld.long 0x8 16. "BSECEN,BSECEN" "0,1" newline bitfld.long 0x8 13. "TZPCEN,TZPCEN" "0,1" bitfld.long 0x8 12. "TZC2EN,TZC2EN" "0,1" newline bitfld.long 0x8 11. "TZC1EN,TZC1EN" "0,1" bitfld.long 0x8 8. "RTCAPBEN,RTCAPBEN" "0,1" newline bitfld.long 0x8 4. "USART1EN,USART1EN" "0,1" bitfld.long 0x8 3. "I2C6EN,I2C6EN" "0,1" newline bitfld.long 0x8 2. "I2C4EN,I2C4EN" "0,1" bitfld.long 0x8 0. "SPI6EN,SPI6EN" "0,1" line.long 0xC "RCC_MC_APB5ENCLRR,This register is used to clear the peripheral clock enable bit" bitfld.long 0xC 20. "STGENEN,STGENEN" "0,1" bitfld.long 0xC 16. "BSECEN,BSECEN" "0,1" newline bitfld.long 0xC 13. "TZPCEN,TZPCEN" "0,1" bitfld.long 0xC 12. "TZC2EN,TZC2EN" "0,1" newline bitfld.long 0xC 11. "TZC1EN,TZC1EN" "0,1" bitfld.long 0xC 8. "RTCAPBEN,RTCAPBEN" "0,1" newline bitfld.long 0xC 4. "USART1EN,USART1EN" "0,1" bitfld.long 0xC 3. "I2C6EN,I2C6EN" "0,1" newline bitfld.long 0xC 2. "I2C4EN,I2C4EN" "0,1" bitfld.long 0xC 0. "SPI6EN,SPI6EN" "0,1" line.long 0x10 "RCC_MC_AHB5ENSETR,This register is used to set the peripheral clock enable bit If TZEN = . this register can only be modified in secure mode." bitfld.long 0x10 8. "BKPSRAMEN,BKPSRAMEN" "0,1" bitfld.long 0x10 6. "RNG1EN,RNG1EN" "0,1" newline bitfld.long 0x10 5. "HASH1EN,HASH1EN" "0,1" bitfld.long 0x10 4. "CRYP1EN,CRYP1EN" "0,1" newline bitfld.long 0x10 0. "GPIOZEN,GPIOZEN" "0,1" line.long 0x14 "RCC_MC_AHB5ENCLRR,This register is used to clear the peripheral clock enable bit If TZEN = . this register can only be modified in secure mode." bitfld.long 0x14 8. "BKPSRAMEN,BKPSRAMEN" "0,1" bitfld.long 0x14 6. "RNG1EN,RNG1EN" "0,1" newline bitfld.long 0x14 5. "HASH1EN,HASH1EN" "0,1" bitfld.long 0x14 4. "CRYP1EN,CRYP1EN" "0,1" newline bitfld.long 0x14 0. "GPIOZEN,GPIOZEN" "0,1" line.long 0x18 "RCC_MC_AHB6ENSETR,This register is used to set the peripheral clock enable bit" bitfld.long 0x18 24. "USBHEN,USBHEN" "0,1" bitfld.long 0x18 20. "CRC1EN,CRC1EN" "0,1" newline bitfld.long 0x18 17. "SDMMC2EN,SDMMC2EN" "0,1" bitfld.long 0x18 16. "SDMMC1EN,SDMMC1EN" "0,1" newline bitfld.long 0x18 14. "QSPIEN,QSPIEN" "0,1" bitfld.long 0x18 12. "FMCEN,FMCEN" "0,1" newline bitfld.long 0x18 10. "ETHMACEN,ETHMACEN" "0,1" bitfld.long 0x18 9. "ETHRXEN,ETHRXEN" "0,1" newline bitfld.long 0x18 8. "ETHTXEN,ETHTXEN" "0,1" bitfld.long 0x18 7. "ETHCKEN,ETHCKEN" "0,1" newline bitfld.long 0x18 5. "GPUEN,GPUEN" "0,1" bitfld.long 0x18 0. "MDMAEN,MDMAEN" "0,1" line.long 0x1C "RCC_MC_AHB6ENCLRR,This register is used to clear the peripheral clock enable bit" bitfld.long 0x1C 24. "USBHEN,USBHEN" "0,1" bitfld.long 0x1C 20. "CRC1EN,CRC1EN" "0,1" newline bitfld.long 0x1C 17. "SDMMC2EN,SDMMC2EN" "0,1" bitfld.long 0x1C 16. "SDMMC1EN,SDMMC1EN" "0,1" newline bitfld.long 0x1C 14. "QSPIEN,QSPIEN" "0,1" bitfld.long 0x1C 12. "FMCEN,FMCEN" "0,1" newline bitfld.long 0x1C 10. "ETHMACEN,ETHMACEN" "0,1" bitfld.long 0x1C 9. "ETHRXEN,ETHRXEN" "0,1" newline bitfld.long 0x1C 8. "ETHTXEN,ETHTXEN" "0,1" bitfld.long 0x1C 7. "ETHCKEN,ETHCKEN" "0,1" newline bitfld.long 0x1C 5. "GPUEN,GPUEN" "0,1" bitfld.long 0x1C 0. "MDMAEN,MDMAEN" "0,1" group.long 0x300++0x27 line.long 0x0 "RCC_MP_APB4LPENSETR,This register is used by the MCU in order to clear the PERxLPEN bits" bitfld.long 0x0 21. "STGENROSTPEN,STGENROSTPEN" "0,1" bitfld.long 0x0 20. "STGENROLPEN,STGENROLPEN" "0,1" newline bitfld.long 0x0 16. "USBPHYLPEN,USBPHYLPEN" "0,1" bitfld.long 0x0 15. "IWDG2APBLPEN,IWDG2APBLPEN" "0,1" newline bitfld.long 0x0 8. "DDRPERFMLPEN,DDRPERFMLPEN" "0,1" bitfld.long 0x0 4. "DSILPEN,DSILPEN" "0,1" newline bitfld.long 0x0 0. "LTDCLPEN,LTDCLPEN" "0,1" line.long 0x4 "RCC_MP_APB4LPENCLRR,This register is used by the MCU" bitfld.long 0x4 21. "STGENROSTPEN,STGENROSTPEN" "0,1" bitfld.long 0x4 20. "STGENROLPEN,STGENROLPEN" "0,1" newline bitfld.long 0x4 16. "USBPHYLPEN,USBPHYLPEN" "0,1" bitfld.long 0x4 15. "IWDG2APBLPEN,IWDG2APBLPEN" "0,1" newline bitfld.long 0x4 8. "DDRPERFMLPEN,DDRPERFMLPEN" "0,1" bitfld.long 0x4 4. "DSILPEN,DSILPEN" "0,1" newline bitfld.long 0x4 0. "LTDCLPEN,LTDCLPEN" "0,1" line.long 0x8 "RCC_MP_APB5LPENSETR,This register is used by the MCU in order to clear the PERxLPEN bits If TZEN = . this register can only be modified in secure mode." bitfld.long 0x8 21. "STGENSTPEN,STGENSTPEN" "0,1" bitfld.long 0x8 20. "STGENLPEN,STGENLPEN" "0,1" newline bitfld.long 0x8 16. "BSECLPEN,BSECLPEN" "0,1" bitfld.long 0x8 15. "IWDG1APBLPEN,IWDG1APBLPEN" "0,1" newline bitfld.long 0x8 13. "TZPCLPEN,TZPCLPEN" "0,1" bitfld.long 0x8 12. "TZC2LPEN,TZC2LPEN" "0,1" newline bitfld.long 0x8 11. "TZC1LPEN,TZC1LPEN" "0,1" bitfld.long 0x8 8. "RTCAPBLPEN,RTCAPBLPEN" "0,1" newline bitfld.long 0x8 4. "USART1LPEN,USART1LPEN" "0,1" bitfld.long 0x8 3. "I2C6LPEN,I2C6LPEN" "0,1" newline bitfld.long 0x8 2. "I2C4LPEN,I2C4LPEN" "0,1" bitfld.long 0x8 0. "SPI6LPEN,SPI6LPEN" "0,1" line.long 0xC "RCC_MP_APB5LPENCLRR,This register is used by the Mpu." bitfld.long 0xC 21. "STGENSTPEN,STGENSTPEN" "0,1" bitfld.long 0xC 20. "STGENLPEN,STGENLPEN" "0,1" newline bitfld.long 0xC 16. "BSECLPEN,BSECLPEN" "0,1" bitfld.long 0xC 15. "IWDG1APBLPEN,IWDG1APBLPEN" "0,1" newline bitfld.long 0xC 13. "TZPCLPEN,TZPCLPEN" "0,1" bitfld.long 0xC 12. "TZC2LPEN,TZC2LPEN" "0,1" newline bitfld.long 0xC 11. "TZC1LPEN,TZC1LPEN" "0,1" bitfld.long 0xC 8. "RTCAPBLPEN,RTCAPBLPEN" "0,1" newline bitfld.long 0xC 4. "USART1LPEN,USART1LPEN" "0,1" bitfld.long 0xC 3. "I2C6LPEN,I2C6LPEN" "0,1" newline bitfld.long 0xC 2. "I2C4LPEN,I2C4LPEN" "0,1" bitfld.long 0xC 0. "SPI6LPEN,SPI6LPEN" "0,1" line.long 0x10 "RCC_MP_AHB5LPENSETR,This register is used by the MCU in order to clear the PERxLPEN bits If TZEN = . this register can only be modified in secure mode." bitfld.long 0x10 8. "BKPSRAMLPEN,BKPSRAMLPEN" "0,1" bitfld.long 0x10 6. "RNG1LPEN,RNG1LPEN" "0,1" newline bitfld.long 0x10 5. "HASH1LPEN,HASH1LPEN" "0,1" bitfld.long 0x10 4. "CRYP1LPEN,CRYP1LPEN" "0,1" newline bitfld.long 0x10 0. "GPIOZLPEN,GPIOZLPEN" "0,1" line.long 0x14 "RCC_MP_AHB5LPENCLRR,This register is used by the MCU" bitfld.long 0x14 8. "BKPSRAMLPEN,BKPSRAMLPEN" "0,1" bitfld.long 0x14 6. "RNG1LPEN,RNG1LPEN" "0,1" newline bitfld.long 0x14 5. "HASH1LPEN,HASH1LPEN" "0,1" bitfld.long 0x14 4. "CRYP1LPEN,CRYP1LPEN" "0,1" newline bitfld.long 0x14 0. "GPIOZLPEN,GPIOZLPEN" "0,1" line.long 0x18 "RCC_MP_AHB6LPENSETR,This register is used by the MCU in order to clear the PERxLPEN bits" bitfld.long 0x18 24. "USBHLPEN,USBHLPEN" "0,1" bitfld.long 0x18 20. "CRC1LPEN,CRC1LPEN" "0,1" newline bitfld.long 0x18 17. "SDMMC2LPEN,SDMMC2LPEN" "0,1" bitfld.long 0x18 16. "SDMMC1LPEN,SDMMC1LPEN" "0,1" newline bitfld.long 0x18 14. "QSPILPEN,QSPILPEN" "0,1" bitfld.long 0x18 12. "FMCLPEN,FMCLPEN" "0,1" newline bitfld.long 0x18 11. "ETHSTPEN,ETHSTPEN" "0,1" bitfld.long 0x18 10. "ETHMACLPEN,ETHMACLPEN" "0,1" newline bitfld.long 0x18 9. "ETHRXLPEN,ETHRXLPEN" "0,1" bitfld.long 0x18 8. "ETHTXLPEN,ETHTXLPEN" "0,1" newline bitfld.long 0x18 7. "ETHCKLPEN,ETHCKLPEN" "0,1" bitfld.long 0x18 5. "GPULPEN,GPULPEN" "0,1" newline bitfld.long 0x18 0. "MDMALPEN,MDMALPEN" "0,1" line.long 0x1C "RCC_MP_AHB6LPENCLRR,This register is used by the MCU in order to clear the PERxLPEN bits" bitfld.long 0x1C 24. "USBHLPEN,USBHLPEN" "0,1" bitfld.long 0x1C 20. "CRC1LPEN,CRC1LPEN" "0,1" newline bitfld.long 0x1C 17. "SDMMC2LPEN,SDMMC2LPEN" "0,1" bitfld.long 0x1C 16. "SDMMC1LPEN,SDMMC1LPEN" "0,1" newline bitfld.long 0x1C 14. "QSPILPEN,QSPILPEN" "0,1" bitfld.long 0x1C 12. "FMCLPEN,FMCLPEN" "0,1" newline bitfld.long 0x1C 11. "ETHSTPEN,ETHSTPEN" "0,1" bitfld.long 0x1C 10. "ETHMACLPEN,ETHMACLPEN" "0,1" newline bitfld.long 0x1C 9. "ETHRXLPEN,ETHRXLPEN" "0,1" bitfld.long 0x1C 8. "ETHTXLPEN,ETHTXLPEN" "0,1" newline bitfld.long 0x1C 7. "ETHCKLPEN,ETHCKLPEN" "0,1" bitfld.long 0x1C 5. "GPULPEN,GPULPEN" "0,1" newline bitfld.long 0x1C 0. "MDMALPEN,MDMALPEN" "0,1" line.long 0x20 "RCC_MP_TZAHB6LPENSETR,This register is used by the MCU in order to clear the PERxLPEN bits If TZEN = . this register can only be modified in secure mode." bitfld.long 0x20 0. "MDMALPEN,MDMALPEN" "0,1" line.long 0x24 "RCC_MP_TZAHB6LPENCLRR,This register is used by the MCU in order to clear the PERxLPEN bits If TZEN = . this register can only be modified in secure mode." bitfld.long 0x24 0. "MDMALPEN,MDMALPEN" "0,1" group.long 0x380++0x1F line.long 0x0 "RCC_MC_APB4LPENSETR,This register is used by the MCU in order to set the PERxLPEN bit." bitfld.long 0x0 21. "STGENROSTPEN,STGENROSTPEN" "0,1" bitfld.long 0x0 20. "STGENROLPEN,STGENROLPEN" "0,1" newline bitfld.long 0x0 16. "USBPHYLPEN,USBPHYLPEN" "0,1" bitfld.long 0x0 8. "DDRPERFMLPEN,DDRPERFMLPEN" "0,1" newline bitfld.long 0x0 4. "DSILPEN,DSILPEN" "0,1" bitfld.long 0x0 0. "LTDCLPEN,LTDCLPEN" "0,1" line.long 0x4 "RCC_MC_APB4LPENCLRR,This register is used by the MCU in order to clear the PERxLPEN bit" bitfld.long 0x4 21. "STGENROSTPEN,STGENROSTPEN" "0,1" bitfld.long 0x4 20. "STGENROLPEN,STGENROLPEN" "0,1" newline bitfld.long 0x4 16. "USBPHYLPEN,USBPHYLPEN" "0,1" bitfld.long 0x4 8. "DDRPERFMLPEN,DDRPERFMLPEN" "0,1" newline bitfld.long 0x4 4. "DSILPEN,DSILPEN" "0,1" bitfld.long 0x4 0. "LTDCLPEN,LTDCLPEN" "0,1" line.long 0x8 "RCC_MC_APB5LPENSETR,This register is used by the MCU in order to set the PERxLPEN bit." bitfld.long 0x8 21. "STGENSTPEN,STGENSTPEN" "0,1" bitfld.long 0x8 20. "STGENLPEN,STGENLPEN" "0,1" newline bitfld.long 0x8 16. "BSECLPEN,BSECLPEN" "0,1" bitfld.long 0x8 13. "TZPCLPEN,TZPCLPEN" "0,1" newline bitfld.long 0x8 12. "TZC2LPEN,TZC2LPEN" "0,1" bitfld.long 0x8 11. "TZC1LPEN,TZC1LPEN" "0,1" newline bitfld.long 0x8 8. "RTCAPBLPEN,RTCAPBLPEN" "0,1" bitfld.long 0x8 4. "USART1LPEN,USART1LPEN" "0,1" newline bitfld.long 0x8 3. "I2C6LPEN,I2C6LPEN" "0,1" bitfld.long 0x8 2. "I2C4LPEN,I2C4LPEN" "0,1" newline bitfld.long 0x8 0. "SPI6LPEN,SPI6LPEN" "0,1" line.long 0xC "RCC_MC_APB5LPENCLRR,This register is used by the MCU in order to clear the PERxLPEN bit" bitfld.long 0xC 21. "STGENSTPEN,STGENSTPEN" "0,1" bitfld.long 0xC 20. "STGENLPEN,STGENLPEN" "0,1" newline bitfld.long 0xC 16. "BSECLPEN,BSECLPEN" "0,1" bitfld.long 0xC 13. "TZPCLPEN,TZPCLPEN" "0,1" newline bitfld.long 0xC 12. "TZC2LPEN,TZC2LPEN" "0,1" bitfld.long 0xC 11. "TZC1LPEN,TZC1LPEN" "0,1" newline bitfld.long 0xC 8. "RTCAPBLPEN,RTCAPBLPEN" "0,1" bitfld.long 0xC 4. "USART1LPEN,USART1LPEN" "0,1" newline bitfld.long 0xC 3. "I2C6LPEN,I2C6LPEN" "0,1" bitfld.long 0xC 2. "I2C4LPEN,I2C4LPEN" "0,1" newline bitfld.long 0xC 0. "SPI6LPEN,SPI6LPEN" "0,1" line.long 0x10 "RCC_MC_AHB5LPENSETR,This register is used by the MCU in order to set the PERxLPEN bit. If TZEN = . this register can only be modified in secure mode." bitfld.long 0x10 8. "BKPSRAMLPEN,BKPSRAMLPEN" "0,1" bitfld.long 0x10 6. "RNG1LPEN,RNG1LPEN" "0,1" newline bitfld.long 0x10 5. "HASH1LPEN,HASH1LPEN" "0,1" bitfld.long 0x10 4. "CRYP1LPEN,CRYP1LPEN" "0,1" newline bitfld.long 0x10 0. "GPIOZLPEN,GPIOZLPEN" "0,1" line.long 0x14 "RCC_MC_AHB5LPENCLRR,This register is used by the MCU in order to clear the PERxLPEN bit If TZEN = . this register can only be modified in secure mode." bitfld.long 0x14 8. "BKPSRAMLPEN,BKPSRAMLPEN" "0,1" bitfld.long 0x14 6. "RNG1LPEN,RNG1LPEN" "0,1" newline bitfld.long 0x14 5. "HASH1LPEN,HASH1LPEN" "0,1" bitfld.long 0x14 4. "CRYP1LPEN,CRYP1LPEN" "0,1" newline bitfld.long 0x14 0. "GPIOZLPEN,GPIOZLPEN" "0,1" line.long 0x18 "RCC_MC_AHB6LPENSETR,This register is used by the MCU in order to set the PERxLPEN bit." bitfld.long 0x18 24. "USBHLPEN,USBHLPEN" "0,1" bitfld.long 0x18 20. "CRC1LPEN,CRC1LPEN" "0,1" newline bitfld.long 0x18 17. "SDMMC2LPEN,SDMMC2LPEN" "0,1" bitfld.long 0x18 16. "SDMMC1LPEN,SDMMC1LPEN" "0,1" newline bitfld.long 0x18 14. "QSPILPEN,QSPILPEN" "0,1" bitfld.long 0x18 12. "FMCLPEN,FMCLPEN" "0,1" newline bitfld.long 0x18 11. "ETHSTPEN,ETHSTPEN" "0,1" bitfld.long 0x18 10. "ETHMACLPEN,ETHMACLPEN" "0,1" newline bitfld.long 0x18 9. "ETHRXLPEN,ETHRXLPEN" "0,1" bitfld.long 0x18 8. "ETHTXLPEN,ETHTXLPEN" "0,1" newline bitfld.long 0x18 7. "ETHCKLPEN,ETHCKLPEN" "0,1" bitfld.long 0x18 5. "GPULPEN,GPULPEN" "0,1" newline bitfld.long 0x18 0. "MDMALPEN,MDMALPEN" "0,1" line.long 0x1C "RCC_MC_AHB6LPENCLRR,This register is used by the MCU in order to clear the PERxLPEN bit" bitfld.long 0x1C 24. "USBHLPEN,USBHLPEN" "0,1" bitfld.long 0x1C 20. "CRC1LPEN,CRC1LPEN" "0,1" newline bitfld.long 0x1C 17. "SDMMC2LPEN,SDMMC2LPEN" "0,1" bitfld.long 0x1C 16. "SDMMC1LPEN,SDMMC1LPEN" "0,1" newline bitfld.long 0x1C 14. "QSPILPEN,QSPILPEN" "0,1" bitfld.long 0x1C 12. "FMCLPEN,FMCLPEN" "0,1" newline bitfld.long 0x1C 11. "ETHSTPEN,ETHSTPEN" "0,1" bitfld.long 0x1C 10. "ETHMACLPEN,ETHMACLPEN" "0,1" newline bitfld.long 0x1C 9. "ETHRXLPEN,ETHRXLPEN" "0,1" bitfld.long 0x1C 8. "ETHTXLPEN,ETHTXLPEN" "0,1" newline bitfld.long 0x1C 7. "ETHCKLPEN,ETHCKLPEN" "0,1" bitfld.long 0x1C 5. "GPULPEN,GPULPEN" "0,1" newline bitfld.long 0x1C 0. "MDMALPEN,MDMALPEN" "0,1" group.long 0x400++0x23 line.long 0x0 "RCC_BR_RSTSCLRR,This register is used by the BOOTROM to check the reset source. Writing has no effect. reading will return the effective values of the corresponding bits. Writing a clears the corresponding bit to . In order to identify the reset.." bitfld.long 0x0 14. "MPUP1RSTF,MPUP1RSTF" "0,1" bitfld.long 0x0 13. "MPUP0RSTF,MPUP0RSTF" "0,1" newline bitfld.long 0x0 9. "IWDG2RSTF,IWDG2RSTF" "0,1" bitfld.long 0x0 8. "IWDG1RSTF,IWDG1RSTF" "0,1" newline bitfld.long 0x0 7. "MCSYSRSTF,MCSYSRSTF" "0,1" bitfld.long 0x0 6. "MPSYSRSTF,MPSYSRSTF" "0,1" newline bitfld.long 0x0 4. "VCORERSTF,VCORERSTF" "0,1" bitfld.long 0x0 3. "HCSSRSTF,HCSSRSTF" "0,1" newline bitfld.long 0x0 2. "PADRSTF,PADRSTF" "0,1" bitfld.long 0x0 1. "BORRSTF,BORRSTF" "0,1" newline bitfld.long 0x0 0. "PORRSTF,PORRSTF" "0,1" line.long 0x4 "RCC_MP_GRSTCSETR,This register is used by the MPU in order to generate either a MCU reset or a system reset or a reset of one of the two MPU processors. Writing has no effect. reading returns the effective values of the corresponding bits. Writing a.." bitfld.long 0x4 5. "MPUP1RST,MPUP1RST" "0,1" bitfld.long 0x4 4. "MPUP0RST,MPUP0RST" "0,1" newline bitfld.long 0x4 1. "MCURST,MCURST" "0,1" bitfld.long 0x4 0. "MPSYSRST,MPSYSRST" "0,1" line.long 0x8 "RCC_MP_RSTSCLRR,This register is used by the MPU to check the reset source. This register is updated by the BOOTROM code. after a power-on reset (por_rst). a system reset (nreset). or an exit from Standby or CStandby.Writing has no effect. reading will.." bitfld.long 0x8 15. "SPARE,SPARE" "0,1" bitfld.long 0x8 14. "MPUP1RSTF,MPUP1RSTF" "0,1" newline bitfld.long 0x8 13. "MPUP0RSTF,MPUP0RSTF" "0,1" bitfld.long 0x8 12. "CSTDBYRSTF,CSTDBYRSTF" "0,1" newline bitfld.long 0x8 11. "STDBYRSTF,STDBYRSTF" "0,1" bitfld.long 0x8 9. "IWDG2RSTF,IWDG2RSTF" "0,1" newline bitfld.long 0x8 8. "IWDG1RSTF,IWDG1RSTF" "0,1" bitfld.long 0x8 7. "MCSYSRSTF,MCSYSRSTF" "0,1" newline bitfld.long 0x8 6. "MPSYSRSTF,MPSYSRSTF" "0,1" bitfld.long 0x8 4. "VCORERSTF,VCORERSTF" "0,1" newline bitfld.long 0x8 3. "HCSSRSTF,HCSSRSTF" "0,1" bitfld.long 0x8 2. "PADRSTF,PADRSTF" "0,1" newline bitfld.long 0x8 1. "BORRSTF,BORRSTF" "0,1" bitfld.long 0x8 0. "PORRSTF,PORRSTF" "0,1" line.long 0xC "RCC_MP_IWDGFZSETR,This register is used by the BOOTROM in order to freeze the IWDGs clocks. After a system reset or Standby reset (nreset). or a CStandby reset (cstby_rst) the MPU is allowed to write it once.Writing has no effect. reading will return.." bitfld.long 0xC 1. "FZ_IWDG2,FZ_IWDG2" "0,1" bitfld.long 0xC 0. "FZ_IWDG1,FZ_IWDG1" "0,1" line.long 0x10 "RCC_MP_IWDGFZCLRR,This register is used by the BOOTROM in order to unfreeze the IWDGs clocks. Writing has no effect. reading will return the effective values of the corresponding bits. Writing a clears the corresponding bit to . If TZEN = . this.." bitfld.long 0x10 1. "FZ_IWDG2,FZ_IWDG2" "0,1" bitfld.long 0x10 0. "FZ_IWDG1,FZ_IWDG1" "0,1" line.long 0x14 "RCC_MP_CIER,This register shall be used by the MPU to control the interrupt source enable. Refer to Section10.5: RCC interrupts for more details. If TZEN = . this register can only be modified in secure mode." bitfld.long 0x14 20. "WKUPIE,WKUPIE" "0,1" bitfld.long 0x14 16. "LSECSSIE,LSECSSIE" "0,1" newline bitfld.long 0x14 11. "PLL4DYIE,PLL4DYIE" "0,1" bitfld.long 0x14 10. "PLL3DYIE,PLL3DYIE" "0,1" newline bitfld.long 0x14 9. "PLL2DYIE,PLL2DYIE" "0,1" bitfld.long 0x14 8. "PLL1DYIE,PLL1DYIE" "0,1" newline bitfld.long 0x14 4. "CSIRDYIE,CSIRDYIE" "0,1" bitfld.long 0x14 3. "HSERDYIE,HSERDYIE" "0,1" newline bitfld.long 0x14 2. "HSIRDYIE,HSIRDYIE" "0,1" bitfld.long 0x14 1. "LSERDYIE,LSERDYIE" "0,1" newline bitfld.long 0x14 0. "LSIRDYIE,LSIRDYIE" "0,1" line.long 0x18 "RCC_MP_CIFR,This register shall be used by the MPU in order to read and clear the interrupt flags.Writing has no effect. writing will clear the corresponding flag.Refer to Section10.5: RCC interrupts for more details. If TZEN = . this register can only.." bitfld.long 0x18 20. "WKUPF,WKUPF" "0,1" bitfld.long 0x18 16. "LSECSSF,LSECSSF" "0,1" newline bitfld.long 0x18 11. "PLL4DYF,PLL4DYF" "0,1" bitfld.long 0x18 10. "PLL3DYF,PLL3DYF" "0,1" newline bitfld.long 0x18 9. "PLL2DYF,PLL2DYF" "0,1" bitfld.long 0x18 8. "PLL1DYF,PLL1DYF" "0,1" newline bitfld.long 0x18 4. "CSIRDYF,CSIRDYF" "0,1" bitfld.long 0x18 3. "HSERDYF,HSERDYF" "0,1" newline bitfld.long 0x18 2. "HSIRDYF,HSIRDYF" "0,1" bitfld.long 0x18 1. "LSERDYF,LSERDYF" "0,1" newline bitfld.long 0x18 0. "LSIRDYF,LSIRDYF" "0,1" line.long 0x1C "RCC_PWRLPDLYCR,This register is used to program the delay between the moment where the system exits from one of the Stop modes. and the moment where it is allowed to enable the PLLs and provide a clock to bridges and processors. If TZEN = . this register.." bitfld.long 0x1C 24. "MCTMPSKP,MCTMPSKP" "0,1" hexmask.long.tbyte 0x1C 0.--21. 1. "PWRLP_DLY,PWRLP_DLY" line.long 0x20 "RCC_MP_RSTSSETR,This register is dedicated to the BOOTROM code in order to update the reset source. This register is updated by the BOOTROM code. after a power-on reset (por_rst). a system reset (nreset). or an exit from Standby or CStandby. The.." bitfld.long 0x20 15. "SPARE,SPARE" "0,1" bitfld.long 0x20 14. "MPUP1RSTF,MPUP1RSTF" "0,1" newline bitfld.long 0x20 13. "MPUP0RSTF,MPUP0RSTF" "0,1" bitfld.long 0x20 12. "CSTDBYRSTF,CSTDBYRSTF" "0,1" newline bitfld.long 0x20 11. "STDBYRSTF,STDBYRSTF" "0,1" bitfld.long 0x20 9. "IWDG2RSTF,IWDG2RSTF" "0,1" newline bitfld.long 0x20 8. "IWDG1RSTF,IWDG1RSTF" "0,1" bitfld.long 0x20 7. "MCSYSRSTF,MCSYSRSTF" "0,1" newline bitfld.long 0x20 6. "MPSYSRSTF,MPSYSRSTF" "0,1" bitfld.long 0x20 4. "VCORERSTF,VCORERSTF" "0,1" newline bitfld.long 0x20 3. "HCSSRSTF,HCSSRSTF" "0,1" bitfld.long 0x20 2. "PADRSTF,PADRSTF" "0,1" newline bitfld.long 0x20 1. "BORRSTF,BORRSTF" "0,1" bitfld.long 0x20 0. "PORRSTF,PORRSTF" "0,1" group.long 0x800++0x7 line.long 0x0 "RCC_MCO1CFGR,This register is used to select the clock generated on MCO1 output." bitfld.long 0x0 12. "MCO1ON,MCO1ON" "0,1" hexmask.long.byte 0x0 4.--7. 1. "MCO1DIV,MCO1DIV" newline bitfld.long 0x0 0.--2. "MCO1SEL,MCO1SEL" "0,1,2,3,4,5,6,7" line.long 0x4 "RCC_MCO2CFGR,This register is used to select the clock generated on MCO2 output." bitfld.long 0x4 12. "MCO2ON,MCO2ON" "0,1" hexmask.long.byte 0x4 4.--7. 1. "MCO2DIV,MCO2DIV" newline bitfld.long 0x4 0.--2. "MCO2SEL,MCO2SEL" "0,1,2,3,4,5,6,7" rgroup.long 0x808++0x3 line.long 0x0 "RCC_OCRDYR,This is a read-only access register. It contains the status flags of oscillators. Writing has no effect." bitfld.long 0x0 25. "CKREST,CKREST" "0,1" bitfld.long 0x0 24. "AXICKRDY,AXICKRDY" "0,1" newline bitfld.long 0x0 23. "MPUCKRDY,MPUCKRDY" "0,1" bitfld.long 0x0 8. "HSERDY,HSERDY" "0,1" newline bitfld.long 0x0 4. "CSIRDY,CSIRDY" "0,1" bitfld.long 0x0 2. "HSIDIVRDY,HSIDIVRDY" "0,1" newline bitfld.long 0x0 0. "HSIRDY,HSIRDY" "0,1" group.long 0x80C++0x3 line.long 0x0 "RCC_DBGCFGR,This is register contains the enable control of the debug and trace function. and the clock divider for the trace function." bitfld.long 0x0 12. "DBGRST,DBGRST" "0,1" bitfld.long 0x0 9. "TRACECKEN,TRACECKEN" "0,1" newline bitfld.long 0x0 8. "DBGCKEN,DBGCKEN" "0,1" bitfld.long 0x0 0.--2. "TRACEDIV,TRACEDIV" "0,1,2,3,4,5,6,7" group.long 0x820++0x1F line.long 0x0 "RCC_RCK3SELR,This register is used to select the reference clock for PLL3. If TZEN = MCKPROT = . this register can only be modified in secure mode." rbitfld.long 0x0 31. "PLL3SRCRDY,PLL3SRCRDY" "0,1" bitfld.long 0x0 0.--1. "PLL3SRC,PLL3SRC" "0,1,2,3" line.long 0x4 "RCC_RCK4SELR,This register is used to select the reference clock for PLL4." rbitfld.long 0x4 31. "PLL4SRCRDY,PLL4SRCRDY" "0,1" bitfld.long 0x4 0.--1. "PLL4SRC,PLL4SRC" "0,1,2,3" line.long 0x8 "RCC_TIMG1PRER,This register is used to control the prescaler value of timers located into APB1 domain. It concerns TIM2. TIM3. TIM4. TIM5. TIM6. TIM7. TIM12. TIM13 and TIM14. Refer to Section: Sub-system clock generation for additional information." rbitfld.long 0x8 31. "TIMG1PRERDY,TIMG1PRERDY" "0,1" bitfld.long 0x8 0. "TIMG1PRE,TIMG1PRE" "0,1" line.long 0xC "RCC_TIMG2PRER,This register is used to control the prescaler value of timers located into APB2 domain. It concerns TIM1. TIM8. TIM15. TIM16. and TIM17. Refer to Section: Sub-system clock generation for additional information." rbitfld.long 0xC 31. "TIMG2PRERDY,TIMG2PRERDY" "0,1" bitfld.long 0xC 0. "TIMG2PRE,TIMG2PRE" "0,1" line.long 0x10 "RCC_MCUDIVR,This register is used to control the MCU sub-system clock prescaler. Refer to Section: Sub-system clock generation for additional information. If TZEN = . this register can only be modified in secure mode." rbitfld.long 0x10 31. "MCUDIVRDY,MCUDIVRDY" "0,1" hexmask.long.byte 0x10 0.--3. 1. "MCUDIV,MCUDIV" line.long 0x14 "RCC_APB1DIVR,This register is used to control the APB1 clock prescaler. Refer to section Section1.4.6.3: Sub-System Clock Generation for additional information." rbitfld.long 0x14 31. "APB1DIVRDY,APB1DIVRDY" "0,1" bitfld.long 0x14 0.--2. "APB1DIV,APB1DIV" "0,1,2,3,4,5,6,7" line.long 0x18 "RCC_APB2DIVR,This register is used to control the APB2 clock prescaler. Refer to Section: Sub-system clock generation for additional information." rbitfld.long 0x18 31. "APB2DIVRDY,APB2DIVRDY" "0,1" bitfld.long 0x18 0.--2. "APB2DIV,APB2DIV" "0,1,2,3,4,5,6,7" line.long 0x1C "RCC_APB3DIVR,This register is used to control the APB3 clock prescaler. Refer to Section: Sub-system clock generation for additional information." rbitfld.long 0x1C 31. "APB3DIVRDY,APB3DIVRDY" "0,1" bitfld.long 0x1C 0.--2. "APB3DIV,APB3DIV" "0,1,2,3,4,5,6,7" group.long 0x880++0x27 line.long 0x0 "RCC_PLL3CR,This register is used to control the PLL3. If TZEN = MCKPROT = . this register can only be modified in secure mode." bitfld.long 0x0 6. "DIVREN,DIVREN" "0,1" bitfld.long 0x0 5. "DIVQEN,DIVQEN" "0,1" newline bitfld.long 0x0 4. "DIVPEN,DIVPEN" "0,1" bitfld.long 0x0 2. "SSCG_CTRL,SSCG_CTRL" "0,1" newline rbitfld.long 0x0 1. "PLL3RDY,PLL3RDY" "0,1" bitfld.long 0x0 0. "PLLON,PLLON" "0,1" line.long 0x4 "RCC_PLL3CFGR1,This register is used to configure the PLL3. If TZEN = MCKPROT = . this register can only be modified in secure mode." bitfld.long 0x4 24.--25. "IFRGE,IFRGE" "0,1,2,3" hexmask.long.byte 0x4 16.--21. 1. "DIVM3,DIVM3" newline hexmask.long.word 0x4 0.--8. 1. "DIVN,DIVN" line.long 0x8 "RCC_PLL3CFGR2,This register is used to configure the PLL3. If TZEN = MCKPROT = . this register can only be modified in secure mode." hexmask.long.byte 0x8 16.--22. 1. "DIVR,DIVR" hexmask.long.byte 0x8 8.--14. 1. "DIVQ,DIVQ" newline hexmask.long.byte 0x8 0.--6. 1. "DIVP,DIVP" line.long 0xC "RCC_PLL3FRACR,This register is used to fine-tune the frequency of the PLL3 VCO. If TZEN = MCKPROT = . this register can only be modified in secure mode." bitfld.long 0xC 16. "FRACLE,FRACLE" "0,1" hexmask.long.word 0xC 3.--15. 1. "FRACV,FRACV" line.long 0x10 "RCC_PLL3CSGR,This register is used to configure the PLL3.It is not recommended to change the content of this register when the PLL3 is enabled (PLLON = ). Refer to Section: Using the PLLs in spread spectrum mode for details. If TZEN = MCKPROT = . this.." hexmask.long.word 0x10 16.--30. 1. "INC_STEP,INC_STEP" bitfld.long 0x10 15. "SSCG_MODE,SSCG_MODE" "0,1" newline bitfld.long 0x10 14. "RPDFN_DIS,RPDFN_DIS" "0,1" bitfld.long 0x10 13. "TPDFN_DIS,TPDFN_DIS" "0,1" newline hexmask.long.word 0x10 0.--12. 1. "MOD_PER,MOD_PER" line.long 0x14 "RCC_PLL4CR,This register is used to control the PLL4." bitfld.long 0x14 6. "DIVREN,DIVREN" "0,1" bitfld.long 0x14 5. "DIVQEN,DIVQEN" "0,1" newline bitfld.long 0x14 4. "DIVPEN,DIVPEN" "0,1" bitfld.long 0x14 2. "SSCG_CTRL,SSCG_CTRL" "0,1" newline rbitfld.long 0x14 1. "PLL4RDY,PLL4RDY" "0,1" bitfld.long 0x14 0. "PLLON,PLLON" "0,1" line.long 0x18 "RCC_PLL4CFGR1,This register is used to configure the PLL4." bitfld.long 0x18 24.--25. "IFRGE,IFRGE" "0,1,2,3" hexmask.long.byte 0x18 16.--21. 1. "DIVM4,DIVM4" newline hexmask.long.word 0x18 0.--8. 1. "DIVN,DIVN" line.long 0x1C "RCC_PLL4CFGR2,This register is used to configure the PLL4." hexmask.long.byte 0x1C 16.--22. 1. "DIVR,DIVR" hexmask.long.byte 0x1C 8.--14. 1. "DIVQ,DIVQ" newline hexmask.long.byte 0x1C 0.--6. 1. "DIVP,DIVP" line.long 0x20 "RCC_PLL4FRACR,This register is used to fine-tune the frequency of the PLL4 VCO." bitfld.long 0x20 16. "FRACLE,FRACLE" "0,1" hexmask.long.word 0x20 3.--15. 1. "FRACV,FRACV" line.long 0x24 "RCC_PLL4CSGR,This register is used to configure the PLL4.It is not recommended to change the content of this register when the PLL4 is enabled (PLLON = ). Refer to Section: Using the PLLs in spread spectrum mode for details. If TZEN = MCKPROT = . this.." hexmask.long.word 0x24 16.--30. 1. "INC_STEP,INC_STEP" bitfld.long 0x24 15. "SSCG_MODE,SSCG_MODE" "0,1" newline bitfld.long 0x24 14. "RPDFN_DIS,RPDFN_DIS" "0,1" bitfld.long 0x24 13. "TPDFN_DIS,TPDFN_DIS" "0,1" newline hexmask.long.word 0x24 0.--12. 1. "MOD_PER,MOD_PER" group.long 0x8C0++0x47 line.long 0x0 "RCC_I2C12CKSELR,This register is used to control the selection of the kernel clock for the I2C1 and I2C2. Note that changing the clock source on-the-fly is allowed. and will not generate any timing violation. however the user has to ensure that both the.." bitfld.long 0x0 0.--2. "I2C12SRC,I2C12SRC" "0,1,2,3,4,5,6,7" line.long 0x4 "RCC_I2C35CKSELR,This register is used to control the selection of the kernel clock for the I2C3 and I2C5. Note that changing the clock source on-the-fly is allowed. and will not generate any timing violation. however the user has to ensure that both the.." bitfld.long 0x4 0.--2. "I2C35SRC,I2C35SRC" "0,1,2,3,4,5,6,7" line.long 0x8 "RCC_SAI1CKSELR,This register is used to control the selection of the kernel clock for the SAI1 and DFSDM audio clock. Note that changing the clock source on-the-fly is allowed. and will not generate any timing violation. however the user has to ensure.." bitfld.long 0x8 0.--2. "SAI1SRC,SAI1SRC" "0,1,2,3,4,5,6,7" line.long 0xC "RCC_SAI2CKSELR,This register is used to control the selection of the kernel clock for the SAI2. Note that changing the clock source on-the-fly is allowed. and will not generate any timing violation. however the user has to ensure that both the previous.." bitfld.long 0xC 0.--2. "SAI2SRC,SAI2SRC" "0,1,2,3,4,5,6,7" line.long 0x10 "RCC_SAI3CKSELR,This register is used to control the selection of the kernel clock for the SAI3. Note that changing the clock source on-the-fly is allowed. and will not generate any timing violation. however the user has to ensure that both the previous.." bitfld.long 0x10 0.--2. "SAI3SRC,SAI3SRC" "0,1,2,3,4,5,6,7" line.long 0x14 "RCC_SAI4CKSELR,This register is used to control the selection of the kernel clock for the SAI4. Note that changing the clock source on-the-fly is allowed. and will not generate any timing violation. however the user has to ensure that both the previous.." bitfld.long 0x14 0.--2. "SAI4SRC,SAI4SRC" "0,1,2,3,4,5,6,7" line.long 0x18 "RCC_SPI2S1CKSELR,This register is used to control the selection of the kernel clock for the SPI/I2S1. Note that changing the clock source on-the-fly is allowed. and will not generate any timing violation. however the user has to ensure that both the.." bitfld.long 0x18 0.--2. "SPI1SRC,SPI1SRC" "0,1,2,3,4,5,6,7" line.long 0x1C "RCC_SPI2S23CKSELR,This register is used to control the selection of the kernel clock for the SPI/I2S2.3. Note that changing the clock source on-the-fly is allowed. and will not generate any timing violation. however the user has to ensure that both the.." bitfld.long 0x1C 0.--2. "SPI23SRC,SPI23SRC" "0,1,2,3,4,5,6,7" line.long 0x20 "RCC_SPI45CKSELR,This register is used to control the selection of the kernel clock for the SPI4.5. Note that changing the clock source on-the-fly is allowed. and will not generate any timing violation. however the user has to ensure that both the.." bitfld.long 0x20 0.--2. "SPI45SRC,SPI45SRC" "0,1,2,3,4,5,6,7" line.long 0x24 "RCC_UART6CKSELR,This register is used to control the selection of the kernel clock for the USART6. Note that changing the clock source on-the-fly is allowed. and will not generate any timing violation. however the user has to ensure that both the.." bitfld.long 0x24 0.--2. "UART6SRC,UART6SRC" "0,1,2,3,4,5,6,7" line.long 0x28 "RCC_UART24CKSELR,This register is used to control the selection of the kernel clock for the USART2 and UART4. Note that changing the clock source on-the-fly is allowed. and will not generate any timing violation. however the user has to ensure that both.." bitfld.long 0x28 0.--2. "UART24SRC,UART24SRC" "0,1,2,3,4,5,6,7" line.long 0x2C "RCC_UART35CKSELR,This register is used to control the selection of the kernel clock for the USART3 and UART5. Note that changing the clock source on-the-fly is allowed. and will not generate any timing violation. however the user has to ensure that both.." bitfld.long 0x2C 0.--2. "UART35SRC,UART35SRC" "0,1,2,3,4,5,6,7" line.long 0x30 "RCC_UART78CKSELR,This register is used to control the selection of the kernel clock for the UART7 and UART8. Note that changing the clock source on-the-fly is allowed. and will not generate any timing violation. however the user has to ensure that both.." bitfld.long 0x30 0.--2. "UART78SRC,UART78SRC" "0,1,2,3,4,5,6,7" line.long 0x34 "RCC_SDMMC12CKSELR,This register is used to control the selection of the kernel clock for the SDMMC1 and SDMMC2. Note that changing the clock source on-the-fly is allowed. and will not generate any timing violation. however the user has to ensure that.." bitfld.long 0x34 0.--2. "SDMMC12SRC,SDMMC12SRC" "0,1,2,3,4,5,6,7" line.long 0x38 "RCC_SDMMC3CKSELR,This register is used to control the selection of the kernel clock for the SDMMC3. Note that changing the clock source on-the-fly is allowed. and will not generate any timing violation. however the user has to ensure that both the.." bitfld.long 0x38 0.--2. "SDMMC3SRC,SDMMC3SRC" "0,1,2,3,4,5,6,7" line.long 0x3C "RCC_ETHCKSELR,This register is used to control the selection of the kernel clock for the ETH block. Note that changing the clock source on-the-fly is allowed. and will not generate any timing violation. however the user has to ensure that both the.." hexmask.long.byte 0x3C 4.--7. 1. "ETHPTPDIV,ETHPTPDIV" bitfld.long 0x3C 0.--1. "ETHSRC,ETHSRC" "0,1,2,3" line.long 0x40 "RCC_QSPICKSELR,This register is used to control the selection of the kernel clock for the QUADSPI. Note that changing the clock source on-the-fly is allowed. and will not generate any timing violation. however the user has to ensure that both the.." bitfld.long 0x40 0.--1. "QSPISRC,QSPISRC" "0,1,2,3" line.long 0x44 "RCC_FMCCKSELR,This register is used to control the selection of the kernel clock for the FMC block. Note that changing the clock source on-the-fly is allowed. and will not generate any timing violation. however the user has to ensure that both the.." bitfld.long 0x44 0.--1. "FMCSRC,FMCSRC" "0,1,2,3" group.long 0x90C++0x3 line.long 0x0 "RCC_FDCANCKSELR,This register is used to control the selection of the kernel clock for the FDCAN block. Note that changing the clock source on-the-fly is allowed. and will not generate any timing violation. however the user has to ensure that both the.." bitfld.long 0x0 0.--1. "FDCANSRC,FDCANSRC" "0,1,2,3" group.long 0x914++0x23 line.long 0x0 "RCC_SPDIFCKSELR,This register is used to control the selection of the kernel clock for the SPDIFRX. Note that changing the clock source on-the-fly is allowed. and will not generate any timing violation. however the user has to ensure that both the.." bitfld.long 0x0 0.--1. "SPDIFSRC,SPDIFSRC" "0,1,2,3" line.long 0x4 "RCC_CECCKSELR,This register is used to control the selection of the kernel clock for the CEC-HDMI." bitfld.long 0x4 0.--1. "CECSRC,CECSRC" "0,1,2,3" line.long 0x8 "RCC_USBCKSELR,This register is used to control the selection of the kernel clock for the USBPHY PLL of the USB HOST and USB OTG" bitfld.long 0x8 4. "USBOSRC,USBOSRC" "0,1" bitfld.long 0x8 0.--1. "USBPHYSRC,USBPHYSRC" "0,1,2,3" line.long 0xC "RCC_RNG2CKSELR,This register is used to control the selection of the kernel clock for the RNG2." bitfld.long 0xC 0.--1. "RNG2SRC,RNG2SRC" "0,1,2,3" line.long 0x10 "RCC_DSICKSELR,This register is used to control the selection of the kernel clock for the DSI block." bitfld.long 0x10 0. "DSISRC,DSISRC" "0,1" line.long 0x14 "RCC_ADCCKSELR,This register is used to control the selection of the kernel clock for the ADC block." bitfld.long 0x14 0.--1. "ADCSRC,ADCSRC" "0,1,2,3" line.long 0x18 "RCC_LPTIM45CKSELR,This register is used to control the selection of the kernel clock for the LPTIM4 and LPTIM5 blocks." bitfld.long 0x18 0.--2. "LPTIM45SRC,LPTIM45SRC" "0,1,2,3,4,5,6,7" line.long 0x1C "RCC_LPTIM23CKSELR,This register is used to control the selection of the kernel clock for the LPTIM2 and LPTIM3 blocks." bitfld.long 0x1C 0.--2. "LPTIM23SRC,LPTIM23SRC" "0,1,2,3,4,5,6,7" line.long 0x20 "RCC_LPTIM1CKSELR,This register is used to control the selection of the kernel clock for the LPTIM1 block." bitfld.long 0x20 0.--2. "LPTIM1SRC,LPTIM1SRC" "0,1,2,3,4,5,6,7" group.long 0x980++0x2F line.long 0x0 "RCC_APB1RSTSETR,This register is used to activate the reset of the corresponding peripheral." bitfld.long 0x0 31. "MDIOSRST,MDIOSRST" "0,1" bitfld.long 0x0 29. "DAC12RST,DAC12RST" "0,1" newline bitfld.long 0x0 27. "CECRST,CECRST" "0,1" bitfld.long 0x0 26. "SPDIFRST,SPDIFRST" "0,1" newline bitfld.long 0x0 24. "I2C5RST,I2C5RST" "0,1" bitfld.long 0x0 23. "I2C3RST,I2C3RST" "0,1" newline bitfld.long 0x0 22. "I2C2RST,I2C2RST" "0,1" bitfld.long 0x0 21. "I2C1RST,I2C1RST" "0,1" newline bitfld.long 0x0 19. "UART8RST,UART8RST" "0,1" bitfld.long 0x0 18. "UART7RST,UART7RST" "0,1" newline bitfld.long 0x0 17. "UART5RST,UART5RST" "0,1" bitfld.long 0x0 16. "UART4RST,UART4RST" "0,1" newline bitfld.long 0x0 15. "USART3RST,USART3RST" "0,1" bitfld.long 0x0 14. "USART2RST,USART2RST" "0,1" newline bitfld.long 0x0 12. "SPI3RST,SPI3RST" "0,1" bitfld.long 0x0 11. "SPI2RST,SPI2RST" "0,1" newline bitfld.long 0x0 9. "LPTIM1RST,LPTIM1RST" "0,1" bitfld.long 0x0 8. "TIM14RST,TIM14RST" "0,1" newline bitfld.long 0x0 7. "TIM13RST,TIM13RST" "0,1" bitfld.long 0x0 6. "TIM12RST,TIM12RST" "0,1" newline bitfld.long 0x0 5. "TIM7RST,TIM7RST" "0,1" bitfld.long 0x0 4. "TIM6RST,TIM6RST" "0,1" newline bitfld.long 0x0 3. "TIM5RST,TIM5RST" "0,1" bitfld.long 0x0 2. "TIM4RST,TIM4RST" "0,1" newline bitfld.long 0x0 1. "TIM3RST,TIM3RST" "0,1" bitfld.long 0x0 0. "TIM2RST,TIM2RST" "0,1" line.long 0x4 "RCC_APB1RSTCLRR,This register is used to release the reset of the corresponding peripheral." bitfld.long 0x4 31. "MDIOSRST,MDIOSRST" "0,1" bitfld.long 0x4 29. "DAC12RST,DAC12RST" "0,1" newline bitfld.long 0x4 27. "CECRST,CECRST" "0,1" bitfld.long 0x4 26. "SPDIFRST,SPDIFRST" "0,1" newline bitfld.long 0x4 24. "I2C5RST,I2C5RST" "0,1" bitfld.long 0x4 23. "I2C3RST,I2C3RST" "0,1" newline bitfld.long 0x4 22. "I2C2RST,I2C2RST" "0,1" bitfld.long 0x4 21. "I2C1RST,I2C1RST" "0,1" newline bitfld.long 0x4 19. "UART8RST,UART8RST" "0,1" bitfld.long 0x4 18. "UART7RST,UART7RST" "0,1" newline bitfld.long 0x4 17. "UART5RST,UART5RST" "0,1" bitfld.long 0x4 16. "UART4RST,UART4RST" "0,1" newline bitfld.long 0x4 15. "USART3RST,USART3RST" "0,1" bitfld.long 0x4 14. "USART2RST,USART2RST" "0,1" newline bitfld.long 0x4 12. "SPI3RST,SPI3RST" "0,1" bitfld.long 0x4 11. "SPI2RST,SPI2RST" "0,1" newline bitfld.long 0x4 9. "LPTIM1RST,LPTIM1RST" "0,1" bitfld.long 0x4 8. "TIM14RST,TIM14RST" "0,1" newline bitfld.long 0x4 7. "TIM13RST,TIM13RST" "0,1" bitfld.long 0x4 6. "TIM12RST,TIM12RST" "0,1" newline bitfld.long 0x4 5. "TIM7RST,TIM7RST" "0,1" bitfld.long 0x4 4. "TIM6RST,TIM6RST" "0,1" newline bitfld.long 0x4 3. "TIM5RST,TIM5RST" "0,1" bitfld.long 0x4 2. "TIM4RST,TIM4RST" "0,1" newline bitfld.long 0x4 1. "TIM3RST,TIM3RST" "0,1" bitfld.long 0x4 0. "TIM2RST,TIM2RST" "0,1" line.long 0x8 "RCC_APB2RSTSETR,This register is used to activate the reset of the corresponding peripheral." bitfld.long 0x8 24. "FDCANRST,FDCANRST" "0,1" bitfld.long 0x8 20. "DFSDMRST,DFSDMRST" "0,1" newline bitfld.long 0x8 18. "SAI3RST,SAI3RST" "0,1" bitfld.long 0x8 17. "SAI2RST,SAI2RST" "0,1" newline bitfld.long 0x8 16. "SAI1RST,SAI1RST" "0,1" bitfld.long 0x8 13. "USART6RST,USART6RST" "0,1" newline bitfld.long 0x8 10. "SPI5RST,SPI5RST" "0,1" bitfld.long 0x8 9. "SPI4RST,SPI4RST" "0,1" newline bitfld.long 0x8 8. "SPI1RST,SPI1RST" "0,1" bitfld.long 0x8 4. "TIM17RST,TIM17RST" "0,1" newline bitfld.long 0x8 3. "TIM16RST,TIM16RST" "0,1" bitfld.long 0x8 2. "TIM15RST,TIM15RST" "0,1" newline bitfld.long 0x8 1. "TIM8RST,TIM8RST" "0,1" bitfld.long 0x8 0. "TIM1RST,TIM1RST" "0,1" line.long 0xC "RCC_APB2RSTCLRR,This register is used to release the reset of the corresponding peripheral." bitfld.long 0xC 24. "FDCANRST,FDCANRST" "0,1" bitfld.long 0xC 20. "DFSDMRST,DFSDMRST" "0,1" newline bitfld.long 0xC 18. "SAI3RST,SAI3RST" "0,1" bitfld.long 0xC 17. "SAI2RST,SAI2RST" "0,1" newline bitfld.long 0xC 16. "SAI1RST,SAI1RST" "0,1" bitfld.long 0xC 13. "USART6RST,USART6RST" "0,1" newline bitfld.long 0xC 10. "SPI5RST,SPI5RST" "0,1" bitfld.long 0xC 9. "SPI4RST,SPI4RST" "0,1" newline bitfld.long 0xC 8. "SPI1RST,SPI1RST" "0,1" bitfld.long 0xC 4. "TIM17RST,TIM17RST" "0,1" newline bitfld.long 0xC 3. "TIM16RST,TIM16RST" "0,1" bitfld.long 0xC 2. "TIM15RST,TIM15RST" "0,1" newline bitfld.long 0xC 1. "TIM8RST,TIM8RST" "0,1" bitfld.long 0xC 0. "TIM1RST,TIM1RST" "0,1" line.long 0x10 "RCC_APB3RSTSETR,This register is used to activate the reset of the corresponding peripheral." bitfld.long 0x10 16. "DTSRST,DTSRST" "0,1" bitfld.long 0x10 13. "VREFRST,VREFRST" "0,1" newline bitfld.long 0x10 11. "SYSCFGRST,SYSCFGRST" "0,1" bitfld.long 0x10 8. "SAI4RST,SAI4RST" "0,1" newline bitfld.long 0x10 3. "LPTIM5RST,LPTIM5RST" "0,1" bitfld.long 0x10 2. "LPTIM4RST,LPTIM4RST" "0,1" newline bitfld.long 0x10 1. "LPTIM3RST,LPTIM3RST" "0,1" bitfld.long 0x10 0. "LPTIM2RST,LPTIM2RST" "0,1" line.long 0x14 "RCC_APB3RSTCLRR,This register is used to release the reset of the corresponding peripheral." bitfld.long 0x14 16. "DTSRST,DTSRST" "0,1" bitfld.long 0x14 13. "VREFRST,VREFRST" "0,1" newline bitfld.long 0x14 11. "SYSCFGRST,SYSCFGRST" "0,1" bitfld.long 0x14 8. "SAI4RST,SAI4RST" "0,1" newline bitfld.long 0x14 3. "LPTIM5RST,LPTIM5RST" "0,1" bitfld.long 0x14 2. "LPTIM4RST,LPTIM4RST" "0,1" newline bitfld.long 0x14 1. "LPTIM3RST,LPTIM3RST" "0,1" bitfld.long 0x14 0. "LPTIM2RST,LPTIM2RST" "0,1" line.long 0x18 "RCC_AHB2RSTSETR,This register is used to activate the reset of the corresponding peripheral." bitfld.long 0x18 16. "SDMMC3RST,SDMMC3RST" "0,1" bitfld.long 0x18 8. "USBORST,USBORST" "0,1" newline bitfld.long 0x18 5. "ADC12RST,ADC12RST" "0,1" bitfld.long 0x18 2. "DMAMUXRST,DMAMUXRST" "0,1" newline bitfld.long 0x18 1. "DMA2RST,DMA2RST" "0,1" bitfld.long 0x18 0. "DMA1RST,DMA1RST" "0,1" line.long 0x1C "RCC_AHB2RSTCLRR,This register is used to release the reset of the corresponding peripheral." bitfld.long 0x1C 16. "SDMMC3RST,SDMMC3RST" "0,1" bitfld.long 0x1C 8. "USBORST,USBORST" "0,1" newline bitfld.long 0x1C 5. "ADC12RST,ADC12RST" "0,1" bitfld.long 0x1C 2. "DMAMUXRST,DMAMUXRST" "0,1" newline bitfld.long 0x1C 1. "DMA2RST,DMA2RST" "0,1" bitfld.long 0x1C 0. "DMA1RST,DMA1RST" "0,1" line.long 0x20 "RCC_AHB3RSTSETR,This register is used to activate the reset of the corresponding peripheral." bitfld.long 0x20 12. "IPCCRST,IPCCRST" "0,1" bitfld.long 0x20 11. "HSEMRST,HSEMRST" "0,1" newline bitfld.long 0x20 7. "CRC2RST,CRC2RST" "0,1" bitfld.long 0x20 6. "RNG2RST,RNG2RST" "0,1" newline bitfld.long 0x20 5. "HASH2RST,HASH2RST" "0,1" bitfld.long 0x20 4. "CRYP2RST,CRYP2RST" "0,1" newline bitfld.long 0x20 0. "DCMIRST,DCMIRST" "0,1" line.long 0x24 "RCC_AHB3RSTCLRR,This register is used to release the reset of the corresponding peripheral." bitfld.long 0x24 12. "IPCCRST,IPCCRST" "0,1" bitfld.long 0x24 11. "HSEMRST,HSEMRST" "0,1" newline bitfld.long 0x24 7. "CRC2RST,CRC2RST" "0,1" bitfld.long 0x24 6. "RNG2RST,RNG2RST" "0,1" newline bitfld.long 0x24 5. "HASH2RST,HASH2RST" "0,1" bitfld.long 0x24 4. "CRYP2RST,CRYP2RST" "0,1" newline bitfld.long 0x24 0. "DCMIRST,DCMIRST" "0,1" line.long 0x28 "RCC_AHB4RSTSETR,This register is used to activate the reset of the corresponding peripheral" bitfld.long 0x28 10. "GPIOKRST,GPIOKRST" "0,1" bitfld.long 0x28 9. "GPIOJRST,GPIOJRST" "0,1" newline bitfld.long 0x28 8. "GPIOIRST,GPIOIRST" "0,1" bitfld.long 0x28 7. "GPIOHRST,GPIOHRST" "0,1" newline bitfld.long 0x28 6. "GPIOGRST,GPIOGRST" "0,1" bitfld.long 0x28 5. "GPIOFRST,GPIOFRST" "0,1" newline bitfld.long 0x28 4. "GPIOERST,GPIOERST" "0,1" bitfld.long 0x28 3. "GPIODRST,GPIODRST" "0,1" newline bitfld.long 0x28 2. "GPIOCRST,GPIOCRST" "0,1" bitfld.long 0x28 1. "GPIOBRST,GPIOBRST" "0,1" newline bitfld.long 0x28 0. "GPIOARST,GPIOARST" "0,1" line.long 0x2C "RCC_AHB4RSTCLRR,This register is used to release the reset of the corresponding peripheral." bitfld.long 0x2C 10. "GPIOKRST,GPIOKRST" "0,1" bitfld.long 0x2C 9. "GPIOJRST,GPIOJRST" "0,1" newline bitfld.long 0x2C 8. "GPIOIRST,GPIOIRST" "0,1" bitfld.long 0x2C 7. "GPIOHRST,GPIOHRST" "0,1" newline bitfld.long 0x2C 6. "GPIOGRST,GPIOGRST" "0,1" bitfld.long 0x2C 5. "GPIOFRST,GPIOFRST" "0,1" newline bitfld.long 0x2C 4. "GPIOERST,GPIOERST" "0,1" bitfld.long 0x2C 3. "GPIODRST,GPIODRST" "0,1" newline bitfld.long 0x2C 2. "GPIOCRST,GPIOCRST" "0,1" bitfld.long 0x2C 1. "GPIOBRST,GPIOBRST" "0,1" newline bitfld.long 0x2C 0. "GPIOARST,GPIOARST" "0,1" group.long 0xA00++0x2F line.long 0x0 "RCC_MP_APB1ENSETR,This register is used to set the peripheral clock enable bit" bitfld.long 0x0 31. "MDIOSEN,MDIOSEN" "0,1" bitfld.long 0x0 29. "DAC12EN,DAC12EN" "0,1" newline bitfld.long 0x0 27. "CECEN,CECEN" "0,1" bitfld.long 0x0 26. "SPDIFEN,SPDIFEN" "0,1" newline bitfld.long 0x0 24. "I2C5EN,I2C5EN" "0,1" bitfld.long 0x0 23. "I2C3EN,I2C3EN" "0,1" newline bitfld.long 0x0 22. "I2C2EN,I2C2EN" "0,1" bitfld.long 0x0 21. "I2C1EN,I2C1EN" "0,1" newline bitfld.long 0x0 19. "UART8EN,UART8EN" "0,1" bitfld.long 0x0 18. "UART7EN,UART7EN" "0,1" newline bitfld.long 0x0 17. "UART5EN,UART5EN" "0,1" bitfld.long 0x0 16. "UART4EN,UART4EN" "0,1" newline bitfld.long 0x0 15. "USART3EN,USART3EN" "0,1" bitfld.long 0x0 14. "USART2EN,USART2EN" "0,1" newline bitfld.long 0x0 12. "SPI3EN,SPI3EN" "0,1" bitfld.long 0x0 11. "SPI2EN,SPI2EN" "0,1" newline bitfld.long 0x0 9. "LPTIM1EN,LPTIM1EN" "0,1" bitfld.long 0x0 8. "TIM14EN,TIM14EN" "0,1" newline bitfld.long 0x0 7. "TIM13EN,TIM13EN" "0,1" bitfld.long 0x0 6. "TIM12EN,TIM12EN" "0,1" newline bitfld.long 0x0 5. "TIM7EN,TIM7EN" "0,1" bitfld.long 0x0 4. "TIM6EN,TIM6EN" "0,1" newline bitfld.long 0x0 3. "TIM5EN,TIM5EN" "0,1" bitfld.long 0x0 2. "TIM4EN,TIM4EN" "0,1" newline bitfld.long 0x0 1. "TIM3EN,TIM3EN" "0,1" bitfld.long 0x0 0. "TIM2EN,TIM2EN" "0,1" line.long 0x4 "RCC_MP_APB1ENCLRR,This register is used to clear the peripheral clock enable bit" bitfld.long 0x4 31. "MDIOSEN,MDIOSEN" "0,1" bitfld.long 0x4 29. "DAC12EN,DAC12EN" "0,1" newline bitfld.long 0x4 27. "CECEN,CECEN" "0,1" bitfld.long 0x4 26. "SPDIFEN,SPDIFEN" "0,1" newline bitfld.long 0x4 24. "I2C5EN,I2C5EN" "0,1" bitfld.long 0x4 23. "I2C3EN,I2C3EN" "0,1" newline bitfld.long 0x4 22. "I2C2EN,I2C2EN" "0,1" bitfld.long 0x4 21. "I2C1EN,I2C1EN" "0,1" newline bitfld.long 0x4 19. "UART8EN,UART8EN" "0,1" bitfld.long 0x4 18. "UART7EN,UART7EN" "0,1" newline bitfld.long 0x4 17. "UART5EN,UART5EN" "0,1" bitfld.long 0x4 16. "UART4EN,UART4EN" "0,1" newline bitfld.long 0x4 15. "USART3EN,USART3EN" "0,1" bitfld.long 0x4 14. "USART2EN,USART2EN" "0,1" newline bitfld.long 0x4 12. "SPI3EN,SPI3EN" "0,1" bitfld.long 0x4 11. "SPI2EN,SPI2EN" "0,1" newline bitfld.long 0x4 9. "LPTIM1EN,LPTIM1EN" "0,1" bitfld.long 0x4 8. "TIM14EN,TIM14EN" "0,1" newline bitfld.long 0x4 7. "TIM13EN,TIM13EN" "0,1" bitfld.long 0x4 6. "TIM12EN,TIM12EN" "0,1" newline bitfld.long 0x4 5. "TIM7EN,TIM7EN" "0,1" bitfld.long 0x4 4. "TIM6EN,TIM6EN" "0,1" newline bitfld.long 0x4 3. "TIM5EN,TIM5EN" "0,1" bitfld.long 0x4 2. "TIM4EN,TIM4EN" "0,1" newline bitfld.long 0x4 1. "TIM3EN,TIM3EN" "0,1" bitfld.long 0x4 0. "TIM2EN,TIM2EN" "0,1" line.long 0x8 "RCC_MP_APB2ENSETR,This register is used to set the peripheral clock enable bit" bitfld.long 0x8 24. "FDCANEN,FDCANEN" "0,1" bitfld.long 0x8 21. "ADFSDMEN,ADFSDMEN" "0,1" newline bitfld.long 0x8 20. "DFSDMEN,DFSDMEN" "0,1" bitfld.long 0x8 18. "SAI3EN,SAI3EN" "0,1" newline bitfld.long 0x8 17. "SAI2EN,SAI2EN" "0,1" bitfld.long 0x8 16. "SAI1EN,SAI1EN" "0,1" newline bitfld.long 0x8 13. "USART6EN,USART6EN" "0,1" bitfld.long 0x8 10. "SPI5EN,SPI5EN" "0,1" newline bitfld.long 0x8 9. "SPI4EN,SPI4EN" "0,1" bitfld.long 0x8 8. "SPI1EN,SPI1EN" "0,1" newline bitfld.long 0x8 4. "TIM17EN,TIM17EN" "0,1" bitfld.long 0x8 3. "TIM16EN,TIM16EN" "0,1" newline bitfld.long 0x8 2. "TIM15EN,TIM15EN" "0,1" bitfld.long 0x8 1. "TIM8EN,TIM8EN" "0,1" newline bitfld.long 0x8 0. "TIM1EN,TIM1EN" "0,1" line.long 0xC "RCC_MP_APB2ENCLRR,This register is used to clear the peripheral clock enable bit of the corresponding peripheral." bitfld.long 0xC 24. "FDCANEN,FDCANEN" "0,1" bitfld.long 0xC 21. "ADFSDMEN,ADFSDMEN" "0,1" newline bitfld.long 0xC 20. "DFSDMEN,DFSDMEN" "0,1" bitfld.long 0xC 18. "SAI3EN,SAI3EN" "0,1" newline bitfld.long 0xC 17. "SAI2EN,SAI2EN" "0,1" bitfld.long 0xC 16. "SAI1EN,SAI1EN" "0,1" newline bitfld.long 0xC 13. "USART6EN,USART6EN" "0,1" bitfld.long 0xC 10. "SPI5EN,SPI5EN" "0,1" newline bitfld.long 0xC 9. "SPI4EN,SPI4EN" "0,1" bitfld.long 0xC 8. "SPI1EN,SPI1EN" "0,1" newline bitfld.long 0xC 4. "TIM17EN,TIM17EN" "0,1" bitfld.long 0xC 3. "TIM16EN,TIM16EN" "0,1" newline bitfld.long 0xC 2. "TIM15EN,TIM15EN" "0,1" bitfld.long 0xC 1. "TIM8EN,TIM8EN" "0,1" newline bitfld.long 0xC 0. "TIM1EN,TIM1EN" "0,1" line.long 0x10 "RCC_MP_APB3ENSETR,This register is used to set the peripheral clock enable bit" bitfld.long 0x10 20. "HDPEN,HDPEN" "0,1" bitfld.long 0x10 16. "DTSEN,DTSEN" "0,1" newline bitfld.long 0x10 13. "VREFEN,VREFEN" "0,1" bitfld.long 0x10 11. "SYSCFGEN,SYSCFGEN" "0,1" newline bitfld.long 0x10 8. "SAI4EN,SAI4EN" "0,1" bitfld.long 0x10 3. "LPTIM5EN,LPTIM5EN" "0,1" newline bitfld.long 0x10 2. "LPTIM4EN,LPTIM4EN" "0,1" bitfld.long 0x10 1. "LPTIM3EN,LPTIM3EN" "0,1" newline bitfld.long 0x10 0. "LPTIM2EN,LPTIM2EN" "0,1" line.long 0x14 "RCC_MP_APB3ENCLRR,This register is used to clear the peripheral clock enable bit of the corresponding peripheral." bitfld.long 0x14 20. "HDPEN,HDPEN" "0,1" bitfld.long 0x14 16. "DTSEN,DTSEN" "0,1" newline bitfld.long 0x14 13. "VREFEN,VREFEN" "0,1" bitfld.long 0x14 11. "SYSCFGEN,SYSCFGEN" "0,1" newline bitfld.long 0x14 8. "SAI4EN,SAI4EN" "0,1" bitfld.long 0x14 3. "LPTIM5EN,LPTIM5EN" "0,1" newline bitfld.long 0x14 2. "LPTIM4EN,LPTIM4EN" "0,1" bitfld.long 0x14 1. "LPTIM3EN,LPTIM3EN" "0,1" newline bitfld.long 0x14 0. "LPTIM2EN,LPTIM2EN" "0,1" line.long 0x18 "RCC_MP_AHB2ENSETR,This register is used to set the peripheral clock enable bit of the corresponding peripheral" bitfld.long 0x18 16. "SDMMC3EN,SDMMC3EN" "0,1" bitfld.long 0x18 8. "USBOEN,USBOEN" "0,1" newline bitfld.long 0x18 5. "ADC12EN,ADC12EN" "0,1" bitfld.long 0x18 2. "DMAMUXEN,DMAMUXEN" "0,1" newline bitfld.long 0x18 1. "DMA2EN,DMA2EN" "0,1" bitfld.long 0x18 0. "DMA1EN,DMA1EN" "0,1" line.long 0x1C "RCC_MP_AHB2ENCLRR,This register is used to clear the peripheral clock enable bit of the corresponding peripheral." bitfld.long 0x1C 16. "SDMMC3EN,SDMMC3EN" "0,1" bitfld.long 0x1C 8. "USBOEN,USBOEN" "0,1" newline bitfld.long 0x1C 5. "ADC12EN,ADC12EN" "0,1" bitfld.long 0x1C 2. "DMAMUXEN,DMAMUXEN" "0,1" newline bitfld.long 0x1C 1. "DMA2EN,DMA2EN" "0,1" bitfld.long 0x1C 0. "DMA1EN,DMA1EN" "0,1" line.long 0x20 "RCC_MP_AHB3ENSETR,This register is used to set the peripheral clock enable bit of the corresponding peripheral" bitfld.long 0x20 12. "IPCCEN,IPCCEN" "0,1" bitfld.long 0x20 11. "HSEMEN,HSEMEN" "0,1" newline bitfld.long 0x20 7. "CRC2EN,CRC2EN" "0,1" bitfld.long 0x20 6. "RNG2EN,RNG2EN" "0,1" newline bitfld.long 0x20 5. "HASH2EN,HASH2EN" "0,1" bitfld.long 0x20 4. "CRYP2EN,CRYP2EN" "0,1" newline bitfld.long 0x20 0. "DCMIEN,DCMIEN" "0,1" line.long 0x24 "RCC_MP_AHB3ENCLRR,This register is used to clear the peripheral clock enable bit of the corresponding peripheral." bitfld.long 0x24 12. "IPCCEN,IPCCEN" "0,1" bitfld.long 0x24 11. "HSEMEN,HSEMEN" "0,1" newline bitfld.long 0x24 7. "CRC2EN,CRC2EN" "0,1" bitfld.long 0x24 6. "RNG2EN,RNG2EN" "0,1" newline bitfld.long 0x24 5. "HASH2EN,HASH2EN" "0,1" bitfld.long 0x24 4. "CRYP2EN,CRYP2EN" "0,1" newline bitfld.long 0x24 0. "DCMIEN,DCMIEN" "0,1" line.long 0x28 "RCC_MP_AHB4ENSETR,This register is used to set the peripheral clock enable bit of the corresponding peripheral to . It shall be used to allocate a peripheral to the MPU." bitfld.long 0x28 10. "GPIOKEN,GPIOKEN" "0,1" bitfld.long 0x28 9. "GPIOJEN,GPIOJEN" "0,1" newline bitfld.long 0x28 8. "GPIOIEN,GPIOIEN" "0,1" bitfld.long 0x28 7. "GPIOHEN,GPIOHEN" "0,1" newline bitfld.long 0x28 6. "GPIOGEN,GPIOGEN" "0,1" bitfld.long 0x28 5. "GPIOFEN,GPIOFEN" "0,1" newline bitfld.long 0x28 4. "GPIOEEN,GPIOEEN" "0,1" bitfld.long 0x28 3. "GPIODEN,GPIODEN" "0,1" newline bitfld.long 0x28 2. "GPIOCEN,GPIOCEN" "0,1" bitfld.long 0x28 1. "GPIOBEN,GPIOBEN" "0,1" newline bitfld.long 0x28 0. "GPIOAEN,GPIOAEN" "0,1" line.long 0x2C "RCC_MP_AHB4ENCLRR,This register is used to clear the peripheral clock enable bit" bitfld.long 0x2C 10. "GPIOKEN,GPIOKEN" "0,1" bitfld.long 0x2C 9. "GPIOJEN,GPIOJEN" "0,1" newline bitfld.long 0x2C 8. "GPIOIEN,GPIOIEN" "0,1" bitfld.long 0x2C 7. "GPIOHEN,GPIOHEN" "0,1" newline bitfld.long 0x2C 6. "GPIOGEN,GPIOGEN" "0,1" bitfld.long 0x2C 5. "GPIOFEN,GPIOFEN" "0,1" newline bitfld.long 0x2C 4. "GPIOEEN,GPIOEEN" "0,1" bitfld.long 0x2C 3. "GPIODEN,GPIODEN" "0,1" newline bitfld.long 0x2C 2. "GPIOCEN,GPIOCEN" "0,1" bitfld.long 0x2C 1. "GPIOBEN,GPIOBEN" "0,1" newline bitfld.long 0x2C 0. "GPIOAEN,GPIOAEN" "0,1" group.long 0xA38++0x7 line.long 0x0 "RCC_MP_MLAHBENSETR,This register is used to set the peripheral clock enable bit" bitfld.long 0x0 4. "RETRAMEN,RETRAMEN" "0,1" line.long 0x4 "RCC_MP_MLAHBENCLRR,This register is used to clear the peripheral clock enable bit." bitfld.long 0x4 4. "RETRAMEN,RETRAMEN" "0,1" group.long 0xA80++0x3F line.long 0x0 "RCC_MC_APB1ENSETR,This register is used to set the peripheral clock enable bit of the corresponding peripheral to . It shall be used to allocate a peripheral to the MCU. Writing has no effect. reading will return . Writing a sets the corresponding bit.." bitfld.long 0x0 31. "MDIOSEN,MDIOSEN" "0,1" bitfld.long 0x0 29. "DAC12EN,DAC12EN" "0,1" newline bitfld.long 0x0 28. "WWDG1EN,WWDG1EN" "0,1" bitfld.long 0x0 27. "CECEN,CECEN" "0,1" newline bitfld.long 0x0 26. "SPDIFEN,SPDIFEN" "0,1" bitfld.long 0x0 24. "I2C5EN,I2C5EN" "0,1" newline bitfld.long 0x0 23. "I2C3EN,I2C3EN" "0,1" bitfld.long 0x0 22. "I2C2EN,I2C2EN" "0,1" newline bitfld.long 0x0 21. "I2C1EN,I2C1EN" "0,1" bitfld.long 0x0 19. "UART8EN,UART8EN" "0,1" newline bitfld.long 0x0 18. "UART7EN,UART7EN" "0,1" bitfld.long 0x0 17. "UART5EN,UART5EN" "0,1" newline bitfld.long 0x0 16. "UART4EN,UART4EN" "0,1" bitfld.long 0x0 15. "USART3EN,USART3EN" "0,1" newline bitfld.long 0x0 14. "USART2EN,USART2EN" "0,1" bitfld.long 0x0 12. "SPI3EN,SPI3EN" "0,1" newline bitfld.long 0x0 11. "SPI2EN,SPI2EN" "0,1" bitfld.long 0x0 9. "LPTIM1EN,LPTIM1EN" "0,1" newline bitfld.long 0x0 8. "TIM14EN,TIM14EN" "0,1" bitfld.long 0x0 7. "TIM13EN,TIM13EN" "0,1" newline bitfld.long 0x0 6. "TIM12EN,TIM12EN" "0,1" bitfld.long 0x0 5. "TIM7EN,TIM7EN" "0,1" newline bitfld.long 0x0 4. "TIM6EN,TIM6EN" "0,1" bitfld.long 0x0 3. "TIM5EN,TIM5EN" "0,1" newline bitfld.long 0x0 2. "TIM4EN,TIM4EN" "0,1" bitfld.long 0x0 1. "TIM3EN,TIM3EN" "0,1" newline bitfld.long 0x0 0. "TIM2EN,TIM2EN" "0,1" line.long 0x4 "RCC_MC_APB1ENCLRR,This register is used to clear the peripheral clock enable bit of the corresponding peripheral." bitfld.long 0x4 31. "MDIOSEN,MDIOSEN" "0,1" bitfld.long 0x4 29. "DAC12EN,DAC12EN" "0,1" newline bitfld.long 0x4 27. "CECEN,CECEN" "0,1" bitfld.long 0x4 26. "SPDIFEN,SPDIFEN" "0,1" newline bitfld.long 0x4 24. "I2C5EN,I2C5EN" "0,1" bitfld.long 0x4 23. "I2C3EN,I2C3EN" "0,1" newline bitfld.long 0x4 22. "I2C2EN,I2C2EN" "0,1" bitfld.long 0x4 21. "I2C1EN,I2C1EN" "0,1" newline bitfld.long 0x4 19. "UART8EN,UART8EN" "0,1" bitfld.long 0x4 18. "UART7EN,UART7EN" "0,1" newline bitfld.long 0x4 17. "UART5EN,UART5EN" "0,1" bitfld.long 0x4 16. "UART4EN,UART4EN" "0,1" newline bitfld.long 0x4 15. "USART3EN,USART3EN" "0,1" bitfld.long 0x4 14. "USART2EN,USART2EN" "0,1" newline bitfld.long 0x4 12. "SPI3EN,SPI3EN" "0,1" bitfld.long 0x4 11. "SPI2EN,SPI2EN" "0,1" newline bitfld.long 0x4 9. "LPTIM1EN,LPTIM1EN" "0,1" bitfld.long 0x4 8. "TIM14EN,TIM14EN" "0,1" newline bitfld.long 0x4 7. "TIM13EN,TIM13EN" "0,1" bitfld.long 0x4 6. "TIM12EN,TIM12EN" "0,1" newline bitfld.long 0x4 5. "TIM7EN,TIM7EN" "0,1" bitfld.long 0x4 4. "TIM6EN,TIM6EN" "0,1" newline bitfld.long 0x4 3. "TIM5EN,TIM5EN" "0,1" bitfld.long 0x4 2. "TIM4EN,TIM4EN" "0,1" newline bitfld.long 0x4 1. "TIM3EN,TIM3EN" "0,1" bitfld.long 0x4 0. "TIM2EN,TIM2EN" "0,1" line.long 0x8 "RCC_MC_APB2ENSETR,This register is used to set the peripheral clock enable bit" bitfld.long 0x8 24. "FDCANEN,FDCANEN" "0,1" bitfld.long 0x8 21. "ADFSDMEN,ADFSDMEN" "0,1" newline bitfld.long 0x8 20. "DFSDMEN,DFSDMEN" "0,1" bitfld.long 0x8 18. "SAI3EN,SAI3EN" "0,1" newline bitfld.long 0x8 17. "SAI2EN,SAI2EN" "0,1" bitfld.long 0x8 16. "SAI1EN,SAI1EN" "0,1" newline bitfld.long 0x8 13. "USART6EN,USART6EN" "0,1" bitfld.long 0x8 10. "SPI5EN,SPI5EN" "0,1" newline bitfld.long 0x8 9. "SPI4EN,SPI4EN" "0,1" bitfld.long 0x8 8. "SPI1EN,SPI1EN" "0,1" newline bitfld.long 0x8 4. "TIM17EN,TIM17EN" "0,1" bitfld.long 0x8 3. "TIM16EN,TIM16EN" "0,1" newline bitfld.long 0x8 2. "TIM15EN,TIM15EN" "0,1" bitfld.long 0x8 1. "TIM8EN,TIM8EN" "0,1" newline bitfld.long 0x8 0. "TIM1EN,TIM1EN" "0,1" line.long 0xC "RCC_MC_APB2ENCLRR,This register is used to clear the peripheral clock enable bit" bitfld.long 0xC 24. "FDCANEN,FDCANEN" "0,1" bitfld.long 0xC 21. "ADFSDMEN,ADFSDMEN" "0,1" newline bitfld.long 0xC 20. "DFSDMEN,DFSDMEN" "0,1" bitfld.long 0xC 18. "SAI3EN,SAI3EN" "0,1" newline bitfld.long 0xC 17. "SAI2EN,SAI2EN" "0,1" bitfld.long 0xC 16. "SAI1EN,SAI1EN" "0,1" newline bitfld.long 0xC 13. "USART6EN,USART6EN" "0,1" bitfld.long 0xC 10. "SPI5EN,SPI5EN" "0,1" newline bitfld.long 0xC 9. "SPI4EN,SPI4EN" "0,1" bitfld.long 0xC 8. "SPI1EN,SPI1EN" "0,1" newline bitfld.long 0xC 4. "TIM17EN,TIM17EN" "0,1" bitfld.long 0xC 3. "TIM16EN,TIM16EN" "0,1" newline bitfld.long 0xC 2. "TIM15EN,TIM15EN" "0,1" bitfld.long 0xC 1. "TIM8EN,TIM8EN" "0,1" newline bitfld.long 0xC 0. "TIM1EN,TIM1EN" "0,1" line.long 0x10 "RCC_MC_APB3ENSETR,This register is used to set the peripheral clock enable bit" bitfld.long 0x10 20. "HDPEN,HDPEN" "0,1" bitfld.long 0x10 16. "DTSEN,DTSEN" "0,1" newline bitfld.long 0x10 13. "VREFEN,VREFEN" "0,1" bitfld.long 0x10 11. "SYSCFGEN,SYSCFGEN" "0,1" newline bitfld.long 0x10 8. "SAI4EN,SAI4EN" "0,1" bitfld.long 0x10 3. "LPTIM5EN,LPTIM5EN" "0,1" newline bitfld.long 0x10 2. "LPTIM4EN,LPTIM4EN" "0,1" bitfld.long 0x10 1. "LPTIM3EN,LPTIM3EN" "0,1" newline bitfld.long 0x10 0. "LPTIM2EN,LPTIM2EN" "0,1" line.long 0x14 "RCC_MC_APB3ENCLRR,This register is used to clear the peripheral clock enable bit" bitfld.long 0x14 20. "HDPEN,HDPEN" "0,1" bitfld.long 0x14 16. "DTSEN,DTSEN" "0,1" newline bitfld.long 0x14 13. "VREFEN,VREFEN" "0,1" bitfld.long 0x14 11. "SYSCFGEN,SYSCFGEN" "0,1" newline bitfld.long 0x14 8. "SAI4EN,SAI4EN" "0,1" bitfld.long 0x14 3. "LPTIM5EN,LPTIM5EN" "0,1" newline bitfld.long 0x14 2. "LPTIM4EN,LPTIM4EN" "0,1" bitfld.long 0x14 1. "LPTIM3EN,LPTIM3EN" "0,1" newline bitfld.long 0x14 0. "LPTIM2EN,LPTIM2EN" "0,1" line.long 0x18 "RCC_MC_AHB2ENSETR,This register is used to set the peripheral clock enable bit" bitfld.long 0x18 16. "SDMMC3EN,SDMMC3EN" "0,1" bitfld.long 0x18 8. "USBOEN,USBOEN" "0,1" newline bitfld.long 0x18 5. "ADC12EN,ADC12EN" "0,1" bitfld.long 0x18 2. "DMAMUXEN,DMAMUXEN" "0,1" newline bitfld.long 0x18 1. "DMA2EN,DMA2EN" "0,1" bitfld.long 0x18 0. "DMA1EN,DMA1EN" "0,1" line.long 0x1C "RCC_MC_AHB2ENCLRR,This register is used to clear the peripheral clock enable bit" bitfld.long 0x1C 16. "SDMMC3EN,SDMMC3EN" "0,1" bitfld.long 0x1C 8. "USBOEN,USBOEN" "0,1" newline bitfld.long 0x1C 5. "ADC12EN,ADC12EN" "0,1" bitfld.long 0x1C 2. "DMAMUXEN,DMAMUXEN" "0,1" newline bitfld.long 0x1C 1. "DMA2EN,DMA2EN" "0,1" bitfld.long 0x1C 0. "DMA1EN,DMA1EN" "0,1" line.long 0x20 "RCC_MC_AHB3ENSETR,This register is used to set the peripheral clock enable bit" bitfld.long 0x20 12. "IPCCEN,IPCCEN" "0,1" bitfld.long 0x20 11. "HSEMEN,HSEMEN" "0,1" newline bitfld.long 0x20 7. "CRC2EN,CRC2EN" "0,1" bitfld.long 0x20 6. "RNG2EN,RNG2EN" "0,1" newline bitfld.long 0x20 5. "HASH2EN,HASH2EN" "0,1" bitfld.long 0x20 4. "CRYP2EN,CRYP2EN" "0,1" newline bitfld.long 0x20 0. "DCMIEN,DCMIEN" "0,1" line.long 0x24 "RCC_MC_AHB3ENCLRR,This register is used to clear the peripheral clock enable bit" bitfld.long 0x24 12. "IPCCEN,IPCCEN" "0,1" bitfld.long 0x24 11. "HSEMEN,HSEMEN" "0,1" newline bitfld.long 0x24 7. "CRC2EN,CRC2EN" "0,1" bitfld.long 0x24 6. "RNG2EN,RNG2EN" "0,1" newline bitfld.long 0x24 5. "HASH2EN,HASH2EN" "0,1" bitfld.long 0x24 4. "CRYP2EN,CRYP2EN" "0,1" newline bitfld.long 0x24 0. "DCMIEN,DCMIEN" "0,1" line.long 0x28 "RCC_MC_AHB4ENSETR,This register is used to set the peripheral clock enable bit" bitfld.long 0x28 10. "GPIOKEN,GPIOKEN" "0,1" bitfld.long 0x28 9. "GPIOJEN,GPIOJEN" "0,1" newline bitfld.long 0x28 8. "GPIOIEN,GPIOIEN" "0,1" bitfld.long 0x28 7. "GPIOHEN,GPIOHEN" "0,1" newline bitfld.long 0x28 6. "GPIOGEN,GPIOGEN" "0,1" bitfld.long 0x28 5. "GPIOFEN,GPIOFEN" "0,1" newline bitfld.long 0x28 4. "GPIOEEN,GPIOEEN" "0,1" bitfld.long 0x28 3. "GPIODEN,GPIODEN" "0,1" newline bitfld.long 0x28 2. "GPIOCEN,GPIOCEN" "0,1" bitfld.long 0x28 1. "GPIOBEN,GPIOBEN" "0,1" newline bitfld.long 0x28 0. "GPIOAEN,GPIOAEN" "0,1" line.long 0x2C "RCC_MC_AHB4ENCLRR,This register is used to clear the peripheral clock enable bit" bitfld.long 0x2C 10. "GPIOKEN,GPIOKEN" "0,1" bitfld.long 0x2C 9. "GPIOJEN,GPIOJEN" "0,1" newline bitfld.long 0x2C 8. "GPIOIEN,GPIOIEN" "0,1" bitfld.long 0x2C 7. "GPIOHEN,GPIOHEN" "0,1" newline bitfld.long 0x2C 6. "GPIOGEN,GPIOGEN" "0,1" bitfld.long 0x2C 5. "GPIOFEN,GPIOFEN" "0,1" newline bitfld.long 0x2C 4. "GPIOEEN,GPIOEEN" "0,1" bitfld.long 0x2C 3. "GPIODEN,GPIODEN" "0,1" newline bitfld.long 0x2C 2. "GPIOCEN,GPIOCEN" "0,1" bitfld.long 0x2C 1. "GPIOBEN,GPIOBEN" "0,1" newline bitfld.long 0x2C 0. "GPIOAEN,GPIOAEN" "0,1" line.long 0x30 "RCC_MC_AXIMENSETR,This register is used to set the peripheral clock enable bit" bitfld.long 0x30 0. "SYSRAMEN,SYSRAMEN" "0,1" line.long 0x34 "RCC_MC_AXIMENCLRR,This register is used to clear the peripheral clock enable bit" bitfld.long 0x34 0. "SYSRAMEN,SYSRAMEN" "0,1" line.long 0x38 "RCC_MC_MLAHBENSETR,This register is used to set the peripheral clock enable bit" bitfld.long 0x38 4. "RETRAMEN,RETRAMEN" "0,1" line.long 0x3C "RCC_MC_MLAHBENCLRR,This register is used to clear the peripheral clock enable bit" bitfld.long 0x3C 4. "RETRAMEN,RETRAMEN" "0,1" group.long 0xB00++0x3F line.long 0x0 "RCC_MP_APB1LPENSETR,This register is used by the MCU in order to clear the PERxLPEN bits" bitfld.long 0x0 31. "MDIOSLPEN,MDIOSLPEN" "0,1" bitfld.long 0x0 29. "DAC12LPEN,DAC12LPEN" "0,1" newline bitfld.long 0x0 27. "CECLPEN,CECLPEN" "0,1" bitfld.long 0x0 26. "SPDIFLPEN,SPDIFLPEN" "0,1" newline bitfld.long 0x0 24. "I2C5LPEN,I2C5LPEN" "0,1" bitfld.long 0x0 23. "I2C3LPEN,I2C3LPEN" "0,1" newline bitfld.long 0x0 22. "I2C2LPEN,I2C2LPEN" "0,1" bitfld.long 0x0 21. "I2C1LPEN,I2C1LPEN" "0,1" newline bitfld.long 0x0 19. "UART8LPEN,UART8LPEN" "0,1" bitfld.long 0x0 18. "UART7LPEN,UART7LPEN" "0,1" newline bitfld.long 0x0 17. "UART5LPEN,UART5LPEN" "0,1" bitfld.long 0x0 16. "UART4LPEN,UART4LPEN" "0,1" newline bitfld.long 0x0 15. "USART3LPEN,USART3LPEN" "0,1" bitfld.long 0x0 14. "USART2LPEN,USART2LPEN" "0,1" newline bitfld.long 0x0 12. "SPI3LPEN,SPI3LPEN" "0,1" bitfld.long 0x0 11. "SPI2LPEN,SPI2LPEN" "0,1" newline bitfld.long 0x0 9. "LPTIM1LPEN,LPTIM1LPEN" "0,1" bitfld.long 0x0 8. "TIM14LPEN,TIM14LPEN" "0,1" newline bitfld.long 0x0 7. "TIM13LPEN,TIM13LPEN" "0,1" bitfld.long 0x0 6. "TIM12LPEN,TIM12LPEN" "0,1" newline bitfld.long 0x0 5. "TIM7LPEN,TIM7LPEN" "0,1" bitfld.long 0x0 4. "TIM6LPEN,TIM6LPEN" "0,1" newline bitfld.long 0x0 3. "TIM5LPEN,TIM5LPEN" "0,1" bitfld.long 0x0 2. "TIM4LPEN,TIM4LPEN" "0,1" newline bitfld.long 0x0 1. "TIM3LPEN,TIM3LPEN" "0,1" bitfld.long 0x0 0. "TIM2LPEN,TIM2LPEN" "0,1" line.long 0x4 "RCC_MP_APB1LPENCLRR,This register is used by the MPU in order to clear the PERxLPEN bits ." bitfld.long 0x4 31. "MDIOSLPEN,MDIOSLPEN" "0,1" bitfld.long 0x4 29. "DAC12LPEN,DAC12LPEN" "0,1" newline bitfld.long 0x4 27. "CECLPEN,CECLPEN" "0,1" bitfld.long 0x4 26. "SPDIFLPEN,SPDIFLPEN" "0,1" newline bitfld.long 0x4 24. "I2C5LPEN,I2C5LPEN" "0,1" bitfld.long 0x4 23. "I2C3LPEN,I2C3LPEN" "0,1" newline bitfld.long 0x4 22. "I2C2LPEN,I2C2LPEN" "0,1" bitfld.long 0x4 21. "I2C1LPEN,I2C1LPEN" "0,1" newline bitfld.long 0x4 19. "UART8LPEN,UART8LPEN" "0,1" bitfld.long 0x4 18. "UART7LPEN,UART7LPEN" "0,1" newline bitfld.long 0x4 17. "UART5LPEN,UART5LPEN" "0,1" bitfld.long 0x4 16. "UART4LPEN,UART4LPEN" "0,1" newline bitfld.long 0x4 15. "USART3LPEN,USART3LPEN" "0,1" bitfld.long 0x4 14. "USART2LPEN,USART2LPEN" "0,1" newline bitfld.long 0x4 12. "SPI3LPEN,SPI3LPEN" "0,1" bitfld.long 0x4 11. "SPI2LPEN,SPI2LPEN" "0,1" newline bitfld.long 0x4 9. "LPTIM1LPEN,LPTIM1LPEN" "0,1" bitfld.long 0x4 8. "TIM14LPEN,TIM14LPEN" "0,1" newline bitfld.long 0x4 7. "TIM13LPEN,TIM13LPEN" "0,1" bitfld.long 0x4 6. "TIM12LPEN,TIM12LPEN" "0,1" newline bitfld.long 0x4 5. "TIM7LPEN,TIM7LPEN" "0,1" bitfld.long 0x4 4. "TIM6LPEN,TIM6LPEN" "0,1" newline bitfld.long 0x4 3. "TIM5LPEN,TIM5LPEN" "0,1" bitfld.long 0x4 2. "TIM4LPEN,TIM4LPEN" "0,1" newline bitfld.long 0x4 1. "TIM3LPEN,TIM3LPEN" "0,1" bitfld.long 0x4 0. "TIM2LPEN,TIM2LPEN" "0,1" line.long 0x8 "RCC_MP_APB2LPENSETR,This register is used by the MCU in order to clear the PERxLPEN bits" bitfld.long 0x8 24. "FDCANLPEN,FDCANLPEN" "0,1" bitfld.long 0x8 21. "ADFSDMLPEN,ADFSDMLPEN" "0,1" newline bitfld.long 0x8 20. "DFSDMLPEN,DFSDMLPEN" "0,1" bitfld.long 0x8 18. "SAI3LPEN,SAI3LPEN" "0,1" newline bitfld.long 0x8 17. "SAI2LPEN,SAI2LPEN" "0,1" bitfld.long 0x8 16. "SAI1LPEN,SAI1LPEN" "0,1" newline bitfld.long 0x8 13. "USART6LPEN,USART6LPEN" "0,1" bitfld.long 0x8 10. "SPI5LPEN,SPI5LPEN" "0,1" newline bitfld.long 0x8 9. "SPI4LPEN,SPI4LPEN" "0,1" bitfld.long 0x8 8. "SPI1LPEN,SPI1LPEN" "0,1" newline bitfld.long 0x8 4. "TIM17LPEN,TIM17LPEN" "0,1" bitfld.long 0x8 3. "TIM16LPEN,TIM16LPEN" "0,1" newline bitfld.long 0x8 2. "TIM15LPEN,TIM15LPEN" "0,1" bitfld.long 0x8 1. "TIM8LPEN,TIM8LPEN" "0,1" newline bitfld.long 0x8 0. "TIM1LPEN,TIM1LPEN" "0,1" line.long 0xC "RCC_MP_APB2LPENCLRR,This register is used by the MCU in order to clear the PERxLPEN bits" bitfld.long 0xC 24. "FDCANLPEN,FDCANLPEN" "0,1" bitfld.long 0xC 21. "ADFSDMLPEN,ADFSDMLPEN" "0,1" newline bitfld.long 0xC 20. "DFSDMLPEN,DFSDMLPEN" "0,1" bitfld.long 0xC 18. "SAI3LPEN,SAI3LPEN" "0,1" newline bitfld.long 0xC 17. "SAI2LPEN,SAI2LPEN" "0,1" bitfld.long 0xC 16. "SAI1LPEN,SAI1LPEN" "0,1" newline bitfld.long 0xC 13. "USART6LPEN,USART6LPEN" "0,1" bitfld.long 0xC 10. "SPI5LPEN,SPI5LPEN" "0,1" newline bitfld.long 0xC 9. "SPI4LPEN,SPI4LPEN" "0,1" bitfld.long 0xC 8. "SPI1LPEN,SPI1LPEN" "0,1" newline bitfld.long 0xC 4. "TIM17LPEN,TIM17LPEN" "0,1" bitfld.long 0xC 3. "TIM16LPEN,TIM16LPEN" "0,1" newline bitfld.long 0xC 2. "TIM15LPEN,TIM15LPEN" "0,1" bitfld.long 0xC 1. "TIM8LPEN,TIM8LPEN" "0,1" newline bitfld.long 0xC 0. "TIM1LPEN,TIM1LPEN" "0,1" line.long 0x10 "RCC_MP_APB3LPENSETR,This register is used by the MCU in order to clear the PERxLPEN bits" bitfld.long 0x10 16. "DTSLPEN,DTSLPEN" "0,1" bitfld.long 0x10 13. "VREFLPEN,VREFLPEN" "0,1" newline bitfld.long 0x10 11. "SYSCFGLPEN,SYSCFGLPEN" "0,1" bitfld.long 0x10 8. "SAI4LPEN,SAI4LPEN" "0,1" newline bitfld.long 0x10 3. "LPTIM5LPEN,LPTIM5LPEN" "0,1" bitfld.long 0x10 2. "LPTIM4LPEN,LPTIM4LPEN" "0,1" newline bitfld.long 0x10 1. "LPTIM3LPEN,LPTIM3LPEN" "0,1" bitfld.long 0x10 0. "LPTIM2LPEN,LPTIM2LPEN" "0,1" line.long 0x14 "RCC_MP_APB3LPENCLRR,This register is used by the MCU in order to clear the PERxLPEN bits" bitfld.long 0x14 16. "DTSLPEN,DTSLPEN" "0,1" bitfld.long 0x14 13. "VREFLPEN,VREFLPEN" "0,1" newline bitfld.long 0x14 11. "SYSCFGLPEN,SYSCFGLPEN" "0,1" bitfld.long 0x14 8. "SAI4LPEN,SAI4LPEN" "0,1" newline bitfld.long 0x14 3. "LPTIM5LPEN,LPTIM5LPEN" "0,1" bitfld.long 0x14 2. "LPTIM4LPEN,LPTIM4LPEN" "0,1" newline bitfld.long 0x14 1. "LPTIM3LPEN,LPTIM3LPEN" "0,1" bitfld.long 0x14 0. "LPTIM2LPEN,LPTIM2LPEN" "0,1" line.long 0x18 "RCC_MP_AHB2LPENSETR,This register is used by the MPU in order to set the PERxLPEN bit." bitfld.long 0x18 16. "SDMMC3LPEN,SDMMC3LPEN" "0,1" bitfld.long 0x18 8. "USBOLPEN,USBOLPEN" "0,1" newline bitfld.long 0x18 5. "ADC12LPEN,ADC12LPEN" "0,1" bitfld.long 0x18 2. "DMAMUXLPEN,DMAMUXLPEN" "0,1" newline bitfld.long 0x18 1. "DMA2LPEN,DMA2LPEN" "0,1" bitfld.long 0x18 0. "DMA1LPEN,DMA1LPEN" "0,1" line.long 0x1C "RCC_MP_AHB2LPENCLRR,This register is used by the MCU in order to clear the PERxLPEN bits" bitfld.long 0x1C 16. "SDMMC3LPEN,SDMMC3LPEN" "0,1" bitfld.long 0x1C 8. "USBOLPEN,USBOLPEN" "0,1" newline bitfld.long 0x1C 5. "ADC12LPEN,ADC12LPEN" "0,1" bitfld.long 0x1C 2. "DMAMUXLPEN,DMAMUXLPEN" "0,1" newline bitfld.long 0x1C 1. "DMA2LPEN,DMA2LPEN" "0,1" bitfld.long 0x1C 0. "DMA1LPEN,DMA1LPEN" "0,1" line.long 0x20 "RCC_MP_AHB3LPENSETR,This register is used by the MPU" bitfld.long 0x20 12. "IPCCLPEN,IPCCLPEN" "0,1" bitfld.long 0x20 11. "HSEMLPEN,HSEMLPEN" "0,1" newline bitfld.long 0x20 7. "CRC2LPEN,CRC2LPEN" "0,1" bitfld.long 0x20 6. "RNG2LPEN,RNG2LPEN" "0,1" newline bitfld.long 0x20 5. "HASH2LPEN,HASH2LPEN" "0,1" bitfld.long 0x20 4. "CRYP2LPEN,CRYP2LPEN" "0,1" newline bitfld.long 0x20 0. "DCMILPEN,DCMILPEN" "0,1" line.long 0x24 "RCC_MP_AHB3LPENCLRR,This register is used by the MPU in order to clear the PERxLPEN bit" bitfld.long 0x24 12. "IPCCLPEN,IPCCLPEN" "0,1" bitfld.long 0x24 11. "HSEMLPEN,HSEMLPEN" "0,1" newline bitfld.long 0x24 7. "CRC2LPEN,CRC2LPEN" "0,1" bitfld.long 0x24 6. "RNG2LPEN,RNG2LPEN" "0,1" newline bitfld.long 0x24 5. "HASH2LPEN,HASH2LPEN" "0,1" bitfld.long 0x24 4. "CRYP2LPEN,CRYP2LPEN" "0,1" newline bitfld.long 0x24 0. "DCMILPEN,DCMILPEN" "0,1" line.long 0x28 "RCC_MP_AHB4LPENSETR,This register is used by the MPU" bitfld.long 0x28 10. "GPIOKLPEN,GPIOKLPEN" "0,1" bitfld.long 0x28 9. "GPIOJLPEN,GPIOJLPEN" "0,1" newline bitfld.long 0x28 8. "GPIOILPEN,GPIOILPEN" "0,1" bitfld.long 0x28 7. "GPIOHLPEN,GPIOHLPEN" "0,1" newline bitfld.long 0x28 6. "GPIOGLPEN,GPIOGLPEN" "0,1" bitfld.long 0x28 5. "GPIOFLPEN,GPIOFLPEN" "0,1" newline bitfld.long 0x28 4. "GPIOELPEN,GPIOELPEN" "0,1" bitfld.long 0x28 3. "GPIODLPEN,GPIODLPEN" "0,1" newline bitfld.long 0x28 2. "GPIOCLPEN,GPIOCLPEN" "0,1" bitfld.long 0x28 1. "GPIOBLPEN,GPIOBLPEN" "0,1" newline bitfld.long 0x28 0. "GPIOALPEN,GPIOALPEN" "0,1" line.long 0x2C "RCC_MP_AHB4LPENCLRR,This register is used by the MPU" bitfld.long 0x2C 10. "GPIOKLPEN,GPIOKLPEN" "0,1" bitfld.long 0x2C 9. "GPIOJLPEN,GPIOJLPEN" "0,1" newline bitfld.long 0x2C 8. "GPIOILPEN,GPIOILPEN" "0,1" bitfld.long 0x2C 7. "GPIOHLPEN,GPIOHLPEN" "0,1" newline bitfld.long 0x2C 6. "GPIOGLPEN,GPIOGLPEN" "0,1" bitfld.long 0x2C 5. "GPIOFLPEN,GPIOFLPEN" "0,1" newline bitfld.long 0x2C 4. "GPIOELPEN,GPIOELPEN" "0,1" bitfld.long 0x2C 3. "GPIODLPEN,GPIODLPEN" "0,1" newline bitfld.long 0x2C 2. "GPIOCLPEN,GPIOCLPEN" "0,1" bitfld.long 0x2C 1. "GPIOBLPEN,GPIOBLPEN" "0,1" newline bitfld.long 0x2C 0. "GPIOALPEN,GPIOALPEN" "0,1" line.long 0x30 "RCC_MP_AXIMLPENSETR,This register is used by the MPU" bitfld.long 0x30 0. "SYSRAMLPEN,SYSRAMLPEN" "0,1" line.long 0x34 "RCC_MP_AXIMLPENCLRR,This register is used by the MPU" bitfld.long 0x34 0. "SYSRAMLPEN,SYSRAMLPEN" "0,1" line.long 0x38 "RCC_MP_MLAHBLPENSETR,This register is used by the MPU in order to set the PERxLPEN bit" bitfld.long 0x38 4. "RETRAMLPEN,RETRAMLPEN" "0,1" bitfld.long 0x38 2. "SRAM34LPEN,SRAM34LPEN" "0,1" newline bitfld.long 0x38 1. "SRAM2LPEN,SRAM2LPEN" "0,1" bitfld.long 0x38 0. "SRAM1LPEN,SRAM1LPEN" "0,1" line.long 0x3C "RCC_MP_MLAHBLPENCLRR,This register is used by the MPU in order to clear the PERxLPEN bit" bitfld.long 0x3C 4. "RETRAMLPEN,RETRAMLPEN" "0,1" bitfld.long 0x3C 2. "SRAM34LPEN,SRAM34LPEN" "0,1" newline bitfld.long 0x3C 1. "SRAM2LPEN,SRAM2LPEN" "0,1" bitfld.long 0x3C 0. "SRAM1LPEN,SRAM1LPEN" "0,1" group.long 0xB80++0x3F line.long 0x0 "RCC_MC_APB1LPENSETR,This register is used by the MCU in order to set the PERxLPEN bit." bitfld.long 0x0 31. "MDIOSLPEN,MDIOSLPEN" "0,1" bitfld.long 0x0 29. "DAC12LPEN,DAC12LPEN" "0,1" newline bitfld.long 0x0 28. "WWDG1LPEN,WWDG1LPEN" "0,1" bitfld.long 0x0 27. "CECLPEN,CECLPEN" "0,1" newline bitfld.long 0x0 26. "SPDIFLPEN,SPDIFLPEN" "0,1" bitfld.long 0x0 24. "I2C5LPEN,I2C5LPEN" "0,1" newline bitfld.long 0x0 23. "I2C3LPEN,I2C3LPEN" "0,1" bitfld.long 0x0 22. "I2C2LPEN,I2C2LPEN" "0,1" newline bitfld.long 0x0 21. "I2C1LPEN,I2C1LPEN" "0,1" bitfld.long 0x0 19. "UART8LPEN,UART8LPEN" "0,1" newline bitfld.long 0x0 18. "UART7LPEN,UART7LPEN" "0,1" bitfld.long 0x0 17. "UART5LPEN,UART5LPEN" "0,1" newline bitfld.long 0x0 16. "UART4LPEN,UART4LPEN" "0,1" bitfld.long 0x0 15. "USART3LPEN,USART3LPEN" "0,1" newline bitfld.long 0x0 14. "USART2LPEN,USART2LPEN" "0,1" bitfld.long 0x0 12. "SPI3LPEN,SPI3LPEN" "0,1" newline bitfld.long 0x0 11. "SPI2LPEN,SPI2LPEN" "0,1" bitfld.long 0x0 9. "LPTIM1LPEN,LPTIM1LPEN" "0,1" newline bitfld.long 0x0 8. "TIM14LPEN,TIM14LPEN" "0,1" bitfld.long 0x0 7. "TIM13LPEN,TIM13LPEN" "0,1" newline bitfld.long 0x0 6. "TIM12LPEN,TIM12LPEN" "0,1" bitfld.long 0x0 5. "TIM7LPEN,TIM7LPEN" "0,1" newline bitfld.long 0x0 4. "TIM6LPEN,TIM6LPEN" "0,1" bitfld.long 0x0 3. "TIM5LPEN,TIM5LPEN" "0,1" newline bitfld.long 0x0 2. "TIM4LPEN,TIM4LPEN" "0,1" bitfld.long 0x0 1. "TIM3LPEN,TIM3LPEN" "0,1" newline bitfld.long 0x0 0. "TIM2LPEN,TIM2LPEN" "0,1" line.long 0x4 "RCC_MC_APB1LPENCLRR,This register is used by the MCU in order to clear the PERxLPEN bits" bitfld.long 0x4 31. "MDIOSLPEN,MDIOSLPEN" "0,1" bitfld.long 0x4 29. "DAC12LPEN,DAC12LPEN" "0,1" newline bitfld.long 0x4 28. "WWDG1LPEN,WWDG1LPEN" "0,1" bitfld.long 0x4 27. "CECLPEN,CECLPEN" "0,1" newline bitfld.long 0x4 26. "SPDIFLPEN,SPDIFLPEN" "0,1" bitfld.long 0x4 24. "I2C5LPEN,I2C5LPEN" "0,1" newline bitfld.long 0x4 23. "I2C3LPEN,I2C3LPEN" "0,1" bitfld.long 0x4 22. "I2C2LPEN,I2C2LPEN" "0,1" newline bitfld.long 0x4 21. "I2C1LPEN,I2C1LPEN" "0,1" bitfld.long 0x4 19. "UART8LPEN,UART8LPEN" "0,1" newline bitfld.long 0x4 18. "UART7LPEN,UART7LPEN" "0,1" bitfld.long 0x4 17. "UART5LPEN,UART5LPEN" "0,1" newline bitfld.long 0x4 16. "UART4LPEN,UART4LPEN" "0,1" bitfld.long 0x4 15. "USART3LPEN,USART3LPEN" "0,1" newline bitfld.long 0x4 14. "USART2LPEN,USART2LPEN" "0,1" bitfld.long 0x4 12. "SPI3LPEN,SPI3LPEN" "0,1" newline bitfld.long 0x4 11. "SPI2LPEN,SPI2LPEN" "0,1" bitfld.long 0x4 9. "LPTIM1LPEN,LPTIM1LPEN" "0,1" newline bitfld.long 0x4 8. "TIM14LPEN,TIM14LPEN" "0,1" bitfld.long 0x4 7. "TIM13LPEN,TIM13LPEN" "0,1" newline bitfld.long 0x4 6. "TIM12LPEN,TIM12LPEN" "0,1" bitfld.long 0x4 5. "TIM7LPEN,TIM7LPEN" "0,1" newline bitfld.long 0x4 4. "TIM6LPEN,TIM6LPEN" "0,1" bitfld.long 0x4 3. "TIM5LPEN,TIM5LPEN" "0,1" newline bitfld.long 0x4 2. "TIM4LPEN,TIM4LPEN" "0,1" bitfld.long 0x4 1. "TIM3LPEN,TIM3LPEN" "0,1" newline bitfld.long 0x4 0. "TIM2LPEN,TIM2LPEN" "0,1" line.long 0x8 "RCC_MC_APB2LPENSETR,This register is used by the MCU in order to set the PERxLPEN bit." bitfld.long 0x8 24. "FDCANLPEN,FDCANLPEN" "0,1" bitfld.long 0x8 21. "ADFSDMLPEN,ADFSDMLPEN" "0,1" newline bitfld.long 0x8 20. "DFSDMLPEN,DFSDMLPEN" "0,1" bitfld.long 0x8 18. "SAI3LPEN,SAI3LPEN" "0,1" newline bitfld.long 0x8 17. "SAI2LPEN,SAI2LPEN" "0,1" bitfld.long 0x8 16. "SAI1LPEN,SAI1LPEN" "0,1" newline bitfld.long 0x8 13. "USART6LPEN,USART6LPEN" "0,1" bitfld.long 0x8 10. "SPI5LPEN,SPI5LPEN" "0,1" newline bitfld.long 0x8 9. "SPI4LPEN,SPI4LPEN" "0,1" bitfld.long 0x8 8. "SPI1LPEN,SPI1LPEN" "0,1" newline bitfld.long 0x8 4. "TIM17LPEN,TIM17LPEN" "0,1" bitfld.long 0x8 3. "TIM16LPEN,TIM16LPEN" "0,1" newline bitfld.long 0x8 2. "TIM15LPEN,TIM15LPEN" "0,1" bitfld.long 0x8 1. "TIM8LPEN,TIM8LPEN" "0,1" newline bitfld.long 0x8 0. "TIM1LPEN,TIM1LPEN" "0,1" line.long 0xC "RCC_MC_APB2LPENCLRR,This register is used by the MCU in order to clear the PERxLPEN bit" bitfld.long 0xC 24. "FDCANLPEN,FDCANLPEN" "0,1" bitfld.long 0xC 21. "ADFSDMLPEN,ADFSDMLPEN" "0,1" newline bitfld.long 0xC 20. "DFSDMLPEN,DFSDMLPEN" "0,1" bitfld.long 0xC 18. "SAI3LPEN,SAI3LPEN" "0,1" newline bitfld.long 0xC 17. "SAI2LPEN,SAI2LPEN" "0,1" bitfld.long 0xC 16. "SAI1LPEN,SAI1LPEN" "0,1" newline bitfld.long 0xC 13. "USART6LPEN,USART6LPEN" "0,1" bitfld.long 0xC 10. "SPI5LPEN,SPI5LPEN" "0,1" newline bitfld.long 0xC 9. "SPI4LPEN,SPI4LPEN" "0,1" bitfld.long 0xC 8. "SPI1LPEN,SPI1LPEN" "0,1" newline bitfld.long 0xC 4. "TIM17LPEN,TIM17LPEN" "0,1" bitfld.long 0xC 3. "TIM16LPEN,TIM16LPEN" "0,1" newline bitfld.long 0xC 2. "TIM15LPEN,TIM15LPEN" "0,1" bitfld.long 0xC 1. "TIM8LPEN,TIM8LPEN" "0,1" newline bitfld.long 0xC 0. "TIM1LPEN,TIM1LPEN" "0,1" line.long 0x10 "RCC_MC_APB3LPENSETR,This register is used by the MCU in order to set the PERxLPEN bit." bitfld.long 0x10 16. "DTSLPEN,DTSLPEN" "0,1" bitfld.long 0x10 13. "VREFLPEN,VREFLPEN" "0,1" newline bitfld.long 0x10 11. "SYSCFGLPEN,SYSCFGLPEN" "0,1" bitfld.long 0x10 8. "SAI4LPEN,SAI4LPEN" "0,1" newline bitfld.long 0x10 3. "LPTIM5LPEN,LPTIM5LPEN" "0,1" bitfld.long 0x10 2. "LPTIM4LPEN,LPTIM4LPEN" "0,1" newline bitfld.long 0x10 1. "LPTIM3LPEN,LPTIM3LPEN" "0,1" bitfld.long 0x10 0. "LPTIM2LPEN,LPTIM2LPEN" "0,1" line.long 0x14 "RCC_MC_APB3LPENCLRR,This register is used by the MCU in order to clear the PERxLPEN bit" bitfld.long 0x14 16. "DTSLPEN,DTSLPEN" "0,1" bitfld.long 0x14 13. "VREFLPEN,VREFLPEN" "0,1" newline bitfld.long 0x14 11. "SYSCFGLPEN,SYSCFGLPEN" "0,1" bitfld.long 0x14 8. "SAI4LPEN,SAI4LPEN" "0,1" newline bitfld.long 0x14 3. "LPTIM5LPEN,LPTIM5LPEN" "0,1" bitfld.long 0x14 2. "LPTIM4LPEN,LPTIM4LPEN" "0,1" newline bitfld.long 0x14 1. "LPTIM3LPEN,LPTIM3LPEN" "0,1" bitfld.long 0x14 0. "LPTIM2LPEN,LPTIM2LPEN" "0,1" line.long 0x18 "RCC_MC_AHB2LPENSETR,This register is used by the MCU in order to set the PERxLPEN bit." bitfld.long 0x18 16. "SDMMC3LPEN,SDMMC3LPEN" "0,1" bitfld.long 0x18 8. "USBOLPEN,USBOLPEN" "0,1" newline bitfld.long 0x18 5. "ADC12LPEN,ADC12LPEN" "0,1" bitfld.long 0x18 2. "DMAMUXLPEN,DMAMUXLPEN" "0,1" newline bitfld.long 0x18 1. "DMA2LPEN,DMA2LPEN" "0,1" bitfld.long 0x18 0. "DMA1LPEN,DMA1LPEN" "0,1" line.long 0x1C "RCC_MC_AHB2LPENCLRR,This register is used by the MCU in order to clear the PERxLPEN bit" bitfld.long 0x1C 16. "SDMMC3LPEN,SDMMC3LPEN" "0,1" bitfld.long 0x1C 8. "USBOLPEN,USBOLPEN" "0,1" newline bitfld.long 0x1C 5. "ADC12LPEN,ADC12LPEN" "0,1" bitfld.long 0x1C 2. "DMAMUXLPEN,DMAMUXLPEN" "0,1" newline bitfld.long 0x1C 1. "DMA2LPEN,DMA2LPEN" "0,1" bitfld.long 0x1C 0. "DMA1LPEN,DMA1LPEN" "0,1" line.long 0x20 "RCC_MC_AHB3LPENSETR,This register is used by the MCU in order to set the PERxLPEN bit." bitfld.long 0x20 12. "IPCCLPEN,IPCCLPEN" "0,1" bitfld.long 0x20 11. "HSEMLPEN,HSEMLPEN" "0,1" newline bitfld.long 0x20 7. "CRC2LPEN,CRC2LPEN" "0,1" bitfld.long 0x20 6. "RNG2LPEN,RNG2LPEN" "0,1" newline bitfld.long 0x20 5. "HASH2LPEN,HASH2LPEN" "0,1" bitfld.long 0x20 4. "CRYP2LPEN,CRYP2LPEN" "0,1" newline bitfld.long 0x20 0. "DCMILPEN,DCMILPEN" "0,1" line.long 0x24 "RCC_MC_AHB3LPENCLRR,This register is used by the MCU in order to clear the PERxLPEN bit" bitfld.long 0x24 12. "IPCCLPEN,IPCCLPEN" "0,1" bitfld.long 0x24 11. "HSEMLPEN,HSEMLPEN" "0,1" newline bitfld.long 0x24 7. "CRC2LPEN,CRC2LPEN" "0,1" bitfld.long 0x24 6. "RNG2LPEN,RNG2LPEN" "0,1" newline bitfld.long 0x24 5. "HASH2LPEN,HASH2LPEN" "0,1" bitfld.long 0x24 4. "CRYP2LPEN,CRYP2LPEN" "0,1" newline bitfld.long 0x24 0. "DCMILPEN,DCMILPEN" "0,1" line.long 0x28 "RCC_MC_AHB4LPENSETR,This register is used by the MCU in order to set the PERxLPEN bit." bitfld.long 0x28 10. "GPIOKLPEN,GPIOKLPEN" "0,1" bitfld.long 0x28 9. "GPIOJLPEN,GPIOJLPEN" "0,1" newline bitfld.long 0x28 8. "GPIOILPEN,GPIOILPEN" "0,1" bitfld.long 0x28 7. "GPIOHLPEN,GPIOHLPEN" "0,1" newline bitfld.long 0x28 6. "GPIOGLPEN,GPIOGLPEN" "0,1" bitfld.long 0x28 5. "GPIOFLPEN,GPIOFLPEN" "0,1" newline bitfld.long 0x28 4. "GPIOELPEN,GPIOELPEN" "0,1" bitfld.long 0x28 3. "GPIODLPEN,GPIODLPEN" "0,1" newline bitfld.long 0x28 2. "GPIOCLPEN,GPIOCLPEN" "0,1" bitfld.long 0x28 1. "GPIOBLPEN,GPIOBLPEN" "0,1" newline bitfld.long 0x28 0. "GPIOALPEN,GPIOALPEN" "0,1" line.long 0x2C "RCC_MC_AHB4LPENCLRR,This register is used by the MCU in order to clear the PERxLPEN bit of the corresponding peripheral." bitfld.long 0x2C 10. "GPIOKLPEN,GPIOKLPEN" "0,1" bitfld.long 0x2C 9. "GPIOJLPEN,GPIOJLPEN" "0,1" newline bitfld.long 0x2C 8. "GPIOILPEN,GPIOILPEN" "0,1" bitfld.long 0x2C 7. "GPIOHLPEN,GPIOHLPEN" "0,1" newline bitfld.long 0x2C 6. "GPIOGLPEN,GPIOGLPEN" "0,1" bitfld.long 0x2C 5. "GPIOFLPEN,GPIOFLPEN" "0,1" newline bitfld.long 0x2C 4. "GPIOELPEN,GPIOELPEN" "0,1" bitfld.long 0x2C 3. "GPIODLPEN,GPIODLPEN" "0,1" newline bitfld.long 0x2C 2. "GPIOCLPEN,GPIOCLPEN" "0,1" bitfld.long 0x2C 1. "GPIOBLPEN,GPIOBLPEN" "0,1" newline bitfld.long 0x2C 0. "GPIOALPEN,GPIOALPEN" "0,1" line.long 0x30 "RCC_MC_AXIMLPENSETR,This register is used by the MCU in order to set the PERxLPEN bit of the corresponding peripheral." bitfld.long 0x30 0. "SYSRAMLPEN,SYSRAMLPEN" "0,1" line.long 0x34 "RCC_MC_AXIMLPENCLRR,This register is used by the MCU in order to clear the PERxLPEN bit of the corresponding peripheral." bitfld.long 0x34 0. "SYSRAMLPEN,SYSRAMLPEN" "0,1" line.long 0x38 "RCC_MC_MLAHBLPENSETR,This register is used by the MCU in order to set the PERxLPEN bit of the corresponding peripheral." bitfld.long 0x38 4. "RETRAMLPEN,RETRAMLPEN" "0,1" bitfld.long 0x38 2. "SRAM34LPEN,SRAM34LPEN" "0,1" newline bitfld.long 0x38 1. "SRAM2LPEN,SRAM2LPEN" "0,1" bitfld.long 0x38 0. "SRAM1LPEN,SRAM1LPEN" "0,1" line.long 0x3C "RCC_MC_MLAHBLPENCLRR,This register is used by the MCU in order to clear the PERxLPEN bit of the corresponding peripheral." bitfld.long 0x3C 4. "RETRAMLPEN,RETRAMLPEN" "0,1" bitfld.long 0x3C 2. "SRAM34LPEN,SRAM34LPEN" "0,1" newline bitfld.long 0x3C 1. "SRAM2LPEN,SRAM2LPEN" "0,1" bitfld.long 0x3C 0. "SRAM1LPEN,SRAM1LPEN" "0,1" group.long 0xC00++0x3 line.long 0x0 "RCC_MC_RSTSCLRR,This register is used by the MCU to check the reset source." bitfld.long 0x0 10. "WWDG1RSTF,WWDG1RSTF" "0,1" bitfld.long 0x0 9. "IWDG2RSTF,IWDG2RSTF" "0,1" newline bitfld.long 0x0 8. "IWDG1RSTF,IWDG1RSTF" "0,1" bitfld.long 0x0 7. "MCSYSRSTF,MCSYSRSTF" "0,1" newline bitfld.long 0x0 6. "MPSYSRSTF,MPSYSRSTF" "0,1" bitfld.long 0x0 5. "MCURSTF,MCURSTF" "0,1" newline bitfld.long 0x0 4. "VCORERSTF,VCORERSTF" "0,1" bitfld.long 0x0 3. "HCSSRSTF,HCSSRSTF" "0,1" newline bitfld.long 0x0 2. "PADRSTF,PADRSTF" "0,1" bitfld.long 0x0 1. "BORRSTF,BORRSTF" "0,1" newline bitfld.long 0x0 0. "PORRSTF,PORRSTF" "0,1" group.long 0xC14++0x7 line.long 0x0 "RCC_MC_CIER,This register shall be used by the MCU to control the interrupt source enable. Refer to Section10.5: RCC interrupts for more details." bitfld.long 0x0 20. "WKUPIE,WKUPIE" "0,1" bitfld.long 0x0 16. "LSECSSIE,LSECSSIE" "0,1" newline bitfld.long 0x0 11. "PLL4DYIE,PLL4DYIE" "0,1" bitfld.long 0x0 10. "PLL3DYIE,PLL3DYIE" "0,1" newline bitfld.long 0x0 9. "PLL2DYIE,PLL2DYIE" "0,1" bitfld.long 0x0 8. "PLL1DYIE,PLL1DYIE" "0,1" newline bitfld.long 0x0 4. "CSIRDYIE,CSIRDYIE" "0,1" bitfld.long 0x0 3. "HSERDYIE,HSERDYIE" "0,1" newline bitfld.long 0x0 2. "HSIRDYIE,HSIRDYIE" "0,1" bitfld.long 0x0 1. "LSERDYIE,LSERDYIE" "0,1" newline bitfld.long 0x0 0. "LSIRDYIE,LSIRDYIE" "0,1" line.long 0x4 "RCC_MC_CIFR,This register shall be used by the MCU in order to read and clear the interrupt flags." bitfld.long 0x4 20. "WKUPF,WKUPF" "0,1" bitfld.long 0x4 16. "LSECSSF,LSECSSF" "0,1" newline bitfld.long 0x4 11. "PLL4DYF,PLL4DYF" "0,1" bitfld.long 0x4 10. "PLL3DYF,PLL3DYF" "0,1" newline bitfld.long 0x4 9. "PLL2DYF,PLL2DYF" "0,1" bitfld.long 0x4 8. "PLL1DYF,PLL1DYF" "0,1" newline bitfld.long 0x4 4. "CSIRDYF,CSIRDYF" "0,1" bitfld.long 0x4 3. "HSERDYF,HSERDYF" "0,1" newline bitfld.long 0x4 2. "HSIRDYF,HSIRDYF" "0,1" bitfld.long 0x4 1. "LSERDYF,LSERDYF" "0,1" newline bitfld.long 0x4 0. "LSIRDYF,LSIRDYF" "0,1" endif sif (cpuis("STM32MP153*")) group.long 0x0++0x3 line.long 0x0 "RCC_TZCR,This register is used to switch the RCC into secure mode. This register can only be accessed in secure mode." bitfld.long 0x0 1. "MCKPROT,MCKPROT" "0,1" bitfld.long 0x0 0. "TZEN,TZEN" "0,1" group.long 0xC++0x7 line.long 0x0 "RCC_OCENSETR,This register is used to control the oscillators.Writing to this register has no effect. writing will set the corresponding bits. Reading will give the effective values of each bit.If TZEN = MCKPROT = . this register can only be modified.." bitfld.long 0x0 11. "HSECSSON,HSECSSON" "0,1" bitfld.long 0x0 10. "HSEBYP,HSEBYP" "0,1" newline bitfld.long 0x0 9. "HSEKERON,HSEKERON" "0,1" bitfld.long 0x0 8. "HSEON,HSEON" "0,1" newline bitfld.long 0x0 7. "DIGBYP,DIGBYP" "0,1" bitfld.long 0x0 5. "CSIKERON,CSIKERON" "0,1" newline bitfld.long 0x0 4. "CSION,CSION" "0,1" bitfld.long 0x0 1. "HSIKERON,HSIKERON" "0,1" newline bitfld.long 0x0 0. "HSION,HSION" "0,1" line.long 0x4 "RCC_OCENCLRR,This register is used to control the oscillators.Writing to this register has no effect. writing will clear the corresponding bits. Reading will give the effective values of the enable bits.If TZEN = . this register can only be modified in.." bitfld.long 0x4 10. "HSEBYP,HSEBYP" "0,1" bitfld.long 0x4 9. "HSEKERON,HSEKERON" "0,1" newline bitfld.long 0x4 8. "HSEON,HSEON" "0,1" bitfld.long 0x4 7. "DIGBYP,DIGBYP" "0,1" newline bitfld.long 0x4 5. "CSIKERON,CSIKERON" "0,1" bitfld.long 0x4 4. "CSION,CSION" "0,1" newline bitfld.long 0x4 1. "HSIKERON,HSIKERON" "0,1" bitfld.long 0x4 0. "HSION,HSION" "0,1" group.long 0x18++0x1B line.long 0x0 "RCC_HSICFGR,This register is used to configure the HSI. If TZEN = . this register can only be modified in secure mode. Write access to this register is not allowed during the clock restore sequence. See Section: The clock restore sequence description for.." hexmask.long.word 0x0 16.--27. 1. "HSICAL,HSICAL" hexmask.long.byte 0x0 8.--14. 1. "HSITRIM,HSITRIM" newline bitfld.long 0x0 0.--1. "HSIDIV,HSIDIV" "0,1,2,3" line.long 0x4 "RCC_CSICFGR,This register is used to fine-tune the CSI frequency. If TZEN = MCKPROT = . this register can only be modified in secure mode. Write access to this register is not allowed during the clock restore sequence. See The clock restore sequence.." hexmask.long.byte 0x4 16.--23. 1. "CSICAL,CSICAL" hexmask.long.byte 0x4 8.--12. 1. "CSITRIM,CSITRIM" line.long 0x8 "RCC_MPCKSELR,This register is used to select the clock source for the MPU. If TZEN = . this register can only be modified in secure mode. Write access to this register is not allowed during the clock restore sequence. See Section: The clock restore.." rbitfld.long 0x8 31. "MPUSRCRDY,MPUSRCRDY" "0,1" bitfld.long 0x8 0.--1. "MPUSRC,MPUSRC" "0,1,2,3" line.long 0xC "RCC_ASSCKSELR,This register is used to select the clock source for the AXI sub-system. If TZEN = . this register can only be modified in secure mode. Write access to this register is not allowed during the clock restore sequence. See Section: The clock.." rbitfld.long 0xC 31. "AXISSRCRDY,AXISSRCRDY" "0,1" bitfld.long 0xC 0.--2. "AXISSRC,AXISSRC" "0,1,2,3,4,5,6,7" line.long 0x10 "RCC_RCK12SELR,This register is used to select the reference clock for PLL1 and PLL2. If TZEN = . this register can only be modified in secure mode. Write access to this register is not allowed during the clock restore sequence. See Section: The clock.." rbitfld.long 0x10 31. "PLL12SRCRDY,PLL12SRCRDY" "0,1" bitfld.long 0x10 0.--1. "PLL12SRC,PLL12SRC" "0,1,2,3" line.long 0x14 "RCC_MPCKDIVR,This register is used to control the MPU clock prescaler. Refer to Section: Sub-system clock generation for additional information. If TZEN = . this register can only be modified in secure mode." rbitfld.long 0x14 31. "MPUDIVRDY,MPUDIVRDY" "0,1" bitfld.long 0x14 0.--2. "MPUDIV,MPUDIV" "0,1,2,3,4,5,6,7" line.long 0x18 "RCC_AXIDIVR,This register is used to control the AXI Matrix clock prescaler. Refer to Section: Sub-system clock generation for additional information. If TZEN = . this register can only be modified in secure mode." rbitfld.long 0x18 31. "AXIDIVRDY,AXIDIVRDY" "0,1" bitfld.long 0x18 0.--2. "AXIDIV,AXIDIV" "0,1,2,3,4,5,6,7" group.long 0x3C++0xF line.long 0x0 "RCC_APB4DIVR,This register is used to control the APB4 clock divider. Refer to Section: Sub-system clock generation for additional information. If TZEN = . this register can only be modified in secure mode." rbitfld.long 0x0 31. "APB4DIVRDY,APB4DIVRDY" "0,1" bitfld.long 0x0 0.--2. "APB4DIV,APB4DIV" "0,1,2,3,4,5,6,7" line.long 0x4 "RCC_APB5DIVR,This register is used to control the APB5 clock divider. Refer to Section: Sub-system clock generation for additional information. If TZEN = . this register can only be modified in secure mode." rbitfld.long 0x4 31. "APB5DIVRDY,APB5DIVRDY" "0,1" bitfld.long 0x4 0.--2. "APB5DIV,APB5DIV" "0,1,2,3,4,5,6,7" line.long 0x8 "RCC_RTCDIVR,This register is used to divide the HSE clock for RTC. If TZEN = . this register can only be modified in secure mode." hexmask.long.byte 0x8 0.--5. 1. "RTCDIV,RTCDIV" line.long 0xC "RCC_MSSCKSELR,This register is used to select the clock source for the MCU sub-system. including the MCU itself. If TZEN = MCKPROT = . this register can only be modified in secure mode. Write access to this register is not allowed during the clock.." rbitfld.long 0xC 31. "MCUSSRCRDY,MCUSSRCRDY" "0,1" bitfld.long 0xC 0.--1. "MCUSSRC,MCUSSRC" "0,1,2,3" group.long 0x80++0x27 line.long 0x0 "RCC_PLL1CR,This register is used to control the PLL1. If TZEN = . this register can only be modified in secure mode. Write access to this register is not allowed during the clock restore sequence. See Section: The clock restore sequence description for.." bitfld.long 0x0 6. "DIVREN,DIVREN" "0,1" bitfld.long 0x0 5. "DIVQEN,DIVQEN" "0,1" newline bitfld.long 0x0 4. "DIVPEN,DIVPEN" "0,1" bitfld.long 0x0 2. "SSCG_CTRL,SSCG_CTRL" "0,1" newline rbitfld.long 0x0 1. "PLL1RDY,PLL1RDY" "0,1" bitfld.long 0x0 0. "PLLON,PLLON" "0,1" line.long 0x4 "RCC_PLL1CFGR1,This register is used to configure the PLL1. If TZEN = . this register can only be modified in secure mode. Write access to this register is not allowed during the clock restore sequence. See Section: The clock restore sequence description.." hexmask.long.byte 0x4 16.--21. 1. "DIVM1,DIVM1" hexmask.long.word 0x4 0.--8. 1. "DIVN,DIVN" line.long 0x8 "RCC_PLL1CFGR2,This register is used to configure the PLL1. If TZEN = . this register can only be modified in secure mode. Write access to this register is not allowed during the clock restore sequence. See Section: The clock restore sequence description.." hexmask.long.byte 0x8 16.--22. 1. "DIVR,DIVR" hexmask.long.byte 0x8 8.--14. 1. "DIVQ,DIVQ" newline hexmask.long.byte 0x8 0.--6. 1. "DIVP,DIVP" line.long 0xC "RCC_PLL1FRACR,This register is used to fine-tune the frequency of the PLL1 VCO. If TZEN = . this register can only be modified in secure mode. Write access to this register is not allowed during the clock restore sequence. See Section: The clock restore.." bitfld.long 0xC 16. "FRACLE,FRACLE" "0,1" hexmask.long.word 0xC 3.--15. 1. "FRACV,FRACV" line.long 0x10 "RCC_PLL1CSGR,This register is used to configure the PLL1.It is not recommended to change the content of this register when the PLL1 is enabled (PLLON = ). Refer to Section: Using the PLLs in spread spectrum mode for details. If TZEN = . this register can.." hexmask.long.word 0x10 16.--30. 1. "INC_STEP,INC_STEP" bitfld.long 0x10 15. "SSCG_MODE,SSCG_MODE" "0,1" newline bitfld.long 0x10 14. "RPDFN_DIS,RPDFN_DIS" "0,1" bitfld.long 0x10 13. "TPDFN_DIS,TPDFN_DIS" "0,1" newline hexmask.long.word 0x10 0.--12. 1. "MOD_PER,MOD_PER" line.long 0x14 "RCC_PLL2CR,This register is used to control the PLL2. If TZEN = . this register can only be modified in secure mode. Write access to this register is not allowed during the clock restore sequence. See Section: The clock restore sequence description for.." bitfld.long 0x14 6. "DIVREN,DIVREN" "0,1" bitfld.long 0x14 5. "DIVQEN,DIVQEN" "0,1" newline bitfld.long 0x14 4. "DIVPEN,DIVPEN" "0,1" bitfld.long 0x14 2. "SSCG_CTRL,SSCG_CTRL" "0,1" newline rbitfld.long 0x14 1. "PLL2RDY,PLL2RDY" "0,1" bitfld.long 0x14 0. "PLLON,PLLON" "0,1" line.long 0x18 "RCC_PLL2CFGR1,This register is used to configure the PLL2. If TZEN = . this register can only be modified in secure mode. Write access to this register is not allowed during the clock restore sequence. See Section: The clock restore sequence description.." hexmask.long.byte 0x18 16.--21. 1. "DIVM2,DIVM2" hexmask.long.word 0x18 0.--8. 1. "DIVN,DIVN" line.long 0x1C "RCC_PLL2CFGR2,This register is used to configure the PLL2. If TZEN = . this register can only be modified in secure mode. Write access to this register is not allowed during the clock restore sequence. See Section: The clock restore sequence description.." hexmask.long.byte 0x1C 16.--22. 1. "DIVR,DIVR" hexmask.long.byte 0x1C 8.--14. 1. "DIVQ,DIVQ" newline hexmask.long.byte 0x1C 0.--6. 1. "DIVP,DIVP" line.long 0x20 "RCC_PLL2FRACR,This register is used to fine-tune the frequency of the PLL2 VCO. If TZEN = . this register can only be modified in secure mode. Write access to this register is not allowed during the clock restore sequence. See Section: The clock restore.." bitfld.long 0x20 16. "FRACLE,FRACLE" "0,1" hexmask.long.word 0x20 3.--15. 1. "FRACV,FRACV" line.long 0x24 "RCC_PLL2CSGR,This register is used to configure the PLL2. It is not recommended to change the content of this register when the PLL2 is enabled (PLLON = ). Refer to Section: Using the PLLs in spread spectrum mode for details. If TZEN = . this register.." hexmask.long.word 0x24 16.--30. 1. "INC_STEP,INC_STEP" bitfld.long 0x24 15. "SSCG_MODE,SSCG_MODE" "0,1" newline bitfld.long 0x24 14. "RPDFN_DIS,RPDFN_DIS" "0,1" bitfld.long 0x24 13. "TPDFN_DIS,TPDFN_DIS" "0,1" newline hexmask.long.word 0x24 0.--12. 1. "MOD_PER,MOD_PER" group.long 0xC0++0x1B line.long 0x0 "RCC_I2C46CKSELR,This register is used to control the selection of the kernel clock for the I2C4 and I2C6. Note that changing the clock source on-the-fly is allowed. and will not generate any timing violation. however the user has to ensure that both the.." bitfld.long 0x0 0.--2. "I2C46SRC,I2C46SRC" "0,1,2,3,4,5,6,7" line.long 0x4 "RCC_SPI6CKSELR,This register is used to control the selection of the kernel clock for the SPI6. Note that changing the clock source on-the-fly is allowed. and will not generate any timing violation. however the user has to ensure that both the previous.." bitfld.long 0x4 0.--2. "SPI6SRC,SPI6SRC" "0,1,2,3,4,5,6,7" line.long 0x8 "RCC_UART1CKSELR,This register is used to control the selection of the kernel clock for the USART1. Note that changing the clock source on-the-fly is allowed. and will not generate any timing violation. however the user has to ensure that both the.." bitfld.long 0x8 0.--2. "UART1SRC,UART1SRC" "0,1,2,3,4,5,6,7" line.long 0xC "RCC_RNG1CKSELR,This register is used to control the selection of the kernel clock for the RNG1. Note that changing the clock source on-the-fly is allowed. and will not generate any timing violation. however the user has to ensure that both the previous.." bitfld.long 0xC 0.--1. "RNG1SRC,RNG1SRC" "0,1,2,3" line.long 0x10 "RCC_CPERCKSELR,This register is used to select an oscillator source as kernel clock for the per_ck clock. The per_ck clock is distributed to several peripherals. Refer to Section: Clock enabling delays." bitfld.long 0x10 0.--1. "CKPERSRC,CKPERSRC" "0,1,2,3" line.long 0x14 "RCC_STGENCKSELR,This register is used to select the peripheral clock for the STGEN block. Note that this clock is used to provide a time reference for the application. Refer to Section: Clock enabling delays. If TZEN = . this register can only be.." bitfld.long 0x14 0.--1. "STGENSRC,STGENSRC" "0,1,2,3" line.long 0x18 "RCC_DDRITFCR,This register is used to control the DDR interface. including the DDRC and DDRPHYC. If TZEN = . this register can only be modified in secure mode." hexmask.long.byte 0x18 28.--31. 1. "GSKP_DUR,GSKP_DUR" bitfld.long 0x18 25.--27. "DFILP_WIDTH,DFILP_WIDTH" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 24. "GSKPCTRL,GSKPCTRL" "0,1" bitfld.long 0x18 23. "GSKPMOD,GSKPMOD" "0,1" newline bitfld.long 0x18 20.--22. "DDRCKMOD,DDRCKMOD" "0,1,2,3,4,5,6,7" bitfld.long 0x18 19. "DPHYCTLRST,DPHYCTLRST" "0,1" newline bitfld.long 0x18 18. "DPHYRST,DPHYRST" "0,1" bitfld.long 0x18 17. "DPHYAPBRST,DPHYAPBRST" "0,1" newline bitfld.long 0x18 16. "DDRCORERST,DDRCORERST" "0,1" bitfld.long 0x18 15. "DDRCAXIRST,DDRCAXIRST" "0,1" newline bitfld.long 0x18 14. "DDRCAPBRST,DDRCAPBRST" "0,1" bitfld.long 0x18 11.--13. "KERDCG_DLY,KERDCG_DLY" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 10. "DDRPHYCAPBLPEN,DDRPHYCAPBLPEN" "0,1" bitfld.long 0x18 9. "DDRPHYCAPBEN,DDRPHYCAPBEN" "0,1" newline bitfld.long 0x18 8. "AXIDCGEN,AXIDCGEN" "0,1" bitfld.long 0x18 7. "DDRCAPBLPEN,DDRCAPBLPEN" "0,1" newline bitfld.long 0x18 6. "DDRCAPBEN,DDRCAPBEN" "0,1" bitfld.long 0x18 5. "DDRPHYCLPEN,DDRPHYCLPEN" "0,1" newline bitfld.long 0x18 4. "DDRPHYCEN,DDRPHYCEN" "0,1" bitfld.long 0x18 3. "DDRC2LPEN,DDRC2LPEN" "0,1" newline bitfld.long 0x18 2. "DDRC2EN,DDRC2EN" "0,1" bitfld.long 0x18 1. "DDRC1LPEN,DDRC1LPEN" "0,1" newline bitfld.long 0x18 0. "DDRC1EN,DDRC1EN" "0,1" group.long 0x100++0x13 line.long 0x0 "RCC_MP_BOOTCR,This register is used to control the HOLD boot function when the system exits from Standby. Refer to Section: MCU HOLD_BOOT after processor reset. This register is reset when a system reset occurs. but not when the circuit exits from.." bitfld.long 0x0 1. "MPU_BEN,MPU_BEN" "0,1" bitfld.long 0x0 0. "MCU_BEN,MCU_BEN" "0,1" line.long 0x4 "RCC_MP_SREQSETR,Writing has no effect. reading will return the values of the bits. Writing a sets the corresponding bit to . The MCU cannot access to this register. If TZEN = . this register can only be modified in secure mode." bitfld.long 0x4 1. "STPREQ_P1,STPREQ_P1" "0,1" bitfld.long 0x4 0. "STPREQ_P0,STPREQ_P0" "0,1" line.long 0x8 "RCC_MP_SREQCLRR,Writing has no effect. reading will return the effective values of the bits. Writing a sets the corresponding bit to . The MCU cannot access to this register. If TZEN = . this register can only be modified in secure mode." bitfld.long 0x8 1. "STPREQ_P1,STPREQ_P1" "0,1" bitfld.long 0x8 0. "STPREQ_P0,STPREQ_P0" "0,1" line.long 0xC "RCC_MP_GCR,The register contains global control bits. If TZEN = . this register can only be modified in secure mode." bitfld.long 0xC 0. "BOOT_MCU,BOOT_MCU" "0,1" line.long 0x10 "RCC_MP_APRSTCR,This register is used to control the behavior of the warm reset. If TZEN = . this register can only be modified in secure mode." hexmask.long.byte 0x10 8.--14. 1. "RSTTO,RSTTO" bitfld.long 0x10 0. "RDCTLEN,RDCTLEN" "0,1" rgroup.long 0x114++0x3 line.long 0x0 "RCC_MP_APRSTSR,This register provides a status of the RDCTL. If TZEN = . this register can only be modified in secure mode." hexmask.long.byte 0x0 8.--14. 1. "RSTTOV,RSTTOV" group.long 0x140++0x7 line.long 0x0 "RCC_BDCR,This register is used to control the LSE function. Wait states are inserted in case of successive write accesses to this register. The number of wait states may be up to 7 cycles of AHB4 clock.After a system reset. the register RCC_BDCR is.." bitfld.long 0x0 31. "VSWRST,VSWRST" "0,1" bitfld.long 0x0 20. "RTCCKEN,RTCCKEN" "0,1" newline rbitfld.long 0x0 16.--17. "RTCSRC,RTCSRC" "0,1,2,3" rbitfld.long 0x0 9. "LSECSSD,LSECSSD" "0,1" newline bitfld.long 0x0 8. "LSECSSON,LSECSSON" "0,1" bitfld.long 0x0 4.--5. "LSEDRV,LSEDRV" "0,1,2,3" newline rbitfld.long 0x0 3. "DIGBYP,DIGBYP" "0,1" rbitfld.long 0x0 2. "LSERDY,LSERDY" "0,1" newline bitfld.long 0x0 1. "LSEBYP,LSEBYP" "0,1" bitfld.long 0x0 0. "LSEON,LSEON" "0,1" line.long 0x4 "RCC_RDLSICR,This register is used to control the minimum NRST active duration and LSI function.0 to 7 wait states are inserted for word. half-word and byte accesses. Wait states are inserted in case of successive accesses to this register.This register.." hexmask.long.byte 0x4 27.--31. 1. "SPARE,SPARE" bitfld.long 0x4 24.--26. "EADLY,EADLY" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x4 16.--20. 1. "MRD,MRD" rbitfld.long 0x4 1. "LSIRDY,LSIRDY" "0,1" newline bitfld.long 0x4 0. "LSION,LSION" "0,1" group.long 0x180++0x27 line.long 0x0 "RCC_APB4RSTSETR,This register is used to activate the reset of the corresponding peripheral. Writing has no effect. reading will return the effective values of the corresponding bits. Writing a activates the reset of the corresponding peripheral." bitfld.long 0x0 16. "USBPHYRST,USBPHYRST" "0,1" bitfld.long 0x0 8. "DDRPERFMRST,DDRPERFMRST" "0,1" newline bitfld.long 0x0 4. "DSIRST,DSIRST" "0,1" bitfld.long 0x0 0. "LTDCRST,LTDCRST" "0,1" line.long 0x4 "RCC_APB4RSTCLRR,This register is used to release the reset of the corresponding peripheral. Writing has no effect. reading will return the effective values of the corresponding bits. Writing a releases the reset of the corresponding peripheral." bitfld.long 0x4 16. "USBPHYRST,USBPHYRST" "0,1" bitfld.long 0x4 8. "DDRPERFMRST,DDRPERFMRST" "0,1" newline bitfld.long 0x4 4. "DSIRST,DSIRST" "0,1" bitfld.long 0x4 0. "LTDCRST,LTDCRST" "0,1" line.long 0x8 "RCC_APB5RSTSETR,This register is used to activate the reset of the corresponding peripheral. Writing has no effect. reading will return the effective values of the corresponding bits. Writing a activates the reset of the corresponding peripheral. If.." bitfld.long 0x8 20. "STGENRST,STGENRST" "0,1" bitfld.long 0x8 4. "USART1RST,USART1RST" "0,1" newline bitfld.long 0x8 3. "I2C6RST,I2C6RST" "0,1" bitfld.long 0x8 2. "I2C4RST,I2C4RST" "0,1" newline bitfld.long 0x8 0. "SPI6RST,SPI6RST" "0,1" line.long 0xC "RCC_APB5RSTCLRR,This register is used to release the reset of the corresponding peripheral. Writing has no effect. reading will return the effective values of the corresponding bits. Writing a releases the reset of the corresponding peripheral. If TZEN.." bitfld.long 0xC 20. "STGENRST,STGENRST" "0,1" bitfld.long 0xC 4. "USART1RST,USART1RST" "0,1" newline bitfld.long 0xC 3. "I2C6RST,I2C6RST" "0,1" bitfld.long 0xC 2. "I2C4RST,I2C4RST" "0,1" newline bitfld.long 0xC 0. "SPI6RST,SPI6RST" "0,1" line.long 0x10 "RCC_AHB5RSTSETR,This register is used to activate the reset of the corresponding peripheral. Writing has no effect. reading will return the effective values of the corresponding bits. Writing a activates the reset of the corresponding peripheral. If.." bitfld.long 0x10 16. "AXIMCRST,AXIMCRST" "0,1" bitfld.long 0x10 6. "RNG1RST,RNG1RST" "0,1" newline bitfld.long 0x10 5. "HASH1RST,HASH1RST" "0,1" bitfld.long 0x10 4. "CRYP1RST,CRYP1RST" "0,1" newline bitfld.long 0x10 0. "GPIOZRST,GPIOZRST" "0,1" line.long 0x14 "RCC_AHB5RSTCLRR,This register is used to release the reset of the corresponding peripheral. Writing has no effect. reading will return the effective values of the corresponding bits. Writing a releases the reset of the corresponding peripheral. If TZEN.." bitfld.long 0x14 16. "AXIMCRST,AXIMCRST" "0,1" bitfld.long 0x14 6. "RNG1RST,RNG1RST" "0,1" newline bitfld.long 0x14 5. "HASH1RST,HASH1RST" "0,1" bitfld.long 0x14 4. "CRYP1RST,CRYP1RST" "0,1" newline bitfld.long 0x14 0. "GPIOZRST,GPIOZRST" "0,1" line.long 0x18 "RCC_AHB6RSTSETR,This register is used to activate the reset of the corresponding peripheral. Writing has no effect. reading will return the effective values of the corresponding bits. Writing a activates the reset of the corresponding peripheral." bitfld.long 0x18 24. "USBHRST,USBHRST" "0,1" bitfld.long 0x18 20. "CRC1RST,CRC1RST" "0,1" newline bitfld.long 0x18 17. "SDMMC2RST,SDMMC2RST" "0,1" bitfld.long 0x18 16. "SDMMC1RST,SDMMC1RST" "0,1" newline bitfld.long 0x18 14. "QSPIRST,QSPIRST" "0,1" bitfld.long 0x18 12. "FMCRST,FMCRST" "0,1" newline bitfld.long 0x18 10. "ETHMACRST,ETHMACRST" "0,1" bitfld.long 0x18 5. "GPURST,GPURST" "0,1" line.long 0x1C "RCC_AHB6RSTCLRR,This register is used to release the reset of the corresponding peripheral. Writing has no effect. reading will return the effective values of the corresponding bits. Writing a releases the reset of the corresponding peripheral." bitfld.long 0x1C 24. "USBHRST,USBHRST" "0,1" bitfld.long 0x1C 20. "CRC1RST,CRC1RST" "0,1" newline bitfld.long 0x1C 17. "SDMMC2RST,SDMMC2RST" "0,1" bitfld.long 0x1C 16. "SDMMC1RST,SDMMC1RST" "0,1" newline bitfld.long 0x1C 14. "QSPIRST,QSPIRST" "0,1" bitfld.long 0x1C 12. "FMCRST,FMCRST" "0,1" newline bitfld.long 0x1C 10. "ETHMACRST,ETHMACRST" "0,1" line.long 0x20 "RCC_TZAHB6RSTSETR,This register is used to activate the reset of the corresponding peripheral. Writing has no effect. reading will return the effective values of the corresponding bits. Writing a activates the reset of the corresponding peripheral. If.." bitfld.long 0x20 0. "MDMARST,MDMARST" "0,1" line.long 0x24 "RCC_TZAHB6RSTCLRR,This register is used to release the reset of the corresponding peripheral. Writing has no effect. reading will return the effective values of the corresponding bits. Writing a releases the reset of the corresponding peripheral. If.." bitfld.long 0x24 0. "MDMARST,MDMARST" "0,1" group.long 0x200++0x27 line.long 0x0 "RCC_MP_APB4ENSETR,This register is used to set the peripheral clock enable bit of the corresponding peripheral to . It shall be used to allocate a peripheral to the MPU. Writing has no effect. reading will return the effective values of the.." bitfld.long 0x0 20. "STGENROEN,STGENROEN" "0,1" bitfld.long 0x0 16. "USBPHYEN,USBPHYEN" "0,1" newline bitfld.long 0x0 15. "IWDG2APBEN,IWDG2APBEN" "0,1" bitfld.long 0x0 8. "DDRPERFMEN,DDRPERFMEN" "0,1" newline bitfld.long 0x0 4. "DSIEN,DSIEN" "0,1" bitfld.long 0x0 0. "LTDCEN,LTDCEN" "0,1" line.long 0x4 "RCC_MP_APB4ENCLRR,This register is used to clear the peripheral clock enable bit of the corresponding peripheral. It shall be used to deallocate a peripheral from MPU. Writing has no effect. reading will return the effective values of the corresponding.." bitfld.long 0x4 20. "STGENROEN,STGENROEN" "0,1" bitfld.long 0x4 16. "USBPHYEN,USBPHYEN" "0,1" newline bitfld.long 0x4 15. "IWDG2APBEN,IWDG2APBEN" "0,1" bitfld.long 0x4 8. "DDRPERFMEN,DDRPERFMEN" "0,1" newline bitfld.long 0x4 4. "DSIEN,DSIEN" "0,1" bitfld.long 0x4 0. "LTDCEN,LTDCEN" "0,1" line.long 0x8 "RCC_MP_APB5ENSETR,This register is used to set the peripheral clock enable bit of the corresponding peripheral to . It shall be used to allocate a peripheral to the MPU. Writing has no effect. reading will return the effective values of the.." bitfld.long 0x8 20. "STGENEN,STGENEN" "0,1" bitfld.long 0x8 16. "BSECEN,BSECEN" "0,1" newline bitfld.long 0x8 15. "IWDG1APBEN,IWDG1APBEN" "0,1" bitfld.long 0x8 13. "TZPCEN,TZPCEN" "0,1" newline bitfld.long 0x8 12. "TZC2EN,TZC2EN" "0,1" bitfld.long 0x8 11. "TZC1EN,TZC1EN" "0,1" newline bitfld.long 0x8 8. "RTCAPBEN,RTCAPBEN" "0,1" bitfld.long 0x8 4. "USART1EN,USART1EN" "0,1" newline bitfld.long 0x8 3. "I2C6EN,I2C6EN" "0,1" bitfld.long 0x8 2. "I2C4EN,I2C4EN" "0,1" newline bitfld.long 0x8 0. "SPI6EN,SPI6EN" "0,1" line.long 0xC "RCC_MP_APB5ENCLRR,This register is used to clear the peripheral clock enable bit of the corresponding peripheral. It shall be used to deallocate a peripheral from MPU. Writing has no effect. reading will return the effective values of the corresponding.." bitfld.long 0xC 20. "STGENEN,STGENEN" "0,1" bitfld.long 0xC 16. "BSECEN,BSECEN" "0,1" newline bitfld.long 0xC 15. "IWDG1APBEN,IWDG1APBEN" "0,1" bitfld.long 0xC 13. "TZPCEN,TZPCEN" "0,1" newline bitfld.long 0xC 12. "TZC2EN,TZC2EN" "0,1" bitfld.long 0xC 11. "TZC1EN,TZC1EN" "0,1" newline bitfld.long 0xC 8. "RTCAPBEN,RTCAPBEN" "0,1" bitfld.long 0xC 4. "USART1EN,USART1EN" "0,1" newline bitfld.long 0xC 3. "I2C6EN,I2C6EN" "0,1" bitfld.long 0xC 2. "I2C4EN,I2C4EN" "0,1" newline bitfld.long 0xC 0. "SPI6EN,SPI6EN" "0,1" line.long 0x10 "RCC_MP_AHB5ENSETR,This register is used to set the peripheral clock enable bit of the corresponding peripheral to . It shall be used to allocate a peripheral to the MPU. Writing has no effect. reading will return the effective values of the.." bitfld.long 0x10 16. "AXIMCEN,AXIMCEN" "0,1" bitfld.long 0x10 8. "BKPSRAMEN,BKPSRAMEN" "0,1" newline bitfld.long 0x10 6. "RNG1EN,RNG1EN" "0,1" bitfld.long 0x10 5. "HASH1EN,HASH1EN" "0,1" newline bitfld.long 0x10 4. "CRYP1EN,CRYP1EN" "0,1" bitfld.long 0x10 0. "GPIOZEN,GPIOZEN" "0,1" line.long 0x14 "RCC_MP_AHB5ENCLRR,This register is used to clear the peripheral clock enable bit of the corresponding peripheral. It shall be used to deallocate a peripheral from MPU. Writing has no effect. reading will return the effective values of the corresponding.." bitfld.long 0x14 16. "AXIMCEN,AXIMCEN" "0,1" bitfld.long 0x14 8. "BKPSRAMEN,BKPSRAMEN" "0,1" newline bitfld.long 0x14 6. "RNG1EN,RNG1EN" "0,1" bitfld.long 0x14 5. "HASH1EN,HASH1EN" "0,1" newline bitfld.long 0x14 4. "CRYP1EN,CRYP1EN" "0,1" bitfld.long 0x14 0. "GPIOZEN,GPIOZEN" "0,1" line.long 0x18 "RCC_MP_AHB6ENSETR,This register is used to set the peripheral clock enable bit of the corresponding peripheral to . It shall be used to allocate a peripheral to the MPU. Writing has no effect. reading will return the effective values of the.." bitfld.long 0x18 24. "USBHEN,USBHEN" "0,1" bitfld.long 0x18 20. "CRC1EN,CRC1EN" "0,1" newline bitfld.long 0x18 17. "SDMMC2EN,SDMMC2EN" "0,1" bitfld.long 0x18 16. "SDMMC1EN,SDMMC1EN" "0,1" newline bitfld.long 0x18 14. "QSPIEN,QSPIEN" "0,1" bitfld.long 0x18 12. "FMCEN,FMCEN" "0,1" newline bitfld.long 0x18 10. "ETHMACEN,ETHMACEN" "0,1" bitfld.long 0x18 9. "ETHRXEN,ETHRXEN" "0,1" newline bitfld.long 0x18 8. "ETHTXEN,ETHTXEN" "0,1" bitfld.long 0x18 7. "ETHCKEN,ETHCKEN" "0,1" newline bitfld.long 0x18 5. "GPUEN,GPUEN" "0,1" bitfld.long 0x18 0. "MDMAEN,MDMAEN" "0,1" line.long 0x1C "RCC_MP_AHB6ENCLRR,This register is used to clear the peripheral clock enable bit of the corresponding peripheral. It shall be used to deallocate a peripheral from MPU. Writing has no effect. reading will return the effective values of the corresponding.." bitfld.long 0x1C 24. "USBHEN,USBHEN" "0,1" bitfld.long 0x1C 20. "CRC1EN,CRC1EN" "0,1" newline bitfld.long 0x1C 17. "SDMMC2EN,SDMMC2EN" "0,1" bitfld.long 0x1C 16. "SDMMC1EN,SDMMC1EN" "0,1" newline bitfld.long 0x1C 14. "QSPIEN,QSPIEN" "0,1" bitfld.long 0x1C 12. "FMCEN,FMCEN" "0,1" newline bitfld.long 0x1C 10. "ETHMACEN,ETHMACEN" "0,1" bitfld.long 0x1C 9. "ETHRXEN,ETHRXEN" "0,1" newline bitfld.long 0x1C 8. "ETHTXEN,ETHTXEN" "0,1" bitfld.long 0x1C 7. "ETHCKEN,ETHCKEN" "0,1" newline bitfld.long 0x1C 5. "GPUEN,GPUEN" "0,1" bitfld.long 0x1C 0. "MDMAEN,MDMAEN" "0,1" line.long 0x20 "RCC_MP_TZAHB6ENSETR,This register is used to set the peripheral clock enable bit of the corresponding peripheral to . It shall be used to allocate a peripheral to the MPU. Writing has no effect. reading will return the effective values of the.." bitfld.long 0x20 0. "MDMAEN,MDMAEN" "0,1" line.long 0x24 "RCC_MP_TZAHB6ENCLRR,This register is used to clear the peripheral clock enable bit of the corresponding peripheral. It shall be used to deallocate a peripheral from MPU. Writing has no effect. reading will return the effective values of the.." bitfld.long 0x24 0. "MDMAEN,MDMAEN" "0,1" group.long 0x280++0x1F line.long 0x0 "RCC_MC_APB4ENSETR,This register is used to set the peripheral clock enable bit" bitfld.long 0x0 20. "STGENROEN,STGENROEN" "0,1" bitfld.long 0x0 16. "USBPHYEN,USBPHYEN" "0,1" newline bitfld.long 0x0 8. "DDRPERFMEN,DDRPERFMEN" "0,1" bitfld.long 0x0 4. "DSIEN,DSIEN" "0,1" newline bitfld.long 0x0 0. "LTDCEN,LTDCEN" "0,1" line.long 0x4 "RCC_MC_APB4ENCLRR,This register is used to clear the peripheral clock enable bit" bitfld.long 0x4 20. "STGENROEN,STGENROEN" "0,1" bitfld.long 0x4 16. "USBPHYEN,USBPHYEN" "0,1" newline bitfld.long 0x4 8. "DDRPERFMEN,DDRPERFMEN" "0,1" bitfld.long 0x4 4. "DSIEN,DSIEN" "0,1" newline bitfld.long 0x4 0. "LTDCEN,LTDCEN" "0,1" line.long 0x8 "RCC_MC_APB5ENSETR,This register is used to set the peripheral clock enable bit" bitfld.long 0x8 20. "STGENEN,STGENEN" "0,1" bitfld.long 0x8 16. "BSECEN,BSECEN" "0,1" newline bitfld.long 0x8 13. "TZPCEN,TZPCEN" "0,1" bitfld.long 0x8 12. "TZC2EN,TZC2EN" "0,1" newline bitfld.long 0x8 11. "TZC1EN,TZC1EN" "0,1" bitfld.long 0x8 8. "RTCAPBEN,RTCAPBEN" "0,1" newline bitfld.long 0x8 4. "USART1EN,USART1EN" "0,1" bitfld.long 0x8 3. "I2C6EN,I2C6EN" "0,1" newline bitfld.long 0x8 2. "I2C4EN,I2C4EN" "0,1" bitfld.long 0x8 0. "SPI6EN,SPI6EN" "0,1" line.long 0xC "RCC_MC_APB5ENCLRR,This register is used to clear the peripheral clock enable bit" bitfld.long 0xC 20. "STGENEN,STGENEN" "0,1" bitfld.long 0xC 16. "BSECEN,BSECEN" "0,1" newline bitfld.long 0xC 13. "TZPCEN,TZPCEN" "0,1" bitfld.long 0xC 12. "TZC2EN,TZC2EN" "0,1" newline bitfld.long 0xC 11. "TZC1EN,TZC1EN" "0,1" bitfld.long 0xC 8. "RTCAPBEN,RTCAPBEN" "0,1" newline bitfld.long 0xC 4. "USART1EN,USART1EN" "0,1" bitfld.long 0xC 3. "I2C6EN,I2C6EN" "0,1" newline bitfld.long 0xC 2. "I2C4EN,I2C4EN" "0,1" bitfld.long 0xC 0. "SPI6EN,SPI6EN" "0,1" line.long 0x10 "RCC_MC_AHB5ENSETR,This register is used to set the peripheral clock enable bit If TZEN = . this register can only be modified in secure mode." bitfld.long 0x10 8. "BKPSRAMEN,BKPSRAMEN" "0,1" bitfld.long 0x10 6. "RNG1EN,RNG1EN" "0,1" newline bitfld.long 0x10 5. "HASH1EN,HASH1EN" "0,1" bitfld.long 0x10 4. "CRYP1EN,CRYP1EN" "0,1" newline bitfld.long 0x10 0. "GPIOZEN,GPIOZEN" "0,1" line.long 0x14 "RCC_MC_AHB5ENCLRR,This register is used to clear the peripheral clock enable bit If TZEN = . this register can only be modified in secure mode." bitfld.long 0x14 8. "BKPSRAMEN,BKPSRAMEN" "0,1" bitfld.long 0x14 6. "RNG1EN,RNG1EN" "0,1" newline bitfld.long 0x14 5. "HASH1EN,HASH1EN" "0,1" bitfld.long 0x14 4. "CRYP1EN,CRYP1EN" "0,1" newline bitfld.long 0x14 0. "GPIOZEN,GPIOZEN" "0,1" line.long 0x18 "RCC_MC_AHB6ENSETR,This register is used to set the peripheral clock enable bit" bitfld.long 0x18 24. "USBHEN,USBHEN" "0,1" bitfld.long 0x18 20. "CRC1EN,CRC1EN" "0,1" newline bitfld.long 0x18 17. "SDMMC2EN,SDMMC2EN" "0,1" bitfld.long 0x18 16. "SDMMC1EN,SDMMC1EN" "0,1" newline bitfld.long 0x18 14. "QSPIEN,QSPIEN" "0,1" bitfld.long 0x18 12. "FMCEN,FMCEN" "0,1" newline bitfld.long 0x18 10. "ETHMACEN,ETHMACEN" "0,1" bitfld.long 0x18 9. "ETHRXEN,ETHRXEN" "0,1" newline bitfld.long 0x18 8. "ETHTXEN,ETHTXEN" "0,1" bitfld.long 0x18 7. "ETHCKEN,ETHCKEN" "0,1" newline bitfld.long 0x18 5. "GPUEN,GPUEN" "0,1" bitfld.long 0x18 0. "MDMAEN,MDMAEN" "0,1" line.long 0x1C "RCC_MC_AHB6ENCLRR,This register is used to clear the peripheral clock enable bit" bitfld.long 0x1C 24. "USBHEN,USBHEN" "0,1" bitfld.long 0x1C 20. "CRC1EN,CRC1EN" "0,1" newline bitfld.long 0x1C 17. "SDMMC2EN,SDMMC2EN" "0,1" bitfld.long 0x1C 16. "SDMMC1EN,SDMMC1EN" "0,1" newline bitfld.long 0x1C 14. "QSPIEN,QSPIEN" "0,1" bitfld.long 0x1C 12. "FMCEN,FMCEN" "0,1" newline bitfld.long 0x1C 10. "ETHMACEN,ETHMACEN" "0,1" bitfld.long 0x1C 9. "ETHRXEN,ETHRXEN" "0,1" newline bitfld.long 0x1C 8. "ETHTXEN,ETHTXEN" "0,1" bitfld.long 0x1C 7. "ETHCKEN,ETHCKEN" "0,1" newline bitfld.long 0x1C 5. "GPUEN,GPUEN" "0,1" bitfld.long 0x1C 0. "MDMAEN,MDMAEN" "0,1" group.long 0x300++0x27 line.long 0x0 "RCC_MP_APB4LPENSETR,This register is used by the MCU in order to clear the PERxLPEN bits" bitfld.long 0x0 21. "STGENROSTPEN,STGENROSTPEN" "0,1" bitfld.long 0x0 20. "STGENROLPEN,STGENROLPEN" "0,1" newline bitfld.long 0x0 16. "USBPHYLPEN,USBPHYLPEN" "0,1" bitfld.long 0x0 15. "IWDG2APBLPEN,IWDG2APBLPEN" "0,1" newline bitfld.long 0x0 8. "DDRPERFMLPEN,DDRPERFMLPEN" "0,1" bitfld.long 0x0 4. "DSILPEN,DSILPEN" "0,1" newline bitfld.long 0x0 0. "LTDCLPEN,LTDCLPEN" "0,1" line.long 0x4 "RCC_MP_APB4LPENCLRR,This register is used by the MCU" bitfld.long 0x4 21. "STGENROSTPEN,STGENROSTPEN" "0,1" bitfld.long 0x4 20. "STGENROLPEN,STGENROLPEN" "0,1" newline bitfld.long 0x4 16. "USBPHYLPEN,USBPHYLPEN" "0,1" bitfld.long 0x4 15. "IWDG2APBLPEN,IWDG2APBLPEN" "0,1" newline bitfld.long 0x4 8. "DDRPERFMLPEN,DDRPERFMLPEN" "0,1" bitfld.long 0x4 4. "DSILPEN,DSILPEN" "0,1" newline bitfld.long 0x4 0. "LTDCLPEN,LTDCLPEN" "0,1" line.long 0x8 "RCC_MP_APB5LPENSETR,This register is used by the MCU in order to clear the PERxLPEN bits If TZEN = . this register can only be modified in secure mode." bitfld.long 0x8 21. "STGENSTPEN,STGENSTPEN" "0,1" bitfld.long 0x8 20. "STGENLPEN,STGENLPEN" "0,1" newline bitfld.long 0x8 16. "BSECLPEN,BSECLPEN" "0,1" bitfld.long 0x8 15. "IWDG1APBLPEN,IWDG1APBLPEN" "0,1" newline bitfld.long 0x8 13. "TZPCLPEN,TZPCLPEN" "0,1" bitfld.long 0x8 12. "TZC2LPEN,TZC2LPEN" "0,1" newline bitfld.long 0x8 11. "TZC1LPEN,TZC1LPEN" "0,1" bitfld.long 0x8 8. "RTCAPBLPEN,RTCAPBLPEN" "0,1" newline bitfld.long 0x8 4. "USART1LPEN,USART1LPEN" "0,1" bitfld.long 0x8 3. "I2C6LPEN,I2C6LPEN" "0,1" newline bitfld.long 0x8 2. "I2C4LPEN,I2C4LPEN" "0,1" bitfld.long 0x8 0. "SPI6LPEN,SPI6LPEN" "0,1" line.long 0xC "RCC_MP_APB5LPENCLRR,This register is used by the Mpu." bitfld.long 0xC 21. "STGENSTPEN,STGENSTPEN" "0,1" bitfld.long 0xC 20. "STGENLPEN,STGENLPEN" "0,1" newline bitfld.long 0xC 16. "BSECLPEN,BSECLPEN" "0,1" bitfld.long 0xC 15. "IWDG1APBLPEN,IWDG1APBLPEN" "0,1" newline bitfld.long 0xC 13. "TZPCLPEN,TZPCLPEN" "0,1" bitfld.long 0xC 12. "TZC2LPEN,TZC2LPEN" "0,1" newline bitfld.long 0xC 11. "TZC1LPEN,TZC1LPEN" "0,1" bitfld.long 0xC 8. "RTCAPBLPEN,RTCAPBLPEN" "0,1" newline bitfld.long 0xC 4. "USART1LPEN,USART1LPEN" "0,1" bitfld.long 0xC 3. "I2C6LPEN,I2C6LPEN" "0,1" newline bitfld.long 0xC 2. "I2C4LPEN,I2C4LPEN" "0,1" bitfld.long 0xC 0. "SPI6LPEN,SPI6LPEN" "0,1" line.long 0x10 "RCC_MP_AHB5LPENSETR,This register is used by the MCU in order to clear the PERxLPEN bits If TZEN = . this register can only be modified in secure mode." bitfld.long 0x10 8. "BKPSRAMLPEN,BKPSRAMLPEN" "0,1" bitfld.long 0x10 6. "RNG1LPEN,RNG1LPEN" "0,1" newline bitfld.long 0x10 5. "HASH1LPEN,HASH1LPEN" "0,1" bitfld.long 0x10 4. "CRYP1LPEN,CRYP1LPEN" "0,1" newline bitfld.long 0x10 0. "GPIOZLPEN,GPIOZLPEN" "0,1" line.long 0x14 "RCC_MP_AHB5LPENCLRR,This register is used by the MCU" bitfld.long 0x14 8. "BKPSRAMLPEN,BKPSRAMLPEN" "0,1" bitfld.long 0x14 6. "RNG1LPEN,RNG1LPEN" "0,1" newline bitfld.long 0x14 5. "HASH1LPEN,HASH1LPEN" "0,1" bitfld.long 0x14 4. "CRYP1LPEN,CRYP1LPEN" "0,1" newline bitfld.long 0x14 0. "GPIOZLPEN,GPIOZLPEN" "0,1" line.long 0x18 "RCC_MP_AHB6LPENSETR,This register is used by the MCU in order to clear the PERxLPEN bits" bitfld.long 0x18 24. "USBHLPEN,USBHLPEN" "0,1" bitfld.long 0x18 20. "CRC1LPEN,CRC1LPEN" "0,1" newline bitfld.long 0x18 17. "SDMMC2LPEN,SDMMC2LPEN" "0,1" bitfld.long 0x18 16. "SDMMC1LPEN,SDMMC1LPEN" "0,1" newline bitfld.long 0x18 14. "QSPILPEN,QSPILPEN" "0,1" bitfld.long 0x18 12. "FMCLPEN,FMCLPEN" "0,1" newline bitfld.long 0x18 11. "ETHSTPEN,ETHSTPEN" "0,1" bitfld.long 0x18 10. "ETHMACLPEN,ETHMACLPEN" "0,1" newline bitfld.long 0x18 9. "ETHRXLPEN,ETHRXLPEN" "0,1" bitfld.long 0x18 8. "ETHTXLPEN,ETHTXLPEN" "0,1" newline bitfld.long 0x18 7. "ETHCKLPEN,ETHCKLPEN" "0,1" bitfld.long 0x18 5. "GPULPEN,GPULPEN" "0,1" newline bitfld.long 0x18 0. "MDMALPEN,MDMALPEN" "0,1" line.long 0x1C "RCC_MP_AHB6LPENCLRR,This register is used by the MCU in order to clear the PERxLPEN bits" bitfld.long 0x1C 24. "USBHLPEN,USBHLPEN" "0,1" bitfld.long 0x1C 20. "CRC1LPEN,CRC1LPEN" "0,1" newline bitfld.long 0x1C 17. "SDMMC2LPEN,SDMMC2LPEN" "0,1" bitfld.long 0x1C 16. "SDMMC1LPEN,SDMMC1LPEN" "0,1" newline bitfld.long 0x1C 14. "QSPILPEN,QSPILPEN" "0,1" bitfld.long 0x1C 12. "FMCLPEN,FMCLPEN" "0,1" newline bitfld.long 0x1C 11. "ETHSTPEN,ETHSTPEN" "0,1" bitfld.long 0x1C 10. "ETHMACLPEN,ETHMACLPEN" "0,1" newline bitfld.long 0x1C 9. "ETHRXLPEN,ETHRXLPEN" "0,1" bitfld.long 0x1C 8. "ETHTXLPEN,ETHTXLPEN" "0,1" newline bitfld.long 0x1C 7. "ETHCKLPEN,ETHCKLPEN" "0,1" bitfld.long 0x1C 5. "GPULPEN,GPULPEN" "0,1" newline bitfld.long 0x1C 0. "MDMALPEN,MDMALPEN" "0,1" line.long 0x20 "RCC_MP_TZAHB6LPENSETR,This register is used by the MCU in order to clear the PERxLPEN bits If TZEN = . this register can only be modified in secure mode." bitfld.long 0x20 0. "MDMALPEN,MDMALPEN" "0,1" line.long 0x24 "RCC_MP_TZAHB6LPENCLRR,This register is used by the MCU in order to clear the PERxLPEN bits If TZEN = . this register can only be modified in secure mode." bitfld.long 0x24 0. "MDMALPEN,MDMALPEN" "0,1" group.long 0x380++0x1F line.long 0x0 "RCC_MC_APB4LPENSETR,This register is used by the MCU in order to set the PERxLPEN bit." bitfld.long 0x0 21. "STGENROSTPEN,STGENROSTPEN" "0,1" bitfld.long 0x0 20. "STGENROLPEN,STGENROLPEN" "0,1" newline bitfld.long 0x0 16. "USBPHYLPEN,USBPHYLPEN" "0,1" bitfld.long 0x0 8. "DDRPERFMLPEN,DDRPERFMLPEN" "0,1" newline bitfld.long 0x0 4. "DSILPEN,DSILPEN" "0,1" bitfld.long 0x0 0. "LTDCLPEN,LTDCLPEN" "0,1" line.long 0x4 "RCC_MC_APB4LPENCLRR,This register is used by the MCU in order to clear the PERxLPEN bit" bitfld.long 0x4 21. "STGENROSTPEN,STGENROSTPEN" "0,1" bitfld.long 0x4 20. "STGENROLPEN,STGENROLPEN" "0,1" newline bitfld.long 0x4 16. "USBPHYLPEN,USBPHYLPEN" "0,1" bitfld.long 0x4 8. "DDRPERFMLPEN,DDRPERFMLPEN" "0,1" newline bitfld.long 0x4 4. "DSILPEN,DSILPEN" "0,1" bitfld.long 0x4 0. "LTDCLPEN,LTDCLPEN" "0,1" line.long 0x8 "RCC_MC_APB5LPENSETR,This register is used by the MCU in order to set the PERxLPEN bit." bitfld.long 0x8 21. "STGENSTPEN,STGENSTPEN" "0,1" bitfld.long 0x8 20. "STGENLPEN,STGENLPEN" "0,1" newline bitfld.long 0x8 16. "BSECLPEN,BSECLPEN" "0,1" bitfld.long 0x8 13. "TZPCLPEN,TZPCLPEN" "0,1" newline bitfld.long 0x8 12. "TZC2LPEN,TZC2LPEN" "0,1" bitfld.long 0x8 11. "TZC1LPEN,TZC1LPEN" "0,1" newline bitfld.long 0x8 8. "RTCAPBLPEN,RTCAPBLPEN" "0,1" bitfld.long 0x8 4. "USART1LPEN,USART1LPEN" "0,1" newline bitfld.long 0x8 3. "I2C6LPEN,I2C6LPEN" "0,1" bitfld.long 0x8 2. "I2C4LPEN,I2C4LPEN" "0,1" newline bitfld.long 0x8 0. "SPI6LPEN,SPI6LPEN" "0,1" line.long 0xC "RCC_MC_APB5LPENCLRR,This register is used by the MCU in order to clear the PERxLPEN bit" bitfld.long 0xC 21. "STGENSTPEN,STGENSTPEN" "0,1" bitfld.long 0xC 20. "STGENLPEN,STGENLPEN" "0,1" newline bitfld.long 0xC 16. "BSECLPEN,BSECLPEN" "0,1" bitfld.long 0xC 13. "TZPCLPEN,TZPCLPEN" "0,1" newline bitfld.long 0xC 12. "TZC2LPEN,TZC2LPEN" "0,1" bitfld.long 0xC 11. "TZC1LPEN,TZC1LPEN" "0,1" newline bitfld.long 0xC 8. "RTCAPBLPEN,RTCAPBLPEN" "0,1" bitfld.long 0xC 4. "USART1LPEN,USART1LPEN" "0,1" newline bitfld.long 0xC 3. "I2C6LPEN,I2C6LPEN" "0,1" bitfld.long 0xC 2. "I2C4LPEN,I2C4LPEN" "0,1" newline bitfld.long 0xC 0. "SPI6LPEN,SPI6LPEN" "0,1" line.long 0x10 "RCC_MC_AHB5LPENSETR,This register is used by the MCU in order to set the PERxLPEN bit. If TZEN = . this register can only be modified in secure mode." bitfld.long 0x10 8. "BKPSRAMLPEN,BKPSRAMLPEN" "0,1" bitfld.long 0x10 6. "RNG1LPEN,RNG1LPEN" "0,1" newline bitfld.long 0x10 5. "HASH1LPEN,HASH1LPEN" "0,1" bitfld.long 0x10 4. "CRYP1LPEN,CRYP1LPEN" "0,1" newline bitfld.long 0x10 0. "GPIOZLPEN,GPIOZLPEN" "0,1" line.long 0x14 "RCC_MC_AHB5LPENCLRR,This register is used by the MCU in order to clear the PERxLPEN bit If TZEN = . this register can only be modified in secure mode." bitfld.long 0x14 8. "BKPSRAMLPEN,BKPSRAMLPEN" "0,1" bitfld.long 0x14 6. "RNG1LPEN,RNG1LPEN" "0,1" newline bitfld.long 0x14 5. "HASH1LPEN,HASH1LPEN" "0,1" bitfld.long 0x14 4. "CRYP1LPEN,CRYP1LPEN" "0,1" newline bitfld.long 0x14 0. "GPIOZLPEN,GPIOZLPEN" "0,1" line.long 0x18 "RCC_MC_AHB6LPENSETR,This register is used by the MCU in order to set the PERxLPEN bit." bitfld.long 0x18 24. "USBHLPEN,USBHLPEN" "0,1" bitfld.long 0x18 20. "CRC1LPEN,CRC1LPEN" "0,1" newline bitfld.long 0x18 17. "SDMMC2LPEN,SDMMC2LPEN" "0,1" bitfld.long 0x18 16. "SDMMC1LPEN,SDMMC1LPEN" "0,1" newline bitfld.long 0x18 14. "QSPILPEN,QSPILPEN" "0,1" bitfld.long 0x18 12. "FMCLPEN,FMCLPEN" "0,1" newline bitfld.long 0x18 11. "ETHSTPEN,ETHSTPEN" "0,1" bitfld.long 0x18 10. "ETHMACLPEN,ETHMACLPEN" "0,1" newline bitfld.long 0x18 9. "ETHRXLPEN,ETHRXLPEN" "0,1" bitfld.long 0x18 8. "ETHTXLPEN,ETHTXLPEN" "0,1" newline bitfld.long 0x18 7. "ETHCKLPEN,ETHCKLPEN" "0,1" bitfld.long 0x18 5. "GPULPEN,GPULPEN" "0,1" newline bitfld.long 0x18 0. "MDMALPEN,MDMALPEN" "0,1" line.long 0x1C "RCC_MC_AHB6LPENCLRR,This register is used by the MCU in order to clear the PERxLPEN bit" bitfld.long 0x1C 24. "USBHLPEN,USBHLPEN" "0,1" bitfld.long 0x1C 20. "CRC1LPEN,CRC1LPEN" "0,1" newline bitfld.long 0x1C 17. "SDMMC2LPEN,SDMMC2LPEN" "0,1" bitfld.long 0x1C 16. "SDMMC1LPEN,SDMMC1LPEN" "0,1" newline bitfld.long 0x1C 14. "QSPILPEN,QSPILPEN" "0,1" bitfld.long 0x1C 12. "FMCLPEN,FMCLPEN" "0,1" newline bitfld.long 0x1C 11. "ETHSTPEN,ETHSTPEN" "0,1" bitfld.long 0x1C 10. "ETHMACLPEN,ETHMACLPEN" "0,1" newline bitfld.long 0x1C 9. "ETHRXLPEN,ETHRXLPEN" "0,1" bitfld.long 0x1C 8. "ETHTXLPEN,ETHTXLPEN" "0,1" newline bitfld.long 0x1C 7. "ETHCKLPEN,ETHCKLPEN" "0,1" bitfld.long 0x1C 5. "GPULPEN,GPULPEN" "0,1" newline bitfld.long 0x1C 0. "MDMALPEN,MDMALPEN" "0,1" group.long 0x400++0x23 line.long 0x0 "RCC_BR_RSTSCLRR,This register is used by the BOOTROM to check the reset source. Writing has no effect. reading will return the effective values of the corresponding bits. Writing a clears the corresponding bit to . In order to identify the reset.." bitfld.long 0x0 14. "MPUP1RSTF,MPUP1RSTF" "0,1" bitfld.long 0x0 13. "MPUP0RSTF,MPUP0RSTF" "0,1" newline bitfld.long 0x0 9. "IWDG2RSTF,IWDG2RSTF" "0,1" bitfld.long 0x0 8. "IWDG1RSTF,IWDG1RSTF" "0,1" newline bitfld.long 0x0 7. "MCSYSRSTF,MCSYSRSTF" "0,1" bitfld.long 0x0 6. "MPSYSRSTF,MPSYSRSTF" "0,1" newline bitfld.long 0x0 4. "VCORERSTF,VCORERSTF" "0,1" bitfld.long 0x0 3. "HCSSRSTF,HCSSRSTF" "0,1" newline bitfld.long 0x0 2. "PADRSTF,PADRSTF" "0,1" bitfld.long 0x0 1. "BORRSTF,BORRSTF" "0,1" newline bitfld.long 0x0 0. "PORRSTF,PORRSTF" "0,1" line.long 0x4 "RCC_MP_GRSTCSETR,This register is used by the MPU in order to generate either a MCU reset or a system reset or a reset of one of the two MPU processors. Writing has no effect. reading returns the effective values of the corresponding bits. Writing a.." bitfld.long 0x4 5. "MPUP1RST,MPUP1RST" "0,1" bitfld.long 0x4 4. "MPUP0RST,MPUP0RST" "0,1" newline bitfld.long 0x4 1. "MCURST,MCURST" "0,1" bitfld.long 0x4 0. "MPSYSRST,MPSYSRST" "0,1" line.long 0x8 "RCC_MP_RSTSCLRR,This register is used by the MPU to check the reset source. This register is updated by the BOOTROM code. after a power-on reset (por_rst). a system reset (nreset). or an exit from Standby or CStandby.Writing has no effect. reading will.." bitfld.long 0x8 15. "SPARE,SPARE" "0,1" bitfld.long 0x8 14. "MPUP1RSTF,MPUP1RSTF" "0,1" newline bitfld.long 0x8 13. "MPUP0RSTF,MPUP0RSTF" "0,1" bitfld.long 0x8 12. "CSTDBYRSTF,CSTDBYRSTF" "0,1" newline bitfld.long 0x8 11. "STDBYRSTF,STDBYRSTF" "0,1" bitfld.long 0x8 9. "IWDG2RSTF,IWDG2RSTF" "0,1" newline bitfld.long 0x8 8. "IWDG1RSTF,IWDG1RSTF" "0,1" bitfld.long 0x8 7. "MCSYSRSTF,MCSYSRSTF" "0,1" newline bitfld.long 0x8 6. "MPSYSRSTF,MPSYSRSTF" "0,1" bitfld.long 0x8 4. "VCORERSTF,VCORERSTF" "0,1" newline bitfld.long 0x8 3. "HCSSRSTF,HCSSRSTF" "0,1" bitfld.long 0x8 2. "PADRSTF,PADRSTF" "0,1" newline bitfld.long 0x8 1. "BORRSTF,BORRSTF" "0,1" bitfld.long 0x8 0. "PORRSTF,PORRSTF" "0,1" line.long 0xC "RCC_MP_IWDGFZSETR,This register is used by the BOOTROM in order to freeze the IWDGs clocks. After a system reset or Standby reset (nreset). or a CStandby reset (cstby_rst) the MPU is allowed to write it once.Writing has no effect. reading will return.." bitfld.long 0xC 1. "FZ_IWDG2,FZ_IWDG2" "0,1" bitfld.long 0xC 0. "FZ_IWDG1,FZ_IWDG1" "0,1" line.long 0x10 "RCC_MP_IWDGFZCLRR,This register is used by the BOOTROM in order to unfreeze the IWDGs clocks. Writing has no effect. reading will return the effective values of the corresponding bits. Writing a clears the corresponding bit to . If TZEN = . this.." bitfld.long 0x10 1. "FZ_IWDG2,FZ_IWDG2" "0,1" bitfld.long 0x10 0. "FZ_IWDG1,FZ_IWDG1" "0,1" line.long 0x14 "RCC_MP_CIER,This register shall be used by the MPU to control the interrupt source enable. Refer to Section10.5: RCC interrupts for more details. If TZEN = . this register can only be modified in secure mode." bitfld.long 0x14 20. "WKUPIE,WKUPIE" "0,1" bitfld.long 0x14 16. "LSECSSIE,LSECSSIE" "0,1" newline bitfld.long 0x14 11. "PLL4DYIE,PLL4DYIE" "0,1" bitfld.long 0x14 10. "PLL3DYIE,PLL3DYIE" "0,1" newline bitfld.long 0x14 9. "PLL2DYIE,PLL2DYIE" "0,1" bitfld.long 0x14 8. "PLL1DYIE,PLL1DYIE" "0,1" newline bitfld.long 0x14 4. "CSIRDYIE,CSIRDYIE" "0,1" bitfld.long 0x14 3. "HSERDYIE,HSERDYIE" "0,1" newline bitfld.long 0x14 2. "HSIRDYIE,HSIRDYIE" "0,1" bitfld.long 0x14 1. "LSERDYIE,LSERDYIE" "0,1" newline bitfld.long 0x14 0. "LSIRDYIE,LSIRDYIE" "0,1" line.long 0x18 "RCC_MP_CIFR,This register shall be used by the MPU in order to read and clear the interrupt flags.Writing has no effect. writing will clear the corresponding flag.Refer to Section10.5: RCC interrupts for more details. If TZEN = . this register can only.." bitfld.long 0x18 20. "WKUPF,WKUPF" "0,1" bitfld.long 0x18 16. "LSECSSF,LSECSSF" "0,1" newline bitfld.long 0x18 11. "PLL4DYF,PLL4DYF" "0,1" bitfld.long 0x18 10. "PLL3DYF,PLL3DYF" "0,1" newline bitfld.long 0x18 9. "PLL2DYF,PLL2DYF" "0,1" bitfld.long 0x18 8. "PLL1DYF,PLL1DYF" "0,1" newline bitfld.long 0x18 4. "CSIRDYF,CSIRDYF" "0,1" bitfld.long 0x18 3. "HSERDYF,HSERDYF" "0,1" newline bitfld.long 0x18 2. "HSIRDYF,HSIRDYF" "0,1" bitfld.long 0x18 1. "LSERDYF,LSERDYF" "0,1" newline bitfld.long 0x18 0. "LSIRDYF,LSIRDYF" "0,1" line.long 0x1C "RCC_PWRLPDLYCR,This register is used to program the delay between the moment where the system exits from one of the Stop modes. and the moment where it is allowed to enable the PLLs and provide a clock to bridges and processors. If TZEN = . this register.." bitfld.long 0x1C 24. "MCTMPSKP,MCTMPSKP" "0,1" hexmask.long.tbyte 0x1C 0.--21. 1. "PWRLP_DLY,PWRLP_DLY" line.long 0x20 "RCC_MP_RSTSSETR,This register is dedicated to the BOOTROM code in order to update the reset source. This register is updated by the BOOTROM code. after a power-on reset (por_rst). a system reset (nreset). or an exit from Standby or CStandby. The.." bitfld.long 0x20 15. "SPARE,SPARE" "0,1" bitfld.long 0x20 14. "MPUP1RSTF,MPUP1RSTF" "0,1" newline bitfld.long 0x20 13. "MPUP0RSTF,MPUP0RSTF" "0,1" bitfld.long 0x20 12. "CSTDBYRSTF,CSTDBYRSTF" "0,1" newline bitfld.long 0x20 11. "STDBYRSTF,STDBYRSTF" "0,1" bitfld.long 0x20 9. "IWDG2RSTF,IWDG2RSTF" "0,1" newline bitfld.long 0x20 8. "IWDG1RSTF,IWDG1RSTF" "0,1" bitfld.long 0x20 7. "MCSYSRSTF,MCSYSRSTF" "0,1" newline bitfld.long 0x20 6. "MPSYSRSTF,MPSYSRSTF" "0,1" bitfld.long 0x20 4. "VCORERSTF,VCORERSTF" "0,1" newline bitfld.long 0x20 3. "HCSSRSTF,HCSSRSTF" "0,1" bitfld.long 0x20 2. "PADRSTF,PADRSTF" "0,1" newline bitfld.long 0x20 1. "BORRSTF,BORRSTF" "0,1" bitfld.long 0x20 0. "PORRSTF,PORRSTF" "0,1" group.long 0x800++0x7 line.long 0x0 "RCC_MCO1CFGR,This register is used to select the clock generated on MCO1 output." bitfld.long 0x0 12. "MCO1ON,MCO1ON" "0,1" hexmask.long.byte 0x0 4.--7. 1. "MCO1DIV,MCO1DIV" newline bitfld.long 0x0 0.--2. "MCO1SEL,MCO1SEL" "0,1,2,3,4,5,6,7" line.long 0x4 "RCC_MCO2CFGR,This register is used to select the clock generated on MCO2 output." bitfld.long 0x4 12. "MCO2ON,MCO2ON" "0,1" hexmask.long.byte 0x4 4.--7. 1. "MCO2DIV,MCO2DIV" newline bitfld.long 0x4 0.--2. "MCO2SEL,MCO2SEL" "0,1,2,3,4,5,6,7" rgroup.long 0x808++0x3 line.long 0x0 "RCC_OCRDYR,This is a read-only access register. It contains the status flags of oscillators. Writing has no effect." bitfld.long 0x0 25. "CKREST,CKREST" "0,1" bitfld.long 0x0 24. "AXICKRDY,AXICKRDY" "0,1" newline bitfld.long 0x0 23. "MPUCKRDY,MPUCKRDY" "0,1" bitfld.long 0x0 8. "HSERDY,HSERDY" "0,1" newline bitfld.long 0x0 4. "CSIRDY,CSIRDY" "0,1" bitfld.long 0x0 2. "HSIDIVRDY,HSIDIVRDY" "0,1" newline bitfld.long 0x0 0. "HSIRDY,HSIRDY" "0,1" group.long 0x80C++0x3 line.long 0x0 "RCC_DBGCFGR,This is register contains the enable control of the debug and trace function. and the clock divider for the trace function." bitfld.long 0x0 12. "DBGRST,DBGRST" "0,1" bitfld.long 0x0 9. "TRACECKEN,TRACECKEN" "0,1" newline bitfld.long 0x0 8. "DBGCKEN,DBGCKEN" "0,1" bitfld.long 0x0 0.--2. "TRACEDIV,TRACEDIV" "0,1,2,3,4,5,6,7" group.long 0x820++0x1F line.long 0x0 "RCC_RCK3SELR,This register is used to select the reference clock for PLL3. If TZEN = MCKPROT = . this register can only be modified in secure mode." rbitfld.long 0x0 31. "PLL3SRCRDY,PLL3SRCRDY" "0,1" bitfld.long 0x0 0.--1. "PLL3SRC,PLL3SRC" "0,1,2,3" line.long 0x4 "RCC_RCK4SELR,This register is used to select the reference clock for PLL4." rbitfld.long 0x4 31. "PLL4SRCRDY,PLL4SRCRDY" "0,1" bitfld.long 0x4 0.--1. "PLL4SRC,PLL4SRC" "0,1,2,3" line.long 0x8 "RCC_TIMG1PRER,This register is used to control the prescaler value of timers located into APB1 domain. It concerns TIM2. TIM3. TIM4. TIM5. TIM6. TIM7. TIM12. TIM13 and TIM14. Refer to Section: Sub-system clock generation for additional information." rbitfld.long 0x8 31. "TIMG1PRERDY,TIMG1PRERDY" "0,1" bitfld.long 0x8 0. "TIMG1PRE,TIMG1PRE" "0,1" line.long 0xC "RCC_TIMG2PRER,This register is used to control the prescaler value of timers located into APB2 domain. It concerns TIM1. TIM8. TIM15. TIM16. and TIM17. Refer to Section: Sub-system clock generation for additional information." rbitfld.long 0xC 31. "TIMG2PRERDY,TIMG2PRERDY" "0,1" bitfld.long 0xC 0. "TIMG2PRE,TIMG2PRE" "0,1" line.long 0x10 "RCC_MCUDIVR,This register is used to control the MCU sub-system clock prescaler. Refer to Section: Sub-system clock generation for additional information. If TZEN = . this register can only be modified in secure mode." rbitfld.long 0x10 31. "MCUDIVRDY,MCUDIVRDY" "0,1" hexmask.long.byte 0x10 0.--3. 1. "MCUDIV,MCUDIV" line.long 0x14 "RCC_APB1DIVR,This register is used to control the APB1 clock prescaler. Refer to section Section1.4.6.3: Sub-System Clock Generation for additional information." rbitfld.long 0x14 31. "APB1DIVRDY,APB1DIVRDY" "0,1" bitfld.long 0x14 0.--2. "APB1DIV,APB1DIV" "0,1,2,3,4,5,6,7" line.long 0x18 "RCC_APB2DIVR,This register is used to control the APB2 clock prescaler. Refer to Section: Sub-system clock generation for additional information." rbitfld.long 0x18 31. "APB2DIVRDY,APB2DIVRDY" "0,1" bitfld.long 0x18 0.--2. "APB2DIV,APB2DIV" "0,1,2,3,4,5,6,7" line.long 0x1C "RCC_APB3DIVR,This register is used to control the APB3 clock prescaler. Refer to Section: Sub-system clock generation for additional information." rbitfld.long 0x1C 31. "APB3DIVRDY,APB3DIVRDY" "0,1" bitfld.long 0x1C 0.--2. "APB3DIV,APB3DIV" "0,1,2,3,4,5,6,7" group.long 0x880++0x27 line.long 0x0 "RCC_PLL3CR,This register is used to control the PLL3. If TZEN = MCKPROT = . this register can only be modified in secure mode." bitfld.long 0x0 6. "DIVREN,DIVREN" "0,1" bitfld.long 0x0 5. "DIVQEN,DIVQEN" "0,1" newline bitfld.long 0x0 4. "DIVPEN,DIVPEN" "0,1" bitfld.long 0x0 2. "SSCG_CTRL,SSCG_CTRL" "0,1" newline rbitfld.long 0x0 1. "PLL3RDY,PLL3RDY" "0,1" bitfld.long 0x0 0. "PLLON,PLLON" "0,1" line.long 0x4 "RCC_PLL3CFGR1,This register is used to configure the PLL3. If TZEN = MCKPROT = . this register can only be modified in secure mode." bitfld.long 0x4 24.--25. "IFRGE,IFRGE" "0,1,2,3" hexmask.long.byte 0x4 16.--21. 1. "DIVM3,DIVM3" newline hexmask.long.word 0x4 0.--8. 1. "DIVN,DIVN" line.long 0x8 "RCC_PLL3CFGR2,This register is used to configure the PLL3. If TZEN = MCKPROT = . this register can only be modified in secure mode." hexmask.long.byte 0x8 16.--22. 1. "DIVR,DIVR" hexmask.long.byte 0x8 8.--14. 1. "DIVQ,DIVQ" newline hexmask.long.byte 0x8 0.--6. 1. "DIVP,DIVP" line.long 0xC "RCC_PLL3FRACR,This register is used to fine-tune the frequency of the PLL3 VCO. If TZEN = MCKPROT = . this register can only be modified in secure mode." bitfld.long 0xC 16. "FRACLE,FRACLE" "0,1" hexmask.long.word 0xC 3.--15. 1. "FRACV,FRACV" line.long 0x10 "RCC_PLL3CSGR,This register is used to configure the PLL3.It is not recommended to change the content of this register when the PLL3 is enabled (PLLON = ). Refer to Section: Using the PLLs in spread spectrum mode for details. If TZEN = MCKPROT = . this.." hexmask.long.word 0x10 16.--30. 1. "INC_STEP,INC_STEP" bitfld.long 0x10 15. "SSCG_MODE,SSCG_MODE" "0,1" newline bitfld.long 0x10 14. "RPDFN_DIS,RPDFN_DIS" "0,1" bitfld.long 0x10 13. "TPDFN_DIS,TPDFN_DIS" "0,1" newline hexmask.long.word 0x10 0.--12. 1. "MOD_PER,MOD_PER" line.long 0x14 "RCC_PLL4CR,This register is used to control the PLL4." bitfld.long 0x14 6. "DIVREN,DIVREN" "0,1" bitfld.long 0x14 5. "DIVQEN,DIVQEN" "0,1" newline bitfld.long 0x14 4. "DIVPEN,DIVPEN" "0,1" bitfld.long 0x14 2. "SSCG_CTRL,SSCG_CTRL" "0,1" newline rbitfld.long 0x14 1. "PLL4RDY,PLL4RDY" "0,1" bitfld.long 0x14 0. "PLLON,PLLON" "0,1" line.long 0x18 "RCC_PLL4CFGR1,This register is used to configure the PLL4." bitfld.long 0x18 24.--25. "IFRGE,IFRGE" "0,1,2,3" hexmask.long.byte 0x18 16.--21. 1. "DIVM4,DIVM4" newline hexmask.long.word 0x18 0.--8. 1. "DIVN,DIVN" line.long 0x1C "RCC_PLL4CFGR2,This register is used to configure the PLL4." hexmask.long.byte 0x1C 16.--22. 1. "DIVR,DIVR" hexmask.long.byte 0x1C 8.--14. 1. "DIVQ,DIVQ" newline hexmask.long.byte 0x1C 0.--6. 1. "DIVP,DIVP" line.long 0x20 "RCC_PLL4FRACR,This register is used to fine-tune the frequency of the PLL4 VCO." bitfld.long 0x20 16. "FRACLE,FRACLE" "0,1" hexmask.long.word 0x20 3.--15. 1. "FRACV,FRACV" line.long 0x24 "RCC_PLL4CSGR,This register is used to configure the PLL4.It is not recommended to change the content of this register when the PLL4 is enabled (PLLON = ). Refer to Section: Using the PLLs in spread spectrum mode for details. If TZEN = MCKPROT = . this.." hexmask.long.word 0x24 16.--30. 1. "INC_STEP,INC_STEP" bitfld.long 0x24 15. "SSCG_MODE,SSCG_MODE" "0,1" newline bitfld.long 0x24 14. "RPDFN_DIS,RPDFN_DIS" "0,1" bitfld.long 0x24 13. "TPDFN_DIS,TPDFN_DIS" "0,1" newline hexmask.long.word 0x24 0.--12. 1. "MOD_PER,MOD_PER" group.long 0x8C0++0x47 line.long 0x0 "RCC_I2C12CKSELR,This register is used to control the selection of the kernel clock for the I2C1 and I2C2. Note that changing the clock source on-the-fly is allowed. and will not generate any timing violation. however the user has to ensure that both the.." bitfld.long 0x0 0.--2. "I2C12SRC,I2C12SRC" "0,1,2,3,4,5,6,7" line.long 0x4 "RCC_I2C35CKSELR,This register is used to control the selection of the kernel clock for the I2C3 and I2C5. Note that changing the clock source on-the-fly is allowed. and will not generate any timing violation. however the user has to ensure that both the.." bitfld.long 0x4 0.--2. "I2C35SRC,I2C35SRC" "0,1,2,3,4,5,6,7" line.long 0x8 "RCC_SAI1CKSELR,This register is used to control the selection of the kernel clock for the SAI1 and DFSDM audio clock. Note that changing the clock source on-the-fly is allowed. and will not generate any timing violation. however the user has to ensure.." bitfld.long 0x8 0.--2. "SAI1SRC,SAI1SRC" "0,1,2,3,4,5,6,7" line.long 0xC "RCC_SAI2CKSELR,This register is used to control the selection of the kernel clock for the SAI2. Note that changing the clock source on-the-fly is allowed. and will not generate any timing violation. however the user has to ensure that both the previous.." bitfld.long 0xC 0.--2. "SAI2SRC,SAI2SRC" "0,1,2,3,4,5,6,7" line.long 0x10 "RCC_SAI3CKSELR,This register is used to control the selection of the kernel clock for the SAI3. Note that changing the clock source on-the-fly is allowed. and will not generate any timing violation. however the user has to ensure that both the previous.." bitfld.long 0x10 0.--2. "SAI3SRC,SAI3SRC" "0,1,2,3,4,5,6,7" line.long 0x14 "RCC_SAI4CKSELR,This register is used to control the selection of the kernel clock for the SAI4. Note that changing the clock source on-the-fly is allowed. and will not generate any timing violation. however the user has to ensure that both the previous.." bitfld.long 0x14 0.--2. "SAI4SRC,SAI4SRC" "0,1,2,3,4,5,6,7" line.long 0x18 "RCC_SPI2S1CKSELR,This register is used to control the selection of the kernel clock for the SPI/I2S1. Note that changing the clock source on-the-fly is allowed. and will not generate any timing violation. however the user has to ensure that both the.." bitfld.long 0x18 0.--2. "SPI1SRC,SPI1SRC" "0,1,2,3,4,5,6,7" line.long 0x1C "RCC_SPI2S23CKSELR,This register is used to control the selection of the kernel clock for the SPI/I2S2.3. Note that changing the clock source on-the-fly is allowed. and will not generate any timing violation. however the user has to ensure that both the.." bitfld.long 0x1C 0.--2. "SPI23SRC,SPI23SRC" "0,1,2,3,4,5,6,7" line.long 0x20 "RCC_SPI45CKSELR,This register is used to control the selection of the kernel clock for the SPI4.5. Note that changing the clock source on-the-fly is allowed. and will not generate any timing violation. however the user has to ensure that both the.." bitfld.long 0x20 0.--2. "SPI45SRC,SPI45SRC" "0,1,2,3,4,5,6,7" line.long 0x24 "RCC_UART6CKSELR,This register is used to control the selection of the kernel clock for the USART6. Note that changing the clock source on-the-fly is allowed. and will not generate any timing violation. however the user has to ensure that both the.." bitfld.long 0x24 0.--2. "UART6SRC,UART6SRC" "0,1,2,3,4,5,6,7" line.long 0x28 "RCC_UART24CKSELR,This register is used to control the selection of the kernel clock for the USART2 and UART4. Note that changing the clock source on-the-fly is allowed. and will not generate any timing violation. however the user has to ensure that both.." bitfld.long 0x28 0.--2. "UART24SRC,UART24SRC" "0,1,2,3,4,5,6,7" line.long 0x2C "RCC_UART35CKSELR,This register is used to control the selection of the kernel clock for the USART3 and UART5. Note that changing the clock source on-the-fly is allowed. and will not generate any timing violation. however the user has to ensure that both.." bitfld.long 0x2C 0.--2. "UART35SRC,UART35SRC" "0,1,2,3,4,5,6,7" line.long 0x30 "RCC_UART78CKSELR,This register is used to control the selection of the kernel clock for the UART7 and UART8. Note that changing the clock source on-the-fly is allowed. and will not generate any timing violation. however the user has to ensure that both.." bitfld.long 0x30 0.--2. "UART78SRC,UART78SRC" "0,1,2,3,4,5,6,7" line.long 0x34 "RCC_SDMMC12CKSELR,This register is used to control the selection of the kernel clock for the SDMMC1 and SDMMC2. Note that changing the clock source on-the-fly is allowed. and will not generate any timing violation. however the user has to ensure that.." bitfld.long 0x34 0.--2. "SDMMC12SRC,SDMMC12SRC" "0,1,2,3,4,5,6,7" line.long 0x38 "RCC_SDMMC3CKSELR,This register is used to control the selection of the kernel clock for the SDMMC3. Note that changing the clock source on-the-fly is allowed. and will not generate any timing violation. however the user has to ensure that both the.." bitfld.long 0x38 0.--2. "SDMMC3SRC,SDMMC3SRC" "0,1,2,3,4,5,6,7" line.long 0x3C "RCC_ETHCKSELR,This register is used to control the selection of the kernel clock for the ETH block. Note that changing the clock source on-the-fly is allowed. and will not generate any timing violation. however the user has to ensure that both the.." hexmask.long.byte 0x3C 4.--7. 1. "ETHPTPDIV,ETHPTPDIV" bitfld.long 0x3C 0.--1. "ETHSRC,ETHSRC" "0,1,2,3" line.long 0x40 "RCC_QSPICKSELR,This register is used to control the selection of the kernel clock for the QUADSPI. Note that changing the clock source on-the-fly is allowed. and will not generate any timing violation. however the user has to ensure that both the.." bitfld.long 0x40 0.--1. "QSPISRC,QSPISRC" "0,1,2,3" line.long 0x44 "RCC_FMCCKSELR,This register is used to control the selection of the kernel clock for the FMC block. Note that changing the clock source on-the-fly is allowed. and will not generate any timing violation. however the user has to ensure that both the.." bitfld.long 0x44 0.--1. "FMCSRC,FMCSRC" "0,1,2,3" group.long 0x90C++0x3 line.long 0x0 "RCC_FDCANCKSELR,This register is used to control the selection of the kernel clock for the FDCAN block. Note that changing the clock source on-the-fly is allowed. and will not generate any timing violation. however the user has to ensure that both the.." bitfld.long 0x0 0.--1. "FDCANSRC,FDCANSRC" "0,1,2,3" group.long 0x914++0x23 line.long 0x0 "RCC_SPDIFCKSELR,This register is used to control the selection of the kernel clock for the SPDIFRX. Note that changing the clock source on-the-fly is allowed. and will not generate any timing violation. however the user has to ensure that both the.." bitfld.long 0x0 0.--1. "SPDIFSRC,SPDIFSRC" "0,1,2,3" line.long 0x4 "RCC_CECCKSELR,This register is used to control the selection of the kernel clock for the CEC-HDMI." bitfld.long 0x4 0.--1. "CECSRC,CECSRC" "0,1,2,3" line.long 0x8 "RCC_USBCKSELR,This register is used to control the selection of the kernel clock for the USBPHY PLL of the USB HOST and USB OTG" bitfld.long 0x8 4. "USBOSRC,USBOSRC" "0,1" bitfld.long 0x8 0.--1. "USBPHYSRC,USBPHYSRC" "0,1,2,3" line.long 0xC "RCC_RNG2CKSELR,This register is used to control the selection of the kernel clock for the RNG2." bitfld.long 0xC 0.--1. "RNG2SRC,RNG2SRC" "0,1,2,3" line.long 0x10 "RCC_DSICKSELR,This register is used to control the selection of the kernel clock for the DSI block." bitfld.long 0x10 0. "DSISRC,DSISRC" "0,1" line.long 0x14 "RCC_ADCCKSELR,This register is used to control the selection of the kernel clock for the ADC block." bitfld.long 0x14 0.--1. "ADCSRC,ADCSRC" "0,1,2,3" line.long 0x18 "RCC_LPTIM45CKSELR,This register is used to control the selection of the kernel clock for the LPTIM4 and LPTIM5 blocks." bitfld.long 0x18 0.--2. "LPTIM45SRC,LPTIM45SRC" "0,1,2,3,4,5,6,7" line.long 0x1C "RCC_LPTIM23CKSELR,This register is used to control the selection of the kernel clock for the LPTIM2 and LPTIM3 blocks." bitfld.long 0x1C 0.--2. "LPTIM23SRC,LPTIM23SRC" "0,1,2,3,4,5,6,7" line.long 0x20 "RCC_LPTIM1CKSELR,This register is used to control the selection of the kernel clock for the LPTIM1 block." bitfld.long 0x20 0.--2. "LPTIM1SRC,LPTIM1SRC" "0,1,2,3,4,5,6,7" group.long 0x980++0x2F line.long 0x0 "RCC_APB1RSTSETR,This register is used to activate the reset of the corresponding peripheral." bitfld.long 0x0 31. "MDIOSRST,MDIOSRST" "0,1" bitfld.long 0x0 29. "DAC12RST,DAC12RST" "0,1" newline bitfld.long 0x0 27. "CECRST,CECRST" "0,1" bitfld.long 0x0 26. "SPDIFRST,SPDIFRST" "0,1" newline bitfld.long 0x0 24. "I2C5RST,I2C5RST" "0,1" bitfld.long 0x0 23. "I2C3RST,I2C3RST" "0,1" newline bitfld.long 0x0 22. "I2C2RST,I2C2RST" "0,1" bitfld.long 0x0 21. "I2C1RST,I2C1RST" "0,1" newline bitfld.long 0x0 19. "UART8RST,UART8RST" "0,1" bitfld.long 0x0 18. "UART7RST,UART7RST" "0,1" newline bitfld.long 0x0 17. "UART5RST,UART5RST" "0,1" bitfld.long 0x0 16. "UART4RST,UART4RST" "0,1" newline bitfld.long 0x0 15. "USART3RST,USART3RST" "0,1" bitfld.long 0x0 14. "USART2RST,USART2RST" "0,1" newline bitfld.long 0x0 12. "SPI3RST,SPI3RST" "0,1" bitfld.long 0x0 11. "SPI2RST,SPI2RST" "0,1" newline bitfld.long 0x0 9. "LPTIM1RST,LPTIM1RST" "0,1" bitfld.long 0x0 8. "TIM14RST,TIM14RST" "0,1" newline bitfld.long 0x0 7. "TIM13RST,TIM13RST" "0,1" bitfld.long 0x0 6. "TIM12RST,TIM12RST" "0,1" newline bitfld.long 0x0 5. "TIM7RST,TIM7RST" "0,1" bitfld.long 0x0 4. "TIM6RST,TIM6RST" "0,1" newline bitfld.long 0x0 3. "TIM5RST,TIM5RST" "0,1" bitfld.long 0x0 2. "TIM4RST,TIM4RST" "0,1" newline bitfld.long 0x0 1. "TIM3RST,TIM3RST" "0,1" bitfld.long 0x0 0. "TIM2RST,TIM2RST" "0,1" line.long 0x4 "RCC_APB1RSTCLRR,This register is used to release the reset of the corresponding peripheral." bitfld.long 0x4 31. "MDIOSRST,MDIOSRST" "0,1" bitfld.long 0x4 29. "DAC12RST,DAC12RST" "0,1" newline bitfld.long 0x4 27. "CECRST,CECRST" "0,1" bitfld.long 0x4 26. "SPDIFRST,SPDIFRST" "0,1" newline bitfld.long 0x4 24. "I2C5RST,I2C5RST" "0,1" bitfld.long 0x4 23. "I2C3RST,I2C3RST" "0,1" newline bitfld.long 0x4 22. "I2C2RST,I2C2RST" "0,1" bitfld.long 0x4 21. "I2C1RST,I2C1RST" "0,1" newline bitfld.long 0x4 19. "UART8RST,UART8RST" "0,1" bitfld.long 0x4 18. "UART7RST,UART7RST" "0,1" newline bitfld.long 0x4 17. "UART5RST,UART5RST" "0,1" bitfld.long 0x4 16. "UART4RST,UART4RST" "0,1" newline bitfld.long 0x4 15. "USART3RST,USART3RST" "0,1" bitfld.long 0x4 14. "USART2RST,USART2RST" "0,1" newline bitfld.long 0x4 12. "SPI3RST,SPI3RST" "0,1" bitfld.long 0x4 11. "SPI2RST,SPI2RST" "0,1" newline bitfld.long 0x4 9. "LPTIM1RST,LPTIM1RST" "0,1" bitfld.long 0x4 8. "TIM14RST,TIM14RST" "0,1" newline bitfld.long 0x4 7. "TIM13RST,TIM13RST" "0,1" bitfld.long 0x4 6. "TIM12RST,TIM12RST" "0,1" newline bitfld.long 0x4 5. "TIM7RST,TIM7RST" "0,1" bitfld.long 0x4 4. "TIM6RST,TIM6RST" "0,1" newline bitfld.long 0x4 3. "TIM5RST,TIM5RST" "0,1" bitfld.long 0x4 2. "TIM4RST,TIM4RST" "0,1" newline bitfld.long 0x4 1. "TIM3RST,TIM3RST" "0,1" bitfld.long 0x4 0. "TIM2RST,TIM2RST" "0,1" line.long 0x8 "RCC_APB2RSTSETR,This register is used to activate the reset of the corresponding peripheral." bitfld.long 0x8 24. "FDCANRST,FDCANRST" "0,1" bitfld.long 0x8 20. "DFSDMRST,DFSDMRST" "0,1" newline bitfld.long 0x8 18. "SAI3RST,SAI3RST" "0,1" bitfld.long 0x8 17. "SAI2RST,SAI2RST" "0,1" newline bitfld.long 0x8 16. "SAI1RST,SAI1RST" "0,1" bitfld.long 0x8 13. "USART6RST,USART6RST" "0,1" newline bitfld.long 0x8 10. "SPI5RST,SPI5RST" "0,1" bitfld.long 0x8 9. "SPI4RST,SPI4RST" "0,1" newline bitfld.long 0x8 8. "SPI1RST,SPI1RST" "0,1" bitfld.long 0x8 4. "TIM17RST,TIM17RST" "0,1" newline bitfld.long 0x8 3. "TIM16RST,TIM16RST" "0,1" bitfld.long 0x8 2. "TIM15RST,TIM15RST" "0,1" newline bitfld.long 0x8 1. "TIM8RST,TIM8RST" "0,1" bitfld.long 0x8 0. "TIM1RST,TIM1RST" "0,1" line.long 0xC "RCC_APB2RSTCLRR,This register is used to release the reset of the corresponding peripheral." bitfld.long 0xC 24. "FDCANRST,FDCANRST" "0,1" bitfld.long 0xC 20. "DFSDMRST,DFSDMRST" "0,1" newline bitfld.long 0xC 18. "SAI3RST,SAI3RST" "0,1" bitfld.long 0xC 17. "SAI2RST,SAI2RST" "0,1" newline bitfld.long 0xC 16. "SAI1RST,SAI1RST" "0,1" bitfld.long 0xC 13. "USART6RST,USART6RST" "0,1" newline bitfld.long 0xC 10. "SPI5RST,SPI5RST" "0,1" bitfld.long 0xC 9. "SPI4RST,SPI4RST" "0,1" newline bitfld.long 0xC 8. "SPI1RST,SPI1RST" "0,1" bitfld.long 0xC 4. "TIM17RST,TIM17RST" "0,1" newline bitfld.long 0xC 3. "TIM16RST,TIM16RST" "0,1" bitfld.long 0xC 2. "TIM15RST,TIM15RST" "0,1" newline bitfld.long 0xC 1. "TIM8RST,TIM8RST" "0,1" bitfld.long 0xC 0. "TIM1RST,TIM1RST" "0,1" line.long 0x10 "RCC_APB3RSTSETR,This register is used to activate the reset of the corresponding peripheral." bitfld.long 0x10 16. "DTSRST,DTSRST" "0,1" bitfld.long 0x10 13. "VREFRST,VREFRST" "0,1" newline bitfld.long 0x10 11. "SYSCFGRST,SYSCFGRST" "0,1" bitfld.long 0x10 8. "SAI4RST,SAI4RST" "0,1" newline bitfld.long 0x10 3. "LPTIM5RST,LPTIM5RST" "0,1" bitfld.long 0x10 2. "LPTIM4RST,LPTIM4RST" "0,1" newline bitfld.long 0x10 1. "LPTIM3RST,LPTIM3RST" "0,1" bitfld.long 0x10 0. "LPTIM2RST,LPTIM2RST" "0,1" line.long 0x14 "RCC_APB3RSTCLRR,This register is used to release the reset of the corresponding peripheral." bitfld.long 0x14 16. "DTSRST,DTSRST" "0,1" bitfld.long 0x14 13. "VREFRST,VREFRST" "0,1" newline bitfld.long 0x14 11. "SYSCFGRST,SYSCFGRST" "0,1" bitfld.long 0x14 8. "SAI4RST,SAI4RST" "0,1" newline bitfld.long 0x14 3. "LPTIM5RST,LPTIM5RST" "0,1" bitfld.long 0x14 2. "LPTIM4RST,LPTIM4RST" "0,1" newline bitfld.long 0x14 1. "LPTIM3RST,LPTIM3RST" "0,1" bitfld.long 0x14 0. "LPTIM2RST,LPTIM2RST" "0,1" line.long 0x18 "RCC_AHB2RSTSETR,This register is used to activate the reset of the corresponding peripheral." bitfld.long 0x18 16. "SDMMC3RST,SDMMC3RST" "0,1" bitfld.long 0x18 8. "USBORST,USBORST" "0,1" newline bitfld.long 0x18 5. "ADC12RST,ADC12RST" "0,1" bitfld.long 0x18 2. "DMAMUXRST,DMAMUXRST" "0,1" newline bitfld.long 0x18 1. "DMA2RST,DMA2RST" "0,1" bitfld.long 0x18 0. "DMA1RST,DMA1RST" "0,1" line.long 0x1C "RCC_AHB2RSTCLRR,This register is used to release the reset of the corresponding peripheral." bitfld.long 0x1C 16. "SDMMC3RST,SDMMC3RST" "0,1" bitfld.long 0x1C 8. "USBORST,USBORST" "0,1" newline bitfld.long 0x1C 5. "ADC12RST,ADC12RST" "0,1" bitfld.long 0x1C 2. "DMAMUXRST,DMAMUXRST" "0,1" newline bitfld.long 0x1C 1. "DMA2RST,DMA2RST" "0,1" bitfld.long 0x1C 0. "DMA1RST,DMA1RST" "0,1" line.long 0x20 "RCC_AHB3RSTSETR,This register is used to activate the reset of the corresponding peripheral." bitfld.long 0x20 12. "IPCCRST,IPCCRST" "0,1" bitfld.long 0x20 11. "HSEMRST,HSEMRST" "0,1" newline bitfld.long 0x20 7. "CRC2RST,CRC2RST" "0,1" bitfld.long 0x20 6. "RNG2RST,RNG2RST" "0,1" newline bitfld.long 0x20 5. "HASH2RST,HASH2RST" "0,1" bitfld.long 0x20 4. "CRYP2RST,CRYP2RST" "0,1" newline bitfld.long 0x20 0. "DCMIRST,DCMIRST" "0,1" line.long 0x24 "RCC_AHB3RSTCLRR,This register is used to release the reset of the corresponding peripheral." bitfld.long 0x24 12. "IPCCRST,IPCCRST" "0,1" bitfld.long 0x24 11. "HSEMRST,HSEMRST" "0,1" newline bitfld.long 0x24 7. "CRC2RST,CRC2RST" "0,1" bitfld.long 0x24 6. "RNG2RST,RNG2RST" "0,1" newline bitfld.long 0x24 5. "HASH2RST,HASH2RST" "0,1" bitfld.long 0x24 4. "CRYP2RST,CRYP2RST" "0,1" newline bitfld.long 0x24 0. "DCMIRST,DCMIRST" "0,1" line.long 0x28 "RCC_AHB4RSTSETR,This register is used to activate the reset of the corresponding peripheral" bitfld.long 0x28 10. "GPIOKRST,GPIOKRST" "0,1" bitfld.long 0x28 9. "GPIOJRST,GPIOJRST" "0,1" newline bitfld.long 0x28 8. "GPIOIRST,GPIOIRST" "0,1" bitfld.long 0x28 7. "GPIOHRST,GPIOHRST" "0,1" newline bitfld.long 0x28 6. "GPIOGRST,GPIOGRST" "0,1" bitfld.long 0x28 5. "GPIOFRST,GPIOFRST" "0,1" newline bitfld.long 0x28 4. "GPIOERST,GPIOERST" "0,1" bitfld.long 0x28 3. "GPIODRST,GPIODRST" "0,1" newline bitfld.long 0x28 2. "GPIOCRST,GPIOCRST" "0,1" bitfld.long 0x28 1. "GPIOBRST,GPIOBRST" "0,1" newline bitfld.long 0x28 0. "GPIOARST,GPIOARST" "0,1" line.long 0x2C "RCC_AHB4RSTCLRR,This register is used to release the reset of the corresponding peripheral." bitfld.long 0x2C 10. "GPIOKRST,GPIOKRST" "0,1" bitfld.long 0x2C 9. "GPIOJRST,GPIOJRST" "0,1" newline bitfld.long 0x2C 8. "GPIOIRST,GPIOIRST" "0,1" bitfld.long 0x2C 7. "GPIOHRST,GPIOHRST" "0,1" newline bitfld.long 0x2C 6. "GPIOGRST,GPIOGRST" "0,1" bitfld.long 0x2C 5. "GPIOFRST,GPIOFRST" "0,1" newline bitfld.long 0x2C 4. "GPIOERST,GPIOERST" "0,1" bitfld.long 0x2C 3. "GPIODRST,GPIODRST" "0,1" newline bitfld.long 0x2C 2. "GPIOCRST,GPIOCRST" "0,1" bitfld.long 0x2C 1. "GPIOBRST,GPIOBRST" "0,1" newline bitfld.long 0x2C 0. "GPIOARST,GPIOARST" "0,1" group.long 0xA00++0x2F line.long 0x0 "RCC_MP_APB1ENSETR,This register is used to set the peripheral clock enable bit" bitfld.long 0x0 31. "MDIOSEN,MDIOSEN" "0,1" bitfld.long 0x0 29. "DAC12EN,DAC12EN" "0,1" newline bitfld.long 0x0 27. "CECEN,CECEN" "0,1" bitfld.long 0x0 26. "SPDIFEN,SPDIFEN" "0,1" newline bitfld.long 0x0 24. "I2C5EN,I2C5EN" "0,1" bitfld.long 0x0 23. "I2C3EN,I2C3EN" "0,1" newline bitfld.long 0x0 22. "I2C2EN,I2C2EN" "0,1" bitfld.long 0x0 21. "I2C1EN,I2C1EN" "0,1" newline bitfld.long 0x0 19. "UART8EN,UART8EN" "0,1" bitfld.long 0x0 18. "UART7EN,UART7EN" "0,1" newline bitfld.long 0x0 17. "UART5EN,UART5EN" "0,1" bitfld.long 0x0 16. "UART4EN,UART4EN" "0,1" newline bitfld.long 0x0 15. "USART3EN,USART3EN" "0,1" bitfld.long 0x0 14. "USART2EN,USART2EN" "0,1" newline bitfld.long 0x0 12. "SPI3EN,SPI3EN" "0,1" bitfld.long 0x0 11. "SPI2EN,SPI2EN" "0,1" newline bitfld.long 0x0 9. "LPTIM1EN,LPTIM1EN" "0,1" bitfld.long 0x0 8. "TIM14EN,TIM14EN" "0,1" newline bitfld.long 0x0 7. "TIM13EN,TIM13EN" "0,1" bitfld.long 0x0 6. "TIM12EN,TIM12EN" "0,1" newline bitfld.long 0x0 5. "TIM7EN,TIM7EN" "0,1" bitfld.long 0x0 4. "TIM6EN,TIM6EN" "0,1" newline bitfld.long 0x0 3. "TIM5EN,TIM5EN" "0,1" bitfld.long 0x0 2. "TIM4EN,TIM4EN" "0,1" newline bitfld.long 0x0 1. "TIM3EN,TIM3EN" "0,1" bitfld.long 0x0 0. "TIM2EN,TIM2EN" "0,1" line.long 0x4 "RCC_MP_APB1ENCLRR,This register is used to clear the peripheral clock enable bit" bitfld.long 0x4 31. "MDIOSEN,MDIOSEN" "0,1" bitfld.long 0x4 29. "DAC12EN,DAC12EN" "0,1" newline bitfld.long 0x4 27. "CECEN,CECEN" "0,1" bitfld.long 0x4 26. "SPDIFEN,SPDIFEN" "0,1" newline bitfld.long 0x4 24. "I2C5EN,I2C5EN" "0,1" bitfld.long 0x4 23. "I2C3EN,I2C3EN" "0,1" newline bitfld.long 0x4 22. "I2C2EN,I2C2EN" "0,1" bitfld.long 0x4 21. "I2C1EN,I2C1EN" "0,1" newline bitfld.long 0x4 19. "UART8EN,UART8EN" "0,1" bitfld.long 0x4 18. "UART7EN,UART7EN" "0,1" newline bitfld.long 0x4 17. "UART5EN,UART5EN" "0,1" bitfld.long 0x4 16. "UART4EN,UART4EN" "0,1" newline bitfld.long 0x4 15. "USART3EN,USART3EN" "0,1" bitfld.long 0x4 14. "USART2EN,USART2EN" "0,1" newline bitfld.long 0x4 12. "SPI3EN,SPI3EN" "0,1" bitfld.long 0x4 11. "SPI2EN,SPI2EN" "0,1" newline bitfld.long 0x4 9. "LPTIM1EN,LPTIM1EN" "0,1" bitfld.long 0x4 8. "TIM14EN,TIM14EN" "0,1" newline bitfld.long 0x4 7. "TIM13EN,TIM13EN" "0,1" bitfld.long 0x4 6. "TIM12EN,TIM12EN" "0,1" newline bitfld.long 0x4 5. "TIM7EN,TIM7EN" "0,1" bitfld.long 0x4 4. "TIM6EN,TIM6EN" "0,1" newline bitfld.long 0x4 3. "TIM5EN,TIM5EN" "0,1" bitfld.long 0x4 2. "TIM4EN,TIM4EN" "0,1" newline bitfld.long 0x4 1. "TIM3EN,TIM3EN" "0,1" bitfld.long 0x4 0. "TIM2EN,TIM2EN" "0,1" line.long 0x8 "RCC_MP_APB2ENSETR,This register is used to set the peripheral clock enable bit" bitfld.long 0x8 24. "FDCANEN,FDCANEN" "0,1" bitfld.long 0x8 21. "ADFSDMEN,ADFSDMEN" "0,1" newline bitfld.long 0x8 20. "DFSDMEN,DFSDMEN" "0,1" bitfld.long 0x8 18. "SAI3EN,SAI3EN" "0,1" newline bitfld.long 0x8 17. "SAI2EN,SAI2EN" "0,1" bitfld.long 0x8 16. "SAI1EN,SAI1EN" "0,1" newline bitfld.long 0x8 13. "USART6EN,USART6EN" "0,1" bitfld.long 0x8 10. "SPI5EN,SPI5EN" "0,1" newline bitfld.long 0x8 9. "SPI4EN,SPI4EN" "0,1" bitfld.long 0x8 8. "SPI1EN,SPI1EN" "0,1" newline bitfld.long 0x8 4. "TIM17EN,TIM17EN" "0,1" bitfld.long 0x8 3. "TIM16EN,TIM16EN" "0,1" newline bitfld.long 0x8 2. "TIM15EN,TIM15EN" "0,1" bitfld.long 0x8 1. "TIM8EN,TIM8EN" "0,1" newline bitfld.long 0x8 0. "TIM1EN,TIM1EN" "0,1" line.long 0xC "RCC_MP_APB2ENCLRR,This register is used to clear the peripheral clock enable bit of the corresponding peripheral." bitfld.long 0xC 24. "FDCANEN,FDCANEN" "0,1" bitfld.long 0xC 21. "ADFSDMEN,ADFSDMEN" "0,1" newline bitfld.long 0xC 20. "DFSDMEN,DFSDMEN" "0,1" bitfld.long 0xC 18. "SAI3EN,SAI3EN" "0,1" newline bitfld.long 0xC 17. "SAI2EN,SAI2EN" "0,1" bitfld.long 0xC 16. "SAI1EN,SAI1EN" "0,1" newline bitfld.long 0xC 13. "USART6EN,USART6EN" "0,1" bitfld.long 0xC 10. "SPI5EN,SPI5EN" "0,1" newline bitfld.long 0xC 9. "SPI4EN,SPI4EN" "0,1" bitfld.long 0xC 8. "SPI1EN,SPI1EN" "0,1" newline bitfld.long 0xC 4. "TIM17EN,TIM17EN" "0,1" bitfld.long 0xC 3. "TIM16EN,TIM16EN" "0,1" newline bitfld.long 0xC 2. "TIM15EN,TIM15EN" "0,1" bitfld.long 0xC 1. "TIM8EN,TIM8EN" "0,1" newline bitfld.long 0xC 0. "TIM1EN,TIM1EN" "0,1" line.long 0x10 "RCC_MP_APB3ENSETR,This register is used to set the peripheral clock enable bit" bitfld.long 0x10 20. "HDPEN,HDPEN" "0,1" bitfld.long 0x10 16. "DTSEN,DTSEN" "0,1" newline bitfld.long 0x10 13. "VREFEN,VREFEN" "0,1" bitfld.long 0x10 11. "SYSCFGEN,SYSCFGEN" "0,1" newline bitfld.long 0x10 8. "SAI4EN,SAI4EN" "0,1" bitfld.long 0x10 3. "LPTIM5EN,LPTIM5EN" "0,1" newline bitfld.long 0x10 2. "LPTIM4EN,LPTIM4EN" "0,1" bitfld.long 0x10 1. "LPTIM3EN,LPTIM3EN" "0,1" newline bitfld.long 0x10 0. "LPTIM2EN,LPTIM2EN" "0,1" line.long 0x14 "RCC_MP_APB3ENCLRR,This register is used to clear the peripheral clock enable bit of the corresponding peripheral." bitfld.long 0x14 20. "HDPEN,HDPEN" "0,1" bitfld.long 0x14 16. "DTSEN,DTSEN" "0,1" newline bitfld.long 0x14 13. "VREFEN,VREFEN" "0,1" bitfld.long 0x14 11. "SYSCFGEN,SYSCFGEN" "0,1" newline bitfld.long 0x14 8. "SAI4EN,SAI4EN" "0,1" bitfld.long 0x14 3. "LPTIM5EN,LPTIM5EN" "0,1" newline bitfld.long 0x14 2. "LPTIM4EN,LPTIM4EN" "0,1" bitfld.long 0x14 1. "LPTIM3EN,LPTIM3EN" "0,1" newline bitfld.long 0x14 0. "LPTIM2EN,LPTIM2EN" "0,1" line.long 0x18 "RCC_MP_AHB2ENSETR,This register is used to set the peripheral clock enable bit of the corresponding peripheral" bitfld.long 0x18 16. "SDMMC3EN,SDMMC3EN" "0,1" bitfld.long 0x18 8. "USBOEN,USBOEN" "0,1" newline bitfld.long 0x18 5. "ADC12EN,ADC12EN" "0,1" bitfld.long 0x18 2. "DMAMUXEN,DMAMUXEN" "0,1" newline bitfld.long 0x18 1. "DMA2EN,DMA2EN" "0,1" bitfld.long 0x18 0. "DMA1EN,DMA1EN" "0,1" line.long 0x1C "RCC_MP_AHB2ENCLRR,This register is used to clear the peripheral clock enable bit of the corresponding peripheral." bitfld.long 0x1C 16. "SDMMC3EN,SDMMC3EN" "0,1" bitfld.long 0x1C 8. "USBOEN,USBOEN" "0,1" newline bitfld.long 0x1C 5. "ADC12EN,ADC12EN" "0,1" bitfld.long 0x1C 2. "DMAMUXEN,DMAMUXEN" "0,1" newline bitfld.long 0x1C 1. "DMA2EN,DMA2EN" "0,1" bitfld.long 0x1C 0. "DMA1EN,DMA1EN" "0,1" line.long 0x20 "RCC_MP_AHB3ENSETR,This register is used to set the peripheral clock enable bit of the corresponding peripheral" bitfld.long 0x20 12. "IPCCEN,IPCCEN" "0,1" bitfld.long 0x20 11. "HSEMEN,HSEMEN" "0,1" newline bitfld.long 0x20 7. "CRC2EN,CRC2EN" "0,1" bitfld.long 0x20 6. "RNG2EN,RNG2EN" "0,1" newline bitfld.long 0x20 5. "HASH2EN,HASH2EN" "0,1" bitfld.long 0x20 4. "CRYP2EN,CRYP2EN" "0,1" newline bitfld.long 0x20 0. "DCMIEN,DCMIEN" "0,1" line.long 0x24 "RCC_MP_AHB3ENCLRR,This register is used to clear the peripheral clock enable bit of the corresponding peripheral." bitfld.long 0x24 12. "IPCCEN,IPCCEN" "0,1" bitfld.long 0x24 11. "HSEMEN,HSEMEN" "0,1" newline bitfld.long 0x24 7. "CRC2EN,CRC2EN" "0,1" bitfld.long 0x24 6. "RNG2EN,RNG2EN" "0,1" newline bitfld.long 0x24 5. "HASH2EN,HASH2EN" "0,1" bitfld.long 0x24 4. "CRYP2EN,CRYP2EN" "0,1" newline bitfld.long 0x24 0. "DCMIEN,DCMIEN" "0,1" line.long 0x28 "RCC_MP_AHB4ENSETR,This register is used to set the peripheral clock enable bit of the corresponding peripheral to . It shall be used to allocate a peripheral to the MPU." bitfld.long 0x28 10. "GPIOKEN,GPIOKEN" "0,1" bitfld.long 0x28 9. "GPIOJEN,GPIOJEN" "0,1" newline bitfld.long 0x28 8. "GPIOIEN,GPIOIEN" "0,1" bitfld.long 0x28 7. "GPIOHEN,GPIOHEN" "0,1" newline bitfld.long 0x28 6. "GPIOGEN,GPIOGEN" "0,1" bitfld.long 0x28 5. "GPIOFEN,GPIOFEN" "0,1" newline bitfld.long 0x28 4. "GPIOEEN,GPIOEEN" "0,1" bitfld.long 0x28 3. "GPIODEN,GPIODEN" "0,1" newline bitfld.long 0x28 2. "GPIOCEN,GPIOCEN" "0,1" bitfld.long 0x28 1. "GPIOBEN,GPIOBEN" "0,1" newline bitfld.long 0x28 0. "GPIOAEN,GPIOAEN" "0,1" line.long 0x2C "RCC_MP_AHB4ENCLRR,This register is used to clear the peripheral clock enable bit" bitfld.long 0x2C 10. "GPIOKEN,GPIOKEN" "0,1" bitfld.long 0x2C 9. "GPIOJEN,GPIOJEN" "0,1" newline bitfld.long 0x2C 8. "GPIOIEN,GPIOIEN" "0,1" bitfld.long 0x2C 7. "GPIOHEN,GPIOHEN" "0,1" newline bitfld.long 0x2C 6. "GPIOGEN,GPIOGEN" "0,1" bitfld.long 0x2C 5. "GPIOFEN,GPIOFEN" "0,1" newline bitfld.long 0x2C 4. "GPIOEEN,GPIOEEN" "0,1" bitfld.long 0x2C 3. "GPIODEN,GPIODEN" "0,1" newline bitfld.long 0x2C 2. "GPIOCEN,GPIOCEN" "0,1" bitfld.long 0x2C 1. "GPIOBEN,GPIOBEN" "0,1" newline bitfld.long 0x2C 0. "GPIOAEN,GPIOAEN" "0,1" group.long 0xA38++0x7 line.long 0x0 "RCC_MP_MLAHBENSETR,This register is used to set the peripheral clock enable bit" bitfld.long 0x0 4. "RETRAMEN,RETRAMEN" "0,1" line.long 0x4 "RCC_MP_MLAHBENCLRR,This register is used to clear the peripheral clock enable bit." bitfld.long 0x4 4. "RETRAMEN,RETRAMEN" "0,1" group.long 0xA80++0x3F line.long 0x0 "RCC_MC_APB1ENSETR,This register is used to set the peripheral clock enable bit of the corresponding peripheral to . It shall be used to allocate a peripheral to the MCU. Writing has no effect. reading will return . Writing a sets the corresponding bit.." bitfld.long 0x0 31. "MDIOSEN,MDIOSEN" "0,1" bitfld.long 0x0 29. "DAC12EN,DAC12EN" "0,1" newline bitfld.long 0x0 28. "WWDG1EN,WWDG1EN" "0,1" bitfld.long 0x0 27. "CECEN,CECEN" "0,1" newline bitfld.long 0x0 26. "SPDIFEN,SPDIFEN" "0,1" bitfld.long 0x0 24. "I2C5EN,I2C5EN" "0,1" newline bitfld.long 0x0 23. "I2C3EN,I2C3EN" "0,1" bitfld.long 0x0 22. "I2C2EN,I2C2EN" "0,1" newline bitfld.long 0x0 21. "I2C1EN,I2C1EN" "0,1" bitfld.long 0x0 19. "UART8EN,UART8EN" "0,1" newline bitfld.long 0x0 18. "UART7EN,UART7EN" "0,1" bitfld.long 0x0 17. "UART5EN,UART5EN" "0,1" newline bitfld.long 0x0 16. "UART4EN,UART4EN" "0,1" bitfld.long 0x0 15. "USART3EN,USART3EN" "0,1" newline bitfld.long 0x0 14. "USART2EN,USART2EN" "0,1" bitfld.long 0x0 12. "SPI3EN,SPI3EN" "0,1" newline bitfld.long 0x0 11. "SPI2EN,SPI2EN" "0,1" bitfld.long 0x0 9. "LPTIM1EN,LPTIM1EN" "0,1" newline bitfld.long 0x0 8. "TIM14EN,TIM14EN" "0,1" bitfld.long 0x0 7. "TIM13EN,TIM13EN" "0,1" newline bitfld.long 0x0 6. "TIM12EN,TIM12EN" "0,1" bitfld.long 0x0 5. "TIM7EN,TIM7EN" "0,1" newline bitfld.long 0x0 4. "TIM6EN,TIM6EN" "0,1" bitfld.long 0x0 3. "TIM5EN,TIM5EN" "0,1" newline bitfld.long 0x0 2. "TIM4EN,TIM4EN" "0,1" bitfld.long 0x0 1. "TIM3EN,TIM3EN" "0,1" newline bitfld.long 0x0 0. "TIM2EN,TIM2EN" "0,1" line.long 0x4 "RCC_MC_APB1ENCLRR,This register is used to clear the peripheral clock enable bit of the corresponding peripheral." bitfld.long 0x4 31. "MDIOSEN,MDIOSEN" "0,1" bitfld.long 0x4 29. "DAC12EN,DAC12EN" "0,1" newline bitfld.long 0x4 27. "CECEN,CECEN" "0,1" bitfld.long 0x4 26. "SPDIFEN,SPDIFEN" "0,1" newline bitfld.long 0x4 24. "I2C5EN,I2C5EN" "0,1" bitfld.long 0x4 23. "I2C3EN,I2C3EN" "0,1" newline bitfld.long 0x4 22. "I2C2EN,I2C2EN" "0,1" bitfld.long 0x4 21. "I2C1EN,I2C1EN" "0,1" newline bitfld.long 0x4 19. "UART8EN,UART8EN" "0,1" bitfld.long 0x4 18. "UART7EN,UART7EN" "0,1" newline bitfld.long 0x4 17. "UART5EN,UART5EN" "0,1" bitfld.long 0x4 16. "UART4EN,UART4EN" "0,1" newline bitfld.long 0x4 15. "USART3EN,USART3EN" "0,1" bitfld.long 0x4 14. "USART2EN,USART2EN" "0,1" newline bitfld.long 0x4 12. "SPI3EN,SPI3EN" "0,1" bitfld.long 0x4 11. "SPI2EN,SPI2EN" "0,1" newline bitfld.long 0x4 9. "LPTIM1EN,LPTIM1EN" "0,1" bitfld.long 0x4 8. "TIM14EN,TIM14EN" "0,1" newline bitfld.long 0x4 7. "TIM13EN,TIM13EN" "0,1" bitfld.long 0x4 6. "TIM12EN,TIM12EN" "0,1" newline bitfld.long 0x4 5. "TIM7EN,TIM7EN" "0,1" bitfld.long 0x4 4. "TIM6EN,TIM6EN" "0,1" newline bitfld.long 0x4 3. "TIM5EN,TIM5EN" "0,1" bitfld.long 0x4 2. "TIM4EN,TIM4EN" "0,1" newline bitfld.long 0x4 1. "TIM3EN,TIM3EN" "0,1" bitfld.long 0x4 0. "TIM2EN,TIM2EN" "0,1" line.long 0x8 "RCC_MC_APB2ENSETR,This register is used to set the peripheral clock enable bit" bitfld.long 0x8 24. "FDCANEN,FDCANEN" "0,1" bitfld.long 0x8 21. "ADFSDMEN,ADFSDMEN" "0,1" newline bitfld.long 0x8 20. "DFSDMEN,DFSDMEN" "0,1" bitfld.long 0x8 18. "SAI3EN,SAI3EN" "0,1" newline bitfld.long 0x8 17. "SAI2EN,SAI2EN" "0,1" bitfld.long 0x8 16. "SAI1EN,SAI1EN" "0,1" newline bitfld.long 0x8 13. "USART6EN,USART6EN" "0,1" bitfld.long 0x8 10. "SPI5EN,SPI5EN" "0,1" newline bitfld.long 0x8 9. "SPI4EN,SPI4EN" "0,1" bitfld.long 0x8 8. "SPI1EN,SPI1EN" "0,1" newline bitfld.long 0x8 4. "TIM17EN,TIM17EN" "0,1" bitfld.long 0x8 3. "TIM16EN,TIM16EN" "0,1" newline bitfld.long 0x8 2. "TIM15EN,TIM15EN" "0,1" bitfld.long 0x8 1. "TIM8EN,TIM8EN" "0,1" newline bitfld.long 0x8 0. "TIM1EN,TIM1EN" "0,1" line.long 0xC "RCC_MC_APB2ENCLRR,This register is used to clear the peripheral clock enable bit" bitfld.long 0xC 24. "FDCANEN,FDCANEN" "0,1" bitfld.long 0xC 21. "ADFSDMEN,ADFSDMEN" "0,1" newline bitfld.long 0xC 20. "DFSDMEN,DFSDMEN" "0,1" bitfld.long 0xC 18. "SAI3EN,SAI3EN" "0,1" newline bitfld.long 0xC 17. "SAI2EN,SAI2EN" "0,1" bitfld.long 0xC 16. "SAI1EN,SAI1EN" "0,1" newline bitfld.long 0xC 13. "USART6EN,USART6EN" "0,1" bitfld.long 0xC 10. "SPI5EN,SPI5EN" "0,1" newline bitfld.long 0xC 9. "SPI4EN,SPI4EN" "0,1" bitfld.long 0xC 8. "SPI1EN,SPI1EN" "0,1" newline bitfld.long 0xC 4. "TIM17EN,TIM17EN" "0,1" bitfld.long 0xC 3. "TIM16EN,TIM16EN" "0,1" newline bitfld.long 0xC 2. "TIM15EN,TIM15EN" "0,1" bitfld.long 0xC 1. "TIM8EN,TIM8EN" "0,1" newline bitfld.long 0xC 0. "TIM1EN,TIM1EN" "0,1" line.long 0x10 "RCC_MC_APB3ENSETR,This register is used to set the peripheral clock enable bit" bitfld.long 0x10 20. "HDPEN,HDPEN" "0,1" bitfld.long 0x10 16. "DTSEN,DTSEN" "0,1" newline bitfld.long 0x10 13. "VREFEN,VREFEN" "0,1" bitfld.long 0x10 11. "SYSCFGEN,SYSCFGEN" "0,1" newline bitfld.long 0x10 8. "SAI4EN,SAI4EN" "0,1" bitfld.long 0x10 3. "LPTIM5EN,LPTIM5EN" "0,1" newline bitfld.long 0x10 2. "LPTIM4EN,LPTIM4EN" "0,1" bitfld.long 0x10 1. "LPTIM3EN,LPTIM3EN" "0,1" newline bitfld.long 0x10 0. "LPTIM2EN,LPTIM2EN" "0,1" line.long 0x14 "RCC_MC_APB3ENCLRR,This register is used to clear the peripheral clock enable bit" bitfld.long 0x14 20. "HDPEN,HDPEN" "0,1" bitfld.long 0x14 16. "DTSEN,DTSEN" "0,1" newline bitfld.long 0x14 13. "VREFEN,VREFEN" "0,1" bitfld.long 0x14 11. "SYSCFGEN,SYSCFGEN" "0,1" newline bitfld.long 0x14 8. "SAI4EN,SAI4EN" "0,1" bitfld.long 0x14 3. "LPTIM5EN,LPTIM5EN" "0,1" newline bitfld.long 0x14 2. "LPTIM4EN,LPTIM4EN" "0,1" bitfld.long 0x14 1. "LPTIM3EN,LPTIM3EN" "0,1" newline bitfld.long 0x14 0. "LPTIM2EN,LPTIM2EN" "0,1" line.long 0x18 "RCC_MC_AHB2ENSETR,This register is used to set the peripheral clock enable bit" bitfld.long 0x18 16. "SDMMC3EN,SDMMC3EN" "0,1" bitfld.long 0x18 8. "USBOEN,USBOEN" "0,1" newline bitfld.long 0x18 5. "ADC12EN,ADC12EN" "0,1" bitfld.long 0x18 2. "DMAMUXEN,DMAMUXEN" "0,1" newline bitfld.long 0x18 1. "DMA2EN,DMA2EN" "0,1" bitfld.long 0x18 0. "DMA1EN,DMA1EN" "0,1" line.long 0x1C "RCC_MC_AHB2ENCLRR,This register is used to clear the peripheral clock enable bit" bitfld.long 0x1C 16. "SDMMC3EN,SDMMC3EN" "0,1" bitfld.long 0x1C 8. "USBOEN,USBOEN" "0,1" newline bitfld.long 0x1C 5. "ADC12EN,ADC12EN" "0,1" bitfld.long 0x1C 2. "DMAMUXEN,DMAMUXEN" "0,1" newline bitfld.long 0x1C 1. "DMA2EN,DMA2EN" "0,1" bitfld.long 0x1C 0. "DMA1EN,DMA1EN" "0,1" line.long 0x20 "RCC_MC_AHB3ENSETR,This register is used to set the peripheral clock enable bit" bitfld.long 0x20 12. "IPCCEN,IPCCEN" "0,1" bitfld.long 0x20 11. "HSEMEN,HSEMEN" "0,1" newline bitfld.long 0x20 7. "CRC2EN,CRC2EN" "0,1" bitfld.long 0x20 6. "RNG2EN,RNG2EN" "0,1" newline bitfld.long 0x20 5. "HASH2EN,HASH2EN" "0,1" bitfld.long 0x20 4. "CRYP2EN,CRYP2EN" "0,1" newline bitfld.long 0x20 0. "DCMIEN,DCMIEN" "0,1" line.long 0x24 "RCC_MC_AHB3ENCLRR,This register is used to clear the peripheral clock enable bit" bitfld.long 0x24 12. "IPCCEN,IPCCEN" "0,1" bitfld.long 0x24 11. "HSEMEN,HSEMEN" "0,1" newline bitfld.long 0x24 7. "CRC2EN,CRC2EN" "0,1" bitfld.long 0x24 6. "RNG2EN,RNG2EN" "0,1" newline bitfld.long 0x24 5. "HASH2EN,HASH2EN" "0,1" bitfld.long 0x24 4. "CRYP2EN,CRYP2EN" "0,1" newline bitfld.long 0x24 0. "DCMIEN,DCMIEN" "0,1" line.long 0x28 "RCC_MC_AHB4ENSETR,This register is used to set the peripheral clock enable bit" bitfld.long 0x28 10. "GPIOKEN,GPIOKEN" "0,1" bitfld.long 0x28 9. "GPIOJEN,GPIOJEN" "0,1" newline bitfld.long 0x28 8. "GPIOIEN,GPIOIEN" "0,1" bitfld.long 0x28 7. "GPIOHEN,GPIOHEN" "0,1" newline bitfld.long 0x28 6. "GPIOGEN,GPIOGEN" "0,1" bitfld.long 0x28 5. "GPIOFEN,GPIOFEN" "0,1" newline bitfld.long 0x28 4. "GPIOEEN,GPIOEEN" "0,1" bitfld.long 0x28 3. "GPIODEN,GPIODEN" "0,1" newline bitfld.long 0x28 2. "GPIOCEN,GPIOCEN" "0,1" bitfld.long 0x28 1. "GPIOBEN,GPIOBEN" "0,1" newline bitfld.long 0x28 0. "GPIOAEN,GPIOAEN" "0,1" line.long 0x2C "RCC_MC_AHB4ENCLRR,This register is used to clear the peripheral clock enable bit" bitfld.long 0x2C 10. "GPIOKEN,GPIOKEN" "0,1" bitfld.long 0x2C 9. "GPIOJEN,GPIOJEN" "0,1" newline bitfld.long 0x2C 8. "GPIOIEN,GPIOIEN" "0,1" bitfld.long 0x2C 7. "GPIOHEN,GPIOHEN" "0,1" newline bitfld.long 0x2C 6. "GPIOGEN,GPIOGEN" "0,1" bitfld.long 0x2C 5. "GPIOFEN,GPIOFEN" "0,1" newline bitfld.long 0x2C 4. "GPIOEEN,GPIOEEN" "0,1" bitfld.long 0x2C 3. "GPIODEN,GPIODEN" "0,1" newline bitfld.long 0x2C 2. "GPIOCEN,GPIOCEN" "0,1" bitfld.long 0x2C 1. "GPIOBEN,GPIOBEN" "0,1" newline bitfld.long 0x2C 0. "GPIOAEN,GPIOAEN" "0,1" line.long 0x30 "RCC_MC_AXIMENSETR,This register is used to set the peripheral clock enable bit" bitfld.long 0x30 0. "SYSRAMEN,SYSRAMEN" "0,1" line.long 0x34 "RCC_MC_AXIMENCLRR,This register is used to clear the peripheral clock enable bit" bitfld.long 0x34 0. "SYSRAMEN,SYSRAMEN" "0,1" line.long 0x38 "RCC_MC_MLAHBENSETR,This register is used to set the peripheral clock enable bit" bitfld.long 0x38 4. "RETRAMEN,RETRAMEN" "0,1" line.long 0x3C "RCC_MC_MLAHBENCLRR,This register is used to clear the peripheral clock enable bit" bitfld.long 0x3C 4. "RETRAMEN,RETRAMEN" "0,1" group.long 0xB00++0x3F line.long 0x0 "RCC_MP_APB1LPENSETR,This register is used by the MCU in order to clear the PERxLPEN bits" bitfld.long 0x0 31. "MDIOSLPEN,MDIOSLPEN" "0,1" bitfld.long 0x0 29. "DAC12LPEN,DAC12LPEN" "0,1" newline bitfld.long 0x0 27. "CECLPEN,CECLPEN" "0,1" bitfld.long 0x0 26. "SPDIFLPEN,SPDIFLPEN" "0,1" newline bitfld.long 0x0 24. "I2C5LPEN,I2C5LPEN" "0,1" bitfld.long 0x0 23. "I2C3LPEN,I2C3LPEN" "0,1" newline bitfld.long 0x0 22. "I2C2LPEN,I2C2LPEN" "0,1" bitfld.long 0x0 21. "I2C1LPEN,I2C1LPEN" "0,1" newline bitfld.long 0x0 19. "UART8LPEN,UART8LPEN" "0,1" bitfld.long 0x0 18. "UART7LPEN,UART7LPEN" "0,1" newline bitfld.long 0x0 17. "UART5LPEN,UART5LPEN" "0,1" bitfld.long 0x0 16. "UART4LPEN,UART4LPEN" "0,1" newline bitfld.long 0x0 15. "USART3LPEN,USART3LPEN" "0,1" bitfld.long 0x0 14. "USART2LPEN,USART2LPEN" "0,1" newline bitfld.long 0x0 12. "SPI3LPEN,SPI3LPEN" "0,1" bitfld.long 0x0 11. "SPI2LPEN,SPI2LPEN" "0,1" newline bitfld.long 0x0 9. "LPTIM1LPEN,LPTIM1LPEN" "0,1" bitfld.long 0x0 8. "TIM14LPEN,TIM14LPEN" "0,1" newline bitfld.long 0x0 7. "TIM13LPEN,TIM13LPEN" "0,1" bitfld.long 0x0 6. "TIM12LPEN,TIM12LPEN" "0,1" newline bitfld.long 0x0 5. "TIM7LPEN,TIM7LPEN" "0,1" bitfld.long 0x0 4. "TIM6LPEN,TIM6LPEN" "0,1" newline bitfld.long 0x0 3. "TIM5LPEN,TIM5LPEN" "0,1" bitfld.long 0x0 2. "TIM4LPEN,TIM4LPEN" "0,1" newline bitfld.long 0x0 1. "TIM3LPEN,TIM3LPEN" "0,1" bitfld.long 0x0 0. "TIM2LPEN,TIM2LPEN" "0,1" line.long 0x4 "RCC_MP_APB1LPENCLRR,This register is used by the MPU in order to clear the PERxLPEN bits ." bitfld.long 0x4 31. "MDIOSLPEN,MDIOSLPEN" "0,1" bitfld.long 0x4 29. "DAC12LPEN,DAC12LPEN" "0,1" newline bitfld.long 0x4 27. "CECLPEN,CECLPEN" "0,1" bitfld.long 0x4 26. "SPDIFLPEN,SPDIFLPEN" "0,1" newline bitfld.long 0x4 24. "I2C5LPEN,I2C5LPEN" "0,1" bitfld.long 0x4 23. "I2C3LPEN,I2C3LPEN" "0,1" newline bitfld.long 0x4 22. "I2C2LPEN,I2C2LPEN" "0,1" bitfld.long 0x4 21. "I2C1LPEN,I2C1LPEN" "0,1" newline bitfld.long 0x4 19. "UART8LPEN,UART8LPEN" "0,1" bitfld.long 0x4 18. "UART7LPEN,UART7LPEN" "0,1" newline bitfld.long 0x4 17. "UART5LPEN,UART5LPEN" "0,1" bitfld.long 0x4 16. "UART4LPEN,UART4LPEN" "0,1" newline bitfld.long 0x4 15. "USART3LPEN,USART3LPEN" "0,1" bitfld.long 0x4 14. "USART2LPEN,USART2LPEN" "0,1" newline bitfld.long 0x4 12. "SPI3LPEN,SPI3LPEN" "0,1" bitfld.long 0x4 11. "SPI2LPEN,SPI2LPEN" "0,1" newline bitfld.long 0x4 9. "LPTIM1LPEN,LPTIM1LPEN" "0,1" bitfld.long 0x4 8. "TIM14LPEN,TIM14LPEN" "0,1" newline bitfld.long 0x4 7. "TIM13LPEN,TIM13LPEN" "0,1" bitfld.long 0x4 6. "TIM12LPEN,TIM12LPEN" "0,1" newline bitfld.long 0x4 5. "TIM7LPEN,TIM7LPEN" "0,1" bitfld.long 0x4 4. "TIM6LPEN,TIM6LPEN" "0,1" newline bitfld.long 0x4 3. "TIM5LPEN,TIM5LPEN" "0,1" bitfld.long 0x4 2. "TIM4LPEN,TIM4LPEN" "0,1" newline bitfld.long 0x4 1. "TIM3LPEN,TIM3LPEN" "0,1" bitfld.long 0x4 0. "TIM2LPEN,TIM2LPEN" "0,1" line.long 0x8 "RCC_MP_APB2LPENSETR,This register is used by the MCU in order to clear the PERxLPEN bits" bitfld.long 0x8 24. "FDCANLPEN,FDCANLPEN" "0,1" bitfld.long 0x8 21. "ADFSDMLPEN,ADFSDMLPEN" "0,1" newline bitfld.long 0x8 20. "DFSDMLPEN,DFSDMLPEN" "0,1" bitfld.long 0x8 18. "SAI3LPEN,SAI3LPEN" "0,1" newline bitfld.long 0x8 17. "SAI2LPEN,SAI2LPEN" "0,1" bitfld.long 0x8 16. "SAI1LPEN,SAI1LPEN" "0,1" newline bitfld.long 0x8 13. "USART6LPEN,USART6LPEN" "0,1" bitfld.long 0x8 10. "SPI5LPEN,SPI5LPEN" "0,1" newline bitfld.long 0x8 9. "SPI4LPEN,SPI4LPEN" "0,1" bitfld.long 0x8 8. "SPI1LPEN,SPI1LPEN" "0,1" newline bitfld.long 0x8 4. "TIM17LPEN,TIM17LPEN" "0,1" bitfld.long 0x8 3. "TIM16LPEN,TIM16LPEN" "0,1" newline bitfld.long 0x8 2. "TIM15LPEN,TIM15LPEN" "0,1" bitfld.long 0x8 1. "TIM8LPEN,TIM8LPEN" "0,1" newline bitfld.long 0x8 0. "TIM1LPEN,TIM1LPEN" "0,1" line.long 0xC "RCC_MP_APB2LPENCLRR,This register is used by the MCU in order to clear the PERxLPEN bits" bitfld.long 0xC 24. "FDCANLPEN,FDCANLPEN" "0,1" bitfld.long 0xC 21. "ADFSDMLPEN,ADFSDMLPEN" "0,1" newline bitfld.long 0xC 20. "DFSDMLPEN,DFSDMLPEN" "0,1" bitfld.long 0xC 18. "SAI3LPEN,SAI3LPEN" "0,1" newline bitfld.long 0xC 17. "SAI2LPEN,SAI2LPEN" "0,1" bitfld.long 0xC 16. "SAI1LPEN,SAI1LPEN" "0,1" newline bitfld.long 0xC 13. "USART6LPEN,USART6LPEN" "0,1" bitfld.long 0xC 10. "SPI5LPEN,SPI5LPEN" "0,1" newline bitfld.long 0xC 9. "SPI4LPEN,SPI4LPEN" "0,1" bitfld.long 0xC 8. "SPI1LPEN,SPI1LPEN" "0,1" newline bitfld.long 0xC 4. "TIM17LPEN,TIM17LPEN" "0,1" bitfld.long 0xC 3. "TIM16LPEN,TIM16LPEN" "0,1" newline bitfld.long 0xC 2. "TIM15LPEN,TIM15LPEN" "0,1" bitfld.long 0xC 1. "TIM8LPEN,TIM8LPEN" "0,1" newline bitfld.long 0xC 0. "TIM1LPEN,TIM1LPEN" "0,1" line.long 0x10 "RCC_MP_APB3LPENSETR,This register is used by the MCU in order to clear the PERxLPEN bits" bitfld.long 0x10 16. "DTSLPEN,DTSLPEN" "0,1" bitfld.long 0x10 13. "VREFLPEN,VREFLPEN" "0,1" newline bitfld.long 0x10 11. "SYSCFGLPEN,SYSCFGLPEN" "0,1" bitfld.long 0x10 8. "SAI4LPEN,SAI4LPEN" "0,1" newline bitfld.long 0x10 3. "LPTIM5LPEN,LPTIM5LPEN" "0,1" bitfld.long 0x10 2. "LPTIM4LPEN,LPTIM4LPEN" "0,1" newline bitfld.long 0x10 1. "LPTIM3LPEN,LPTIM3LPEN" "0,1" bitfld.long 0x10 0. "LPTIM2LPEN,LPTIM2LPEN" "0,1" line.long 0x14 "RCC_MP_APB3LPENCLRR,This register is used by the MCU in order to clear the PERxLPEN bits" bitfld.long 0x14 16. "DTSLPEN,DTSLPEN" "0,1" bitfld.long 0x14 13. "VREFLPEN,VREFLPEN" "0,1" newline bitfld.long 0x14 11. "SYSCFGLPEN,SYSCFGLPEN" "0,1" bitfld.long 0x14 8. "SAI4LPEN,SAI4LPEN" "0,1" newline bitfld.long 0x14 3. "LPTIM5LPEN,LPTIM5LPEN" "0,1" bitfld.long 0x14 2. "LPTIM4LPEN,LPTIM4LPEN" "0,1" newline bitfld.long 0x14 1. "LPTIM3LPEN,LPTIM3LPEN" "0,1" bitfld.long 0x14 0. "LPTIM2LPEN,LPTIM2LPEN" "0,1" line.long 0x18 "RCC_MP_AHB2LPENSETR,This register is used by the MPU in order to set the PERxLPEN bit." bitfld.long 0x18 16. "SDMMC3LPEN,SDMMC3LPEN" "0,1" bitfld.long 0x18 8. "USBOLPEN,USBOLPEN" "0,1" newline bitfld.long 0x18 5. "ADC12LPEN,ADC12LPEN" "0,1" bitfld.long 0x18 2. "DMAMUXLPEN,DMAMUXLPEN" "0,1" newline bitfld.long 0x18 1. "DMA2LPEN,DMA2LPEN" "0,1" bitfld.long 0x18 0. "DMA1LPEN,DMA1LPEN" "0,1" line.long 0x1C "RCC_MP_AHB2LPENCLRR,This register is used by the MCU in order to clear the PERxLPEN bits" bitfld.long 0x1C 16. "SDMMC3LPEN,SDMMC3LPEN" "0,1" bitfld.long 0x1C 8. "USBOLPEN,USBOLPEN" "0,1" newline bitfld.long 0x1C 5. "ADC12LPEN,ADC12LPEN" "0,1" bitfld.long 0x1C 2. "DMAMUXLPEN,DMAMUXLPEN" "0,1" newline bitfld.long 0x1C 1. "DMA2LPEN,DMA2LPEN" "0,1" bitfld.long 0x1C 0. "DMA1LPEN,DMA1LPEN" "0,1" line.long 0x20 "RCC_MP_AHB3LPENSETR,This register is used by the MPU" bitfld.long 0x20 12. "IPCCLPEN,IPCCLPEN" "0,1" bitfld.long 0x20 11. "HSEMLPEN,HSEMLPEN" "0,1" newline bitfld.long 0x20 7. "CRC2LPEN,CRC2LPEN" "0,1" bitfld.long 0x20 6. "RNG2LPEN,RNG2LPEN" "0,1" newline bitfld.long 0x20 5. "HASH2LPEN,HASH2LPEN" "0,1" bitfld.long 0x20 4. "CRYP2LPEN,CRYP2LPEN" "0,1" newline bitfld.long 0x20 0. "DCMILPEN,DCMILPEN" "0,1" line.long 0x24 "RCC_MP_AHB3LPENCLRR,This register is used by the MPU in order to clear the PERxLPEN bit" bitfld.long 0x24 12. "IPCCLPEN,IPCCLPEN" "0,1" bitfld.long 0x24 11. "HSEMLPEN,HSEMLPEN" "0,1" newline bitfld.long 0x24 7. "CRC2LPEN,CRC2LPEN" "0,1" bitfld.long 0x24 6. "RNG2LPEN,RNG2LPEN" "0,1" newline bitfld.long 0x24 5. "HASH2LPEN,HASH2LPEN" "0,1" bitfld.long 0x24 4. "CRYP2LPEN,CRYP2LPEN" "0,1" newline bitfld.long 0x24 0. "DCMILPEN,DCMILPEN" "0,1" line.long 0x28 "RCC_MP_AHB4LPENSETR,This register is used by the MPU" bitfld.long 0x28 10. "GPIOKLPEN,GPIOKLPEN" "0,1" bitfld.long 0x28 9. "GPIOJLPEN,GPIOJLPEN" "0,1" newline bitfld.long 0x28 8. "GPIOILPEN,GPIOILPEN" "0,1" bitfld.long 0x28 7. "GPIOHLPEN,GPIOHLPEN" "0,1" newline bitfld.long 0x28 6. "GPIOGLPEN,GPIOGLPEN" "0,1" bitfld.long 0x28 5. "GPIOFLPEN,GPIOFLPEN" "0,1" newline bitfld.long 0x28 4. "GPIOELPEN,GPIOELPEN" "0,1" bitfld.long 0x28 3. "GPIODLPEN,GPIODLPEN" "0,1" newline bitfld.long 0x28 2. "GPIOCLPEN,GPIOCLPEN" "0,1" bitfld.long 0x28 1. "GPIOBLPEN,GPIOBLPEN" "0,1" newline bitfld.long 0x28 0. "GPIOALPEN,GPIOALPEN" "0,1" line.long 0x2C "RCC_MP_AHB4LPENCLRR,This register is used by the MPU" bitfld.long 0x2C 10. "GPIOKLPEN,GPIOKLPEN" "0,1" bitfld.long 0x2C 9. "GPIOJLPEN,GPIOJLPEN" "0,1" newline bitfld.long 0x2C 8. "GPIOILPEN,GPIOILPEN" "0,1" bitfld.long 0x2C 7. "GPIOHLPEN,GPIOHLPEN" "0,1" newline bitfld.long 0x2C 6. "GPIOGLPEN,GPIOGLPEN" "0,1" bitfld.long 0x2C 5. "GPIOFLPEN,GPIOFLPEN" "0,1" newline bitfld.long 0x2C 4. "GPIOELPEN,GPIOELPEN" "0,1" bitfld.long 0x2C 3. "GPIODLPEN,GPIODLPEN" "0,1" newline bitfld.long 0x2C 2. "GPIOCLPEN,GPIOCLPEN" "0,1" bitfld.long 0x2C 1. "GPIOBLPEN,GPIOBLPEN" "0,1" newline bitfld.long 0x2C 0. "GPIOALPEN,GPIOALPEN" "0,1" line.long 0x30 "RCC_MP_AXIMLPENSETR,This register is used by the MPU" bitfld.long 0x30 0. "SYSRAMLPEN,SYSRAMLPEN" "0,1" line.long 0x34 "RCC_MP_AXIMLPENCLRR,This register is used by the MPU" bitfld.long 0x34 0. "SYSRAMLPEN,SYSRAMLPEN" "0,1" line.long 0x38 "RCC_MP_MLAHBLPENSETR,This register is used by the MPU in order to set the PERxLPEN bit" bitfld.long 0x38 4. "RETRAMLPEN,RETRAMLPEN" "0,1" bitfld.long 0x38 2. "SRAM34LPEN,SRAM34LPEN" "0,1" newline bitfld.long 0x38 1. "SRAM2LPEN,SRAM2LPEN" "0,1" bitfld.long 0x38 0. "SRAM1LPEN,SRAM1LPEN" "0,1" line.long 0x3C "RCC_MP_MLAHBLPENCLRR,This register is used by the MPU in order to clear the PERxLPEN bit" bitfld.long 0x3C 4. "RETRAMLPEN,RETRAMLPEN" "0,1" bitfld.long 0x3C 2. "SRAM34LPEN,SRAM34LPEN" "0,1" newline bitfld.long 0x3C 1. "SRAM2LPEN,SRAM2LPEN" "0,1" bitfld.long 0x3C 0. "SRAM1LPEN,SRAM1LPEN" "0,1" group.long 0xB80++0x3F line.long 0x0 "RCC_MC_APB1LPENSETR,This register is used by the MCU in order to set the PERxLPEN bit." bitfld.long 0x0 31. "MDIOSLPEN,MDIOSLPEN" "0,1" bitfld.long 0x0 29. "DAC12LPEN,DAC12LPEN" "0,1" newline bitfld.long 0x0 28. "WWDG1LPEN,WWDG1LPEN" "0,1" bitfld.long 0x0 27. "CECLPEN,CECLPEN" "0,1" newline bitfld.long 0x0 26. "SPDIFLPEN,SPDIFLPEN" "0,1" bitfld.long 0x0 24. "I2C5LPEN,I2C5LPEN" "0,1" newline bitfld.long 0x0 23. "I2C3LPEN,I2C3LPEN" "0,1" bitfld.long 0x0 22. "I2C2LPEN,I2C2LPEN" "0,1" newline bitfld.long 0x0 21. "I2C1LPEN,I2C1LPEN" "0,1" bitfld.long 0x0 19. "UART8LPEN,UART8LPEN" "0,1" newline bitfld.long 0x0 18. "UART7LPEN,UART7LPEN" "0,1" bitfld.long 0x0 17. "UART5LPEN,UART5LPEN" "0,1" newline bitfld.long 0x0 16. "UART4LPEN,UART4LPEN" "0,1" bitfld.long 0x0 15. "USART3LPEN,USART3LPEN" "0,1" newline bitfld.long 0x0 14. "USART2LPEN,USART2LPEN" "0,1" bitfld.long 0x0 12. "SPI3LPEN,SPI3LPEN" "0,1" newline bitfld.long 0x0 11. "SPI2LPEN,SPI2LPEN" "0,1" bitfld.long 0x0 9. "LPTIM1LPEN,LPTIM1LPEN" "0,1" newline bitfld.long 0x0 8. "TIM14LPEN,TIM14LPEN" "0,1" bitfld.long 0x0 7. "TIM13LPEN,TIM13LPEN" "0,1" newline bitfld.long 0x0 6. "TIM12LPEN,TIM12LPEN" "0,1" bitfld.long 0x0 5. "TIM7LPEN,TIM7LPEN" "0,1" newline bitfld.long 0x0 4. "TIM6LPEN,TIM6LPEN" "0,1" bitfld.long 0x0 3. "TIM5LPEN,TIM5LPEN" "0,1" newline bitfld.long 0x0 2. "TIM4LPEN,TIM4LPEN" "0,1" bitfld.long 0x0 1. "TIM3LPEN,TIM3LPEN" "0,1" newline bitfld.long 0x0 0. "TIM2LPEN,TIM2LPEN" "0,1" line.long 0x4 "RCC_MC_APB1LPENCLRR,This register is used by the MCU in order to clear the PERxLPEN bits" bitfld.long 0x4 31. "MDIOSLPEN,MDIOSLPEN" "0,1" bitfld.long 0x4 29. "DAC12LPEN,DAC12LPEN" "0,1" newline bitfld.long 0x4 28. "WWDG1LPEN,WWDG1LPEN" "0,1" bitfld.long 0x4 27. "CECLPEN,CECLPEN" "0,1" newline bitfld.long 0x4 26. "SPDIFLPEN,SPDIFLPEN" "0,1" bitfld.long 0x4 24. "I2C5LPEN,I2C5LPEN" "0,1" newline bitfld.long 0x4 23. "I2C3LPEN,I2C3LPEN" "0,1" bitfld.long 0x4 22. "I2C2LPEN,I2C2LPEN" "0,1" newline bitfld.long 0x4 21. "I2C1LPEN,I2C1LPEN" "0,1" bitfld.long 0x4 19. "UART8LPEN,UART8LPEN" "0,1" newline bitfld.long 0x4 18. "UART7LPEN,UART7LPEN" "0,1" bitfld.long 0x4 17. "UART5LPEN,UART5LPEN" "0,1" newline bitfld.long 0x4 16. "UART4LPEN,UART4LPEN" "0,1" bitfld.long 0x4 15. "USART3LPEN,USART3LPEN" "0,1" newline bitfld.long 0x4 14. "USART2LPEN,USART2LPEN" "0,1" bitfld.long 0x4 12. "SPI3LPEN,SPI3LPEN" "0,1" newline bitfld.long 0x4 11. "SPI2LPEN,SPI2LPEN" "0,1" bitfld.long 0x4 9. "LPTIM1LPEN,LPTIM1LPEN" "0,1" newline bitfld.long 0x4 8. "TIM14LPEN,TIM14LPEN" "0,1" bitfld.long 0x4 7. "TIM13LPEN,TIM13LPEN" "0,1" newline bitfld.long 0x4 6. "TIM12LPEN,TIM12LPEN" "0,1" bitfld.long 0x4 5. "TIM7LPEN,TIM7LPEN" "0,1" newline bitfld.long 0x4 4. "TIM6LPEN,TIM6LPEN" "0,1" bitfld.long 0x4 3. "TIM5LPEN,TIM5LPEN" "0,1" newline bitfld.long 0x4 2. "TIM4LPEN,TIM4LPEN" "0,1" bitfld.long 0x4 1. "TIM3LPEN,TIM3LPEN" "0,1" newline bitfld.long 0x4 0. "TIM2LPEN,TIM2LPEN" "0,1" line.long 0x8 "RCC_MC_APB2LPENSETR,This register is used by the MCU in order to set the PERxLPEN bit." bitfld.long 0x8 24. "FDCANLPEN,FDCANLPEN" "0,1" bitfld.long 0x8 21. "ADFSDMLPEN,ADFSDMLPEN" "0,1" newline bitfld.long 0x8 20. "DFSDMLPEN,DFSDMLPEN" "0,1" bitfld.long 0x8 18. "SAI3LPEN,SAI3LPEN" "0,1" newline bitfld.long 0x8 17. "SAI2LPEN,SAI2LPEN" "0,1" bitfld.long 0x8 16. "SAI1LPEN,SAI1LPEN" "0,1" newline bitfld.long 0x8 13. "USART6LPEN,USART6LPEN" "0,1" bitfld.long 0x8 10. "SPI5LPEN,SPI5LPEN" "0,1" newline bitfld.long 0x8 9. "SPI4LPEN,SPI4LPEN" "0,1" bitfld.long 0x8 8. "SPI1LPEN,SPI1LPEN" "0,1" newline bitfld.long 0x8 4. "TIM17LPEN,TIM17LPEN" "0,1" bitfld.long 0x8 3. "TIM16LPEN,TIM16LPEN" "0,1" newline bitfld.long 0x8 2. "TIM15LPEN,TIM15LPEN" "0,1" bitfld.long 0x8 1. "TIM8LPEN,TIM8LPEN" "0,1" newline bitfld.long 0x8 0. "TIM1LPEN,TIM1LPEN" "0,1" line.long 0xC "RCC_MC_APB2LPENCLRR,This register is used by the MCU in order to clear the PERxLPEN bit" bitfld.long 0xC 24. "FDCANLPEN,FDCANLPEN" "0,1" bitfld.long 0xC 21. "ADFSDMLPEN,ADFSDMLPEN" "0,1" newline bitfld.long 0xC 20. "DFSDMLPEN,DFSDMLPEN" "0,1" bitfld.long 0xC 18. "SAI3LPEN,SAI3LPEN" "0,1" newline bitfld.long 0xC 17. "SAI2LPEN,SAI2LPEN" "0,1" bitfld.long 0xC 16. "SAI1LPEN,SAI1LPEN" "0,1" newline bitfld.long 0xC 13. "USART6LPEN,USART6LPEN" "0,1" bitfld.long 0xC 10. "SPI5LPEN,SPI5LPEN" "0,1" newline bitfld.long 0xC 9. "SPI4LPEN,SPI4LPEN" "0,1" bitfld.long 0xC 8. "SPI1LPEN,SPI1LPEN" "0,1" newline bitfld.long 0xC 4. "TIM17LPEN,TIM17LPEN" "0,1" bitfld.long 0xC 3. "TIM16LPEN,TIM16LPEN" "0,1" newline bitfld.long 0xC 2. "TIM15LPEN,TIM15LPEN" "0,1" bitfld.long 0xC 1. "TIM8LPEN,TIM8LPEN" "0,1" newline bitfld.long 0xC 0. "TIM1LPEN,TIM1LPEN" "0,1" line.long 0x10 "RCC_MC_APB3LPENSETR,This register is used by the MCU in order to set the PERxLPEN bit." bitfld.long 0x10 16. "DTSLPEN,DTSLPEN" "0,1" bitfld.long 0x10 13. "VREFLPEN,VREFLPEN" "0,1" newline bitfld.long 0x10 11. "SYSCFGLPEN,SYSCFGLPEN" "0,1" bitfld.long 0x10 8. "SAI4LPEN,SAI4LPEN" "0,1" newline bitfld.long 0x10 3. "LPTIM5LPEN,LPTIM5LPEN" "0,1" bitfld.long 0x10 2. "LPTIM4LPEN,LPTIM4LPEN" "0,1" newline bitfld.long 0x10 1. "LPTIM3LPEN,LPTIM3LPEN" "0,1" bitfld.long 0x10 0. "LPTIM2LPEN,LPTIM2LPEN" "0,1" line.long 0x14 "RCC_MC_APB3LPENCLRR,This register is used by the MCU in order to clear the PERxLPEN bit" bitfld.long 0x14 16. "DTSLPEN,DTSLPEN" "0,1" bitfld.long 0x14 13. "VREFLPEN,VREFLPEN" "0,1" newline bitfld.long 0x14 11. "SYSCFGLPEN,SYSCFGLPEN" "0,1" bitfld.long 0x14 8. "SAI4LPEN,SAI4LPEN" "0,1" newline bitfld.long 0x14 3. "LPTIM5LPEN,LPTIM5LPEN" "0,1" bitfld.long 0x14 2. "LPTIM4LPEN,LPTIM4LPEN" "0,1" newline bitfld.long 0x14 1. "LPTIM3LPEN,LPTIM3LPEN" "0,1" bitfld.long 0x14 0. "LPTIM2LPEN,LPTIM2LPEN" "0,1" line.long 0x18 "RCC_MC_AHB2LPENSETR,This register is used by the MCU in order to set the PERxLPEN bit." bitfld.long 0x18 16. "SDMMC3LPEN,SDMMC3LPEN" "0,1" bitfld.long 0x18 8. "USBOLPEN,USBOLPEN" "0,1" newline bitfld.long 0x18 5. "ADC12LPEN,ADC12LPEN" "0,1" bitfld.long 0x18 2. "DMAMUXLPEN,DMAMUXLPEN" "0,1" newline bitfld.long 0x18 1. "DMA2LPEN,DMA2LPEN" "0,1" bitfld.long 0x18 0. "DMA1LPEN,DMA1LPEN" "0,1" line.long 0x1C "RCC_MC_AHB2LPENCLRR,This register is used by the MCU in order to clear the PERxLPEN bit" bitfld.long 0x1C 16. "SDMMC3LPEN,SDMMC3LPEN" "0,1" bitfld.long 0x1C 8. "USBOLPEN,USBOLPEN" "0,1" newline bitfld.long 0x1C 5. "ADC12LPEN,ADC12LPEN" "0,1" bitfld.long 0x1C 2. "DMAMUXLPEN,DMAMUXLPEN" "0,1" newline bitfld.long 0x1C 1. "DMA2LPEN,DMA2LPEN" "0,1" bitfld.long 0x1C 0. "DMA1LPEN,DMA1LPEN" "0,1" line.long 0x20 "RCC_MC_AHB3LPENSETR,This register is used by the MCU in order to set the PERxLPEN bit." bitfld.long 0x20 12. "IPCCLPEN,IPCCLPEN" "0,1" bitfld.long 0x20 11. "HSEMLPEN,HSEMLPEN" "0,1" newline bitfld.long 0x20 7. "CRC2LPEN,CRC2LPEN" "0,1" bitfld.long 0x20 6. "RNG2LPEN,RNG2LPEN" "0,1" newline bitfld.long 0x20 5. "HASH2LPEN,HASH2LPEN" "0,1" bitfld.long 0x20 4. "CRYP2LPEN,CRYP2LPEN" "0,1" newline bitfld.long 0x20 0. "DCMILPEN,DCMILPEN" "0,1" line.long 0x24 "RCC_MC_AHB3LPENCLRR,This register is used by the MCU in order to clear the PERxLPEN bit" bitfld.long 0x24 12. "IPCCLPEN,IPCCLPEN" "0,1" bitfld.long 0x24 11. "HSEMLPEN,HSEMLPEN" "0,1" newline bitfld.long 0x24 7. "CRC2LPEN,CRC2LPEN" "0,1" bitfld.long 0x24 6. "RNG2LPEN,RNG2LPEN" "0,1" newline bitfld.long 0x24 5. "HASH2LPEN,HASH2LPEN" "0,1" bitfld.long 0x24 4. "CRYP2LPEN,CRYP2LPEN" "0,1" newline bitfld.long 0x24 0. "DCMILPEN,DCMILPEN" "0,1" line.long 0x28 "RCC_MC_AHB4LPENSETR,This register is used by the MCU in order to set the PERxLPEN bit." bitfld.long 0x28 10. "GPIOKLPEN,GPIOKLPEN" "0,1" bitfld.long 0x28 9. "GPIOJLPEN,GPIOJLPEN" "0,1" newline bitfld.long 0x28 8. "GPIOILPEN,GPIOILPEN" "0,1" bitfld.long 0x28 7. "GPIOHLPEN,GPIOHLPEN" "0,1" newline bitfld.long 0x28 6. "GPIOGLPEN,GPIOGLPEN" "0,1" bitfld.long 0x28 5. "GPIOFLPEN,GPIOFLPEN" "0,1" newline bitfld.long 0x28 4. "GPIOELPEN,GPIOELPEN" "0,1" bitfld.long 0x28 3. "GPIODLPEN,GPIODLPEN" "0,1" newline bitfld.long 0x28 2. "GPIOCLPEN,GPIOCLPEN" "0,1" bitfld.long 0x28 1. "GPIOBLPEN,GPIOBLPEN" "0,1" newline bitfld.long 0x28 0. "GPIOALPEN,GPIOALPEN" "0,1" line.long 0x2C "RCC_MC_AHB4LPENCLRR,This register is used by the MCU in order to clear the PERxLPEN bit of the corresponding peripheral." bitfld.long 0x2C 10. "GPIOKLPEN,GPIOKLPEN" "0,1" bitfld.long 0x2C 9. "GPIOJLPEN,GPIOJLPEN" "0,1" newline bitfld.long 0x2C 8. "GPIOILPEN,GPIOILPEN" "0,1" bitfld.long 0x2C 7. "GPIOHLPEN,GPIOHLPEN" "0,1" newline bitfld.long 0x2C 6. "GPIOGLPEN,GPIOGLPEN" "0,1" bitfld.long 0x2C 5. "GPIOFLPEN,GPIOFLPEN" "0,1" newline bitfld.long 0x2C 4. "GPIOELPEN,GPIOELPEN" "0,1" bitfld.long 0x2C 3. "GPIODLPEN,GPIODLPEN" "0,1" newline bitfld.long 0x2C 2. "GPIOCLPEN,GPIOCLPEN" "0,1" bitfld.long 0x2C 1. "GPIOBLPEN,GPIOBLPEN" "0,1" newline bitfld.long 0x2C 0. "GPIOALPEN,GPIOALPEN" "0,1" line.long 0x30 "RCC_MC_AXIMLPENSETR,This register is used by the MCU in order to set the PERxLPEN bit of the corresponding peripheral." bitfld.long 0x30 0. "SYSRAMLPEN,SYSRAMLPEN" "0,1" line.long 0x34 "RCC_MC_AXIMLPENCLRR,This register is used by the MCU in order to clear the PERxLPEN bit of the corresponding peripheral." bitfld.long 0x34 0. "SYSRAMLPEN,SYSRAMLPEN" "0,1" line.long 0x38 "RCC_MC_MLAHBLPENSETR,This register is used by the MCU in order to set the PERxLPEN bit of the corresponding peripheral." bitfld.long 0x38 4. "RETRAMLPEN,RETRAMLPEN" "0,1" bitfld.long 0x38 2. "SRAM34LPEN,SRAM34LPEN" "0,1" newline bitfld.long 0x38 1. "SRAM2LPEN,SRAM2LPEN" "0,1" bitfld.long 0x38 0. "SRAM1LPEN,SRAM1LPEN" "0,1" line.long 0x3C "RCC_MC_MLAHBLPENCLRR,This register is used by the MCU in order to clear the PERxLPEN bit of the corresponding peripheral." bitfld.long 0x3C 4. "RETRAMLPEN,RETRAMLPEN" "0,1" bitfld.long 0x3C 2. "SRAM34LPEN,SRAM34LPEN" "0,1" newline bitfld.long 0x3C 1. "SRAM2LPEN,SRAM2LPEN" "0,1" bitfld.long 0x3C 0. "SRAM1LPEN,SRAM1LPEN" "0,1" group.long 0xC00++0x3 line.long 0x0 "RCC_MC_RSTSCLRR,This register is used by the MCU to check the reset source." bitfld.long 0x0 10. "WWDG1RSTF,WWDG1RSTF" "0,1" bitfld.long 0x0 9. "IWDG2RSTF,IWDG2RSTF" "0,1" newline bitfld.long 0x0 8. "IWDG1RSTF,IWDG1RSTF" "0,1" bitfld.long 0x0 7. "MCSYSRSTF,MCSYSRSTF" "0,1" newline bitfld.long 0x0 6. "MPSYSRSTF,MPSYSRSTF" "0,1" bitfld.long 0x0 5. "MCURSTF,MCURSTF" "0,1" newline bitfld.long 0x0 4. "VCORERSTF,VCORERSTF" "0,1" bitfld.long 0x0 3. "HCSSRSTF,HCSSRSTF" "0,1" newline bitfld.long 0x0 2. "PADRSTF,PADRSTF" "0,1" bitfld.long 0x0 1. "BORRSTF,BORRSTF" "0,1" newline bitfld.long 0x0 0. "PORRSTF,PORRSTF" "0,1" group.long 0xC14++0x7 line.long 0x0 "RCC_MC_CIER,This register shall be used by the MCU to control the interrupt source enable. Refer to Section10.5: RCC interrupts for more details." bitfld.long 0x0 20. "WKUPIE,WKUPIE" "0,1" bitfld.long 0x0 16. "LSECSSIE,LSECSSIE" "0,1" newline bitfld.long 0x0 11. "PLL4DYIE,PLL4DYIE" "0,1" bitfld.long 0x0 10. "PLL3DYIE,PLL3DYIE" "0,1" newline bitfld.long 0x0 9. "PLL2DYIE,PLL2DYIE" "0,1" bitfld.long 0x0 8. "PLL1DYIE,PLL1DYIE" "0,1" newline bitfld.long 0x0 4. "CSIRDYIE,CSIRDYIE" "0,1" bitfld.long 0x0 3. "HSERDYIE,HSERDYIE" "0,1" newline bitfld.long 0x0 2. "HSIRDYIE,HSIRDYIE" "0,1" bitfld.long 0x0 1. "LSERDYIE,LSERDYIE" "0,1" newline bitfld.long 0x0 0. "LSIRDYIE,LSIRDYIE" "0,1" line.long 0x4 "RCC_MC_CIFR,This register shall be used by the MCU in order to read and clear the interrupt flags." bitfld.long 0x4 20. "WKUPF,WKUPF" "0,1" bitfld.long 0x4 16. "LSECSSF,LSECSSF" "0,1" newline bitfld.long 0x4 11. "PLL4DYF,PLL4DYF" "0,1" bitfld.long 0x4 10. "PLL3DYF,PLL3DYF" "0,1" newline bitfld.long 0x4 9. "PLL2DYF,PLL2DYF" "0,1" bitfld.long 0x4 8. "PLL1DYF,PLL1DYF" "0,1" newline bitfld.long 0x4 4. "CSIRDYF,CSIRDYF" "0,1" bitfld.long 0x4 3. "HSERDYF,HSERDYF" "0,1" newline bitfld.long 0x4 2. "HSIRDYF,HSIRDYF" "0,1" bitfld.long 0x4 1. "LSERDYF,LSERDYF" "0,1" newline bitfld.long 0x4 0. "LSIRDYF,LSIRDYF" "0,1" endif sif (cpuis("STM32MP157*")) group.long 0x0++0x3 line.long 0x0 "RCC_TZCR,This register is used to switch the RCC into secure mode. This register can only be accessed in secure mode." bitfld.long 0x0 1. "MCKPROT,MCKPROT" "0,1" bitfld.long 0x0 0. "TZEN,TZEN" "0,1" group.long 0xC++0x7 line.long 0x0 "RCC_OCENSETR,This register is used to control the oscillators.Writing to this register has no effect. writing will set the corresponding bits. Reading will give the effective values of each bit.If TZEN = MCKPROT = . this register can only be modified.." bitfld.long 0x0 11. "HSECSSON,HSECSSON" "0,1" bitfld.long 0x0 10. "HSEBYP,HSEBYP" "0,1" newline bitfld.long 0x0 9. "HSEKERON,HSEKERON" "0,1" bitfld.long 0x0 8. "HSEON,HSEON" "0,1" newline bitfld.long 0x0 7. "DIGBYP,DIGBYP" "0,1" bitfld.long 0x0 5. "CSIKERON,CSIKERON" "0,1" newline bitfld.long 0x0 4. "CSION,CSION" "0,1" bitfld.long 0x0 1. "HSIKERON,HSIKERON" "0,1" newline bitfld.long 0x0 0. "HSION,HSION" "0,1" line.long 0x4 "RCC_OCENCLRR,This register is used to control the oscillators.Writing to this register has no effect. writing will clear the corresponding bits. Reading will give the effective values of the enable bits.If TZEN = . this register can only be modified in.." bitfld.long 0x4 10. "HSEBYP,HSEBYP" "0,1" bitfld.long 0x4 9. "HSEKERON,HSEKERON" "0,1" newline bitfld.long 0x4 8. "HSEON,HSEON" "0,1" bitfld.long 0x4 7. "DIGBYP,DIGBYP" "0,1" newline bitfld.long 0x4 5. "CSIKERON,CSIKERON" "0,1" bitfld.long 0x4 4. "CSION,CSION" "0,1" newline bitfld.long 0x4 1. "HSIKERON,HSIKERON" "0,1" bitfld.long 0x4 0. "HSION,HSION" "0,1" group.long 0x18++0x1B line.long 0x0 "RCC_HSICFGR,This register is used to configure the HSI. If TZEN = . this register can only be modified in secure mode. Write access to this register is not allowed during the clock restore sequence. See Section: The clock restore sequence description for.." hexmask.long.word 0x0 16.--27. 1. "HSICAL,HSICAL" hexmask.long.byte 0x0 8.--14. 1. "HSITRIM,HSITRIM" newline bitfld.long 0x0 0.--1. "HSIDIV,HSIDIV" "0,1,2,3" line.long 0x4 "RCC_CSICFGR,This register is used to fine-tune the CSI frequency. If TZEN = MCKPROT = . this register can only be modified in secure mode. Write access to this register is not allowed during the clock restore sequence. See The clock restore sequence.." hexmask.long.byte 0x4 16.--23. 1. "CSICAL,CSICAL" hexmask.long.byte 0x4 8.--12. 1. "CSITRIM,CSITRIM" line.long 0x8 "RCC_MPCKSELR,This register is used to select the clock source for the MPU. If TZEN = . this register can only be modified in secure mode. Write access to this register is not allowed during the clock restore sequence. See Section: The clock restore.." rbitfld.long 0x8 31. "MPUSRCRDY,MPUSRCRDY" "0,1" bitfld.long 0x8 0.--1. "MPUSRC,MPUSRC" "0,1,2,3" line.long 0xC "RCC_ASSCKSELR,This register is used to select the clock source for the AXI sub-system. If TZEN = . this register can only be modified in secure mode. Write access to this register is not allowed during the clock restore sequence. See Section: The clock.." rbitfld.long 0xC 31. "AXISSRCRDY,AXISSRCRDY" "0,1" bitfld.long 0xC 0.--2. "AXISSRC,AXISSRC" "0,1,2,3,4,5,6,7" line.long 0x10 "RCC_RCK12SELR,This register is used to select the reference clock for PLL1 and PLL2. If TZEN = . this register can only be modified in secure mode. Write access to this register is not allowed during the clock restore sequence. See Section: The clock.." rbitfld.long 0x10 31. "PLL12SRCRDY,PLL12SRCRDY" "0,1" bitfld.long 0x10 0.--1. "PLL12SRC,PLL12SRC" "0,1,2,3" line.long 0x14 "RCC_MPCKDIVR,This register is used to control the MPU clock prescaler. Refer to Section: Sub-system clock generation for additional information. If TZEN = . this register can only be modified in secure mode." rbitfld.long 0x14 31. "MPUDIVRDY,MPUDIVRDY" "0,1" bitfld.long 0x14 0.--2. "MPUDIV,MPUDIV" "0,1,2,3,4,5,6,7" line.long 0x18 "RCC_AXIDIVR,This register is used to control the AXI Matrix clock prescaler. Refer to Section: Sub-system clock generation for additional information. If TZEN = . this register can only be modified in secure mode." rbitfld.long 0x18 31. "AXIDIVRDY,AXIDIVRDY" "0,1" bitfld.long 0x18 0.--2. "AXIDIV,AXIDIV" "0,1,2,3,4,5,6,7" group.long 0x3C++0xF line.long 0x0 "RCC_APB4DIVR,This register is used to control the APB4 clock divider. Refer to Section: Sub-system clock generation for additional information. If TZEN = . this register can only be modified in secure mode." rbitfld.long 0x0 31. "APB4DIVRDY,APB4DIVRDY" "0,1" bitfld.long 0x0 0.--2. "APB4DIV,APB4DIV" "0,1,2,3,4,5,6,7" line.long 0x4 "RCC_APB5DIVR,This register is used to control the APB5 clock divider. Refer to Section: Sub-system clock generation for additional information. If TZEN = . this register can only be modified in secure mode." rbitfld.long 0x4 31. "APB5DIVRDY,APB5DIVRDY" "0,1" bitfld.long 0x4 0.--2. "APB5DIV,APB5DIV" "0,1,2,3,4,5,6,7" line.long 0x8 "RCC_RTCDIVR,This register is used to divide the HSE clock for RTC. If TZEN = . this register can only be modified in secure mode." hexmask.long.byte 0x8 0.--5. 1. "RTCDIV,RTCDIV" line.long 0xC "RCC_MSSCKSELR,This register is used to select the clock source for the MCU sub-system. including the MCU itself. If TZEN = MCKPROT = . this register can only be modified in secure mode. Write access to this register is not allowed during the clock.." rbitfld.long 0xC 31. "MCUSSRCRDY,MCUSSRCRDY" "0,1" bitfld.long 0xC 0.--1. "MCUSSRC,MCUSSRC" "0,1,2,3" group.long 0x80++0x27 line.long 0x0 "RCC_PLL1CR,This register is used to control the PLL1. If TZEN = . this register can only be modified in secure mode. Write access to this register is not allowed during the clock restore sequence. See Section: The clock restore sequence description for.." bitfld.long 0x0 6. "DIVREN,DIVREN" "0,1" bitfld.long 0x0 5. "DIVQEN,DIVQEN" "0,1" newline bitfld.long 0x0 4. "DIVPEN,DIVPEN" "0,1" bitfld.long 0x0 2. "SSCG_CTRL,SSCG_CTRL" "0,1" newline rbitfld.long 0x0 1. "PLL1RDY,PLL1RDY" "0,1" bitfld.long 0x0 0. "PLLON,PLLON" "0,1" line.long 0x4 "RCC_PLL1CFGR1,This register is used to configure the PLL1. If TZEN = . this register can only be modified in secure mode. Write access to this register is not allowed during the clock restore sequence. See Section: The clock restore sequence description.." hexmask.long.byte 0x4 16.--21. 1. "DIVM1,DIVM1" hexmask.long.word 0x4 0.--8. 1. "DIVN,DIVN" line.long 0x8 "RCC_PLL1CFGR2,This register is used to configure the PLL1. If TZEN = . this register can only be modified in secure mode. Write access to this register is not allowed during the clock restore sequence. See Section: The clock restore sequence description.." hexmask.long.byte 0x8 16.--22. 1. "DIVR,DIVR" hexmask.long.byte 0x8 8.--14. 1. "DIVQ,DIVQ" newline hexmask.long.byte 0x8 0.--6. 1. "DIVP,DIVP" line.long 0xC "RCC_PLL1FRACR,This register is used to fine-tune the frequency of the PLL1 VCO. If TZEN = . this register can only be modified in secure mode. Write access to this register is not allowed during the clock restore sequence. See Section: The clock restore.." bitfld.long 0xC 16. "FRACLE,FRACLE" "0,1" hexmask.long.word 0xC 3.--15. 1. "FRACV,FRACV" line.long 0x10 "RCC_PLL1CSGR,This register is used to configure the PLL1.It is not recommended to change the content of this register when the PLL1 is enabled (PLLON = ). Refer to Section: Using the PLLs in spread spectrum mode for details. If TZEN = . this register can.." hexmask.long.word 0x10 16.--30. 1. "INC_STEP,INC_STEP" bitfld.long 0x10 15. "SSCG_MODE,SSCG_MODE" "0,1" newline bitfld.long 0x10 14. "RPDFN_DIS,RPDFN_DIS" "0,1" bitfld.long 0x10 13. "TPDFN_DIS,TPDFN_DIS" "0,1" newline hexmask.long.word 0x10 0.--12. 1. "MOD_PER,MOD_PER" line.long 0x14 "RCC_PLL2CR,This register is used to control the PLL2. If TZEN = . this register can only be modified in secure mode. Write access to this register is not allowed during the clock restore sequence. See Section: The clock restore sequence description for.." bitfld.long 0x14 6. "DIVREN,DIVREN" "0,1" bitfld.long 0x14 5. "DIVQEN,DIVQEN" "0,1" newline bitfld.long 0x14 4. "DIVPEN,DIVPEN" "0,1" bitfld.long 0x14 2. "SSCG_CTRL,SSCG_CTRL" "0,1" newline rbitfld.long 0x14 1. "PLL2RDY,PLL2RDY" "0,1" bitfld.long 0x14 0. "PLLON,PLLON" "0,1" line.long 0x18 "RCC_PLL2CFGR1,This register is used to configure the PLL2. If TZEN = . this register can only be modified in secure mode. Write access to this register is not allowed during the clock restore sequence. See Section: The clock restore sequence description.." hexmask.long.byte 0x18 16.--21. 1. "DIVM2,DIVM2" hexmask.long.word 0x18 0.--8. 1. "DIVN,DIVN" line.long 0x1C "RCC_PLL2CFGR2,This register is used to configure the PLL2. If TZEN = . this register can only be modified in secure mode. Write access to this register is not allowed during the clock restore sequence. See Section: The clock restore sequence description.." hexmask.long.byte 0x1C 16.--22. 1. "DIVR,DIVR" hexmask.long.byte 0x1C 8.--14. 1. "DIVQ,DIVQ" newline hexmask.long.byte 0x1C 0.--6. 1. "DIVP,DIVP" line.long 0x20 "RCC_PLL2FRACR,This register is used to fine-tune the frequency of the PLL2 VCO. If TZEN = . this register can only be modified in secure mode. Write access to this register is not allowed during the clock restore sequence. See Section: The clock restore.." bitfld.long 0x20 16. "FRACLE,FRACLE" "0,1" hexmask.long.word 0x20 3.--15. 1. "FRACV,FRACV" line.long 0x24 "RCC_PLL2CSGR,This register is used to configure the PLL2. It is not recommended to change the content of this register when the PLL2 is enabled (PLLON = ). Refer to Section: Using the PLLs in spread spectrum mode for details. If TZEN = . this register.." hexmask.long.word 0x24 16.--30. 1. "INC_STEP,INC_STEP" bitfld.long 0x24 15. "SSCG_MODE,SSCG_MODE" "0,1" newline bitfld.long 0x24 14. "RPDFN_DIS,RPDFN_DIS" "0,1" bitfld.long 0x24 13. "TPDFN_DIS,TPDFN_DIS" "0,1" newline hexmask.long.word 0x24 0.--12. 1. "MOD_PER,MOD_PER" group.long 0xC0++0x1B line.long 0x0 "RCC_I2C46CKSELR,This register is used to control the selection of the kernel clock for the I2C4 and I2C6. Note that changing the clock source on-the-fly is allowed. and will not generate any timing violation. however the user has to ensure that both the.." bitfld.long 0x0 0.--2. "I2C46SRC,I2C46SRC" "0,1,2,3,4,5,6,7" line.long 0x4 "RCC_SPI6CKSELR,This register is used to control the selection of the kernel clock for the SPI6. Note that changing the clock source on-the-fly is allowed. and will not generate any timing violation. however the user has to ensure that both the previous.." bitfld.long 0x4 0.--2. "SPI6SRC,SPI6SRC" "0,1,2,3,4,5,6,7" line.long 0x8 "RCC_UART1CKSELR,This register is used to control the selection of the kernel clock for the USART1. Note that changing the clock source on-the-fly is allowed. and will not generate any timing violation. however the user has to ensure that both the.." bitfld.long 0x8 0.--2. "UART1SRC,UART1SRC" "0,1,2,3,4,5,6,7" line.long 0xC "RCC_RNG1CKSELR,This register is used to control the selection of the kernel clock for the RNG1. Note that changing the clock source on-the-fly is allowed. and will not generate any timing violation. however the user has to ensure that both the previous.." bitfld.long 0xC 0.--1. "RNG1SRC,RNG1SRC" "0,1,2,3" line.long 0x10 "RCC_CPERCKSELR,This register is used to select an oscillator source as kernel clock for the per_ck clock. The per_ck clock is distributed to several peripherals. Refer to Section: Clock enabling delays." bitfld.long 0x10 0.--1. "CKPERSRC,CKPERSRC" "0,1,2,3" line.long 0x14 "RCC_STGENCKSELR,This register is used to select the peripheral clock for the STGEN block. Note that this clock is used to provide a time reference for the application. Refer to Section: Clock enabling delays. If TZEN = . this register can only be.." bitfld.long 0x14 0.--1. "STGENSRC,STGENSRC" "0,1,2,3" line.long 0x18 "RCC_DDRITFCR,This register is used to control the DDR interface. including the DDRC and DDRPHYC. If TZEN = . this register can only be modified in secure mode." hexmask.long.byte 0x18 28.--31. 1. "GSKP_DUR,GSKP_DUR" bitfld.long 0x18 25.--27. "DFILP_WIDTH,DFILP_WIDTH" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 24. "GSKPCTRL,GSKPCTRL" "0,1" bitfld.long 0x18 23. "GSKPMOD,GSKPMOD" "0,1" newline bitfld.long 0x18 20.--22. "DDRCKMOD,DDRCKMOD" "0,1,2,3,4,5,6,7" bitfld.long 0x18 19. "DPHYCTLRST,DPHYCTLRST" "0,1" newline bitfld.long 0x18 18. "DPHYRST,DPHYRST" "0,1" bitfld.long 0x18 17. "DPHYAPBRST,DPHYAPBRST" "0,1" newline bitfld.long 0x18 16. "DDRCORERST,DDRCORERST" "0,1" bitfld.long 0x18 15. "DDRCAXIRST,DDRCAXIRST" "0,1" newline bitfld.long 0x18 14. "DDRCAPBRST,DDRCAPBRST" "0,1" bitfld.long 0x18 11.--13. "KERDCG_DLY,KERDCG_DLY" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 10. "DDRPHYCAPBLPEN,DDRPHYCAPBLPEN" "0,1" bitfld.long 0x18 9. "DDRPHYCAPBEN,DDRPHYCAPBEN" "0,1" newline bitfld.long 0x18 8. "AXIDCGEN,AXIDCGEN" "0,1" bitfld.long 0x18 7. "DDRCAPBLPEN,DDRCAPBLPEN" "0,1" newline bitfld.long 0x18 6. "DDRCAPBEN,DDRCAPBEN" "0,1" bitfld.long 0x18 5. "DDRPHYCLPEN,DDRPHYCLPEN" "0,1" newline bitfld.long 0x18 4. "DDRPHYCEN,DDRPHYCEN" "0,1" bitfld.long 0x18 3. "DDRC2LPEN,DDRC2LPEN" "0,1" newline bitfld.long 0x18 2. "DDRC2EN,DDRC2EN" "0,1" bitfld.long 0x18 1. "DDRC1LPEN,DDRC1LPEN" "0,1" newline bitfld.long 0x18 0. "DDRC1EN,DDRC1EN" "0,1" group.long 0x100++0x13 line.long 0x0 "RCC_MP_BOOTCR,This register is used to control the HOLD boot function when the system exits from Standby. Refer to Section: MCU HOLD_BOOT after processor reset. This register is reset when a system reset occurs. but not when the circuit exits from.." bitfld.long 0x0 1. "MPU_BEN,MPU_BEN" "0,1" bitfld.long 0x0 0. "MCU_BEN,MCU_BEN" "0,1" line.long 0x4 "RCC_MP_SREQSETR,Writing has no effect. reading will return the values of the bits. Writing a sets the corresponding bit to . The MCU cannot access to this register. If TZEN = . this register can only be modified in secure mode." bitfld.long 0x4 1. "STPREQ_P1,STPREQ_P1" "0,1" bitfld.long 0x4 0. "STPREQ_P0,STPREQ_P0" "0,1" line.long 0x8 "RCC_MP_SREQCLRR,Writing has no effect. reading will return the effective values of the bits. Writing a sets the corresponding bit to . The MCU cannot access to this register. If TZEN = . this register can only be modified in secure mode." bitfld.long 0x8 1. "STPREQ_P1,STPREQ_P1" "0,1" bitfld.long 0x8 0. "STPREQ_P0,STPREQ_P0" "0,1" line.long 0xC "RCC_MP_GCR,The register contains global control bits. If TZEN = . this register can only be modified in secure mode." bitfld.long 0xC 0. "BOOT_MCU,BOOT_MCU" "0,1" line.long 0x10 "RCC_MP_APRSTCR,This register is used to control the behavior of the warm reset. If TZEN = . this register can only be modified in secure mode." hexmask.long.byte 0x10 8.--14. 1. "RSTTO,RSTTO" bitfld.long 0x10 0. "RDCTLEN,RDCTLEN" "0,1" rgroup.long 0x114++0x3 line.long 0x0 "RCC_MP_APRSTSR,This register provides a status of the RDCTL. If TZEN = . this register can only be modified in secure mode." hexmask.long.byte 0x0 8.--14. 1. "RSTTOV,RSTTOV" group.long 0x140++0x7 line.long 0x0 "RCC_BDCR,This register is used to control the LSE function. Wait states are inserted in case of successive write accesses to this register. The number of wait states may be up to 7 cycles of AHB4 clock.After a system reset. the register RCC_BDCR is.." bitfld.long 0x0 31. "VSWRST,VSWRST" "0,1" bitfld.long 0x0 20. "RTCCKEN,RTCCKEN" "0,1" newline rbitfld.long 0x0 16.--17. "RTCSRC,RTCSRC" "0,1,2,3" rbitfld.long 0x0 9. "LSECSSD,LSECSSD" "0,1" newline bitfld.long 0x0 8. "LSECSSON,LSECSSON" "0,1" bitfld.long 0x0 4.--5. "LSEDRV,LSEDRV" "0,1,2,3" newline rbitfld.long 0x0 3. "DIGBYP,DIGBYP" "0,1" rbitfld.long 0x0 2. "LSERDY,LSERDY" "0,1" newline bitfld.long 0x0 1. "LSEBYP,LSEBYP" "0,1" bitfld.long 0x0 0. "LSEON,LSEON" "0,1" line.long 0x4 "RCC_RDLSICR,This register is used to control the minimum NRST active duration and LSI function.0 to 7 wait states are inserted for word. half-word and byte accesses. Wait states are inserted in case of successive accesses to this register.This register.." hexmask.long.byte 0x4 27.--31. 1. "SPARE,SPARE" bitfld.long 0x4 24.--26. "EADLY,EADLY" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x4 16.--20. 1. "MRD,MRD" rbitfld.long 0x4 1. "LSIRDY,LSIRDY" "0,1" newline bitfld.long 0x4 0. "LSION,LSION" "0,1" group.long 0x180++0x27 line.long 0x0 "RCC_APB4RSTSETR,This register is used to activate the reset of the corresponding peripheral. Writing has no effect. reading will return the effective values of the corresponding bits. Writing a activates the reset of the corresponding peripheral." bitfld.long 0x0 16. "USBPHYRST,USBPHYRST" "0,1" bitfld.long 0x0 8. "DDRPERFMRST,DDRPERFMRST" "0,1" newline bitfld.long 0x0 4. "DSIRST,DSIRST" "0,1" bitfld.long 0x0 0. "LTDCRST,LTDCRST" "0,1" line.long 0x4 "RCC_APB4RSTCLRR,This register is used to release the reset of the corresponding peripheral. Writing has no effect. reading will return the effective values of the corresponding bits. Writing a releases the reset of the corresponding peripheral." bitfld.long 0x4 16. "USBPHYRST,USBPHYRST" "0,1" bitfld.long 0x4 8. "DDRPERFMRST,DDRPERFMRST" "0,1" newline bitfld.long 0x4 4. "DSIRST,DSIRST" "0,1" bitfld.long 0x4 0. "LTDCRST,LTDCRST" "0,1" line.long 0x8 "RCC_APB5RSTSETR,This register is used to activate the reset of the corresponding peripheral. Writing has no effect. reading will return the effective values of the corresponding bits. Writing a activates the reset of the corresponding peripheral. If.." bitfld.long 0x8 20. "STGENRST,STGENRST" "0,1" bitfld.long 0x8 4. "USART1RST,USART1RST" "0,1" newline bitfld.long 0x8 3. "I2C6RST,I2C6RST" "0,1" bitfld.long 0x8 2. "I2C4RST,I2C4RST" "0,1" newline bitfld.long 0x8 0. "SPI6RST,SPI6RST" "0,1" line.long 0xC "RCC_APB5RSTCLRR,This register is used to release the reset of the corresponding peripheral. Writing has no effect. reading will return the effective values of the corresponding bits. Writing a releases the reset of the corresponding peripheral. If TZEN.." bitfld.long 0xC 20. "STGENRST,STGENRST" "0,1" bitfld.long 0xC 4. "USART1RST,USART1RST" "0,1" newline bitfld.long 0xC 3. "I2C6RST,I2C6RST" "0,1" bitfld.long 0xC 2. "I2C4RST,I2C4RST" "0,1" newline bitfld.long 0xC 0. "SPI6RST,SPI6RST" "0,1" line.long 0x10 "RCC_AHB5RSTSETR,This register is used to activate the reset of the corresponding peripheral. Writing has no effect. reading will return the effective values of the corresponding bits. Writing a activates the reset of the corresponding peripheral. If.." bitfld.long 0x10 16. "AXIMCRST,AXIMCRST" "0,1" bitfld.long 0x10 6. "RNG1RST,RNG1RST" "0,1" newline bitfld.long 0x10 5. "HASH1RST,HASH1RST" "0,1" bitfld.long 0x10 4. "CRYP1RST,CRYP1RST" "0,1" newline bitfld.long 0x10 0. "GPIOZRST,GPIOZRST" "0,1" line.long 0x14 "RCC_AHB5RSTCLRR,This register is used to release the reset of the corresponding peripheral. Writing has no effect. reading will return the effective values of the corresponding bits. Writing a releases the reset of the corresponding peripheral. If TZEN.." bitfld.long 0x14 16. "AXIMCRST,AXIMCRST" "0,1" bitfld.long 0x14 6. "RNG1RST,RNG1RST" "0,1" newline bitfld.long 0x14 5. "HASH1RST,HASH1RST" "0,1" bitfld.long 0x14 4. "CRYP1RST,CRYP1RST" "0,1" newline bitfld.long 0x14 0. "GPIOZRST,GPIOZRST" "0,1" line.long 0x18 "RCC_AHB6RSTSETR,This register is used to activate the reset of the corresponding peripheral. Writing has no effect. reading will return the effective values of the corresponding bits. Writing a activates the reset of the corresponding peripheral." bitfld.long 0x18 24. "USBHRST,USBHRST" "0,1" bitfld.long 0x18 20. "CRC1RST,CRC1RST" "0,1" newline bitfld.long 0x18 17. "SDMMC2RST,SDMMC2RST" "0,1" bitfld.long 0x18 16. "SDMMC1RST,SDMMC1RST" "0,1" newline bitfld.long 0x18 14. "QSPIRST,QSPIRST" "0,1" bitfld.long 0x18 12. "FMCRST,FMCRST" "0,1" newline bitfld.long 0x18 10. "ETHMACRST,ETHMACRST" "0,1" bitfld.long 0x18 5. "GPURST,GPURST" "0,1" line.long 0x1C "RCC_AHB6RSTCLRR,This register is used to release the reset of the corresponding peripheral. Writing has no effect. reading will return the effective values of the corresponding bits. Writing a releases the reset of the corresponding peripheral." bitfld.long 0x1C 24. "USBHRST,USBHRST" "0,1" bitfld.long 0x1C 20. "CRC1RST,CRC1RST" "0,1" newline bitfld.long 0x1C 17. "SDMMC2RST,SDMMC2RST" "0,1" bitfld.long 0x1C 16. "SDMMC1RST,SDMMC1RST" "0,1" newline bitfld.long 0x1C 14. "QSPIRST,QSPIRST" "0,1" bitfld.long 0x1C 12. "FMCRST,FMCRST" "0,1" newline bitfld.long 0x1C 10. "ETHMACRST,ETHMACRST" "0,1" line.long 0x20 "RCC_TZAHB6RSTSETR,This register is used to activate the reset of the corresponding peripheral. Writing has no effect. reading will return the effective values of the corresponding bits. Writing a activates the reset of the corresponding peripheral. If.." bitfld.long 0x20 0. "MDMARST,MDMARST" "0,1" line.long 0x24 "RCC_TZAHB6RSTCLRR,This register is used to release the reset of the corresponding peripheral. Writing has no effect. reading will return the effective values of the corresponding bits. Writing a releases the reset of the corresponding peripheral. If.." bitfld.long 0x24 0. "MDMARST,MDMARST" "0,1" group.long 0x200++0x27 line.long 0x0 "RCC_MP_APB4ENSETR,This register is used to set the peripheral clock enable bit of the corresponding peripheral to . It shall be used to allocate a peripheral to the MPU. Writing has no effect. reading will return the effective values of the.." bitfld.long 0x0 20. "STGENROEN,STGENROEN" "0,1" bitfld.long 0x0 16. "USBPHYEN,USBPHYEN" "0,1" newline bitfld.long 0x0 15. "IWDG2APBEN,IWDG2APBEN" "0,1" bitfld.long 0x0 8. "DDRPERFMEN,DDRPERFMEN" "0,1" newline bitfld.long 0x0 4. "DSIEN,DSIEN" "0,1" bitfld.long 0x0 0. "LTDCEN,LTDCEN" "0,1" line.long 0x4 "RCC_MP_APB4ENCLRR,This register is used to clear the peripheral clock enable bit of the corresponding peripheral. It shall be used to deallocate a peripheral from MPU. Writing has no effect. reading will return the effective values of the corresponding.." bitfld.long 0x4 20. "STGENROEN,STGENROEN" "0,1" bitfld.long 0x4 16. "USBPHYEN,USBPHYEN" "0,1" newline bitfld.long 0x4 15. "IWDG2APBEN,IWDG2APBEN" "0,1" bitfld.long 0x4 8. "DDRPERFMEN,DDRPERFMEN" "0,1" newline bitfld.long 0x4 4. "DSIEN,DSIEN" "0,1" bitfld.long 0x4 0. "LTDCEN,LTDCEN" "0,1" line.long 0x8 "RCC_MP_APB5ENSETR,This register is used to set the peripheral clock enable bit of the corresponding peripheral to . It shall be used to allocate a peripheral to the MPU. Writing has no effect. reading will return the effective values of the.." bitfld.long 0x8 20. "STGENEN,STGENEN" "0,1" bitfld.long 0x8 16. "BSECEN,BSECEN" "0,1" newline bitfld.long 0x8 15. "IWDG1APBEN,IWDG1APBEN" "0,1" bitfld.long 0x8 13. "TZPCEN,TZPCEN" "0,1" newline bitfld.long 0x8 12. "TZC2EN,TZC2EN" "0,1" bitfld.long 0x8 11. "TZC1EN,TZC1EN" "0,1" newline bitfld.long 0x8 8. "RTCAPBEN,RTCAPBEN" "0,1" bitfld.long 0x8 4. "USART1EN,USART1EN" "0,1" newline bitfld.long 0x8 3. "I2C6EN,I2C6EN" "0,1" bitfld.long 0x8 2. "I2C4EN,I2C4EN" "0,1" newline bitfld.long 0x8 0. "SPI6EN,SPI6EN" "0,1" line.long 0xC "RCC_MP_APB5ENCLRR,This register is used to clear the peripheral clock enable bit of the corresponding peripheral. It shall be used to deallocate a peripheral from MPU. Writing has no effect. reading will return the effective values of the corresponding.." bitfld.long 0xC 20. "STGENEN,STGENEN" "0,1" bitfld.long 0xC 16. "BSECEN,BSECEN" "0,1" newline bitfld.long 0xC 15. "IWDG1APBEN,IWDG1APBEN" "0,1" bitfld.long 0xC 13. "TZPCEN,TZPCEN" "0,1" newline bitfld.long 0xC 12. "TZC2EN,TZC2EN" "0,1" bitfld.long 0xC 11. "TZC1EN,TZC1EN" "0,1" newline bitfld.long 0xC 8. "RTCAPBEN,RTCAPBEN" "0,1" bitfld.long 0xC 4. "USART1EN,USART1EN" "0,1" newline bitfld.long 0xC 3. "I2C6EN,I2C6EN" "0,1" bitfld.long 0xC 2. "I2C4EN,I2C4EN" "0,1" newline bitfld.long 0xC 0. "SPI6EN,SPI6EN" "0,1" line.long 0x10 "RCC_MP_AHB5ENSETR,This register is used to set the peripheral clock enable bit of the corresponding peripheral to . It shall be used to allocate a peripheral to the MPU. Writing has no effect. reading will return the effective values of the.." bitfld.long 0x10 16. "AXIMCEN,AXIMCEN" "0,1" bitfld.long 0x10 8. "BKPSRAMEN,BKPSRAMEN" "0,1" newline bitfld.long 0x10 6. "RNG1EN,RNG1EN" "0,1" bitfld.long 0x10 5. "HASH1EN,HASH1EN" "0,1" newline bitfld.long 0x10 4. "CRYP1EN,CRYP1EN" "0,1" bitfld.long 0x10 0. "GPIOZEN,GPIOZEN" "0,1" line.long 0x14 "RCC_MP_AHB5ENCLRR,This register is used to clear the peripheral clock enable bit of the corresponding peripheral. It shall be used to deallocate a peripheral from MPU. Writing has no effect. reading will return the effective values of the corresponding.." bitfld.long 0x14 16. "AXIMCEN,AXIMCEN" "0,1" bitfld.long 0x14 8. "BKPSRAMEN,BKPSRAMEN" "0,1" newline bitfld.long 0x14 6. "RNG1EN,RNG1EN" "0,1" bitfld.long 0x14 5. "HASH1EN,HASH1EN" "0,1" newline bitfld.long 0x14 4. "CRYP1EN,CRYP1EN" "0,1" bitfld.long 0x14 0. "GPIOZEN,GPIOZEN" "0,1" line.long 0x18 "RCC_MP_AHB6ENSETR,This register is used to set the peripheral clock enable bit of the corresponding peripheral to . It shall be used to allocate a peripheral to the MPU. Writing has no effect. reading will return the effective values of the.." bitfld.long 0x18 24. "USBHEN,USBHEN" "0,1" bitfld.long 0x18 20. "CRC1EN,CRC1EN" "0,1" newline bitfld.long 0x18 17. "SDMMC2EN,SDMMC2EN" "0,1" bitfld.long 0x18 16. "SDMMC1EN,SDMMC1EN" "0,1" newline bitfld.long 0x18 14. "QSPIEN,QSPIEN" "0,1" bitfld.long 0x18 12. "FMCEN,FMCEN" "0,1" newline bitfld.long 0x18 10. "ETHMACEN,ETHMACEN" "0,1" bitfld.long 0x18 9. "ETHRXEN,ETHRXEN" "0,1" newline bitfld.long 0x18 8. "ETHTXEN,ETHTXEN" "0,1" bitfld.long 0x18 7. "ETHCKEN,ETHCKEN" "0,1" newline bitfld.long 0x18 5. "GPUEN,GPUEN" "0,1" bitfld.long 0x18 0. "MDMAEN,MDMAEN" "0,1" line.long 0x1C "RCC_MP_AHB6ENCLRR,This register is used to clear the peripheral clock enable bit of the corresponding peripheral. It shall be used to deallocate a peripheral from MPU. Writing has no effect. reading will return the effective values of the corresponding.." bitfld.long 0x1C 24. "USBHEN,USBHEN" "0,1" bitfld.long 0x1C 20. "CRC1EN,CRC1EN" "0,1" newline bitfld.long 0x1C 17. "SDMMC2EN,SDMMC2EN" "0,1" bitfld.long 0x1C 16. "SDMMC1EN,SDMMC1EN" "0,1" newline bitfld.long 0x1C 14. "QSPIEN,QSPIEN" "0,1" bitfld.long 0x1C 12. "FMCEN,FMCEN" "0,1" newline bitfld.long 0x1C 10. "ETHMACEN,ETHMACEN" "0,1" bitfld.long 0x1C 9. "ETHRXEN,ETHRXEN" "0,1" newline bitfld.long 0x1C 8. "ETHTXEN,ETHTXEN" "0,1" bitfld.long 0x1C 7. "ETHCKEN,ETHCKEN" "0,1" newline bitfld.long 0x1C 5. "GPUEN,GPUEN" "0,1" bitfld.long 0x1C 0. "MDMAEN,MDMAEN" "0,1" line.long 0x20 "RCC_MP_TZAHB6ENSETR,This register is used to set the peripheral clock enable bit of the corresponding peripheral to . It shall be used to allocate a peripheral to the MPU. Writing has no effect. reading will return the effective values of the.." bitfld.long 0x20 0. "MDMAEN,MDMAEN" "0,1" line.long 0x24 "RCC_MP_TZAHB6ENCLRR,This register is used to clear the peripheral clock enable bit of the corresponding peripheral. It shall be used to deallocate a peripheral from MPU. Writing has no effect. reading will return the effective values of the.." bitfld.long 0x24 0. "MDMAEN,MDMAEN" "0,1" group.long 0x280++0x1F line.long 0x0 "RCC_MC_APB4ENSETR,This register is used to set the peripheral clock enable bit" bitfld.long 0x0 20. "STGENROEN,STGENROEN" "0,1" bitfld.long 0x0 16. "USBPHYEN,USBPHYEN" "0,1" newline bitfld.long 0x0 8. "DDRPERFMEN,DDRPERFMEN" "0,1" bitfld.long 0x0 4. "DSIEN,DSIEN" "0,1" newline bitfld.long 0x0 0. "LTDCEN,LTDCEN" "0,1" line.long 0x4 "RCC_MC_APB4ENCLRR,This register is used to clear the peripheral clock enable bit" bitfld.long 0x4 20. "STGENROEN,STGENROEN" "0,1" bitfld.long 0x4 16. "USBPHYEN,USBPHYEN" "0,1" newline bitfld.long 0x4 8. "DDRPERFMEN,DDRPERFMEN" "0,1" bitfld.long 0x4 4. "DSIEN,DSIEN" "0,1" newline bitfld.long 0x4 0. "LTDCEN,LTDCEN" "0,1" line.long 0x8 "RCC_MC_APB5ENSETR,This register is used to set the peripheral clock enable bit" bitfld.long 0x8 20. "STGENEN,STGENEN" "0,1" bitfld.long 0x8 16. "BSECEN,BSECEN" "0,1" newline bitfld.long 0x8 13. "TZPCEN,TZPCEN" "0,1" bitfld.long 0x8 12. "TZC2EN,TZC2EN" "0,1" newline bitfld.long 0x8 11. "TZC1EN,TZC1EN" "0,1" bitfld.long 0x8 8. "RTCAPBEN,RTCAPBEN" "0,1" newline bitfld.long 0x8 4. "USART1EN,USART1EN" "0,1" bitfld.long 0x8 3. "I2C6EN,I2C6EN" "0,1" newline bitfld.long 0x8 2. "I2C4EN,I2C4EN" "0,1" bitfld.long 0x8 0. "SPI6EN,SPI6EN" "0,1" line.long 0xC "RCC_MC_APB5ENCLRR,This register is used to clear the peripheral clock enable bit" bitfld.long 0xC 20. "STGENEN,STGENEN" "0,1" bitfld.long 0xC 16. "BSECEN,BSECEN" "0,1" newline bitfld.long 0xC 13. "TZPCEN,TZPCEN" "0,1" bitfld.long 0xC 12. "TZC2EN,TZC2EN" "0,1" newline bitfld.long 0xC 11. "TZC1EN,TZC1EN" "0,1" bitfld.long 0xC 8. "RTCAPBEN,RTCAPBEN" "0,1" newline bitfld.long 0xC 4. "USART1EN,USART1EN" "0,1" bitfld.long 0xC 3. "I2C6EN,I2C6EN" "0,1" newline bitfld.long 0xC 2. "I2C4EN,I2C4EN" "0,1" bitfld.long 0xC 0. "SPI6EN,SPI6EN" "0,1" line.long 0x10 "RCC_MC_AHB5ENSETR,This register is used to set the peripheral clock enable bit If TZEN = . this register can only be modified in secure mode." bitfld.long 0x10 8. "BKPSRAMEN,BKPSRAMEN" "0,1" bitfld.long 0x10 6. "RNG1EN,RNG1EN" "0,1" newline bitfld.long 0x10 5. "HASH1EN,HASH1EN" "0,1" bitfld.long 0x10 4. "CRYP1EN,CRYP1EN" "0,1" newline bitfld.long 0x10 0. "GPIOZEN,GPIOZEN" "0,1" line.long 0x14 "RCC_MC_AHB5ENCLRR,This register is used to clear the peripheral clock enable bit If TZEN = . this register can only be modified in secure mode." bitfld.long 0x14 8. "BKPSRAMEN,BKPSRAMEN" "0,1" bitfld.long 0x14 6. "RNG1EN,RNG1EN" "0,1" newline bitfld.long 0x14 5. "HASH1EN,HASH1EN" "0,1" bitfld.long 0x14 4. "CRYP1EN,CRYP1EN" "0,1" newline bitfld.long 0x14 0. "GPIOZEN,GPIOZEN" "0,1" line.long 0x18 "RCC_MC_AHB6ENSETR,This register is used to set the peripheral clock enable bit" bitfld.long 0x18 24. "USBHEN,USBHEN" "0,1" bitfld.long 0x18 20. "CRC1EN,CRC1EN" "0,1" newline bitfld.long 0x18 17. "SDMMC2EN,SDMMC2EN" "0,1" bitfld.long 0x18 16. "SDMMC1EN,SDMMC1EN" "0,1" newline bitfld.long 0x18 14. "QSPIEN,QSPIEN" "0,1" bitfld.long 0x18 12. "FMCEN,FMCEN" "0,1" newline bitfld.long 0x18 10. "ETHMACEN,ETHMACEN" "0,1" bitfld.long 0x18 9. "ETHRXEN,ETHRXEN" "0,1" newline bitfld.long 0x18 8. "ETHTXEN,ETHTXEN" "0,1" bitfld.long 0x18 7. "ETHCKEN,ETHCKEN" "0,1" newline bitfld.long 0x18 5. "GPUEN,GPUEN" "0,1" bitfld.long 0x18 0. "MDMAEN,MDMAEN" "0,1" line.long 0x1C "RCC_MC_AHB6ENCLRR,This register is used to clear the peripheral clock enable bit" bitfld.long 0x1C 24. "USBHEN,USBHEN" "0,1" bitfld.long 0x1C 20. "CRC1EN,CRC1EN" "0,1" newline bitfld.long 0x1C 17. "SDMMC2EN,SDMMC2EN" "0,1" bitfld.long 0x1C 16. "SDMMC1EN,SDMMC1EN" "0,1" newline bitfld.long 0x1C 14. "QSPIEN,QSPIEN" "0,1" bitfld.long 0x1C 12. "FMCEN,FMCEN" "0,1" newline bitfld.long 0x1C 10. "ETHMACEN,ETHMACEN" "0,1" bitfld.long 0x1C 9. "ETHRXEN,ETHRXEN" "0,1" newline bitfld.long 0x1C 8. "ETHTXEN,ETHTXEN" "0,1" bitfld.long 0x1C 7. "ETHCKEN,ETHCKEN" "0,1" newline bitfld.long 0x1C 5. "GPUEN,GPUEN" "0,1" bitfld.long 0x1C 0. "MDMAEN,MDMAEN" "0,1" group.long 0x300++0x27 line.long 0x0 "RCC_MP_APB4LPENSETR,This register is used by the MCU in order to clear the PERxLPEN bits" bitfld.long 0x0 21. "STGENROSTPEN,STGENROSTPEN" "0,1" bitfld.long 0x0 20. "STGENROLPEN,STGENROLPEN" "0,1" newline bitfld.long 0x0 16. "USBPHYLPEN,USBPHYLPEN" "0,1" bitfld.long 0x0 15. "IWDG2APBLPEN,IWDG2APBLPEN" "0,1" newline bitfld.long 0x0 8. "DDRPERFMLPEN,DDRPERFMLPEN" "0,1" bitfld.long 0x0 4. "DSILPEN,DSILPEN" "0,1" newline bitfld.long 0x0 0. "LTDCLPEN,LTDCLPEN" "0,1" line.long 0x4 "RCC_MP_APB4LPENCLRR,This register is used by the MCU" bitfld.long 0x4 21. "STGENROSTPEN,STGENROSTPEN" "0,1" bitfld.long 0x4 20. "STGENROLPEN,STGENROLPEN" "0,1" newline bitfld.long 0x4 16. "USBPHYLPEN,USBPHYLPEN" "0,1" bitfld.long 0x4 15. "IWDG2APBLPEN,IWDG2APBLPEN" "0,1" newline bitfld.long 0x4 8. "DDRPERFMLPEN,DDRPERFMLPEN" "0,1" bitfld.long 0x4 4. "DSILPEN,DSILPEN" "0,1" newline bitfld.long 0x4 0. "LTDCLPEN,LTDCLPEN" "0,1" line.long 0x8 "RCC_MP_APB5LPENSETR,This register is used by the MCU in order to clear the PERxLPEN bits If TZEN = . this register can only be modified in secure mode." bitfld.long 0x8 21. "STGENSTPEN,STGENSTPEN" "0,1" bitfld.long 0x8 20. "STGENLPEN,STGENLPEN" "0,1" newline bitfld.long 0x8 16. "BSECLPEN,BSECLPEN" "0,1" bitfld.long 0x8 15. "IWDG1APBLPEN,IWDG1APBLPEN" "0,1" newline bitfld.long 0x8 13. "TZPCLPEN,TZPCLPEN" "0,1" bitfld.long 0x8 12. "TZC2LPEN,TZC2LPEN" "0,1" newline bitfld.long 0x8 11. "TZC1LPEN,TZC1LPEN" "0,1" bitfld.long 0x8 8. "RTCAPBLPEN,RTCAPBLPEN" "0,1" newline bitfld.long 0x8 4. "USART1LPEN,USART1LPEN" "0,1" bitfld.long 0x8 3. "I2C6LPEN,I2C6LPEN" "0,1" newline bitfld.long 0x8 2. "I2C4LPEN,I2C4LPEN" "0,1" bitfld.long 0x8 0. "SPI6LPEN,SPI6LPEN" "0,1" line.long 0xC "RCC_MP_APB5LPENCLRR,This register is used by the Mpu." bitfld.long 0xC 21. "STGENSTPEN,STGENSTPEN" "0,1" bitfld.long 0xC 20. "STGENLPEN,STGENLPEN" "0,1" newline bitfld.long 0xC 16. "BSECLPEN,BSECLPEN" "0,1" bitfld.long 0xC 15. "IWDG1APBLPEN,IWDG1APBLPEN" "0,1" newline bitfld.long 0xC 13. "TZPCLPEN,TZPCLPEN" "0,1" bitfld.long 0xC 12. "TZC2LPEN,TZC2LPEN" "0,1" newline bitfld.long 0xC 11. "TZC1LPEN,TZC1LPEN" "0,1" bitfld.long 0xC 8. "RTCAPBLPEN,RTCAPBLPEN" "0,1" newline bitfld.long 0xC 4. "USART1LPEN,USART1LPEN" "0,1" bitfld.long 0xC 3. "I2C6LPEN,I2C6LPEN" "0,1" newline bitfld.long 0xC 2. "I2C4LPEN,I2C4LPEN" "0,1" bitfld.long 0xC 0. "SPI6LPEN,SPI6LPEN" "0,1" line.long 0x10 "RCC_MP_AHB5LPENSETR,This register is used by the MCU in order to clear the PERxLPEN bits If TZEN = . this register can only be modified in secure mode." bitfld.long 0x10 8. "BKPSRAMLPEN,BKPSRAMLPEN" "0,1" bitfld.long 0x10 6. "RNG1LPEN,RNG1LPEN" "0,1" newline bitfld.long 0x10 5. "HASH1LPEN,HASH1LPEN" "0,1" bitfld.long 0x10 4. "CRYP1LPEN,CRYP1LPEN" "0,1" newline bitfld.long 0x10 0. "GPIOZLPEN,GPIOZLPEN" "0,1" line.long 0x14 "RCC_MP_AHB5LPENCLRR,This register is used by the MCU" bitfld.long 0x14 8. "BKPSRAMLPEN,BKPSRAMLPEN" "0,1" bitfld.long 0x14 6. "RNG1LPEN,RNG1LPEN" "0,1" newline bitfld.long 0x14 5. "HASH1LPEN,HASH1LPEN" "0,1" bitfld.long 0x14 4. "CRYP1LPEN,CRYP1LPEN" "0,1" newline bitfld.long 0x14 0. "GPIOZLPEN,GPIOZLPEN" "0,1" line.long 0x18 "RCC_MP_AHB6LPENSETR,This register is used by the MCU in order to clear the PERxLPEN bits" bitfld.long 0x18 24. "USBHLPEN,USBHLPEN" "0,1" bitfld.long 0x18 20. "CRC1LPEN,CRC1LPEN" "0,1" newline bitfld.long 0x18 17. "SDMMC2LPEN,SDMMC2LPEN" "0,1" bitfld.long 0x18 16. "SDMMC1LPEN,SDMMC1LPEN" "0,1" newline bitfld.long 0x18 14. "QSPILPEN,QSPILPEN" "0,1" bitfld.long 0x18 12. "FMCLPEN,FMCLPEN" "0,1" newline bitfld.long 0x18 11. "ETHSTPEN,ETHSTPEN" "0,1" bitfld.long 0x18 10. "ETHMACLPEN,ETHMACLPEN" "0,1" newline bitfld.long 0x18 9. "ETHRXLPEN,ETHRXLPEN" "0,1" bitfld.long 0x18 8. "ETHTXLPEN,ETHTXLPEN" "0,1" newline bitfld.long 0x18 7. "ETHCKLPEN,ETHCKLPEN" "0,1" bitfld.long 0x18 5. "GPULPEN,GPULPEN" "0,1" newline bitfld.long 0x18 0. "MDMALPEN,MDMALPEN" "0,1" line.long 0x1C "RCC_MP_AHB6LPENCLRR,This register is used by the MCU in order to clear the PERxLPEN bits" bitfld.long 0x1C 24. "USBHLPEN,USBHLPEN" "0,1" bitfld.long 0x1C 20. "CRC1LPEN,CRC1LPEN" "0,1" newline bitfld.long 0x1C 17. "SDMMC2LPEN,SDMMC2LPEN" "0,1" bitfld.long 0x1C 16. "SDMMC1LPEN,SDMMC1LPEN" "0,1" newline bitfld.long 0x1C 14. "QSPILPEN,QSPILPEN" "0,1" bitfld.long 0x1C 12. "FMCLPEN,FMCLPEN" "0,1" newline bitfld.long 0x1C 11. "ETHSTPEN,ETHSTPEN" "0,1" bitfld.long 0x1C 10. "ETHMACLPEN,ETHMACLPEN" "0,1" newline bitfld.long 0x1C 9. "ETHRXLPEN,ETHRXLPEN" "0,1" bitfld.long 0x1C 8. "ETHTXLPEN,ETHTXLPEN" "0,1" newline bitfld.long 0x1C 7. "ETHCKLPEN,ETHCKLPEN" "0,1" bitfld.long 0x1C 5. "GPULPEN,GPULPEN" "0,1" newline bitfld.long 0x1C 0. "MDMALPEN,MDMALPEN" "0,1" line.long 0x20 "RCC_MP_TZAHB6LPENSETR,This register is used by the MCU in order to clear the PERxLPEN bits If TZEN = . this register can only be modified in secure mode." bitfld.long 0x20 0. "MDMALPEN,MDMALPEN" "0,1" line.long 0x24 "RCC_MP_TZAHB6LPENCLRR,This register is used by the MCU in order to clear the PERxLPEN bits If TZEN = . this register can only be modified in secure mode." bitfld.long 0x24 0. "MDMALPEN,MDMALPEN" "0,1" group.long 0x380++0x1F line.long 0x0 "RCC_MC_APB4LPENSETR,This register is used by the MCU in order to set the PERxLPEN bit." bitfld.long 0x0 21. "STGENROSTPEN,STGENROSTPEN" "0,1" bitfld.long 0x0 20. "STGENROLPEN,STGENROLPEN" "0,1" newline bitfld.long 0x0 16. "USBPHYLPEN,USBPHYLPEN" "0,1" bitfld.long 0x0 8. "DDRPERFMLPEN,DDRPERFMLPEN" "0,1" newline bitfld.long 0x0 4. "DSILPEN,DSILPEN" "0,1" bitfld.long 0x0 0. "LTDCLPEN,LTDCLPEN" "0,1" line.long 0x4 "RCC_MC_APB4LPENCLRR,This register is used by the MCU in order to clear the PERxLPEN bit" bitfld.long 0x4 21. "STGENROSTPEN,STGENROSTPEN" "0,1" bitfld.long 0x4 20. "STGENROLPEN,STGENROLPEN" "0,1" newline bitfld.long 0x4 16. "USBPHYLPEN,USBPHYLPEN" "0,1" bitfld.long 0x4 8. "DDRPERFMLPEN,DDRPERFMLPEN" "0,1" newline bitfld.long 0x4 4. "DSILPEN,DSILPEN" "0,1" bitfld.long 0x4 0. "LTDCLPEN,LTDCLPEN" "0,1" line.long 0x8 "RCC_MC_APB5LPENSETR,This register is used by the MCU in order to set the PERxLPEN bit." bitfld.long 0x8 21. "STGENSTPEN,STGENSTPEN" "0,1" bitfld.long 0x8 20. "STGENLPEN,STGENLPEN" "0,1" newline bitfld.long 0x8 16. "BSECLPEN,BSECLPEN" "0,1" bitfld.long 0x8 13. "TZPCLPEN,TZPCLPEN" "0,1" newline bitfld.long 0x8 12. "TZC2LPEN,TZC2LPEN" "0,1" bitfld.long 0x8 11. "TZC1LPEN,TZC1LPEN" "0,1" newline bitfld.long 0x8 8. "RTCAPBLPEN,RTCAPBLPEN" "0,1" bitfld.long 0x8 4. "USART1LPEN,USART1LPEN" "0,1" newline bitfld.long 0x8 3. "I2C6LPEN,I2C6LPEN" "0,1" bitfld.long 0x8 2. "I2C4LPEN,I2C4LPEN" "0,1" newline bitfld.long 0x8 0. "SPI6LPEN,SPI6LPEN" "0,1" line.long 0xC "RCC_MC_APB5LPENCLRR,This register is used by the MCU in order to clear the PERxLPEN bit" bitfld.long 0xC 21. "STGENSTPEN,STGENSTPEN" "0,1" bitfld.long 0xC 20. "STGENLPEN,STGENLPEN" "0,1" newline bitfld.long 0xC 16. "BSECLPEN,BSECLPEN" "0,1" bitfld.long 0xC 13. "TZPCLPEN,TZPCLPEN" "0,1" newline bitfld.long 0xC 12. "TZC2LPEN,TZC2LPEN" "0,1" bitfld.long 0xC 11. "TZC1LPEN,TZC1LPEN" "0,1" newline bitfld.long 0xC 8. "RTCAPBLPEN,RTCAPBLPEN" "0,1" bitfld.long 0xC 4. "USART1LPEN,USART1LPEN" "0,1" newline bitfld.long 0xC 3. "I2C6LPEN,I2C6LPEN" "0,1" bitfld.long 0xC 2. "I2C4LPEN,I2C4LPEN" "0,1" newline bitfld.long 0xC 0. "SPI6LPEN,SPI6LPEN" "0,1" line.long 0x10 "RCC_MC_AHB5LPENSETR,This register is used by the MCU in order to set the PERxLPEN bit. If TZEN = . this register can only be modified in secure mode." bitfld.long 0x10 8. "BKPSRAMLPEN,BKPSRAMLPEN" "0,1" bitfld.long 0x10 6. "RNG1LPEN,RNG1LPEN" "0,1" newline bitfld.long 0x10 5. "HASH1LPEN,HASH1LPEN" "0,1" bitfld.long 0x10 4. "CRYP1LPEN,CRYP1LPEN" "0,1" newline bitfld.long 0x10 0. "GPIOZLPEN,GPIOZLPEN" "0,1" line.long 0x14 "RCC_MC_AHB5LPENCLRR,This register is used by the MCU in order to clear the PERxLPEN bit If TZEN = . this register can only be modified in secure mode." bitfld.long 0x14 8. "BKPSRAMLPEN,BKPSRAMLPEN" "0,1" bitfld.long 0x14 6. "RNG1LPEN,RNG1LPEN" "0,1" newline bitfld.long 0x14 5. "HASH1LPEN,HASH1LPEN" "0,1" bitfld.long 0x14 4. "CRYP1LPEN,CRYP1LPEN" "0,1" newline bitfld.long 0x14 0. "GPIOZLPEN,GPIOZLPEN" "0,1" line.long 0x18 "RCC_MC_AHB6LPENSETR,This register is used by the MCU in order to set the PERxLPEN bit." bitfld.long 0x18 24. "USBHLPEN,USBHLPEN" "0,1" bitfld.long 0x18 20. "CRC1LPEN,CRC1LPEN" "0,1" newline bitfld.long 0x18 17. "SDMMC2LPEN,SDMMC2LPEN" "0,1" bitfld.long 0x18 16. "SDMMC1LPEN,SDMMC1LPEN" "0,1" newline bitfld.long 0x18 14. "QSPILPEN,QSPILPEN" "0,1" bitfld.long 0x18 12. "FMCLPEN,FMCLPEN" "0,1" newline bitfld.long 0x18 11. "ETHSTPEN,ETHSTPEN" "0,1" bitfld.long 0x18 10. "ETHMACLPEN,ETHMACLPEN" "0,1" newline bitfld.long 0x18 9. "ETHRXLPEN,ETHRXLPEN" "0,1" bitfld.long 0x18 8. "ETHTXLPEN,ETHTXLPEN" "0,1" newline bitfld.long 0x18 7. "ETHCKLPEN,ETHCKLPEN" "0,1" bitfld.long 0x18 5. "GPULPEN,GPULPEN" "0,1" newline bitfld.long 0x18 0. "MDMALPEN,MDMALPEN" "0,1" line.long 0x1C "RCC_MC_AHB6LPENCLRR,This register is used by the MCU in order to clear the PERxLPEN bit" bitfld.long 0x1C 24. "USBHLPEN,USBHLPEN" "0,1" bitfld.long 0x1C 20. "CRC1LPEN,CRC1LPEN" "0,1" newline bitfld.long 0x1C 17. "SDMMC2LPEN,SDMMC2LPEN" "0,1" bitfld.long 0x1C 16. "SDMMC1LPEN,SDMMC1LPEN" "0,1" newline bitfld.long 0x1C 14. "QSPILPEN,QSPILPEN" "0,1" bitfld.long 0x1C 12. "FMCLPEN,FMCLPEN" "0,1" newline bitfld.long 0x1C 11. "ETHSTPEN,ETHSTPEN" "0,1" bitfld.long 0x1C 10. "ETHMACLPEN,ETHMACLPEN" "0,1" newline bitfld.long 0x1C 9. "ETHRXLPEN,ETHRXLPEN" "0,1" bitfld.long 0x1C 8. "ETHTXLPEN,ETHTXLPEN" "0,1" newline bitfld.long 0x1C 7. "ETHCKLPEN,ETHCKLPEN" "0,1" bitfld.long 0x1C 5. "GPULPEN,GPULPEN" "0,1" newline bitfld.long 0x1C 0. "MDMALPEN,MDMALPEN" "0,1" group.long 0x400++0x23 line.long 0x0 "RCC_BR_RSTSCLRR,This register is used by the BOOTROM to check the reset source. Writing has no effect. reading will return the effective values of the corresponding bits. Writing a clears the corresponding bit to . In order to identify the reset.." bitfld.long 0x0 14. "MPUP1RSTF,MPUP1RSTF" "0,1" bitfld.long 0x0 13. "MPUP0RSTF,MPUP0RSTF" "0,1" newline bitfld.long 0x0 9. "IWDG2RSTF,IWDG2RSTF" "0,1" bitfld.long 0x0 8. "IWDG1RSTF,IWDG1RSTF" "0,1" newline bitfld.long 0x0 7. "MCSYSRSTF,MCSYSRSTF" "0,1" bitfld.long 0x0 6. "MPSYSRSTF,MPSYSRSTF" "0,1" newline bitfld.long 0x0 4. "VCORERSTF,VCORERSTF" "0,1" bitfld.long 0x0 3. "HCSSRSTF,HCSSRSTF" "0,1" newline bitfld.long 0x0 2. "PADRSTF,PADRSTF" "0,1" bitfld.long 0x0 1. "BORRSTF,BORRSTF" "0,1" newline bitfld.long 0x0 0. "PORRSTF,PORRSTF" "0,1" line.long 0x4 "RCC_MP_GRSTCSETR,This register is used by the MPU in order to generate either a MCU reset or a system reset or a reset of one of the two MPU processors. Writing has no effect. reading returns the effective values of the corresponding bits. Writing a.." bitfld.long 0x4 5. "MPUP1RST,MPUP1RST" "0,1" bitfld.long 0x4 4. "MPUP0RST,MPUP0RST" "0,1" newline bitfld.long 0x4 1. "MCURST,MCURST" "0,1" bitfld.long 0x4 0. "MPSYSRST,MPSYSRST" "0,1" line.long 0x8 "RCC_MP_RSTSCLRR,This register is used by the MPU to check the reset source. This register is updated by the BOOTROM code. after a power-on reset (por_rst). a system reset (nreset). or an exit from Standby or CStandby.Writing has no effect. reading will.." bitfld.long 0x8 15. "SPARE,SPARE" "0,1" bitfld.long 0x8 14. "MPUP1RSTF,MPUP1RSTF" "0,1" newline bitfld.long 0x8 13. "MPUP0RSTF,MPUP0RSTF" "0,1" bitfld.long 0x8 12. "CSTDBYRSTF,CSTDBYRSTF" "0,1" newline bitfld.long 0x8 11. "STDBYRSTF,STDBYRSTF" "0,1" bitfld.long 0x8 9. "IWDG2RSTF,IWDG2RSTF" "0,1" newline bitfld.long 0x8 8. "IWDG1RSTF,IWDG1RSTF" "0,1" bitfld.long 0x8 7. "MCSYSRSTF,MCSYSRSTF" "0,1" newline bitfld.long 0x8 6. "MPSYSRSTF,MPSYSRSTF" "0,1" bitfld.long 0x8 4. "VCORERSTF,VCORERSTF" "0,1" newline bitfld.long 0x8 3. "HCSSRSTF,HCSSRSTF" "0,1" bitfld.long 0x8 2. "PADRSTF,PADRSTF" "0,1" newline bitfld.long 0x8 1. "BORRSTF,BORRSTF" "0,1" bitfld.long 0x8 0. "PORRSTF,PORRSTF" "0,1" line.long 0xC "RCC_MP_IWDGFZSETR,This register is used by the BOOTROM in order to freeze the IWDGs clocks. After a system reset or Standby reset (nreset). or a CStandby reset (cstby_rst) the MPU is allowed to write it once.Writing has no effect. reading will return.." bitfld.long 0xC 1. "FZ_IWDG2,FZ_IWDG2" "0,1" bitfld.long 0xC 0. "FZ_IWDG1,FZ_IWDG1" "0,1" line.long 0x10 "RCC_MP_IWDGFZCLRR,This register is used by the BOOTROM in order to unfreeze the IWDGs clocks. Writing has no effect. reading will return the effective values of the corresponding bits. Writing a clears the corresponding bit to . If TZEN = . this.." bitfld.long 0x10 1. "FZ_IWDG2,FZ_IWDG2" "0,1" bitfld.long 0x10 0. "FZ_IWDG1,FZ_IWDG1" "0,1" line.long 0x14 "RCC_MP_CIER,This register shall be used by the MPU to control the interrupt source enable. Refer to Section10.5: RCC interrupts for more details. If TZEN = . this register can only be modified in secure mode." bitfld.long 0x14 20. "WKUPIE,WKUPIE" "0,1" bitfld.long 0x14 16. "LSECSSIE,LSECSSIE" "0,1" newline bitfld.long 0x14 11. "PLL4DYIE,PLL4DYIE" "0,1" bitfld.long 0x14 10. "PLL3DYIE,PLL3DYIE" "0,1" newline bitfld.long 0x14 9. "PLL2DYIE,PLL2DYIE" "0,1" bitfld.long 0x14 8. "PLL1DYIE,PLL1DYIE" "0,1" newline bitfld.long 0x14 4. "CSIRDYIE,CSIRDYIE" "0,1" bitfld.long 0x14 3. "HSERDYIE,HSERDYIE" "0,1" newline bitfld.long 0x14 2. "HSIRDYIE,HSIRDYIE" "0,1" bitfld.long 0x14 1. "LSERDYIE,LSERDYIE" "0,1" newline bitfld.long 0x14 0. "LSIRDYIE,LSIRDYIE" "0,1" line.long 0x18 "RCC_MP_CIFR,This register shall be used by the MPU in order to read and clear the interrupt flags.Writing has no effect. writing will clear the corresponding flag.Refer to Section10.5: RCC interrupts for more details. If TZEN = . this register can only.." bitfld.long 0x18 20. "WKUPF,WKUPF" "0,1" bitfld.long 0x18 16. "LSECSSF,LSECSSF" "0,1" newline bitfld.long 0x18 11. "PLL4DYF,PLL4DYF" "0,1" bitfld.long 0x18 10. "PLL3DYF,PLL3DYF" "0,1" newline bitfld.long 0x18 9. "PLL2DYF,PLL2DYF" "0,1" bitfld.long 0x18 8. "PLL1DYF,PLL1DYF" "0,1" newline bitfld.long 0x18 4. "CSIRDYF,CSIRDYF" "0,1" bitfld.long 0x18 3. "HSERDYF,HSERDYF" "0,1" newline bitfld.long 0x18 2. "HSIRDYF,HSIRDYF" "0,1" bitfld.long 0x18 1. "LSERDYF,LSERDYF" "0,1" newline bitfld.long 0x18 0. "LSIRDYF,LSIRDYF" "0,1" line.long 0x1C "RCC_PWRLPDLYCR,This register is used to program the delay between the moment where the system exits from one of the Stop modes. and the moment where it is allowed to enable the PLLs and provide a clock to bridges and processors. If TZEN = . this register.." bitfld.long 0x1C 24. "MCTMPSKP,MCTMPSKP" "0,1" hexmask.long.tbyte 0x1C 0.--21. 1. "PWRLP_DLY,PWRLP_DLY" line.long 0x20 "RCC_MP_RSTSSETR,This register is dedicated to the BOOTROM code in order to update the reset source. This register is updated by the BOOTROM code. after a power-on reset (por_rst). a system reset (nreset). or an exit from Standby or CStandby. The.." bitfld.long 0x20 15. "SPARE,SPARE" "0,1" bitfld.long 0x20 14. "MPUP1RSTF,MPUP1RSTF" "0,1" newline bitfld.long 0x20 13. "MPUP0RSTF,MPUP0RSTF" "0,1" bitfld.long 0x20 12. "CSTDBYRSTF,CSTDBYRSTF" "0,1" newline bitfld.long 0x20 11. "STDBYRSTF,STDBYRSTF" "0,1" bitfld.long 0x20 9. "IWDG2RSTF,IWDG2RSTF" "0,1" newline bitfld.long 0x20 8. "IWDG1RSTF,IWDG1RSTF" "0,1" bitfld.long 0x20 7. "MCSYSRSTF,MCSYSRSTF" "0,1" newline bitfld.long 0x20 6. "MPSYSRSTF,MPSYSRSTF" "0,1" bitfld.long 0x20 4. "VCORERSTF,VCORERSTF" "0,1" newline bitfld.long 0x20 3. "HCSSRSTF,HCSSRSTF" "0,1" bitfld.long 0x20 2. "PADRSTF,PADRSTF" "0,1" newline bitfld.long 0x20 1. "BORRSTF,BORRSTF" "0,1" bitfld.long 0x20 0. "PORRSTF,PORRSTF" "0,1" group.long 0x800++0x7 line.long 0x0 "RCC_MCO1CFGR,This register is used to select the clock generated on MCO1 output." bitfld.long 0x0 12. "MCO1ON,MCO1ON" "0,1" hexmask.long.byte 0x0 4.--7. 1. "MCO1DIV,MCO1DIV" newline bitfld.long 0x0 0.--2. "MCO1SEL,MCO1SEL" "0,1,2,3,4,5,6,7" line.long 0x4 "RCC_MCO2CFGR,This register is used to select the clock generated on MCO2 output." bitfld.long 0x4 12. "MCO2ON,MCO2ON" "0,1" hexmask.long.byte 0x4 4.--7. 1. "MCO2DIV,MCO2DIV" newline bitfld.long 0x4 0.--2. "MCO2SEL,MCO2SEL" "0,1,2,3,4,5,6,7" rgroup.long 0x808++0x3 line.long 0x0 "RCC_OCRDYR,This is a read-only access register. It contains the status flags of oscillators. Writing has no effect." bitfld.long 0x0 25. "CKREST,CKREST" "0,1" bitfld.long 0x0 24. "AXICKRDY,AXICKRDY" "0,1" newline bitfld.long 0x0 23. "MPUCKRDY,MPUCKRDY" "0,1" bitfld.long 0x0 8. "HSERDY,HSERDY" "0,1" newline bitfld.long 0x0 4. "CSIRDY,CSIRDY" "0,1" bitfld.long 0x0 2. "HSIDIVRDY,HSIDIVRDY" "0,1" newline bitfld.long 0x0 0. "HSIRDY,HSIRDY" "0,1" group.long 0x80C++0x3 line.long 0x0 "RCC_DBGCFGR,This is register contains the enable control of the debug and trace function. and the clock divider for the trace function." bitfld.long 0x0 12. "DBGRST,DBGRST" "0,1" bitfld.long 0x0 9. "TRACECKEN,TRACECKEN" "0,1" newline bitfld.long 0x0 8. "DBGCKEN,DBGCKEN" "0,1" bitfld.long 0x0 0.--2. "TRACEDIV,TRACEDIV" "0,1,2,3,4,5,6,7" group.long 0x820++0x1F line.long 0x0 "RCC_RCK3SELR,This register is used to select the reference clock for PLL3. If TZEN = MCKPROT = . this register can only be modified in secure mode." rbitfld.long 0x0 31. "PLL3SRCRDY,PLL3SRCRDY" "0,1" bitfld.long 0x0 0.--1. "PLL3SRC,PLL3SRC" "0,1,2,3" line.long 0x4 "RCC_RCK4SELR,This register is used to select the reference clock for PLL4." rbitfld.long 0x4 31. "PLL4SRCRDY,PLL4SRCRDY" "0,1" bitfld.long 0x4 0.--1. "PLL4SRC,PLL4SRC" "0,1,2,3" line.long 0x8 "RCC_TIMG1PRER,This register is used to control the prescaler value of timers located into APB1 domain. It concerns TIM2. TIM3. TIM4. TIM5. TIM6. TIM7. TIM12. TIM13 and TIM14. Refer to Section: Sub-system clock generation for additional information." rbitfld.long 0x8 31. "TIMG1PRERDY,TIMG1PRERDY" "0,1" bitfld.long 0x8 0. "TIMG1PRE,TIMG1PRE" "0,1" line.long 0xC "RCC_TIMG2PRER,This register is used to control the prescaler value of timers located into APB2 domain. It concerns TIM1. TIM8. TIM15. TIM16. and TIM17. Refer to Section: Sub-system clock generation for additional information." rbitfld.long 0xC 31. "TIMG2PRERDY,TIMG2PRERDY" "0,1" bitfld.long 0xC 0. "TIMG2PRE,TIMG2PRE" "0,1" line.long 0x10 "RCC_MCUDIVR,This register is used to control the MCU sub-system clock prescaler. Refer to Section: Sub-system clock generation for additional information. If TZEN = . this register can only be modified in secure mode." rbitfld.long 0x10 31. "MCUDIVRDY,MCUDIVRDY" "0,1" hexmask.long.byte 0x10 0.--3. 1. "MCUDIV,MCUDIV" line.long 0x14 "RCC_APB1DIVR,This register is used to control the APB1 clock prescaler. Refer to section Section1.4.6.3: Sub-System Clock Generation for additional information." rbitfld.long 0x14 31. "APB1DIVRDY,APB1DIVRDY" "0,1" bitfld.long 0x14 0.--2. "APB1DIV,APB1DIV" "0,1,2,3,4,5,6,7" line.long 0x18 "RCC_APB2DIVR,This register is used to control the APB2 clock prescaler. Refer to Section: Sub-system clock generation for additional information." rbitfld.long 0x18 31. "APB2DIVRDY,APB2DIVRDY" "0,1" bitfld.long 0x18 0.--2. "APB2DIV,APB2DIV" "0,1,2,3,4,5,6,7" line.long 0x1C "RCC_APB3DIVR,This register is used to control the APB3 clock prescaler. Refer to Section: Sub-system clock generation for additional information." rbitfld.long 0x1C 31. "APB3DIVRDY,APB3DIVRDY" "0,1" bitfld.long 0x1C 0.--2. "APB3DIV,APB3DIV" "0,1,2,3,4,5,6,7" group.long 0x880++0x27 line.long 0x0 "RCC_PLL3CR,This register is used to control the PLL3. If TZEN = MCKPROT = . this register can only be modified in secure mode." bitfld.long 0x0 6. "DIVREN,DIVREN" "0,1" bitfld.long 0x0 5. "DIVQEN,DIVQEN" "0,1" newline bitfld.long 0x0 4. "DIVPEN,DIVPEN" "0,1" bitfld.long 0x0 2. "SSCG_CTRL,SSCG_CTRL" "0,1" newline rbitfld.long 0x0 1. "PLL3RDY,PLL3RDY" "0,1" bitfld.long 0x0 0. "PLLON,PLLON" "0,1" line.long 0x4 "RCC_PLL3CFGR1,This register is used to configure the PLL3. If TZEN = MCKPROT = . this register can only be modified in secure mode." bitfld.long 0x4 24.--25. "IFRGE,IFRGE" "0,1,2,3" hexmask.long.byte 0x4 16.--21. 1. "DIVM3,DIVM3" newline hexmask.long.word 0x4 0.--8. 1. "DIVN,DIVN" line.long 0x8 "RCC_PLL3CFGR2,This register is used to configure the PLL3. If TZEN = MCKPROT = . this register can only be modified in secure mode." hexmask.long.byte 0x8 16.--22. 1. "DIVR,DIVR" hexmask.long.byte 0x8 8.--14. 1. "DIVQ,DIVQ" newline hexmask.long.byte 0x8 0.--6. 1. "DIVP,DIVP" line.long 0xC "RCC_PLL3FRACR,This register is used to fine-tune the frequency of the PLL3 VCO. If TZEN = MCKPROT = . this register can only be modified in secure mode." bitfld.long 0xC 16. "FRACLE,FRACLE" "0,1" hexmask.long.word 0xC 3.--15. 1. "FRACV,FRACV" line.long 0x10 "RCC_PLL3CSGR,This register is used to configure the PLL3.It is not recommended to change the content of this register when the PLL3 is enabled (PLLON = ). Refer to Section: Using the PLLs in spread spectrum mode for details. If TZEN = MCKPROT = . this.." hexmask.long.word 0x10 16.--30. 1. "INC_STEP,INC_STEP" bitfld.long 0x10 15. "SSCG_MODE,SSCG_MODE" "0,1" newline bitfld.long 0x10 14. "RPDFN_DIS,RPDFN_DIS" "0,1" bitfld.long 0x10 13. "TPDFN_DIS,TPDFN_DIS" "0,1" newline hexmask.long.word 0x10 0.--12. 1. "MOD_PER,MOD_PER" line.long 0x14 "RCC_PLL4CR,This register is used to control the PLL4." bitfld.long 0x14 6. "DIVREN,DIVREN" "0,1" bitfld.long 0x14 5. "DIVQEN,DIVQEN" "0,1" newline bitfld.long 0x14 4. "DIVPEN,DIVPEN" "0,1" bitfld.long 0x14 2. "SSCG_CTRL,SSCG_CTRL" "0,1" newline rbitfld.long 0x14 1. "PLL4RDY,PLL4RDY" "0,1" bitfld.long 0x14 0. "PLLON,PLLON" "0,1" line.long 0x18 "RCC_PLL4CFGR1,This register is used to configure the PLL4." bitfld.long 0x18 24.--25. "IFRGE,IFRGE" "0,1,2,3" hexmask.long.byte 0x18 16.--21. 1. "DIVM4,DIVM4" newline hexmask.long.word 0x18 0.--8. 1. "DIVN,DIVN" line.long 0x1C "RCC_PLL4CFGR2,This register is used to configure the PLL4." hexmask.long.byte 0x1C 16.--22. 1. "DIVR,DIVR" hexmask.long.byte 0x1C 8.--14. 1. "DIVQ,DIVQ" newline hexmask.long.byte 0x1C 0.--6. 1. "DIVP,DIVP" line.long 0x20 "RCC_PLL4FRACR,This register is used to fine-tune the frequency of the PLL4 VCO." bitfld.long 0x20 16. "FRACLE,FRACLE" "0,1" hexmask.long.word 0x20 3.--15. 1. "FRACV,FRACV" line.long 0x24 "RCC_PLL4CSGR,This register is used to configure the PLL4.It is not recommended to change the content of this register when the PLL4 is enabled (PLLON = ). Refer to Section: Using the PLLs in spread spectrum mode for details. If TZEN = MCKPROT = . this.." hexmask.long.word 0x24 16.--30. 1. "INC_STEP,INC_STEP" bitfld.long 0x24 15. "SSCG_MODE,SSCG_MODE" "0,1" newline bitfld.long 0x24 14. "RPDFN_DIS,RPDFN_DIS" "0,1" bitfld.long 0x24 13. "TPDFN_DIS,TPDFN_DIS" "0,1" newline hexmask.long.word 0x24 0.--12. 1. "MOD_PER,MOD_PER" group.long 0x8C0++0x47 line.long 0x0 "RCC_I2C12CKSELR,This register is used to control the selection of the kernel clock for the I2C1 and I2C2. Note that changing the clock source on-the-fly is allowed. and will not generate any timing violation. however the user has to ensure that both the.." bitfld.long 0x0 0.--2. "I2C12SRC,I2C12SRC" "0,1,2,3,4,5,6,7" line.long 0x4 "RCC_I2C35CKSELR,This register is used to control the selection of the kernel clock for the I2C3 and I2C5. Note that changing the clock source on-the-fly is allowed. and will not generate any timing violation. however the user has to ensure that both the.." bitfld.long 0x4 0.--2. "I2C35SRC,I2C35SRC" "0,1,2,3,4,5,6,7" line.long 0x8 "RCC_SAI1CKSELR,This register is used to control the selection of the kernel clock for the SAI1 and DFSDM audio clock. Note that changing the clock source on-the-fly is allowed. and will not generate any timing violation. however the user has to ensure.." bitfld.long 0x8 0.--2. "SAI1SRC,SAI1SRC" "0,1,2,3,4,5,6,7" line.long 0xC "RCC_SAI2CKSELR,This register is used to control the selection of the kernel clock for the SAI2. Note that changing the clock source on-the-fly is allowed. and will not generate any timing violation. however the user has to ensure that both the previous.." bitfld.long 0xC 0.--2. "SAI2SRC,SAI2SRC" "0,1,2,3,4,5,6,7" line.long 0x10 "RCC_SAI3CKSELR,This register is used to control the selection of the kernel clock for the SAI3. Note that changing the clock source on-the-fly is allowed. and will not generate any timing violation. however the user has to ensure that both the previous.." bitfld.long 0x10 0.--2. "SAI3SRC,SAI3SRC" "0,1,2,3,4,5,6,7" line.long 0x14 "RCC_SAI4CKSELR,This register is used to control the selection of the kernel clock for the SAI4. Note that changing the clock source on-the-fly is allowed. and will not generate any timing violation. however the user has to ensure that both the previous.." bitfld.long 0x14 0.--2. "SAI4SRC,SAI4SRC" "0,1,2,3,4,5,6,7" line.long 0x18 "RCC_SPI2S1CKSELR,This register is used to control the selection of the kernel clock for the SPI/I2S1. Note that changing the clock source on-the-fly is allowed. and will not generate any timing violation. however the user has to ensure that both the.." bitfld.long 0x18 0.--2. "SPI1SRC,SPI1SRC" "0,1,2,3,4,5,6,7" line.long 0x1C "RCC_SPI2S23CKSELR,This register is used to control the selection of the kernel clock for the SPI/I2S2.3. Note that changing the clock source on-the-fly is allowed. and will not generate any timing violation. however the user has to ensure that both the.." bitfld.long 0x1C 0.--2. "SPI23SRC,SPI23SRC" "0,1,2,3,4,5,6,7" line.long 0x20 "RCC_SPI45CKSELR,This register is used to control the selection of the kernel clock for the SPI4.5. Note that changing the clock source on-the-fly is allowed. and will not generate any timing violation. however the user has to ensure that both the.." bitfld.long 0x20 0.--2. "SPI45SRC,SPI45SRC" "0,1,2,3,4,5,6,7" line.long 0x24 "RCC_UART6CKSELR,This register is used to control the selection of the kernel clock for the USART6. Note that changing the clock source on-the-fly is allowed. and will not generate any timing violation. however the user has to ensure that both the.." bitfld.long 0x24 0.--2. "UART6SRC,UART6SRC" "0,1,2,3,4,5,6,7" line.long 0x28 "RCC_UART24CKSELR,This register is used to control the selection of the kernel clock for the USART2 and UART4. Note that changing the clock source on-the-fly is allowed. and will not generate any timing violation. however the user has to ensure that both.." bitfld.long 0x28 0.--2. "UART24SRC,UART24SRC" "0,1,2,3,4,5,6,7" line.long 0x2C "RCC_UART35CKSELR,This register is used to control the selection of the kernel clock for the USART3 and UART5. Note that changing the clock source on-the-fly is allowed. and will not generate any timing violation. however the user has to ensure that both.." bitfld.long 0x2C 0.--2. "UART35SRC,UART35SRC" "0,1,2,3,4,5,6,7" line.long 0x30 "RCC_UART78CKSELR,This register is used to control the selection of the kernel clock for the UART7 and UART8. Note that changing the clock source on-the-fly is allowed. and will not generate any timing violation. however the user has to ensure that both.." bitfld.long 0x30 0.--2. "UART78SRC,UART78SRC" "0,1,2,3,4,5,6,7" line.long 0x34 "RCC_SDMMC12CKSELR,This register is used to control the selection of the kernel clock for the SDMMC1 and SDMMC2. Note that changing the clock source on-the-fly is allowed. and will not generate any timing violation. however the user has to ensure that.." bitfld.long 0x34 0.--2. "SDMMC12SRC,SDMMC12SRC" "0,1,2,3,4,5,6,7" line.long 0x38 "RCC_SDMMC3CKSELR,This register is used to control the selection of the kernel clock for the SDMMC3. Note that changing the clock source on-the-fly is allowed. and will not generate any timing violation. however the user has to ensure that both the.." bitfld.long 0x38 0.--2. "SDMMC3SRC,SDMMC3SRC" "0,1,2,3,4,5,6,7" line.long 0x3C "RCC_ETHCKSELR,This register is used to control the selection of the kernel clock for the ETH block. Note that changing the clock source on-the-fly is allowed. and will not generate any timing violation. however the user has to ensure that both the.." hexmask.long.byte 0x3C 4.--7. 1. "ETHPTPDIV,ETHPTPDIV" bitfld.long 0x3C 0.--1. "ETHSRC,ETHSRC" "0,1,2,3" line.long 0x40 "RCC_QSPICKSELR,This register is used to control the selection of the kernel clock for the QUADSPI. Note that changing the clock source on-the-fly is allowed. and will not generate any timing violation. however the user has to ensure that both the.." bitfld.long 0x40 0.--1. "QSPISRC,QSPISRC" "0,1,2,3" line.long 0x44 "RCC_FMCCKSELR,This register is used to control the selection of the kernel clock for the FMC block. Note that changing the clock source on-the-fly is allowed. and will not generate any timing violation. however the user has to ensure that both the.." bitfld.long 0x44 0.--1. "FMCSRC,FMCSRC" "0,1,2,3" group.long 0x90C++0x3 line.long 0x0 "RCC_FDCANCKSELR,This register is used to control the selection of the kernel clock for the FDCAN block. Note that changing the clock source on-the-fly is allowed. and will not generate any timing violation. however the user has to ensure that both the.." bitfld.long 0x0 0.--1. "FDCANSRC,FDCANSRC" "0,1,2,3" group.long 0x914++0x23 line.long 0x0 "RCC_SPDIFCKSELR,This register is used to control the selection of the kernel clock for the SPDIFRX. Note that changing the clock source on-the-fly is allowed. and will not generate any timing violation. however the user has to ensure that both the.." bitfld.long 0x0 0.--1. "SPDIFSRC,SPDIFSRC" "0,1,2,3" line.long 0x4 "RCC_CECCKSELR,This register is used to control the selection of the kernel clock for the CEC-HDMI." bitfld.long 0x4 0.--1. "CECSRC,CECSRC" "0,1,2,3" line.long 0x8 "RCC_USBCKSELR,This register is used to control the selection of the kernel clock for the USBPHY PLL of the USB HOST and USB OTG" bitfld.long 0x8 4. "USBOSRC,USBOSRC" "0,1" bitfld.long 0x8 0.--1. "USBPHYSRC,USBPHYSRC" "0,1,2,3" line.long 0xC "RCC_RNG2CKSELR,This register is used to control the selection of the kernel clock for the RNG2." bitfld.long 0xC 0.--1. "RNG2SRC,RNG2SRC" "0,1,2,3" line.long 0x10 "RCC_DSICKSELR,This register is used to control the selection of the kernel clock for the DSI block." bitfld.long 0x10 0. "DSISRC,DSISRC" "0,1" line.long 0x14 "RCC_ADCCKSELR,This register is used to control the selection of the kernel clock for the ADC block." bitfld.long 0x14 0.--1. "ADCSRC,ADCSRC" "0,1,2,3" line.long 0x18 "RCC_LPTIM45CKSELR,This register is used to control the selection of the kernel clock for the LPTIM4 and LPTIM5 blocks." bitfld.long 0x18 0.--2. "LPTIM45SRC,LPTIM45SRC" "0,1,2,3,4,5,6,7" line.long 0x1C "RCC_LPTIM23CKSELR,This register is used to control the selection of the kernel clock for the LPTIM2 and LPTIM3 blocks." bitfld.long 0x1C 0.--2. "LPTIM23SRC,LPTIM23SRC" "0,1,2,3,4,5,6,7" line.long 0x20 "RCC_LPTIM1CKSELR,This register is used to control the selection of the kernel clock for the LPTIM1 block." bitfld.long 0x20 0.--2. "LPTIM1SRC,LPTIM1SRC" "0,1,2,3,4,5,6,7" group.long 0x980++0x2F line.long 0x0 "RCC_APB1RSTSETR,This register is used to activate the reset of the corresponding peripheral." bitfld.long 0x0 31. "MDIOSRST,MDIOSRST" "0,1" bitfld.long 0x0 29. "DAC12RST,DAC12RST" "0,1" newline bitfld.long 0x0 27. "CECRST,CECRST" "0,1" bitfld.long 0x0 26. "SPDIFRST,SPDIFRST" "0,1" newline bitfld.long 0x0 24. "I2C5RST,I2C5RST" "0,1" bitfld.long 0x0 23. "I2C3RST,I2C3RST" "0,1" newline bitfld.long 0x0 22. "I2C2RST,I2C2RST" "0,1" bitfld.long 0x0 21. "I2C1RST,I2C1RST" "0,1" newline bitfld.long 0x0 19. "UART8RST,UART8RST" "0,1" bitfld.long 0x0 18. "UART7RST,UART7RST" "0,1" newline bitfld.long 0x0 17. "UART5RST,UART5RST" "0,1" bitfld.long 0x0 16. "UART4RST,UART4RST" "0,1" newline bitfld.long 0x0 15. "USART3RST,USART3RST" "0,1" bitfld.long 0x0 14. "USART2RST,USART2RST" "0,1" newline bitfld.long 0x0 12. "SPI3RST,SPI3RST" "0,1" bitfld.long 0x0 11. "SPI2RST,SPI2RST" "0,1" newline bitfld.long 0x0 9. "LPTIM1RST,LPTIM1RST" "0,1" bitfld.long 0x0 8. "TIM14RST,TIM14RST" "0,1" newline bitfld.long 0x0 7. "TIM13RST,TIM13RST" "0,1" bitfld.long 0x0 6. "TIM12RST,TIM12RST" "0,1" newline bitfld.long 0x0 5. "TIM7RST,TIM7RST" "0,1" bitfld.long 0x0 4. "TIM6RST,TIM6RST" "0,1" newline bitfld.long 0x0 3. "TIM5RST,TIM5RST" "0,1" bitfld.long 0x0 2. "TIM4RST,TIM4RST" "0,1" newline bitfld.long 0x0 1. "TIM3RST,TIM3RST" "0,1" bitfld.long 0x0 0. "TIM2RST,TIM2RST" "0,1" line.long 0x4 "RCC_APB1RSTCLRR,This register is used to release the reset of the corresponding peripheral." bitfld.long 0x4 31. "MDIOSRST,MDIOSRST" "0,1" bitfld.long 0x4 29. "DAC12RST,DAC12RST" "0,1" newline bitfld.long 0x4 27. "CECRST,CECRST" "0,1" bitfld.long 0x4 26. "SPDIFRST,SPDIFRST" "0,1" newline bitfld.long 0x4 24. "I2C5RST,I2C5RST" "0,1" bitfld.long 0x4 23. "I2C3RST,I2C3RST" "0,1" newline bitfld.long 0x4 22. "I2C2RST,I2C2RST" "0,1" bitfld.long 0x4 21. "I2C1RST,I2C1RST" "0,1" newline bitfld.long 0x4 19. "UART8RST,UART8RST" "0,1" bitfld.long 0x4 18. "UART7RST,UART7RST" "0,1" newline bitfld.long 0x4 17. "UART5RST,UART5RST" "0,1" bitfld.long 0x4 16. "UART4RST,UART4RST" "0,1" newline bitfld.long 0x4 15. "USART3RST,USART3RST" "0,1" bitfld.long 0x4 14. "USART2RST,USART2RST" "0,1" newline bitfld.long 0x4 12. "SPI3RST,SPI3RST" "0,1" bitfld.long 0x4 11. "SPI2RST,SPI2RST" "0,1" newline bitfld.long 0x4 9. "LPTIM1RST,LPTIM1RST" "0,1" bitfld.long 0x4 8. "TIM14RST,TIM14RST" "0,1" newline bitfld.long 0x4 7. "TIM13RST,TIM13RST" "0,1" bitfld.long 0x4 6. "TIM12RST,TIM12RST" "0,1" newline bitfld.long 0x4 5. "TIM7RST,TIM7RST" "0,1" bitfld.long 0x4 4. "TIM6RST,TIM6RST" "0,1" newline bitfld.long 0x4 3. "TIM5RST,TIM5RST" "0,1" bitfld.long 0x4 2. "TIM4RST,TIM4RST" "0,1" newline bitfld.long 0x4 1. "TIM3RST,TIM3RST" "0,1" bitfld.long 0x4 0. "TIM2RST,TIM2RST" "0,1" line.long 0x8 "RCC_APB2RSTSETR,This register is used to activate the reset of the corresponding peripheral." bitfld.long 0x8 24. "FDCANRST,FDCANRST" "0,1" bitfld.long 0x8 20. "DFSDMRST,DFSDMRST" "0,1" newline bitfld.long 0x8 18. "SAI3RST,SAI3RST" "0,1" bitfld.long 0x8 17. "SAI2RST,SAI2RST" "0,1" newline bitfld.long 0x8 16. "SAI1RST,SAI1RST" "0,1" bitfld.long 0x8 13. "USART6RST,USART6RST" "0,1" newline bitfld.long 0x8 10. "SPI5RST,SPI5RST" "0,1" bitfld.long 0x8 9. "SPI4RST,SPI4RST" "0,1" newline bitfld.long 0x8 8. "SPI1RST,SPI1RST" "0,1" bitfld.long 0x8 4. "TIM17RST,TIM17RST" "0,1" newline bitfld.long 0x8 3. "TIM16RST,TIM16RST" "0,1" bitfld.long 0x8 2. "TIM15RST,TIM15RST" "0,1" newline bitfld.long 0x8 1. "TIM8RST,TIM8RST" "0,1" bitfld.long 0x8 0. "TIM1RST,TIM1RST" "0,1" line.long 0xC "RCC_APB2RSTCLRR,This register is used to release the reset of the corresponding peripheral." bitfld.long 0xC 24. "FDCANRST,FDCANRST" "0,1" bitfld.long 0xC 20. "DFSDMRST,DFSDMRST" "0,1" newline bitfld.long 0xC 18. "SAI3RST,SAI3RST" "0,1" bitfld.long 0xC 17. "SAI2RST,SAI2RST" "0,1" newline bitfld.long 0xC 16. "SAI1RST,SAI1RST" "0,1" bitfld.long 0xC 13. "USART6RST,USART6RST" "0,1" newline bitfld.long 0xC 10. "SPI5RST,SPI5RST" "0,1" bitfld.long 0xC 9. "SPI4RST,SPI4RST" "0,1" newline bitfld.long 0xC 8. "SPI1RST,SPI1RST" "0,1" bitfld.long 0xC 4. "TIM17RST,TIM17RST" "0,1" newline bitfld.long 0xC 3. "TIM16RST,TIM16RST" "0,1" bitfld.long 0xC 2. "TIM15RST,TIM15RST" "0,1" newline bitfld.long 0xC 1. "TIM8RST,TIM8RST" "0,1" bitfld.long 0xC 0. "TIM1RST,TIM1RST" "0,1" line.long 0x10 "RCC_APB3RSTSETR,This register is used to activate the reset of the corresponding peripheral." bitfld.long 0x10 16. "DTSRST,DTSRST" "0,1" bitfld.long 0x10 13. "VREFRST,VREFRST" "0,1" newline bitfld.long 0x10 11. "SYSCFGRST,SYSCFGRST" "0,1" bitfld.long 0x10 8. "SAI4RST,SAI4RST" "0,1" newline bitfld.long 0x10 3. "LPTIM5RST,LPTIM5RST" "0,1" bitfld.long 0x10 2. "LPTIM4RST,LPTIM4RST" "0,1" newline bitfld.long 0x10 1. "LPTIM3RST,LPTIM3RST" "0,1" bitfld.long 0x10 0. "LPTIM2RST,LPTIM2RST" "0,1" line.long 0x14 "RCC_APB3RSTCLRR,This register is used to release the reset of the corresponding peripheral." bitfld.long 0x14 16. "DTSRST,DTSRST" "0,1" bitfld.long 0x14 13. "VREFRST,VREFRST" "0,1" newline bitfld.long 0x14 11. "SYSCFGRST,SYSCFGRST" "0,1" bitfld.long 0x14 8. "SAI4RST,SAI4RST" "0,1" newline bitfld.long 0x14 3. "LPTIM5RST,LPTIM5RST" "0,1" bitfld.long 0x14 2. "LPTIM4RST,LPTIM4RST" "0,1" newline bitfld.long 0x14 1. "LPTIM3RST,LPTIM3RST" "0,1" bitfld.long 0x14 0. "LPTIM2RST,LPTIM2RST" "0,1" line.long 0x18 "RCC_AHB2RSTSETR,This register is used to activate the reset of the corresponding peripheral." bitfld.long 0x18 16. "SDMMC3RST,SDMMC3RST" "0,1" bitfld.long 0x18 8. "USBORST,USBORST" "0,1" newline bitfld.long 0x18 5. "ADC12RST,ADC12RST" "0,1" bitfld.long 0x18 2. "DMAMUXRST,DMAMUXRST" "0,1" newline bitfld.long 0x18 1. "DMA2RST,DMA2RST" "0,1" bitfld.long 0x18 0. "DMA1RST,DMA1RST" "0,1" line.long 0x1C "RCC_AHB2RSTCLRR,This register is used to release the reset of the corresponding peripheral." bitfld.long 0x1C 16. "SDMMC3RST,SDMMC3RST" "0,1" bitfld.long 0x1C 8. "USBORST,USBORST" "0,1" newline bitfld.long 0x1C 5. "ADC12RST,ADC12RST" "0,1" bitfld.long 0x1C 2. "DMAMUXRST,DMAMUXRST" "0,1" newline bitfld.long 0x1C 1. "DMA2RST,DMA2RST" "0,1" bitfld.long 0x1C 0. "DMA1RST,DMA1RST" "0,1" line.long 0x20 "RCC_AHB3RSTSETR,This register is used to activate the reset of the corresponding peripheral." bitfld.long 0x20 12. "IPCCRST,IPCCRST" "0,1" bitfld.long 0x20 11. "HSEMRST,HSEMRST" "0,1" newline bitfld.long 0x20 7. "CRC2RST,CRC2RST" "0,1" bitfld.long 0x20 6. "RNG2RST,RNG2RST" "0,1" newline bitfld.long 0x20 5. "HASH2RST,HASH2RST" "0,1" bitfld.long 0x20 4. "CRYP2RST,CRYP2RST" "0,1" newline bitfld.long 0x20 0. "DCMIRST,DCMIRST" "0,1" line.long 0x24 "RCC_AHB3RSTCLRR,This register is used to release the reset of the corresponding peripheral." bitfld.long 0x24 12. "IPCCRST,IPCCRST" "0,1" bitfld.long 0x24 11. "HSEMRST,HSEMRST" "0,1" newline bitfld.long 0x24 7. "CRC2RST,CRC2RST" "0,1" bitfld.long 0x24 6. "RNG2RST,RNG2RST" "0,1" newline bitfld.long 0x24 5. "HASH2RST,HASH2RST" "0,1" bitfld.long 0x24 4. "CRYP2RST,CRYP2RST" "0,1" newline bitfld.long 0x24 0. "DCMIRST,DCMIRST" "0,1" line.long 0x28 "RCC_AHB4RSTSETR,This register is used to activate the reset of the corresponding peripheral" bitfld.long 0x28 10. "GPIOKRST,GPIOKRST" "0,1" bitfld.long 0x28 9. "GPIOJRST,GPIOJRST" "0,1" newline bitfld.long 0x28 8. "GPIOIRST,GPIOIRST" "0,1" bitfld.long 0x28 7. "GPIOHRST,GPIOHRST" "0,1" newline bitfld.long 0x28 6. "GPIOGRST,GPIOGRST" "0,1" bitfld.long 0x28 5. "GPIOFRST,GPIOFRST" "0,1" newline bitfld.long 0x28 4. "GPIOERST,GPIOERST" "0,1" bitfld.long 0x28 3. "GPIODRST,GPIODRST" "0,1" newline bitfld.long 0x28 2. "GPIOCRST,GPIOCRST" "0,1" bitfld.long 0x28 1. "GPIOBRST,GPIOBRST" "0,1" newline bitfld.long 0x28 0. "GPIOARST,GPIOARST" "0,1" line.long 0x2C "RCC_AHB4RSTCLRR,This register is used to release the reset of the corresponding peripheral." bitfld.long 0x2C 10. "GPIOKRST,GPIOKRST" "0,1" bitfld.long 0x2C 9. "GPIOJRST,GPIOJRST" "0,1" newline bitfld.long 0x2C 8. "GPIOIRST,GPIOIRST" "0,1" bitfld.long 0x2C 7. "GPIOHRST,GPIOHRST" "0,1" newline bitfld.long 0x2C 6. "GPIOGRST,GPIOGRST" "0,1" bitfld.long 0x2C 5. "GPIOFRST,GPIOFRST" "0,1" newline bitfld.long 0x2C 4. "GPIOERST,GPIOERST" "0,1" bitfld.long 0x2C 3. "GPIODRST,GPIODRST" "0,1" newline bitfld.long 0x2C 2. "GPIOCRST,GPIOCRST" "0,1" bitfld.long 0x2C 1. "GPIOBRST,GPIOBRST" "0,1" newline bitfld.long 0x2C 0. "GPIOARST,GPIOARST" "0,1" group.long 0xA00++0x2F line.long 0x0 "RCC_MP_APB1ENSETR,This register is used to set the peripheral clock enable bit" bitfld.long 0x0 31. "MDIOSEN,MDIOSEN" "0,1" bitfld.long 0x0 29. "DAC12EN,DAC12EN" "0,1" newline bitfld.long 0x0 27. "CECEN,CECEN" "0,1" bitfld.long 0x0 26. "SPDIFEN,SPDIFEN" "0,1" newline bitfld.long 0x0 24. "I2C5EN,I2C5EN" "0,1" bitfld.long 0x0 23. "I2C3EN,I2C3EN" "0,1" newline bitfld.long 0x0 22. "I2C2EN,I2C2EN" "0,1" bitfld.long 0x0 21. "I2C1EN,I2C1EN" "0,1" newline bitfld.long 0x0 19. "UART8EN,UART8EN" "0,1" bitfld.long 0x0 18. "UART7EN,UART7EN" "0,1" newline bitfld.long 0x0 17. "UART5EN,UART5EN" "0,1" bitfld.long 0x0 16. "UART4EN,UART4EN" "0,1" newline bitfld.long 0x0 15. "USART3EN,USART3EN" "0,1" bitfld.long 0x0 14. "USART2EN,USART2EN" "0,1" newline bitfld.long 0x0 12. "SPI3EN,SPI3EN" "0,1" bitfld.long 0x0 11. "SPI2EN,SPI2EN" "0,1" newline bitfld.long 0x0 9. "LPTIM1EN,LPTIM1EN" "0,1" bitfld.long 0x0 8. "TIM14EN,TIM14EN" "0,1" newline bitfld.long 0x0 7. "TIM13EN,TIM13EN" "0,1" bitfld.long 0x0 6. "TIM12EN,TIM12EN" "0,1" newline bitfld.long 0x0 5. "TIM7EN,TIM7EN" "0,1" bitfld.long 0x0 4. "TIM6EN,TIM6EN" "0,1" newline bitfld.long 0x0 3. "TIM5EN,TIM5EN" "0,1" bitfld.long 0x0 2. "TIM4EN,TIM4EN" "0,1" newline bitfld.long 0x0 1. "TIM3EN,TIM3EN" "0,1" bitfld.long 0x0 0. "TIM2EN,TIM2EN" "0,1" line.long 0x4 "RCC_MP_APB1ENCLRR,This register is used to clear the peripheral clock enable bit" bitfld.long 0x4 31. "MDIOSEN,MDIOSEN" "0,1" bitfld.long 0x4 29. "DAC12EN,DAC12EN" "0,1" newline bitfld.long 0x4 27. "CECEN,CECEN" "0,1" bitfld.long 0x4 26. "SPDIFEN,SPDIFEN" "0,1" newline bitfld.long 0x4 24. "I2C5EN,I2C5EN" "0,1" bitfld.long 0x4 23. "I2C3EN,I2C3EN" "0,1" newline bitfld.long 0x4 22. "I2C2EN,I2C2EN" "0,1" bitfld.long 0x4 21. "I2C1EN,I2C1EN" "0,1" newline bitfld.long 0x4 19. "UART8EN,UART8EN" "0,1" bitfld.long 0x4 18. "UART7EN,UART7EN" "0,1" newline bitfld.long 0x4 17. "UART5EN,UART5EN" "0,1" bitfld.long 0x4 16. "UART4EN,UART4EN" "0,1" newline bitfld.long 0x4 15. "USART3EN,USART3EN" "0,1" bitfld.long 0x4 14. "USART2EN,USART2EN" "0,1" newline bitfld.long 0x4 12. "SPI3EN,SPI3EN" "0,1" bitfld.long 0x4 11. "SPI2EN,SPI2EN" "0,1" newline bitfld.long 0x4 9. "LPTIM1EN,LPTIM1EN" "0,1" bitfld.long 0x4 8. "TIM14EN,TIM14EN" "0,1" newline bitfld.long 0x4 7. "TIM13EN,TIM13EN" "0,1" bitfld.long 0x4 6. "TIM12EN,TIM12EN" "0,1" newline bitfld.long 0x4 5. "TIM7EN,TIM7EN" "0,1" bitfld.long 0x4 4. "TIM6EN,TIM6EN" "0,1" newline bitfld.long 0x4 3. "TIM5EN,TIM5EN" "0,1" bitfld.long 0x4 2. "TIM4EN,TIM4EN" "0,1" newline bitfld.long 0x4 1. "TIM3EN,TIM3EN" "0,1" bitfld.long 0x4 0. "TIM2EN,TIM2EN" "0,1" line.long 0x8 "RCC_MP_APB2ENSETR,This register is used to set the peripheral clock enable bit" bitfld.long 0x8 24. "FDCANEN,FDCANEN" "0,1" bitfld.long 0x8 21. "ADFSDMEN,ADFSDMEN" "0,1" newline bitfld.long 0x8 20. "DFSDMEN,DFSDMEN" "0,1" bitfld.long 0x8 18. "SAI3EN,SAI3EN" "0,1" newline bitfld.long 0x8 17. "SAI2EN,SAI2EN" "0,1" bitfld.long 0x8 16. "SAI1EN,SAI1EN" "0,1" newline bitfld.long 0x8 13. "USART6EN,USART6EN" "0,1" bitfld.long 0x8 10. "SPI5EN,SPI5EN" "0,1" newline bitfld.long 0x8 9. "SPI4EN,SPI4EN" "0,1" bitfld.long 0x8 8. "SPI1EN,SPI1EN" "0,1" newline bitfld.long 0x8 4. "TIM17EN,TIM17EN" "0,1" bitfld.long 0x8 3. "TIM16EN,TIM16EN" "0,1" newline bitfld.long 0x8 2. "TIM15EN,TIM15EN" "0,1" bitfld.long 0x8 1. "TIM8EN,TIM8EN" "0,1" newline bitfld.long 0x8 0. "TIM1EN,TIM1EN" "0,1" line.long 0xC "RCC_MP_APB2ENCLRR,This register is used to clear the peripheral clock enable bit of the corresponding peripheral." bitfld.long 0xC 24. "FDCANEN,FDCANEN" "0,1" bitfld.long 0xC 21. "ADFSDMEN,ADFSDMEN" "0,1" newline bitfld.long 0xC 20. "DFSDMEN,DFSDMEN" "0,1" bitfld.long 0xC 18. "SAI3EN,SAI3EN" "0,1" newline bitfld.long 0xC 17. "SAI2EN,SAI2EN" "0,1" bitfld.long 0xC 16. "SAI1EN,SAI1EN" "0,1" newline bitfld.long 0xC 13. "USART6EN,USART6EN" "0,1" bitfld.long 0xC 10. "SPI5EN,SPI5EN" "0,1" newline bitfld.long 0xC 9. "SPI4EN,SPI4EN" "0,1" bitfld.long 0xC 8. "SPI1EN,SPI1EN" "0,1" newline bitfld.long 0xC 4. "TIM17EN,TIM17EN" "0,1" bitfld.long 0xC 3. "TIM16EN,TIM16EN" "0,1" newline bitfld.long 0xC 2. "TIM15EN,TIM15EN" "0,1" bitfld.long 0xC 1. "TIM8EN,TIM8EN" "0,1" newline bitfld.long 0xC 0. "TIM1EN,TIM1EN" "0,1" line.long 0x10 "RCC_MP_APB3ENSETR,This register is used to set the peripheral clock enable bit" bitfld.long 0x10 20. "HDPEN,HDPEN" "0,1" bitfld.long 0x10 16. "DTSEN,DTSEN" "0,1" newline bitfld.long 0x10 13. "VREFEN,VREFEN" "0,1" bitfld.long 0x10 11. "SYSCFGEN,SYSCFGEN" "0,1" newline bitfld.long 0x10 8. "SAI4EN,SAI4EN" "0,1" bitfld.long 0x10 3. "LPTIM5EN,LPTIM5EN" "0,1" newline bitfld.long 0x10 2. "LPTIM4EN,LPTIM4EN" "0,1" bitfld.long 0x10 1. "LPTIM3EN,LPTIM3EN" "0,1" newline bitfld.long 0x10 0. "LPTIM2EN,LPTIM2EN" "0,1" line.long 0x14 "RCC_MP_APB3ENCLRR,This register is used to clear the peripheral clock enable bit of the corresponding peripheral." bitfld.long 0x14 20. "HDPEN,HDPEN" "0,1" bitfld.long 0x14 16. "DTSEN,DTSEN" "0,1" newline bitfld.long 0x14 13. "VREFEN,VREFEN" "0,1" bitfld.long 0x14 11. "SYSCFGEN,SYSCFGEN" "0,1" newline bitfld.long 0x14 8. "SAI4EN,SAI4EN" "0,1" bitfld.long 0x14 3. "LPTIM5EN,LPTIM5EN" "0,1" newline bitfld.long 0x14 2. "LPTIM4EN,LPTIM4EN" "0,1" bitfld.long 0x14 1. "LPTIM3EN,LPTIM3EN" "0,1" newline bitfld.long 0x14 0. "LPTIM2EN,LPTIM2EN" "0,1" line.long 0x18 "RCC_MP_AHB2ENSETR,This register is used to set the peripheral clock enable bit of the corresponding peripheral" bitfld.long 0x18 16. "SDMMC3EN,SDMMC3EN" "0,1" bitfld.long 0x18 8. "USBOEN,USBOEN" "0,1" newline bitfld.long 0x18 5. "ADC12EN,ADC12EN" "0,1" bitfld.long 0x18 2. "DMAMUXEN,DMAMUXEN" "0,1" newline bitfld.long 0x18 1. "DMA2EN,DMA2EN" "0,1" bitfld.long 0x18 0. "DMA1EN,DMA1EN" "0,1" line.long 0x1C "RCC_MP_AHB2ENCLRR,This register is used to clear the peripheral clock enable bit of the corresponding peripheral." bitfld.long 0x1C 16. "SDMMC3EN,SDMMC3EN" "0,1" bitfld.long 0x1C 8. "USBOEN,USBOEN" "0,1" newline bitfld.long 0x1C 5. "ADC12EN,ADC12EN" "0,1" bitfld.long 0x1C 2. "DMAMUXEN,DMAMUXEN" "0,1" newline bitfld.long 0x1C 1. "DMA2EN,DMA2EN" "0,1" bitfld.long 0x1C 0. "DMA1EN,DMA1EN" "0,1" line.long 0x20 "RCC_MP_AHB3ENSETR,This register is used to set the peripheral clock enable bit of the corresponding peripheral" bitfld.long 0x20 12. "IPCCEN,IPCCEN" "0,1" bitfld.long 0x20 11. "HSEMEN,HSEMEN" "0,1" newline bitfld.long 0x20 7. "CRC2EN,CRC2EN" "0,1" bitfld.long 0x20 6. "RNG2EN,RNG2EN" "0,1" newline bitfld.long 0x20 5. "HASH2EN,HASH2EN" "0,1" bitfld.long 0x20 4. "CRYP2EN,CRYP2EN" "0,1" newline bitfld.long 0x20 0. "DCMIEN,DCMIEN" "0,1" line.long 0x24 "RCC_MP_AHB3ENCLRR,This register is used to clear the peripheral clock enable bit of the corresponding peripheral." bitfld.long 0x24 12. "IPCCEN,IPCCEN" "0,1" bitfld.long 0x24 11. "HSEMEN,HSEMEN" "0,1" newline bitfld.long 0x24 7. "CRC2EN,CRC2EN" "0,1" bitfld.long 0x24 6. "RNG2EN,RNG2EN" "0,1" newline bitfld.long 0x24 5. "HASH2EN,HASH2EN" "0,1" bitfld.long 0x24 4. "CRYP2EN,CRYP2EN" "0,1" newline bitfld.long 0x24 0. "DCMIEN,DCMIEN" "0,1" line.long 0x28 "RCC_MP_AHB4ENSETR,This register is used to set the peripheral clock enable bit of the corresponding peripheral to . It shall be used to allocate a peripheral to the MPU." bitfld.long 0x28 10. "GPIOKEN,GPIOKEN" "0,1" bitfld.long 0x28 9. "GPIOJEN,GPIOJEN" "0,1" newline bitfld.long 0x28 8. "GPIOIEN,GPIOIEN" "0,1" bitfld.long 0x28 7. "GPIOHEN,GPIOHEN" "0,1" newline bitfld.long 0x28 6. "GPIOGEN,GPIOGEN" "0,1" bitfld.long 0x28 5. "GPIOFEN,GPIOFEN" "0,1" newline bitfld.long 0x28 4. "GPIOEEN,GPIOEEN" "0,1" bitfld.long 0x28 3. "GPIODEN,GPIODEN" "0,1" newline bitfld.long 0x28 2. "GPIOCEN,GPIOCEN" "0,1" bitfld.long 0x28 1. "GPIOBEN,GPIOBEN" "0,1" newline bitfld.long 0x28 0. "GPIOAEN,GPIOAEN" "0,1" line.long 0x2C "RCC_MP_AHB4ENCLRR,This register is used to clear the peripheral clock enable bit" bitfld.long 0x2C 10. "GPIOKEN,GPIOKEN" "0,1" bitfld.long 0x2C 9. "GPIOJEN,GPIOJEN" "0,1" newline bitfld.long 0x2C 8. "GPIOIEN,GPIOIEN" "0,1" bitfld.long 0x2C 7. "GPIOHEN,GPIOHEN" "0,1" newline bitfld.long 0x2C 6. "GPIOGEN,GPIOGEN" "0,1" bitfld.long 0x2C 5. "GPIOFEN,GPIOFEN" "0,1" newline bitfld.long 0x2C 4. "GPIOEEN,GPIOEEN" "0,1" bitfld.long 0x2C 3. "GPIODEN,GPIODEN" "0,1" newline bitfld.long 0x2C 2. "GPIOCEN,GPIOCEN" "0,1" bitfld.long 0x2C 1. "GPIOBEN,GPIOBEN" "0,1" newline bitfld.long 0x2C 0. "GPIOAEN,GPIOAEN" "0,1" group.long 0xA38++0x7 line.long 0x0 "RCC_MP_MLAHBENSETR,This register is used to set the peripheral clock enable bit" bitfld.long 0x0 4. "RETRAMEN,RETRAMEN" "0,1" line.long 0x4 "RCC_MP_MLAHBENCLRR,This register is used to clear the peripheral clock enable bit." bitfld.long 0x4 4. "RETRAMEN,RETRAMEN" "0,1" group.long 0xA80++0x3F line.long 0x0 "RCC_MC_APB1ENSETR,This register is used to set the peripheral clock enable bit of the corresponding peripheral to . It shall be used to allocate a peripheral to the MCU. Writing has no effect. reading will return . Writing a sets the corresponding bit.." bitfld.long 0x0 31. "MDIOSEN,MDIOSEN" "0,1" bitfld.long 0x0 29. "DAC12EN,DAC12EN" "0,1" newline bitfld.long 0x0 28. "WWDG1EN,WWDG1EN" "0,1" bitfld.long 0x0 27. "CECEN,CECEN" "0,1" newline bitfld.long 0x0 26. "SPDIFEN,SPDIFEN" "0,1" bitfld.long 0x0 24. "I2C5EN,I2C5EN" "0,1" newline bitfld.long 0x0 23. "I2C3EN,I2C3EN" "0,1" bitfld.long 0x0 22. "I2C2EN,I2C2EN" "0,1" newline bitfld.long 0x0 21. "I2C1EN,I2C1EN" "0,1" bitfld.long 0x0 19. "UART8EN,UART8EN" "0,1" newline bitfld.long 0x0 18. "UART7EN,UART7EN" "0,1" bitfld.long 0x0 17. "UART5EN,UART5EN" "0,1" newline bitfld.long 0x0 16. "UART4EN,UART4EN" "0,1" bitfld.long 0x0 15. "USART3EN,USART3EN" "0,1" newline bitfld.long 0x0 14. "USART2EN,USART2EN" "0,1" bitfld.long 0x0 12. "SPI3EN,SPI3EN" "0,1" newline bitfld.long 0x0 11. "SPI2EN,SPI2EN" "0,1" bitfld.long 0x0 9. "LPTIM1EN,LPTIM1EN" "0,1" newline bitfld.long 0x0 8. "TIM14EN,TIM14EN" "0,1" bitfld.long 0x0 7. "TIM13EN,TIM13EN" "0,1" newline bitfld.long 0x0 6. "TIM12EN,TIM12EN" "0,1" bitfld.long 0x0 5. "TIM7EN,TIM7EN" "0,1" newline bitfld.long 0x0 4. "TIM6EN,TIM6EN" "0,1" bitfld.long 0x0 3. "TIM5EN,TIM5EN" "0,1" newline bitfld.long 0x0 2. "TIM4EN,TIM4EN" "0,1" bitfld.long 0x0 1. "TIM3EN,TIM3EN" "0,1" newline bitfld.long 0x0 0. "TIM2EN,TIM2EN" "0,1" line.long 0x4 "RCC_MC_APB1ENCLRR,This register is used to clear the peripheral clock enable bit of the corresponding peripheral." bitfld.long 0x4 31. "MDIOSEN,MDIOSEN" "0,1" bitfld.long 0x4 29. "DAC12EN,DAC12EN" "0,1" newline bitfld.long 0x4 27. "CECEN,CECEN" "0,1" bitfld.long 0x4 26. "SPDIFEN,SPDIFEN" "0,1" newline bitfld.long 0x4 24. "I2C5EN,I2C5EN" "0,1" bitfld.long 0x4 23. "I2C3EN,I2C3EN" "0,1" newline bitfld.long 0x4 22. "I2C2EN,I2C2EN" "0,1" bitfld.long 0x4 21. "I2C1EN,I2C1EN" "0,1" newline bitfld.long 0x4 19. "UART8EN,UART8EN" "0,1" bitfld.long 0x4 18. "UART7EN,UART7EN" "0,1" newline bitfld.long 0x4 17. "UART5EN,UART5EN" "0,1" bitfld.long 0x4 16. "UART4EN,UART4EN" "0,1" newline bitfld.long 0x4 15. "USART3EN,USART3EN" "0,1" bitfld.long 0x4 14. "USART2EN,USART2EN" "0,1" newline bitfld.long 0x4 12. "SPI3EN,SPI3EN" "0,1" bitfld.long 0x4 11. "SPI2EN,SPI2EN" "0,1" newline bitfld.long 0x4 9. "LPTIM1EN,LPTIM1EN" "0,1" bitfld.long 0x4 8. "TIM14EN,TIM14EN" "0,1" newline bitfld.long 0x4 7. "TIM13EN,TIM13EN" "0,1" bitfld.long 0x4 6. "TIM12EN,TIM12EN" "0,1" newline bitfld.long 0x4 5. "TIM7EN,TIM7EN" "0,1" bitfld.long 0x4 4. "TIM6EN,TIM6EN" "0,1" newline bitfld.long 0x4 3. "TIM5EN,TIM5EN" "0,1" bitfld.long 0x4 2. "TIM4EN,TIM4EN" "0,1" newline bitfld.long 0x4 1. "TIM3EN,TIM3EN" "0,1" bitfld.long 0x4 0. "TIM2EN,TIM2EN" "0,1" line.long 0x8 "RCC_MC_APB2ENSETR,This register is used to set the peripheral clock enable bit" bitfld.long 0x8 24. "FDCANEN,FDCANEN" "0,1" bitfld.long 0x8 21. "ADFSDMEN,ADFSDMEN" "0,1" newline bitfld.long 0x8 20. "DFSDMEN,DFSDMEN" "0,1" bitfld.long 0x8 18. "SAI3EN,SAI3EN" "0,1" newline bitfld.long 0x8 17. "SAI2EN,SAI2EN" "0,1" bitfld.long 0x8 16. "SAI1EN,SAI1EN" "0,1" newline bitfld.long 0x8 13. "USART6EN,USART6EN" "0,1" bitfld.long 0x8 10. "SPI5EN,SPI5EN" "0,1" newline bitfld.long 0x8 9. "SPI4EN,SPI4EN" "0,1" bitfld.long 0x8 8. "SPI1EN,SPI1EN" "0,1" newline bitfld.long 0x8 4. "TIM17EN,TIM17EN" "0,1" bitfld.long 0x8 3. "TIM16EN,TIM16EN" "0,1" newline bitfld.long 0x8 2. "TIM15EN,TIM15EN" "0,1" bitfld.long 0x8 1. "TIM8EN,TIM8EN" "0,1" newline bitfld.long 0x8 0. "TIM1EN,TIM1EN" "0,1" line.long 0xC "RCC_MC_APB2ENCLRR,This register is used to clear the peripheral clock enable bit" bitfld.long 0xC 24. "FDCANEN,FDCANEN" "0,1" bitfld.long 0xC 21. "ADFSDMEN,ADFSDMEN" "0,1" newline bitfld.long 0xC 20. "DFSDMEN,DFSDMEN" "0,1" bitfld.long 0xC 18. "SAI3EN,SAI3EN" "0,1" newline bitfld.long 0xC 17. "SAI2EN,SAI2EN" "0,1" bitfld.long 0xC 16. "SAI1EN,SAI1EN" "0,1" newline bitfld.long 0xC 13. "USART6EN,USART6EN" "0,1" bitfld.long 0xC 10. "SPI5EN,SPI5EN" "0,1" newline bitfld.long 0xC 9. "SPI4EN,SPI4EN" "0,1" bitfld.long 0xC 8. "SPI1EN,SPI1EN" "0,1" newline bitfld.long 0xC 4. "TIM17EN,TIM17EN" "0,1" bitfld.long 0xC 3. "TIM16EN,TIM16EN" "0,1" newline bitfld.long 0xC 2. "TIM15EN,TIM15EN" "0,1" bitfld.long 0xC 1. "TIM8EN,TIM8EN" "0,1" newline bitfld.long 0xC 0. "TIM1EN,TIM1EN" "0,1" line.long 0x10 "RCC_MC_APB3ENSETR,This register is used to set the peripheral clock enable bit" bitfld.long 0x10 20. "HDPEN,HDPEN" "0,1" bitfld.long 0x10 16. "DTSEN,DTSEN" "0,1" newline bitfld.long 0x10 13. "VREFEN,VREFEN" "0,1" bitfld.long 0x10 11. "SYSCFGEN,SYSCFGEN" "0,1" newline bitfld.long 0x10 8. "SAI4EN,SAI4EN" "0,1" bitfld.long 0x10 3. "LPTIM5EN,LPTIM5EN" "0,1" newline bitfld.long 0x10 2. "LPTIM4EN,LPTIM4EN" "0,1" bitfld.long 0x10 1. "LPTIM3EN,LPTIM3EN" "0,1" newline bitfld.long 0x10 0. "LPTIM2EN,LPTIM2EN" "0,1" line.long 0x14 "RCC_MC_APB3ENCLRR,This register is used to clear the peripheral clock enable bit" bitfld.long 0x14 20. "HDPEN,HDPEN" "0,1" bitfld.long 0x14 16. "DTSEN,DTSEN" "0,1" newline bitfld.long 0x14 13. "VREFEN,VREFEN" "0,1" bitfld.long 0x14 11. "SYSCFGEN,SYSCFGEN" "0,1" newline bitfld.long 0x14 8. "SAI4EN,SAI4EN" "0,1" bitfld.long 0x14 3. "LPTIM5EN,LPTIM5EN" "0,1" newline bitfld.long 0x14 2. "LPTIM4EN,LPTIM4EN" "0,1" bitfld.long 0x14 1. "LPTIM3EN,LPTIM3EN" "0,1" newline bitfld.long 0x14 0. "LPTIM2EN,LPTIM2EN" "0,1" line.long 0x18 "RCC_MC_AHB2ENSETR,This register is used to set the peripheral clock enable bit" bitfld.long 0x18 16. "SDMMC3EN,SDMMC3EN" "0,1" bitfld.long 0x18 8. "USBOEN,USBOEN" "0,1" newline bitfld.long 0x18 5. "ADC12EN,ADC12EN" "0,1" bitfld.long 0x18 2. "DMAMUXEN,DMAMUXEN" "0,1" newline bitfld.long 0x18 1. "DMA2EN,DMA2EN" "0,1" bitfld.long 0x18 0. "DMA1EN,DMA1EN" "0,1" line.long 0x1C "RCC_MC_AHB2ENCLRR,This register is used to clear the peripheral clock enable bit" bitfld.long 0x1C 16. "SDMMC3EN,SDMMC3EN" "0,1" bitfld.long 0x1C 8. "USBOEN,USBOEN" "0,1" newline bitfld.long 0x1C 5. "ADC12EN,ADC12EN" "0,1" bitfld.long 0x1C 2. "DMAMUXEN,DMAMUXEN" "0,1" newline bitfld.long 0x1C 1. "DMA2EN,DMA2EN" "0,1" bitfld.long 0x1C 0. "DMA1EN,DMA1EN" "0,1" line.long 0x20 "RCC_MC_AHB3ENSETR,This register is used to set the peripheral clock enable bit" bitfld.long 0x20 12. "IPCCEN,IPCCEN" "0,1" bitfld.long 0x20 11. "HSEMEN,HSEMEN" "0,1" newline bitfld.long 0x20 7. "CRC2EN,CRC2EN" "0,1" bitfld.long 0x20 6. "RNG2EN,RNG2EN" "0,1" newline bitfld.long 0x20 5. "HASH2EN,HASH2EN" "0,1" bitfld.long 0x20 4. "CRYP2EN,CRYP2EN" "0,1" newline bitfld.long 0x20 0. "DCMIEN,DCMIEN" "0,1" line.long 0x24 "RCC_MC_AHB3ENCLRR,This register is used to clear the peripheral clock enable bit" bitfld.long 0x24 12. "IPCCEN,IPCCEN" "0,1" bitfld.long 0x24 11. "HSEMEN,HSEMEN" "0,1" newline bitfld.long 0x24 7. "CRC2EN,CRC2EN" "0,1" bitfld.long 0x24 6. "RNG2EN,RNG2EN" "0,1" newline bitfld.long 0x24 5. "HASH2EN,HASH2EN" "0,1" bitfld.long 0x24 4. "CRYP2EN,CRYP2EN" "0,1" newline bitfld.long 0x24 0. "DCMIEN,DCMIEN" "0,1" line.long 0x28 "RCC_MC_AHB4ENSETR,This register is used to set the peripheral clock enable bit" bitfld.long 0x28 10. "GPIOKEN,GPIOKEN" "0,1" bitfld.long 0x28 9. "GPIOJEN,GPIOJEN" "0,1" newline bitfld.long 0x28 8. "GPIOIEN,GPIOIEN" "0,1" bitfld.long 0x28 7. "GPIOHEN,GPIOHEN" "0,1" newline bitfld.long 0x28 6. "GPIOGEN,GPIOGEN" "0,1" bitfld.long 0x28 5. "GPIOFEN,GPIOFEN" "0,1" newline bitfld.long 0x28 4. "GPIOEEN,GPIOEEN" "0,1" bitfld.long 0x28 3. "GPIODEN,GPIODEN" "0,1" newline bitfld.long 0x28 2. "GPIOCEN,GPIOCEN" "0,1" bitfld.long 0x28 1. "GPIOBEN,GPIOBEN" "0,1" newline bitfld.long 0x28 0. "GPIOAEN,GPIOAEN" "0,1" line.long 0x2C "RCC_MC_AHB4ENCLRR,This register is used to clear the peripheral clock enable bit" bitfld.long 0x2C 10. "GPIOKEN,GPIOKEN" "0,1" bitfld.long 0x2C 9. "GPIOJEN,GPIOJEN" "0,1" newline bitfld.long 0x2C 8. "GPIOIEN,GPIOIEN" "0,1" bitfld.long 0x2C 7. "GPIOHEN,GPIOHEN" "0,1" newline bitfld.long 0x2C 6. "GPIOGEN,GPIOGEN" "0,1" bitfld.long 0x2C 5. "GPIOFEN,GPIOFEN" "0,1" newline bitfld.long 0x2C 4. "GPIOEEN,GPIOEEN" "0,1" bitfld.long 0x2C 3. "GPIODEN,GPIODEN" "0,1" newline bitfld.long 0x2C 2. "GPIOCEN,GPIOCEN" "0,1" bitfld.long 0x2C 1. "GPIOBEN,GPIOBEN" "0,1" newline bitfld.long 0x2C 0. "GPIOAEN,GPIOAEN" "0,1" line.long 0x30 "RCC_MC_AXIMENSETR,This register is used to set the peripheral clock enable bit" bitfld.long 0x30 0. "SYSRAMEN,SYSRAMEN" "0,1" line.long 0x34 "RCC_MC_AXIMENCLRR,This register is used to clear the peripheral clock enable bit" bitfld.long 0x34 0. "SYSRAMEN,SYSRAMEN" "0,1" line.long 0x38 "RCC_MC_MLAHBENSETR,This register is used to set the peripheral clock enable bit" bitfld.long 0x38 4. "RETRAMEN,RETRAMEN" "0,1" line.long 0x3C "RCC_MC_MLAHBENCLRR,This register is used to clear the peripheral clock enable bit" bitfld.long 0x3C 4. "RETRAMEN,RETRAMEN" "0,1" group.long 0xB00++0x3F line.long 0x0 "RCC_MP_APB1LPENSETR,This register is used by the MCU in order to clear the PERxLPEN bits" bitfld.long 0x0 31. "MDIOSLPEN,MDIOSLPEN" "0,1" bitfld.long 0x0 29. "DAC12LPEN,DAC12LPEN" "0,1" newline bitfld.long 0x0 27. "CECLPEN,CECLPEN" "0,1" bitfld.long 0x0 26. "SPDIFLPEN,SPDIFLPEN" "0,1" newline bitfld.long 0x0 24. "I2C5LPEN,I2C5LPEN" "0,1" bitfld.long 0x0 23. "I2C3LPEN,I2C3LPEN" "0,1" newline bitfld.long 0x0 22. "I2C2LPEN,I2C2LPEN" "0,1" bitfld.long 0x0 21. "I2C1LPEN,I2C1LPEN" "0,1" newline bitfld.long 0x0 19. "UART8LPEN,UART8LPEN" "0,1" bitfld.long 0x0 18. "UART7LPEN,UART7LPEN" "0,1" newline bitfld.long 0x0 17. "UART5LPEN,UART5LPEN" "0,1" bitfld.long 0x0 16. "UART4LPEN,UART4LPEN" "0,1" newline bitfld.long 0x0 15. "USART3LPEN,USART3LPEN" "0,1" bitfld.long 0x0 14. "USART2LPEN,USART2LPEN" "0,1" newline bitfld.long 0x0 12. "SPI3LPEN,SPI3LPEN" "0,1" bitfld.long 0x0 11. "SPI2LPEN,SPI2LPEN" "0,1" newline bitfld.long 0x0 9. "LPTIM1LPEN,LPTIM1LPEN" "0,1" bitfld.long 0x0 8. "TIM14LPEN,TIM14LPEN" "0,1" newline bitfld.long 0x0 7. "TIM13LPEN,TIM13LPEN" "0,1" bitfld.long 0x0 6. "TIM12LPEN,TIM12LPEN" "0,1" newline bitfld.long 0x0 5. "TIM7LPEN,TIM7LPEN" "0,1" bitfld.long 0x0 4. "TIM6LPEN,TIM6LPEN" "0,1" newline bitfld.long 0x0 3. "TIM5LPEN,TIM5LPEN" "0,1" bitfld.long 0x0 2. "TIM4LPEN,TIM4LPEN" "0,1" newline bitfld.long 0x0 1. "TIM3LPEN,TIM3LPEN" "0,1" bitfld.long 0x0 0. "TIM2LPEN,TIM2LPEN" "0,1" line.long 0x4 "RCC_MP_APB1LPENCLRR,This register is used by the MPU in order to clear the PERxLPEN bits ." bitfld.long 0x4 31. "MDIOSLPEN,MDIOSLPEN" "0,1" bitfld.long 0x4 29. "DAC12LPEN,DAC12LPEN" "0,1" newline bitfld.long 0x4 27. "CECLPEN,CECLPEN" "0,1" bitfld.long 0x4 26. "SPDIFLPEN,SPDIFLPEN" "0,1" newline bitfld.long 0x4 24. "I2C5LPEN,I2C5LPEN" "0,1" bitfld.long 0x4 23. "I2C3LPEN,I2C3LPEN" "0,1" newline bitfld.long 0x4 22. "I2C2LPEN,I2C2LPEN" "0,1" bitfld.long 0x4 21. "I2C1LPEN,I2C1LPEN" "0,1" newline bitfld.long 0x4 19. "UART8LPEN,UART8LPEN" "0,1" bitfld.long 0x4 18. "UART7LPEN,UART7LPEN" "0,1" newline bitfld.long 0x4 17. "UART5LPEN,UART5LPEN" "0,1" bitfld.long 0x4 16. "UART4LPEN,UART4LPEN" "0,1" newline bitfld.long 0x4 15. "USART3LPEN,USART3LPEN" "0,1" bitfld.long 0x4 14. "USART2LPEN,USART2LPEN" "0,1" newline bitfld.long 0x4 12. "SPI3LPEN,SPI3LPEN" "0,1" bitfld.long 0x4 11. "SPI2LPEN,SPI2LPEN" "0,1" newline bitfld.long 0x4 9. "LPTIM1LPEN,LPTIM1LPEN" "0,1" bitfld.long 0x4 8. "TIM14LPEN,TIM14LPEN" "0,1" newline bitfld.long 0x4 7. "TIM13LPEN,TIM13LPEN" "0,1" bitfld.long 0x4 6. "TIM12LPEN,TIM12LPEN" "0,1" newline bitfld.long 0x4 5. "TIM7LPEN,TIM7LPEN" "0,1" bitfld.long 0x4 4. "TIM6LPEN,TIM6LPEN" "0,1" newline bitfld.long 0x4 3. "TIM5LPEN,TIM5LPEN" "0,1" bitfld.long 0x4 2. "TIM4LPEN,TIM4LPEN" "0,1" newline bitfld.long 0x4 1. "TIM3LPEN,TIM3LPEN" "0,1" bitfld.long 0x4 0. "TIM2LPEN,TIM2LPEN" "0,1" line.long 0x8 "RCC_MP_APB2LPENSETR,This register is used by the MCU in order to clear the PERxLPEN bits" bitfld.long 0x8 24. "FDCANLPEN,FDCANLPEN" "0,1" bitfld.long 0x8 21. "ADFSDMLPEN,ADFSDMLPEN" "0,1" newline bitfld.long 0x8 20. "DFSDMLPEN,DFSDMLPEN" "0,1" bitfld.long 0x8 18. "SAI3LPEN,SAI3LPEN" "0,1" newline bitfld.long 0x8 17. "SAI2LPEN,SAI2LPEN" "0,1" bitfld.long 0x8 16. "SAI1LPEN,SAI1LPEN" "0,1" newline bitfld.long 0x8 13. "USART6LPEN,USART6LPEN" "0,1" bitfld.long 0x8 10. "SPI5LPEN,SPI5LPEN" "0,1" newline bitfld.long 0x8 9. "SPI4LPEN,SPI4LPEN" "0,1" bitfld.long 0x8 8. "SPI1LPEN,SPI1LPEN" "0,1" newline bitfld.long 0x8 4. "TIM17LPEN,TIM17LPEN" "0,1" bitfld.long 0x8 3. "TIM16LPEN,TIM16LPEN" "0,1" newline bitfld.long 0x8 2. "TIM15LPEN,TIM15LPEN" "0,1" bitfld.long 0x8 1. "TIM8LPEN,TIM8LPEN" "0,1" newline bitfld.long 0x8 0. "TIM1LPEN,TIM1LPEN" "0,1" line.long 0xC "RCC_MP_APB2LPENCLRR,This register is used by the MCU in order to clear the PERxLPEN bits" bitfld.long 0xC 24. "FDCANLPEN,FDCANLPEN" "0,1" bitfld.long 0xC 21. "ADFSDMLPEN,ADFSDMLPEN" "0,1" newline bitfld.long 0xC 20. "DFSDMLPEN,DFSDMLPEN" "0,1" bitfld.long 0xC 18. "SAI3LPEN,SAI3LPEN" "0,1" newline bitfld.long 0xC 17. "SAI2LPEN,SAI2LPEN" "0,1" bitfld.long 0xC 16. "SAI1LPEN,SAI1LPEN" "0,1" newline bitfld.long 0xC 13. "USART6LPEN,USART6LPEN" "0,1" bitfld.long 0xC 10. "SPI5LPEN,SPI5LPEN" "0,1" newline bitfld.long 0xC 9. "SPI4LPEN,SPI4LPEN" "0,1" bitfld.long 0xC 8. "SPI1LPEN,SPI1LPEN" "0,1" newline bitfld.long 0xC 4. "TIM17LPEN,TIM17LPEN" "0,1" bitfld.long 0xC 3. "TIM16LPEN,TIM16LPEN" "0,1" newline bitfld.long 0xC 2. "TIM15LPEN,TIM15LPEN" "0,1" bitfld.long 0xC 1. "TIM8LPEN,TIM8LPEN" "0,1" newline bitfld.long 0xC 0. "TIM1LPEN,TIM1LPEN" "0,1" line.long 0x10 "RCC_MP_APB3LPENSETR,This register is used by the MCU in order to clear the PERxLPEN bits" bitfld.long 0x10 16. "DTSLPEN,DTSLPEN" "0,1" bitfld.long 0x10 13. "VREFLPEN,VREFLPEN" "0,1" newline bitfld.long 0x10 11. "SYSCFGLPEN,SYSCFGLPEN" "0,1" bitfld.long 0x10 8. "SAI4LPEN,SAI4LPEN" "0,1" newline bitfld.long 0x10 3. "LPTIM5LPEN,LPTIM5LPEN" "0,1" bitfld.long 0x10 2. "LPTIM4LPEN,LPTIM4LPEN" "0,1" newline bitfld.long 0x10 1. "LPTIM3LPEN,LPTIM3LPEN" "0,1" bitfld.long 0x10 0. "LPTIM2LPEN,LPTIM2LPEN" "0,1" line.long 0x14 "RCC_MP_APB3LPENCLRR,This register is used by the MCU in order to clear the PERxLPEN bits" bitfld.long 0x14 16. "DTSLPEN,DTSLPEN" "0,1" bitfld.long 0x14 13. "VREFLPEN,VREFLPEN" "0,1" newline bitfld.long 0x14 11. "SYSCFGLPEN,SYSCFGLPEN" "0,1" bitfld.long 0x14 8. "SAI4LPEN,SAI4LPEN" "0,1" newline bitfld.long 0x14 3. "LPTIM5LPEN,LPTIM5LPEN" "0,1" bitfld.long 0x14 2. "LPTIM4LPEN,LPTIM4LPEN" "0,1" newline bitfld.long 0x14 1. "LPTIM3LPEN,LPTIM3LPEN" "0,1" bitfld.long 0x14 0. "LPTIM2LPEN,LPTIM2LPEN" "0,1" line.long 0x18 "RCC_MP_AHB2LPENSETR,This register is used by the MPU in order to set the PERxLPEN bit." bitfld.long 0x18 16. "SDMMC3LPEN,SDMMC3LPEN" "0,1" bitfld.long 0x18 8. "USBOLPEN,USBOLPEN" "0,1" newline bitfld.long 0x18 5. "ADC12LPEN,ADC12LPEN" "0,1" bitfld.long 0x18 2. "DMAMUXLPEN,DMAMUXLPEN" "0,1" newline bitfld.long 0x18 1. "DMA2LPEN,DMA2LPEN" "0,1" bitfld.long 0x18 0. "DMA1LPEN,DMA1LPEN" "0,1" line.long 0x1C "RCC_MP_AHB2LPENCLRR,This register is used by the MCU in order to clear the PERxLPEN bits" bitfld.long 0x1C 16. "SDMMC3LPEN,SDMMC3LPEN" "0,1" bitfld.long 0x1C 8. "USBOLPEN,USBOLPEN" "0,1" newline bitfld.long 0x1C 5. "ADC12LPEN,ADC12LPEN" "0,1" bitfld.long 0x1C 2. "DMAMUXLPEN,DMAMUXLPEN" "0,1" newline bitfld.long 0x1C 1. "DMA2LPEN,DMA2LPEN" "0,1" bitfld.long 0x1C 0. "DMA1LPEN,DMA1LPEN" "0,1" line.long 0x20 "RCC_MP_AHB3LPENSETR,This register is used by the MPU" bitfld.long 0x20 12. "IPCCLPEN,IPCCLPEN" "0,1" bitfld.long 0x20 11. "HSEMLPEN,HSEMLPEN" "0,1" newline bitfld.long 0x20 7. "CRC2LPEN,CRC2LPEN" "0,1" bitfld.long 0x20 6. "RNG2LPEN,RNG2LPEN" "0,1" newline bitfld.long 0x20 5. "HASH2LPEN,HASH2LPEN" "0,1" bitfld.long 0x20 4. "CRYP2LPEN,CRYP2LPEN" "0,1" newline bitfld.long 0x20 0. "DCMILPEN,DCMILPEN" "0,1" line.long 0x24 "RCC_MP_AHB3LPENCLRR,This register is used by the MPU in order to clear the PERxLPEN bit" bitfld.long 0x24 12. "IPCCLPEN,IPCCLPEN" "0,1" bitfld.long 0x24 11. "HSEMLPEN,HSEMLPEN" "0,1" newline bitfld.long 0x24 7. "CRC2LPEN,CRC2LPEN" "0,1" bitfld.long 0x24 6. "RNG2LPEN,RNG2LPEN" "0,1" newline bitfld.long 0x24 5. "HASH2LPEN,HASH2LPEN" "0,1" bitfld.long 0x24 4. "CRYP2LPEN,CRYP2LPEN" "0,1" newline bitfld.long 0x24 0. "DCMILPEN,DCMILPEN" "0,1" line.long 0x28 "RCC_MP_AHB4LPENSETR,This register is used by the MPU" bitfld.long 0x28 10. "GPIOKLPEN,GPIOKLPEN" "0,1" bitfld.long 0x28 9. "GPIOJLPEN,GPIOJLPEN" "0,1" newline bitfld.long 0x28 8. "GPIOILPEN,GPIOILPEN" "0,1" bitfld.long 0x28 7. "GPIOHLPEN,GPIOHLPEN" "0,1" newline bitfld.long 0x28 6. "GPIOGLPEN,GPIOGLPEN" "0,1" bitfld.long 0x28 5. "GPIOFLPEN,GPIOFLPEN" "0,1" newline bitfld.long 0x28 4. "GPIOELPEN,GPIOELPEN" "0,1" bitfld.long 0x28 3. "GPIODLPEN,GPIODLPEN" "0,1" newline bitfld.long 0x28 2. "GPIOCLPEN,GPIOCLPEN" "0,1" bitfld.long 0x28 1. "GPIOBLPEN,GPIOBLPEN" "0,1" newline bitfld.long 0x28 0. "GPIOALPEN,GPIOALPEN" "0,1" line.long 0x2C "RCC_MP_AHB4LPENCLRR,This register is used by the MPU" bitfld.long 0x2C 10. "GPIOKLPEN,GPIOKLPEN" "0,1" bitfld.long 0x2C 9. "GPIOJLPEN,GPIOJLPEN" "0,1" newline bitfld.long 0x2C 8. "GPIOILPEN,GPIOILPEN" "0,1" bitfld.long 0x2C 7. "GPIOHLPEN,GPIOHLPEN" "0,1" newline bitfld.long 0x2C 6. "GPIOGLPEN,GPIOGLPEN" "0,1" bitfld.long 0x2C 5. "GPIOFLPEN,GPIOFLPEN" "0,1" newline bitfld.long 0x2C 4. "GPIOELPEN,GPIOELPEN" "0,1" bitfld.long 0x2C 3. "GPIODLPEN,GPIODLPEN" "0,1" newline bitfld.long 0x2C 2. "GPIOCLPEN,GPIOCLPEN" "0,1" bitfld.long 0x2C 1. "GPIOBLPEN,GPIOBLPEN" "0,1" newline bitfld.long 0x2C 0. "GPIOALPEN,GPIOALPEN" "0,1" line.long 0x30 "RCC_MP_AXIMLPENSETR,This register is used by the MPU" bitfld.long 0x30 0. "SYSRAMLPEN,SYSRAMLPEN" "0,1" line.long 0x34 "RCC_MP_AXIMLPENCLRR,This register is used by the MPU" bitfld.long 0x34 0. "SYSRAMLPEN,SYSRAMLPEN" "0,1" line.long 0x38 "RCC_MP_MLAHBLPENSETR,This register is used by the MPU in order to set the PERxLPEN bit" bitfld.long 0x38 4. "RETRAMLPEN,RETRAMLPEN" "0,1" bitfld.long 0x38 2. "SRAM34LPEN,SRAM34LPEN" "0,1" newline bitfld.long 0x38 1. "SRAM2LPEN,SRAM2LPEN" "0,1" bitfld.long 0x38 0. "SRAM1LPEN,SRAM1LPEN" "0,1" line.long 0x3C "RCC_MP_MLAHBLPENCLRR,This register is used by the MPU in order to clear the PERxLPEN bit" bitfld.long 0x3C 4. "RETRAMLPEN,RETRAMLPEN" "0,1" bitfld.long 0x3C 2. "SRAM34LPEN,SRAM34LPEN" "0,1" newline bitfld.long 0x3C 1. "SRAM2LPEN,SRAM2LPEN" "0,1" bitfld.long 0x3C 0. "SRAM1LPEN,SRAM1LPEN" "0,1" group.long 0xB80++0x3F line.long 0x0 "RCC_MC_APB1LPENSETR,This register is used by the MCU in order to set the PERxLPEN bit." bitfld.long 0x0 31. "MDIOSLPEN,MDIOSLPEN" "0,1" bitfld.long 0x0 29. "DAC12LPEN,DAC12LPEN" "0,1" newline bitfld.long 0x0 28. "WWDG1LPEN,WWDG1LPEN" "0,1" bitfld.long 0x0 27. "CECLPEN,CECLPEN" "0,1" newline bitfld.long 0x0 26. "SPDIFLPEN,SPDIFLPEN" "0,1" bitfld.long 0x0 24. "I2C5LPEN,I2C5LPEN" "0,1" newline bitfld.long 0x0 23. "I2C3LPEN,I2C3LPEN" "0,1" bitfld.long 0x0 22. "I2C2LPEN,I2C2LPEN" "0,1" newline bitfld.long 0x0 21. "I2C1LPEN,I2C1LPEN" "0,1" bitfld.long 0x0 19. "UART8LPEN,UART8LPEN" "0,1" newline bitfld.long 0x0 18. "UART7LPEN,UART7LPEN" "0,1" bitfld.long 0x0 17. "UART5LPEN,UART5LPEN" "0,1" newline bitfld.long 0x0 16. "UART4LPEN,UART4LPEN" "0,1" bitfld.long 0x0 15. "USART3LPEN,USART3LPEN" "0,1" newline bitfld.long 0x0 14. "USART2LPEN,USART2LPEN" "0,1" bitfld.long 0x0 12. "SPI3LPEN,SPI3LPEN" "0,1" newline bitfld.long 0x0 11. "SPI2LPEN,SPI2LPEN" "0,1" bitfld.long 0x0 9. "LPTIM1LPEN,LPTIM1LPEN" "0,1" newline bitfld.long 0x0 8. "TIM14LPEN,TIM14LPEN" "0,1" bitfld.long 0x0 7. "TIM13LPEN,TIM13LPEN" "0,1" newline bitfld.long 0x0 6. "TIM12LPEN,TIM12LPEN" "0,1" bitfld.long 0x0 5. "TIM7LPEN,TIM7LPEN" "0,1" newline bitfld.long 0x0 4. "TIM6LPEN,TIM6LPEN" "0,1" bitfld.long 0x0 3. "TIM5LPEN,TIM5LPEN" "0,1" newline bitfld.long 0x0 2. "TIM4LPEN,TIM4LPEN" "0,1" bitfld.long 0x0 1. "TIM3LPEN,TIM3LPEN" "0,1" newline bitfld.long 0x0 0. "TIM2LPEN,TIM2LPEN" "0,1" line.long 0x4 "RCC_MC_APB1LPENCLRR,This register is used by the MCU in order to clear the PERxLPEN bits" bitfld.long 0x4 31. "MDIOSLPEN,MDIOSLPEN" "0,1" bitfld.long 0x4 29. "DAC12LPEN,DAC12LPEN" "0,1" newline bitfld.long 0x4 28. "WWDG1LPEN,WWDG1LPEN" "0,1" bitfld.long 0x4 27. "CECLPEN,CECLPEN" "0,1" newline bitfld.long 0x4 26. "SPDIFLPEN,SPDIFLPEN" "0,1" bitfld.long 0x4 24. "I2C5LPEN,I2C5LPEN" "0,1" newline bitfld.long 0x4 23. "I2C3LPEN,I2C3LPEN" "0,1" bitfld.long 0x4 22. "I2C2LPEN,I2C2LPEN" "0,1" newline bitfld.long 0x4 21. "I2C1LPEN,I2C1LPEN" "0,1" bitfld.long 0x4 19. "UART8LPEN,UART8LPEN" "0,1" newline bitfld.long 0x4 18. "UART7LPEN,UART7LPEN" "0,1" bitfld.long 0x4 17. "UART5LPEN,UART5LPEN" "0,1" newline bitfld.long 0x4 16. "UART4LPEN,UART4LPEN" "0,1" bitfld.long 0x4 15. "USART3LPEN,USART3LPEN" "0,1" newline bitfld.long 0x4 14. "USART2LPEN,USART2LPEN" "0,1" bitfld.long 0x4 12. "SPI3LPEN,SPI3LPEN" "0,1" newline bitfld.long 0x4 11. "SPI2LPEN,SPI2LPEN" "0,1" bitfld.long 0x4 9. "LPTIM1LPEN,LPTIM1LPEN" "0,1" newline bitfld.long 0x4 8. "TIM14LPEN,TIM14LPEN" "0,1" bitfld.long 0x4 7. "TIM13LPEN,TIM13LPEN" "0,1" newline bitfld.long 0x4 6. "TIM12LPEN,TIM12LPEN" "0,1" bitfld.long 0x4 5. "TIM7LPEN,TIM7LPEN" "0,1" newline bitfld.long 0x4 4. "TIM6LPEN,TIM6LPEN" "0,1" bitfld.long 0x4 3. "TIM5LPEN,TIM5LPEN" "0,1" newline bitfld.long 0x4 2. "TIM4LPEN,TIM4LPEN" "0,1" bitfld.long 0x4 1. "TIM3LPEN,TIM3LPEN" "0,1" newline bitfld.long 0x4 0. "TIM2LPEN,TIM2LPEN" "0,1" line.long 0x8 "RCC_MC_APB2LPENSETR,This register is used by the MCU in order to set the PERxLPEN bit." bitfld.long 0x8 24. "FDCANLPEN,FDCANLPEN" "0,1" bitfld.long 0x8 21. "ADFSDMLPEN,ADFSDMLPEN" "0,1" newline bitfld.long 0x8 20. "DFSDMLPEN,DFSDMLPEN" "0,1" bitfld.long 0x8 18. "SAI3LPEN,SAI3LPEN" "0,1" newline bitfld.long 0x8 17. "SAI2LPEN,SAI2LPEN" "0,1" bitfld.long 0x8 16. "SAI1LPEN,SAI1LPEN" "0,1" newline bitfld.long 0x8 13. "USART6LPEN,USART6LPEN" "0,1" bitfld.long 0x8 10. "SPI5LPEN,SPI5LPEN" "0,1" newline bitfld.long 0x8 9. "SPI4LPEN,SPI4LPEN" "0,1" bitfld.long 0x8 8. "SPI1LPEN,SPI1LPEN" "0,1" newline bitfld.long 0x8 4. "TIM17LPEN,TIM17LPEN" "0,1" bitfld.long 0x8 3. "TIM16LPEN,TIM16LPEN" "0,1" newline bitfld.long 0x8 2. "TIM15LPEN,TIM15LPEN" "0,1" bitfld.long 0x8 1. "TIM8LPEN,TIM8LPEN" "0,1" newline bitfld.long 0x8 0. "TIM1LPEN,TIM1LPEN" "0,1" line.long 0xC "RCC_MC_APB2LPENCLRR,This register is used by the MCU in order to clear the PERxLPEN bit" bitfld.long 0xC 24. "FDCANLPEN,FDCANLPEN" "0,1" bitfld.long 0xC 21. "ADFSDMLPEN,ADFSDMLPEN" "0,1" newline bitfld.long 0xC 20. "DFSDMLPEN,DFSDMLPEN" "0,1" bitfld.long 0xC 18. "SAI3LPEN,SAI3LPEN" "0,1" newline bitfld.long 0xC 17. "SAI2LPEN,SAI2LPEN" "0,1" bitfld.long 0xC 16. "SAI1LPEN,SAI1LPEN" "0,1" newline bitfld.long 0xC 13. "USART6LPEN,USART6LPEN" "0,1" bitfld.long 0xC 10. "SPI5LPEN,SPI5LPEN" "0,1" newline bitfld.long 0xC 9. "SPI4LPEN,SPI4LPEN" "0,1" bitfld.long 0xC 8. "SPI1LPEN,SPI1LPEN" "0,1" newline bitfld.long 0xC 4. "TIM17LPEN,TIM17LPEN" "0,1" bitfld.long 0xC 3. "TIM16LPEN,TIM16LPEN" "0,1" newline bitfld.long 0xC 2. "TIM15LPEN,TIM15LPEN" "0,1" bitfld.long 0xC 1. "TIM8LPEN,TIM8LPEN" "0,1" newline bitfld.long 0xC 0. "TIM1LPEN,TIM1LPEN" "0,1" line.long 0x10 "RCC_MC_APB3LPENSETR,This register is used by the MCU in order to set the PERxLPEN bit." bitfld.long 0x10 16. "DTSLPEN,DTSLPEN" "0,1" bitfld.long 0x10 13. "VREFLPEN,VREFLPEN" "0,1" newline bitfld.long 0x10 11. "SYSCFGLPEN,SYSCFGLPEN" "0,1" bitfld.long 0x10 8. "SAI4LPEN,SAI4LPEN" "0,1" newline bitfld.long 0x10 3. "LPTIM5LPEN,LPTIM5LPEN" "0,1" bitfld.long 0x10 2. "LPTIM4LPEN,LPTIM4LPEN" "0,1" newline bitfld.long 0x10 1. "LPTIM3LPEN,LPTIM3LPEN" "0,1" bitfld.long 0x10 0. "LPTIM2LPEN,LPTIM2LPEN" "0,1" line.long 0x14 "RCC_MC_APB3LPENCLRR,This register is used by the MCU in order to clear the PERxLPEN bit" bitfld.long 0x14 16. "DTSLPEN,DTSLPEN" "0,1" bitfld.long 0x14 13. "VREFLPEN,VREFLPEN" "0,1" newline bitfld.long 0x14 11. "SYSCFGLPEN,SYSCFGLPEN" "0,1" bitfld.long 0x14 8. "SAI4LPEN,SAI4LPEN" "0,1" newline bitfld.long 0x14 3. "LPTIM5LPEN,LPTIM5LPEN" "0,1" bitfld.long 0x14 2. "LPTIM4LPEN,LPTIM4LPEN" "0,1" newline bitfld.long 0x14 1. "LPTIM3LPEN,LPTIM3LPEN" "0,1" bitfld.long 0x14 0. "LPTIM2LPEN,LPTIM2LPEN" "0,1" line.long 0x18 "RCC_MC_AHB2LPENSETR,This register is used by the MCU in order to set the PERxLPEN bit." bitfld.long 0x18 16. "SDMMC3LPEN,SDMMC3LPEN" "0,1" bitfld.long 0x18 8. "USBOLPEN,USBOLPEN" "0,1" newline bitfld.long 0x18 5. "ADC12LPEN,ADC12LPEN" "0,1" bitfld.long 0x18 2. "DMAMUXLPEN,DMAMUXLPEN" "0,1" newline bitfld.long 0x18 1. "DMA2LPEN,DMA2LPEN" "0,1" bitfld.long 0x18 0. "DMA1LPEN,DMA1LPEN" "0,1" line.long 0x1C "RCC_MC_AHB2LPENCLRR,This register is used by the MCU in order to clear the PERxLPEN bit" bitfld.long 0x1C 16. "SDMMC3LPEN,SDMMC3LPEN" "0,1" bitfld.long 0x1C 8. "USBOLPEN,USBOLPEN" "0,1" newline bitfld.long 0x1C 5. "ADC12LPEN,ADC12LPEN" "0,1" bitfld.long 0x1C 2. "DMAMUXLPEN,DMAMUXLPEN" "0,1" newline bitfld.long 0x1C 1. "DMA2LPEN,DMA2LPEN" "0,1" bitfld.long 0x1C 0. "DMA1LPEN,DMA1LPEN" "0,1" line.long 0x20 "RCC_MC_AHB3LPENSETR,This register is used by the MCU in order to set the PERxLPEN bit." bitfld.long 0x20 12. "IPCCLPEN,IPCCLPEN" "0,1" bitfld.long 0x20 11. "HSEMLPEN,HSEMLPEN" "0,1" newline bitfld.long 0x20 7. "CRC2LPEN,CRC2LPEN" "0,1" bitfld.long 0x20 6. "RNG2LPEN,RNG2LPEN" "0,1" newline bitfld.long 0x20 5. "HASH2LPEN,HASH2LPEN" "0,1" bitfld.long 0x20 4. "CRYP2LPEN,CRYP2LPEN" "0,1" newline bitfld.long 0x20 0. "DCMILPEN,DCMILPEN" "0,1" line.long 0x24 "RCC_MC_AHB3LPENCLRR,This register is used by the MCU in order to clear the PERxLPEN bit" bitfld.long 0x24 12. "IPCCLPEN,IPCCLPEN" "0,1" bitfld.long 0x24 11. "HSEMLPEN,HSEMLPEN" "0,1" newline bitfld.long 0x24 7. "CRC2LPEN,CRC2LPEN" "0,1" bitfld.long 0x24 6. "RNG2LPEN,RNG2LPEN" "0,1" newline bitfld.long 0x24 5. "HASH2LPEN,HASH2LPEN" "0,1" bitfld.long 0x24 4. "CRYP2LPEN,CRYP2LPEN" "0,1" newline bitfld.long 0x24 0. "DCMILPEN,DCMILPEN" "0,1" line.long 0x28 "RCC_MC_AHB4LPENSETR,This register is used by the MCU in order to set the PERxLPEN bit." bitfld.long 0x28 10. "GPIOKLPEN,GPIOKLPEN" "0,1" bitfld.long 0x28 9. "GPIOJLPEN,GPIOJLPEN" "0,1" newline bitfld.long 0x28 8. "GPIOILPEN,GPIOILPEN" "0,1" bitfld.long 0x28 7. "GPIOHLPEN,GPIOHLPEN" "0,1" newline bitfld.long 0x28 6. "GPIOGLPEN,GPIOGLPEN" "0,1" bitfld.long 0x28 5. "GPIOFLPEN,GPIOFLPEN" "0,1" newline bitfld.long 0x28 4. "GPIOELPEN,GPIOELPEN" "0,1" bitfld.long 0x28 3. "GPIODLPEN,GPIODLPEN" "0,1" newline bitfld.long 0x28 2. "GPIOCLPEN,GPIOCLPEN" "0,1" bitfld.long 0x28 1. "GPIOBLPEN,GPIOBLPEN" "0,1" newline bitfld.long 0x28 0. "GPIOALPEN,GPIOALPEN" "0,1" line.long 0x2C "RCC_MC_AHB4LPENCLRR,This register is used by the MCU in order to clear the PERxLPEN bit of the corresponding peripheral." bitfld.long 0x2C 10. "GPIOKLPEN,GPIOKLPEN" "0,1" bitfld.long 0x2C 9. "GPIOJLPEN,GPIOJLPEN" "0,1" newline bitfld.long 0x2C 8. "GPIOILPEN,GPIOILPEN" "0,1" bitfld.long 0x2C 7. "GPIOHLPEN,GPIOHLPEN" "0,1" newline bitfld.long 0x2C 6. "GPIOGLPEN,GPIOGLPEN" "0,1" bitfld.long 0x2C 5. "GPIOFLPEN,GPIOFLPEN" "0,1" newline bitfld.long 0x2C 4. "GPIOELPEN,GPIOELPEN" "0,1" bitfld.long 0x2C 3. "GPIODLPEN,GPIODLPEN" "0,1" newline bitfld.long 0x2C 2. "GPIOCLPEN,GPIOCLPEN" "0,1" bitfld.long 0x2C 1. "GPIOBLPEN,GPIOBLPEN" "0,1" newline bitfld.long 0x2C 0. "GPIOALPEN,GPIOALPEN" "0,1" line.long 0x30 "RCC_MC_AXIMLPENSETR,This register is used by the MCU in order to set the PERxLPEN bit of the corresponding peripheral." bitfld.long 0x30 0. "SYSRAMLPEN,SYSRAMLPEN" "0,1" line.long 0x34 "RCC_MC_AXIMLPENCLRR,This register is used by the MCU in order to clear the PERxLPEN bit of the corresponding peripheral." bitfld.long 0x34 0. "SYSRAMLPEN,SYSRAMLPEN" "0,1" line.long 0x38 "RCC_MC_MLAHBLPENSETR,This register is used by the MCU in order to set the PERxLPEN bit of the corresponding peripheral." bitfld.long 0x38 4. "RETRAMLPEN,RETRAMLPEN" "0,1" bitfld.long 0x38 2. "SRAM34LPEN,SRAM34LPEN" "0,1" newline bitfld.long 0x38 1. "SRAM2LPEN,SRAM2LPEN" "0,1" bitfld.long 0x38 0. "SRAM1LPEN,SRAM1LPEN" "0,1" line.long 0x3C "RCC_MC_MLAHBLPENCLRR,This register is used by the MCU in order to clear the PERxLPEN bit of the corresponding peripheral." bitfld.long 0x3C 4. "RETRAMLPEN,RETRAMLPEN" "0,1" bitfld.long 0x3C 2. "SRAM34LPEN,SRAM34LPEN" "0,1" newline bitfld.long 0x3C 1. "SRAM2LPEN,SRAM2LPEN" "0,1" bitfld.long 0x3C 0. "SRAM1LPEN,SRAM1LPEN" "0,1" group.long 0xC00++0x3 line.long 0x0 "RCC_MC_RSTSCLRR,This register is used by the MCU to check the reset source." bitfld.long 0x0 10. "WWDG1RSTF,WWDG1RSTF" "0,1" bitfld.long 0x0 9. "IWDG2RSTF,IWDG2RSTF" "0,1" newline bitfld.long 0x0 8. "IWDG1RSTF,IWDG1RSTF" "0,1" bitfld.long 0x0 7. "MCSYSRSTF,MCSYSRSTF" "0,1" newline bitfld.long 0x0 6. "MPSYSRSTF,MPSYSRSTF" "0,1" bitfld.long 0x0 5. "MCURSTF,MCURSTF" "0,1" newline bitfld.long 0x0 4. "VCORERSTF,VCORERSTF" "0,1" bitfld.long 0x0 3. "HCSSRSTF,HCSSRSTF" "0,1" newline bitfld.long 0x0 2. "PADRSTF,PADRSTF" "0,1" bitfld.long 0x0 1. "BORRSTF,BORRSTF" "0,1" newline bitfld.long 0x0 0. "PORRSTF,PORRSTF" "0,1" group.long 0xC14++0x7 line.long 0x0 "RCC_MC_CIER,This register shall be used by the MCU to control the interrupt source enable. Refer to Section10.5: RCC interrupts for more details." bitfld.long 0x0 20. "WKUPIE,WKUPIE" "0,1" bitfld.long 0x0 16. "LSECSSIE,LSECSSIE" "0,1" newline bitfld.long 0x0 11. "PLL4DYIE,PLL4DYIE" "0,1" bitfld.long 0x0 10. "PLL3DYIE,PLL3DYIE" "0,1" newline bitfld.long 0x0 9. "PLL2DYIE,PLL2DYIE" "0,1" bitfld.long 0x0 8. "PLL1DYIE,PLL1DYIE" "0,1" newline bitfld.long 0x0 4. "CSIRDYIE,CSIRDYIE" "0,1" bitfld.long 0x0 3. "HSERDYIE,HSERDYIE" "0,1" newline bitfld.long 0x0 2. "HSIRDYIE,HSIRDYIE" "0,1" bitfld.long 0x0 1. "LSERDYIE,LSERDYIE" "0,1" newline bitfld.long 0x0 0. "LSIRDYIE,LSIRDYIE" "0,1" line.long 0x4 "RCC_MC_CIFR,This register shall be used by the MCU in order to read and clear the interrupt flags." bitfld.long 0x4 20. "WKUPF,WKUPF" "0,1" bitfld.long 0x4 16. "LSECSSF,LSECSSF" "0,1" newline bitfld.long 0x4 11. "PLL4DYF,PLL4DYF" "0,1" bitfld.long 0x4 10. "PLL3DYF,PLL3DYF" "0,1" newline bitfld.long 0x4 9. "PLL2DYF,PLL2DYF" "0,1" bitfld.long 0x4 8. "PLL1DYF,PLL1DYF" "0,1" newline bitfld.long 0x4 4. "CSIRDYF,CSIRDYF" "0,1" bitfld.long 0x4 3. "HSERDYF,HSERDYF" "0,1" newline bitfld.long 0x4 2. "HSIRDYF,HSIRDYF" "0,1" bitfld.long 0x4 1. "LSERDYF,LSERDYF" "0,1" newline bitfld.long 0x4 0. "LSIRDYF,LSIRDYF" "0,1" endif group.long 0xFF4++0xB line.long 0x0 "RCC_VERR,This register gives the IP version" sif (cpuis("STM32MP13*")) hexmask.long.byte 0x0 4.--7. 1. "MAJREV,Major Revision of the IP" hexmask.long.byte 0x0 0.--3. 1. "MINREV,Minor Revision of the IP" endif sif (cpuis("STM32MP151*")) hexmask.long.byte 0x0 4.--7. 1. "MAJREV,MAJREV" hexmask.long.byte 0x0 0.--3. 1. "MINREV,MINREV" endif sif (cpuis("STM32MP153*")) hexmask.long.byte 0x0 4.--7. 1. "MAJREV,MAJREV" hexmask.long.byte 0x0 0.--3. 1. "MINREV,MINREV" endif sif (cpuis("STM32MP157*")) hexmask.long.byte 0x0 4.--7. 1. "MAJREV,MAJREV" newline hexmask.long.byte 0x0 0.--3. 1. "MINREV,MINREV" endif line.long 0x4 "RCC_IDR,This register gives the unique identifier of the RCC" sif (cpuis("STM32MP13*")) hexmask.long 0x4 0.--31. 1. "ID,Identifier of the RCC" endif sif (cpuis("STM32MP151*")) hexmask.long 0x4 0.--31. 1. "ID,ID" endif sif (cpuis("STM32MP153*")) hexmask.long 0x4 0.--31. 1. "ID,ID" endif sif (cpuis("STM32MP157*")) hexmask.long 0x4 0.--31. 1. "ID,ID" endif line.long 0x8 "RCC_SIDR,This register gives the decoding space. which is for the RCC of 4 kB." sif (cpuis("STM32MP13*")) hexmask.long 0x8 0.--31. 1. "SID,Decoding space is 4 kbytes" endif sif (cpuis("STM32MP151*")) hexmask.long 0x8 0.--31. 1. "SID,SID" endif sif (cpuis("STM32MP153*")) hexmask.long 0x8 0.--31. 1. "SID,SID" endif sif (cpuis("STM32MP157*")) hexmask.long 0x8 0.--31. 1. "SID,SID" endif sif (cpuis("STM32MP151*")) rgroup.long 0xFF4++0x3 line.long 0x0 "RCC_VERR,This register gives the IP version" endif sif (cpuis("STM32MP151*")) rgroup.long 0xFF8++0x3 line.long 0x0 "RCC_IDR,This register gives the unique identifier of the RCC" endif sif (cpuis("STM32MP151*")) rgroup.long 0xFFC++0x3 line.long 0x0 "RCC_SIDR,This register gives the decoding space. which is for the RCC of 4 kB." endif sif (cpuis("STM32MP153*")) rgroup.long 0xFF4++0x3 line.long 0x0 "RCC_VERR,This register gives the IP version" endif sif (cpuis("STM32MP153*")) rgroup.long 0xFF8++0x3 line.long 0x0 "RCC_IDR,This register gives the unique identifier of the RCC" endif sif (cpuis("STM32MP153*")) rgroup.long 0xFFC++0x3 line.long 0x0 "RCC_SIDR,This register gives the decoding space. which is for the RCC of 4 kB." endif sif (cpuis("STM32MP157*")) rgroup.long 0xFF4++0x3 line.long 0x0 "RCC_VERR,This register gives the IP version" endif sif (cpuis("STM32MP157*")) rgroup.long 0xFF8++0x3 line.long 0x0 "RCC_IDR,This register gives the unique identifier of the RCC" endif sif (cpuis("STM32MP157*")) rgroup.long 0xFFC++0x3 line.long 0x0 "RCC_SIDR,This register gives the decoding space. which is for the RCC of 4 kB." endif tree.end tree "RNG (True Random Number Generator)" base ad:0x0 sif (cpuis("STM32MP13*")) tree "RNG" base ad:0x54004000 group.long 0x0++0x7 line.long 0x0 "RNG_CR,RNG control register" bitfld.long 0x0 5. "CED,Clock error detection" "0: Clock error detection is enable,1: Clock error detection is disable" bitfld.long 0x0 3. "IE,Interrupt Enable" "0: RNG Interrupt is disabled,1: RNG Interrupt is enabled. An interrupt is.." newline bitfld.long 0x0 2. "RNGEN,True random number generator enable" "0: True random number generator is disabled. Analog..,1: True random number generator is enabled." line.long 0x4 "RNG_SR,RNG status register" bitfld.long 0x4 6. "SEIS,Seed error interrupt status" "0: No faulty sequence detected,1: At least one faulty sequence has been detected." bitfld.long 0x4 5. "CEIS,Clock error interrupt status" "0: The RNG clock is correct (fRNGCLK> fHCLK/32),1: The RNG has been detected too slow (fRNGCLK<.." newline rbitfld.long 0x4 2. "SECS,Seed error current status" "0: No faulty sequence has currently been detected.,1: At least one of the following faulty sequence.." rbitfld.long 0x4 1. "CECS,Clock error current status" "0: The RNG clock is correct (fRNGCLK> fHCLK/32). If..,1: The RNG clock is too slow (fRNGCLK< fHCLK/32)." newline rbitfld.long 0x4 0. "DRDY,Data Ready" "0: The RNG_DR register is not yet valid no random..,1: The RNG_DR register contains valid random data." rgroup.long 0x8++0x3 line.long 0x0 "RNG_DR,RNG data register" hexmask.long 0x0 0.--31. 1. "RNDATA,Random data" rgroup.long 0x3F4++0xB line.long 0x0 "RNG_VERR,RNG version register" hexmask.long.byte 0x0 4.--7. 1. "MAJREV,Major revision" hexmask.long.byte 0x0 0.--3. 1. "MINREV,Minor revision" line.long 0x4 "RNG_IPIDR,RNG identification register" hexmask.long 0x4 0.--31. 1. "ID,Identification code of the peripheral" line.long 0x8 "RNG_SIDR,RNG size ID register" hexmask.long 0x8 0.--31. 1. "SID,Size identification code" tree.end endif sif (cpuis("STM32MP151*")||cpuis("STM32MP153*")||cpuis("STM32MP157*")) tree "RNG1" base ad:0x54003000 group.long 0x0++0x7 line.long 0x0 "RNG_CR,RNG control register" bitfld.long 0x0 5. "CED,CED" "0,1" bitfld.long 0x0 3. "IE,IE" "0,1" bitfld.long 0x0 2. "RNGEN,RNGEN" "0,1" line.long 0x4 "RNG_SR,RNG status register" bitfld.long 0x4 6. "SEIS,SEIS" "0,1" bitfld.long 0x4 5. "CEIS,CEIS" "0,1" rbitfld.long 0x4 2. "SECS,SECS" "0,1" rbitfld.long 0x4 1. "CECS,CECS" "0,1" rbitfld.long 0x4 0. "DRDY,DRDY" "0,1" rgroup.long 0x8++0x3 line.long 0x0 "RNG_DR,The RNG_DR register is a read-only register." hexmask.long 0x0 0.--31. 1. "RNDATA,RNDATA" rgroup.long 0x3F0++0xF line.long 0x0 "RNG_HWCFGR,RNG hardware configuration register" line.long 0x4 "RNG_VERR,RNG version register" hexmask.long.byte 0x4 4.--7. 1. "MAJREV,MAJREV" hexmask.long.byte 0x4 0.--3. 1. "MINREV,MINREV" line.long 0x8 "RNG_IPIDR,RNG identification register" hexmask.long 0x8 0.--31. 1. "ID,ID" line.long 0xC "RNG_SIDR,RNG size ID register" hexmask.long 0xC 0.--31. 1. "SID,SID" tree.end endif sif (cpuis("STM32MP151*")||cpuis("STM32MP153*")||cpuis("STM32MP157*")) tree "RNG2" base ad:0x4C003000 group.long 0x0++0x7 line.long 0x0 "RNG_CR,RNG control register" bitfld.long 0x0 5. "CED,CED" "0,1" bitfld.long 0x0 3. "IE,IE" "0,1" bitfld.long 0x0 2. "RNGEN,RNGEN" "0,1" line.long 0x4 "RNG_SR,RNG status register" bitfld.long 0x4 6. "SEIS,SEIS" "0,1" bitfld.long 0x4 5. "CEIS,CEIS" "0,1" rbitfld.long 0x4 2. "SECS,SECS" "0,1" rbitfld.long 0x4 1. "CECS,CECS" "0,1" rbitfld.long 0x4 0. "DRDY,DRDY" "0,1" rgroup.long 0x8++0x3 line.long 0x0 "RNG_DR,The RNG_DR register is a read-only register." hexmask.long 0x0 0.--31. 1. "RNDATA,RNDATA" rgroup.long 0x3F0++0xF line.long 0x0 "RNG_HWCFGR,RNG hardware configuration register" line.long 0x4 "RNG_VERR,RNG version register" hexmask.long.byte 0x4 4.--7. 1. "MAJREV,MAJREV" hexmask.long.byte 0x4 0.--3. 1. "MINREV,MINREV" line.long 0x8 "RNG_IPIDR,RNG identification register" hexmask.long 0x8 0.--31. 1. "ID,ID" line.long 0xC "RNG_SIDR,RNG size ID register" hexmask.long 0xC 0.--31. 1. "SID,SID" tree.end endif tree.end tree "RTC (Real-Time Clock)" base ad:0x5C004000 group.long 0x0++0x7 line.long 0x0 "RTC_TR,The RTC_TR is the calendar time shadow register. This register must be written in initialization mode only. Refer to Calendar initialization and configuration on page1830 and Reading the calendar on page1831. This register is write protected. The.." bitfld.long 0x0 22. "PM,PM" "0,1" bitfld.long 0x0 20.--21. "HT,HT" "0,1,2,3" hexmask.long.byte 0x0 16.--19. 1. "HU,HU" bitfld.long 0x0 12.--14. "MNT,MNT" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 8.--11. 1. "MNU,MNU" bitfld.long 0x0 4.--6. "ST,ST" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 0.--3. 1. "SU,SU" line.long 0x4 "RTC_DR,The RTC_DR is the calendar date shadow register. This register must be written in initialization mode only. Refer to Calendar initialization and configuration on page1830 and Reading the calendar on page1831. This register is write protected. The.." hexmask.long.byte 0x4 20.--23. 1. "YT,YT" hexmask.long.byte 0x4 16.--19. 1. "YU,YU" bitfld.long 0x4 13.--15. "WDU,WDU" "0,1,2,3,4,5,6,7" bitfld.long 0x4 12. "MT,MT" "0,1" hexmask.long.byte 0x4 8.--11. 1. "MU,MU" bitfld.long 0x4 4.--5. "DT,DT" "0,1,2,3" newline hexmask.long.byte 0x4 0.--3. 1. "DU,DU" rgroup.long 0x8++0x3 line.long 0x0 "RTC_SSR,RTC sub second register" hexmask.long.word 0x0 0.--15. 1. "SS,SS" group.long 0xC++0xF line.long 0x0 "RTC_ICSR,This register is write protected. The write access procedure is described in RTC register write protection on page1830. This register can be globally protected. or each bit of this register can be individually protected against non-secure.." rbitfld.long 0x0 16. "RECALPF,RECALPF" "0,1" bitfld.long 0x0 7. "INIT,INIT" "0,1" rbitfld.long 0x0 6. "INITF,INITF" "0,1" bitfld.long 0x0 5. "RSF,RSF" "0,1" rbitfld.long 0x0 4. "INITS,INITS" "0,1" rbitfld.long 0x0 3. "SHPF,SHPF" "0,1" newline rbitfld.long 0x0 2. "WUTWF,WUTWF" "0,1" rbitfld.long 0x0 1. "ALRBWF,ALRBWF" "0,1" rbitfld.long 0x0 0. "ALRAWF,ALRAWF" "0,1" line.long 0x4 "RTC_PRER,This register must be written in initialization mode only. The initialization must be performed in two separate write accesses. Refer to Calendar initialization and configuration on page1830. This register is write protected. The write access.." hexmask.long.byte 0x4 16.--22. 1. "PREDIV_A,PREDIV_A" hexmask.long.word 0x4 0.--14. 1. "PREDIV_S,PREDIV_S" line.long 0x8 "RTC_WUTR,This register can be written only when WUTWF is set to 1 in RTC_ICSR. This register is write protected. The write access procedure is described in RTC register write protection on page1830. This register can be protected against non-secure.." hexmask.long.word 0x8 0.--15. 1. "WUT,WUT" line.long 0xC "RTC_CR,This register is write protected. The write access procedure is described in RTC register write protection on page1830. This register can be globally protected. or each bit of this register can be individually protected against non-secure access." bitfld.long 0xC 31. "OUT2EN,OUT2EN" "0,1" bitfld.long 0xC 30. "TAMPALRM_TYPE,TAMPALRM_TYPE" "0,1" bitfld.long 0xC 29. "TAMPALRM_PU,TAMPALRM_PU" "0,1" bitfld.long 0xC 26. "TAMPOE,TAMPOE" "0,1" bitfld.long 0xC 25. "TAMPTS,TAMPTS" "0,1" bitfld.long 0xC 24. "ITSE,ITSE" "0,1" newline bitfld.long 0xC 23. "COE,COE" "0,1" bitfld.long 0xC 21.--22. "OSEL,OSEL" "0,1,2,3" bitfld.long 0xC 20. "POL,POL" "0,1" bitfld.long 0xC 19. "COSEL,COSEL" "0,1" bitfld.long 0xC 18. "BKP,BKP" "0,1" bitfld.long 0xC 17. "SUB1H,SUB1H" "0,1" newline bitfld.long 0xC 16. "ADD1H,ADD1H" "0,1" bitfld.long 0xC 15. "TSIE,TSIE" "0,1" bitfld.long 0xC 14. "WUTIE,WUTIE" "0,1" bitfld.long 0xC 13. "ALRBIE,ALRBIE" "0,1" bitfld.long 0xC 12. "ALRAIE,ALRAIE" "0,1" bitfld.long 0xC 11. "TSE,TSE" "0,1" newline bitfld.long 0xC 10. "WUTE,WUTE" "0,1" bitfld.long 0xC 9. "ALRBE,ALRBE" "0,1" bitfld.long 0xC 8. "ALRAE,ALRAE" "0,1" bitfld.long 0xC 6. "FMT,FMT" "0,1" bitfld.long 0xC 5. "BYPSHAD,BYPSHAD" "0,1" bitfld.long 0xC 4. "REFCKON,REFCKON" "0,1" newline bitfld.long 0xC 3. "TSEDGE,TSEDGE" "0,1" bitfld.long 0xC 0.--2. "WUCKSEL,WUCKSEL" "0,1,2,3,4,5,6,7" group.long 0x20++0x3 line.long 0x0 "RTC_SMCR,This register can be written only when the APB access is secure." bitfld.long 0x0 15. "DECPROT,DECPROT" "0,1" bitfld.long 0x0 14. "INITDPROT,INITDPROT" "0,1" bitfld.long 0x0 13. "CALDPROT,CALDPROT" "0,1" bitfld.long 0x0 3. "TSDPROT,TSDPROT" "0,1" bitfld.long 0x0 2. "WUTDPROT,WUTDPROT" "0,1" bitfld.long 0x0 1. "ALRBDPROT,ALRBDPROT" "0,1" newline bitfld.long 0x0 0. "ALRADPROT,ALRADPROT" "0,1" wgroup.long 0x24++0x3 line.long 0x0 "RTC_WPR,RTC write protection register" hexmask.long.byte 0x0 0.--7. 1. "KEY,KEY" group.long 0x28++0x3 line.long 0x0 "RTC_CALR,This register is write protected. The write access procedure is described in RTC register write protection on page1830. This register can be write-protected against non-secure access. Refer to Section50.3.4: RTC secure protection modes." bitfld.long 0x0 15. "CALP,CALP" "0,1" bitfld.long 0x0 14. "CALW8,CALW8" "0,1" bitfld.long 0x0 13. "CALW16,CALW16" "0,1" hexmask.long.word 0x0 0.--8. 1. "CALM,CALM" wgroup.long 0x2C++0x3 line.long 0x0 "RTC_SHIFTR,This register is write protected. The write access procedure is described in RTC register write protection on page1830. This register can be protected against non-secure access. Refer to Section50.3.4: RTC secure protection modes." bitfld.long 0x0 31. "ADD1S,ADD1S" "0,1" hexmask.long.word 0x0 0.--14. 1. "SUBFS,SUBFS" rgroup.long 0x30++0xB line.long 0x0 "RTC_TSTR,The content of this register is valid only when TSF is set to 1 in RTC_SR. It is cleared when TSF bit is reset. This register can be protected against non-secure access. Refer to Section50.3.4: RTC secure protection modes." bitfld.long 0x0 22. "PM,PM" "0,1" bitfld.long 0x0 20.--21. "HT,HT" "0,1,2,3" hexmask.long.byte 0x0 16.--19. 1. "HU,HU" bitfld.long 0x0 12.--14. "MNT,MNT" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 8.--11. 1. "MNU,MNU" bitfld.long 0x0 4.--6. "ST,ST" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 0.--3. 1. "SU,SU" line.long 0x4 "RTC_TSDR,The content of this register is valid only when TSF is set to 1 in RTC_SR. It is cleared when TSF bit is reset. This register can be protected against non-secure access. Refer to Section50.3.4: RTC secure protection modes." bitfld.long 0x4 13.--15. "WDU,WDU" "0,1,2,3,4,5,6,7" bitfld.long 0x4 12. "MT,MT" "0,1" hexmask.long.byte 0x4 8.--11. 1. "MU,MU" bitfld.long 0x4 4.--5. "DT,DT" "0,1,2,3" hexmask.long.byte 0x4 0.--3. 1. "DU,DU" line.long 0x8 "RTC_TSSSR,The content of this register is valid only when TSF is set to 1 in RTC_SR. It is cleared when the TSF bit is reset. This register can be protected against non-secure access. Refer to Section50.3.4: RTC secure protection modes." hexmask.long.word 0x8 0.--15. 1. "SS,SS" group.long 0x40++0xF line.long 0x0 "RTC_ALRMAR,This register can be written only when ALRAWF is set to 1 in RTC_ICSR. or in initialization mode. This register is write protected. The write access procedure is described in RTC register write protection on page1830. This register can be.." bitfld.long 0x0 31. "MSK4,MSK4" "0,1" bitfld.long 0x0 30. "WDSEL,WDSEL" "0,1" bitfld.long 0x0 28.--29. "DT,DT" "0,1,2,3" hexmask.long.byte 0x0 24.--27. 1. "DU,DU" bitfld.long 0x0 23. "MSK3,MSK3" "0,1" bitfld.long 0x0 22. "PM,PM" "0,1" newline bitfld.long 0x0 20.--21. "HT,HT" "0,1,2,3" hexmask.long.byte 0x0 16.--19. 1. "HU,HU" bitfld.long 0x0 15. "MSK2,MSK2" "0,1" bitfld.long 0x0 12.--14. "MNT,MNT" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 8.--11. 1. "MNU,MNU" bitfld.long 0x0 7. "MSK1,MSK1" "0,1" newline bitfld.long 0x0 4.--6. "ST,ST" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 0.--3. 1. "SU,SU" line.long 0x4 "RTC_ALRMASSR,This register can be written only when ALRAWF is set to 1 in RTC_ICSR. or in initialization mode. This register is write protected. The write access procedure is described in RTC register write protection on page1830. This register can be.." hexmask.long.byte 0x4 24.--27. 1. "MASKSS,MASKSS" hexmask.long.word 0x4 0.--14. 1. "SS,SS" line.long 0x8 "RTC_ALRMBR,This register can be written only when ALRBWF is set to 1 in RTC_ICSR. or in initialization mode. This register is write protected. The write access procedure is described in RTC register write protection on page1830. This register can be.." bitfld.long 0x8 31. "MSK4,MSK4" "0,1" bitfld.long 0x8 30. "WDSEL,WDSEL" "0,1" bitfld.long 0x8 28.--29. "DT,DT" "0,1,2,3" hexmask.long.byte 0x8 24.--27. 1. "DU,DU" bitfld.long 0x8 23. "MSK3,MSK3" "0,1" bitfld.long 0x8 22. "PM,PM" "0,1" newline bitfld.long 0x8 20.--21. "HT,HT" "0,1,2,3" hexmask.long.byte 0x8 16.--19. 1. "HU,HU" bitfld.long 0x8 15. "MSK2,MSK2" "0,1" bitfld.long 0x8 12.--14. "MNT,MNT" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x8 8.--11. 1. "MNU,MNU" bitfld.long 0x8 7. "MSK1,MSK1" "0,1" newline bitfld.long 0x8 4.--6. "ST,ST" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x8 0.--3. 1. "SU,SU" line.long 0xC "RTC_ALRMBSSR,This register can be written only when ALRBE is reset in RTC_CR register. or in initialization mode. This register is write protected.The write access procedure is described in Section: RTC register write protection. This register can be.." hexmask.long.byte 0xC 24.--27. 1. "MASKSS,MASKSS" hexmask.long.word 0xC 0.--14. 1. "SS,SS" rgroup.long 0x50++0xB line.long 0x0 "RTC_SR,This register can be protected against non-secure access. Refer to Section50.3.4: RTC secure protection modes." bitfld.long 0x0 5. "ITSF,ITSF" "0,1" bitfld.long 0x0 4. "TSOVF,TSOVF" "0,1" bitfld.long 0x0 3. "TSF,TSF" "0,1" bitfld.long 0x0 2. "WUTF,WUTF" "0,1" bitfld.long 0x0 1. "ALRBF,ALRBF" "0,1" bitfld.long 0x0 0. "ALRAF,ALRAF" "0,1" line.long 0x4 "RTC_MISR,RTC non-secure masked interrupt status register" bitfld.long 0x4 5. "ITSMF,ITSMF" "0,1" bitfld.long 0x4 4. "TSOVMF,TSOVMF" "0,1" bitfld.long 0x4 3. "TSMF,TSMF" "0,1" bitfld.long 0x4 2. "WUTMF,WUTMF" "0,1" bitfld.long 0x4 1. "ALRBMF,ALRBMF" "0,1" bitfld.long 0x4 0. "ALRAMF,ALRAMF" "0,1" line.long 0x8 "RTC_SMISR,This register can be protected against non-secure access. Refer to Section50.3.4: RTC secure protection modes." bitfld.long 0x8 5. "ITSMF,ITSMF" "0,1" bitfld.long 0x8 4. "TSOVMF,TSOVMF" "0,1" bitfld.long 0x8 3. "TSMF,TSMF" "0,1" bitfld.long 0x8 2. "WUTMF,WUTMF" "0,1" bitfld.long 0x8 1. "ALRBMF,ALRBMF" "0,1" bitfld.long 0x8 0. "ALRAMF,ALRAMF" "0,1" wgroup.long 0x5C++0x3 line.long 0x0 "RTC_SCR,This register can be protected against non-secure access. Refer to Section50.3.4: RTC secure protection modes." bitfld.long 0x0 5. "CITSF,CITSF" "0,1" bitfld.long 0x0 4. "CTSOVF,CTSOVF" "0,1" bitfld.long 0x0 3. "CTSF,CTSF" "0,1" bitfld.long 0x0 2. "CWUTF,CWUTF" "0,1" bitfld.long 0x0 1. "CALRBF,CALRBF" "0,1" bitfld.long 0x0 0. "CALRAF,CALRAF" "0,1" group.long 0x60++0x3 line.long 0x0 "RTC_CFGR,RTC configuration register" bitfld.long 0x0 1.--2. "LSCOEN,LSCOEN" "0,1,2,3" bitfld.long 0x0 0. "OUT2_RMP,OUT2_RMP" "0,1" rgroup.long 0x3F0++0xF line.long 0x0 "RTC_HWCFGR,RTC hardware configuration register" hexmask.long.byte 0x0 24.--27. 1. "TRUST_ZONE,TRUST_ZONE" hexmask.long.byte 0x0 16.--23. 1. "OPTIONREG_OUT,OPTIONREG_OUT" hexmask.long.byte 0x0 12.--15. 1. "TIMESTAMP,TIMESTAMP" hexmask.long.byte 0x0 8.--11. 1. "SMOOTH_CALIB,SMOOTH_CALIB" hexmask.long.byte 0x0 4.--7. 1. "WAKEUP,WAKEUP" hexmask.long.byte 0x0 0.--3. 1. "ALARMB,ALARMB" line.long 0x4 "RTC_VERR,RTC version register" hexmask.long.byte 0x4 4.--7. 1. "MAJREV,MAJREV" hexmask.long.byte 0x4 0.--3. 1. "MINREV,MINREV" line.long 0x8 "RTC_IPIDR,RTC identification register" hexmask.long 0x8 0.--31. 1. "ID,ID" line.long 0xC "RTC_SIDR,RTC size identification register" hexmask.long 0xC 0.--31. 1. "SID,SID" tree.end sif (cpuis("STM32MP13*")) tree "SAES (Secure AES Coprocessor)" base ad:0x54005000 group.long 0x0++0x3 line.long 0x0 "SAES_CR,SAES control register" bitfld.long 0x0 31. "IPRST,SAES peripheral software reset" "0,1" bitfld.long 0x0 28.--30. "KEYSEL,Key selection" "0: Software key loaded in key registers SAES_KEYx,1: Derived hardware unique key (DHUK),2: Boot hardware key (BHK),?,4: XOR of DHUK and BHK,?,?,7: Test mode key (256-bit hardware constant.." newline bitfld.long 0x0 26.--27. "KSHAREID,Key share identification" "0: CRYP1 peripheral,1: CRYP2 peripheral,?,?" bitfld.long 0x0 24.--25. "KMOD,Key mode selection" "0: Normal key,1: 0] bitfield,2: Shared key,?" newline hexmask.long.byte 0x0 20.--23. 1. "NPBLB,Number of padding bytes in last block" bitfld.long 0x0 19. "KEYPROT,Key protection" "0: When KEYVALID is set and KEYSEL=0 application..,1: When KEYVALID is set key error flag (KEIF) is.." newline bitfld.long 0x0 18. "KEYSIZE,Key size selection" "0: 128,1: 256" bitfld.long 0x0 16. "CHMOD2,Chaining mode selection" "0,1" newline bitfld.long 0x0 13.--14. "GCMPH,GCM or CCM phase selection" "0: Init phase,1: Header phase,2: Payload phase,3: Final phase" bitfld.long 0x0 12. "DMAOUTEN,DMA output enable" "0: Disable,1: Enable" newline bitfld.long 0x0 11. "DMAINEN,DMA input enable" "0: Disable,1: Enable" bitfld.long 0x0 5.--6. "CHMOD1,Chaining mode selection" "0,1,2,3" newline bitfld.long 0x0 3.--4. "MODE,SAES operating mode" "0: Mode 1: encryption,1: Mode 2: key derivation (or key preparation for..,2: Mode 3: decryption,?" bitfld.long 0x0 1.--2. "DATATYPE,Data type selection" "0: None,1: Half-word (16-bit),2: Byte (8-bit),3: Bit" newline bitfld.long 0x0 0. "EN,SAES enable" "0: Disable,1: Enable" rgroup.long 0x4++0x3 line.long 0x0 "SAES_SR,SAES status register" bitfld.long 0x0 7. "KEYVALID,Key Valid flag" "0: No valid key information is available in key..,1: Valid key information defined by KEYSIZE in.." bitfld.long 0x0 3. "BUSY,Busy" "0: Idle,1: Busy" newline bitfld.long 0x0 2. "WRERR,Write error" "0: Not detected,1: Detected" bitfld.long 0x0 1. "RDERR,Read error flag" "0: Not detected,1: Detected" newline bitfld.long 0x0 0. "CCF,Computation completed flag" "0,1" wgroup.long 0x8++0x3 line.long 0x0 "SAES_DINR,SAES data input register" hexmask.long 0x0 0.--31. 1. "DIN,Input data word" rgroup.long 0xC++0x3 line.long 0x0 "SAES_DOUTR,SAES data output register" hexmask.long 0x0 0.--31. 1. "DOUT,Output data word" wgroup.long 0x10++0xF line.long 0x0 "SAES_KEYR0,SAES key register 0" hexmask.long 0x0 0.--31. 1. "KEY,Cryptographic key bits [31:0]" line.long 0x4 "SAES_KEYR1,SAES key register 1" hexmask.long 0x4 0.--31. 1. "KEY,Cryptographic key bits [63:32]" line.long 0x8 "SAES_KEYR2,SAES key register 2" hexmask.long 0x8 0.--31. 1. "KEY,Cryptographic key bits [95:64]" line.long 0xC "SAES_KEYR3,SAES key register 3" hexmask.long 0xC 0.--31. 1. "KEY,Cryptographic key bits [127:96]" group.long 0x20++0xF line.long 0x0 "SAES_IVR0,SAES initialization vector register 0" hexmask.long 0x0 0.--31. 1. "IVI,Initialization vector input bits [31:0]" line.long 0x4 "SAES_IVR1,SAES initialization vector register 1" hexmask.long 0x4 0.--31. 1. "IVI,Initialization vector input bits [63:32]" line.long 0x8 "SAES_IVR2,SAES initialization vector register 2" hexmask.long 0x8 0.--31. 1. "IVI,Initialization vector input bits [95:64]" line.long 0xC "SAES_IVR3,SAES initialization vector register 3" hexmask.long 0xC 0.--31. 1. "IVI,Initialization vector input bits [127:96]" wgroup.long 0x30++0xF line.long 0x0 "SAES_KEYR4,SAES key register 4" hexmask.long 0x0 0.--31. 1. "KEY,Cryptographic key bits [159:128]" line.long 0x4 "SAES_KEYR5,SAES key register 5" hexmask.long 0x4 0.--31. 1. "KEY,Cryptographic key bits [191:160]" line.long 0x8 "SAES_KEYR6,SAES key register 6" hexmask.long 0x8 0.--31. 1. "KEY,Cryptographic key bits [223:192]" line.long 0xC "SAES_KEYR7,SAES key register 7" hexmask.long 0xC 0.--31. 1. "KEY,Cryptographic key bits [255:224]" group.long 0x40++0x1F line.long 0x0 "SAES_SUSP0R,SAES suspend registers" hexmask.long 0x0 0.--31. 1. "SUSP,SAES suspend" line.long 0x4 "SAES_SUSP1R,SAES suspend registers" hexmask.long 0x4 0.--31. 1. "SUSP,SAES suspend" line.long 0x8 "SAES_SUSP2R,SAES suspend registers" hexmask.long 0x8 0.--31. 1. "SUSP,SAES suspend" line.long 0xC "SAES_SUSP3R,SAES suspend registers" hexmask.long 0xC 0.--31. 1. "SUSP,SAES suspend" line.long 0x10 "SAES_SUSP4R,SAES suspend registers" hexmask.long 0x10 0.--31. 1. "SUSP,SAES suspend" line.long 0x14 "SAES_SUSP5R,SAES suspend registers" hexmask.long 0x14 0.--31. 1. "SUSP,SAES suspend" line.long 0x18 "SAES_SUSP6R,SAES suspend registers" hexmask.long 0x18 0.--31. 1. "SUSP,SAES suspend" line.long 0x1C "SAES_SUSP7R,SAES suspend registers" hexmask.long 0x1C 0.--31. 1. "SUSP,SAES suspend" group.long 0x300++0x3 line.long 0x0 "SAES_IER,SAES interrupt enable register" bitfld.long 0x0 3. "RNGEIE,RNG error interrupt enable" "0: Disabled (masked),1: Enabled (not masked)" bitfld.long 0x0 2. "KEIE,Key error interrupt enable" "0: Disabled (masked),1: Enabled (not masked)" newline bitfld.long 0x0 1. "RWEIE,Read or write error interrupt enable" "0: Disabled (masked),1: Enabled (not masked)" bitfld.long 0x0 0. "CCFIE,Computation complete flag interrupt enable" "0: Disabled (masked),1: Enabled (not masked)" rgroup.long 0x304++0x3 line.long 0x0 "SAES_ISR,SAES interrupt status register" bitfld.long 0x0 3. "RNGEIF,RNG error interrupt flag" "0: RNG bus is functional,1: Error detected on RNG bus interface (random seed.." bitfld.long 0x0 2. "KEIF,Key error interrupt flag" "0: No key error detected,1: Key information failed to load into key.." newline bitfld.long 0x0 1. "RWEIF,Read or write error interrupt flag" "0: No read or write error detected,1: Read or write error detected (see SAES_SR.." bitfld.long 0x0 0. "CCF,Computation complete flag" "0: Not completed,1: Completed" wgroup.long 0x308++0x3 line.long 0x0 "SAES_ICR,SAES interrupt clear register" bitfld.long 0x0 3. "RNGEIF,RNG error interrupt flag clear" "0,1" bitfld.long 0x0 2. "KEIF,Key error interrupt flag clear" "0,1" newline bitfld.long 0x0 1. "RWEIF,Read or write error interrupt flag clear" "0,1" bitfld.long 0x0 0. "CCF,Computation complete flag clear" "0,1" rgroup.long 0x3F0++0xF line.long 0x0 "SAES_HWCFGR,SAES hardware configuration register" hexmask.long.byte 0x0 8.--11. 1. "CFG3,HW Generic 3" hexmask.long.byte 0x0 4.--7. 1. "CFG2,HW Generic 2" newline hexmask.long.byte 0x0 0.--3. 1. "CFG1,HW Generic 1" line.long 0x4 "SAES_VERR,SAES version register" hexmask.long.byte 0x4 4.--7. 1. "MAJREV,Major revision" hexmask.long.byte 0x4 0.--3. 1. "MINREV,Minor revision" line.long 0x8 "SAES_IPIDR,SAES identification register" hexmask.long 0x8 0.--31. 1. "ID,Identification code of the peripheral" line.long 0xC "SAES_SIDR,SAES size ID register" hexmask.long 0xC 0.--31. 1. "SID,Size identification code" tree.end endif tree "SAI (Serial Audio Interface)" base ad:0x0 tree "SAI1" base ad:0x4400A000 group.long 0x0++0x17 line.long 0x0 "SAI_GCR,Global configuration register" bitfld.long 0x0 4.--5. "SYNCOUT,SYNCOUT" "0,1,2,3" bitfld.long 0x0 0.--1. "SYNCIN,SYNCIN" "0,1,2,3" line.long 0x4 "SAI_ACR1,Configuration register 1" bitfld.long 0x4 27. "MCKEN,MCKEN" "0,1" bitfld.long 0x4 26. "OSR,OSR" "0,1" hexmask.long.byte 0x4 20.--25. 1. "MCKDIV,MCKDIV" bitfld.long 0x4 19. "NODIV,NODIV" "0,1" bitfld.long 0x4 17. "DMAEN,DMAEN" "0,1" bitfld.long 0x4 16. "SAIEN,SAIEN" "0,1" newline bitfld.long 0x4 13. "OUTDRIV,OUTDRIV" "0,1" bitfld.long 0x4 12. "MONO,MONO" "0,1" bitfld.long 0x4 10.--11. "SYNCEN,SYNCEN" "0,1,2,3" bitfld.long 0x4 9. "CKSTR,CKSTR" "0,1" bitfld.long 0x4 8. "LSBFIRST,LSBFIRST" "0,1" bitfld.long 0x4 5.--7. "DS,DS" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 2.--3. "PRTCFG,PRTCFG" "0,1,2,3" bitfld.long 0x4 0.--1. "MODE,MODE" "0,1,2,3" line.long 0x8 "SAI_ACR2,Configuration register 2" bitfld.long 0x8 14.--15. "COMP,COMP" "0,1,2,3" bitfld.long 0x8 13. "CPL,CPL" "0,1" hexmask.long.byte 0x8 7.--12. 1. "MUTECNT,MUTECNT" bitfld.long 0x8 6. "MUTEVAL,MUTEVAL" "0,1" bitfld.long 0x8 5. "MUTE,MUTE" "0,1" bitfld.long 0x8 4. "TRIS,TRIS" "0,1" newline bitfld.long 0x8 3. "FFLUSH,FFLUSH" "0,1" bitfld.long 0x8 0.--2. "FTH,FTH" "0,1,2,3,4,5,6,7" line.long 0xC "SAI_AFRCR,This register has no meaning in and SPDIF audio protocol" bitfld.long 0xC 18. "FSOFF,FSOFF" "0,1" bitfld.long 0xC 17. "FSPOL,FSPOL" "0,1" rbitfld.long 0xC 16. "FSDEF,FSDEF" "0,1" hexmask.long.byte 0xC 8.--14. 1. "FSALL,FSALL" hexmask.long.byte 0xC 0.--7. 1. "FRL,FRL" line.long 0x10 "SAI_ASLOTR,This register has no meaning in and SPDIF audio protocol" hexmask.long.word 0x10 16.--31. 1. "SLOTEN,SLOTEN" hexmask.long.byte 0x10 8.--11. 1. "NBSLOT,NBSLOT" bitfld.long 0x10 6.--7. "SLOTSZ,SLOTSZ" "0,1,2,3" hexmask.long.byte 0x10 0.--4. 1. "FBOFF,FBOFF" line.long 0x14 "SAI_AIM,Interrupt mask register" bitfld.long 0x14 6. "LFSDETIE,LFSDETIE" "0,1" bitfld.long 0x14 5. "AFSDETIE,AFSDETIE" "0,1" bitfld.long 0x14 4. "CNRDYIE,CNRDYIE" "0,1" bitfld.long 0x14 3. "FREQIE,FREQIE" "0,1" bitfld.long 0x14 2. "WCKCFGIE,WCKCFGIE" "0,1" bitfld.long 0x14 1. "MUTEDETIE,MUTEDETIE" "0,1" newline bitfld.long 0x14 0. "OVRUDRIE,OVRUDRIE" "0,1" rgroup.long 0x18++0x3 line.long 0x0 "SAI_ASR,Status register" bitfld.long 0x0 16.--18. "FLVL,FLVL" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6. "LFSDET,LFSDET" "0,1" bitfld.long 0x0 5. "AFSDET,AFSDET" "0,1" bitfld.long 0x0 4. "CNRDY,CNRDY" "0,1" bitfld.long 0x0 3. "FREQ,FREQ" "0,1" bitfld.long 0x0 2. "WCKCFG,WCKCFG" "0,1" newline bitfld.long 0x0 1. "MUTEDET,MUTEDET" "0,1" bitfld.long 0x0 0. "OVRUDR,OVRUDR" "0,1" wgroup.long 0x1C++0x3 line.long 0x0 "SAI_ACLRFR,Clear flag register" bitfld.long 0x0 6. "CLFSDET,CLFSDET" "0,1" bitfld.long 0x0 5. "CAFSDET,CAFSDET" "0,1" bitfld.long 0x0 4. "CCNRDY,CCNRDY" "0,1" bitfld.long 0x0 2. "CWCKCFG,CWCKCFG" "0,1" bitfld.long 0x0 1. "CMUTEDET,CMUTEDET" "0,1" bitfld.long 0x0 0. "COVRUDR,COVRUDR" "0,1" group.long 0x20++0x17 line.long 0x0 "SAI_ADR,Data register" hexmask.long 0x0 0.--31. 1. "DATA,DATA" line.long 0x4 "SAI_BCR1,Configuration register 1" bitfld.long 0x4 27. "MCKEN,MCKEN" "0,1" bitfld.long 0x4 26. "OSR,OSR" "0,1" hexmask.long.byte 0x4 20.--25. 1. "MCKDIV,MCKDIV" bitfld.long 0x4 19. "NODIV,NODIV" "0,1" bitfld.long 0x4 17. "DMAEN,DMAEN" "0,1" bitfld.long 0x4 16. "SAIEN,SAIEN" "0,1" newline bitfld.long 0x4 13. "OUTDRIV,OUTDRIV" "0,1" bitfld.long 0x4 12. "MONO,MONO" "0,1" bitfld.long 0x4 10.--11. "SYNCEN,SYNCEN" "0,1,2,3" bitfld.long 0x4 9. "CKSTR,CKSTR" "0,1" bitfld.long 0x4 8. "LSBFIRST,LSBFIRST" "0,1" bitfld.long 0x4 5.--7. "DS,DS" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 2.--3. "PRTCFG,PRTCFG" "0,1,2,3" bitfld.long 0x4 0.--1. "MODE,MODE" "0,1,2,3" line.long 0x8 "SAI_BCR2,Configuration register 2" bitfld.long 0x8 14.--15. "COMP,COMP" "0,1,2,3" bitfld.long 0x8 13. "CPL,CPL" "0,1" hexmask.long.byte 0x8 7.--12. 1. "MUTECNT,MUTECNT" bitfld.long 0x8 6. "MUTEVAL,MUTEVAL" "0,1" bitfld.long 0x8 5. "MUTE,MUTE" "0,1" bitfld.long 0x8 4. "TRIS,TRIS" "0,1" newline bitfld.long 0x8 3. "FFLUSH,FFLUSH" "0,1" bitfld.long 0x8 0.--2. "FTH,FTH" "0,1,2,3,4,5,6,7" line.long 0xC "SAI_BFRCR,This register has no meaning in and SPDIF audio protocol" bitfld.long 0xC 18. "FSOFF,FSOFF" "0,1" bitfld.long 0xC 17. "FSPOL,FSPOL" "0,1" rbitfld.long 0xC 16. "FSDEF,FSDEF" "0,1" hexmask.long.byte 0xC 8.--14. 1. "FSALL,FSALL" hexmask.long.byte 0xC 0.--7. 1. "FRL,FRL" line.long 0x10 "SAI_BSLOTR,This register has no meaning in and SPDIF audio protocol" hexmask.long.word 0x10 16.--31. 1. "SLOTEN,SLOTEN" hexmask.long.byte 0x10 8.--11. 1. "NBSLOT,NBSLOT" bitfld.long 0x10 6.--7. "SLOTSZ,SLOTSZ" "0,1,2,3" hexmask.long.byte 0x10 0.--4. 1. "FBOFF,FBOFF" line.long 0x14 "SAI_BIM,Interrupt mask register" bitfld.long 0x14 6. "LFSDETIE,LFSDETIE" "0,1" bitfld.long 0x14 5. "AFSDETIE,AFSDETIE" "0,1" bitfld.long 0x14 4. "CNRDYIE,CNRDYIE" "0,1" bitfld.long 0x14 3. "FREQIE,FREQIE" "0,1" bitfld.long 0x14 2. "WCKCFGIE,WCKCFGIE" "0,1" bitfld.long 0x14 1. "MUTEDETIE,MUTEDETIE" "0,1" newline bitfld.long 0x14 0. "OVRUDRIE,OVRUDRIE" "0,1" rgroup.long 0x38++0x3 line.long 0x0 "SAI_BSR,Status register" bitfld.long 0x0 16.--18. "FLVL,FLVL" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6. "LFSDET,LFSDET" "0,1" bitfld.long 0x0 5. "AFSDET,AFSDET" "0,1" bitfld.long 0x0 4. "CNRDY,CNRDY" "0,1" bitfld.long 0x0 3. "FREQ,FREQ" "0,1" bitfld.long 0x0 2. "WCKCFG,WCKCFG" "0,1" newline bitfld.long 0x0 1. "MUTEDET,MUTEDET" "0,1" bitfld.long 0x0 0. "OVRUDR,OVRUDR" "0,1" wgroup.long 0x3C++0x3 line.long 0x0 "SAI_BCLRFR,Clear flag register" bitfld.long 0x0 6. "CLFSDET,CLFSDET" "0,1" bitfld.long 0x0 5. "CAFSDET,CAFSDET" "0,1" bitfld.long 0x0 4. "CCNRDY,CCNRDY" "0,1" bitfld.long 0x0 2. "CWCKCFG,CWCKCFG" "0,1" bitfld.long 0x0 1. "CMUTEDET,CMUTEDET" "0,1" bitfld.long 0x0 0. "COVRUDR,COVRUDR" "0,1" group.long 0x40++0xB line.long 0x0 "SAI_BDR,Data register" hexmask.long 0x0 0.--31. 1. "DATA,DATA" line.long 0x4 "SAI_PDMCR,PDM control register" bitfld.long 0x4 11. "CKEN4,CKEN4" "0,1" bitfld.long 0x4 10. "CKEN3,CKEN3" "0,1" bitfld.long 0x4 9. "CKEN2,CKEN2" "0,1" bitfld.long 0x4 8. "CKEN1,CKEN1" "0,1" bitfld.long 0x4 4.--5. "MICNBR,MICNBR" "0,1,2,3" bitfld.long 0x4 0. "PDMEN,PDMEN" "0,1" line.long 0x8 "SAI_PDMDLY,PDM delay register" bitfld.long 0x8 28.--30. "DLYM4R,DLYM4R" "0,1,2,3,4,5,6,7" bitfld.long 0x8 24.--26. "DLYM4L,DLYM4L" "0,1,2,3,4,5,6,7" bitfld.long 0x8 20.--22. "DLYM3R,DLYM3R" "0,1,2,3,4,5,6,7" bitfld.long 0x8 16.--18. "DLYM3L,DLYM3L" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "DLYM2R,DLYM2R" "0,1,2,3,4,5,6,7" bitfld.long 0x8 8.--10. "DLYM2L,DLYM2L" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 4.--6. "DLYM1R,DLYM1R" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "DLYM1L,DLYM1L" "0,1,2,3,4,5,6,7" rgroup.long 0x3F0++0xF line.long 0x0 "SAI_HWCFGR,SAI hardware configuration register" hexmask.long.byte 0x0 12.--19. 1. "OPTION_REGOUT,OPTION_REGOUT" hexmask.long.byte 0x0 8.--11. 1. "SPDIF_PDM,SPDIF_PDM" hexmask.long.byte 0x0 0.--7. 1. "FIFO_SIZE,FIFO_SIZE" line.long 0x4 "SAI_VERR,SAI version register" hexmask.long.byte 0x4 4.--7. 1. "MAJREV,MAJREV" hexmask.long.byte 0x4 0.--3. 1. "MINREV,MINREV" line.long 0x8 "SAI_IPIDR,SAI identification register" hexmask.long 0x8 0.--31. 1. "ID,ID" line.long 0xC "SAI_SIDR,SAI size identification register" hexmask.long 0xC 0.--31. 1. "SID,SID" tree.end tree "SAI2" base ad:0x4400B000 group.long 0x0++0x17 line.long 0x0 "SAI_GCR,Global configuration register" bitfld.long 0x0 4.--5. "SYNCOUT,SYNCOUT" "0,1,2,3" bitfld.long 0x0 0.--1. "SYNCIN,SYNCIN" "0,1,2,3" line.long 0x4 "SAI_ACR1,Configuration register 1" bitfld.long 0x4 27. "MCKEN,MCKEN" "0,1" bitfld.long 0x4 26. "OSR,OSR" "0,1" hexmask.long.byte 0x4 20.--25. 1. "MCKDIV,MCKDIV" bitfld.long 0x4 19. "NODIV,NODIV" "0,1" bitfld.long 0x4 17. "DMAEN,DMAEN" "0,1" bitfld.long 0x4 16. "SAIEN,SAIEN" "0,1" newline bitfld.long 0x4 13. "OUTDRIV,OUTDRIV" "0,1" bitfld.long 0x4 12. "MONO,MONO" "0,1" bitfld.long 0x4 10.--11. "SYNCEN,SYNCEN" "0,1,2,3" bitfld.long 0x4 9. "CKSTR,CKSTR" "0,1" bitfld.long 0x4 8. "LSBFIRST,LSBFIRST" "0,1" bitfld.long 0x4 5.--7. "DS,DS" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 2.--3. "PRTCFG,PRTCFG" "0,1,2,3" bitfld.long 0x4 0.--1. "MODE,MODE" "0,1,2,3" line.long 0x8 "SAI_ACR2,Configuration register 2" bitfld.long 0x8 14.--15. "COMP,COMP" "0,1,2,3" bitfld.long 0x8 13. "CPL,CPL" "0,1" hexmask.long.byte 0x8 7.--12. 1. "MUTECNT,MUTECNT" bitfld.long 0x8 6. "MUTEVAL,MUTEVAL" "0,1" bitfld.long 0x8 5. "MUTE,MUTE" "0,1" bitfld.long 0x8 4. "TRIS,TRIS" "0,1" newline bitfld.long 0x8 3. "FFLUSH,FFLUSH" "0,1" bitfld.long 0x8 0.--2. "FTH,FTH" "0,1,2,3,4,5,6,7" line.long 0xC "SAI_AFRCR,This register has no meaning in and SPDIF audio protocol" bitfld.long 0xC 18. "FSOFF,FSOFF" "0,1" bitfld.long 0xC 17. "FSPOL,FSPOL" "0,1" rbitfld.long 0xC 16. "FSDEF,FSDEF" "0,1" hexmask.long.byte 0xC 8.--14. 1. "FSALL,FSALL" hexmask.long.byte 0xC 0.--7. 1. "FRL,FRL" line.long 0x10 "SAI_ASLOTR,This register has no meaning in and SPDIF audio protocol" hexmask.long.word 0x10 16.--31. 1. "SLOTEN,SLOTEN" hexmask.long.byte 0x10 8.--11. 1. "NBSLOT,NBSLOT" bitfld.long 0x10 6.--7. "SLOTSZ,SLOTSZ" "0,1,2,3" hexmask.long.byte 0x10 0.--4. 1. "FBOFF,FBOFF" line.long 0x14 "SAI_AIM,Interrupt mask register" bitfld.long 0x14 6. "LFSDETIE,LFSDETIE" "0,1" bitfld.long 0x14 5. "AFSDETIE,AFSDETIE" "0,1" bitfld.long 0x14 4. "CNRDYIE,CNRDYIE" "0,1" bitfld.long 0x14 3. "FREQIE,FREQIE" "0,1" bitfld.long 0x14 2. "WCKCFGIE,WCKCFGIE" "0,1" bitfld.long 0x14 1. "MUTEDETIE,MUTEDETIE" "0,1" newline bitfld.long 0x14 0. "OVRUDRIE,OVRUDRIE" "0,1" rgroup.long 0x18++0x3 line.long 0x0 "SAI_ASR,Status register" bitfld.long 0x0 16.--18. "FLVL,FLVL" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6. "LFSDET,LFSDET" "0,1" bitfld.long 0x0 5. "AFSDET,AFSDET" "0,1" bitfld.long 0x0 4. "CNRDY,CNRDY" "0,1" bitfld.long 0x0 3. "FREQ,FREQ" "0,1" bitfld.long 0x0 2. "WCKCFG,WCKCFG" "0,1" newline bitfld.long 0x0 1. "MUTEDET,MUTEDET" "0,1" bitfld.long 0x0 0. "OVRUDR,OVRUDR" "0,1" wgroup.long 0x1C++0x3 line.long 0x0 "SAI_ACLRFR,Clear flag register" bitfld.long 0x0 6. "CLFSDET,CLFSDET" "0,1" bitfld.long 0x0 5. "CAFSDET,CAFSDET" "0,1" bitfld.long 0x0 4. "CCNRDY,CCNRDY" "0,1" bitfld.long 0x0 2. "CWCKCFG,CWCKCFG" "0,1" bitfld.long 0x0 1. "CMUTEDET,CMUTEDET" "0,1" bitfld.long 0x0 0. "COVRUDR,COVRUDR" "0,1" group.long 0x20++0x17 line.long 0x0 "SAI_ADR,Data register" hexmask.long 0x0 0.--31. 1. "DATA,DATA" line.long 0x4 "SAI_BCR1,Configuration register 1" bitfld.long 0x4 27. "MCKEN,MCKEN" "0,1" bitfld.long 0x4 26. "OSR,OSR" "0,1" hexmask.long.byte 0x4 20.--25. 1. "MCKDIV,MCKDIV" bitfld.long 0x4 19. "NODIV,NODIV" "0,1" bitfld.long 0x4 17. "DMAEN,DMAEN" "0,1" bitfld.long 0x4 16. "SAIEN,SAIEN" "0,1" newline bitfld.long 0x4 13. "OUTDRIV,OUTDRIV" "0,1" bitfld.long 0x4 12. "MONO,MONO" "0,1" bitfld.long 0x4 10.--11. "SYNCEN,SYNCEN" "0,1,2,3" bitfld.long 0x4 9. "CKSTR,CKSTR" "0,1" bitfld.long 0x4 8. "LSBFIRST,LSBFIRST" "0,1" bitfld.long 0x4 5.--7. "DS,DS" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 2.--3. "PRTCFG,PRTCFG" "0,1,2,3" bitfld.long 0x4 0.--1. "MODE,MODE" "0,1,2,3" line.long 0x8 "SAI_BCR2,Configuration register 2" bitfld.long 0x8 14.--15. "COMP,COMP" "0,1,2,3" bitfld.long 0x8 13. "CPL,CPL" "0,1" hexmask.long.byte 0x8 7.--12. 1. "MUTECNT,MUTECNT" bitfld.long 0x8 6. "MUTEVAL,MUTEVAL" "0,1" bitfld.long 0x8 5. "MUTE,MUTE" "0,1" bitfld.long 0x8 4. "TRIS,TRIS" "0,1" newline bitfld.long 0x8 3. "FFLUSH,FFLUSH" "0,1" bitfld.long 0x8 0.--2. "FTH,FTH" "0,1,2,3,4,5,6,7" line.long 0xC "SAI_BFRCR,This register has no meaning in and SPDIF audio protocol" bitfld.long 0xC 18. "FSOFF,FSOFF" "0,1" bitfld.long 0xC 17. "FSPOL,FSPOL" "0,1" rbitfld.long 0xC 16. "FSDEF,FSDEF" "0,1" hexmask.long.byte 0xC 8.--14. 1. "FSALL,FSALL" hexmask.long.byte 0xC 0.--7. 1. "FRL,FRL" line.long 0x10 "SAI_BSLOTR,This register has no meaning in and SPDIF audio protocol" hexmask.long.word 0x10 16.--31. 1. "SLOTEN,SLOTEN" hexmask.long.byte 0x10 8.--11. 1. "NBSLOT,NBSLOT" bitfld.long 0x10 6.--7. "SLOTSZ,SLOTSZ" "0,1,2,3" hexmask.long.byte 0x10 0.--4. 1. "FBOFF,FBOFF" line.long 0x14 "SAI_BIM,Interrupt mask register" bitfld.long 0x14 6. "LFSDETIE,LFSDETIE" "0,1" bitfld.long 0x14 5. "AFSDETIE,AFSDETIE" "0,1" bitfld.long 0x14 4. "CNRDYIE,CNRDYIE" "0,1" bitfld.long 0x14 3. "FREQIE,FREQIE" "0,1" bitfld.long 0x14 2. "WCKCFGIE,WCKCFGIE" "0,1" bitfld.long 0x14 1. "MUTEDETIE,MUTEDETIE" "0,1" newline bitfld.long 0x14 0. "OVRUDRIE,OVRUDRIE" "0,1" rgroup.long 0x38++0x3 line.long 0x0 "SAI_BSR,Status register" bitfld.long 0x0 16.--18. "FLVL,FLVL" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6. "LFSDET,LFSDET" "0,1" bitfld.long 0x0 5. "AFSDET,AFSDET" "0,1" bitfld.long 0x0 4. "CNRDY,CNRDY" "0,1" bitfld.long 0x0 3. "FREQ,FREQ" "0,1" bitfld.long 0x0 2. "WCKCFG,WCKCFG" "0,1" newline bitfld.long 0x0 1. "MUTEDET,MUTEDET" "0,1" bitfld.long 0x0 0. "OVRUDR,OVRUDR" "0,1" wgroup.long 0x3C++0x3 line.long 0x0 "SAI_BCLRFR,Clear flag register" bitfld.long 0x0 6. "CLFSDET,CLFSDET" "0,1" bitfld.long 0x0 5. "CAFSDET,CAFSDET" "0,1" bitfld.long 0x0 4. "CCNRDY,CCNRDY" "0,1" bitfld.long 0x0 2. "CWCKCFG,CWCKCFG" "0,1" bitfld.long 0x0 1. "CMUTEDET,CMUTEDET" "0,1" bitfld.long 0x0 0. "COVRUDR,COVRUDR" "0,1" group.long 0x40++0xB line.long 0x0 "SAI_BDR,Data register" hexmask.long 0x0 0.--31. 1. "DATA,DATA" line.long 0x4 "SAI_PDMCR,PDM control register" bitfld.long 0x4 11. "CKEN4,CKEN4" "0,1" bitfld.long 0x4 10. "CKEN3,CKEN3" "0,1" bitfld.long 0x4 9. "CKEN2,CKEN2" "0,1" bitfld.long 0x4 8. "CKEN1,CKEN1" "0,1" bitfld.long 0x4 4.--5. "MICNBR,MICNBR" "0,1,2,3" bitfld.long 0x4 0. "PDMEN,PDMEN" "0,1" line.long 0x8 "SAI_PDMDLY,PDM delay register" bitfld.long 0x8 28.--30. "DLYM4R,DLYM4R" "0,1,2,3,4,5,6,7" bitfld.long 0x8 24.--26. "DLYM4L,DLYM4L" "0,1,2,3,4,5,6,7" bitfld.long 0x8 20.--22. "DLYM3R,DLYM3R" "0,1,2,3,4,5,6,7" bitfld.long 0x8 16.--18. "DLYM3L,DLYM3L" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "DLYM2R,DLYM2R" "0,1,2,3,4,5,6,7" bitfld.long 0x8 8.--10. "DLYM2L,DLYM2L" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 4.--6. "DLYM1R,DLYM1R" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "DLYM1L,DLYM1L" "0,1,2,3,4,5,6,7" rgroup.long 0x3F0++0xF line.long 0x0 "SAI_HWCFGR,SAI hardware configuration register" hexmask.long.byte 0x0 12.--19. 1. "OPTION_REGOUT,OPTION_REGOUT" hexmask.long.byte 0x0 8.--11. 1. "SPDIF_PDM,SPDIF_PDM" hexmask.long.byte 0x0 0.--7. 1. "FIFO_SIZE,FIFO_SIZE" line.long 0x4 "SAI_VERR,SAI version register" hexmask.long.byte 0x4 4.--7. 1. "MAJREV,MAJREV" hexmask.long.byte 0x4 0.--3. 1. "MINREV,MINREV" line.long 0x8 "SAI_IPIDR,SAI identification register" hexmask.long 0x8 0.--31. 1. "ID,ID" line.long 0xC "SAI_SIDR,SAI size identification register" hexmask.long 0xC 0.--31. 1. "SID,SID" tree.end sif (cpuis("STM32MP151*")) tree "SAI3" base ad:0x4400C000 group.long 0x0++0x17 line.long 0x0 "SAI_GCR,Global configuration register" bitfld.long 0x0 4.--5. "SYNCOUT,SYNCOUT" "0,1,2,3" bitfld.long 0x0 0.--1. "SYNCIN,SYNCIN" "0,1,2,3" line.long 0x4 "SAI_ACR1,Configuration register 1" bitfld.long 0x4 27. "MCKEN,MCKEN" "0,1" bitfld.long 0x4 26. "OSR,OSR" "0,1" hexmask.long.byte 0x4 20.--25. 1. "MCKDIV,MCKDIV" bitfld.long 0x4 19. "NODIV,NODIV" "0,1" bitfld.long 0x4 17. "DMAEN,DMAEN" "0,1" bitfld.long 0x4 16. "SAIEN,SAIEN" "0,1" newline bitfld.long 0x4 13. "OUTDRIV,OUTDRIV" "0,1" bitfld.long 0x4 12. "MONO,MONO" "0,1" bitfld.long 0x4 10.--11. "SYNCEN,SYNCEN" "0,1,2,3" bitfld.long 0x4 9. "CKSTR,CKSTR" "0,1" bitfld.long 0x4 8. "LSBFIRST,LSBFIRST" "0,1" bitfld.long 0x4 5.--7. "DS,DS" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 2.--3. "PRTCFG,PRTCFG" "0,1,2,3" bitfld.long 0x4 0.--1. "MODE,MODE" "0,1,2,3" line.long 0x8 "SAI_ACR2,Configuration register 2" bitfld.long 0x8 14.--15. "COMP,COMP" "0,1,2,3" bitfld.long 0x8 13. "CPL,CPL" "0,1" hexmask.long.byte 0x8 7.--12. 1. "MUTECNT,MUTECNT" bitfld.long 0x8 6. "MUTEVAL,MUTEVAL" "0,1" bitfld.long 0x8 5. "MUTE,MUTE" "0,1" bitfld.long 0x8 4. "TRIS,TRIS" "0,1" newline bitfld.long 0x8 3. "FFLUSH,FFLUSH" "0,1" bitfld.long 0x8 0.--2. "FTH,FTH" "0,1,2,3,4,5,6,7" line.long 0xC "SAI_AFRCR,This register has no meaning in and SPDIF audio protocol" bitfld.long 0xC 18. "FSOFF,FSOFF" "0,1" bitfld.long 0xC 17. "FSPOL,FSPOL" "0,1" rbitfld.long 0xC 16. "FSDEF,FSDEF" "0,1" hexmask.long.byte 0xC 8.--14. 1. "FSALL,FSALL" hexmask.long.byte 0xC 0.--7. 1. "FRL,FRL" line.long 0x10 "SAI_ASLOTR,This register has no meaning in and SPDIF audio protocol" hexmask.long.word 0x10 16.--31. 1. "SLOTEN,SLOTEN" hexmask.long.byte 0x10 8.--11. 1. "NBSLOT,NBSLOT" bitfld.long 0x10 6.--7. "SLOTSZ,SLOTSZ" "0,1,2,3" hexmask.long.byte 0x10 0.--4. 1. "FBOFF,FBOFF" line.long 0x14 "SAI_AIM,Interrupt mask register" bitfld.long 0x14 6. "LFSDETIE,LFSDETIE" "0,1" bitfld.long 0x14 5. "AFSDETIE,AFSDETIE" "0,1" bitfld.long 0x14 4. "CNRDYIE,CNRDYIE" "0,1" bitfld.long 0x14 3. "FREQIE,FREQIE" "0,1" bitfld.long 0x14 2. "WCKCFGIE,WCKCFGIE" "0,1" bitfld.long 0x14 1. "MUTEDETIE,MUTEDETIE" "0,1" newline bitfld.long 0x14 0. "OVRUDRIE,OVRUDRIE" "0,1" rgroup.long 0x18++0x3 line.long 0x0 "SAI_ASR,Status register" bitfld.long 0x0 16.--18. "FLVL,FLVL" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6. "LFSDET,LFSDET" "0,1" bitfld.long 0x0 5. "AFSDET,AFSDET" "0,1" bitfld.long 0x0 4. "CNRDY,CNRDY" "0,1" bitfld.long 0x0 3. "FREQ,FREQ" "0,1" bitfld.long 0x0 2. "WCKCFG,WCKCFG" "0,1" newline bitfld.long 0x0 1. "MUTEDET,MUTEDET" "0,1" bitfld.long 0x0 0. "OVRUDR,OVRUDR" "0,1" wgroup.long 0x1C++0x3 line.long 0x0 "SAI_ACLRFR,Clear flag register" bitfld.long 0x0 6. "CLFSDET,CLFSDET" "0,1" bitfld.long 0x0 5. "CAFSDET,CAFSDET" "0,1" bitfld.long 0x0 4. "CCNRDY,CCNRDY" "0,1" bitfld.long 0x0 2. "CWCKCFG,CWCKCFG" "0,1" bitfld.long 0x0 1. "CMUTEDET,CMUTEDET" "0,1" bitfld.long 0x0 0. "COVRUDR,COVRUDR" "0,1" group.long 0x20++0x17 line.long 0x0 "SAI_ADR,Data register" hexmask.long 0x0 0.--31. 1. "DATA,DATA" line.long 0x4 "SAI_BCR1,Configuration register 1" bitfld.long 0x4 27. "MCKEN,MCKEN" "0,1" bitfld.long 0x4 26. "OSR,OSR" "0,1" hexmask.long.byte 0x4 20.--25. 1. "MCKDIV,MCKDIV" bitfld.long 0x4 19. "NODIV,NODIV" "0,1" bitfld.long 0x4 17. "DMAEN,DMAEN" "0,1" bitfld.long 0x4 16. "SAIEN,SAIEN" "0,1" newline bitfld.long 0x4 13. "OUTDRIV,OUTDRIV" "0,1" bitfld.long 0x4 12. "MONO,MONO" "0,1" bitfld.long 0x4 10.--11. "SYNCEN,SYNCEN" "0,1,2,3" bitfld.long 0x4 9. "CKSTR,CKSTR" "0,1" bitfld.long 0x4 8. "LSBFIRST,LSBFIRST" "0,1" bitfld.long 0x4 5.--7. "DS,DS" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 2.--3. "PRTCFG,PRTCFG" "0,1,2,3" bitfld.long 0x4 0.--1. "MODE,MODE" "0,1,2,3" line.long 0x8 "SAI_BCR2,Configuration register 2" bitfld.long 0x8 14.--15. "COMP,COMP" "0,1,2,3" bitfld.long 0x8 13. "CPL,CPL" "0,1" hexmask.long.byte 0x8 7.--12. 1. "MUTECNT,MUTECNT" bitfld.long 0x8 6. "MUTEVAL,MUTEVAL" "0,1" bitfld.long 0x8 5. "MUTE,MUTE" "0,1" bitfld.long 0x8 4. "TRIS,TRIS" "0,1" newline bitfld.long 0x8 3. "FFLUSH,FFLUSH" "0,1" bitfld.long 0x8 0.--2. "FTH,FTH" "0,1,2,3,4,5,6,7" line.long 0xC "SAI_BFRCR,This register has no meaning in and SPDIF audio protocol" bitfld.long 0xC 18. "FSOFF,FSOFF" "0,1" bitfld.long 0xC 17. "FSPOL,FSPOL" "0,1" rbitfld.long 0xC 16. "FSDEF,FSDEF" "0,1" hexmask.long.byte 0xC 8.--14. 1. "FSALL,FSALL" hexmask.long.byte 0xC 0.--7. 1. "FRL,FRL" line.long 0x10 "SAI_BSLOTR,This register has no meaning in and SPDIF audio protocol" hexmask.long.word 0x10 16.--31. 1. "SLOTEN,SLOTEN" hexmask.long.byte 0x10 8.--11. 1. "NBSLOT,NBSLOT" bitfld.long 0x10 6.--7. "SLOTSZ,SLOTSZ" "0,1,2,3" hexmask.long.byte 0x10 0.--4. 1. "FBOFF,FBOFF" line.long 0x14 "SAI_BIM,Interrupt mask register" bitfld.long 0x14 6. "LFSDETIE,LFSDETIE" "0,1" bitfld.long 0x14 5. "AFSDETIE,AFSDETIE" "0,1" bitfld.long 0x14 4. "CNRDYIE,CNRDYIE" "0,1" bitfld.long 0x14 3. "FREQIE,FREQIE" "0,1" bitfld.long 0x14 2. "WCKCFGIE,WCKCFGIE" "0,1" bitfld.long 0x14 1. "MUTEDETIE,MUTEDETIE" "0,1" newline bitfld.long 0x14 0. "OVRUDRIE,OVRUDRIE" "0,1" rgroup.long 0x38++0x3 line.long 0x0 "SAI_BSR,Status register" bitfld.long 0x0 16.--18. "FLVL,FLVL" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6. "LFSDET,LFSDET" "0,1" bitfld.long 0x0 5. "AFSDET,AFSDET" "0,1" bitfld.long 0x0 4. "CNRDY,CNRDY" "0,1" bitfld.long 0x0 3. "FREQ,FREQ" "0,1" bitfld.long 0x0 2. "WCKCFG,WCKCFG" "0,1" newline bitfld.long 0x0 1. "MUTEDET,MUTEDET" "0,1" bitfld.long 0x0 0. "OVRUDR,OVRUDR" "0,1" wgroup.long 0x3C++0x3 line.long 0x0 "SAI_BCLRFR,Clear flag register" bitfld.long 0x0 6. "CLFSDET,CLFSDET" "0,1" bitfld.long 0x0 5. "CAFSDET,CAFSDET" "0,1" bitfld.long 0x0 4. "CCNRDY,CCNRDY" "0,1" bitfld.long 0x0 2. "CWCKCFG,CWCKCFG" "0,1" bitfld.long 0x0 1. "CMUTEDET,CMUTEDET" "0,1" bitfld.long 0x0 0. "COVRUDR,COVRUDR" "0,1" group.long 0x40++0xB line.long 0x0 "SAI_BDR,Data register" hexmask.long 0x0 0.--31. 1. "DATA,DATA" line.long 0x4 "SAI_PDMCR,PDM control register" bitfld.long 0x4 11. "CKEN4,CKEN4" "0,1" bitfld.long 0x4 10. "CKEN3,CKEN3" "0,1" bitfld.long 0x4 9. "CKEN2,CKEN2" "0,1" bitfld.long 0x4 8. "CKEN1,CKEN1" "0,1" bitfld.long 0x4 4.--5. "MICNBR,MICNBR" "0,1,2,3" bitfld.long 0x4 0. "PDMEN,PDMEN" "0,1" line.long 0x8 "SAI_PDMDLY,PDM delay register" bitfld.long 0x8 28.--30. "DLYM4R,DLYM4R" "0,1,2,3,4,5,6,7" bitfld.long 0x8 24.--26. "DLYM4L,DLYM4L" "0,1,2,3,4,5,6,7" bitfld.long 0x8 20.--22. "DLYM3R,DLYM3R" "0,1,2,3,4,5,6,7" bitfld.long 0x8 16.--18. "DLYM3L,DLYM3L" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "DLYM2R,DLYM2R" "0,1,2,3,4,5,6,7" bitfld.long 0x8 8.--10. "DLYM2L,DLYM2L" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 4.--6. "DLYM1R,DLYM1R" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "DLYM1L,DLYM1L" "0,1,2,3,4,5,6,7" rgroup.long 0x3F0++0xF line.long 0x0 "SAI_HWCFGR,SAI hardware configuration register" hexmask.long.byte 0x0 12.--19. 1. "OPTION_REGOUT,OPTION_REGOUT" hexmask.long.byte 0x0 8.--11. 1. "SPDIF_PDM,SPDIF_PDM" hexmask.long.byte 0x0 0.--7. 1. "FIFO_SIZE,FIFO_SIZE" line.long 0x4 "SAI_VERR,SAI version register" hexmask.long.byte 0x4 4.--7. 1. "MAJREV,MAJREV" hexmask.long.byte 0x4 0.--3. 1. "MINREV,MINREV" line.long 0x8 "SAI_IPIDR,SAI identification register" hexmask.long 0x8 0.--31. 1. "ID,ID" line.long 0xC "SAI_SIDR,SAI size identification register" hexmask.long 0xC 0.--31. 1. "SID,SID" tree.end tree "SAI4" base ad:0x50027000 group.long 0x0++0x17 line.long 0x0 "SAI_GCR,Global configuration register" bitfld.long 0x0 4.--5. "SYNCOUT,SYNCOUT" "0,1,2,3" bitfld.long 0x0 0.--1. "SYNCIN,SYNCIN" "0,1,2,3" line.long 0x4 "SAI_ACR1,Configuration register 1" bitfld.long 0x4 27. "MCKEN,MCKEN" "0,1" bitfld.long 0x4 26. "OSR,OSR" "0,1" hexmask.long.byte 0x4 20.--25. 1. "MCKDIV,MCKDIV" bitfld.long 0x4 19. "NODIV,NODIV" "0,1" bitfld.long 0x4 17. "DMAEN,DMAEN" "0,1" bitfld.long 0x4 16. "SAIEN,SAIEN" "0,1" newline bitfld.long 0x4 13. "OUTDRIV,OUTDRIV" "0,1" bitfld.long 0x4 12. "MONO,MONO" "0,1" bitfld.long 0x4 10.--11. "SYNCEN,SYNCEN" "0,1,2,3" bitfld.long 0x4 9. "CKSTR,CKSTR" "0,1" bitfld.long 0x4 8. "LSBFIRST,LSBFIRST" "0,1" bitfld.long 0x4 5.--7. "DS,DS" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 2.--3. "PRTCFG,PRTCFG" "0,1,2,3" bitfld.long 0x4 0.--1. "MODE,MODE" "0,1,2,3" line.long 0x8 "SAI_ACR2,Configuration register 2" bitfld.long 0x8 14.--15. "COMP,COMP" "0,1,2,3" bitfld.long 0x8 13. "CPL,CPL" "0,1" hexmask.long.byte 0x8 7.--12. 1. "MUTECNT,MUTECNT" bitfld.long 0x8 6. "MUTEVAL,MUTEVAL" "0,1" bitfld.long 0x8 5. "MUTE,MUTE" "0,1" bitfld.long 0x8 4. "TRIS,TRIS" "0,1" newline bitfld.long 0x8 3. "FFLUSH,FFLUSH" "0,1" bitfld.long 0x8 0.--2. "FTH,FTH" "0,1,2,3,4,5,6,7" line.long 0xC "SAI_AFRCR,This register has no meaning in and SPDIF audio protocol" bitfld.long 0xC 18. "FSOFF,FSOFF" "0,1" bitfld.long 0xC 17. "FSPOL,FSPOL" "0,1" rbitfld.long 0xC 16. "FSDEF,FSDEF" "0,1" hexmask.long.byte 0xC 8.--14. 1. "FSALL,FSALL" hexmask.long.byte 0xC 0.--7. 1. "FRL,FRL" line.long 0x10 "SAI_ASLOTR,This register has no meaning in and SPDIF audio protocol" hexmask.long.word 0x10 16.--31. 1. "SLOTEN,SLOTEN" hexmask.long.byte 0x10 8.--11. 1. "NBSLOT,NBSLOT" bitfld.long 0x10 6.--7. "SLOTSZ,SLOTSZ" "0,1,2,3" hexmask.long.byte 0x10 0.--4. 1. "FBOFF,FBOFF" line.long 0x14 "SAI_AIM,Interrupt mask register" bitfld.long 0x14 6. "LFSDETIE,LFSDETIE" "0,1" bitfld.long 0x14 5. "AFSDETIE,AFSDETIE" "0,1" bitfld.long 0x14 4. "CNRDYIE,CNRDYIE" "0,1" bitfld.long 0x14 3. "FREQIE,FREQIE" "0,1" bitfld.long 0x14 2. "WCKCFGIE,WCKCFGIE" "0,1" bitfld.long 0x14 1. "MUTEDETIE,MUTEDETIE" "0,1" newline bitfld.long 0x14 0. "OVRUDRIE,OVRUDRIE" "0,1" rgroup.long 0x18++0x3 line.long 0x0 "SAI_ASR,Status register" bitfld.long 0x0 16.--18. "FLVL,FLVL" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6. "LFSDET,LFSDET" "0,1" bitfld.long 0x0 5. "AFSDET,AFSDET" "0,1" bitfld.long 0x0 4. "CNRDY,CNRDY" "0,1" bitfld.long 0x0 3. "FREQ,FREQ" "0,1" bitfld.long 0x0 2. "WCKCFG,WCKCFG" "0,1" newline bitfld.long 0x0 1. "MUTEDET,MUTEDET" "0,1" bitfld.long 0x0 0. "OVRUDR,OVRUDR" "0,1" wgroup.long 0x1C++0x3 line.long 0x0 "SAI_ACLRFR,Clear flag register" bitfld.long 0x0 6. "CLFSDET,CLFSDET" "0,1" bitfld.long 0x0 5. "CAFSDET,CAFSDET" "0,1" bitfld.long 0x0 4. "CCNRDY,CCNRDY" "0,1" bitfld.long 0x0 2. "CWCKCFG,CWCKCFG" "0,1" bitfld.long 0x0 1. "CMUTEDET,CMUTEDET" "0,1" bitfld.long 0x0 0. "COVRUDR,COVRUDR" "0,1" group.long 0x20++0x17 line.long 0x0 "SAI_ADR,Data register" hexmask.long 0x0 0.--31. 1. "DATA,DATA" line.long 0x4 "SAI_BCR1,Configuration register 1" bitfld.long 0x4 27. "MCKEN,MCKEN" "0,1" bitfld.long 0x4 26. "OSR,OSR" "0,1" hexmask.long.byte 0x4 20.--25. 1. "MCKDIV,MCKDIV" bitfld.long 0x4 19. "NODIV,NODIV" "0,1" bitfld.long 0x4 17. "DMAEN,DMAEN" "0,1" bitfld.long 0x4 16. "SAIEN,SAIEN" "0,1" newline bitfld.long 0x4 13. "OUTDRIV,OUTDRIV" "0,1" bitfld.long 0x4 12. "MONO,MONO" "0,1" bitfld.long 0x4 10.--11. "SYNCEN,SYNCEN" "0,1,2,3" bitfld.long 0x4 9. "CKSTR,CKSTR" "0,1" bitfld.long 0x4 8. "LSBFIRST,LSBFIRST" "0,1" bitfld.long 0x4 5.--7. "DS,DS" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 2.--3. "PRTCFG,PRTCFG" "0,1,2,3" bitfld.long 0x4 0.--1. "MODE,MODE" "0,1,2,3" line.long 0x8 "SAI_BCR2,Configuration register 2" bitfld.long 0x8 14.--15. "COMP,COMP" "0,1,2,3" bitfld.long 0x8 13. "CPL,CPL" "0,1" hexmask.long.byte 0x8 7.--12. 1. "MUTECNT,MUTECNT" bitfld.long 0x8 6. "MUTEVAL,MUTEVAL" "0,1" bitfld.long 0x8 5. "MUTE,MUTE" "0,1" bitfld.long 0x8 4. "TRIS,TRIS" "0,1" newline bitfld.long 0x8 3. "FFLUSH,FFLUSH" "0,1" bitfld.long 0x8 0.--2. "FTH,FTH" "0,1,2,3,4,5,6,7" line.long 0xC "SAI_BFRCR,This register has no meaning in and SPDIF audio protocol" bitfld.long 0xC 18. "FSOFF,FSOFF" "0,1" bitfld.long 0xC 17. "FSPOL,FSPOL" "0,1" rbitfld.long 0xC 16. "FSDEF,FSDEF" "0,1" hexmask.long.byte 0xC 8.--14. 1. "FSALL,FSALL" hexmask.long.byte 0xC 0.--7. 1. "FRL,FRL" line.long 0x10 "SAI_BSLOTR,This register has no meaning in and SPDIF audio protocol" hexmask.long.word 0x10 16.--31. 1. "SLOTEN,SLOTEN" hexmask.long.byte 0x10 8.--11. 1. "NBSLOT,NBSLOT" bitfld.long 0x10 6.--7. "SLOTSZ,SLOTSZ" "0,1,2,3" hexmask.long.byte 0x10 0.--4. 1. "FBOFF,FBOFF" line.long 0x14 "SAI_BIM,Interrupt mask register" bitfld.long 0x14 6. "LFSDETIE,LFSDETIE" "0,1" bitfld.long 0x14 5. "AFSDETIE,AFSDETIE" "0,1" bitfld.long 0x14 4. "CNRDYIE,CNRDYIE" "0,1" bitfld.long 0x14 3. "FREQIE,FREQIE" "0,1" bitfld.long 0x14 2. "WCKCFGIE,WCKCFGIE" "0,1" bitfld.long 0x14 1. "MUTEDETIE,MUTEDETIE" "0,1" newline bitfld.long 0x14 0. "OVRUDRIE,OVRUDRIE" "0,1" rgroup.long 0x38++0x3 line.long 0x0 "SAI_BSR,Status register" bitfld.long 0x0 16.--18. "FLVL,FLVL" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6. "LFSDET,LFSDET" "0,1" bitfld.long 0x0 5. "AFSDET,AFSDET" "0,1" bitfld.long 0x0 4. "CNRDY,CNRDY" "0,1" bitfld.long 0x0 3. "FREQ,FREQ" "0,1" bitfld.long 0x0 2. "WCKCFG,WCKCFG" "0,1" newline bitfld.long 0x0 1. "MUTEDET,MUTEDET" "0,1" bitfld.long 0x0 0. "OVRUDR,OVRUDR" "0,1" wgroup.long 0x3C++0x3 line.long 0x0 "SAI_BCLRFR,Clear flag register" bitfld.long 0x0 6. "CLFSDET,CLFSDET" "0,1" bitfld.long 0x0 5. "CAFSDET,CAFSDET" "0,1" bitfld.long 0x0 4. "CCNRDY,CCNRDY" "0,1" bitfld.long 0x0 2. "CWCKCFG,CWCKCFG" "0,1" bitfld.long 0x0 1. "CMUTEDET,CMUTEDET" "0,1" bitfld.long 0x0 0. "COVRUDR,COVRUDR" "0,1" group.long 0x40++0xB line.long 0x0 "SAI_BDR,Data register" hexmask.long 0x0 0.--31. 1. "DATA,DATA" line.long 0x4 "SAI_PDMCR,PDM control register" bitfld.long 0x4 11. "CKEN4,CKEN4" "0,1" bitfld.long 0x4 10. "CKEN3,CKEN3" "0,1" bitfld.long 0x4 9. "CKEN2,CKEN2" "0,1" bitfld.long 0x4 8. "CKEN1,CKEN1" "0,1" bitfld.long 0x4 4.--5. "MICNBR,MICNBR" "0,1,2,3" bitfld.long 0x4 0. "PDMEN,PDMEN" "0,1" line.long 0x8 "SAI_PDMDLY,PDM delay register" bitfld.long 0x8 28.--30. "DLYM4R,DLYM4R" "0,1,2,3,4,5,6,7" bitfld.long 0x8 24.--26. "DLYM4L,DLYM4L" "0,1,2,3,4,5,6,7" bitfld.long 0x8 20.--22. "DLYM3R,DLYM3R" "0,1,2,3,4,5,6,7" bitfld.long 0x8 16.--18. "DLYM3L,DLYM3L" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "DLYM2R,DLYM2R" "0,1,2,3,4,5,6,7" bitfld.long 0x8 8.--10. "DLYM2L,DLYM2L" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 4.--6. "DLYM1R,DLYM1R" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "DLYM1L,DLYM1L" "0,1,2,3,4,5,6,7" rgroup.long 0x3F0++0xF line.long 0x0 "SAI_HWCFGR,SAI hardware configuration register" hexmask.long.byte 0x0 12.--19. 1. "OPTION_REGOUT,OPTION_REGOUT" hexmask.long.byte 0x0 8.--11. 1. "SPDIF_PDM,SPDIF_PDM" hexmask.long.byte 0x0 0.--7. 1. "FIFO_SIZE,FIFO_SIZE" line.long 0x4 "SAI_VERR,SAI version register" hexmask.long.byte 0x4 4.--7. 1. "MAJREV,MAJREV" hexmask.long.byte 0x4 0.--3. 1. "MINREV,MINREV" line.long 0x8 "SAI_IPIDR,SAI identification register" hexmask.long 0x8 0.--31. 1. "ID,ID" line.long 0xC "SAI_SIDR,SAI size identification register" hexmask.long 0xC 0.--31. 1. "SID,SID" tree.end endif sif (cpuis("STM32MP153*")) tree "SAI3" base ad:0x4400C000 group.long 0x0++0x17 line.long 0x0 "SAI_GCR,Global configuration register" bitfld.long 0x0 4.--5. "SYNCOUT,SYNCOUT" "0,1,2,3" bitfld.long 0x0 0.--1. "SYNCIN,SYNCIN" "0,1,2,3" line.long 0x4 "SAI_ACR1,Configuration register 1" bitfld.long 0x4 27. "MCKEN,MCKEN" "0,1" bitfld.long 0x4 26. "OSR,OSR" "0,1" hexmask.long.byte 0x4 20.--25. 1. "MCKDIV,MCKDIV" bitfld.long 0x4 19. "NODIV,NODIV" "0,1" bitfld.long 0x4 17. "DMAEN,DMAEN" "0,1" bitfld.long 0x4 16. "SAIEN,SAIEN" "0,1" newline bitfld.long 0x4 13. "OUTDRIV,OUTDRIV" "0,1" bitfld.long 0x4 12. "MONO,MONO" "0,1" bitfld.long 0x4 10.--11. "SYNCEN,SYNCEN" "0,1,2,3" bitfld.long 0x4 9. "CKSTR,CKSTR" "0,1" bitfld.long 0x4 8. "LSBFIRST,LSBFIRST" "0,1" bitfld.long 0x4 5.--7. "DS,DS" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 2.--3. "PRTCFG,PRTCFG" "0,1,2,3" bitfld.long 0x4 0.--1. "MODE,MODE" "0,1,2,3" line.long 0x8 "SAI_ACR2,Configuration register 2" bitfld.long 0x8 14.--15. "COMP,COMP" "0,1,2,3" bitfld.long 0x8 13. "CPL,CPL" "0,1" hexmask.long.byte 0x8 7.--12. 1. "MUTECNT,MUTECNT" bitfld.long 0x8 6. "MUTEVAL,MUTEVAL" "0,1" bitfld.long 0x8 5. "MUTE,MUTE" "0,1" bitfld.long 0x8 4. "TRIS,TRIS" "0,1" newline bitfld.long 0x8 3. "FFLUSH,FFLUSH" "0,1" bitfld.long 0x8 0.--2. "FTH,FTH" "0,1,2,3,4,5,6,7" line.long 0xC "SAI_AFRCR,This register has no meaning in and SPDIF audio protocol" bitfld.long 0xC 18. "FSOFF,FSOFF" "0,1" bitfld.long 0xC 17. "FSPOL,FSPOL" "0,1" rbitfld.long 0xC 16. "FSDEF,FSDEF" "0,1" hexmask.long.byte 0xC 8.--14. 1. "FSALL,FSALL" hexmask.long.byte 0xC 0.--7. 1. "FRL,FRL" line.long 0x10 "SAI_ASLOTR,This register has no meaning in and SPDIF audio protocol" hexmask.long.word 0x10 16.--31. 1. "SLOTEN,SLOTEN" hexmask.long.byte 0x10 8.--11. 1. "NBSLOT,NBSLOT" bitfld.long 0x10 6.--7. "SLOTSZ,SLOTSZ" "0,1,2,3" hexmask.long.byte 0x10 0.--4. 1. "FBOFF,FBOFF" line.long 0x14 "SAI_AIM,Interrupt mask register" bitfld.long 0x14 6. "LFSDETIE,LFSDETIE" "0,1" bitfld.long 0x14 5. "AFSDETIE,AFSDETIE" "0,1" bitfld.long 0x14 4. "CNRDYIE,CNRDYIE" "0,1" bitfld.long 0x14 3. "FREQIE,FREQIE" "0,1" bitfld.long 0x14 2. "WCKCFGIE,WCKCFGIE" "0,1" bitfld.long 0x14 1. "MUTEDETIE,MUTEDETIE" "0,1" newline bitfld.long 0x14 0. "OVRUDRIE,OVRUDRIE" "0,1" rgroup.long 0x18++0x3 line.long 0x0 "SAI_ASR,Status register" bitfld.long 0x0 16.--18. "FLVL,FLVL" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6. "LFSDET,LFSDET" "0,1" bitfld.long 0x0 5. "AFSDET,AFSDET" "0,1" bitfld.long 0x0 4. "CNRDY,CNRDY" "0,1" bitfld.long 0x0 3. "FREQ,FREQ" "0,1" bitfld.long 0x0 2. "WCKCFG,WCKCFG" "0,1" newline bitfld.long 0x0 1. "MUTEDET,MUTEDET" "0,1" bitfld.long 0x0 0. "OVRUDR,OVRUDR" "0,1" wgroup.long 0x1C++0x3 line.long 0x0 "SAI_ACLRFR,Clear flag register" bitfld.long 0x0 6. "CLFSDET,CLFSDET" "0,1" bitfld.long 0x0 5. "CAFSDET,CAFSDET" "0,1" bitfld.long 0x0 4. "CCNRDY,CCNRDY" "0,1" bitfld.long 0x0 2. "CWCKCFG,CWCKCFG" "0,1" bitfld.long 0x0 1. "CMUTEDET,CMUTEDET" "0,1" bitfld.long 0x0 0. "COVRUDR,COVRUDR" "0,1" group.long 0x20++0x17 line.long 0x0 "SAI_ADR,Data register" hexmask.long 0x0 0.--31. 1. "DATA,DATA" line.long 0x4 "SAI_BCR1,Configuration register 1" bitfld.long 0x4 27. "MCKEN,MCKEN" "0,1" bitfld.long 0x4 26. "OSR,OSR" "0,1" hexmask.long.byte 0x4 20.--25. 1. "MCKDIV,MCKDIV" bitfld.long 0x4 19. "NODIV,NODIV" "0,1" bitfld.long 0x4 17. "DMAEN,DMAEN" "0,1" bitfld.long 0x4 16. "SAIEN,SAIEN" "0,1" newline bitfld.long 0x4 13. "OUTDRIV,OUTDRIV" "0,1" bitfld.long 0x4 12. "MONO,MONO" "0,1" bitfld.long 0x4 10.--11. "SYNCEN,SYNCEN" "0,1,2,3" bitfld.long 0x4 9. "CKSTR,CKSTR" "0,1" bitfld.long 0x4 8. "LSBFIRST,LSBFIRST" "0,1" bitfld.long 0x4 5.--7. "DS,DS" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 2.--3. "PRTCFG,PRTCFG" "0,1,2,3" bitfld.long 0x4 0.--1. "MODE,MODE" "0,1,2,3" line.long 0x8 "SAI_BCR2,Configuration register 2" bitfld.long 0x8 14.--15. "COMP,COMP" "0,1,2,3" bitfld.long 0x8 13. "CPL,CPL" "0,1" hexmask.long.byte 0x8 7.--12. 1. "MUTECNT,MUTECNT" bitfld.long 0x8 6. "MUTEVAL,MUTEVAL" "0,1" bitfld.long 0x8 5. "MUTE,MUTE" "0,1" bitfld.long 0x8 4. "TRIS,TRIS" "0,1" newline bitfld.long 0x8 3. "FFLUSH,FFLUSH" "0,1" bitfld.long 0x8 0.--2. "FTH,FTH" "0,1,2,3,4,5,6,7" line.long 0xC "SAI_BFRCR,This register has no meaning in and SPDIF audio protocol" bitfld.long 0xC 18. "FSOFF,FSOFF" "0,1" bitfld.long 0xC 17. "FSPOL,FSPOL" "0,1" rbitfld.long 0xC 16. "FSDEF,FSDEF" "0,1" hexmask.long.byte 0xC 8.--14. 1. "FSALL,FSALL" hexmask.long.byte 0xC 0.--7. 1. "FRL,FRL" line.long 0x10 "SAI_BSLOTR,This register has no meaning in and SPDIF audio protocol" hexmask.long.word 0x10 16.--31. 1. "SLOTEN,SLOTEN" hexmask.long.byte 0x10 8.--11. 1. "NBSLOT,NBSLOT" bitfld.long 0x10 6.--7. "SLOTSZ,SLOTSZ" "0,1,2,3" hexmask.long.byte 0x10 0.--4. 1. "FBOFF,FBOFF" line.long 0x14 "SAI_BIM,Interrupt mask register" bitfld.long 0x14 6. "LFSDETIE,LFSDETIE" "0,1" bitfld.long 0x14 5. "AFSDETIE,AFSDETIE" "0,1" bitfld.long 0x14 4. "CNRDYIE,CNRDYIE" "0,1" bitfld.long 0x14 3. "FREQIE,FREQIE" "0,1" bitfld.long 0x14 2. "WCKCFGIE,WCKCFGIE" "0,1" bitfld.long 0x14 1. "MUTEDETIE,MUTEDETIE" "0,1" newline bitfld.long 0x14 0. "OVRUDRIE,OVRUDRIE" "0,1" rgroup.long 0x38++0x3 line.long 0x0 "SAI_BSR,Status register" bitfld.long 0x0 16.--18. "FLVL,FLVL" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6. "LFSDET,LFSDET" "0,1" bitfld.long 0x0 5. "AFSDET,AFSDET" "0,1" bitfld.long 0x0 4. "CNRDY,CNRDY" "0,1" bitfld.long 0x0 3. "FREQ,FREQ" "0,1" bitfld.long 0x0 2. "WCKCFG,WCKCFG" "0,1" newline bitfld.long 0x0 1. "MUTEDET,MUTEDET" "0,1" bitfld.long 0x0 0. "OVRUDR,OVRUDR" "0,1" wgroup.long 0x3C++0x3 line.long 0x0 "SAI_BCLRFR,Clear flag register" bitfld.long 0x0 6. "CLFSDET,CLFSDET" "0,1" bitfld.long 0x0 5. "CAFSDET,CAFSDET" "0,1" bitfld.long 0x0 4. "CCNRDY,CCNRDY" "0,1" bitfld.long 0x0 2. "CWCKCFG,CWCKCFG" "0,1" bitfld.long 0x0 1. "CMUTEDET,CMUTEDET" "0,1" bitfld.long 0x0 0. "COVRUDR,COVRUDR" "0,1" group.long 0x40++0xB line.long 0x0 "SAI_BDR,Data register" hexmask.long 0x0 0.--31. 1. "DATA,DATA" line.long 0x4 "SAI_PDMCR,PDM control register" bitfld.long 0x4 11. "CKEN4,CKEN4" "0,1" bitfld.long 0x4 10. "CKEN3,CKEN3" "0,1" bitfld.long 0x4 9. "CKEN2,CKEN2" "0,1" bitfld.long 0x4 8. "CKEN1,CKEN1" "0,1" bitfld.long 0x4 4.--5. "MICNBR,MICNBR" "0,1,2,3" bitfld.long 0x4 0. "PDMEN,PDMEN" "0,1" line.long 0x8 "SAI_PDMDLY,PDM delay register" bitfld.long 0x8 28.--30. "DLYM4R,DLYM4R" "0,1,2,3,4,5,6,7" bitfld.long 0x8 24.--26. "DLYM4L,DLYM4L" "0,1,2,3,4,5,6,7" bitfld.long 0x8 20.--22. "DLYM3R,DLYM3R" "0,1,2,3,4,5,6,7" bitfld.long 0x8 16.--18. "DLYM3L,DLYM3L" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "DLYM2R,DLYM2R" "0,1,2,3,4,5,6,7" bitfld.long 0x8 8.--10. "DLYM2L,DLYM2L" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 4.--6. "DLYM1R,DLYM1R" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "DLYM1L,DLYM1L" "0,1,2,3,4,5,6,7" rgroup.long 0x3F0++0xF line.long 0x0 "SAI_HWCFGR,SAI hardware configuration register" hexmask.long.byte 0x0 12.--19. 1. "OPTION_REGOUT,OPTION_REGOUT" hexmask.long.byte 0x0 8.--11. 1. "SPDIF_PDM,SPDIF_PDM" hexmask.long.byte 0x0 0.--7. 1. "FIFO_SIZE,FIFO_SIZE" line.long 0x4 "SAI_VERR,SAI version register" hexmask.long.byte 0x4 4.--7. 1. "MAJREV,MAJREV" hexmask.long.byte 0x4 0.--3. 1. "MINREV,MINREV" line.long 0x8 "SAI_IPIDR,SAI identification register" hexmask.long 0x8 0.--31. 1. "ID,ID" line.long 0xC "SAI_SIDR,SAI size identification register" hexmask.long 0xC 0.--31. 1. "SID,SID" tree.end tree "SAI4" base ad:0x50027000 group.long 0x0++0x17 line.long 0x0 "SAI_GCR,Global configuration register" bitfld.long 0x0 4.--5. "SYNCOUT,SYNCOUT" "0,1,2,3" bitfld.long 0x0 0.--1. "SYNCIN,SYNCIN" "0,1,2,3" line.long 0x4 "SAI_ACR1,Configuration register 1" bitfld.long 0x4 27. "MCKEN,MCKEN" "0,1" bitfld.long 0x4 26. "OSR,OSR" "0,1" hexmask.long.byte 0x4 20.--25. 1. "MCKDIV,MCKDIV" bitfld.long 0x4 19. "NODIV,NODIV" "0,1" bitfld.long 0x4 17. "DMAEN,DMAEN" "0,1" bitfld.long 0x4 16. "SAIEN,SAIEN" "0,1" newline bitfld.long 0x4 13. "OUTDRIV,OUTDRIV" "0,1" bitfld.long 0x4 12. "MONO,MONO" "0,1" bitfld.long 0x4 10.--11. "SYNCEN,SYNCEN" "0,1,2,3" bitfld.long 0x4 9. "CKSTR,CKSTR" "0,1" bitfld.long 0x4 8. "LSBFIRST,LSBFIRST" "0,1" bitfld.long 0x4 5.--7. "DS,DS" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 2.--3. "PRTCFG,PRTCFG" "0,1,2,3" bitfld.long 0x4 0.--1. "MODE,MODE" "0,1,2,3" line.long 0x8 "SAI_ACR2,Configuration register 2" bitfld.long 0x8 14.--15. "COMP,COMP" "0,1,2,3" bitfld.long 0x8 13. "CPL,CPL" "0,1" hexmask.long.byte 0x8 7.--12. 1. "MUTECNT,MUTECNT" bitfld.long 0x8 6. "MUTEVAL,MUTEVAL" "0,1" bitfld.long 0x8 5. "MUTE,MUTE" "0,1" bitfld.long 0x8 4. "TRIS,TRIS" "0,1" newline bitfld.long 0x8 3. "FFLUSH,FFLUSH" "0,1" bitfld.long 0x8 0.--2. "FTH,FTH" "0,1,2,3,4,5,6,7" line.long 0xC "SAI_AFRCR,This register has no meaning in and SPDIF audio protocol" bitfld.long 0xC 18. "FSOFF,FSOFF" "0,1" bitfld.long 0xC 17. "FSPOL,FSPOL" "0,1" rbitfld.long 0xC 16. "FSDEF,FSDEF" "0,1" hexmask.long.byte 0xC 8.--14. 1. "FSALL,FSALL" hexmask.long.byte 0xC 0.--7. 1. "FRL,FRL" line.long 0x10 "SAI_ASLOTR,This register has no meaning in and SPDIF audio protocol" hexmask.long.word 0x10 16.--31. 1. "SLOTEN,SLOTEN" hexmask.long.byte 0x10 8.--11. 1. "NBSLOT,NBSLOT" bitfld.long 0x10 6.--7. "SLOTSZ,SLOTSZ" "0,1,2,3" hexmask.long.byte 0x10 0.--4. 1. "FBOFF,FBOFF" line.long 0x14 "SAI_AIM,Interrupt mask register" bitfld.long 0x14 6. "LFSDETIE,LFSDETIE" "0,1" bitfld.long 0x14 5. "AFSDETIE,AFSDETIE" "0,1" bitfld.long 0x14 4. "CNRDYIE,CNRDYIE" "0,1" bitfld.long 0x14 3. "FREQIE,FREQIE" "0,1" bitfld.long 0x14 2. "WCKCFGIE,WCKCFGIE" "0,1" bitfld.long 0x14 1. "MUTEDETIE,MUTEDETIE" "0,1" newline bitfld.long 0x14 0. "OVRUDRIE,OVRUDRIE" "0,1" rgroup.long 0x18++0x3 line.long 0x0 "SAI_ASR,Status register" bitfld.long 0x0 16.--18. "FLVL,FLVL" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6. "LFSDET,LFSDET" "0,1" bitfld.long 0x0 5. "AFSDET,AFSDET" "0,1" bitfld.long 0x0 4. "CNRDY,CNRDY" "0,1" bitfld.long 0x0 3. "FREQ,FREQ" "0,1" bitfld.long 0x0 2. "WCKCFG,WCKCFG" "0,1" newline bitfld.long 0x0 1. "MUTEDET,MUTEDET" "0,1" bitfld.long 0x0 0. "OVRUDR,OVRUDR" "0,1" wgroup.long 0x1C++0x3 line.long 0x0 "SAI_ACLRFR,Clear flag register" bitfld.long 0x0 6. "CLFSDET,CLFSDET" "0,1" bitfld.long 0x0 5. "CAFSDET,CAFSDET" "0,1" bitfld.long 0x0 4. "CCNRDY,CCNRDY" "0,1" bitfld.long 0x0 2. "CWCKCFG,CWCKCFG" "0,1" bitfld.long 0x0 1. "CMUTEDET,CMUTEDET" "0,1" bitfld.long 0x0 0. "COVRUDR,COVRUDR" "0,1" group.long 0x20++0x17 line.long 0x0 "SAI_ADR,Data register" hexmask.long 0x0 0.--31. 1. "DATA,DATA" line.long 0x4 "SAI_BCR1,Configuration register 1" bitfld.long 0x4 27. "MCKEN,MCKEN" "0,1" bitfld.long 0x4 26. "OSR,OSR" "0,1" hexmask.long.byte 0x4 20.--25. 1. "MCKDIV,MCKDIV" bitfld.long 0x4 19. "NODIV,NODIV" "0,1" bitfld.long 0x4 17. "DMAEN,DMAEN" "0,1" bitfld.long 0x4 16. "SAIEN,SAIEN" "0,1" newline bitfld.long 0x4 13. "OUTDRIV,OUTDRIV" "0,1" bitfld.long 0x4 12. "MONO,MONO" "0,1" bitfld.long 0x4 10.--11. "SYNCEN,SYNCEN" "0,1,2,3" bitfld.long 0x4 9. "CKSTR,CKSTR" "0,1" bitfld.long 0x4 8. "LSBFIRST,LSBFIRST" "0,1" bitfld.long 0x4 5.--7. "DS,DS" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 2.--3. "PRTCFG,PRTCFG" "0,1,2,3" bitfld.long 0x4 0.--1. "MODE,MODE" "0,1,2,3" line.long 0x8 "SAI_BCR2,Configuration register 2" bitfld.long 0x8 14.--15. "COMP,COMP" "0,1,2,3" bitfld.long 0x8 13. "CPL,CPL" "0,1" hexmask.long.byte 0x8 7.--12. 1. "MUTECNT,MUTECNT" bitfld.long 0x8 6. "MUTEVAL,MUTEVAL" "0,1" bitfld.long 0x8 5. "MUTE,MUTE" "0,1" bitfld.long 0x8 4. "TRIS,TRIS" "0,1" newline bitfld.long 0x8 3. "FFLUSH,FFLUSH" "0,1" bitfld.long 0x8 0.--2. "FTH,FTH" "0,1,2,3,4,5,6,7" line.long 0xC "SAI_BFRCR,This register has no meaning in and SPDIF audio protocol" bitfld.long 0xC 18. "FSOFF,FSOFF" "0,1" bitfld.long 0xC 17. "FSPOL,FSPOL" "0,1" rbitfld.long 0xC 16. "FSDEF,FSDEF" "0,1" hexmask.long.byte 0xC 8.--14. 1. "FSALL,FSALL" hexmask.long.byte 0xC 0.--7. 1. "FRL,FRL" line.long 0x10 "SAI_BSLOTR,This register has no meaning in and SPDIF audio protocol" hexmask.long.word 0x10 16.--31. 1. "SLOTEN,SLOTEN" hexmask.long.byte 0x10 8.--11. 1. "NBSLOT,NBSLOT" bitfld.long 0x10 6.--7. "SLOTSZ,SLOTSZ" "0,1,2,3" hexmask.long.byte 0x10 0.--4. 1. "FBOFF,FBOFF" line.long 0x14 "SAI_BIM,Interrupt mask register" bitfld.long 0x14 6. "LFSDETIE,LFSDETIE" "0,1" bitfld.long 0x14 5. "AFSDETIE,AFSDETIE" "0,1" bitfld.long 0x14 4. "CNRDYIE,CNRDYIE" "0,1" bitfld.long 0x14 3. "FREQIE,FREQIE" "0,1" bitfld.long 0x14 2. "WCKCFGIE,WCKCFGIE" "0,1" bitfld.long 0x14 1. "MUTEDETIE,MUTEDETIE" "0,1" newline bitfld.long 0x14 0. "OVRUDRIE,OVRUDRIE" "0,1" rgroup.long 0x38++0x3 line.long 0x0 "SAI_BSR,Status register" bitfld.long 0x0 16.--18. "FLVL,FLVL" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6. "LFSDET,LFSDET" "0,1" bitfld.long 0x0 5. "AFSDET,AFSDET" "0,1" bitfld.long 0x0 4. "CNRDY,CNRDY" "0,1" bitfld.long 0x0 3. "FREQ,FREQ" "0,1" bitfld.long 0x0 2. "WCKCFG,WCKCFG" "0,1" newline bitfld.long 0x0 1. "MUTEDET,MUTEDET" "0,1" bitfld.long 0x0 0. "OVRUDR,OVRUDR" "0,1" wgroup.long 0x3C++0x3 line.long 0x0 "SAI_BCLRFR,Clear flag register" bitfld.long 0x0 6. "CLFSDET,CLFSDET" "0,1" bitfld.long 0x0 5. "CAFSDET,CAFSDET" "0,1" bitfld.long 0x0 4. "CCNRDY,CCNRDY" "0,1" bitfld.long 0x0 2. "CWCKCFG,CWCKCFG" "0,1" bitfld.long 0x0 1. "CMUTEDET,CMUTEDET" "0,1" bitfld.long 0x0 0. "COVRUDR,COVRUDR" "0,1" group.long 0x40++0xB line.long 0x0 "SAI_BDR,Data register" hexmask.long 0x0 0.--31. 1. "DATA,DATA" line.long 0x4 "SAI_PDMCR,PDM control register" bitfld.long 0x4 11. "CKEN4,CKEN4" "0,1" bitfld.long 0x4 10. "CKEN3,CKEN3" "0,1" bitfld.long 0x4 9. "CKEN2,CKEN2" "0,1" bitfld.long 0x4 8. "CKEN1,CKEN1" "0,1" bitfld.long 0x4 4.--5. "MICNBR,MICNBR" "0,1,2,3" bitfld.long 0x4 0. "PDMEN,PDMEN" "0,1" line.long 0x8 "SAI_PDMDLY,PDM delay register" bitfld.long 0x8 28.--30. "DLYM4R,DLYM4R" "0,1,2,3,4,5,6,7" bitfld.long 0x8 24.--26. "DLYM4L,DLYM4L" "0,1,2,3,4,5,6,7" bitfld.long 0x8 20.--22. "DLYM3R,DLYM3R" "0,1,2,3,4,5,6,7" bitfld.long 0x8 16.--18. "DLYM3L,DLYM3L" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "DLYM2R,DLYM2R" "0,1,2,3,4,5,6,7" bitfld.long 0x8 8.--10. "DLYM2L,DLYM2L" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 4.--6. "DLYM1R,DLYM1R" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "DLYM1L,DLYM1L" "0,1,2,3,4,5,6,7" rgroup.long 0x3F0++0xF line.long 0x0 "SAI_HWCFGR,SAI hardware configuration register" hexmask.long.byte 0x0 12.--19. 1. "OPTION_REGOUT,OPTION_REGOUT" hexmask.long.byte 0x0 8.--11. 1. "SPDIF_PDM,SPDIF_PDM" hexmask.long.byte 0x0 0.--7. 1. "FIFO_SIZE,FIFO_SIZE" line.long 0x4 "SAI_VERR,SAI version register" hexmask.long.byte 0x4 4.--7. 1. "MAJREV,MAJREV" hexmask.long.byte 0x4 0.--3. 1. "MINREV,MINREV" line.long 0x8 "SAI_IPIDR,SAI identification register" hexmask.long 0x8 0.--31. 1. "ID,ID" line.long 0xC "SAI_SIDR,SAI size identification register" hexmask.long 0xC 0.--31. 1. "SID,SID" tree.end endif sif (cpuis("STM32MP157*")) tree "SAI3" base ad:0x4400C000 group.long 0x0++0x17 line.long 0x0 "SAI_GCR,Global configuration register" bitfld.long 0x0 4.--5. "SYNCOUT,SYNCOUT" "0,1,2,3" bitfld.long 0x0 0.--1. "SYNCIN,SYNCIN" "0,1,2,3" line.long 0x4 "SAI_ACR1,Configuration register 1" bitfld.long 0x4 27. "MCKEN,MCKEN" "0,1" bitfld.long 0x4 26. "OSR,OSR" "0,1" hexmask.long.byte 0x4 20.--25. 1. "MCKDIV,MCKDIV" bitfld.long 0x4 19. "NODIV,NODIV" "0,1" bitfld.long 0x4 17. "DMAEN,DMAEN" "0,1" bitfld.long 0x4 16. "SAIEN,SAIEN" "0,1" newline bitfld.long 0x4 13. "OUTDRIV,OUTDRIV" "0,1" bitfld.long 0x4 12. "MONO,MONO" "0,1" bitfld.long 0x4 10.--11. "SYNCEN,SYNCEN" "0,1,2,3" bitfld.long 0x4 9. "CKSTR,CKSTR" "0,1" bitfld.long 0x4 8. "LSBFIRST,LSBFIRST" "0,1" bitfld.long 0x4 5.--7. "DS,DS" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 2.--3. "PRTCFG,PRTCFG" "0,1,2,3" bitfld.long 0x4 0.--1. "MODE,MODE" "0,1,2,3" line.long 0x8 "SAI_ACR2,Configuration register 2" bitfld.long 0x8 14.--15. "COMP,COMP" "0,1,2,3" bitfld.long 0x8 13. "CPL,CPL" "0,1" hexmask.long.byte 0x8 7.--12. 1. "MUTECNT,MUTECNT" bitfld.long 0x8 6. "MUTEVAL,MUTEVAL" "0,1" bitfld.long 0x8 5. "MUTE,MUTE" "0,1" bitfld.long 0x8 4. "TRIS,TRIS" "0,1" newline bitfld.long 0x8 3. "FFLUSH,FFLUSH" "0,1" bitfld.long 0x8 0.--2. "FTH,FTH" "0,1,2,3,4,5,6,7" line.long 0xC "SAI_AFRCR,This register has no meaning in and SPDIF audio protocol" bitfld.long 0xC 18. "FSOFF,FSOFF" "0,1" bitfld.long 0xC 17. "FSPOL,FSPOL" "0,1" rbitfld.long 0xC 16. "FSDEF,FSDEF" "0,1" hexmask.long.byte 0xC 8.--14. 1. "FSALL,FSALL" hexmask.long.byte 0xC 0.--7. 1. "FRL,FRL" line.long 0x10 "SAI_ASLOTR,This register has no meaning in and SPDIF audio protocol" hexmask.long.word 0x10 16.--31. 1. "SLOTEN,SLOTEN" hexmask.long.byte 0x10 8.--11. 1. "NBSLOT,NBSLOT" bitfld.long 0x10 6.--7. "SLOTSZ,SLOTSZ" "0,1,2,3" hexmask.long.byte 0x10 0.--4. 1. "FBOFF,FBOFF" line.long 0x14 "SAI_AIM,Interrupt mask register" bitfld.long 0x14 6. "LFSDETIE,LFSDETIE" "0,1" bitfld.long 0x14 5. "AFSDETIE,AFSDETIE" "0,1" bitfld.long 0x14 4. "CNRDYIE,CNRDYIE" "0,1" bitfld.long 0x14 3. "FREQIE,FREQIE" "0,1" bitfld.long 0x14 2. "WCKCFGIE,WCKCFGIE" "0,1" bitfld.long 0x14 1. "MUTEDETIE,MUTEDETIE" "0,1" newline bitfld.long 0x14 0. "OVRUDRIE,OVRUDRIE" "0,1" rgroup.long 0x18++0x3 line.long 0x0 "SAI_ASR,Status register" bitfld.long 0x0 16.--18. "FLVL,FLVL" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6. "LFSDET,LFSDET" "0,1" bitfld.long 0x0 5. "AFSDET,AFSDET" "0,1" bitfld.long 0x0 4. "CNRDY,CNRDY" "0,1" bitfld.long 0x0 3. "FREQ,FREQ" "0,1" bitfld.long 0x0 2. "WCKCFG,WCKCFG" "0,1" newline bitfld.long 0x0 1. "MUTEDET,MUTEDET" "0,1" bitfld.long 0x0 0. "OVRUDR,OVRUDR" "0,1" wgroup.long 0x1C++0x3 line.long 0x0 "SAI_ACLRFR,Clear flag register" bitfld.long 0x0 6. "CLFSDET,CLFSDET" "0,1" bitfld.long 0x0 5. "CAFSDET,CAFSDET" "0,1" bitfld.long 0x0 4. "CCNRDY,CCNRDY" "0,1" bitfld.long 0x0 2. "CWCKCFG,CWCKCFG" "0,1" bitfld.long 0x0 1. "CMUTEDET,CMUTEDET" "0,1" bitfld.long 0x0 0. "COVRUDR,COVRUDR" "0,1" group.long 0x20++0x17 line.long 0x0 "SAI_ADR,Data register" hexmask.long 0x0 0.--31. 1. "DATA,DATA" line.long 0x4 "SAI_BCR1,Configuration register 1" bitfld.long 0x4 27. "MCKEN,MCKEN" "0,1" bitfld.long 0x4 26. "OSR,OSR" "0,1" hexmask.long.byte 0x4 20.--25. 1. "MCKDIV,MCKDIV" bitfld.long 0x4 19. "NODIV,NODIV" "0,1" bitfld.long 0x4 17. "DMAEN,DMAEN" "0,1" bitfld.long 0x4 16. "SAIEN,SAIEN" "0,1" newline bitfld.long 0x4 13. "OUTDRIV,OUTDRIV" "0,1" bitfld.long 0x4 12. "MONO,MONO" "0,1" bitfld.long 0x4 10.--11. "SYNCEN,SYNCEN" "0,1,2,3" bitfld.long 0x4 9. "CKSTR,CKSTR" "0,1" bitfld.long 0x4 8. "LSBFIRST,LSBFIRST" "0,1" bitfld.long 0x4 5.--7. "DS,DS" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 2.--3. "PRTCFG,PRTCFG" "0,1,2,3" bitfld.long 0x4 0.--1. "MODE,MODE" "0,1,2,3" line.long 0x8 "SAI_BCR2,Configuration register 2" bitfld.long 0x8 14.--15. "COMP,COMP" "0,1,2,3" bitfld.long 0x8 13. "CPL,CPL" "0,1" hexmask.long.byte 0x8 7.--12. 1. "MUTECNT,MUTECNT" bitfld.long 0x8 6. "MUTEVAL,MUTEVAL" "0,1" bitfld.long 0x8 5. "MUTE,MUTE" "0,1" bitfld.long 0x8 4. "TRIS,TRIS" "0,1" newline bitfld.long 0x8 3. "FFLUSH,FFLUSH" "0,1" bitfld.long 0x8 0.--2. "FTH,FTH" "0,1,2,3,4,5,6,7" line.long 0xC "SAI_BFRCR,This register has no meaning in and SPDIF audio protocol" bitfld.long 0xC 18. "FSOFF,FSOFF" "0,1" bitfld.long 0xC 17. "FSPOL,FSPOL" "0,1" rbitfld.long 0xC 16. "FSDEF,FSDEF" "0,1" hexmask.long.byte 0xC 8.--14. 1. "FSALL,FSALL" hexmask.long.byte 0xC 0.--7. 1. "FRL,FRL" line.long 0x10 "SAI_BSLOTR,This register has no meaning in and SPDIF audio protocol" hexmask.long.word 0x10 16.--31. 1. "SLOTEN,SLOTEN" hexmask.long.byte 0x10 8.--11. 1. "NBSLOT,NBSLOT" bitfld.long 0x10 6.--7. "SLOTSZ,SLOTSZ" "0,1,2,3" hexmask.long.byte 0x10 0.--4. 1. "FBOFF,FBOFF" line.long 0x14 "SAI_BIM,Interrupt mask register" bitfld.long 0x14 6. "LFSDETIE,LFSDETIE" "0,1" bitfld.long 0x14 5. "AFSDETIE,AFSDETIE" "0,1" bitfld.long 0x14 4. "CNRDYIE,CNRDYIE" "0,1" bitfld.long 0x14 3. "FREQIE,FREQIE" "0,1" bitfld.long 0x14 2. "WCKCFGIE,WCKCFGIE" "0,1" bitfld.long 0x14 1. "MUTEDETIE,MUTEDETIE" "0,1" newline bitfld.long 0x14 0. "OVRUDRIE,OVRUDRIE" "0,1" rgroup.long 0x38++0x3 line.long 0x0 "SAI_BSR,Status register" bitfld.long 0x0 16.--18. "FLVL,FLVL" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6. "LFSDET,LFSDET" "0,1" bitfld.long 0x0 5. "AFSDET,AFSDET" "0,1" bitfld.long 0x0 4. "CNRDY,CNRDY" "0,1" bitfld.long 0x0 3. "FREQ,FREQ" "0,1" bitfld.long 0x0 2. "WCKCFG,WCKCFG" "0,1" newline bitfld.long 0x0 1. "MUTEDET,MUTEDET" "0,1" bitfld.long 0x0 0. "OVRUDR,OVRUDR" "0,1" wgroup.long 0x3C++0x3 line.long 0x0 "SAI_BCLRFR,Clear flag register" bitfld.long 0x0 6. "CLFSDET,CLFSDET" "0,1" bitfld.long 0x0 5. "CAFSDET,CAFSDET" "0,1" bitfld.long 0x0 4. "CCNRDY,CCNRDY" "0,1" bitfld.long 0x0 2. "CWCKCFG,CWCKCFG" "0,1" bitfld.long 0x0 1. "CMUTEDET,CMUTEDET" "0,1" bitfld.long 0x0 0. "COVRUDR,COVRUDR" "0,1" group.long 0x40++0xB line.long 0x0 "SAI_BDR,Data register" hexmask.long 0x0 0.--31. 1. "DATA,DATA" line.long 0x4 "SAI_PDMCR,PDM control register" bitfld.long 0x4 11. "CKEN4,CKEN4" "0,1" bitfld.long 0x4 10. "CKEN3,CKEN3" "0,1" bitfld.long 0x4 9. "CKEN2,CKEN2" "0,1" bitfld.long 0x4 8. "CKEN1,CKEN1" "0,1" bitfld.long 0x4 4.--5. "MICNBR,MICNBR" "0,1,2,3" bitfld.long 0x4 0. "PDMEN,PDMEN" "0,1" line.long 0x8 "SAI_PDMDLY,PDM delay register" bitfld.long 0x8 28.--30. "DLYM4R,DLYM4R" "0,1,2,3,4,5,6,7" bitfld.long 0x8 24.--26. "DLYM4L,DLYM4L" "0,1,2,3,4,5,6,7" bitfld.long 0x8 20.--22. "DLYM3R,DLYM3R" "0,1,2,3,4,5,6,7" bitfld.long 0x8 16.--18. "DLYM3L,DLYM3L" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "DLYM2R,DLYM2R" "0,1,2,3,4,5,6,7" bitfld.long 0x8 8.--10. "DLYM2L,DLYM2L" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 4.--6. "DLYM1R,DLYM1R" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "DLYM1L,DLYM1L" "0,1,2,3,4,5,6,7" rgroup.long 0x3F0++0xF line.long 0x0 "SAI_HWCFGR,SAI hardware configuration register" hexmask.long.byte 0x0 12.--19. 1. "OPTION_REGOUT,OPTION_REGOUT" hexmask.long.byte 0x0 8.--11. 1. "SPDIF_PDM,SPDIF_PDM" hexmask.long.byte 0x0 0.--7. 1. "FIFO_SIZE,FIFO_SIZE" line.long 0x4 "SAI_VERR,SAI version register" hexmask.long.byte 0x4 4.--7. 1. "MAJREV,MAJREV" hexmask.long.byte 0x4 0.--3. 1. "MINREV,MINREV" line.long 0x8 "SAI_IPIDR,SAI identification register" hexmask.long 0x8 0.--31. 1. "ID,ID" line.long 0xC "SAI_SIDR,SAI size identification register" hexmask.long 0xC 0.--31. 1. "SID,SID" tree.end tree "SAI4" base ad:0x50027000 group.long 0x0++0x17 line.long 0x0 "SAI_GCR,Global configuration register" bitfld.long 0x0 4.--5. "SYNCOUT,SYNCOUT" "0,1,2,3" bitfld.long 0x0 0.--1. "SYNCIN,SYNCIN" "0,1,2,3" line.long 0x4 "SAI_ACR1,Configuration register 1" bitfld.long 0x4 27. "MCKEN,MCKEN" "0,1" bitfld.long 0x4 26. "OSR,OSR" "0,1" hexmask.long.byte 0x4 20.--25. 1. "MCKDIV,MCKDIV" bitfld.long 0x4 19. "NODIV,NODIV" "0,1" bitfld.long 0x4 17. "DMAEN,DMAEN" "0,1" bitfld.long 0x4 16. "SAIEN,SAIEN" "0,1" newline bitfld.long 0x4 13. "OUTDRIV,OUTDRIV" "0,1" bitfld.long 0x4 12. "MONO,MONO" "0,1" bitfld.long 0x4 10.--11. "SYNCEN,SYNCEN" "0,1,2,3" bitfld.long 0x4 9. "CKSTR,CKSTR" "0,1" bitfld.long 0x4 8. "LSBFIRST,LSBFIRST" "0,1" bitfld.long 0x4 5.--7. "DS,DS" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 2.--3. "PRTCFG,PRTCFG" "0,1,2,3" bitfld.long 0x4 0.--1. "MODE,MODE" "0,1,2,3" line.long 0x8 "SAI_ACR2,Configuration register 2" bitfld.long 0x8 14.--15. "COMP,COMP" "0,1,2,3" bitfld.long 0x8 13. "CPL,CPL" "0,1" hexmask.long.byte 0x8 7.--12. 1. "MUTECNT,MUTECNT" bitfld.long 0x8 6. "MUTEVAL,MUTEVAL" "0,1" bitfld.long 0x8 5. "MUTE,MUTE" "0,1" bitfld.long 0x8 4. "TRIS,TRIS" "0,1" newline bitfld.long 0x8 3. "FFLUSH,FFLUSH" "0,1" bitfld.long 0x8 0.--2. "FTH,FTH" "0,1,2,3,4,5,6,7" line.long 0xC "SAI_AFRCR,This register has no meaning in and SPDIF audio protocol" bitfld.long 0xC 18. "FSOFF,FSOFF" "0,1" bitfld.long 0xC 17. "FSPOL,FSPOL" "0,1" rbitfld.long 0xC 16. "FSDEF,FSDEF" "0,1" hexmask.long.byte 0xC 8.--14. 1. "FSALL,FSALL" hexmask.long.byte 0xC 0.--7. 1. "FRL,FRL" line.long 0x10 "SAI_ASLOTR,This register has no meaning in and SPDIF audio protocol" hexmask.long.word 0x10 16.--31. 1. "SLOTEN,SLOTEN" hexmask.long.byte 0x10 8.--11. 1. "NBSLOT,NBSLOT" bitfld.long 0x10 6.--7. "SLOTSZ,SLOTSZ" "0,1,2,3" hexmask.long.byte 0x10 0.--4. 1. "FBOFF,FBOFF" line.long 0x14 "SAI_AIM,Interrupt mask register" bitfld.long 0x14 6. "LFSDETIE,LFSDETIE" "0,1" bitfld.long 0x14 5. "AFSDETIE,AFSDETIE" "0,1" bitfld.long 0x14 4. "CNRDYIE,CNRDYIE" "0,1" bitfld.long 0x14 3. "FREQIE,FREQIE" "0,1" bitfld.long 0x14 2. "WCKCFGIE,WCKCFGIE" "0,1" bitfld.long 0x14 1. "MUTEDETIE,MUTEDETIE" "0,1" newline bitfld.long 0x14 0. "OVRUDRIE,OVRUDRIE" "0,1" rgroup.long 0x18++0x3 line.long 0x0 "SAI_ASR,Status register" bitfld.long 0x0 16.--18. "FLVL,FLVL" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6. "LFSDET,LFSDET" "0,1" bitfld.long 0x0 5. "AFSDET,AFSDET" "0,1" bitfld.long 0x0 4. "CNRDY,CNRDY" "0,1" bitfld.long 0x0 3. "FREQ,FREQ" "0,1" bitfld.long 0x0 2. "WCKCFG,WCKCFG" "0,1" newline bitfld.long 0x0 1. "MUTEDET,MUTEDET" "0,1" bitfld.long 0x0 0. "OVRUDR,OVRUDR" "0,1" wgroup.long 0x1C++0x3 line.long 0x0 "SAI_ACLRFR,Clear flag register" bitfld.long 0x0 6. "CLFSDET,CLFSDET" "0,1" bitfld.long 0x0 5. "CAFSDET,CAFSDET" "0,1" bitfld.long 0x0 4. "CCNRDY,CCNRDY" "0,1" bitfld.long 0x0 2. "CWCKCFG,CWCKCFG" "0,1" bitfld.long 0x0 1. "CMUTEDET,CMUTEDET" "0,1" bitfld.long 0x0 0. "COVRUDR,COVRUDR" "0,1" group.long 0x20++0x17 line.long 0x0 "SAI_ADR,Data register" hexmask.long 0x0 0.--31. 1. "DATA,DATA" line.long 0x4 "SAI_BCR1,Configuration register 1" bitfld.long 0x4 27. "MCKEN,MCKEN" "0,1" bitfld.long 0x4 26. "OSR,OSR" "0,1" hexmask.long.byte 0x4 20.--25. 1. "MCKDIV,MCKDIV" bitfld.long 0x4 19. "NODIV,NODIV" "0,1" bitfld.long 0x4 17. "DMAEN,DMAEN" "0,1" bitfld.long 0x4 16. "SAIEN,SAIEN" "0,1" newline bitfld.long 0x4 13. "OUTDRIV,OUTDRIV" "0,1" bitfld.long 0x4 12. "MONO,MONO" "0,1" bitfld.long 0x4 10.--11. "SYNCEN,SYNCEN" "0,1,2,3" bitfld.long 0x4 9. "CKSTR,CKSTR" "0,1" bitfld.long 0x4 8. "LSBFIRST,LSBFIRST" "0,1" bitfld.long 0x4 5.--7. "DS,DS" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 2.--3. "PRTCFG,PRTCFG" "0,1,2,3" bitfld.long 0x4 0.--1. "MODE,MODE" "0,1,2,3" line.long 0x8 "SAI_BCR2,Configuration register 2" bitfld.long 0x8 14.--15. "COMP,COMP" "0,1,2,3" bitfld.long 0x8 13. "CPL,CPL" "0,1" hexmask.long.byte 0x8 7.--12. 1. "MUTECNT,MUTECNT" bitfld.long 0x8 6. "MUTEVAL,MUTEVAL" "0,1" bitfld.long 0x8 5. "MUTE,MUTE" "0,1" bitfld.long 0x8 4. "TRIS,TRIS" "0,1" newline bitfld.long 0x8 3. "FFLUSH,FFLUSH" "0,1" bitfld.long 0x8 0.--2. "FTH,FTH" "0,1,2,3,4,5,6,7" line.long 0xC "SAI_BFRCR,This register has no meaning in and SPDIF audio protocol" bitfld.long 0xC 18. "FSOFF,FSOFF" "0,1" bitfld.long 0xC 17. "FSPOL,FSPOL" "0,1" rbitfld.long 0xC 16. "FSDEF,FSDEF" "0,1" hexmask.long.byte 0xC 8.--14. 1. "FSALL,FSALL" hexmask.long.byte 0xC 0.--7. 1. "FRL,FRL" line.long 0x10 "SAI_BSLOTR,This register has no meaning in and SPDIF audio protocol" hexmask.long.word 0x10 16.--31. 1. "SLOTEN,SLOTEN" hexmask.long.byte 0x10 8.--11. 1. "NBSLOT,NBSLOT" bitfld.long 0x10 6.--7. "SLOTSZ,SLOTSZ" "0,1,2,3" hexmask.long.byte 0x10 0.--4. 1. "FBOFF,FBOFF" line.long 0x14 "SAI_BIM,Interrupt mask register" bitfld.long 0x14 6. "LFSDETIE,LFSDETIE" "0,1" bitfld.long 0x14 5. "AFSDETIE,AFSDETIE" "0,1" bitfld.long 0x14 4. "CNRDYIE,CNRDYIE" "0,1" bitfld.long 0x14 3. "FREQIE,FREQIE" "0,1" bitfld.long 0x14 2. "WCKCFGIE,WCKCFGIE" "0,1" bitfld.long 0x14 1. "MUTEDETIE,MUTEDETIE" "0,1" newline bitfld.long 0x14 0. "OVRUDRIE,OVRUDRIE" "0,1" rgroup.long 0x38++0x3 line.long 0x0 "SAI_BSR,Status register" bitfld.long 0x0 16.--18. "FLVL,FLVL" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6. "LFSDET,LFSDET" "0,1" bitfld.long 0x0 5. "AFSDET,AFSDET" "0,1" bitfld.long 0x0 4. "CNRDY,CNRDY" "0,1" bitfld.long 0x0 3. "FREQ,FREQ" "0,1" bitfld.long 0x0 2. "WCKCFG,WCKCFG" "0,1" newline bitfld.long 0x0 1. "MUTEDET,MUTEDET" "0,1" bitfld.long 0x0 0. "OVRUDR,OVRUDR" "0,1" wgroup.long 0x3C++0x3 line.long 0x0 "SAI_BCLRFR,Clear flag register" bitfld.long 0x0 6. "CLFSDET,CLFSDET" "0,1" bitfld.long 0x0 5. "CAFSDET,CAFSDET" "0,1" bitfld.long 0x0 4. "CCNRDY,CCNRDY" "0,1" bitfld.long 0x0 2. "CWCKCFG,CWCKCFG" "0,1" bitfld.long 0x0 1. "CMUTEDET,CMUTEDET" "0,1" bitfld.long 0x0 0. "COVRUDR,COVRUDR" "0,1" group.long 0x40++0xB line.long 0x0 "SAI_BDR,Data register" hexmask.long 0x0 0.--31. 1. "DATA,DATA" line.long 0x4 "SAI_PDMCR,PDM control register" bitfld.long 0x4 11. "CKEN4,CKEN4" "0,1" bitfld.long 0x4 10. "CKEN3,CKEN3" "0,1" bitfld.long 0x4 9. "CKEN2,CKEN2" "0,1" bitfld.long 0x4 8. "CKEN1,CKEN1" "0,1" bitfld.long 0x4 4.--5. "MICNBR,MICNBR" "0,1,2,3" bitfld.long 0x4 0. "PDMEN,PDMEN" "0,1" line.long 0x8 "SAI_PDMDLY,PDM delay register" bitfld.long 0x8 28.--30. "DLYM4R,DLYM4R" "0,1,2,3,4,5,6,7" bitfld.long 0x8 24.--26. "DLYM4L,DLYM4L" "0,1,2,3,4,5,6,7" bitfld.long 0x8 20.--22. "DLYM3R,DLYM3R" "0,1,2,3,4,5,6,7" bitfld.long 0x8 16.--18. "DLYM3L,DLYM3L" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "DLYM2R,DLYM2R" "0,1,2,3,4,5,6,7" bitfld.long 0x8 8.--10. "DLYM2L,DLYM2L" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 4.--6. "DLYM1R,DLYM1R" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "DLYM1L,DLYM1L" "0,1,2,3,4,5,6,7" rgroup.long 0x3F0++0xF line.long 0x0 "SAI_HWCFGR,SAI hardware configuration register" hexmask.long.byte 0x0 12.--19. 1. "OPTION_REGOUT,OPTION_REGOUT" hexmask.long.byte 0x0 8.--11. 1. "SPDIF_PDM,SPDIF_PDM" hexmask.long.byte 0x0 0.--7. 1. "FIFO_SIZE,FIFO_SIZE" line.long 0x4 "SAI_VERR,SAI version register" hexmask.long.byte 0x4 4.--7. 1. "MAJREV,MAJREV" hexmask.long.byte 0x4 0.--3. 1. "MINREV,MINREV" line.long 0x8 "SAI_IPIDR,SAI identification register" hexmask.long 0x8 0.--31. 1. "ID,ID" line.long 0xC "SAI_SIDR,SAI size identification register" hexmask.long 0xC 0.--31. 1. "SID,SID" tree.end endif tree.end sif (cpuis("STM32MP151*")||cpuis("STM32MP153*")||cpuis("STM32MP157*")) tree "SDMMC (Secure Digital Input/Output MultiMediaCard Interface)" base ad:0x0 tree "SDMMC1" base ad:0x58005000 group.long 0x0++0xF line.long 0x0 "SDMMC_POWER,SDMMC power control register" bitfld.long 0x0 4. "DIRPOL,DIRPOL" "0,1" bitfld.long 0x0 3. "VSWITCHEN,VSWITCHEN" "0,1" bitfld.long 0x0 2. "VSWITCH,VSWITCH" "0,1" bitfld.long 0x0 0.--1. "PWRCTRL,PWRCTRL" "0,1,2,3" line.long 0x4 "SDMMC_CLKCR,The SDMMC_CLKCR register controls the SDMMC_CK output clock. the sdmmc_rx_ck receive clock. and the bus width." bitfld.long 0x4 20.--21. "SELCLKRX,SELCLKRX" "0,1,2,3" bitfld.long 0x4 19. "BUSSPEED,BUSSPEED" "0,1" bitfld.long 0x4 18. "DDR,DDR" "0,1" bitfld.long 0x4 17. "HWFC_EN,HWFC_EN" "0,1" bitfld.long 0x4 16. "NEGEDGE,NEGEDGE" "0,1" bitfld.long 0x4 14.--15. "WIDBUS,WIDBUS" "0,1,2,3" newline bitfld.long 0x4 12. "PWRSAV,PWRSAV" "0,1" hexmask.long.word 0x4 0.--9. 1. "CLKDIV,CLKDIV" line.long 0x8 "SDMMC_ARGR,The SDMMC_ARGR register contains a 32-bit command argument. which is sent to a card as part of a command message." hexmask.long 0x8 0.--31. 1. "CMDARG,CMDARG" line.long 0xC "SDMMC_CMDR,The SDMMC_CMDR register contains the command index and command type bits. The command index is sent to a card as part of a command message. The command type bits control the command path state machine (CPSM)." bitfld.long 0xC 16. "CMDSUSPEND,CMDSUSPEND" "0,1" bitfld.long 0xC 15. "BOOTEN,BOOTEN" "0,1" bitfld.long 0xC 14. "BOOTMODE,BOOTMODE" "0,1" bitfld.long 0xC 13. "DTHOLD,DTHOLD" "0,1" bitfld.long 0xC 12. "CPSMEN,CPSMEN" "0,1" bitfld.long 0xC 11. "WAITPEND,WAITPEND" "0,1" newline bitfld.long 0xC 10. "WAITINT,WAITINT" "0,1" bitfld.long 0xC 8.--9. "WAITRESP,WAITRESP" "0,1,2,3" bitfld.long 0xC 7. "CMDSTOP,CMDSTOP" "0,1" bitfld.long 0xC 6. "CMDTRANS,CMDTRANS" "0,1" hexmask.long.byte 0xC 0.--5. 1. "CMDINDEX,CMDINDEX" rgroup.long 0x10++0x13 line.long 0x0 "SDMMC_RESPCMDR,The SDMMC_RESPCMDR register contains the command index field of the last command response received. If the command response transmission does not contain the command index field (long or OCR response). the RESPCMD field is unknown..." hexmask.long.byte 0x0 0.--5. 1. "RESPCMD,RESPCMD" line.long 0x4 "SDMMC_RESP1R,The SDMMC_RESP1/2/3/4R registers contain the status of a card. which is part of the received response." hexmask.long 0x4 0.--31. 1. "CARDSTATUS1,CARDSTATUS1" line.long 0x8 "SDMMC_RESP2R,The SDMMC_RESP1/2/3/4R registers contain the status of a card. which is part of the received response." hexmask.long 0x8 0.--31. 1. "CARDSTATUS2,CARDSTATUS2" line.long 0xC "SDMMC_RESP3R,The SDMMC_RESP1/2/3/4R registers contain the status of a card. which is part of the received response." hexmask.long 0xC 0.--31. 1. "CARDSTATUS3,CARDSTATUS3" line.long 0x10 "SDMMC_RESP4R,The SDMMC_RESP1/2/3/4R registers contain the status of a card. which is part of the received response." hexmask.long 0x10 0.--31. 1. "CARDSTATUS4,CARDSTATUS4" group.long 0x24++0xB line.long 0x0 "SDMMC_DTIMER,The SDMMC_DTIMER register contains the data timeout period. in card bus clock periods. A counter loads the value from the SDMMC_DTIMER register. and starts decrementing when the data path state machine (DPSM) enters the Wait_R or Busy state." hexmask.long 0x0 0.--31. 1. "DATATIME,DATATIME" line.long 0x4 "SDMMC_DLENR,The SDMMC_DLENR register contains the number of data bytes to be transferred. The value is loaded into the data counter when data transfer starts." hexmask.long 0x4 0.--24. 1. "DATALENGTH,DATALENGTH" line.long 0x8 "SDMMC_DCTRL,The SDMMC_DCTRL register control the data path state machine (DPSM)." bitfld.long 0x8 13. "FIFORST,FIFORST" "0,1" bitfld.long 0x8 12. "BOOTACKEN,BOOTACKEN" "0,1" bitfld.long 0x8 11. "SDIOEN,SDIOEN" "0,1" bitfld.long 0x8 10. "RWMOD,RWMOD" "0,1" bitfld.long 0x8 9. "RWSTOP,RWSTOP" "0,1" bitfld.long 0x8 8. "RWSTART,RWSTART" "0,1" newline hexmask.long.byte 0x8 4.--7. 1. "DBLOCKSIZE,DBLOCKSIZE" bitfld.long 0x8 2.--3. "DTMODE,DTMODE" "0,1,2,3" bitfld.long 0x8 1. "DTDIR,DTDIR" "0,1" bitfld.long 0x8 0. "DTEN,DTEN" "0,1" rgroup.long 0x30++0x7 line.long 0x0 "SDMMC_DCNTR,The SDMMC_DCNTR register loads the value from the data length register (see SDMMC_DLENR) when the DPSM moves from the Idle state to the Wait_R or Wait_S state. As data is transferred. the counter decrements the value until it reaches 0. The.." hexmask.long 0x0 0.--24. 1. "DATACOUNT,DATACOUNT" line.long 0x4 "SDMMC_STAR,The SDMMC_STAR register is a read-only register. It contains two types of flag: Static flags (bits [28. 21. 11:0]): these bits remain asserted until they are cleared by writing to the SDMMC interrupt Clear register (see SDMMC_ICR) Dynamic.." bitfld.long 0x4 28. "IDMABTC,IDMABTC" "0,1" bitfld.long 0x4 27. "IDMATE,IDMATE" "0,1" bitfld.long 0x4 26. "CKSTOP,CKSTOP" "0,1" bitfld.long 0x4 25. "VSWEND,VSWEND" "0,1" bitfld.long 0x4 24. "ACKTIMEOUT,ACKTIMEOUT" "0,1" bitfld.long 0x4 23. "ACKFAIL,ACKFAIL" "0,1" newline bitfld.long 0x4 22. "SDIOIT,SDIOIT" "0,1" bitfld.long 0x4 21. "BUSYD0END,BUSYD0END" "0,1" bitfld.long 0x4 20. "BUSYD0,BUSYD0" "0,1" bitfld.long 0x4 19. "RXFIFOE,RXFIFOE" "0,1" bitfld.long 0x4 18. "TXFIFOE,TXFIFOE" "0,1" bitfld.long 0x4 17. "RXFIFOF,RXFIFOF" "0,1" newline bitfld.long 0x4 16. "TXFIFOF,TXFIFOF" "0,1" bitfld.long 0x4 15. "RXFIFOHF,RXFIFOHF" "0,1" bitfld.long 0x4 14. "TXFIFOHE,TXFIFOHE" "0,1" bitfld.long 0x4 13. "CPSMACT,CPSMACT" "0,1" bitfld.long 0x4 12. "DPSMACT,DPSMACT" "0,1" bitfld.long 0x4 11. "DABORT,DABORT" "0,1" newline bitfld.long 0x4 10. "DBCKEND,DBCKEND" "0,1" bitfld.long 0x4 9. "DHOLD,DHOLD" "0,1" bitfld.long 0x4 8. "DATAEND,DATAEND" "0,1" bitfld.long 0x4 7. "CMDSENT,CMDSENT" "0,1" bitfld.long 0x4 6. "CMDREND,CMDREND" "0,1" bitfld.long 0x4 5. "RXOVERR,RXOVERR" "0,1" newline bitfld.long 0x4 4. "TXUNDERR,TXUNDERR" "0,1" bitfld.long 0x4 3. "DTIMEOUT,DTIMEOUT" "0,1" bitfld.long 0x4 2. "CTIMEOUT,CTIMEOUT" "0,1" bitfld.long 0x4 1. "DCRCFAIL,DCRCFAIL" "0,1" bitfld.long 0x4 0. "CCRCFAIL,CCRCFAIL" "0,1" group.long 0x38++0xB line.long 0x0 "SDMMC_ICR,The SDMMC_ICR register is a write-only register. Writing a bit with 1 clears the corresponding bit in the SDMMC_STAR status register." bitfld.long 0x0 28. "IDMABTCC,IDMABTCC" "0,1" bitfld.long 0x0 27. "IDMATEC,IDMATEC" "0,1" bitfld.long 0x0 26. "CKSTOPC,CKSTOPC" "0,1" bitfld.long 0x0 25. "VSWENDC,VSWENDC" "0,1" bitfld.long 0x0 24. "ACKTIMEOUTC,ACKTIMEOUTC" "0,1" bitfld.long 0x0 23. "ACKFAILC,ACKFAILC" "0,1" newline bitfld.long 0x0 22. "SDIOITC,SDIOITC" "0,1" bitfld.long 0x0 21. "BUSYD0ENDC,BUSYD0ENDC" "0,1" bitfld.long 0x0 11. "DABORTC,DABORTC" "0,1" bitfld.long 0x0 10. "DBCKENDC,DBCKENDC" "0,1" bitfld.long 0x0 9. "DHOLDC,DHOLDC" "0,1" bitfld.long 0x0 8. "DATAENDC,DATAENDC" "0,1" newline bitfld.long 0x0 7. "CMDSENTC,CMDSENTC" "0,1" bitfld.long 0x0 6. "CMDRENDC,CMDRENDC" "0,1" bitfld.long 0x0 5. "RXOVERRC,RXOVERRC" "0,1" bitfld.long 0x0 4. "TXUNDERRC,TXUNDERRC" "0,1" bitfld.long 0x0 3. "DTIMEOUTC,DTIMEOUTC" "0,1" bitfld.long 0x0 2. "CTIMEOUTC,CTIMEOUTC" "0,1" newline bitfld.long 0x0 1. "DCRCFAILC,DCRCFAILC" "0,1" bitfld.long 0x0 0. "CCRCFAILC,CCRCFAILC" "0,1" line.long 0x4 "SDMMC_MASKR,The interrupt mask register determines which status flags generate an interrupt request by setting the corresponding bit to 1." bitfld.long 0x4 28. "IDMABTCIE,IDMABTCIE" "0,1" bitfld.long 0x4 26. "CKSTOPIE,CKSTOPIE" "0,1" bitfld.long 0x4 25. "VSWENDIE,VSWENDIE" "0,1" bitfld.long 0x4 24. "ACKTIMEOUTIE,ACKTIMEOUTIE" "0,1" bitfld.long 0x4 23. "ACKFAILIE,ACKFAILIE" "0,1" bitfld.long 0x4 22. "SDIOITIE,SDIOITIE" "0,1" newline bitfld.long 0x4 21. "BUSYD0ENDIE,BUSYD0ENDIE" "0,1" bitfld.long 0x4 18. "TXFIFOEIE,TXFIFOEIE" "0,1" bitfld.long 0x4 17. "RXFIFOFIE,RXFIFOFIE" "0,1" bitfld.long 0x4 15. "RXFIFOHFIE,RXFIFOHFIE" "0,1" bitfld.long 0x4 14. "TXFIFOHEIE,TXFIFOHEIE" "0,1" bitfld.long 0x4 11. "DABORTIE,DABORTIE" "0,1" newline bitfld.long 0x4 10. "DBCKENDIE,DBCKENDIE" "0,1" bitfld.long 0x4 9. "DHOLDIE,DHOLDIE" "0,1" bitfld.long 0x4 8. "DATAENDIE,DATAENDIE" "0,1" bitfld.long 0x4 7. "CMDSENTIE,CMDSENTIE" "0,1" bitfld.long 0x4 6. "CMDRENDIE,CMDRENDIE" "0,1" bitfld.long 0x4 5. "RXOVERRIE,RXOVERRIE" "0,1" newline bitfld.long 0x4 4. "TXUNDERRIE,TXUNDERRIE" "0,1" bitfld.long 0x4 3. "DTIMEOUTIE,DTIMEOUTIE" "0,1" bitfld.long 0x4 2. "CTIMEOUTIE,CTIMEOUTIE" "0,1" bitfld.long 0x4 1. "DCRCFAILIE,DCRCFAILIE" "0,1" bitfld.long 0x4 0. "CCRCFAILIE,CCRCFAILIE" "0,1" line.long 0x8 "SDMMC_ACKTIMER,The SDMMC_ACKTIMER register contains the acknowledgment timeout period. in SDMMC_CK bus clock periods. A counter loads the value from the SDMMC_ACKTIMER register. and starts decrementing when the data path state machine (DPSM) enters the.." hexmask.long 0x8 0.--24. 1. "ACKTIME,ACKTIME" group.long 0x50++0xB line.long 0x0 "SDMMC_IDMACTRLR,The receive and transmit FIFOs can be read or written as 32-bit wide registers. The FIFOs contain 32 entries on 32 sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO." bitfld.long 0x0 1. "IDMABMODE,IDMABMODE" "0,1" bitfld.long 0x0 0. "IDMAEN,IDMAEN" "0,1" line.long 0x4 "SDMMC_IDMABSIZER,The SDMMC_IDMABSIZER register contains the buffer size when in linked list configuration." hexmask.long.word 0x4 5.--16. 1. "IDMABNDT,IDMABNDT" line.long 0x8 "SDMMC_IDMABASER,The SDMMC_IDMABASER register contains the memory buffer base address in single buffer configuration and linked list configuration." hexmask.long 0x8 0.--31. 1. "IDMABASE,IDMABASE" group.long 0x64++0x7 line.long 0x0 "SDMMC_IDMALAR,SDMMC IDMA linked list address register" bitfld.long 0x0 31. "ULA,ULA" "0,1" bitfld.long 0x0 30. "ULS,ULS" "0,1" bitfld.long 0x0 29. "ABR,ABR" "0,1" hexmask.long.word 0x0 2.--15. 1. "IDMALA,IDMALA" line.long 0x4 "SDMMC_IDMABAR,SDMMC IDMA linked list memory base register" hexmask.long 0x4 2.--31. 1. "IDMABA,IDMABA" group.long 0x80++0x3F line.long 0x0 "SDMMC_FIFOR0,The receive and transmit FIFOs can be only read or written as word (32-bit) wide registers. The FIFOs contain 16 entries on sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO." hexmask.long 0x0 0.--31. 1. "FIFODATA,FIFODATA" line.long 0x4 "SDMMC_FIFOR1,The receive and transmit FIFOs can be only read or written as word (32-bit) wide registers. The FIFOs contain 16 entries on sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO." hexmask.long 0x4 0.--31. 1. "FIFODATA,FIFODATA" line.long 0x8 "SDMMC_FIFOR2,The receive and transmit FIFOs can be only read or written as word (32-bit) wide registers. The FIFOs contain 16 entries on sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO." hexmask.long 0x8 0.--31. 1. "FIFODATA,FIFODATA" line.long 0xC "SDMMC_FIFOR3,The receive and transmit FIFOs can be only read or written as word (32-bit) wide registers. The FIFOs contain 16 entries on sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO." hexmask.long 0xC 0.--31. 1. "FIFODATA,FIFODATA" line.long 0x10 "SDMMC_FIFOR4,The receive and transmit FIFOs can be only read or written as word (32-bit) wide registers. The FIFOs contain 16 entries on sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO." hexmask.long 0x10 0.--31. 1. "FIFODATA,FIFODATA" line.long 0x14 "SDMMC_FIFOR5,The receive and transmit FIFOs can be only read or written as word (32-bit) wide registers. The FIFOs contain 16 entries on sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO." hexmask.long 0x14 0.--31. 1. "FIFODATA,FIFODATA" line.long 0x18 "SDMMC_FIFOR6,The receive and transmit FIFOs can be only read or written as word (32-bit) wide registers. The FIFOs contain 16 entries on sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO." hexmask.long 0x18 0.--31. 1. "FIFODATA,FIFODATA" line.long 0x1C "SDMMC_FIFOR7,The receive and transmit FIFOs can be only read or written as word (32-bit) wide registers. The FIFOs contain 16 entries on sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO." hexmask.long 0x1C 0.--31. 1. "FIFODATA,FIFODATA" line.long 0x20 "SDMMC_FIFOR8,The receive and transmit FIFOs can be only read or written as word (32-bit) wide registers. The FIFOs contain 16 entries on sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO." hexmask.long 0x20 0.--31. 1. "FIFODATA,FIFODATA" line.long 0x24 "SDMMC_FIFOR9,The receive and transmit FIFOs can be only read or written as word (32-bit) wide registers. The FIFOs contain 16 entries on sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO." hexmask.long 0x24 0.--31. 1. "FIFODATA,FIFODATA" line.long 0x28 "SDMMC_FIFOR10,The receive and transmit FIFOs can be only read or written as word (32-bit) wide registers. The FIFOs contain 16 entries on sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the.." hexmask.long 0x28 0.--31. 1. "FIFODATA,FIFODATA" line.long 0x2C "SDMMC_FIFOR11,The receive and transmit FIFOs can be only read or written as word (32-bit) wide registers. The FIFOs contain 16 entries on sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the.." hexmask.long 0x2C 0.--31. 1. "FIFODATA,FIFODATA" line.long 0x30 "SDMMC_FIFOR12,The receive and transmit FIFOs can be only read or written as word (32-bit) wide registers. The FIFOs contain 16 entries on sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the.." hexmask.long 0x30 0.--31. 1. "FIFODATA,FIFODATA" line.long 0x34 "SDMMC_FIFOR13,The receive and transmit FIFOs can be only read or written as word (32-bit) wide registers. The FIFOs contain 16 entries on sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the.." hexmask.long 0x34 0.--31. 1. "FIFODATA,FIFODATA" line.long 0x38 "SDMMC_FIFOR14,The receive and transmit FIFOs can be only read or written as word (32-bit) wide registers. The FIFOs contain 16 entries on sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the.." hexmask.long 0x38 0.--31. 1. "FIFODATA,FIFODATA" line.long 0x3C "SDMMC_FIFOR15,The receive and transmit FIFOs can be only read or written as word (32-bit) wide registers. The FIFOs contain 16 entries on sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the.." hexmask.long 0x3C 0.--31. 1. "FIFODATA,FIFODATA" rgroup.long 0x3F4++0xB line.long 0x0 "SDMMC_VERR,SDMMC version register" hexmask.long.byte 0x0 4.--7. 1. "MAJREV,MAJREV" hexmask.long.byte 0x0 0.--3. 1. "MINREV,MINREV" line.long 0x4 "SDMMC_IPIDR,SDMMC identification register" hexmask.long 0x4 0.--31. 1. "IP_ID,IP_ID" line.long 0x8 "SDMMC_SIDR,SDMMC size ID register" hexmask.long 0x8 0.--31. 1. "SID,SID" tree.end tree "SDMMC2" base ad:0x58007000 group.long 0x0++0xF line.long 0x0 "SDMMC_POWER,SDMMC power control register" bitfld.long 0x0 4. "DIRPOL,DIRPOL" "0,1" bitfld.long 0x0 3. "VSWITCHEN,VSWITCHEN" "0,1" bitfld.long 0x0 2. "VSWITCH,VSWITCH" "0,1" bitfld.long 0x0 0.--1. "PWRCTRL,PWRCTRL" "0,1,2,3" line.long 0x4 "SDMMC_CLKCR,The SDMMC_CLKCR register controls the SDMMC_CK output clock. the sdmmc_rx_ck receive clock. and the bus width." bitfld.long 0x4 20.--21. "SELCLKRX,SELCLKRX" "0,1,2,3" bitfld.long 0x4 19. "BUSSPEED,BUSSPEED" "0,1" bitfld.long 0x4 18. "DDR,DDR" "0,1" bitfld.long 0x4 17. "HWFC_EN,HWFC_EN" "0,1" bitfld.long 0x4 16. "NEGEDGE,NEGEDGE" "0,1" bitfld.long 0x4 14.--15. "WIDBUS,WIDBUS" "0,1,2,3" newline bitfld.long 0x4 12. "PWRSAV,PWRSAV" "0,1" hexmask.long.word 0x4 0.--9. 1. "CLKDIV,CLKDIV" line.long 0x8 "SDMMC_ARGR,The SDMMC_ARGR register contains a 32-bit command argument. which is sent to a card as part of a command message." hexmask.long 0x8 0.--31. 1. "CMDARG,CMDARG" line.long 0xC "SDMMC_CMDR,The SDMMC_CMDR register contains the command index and command type bits. The command index is sent to a card as part of a command message. The command type bits control the command path state machine (CPSM)." bitfld.long 0xC 16. "CMDSUSPEND,CMDSUSPEND" "0,1" bitfld.long 0xC 15. "BOOTEN,BOOTEN" "0,1" bitfld.long 0xC 14. "BOOTMODE,BOOTMODE" "0,1" bitfld.long 0xC 13. "DTHOLD,DTHOLD" "0,1" bitfld.long 0xC 12. "CPSMEN,CPSMEN" "0,1" bitfld.long 0xC 11. "WAITPEND,WAITPEND" "0,1" newline bitfld.long 0xC 10. "WAITINT,WAITINT" "0,1" bitfld.long 0xC 8.--9. "WAITRESP,WAITRESP" "0,1,2,3" bitfld.long 0xC 7. "CMDSTOP,CMDSTOP" "0,1" bitfld.long 0xC 6. "CMDTRANS,CMDTRANS" "0,1" hexmask.long.byte 0xC 0.--5. 1. "CMDINDEX,CMDINDEX" rgroup.long 0x10++0x13 line.long 0x0 "SDMMC_RESPCMDR,The SDMMC_RESPCMDR register contains the command index field of the last command response received. If the command response transmission does not contain the command index field (long or OCR response). the RESPCMD field is unknown..." hexmask.long.byte 0x0 0.--5. 1. "RESPCMD,RESPCMD" line.long 0x4 "SDMMC_RESP1R,The SDMMC_RESP1/2/3/4R registers contain the status of a card. which is part of the received response." hexmask.long 0x4 0.--31. 1. "CARDSTATUS1,CARDSTATUS1" line.long 0x8 "SDMMC_RESP2R,The SDMMC_RESP1/2/3/4R registers contain the status of a card. which is part of the received response." hexmask.long 0x8 0.--31. 1. "CARDSTATUS2,CARDSTATUS2" line.long 0xC "SDMMC_RESP3R,The SDMMC_RESP1/2/3/4R registers contain the status of a card. which is part of the received response." hexmask.long 0xC 0.--31. 1. "CARDSTATUS3,CARDSTATUS3" line.long 0x10 "SDMMC_RESP4R,The SDMMC_RESP1/2/3/4R registers contain the status of a card. which is part of the received response." hexmask.long 0x10 0.--31. 1. "CARDSTATUS4,CARDSTATUS4" group.long 0x24++0xB line.long 0x0 "SDMMC_DTIMER,The SDMMC_DTIMER register contains the data timeout period. in card bus clock periods. A counter loads the value from the SDMMC_DTIMER register. and starts decrementing when the data path state machine (DPSM) enters the Wait_R or Busy state." hexmask.long 0x0 0.--31. 1. "DATATIME,DATATIME" line.long 0x4 "SDMMC_DLENR,The SDMMC_DLENR register contains the number of data bytes to be transferred. The value is loaded into the data counter when data transfer starts." hexmask.long 0x4 0.--24. 1. "DATALENGTH,DATALENGTH" line.long 0x8 "SDMMC_DCTRL,The SDMMC_DCTRL register control the data path state machine (DPSM)." bitfld.long 0x8 13. "FIFORST,FIFORST" "0,1" bitfld.long 0x8 12. "BOOTACKEN,BOOTACKEN" "0,1" bitfld.long 0x8 11. "SDIOEN,SDIOEN" "0,1" bitfld.long 0x8 10. "RWMOD,RWMOD" "0,1" bitfld.long 0x8 9. "RWSTOP,RWSTOP" "0,1" bitfld.long 0x8 8. "RWSTART,RWSTART" "0,1" newline hexmask.long.byte 0x8 4.--7. 1. "DBLOCKSIZE,DBLOCKSIZE" bitfld.long 0x8 2.--3. "DTMODE,DTMODE" "0,1,2,3" bitfld.long 0x8 1. "DTDIR,DTDIR" "0,1" bitfld.long 0x8 0. "DTEN,DTEN" "0,1" rgroup.long 0x30++0x7 line.long 0x0 "SDMMC_DCNTR,The SDMMC_DCNTR register loads the value from the data length register (see SDMMC_DLENR) when the DPSM moves from the Idle state to the Wait_R or Wait_S state. As data is transferred. the counter decrements the value until it reaches 0. The.." hexmask.long 0x0 0.--24. 1. "DATACOUNT,DATACOUNT" line.long 0x4 "SDMMC_STAR,The SDMMC_STAR register is a read-only register. It contains two types of flag: Static flags (bits [28. 21. 11:0]): these bits remain asserted until they are cleared by writing to the SDMMC interrupt Clear register (see SDMMC_ICR) Dynamic.." bitfld.long 0x4 28. "IDMABTC,IDMABTC" "0,1" bitfld.long 0x4 27. "IDMATE,IDMATE" "0,1" bitfld.long 0x4 26. "CKSTOP,CKSTOP" "0,1" bitfld.long 0x4 25. "VSWEND,VSWEND" "0,1" bitfld.long 0x4 24. "ACKTIMEOUT,ACKTIMEOUT" "0,1" bitfld.long 0x4 23. "ACKFAIL,ACKFAIL" "0,1" newline bitfld.long 0x4 22. "SDIOIT,SDIOIT" "0,1" bitfld.long 0x4 21. "BUSYD0END,BUSYD0END" "0,1" bitfld.long 0x4 20. "BUSYD0,BUSYD0" "0,1" bitfld.long 0x4 19. "RXFIFOE,RXFIFOE" "0,1" bitfld.long 0x4 18. "TXFIFOE,TXFIFOE" "0,1" bitfld.long 0x4 17. "RXFIFOF,RXFIFOF" "0,1" newline bitfld.long 0x4 16. "TXFIFOF,TXFIFOF" "0,1" bitfld.long 0x4 15. "RXFIFOHF,RXFIFOHF" "0,1" bitfld.long 0x4 14. "TXFIFOHE,TXFIFOHE" "0,1" bitfld.long 0x4 13. "CPSMACT,CPSMACT" "0,1" bitfld.long 0x4 12. "DPSMACT,DPSMACT" "0,1" bitfld.long 0x4 11. "DABORT,DABORT" "0,1" newline bitfld.long 0x4 10. "DBCKEND,DBCKEND" "0,1" bitfld.long 0x4 9. "DHOLD,DHOLD" "0,1" bitfld.long 0x4 8. "DATAEND,DATAEND" "0,1" bitfld.long 0x4 7. "CMDSENT,CMDSENT" "0,1" bitfld.long 0x4 6. "CMDREND,CMDREND" "0,1" bitfld.long 0x4 5. "RXOVERR,RXOVERR" "0,1" newline bitfld.long 0x4 4. "TXUNDERR,TXUNDERR" "0,1" bitfld.long 0x4 3. "DTIMEOUT,DTIMEOUT" "0,1" bitfld.long 0x4 2. "CTIMEOUT,CTIMEOUT" "0,1" bitfld.long 0x4 1. "DCRCFAIL,DCRCFAIL" "0,1" bitfld.long 0x4 0. "CCRCFAIL,CCRCFAIL" "0,1" group.long 0x38++0xB line.long 0x0 "SDMMC_ICR,The SDMMC_ICR register is a write-only register. Writing a bit with 1 clears the corresponding bit in the SDMMC_STAR status register." bitfld.long 0x0 28. "IDMABTCC,IDMABTCC" "0,1" bitfld.long 0x0 27. "IDMATEC,IDMATEC" "0,1" bitfld.long 0x0 26. "CKSTOPC,CKSTOPC" "0,1" bitfld.long 0x0 25. "VSWENDC,VSWENDC" "0,1" bitfld.long 0x0 24. "ACKTIMEOUTC,ACKTIMEOUTC" "0,1" bitfld.long 0x0 23. "ACKFAILC,ACKFAILC" "0,1" newline bitfld.long 0x0 22. "SDIOITC,SDIOITC" "0,1" bitfld.long 0x0 21. "BUSYD0ENDC,BUSYD0ENDC" "0,1" bitfld.long 0x0 11. "DABORTC,DABORTC" "0,1" bitfld.long 0x0 10. "DBCKENDC,DBCKENDC" "0,1" bitfld.long 0x0 9. "DHOLDC,DHOLDC" "0,1" bitfld.long 0x0 8. "DATAENDC,DATAENDC" "0,1" newline bitfld.long 0x0 7. "CMDSENTC,CMDSENTC" "0,1" bitfld.long 0x0 6. "CMDRENDC,CMDRENDC" "0,1" bitfld.long 0x0 5. "RXOVERRC,RXOVERRC" "0,1" bitfld.long 0x0 4. "TXUNDERRC,TXUNDERRC" "0,1" bitfld.long 0x0 3. "DTIMEOUTC,DTIMEOUTC" "0,1" bitfld.long 0x0 2. "CTIMEOUTC,CTIMEOUTC" "0,1" newline bitfld.long 0x0 1. "DCRCFAILC,DCRCFAILC" "0,1" bitfld.long 0x0 0. "CCRCFAILC,CCRCFAILC" "0,1" line.long 0x4 "SDMMC_MASKR,The interrupt mask register determines which status flags generate an interrupt request by setting the corresponding bit to 1." bitfld.long 0x4 28. "IDMABTCIE,IDMABTCIE" "0,1" bitfld.long 0x4 26. "CKSTOPIE,CKSTOPIE" "0,1" bitfld.long 0x4 25. "VSWENDIE,VSWENDIE" "0,1" bitfld.long 0x4 24. "ACKTIMEOUTIE,ACKTIMEOUTIE" "0,1" bitfld.long 0x4 23. "ACKFAILIE,ACKFAILIE" "0,1" bitfld.long 0x4 22. "SDIOITIE,SDIOITIE" "0,1" newline bitfld.long 0x4 21. "BUSYD0ENDIE,BUSYD0ENDIE" "0,1" bitfld.long 0x4 18. "TXFIFOEIE,TXFIFOEIE" "0,1" bitfld.long 0x4 17. "RXFIFOFIE,RXFIFOFIE" "0,1" bitfld.long 0x4 15. "RXFIFOHFIE,RXFIFOHFIE" "0,1" bitfld.long 0x4 14. "TXFIFOHEIE,TXFIFOHEIE" "0,1" bitfld.long 0x4 11. "DABORTIE,DABORTIE" "0,1" newline bitfld.long 0x4 10. "DBCKENDIE,DBCKENDIE" "0,1" bitfld.long 0x4 9. "DHOLDIE,DHOLDIE" "0,1" bitfld.long 0x4 8. "DATAENDIE,DATAENDIE" "0,1" bitfld.long 0x4 7. "CMDSENTIE,CMDSENTIE" "0,1" bitfld.long 0x4 6. "CMDRENDIE,CMDRENDIE" "0,1" bitfld.long 0x4 5. "RXOVERRIE,RXOVERRIE" "0,1" newline bitfld.long 0x4 4. "TXUNDERRIE,TXUNDERRIE" "0,1" bitfld.long 0x4 3. "DTIMEOUTIE,DTIMEOUTIE" "0,1" bitfld.long 0x4 2. "CTIMEOUTIE,CTIMEOUTIE" "0,1" bitfld.long 0x4 1. "DCRCFAILIE,DCRCFAILIE" "0,1" bitfld.long 0x4 0. "CCRCFAILIE,CCRCFAILIE" "0,1" line.long 0x8 "SDMMC_ACKTIMER,The SDMMC_ACKTIMER register contains the acknowledgment timeout period. in SDMMC_CK bus clock periods. A counter loads the value from the SDMMC_ACKTIMER register. and starts decrementing when the data path state machine (DPSM) enters the.." hexmask.long 0x8 0.--24. 1. "ACKTIME,ACKTIME" group.long 0x50++0xB line.long 0x0 "SDMMC_IDMACTRLR,The receive and transmit FIFOs can be read or written as 32-bit wide registers. The FIFOs contain 32 entries on 32 sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO." bitfld.long 0x0 1. "IDMABMODE,IDMABMODE" "0,1" bitfld.long 0x0 0. "IDMAEN,IDMAEN" "0,1" line.long 0x4 "SDMMC_IDMABSIZER,The SDMMC_IDMABSIZER register contains the buffer size when in linked list configuration." hexmask.long.word 0x4 5.--16. 1. "IDMABNDT,IDMABNDT" line.long 0x8 "SDMMC_IDMABASER,The SDMMC_IDMABASER register contains the memory buffer base address in single buffer configuration and linked list configuration." hexmask.long 0x8 0.--31. 1. "IDMABASE,IDMABASE" group.long 0x64++0x7 line.long 0x0 "SDMMC_IDMALAR,SDMMC IDMA linked list address register" bitfld.long 0x0 31. "ULA,ULA" "0,1" bitfld.long 0x0 30. "ULS,ULS" "0,1" bitfld.long 0x0 29. "ABR,ABR" "0,1" hexmask.long.word 0x0 2.--15. 1. "IDMALA,IDMALA" line.long 0x4 "SDMMC_IDMABAR,SDMMC IDMA linked list memory base register" hexmask.long 0x4 2.--31. 1. "IDMABA,IDMABA" group.long 0x80++0x3F line.long 0x0 "SDMMC_FIFOR0,The receive and transmit FIFOs can be only read or written as word (32-bit) wide registers. The FIFOs contain 16 entries on sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO." hexmask.long 0x0 0.--31. 1. "FIFODATA,FIFODATA" line.long 0x4 "SDMMC_FIFOR1,The receive and transmit FIFOs can be only read or written as word (32-bit) wide registers. The FIFOs contain 16 entries on sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO." hexmask.long 0x4 0.--31. 1. "FIFODATA,FIFODATA" line.long 0x8 "SDMMC_FIFOR2,The receive and transmit FIFOs can be only read or written as word (32-bit) wide registers. The FIFOs contain 16 entries on sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO." hexmask.long 0x8 0.--31. 1. "FIFODATA,FIFODATA" line.long 0xC "SDMMC_FIFOR3,The receive and transmit FIFOs can be only read or written as word (32-bit) wide registers. The FIFOs contain 16 entries on sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO." hexmask.long 0xC 0.--31. 1. "FIFODATA,FIFODATA" line.long 0x10 "SDMMC_FIFOR4,The receive and transmit FIFOs can be only read or written as word (32-bit) wide registers. The FIFOs contain 16 entries on sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO." hexmask.long 0x10 0.--31. 1. "FIFODATA,FIFODATA" line.long 0x14 "SDMMC_FIFOR5,The receive and transmit FIFOs can be only read or written as word (32-bit) wide registers. The FIFOs contain 16 entries on sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO." hexmask.long 0x14 0.--31. 1. "FIFODATA,FIFODATA" line.long 0x18 "SDMMC_FIFOR6,The receive and transmit FIFOs can be only read or written as word (32-bit) wide registers. The FIFOs contain 16 entries on sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO." hexmask.long 0x18 0.--31. 1. "FIFODATA,FIFODATA" line.long 0x1C "SDMMC_FIFOR7,The receive and transmit FIFOs can be only read or written as word (32-bit) wide registers. The FIFOs contain 16 entries on sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO." hexmask.long 0x1C 0.--31. 1. "FIFODATA,FIFODATA" line.long 0x20 "SDMMC_FIFOR8,The receive and transmit FIFOs can be only read or written as word (32-bit) wide registers. The FIFOs contain 16 entries on sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO." hexmask.long 0x20 0.--31. 1. "FIFODATA,FIFODATA" line.long 0x24 "SDMMC_FIFOR9,The receive and transmit FIFOs can be only read or written as word (32-bit) wide registers. The FIFOs contain 16 entries on sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO." hexmask.long 0x24 0.--31. 1. "FIFODATA,FIFODATA" line.long 0x28 "SDMMC_FIFOR10,The receive and transmit FIFOs can be only read or written as word (32-bit) wide registers. The FIFOs contain 16 entries on sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the.." hexmask.long 0x28 0.--31. 1. "FIFODATA,FIFODATA" line.long 0x2C "SDMMC_FIFOR11,The receive and transmit FIFOs can be only read or written as word (32-bit) wide registers. The FIFOs contain 16 entries on sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the.." hexmask.long 0x2C 0.--31. 1. "FIFODATA,FIFODATA" line.long 0x30 "SDMMC_FIFOR12,The receive and transmit FIFOs can be only read or written as word (32-bit) wide registers. The FIFOs contain 16 entries on sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the.." hexmask.long 0x30 0.--31. 1. "FIFODATA,FIFODATA" line.long 0x34 "SDMMC_FIFOR13,The receive and transmit FIFOs can be only read or written as word (32-bit) wide registers. The FIFOs contain 16 entries on sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the.." hexmask.long 0x34 0.--31. 1. "FIFODATA,FIFODATA" line.long 0x38 "SDMMC_FIFOR14,The receive and transmit FIFOs can be only read or written as word (32-bit) wide registers. The FIFOs contain 16 entries on sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the.." hexmask.long 0x38 0.--31. 1. "FIFODATA,FIFODATA" line.long 0x3C "SDMMC_FIFOR15,The receive and transmit FIFOs can be only read or written as word (32-bit) wide registers. The FIFOs contain 16 entries on sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the.." hexmask.long 0x3C 0.--31. 1. "FIFODATA,FIFODATA" rgroup.long 0x3F4++0xB line.long 0x0 "SDMMC_VERR,SDMMC version register" hexmask.long.byte 0x0 4.--7. 1. "MAJREV,MAJREV" hexmask.long.byte 0x0 0.--3. 1. "MINREV,MINREV" line.long 0x4 "SDMMC_IPIDR,SDMMC identification register" hexmask.long 0x4 0.--31. 1. "IP_ID,IP_ID" line.long 0x8 "SDMMC_SIDR,SDMMC size ID register" hexmask.long 0x8 0.--31. 1. "SID,SID" tree.end tree "SDMMC3" base ad:0x48004000 group.long 0x0++0xF line.long 0x0 "SDMMC_POWER,SDMMC power control register" bitfld.long 0x0 4. "DIRPOL,DIRPOL" "0,1" bitfld.long 0x0 3. "VSWITCHEN,VSWITCHEN" "0,1" bitfld.long 0x0 2. "VSWITCH,VSWITCH" "0,1" bitfld.long 0x0 0.--1. "PWRCTRL,PWRCTRL" "0,1,2,3" line.long 0x4 "SDMMC_CLKCR,The SDMMC_CLKCR register controls the SDMMC_CK output clock. the sdmmc_rx_ck receive clock. and the bus width." bitfld.long 0x4 20.--21. "SELCLKRX,SELCLKRX" "0,1,2,3" bitfld.long 0x4 19. "BUSSPEED,BUSSPEED" "0,1" bitfld.long 0x4 18. "DDR,DDR" "0,1" bitfld.long 0x4 17. "HWFC_EN,HWFC_EN" "0,1" bitfld.long 0x4 16. "NEGEDGE,NEGEDGE" "0,1" bitfld.long 0x4 14.--15. "WIDBUS,WIDBUS" "0,1,2,3" newline bitfld.long 0x4 12. "PWRSAV,PWRSAV" "0,1" hexmask.long.word 0x4 0.--9. 1. "CLKDIV,CLKDIV" line.long 0x8 "SDMMC_ARGR,The SDMMC_ARGR register contains a 32-bit command argument. which is sent to a card as part of a command message." hexmask.long 0x8 0.--31. 1. "CMDARG,CMDARG" line.long 0xC "SDMMC_CMDR,The SDMMC_CMDR register contains the command index and command type bits. The command index is sent to a card as part of a command message. The command type bits control the command path state machine (CPSM)." bitfld.long 0xC 16. "CMDSUSPEND,CMDSUSPEND" "0,1" bitfld.long 0xC 15. "BOOTEN,BOOTEN" "0,1" bitfld.long 0xC 14. "BOOTMODE,BOOTMODE" "0,1" bitfld.long 0xC 13. "DTHOLD,DTHOLD" "0,1" bitfld.long 0xC 12. "CPSMEN,CPSMEN" "0,1" bitfld.long 0xC 11. "WAITPEND,WAITPEND" "0,1" newline bitfld.long 0xC 10. "WAITINT,WAITINT" "0,1" bitfld.long 0xC 8.--9. "WAITRESP,WAITRESP" "0,1,2,3" bitfld.long 0xC 7. "CMDSTOP,CMDSTOP" "0,1" bitfld.long 0xC 6. "CMDTRANS,CMDTRANS" "0,1" hexmask.long.byte 0xC 0.--5. 1. "CMDINDEX,CMDINDEX" rgroup.long 0x10++0x13 line.long 0x0 "SDMMC_RESPCMDR,The SDMMC_RESPCMDR register contains the command index field of the last command response received. If the command response transmission does not contain the command index field (long or OCR response). the RESPCMD field is unknown..." hexmask.long.byte 0x0 0.--5. 1. "RESPCMD,RESPCMD" line.long 0x4 "SDMMC_RESP1R,The SDMMC_RESP1/2/3/4R registers contain the status of a card. which is part of the received response." hexmask.long 0x4 0.--31. 1. "CARDSTATUS1,CARDSTATUS1" line.long 0x8 "SDMMC_RESP2R,The SDMMC_RESP1/2/3/4R registers contain the status of a card. which is part of the received response." hexmask.long 0x8 0.--31. 1. "CARDSTATUS2,CARDSTATUS2" line.long 0xC "SDMMC_RESP3R,The SDMMC_RESP1/2/3/4R registers contain the status of a card. which is part of the received response." hexmask.long 0xC 0.--31. 1. "CARDSTATUS3,CARDSTATUS3" line.long 0x10 "SDMMC_RESP4R,The SDMMC_RESP1/2/3/4R registers contain the status of a card. which is part of the received response." hexmask.long 0x10 0.--31. 1. "CARDSTATUS4,CARDSTATUS4" group.long 0x24++0xB line.long 0x0 "SDMMC_DTIMER,The SDMMC_DTIMER register contains the data timeout period. in card bus clock periods. A counter loads the value from the SDMMC_DTIMER register. and starts decrementing when the data path state machine (DPSM) enters the Wait_R or Busy state." hexmask.long 0x0 0.--31. 1. "DATATIME,DATATIME" line.long 0x4 "SDMMC_DLENR,The SDMMC_DLENR register contains the number of data bytes to be transferred. The value is loaded into the data counter when data transfer starts." hexmask.long 0x4 0.--24. 1. "DATALENGTH,DATALENGTH" line.long 0x8 "SDMMC_DCTRL,The SDMMC_DCTRL register control the data path state machine (DPSM)." bitfld.long 0x8 13. "FIFORST,FIFORST" "0,1" bitfld.long 0x8 12. "BOOTACKEN,BOOTACKEN" "0,1" bitfld.long 0x8 11. "SDIOEN,SDIOEN" "0,1" bitfld.long 0x8 10. "RWMOD,RWMOD" "0,1" bitfld.long 0x8 9. "RWSTOP,RWSTOP" "0,1" bitfld.long 0x8 8. "RWSTART,RWSTART" "0,1" newline hexmask.long.byte 0x8 4.--7. 1. "DBLOCKSIZE,DBLOCKSIZE" bitfld.long 0x8 2.--3. "DTMODE,DTMODE" "0,1,2,3" bitfld.long 0x8 1. "DTDIR,DTDIR" "0,1" bitfld.long 0x8 0. "DTEN,DTEN" "0,1" rgroup.long 0x30++0x7 line.long 0x0 "SDMMC_DCNTR,The SDMMC_DCNTR register loads the value from the data length register (see SDMMC_DLENR) when the DPSM moves from the Idle state to the Wait_R or Wait_S state. As data is transferred. the counter decrements the value until it reaches 0. The.." hexmask.long 0x0 0.--24. 1. "DATACOUNT,DATACOUNT" line.long 0x4 "SDMMC_STAR,The SDMMC_STAR register is a read-only register. It contains two types of flag: Static flags (bits [28. 21. 11:0]): these bits remain asserted until they are cleared by writing to the SDMMC interrupt Clear register (see SDMMC_ICR) Dynamic.." bitfld.long 0x4 28. "IDMABTC,IDMABTC" "0,1" bitfld.long 0x4 27. "IDMATE,IDMATE" "0,1" bitfld.long 0x4 26. "CKSTOP,CKSTOP" "0,1" bitfld.long 0x4 25. "VSWEND,VSWEND" "0,1" bitfld.long 0x4 24. "ACKTIMEOUT,ACKTIMEOUT" "0,1" bitfld.long 0x4 23. "ACKFAIL,ACKFAIL" "0,1" newline bitfld.long 0x4 22. "SDIOIT,SDIOIT" "0,1" bitfld.long 0x4 21. "BUSYD0END,BUSYD0END" "0,1" bitfld.long 0x4 20. "BUSYD0,BUSYD0" "0,1" bitfld.long 0x4 19. "RXFIFOE,RXFIFOE" "0,1" bitfld.long 0x4 18. "TXFIFOE,TXFIFOE" "0,1" bitfld.long 0x4 17. "RXFIFOF,RXFIFOF" "0,1" newline bitfld.long 0x4 16. "TXFIFOF,TXFIFOF" "0,1" bitfld.long 0x4 15. "RXFIFOHF,RXFIFOHF" "0,1" bitfld.long 0x4 14. "TXFIFOHE,TXFIFOHE" "0,1" bitfld.long 0x4 13. "CPSMACT,CPSMACT" "0,1" bitfld.long 0x4 12. "DPSMACT,DPSMACT" "0,1" bitfld.long 0x4 11. "DABORT,DABORT" "0,1" newline bitfld.long 0x4 10. "DBCKEND,DBCKEND" "0,1" bitfld.long 0x4 9. "DHOLD,DHOLD" "0,1" bitfld.long 0x4 8. "DATAEND,DATAEND" "0,1" bitfld.long 0x4 7. "CMDSENT,CMDSENT" "0,1" bitfld.long 0x4 6. "CMDREND,CMDREND" "0,1" bitfld.long 0x4 5. "RXOVERR,RXOVERR" "0,1" newline bitfld.long 0x4 4. "TXUNDERR,TXUNDERR" "0,1" bitfld.long 0x4 3. "DTIMEOUT,DTIMEOUT" "0,1" bitfld.long 0x4 2. "CTIMEOUT,CTIMEOUT" "0,1" bitfld.long 0x4 1. "DCRCFAIL,DCRCFAIL" "0,1" bitfld.long 0x4 0. "CCRCFAIL,CCRCFAIL" "0,1" group.long 0x38++0xB line.long 0x0 "SDMMC_ICR,The SDMMC_ICR register is a write-only register. Writing a bit with 1 clears the corresponding bit in the SDMMC_STAR status register." bitfld.long 0x0 28. "IDMABTCC,IDMABTCC" "0,1" bitfld.long 0x0 27. "IDMATEC,IDMATEC" "0,1" bitfld.long 0x0 26. "CKSTOPC,CKSTOPC" "0,1" bitfld.long 0x0 25. "VSWENDC,VSWENDC" "0,1" bitfld.long 0x0 24. "ACKTIMEOUTC,ACKTIMEOUTC" "0,1" bitfld.long 0x0 23. "ACKFAILC,ACKFAILC" "0,1" newline bitfld.long 0x0 22. "SDIOITC,SDIOITC" "0,1" bitfld.long 0x0 21. "BUSYD0ENDC,BUSYD0ENDC" "0,1" bitfld.long 0x0 11. "DABORTC,DABORTC" "0,1" bitfld.long 0x0 10. "DBCKENDC,DBCKENDC" "0,1" bitfld.long 0x0 9. "DHOLDC,DHOLDC" "0,1" bitfld.long 0x0 8. "DATAENDC,DATAENDC" "0,1" newline bitfld.long 0x0 7. "CMDSENTC,CMDSENTC" "0,1" bitfld.long 0x0 6. "CMDRENDC,CMDRENDC" "0,1" bitfld.long 0x0 5. "RXOVERRC,RXOVERRC" "0,1" bitfld.long 0x0 4. "TXUNDERRC,TXUNDERRC" "0,1" bitfld.long 0x0 3. "DTIMEOUTC,DTIMEOUTC" "0,1" bitfld.long 0x0 2. "CTIMEOUTC,CTIMEOUTC" "0,1" newline bitfld.long 0x0 1. "DCRCFAILC,DCRCFAILC" "0,1" bitfld.long 0x0 0. "CCRCFAILC,CCRCFAILC" "0,1" line.long 0x4 "SDMMC_MASKR,The interrupt mask register determines which status flags generate an interrupt request by setting the corresponding bit to 1." bitfld.long 0x4 28. "IDMABTCIE,IDMABTCIE" "0,1" bitfld.long 0x4 26. "CKSTOPIE,CKSTOPIE" "0,1" bitfld.long 0x4 25. "VSWENDIE,VSWENDIE" "0,1" bitfld.long 0x4 24. "ACKTIMEOUTIE,ACKTIMEOUTIE" "0,1" bitfld.long 0x4 23. "ACKFAILIE,ACKFAILIE" "0,1" bitfld.long 0x4 22. "SDIOITIE,SDIOITIE" "0,1" newline bitfld.long 0x4 21. "BUSYD0ENDIE,BUSYD0ENDIE" "0,1" bitfld.long 0x4 18. "TXFIFOEIE,TXFIFOEIE" "0,1" bitfld.long 0x4 17. "RXFIFOFIE,RXFIFOFIE" "0,1" bitfld.long 0x4 15. "RXFIFOHFIE,RXFIFOHFIE" "0,1" bitfld.long 0x4 14. "TXFIFOHEIE,TXFIFOHEIE" "0,1" bitfld.long 0x4 11. "DABORTIE,DABORTIE" "0,1" newline bitfld.long 0x4 10. "DBCKENDIE,DBCKENDIE" "0,1" bitfld.long 0x4 9. "DHOLDIE,DHOLDIE" "0,1" bitfld.long 0x4 8. "DATAENDIE,DATAENDIE" "0,1" bitfld.long 0x4 7. "CMDSENTIE,CMDSENTIE" "0,1" bitfld.long 0x4 6. "CMDRENDIE,CMDRENDIE" "0,1" bitfld.long 0x4 5. "RXOVERRIE,RXOVERRIE" "0,1" newline bitfld.long 0x4 4. "TXUNDERRIE,TXUNDERRIE" "0,1" bitfld.long 0x4 3. "DTIMEOUTIE,DTIMEOUTIE" "0,1" bitfld.long 0x4 2. "CTIMEOUTIE,CTIMEOUTIE" "0,1" bitfld.long 0x4 1. "DCRCFAILIE,DCRCFAILIE" "0,1" bitfld.long 0x4 0. "CCRCFAILIE,CCRCFAILIE" "0,1" line.long 0x8 "SDMMC_ACKTIMER,The SDMMC_ACKTIMER register contains the acknowledgment timeout period. in SDMMC_CK bus clock periods. A counter loads the value from the SDMMC_ACKTIMER register. and starts decrementing when the data path state machine (DPSM) enters the.." hexmask.long 0x8 0.--24. 1. "ACKTIME,ACKTIME" group.long 0x50++0xB line.long 0x0 "SDMMC_IDMACTRLR,The receive and transmit FIFOs can be read or written as 32-bit wide registers. The FIFOs contain 32 entries on 32 sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO." bitfld.long 0x0 1. "IDMABMODE,IDMABMODE" "0,1" bitfld.long 0x0 0. "IDMAEN,IDMAEN" "0,1" line.long 0x4 "SDMMC_IDMABSIZER,The SDMMC_IDMABSIZER register contains the buffer size when in linked list configuration." hexmask.long.word 0x4 5.--16. 1. "IDMABNDT,IDMABNDT" line.long 0x8 "SDMMC_IDMABASER,The SDMMC_IDMABASER register contains the memory buffer base address in single buffer configuration and linked list configuration." hexmask.long 0x8 0.--31. 1. "IDMABASE,IDMABASE" group.long 0x64++0x7 line.long 0x0 "SDMMC_IDMALAR,SDMMC IDMA linked list address register" bitfld.long 0x0 31. "ULA,ULA" "0,1" bitfld.long 0x0 30. "ULS,ULS" "0,1" bitfld.long 0x0 29. "ABR,ABR" "0,1" hexmask.long.word 0x0 2.--15. 1. "IDMALA,IDMALA" line.long 0x4 "SDMMC_IDMABAR,SDMMC IDMA linked list memory base register" hexmask.long 0x4 2.--31. 1. "IDMABA,IDMABA" group.long 0x80++0x3F line.long 0x0 "SDMMC_FIFOR0,The receive and transmit FIFOs can be only read or written as word (32-bit) wide registers. The FIFOs contain 16 entries on sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO." hexmask.long 0x0 0.--31. 1. "FIFODATA,FIFODATA" line.long 0x4 "SDMMC_FIFOR1,The receive and transmit FIFOs can be only read or written as word (32-bit) wide registers. The FIFOs contain 16 entries on sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO." hexmask.long 0x4 0.--31. 1. "FIFODATA,FIFODATA" line.long 0x8 "SDMMC_FIFOR2,The receive and transmit FIFOs can be only read or written as word (32-bit) wide registers. The FIFOs contain 16 entries on sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO." hexmask.long 0x8 0.--31. 1. "FIFODATA,FIFODATA" line.long 0xC "SDMMC_FIFOR3,The receive and transmit FIFOs can be only read or written as word (32-bit) wide registers. The FIFOs contain 16 entries on sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO." hexmask.long 0xC 0.--31. 1. "FIFODATA,FIFODATA" line.long 0x10 "SDMMC_FIFOR4,The receive and transmit FIFOs can be only read or written as word (32-bit) wide registers. The FIFOs contain 16 entries on sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO." hexmask.long 0x10 0.--31. 1. "FIFODATA,FIFODATA" line.long 0x14 "SDMMC_FIFOR5,The receive and transmit FIFOs can be only read or written as word (32-bit) wide registers. The FIFOs contain 16 entries on sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO." hexmask.long 0x14 0.--31. 1. "FIFODATA,FIFODATA" line.long 0x18 "SDMMC_FIFOR6,The receive and transmit FIFOs can be only read or written as word (32-bit) wide registers. The FIFOs contain 16 entries on sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO." hexmask.long 0x18 0.--31. 1. "FIFODATA,FIFODATA" line.long 0x1C "SDMMC_FIFOR7,The receive and transmit FIFOs can be only read or written as word (32-bit) wide registers. The FIFOs contain 16 entries on sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO." hexmask.long 0x1C 0.--31. 1. "FIFODATA,FIFODATA" line.long 0x20 "SDMMC_FIFOR8,The receive and transmit FIFOs can be only read or written as word (32-bit) wide registers. The FIFOs contain 16 entries on sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO." hexmask.long 0x20 0.--31. 1. "FIFODATA,FIFODATA" line.long 0x24 "SDMMC_FIFOR9,The receive and transmit FIFOs can be only read or written as word (32-bit) wide registers. The FIFOs contain 16 entries on sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO." hexmask.long 0x24 0.--31. 1. "FIFODATA,FIFODATA" line.long 0x28 "SDMMC_FIFOR10,The receive and transmit FIFOs can be only read or written as word (32-bit) wide registers. The FIFOs contain 16 entries on sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the.." hexmask.long 0x28 0.--31. 1. "FIFODATA,FIFODATA" line.long 0x2C "SDMMC_FIFOR11,The receive and transmit FIFOs can be only read or written as word (32-bit) wide registers. The FIFOs contain 16 entries on sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the.." hexmask.long 0x2C 0.--31. 1. "FIFODATA,FIFODATA" line.long 0x30 "SDMMC_FIFOR12,The receive and transmit FIFOs can be only read or written as word (32-bit) wide registers. The FIFOs contain 16 entries on sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the.." hexmask.long 0x30 0.--31. 1. "FIFODATA,FIFODATA" line.long 0x34 "SDMMC_FIFOR13,The receive and transmit FIFOs can be only read or written as word (32-bit) wide registers. The FIFOs contain 16 entries on sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the.." hexmask.long 0x34 0.--31. 1. "FIFODATA,FIFODATA" line.long 0x38 "SDMMC_FIFOR14,The receive and transmit FIFOs can be only read or written as word (32-bit) wide registers. The FIFOs contain 16 entries on sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the.." hexmask.long 0x38 0.--31. 1. "FIFODATA,FIFODATA" line.long 0x3C "SDMMC_FIFOR15,The receive and transmit FIFOs can be only read or written as word (32-bit) wide registers. The FIFOs contain 16 entries on sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the.." hexmask.long 0x3C 0.--31. 1. "FIFODATA,FIFODATA" rgroup.long 0x3F4++0xB line.long 0x0 "SDMMC_VERR,SDMMC version register" hexmask.long.byte 0x0 4.--7. 1. "MAJREV,MAJREV" hexmask.long.byte 0x0 0.--3. 1. "MINREV,MINREV" line.long 0x4 "SDMMC_IPIDR,SDMMC identification register" hexmask.long 0x4 0.--31. 1. "IP_ID,IP_ID" line.long 0x8 "SDMMC_SIDR,SDMMC size ID register" hexmask.long 0x8 0.--31. 1. "SID,SID" tree.end tree.end endif tree "SPDIFRX (SPDIF Receiver Interface)" base ad:0x4000D000 group.long 0x0++0x7 line.long 0x0 "SPDIFRX_CR,Control register" bitfld.long 0x0 21. "CKSBKPEN,CKSBKPEN" "0,1" bitfld.long 0x0 20. "CKSEN,CKSEN" "0,1" bitfld.long 0x0 16.--18. "INSEL,INSEL" "0,1,2,3,4,5,6,7" bitfld.long 0x0 14. "WFA,WFA" "0,1" bitfld.long 0x0 12.--13. "NBTR,NBTR" "0,1,2,3" bitfld.long 0x0 11. "CHSEL,CHSEL" "0,1" bitfld.long 0x0 10. "CBDMAEN,CBDMAEN" "0,1" newline bitfld.long 0x0 9. "PTMSK,PTMSK" "0,1" bitfld.long 0x0 8. "CUMSK,CUMSK" "0,1" bitfld.long 0x0 7. "VMSK,VMSK" "0,1" bitfld.long 0x0 6. "PMSK,PMSK" "0,1" bitfld.long 0x0 4.--5. "DRFMT,DRFMT" "0,1,2,3" bitfld.long 0x0 3. "RXSTEO,RXSTEO" "0,1" bitfld.long 0x0 2. "RXDMAEN,RXDMAEN" "0,1" newline bitfld.long 0x0 0.--1. "SPDIFRXEN,SPDIFRXEN" "0,1,2,3" line.long 0x4 "SPDIFRX_IMR,Interrupt mask register" bitfld.long 0x4 6. "IFEIE,IFEIE" "0,1" bitfld.long 0x4 5. "SYNCDIE,SYNCDIE" "0,1" bitfld.long 0x4 4. "SBLKIE,SBLKIE" "0,1" bitfld.long 0x4 3. "OVRIE,OVRIE" "0,1" bitfld.long 0x4 2. "PERRIE,PERRIE" "0,1" bitfld.long 0x4 1. "CSRNEIE,CSRNEIE" "0,1" bitfld.long 0x4 0. "RXNEIE,RXNEIE" "0,1" rgroup.long 0x8++0x3 line.long 0x0 "SPDIFRX_SR,Status register" hexmask.long.word 0x0 16.--30. 1. "WIDTH5,WIDTH5" bitfld.long 0x0 8. "TERR,TERR" "0,1" bitfld.long 0x0 7. "SERR,SERR" "0,1" bitfld.long 0x0 6. "FERR,FERR" "0,1" bitfld.long 0x0 5. "SYNCD,SYNCD" "0,1" bitfld.long 0x0 4. "SBD,SBD" "0,1" bitfld.long 0x0 3. "OVR,OVR" "0,1" newline bitfld.long 0x0 2. "PERR,PERR" "0,1" bitfld.long 0x0 1. "CSRNE,CSRNE" "0,1" bitfld.long 0x0 0. "RXNE,RXNE" "0,1" wgroup.long 0xC++0x3 line.long 0x0 "SPDIFRX_IFCR,Interrupt flag clear register" bitfld.long 0x0 5. "SYNCDCF,SYNCDCF" "0,1" bitfld.long 0x0 4. "SBDCF,SBDCF" "0,1" bitfld.long 0x0 3. "OVRCF,OVRCF" "0,1" bitfld.long 0x0 2. "PERRCF,PERRCF" "0,1" rgroup.long 0x10++0xB line.long 0x0 "SPDIFRX_FMT0_DR,This register can take 3 different formats according to DRFMT. Here is the format when DRFMT = 00:" bitfld.long 0x0 28.--29. "PT,PT" "0,1,2,3" bitfld.long 0x0 27. "C,C" "0,1" bitfld.long 0x0 26. "U,U" "0,1" bitfld.long 0x0 25. "V,V" "0,1" bitfld.long 0x0 24. "PE,PE" "0,1" hexmask.long.tbyte 0x0 0.--23. 1. "DR,DR" line.long 0x4 "SPDIFRX_CSR,Channel status register" bitfld.long 0x4 24. "SOB,SOB" "0,1" hexmask.long.byte 0x4 16.--23. 1. "CS,CS" hexmask.long.word 0x4 0.--15. 1. "USR,USR" line.long 0x8 "SPDIFRX_DIR,Debug information register" hexmask.long.word 0x8 16.--28. 1. "TLO,TLO" hexmask.long.word 0x8 0.--12. 1. "THI,THI" rgroup.long 0x3F4++0xB line.long 0x0 "SPDIFRX_VERR,SPDIFRX version register" hexmask.long.byte 0x0 4.--7. 1. "MAJREV,MAJREV" hexmask.long.byte 0x0 0.--3. 1. "MINREV,MINREV" line.long 0x4 "SPDIFRX_IPIDR,SPDIFRX identification register" hexmask.long 0x4 0.--31. 1. "ID,ID" line.long 0x8 "SPDIFRX_SIDR,SPDIFRX size identification register" hexmask.long 0x8 0.--31. 1. "SID,SID" tree.end tree "SPI (Serial Peripheral Interface)" base ad:0x0 sif (cpuis("STM32MP13*")||cpuis("STM32MP151*")) tree "SPI1" base ad:0x44004000 sif (cpuis("STM32MP13*")) group.long 0x0++0x3 line.long 0x0 "SPI_CR1,SPI/I2S control register 1" bitfld.long 0x0 16. "IOLOCK,locking the AF configuration of associated IOs" "0: AF configuration is not locked,1: AF configuration is locked" bitfld.long 0x0 15. "TCRCINI,CRC calculation initialization pattern control for transmitter" "0: All zero pattern is applied,1: All ones pattern is applied" newline bitfld.long 0x0 14. "RCRCINI,CRC calculation initialization pattern control for receiver" "0: all zero pattern is applied,1: all ones pattern is applied" bitfld.long 0x0 13. "CRC33_17,32-bit CRC polynomial configuration" "0: full size (33-bit or 17-bit) CRC polynomial is..,1: full size (33-bit or 17-bit) CRC polynomial is.." newline bitfld.long 0x0 12. "SSI,internal SS signal input level" "0,1" bitfld.long 0x0 11. "HDDIR,Rx/Tx direction at Half-duplex mode" "0: SPI is Receiver,1: SPI is transmitter" newline bitfld.long 0x0 10. "CSUSP,master suspend request" "0,1" bitfld.long 0x0 9. "CSTART,master transfer start" "0: master transfer is at idle,1: master transfer is on-going or temporary.." newline bitfld.long 0x0 8. "MASRX,master automatic SUSP in Receive mode" "0: SPI flow/clock generation is continuous..,1: SPI flow is suspended temporary on RxFIFO full.." bitfld.long 0x0 0. "SPE,serial peripheral enable" "0: serial peripheral disabled.,1: serial peripheral enabled" group.long 0x10++0x3 line.long 0x0 "SPI_IER,SPI/I2S interrupt enable register" bitfld.long 0x0 10. "TSERFIE,additional number of transactions reload interrupt enable" "0: TSERF interrupt disabled,1: TSERF interrupt enabled" bitfld.long 0x0 9. "MODFIE,mode fault interrupt enable" "0: MODF interrupt disabled,1: MODF interrupt enabled" newline bitfld.long 0x0 8. "TIFREIE,TIFRE interrupt enable" "0: TIFRE interrupt disabled,1: TIFRE interrupt enabled" bitfld.long 0x0 7. "CRCEIE,CRC error interrupt enable" "0: CRC interrupt disabled,1: CRC interrupt enabled" newline bitfld.long 0x0 6. "OVRIE,OVR interrupt enable" "0: OVR interrupt disabled,1: OVR interrupt enabled" bitfld.long 0x0 5. "UDRIE,UDR interrupt enable" "0: UDR interrupt disabled,1: UDR interrupt enabled" newline bitfld.long 0x0 4. "TXTFIE,TXTFIE interrupt enable" "0: TXTF interrupt disabled,1: TXTF interrupt enabled" bitfld.long 0x0 3. "EOTIE,EOT SUSP and TXC interrupt enable" "0: EOT/SUSP/TXC interrupt disabled,1: EOT/SUSP/TXC interrupt enabled" newline bitfld.long 0x0 2. "DXPIE,DXP interrupt enabled" "0: DXP interrupt disabled,1: DXP interrupt enabled" bitfld.long 0x0 1. "TXPIE,TXP interrupt enable" "0: TXP interrupt disabled,1: TXP interrupt enabled" newline bitfld.long 0x0 0. "RXPIE,RXP Interrupt Enable" "0: RXP interrupt disabled,1: RXP interrupt enabled" rgroup.long 0x14++0x3 line.long 0x0 "SPI_SR,SPI/I2S status register" hexmask.long.word 0x0 16.--31. 1. "CTSIZE,number of data frames remaining in current TSIZE session" bitfld.long 0x0 15. "RXWNE,RxFIFO word not empty" "0: less than four bytes of RxFIFO space is occupied..,1: at least four bytes of RxFIFO space is occupied.." newline bitfld.long 0x0 13.--14. "RXPLVL,RxFIFO packing leveL" "0: no next frame is available at RxFIFO,1: 1 frame is available,2: 2 frames are available*,3: 3 frames are available*" bitfld.long 0x0 12. "TXC,TxFIFO transmission complete" "0: Current data transaction is still ongoing data..,1: Last TxFIFO frame transmission completed" newline bitfld.long 0x0 11. "SUSP,suspension status" "0: SPI not suspended (master mode active or other..,1: Master mode is suspended (current frame.." bitfld.long 0x0 10. "TSERF,additional number of SPI data to be transacted was reload" "0: no acceptation,1: additional number of data accepted current.." newline bitfld.long 0x0 9. "MODF,mode fault" "0: no mode fault,1: mode fault detected" bitfld.long 0x0 8. "TIFRE,TI frame format error" "0: no TI Frame Error,1: TI Frame Error detected" newline bitfld.long 0x0 7. "CRCE,CRC error" "0: no CRC error,1: CRC error detected" bitfld.long 0x0 6. "OVR,overrun" "0: no overrun,1: overrun detected" newline bitfld.long 0x0 5. "UDR,underrun at slave transmission mode" "0: no underrun,1: underrun detected" bitfld.long 0x0 4. "TXTF,transmission transfer filled" "0: upload of TxFIFO is on-going or not started,1: TxFIFO upload is finished" newline bitfld.long 0x0 3. "EOT,end of transfer" "0: transfer is on-going or not started,1: transfer complete" bitfld.long 0x0 2. "DXP,duplex packet" "0: TxFIFO is Full and/or RxFIFO is Empty,1: Both TxFIFO has space for write and RxFIFO.." newline bitfld.long 0x0 1. "TXP,Tx-packet space available" "0: there is not enough space to locate next data..,1: TxFIFO has enough free location to host 1 data.." bitfld.long 0x0 0. "RXP,Rx-packet available" "0: RxFIFO is empty or a not complete data packet is..,1: RxFIFO contains at least 1 data packet" wgroup.long 0x18++0x3 line.long 0x0 "SPI_IFCR,SPI/I2S interrupt/status flags clear register" bitfld.long 0x0 11. "SUSPC,SUSPend flag clear" "0,1" bitfld.long 0x0 10. "TSERFC,TSERFC flag clear" "0,1" newline bitfld.long 0x0 9. "MODFC,mode fault flag clear" "0,1" bitfld.long 0x0 8. "TIFREC,TI frame format error flag clear" "0,1" newline bitfld.long 0x0 7. "CRCEC,CRC error flag clear" "0,1" bitfld.long 0x0 6. "OVRC,overrun flag clear" "0,1" newline bitfld.long 0x0 5. "UDRC,underrun flag clear" "0,1" bitfld.long 0x0 4. "TXTFC,transmission Transfer Filled flag clear" "0,1" newline bitfld.long 0x0 3. "EOTC,end of transfer flag clear" "0,1" wgroup.long 0x20++0x3 line.long 0x0 "SPI_TXDR,SPI/I2S transmit data register" hexmask.long 0x0 0.--31. 1. "TXDR,transmit data register" rgroup.long 0x30++0x3 line.long 0x0 "SPI_RXDR,SPI/I2S receive data register" hexmask.long 0x0 0.--31. 1. "RXDR,receive data register" endif sif (cpuis("STM32MP151*")) group.long 0x0++0x3 line.long 0x0 "SPI2S_CR1,SPI/I2S control register 1" bitfld.long 0x0 16. "IOLOCK,IOLOCK" "0,1" bitfld.long 0x0 15. "TCRCINI,TCRCINI" "0,1" newline bitfld.long 0x0 14. "RCRCINI,RCRCINI" "0,1" bitfld.long 0x0 13. "CRC33_17,CRC33_17" "0,1" newline bitfld.long 0x0 12. "SSI,SSI" "0,1" bitfld.long 0x0 11. "HDDIR,HDDIR" "0,1" newline bitfld.long 0x0 10. "CSUSP,CSUSP" "0,1" bitfld.long 0x0 9. "CSTART,CSTART" "0,1" newline bitfld.long 0x0 8. "MASRX,MASRX" "0,1" bitfld.long 0x0 0. "SPE,SPE" "0,1" group.long 0x10++0x3 line.long 0x0 "SPI2S_IER,SPI/I2S interrupt enable register" bitfld.long 0x0 10. "TSERFIE,TSERFIE" "0,1" bitfld.long 0x0 9. "MODFIE,MODFIE" "0,1" newline bitfld.long 0x0 8. "TIFREIE,TIFREIE" "0,1" bitfld.long 0x0 7. "CRCEIE,CRCEIE" "0,1" newline bitfld.long 0x0 6. "OVRIE,OVRIE" "0,1" bitfld.long 0x0 5. "UDRIE,UDRIE" "0,1" newline bitfld.long 0x0 4. "TXTFIE,TXTFIE" "0,1" bitfld.long 0x0 3. "EOTIE,EOTIE" "0,1" newline bitfld.long 0x0 2. "DXPIE,DXPIE" "0,1" bitfld.long 0x0 1. "TXPIE,TXPIE" "0,1" newline bitfld.long 0x0 0. "RXPIE,RXPIE" "0,1" rgroup.long 0x14++0x3 line.long 0x0 "SPI2S_SR,SPI/I2S status register" hexmask.long.word 0x0 16.--31. 1. "CTSIZE,CTSIZE" bitfld.long 0x0 15. "RXWNE,RXWNE" "0,1" newline bitfld.long 0x0 13.--14. "RXPLVL,RXPLVL" "0,1,2,3" bitfld.long 0x0 12. "TXC,TXC" "0,1" newline bitfld.long 0x0 11. "SUSP,SUSP" "0,1" bitfld.long 0x0 10. "TSERF,TSERF" "0,1" newline bitfld.long 0x0 9. "MODF,MODF" "0,1" bitfld.long 0x0 8. "TIFRE,TIFRE" "0,1" newline bitfld.long 0x0 7. "CRCE,CRCE" "0,1" bitfld.long 0x0 6. "OVR,OVR" "0,1" newline bitfld.long 0x0 5. "UDR,UDR" "0,1" bitfld.long 0x0 4. "TXTF,TXTF" "0,1" newline bitfld.long 0x0 3. "EOT,EOT" "0,1" bitfld.long 0x0 2. "DXP,DXP" "0,1" newline bitfld.long 0x0 1. "TXP,TXP" "0,1" bitfld.long 0x0 0. "RXP,RXP" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "SPI2S_IFCR,SPI/I2S interrupt/status flags clear register" bitfld.long 0x0 11. "SUSPC,SUSPC" "0,1" bitfld.long 0x0 10. "TSERFC,TSERFC" "0,1" newline bitfld.long 0x0 9. "MODFC,MODFC" "0,1" bitfld.long 0x0 8. "TIFREC,TIFREC" "0,1" newline bitfld.long 0x0 7. "CRCEC,CRCEC" "0,1" bitfld.long 0x0 6. "OVRC,OVRC" "0,1" newline bitfld.long 0x0 5. "UDRC,UDRC" "0,1" bitfld.long 0x0 4. "TXTFC,TXTFC" "0,1" newline bitfld.long 0x0 3. "EOTC,EOTC" "0,1" wgroup.long 0x20++0x3 line.long 0x0 "SPI2S_TXDR,SPI/I2S transmit data register" hexmask.long 0x0 0.--31. 1. "TXDR,TXDR" rgroup.long 0x30++0x3 line.long 0x0 "SPI2S_RXDR,SPI/I2S receive data register" hexmask.long 0x0 0.--31. 1. "RXDR,RXDR" endif group.long 0x4++0xB line.long 0x0 "SPI_CR2,SPI control register 2" hexmask.long.word 0x0 16.--31. 1. "TSER,number of data transfer extension to be reload into TSIZE just when a previous number of data stored at TSIZE is transacted" hexmask.long.word 0x0 0.--15. 1. "TSIZE,number of data at current transfer" line.long 0x4 "SPI_CFG1,SPI configuration register 1" sif (cpuis("STM32MP13*")) bitfld.long 0x4 28.--30. "MBR,master baud rate" "0: SPI master clock/2,1: SPI master clock/4,2: SPI master clock/8,3: SPI master clock/16,4: SPI master clock/32,5: SPI master clock/64,6: SPI master clock/128,7: SPI master clock/256" bitfld.long 0x4 22. "CRCEN,hardware CRC computation enable" "0: CRC calculation disabled,1: CRC calculation Enabled" newline hexmask.long.byte 0x4 16.--20. 1. "CRCSIZE,length of CRC frame to be transacted and compared" bitfld.long 0x4 15. "TXDMAEN,Tx DMA stream enable" "0: Tx DMA disabled,1: Tx DMA enabled" newline bitfld.long 0x4 14. "RXDMAEN,Rx DMA stream enable" "0: Rx-DMA disabled,1: Rx-DMA enabled" bitfld.long 0x4 11.--12. "UDRDET,detection of underrun condition at slave transmitter" "0: underrun is detected at begin of data frame (no..,1: underrun is detected at end of last data frame,2: underrun is detected by begin of active SS signal,?" newline bitfld.long 0x4 9.--10. "UDRCFG,behavior of slave transmitter at underrun condition" "0: slave sends a constant pattern defined by the..,1: slave repeats lastly received data frame from..,2: slave repeats its lastly transmitted data frame,?" hexmask.long.byte 0x4 5.--8. 1. "FTHLV,FIFO threshold level" newline hexmask.long.byte 0x4 0.--4. 1. "DSIZE,number of bits in at single SPI data frame" endif sif (cpuis("STM32MP151*")) bitfld.long 0x4 28.--30. "MBR,MBR" "0,1,2,3,4,5,6,7" newline endif sif (cpuis("STM32MP151*")) bitfld.long 0x4 22. "CRCEN,CRCEN" "0,1" endif sif (cpuis("STM32MP151*")) hexmask.long.byte 0x4 16.--20. 1. "CRCSIZE,CRCSIZE" newline bitfld.long 0x4 15. "TXDMAEN,TXDMAEN" "0,1" bitfld.long 0x4 14. "RXDMAEN,RXDMAEN" "0,1" newline endif sif (cpuis("STM32MP151*")) bitfld.long 0x4 11.--12. "UDRDET,UDRDET" "0,1,2,3" bitfld.long 0x4 9.--10. "UDRCFG,UDRCFG" "0,1,2,3" newline hexmask.long.byte 0x4 5.--8. 1. "FTHLV,FTHLV" endif line.long 0x8 "SPI_CFG2,SPI configuration register 2" sif (cpuis("STM32MP13*")) bitfld.long 0x8 31. "AFCNTR,alternate function GPIOs control" "0: the peripheral takes no control of GPIOs while..,1: the peripheral keeps always control of all.." bitfld.long 0x8 30. "SSOM,SS output management in master mode" "0: SS is kept at active level till data transfer is..,1: SPI data frames are interleaved with SS non.." newline bitfld.long 0x8 29. "SSOE,SS output enable" "0: SS output is disabled and the SPI can work in..,1: SS output is enabled. The SPI cannot work in a.." bitfld.long 0x8 28. "SSIOP,SS input/output polarity" "0: low level is active for SS signal,1: high level is active for SS signal" newline bitfld.long 0x8 26. "SSM,software management of SS signal input" "0: SS input value is determined by the SS PAD,1: SS input value is determined by the SSI bit" bitfld.long 0x8 25. "CPOL,clock polarity" "0: SCK signal is at 0 when idle,1: SCK signal is at 1 when idle" newline bitfld.long 0x8 24. "CPHA,clock phase" "0: the first clock transition is the first data..,1: the second clock transition is the first data.." bitfld.long 0x8 23. "LSBFRST,data frame format" "0: MSB transmitted first,1: LSB transmitted first" newline bitfld.long 0x8 22. "MASTER,SPI master" "0: SPI Slave,1: SPI Master" bitfld.long 0x8 19.--21. "SP,Serial protocol" "0: SPI Motorola,1: SPI TI,?,?,?,?,?,?" newline bitfld.long 0x8 17.--18. "COMM,SPI communication mode" "0: full-duplex,1: simplex transmitter,2: simplex receiver,3: half-duplex" bitfld.long 0x8 15. "IOSWP,swap functionality of MISO and MOSI pins" "0: no swap,1: MOSI and MISO are swapped" newline hexmask.long.byte 0x8 4.--7. 1. "MIDI,master Inter-Data Idleness" hexmask.long.byte 0x8 0.--3. 1. "MSSI,master SS idleness" newline endif sif (cpuis("STM32MP151*")) bitfld.long 0x8 31. "AFCNTR,AFCNTR" "0,1" bitfld.long 0x8 30. "SSOM,SSOM" "0,1" newline bitfld.long 0x8 29. "SSOE,SSOE" "0,1" bitfld.long 0x8 28. "SSIOP,SSIOP" "0,1" newline endif sif (cpuis("STM32MP151*")) bitfld.long 0x8 26. "SSM,SSM" "0,1" bitfld.long 0x8 25. "CPOL,CPOL" "0,1" newline bitfld.long 0x8 24. "CPHA,CPHA" "0,1" bitfld.long 0x8 23. "LSBFRST,LSBFRST" "0,1" newline bitfld.long 0x8 22. "MASTER,MASTER" "0,1" bitfld.long 0x8 19.--21. "SP,SP" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 17.--18. "COMM,COMM" "0,1,2,3" endif sif (cpuis("STM32MP151*")) bitfld.long 0x8 15. "IOSWP,IOSWP" "0,1" newline endif sif (cpuis("STM32MP151*")) hexmask.long.byte 0x8 4.--7. 1. "MIDI,MIDI" endif group.long 0x40++0x13 line.long 0x0 "SPI_CRCPOLY,SPI polynomial register" hexmask.long 0x0 0.--31. 1. "CRCPOLY,CRC polynomial register" line.long 0x4 "SPI_TXCRC,SPI transmitter CRC register" sif (cpuis("STM32MP13*")) hexmask.long 0x4 0.--31. 1. "TXCRC,CRC register for transmitter" endif sif (cpuis("STM32MP151*")) hexmask.long 0x4 0.--31. 1. "TXCRC,TXCRC" endif line.long 0x8 "SPI_RXCRC,SPI receiver CRC register" sif (cpuis("STM32MP13*")) hexmask.long 0x8 0.--31. 1. "RXCRC,CRC register for receiver" endif sif (cpuis("STM32MP151*")) hexmask.long 0x8 0.--31. 1. "RXCRC,RXCRC" endif line.long 0xC "SPI_UDRDR,SPI underrun data register" hexmask.long 0xC 0.--31. 1. "UDRDR,data at slave underrun condition" line.long 0x10 "SPI_I2SCFGR,SPI/I2S configuration register" sif (cpuis("STM32MP13*")) bitfld.long 0x10 25. "MCKOE,master clock output enable" "0: Master clock output is disabled,1: Master clock output is enabled" bitfld.long 0x10 24. "ODD,odd factor for the prescaler" "0: Real divider value is = I2SDIV *2,1: Real divider value is = (I2SDIV * 2) + 1" newline bitfld.long 0x10 14. "DATFMT,data format" "0: the data inside the SPI_RXDR or SPI_TXDR are..,1: the data inside the SPI_RXDR or SPI_TXDR are.." bitfld.long 0x10 13. "WSINV,Word select inversion" "0: in I2S Philips standard Left channel is..,1: in I2S Philips standard Left channel is.." newline bitfld.long 0x10 12. "FIXCH,fixed channel length in slave" "0: the channel length in slave mode is different..,1: the channel length in slave mode is supposed to.." bitfld.long 0x10 11. "CKPOL,serial audio clock polarity" "0: the signals generated by the SPI/I2S (i.e. SDO..,1: the signals generated by the SPI/I2S (i.e. SDO.." newline bitfld.long 0x10 10. "CHLEN,channel length (number of bits per audio channel)" "0: 16-bit wide,1: 32-bit wide" bitfld.long 0x10 8.--9. "DATLEN,data length to be transferred" "0: 16-bit data length,1: 24-bit data length,2: 32-bit data length,3: not allowed" newline bitfld.long 0x10 7. "PCMSYNC,PCM frame synchronization" "0: short frame synchronization,1: long frame synchronization" bitfld.long 0x10 4.--5. "I2SSTD,I2S standard selection" "0: I2S Philips standard.,1: MSB justified standard (left justified),2: LSB justified standard (right justified),3: PCM standard" newline bitfld.long 0x10 1.--3. "I2SCFG,I2S configuration mode" "0: slave - transmit,1: slave - receive,2: master - transmit,3: master - receive,4: slave - full duplex,5: master - full duplex,?,?" bitfld.long 0x10 0. "I2SMOD,I2S mode selection" "0: SPI mode is selected,1: I2S/PCM mode is selected" newline endif sif (cpuis("STM32MP151*")) bitfld.long 0x10 25. "MCKOE,MCKOE" "0,1" bitfld.long 0x10 24. "ODD,ODD" "0,1" newline endif hexmask.long.byte 0x10 16.--23. 1. "I2SDIV,I2S linear prescaler" sif (cpuis("STM32MP151*")) bitfld.long 0x10 14. "DATFMT,DATFMT" "0,1" newline bitfld.long 0x10 13. "WSINV,WSINV" "0,1" bitfld.long 0x10 12. "FIXCH,FIXCH" "0,1" newline bitfld.long 0x10 11. "CKPOL,CKPOL" "0,1" bitfld.long 0x10 10. "CHLEN,CHLEN" "0,1" newline bitfld.long 0x10 8.--9. "DATLEN,DATLEN" "0,1,2,3" bitfld.long 0x10 7. "PCMSYNC,PCMSYNC" "0,1" newline endif sif (cpuis("STM32MP151*")) bitfld.long 0x10 4.--5. "I2SSTD,I2SSTD" "0,1,2,3" bitfld.long 0x10 1.--3. "I2SCFG,I2SCFG" "0,1,2,3,4,5,6,7" endif group.long 0x3F0++0x3 line.long 0x0 "SPI_I2S_HWCFGR,SPI/I2S hardware configuration register" sif (cpuis("STM32MP13*")) hexmask.long.byte 0x0 16.--19. 1. "DSCFG,SPI data size configuration" hexmask.long.byte 0x0 12.--15. 1. "I2SCFG,I2S configuration" newline hexmask.long.byte 0x0 8.--11. 1. "CRCCFG,CRC configuration for SPI" hexmask.long.byte 0x0 4.--7. 1. "RXFCFG,RxFIFO size" newline hexmask.long.byte 0x0 0.--3. 1. "TXFCFG,TxFIFO size" endif sif (cpuis("STM32MP151*")) hexmask.long.byte 0x0 16.--19. 1. "DSCFG,DSCFG" newline hexmask.long.byte 0x0 12.--15. 1. "I2SCFG,I2SCFG" hexmask.long.byte 0x0 8.--11. 1. "CRCCFG,CRCCFG" newline hexmask.long.byte 0x0 4.--7. 1. "RXFCFG,RXFCFG" hexmask.long.byte 0x0 0.--3. 1. "TXFCFG,TXFCFG" endif rgroup.long 0x3F4++0x3 line.long 0x0 "SPI_VERR,SPI/I2S version register" sif (cpuis("STM32MP13*")) hexmask.long.byte 0x0 4.--7. 1. "MAJREV,major revision of the IP." hexmask.long.byte 0x0 0.--3. 1. "MINREV,minor revision of the IP." newline endif sif (cpuis("STM32MP151*")) hexmask.long.byte 0x0 4.--7. 1. "MAJREV,MAJREV" hexmask.long.byte 0x0 0.--3. 1. "MINREV,MINREV" endif group.long 0x3F8++0x7 line.long 0x0 "SPI_IPIDR,SPI/I2S identification register" sif (cpuis("STM32MP13*")) hexmask.long 0x0 0.--31. 1. "ID,IP identification" endif sif (cpuis("STM32MP151*")) hexmask.long 0x0 0.--31. 1. "ID,ID" endif line.long 0x4 "SPI_SIDR,SPI/I2S size identification register" sif (cpuis("STM32MP13*")) hexmask.long 0x4 0.--31. 1. "SID,size identification" endif sif (cpuis("STM32MP151*")) hexmask.long 0x4 0.--31. 1. "SID,SID" endif sif (cpuis("STM32MP151*")) rgroup.long 0x44++0x3 line.long 0x0 "SPI_TXCRC,SPI transmitter CRC register" endif sif (cpuis("STM32MP151*")) rgroup.long 0x48++0x3 line.long 0x0 "SPI_RXCRC,SPI receiver CRC register" endif sif (cpuis("STM32MP151*")) rgroup.long 0x3F0++0x3 line.long 0x0 "SPI_I2S_HWCFGR,SPI/I2S hardware configuration register" endif sif (cpuis("STM32MP151*")) rgroup.long 0x3F4++0x3 line.long 0x0 "SPI_VERR,SPI/I2S version register" endif sif (cpuis("STM32MP151*")) rgroup.long 0x3F8++0x3 line.long 0x0 "SPI_IPIDR,SPI/I2S identification register" endif sif (cpuis("STM32MP151*")) rgroup.long 0x3FC++0x3 line.long 0x0 "SPI_SIDR,SPI/I2S size identification register" endif tree.end endif sif (cpuis("STM32MP13*")||cpuis("STM32MP151*")) tree "SPI2" base ad:0x4000B000 sif (cpuis("STM32MP13*")) group.long 0x0++0x3 line.long 0x0 "SPI_CR1,SPI/I2S control register 1" bitfld.long 0x0 16. "IOLOCK,locking the AF configuration of associated IOs" "0: AF configuration is not locked,1: AF configuration is locked" bitfld.long 0x0 15. "TCRCINI,CRC calculation initialization pattern control for transmitter" "0: All zero pattern is applied,1: All ones pattern is applied" newline bitfld.long 0x0 14. "RCRCINI,CRC calculation initialization pattern control for receiver" "0: all zero pattern is applied,1: all ones pattern is applied" bitfld.long 0x0 13. "CRC33_17,32-bit CRC polynomial configuration" "0: full size (33-bit or 17-bit) CRC polynomial is..,1: full size (33-bit or 17-bit) CRC polynomial is.." newline bitfld.long 0x0 12. "SSI,internal SS signal input level" "0,1" bitfld.long 0x0 11. "HDDIR,Rx/Tx direction at Half-duplex mode" "0: SPI is Receiver,1: SPI is transmitter" newline bitfld.long 0x0 10. "CSUSP,master suspend request" "0,1" bitfld.long 0x0 9. "CSTART,master transfer start" "0: master transfer is at idle,1: master transfer is on-going or temporary.." newline bitfld.long 0x0 8. "MASRX,master automatic SUSP in Receive mode" "0: SPI flow/clock generation is continuous..,1: SPI flow is suspended temporary on RxFIFO full.." bitfld.long 0x0 0. "SPE,serial peripheral enable" "0: serial peripheral disabled.,1: serial peripheral enabled" group.long 0x10++0x3 line.long 0x0 "SPI_IER,SPI/I2S interrupt enable register" bitfld.long 0x0 10. "TSERFIE,additional number of transactions reload interrupt enable" "0: TSERF interrupt disabled,1: TSERF interrupt enabled" bitfld.long 0x0 9. "MODFIE,mode fault interrupt enable" "0: MODF interrupt disabled,1: MODF interrupt enabled" newline bitfld.long 0x0 8. "TIFREIE,TIFRE interrupt enable" "0: TIFRE interrupt disabled,1: TIFRE interrupt enabled" bitfld.long 0x0 7. "CRCEIE,CRC error interrupt enable" "0: CRC interrupt disabled,1: CRC interrupt enabled" newline bitfld.long 0x0 6. "OVRIE,OVR interrupt enable" "0: OVR interrupt disabled,1: OVR interrupt enabled" bitfld.long 0x0 5. "UDRIE,UDR interrupt enable" "0: UDR interrupt disabled,1: UDR interrupt enabled" newline bitfld.long 0x0 4. "TXTFIE,TXTFIE interrupt enable" "0: TXTF interrupt disabled,1: TXTF interrupt enabled" bitfld.long 0x0 3. "EOTIE,EOT SUSP and TXC interrupt enable" "0: EOT/SUSP/TXC interrupt disabled,1: EOT/SUSP/TXC interrupt enabled" newline bitfld.long 0x0 2. "DXPIE,DXP interrupt enabled" "0: DXP interrupt disabled,1: DXP interrupt enabled" bitfld.long 0x0 1. "TXPIE,TXP interrupt enable" "0: TXP interrupt disabled,1: TXP interrupt enabled" newline bitfld.long 0x0 0. "RXPIE,RXP Interrupt Enable" "0: RXP interrupt disabled,1: RXP interrupt enabled" rgroup.long 0x14++0x3 line.long 0x0 "SPI_SR,SPI/I2S status register" hexmask.long.word 0x0 16.--31. 1. "CTSIZE,number of data frames remaining in current TSIZE session" bitfld.long 0x0 15. "RXWNE,RxFIFO word not empty" "0: less than four bytes of RxFIFO space is occupied..,1: at least four bytes of RxFIFO space is occupied.." newline bitfld.long 0x0 13.--14. "RXPLVL,RxFIFO packing leveL" "0: no next frame is available at RxFIFO,1: 1 frame is available,2: 2 frames are available*,3: 3 frames are available*" bitfld.long 0x0 12. "TXC,TxFIFO transmission complete" "0: Current data transaction is still ongoing data..,1: Last TxFIFO frame transmission completed" newline bitfld.long 0x0 11. "SUSP,suspension status" "0: SPI not suspended (master mode active or other..,1: Master mode is suspended (current frame.." bitfld.long 0x0 10. "TSERF,additional number of SPI data to be transacted was reload" "0: no acceptation,1: additional number of data accepted current.." newline bitfld.long 0x0 9. "MODF,mode fault" "0: no mode fault,1: mode fault detected" bitfld.long 0x0 8. "TIFRE,TI frame format error" "0: no TI Frame Error,1: TI Frame Error detected" newline bitfld.long 0x0 7. "CRCE,CRC error" "0: no CRC error,1: CRC error detected" bitfld.long 0x0 6. "OVR,overrun" "0: no overrun,1: overrun detected" newline bitfld.long 0x0 5. "UDR,underrun at slave transmission mode" "0: no underrun,1: underrun detected" bitfld.long 0x0 4. "TXTF,transmission transfer filled" "0: upload of TxFIFO is on-going or not started,1: TxFIFO upload is finished" newline bitfld.long 0x0 3. "EOT,end of transfer" "0: transfer is on-going or not started,1: transfer complete" bitfld.long 0x0 2. "DXP,duplex packet" "0: TxFIFO is Full and/or RxFIFO is Empty,1: Both TxFIFO has space for write and RxFIFO.." newline bitfld.long 0x0 1. "TXP,Tx-packet space available" "0: there is not enough space to locate next data..,1: TxFIFO has enough free location to host 1 data.." bitfld.long 0x0 0. "RXP,Rx-packet available" "0: RxFIFO is empty or a not complete data packet is..,1: RxFIFO contains at least 1 data packet" wgroup.long 0x18++0x3 line.long 0x0 "SPI_IFCR,SPI/I2S interrupt/status flags clear register" bitfld.long 0x0 11. "SUSPC,SUSPend flag clear" "0,1" bitfld.long 0x0 10. "TSERFC,TSERFC flag clear" "0,1" newline bitfld.long 0x0 9. "MODFC,mode fault flag clear" "0,1" bitfld.long 0x0 8. "TIFREC,TI frame format error flag clear" "0,1" newline bitfld.long 0x0 7. "CRCEC,CRC error flag clear" "0,1" bitfld.long 0x0 6. "OVRC,overrun flag clear" "0,1" newline bitfld.long 0x0 5. "UDRC,underrun flag clear" "0,1" bitfld.long 0x0 4. "TXTFC,transmission Transfer Filled flag clear" "0,1" newline bitfld.long 0x0 3. "EOTC,end of transfer flag clear" "0,1" wgroup.long 0x20++0x3 line.long 0x0 "SPI_TXDR,SPI/I2S transmit data register" hexmask.long 0x0 0.--31. 1. "TXDR,transmit data register" rgroup.long 0x30++0x3 line.long 0x0 "SPI_RXDR,SPI/I2S receive data register" hexmask.long 0x0 0.--31. 1. "RXDR,receive data register" endif sif (cpuis("STM32MP151*")) group.long 0x0++0x3 line.long 0x0 "SPI2S_CR1,SPI/I2S control register 1" bitfld.long 0x0 16. "IOLOCK,IOLOCK" "0,1" bitfld.long 0x0 15. "TCRCINI,TCRCINI" "0,1" newline bitfld.long 0x0 14. "RCRCINI,RCRCINI" "0,1" bitfld.long 0x0 13. "CRC33_17,CRC33_17" "0,1" newline bitfld.long 0x0 12. "SSI,SSI" "0,1" bitfld.long 0x0 11. "HDDIR,HDDIR" "0,1" newline bitfld.long 0x0 10. "CSUSP,CSUSP" "0,1" bitfld.long 0x0 9. "CSTART,CSTART" "0,1" newline bitfld.long 0x0 8. "MASRX,MASRX" "0,1" bitfld.long 0x0 0. "SPE,SPE" "0,1" group.long 0x10++0x3 line.long 0x0 "SPI2S_IER,SPI/I2S interrupt enable register" bitfld.long 0x0 10. "TSERFIE,TSERFIE" "0,1" bitfld.long 0x0 9. "MODFIE,MODFIE" "0,1" newline bitfld.long 0x0 8. "TIFREIE,TIFREIE" "0,1" bitfld.long 0x0 7. "CRCEIE,CRCEIE" "0,1" newline bitfld.long 0x0 6. "OVRIE,OVRIE" "0,1" bitfld.long 0x0 5. "UDRIE,UDRIE" "0,1" newline bitfld.long 0x0 4. "TXTFIE,TXTFIE" "0,1" bitfld.long 0x0 3. "EOTIE,EOTIE" "0,1" newline bitfld.long 0x0 2. "DXPIE,DXPIE" "0,1" bitfld.long 0x0 1. "TXPIE,TXPIE" "0,1" newline bitfld.long 0x0 0. "RXPIE,RXPIE" "0,1" rgroup.long 0x14++0x3 line.long 0x0 "SPI2S_SR,SPI/I2S status register" hexmask.long.word 0x0 16.--31. 1. "CTSIZE,CTSIZE" bitfld.long 0x0 15. "RXWNE,RXWNE" "0,1" newline bitfld.long 0x0 13.--14. "RXPLVL,RXPLVL" "0,1,2,3" bitfld.long 0x0 12. "TXC,TXC" "0,1" newline bitfld.long 0x0 11. "SUSP,SUSP" "0,1" bitfld.long 0x0 10. "TSERF,TSERF" "0,1" newline bitfld.long 0x0 9. "MODF,MODF" "0,1" bitfld.long 0x0 8. "TIFRE,TIFRE" "0,1" newline bitfld.long 0x0 7. "CRCE,CRCE" "0,1" bitfld.long 0x0 6. "OVR,OVR" "0,1" newline bitfld.long 0x0 5. "UDR,UDR" "0,1" bitfld.long 0x0 4. "TXTF,TXTF" "0,1" newline bitfld.long 0x0 3. "EOT,EOT" "0,1" bitfld.long 0x0 2. "DXP,DXP" "0,1" newline bitfld.long 0x0 1. "TXP,TXP" "0,1" bitfld.long 0x0 0. "RXP,RXP" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "SPI2S_IFCR,SPI/I2S interrupt/status flags clear register" bitfld.long 0x0 11. "SUSPC,SUSPC" "0,1" bitfld.long 0x0 10. "TSERFC,TSERFC" "0,1" newline bitfld.long 0x0 9. "MODFC,MODFC" "0,1" bitfld.long 0x0 8. "TIFREC,TIFREC" "0,1" newline bitfld.long 0x0 7. "CRCEC,CRCEC" "0,1" bitfld.long 0x0 6. "OVRC,OVRC" "0,1" newline bitfld.long 0x0 5. "UDRC,UDRC" "0,1" bitfld.long 0x0 4. "TXTFC,TXTFC" "0,1" newline bitfld.long 0x0 3. "EOTC,EOTC" "0,1" wgroup.long 0x20++0x3 line.long 0x0 "SPI2S_TXDR,SPI/I2S transmit data register" hexmask.long 0x0 0.--31. 1. "TXDR,TXDR" rgroup.long 0x30++0x3 line.long 0x0 "SPI2S_RXDR,SPI/I2S receive data register" hexmask.long 0x0 0.--31. 1. "RXDR,RXDR" endif group.long 0x4++0xB line.long 0x0 "SPI_CR2,SPI control register 2" hexmask.long.word 0x0 16.--31. 1. "TSER,number of data transfer extension to be reload into TSIZE just when a previous number of data stored at TSIZE is transacted" hexmask.long.word 0x0 0.--15. 1. "TSIZE,number of data at current transfer" line.long 0x4 "SPI_CFG1,SPI configuration register 1" sif (cpuis("STM32MP13*")) bitfld.long 0x4 28.--30. "MBR,master baud rate" "0: SPI master clock/2,1: SPI master clock/4,2: SPI master clock/8,3: SPI master clock/16,4: SPI master clock/32,5: SPI master clock/64,6: SPI master clock/128,7: SPI master clock/256" bitfld.long 0x4 22. "CRCEN,hardware CRC computation enable" "0: CRC calculation disabled,1: CRC calculation Enabled" newline hexmask.long.byte 0x4 16.--20. 1. "CRCSIZE,length of CRC frame to be transacted and compared" bitfld.long 0x4 15. "TXDMAEN,Tx DMA stream enable" "0: Tx DMA disabled,1: Tx DMA enabled" newline bitfld.long 0x4 14. "RXDMAEN,Rx DMA stream enable" "0: Rx-DMA disabled,1: Rx-DMA enabled" bitfld.long 0x4 11.--12. "UDRDET,detection of underrun condition at slave transmitter" "0: underrun is detected at begin of data frame (no..,1: underrun is detected at end of last data frame,2: underrun is detected by begin of active SS signal,?" newline bitfld.long 0x4 9.--10. "UDRCFG,behavior of slave transmitter at underrun condition" "0: slave sends a constant pattern defined by the..,1: slave repeats lastly received data frame from..,2: slave repeats its lastly transmitted data frame,?" hexmask.long.byte 0x4 5.--8. 1. "FTHLV,FIFO threshold level" newline hexmask.long.byte 0x4 0.--4. 1. "DSIZE,number of bits in at single SPI data frame" endif sif (cpuis("STM32MP151*")) bitfld.long 0x4 28.--30. "MBR,MBR" "0,1,2,3,4,5,6,7" newline endif sif (cpuis("STM32MP151*")) bitfld.long 0x4 22. "CRCEN,CRCEN" "0,1" endif sif (cpuis("STM32MP151*")) hexmask.long.byte 0x4 16.--20. 1. "CRCSIZE,CRCSIZE" newline bitfld.long 0x4 15. "TXDMAEN,TXDMAEN" "0,1" bitfld.long 0x4 14. "RXDMAEN,RXDMAEN" "0,1" newline endif sif (cpuis("STM32MP151*")) bitfld.long 0x4 11.--12. "UDRDET,UDRDET" "0,1,2,3" bitfld.long 0x4 9.--10. "UDRCFG,UDRCFG" "0,1,2,3" newline hexmask.long.byte 0x4 5.--8. 1. "FTHLV,FTHLV" endif line.long 0x8 "SPI_CFG2,SPI configuration register 2" sif (cpuis("STM32MP13*")) bitfld.long 0x8 31. "AFCNTR,alternate function GPIOs control" "0: the peripheral takes no control of GPIOs while..,1: the peripheral keeps always control of all.." bitfld.long 0x8 30. "SSOM,SS output management in master mode" "0: SS is kept at active level till data transfer is..,1: SPI data frames are interleaved with SS non.." newline bitfld.long 0x8 29. "SSOE,SS output enable" "0: SS output is disabled and the SPI can work in..,1: SS output is enabled. The SPI cannot work in a.." bitfld.long 0x8 28. "SSIOP,SS input/output polarity" "0: low level is active for SS signal,1: high level is active for SS signal" newline bitfld.long 0x8 26. "SSM,software management of SS signal input" "0: SS input value is determined by the SS PAD,1: SS input value is determined by the SSI bit" bitfld.long 0x8 25. "CPOL,clock polarity" "0: SCK signal is at 0 when idle,1: SCK signal is at 1 when idle" newline bitfld.long 0x8 24. "CPHA,clock phase" "0: the first clock transition is the first data..,1: the second clock transition is the first data.." bitfld.long 0x8 23. "LSBFRST,data frame format" "0: MSB transmitted first,1: LSB transmitted first" newline bitfld.long 0x8 22. "MASTER,SPI master" "0: SPI Slave,1: SPI Master" bitfld.long 0x8 19.--21. "SP,Serial protocol" "0: SPI Motorola,1: SPI TI,?,?,?,?,?,?" newline bitfld.long 0x8 17.--18. "COMM,SPI communication mode" "0: full-duplex,1: simplex transmitter,2: simplex receiver,3: half-duplex" bitfld.long 0x8 15. "IOSWP,swap functionality of MISO and MOSI pins" "0: no swap,1: MOSI and MISO are swapped" newline hexmask.long.byte 0x8 4.--7. 1. "MIDI,master Inter-Data Idleness" hexmask.long.byte 0x8 0.--3. 1. "MSSI,master SS idleness" newline endif sif (cpuis("STM32MP151*")) bitfld.long 0x8 31. "AFCNTR,AFCNTR" "0,1" bitfld.long 0x8 30. "SSOM,SSOM" "0,1" newline bitfld.long 0x8 29. "SSOE,SSOE" "0,1" bitfld.long 0x8 28. "SSIOP,SSIOP" "0,1" newline endif sif (cpuis("STM32MP151*")) bitfld.long 0x8 26. "SSM,SSM" "0,1" bitfld.long 0x8 25. "CPOL,CPOL" "0,1" newline bitfld.long 0x8 24. "CPHA,CPHA" "0,1" bitfld.long 0x8 23. "LSBFRST,LSBFRST" "0,1" newline bitfld.long 0x8 22. "MASTER,MASTER" "0,1" bitfld.long 0x8 19.--21. "SP,SP" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 17.--18. "COMM,COMM" "0,1,2,3" endif sif (cpuis("STM32MP151*")) bitfld.long 0x8 15. "IOSWP,IOSWP" "0,1" newline endif sif (cpuis("STM32MP151*")) hexmask.long.byte 0x8 4.--7. 1. "MIDI,MIDI" endif group.long 0x40++0x13 line.long 0x0 "SPI_CRCPOLY,SPI polynomial register" hexmask.long 0x0 0.--31. 1. "CRCPOLY,CRC polynomial register" line.long 0x4 "SPI_TXCRC,SPI transmitter CRC register" sif (cpuis("STM32MP13*")) hexmask.long 0x4 0.--31. 1. "TXCRC,CRC register for transmitter" endif sif (cpuis("STM32MP151*")) hexmask.long 0x4 0.--31. 1. "TXCRC,TXCRC" endif line.long 0x8 "SPI_RXCRC,SPI receiver CRC register" sif (cpuis("STM32MP13*")) hexmask.long 0x8 0.--31. 1. "RXCRC,CRC register for receiver" endif sif (cpuis("STM32MP151*")) hexmask.long 0x8 0.--31. 1. "RXCRC,RXCRC" endif line.long 0xC "SPI_UDRDR,SPI underrun data register" hexmask.long 0xC 0.--31. 1. "UDRDR,data at slave underrun condition" line.long 0x10 "SPI_I2SCFGR,SPI/I2S configuration register" sif (cpuis("STM32MP13*")) bitfld.long 0x10 25. "MCKOE,master clock output enable" "0: Master clock output is disabled,1: Master clock output is enabled" bitfld.long 0x10 24. "ODD,odd factor for the prescaler" "0: Real divider value is = I2SDIV *2,1: Real divider value is = (I2SDIV * 2) + 1" newline bitfld.long 0x10 14. "DATFMT,data format" "0: the data inside the SPI_RXDR or SPI_TXDR are..,1: the data inside the SPI_RXDR or SPI_TXDR are.." bitfld.long 0x10 13. "WSINV,Word select inversion" "0: in I2S Philips standard Left channel is..,1: in I2S Philips standard Left channel is.." newline bitfld.long 0x10 12. "FIXCH,fixed channel length in slave" "0: the channel length in slave mode is different..,1: the channel length in slave mode is supposed to.." bitfld.long 0x10 11. "CKPOL,serial audio clock polarity" "0: the signals generated by the SPI/I2S (i.e. SDO..,1: the signals generated by the SPI/I2S (i.e. SDO.." newline bitfld.long 0x10 10. "CHLEN,channel length (number of bits per audio channel)" "0: 16-bit wide,1: 32-bit wide" bitfld.long 0x10 8.--9. "DATLEN,data length to be transferred" "0: 16-bit data length,1: 24-bit data length,2: 32-bit data length,3: not allowed" newline bitfld.long 0x10 7. "PCMSYNC,PCM frame synchronization" "0: short frame synchronization,1: long frame synchronization" bitfld.long 0x10 4.--5. "I2SSTD,I2S standard selection" "0: I2S Philips standard.,1: MSB justified standard (left justified),2: LSB justified standard (right justified),3: PCM standard" newline bitfld.long 0x10 1.--3. "I2SCFG,I2S configuration mode" "0: slave - transmit,1: slave - receive,2: master - transmit,3: master - receive,4: slave - full duplex,5: master - full duplex,?,?" bitfld.long 0x10 0. "I2SMOD,I2S mode selection" "0: SPI mode is selected,1: I2S/PCM mode is selected" newline endif sif (cpuis("STM32MP151*")) bitfld.long 0x10 25. "MCKOE,MCKOE" "0,1" bitfld.long 0x10 24. "ODD,ODD" "0,1" newline endif hexmask.long.byte 0x10 16.--23. 1. "I2SDIV,I2S linear prescaler" sif (cpuis("STM32MP151*")) bitfld.long 0x10 14. "DATFMT,DATFMT" "0,1" newline bitfld.long 0x10 13. "WSINV,WSINV" "0,1" bitfld.long 0x10 12. "FIXCH,FIXCH" "0,1" newline bitfld.long 0x10 11. "CKPOL,CKPOL" "0,1" bitfld.long 0x10 10. "CHLEN,CHLEN" "0,1" newline bitfld.long 0x10 8.--9. "DATLEN,DATLEN" "0,1,2,3" bitfld.long 0x10 7. "PCMSYNC,PCMSYNC" "0,1" newline endif sif (cpuis("STM32MP151*")) bitfld.long 0x10 4.--5. "I2SSTD,I2SSTD" "0,1,2,3" bitfld.long 0x10 1.--3. "I2SCFG,I2SCFG" "0,1,2,3,4,5,6,7" endif group.long 0x3F0++0x3 line.long 0x0 "SPI_I2S_HWCFGR,SPI/I2S hardware configuration register" sif (cpuis("STM32MP13*")) hexmask.long.byte 0x0 16.--19. 1. "DSCFG,SPI data size configuration" hexmask.long.byte 0x0 12.--15. 1. "I2SCFG,I2S configuration" newline hexmask.long.byte 0x0 8.--11. 1. "CRCCFG,CRC configuration for SPI" hexmask.long.byte 0x0 4.--7. 1. "RXFCFG,RxFIFO size" newline hexmask.long.byte 0x0 0.--3. 1. "TXFCFG,TxFIFO size" endif sif (cpuis("STM32MP151*")) hexmask.long.byte 0x0 16.--19. 1. "DSCFG,DSCFG" newline hexmask.long.byte 0x0 12.--15. 1. "I2SCFG,I2SCFG" hexmask.long.byte 0x0 8.--11. 1. "CRCCFG,CRCCFG" newline hexmask.long.byte 0x0 4.--7. 1. "RXFCFG,RXFCFG" hexmask.long.byte 0x0 0.--3. 1. "TXFCFG,TXFCFG" endif rgroup.long 0x3F4++0x3 line.long 0x0 "SPI_VERR,SPI/I2S version register" sif (cpuis("STM32MP13*")) hexmask.long.byte 0x0 4.--7. 1. "MAJREV,major revision of the IP." hexmask.long.byte 0x0 0.--3. 1. "MINREV,minor revision of the IP." newline endif sif (cpuis("STM32MP151*")) hexmask.long.byte 0x0 4.--7. 1. "MAJREV,MAJREV" hexmask.long.byte 0x0 0.--3. 1. "MINREV,MINREV" endif group.long 0x3F8++0x7 line.long 0x0 "SPI_IPIDR,SPI/I2S identification register" sif (cpuis("STM32MP13*")) hexmask.long 0x0 0.--31. 1. "ID,IP identification" endif sif (cpuis("STM32MP151*")) hexmask.long 0x0 0.--31. 1. "ID,ID" endif line.long 0x4 "SPI_SIDR,SPI/I2S size identification register" sif (cpuis("STM32MP13*")) hexmask.long 0x4 0.--31. 1. "SID,size identification" endif sif (cpuis("STM32MP151*")) hexmask.long 0x4 0.--31. 1. "SID,SID" endif sif (cpuis("STM32MP151*")) rgroup.long 0x44++0x3 line.long 0x0 "SPI_TXCRC,SPI transmitter CRC register" endif sif (cpuis("STM32MP151*")) rgroup.long 0x48++0x3 line.long 0x0 "SPI_RXCRC,SPI receiver CRC register" endif sif (cpuis("STM32MP151*")) rgroup.long 0x3F0++0x3 line.long 0x0 "SPI_I2S_HWCFGR,SPI/I2S hardware configuration register" endif sif (cpuis("STM32MP151*")) rgroup.long 0x3F4++0x3 line.long 0x0 "SPI_VERR,SPI/I2S version register" endif sif (cpuis("STM32MP151*")) rgroup.long 0x3F8++0x3 line.long 0x0 "SPI_IPIDR,SPI/I2S identification register" endif sif (cpuis("STM32MP151*")) rgroup.long 0x3FC++0x3 line.long 0x0 "SPI_SIDR,SPI/I2S size identification register" endif tree.end endif sif (cpuis("STM32MP13*")||cpuis("STM32MP151*")) tree "SPI3" base ad:0x4000C000 sif (cpuis("STM32MP13*")) group.long 0x0++0x3 line.long 0x0 "SPI_CR1,SPI/I2S control register 1" bitfld.long 0x0 16. "IOLOCK,locking the AF configuration of associated IOs" "0: AF configuration is not locked,1: AF configuration is locked" bitfld.long 0x0 15. "TCRCINI,CRC calculation initialization pattern control for transmitter" "0: All zero pattern is applied,1: All ones pattern is applied" newline bitfld.long 0x0 14. "RCRCINI,CRC calculation initialization pattern control for receiver" "0: all zero pattern is applied,1: all ones pattern is applied" bitfld.long 0x0 13. "CRC33_17,32-bit CRC polynomial configuration" "0: full size (33-bit or 17-bit) CRC polynomial is..,1: full size (33-bit or 17-bit) CRC polynomial is.." newline bitfld.long 0x0 12. "SSI,internal SS signal input level" "0,1" bitfld.long 0x0 11. "HDDIR,Rx/Tx direction at Half-duplex mode" "0: SPI is Receiver,1: SPI is transmitter" newline bitfld.long 0x0 10. "CSUSP,master suspend request" "0,1" bitfld.long 0x0 9. "CSTART,master transfer start" "0: master transfer is at idle,1: master transfer is on-going or temporary.." newline bitfld.long 0x0 8. "MASRX,master automatic SUSP in Receive mode" "0: SPI flow/clock generation is continuous..,1: SPI flow is suspended temporary on RxFIFO full.." bitfld.long 0x0 0. "SPE,serial peripheral enable" "0: serial peripheral disabled.,1: serial peripheral enabled" group.long 0x10++0x3 line.long 0x0 "SPI_IER,SPI/I2S interrupt enable register" bitfld.long 0x0 10. "TSERFIE,additional number of transactions reload interrupt enable" "0: TSERF interrupt disabled,1: TSERF interrupt enabled" bitfld.long 0x0 9. "MODFIE,mode fault interrupt enable" "0: MODF interrupt disabled,1: MODF interrupt enabled" newline bitfld.long 0x0 8. "TIFREIE,TIFRE interrupt enable" "0: TIFRE interrupt disabled,1: TIFRE interrupt enabled" bitfld.long 0x0 7. "CRCEIE,CRC error interrupt enable" "0: CRC interrupt disabled,1: CRC interrupt enabled" newline bitfld.long 0x0 6. "OVRIE,OVR interrupt enable" "0: OVR interrupt disabled,1: OVR interrupt enabled" bitfld.long 0x0 5. "UDRIE,UDR interrupt enable" "0: UDR interrupt disabled,1: UDR interrupt enabled" newline bitfld.long 0x0 4. "TXTFIE,TXTFIE interrupt enable" "0: TXTF interrupt disabled,1: TXTF interrupt enabled" bitfld.long 0x0 3. "EOTIE,EOT SUSP and TXC interrupt enable" "0: EOT/SUSP/TXC interrupt disabled,1: EOT/SUSP/TXC interrupt enabled" newline bitfld.long 0x0 2. "DXPIE,DXP interrupt enabled" "0: DXP interrupt disabled,1: DXP interrupt enabled" bitfld.long 0x0 1. "TXPIE,TXP interrupt enable" "0: TXP interrupt disabled,1: TXP interrupt enabled" newline bitfld.long 0x0 0. "RXPIE,RXP Interrupt Enable" "0: RXP interrupt disabled,1: RXP interrupt enabled" rgroup.long 0x14++0x3 line.long 0x0 "SPI_SR,SPI/I2S status register" hexmask.long.word 0x0 16.--31. 1. "CTSIZE,number of data frames remaining in current TSIZE session" bitfld.long 0x0 15. "RXWNE,RxFIFO word not empty" "0: less than four bytes of RxFIFO space is occupied..,1: at least four bytes of RxFIFO space is occupied.." newline bitfld.long 0x0 13.--14. "RXPLVL,RxFIFO packing leveL" "0: no next frame is available at RxFIFO,1: 1 frame is available,2: 2 frames are available*,3: 3 frames are available*" bitfld.long 0x0 12. "TXC,TxFIFO transmission complete" "0: Current data transaction is still ongoing data..,1: Last TxFIFO frame transmission completed" newline bitfld.long 0x0 11. "SUSP,suspension status" "0: SPI not suspended (master mode active or other..,1: Master mode is suspended (current frame.." bitfld.long 0x0 10. "TSERF,additional number of SPI data to be transacted was reload" "0: no acceptation,1: additional number of data accepted current.." newline bitfld.long 0x0 9. "MODF,mode fault" "0: no mode fault,1: mode fault detected" bitfld.long 0x0 8. "TIFRE,TI frame format error" "0: no TI Frame Error,1: TI Frame Error detected" newline bitfld.long 0x0 7. "CRCE,CRC error" "0: no CRC error,1: CRC error detected" bitfld.long 0x0 6. "OVR,overrun" "0: no overrun,1: overrun detected" newline bitfld.long 0x0 5. "UDR,underrun at slave transmission mode" "0: no underrun,1: underrun detected" bitfld.long 0x0 4. "TXTF,transmission transfer filled" "0: upload of TxFIFO is on-going or not started,1: TxFIFO upload is finished" newline bitfld.long 0x0 3. "EOT,end of transfer" "0: transfer is on-going or not started,1: transfer complete" bitfld.long 0x0 2. "DXP,duplex packet" "0: TxFIFO is Full and/or RxFIFO is Empty,1: Both TxFIFO has space for write and RxFIFO.." newline bitfld.long 0x0 1. "TXP,Tx-packet space available" "0: there is not enough space to locate next data..,1: TxFIFO has enough free location to host 1 data.." bitfld.long 0x0 0. "RXP,Rx-packet available" "0: RxFIFO is empty or a not complete data packet is..,1: RxFIFO contains at least 1 data packet" wgroup.long 0x18++0x3 line.long 0x0 "SPI_IFCR,SPI/I2S interrupt/status flags clear register" bitfld.long 0x0 11. "SUSPC,SUSPend flag clear" "0,1" bitfld.long 0x0 10. "TSERFC,TSERFC flag clear" "0,1" newline bitfld.long 0x0 9. "MODFC,mode fault flag clear" "0,1" bitfld.long 0x0 8. "TIFREC,TI frame format error flag clear" "0,1" newline bitfld.long 0x0 7. "CRCEC,CRC error flag clear" "0,1" bitfld.long 0x0 6. "OVRC,overrun flag clear" "0,1" newline bitfld.long 0x0 5. "UDRC,underrun flag clear" "0,1" bitfld.long 0x0 4. "TXTFC,transmission Transfer Filled flag clear" "0,1" newline bitfld.long 0x0 3. "EOTC,end of transfer flag clear" "0,1" wgroup.long 0x20++0x3 line.long 0x0 "SPI_TXDR,SPI/I2S transmit data register" hexmask.long 0x0 0.--31. 1. "TXDR,transmit data register" rgroup.long 0x30++0x3 line.long 0x0 "SPI_RXDR,SPI/I2S receive data register" hexmask.long 0x0 0.--31. 1. "RXDR,receive data register" endif sif (cpuis("STM32MP151*")) group.long 0x0++0x3 line.long 0x0 "SPI2S_CR1,SPI/I2S control register 1" bitfld.long 0x0 16. "IOLOCK,IOLOCK" "0,1" bitfld.long 0x0 15. "TCRCINI,TCRCINI" "0,1" newline bitfld.long 0x0 14. "RCRCINI,RCRCINI" "0,1" bitfld.long 0x0 13. "CRC33_17,CRC33_17" "0,1" newline bitfld.long 0x0 12. "SSI,SSI" "0,1" bitfld.long 0x0 11. "HDDIR,HDDIR" "0,1" newline bitfld.long 0x0 10. "CSUSP,CSUSP" "0,1" bitfld.long 0x0 9. "CSTART,CSTART" "0,1" newline bitfld.long 0x0 8. "MASRX,MASRX" "0,1" bitfld.long 0x0 0. "SPE,SPE" "0,1" group.long 0x10++0x3 line.long 0x0 "SPI2S_IER,SPI/I2S interrupt enable register" bitfld.long 0x0 10. "TSERFIE,TSERFIE" "0,1" bitfld.long 0x0 9. "MODFIE,MODFIE" "0,1" newline bitfld.long 0x0 8. "TIFREIE,TIFREIE" "0,1" bitfld.long 0x0 7. "CRCEIE,CRCEIE" "0,1" newline bitfld.long 0x0 6. "OVRIE,OVRIE" "0,1" bitfld.long 0x0 5. "UDRIE,UDRIE" "0,1" newline bitfld.long 0x0 4. "TXTFIE,TXTFIE" "0,1" bitfld.long 0x0 3. "EOTIE,EOTIE" "0,1" newline bitfld.long 0x0 2. "DXPIE,DXPIE" "0,1" bitfld.long 0x0 1. "TXPIE,TXPIE" "0,1" newline bitfld.long 0x0 0. "RXPIE,RXPIE" "0,1" rgroup.long 0x14++0x3 line.long 0x0 "SPI2S_SR,SPI/I2S status register" hexmask.long.word 0x0 16.--31. 1. "CTSIZE,CTSIZE" bitfld.long 0x0 15. "RXWNE,RXWNE" "0,1" newline bitfld.long 0x0 13.--14. "RXPLVL,RXPLVL" "0,1,2,3" bitfld.long 0x0 12. "TXC,TXC" "0,1" newline bitfld.long 0x0 11. "SUSP,SUSP" "0,1" bitfld.long 0x0 10. "TSERF,TSERF" "0,1" newline bitfld.long 0x0 9. "MODF,MODF" "0,1" bitfld.long 0x0 8. "TIFRE,TIFRE" "0,1" newline bitfld.long 0x0 7. "CRCE,CRCE" "0,1" bitfld.long 0x0 6. "OVR,OVR" "0,1" newline bitfld.long 0x0 5. "UDR,UDR" "0,1" bitfld.long 0x0 4. "TXTF,TXTF" "0,1" newline bitfld.long 0x0 3. "EOT,EOT" "0,1" bitfld.long 0x0 2. "DXP,DXP" "0,1" newline bitfld.long 0x0 1. "TXP,TXP" "0,1" bitfld.long 0x0 0. "RXP,RXP" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "SPI2S_IFCR,SPI/I2S interrupt/status flags clear register" bitfld.long 0x0 11. "SUSPC,SUSPC" "0,1" bitfld.long 0x0 10. "TSERFC,TSERFC" "0,1" newline bitfld.long 0x0 9. "MODFC,MODFC" "0,1" bitfld.long 0x0 8. "TIFREC,TIFREC" "0,1" newline bitfld.long 0x0 7. "CRCEC,CRCEC" "0,1" bitfld.long 0x0 6. "OVRC,OVRC" "0,1" newline bitfld.long 0x0 5. "UDRC,UDRC" "0,1" bitfld.long 0x0 4. "TXTFC,TXTFC" "0,1" newline bitfld.long 0x0 3. "EOTC,EOTC" "0,1" wgroup.long 0x20++0x3 line.long 0x0 "SPI2S_TXDR,SPI/I2S transmit data register" hexmask.long 0x0 0.--31. 1. "TXDR,TXDR" rgroup.long 0x30++0x3 line.long 0x0 "SPI2S_RXDR,SPI/I2S receive data register" hexmask.long 0x0 0.--31. 1. "RXDR,RXDR" endif group.long 0x4++0xB line.long 0x0 "SPI_CR2,SPI control register 2" hexmask.long.word 0x0 16.--31. 1. "TSER,number of data transfer extension to be reload into TSIZE just when a previous number of data stored at TSIZE is transacted" hexmask.long.word 0x0 0.--15. 1. "TSIZE,number of data at current transfer" line.long 0x4 "SPI_CFG1,SPI configuration register 1" sif (cpuis("STM32MP13*")) bitfld.long 0x4 28.--30. "MBR,master baud rate" "0: SPI master clock/2,1: SPI master clock/4,2: SPI master clock/8,3: SPI master clock/16,4: SPI master clock/32,5: SPI master clock/64,6: SPI master clock/128,7: SPI master clock/256" bitfld.long 0x4 22. "CRCEN,hardware CRC computation enable" "0: CRC calculation disabled,1: CRC calculation Enabled" newline hexmask.long.byte 0x4 16.--20. 1. "CRCSIZE,length of CRC frame to be transacted and compared" bitfld.long 0x4 15. "TXDMAEN,Tx DMA stream enable" "0: Tx DMA disabled,1: Tx DMA enabled" newline bitfld.long 0x4 14. "RXDMAEN,Rx DMA stream enable" "0: Rx-DMA disabled,1: Rx-DMA enabled" bitfld.long 0x4 11.--12. "UDRDET,detection of underrun condition at slave transmitter" "0: underrun is detected at begin of data frame (no..,1: underrun is detected at end of last data frame,2: underrun is detected by begin of active SS signal,?" newline bitfld.long 0x4 9.--10. "UDRCFG,behavior of slave transmitter at underrun condition" "0: slave sends a constant pattern defined by the..,1: slave repeats lastly received data frame from..,2: slave repeats its lastly transmitted data frame,?" hexmask.long.byte 0x4 5.--8. 1. "FTHLV,FIFO threshold level" newline hexmask.long.byte 0x4 0.--4. 1. "DSIZE,number of bits in at single SPI data frame" endif sif (cpuis("STM32MP151*")) bitfld.long 0x4 28.--30. "MBR,MBR" "0,1,2,3,4,5,6,7" newline endif sif (cpuis("STM32MP151*")) bitfld.long 0x4 22. "CRCEN,CRCEN" "0,1" endif sif (cpuis("STM32MP151*")) hexmask.long.byte 0x4 16.--20. 1. "CRCSIZE,CRCSIZE" newline bitfld.long 0x4 15. "TXDMAEN,TXDMAEN" "0,1" bitfld.long 0x4 14. "RXDMAEN,RXDMAEN" "0,1" newline endif sif (cpuis("STM32MP151*")) bitfld.long 0x4 11.--12. "UDRDET,UDRDET" "0,1,2,3" bitfld.long 0x4 9.--10. "UDRCFG,UDRCFG" "0,1,2,3" newline hexmask.long.byte 0x4 5.--8. 1. "FTHLV,FTHLV" endif line.long 0x8 "SPI_CFG2,SPI configuration register 2" sif (cpuis("STM32MP13*")) bitfld.long 0x8 31. "AFCNTR,alternate function GPIOs control" "0: the peripheral takes no control of GPIOs while..,1: the peripheral keeps always control of all.." bitfld.long 0x8 30. "SSOM,SS output management in master mode" "0: SS is kept at active level till data transfer is..,1: SPI data frames are interleaved with SS non.." newline bitfld.long 0x8 29. "SSOE,SS output enable" "0: SS output is disabled and the SPI can work in..,1: SS output is enabled. The SPI cannot work in a.." bitfld.long 0x8 28. "SSIOP,SS input/output polarity" "0: low level is active for SS signal,1: high level is active for SS signal" newline bitfld.long 0x8 26. "SSM,software management of SS signal input" "0: SS input value is determined by the SS PAD,1: SS input value is determined by the SSI bit" bitfld.long 0x8 25. "CPOL,clock polarity" "0: SCK signal is at 0 when idle,1: SCK signal is at 1 when idle" newline bitfld.long 0x8 24. "CPHA,clock phase" "0: the first clock transition is the first data..,1: the second clock transition is the first data.." bitfld.long 0x8 23. "LSBFRST,data frame format" "0: MSB transmitted first,1: LSB transmitted first" newline bitfld.long 0x8 22. "MASTER,SPI master" "0: SPI Slave,1: SPI Master" bitfld.long 0x8 19.--21. "SP,Serial protocol" "0: SPI Motorola,1: SPI TI,?,?,?,?,?,?" newline bitfld.long 0x8 17.--18. "COMM,SPI communication mode" "0: full-duplex,1: simplex transmitter,2: simplex receiver,3: half-duplex" bitfld.long 0x8 15. "IOSWP,swap functionality of MISO and MOSI pins" "0: no swap,1: MOSI and MISO are swapped" newline hexmask.long.byte 0x8 4.--7. 1. "MIDI,master Inter-Data Idleness" hexmask.long.byte 0x8 0.--3. 1. "MSSI,master SS idleness" newline endif sif (cpuis("STM32MP151*")) bitfld.long 0x8 31. "AFCNTR,AFCNTR" "0,1" bitfld.long 0x8 30. "SSOM,SSOM" "0,1" newline bitfld.long 0x8 29. "SSOE,SSOE" "0,1" bitfld.long 0x8 28. "SSIOP,SSIOP" "0,1" newline endif sif (cpuis("STM32MP151*")) bitfld.long 0x8 26. "SSM,SSM" "0,1" bitfld.long 0x8 25. "CPOL,CPOL" "0,1" newline bitfld.long 0x8 24. "CPHA,CPHA" "0,1" bitfld.long 0x8 23. "LSBFRST,LSBFRST" "0,1" newline bitfld.long 0x8 22. "MASTER,MASTER" "0,1" bitfld.long 0x8 19.--21. "SP,SP" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 17.--18. "COMM,COMM" "0,1,2,3" endif sif (cpuis("STM32MP151*")) bitfld.long 0x8 15. "IOSWP,IOSWP" "0,1" newline endif sif (cpuis("STM32MP151*")) hexmask.long.byte 0x8 4.--7. 1. "MIDI,MIDI" endif group.long 0x40++0x13 line.long 0x0 "SPI_CRCPOLY,SPI polynomial register" hexmask.long 0x0 0.--31. 1. "CRCPOLY,CRC polynomial register" line.long 0x4 "SPI_TXCRC,SPI transmitter CRC register" sif (cpuis("STM32MP13*")) hexmask.long 0x4 0.--31. 1. "TXCRC,CRC register for transmitter" endif sif (cpuis("STM32MP151*")) hexmask.long 0x4 0.--31. 1. "TXCRC,TXCRC" endif line.long 0x8 "SPI_RXCRC,SPI receiver CRC register" sif (cpuis("STM32MP13*")) hexmask.long 0x8 0.--31. 1. "RXCRC,CRC register for receiver" endif sif (cpuis("STM32MP151*")) hexmask.long 0x8 0.--31. 1. "RXCRC,RXCRC" endif line.long 0xC "SPI_UDRDR,SPI underrun data register" hexmask.long 0xC 0.--31. 1. "UDRDR,data at slave underrun condition" line.long 0x10 "SPI_I2SCFGR,SPI/I2S configuration register" sif (cpuis("STM32MP13*")) bitfld.long 0x10 25. "MCKOE,master clock output enable" "0: Master clock output is disabled,1: Master clock output is enabled" bitfld.long 0x10 24. "ODD,odd factor for the prescaler" "0: Real divider value is = I2SDIV *2,1: Real divider value is = (I2SDIV * 2) + 1" newline bitfld.long 0x10 14. "DATFMT,data format" "0: the data inside the SPI_RXDR or SPI_TXDR are..,1: the data inside the SPI_RXDR or SPI_TXDR are.." bitfld.long 0x10 13. "WSINV,Word select inversion" "0: in I2S Philips standard Left channel is..,1: in I2S Philips standard Left channel is.." newline bitfld.long 0x10 12. "FIXCH,fixed channel length in slave" "0: the channel length in slave mode is different..,1: the channel length in slave mode is supposed to.." bitfld.long 0x10 11. "CKPOL,serial audio clock polarity" "0: the signals generated by the SPI/I2S (i.e. SDO..,1: the signals generated by the SPI/I2S (i.e. SDO.." newline bitfld.long 0x10 10. "CHLEN,channel length (number of bits per audio channel)" "0: 16-bit wide,1: 32-bit wide" bitfld.long 0x10 8.--9. "DATLEN,data length to be transferred" "0: 16-bit data length,1: 24-bit data length,2: 32-bit data length,3: not allowed" newline bitfld.long 0x10 7. "PCMSYNC,PCM frame synchronization" "0: short frame synchronization,1: long frame synchronization" bitfld.long 0x10 4.--5. "I2SSTD,I2S standard selection" "0: I2S Philips standard.,1: MSB justified standard (left justified),2: LSB justified standard (right justified),3: PCM standard" newline bitfld.long 0x10 1.--3. "I2SCFG,I2S configuration mode" "0: slave - transmit,1: slave - receive,2: master - transmit,3: master - receive,4: slave - full duplex,5: master - full duplex,?,?" bitfld.long 0x10 0. "I2SMOD,I2S mode selection" "0: SPI mode is selected,1: I2S/PCM mode is selected" newline endif sif (cpuis("STM32MP151*")) bitfld.long 0x10 25. "MCKOE,MCKOE" "0,1" bitfld.long 0x10 24. "ODD,ODD" "0,1" newline endif hexmask.long.byte 0x10 16.--23. 1. "I2SDIV,I2S linear prescaler" sif (cpuis("STM32MP151*")) bitfld.long 0x10 14. "DATFMT,DATFMT" "0,1" newline bitfld.long 0x10 13. "WSINV,WSINV" "0,1" bitfld.long 0x10 12. "FIXCH,FIXCH" "0,1" newline bitfld.long 0x10 11. "CKPOL,CKPOL" "0,1" bitfld.long 0x10 10. "CHLEN,CHLEN" "0,1" newline bitfld.long 0x10 8.--9. "DATLEN,DATLEN" "0,1,2,3" bitfld.long 0x10 7. "PCMSYNC,PCMSYNC" "0,1" newline endif sif (cpuis("STM32MP151*")) bitfld.long 0x10 4.--5. "I2SSTD,I2SSTD" "0,1,2,3" bitfld.long 0x10 1.--3. "I2SCFG,I2SCFG" "0,1,2,3,4,5,6,7" endif group.long 0x3F0++0x3 line.long 0x0 "SPI_I2S_HWCFGR,SPI/I2S hardware configuration register" sif (cpuis("STM32MP13*")) hexmask.long.byte 0x0 16.--19. 1. "DSCFG,SPI data size configuration" hexmask.long.byte 0x0 12.--15. 1. "I2SCFG,I2S configuration" newline hexmask.long.byte 0x0 8.--11. 1. "CRCCFG,CRC configuration for SPI" hexmask.long.byte 0x0 4.--7. 1. "RXFCFG,RxFIFO size" newline hexmask.long.byte 0x0 0.--3. 1. "TXFCFG,TxFIFO size" endif sif (cpuis("STM32MP151*")) hexmask.long.byte 0x0 16.--19. 1. "DSCFG,DSCFG" newline hexmask.long.byte 0x0 12.--15. 1. "I2SCFG,I2SCFG" hexmask.long.byte 0x0 8.--11. 1. "CRCCFG,CRCCFG" newline hexmask.long.byte 0x0 4.--7. 1. "RXFCFG,RXFCFG" hexmask.long.byte 0x0 0.--3. 1. "TXFCFG,TXFCFG" endif rgroup.long 0x3F4++0x3 line.long 0x0 "SPI_VERR,SPI/I2S version register" sif (cpuis("STM32MP13*")) hexmask.long.byte 0x0 4.--7. 1. "MAJREV,major revision of the IP." hexmask.long.byte 0x0 0.--3. 1. "MINREV,minor revision of the IP." newline endif sif (cpuis("STM32MP151*")) hexmask.long.byte 0x0 4.--7. 1. "MAJREV,MAJREV" hexmask.long.byte 0x0 0.--3. 1. "MINREV,MINREV" endif group.long 0x3F8++0x7 line.long 0x0 "SPI_IPIDR,SPI/I2S identification register" sif (cpuis("STM32MP13*")) hexmask.long 0x0 0.--31. 1. "ID,IP identification" endif sif (cpuis("STM32MP151*")) hexmask.long 0x0 0.--31. 1. "ID,ID" endif line.long 0x4 "SPI_SIDR,SPI/I2S size identification register" sif (cpuis("STM32MP13*")) hexmask.long 0x4 0.--31. 1. "SID,size identification" endif sif (cpuis("STM32MP151*")) hexmask.long 0x4 0.--31. 1. "SID,SID" endif sif (cpuis("STM32MP151*")) rgroup.long 0x44++0x3 line.long 0x0 "SPI_TXCRC,SPI transmitter CRC register" endif sif (cpuis("STM32MP151*")) rgroup.long 0x48++0x3 line.long 0x0 "SPI_RXCRC,SPI receiver CRC register" endif sif (cpuis("STM32MP151*")) rgroup.long 0x3F0++0x3 line.long 0x0 "SPI_I2S_HWCFGR,SPI/I2S hardware configuration register" endif sif (cpuis("STM32MP151*")) rgroup.long 0x3F4++0x3 line.long 0x0 "SPI_VERR,SPI/I2S version register" endif sif (cpuis("STM32MP151*")) rgroup.long 0x3F8++0x3 line.long 0x0 "SPI_IPIDR,SPI/I2S identification register" endif sif (cpuis("STM32MP151*")) rgroup.long 0x3FC++0x3 line.long 0x0 "SPI_SIDR,SPI/I2S size identification register" endif tree.end endif sif (cpuis("STM32MP13*")) base ad:0x4C002000 elif (cpuis("STM32MP151*")) base ad:0x44005000 endif sif (cpuis("STM32MP13*")||cpuis("STM32MP151*")) tree "SPI4" sif (cpuis("STM32MP13*")) group.long 0x0++0x3 line.long 0x0 "SPI_CR1,SPI/I2S control register 1" bitfld.long 0x0 16. "IOLOCK,locking the AF configuration of associated IOs" "0: AF configuration is not locked,1: AF configuration is locked" bitfld.long 0x0 15. "TCRCINI,CRC calculation initialization pattern control for transmitter" "0: All zero pattern is applied,1: All ones pattern is applied" newline bitfld.long 0x0 14. "RCRCINI,CRC calculation initialization pattern control for receiver" "0: all zero pattern is applied,1: all ones pattern is applied" bitfld.long 0x0 13. "CRC33_17,32-bit CRC polynomial configuration" "0: full size (33-bit or 17-bit) CRC polynomial is..,1: full size (33-bit or 17-bit) CRC polynomial is.." newline bitfld.long 0x0 12. "SSI,internal SS signal input level" "0,1" bitfld.long 0x0 11. "HDDIR,Rx/Tx direction at Half-duplex mode" "0: SPI is Receiver,1: SPI is transmitter" newline bitfld.long 0x0 10. "CSUSP,master suspend request" "0,1" bitfld.long 0x0 9. "CSTART,master transfer start" "0: master transfer is at idle,1: master transfer is on-going or temporary.." newline bitfld.long 0x0 8. "MASRX,master automatic SUSP in Receive mode" "0: SPI flow/clock generation is continuous..,1: SPI flow is suspended temporary on RxFIFO full.." bitfld.long 0x0 0. "SPE,serial peripheral enable" "0: serial peripheral disabled.,1: serial peripheral enabled" group.long 0x10++0x3 line.long 0x0 "SPI_IER,SPI/I2S interrupt enable register" bitfld.long 0x0 10. "TSERFIE,additional number of transactions reload interrupt enable" "0: TSERF interrupt disabled,1: TSERF interrupt enabled" bitfld.long 0x0 9. "MODFIE,mode fault interrupt enable" "0: MODF interrupt disabled,1: MODF interrupt enabled" newline bitfld.long 0x0 8. "TIFREIE,TIFRE interrupt enable" "0: TIFRE interrupt disabled,1: TIFRE interrupt enabled" bitfld.long 0x0 7. "CRCEIE,CRC error interrupt enable" "0: CRC interrupt disabled,1: CRC interrupt enabled" newline bitfld.long 0x0 6. "OVRIE,OVR interrupt enable" "0: OVR interrupt disabled,1: OVR interrupt enabled" bitfld.long 0x0 5. "UDRIE,UDR interrupt enable" "0: UDR interrupt disabled,1: UDR interrupt enabled" newline bitfld.long 0x0 4. "TXTFIE,TXTFIE interrupt enable" "0: TXTF interrupt disabled,1: TXTF interrupt enabled" bitfld.long 0x0 3. "EOTIE,EOT SUSP and TXC interrupt enable" "0: EOT/SUSP/TXC interrupt disabled,1: EOT/SUSP/TXC interrupt enabled" newline bitfld.long 0x0 2. "DXPIE,DXP interrupt enabled" "0: DXP interrupt disabled,1: DXP interrupt enabled" bitfld.long 0x0 1. "TXPIE,TXP interrupt enable" "0: TXP interrupt disabled,1: TXP interrupt enabled" newline bitfld.long 0x0 0. "RXPIE,RXP Interrupt Enable" "0: RXP interrupt disabled,1: RXP interrupt enabled" rgroup.long 0x14++0x3 line.long 0x0 "SPI_SR,SPI/I2S status register" hexmask.long.word 0x0 16.--31. 1. "CTSIZE,number of data frames remaining in current TSIZE session" bitfld.long 0x0 15. "RXWNE,RxFIFO word not empty" "0: less than four bytes of RxFIFO space is occupied..,1: at least four bytes of RxFIFO space is occupied.." newline bitfld.long 0x0 13.--14. "RXPLVL,RxFIFO packing leveL" "0: no next frame is available at RxFIFO,1: 1 frame is available,2: 2 frames are available*,3: 3 frames are available*" bitfld.long 0x0 12. "TXC,TxFIFO transmission complete" "0: Current data transaction is still ongoing data..,1: Last TxFIFO frame transmission completed" newline bitfld.long 0x0 11. "SUSP,suspension status" "0: SPI not suspended (master mode active or other..,1: Master mode is suspended (current frame.." bitfld.long 0x0 10. "TSERF,additional number of SPI data to be transacted was reload" "0: no acceptation,1: additional number of data accepted current.." newline bitfld.long 0x0 9. "MODF,mode fault" "0: no mode fault,1: mode fault detected" bitfld.long 0x0 8. "TIFRE,TI frame format error" "0: no TI Frame Error,1: TI Frame Error detected" newline bitfld.long 0x0 7. "CRCE,CRC error" "0: no CRC error,1: CRC error detected" bitfld.long 0x0 6. "OVR,overrun" "0: no overrun,1: overrun detected" newline bitfld.long 0x0 5. "UDR,underrun at slave transmission mode" "0: no underrun,1: underrun detected" bitfld.long 0x0 4. "TXTF,transmission transfer filled" "0: upload of TxFIFO is on-going or not started,1: TxFIFO upload is finished" newline bitfld.long 0x0 3. "EOT,end of transfer" "0: transfer is on-going or not started,1: transfer complete" bitfld.long 0x0 2. "DXP,duplex packet" "0: TxFIFO is Full and/or RxFIFO is Empty,1: Both TxFIFO has space for write and RxFIFO.." newline bitfld.long 0x0 1. "TXP,Tx-packet space available" "0: there is not enough space to locate next data..,1: TxFIFO has enough free location to host 1 data.." bitfld.long 0x0 0. "RXP,Rx-packet available" "0: RxFIFO is empty or a not complete data packet is..,1: RxFIFO contains at least 1 data packet" wgroup.long 0x18++0x3 line.long 0x0 "SPI_IFCR,SPI/I2S interrupt/status flags clear register" bitfld.long 0x0 11. "SUSPC,SUSPend flag clear" "0,1" bitfld.long 0x0 10. "TSERFC,TSERFC flag clear" "0,1" newline bitfld.long 0x0 9. "MODFC,mode fault flag clear" "0,1" bitfld.long 0x0 8. "TIFREC,TI frame format error flag clear" "0,1" newline bitfld.long 0x0 7. "CRCEC,CRC error flag clear" "0,1" bitfld.long 0x0 6. "OVRC,overrun flag clear" "0,1" newline bitfld.long 0x0 5. "UDRC,underrun flag clear" "0,1" bitfld.long 0x0 4. "TXTFC,transmission Transfer Filled flag clear" "0,1" newline bitfld.long 0x0 3. "EOTC,end of transfer flag clear" "0,1" wgroup.long 0x20++0x3 line.long 0x0 "SPI_TXDR,SPI/I2S transmit data register" hexmask.long 0x0 0.--31. 1. "TXDR,transmit data register" rgroup.long 0x30++0x3 line.long 0x0 "SPI_RXDR,SPI/I2S receive data register" hexmask.long 0x0 0.--31. 1. "RXDR,receive data register" endif sif (cpuis("STM32MP151*")) group.long 0x0++0x3 line.long 0x0 "SPI2S_CR1,SPI/I2S control register 1" bitfld.long 0x0 16. "IOLOCK,IOLOCK" "0,1" bitfld.long 0x0 15. "TCRCINI,TCRCINI" "0,1" newline bitfld.long 0x0 14. "RCRCINI,RCRCINI" "0,1" bitfld.long 0x0 13. "CRC33_17,CRC33_17" "0,1" newline bitfld.long 0x0 12. "SSI,SSI" "0,1" bitfld.long 0x0 11. "HDDIR,HDDIR" "0,1" newline bitfld.long 0x0 10. "CSUSP,CSUSP" "0,1" bitfld.long 0x0 9. "CSTART,CSTART" "0,1" newline bitfld.long 0x0 8. "MASRX,MASRX" "0,1" bitfld.long 0x0 0. "SPE,SPE" "0,1" group.long 0x10++0x3 line.long 0x0 "SPI2S_IER,SPI/I2S interrupt enable register" bitfld.long 0x0 10. "TSERFIE,TSERFIE" "0,1" bitfld.long 0x0 9. "MODFIE,MODFIE" "0,1" newline bitfld.long 0x0 8. "TIFREIE,TIFREIE" "0,1" bitfld.long 0x0 7. "CRCEIE,CRCEIE" "0,1" newline bitfld.long 0x0 6. "OVRIE,OVRIE" "0,1" bitfld.long 0x0 5. "UDRIE,UDRIE" "0,1" newline bitfld.long 0x0 4. "TXTFIE,TXTFIE" "0,1" bitfld.long 0x0 3. "EOTIE,EOTIE" "0,1" newline bitfld.long 0x0 2. "DXPIE,DXPIE" "0,1" bitfld.long 0x0 1. "TXPIE,TXPIE" "0,1" newline bitfld.long 0x0 0. "RXPIE,RXPIE" "0,1" rgroup.long 0x14++0x3 line.long 0x0 "SPI2S_SR,SPI/I2S status register" hexmask.long.word 0x0 16.--31. 1. "CTSIZE,CTSIZE" bitfld.long 0x0 15. "RXWNE,RXWNE" "0,1" newline bitfld.long 0x0 13.--14. "RXPLVL,RXPLVL" "0,1,2,3" bitfld.long 0x0 12. "TXC,TXC" "0,1" newline bitfld.long 0x0 11. "SUSP,SUSP" "0,1" bitfld.long 0x0 10. "TSERF,TSERF" "0,1" newline bitfld.long 0x0 9. "MODF,MODF" "0,1" bitfld.long 0x0 8. "TIFRE,TIFRE" "0,1" newline bitfld.long 0x0 7. "CRCE,CRCE" "0,1" bitfld.long 0x0 6. "OVR,OVR" "0,1" newline bitfld.long 0x0 5. "UDR,UDR" "0,1" bitfld.long 0x0 4. "TXTF,TXTF" "0,1" newline bitfld.long 0x0 3. "EOT,EOT" "0,1" bitfld.long 0x0 2. "DXP,DXP" "0,1" newline bitfld.long 0x0 1. "TXP,TXP" "0,1" bitfld.long 0x0 0. "RXP,RXP" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "SPI2S_IFCR,SPI/I2S interrupt/status flags clear register" bitfld.long 0x0 11. "SUSPC,SUSPC" "0,1" bitfld.long 0x0 10. "TSERFC,TSERFC" "0,1" newline bitfld.long 0x0 9. "MODFC,MODFC" "0,1" bitfld.long 0x0 8. "TIFREC,TIFREC" "0,1" newline bitfld.long 0x0 7. "CRCEC,CRCEC" "0,1" bitfld.long 0x0 6. "OVRC,OVRC" "0,1" newline bitfld.long 0x0 5. "UDRC,UDRC" "0,1" bitfld.long 0x0 4. "TXTFC,TXTFC" "0,1" newline bitfld.long 0x0 3. "EOTC,EOTC" "0,1" wgroup.long 0x20++0x3 line.long 0x0 "SPI2S_TXDR,SPI/I2S transmit data register" hexmask.long 0x0 0.--31. 1. "TXDR,TXDR" rgroup.long 0x30++0x3 line.long 0x0 "SPI2S_RXDR,SPI/I2S receive data register" hexmask.long 0x0 0.--31. 1. "RXDR,RXDR" endif group.long 0x4++0xB line.long 0x0 "SPI_CR2,SPI control register 2" hexmask.long.word 0x0 16.--31. 1. "TSER,number of data transfer extension to be reload into TSIZE just when a previous number of data stored at TSIZE is transacted" hexmask.long.word 0x0 0.--15. 1. "TSIZE,number of data at current transfer" line.long 0x4 "SPI_CFG1,SPI configuration register 1" sif (cpuis("STM32MP13*")) bitfld.long 0x4 28.--30. "MBR,master baud rate" "0: SPI master clock/2,1: SPI master clock/4,2: SPI master clock/8,3: SPI master clock/16,4: SPI master clock/32,5: SPI master clock/64,6: SPI master clock/128,7: SPI master clock/256" bitfld.long 0x4 22. "CRCEN,hardware CRC computation enable" "0: CRC calculation disabled,1: CRC calculation Enabled" newline hexmask.long.byte 0x4 16.--20. 1. "CRCSIZE,length of CRC frame to be transacted and compared" bitfld.long 0x4 15. "TXDMAEN,Tx DMA stream enable" "0: Tx DMA disabled,1: Tx DMA enabled" newline bitfld.long 0x4 14. "RXDMAEN,Rx DMA stream enable" "0: Rx-DMA disabled,1: Rx-DMA enabled" bitfld.long 0x4 11.--12. "UDRDET,detection of underrun condition at slave transmitter" "0: underrun is detected at begin of data frame (no..,1: underrun is detected at end of last data frame,2: underrun is detected by begin of active SS signal,?" newline bitfld.long 0x4 9.--10. "UDRCFG,behavior of slave transmitter at underrun condition" "0: slave sends a constant pattern defined by the..,1: slave repeats lastly received data frame from..,2: slave repeats its lastly transmitted data frame,?" hexmask.long.byte 0x4 5.--8. 1. "FTHLV,FIFO threshold level" newline hexmask.long.byte 0x4 0.--4. 1. "DSIZE,number of bits in at single SPI data frame" endif sif (cpuis("STM32MP151*")) bitfld.long 0x4 28.--30. "MBR,MBR" "0,1,2,3,4,5,6,7" newline endif sif (cpuis("STM32MP151*")) bitfld.long 0x4 22. "CRCEN,CRCEN" "0,1" endif sif (cpuis("STM32MP151*")) hexmask.long.byte 0x4 16.--20. 1. "CRCSIZE,CRCSIZE" newline bitfld.long 0x4 15. "TXDMAEN,TXDMAEN" "0,1" bitfld.long 0x4 14. "RXDMAEN,RXDMAEN" "0,1" newline endif sif (cpuis("STM32MP151*")) bitfld.long 0x4 11.--12. "UDRDET,UDRDET" "0,1,2,3" bitfld.long 0x4 9.--10. "UDRCFG,UDRCFG" "0,1,2,3" newline hexmask.long.byte 0x4 5.--8. 1. "FTHLV,FTHLV" endif line.long 0x8 "SPI_CFG2,SPI configuration register 2" sif (cpuis("STM32MP13*")) bitfld.long 0x8 31. "AFCNTR,alternate function GPIOs control" "0: the peripheral takes no control of GPIOs while..,1: the peripheral keeps always control of all.." bitfld.long 0x8 30. "SSOM,SS output management in master mode" "0: SS is kept at active level till data transfer is..,1: SPI data frames are interleaved with SS non.." newline bitfld.long 0x8 29. "SSOE,SS output enable" "0: SS output is disabled and the SPI can work in..,1: SS output is enabled. The SPI cannot work in a.." bitfld.long 0x8 28. "SSIOP,SS input/output polarity" "0: low level is active for SS signal,1: high level is active for SS signal" newline bitfld.long 0x8 26. "SSM,software management of SS signal input" "0: SS input value is determined by the SS PAD,1: SS input value is determined by the SSI bit" bitfld.long 0x8 25. "CPOL,clock polarity" "0: SCK signal is at 0 when idle,1: SCK signal is at 1 when idle" newline bitfld.long 0x8 24. "CPHA,clock phase" "0: the first clock transition is the first data..,1: the second clock transition is the first data.." bitfld.long 0x8 23. "LSBFRST,data frame format" "0: MSB transmitted first,1: LSB transmitted first" newline bitfld.long 0x8 22. "MASTER,SPI master" "0: SPI Slave,1: SPI Master" bitfld.long 0x8 19.--21. "SP,Serial protocol" "0: SPI Motorola,1: SPI TI,?,?,?,?,?,?" newline bitfld.long 0x8 17.--18. "COMM,SPI communication mode" "0: full-duplex,1: simplex transmitter,2: simplex receiver,3: half-duplex" bitfld.long 0x8 15. "IOSWP,swap functionality of MISO and MOSI pins" "0: no swap,1: MOSI and MISO are swapped" newline hexmask.long.byte 0x8 4.--7. 1. "MIDI,master Inter-Data Idleness" hexmask.long.byte 0x8 0.--3. 1. "MSSI,master SS idleness" newline endif sif (cpuis("STM32MP151*")) bitfld.long 0x8 31. "AFCNTR,AFCNTR" "0,1" bitfld.long 0x8 30. "SSOM,SSOM" "0,1" newline bitfld.long 0x8 29. "SSOE,SSOE" "0,1" bitfld.long 0x8 28. "SSIOP,SSIOP" "0,1" newline endif sif (cpuis("STM32MP151*")) bitfld.long 0x8 26. "SSM,SSM" "0,1" bitfld.long 0x8 25. "CPOL,CPOL" "0,1" newline bitfld.long 0x8 24. "CPHA,CPHA" "0,1" bitfld.long 0x8 23. "LSBFRST,LSBFRST" "0,1" newline bitfld.long 0x8 22. "MASTER,MASTER" "0,1" bitfld.long 0x8 19.--21. "SP,SP" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 17.--18. "COMM,COMM" "0,1,2,3" endif sif (cpuis("STM32MP151*")) bitfld.long 0x8 15. "IOSWP,IOSWP" "0,1" newline endif sif (cpuis("STM32MP151*")) hexmask.long.byte 0x8 4.--7. 1. "MIDI,MIDI" endif group.long 0x40++0x13 line.long 0x0 "SPI_CRCPOLY,SPI polynomial register" hexmask.long 0x0 0.--31. 1. "CRCPOLY,CRC polynomial register" line.long 0x4 "SPI_TXCRC,SPI transmitter CRC register" sif (cpuis("STM32MP13*")) hexmask.long 0x4 0.--31. 1. "TXCRC,CRC register for transmitter" endif sif (cpuis("STM32MP151*")) hexmask.long 0x4 0.--31. 1. "TXCRC,TXCRC" endif line.long 0x8 "SPI_RXCRC,SPI receiver CRC register" sif (cpuis("STM32MP13*")) hexmask.long 0x8 0.--31. 1. "RXCRC,CRC register for receiver" endif sif (cpuis("STM32MP151*")) hexmask.long 0x8 0.--31. 1. "RXCRC,RXCRC" endif line.long 0xC "SPI_UDRDR,SPI underrun data register" hexmask.long 0xC 0.--31. 1. "UDRDR,data at slave underrun condition" line.long 0x10 "SPI_I2SCFGR,SPI/I2S configuration register" sif (cpuis("STM32MP13*")) bitfld.long 0x10 25. "MCKOE,master clock output enable" "0: Master clock output is disabled,1: Master clock output is enabled" bitfld.long 0x10 24. "ODD,odd factor for the prescaler" "0: Real divider value is = I2SDIV *2,1: Real divider value is = (I2SDIV * 2) + 1" newline bitfld.long 0x10 14. "DATFMT,data format" "0: the data inside the SPI_RXDR or SPI_TXDR are..,1: the data inside the SPI_RXDR or SPI_TXDR are.." bitfld.long 0x10 13. "WSINV,Word select inversion" "0: in I2S Philips standard Left channel is..,1: in I2S Philips standard Left channel is.." newline bitfld.long 0x10 12. "FIXCH,fixed channel length in slave" "0: the channel length in slave mode is different..,1: the channel length in slave mode is supposed to.." bitfld.long 0x10 11. "CKPOL,serial audio clock polarity" "0: the signals generated by the SPI/I2S (i.e. SDO..,1: the signals generated by the SPI/I2S (i.e. SDO.." newline bitfld.long 0x10 10. "CHLEN,channel length (number of bits per audio channel)" "0: 16-bit wide,1: 32-bit wide" bitfld.long 0x10 8.--9. "DATLEN,data length to be transferred" "0: 16-bit data length,1: 24-bit data length,2: 32-bit data length,3: not allowed" newline bitfld.long 0x10 7. "PCMSYNC,PCM frame synchronization" "0: short frame synchronization,1: long frame synchronization" bitfld.long 0x10 4.--5. "I2SSTD,I2S standard selection" "0: I2S Philips standard.,1: MSB justified standard (left justified),2: LSB justified standard (right justified),3: PCM standard" newline bitfld.long 0x10 1.--3. "I2SCFG,I2S configuration mode" "0: slave - transmit,1: slave - receive,2: master - transmit,3: master - receive,4: slave - full duplex,5: master - full duplex,?,?" bitfld.long 0x10 0. "I2SMOD,I2S mode selection" "0: SPI mode is selected,1: I2S/PCM mode is selected" newline endif sif (cpuis("STM32MP151*")) bitfld.long 0x10 25. "MCKOE,MCKOE" "0,1" bitfld.long 0x10 24. "ODD,ODD" "0,1" newline endif hexmask.long.byte 0x10 16.--23. 1. "I2SDIV,I2S linear prescaler" sif (cpuis("STM32MP151*")) bitfld.long 0x10 14. "DATFMT,DATFMT" "0,1" newline bitfld.long 0x10 13. "WSINV,WSINV" "0,1" bitfld.long 0x10 12. "FIXCH,FIXCH" "0,1" newline bitfld.long 0x10 11. "CKPOL,CKPOL" "0,1" bitfld.long 0x10 10. "CHLEN,CHLEN" "0,1" newline bitfld.long 0x10 8.--9. "DATLEN,DATLEN" "0,1,2,3" bitfld.long 0x10 7. "PCMSYNC,PCMSYNC" "0,1" newline endif sif (cpuis("STM32MP151*")) bitfld.long 0x10 4.--5. "I2SSTD,I2SSTD" "0,1,2,3" bitfld.long 0x10 1.--3. "I2SCFG,I2SCFG" "0,1,2,3,4,5,6,7" endif group.long 0x3F0++0x3 line.long 0x0 "SPI_I2S_HWCFGR,SPI/I2S hardware configuration register" sif (cpuis("STM32MP13*")) hexmask.long.byte 0x0 16.--19. 1. "DSCFG,SPI data size configuration" hexmask.long.byte 0x0 12.--15. 1. "I2SCFG,I2S configuration" newline hexmask.long.byte 0x0 8.--11. 1. "CRCCFG,CRC configuration for SPI" hexmask.long.byte 0x0 4.--7. 1. "RXFCFG,RxFIFO size" newline hexmask.long.byte 0x0 0.--3. 1. "TXFCFG,TxFIFO size" endif sif (cpuis("STM32MP151*")) hexmask.long.byte 0x0 16.--19. 1. "DSCFG,DSCFG" newline hexmask.long.byte 0x0 12.--15. 1. "I2SCFG,I2SCFG" hexmask.long.byte 0x0 8.--11. 1. "CRCCFG,CRCCFG" newline hexmask.long.byte 0x0 4.--7. 1. "RXFCFG,RXFCFG" hexmask.long.byte 0x0 0.--3. 1. "TXFCFG,TXFCFG" endif rgroup.long 0x3F4++0x3 line.long 0x0 "SPI_VERR,SPI/I2S version register" sif (cpuis("STM32MP13*")) hexmask.long.byte 0x0 4.--7. 1. "MAJREV,major revision of the IP." hexmask.long.byte 0x0 0.--3. 1. "MINREV,minor revision of the IP." newline endif sif (cpuis("STM32MP151*")) hexmask.long.byte 0x0 4.--7. 1. "MAJREV,MAJREV" hexmask.long.byte 0x0 0.--3. 1. "MINREV,MINREV" endif group.long 0x3F8++0x7 line.long 0x0 "SPI_IPIDR,SPI/I2S identification register" sif (cpuis("STM32MP13*")) hexmask.long 0x0 0.--31. 1. "ID,IP identification" endif sif (cpuis("STM32MP151*")) hexmask.long 0x0 0.--31. 1. "ID,ID" endif line.long 0x4 "SPI_SIDR,SPI/I2S size identification register" sif (cpuis("STM32MP13*")) hexmask.long 0x4 0.--31. 1. "SID,size identification" endif sif (cpuis("STM32MP151*")) hexmask.long 0x4 0.--31. 1. "SID,SID" endif sif (cpuis("STM32MP151*")) rgroup.long 0x44++0x3 line.long 0x0 "SPI_TXCRC,SPI transmitter CRC register" endif sif (cpuis("STM32MP151*")) rgroup.long 0x48++0x3 line.long 0x0 "SPI_RXCRC,SPI receiver CRC register" endif sif (cpuis("STM32MP151*")) rgroup.long 0x3F0++0x3 line.long 0x0 "SPI_I2S_HWCFGR,SPI/I2S hardware configuration register" endif sif (cpuis("STM32MP151*")) rgroup.long 0x3F4++0x3 line.long 0x0 "SPI_VERR,SPI/I2S version register" endif sif (cpuis("STM32MP151*")) rgroup.long 0x3F8++0x3 line.long 0x0 "SPI_IPIDR,SPI/I2S identification register" endif sif (cpuis("STM32MP151*")) rgroup.long 0x3FC++0x3 line.long 0x0 "SPI_SIDR,SPI/I2S size identification register" endif tree.end endif sif (cpuis("STM32MP13*")) base ad:0x4C003000 elif (cpuis("STM32MP151*")) base ad:0x44009000 endif sif (cpuis("STM32MP13*")||cpuis("STM32MP151*")) tree "SPI5" sif (cpuis("STM32MP13*")) group.long 0x0++0x3 line.long 0x0 "SPI_CR1,SPI/I2S control register 1" bitfld.long 0x0 16. "IOLOCK,locking the AF configuration of associated IOs" "0: AF configuration is not locked,1: AF configuration is locked" bitfld.long 0x0 15. "TCRCINI,CRC calculation initialization pattern control for transmitter" "0: All zero pattern is applied,1: All ones pattern is applied" newline bitfld.long 0x0 14. "RCRCINI,CRC calculation initialization pattern control for receiver" "0: all zero pattern is applied,1: all ones pattern is applied" bitfld.long 0x0 13. "CRC33_17,32-bit CRC polynomial configuration" "0: full size (33-bit or 17-bit) CRC polynomial is..,1: full size (33-bit or 17-bit) CRC polynomial is.." newline bitfld.long 0x0 12. "SSI,internal SS signal input level" "0,1" bitfld.long 0x0 11. "HDDIR,Rx/Tx direction at Half-duplex mode" "0: SPI is Receiver,1: SPI is transmitter" newline bitfld.long 0x0 10. "CSUSP,master suspend request" "0,1" bitfld.long 0x0 9. "CSTART,master transfer start" "0: master transfer is at idle,1: master transfer is on-going or temporary.." newline bitfld.long 0x0 8. "MASRX,master automatic SUSP in Receive mode" "0: SPI flow/clock generation is continuous..,1: SPI flow is suspended temporary on RxFIFO full.." bitfld.long 0x0 0. "SPE,serial peripheral enable" "0: serial peripheral disabled.,1: serial peripheral enabled" group.long 0x10++0x3 line.long 0x0 "SPI_IER,SPI/I2S interrupt enable register" bitfld.long 0x0 10. "TSERFIE,additional number of transactions reload interrupt enable" "0: TSERF interrupt disabled,1: TSERF interrupt enabled" bitfld.long 0x0 9. "MODFIE,mode fault interrupt enable" "0: MODF interrupt disabled,1: MODF interrupt enabled" newline bitfld.long 0x0 8. "TIFREIE,TIFRE interrupt enable" "0: TIFRE interrupt disabled,1: TIFRE interrupt enabled" bitfld.long 0x0 7. "CRCEIE,CRC error interrupt enable" "0: CRC interrupt disabled,1: CRC interrupt enabled" newline bitfld.long 0x0 6. "OVRIE,OVR interrupt enable" "0: OVR interrupt disabled,1: OVR interrupt enabled" bitfld.long 0x0 5. "UDRIE,UDR interrupt enable" "0: UDR interrupt disabled,1: UDR interrupt enabled" newline bitfld.long 0x0 4. "TXTFIE,TXTFIE interrupt enable" "0: TXTF interrupt disabled,1: TXTF interrupt enabled" bitfld.long 0x0 3. "EOTIE,EOT SUSP and TXC interrupt enable" "0: EOT/SUSP/TXC interrupt disabled,1: EOT/SUSP/TXC interrupt enabled" newline bitfld.long 0x0 2. "DXPIE,DXP interrupt enabled" "0: DXP interrupt disabled,1: DXP interrupt enabled" bitfld.long 0x0 1. "TXPIE,TXP interrupt enable" "0: TXP interrupt disabled,1: TXP interrupt enabled" newline bitfld.long 0x0 0. "RXPIE,RXP Interrupt Enable" "0: RXP interrupt disabled,1: RXP interrupt enabled" rgroup.long 0x14++0x3 line.long 0x0 "SPI_SR,SPI/I2S status register" hexmask.long.word 0x0 16.--31. 1. "CTSIZE,number of data frames remaining in current TSIZE session" bitfld.long 0x0 15. "RXWNE,RxFIFO word not empty" "0: less than four bytes of RxFIFO space is occupied..,1: at least four bytes of RxFIFO space is occupied.." newline bitfld.long 0x0 13.--14. "RXPLVL,RxFIFO packing leveL" "0: no next frame is available at RxFIFO,1: 1 frame is available,2: 2 frames are available*,3: 3 frames are available*" bitfld.long 0x0 12. "TXC,TxFIFO transmission complete" "0: Current data transaction is still ongoing data..,1: Last TxFIFO frame transmission completed" newline bitfld.long 0x0 11. "SUSP,suspension status" "0: SPI not suspended (master mode active or other..,1: Master mode is suspended (current frame.." bitfld.long 0x0 10. "TSERF,additional number of SPI data to be transacted was reload" "0: no acceptation,1: additional number of data accepted current.." newline bitfld.long 0x0 9. "MODF,mode fault" "0: no mode fault,1: mode fault detected" bitfld.long 0x0 8. "TIFRE,TI frame format error" "0: no TI Frame Error,1: TI Frame Error detected" newline bitfld.long 0x0 7. "CRCE,CRC error" "0: no CRC error,1: CRC error detected" bitfld.long 0x0 6. "OVR,overrun" "0: no overrun,1: overrun detected" newline bitfld.long 0x0 5. "UDR,underrun at slave transmission mode" "0: no underrun,1: underrun detected" bitfld.long 0x0 4. "TXTF,transmission transfer filled" "0: upload of TxFIFO is on-going or not started,1: TxFIFO upload is finished" newline bitfld.long 0x0 3. "EOT,end of transfer" "0: transfer is on-going or not started,1: transfer complete" bitfld.long 0x0 2. "DXP,duplex packet" "0: TxFIFO is Full and/or RxFIFO is Empty,1: Both TxFIFO has space for write and RxFIFO.." newline bitfld.long 0x0 1. "TXP,Tx-packet space available" "0: there is not enough space to locate next data..,1: TxFIFO has enough free location to host 1 data.." bitfld.long 0x0 0. "RXP,Rx-packet available" "0: RxFIFO is empty or a not complete data packet is..,1: RxFIFO contains at least 1 data packet" wgroup.long 0x18++0x3 line.long 0x0 "SPI_IFCR,SPI/I2S interrupt/status flags clear register" bitfld.long 0x0 11. "SUSPC,SUSPend flag clear" "0,1" bitfld.long 0x0 10. "TSERFC,TSERFC flag clear" "0,1" newline bitfld.long 0x0 9. "MODFC,mode fault flag clear" "0,1" bitfld.long 0x0 8. "TIFREC,TI frame format error flag clear" "0,1" newline bitfld.long 0x0 7. "CRCEC,CRC error flag clear" "0,1" bitfld.long 0x0 6. "OVRC,overrun flag clear" "0,1" newline bitfld.long 0x0 5. "UDRC,underrun flag clear" "0,1" bitfld.long 0x0 4. "TXTFC,transmission Transfer Filled flag clear" "0,1" newline bitfld.long 0x0 3. "EOTC,end of transfer flag clear" "0,1" wgroup.long 0x20++0x3 line.long 0x0 "SPI_TXDR,SPI/I2S transmit data register" hexmask.long 0x0 0.--31. 1. "TXDR,transmit data register" rgroup.long 0x30++0x3 line.long 0x0 "SPI_RXDR,SPI/I2S receive data register" hexmask.long 0x0 0.--31. 1. "RXDR,receive data register" endif sif (cpuis("STM32MP151*")) group.long 0x0++0x3 line.long 0x0 "SPI2S_CR1,SPI/I2S control register 1" bitfld.long 0x0 16. "IOLOCK,IOLOCK" "0,1" bitfld.long 0x0 15. "TCRCINI,TCRCINI" "0,1" newline bitfld.long 0x0 14. "RCRCINI,RCRCINI" "0,1" bitfld.long 0x0 13. "CRC33_17,CRC33_17" "0,1" newline bitfld.long 0x0 12. "SSI,SSI" "0,1" bitfld.long 0x0 11. "HDDIR,HDDIR" "0,1" newline bitfld.long 0x0 10. "CSUSP,CSUSP" "0,1" bitfld.long 0x0 9. "CSTART,CSTART" "0,1" newline bitfld.long 0x0 8. "MASRX,MASRX" "0,1" bitfld.long 0x0 0. "SPE,SPE" "0,1" group.long 0x10++0x3 line.long 0x0 "SPI2S_IER,SPI/I2S interrupt enable register" bitfld.long 0x0 10. "TSERFIE,TSERFIE" "0,1" bitfld.long 0x0 9. "MODFIE,MODFIE" "0,1" newline bitfld.long 0x0 8. "TIFREIE,TIFREIE" "0,1" bitfld.long 0x0 7. "CRCEIE,CRCEIE" "0,1" newline bitfld.long 0x0 6. "OVRIE,OVRIE" "0,1" bitfld.long 0x0 5. "UDRIE,UDRIE" "0,1" newline bitfld.long 0x0 4. "TXTFIE,TXTFIE" "0,1" bitfld.long 0x0 3. "EOTIE,EOTIE" "0,1" newline bitfld.long 0x0 2. "DXPIE,DXPIE" "0,1" bitfld.long 0x0 1. "TXPIE,TXPIE" "0,1" newline bitfld.long 0x0 0. "RXPIE,RXPIE" "0,1" rgroup.long 0x14++0x3 line.long 0x0 "SPI2S_SR,SPI/I2S status register" hexmask.long.word 0x0 16.--31. 1. "CTSIZE,CTSIZE" bitfld.long 0x0 15. "RXWNE,RXWNE" "0,1" newline bitfld.long 0x0 13.--14. "RXPLVL,RXPLVL" "0,1,2,3" bitfld.long 0x0 12. "TXC,TXC" "0,1" newline bitfld.long 0x0 11. "SUSP,SUSP" "0,1" bitfld.long 0x0 10. "TSERF,TSERF" "0,1" newline bitfld.long 0x0 9. "MODF,MODF" "0,1" bitfld.long 0x0 8. "TIFRE,TIFRE" "0,1" newline bitfld.long 0x0 7. "CRCE,CRCE" "0,1" bitfld.long 0x0 6. "OVR,OVR" "0,1" newline bitfld.long 0x0 5. "UDR,UDR" "0,1" bitfld.long 0x0 4. "TXTF,TXTF" "0,1" newline bitfld.long 0x0 3. "EOT,EOT" "0,1" bitfld.long 0x0 2. "DXP,DXP" "0,1" newline bitfld.long 0x0 1. "TXP,TXP" "0,1" bitfld.long 0x0 0. "RXP,RXP" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "SPI2S_IFCR,SPI/I2S interrupt/status flags clear register" bitfld.long 0x0 11. "SUSPC,SUSPC" "0,1" bitfld.long 0x0 10. "TSERFC,TSERFC" "0,1" newline bitfld.long 0x0 9. "MODFC,MODFC" "0,1" bitfld.long 0x0 8. "TIFREC,TIFREC" "0,1" newline bitfld.long 0x0 7. "CRCEC,CRCEC" "0,1" bitfld.long 0x0 6. "OVRC,OVRC" "0,1" newline bitfld.long 0x0 5. "UDRC,UDRC" "0,1" bitfld.long 0x0 4. "TXTFC,TXTFC" "0,1" newline bitfld.long 0x0 3. "EOTC,EOTC" "0,1" wgroup.long 0x20++0x3 line.long 0x0 "SPI2S_TXDR,SPI/I2S transmit data register" hexmask.long 0x0 0.--31. 1. "TXDR,TXDR" rgroup.long 0x30++0x3 line.long 0x0 "SPI2S_RXDR,SPI/I2S receive data register" hexmask.long 0x0 0.--31. 1. "RXDR,RXDR" endif group.long 0x4++0xB line.long 0x0 "SPI_CR2,SPI control register 2" hexmask.long.word 0x0 16.--31. 1. "TSER,number of data transfer extension to be reload into TSIZE just when a previous number of data stored at TSIZE is transacted" hexmask.long.word 0x0 0.--15. 1. "TSIZE,number of data at current transfer" line.long 0x4 "SPI_CFG1,SPI configuration register 1" sif (cpuis("STM32MP13*")) bitfld.long 0x4 28.--30. "MBR,master baud rate" "0: SPI master clock/2,1: SPI master clock/4,2: SPI master clock/8,3: SPI master clock/16,4: SPI master clock/32,5: SPI master clock/64,6: SPI master clock/128,7: SPI master clock/256" bitfld.long 0x4 22. "CRCEN,hardware CRC computation enable" "0: CRC calculation disabled,1: CRC calculation Enabled" newline hexmask.long.byte 0x4 16.--20. 1. "CRCSIZE,length of CRC frame to be transacted and compared" bitfld.long 0x4 15. "TXDMAEN,Tx DMA stream enable" "0: Tx DMA disabled,1: Tx DMA enabled" newline bitfld.long 0x4 14. "RXDMAEN,Rx DMA stream enable" "0: Rx-DMA disabled,1: Rx-DMA enabled" bitfld.long 0x4 11.--12. "UDRDET,detection of underrun condition at slave transmitter" "0: underrun is detected at begin of data frame (no..,1: underrun is detected at end of last data frame,2: underrun is detected by begin of active SS signal,?" newline bitfld.long 0x4 9.--10. "UDRCFG,behavior of slave transmitter at underrun condition" "0: slave sends a constant pattern defined by the..,1: slave repeats lastly received data frame from..,2: slave repeats its lastly transmitted data frame,?" hexmask.long.byte 0x4 5.--8. 1. "FTHLV,FIFO threshold level" newline hexmask.long.byte 0x4 0.--4. 1. "DSIZE,number of bits in at single SPI data frame" endif sif (cpuis("STM32MP151*")) bitfld.long 0x4 28.--30. "MBR,MBR" "0,1,2,3,4,5,6,7" newline endif sif (cpuis("STM32MP151*")) bitfld.long 0x4 22. "CRCEN,CRCEN" "0,1" endif sif (cpuis("STM32MP151*")) hexmask.long.byte 0x4 16.--20. 1. "CRCSIZE,CRCSIZE" newline bitfld.long 0x4 15. "TXDMAEN,TXDMAEN" "0,1" bitfld.long 0x4 14. "RXDMAEN,RXDMAEN" "0,1" newline endif sif (cpuis("STM32MP151*")) bitfld.long 0x4 11.--12. "UDRDET,UDRDET" "0,1,2,3" bitfld.long 0x4 9.--10. "UDRCFG,UDRCFG" "0,1,2,3" newline hexmask.long.byte 0x4 5.--8. 1. "FTHLV,FTHLV" endif line.long 0x8 "SPI_CFG2,SPI configuration register 2" sif (cpuis("STM32MP13*")) bitfld.long 0x8 31. "AFCNTR,alternate function GPIOs control" "0: the peripheral takes no control of GPIOs while..,1: the peripheral keeps always control of all.." bitfld.long 0x8 30. "SSOM,SS output management in master mode" "0: SS is kept at active level till data transfer is..,1: SPI data frames are interleaved with SS non.." newline bitfld.long 0x8 29. "SSOE,SS output enable" "0: SS output is disabled and the SPI can work in..,1: SS output is enabled. The SPI cannot work in a.." bitfld.long 0x8 28. "SSIOP,SS input/output polarity" "0: low level is active for SS signal,1: high level is active for SS signal" newline bitfld.long 0x8 26. "SSM,software management of SS signal input" "0: SS input value is determined by the SS PAD,1: SS input value is determined by the SSI bit" bitfld.long 0x8 25. "CPOL,clock polarity" "0: SCK signal is at 0 when idle,1: SCK signal is at 1 when idle" newline bitfld.long 0x8 24. "CPHA,clock phase" "0: the first clock transition is the first data..,1: the second clock transition is the first data.." bitfld.long 0x8 23. "LSBFRST,data frame format" "0: MSB transmitted first,1: LSB transmitted first" newline bitfld.long 0x8 22. "MASTER,SPI master" "0: SPI Slave,1: SPI Master" bitfld.long 0x8 19.--21. "SP,Serial protocol" "0: SPI Motorola,1: SPI TI,?,?,?,?,?,?" newline bitfld.long 0x8 17.--18. "COMM,SPI communication mode" "0: full-duplex,1: simplex transmitter,2: simplex receiver,3: half-duplex" bitfld.long 0x8 15. "IOSWP,swap functionality of MISO and MOSI pins" "0: no swap,1: MOSI and MISO are swapped" newline hexmask.long.byte 0x8 4.--7. 1. "MIDI,master Inter-Data Idleness" hexmask.long.byte 0x8 0.--3. 1. "MSSI,master SS idleness" newline endif sif (cpuis("STM32MP151*")) bitfld.long 0x8 31. "AFCNTR,AFCNTR" "0,1" bitfld.long 0x8 30. "SSOM,SSOM" "0,1" newline bitfld.long 0x8 29. "SSOE,SSOE" "0,1" bitfld.long 0x8 28. "SSIOP,SSIOP" "0,1" newline endif sif (cpuis("STM32MP151*")) bitfld.long 0x8 26. "SSM,SSM" "0,1" bitfld.long 0x8 25. "CPOL,CPOL" "0,1" newline bitfld.long 0x8 24. "CPHA,CPHA" "0,1" bitfld.long 0x8 23. "LSBFRST,LSBFRST" "0,1" newline bitfld.long 0x8 22. "MASTER,MASTER" "0,1" bitfld.long 0x8 19.--21. "SP,SP" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 17.--18. "COMM,COMM" "0,1,2,3" endif sif (cpuis("STM32MP151*")) bitfld.long 0x8 15. "IOSWP,IOSWP" "0,1" newline endif sif (cpuis("STM32MP151*")) hexmask.long.byte 0x8 4.--7. 1. "MIDI,MIDI" endif group.long 0x40++0x13 line.long 0x0 "SPI_CRCPOLY,SPI polynomial register" hexmask.long 0x0 0.--31. 1. "CRCPOLY,CRC polynomial register" line.long 0x4 "SPI_TXCRC,SPI transmitter CRC register" sif (cpuis("STM32MP13*")) hexmask.long 0x4 0.--31. 1. "TXCRC,CRC register for transmitter" endif sif (cpuis("STM32MP151*")) hexmask.long 0x4 0.--31. 1. "TXCRC,TXCRC" endif line.long 0x8 "SPI_RXCRC,SPI receiver CRC register" sif (cpuis("STM32MP13*")) hexmask.long 0x8 0.--31. 1. "RXCRC,CRC register for receiver" endif sif (cpuis("STM32MP151*")) hexmask.long 0x8 0.--31. 1. "RXCRC,RXCRC" endif line.long 0xC "SPI_UDRDR,SPI underrun data register" hexmask.long 0xC 0.--31. 1. "UDRDR,data at slave underrun condition" line.long 0x10 "SPI_I2SCFGR,SPI/I2S configuration register" sif (cpuis("STM32MP13*")) bitfld.long 0x10 25. "MCKOE,master clock output enable" "0: Master clock output is disabled,1: Master clock output is enabled" bitfld.long 0x10 24. "ODD,odd factor for the prescaler" "0: Real divider value is = I2SDIV *2,1: Real divider value is = (I2SDIV * 2) + 1" newline bitfld.long 0x10 14. "DATFMT,data format" "0: the data inside the SPI_RXDR or SPI_TXDR are..,1: the data inside the SPI_RXDR or SPI_TXDR are.." bitfld.long 0x10 13. "WSINV,Word select inversion" "0: in I2S Philips standard Left channel is..,1: in I2S Philips standard Left channel is.." newline bitfld.long 0x10 12. "FIXCH,fixed channel length in slave" "0: the channel length in slave mode is different..,1: the channel length in slave mode is supposed to.." bitfld.long 0x10 11. "CKPOL,serial audio clock polarity" "0: the signals generated by the SPI/I2S (i.e. SDO..,1: the signals generated by the SPI/I2S (i.e. SDO.." newline bitfld.long 0x10 10. "CHLEN,channel length (number of bits per audio channel)" "0: 16-bit wide,1: 32-bit wide" bitfld.long 0x10 8.--9. "DATLEN,data length to be transferred" "0: 16-bit data length,1: 24-bit data length,2: 32-bit data length,3: not allowed" newline bitfld.long 0x10 7. "PCMSYNC,PCM frame synchronization" "0: short frame synchronization,1: long frame synchronization" bitfld.long 0x10 4.--5. "I2SSTD,I2S standard selection" "0: I2S Philips standard.,1: MSB justified standard (left justified),2: LSB justified standard (right justified),3: PCM standard" newline bitfld.long 0x10 1.--3. "I2SCFG,I2S configuration mode" "0: slave - transmit,1: slave - receive,2: master - transmit,3: master - receive,4: slave - full duplex,5: master - full duplex,?,?" bitfld.long 0x10 0. "I2SMOD,I2S mode selection" "0: SPI mode is selected,1: I2S/PCM mode is selected" newline endif sif (cpuis("STM32MP151*")) bitfld.long 0x10 25. "MCKOE,MCKOE" "0,1" bitfld.long 0x10 24. "ODD,ODD" "0,1" newline endif hexmask.long.byte 0x10 16.--23. 1. "I2SDIV,I2S linear prescaler" sif (cpuis("STM32MP151*")) bitfld.long 0x10 14. "DATFMT,DATFMT" "0,1" newline bitfld.long 0x10 13. "WSINV,WSINV" "0,1" bitfld.long 0x10 12. "FIXCH,FIXCH" "0,1" newline bitfld.long 0x10 11. "CKPOL,CKPOL" "0,1" bitfld.long 0x10 10. "CHLEN,CHLEN" "0,1" newline bitfld.long 0x10 8.--9. "DATLEN,DATLEN" "0,1,2,3" bitfld.long 0x10 7. "PCMSYNC,PCMSYNC" "0,1" newline endif sif (cpuis("STM32MP151*")) bitfld.long 0x10 4.--5. "I2SSTD,I2SSTD" "0,1,2,3" bitfld.long 0x10 1.--3. "I2SCFG,I2SCFG" "0,1,2,3,4,5,6,7" endif group.long 0x3F0++0x3 line.long 0x0 "SPI_I2S_HWCFGR,SPI/I2S hardware configuration register" sif (cpuis("STM32MP13*")) hexmask.long.byte 0x0 16.--19. 1. "DSCFG,SPI data size configuration" hexmask.long.byte 0x0 12.--15. 1. "I2SCFG,I2S configuration" newline hexmask.long.byte 0x0 8.--11. 1. "CRCCFG,CRC configuration for SPI" hexmask.long.byte 0x0 4.--7. 1. "RXFCFG,RxFIFO size" newline hexmask.long.byte 0x0 0.--3. 1. "TXFCFG,TxFIFO size" endif sif (cpuis("STM32MP151*")) hexmask.long.byte 0x0 16.--19. 1. "DSCFG,DSCFG" newline hexmask.long.byte 0x0 12.--15. 1. "I2SCFG,I2SCFG" hexmask.long.byte 0x0 8.--11. 1. "CRCCFG,CRCCFG" newline hexmask.long.byte 0x0 4.--7. 1. "RXFCFG,RXFCFG" hexmask.long.byte 0x0 0.--3. 1. "TXFCFG,TXFCFG" endif rgroup.long 0x3F4++0x3 line.long 0x0 "SPI_VERR,SPI/I2S version register" sif (cpuis("STM32MP13*")) hexmask.long.byte 0x0 4.--7. 1. "MAJREV,major revision of the IP." hexmask.long.byte 0x0 0.--3. 1. "MINREV,minor revision of the IP." newline endif sif (cpuis("STM32MP151*")) hexmask.long.byte 0x0 4.--7. 1. "MAJREV,MAJREV" hexmask.long.byte 0x0 0.--3. 1. "MINREV,MINREV" endif group.long 0x3F8++0x7 line.long 0x0 "SPI_IPIDR,SPI/I2S identification register" sif (cpuis("STM32MP13*")) hexmask.long 0x0 0.--31. 1. "ID,IP identification" endif sif (cpuis("STM32MP151*")) hexmask.long 0x0 0.--31. 1. "ID,ID" endif line.long 0x4 "SPI_SIDR,SPI/I2S size identification register" sif (cpuis("STM32MP13*")) hexmask.long 0x4 0.--31. 1. "SID,size identification" endif sif (cpuis("STM32MP151*")) hexmask.long 0x4 0.--31. 1. "SID,SID" endif sif (cpuis("STM32MP151*")) rgroup.long 0x44++0x3 line.long 0x0 "SPI_TXCRC,SPI transmitter CRC register" endif sif (cpuis("STM32MP151*")) rgroup.long 0x48++0x3 line.long 0x0 "SPI_RXCRC,SPI receiver CRC register" endif sif (cpuis("STM32MP151*")) rgroup.long 0x3F0++0x3 line.long 0x0 "SPI_I2S_HWCFGR,SPI/I2S hardware configuration register" endif sif (cpuis("STM32MP151*")) rgroup.long 0x3F4++0x3 line.long 0x0 "SPI_VERR,SPI/I2S version register" endif sif (cpuis("STM32MP151*")) rgroup.long 0x3F8++0x3 line.long 0x0 "SPI_IPIDR,SPI/I2S identification register" endif sif (cpuis("STM32MP151*")) rgroup.long 0x3FC++0x3 line.long 0x0 "SPI_SIDR,SPI/I2S size identification register" endif tree.end endif sif (cpuis("STM32MP151*")) tree "SPI6" base ad:0x5C001000 group.long 0x0++0x3 line.long 0x0 "SPI2S_CR1,SPI/I2S control register 1" bitfld.long 0x0 16. "IOLOCK,IOLOCK" "0,1" bitfld.long 0x0 15. "TCRCINI,TCRCINI" "0,1" bitfld.long 0x0 14. "RCRCINI,RCRCINI" "0,1" bitfld.long 0x0 13. "CRC33_17,CRC33_17" "0,1" bitfld.long 0x0 12. "SSI,SSI" "0,1" bitfld.long 0x0 11. "HDDIR,HDDIR" "0,1" bitfld.long 0x0 10. "CSUSP,CSUSP" "0,1" bitfld.long 0x0 9. "CSTART,CSTART" "0,1" newline bitfld.long 0x0 8. "MASRX,MASRX" "0,1" bitfld.long 0x0 0. "SPE,SPE" "0,1" group.long 0x10++0x3 line.long 0x0 "SPI2S_IER,SPI/I2S interrupt enable register" bitfld.long 0x0 10. "TSERFIE,TSERFIE" "0,1" bitfld.long 0x0 9. "MODFIE,MODFIE" "0,1" bitfld.long 0x0 8. "TIFREIE,TIFREIE" "0,1" bitfld.long 0x0 7. "CRCEIE,CRCEIE" "0,1" bitfld.long 0x0 6. "OVRIE,OVRIE" "0,1" bitfld.long 0x0 5. "UDRIE,UDRIE" "0,1" bitfld.long 0x0 4. "TXTFIE,TXTFIE" "0,1" bitfld.long 0x0 3. "EOTIE,EOTIE" "0,1" newline bitfld.long 0x0 2. "DXPIE,DXPIE" "0,1" bitfld.long 0x0 1. "TXPIE,TXPIE" "0,1" bitfld.long 0x0 0. "RXPIE,RXPIE" "0,1" rgroup.long 0x14++0x3 line.long 0x0 "SPI2S_SR,SPI/I2S status register" hexmask.long.word 0x0 16.--31. 1. "CTSIZE,CTSIZE" bitfld.long 0x0 15. "RXWNE,RXWNE" "0,1" bitfld.long 0x0 13.--14. "RXPLVL,RXPLVL" "0,1,2,3" bitfld.long 0x0 12. "TXC,TXC" "0,1" bitfld.long 0x0 11. "SUSP,SUSP" "0,1" bitfld.long 0x0 10. "TSERF,TSERF" "0,1" bitfld.long 0x0 9. "MODF,MODF" "0,1" bitfld.long 0x0 8. "TIFRE,TIFRE" "0,1" newline bitfld.long 0x0 7. "CRCE,CRCE" "0,1" bitfld.long 0x0 6. "OVR,OVR" "0,1" bitfld.long 0x0 5. "UDR,UDR" "0,1" bitfld.long 0x0 4. "TXTF,TXTF" "0,1" bitfld.long 0x0 3. "EOT,EOT" "0,1" bitfld.long 0x0 2. "DXP,DXP" "0,1" bitfld.long 0x0 1. "TXP,TXP" "0,1" bitfld.long 0x0 0. "RXP,RXP" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "SPI2S_IFCR,SPI/I2S interrupt/status flags clear register" bitfld.long 0x0 11. "SUSPC,SUSPC" "0,1" bitfld.long 0x0 10. "TSERFC,TSERFC" "0,1" bitfld.long 0x0 9. "MODFC,MODFC" "0,1" bitfld.long 0x0 8. "TIFREC,TIFREC" "0,1" bitfld.long 0x0 7. "CRCEC,CRCEC" "0,1" bitfld.long 0x0 6. "OVRC,OVRC" "0,1" bitfld.long 0x0 5. "UDRC,UDRC" "0,1" bitfld.long 0x0 4. "TXTFC,TXTFC" "0,1" newline bitfld.long 0x0 3. "EOTC,EOTC" "0,1" wgroup.long 0x20++0x3 line.long 0x0 "SPI2S_TXDR,SPI/I2S transmit data register" hexmask.long 0x0 0.--31. 1. "TXDR,TXDR" rgroup.long 0x30++0x3 line.long 0x0 "SPI2S_RXDR,SPI/I2S receive data register" hexmask.long 0x0 0.--31. 1. "RXDR,RXDR" group.long 0x4++0xB line.long 0x0 "SPI_CR2,SPI control register 2" hexmask.long.word 0x0 16.--31. 1. "TSER,TSER" hexmask.long.word 0x0 0.--15. 1. "TSIZE,TSIZE" line.long 0x4 "SPI_CFG1,Content of this register is write protected when SPI is enabled" bitfld.long 0x4 28.--30. "MBR,MBR" "0,1,2,3,4,5,6,7" bitfld.long 0x4 22. "CRCEN,CRCEN" "0,1" hexmask.long.byte 0x4 16.--20. 1. "CRCSIZE,CRCSIZE" bitfld.long 0x4 15. "TXDMAEN,TXDMAEN" "0,1" bitfld.long 0x4 14. "RXDMAEN,RXDMAEN" "0,1" bitfld.long 0x4 11.--12. "UDRDET,UDRDET" "0,1,2,3" bitfld.long 0x4 9.--10. "UDRCFG,UDRCFG" "0,1,2,3" hexmask.long.byte 0x4 5.--8. 1. "FTHLV,FTHLV" newline hexmask.long.byte 0x4 0.--4. 1. "DSIZE,DSIZE" line.long 0x8 "SPI_CFG2,The content of this register is write protected when SPI is enabled or IOLOCK bit is set at SPI2S_CR1 register." bitfld.long 0x8 31. "AFCNTR,AFCNTR" "0,1" bitfld.long 0x8 30. "SSOM,SSOM" "0,1" bitfld.long 0x8 29. "SSOE,SSOE" "0,1" bitfld.long 0x8 28. "SSIOP,SSIOP" "0,1" bitfld.long 0x8 26. "SSM,SSM" "0,1" bitfld.long 0x8 25. "CPOL,CPOL" "0,1" bitfld.long 0x8 24. "CPHA,CPHA" "0,1" bitfld.long 0x8 23. "LSBFRST,LSBFRST" "0,1" newline bitfld.long 0x8 22. "MASTER,MASTER" "0,1" bitfld.long 0x8 19.--21. "SP,SP" "0,1,2,3,4,5,6,7" bitfld.long 0x8 17.--18. "COMM,COMM" "0,1,2,3" bitfld.long 0x8 15. "IOSWP,IOSWP" "0,1" hexmask.long.byte 0x8 4.--7. 1. "MIDI,MIDI" hexmask.long.byte 0x8 0.--3. 1. "MSSI,MSSI" group.long 0x40++0x3 line.long 0x0 "SPI_CRCPOLY,SPI polynomial register" hexmask.long 0x0 0.--31. 1. "CRCPOLY,CRCPOLY" rgroup.long 0x44++0x7 line.long 0x0 "SPI_TXCRC,SPI transmitter CRC register" hexmask.long 0x0 0.--31. 1. "TXCRC,TXCRC" line.long 0x4 "SPI_RXCRC,SPI receiver CRC register" hexmask.long 0x4 0.--31. 1. "RXCRC,RXCRC" group.long 0x4C++0x7 line.long 0x0 "SPI_UDRDR,SPI underrun data register" hexmask.long 0x0 0.--31. 1. "UDRDR,UDRDR" line.long 0x4 "SPI_I2SCFGR,All documented bits in this register must be configured when the I2S is disabled (SPE = 0).These bits are not used in SPI mode except for I2SMOD which needs to be set to 0 in SPI mode." bitfld.long 0x4 25. "MCKOE,MCKOE" "0,1" bitfld.long 0x4 24. "ODD,ODD" "0,1" hexmask.long.byte 0x4 16.--23. 1. "I2SDIV,I2SDIV" bitfld.long 0x4 14. "DATFMT,DATFMT" "0,1" bitfld.long 0x4 13. "WSINV,WSINV" "0,1" bitfld.long 0x4 12. "FIXCH,FIXCH" "0,1" bitfld.long 0x4 11. "CKPOL,CKPOL" "0,1" bitfld.long 0x4 10. "CHLEN,CHLEN" "0,1" newline bitfld.long 0x4 8.--9. "DATLEN,DATLEN" "0,1,2,3" bitfld.long 0x4 7. "PCMSYNC,PCMSYNC" "0,1" bitfld.long 0x4 4.--5. "I2SSTD,I2SSTD" "0,1,2,3" bitfld.long 0x4 1.--3. "I2SCFG,I2SCFG" "0,1,2,3,4,5,6,7" bitfld.long 0x4 0. "I2SMOD,I2SMOD" "0,1" rgroup.long 0x3F0++0xF line.long 0x0 "SPI_I2S_HWCFGR,SPI/I2S hardware configuration register" hexmask.long.byte 0x0 16.--19. 1. "DSCFG,DSCFG" hexmask.long.byte 0x0 12.--15. 1. "I2SCFG,I2SCFG" hexmask.long.byte 0x0 8.--11. 1. "CRCCFG,CRCCFG" hexmask.long.byte 0x0 4.--7. 1. "RXFCFG,RXFCFG" hexmask.long.byte 0x0 0.--3. 1. "TXFCFG,TXFCFG" line.long 0x4 "SPI_VERR,SPI/I2S version register" hexmask.long.byte 0x4 4.--7. 1. "MAJREV,MAJREV" hexmask.long.byte 0x4 0.--3. 1. "MINREV,MINREV" line.long 0x8 "SPI_IPIDR,SPI/I2S identification register" hexmask.long 0x8 0.--31. 1. "ID,ID" line.long 0xC "SPI_SIDR,SPI/I2S size identification register" hexmask.long 0xC 0.--31. 1. "SID,SID" tree.end endif sif (cpuis("STM32MP153*")) tree "SPI1" base ad:0x44004000 group.long 0x0++0x3 line.long 0x0 "SPI2S_CR1,SPI/I2S control register 1" bitfld.long 0x0 16. "IOLOCK,IOLOCK" "0,1" bitfld.long 0x0 15. "TCRCINI,TCRCINI" "0,1" bitfld.long 0x0 14. "RCRCINI,RCRCINI" "0,1" bitfld.long 0x0 13. "CRC33_17,CRC33_17" "0,1" bitfld.long 0x0 12. "SSI,SSI" "0,1" bitfld.long 0x0 11. "HDDIR,HDDIR" "0,1" bitfld.long 0x0 10. "CSUSP,CSUSP" "0,1" bitfld.long 0x0 9. "CSTART,CSTART" "0,1" newline bitfld.long 0x0 8. "MASRX,MASRX" "0,1" bitfld.long 0x0 0. "SPE,SPE" "0,1" group.long 0x10++0x3 line.long 0x0 "SPI2S_IER,SPI/I2S interrupt enable register" bitfld.long 0x0 10. "TSERFIE,TSERFIE" "0,1" bitfld.long 0x0 9. "MODFIE,MODFIE" "0,1" bitfld.long 0x0 8. "TIFREIE,TIFREIE" "0,1" bitfld.long 0x0 7. "CRCEIE,CRCEIE" "0,1" bitfld.long 0x0 6. "OVRIE,OVRIE" "0,1" bitfld.long 0x0 5. "UDRIE,UDRIE" "0,1" bitfld.long 0x0 4. "TXTFIE,TXTFIE" "0,1" bitfld.long 0x0 3. "EOTIE,EOTIE" "0,1" newline bitfld.long 0x0 2. "DXPIE,DXPIE" "0,1" bitfld.long 0x0 1. "TXPIE,TXPIE" "0,1" bitfld.long 0x0 0. "RXPIE,RXPIE" "0,1" rgroup.long 0x14++0x3 line.long 0x0 "SPI2S_SR,SPI/I2S status register" hexmask.long.word 0x0 16.--31. 1. "CTSIZE,CTSIZE" bitfld.long 0x0 15. "RXWNE,RXWNE" "0,1" bitfld.long 0x0 13.--14. "RXPLVL,RXPLVL" "0,1,2,3" bitfld.long 0x0 12. "TXC,TXC" "0,1" bitfld.long 0x0 11. "SUSP,SUSP" "0,1" bitfld.long 0x0 10. "TSERF,TSERF" "0,1" bitfld.long 0x0 9. "MODF,MODF" "0,1" bitfld.long 0x0 8. "TIFRE,TIFRE" "0,1" newline bitfld.long 0x0 7. "CRCE,CRCE" "0,1" bitfld.long 0x0 6. "OVR,OVR" "0,1" bitfld.long 0x0 5. "UDR,UDR" "0,1" bitfld.long 0x0 4. "TXTF,TXTF" "0,1" bitfld.long 0x0 3. "EOT,EOT" "0,1" bitfld.long 0x0 2. "DXP,DXP" "0,1" bitfld.long 0x0 1. "TXP,TXP" "0,1" bitfld.long 0x0 0. "RXP,RXP" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "SPI2S_IFCR,SPI/I2S interrupt/status flags clear register" bitfld.long 0x0 11. "SUSPC,SUSPC" "0,1" bitfld.long 0x0 10. "TSERFC,TSERFC" "0,1" bitfld.long 0x0 9. "MODFC,MODFC" "0,1" bitfld.long 0x0 8. "TIFREC,TIFREC" "0,1" bitfld.long 0x0 7. "CRCEC,CRCEC" "0,1" bitfld.long 0x0 6. "OVRC,OVRC" "0,1" bitfld.long 0x0 5. "UDRC,UDRC" "0,1" bitfld.long 0x0 4. "TXTFC,TXTFC" "0,1" newline bitfld.long 0x0 3. "EOTC,EOTC" "0,1" wgroup.long 0x20++0x3 line.long 0x0 "SPI2S_TXDR,SPI/I2S transmit data register" hexmask.long 0x0 0.--31. 1. "TXDR,TXDR" rgroup.long 0x30++0x3 line.long 0x0 "SPI2S_RXDR,SPI/I2S receive data register" hexmask.long 0x0 0.--31. 1. "RXDR,RXDR" group.long 0x4++0xB line.long 0x0 "SPI_CR2,SPI control register 2" hexmask.long.word 0x0 16.--31. 1. "TSER,TSER" hexmask.long.word 0x0 0.--15. 1. "TSIZE,TSIZE" line.long 0x4 "SPI_CFG1,Content of this register is write protected when SPI is enabled" bitfld.long 0x4 28.--30. "MBR,MBR" "0,1,2,3,4,5,6,7" bitfld.long 0x4 22. "CRCEN,CRCEN" "0,1" hexmask.long.byte 0x4 16.--20. 1. "CRCSIZE,CRCSIZE" bitfld.long 0x4 15. "TXDMAEN,TXDMAEN" "0,1" bitfld.long 0x4 14. "RXDMAEN,RXDMAEN" "0,1" bitfld.long 0x4 11.--12. "UDRDET,UDRDET" "0,1,2,3" bitfld.long 0x4 9.--10. "UDRCFG,UDRCFG" "0,1,2,3" hexmask.long.byte 0x4 5.--8. 1. "FTHLV,FTHLV" newline hexmask.long.byte 0x4 0.--4. 1. "DSIZE,DSIZE" line.long 0x8 "SPI_CFG2,The content of this register is write protected when SPI is enabled or IOLOCK bit is set at SPI2S_CR1 register." bitfld.long 0x8 31. "AFCNTR,AFCNTR" "0,1" bitfld.long 0x8 30. "SSOM,SSOM" "0,1" bitfld.long 0x8 29. "SSOE,SSOE" "0,1" bitfld.long 0x8 28. "SSIOP,SSIOP" "0,1" bitfld.long 0x8 26. "SSM,SSM" "0,1" bitfld.long 0x8 25. "CPOL,CPOL" "0,1" bitfld.long 0x8 24. "CPHA,CPHA" "0,1" bitfld.long 0x8 23. "LSBFRST,LSBFRST" "0,1" newline bitfld.long 0x8 22. "MASTER,MASTER" "0,1" bitfld.long 0x8 19.--21. "SP,SP" "0,1,2,3,4,5,6,7" bitfld.long 0x8 17.--18. "COMM,COMM" "0,1,2,3" bitfld.long 0x8 15. "IOSWP,IOSWP" "0,1" hexmask.long.byte 0x8 4.--7. 1. "MIDI,MIDI" hexmask.long.byte 0x8 0.--3. 1. "MSSI,MSSI" group.long 0x40++0x3 line.long 0x0 "SPI_CRCPOLY,SPI polynomial register" hexmask.long 0x0 0.--31. 1. "CRCPOLY,CRCPOLY" rgroup.long 0x44++0x7 line.long 0x0 "SPI_TXCRC,SPI transmitter CRC register" hexmask.long 0x0 0.--31. 1. "TXCRC,TXCRC" line.long 0x4 "SPI_RXCRC,SPI receiver CRC register" hexmask.long 0x4 0.--31. 1. "RXCRC,RXCRC" group.long 0x4C++0x7 line.long 0x0 "SPI_UDRDR,SPI underrun data register" hexmask.long 0x0 0.--31. 1. "UDRDR,UDRDR" line.long 0x4 "SPI_I2SCFGR,All documented bits in this register must be configured when the I2S is disabled (SPE = 0).These bits are not used in SPI mode except for I2SMOD which needs to be set to 0 in SPI mode." bitfld.long 0x4 25. "MCKOE,MCKOE" "0,1" bitfld.long 0x4 24. "ODD,ODD" "0,1" hexmask.long.byte 0x4 16.--23. 1. "I2SDIV,I2SDIV" bitfld.long 0x4 14. "DATFMT,DATFMT" "0,1" bitfld.long 0x4 13. "WSINV,WSINV" "0,1" bitfld.long 0x4 12. "FIXCH,FIXCH" "0,1" bitfld.long 0x4 11. "CKPOL,CKPOL" "0,1" bitfld.long 0x4 10. "CHLEN,CHLEN" "0,1" newline bitfld.long 0x4 8.--9. "DATLEN,DATLEN" "0,1,2,3" bitfld.long 0x4 7. "PCMSYNC,PCMSYNC" "0,1" bitfld.long 0x4 4.--5. "I2SSTD,I2SSTD" "0,1,2,3" bitfld.long 0x4 1.--3. "I2SCFG,I2SCFG" "0,1,2,3,4,5,6,7" bitfld.long 0x4 0. "I2SMOD,I2SMOD" "0,1" rgroup.long 0x3F0++0xF line.long 0x0 "SPI_I2S_HWCFGR,SPI/I2S hardware configuration register" hexmask.long.byte 0x0 16.--19. 1. "DSCFG,DSCFG" hexmask.long.byte 0x0 12.--15. 1. "I2SCFG,I2SCFG" hexmask.long.byte 0x0 8.--11. 1. "CRCCFG,CRCCFG" hexmask.long.byte 0x0 4.--7. 1. "RXFCFG,RXFCFG" hexmask.long.byte 0x0 0.--3. 1. "TXFCFG,TXFCFG" line.long 0x4 "SPI_VERR,SPI/I2S version register" hexmask.long.byte 0x4 4.--7. 1. "MAJREV,MAJREV" hexmask.long.byte 0x4 0.--3. 1. "MINREV,MINREV" line.long 0x8 "SPI_IPIDR,SPI/I2S identification register" hexmask.long 0x8 0.--31. 1. "ID,ID" line.long 0xC "SPI_SIDR,SPI/I2S size identification register" hexmask.long 0xC 0.--31. 1. "SID,SID" tree.end endif sif (cpuis("STM32MP153*")) tree "SPI2" base ad:0x4000B000 group.long 0x0++0x3 line.long 0x0 "SPI2S_CR1,SPI/I2S control register 1" bitfld.long 0x0 16. "IOLOCK,IOLOCK" "0,1" bitfld.long 0x0 15. "TCRCINI,TCRCINI" "0,1" bitfld.long 0x0 14. "RCRCINI,RCRCINI" "0,1" bitfld.long 0x0 13. "CRC33_17,CRC33_17" "0,1" bitfld.long 0x0 12. "SSI,SSI" "0,1" bitfld.long 0x0 11. "HDDIR,HDDIR" "0,1" bitfld.long 0x0 10. "CSUSP,CSUSP" "0,1" bitfld.long 0x0 9. "CSTART,CSTART" "0,1" newline bitfld.long 0x0 8. "MASRX,MASRX" "0,1" bitfld.long 0x0 0. "SPE,SPE" "0,1" group.long 0x10++0x3 line.long 0x0 "SPI2S_IER,SPI/I2S interrupt enable register" bitfld.long 0x0 10. "TSERFIE,TSERFIE" "0,1" bitfld.long 0x0 9. "MODFIE,MODFIE" "0,1" bitfld.long 0x0 8. "TIFREIE,TIFREIE" "0,1" bitfld.long 0x0 7. "CRCEIE,CRCEIE" "0,1" bitfld.long 0x0 6. "OVRIE,OVRIE" "0,1" bitfld.long 0x0 5. "UDRIE,UDRIE" "0,1" bitfld.long 0x0 4. "TXTFIE,TXTFIE" "0,1" bitfld.long 0x0 3. "EOTIE,EOTIE" "0,1" newline bitfld.long 0x0 2. "DXPIE,DXPIE" "0,1" bitfld.long 0x0 1. "TXPIE,TXPIE" "0,1" bitfld.long 0x0 0. "RXPIE,RXPIE" "0,1" rgroup.long 0x14++0x3 line.long 0x0 "SPI2S_SR,SPI/I2S status register" hexmask.long.word 0x0 16.--31. 1. "CTSIZE,CTSIZE" bitfld.long 0x0 15. "RXWNE,RXWNE" "0,1" bitfld.long 0x0 13.--14. "RXPLVL,RXPLVL" "0,1,2,3" bitfld.long 0x0 12. "TXC,TXC" "0,1" bitfld.long 0x0 11. "SUSP,SUSP" "0,1" bitfld.long 0x0 10. "TSERF,TSERF" "0,1" bitfld.long 0x0 9. "MODF,MODF" "0,1" bitfld.long 0x0 8. "TIFRE,TIFRE" "0,1" newline bitfld.long 0x0 7. "CRCE,CRCE" "0,1" bitfld.long 0x0 6. "OVR,OVR" "0,1" bitfld.long 0x0 5. "UDR,UDR" "0,1" bitfld.long 0x0 4. "TXTF,TXTF" "0,1" bitfld.long 0x0 3. "EOT,EOT" "0,1" bitfld.long 0x0 2. "DXP,DXP" "0,1" bitfld.long 0x0 1. "TXP,TXP" "0,1" bitfld.long 0x0 0. "RXP,RXP" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "SPI2S_IFCR,SPI/I2S interrupt/status flags clear register" bitfld.long 0x0 11. "SUSPC,SUSPC" "0,1" bitfld.long 0x0 10. "TSERFC,TSERFC" "0,1" bitfld.long 0x0 9. "MODFC,MODFC" "0,1" bitfld.long 0x0 8. "TIFREC,TIFREC" "0,1" bitfld.long 0x0 7. "CRCEC,CRCEC" "0,1" bitfld.long 0x0 6. "OVRC,OVRC" "0,1" bitfld.long 0x0 5. "UDRC,UDRC" "0,1" bitfld.long 0x0 4. "TXTFC,TXTFC" "0,1" newline bitfld.long 0x0 3. "EOTC,EOTC" "0,1" wgroup.long 0x20++0x3 line.long 0x0 "SPI2S_TXDR,SPI/I2S transmit data register" hexmask.long 0x0 0.--31. 1. "TXDR,TXDR" rgroup.long 0x30++0x3 line.long 0x0 "SPI2S_RXDR,SPI/I2S receive data register" hexmask.long 0x0 0.--31. 1. "RXDR,RXDR" group.long 0x4++0xB line.long 0x0 "SPI_CR2,SPI control register 2" hexmask.long.word 0x0 16.--31. 1. "TSER,TSER" hexmask.long.word 0x0 0.--15. 1. "TSIZE,TSIZE" line.long 0x4 "SPI_CFG1,Content of this register is write protected when SPI is enabled" bitfld.long 0x4 28.--30. "MBR,MBR" "0,1,2,3,4,5,6,7" bitfld.long 0x4 22. "CRCEN,CRCEN" "0,1" hexmask.long.byte 0x4 16.--20. 1. "CRCSIZE,CRCSIZE" bitfld.long 0x4 15. "TXDMAEN,TXDMAEN" "0,1" bitfld.long 0x4 14. "RXDMAEN,RXDMAEN" "0,1" bitfld.long 0x4 11.--12. "UDRDET,UDRDET" "0,1,2,3" bitfld.long 0x4 9.--10. "UDRCFG,UDRCFG" "0,1,2,3" hexmask.long.byte 0x4 5.--8. 1. "FTHLV,FTHLV" newline hexmask.long.byte 0x4 0.--4. 1. "DSIZE,DSIZE" line.long 0x8 "SPI_CFG2,The content of this register is write protected when SPI is enabled or IOLOCK bit is set at SPI2S_CR1 register." bitfld.long 0x8 31. "AFCNTR,AFCNTR" "0,1" bitfld.long 0x8 30. "SSOM,SSOM" "0,1" bitfld.long 0x8 29. "SSOE,SSOE" "0,1" bitfld.long 0x8 28. "SSIOP,SSIOP" "0,1" bitfld.long 0x8 26. "SSM,SSM" "0,1" bitfld.long 0x8 25. "CPOL,CPOL" "0,1" bitfld.long 0x8 24. "CPHA,CPHA" "0,1" bitfld.long 0x8 23. "LSBFRST,LSBFRST" "0,1" newline bitfld.long 0x8 22. "MASTER,MASTER" "0,1" bitfld.long 0x8 19.--21. "SP,SP" "0,1,2,3,4,5,6,7" bitfld.long 0x8 17.--18. "COMM,COMM" "0,1,2,3" bitfld.long 0x8 15. "IOSWP,IOSWP" "0,1" hexmask.long.byte 0x8 4.--7. 1. "MIDI,MIDI" hexmask.long.byte 0x8 0.--3. 1. "MSSI,MSSI" group.long 0x40++0x3 line.long 0x0 "SPI_CRCPOLY,SPI polynomial register" hexmask.long 0x0 0.--31. 1. "CRCPOLY,CRCPOLY" rgroup.long 0x44++0x7 line.long 0x0 "SPI_TXCRC,SPI transmitter CRC register" hexmask.long 0x0 0.--31. 1. "TXCRC,TXCRC" line.long 0x4 "SPI_RXCRC,SPI receiver CRC register" hexmask.long 0x4 0.--31. 1. "RXCRC,RXCRC" group.long 0x4C++0x7 line.long 0x0 "SPI_UDRDR,SPI underrun data register" hexmask.long 0x0 0.--31. 1. "UDRDR,UDRDR" line.long 0x4 "SPI_I2SCFGR,All documented bits in this register must be configured when the I2S is disabled (SPE = 0).These bits are not used in SPI mode except for I2SMOD which needs to be set to 0 in SPI mode." bitfld.long 0x4 25. "MCKOE,MCKOE" "0,1" bitfld.long 0x4 24. "ODD,ODD" "0,1" hexmask.long.byte 0x4 16.--23. 1. "I2SDIV,I2SDIV" bitfld.long 0x4 14. "DATFMT,DATFMT" "0,1" bitfld.long 0x4 13. "WSINV,WSINV" "0,1" bitfld.long 0x4 12. "FIXCH,FIXCH" "0,1" bitfld.long 0x4 11. "CKPOL,CKPOL" "0,1" bitfld.long 0x4 10. "CHLEN,CHLEN" "0,1" newline bitfld.long 0x4 8.--9. "DATLEN,DATLEN" "0,1,2,3" bitfld.long 0x4 7. "PCMSYNC,PCMSYNC" "0,1" bitfld.long 0x4 4.--5. "I2SSTD,I2SSTD" "0,1,2,3" bitfld.long 0x4 1.--3. "I2SCFG,I2SCFG" "0,1,2,3,4,5,6,7" bitfld.long 0x4 0. "I2SMOD,I2SMOD" "0,1" rgroup.long 0x3F0++0xF line.long 0x0 "SPI_I2S_HWCFGR,SPI/I2S hardware configuration register" hexmask.long.byte 0x0 16.--19. 1. "DSCFG,DSCFG" hexmask.long.byte 0x0 12.--15. 1. "I2SCFG,I2SCFG" hexmask.long.byte 0x0 8.--11. 1. "CRCCFG,CRCCFG" hexmask.long.byte 0x0 4.--7. 1. "RXFCFG,RXFCFG" hexmask.long.byte 0x0 0.--3. 1. "TXFCFG,TXFCFG" line.long 0x4 "SPI_VERR,SPI/I2S version register" hexmask.long.byte 0x4 4.--7. 1. "MAJREV,MAJREV" hexmask.long.byte 0x4 0.--3. 1. "MINREV,MINREV" line.long 0x8 "SPI_IPIDR,SPI/I2S identification register" hexmask.long 0x8 0.--31. 1. "ID,ID" line.long 0xC "SPI_SIDR,SPI/I2S size identification register" hexmask.long 0xC 0.--31. 1. "SID,SID" tree.end tree "SPI3" base ad:0x4000C000 group.long 0x0++0x3 line.long 0x0 "SPI2S_CR1,SPI/I2S control register 1" bitfld.long 0x0 16. "IOLOCK,IOLOCK" "0,1" bitfld.long 0x0 15. "TCRCINI,TCRCINI" "0,1" bitfld.long 0x0 14. "RCRCINI,RCRCINI" "0,1" bitfld.long 0x0 13. "CRC33_17,CRC33_17" "0,1" bitfld.long 0x0 12. "SSI,SSI" "0,1" bitfld.long 0x0 11. "HDDIR,HDDIR" "0,1" bitfld.long 0x0 10. "CSUSP,CSUSP" "0,1" bitfld.long 0x0 9. "CSTART,CSTART" "0,1" newline bitfld.long 0x0 8. "MASRX,MASRX" "0,1" bitfld.long 0x0 0. "SPE,SPE" "0,1" group.long 0x10++0x3 line.long 0x0 "SPI2S_IER,SPI/I2S interrupt enable register" bitfld.long 0x0 10. "TSERFIE,TSERFIE" "0,1" bitfld.long 0x0 9. "MODFIE,MODFIE" "0,1" bitfld.long 0x0 8. "TIFREIE,TIFREIE" "0,1" bitfld.long 0x0 7. "CRCEIE,CRCEIE" "0,1" bitfld.long 0x0 6. "OVRIE,OVRIE" "0,1" bitfld.long 0x0 5. "UDRIE,UDRIE" "0,1" bitfld.long 0x0 4. "TXTFIE,TXTFIE" "0,1" bitfld.long 0x0 3. "EOTIE,EOTIE" "0,1" newline bitfld.long 0x0 2. "DXPIE,DXPIE" "0,1" bitfld.long 0x0 1. "TXPIE,TXPIE" "0,1" bitfld.long 0x0 0. "RXPIE,RXPIE" "0,1" rgroup.long 0x14++0x3 line.long 0x0 "SPI2S_SR,SPI/I2S status register" hexmask.long.word 0x0 16.--31. 1. "CTSIZE,CTSIZE" bitfld.long 0x0 15. "RXWNE,RXWNE" "0,1" bitfld.long 0x0 13.--14. "RXPLVL,RXPLVL" "0,1,2,3" bitfld.long 0x0 12. "TXC,TXC" "0,1" bitfld.long 0x0 11. "SUSP,SUSP" "0,1" bitfld.long 0x0 10. "TSERF,TSERF" "0,1" bitfld.long 0x0 9. "MODF,MODF" "0,1" bitfld.long 0x0 8. "TIFRE,TIFRE" "0,1" newline bitfld.long 0x0 7. "CRCE,CRCE" "0,1" bitfld.long 0x0 6. "OVR,OVR" "0,1" bitfld.long 0x0 5. "UDR,UDR" "0,1" bitfld.long 0x0 4. "TXTF,TXTF" "0,1" bitfld.long 0x0 3. "EOT,EOT" "0,1" bitfld.long 0x0 2. "DXP,DXP" "0,1" bitfld.long 0x0 1. "TXP,TXP" "0,1" bitfld.long 0x0 0. "RXP,RXP" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "SPI2S_IFCR,SPI/I2S interrupt/status flags clear register" bitfld.long 0x0 11. "SUSPC,SUSPC" "0,1" bitfld.long 0x0 10. "TSERFC,TSERFC" "0,1" bitfld.long 0x0 9. "MODFC,MODFC" "0,1" bitfld.long 0x0 8. "TIFREC,TIFREC" "0,1" bitfld.long 0x0 7. "CRCEC,CRCEC" "0,1" bitfld.long 0x0 6. "OVRC,OVRC" "0,1" bitfld.long 0x0 5. "UDRC,UDRC" "0,1" bitfld.long 0x0 4. "TXTFC,TXTFC" "0,1" newline bitfld.long 0x0 3. "EOTC,EOTC" "0,1" wgroup.long 0x20++0x3 line.long 0x0 "SPI2S_TXDR,SPI/I2S transmit data register" hexmask.long 0x0 0.--31. 1. "TXDR,TXDR" rgroup.long 0x30++0x3 line.long 0x0 "SPI2S_RXDR,SPI/I2S receive data register" hexmask.long 0x0 0.--31. 1. "RXDR,RXDR" group.long 0x4++0xB line.long 0x0 "SPI_CR2,SPI control register 2" hexmask.long.word 0x0 16.--31. 1. "TSER,TSER" hexmask.long.word 0x0 0.--15. 1. "TSIZE,TSIZE" line.long 0x4 "SPI_CFG1,Content of this register is write protected when SPI is enabled" bitfld.long 0x4 28.--30. "MBR,MBR" "0,1,2,3,4,5,6,7" bitfld.long 0x4 22. "CRCEN,CRCEN" "0,1" hexmask.long.byte 0x4 16.--20. 1. "CRCSIZE,CRCSIZE" bitfld.long 0x4 15. "TXDMAEN,TXDMAEN" "0,1" bitfld.long 0x4 14. "RXDMAEN,RXDMAEN" "0,1" bitfld.long 0x4 11.--12. "UDRDET,UDRDET" "0,1,2,3" bitfld.long 0x4 9.--10. "UDRCFG,UDRCFG" "0,1,2,3" hexmask.long.byte 0x4 5.--8. 1. "FTHLV,FTHLV" newline hexmask.long.byte 0x4 0.--4. 1. "DSIZE,DSIZE" line.long 0x8 "SPI_CFG2,The content of this register is write protected when SPI is enabled or IOLOCK bit is set at SPI2S_CR1 register." bitfld.long 0x8 31. "AFCNTR,AFCNTR" "0,1" bitfld.long 0x8 30. "SSOM,SSOM" "0,1" bitfld.long 0x8 29. "SSOE,SSOE" "0,1" bitfld.long 0x8 28. "SSIOP,SSIOP" "0,1" bitfld.long 0x8 26. "SSM,SSM" "0,1" bitfld.long 0x8 25. "CPOL,CPOL" "0,1" bitfld.long 0x8 24. "CPHA,CPHA" "0,1" bitfld.long 0x8 23. "LSBFRST,LSBFRST" "0,1" newline bitfld.long 0x8 22. "MASTER,MASTER" "0,1" bitfld.long 0x8 19.--21. "SP,SP" "0,1,2,3,4,5,6,7" bitfld.long 0x8 17.--18. "COMM,COMM" "0,1,2,3" bitfld.long 0x8 15. "IOSWP,IOSWP" "0,1" hexmask.long.byte 0x8 4.--7. 1. "MIDI,MIDI" hexmask.long.byte 0x8 0.--3. 1. "MSSI,MSSI" group.long 0x40++0x3 line.long 0x0 "SPI_CRCPOLY,SPI polynomial register" hexmask.long 0x0 0.--31. 1. "CRCPOLY,CRCPOLY" rgroup.long 0x44++0x7 line.long 0x0 "SPI_TXCRC,SPI transmitter CRC register" hexmask.long 0x0 0.--31. 1. "TXCRC,TXCRC" line.long 0x4 "SPI_RXCRC,SPI receiver CRC register" hexmask.long 0x4 0.--31. 1. "RXCRC,RXCRC" group.long 0x4C++0x7 line.long 0x0 "SPI_UDRDR,SPI underrun data register" hexmask.long 0x0 0.--31. 1. "UDRDR,UDRDR" line.long 0x4 "SPI_I2SCFGR,All documented bits in this register must be configured when the I2S is disabled (SPE = 0).These bits are not used in SPI mode except for I2SMOD which needs to be set to 0 in SPI mode." bitfld.long 0x4 25. "MCKOE,MCKOE" "0,1" bitfld.long 0x4 24. "ODD,ODD" "0,1" hexmask.long.byte 0x4 16.--23. 1. "I2SDIV,I2SDIV" bitfld.long 0x4 14. "DATFMT,DATFMT" "0,1" bitfld.long 0x4 13. "WSINV,WSINV" "0,1" bitfld.long 0x4 12. "FIXCH,FIXCH" "0,1" bitfld.long 0x4 11. "CKPOL,CKPOL" "0,1" bitfld.long 0x4 10. "CHLEN,CHLEN" "0,1" newline bitfld.long 0x4 8.--9. "DATLEN,DATLEN" "0,1,2,3" bitfld.long 0x4 7. "PCMSYNC,PCMSYNC" "0,1" bitfld.long 0x4 4.--5. "I2SSTD,I2SSTD" "0,1,2,3" bitfld.long 0x4 1.--3. "I2SCFG,I2SCFG" "0,1,2,3,4,5,6,7" bitfld.long 0x4 0. "I2SMOD,I2SMOD" "0,1" rgroup.long 0x3F0++0xF line.long 0x0 "SPI_I2S_HWCFGR,SPI/I2S hardware configuration register" hexmask.long.byte 0x0 16.--19. 1. "DSCFG,DSCFG" hexmask.long.byte 0x0 12.--15. 1. "I2SCFG,I2SCFG" hexmask.long.byte 0x0 8.--11. 1. "CRCCFG,CRCCFG" hexmask.long.byte 0x0 4.--7. 1. "RXFCFG,RXFCFG" hexmask.long.byte 0x0 0.--3. 1. "TXFCFG,TXFCFG" line.long 0x4 "SPI_VERR,SPI/I2S version register" hexmask.long.byte 0x4 4.--7. 1. "MAJREV,MAJREV" hexmask.long.byte 0x4 0.--3. 1. "MINREV,MINREV" line.long 0x8 "SPI_IPIDR,SPI/I2S identification register" hexmask.long 0x8 0.--31. 1. "ID,ID" line.long 0xC "SPI_SIDR,SPI/I2S size identification register" hexmask.long 0xC 0.--31. 1. "SID,SID" tree.end tree "SPI4" base ad:0x44005000 group.long 0x0++0x3 line.long 0x0 "SPI2S_CR1,SPI/I2S control register 1" bitfld.long 0x0 16. "IOLOCK,IOLOCK" "0,1" bitfld.long 0x0 15. "TCRCINI,TCRCINI" "0,1" bitfld.long 0x0 14. "RCRCINI,RCRCINI" "0,1" bitfld.long 0x0 13. "CRC33_17,CRC33_17" "0,1" bitfld.long 0x0 12. "SSI,SSI" "0,1" bitfld.long 0x0 11. "HDDIR,HDDIR" "0,1" bitfld.long 0x0 10. "CSUSP,CSUSP" "0,1" bitfld.long 0x0 9. "CSTART,CSTART" "0,1" newline bitfld.long 0x0 8. "MASRX,MASRX" "0,1" bitfld.long 0x0 0. "SPE,SPE" "0,1" group.long 0x10++0x3 line.long 0x0 "SPI2S_IER,SPI/I2S interrupt enable register" bitfld.long 0x0 10. "TSERFIE,TSERFIE" "0,1" bitfld.long 0x0 9. "MODFIE,MODFIE" "0,1" bitfld.long 0x0 8. "TIFREIE,TIFREIE" "0,1" bitfld.long 0x0 7. "CRCEIE,CRCEIE" "0,1" bitfld.long 0x0 6. "OVRIE,OVRIE" "0,1" bitfld.long 0x0 5. "UDRIE,UDRIE" "0,1" bitfld.long 0x0 4. "TXTFIE,TXTFIE" "0,1" bitfld.long 0x0 3. "EOTIE,EOTIE" "0,1" newline bitfld.long 0x0 2. "DXPIE,DXPIE" "0,1" bitfld.long 0x0 1. "TXPIE,TXPIE" "0,1" bitfld.long 0x0 0. "RXPIE,RXPIE" "0,1" rgroup.long 0x14++0x3 line.long 0x0 "SPI2S_SR,SPI/I2S status register" hexmask.long.word 0x0 16.--31. 1. "CTSIZE,CTSIZE" bitfld.long 0x0 15. "RXWNE,RXWNE" "0,1" bitfld.long 0x0 13.--14. "RXPLVL,RXPLVL" "0,1,2,3" bitfld.long 0x0 12. "TXC,TXC" "0,1" bitfld.long 0x0 11. "SUSP,SUSP" "0,1" bitfld.long 0x0 10. "TSERF,TSERF" "0,1" bitfld.long 0x0 9. "MODF,MODF" "0,1" bitfld.long 0x0 8. "TIFRE,TIFRE" "0,1" newline bitfld.long 0x0 7. "CRCE,CRCE" "0,1" bitfld.long 0x0 6. "OVR,OVR" "0,1" bitfld.long 0x0 5. "UDR,UDR" "0,1" bitfld.long 0x0 4. "TXTF,TXTF" "0,1" bitfld.long 0x0 3. "EOT,EOT" "0,1" bitfld.long 0x0 2. "DXP,DXP" "0,1" bitfld.long 0x0 1. "TXP,TXP" "0,1" bitfld.long 0x0 0. "RXP,RXP" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "SPI2S_IFCR,SPI/I2S interrupt/status flags clear register" bitfld.long 0x0 11. "SUSPC,SUSPC" "0,1" bitfld.long 0x0 10. "TSERFC,TSERFC" "0,1" bitfld.long 0x0 9. "MODFC,MODFC" "0,1" bitfld.long 0x0 8. "TIFREC,TIFREC" "0,1" bitfld.long 0x0 7. "CRCEC,CRCEC" "0,1" bitfld.long 0x0 6. "OVRC,OVRC" "0,1" bitfld.long 0x0 5. "UDRC,UDRC" "0,1" bitfld.long 0x0 4. "TXTFC,TXTFC" "0,1" newline bitfld.long 0x0 3. "EOTC,EOTC" "0,1" wgroup.long 0x20++0x3 line.long 0x0 "SPI2S_TXDR,SPI/I2S transmit data register" hexmask.long 0x0 0.--31. 1. "TXDR,TXDR" rgroup.long 0x30++0x3 line.long 0x0 "SPI2S_RXDR,SPI/I2S receive data register" hexmask.long 0x0 0.--31. 1. "RXDR,RXDR" group.long 0x4++0xB line.long 0x0 "SPI_CR2,SPI control register 2" hexmask.long.word 0x0 16.--31. 1. "TSER,TSER" hexmask.long.word 0x0 0.--15. 1. "TSIZE,TSIZE" line.long 0x4 "SPI_CFG1,Content of this register is write protected when SPI is enabled" bitfld.long 0x4 28.--30. "MBR,MBR" "0,1,2,3,4,5,6,7" bitfld.long 0x4 22. "CRCEN,CRCEN" "0,1" hexmask.long.byte 0x4 16.--20. 1. "CRCSIZE,CRCSIZE" bitfld.long 0x4 15. "TXDMAEN,TXDMAEN" "0,1" bitfld.long 0x4 14. "RXDMAEN,RXDMAEN" "0,1" bitfld.long 0x4 11.--12. "UDRDET,UDRDET" "0,1,2,3" bitfld.long 0x4 9.--10. "UDRCFG,UDRCFG" "0,1,2,3" hexmask.long.byte 0x4 5.--8. 1. "FTHLV,FTHLV" newline hexmask.long.byte 0x4 0.--4. 1. "DSIZE,DSIZE" line.long 0x8 "SPI_CFG2,The content of this register is write protected when SPI is enabled or IOLOCK bit is set at SPI2S_CR1 register." bitfld.long 0x8 31. "AFCNTR,AFCNTR" "0,1" bitfld.long 0x8 30. "SSOM,SSOM" "0,1" bitfld.long 0x8 29. "SSOE,SSOE" "0,1" bitfld.long 0x8 28. "SSIOP,SSIOP" "0,1" bitfld.long 0x8 26. "SSM,SSM" "0,1" bitfld.long 0x8 25. "CPOL,CPOL" "0,1" bitfld.long 0x8 24. "CPHA,CPHA" "0,1" bitfld.long 0x8 23. "LSBFRST,LSBFRST" "0,1" newline bitfld.long 0x8 22. "MASTER,MASTER" "0,1" bitfld.long 0x8 19.--21. "SP,SP" "0,1,2,3,4,5,6,7" bitfld.long 0x8 17.--18. "COMM,COMM" "0,1,2,3" bitfld.long 0x8 15. "IOSWP,IOSWP" "0,1" hexmask.long.byte 0x8 4.--7. 1. "MIDI,MIDI" hexmask.long.byte 0x8 0.--3. 1. "MSSI,MSSI" group.long 0x40++0x3 line.long 0x0 "SPI_CRCPOLY,SPI polynomial register" hexmask.long 0x0 0.--31. 1. "CRCPOLY,CRCPOLY" rgroup.long 0x44++0x7 line.long 0x0 "SPI_TXCRC,SPI transmitter CRC register" hexmask.long 0x0 0.--31. 1. "TXCRC,TXCRC" line.long 0x4 "SPI_RXCRC,SPI receiver CRC register" hexmask.long 0x4 0.--31. 1. "RXCRC,RXCRC" group.long 0x4C++0x7 line.long 0x0 "SPI_UDRDR,SPI underrun data register" hexmask.long 0x0 0.--31. 1. "UDRDR,UDRDR" line.long 0x4 "SPI_I2SCFGR,All documented bits in this register must be configured when the I2S is disabled (SPE = 0).These bits are not used in SPI mode except for I2SMOD which needs to be set to 0 in SPI mode." bitfld.long 0x4 25. "MCKOE,MCKOE" "0,1" bitfld.long 0x4 24. "ODD,ODD" "0,1" hexmask.long.byte 0x4 16.--23. 1. "I2SDIV,I2SDIV" bitfld.long 0x4 14. "DATFMT,DATFMT" "0,1" bitfld.long 0x4 13. "WSINV,WSINV" "0,1" bitfld.long 0x4 12. "FIXCH,FIXCH" "0,1" bitfld.long 0x4 11. "CKPOL,CKPOL" "0,1" bitfld.long 0x4 10. "CHLEN,CHLEN" "0,1" newline bitfld.long 0x4 8.--9. "DATLEN,DATLEN" "0,1,2,3" bitfld.long 0x4 7. "PCMSYNC,PCMSYNC" "0,1" bitfld.long 0x4 4.--5. "I2SSTD,I2SSTD" "0,1,2,3" bitfld.long 0x4 1.--3. "I2SCFG,I2SCFG" "0,1,2,3,4,5,6,7" bitfld.long 0x4 0. "I2SMOD,I2SMOD" "0,1" rgroup.long 0x3F0++0xF line.long 0x0 "SPI_I2S_HWCFGR,SPI/I2S hardware configuration register" hexmask.long.byte 0x0 16.--19. 1. "DSCFG,DSCFG" hexmask.long.byte 0x0 12.--15. 1. "I2SCFG,I2SCFG" hexmask.long.byte 0x0 8.--11. 1. "CRCCFG,CRCCFG" hexmask.long.byte 0x0 4.--7. 1. "RXFCFG,RXFCFG" hexmask.long.byte 0x0 0.--3. 1. "TXFCFG,TXFCFG" line.long 0x4 "SPI_VERR,SPI/I2S version register" hexmask.long.byte 0x4 4.--7. 1. "MAJREV,MAJREV" hexmask.long.byte 0x4 0.--3. 1. "MINREV,MINREV" line.long 0x8 "SPI_IPIDR,SPI/I2S identification register" hexmask.long 0x8 0.--31. 1. "ID,ID" line.long 0xC "SPI_SIDR,SPI/I2S size identification register" hexmask.long 0xC 0.--31. 1. "SID,SID" tree.end tree "SPI5" base ad:0x44009000 group.long 0x0++0x3 line.long 0x0 "SPI2S_CR1,SPI/I2S control register 1" bitfld.long 0x0 16. "IOLOCK,IOLOCK" "0,1" bitfld.long 0x0 15. "TCRCINI,TCRCINI" "0,1" bitfld.long 0x0 14. "RCRCINI,RCRCINI" "0,1" bitfld.long 0x0 13. "CRC33_17,CRC33_17" "0,1" bitfld.long 0x0 12. "SSI,SSI" "0,1" bitfld.long 0x0 11. "HDDIR,HDDIR" "0,1" bitfld.long 0x0 10. "CSUSP,CSUSP" "0,1" bitfld.long 0x0 9. "CSTART,CSTART" "0,1" newline bitfld.long 0x0 8. "MASRX,MASRX" "0,1" bitfld.long 0x0 0. "SPE,SPE" "0,1" group.long 0x10++0x3 line.long 0x0 "SPI2S_IER,SPI/I2S interrupt enable register" bitfld.long 0x0 10. "TSERFIE,TSERFIE" "0,1" bitfld.long 0x0 9. "MODFIE,MODFIE" "0,1" bitfld.long 0x0 8. "TIFREIE,TIFREIE" "0,1" bitfld.long 0x0 7. "CRCEIE,CRCEIE" "0,1" bitfld.long 0x0 6. "OVRIE,OVRIE" "0,1" bitfld.long 0x0 5. "UDRIE,UDRIE" "0,1" bitfld.long 0x0 4. "TXTFIE,TXTFIE" "0,1" bitfld.long 0x0 3. "EOTIE,EOTIE" "0,1" newline bitfld.long 0x0 2. "DXPIE,DXPIE" "0,1" bitfld.long 0x0 1. "TXPIE,TXPIE" "0,1" bitfld.long 0x0 0. "RXPIE,RXPIE" "0,1" rgroup.long 0x14++0x3 line.long 0x0 "SPI2S_SR,SPI/I2S status register" hexmask.long.word 0x0 16.--31. 1. "CTSIZE,CTSIZE" bitfld.long 0x0 15. "RXWNE,RXWNE" "0,1" bitfld.long 0x0 13.--14. "RXPLVL,RXPLVL" "0,1,2,3" bitfld.long 0x0 12. "TXC,TXC" "0,1" bitfld.long 0x0 11. "SUSP,SUSP" "0,1" bitfld.long 0x0 10. "TSERF,TSERF" "0,1" bitfld.long 0x0 9. "MODF,MODF" "0,1" bitfld.long 0x0 8. "TIFRE,TIFRE" "0,1" newline bitfld.long 0x0 7. "CRCE,CRCE" "0,1" bitfld.long 0x0 6. "OVR,OVR" "0,1" bitfld.long 0x0 5. "UDR,UDR" "0,1" bitfld.long 0x0 4. "TXTF,TXTF" "0,1" bitfld.long 0x0 3. "EOT,EOT" "0,1" bitfld.long 0x0 2. "DXP,DXP" "0,1" bitfld.long 0x0 1. "TXP,TXP" "0,1" bitfld.long 0x0 0. "RXP,RXP" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "SPI2S_IFCR,SPI/I2S interrupt/status flags clear register" bitfld.long 0x0 11. "SUSPC,SUSPC" "0,1" bitfld.long 0x0 10. "TSERFC,TSERFC" "0,1" bitfld.long 0x0 9. "MODFC,MODFC" "0,1" bitfld.long 0x0 8. "TIFREC,TIFREC" "0,1" bitfld.long 0x0 7. "CRCEC,CRCEC" "0,1" bitfld.long 0x0 6. "OVRC,OVRC" "0,1" bitfld.long 0x0 5. "UDRC,UDRC" "0,1" bitfld.long 0x0 4. "TXTFC,TXTFC" "0,1" newline bitfld.long 0x0 3. "EOTC,EOTC" "0,1" wgroup.long 0x20++0x3 line.long 0x0 "SPI2S_TXDR,SPI/I2S transmit data register" hexmask.long 0x0 0.--31. 1. "TXDR,TXDR" rgroup.long 0x30++0x3 line.long 0x0 "SPI2S_RXDR,SPI/I2S receive data register" hexmask.long 0x0 0.--31. 1. "RXDR,RXDR" group.long 0x4++0xB line.long 0x0 "SPI_CR2,SPI control register 2" hexmask.long.word 0x0 16.--31. 1. "TSER,TSER" hexmask.long.word 0x0 0.--15. 1. "TSIZE,TSIZE" line.long 0x4 "SPI_CFG1,Content of this register is write protected when SPI is enabled" bitfld.long 0x4 28.--30. "MBR,MBR" "0,1,2,3,4,5,6,7" bitfld.long 0x4 22. "CRCEN,CRCEN" "0,1" hexmask.long.byte 0x4 16.--20. 1. "CRCSIZE,CRCSIZE" bitfld.long 0x4 15. "TXDMAEN,TXDMAEN" "0,1" bitfld.long 0x4 14. "RXDMAEN,RXDMAEN" "0,1" bitfld.long 0x4 11.--12. "UDRDET,UDRDET" "0,1,2,3" bitfld.long 0x4 9.--10. "UDRCFG,UDRCFG" "0,1,2,3" hexmask.long.byte 0x4 5.--8. 1. "FTHLV,FTHLV" newline hexmask.long.byte 0x4 0.--4. 1. "DSIZE,DSIZE" line.long 0x8 "SPI_CFG2,The content of this register is write protected when SPI is enabled or IOLOCK bit is set at SPI2S_CR1 register." bitfld.long 0x8 31. "AFCNTR,AFCNTR" "0,1" bitfld.long 0x8 30. "SSOM,SSOM" "0,1" bitfld.long 0x8 29. "SSOE,SSOE" "0,1" bitfld.long 0x8 28. "SSIOP,SSIOP" "0,1" bitfld.long 0x8 26. "SSM,SSM" "0,1" bitfld.long 0x8 25. "CPOL,CPOL" "0,1" bitfld.long 0x8 24. "CPHA,CPHA" "0,1" bitfld.long 0x8 23. "LSBFRST,LSBFRST" "0,1" newline bitfld.long 0x8 22. "MASTER,MASTER" "0,1" bitfld.long 0x8 19.--21. "SP,SP" "0,1,2,3,4,5,6,7" bitfld.long 0x8 17.--18. "COMM,COMM" "0,1,2,3" bitfld.long 0x8 15. "IOSWP,IOSWP" "0,1" hexmask.long.byte 0x8 4.--7. 1. "MIDI,MIDI" hexmask.long.byte 0x8 0.--3. 1. "MSSI,MSSI" group.long 0x40++0x3 line.long 0x0 "SPI_CRCPOLY,SPI polynomial register" hexmask.long 0x0 0.--31. 1. "CRCPOLY,CRCPOLY" rgroup.long 0x44++0x7 line.long 0x0 "SPI_TXCRC,SPI transmitter CRC register" hexmask.long 0x0 0.--31. 1. "TXCRC,TXCRC" line.long 0x4 "SPI_RXCRC,SPI receiver CRC register" hexmask.long 0x4 0.--31. 1. "RXCRC,RXCRC" group.long 0x4C++0x7 line.long 0x0 "SPI_UDRDR,SPI underrun data register" hexmask.long 0x0 0.--31. 1. "UDRDR,UDRDR" line.long 0x4 "SPI_I2SCFGR,All documented bits in this register must be configured when the I2S is disabled (SPE = 0).These bits are not used in SPI mode except for I2SMOD which needs to be set to 0 in SPI mode." bitfld.long 0x4 25. "MCKOE,MCKOE" "0,1" bitfld.long 0x4 24. "ODD,ODD" "0,1" hexmask.long.byte 0x4 16.--23. 1. "I2SDIV,I2SDIV" bitfld.long 0x4 14. "DATFMT,DATFMT" "0,1" bitfld.long 0x4 13. "WSINV,WSINV" "0,1" bitfld.long 0x4 12. "FIXCH,FIXCH" "0,1" bitfld.long 0x4 11. "CKPOL,CKPOL" "0,1" bitfld.long 0x4 10. "CHLEN,CHLEN" "0,1" newline bitfld.long 0x4 8.--9. "DATLEN,DATLEN" "0,1,2,3" bitfld.long 0x4 7. "PCMSYNC,PCMSYNC" "0,1" bitfld.long 0x4 4.--5. "I2SSTD,I2SSTD" "0,1,2,3" bitfld.long 0x4 1.--3. "I2SCFG,I2SCFG" "0,1,2,3,4,5,6,7" bitfld.long 0x4 0. "I2SMOD,I2SMOD" "0,1" rgroup.long 0x3F0++0xF line.long 0x0 "SPI_I2S_HWCFGR,SPI/I2S hardware configuration register" hexmask.long.byte 0x0 16.--19. 1. "DSCFG,DSCFG" hexmask.long.byte 0x0 12.--15. 1. "I2SCFG,I2SCFG" hexmask.long.byte 0x0 8.--11. 1. "CRCCFG,CRCCFG" hexmask.long.byte 0x0 4.--7. 1. "RXFCFG,RXFCFG" hexmask.long.byte 0x0 0.--3. 1. "TXFCFG,TXFCFG" line.long 0x4 "SPI_VERR,SPI/I2S version register" hexmask.long.byte 0x4 4.--7. 1. "MAJREV,MAJREV" hexmask.long.byte 0x4 0.--3. 1. "MINREV,MINREV" line.long 0x8 "SPI_IPIDR,SPI/I2S identification register" hexmask.long 0x8 0.--31. 1. "ID,ID" line.long 0xC "SPI_SIDR,SPI/I2S size identification register" hexmask.long 0xC 0.--31. 1. "SID,SID" tree.end tree "SPI6" base ad:0x5C001000 group.long 0x0++0x3 line.long 0x0 "SPI2S_CR1,SPI/I2S control register 1" bitfld.long 0x0 16. "IOLOCK,IOLOCK" "0,1" bitfld.long 0x0 15. "TCRCINI,TCRCINI" "0,1" bitfld.long 0x0 14. "RCRCINI,RCRCINI" "0,1" bitfld.long 0x0 13. "CRC33_17,CRC33_17" "0,1" bitfld.long 0x0 12. "SSI,SSI" "0,1" bitfld.long 0x0 11. "HDDIR,HDDIR" "0,1" bitfld.long 0x0 10. "CSUSP,CSUSP" "0,1" bitfld.long 0x0 9. "CSTART,CSTART" "0,1" newline bitfld.long 0x0 8. "MASRX,MASRX" "0,1" bitfld.long 0x0 0. "SPE,SPE" "0,1" group.long 0x10++0x3 line.long 0x0 "SPI2S_IER,SPI/I2S interrupt enable register" bitfld.long 0x0 10. "TSERFIE,TSERFIE" "0,1" bitfld.long 0x0 9. "MODFIE,MODFIE" "0,1" bitfld.long 0x0 8. "TIFREIE,TIFREIE" "0,1" bitfld.long 0x0 7. "CRCEIE,CRCEIE" "0,1" bitfld.long 0x0 6. "OVRIE,OVRIE" "0,1" bitfld.long 0x0 5. "UDRIE,UDRIE" "0,1" bitfld.long 0x0 4. "TXTFIE,TXTFIE" "0,1" bitfld.long 0x0 3. "EOTIE,EOTIE" "0,1" newline bitfld.long 0x0 2. "DXPIE,DXPIE" "0,1" bitfld.long 0x0 1. "TXPIE,TXPIE" "0,1" bitfld.long 0x0 0. "RXPIE,RXPIE" "0,1" rgroup.long 0x14++0x3 line.long 0x0 "SPI2S_SR,SPI/I2S status register" hexmask.long.word 0x0 16.--31. 1. "CTSIZE,CTSIZE" bitfld.long 0x0 15. "RXWNE,RXWNE" "0,1" bitfld.long 0x0 13.--14. "RXPLVL,RXPLVL" "0,1,2,3" bitfld.long 0x0 12. "TXC,TXC" "0,1" bitfld.long 0x0 11. "SUSP,SUSP" "0,1" bitfld.long 0x0 10. "TSERF,TSERF" "0,1" bitfld.long 0x0 9. "MODF,MODF" "0,1" bitfld.long 0x0 8. "TIFRE,TIFRE" "0,1" newline bitfld.long 0x0 7. "CRCE,CRCE" "0,1" bitfld.long 0x0 6. "OVR,OVR" "0,1" bitfld.long 0x0 5. "UDR,UDR" "0,1" bitfld.long 0x0 4. "TXTF,TXTF" "0,1" bitfld.long 0x0 3. "EOT,EOT" "0,1" bitfld.long 0x0 2. "DXP,DXP" "0,1" bitfld.long 0x0 1. "TXP,TXP" "0,1" bitfld.long 0x0 0. "RXP,RXP" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "SPI2S_IFCR,SPI/I2S interrupt/status flags clear register" bitfld.long 0x0 11. "SUSPC,SUSPC" "0,1" bitfld.long 0x0 10. "TSERFC,TSERFC" "0,1" bitfld.long 0x0 9. "MODFC,MODFC" "0,1" bitfld.long 0x0 8. "TIFREC,TIFREC" "0,1" bitfld.long 0x0 7. "CRCEC,CRCEC" "0,1" bitfld.long 0x0 6. "OVRC,OVRC" "0,1" bitfld.long 0x0 5. "UDRC,UDRC" "0,1" bitfld.long 0x0 4. "TXTFC,TXTFC" "0,1" newline bitfld.long 0x0 3. "EOTC,EOTC" "0,1" wgroup.long 0x20++0x3 line.long 0x0 "SPI2S_TXDR,SPI/I2S transmit data register" hexmask.long 0x0 0.--31. 1. "TXDR,TXDR" rgroup.long 0x30++0x3 line.long 0x0 "SPI2S_RXDR,SPI/I2S receive data register" hexmask.long 0x0 0.--31. 1. "RXDR,RXDR" group.long 0x4++0xB line.long 0x0 "SPI_CR2,SPI control register 2" hexmask.long.word 0x0 16.--31. 1. "TSER,TSER" hexmask.long.word 0x0 0.--15. 1. "TSIZE,TSIZE" line.long 0x4 "SPI_CFG1,Content of this register is write protected when SPI is enabled" bitfld.long 0x4 28.--30. "MBR,MBR" "0,1,2,3,4,5,6,7" bitfld.long 0x4 22. "CRCEN,CRCEN" "0,1" hexmask.long.byte 0x4 16.--20. 1. "CRCSIZE,CRCSIZE" bitfld.long 0x4 15. "TXDMAEN,TXDMAEN" "0,1" bitfld.long 0x4 14. "RXDMAEN,RXDMAEN" "0,1" bitfld.long 0x4 11.--12. "UDRDET,UDRDET" "0,1,2,3" bitfld.long 0x4 9.--10. "UDRCFG,UDRCFG" "0,1,2,3" hexmask.long.byte 0x4 5.--8. 1. "FTHLV,FTHLV" newline hexmask.long.byte 0x4 0.--4. 1. "DSIZE,DSIZE" line.long 0x8 "SPI_CFG2,The content of this register is write protected when SPI is enabled or IOLOCK bit is set at SPI2S_CR1 register." bitfld.long 0x8 31. "AFCNTR,AFCNTR" "0,1" bitfld.long 0x8 30. "SSOM,SSOM" "0,1" bitfld.long 0x8 29. "SSOE,SSOE" "0,1" bitfld.long 0x8 28. "SSIOP,SSIOP" "0,1" bitfld.long 0x8 26. "SSM,SSM" "0,1" bitfld.long 0x8 25. "CPOL,CPOL" "0,1" bitfld.long 0x8 24. "CPHA,CPHA" "0,1" bitfld.long 0x8 23. "LSBFRST,LSBFRST" "0,1" newline bitfld.long 0x8 22. "MASTER,MASTER" "0,1" bitfld.long 0x8 19.--21. "SP,SP" "0,1,2,3,4,5,6,7" bitfld.long 0x8 17.--18. "COMM,COMM" "0,1,2,3" bitfld.long 0x8 15. "IOSWP,IOSWP" "0,1" hexmask.long.byte 0x8 4.--7. 1. "MIDI,MIDI" hexmask.long.byte 0x8 0.--3. 1. "MSSI,MSSI" group.long 0x40++0x3 line.long 0x0 "SPI_CRCPOLY,SPI polynomial register" hexmask.long 0x0 0.--31. 1. "CRCPOLY,CRCPOLY" rgroup.long 0x44++0x7 line.long 0x0 "SPI_TXCRC,SPI transmitter CRC register" hexmask.long 0x0 0.--31. 1. "TXCRC,TXCRC" line.long 0x4 "SPI_RXCRC,SPI receiver CRC register" hexmask.long 0x4 0.--31. 1. "RXCRC,RXCRC" group.long 0x4C++0x7 line.long 0x0 "SPI_UDRDR,SPI underrun data register" hexmask.long 0x0 0.--31. 1. "UDRDR,UDRDR" line.long 0x4 "SPI_I2SCFGR,All documented bits in this register must be configured when the I2S is disabled (SPE = 0).These bits are not used in SPI mode except for I2SMOD which needs to be set to 0 in SPI mode." bitfld.long 0x4 25. "MCKOE,MCKOE" "0,1" bitfld.long 0x4 24. "ODD,ODD" "0,1" hexmask.long.byte 0x4 16.--23. 1. "I2SDIV,I2SDIV" bitfld.long 0x4 14. "DATFMT,DATFMT" "0,1" bitfld.long 0x4 13. "WSINV,WSINV" "0,1" bitfld.long 0x4 12. "FIXCH,FIXCH" "0,1" bitfld.long 0x4 11. "CKPOL,CKPOL" "0,1" bitfld.long 0x4 10. "CHLEN,CHLEN" "0,1" newline bitfld.long 0x4 8.--9. "DATLEN,DATLEN" "0,1,2,3" bitfld.long 0x4 7. "PCMSYNC,PCMSYNC" "0,1" bitfld.long 0x4 4.--5. "I2SSTD,I2SSTD" "0,1,2,3" bitfld.long 0x4 1.--3. "I2SCFG,I2SCFG" "0,1,2,3,4,5,6,7" bitfld.long 0x4 0. "I2SMOD,I2SMOD" "0,1" rgroup.long 0x3F0++0xF line.long 0x0 "SPI_I2S_HWCFGR,SPI/I2S hardware configuration register" hexmask.long.byte 0x0 16.--19. 1. "DSCFG,DSCFG" hexmask.long.byte 0x0 12.--15. 1. "I2SCFG,I2SCFG" hexmask.long.byte 0x0 8.--11. 1. "CRCCFG,CRCCFG" hexmask.long.byte 0x0 4.--7. 1. "RXFCFG,RXFCFG" hexmask.long.byte 0x0 0.--3. 1. "TXFCFG,TXFCFG" line.long 0x4 "SPI_VERR,SPI/I2S version register" hexmask.long.byte 0x4 4.--7. 1. "MAJREV,MAJREV" hexmask.long.byte 0x4 0.--3. 1. "MINREV,MINREV" line.long 0x8 "SPI_IPIDR,SPI/I2S identification register" hexmask.long 0x8 0.--31. 1. "ID,ID" line.long 0xC "SPI_SIDR,SPI/I2S size identification register" hexmask.long 0xC 0.--31. 1. "SID,SID" tree.end endif sif (cpuis("STM32MP157*")) tree "SPI1" base ad:0x44004000 group.long 0x0++0x3 line.long 0x0 "SPI2S_CR1,SPI/I2S control register 1" bitfld.long 0x0 16. "IOLOCK,IOLOCK" "0,1" bitfld.long 0x0 15. "TCRCINI,TCRCINI" "0,1" bitfld.long 0x0 14. "RCRCINI,RCRCINI" "0,1" bitfld.long 0x0 13. "CRC33_17,CRC33_17" "0,1" bitfld.long 0x0 12. "SSI,SSI" "0,1" bitfld.long 0x0 11. "HDDIR,HDDIR" "0,1" bitfld.long 0x0 10. "CSUSP,CSUSP" "0,1" bitfld.long 0x0 9. "CSTART,CSTART" "0,1" newline bitfld.long 0x0 8. "MASRX,MASRX" "0,1" bitfld.long 0x0 0. "SPE,SPE" "0,1" group.long 0x10++0x3 line.long 0x0 "SPI2S_IER,SPI/I2S interrupt enable register" bitfld.long 0x0 10. "TSERFIE,TSERFIE" "0,1" bitfld.long 0x0 9. "MODFIE,MODFIE" "0,1" bitfld.long 0x0 8. "TIFREIE,TIFREIE" "0,1" bitfld.long 0x0 7. "CRCEIE,CRCEIE" "0,1" bitfld.long 0x0 6. "OVRIE,OVRIE" "0,1" bitfld.long 0x0 5. "UDRIE,UDRIE" "0,1" bitfld.long 0x0 4. "TXTFIE,TXTFIE" "0,1" bitfld.long 0x0 3. "EOTIE,EOTIE" "0,1" newline bitfld.long 0x0 2. "DXPIE,DXPIE" "0,1" bitfld.long 0x0 1. "TXPIE,TXPIE" "0,1" bitfld.long 0x0 0. "RXPIE,RXPIE" "0,1" rgroup.long 0x14++0x3 line.long 0x0 "SPI2S_SR,SPI/I2S status register" hexmask.long.word 0x0 16.--31. 1. "CTSIZE,CTSIZE" bitfld.long 0x0 15. "RXWNE,RXWNE" "0,1" bitfld.long 0x0 13.--14. "RXPLVL,RXPLVL" "0,1,2,3" bitfld.long 0x0 12. "TXC,TXC" "0,1" bitfld.long 0x0 11. "SUSP,SUSP" "0,1" bitfld.long 0x0 10. "TSERF,TSERF" "0,1" bitfld.long 0x0 9. "MODF,MODF" "0,1" bitfld.long 0x0 8. "TIFRE,TIFRE" "0,1" newline bitfld.long 0x0 7. "CRCE,CRCE" "0,1" bitfld.long 0x0 6. "OVR,OVR" "0,1" bitfld.long 0x0 5. "UDR,UDR" "0,1" bitfld.long 0x0 4. "TXTF,TXTF" "0,1" bitfld.long 0x0 3. "EOT,EOT" "0,1" bitfld.long 0x0 2. "DXP,DXP" "0,1" bitfld.long 0x0 1. "TXP,TXP" "0,1" bitfld.long 0x0 0. "RXP,RXP" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "SPI2S_IFCR,SPI/I2S interrupt/status flags clear register" bitfld.long 0x0 11. "SUSPC,SUSPC" "0,1" bitfld.long 0x0 10. "TSERFC,TSERFC" "0,1" bitfld.long 0x0 9. "MODFC,MODFC" "0,1" bitfld.long 0x0 8. "TIFREC,TIFREC" "0,1" bitfld.long 0x0 7. "CRCEC,CRCEC" "0,1" bitfld.long 0x0 6. "OVRC,OVRC" "0,1" bitfld.long 0x0 5. "UDRC,UDRC" "0,1" bitfld.long 0x0 4. "TXTFC,TXTFC" "0,1" newline bitfld.long 0x0 3. "EOTC,EOTC" "0,1" wgroup.long 0x20++0x3 line.long 0x0 "SPI2S_TXDR,SPI/I2S transmit data register" hexmask.long 0x0 0.--31. 1. "TXDR,TXDR" rgroup.long 0x30++0x3 line.long 0x0 "SPI2S_RXDR,SPI/I2S receive data register" hexmask.long 0x0 0.--31. 1. "RXDR,RXDR" group.long 0x4++0xB line.long 0x0 "SPI_CR2,SPI control register 2" hexmask.long.word 0x0 16.--31. 1. "TSER,TSER" hexmask.long.word 0x0 0.--15. 1. "TSIZE,TSIZE" line.long 0x4 "SPI_CFG1,Content of this register is write protected when SPI is enabled" bitfld.long 0x4 28.--30. "MBR,MBR" "0,1,2,3,4,5,6,7" bitfld.long 0x4 22. "CRCEN,CRCEN" "0,1" hexmask.long.byte 0x4 16.--20. 1. "CRCSIZE,CRCSIZE" bitfld.long 0x4 15. "TXDMAEN,TXDMAEN" "0,1" bitfld.long 0x4 14. "RXDMAEN,RXDMAEN" "0,1" bitfld.long 0x4 11.--12. "UDRDET,UDRDET" "0,1,2,3" bitfld.long 0x4 9.--10. "UDRCFG,UDRCFG" "0,1,2,3" hexmask.long.byte 0x4 5.--8. 1. "FTHLV,FTHLV" newline hexmask.long.byte 0x4 0.--4. 1. "DSIZE,DSIZE" line.long 0x8 "SPI_CFG2,The content of this register is write protected when SPI is enabled or IOLOCK bit is set at SPI2S_CR1 register." bitfld.long 0x8 31. "AFCNTR,AFCNTR" "0,1" bitfld.long 0x8 30. "SSOM,SSOM" "0,1" bitfld.long 0x8 29. "SSOE,SSOE" "0,1" bitfld.long 0x8 28. "SSIOP,SSIOP" "0,1" bitfld.long 0x8 26. "SSM,SSM" "0,1" bitfld.long 0x8 25. "CPOL,CPOL" "0,1" bitfld.long 0x8 24. "CPHA,CPHA" "0,1" bitfld.long 0x8 23. "LSBFRST,LSBFRST" "0,1" newline bitfld.long 0x8 22. "MASTER,MASTER" "0,1" bitfld.long 0x8 19.--21. "SP,SP" "0,1,2,3,4,5,6,7" bitfld.long 0x8 17.--18. "COMM,COMM" "0,1,2,3" bitfld.long 0x8 15. "IOSWP,IOSWP" "0,1" hexmask.long.byte 0x8 4.--7. 1. "MIDI,MIDI" hexmask.long.byte 0x8 0.--3. 1. "MSSI,MSSI" group.long 0x40++0x3 line.long 0x0 "SPI_CRCPOLY,SPI polynomial register" hexmask.long 0x0 0.--31. 1. "CRCPOLY,CRCPOLY" rgroup.long 0x44++0x7 line.long 0x0 "SPI_TXCRC,SPI transmitter CRC register" hexmask.long 0x0 0.--31. 1. "TXCRC,TXCRC" line.long 0x4 "SPI_RXCRC,SPI receiver CRC register" hexmask.long 0x4 0.--31. 1. "RXCRC,RXCRC" group.long 0x4C++0x7 line.long 0x0 "SPI_UDRDR,SPI underrun data register" hexmask.long 0x0 0.--31. 1. "UDRDR,UDRDR" line.long 0x4 "SPI_I2SCFGR,All documented bits in this register must be configured when the I2S is disabled (SPE = 0).These bits are not used in SPI mode except for I2SMOD which needs to be set to 0 in SPI mode." bitfld.long 0x4 25. "MCKOE,MCKOE" "0,1" bitfld.long 0x4 24. "ODD,ODD" "0,1" hexmask.long.byte 0x4 16.--23. 1. "I2SDIV,I2SDIV" bitfld.long 0x4 14. "DATFMT,DATFMT" "0,1" bitfld.long 0x4 13. "WSINV,WSINV" "0,1" bitfld.long 0x4 12. "FIXCH,FIXCH" "0,1" bitfld.long 0x4 11. "CKPOL,CKPOL" "0,1" bitfld.long 0x4 10. "CHLEN,CHLEN" "0,1" newline bitfld.long 0x4 8.--9. "DATLEN,DATLEN" "0,1,2,3" bitfld.long 0x4 7. "PCMSYNC,PCMSYNC" "0,1" bitfld.long 0x4 4.--5. "I2SSTD,I2SSTD" "0,1,2,3" bitfld.long 0x4 1.--3. "I2SCFG,I2SCFG" "0,1,2,3,4,5,6,7" bitfld.long 0x4 0. "I2SMOD,I2SMOD" "0,1" rgroup.long 0x3F0++0xF line.long 0x0 "SPI_I2S_HWCFGR,SPI/I2S hardware configuration register" hexmask.long.byte 0x0 16.--19. 1. "DSCFG,DSCFG" hexmask.long.byte 0x0 12.--15. 1. "I2SCFG,I2SCFG" hexmask.long.byte 0x0 8.--11. 1. "CRCCFG,CRCCFG" hexmask.long.byte 0x0 4.--7. 1. "RXFCFG,RXFCFG" hexmask.long.byte 0x0 0.--3. 1. "TXFCFG,TXFCFG" line.long 0x4 "SPI_VERR,SPI/I2S version register" hexmask.long.byte 0x4 4.--7. 1. "MAJREV,MAJREV" hexmask.long.byte 0x4 0.--3. 1. "MINREV,MINREV" line.long 0x8 "SPI_IPIDR,SPI/I2S identification register" hexmask.long 0x8 0.--31. 1. "ID,ID" line.long 0xC "SPI_SIDR,SPI/I2S size identification register" hexmask.long 0xC 0.--31. 1. "SID,SID" tree.end endif sif (cpuis("STM32MP157*")) tree "SPI2" base ad:0x4000B000 group.long 0x0++0x3 line.long 0x0 "SPI2S_CR1,SPI/I2S control register 1" bitfld.long 0x0 16. "IOLOCK,IOLOCK" "0,1" bitfld.long 0x0 15. "TCRCINI,TCRCINI" "0,1" bitfld.long 0x0 14. "RCRCINI,RCRCINI" "0,1" bitfld.long 0x0 13. "CRC33_17,CRC33_17" "0,1" bitfld.long 0x0 12. "SSI,SSI" "0,1" bitfld.long 0x0 11. "HDDIR,HDDIR" "0,1" bitfld.long 0x0 10. "CSUSP,CSUSP" "0,1" bitfld.long 0x0 9. "CSTART,CSTART" "0,1" newline bitfld.long 0x0 8. "MASRX,MASRX" "0,1" bitfld.long 0x0 0. "SPE,SPE" "0,1" group.long 0x10++0x3 line.long 0x0 "SPI2S_IER,SPI/I2S interrupt enable register" bitfld.long 0x0 10. "TSERFIE,TSERFIE" "0,1" bitfld.long 0x0 9. "MODFIE,MODFIE" "0,1" bitfld.long 0x0 8. "TIFREIE,TIFREIE" "0,1" bitfld.long 0x0 7. "CRCEIE,CRCEIE" "0,1" bitfld.long 0x0 6. "OVRIE,OVRIE" "0,1" bitfld.long 0x0 5. "UDRIE,UDRIE" "0,1" bitfld.long 0x0 4. "TXTFIE,TXTFIE" "0,1" bitfld.long 0x0 3. "EOTIE,EOTIE" "0,1" newline bitfld.long 0x0 2. "DXPIE,DXPIE" "0,1" bitfld.long 0x0 1. "TXPIE,TXPIE" "0,1" bitfld.long 0x0 0. "RXPIE,RXPIE" "0,1" rgroup.long 0x14++0x3 line.long 0x0 "SPI2S_SR,SPI/I2S status register" hexmask.long.word 0x0 16.--31. 1. "CTSIZE,CTSIZE" bitfld.long 0x0 15. "RXWNE,RXWNE" "0,1" bitfld.long 0x0 13.--14. "RXPLVL,RXPLVL" "0,1,2,3" bitfld.long 0x0 12. "TXC,TXC" "0,1" bitfld.long 0x0 11. "SUSP,SUSP" "0,1" bitfld.long 0x0 10. "TSERF,TSERF" "0,1" bitfld.long 0x0 9. "MODF,MODF" "0,1" bitfld.long 0x0 8. "TIFRE,TIFRE" "0,1" newline bitfld.long 0x0 7. "CRCE,CRCE" "0,1" bitfld.long 0x0 6. "OVR,OVR" "0,1" bitfld.long 0x0 5. "UDR,UDR" "0,1" bitfld.long 0x0 4. "TXTF,TXTF" "0,1" bitfld.long 0x0 3. "EOT,EOT" "0,1" bitfld.long 0x0 2. "DXP,DXP" "0,1" bitfld.long 0x0 1. "TXP,TXP" "0,1" bitfld.long 0x0 0. "RXP,RXP" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "SPI2S_IFCR,SPI/I2S interrupt/status flags clear register" bitfld.long 0x0 11. "SUSPC,SUSPC" "0,1" bitfld.long 0x0 10. "TSERFC,TSERFC" "0,1" bitfld.long 0x0 9. "MODFC,MODFC" "0,1" bitfld.long 0x0 8. "TIFREC,TIFREC" "0,1" bitfld.long 0x0 7. "CRCEC,CRCEC" "0,1" bitfld.long 0x0 6. "OVRC,OVRC" "0,1" bitfld.long 0x0 5. "UDRC,UDRC" "0,1" bitfld.long 0x0 4. "TXTFC,TXTFC" "0,1" newline bitfld.long 0x0 3. "EOTC,EOTC" "0,1" wgroup.long 0x20++0x3 line.long 0x0 "SPI2S_TXDR,SPI/I2S transmit data register" hexmask.long 0x0 0.--31. 1. "TXDR,TXDR" rgroup.long 0x30++0x3 line.long 0x0 "SPI2S_RXDR,SPI/I2S receive data register" hexmask.long 0x0 0.--31. 1. "RXDR,RXDR" group.long 0x4++0xB line.long 0x0 "SPI_CR2,SPI control register 2" hexmask.long.word 0x0 16.--31. 1. "TSER,TSER" hexmask.long.word 0x0 0.--15. 1. "TSIZE,TSIZE" line.long 0x4 "SPI_CFG1,Content of this register is write protected when SPI is enabled" bitfld.long 0x4 28.--30. "MBR,MBR" "0,1,2,3,4,5,6,7" bitfld.long 0x4 22. "CRCEN,CRCEN" "0,1" hexmask.long.byte 0x4 16.--20. 1. "CRCSIZE,CRCSIZE" bitfld.long 0x4 15. "TXDMAEN,TXDMAEN" "0,1" bitfld.long 0x4 14. "RXDMAEN,RXDMAEN" "0,1" bitfld.long 0x4 11.--12. "UDRDET,UDRDET" "0,1,2,3" bitfld.long 0x4 9.--10. "UDRCFG,UDRCFG" "0,1,2,3" hexmask.long.byte 0x4 5.--8. 1. "FTHLV,FTHLV" newline hexmask.long.byte 0x4 0.--4. 1. "DSIZE,DSIZE" line.long 0x8 "SPI_CFG2,The content of this register is write protected when SPI is enabled or IOLOCK bit is set at SPI2S_CR1 register." bitfld.long 0x8 31. "AFCNTR,AFCNTR" "0,1" bitfld.long 0x8 30. "SSOM,SSOM" "0,1" bitfld.long 0x8 29. "SSOE,SSOE" "0,1" bitfld.long 0x8 28. "SSIOP,SSIOP" "0,1" bitfld.long 0x8 26. "SSM,SSM" "0,1" bitfld.long 0x8 25. "CPOL,CPOL" "0,1" bitfld.long 0x8 24. "CPHA,CPHA" "0,1" bitfld.long 0x8 23. "LSBFRST,LSBFRST" "0,1" newline bitfld.long 0x8 22. "MASTER,MASTER" "0,1" bitfld.long 0x8 19.--21. "SP,SP" "0,1,2,3,4,5,6,7" bitfld.long 0x8 17.--18. "COMM,COMM" "0,1,2,3" bitfld.long 0x8 15. "IOSWP,IOSWP" "0,1" hexmask.long.byte 0x8 4.--7. 1. "MIDI,MIDI" hexmask.long.byte 0x8 0.--3. 1. "MSSI,MSSI" group.long 0x40++0x3 line.long 0x0 "SPI_CRCPOLY,SPI polynomial register" hexmask.long 0x0 0.--31. 1. "CRCPOLY,CRCPOLY" rgroup.long 0x44++0x7 line.long 0x0 "SPI_TXCRC,SPI transmitter CRC register" hexmask.long 0x0 0.--31. 1. "TXCRC,TXCRC" line.long 0x4 "SPI_RXCRC,SPI receiver CRC register" hexmask.long 0x4 0.--31. 1. "RXCRC,RXCRC" group.long 0x4C++0x7 line.long 0x0 "SPI_UDRDR,SPI underrun data register" hexmask.long 0x0 0.--31. 1. "UDRDR,UDRDR" line.long 0x4 "SPI_I2SCFGR,All documented bits in this register must be configured when the I2S is disabled (SPE = 0).These bits are not used in SPI mode except for I2SMOD which needs to be set to 0 in SPI mode." bitfld.long 0x4 25. "MCKOE,MCKOE" "0,1" bitfld.long 0x4 24. "ODD,ODD" "0,1" hexmask.long.byte 0x4 16.--23. 1. "I2SDIV,I2SDIV" bitfld.long 0x4 14. "DATFMT,DATFMT" "0,1" bitfld.long 0x4 13. "WSINV,WSINV" "0,1" bitfld.long 0x4 12. "FIXCH,FIXCH" "0,1" bitfld.long 0x4 11. "CKPOL,CKPOL" "0,1" bitfld.long 0x4 10. "CHLEN,CHLEN" "0,1" newline bitfld.long 0x4 8.--9. "DATLEN,DATLEN" "0,1,2,3" bitfld.long 0x4 7. "PCMSYNC,PCMSYNC" "0,1" bitfld.long 0x4 4.--5. "I2SSTD,I2SSTD" "0,1,2,3" bitfld.long 0x4 1.--3. "I2SCFG,I2SCFG" "0,1,2,3,4,5,6,7" bitfld.long 0x4 0. "I2SMOD,I2SMOD" "0,1" rgroup.long 0x3F0++0xF line.long 0x0 "SPI_I2S_HWCFGR,SPI/I2S hardware configuration register" hexmask.long.byte 0x0 16.--19. 1. "DSCFG,DSCFG" hexmask.long.byte 0x0 12.--15. 1. "I2SCFG,I2SCFG" hexmask.long.byte 0x0 8.--11. 1. "CRCCFG,CRCCFG" hexmask.long.byte 0x0 4.--7. 1. "RXFCFG,RXFCFG" hexmask.long.byte 0x0 0.--3. 1. "TXFCFG,TXFCFG" line.long 0x4 "SPI_VERR,SPI/I2S version register" hexmask.long.byte 0x4 4.--7. 1. "MAJREV,MAJREV" hexmask.long.byte 0x4 0.--3. 1. "MINREV,MINREV" line.long 0x8 "SPI_IPIDR,SPI/I2S identification register" hexmask.long 0x8 0.--31. 1. "ID,ID" line.long 0xC "SPI_SIDR,SPI/I2S size identification register" hexmask.long 0xC 0.--31. 1. "SID,SID" tree.end tree "SPI3" base ad:0x4000C000 group.long 0x0++0x3 line.long 0x0 "SPI2S_CR1,SPI/I2S control register 1" bitfld.long 0x0 16. "IOLOCK,IOLOCK" "0,1" bitfld.long 0x0 15. "TCRCINI,TCRCINI" "0,1" bitfld.long 0x0 14. "RCRCINI,RCRCINI" "0,1" bitfld.long 0x0 13. "CRC33_17,CRC33_17" "0,1" bitfld.long 0x0 12. "SSI,SSI" "0,1" bitfld.long 0x0 11. "HDDIR,HDDIR" "0,1" bitfld.long 0x0 10. "CSUSP,CSUSP" "0,1" bitfld.long 0x0 9. "CSTART,CSTART" "0,1" newline bitfld.long 0x0 8. "MASRX,MASRX" "0,1" bitfld.long 0x0 0. "SPE,SPE" "0,1" group.long 0x10++0x3 line.long 0x0 "SPI2S_IER,SPI/I2S interrupt enable register" bitfld.long 0x0 10. "TSERFIE,TSERFIE" "0,1" bitfld.long 0x0 9. "MODFIE,MODFIE" "0,1" bitfld.long 0x0 8. "TIFREIE,TIFREIE" "0,1" bitfld.long 0x0 7. "CRCEIE,CRCEIE" "0,1" bitfld.long 0x0 6. "OVRIE,OVRIE" "0,1" bitfld.long 0x0 5. "UDRIE,UDRIE" "0,1" bitfld.long 0x0 4. "TXTFIE,TXTFIE" "0,1" bitfld.long 0x0 3. "EOTIE,EOTIE" "0,1" newline bitfld.long 0x0 2. "DXPIE,DXPIE" "0,1" bitfld.long 0x0 1. "TXPIE,TXPIE" "0,1" bitfld.long 0x0 0. "RXPIE,RXPIE" "0,1" rgroup.long 0x14++0x3 line.long 0x0 "SPI2S_SR,SPI/I2S status register" hexmask.long.word 0x0 16.--31. 1. "CTSIZE,CTSIZE" bitfld.long 0x0 15. "RXWNE,RXWNE" "0,1" bitfld.long 0x0 13.--14. "RXPLVL,RXPLVL" "0,1,2,3" bitfld.long 0x0 12. "TXC,TXC" "0,1" bitfld.long 0x0 11. "SUSP,SUSP" "0,1" bitfld.long 0x0 10. "TSERF,TSERF" "0,1" bitfld.long 0x0 9. "MODF,MODF" "0,1" bitfld.long 0x0 8. "TIFRE,TIFRE" "0,1" newline bitfld.long 0x0 7. "CRCE,CRCE" "0,1" bitfld.long 0x0 6. "OVR,OVR" "0,1" bitfld.long 0x0 5. "UDR,UDR" "0,1" bitfld.long 0x0 4. "TXTF,TXTF" "0,1" bitfld.long 0x0 3. "EOT,EOT" "0,1" bitfld.long 0x0 2. "DXP,DXP" "0,1" bitfld.long 0x0 1. "TXP,TXP" "0,1" bitfld.long 0x0 0. "RXP,RXP" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "SPI2S_IFCR,SPI/I2S interrupt/status flags clear register" bitfld.long 0x0 11. "SUSPC,SUSPC" "0,1" bitfld.long 0x0 10. "TSERFC,TSERFC" "0,1" bitfld.long 0x0 9. "MODFC,MODFC" "0,1" bitfld.long 0x0 8. "TIFREC,TIFREC" "0,1" bitfld.long 0x0 7. "CRCEC,CRCEC" "0,1" bitfld.long 0x0 6. "OVRC,OVRC" "0,1" bitfld.long 0x0 5. "UDRC,UDRC" "0,1" bitfld.long 0x0 4. "TXTFC,TXTFC" "0,1" newline bitfld.long 0x0 3. "EOTC,EOTC" "0,1" wgroup.long 0x20++0x3 line.long 0x0 "SPI2S_TXDR,SPI/I2S transmit data register" hexmask.long 0x0 0.--31. 1. "TXDR,TXDR" rgroup.long 0x30++0x3 line.long 0x0 "SPI2S_RXDR,SPI/I2S receive data register" hexmask.long 0x0 0.--31. 1. "RXDR,RXDR" group.long 0x4++0xB line.long 0x0 "SPI_CR2,SPI control register 2" hexmask.long.word 0x0 16.--31. 1. "TSER,TSER" hexmask.long.word 0x0 0.--15. 1. "TSIZE,TSIZE" line.long 0x4 "SPI_CFG1,Content of this register is write protected when SPI is enabled" bitfld.long 0x4 28.--30. "MBR,MBR" "0,1,2,3,4,5,6,7" bitfld.long 0x4 22. "CRCEN,CRCEN" "0,1" hexmask.long.byte 0x4 16.--20. 1. "CRCSIZE,CRCSIZE" bitfld.long 0x4 15. "TXDMAEN,TXDMAEN" "0,1" bitfld.long 0x4 14. "RXDMAEN,RXDMAEN" "0,1" bitfld.long 0x4 11.--12. "UDRDET,UDRDET" "0,1,2,3" bitfld.long 0x4 9.--10. "UDRCFG,UDRCFG" "0,1,2,3" hexmask.long.byte 0x4 5.--8. 1. "FTHLV,FTHLV" newline hexmask.long.byte 0x4 0.--4. 1. "DSIZE,DSIZE" line.long 0x8 "SPI_CFG2,The content of this register is write protected when SPI is enabled or IOLOCK bit is set at SPI2S_CR1 register." bitfld.long 0x8 31. "AFCNTR,AFCNTR" "0,1" bitfld.long 0x8 30. "SSOM,SSOM" "0,1" bitfld.long 0x8 29. "SSOE,SSOE" "0,1" bitfld.long 0x8 28. "SSIOP,SSIOP" "0,1" bitfld.long 0x8 26. "SSM,SSM" "0,1" bitfld.long 0x8 25. "CPOL,CPOL" "0,1" bitfld.long 0x8 24. "CPHA,CPHA" "0,1" bitfld.long 0x8 23. "LSBFRST,LSBFRST" "0,1" newline bitfld.long 0x8 22. "MASTER,MASTER" "0,1" bitfld.long 0x8 19.--21. "SP,SP" "0,1,2,3,4,5,6,7" bitfld.long 0x8 17.--18. "COMM,COMM" "0,1,2,3" bitfld.long 0x8 15. "IOSWP,IOSWP" "0,1" hexmask.long.byte 0x8 4.--7. 1. "MIDI,MIDI" hexmask.long.byte 0x8 0.--3. 1. "MSSI,MSSI" group.long 0x40++0x3 line.long 0x0 "SPI_CRCPOLY,SPI polynomial register" hexmask.long 0x0 0.--31. 1. "CRCPOLY,CRCPOLY" rgroup.long 0x44++0x7 line.long 0x0 "SPI_TXCRC,SPI transmitter CRC register" hexmask.long 0x0 0.--31. 1. "TXCRC,TXCRC" line.long 0x4 "SPI_RXCRC,SPI receiver CRC register" hexmask.long 0x4 0.--31. 1. "RXCRC,RXCRC" group.long 0x4C++0x7 line.long 0x0 "SPI_UDRDR,SPI underrun data register" hexmask.long 0x0 0.--31. 1. "UDRDR,UDRDR" line.long 0x4 "SPI_I2SCFGR,All documented bits in this register must be configured when the I2S is disabled (SPE = 0).These bits are not used in SPI mode except for I2SMOD which needs to be set to 0 in SPI mode." bitfld.long 0x4 25. "MCKOE,MCKOE" "0,1" bitfld.long 0x4 24. "ODD,ODD" "0,1" hexmask.long.byte 0x4 16.--23. 1. "I2SDIV,I2SDIV" bitfld.long 0x4 14. "DATFMT,DATFMT" "0,1" bitfld.long 0x4 13. "WSINV,WSINV" "0,1" bitfld.long 0x4 12. "FIXCH,FIXCH" "0,1" bitfld.long 0x4 11. "CKPOL,CKPOL" "0,1" bitfld.long 0x4 10. "CHLEN,CHLEN" "0,1" newline bitfld.long 0x4 8.--9. "DATLEN,DATLEN" "0,1,2,3" bitfld.long 0x4 7. "PCMSYNC,PCMSYNC" "0,1" bitfld.long 0x4 4.--5. "I2SSTD,I2SSTD" "0,1,2,3" bitfld.long 0x4 1.--3. "I2SCFG,I2SCFG" "0,1,2,3,4,5,6,7" bitfld.long 0x4 0. "I2SMOD,I2SMOD" "0,1" rgroup.long 0x3F0++0xF line.long 0x0 "SPI_I2S_HWCFGR,SPI/I2S hardware configuration register" hexmask.long.byte 0x0 16.--19. 1. "DSCFG,DSCFG" hexmask.long.byte 0x0 12.--15. 1. "I2SCFG,I2SCFG" hexmask.long.byte 0x0 8.--11. 1. "CRCCFG,CRCCFG" hexmask.long.byte 0x0 4.--7. 1. "RXFCFG,RXFCFG" hexmask.long.byte 0x0 0.--3. 1. "TXFCFG,TXFCFG" line.long 0x4 "SPI_VERR,SPI/I2S version register" hexmask.long.byte 0x4 4.--7. 1. "MAJREV,MAJREV" hexmask.long.byte 0x4 0.--3. 1. "MINREV,MINREV" line.long 0x8 "SPI_IPIDR,SPI/I2S identification register" hexmask.long 0x8 0.--31. 1. "ID,ID" line.long 0xC "SPI_SIDR,SPI/I2S size identification register" hexmask.long 0xC 0.--31. 1. "SID,SID" tree.end tree "SPI4" base ad:0x44005000 group.long 0x0++0x3 line.long 0x0 "SPI2S_CR1,SPI/I2S control register 1" bitfld.long 0x0 16. "IOLOCK,IOLOCK" "0,1" bitfld.long 0x0 15. "TCRCINI,TCRCINI" "0,1" bitfld.long 0x0 14. "RCRCINI,RCRCINI" "0,1" bitfld.long 0x0 13. "CRC33_17,CRC33_17" "0,1" bitfld.long 0x0 12. "SSI,SSI" "0,1" bitfld.long 0x0 11. "HDDIR,HDDIR" "0,1" bitfld.long 0x0 10. "CSUSP,CSUSP" "0,1" bitfld.long 0x0 9. "CSTART,CSTART" "0,1" newline bitfld.long 0x0 8. "MASRX,MASRX" "0,1" bitfld.long 0x0 0. "SPE,SPE" "0,1" group.long 0x10++0x3 line.long 0x0 "SPI2S_IER,SPI/I2S interrupt enable register" bitfld.long 0x0 10. "TSERFIE,TSERFIE" "0,1" bitfld.long 0x0 9. "MODFIE,MODFIE" "0,1" bitfld.long 0x0 8. "TIFREIE,TIFREIE" "0,1" bitfld.long 0x0 7. "CRCEIE,CRCEIE" "0,1" bitfld.long 0x0 6. "OVRIE,OVRIE" "0,1" bitfld.long 0x0 5. "UDRIE,UDRIE" "0,1" bitfld.long 0x0 4. "TXTFIE,TXTFIE" "0,1" bitfld.long 0x0 3. "EOTIE,EOTIE" "0,1" newline bitfld.long 0x0 2. "DXPIE,DXPIE" "0,1" bitfld.long 0x0 1. "TXPIE,TXPIE" "0,1" bitfld.long 0x0 0. "RXPIE,RXPIE" "0,1" rgroup.long 0x14++0x3 line.long 0x0 "SPI2S_SR,SPI/I2S status register" hexmask.long.word 0x0 16.--31. 1. "CTSIZE,CTSIZE" bitfld.long 0x0 15. "RXWNE,RXWNE" "0,1" bitfld.long 0x0 13.--14. "RXPLVL,RXPLVL" "0,1,2,3" bitfld.long 0x0 12. "TXC,TXC" "0,1" bitfld.long 0x0 11. "SUSP,SUSP" "0,1" bitfld.long 0x0 10. "TSERF,TSERF" "0,1" bitfld.long 0x0 9. "MODF,MODF" "0,1" bitfld.long 0x0 8. "TIFRE,TIFRE" "0,1" newline bitfld.long 0x0 7. "CRCE,CRCE" "0,1" bitfld.long 0x0 6. "OVR,OVR" "0,1" bitfld.long 0x0 5. "UDR,UDR" "0,1" bitfld.long 0x0 4. "TXTF,TXTF" "0,1" bitfld.long 0x0 3. "EOT,EOT" "0,1" bitfld.long 0x0 2. "DXP,DXP" "0,1" bitfld.long 0x0 1. "TXP,TXP" "0,1" bitfld.long 0x0 0. "RXP,RXP" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "SPI2S_IFCR,SPI/I2S interrupt/status flags clear register" bitfld.long 0x0 11. "SUSPC,SUSPC" "0,1" bitfld.long 0x0 10. "TSERFC,TSERFC" "0,1" bitfld.long 0x0 9. "MODFC,MODFC" "0,1" bitfld.long 0x0 8. "TIFREC,TIFREC" "0,1" bitfld.long 0x0 7. "CRCEC,CRCEC" "0,1" bitfld.long 0x0 6. "OVRC,OVRC" "0,1" bitfld.long 0x0 5. "UDRC,UDRC" "0,1" bitfld.long 0x0 4. "TXTFC,TXTFC" "0,1" newline bitfld.long 0x0 3. "EOTC,EOTC" "0,1" wgroup.long 0x20++0x3 line.long 0x0 "SPI2S_TXDR,SPI/I2S transmit data register" hexmask.long 0x0 0.--31. 1. "TXDR,TXDR" rgroup.long 0x30++0x3 line.long 0x0 "SPI2S_RXDR,SPI/I2S receive data register" hexmask.long 0x0 0.--31. 1. "RXDR,RXDR" group.long 0x4++0xB line.long 0x0 "SPI_CR2,SPI control register 2" hexmask.long.word 0x0 16.--31. 1. "TSER,TSER" hexmask.long.word 0x0 0.--15. 1. "TSIZE,TSIZE" line.long 0x4 "SPI_CFG1,Content of this register is write protected when SPI is enabled" bitfld.long 0x4 28.--30. "MBR,MBR" "0,1,2,3,4,5,6,7" bitfld.long 0x4 22. "CRCEN,CRCEN" "0,1" hexmask.long.byte 0x4 16.--20. 1. "CRCSIZE,CRCSIZE" bitfld.long 0x4 15. "TXDMAEN,TXDMAEN" "0,1" bitfld.long 0x4 14. "RXDMAEN,RXDMAEN" "0,1" bitfld.long 0x4 11.--12. "UDRDET,UDRDET" "0,1,2,3" bitfld.long 0x4 9.--10. "UDRCFG,UDRCFG" "0,1,2,3" hexmask.long.byte 0x4 5.--8. 1. "FTHLV,FTHLV" newline hexmask.long.byte 0x4 0.--4. 1. "DSIZE,DSIZE" line.long 0x8 "SPI_CFG2,The content of this register is write protected when SPI is enabled or IOLOCK bit is set at SPI2S_CR1 register." bitfld.long 0x8 31. "AFCNTR,AFCNTR" "0,1" bitfld.long 0x8 30. "SSOM,SSOM" "0,1" bitfld.long 0x8 29. "SSOE,SSOE" "0,1" bitfld.long 0x8 28. "SSIOP,SSIOP" "0,1" bitfld.long 0x8 26. "SSM,SSM" "0,1" bitfld.long 0x8 25. "CPOL,CPOL" "0,1" bitfld.long 0x8 24. "CPHA,CPHA" "0,1" bitfld.long 0x8 23. "LSBFRST,LSBFRST" "0,1" newline bitfld.long 0x8 22. "MASTER,MASTER" "0,1" bitfld.long 0x8 19.--21. "SP,SP" "0,1,2,3,4,5,6,7" bitfld.long 0x8 17.--18. "COMM,COMM" "0,1,2,3" bitfld.long 0x8 15. "IOSWP,IOSWP" "0,1" hexmask.long.byte 0x8 4.--7. 1. "MIDI,MIDI" hexmask.long.byte 0x8 0.--3. 1. "MSSI,MSSI" group.long 0x40++0x3 line.long 0x0 "SPI_CRCPOLY,SPI polynomial register" hexmask.long 0x0 0.--31. 1. "CRCPOLY,CRCPOLY" rgroup.long 0x44++0x7 line.long 0x0 "SPI_TXCRC,SPI transmitter CRC register" hexmask.long 0x0 0.--31. 1. "TXCRC,TXCRC" line.long 0x4 "SPI_RXCRC,SPI receiver CRC register" hexmask.long 0x4 0.--31. 1. "RXCRC,RXCRC" group.long 0x4C++0x7 line.long 0x0 "SPI_UDRDR,SPI underrun data register" hexmask.long 0x0 0.--31. 1. "UDRDR,UDRDR" line.long 0x4 "SPI_I2SCFGR,All documented bits in this register must be configured when the I2S is disabled (SPE = 0).These bits are not used in SPI mode except for I2SMOD which needs to be set to 0 in SPI mode." bitfld.long 0x4 25. "MCKOE,MCKOE" "0,1" bitfld.long 0x4 24. "ODD,ODD" "0,1" hexmask.long.byte 0x4 16.--23. 1. "I2SDIV,I2SDIV" bitfld.long 0x4 14. "DATFMT,DATFMT" "0,1" bitfld.long 0x4 13. "WSINV,WSINV" "0,1" bitfld.long 0x4 12. "FIXCH,FIXCH" "0,1" bitfld.long 0x4 11. "CKPOL,CKPOL" "0,1" bitfld.long 0x4 10. "CHLEN,CHLEN" "0,1" newline bitfld.long 0x4 8.--9. "DATLEN,DATLEN" "0,1,2,3" bitfld.long 0x4 7. "PCMSYNC,PCMSYNC" "0,1" bitfld.long 0x4 4.--5. "I2SSTD,I2SSTD" "0,1,2,3" bitfld.long 0x4 1.--3. "I2SCFG,I2SCFG" "0,1,2,3,4,5,6,7" bitfld.long 0x4 0. "I2SMOD,I2SMOD" "0,1" rgroup.long 0x3F0++0xF line.long 0x0 "SPI_I2S_HWCFGR,SPI/I2S hardware configuration register" hexmask.long.byte 0x0 16.--19. 1. "DSCFG,DSCFG" hexmask.long.byte 0x0 12.--15. 1. "I2SCFG,I2SCFG" hexmask.long.byte 0x0 8.--11. 1. "CRCCFG,CRCCFG" hexmask.long.byte 0x0 4.--7. 1. "RXFCFG,RXFCFG" hexmask.long.byte 0x0 0.--3. 1. "TXFCFG,TXFCFG" line.long 0x4 "SPI_VERR,SPI/I2S version register" hexmask.long.byte 0x4 4.--7. 1. "MAJREV,MAJREV" hexmask.long.byte 0x4 0.--3. 1. "MINREV,MINREV" line.long 0x8 "SPI_IPIDR,SPI/I2S identification register" hexmask.long 0x8 0.--31. 1. "ID,ID" line.long 0xC "SPI_SIDR,SPI/I2S size identification register" hexmask.long 0xC 0.--31. 1. "SID,SID" tree.end tree "SPI5" base ad:0x44009000 group.long 0x0++0x3 line.long 0x0 "SPI2S_CR1,SPI/I2S control register 1" bitfld.long 0x0 16. "IOLOCK,IOLOCK" "0,1" bitfld.long 0x0 15. "TCRCINI,TCRCINI" "0,1" bitfld.long 0x0 14. "RCRCINI,RCRCINI" "0,1" bitfld.long 0x0 13. "CRC33_17,CRC33_17" "0,1" bitfld.long 0x0 12. "SSI,SSI" "0,1" bitfld.long 0x0 11. "HDDIR,HDDIR" "0,1" bitfld.long 0x0 10. "CSUSP,CSUSP" "0,1" bitfld.long 0x0 9. "CSTART,CSTART" "0,1" newline bitfld.long 0x0 8. "MASRX,MASRX" "0,1" bitfld.long 0x0 0. "SPE,SPE" "0,1" group.long 0x10++0x3 line.long 0x0 "SPI2S_IER,SPI/I2S interrupt enable register" bitfld.long 0x0 10. "TSERFIE,TSERFIE" "0,1" bitfld.long 0x0 9. "MODFIE,MODFIE" "0,1" bitfld.long 0x0 8. "TIFREIE,TIFREIE" "0,1" bitfld.long 0x0 7. "CRCEIE,CRCEIE" "0,1" bitfld.long 0x0 6. "OVRIE,OVRIE" "0,1" bitfld.long 0x0 5. "UDRIE,UDRIE" "0,1" bitfld.long 0x0 4. "TXTFIE,TXTFIE" "0,1" bitfld.long 0x0 3. "EOTIE,EOTIE" "0,1" newline bitfld.long 0x0 2. "DXPIE,DXPIE" "0,1" bitfld.long 0x0 1. "TXPIE,TXPIE" "0,1" bitfld.long 0x0 0. "RXPIE,RXPIE" "0,1" rgroup.long 0x14++0x3 line.long 0x0 "SPI2S_SR,SPI/I2S status register" hexmask.long.word 0x0 16.--31. 1. "CTSIZE,CTSIZE" bitfld.long 0x0 15. "RXWNE,RXWNE" "0,1" bitfld.long 0x0 13.--14. "RXPLVL,RXPLVL" "0,1,2,3" bitfld.long 0x0 12. "TXC,TXC" "0,1" bitfld.long 0x0 11. "SUSP,SUSP" "0,1" bitfld.long 0x0 10. "TSERF,TSERF" "0,1" bitfld.long 0x0 9. "MODF,MODF" "0,1" bitfld.long 0x0 8. "TIFRE,TIFRE" "0,1" newline bitfld.long 0x0 7. "CRCE,CRCE" "0,1" bitfld.long 0x0 6. "OVR,OVR" "0,1" bitfld.long 0x0 5. "UDR,UDR" "0,1" bitfld.long 0x0 4. "TXTF,TXTF" "0,1" bitfld.long 0x0 3. "EOT,EOT" "0,1" bitfld.long 0x0 2. "DXP,DXP" "0,1" bitfld.long 0x0 1. "TXP,TXP" "0,1" bitfld.long 0x0 0. "RXP,RXP" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "SPI2S_IFCR,SPI/I2S interrupt/status flags clear register" bitfld.long 0x0 11. "SUSPC,SUSPC" "0,1" bitfld.long 0x0 10. "TSERFC,TSERFC" "0,1" bitfld.long 0x0 9. "MODFC,MODFC" "0,1" bitfld.long 0x0 8. "TIFREC,TIFREC" "0,1" bitfld.long 0x0 7. "CRCEC,CRCEC" "0,1" bitfld.long 0x0 6. "OVRC,OVRC" "0,1" bitfld.long 0x0 5. "UDRC,UDRC" "0,1" bitfld.long 0x0 4. "TXTFC,TXTFC" "0,1" newline bitfld.long 0x0 3. "EOTC,EOTC" "0,1" wgroup.long 0x20++0x3 line.long 0x0 "SPI2S_TXDR,SPI/I2S transmit data register" hexmask.long 0x0 0.--31. 1. "TXDR,TXDR" rgroup.long 0x30++0x3 line.long 0x0 "SPI2S_RXDR,SPI/I2S receive data register" hexmask.long 0x0 0.--31. 1. "RXDR,RXDR" group.long 0x4++0xB line.long 0x0 "SPI_CR2,SPI control register 2" hexmask.long.word 0x0 16.--31. 1. "TSER,TSER" hexmask.long.word 0x0 0.--15. 1. "TSIZE,TSIZE" line.long 0x4 "SPI_CFG1,Content of this register is write protected when SPI is enabled" bitfld.long 0x4 28.--30. "MBR,MBR" "0,1,2,3,4,5,6,7" bitfld.long 0x4 22. "CRCEN,CRCEN" "0,1" hexmask.long.byte 0x4 16.--20. 1. "CRCSIZE,CRCSIZE" bitfld.long 0x4 15. "TXDMAEN,TXDMAEN" "0,1" bitfld.long 0x4 14. "RXDMAEN,RXDMAEN" "0,1" bitfld.long 0x4 11.--12. "UDRDET,UDRDET" "0,1,2,3" bitfld.long 0x4 9.--10. "UDRCFG,UDRCFG" "0,1,2,3" hexmask.long.byte 0x4 5.--8. 1. "FTHLV,FTHLV" newline hexmask.long.byte 0x4 0.--4. 1. "DSIZE,DSIZE" line.long 0x8 "SPI_CFG2,The content of this register is write protected when SPI is enabled or IOLOCK bit is set at SPI2S_CR1 register." bitfld.long 0x8 31. "AFCNTR,AFCNTR" "0,1" bitfld.long 0x8 30. "SSOM,SSOM" "0,1" bitfld.long 0x8 29. "SSOE,SSOE" "0,1" bitfld.long 0x8 28. "SSIOP,SSIOP" "0,1" bitfld.long 0x8 26. "SSM,SSM" "0,1" bitfld.long 0x8 25. "CPOL,CPOL" "0,1" bitfld.long 0x8 24. "CPHA,CPHA" "0,1" bitfld.long 0x8 23. "LSBFRST,LSBFRST" "0,1" newline bitfld.long 0x8 22. "MASTER,MASTER" "0,1" bitfld.long 0x8 19.--21. "SP,SP" "0,1,2,3,4,5,6,7" bitfld.long 0x8 17.--18. "COMM,COMM" "0,1,2,3" bitfld.long 0x8 15. "IOSWP,IOSWP" "0,1" hexmask.long.byte 0x8 4.--7. 1. "MIDI,MIDI" hexmask.long.byte 0x8 0.--3. 1. "MSSI,MSSI" group.long 0x40++0x3 line.long 0x0 "SPI_CRCPOLY,SPI polynomial register" hexmask.long 0x0 0.--31. 1. "CRCPOLY,CRCPOLY" rgroup.long 0x44++0x7 line.long 0x0 "SPI_TXCRC,SPI transmitter CRC register" hexmask.long 0x0 0.--31. 1. "TXCRC,TXCRC" line.long 0x4 "SPI_RXCRC,SPI receiver CRC register" hexmask.long 0x4 0.--31. 1. "RXCRC,RXCRC" group.long 0x4C++0x7 line.long 0x0 "SPI_UDRDR,SPI underrun data register" hexmask.long 0x0 0.--31. 1. "UDRDR,UDRDR" line.long 0x4 "SPI_I2SCFGR,All documented bits in this register must be configured when the I2S is disabled (SPE = 0).These bits are not used in SPI mode except for I2SMOD which needs to be set to 0 in SPI mode." bitfld.long 0x4 25. "MCKOE,MCKOE" "0,1" bitfld.long 0x4 24. "ODD,ODD" "0,1" hexmask.long.byte 0x4 16.--23. 1. "I2SDIV,I2SDIV" bitfld.long 0x4 14. "DATFMT,DATFMT" "0,1" bitfld.long 0x4 13. "WSINV,WSINV" "0,1" bitfld.long 0x4 12. "FIXCH,FIXCH" "0,1" bitfld.long 0x4 11. "CKPOL,CKPOL" "0,1" bitfld.long 0x4 10. "CHLEN,CHLEN" "0,1" newline bitfld.long 0x4 8.--9. "DATLEN,DATLEN" "0,1,2,3" bitfld.long 0x4 7. "PCMSYNC,PCMSYNC" "0,1" bitfld.long 0x4 4.--5. "I2SSTD,I2SSTD" "0,1,2,3" bitfld.long 0x4 1.--3. "I2SCFG,I2SCFG" "0,1,2,3,4,5,6,7" bitfld.long 0x4 0. "I2SMOD,I2SMOD" "0,1" rgroup.long 0x3F0++0xF line.long 0x0 "SPI_I2S_HWCFGR,SPI/I2S hardware configuration register" hexmask.long.byte 0x0 16.--19. 1. "DSCFG,DSCFG" hexmask.long.byte 0x0 12.--15. 1. "I2SCFG,I2SCFG" hexmask.long.byte 0x0 8.--11. 1. "CRCCFG,CRCCFG" hexmask.long.byte 0x0 4.--7. 1. "RXFCFG,RXFCFG" hexmask.long.byte 0x0 0.--3. 1. "TXFCFG,TXFCFG" line.long 0x4 "SPI_VERR,SPI/I2S version register" hexmask.long.byte 0x4 4.--7. 1. "MAJREV,MAJREV" hexmask.long.byte 0x4 0.--3. 1. "MINREV,MINREV" line.long 0x8 "SPI_IPIDR,SPI/I2S identification register" hexmask.long 0x8 0.--31. 1. "ID,ID" line.long 0xC "SPI_SIDR,SPI/I2S size identification register" hexmask.long 0xC 0.--31. 1. "SID,SID" tree.end tree "SPI6" base ad:0x5C001000 group.long 0x0++0x3 line.long 0x0 "SPI2S_CR1,SPI/I2S control register 1" bitfld.long 0x0 16. "IOLOCK,IOLOCK" "0,1" bitfld.long 0x0 15. "TCRCINI,TCRCINI" "0,1" bitfld.long 0x0 14. "RCRCINI,RCRCINI" "0,1" bitfld.long 0x0 13. "CRC33_17,CRC33_17" "0,1" bitfld.long 0x0 12. "SSI,SSI" "0,1" bitfld.long 0x0 11. "HDDIR,HDDIR" "0,1" bitfld.long 0x0 10. "CSUSP,CSUSP" "0,1" bitfld.long 0x0 9. "CSTART,CSTART" "0,1" newline bitfld.long 0x0 8. "MASRX,MASRX" "0,1" bitfld.long 0x0 0. "SPE,SPE" "0,1" group.long 0x10++0x3 line.long 0x0 "SPI2S_IER,SPI/I2S interrupt enable register" bitfld.long 0x0 10. "TSERFIE,TSERFIE" "0,1" bitfld.long 0x0 9. "MODFIE,MODFIE" "0,1" bitfld.long 0x0 8. "TIFREIE,TIFREIE" "0,1" bitfld.long 0x0 7. "CRCEIE,CRCEIE" "0,1" bitfld.long 0x0 6. "OVRIE,OVRIE" "0,1" bitfld.long 0x0 5. "UDRIE,UDRIE" "0,1" bitfld.long 0x0 4. "TXTFIE,TXTFIE" "0,1" bitfld.long 0x0 3. "EOTIE,EOTIE" "0,1" newline bitfld.long 0x0 2. "DXPIE,DXPIE" "0,1" bitfld.long 0x0 1. "TXPIE,TXPIE" "0,1" bitfld.long 0x0 0. "RXPIE,RXPIE" "0,1" rgroup.long 0x14++0x3 line.long 0x0 "SPI2S_SR,SPI/I2S status register" hexmask.long.word 0x0 16.--31. 1. "CTSIZE,CTSIZE" bitfld.long 0x0 15. "RXWNE,RXWNE" "0,1" bitfld.long 0x0 13.--14. "RXPLVL,RXPLVL" "0,1,2,3" bitfld.long 0x0 12. "TXC,TXC" "0,1" bitfld.long 0x0 11. "SUSP,SUSP" "0,1" bitfld.long 0x0 10. "TSERF,TSERF" "0,1" bitfld.long 0x0 9. "MODF,MODF" "0,1" bitfld.long 0x0 8. "TIFRE,TIFRE" "0,1" newline bitfld.long 0x0 7. "CRCE,CRCE" "0,1" bitfld.long 0x0 6. "OVR,OVR" "0,1" bitfld.long 0x0 5. "UDR,UDR" "0,1" bitfld.long 0x0 4. "TXTF,TXTF" "0,1" bitfld.long 0x0 3. "EOT,EOT" "0,1" bitfld.long 0x0 2. "DXP,DXP" "0,1" bitfld.long 0x0 1. "TXP,TXP" "0,1" bitfld.long 0x0 0. "RXP,RXP" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "SPI2S_IFCR,SPI/I2S interrupt/status flags clear register" bitfld.long 0x0 11. "SUSPC,SUSPC" "0,1" bitfld.long 0x0 10. "TSERFC,TSERFC" "0,1" bitfld.long 0x0 9. "MODFC,MODFC" "0,1" bitfld.long 0x0 8. "TIFREC,TIFREC" "0,1" bitfld.long 0x0 7. "CRCEC,CRCEC" "0,1" bitfld.long 0x0 6. "OVRC,OVRC" "0,1" bitfld.long 0x0 5. "UDRC,UDRC" "0,1" bitfld.long 0x0 4. "TXTFC,TXTFC" "0,1" newline bitfld.long 0x0 3. "EOTC,EOTC" "0,1" wgroup.long 0x20++0x3 line.long 0x0 "SPI2S_TXDR,SPI/I2S transmit data register" hexmask.long 0x0 0.--31. 1. "TXDR,TXDR" rgroup.long 0x30++0x3 line.long 0x0 "SPI2S_RXDR,SPI/I2S receive data register" hexmask.long 0x0 0.--31. 1. "RXDR,RXDR" group.long 0x4++0xB line.long 0x0 "SPI_CR2,SPI control register 2" hexmask.long.word 0x0 16.--31. 1. "TSER,TSER" hexmask.long.word 0x0 0.--15. 1. "TSIZE,TSIZE" line.long 0x4 "SPI_CFG1,Content of this register is write protected when SPI is enabled" bitfld.long 0x4 28.--30. "MBR,MBR" "0,1,2,3,4,5,6,7" bitfld.long 0x4 22. "CRCEN,CRCEN" "0,1" hexmask.long.byte 0x4 16.--20. 1. "CRCSIZE,CRCSIZE" bitfld.long 0x4 15. "TXDMAEN,TXDMAEN" "0,1" bitfld.long 0x4 14. "RXDMAEN,RXDMAEN" "0,1" bitfld.long 0x4 11.--12. "UDRDET,UDRDET" "0,1,2,3" bitfld.long 0x4 9.--10. "UDRCFG,UDRCFG" "0,1,2,3" hexmask.long.byte 0x4 5.--8. 1. "FTHLV,FTHLV" newline hexmask.long.byte 0x4 0.--4. 1. "DSIZE,DSIZE" line.long 0x8 "SPI_CFG2,The content of this register is write protected when SPI is enabled or IOLOCK bit is set at SPI2S_CR1 register." bitfld.long 0x8 31. "AFCNTR,AFCNTR" "0,1" bitfld.long 0x8 30. "SSOM,SSOM" "0,1" bitfld.long 0x8 29. "SSOE,SSOE" "0,1" bitfld.long 0x8 28. "SSIOP,SSIOP" "0,1" bitfld.long 0x8 26. "SSM,SSM" "0,1" bitfld.long 0x8 25. "CPOL,CPOL" "0,1" bitfld.long 0x8 24. "CPHA,CPHA" "0,1" bitfld.long 0x8 23. "LSBFRST,LSBFRST" "0,1" newline bitfld.long 0x8 22. "MASTER,MASTER" "0,1" bitfld.long 0x8 19.--21. "SP,SP" "0,1,2,3,4,5,6,7" bitfld.long 0x8 17.--18. "COMM,COMM" "0,1,2,3" bitfld.long 0x8 15. "IOSWP,IOSWP" "0,1" hexmask.long.byte 0x8 4.--7. 1. "MIDI,MIDI" hexmask.long.byte 0x8 0.--3. 1. "MSSI,MSSI" group.long 0x40++0x3 line.long 0x0 "SPI_CRCPOLY,SPI polynomial register" hexmask.long 0x0 0.--31. 1. "CRCPOLY,CRCPOLY" rgroup.long 0x44++0x7 line.long 0x0 "SPI_TXCRC,SPI transmitter CRC register" hexmask.long 0x0 0.--31. 1. "TXCRC,TXCRC" line.long 0x4 "SPI_RXCRC,SPI receiver CRC register" hexmask.long 0x4 0.--31. 1. "RXCRC,RXCRC" group.long 0x4C++0x7 line.long 0x0 "SPI_UDRDR,SPI underrun data register" hexmask.long 0x0 0.--31. 1. "UDRDR,UDRDR" line.long 0x4 "SPI_I2SCFGR,All documented bits in this register must be configured when the I2S is disabled (SPE = 0).These bits are not used in SPI mode except for I2SMOD which needs to be set to 0 in SPI mode." bitfld.long 0x4 25. "MCKOE,MCKOE" "0,1" bitfld.long 0x4 24. "ODD,ODD" "0,1" hexmask.long.byte 0x4 16.--23. 1. "I2SDIV,I2SDIV" bitfld.long 0x4 14. "DATFMT,DATFMT" "0,1" bitfld.long 0x4 13. "WSINV,WSINV" "0,1" bitfld.long 0x4 12. "FIXCH,FIXCH" "0,1" bitfld.long 0x4 11. "CKPOL,CKPOL" "0,1" bitfld.long 0x4 10. "CHLEN,CHLEN" "0,1" newline bitfld.long 0x4 8.--9. "DATLEN,DATLEN" "0,1,2,3" bitfld.long 0x4 7. "PCMSYNC,PCMSYNC" "0,1" bitfld.long 0x4 4.--5. "I2SSTD,I2SSTD" "0,1,2,3" bitfld.long 0x4 1.--3. "I2SCFG,I2SCFG" "0,1,2,3,4,5,6,7" bitfld.long 0x4 0. "I2SMOD,I2SMOD" "0,1" rgroup.long 0x3F0++0xF line.long 0x0 "SPI_I2S_HWCFGR,SPI/I2S hardware configuration register" hexmask.long.byte 0x0 16.--19. 1. "DSCFG,DSCFG" hexmask.long.byte 0x0 12.--15. 1. "I2SCFG,I2SCFG" hexmask.long.byte 0x0 8.--11. 1. "CRCCFG,CRCCFG" hexmask.long.byte 0x0 4.--7. 1. "RXFCFG,RXFCFG" hexmask.long.byte 0x0 0.--3. 1. "TXFCFG,TXFCFG" line.long 0x4 "SPI_VERR,SPI/I2S version register" hexmask.long.byte 0x4 4.--7. 1. "MAJREV,MAJREV" hexmask.long.byte 0x4 0.--3. 1. "MINREV,MINREV" line.long 0x8 "SPI_IPIDR,SPI/I2S identification register" hexmask.long 0x8 0.--31. 1. "ID,ID" line.long 0xC "SPI_SIDR,SPI/I2S size identification register" hexmask.long 0xC 0.--31. 1. "SID,SID" tree.end endif tree.end tree "STGEN (System Timer Generator)" base ad:0x0 sif (cpuis("STM32MP13*")) tree "STGENR" base ad:0x0 tree "STGENR (STGENR)" base ad:0x5A005000 rgroup.long 0x0++0x7 line.long 0x0 "STGENR_CNTCVL,STGENR value lower register" hexmask.long 0x0 0.--31. 1. "CNTCVL_L_32,current value of the timestamp counter (the lower 32 bits)" line.long 0x4 "STGENR_CNTCVU,STGENR value upper register" hexmask.long 0x4 0.--31. 1. "CNTCVU_U_32,current value of the timestamp counter (the upper 32 bits)" rgroup.long 0xFD0++0x2F line.long 0x0 "STGENR_PIDR4,STGENR peripheral ID4 register" hexmask.long.byte 0x0 4.--7. 1. "SIZE,always 0b0000" hexmask.long.byte 0x0 0.--3. 1. "DES_2,part of designer identification" line.long 0x4 "STGENR_PIDR5,STGENR peripheral ID5 register" hexmask.long 0x4 0.--31. 1. "PIDR5,peripheral ID5" line.long 0x8 "STGENR_PIDR6,STGENR peripheral ID6 register" hexmask.long 0x8 0.--31. 1. "PIDR6,peripheral ID6" line.long 0xC "STGENR_PIDR7,STGENR peripheral ID7 register" hexmask.long 0xC 0.--31. 1. "PIDR7,peripheral ID7" line.long 0x10 "STGENR_PIDR0,STGENR peripheral ID0 register" hexmask.long.byte 0x10 0.--7. 1. "PART_0,bits[7:0] of the 12-bit part number of the component." line.long 0x14 "STGENR_PIDR1,STGENR peripheral ID1 register" hexmask.long.byte 0x14 4.--7. 1. "DES_0,part of designer identification" hexmask.long.byte 0x14 0.--3. 1. "PART_1,Bits[11:8] of the 12-bit part number of the component" line.long 0x18 "STGENR_PIDR2,STGENR peripheral ID2 register" hexmask.long.byte 0x18 4.--7. 1. "REVISION,device revision number" bitfld.long 0x18 3. "JEDEC,always 1" "0,1" bitfld.long 0x18 0.--2. "DES_1,part of designer identification" "0,1,2,3,4,5,6,7" line.long 0x1C "STGENR_PIDR3,STGENR peripheral ID3 register" hexmask.long.byte 0x1C 4.--7. 1. "REVAND,errata fix identification" hexmask.long.byte 0x1C 0.--3. 1. "CMOD,customer modified" line.long 0x20 "STGENR_CIDR0,STGENR component ID0 register" hexmask.long.byte 0x20 0.--7. 1. "PRMBL_0,preamble 0" line.long 0x24 "STGENR_CIDR1,STGENR component ID1 register" hexmask.long.byte 0x24 4.--7. 1. "CLASS,class of the component" hexmask.long.byte 0x24 0.--3. 1. "PRMBL_1,preamble 1" line.long 0x28 "STGENR_CIDR2,STGENR component ID2 register" hexmask.long.byte 0x28 0.--7. 1. "PRMBL_2,preamble 2" line.long 0x2C "STGENR_CIDR3,STGENR component ID3 register" hexmask.long.byte 0x2C 0.--7. 1. "PRMBL_3,preamble 3" tree.end tree.end endif sif (cpuis("STM32MP13*")) tree "STGENC" base ad:0x5C008000 group.long 0x0++0x3 line.long 0x0 "STGENC_CNTCR,STGENC control register" bitfld.long 0x0 1. "HLTDBG,halt on debug" "0: do not halt on debug; hltdbg signal into the..,1: halt on debug; when hltdbg is driven high the.." bitfld.long 0x0 0. "EN,enable" "0: counter disabled and not incrementing,1: counter enabled and incrementing" rgroup.long 0x4++0x3 line.long 0x0 "STGENC_CNTSR,STGENC status register" bitfld.long 0x0 1. "HLTDBG,halt on debug" "0: do not halt on debug; hltdbg signal into the..,1: halt on debug; when hltdbg is driven high the.." bitfld.long 0x0 0. "EN,enable" "0: counter disabled and not incrementing,1: counter enabled and incrementing" group.long 0x8++0x7 line.long 0x0 "STGENC_CNTCVL,STGENC value lower register" hexmask.long 0x0 0.--31. 1. "CNTCVL_L_32,current value of the timestamp counter lower 32 bits" line.long 0x4 "STGENC_CNTCVU,STGENC value upper register" hexmask.long 0x4 0.--31. 1. "CNTCVU_U_32,current value of the timestamp counter upper 32 bits" group.long 0x20++0x3 line.long 0x0 "STGENC_CNTFID0,STGENC base frequency register" hexmask.long 0x0 0.--31. 1. "FREQ,frequency in number of ticks per second." rgroup.long 0xFD0++0x2F line.long 0x0 "STGENC_PIDR4,STGENC peripheral ID4 register" hexmask.long.byte 0x0 4.--7. 1. "SIZE,always 0b0000" hexmask.long.byte 0x0 0.--3. 1. "DES_2,part of designer identification" line.long 0x4 "STGENC_PIDR5,STGENC peripheral ID5 register" hexmask.long 0x4 0.--31. 1. "PIDR5,peripheral ID5" line.long 0x8 "STGENC_PIDR6,STGENC peripheral ID6 register" hexmask.long 0x8 0.--31. 1. "PIDR6,peripheral ID6" line.long 0xC "STGENC_PIDR7,STGENC peripheral ID7 register" hexmask.long 0xC 0.--31. 1. "PIDR7,peripheral ID7" line.long 0x10 "STGENC_PIDR0,STGENC peripheral ID0 register" hexmask.long.byte 0x10 0.--7. 1. "PART_0,bits[7:0] of the 12-bit part number of the component." line.long 0x14 "STGENC_PIDR1,STGENC peripheral ID1 register" hexmask.long.byte 0x14 4.--7. 1. "DES_0,part of designer identification" hexmask.long.byte 0x14 0.--3. 1. "PART_1,Bits[11:8] of the 12-bit part number of the component" line.long 0x18 "STGENC_PIDR2,STGENC peripheral ID2 register" hexmask.long.byte 0x18 4.--7. 1. "REVISION,device revision number" bitfld.long 0x18 3. "JEDEC,always 1" "0,1" bitfld.long 0x18 0.--2. "DES_1,part of designer identification" "0,1,2,3,4,5,6,7" line.long 0x1C "STGENC_PIDR3,STGENC peripheral ID3 register" hexmask.long.byte 0x1C 4.--7. 1. "REVAND,customer version" hexmask.long.byte 0x1C 0.--3. 1. "CMOD,customer modified" line.long 0x20 "STGENC_CIDR0,STGENC component ID0 register" hexmask.long.byte 0x20 0.--7. 1. "PRMBL_0,preamble 0" line.long 0x24 "STGENC_CIDR1,STGENC component ID1 register" hexmask.long.byte 0x24 4.--7. 1. "CLASS,class of the component" hexmask.long.byte 0x24 0.--3. 1. "PRMBL_1,preamble 1" line.long 0x28 "STGENC_CIDR2,STGENC component ID2 register" hexmask.long.byte 0x28 0.--7. 1. "PRMBL_2,preamble 2" line.long 0x2C "STGENC_CIDR3,STGENC component ID3 register" hexmask.long.byte 0x2C 0.--7. 1. "PRMBL_3,preamble 3" tree.end endif sif (cpuis("STM32MP151*")||cpuis("STM32MP153*")||cpuis("STM32MP157*")) tree "STGENC" base ad:0x5C008000 group.long 0x0++0x3 line.long 0x0 "STGENC_CNTCR,STGENC control register" bitfld.long 0x0 1. "HLTDBG,HLTDBG" "0,1" bitfld.long 0x0 0. "EN,EN" "0,1" rgroup.long 0x4++0x3 line.long 0x0 "STGENC_CNTSR,STGENC status register" bitfld.long 0x0 1. "HLTDBG,HLTDBG" "0,1" bitfld.long 0x0 0. "EN,EN" "0,1" group.long 0x8++0x7 line.long 0x0 "STGENC_CNTCVL,the control interface must clear the STGENC_CNTCR.EN bit before writing to this register." hexmask.long 0x0 0.--31. 1. "CNTCVL_L_32,CNTCVL_L_32" line.long 0x4 "STGENC_CNTCVU,the control interface must clear the STGENC_CNTCR.EN bit before writing to this register." hexmask.long 0x4 0.--31. 1. "CNTCVU_U_32,CNTCVU_U_32" group.long 0x20++0x3 line.long 0x0 "STGENC_CNTFID0,the control interface must clear the STGEN_CNTCR.EN bit before writing to this register." hexmask.long 0x0 0.--31. 1. "FREQ,FREQ" rgroup.long 0xFD0++0x2F line.long 0x0 "STGENC_PIDR4,STGENC peripheral ID4 register" hexmask.long.byte 0x0 4.--7. 1. "SIZE,SIZE" hexmask.long.byte 0x0 0.--3. 1. "DES_2,DES_2" line.long 0x4 "STGENC_PIDR5,STGENC peripheral ID5 register" hexmask.long 0x4 0.--31. 1. "PIDR5,PIDR5" line.long 0x8 "STGENC_PIDR6,STGENC peripheral ID6 register" hexmask.long 0x8 0.--31. 1. "PIDR6,PIDR6" line.long 0xC "STGENC_PIDR7,STGENC peripheral ID7 register" hexmask.long 0xC 0.--31. 1. "PIDR7,PIDR7" line.long 0x10 "STGENC_PIDR0,STGENC peripheral ID0 register" hexmask.long.byte 0x10 0.--7. 1. "PART_0,PART_0" line.long 0x14 "STGENC_PIDR1,STGENC peripheral ID1 register" hexmask.long.byte 0x14 4.--7. 1. "DES_0,DES_0" hexmask.long.byte 0x14 0.--3. 1. "PART_1,PART_1" line.long 0x18 "STGENC_PIDR2,STGENC peripheral ID2 register" hexmask.long.byte 0x18 4.--7. 1. "REVISION,REVISION" bitfld.long 0x18 3. "JEDEC,JEDEC" "0,1" bitfld.long 0x18 0.--2. "DES_1,DES_1" "0,1,2,3,4,5,6,7" line.long 0x1C "STGENC_PIDR3,STGENC peripheral ID3 register" hexmask.long.byte 0x1C 4.--7. 1. "REVAND,REVAND" hexmask.long.byte 0x1C 0.--3. 1. "CMOD,CMOD" line.long 0x20 "STGENC_CIDR0,STGENC component ID0 register" hexmask.long.byte 0x20 0.--7. 1. "PRMBL_0,PRMBL_0" line.long 0x24 "STGENC_CIDR1,STGENC component ID1 register" hexmask.long.byte 0x24 4.--7. 1. "CLASS,CLASS" hexmask.long.byte 0x24 0.--3. 1. "PRMBL_1,PRMBL_1" line.long 0x28 "STGENC_CIDR2,STGENC component ID2 register" hexmask.long.byte 0x28 0.--7. 1. "PRMBL_2,PRMBL_2" line.long 0x2C "STGENC_CIDR3,STGENC component ID3 register" hexmask.long.byte 0x2C 0.--7. 1. "PRMBL_3,PRMBL_3" tree.end endif sif (cpuis("STM32MP151*")||cpuis("STM32MP153*")||cpuis("STM32MP157*")) tree "STGENR" base ad:0x5A005000 rgroup.long 0x0++0x7 line.long 0x0 "STGENR_CNTCVL,the control interface must clear the STGEN_CNTCR.EN bit before writing to this register." hexmask.long 0x0 0.--31. 1. "CNTCVL_L_32,CNTCVL_L_32" line.long 0x4 "STGENR_CNTCVU,the control interface must clear the STGEN_CNTCR.EN bit before writing to this register." hexmask.long 0x4 0.--31. 1. "CNTCVU_U_32,CNTCVU_U_32" rgroup.long 0xFD0++0x2F line.long 0x0 "STGENR_PIDR4,STGENR peripheral ID4 register" hexmask.long.byte 0x0 4.--7. 1. "SIZE,SIZE" hexmask.long.byte 0x0 0.--3. 1. "DES_2,DES_2" line.long 0x4 "STGENR_PIDR5,STGENR peripheral ID5 register" hexmask.long 0x4 0.--31. 1. "PIDR5,PIDR5" line.long 0x8 "STGENR_PIDR6,STGENR peripheral ID6 register" hexmask.long 0x8 0.--31. 1. "PIDR6,PIDR6" line.long 0xC "STGENR_PIDR7,STGENR peripheral ID7 register" hexmask.long 0xC 0.--31. 1. "PIDR7,PIDR7" line.long 0x10 "STGENR_PIDR0,STGENR peripheral ID0 register" hexmask.long.byte 0x10 0.--7. 1. "PART_0,PART_0" line.long 0x14 "STGENR_PIDR1,STGENR peripheral ID1 register" hexmask.long.byte 0x14 4.--7. 1. "DES_0,DES_0" hexmask.long.byte 0x14 0.--3. 1. "PART_1,PART_1" line.long 0x18 "STGENR_PIDR2,STGENR peripheral ID2 register" hexmask.long.byte 0x18 4.--7. 1. "REVISION,REVISION" bitfld.long 0x18 3. "JEDEC,JEDEC" "0,1" bitfld.long 0x18 0.--2. "DES_1,DES_1" "0,1,2,3,4,5,6,7" line.long 0x1C "STGENR_PIDR3,STGENR peripheral ID3 register" hexmask.long.byte 0x1C 4.--7. 1. "REVAND,REVAND" hexmask.long.byte 0x1C 0.--3. 1. "CMOD,CMOD" line.long 0x20 "STGENR_CIDR0,STGENR component ID0 register" hexmask.long.byte 0x20 0.--7. 1. "PRMBL_0,PRMBL_0" line.long 0x24 "STGENR_CIDR1,STGENR component ID1 register" hexmask.long.byte 0x24 4.--7. 1. "CLASS,CLASS" hexmask.long.byte 0x24 0.--3. 1. "PRMBL_1,PRMBL_1" line.long 0x28 "STGENR_CIDR2,STGENR component ID2 register" hexmask.long.byte 0x28 0.--7. 1. "PRMBL_2,PRMBL_2" line.long 0x2C "STGENR_CIDR3,STGENR component ID3 register" hexmask.long.byte 0x2C 0.--7. 1. "PRMBL_3,PRMBL_3" tree.end endif tree.end tree "SYSCFG (System Configuration Controller)" base ad:0x50020000 group.long 0x0++0x7 line.long 0x0 "SYSCFG_BOOTR,SYSCFG boot pins control register" sif (cpuis("STM32MP151*")) bitfld.long 0x0 6. "BOOT2_PD,BOOT2_PD" "0,1" newline bitfld.long 0x0 5. "BOOT1_PD,BOOT1_PD" "0,1" newline bitfld.long 0x0 4. "BOOT0_PD,BOOT0_PD" "0,1" newline endif sif (cpuis("STM32MP153*")) bitfld.long 0x0 6. "BOOT2_PD,BOOT2_PD" "0,1" newline bitfld.long 0x0 5. "BOOT1_PD,BOOT1_PD" "0,1" newline bitfld.long 0x0 4. "BOOT0_PD,BOOT0_PD" "0,1" newline endif sif (cpuis("STM32MP157*")) bitfld.long 0x0 6. "BOOT2_PD,BOOT2_PD" "0,1" newline bitfld.long 0x0 5. "BOOT1_PD,BOOT1_PD" "0,1" newline bitfld.long 0x0 4. "BOOT0_PD,BOOT0_PD" "0,1" newline endif sif (cpuis("STM32MP13*")) rbitfld.long 0x0 2. "BOOT2,BOOT2 pin value" "0: BOOT2 pin connected to VSS,1: BOOT2 pin connected to VDD" newline rbitfld.long 0x0 1. "BOOT1,BOOT1 pin value" "0: BOOT1 pin connected to VSS,1: BOOT1 pin connected to VDD" newline rbitfld.long 0x0 0. "BOOT0,BOOT0 pin value" "0: BOOT0 pin connected to VSS,1: BOOT0 pin connected to VDD" newline endif sif (cpuis("STM32MP151*")) rbitfld.long 0x0 2. "BOOT2,BOOT2" "0,1" newline rbitfld.long 0x0 1. "BOOT1,BOOT1" "0,1" newline endif sif (cpuis("STM32MP153*")) rbitfld.long 0x0 2. "BOOT2,BOOT2" "0,1" newline rbitfld.long 0x0 1. "BOOT1,BOOT1" "0,1" newline rbitfld.long 0x0 0. "BOOT0,BOOT0" "0,1" newline endif sif (cpuis("STM32MP157*")) rbitfld.long 0x0 2. "BOOT2,BOOT2" "0,1" newline rbitfld.long 0x0 1. "BOOT1,BOOT1" "0,1" newline rbitfld.long 0x0 0. "BOOT0,BOOT0" "0,1" endif line.long 0x4 "SYSCFG_PMCSETR,SYSCFG peripheral mode configuration set register" sif (cpuis("STM32MP13*")) bitfld.long 0x4 29.--31. "ETH2_SEL,Ethernet PHY interface selection." "0: MII,1: RGMII,?,?,4: RMII,?,?,?" newline bitfld.long 0x4 25. "ETH2_REF_CLK_SEL,Ethernet reference clock selection." "0: Writing '0' has no effect reading '0' means the..,1: Writing '1' sets this bit reading '1' means the.." newline bitfld.long 0x4 24. "ETH2_CLK_SEL,Gigabit Ethernet 125 MHz clock selection. Only useful with RGMII PHY." "0: Writing '0' has no effect reading '0' means the..,1: Writing '1' sets this bit reading '1' means the.." newline bitfld.long 0x4 21.--23. "ETH1_SEL,Ethernet PHY interface selection." "0: MII,1: RGMII,?,?,4: RMII,?,?,?" newline bitfld.long 0x4 17. "ETH1_REF_CLK_SEL,Ethernet reference clock selection." "0: Writing '0' has no effect reading '0' means the..,1: Writing '1' sets this bit reading '1' means the.." newline bitfld.long 0x4 16. "ETH1_CLK_SEL,Gigabit Ethernet 125 MHz clock selection. Only useful with RGMII PHY." "0: Writing '0' has no effect reading '0' means the..,1: Writing '1' sets this bit reading '1' means the.." newline bitfld.long 0x4 9. "ANASWVDD,GPIO analog switch supply voltage selection" "0: Writing '0' has no effect reading '0' means..,1: Writing '1' sets this bit reading '1' means.." newline bitfld.long 0x4 8. "EN_BOOSTER,GPIO analog switch supply voltage booster enable." "0: Writing '0' has no effect reading '0' means..,1: Writing '1' sets this bit reading '1' means.." newline bitfld.long 0x4 4. "I2C5_FMP,Fast mode plus (FM+) enable" "0: Writing '0' has no effect reading '0' means I2C5..,1: Writing '1' sets this bit reading '1' means the.." newline bitfld.long 0x4 3. "I2C4_FMP,Fast Mode Plus (FM+) Enable" "0: Writing '0' has no effect reading '0' means I2C4..,1: Writing '1' sets this bit reading '1' means the.." newline bitfld.long 0x4 2. "I2C3_FMP,Fast Mode Plus (FM+) Enable" "0: Writing '0' has no effect reading '0' means I2C3..,1: Writing '1' sets this bit reading '1' means the.." newline bitfld.long 0x4 1. "I2C2_FMP,Fast Mode Plus (FM+) Enable" "0: Writing '0' has no effect reading '0' means I2C2..,1: Writing '1' sets this bit reading '1' means the.." newline bitfld.long 0x4 0. "I2C1_FMP,Fast Mode Plus (FM+) Enable" "0: Writing '0' has no effect reading '0' means I2C1..,1: Writing '1' sets this bit reading '1' means the.." newline endif sif (cpuis("STM32MP151*")) bitfld.long 0x4 25. "ANA1_SEL,ANA1_SEL" "0,1" newline bitfld.long 0x4 24. "ANA0_SEL,ANA0_SEL" "0,1" newline bitfld.long 0x4 21.--23. "ETH_SEL,ETH_SEL" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 20. "ETH_SELMII,ETH_SELMII" "0,1" newline endif sif (cpuis("STM32MP153*")) bitfld.long 0x4 25. "ANA1_SEL,ANA1_SEL" "0,1" newline bitfld.long 0x4 24. "ANA0_SEL,ANA0_SEL" "0,1" newline bitfld.long 0x4 21.--23. "ETH_SEL,ETH_SEL" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 20. "ETH_SELMII,ETH_SELMII" "0,1" newline endif sif (cpuis("STM32MP157*")) bitfld.long 0x4 25. "ANA1_SEL,ANA1_SEL" "0,1" newline bitfld.long 0x4 24. "ANA0_SEL,ANA0_SEL" "0,1" newline bitfld.long 0x4 21.--23. "ETH_SEL,ETH_SEL" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 20. "ETH_SELMII,ETH_SELMII" "0,1" newline endif sif (cpuis("STM32MP151*")) bitfld.long 0x4 17. "ETH_REF_CLK_SEL,ETH_REF_CLK_SEL" "0,1" newline bitfld.long 0x4 16. "ETH_CLK_SEL,ETH_CLK_SEL" "0,1" newline endif sif (cpuis("STM32MP153*")) bitfld.long 0x4 17. "ETH_REF_CLK_SEL,ETH_REF_CLK_SEL" "0,1" newline bitfld.long 0x4 16. "ETH_CLK_SEL,ETH_CLK_SEL" "0,1" newline endif sif (cpuis("STM32MP157*")) bitfld.long 0x4 17. "ETH_REF_CLK_SEL,ETH_REF_CLK_SEL" "0,1" newline bitfld.long 0x4 16. "ETH_CLK_SEL,ETH_CLK_SEL" "0,1" newline endif sif (cpuis("STM32MP151*")) bitfld.long 0x4 9. "ANASWVDD,ANASWVDD" "0,1" newline bitfld.long 0x4 8. "EN_BOOSTER,EN_BOOSTER" "0,1" newline endif sif (cpuis("STM32MP153*")) bitfld.long 0x4 9. "ANASWVDD,ANASWVDD" "0,1" newline bitfld.long 0x4 8. "EN_BOOSTER,EN_BOOSTER" "0,1" newline endif sif (cpuis("STM32MP157*")) bitfld.long 0x4 9. "ANASWVDD,ANASWVDD" "0,1" newline bitfld.long 0x4 8. "EN_BOOSTER,EN_BOOSTER" "0,1" newline endif sif (cpuis("STM32MP151*")) bitfld.long 0x4 5. "I2C6_FMP,I2C6_FMP" "0,1" newline bitfld.long 0x4 4. "I2C5_FMP,I2C5_FMP" "0,1" newline bitfld.long 0x4 3. "I2C4_FMP,I2C4_FMP" "0,1" newline bitfld.long 0x4 2. "I2C3_FMP,I2C3_FMP" "0,1" newline bitfld.long 0x4 1. "I2C2_FMP,I2C2_FMP" "0,1" newline endif sif (cpuis("STM32MP153*")) bitfld.long 0x4 5. "I2C6_FMP,I2C6_FMP" "0,1" newline bitfld.long 0x4 4. "I2C5_FMP,I2C5_FMP" "0,1" newline bitfld.long 0x4 3. "I2C4_FMP,I2C4_FMP" "0,1" newline bitfld.long 0x4 2. "I2C3_FMP,I2C3_FMP" "0,1" newline bitfld.long 0x4 1. "I2C2_FMP,I2C2_FMP" "0,1" newline bitfld.long 0x4 0. "I2C1_FMP,I2C1_FMP" "0,1" newline endif sif (cpuis("STM32MP157*")) bitfld.long 0x4 5. "I2C6_FMP,I2C6_FMP" "0,1" newline bitfld.long 0x4 4. "I2C5_FMP,I2C5_FMP" "0,1" newline bitfld.long 0x4 3. "I2C4_FMP,I2C4_FMP" "0,1" newline bitfld.long 0x4 2. "I2C3_FMP,I2C3_FMP" "0,1" newline bitfld.long 0x4 1. "I2C2_FMP,I2C2_FMP" "0,1" newline bitfld.long 0x4 0. "I2C1_FMP,I2C1_FMP" "0,1" endif sif (cpuis("STM32MP13*")) group.long 0x8++0xB line.long 0x0 "SYSCFG_PMCCLRR,SYSCFG peripheral mode configuration clear register" bitfld.long 0x0 29.--31. "ETH2_SEL,Ethernet PHY interface selection." "0: MII,1: RGMII,?,?,4: RMII,?,?,?" bitfld.long 0x0 25. "ETH2_REF_CLK_SEL,Ethernet reference clock selection." "0: 'Writing '0' has no effect reading '0' means the..,1: Writing '1' clears this bit reading '1' means.." newline bitfld.long 0x0 24. "ETH2_CLK_SEL,Gigabit Ethernet 125 MHz clock selection. Only useful with RGMII PHY." "0: Writing '0' has no effect reading '0' means the..,1: Writing '1' clears this bit reading '1' means.." bitfld.long 0x0 21.--23. "ETH1_SEL,Ethernet PHY interface selection." "0: MII,1: RGMII,?,?,4: RMII,?,?,?" newline bitfld.long 0x0 17. "ETH1_REF_CLK_SEL,Ethernet reference clock selection." "0: Writing '0' has no effect reading '0' means the..,1: Writing '1' clears this bit reading '1' means.." bitfld.long 0x0 16. "ETH1_CLK_SEL,Gigabit Ethernet 125 MHz clock selection. Only useful with RGMII PHY." "0: Writing '0' has no effect reading '0' means the..,1: Writing '1' clears this bit reading '1' means.." newline bitfld.long 0x0 9. "ANASWVDD,GPIO analog switch supply voltage selection" "0: Writing '0' has no effect reading '0' means..,1: Writing '1' clears this bit reading '1' means.." bitfld.long 0x0 8. "EN_BOOSTER,GPIO analog switch supply voltage booster enable." "0: Writing '0' has no effect reading '0' means..,1: Writing '1' clears this bit reading '1' means.." newline bitfld.long 0x0 4. "I2C5_FMP,Fast Mode Plus (FM+) Enable" "0: Writing '0' has no effect reading '0' means I2C5..,1: Writing '1' sets this bit reading '1' means the.." bitfld.long 0x0 3. "I2C4_FMP,Fast Mode Plus (FM+) Enable" "0: Writing '0' has no effect reading '0' means I2C4..,1: Writing '1' sets this bit reading '1' means the.." newline bitfld.long 0x0 2. "I2C3_FMP,Fast Mode Plus (FM+) Enable" "0: Writing '0' has no effect reading '0' means I2C3..,1: Writing '1' sets this bit reading '1' means the.." bitfld.long 0x0 1. "I2C2_FMP,Fast Mode Plus (FM+) Enable" "0: Writing '0' has no effect reading '0' means I2C2..,1: Writing '1' sets this bit reading '1' means the.." newline bitfld.long 0x0 0. "I2C1_FMP,Fast Mode Plus (FM+) Enable" "0: Writing '0' has no effect reading '0' means I2C1..,1: Writing '1' sets this bit reading '1' means the.." line.long 0x4 "SYSCFG_BOOTCR,SYSCFG boot control register" bitfld.long 0x4 0. "BMEN,Boot mode enable" "0: While a potential tamper event is raised by TAMP..,1: While a potential tamper event is raised by TAMP.." line.long 0x8 "SYSCFG_SRAM3ERASER,SYSCFG SRAM3 erase register" rbitfld.long 0x8 1. "SRAM3EO,SRAM3 erase ongoing" "0: no erase ongoing,1: erase ongoing" bitfld.long 0x8 0. "SRAM3ER,SRAM3 erase request" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "SYSCFG_SRAM3KR,SYSCFG SRAM3 erase key register" hexmask.long.byte 0x0 0.--7. 1. "KEY,SRAM3 software erase key" group.long 0x30++0xB line.long 0x0 "SYSCFG_CMPSD1CR,SYSCFG VDDSD1 compensation cell control register" hexmask.long.byte 0x0 28.--31. 1. "APSRC,PMOS I/O Compensation value provided by compensation cell" hexmask.long.byte 0x0 24.--27. 1. "ANSRC,NMOS I/O Compensation value provided by compensation cell" newline hexmask.long.byte 0x0 20.--23. 1. "RAPSRC,PMOS I/O compensation value sent to I/Os when SW_CTRL = 1" hexmask.long.byte 0x0 16.--19. 1. "RANSRC,NMOS I/O compensation value sent to I/Os when SW_CTRL = 1" newline rbitfld.long 0x0 8. "READY,Compensation cell ready flag" "0: I/O compensation cell not ready.,1: I/O compensation cell ready the values of.." bitfld.long 0x0 1. "SW_CTRL,Compensation software control" "0: I/O compensation values come from compensation..,1: I/O compensation values come from RANSRC[3:0].." line.long 0x4 "SYSCFG_CMPSD1ENSETR,SYSCFG VDDSD1 compensation cell enable set register" bitfld.long 0x4 0. "EN,Compensation cell enable" "0: Writing '0' has no effect reading '0’ means..,1: Writing '1' enables I/O compensation cell.." line.long 0x8 "SYSCFG_CMPSD1ENCLRR,SYSCFG VDDSD1 compensation cell enable clear register" bitfld.long 0x8 0. "EN,Compensation cell enable" "0: Writing '0' has no effect reading '0’ means..,1: Writing '1' clear EN bit reading '1’ means.." group.long 0x40++0xB line.long 0x0 "SYSCFG_CMPSD2CR,SYSCFG VDDSD2 compensation cell control register" hexmask.long.byte 0x0 28.--31. 1. "APSRC,PMOS I/O Compensation value provided by compensation cell" hexmask.long.byte 0x0 24.--27. 1. "ANSRC,NMOS I/O Compensation value provided by compensation cell" newline hexmask.long.byte 0x0 20.--23. 1. "RAPSRC,PMOS I/O compensation value sent to I/Os when SW_CTRL = 1" hexmask.long.byte 0x0 16.--19. 1. "RANSRC,NMOS I/O compensation value sent to I/Os when SW_CTRL = 1" newline rbitfld.long 0x0 8. "READY,Compensation cell ready flag" "0: I/O compensation cell not ready.,1: I/O compensation cell ready the values of.." bitfld.long 0x0 1. "SW_CTRL,Compensation Software Control" "0: I/O compensation values come from compensation..,1: I/O compensation values come from RANSRC[3:0].." line.long 0x4 "SYSCFG_CMPSD2ENSETR,SYSCFG VDDSD2 compensation cell enable set register" bitfld.long 0x4 0. "EN,Compensation cell enable" "0: Writing '0' has no effect reading '0’ means..,1: Writing '1' enables I/O compensation cell.." line.long 0x8 "SYSCFG_CMPSD2ENCLRR,SYSCFG VDDSD2 compensation cell enable clear register" bitfld.long 0x8 0. "EN,Compensation cell enable" "0: Writing '0' has no effect reading '0’ means..,1: Writing '1' clear MPU_EN bit reading '1’.." wgroup.long 0x50++0x2F line.long 0x0 "SYSCFG_HSLVEN0R,SYSCFG high-speed low-voltage enable register 0" hexmask.long.word 0x0 0.--15. 1. "HSLVEN,High-speed low-voltage I/O mode enable." line.long 0x4 "SYSCFG_HSLVEN1R,SYSCFG high-speed low-voltage enable register 1" hexmask.long.word 0x4 0.--15. 1. "HSLVEN,High-speed low-voltage I/O mode enable." line.long 0x8 "SYSCFG_HSLVEN2R,SYSCFG high-speed low-voltage enable register 2" hexmask.long.word 0x8 0.--15. 1. "HSLVEN,High-speed low-voltage I/O mode enable." line.long 0xC "SYSCFG_HSLVEN3R,SYSCFG high-speed low-voltage enable register 3" hexmask.long.word 0xC 0.--15. 1. "HSLVEN,High-speed low-voltage I/O mode enable." line.long 0x10 "SYSCFG_HSLVEN4R,SYSCFG high-speed low-voltage enable register 4" hexmask.long.word 0x10 0.--15. 1. "HSLVEN,High-speed low-voltage I/O mode enable." line.long 0x14 "SYSCFG_HSLVEN5R,SYSCFG high-speed low-voltage enable register 5" hexmask.long.word 0x14 0.--15. 1. "HSLVEN,High-speed low-voltage I/O mode enable." line.long 0x18 "SYSCFG_HSLVEN6R,SYSCFG high-speed low-voltage enable register 6" hexmask.long.word 0x18 0.--15. 1. "HSLVEN,High-speed low-voltage I/O mode enable." line.long 0x1C "SYSCFG_HSLVEN7R,SYSCFG high-speed low-voltage enable register 7" hexmask.long.word 0x1C 0.--15. 1. "HSLVEN,High-speed low-voltage I/O mode enable." line.long 0x20 "SYSCFG_HSLVEN8R,SYSCFG high-speed low-voltage enable register 8" hexmask.long.word 0x20 0.--15. 1. "HSLVEN,High-speed low-voltage I/O mode enable." line.long 0x24 "SYSCFG_HSLVEN9R,SYSCFG high-speed low-voltage enable register 9" hexmask.long.word 0x24 0.--15. 1. "HSLVEN,High-speed low-voltage I/O mode enable." line.long 0x28 "SYSCFG_HSLVEN10R,SYSCFG high-speed low-voltage enable register 10" hexmask.long.word 0x28 0.--15. 1. "HSLVEN,High-speed low-voltage I/O mode enable." line.long 0x2C "SYSCFG_HSLVEN11R,SYSCFG high-speed low-voltage enable register 11" hexmask.long.word 0x2C 0.--15. 1. "HSLVEN,High-speed low-voltage I/O mode enable." rgroup.long 0x380++0x3 line.long 0x0 "SYSCFG_IDC,SYSCFG identity code register" hexmask.long.word 0x0 16.--31. 1. "REV_ID,device revision" hexmask.long.word 0x0 0.--11. 1. "DEV_ID,device ID" endif sif (cpuis("STM32MP151*")) group.long 0x18++0x7 line.long 0x0 "SYSCFG_IOCTRLSETR,SYSCFG IO control register" bitfld.long 0x0 4. "HSLVEN_SPI,HSLVEN_SPI" "0,1" bitfld.long 0x0 3. "HSLVEN_SDMMC,HSLVEN_SDMMC" "0,1" newline bitfld.long 0x0 2. "HSLVEN_ETH,HSLVEN_ETH" "0,1" bitfld.long 0x0 1. "HSLVEN_QUADSPI,HSLVEN_QUADSPI" "0,1" newline bitfld.long 0x0 0. "HSLVEN_TRACE,HSLVEN_TRACE" "0,1" line.long 0x4 "SYSCFG_ICNR,SYSCFG interconnect control register" bitfld.long 0x4 10. "AXI_M10,AXI_M10" "0,1" bitfld.long 0x4 9. "AXI_M9,AXI_M9" "0,1" newline bitfld.long 0x4 8. "AXI_M8,AXI_M8" "0,1" bitfld.long 0x4 7. "AXI_M7,AXI_M7" "0,1" newline bitfld.long 0x4 6. "AXI_M6,AXI_M6" "0,1" bitfld.long 0x4 5. "AXI_M5,AXI_M5" "0,1" newline bitfld.long 0x4 3. "AXI_M3,AXI_M3" "0,1" bitfld.long 0x4 2. "AXI_M2,AXI_M2" "0,1" newline bitfld.long 0x4 1. "AXI_M1,AXI_M1" "0,1" bitfld.long 0x4 0. "AXI_M0,AXI_M0" "0,1" group.long 0x44++0x3 line.long 0x0 "SYSCFG_PMCCLRR,SYSCFG peripheral mode configuration clear register" bitfld.long 0x0 25. "ANA1_SEL,ANA1_SEL" "0,1" bitfld.long 0x0 24. "ANA0_SEL,ANA0_SEL" "0,1" newline bitfld.long 0x0 21.--23. "ETH_SEL,ETH_SEL" "0,1,2,3,4,5,6,7" bitfld.long 0x0 20. "ETH_SELMII,ETH_SELMII" "0,1" newline bitfld.long 0x0 17. "ETH_REF_CLK_SEL,ETH_REF_CLK_SEL" "0,1" bitfld.long 0x0 16. "ETH_CLK_SEL,ETH_CLK_SEL" "0,1" newline bitfld.long 0x0 9. "ANASWVDD,ANASWVDD" "0,1" bitfld.long 0x0 8. "EN_BOOSTER,EN_BOOSTER" "0,1" newline bitfld.long 0x0 5. "I2C6_FMP,I2C6_FMP" "0,1" bitfld.long 0x0 4. "I2C5_FMP,I2C5_FMP" "0,1" newline bitfld.long 0x0 3. "I2C4_FMP,I2C4_FMP" "0,1" bitfld.long 0x0 2. "I2C3_FMP,I2C3_FMP" "0,1" newline bitfld.long 0x0 1. "I2C2_FMP,I2C2_FMP" "0,1" bitfld.long 0x0 0. "I2C1_FMP,I2C1_FMP" "0,1" group.long 0x58++0x3 line.long 0x0 "SYSCFG_IOCTRLCLRR,SYSCFG IO control register" bitfld.long 0x0 4. "HSLVEN_SPI,HSLVEN_SPI" "0,1" bitfld.long 0x0 3. "HSLVEN_SDMMC,HSLVEN_SDMMC" "0,1" newline bitfld.long 0x0 2. "HSLVEN_ETH,HSLVEN_ETH" "0,1" bitfld.long 0x0 1. "HSLVEN_QUADSPI,HSLVEN_QUADSPI" "0,1" newline bitfld.long 0x0 0. "HSLVEN_TRACE,HSLVEN_TRACE" "0,1" endif sif (cpuis("STM32MP153*")) group.long 0x18++0x7 line.long 0x0 "SYSCFG_IOCTRLSETR,SYSCFG IO control register" bitfld.long 0x0 4. "HSLVEN_SPI,HSLVEN_SPI" "0,1" bitfld.long 0x0 3. "HSLVEN_SDMMC,HSLVEN_SDMMC" "0,1" newline bitfld.long 0x0 2. "HSLVEN_ETH,HSLVEN_ETH" "0,1" bitfld.long 0x0 1. "HSLVEN_QUADSPI,HSLVEN_QUADSPI" "0,1" newline bitfld.long 0x0 0. "HSLVEN_TRACE,HSLVEN_TRACE" "0,1" line.long 0x4 "SYSCFG_ICNR,SYSCFG interconnect control register" bitfld.long 0x4 10. "AXI_M10,AXI_M10" "0,1" bitfld.long 0x4 9. "AXI_M9,AXI_M9" "0,1" newline bitfld.long 0x4 8. "AXI_M8,AXI_M8" "0,1" bitfld.long 0x4 7. "AXI_M7,AXI_M7" "0,1" newline bitfld.long 0x4 6. "AXI_M6,AXI_M6" "0,1" bitfld.long 0x4 5. "AXI_M5,AXI_M5" "0,1" newline bitfld.long 0x4 3. "AXI_M3,AXI_M3" "0,1" bitfld.long 0x4 2. "AXI_M2,AXI_M2" "0,1" newline bitfld.long 0x4 1. "AXI_M1,AXI_M1" "0,1" bitfld.long 0x4 0. "AXI_M0,AXI_M0" "0,1" group.long 0x44++0x3 line.long 0x0 "SYSCFG_PMCCLRR,SYSCFG peripheral mode configuration clear register" bitfld.long 0x0 25. "ANA1_SEL,ANA1_SEL" "0,1" bitfld.long 0x0 24. "ANA0_SEL,ANA0_SEL" "0,1" newline bitfld.long 0x0 21.--23. "ETH_SEL,ETH_SEL" "0,1,2,3,4,5,6,7" bitfld.long 0x0 20. "ETH_SELMII,ETH_SELMII" "0,1" newline bitfld.long 0x0 17. "ETH_REF_CLK_SEL,ETH_REF_CLK_SEL" "0,1" bitfld.long 0x0 16. "ETH_CLK_SEL,ETH_CLK_SEL" "0,1" newline bitfld.long 0x0 9. "ANASWVDD,ANASWVDD" "0,1" bitfld.long 0x0 8. "EN_BOOSTER,EN_BOOSTER" "0,1" newline bitfld.long 0x0 5. "I2C6_FMP,I2C6_FMP" "0,1" bitfld.long 0x0 4. "I2C5_FMP,I2C5_FMP" "0,1" newline bitfld.long 0x0 3. "I2C4_FMP,I2C4_FMP" "0,1" bitfld.long 0x0 2. "I2C3_FMP,I2C3_FMP" "0,1" newline bitfld.long 0x0 1. "I2C2_FMP,I2C2_FMP" "0,1" bitfld.long 0x0 0. "I2C1_FMP,I2C1_FMP" "0,1" group.long 0x58++0x3 line.long 0x0 "SYSCFG_IOCTRLCLRR,SYSCFG IO control register" bitfld.long 0x0 4. "HSLVEN_SPI,HSLVEN_SPI" "0,1" bitfld.long 0x0 3. "HSLVEN_SDMMC,HSLVEN_SDMMC" "0,1" newline bitfld.long 0x0 2. "HSLVEN_ETH,HSLVEN_ETH" "0,1" bitfld.long 0x0 1. "HSLVEN_QUADSPI,HSLVEN_QUADSPI" "0,1" newline bitfld.long 0x0 0. "HSLVEN_TRACE,HSLVEN_TRACE" "0,1" endif sif (cpuis("STM32MP157*")) group.long 0x18++0x7 line.long 0x0 "SYSCFG_IOCTRLSETR,SYSCFG IO control register" bitfld.long 0x0 4. "HSLVEN_SPI,HSLVEN_SPI" "0,1" bitfld.long 0x0 3. "HSLVEN_SDMMC,HSLVEN_SDMMC" "0,1" newline bitfld.long 0x0 2. "HSLVEN_ETH,HSLVEN_ETH" "0,1" bitfld.long 0x0 1. "HSLVEN_QUADSPI,HSLVEN_QUADSPI" "0,1" newline bitfld.long 0x0 0. "HSLVEN_TRACE,HSLVEN_TRACE" "0,1" line.long 0x4 "SYSCFG_ICNR,SYSCFG interconnect control register" bitfld.long 0x4 10. "AXI_M10,AXI_M10" "0,1" bitfld.long 0x4 9. "AXI_M9,AXI_M9" "0,1" newline bitfld.long 0x4 8. "AXI_M8,AXI_M8" "0,1" bitfld.long 0x4 7. "AXI_M7,AXI_M7" "0,1" newline bitfld.long 0x4 6. "AXI_M6,AXI_M6" "0,1" bitfld.long 0x4 5. "AXI_M5,AXI_M5" "0,1" newline bitfld.long 0x4 3. "AXI_M3,AXI_M3" "0,1" bitfld.long 0x4 2. "AXI_M2,AXI_M2" "0,1" newline bitfld.long 0x4 1. "AXI_M1,AXI_M1" "0,1" bitfld.long 0x4 0. "AXI_M0,AXI_M0" "0,1" group.long 0x44++0x3 line.long 0x0 "SYSCFG_PMCCLRR,SYSCFG peripheral mode configuration clear register" bitfld.long 0x0 25. "ANA1_SEL,ANA1_SEL" "0,1" bitfld.long 0x0 24. "ANA0_SEL,ANA0_SEL" "0,1" newline bitfld.long 0x0 21.--23. "ETH_SEL,ETH_SEL" "0,1,2,3,4,5,6,7" bitfld.long 0x0 20. "ETH_SELMII,ETH_SELMII" "0,1" newline bitfld.long 0x0 17. "ETH_REF_CLK_SEL,ETH_REF_CLK_SEL" "0,1" bitfld.long 0x0 16. "ETH_CLK_SEL,ETH_CLK_SEL" "0,1" newline bitfld.long 0x0 9. "ANASWVDD,ANASWVDD" "0,1" bitfld.long 0x0 8. "EN_BOOSTER,EN_BOOSTER" "0,1" newline bitfld.long 0x0 5. "I2C6_FMP,I2C6_FMP" "0,1" bitfld.long 0x0 4. "I2C5_FMP,I2C5_FMP" "0,1" newline bitfld.long 0x0 3. "I2C4_FMP,I2C4_FMP" "0,1" bitfld.long 0x0 2. "I2C3_FMP,I2C3_FMP" "0,1" newline bitfld.long 0x0 1. "I2C2_FMP,I2C2_FMP" "0,1" bitfld.long 0x0 0. "I2C1_FMP,I2C1_FMP" "0,1" group.long 0x58++0x3 line.long 0x0 "SYSCFG_IOCTRLCLRR,SYSCFG IO control register" bitfld.long 0x0 4. "HSLVEN_SPI,HSLVEN_SPI" "0,1" bitfld.long 0x0 3. "HSLVEN_SDMMC,HSLVEN_SDMMC" "0,1" newline bitfld.long 0x0 2. "HSLVEN_ETH,HSLVEN_ETH" "0,1" bitfld.long 0x0 1. "HSLVEN_QUADSPI,HSLVEN_QUADSPI" "0,1" newline bitfld.long 0x0 0. "HSLVEN_TRACE,HSLVEN_TRACE" "0,1" endif group.long 0x20++0xF line.long 0x0 "SYSCFG_CMPCR,SYSCFG main compensation cell control register" hexmask.long.byte 0x0 28.--31. 1. "APSRC,PMOS I/O compensation value provided by compensation cell" newline hexmask.long.byte 0x0 24.--27. 1. "ANSRC,NMOS I/O compensation value provided by compensation cell" newline sif (cpuis("STM32MP13*")) hexmask.long.byte 0x0 20.--23. 1. "RAPSRC,PMOS I/O Compensation value sent to I/Os when SW_CTRL = 1" newline hexmask.long.byte 0x0 16.--19. 1. "RANSRC,NMOS I/O compensation value sent to I/Os when SW_CTRL = 1" newline rbitfld.long 0x0 8. "READY,Compensation cell ready flag" "0: I/O compensation cell not ready,1: I/O compensation cell ready the values of.." newline bitfld.long 0x0 1. "SW_CTRL,Compensation software control" "0: I/O compensation values come from compensation..,1: I/O compensation values come from RANSRC[3:0].." newline endif sif (cpuis("STM32MP151*")) hexmask.long.byte 0x0 20.--23. 1. "RAPSRC,RAPSRC" newline hexmask.long.byte 0x0 16.--19. 1. "RANSRC,RANSRC" newline endif sif (cpuis("STM32MP153*")) hexmask.long.byte 0x0 20.--23. 1. "RAPSRC,RAPSRC" newline hexmask.long.byte 0x0 16.--19. 1. "RANSRC,RANSRC" newline endif sif (cpuis("STM32MP157*")) hexmask.long.byte 0x0 20.--23. 1. "RAPSRC,RAPSRC" newline hexmask.long.byte 0x0 16.--19. 1. "RANSRC,RANSRC" newline endif sif (cpuis("STM32MP151*")) rbitfld.long 0x0 8. "READY,READY" "0,1" newline endif sif (cpuis("STM32MP153*")) rbitfld.long 0x0 8. "READY,READY" "0,1" newline endif sif (cpuis("STM32MP157*")) rbitfld.long 0x0 8. "READY,READY" "0,1" newline endif sif (cpuis("STM32MP153*")) bitfld.long 0x0 1. "SW_CTRL,SW_CTRL" "0,1" newline endif sif (cpuis("STM32MP157*")) bitfld.long 0x0 1. "SW_CTRL,SW_CTRL" "0,1" endif line.long 0x4 "SYSCFG_CMPENSETR,SYSCFG main compensation cell enable set register" sif (cpuis("STM32MP151*")) bitfld.long 0x4 1. "MCU_EN,MCU_EN" "0,1" newline bitfld.long 0x4 0. "MPU_EN,MPU_EN" "0,1" newline endif sif (cpuis("STM32MP153*")) bitfld.long 0x4 1. "MCU_EN,MCU_EN" "0,1" newline bitfld.long 0x4 0. "MPU_EN,MPU_EN" "0,1" newline endif sif (cpuis("STM32MP157*")) bitfld.long 0x4 1. "MCU_EN,MCU_EN" "0,1" newline bitfld.long 0x4 0. "MPU_EN,MPU_EN" "0,1" newline endif sif (cpuis("STM32MP13*")) bitfld.long 0x4 0. "EN,Compensation cell enable" "0: Writing '0' has no effect reading '0’ means..,1: Writing '1' enables I/O compensation cell.." endif line.long 0x8 "SYSCFG_CMPENCLRR,SYSCFG main compensation cell enable set register" sif (cpuis("STM32MP151*")) bitfld.long 0x8 1. "MCU_EN,MCU_EN" "0,1" newline bitfld.long 0x8 0. "MPU_EN,MPU_EN" "0,1" newline endif sif (cpuis("STM32MP153*")) bitfld.long 0x8 1. "MCU_EN,MCU_EN" "0,1" newline bitfld.long 0x8 0. "MPU_EN,MPU_EN" "0,1" newline endif sif (cpuis("STM32MP157*")) bitfld.long 0x8 1. "MCU_EN,MCU_EN" "0,1" newline bitfld.long 0x8 0. "MPU_EN,MPU_EN" "0,1" newline endif sif (cpuis("STM32MP13*")) bitfld.long 0x8 0. "EN,Compensation cell enable" "0: Writing '0' has no effect reading '0’ means..,1: Writing '1' clears EN bit reading '1’ means.." endif line.long 0xC "SYSCFG_CBR,SYSCFG control timer break register" sif (cpuis("STM32MP13*")) bitfld.long 0xC 2. "PVDL,PVD lock enable bit" "0: PVD interrupt disconnected from TIM1/8/15/16/17..,1: PVD interrupt connected to TIM1/8/15/16/17 Break.." newline endif sif (cpuis("STM32MP151*")) bitfld.long 0xC 2. "PVDL,PVDL" "0,1" newline endif sif (cpuis("STM32MP153*")) bitfld.long 0xC 2. "PVDL,PVDL" "0,1" newline endif sif (cpuis("STM32MP157*")) bitfld.long 0xC 2. "PVDL,PVDL" "0,1" newline endif sif (cpuis("STM32MP151*")) bitfld.long 0xC 0. "CLL,CLL" "0,1" newline endif sif (cpuis("STM32MP153*")) bitfld.long 0xC 0. "CLL,CLL" "0,1" newline endif sif (cpuis("STM32MP157*")) bitfld.long 0xC 0. "CLL,CLL" "0,1" endif group.long 0x3F4++0xB line.long 0x0 "SYSCFG_VERR,SYSCFG version register" sif (cpuis("STM32MP13*")) hexmask.long.byte 0x0 4.--7. 1. "MAJREV,Major revision" newline hexmask.long.byte 0x0 0.--3. 1. "MINREV,Minor revision" newline endif sif (cpuis("STM32MP151*")) hexmask.long.byte 0x0 4.--7. 1. "MAJREV,MAJREV" newline hexmask.long.byte 0x0 0.--3. 1. "MINREV,MINREV" newline endif sif (cpuis("STM32MP153*")) hexmask.long.byte 0x0 4.--7. 1. "MAJREV,MAJREV" newline hexmask.long.byte 0x0 0.--3. 1. "MINREV,MINREV" newline endif sif (cpuis("STM32MP157*")) hexmask.long.byte 0x0 4.--7. 1. "MAJREV,MAJREV" newline hexmask.long.byte 0x0 0.--3. 1. "MINREV,MINREV" endif line.long 0x4 "SYSCFG_IPIDR,SYSCFG identification register" sif (cpuis("STM32MP13*")) hexmask.long 0x4 0.--31. 1. "ID,SYSCFG identifier" newline endif sif (cpuis("STM32MP151*")) hexmask.long 0x4 0.--31. 1. "ID,ID" newline endif sif (cpuis("STM32MP153*")) hexmask.long 0x4 0.--31. 1. "ID,ID" newline endif sif (cpuis("STM32MP157*")) hexmask.long 0x4 0.--31. 1. "ID,ID" endif line.long 0x8 "SYSCFG_SIDR,SYSCFG size identification register" sif (cpuis("STM32MP13*")) hexmask.long 0x8 0.--31. 1. "SID,Size identification" newline endif sif (cpuis("STM32MP151*")) hexmask.long 0x8 0.--31. 1. "SID,SID" newline endif sif (cpuis("STM32MP153*")) hexmask.long 0x8 0.--31. 1. "SID,SID" newline endif sif (cpuis("STM32MP157*")) hexmask.long 0x8 0.--31. 1. "SID,SID" endif sif (cpuis("STM32MP151*")) rgroup.long 0x3F4++0x3 line.long 0x0 "SYSCFG_VERR,SYSCFG version register" endif sif (cpuis("STM32MP151*")) rgroup.long 0x3F8++0x3 line.long 0x0 "SYSCFG_IPIDR,SYSCFG identification register" endif sif (cpuis("STM32MP151*")) rgroup.long 0x3FC++0x3 line.long 0x0 "SYSCFG_SIDR,SYSCFG size identification register" endif sif (cpuis("STM32MP153*")) rgroup.long 0x3F4++0x3 line.long 0x0 "SYSCFG_VERR,SYSCFG version register" endif sif (cpuis("STM32MP153*")) rgroup.long 0x3F8++0x3 line.long 0x0 "SYSCFG_IPIDR,SYSCFG identification register" endif sif (cpuis("STM32MP153*")) rgroup.long 0x3FC++0x3 line.long 0x0 "SYSCFG_SIDR,SYSCFG size identification register" endif sif (cpuis("STM32MP157*")) rgroup.long 0x3F4++0x3 line.long 0x0 "SYSCFG_VERR,SYSCFG version register" endif sif (cpuis("STM32MP157*")) rgroup.long 0x3F8++0x3 line.long 0x0 "SYSCFG_IPIDR,SYSCFG identification register" endif sif (cpuis("STM32MP157*")) rgroup.long 0x3FC++0x3 line.long 0x0 "SYSCFG_SIDR,SYSCFG size identification register" endif tree.end tree "TAMP (Tamper and Backup)" base ad:0x5C00A000 group.long 0x0++0x7 line.long 0x0 "TAMP_CR1,This register can be protected against non-secure access. Refer to Section51.3.3: TAMP secure protection modes." bitfld.long 0x0 23. "ITAMP8E,ITAMP8E" "0,1" bitfld.long 0x0 20. "ITAMP5E,ITAMP5E" "0,1" bitfld.long 0x0 19. "ITAMP4E,ITAMP4E" "0,1" bitfld.long 0x0 18. "ITAMP3E,ITAMP3E" "0,1" bitfld.long 0x0 17. "ITAMP2E,ITAMP2E" "0,1" bitfld.long 0x0 16. "ITAMP1E,ITAMP1E" "0,1" newline bitfld.long 0x0 2. "TAMP3E,TAMP3E" "0,1" bitfld.long 0x0 1. "TAMP2E,TAMP2E" "0,1" bitfld.long 0x0 0. "TAMP1E,TAMP1E" "0,1" line.long 0x4 "TAMP_CR2,This register can be protected against non-secure access. Refer to Section51.3.3: TAMP secure protection modes." bitfld.long 0x4 26. "TAMP3TRG,TAMP3TRG" "0,1" bitfld.long 0x4 25. "TAMP2TRG,TAMP2TRG" "0,1" bitfld.long 0x4 24. "TAMP1TRG,TAMP1TRG" "0,1" bitfld.long 0x4 18. "TAMP3MSK,TAMP3MSK" "0,1" bitfld.long 0x4 17. "TAMP2MSK,TAMP2MSK" "0,1" bitfld.long 0x4 16. "TAMP1MSK,TAMP1MSK" "0,1" newline bitfld.long 0x4 2. "TAMP3NOER,TAMP3NOER" "0,1" bitfld.long 0x4 1. "TAMP2NOER,TAMP2NOER" "0,1" bitfld.long 0x4 0. "TAMP1NOER,TAMP1NOER" "0,1" group.long 0xC++0x7 line.long 0x0 "TAMP_FLTCR,This register can be protected against non-secure access. Refer to Section51.3.3: TAMP secure protection modes." bitfld.long 0x0 7. "TAMPPUDIS,TAMPPUDIS" "0,1" bitfld.long 0x0 5.--6. "TAMPPRCH,TAMPPRCH" "0,1,2,3" bitfld.long 0x0 3.--4. "TAMPFLT,TAMPFLT" "0,1,2,3" bitfld.long 0x0 0.--2. "TAMPFREQ,TAMPFREQ" "0,1,2,3,4,5,6,7" line.long 0x4 "TAMP_ATCR1,This register can be protected against non-secure access. Refer to Section51.3.3: TAMP secure protection modes." bitfld.long 0x4 31. "FLTEN,FLTEN" "0,1" bitfld.long 0x4 30. "ATOSHARE,ATOSHARE" "0,1" bitfld.long 0x4 24.--26. "ATPER,ATPER" "0,1,2,3,4,5,6,7" bitfld.long 0x4 16.--18. "ATCKSEL,ATCKSEL" "0,1,2,3,4,5,6,7" bitfld.long 0x4 12.--13. "ATOSEL3,ATOSEL3" "0,1,2,3" bitfld.long 0x4 10.--11. "ATOSEL2,ATOSEL2" "0,1,2,3" newline bitfld.long 0x4 8.--9. "ATOSEL1,ATOSEL1" "0,1,2,3" bitfld.long 0x4 2. "TAMP3AM,TAMP3AM" "0,1" bitfld.long 0x4 1. "TAMP2AM,TAMP2AM" "0,1" bitfld.long 0x4 0. "TAMP1AM,TAMP1AM" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "TAMP_ATSEEDR,This register can be protected against non-secure access. Refer to Section51.3.3: TAMP secure protection modes." hexmask.long 0x0 0.--31. 1. "SEED,SEED" rgroup.long 0x18++0x3 line.long 0x0 "TAMP_ATOR,This register can be protected against non-secure access. Refer to Section51.3.3: TAMP secure protection modes." bitfld.long 0x0 15. "INITS,INITS" "0,1" bitfld.long 0x0 14. "SEEDF,SEEDF" "0,1" hexmask.long.byte 0x0 0.--7. 1. "PRNG,PRNG" group.long 0x20++0x3 line.long 0x0 "TAMP_SMCR,This register can be written only when the APB access is secure." bitfld.long 0x0 31. "TAMPDPROT,TAMPDPROT" "0,1" hexmask.long.byte 0x0 16.--23. 1. "BKPWDPROT,BKPWDPROT" hexmask.long.byte 0x0 0.--7. 1. "BKPRWDPROT,BKPRWDPROT" group.long 0x2C++0x3 line.long 0x0 "TAMP_IER,This register can be protected against non-secure access. Refer to Section51.3.3: TAMP secure protection modes." bitfld.long 0x0 23. "ITAMP8IE,ITAMP8IE" "0,1" bitfld.long 0x0 20. "ITAMP5IE,ITAMP5IE" "0,1" bitfld.long 0x0 19. "ITAMP4IE,ITAMP4IE" "0,1" bitfld.long 0x0 18. "ITAMP3IE,ITAMP3IE" "0,1" bitfld.long 0x0 17. "ITAMP2IE,ITAMP2IE" "0,1" bitfld.long 0x0 16. "ITAMP1IE,ITAMP1IE" "0,1" newline bitfld.long 0x0 2. "TAMP3IE,TAMP3IE" "0,1" bitfld.long 0x0 1. "TAMP2IE,TAMP2IE" "0,1" bitfld.long 0x0 0. "TAMP1IE,TAMP1IE" "0,1" rgroup.long 0x30++0xB line.long 0x0 "TAMP_SR,This register can be protected against non-secure access. Refer to Section51.3.3: TAMP secure protection modes." bitfld.long 0x0 23. "ITAMP8F,ITAMP8F" "0,1" bitfld.long 0x0 20. "ITAMP5F,ITAMP5F" "0,1" bitfld.long 0x0 19. "ITAMP4F,ITAMP4F" "0,1" bitfld.long 0x0 18. "ITAMP3F,ITAMP3F" "0,1" bitfld.long 0x0 17. "ITAMP2F,ITAMP2F" "0,1" bitfld.long 0x0 16. "ITAMP1F,ITAMP1F" "0,1" newline bitfld.long 0x0 2. "TAMP3F,TAMP3F" "0,1" bitfld.long 0x0 1. "TAMP2F,TAMP2F" "0,1" bitfld.long 0x0 0. "TAMP1F,TAMP1F" "0,1" line.long 0x4 "TAMP_MISR,TAMP non-secure masked interrupt status register" bitfld.long 0x4 23. "ITAMP8MF,ITAMP8MF" "0,1" bitfld.long 0x4 20. "ITAMP5MF,ITAMP5MF" "0,1" bitfld.long 0x4 19. "ITAMP4MF,ITAMP4MF" "0,1" bitfld.long 0x4 18. "ITAMP3MF,ITAMP3MF" "0,1" bitfld.long 0x4 17. "ITAMP2MF,ITAMP2MF" "0,1" bitfld.long 0x4 16. "ITAMP1MF,ITAMP1MF" "0,1" newline bitfld.long 0x4 2. "TAMP3MF,TAMP3MF" "0,1" bitfld.long 0x4 1. "TAMP2MF,TAMP2MF" "0,1" bitfld.long 0x4 0. "TAMP1MF,TAMP1MF" "0,1" line.long 0x8 "TAMP_SMISR,TAMP secure masked interrupt status register" bitfld.long 0x8 23. "ITAMP8MF,ITAMP8MF" "0,1" bitfld.long 0x8 20. "ITAMP5MF,ITAMP5MF" "0,1" bitfld.long 0x8 19. "ITAMP4MF,ITAMP4MF" "0,1" bitfld.long 0x8 18. "ITAMP3MF,ITAMP3MF" "0,1" bitfld.long 0x8 17. "ITAMP2MF,ITAMP2MF" "0,1" bitfld.long 0x8 16. "ITAMP1MF,ITAMP1MF" "0,1" newline bitfld.long 0x8 2. "TAMP3MF,TAMP3MF" "0,1" bitfld.long 0x8 1. "TAMP2MF,TAMP2MF" "0,1" bitfld.long 0x8 0. "TAMP1MF,TAMP1MF" "0,1" wgroup.long 0x3C++0x3 line.long 0x0 "TAMP_SCR,TAMP status clear register" bitfld.long 0x0 23. "CITAMP8F,CITAMP8F" "0,1" bitfld.long 0x0 20. "CITAMP5F,CITAMP5F" "0,1" bitfld.long 0x0 19. "CITAMP4F,CITAMP4F" "0,1" bitfld.long 0x0 18. "CITAMP3F,CITAMP3F" "0,1" bitfld.long 0x0 17. "CITAMP2F,CITAMP2F" "0,1" bitfld.long 0x0 16. "CITAMP1F,CITAMP1F" "0,1" newline bitfld.long 0x0 2. "CTAMP3F,CTAMP3F" "0,1" bitfld.long 0x0 1. "CTAMP2F,CTAMP2F" "0,1" bitfld.long 0x0 0. "CTAMP1F,CTAMP1F" "0,1" rgroup.long 0x40++0x3 line.long 0x0 "TAMP_COUNTR,TAMP monotonic counter register" hexmask.long 0x0 0.--31. 1. "COUNT,COUNT" group.long 0x50++0x3 line.long 0x0 "TAMP_CFGR,TAMP configuration register" bitfld.long 0x0 0. "OUT3_RMP,OUT3_RMP" "0,1" group.long 0x100++0x7F line.long 0x0 "TAMP_BKP0R,TAMP backup 0 register" hexmask.long 0x0 0.--31. 1. "BKP,BKP" line.long 0x4 "TAMP_BKP1R,TAMP backup 1 register" hexmask.long 0x4 0.--31. 1. "BKP,BKP" line.long 0x8 "TAMP_BKP2R,TAMP backup 2 register" hexmask.long 0x8 0.--31. 1. "BKP,BKP" line.long 0xC "TAMP_BKP3R,TAMP backup 3 register" hexmask.long 0xC 0.--31. 1. "BKP,BKP" line.long 0x10 "TAMP_BKP4R,TAMP backup 4 register" hexmask.long 0x10 0.--31. 1. "BKP,BKP" line.long 0x14 "TAMP_BKP5R,TAMP backup 5 register" hexmask.long 0x14 0.--31. 1. "BKP,BKP" line.long 0x18 "TAMP_BKP6R,TAMP backup 6 register" hexmask.long 0x18 0.--31. 1. "BKP,BKP" line.long 0x1C "TAMP_BKP7R,TAMP backup 7 register" hexmask.long 0x1C 0.--31. 1. "BKP,BKP" line.long 0x20 "TAMP_BKP8R,TAMP backup 8 register" hexmask.long 0x20 0.--31. 1. "BKP,BKP" line.long 0x24 "TAMP_BKP9R,TAMP backup 9 register" hexmask.long 0x24 0.--31. 1. "BKP,BKP" line.long 0x28 "TAMP_BKP10R,TAMP backup 10 register" hexmask.long 0x28 0.--31. 1. "BKP,BKP" line.long 0x2C "TAMP_BKP11R,TAMP backup 11 register" hexmask.long 0x2C 0.--31. 1. "BKP,BKP" line.long 0x30 "TAMP_BKP12R,TAMP backup 12 register" hexmask.long 0x30 0.--31. 1. "BKP,BKP" line.long 0x34 "TAMP_BKP13R,TAMP backup 13 register" hexmask.long 0x34 0.--31. 1. "BKP,BKP" line.long 0x38 "TAMP_BKP14R,TAMP backup 14 register" hexmask.long 0x38 0.--31. 1. "BKP,BKP" line.long 0x3C "TAMP_BKP15R,TAMP backup 15 register" hexmask.long 0x3C 0.--31. 1. "BKP,BKP" line.long 0x40 "TAMP_BKP16R,TAMP backup 16 register" hexmask.long 0x40 0.--31. 1. "BKP,BKP" line.long 0x44 "TAMP_BKP17R,TAMP backup 17 register" hexmask.long 0x44 0.--31. 1. "BKP,BKP" line.long 0x48 "TAMP_BKP18R,TAMP backup 18 register" hexmask.long 0x48 0.--31. 1. "BKP,BKP" line.long 0x4C "TAMP_BKP19R,TAMP backup 19 register" hexmask.long 0x4C 0.--31. 1. "BKP,BKP" line.long 0x50 "TAMP_BKP20R,TAMP backup 20 register" hexmask.long 0x50 0.--31. 1. "BKP,BKP" line.long 0x54 "TAMP_BKP21R,TAMP backup 21 register" hexmask.long 0x54 0.--31. 1. "BKP,BKP" line.long 0x58 "TAMP_BKP22R,TAMP backup 22 register" hexmask.long 0x58 0.--31. 1. "BKP,BKP" line.long 0x5C "TAMP_BKP23R,TAMP backup 23 register" hexmask.long 0x5C 0.--31. 1. "BKP,BKP" line.long 0x60 "TAMP_BKP24R,TAMP backup 24 register" hexmask.long 0x60 0.--31. 1. "BKP,BKP" line.long 0x64 "TAMP_BKP25R,TAMP backup 25 register" hexmask.long 0x64 0.--31. 1. "BKP,BKP" line.long 0x68 "TAMP_BKP26R,TAMP backup 26 register" hexmask.long 0x68 0.--31. 1. "BKP,BKP" line.long 0x6C "TAMP_BKP27R,TAMP backup 27 register" hexmask.long 0x6C 0.--31. 1. "BKP,BKP" line.long 0x70 "TAMP_BKP28R,TAMP backup 28 register" hexmask.long 0x70 0.--31. 1. "BKP,BKP" line.long 0x74 "TAMP_BKP29R,TAMP backup 29 register" hexmask.long 0x74 0.--31. 1. "BKP,BKP" line.long 0x78 "TAMP_BKP30R,TAMP backup 30 register" hexmask.long 0x78 0.--31. 1. "BKP,BKP" line.long 0x7C "TAMP_BKP31R,TAMP backup 31 register" hexmask.long 0x7C 0.--31. 1. "BKP,BKP" rgroup.long 0x3EC++0x13 line.long 0x0 "TAMP_HWCFGR2,TAMP hardware configuration register 2" hexmask.long.byte 0x0 8.--11. 1. "TRUST_ZONE,TRUST_ZONE" hexmask.long.byte 0x0 0.--7. 1. "OPTIONREG_OUT,OPTIONREG_OUT" line.long 0x4 "TAMP_HWCFGR1,TAMP hardware configuration register 1" hexmask.long.word 0x4 16.--31. 1. "INT_TAMPER,INT_TAMPER" hexmask.long.byte 0x4 12.--15. 1. "ACTIVE_TAMPER,ACTIVE_TAMPER" hexmask.long.byte 0x4 8.--11. 1. "TAMPER,TAMPER" hexmask.long.byte 0x4 0.--7. 1. "BACKUP_REGS,BACKUP_REGS" line.long 0x8 "TAMP_VERR,TAMP version register" hexmask.long.byte 0x8 4.--7. 1. "MAJREV,MAJREV" hexmask.long.byte 0x8 0.--3. 1. "MINREV,MINREV" line.long 0xC "TAMP_IPIDR,TAMP identification register" hexmask.long 0xC 0.--31. 1. "ID,ID" line.long 0x10 "TAMP_SIDR,TAMP size identification register" hexmask.long 0x10 0.--31. 1. "SID,SID" tree.end tree "TIM (Timers)" base ad:0x0 sif (cpuis("STM32MP13*")) tree "TIM1" base ad:0x44000000 group.word 0x0++0x1 line.word 0x0 "TIM1_CR1," bitfld.word 0x0 11. "UIFREMAP,UIF status bit remapping" "0: No remapping. UIF status bit is not copied to..,1: Remapping enabled. UIF status bit is copied to.." bitfld.word 0x0 8.--9. "CKD,Clock division" "0: tDTS=tCK_INT,1: tDTS=2*tCK_INT,2: tDTS=4*tCK_INT,3: Reserved do not program this value" newline bitfld.word 0x0 7. "ARPE,Auto-reload preload enable" "0: TIMx_ARR register is not buffered,1: TIMx_ARR register is buffered" bitfld.word 0x0 5.--6. "CMS,Center-aligned mode selection" "0: Edge-aligned mode. The counter counts up or down..,1: Center-aligned mode 1. The counter counts up and..,2: Center-aligned mode 2. The counter counts up and..,3: Center-aligned mode 3. The counter counts up and.." newline bitfld.word 0x0 4. "DIR,Direction" "0: Counter used as upcounter,1: Counter used as downcounter" bitfld.word 0x0 3. "OPM,One pulse mode" "0: Counter is not stopped at update event,1: Counter stops counting at the next update event.." newline bitfld.word 0x0 2. "URS,Update request source" "0: Any of the following events generate an update..,1: Only counter overflow/underflow generates an.." bitfld.word 0x0 1. "UDIS,Update disable" "0: UEV enabled. The Update (UEV) event is generated..,1: UEV disabled. The Update event is not generated.." newline bitfld.word 0x0 0. "CEN,Counter enable" "0: Counter disabled,1: Counter enabled" group.long 0x4++0x7 line.long 0x0 "TIM1_CR2," hexmask.long.byte 0x0 20.--23. 1. "MMS2,Master mode selection 2" bitfld.long 0x0 18. "OIS6,Output Idle state 6 (OC6 output)" "0,1" newline bitfld.long 0x0 16. "OIS5,Output Idle state 5 (OC5 output)" "0,1" bitfld.long 0x0 14. "OIS4,Output Idle state 4 (OC4 output)" "0,1" newline bitfld.long 0x0 13. "OIS3N,Output Idle state 3 (OC3N output)" "0,1" bitfld.long 0x0 12. "OIS3,Output Idle state 3 (OC3 output)" "0,1" newline bitfld.long 0x0 11. "OIS2N,Output Idle state 2 (OC2N output)" "0,1" bitfld.long 0x0 10. "OIS2,Output Idle state 2 (OC2 output)" "0,1" newline bitfld.long 0x0 9. "OIS1N,Output Idle state 1 (OC1N output)" "0: OC1N=0 after a dead-time when MOE=0,1: OC1N=1 after a dead-time when MOE=0" bitfld.long 0x0 8. "OIS1,Output Idle state 1 (OC1 output)" "0: OC1=0 (after a dead-time if OC1N is implemented)..,1: OC1=1 (after a dead-time if OC1N is implemented).." newline bitfld.long 0x0 7. "TI1S,TI1 selection" "0: The TIMx_CH1 pin is connected to TI1 input,1: The TIMx_CH1 CH2 and CH3 pins are connected to.." bitfld.long 0x0 4.--6. "MMS,Master mode selection" "0: Reset - the UG bit from the TIMx_EGR register is..,1: Enable - the Counter Enable signal CNT_EN is..,2: Update - The update event is selected as trigger..,3: Compare Pulse - The trigger output send a..,4: Compare - OC1REFC signal is used as trigger..,5: Compare - OC2REFC signal is used as trigger..,6: Compare - OC3REFC signal is used as trigger..,7: Compare - OC4REFC signal is used as trigger.." newline bitfld.long 0x0 3. "CCDS,Capture/compare DMA selection" "0: CCx DMA request sent when CCx event occurs,1: CCx DMA requests sent when update event occurs" bitfld.long 0x0 2. "CCUS,Capture/compare control update selection" "0: When capture/compare control bits are preloaded..,1: When capture/compare control bits are preloaded.." newline bitfld.long 0x0 0. "CCPC,Capture/compare preloaded control" "0: CCxE CCxNE and OCxM bits are not preloaded,1: CCxE CCxNE and OCxM bits are preloaded after.." line.long 0x4 "TIM1_SMCR," bitfld.long 0x4 20.--21. "TS2,Trigger selection" "0,1,2,3" bitfld.long 0x4 16. "SMS2,Slave mode selection" "0,1" newline bitfld.long 0x4 15. "ETP,External trigger polarity" "0: ETR is non-inverted active at high level or..,1: ETR is inverted active at low level or falling.." bitfld.long 0x4 14. "ECE,External clock enable" "0: External clock mode 2 disabled,1: External clock mode 2 enabled. The counter is.." newline bitfld.long 0x4 12.--13. "ETPS,External trigger prescaler" "0: Prescaler OFF,1: ETRP frequency divided by 2,2: ETRP frequency divided by 4,3: ETRP frequency divided by 8" hexmask.long.byte 0x4 8.--11. 1. "ETF,External trigger filter" newline bitfld.long 0x4 7. "MSM,Master/slave mode" "0: No action,1: The effect of an event on the trigger input.." bitfld.long 0x4 4.--6. "TS1,Trigger selection" "0: Internal Trigger 0 (ITR0),1: Internal Trigger 1 (ITR1),2: Internal Trigger 2 (ITR2),3: Internal Trigger 3 (ITR3),4: TI1 Edge Detector (TI1F_ED),5: Filtered Timer Input 1 (TI1FP1),6: Filtered Timer Input 2 (TI2FP2),7: External Trigger input (ETRF)" newline bitfld.long 0x4 0.--2. "SMS1,Slave mode selection" "0,1,2,3,4,5,6,7" group.word 0xC++0x1 line.word 0x0 "TIM1_DIER," bitfld.word 0x0 14. "TDE,Trigger DMA request enable" "0: Trigger DMA request disabled,1: Trigger DMA request enabled" bitfld.word 0x0 13. "COMDE,COM DMA request enable" "0: COM DMA request disabled,1: COM DMA request enabled" newline bitfld.word 0x0 12. "CC4DE,Capture/Compare 4 DMA request enable" "0: CC4 DMA request disabled,1: CC4 DMA request enabled" bitfld.word 0x0 11. "CC3DE,Capture/Compare 3 DMA request enable" "0: CC3 DMA request disabled,1: CC3 DMA request enabled" newline bitfld.word 0x0 10. "CC2DE,Capture/Compare 2 DMA request enable" "0: CC2 DMA request disabled,1: CC2 DMA request enabled" bitfld.word 0x0 9. "CC1DE,Capture/Compare 1 DMA request enable" "0: CC1 DMA request disabled,1: CC1 DMA request enabled" newline bitfld.word 0x0 8. "UDE,Update DMA request enable" "0: Update DMA request disabled,1: Update DMA request enabled" bitfld.word 0x0 7. "BIE,Break interrupt enable" "0: Break interrupt disabled,1: Break interrupt enabled" newline bitfld.word 0x0 6. "TIE,Trigger interrupt enable" "0: Trigger interrupt disabled,1: Trigger interrupt enabled" bitfld.word 0x0 5. "COMIE,COM interrupt enable" "0: COM interrupt disabled,1: COM interrupt enabled" newline bitfld.word 0x0 4. "CC4IE,Capture/Compare 4 interrupt enable" "0: CC4 interrupt disabled,1: CC4 interrupt enabled" bitfld.word 0x0 3. "CC3IE,Capture/Compare 3 interrupt enable" "0: CC3 interrupt disabled,1: CC3 interrupt enabled" newline bitfld.word 0x0 2. "CC2IE,Capture/Compare 2 interrupt enable" "0: CC2 interrupt disabled,1: CC2 interrupt enabled" bitfld.word 0x0 1. "CC1IE,Capture/Compare 1 interrupt enable" "0: CC1 interrupt disabled,1: CC1 interrupt enabled" newline bitfld.word 0x0 0. "UIE,Update interrupt enable" "0: Update interrupt disabled,1: Update interrupt enabled" group.long 0x10++0x3 line.long 0x0 "TIM1_SR," bitfld.long 0x0 17. "CC6IF,Compare 6 interrupt flag" "0,1" bitfld.long 0x0 16. "CC5IF,Compare 5 interrupt flag" "0,1" newline bitfld.long 0x0 13. "SBIF,System Break interrupt flag" "0: No break event occurred.,1: An active level has been detected on the system.." bitfld.long 0x0 12. "CC4OF,Capture/Compare 4 overcapture flag" "0,1" newline bitfld.long 0x0 11. "CC3OF,Capture/Compare 3 overcapture flag" "0,1" bitfld.long 0x0 10. "CC2OF,Capture/Compare 2 overcapture flag" "0,1" newline bitfld.long 0x0 9. "CC1OF,Capture/Compare 1 overcapture flag" "0: No overcapture has been detected.,1: The counter value has been captured in TIMx_CCR1.." bitfld.long 0x0 8. "B2IF,Break 2 interrupt flag" "0: No break event occurred.,1: An active level has been detected on the break 2.." newline bitfld.long 0x0 7. "BIF,Break interrupt flag" "0: No break event occurred.,1: An active level has been detected on the break.." bitfld.long 0x0 6. "TIF,Trigger interrupt flag" "0: No trigger event occurred.,1: Trigger interrupt pending." newline bitfld.long 0x0 5. "COMIF,COM interrupt flag" "0: No COM event occurred.,1: COM interrupt pending." bitfld.long 0x0 4. "CC4IF,Capture/Compare 4 interrupt flag" "0,1" newline bitfld.long 0x0 3. "CC3IF,Capture/Compare 3 interrupt flag" "0,1" bitfld.long 0x0 2. "CC2IF,Capture/Compare 2 interrupt flag" "0,1" newline bitfld.long 0x0 1. "CC1IF,Capture/Compare 1 interrupt flag" "0: No compare match / No input capture occurred,1: A compare match or an input capture occurred." bitfld.long 0x0 0. "UIF,Update interrupt flag" "0: No update occurred.,1: Update interrupt pending. This bit is set by.." wgroup.word 0x14++0x1 line.word 0x0 "TIM1_EGR," bitfld.word 0x0 8. "B2G,Break 2 generation" "0: No action,1: A break 2 event is generated. MOE bit is cleared.." bitfld.word 0x0 7. "BG,Break generation" "0: No action,1: A break event is generated. MOE bit is cleared.." newline bitfld.word 0x0 6. "TG,Trigger generation" "0: No action,1: The TIF flag is set in TIMx_SR register. Related.." bitfld.word 0x0 5. "COMG,Capture/Compare control update generation" "0: No action,1: When CCPC bit is set it allows CCxE CCxNE and.." newline bitfld.word 0x0 4. "CC4G,Capture/Compare 4 generation" "0,1" bitfld.word 0x0 3. "CC3G,Capture/Compare 3 generation" "0,1" newline bitfld.word 0x0 2. "CC2G,Capture/Compare 2 generation" "0,1" bitfld.word 0x0 1. "CC1G,Capture/Compare 1 generation" "0: No action,1: A capture/compare event is generated on channel 1:" newline bitfld.word 0x0 0. "UG,Update generation" "0: No action,1: Reinitialize the counter and generates an update.." group.long 0x18++0x3 line.long 0x0 "TIM1_CCMR1_output,TIM1 capture/compare mode register 1" bitfld.long 0x0 24. "OC2M2,Output Compare 2 mode" "0,1" bitfld.long 0x0 16. "OC1M2,Output Compare 1 mode" "0,1" newline bitfld.long 0x0 15. "OC2CE,Output Compare 2 clear enable" "0,1" bitfld.long 0x0 12.--14. "OC2M1,Output Compare 2 mode" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 11. "OC2PE,Output Compare 2 preload enable" "0,1" bitfld.long 0x0 10. "OC2FE,Output Compare 2 fast enable" "0,1" newline bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2 selection" "0: CC2 channel is configured as output,1: CC2 channel is configured as input IC2 is mapped..,2: CC2 channel is configured as input IC2 is mapped..,3: CC2 channel is configured as input IC2 is mapped.." bitfld.long 0x0 7. "OC1CE,Output Compare 1 clear enable" "0: OC1Ref is not affected by the ETRF input,1: OC1Ref is cleared as soon as a High level is.." newline bitfld.long 0x0 4.--6. "OC1M1,Output Compare 1 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "OC1PE,Output Compare 1 preload enable" "0: Preload register on TIMx_CCR1 disabled.,1: Preload register on TIMx_CCR1 enabled." newline bitfld.long 0x0 2. "OC1FE,Output Compare 1 fast enable" "0: CC1 behaves normally depending on counter and..,1: An active edge on the trigger input acts like a.." bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1 selection" "0: CC1 channel is configured as output,1: CC1 channel is configured as input IC1 is mapped..,2: CC1 channel is configured as input IC1 is mapped..,3: CC1 channel is configured as input IC1 is mapped.." group.long 0x18++0x7 line.long 0x0 "TIM1_CCMR1_input,TIM1 capture/compare mode register 1 [alternate]" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PSC,Input capture 2 prescaler" "0,1,2,3" newline bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2 selection" "0: CC2 channel is configured as output,1: CC2 channel is configured as input IC2 is mapped..,2: CC2 channel is configured as input IC2 is mapped..,3: CC2 channel is configured as input IC2 is mapped.." hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" newline bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0: no prescaler capture is done each time an edge..,1: capture is done once every 2 events,2: capture is done once every 4 events,3: capture is done once every 8 events" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1 Selection" "0: CC1 channel is configured as output,1: CC1 channel is configured as input IC1 is mapped..,2: CC1 channel is configured as input IC1 is mapped..,3: CC1 channel is configured as input IC1 is mapped.." line.long 0x4 "TIM1_CCMR2_output,TIM1 capture/compare mode register 2 [alternate]" bitfld.long 0x4 24. "OC4M2,Output compare 4 mode" "0,1" bitfld.long 0x4 16. "OC3M2,Output compare 3 mode" "0,1" newline bitfld.long 0x4 15. "OC4CE,Output compare 4 clear enable" "0,1" bitfld.long 0x4 12.--14. "OC4M1,Output compare 4 mode" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 11. "OC4PE,Output compare 4 preload enable" "0,1" bitfld.long 0x4 10. "OC4FE,Output compare 4 fast enable" "0,1" newline bitfld.long 0x4 8.--9. "CC4S,Capture/Compare 4 selection" "0: CC4 channel is configured as output,1: CC4 channel is configured as input IC4 is mapped..,2: CC4 channel is configured as input IC4 is mapped..,3: CC4 channel is configured as input IC4 is mapped.." bitfld.long 0x4 7. "OC3CE,Output compare 3 clear enable" "0,1" newline bitfld.long 0x4 4.--6. "OC3M1,Output compare 3 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "OC3PE,Output compare 3 preload enable" "0,1" newline bitfld.long 0x4 2. "OC3FE,Output compare 3 fast enable" "0,1" bitfld.long 0x4 0.--1. "CC3S,Capture/Compare 3 selection" "0: CC3 channel is configured as output,1: CC3 channel is configured as input IC3 is mapped..,2: CC3 channel is configured as input IC3 is mapped..,3: CC3 channel is configured as input IC3 is mapped.." group.long 0x1C++0xB line.long 0x0 "TIM1_CCMR2_input,TIM1 capture/compare mode register 2 [alternate]" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" newline bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4 selection" "0: CC4 channel is configured as output,1: CC4 channel is configured as input IC4 is mapped..,2: CC4 channel is configured as input IC4 is mapped..,3: CC4 channel is configured as input IC4 is mapped.." hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" newline bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/compare 3 selection" "0: CC3 channel is configured as output,1: CC3 channel is configured as input IC3 is mapped..,2: CC3 channel is configured as input IC3 is mapped..,3: CC3 channel is configured as input IC3 is mapped.." line.long 0x4 "TIM1_CCER," bitfld.long 0x4 21. "CC6P,Capture/Compare 6 output polarity" "0,1" bitfld.long 0x4 20. "CC6E,Capture/Compare 6 output enable" "0,1" newline bitfld.long 0x4 17. "CC5P,Capture/Compare 5 output polarity" "0,1" bitfld.long 0x4 16. "CC5E,Capture/Compare 5 output enable" "0,1" newline bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 complementary output polarity" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 4 output polarity" "0,1" newline bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output enable" "0,1" bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 complementary output polarity" "0,1" newline bitfld.long 0x4 10. "CC3NE,Capture/Compare 3 complementary output enable" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output polarity" "0,1" newline bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output enable" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 complementary output polarity" "0,1" newline bitfld.long 0x4 6. "CC2NE,Capture/Compare 2 complementary output enable" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output polarity" "0,1" newline bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output enable" "0,1" bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 complementary output polarity" "0: OC1N active high.,1: OC1N active low." newline bitfld.long 0x4 2. "CC1NE,Capture/Compare 1 complementary output enable" "0: Off - OC1N is not active. OC1N level is then..,1: On - OC1N signal is output on the corresponding.." bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output polarity" "0: The configuration is reserved,1: non-inverted/both edges/ The circuit is.." newline bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output enable" "0: Capture mode disabled / OC1 is not active (see..,1: Capture mode enabled / OC1 signal is output on.." line.long 0x8 "TIM1_CNT," rbitfld.long 0x8 31. "UIFCPY,UIF copy" "0,1" hexmask.long.word 0x8 0.--15. 1. "CNT,Counter value" group.word 0x28++0x1 line.word 0x0 "TIM1_PSC," hexmask.word 0x0 0.--15. 1. "PSC,Prescaler value" group.word 0x2C++0x1 line.word 0x0 "TIM1_ARR," hexmask.word 0x0 0.--15. 1. "ARR,Auto-reload value" group.word 0x30++0x1 line.word 0x0 "TIM1_RCR," hexmask.word 0x0 0.--15. 1. "REP,Repetition counter value" group.word 0x34++0x1 line.word 0x0 "TIM1_CCR1," hexmask.word 0x0 0.--15. 1. "CCR1,Capture/Compare 1 value" group.word 0x38++0x1 line.word 0x0 "TIM1_CCR2," hexmask.word 0x0 0.--15. 1. "CCR2,Capture/Compare 2 value" group.word 0x3C++0x1 line.word 0x0 "TIM1_CCR3," hexmask.word 0x0 0.--15. 1. "CCR3,Capture/Compare value" group.word 0x40++0x1 line.word 0x0 "TIM1_CCR4," hexmask.word 0x0 0.--15. 1. "CCR4,Capture/Compare value" group.long 0x44++0x3 line.long 0x0 "TIM1_BDTR," bitfld.long 0x0 29. "BK2BID,Break2 bidirectional" "0,1" bitfld.long 0x0 28. "BKBID,Break Bidirectional" "0: Break input BRK in input mode,1: Break input BRK in bidirectional mode" newline bitfld.long 0x0 27. "BK2DSRM,Break2 Disarm" "0,1" bitfld.long 0x0 26. "BKDSRM,Break Disarm" "0: Break input BRK is armed,1: Break input BRK is disarmed" newline bitfld.long 0x0 25. "BK2P,Break 2 polarity" "0: Break input BRK2 is active low,1: Break input BRK2 is active high" bitfld.long 0x0 24. "BK2E,Break 2 enable" "0: Break2 function disabled,1: Break2 function enabled" newline hexmask.long.byte 0x0 20.--23. 1. "BK2F,Break 2 filter" hexmask.long.byte 0x0 16.--19. 1. "BKF,Break filter" newline bitfld.long 0x0 15. "MOE,Main output enable" "0: OC and OCN outputs are disabled or forced to..,1: OC and OCN outputs are enabled if their.." bitfld.long 0x0 14. "AOE,Automatic output enable" "0: MOE can be set only by software,1: MOE can be set by software or automatically at.." newline bitfld.long 0x0 13. "BKP,Break polarity" "0: Break input BRK is active low,1: Break input BRK is active high" bitfld.long 0x0 12. "BKE,Break enable" "0: Break function disabled,1: Break function enabled" newline bitfld.long 0x0 11. "OSSR,Off-state selection for Run mode" "0: When inactive OC/OCN outputs are disabled (the..,1: When inactive OC/OCN outputs are enabled with.." bitfld.long 0x0 10. "OSSI,Off-state selection for Idle mode" "0: When inactive OC/OCN outputs are disabled (the..,1: When inactive OC/OCN outputs are first forced.." newline bitfld.long 0x0 8.--9. "LOCK,Lock configuration" "0: LOCK OFF - No bit is write protected.,1: LOCK Level 1 = DTG bits in TIMx_BDTR register..,2: LOCK Level 2 = LOCK Level 1 + CC Polarity bits..,3: LOCK Level 3 = LOCK Level 2 + CC Control bits.." hexmask.long.byte 0x0 0.--7. 1. "DTG,Dead-time generator setup" group.word 0x48++0x1 line.word 0x0 "TIM1_DCR," hexmask.word.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.word.byte 0x0 0.--4. 1. "DBA,DMA base address" group.long 0x4C++0x3 line.long 0x0 "TIM1_DMAR," hexmask.long 0x0 0.--31. 1. "DMAB,DMA register for burst accesses" group.long 0x54++0x7 line.long 0x0 "TIM1_CCMR3,TIM1 capture/compare mode register 3" bitfld.long 0x0 24. "OC6M2,Output compare 6 mode" "0,1" bitfld.long 0x0 16. "OC5M2,Output compare 5 mode" "0,1" newline bitfld.long 0x0 15. "OC6CE,Output compare 6 clear enable" "0,1" bitfld.long 0x0 12.--14. "OC6M1,Output compare 6 mode" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 11. "OC6PE,Output compare 6 preload enable" "0,1" bitfld.long 0x0 10. "OC6FE,Output compare 6 fast enable" "0,1" newline bitfld.long 0x0 7. "OC5CE,Output compare 5 clear enable" "0,1" bitfld.long 0x0 4.--6. "OC5M1,Output compare 5 mode" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3. "OC5PE,Output compare 5 preload enable" "0,1" bitfld.long 0x0 2. "OC5FE,Output compare 5 fast enable" "0,1" line.long 0x4 "TIM1_CCR5," bitfld.long 0x4 31. "GC5C3,Group Channel 5 and Channel 3" "0: No effect of OC5REF on OC3REFC,1: OC3REFC is the logical AND of OC3REFC and OC5REF" bitfld.long 0x4 30. "GC5C2,Group Channel 5 and Channel 2" "0: No effect of OC5REF on OC2REFC,1: OC2REFC is the logical AND of OC2REFC and OC5REF" newline bitfld.long 0x4 29. "GC5C1,Group Channel 5 and Channel 1" "0: No effect of OC5REF on OC1REFC5,1: OC1REFC is the logical AND of OC1REFC and OC5REF" hexmask.long.word 0x4 0.--15. 1. "CCR5,Capture/Compare 5 value" group.word 0x5C++0x1 line.word 0x0 "TIM1_CCR6," hexmask.word 0x0 0.--15. 1. "CCR6,Capture/Compare 6 value" group.long 0x60++0xB line.long 0x0 "TIM1_AF1," hexmask.long.byte 0x0 14.--17. 1. "ETRSEL,ETR source selection" bitfld.long 0x0 9. "BKINP,BRK BKIN input polarity" "0: BKIN input polarity is not inverted (active low..,1: BKIN input polarity is inverted (active high if.." newline bitfld.long 0x0 8. "BKDF1BK0E,BRK dfsdm1_break[0] enable" "0: dfsdm1_break[0] input disabled,1: dfsdm1_break[0] input enabled" bitfld.long 0x0 0. "BKINE,BRK BKIN input enable" "0: BKIN input disabled,1: BKIN input enabled" line.long 0x4 "TIM1_AF2," bitfld.long 0x4 9. "BK2INP,BRK2 BKIN2 input polarity" "0: BKIN2 input polarity is not inverted (active low..,1: BKIN2 input polarity is inverted (active high if.." bitfld.long 0x4 8. "BK2DF1BK1E,BRK2 dfsdm1_break[1] enable" "0: dfsdm1_break[1] input disabled,1: dfsdm1_break[1] input enabled" newline bitfld.long 0x4 0. "BK2INE,BRK2 BKIN input enable" "0: BKIN2 input disabled,1: BKIN2 input enabled" line.long 0x8 "TIM1_TISEL," hexmask.long.byte 0x8 24.--27. 1. "TI4SEL,selects TI4[0] to TI4[15] input" hexmask.long.byte 0x8 16.--19. 1. "TI3SEL,selects TI3[0] to TI3[15] input" newline hexmask.long.byte 0x8 8.--11. 1. "TI2SEL,selects TI2[0] to TI2[15] input" hexmask.long.byte 0x8 0.--3. 1. "TI1SEL,selects TI1[0] to TI1[15] input" tree.end endif sif (cpuis("STM32MP13*")) tree "TIM8" base ad:0x44001000 group.word 0x0++0x1 line.word 0x0 "TIM8_CR1," bitfld.word 0x0 11. "UIFREMAP,UIF status bit remapping" "0: No remapping. UIF status bit is not copied to..,1: Remapping enabled. UIF status bit is copied to.." bitfld.word 0x0 8.--9. "CKD,Clock division" "0: tDTS=tCK_INT,1: tDTS=2*tCK_INT,2: tDTS=4*tCK_INT,3: Reserved do not program this value" newline bitfld.word 0x0 7. "ARPE,Auto-reload preload enable" "0: TIMx_ARR register is not buffered,1: TIMx_ARR register is buffered" bitfld.word 0x0 5.--6. "CMS,Center-aligned mode selection" "0: Edge-aligned mode. The counter counts up or down..,1: Center-aligned mode 1. The counter counts up and..,2: Center-aligned mode 2. The counter counts up and..,3: Center-aligned mode 3. The counter counts up and.." newline bitfld.word 0x0 4. "DIR,Direction" "0: Counter used as upcounter,1: Counter used as downcounter" bitfld.word 0x0 3. "OPM,One pulse mode" "0: Counter is not stopped at update event,1: Counter stops counting at the next update event.." newline bitfld.word 0x0 2. "URS,Update request source" "0: Any of the following events generate an update..,1: Only counter overflow/underflow generates an.." bitfld.word 0x0 1. "UDIS,Update disable" "0: UEV enabled. The Update (UEV) event is generated..,1: UEV disabled. The Update event is not generated.." newline bitfld.word 0x0 0. "CEN,Counter enable" "0: Counter disabled,1: Counter enabled" group.long 0x4++0x7 line.long 0x0 "TIM8_CR2," hexmask.long.byte 0x0 20.--23. 1. "MMS2,Master mode selection 2" bitfld.long 0x0 18. "OIS6,Output Idle state 6 (OC6 output)" "0,1" newline bitfld.long 0x0 16. "OIS5,Output Idle state 5 (OC5 output)" "0,1" bitfld.long 0x0 14. "OIS4,Output Idle state 4 (OC4 output)" "0,1" newline bitfld.long 0x0 13. "OIS3N,Output Idle state 3 (OC3N output)" "0,1" bitfld.long 0x0 12. "OIS3,Output Idle state 3 (OC3 output)" "0,1" newline bitfld.long 0x0 11. "OIS2N,Output Idle state 2 (OC2N output)" "0,1" bitfld.long 0x0 10. "OIS2,Output Idle state 2 (OC2 output)" "0,1" newline bitfld.long 0x0 9. "OIS1N,Output Idle state 1 (OC1N output)" "0: OC1N=0 after a dead-time when MOE=0,1: OC1N=1 after a dead-time when MOE=0" bitfld.long 0x0 8. "OIS1,Output Idle state 1 (OC1 output)" "0: OC1=0 (after a dead-time if OC1N is implemented)..,1: OC1=1 (after a dead-time if OC1N is implemented).." newline bitfld.long 0x0 7. "TI1S,TI1 selection" "0: The TIMx_CH1 pin is connected to TI1 input,1: The TIMx_CH1 CH2 and CH3 pins are connected to.." bitfld.long 0x0 4.--6. "MMS,Master mode selection" "0: Reset - the UG bit from the TIMx_EGR register is..,1: Enable - the Counter Enable signal CNT_EN is..,2: Update - The update event is selected as trigger..,3: Compare Pulse - The trigger output send a..,4: Compare - OC1REFC signal is used as trigger..,5: Compare - OC2REFC signal is used as trigger..,6: Compare - OC3REFC signal is used as trigger..,7: Compare - OC4REFC signal is used as trigger.." newline bitfld.long 0x0 3. "CCDS,Capture/compare DMA selection" "0: CCx DMA request sent when CCx event occurs,1: CCx DMA requests sent when update event occurs" bitfld.long 0x0 2. "CCUS,Capture/compare control update selection" "0: When capture/compare control bits are preloaded..,1: When capture/compare control bits are preloaded.." newline bitfld.long 0x0 0. "CCPC,Capture/compare preloaded control" "0: CCxE CCxNE and OCxM bits are not preloaded,1: CCxE CCxNE and OCxM bits are preloaded after.." line.long 0x4 "TIM8_SMCR," bitfld.long 0x4 20.--21. "TS2,Trigger selection" "0,1,2,3" bitfld.long 0x4 16. "SMS2,Slave mode selection" "0,1" newline bitfld.long 0x4 15. "ETP,External trigger polarity" "0: ETR is non-inverted active at high level or..,1: ETR is inverted active at low level or falling.." bitfld.long 0x4 14. "ECE,External clock enable" "0: External clock mode 2 disabled,1: External clock mode 2 enabled. The counter is.." newline bitfld.long 0x4 12.--13. "ETPS,External trigger prescaler" "0: Prescaler OFF,1: ETRP frequency divided by 2,2: ETRP frequency divided by 4,3: ETRP frequency divided by 8" hexmask.long.byte 0x4 8.--11. 1. "ETF,External trigger filter" newline bitfld.long 0x4 7. "MSM,Master/slave mode" "0: No action,1: The effect of an event on the trigger input.." bitfld.long 0x4 4.--6. "TS1,Trigger selection" "0: Internal Trigger 0 (ITR0),1: Internal Trigger 1 (ITR1),2: Internal Trigger 2 (ITR2),3: Internal Trigger 3 (ITR3),4: TI1 Edge Detector (TI1F_ED),5: Filtered Timer Input 1 (TI1FP1),6: Filtered Timer Input 2 (TI2FP2),7: External Trigger input (ETRF)" newline bitfld.long 0x4 0.--2. "SMS1,Slave mode selection" "0,1,2,3,4,5,6,7" group.word 0xC++0x1 line.word 0x0 "TIM8_DIER," bitfld.word 0x0 14. "TDE,Trigger DMA request enable" "0: Trigger DMA request disabled,1: Trigger DMA request enabled" bitfld.word 0x0 13. "COMDE,COM DMA request enable" "0: COM DMA request disabled,1: COM DMA request enabled" newline bitfld.word 0x0 12. "CC4DE,Capture/Compare 4 DMA request enable" "0: CC4 DMA request disabled,1: CC4 DMA request enabled" bitfld.word 0x0 11. "CC3DE,Capture/Compare 3 DMA request enable" "0: CC3 DMA request disabled,1: CC3 DMA request enabled" newline bitfld.word 0x0 10. "CC2DE,Capture/Compare 2 DMA request enable" "0: CC2 DMA request disabled,1: CC2 DMA request enabled" bitfld.word 0x0 9. "CC1DE,Capture/Compare 1 DMA request enable" "0: CC1 DMA request disabled,1: CC1 DMA request enabled" newline bitfld.word 0x0 8. "UDE,Update DMA request enable" "0: Update DMA request disabled,1: Update DMA request enabled" bitfld.word 0x0 7. "BIE,Break interrupt enable" "0: Break interrupt disabled,1: Break interrupt enabled" newline bitfld.word 0x0 6. "TIE,Trigger interrupt enable" "0: Trigger interrupt disabled,1: Trigger interrupt enabled" bitfld.word 0x0 5. "COMIE,COM interrupt enable" "0: COM interrupt disabled,1: COM interrupt enabled" newline bitfld.word 0x0 4. "CC4IE,Capture/Compare 4 interrupt enable" "0: CC4 interrupt disabled,1: CC4 interrupt enabled" bitfld.word 0x0 3. "CC3IE,Capture/Compare 3 interrupt enable" "0: CC3 interrupt disabled,1: CC3 interrupt enabled" newline bitfld.word 0x0 2. "CC2IE,Capture/Compare 2 interrupt enable" "0: CC2 interrupt disabled,1: CC2 interrupt enabled" bitfld.word 0x0 1. "CC1IE,Capture/Compare 1 interrupt enable" "0: CC1 interrupt disabled,1: CC1 interrupt enabled" newline bitfld.word 0x0 0. "UIE,Update interrupt enable" "0: Update interrupt disabled,1: Update interrupt enabled" group.long 0x10++0x3 line.long 0x0 "TIM8_SR," bitfld.long 0x0 17. "CC6IF,Compare 6 interrupt flag" "0,1" bitfld.long 0x0 16. "CC5IF,Compare 5 interrupt flag" "0,1" newline bitfld.long 0x0 13. "SBIF,System Break interrupt flag" "0: No break event occurred.,1: An active level has been detected on the system.." bitfld.long 0x0 12. "CC4OF,Capture/Compare 4 overcapture flag" "0,1" newline bitfld.long 0x0 11. "CC3OF,Capture/Compare 3 overcapture flag" "0,1" bitfld.long 0x0 10. "CC2OF,Capture/Compare 2 overcapture flag" "0,1" newline bitfld.long 0x0 9. "CC1OF,Capture/Compare 1 overcapture flag" "0: No overcapture has been detected.,1: The counter value has been captured in TIMx_CCR1.." bitfld.long 0x0 8. "B2IF,Break 2 interrupt flag" "0: No break event occurred.,1: An active level has been detected on the break 2.." newline bitfld.long 0x0 7. "BIF,Break interrupt flag" "0: No break event occurred.,1: An active level has been detected on the break.." bitfld.long 0x0 6. "TIF,Trigger interrupt flag" "0: No trigger event occurred.,1: Trigger interrupt pending." newline bitfld.long 0x0 5. "COMIF,COM interrupt flag" "0: No COM event occurred.,1: COM interrupt pending." bitfld.long 0x0 4. "CC4IF,Capture/Compare 4 interrupt flag" "0,1" newline bitfld.long 0x0 3. "CC3IF,Capture/Compare 3 interrupt flag" "0,1" bitfld.long 0x0 2. "CC2IF,Capture/Compare 2 interrupt flag" "0,1" newline bitfld.long 0x0 1. "CC1IF,Capture/Compare 1 interrupt flag" "0: No compare match / No input capture occurred,1: A compare match or an input capture occurred." bitfld.long 0x0 0. "UIF,Update interrupt flag" "0: No update occurred.,1: Update interrupt pending. This bit is set by.." wgroup.word 0x14++0x1 line.word 0x0 "TIM8_EGR," bitfld.word 0x0 8. "B2G,Break 2 generation" "0: No action,1: A break 2 event is generated. MOE bit is cleared.." bitfld.word 0x0 7. "BG,Break generation" "0: No action,1: A break event is generated. MOE bit is cleared.." newline bitfld.word 0x0 6. "TG,Trigger generation" "0: No action,1: The TIF flag is set in TIMx_SR register. Related.." bitfld.word 0x0 5. "COMG,Capture/Compare control update generation" "0: No action,1: When CCPC bit is set it allows CCxE CCxNE and.." newline bitfld.word 0x0 4. "CC4G,Capture/Compare 4 generation" "0,1" bitfld.word 0x0 3. "CC3G,Capture/Compare 3 generation" "0,1" newline bitfld.word 0x0 2. "CC2G,Capture/Compare 2 generation" "0,1" bitfld.word 0x0 1. "CC1G,Capture/Compare 1 generation" "0: No action,1: A capture/compare event is generated on channel 1:" newline bitfld.word 0x0 0. "UG,Update generation" "0: No action,1: Reinitialize the counter and generates an update.." group.long 0x18++0x3 line.long 0x0 "TIM8_CCMR1_input,TIM8 capture/compare mode register 1 [alternate]" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PSC,Input capture 2 prescaler" "0,1,2,3" newline bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2 selection" "0: CC2 channel is configured as output,1: CC2 channel is configured as input IC2 is mapped..,2: CC2 channel is configured as input IC2 is mapped..,3: CC2 channel is configured as input IC2 is mapped.." hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" newline bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0: no prescaler capture is done each time an edge..,1: capture is done once every 2 events,2: capture is done once every 4 events,3: capture is done once every 8 events" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1 Selection" "0: CC1 channel is configured as output,1: CC1 channel is configured as input IC1 is mapped..,2: CC1 channel is configured as input IC1 is mapped..,3: CC1 channel is configured as input IC1 is mapped.." group.long 0x18++0x7 line.long 0x0 "TIM8_CCMR1_output,TIM8 capture/compare mode register 1 [alternate]" bitfld.long 0x0 24. "OC2M2,Output Compare 2 mode" "0,1" bitfld.long 0x0 16. "OC1M2,Output Compare 1 mode" "0: Frozen - The comparison between the output..,1: Set channel 1 to active level on match. OC1REF.." newline bitfld.long 0x0 15. "OC2CE,Output Compare 2 clear enable" "0,1" bitfld.long 0x0 12.--14. "OC2M1,Output Compare 2 mode" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 11. "OC2PE,Output Compare 2 preload enable" "0,1" bitfld.long 0x0 10. "OC2FE,Output Compare 2 fast enable" "0,1" newline bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2 selection" "0: CC2 channel is configured as output,1: CC2 channel is configured as input IC2 is mapped..,2: CC2 channel is configured as input IC2 is mapped..,3: CC2 channel is configured as input IC2 is mapped.." bitfld.long 0x0 7. "OC1CE,Output Compare 1 clear enable" "0: OC1Ref is not affected by the ETRF input,1: OC1Ref is cleared as soon as a High level is.." newline bitfld.long 0x0 4.--6. "OC1M1,Output Compare 1 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "OC1PE,Output Compare 1 preload enable" "0: Preload register on TIMx_CCR1 disabled.,1: Preload register on TIMx_CCR1 enabled." newline bitfld.long 0x0 2. "OC1FE,Output Compare 1 fast enable" "0: CC1 behaves normally depending on counter and..,1: An active edge on the trigger input acts like a.." bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1 selection" "0: CC1 channel is configured as output,1: CC1 channel is configured as input IC1 is mapped..,2: CC1 channel is configured as input IC1 is mapped..,3: CC1 channel is configured as input IC1 is mapped.." line.long 0x4 "TIM8_CCMR2_input,TIM8 capture/compare mode register 2 [alternate]" hexmask.long.byte 0x4 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x4 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" newline bitfld.long 0x4 8.--9. "CC4S,Capture/Compare 4 selection" "0: CC4 channel is configured as output,1: CC4 channel is configured as input IC4 is mapped..,2: CC4 channel is configured as input IC4 is mapped..,3: CC4 channel is configured as input IC4 is mapped.." hexmask.long.byte 0x4 4.--7. 1. "IC3F,Input capture 3 filter" newline bitfld.long 0x4 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x4 0.--1. "CC3S,Capture/compare 3 selection" "0: CC3 channel is configured as output,1: CC3 channel is configured as input IC3 is mapped..,2: CC3 channel is configured as input IC3 is mapped..,3: CC3 channel is configured as input IC3 is mapped.." group.long 0x1C++0xB line.long 0x0 "TIM8_CCMR2_output,TIM8 capture/compare mode register 2 [alternate]" bitfld.long 0x0 24. "OC4M2,Output compare 4 mode" "0,1" bitfld.long 0x0 16. "OC3M2,Output compare 3 mode" "0,1" newline bitfld.long 0x0 15. "OC4CE,Output compare 4 clear enable" "0,1" bitfld.long 0x0 12.--14. "OC4M1,Output compare 4 mode" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 11. "OC4PE,Output compare 4 preload enable" "0,1" bitfld.long 0x0 10. "OC4FE,Output compare 4 fast enable" "0,1" newline bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4 selection" "0: CC4 channel is configured as output,1: CC4 channel is configured as input IC4 is mapped..,2: CC4 channel is configured as input IC4 is mapped..,3: CC4 channel is configured as input IC4 is mapped.." bitfld.long 0x0 7. "OC3CE,Output compare 3 clear enable" "0,1" newline bitfld.long 0x0 4.--6. "OC3M1,Output compare 3 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "OC3PE,Output compare 3 preload enable" "0,1" newline bitfld.long 0x0 2. "OC3FE,Output compare 3 fast enable" "0,1" bitfld.long 0x0 0.--1. "CC3S,Capture/Compare 3 selection" "0: CC3 channel is configured as output,1: CC3 channel is configured as input IC3 is mapped..,2: CC3 channel is configured as input IC3 is mapped..,3: CC3 channel is configured as input IC3 is mapped.." line.long 0x4 "TIM8_CCER," bitfld.long 0x4 21. "CC6P,Capture/Compare 6 output polarity" "0,1" bitfld.long 0x4 20. "CC6E,Capture/Compare 6 output enable" "0,1" newline bitfld.long 0x4 17. "CC5P,Capture/Compare 5 output polarity" "0,1" bitfld.long 0x4 16. "CC5E,Capture/Compare 5 output enable" "0,1" newline bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 complementary output polarity" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 4 output polarity" "0,1" newline bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output enable" "0,1" bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 complementary output polarity" "0,1" newline bitfld.long 0x4 10. "CC3NE,Capture/Compare 3 complementary output enable" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output polarity" "0,1" newline bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output enable" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 complementary output polarity" "0,1" newline bitfld.long 0x4 6. "CC2NE,Capture/Compare 2 complementary output enable" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output polarity" "0,1" newline bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output enable" "0,1" bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 complementary output polarity" "0: OC1N active high.,1: OC1N active low." newline bitfld.long 0x4 2. "CC1NE,Capture/Compare 1 complementary output enable" "0: Off - OC1N is not active. OC1N level is then..,1: On - OC1N signal is output on the corresponding.." bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output polarity" "0: The configuration is reserved,1: non-inverted/both edges/ The circuit is.." newline bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output enable" "0: Capture mode disabled / OC1 is not active (see..,1: Capture mode enabled / OC1 signal is output on.." line.long 0x8 "TIM8_CNT," rbitfld.long 0x8 31. "UIFCPY,UIF copy" "0,1" hexmask.long.word 0x8 0.--15. 1. "CNT,Counter value" group.word 0x28++0x1 line.word 0x0 "TIM8_PSC," hexmask.word 0x0 0.--15. 1. "PSC,Prescaler value" group.word 0x2C++0x1 line.word 0x0 "TIM8_ARR," hexmask.word 0x0 0.--15. 1. "ARR,Auto-reload value" group.word 0x30++0x1 line.word 0x0 "TIM8_RCR," hexmask.word 0x0 0.--15. 1. "REP,Repetition counter value" group.word 0x34++0x1 line.word 0x0 "TIM8_CCR1," hexmask.word 0x0 0.--15. 1. "CCR1,Capture/Compare 1 value" group.word 0x38++0x1 line.word 0x0 "TIM8_CCR2," hexmask.word 0x0 0.--15. 1. "CCR2,Capture/Compare 2 value" group.word 0x3C++0x1 line.word 0x0 "TIM8_CCR3," hexmask.word 0x0 0.--15. 1. "CCR3,Capture/Compare value" group.word 0x40++0x1 line.word 0x0 "TIM8_CCR4," hexmask.word 0x0 0.--15. 1. "CCR4,Capture/Compare value" group.long 0x44++0x3 line.long 0x0 "TIM8_BDTR," bitfld.long 0x0 29. "BK2BID,Break2 bidirectional" "0,1" bitfld.long 0x0 28. "BKBID,Break Bidirectional" "0: Break input BRK in input mode,1: Break input BRK in bidirectional mode" newline bitfld.long 0x0 27. "BK2DSRM,Break2 Disarm" "0,1" bitfld.long 0x0 26. "BKDSRM,Break Disarm" "0: Break input BRK is armed,1: Break input BRK is disarmed" newline bitfld.long 0x0 25. "BK2P,Break 2 polarity" "0: Break input BRK2 is active low,1: Break input BRK2 is active high" bitfld.long 0x0 24. "BK2E,Break 2 enable" "0: Break2 function disabled,1: Break2 function enabled" newline hexmask.long.byte 0x0 20.--23. 1. "BK2F,Break 2 filter" hexmask.long.byte 0x0 16.--19. 1. "BKF,Break filter" newline bitfld.long 0x0 15. "MOE,Main output enable" "0: OC and OCN outputs are disabled or forced to..,1: OC and OCN outputs are enabled if their.." bitfld.long 0x0 14. "AOE,Automatic output enable" "0: MOE can be set only by software,1: MOE can be set by software or automatically at.." newline bitfld.long 0x0 13. "BKP,Break polarity" "0: Break input BRK is active low,1: Break input BRK is active high" bitfld.long 0x0 12. "BKE,Break enable" "0: Break function disabled,1: Break function enabled" newline bitfld.long 0x0 11. "OSSR,Off-state selection for Run mode" "0: When inactive OC/OCN outputs are disabled (the..,1: When inactive OC/OCN outputs are enabled with.." bitfld.long 0x0 10. "OSSI,Off-state selection for Idle mode" "0: When inactive OC/OCN outputs are disabled (the..,1: When inactive OC/OCN outputs are first forced.." newline bitfld.long 0x0 8.--9. "LOCK,Lock configuration" "0: LOCK OFF - No bit is write protected.,1: LOCK Level 1 = DTG bits in TIMx_BDTR register..,2: LOCK Level 2 = LOCK Level 1 + CC Polarity bits..,3: LOCK Level 3 = LOCK Level 2 + CC Control bits.." hexmask.long.byte 0x0 0.--7. 1. "DTG,Dead-time generator setup" group.word 0x48++0x1 line.word 0x0 "TIM8_DCR," hexmask.word.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.word.byte 0x0 0.--4. 1. "DBA,DMA base address" group.long 0x4C++0x3 line.long 0x0 "TIM8_DMAR," hexmask.long 0x0 0.--31. 1. "DMAB,DMA register for burst accesses" group.long 0x54++0x7 line.long 0x0 "TIM8_CCMR3,TIM8 capture/compare mode register 3" bitfld.long 0x0 24. "OC6M2,Output compare 6 mode" "0,1" bitfld.long 0x0 16. "OC5M2,Output compare 5 mode" "0,1" newline bitfld.long 0x0 15. "OC6CE,Output compare 6 clear enable" "0,1" bitfld.long 0x0 12.--14. "OC6M1,Output compare 6 mode" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 11. "OC6PE,Output compare 6 preload enable" "0,1" bitfld.long 0x0 10. "OC6FE,Output compare 6 fast enable" "0,1" newline bitfld.long 0x0 7. "OC5CE,Output compare 5 clear enable" "0,1" bitfld.long 0x0 4.--6. "OC5M1,Output compare 5 mode" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3. "OC5PE,Output compare 5 preload enable" "0,1" bitfld.long 0x0 2. "OC5FE,Output compare 5 fast enable" "0,1" line.long 0x4 "TIM8_CCR5," bitfld.long 0x4 31. "GC5C3,Group Channel 5 and Channel 3" "0: No effect of OC5REF on OC3REFC,1: OC3REFC is the logical AND of OC3REFC and OC5REF" bitfld.long 0x4 30. "GC5C2,Group Channel 5 and Channel 2" "0: No effect of OC5REF on OC2REFC,1: OC2REFC is the logical AND of OC2REFC and OC5REF" newline bitfld.long 0x4 29. "GC5C1,Group Channel 5 and Channel 1" "0: No effect of OC5REF on OC1REFC5,1: OC1REFC is the logical AND of OC1REFC and OC5REF" hexmask.long.word 0x4 0.--15. 1. "CCR5,Capture/Compare 5 value" group.word 0x5C++0x1 line.word 0x0 "TIM8_CCR6," hexmask.word 0x0 0.--15. 1. "CCR6,Capture/Compare 6 value" group.long 0x60++0xB line.long 0x0 "TIM8_AF1," hexmask.long.byte 0x0 14.--17. 1. "ETRSEL,ETR source selection" bitfld.long 0x0 9. "BKINP,BRK BKIN input polarity" "0: BKIN input polarity is not inverted (active low..,1: BKIN input polarity is inverted (active high if.." newline bitfld.long 0x0 8. "BKDF1BK2E,BRK dfsdm1_break[2] enable" "0: dfsdm1_break[2] input disabled,1: dfsdm1_break[2] input enabled" bitfld.long 0x0 0. "BKINE,BRK BKIN input enable" "0: BKIN input disabled,1: BKIN input enabled" line.long 0x4 "TIM8_AF2," bitfld.long 0x4 9. "BK2INP,BRK2 BKIN2 input polarity" "0: BKIN2 input polarity is not inverted (active low..,1: BKIN2 input polarity is inverted (active high if.." bitfld.long 0x4 8. "BK2DF1BK3E,BRK2 dfsdm1_break[3] enable" "0: dfsdm1_break[3] input disabled,1: dfsdm1_break[3] input enabled" newline bitfld.long 0x4 0. "BK2INE,BRK2 BKIN input enable" "0: BKIN2 input disabled,1: BKIN2 input enabled" line.long 0x8 "TIM8_TISEL," hexmask.long.byte 0x8 24.--27. 1. "TI4SEL,selects TI4[0] to TI4[15] input" hexmask.long.byte 0x8 16.--19. 1. "TI3SEL,selects TI3[0] to TI3[15] input" newline hexmask.long.byte 0x8 8.--11. 1. "TI2SEL,selects TI2[0] to TI2[15] input" hexmask.long.byte 0x8 0.--3. 1. "TI1SEL,selects TI1[0] to TI1[15] input" tree.end endif sif (cpuis("STM32MP13*")) tree "TIM2" base ad:0x40000000 group.word 0x0++0x1 line.word 0x0 "TIM2_CR1,TIM2 control register 1" bitfld.word 0x0 11. "UIFREMAP,UIFREMAP" "0,1" bitfld.word 0x0 8.--9. "CKD,CKD" "0,1,2,3" newline bitfld.word 0x0 7. "ARPE,ARPE" "0,1" bitfld.word 0x0 5.--6. "CMS,CMS" "0,1,2,3" newline bitfld.word 0x0 4. "DIR,DIR" "0,1" bitfld.word 0x0 3. "OPM,OPM" "0,1" newline bitfld.word 0x0 2. "URS,URS" "0,1" bitfld.word 0x0 1. "UDIS,UDIS" "0,1" newline bitfld.word 0x0 0. "CEN,CEN" "0,1" group.long 0x4++0x7 line.long 0x0 "TIM2_CR2,TIM2 control register 2" hexmask.long.byte 0x0 20.--23. 1. "MMS2,MMS2" bitfld.long 0x0 18. "OIS6,OIS6" "0,1" newline bitfld.long 0x0 16. "OIS5,OIS5" "0,1" bitfld.long 0x0 14. "OIS4,OIS4" "0,1" newline bitfld.long 0x0 13. "OIS3N,OIS3N" "0,1" bitfld.long 0x0 12. "OIS3,OIS3" "0,1" newline bitfld.long 0x0 11. "OIS2N,OIS2N" "0,1" bitfld.long 0x0 10. "OIS2,OIS2" "0,1" newline bitfld.long 0x0 9. "OIS1N,OIS1N" "0,1" bitfld.long 0x0 8. "OIS1,OIS1" "0,1" newline bitfld.long 0x0 7. "TI1S,TI1S" "0,1" bitfld.long 0x0 4.--6. "MMS,MMS" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3. "CCDS,CCDS" "0,1" bitfld.long 0x0 2. "CCUS,CCUS" "0,1" newline bitfld.long 0x0 0. "CCPC,CCPC" "0,1" line.long 0x4 "TIM2_SMCR,TIM2 slave mode control register" bitfld.long 0x4 21. "TS4,TS4" "0,1" bitfld.long 0x4 20. "TS3,TS3" "0,1" newline bitfld.long 0x4 16. "SMS3,SMS3" "0,1" bitfld.long 0x4 15. "ETP,ETP" "0,1" newline bitfld.long 0x4 14. "ECE,ECE" "0,1" bitfld.long 0x4 12.--13. "ETPS,ETPS" "0,1,2,3" newline hexmask.long.byte 0x4 8.--11. 1. "ETF,ETF" bitfld.long 0x4 7. "MSM,MSM" "0,1" newline bitfld.long 0x4 4.--6. "TS,TS" "0,1,2,3,4,5,6,7" bitfld.long 0x4 0.--2. "SMS,SMS" "0,1,2,3,4,5,6,7" group.word 0xC++0x1 line.word 0x0 "TIM2_DIER,TIM2 DMA/interrupt enable register" bitfld.word 0x0 14. "TDE,TDE" "0,1" bitfld.word 0x0 13. "COMDE,COMDE" "0,1" newline bitfld.word 0x0 12. "CC4DE,CC4DE" "0,1" bitfld.word 0x0 11. "CC3DE,CC3DE" "0,1" newline bitfld.word 0x0 10. "CC2DE,CC2DE" "0,1" bitfld.word 0x0 9. "CC1DE,CC1DE" "0,1" newline bitfld.word 0x0 8. "UDE,UDE" "0,1" bitfld.word 0x0 7. "BIE,BIE" "0,1" newline bitfld.word 0x0 6. "TIE,TIE" "0,1" bitfld.word 0x0 5. "COMIE,COMIE" "0,1" newline bitfld.word 0x0 4. "CC4IE,CC4IE" "0,1" bitfld.word 0x0 3. "CC3IE,CC3IE" "0,1" newline bitfld.word 0x0 2. "CC2IE,CC2IE" "0,1" bitfld.word 0x0 1. "CC1IE,CC1IE" "0,1" newline bitfld.word 0x0 0. "UIE,UIE" "0,1" group.long 0x10++0x3 line.long 0x0 "TIM2_SR,TIM2 status register" bitfld.long 0x0 17. "CC6IF,CC6IF" "0,1" bitfld.long 0x0 16. "CC5IF,CC5IF" "0,1" newline bitfld.long 0x0 13. "SBIF,SBIF" "0,1" bitfld.long 0x0 12. "CC4OF,CC4OF" "0,1" newline bitfld.long 0x0 11. "CC3OF,CC3OF" "0,1" bitfld.long 0x0 10. "CC2OF,CC2OF" "0,1" newline bitfld.long 0x0 9. "CC1OF,CC1OF" "0,1" bitfld.long 0x0 8. "B2IF,B2IF" "0,1" newline bitfld.long 0x0 7. "BIF,BIF" "0,1" bitfld.long 0x0 6. "TIF,TIF" "0,1" newline bitfld.long 0x0 5. "COMIF,COMIF" "0,1" bitfld.long 0x0 4. "CC4IF,CC4IF" "0,1" newline bitfld.long 0x0 3. "CC3IF,CC3IF" "0,1" bitfld.long 0x0 2. "CC2IF,CC2IF" "0,1" newline bitfld.long 0x0 1. "CC1IF,CC1IF" "0,1" bitfld.long 0x0 0. "UIF,UIF" "0,1" wgroup.word 0x14++0x1 line.word 0x0 "TIM2_EGR,TIM2 event generation register" bitfld.word 0x0 8. "B2G,B2G" "0,1" bitfld.word 0x0 7. "BG,BG" "0,1" newline bitfld.word 0x0 6. "TG,TG" "0,1" bitfld.word 0x0 5. "COMG,COMG" "0,1" newline bitfld.word 0x0 4. "CC4G,CC4G" "0,1" bitfld.word 0x0 3. "CC3G,CC3G" "0,1" newline bitfld.word 0x0 2. "CC2G,CC2G" "0,1" bitfld.word 0x0 1. "CC1G,CC1G" "0,1" newline bitfld.word 0x0 0. "UG,UG" "0,1" group.long 0x18++0x3 line.long 0x0 "TIM2_CCMR1_output,The same register can be used for input capture mode (this section) or for output compare mode (next section). The direction of a channel is defined by configuring the corresponding CCxS bits. All the other bits of this register have a.." bitfld.long 0x0 24. "OC2M2,Output compare 2 mode" "0,1" bitfld.long 0x0 16. "OC1M2,Output compare 1 mode" "0: Frozen - The comparison between the output..,1: Set channel 1 to active level on match. OC1REF.." newline bitfld.long 0x0 15. "OC2CE,Output compare 2 clear enable" "0,1" bitfld.long 0x0 12.--14. "OC2M1,Output compare 2 mode" "?,?,?,?,?,?,6: 4,?" newline bitfld.long 0x0 11. "OC2PE,Output compare 2 preload enable" "0,1" bitfld.long 0x0 10. "OC2FE,Output compare 2 fast enable" "0,1" newline bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2 selection" "0: CC2 channel is configured as output,1: CC2 channel is configured as input IC2 is mapped..,2: CC2 channel is configured as input IC2 is mapped..,3: CC2 channel is configured as input IC2 is mapped.." bitfld.long 0x0 7. "OC1CE,Output compare 1 clear enable" "0: OC1Ref is not affected by the ETRF input,1: OC1Ref is cleared as soon as a High level is.." newline bitfld.long 0x0 4.--6. "OC1M1,Output compare 1 mode" "0: Frozen - The comparison between the output..,1: Set channel 1 to active level on match. OC1REF..,2: Set channel 1 to inactive level on match. OC1REF..,3: Toggle - OC1REF toggles when TIMx_CNT=TIMx_CCR1.,4: Force inactive level - OC1REF is forced low.,5: Force active level - OC1REF is forced high.,6: PWM mode 1 - In upcounting channel 1 is active..,7: PWM mode 2 - In upcounting channel 1 is inactive.." bitfld.long 0x0 3. "OC1PE,Output compare 1 preload enable" "0: Preload register on TIMx_CCR1 disabled.,1: Preload register on TIMx_CCR1 enabled." newline bitfld.long 0x0 2. "OC1FE,Output compare 1 fast enable" "0: CC1 behaves normally depending on counter and..,1: An active edge on the trigger input acts like a.." bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1 selection" "0: CC1 channel is configured as output.,1: CC1 channel is configured as input IC1 is mapped..,2: CC1 channel is configured as input IC1 is mapped..,3: CC1 channel is configured as input IC1 is mapped.." group.long 0x18++0x7 line.long 0x0 "TIM2_CCMR1_input,The same register can be used for input capture mode (this section) or for output compare mode (next section). The direction of a channel is defined by configuring the corresponding CCxS bits. All the other bits of this register have a.." hexmask.long.byte 0x0 12.--15. 1. "IC2F,IC2F" bitfld.long 0x0 10.--11. "IC2PSC,IC2PSC" "0,1,2,3" newline bitfld.long 0x0 8.--9. "CC2S,CC2S" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,IC1F" newline bitfld.long 0x0 2.--3. "IC1PSC,IC1PSC" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,CC1S" "0,1,2,3" line.long 0x4 "TIM2_CCMR2_output,The same register can be used for input capture mode (this section) or for output compare mode (next section). The direction of a channel is defined by configuring the corresponding CCxS bits. All the other bits of this register have a.." bitfld.long 0x4 24. "OC4M2,Output compare 4 mode" "0,1" bitfld.long 0x4 16. "OC3M2,Output compare 3 mode" "0,1" newline bitfld.long 0x4 15. "OC4CE,Output compare 4 clear enable" "0,1" bitfld.long 0x4 12.--14. "OC4M1,Output compare 4 mode" "?,?,?,?,?,?,6: 4 in TIMx_CCMR1 register,?" newline bitfld.long 0x4 11. "OC4PE,Output compare 4 preload enable" "0,1" bitfld.long 0x4 10. "OC4FE,Output compare 4 fast enable" "0,1" newline bitfld.long 0x4 8.--9. "CC4S,Capture/Compare 4 selection" "0: CC4 channel is configured as output,1: CC4 channel is configured as input IC4 is mapped..,2: CC4 channel is configured as input IC4 is mapped..,3: CC4 channel is configured as input IC4 is mapped.." bitfld.long 0x4 7. "OC3CE,Output compare 3 clear enable" "0,1" newline bitfld.long 0x4 4.--6. "OC3M1,Output compare 3 mode" "?,?,?,?,?,?,6: 4 in TIMx_CCMR1 register,?" bitfld.long 0x4 3. "OC3PE,Output compare 3 preload enable" "0,1" newline bitfld.long 0x4 2. "OC3FE,Output compare 3 fast enable" "0,1" bitfld.long 0x4 0.--1. "CC3S,Capture/Compare 3 selection" "0: CC3 channel is configured as output,1: CC3 channel is configured as input IC3 is mapped..,2: CC3 channel is configured as input IC3 is mapped..,3: CC3 channel is configured as input IC3 is mapped.." group.long 0x1C++0xB line.long 0x0 "TIM2_CCMR2_intput,The same register can be used for input capture mode (this section) or for output compare mode (next section). The direction of a channel is defined by configuring the corresponding CCxS bits. All the other bits of this register have a.." hexmask.long.byte 0x0 12.--15. 1. "IC4F,IC4F" bitfld.long 0x0 10.--11. "IC4PSC,IC4PSC" "0,1,2,3" newline bitfld.long 0x0 8.--9. "CC4S,CC4S" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,IC3F" newline bitfld.long 0x0 2.--3. "IC3PSC,IC3PSC" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,CC3S" "0,1,2,3" line.long 0x4 "TIM2_CCER,TIM2 capture/compare enable register" bitfld.long 0x4 21. "CC6P,CC6P" "0,1" bitfld.long 0x4 20. "CC6E,CC6E" "0,1" newline bitfld.long 0x4 17. "CC5P,CC5P" "0,1" bitfld.long 0x4 16. "CC5E,CC5E" "0,1" newline bitfld.long 0x4 15. "CC4NP,CC4NP" "0,1" bitfld.long 0x4 13. "CC4P,CC4P" "0,1" newline bitfld.long 0x4 12. "CC4E,CC4E" "0,1" bitfld.long 0x4 11. "CC3NP,CC3NP" "0,1" newline bitfld.long 0x4 10. "CC3NE,CC3NE" "0,1" bitfld.long 0x4 9. "CC3P,CC3P" "0,1" newline bitfld.long 0x4 8. "CC3E,CC3E" "0,1" bitfld.long 0x4 7. "CC2NP,CC2NP" "0,1" newline bitfld.long 0x4 6. "CC2NE,CC2NE" "0,1" bitfld.long 0x4 5. "CC2P,CC2P" "0,1" newline bitfld.long 0x4 4. "CC2E,CC2E" "0,1" bitfld.long 0x4 3. "CC1NP,CC1NP" "0,1" newline bitfld.long 0x4 2. "CC1NE,CC1NE" "0,1" bitfld.long 0x4 1. "CC1P,CC1P" "0,1" newline bitfld.long 0x4 0. "CC1E,CC1E" "0,1" line.long 0x8 "TIM2_CNT,TIM2 counter" rbitfld.long 0x8 31. "UIFCPY,UIFCPY" "0,1" hexmask.long.word 0x8 0.--15. 1. "CNT,CNT" group.word 0x28++0x1 line.word 0x0 "TIM2_PSC,TIM2 prescaler" hexmask.word 0x0 0.--15. 1. "PSC,PSC" group.word 0x2C++0x1 line.word 0x0 "TIM2_ARR,TIM2 auto-reload register" hexmask.word 0x0 0.--15. 1. "ARR,ARR" group.word 0x34++0x1 line.word 0x0 "TIM2_CCR1,TIM2 capture/compare register 1" hexmask.word 0x0 0.--15. 1. "CCR1,CCR1" group.word 0x38++0x1 line.word 0x0 "TIM2_CCR2,TIM2 capture/compare register 2" hexmask.word 0x0 0.--15. 1. "CCR2,CCR2" group.word 0x3C++0x1 line.word 0x0 "TIM2_CCR3,TIM2 capture/compare register 3" hexmask.word 0x0 0.--15. 1. "CCR3,CCR3" group.word 0x40++0x1 line.word 0x0 "TIM2_CCR4,TIM2 capture/compare register 4" hexmask.word 0x0 0.--15. 1. "CCR4,CCR4" group.word 0x48++0x1 line.word 0x0 "TIM2_DCR,TIM2 DMA control register" hexmask.word.byte 0x0 8.--12. 1. "DBL,DBL" hexmask.word.byte 0x0 0.--4. 1. "DBA,DBA" group.long 0x4C++0x3 line.long 0x0 "TIM2_DMAR,TIM2 DMA address for full transfer" hexmask.long 0x0 0.--31. 1. "DMAB,DMAB" group.long 0x60++0x3 line.long 0x0 "TIM2_AF1," hexmask.long.byte 0x0 14.--17. 1. "ETRSEL,ETR source selection" group.long 0x68++0x3 line.long 0x0 "TIM8_TISEL," hexmask.long.byte 0x0 24.--27. 1. "TI4SEL,selects TI4[0] to TI4[15] input" hexmask.long.byte 0x0 16.--19. 1. "TI3SEL,selects TI3[0] to TI3[15] input" newline hexmask.long.byte 0x0 8.--11. 1. "TI2SEL,selects TI2[0] to TI2[15] input" hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,selects TI1[0] to TI1[15] input" tree.end endif sif (cpuis("STM32MP13*")) tree "TIM3" base ad:0x40001000 group.word 0x0++0x1 line.word 0x0 "TIM2_CR1,TIM2 control register 1" bitfld.word 0x0 11. "UIFREMAP,UIFREMAP" "0,1" bitfld.word 0x0 8.--9. "CKD,CKD" "0,1,2,3" newline bitfld.word 0x0 7. "ARPE,ARPE" "0,1" bitfld.word 0x0 5.--6. "CMS,CMS" "0,1,2,3" newline bitfld.word 0x0 4. "DIR,DIR" "0,1" bitfld.word 0x0 3. "OPM,OPM" "0,1" newline bitfld.word 0x0 2. "URS,URS" "0,1" bitfld.word 0x0 1. "UDIS,UDIS" "0,1" newline bitfld.word 0x0 0. "CEN,CEN" "0,1" group.long 0x4++0x7 line.long 0x0 "TIM2_CR2,TIM2 control register 2" hexmask.long.byte 0x0 20.--23. 1. "MMS2,MMS2" bitfld.long 0x0 18. "OIS6,OIS6" "0,1" newline bitfld.long 0x0 16. "OIS5,OIS5" "0,1" bitfld.long 0x0 14. "OIS4,OIS4" "0,1" newline bitfld.long 0x0 13. "OIS3N,OIS3N" "0,1" bitfld.long 0x0 12. "OIS3,OIS3" "0,1" newline bitfld.long 0x0 11. "OIS2N,OIS2N" "0,1" bitfld.long 0x0 10. "OIS2,OIS2" "0,1" newline bitfld.long 0x0 9. "OIS1N,OIS1N" "0,1" bitfld.long 0x0 8. "OIS1,OIS1" "0,1" newline bitfld.long 0x0 7. "TI1S,TI1S" "0,1" bitfld.long 0x0 4.--6. "MMS,MMS" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3. "CCDS,CCDS" "0,1" bitfld.long 0x0 2. "CCUS,CCUS" "0,1" newline bitfld.long 0x0 0. "CCPC,CCPC" "0,1" line.long 0x4 "TIM2_SMCR,TIM2 slave mode control register" bitfld.long 0x4 21. "TS4,TS4" "0,1" bitfld.long 0x4 20. "TS3,TS3" "0,1" newline bitfld.long 0x4 16. "SMS3,SMS3" "0,1" bitfld.long 0x4 15. "ETP,ETP" "0,1" newline bitfld.long 0x4 14. "ECE,ECE" "0,1" bitfld.long 0x4 12.--13. "ETPS,ETPS" "0,1,2,3" newline hexmask.long.byte 0x4 8.--11. 1. "ETF,ETF" bitfld.long 0x4 7. "MSM,MSM" "0,1" newline bitfld.long 0x4 4.--6. "TS,TS" "0,1,2,3,4,5,6,7" bitfld.long 0x4 0.--2. "SMS,SMS" "0,1,2,3,4,5,6,7" group.word 0xC++0x1 line.word 0x0 "TIM2_DIER,TIM2 DMA/interrupt enable register" bitfld.word 0x0 14. "TDE,TDE" "0,1" bitfld.word 0x0 13. "COMDE,COMDE" "0,1" newline bitfld.word 0x0 12. "CC4DE,CC4DE" "0,1" bitfld.word 0x0 11. "CC3DE,CC3DE" "0,1" newline bitfld.word 0x0 10. "CC2DE,CC2DE" "0,1" bitfld.word 0x0 9. "CC1DE,CC1DE" "0,1" newline bitfld.word 0x0 8. "UDE,UDE" "0,1" bitfld.word 0x0 7. "BIE,BIE" "0,1" newline bitfld.word 0x0 6. "TIE,TIE" "0,1" bitfld.word 0x0 5. "COMIE,COMIE" "0,1" newline bitfld.word 0x0 4. "CC4IE,CC4IE" "0,1" bitfld.word 0x0 3. "CC3IE,CC3IE" "0,1" newline bitfld.word 0x0 2. "CC2IE,CC2IE" "0,1" bitfld.word 0x0 1. "CC1IE,CC1IE" "0,1" newline bitfld.word 0x0 0. "UIE,UIE" "0,1" group.long 0x10++0x3 line.long 0x0 "TIM2_SR,TIM2 status register" bitfld.long 0x0 17. "CC6IF,CC6IF" "0,1" bitfld.long 0x0 16. "CC5IF,CC5IF" "0,1" newline bitfld.long 0x0 13. "SBIF,SBIF" "0,1" bitfld.long 0x0 12. "CC4OF,CC4OF" "0,1" newline bitfld.long 0x0 11. "CC3OF,CC3OF" "0,1" bitfld.long 0x0 10. "CC2OF,CC2OF" "0,1" newline bitfld.long 0x0 9. "CC1OF,CC1OF" "0,1" bitfld.long 0x0 8. "B2IF,B2IF" "0,1" newline bitfld.long 0x0 7. "BIF,BIF" "0,1" bitfld.long 0x0 6. "TIF,TIF" "0,1" newline bitfld.long 0x0 5. "COMIF,COMIF" "0,1" bitfld.long 0x0 4. "CC4IF,CC4IF" "0,1" newline bitfld.long 0x0 3. "CC3IF,CC3IF" "0,1" bitfld.long 0x0 2. "CC2IF,CC2IF" "0,1" newline bitfld.long 0x0 1. "CC1IF,CC1IF" "0,1" bitfld.long 0x0 0. "UIF,UIF" "0,1" wgroup.word 0x14++0x1 line.word 0x0 "TIM2_EGR,TIM2 event generation register" bitfld.word 0x0 8. "B2G,B2G" "0,1" bitfld.word 0x0 7. "BG,BG" "0,1" newline bitfld.word 0x0 6. "TG,TG" "0,1" bitfld.word 0x0 5. "COMG,COMG" "0,1" newline bitfld.word 0x0 4. "CC4G,CC4G" "0,1" bitfld.word 0x0 3. "CC3G,CC3G" "0,1" newline bitfld.word 0x0 2. "CC2G,CC2G" "0,1" bitfld.word 0x0 1. "CC1G,CC1G" "0,1" newline bitfld.word 0x0 0. "UG,UG" "0,1" group.long 0x18++0x3 line.long 0x0 "TIM2_CCMR1_output,The same register can be used for input capture mode (this section) or for output compare mode (next section). The direction of a channel is defined by configuring the corresponding CCxS bits. All the other bits of this register have a.." bitfld.long 0x0 24. "OC2M2,Output compare 2 mode" "0,1" bitfld.long 0x0 16. "OC1M2,Output compare 1 mode" "0: Frozen - The comparison between the output..,1: Set channel 1 to active level on match. OC1REF.." newline bitfld.long 0x0 15. "OC2CE,Output compare 2 clear enable" "0,1" bitfld.long 0x0 12.--14. "OC2M1,Output compare 2 mode" "?,?,?,?,?,?,6: 4,?" newline bitfld.long 0x0 11. "OC2PE,Output compare 2 preload enable" "0,1" bitfld.long 0x0 10. "OC2FE,Output compare 2 fast enable" "0,1" newline bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2 selection" "0: CC2 channel is configured as output,1: CC2 channel is configured as input IC2 is mapped..,2: CC2 channel is configured as input IC2 is mapped..,3: CC2 channel is configured as input IC2 is mapped.." bitfld.long 0x0 7. "OC1CE,Output compare 1 clear enable" "0: OC1Ref is not affected by the ETRF input,1: OC1Ref is cleared as soon as a High level is.." newline bitfld.long 0x0 4.--6. "OC1M1,Output compare 1 mode" "0: Frozen - The comparison between the output..,1: Set channel 1 to active level on match. OC1REF..,2: Set channel 1 to inactive level on match. OC1REF..,3: Toggle - OC1REF toggles when TIMx_CNT=TIMx_CCR1.,4: Force inactive level - OC1REF is forced low.,5: Force active level - OC1REF is forced high.,6: PWM mode 1 - In upcounting channel 1 is active..,7: PWM mode 2 - In upcounting channel 1 is inactive.." bitfld.long 0x0 3. "OC1PE,Output compare 1 preload enable" "0: Preload register on TIMx_CCR1 disabled.,1: Preload register on TIMx_CCR1 enabled." newline bitfld.long 0x0 2. "OC1FE,Output compare 1 fast enable" "0: CC1 behaves normally depending on counter and..,1: An active edge on the trigger input acts like a.." bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1 selection" "0: CC1 channel is configured as output.,1: CC1 channel is configured as input IC1 is mapped..,2: CC1 channel is configured as input IC1 is mapped..,3: CC1 channel is configured as input IC1 is mapped.." group.long 0x18++0x7 line.long 0x0 "TIM2_CCMR1_input,The same register can be used for input capture mode (this section) or for output compare mode (next section). The direction of a channel is defined by configuring the corresponding CCxS bits. All the other bits of this register have a.." hexmask.long.byte 0x0 12.--15. 1. "IC2F,IC2F" bitfld.long 0x0 10.--11. "IC2PSC,IC2PSC" "0,1,2,3" newline bitfld.long 0x0 8.--9. "CC2S,CC2S" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,IC1F" newline bitfld.long 0x0 2.--3. "IC1PSC,IC1PSC" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,CC1S" "0,1,2,3" line.long 0x4 "TIM2_CCMR2_output,The same register can be used for input capture mode (this section) or for output compare mode (next section). The direction of a channel is defined by configuring the corresponding CCxS bits. All the other bits of this register have a.." bitfld.long 0x4 24. "OC4M2,Output compare 4 mode" "0,1" bitfld.long 0x4 16. "OC3M2,Output compare 3 mode" "0,1" newline bitfld.long 0x4 15. "OC4CE,Output compare 4 clear enable" "0,1" bitfld.long 0x4 12.--14. "OC4M1,Output compare 4 mode" "?,?,?,?,?,?,6: 4 in TIMx_CCMR1 register,?" newline bitfld.long 0x4 11. "OC4PE,Output compare 4 preload enable" "0,1" bitfld.long 0x4 10. "OC4FE,Output compare 4 fast enable" "0,1" newline bitfld.long 0x4 8.--9. "CC4S,Capture/Compare 4 selection" "0: CC4 channel is configured as output,1: CC4 channel is configured as input IC4 is mapped..,2: CC4 channel is configured as input IC4 is mapped..,3: CC4 channel is configured as input IC4 is mapped.." bitfld.long 0x4 7. "OC3CE,Output compare 3 clear enable" "0,1" newline bitfld.long 0x4 4.--6. "OC3M1,Output compare 3 mode" "?,?,?,?,?,?,6: 4 in TIMx_CCMR1 register,?" bitfld.long 0x4 3. "OC3PE,Output compare 3 preload enable" "0,1" newline bitfld.long 0x4 2. "OC3FE,Output compare 3 fast enable" "0,1" bitfld.long 0x4 0.--1. "CC3S,Capture/Compare 3 selection" "0: CC3 channel is configured as output,1: CC3 channel is configured as input IC3 is mapped..,2: CC3 channel is configured as input IC3 is mapped..,3: CC3 channel is configured as input IC3 is mapped.." group.long 0x1C++0xB line.long 0x0 "TIM2_CCMR2_intput,The same register can be used for input capture mode (this section) or for output compare mode (next section). The direction of a channel is defined by configuring the corresponding CCxS bits. All the other bits of this register have a.." hexmask.long.byte 0x0 12.--15. 1. "IC4F,IC4F" bitfld.long 0x0 10.--11. "IC4PSC,IC4PSC" "0,1,2,3" newline bitfld.long 0x0 8.--9. "CC4S,CC4S" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,IC3F" newline bitfld.long 0x0 2.--3. "IC3PSC,IC3PSC" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,CC3S" "0,1,2,3" line.long 0x4 "TIM2_CCER,TIM2 capture/compare enable register" bitfld.long 0x4 21. "CC6P,CC6P" "0,1" bitfld.long 0x4 20. "CC6E,CC6E" "0,1" newline bitfld.long 0x4 17. "CC5P,CC5P" "0,1" bitfld.long 0x4 16. "CC5E,CC5E" "0,1" newline bitfld.long 0x4 15. "CC4NP,CC4NP" "0,1" bitfld.long 0x4 13. "CC4P,CC4P" "0,1" newline bitfld.long 0x4 12. "CC4E,CC4E" "0,1" bitfld.long 0x4 11. "CC3NP,CC3NP" "0,1" newline bitfld.long 0x4 10. "CC3NE,CC3NE" "0,1" bitfld.long 0x4 9. "CC3P,CC3P" "0,1" newline bitfld.long 0x4 8. "CC3E,CC3E" "0,1" bitfld.long 0x4 7. "CC2NP,CC2NP" "0,1" newline bitfld.long 0x4 6. "CC2NE,CC2NE" "0,1" bitfld.long 0x4 5. "CC2P,CC2P" "0,1" newline bitfld.long 0x4 4. "CC2E,CC2E" "0,1" bitfld.long 0x4 3. "CC1NP,CC1NP" "0,1" newline bitfld.long 0x4 2. "CC1NE,CC1NE" "0,1" bitfld.long 0x4 1. "CC1P,CC1P" "0,1" newline bitfld.long 0x4 0. "CC1E,CC1E" "0,1" line.long 0x8 "TIM2_CNT,TIM2 counter" rbitfld.long 0x8 31. "UIFCPY,UIFCPY" "0,1" hexmask.long.word 0x8 0.--15. 1. "CNT,CNT" group.word 0x28++0x1 line.word 0x0 "TIM2_PSC,TIM2 prescaler" hexmask.word 0x0 0.--15. 1. "PSC,PSC" group.word 0x2C++0x1 line.word 0x0 "TIM2_ARR,TIM2 auto-reload register" hexmask.word 0x0 0.--15. 1. "ARR,ARR" group.word 0x34++0x1 line.word 0x0 "TIM2_CCR1,TIM2 capture/compare register 1" hexmask.word 0x0 0.--15. 1. "CCR1,CCR1" group.word 0x38++0x1 line.word 0x0 "TIM2_CCR2,TIM2 capture/compare register 2" hexmask.word 0x0 0.--15. 1. "CCR2,CCR2" group.word 0x3C++0x1 line.word 0x0 "TIM2_CCR3,TIM2 capture/compare register 3" hexmask.word 0x0 0.--15. 1. "CCR3,CCR3" group.word 0x40++0x1 line.word 0x0 "TIM2_CCR4,TIM2 capture/compare register 4" hexmask.word 0x0 0.--15. 1. "CCR4,CCR4" group.word 0x48++0x1 line.word 0x0 "TIM2_DCR,TIM2 DMA control register" hexmask.word.byte 0x0 8.--12. 1. "DBL,DBL" hexmask.word.byte 0x0 0.--4. 1. "DBA,DBA" group.long 0x4C++0x3 line.long 0x0 "TIM2_DMAR,TIM2 DMA address for full transfer" hexmask.long 0x0 0.--31. 1. "DMAB,DMAB" group.long 0x60++0x3 line.long 0x0 "TIM2_AF1," hexmask.long.byte 0x0 14.--17. 1. "ETRSEL,ETR source selection" group.long 0x68++0x3 line.long 0x0 "TIM8_TISEL," hexmask.long.byte 0x0 24.--27. 1. "TI4SEL,selects TI4[0] to TI4[15] input" hexmask.long.byte 0x0 16.--19. 1. "TI3SEL,selects TI3[0] to TI3[15] input" newline hexmask.long.byte 0x0 8.--11. 1. "TI2SEL,selects TI2[0] to TI2[15] input" hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,selects TI1[0] to TI1[15] input" tree.end endif sif (cpuis("STM32MP13*")) tree "TIM4" base ad:0x40002000 group.word 0x0++0x1 line.word 0x0 "TIM2_CR1,TIM2 control register 1" bitfld.word 0x0 11. "UIFREMAP,UIFREMAP" "0,1" bitfld.word 0x0 8.--9. "CKD,CKD" "0,1,2,3" newline bitfld.word 0x0 7. "ARPE,ARPE" "0,1" bitfld.word 0x0 5.--6. "CMS,CMS" "0,1,2,3" newline bitfld.word 0x0 4. "DIR,DIR" "0,1" bitfld.word 0x0 3. "OPM,OPM" "0,1" newline bitfld.word 0x0 2. "URS,URS" "0,1" bitfld.word 0x0 1. "UDIS,UDIS" "0,1" newline bitfld.word 0x0 0. "CEN,CEN" "0,1" group.long 0x4++0x7 line.long 0x0 "TIM2_CR2,TIM2 control register 2" hexmask.long.byte 0x0 20.--23. 1. "MMS2,MMS2" bitfld.long 0x0 18. "OIS6,OIS6" "0,1" newline bitfld.long 0x0 16. "OIS5,OIS5" "0,1" bitfld.long 0x0 14. "OIS4,OIS4" "0,1" newline bitfld.long 0x0 13. "OIS3N,OIS3N" "0,1" bitfld.long 0x0 12. "OIS3,OIS3" "0,1" newline bitfld.long 0x0 11. "OIS2N,OIS2N" "0,1" bitfld.long 0x0 10. "OIS2,OIS2" "0,1" newline bitfld.long 0x0 9. "OIS1N,OIS1N" "0,1" bitfld.long 0x0 8. "OIS1,OIS1" "0,1" newline bitfld.long 0x0 7. "TI1S,TI1S" "0,1" bitfld.long 0x0 4.--6. "MMS,MMS" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3. "CCDS,CCDS" "0,1" bitfld.long 0x0 2. "CCUS,CCUS" "0,1" newline bitfld.long 0x0 0. "CCPC,CCPC" "0,1" line.long 0x4 "TIM2_SMCR,TIM2 slave mode control register" bitfld.long 0x4 21. "TS4,TS4" "0,1" bitfld.long 0x4 20. "TS3,TS3" "0,1" newline bitfld.long 0x4 16. "SMS3,SMS3" "0,1" bitfld.long 0x4 15. "ETP,ETP" "0,1" newline bitfld.long 0x4 14. "ECE,ECE" "0,1" bitfld.long 0x4 12.--13. "ETPS,ETPS" "0,1,2,3" newline hexmask.long.byte 0x4 8.--11. 1. "ETF,ETF" bitfld.long 0x4 7. "MSM,MSM" "0,1" newline bitfld.long 0x4 4.--6. "TS,TS" "0,1,2,3,4,5,6,7" bitfld.long 0x4 0.--2. "SMS,SMS" "0,1,2,3,4,5,6,7" group.word 0xC++0x1 line.word 0x0 "TIM2_DIER,TIM2 DMA/interrupt enable register" bitfld.word 0x0 14. "TDE,TDE" "0,1" bitfld.word 0x0 13. "COMDE,COMDE" "0,1" newline bitfld.word 0x0 12. "CC4DE,CC4DE" "0,1" bitfld.word 0x0 11. "CC3DE,CC3DE" "0,1" newline bitfld.word 0x0 10. "CC2DE,CC2DE" "0,1" bitfld.word 0x0 9. "CC1DE,CC1DE" "0,1" newline bitfld.word 0x0 8. "UDE,UDE" "0,1" bitfld.word 0x0 7. "BIE,BIE" "0,1" newline bitfld.word 0x0 6. "TIE,TIE" "0,1" bitfld.word 0x0 5. "COMIE,COMIE" "0,1" newline bitfld.word 0x0 4. "CC4IE,CC4IE" "0,1" bitfld.word 0x0 3. "CC3IE,CC3IE" "0,1" newline bitfld.word 0x0 2. "CC2IE,CC2IE" "0,1" bitfld.word 0x0 1. "CC1IE,CC1IE" "0,1" newline bitfld.word 0x0 0. "UIE,UIE" "0,1" group.long 0x10++0x3 line.long 0x0 "TIM2_SR,TIM2 status register" bitfld.long 0x0 17. "CC6IF,CC6IF" "0,1" bitfld.long 0x0 16. "CC5IF,CC5IF" "0,1" newline bitfld.long 0x0 13. "SBIF,SBIF" "0,1" bitfld.long 0x0 12. "CC4OF,CC4OF" "0,1" newline bitfld.long 0x0 11. "CC3OF,CC3OF" "0,1" bitfld.long 0x0 10. "CC2OF,CC2OF" "0,1" newline bitfld.long 0x0 9. "CC1OF,CC1OF" "0,1" bitfld.long 0x0 8. "B2IF,B2IF" "0,1" newline bitfld.long 0x0 7. "BIF,BIF" "0,1" bitfld.long 0x0 6. "TIF,TIF" "0,1" newline bitfld.long 0x0 5. "COMIF,COMIF" "0,1" bitfld.long 0x0 4. "CC4IF,CC4IF" "0,1" newline bitfld.long 0x0 3. "CC3IF,CC3IF" "0,1" bitfld.long 0x0 2. "CC2IF,CC2IF" "0,1" newline bitfld.long 0x0 1. "CC1IF,CC1IF" "0,1" bitfld.long 0x0 0. "UIF,UIF" "0,1" wgroup.word 0x14++0x1 line.word 0x0 "TIM2_EGR,TIM2 event generation register" bitfld.word 0x0 8. "B2G,B2G" "0,1" bitfld.word 0x0 7. "BG,BG" "0,1" newline bitfld.word 0x0 6. "TG,TG" "0,1" bitfld.word 0x0 5. "COMG,COMG" "0,1" newline bitfld.word 0x0 4. "CC4G,CC4G" "0,1" bitfld.word 0x0 3. "CC3G,CC3G" "0,1" newline bitfld.word 0x0 2. "CC2G,CC2G" "0,1" bitfld.word 0x0 1. "CC1G,CC1G" "0,1" newline bitfld.word 0x0 0. "UG,UG" "0,1" group.long 0x18++0x3 line.long 0x0 "TIM2_CCMR1_output,The same register can be used for input capture mode (this section) or for output compare mode (next section). The direction of a channel is defined by configuring the corresponding CCxS bits. All the other bits of this register have a.." bitfld.long 0x0 24. "OC2M2,Output compare 2 mode" "0,1" bitfld.long 0x0 16. "OC1M2,Output compare 1 mode" "0: Frozen - The comparison between the output..,1: Set channel 1 to active level on match. OC1REF.." newline bitfld.long 0x0 15. "OC2CE,Output compare 2 clear enable" "0,1" bitfld.long 0x0 12.--14. "OC2M1,Output compare 2 mode" "?,?,?,?,?,?,6: 4,?" newline bitfld.long 0x0 11. "OC2PE,Output compare 2 preload enable" "0,1" bitfld.long 0x0 10. "OC2FE,Output compare 2 fast enable" "0,1" newline bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2 selection" "0: CC2 channel is configured as output,1: CC2 channel is configured as input IC2 is mapped..,2: CC2 channel is configured as input IC2 is mapped..,3: CC2 channel is configured as input IC2 is mapped.." bitfld.long 0x0 7. "OC1CE,Output compare 1 clear enable" "0: OC1Ref is not affected by the ETRF input,1: OC1Ref is cleared as soon as a High level is.." newline bitfld.long 0x0 4.--6. "OC1M1,Output compare 1 mode" "0: Frozen - The comparison between the output..,1: Set channel 1 to active level on match. OC1REF..,2: Set channel 1 to inactive level on match. OC1REF..,3: Toggle - OC1REF toggles when TIMx_CNT=TIMx_CCR1.,4: Force inactive level - OC1REF is forced low.,5: Force active level - OC1REF is forced high.,6: PWM mode 1 - In upcounting channel 1 is active..,7: PWM mode 2 - In upcounting channel 1 is inactive.." bitfld.long 0x0 3. "OC1PE,Output compare 1 preload enable" "0: Preload register on TIMx_CCR1 disabled.,1: Preload register on TIMx_CCR1 enabled." newline bitfld.long 0x0 2. "OC1FE,Output compare 1 fast enable" "0: CC1 behaves normally depending on counter and..,1: An active edge on the trigger input acts like a.." bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1 selection" "0: CC1 channel is configured as output.,1: CC1 channel is configured as input IC1 is mapped..,2: CC1 channel is configured as input IC1 is mapped..,3: CC1 channel is configured as input IC1 is mapped.." group.long 0x18++0x7 line.long 0x0 "TIM2_CCMR1_input,The same register can be used for input capture mode (this section) or for output compare mode (next section). The direction of a channel is defined by configuring the corresponding CCxS bits. All the other bits of this register have a.." hexmask.long.byte 0x0 12.--15. 1. "IC2F,IC2F" bitfld.long 0x0 10.--11. "IC2PSC,IC2PSC" "0,1,2,3" newline bitfld.long 0x0 8.--9. "CC2S,CC2S" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,IC1F" newline bitfld.long 0x0 2.--3. "IC1PSC,IC1PSC" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,CC1S" "0,1,2,3" line.long 0x4 "TIM2_CCMR2_output,The same register can be used for input capture mode (this section) or for output compare mode (next section). The direction of a channel is defined by configuring the corresponding CCxS bits. All the other bits of this register have a.." bitfld.long 0x4 24. "OC4M2,Output compare 4 mode" "0,1" bitfld.long 0x4 16. "OC3M2,Output compare 3 mode" "0,1" newline bitfld.long 0x4 15. "OC4CE,Output compare 4 clear enable" "0,1" bitfld.long 0x4 12.--14. "OC4M1,Output compare 4 mode" "?,?,?,?,?,?,6: 4 in TIMx_CCMR1 register,?" newline bitfld.long 0x4 11. "OC4PE,Output compare 4 preload enable" "0,1" bitfld.long 0x4 10. "OC4FE,Output compare 4 fast enable" "0,1" newline bitfld.long 0x4 8.--9. "CC4S,Capture/Compare 4 selection" "0: CC4 channel is configured as output,1: CC4 channel is configured as input IC4 is mapped..,2: CC4 channel is configured as input IC4 is mapped..,3: CC4 channel is configured as input IC4 is mapped.." bitfld.long 0x4 7. "OC3CE,Output compare 3 clear enable" "0,1" newline bitfld.long 0x4 4.--6. "OC3M1,Output compare 3 mode" "?,?,?,?,?,?,6: 4 in TIMx_CCMR1 register,?" bitfld.long 0x4 3. "OC3PE,Output compare 3 preload enable" "0,1" newline bitfld.long 0x4 2. "OC3FE,Output compare 3 fast enable" "0,1" bitfld.long 0x4 0.--1. "CC3S,Capture/Compare 3 selection" "0: CC3 channel is configured as output,1: CC3 channel is configured as input IC3 is mapped..,2: CC3 channel is configured as input IC3 is mapped..,3: CC3 channel is configured as input IC3 is mapped.." group.long 0x1C++0xB line.long 0x0 "TIM2_CCMR2_intput,The same register can be used for input capture mode (this section) or for output compare mode (next section). The direction of a channel is defined by configuring the corresponding CCxS bits. All the other bits of this register have a.." hexmask.long.byte 0x0 12.--15. 1. "IC4F,IC4F" bitfld.long 0x0 10.--11. "IC4PSC,IC4PSC" "0,1,2,3" newline bitfld.long 0x0 8.--9. "CC4S,CC4S" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,IC3F" newline bitfld.long 0x0 2.--3. "IC3PSC,IC3PSC" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,CC3S" "0,1,2,3" line.long 0x4 "TIM2_CCER,TIM2 capture/compare enable register" bitfld.long 0x4 21. "CC6P,CC6P" "0,1" bitfld.long 0x4 20. "CC6E,CC6E" "0,1" newline bitfld.long 0x4 17. "CC5P,CC5P" "0,1" bitfld.long 0x4 16. "CC5E,CC5E" "0,1" newline bitfld.long 0x4 15. "CC4NP,CC4NP" "0,1" bitfld.long 0x4 13. "CC4P,CC4P" "0,1" newline bitfld.long 0x4 12. "CC4E,CC4E" "0,1" bitfld.long 0x4 11. "CC3NP,CC3NP" "0,1" newline bitfld.long 0x4 10. "CC3NE,CC3NE" "0,1" bitfld.long 0x4 9. "CC3P,CC3P" "0,1" newline bitfld.long 0x4 8. "CC3E,CC3E" "0,1" bitfld.long 0x4 7. "CC2NP,CC2NP" "0,1" newline bitfld.long 0x4 6. "CC2NE,CC2NE" "0,1" bitfld.long 0x4 5. "CC2P,CC2P" "0,1" newline bitfld.long 0x4 4. "CC2E,CC2E" "0,1" bitfld.long 0x4 3. "CC1NP,CC1NP" "0,1" newline bitfld.long 0x4 2. "CC1NE,CC1NE" "0,1" bitfld.long 0x4 1. "CC1P,CC1P" "0,1" newline bitfld.long 0x4 0. "CC1E,CC1E" "0,1" line.long 0x8 "TIM2_CNT,TIM2 counter" rbitfld.long 0x8 31. "UIFCPY,UIFCPY" "0,1" hexmask.long.word 0x8 0.--15. 1. "CNT,CNT" group.word 0x28++0x1 line.word 0x0 "TIM2_PSC,TIM2 prescaler" hexmask.word 0x0 0.--15. 1. "PSC,PSC" group.word 0x2C++0x1 line.word 0x0 "TIM2_ARR,TIM2 auto-reload register" hexmask.word 0x0 0.--15. 1. "ARR,ARR" group.word 0x34++0x1 line.word 0x0 "TIM2_CCR1,TIM2 capture/compare register 1" hexmask.word 0x0 0.--15. 1. "CCR1,CCR1" group.word 0x38++0x1 line.word 0x0 "TIM2_CCR2,TIM2 capture/compare register 2" hexmask.word 0x0 0.--15. 1. "CCR2,CCR2" group.word 0x3C++0x1 line.word 0x0 "TIM2_CCR3,TIM2 capture/compare register 3" hexmask.word 0x0 0.--15. 1. "CCR3,CCR3" group.word 0x40++0x1 line.word 0x0 "TIM2_CCR4,TIM2 capture/compare register 4" hexmask.word 0x0 0.--15. 1. "CCR4,CCR4" group.word 0x48++0x1 line.word 0x0 "TIM2_DCR,TIM2 DMA control register" hexmask.word.byte 0x0 8.--12. 1. "DBL,DBL" hexmask.word.byte 0x0 0.--4. 1. "DBA,DBA" group.long 0x4C++0x3 line.long 0x0 "TIM2_DMAR,TIM2 DMA address for full transfer" hexmask.long 0x0 0.--31. 1. "DMAB,DMAB" group.long 0x60++0x3 line.long 0x0 "TIM2_AF1," hexmask.long.byte 0x0 14.--17. 1. "ETRSEL,ETR source selection" group.long 0x68++0x3 line.long 0x0 "TIM8_TISEL," hexmask.long.byte 0x0 24.--27. 1. "TI4SEL,selects TI4[0] to TI4[15] input" hexmask.long.byte 0x0 16.--19. 1. "TI3SEL,selects TI3[0] to TI3[15] input" newline hexmask.long.byte 0x0 8.--11. 1. "TI2SEL,selects TI2[0] to TI2[15] input" hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,selects TI1[0] to TI1[15] input" tree.end endif sif (cpuis("STM32MP13*")) tree "TIM5" base ad:0x40003000 group.word 0x0++0x1 line.word 0x0 "TIM2_CR1,TIM2 control register 1" bitfld.word 0x0 11. "UIFREMAP,UIFREMAP" "0,1" bitfld.word 0x0 8.--9. "CKD,CKD" "0,1,2,3" newline bitfld.word 0x0 7. "ARPE,ARPE" "0,1" bitfld.word 0x0 5.--6. "CMS,CMS" "0,1,2,3" newline bitfld.word 0x0 4. "DIR,DIR" "0,1" bitfld.word 0x0 3. "OPM,OPM" "0,1" newline bitfld.word 0x0 2. "URS,URS" "0,1" bitfld.word 0x0 1. "UDIS,UDIS" "0,1" newline bitfld.word 0x0 0. "CEN,CEN" "0,1" group.long 0x4++0x7 line.long 0x0 "TIM2_CR2,TIM2 control register 2" hexmask.long.byte 0x0 20.--23. 1. "MMS2,MMS2" bitfld.long 0x0 18. "OIS6,OIS6" "0,1" newline bitfld.long 0x0 16. "OIS5,OIS5" "0,1" bitfld.long 0x0 14. "OIS4,OIS4" "0,1" newline bitfld.long 0x0 13. "OIS3N,OIS3N" "0,1" bitfld.long 0x0 12. "OIS3,OIS3" "0,1" newline bitfld.long 0x0 11. "OIS2N,OIS2N" "0,1" bitfld.long 0x0 10. "OIS2,OIS2" "0,1" newline bitfld.long 0x0 9. "OIS1N,OIS1N" "0,1" bitfld.long 0x0 8. "OIS1,OIS1" "0,1" newline bitfld.long 0x0 7. "TI1S,TI1S" "0,1" bitfld.long 0x0 4.--6. "MMS,MMS" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3. "CCDS,CCDS" "0,1" bitfld.long 0x0 2. "CCUS,CCUS" "0,1" newline bitfld.long 0x0 0. "CCPC,CCPC" "0,1" line.long 0x4 "TIM2_SMCR,TIM2 slave mode control register" bitfld.long 0x4 21. "TS4,TS4" "0,1" bitfld.long 0x4 20. "TS3,TS3" "0,1" newline bitfld.long 0x4 16. "SMS3,SMS3" "0,1" bitfld.long 0x4 15. "ETP,ETP" "0,1" newline bitfld.long 0x4 14. "ECE,ECE" "0,1" bitfld.long 0x4 12.--13. "ETPS,ETPS" "0,1,2,3" newline hexmask.long.byte 0x4 8.--11. 1. "ETF,ETF" bitfld.long 0x4 7. "MSM,MSM" "0,1" newline bitfld.long 0x4 4.--6. "TS,TS" "0,1,2,3,4,5,6,7" bitfld.long 0x4 0.--2. "SMS,SMS" "0,1,2,3,4,5,6,7" group.word 0xC++0x1 line.word 0x0 "TIM2_DIER,TIM2 DMA/interrupt enable register" bitfld.word 0x0 14. "TDE,TDE" "0,1" bitfld.word 0x0 13. "COMDE,COMDE" "0,1" newline bitfld.word 0x0 12. "CC4DE,CC4DE" "0,1" bitfld.word 0x0 11. "CC3DE,CC3DE" "0,1" newline bitfld.word 0x0 10. "CC2DE,CC2DE" "0,1" bitfld.word 0x0 9. "CC1DE,CC1DE" "0,1" newline bitfld.word 0x0 8. "UDE,UDE" "0,1" bitfld.word 0x0 7. "BIE,BIE" "0,1" newline bitfld.word 0x0 6. "TIE,TIE" "0,1" bitfld.word 0x0 5. "COMIE,COMIE" "0,1" newline bitfld.word 0x0 4. "CC4IE,CC4IE" "0,1" bitfld.word 0x0 3. "CC3IE,CC3IE" "0,1" newline bitfld.word 0x0 2. "CC2IE,CC2IE" "0,1" bitfld.word 0x0 1. "CC1IE,CC1IE" "0,1" newline bitfld.word 0x0 0. "UIE,UIE" "0,1" group.long 0x10++0x3 line.long 0x0 "TIM2_SR,TIM2 status register" bitfld.long 0x0 17. "CC6IF,CC6IF" "0,1" bitfld.long 0x0 16. "CC5IF,CC5IF" "0,1" newline bitfld.long 0x0 13. "SBIF,SBIF" "0,1" bitfld.long 0x0 12. "CC4OF,CC4OF" "0,1" newline bitfld.long 0x0 11. "CC3OF,CC3OF" "0,1" bitfld.long 0x0 10. "CC2OF,CC2OF" "0,1" newline bitfld.long 0x0 9. "CC1OF,CC1OF" "0,1" bitfld.long 0x0 8. "B2IF,B2IF" "0,1" newline bitfld.long 0x0 7. "BIF,BIF" "0,1" bitfld.long 0x0 6. "TIF,TIF" "0,1" newline bitfld.long 0x0 5. "COMIF,COMIF" "0,1" bitfld.long 0x0 4. "CC4IF,CC4IF" "0,1" newline bitfld.long 0x0 3. "CC3IF,CC3IF" "0,1" bitfld.long 0x0 2. "CC2IF,CC2IF" "0,1" newline bitfld.long 0x0 1. "CC1IF,CC1IF" "0,1" bitfld.long 0x0 0. "UIF,UIF" "0,1" wgroup.word 0x14++0x1 line.word 0x0 "TIM2_EGR,TIM2 event generation register" bitfld.word 0x0 8. "B2G,B2G" "0,1" bitfld.word 0x0 7. "BG,BG" "0,1" newline bitfld.word 0x0 6. "TG,TG" "0,1" bitfld.word 0x0 5. "COMG,COMG" "0,1" newline bitfld.word 0x0 4. "CC4G,CC4G" "0,1" bitfld.word 0x0 3. "CC3G,CC3G" "0,1" newline bitfld.word 0x0 2. "CC2G,CC2G" "0,1" bitfld.word 0x0 1. "CC1G,CC1G" "0,1" newline bitfld.word 0x0 0. "UG,UG" "0,1" group.long 0x18++0x3 line.long 0x0 "TIM2_CCMR1_output,The same register can be used for input capture mode (this section) or for output compare mode (next section). The direction of a channel is defined by configuring the corresponding CCxS bits. All the other bits of this register have a.." bitfld.long 0x0 24. "OC2M2,Output compare 2 mode" "0,1" bitfld.long 0x0 16. "OC1M2,Output compare 1 mode" "0: Frozen - The comparison between the output..,1: Set channel 1 to active level on match. OC1REF.." newline bitfld.long 0x0 15. "OC2CE,Output compare 2 clear enable" "0,1" bitfld.long 0x0 12.--14. "OC2M1,Output compare 2 mode" "?,?,?,?,?,?,6: 4,?" newline bitfld.long 0x0 11. "OC2PE,Output compare 2 preload enable" "0,1" bitfld.long 0x0 10. "OC2FE,Output compare 2 fast enable" "0,1" newline bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2 selection" "0: CC2 channel is configured as output,1: CC2 channel is configured as input IC2 is mapped..,2: CC2 channel is configured as input IC2 is mapped..,3: CC2 channel is configured as input IC2 is mapped.." bitfld.long 0x0 7. "OC1CE,Output compare 1 clear enable" "0: OC1Ref is not affected by the ETRF input,1: OC1Ref is cleared as soon as a High level is.." newline bitfld.long 0x0 4.--6. "OC1M1,Output compare 1 mode" "0: Frozen - The comparison between the output..,1: Set channel 1 to active level on match. OC1REF..,2: Set channel 1 to inactive level on match. OC1REF..,3: Toggle - OC1REF toggles when TIMx_CNT=TIMx_CCR1.,4: Force inactive level - OC1REF is forced low.,5: Force active level - OC1REF is forced high.,6: PWM mode 1 - In upcounting channel 1 is active..,7: PWM mode 2 - In upcounting channel 1 is inactive.." bitfld.long 0x0 3. "OC1PE,Output compare 1 preload enable" "0: Preload register on TIMx_CCR1 disabled.,1: Preload register on TIMx_CCR1 enabled." newline bitfld.long 0x0 2. "OC1FE,Output compare 1 fast enable" "0: CC1 behaves normally depending on counter and..,1: An active edge on the trigger input acts like a.." bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1 selection" "0: CC1 channel is configured as output.,1: CC1 channel is configured as input IC1 is mapped..,2: CC1 channel is configured as input IC1 is mapped..,3: CC1 channel is configured as input IC1 is mapped.." group.long 0x18++0x7 line.long 0x0 "TIM2_CCMR1_input,The same register can be used for input capture mode (this section) or for output compare mode (next section). The direction of a channel is defined by configuring the corresponding CCxS bits. All the other bits of this register have a.." hexmask.long.byte 0x0 12.--15. 1. "IC2F,IC2F" bitfld.long 0x0 10.--11. "IC2PSC,IC2PSC" "0,1,2,3" newline bitfld.long 0x0 8.--9. "CC2S,CC2S" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,IC1F" newline bitfld.long 0x0 2.--3. "IC1PSC,IC1PSC" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,CC1S" "0,1,2,3" line.long 0x4 "TIM2_CCMR2_output,The same register can be used for input capture mode (this section) or for output compare mode (next section). The direction of a channel is defined by configuring the corresponding CCxS bits. All the other bits of this register have a.." bitfld.long 0x4 24. "OC4M2,Output compare 4 mode" "0,1" bitfld.long 0x4 16. "OC3M2,Output compare 3 mode" "0,1" newline bitfld.long 0x4 15. "OC4CE,Output compare 4 clear enable" "0,1" bitfld.long 0x4 12.--14. "OC4M1,Output compare 4 mode" "?,?,?,?,?,?,6: 4 in TIMx_CCMR1 register,?" newline bitfld.long 0x4 11. "OC4PE,Output compare 4 preload enable" "0,1" bitfld.long 0x4 10. "OC4FE,Output compare 4 fast enable" "0,1" newline bitfld.long 0x4 8.--9. "CC4S,Capture/Compare 4 selection" "0: CC4 channel is configured as output,1: CC4 channel is configured as input IC4 is mapped..,2: CC4 channel is configured as input IC4 is mapped..,3: CC4 channel is configured as input IC4 is mapped.." bitfld.long 0x4 7. "OC3CE,Output compare 3 clear enable" "0,1" newline bitfld.long 0x4 4.--6. "OC3M1,Output compare 3 mode" "?,?,?,?,?,?,6: 4 in TIMx_CCMR1 register,?" bitfld.long 0x4 3. "OC3PE,Output compare 3 preload enable" "0,1" newline bitfld.long 0x4 2. "OC3FE,Output compare 3 fast enable" "0,1" bitfld.long 0x4 0.--1. "CC3S,Capture/Compare 3 selection" "0: CC3 channel is configured as output,1: CC3 channel is configured as input IC3 is mapped..,2: CC3 channel is configured as input IC3 is mapped..,3: CC3 channel is configured as input IC3 is mapped.." group.long 0x1C++0xB line.long 0x0 "TIM2_CCMR2_intput,The same register can be used for input capture mode (this section) or for output compare mode (next section). The direction of a channel is defined by configuring the corresponding CCxS bits. All the other bits of this register have a.." hexmask.long.byte 0x0 12.--15. 1. "IC4F,IC4F" bitfld.long 0x0 10.--11. "IC4PSC,IC4PSC" "0,1,2,3" newline bitfld.long 0x0 8.--9. "CC4S,CC4S" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,IC3F" newline bitfld.long 0x0 2.--3. "IC3PSC,IC3PSC" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,CC3S" "0,1,2,3" line.long 0x4 "TIM2_CCER,TIM2 capture/compare enable register" bitfld.long 0x4 21. "CC6P,CC6P" "0,1" bitfld.long 0x4 20. "CC6E,CC6E" "0,1" newline bitfld.long 0x4 17. "CC5P,CC5P" "0,1" bitfld.long 0x4 16. "CC5E,CC5E" "0,1" newline bitfld.long 0x4 15. "CC4NP,CC4NP" "0,1" bitfld.long 0x4 13. "CC4P,CC4P" "0,1" newline bitfld.long 0x4 12. "CC4E,CC4E" "0,1" bitfld.long 0x4 11. "CC3NP,CC3NP" "0,1" newline bitfld.long 0x4 10. "CC3NE,CC3NE" "0,1" bitfld.long 0x4 9. "CC3P,CC3P" "0,1" newline bitfld.long 0x4 8. "CC3E,CC3E" "0,1" bitfld.long 0x4 7. "CC2NP,CC2NP" "0,1" newline bitfld.long 0x4 6. "CC2NE,CC2NE" "0,1" bitfld.long 0x4 5. "CC2P,CC2P" "0,1" newline bitfld.long 0x4 4. "CC2E,CC2E" "0,1" bitfld.long 0x4 3. "CC1NP,CC1NP" "0,1" newline bitfld.long 0x4 2. "CC1NE,CC1NE" "0,1" bitfld.long 0x4 1. "CC1P,CC1P" "0,1" newline bitfld.long 0x4 0. "CC1E,CC1E" "0,1" line.long 0x8 "TIM2_CNT,TIM2 counter" rbitfld.long 0x8 31. "UIFCPY,UIFCPY" "0,1" hexmask.long.word 0x8 0.--15. 1. "CNT,CNT" group.word 0x28++0x1 line.word 0x0 "TIM2_PSC,TIM2 prescaler" hexmask.word 0x0 0.--15. 1. "PSC,PSC" group.word 0x2C++0x1 line.word 0x0 "TIM2_ARR,TIM2 auto-reload register" hexmask.word 0x0 0.--15. 1. "ARR,ARR" group.word 0x34++0x1 line.word 0x0 "TIM2_CCR1,TIM2 capture/compare register 1" hexmask.word 0x0 0.--15. 1. "CCR1,CCR1" group.word 0x38++0x1 line.word 0x0 "TIM2_CCR2,TIM2 capture/compare register 2" hexmask.word 0x0 0.--15. 1. "CCR2,CCR2" group.word 0x3C++0x1 line.word 0x0 "TIM2_CCR3,TIM2 capture/compare register 3" hexmask.word 0x0 0.--15. 1. "CCR3,CCR3" group.word 0x40++0x1 line.word 0x0 "TIM2_CCR4,TIM2 capture/compare register 4" hexmask.word 0x0 0.--15. 1. "CCR4,CCR4" group.word 0x48++0x1 line.word 0x0 "TIM2_DCR,TIM2 DMA control register" hexmask.word.byte 0x0 8.--12. 1. "DBL,DBL" hexmask.word.byte 0x0 0.--4. 1. "DBA,DBA" group.long 0x4C++0x3 line.long 0x0 "TIM2_DMAR,TIM2 DMA address for full transfer" hexmask.long 0x0 0.--31. 1. "DMAB,DMAB" group.long 0x60++0x3 line.long 0x0 "TIM2_AF1," hexmask.long.byte 0x0 14.--17. 1. "ETRSEL,ETR source selection" group.long 0x68++0x3 line.long 0x0 "TIM8_TISEL," hexmask.long.byte 0x0 24.--27. 1. "TI4SEL,selects TI4[0] to TI4[15] input" hexmask.long.byte 0x0 16.--19. 1. "TI3SEL,selects TI3[0] to TI3[15] input" newline hexmask.long.byte 0x0 8.--11. 1. "TI2SEL,selects TI2[0] to TI2[15] input" hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,selects TI1[0] to TI1[15] input" tree.end endif sif (cpuis("STM32MP13*")) tree "TIM6" base ad:0x40004000 group.word 0x0++0x1 line.word 0x0 "TIM6_CR1,TIM6 control register 1" bitfld.word 0x0 11. "UIFREMAP,UIFREMAP" "0,1" bitfld.word 0x0 7. "ARPE,ARPE" "0,1" bitfld.word 0x0 3. "OPM,OPM" "0,1" bitfld.word 0x0 2. "URS,URS" "0,1" bitfld.word 0x0 1. "UDIS,UDIS" "0,1" bitfld.word 0x0 0. "CEN,CEN" "0,1" group.long 0x4++0x3 line.long 0x0 "TIM6_CR2,TIM6 control register 2" bitfld.long 0x0 4.--6. "MMS,MMS" "0,1,2,3,4,5,6,7" group.word 0xC++0x1 line.word 0x0 "TIM6_DIER,TIM6 DMA/interrupt enable register" bitfld.word 0x0 8. "UDE,UDE" "0,1" bitfld.word 0x0 0. "UIE,UIE" "0,1" group.long 0x10++0x3 line.long 0x0 "TIM6_SR,TIM6 status register" bitfld.long 0x0 0. "UIF,UIF" "0,1" wgroup.word 0x14++0x1 line.word 0x0 "TIM6_EGR,TIM6 event generation register" bitfld.word 0x0 0. "UG,UG" "0,1" group.long 0x24++0x3 line.long 0x0 "TIM6_CNT,TIM6 counter" rbitfld.long 0x0 31. "UIFCPY,UIFCPY" "0,1" hexmask.long.word 0x0 0.--15. 1. "CNT,CNT" group.word 0x28++0x1 line.word 0x0 "TIM6_PSC,TIM6 prescaler" hexmask.word 0x0 0.--15. 1. "PSC,PSC" group.word 0x2C++0x1 line.word 0x0 "TIM6_ARR,TIM6 auto-reload register" hexmask.word 0x0 0.--15. 1. "ARR,ARR" tree.end endif sif (cpuis("STM32MP13*")) tree "TIM7" base ad:0x40005000 group.word 0x0++0x1 line.word 0x0 "TIM6_CR1,TIM6 control register 1" bitfld.word 0x0 11. "UIFREMAP,UIFREMAP" "0,1" bitfld.word 0x0 7. "ARPE,ARPE" "0,1" bitfld.word 0x0 3. "OPM,OPM" "0,1" bitfld.word 0x0 2. "URS,URS" "0,1" bitfld.word 0x0 1. "UDIS,UDIS" "0,1" bitfld.word 0x0 0. "CEN,CEN" "0,1" group.long 0x4++0x3 line.long 0x0 "TIM6_CR2,TIM6 control register 2" bitfld.long 0x0 4.--6. "MMS,MMS" "0,1,2,3,4,5,6,7" group.word 0xC++0x1 line.word 0x0 "TIM6_DIER,TIM6 DMA/interrupt enable register" bitfld.word 0x0 8. "UDE,UDE" "0,1" bitfld.word 0x0 0. "UIE,UIE" "0,1" group.long 0x10++0x3 line.long 0x0 "TIM6_SR,TIM6 status register" bitfld.long 0x0 0. "UIF,UIF" "0,1" wgroup.word 0x14++0x1 line.word 0x0 "TIM6_EGR,TIM6 event generation register" bitfld.word 0x0 0. "UG,UG" "0,1" group.long 0x24++0x3 line.long 0x0 "TIM6_CNT,TIM6 counter" rbitfld.long 0x0 31. "UIFCPY,UIFCPY" "0,1" hexmask.long.word 0x0 0.--15. 1. "CNT,CNT" group.word 0x28++0x1 line.word 0x0 "TIM6_PSC,TIM6 prescaler" hexmask.word 0x0 0.--15. 1. "PSC,PSC" group.word 0x2C++0x1 line.word 0x0 "TIM6_ARR,TIM6 auto-reload register" hexmask.word 0x0 0.--15. 1. "ARR,ARR" tree.end endif sif (cpuis("STM32MP13*")) tree "TIM12" base ad:0x4C007000 group.word 0x0++0x1 line.word 0x0 "TIM12_CR1,TIM12 control register 1" bitfld.word 0x0 11. "UIFREMAP,UIF status bit remapping" "0: No remapping. UIF status bit is not copied to..,1: Remapping enabled. UIF status bit is copied to.." bitfld.word 0x0 8.--9. "CKD,Clock division" "0: tDTS = tCK_INT,1: tDTS = 2 × tCK_INT,2: tDTS = 4 × tCK_INT,?" newline bitfld.word 0x0 7. "ARPE,Auto-reload preload enable" "0: TIMx_ARR register is not buffered.,1: TIMx_ARR register is buffered." bitfld.word 0x0 3. "OPM,One-pulse mode" "0: Counter is not stopped on the update event,1: Counter stops counting on the next update event.." newline bitfld.word 0x0 2. "URS,Update request source" "0: Any of the following events generates an update..,1: Only counter overflow generates an update.." bitfld.word 0x0 1. "UDIS,Update disable" "0: UEV enabled. An UEV is generated by one of the..,1: UEV disabled. No UEV is generated shadow.." newline bitfld.word 0x0 0. "CEN,Counter enable" "0: Counter disabled,1: Counter enabled" group.word 0x4++0x1 line.word 0x0 "TIM12_CR2,TIM12 control register 2" bitfld.word 0x0 7. "TI1S,TI1 selection" "0: The TIM12_CH1 pin is connected to TI1 input,1: The TIM12_CH1 CH2 pins are connected to the TI1.." bitfld.word 0x0 4.--6. "MMS,Master mode selection" "0: Reset - the UG bit from the TIMx_EGR register is..,1: Enable - the Counter Enable signal CNT_EN is..,2: Update - The update event is selected as trigger..,3: Compare Pulse - The trigger output send a..,4: Compare - OC1REFC signal is used as trigger..,5: Compare - OC2REFC signal is used as trigger..,?,?" group.long 0x8++0x3 line.long 0x0 "TIM12_SMCR,TIM12 slave mode control register" bitfld.long 0x0 20.--21. "TS2,Trigger selection" "0: Internal Trigger 0 (ITR0),1: Internal Trigger 1 (ITR1),2: Internal Trigger 2 (ITR2),3: Internal Trigger 3 (ITR3)" bitfld.long 0x0 16. "SMS2,Slave mode selection" "0: Slave mode disabled - if CEN = '1’ then the..,?" newline bitfld.long 0x0 7. "MSM,Master/Slave mode" "0: No action,1: The effect of an event on the trigger input.." bitfld.long 0x0 4.--6. "TS1,Trigger selection" "0: Internal Trigger 0 (ITR0),1: Internal Trigger 1 (ITR1),2: Internal Trigger 2 (ITR2),3: Internal Trigger 3 (ITR3),4: TI1 Edge Detector (TI1F_ED),5: Filtered Timer Input 1 (TI1FP1),6: Filtered Timer Input 2 (TI2FP2),?" newline bitfld.long 0x0 0.--2. "SMS1,Slave mode selection" "0: Slave mode disabled - if CEN = '1’ then the..,?,?,?,4: Reset Mode - Rising edge of the selected trigger..,5: Gated Mode - The counter clock is enabled when..,6: Trigger Mode - The counter starts at a rising..,7: External Clock Mode 1 - Rising edges of the.." group.word 0xC++0x1 line.word 0x0 "TIM12_DIER,TIM12 Interrupt enable register" bitfld.word 0x0 6. "TIE,Trigger interrupt enable" "0: Trigger interrupt disabled.,1: Trigger interrupt enabled." bitfld.word 0x0 2. "CC2IE,Capture/Compare 2 interrupt enable" "0: CC2 interrupt disabled.,1: CC2 interrupt enabled." newline bitfld.word 0x0 1. "CC1IE,Capture/Compare 1 interrupt enable" "0: CC1 interrupt disabled.,1: CC1 interrupt enabled." bitfld.word 0x0 0. "UIE,Update interrupt enable" "0: Update interrupt disabled.,1: Update interrupt enabled." group.word 0x10++0x1 line.word 0x0 "TIM12_SR,TIM12 status register" bitfld.word 0x0 10. "CC2OF,Capture/compare 2 overcapture flag" "0,1" bitfld.word 0x0 9. "CC1OF,Capture/Compare 1 overcapture flag" "0: No overcapture has been detected.,1: The counter value has been captured in TIMx_CCR1.." newline bitfld.word 0x0 6. "TIF,Trigger interrupt flag" "0: No trigger event occurred.,1: Trigger interrupt pending." bitfld.word 0x0 2. "CC2IF,Capture/Compare 2 interrupt flag" "0,1" newline bitfld.word 0x0 1. "CC1IF,Capture/compare 1 interrupt flag" "0: No compare match / No input capture occurred,1: A compare match or an input capture occurred." bitfld.word 0x0 0. "UIF,Update interrupt flag" "0: No update occurred.,1: Update interrupt pending. This bit is set by.." wgroup.word 0x14++0x1 line.word 0x0 "TIM12_EGR,TIM12 event generation register" bitfld.word 0x0 6. "TG,Trigger generation" "0: No action,1: The TIF flag is set in the TIMx_SR register." bitfld.word 0x0 2. "CC2G,Capture/compare 2 generation" "0,1" newline bitfld.word 0x0 1. "CC1G,Capture/compare 1 generation" "0: No action,1: A capture/compare event is generated on channel 1:" bitfld.word 0x0 0. "UG,Update generation" "0: No action,1: Re-initializes the counter and generates an.." group.long 0x18++0x3 line.long 0x0 "TIM12_CCMR1_Output,TIM12 capture/compare mode register 1 [alternate]" bitfld.long 0x0 24. "OC2M2,Output compare 2 mode" "0,1" bitfld.long 0x0 16. "OC1M2,Output compare 1 mode (refer to bit 16 for OC1M[3])" "0: Frozen - The comparison between the output..,1: Set channel 1 to active level on match. The.." newline bitfld.long 0x0 12.--14. "OC2M1,Output compare 2 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,Output compare 2 preload enable" "0,1" newline bitfld.long 0x0 10. "OC2FE,Output compare 2 fast enable" "0,1" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2 selection" "0: CC2 channel is configured as output,1: CC2 channel is configured as input IC2 is mapped..,2: CC2 channel is configured as input IC2 is mapped..,3: CC2 channel is configured as input IC2 is mapped.." newline bitfld.long 0x0 4.--6. "OC1M1,Output compare 1 mode (refer to bit 16 for OC1M[3])" "0: Frozen - The comparison between the output..,1: Set channel 1 to active level on match. The..,2: Set channel 1 to inactive level on match. The..,3: Toggle - OC1REF toggles when TIMx_CNT=TIMx_CCR1,4: Force inactive level - OC1REF is forced low,5: Force active level - OC1REF is forced high,6: PWM mode 1 - channel 1 is active as long as..,7: PWM mode 2 - channel 1 is inactive as long as.." bitfld.long 0x0 3. "OC1PE,Output compare 1 preload enable" "0: Preload register on TIMx_CCR1 disabled.,1: Preload register on TIMx_CCR1 enabled." newline bitfld.long 0x0 2. "OC1FE,Output compare 1 fast enable" "0: CC1 behaves normally depending on the counter..,1: An active edge on the trigger input acts like a.." bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1 selection" "0: CC1 channel is configured as output,1: CC1 channel is configured as input IC1 is mapped..,2: CC1 channel is configured as input IC1 is mapped..,3: CC1 channel is configured as input IC1 is mapped.." group.long 0x18++0x3 line.long 0x0 "TIM12_CCMR1_Input,TIM12 capture/compare mode register 1 [alternate]" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PSC,Input capture 2 prescaler" "0,1,2,3" newline bitfld.long 0x0 8.--9. "CC2S,Capture/compare 2 selection" "0: CC2 channel is configured as output,1: CC2 channel is configured as input IC2 is mapped..,2: CC2 channel is configured as input IC2 is mapped..,3: CC2 channel is configured as input IC2 is mapped.." hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" newline bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0: no prescaler capture is done each time an edge..,1: capture is done once every 2 events,2: capture is done once every 4 events,3: capture is done once every 8 events" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1 selection" "0: CC1 channel is configured as output,1: CC1 channel is configured as input IC1 is mapped..,2: CC1 channel is configured as input IC1 is mapped..,3: CC1 channel is configured as input IC1 is mapped.." group.word 0x20++0x1 line.word 0x0 "TIM12_CCER,TIM12 capture/compare enable register" bitfld.word 0x0 7. "CC2NP,Capture/Compare 2 output Polarity" "0,1" bitfld.word 0x0 5. "CC2P,Capture/Compare 2 output Polarity" "0,1" newline bitfld.word 0x0 4. "CC2E,Capture/Compare 2 output enable" "0,1" bitfld.word 0x0 3. "CC1NP,Capture/Compare 1 complementary output Polarity" "0,1" newline bitfld.word 0x0 1. "CC1P,Capture/Compare 1 output Polarity." "0: This configuration is reserved,1: non-inverted/both edges/ The circuit is.." bitfld.word 0x0 0. "CC1E,Capture/Compare 1 output enable." "0: Capture mode disabled / OC1 is not active,1: Capture mode enabled / OC1 signal is output on.." group.long 0x24++0x3 line.long 0x0 "TIM12_CNT,TIM12 counter" bitfld.long 0x0 31. "UIFCPY,UIF Copy" "0,1" hexmask.long.word 0x0 0.--15. 1. "CNT,Counter value" group.word 0x28++0x1 line.word 0x0 "TIM12_PSC,TIM12 prescaler" hexmask.word 0x0 0.--15. 1. "PSC,Prescaler value" group.word 0x2C++0x1 line.word 0x0 "TIM12_ARR,TIM12 auto-reload register" hexmask.word 0x0 0.--15. 1. "ARR,Auto-reload value" group.word 0x34++0x1 line.word 0x0 "TIM12_CCR1,TIM12 capture/compare register 1" hexmask.word 0x0 0.--15. 1. "CCR1,Capture/Compare 1 value" group.word 0x38++0x1 line.word 0x0 "TIM12_CCR2,TIM12 capture/compare register 2" hexmask.word 0x0 0.--15. 1. "CCR2,Capture/Compare 2 value" group.word 0x68++0x1 line.word 0x0 "TIM12_TISEL,TIM12 timer input selection register" hexmask.word.byte 0x0 8.--11. 1. "TI2SEL,selects TI2[0] to TI2[15] input" hexmask.word.byte 0x0 0.--3. 1. "TI1SEL,selects TI1[0] to TI1[15] input" tree.end endif sif (cpuis("STM32MP13*")) tree "TIM13" base ad:0x4C008000 group.word 0x0++0x1 line.word 0x0 "TIM13_CR1,TIM13 control register 1" bitfld.word 0x0 11. "UIFREMAP,UIF status bit remapping" "0: No remapping. UIF status bit is not copied to..,1: Remapping enabled. UIF status bit is copied to.." bitfld.word 0x0 8.--9. "CKD,Clock division" "0: tDTS = tCK_INT,1: tDTS = 2 × tCK_INT,2: tDTS = 4 × tCK_INT,?" newline bitfld.word 0x0 7. "ARPE,Auto-reload preload enable" "0: TIMx_ARR register is not buffered,1: TIMx_ARR register is buffered" bitfld.word 0x0 3. "OPM,One-pulse mode" "0: Counter is not stopped on the update event,1: Counter stops counting on the next update event.." newline bitfld.word 0x0 2. "URS,Update request source" "0: Any of the following events generate an UEV if..,1: Only counter overflow generates an UEV if enabled." bitfld.word 0x0 1. "UDIS,Update disable" "0: UEV enabled. An UEV is generated by one of the..,1: UEV disabled. No UEV is generated shadow.." newline bitfld.word 0x0 0. "CEN,Counter enable" "0: Counter disabled,1: Counter enabled" group.word 0xC++0x1 line.word 0x0 "TIM13_DIER,TIM13 Interrupt enable register" bitfld.word 0x0 1. "CC1IE,Capture/Compare 1 interrupt enable" "0: CC1 interrupt disabled,1: CC1 interrupt enabled" bitfld.word 0x0 0. "UIE,Update interrupt enable" "0: Update interrupt disabled,1: Update interrupt enabled" group.word 0x10++0x1 line.word 0x0 "TIM13_SR,TIM13 status register" bitfld.word 0x0 9. "CC1OF,Capture/Compare 1 overcapture flag" "0: No overcapture has been detected.,1: The counter value has been captured in TIMx_CCR1.." bitfld.word 0x0 1. "CC1IF,Capture/compare 1 interrupt flag" "0: No compare match / No input capture occurred,1: A compare match or an input capture occurred." newline bitfld.word 0x0 0. "UIF,Update interrupt flag" "0: No update occurred.,1: Update interrupt pending. This bit is set by.." wgroup.word 0x14++0x1 line.word 0x0 "TIM13_EGR,TIM13 event generation register" bitfld.word 0x0 1. "CC1G,Capture/compare 1 generation" "0: No action,1: A capture/compare event is generated on channel 1:" bitfld.word 0x0 0. "UG,Update generation" "0: No action,1: Re-initialize the counter and generates an.." group.long 0x18++0x3 line.long 0x0 "TIM13_CCMR1_Output,TIM13 capture/compare mode register 1 [alternate]" bitfld.long 0x0 16. "OC1M2,Output compare 1 mode (refer to bit 16 for OC1M[3])" "0: Frozen. The comparison between the output..,1: Set channel 1 to active level on match. OC1REF.." bitfld.long 0x0 4.--6. "OC1M1,Output compare 1 mode (refer to bit 16 for OC1M[3])" "0: Frozen. The comparison between the output..,1: Set channel 1 to active level on match. OC1REF..,2: Set channel 1 to inactive level on match. OC1REF..,3: Toggle - OC1REF toggles when TIMx_CNT =..,4: Force inactive level - OC1REF is forced low.,5: Force active level - OC1REF is forced high.,6: PWM mode 1 - Channel 1 is active as long as..,7: PWM mode 2 - Channel 1 is inactive as long as.." newline bitfld.long 0x0 3. "OC1PE,Output compare 1 preload enable" "0: Preload register on TIMx_CCR1 disabled.,1: Preload register on TIMx_CCR1 enabled." bitfld.long 0x0 2. "OC1FE,Output compare 1 fast enable" "0: CC1 behaves normally depending on counter and..,1: An active edge on the trigger input acts like a.." newline bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1 selection" "0: CC1 channel is configured as output.,1: CC1 channel is configured as input IC1 is mapped..,?,?" group.long 0x18++0x3 line.long 0x0 "TIM13_CCMR1_Input,TIM13 capture/compare mode register 1 [alternate]" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0: no prescaler capture is done each time an edge..,1: capture is done once every 2 events,2: capture is done once every 4 events,3: capture is done once every 8 events" newline bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1 selection" "0: CC1 channel is configured as output,1: CC1 channel is configured as input IC1 is mapped..,?,?" group.word 0x20++0x1 line.word 0x0 "TIM13_CCER,TIM13 capture/compare enable register" bitfld.word 0x0 3. "CC1NP,Capture/Compare 1 complementary output Polarity." "0,1" bitfld.word 0x0 1. "CC1P,Capture/Compare 1 output Polarity." "0: This configuration is reserved,1: non-inverted/both edges/ The circuit is.." newline bitfld.word 0x0 0. "CC1E,Capture/Compare 1 output enable." "0: Capture mode disabled / OC1 is not active,1: Capture mode enabled / OC1 signal is output on.." group.long 0x24++0x3 line.long 0x0 "TIM13_CNT,TIM13 counter" bitfld.long 0x0 31. "UIFCPY,UIF Copy" "0,1" hexmask.long.word 0x0 0.--15. 1. "CNT,Counter value" group.word 0x28++0x1 line.word 0x0 "TIM13_PSC,TIM13 prescaler" hexmask.word 0x0 0.--15. 1. "PSC,Prescaler value" group.word 0x2C++0x1 line.word 0x0 "TIM13_ARR,TIM13 auto-reload register" hexmask.word 0x0 0.--15. 1. "ARR,Auto-reload value" group.word 0x34++0x1 line.word 0x0 "TIM13_CCR1,TIM13 capture/compare register 1" hexmask.word 0x0 0.--15. 1. "CCR1,Capture/Compare 1 value" group.word 0x68++0x1 line.word 0x0 "TIM13_TISEL,TIM13 timer input selection register" hexmask.word.byte 0x0 0.--3. 1. "TI1SEL,selects TI1[0] to TI1[15] input" tree.end endif sif (cpuis("STM32MP13*")) tree "TIM14" base ad:0x4C009000 group.word 0x0++0x1 line.word 0x0 "TIM13_CR1,TIM13 control register 1" bitfld.word 0x0 11. "UIFREMAP,UIF status bit remapping" "0: No remapping. UIF status bit is not copied to..,1: Remapping enabled. UIF status bit is copied to.." bitfld.word 0x0 8.--9. "CKD,Clock division" "0: tDTS = tCK_INT,1: tDTS = 2 × tCK_INT,2: tDTS = 4 × tCK_INT,?" newline bitfld.word 0x0 7. "ARPE,Auto-reload preload enable" "0: TIMx_ARR register is not buffered,1: TIMx_ARR register is buffered" bitfld.word 0x0 3. "OPM,One-pulse mode" "0: Counter is not stopped on the update event,1: Counter stops counting on the next update event.." newline bitfld.word 0x0 2. "URS,Update request source" "0: Any of the following events generate an UEV if..,1: Only counter overflow generates an UEV if enabled." bitfld.word 0x0 1. "UDIS,Update disable" "0: UEV enabled. An UEV is generated by one of the..,1: UEV disabled. No UEV is generated shadow.." newline bitfld.word 0x0 0. "CEN,Counter enable" "0: Counter disabled,1: Counter enabled" group.word 0xC++0x1 line.word 0x0 "TIM13_DIER,TIM13 Interrupt enable register" bitfld.word 0x0 1. "CC1IE,Capture/Compare 1 interrupt enable" "0: CC1 interrupt disabled,1: CC1 interrupt enabled" bitfld.word 0x0 0. "UIE,Update interrupt enable" "0: Update interrupt disabled,1: Update interrupt enabled" group.word 0x10++0x1 line.word 0x0 "TIM13_SR,TIM13 status register" bitfld.word 0x0 9. "CC1OF,Capture/Compare 1 overcapture flag" "0: No overcapture has been detected.,1: The counter value has been captured in TIMx_CCR1.." bitfld.word 0x0 1. "CC1IF,Capture/compare 1 interrupt flag" "0: No compare match / No input capture occurred,1: A compare match or an input capture occurred." newline bitfld.word 0x0 0. "UIF,Update interrupt flag" "0: No update occurred.,1: Update interrupt pending. This bit is set by.." wgroup.word 0x14++0x1 line.word 0x0 "TIM13_EGR,TIM13 event generation register" bitfld.word 0x0 1. "CC1G,Capture/compare 1 generation" "0: No action,1: A capture/compare event is generated on channel 1:" bitfld.word 0x0 0. "UG,Update generation" "0: No action,1: Re-initialize the counter and generates an.." group.long 0x18++0x3 line.long 0x0 "TIM13_CCMR1_Output,TIM13 capture/compare mode register 1 [alternate]" bitfld.long 0x0 16. "OC1M2,Output compare 1 mode (refer to bit 16 for OC1M[3])" "0: Frozen. The comparison between the output..,1: Set channel 1 to active level on match. OC1REF.." bitfld.long 0x0 4.--6. "OC1M1,Output compare 1 mode (refer to bit 16 for OC1M[3])" "0: Frozen. The comparison between the output..,1: Set channel 1 to active level on match. OC1REF..,2: Set channel 1 to inactive level on match. OC1REF..,3: Toggle - OC1REF toggles when TIMx_CNT =..,4: Force inactive level - OC1REF is forced low.,5: Force active level - OC1REF is forced high.,6: PWM mode 1 - Channel 1 is active as long as..,7: PWM mode 2 - Channel 1 is inactive as long as.." newline bitfld.long 0x0 3. "OC1PE,Output compare 1 preload enable" "0: Preload register on TIMx_CCR1 disabled.,1: Preload register on TIMx_CCR1 enabled." bitfld.long 0x0 2. "OC1FE,Output compare 1 fast enable" "0: CC1 behaves normally depending on counter and..,1: An active edge on the trigger input acts like a.." newline bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1 selection" "0: CC1 channel is configured as output.,1: CC1 channel is configured as input IC1 is mapped..,?,?" group.long 0x18++0x3 line.long 0x0 "TIM13_CCMR1_Input,TIM13 capture/compare mode register 1 [alternate]" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0: no prescaler capture is done each time an edge..,1: capture is done once every 2 events,2: capture is done once every 4 events,3: capture is done once every 8 events" newline bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1 selection" "0: CC1 channel is configured as output,1: CC1 channel is configured as input IC1 is mapped..,?,?" group.word 0x20++0x1 line.word 0x0 "TIM13_CCER,TIM13 capture/compare enable register" bitfld.word 0x0 3. "CC1NP,Capture/Compare 1 complementary output Polarity." "0,1" bitfld.word 0x0 1. "CC1P,Capture/Compare 1 output Polarity." "0: This configuration is reserved,1: non-inverted/both edges/ The circuit is.." newline bitfld.word 0x0 0. "CC1E,Capture/Compare 1 output enable." "0: Capture mode disabled / OC1 is not active,1: Capture mode enabled / OC1 signal is output on.." group.long 0x24++0x3 line.long 0x0 "TIM13_CNT,TIM13 counter" bitfld.long 0x0 31. "UIFCPY,UIF Copy" "0,1" hexmask.long.word 0x0 0.--15. 1. "CNT,Counter value" group.word 0x28++0x1 line.word 0x0 "TIM13_PSC,TIM13 prescaler" hexmask.word 0x0 0.--15. 1. "PSC,Prescaler value" group.word 0x2C++0x1 line.word 0x0 "TIM13_ARR,TIM13 auto-reload register" hexmask.word 0x0 0.--15. 1. "ARR,Auto-reload value" group.word 0x34++0x1 line.word 0x0 "TIM13_CCR1,TIM13 capture/compare register 1" hexmask.word 0x0 0.--15. 1. "CCR1,Capture/Compare 1 value" group.word 0x68++0x1 line.word 0x0 "TIM13_TISEL,TIM13 timer input selection register" hexmask.word.byte 0x0 0.--3. 1. "TI1SEL,selects TI1[0] to TI1[15] input" tree.end endif sif (cpuis("STM32MP13*")) tree "TIM15" base ad:0x4C00A000 group.word 0x0++0x1 line.word 0x0 "TIM15_CR1,TIM15 control register 1" bitfld.word 0x0 11. "UIFREMAP,UIFREMAP" "0,1" bitfld.word 0x0 8.--9. "CKD,CKD" "0,1,2,3" bitfld.word 0x0 7. "ARPE,ARPE" "0,1" bitfld.word 0x0 3. "OPM,OPM" "0,1" bitfld.word 0x0 2. "URS,URS" "0,1" bitfld.word 0x0 1. "UDIS,UDIS" "0,1" bitfld.word 0x0 0. "CEN,CEN" "0,1" group.word 0x4++0x1 line.word 0x0 "TIM15_CR2,TIM15 control register 2" bitfld.word 0x0 10. "OIS2,OIS2" "0,1" bitfld.word 0x0 9. "OIS1N,OIS1N" "0,1" bitfld.word 0x0 8. "OIS1,OIS1" "0,1" bitfld.word 0x0 7. "TI1S,TI1S" "0,1" bitfld.word 0x0 4.--6. "MMS,MMS" "0,1,2,3,4,5,6,7" bitfld.word 0x0 3. "CCDS,CCDS" "0,1" bitfld.word 0x0 2. "CCUS,CCUS" "0,1" bitfld.word 0x0 0. "CCPC,CCPC" "0,1" group.long 0x8++0x3 line.long 0x0 "TIMx_SMCR,slave mode control register" bitfld.long 0x0 20.--21. "TS_4_3,Trigger selection" "0,1,2,3" bitfld.long 0x0 16. "SMS_3,Slave mode selection - bit" "0,1" bitfld.long 0x0 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x0 4.--6. "TS,Trigger selection" "0,1,2,3,4,5,6,7" bitfld.long 0x0 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" group.word 0xC++0x1 line.word 0x0 "TIM15_DIER,TIM15 DMA/interrupt enable" bitfld.word 0x0 14. "TDE,TDE" "0,1" bitfld.word 0x0 13. "COMDE,COMDE" "0,1" bitfld.word 0x0 10. "CC2DE,CC2DE" "0,1" bitfld.word 0x0 9. "CC1DE,CC1DE" "0,1" bitfld.word 0x0 8. "UDE,UDE" "0,1" bitfld.word 0x0 7. "BIE,BIE" "0,1" bitfld.word 0x0 6. "TIE,TIE" "0,1" bitfld.word 0x0 5. "COMIE,COMIE" "0,1" bitfld.word 0x0 2. "CC2IE,CC2IE" "0,1" newline bitfld.word 0x0 1. "CC1IE,CC1IE" "0,1" bitfld.word 0x0 0. "UIE,UIE" "0,1" group.word 0x10++0x1 line.word 0x0 "TIM15_SR,TIM15 status register" bitfld.word 0x0 10. "CC2OF,CC2OF" "0,1" bitfld.word 0x0 9. "CC1OF,CC1OF" "0,1" bitfld.word 0x0 7. "BIF,BIF" "0,1" bitfld.word 0x0 6. "TIF,TIF" "0,1" bitfld.word 0x0 5. "COMIF,COMIF" "0,1" bitfld.word 0x0 2. "CC2IF,CC2IF" "0,1" bitfld.word 0x0 1. "CC1IF,CC1IF" "0,1" bitfld.word 0x0 0. "UIF,UIF" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "TIMx_EGR,event generation register" bitfld.long 0x0 7. "BG,BG" "0,1" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 5. "COMG,COMG" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "TIMx_CCMR1_Output,capture/compare mode register 1 (output" bitfld.long 0x0 24. "OC2M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,Output compare 2 clear" "0,1" bitfld.long 0x0 12.--14. "OC2M,Output compare 2 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,Output compare 2 preload" "0,1" bitfld.long 0x0 10. "OC2FE,Output compare 2 fast" "0,1" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" bitfld.long 0x0 7. "OC1CE,Output compare 1 clear" "0,1" bitfld.long 0x0 4.--6. "OC1M,Output compare 1 mode" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3. "OC1PE,Output compare 1 preload" "0,1" bitfld.long 0x0 2. "OC1FE,Output compare 1 fast" "0,1" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x18++0x3 line.long 0x0 "TIMx_CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PSC,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.word 0x20++0x1 line.word 0x0 "TIM15_CCER,TIM15 capture/compare enable" bitfld.word 0x0 7. "CC2NP,CC2NP" "0,1" bitfld.word 0x0 5. "CC2P,CC2P" "0,1" bitfld.word 0x0 4. "CC2E,CC2E" "0,1" bitfld.word 0x0 3. "CC1NP,CC1NP" "0,1" bitfld.word 0x0 2. "CC1NE,CC1NE" "0,1" bitfld.word 0x0 1. "CC1P,CC1P" "0,1" bitfld.word 0x0 0. "CC1E,CC1E" "0,1" group.long 0x24++0x3 line.long 0x0 "TIM15_CNT,TIM15 counter" rbitfld.long 0x0 31. "UIFCPY,UIFCPY" "0,1" hexmask.long.word 0x0 0.--15. 1. "CNT,CNT" group.word 0x28++0x1 line.word 0x0 "TIM15_PSC,TIM15 prescaler" hexmask.word 0x0 0.--15. 1. "PSC,PSC" group.word 0x2C++0x1 line.word 0x0 "TIM15_ARR,TIM15 auto-reload register" hexmask.word 0x0 0.--15. 1. "ARR,ARR" group.word 0x30++0x1 line.word 0x0 "TIM15_RCR,TIM15 repetition counter" hexmask.word.byte 0x0 0.--7. 1. "REP,REP" group.word 0x34++0x1 line.word 0x0 "TIM15_CCR1,TIM15 capture/compare register" hexmask.word 0x0 0.--15. 1. "CCR1,CCR1" group.word 0x38++0x1 line.word 0x0 "TIM15_CCR2,TIM15 capture/compare register" hexmask.word 0x0 0.--15. 1. "CCR2,CCR2" group.long 0x44++0x3 line.long 0x0 "TIMx_BDTR,As the bits BK2BID. BKBID. BK2DSRM. BKDSRM." bitfld.long 0x0 28. "BKBID,BKBID" "0,1" bitfld.long 0x0 26. "BKDSRM,BKDSRM" "0,1" hexmask.long.byte 0x0 16.--19. 1. "BKF,BKF" bitfld.long 0x0 15. "MOE,MOE" "0,1" bitfld.long 0x0 14. "AOE,AOE" "0,1" bitfld.long 0x0 13. "BKP,BKP" "0,1" bitfld.long 0x0 12. "BKE,BKE" "0,1" bitfld.long 0x0 11. "OSSR,OSSR" "0,1" bitfld.long 0x0 10. "OSSI,OSSI" "0,1" newline bitfld.long 0x0 8.--9. "LOCK,LOCK" "0,1,2,3" hexmask.long.byte 0x0 0.--7. 1. "DTG,DTG" group.word 0x48++0x1 line.word 0x0 "TIM15_DCR,TIM15 DMA control register" hexmask.word.byte 0x0 8.--12. 1. "DBL,DBL" hexmask.word.byte 0x0 0.--4. 1. "DBA,DBA" group.word 0x4C++0x1 line.word 0x0 "TIM15_DMAR,TIM15 DMA address for full" hexmask.word 0x0 0.--15. 1. "DMAB,DMAB" group.long 0x60++0x3 line.long 0x0 "TIM15_AF1,TIM15 alternate register 1" bitfld.long 0x0 9. "BKINP,BKINP" "0,1" bitfld.long 0x0 8. "BKDF1BK0E,BKDF1BK0E" "0,1" bitfld.long 0x0 0. "BKINE,BKINE" "0,1" group.long 0x68++0x3 line.long 0x0 "TIM15_TISEL,TIM15 input selection register" hexmask.long.byte 0x0 8.--11. 1. "TI2SEL,TI2SEL" hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,TI1SEL" tree.end endif sif (cpuis("STM32MP13*")) tree "TIM16" base ad:0x4C00B000 group.word 0x0++0x1 line.word 0x0 "TIMx_CR1,TIM16/TIM17 control register 1" bitfld.word 0x0 11. "UIFREMAP,UIFREMAP" "0,1" bitfld.word 0x0 8.--9. "CKD,CKD" "0,1,2,3" newline bitfld.word 0x0 7. "ARPE,ARPE" "0,1" bitfld.word 0x0 3. "OPM,OPM" "0,1" newline bitfld.word 0x0 2. "URS,URS" "0,1" bitfld.word 0x0 1. "UDIS,UDIS" "0,1" newline bitfld.word 0x0 0. "CEN,CEN" "0,1" group.word 0x4++0x1 line.word 0x0 "TIMx_CR2,TIM16/TIM17 control register 2" bitfld.word 0x0 9. "OIS1N,OIS1N" "0,1" bitfld.word 0x0 8. "OIS1,OIS1" "0,1" newline bitfld.word 0x0 3. "CCDS,CCDS" "0,1" bitfld.word 0x0 2. "CCUS,CCUS" "0,1" newline bitfld.word 0x0 0. "CCPC,CCPC" "0,1" group.word 0xC++0x1 line.word 0x0 "TIMx_DIER,TIM16/TIM17 DMA/interrupt enable" bitfld.word 0x0 13. "COMDE,COMDE" "0,1" bitfld.word 0x0 9. "CC1DE,CC1DE" "0,1" newline bitfld.word 0x0 8. "UDE,UDE" "0,1" bitfld.word 0x0 7. "BIE,BIE" "0,1" newline bitfld.word 0x0 5. "COMIE,COMIE" "0,1" bitfld.word 0x0 1. "CC1IE,CC1IE" "0,1" newline bitfld.word 0x0 0. "UIE,UIE" "0,1" group.word 0x10++0x1 line.word 0x0 "TIMx_SR,TIM16/TIM17 status register" bitfld.word 0x0 9. "CC1OF,CC1OF" "0,1" bitfld.word 0x0 7. "BIF,BIF" "0,1" newline bitfld.word 0x0 5. "COMIF,COMIF" "0,1" bitfld.word 0x0 1. "CC1IF,CC1IF" "0,1" newline bitfld.word 0x0 0. "UIF,UIF" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "TIMx_EGR,event generation register" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "TIMx_CCMR1_Output,capture/compare mode register 1 (output" bitfld.long 0x0 16. "OC1M2,Output Compare 1 mode" "0: Frozen - The comparison between the output..,1: Set channel 1 to active level on match. OC1REF.." bitfld.long 0x0 4.--6. "OC1M1,Output Compare 1 mode" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3. "OC1PE,Output Compare 1 preload enable" "0: Preload register on TIMx_CCR1 disabled.,1: Preload register on TIMx_CCR1 enabled." bitfld.long 0x0 2. "OC1FE,Output Compare 1 fast enable" "0: CC1 behaves normally depending on counter and..,1: An active edge on the trigger input acts like a.." newline bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1 selection" "0: CC1 channel is configured as output,1: CC1 channel is configured as input IC1 is mapped..,2: CC1 channel is configured as input IC1 is mapped..,3: CC1 channel is configured as input IC1 is mapped.." group.long 0x18++0x3 line.long 0x0 "TIMx_CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0: no prescaler capture is done each time an edge..,1: capture is done once every 2 events,2: capture is done once every 4 events,3: capture is done once every 8 events" newline bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1 Selection" "0: CC1 channel is configured as output,1: CC1 channel is configured as input IC1 is mapped..,2: CC1 channel is configured as input IC1 is mapped..,3: CC1 channel is configured as input IC1 is mapped.." group.word 0x20++0x1 line.word 0x0 "TIMx_CCER,TIM16/TIM17 capture/compare enable" bitfld.word 0x0 3. "CC1NP,CC1NP" "0,1" bitfld.word 0x0 2. "CC1NE,CC1NE" "0,1" newline bitfld.word 0x0 1. "CC1P,CC1P" "0,1" bitfld.word 0x0 0. "CC1E,CC1E" "0,1" group.long 0x24++0x3 line.long 0x0 "TIMx_CNT,TIM16/TIM17 counter" rbitfld.long 0x0 31. "UIFCPY,UIFCPY" "0,1" hexmask.long.word 0x0 0.--15. 1. "CNT,CNT" group.word 0x28++0x1 line.word 0x0 "TIMx_PSC,TIM16/TIM17 prescaler" hexmask.word 0x0 0.--15. 1. "PSC,PSC" group.word 0x2C++0x1 line.word 0x0 "TIMx_ARR,TIM16/TIM17 auto-reload" hexmask.word 0x0 0.--15. 1. "ARR,ARR" group.word 0x30++0x1 line.word 0x0 "TIMx_RCR,TIM16/TIM17 repetition counter" hexmask.word.byte 0x0 0.--7. 1. "REP,REP" group.word 0x34++0x1 line.word 0x0 "TIMx_CCR1,TIM16/TIM17 capture/compare register" hexmask.word 0x0 0.--15. 1. "CCR1,CCR1" group.long 0x44++0x3 line.long 0x0 "TIMx_BDTR,As the BKBID. BKDSRM. BKF[3:0]. AOE. BKP." bitfld.long 0x0 28. "BKBID,BKBID" "0,1" bitfld.long 0x0 26. "BKDSRM,BKDSRM" "0,1" newline hexmask.long.byte 0x0 16.--19. 1. "BKF,BKF" bitfld.long 0x0 15. "MOE,MOE" "0,1" newline bitfld.long 0x0 14. "AOE,AOE" "0,1" bitfld.long 0x0 13. "BKP,BKP" "0,1" newline bitfld.long 0x0 12. "BKE,BKE" "0,1" bitfld.long 0x0 11. "OSSR,OSSR" "0,1" newline bitfld.long 0x0 10. "OSSI,OSSI" "0,1" bitfld.long 0x0 8.--9. "LOCK,LOCK" "0,1,2,3" newline hexmask.long.byte 0x0 0.--7. 1. "DTG,DTG" group.word 0x48++0x1 line.word 0x0 "TIMx_DCR,TIM16/TIM17 DMA control" hexmask.word.byte 0x0 8.--12. 1. "DBL,DBL" hexmask.word.byte 0x0 0.--4. 1. "DBA,DBA" group.word 0x4C++0x1 line.word 0x0 "TIMx_DMAR,TIM16/TIM17 DMA address for full" hexmask.word 0x0 0.--15. 1. "DMAB,DMAB" group.long 0x60++0x3 line.long 0x0 "TIMx_AF1,TIM17 alternate function register" bitfld.long 0x0 9. "BKINP,BKINP" "0,1" bitfld.long 0x0 8. "BKDF1BK2E,BKDF1BK2E" "0,1" newline bitfld.long 0x0 0. "BKINE,BKINE" "0,1" group.long 0x68++0x3 line.long 0x0 "TIMx_TISEL,TIM17 input selection register" hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,TI1SEL" tree.end endif sif (cpuis("STM32MP13*")) tree "TIM17" base ad:0x4C00C000 group.word 0x0++0x1 line.word 0x0 "TIMx_CR1,TIM16/TIM17 control register 1" bitfld.word 0x0 11. "UIFREMAP,UIFREMAP" "0,1" bitfld.word 0x0 8.--9. "CKD,CKD" "0,1,2,3" newline bitfld.word 0x0 7. "ARPE,ARPE" "0,1" bitfld.word 0x0 3. "OPM,OPM" "0,1" newline bitfld.word 0x0 2. "URS,URS" "0,1" bitfld.word 0x0 1. "UDIS,UDIS" "0,1" newline bitfld.word 0x0 0. "CEN,CEN" "0,1" group.word 0x4++0x1 line.word 0x0 "TIMx_CR2,TIM16/TIM17 control register 2" bitfld.word 0x0 9. "OIS1N,OIS1N" "0,1" bitfld.word 0x0 8. "OIS1,OIS1" "0,1" newline bitfld.word 0x0 3. "CCDS,CCDS" "0,1" bitfld.word 0x0 2. "CCUS,CCUS" "0,1" newline bitfld.word 0x0 0. "CCPC,CCPC" "0,1" group.word 0xC++0x1 line.word 0x0 "TIMx_DIER,TIM16/TIM17 DMA/interrupt enable" bitfld.word 0x0 13. "COMDE,COMDE" "0,1" bitfld.word 0x0 9. "CC1DE,CC1DE" "0,1" newline bitfld.word 0x0 8. "UDE,UDE" "0,1" bitfld.word 0x0 7. "BIE,BIE" "0,1" newline bitfld.word 0x0 5. "COMIE,COMIE" "0,1" bitfld.word 0x0 1. "CC1IE,CC1IE" "0,1" newline bitfld.word 0x0 0. "UIE,UIE" "0,1" group.word 0x10++0x1 line.word 0x0 "TIMx_SR,TIM16/TIM17 status register" bitfld.word 0x0 9. "CC1OF,CC1OF" "0,1" bitfld.word 0x0 7. "BIF,BIF" "0,1" newline bitfld.word 0x0 5. "COMIF,COMIF" "0,1" bitfld.word 0x0 1. "CC1IF,CC1IF" "0,1" newline bitfld.word 0x0 0. "UIF,UIF" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "TIMx_EGR,event generation register" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "TIMx_CCMR1_Output,capture/compare mode register 1 (output" bitfld.long 0x0 16. "OC1M2,Output Compare 1 mode" "0: Frozen - The comparison between the output..,1: Set channel 1 to active level on match. OC1REF.." bitfld.long 0x0 4.--6. "OC1M1,Output Compare 1 mode" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3. "OC1PE,Output Compare 1 preload enable" "0: Preload register on TIMx_CCR1 disabled.,1: Preload register on TIMx_CCR1 enabled." bitfld.long 0x0 2. "OC1FE,Output Compare 1 fast enable" "0: CC1 behaves normally depending on counter and..,1: An active edge on the trigger input acts like a.." newline bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1 selection" "0: CC1 channel is configured as output,1: CC1 channel is configured as input IC1 is mapped..,2: CC1 channel is configured as input IC1 is mapped..,3: CC1 channel is configured as input IC1 is mapped.." group.long 0x18++0x3 line.long 0x0 "TIMx_CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0: no prescaler capture is done each time an edge..,1: capture is done once every 2 events,2: capture is done once every 4 events,3: capture is done once every 8 events" newline bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1 Selection" "0: CC1 channel is configured as output,1: CC1 channel is configured as input IC1 is mapped..,2: CC1 channel is configured as input IC1 is mapped..,3: CC1 channel is configured as input IC1 is mapped.." group.word 0x20++0x1 line.word 0x0 "TIMx_CCER,TIM16/TIM17 capture/compare enable" bitfld.word 0x0 3. "CC1NP,CC1NP" "0,1" bitfld.word 0x0 2. "CC1NE,CC1NE" "0,1" newline bitfld.word 0x0 1. "CC1P,CC1P" "0,1" bitfld.word 0x0 0. "CC1E,CC1E" "0,1" group.long 0x24++0x3 line.long 0x0 "TIMx_CNT,TIM16/TIM17 counter" rbitfld.long 0x0 31. "UIFCPY,UIFCPY" "0,1" hexmask.long.word 0x0 0.--15. 1. "CNT,CNT" group.word 0x28++0x1 line.word 0x0 "TIMx_PSC,TIM16/TIM17 prescaler" hexmask.word 0x0 0.--15. 1. "PSC,PSC" group.word 0x2C++0x1 line.word 0x0 "TIMx_ARR,TIM16/TIM17 auto-reload" hexmask.word 0x0 0.--15. 1. "ARR,ARR" group.word 0x30++0x1 line.word 0x0 "TIMx_RCR,TIM16/TIM17 repetition counter" hexmask.word.byte 0x0 0.--7. 1. "REP,REP" group.word 0x34++0x1 line.word 0x0 "TIMx_CCR1,TIM16/TIM17 capture/compare register" hexmask.word 0x0 0.--15. 1. "CCR1,CCR1" group.long 0x44++0x3 line.long 0x0 "TIMx_BDTR,As the BKBID. BKDSRM. BKF[3:0]. AOE. BKP." bitfld.long 0x0 28. "BKBID,BKBID" "0,1" bitfld.long 0x0 26. "BKDSRM,BKDSRM" "0,1" newline hexmask.long.byte 0x0 16.--19. 1. "BKF,BKF" bitfld.long 0x0 15. "MOE,MOE" "0,1" newline bitfld.long 0x0 14. "AOE,AOE" "0,1" bitfld.long 0x0 13. "BKP,BKP" "0,1" newline bitfld.long 0x0 12. "BKE,BKE" "0,1" bitfld.long 0x0 11. "OSSR,OSSR" "0,1" newline bitfld.long 0x0 10. "OSSI,OSSI" "0,1" bitfld.long 0x0 8.--9. "LOCK,LOCK" "0,1,2,3" newline hexmask.long.byte 0x0 0.--7. 1. "DTG,DTG" group.word 0x48++0x1 line.word 0x0 "TIMx_DCR,TIM16/TIM17 DMA control" hexmask.word.byte 0x0 8.--12. 1. "DBL,DBL" hexmask.word.byte 0x0 0.--4. 1. "DBA,DBA" group.word 0x4C++0x1 line.word 0x0 "TIMx_DMAR,TIM16/TIM17 DMA address for full" hexmask.word 0x0 0.--15. 1. "DMAB,DMAB" group.long 0x60++0x3 line.long 0x0 "TIMx_AF1,TIM17 alternate function register" bitfld.long 0x0 9. "BKINP,BKINP" "0,1" bitfld.long 0x0 8. "BKDF1BK2E,BKDF1BK2E" "0,1" newline bitfld.long 0x0 0. "BKINE,BKINE" "0,1" group.long 0x68++0x3 line.long 0x0 "TIMx_TISEL,TIM17 input selection register" hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,TI1SEL" tree.end endif sif (cpuis("STM32MP151*")||cpuis("STM32MP153*")||cpuis("STM32MP157*")) tree "TIM1" base ad:0x44000000 group.word 0x0++0x1 line.word 0x0 "TIM1_CR1,TIM1 control register 1" bitfld.word 0x0 11. "UIFREMAP,UIFREMAP" "0,1" bitfld.word 0x0 8.--9. "CKD,CKD" "0,1,2,3" bitfld.word 0x0 7. "ARPE,ARPE" "0,1" bitfld.word 0x0 5.--6. "CMS,CMS" "0,1,2,3" bitfld.word 0x0 4. "DIR,DIR" "0,1" bitfld.word 0x0 3. "OPM,OPM" "0,1" bitfld.word 0x0 2. "URS,URS" "0,1" newline bitfld.word 0x0 1. "UDIS,UDIS" "0,1" bitfld.word 0x0 0. "CEN,CEN" "0,1" group.long 0x4++0x7 line.long 0x0 "TIM1_CR2,TIM1 control register 2" hexmask.long.byte 0x0 20.--23. 1. "MMS2,MMS2" bitfld.long 0x0 18. "OIS6,OIS6" "0,1" bitfld.long 0x0 16. "OIS5,OIS5" "0,1" bitfld.long 0x0 14. "OIS4,OIS4" "0,1" bitfld.long 0x0 13. "OIS3N,OIS3N" "0,1" bitfld.long 0x0 12. "OIS3,OIS3" "0,1" bitfld.long 0x0 11. "OIS2N,OIS2N" "0,1" newline bitfld.long 0x0 10. "OIS2,OIS2" "0,1" bitfld.long 0x0 9. "OIS1N,OIS1N" "0,1" bitfld.long 0x0 8. "OIS1,OIS1" "0,1" bitfld.long 0x0 7. "TI1S,TI1S" "0,1" bitfld.long 0x0 4.--6. "MMS,MMS" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "CCDS,CCDS" "0,1" bitfld.long 0x0 2. "CCUS,CCUS" "0,1" newline bitfld.long 0x0 0. "CCPC,CCPC" "0,1" line.long 0x4 "TIM1_SMCR,TIM1 slave mode control register" bitfld.long 0x4 21. "TS4,TS4" "0,1" bitfld.long 0x4 20. "TS3,TS3" "0,1" bitfld.long 0x4 16. "SMS3,SMS3" "0,1" bitfld.long 0x4 15. "ETP,ETP" "0,1" bitfld.long 0x4 14. "ECE,ECE" "0,1" bitfld.long 0x4 12.--13. "ETPS,ETPS" "0,1,2,3" hexmask.long.byte 0x4 8.--11. 1. "ETF,ETF" newline bitfld.long 0x4 7. "MSM,MSM" "0,1" bitfld.long 0x4 4.--6. "TS,TS" "0,1,2,3,4,5,6,7" bitfld.long 0x4 0.--2. "SMS,SMS" "0,1,2,3,4,5,6,7" group.word 0xC++0x1 line.word 0x0 "TIM1_DIER,TIM1 DMA/interrupt enable register" bitfld.word 0x0 14. "TDE,TDE" "0,1" bitfld.word 0x0 13. "COMDE,COMDE" "0,1" bitfld.word 0x0 12. "CC4DE,CC4DE" "0,1" bitfld.word 0x0 11. "CC3DE,CC3DE" "0,1" bitfld.word 0x0 10. "CC2DE,CC2DE" "0,1" bitfld.word 0x0 9. "CC1DE,CC1DE" "0,1" bitfld.word 0x0 8. "UDE,UDE" "0,1" newline bitfld.word 0x0 7. "BIE,BIE" "0,1" bitfld.word 0x0 6. "TIE,TIE" "0,1" bitfld.word 0x0 5. "COMIE,COMIE" "0,1" bitfld.word 0x0 4. "CC4IE,CC4IE" "0,1" bitfld.word 0x0 3. "CC3IE,CC3IE" "0,1" bitfld.word 0x0 2. "CC2IE,CC2IE" "0,1" bitfld.word 0x0 1. "CC1IE,CC1IE" "0,1" newline bitfld.word 0x0 0. "UIE,UIE" "0,1" group.long 0x10++0x3 line.long 0x0 "TIM1_SR,TIM1 status register" bitfld.long 0x0 17. "CC6IF,CC6IF" "0,1" bitfld.long 0x0 16. "CC5IF,CC5IF" "0,1" bitfld.long 0x0 13. "SBIF,SBIF" "0,1" bitfld.long 0x0 12. "CC4OF,CC4OF" "0,1" bitfld.long 0x0 11. "CC3OF,CC3OF" "0,1" bitfld.long 0x0 10. "CC2OF,CC2OF" "0,1" bitfld.long 0x0 9. "CC1OF,CC1OF" "0,1" newline bitfld.long 0x0 8. "B2IF,B2IF" "0,1" bitfld.long 0x0 7. "BIF,BIF" "0,1" bitfld.long 0x0 6. "TIF,TIF" "0,1" bitfld.long 0x0 5. "COMIF,COMIF" "0,1" bitfld.long 0x0 4. "CC4IF,CC4IF" "0,1" bitfld.long 0x0 3. "CC3IF,CC3IF" "0,1" bitfld.long 0x0 2. "CC2IF,CC2IF" "0,1" newline bitfld.long 0x0 1. "CC1IF,CC1IF" "0,1" bitfld.long 0x0 0. "UIF,UIF" "0,1" wgroup.word 0x14++0x1 line.word 0x0 "TIM1_EGR,TIM1 event generation register" bitfld.word 0x0 8. "B2G,B2G" "0,1" bitfld.word 0x0 7. "BG,BG" "0,1" bitfld.word 0x0 6. "TG,TG" "0,1" bitfld.word 0x0 5. "COMG,COMG" "0,1" bitfld.word 0x0 4. "CC4G,CC4G" "0,1" bitfld.word 0x0 3. "CC3G,CC3G" "0,1" bitfld.word 0x0 2. "CC2G,CC2G" "0,1" newline bitfld.word 0x0 1. "CC1G,CC1G" "0,1" bitfld.word 0x0 0. "UG,UG" "0,1" group.long 0x18++0xF line.long 0x0 "TIM1_CCMR1ALTERNATE1,The same register can be used for input capture mode (this section) or for output compare mode (next section). The direction of a channel is defined by configuring the corresponding CCxS bits. All the other bits of this register have.." hexmask.long.byte 0x0 12.--15. 1. "IC2F,IC2F" bitfld.long 0x0 10.--11. "IC2PSC,IC2PSC" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,CC2S" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,IC1F" bitfld.long 0x0 2.--3. "IC1PSC,IC1PSC" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,CC1S" "0,1,2,3" line.long 0x4 "TIM1_CCMR2ALTERNATE17,The same register can be used for input capture mode (this section) or for output compare mode (next section). The direction of a channel is defined by configuring the corresponding CCxS bits. All the other bits of this register.." hexmask.long.byte 0x4 12.--15. 1. "IC4F,IC4F" bitfld.long 0x4 10.--11. "IC4PSC,IC4PSC" "0,1,2,3" bitfld.long 0x4 8.--9. "CC4S,CC4S" "0,1,2,3" hexmask.long.byte 0x4 4.--7. 1. "IC3F,IC3F" bitfld.long 0x4 2.--3. "IC3PSC,IC3PSC" "0,1,2,3" bitfld.long 0x4 0.--1. "CC3S,CC3S" "0,1,2,3" line.long 0x8 "TIM1_CCER,TIM1 capture/compare enable register" bitfld.long 0x8 21. "CC6P,CC6P" "0,1" bitfld.long 0x8 20. "CC6E,CC6E" "0,1" bitfld.long 0x8 17. "CC5P,CC5P" "0,1" bitfld.long 0x8 16. "CC5E,CC5E" "0,1" bitfld.long 0x8 15. "CC4NP,CC4NP" "0,1" bitfld.long 0x8 13. "CC4P,CC4P" "0,1" bitfld.long 0x8 12. "CC4E,CC4E" "0,1" newline bitfld.long 0x8 11. "CC3NP,CC3NP" "0,1" bitfld.long 0x8 10. "CC3NE,CC3NE" "0,1" bitfld.long 0x8 9. "CC3P,CC3P" "0,1" bitfld.long 0x8 8. "CC3E,CC3E" "0,1" bitfld.long 0x8 7. "CC2NP,CC2NP" "0,1" bitfld.long 0x8 6. "CC2NE,CC2NE" "0,1" bitfld.long 0x8 5. "CC2P,CC2P" "0,1" newline bitfld.long 0x8 4. "CC2E,CC2E" "0,1" bitfld.long 0x8 3. "CC1NP,CC1NP" "0,1" bitfld.long 0x8 2. "CC1NE,CC1NE" "0,1" bitfld.long 0x8 1. "CC1P,CC1P" "0,1" bitfld.long 0x8 0. "CC1E,CC1E" "0,1" line.long 0xC "TIM1_CNT,TIM1 counter" rbitfld.long 0xC 31. "UIFCPY,UIFCPY" "0,1" hexmask.long.word 0xC 0.--15. 1. "CNT,CNT" group.word 0x28++0x1 line.word 0x0 "TIM1_PSC,TIM1 prescaler" hexmask.word 0x0 0.--15. 1. "PSC,PSC" group.word 0x2C++0x1 line.word 0x0 "TIM1_ARR,TIM1 auto-reload register" hexmask.word 0x0 0.--15. 1. "ARR,ARR" group.word 0x30++0x1 line.word 0x0 "TIM1_RCR,TIM1 repetition counter register" hexmask.word 0x0 0.--15. 1. "REP,REP" group.word 0x34++0x1 line.word 0x0 "TIM1_CCR1,TIM1 capture/compare register 1" hexmask.word 0x0 0.--15. 1. "CCR1,CCR1" group.word 0x38++0x1 line.word 0x0 "TIM1_CCR2,TIM1 capture/compare register 2" hexmask.word 0x0 0.--15. 1. "CCR2,CCR2" group.word 0x3C++0x1 line.word 0x0 "TIM1_CCR3,TIM1 capture/compare register 3" hexmask.word 0x0 0.--15. 1. "CCR3,CCR3" group.word 0x40++0x1 line.word 0x0 "TIM1_CCR4,TIM1 capture/compare register 4" hexmask.word 0x0 0.--15. 1. "CCR4,CCR4" group.long 0x44++0x3 line.long 0x0 "TIM1_BDTR,As the bits BK2BID. BKBID. BK2DSRM. BKDSRM. BK2P. BK2E. BK2F[3:0]. BKF[3:0]. AOE. BKP. BKE. OSSI. OSSR and DTG[7:0] can be write-locked depending on the LOCK configuration. it can be necessary to configure all of them during the first write.." bitfld.long 0x0 29. "BK2BID,BK2BID" "0,1" bitfld.long 0x0 28. "BKBID,BKBID" "0,1" bitfld.long 0x0 27. "BK2DSRM,BK2DSRM" "0,1" bitfld.long 0x0 26. "BKDSRM,BKDSRM" "0,1" bitfld.long 0x0 25. "BK2P,BK2P" "0,1" bitfld.long 0x0 24. "BK2E,BK2E" "0,1" hexmask.long.byte 0x0 20.--23. 1. "BK2F,BK2F" newline hexmask.long.byte 0x0 16.--19. 1. "BKF,BKF" bitfld.long 0x0 15. "MOE,MOE" "0,1" bitfld.long 0x0 14. "AOE,AOE" "0,1" bitfld.long 0x0 13. "BKP,BKP" "0,1" bitfld.long 0x0 12. "BKE,BKE" "0,1" bitfld.long 0x0 11. "OSSR,OSSR" "0,1" bitfld.long 0x0 10. "OSSI,OSSI" "0,1" newline bitfld.long 0x0 8.--9. "LOCK,LOCK" "0,1,2,3" hexmask.long.byte 0x0 0.--7. 1. "DTG,DTG" group.word 0x48++0x1 line.word 0x0 "TIM1_DCR,TIM1 DMA control register" hexmask.word.byte 0x0 8.--12. 1. "DBL,DBL" hexmask.word.byte 0x0 0.--4. 1. "DBA,DBA" group.long 0x4C++0x3 line.long 0x0 "TIM1_DMAR,TIM1 DMA address for full transfer" hexmask.long 0x0 0.--31. 1. "DMAB,DMAB" group.long 0x54++0x7 line.long 0x0 "TIM1_CCMR3,The channels 5 and 6 can only be configured in output. Output compare mode:" bitfld.long 0x0 24. "OC6M3,OC6M3" "0,1" bitfld.long 0x0 16. "OC5M3,OC5M3" "0,1" bitfld.long 0x0 15. "OC6CE,OC6CE" "0,1" bitfld.long 0x0 12.--14. "OC6M,OC6M" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC6PE,OC6PE" "0,1" bitfld.long 0x0 10. "OC6FE,OC6FE" "0,1" bitfld.long 0x0 7. "OC5CE,OC5CE" "0,1" newline bitfld.long 0x0 4.--6. "OC5M,OC5M" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "OC5PE,OC5PE" "0,1" bitfld.long 0x0 2. "OC5FE,OC5FE" "0,1" line.long 0x4 "TIM1_CCR5,TIM1 capture/compare register 5" bitfld.long 0x4 31. "GC5C3,GC5C3" "0,1" bitfld.long 0x4 30. "GC5C2,GC5C2" "0,1" bitfld.long 0x4 29. "GC5C1,GC5C1" "0,1" hexmask.long.word 0x4 0.--15. 1. "CCR5,CCR5" group.word 0x5C++0x1 line.word 0x0 "TIM1_CCR6,TIM1 capture/compare register 6" hexmask.word 0x0 0.--15. 1. "CCR6,CCR6" group.long 0x60++0xB line.long 0x0 "TIM1_AF1,TIM1 alternate function option register 1" hexmask.long.byte 0x0 14.--17. 1. "ETRSEL,ETRSEL" bitfld.long 0x0 9. "BKINP,BKINP" "0,1" bitfld.long 0x0 8. "BKDF1BK0E,BKDF1BK0E" "0,1" bitfld.long 0x0 0. "BKINE,BKINE" "0,1" line.long 0x4 "TIM1_AF2,TIM1 Alternate function register 2" bitfld.long 0x4 9. "BK2INP,BK2INP" "0,1" bitfld.long 0x4 8. "BK2DF1BK1E,BK2DF1BK1E" "0,1" bitfld.long 0x4 0. "BK2INE,BK2INE" "0,1" line.long 0x8 "TIM1_TISEL,TIM1 timer input selection register" hexmask.long.byte 0x8 24.--27. 1. "TI4SEL,TI4SEL" hexmask.long.byte 0x8 16.--19. 1. "TI3SEL,TI3SEL" hexmask.long.byte 0x8 8.--11. 1. "TI2SEL,TI2SEL" hexmask.long.byte 0x8 0.--3. 1. "TI1SEL,TI1SEL" tree.end endif sif (cpuis("STM32MP151*")||cpuis("STM32MP153*")||cpuis("STM32MP157*")) tree "TIM2" base ad:0x40000000 group.word 0x0++0x1 line.word 0x0 "TIM2_CR1,TIM2 control register 1" bitfld.word 0x0 11. "UIFREMAP,UIFREMAP" "0,1" bitfld.word 0x0 8.--9. "CKD,CKD" "0,1,2,3" bitfld.word 0x0 7. "ARPE,ARPE" "0,1" bitfld.word 0x0 5.--6. "CMS,CMS" "0,1,2,3" bitfld.word 0x0 4. "DIR,DIR" "0,1" bitfld.word 0x0 3. "OPM,OPM" "0,1" bitfld.word 0x0 2. "URS,URS" "0,1" bitfld.word 0x0 1. "UDIS,UDIS" "0,1" newline bitfld.word 0x0 0. "CEN,CEN" "0,1" group.long 0x4++0x7 line.long 0x0 "TIM2_CR2,TIM2 control register 2" hexmask.long.byte 0x0 20.--23. 1. "MMS2,MMS2" bitfld.long 0x0 18. "OIS6,OIS6" "0,1" bitfld.long 0x0 16. "OIS5,OIS5" "0,1" bitfld.long 0x0 14. "OIS4,OIS4" "0,1" bitfld.long 0x0 13. "OIS3N,OIS3N" "0,1" bitfld.long 0x0 12. "OIS3,OIS3" "0,1" bitfld.long 0x0 11. "OIS2N,OIS2N" "0,1" bitfld.long 0x0 10. "OIS2,OIS2" "0,1" newline bitfld.long 0x0 9. "OIS1N,OIS1N" "0,1" bitfld.long 0x0 8. "OIS1,OIS1" "0,1" bitfld.long 0x0 7. "TI1S,TI1S" "0,1" bitfld.long 0x0 4.--6. "MMS,MMS" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "CCDS,CCDS" "0,1" bitfld.long 0x0 2. "CCUS,CCUS" "0,1" bitfld.long 0x0 0. "CCPC,CCPC" "0,1" line.long 0x4 "TIM2_SMCR,TIM2 slave mode control register" bitfld.long 0x4 21. "TS4,TS4" "0,1" bitfld.long 0x4 20. "TS3,TS3" "0,1" bitfld.long 0x4 16. "SMS3,SMS3" "0,1" bitfld.long 0x4 15. "ETP,ETP" "0,1" bitfld.long 0x4 14. "ECE,ECE" "0,1" bitfld.long 0x4 12.--13. "ETPS,ETPS" "0,1,2,3" hexmask.long.byte 0x4 8.--11. 1. "ETF,ETF" bitfld.long 0x4 7. "MSM,MSM" "0,1" newline bitfld.long 0x4 4.--6. "TS,TS" "0,1,2,3,4,5,6,7" bitfld.long 0x4 0.--2. "SMS,SMS" "0,1,2,3,4,5,6,7" group.word 0xC++0x1 line.word 0x0 "TIM2_DIER,TIM2 DMA/interrupt enable register" bitfld.word 0x0 14. "TDE,TDE" "0,1" bitfld.word 0x0 13. "COMDE,COMDE" "0,1" bitfld.word 0x0 12. "CC4DE,CC4DE" "0,1" bitfld.word 0x0 11. "CC3DE,CC3DE" "0,1" bitfld.word 0x0 10. "CC2DE,CC2DE" "0,1" bitfld.word 0x0 9. "CC1DE,CC1DE" "0,1" bitfld.word 0x0 8. "UDE,UDE" "0,1" bitfld.word 0x0 7. "BIE,BIE" "0,1" newline bitfld.word 0x0 6. "TIE,TIE" "0,1" bitfld.word 0x0 5. "COMIE,COMIE" "0,1" bitfld.word 0x0 4. "CC4IE,CC4IE" "0,1" bitfld.word 0x0 3. "CC3IE,CC3IE" "0,1" bitfld.word 0x0 2. "CC2IE,CC2IE" "0,1" bitfld.word 0x0 1. "CC1IE,CC1IE" "0,1" bitfld.word 0x0 0. "UIE,UIE" "0,1" group.long 0x10++0x3 line.long 0x0 "TIM2_SR,TIM2 status register" bitfld.long 0x0 17. "CC6IF,CC6IF" "0,1" bitfld.long 0x0 16. "CC5IF,CC5IF" "0,1" bitfld.long 0x0 13. "SBIF,SBIF" "0,1" bitfld.long 0x0 12. "CC4OF,CC4OF" "0,1" bitfld.long 0x0 11. "CC3OF,CC3OF" "0,1" bitfld.long 0x0 10. "CC2OF,CC2OF" "0,1" bitfld.long 0x0 9. "CC1OF,CC1OF" "0,1" bitfld.long 0x0 8. "B2IF,B2IF" "0,1" newline bitfld.long 0x0 7. "BIF,BIF" "0,1" bitfld.long 0x0 6. "TIF,TIF" "0,1" bitfld.long 0x0 5. "COMIF,COMIF" "0,1" bitfld.long 0x0 4. "CC4IF,CC4IF" "0,1" bitfld.long 0x0 3. "CC3IF,CC3IF" "0,1" bitfld.long 0x0 2. "CC2IF,CC2IF" "0,1" bitfld.long 0x0 1. "CC1IF,CC1IF" "0,1" bitfld.long 0x0 0. "UIF,UIF" "0,1" wgroup.word 0x14++0x1 line.word 0x0 "TIM2_EGR,TIM2 event generation register" bitfld.word 0x0 8. "B2G,B2G" "0,1" bitfld.word 0x0 7. "BG,BG" "0,1" bitfld.word 0x0 6. "TG,TG" "0,1" bitfld.word 0x0 5. "COMG,COMG" "0,1" bitfld.word 0x0 4. "CC4G,CC4G" "0,1" bitfld.word 0x0 3. "CC3G,CC3G" "0,1" bitfld.word 0x0 2. "CC2G,CC2G" "0,1" bitfld.word 0x0 1. "CC1G,CC1G" "0,1" newline bitfld.word 0x0 0. "UG,UG" "0,1" group.long 0x18++0xF line.long 0x0 "TIM2_CCMR1ALTERNATE2,The same register can be used for input capture mode (this section) or for output compare mode (next section). The direction of a channel is defined by configuring the corresponding CCxS bits. All the other bits of this register have.." hexmask.long.byte 0x0 12.--15. 1. "IC2F,IC2F" bitfld.long 0x0 10.--11. "IC2PSC,IC2PSC" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,CC2S" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,IC1F" bitfld.long 0x0 2.--3. "IC1PSC,IC1PSC" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,CC1S" "0,1,2,3" line.long 0x4 "TIM2_CCMR2ALTERNATE18,The same register can be used for input capture mode (this section) or for output compare mode (next section). The direction of a channel is defined by configuring the corresponding CCxS bits. All the other bits of this register.." hexmask.long.byte 0x4 12.--15. 1. "IC4F,IC4F" bitfld.long 0x4 10.--11. "IC4PSC,IC4PSC" "0,1,2,3" bitfld.long 0x4 8.--9. "CC4S,CC4S" "0,1,2,3" hexmask.long.byte 0x4 4.--7. 1. "IC3F,IC3F" bitfld.long 0x4 2.--3. "IC3PSC,IC3PSC" "0,1,2,3" bitfld.long 0x4 0.--1. "CC3S,CC3S" "0,1,2,3" line.long 0x8 "TIM2_CCER,TIM2 capture/compare enable register" bitfld.long 0x8 21. "CC6P,CC6P" "0,1" bitfld.long 0x8 20. "CC6E,CC6E" "0,1" bitfld.long 0x8 17. "CC5P,CC5P" "0,1" bitfld.long 0x8 16. "CC5E,CC5E" "0,1" bitfld.long 0x8 15. "CC4NP,CC4NP" "0,1" bitfld.long 0x8 13. "CC4P,CC4P" "0,1" bitfld.long 0x8 12. "CC4E,CC4E" "0,1" bitfld.long 0x8 11. "CC3NP,CC3NP" "0,1" newline bitfld.long 0x8 10. "CC3NE,CC3NE" "0,1" bitfld.long 0x8 9. "CC3P,CC3P" "0,1" bitfld.long 0x8 8. "CC3E,CC3E" "0,1" bitfld.long 0x8 7. "CC2NP,CC2NP" "0,1" bitfld.long 0x8 6. "CC2NE,CC2NE" "0,1" bitfld.long 0x8 5. "CC2P,CC2P" "0,1" bitfld.long 0x8 4. "CC2E,CC2E" "0,1" bitfld.long 0x8 3. "CC1NP,CC1NP" "0,1" newline bitfld.long 0x8 2. "CC1NE,CC1NE" "0,1" bitfld.long 0x8 1. "CC1P,CC1P" "0,1" bitfld.long 0x8 0. "CC1E,CC1E" "0,1" line.long 0xC "TIM2_CNT,TIM2 counter" rbitfld.long 0xC 31. "UIFCPY,UIFCPY" "0,1" hexmask.long.word 0xC 0.--15. 1. "CNT,CNT" group.word 0x28++0x1 line.word 0x0 "TIM2_PSC,TIM2 prescaler" hexmask.word 0x0 0.--15. 1. "PSC,PSC" group.word 0x2C++0x1 line.word 0x0 "TIM2_ARR,TIM2 auto-reload register" hexmask.word 0x0 0.--15. 1. "ARR,ARR" group.word 0x30++0x1 line.word 0x0 "TIM2_RCR,TIM2 repetition counter register" hexmask.word 0x0 0.--15. 1. "REP,REP" group.word 0x34++0x1 line.word 0x0 "TIM2_CCR1,TIM2 capture/compare register 1" hexmask.word 0x0 0.--15. 1. "CCR1,CCR1" group.word 0x38++0x1 line.word 0x0 "TIM2_CCR2,TIM2 capture/compare register 2" hexmask.word 0x0 0.--15. 1. "CCR2,CCR2" group.word 0x3C++0x1 line.word 0x0 "TIM2_CCR3,TIM2 capture/compare register 3" hexmask.word 0x0 0.--15. 1. "CCR3,CCR3" group.word 0x40++0x1 line.word 0x0 "TIM2_CCR4,TIM2 capture/compare register 4" hexmask.word 0x0 0.--15. 1. "CCR4,CCR4" group.long 0x44++0x3 line.long 0x0 "TIM2_BDTR,As the bits BK2BID. BKBID. BK2DSRM. BKDSRM. BK2P. BK2E. BK2F[3:0]. BKF[3:0]. AOE. BKP. BKE. OSSI. OSSR and DTG[7:0] can be write-locked depending on the LOCK configuration. it can be necessary to configure all of them during the first write.." bitfld.long 0x0 29. "BK2BID,BK2BID" "0,1" bitfld.long 0x0 28. "BKBID,BKBID" "0,1" bitfld.long 0x0 27. "BK2DSRM,BK2DSRM" "0,1" bitfld.long 0x0 26. "BKDSRM,BKDSRM" "0,1" bitfld.long 0x0 25. "BK2P,BK2P" "0,1" bitfld.long 0x0 24. "BK2E,BK2E" "0,1" hexmask.long.byte 0x0 20.--23. 1. "BK2F,BK2F" hexmask.long.byte 0x0 16.--19. 1. "BKF,BKF" newline bitfld.long 0x0 15. "MOE,MOE" "0,1" bitfld.long 0x0 14. "AOE,AOE" "0,1" bitfld.long 0x0 13. "BKP,BKP" "0,1" bitfld.long 0x0 12. "BKE,BKE" "0,1" bitfld.long 0x0 11. "OSSR,OSSR" "0,1" bitfld.long 0x0 10. "OSSI,OSSI" "0,1" bitfld.long 0x0 8.--9. "LOCK,LOCK" "0,1,2,3" hexmask.long.byte 0x0 0.--7. 1. "DTG,DTG" group.word 0x48++0x1 line.word 0x0 "TIM2_DCR,TIM2 DMA control register" hexmask.word.byte 0x0 8.--12. 1. "DBL,DBL" hexmask.word.byte 0x0 0.--4. 1. "DBA,DBA" group.long 0x4C++0x3 line.long 0x0 "TIM2_DMAR,TIM2 DMA address for full transfer" hexmask.long 0x0 0.--31. 1. "DMAB,DMAB" group.long 0x54++0x7 line.long 0x0 "TIM2_CCMR3,The channels 5 and 6 can only be configured in output. Output compare mode:" bitfld.long 0x0 24. "OC6M3,OC6M3" "0,1" bitfld.long 0x0 16. "OC5M3,OC5M3" "0,1" bitfld.long 0x0 15. "OC6CE,OC6CE" "0,1" bitfld.long 0x0 12.--14. "OC6M,OC6M" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC6PE,OC6PE" "0,1" bitfld.long 0x0 10. "OC6FE,OC6FE" "0,1" bitfld.long 0x0 7. "OC5CE,OC5CE" "0,1" bitfld.long 0x0 4.--6. "OC5M,OC5M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3. "OC5PE,OC5PE" "0,1" bitfld.long 0x0 2. "OC5FE,OC5FE" "0,1" line.long 0x4 "TIM2_CCR5,TIM2 capture/compare register 5" bitfld.long 0x4 31. "GC5C3,GC5C3" "0,1" bitfld.long 0x4 30. "GC5C2,GC5C2" "0,1" bitfld.long 0x4 29. "GC5C1,GC5C1" "0,1" hexmask.long.word 0x4 0.--15. 1. "CCR5,CCR5" group.word 0x5C++0x1 line.word 0x0 "TIM2_CCR6,TIM2 capture/compare register 6" hexmask.word 0x0 0.--15. 1. "CCR6,CCR6" tree.end endif sif (cpuis("STM32MP151*")||cpuis("STM32MP153*")||cpuis("STM32MP157*")) tree "TIM3" base ad:0x40001000 group.word 0x0++0x1 line.word 0x0 "TIM3_CR1,TIM3 control register 1" bitfld.word 0x0 11. "UIFREMAP,UIFREMAP" "0,1" bitfld.word 0x0 8.--9. "CKD,CKD" "0,1,2,3" bitfld.word 0x0 7. "ARPE,ARPE" "0,1" bitfld.word 0x0 5.--6. "CMS,CMS" "0,1,2,3" bitfld.word 0x0 4. "DIR,DIR" "0,1" bitfld.word 0x0 3. "OPM,OPM" "0,1" bitfld.word 0x0 2. "URS,URS" "0,1" bitfld.word 0x0 1. "UDIS,UDIS" "0,1" newline bitfld.word 0x0 0. "CEN,CEN" "0,1" group.long 0x4++0x7 line.long 0x0 "TIM3_CR2,TIM3 control register 2" hexmask.long.byte 0x0 20.--23. 1. "MMS2,MMS2" bitfld.long 0x0 18. "OIS6,OIS6" "0,1" bitfld.long 0x0 16. "OIS5,OIS5" "0,1" bitfld.long 0x0 14. "OIS4,OIS4" "0,1" bitfld.long 0x0 13. "OIS3N,OIS3N" "0,1" bitfld.long 0x0 12. "OIS3,OIS3" "0,1" bitfld.long 0x0 11. "OIS2N,OIS2N" "0,1" bitfld.long 0x0 10. "OIS2,OIS2" "0,1" newline bitfld.long 0x0 9. "OIS1N,OIS1N" "0,1" bitfld.long 0x0 8. "OIS1,OIS1" "0,1" bitfld.long 0x0 7. "TI1S,TI1S" "0,1" bitfld.long 0x0 4.--6. "MMS,MMS" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "CCDS,CCDS" "0,1" bitfld.long 0x0 2. "CCUS,CCUS" "0,1" bitfld.long 0x0 0. "CCPC,CCPC" "0,1" line.long 0x4 "TIM3_SMCR,TIM3 slave mode control register" bitfld.long 0x4 21. "TS4,TS4" "0,1" bitfld.long 0x4 20. "TS3,TS3" "0,1" bitfld.long 0x4 16. "SMS3,SMS3" "0,1" bitfld.long 0x4 15. "ETP,ETP" "0,1" bitfld.long 0x4 14. "ECE,ECE" "0,1" bitfld.long 0x4 12.--13. "ETPS,ETPS" "0,1,2,3" hexmask.long.byte 0x4 8.--11. 1. "ETF,ETF" bitfld.long 0x4 7. "MSM,MSM" "0,1" newline bitfld.long 0x4 4.--6. "TS,TS" "0,1,2,3,4,5,6,7" bitfld.long 0x4 0.--2. "SMS,SMS" "0,1,2,3,4,5,6,7" group.word 0xC++0x1 line.word 0x0 "TIM3_DIER,TIM3 DMA/interrupt enable register" bitfld.word 0x0 14. "TDE,TDE" "0,1" bitfld.word 0x0 13. "COMDE,COMDE" "0,1" bitfld.word 0x0 12. "CC4DE,CC4DE" "0,1" bitfld.word 0x0 11. "CC3DE,CC3DE" "0,1" bitfld.word 0x0 10. "CC2DE,CC2DE" "0,1" bitfld.word 0x0 9. "CC1DE,CC1DE" "0,1" bitfld.word 0x0 8. "UDE,UDE" "0,1" bitfld.word 0x0 7. "BIE,BIE" "0,1" newline bitfld.word 0x0 6. "TIE,TIE" "0,1" bitfld.word 0x0 5. "COMIE,COMIE" "0,1" bitfld.word 0x0 4. "CC4IE,CC4IE" "0,1" bitfld.word 0x0 3. "CC3IE,CC3IE" "0,1" bitfld.word 0x0 2. "CC2IE,CC2IE" "0,1" bitfld.word 0x0 1. "CC1IE,CC1IE" "0,1" bitfld.word 0x0 0. "UIE,UIE" "0,1" group.long 0x10++0x3 line.long 0x0 "TIM3_SR,TIM3 status register" bitfld.long 0x0 17. "CC6IF,CC6IF" "0,1" bitfld.long 0x0 16. "CC5IF,CC5IF" "0,1" bitfld.long 0x0 13. "SBIF,SBIF" "0,1" bitfld.long 0x0 12. "CC4OF,CC4OF" "0,1" bitfld.long 0x0 11. "CC3OF,CC3OF" "0,1" bitfld.long 0x0 10. "CC2OF,CC2OF" "0,1" bitfld.long 0x0 9. "CC1OF,CC1OF" "0,1" bitfld.long 0x0 8. "B2IF,B2IF" "0,1" newline bitfld.long 0x0 7. "BIF,BIF" "0,1" bitfld.long 0x0 6. "TIF,TIF" "0,1" bitfld.long 0x0 5. "COMIF,COMIF" "0,1" bitfld.long 0x0 4. "CC4IF,CC4IF" "0,1" bitfld.long 0x0 3. "CC3IF,CC3IF" "0,1" bitfld.long 0x0 2. "CC2IF,CC2IF" "0,1" bitfld.long 0x0 1. "CC1IF,CC1IF" "0,1" bitfld.long 0x0 0. "UIF,UIF" "0,1" wgroup.word 0x14++0x1 line.word 0x0 "TIM3_EGR,TIM3 event generation register" bitfld.word 0x0 8. "B2G,B2G" "0,1" bitfld.word 0x0 7. "BG,BG" "0,1" bitfld.word 0x0 6. "TG,TG" "0,1" bitfld.word 0x0 5. "COMG,COMG" "0,1" bitfld.word 0x0 4. "CC4G,CC4G" "0,1" bitfld.word 0x0 3. "CC3G,CC3G" "0,1" bitfld.word 0x0 2. "CC2G,CC2G" "0,1" bitfld.word 0x0 1. "CC1G,CC1G" "0,1" newline bitfld.word 0x0 0. "UG,UG" "0,1" group.long 0x18++0xF line.long 0x0 "TIM3_CCMR1ALTERNATE3,The same register can be used for input capture mode (this section) or for output compare mode (next section). The direction of a channel is defined by configuring the corresponding CCxS bits. All the other bits of this register have.." hexmask.long.byte 0x0 12.--15. 1. "IC2F,IC2F" bitfld.long 0x0 10.--11. "IC2PSC,IC2PSC" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,CC2S" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,IC1F" bitfld.long 0x0 2.--3. "IC1PSC,IC1PSC" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,CC1S" "0,1,2,3" line.long 0x4 "TIM3_CCMR2ALTERNATE19,The same register can be used for input capture mode (this section) or for output compare mode (next section). The direction of a channel is defined by configuring the corresponding CCxS bits. All the other bits of this register.." hexmask.long.byte 0x4 12.--15. 1. "IC4F,IC4F" bitfld.long 0x4 10.--11. "IC4PSC,IC4PSC" "0,1,2,3" bitfld.long 0x4 8.--9. "CC4S,CC4S" "0,1,2,3" hexmask.long.byte 0x4 4.--7. 1. "IC3F,IC3F" bitfld.long 0x4 2.--3. "IC3PSC,IC3PSC" "0,1,2,3" bitfld.long 0x4 0.--1. "CC3S,CC3S" "0,1,2,3" line.long 0x8 "TIM3_CCER,TIM3 capture/compare enable register" bitfld.long 0x8 21. "CC6P,CC6P" "0,1" bitfld.long 0x8 20. "CC6E,CC6E" "0,1" bitfld.long 0x8 17. "CC5P,CC5P" "0,1" bitfld.long 0x8 16. "CC5E,CC5E" "0,1" bitfld.long 0x8 15. "CC4NP,CC4NP" "0,1" bitfld.long 0x8 13. "CC4P,CC4P" "0,1" bitfld.long 0x8 12. "CC4E,CC4E" "0,1" bitfld.long 0x8 11. "CC3NP,CC3NP" "0,1" newline bitfld.long 0x8 10. "CC3NE,CC3NE" "0,1" bitfld.long 0x8 9. "CC3P,CC3P" "0,1" bitfld.long 0x8 8. "CC3E,CC3E" "0,1" bitfld.long 0x8 7. "CC2NP,CC2NP" "0,1" bitfld.long 0x8 6. "CC2NE,CC2NE" "0,1" bitfld.long 0x8 5. "CC2P,CC2P" "0,1" bitfld.long 0x8 4. "CC2E,CC2E" "0,1" bitfld.long 0x8 3. "CC1NP,CC1NP" "0,1" newline bitfld.long 0x8 2. "CC1NE,CC1NE" "0,1" bitfld.long 0x8 1. "CC1P,CC1P" "0,1" bitfld.long 0x8 0. "CC1E,CC1E" "0,1" line.long 0xC "TIM3_CNT,TIM3 counter" rbitfld.long 0xC 31. "UIFCPY,UIFCPY" "0,1" hexmask.long.word 0xC 0.--15. 1. "CNT,CNT" group.word 0x28++0x1 line.word 0x0 "TIM3_PSC,TIM3 prescaler" hexmask.word 0x0 0.--15. 1. "PSC,PSC" group.word 0x2C++0x1 line.word 0x0 "TIM3_ARR,TIM3 auto-reload register" hexmask.word 0x0 0.--15. 1. "ARR,ARR" group.word 0x30++0x1 line.word 0x0 "TIM3_RCR,TIM3 repetition counter register" hexmask.word 0x0 0.--15. 1. "REP,REP" group.word 0x34++0x1 line.word 0x0 "TIM3_CCR1,TIM3 capture/compare register 1" hexmask.word 0x0 0.--15. 1. "CCR1,CCR1" group.word 0x38++0x1 line.word 0x0 "TIM3_CCR2,TIM3 capture/compare register 2" hexmask.word 0x0 0.--15. 1. "CCR2,CCR2" group.word 0x3C++0x1 line.word 0x0 "TIM3_CCR3,TIM3 capture/compare register 3" hexmask.word 0x0 0.--15. 1. "CCR3,CCR3" group.word 0x40++0x1 line.word 0x0 "TIM3_CCR4,TIM3 capture/compare register 4" hexmask.word 0x0 0.--15. 1. "CCR4,CCR4" group.long 0x44++0x3 line.long 0x0 "TIM3_BDTR,As the bits BK2BID. BKBID. BK2DSRM. BKDSRM. BK2P. BK2E. BK2F[3:0]. BKF[3:0]. AOE. BKP. BKE. OSSI. OSSR and DTG[7:0] can be write-locked depending on the LOCK configuration. it can be necessary to configure all of them during the first write.." bitfld.long 0x0 29. "BK2BID,BK2BID" "0,1" bitfld.long 0x0 28. "BKBID,BKBID" "0,1" bitfld.long 0x0 27. "BK2DSRM,BK2DSRM" "0,1" bitfld.long 0x0 26. "BKDSRM,BKDSRM" "0,1" bitfld.long 0x0 25. "BK2P,BK2P" "0,1" bitfld.long 0x0 24. "BK2E,BK2E" "0,1" hexmask.long.byte 0x0 20.--23. 1. "BK2F,BK2F" hexmask.long.byte 0x0 16.--19. 1. "BKF,BKF" newline bitfld.long 0x0 15. "MOE,MOE" "0,1" bitfld.long 0x0 14. "AOE,AOE" "0,1" bitfld.long 0x0 13. "BKP,BKP" "0,1" bitfld.long 0x0 12. "BKE,BKE" "0,1" bitfld.long 0x0 11. "OSSR,OSSR" "0,1" bitfld.long 0x0 10. "OSSI,OSSI" "0,1" bitfld.long 0x0 8.--9. "LOCK,LOCK" "0,1,2,3" hexmask.long.byte 0x0 0.--7. 1. "DTG,DTG" group.word 0x48++0x1 line.word 0x0 "TIM3_DCR,TIM3 DMA control register" hexmask.word.byte 0x0 8.--12. 1. "DBL,DBL" hexmask.word.byte 0x0 0.--4. 1. "DBA,DBA" group.long 0x4C++0x3 line.long 0x0 "TIM3_DMAR,TIM3 DMA address for full transfer" hexmask.long 0x0 0.--31. 1. "DMAB,DMAB" group.long 0x54++0x7 line.long 0x0 "TIM3_CCMR3,The channels 5 and 6 can only be configured in output. Output compare mode:" bitfld.long 0x0 24. "OC6M3,OC6M3" "0,1" bitfld.long 0x0 16. "OC5M3,OC5M3" "0,1" bitfld.long 0x0 15. "OC6CE,OC6CE" "0,1" bitfld.long 0x0 12.--14. "OC6M,OC6M" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC6PE,OC6PE" "0,1" bitfld.long 0x0 10. "OC6FE,OC6FE" "0,1" bitfld.long 0x0 7. "OC5CE,OC5CE" "0,1" bitfld.long 0x0 4.--6. "OC5M,OC5M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3. "OC5PE,OC5PE" "0,1" bitfld.long 0x0 2. "OC5FE,OC5FE" "0,1" line.long 0x4 "TIM3_CCR5,TIM3 capture/compare register 5" bitfld.long 0x4 31. "GC5C3,GC5C3" "0,1" bitfld.long 0x4 30. "GC5C2,GC5C2" "0,1" bitfld.long 0x4 29. "GC5C1,GC5C1" "0,1" hexmask.long.word 0x4 0.--15. 1. "CCR5,CCR5" group.word 0x5C++0x1 line.word 0x0 "TIM3_CCR6,TIM3 capture/compare register 6" hexmask.word 0x0 0.--15. 1. "CCR6,CCR6" tree.end endif sif (cpuis("STM32MP151*")||cpuis("STM32MP153*")||cpuis("STM32MP157*")) tree "TIM4" base ad:0x40002000 group.word 0x0++0x1 line.word 0x0 "TIM4_CR1,TIM4 control register 1" bitfld.word 0x0 11. "UIFREMAP,UIFREMAP" "0,1" bitfld.word 0x0 8.--9. "CKD,CKD" "0,1,2,3" bitfld.word 0x0 7. "ARPE,ARPE" "0,1" bitfld.word 0x0 5.--6. "CMS,CMS" "0,1,2,3" bitfld.word 0x0 4. "DIR,DIR" "0,1" bitfld.word 0x0 3. "OPM,OPM" "0,1" bitfld.word 0x0 2. "URS,URS" "0,1" bitfld.word 0x0 1. "UDIS,UDIS" "0,1" newline bitfld.word 0x0 0. "CEN,CEN" "0,1" group.long 0x4++0x7 line.long 0x0 "TIM4_CR2,TIM4 control register 2" hexmask.long.byte 0x0 20.--23. 1. "MMS2,MMS2" bitfld.long 0x0 18. "OIS6,OIS6" "0,1" bitfld.long 0x0 16. "OIS5,OIS5" "0,1" bitfld.long 0x0 14. "OIS4,OIS4" "0,1" bitfld.long 0x0 13. "OIS3N,OIS3N" "0,1" bitfld.long 0x0 12. "OIS3,OIS3" "0,1" bitfld.long 0x0 11. "OIS2N,OIS2N" "0,1" bitfld.long 0x0 10. "OIS2,OIS2" "0,1" newline bitfld.long 0x0 9. "OIS1N,OIS1N" "0,1" bitfld.long 0x0 8. "OIS1,OIS1" "0,1" bitfld.long 0x0 7. "TI1S,TI1S" "0,1" bitfld.long 0x0 4.--6. "MMS,MMS" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "CCDS,CCDS" "0,1" bitfld.long 0x0 2. "CCUS,CCUS" "0,1" bitfld.long 0x0 0. "CCPC,CCPC" "0,1" line.long 0x4 "TIM4_SMCR,TIM4 slave mode control register" bitfld.long 0x4 21. "TS4,TS4" "0,1" bitfld.long 0x4 20. "TS3,TS3" "0,1" bitfld.long 0x4 16. "SMS3,SMS3" "0,1" bitfld.long 0x4 15. "ETP,ETP" "0,1" bitfld.long 0x4 14. "ECE,ECE" "0,1" bitfld.long 0x4 12.--13. "ETPS,ETPS" "0,1,2,3" hexmask.long.byte 0x4 8.--11. 1. "ETF,ETF" bitfld.long 0x4 7. "MSM,MSM" "0,1" newline bitfld.long 0x4 4.--6. "TS,TS" "0,1,2,3,4,5,6,7" bitfld.long 0x4 0.--2. "SMS,SMS" "0,1,2,3,4,5,6,7" group.word 0xC++0x1 line.word 0x0 "TIM4_DIER,TIM4 DMA/interrupt enable register" bitfld.word 0x0 14. "TDE,TDE" "0,1" bitfld.word 0x0 13. "COMDE,COMDE" "0,1" bitfld.word 0x0 12. "CC4DE,CC4DE" "0,1" bitfld.word 0x0 11. "CC3DE,CC3DE" "0,1" bitfld.word 0x0 10. "CC2DE,CC2DE" "0,1" bitfld.word 0x0 9. "CC1DE,CC1DE" "0,1" bitfld.word 0x0 8. "UDE,UDE" "0,1" bitfld.word 0x0 7. "BIE,BIE" "0,1" newline bitfld.word 0x0 6. "TIE,TIE" "0,1" bitfld.word 0x0 5. "COMIE,COMIE" "0,1" bitfld.word 0x0 4. "CC4IE,CC4IE" "0,1" bitfld.word 0x0 3. "CC3IE,CC3IE" "0,1" bitfld.word 0x0 2. "CC2IE,CC2IE" "0,1" bitfld.word 0x0 1. "CC1IE,CC1IE" "0,1" bitfld.word 0x0 0. "UIE,UIE" "0,1" group.long 0x10++0x3 line.long 0x0 "TIM4_SR,TIM4 status register" bitfld.long 0x0 17. "CC6IF,CC6IF" "0,1" bitfld.long 0x0 16. "CC5IF,CC5IF" "0,1" bitfld.long 0x0 13. "SBIF,SBIF" "0,1" bitfld.long 0x0 12. "CC4OF,CC4OF" "0,1" bitfld.long 0x0 11. "CC3OF,CC3OF" "0,1" bitfld.long 0x0 10. "CC2OF,CC2OF" "0,1" bitfld.long 0x0 9. "CC1OF,CC1OF" "0,1" bitfld.long 0x0 8. "B2IF,B2IF" "0,1" newline bitfld.long 0x0 7. "BIF,BIF" "0,1" bitfld.long 0x0 6. "TIF,TIF" "0,1" bitfld.long 0x0 5. "COMIF,COMIF" "0,1" bitfld.long 0x0 4. "CC4IF,CC4IF" "0,1" bitfld.long 0x0 3. "CC3IF,CC3IF" "0,1" bitfld.long 0x0 2. "CC2IF,CC2IF" "0,1" bitfld.long 0x0 1. "CC1IF,CC1IF" "0,1" bitfld.long 0x0 0. "UIF,UIF" "0,1" wgroup.word 0x14++0x1 line.word 0x0 "TIM4_EGR,TIM4 event generation register" bitfld.word 0x0 8. "B2G,B2G" "0,1" bitfld.word 0x0 7. "BG,BG" "0,1" bitfld.word 0x0 6. "TG,TG" "0,1" bitfld.word 0x0 5. "COMG,COMG" "0,1" bitfld.word 0x0 4. "CC4G,CC4G" "0,1" bitfld.word 0x0 3. "CC3G,CC3G" "0,1" bitfld.word 0x0 2. "CC2G,CC2G" "0,1" bitfld.word 0x0 1. "CC1G,CC1G" "0,1" newline bitfld.word 0x0 0. "UG,UG" "0,1" group.long 0x18++0xF line.long 0x0 "TIM4_CCMR1ALTERNATE4,The same register can be used for input capture mode (this section) or for output compare mode (next section). The direction of a channel is defined by configuring the corresponding CCxS bits. All the other bits of this register have.." hexmask.long.byte 0x0 12.--15. 1. "IC2F,IC2F" bitfld.long 0x0 10.--11. "IC2PSC,IC2PSC" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,CC2S" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,IC1F" bitfld.long 0x0 2.--3. "IC1PSC,IC1PSC" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,CC1S" "0,1,2,3" line.long 0x4 "TIM4_CCMR2ALTERNATE20,The same register can be used for input capture mode (this section) or for output compare mode (next section). The direction of a channel is defined by configuring the corresponding CCxS bits. All the other bits of this register.." hexmask.long.byte 0x4 12.--15. 1. "IC4F,IC4F" bitfld.long 0x4 10.--11. "IC4PSC,IC4PSC" "0,1,2,3" bitfld.long 0x4 8.--9. "CC4S,CC4S" "0,1,2,3" hexmask.long.byte 0x4 4.--7. 1. "IC3F,IC3F" bitfld.long 0x4 2.--3. "IC3PSC,IC3PSC" "0,1,2,3" bitfld.long 0x4 0.--1. "CC3S,CC3S" "0,1,2,3" line.long 0x8 "TIM4_CCER,TIM4 capture/compare enable register" bitfld.long 0x8 21. "CC6P,CC6P" "0,1" bitfld.long 0x8 20. "CC6E,CC6E" "0,1" bitfld.long 0x8 17. "CC5P,CC5P" "0,1" bitfld.long 0x8 16. "CC5E,CC5E" "0,1" bitfld.long 0x8 15. "CC4NP,CC4NP" "0,1" bitfld.long 0x8 13. "CC4P,CC4P" "0,1" bitfld.long 0x8 12. "CC4E,CC4E" "0,1" bitfld.long 0x8 11. "CC3NP,CC3NP" "0,1" newline bitfld.long 0x8 10. "CC3NE,CC3NE" "0,1" bitfld.long 0x8 9. "CC3P,CC3P" "0,1" bitfld.long 0x8 8. "CC3E,CC3E" "0,1" bitfld.long 0x8 7. "CC2NP,CC2NP" "0,1" bitfld.long 0x8 6. "CC2NE,CC2NE" "0,1" bitfld.long 0x8 5. "CC2P,CC2P" "0,1" bitfld.long 0x8 4. "CC2E,CC2E" "0,1" bitfld.long 0x8 3. "CC1NP,CC1NP" "0,1" newline bitfld.long 0x8 2. "CC1NE,CC1NE" "0,1" bitfld.long 0x8 1. "CC1P,CC1P" "0,1" bitfld.long 0x8 0. "CC1E,CC1E" "0,1" line.long 0xC "TIM4_CNT,TIM4 counter" rbitfld.long 0xC 31. "UIFCPY,UIFCPY" "0,1" hexmask.long.word 0xC 0.--15. 1. "CNT,CNT" group.word 0x28++0x1 line.word 0x0 "TIM4_PSC,TIM4 prescaler" hexmask.word 0x0 0.--15. 1. "PSC,PSC" group.word 0x2C++0x1 line.word 0x0 "TIM4_ARR,TIM4 auto-reload register" hexmask.word 0x0 0.--15. 1. "ARR,ARR" group.word 0x30++0x1 line.word 0x0 "TIM4_RCR,TIM4 repetition counter register" hexmask.word 0x0 0.--15. 1. "REP,REP" group.word 0x34++0x1 line.word 0x0 "TIM4_CCR1,TIM4 capture/compare register 1" hexmask.word 0x0 0.--15. 1. "CCR1,CCR1" group.word 0x38++0x1 line.word 0x0 "TIM4_CCR2,TIM4 capture/compare register 2" hexmask.word 0x0 0.--15. 1. "CCR2,CCR2" group.word 0x3C++0x1 line.word 0x0 "TIM4_CCR3,TIM4 capture/compare register 3" hexmask.word 0x0 0.--15. 1. "CCR3,CCR3" group.word 0x40++0x1 line.word 0x0 "TIM4_CCR4,TIM4 capture/compare register 4" hexmask.word 0x0 0.--15. 1. "CCR4,CCR4" group.long 0x44++0x3 line.long 0x0 "TIM4_BDTR,As the bits BK2BID. BKBID. BK2DSRM. BKDSRM. BK2P. BK2E. BK2F[3:0]. BKF[3:0]. AOE. BKP. BKE. OSSI. OSSR and DTG[7:0] can be write-locked depending on the LOCK configuration. it can be necessary to configure all of them during the first write.." bitfld.long 0x0 29. "BK2BID,BK2BID" "0,1" bitfld.long 0x0 28. "BKBID,BKBID" "0,1" bitfld.long 0x0 27. "BK2DSRM,BK2DSRM" "0,1" bitfld.long 0x0 26. "BKDSRM,BKDSRM" "0,1" bitfld.long 0x0 25. "BK2P,BK2P" "0,1" bitfld.long 0x0 24. "BK2E,BK2E" "0,1" hexmask.long.byte 0x0 20.--23. 1. "BK2F,BK2F" hexmask.long.byte 0x0 16.--19. 1. "BKF,BKF" newline bitfld.long 0x0 15. "MOE,MOE" "0,1" bitfld.long 0x0 14. "AOE,AOE" "0,1" bitfld.long 0x0 13. "BKP,BKP" "0,1" bitfld.long 0x0 12. "BKE,BKE" "0,1" bitfld.long 0x0 11. "OSSR,OSSR" "0,1" bitfld.long 0x0 10. "OSSI,OSSI" "0,1" bitfld.long 0x0 8.--9. "LOCK,LOCK" "0,1,2,3" hexmask.long.byte 0x0 0.--7. 1. "DTG,DTG" group.word 0x48++0x1 line.word 0x0 "TIM4_DCR,TIM4 DMA control register" hexmask.word.byte 0x0 8.--12. 1. "DBL,DBL" hexmask.word.byte 0x0 0.--4. 1. "DBA,DBA" group.long 0x4C++0x3 line.long 0x0 "TIM4_DMAR,TIM4 DMA address for full transfer" hexmask.long 0x0 0.--31. 1. "DMAB,DMAB" group.long 0x54++0x7 line.long 0x0 "TIM4_CCMR3,The channels 5 and 6 can only be configured in output. Output compare mode:" bitfld.long 0x0 24. "OC6M3,OC6M3" "0,1" bitfld.long 0x0 16. "OC5M3,OC5M3" "0,1" bitfld.long 0x0 15. "OC6CE,OC6CE" "0,1" bitfld.long 0x0 12.--14. "OC6M,OC6M" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC6PE,OC6PE" "0,1" bitfld.long 0x0 10. "OC6FE,OC6FE" "0,1" bitfld.long 0x0 7. "OC5CE,OC5CE" "0,1" bitfld.long 0x0 4.--6. "OC5M,OC5M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3. "OC5PE,OC5PE" "0,1" bitfld.long 0x0 2. "OC5FE,OC5FE" "0,1" line.long 0x4 "TIM4_CCR5,TIM4 capture/compare register 5" bitfld.long 0x4 31. "GC5C3,GC5C3" "0,1" bitfld.long 0x4 30. "GC5C2,GC5C2" "0,1" bitfld.long 0x4 29. "GC5C1,GC5C1" "0,1" hexmask.long.word 0x4 0.--15. 1. "CCR5,CCR5" group.word 0x5C++0x1 line.word 0x0 "TIM4_CCR6,TIM4 capture/compare register 6" hexmask.word 0x0 0.--15. 1. "CCR6,CCR6" tree.end endif sif (cpuis("STM32MP151*")||cpuis("STM32MP153*")||cpuis("STM32MP157*")) tree "TIM5" base ad:0x40003000 group.word 0x0++0x1 line.word 0x0 "TIM5_CR1,TIM5 control register 1" bitfld.word 0x0 11. "UIFREMAP,UIFREMAP" "0,1" bitfld.word 0x0 8.--9. "CKD,CKD" "0,1,2,3" bitfld.word 0x0 7. "ARPE,ARPE" "0,1" bitfld.word 0x0 5.--6. "CMS,CMS" "0,1,2,3" bitfld.word 0x0 4. "DIR,DIR" "0,1" bitfld.word 0x0 3. "OPM,OPM" "0,1" bitfld.word 0x0 2. "URS,URS" "0,1" bitfld.word 0x0 1. "UDIS,UDIS" "0,1" newline bitfld.word 0x0 0. "CEN,CEN" "0,1" group.long 0x4++0x7 line.long 0x0 "TIM5_CR2,TIM5 control register 2" hexmask.long.byte 0x0 20.--23. 1. "MMS2,MMS2" bitfld.long 0x0 18. "OIS6,OIS6" "0,1" bitfld.long 0x0 16. "OIS5,OIS5" "0,1" bitfld.long 0x0 14. "OIS4,OIS4" "0,1" bitfld.long 0x0 13. "OIS3N,OIS3N" "0,1" bitfld.long 0x0 12. "OIS3,OIS3" "0,1" bitfld.long 0x0 11. "OIS2N,OIS2N" "0,1" bitfld.long 0x0 10. "OIS2,OIS2" "0,1" newline bitfld.long 0x0 9. "OIS1N,OIS1N" "0,1" bitfld.long 0x0 8. "OIS1,OIS1" "0,1" bitfld.long 0x0 7. "TI1S,TI1S" "0,1" bitfld.long 0x0 4.--6. "MMS,MMS" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "CCDS,CCDS" "0,1" bitfld.long 0x0 2. "CCUS,CCUS" "0,1" bitfld.long 0x0 0. "CCPC,CCPC" "0,1" line.long 0x4 "TIM5_SMCR,TIM5 slave mode control register" bitfld.long 0x4 21. "TS4,TS4" "0,1" bitfld.long 0x4 20. "TS3,TS3" "0,1" bitfld.long 0x4 16. "SMS3,SMS3" "0,1" bitfld.long 0x4 15. "ETP,ETP" "0,1" bitfld.long 0x4 14. "ECE,ECE" "0,1" bitfld.long 0x4 12.--13. "ETPS,ETPS" "0,1,2,3" hexmask.long.byte 0x4 8.--11. 1. "ETF,ETF" bitfld.long 0x4 7. "MSM,MSM" "0,1" newline bitfld.long 0x4 4.--6. "TS,TS" "0,1,2,3,4,5,6,7" bitfld.long 0x4 0.--2. "SMS,SMS" "0,1,2,3,4,5,6,7" group.word 0xC++0x1 line.word 0x0 "TIM5_DIER,TIM5 DMA/interrupt enable register" bitfld.word 0x0 14. "TDE,TDE" "0,1" bitfld.word 0x0 13. "COMDE,COMDE" "0,1" bitfld.word 0x0 12. "CC4DE,CC4DE" "0,1" bitfld.word 0x0 11. "CC3DE,CC3DE" "0,1" bitfld.word 0x0 10. "CC2DE,CC2DE" "0,1" bitfld.word 0x0 9. "CC1DE,CC1DE" "0,1" bitfld.word 0x0 8. "UDE,UDE" "0,1" bitfld.word 0x0 7. "BIE,BIE" "0,1" newline bitfld.word 0x0 6. "TIE,TIE" "0,1" bitfld.word 0x0 5. "COMIE,COMIE" "0,1" bitfld.word 0x0 4. "CC4IE,CC4IE" "0,1" bitfld.word 0x0 3. "CC3IE,CC3IE" "0,1" bitfld.word 0x0 2. "CC2IE,CC2IE" "0,1" bitfld.word 0x0 1. "CC1IE,CC1IE" "0,1" bitfld.word 0x0 0. "UIE,UIE" "0,1" group.long 0x10++0x3 line.long 0x0 "TIM5_SR,TIM5 status register" bitfld.long 0x0 17. "CC6IF,CC6IF" "0,1" bitfld.long 0x0 16. "CC5IF,CC5IF" "0,1" bitfld.long 0x0 13. "SBIF,SBIF" "0,1" bitfld.long 0x0 12. "CC4OF,CC4OF" "0,1" bitfld.long 0x0 11. "CC3OF,CC3OF" "0,1" bitfld.long 0x0 10. "CC2OF,CC2OF" "0,1" bitfld.long 0x0 9. "CC1OF,CC1OF" "0,1" bitfld.long 0x0 8. "B2IF,B2IF" "0,1" newline bitfld.long 0x0 7. "BIF,BIF" "0,1" bitfld.long 0x0 6. "TIF,TIF" "0,1" bitfld.long 0x0 5. "COMIF,COMIF" "0,1" bitfld.long 0x0 4. "CC4IF,CC4IF" "0,1" bitfld.long 0x0 3. "CC3IF,CC3IF" "0,1" bitfld.long 0x0 2. "CC2IF,CC2IF" "0,1" bitfld.long 0x0 1. "CC1IF,CC1IF" "0,1" bitfld.long 0x0 0. "UIF,UIF" "0,1" wgroup.word 0x14++0x1 line.word 0x0 "TIM5_EGR,TIM5 event generation register" bitfld.word 0x0 8. "B2G,B2G" "0,1" bitfld.word 0x0 7. "BG,BG" "0,1" bitfld.word 0x0 6. "TG,TG" "0,1" bitfld.word 0x0 5. "COMG,COMG" "0,1" bitfld.word 0x0 4. "CC4G,CC4G" "0,1" bitfld.word 0x0 3. "CC3G,CC3G" "0,1" bitfld.word 0x0 2. "CC2G,CC2G" "0,1" bitfld.word 0x0 1. "CC1G,CC1G" "0,1" newline bitfld.word 0x0 0. "UG,UG" "0,1" group.long 0x18++0xF line.long 0x0 "TIM5_CCMR1ALTERNATE5,The same register can be used for input capture mode (this section) or for output compare mode (next section). The direction of a channel is defined by configuring the corresponding CCxS bits. All the other bits of this register have.." hexmask.long.byte 0x0 12.--15. 1. "IC2F,IC2F" bitfld.long 0x0 10.--11. "IC2PSC,IC2PSC" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,CC2S" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,IC1F" bitfld.long 0x0 2.--3. "IC1PSC,IC1PSC" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,CC1S" "0,1,2,3" line.long 0x4 "TIM5_CCMR2ALTERNATE21,The same register can be used for input capture mode (this section) or for output compare mode (next section). The direction of a channel is defined by configuring the corresponding CCxS bits. All the other bits of this register.." hexmask.long.byte 0x4 12.--15. 1. "IC4F,IC4F" bitfld.long 0x4 10.--11. "IC4PSC,IC4PSC" "0,1,2,3" bitfld.long 0x4 8.--9. "CC4S,CC4S" "0,1,2,3" hexmask.long.byte 0x4 4.--7. 1. "IC3F,IC3F" bitfld.long 0x4 2.--3. "IC3PSC,IC3PSC" "0,1,2,3" bitfld.long 0x4 0.--1. "CC3S,CC3S" "0,1,2,3" line.long 0x8 "TIM5_CCER,TIM5 capture/compare enable register" bitfld.long 0x8 21. "CC6P,CC6P" "0,1" bitfld.long 0x8 20. "CC6E,CC6E" "0,1" bitfld.long 0x8 17. "CC5P,CC5P" "0,1" bitfld.long 0x8 16. "CC5E,CC5E" "0,1" bitfld.long 0x8 15. "CC4NP,CC4NP" "0,1" bitfld.long 0x8 13. "CC4P,CC4P" "0,1" bitfld.long 0x8 12. "CC4E,CC4E" "0,1" bitfld.long 0x8 11. "CC3NP,CC3NP" "0,1" newline bitfld.long 0x8 10. "CC3NE,CC3NE" "0,1" bitfld.long 0x8 9. "CC3P,CC3P" "0,1" bitfld.long 0x8 8. "CC3E,CC3E" "0,1" bitfld.long 0x8 7. "CC2NP,CC2NP" "0,1" bitfld.long 0x8 6. "CC2NE,CC2NE" "0,1" bitfld.long 0x8 5. "CC2P,CC2P" "0,1" bitfld.long 0x8 4. "CC2E,CC2E" "0,1" bitfld.long 0x8 3. "CC1NP,CC1NP" "0,1" newline bitfld.long 0x8 2. "CC1NE,CC1NE" "0,1" bitfld.long 0x8 1. "CC1P,CC1P" "0,1" bitfld.long 0x8 0. "CC1E,CC1E" "0,1" line.long 0xC "TIM5_CNT,TIM5 counter" rbitfld.long 0xC 31. "UIFCPY,UIFCPY" "0,1" hexmask.long.word 0xC 0.--15. 1. "CNT,CNT" group.word 0x28++0x1 line.word 0x0 "TIM5_PSC,TIM5 prescaler" hexmask.word 0x0 0.--15. 1. "PSC,PSC" group.word 0x2C++0x1 line.word 0x0 "TIM5_ARR,TIM5 auto-reload register" hexmask.word 0x0 0.--15. 1. "ARR,ARR" group.word 0x30++0x1 line.word 0x0 "TIM5_RCR,TIM5 repetition counter register" hexmask.word 0x0 0.--15. 1. "REP,REP" group.word 0x34++0x1 line.word 0x0 "TIM5_CCR1,TIM5 capture/compare register 1" hexmask.word 0x0 0.--15. 1. "CCR1,CCR1" group.word 0x38++0x1 line.word 0x0 "TIM5_CCR2,TIM5 capture/compare register 2" hexmask.word 0x0 0.--15. 1. "CCR2,CCR2" group.word 0x3C++0x1 line.word 0x0 "TIM5_CCR3,TIM5 capture/compare register 3" hexmask.word 0x0 0.--15. 1. "CCR3,CCR3" group.word 0x40++0x1 line.word 0x0 "TIM5_CCR4,TIM5 capture/compare register 4" hexmask.word 0x0 0.--15. 1. "CCR4,CCR4" group.long 0x44++0x3 line.long 0x0 "TIM5_BDTR,As the bits BK2BID. BKBID. BK2DSRM. BKDSRM. BK2P. BK2E. BK2F[3:0]. BKF[3:0]. AOE. BKP. BKE. OSSI. OSSR and DTG[7:0] can be write-locked depending on the LOCK configuration. it can be necessary to configure all of them during the first write.." bitfld.long 0x0 29. "BK2BID,BK2BID" "0,1" bitfld.long 0x0 28. "BKBID,BKBID" "0,1" bitfld.long 0x0 27. "BK2DSRM,BK2DSRM" "0,1" bitfld.long 0x0 26. "BKDSRM,BKDSRM" "0,1" bitfld.long 0x0 25. "BK2P,BK2P" "0,1" bitfld.long 0x0 24. "BK2E,BK2E" "0,1" hexmask.long.byte 0x0 20.--23. 1. "BK2F,BK2F" hexmask.long.byte 0x0 16.--19. 1. "BKF,BKF" newline bitfld.long 0x0 15. "MOE,MOE" "0,1" bitfld.long 0x0 14. "AOE,AOE" "0,1" bitfld.long 0x0 13. "BKP,BKP" "0,1" bitfld.long 0x0 12. "BKE,BKE" "0,1" bitfld.long 0x0 11. "OSSR,OSSR" "0,1" bitfld.long 0x0 10. "OSSI,OSSI" "0,1" bitfld.long 0x0 8.--9. "LOCK,LOCK" "0,1,2,3" hexmask.long.byte 0x0 0.--7. 1. "DTG,DTG" group.word 0x48++0x1 line.word 0x0 "TIM5_DCR,TIM5 DMA control register" hexmask.word.byte 0x0 8.--12. 1. "DBL,DBL" hexmask.word.byte 0x0 0.--4. 1. "DBA,DBA" group.long 0x4C++0x3 line.long 0x0 "TIM5_DMAR,TIM5 DMA address for full transfer" hexmask.long 0x0 0.--31. 1. "DMAB,DMAB" group.long 0x54++0x7 line.long 0x0 "TIM5_CCMR3,The channels 5 and 6 can only be configured in output. Output compare mode:" bitfld.long 0x0 24. "OC6M3,OC6M3" "0,1" bitfld.long 0x0 16. "OC5M3,OC5M3" "0,1" bitfld.long 0x0 15. "OC6CE,OC6CE" "0,1" bitfld.long 0x0 12.--14. "OC6M,OC6M" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC6PE,OC6PE" "0,1" bitfld.long 0x0 10. "OC6FE,OC6FE" "0,1" bitfld.long 0x0 7. "OC5CE,OC5CE" "0,1" bitfld.long 0x0 4.--6. "OC5M,OC5M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3. "OC5PE,OC5PE" "0,1" bitfld.long 0x0 2. "OC5FE,OC5FE" "0,1" line.long 0x4 "TIM5_CCR5,TIM5 capture/compare register 5" bitfld.long 0x4 31. "GC5C3,GC5C3" "0,1" bitfld.long 0x4 30. "GC5C2,GC5C2" "0,1" bitfld.long 0x4 29. "GC5C1,GC5C1" "0,1" hexmask.long.word 0x4 0.--15. 1. "CCR5,CCR5" group.word 0x5C++0x1 line.word 0x0 "TIM5_CCR6,TIM5 capture/compare register 6" hexmask.word 0x0 0.--15. 1. "CCR6,CCR6" tree.end endif sif (cpuis("STM32MP151*")||cpuis("STM32MP153*")||cpuis("STM32MP157*")) tree "TIM6" base ad:0x40004000 group.word 0x0++0x1 line.word 0x0 "TIM6_CR1,TIM6 control register 1" bitfld.word 0x0 11. "UIFREMAP,UIFREMAP" "0,1" bitfld.word 0x0 8.--9. "CKD,CKD" "0,1,2,3" bitfld.word 0x0 7. "ARPE,ARPE" "0,1" bitfld.word 0x0 5.--6. "CMS,CMS" "0,1,2,3" bitfld.word 0x0 4. "DIR,DIR" "0,1" bitfld.word 0x0 3. "OPM,OPM" "0,1" bitfld.word 0x0 2. "URS,URS" "0,1" bitfld.word 0x0 1. "UDIS,UDIS" "0,1" newline bitfld.word 0x0 0. "CEN,CEN" "0,1" group.long 0x4++0x7 line.long 0x0 "TIM6_CR2,TIM6 control register 2" hexmask.long.byte 0x0 20.--23. 1. "MMS2,MMS2" bitfld.long 0x0 18. "OIS6,OIS6" "0,1" bitfld.long 0x0 16. "OIS5,OIS5" "0,1" bitfld.long 0x0 14. "OIS4,OIS4" "0,1" bitfld.long 0x0 13. "OIS3N,OIS3N" "0,1" bitfld.long 0x0 12. "OIS3,OIS3" "0,1" bitfld.long 0x0 11. "OIS2N,OIS2N" "0,1" bitfld.long 0x0 10. "OIS2,OIS2" "0,1" newline bitfld.long 0x0 9. "OIS1N,OIS1N" "0,1" bitfld.long 0x0 8. "OIS1,OIS1" "0,1" bitfld.long 0x0 7. "TI1S,TI1S" "0,1" bitfld.long 0x0 4.--6. "MMS,MMS" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "CCDS,CCDS" "0,1" bitfld.long 0x0 2. "CCUS,CCUS" "0,1" bitfld.long 0x0 0. "CCPC,CCPC" "0,1" line.long 0x4 "TIM6_SMCR,TIM6 slave mode control register" bitfld.long 0x4 21. "TS4,TS4" "0,1" bitfld.long 0x4 20. "TS3,TS3" "0,1" bitfld.long 0x4 16. "SMS3,SMS3" "0,1" bitfld.long 0x4 15. "ETP,ETP" "0,1" bitfld.long 0x4 14. "ECE,ECE" "0,1" bitfld.long 0x4 12.--13. "ETPS,ETPS" "0,1,2,3" hexmask.long.byte 0x4 8.--11. 1. "ETF,ETF" bitfld.long 0x4 7. "MSM,MSM" "0,1" newline bitfld.long 0x4 4.--6. "TS,TS" "0,1,2,3,4,5,6,7" bitfld.long 0x4 0.--2. "SMS,SMS" "0,1,2,3,4,5,6,7" group.word 0xC++0x1 line.word 0x0 "TIM6_DIER,TIM6 DMA/interrupt enable register" bitfld.word 0x0 14. "TDE,TDE" "0,1" bitfld.word 0x0 13. "COMDE,COMDE" "0,1" bitfld.word 0x0 12. "CC4DE,CC4DE" "0,1" bitfld.word 0x0 11. "CC3DE,CC3DE" "0,1" bitfld.word 0x0 10. "CC2DE,CC2DE" "0,1" bitfld.word 0x0 9. "CC1DE,CC1DE" "0,1" bitfld.word 0x0 8. "UDE,UDE" "0,1" bitfld.word 0x0 7. "BIE,BIE" "0,1" newline bitfld.word 0x0 6. "TIE,TIE" "0,1" bitfld.word 0x0 5. "COMIE,COMIE" "0,1" bitfld.word 0x0 4. "CC4IE,CC4IE" "0,1" bitfld.word 0x0 3. "CC3IE,CC3IE" "0,1" bitfld.word 0x0 2. "CC2IE,CC2IE" "0,1" bitfld.word 0x0 1. "CC1IE,CC1IE" "0,1" bitfld.word 0x0 0. "UIE,UIE" "0,1" group.long 0x10++0x3 line.long 0x0 "TIM6_SR,TIM6 status register" bitfld.long 0x0 17. "CC6IF,CC6IF" "0,1" bitfld.long 0x0 16. "CC5IF,CC5IF" "0,1" bitfld.long 0x0 13. "SBIF,SBIF" "0,1" bitfld.long 0x0 12. "CC4OF,CC4OF" "0,1" bitfld.long 0x0 11. "CC3OF,CC3OF" "0,1" bitfld.long 0x0 10. "CC2OF,CC2OF" "0,1" bitfld.long 0x0 9. "CC1OF,CC1OF" "0,1" bitfld.long 0x0 8. "B2IF,B2IF" "0,1" newline bitfld.long 0x0 7. "BIF,BIF" "0,1" bitfld.long 0x0 6. "TIF,TIF" "0,1" bitfld.long 0x0 5. "COMIF,COMIF" "0,1" bitfld.long 0x0 4. "CC4IF,CC4IF" "0,1" bitfld.long 0x0 3. "CC3IF,CC3IF" "0,1" bitfld.long 0x0 2. "CC2IF,CC2IF" "0,1" bitfld.long 0x0 1. "CC1IF,CC1IF" "0,1" bitfld.long 0x0 0. "UIF,UIF" "0,1" wgroup.word 0x14++0x1 line.word 0x0 "TIM6_EGR,TIM6 event generation register" bitfld.word 0x0 8. "B2G,B2G" "0,1" bitfld.word 0x0 7. "BG,BG" "0,1" bitfld.word 0x0 6. "TG,TG" "0,1" bitfld.word 0x0 5. "COMG,COMG" "0,1" bitfld.word 0x0 4. "CC4G,CC4G" "0,1" bitfld.word 0x0 3. "CC3G,CC3G" "0,1" bitfld.word 0x0 2. "CC2G,CC2G" "0,1" bitfld.word 0x0 1. "CC1G,CC1G" "0,1" newline bitfld.word 0x0 0. "UG,UG" "0,1" group.long 0x18++0xF line.long 0x0 "TIM6_CCMR1ALTERNATE6,The same register can be used for input capture mode (this section) or for output compare mode (next section). The direction of a channel is defined by configuring the corresponding CCxS bits. All the other bits of this register have.." hexmask.long.byte 0x0 12.--15. 1. "IC2F,IC2F" bitfld.long 0x0 10.--11. "IC2PSC,IC2PSC" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,CC2S" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,IC1F" bitfld.long 0x0 2.--3. "IC1PSC,IC1PSC" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,CC1S" "0,1,2,3" line.long 0x4 "TIM6_CCMR2ALTERNATE22,The same register can be used for input capture mode (this section) or for output compare mode (next section). The direction of a channel is defined by configuring the corresponding CCxS bits. All the other bits of this register.." hexmask.long.byte 0x4 12.--15. 1. "IC4F,IC4F" bitfld.long 0x4 10.--11. "IC4PSC,IC4PSC" "0,1,2,3" bitfld.long 0x4 8.--9. "CC4S,CC4S" "0,1,2,3" hexmask.long.byte 0x4 4.--7. 1. "IC3F,IC3F" bitfld.long 0x4 2.--3. "IC3PSC,IC3PSC" "0,1,2,3" bitfld.long 0x4 0.--1. "CC3S,CC3S" "0,1,2,3" line.long 0x8 "TIM6_CCER,TIM6 capture/compare enable register" bitfld.long 0x8 21. "CC6P,CC6P" "0,1" bitfld.long 0x8 20. "CC6E,CC6E" "0,1" bitfld.long 0x8 17. "CC5P,CC5P" "0,1" bitfld.long 0x8 16. "CC5E,CC5E" "0,1" bitfld.long 0x8 15. "CC4NP,CC4NP" "0,1" bitfld.long 0x8 13. "CC4P,CC4P" "0,1" bitfld.long 0x8 12. "CC4E,CC4E" "0,1" bitfld.long 0x8 11. "CC3NP,CC3NP" "0,1" newline bitfld.long 0x8 10. "CC3NE,CC3NE" "0,1" bitfld.long 0x8 9. "CC3P,CC3P" "0,1" bitfld.long 0x8 8. "CC3E,CC3E" "0,1" bitfld.long 0x8 7. "CC2NP,CC2NP" "0,1" bitfld.long 0x8 6. "CC2NE,CC2NE" "0,1" bitfld.long 0x8 5. "CC2P,CC2P" "0,1" bitfld.long 0x8 4. "CC2E,CC2E" "0,1" bitfld.long 0x8 3. "CC1NP,CC1NP" "0,1" newline bitfld.long 0x8 2. "CC1NE,CC1NE" "0,1" bitfld.long 0x8 1. "CC1P,CC1P" "0,1" bitfld.long 0x8 0. "CC1E,CC1E" "0,1" line.long 0xC "TIM6_CNT,TIM6 counter" rbitfld.long 0xC 31. "UIFCPY,UIFCPY" "0,1" hexmask.long.word 0xC 0.--15. 1. "CNT,CNT" group.word 0x28++0x1 line.word 0x0 "TIM6_PSC,TIM6 prescaler" hexmask.word 0x0 0.--15. 1. "PSC,PSC" group.word 0x2C++0x1 line.word 0x0 "TIM6_ARR,TIM6 auto-reload register" hexmask.word 0x0 0.--15. 1. "ARR,ARR" group.word 0x30++0x1 line.word 0x0 "TIM6_RCR,TIM6 repetition counter register" hexmask.word 0x0 0.--15. 1. "REP,REP" group.word 0x34++0x1 line.word 0x0 "TIM6_CCR1,TIM6 capture/compare register 1" hexmask.word 0x0 0.--15. 1. "CCR1,CCR1" group.word 0x38++0x1 line.word 0x0 "TIM6_CCR2,TIM6 capture/compare register 2" hexmask.word 0x0 0.--15. 1. "CCR2,CCR2" group.word 0x3C++0x1 line.word 0x0 "TIM6_CCR3,TIM6 capture/compare register 3" hexmask.word 0x0 0.--15. 1. "CCR3,CCR3" group.word 0x40++0x1 line.word 0x0 "TIM6_CCR4,TIM6 capture/compare register 4" hexmask.word 0x0 0.--15. 1. "CCR4,CCR4" group.long 0x44++0x3 line.long 0x0 "TIM6_BDTR,As the bits BK2BID. BKBID. BK2DSRM. BKDSRM. BK2P. BK2E. BK2F[3:0]. BKF[3:0]. AOE. BKP. BKE. OSSI. OSSR and DTG[7:0] can be write-locked depending on the LOCK configuration. it can be necessary to configure all of them during the first write.." bitfld.long 0x0 29. "BK2BID,BK2BID" "0,1" bitfld.long 0x0 28. "BKBID,BKBID" "0,1" bitfld.long 0x0 27. "BK2DSRM,BK2DSRM" "0,1" bitfld.long 0x0 26. "BKDSRM,BKDSRM" "0,1" bitfld.long 0x0 25. "BK2P,BK2P" "0,1" bitfld.long 0x0 24. "BK2E,BK2E" "0,1" hexmask.long.byte 0x0 20.--23. 1. "BK2F,BK2F" hexmask.long.byte 0x0 16.--19. 1. "BKF,BKF" newline bitfld.long 0x0 15. "MOE,MOE" "0,1" bitfld.long 0x0 14. "AOE,AOE" "0,1" bitfld.long 0x0 13. "BKP,BKP" "0,1" bitfld.long 0x0 12. "BKE,BKE" "0,1" bitfld.long 0x0 11. "OSSR,OSSR" "0,1" bitfld.long 0x0 10. "OSSI,OSSI" "0,1" bitfld.long 0x0 8.--9. "LOCK,LOCK" "0,1,2,3" hexmask.long.byte 0x0 0.--7. 1. "DTG,DTG" group.word 0x48++0x1 line.word 0x0 "TIM6_DCR,TIM6 DMA control register" hexmask.word.byte 0x0 8.--12. 1. "DBL,DBL" hexmask.word.byte 0x0 0.--4. 1. "DBA,DBA" group.long 0x4C++0x3 line.long 0x0 "TIM6_DMAR,TIM6 DMA address for full transfer" hexmask.long 0x0 0.--31. 1. "DMAB,DMAB" group.long 0x54++0x7 line.long 0x0 "TIM6_CCMR3,The channels 5 and 6 can only be configured in output. Output compare mode:" bitfld.long 0x0 24. "OC6M3,OC6M3" "0,1" bitfld.long 0x0 16. "OC5M3,OC5M3" "0,1" bitfld.long 0x0 15. "OC6CE,OC6CE" "0,1" bitfld.long 0x0 12.--14. "OC6M,OC6M" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC6PE,OC6PE" "0,1" bitfld.long 0x0 10. "OC6FE,OC6FE" "0,1" bitfld.long 0x0 7. "OC5CE,OC5CE" "0,1" bitfld.long 0x0 4.--6. "OC5M,OC5M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3. "OC5PE,OC5PE" "0,1" bitfld.long 0x0 2. "OC5FE,OC5FE" "0,1" line.long 0x4 "TIM6_CCR5,TIM6 capture/compare register 5" bitfld.long 0x4 31. "GC5C3,GC5C3" "0,1" bitfld.long 0x4 30. "GC5C2,GC5C2" "0,1" bitfld.long 0x4 29. "GC5C1,GC5C1" "0,1" hexmask.long.word 0x4 0.--15. 1. "CCR5,CCR5" group.word 0x5C++0x1 line.word 0x0 "TIM6_CCR6,TIM6 capture/compare register 6" hexmask.word 0x0 0.--15. 1. "CCR6,CCR6" tree.end endif sif (cpuis("STM32MP151*")||cpuis("STM32MP153*")||cpuis("STM32MP157*")) tree "TIM7" base ad:0x40005000 group.word 0x0++0x1 line.word 0x0 "TIM7_CR1,TIM7 control register 1" bitfld.word 0x0 11. "UIFREMAP,UIFREMAP" "0,1" bitfld.word 0x0 8.--9. "CKD,CKD" "0,1,2,3" bitfld.word 0x0 7. "ARPE,ARPE" "0,1" bitfld.word 0x0 5.--6. "CMS,CMS" "0,1,2,3" bitfld.word 0x0 4. "DIR,DIR" "0,1" bitfld.word 0x0 3. "OPM,OPM" "0,1" bitfld.word 0x0 2. "URS,URS" "0,1" bitfld.word 0x0 1. "UDIS,UDIS" "0,1" newline bitfld.word 0x0 0. "CEN,CEN" "0,1" group.long 0x4++0x7 line.long 0x0 "TIM7_CR2,TIM7 control register 2" hexmask.long.byte 0x0 20.--23. 1. "MMS2,MMS2" bitfld.long 0x0 18. "OIS6,OIS6" "0,1" bitfld.long 0x0 16. "OIS5,OIS5" "0,1" bitfld.long 0x0 14. "OIS4,OIS4" "0,1" bitfld.long 0x0 13. "OIS3N,OIS3N" "0,1" bitfld.long 0x0 12. "OIS3,OIS3" "0,1" bitfld.long 0x0 11. "OIS2N,OIS2N" "0,1" bitfld.long 0x0 10. "OIS2,OIS2" "0,1" newline bitfld.long 0x0 9. "OIS1N,OIS1N" "0,1" bitfld.long 0x0 8. "OIS1,OIS1" "0,1" bitfld.long 0x0 7. "TI1S,TI1S" "0,1" bitfld.long 0x0 4.--6. "MMS,MMS" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "CCDS,CCDS" "0,1" bitfld.long 0x0 2. "CCUS,CCUS" "0,1" bitfld.long 0x0 0. "CCPC,CCPC" "0,1" line.long 0x4 "TIM7_SMCR,TIM7 slave mode control register" bitfld.long 0x4 21. "TS4,TS4" "0,1" bitfld.long 0x4 20. "TS3,TS3" "0,1" bitfld.long 0x4 16. "SMS3,SMS3" "0,1" bitfld.long 0x4 15. "ETP,ETP" "0,1" bitfld.long 0x4 14. "ECE,ECE" "0,1" bitfld.long 0x4 12.--13. "ETPS,ETPS" "0,1,2,3" hexmask.long.byte 0x4 8.--11. 1. "ETF,ETF" bitfld.long 0x4 7. "MSM,MSM" "0,1" newline bitfld.long 0x4 4.--6. "TS,TS" "0,1,2,3,4,5,6,7" bitfld.long 0x4 0.--2. "SMS,SMS" "0,1,2,3,4,5,6,7" group.word 0xC++0x1 line.word 0x0 "TIM7_DIER,TIM7 DMA/interrupt enable register" bitfld.word 0x0 14. "TDE,TDE" "0,1" bitfld.word 0x0 13. "COMDE,COMDE" "0,1" bitfld.word 0x0 12. "CC4DE,CC4DE" "0,1" bitfld.word 0x0 11. "CC3DE,CC3DE" "0,1" bitfld.word 0x0 10. "CC2DE,CC2DE" "0,1" bitfld.word 0x0 9. "CC1DE,CC1DE" "0,1" bitfld.word 0x0 8. "UDE,UDE" "0,1" bitfld.word 0x0 7. "BIE,BIE" "0,1" newline bitfld.word 0x0 6. "TIE,TIE" "0,1" bitfld.word 0x0 5. "COMIE,COMIE" "0,1" bitfld.word 0x0 4. "CC4IE,CC4IE" "0,1" bitfld.word 0x0 3. "CC3IE,CC3IE" "0,1" bitfld.word 0x0 2. "CC2IE,CC2IE" "0,1" bitfld.word 0x0 1. "CC1IE,CC1IE" "0,1" bitfld.word 0x0 0. "UIE,UIE" "0,1" group.long 0x10++0x3 line.long 0x0 "TIM7_SR,TIM7 status register" bitfld.long 0x0 17. "CC6IF,CC6IF" "0,1" bitfld.long 0x0 16. "CC5IF,CC5IF" "0,1" bitfld.long 0x0 13. "SBIF,SBIF" "0,1" bitfld.long 0x0 12. "CC4OF,CC4OF" "0,1" bitfld.long 0x0 11. "CC3OF,CC3OF" "0,1" bitfld.long 0x0 10. "CC2OF,CC2OF" "0,1" bitfld.long 0x0 9. "CC1OF,CC1OF" "0,1" bitfld.long 0x0 8. "B2IF,B2IF" "0,1" newline bitfld.long 0x0 7. "BIF,BIF" "0,1" bitfld.long 0x0 6. "TIF,TIF" "0,1" bitfld.long 0x0 5. "COMIF,COMIF" "0,1" bitfld.long 0x0 4. "CC4IF,CC4IF" "0,1" bitfld.long 0x0 3. "CC3IF,CC3IF" "0,1" bitfld.long 0x0 2. "CC2IF,CC2IF" "0,1" bitfld.long 0x0 1. "CC1IF,CC1IF" "0,1" bitfld.long 0x0 0. "UIF,UIF" "0,1" wgroup.word 0x14++0x1 line.word 0x0 "TIM7_EGR,TIM7 event generation register" bitfld.word 0x0 8. "B2G,B2G" "0,1" bitfld.word 0x0 7. "BG,BG" "0,1" bitfld.word 0x0 6. "TG,TG" "0,1" bitfld.word 0x0 5. "COMG,COMG" "0,1" bitfld.word 0x0 4. "CC4G,CC4G" "0,1" bitfld.word 0x0 3. "CC3G,CC3G" "0,1" bitfld.word 0x0 2. "CC2G,CC2G" "0,1" bitfld.word 0x0 1. "CC1G,CC1G" "0,1" newline bitfld.word 0x0 0. "UG,UG" "0,1" group.long 0x18++0xF line.long 0x0 "TIM7_CCMR1ALTERNATE7,The same register can be used for input capture mode (this section) or for output compare mode (next section). The direction of a channel is defined by configuring the corresponding CCxS bits. All the other bits of this register have.." hexmask.long.byte 0x0 12.--15. 1. "IC2F,IC2F" bitfld.long 0x0 10.--11. "IC2PSC,IC2PSC" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,CC2S" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,IC1F" bitfld.long 0x0 2.--3. "IC1PSC,IC1PSC" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,CC1S" "0,1,2,3" line.long 0x4 "TIM7_CCMR2ALTERNATE23,The same register can be used for input capture mode (this section) or for output compare mode (next section). The direction of a channel is defined by configuring the corresponding CCxS bits. All the other bits of this register.." hexmask.long.byte 0x4 12.--15. 1. "IC4F,IC4F" bitfld.long 0x4 10.--11. "IC4PSC,IC4PSC" "0,1,2,3" bitfld.long 0x4 8.--9. "CC4S,CC4S" "0,1,2,3" hexmask.long.byte 0x4 4.--7. 1. "IC3F,IC3F" bitfld.long 0x4 2.--3. "IC3PSC,IC3PSC" "0,1,2,3" bitfld.long 0x4 0.--1. "CC3S,CC3S" "0,1,2,3" line.long 0x8 "TIM7_CCER,TIM7 capture/compare enable register" bitfld.long 0x8 21. "CC6P,CC6P" "0,1" bitfld.long 0x8 20. "CC6E,CC6E" "0,1" bitfld.long 0x8 17. "CC5P,CC5P" "0,1" bitfld.long 0x8 16. "CC5E,CC5E" "0,1" bitfld.long 0x8 15. "CC4NP,CC4NP" "0,1" bitfld.long 0x8 13. "CC4P,CC4P" "0,1" bitfld.long 0x8 12. "CC4E,CC4E" "0,1" bitfld.long 0x8 11. "CC3NP,CC3NP" "0,1" newline bitfld.long 0x8 10. "CC3NE,CC3NE" "0,1" bitfld.long 0x8 9. "CC3P,CC3P" "0,1" bitfld.long 0x8 8. "CC3E,CC3E" "0,1" bitfld.long 0x8 7. "CC2NP,CC2NP" "0,1" bitfld.long 0x8 6. "CC2NE,CC2NE" "0,1" bitfld.long 0x8 5. "CC2P,CC2P" "0,1" bitfld.long 0x8 4. "CC2E,CC2E" "0,1" bitfld.long 0x8 3. "CC1NP,CC1NP" "0,1" newline bitfld.long 0x8 2. "CC1NE,CC1NE" "0,1" bitfld.long 0x8 1. "CC1P,CC1P" "0,1" bitfld.long 0x8 0. "CC1E,CC1E" "0,1" line.long 0xC "TIM7_CNT,TIM7 counter" rbitfld.long 0xC 31. "UIFCPY,UIFCPY" "0,1" hexmask.long.word 0xC 0.--15. 1. "CNT,CNT" group.word 0x28++0x1 line.word 0x0 "TIM7_PSC,TIM7 prescaler" hexmask.word 0x0 0.--15. 1. "PSC,PSC" group.word 0x2C++0x1 line.word 0x0 "TIM7_ARR,TIM7 auto-reload register" hexmask.word 0x0 0.--15. 1. "ARR,ARR" group.word 0x30++0x1 line.word 0x0 "TIM7_RCR,TIM7 repetition counter register" hexmask.word 0x0 0.--15. 1. "REP,REP" group.word 0x34++0x1 line.word 0x0 "TIM7_CCR1,TIM7 capture/compare register 1" hexmask.word 0x0 0.--15. 1. "CCR1,CCR1" group.word 0x38++0x1 line.word 0x0 "TIM7_CCR2,TIM7 capture/compare register 2" hexmask.word 0x0 0.--15. 1. "CCR2,CCR2" group.word 0x3C++0x1 line.word 0x0 "TIM7_CCR3,TIM7 capture/compare register 3" hexmask.word 0x0 0.--15. 1. "CCR3,CCR3" group.word 0x40++0x1 line.word 0x0 "TIM7_CCR4,TIM7 capture/compare register 4" hexmask.word 0x0 0.--15. 1. "CCR4,CCR4" group.long 0x44++0x3 line.long 0x0 "TIM7_BDTR,As the bits BK2BID. BKBID. BK2DSRM. BKDSRM. BK2P. BK2E. BK2F[3:0]. BKF[3:0]. AOE. BKP. BKE. OSSI. OSSR and DTG[7:0] can be write-locked depending on the LOCK configuration. it can be necessary to configure all of them during the first write.." bitfld.long 0x0 29. "BK2BID,BK2BID" "0,1" bitfld.long 0x0 28. "BKBID,BKBID" "0,1" bitfld.long 0x0 27. "BK2DSRM,BK2DSRM" "0,1" bitfld.long 0x0 26. "BKDSRM,BKDSRM" "0,1" bitfld.long 0x0 25. "BK2P,BK2P" "0,1" bitfld.long 0x0 24. "BK2E,BK2E" "0,1" hexmask.long.byte 0x0 20.--23. 1. "BK2F,BK2F" hexmask.long.byte 0x0 16.--19. 1. "BKF,BKF" newline bitfld.long 0x0 15. "MOE,MOE" "0,1" bitfld.long 0x0 14. "AOE,AOE" "0,1" bitfld.long 0x0 13. "BKP,BKP" "0,1" bitfld.long 0x0 12. "BKE,BKE" "0,1" bitfld.long 0x0 11. "OSSR,OSSR" "0,1" bitfld.long 0x0 10. "OSSI,OSSI" "0,1" bitfld.long 0x0 8.--9. "LOCK,LOCK" "0,1,2,3" hexmask.long.byte 0x0 0.--7. 1. "DTG,DTG" group.word 0x48++0x1 line.word 0x0 "TIM7_DCR,TIM7 DMA control register" hexmask.word.byte 0x0 8.--12. 1. "DBL,DBL" hexmask.word.byte 0x0 0.--4. 1. "DBA,DBA" group.long 0x4C++0x3 line.long 0x0 "TIM7_DMAR,TIM7 DMA address for full transfer" hexmask.long 0x0 0.--31. 1. "DMAB,DMAB" group.long 0x54++0x7 line.long 0x0 "TIM7_CCMR3,The channels 5 and 6 can only be configured in output. Output compare mode:" bitfld.long 0x0 24. "OC6M3,OC6M3" "0,1" bitfld.long 0x0 16. "OC5M3,OC5M3" "0,1" bitfld.long 0x0 15. "OC6CE,OC6CE" "0,1" bitfld.long 0x0 12.--14. "OC6M,OC6M" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC6PE,OC6PE" "0,1" bitfld.long 0x0 10. "OC6FE,OC6FE" "0,1" bitfld.long 0x0 7. "OC5CE,OC5CE" "0,1" bitfld.long 0x0 4.--6. "OC5M,OC5M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3. "OC5PE,OC5PE" "0,1" bitfld.long 0x0 2. "OC5FE,OC5FE" "0,1" line.long 0x4 "TIM7_CCR5,TIM7 capture/compare register 5" bitfld.long 0x4 31. "GC5C3,GC5C3" "0,1" bitfld.long 0x4 30. "GC5C2,GC5C2" "0,1" bitfld.long 0x4 29. "GC5C1,GC5C1" "0,1" hexmask.long.word 0x4 0.--15. 1. "CCR5,CCR5" group.word 0x5C++0x1 line.word 0x0 "TIM7_CCR6,TIM7 capture/compare register 6" hexmask.word 0x0 0.--15. 1. "CCR6,CCR6" tree.end endif sif (cpuis("STM32MP151*")||cpuis("STM32MP153*")||cpuis("STM32MP157*")) tree "TIM8" base ad:0x44001000 group.word 0x0++0x1 line.word 0x0 "TIM8_CR1,TIM8 control register 1" bitfld.word 0x0 11. "UIFREMAP,UIFREMAP" "0,1" bitfld.word 0x0 8.--9. "CKD,CKD" "0,1,2,3" bitfld.word 0x0 7. "ARPE,ARPE" "0,1" bitfld.word 0x0 5.--6. "CMS,CMS" "0,1,2,3" bitfld.word 0x0 4. "DIR,DIR" "0,1" bitfld.word 0x0 3. "OPM,OPM" "0,1" bitfld.word 0x0 2. "URS,URS" "0,1" newline bitfld.word 0x0 1. "UDIS,UDIS" "0,1" bitfld.word 0x0 0. "CEN,CEN" "0,1" group.long 0x4++0x7 line.long 0x0 "TIM8_CR2,TIM8 control register 2" hexmask.long.byte 0x0 20.--23. 1. "MMS2,MMS2" bitfld.long 0x0 18. "OIS6,OIS6" "0,1" bitfld.long 0x0 16. "OIS5,OIS5" "0,1" bitfld.long 0x0 14. "OIS4,OIS4" "0,1" bitfld.long 0x0 13. "OIS3N,OIS3N" "0,1" bitfld.long 0x0 12. "OIS3,OIS3" "0,1" bitfld.long 0x0 11. "OIS2N,OIS2N" "0,1" newline bitfld.long 0x0 10. "OIS2,OIS2" "0,1" bitfld.long 0x0 9. "OIS1N,OIS1N" "0,1" bitfld.long 0x0 8. "OIS1,OIS1" "0,1" bitfld.long 0x0 7. "TI1S,TI1S" "0,1" bitfld.long 0x0 4.--6. "MMS,MMS" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "CCDS,CCDS" "0,1" bitfld.long 0x0 2. "CCUS,CCUS" "0,1" newline bitfld.long 0x0 0. "CCPC,CCPC" "0,1" line.long 0x4 "TIM8_SMCR,TIM8 slave mode control register" bitfld.long 0x4 21. "TS4,TS4" "0,1" bitfld.long 0x4 20. "TS3,TS3" "0,1" bitfld.long 0x4 16. "SMS3,SMS3" "0,1" bitfld.long 0x4 15. "ETP,ETP" "0,1" bitfld.long 0x4 14. "ECE,ECE" "0,1" bitfld.long 0x4 12.--13. "ETPS,ETPS" "0,1,2,3" hexmask.long.byte 0x4 8.--11. 1. "ETF,ETF" newline bitfld.long 0x4 7. "MSM,MSM" "0,1" bitfld.long 0x4 4.--6. "TS,TS" "0,1,2,3,4,5,6,7" bitfld.long 0x4 0.--2. "SMS,SMS" "0,1,2,3,4,5,6,7" group.word 0xC++0x1 line.word 0x0 "TIM8_DIER,TIM8 DMA/interrupt enable register" bitfld.word 0x0 14. "TDE,TDE" "0,1" bitfld.word 0x0 13. "COMDE,COMDE" "0,1" bitfld.word 0x0 12. "CC4DE,CC4DE" "0,1" bitfld.word 0x0 11. "CC3DE,CC3DE" "0,1" bitfld.word 0x0 10. "CC2DE,CC2DE" "0,1" bitfld.word 0x0 9. "CC1DE,CC1DE" "0,1" bitfld.word 0x0 8. "UDE,UDE" "0,1" newline bitfld.word 0x0 7. "BIE,BIE" "0,1" bitfld.word 0x0 6. "TIE,TIE" "0,1" bitfld.word 0x0 5. "COMIE,COMIE" "0,1" bitfld.word 0x0 4. "CC4IE,CC4IE" "0,1" bitfld.word 0x0 3. "CC3IE,CC3IE" "0,1" bitfld.word 0x0 2. "CC2IE,CC2IE" "0,1" bitfld.word 0x0 1. "CC1IE,CC1IE" "0,1" newline bitfld.word 0x0 0. "UIE,UIE" "0,1" group.long 0x10++0x3 line.long 0x0 "TIM8_SR,TIM8 status register" bitfld.long 0x0 17. "CC6IF,CC6IF" "0,1" bitfld.long 0x0 16. "CC5IF,CC5IF" "0,1" bitfld.long 0x0 13. "SBIF,SBIF" "0,1" bitfld.long 0x0 12. "CC4OF,CC4OF" "0,1" bitfld.long 0x0 11. "CC3OF,CC3OF" "0,1" bitfld.long 0x0 10. "CC2OF,CC2OF" "0,1" bitfld.long 0x0 9. "CC1OF,CC1OF" "0,1" newline bitfld.long 0x0 8. "B2IF,B2IF" "0,1" bitfld.long 0x0 7. "BIF,BIF" "0,1" bitfld.long 0x0 6. "TIF,TIF" "0,1" bitfld.long 0x0 5. "COMIF,COMIF" "0,1" bitfld.long 0x0 4. "CC4IF,CC4IF" "0,1" bitfld.long 0x0 3. "CC3IF,CC3IF" "0,1" bitfld.long 0x0 2. "CC2IF,CC2IF" "0,1" newline bitfld.long 0x0 1. "CC1IF,CC1IF" "0,1" bitfld.long 0x0 0. "UIF,UIF" "0,1" wgroup.word 0x14++0x1 line.word 0x0 "TIM8_EGR,TIM8 event generation register" bitfld.word 0x0 8. "B2G,B2G" "0,1" bitfld.word 0x0 7. "BG,BG" "0,1" bitfld.word 0x0 6. "TG,TG" "0,1" bitfld.word 0x0 5. "COMG,COMG" "0,1" bitfld.word 0x0 4. "CC4G,CC4G" "0,1" bitfld.word 0x0 3. "CC3G,CC3G" "0,1" bitfld.word 0x0 2. "CC2G,CC2G" "0,1" newline bitfld.word 0x0 1. "CC1G,CC1G" "0,1" bitfld.word 0x0 0. "UG,UG" "0,1" group.long 0x18++0xF line.long 0x0 "TIM8_CCMR1ALTERNATE8,The same register can be used for input capture mode (this section) or for output compare mode (next section). The direction of a channel is defined by configuring the corresponding CCxS bits. All the other bits of this register have.." hexmask.long.byte 0x0 12.--15. 1. "IC2F,IC2F" bitfld.long 0x0 10.--11. "IC2PSC,IC2PSC" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,CC2S" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,IC1F" bitfld.long 0x0 2.--3. "IC1PSC,IC1PSC" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,CC1S" "0,1,2,3" line.long 0x4 "TIM8_CCMR2ALTERNATE24,The same register can be used for input capture mode (this section) or for output compare mode (next section). The direction of a channel is defined by configuring the corresponding CCxS bits. All the other bits of this register.." hexmask.long.byte 0x4 12.--15. 1. "IC4F,IC4F" bitfld.long 0x4 10.--11. "IC4PSC,IC4PSC" "0,1,2,3" bitfld.long 0x4 8.--9. "CC4S,CC4S" "0,1,2,3" hexmask.long.byte 0x4 4.--7. 1. "IC3F,IC3F" bitfld.long 0x4 2.--3. "IC3PSC,IC3PSC" "0,1,2,3" bitfld.long 0x4 0.--1. "CC3S,CC3S" "0,1,2,3" line.long 0x8 "TIM8_CCER,TIM8 capture/compare enable register" bitfld.long 0x8 21. "CC6P,CC6P" "0,1" bitfld.long 0x8 20. "CC6E,CC6E" "0,1" bitfld.long 0x8 17. "CC5P,CC5P" "0,1" bitfld.long 0x8 16. "CC5E,CC5E" "0,1" bitfld.long 0x8 15. "CC4NP,CC4NP" "0,1" bitfld.long 0x8 13. "CC4P,CC4P" "0,1" bitfld.long 0x8 12. "CC4E,CC4E" "0,1" newline bitfld.long 0x8 11. "CC3NP,CC3NP" "0,1" bitfld.long 0x8 10. "CC3NE,CC3NE" "0,1" bitfld.long 0x8 9. "CC3P,CC3P" "0,1" bitfld.long 0x8 8. "CC3E,CC3E" "0,1" bitfld.long 0x8 7. "CC2NP,CC2NP" "0,1" bitfld.long 0x8 6. "CC2NE,CC2NE" "0,1" bitfld.long 0x8 5. "CC2P,CC2P" "0,1" newline bitfld.long 0x8 4. "CC2E,CC2E" "0,1" bitfld.long 0x8 3. "CC1NP,CC1NP" "0,1" bitfld.long 0x8 2. "CC1NE,CC1NE" "0,1" bitfld.long 0x8 1. "CC1P,CC1P" "0,1" bitfld.long 0x8 0. "CC1E,CC1E" "0,1" line.long 0xC "TIM8_CNT,TIM8 counter" rbitfld.long 0xC 31. "UIFCPY,UIFCPY" "0,1" hexmask.long.word 0xC 0.--15. 1. "CNT,CNT" group.word 0x28++0x1 line.word 0x0 "TIM8_PSC,TIM8 prescaler" hexmask.word 0x0 0.--15. 1. "PSC,PSC" group.word 0x2C++0x1 line.word 0x0 "TIM8_ARR,TIM8 auto-reload register" hexmask.word 0x0 0.--15. 1. "ARR,ARR" group.word 0x30++0x1 line.word 0x0 "TIM8_RCR,TIM8 repetition counter register" hexmask.word 0x0 0.--15. 1. "REP,REP" group.word 0x34++0x1 line.word 0x0 "TIM8_CCR1,TIM8 capture/compare register 1" hexmask.word 0x0 0.--15. 1. "CCR1,CCR1" group.word 0x38++0x1 line.word 0x0 "TIM8_CCR2,TIM8 capture/compare register 2" hexmask.word 0x0 0.--15. 1. "CCR2,CCR2" group.word 0x3C++0x1 line.word 0x0 "TIM8_CCR3,TIM8 capture/compare register 3" hexmask.word 0x0 0.--15. 1. "CCR3,CCR3" group.word 0x40++0x1 line.word 0x0 "TIM8_CCR4,TIM8 capture/compare register 4" hexmask.word 0x0 0.--15. 1. "CCR4,CCR4" group.long 0x44++0x3 line.long 0x0 "TIM8_BDTR,As the bits BK2BID. BKBID. BK2DSRM. BKDSRM. BK2P. BK2E. BK2F[3:0]. BKF[3:0]. AOE. BKP. BKE. OSSI. OSSR and DTG[7:0] can be write-locked depending on the LOCK configuration. it can be necessary to configure all of them during the first write.." bitfld.long 0x0 29. "BK2BID,BK2BID" "0,1" bitfld.long 0x0 28. "BKBID,BKBID" "0,1" bitfld.long 0x0 27. "BK2DSRM,BK2DSRM" "0,1" bitfld.long 0x0 26. "BKDSRM,BKDSRM" "0,1" bitfld.long 0x0 25. "BK2P,BK2P" "0,1" bitfld.long 0x0 24. "BK2E,BK2E" "0,1" hexmask.long.byte 0x0 20.--23. 1. "BK2F,BK2F" newline hexmask.long.byte 0x0 16.--19. 1. "BKF,BKF" bitfld.long 0x0 15. "MOE,MOE" "0,1" bitfld.long 0x0 14. "AOE,AOE" "0,1" bitfld.long 0x0 13. "BKP,BKP" "0,1" bitfld.long 0x0 12. "BKE,BKE" "0,1" bitfld.long 0x0 11. "OSSR,OSSR" "0,1" bitfld.long 0x0 10. "OSSI,OSSI" "0,1" newline bitfld.long 0x0 8.--9. "LOCK,LOCK" "0,1,2,3" hexmask.long.byte 0x0 0.--7. 1. "DTG,DTG" group.word 0x48++0x1 line.word 0x0 "TIM8_DCR,TIM8 DMA control register" hexmask.word.byte 0x0 8.--12. 1. "DBL,DBL" hexmask.word.byte 0x0 0.--4. 1. "DBA,DBA" group.long 0x4C++0x3 line.long 0x0 "TIM8_DMAR,TIM8 DMA address for full transfer" hexmask.long 0x0 0.--31. 1. "DMAB,DMAB" group.long 0x54++0x7 line.long 0x0 "TIM8_CCMR3,The channels 5 and 6 can only be configured in output. Output compare mode:" bitfld.long 0x0 24. "OC6M3,OC6M3" "0,1" bitfld.long 0x0 16. "OC5M3,OC5M3" "0,1" bitfld.long 0x0 15. "OC6CE,OC6CE" "0,1" bitfld.long 0x0 12.--14. "OC6M,OC6M" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC6PE,OC6PE" "0,1" bitfld.long 0x0 10. "OC6FE,OC6FE" "0,1" bitfld.long 0x0 7. "OC5CE,OC5CE" "0,1" newline bitfld.long 0x0 4.--6. "OC5M,OC5M" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "OC5PE,OC5PE" "0,1" bitfld.long 0x0 2. "OC5FE,OC5FE" "0,1" line.long 0x4 "TIM8_CCR5,TIM8 capture/compare register 5" bitfld.long 0x4 31. "GC5C3,GC5C3" "0,1" bitfld.long 0x4 30. "GC5C2,GC5C2" "0,1" bitfld.long 0x4 29. "GC5C1,GC5C1" "0,1" hexmask.long.word 0x4 0.--15. 1. "CCR5,CCR5" group.word 0x5C++0x1 line.word 0x0 "TIM8_CCR6,TIM8 capture/compare register 6" hexmask.word 0x0 0.--15. 1. "CCR6,CCR6" group.long 0x60++0xB line.long 0x0 "TIM8_AF1,TIM8 Alternate function option register 1" hexmask.long.byte 0x0 14.--17. 1. "ETRSEL,ETRSEL" bitfld.long 0x0 9. "BKINP,BKINP" "0,1" bitfld.long 0x0 8. "BKDF1BK2E,BKDF1BK2E" "0,1" bitfld.long 0x0 0. "BKINE,BKINE" "0,1" line.long 0x4 "TIM8_AF2,TIM8 Alternate function option register 2" bitfld.long 0x4 9. "BK2INP,BK2INP" "0,1" bitfld.long 0x4 8. "BK2DF1BK3E,BK2DF1BK3E" "0,1" bitfld.long 0x4 0. "BK2INE,BK2INE" "0,1" line.long 0x8 "TIM8_TISEL,TIM8 timer input selection register" hexmask.long.byte 0x8 24.--27. 1. "TI4SEL,TI4SEL" hexmask.long.byte 0x8 16.--19. 1. "TI3SEL,TI3SEL" hexmask.long.byte 0x8 8.--11. 1. "TI2SEL,TI2SEL" hexmask.long.byte 0x8 0.--3. 1. "TI1SEL,TI1SEL" tree.end endif sif (cpuis("STM32MP151*")||cpuis("STM32MP153*")||cpuis("STM32MP157*")) tree "TIM12" base ad:0x40006000 group.word 0x0++0x1 line.word 0x0 "TIM12_CR1,TIM12 control register 1" bitfld.word 0x0 11. "UIFREMAP,UIFREMAP" "0,1" bitfld.word 0x0 8.--9. "CKD,CKD" "0,1,2,3" bitfld.word 0x0 7. "ARPE,ARPE" "0,1" bitfld.word 0x0 3. "OPM,OPM" "0,1" bitfld.word 0x0 2. "URS,URS" "0,1" bitfld.word 0x0 1. "UDIS,UDIS" "0,1" bitfld.word 0x0 0. "CEN,CEN" "0,1" group.long 0x4++0x7 line.long 0x0 "TIM12_CR2,TIM12 control register 2" bitfld.long 0x0 7. "TI1S,TI1S" "0,1" bitfld.long 0x0 4.--6. "MMS,MMS" "0,1,2,3,4,5,6,7" line.long 0x4 "TIM12_SMCR,TIM12 slave mode control register" bitfld.long 0x4 21. "TS_4,TS_4" "0,1" bitfld.long 0x4 20. "TS_3,TS_3" "0,1" bitfld.long 0x4 16. "SMS_3,SMS_3" "0,1" bitfld.long 0x4 7. "MSM,MSM" "0,1" bitfld.long 0x4 4.--6. "TS,TS" "0,1,2,3,4,5,6,7" bitfld.long 0x4 0.--2. "SMS,SMS" "0,1,2,3,4,5,6,7" group.word 0xC++0x1 line.word 0x0 "TIM12_DIER,TIM12 interrupt enable register" bitfld.word 0x0 6. "TIE,TIE" "0,1" bitfld.word 0x0 2. "CC2IE,CC2IE" "0,1" bitfld.word 0x0 1. "CC1IE,CC1IE" "0,1" bitfld.word 0x0 0. "UIE,UIE" "0,1" group.long 0x10++0x3 line.long 0x0 "TIM12_SR,TIM12 status register" bitfld.long 0x0 10. "CC2OF,CC2OF" "0,1" bitfld.long 0x0 9. "CC1OF,CC1OF" "0,1" bitfld.long 0x0 6. "TIF,TIF" "0,1" bitfld.long 0x0 2. "CC2IF,CC2IF" "0,1" bitfld.long 0x0 1. "CC1IF,CC1IF" "0,1" bitfld.long 0x0 0. "UIF,UIF" "0,1" wgroup.word 0x14++0x1 line.word 0x0 "TIM12_EGR,TIM12 event generation register" bitfld.word 0x0 6. "TG,TG" "0,1" bitfld.word 0x0 2. "CC2G,CC2G" "0,1" bitfld.word 0x0 1. "CC1G,CC1G" "0,1" bitfld.word 0x0 0. "UG,UG" "0,1" group.long 0x18++0x3 line.long 0x0 "TIM12_CCMR1_input,TIM12 capture/compare mode register 1" hexmask.long.byte 0x0 12.--15. 1. "IC2F,IC2F" bitfld.long 0x0 10.--11. "IC2PSC,IC2PSC" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,CC2S" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,IC1F" bitfld.long 0x0 2.--3. "IC1PSC,IC1PSC" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,CC1S" "0,1,2,3" group.long 0x18++0x3 line.long 0x0 "TIM12_CCMR1_output,TIM12 capture/compare mode register 1" bitfld.long 0x0 24. "OC2M_3,OC2M_3" "0,1" bitfld.long 0x0 16. "OC1M_3,OC1M_3" "0,1" bitfld.long 0x0 12.--14. "OC2M,OC2M" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,OC2PE" "0,1" bitfld.long 0x0 10. "OC2FE,OC2FE" "0,1" bitfld.long 0x0 8.--9. "CC2S,CC2S" "0,1,2,3" bitfld.long 0x0 4.--6. "OC1M,OC1M" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "OC1PE,OC1FE" "0,1" bitfld.long 0x0 2. "OC1FE,OC1FE" "0,1" newline bitfld.long 0x0 0.--1. "CC1S,CC1S" "0,1,2,3" group.long 0x20++0x7 line.long 0x0 "TIM12_CCER,TIM12 capture/compare enable register" bitfld.long 0x0 7. "CC2NP,CC2NP" "0,1" bitfld.long 0x0 5. "CC2P,CC2P" "0,1" bitfld.long 0x0 4. "CC2E,CC2E" "0,1" bitfld.long 0x0 3. "CC1NP,CC1NP" "0,1" bitfld.long 0x0 1. "CC1P,CC1P" "0,1" bitfld.long 0x0 0. "CC1E,CC1E" "0,1" line.long 0x4 "TIM12_CNT,TIM12 counter" rbitfld.long 0x4 31. "UIFCPY,UIFCPY" "0,1" hexmask.long.word 0x4 0.--15. 1. "CNT,CNT" group.word 0x28++0x1 line.word 0x0 "TIM12_PSC,TIM12 prescaler" hexmask.word 0x0 0.--15. 1. "PSC,PSC" group.word 0x2C++0x1 line.word 0x0 "TIM12_ARR,TIM12 auto-reload register" hexmask.word 0x0 0.--15. 1. "ARR,ARR" group.word 0x34++0x1 line.word 0x0 "TIM12_CCR1,TIM12 capture/compare register 1" hexmask.word 0x0 0.--15. 1. "CCR1,CCR1" group.word 0x38++0x1 line.word 0x0 "TIM12_CCR2,TIM12 capture/compare register 2" hexmask.word 0x0 0.--15. 1. "CCR2,CCR2" group.long 0x68++0x3 line.long 0x0 "TIM12_TISEL,TIM12 timer input selection register" hexmask.long.byte 0x0 8.--11. 1. "TI2SEL,TI2SEL" hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,TI1SEL" tree.end endif sif (cpuis("STM32MP151*")||cpuis("STM32MP153*")||cpuis("STM32MP157*")) tree "TIM13" base ad:0x40007000 group.word 0x0++0x1 line.word 0x0 "TIM13_CR1,TIM13 control register 1" bitfld.word 0x0 11. "UIFREMAP,UIFREMAP" "0,1" bitfld.word 0x0 8.--9. "CKD,CKD" "0,1,2,3" bitfld.word 0x0 7. "ARPE,ARPE" "0,1" bitfld.word 0x0 3. "OPM,OPM" "0,1" bitfld.word 0x0 2. "URS,URS" "0,1" bitfld.word 0x0 1. "UDIS,UDIS" "0,1" bitfld.word 0x0 0. "CEN,CEN" "0,1" group.word 0xC++0x1 line.word 0x0 "TIM13_DIER,TIM13 Interrupt enable register" bitfld.word 0x0 1. "CC1IE,CC1IE" "0,1" bitfld.word 0x0 0. "UIE,UIE" "0,1" group.word 0x10++0x1 line.word 0x0 "TIM13_SR,TIM13 status register" bitfld.word 0x0 9. "CC1OF,CC1OF" "0,1" bitfld.word 0x0 1. "CC1IF,CC1IF" "0,1" bitfld.word 0x0 0. "UIF,UIF" "0,1" wgroup.word 0x14++0x1 line.word 0x0 "TIM13_EGR,TIM13 event generation register" bitfld.word 0x0 1. "CC1G,CC1G" "0,1" bitfld.word 0x0 0. "UG,UG" "0,1" group.long 0x18++0x3 line.long 0x0 "TIM13_CCMR1,The channels can be used in input (capture mode) or in output (compare mode). The direction of a channel is defined by configuring the corresponding CCxS bits. All the other bits of this register have a different function in input and in.." bitfld.long 0x0 16. "OC1M3,OC1M3" "0,1" bitfld.long 0x0 4.--6. "OC1M,OC1M" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "OC1PE,OC1PE" "0,1" bitfld.long 0x0 2. "OC1FE,OC1FE" "0,1" bitfld.long 0x0 0.--1. "CC1S,CC1S" "0,1,2,3" group.word 0x20++0x1 line.word 0x0 "TIM13_CCER,TIM13 capture/compare enable register" bitfld.word 0x0 3. "CC1NP,CC1NP" "0,1" bitfld.word 0x0 1. "CC1P,CC1P" "0,1" bitfld.word 0x0 0. "CC1E,CC1E" "0,1" group.long 0x24++0x3 line.long 0x0 "TIM13_CNT,TIM13 counter" bitfld.long 0x0 31. "UIFCPY,UIFCPY" "0,1" hexmask.long.word 0x0 0.--15. 1. "CNT,CNT" group.word 0x28++0x1 line.word 0x0 "TIM13_PSC,TIM13 prescaler" hexmask.word 0x0 0.--15. 1. "PSC,PSC" group.word 0x2C++0x1 line.word 0x0 "TIM13_ARR,TIM13 auto-reload register" hexmask.word 0x0 0.--15. 1. "ARR,ARR" group.word 0x34++0x1 line.word 0x0 "TIM13_CCR1,TIM13 capture/compare register 1" hexmask.word 0x0 0.--15. 1. "CCR1,CCR1" group.word 0x68++0x1 line.word 0x0 "TIM13_TISEL,TIM13 timer input selection register" hexmask.word.byte 0x0 0.--3. 1. "TI1SEL,TI1SEL" tree.end endif sif (cpuis("STM32MP151*")||cpuis("STM32MP153*")||cpuis("STM32MP157*")) tree "TIM14" base ad:0x40008000 group.word 0x0++0x1 line.word 0x0 "TIM14_CR1,TIM14 control register 1" bitfld.word 0x0 11. "UIFREMAP,UIFREMAP" "0,1" bitfld.word 0x0 8.--9. "CKD,CKD" "0,1,2,3" bitfld.word 0x0 7. "ARPE,ARPE" "0,1" bitfld.word 0x0 3. "OPM,OPM" "0,1" bitfld.word 0x0 2. "URS,URS" "0,1" bitfld.word 0x0 1. "UDIS,UDIS" "0,1" bitfld.word 0x0 0. "CEN,CEN" "0,1" group.word 0xC++0x1 line.word 0x0 "TIM14_DIER,TIM14 Interrupt enable register" bitfld.word 0x0 1. "CC1IE,CC1IE" "0,1" bitfld.word 0x0 0. "UIE,UIE" "0,1" group.word 0x10++0x1 line.word 0x0 "TIM14_SR,TIM14 status register" bitfld.word 0x0 9. "CC1OF,CC1OF" "0,1" bitfld.word 0x0 1. "CC1IF,CC1IF" "0,1" bitfld.word 0x0 0. "UIF,UIF" "0,1" wgroup.word 0x14++0x1 line.word 0x0 "TIM14_EGR,TIM14 event generation register" bitfld.word 0x0 1. "CC1G,CC1G" "0,1" bitfld.word 0x0 0. "UG,UG" "0,1" group.long 0x18++0x3 line.long 0x0 "TIM14_CCMR1,The channels can be used in input (capture mode) or in output (compare mode). The direction of a channel is defined by configuring the corresponding CCxS bits. All the other bits of this register have a different function in input and in.." bitfld.long 0x0 16. "OC1M3,OC1M3" "0,1" bitfld.long 0x0 4.--6. "OC1M,OC1M" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "OC1PE,OC1PE" "0,1" bitfld.long 0x0 2. "OC1FE,OC1FE" "0,1" bitfld.long 0x0 0.--1. "CC1S,CC1S" "0,1,2,3" group.word 0x20++0x1 line.word 0x0 "TIM14_CCER,TIM14 capture/compare enable register" bitfld.word 0x0 3. "CC1NP,CC1NP" "0,1" bitfld.word 0x0 1. "CC1P,CC1P" "0,1" bitfld.word 0x0 0. "CC1E,CC1E" "0,1" group.long 0x24++0x3 line.long 0x0 "TIM14_CNT,TIM14 counter" bitfld.long 0x0 31. "UIFCPY,UIFCPY" "0,1" hexmask.long.word 0x0 0.--15. 1. "CNT,CNT" group.word 0x28++0x1 line.word 0x0 "TIM14_PSC,TIM14 prescaler" hexmask.word 0x0 0.--15. 1. "PSC,PSC" group.word 0x2C++0x1 line.word 0x0 "TIM14_ARR,TIM14 auto-reload register" hexmask.word 0x0 0.--15. 1. "ARR,ARR" group.word 0x34++0x1 line.word 0x0 "TIM14_CCR1,TIM14 capture/compare register 1" hexmask.word 0x0 0.--15. 1. "CCR1,CCR1" group.word 0x68++0x1 line.word 0x0 "TIM14_TISEL,TIM14 timer input selection register" hexmask.word.byte 0x0 0.--3. 1. "TI1SEL,TI1SEL" tree.end endif sif (cpuis("STM32MP151*")||cpuis("STM32MP153*")||cpuis("STM32MP157*")) tree "TIM15" base ad:0x44006000 group.word 0x0++0x1 line.word 0x0 "TIM15_CR1,TIM15 control register 1" bitfld.word 0x0 11. "UIFREMAP,UIFREMAP" "0,1" bitfld.word 0x0 8.--9. "CKD,CKD" "0,1,2,3" bitfld.word 0x0 7. "ARPE,ARPE" "0,1" bitfld.word 0x0 3. "OPM,OPM" "0,1" bitfld.word 0x0 2. "URS,URS" "0,1" bitfld.word 0x0 1. "UDIS,UDIS" "0,1" bitfld.word 0x0 0. "CEN,CEN" "0,1" group.word 0x4++0x1 line.word 0x0 "TIM15_CR2,TIM15 control register 2" bitfld.word 0x0 10. "OIS2,OIS2" "0,1" bitfld.word 0x0 9. "OIS1N,OIS1N" "0,1" bitfld.word 0x0 8. "OIS1,OIS1" "0,1" bitfld.word 0x0 7. "TI1S,TI1S" "0,1" bitfld.word 0x0 4.--6. "MMS,MMS" "0,1,2,3,4,5,6,7" bitfld.word 0x0 3. "CCDS,CCDS" "0,1" bitfld.word 0x0 2. "CCUS,CCUS" "0,1" bitfld.word 0x0 0. "CCPC,CCPC" "0,1" group.long 0x8++0x3 line.long 0x0 "TIMx_SMCR,slave mode control register" bitfld.long 0x0 20.--21. "TS_4_3,Trigger selection" "0,1,2,3" bitfld.long 0x0 16. "SMS_3,Slave mode selection - bit" "0,1" bitfld.long 0x0 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x0 4.--6. "TS,Trigger selection" "0,1,2,3,4,5,6,7" bitfld.long 0x0 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" group.word 0xC++0x1 line.word 0x0 "TIM15_DIER,TIM15 DMA/interrupt enable" bitfld.word 0x0 14. "TDE,TDE" "0,1" bitfld.word 0x0 13. "COMDE,COMDE" "0,1" bitfld.word 0x0 10. "CC2DE,CC2DE" "0,1" bitfld.word 0x0 9. "CC1DE,CC1DE" "0,1" bitfld.word 0x0 8. "UDE,UDE" "0,1" bitfld.word 0x0 7. "BIE,BIE" "0,1" bitfld.word 0x0 6. "TIE,TIE" "0,1" bitfld.word 0x0 5. "COMIE,COMIE" "0,1" bitfld.word 0x0 2. "CC2IE,CC2IE" "0,1" newline bitfld.word 0x0 1. "CC1IE,CC1IE" "0,1" bitfld.word 0x0 0. "UIE,UIE" "0,1" group.word 0x10++0x1 line.word 0x0 "TIM15_SR,TIM15 status register" bitfld.word 0x0 10. "CC2OF,CC2OF" "0,1" bitfld.word 0x0 9. "CC1OF,CC1OF" "0,1" bitfld.word 0x0 7. "BIF,BIF" "0,1" bitfld.word 0x0 6. "TIF,TIF" "0,1" bitfld.word 0x0 5. "COMIF,COMIF" "0,1" bitfld.word 0x0 2. "CC2IF,CC2IF" "0,1" bitfld.word 0x0 1. "CC1IF,CC1IF" "0,1" bitfld.word 0x0 0. "UIF,UIF" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "TIMx_EGR,event generation register" bitfld.long 0x0 7. "BG,BG" "0,1" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 5. "COMG,COMG" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "TIMx_CCMR1_Output,capture/compare mode register 1 (output" bitfld.long 0x0 24. "OC2M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,Output compare 2 clear" "0,1" bitfld.long 0x0 12.--14. "OC2M,Output compare 2 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,Output compare 2 preload" "0,1" bitfld.long 0x0 10. "OC2FE,Output compare 2 fast" "0,1" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" bitfld.long 0x0 7. "OC1CE,Output compare 1 clear" "0,1" bitfld.long 0x0 4.--6. "OC1M,Output compare 1 mode" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3. "OC1PE,Output compare 1 preload" "0,1" bitfld.long 0x0 2. "OC1FE,Output compare 1 fast" "0,1" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x18++0x3 line.long 0x0 "TIMx_CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PSC,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.word 0x20++0x1 line.word 0x0 "TIM15_CCER,TIM15 capture/compare enable" bitfld.word 0x0 7. "CC2NP,CC2NP" "0,1" bitfld.word 0x0 5. "CC2P,CC2P" "0,1" bitfld.word 0x0 4. "CC2E,CC2E" "0,1" bitfld.word 0x0 3. "CC1NP,CC1NP" "0,1" bitfld.word 0x0 2. "CC1NE,CC1NE" "0,1" bitfld.word 0x0 1. "CC1P,CC1P" "0,1" bitfld.word 0x0 0. "CC1E,CC1E" "0,1" group.long 0x24++0x3 line.long 0x0 "TIM15_CNT,TIM15 counter" rbitfld.long 0x0 31. "UIFCPY,UIFCPY" "0,1" hexmask.long.word 0x0 0.--15. 1. "CNT,CNT" group.word 0x28++0x1 line.word 0x0 "TIM15_PSC,TIM15 prescaler" hexmask.word 0x0 0.--15. 1. "PSC,PSC" group.word 0x2C++0x1 line.word 0x0 "TIM15_ARR,TIM15 auto-reload register" hexmask.word 0x0 0.--15. 1. "ARR,ARR" group.word 0x30++0x1 line.word 0x0 "TIM15_RCR,TIM15 repetition counter" hexmask.word.byte 0x0 0.--7. 1. "REP,REP" group.word 0x34++0x1 line.word 0x0 "TIM15_CCR1,TIM15 capture/compare register" hexmask.word 0x0 0.--15. 1. "CCR1,CCR1" group.word 0x38++0x1 line.word 0x0 "TIM15_CCR2,TIM15 capture/compare register" hexmask.word 0x0 0.--15. 1. "CCR2,CCR2" group.long 0x44++0x3 line.long 0x0 "TIMx_BDTR,As the bits BK2BID. BKBID. BK2DSRM. BKDSRM." bitfld.long 0x0 28. "BKBID,BKBID" "0,1" bitfld.long 0x0 26. "BKDSRM,BKDSRM" "0,1" hexmask.long.byte 0x0 16.--19. 1. "BKF,BKF" bitfld.long 0x0 15. "MOE,MOE" "0,1" bitfld.long 0x0 14. "AOE,AOE" "0,1" bitfld.long 0x0 13. "BKP,BKP" "0,1" bitfld.long 0x0 12. "BKE,BKE" "0,1" bitfld.long 0x0 11. "OSSR,OSSR" "0,1" bitfld.long 0x0 10. "OSSI,OSSI" "0,1" newline bitfld.long 0x0 8.--9. "LOCK,LOCK" "0,1,2,3" hexmask.long.byte 0x0 0.--7. 1. "DTG,DTG" group.word 0x48++0x1 line.word 0x0 "TIM15_DCR,TIM15 DMA control register" hexmask.word.byte 0x0 8.--12. 1. "DBL,DBL" hexmask.word.byte 0x0 0.--4. 1. "DBA,DBA" group.word 0x4C++0x1 line.word 0x0 "TIM15_DMAR,TIM15 DMA address for full" hexmask.word 0x0 0.--15. 1. "DMAB,DMAB" group.long 0x60++0x3 line.long 0x0 "TIM15_AF1,TIM15 alternate register 1" bitfld.long 0x0 9. "BKINP,BKINP" "0,1" bitfld.long 0x0 8. "BKDF1BK0E,BKDF1BK0E" "0,1" bitfld.long 0x0 0. "BKINE,BKINE" "0,1" group.long 0x68++0x3 line.long 0x0 "TIM15_TISEL,TIM15 input selection register" hexmask.long.byte 0x0 8.--11. 1. "TI2SEL,TI2SEL" hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,TI1SEL" tree.end endif sif (cpuis("STM32MP151*")||cpuis("STM32MP153*")||cpuis("STM32MP157*")) tree "TIM16" base ad:0x44007000 group.word 0x0++0x1 line.word 0x0 "TIMx_CR1,TIM16/TIM17 control register 1" bitfld.word 0x0 11. "UIFREMAP,UIFREMAP" "0,1" bitfld.word 0x0 8.--9. "CKD,CKD" "0,1,2,3" bitfld.word 0x0 7. "ARPE,ARPE" "0,1" bitfld.word 0x0 3. "OPM,OPM" "0,1" bitfld.word 0x0 2. "URS,URS" "0,1" bitfld.word 0x0 1. "UDIS,UDIS" "0,1" bitfld.word 0x0 0. "CEN,CEN" "0,1" group.word 0x4++0x1 line.word 0x0 "TIMx_CR2,TIM16/TIM17 control register 2" bitfld.word 0x0 9. "OIS1N,OIS1N" "0,1" bitfld.word 0x0 8. "OIS1,OIS1" "0,1" bitfld.word 0x0 3. "CCDS,CCDS" "0,1" bitfld.word 0x0 2. "CCUS,CCUS" "0,1" bitfld.word 0x0 0. "CCPC,CCPC" "0,1" group.word 0xC++0x1 line.word 0x0 "TIMx_DIER,TIM16/TIM17 DMA/interrupt enable" bitfld.word 0x0 13. "COMDE,COMDE" "0,1" bitfld.word 0x0 9. "CC1DE,CC1DE" "0,1" bitfld.word 0x0 8. "UDE,UDE" "0,1" bitfld.word 0x0 7. "BIE,BIE" "0,1" bitfld.word 0x0 5. "COMIE,COMIE" "0,1" bitfld.word 0x0 1. "CC1IE,CC1IE" "0,1" bitfld.word 0x0 0. "UIE,UIE" "0,1" group.word 0x10++0x1 line.word 0x0 "TIMx_SR,TIM16/TIM17 status register" bitfld.word 0x0 9. "CC1OF,CC1OF" "0,1" bitfld.word 0x0 7. "BIF,BIF" "0,1" bitfld.word 0x0 5. "COMIF,COMIF" "0,1" bitfld.word 0x0 1. "CC1IF,CC1IF" "0,1" bitfld.word 0x0 0. "UIF,UIF" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "TIMx_EGR,event generation register" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.word 0x20++0x1 line.word 0x0 "TIMx_CCER,TIM16/TIM17 capture/compare enable" bitfld.word 0x0 3. "CC1NP,CC1NP" "0,1" bitfld.word 0x0 2. "CC1NE,CC1NE" "0,1" bitfld.word 0x0 1. "CC1P,CC1P" "0,1" bitfld.word 0x0 0. "CC1E,CC1E" "0,1" group.long 0x24++0x3 line.long 0x0 "TIMx_CNT,TIM16/TIM17 counter" rbitfld.long 0x0 31. "UIFCPY,UIFCPY" "0,1" hexmask.long.word 0x0 0.--15. 1. "CNT,CNT" group.word 0x28++0x1 line.word 0x0 "TIMx_PSC,TIM16/TIM17 prescaler" hexmask.word 0x0 0.--15. 1. "PSC,PSC" group.word 0x2C++0x1 line.word 0x0 "TIMx_ARR,TIM16/TIM17 auto-reload" hexmask.word 0x0 0.--15. 1. "ARR,ARR" group.word 0x30++0x1 line.word 0x0 "TIMx_RCR,TIM16/TIM17 repetition counter" hexmask.word.byte 0x0 0.--7. 1. "REP,REP" group.word 0x34++0x1 line.word 0x0 "TIMx_CCR1,TIM16/TIM17 capture/compare register" hexmask.word 0x0 0.--15. 1. "CCR1,CCR1" group.long 0x44++0x3 line.long 0x0 "TIMx_BDTR,As the BKBID. BKDSRM. BKF[3:0]. AOE. BKP." bitfld.long 0x0 28. "BKBID,BKBID" "0,1" bitfld.long 0x0 26. "BKDSRM,BKDSRM" "0,1" hexmask.long.byte 0x0 16.--19. 1. "BKF,BKF" bitfld.long 0x0 15. "MOE,MOE" "0,1" bitfld.long 0x0 14. "AOE,AOE" "0,1" bitfld.long 0x0 13. "BKP,BKP" "0,1" bitfld.long 0x0 12. "BKE,BKE" "0,1" bitfld.long 0x0 11. "OSSR,OSSR" "0,1" bitfld.long 0x0 10. "OSSI,OSSI" "0,1" newline bitfld.long 0x0 8.--9. "LOCK,LOCK" "0,1,2,3" hexmask.long.byte 0x0 0.--7. 1. "DTG,DTG" group.word 0x48++0x1 line.word 0x0 "TIMx_DCR,TIM16/TIM17 DMA control" hexmask.word.byte 0x0 8.--12. 1. "DBL,DBL" hexmask.word.byte 0x0 0.--4. 1. "DBA,DBA" group.word 0x4C++0x1 line.word 0x0 "TIMx_DMAR,TIM16/TIM17 DMA address for full" hexmask.word 0x0 0.--15. 1. "DMAB,DMAB" group.long 0x60++0x3 line.long 0x0 "TIMx_AF1,TIM17 alternate function register" bitfld.long 0x0 9. "BKINP,BKINP" "0,1" bitfld.long 0x0 8. "BKDF1BK2E,BKDF1BK2E" "0,1" bitfld.long 0x0 0. "BKINE,BKINE" "0,1" group.long 0x68++0x3 line.long 0x0 "TIMx_TISEL,TIM17 input selection register" hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,TI1SEL" tree.end endif sif (cpuis("STM32MP151*")||cpuis("STM32MP153*")||cpuis("STM32MP157*")) tree "TIM17" base ad:0x44008000 group.word 0x0++0x1 line.word 0x0 "TIMx_CR1,TIM16/TIM17 control register 1" bitfld.word 0x0 11. "UIFREMAP,UIFREMAP" "0,1" bitfld.word 0x0 8.--9. "CKD,CKD" "0,1,2,3" bitfld.word 0x0 7. "ARPE,ARPE" "0,1" bitfld.word 0x0 3. "OPM,OPM" "0,1" bitfld.word 0x0 2. "URS,URS" "0,1" bitfld.word 0x0 1. "UDIS,UDIS" "0,1" bitfld.word 0x0 0. "CEN,CEN" "0,1" group.word 0x4++0x1 line.word 0x0 "TIMx_CR2,TIM16/TIM17 control register 2" bitfld.word 0x0 9. "OIS1N,OIS1N" "0,1" bitfld.word 0x0 8. "OIS1,OIS1" "0,1" bitfld.word 0x0 3. "CCDS,CCDS" "0,1" bitfld.word 0x0 2. "CCUS,CCUS" "0,1" bitfld.word 0x0 0. "CCPC,CCPC" "0,1" group.word 0xC++0x1 line.word 0x0 "TIMx_DIER,TIM16/TIM17 DMA/interrupt enable" bitfld.word 0x0 13. "COMDE,COMDE" "0,1" bitfld.word 0x0 9. "CC1DE,CC1DE" "0,1" bitfld.word 0x0 8. "UDE,UDE" "0,1" bitfld.word 0x0 7. "BIE,BIE" "0,1" bitfld.word 0x0 5. "COMIE,COMIE" "0,1" bitfld.word 0x0 1. "CC1IE,CC1IE" "0,1" bitfld.word 0x0 0. "UIE,UIE" "0,1" group.word 0x10++0x1 line.word 0x0 "TIMx_SR,TIM16/TIM17 status register" bitfld.word 0x0 9. "CC1OF,CC1OF" "0,1" bitfld.word 0x0 7. "BIF,BIF" "0,1" bitfld.word 0x0 5. "COMIF,COMIF" "0,1" bitfld.word 0x0 1. "CC1IF,CC1IF" "0,1" bitfld.word 0x0 0. "UIF,UIF" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "TIMx_EGR,event generation register" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.word 0x20++0x1 line.word 0x0 "TIMx_CCER,TIM16/TIM17 capture/compare enable" bitfld.word 0x0 3. "CC1NP,CC1NP" "0,1" bitfld.word 0x0 2. "CC1NE,CC1NE" "0,1" bitfld.word 0x0 1. "CC1P,CC1P" "0,1" bitfld.word 0x0 0. "CC1E,CC1E" "0,1" group.long 0x24++0x3 line.long 0x0 "TIMx_CNT,TIM16/TIM17 counter" rbitfld.long 0x0 31. "UIFCPY,UIFCPY" "0,1" hexmask.long.word 0x0 0.--15. 1. "CNT,CNT" group.word 0x28++0x1 line.word 0x0 "TIMx_PSC,TIM16/TIM17 prescaler" hexmask.word 0x0 0.--15. 1. "PSC,PSC" group.word 0x2C++0x1 line.word 0x0 "TIMx_ARR,TIM16/TIM17 auto-reload" hexmask.word 0x0 0.--15. 1. "ARR,ARR" group.word 0x30++0x1 line.word 0x0 "TIMx_RCR,TIM16/TIM17 repetition counter" hexmask.word.byte 0x0 0.--7. 1. "REP,REP" group.word 0x34++0x1 line.word 0x0 "TIMx_CCR1,TIM16/TIM17 capture/compare register" hexmask.word 0x0 0.--15. 1. "CCR1,CCR1" group.long 0x44++0x3 line.long 0x0 "TIMx_BDTR,As the BKBID. BKDSRM. BKF[3:0]. AOE. BKP." bitfld.long 0x0 28. "BKBID,BKBID" "0,1" bitfld.long 0x0 26. "BKDSRM,BKDSRM" "0,1" hexmask.long.byte 0x0 16.--19. 1. "BKF,BKF" bitfld.long 0x0 15. "MOE,MOE" "0,1" bitfld.long 0x0 14. "AOE,AOE" "0,1" bitfld.long 0x0 13. "BKP,BKP" "0,1" bitfld.long 0x0 12. "BKE,BKE" "0,1" bitfld.long 0x0 11. "OSSR,OSSR" "0,1" bitfld.long 0x0 10. "OSSI,OSSI" "0,1" newline bitfld.long 0x0 8.--9. "LOCK,LOCK" "0,1,2,3" hexmask.long.byte 0x0 0.--7. 1. "DTG,DTG" group.word 0x48++0x1 line.word 0x0 "TIMx_DCR,TIM16/TIM17 DMA control" hexmask.word.byte 0x0 8.--12. 1. "DBL,DBL" hexmask.word.byte 0x0 0.--4. 1. "DBA,DBA" group.word 0x4C++0x1 line.word 0x0 "TIMx_DMAR,TIM16/TIM17 DMA address for full" hexmask.word 0x0 0.--15. 1. "DMAB,DMAB" group.long 0x60++0x3 line.long 0x0 "TIMx_AF1,TIM17 alternate function register" bitfld.long 0x0 9. "BKINP,BKINP" "0,1" bitfld.long 0x0 8. "BKDF1BK2E,BKDF1BK2E" "0,1" bitfld.long 0x0 0. "BKINE,BKINE" "0,1" group.long 0x68++0x3 line.long 0x0 "TIMx_TISEL,TIM17 input selection register" hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,TI1SEL" tree.end endif tree.end sif (cpuis("STM32MP13*")) tree "TSC (Transaction Service Control)" base ad:0x5000B000 group.long 0x0++0xB line.long 0x0 "TSC_CR," hexmask.long.byte 0x0 28.--31. 1. "CTPH,Charge transfer pulse high" hexmask.long.byte 0x0 24.--27. 1. "CTPL,Charge transfer pulse low" newline hexmask.long.byte 0x0 17.--23. 1. "SSD,Spread spectrum deviation" bitfld.long 0x0 16. "SSE,Spread spectrum enable" "0: Spread spectrum disabled,1: Spread spectrum enabled" newline bitfld.long 0x0 15. "SSPSC,Spread spectrum prescaler" "0: fHCLK,1: fHCLK /2" bitfld.long 0x0 12.--14. "PGPSC,Pulse generator prescaler" "0: fHCLK,1: fHCLK /2,2: fHCLK /4,3: fHCLK /8,4: fHCLK /16,5: fHCLK /32,6: fHCLK /64,7: fHCLK /128" newline bitfld.long 0x0 5.--7. "MCV,Max count value" "0: 255,1: 511,2: 1023,3: 2047,4: 4095,5: 8191,6: 16383,?" bitfld.long 0x0 4. "IODEF,I/O Default mode" "0: I/Os are forced to output push-pull low,1: I/Os are in input floating" newline bitfld.long 0x0 3. "SYNCPOL,Synchronization pin polarity" "0: Falling edge only,1: Rising edge and high level" bitfld.long 0x0 2. "AM,Acquisition mode" "0: Normal acquisition mode (acquisition starts as..,1: Synchronized acquisition mode (acquisition.." newline bitfld.long 0x0 1. "START,Start a new acquisition" "0: Acquisition not started,1: Start a new acquisition" bitfld.long 0x0 0. "TSCE,Touch sensing controller enable" "0: Touch sensing controller disabled,1: Touch sensing controller enabled" line.long 0x4 "TSC_IER," bitfld.long 0x4 1. "MCEIE,Max count error interrupt enable" "0: Max count error interrupt disabled,1: Max count error interrupt enabled" bitfld.long 0x4 0. "EOAIE,End of acquisition interrupt enable" "0: End of acquisition interrupt disabled,1: End of acquisition interrupt enabled" line.long 0x8 "TSC_ICR," bitfld.long 0x8 1. "MCEIC,Max count error interrupt clear" "0: No effect,1: Clears the corresponding MCEF of the TSC_ISR.." bitfld.long 0x8 0. "EOAIC,End of acquisition interrupt clear" "0: No effect,1: Clears the corresponding EOAF of the TSC_ISR.." rgroup.long 0xC++0x3 line.long 0x0 "TSC_ISR," bitfld.long 0x0 1. "MCEF,Max count error flag" "0: No max count error (MCE) detected,1: Max count error (MCE) detected" bitfld.long 0x0 0. "EOAF,End of acquisition flag" "0: Acquisition is ongoing or not started,1: Acquisition is complete" group.long 0x10++0x3 line.long 0x0 "TSC_IOHCR," bitfld.long 0x0 19. "G5_IO4," "0,1" bitfld.long 0x0 18. "G5_IO3," "0,1" newline bitfld.long 0x0 17. "G5_IO2," "0,1" bitfld.long 0x0 16. "G5_IO1," "0,1" newline bitfld.long 0x0 15. "G4_IO4," "0,1" bitfld.long 0x0 14. "G4_IO3," "0,1" newline bitfld.long 0x0 13. "G4_IO2," "0,1" bitfld.long 0x0 12. "G4_IO1," "0,1" newline bitfld.long 0x0 11. "G3_IO4," "0,1" bitfld.long 0x0 10. "G3_IO3," "0,1" newline bitfld.long 0x0 9. "G3_IO2," "0,1" bitfld.long 0x0 8. "G3_IO1," "0,1" newline bitfld.long 0x0 7. "G2_IO4," "0,1" bitfld.long 0x0 6. "G2_IO3," "0,1" newline bitfld.long 0x0 5. "G2_IO2," "0,1" bitfld.long 0x0 4. "G2_IO1," "0,1" newline bitfld.long 0x0 3. "G1_IO4," "0,1" bitfld.long 0x0 2. "G1_IO3," "0,1" newline bitfld.long 0x0 1. "G1_IO2," "0,1" bitfld.long 0x0 0. "G1_IO1," "0,1" group.long 0x18++0x3 line.long 0x0 "TSC_IOASCR," bitfld.long 0x0 19. "G5_IO4," "0,1" bitfld.long 0x0 18. "G5_IO3," "0,1" newline bitfld.long 0x0 17. "G5_IO2," "0,1" bitfld.long 0x0 16. "G5_IO1," "0,1" newline bitfld.long 0x0 15. "G4_IO4," "0,1" bitfld.long 0x0 14. "G4_IO3," "0,1" newline bitfld.long 0x0 13. "G4_IO2," "0,1" bitfld.long 0x0 12. "G4_IO1," "0,1" newline bitfld.long 0x0 11. "G3_IO4," "0,1" bitfld.long 0x0 10. "G3_IO3," "0,1" newline bitfld.long 0x0 9. "G3_IO2," "0,1" bitfld.long 0x0 8. "G3_IO1," "0,1" newline bitfld.long 0x0 7. "G2_IO4," "0,1" bitfld.long 0x0 6. "G2_IO3," "0,1" newline bitfld.long 0x0 5. "G2_IO2," "0,1" bitfld.long 0x0 4. "G2_IO1," "0,1" newline bitfld.long 0x0 3. "G1_IO4," "0,1" bitfld.long 0x0 2. "G1_IO3," "0,1" newline bitfld.long 0x0 1. "G1_IO2," "0,1" bitfld.long 0x0 0. "G1_IO1," "0,1" group.long 0x28++0x3 line.long 0x0 "TSC_IOCCR," bitfld.long 0x0 19. "G5_IO4," "0,1" bitfld.long 0x0 18. "G5_IO3," "0,1" newline bitfld.long 0x0 17. "G5_IO2," "0,1" bitfld.long 0x0 16. "G5_IO1," "0,1" newline bitfld.long 0x0 15. "G4_IO4," "0,1" bitfld.long 0x0 14. "G4_IO3," "0,1" newline bitfld.long 0x0 13. "G4_IO2," "0,1" bitfld.long 0x0 12. "G4_IO1," "0,1" newline bitfld.long 0x0 11. "G3_IO4," "0,1" bitfld.long 0x0 10. "G3_IO3," "0,1" newline bitfld.long 0x0 9. "G3_IO2," "0,1" bitfld.long 0x0 8. "G3_IO1," "0,1" newline bitfld.long 0x0 7. "G2_IO4," "0,1" bitfld.long 0x0 6. "G2_IO3," "0,1" newline bitfld.long 0x0 5. "G2_IO2," "0,1" bitfld.long 0x0 4. "G2_IO1," "0,1" newline bitfld.long 0x0 3. "G1_IO4," "0,1" bitfld.long 0x0 2. "G1_IO3," "0,1" newline bitfld.long 0x0 1. "G1_IO2," "0,1" bitfld.long 0x0 0. "G1_IO1," "0,1" group.long 0x30++0x3 line.long 0x0 "TSC_IOGCSR," rbitfld.long 0x0 20. "G5S," "0,1" rbitfld.long 0x0 19. "G4S," "0,1" newline rbitfld.long 0x0 18. "G3S," "0,1" rbitfld.long 0x0 17. "G2S," "0,1" newline rbitfld.long 0x0 16. "G1S," "0,1" bitfld.long 0x0 4. "G5E," "0,1" newline bitfld.long 0x0 3. "G4E," "0,1" bitfld.long 0x0 2. "G3E," "0,1" newline bitfld.long 0x0 1. "G2E," "0,1" bitfld.long 0x0 0. "G1E," "0,1" rgroup.long 0x34++0xF line.long 0x0 "TSC_IOG1CR," hexmask.long.word 0x0 0.--13. 1. "CNT,Counter value" line.long 0x4 "TSC_IOG2CR," hexmask.long.word 0x4 0.--13. 1. "CNT,Counter value" line.long 0x8 "TSC_IOG3CR," hexmask.long.word 0x8 0.--13. 1. "CNT,Counter value" line.long 0xC "TSC_IOG4CR," hexmask.long.word 0xC 0.--13. 1. "CNT,Counter value" rgroup.long 0x3F0++0xF line.long 0x0 "TSC_HWCFGR," hexmask.long.byte 0x0 4.--7. 1. "CFG2,TSC hardware configuration 2" hexmask.long.byte 0x0 0.--3. 1. "CFG1,TSC hardware configuration 1" line.long 0x4 "TSC_VERR," hexmask.long.byte 0x4 4.--7. 1. "MAJREV,Major revision" hexmask.long.byte 0x4 0.--3. 1. "MINREV,Minor revision" line.long 0x8 "TSC_IDR," hexmask.long 0x8 0.--31. 1. "ID,TSC identifier" line.long 0xC "TSC_SIDR," hexmask.long 0xC 0.--31. 1. "SID,TSC size identification" tree.end endif tree "TZC (TrustZone Address Space Controller)" base ad:0x5C006000 group.long 0x0++0x13 line.long 0x0 "TZC_BUILD_CONFIG,TZC configuration register" sif (cpuis("STM32MP13*")) rbitfld.long 0x0 24. "NO_OF_FILTERS,Number of filters" "0: 1 filter,?" hexmask.long.byte 0x0 8.--13. 1. "ADDRESS_WIDTH,Address width" newline hexmask.long.byte 0x0 0.--4. 1. "NO_OF_REGIONS,Number fo regions" endif sif (cpuis("STM32MP151*")) rbitfld.long 0x0 24.--25. "NO_OF_FILTERS,NO_OF_FILTERS" "0,1,2,3" newline endif sif (cpuis("STM32MP153*")) rbitfld.long 0x0 24.--25. "NO_OF_FILTERS,NO_OF_FILTERS" "0,1,2,3" endif sif (cpuis("STM32MP157*")) rbitfld.long 0x0 24.--25. "NO_OF_FILTERS,NO_OF_FILTERS" "0,1,2,3" newline endif sif (cpuis("STM32MP151*")) hexmask.long.byte 0x0 8.--13. 1. "ADDRESS_WIDTH,ADDRESS_WIDTH" endif sif (cpuis("STM32MP153*")) hexmask.long.byte 0x0 8.--13. 1. "ADDRESS_WIDTH,ADDRESS_WIDTH" newline endif sif (cpuis("STM32MP157*")) hexmask.long.byte 0x0 8.--13. 1. "ADDRESS_WIDTH,ADDRESS_WIDTH" endif sif (cpuis("STM32MP153*")) hexmask.long.byte 0x0 0.--4. 1. "NO_OF_REGIONS,NO_OF_REGIONS" newline endif sif (cpuis("STM32MP157*")) hexmask.long.byte 0x0 0.--4. 1. "NO_OF_REGIONS,NO_OF_REGIONS" endif line.long 0x4 "TZC_ACTION,TZC action register" sif (cpuis("STM32MP13*")) bitfld.long 0x4 0.--1. "REACTION_VALUE,Permission failure reaction" "0: set tzcint low and issue OKAY on the bus,1: set tzcint low and issue DECERR on the bus,2: set tzcint high and issue OKAY on the bus,3: set tzcint high and issue DECERR on the bus" endif sif (cpuis("STM32MP153*")) bitfld.long 0x4 0.--1. "REACTION_VALUE,REACTION_VALUE" "0,1,2,3" newline endif sif (cpuis("STM32MP157*")) bitfld.long 0x4 0.--1. "REACTION_VALUE,REACTION_VALUE" "0,1,2,3" endif line.long 0x8 "TZC_GATE_KEEPER,TZC gate keeper register" sif (cpuis("STM32MP13*")) rbitfld.long 0x8 16. "OPENSTAT,Gate keeper status for filter" "0: filter is opened,1: filter is closed" bitfld.long 0x8 0. "OPENREQ,Gate keeper open request for filter" "0: request filter to open,1: request filter to close" newline endif sif (cpuis("STM32MP151*")) rbitfld.long 0x8 16.--17. "OPENSTAT,OPENSTAT" "0,1,2,3" endif sif (cpuis("STM32MP153*")) rbitfld.long 0x8 16.--17. "OPENSTAT,OPENSTAT" "0,1,2,3" newline endif sif (cpuis("STM32MP157*")) rbitfld.long 0x8 16.--17. "OPENSTAT,OPENSTAT" "0,1,2,3" endif sif (cpuis("STM32MP151*")) bitfld.long 0x8 0.--1. "OPENREQ,OPENREQ" "0,1,2,3" newline endif sif (cpuis("STM32MP153*")) bitfld.long 0x8 0.--1. "OPENREQ,OPENREQ" "0,1,2,3" endif sif (cpuis("STM32MP157*")) bitfld.long 0x8 0.--1. "OPENREQ,OPENREQ" "0,1,2,3" endif line.long 0xC "TZC_SPECULATION_CTRL,TZC speculation control register" sif (cpuis("STM32MP13*")) bitfld.long 0xC 1. "WRITESPEC_DISABLE,Write access speculation disable" "0: write access speculation enabled,1: write access speculation disabled" bitfld.long 0xC 0. "READSPEC_DISABLE,Read access speculation disable" "0: read access speculation enabled,1: read access speculation disabled" newline endif sif (cpuis("STM32MP151*")) bitfld.long 0xC 1. "WRITESPEC_DISABLE,WRITESPEC_DISABLE" "0,1" endif sif (cpuis("STM32MP153*")) bitfld.long 0xC 1. "WRITESPEC_DISABLE,WRITESPEC_DISABLE" "0,1" newline bitfld.long 0xC 0. "READSPEC_DISABLE,READSPEC_DISABLE" "0,1" endif sif (cpuis("STM32MP157*")) bitfld.long 0xC 1. "WRITESPEC_DISABLE,WRITESPEC_DISABLE" "0,1" newline bitfld.long 0xC 0. "READSPEC_DISABLE,READSPEC_DISABLE" "0,1" endif line.long 0x10 "TZC_INT_STATUS,TZC interrupt status register" sif (cpuis("STM32MP13*")) rbitfld.long 0x10 16.--17. "OVERLAP,Overlap violation for each filter" "0: interrupt is not asserted,1: interrupt asserted and waiting to be cleared,?,?" rbitfld.long 0x10 8. "OVERRUN,Permission failure overrun" "0: interrupt is not asserted,1: interrupt asserted and waiting to be cleared" newline rbitfld.long 0x10 0. "STATUS,Interrupt status for the filter." "0: interrupt is not asserted,1: interrupt asserted and waiting to be cleared" endif sif (cpuis("STM32MP151*")) rbitfld.long 0x10 16.--17. "OVERLAP,OVERLAP" "0,1,2,3" newline endif sif (cpuis("STM32MP153*")) rbitfld.long 0x10 16.--17. "OVERLAP,OVERLAP" "0,1,2,3" endif sif (cpuis("STM32MP157*")) rbitfld.long 0x10 16.--17. "OVERLAP,OVERLAP" "0,1,2,3" newline endif sif (cpuis("STM32MP151*")) rbitfld.long 0x10 8.--9. "OVERRUN,OVERRUN" "0,1,2,3" endif sif (cpuis("STM32MP153*")) rbitfld.long 0x10 8.--9. "OVERRUN,OVERRUN" "0,1,2,3" newline endif sif (cpuis("STM32MP157*")) rbitfld.long 0x10 8.--9. "OVERRUN,OVERRUN" "0,1,2,3" endif sif (cpuis("STM32MP151*")) rbitfld.long 0x10 0.--1. "STATUS,STATUS" "0,1,2,3" newline endif sif (cpuis("STM32MP153*")) rbitfld.long 0x10 0.--1. "STATUS,STATUS" "0,1,2,3" endif sif (cpuis("STM32MP157*")) rbitfld.long 0x10 0.--1. "STATUS,STATUS" "0,1,2,3" endif wgroup.long 0x14++0x3 line.long 0x0 "TZC_INT_CLEAR,TZC interrupt clear register" sif (cpuis("STM32MP13*")) bitfld.long 0x0 0. "CLEAR,Filter interrupt clear" "0,1" endif sif (cpuis("STM32MP151*")) bitfld.long 0x0 0.--1. "CLEAR,CLEAR" "0,1,2,3" newline endif sif (cpuis("STM32MP153*")) bitfld.long 0x0 0.--1. "CLEAR,CLEAR" "0,1,2,3" endif sif (cpuis("STM32MP157*")) bitfld.long 0x0 0.--1. "CLEAR,CLEAR" "0,1,2,3" endif rgroup.long 0x108++0x3 line.long 0x0 "TZC_REGION_TOP_LOW0,TZC region 0 top address low register" sif (cpuis("STM32MP13*")) hexmask.long.tbyte 0x0 12.--31. 1. "TOP_ADDRESS_LOW,Top address bits [31:12] of region 0" endif sif (cpuis("STM32MP153*")) hexmask.long.tbyte 0x0 12.--31. 1. "TOP_ADDRESS_LOW,TOP_ADDRESS_LOW" newline endif sif (cpuis("STM32MP157*")) hexmask.long.tbyte 0x0 12.--31. 1. "TOP_ADDRESS_LOW,TOP_ADDRESS_LOW" endif group.long 0x110++0x7 line.long 0x0 "TZC_REGION_ATTRIBUTE0,TZC region 0 attribute register" sif (cpuis("STM32MP13*")) bitfld.long 0x0 31. "S_WR_EN,Secure global write enable" "0: secure write to the region are not allowed,1: permit secure write into the region" bitfld.long 0x0 30. "S_RD_EN,Secure global read enable" "0: secure read to the region are not allowed,1: permit secure read into the region" newline rbitfld.long 0x0 0. "FILTER_EN,Region enable for the filter" "?,1: enable filter for the region" endif sif (cpuis("STM32MP151*")) bitfld.long 0x0 31. "S_WR_EN,S_WR_EN" "0,1" newline bitfld.long 0x0 30. "S_RD_EN,S_RD_EN" "0,1" endif sif (cpuis("STM32MP153*")) bitfld.long 0x0 31. "S_WR_EN,S_WR_EN" "0,1" newline bitfld.long 0x0 30. "S_RD_EN,S_RD_EN" "0,1" endif sif (cpuis("STM32MP157*")) bitfld.long 0x0 31. "S_WR_EN,S_WR_EN" "0,1" newline bitfld.long 0x0 30. "S_RD_EN,S_RD_EN" "0,1" endif sif (cpuis("STM32MP151*")) rbitfld.long 0x0 0.--1. "FILTER_EN,FILTER_EN" "0,1,2,3" newline endif sif (cpuis("STM32MP153*")) rbitfld.long 0x0 0.--1. "FILTER_EN,FILTER_EN" "0,1,2,3" endif sif (cpuis("STM32MP157*")) rbitfld.long 0x0 0.--1. "FILTER_EN,FILTER_EN" "0,1,2,3" endif line.long 0x4 "TZC_REGION_ID_ACCESS0,TZC region 0 ID access register" sif (cpuis("STM32MP13*")) hexmask.long.word 0x4 16.--31. 1. "NSAID_WR_EN,Region write enable for each NSAID" hexmask.long.word 0x4 0.--15. 1. "NSAID_RD_EN,Region read enable for each NSAID" newline endif sif (cpuis("STM32MP151*")) hexmask.long.word 0x4 16.--31. 1. "NSAID_WR_EN,NSAID_WR_EN" endif sif (cpuis("STM32MP153*")) hexmask.long.word 0x4 16.--31. 1. "NSAID_WR_EN,NSAID_WR_EN" newline hexmask.long.word 0x4 0.--15. 1. "NSAID_RD_EN,NSAID_RD_EN" endif sif (cpuis("STM32MP157*")) hexmask.long.word 0x4 16.--31. 1. "NSAID_WR_EN,NSAID_WR_EN" newline hexmask.long.word 0x4 0.--15. 1. "NSAID_RD_EN,NSAID_RD_EN" endif group.long 0x120++0x3 line.long 0x0 "TZC_REGION_BASE_LOW1,TZC region 1 base address low register" hexmask.long.tbyte 0x0 12.--31. 1. "BASE_ADDRESS_LOW,Base address bits[31:12] for region x" group.long 0x128++0x3 line.long 0x0 "TZC_REGION_TOP_LOW1,TZC regions 1 top address low register" hexmask.long.tbyte 0x0 12.--31. 1. "TOP_ADDRESS_LOW,Top address bits [31:12] of region x" group.long 0x130++0x7 line.long 0x0 "TZC_REGION_ATTRIBUTE1,TZC region 1 attribute register" sif (cpuis("STM32MP13*")) bitfld.long 0x0 31. "S_WR_EN,Secure global write enable" "0: secure write to the region are not allowed,1: permit secure write into the region" bitfld.long 0x0 30. "S_RD_EN,Secure global read enable" "0: secure read to the region are not allowed,1: permit secure read into the region" newline bitfld.long 0x0 0. "FILTER_EN,Region enable for the filter" "0: disable filter for the region,1: enable filter for the region" endif sif (cpuis("STM32MP151*")) bitfld.long 0x0 31. "S_WR_EN,S_WR_EN" "0,1" newline bitfld.long 0x0 30. "S_RD_EN,S_RD_EN" "0,1" endif sif (cpuis("STM32MP153*")) bitfld.long 0x0 31. "S_WR_EN,S_WR_EN" "0,1" newline bitfld.long 0x0 30. "S_RD_EN,S_RD_EN" "0,1" endif sif (cpuis("STM32MP157*")) bitfld.long 0x0 31. "S_WR_EN,S_WR_EN" "0,1" newline bitfld.long 0x0 30. "S_RD_EN,S_RD_EN" "0,1" endif sif (cpuis("STM32MP151*")) bitfld.long 0x0 0.--1. "FILTER_EN,FILTER_EN" "0,1,2,3" newline endif sif (cpuis("STM32MP153*")) bitfld.long 0x0 0.--1. "FILTER_EN,FILTER_EN" "0,1,2,3" endif sif (cpuis("STM32MP157*")) bitfld.long 0x0 0.--1. "FILTER_EN,FILTER_EN" "0,1,2,3" endif line.long 0x4 "TZC_REGION_ID_ACCESS1,TZC region 1 ID access register" sif (cpuis("STM32MP13*")) hexmask.long.word 0x4 16.--31. 1. "NSAID_WR_EN,Region write enable for each NSAID" hexmask.long.word 0x4 0.--15. 1. "NSAID_RD_EN,Region read enable for each NSAID" newline endif sif (cpuis("STM32MP151*")) hexmask.long.word 0x4 16.--31. 1. "NSAID_WR_EN,NSAID_WR_EN" endif sif (cpuis("STM32MP153*")) hexmask.long.word 0x4 16.--31. 1. "NSAID_WR_EN,NSAID_WR_EN" newline hexmask.long.word 0x4 0.--15. 1. "NSAID_RD_EN,NSAID_RD_EN" endif sif (cpuis("STM32MP157*")) hexmask.long.word 0x4 16.--31. 1. "NSAID_WR_EN,NSAID_WR_EN" newline hexmask.long.word 0x4 0.--15. 1. "NSAID_RD_EN,NSAID_RD_EN" endif group.long 0x140++0x3 line.long 0x0 "TZC_REGION_BASE_LOW2,TZC region 2 base address low register" hexmask.long.tbyte 0x0 12.--31. 1. "BASE_ADDRESS_LOW,Base address bits[31:12] for region x" group.long 0x148++0x3 line.long 0x0 "TZC_REGION_TOP_LOW2,TZC regions 2 top address low register" hexmask.long.tbyte 0x0 12.--31. 1. "TOP_ADDRESS_LOW,Top address bits [31:12] of region x" group.long 0x150++0x7 line.long 0x0 "TZC_REGION_ATTRIBUTE2,TZC region 2 attribute register" sif (cpuis("STM32MP13*")) bitfld.long 0x0 31. "S_WR_EN,Secure global write enable" "0: secure write to the region are not allowed,1: permit secure write into the region" bitfld.long 0x0 30. "S_RD_EN,Secure global read enable" "0: secure read to the region are not allowed,1: permit secure read into the region" newline bitfld.long 0x0 0. "FILTER_EN,Region enable for the filter" "0: disable filter for the region,1: enable filter for the region" endif sif (cpuis("STM32MP151*")) bitfld.long 0x0 31. "S_WR_EN,S_WR_EN" "0,1" newline bitfld.long 0x0 30. "S_RD_EN,S_RD_EN" "0,1" endif sif (cpuis("STM32MP153*")) bitfld.long 0x0 31. "S_WR_EN,S_WR_EN" "0,1" newline bitfld.long 0x0 30. "S_RD_EN,S_RD_EN" "0,1" endif sif (cpuis("STM32MP157*")) bitfld.long 0x0 31. "S_WR_EN,S_WR_EN" "0,1" newline bitfld.long 0x0 30. "S_RD_EN,S_RD_EN" "0,1" endif sif (cpuis("STM32MP151*")) bitfld.long 0x0 0.--1. "FILTER_EN,FILTER_EN" "0,1,2,3" newline endif sif (cpuis("STM32MP153*")) bitfld.long 0x0 0.--1. "FILTER_EN,FILTER_EN" "0,1,2,3" endif sif (cpuis("STM32MP157*")) bitfld.long 0x0 0.--1. "FILTER_EN,FILTER_EN" "0,1,2,3" endif line.long 0x4 "TZC_REGION_ID_ACCESS2,TZC region 2 ID access register" sif (cpuis("STM32MP13*")) hexmask.long.word 0x4 16.--31. 1. "NSAID_WR_EN,Region write enable for each NSAID" hexmask.long.word 0x4 0.--15. 1. "NSAID_RD_EN,Region read enable for each NSAID" newline endif sif (cpuis("STM32MP151*")) hexmask.long.word 0x4 16.--31. 1. "NSAID_WR_EN,NSAID_WR_EN" endif sif (cpuis("STM32MP153*")) hexmask.long.word 0x4 16.--31. 1. "NSAID_WR_EN,NSAID_WR_EN" newline hexmask.long.word 0x4 0.--15. 1. "NSAID_RD_EN,NSAID_RD_EN" endif sif (cpuis("STM32MP157*")) hexmask.long.word 0x4 16.--31. 1. "NSAID_WR_EN,NSAID_WR_EN" newline hexmask.long.word 0x4 0.--15. 1. "NSAID_RD_EN,NSAID_RD_EN" endif group.long 0x160++0x3 line.long 0x0 "TZC_REGION_BASE_LOW3,TZC region 3 base address low register" hexmask.long.tbyte 0x0 12.--31. 1. "BASE_ADDRESS_LOW,Base address bits[31:12] for region x" group.long 0x168++0x3 line.long 0x0 "TZC_REGION_TOP_LOW3,TZC regions 3 top address low register" hexmask.long.tbyte 0x0 12.--31. 1. "TOP_ADDRESS_LOW,Top address bits [31:12] of region x" group.long 0x170++0x7 line.long 0x0 "TZC_REGION_ATTRIBUTE3,TZC region 3 attribute register" sif (cpuis("STM32MP13*")) bitfld.long 0x0 31. "S_WR_EN,Secure global write enable" "0: secure write to the region are not allowed,1: permit secure write into the region" bitfld.long 0x0 30. "S_RD_EN,Secure global read enable" "0: secure read to the region are not allowed,1: permit secure read into the region" newline bitfld.long 0x0 0. "FILTER_EN,Region enable for the filter" "0: disable filter for the region,1: enable filter for the region" endif sif (cpuis("STM32MP151*")) bitfld.long 0x0 31. "S_WR_EN,S_WR_EN" "0,1" newline bitfld.long 0x0 30. "S_RD_EN,S_RD_EN" "0,1" endif sif (cpuis("STM32MP153*")) bitfld.long 0x0 31. "S_WR_EN,S_WR_EN" "0,1" newline bitfld.long 0x0 30. "S_RD_EN,S_RD_EN" "0,1" endif sif (cpuis("STM32MP157*")) bitfld.long 0x0 31. "S_WR_EN,S_WR_EN" "0,1" newline bitfld.long 0x0 30. "S_RD_EN,S_RD_EN" "0,1" endif sif (cpuis("STM32MP151*")) bitfld.long 0x0 0.--1. "FILTER_EN,FILTER_EN" "0,1,2,3" newline endif sif (cpuis("STM32MP153*")) bitfld.long 0x0 0.--1. "FILTER_EN,FILTER_EN" "0,1,2,3" endif sif (cpuis("STM32MP157*")) bitfld.long 0x0 0.--1. "FILTER_EN,FILTER_EN" "0,1,2,3" endif line.long 0x4 "TZC_REGION_ID_ACCESS3,TZC region 3 ID access register" sif (cpuis("STM32MP13*")) hexmask.long.word 0x4 16.--31. 1. "NSAID_WR_EN,Region write enable for each NSAID" hexmask.long.word 0x4 0.--15. 1. "NSAID_RD_EN,Region read enable for each NSAID" newline endif sif (cpuis("STM32MP151*")) hexmask.long.word 0x4 16.--31. 1. "NSAID_WR_EN,NSAID_WR_EN" endif sif (cpuis("STM32MP153*")) hexmask.long.word 0x4 16.--31. 1. "NSAID_WR_EN,NSAID_WR_EN" newline hexmask.long.word 0x4 0.--15. 1. "NSAID_RD_EN,NSAID_RD_EN" endif sif (cpuis("STM32MP157*")) hexmask.long.word 0x4 16.--31. 1. "NSAID_WR_EN,NSAID_WR_EN" newline hexmask.long.word 0x4 0.--15. 1. "NSAID_RD_EN,NSAID_RD_EN" endif group.long 0x180++0x3 line.long 0x0 "TZC_REGION_BASE_LOW4,TZC region 4 base address low register" hexmask.long.tbyte 0x0 12.--31. 1. "BASE_ADDRESS_LOW,Base address bits[31:12] for region x" group.long 0x188++0x3 line.long 0x0 "TZC_REGION_TOP_LOW4,TZC regions 4 top address low register" hexmask.long.tbyte 0x0 12.--31. 1. "TOP_ADDRESS_LOW,Top address bits [31:12] of region x" group.long 0x190++0x7 line.long 0x0 "TZC_REGION_ATTRIBUTE4,TZC region 4 attribute register" sif (cpuis("STM32MP13*")) bitfld.long 0x0 31. "S_WR_EN,Secure global write enable" "0: secure write to the region are not allowed,1: permit secure write into the region" bitfld.long 0x0 30. "S_RD_EN,Secure global read enable" "0: secure read to the region are not allowed,1: permit secure read into the region" newline bitfld.long 0x0 0. "FILTER_EN,Region enable for the filter" "0: disable filter for the region,1: enable filter for the region" endif sif (cpuis("STM32MP151*")) bitfld.long 0x0 31. "S_WR_EN,S_WR_EN" "0,1" newline bitfld.long 0x0 30. "S_RD_EN,S_RD_EN" "0,1" endif sif (cpuis("STM32MP153*")) bitfld.long 0x0 31. "S_WR_EN,S_WR_EN" "0,1" newline bitfld.long 0x0 30. "S_RD_EN,S_RD_EN" "0,1" endif sif (cpuis("STM32MP157*")) bitfld.long 0x0 31. "S_WR_EN,S_WR_EN" "0,1" newline bitfld.long 0x0 30. "S_RD_EN,S_RD_EN" "0,1" endif sif (cpuis("STM32MP151*")) bitfld.long 0x0 0.--1. "FILTER_EN,FILTER_EN" "0,1,2,3" newline endif sif (cpuis("STM32MP153*")) bitfld.long 0x0 0.--1. "FILTER_EN,FILTER_EN" "0,1,2,3" endif sif (cpuis("STM32MP157*")) bitfld.long 0x0 0.--1. "FILTER_EN,FILTER_EN" "0,1,2,3" endif line.long 0x4 "TZC_REGION_ID_ACCESS4,TZC region 4 ID access register" sif (cpuis("STM32MP13*")) hexmask.long.word 0x4 16.--31. 1. "NSAID_WR_EN,Region write enable for each NSAID" hexmask.long.word 0x4 0.--15. 1. "NSAID_RD_EN,Region read enable for each NSAID" newline endif sif (cpuis("STM32MP151*")) hexmask.long.word 0x4 16.--31. 1. "NSAID_WR_EN,NSAID_WR_EN" endif sif (cpuis("STM32MP153*")) hexmask.long.word 0x4 16.--31. 1. "NSAID_WR_EN,NSAID_WR_EN" newline hexmask.long.word 0x4 0.--15. 1. "NSAID_RD_EN,NSAID_RD_EN" endif sif (cpuis("STM32MP157*")) hexmask.long.word 0x4 16.--31. 1. "NSAID_WR_EN,NSAID_WR_EN" newline hexmask.long.word 0x4 0.--15. 1. "NSAID_RD_EN,NSAID_RD_EN" endif group.long 0x1A0++0x3 line.long 0x0 "TZC_REGION_BASE_LOW5,TZC region 5 base address low register" hexmask.long.tbyte 0x0 12.--31. 1. "BASE_ADDRESS_LOW,Base address bits[31:12] for region x" group.long 0x1A8++0x3 line.long 0x0 "TZC_REGION_TOP_LOW5,TZC regions 5 top address low register" hexmask.long.tbyte 0x0 12.--31. 1. "TOP_ADDRESS_LOW,Top address bits [31:12] of region x" group.long 0x1B0++0x7 line.long 0x0 "TZC_REGION_ATTRIBUTE5,TZC region 5 attribute register" sif (cpuis("STM32MP13*")) bitfld.long 0x0 31. "S_WR_EN,Secure global write enable" "0: secure write to the region are not allowed,1: permit secure write into the region" bitfld.long 0x0 30. "S_RD_EN,Secure global read enable" "0: secure read to the region are not allowed,1: permit secure read into the region" newline bitfld.long 0x0 0. "FILTER_EN,Region enable for the filter" "0: disable filter for the region,1: enable filter for the region" endif sif (cpuis("STM32MP151*")) bitfld.long 0x0 31. "S_WR_EN,S_WR_EN" "0,1" newline bitfld.long 0x0 30. "S_RD_EN,S_RD_EN" "0,1" endif sif (cpuis("STM32MP153*")) bitfld.long 0x0 31. "S_WR_EN,S_WR_EN" "0,1" newline bitfld.long 0x0 30. "S_RD_EN,S_RD_EN" "0,1" endif sif (cpuis("STM32MP157*")) bitfld.long 0x0 31. "S_WR_EN,S_WR_EN" "0,1" newline bitfld.long 0x0 30. "S_RD_EN,S_RD_EN" "0,1" endif sif (cpuis("STM32MP151*")) bitfld.long 0x0 0.--1. "FILTER_EN,FILTER_EN" "0,1,2,3" newline endif sif (cpuis("STM32MP153*")) bitfld.long 0x0 0.--1. "FILTER_EN,FILTER_EN" "0,1,2,3" endif sif (cpuis("STM32MP157*")) bitfld.long 0x0 0.--1. "FILTER_EN,FILTER_EN" "0,1,2,3" endif line.long 0x4 "TZC_REGION_ID_ACCESS5,TZC region 5 ID access register" sif (cpuis("STM32MP13*")) hexmask.long.word 0x4 16.--31. 1. "NSAID_WR_EN,Region write enable for each NSAID" hexmask.long.word 0x4 0.--15. 1. "NSAID_RD_EN,Region read enable for each NSAID" newline endif sif (cpuis("STM32MP151*")) hexmask.long.word 0x4 16.--31. 1. "NSAID_WR_EN,NSAID_WR_EN" endif sif (cpuis("STM32MP153*")) hexmask.long.word 0x4 16.--31. 1. "NSAID_WR_EN,NSAID_WR_EN" newline hexmask.long.word 0x4 0.--15. 1. "NSAID_RD_EN,NSAID_RD_EN" endif sif (cpuis("STM32MP157*")) hexmask.long.word 0x4 16.--31. 1. "NSAID_WR_EN,NSAID_WR_EN" newline hexmask.long.word 0x4 0.--15. 1. "NSAID_RD_EN,NSAID_RD_EN" endif group.long 0x1C0++0x3 line.long 0x0 "TZC_REGION_BASE_LOW6,TZC region 6 base address low register" hexmask.long.tbyte 0x0 12.--31. 1. "BASE_ADDRESS_LOW,Base address bits[31:12] for region x" group.long 0x1C8++0x3 line.long 0x0 "TZC_REGION_TOP_LOW6,TZC regions 6 top address low register" hexmask.long.tbyte 0x0 12.--31. 1. "TOP_ADDRESS_LOW,Top address bits [31:12] of region x" group.long 0x1D0++0x7 line.long 0x0 "TZC_REGION_ATTRIBUTE6,TZC region 6 attribute register" sif (cpuis("STM32MP13*")) bitfld.long 0x0 31. "S_WR_EN,Secure global write enable" "0: secure write to the region are not allowed,1: permit secure write into the region" bitfld.long 0x0 30. "S_RD_EN,Secure global read enable" "0: secure read to the region are not allowed,1: permit secure read into the region" newline bitfld.long 0x0 0. "FILTER_EN,Region enable for the filter" "0: disable filter for the region,1: enable filter for the region" endif sif (cpuis("STM32MP151*")) bitfld.long 0x0 31. "S_WR_EN,S_WR_EN" "0,1" newline bitfld.long 0x0 30. "S_RD_EN,S_RD_EN" "0,1" endif sif (cpuis("STM32MP153*")) bitfld.long 0x0 31. "S_WR_EN,S_WR_EN" "0,1" newline bitfld.long 0x0 30. "S_RD_EN,S_RD_EN" "0,1" endif sif (cpuis("STM32MP157*")) bitfld.long 0x0 31. "S_WR_EN,S_WR_EN" "0,1" newline bitfld.long 0x0 30. "S_RD_EN,S_RD_EN" "0,1" endif sif (cpuis("STM32MP151*")) bitfld.long 0x0 0.--1. "FILTER_EN,FILTER_EN" "0,1,2,3" newline endif sif (cpuis("STM32MP153*")) bitfld.long 0x0 0.--1. "FILTER_EN,FILTER_EN" "0,1,2,3" endif sif (cpuis("STM32MP157*")) bitfld.long 0x0 0.--1. "FILTER_EN,FILTER_EN" "0,1,2,3" endif line.long 0x4 "TZC_REGION_ID_ACCESS6,TZC region 6 ID access register" sif (cpuis("STM32MP13*")) hexmask.long.word 0x4 16.--31. 1. "NSAID_WR_EN,Region write enable for each NSAID" hexmask.long.word 0x4 0.--15. 1. "NSAID_RD_EN,Region read enable for each NSAID" newline endif sif (cpuis("STM32MP151*")) hexmask.long.word 0x4 16.--31. 1. "NSAID_WR_EN,NSAID_WR_EN" endif sif (cpuis("STM32MP153*")) hexmask.long.word 0x4 16.--31. 1. "NSAID_WR_EN,NSAID_WR_EN" newline hexmask.long.word 0x4 0.--15. 1. "NSAID_RD_EN,NSAID_RD_EN" endif sif (cpuis("STM32MP157*")) hexmask.long.word 0x4 16.--31. 1. "NSAID_WR_EN,NSAID_WR_EN" newline hexmask.long.word 0x4 0.--15. 1. "NSAID_RD_EN,NSAID_RD_EN" endif group.long 0x1E8++0x3 line.long 0x0 "TZC_REGION_TOP_LOW7,TZC regions 7 top address low register" hexmask.long.tbyte 0x0 12.--31. 1. "TOP_ADDRESS_LOW,Top address bits [31:12] of region x" group.long 0x1F0++0x3 line.long 0x0 "TZC_REGION_ATTRIBUTE7,TZC region 7 attribute register" sif (cpuis("STM32MP13*")) bitfld.long 0x0 31. "S_WR_EN,Secure global write enable" "0: secure write to the region are not allowed,1: permit secure write into the region" bitfld.long 0x0 30. "S_RD_EN,Secure global read enable" "0: secure read to the region are not allowed,1: permit secure read into the region" newline bitfld.long 0x0 0. "FILTER_EN,Region enable for the filter" "0: disable filter for the region,1: enable filter for the region" endif sif (cpuis("STM32MP151*")) bitfld.long 0x0 31. "S_WR_EN,S_WR_EN" "0,1" newline bitfld.long 0x0 30. "S_RD_EN,S_RD_EN" "0,1" endif sif (cpuis("STM32MP153*")) bitfld.long 0x0 31. "S_WR_EN,S_WR_EN" "0,1" newline bitfld.long 0x0 30. "S_RD_EN,S_RD_EN" "0,1" endif sif (cpuis("STM32MP157*")) bitfld.long 0x0 31. "S_WR_EN,S_WR_EN" "0,1" newline bitfld.long 0x0 30. "S_RD_EN,S_RD_EN" "0,1" endif sif (cpuis("STM32MP151*")) bitfld.long 0x0 0.--1. "FILTER_EN,FILTER_EN" "0,1,2,3" newline endif sif (cpuis("STM32MP153*")) bitfld.long 0x0 0.--1. "FILTER_EN,FILTER_EN" "0,1,2,3" endif sif (cpuis("STM32MP157*")) bitfld.long 0x0 0.--1. "FILTER_EN,FILTER_EN" "0,1,2,3" endif group.long 0x200++0x3 line.long 0x0 "TZC_REGION_BASE_LOW8,TZC region 8 base address low register" hexmask.long.tbyte 0x0 12.--31. 1. "BASE_ADDRESS_LOW,Base address bits[31:12] for region x" group.long 0x210++0x3 line.long 0x0 "TZC_REGION_ATTRIBUTE8,TZC region 8 attribute register" sif (cpuis("STM32MP13*")) bitfld.long 0x0 31. "S_WR_EN,Secure global write enable" "0: secure write to the region are not allowed,1: permit secure write into the region" bitfld.long 0x0 0. "FILTER_EN,Region enable for the filter" "0: disable filter for the region,1: enable filter for the region" newline endif sif (cpuis("STM32MP151*")) bitfld.long 0x0 31. "S_WR_EN,S_WR_EN" "0,1" endif sif (cpuis("STM32MP153*")) bitfld.long 0x0 31. "S_WR_EN,S_WR_EN" "0,1" newline endif sif (cpuis("STM32MP157*")) bitfld.long 0x0 31. "S_WR_EN,S_WR_EN" "0,1" endif bitfld.long 0x0 30. "S_RD_EN,Secure global read enable" "0,1" newline sif (cpuis("STM32MP153*")) bitfld.long 0x0 0.--1. "FILTER_EN,FILTER_EN" "0,1,2,3" endif sif (cpuis("STM32MP157*")) bitfld.long 0x0 0.--1. "FILTER_EN,FILTER_EN" "0,1,2,3" newline endif sif (cpuis("STM32MP151*")) bitfld.long 0x0 0.--1. "FILTER_EN,FILTER_EN" "0,1,2,3" endif rgroup.long 0xFD0++0x2F line.long 0x0 "TZC_PID4,TZC peripheral ID 4 register" hexmask.long.byte 0x0 0.--7. 1. "PER_ID_4,Peripheral ID 4" line.long 0x4 "TZC_PID5,TZC peripheral ID 5 register" hexmask.long.byte 0x4 0.--7. 1. "PER_ID_5,Peripheral ID 5" line.long 0x8 "TZC_PID6,TZC peripheral ID 6 register" hexmask.long.byte 0x8 0.--7. 1. "PER_ID_6,Peripheral ID 6" line.long 0xC "TZC_PID7,TZC peripheral ID 7 register" hexmask.long.byte 0xC 0.--7. 1. "PER_ID_7,Peripheral ID 7" line.long 0x10 "TZC_PID0,TZC peripheral ID 0 register" hexmask.long.byte 0x10 0.--7. 1. "PER_ID_0,Peripheral ID 0" line.long 0x14 "TZC_PID1,TZC peripheral ID 1 register" hexmask.long.byte 0x14 0.--7. 1. "PER_ID_1,Peripheral ID 1" line.long 0x18 "TZC_PID2,TZC peripheral ID 2 register" hexmask.long.byte 0x18 0.--7. 1. "PER_ID_2,Peripheral ID 2" line.long 0x1C "TZC_PID3,TZC peripheral ID 3 register" hexmask.long.byte 0x1C 0.--7. 1. "PER_ID_3,Peripheral ID 3" line.long 0x20 "TZC_CID0,TZC component ID 0 register" hexmask.long.byte 0x20 0.--7. 1. "COMP_ID_0,Component ID 0" line.long 0x24 "TZC_CID1,TZC component ID 1 register" hexmask.long.byte 0x24 0.--7. 1. "COMP_ID_1,Component ID 0" line.long 0x28 "TZC_CID2,TZC component ID 2 register" hexmask.long.byte 0x28 0.--7. 1. "COMP_ID_2,Component ID 2" line.long 0x2C "TZC_CID3,TZC component ID 3 register" hexmask.long.byte 0x2C 0.--7. 1. "COMP_ID_3,Component ID 3" sif (cpuis("STM32MP13*")) rgroup.long 0x20++0x3 line.long 0x0 "TZC_FAIL_ADDRESS_LOW,TZC fail address low register x" hexmask.long 0x0 0.--31. 1. "ADDR_STATUS_LOW,Fail address low bits" rgroup.long 0x28++0x7 line.long 0x0 "TZC_FAIL_CONTROL,TZC fail control register x" bitfld.long 0x0 24. "DIRECTION,Access failure direction" "0: Read access failure,1: Write access failure" bitfld.long 0x0 21. "NON_SECURE,Non-secure access failure" "0: Secure access failure,1: Non-secure access failure" newline bitfld.long 0x0 20. "PRIVILEGE,Privilege access failure" "0: Unprivileged access failure,1: Privileged access failure" line.long 0x4 "TZC_FAIL_ID,TZC fail ID register x" hexmask.long.word 0x4 0.--10. 1. "ID,AXI fail ID" rgroup.long 0x100++0x3 line.long 0x0 "TZC_REGION_BASE_LOW0,TZC region 0 base address low register" hexmask.long.tbyte 0x0 12.--31. 1. "BASE_ADDRESS_LOW,base address bits[31:12] for region 0" group.long 0x1E0++0x3 line.long 0x0 "TZC_REGION_BASE_LOW7,TZC region 7 base address low register" hexmask.long.tbyte 0x0 12.--31. 1. "BASE_ADDRESS_LOW,Base address bits[31:12] for region x" group.long 0x1F4++0x3 line.long 0x0 "TZC_REGION_ID_ACCESS7,TZC region 7 ID access register" hexmask.long.word 0x0 16.--31. 1. "NSAID_WR_EN,Region write enable for each NSAID" hexmask.long.word 0x0 0.--15. 1. "NSAID_RD_EN,Region read enable for each NSAID" group.long 0x208++0x3 line.long 0x0 "TZC_REGION_TOP_LOW8,TZC regions 8 top address low register" hexmask.long.tbyte 0x0 12.--31. 1. "TOP_ADDRESS_LOW,Top address bits [31:12] of region x" group.long 0x214++0x3 line.long 0x0 "TZC_REGION_ID_ACCESS8,TZC region 8 ID access register" hexmask.long.word 0x0 16.--31. 1. "NSAID_WR_EN,Region write enable for each NSAID" hexmask.long.word 0x0 0.--15. 1. "NSAID_RD_EN,Region read enable for each NSAID" endif sif (cpuis("STM32MP151*")) rgroup.long 0x0++0x3 line.long 0x0 "TZC_BUILD_CONFIG,Provides information about TZC configuration." rgroup.long 0x20++0x7 line.long 0x0 "TZC_FAIL_ADDRESS_LOW0,Address low bits of the first failed access in the associated filter (0 to 1)." hexmask.long 0x0 0.--31. 1. "ADDR_STATUS_LOW,ADDR_STATUS_LOW" line.long 0x4 "TZC_FAIL_ADDRESS_HIGH0,Address high bit of the first failed access in the associated filter (0 to 1)." rgroup.long 0x30++0x7 line.long 0x0 "TZC_FAIL_ADDRESS_LOW1,Address low bits of the first failed access in the associated filter (0 to 1)." hexmask.long 0x0 0.--31. 1. "ADDR_STATUS_LOW,ADDR_STATUS_LOW" line.long 0x4 "TZC_FAIL_ADDRESS_HIGH1,Address high bit of the first failed access in the associated filter (0 to 1)." rgroup.long 0x104++0x3 line.long 0x0 "TZC_REGION_BASE_HIGH0,Base address high are not used with 32-bit address." rgroup.long 0x204++0x3 line.long 0x0 "TZC_REGION_BASE_HIGH8,Base address high are not used with 32-bit address." endif sif (cpuis("STM32MP151*")) rgroup.long 0x10++0x3 line.long 0x0 "TZC_INT_STATUS,Contains the status of the interrupt signal. TZCINT. that reports access security violations or region overlap errors." rgroup.long 0x28++0x7 line.long 0x0 "TZC_FAIL_CONTROL0,Status information about the first access that failed a region permission check in the associated filter (0 to 1)." bitfld.long 0x0 24. "DIRECTION,DIRECTION" "0,1" bitfld.long 0x0 21. "NON_SECURE,NON_SECURE" "0,1" newline bitfld.long 0x0 20. "PRIVILEGE,PRIVILEGE" "0,1" line.long 0x4 "TZC_FAIL_ID0,Contains the master AXI ARID or AWID of the first access that failed a region permission check in the associated filter unit. This occurs even if the ACTION register is set to not drive the interrupt signal." hexmask.long.word 0x4 0.--10. 1. "ID,ID" rgroup.long 0x38++0x7 line.long 0x0 "TZC_FAIL_CONTROL1,Status information about the first access that failed a region permission check in the associated filter (0 to 1)." bitfld.long 0x0 24. "DIRECTION,DIRECTION" "0,1" bitfld.long 0x0 21. "NON_SECURE,NON_SECURE" "0,1" newline bitfld.long 0x0 20. "PRIVILEGE,PRIVILEGE" "0,1" line.long 0x4 "TZC_FAIL_ID1,Contains the master AXI ARID or AWID of the first access that failed a region permission check in the associated filter unit. This occurs even if the ACTION register is set to not drive the interrupt signal." hexmask.long.word 0x4 0.--10. 1. "ID,ID" endif sif (cpuis("STM32MP151*")) rgroup.long 0xFD0++0x3 line.long 0x0 "TZC_PID4,Peripheral ID 4." hexmask.long.byte 0x0 0.--7. 1. "PER_ID_4,PER_ID_4" endif sif (cpuis("STM32MP151*")) rgroup.long 0xFD4++0x3 line.long 0x0 "TZC_PID5,Peripheral ID 5." hexmask.long.byte 0x0 0.--7. 1. "PER_ID_5,PER_ID_5" endif sif (cpuis("STM32MP151*")) rgroup.long 0xFD8++0x3 line.long 0x0 "TZC_PID6,Peripheral ID 6." hexmask.long.byte 0x0 0.--7. 1. "PER_ID_6,PER_ID_6" endif sif (cpuis("STM32MP151*")) rgroup.long 0xFDC++0x3 line.long 0x0 "TZC_PID7,Peripheral ID 7." hexmask.long.byte 0x0 0.--7. 1. "PER_ID_7,PER_ID_7" endif sif (cpuis("STM32MP151*")) rgroup.long 0xFE0++0x3 line.long 0x0 "TZC_PID0,Peripheral ID 0." hexmask.long.byte 0x0 0.--7. 1. "PER_ID_0,PER_ID_0" endif sif (cpuis("STM32MP151*")) rgroup.long 0xFE4++0x3 line.long 0x0 "TZC_PID1,Peripheral ID 1." hexmask.long.byte 0x0 0.--7. 1. "PER_ID_1,PER_ID_1" endif sif (cpuis("STM32MP151*")) rgroup.long 0xFE8++0x3 line.long 0x0 "TZC_PID2,Peripheral ID 2." hexmask.long.byte 0x0 0.--7. 1. "PER_ID_2,PER_ID_2" endif sif (cpuis("STM32MP151*")) rgroup.long 0xFEC++0x3 line.long 0x0 "TZC_PID3,Peripheral ID 3." hexmask.long.byte 0x0 0.--7. 1. "PER_ID_3,PER_ID_3" endif sif (cpuis("STM32MP151*")) rgroup.long 0xFF0++0x3 line.long 0x0 "TZC_CID0,Component ID 0." hexmask.long.byte 0x0 0.--7. 1. "COMP_ID_0,COMP_ID_0" endif sif (cpuis("STM32MP151*")) rgroup.long 0xFF4++0x3 line.long 0x0 "TZC_CID1,Component ID 1." hexmask.long.byte 0x0 0.--7. 1. "COMP_ID_1,COMP_ID_1" endif sif (cpuis("STM32MP151*")) rgroup.long 0xFF8++0x3 line.long 0x0 "TZC_CID2,Component ID 2." hexmask.long.byte 0x0 0.--7. 1. "COMP_ID_2,COMP_ID_2" endif sif (cpuis("STM32MP151*")) rgroup.long 0xFFC++0x3 line.long 0x0 "TZC_CID3,Component ID 3." hexmask.long.byte 0x0 0.--7. 1. "COMP_ID_3,COMP_ID_3" endif sif (cpuis("STM32MP151*")) rgroup.long 0x108++0x7 line.long 0x0 "TZC_REGION_TOP_LOW0,Top address bits [31:12] for region 0." line.long 0x4 "TZC_REGION_TOP_HIGH0,Top address high of region are not used with 32-bit address." rgroup.long 0x124++0x3 line.long 0x0 "TZC_REGION_BASE_HIGH1,Base address high are not used with 32-bit address." rgroup.long 0x12C++0x3 line.long 0x0 "TZC_REGION_TOP_HIGH1,Top address high of region are not used with 32-bit address." rgroup.long 0x144++0x3 line.long 0x0 "TZC_REGION_BASE_HIGH2,Base address high are not used with 32-bit address." rgroup.long 0x14C++0x3 line.long 0x0 "TZC_REGION_TOP_HIGH2,Top address high of region are not used with 32-bit address." rgroup.long 0x164++0x3 line.long 0x0 "TZC_REGION_BASE_HIGH3,Base address high are not used with 32-bit address." rgroup.long 0x16C++0x3 line.long 0x0 "TZC_REGION_TOP_HIGH3,Top address high of region are not used with 32-bit address." rgroup.long 0x184++0x3 line.long 0x0 "TZC_REGION_BASE_HIGH4,Base address high are not used with 32-bit address." rgroup.long 0x18C++0x3 line.long 0x0 "TZC_REGION_TOP_HIGH4,Top address high of region are not used with 32-bit address." rgroup.long 0x1A4++0x3 line.long 0x0 "TZC_REGION_BASE_HIGH5,Base address high are not used with 32-bit address." rgroup.long 0x1AC++0x3 line.long 0x0 "TZC_REGION_TOP_HIGH5,Top address high of region are not used with 32-bit address." rgroup.long 0x1C4++0x3 line.long 0x0 "TZC_REGION_BASE_HIGH6,Base address high are not used with 32-bit address." rgroup.long 0x1CC++0x3 line.long 0x0 "TZC_REGION_TOP_HIGH6,Top address high of region are not used with 32-bit address." group.long 0x2E0++0x3 line.long 0x0 "TZC_REGION_BASE_LOW7,Base address low for regions 1 to 8." hexmask.long.tbyte 0x0 12.--31. 1. "BASE_ADDRESS_LOW,BASE_ADDRESS_LOW" rgroup.long 0x2E4++0x3 line.long 0x0 "TZC_REGION_BASE_HIGH7,Base address high are not used with 32-bit address." rgroup.long 0x2EC++0x3 line.long 0x0 "TZC_REGION_TOP_HIGH7,Top address high of region are not used with 32-bit address." group.long 0x2F4++0x3 line.long 0x0 "TZC_REGION_ID_ACCESS7,Region non-secure access based on NSAID." hexmask.long.word 0x0 16.--31. 1. "NSAID_WR_EN,NSAID_WR_EN" hexmask.long.word 0x0 0.--15. 1. "NSAID_RD_EN,NSAID_RD_EN" group.long 0x308++0x3 line.long 0x0 "TZC_REGION_TOP_LOW8,Top address bits [31:12] for region x." hexmask.long.tbyte 0x0 12.--31. 1. "TOP_ADDRESS_LOW,TOP_ADDRESS_LOW" rgroup.long 0x30C++0x3 line.long 0x0 "TZC_REGION_TOP_HIGH8,Top address high of region are not used with 32-bit address." group.long 0x314++0x3 line.long 0x0 "TZC_REGION_ID_ACCESS8,Region non-secure access based on NSAID." hexmask.long.word 0x0 16.--31. 1. "NSAID_WR_EN,NSAID_WR_EN" hexmask.long.word 0x0 0.--15. 1. "NSAID_RD_EN,NSAID_RD_EN" endif sif (cpuis("STM32MP153*")) rgroup.long 0x0++0x3 line.long 0x0 "TZC_BUILD_CONFIG,Provides information about TZC configuration." rgroup.long 0x20++0x7 line.long 0x0 "TZC_FAIL_ADDRESS_LOW0,Address low bits of the first failed access in the associated filter (0 to 1)." hexmask.long 0x0 0.--31. 1. "ADDR_STATUS_LOW,ADDR_STATUS_LOW" line.long 0x4 "TZC_FAIL_ADDRESS_HIGH0,Address high bit of the first failed access in the associated filter (0 to 1)." rgroup.long 0x30++0x7 line.long 0x0 "TZC_FAIL_ADDRESS_LOW1,Address low bits of the first failed access in the associated filter (0 to 1)." hexmask.long 0x0 0.--31. 1. "ADDR_STATUS_LOW,ADDR_STATUS_LOW" line.long 0x4 "TZC_FAIL_ADDRESS_HIGH1,Address high bit of the first failed access in the associated filter (0 to 1)." rgroup.long 0x104++0x3 line.long 0x0 "TZC_REGION_BASE_HIGH0,Base address high are not used with 32-bit address." rgroup.long 0x204++0x3 line.long 0x0 "TZC_REGION_BASE_HIGH8,Base address high are not used with 32-bit address." endif sif (cpuis("STM32MP153*")) rgroup.long 0x10++0x3 line.long 0x0 "TZC_INT_STATUS,Contains the status of the interrupt signal. TZCINT. that reports access security violations or region overlap errors." rgroup.long 0x28++0x7 line.long 0x0 "TZC_FAIL_CONTROL0,Status information about the first access that failed a region permission check in the associated filter (0 to 1)." bitfld.long 0x0 24. "DIRECTION,DIRECTION" "0,1" bitfld.long 0x0 21. "NON_SECURE,NON_SECURE" "0,1" newline bitfld.long 0x0 20. "PRIVILEGE,PRIVILEGE" "0,1" line.long 0x4 "TZC_FAIL_ID0,Contains the master AXI ARID or AWID of the first access that failed a region permission check in the associated filter unit. This occurs even if the ACTION register is set to not drive the interrupt signal." hexmask.long.word 0x4 0.--10. 1. "ID,ID" rgroup.long 0x38++0x7 line.long 0x0 "TZC_FAIL_CONTROL1,Status information about the first access that failed a region permission check in the associated filter (0 to 1)." bitfld.long 0x0 24. "DIRECTION,DIRECTION" "0,1" bitfld.long 0x0 21. "NON_SECURE,NON_SECURE" "0,1" newline bitfld.long 0x0 20. "PRIVILEGE,PRIVILEGE" "0,1" line.long 0x4 "TZC_FAIL_ID1,Contains the master AXI ARID or AWID of the first access that failed a region permission check in the associated filter unit. This occurs even if the ACTION register is set to not drive the interrupt signal." hexmask.long.word 0x4 0.--10. 1. "ID,ID" endif sif (cpuis("STM32MP153*")) rgroup.long 0xFD0++0x3 line.long 0x0 "TZC_PID4,Peripheral ID 4." hexmask.long.byte 0x0 0.--7. 1. "PER_ID_4,PER_ID_4" endif sif (cpuis("STM32MP153*")) rgroup.long 0xFD4++0x3 line.long 0x0 "TZC_PID5,Peripheral ID 5." hexmask.long.byte 0x0 0.--7. 1. "PER_ID_5,PER_ID_5" endif sif (cpuis("STM32MP153*")) rgroup.long 0xFD8++0x3 line.long 0x0 "TZC_PID6,Peripheral ID 6." hexmask.long.byte 0x0 0.--7. 1. "PER_ID_6,PER_ID_6" endif sif (cpuis("STM32MP153*")) rgroup.long 0xFDC++0x3 line.long 0x0 "TZC_PID7,Peripheral ID 7." hexmask.long.byte 0x0 0.--7. 1. "PER_ID_7,PER_ID_7" endif sif (cpuis("STM32MP153*")) rgroup.long 0xFE0++0x3 line.long 0x0 "TZC_PID0,Peripheral ID 0." hexmask.long.byte 0x0 0.--7. 1. "PER_ID_0,PER_ID_0" endif sif (cpuis("STM32MP153*")) rgroup.long 0xFE4++0x3 line.long 0x0 "TZC_PID1,Peripheral ID 1." hexmask.long.byte 0x0 0.--7. 1. "PER_ID_1,PER_ID_1" endif sif (cpuis("STM32MP153*")) rgroup.long 0xFE8++0x3 line.long 0x0 "TZC_PID2,Peripheral ID 2." hexmask.long.byte 0x0 0.--7. 1. "PER_ID_2,PER_ID_2" endif sif (cpuis("STM32MP153*")) rgroup.long 0xFEC++0x3 line.long 0x0 "TZC_PID3,Peripheral ID 3." hexmask.long.byte 0x0 0.--7. 1. "PER_ID_3,PER_ID_3" endif sif (cpuis("STM32MP153*")) rgroup.long 0xFF0++0x3 line.long 0x0 "TZC_CID0,Component ID 0." hexmask.long.byte 0x0 0.--7. 1. "COMP_ID_0,COMP_ID_0" endif sif (cpuis("STM32MP153*")) rgroup.long 0xFF4++0x3 line.long 0x0 "TZC_CID1,Component ID 1." hexmask.long.byte 0x0 0.--7. 1. "COMP_ID_1,COMP_ID_1" endif sif (cpuis("STM32MP153*")) rgroup.long 0xFF8++0x3 line.long 0x0 "TZC_CID2,Component ID 2." hexmask.long.byte 0x0 0.--7. 1. "COMP_ID_2,COMP_ID_2" endif sif (cpuis("STM32MP153*")) rgroup.long 0xFFC++0x3 line.long 0x0 "TZC_CID3,Component ID 3." hexmask.long.byte 0x0 0.--7. 1. "COMP_ID_3,COMP_ID_3" endif sif (cpuis("STM32MP153*")) rgroup.long 0x108++0x7 line.long 0x0 "TZC_REGION_TOP_LOW0,Top address bits [31:12] for region 0." line.long 0x4 "TZC_REGION_TOP_HIGH0,Top address high of region are not used with 32-bit address." rgroup.long 0x124++0x3 line.long 0x0 "TZC_REGION_BASE_HIGH1,Base address high are not used with 32-bit address." rgroup.long 0x12C++0x3 line.long 0x0 "TZC_REGION_TOP_HIGH1,Top address high of region are not used with 32-bit address." rgroup.long 0x144++0x3 line.long 0x0 "TZC_REGION_BASE_HIGH2,Base address high are not used with 32-bit address." rgroup.long 0x14C++0x3 line.long 0x0 "TZC_REGION_TOP_HIGH2,Top address high of region are not used with 32-bit address." rgroup.long 0x164++0x3 line.long 0x0 "TZC_REGION_BASE_HIGH3,Base address high are not used with 32-bit address." rgroup.long 0x16C++0x3 line.long 0x0 "TZC_REGION_TOP_HIGH3,Top address high of region are not used with 32-bit address." rgroup.long 0x184++0x3 line.long 0x0 "TZC_REGION_BASE_HIGH4,Base address high are not used with 32-bit address." rgroup.long 0x18C++0x3 line.long 0x0 "TZC_REGION_TOP_HIGH4,Top address high of region are not used with 32-bit address." rgroup.long 0x1A4++0x3 line.long 0x0 "TZC_REGION_BASE_HIGH5,Base address high are not used with 32-bit address." rgroup.long 0x1AC++0x3 line.long 0x0 "TZC_REGION_TOP_HIGH5,Top address high of region are not used with 32-bit address." rgroup.long 0x1C4++0x3 line.long 0x0 "TZC_REGION_BASE_HIGH6,Base address high are not used with 32-bit address." rgroup.long 0x1CC++0x3 line.long 0x0 "TZC_REGION_TOP_HIGH6,Top address high of region are not used with 32-bit address." group.long 0x2E0++0x3 line.long 0x0 "TZC_REGION_BASE_LOW7,Base address low for regions 1 to 8." hexmask.long.tbyte 0x0 12.--31. 1. "BASE_ADDRESS_LOW,BASE_ADDRESS_LOW" rgroup.long 0x2E4++0x3 line.long 0x0 "TZC_REGION_BASE_HIGH7,Base address high are not used with 32-bit address." rgroup.long 0x2EC++0x3 line.long 0x0 "TZC_REGION_TOP_HIGH7,Top address high of region are not used with 32-bit address." group.long 0x2F4++0x3 line.long 0x0 "TZC_REGION_ID_ACCESS7,Region non-secure access based on NSAID." hexmask.long.word 0x0 16.--31. 1. "NSAID_WR_EN,NSAID_WR_EN" hexmask.long.word 0x0 0.--15. 1. "NSAID_RD_EN,NSAID_RD_EN" group.long 0x308++0x3 line.long 0x0 "TZC_REGION_TOP_LOW8,Top address bits [31:12] for region x." hexmask.long.tbyte 0x0 12.--31. 1. "TOP_ADDRESS_LOW,TOP_ADDRESS_LOW" rgroup.long 0x30C++0x3 line.long 0x0 "TZC_REGION_TOP_HIGH8,Top address high of region are not used with 32-bit address." group.long 0x314++0x3 line.long 0x0 "TZC_REGION_ID_ACCESS8,Region non-secure access based on NSAID." hexmask.long.word 0x0 16.--31. 1. "NSAID_WR_EN,NSAID_WR_EN" hexmask.long.word 0x0 0.--15. 1. "NSAID_RD_EN,NSAID_RD_EN" endif sif (cpuis("STM32MP157*")) rgroup.long 0x0++0x3 line.long 0x0 "TZC_BUILD_CONFIG,Provides information about TZC configuration." rgroup.long 0x20++0x7 line.long 0x0 "TZC_FAIL_ADDRESS_LOW0,Address low bits of the first failed access in the associated filter (0 to 1)." hexmask.long 0x0 0.--31. 1. "ADDR_STATUS_LOW,ADDR_STATUS_LOW" line.long 0x4 "TZC_FAIL_ADDRESS_HIGH0,Address high bit of the first failed access in the associated filter (0 to 1)." rgroup.long 0x30++0x7 line.long 0x0 "TZC_FAIL_ADDRESS_LOW1,Address low bits of the first failed access in the associated filter (0 to 1)." hexmask.long 0x0 0.--31. 1. "ADDR_STATUS_LOW,ADDR_STATUS_LOW" line.long 0x4 "TZC_FAIL_ADDRESS_HIGH1,Address high bit of the first failed access in the associated filter (0 to 1)." rgroup.long 0x104++0x3 line.long 0x0 "TZC_REGION_BASE_HIGH0,Base address high are not used with 32-bit address." rgroup.long 0x204++0x3 line.long 0x0 "TZC_REGION_BASE_HIGH8,Base address high are not used with 32-bit address." endif sif (cpuis("STM32MP157*")) rgroup.long 0x10++0x3 line.long 0x0 "TZC_INT_STATUS,Contains the status of the interrupt signal. TZCINT. that reports access security violations or region overlap errors." rgroup.long 0x28++0x7 line.long 0x0 "TZC_FAIL_CONTROL0,Status information about the first access that failed a region permission check in the associated filter (0 to 1)." bitfld.long 0x0 24. "DIRECTION,DIRECTION" "0,1" bitfld.long 0x0 21. "NON_SECURE,NON_SECURE" "0,1" newline bitfld.long 0x0 20. "PRIVILEGE,PRIVILEGE" "0,1" line.long 0x4 "TZC_FAIL_ID0,Contains the master AXI ARID or AWID of the first access that failed a region permission check in the associated filter unit. This occurs even if the ACTION register is set to not drive the interrupt signal." hexmask.long.word 0x4 0.--10. 1. "ID,ID" rgroup.long 0x38++0x7 line.long 0x0 "TZC_FAIL_CONTROL1,Status information about the first access that failed a region permission check in the associated filter (0 to 1)." bitfld.long 0x0 24. "DIRECTION,DIRECTION" "0,1" bitfld.long 0x0 21. "NON_SECURE,NON_SECURE" "0,1" newline bitfld.long 0x0 20. "PRIVILEGE,PRIVILEGE" "0,1" line.long 0x4 "TZC_FAIL_ID1,Contains the master AXI ARID or AWID of the first access that failed a region permission check in the associated filter unit. This occurs even if the ACTION register is set to not drive the interrupt signal." hexmask.long.word 0x4 0.--10. 1. "ID,ID" endif sif (cpuis("STM32MP157*")) rgroup.long 0xFD0++0x3 line.long 0x0 "TZC_PID4,Peripheral ID 4." hexmask.long.byte 0x0 0.--7. 1. "PER_ID_4,PER_ID_4" endif sif (cpuis("STM32MP157*")) rgroup.long 0xFD4++0x3 line.long 0x0 "TZC_PID5,Peripheral ID 5." hexmask.long.byte 0x0 0.--7. 1. "PER_ID_5,PER_ID_5" endif sif (cpuis("STM32MP157*")) rgroup.long 0xFD8++0x3 line.long 0x0 "TZC_PID6,Peripheral ID 6." hexmask.long.byte 0x0 0.--7. 1. "PER_ID_6,PER_ID_6" endif sif (cpuis("STM32MP157*")) rgroup.long 0xFDC++0x3 line.long 0x0 "TZC_PID7,Peripheral ID 7." hexmask.long.byte 0x0 0.--7. 1. "PER_ID_7,PER_ID_7" endif sif (cpuis("STM32MP157*")) rgroup.long 0xFE0++0x3 line.long 0x0 "TZC_PID0,Peripheral ID 0." hexmask.long.byte 0x0 0.--7. 1. "PER_ID_0,PER_ID_0" endif sif (cpuis("STM32MP157*")) rgroup.long 0xFE4++0x3 line.long 0x0 "TZC_PID1,Peripheral ID 1." hexmask.long.byte 0x0 0.--7. 1. "PER_ID_1,PER_ID_1" endif sif (cpuis("STM32MP157*")) rgroup.long 0xFE8++0x3 line.long 0x0 "TZC_PID2,Peripheral ID 2." hexmask.long.byte 0x0 0.--7. 1. "PER_ID_2,PER_ID_2" endif sif (cpuis("STM32MP157*")) rgroup.long 0xFEC++0x3 line.long 0x0 "TZC_PID3,Peripheral ID 3." hexmask.long.byte 0x0 0.--7. 1. "PER_ID_3,PER_ID_3" endif sif (cpuis("STM32MP157*")) rgroup.long 0xFF0++0x3 line.long 0x0 "TZC_CID0,Component ID 0." hexmask.long.byte 0x0 0.--7. 1. "COMP_ID_0,COMP_ID_0" endif sif (cpuis("STM32MP157*")) rgroup.long 0xFF4++0x3 line.long 0x0 "TZC_CID1,Component ID 1." hexmask.long.byte 0x0 0.--7. 1. "COMP_ID_1,COMP_ID_1" endif sif (cpuis("STM32MP157*")) rgroup.long 0xFF8++0x3 line.long 0x0 "TZC_CID2,Component ID 2." hexmask.long.byte 0x0 0.--7. 1. "COMP_ID_2,COMP_ID_2" endif sif (cpuis("STM32MP157*")) rgroup.long 0xFFC++0x3 line.long 0x0 "TZC_CID3,Component ID 3." hexmask.long.byte 0x0 0.--7. 1. "COMP_ID_3,COMP_ID_3" endif sif (cpuis("STM32MP157*")) rgroup.long 0x108++0x7 line.long 0x0 "TZC_REGION_TOP_LOW0,Top address bits [31:12] for region 0." line.long 0x4 "TZC_REGION_TOP_HIGH0,Top address high of region are not used with 32-bit address." rgroup.long 0x124++0x3 line.long 0x0 "TZC_REGION_BASE_HIGH1,Base address high are not used with 32-bit address." rgroup.long 0x12C++0x3 line.long 0x0 "TZC_REGION_TOP_HIGH1,Top address high of region are not used with 32-bit address." rgroup.long 0x144++0x3 line.long 0x0 "TZC_REGION_BASE_HIGH2,Base address high are not used with 32-bit address." rgroup.long 0x14C++0x3 line.long 0x0 "TZC_REGION_TOP_HIGH2,Top address high of region are not used with 32-bit address." rgroup.long 0x164++0x3 line.long 0x0 "TZC_REGION_BASE_HIGH3,Base address high are not used with 32-bit address." rgroup.long 0x16C++0x3 line.long 0x0 "TZC_REGION_TOP_HIGH3,Top address high of region are not used with 32-bit address." rgroup.long 0x184++0x3 line.long 0x0 "TZC_REGION_BASE_HIGH4,Base address high are not used with 32-bit address." rgroup.long 0x18C++0x3 line.long 0x0 "TZC_REGION_TOP_HIGH4,Top address high of region are not used with 32-bit address." rgroup.long 0x1A4++0x3 line.long 0x0 "TZC_REGION_BASE_HIGH5,Base address high are not used with 32-bit address." rgroup.long 0x1AC++0x3 line.long 0x0 "TZC_REGION_TOP_HIGH5,Top address high of region are not used with 32-bit address." rgroup.long 0x1C4++0x3 line.long 0x0 "TZC_REGION_BASE_HIGH6,Base address high are not used with 32-bit address." rgroup.long 0x1CC++0x3 line.long 0x0 "TZC_REGION_TOP_HIGH6,Top address high of region are not used with 32-bit address." group.long 0x2E0++0x3 line.long 0x0 "TZC_REGION_BASE_LOW7,Base address low for regions 1 to 8." hexmask.long.tbyte 0x0 12.--31. 1. "BASE_ADDRESS_LOW,BASE_ADDRESS_LOW" rgroup.long 0x2E4++0x3 line.long 0x0 "TZC_REGION_BASE_HIGH7,Base address high are not used with 32-bit address." rgroup.long 0x2EC++0x3 line.long 0x0 "TZC_REGION_TOP_HIGH7,Top address high of region are not used with 32-bit address." group.long 0x2F4++0x3 line.long 0x0 "TZC_REGION_ID_ACCESS7,Region non-secure access based on NSAID." hexmask.long.word 0x0 16.--31. 1. "NSAID_WR_EN,NSAID_WR_EN" hexmask.long.word 0x0 0.--15. 1. "NSAID_RD_EN,NSAID_RD_EN" group.long 0x308++0x3 line.long 0x0 "TZC_REGION_TOP_LOW8,Top address bits [31:12] for region x." hexmask.long.tbyte 0x0 12.--31. 1. "TOP_ADDRESS_LOW,TOP_ADDRESS_LOW" rgroup.long 0x30C++0x3 line.long 0x0 "TZC_REGION_TOP_HIGH8,Top address high of region are not used with 32-bit address." group.long 0x314++0x3 line.long 0x0 "TZC_REGION_ID_ACCESS8,Region non-secure access based on NSAID." hexmask.long.word 0x0 16.--31. 1. "NSAID_WR_EN,NSAID_WR_EN" hexmask.long.word 0x0 0.--15. 1. "NSAID_RD_EN,NSAID_RD_EN" endif tree.end tree "USART (Universal Synchronous/Asynchronous Receiver Transmitter)" base ad:0x0 sif (cpuis("STM32MP13*")) base ad:0x4C000000 elif (cpuis("STM32MP151*")) base ad:0x5C000000 endif sif (cpuis("STM32MP13*")||cpuis("STM32MP151*")) tree "USART1" sif (cpuis("STM32MP13*")) group.long 0x0++0x3 line.long 0x0 "CR1_FIFO_enabled,Control register 1" bitfld.long 0x0 31. "RXFFIE,RXFIFO Full interrupt enable" "0,1" bitfld.long 0x0 30. "TXFEIE,TXFIFO empty interrupt enable" "0,1" newline bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0,1" bitfld.long 0x0 28. "M1,Word length" "0,1" newline bitfld.long 0x0 27. "EOBIE,End of Block interrupt enable" "0,1" bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0,1" newline hexmask.long.byte 0x0 21.--25. 1. "DEAT,DEAT" hexmask.long.byte 0x0 16.--20. 1. "DEDT,DEDT" newline bitfld.long 0x0 15. "OVER8,Oversampling mode" "0,1" bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0,1" newline bitfld.long 0x0 13. "MME,Mute mode enable" "0,1" bitfld.long 0x0 12. "M0,Word length" "0,1" newline bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0,1" bitfld.long 0x0 10. "PCE,Parity control enable" "0,1" newline bitfld.long 0x0 9. "PS,Parity selection" "0,1" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0,1" newline bitfld.long 0x0 7. "TXEIE,interrupt enable" "0,1" bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0,1" newline bitfld.long 0x0 5. "RXNEIE,RXNE interrupt enable" "0,1" bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0,1" newline bitfld.long 0x0 3. "TE,Transmitter enable" "0,1" bitfld.long 0x0 2. "RE,Receiver enable" "0,1" newline bitfld.long 0x0 1. "UESM,USART enable in Stop mode" "0,1" bitfld.long 0x0 0. "UE,USART enable" "0,1" group.long 0x0++0x3 line.long 0x0 "CR1_FIFO_disabled,Control register 1" bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0,1" bitfld.long 0x0 28. "M1,Word length" "0,1" newline bitfld.long 0x0 27. "EOBIE,End of Block interrupt enable" "0,1" bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0,1" newline hexmask.long.byte 0x0 21.--25. 1. "DEAT,DEAT" hexmask.long.byte 0x0 16.--20. 1. "DEDT,DEDT" newline bitfld.long 0x0 15. "OVER8,Oversampling mode" "0,1" bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0,1" newline bitfld.long 0x0 13. "MME,Mute mode enable" "0,1" bitfld.long 0x0 12. "M0,Word length" "0,1" newline bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0,1" bitfld.long 0x0 10. "PCE,Parity control enable" "0,1" newline bitfld.long 0x0 9. "PS,Parity selection" "0,1" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0,1" newline bitfld.long 0x0 7. "TXEIE,interrupt enable" "0,1" bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0,1" newline bitfld.long 0x0 5. "RXNEIE,RXNE interrupt enable" "0,1" bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0,1" newline bitfld.long 0x0 3. "TE,Transmitter enable" "0,1" bitfld.long 0x0 2. "RE,Receiver enable" "0,1" newline bitfld.long 0x0 1. "UESM,USART enable in Stop mode" "0,1" bitfld.long 0x0 0. "UE,USART enable" "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "ISR_FIFO_enabled,USART interrupt and status register" bitfld.long 0x0 27. "TXFT,TXFIFO threshold flag" "0,1" bitfld.long 0x0 26. "RXFT,RXFIFO threshold flag" "0,1" newline bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time flag" "0,1" bitfld.long 0x0 24. "RXFF,RXFIFO Full" "0,1" newline bitfld.long 0x0 23. "TXFE,TXFIFO Empty" "0,1" bitfld.long 0x0 22. "REACK,REACK" "0,1" newline bitfld.long 0x0 21. "TEACK,TEACK" "0,1" bitfld.long 0x0 20. "WUF,WUF" "0,1" newline bitfld.long 0x0 19. "RWU,RWU" "0,1" bitfld.long 0x0 18. "SBKF,SBKF" "0,1" newline bitfld.long 0x0 17. "CMF,CMF" "0,1" bitfld.long 0x0 16. "BUSY,BUSY" "0,1" newline bitfld.long 0x0 15. "ABRF,ABRF" "0,1" bitfld.long 0x0 14. "ABRE,ABRE" "0,1" newline bitfld.long 0x0 13. "UDR,SPI slave underrun error flag" "0,1" bitfld.long 0x0 12. "EOBF,EOBF" "0,1" newline bitfld.long 0x0 11. "RTOF,RTOF" "0,1" bitfld.long 0x0 10. "CTS,CTS" "0,1" newline bitfld.long 0x0 9. "CTSIF,CTSIF" "0,1" bitfld.long 0x0 8. "LBDF,LBDF" "0,1" newline bitfld.long 0x0 7. "TXE,TXE" "0,1" bitfld.long 0x0 6. "TC,TC" "0,1" newline bitfld.long 0x0 5. "RXNE,RXNE" "0,1" bitfld.long 0x0 4. "IDLE,IDLE" "0,1" newline bitfld.long 0x0 3. "ORE,ORE" "0,1" bitfld.long 0x0 2. "NF,NF" "0,1" newline bitfld.long 0x0 1. "FE,FE" "0,1" bitfld.long 0x0 0. "PE,PE" "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "ISR_FIFO_disabled,USART interrupt and status register" bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time flag" "0,1" bitfld.long 0x0 22. "REACK,REACK" "0,1" newline bitfld.long 0x0 21. "TEACK,TEACK" "0,1" bitfld.long 0x0 20. "WUF,WUF" "0,1" newline bitfld.long 0x0 19. "RWU,RWU" "0,1" bitfld.long 0x0 18. "SBKF,SBKF" "0,1" newline bitfld.long 0x0 17. "CMF,CMF" "0,1" bitfld.long 0x0 16. "BUSY,BUSY" "0,1" newline bitfld.long 0x0 15. "ABRF,ABRF" "0,1" bitfld.long 0x0 14. "ABRE,ABRE" "0,1" newline bitfld.long 0x0 13. "UDR,SPI slave underrun error flag" "0,1" bitfld.long 0x0 12. "EOBF,EOBF" "0,1" newline bitfld.long 0x0 11. "RTOF,RTOF" "0,1" bitfld.long 0x0 10. "CTS,CTS" "0,1" newline bitfld.long 0x0 9. "CTSIF,CTSIF" "0,1" bitfld.long 0x0 8. "LBDF,LBDF" "0,1" newline bitfld.long 0x0 7. "TXE,TXE" "0,1" bitfld.long 0x0 6. "TC,TC" "0,1" newline bitfld.long 0x0 5. "RXNE,RXNE" "0,1" bitfld.long 0x0 4. "IDLE,IDLE" "0,1" newline bitfld.long 0x0 3. "ORE,ORE" "0,1" bitfld.long 0x0 2. "NF,NF" "0,1" newline bitfld.long 0x0 1. "FE,FE" "0,1" bitfld.long 0x0 0. "PE,PE" "0,1" endif sif (cpuis("STM32MP151*")) group.long 0x0++0x3 line.long 0x0 "CR1,Control register 1" bitfld.long 0x0 31. "RXFFIE,RXFIFO Full interrupt enable" "0,1" bitfld.long 0x0 30. "TXFEIE,TXFIFO empty interrupt enable" "0,1" newline bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0,1" bitfld.long 0x0 28. "M1,Word length" "0,1" newline bitfld.long 0x0 27. "EOBIE,End of Block interrupt enable" "0,1" bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0,1" newline hexmask.long.byte 0x0 21.--25. 1. "DEAT,DEAT" hexmask.long.byte 0x0 16.--20. 1. "DEDT,DEDT" newline bitfld.long 0x0 15. "OVER8,Oversampling mode" "0,1" bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0,1" newline bitfld.long 0x0 13. "MME,Mute mode enable" "0,1" bitfld.long 0x0 12. "M0,Word length" "0,1" newline bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0,1" bitfld.long 0x0 10. "PCE,Parity control enable" "0,1" newline bitfld.long 0x0 9. "PS,Parity selection" "0,1" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0,1" newline bitfld.long 0x0 7. "TXEIE,interrupt enable" "0,1" bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0,1" newline bitfld.long 0x0 5. "RXNEIE,RXNE interrupt enable" "0,1" bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0,1" newline bitfld.long 0x0 3. "TE,Transmitter enable" "0,1" bitfld.long 0x0 2. "RE,Receiver enable" "0,1" newline bitfld.long 0x0 1. "UESM,USART enable in Stop mode" "0,1" bitfld.long 0x0 0. "UE,USART enable" "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "ISR,Interrupt & status register" bitfld.long 0x0 27. "TXFT,TXFIFO threshold flag" "0,1" bitfld.long 0x0 26. "RXFT,RXFIFO threshold flag" "0,1" newline bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time flag" "0,1" bitfld.long 0x0 24. "RXFF,RXFIFO Full" "0,1" newline bitfld.long 0x0 23. "TXFE,TXFIFO Empty" "0,1" bitfld.long 0x0 22. "REACK,REACK" "0,1" newline bitfld.long 0x0 21. "TEACK,TEACK" "0,1" bitfld.long 0x0 20. "WUF,WUF" "0,1" newline bitfld.long 0x0 19. "RWU,RWU" "0,1" bitfld.long 0x0 18. "SBKF,SBKF" "0,1" newline bitfld.long 0x0 17. "CMF,CMF" "0,1" bitfld.long 0x0 16. "BUSY,BUSY" "0,1" newline bitfld.long 0x0 15. "ABRF,ABRF" "0,1" bitfld.long 0x0 14. "ABRE,ABRE" "0,1" newline bitfld.long 0x0 13. "UDR,SPI slave underrun error flag" "0,1" bitfld.long 0x0 12. "EOBF,EOBF" "0,1" newline bitfld.long 0x0 11. "RTOF,RTOF" "0,1" bitfld.long 0x0 10. "CTS,CTS" "0,1" newline bitfld.long 0x0 9. "CTSIF,CTSIF" "0,1" bitfld.long 0x0 8. "LBDF,LBDF" "0,1" newline bitfld.long 0x0 7. "TXE,TXE" "0,1" bitfld.long 0x0 6. "TC,TC" "0,1" newline bitfld.long 0x0 5. "RXNE,RXNE" "0,1" bitfld.long 0x0 4. "IDLE,IDLE" "0,1" newline bitfld.long 0x0 3. "ORE,ORE" "0,1" bitfld.long 0x0 2. "NF,NF" "0,1" newline bitfld.long 0x0 1. "FE,FE" "0,1" bitfld.long 0x0 0. "PE,PE" "0,1" endif group.long 0x4++0x13 line.long 0x0 "CR2,Control register 2" hexmask.long.byte 0x0 28.--31. 1. "ADD4_7,Address of the USART node" hexmask.long.byte 0x0 24.--27. 1. "ADD0_3,Address of the USART node" bitfld.long 0x0 23. "RTOEN,Receiver timeout enable" "0,1" bitfld.long 0x0 21.--22. "ABRMOD,Auto baud rate mode" "0,1,2,3" bitfld.long 0x0 20. "ABREN,Auto baud rate enable" "0,1" bitfld.long 0x0 19. "MSBFIRST,Most significant bit first" "0,1" bitfld.long 0x0 18. "TAINV,Binary data inversion" "0,1" bitfld.long 0x0 17. "TXINV,TX pin active level inversion" "0,1" newline bitfld.long 0x0 16. "RXINV,RX pin active level inversion" "0,1" bitfld.long 0x0 15. "SWAP,Swap TX/RX pins" "0,1" bitfld.long 0x0 14. "LINEN,LIN mode enable" "0,1" bitfld.long 0x0 12.--13. "STOP,STOP bits" "0,1,2,3" bitfld.long 0x0 11. "CLKEN,Clock enable" "0,1" bitfld.long 0x0 10. "CPOL,Clock polarity" "0,1" bitfld.long 0x0 9. "CPHA,Clock phase" "0,1" bitfld.long 0x0 8. "LBCL,Last bit clock pulse" "0,1" newline bitfld.long 0x0 6. "LBDIE,LIN break detection interrupt enable" "0,1" bitfld.long 0x0 5. "LBDL,LIN break detection length" "0,1" bitfld.long 0x0 4. "ADDM7,7-bit Address Detection/4-bit Address Detection" "0,1" bitfld.long 0x0 3. "DIS_NSS,When the DSI_NSS bit is set the NSS pin input will be ignored" "0,1" bitfld.long 0x0 0. "SLVEN,Synchronous Slave mode enable" "0,1" line.long 0x4 "CR3,Control register 3" bitfld.long 0x4 29.--31. "TXFTCFG,TXFIFO threshold configuration" "0,1,2,3,4,5,6,7" bitfld.long 0x4 28. "RXFTIE,RXFIFO threshold interrupt enable" "0,1" bitfld.long 0x4 25.--27. "RXFTCFG,Receive FIFO threshold configuration" "0,1,2,3,4,5,6,7" bitfld.long 0x4 24. "TCBGTIE,Tr Complete before guard time interrupt enable" "0,1" bitfld.long 0x4 23. "TXFTIE,threshold interrupt enable" "0,1" bitfld.long 0x4 22. "WUFIE,Wakeup from Stop mode interrupt enable" "0,1" bitfld.long 0x4 20.--21. "WUS,Wakeup from Stop mode interrupt flag selection" "0,1,2,3" bitfld.long 0x4 17.--19. "SCARCNT,Smartcard auto-retry count" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 15. "DEP,Driver enable polarity selection" "0,1" bitfld.long 0x4 14. "DEM,Driver enable mode" "0,1" bitfld.long 0x4 13. "DDRE,DMA Disable on Reception Error" "0,1" bitfld.long 0x4 12. "OVRDIS,Overrun Disable" "0,1" bitfld.long 0x4 11. "ONEBIT,One sample bit method enable" "0,1" bitfld.long 0x4 10. "CTSIE,CTS interrupt enable" "0,1" bitfld.long 0x4 9. "CTSE,CTS enable" "0,1" bitfld.long 0x4 8. "RTSE,RTS enable" "0,1" newline bitfld.long 0x4 7. "DMAT,DMA enable transmitter" "0,1" bitfld.long 0x4 6. "DMAR,DMA enable receiver" "0,1" bitfld.long 0x4 5. "SCEN,Smartcard mode enable" "0,1" bitfld.long 0x4 4. "NACK,Smartcard NACK enable" "0,1" bitfld.long 0x4 3. "HDSEL,Half-duplex selection" "0,1" bitfld.long 0x4 2. "IRLP,Ir low-power" "0,1" bitfld.long 0x4 1. "IREN,Ir mode enable" "0,1" bitfld.long 0x4 0. "EIE,Error interrupt enable" "0,1" line.long 0x8 "BRR,Baud rate register" hexmask.long.word 0x8 4.--15. 1. "BRR_4_15,BRR_4_15" hexmask.long.byte 0x8 0.--3. 1. "BRR_0_3,BRR_0_3" line.long 0xC "GTPR,Guard time and prescaler register" hexmask.long.byte 0xC 8.--15. 1. "GT,Guard time value" hexmask.long.byte 0xC 0.--7. 1. "PSC,Prescaler value" line.long 0x10 "RTOR,Receiver timeout register" hexmask.long.byte 0x10 24.--31. 1. "BLEN,Block Length" hexmask.long.tbyte 0x10 0.--23. 1. "RTO,Receiver timeout value" wgroup.long 0x18++0x3 line.long 0x0 "RQR,Request register" bitfld.long 0x0 4. "TXFRQ,Transmit data flush request" "0,1" bitfld.long 0x0 3. "RXFRQ,Receive data flush request" "0,1" bitfld.long 0x0 2. "MMRQ,Mute mode request" "0,1" bitfld.long 0x0 1. "SBKRQ,Send break request" "0,1" bitfld.long 0x0 0. "ABRRQ,Auto baud rate request" "0,1" wgroup.long 0x20++0x3 line.long 0x0 "ICR,Interrupt flag clear register" bitfld.long 0x0 20. "WUCF,Wakeup from Stop mode clear flag" "0,1" bitfld.long 0x0 17. "CMCF,Character match clear flag" "0,1" bitfld.long 0x0 13. "UDRCF,SPI slave underrun clear flag" "0,1" bitfld.long 0x0 12. "EOBCF,End of block clear flag" "0,1" bitfld.long 0x0 11. "RTOCF,Receiver timeout clear flag" "0,1" bitfld.long 0x0 9. "CTSCF,CTS clear flag" "0,1" bitfld.long 0x0 8. "LBDCF,LIN break detection clear flag" "0,1" bitfld.long 0x0 7. "TCBGTCF,Transmission complete before Guard time clear flag" "0,1" newline bitfld.long 0x0 6. "TCCF,Transmission complete clear flag" "0,1" bitfld.long 0x0 5. "TXFECF,TXFIFO empty clear flag" "0,1" bitfld.long 0x0 4. "IDLECF,Idle line detected clear flag" "0,1" bitfld.long 0x0 3. "ORECF,Overrun error clear flag" "0,1" bitfld.long 0x0 2. "NCF,Noise detected clear flag" "0,1" bitfld.long 0x0 1. "FECF,Framing error clear flag" "0,1" bitfld.long 0x0 0. "PECF,Parity error clear flag" "0,1" rgroup.long 0x24++0x3 line.long 0x0 "RDR,Receive data register" hexmask.long.word 0x0 0.--8. 1. "RDR,Receive data value" group.long 0x28++0x7 line.long 0x0 "TDR,Transmit data register" hexmask.long.word 0x0 0.--8. 1. "TDR,Transmit data value" line.long 0x4 "PRESC,Prescaler register" hexmask.long.byte 0x4 0.--3. 1. "PRESCALER,Clock prescaler" rgroup.long 0x3EC++0x13 line.long 0x0 "HWCFGR2,USART Hardware Configuration register 2" hexmask.long.byte 0x0 4.--7. 1. "CFG2,CFG2" hexmask.long.byte 0x0 0.--3. 1. "CFG1,CFG1" line.long 0x4 "HWCFGR1,USART Hardware Configuration register 1" hexmask.long.byte 0x4 28.--31. 1. "CFG8,CFG8" hexmask.long.byte 0x4 24.--27. 1. "CFG7,CFG7" hexmask.long.byte 0x4 20.--23. 1. "CFG6,CFG6" hexmask.long.byte 0x4 16.--19. 1. "CFG5,CFG5" hexmask.long.byte 0x4 12.--15. 1. "CFG4,CFG4" hexmask.long.byte 0x4 8.--11. 1. "CFG3,CFG3" hexmask.long.byte 0x4 4.--7. 1. "CFG2,CFG2" hexmask.long.byte 0x4 0.--3. 1. "CFG1,CFG1" line.long 0x8 "VERR,EXTI IP Version register" hexmask.long.byte 0x8 4.--7. 1. "MAJREV,Major Revision number" hexmask.long.byte 0x8 0.--3. 1. "MINREV,Minor Revision number" line.long 0xC "IPIDR,EXTI Identification register" hexmask.long 0xC 0.--31. 1. "IPID,IP Identification" line.long 0x10 "SIDR,EXTI Size ID register" hexmask.long 0x10 0.--31. 1. "SID,Size Identification" tree.end endif sif (cpuis("STM32MP13*")) base ad:0x4C001000 elif (cpuis("STM32MP151*")) base ad:0x4000E000 endif sif (cpuis("STM32MP13*")||cpuis("STM32MP151*")) tree "USART2" sif (cpuis("STM32MP13*")) group.long 0x0++0x3 line.long 0x0 "CR1_FIFO_enabled,Control register 1" bitfld.long 0x0 31. "RXFFIE,RXFIFO Full interrupt enable" "0,1" bitfld.long 0x0 30. "TXFEIE,TXFIFO empty interrupt enable" "0,1" newline bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0,1" bitfld.long 0x0 28. "M1,Word length" "0,1" newline bitfld.long 0x0 27. "EOBIE,End of Block interrupt enable" "0,1" bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0,1" newline hexmask.long.byte 0x0 21.--25. 1. "DEAT,DEAT" hexmask.long.byte 0x0 16.--20. 1. "DEDT,DEDT" newline bitfld.long 0x0 15. "OVER8,Oversampling mode" "0,1" bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0,1" newline bitfld.long 0x0 13. "MME,Mute mode enable" "0,1" bitfld.long 0x0 12. "M0,Word length" "0,1" newline bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0,1" bitfld.long 0x0 10. "PCE,Parity control enable" "0,1" newline bitfld.long 0x0 9. "PS,Parity selection" "0,1" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0,1" newline bitfld.long 0x0 7. "TXEIE,interrupt enable" "0,1" bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0,1" newline bitfld.long 0x0 5. "RXNEIE,RXNE interrupt enable" "0,1" bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0,1" newline bitfld.long 0x0 3. "TE,Transmitter enable" "0,1" bitfld.long 0x0 2. "RE,Receiver enable" "0,1" newline bitfld.long 0x0 1. "UESM,USART enable in Stop mode" "0,1" bitfld.long 0x0 0. "UE,USART enable" "0,1" group.long 0x0++0x3 line.long 0x0 "CR1_FIFO_disabled,Control register 1" bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0,1" bitfld.long 0x0 28. "M1,Word length" "0,1" newline bitfld.long 0x0 27. "EOBIE,End of Block interrupt enable" "0,1" bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0,1" newline hexmask.long.byte 0x0 21.--25. 1. "DEAT,DEAT" hexmask.long.byte 0x0 16.--20. 1. "DEDT,DEDT" newline bitfld.long 0x0 15. "OVER8,Oversampling mode" "0,1" bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0,1" newline bitfld.long 0x0 13. "MME,Mute mode enable" "0,1" bitfld.long 0x0 12. "M0,Word length" "0,1" newline bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0,1" bitfld.long 0x0 10. "PCE,Parity control enable" "0,1" newline bitfld.long 0x0 9. "PS,Parity selection" "0,1" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0,1" newline bitfld.long 0x0 7. "TXEIE,interrupt enable" "0,1" bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0,1" newline bitfld.long 0x0 5. "RXNEIE,RXNE interrupt enable" "0,1" bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0,1" newline bitfld.long 0x0 3. "TE,Transmitter enable" "0,1" bitfld.long 0x0 2. "RE,Receiver enable" "0,1" newline bitfld.long 0x0 1. "UESM,USART enable in Stop mode" "0,1" bitfld.long 0x0 0. "UE,USART enable" "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "ISR_FIFO_enabled,USART interrupt and status register" bitfld.long 0x0 27. "TXFT,TXFIFO threshold flag" "0,1" bitfld.long 0x0 26. "RXFT,RXFIFO threshold flag" "0,1" newline bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time flag" "0,1" bitfld.long 0x0 24. "RXFF,RXFIFO Full" "0,1" newline bitfld.long 0x0 23. "TXFE,TXFIFO Empty" "0,1" bitfld.long 0x0 22. "REACK,REACK" "0,1" newline bitfld.long 0x0 21. "TEACK,TEACK" "0,1" bitfld.long 0x0 20. "WUF,WUF" "0,1" newline bitfld.long 0x0 19. "RWU,RWU" "0,1" bitfld.long 0x0 18. "SBKF,SBKF" "0,1" newline bitfld.long 0x0 17. "CMF,CMF" "0,1" bitfld.long 0x0 16. "BUSY,BUSY" "0,1" newline bitfld.long 0x0 15. "ABRF,ABRF" "0,1" bitfld.long 0x0 14. "ABRE,ABRE" "0,1" newline bitfld.long 0x0 13. "UDR,SPI slave underrun error flag" "0,1" bitfld.long 0x0 12. "EOBF,EOBF" "0,1" newline bitfld.long 0x0 11. "RTOF,RTOF" "0,1" bitfld.long 0x0 10. "CTS,CTS" "0,1" newline bitfld.long 0x0 9. "CTSIF,CTSIF" "0,1" bitfld.long 0x0 8. "LBDF,LBDF" "0,1" newline bitfld.long 0x0 7. "TXE,TXE" "0,1" bitfld.long 0x0 6. "TC,TC" "0,1" newline bitfld.long 0x0 5. "RXNE,RXNE" "0,1" bitfld.long 0x0 4. "IDLE,IDLE" "0,1" newline bitfld.long 0x0 3. "ORE,ORE" "0,1" bitfld.long 0x0 2. "NF,NF" "0,1" newline bitfld.long 0x0 1. "FE,FE" "0,1" bitfld.long 0x0 0. "PE,PE" "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "ISR_FIFO_disabled,USART interrupt and status register" bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time flag" "0,1" bitfld.long 0x0 22. "REACK,REACK" "0,1" newline bitfld.long 0x0 21. "TEACK,TEACK" "0,1" bitfld.long 0x0 20. "WUF,WUF" "0,1" newline bitfld.long 0x0 19. "RWU,RWU" "0,1" bitfld.long 0x0 18. "SBKF,SBKF" "0,1" newline bitfld.long 0x0 17. "CMF,CMF" "0,1" bitfld.long 0x0 16. "BUSY,BUSY" "0,1" newline bitfld.long 0x0 15. "ABRF,ABRF" "0,1" bitfld.long 0x0 14. "ABRE,ABRE" "0,1" newline bitfld.long 0x0 13. "UDR,SPI slave underrun error flag" "0,1" bitfld.long 0x0 12. "EOBF,EOBF" "0,1" newline bitfld.long 0x0 11. "RTOF,RTOF" "0,1" bitfld.long 0x0 10. "CTS,CTS" "0,1" newline bitfld.long 0x0 9. "CTSIF,CTSIF" "0,1" bitfld.long 0x0 8. "LBDF,LBDF" "0,1" newline bitfld.long 0x0 7. "TXE,TXE" "0,1" bitfld.long 0x0 6. "TC,TC" "0,1" newline bitfld.long 0x0 5. "RXNE,RXNE" "0,1" bitfld.long 0x0 4. "IDLE,IDLE" "0,1" newline bitfld.long 0x0 3. "ORE,ORE" "0,1" bitfld.long 0x0 2. "NF,NF" "0,1" newline bitfld.long 0x0 1. "FE,FE" "0,1" bitfld.long 0x0 0. "PE,PE" "0,1" endif sif (cpuis("STM32MP151*")) group.long 0x0++0x3 line.long 0x0 "CR1,Control register 1" bitfld.long 0x0 31. "RXFFIE,RXFIFO Full interrupt enable" "0,1" bitfld.long 0x0 30. "TXFEIE,TXFIFO empty interrupt enable" "0,1" newline bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0,1" bitfld.long 0x0 28. "M1,Word length" "0,1" newline bitfld.long 0x0 27. "EOBIE,End of Block interrupt enable" "0,1" bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0,1" newline hexmask.long.byte 0x0 21.--25. 1. "DEAT,DEAT" hexmask.long.byte 0x0 16.--20. 1. "DEDT,DEDT" newline bitfld.long 0x0 15. "OVER8,Oversampling mode" "0,1" bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0,1" newline bitfld.long 0x0 13. "MME,Mute mode enable" "0,1" bitfld.long 0x0 12. "M0,Word length" "0,1" newline bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0,1" bitfld.long 0x0 10. "PCE,Parity control enable" "0,1" newline bitfld.long 0x0 9. "PS,Parity selection" "0,1" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0,1" newline bitfld.long 0x0 7. "TXEIE,interrupt enable" "0,1" bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0,1" newline bitfld.long 0x0 5. "RXNEIE,RXNE interrupt enable" "0,1" bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0,1" newline bitfld.long 0x0 3. "TE,Transmitter enable" "0,1" bitfld.long 0x0 2. "RE,Receiver enable" "0,1" newline bitfld.long 0x0 1. "UESM,USART enable in Stop mode" "0,1" bitfld.long 0x0 0. "UE,USART enable" "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "ISR,Interrupt & status register" bitfld.long 0x0 27. "TXFT,TXFIFO threshold flag" "0,1" bitfld.long 0x0 26. "RXFT,RXFIFO threshold flag" "0,1" newline bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time flag" "0,1" bitfld.long 0x0 24. "RXFF,RXFIFO Full" "0,1" newline bitfld.long 0x0 23. "TXFE,TXFIFO Empty" "0,1" bitfld.long 0x0 22. "REACK,REACK" "0,1" newline bitfld.long 0x0 21. "TEACK,TEACK" "0,1" bitfld.long 0x0 20. "WUF,WUF" "0,1" newline bitfld.long 0x0 19. "RWU,RWU" "0,1" bitfld.long 0x0 18. "SBKF,SBKF" "0,1" newline bitfld.long 0x0 17. "CMF,CMF" "0,1" bitfld.long 0x0 16. "BUSY,BUSY" "0,1" newline bitfld.long 0x0 15. "ABRF,ABRF" "0,1" bitfld.long 0x0 14. "ABRE,ABRE" "0,1" newline bitfld.long 0x0 13. "UDR,SPI slave underrun error flag" "0,1" bitfld.long 0x0 12. "EOBF,EOBF" "0,1" newline bitfld.long 0x0 11. "RTOF,RTOF" "0,1" bitfld.long 0x0 10. "CTS,CTS" "0,1" newline bitfld.long 0x0 9. "CTSIF,CTSIF" "0,1" bitfld.long 0x0 8. "LBDF,LBDF" "0,1" newline bitfld.long 0x0 7. "TXE,TXE" "0,1" bitfld.long 0x0 6. "TC,TC" "0,1" newline bitfld.long 0x0 5. "RXNE,RXNE" "0,1" bitfld.long 0x0 4. "IDLE,IDLE" "0,1" newline bitfld.long 0x0 3. "ORE,ORE" "0,1" bitfld.long 0x0 2. "NF,NF" "0,1" newline bitfld.long 0x0 1. "FE,FE" "0,1" bitfld.long 0x0 0. "PE,PE" "0,1" endif group.long 0x4++0x13 line.long 0x0 "CR2,Control register 2" hexmask.long.byte 0x0 28.--31. 1. "ADD4_7,Address of the USART node" hexmask.long.byte 0x0 24.--27. 1. "ADD0_3,Address of the USART node" bitfld.long 0x0 23. "RTOEN,Receiver timeout enable" "0,1" bitfld.long 0x0 21.--22. "ABRMOD,Auto baud rate mode" "0,1,2,3" bitfld.long 0x0 20. "ABREN,Auto baud rate enable" "0,1" bitfld.long 0x0 19. "MSBFIRST,Most significant bit first" "0,1" bitfld.long 0x0 18. "TAINV,Binary data inversion" "0,1" bitfld.long 0x0 17. "TXINV,TX pin active level inversion" "0,1" newline bitfld.long 0x0 16. "RXINV,RX pin active level inversion" "0,1" bitfld.long 0x0 15. "SWAP,Swap TX/RX pins" "0,1" bitfld.long 0x0 14. "LINEN,LIN mode enable" "0,1" bitfld.long 0x0 12.--13. "STOP,STOP bits" "0,1,2,3" bitfld.long 0x0 11. "CLKEN,Clock enable" "0,1" bitfld.long 0x0 10. "CPOL,Clock polarity" "0,1" bitfld.long 0x0 9. "CPHA,Clock phase" "0,1" bitfld.long 0x0 8. "LBCL,Last bit clock pulse" "0,1" newline bitfld.long 0x0 6. "LBDIE,LIN break detection interrupt enable" "0,1" bitfld.long 0x0 5. "LBDL,LIN break detection length" "0,1" bitfld.long 0x0 4. "ADDM7,7-bit Address Detection/4-bit Address Detection" "0,1" bitfld.long 0x0 3. "DIS_NSS,When the DSI_NSS bit is set the NSS pin input will be ignored" "0,1" bitfld.long 0x0 0. "SLVEN,Synchronous Slave mode enable" "0,1" line.long 0x4 "CR3,Control register 3" bitfld.long 0x4 29.--31. "TXFTCFG,TXFIFO threshold configuration" "0,1,2,3,4,5,6,7" bitfld.long 0x4 28. "RXFTIE,RXFIFO threshold interrupt enable" "0,1" bitfld.long 0x4 25.--27. "RXFTCFG,Receive FIFO threshold configuration" "0,1,2,3,4,5,6,7" bitfld.long 0x4 24. "TCBGTIE,Tr Complete before guard time interrupt enable" "0,1" bitfld.long 0x4 23. "TXFTIE,threshold interrupt enable" "0,1" bitfld.long 0x4 22. "WUFIE,Wakeup from Stop mode interrupt enable" "0,1" bitfld.long 0x4 20.--21. "WUS,Wakeup from Stop mode interrupt flag selection" "0,1,2,3" bitfld.long 0x4 17.--19. "SCARCNT,Smartcard auto-retry count" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 15. "DEP,Driver enable polarity selection" "0,1" bitfld.long 0x4 14. "DEM,Driver enable mode" "0,1" bitfld.long 0x4 13. "DDRE,DMA Disable on Reception Error" "0,1" bitfld.long 0x4 12. "OVRDIS,Overrun Disable" "0,1" bitfld.long 0x4 11. "ONEBIT,One sample bit method enable" "0,1" bitfld.long 0x4 10. "CTSIE,CTS interrupt enable" "0,1" bitfld.long 0x4 9. "CTSE,CTS enable" "0,1" bitfld.long 0x4 8. "RTSE,RTS enable" "0,1" newline bitfld.long 0x4 7. "DMAT,DMA enable transmitter" "0,1" bitfld.long 0x4 6. "DMAR,DMA enable receiver" "0,1" bitfld.long 0x4 5. "SCEN,Smartcard mode enable" "0,1" bitfld.long 0x4 4. "NACK,Smartcard NACK enable" "0,1" bitfld.long 0x4 3. "HDSEL,Half-duplex selection" "0,1" bitfld.long 0x4 2. "IRLP,Ir low-power" "0,1" bitfld.long 0x4 1. "IREN,Ir mode enable" "0,1" bitfld.long 0x4 0. "EIE,Error interrupt enable" "0,1" line.long 0x8 "BRR,Baud rate register" hexmask.long.word 0x8 4.--15. 1. "BRR_4_15,BRR_4_15" hexmask.long.byte 0x8 0.--3. 1. "BRR_0_3,BRR_0_3" line.long 0xC "GTPR,Guard time and prescaler register" hexmask.long.byte 0xC 8.--15. 1. "GT,Guard time value" hexmask.long.byte 0xC 0.--7. 1. "PSC,Prescaler value" line.long 0x10 "RTOR,Receiver timeout register" hexmask.long.byte 0x10 24.--31. 1. "BLEN,Block Length" hexmask.long.tbyte 0x10 0.--23. 1. "RTO,Receiver timeout value" wgroup.long 0x18++0x3 line.long 0x0 "RQR,Request register" bitfld.long 0x0 4. "TXFRQ,Transmit data flush request" "0,1" bitfld.long 0x0 3. "RXFRQ,Receive data flush request" "0,1" bitfld.long 0x0 2. "MMRQ,Mute mode request" "0,1" bitfld.long 0x0 1. "SBKRQ,Send break request" "0,1" bitfld.long 0x0 0. "ABRRQ,Auto baud rate request" "0,1" wgroup.long 0x20++0x3 line.long 0x0 "ICR,Interrupt flag clear register" bitfld.long 0x0 20. "WUCF,Wakeup from Stop mode clear flag" "0,1" bitfld.long 0x0 17. "CMCF,Character match clear flag" "0,1" bitfld.long 0x0 13. "UDRCF,SPI slave underrun clear flag" "0,1" bitfld.long 0x0 12. "EOBCF,End of block clear flag" "0,1" bitfld.long 0x0 11. "RTOCF,Receiver timeout clear flag" "0,1" bitfld.long 0x0 9. "CTSCF,CTS clear flag" "0,1" bitfld.long 0x0 8. "LBDCF,LIN break detection clear flag" "0,1" bitfld.long 0x0 7. "TCBGTCF,Transmission complete before Guard time clear flag" "0,1" newline bitfld.long 0x0 6. "TCCF,Transmission complete clear flag" "0,1" bitfld.long 0x0 5. "TXFECF,TXFIFO empty clear flag" "0,1" bitfld.long 0x0 4. "IDLECF,Idle line detected clear flag" "0,1" bitfld.long 0x0 3. "ORECF,Overrun error clear flag" "0,1" bitfld.long 0x0 2. "NCF,Noise detected clear flag" "0,1" bitfld.long 0x0 1. "FECF,Framing error clear flag" "0,1" bitfld.long 0x0 0. "PECF,Parity error clear flag" "0,1" rgroup.long 0x24++0x3 line.long 0x0 "RDR,Receive data register" hexmask.long.word 0x0 0.--8. 1. "RDR,Receive data value" group.long 0x28++0x7 line.long 0x0 "TDR,Transmit data register" hexmask.long.word 0x0 0.--8. 1. "TDR,Transmit data value" line.long 0x4 "PRESC,Prescaler register" hexmask.long.byte 0x4 0.--3. 1. "PRESCALER,Clock prescaler" rgroup.long 0x3EC++0x13 line.long 0x0 "HWCFGR2,USART Hardware Configuration register 2" hexmask.long.byte 0x0 4.--7. 1. "CFG2,CFG2" hexmask.long.byte 0x0 0.--3. 1. "CFG1,CFG1" line.long 0x4 "HWCFGR1,USART Hardware Configuration register 1" hexmask.long.byte 0x4 28.--31. 1. "CFG8,CFG8" hexmask.long.byte 0x4 24.--27. 1. "CFG7,CFG7" hexmask.long.byte 0x4 20.--23. 1. "CFG6,CFG6" hexmask.long.byte 0x4 16.--19. 1. "CFG5,CFG5" hexmask.long.byte 0x4 12.--15. 1. "CFG4,CFG4" hexmask.long.byte 0x4 8.--11. 1. "CFG3,CFG3" hexmask.long.byte 0x4 4.--7. 1. "CFG2,CFG2" hexmask.long.byte 0x4 0.--3. 1. "CFG1,CFG1" line.long 0x8 "VERR,EXTI IP Version register" hexmask.long.byte 0x8 4.--7. 1. "MAJREV,Major Revision number" hexmask.long.byte 0x8 0.--3. 1. "MINREV,Minor Revision number" line.long 0xC "IPIDR,EXTI Identification register" hexmask.long 0xC 0.--31. 1. "IPID,IP Identification" line.long 0x10 "SIDR,EXTI Size ID register" hexmask.long 0x10 0.--31. 1. "SID,Size Identification" tree.end endif sif (cpuis("STM32MP13*")||cpuis("STM32MP151*")) tree "USART3" base ad:0x4000F000 sif (cpuis("STM32MP13*")) group.long 0x0++0x3 line.long 0x0 "CR1_FIFO_enabled,Control register 1" bitfld.long 0x0 31. "RXFFIE,RXFIFO Full interrupt enable" "0,1" bitfld.long 0x0 30. "TXFEIE,TXFIFO empty interrupt enable" "0,1" newline bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0,1" bitfld.long 0x0 28. "M1,Word length" "0,1" newline bitfld.long 0x0 27. "EOBIE,End of Block interrupt enable" "0,1" bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0,1" newline hexmask.long.byte 0x0 21.--25. 1. "DEAT,DEAT" hexmask.long.byte 0x0 16.--20. 1. "DEDT,DEDT" newline bitfld.long 0x0 15. "OVER8,Oversampling mode" "0,1" bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0,1" newline bitfld.long 0x0 13. "MME,Mute mode enable" "0,1" bitfld.long 0x0 12. "M0,Word length" "0,1" newline bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0,1" bitfld.long 0x0 10. "PCE,Parity control enable" "0,1" newline bitfld.long 0x0 9. "PS,Parity selection" "0,1" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0,1" newline bitfld.long 0x0 7. "TXEIE,interrupt enable" "0,1" bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0,1" newline bitfld.long 0x0 5. "RXNEIE,RXNE interrupt enable" "0,1" bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0,1" newline bitfld.long 0x0 3. "TE,Transmitter enable" "0,1" bitfld.long 0x0 2. "RE,Receiver enable" "0,1" newline bitfld.long 0x0 1. "UESM,USART enable in Stop mode" "0,1" bitfld.long 0x0 0. "UE,USART enable" "0,1" group.long 0x0++0x3 line.long 0x0 "CR1_FIFO_disabled,Control register 1" bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0,1" bitfld.long 0x0 28. "M1,Word length" "0,1" newline bitfld.long 0x0 27. "EOBIE,End of Block interrupt enable" "0,1" bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0,1" newline hexmask.long.byte 0x0 21.--25. 1. "DEAT,DEAT" hexmask.long.byte 0x0 16.--20. 1. "DEDT,DEDT" newline bitfld.long 0x0 15. "OVER8,Oversampling mode" "0,1" bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0,1" newline bitfld.long 0x0 13. "MME,Mute mode enable" "0,1" bitfld.long 0x0 12. "M0,Word length" "0,1" newline bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0,1" bitfld.long 0x0 10. "PCE,Parity control enable" "0,1" newline bitfld.long 0x0 9. "PS,Parity selection" "0,1" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0,1" newline bitfld.long 0x0 7. "TXEIE,interrupt enable" "0,1" bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0,1" newline bitfld.long 0x0 5. "RXNEIE,RXNE interrupt enable" "0,1" bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0,1" newline bitfld.long 0x0 3. "TE,Transmitter enable" "0,1" bitfld.long 0x0 2. "RE,Receiver enable" "0,1" newline bitfld.long 0x0 1. "UESM,USART enable in Stop mode" "0,1" bitfld.long 0x0 0. "UE,USART enable" "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "ISR_FIFO_enabled,USART interrupt and status register" bitfld.long 0x0 27. "TXFT,TXFIFO threshold flag" "0,1" bitfld.long 0x0 26. "RXFT,RXFIFO threshold flag" "0,1" newline bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time flag" "0,1" bitfld.long 0x0 24. "RXFF,RXFIFO Full" "0,1" newline bitfld.long 0x0 23. "TXFE,TXFIFO Empty" "0,1" bitfld.long 0x0 22. "REACK,REACK" "0,1" newline bitfld.long 0x0 21. "TEACK,TEACK" "0,1" bitfld.long 0x0 20. "WUF,WUF" "0,1" newline bitfld.long 0x0 19. "RWU,RWU" "0,1" bitfld.long 0x0 18. "SBKF,SBKF" "0,1" newline bitfld.long 0x0 17. "CMF,CMF" "0,1" bitfld.long 0x0 16. "BUSY,BUSY" "0,1" newline bitfld.long 0x0 15. "ABRF,ABRF" "0,1" bitfld.long 0x0 14. "ABRE,ABRE" "0,1" newline bitfld.long 0x0 13. "UDR,SPI slave underrun error flag" "0,1" bitfld.long 0x0 12. "EOBF,EOBF" "0,1" newline bitfld.long 0x0 11. "RTOF,RTOF" "0,1" bitfld.long 0x0 10. "CTS,CTS" "0,1" newline bitfld.long 0x0 9. "CTSIF,CTSIF" "0,1" bitfld.long 0x0 8. "LBDF,LBDF" "0,1" newline bitfld.long 0x0 7. "TXE,TXE" "0,1" bitfld.long 0x0 6. "TC,TC" "0,1" newline bitfld.long 0x0 5. "RXNE,RXNE" "0,1" bitfld.long 0x0 4. "IDLE,IDLE" "0,1" newline bitfld.long 0x0 3. "ORE,ORE" "0,1" bitfld.long 0x0 2. "NF,NF" "0,1" newline bitfld.long 0x0 1. "FE,FE" "0,1" bitfld.long 0x0 0. "PE,PE" "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "ISR_FIFO_disabled,USART interrupt and status register" bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time flag" "0,1" bitfld.long 0x0 22. "REACK,REACK" "0,1" newline bitfld.long 0x0 21. "TEACK,TEACK" "0,1" bitfld.long 0x0 20. "WUF,WUF" "0,1" newline bitfld.long 0x0 19. "RWU,RWU" "0,1" bitfld.long 0x0 18. "SBKF,SBKF" "0,1" newline bitfld.long 0x0 17. "CMF,CMF" "0,1" bitfld.long 0x0 16. "BUSY,BUSY" "0,1" newline bitfld.long 0x0 15. "ABRF,ABRF" "0,1" bitfld.long 0x0 14. "ABRE,ABRE" "0,1" newline bitfld.long 0x0 13. "UDR,SPI slave underrun error flag" "0,1" bitfld.long 0x0 12. "EOBF,EOBF" "0,1" newline bitfld.long 0x0 11. "RTOF,RTOF" "0,1" bitfld.long 0x0 10. "CTS,CTS" "0,1" newline bitfld.long 0x0 9. "CTSIF,CTSIF" "0,1" bitfld.long 0x0 8. "LBDF,LBDF" "0,1" newline bitfld.long 0x0 7. "TXE,TXE" "0,1" bitfld.long 0x0 6. "TC,TC" "0,1" newline bitfld.long 0x0 5. "RXNE,RXNE" "0,1" bitfld.long 0x0 4. "IDLE,IDLE" "0,1" newline bitfld.long 0x0 3. "ORE,ORE" "0,1" bitfld.long 0x0 2. "NF,NF" "0,1" newline bitfld.long 0x0 1. "FE,FE" "0,1" bitfld.long 0x0 0. "PE,PE" "0,1" endif sif (cpuis("STM32MP151*")) group.long 0x0++0x3 line.long 0x0 "CR1,Control register 1" bitfld.long 0x0 31. "RXFFIE,RXFIFO Full interrupt enable" "0,1" bitfld.long 0x0 30. "TXFEIE,TXFIFO empty interrupt enable" "0,1" newline bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0,1" bitfld.long 0x0 28. "M1,Word length" "0,1" newline bitfld.long 0x0 27. "EOBIE,End of Block interrupt enable" "0,1" bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0,1" newline hexmask.long.byte 0x0 21.--25. 1. "DEAT,DEAT" hexmask.long.byte 0x0 16.--20. 1. "DEDT,DEDT" newline bitfld.long 0x0 15. "OVER8,Oversampling mode" "0,1" bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0,1" newline bitfld.long 0x0 13. "MME,Mute mode enable" "0,1" bitfld.long 0x0 12. "M0,Word length" "0,1" newline bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0,1" bitfld.long 0x0 10. "PCE,Parity control enable" "0,1" newline bitfld.long 0x0 9. "PS,Parity selection" "0,1" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0,1" newline bitfld.long 0x0 7. "TXEIE,interrupt enable" "0,1" bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0,1" newline bitfld.long 0x0 5. "RXNEIE,RXNE interrupt enable" "0,1" bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0,1" newline bitfld.long 0x0 3. "TE,Transmitter enable" "0,1" bitfld.long 0x0 2. "RE,Receiver enable" "0,1" newline bitfld.long 0x0 1. "UESM,USART enable in Stop mode" "0,1" bitfld.long 0x0 0. "UE,USART enable" "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "ISR,Interrupt & status register" bitfld.long 0x0 27. "TXFT,TXFIFO threshold flag" "0,1" bitfld.long 0x0 26. "RXFT,RXFIFO threshold flag" "0,1" newline bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time flag" "0,1" bitfld.long 0x0 24. "RXFF,RXFIFO Full" "0,1" newline bitfld.long 0x0 23. "TXFE,TXFIFO Empty" "0,1" bitfld.long 0x0 22. "REACK,REACK" "0,1" newline bitfld.long 0x0 21. "TEACK,TEACK" "0,1" bitfld.long 0x0 20. "WUF,WUF" "0,1" newline bitfld.long 0x0 19. "RWU,RWU" "0,1" bitfld.long 0x0 18. "SBKF,SBKF" "0,1" newline bitfld.long 0x0 17. "CMF,CMF" "0,1" bitfld.long 0x0 16. "BUSY,BUSY" "0,1" newline bitfld.long 0x0 15. "ABRF,ABRF" "0,1" bitfld.long 0x0 14. "ABRE,ABRE" "0,1" newline bitfld.long 0x0 13. "UDR,SPI slave underrun error flag" "0,1" bitfld.long 0x0 12. "EOBF,EOBF" "0,1" newline bitfld.long 0x0 11. "RTOF,RTOF" "0,1" bitfld.long 0x0 10. "CTS,CTS" "0,1" newline bitfld.long 0x0 9. "CTSIF,CTSIF" "0,1" bitfld.long 0x0 8. "LBDF,LBDF" "0,1" newline bitfld.long 0x0 7. "TXE,TXE" "0,1" bitfld.long 0x0 6. "TC,TC" "0,1" newline bitfld.long 0x0 5. "RXNE,RXNE" "0,1" bitfld.long 0x0 4. "IDLE,IDLE" "0,1" newline bitfld.long 0x0 3. "ORE,ORE" "0,1" bitfld.long 0x0 2. "NF,NF" "0,1" newline bitfld.long 0x0 1. "FE,FE" "0,1" bitfld.long 0x0 0. "PE,PE" "0,1" endif group.long 0x4++0x13 line.long 0x0 "CR2,Control register 2" hexmask.long.byte 0x0 28.--31. 1. "ADD4_7,Address of the USART node" hexmask.long.byte 0x0 24.--27. 1. "ADD0_3,Address of the USART node" bitfld.long 0x0 23. "RTOEN,Receiver timeout enable" "0,1" bitfld.long 0x0 21.--22. "ABRMOD,Auto baud rate mode" "0,1,2,3" bitfld.long 0x0 20. "ABREN,Auto baud rate enable" "0,1" bitfld.long 0x0 19. "MSBFIRST,Most significant bit first" "0,1" bitfld.long 0x0 18. "TAINV,Binary data inversion" "0,1" bitfld.long 0x0 17. "TXINV,TX pin active level inversion" "0,1" newline bitfld.long 0x0 16. "RXINV,RX pin active level inversion" "0,1" bitfld.long 0x0 15. "SWAP,Swap TX/RX pins" "0,1" bitfld.long 0x0 14. "LINEN,LIN mode enable" "0,1" bitfld.long 0x0 12.--13. "STOP,STOP bits" "0,1,2,3" bitfld.long 0x0 11. "CLKEN,Clock enable" "0,1" bitfld.long 0x0 10. "CPOL,Clock polarity" "0,1" bitfld.long 0x0 9. "CPHA,Clock phase" "0,1" bitfld.long 0x0 8. "LBCL,Last bit clock pulse" "0,1" newline bitfld.long 0x0 6. "LBDIE,LIN break detection interrupt enable" "0,1" bitfld.long 0x0 5. "LBDL,LIN break detection length" "0,1" bitfld.long 0x0 4. "ADDM7,7-bit Address Detection/4-bit Address Detection" "0,1" bitfld.long 0x0 3. "DIS_NSS,When the DSI_NSS bit is set the NSS pin input will be ignored" "0,1" bitfld.long 0x0 0. "SLVEN,Synchronous Slave mode enable" "0,1" line.long 0x4 "CR3,Control register 3" bitfld.long 0x4 29.--31. "TXFTCFG,TXFIFO threshold configuration" "0,1,2,3,4,5,6,7" bitfld.long 0x4 28. "RXFTIE,RXFIFO threshold interrupt enable" "0,1" bitfld.long 0x4 25.--27. "RXFTCFG,Receive FIFO threshold configuration" "0,1,2,3,4,5,6,7" bitfld.long 0x4 24. "TCBGTIE,Tr Complete before guard time interrupt enable" "0,1" bitfld.long 0x4 23. "TXFTIE,threshold interrupt enable" "0,1" bitfld.long 0x4 22. "WUFIE,Wakeup from Stop mode interrupt enable" "0,1" bitfld.long 0x4 20.--21. "WUS,Wakeup from Stop mode interrupt flag selection" "0,1,2,3" bitfld.long 0x4 17.--19. "SCARCNT,Smartcard auto-retry count" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 15. "DEP,Driver enable polarity selection" "0,1" bitfld.long 0x4 14. "DEM,Driver enable mode" "0,1" bitfld.long 0x4 13. "DDRE,DMA Disable on Reception Error" "0,1" bitfld.long 0x4 12. "OVRDIS,Overrun Disable" "0,1" bitfld.long 0x4 11. "ONEBIT,One sample bit method enable" "0,1" bitfld.long 0x4 10. "CTSIE,CTS interrupt enable" "0,1" bitfld.long 0x4 9. "CTSE,CTS enable" "0,1" bitfld.long 0x4 8. "RTSE,RTS enable" "0,1" newline bitfld.long 0x4 7. "DMAT,DMA enable transmitter" "0,1" bitfld.long 0x4 6. "DMAR,DMA enable receiver" "0,1" bitfld.long 0x4 5. "SCEN,Smartcard mode enable" "0,1" bitfld.long 0x4 4. "NACK,Smartcard NACK enable" "0,1" bitfld.long 0x4 3. "HDSEL,Half-duplex selection" "0,1" bitfld.long 0x4 2. "IRLP,Ir low-power" "0,1" bitfld.long 0x4 1. "IREN,Ir mode enable" "0,1" bitfld.long 0x4 0. "EIE,Error interrupt enable" "0,1" line.long 0x8 "BRR,Baud rate register" hexmask.long.word 0x8 4.--15. 1. "BRR_4_15,BRR_4_15" hexmask.long.byte 0x8 0.--3. 1. "BRR_0_3,BRR_0_3" line.long 0xC "GTPR,Guard time and prescaler register" hexmask.long.byte 0xC 8.--15. 1. "GT,Guard time value" hexmask.long.byte 0xC 0.--7. 1. "PSC,Prescaler value" line.long 0x10 "RTOR,Receiver timeout register" hexmask.long.byte 0x10 24.--31. 1. "BLEN,Block Length" hexmask.long.tbyte 0x10 0.--23. 1. "RTO,Receiver timeout value" wgroup.long 0x18++0x3 line.long 0x0 "RQR,Request register" bitfld.long 0x0 4. "TXFRQ,Transmit data flush request" "0,1" bitfld.long 0x0 3. "RXFRQ,Receive data flush request" "0,1" bitfld.long 0x0 2. "MMRQ,Mute mode request" "0,1" bitfld.long 0x0 1. "SBKRQ,Send break request" "0,1" bitfld.long 0x0 0. "ABRRQ,Auto baud rate request" "0,1" wgroup.long 0x20++0x3 line.long 0x0 "ICR,Interrupt flag clear register" bitfld.long 0x0 20. "WUCF,Wakeup from Stop mode clear flag" "0,1" bitfld.long 0x0 17. "CMCF,Character match clear flag" "0,1" bitfld.long 0x0 13. "UDRCF,SPI slave underrun clear flag" "0,1" bitfld.long 0x0 12. "EOBCF,End of block clear flag" "0,1" bitfld.long 0x0 11. "RTOCF,Receiver timeout clear flag" "0,1" bitfld.long 0x0 9. "CTSCF,CTS clear flag" "0,1" bitfld.long 0x0 8. "LBDCF,LIN break detection clear flag" "0,1" bitfld.long 0x0 7. "TCBGTCF,Transmission complete before Guard time clear flag" "0,1" newline bitfld.long 0x0 6. "TCCF,Transmission complete clear flag" "0,1" bitfld.long 0x0 5. "TXFECF,TXFIFO empty clear flag" "0,1" bitfld.long 0x0 4. "IDLECF,Idle line detected clear flag" "0,1" bitfld.long 0x0 3. "ORECF,Overrun error clear flag" "0,1" bitfld.long 0x0 2. "NCF,Noise detected clear flag" "0,1" bitfld.long 0x0 1. "FECF,Framing error clear flag" "0,1" bitfld.long 0x0 0. "PECF,Parity error clear flag" "0,1" rgroup.long 0x24++0x3 line.long 0x0 "RDR,Receive data register" hexmask.long.word 0x0 0.--8. 1. "RDR,Receive data value" group.long 0x28++0x7 line.long 0x0 "TDR,Transmit data register" hexmask.long.word 0x0 0.--8. 1. "TDR,Transmit data value" line.long 0x4 "PRESC,Prescaler register" hexmask.long.byte 0x4 0.--3. 1. "PRESCALER,Clock prescaler" rgroup.long 0x3EC++0x13 line.long 0x0 "HWCFGR2,USART Hardware Configuration register 2" hexmask.long.byte 0x0 4.--7. 1. "CFG2,CFG2" hexmask.long.byte 0x0 0.--3. 1. "CFG1,CFG1" line.long 0x4 "HWCFGR1,USART Hardware Configuration register 1" hexmask.long.byte 0x4 28.--31. 1. "CFG8,CFG8" hexmask.long.byte 0x4 24.--27. 1. "CFG7,CFG7" hexmask.long.byte 0x4 20.--23. 1. "CFG6,CFG6" hexmask.long.byte 0x4 16.--19. 1. "CFG5,CFG5" hexmask.long.byte 0x4 12.--15. 1. "CFG4,CFG4" hexmask.long.byte 0x4 8.--11. 1. "CFG3,CFG3" hexmask.long.byte 0x4 4.--7. 1. "CFG2,CFG2" hexmask.long.byte 0x4 0.--3. 1. "CFG1,CFG1" line.long 0x8 "VERR,EXTI IP Version register" hexmask.long.byte 0x8 4.--7. 1. "MAJREV,Major Revision number" hexmask.long.byte 0x8 0.--3. 1. "MINREV,Minor Revision number" line.long 0xC "IPIDR,EXTI Identification register" hexmask.long 0xC 0.--31. 1. "IPID,IP Identification" line.long 0x10 "SIDR,EXTI Size ID register" hexmask.long 0x10 0.--31. 1. "SID,Size Identification" tree.end endif sif (cpuis("STM32MP13*")||cpuis("STM32MP151*")) tree "USART4" base ad:0x40010000 sif (cpuis("STM32MP13*")) group.long 0x0++0x3 line.long 0x0 "CR1_FIFO_enabled,Control register 1" bitfld.long 0x0 31. "RXFFIE,RXFIFO Full interrupt enable" "0,1" bitfld.long 0x0 30. "TXFEIE,TXFIFO empty interrupt enable" "0,1" newline bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0,1" bitfld.long 0x0 28. "M1,Word length" "0,1" newline bitfld.long 0x0 27. "EOBIE,End of Block interrupt enable" "0,1" bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0,1" newline hexmask.long.byte 0x0 21.--25. 1. "DEAT,DEAT" hexmask.long.byte 0x0 16.--20. 1. "DEDT,DEDT" newline bitfld.long 0x0 15. "OVER8,Oversampling mode" "0,1" bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0,1" newline bitfld.long 0x0 13. "MME,Mute mode enable" "0,1" bitfld.long 0x0 12. "M0,Word length" "0,1" newline bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0,1" bitfld.long 0x0 10. "PCE,Parity control enable" "0,1" newline bitfld.long 0x0 9. "PS,Parity selection" "0,1" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0,1" newline bitfld.long 0x0 7. "TXEIE,interrupt enable" "0,1" bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0,1" newline bitfld.long 0x0 5. "RXNEIE,RXNE interrupt enable" "0,1" bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0,1" newline bitfld.long 0x0 3. "TE,Transmitter enable" "0,1" bitfld.long 0x0 2. "RE,Receiver enable" "0,1" newline bitfld.long 0x0 1. "UESM,USART enable in Stop mode" "0,1" bitfld.long 0x0 0. "UE,USART enable" "0,1" group.long 0x0++0x3 line.long 0x0 "CR1_FIFO_disabled,Control register 1" bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0,1" bitfld.long 0x0 28. "M1,Word length" "0,1" newline bitfld.long 0x0 27. "EOBIE,End of Block interrupt enable" "0,1" bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0,1" newline hexmask.long.byte 0x0 21.--25. 1. "DEAT,DEAT" hexmask.long.byte 0x0 16.--20. 1. "DEDT,DEDT" newline bitfld.long 0x0 15. "OVER8,Oversampling mode" "0,1" bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0,1" newline bitfld.long 0x0 13. "MME,Mute mode enable" "0,1" bitfld.long 0x0 12. "M0,Word length" "0,1" newline bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0,1" bitfld.long 0x0 10. "PCE,Parity control enable" "0,1" newline bitfld.long 0x0 9. "PS,Parity selection" "0,1" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0,1" newline bitfld.long 0x0 7. "TXEIE,interrupt enable" "0,1" bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0,1" newline bitfld.long 0x0 5. "RXNEIE,RXNE interrupt enable" "0,1" bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0,1" newline bitfld.long 0x0 3. "TE,Transmitter enable" "0,1" bitfld.long 0x0 2. "RE,Receiver enable" "0,1" newline bitfld.long 0x0 1. "UESM,USART enable in Stop mode" "0,1" bitfld.long 0x0 0. "UE,USART enable" "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "ISR_FIFO_enabled,USART interrupt and status register" bitfld.long 0x0 27. "TXFT,TXFIFO threshold flag" "0,1" bitfld.long 0x0 26. "RXFT,RXFIFO threshold flag" "0,1" newline bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time flag" "0,1" bitfld.long 0x0 24. "RXFF,RXFIFO Full" "0,1" newline bitfld.long 0x0 23. "TXFE,TXFIFO Empty" "0,1" bitfld.long 0x0 22. "REACK,REACK" "0,1" newline bitfld.long 0x0 21. "TEACK,TEACK" "0,1" bitfld.long 0x0 20. "WUF,WUF" "0,1" newline bitfld.long 0x0 19. "RWU,RWU" "0,1" bitfld.long 0x0 18. "SBKF,SBKF" "0,1" newline bitfld.long 0x0 17. "CMF,CMF" "0,1" bitfld.long 0x0 16. "BUSY,BUSY" "0,1" newline bitfld.long 0x0 15. "ABRF,ABRF" "0,1" bitfld.long 0x0 14. "ABRE,ABRE" "0,1" newline bitfld.long 0x0 13. "UDR,SPI slave underrun error flag" "0,1" bitfld.long 0x0 12. "EOBF,EOBF" "0,1" newline bitfld.long 0x0 11. "RTOF,RTOF" "0,1" bitfld.long 0x0 10. "CTS,CTS" "0,1" newline bitfld.long 0x0 9. "CTSIF,CTSIF" "0,1" bitfld.long 0x0 8. "LBDF,LBDF" "0,1" newline bitfld.long 0x0 7. "TXE,TXE" "0,1" bitfld.long 0x0 6. "TC,TC" "0,1" newline bitfld.long 0x0 5. "RXNE,RXNE" "0,1" bitfld.long 0x0 4. "IDLE,IDLE" "0,1" newline bitfld.long 0x0 3. "ORE,ORE" "0,1" bitfld.long 0x0 2. "NF,NF" "0,1" newline bitfld.long 0x0 1. "FE,FE" "0,1" bitfld.long 0x0 0. "PE,PE" "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "ISR_FIFO_disabled,USART interrupt and status register" bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time flag" "0,1" bitfld.long 0x0 22. "REACK,REACK" "0,1" newline bitfld.long 0x0 21. "TEACK,TEACK" "0,1" bitfld.long 0x0 20. "WUF,WUF" "0,1" newline bitfld.long 0x0 19. "RWU,RWU" "0,1" bitfld.long 0x0 18. "SBKF,SBKF" "0,1" newline bitfld.long 0x0 17. "CMF,CMF" "0,1" bitfld.long 0x0 16. "BUSY,BUSY" "0,1" newline bitfld.long 0x0 15. "ABRF,ABRF" "0,1" bitfld.long 0x0 14. "ABRE,ABRE" "0,1" newline bitfld.long 0x0 13. "UDR,SPI slave underrun error flag" "0,1" bitfld.long 0x0 12. "EOBF,EOBF" "0,1" newline bitfld.long 0x0 11. "RTOF,RTOF" "0,1" bitfld.long 0x0 10. "CTS,CTS" "0,1" newline bitfld.long 0x0 9. "CTSIF,CTSIF" "0,1" bitfld.long 0x0 8. "LBDF,LBDF" "0,1" newline bitfld.long 0x0 7. "TXE,TXE" "0,1" bitfld.long 0x0 6. "TC,TC" "0,1" newline bitfld.long 0x0 5. "RXNE,RXNE" "0,1" bitfld.long 0x0 4. "IDLE,IDLE" "0,1" newline bitfld.long 0x0 3. "ORE,ORE" "0,1" bitfld.long 0x0 2. "NF,NF" "0,1" newline bitfld.long 0x0 1. "FE,FE" "0,1" bitfld.long 0x0 0. "PE,PE" "0,1" endif sif (cpuis("STM32MP151*")) group.long 0x0++0x3 line.long 0x0 "CR1,Control register 1" bitfld.long 0x0 31. "RXFFIE,RXFIFO Full interrupt enable" "0,1" bitfld.long 0x0 30. "TXFEIE,TXFIFO empty interrupt enable" "0,1" newline bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0,1" bitfld.long 0x0 28. "M1,Word length" "0,1" newline bitfld.long 0x0 27. "EOBIE,End of Block interrupt enable" "0,1" bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0,1" newline hexmask.long.byte 0x0 21.--25. 1. "DEAT,DEAT" hexmask.long.byte 0x0 16.--20. 1. "DEDT,DEDT" newline bitfld.long 0x0 15. "OVER8,Oversampling mode" "0,1" bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0,1" newline bitfld.long 0x0 13. "MME,Mute mode enable" "0,1" bitfld.long 0x0 12. "M0,Word length" "0,1" newline bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0,1" bitfld.long 0x0 10. "PCE,Parity control enable" "0,1" newline bitfld.long 0x0 9. "PS,Parity selection" "0,1" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0,1" newline bitfld.long 0x0 7. "TXEIE,interrupt enable" "0,1" bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0,1" newline bitfld.long 0x0 5. "RXNEIE,RXNE interrupt enable" "0,1" bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0,1" newline bitfld.long 0x0 3. "TE,Transmitter enable" "0,1" bitfld.long 0x0 2. "RE,Receiver enable" "0,1" newline bitfld.long 0x0 1. "UESM,USART enable in Stop mode" "0,1" bitfld.long 0x0 0. "UE,USART enable" "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "ISR,Interrupt & status register" bitfld.long 0x0 27. "TXFT,TXFIFO threshold flag" "0,1" bitfld.long 0x0 26. "RXFT,RXFIFO threshold flag" "0,1" newline bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time flag" "0,1" bitfld.long 0x0 24. "RXFF,RXFIFO Full" "0,1" newline bitfld.long 0x0 23. "TXFE,TXFIFO Empty" "0,1" bitfld.long 0x0 22. "REACK,REACK" "0,1" newline bitfld.long 0x0 21. "TEACK,TEACK" "0,1" bitfld.long 0x0 20. "WUF,WUF" "0,1" newline bitfld.long 0x0 19. "RWU,RWU" "0,1" bitfld.long 0x0 18. "SBKF,SBKF" "0,1" newline bitfld.long 0x0 17. "CMF,CMF" "0,1" bitfld.long 0x0 16. "BUSY,BUSY" "0,1" newline bitfld.long 0x0 15. "ABRF,ABRF" "0,1" bitfld.long 0x0 14. "ABRE,ABRE" "0,1" newline bitfld.long 0x0 13. "UDR,SPI slave underrun error flag" "0,1" bitfld.long 0x0 12. "EOBF,EOBF" "0,1" newline bitfld.long 0x0 11. "RTOF,RTOF" "0,1" bitfld.long 0x0 10. "CTS,CTS" "0,1" newline bitfld.long 0x0 9. "CTSIF,CTSIF" "0,1" bitfld.long 0x0 8. "LBDF,LBDF" "0,1" newline bitfld.long 0x0 7. "TXE,TXE" "0,1" bitfld.long 0x0 6. "TC,TC" "0,1" newline bitfld.long 0x0 5. "RXNE,RXNE" "0,1" bitfld.long 0x0 4. "IDLE,IDLE" "0,1" newline bitfld.long 0x0 3. "ORE,ORE" "0,1" bitfld.long 0x0 2. "NF,NF" "0,1" newline bitfld.long 0x0 1. "FE,FE" "0,1" bitfld.long 0x0 0. "PE,PE" "0,1" endif group.long 0x4++0x13 line.long 0x0 "CR2,Control register 2" hexmask.long.byte 0x0 28.--31. 1. "ADD4_7,Address of the USART node" hexmask.long.byte 0x0 24.--27. 1. "ADD0_3,Address of the USART node" bitfld.long 0x0 23. "RTOEN,Receiver timeout enable" "0,1" bitfld.long 0x0 21.--22. "ABRMOD,Auto baud rate mode" "0,1,2,3" bitfld.long 0x0 20. "ABREN,Auto baud rate enable" "0,1" bitfld.long 0x0 19. "MSBFIRST,Most significant bit first" "0,1" bitfld.long 0x0 18. "TAINV,Binary data inversion" "0,1" bitfld.long 0x0 17. "TXINV,TX pin active level inversion" "0,1" newline bitfld.long 0x0 16. "RXINV,RX pin active level inversion" "0,1" bitfld.long 0x0 15. "SWAP,Swap TX/RX pins" "0,1" bitfld.long 0x0 14. "LINEN,LIN mode enable" "0,1" bitfld.long 0x0 12.--13. "STOP,STOP bits" "0,1,2,3" bitfld.long 0x0 11. "CLKEN,Clock enable" "0,1" bitfld.long 0x0 10. "CPOL,Clock polarity" "0,1" bitfld.long 0x0 9. "CPHA,Clock phase" "0,1" bitfld.long 0x0 8. "LBCL,Last bit clock pulse" "0,1" newline bitfld.long 0x0 6. "LBDIE,LIN break detection interrupt enable" "0,1" bitfld.long 0x0 5. "LBDL,LIN break detection length" "0,1" bitfld.long 0x0 4. "ADDM7,7-bit Address Detection/4-bit Address Detection" "0,1" bitfld.long 0x0 3. "DIS_NSS,When the DSI_NSS bit is set the NSS pin input will be ignored" "0,1" bitfld.long 0x0 0. "SLVEN,Synchronous Slave mode enable" "0,1" line.long 0x4 "CR3,Control register 3" bitfld.long 0x4 29.--31. "TXFTCFG,TXFIFO threshold configuration" "0,1,2,3,4,5,6,7" bitfld.long 0x4 28. "RXFTIE,RXFIFO threshold interrupt enable" "0,1" bitfld.long 0x4 25.--27. "RXFTCFG,Receive FIFO threshold configuration" "0,1,2,3,4,5,6,7" bitfld.long 0x4 24. "TCBGTIE,Tr Complete before guard time interrupt enable" "0,1" bitfld.long 0x4 23. "TXFTIE,threshold interrupt enable" "0,1" bitfld.long 0x4 22. "WUFIE,Wakeup from Stop mode interrupt enable" "0,1" bitfld.long 0x4 20.--21. "WUS,Wakeup from Stop mode interrupt flag selection" "0,1,2,3" bitfld.long 0x4 17.--19. "SCARCNT,Smartcard auto-retry count" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 15. "DEP,Driver enable polarity selection" "0,1" bitfld.long 0x4 14. "DEM,Driver enable mode" "0,1" bitfld.long 0x4 13. "DDRE,DMA Disable on Reception Error" "0,1" bitfld.long 0x4 12. "OVRDIS,Overrun Disable" "0,1" bitfld.long 0x4 11. "ONEBIT,One sample bit method enable" "0,1" bitfld.long 0x4 10. "CTSIE,CTS interrupt enable" "0,1" bitfld.long 0x4 9. "CTSE,CTS enable" "0,1" bitfld.long 0x4 8. "RTSE,RTS enable" "0,1" newline bitfld.long 0x4 7. "DMAT,DMA enable transmitter" "0,1" bitfld.long 0x4 6. "DMAR,DMA enable receiver" "0,1" bitfld.long 0x4 5. "SCEN,Smartcard mode enable" "0,1" bitfld.long 0x4 4. "NACK,Smartcard NACK enable" "0,1" bitfld.long 0x4 3. "HDSEL,Half-duplex selection" "0,1" bitfld.long 0x4 2. "IRLP,Ir low-power" "0,1" bitfld.long 0x4 1. "IREN,Ir mode enable" "0,1" bitfld.long 0x4 0. "EIE,Error interrupt enable" "0,1" line.long 0x8 "BRR,Baud rate register" hexmask.long.word 0x8 4.--15. 1. "BRR_4_15,BRR_4_15" hexmask.long.byte 0x8 0.--3. 1. "BRR_0_3,BRR_0_3" line.long 0xC "GTPR,Guard time and prescaler register" hexmask.long.byte 0xC 8.--15. 1. "GT,Guard time value" hexmask.long.byte 0xC 0.--7. 1. "PSC,Prescaler value" line.long 0x10 "RTOR,Receiver timeout register" hexmask.long.byte 0x10 24.--31. 1. "BLEN,Block Length" hexmask.long.tbyte 0x10 0.--23. 1. "RTO,Receiver timeout value" wgroup.long 0x18++0x3 line.long 0x0 "RQR,Request register" bitfld.long 0x0 4. "TXFRQ,Transmit data flush request" "0,1" bitfld.long 0x0 3. "RXFRQ,Receive data flush request" "0,1" bitfld.long 0x0 2. "MMRQ,Mute mode request" "0,1" bitfld.long 0x0 1. "SBKRQ,Send break request" "0,1" bitfld.long 0x0 0. "ABRRQ,Auto baud rate request" "0,1" wgroup.long 0x20++0x3 line.long 0x0 "ICR,Interrupt flag clear register" bitfld.long 0x0 20. "WUCF,Wakeup from Stop mode clear flag" "0,1" bitfld.long 0x0 17. "CMCF,Character match clear flag" "0,1" bitfld.long 0x0 13. "UDRCF,SPI slave underrun clear flag" "0,1" bitfld.long 0x0 12. "EOBCF,End of block clear flag" "0,1" bitfld.long 0x0 11. "RTOCF,Receiver timeout clear flag" "0,1" bitfld.long 0x0 9. "CTSCF,CTS clear flag" "0,1" bitfld.long 0x0 8. "LBDCF,LIN break detection clear flag" "0,1" bitfld.long 0x0 7. "TCBGTCF,Transmission complete before Guard time clear flag" "0,1" newline bitfld.long 0x0 6. "TCCF,Transmission complete clear flag" "0,1" bitfld.long 0x0 5. "TXFECF,TXFIFO empty clear flag" "0,1" bitfld.long 0x0 4. "IDLECF,Idle line detected clear flag" "0,1" bitfld.long 0x0 3. "ORECF,Overrun error clear flag" "0,1" bitfld.long 0x0 2. "NCF,Noise detected clear flag" "0,1" bitfld.long 0x0 1. "FECF,Framing error clear flag" "0,1" bitfld.long 0x0 0. "PECF,Parity error clear flag" "0,1" rgroup.long 0x24++0x3 line.long 0x0 "RDR,Receive data register" hexmask.long.word 0x0 0.--8. 1. "RDR,Receive data value" group.long 0x28++0x7 line.long 0x0 "TDR,Transmit data register" hexmask.long.word 0x0 0.--8. 1. "TDR,Transmit data value" line.long 0x4 "PRESC,Prescaler register" hexmask.long.byte 0x4 0.--3. 1. "PRESCALER,Clock prescaler" rgroup.long 0x3EC++0x13 line.long 0x0 "HWCFGR2,USART Hardware Configuration register 2" hexmask.long.byte 0x0 4.--7. 1. "CFG2,CFG2" hexmask.long.byte 0x0 0.--3. 1. "CFG1,CFG1" line.long 0x4 "HWCFGR1,USART Hardware Configuration register 1" hexmask.long.byte 0x4 28.--31. 1. "CFG8,CFG8" hexmask.long.byte 0x4 24.--27. 1. "CFG7,CFG7" hexmask.long.byte 0x4 20.--23. 1. "CFG6,CFG6" hexmask.long.byte 0x4 16.--19. 1. "CFG5,CFG5" hexmask.long.byte 0x4 12.--15. 1. "CFG4,CFG4" hexmask.long.byte 0x4 8.--11. 1. "CFG3,CFG3" hexmask.long.byte 0x4 4.--7. 1. "CFG2,CFG2" hexmask.long.byte 0x4 0.--3. 1. "CFG1,CFG1" line.long 0x8 "VERR,EXTI IP Version register" hexmask.long.byte 0x8 4.--7. 1. "MAJREV,Major Revision number" hexmask.long.byte 0x8 0.--3. 1. "MINREV,Minor Revision number" line.long 0xC "IPIDR,EXTI Identification register" hexmask.long 0xC 0.--31. 1. "IPID,IP Identification" line.long 0x10 "SIDR,EXTI Size ID register" hexmask.long 0x10 0.--31. 1. "SID,Size Identification" tree.end endif sif (cpuis("STM32MP13*")||cpuis("STM32MP151*")) tree "USART5" base ad:0x40011000 sif (cpuis("STM32MP13*")) group.long 0x0++0x3 line.long 0x0 "CR1_FIFO_enabled,Control register 1" bitfld.long 0x0 31. "RXFFIE,RXFIFO Full interrupt enable" "0,1" bitfld.long 0x0 30. "TXFEIE,TXFIFO empty interrupt enable" "0,1" newline bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0,1" bitfld.long 0x0 28. "M1,Word length" "0,1" newline bitfld.long 0x0 27. "EOBIE,End of Block interrupt enable" "0,1" bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0,1" newline hexmask.long.byte 0x0 21.--25. 1. "DEAT,DEAT" hexmask.long.byte 0x0 16.--20. 1. "DEDT,DEDT" newline bitfld.long 0x0 15. "OVER8,Oversampling mode" "0,1" bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0,1" newline bitfld.long 0x0 13. "MME,Mute mode enable" "0,1" bitfld.long 0x0 12. "M0,Word length" "0,1" newline bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0,1" bitfld.long 0x0 10. "PCE,Parity control enable" "0,1" newline bitfld.long 0x0 9. "PS,Parity selection" "0,1" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0,1" newline bitfld.long 0x0 7. "TXEIE,interrupt enable" "0,1" bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0,1" newline bitfld.long 0x0 5. "RXNEIE,RXNE interrupt enable" "0,1" bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0,1" newline bitfld.long 0x0 3. "TE,Transmitter enable" "0,1" bitfld.long 0x0 2. "RE,Receiver enable" "0,1" newline bitfld.long 0x0 1. "UESM,USART enable in Stop mode" "0,1" bitfld.long 0x0 0. "UE,USART enable" "0,1" group.long 0x0++0x3 line.long 0x0 "CR1_FIFO_disabled,Control register 1" bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0,1" bitfld.long 0x0 28. "M1,Word length" "0,1" newline bitfld.long 0x0 27. "EOBIE,End of Block interrupt enable" "0,1" bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0,1" newline hexmask.long.byte 0x0 21.--25. 1. "DEAT,DEAT" hexmask.long.byte 0x0 16.--20. 1. "DEDT,DEDT" newline bitfld.long 0x0 15. "OVER8,Oversampling mode" "0,1" bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0,1" newline bitfld.long 0x0 13. "MME,Mute mode enable" "0,1" bitfld.long 0x0 12. "M0,Word length" "0,1" newline bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0,1" bitfld.long 0x0 10. "PCE,Parity control enable" "0,1" newline bitfld.long 0x0 9. "PS,Parity selection" "0,1" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0,1" newline bitfld.long 0x0 7. "TXEIE,interrupt enable" "0,1" bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0,1" newline bitfld.long 0x0 5. "RXNEIE,RXNE interrupt enable" "0,1" bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0,1" newline bitfld.long 0x0 3. "TE,Transmitter enable" "0,1" bitfld.long 0x0 2. "RE,Receiver enable" "0,1" newline bitfld.long 0x0 1. "UESM,USART enable in Stop mode" "0,1" bitfld.long 0x0 0. "UE,USART enable" "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "ISR_FIFO_enabled,USART interrupt and status register" bitfld.long 0x0 27. "TXFT,TXFIFO threshold flag" "0,1" bitfld.long 0x0 26. "RXFT,RXFIFO threshold flag" "0,1" newline bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time flag" "0,1" bitfld.long 0x0 24. "RXFF,RXFIFO Full" "0,1" newline bitfld.long 0x0 23. "TXFE,TXFIFO Empty" "0,1" bitfld.long 0x0 22. "REACK,REACK" "0,1" newline bitfld.long 0x0 21. "TEACK,TEACK" "0,1" bitfld.long 0x0 20. "WUF,WUF" "0,1" newline bitfld.long 0x0 19. "RWU,RWU" "0,1" bitfld.long 0x0 18. "SBKF,SBKF" "0,1" newline bitfld.long 0x0 17. "CMF,CMF" "0,1" bitfld.long 0x0 16. "BUSY,BUSY" "0,1" newline bitfld.long 0x0 15. "ABRF,ABRF" "0,1" bitfld.long 0x0 14. "ABRE,ABRE" "0,1" newline bitfld.long 0x0 13. "UDR,SPI slave underrun error flag" "0,1" bitfld.long 0x0 12. "EOBF,EOBF" "0,1" newline bitfld.long 0x0 11. "RTOF,RTOF" "0,1" bitfld.long 0x0 10. "CTS,CTS" "0,1" newline bitfld.long 0x0 9. "CTSIF,CTSIF" "0,1" bitfld.long 0x0 8. "LBDF,LBDF" "0,1" newline bitfld.long 0x0 7. "TXE,TXE" "0,1" bitfld.long 0x0 6. "TC,TC" "0,1" newline bitfld.long 0x0 5. "RXNE,RXNE" "0,1" bitfld.long 0x0 4. "IDLE,IDLE" "0,1" newline bitfld.long 0x0 3. "ORE,ORE" "0,1" bitfld.long 0x0 2. "NF,NF" "0,1" newline bitfld.long 0x0 1. "FE,FE" "0,1" bitfld.long 0x0 0. "PE,PE" "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "ISR_FIFO_disabled,USART interrupt and status register" bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time flag" "0,1" bitfld.long 0x0 22. "REACK,REACK" "0,1" newline bitfld.long 0x0 21. "TEACK,TEACK" "0,1" bitfld.long 0x0 20. "WUF,WUF" "0,1" newline bitfld.long 0x0 19. "RWU,RWU" "0,1" bitfld.long 0x0 18. "SBKF,SBKF" "0,1" newline bitfld.long 0x0 17. "CMF,CMF" "0,1" bitfld.long 0x0 16. "BUSY,BUSY" "0,1" newline bitfld.long 0x0 15. "ABRF,ABRF" "0,1" bitfld.long 0x0 14. "ABRE,ABRE" "0,1" newline bitfld.long 0x0 13. "UDR,SPI slave underrun error flag" "0,1" bitfld.long 0x0 12. "EOBF,EOBF" "0,1" newline bitfld.long 0x0 11. "RTOF,RTOF" "0,1" bitfld.long 0x0 10. "CTS,CTS" "0,1" newline bitfld.long 0x0 9. "CTSIF,CTSIF" "0,1" bitfld.long 0x0 8. "LBDF,LBDF" "0,1" newline bitfld.long 0x0 7. "TXE,TXE" "0,1" bitfld.long 0x0 6. "TC,TC" "0,1" newline bitfld.long 0x0 5. "RXNE,RXNE" "0,1" bitfld.long 0x0 4. "IDLE,IDLE" "0,1" newline bitfld.long 0x0 3. "ORE,ORE" "0,1" bitfld.long 0x0 2. "NF,NF" "0,1" newline bitfld.long 0x0 1. "FE,FE" "0,1" bitfld.long 0x0 0. "PE,PE" "0,1" endif sif (cpuis("STM32MP151*")) group.long 0x0++0x3 line.long 0x0 "CR1,Control register 1" bitfld.long 0x0 31. "RXFFIE,RXFIFO Full interrupt enable" "0,1" bitfld.long 0x0 30. "TXFEIE,TXFIFO empty interrupt enable" "0,1" newline bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0,1" bitfld.long 0x0 28. "M1,Word length" "0,1" newline bitfld.long 0x0 27. "EOBIE,End of Block interrupt enable" "0,1" bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0,1" newline hexmask.long.byte 0x0 21.--25. 1. "DEAT,DEAT" hexmask.long.byte 0x0 16.--20. 1. "DEDT,DEDT" newline bitfld.long 0x0 15. "OVER8,Oversampling mode" "0,1" bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0,1" newline bitfld.long 0x0 13. "MME,Mute mode enable" "0,1" bitfld.long 0x0 12. "M0,Word length" "0,1" newline bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0,1" bitfld.long 0x0 10. "PCE,Parity control enable" "0,1" newline bitfld.long 0x0 9. "PS,Parity selection" "0,1" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0,1" newline bitfld.long 0x0 7. "TXEIE,interrupt enable" "0,1" bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0,1" newline bitfld.long 0x0 5. "RXNEIE,RXNE interrupt enable" "0,1" bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0,1" newline bitfld.long 0x0 3. "TE,Transmitter enable" "0,1" bitfld.long 0x0 2. "RE,Receiver enable" "0,1" newline bitfld.long 0x0 1. "UESM,USART enable in Stop mode" "0,1" bitfld.long 0x0 0. "UE,USART enable" "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "ISR,Interrupt & status register" bitfld.long 0x0 27. "TXFT,TXFIFO threshold flag" "0,1" bitfld.long 0x0 26. "RXFT,RXFIFO threshold flag" "0,1" newline bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time flag" "0,1" bitfld.long 0x0 24. "RXFF,RXFIFO Full" "0,1" newline bitfld.long 0x0 23. "TXFE,TXFIFO Empty" "0,1" bitfld.long 0x0 22. "REACK,REACK" "0,1" newline bitfld.long 0x0 21. "TEACK,TEACK" "0,1" bitfld.long 0x0 20. "WUF,WUF" "0,1" newline bitfld.long 0x0 19. "RWU,RWU" "0,1" bitfld.long 0x0 18. "SBKF,SBKF" "0,1" newline bitfld.long 0x0 17. "CMF,CMF" "0,1" bitfld.long 0x0 16. "BUSY,BUSY" "0,1" newline bitfld.long 0x0 15. "ABRF,ABRF" "0,1" bitfld.long 0x0 14. "ABRE,ABRE" "0,1" newline bitfld.long 0x0 13. "UDR,SPI slave underrun error flag" "0,1" bitfld.long 0x0 12. "EOBF,EOBF" "0,1" newline bitfld.long 0x0 11. "RTOF,RTOF" "0,1" bitfld.long 0x0 10. "CTS,CTS" "0,1" newline bitfld.long 0x0 9. "CTSIF,CTSIF" "0,1" bitfld.long 0x0 8. "LBDF,LBDF" "0,1" newline bitfld.long 0x0 7. "TXE,TXE" "0,1" bitfld.long 0x0 6. "TC,TC" "0,1" newline bitfld.long 0x0 5. "RXNE,RXNE" "0,1" bitfld.long 0x0 4. "IDLE,IDLE" "0,1" newline bitfld.long 0x0 3. "ORE,ORE" "0,1" bitfld.long 0x0 2. "NF,NF" "0,1" newline bitfld.long 0x0 1. "FE,FE" "0,1" bitfld.long 0x0 0. "PE,PE" "0,1" endif group.long 0x4++0x13 line.long 0x0 "CR2,Control register 2" hexmask.long.byte 0x0 28.--31. 1. "ADD4_7,Address of the USART node" hexmask.long.byte 0x0 24.--27. 1. "ADD0_3,Address of the USART node" bitfld.long 0x0 23. "RTOEN,Receiver timeout enable" "0,1" bitfld.long 0x0 21.--22. "ABRMOD,Auto baud rate mode" "0,1,2,3" bitfld.long 0x0 20. "ABREN,Auto baud rate enable" "0,1" bitfld.long 0x0 19. "MSBFIRST,Most significant bit first" "0,1" bitfld.long 0x0 18. "TAINV,Binary data inversion" "0,1" bitfld.long 0x0 17. "TXINV,TX pin active level inversion" "0,1" newline bitfld.long 0x0 16. "RXINV,RX pin active level inversion" "0,1" bitfld.long 0x0 15. "SWAP,Swap TX/RX pins" "0,1" bitfld.long 0x0 14. "LINEN,LIN mode enable" "0,1" bitfld.long 0x0 12.--13. "STOP,STOP bits" "0,1,2,3" bitfld.long 0x0 11. "CLKEN,Clock enable" "0,1" bitfld.long 0x0 10. "CPOL,Clock polarity" "0,1" bitfld.long 0x0 9. "CPHA,Clock phase" "0,1" bitfld.long 0x0 8. "LBCL,Last bit clock pulse" "0,1" newline bitfld.long 0x0 6. "LBDIE,LIN break detection interrupt enable" "0,1" bitfld.long 0x0 5. "LBDL,LIN break detection length" "0,1" bitfld.long 0x0 4. "ADDM7,7-bit Address Detection/4-bit Address Detection" "0,1" bitfld.long 0x0 3. "DIS_NSS,When the DSI_NSS bit is set the NSS pin input will be ignored" "0,1" bitfld.long 0x0 0. "SLVEN,Synchronous Slave mode enable" "0,1" line.long 0x4 "CR3,Control register 3" bitfld.long 0x4 29.--31. "TXFTCFG,TXFIFO threshold configuration" "0,1,2,3,4,5,6,7" bitfld.long 0x4 28. "RXFTIE,RXFIFO threshold interrupt enable" "0,1" bitfld.long 0x4 25.--27. "RXFTCFG,Receive FIFO threshold configuration" "0,1,2,3,4,5,6,7" bitfld.long 0x4 24. "TCBGTIE,Tr Complete before guard time interrupt enable" "0,1" bitfld.long 0x4 23. "TXFTIE,threshold interrupt enable" "0,1" bitfld.long 0x4 22. "WUFIE,Wakeup from Stop mode interrupt enable" "0,1" bitfld.long 0x4 20.--21. "WUS,Wakeup from Stop mode interrupt flag selection" "0,1,2,3" bitfld.long 0x4 17.--19. "SCARCNT,Smartcard auto-retry count" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 15. "DEP,Driver enable polarity selection" "0,1" bitfld.long 0x4 14. "DEM,Driver enable mode" "0,1" bitfld.long 0x4 13. "DDRE,DMA Disable on Reception Error" "0,1" bitfld.long 0x4 12. "OVRDIS,Overrun Disable" "0,1" bitfld.long 0x4 11. "ONEBIT,One sample bit method enable" "0,1" bitfld.long 0x4 10. "CTSIE,CTS interrupt enable" "0,1" bitfld.long 0x4 9. "CTSE,CTS enable" "0,1" bitfld.long 0x4 8. "RTSE,RTS enable" "0,1" newline bitfld.long 0x4 7. "DMAT,DMA enable transmitter" "0,1" bitfld.long 0x4 6. "DMAR,DMA enable receiver" "0,1" bitfld.long 0x4 5. "SCEN,Smartcard mode enable" "0,1" bitfld.long 0x4 4. "NACK,Smartcard NACK enable" "0,1" bitfld.long 0x4 3. "HDSEL,Half-duplex selection" "0,1" bitfld.long 0x4 2. "IRLP,Ir low-power" "0,1" bitfld.long 0x4 1. "IREN,Ir mode enable" "0,1" bitfld.long 0x4 0. "EIE,Error interrupt enable" "0,1" line.long 0x8 "BRR,Baud rate register" hexmask.long.word 0x8 4.--15. 1. "BRR_4_15,BRR_4_15" hexmask.long.byte 0x8 0.--3. 1. "BRR_0_3,BRR_0_3" line.long 0xC "GTPR,Guard time and prescaler register" hexmask.long.byte 0xC 8.--15. 1. "GT,Guard time value" hexmask.long.byte 0xC 0.--7. 1. "PSC,Prescaler value" line.long 0x10 "RTOR,Receiver timeout register" hexmask.long.byte 0x10 24.--31. 1. "BLEN,Block Length" hexmask.long.tbyte 0x10 0.--23. 1. "RTO,Receiver timeout value" wgroup.long 0x18++0x3 line.long 0x0 "RQR,Request register" bitfld.long 0x0 4. "TXFRQ,Transmit data flush request" "0,1" bitfld.long 0x0 3. "RXFRQ,Receive data flush request" "0,1" bitfld.long 0x0 2. "MMRQ,Mute mode request" "0,1" bitfld.long 0x0 1. "SBKRQ,Send break request" "0,1" bitfld.long 0x0 0. "ABRRQ,Auto baud rate request" "0,1" wgroup.long 0x20++0x3 line.long 0x0 "ICR,Interrupt flag clear register" bitfld.long 0x0 20. "WUCF,Wakeup from Stop mode clear flag" "0,1" bitfld.long 0x0 17. "CMCF,Character match clear flag" "0,1" bitfld.long 0x0 13. "UDRCF,SPI slave underrun clear flag" "0,1" bitfld.long 0x0 12. "EOBCF,End of block clear flag" "0,1" bitfld.long 0x0 11. "RTOCF,Receiver timeout clear flag" "0,1" bitfld.long 0x0 9. "CTSCF,CTS clear flag" "0,1" bitfld.long 0x0 8. "LBDCF,LIN break detection clear flag" "0,1" bitfld.long 0x0 7. "TCBGTCF,Transmission complete before Guard time clear flag" "0,1" newline bitfld.long 0x0 6. "TCCF,Transmission complete clear flag" "0,1" bitfld.long 0x0 5. "TXFECF,TXFIFO empty clear flag" "0,1" bitfld.long 0x0 4. "IDLECF,Idle line detected clear flag" "0,1" bitfld.long 0x0 3. "ORECF,Overrun error clear flag" "0,1" bitfld.long 0x0 2. "NCF,Noise detected clear flag" "0,1" bitfld.long 0x0 1. "FECF,Framing error clear flag" "0,1" bitfld.long 0x0 0. "PECF,Parity error clear flag" "0,1" rgroup.long 0x24++0x3 line.long 0x0 "RDR,Receive data register" hexmask.long.word 0x0 0.--8. 1. "RDR,Receive data value" group.long 0x28++0x7 line.long 0x0 "TDR,Transmit data register" hexmask.long.word 0x0 0.--8. 1. "TDR,Transmit data value" line.long 0x4 "PRESC,Prescaler register" hexmask.long.byte 0x4 0.--3. 1. "PRESCALER,Clock prescaler" rgroup.long 0x3EC++0x13 line.long 0x0 "HWCFGR2,USART Hardware Configuration register 2" hexmask.long.byte 0x0 4.--7. 1. "CFG2,CFG2" hexmask.long.byte 0x0 0.--3. 1. "CFG1,CFG1" line.long 0x4 "HWCFGR1,USART Hardware Configuration register 1" hexmask.long.byte 0x4 28.--31. 1. "CFG8,CFG8" hexmask.long.byte 0x4 24.--27. 1. "CFG7,CFG7" hexmask.long.byte 0x4 20.--23. 1. "CFG6,CFG6" hexmask.long.byte 0x4 16.--19. 1. "CFG5,CFG5" hexmask.long.byte 0x4 12.--15. 1. "CFG4,CFG4" hexmask.long.byte 0x4 8.--11. 1. "CFG3,CFG3" hexmask.long.byte 0x4 4.--7. 1. "CFG2,CFG2" hexmask.long.byte 0x4 0.--3. 1. "CFG1,CFG1" line.long 0x8 "VERR,EXTI IP Version register" hexmask.long.byte 0x8 4.--7. 1. "MAJREV,Major Revision number" hexmask.long.byte 0x8 0.--3. 1. "MINREV,Minor Revision number" line.long 0xC "IPIDR,EXTI Identification register" hexmask.long 0xC 0.--31. 1. "IPID,IP Identification" line.long 0x10 "SIDR,EXTI Size ID register" hexmask.long 0x10 0.--31. 1. "SID,Size Identification" tree.end endif sif (cpuis("STM32MP13*")||cpuis("STM32MP151*")) tree "USART6" base ad:0x44003000 sif (cpuis("STM32MP13*")) group.long 0x0++0x3 line.long 0x0 "CR1_FIFO_enabled,Control register 1" bitfld.long 0x0 31. "RXFFIE,RXFIFO Full interrupt enable" "0,1" bitfld.long 0x0 30. "TXFEIE,TXFIFO empty interrupt enable" "0,1" newline bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0,1" bitfld.long 0x0 28. "M1,Word length" "0,1" newline bitfld.long 0x0 27. "EOBIE,End of Block interrupt enable" "0,1" bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0,1" newline hexmask.long.byte 0x0 21.--25. 1. "DEAT,DEAT" hexmask.long.byte 0x0 16.--20. 1. "DEDT,DEDT" newline bitfld.long 0x0 15. "OVER8,Oversampling mode" "0,1" bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0,1" newline bitfld.long 0x0 13. "MME,Mute mode enable" "0,1" bitfld.long 0x0 12. "M0,Word length" "0,1" newline bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0,1" bitfld.long 0x0 10. "PCE,Parity control enable" "0,1" newline bitfld.long 0x0 9. "PS,Parity selection" "0,1" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0,1" newline bitfld.long 0x0 7. "TXEIE,interrupt enable" "0,1" bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0,1" newline bitfld.long 0x0 5. "RXNEIE,RXNE interrupt enable" "0,1" bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0,1" newline bitfld.long 0x0 3. "TE,Transmitter enable" "0,1" bitfld.long 0x0 2. "RE,Receiver enable" "0,1" newline bitfld.long 0x0 1. "UESM,USART enable in Stop mode" "0,1" bitfld.long 0x0 0. "UE,USART enable" "0,1" group.long 0x0++0x3 line.long 0x0 "CR1_FIFO_disabled,Control register 1" bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0,1" bitfld.long 0x0 28. "M1,Word length" "0,1" newline bitfld.long 0x0 27. "EOBIE,End of Block interrupt enable" "0,1" bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0,1" newline hexmask.long.byte 0x0 21.--25. 1. "DEAT,DEAT" hexmask.long.byte 0x0 16.--20. 1. "DEDT,DEDT" newline bitfld.long 0x0 15. "OVER8,Oversampling mode" "0,1" bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0,1" newline bitfld.long 0x0 13. "MME,Mute mode enable" "0,1" bitfld.long 0x0 12. "M0,Word length" "0,1" newline bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0,1" bitfld.long 0x0 10. "PCE,Parity control enable" "0,1" newline bitfld.long 0x0 9. "PS,Parity selection" "0,1" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0,1" newline bitfld.long 0x0 7. "TXEIE,interrupt enable" "0,1" bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0,1" newline bitfld.long 0x0 5. "RXNEIE,RXNE interrupt enable" "0,1" bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0,1" newline bitfld.long 0x0 3. "TE,Transmitter enable" "0,1" bitfld.long 0x0 2. "RE,Receiver enable" "0,1" newline bitfld.long 0x0 1. "UESM,USART enable in Stop mode" "0,1" bitfld.long 0x0 0. "UE,USART enable" "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "ISR_FIFO_enabled,USART interrupt and status register" bitfld.long 0x0 27. "TXFT,TXFIFO threshold flag" "0,1" bitfld.long 0x0 26. "RXFT,RXFIFO threshold flag" "0,1" newline bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time flag" "0,1" bitfld.long 0x0 24. "RXFF,RXFIFO Full" "0,1" newline bitfld.long 0x0 23. "TXFE,TXFIFO Empty" "0,1" bitfld.long 0x0 22. "REACK,REACK" "0,1" newline bitfld.long 0x0 21. "TEACK,TEACK" "0,1" bitfld.long 0x0 20. "WUF,WUF" "0,1" newline bitfld.long 0x0 19. "RWU,RWU" "0,1" bitfld.long 0x0 18. "SBKF,SBKF" "0,1" newline bitfld.long 0x0 17. "CMF,CMF" "0,1" bitfld.long 0x0 16. "BUSY,BUSY" "0,1" newline bitfld.long 0x0 15. "ABRF,ABRF" "0,1" bitfld.long 0x0 14. "ABRE,ABRE" "0,1" newline bitfld.long 0x0 13. "UDR,SPI slave underrun error flag" "0,1" bitfld.long 0x0 12. "EOBF,EOBF" "0,1" newline bitfld.long 0x0 11. "RTOF,RTOF" "0,1" bitfld.long 0x0 10. "CTS,CTS" "0,1" newline bitfld.long 0x0 9. "CTSIF,CTSIF" "0,1" bitfld.long 0x0 8. "LBDF,LBDF" "0,1" newline bitfld.long 0x0 7. "TXE,TXE" "0,1" bitfld.long 0x0 6. "TC,TC" "0,1" newline bitfld.long 0x0 5. "RXNE,RXNE" "0,1" bitfld.long 0x0 4. "IDLE,IDLE" "0,1" newline bitfld.long 0x0 3. "ORE,ORE" "0,1" bitfld.long 0x0 2. "NF,NF" "0,1" newline bitfld.long 0x0 1. "FE,FE" "0,1" bitfld.long 0x0 0. "PE,PE" "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "ISR_FIFO_disabled,USART interrupt and status register" bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time flag" "0,1" bitfld.long 0x0 22. "REACK,REACK" "0,1" newline bitfld.long 0x0 21. "TEACK,TEACK" "0,1" bitfld.long 0x0 20. "WUF,WUF" "0,1" newline bitfld.long 0x0 19. "RWU,RWU" "0,1" bitfld.long 0x0 18. "SBKF,SBKF" "0,1" newline bitfld.long 0x0 17. "CMF,CMF" "0,1" bitfld.long 0x0 16. "BUSY,BUSY" "0,1" newline bitfld.long 0x0 15. "ABRF,ABRF" "0,1" bitfld.long 0x0 14. "ABRE,ABRE" "0,1" newline bitfld.long 0x0 13. "UDR,SPI slave underrun error flag" "0,1" bitfld.long 0x0 12. "EOBF,EOBF" "0,1" newline bitfld.long 0x0 11. "RTOF,RTOF" "0,1" bitfld.long 0x0 10. "CTS,CTS" "0,1" newline bitfld.long 0x0 9. "CTSIF,CTSIF" "0,1" bitfld.long 0x0 8. "LBDF,LBDF" "0,1" newline bitfld.long 0x0 7. "TXE,TXE" "0,1" bitfld.long 0x0 6. "TC,TC" "0,1" newline bitfld.long 0x0 5. "RXNE,RXNE" "0,1" bitfld.long 0x0 4. "IDLE,IDLE" "0,1" newline bitfld.long 0x0 3. "ORE,ORE" "0,1" bitfld.long 0x0 2. "NF,NF" "0,1" newline bitfld.long 0x0 1. "FE,FE" "0,1" bitfld.long 0x0 0. "PE,PE" "0,1" endif sif (cpuis("STM32MP151*")) group.long 0x0++0x3 line.long 0x0 "CR1,Control register 1" bitfld.long 0x0 31. "RXFFIE,RXFIFO Full interrupt enable" "0,1" bitfld.long 0x0 30. "TXFEIE,TXFIFO empty interrupt enable" "0,1" newline bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0,1" bitfld.long 0x0 28. "M1,Word length" "0,1" newline bitfld.long 0x0 27. "EOBIE,End of Block interrupt enable" "0,1" bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0,1" newline hexmask.long.byte 0x0 21.--25. 1. "DEAT,DEAT" hexmask.long.byte 0x0 16.--20. 1. "DEDT,DEDT" newline bitfld.long 0x0 15. "OVER8,Oversampling mode" "0,1" bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0,1" newline bitfld.long 0x0 13. "MME,Mute mode enable" "0,1" bitfld.long 0x0 12. "M0,Word length" "0,1" newline bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0,1" bitfld.long 0x0 10. "PCE,Parity control enable" "0,1" newline bitfld.long 0x0 9. "PS,Parity selection" "0,1" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0,1" newline bitfld.long 0x0 7. "TXEIE,interrupt enable" "0,1" bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0,1" newline bitfld.long 0x0 5. "RXNEIE,RXNE interrupt enable" "0,1" bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0,1" newline bitfld.long 0x0 3. "TE,Transmitter enable" "0,1" bitfld.long 0x0 2. "RE,Receiver enable" "0,1" newline bitfld.long 0x0 1. "UESM,USART enable in Stop mode" "0,1" bitfld.long 0x0 0. "UE,USART enable" "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "ISR,Interrupt & status register" bitfld.long 0x0 27. "TXFT,TXFIFO threshold flag" "0,1" bitfld.long 0x0 26. "RXFT,RXFIFO threshold flag" "0,1" newline bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time flag" "0,1" bitfld.long 0x0 24. "RXFF,RXFIFO Full" "0,1" newline bitfld.long 0x0 23. "TXFE,TXFIFO Empty" "0,1" bitfld.long 0x0 22. "REACK,REACK" "0,1" newline bitfld.long 0x0 21. "TEACK,TEACK" "0,1" bitfld.long 0x0 20. "WUF,WUF" "0,1" newline bitfld.long 0x0 19. "RWU,RWU" "0,1" bitfld.long 0x0 18. "SBKF,SBKF" "0,1" newline bitfld.long 0x0 17. "CMF,CMF" "0,1" bitfld.long 0x0 16. "BUSY,BUSY" "0,1" newline bitfld.long 0x0 15. "ABRF,ABRF" "0,1" bitfld.long 0x0 14. "ABRE,ABRE" "0,1" newline bitfld.long 0x0 13. "UDR,SPI slave underrun error flag" "0,1" bitfld.long 0x0 12. "EOBF,EOBF" "0,1" newline bitfld.long 0x0 11. "RTOF,RTOF" "0,1" bitfld.long 0x0 10. "CTS,CTS" "0,1" newline bitfld.long 0x0 9. "CTSIF,CTSIF" "0,1" bitfld.long 0x0 8. "LBDF,LBDF" "0,1" newline bitfld.long 0x0 7. "TXE,TXE" "0,1" bitfld.long 0x0 6. "TC,TC" "0,1" newline bitfld.long 0x0 5. "RXNE,RXNE" "0,1" bitfld.long 0x0 4. "IDLE,IDLE" "0,1" newline bitfld.long 0x0 3. "ORE,ORE" "0,1" bitfld.long 0x0 2. "NF,NF" "0,1" newline bitfld.long 0x0 1. "FE,FE" "0,1" bitfld.long 0x0 0. "PE,PE" "0,1" endif group.long 0x4++0x13 line.long 0x0 "CR2,Control register 2" hexmask.long.byte 0x0 28.--31. 1. "ADD4_7,Address of the USART node" hexmask.long.byte 0x0 24.--27. 1. "ADD0_3,Address of the USART node" bitfld.long 0x0 23. "RTOEN,Receiver timeout enable" "0,1" bitfld.long 0x0 21.--22. "ABRMOD,Auto baud rate mode" "0,1,2,3" bitfld.long 0x0 20. "ABREN,Auto baud rate enable" "0,1" bitfld.long 0x0 19. "MSBFIRST,Most significant bit first" "0,1" bitfld.long 0x0 18. "TAINV,Binary data inversion" "0,1" bitfld.long 0x0 17. "TXINV,TX pin active level inversion" "0,1" newline bitfld.long 0x0 16. "RXINV,RX pin active level inversion" "0,1" bitfld.long 0x0 15. "SWAP,Swap TX/RX pins" "0,1" bitfld.long 0x0 14. "LINEN,LIN mode enable" "0,1" bitfld.long 0x0 12.--13. "STOP,STOP bits" "0,1,2,3" bitfld.long 0x0 11. "CLKEN,Clock enable" "0,1" bitfld.long 0x0 10. "CPOL,Clock polarity" "0,1" bitfld.long 0x0 9. "CPHA,Clock phase" "0,1" bitfld.long 0x0 8. "LBCL,Last bit clock pulse" "0,1" newline bitfld.long 0x0 6. "LBDIE,LIN break detection interrupt enable" "0,1" bitfld.long 0x0 5. "LBDL,LIN break detection length" "0,1" bitfld.long 0x0 4. "ADDM7,7-bit Address Detection/4-bit Address Detection" "0,1" bitfld.long 0x0 3. "DIS_NSS,When the DSI_NSS bit is set the NSS pin input will be ignored" "0,1" bitfld.long 0x0 0. "SLVEN,Synchronous Slave mode enable" "0,1" line.long 0x4 "CR3,Control register 3" bitfld.long 0x4 29.--31. "TXFTCFG,TXFIFO threshold configuration" "0,1,2,3,4,5,6,7" bitfld.long 0x4 28. "RXFTIE,RXFIFO threshold interrupt enable" "0,1" bitfld.long 0x4 25.--27. "RXFTCFG,Receive FIFO threshold configuration" "0,1,2,3,4,5,6,7" bitfld.long 0x4 24. "TCBGTIE,Tr Complete before guard time interrupt enable" "0,1" bitfld.long 0x4 23. "TXFTIE,threshold interrupt enable" "0,1" bitfld.long 0x4 22. "WUFIE,Wakeup from Stop mode interrupt enable" "0,1" bitfld.long 0x4 20.--21. "WUS,Wakeup from Stop mode interrupt flag selection" "0,1,2,3" bitfld.long 0x4 17.--19. "SCARCNT,Smartcard auto-retry count" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 15. "DEP,Driver enable polarity selection" "0,1" bitfld.long 0x4 14. "DEM,Driver enable mode" "0,1" bitfld.long 0x4 13. "DDRE,DMA Disable on Reception Error" "0,1" bitfld.long 0x4 12. "OVRDIS,Overrun Disable" "0,1" bitfld.long 0x4 11. "ONEBIT,One sample bit method enable" "0,1" bitfld.long 0x4 10. "CTSIE,CTS interrupt enable" "0,1" bitfld.long 0x4 9. "CTSE,CTS enable" "0,1" bitfld.long 0x4 8. "RTSE,RTS enable" "0,1" newline bitfld.long 0x4 7. "DMAT,DMA enable transmitter" "0,1" bitfld.long 0x4 6. "DMAR,DMA enable receiver" "0,1" bitfld.long 0x4 5. "SCEN,Smartcard mode enable" "0,1" bitfld.long 0x4 4. "NACK,Smartcard NACK enable" "0,1" bitfld.long 0x4 3. "HDSEL,Half-duplex selection" "0,1" bitfld.long 0x4 2. "IRLP,Ir low-power" "0,1" bitfld.long 0x4 1. "IREN,Ir mode enable" "0,1" bitfld.long 0x4 0. "EIE,Error interrupt enable" "0,1" line.long 0x8 "BRR,Baud rate register" hexmask.long.word 0x8 4.--15. 1. "BRR_4_15,BRR_4_15" hexmask.long.byte 0x8 0.--3. 1. "BRR_0_3,BRR_0_3" line.long 0xC "GTPR,Guard time and prescaler register" hexmask.long.byte 0xC 8.--15. 1. "GT,Guard time value" hexmask.long.byte 0xC 0.--7. 1. "PSC,Prescaler value" line.long 0x10 "RTOR,Receiver timeout register" hexmask.long.byte 0x10 24.--31. 1. "BLEN,Block Length" hexmask.long.tbyte 0x10 0.--23. 1. "RTO,Receiver timeout value" wgroup.long 0x18++0x3 line.long 0x0 "RQR,Request register" bitfld.long 0x0 4. "TXFRQ,Transmit data flush request" "0,1" bitfld.long 0x0 3. "RXFRQ,Receive data flush request" "0,1" bitfld.long 0x0 2. "MMRQ,Mute mode request" "0,1" bitfld.long 0x0 1. "SBKRQ,Send break request" "0,1" bitfld.long 0x0 0. "ABRRQ,Auto baud rate request" "0,1" wgroup.long 0x20++0x3 line.long 0x0 "ICR,Interrupt flag clear register" bitfld.long 0x0 20. "WUCF,Wakeup from Stop mode clear flag" "0,1" bitfld.long 0x0 17. "CMCF,Character match clear flag" "0,1" bitfld.long 0x0 13. "UDRCF,SPI slave underrun clear flag" "0,1" bitfld.long 0x0 12. "EOBCF,End of block clear flag" "0,1" bitfld.long 0x0 11. "RTOCF,Receiver timeout clear flag" "0,1" bitfld.long 0x0 9. "CTSCF,CTS clear flag" "0,1" bitfld.long 0x0 8. "LBDCF,LIN break detection clear flag" "0,1" bitfld.long 0x0 7. "TCBGTCF,Transmission complete before Guard time clear flag" "0,1" newline bitfld.long 0x0 6. "TCCF,Transmission complete clear flag" "0,1" bitfld.long 0x0 5. "TXFECF,TXFIFO empty clear flag" "0,1" bitfld.long 0x0 4. "IDLECF,Idle line detected clear flag" "0,1" bitfld.long 0x0 3. "ORECF,Overrun error clear flag" "0,1" bitfld.long 0x0 2. "NCF,Noise detected clear flag" "0,1" bitfld.long 0x0 1. "FECF,Framing error clear flag" "0,1" bitfld.long 0x0 0. "PECF,Parity error clear flag" "0,1" rgroup.long 0x24++0x3 line.long 0x0 "RDR,Receive data register" hexmask.long.word 0x0 0.--8. 1. "RDR,Receive data value" group.long 0x28++0x7 line.long 0x0 "TDR,Transmit data register" hexmask.long.word 0x0 0.--8. 1. "TDR,Transmit data value" line.long 0x4 "PRESC,Prescaler register" hexmask.long.byte 0x4 0.--3. 1. "PRESCALER,Clock prescaler" rgroup.long 0x3EC++0x13 line.long 0x0 "HWCFGR2,USART Hardware Configuration register 2" hexmask.long.byte 0x0 4.--7. 1. "CFG2,CFG2" hexmask.long.byte 0x0 0.--3. 1. "CFG1,CFG1" line.long 0x4 "HWCFGR1,USART Hardware Configuration register 1" hexmask.long.byte 0x4 28.--31. 1. "CFG8,CFG8" hexmask.long.byte 0x4 24.--27. 1. "CFG7,CFG7" hexmask.long.byte 0x4 20.--23. 1. "CFG6,CFG6" hexmask.long.byte 0x4 16.--19. 1. "CFG5,CFG5" hexmask.long.byte 0x4 12.--15. 1. "CFG4,CFG4" hexmask.long.byte 0x4 8.--11. 1. "CFG3,CFG3" hexmask.long.byte 0x4 4.--7. 1. "CFG2,CFG2" hexmask.long.byte 0x4 0.--3. 1. "CFG1,CFG1" line.long 0x8 "VERR,EXTI IP Version register" hexmask.long.byte 0x8 4.--7. 1. "MAJREV,Major Revision number" hexmask.long.byte 0x8 0.--3. 1. "MINREV,Minor Revision number" line.long 0xC "IPIDR,EXTI Identification register" hexmask.long 0xC 0.--31. 1. "IPID,IP Identification" line.long 0x10 "SIDR,EXTI Size ID register" hexmask.long 0x10 0.--31. 1. "SID,Size Identification" tree.end endif sif (cpuis("STM32MP13*")||cpuis("STM32MP151*")) tree "USART7" base ad:0x40018000 sif (cpuis("STM32MP13*")) group.long 0x0++0x3 line.long 0x0 "CR1_FIFO_enabled,Control register 1" bitfld.long 0x0 31. "RXFFIE,RXFIFO Full interrupt enable" "0,1" bitfld.long 0x0 30. "TXFEIE,TXFIFO empty interrupt enable" "0,1" newline bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0,1" bitfld.long 0x0 28. "M1,Word length" "0,1" newline bitfld.long 0x0 27. "EOBIE,End of Block interrupt enable" "0,1" bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0,1" newline hexmask.long.byte 0x0 21.--25. 1. "DEAT,DEAT" hexmask.long.byte 0x0 16.--20. 1. "DEDT,DEDT" newline bitfld.long 0x0 15. "OVER8,Oversampling mode" "0,1" bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0,1" newline bitfld.long 0x0 13. "MME,Mute mode enable" "0,1" bitfld.long 0x0 12. "M0,Word length" "0,1" newline bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0,1" bitfld.long 0x0 10. "PCE,Parity control enable" "0,1" newline bitfld.long 0x0 9. "PS,Parity selection" "0,1" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0,1" newline bitfld.long 0x0 7. "TXEIE,interrupt enable" "0,1" bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0,1" newline bitfld.long 0x0 5. "RXNEIE,RXNE interrupt enable" "0,1" bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0,1" newline bitfld.long 0x0 3. "TE,Transmitter enable" "0,1" bitfld.long 0x0 2. "RE,Receiver enable" "0,1" newline bitfld.long 0x0 1. "UESM,USART enable in Stop mode" "0,1" bitfld.long 0x0 0. "UE,USART enable" "0,1" group.long 0x0++0x3 line.long 0x0 "CR1_FIFO_disabled,Control register 1" bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0,1" bitfld.long 0x0 28. "M1,Word length" "0,1" newline bitfld.long 0x0 27. "EOBIE,End of Block interrupt enable" "0,1" bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0,1" newline hexmask.long.byte 0x0 21.--25. 1. "DEAT,DEAT" hexmask.long.byte 0x0 16.--20. 1. "DEDT,DEDT" newline bitfld.long 0x0 15. "OVER8,Oversampling mode" "0,1" bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0,1" newline bitfld.long 0x0 13. "MME,Mute mode enable" "0,1" bitfld.long 0x0 12. "M0,Word length" "0,1" newline bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0,1" bitfld.long 0x0 10. "PCE,Parity control enable" "0,1" newline bitfld.long 0x0 9. "PS,Parity selection" "0,1" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0,1" newline bitfld.long 0x0 7. "TXEIE,interrupt enable" "0,1" bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0,1" newline bitfld.long 0x0 5. "RXNEIE,RXNE interrupt enable" "0,1" bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0,1" newline bitfld.long 0x0 3. "TE,Transmitter enable" "0,1" bitfld.long 0x0 2. "RE,Receiver enable" "0,1" newline bitfld.long 0x0 1. "UESM,USART enable in Stop mode" "0,1" bitfld.long 0x0 0. "UE,USART enable" "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "ISR_FIFO_enabled,USART interrupt and status register" bitfld.long 0x0 27. "TXFT,TXFIFO threshold flag" "0,1" bitfld.long 0x0 26. "RXFT,RXFIFO threshold flag" "0,1" newline bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time flag" "0,1" bitfld.long 0x0 24. "RXFF,RXFIFO Full" "0,1" newline bitfld.long 0x0 23. "TXFE,TXFIFO Empty" "0,1" bitfld.long 0x0 22. "REACK,REACK" "0,1" newline bitfld.long 0x0 21. "TEACK,TEACK" "0,1" bitfld.long 0x0 20. "WUF,WUF" "0,1" newline bitfld.long 0x0 19. "RWU,RWU" "0,1" bitfld.long 0x0 18. "SBKF,SBKF" "0,1" newline bitfld.long 0x0 17. "CMF,CMF" "0,1" bitfld.long 0x0 16. "BUSY,BUSY" "0,1" newline bitfld.long 0x0 15. "ABRF,ABRF" "0,1" bitfld.long 0x0 14. "ABRE,ABRE" "0,1" newline bitfld.long 0x0 13. "UDR,SPI slave underrun error flag" "0,1" bitfld.long 0x0 12. "EOBF,EOBF" "0,1" newline bitfld.long 0x0 11. "RTOF,RTOF" "0,1" bitfld.long 0x0 10. "CTS,CTS" "0,1" newline bitfld.long 0x0 9. "CTSIF,CTSIF" "0,1" bitfld.long 0x0 8. "LBDF,LBDF" "0,1" newline bitfld.long 0x0 7. "TXE,TXE" "0,1" bitfld.long 0x0 6. "TC,TC" "0,1" newline bitfld.long 0x0 5. "RXNE,RXNE" "0,1" bitfld.long 0x0 4. "IDLE,IDLE" "0,1" newline bitfld.long 0x0 3. "ORE,ORE" "0,1" bitfld.long 0x0 2. "NF,NF" "0,1" newline bitfld.long 0x0 1. "FE,FE" "0,1" bitfld.long 0x0 0. "PE,PE" "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "ISR_FIFO_disabled,USART interrupt and status register" bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time flag" "0,1" bitfld.long 0x0 22. "REACK,REACK" "0,1" newline bitfld.long 0x0 21. "TEACK,TEACK" "0,1" bitfld.long 0x0 20. "WUF,WUF" "0,1" newline bitfld.long 0x0 19. "RWU,RWU" "0,1" bitfld.long 0x0 18. "SBKF,SBKF" "0,1" newline bitfld.long 0x0 17. "CMF,CMF" "0,1" bitfld.long 0x0 16. "BUSY,BUSY" "0,1" newline bitfld.long 0x0 15. "ABRF,ABRF" "0,1" bitfld.long 0x0 14. "ABRE,ABRE" "0,1" newline bitfld.long 0x0 13. "UDR,SPI slave underrun error flag" "0,1" bitfld.long 0x0 12. "EOBF,EOBF" "0,1" newline bitfld.long 0x0 11. "RTOF,RTOF" "0,1" bitfld.long 0x0 10. "CTS,CTS" "0,1" newline bitfld.long 0x0 9. "CTSIF,CTSIF" "0,1" bitfld.long 0x0 8. "LBDF,LBDF" "0,1" newline bitfld.long 0x0 7. "TXE,TXE" "0,1" bitfld.long 0x0 6. "TC,TC" "0,1" newline bitfld.long 0x0 5. "RXNE,RXNE" "0,1" bitfld.long 0x0 4. "IDLE,IDLE" "0,1" newline bitfld.long 0x0 3. "ORE,ORE" "0,1" bitfld.long 0x0 2. "NF,NF" "0,1" newline bitfld.long 0x0 1. "FE,FE" "0,1" bitfld.long 0x0 0. "PE,PE" "0,1" endif sif (cpuis("STM32MP151*")) group.long 0x0++0x3 line.long 0x0 "CR1,Control register 1" bitfld.long 0x0 31. "RXFFIE,RXFIFO Full interrupt enable" "0,1" bitfld.long 0x0 30. "TXFEIE,TXFIFO empty interrupt enable" "0,1" newline bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0,1" bitfld.long 0x0 28. "M1,Word length" "0,1" newline bitfld.long 0x0 27. "EOBIE,End of Block interrupt enable" "0,1" bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0,1" newline hexmask.long.byte 0x0 21.--25. 1. "DEAT,DEAT" hexmask.long.byte 0x0 16.--20. 1. "DEDT,DEDT" newline bitfld.long 0x0 15. "OVER8,Oversampling mode" "0,1" bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0,1" newline bitfld.long 0x0 13. "MME,Mute mode enable" "0,1" bitfld.long 0x0 12. "M0,Word length" "0,1" newline bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0,1" bitfld.long 0x0 10. "PCE,Parity control enable" "0,1" newline bitfld.long 0x0 9. "PS,Parity selection" "0,1" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0,1" newline bitfld.long 0x0 7. "TXEIE,interrupt enable" "0,1" bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0,1" newline bitfld.long 0x0 5. "RXNEIE,RXNE interrupt enable" "0,1" bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0,1" newline bitfld.long 0x0 3. "TE,Transmitter enable" "0,1" bitfld.long 0x0 2. "RE,Receiver enable" "0,1" newline bitfld.long 0x0 1. "UESM,USART enable in Stop mode" "0,1" bitfld.long 0x0 0. "UE,USART enable" "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "ISR,Interrupt & status register" bitfld.long 0x0 27. "TXFT,TXFIFO threshold flag" "0,1" bitfld.long 0x0 26. "RXFT,RXFIFO threshold flag" "0,1" newline bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time flag" "0,1" bitfld.long 0x0 24. "RXFF,RXFIFO Full" "0,1" newline bitfld.long 0x0 23. "TXFE,TXFIFO Empty" "0,1" bitfld.long 0x0 22. "REACK,REACK" "0,1" newline bitfld.long 0x0 21. "TEACK,TEACK" "0,1" bitfld.long 0x0 20. "WUF,WUF" "0,1" newline bitfld.long 0x0 19. "RWU,RWU" "0,1" bitfld.long 0x0 18. "SBKF,SBKF" "0,1" newline bitfld.long 0x0 17. "CMF,CMF" "0,1" bitfld.long 0x0 16. "BUSY,BUSY" "0,1" newline bitfld.long 0x0 15. "ABRF,ABRF" "0,1" bitfld.long 0x0 14. "ABRE,ABRE" "0,1" newline bitfld.long 0x0 13. "UDR,SPI slave underrun error flag" "0,1" bitfld.long 0x0 12. "EOBF,EOBF" "0,1" newline bitfld.long 0x0 11. "RTOF,RTOF" "0,1" bitfld.long 0x0 10. "CTS,CTS" "0,1" newline bitfld.long 0x0 9. "CTSIF,CTSIF" "0,1" bitfld.long 0x0 8. "LBDF,LBDF" "0,1" newline bitfld.long 0x0 7. "TXE,TXE" "0,1" bitfld.long 0x0 6. "TC,TC" "0,1" newline bitfld.long 0x0 5. "RXNE,RXNE" "0,1" bitfld.long 0x0 4. "IDLE,IDLE" "0,1" newline bitfld.long 0x0 3. "ORE,ORE" "0,1" bitfld.long 0x0 2. "NF,NF" "0,1" newline bitfld.long 0x0 1. "FE,FE" "0,1" bitfld.long 0x0 0. "PE,PE" "0,1" endif group.long 0x4++0x13 line.long 0x0 "CR2,Control register 2" hexmask.long.byte 0x0 28.--31. 1. "ADD4_7,Address of the USART node" hexmask.long.byte 0x0 24.--27. 1. "ADD0_3,Address of the USART node" bitfld.long 0x0 23. "RTOEN,Receiver timeout enable" "0,1" bitfld.long 0x0 21.--22. "ABRMOD,Auto baud rate mode" "0,1,2,3" bitfld.long 0x0 20. "ABREN,Auto baud rate enable" "0,1" bitfld.long 0x0 19. "MSBFIRST,Most significant bit first" "0,1" bitfld.long 0x0 18. "TAINV,Binary data inversion" "0,1" bitfld.long 0x0 17. "TXINV,TX pin active level inversion" "0,1" newline bitfld.long 0x0 16. "RXINV,RX pin active level inversion" "0,1" bitfld.long 0x0 15. "SWAP,Swap TX/RX pins" "0,1" bitfld.long 0x0 14. "LINEN,LIN mode enable" "0,1" bitfld.long 0x0 12.--13. "STOP,STOP bits" "0,1,2,3" bitfld.long 0x0 11. "CLKEN,Clock enable" "0,1" bitfld.long 0x0 10. "CPOL,Clock polarity" "0,1" bitfld.long 0x0 9. "CPHA,Clock phase" "0,1" bitfld.long 0x0 8. "LBCL,Last bit clock pulse" "0,1" newline bitfld.long 0x0 6. "LBDIE,LIN break detection interrupt enable" "0,1" bitfld.long 0x0 5. "LBDL,LIN break detection length" "0,1" bitfld.long 0x0 4. "ADDM7,7-bit Address Detection/4-bit Address Detection" "0,1" bitfld.long 0x0 3. "DIS_NSS,When the DSI_NSS bit is set the NSS pin input will be ignored" "0,1" bitfld.long 0x0 0. "SLVEN,Synchronous Slave mode enable" "0,1" line.long 0x4 "CR3,Control register 3" bitfld.long 0x4 29.--31. "TXFTCFG,TXFIFO threshold configuration" "0,1,2,3,4,5,6,7" bitfld.long 0x4 28. "RXFTIE,RXFIFO threshold interrupt enable" "0,1" bitfld.long 0x4 25.--27. "RXFTCFG,Receive FIFO threshold configuration" "0,1,2,3,4,5,6,7" bitfld.long 0x4 24. "TCBGTIE,Tr Complete before guard time interrupt enable" "0,1" bitfld.long 0x4 23. "TXFTIE,threshold interrupt enable" "0,1" bitfld.long 0x4 22. "WUFIE,Wakeup from Stop mode interrupt enable" "0,1" bitfld.long 0x4 20.--21. "WUS,Wakeup from Stop mode interrupt flag selection" "0,1,2,3" bitfld.long 0x4 17.--19. "SCARCNT,Smartcard auto-retry count" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 15. "DEP,Driver enable polarity selection" "0,1" bitfld.long 0x4 14. "DEM,Driver enable mode" "0,1" bitfld.long 0x4 13. "DDRE,DMA Disable on Reception Error" "0,1" bitfld.long 0x4 12. "OVRDIS,Overrun Disable" "0,1" bitfld.long 0x4 11. "ONEBIT,One sample bit method enable" "0,1" bitfld.long 0x4 10. "CTSIE,CTS interrupt enable" "0,1" bitfld.long 0x4 9. "CTSE,CTS enable" "0,1" bitfld.long 0x4 8. "RTSE,RTS enable" "0,1" newline bitfld.long 0x4 7. "DMAT,DMA enable transmitter" "0,1" bitfld.long 0x4 6. "DMAR,DMA enable receiver" "0,1" bitfld.long 0x4 5. "SCEN,Smartcard mode enable" "0,1" bitfld.long 0x4 4. "NACK,Smartcard NACK enable" "0,1" bitfld.long 0x4 3. "HDSEL,Half-duplex selection" "0,1" bitfld.long 0x4 2. "IRLP,Ir low-power" "0,1" bitfld.long 0x4 1. "IREN,Ir mode enable" "0,1" bitfld.long 0x4 0. "EIE,Error interrupt enable" "0,1" line.long 0x8 "BRR,Baud rate register" hexmask.long.word 0x8 4.--15. 1. "BRR_4_15,BRR_4_15" hexmask.long.byte 0x8 0.--3. 1. "BRR_0_3,BRR_0_3" line.long 0xC "GTPR,Guard time and prescaler register" hexmask.long.byte 0xC 8.--15. 1. "GT,Guard time value" hexmask.long.byte 0xC 0.--7. 1. "PSC,Prescaler value" line.long 0x10 "RTOR,Receiver timeout register" hexmask.long.byte 0x10 24.--31. 1. "BLEN,Block Length" hexmask.long.tbyte 0x10 0.--23. 1. "RTO,Receiver timeout value" wgroup.long 0x18++0x3 line.long 0x0 "RQR,Request register" bitfld.long 0x0 4. "TXFRQ,Transmit data flush request" "0,1" bitfld.long 0x0 3. "RXFRQ,Receive data flush request" "0,1" bitfld.long 0x0 2. "MMRQ,Mute mode request" "0,1" bitfld.long 0x0 1. "SBKRQ,Send break request" "0,1" bitfld.long 0x0 0. "ABRRQ,Auto baud rate request" "0,1" wgroup.long 0x20++0x3 line.long 0x0 "ICR,Interrupt flag clear register" bitfld.long 0x0 20. "WUCF,Wakeup from Stop mode clear flag" "0,1" bitfld.long 0x0 17. "CMCF,Character match clear flag" "0,1" bitfld.long 0x0 13. "UDRCF,SPI slave underrun clear flag" "0,1" bitfld.long 0x0 12. "EOBCF,End of block clear flag" "0,1" bitfld.long 0x0 11. "RTOCF,Receiver timeout clear flag" "0,1" bitfld.long 0x0 9. "CTSCF,CTS clear flag" "0,1" bitfld.long 0x0 8. "LBDCF,LIN break detection clear flag" "0,1" bitfld.long 0x0 7. "TCBGTCF,Transmission complete before Guard time clear flag" "0,1" newline bitfld.long 0x0 6. "TCCF,Transmission complete clear flag" "0,1" bitfld.long 0x0 5. "TXFECF,TXFIFO empty clear flag" "0,1" bitfld.long 0x0 4. "IDLECF,Idle line detected clear flag" "0,1" bitfld.long 0x0 3. "ORECF,Overrun error clear flag" "0,1" bitfld.long 0x0 2. "NCF,Noise detected clear flag" "0,1" bitfld.long 0x0 1. "FECF,Framing error clear flag" "0,1" bitfld.long 0x0 0. "PECF,Parity error clear flag" "0,1" rgroup.long 0x24++0x3 line.long 0x0 "RDR,Receive data register" hexmask.long.word 0x0 0.--8. 1. "RDR,Receive data value" group.long 0x28++0x7 line.long 0x0 "TDR,Transmit data register" hexmask.long.word 0x0 0.--8. 1. "TDR,Transmit data value" line.long 0x4 "PRESC,Prescaler register" hexmask.long.byte 0x4 0.--3. 1. "PRESCALER,Clock prescaler" rgroup.long 0x3EC++0x13 line.long 0x0 "HWCFGR2,USART Hardware Configuration register 2" hexmask.long.byte 0x0 4.--7. 1. "CFG2,CFG2" hexmask.long.byte 0x0 0.--3. 1. "CFG1,CFG1" line.long 0x4 "HWCFGR1,USART Hardware Configuration register 1" hexmask.long.byte 0x4 28.--31. 1. "CFG8,CFG8" hexmask.long.byte 0x4 24.--27. 1. "CFG7,CFG7" hexmask.long.byte 0x4 20.--23. 1. "CFG6,CFG6" hexmask.long.byte 0x4 16.--19. 1. "CFG5,CFG5" hexmask.long.byte 0x4 12.--15. 1. "CFG4,CFG4" hexmask.long.byte 0x4 8.--11. 1. "CFG3,CFG3" hexmask.long.byte 0x4 4.--7. 1. "CFG2,CFG2" hexmask.long.byte 0x4 0.--3. 1. "CFG1,CFG1" line.long 0x8 "VERR,EXTI IP Version register" hexmask.long.byte 0x8 4.--7. 1. "MAJREV,Major Revision number" hexmask.long.byte 0x8 0.--3. 1. "MINREV,Minor Revision number" line.long 0xC "IPIDR,EXTI Identification register" hexmask.long 0xC 0.--31. 1. "IPID,IP Identification" line.long 0x10 "SIDR,EXTI Size ID register" hexmask.long 0x10 0.--31. 1. "SID,Size Identification" tree.end endif sif (cpuis("STM32MP13*")||cpuis("STM32MP151*")) tree "USART8" base ad:0x40019000 sif (cpuis("STM32MP13*")) group.long 0x0++0x3 line.long 0x0 "CR1_FIFO_enabled,Control register 1" bitfld.long 0x0 31. "RXFFIE,RXFIFO Full interrupt enable" "0,1" bitfld.long 0x0 30. "TXFEIE,TXFIFO empty interrupt enable" "0,1" newline bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0,1" bitfld.long 0x0 28. "M1,Word length" "0,1" newline bitfld.long 0x0 27. "EOBIE,End of Block interrupt enable" "0,1" bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0,1" newline hexmask.long.byte 0x0 21.--25. 1. "DEAT,DEAT" hexmask.long.byte 0x0 16.--20. 1. "DEDT,DEDT" newline bitfld.long 0x0 15. "OVER8,Oversampling mode" "0,1" bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0,1" newline bitfld.long 0x0 13. "MME,Mute mode enable" "0,1" bitfld.long 0x0 12. "M0,Word length" "0,1" newline bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0,1" bitfld.long 0x0 10. "PCE,Parity control enable" "0,1" newline bitfld.long 0x0 9. "PS,Parity selection" "0,1" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0,1" newline bitfld.long 0x0 7. "TXEIE,interrupt enable" "0,1" bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0,1" newline bitfld.long 0x0 5. "RXNEIE,RXNE interrupt enable" "0,1" bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0,1" newline bitfld.long 0x0 3. "TE,Transmitter enable" "0,1" bitfld.long 0x0 2. "RE,Receiver enable" "0,1" newline bitfld.long 0x0 1. "UESM,USART enable in Stop mode" "0,1" bitfld.long 0x0 0. "UE,USART enable" "0,1" group.long 0x0++0x3 line.long 0x0 "CR1_FIFO_disabled,Control register 1" bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0,1" bitfld.long 0x0 28. "M1,Word length" "0,1" newline bitfld.long 0x0 27. "EOBIE,End of Block interrupt enable" "0,1" bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0,1" newline hexmask.long.byte 0x0 21.--25. 1. "DEAT,DEAT" hexmask.long.byte 0x0 16.--20. 1. "DEDT,DEDT" newline bitfld.long 0x0 15. "OVER8,Oversampling mode" "0,1" bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0,1" newline bitfld.long 0x0 13. "MME,Mute mode enable" "0,1" bitfld.long 0x0 12. "M0,Word length" "0,1" newline bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0,1" bitfld.long 0x0 10. "PCE,Parity control enable" "0,1" newline bitfld.long 0x0 9. "PS,Parity selection" "0,1" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0,1" newline bitfld.long 0x0 7. "TXEIE,interrupt enable" "0,1" bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0,1" newline bitfld.long 0x0 5. "RXNEIE,RXNE interrupt enable" "0,1" bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0,1" newline bitfld.long 0x0 3. "TE,Transmitter enable" "0,1" bitfld.long 0x0 2. "RE,Receiver enable" "0,1" newline bitfld.long 0x0 1. "UESM,USART enable in Stop mode" "0,1" bitfld.long 0x0 0. "UE,USART enable" "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "ISR_FIFO_enabled,USART interrupt and status register" bitfld.long 0x0 27. "TXFT,TXFIFO threshold flag" "0,1" bitfld.long 0x0 26. "RXFT,RXFIFO threshold flag" "0,1" newline bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time flag" "0,1" bitfld.long 0x0 24. "RXFF,RXFIFO Full" "0,1" newline bitfld.long 0x0 23. "TXFE,TXFIFO Empty" "0,1" bitfld.long 0x0 22. "REACK,REACK" "0,1" newline bitfld.long 0x0 21. "TEACK,TEACK" "0,1" bitfld.long 0x0 20. "WUF,WUF" "0,1" newline bitfld.long 0x0 19. "RWU,RWU" "0,1" bitfld.long 0x0 18. "SBKF,SBKF" "0,1" newline bitfld.long 0x0 17. "CMF,CMF" "0,1" bitfld.long 0x0 16. "BUSY,BUSY" "0,1" newline bitfld.long 0x0 15. "ABRF,ABRF" "0,1" bitfld.long 0x0 14. "ABRE,ABRE" "0,1" newline bitfld.long 0x0 13. "UDR,SPI slave underrun error flag" "0,1" bitfld.long 0x0 12. "EOBF,EOBF" "0,1" newline bitfld.long 0x0 11. "RTOF,RTOF" "0,1" bitfld.long 0x0 10. "CTS,CTS" "0,1" newline bitfld.long 0x0 9. "CTSIF,CTSIF" "0,1" bitfld.long 0x0 8. "LBDF,LBDF" "0,1" newline bitfld.long 0x0 7. "TXE,TXE" "0,1" bitfld.long 0x0 6. "TC,TC" "0,1" newline bitfld.long 0x0 5. "RXNE,RXNE" "0,1" bitfld.long 0x0 4. "IDLE,IDLE" "0,1" newline bitfld.long 0x0 3. "ORE,ORE" "0,1" bitfld.long 0x0 2. "NF,NF" "0,1" newline bitfld.long 0x0 1. "FE,FE" "0,1" bitfld.long 0x0 0. "PE,PE" "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "ISR_FIFO_disabled,USART interrupt and status register" bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time flag" "0,1" bitfld.long 0x0 22. "REACK,REACK" "0,1" newline bitfld.long 0x0 21. "TEACK,TEACK" "0,1" bitfld.long 0x0 20. "WUF,WUF" "0,1" newline bitfld.long 0x0 19. "RWU,RWU" "0,1" bitfld.long 0x0 18. "SBKF,SBKF" "0,1" newline bitfld.long 0x0 17. "CMF,CMF" "0,1" bitfld.long 0x0 16. "BUSY,BUSY" "0,1" newline bitfld.long 0x0 15. "ABRF,ABRF" "0,1" bitfld.long 0x0 14. "ABRE,ABRE" "0,1" newline bitfld.long 0x0 13. "UDR,SPI slave underrun error flag" "0,1" bitfld.long 0x0 12. "EOBF,EOBF" "0,1" newline bitfld.long 0x0 11. "RTOF,RTOF" "0,1" bitfld.long 0x0 10. "CTS,CTS" "0,1" newline bitfld.long 0x0 9. "CTSIF,CTSIF" "0,1" bitfld.long 0x0 8. "LBDF,LBDF" "0,1" newline bitfld.long 0x0 7. "TXE,TXE" "0,1" bitfld.long 0x0 6. "TC,TC" "0,1" newline bitfld.long 0x0 5. "RXNE,RXNE" "0,1" bitfld.long 0x0 4. "IDLE,IDLE" "0,1" newline bitfld.long 0x0 3. "ORE,ORE" "0,1" bitfld.long 0x0 2. "NF,NF" "0,1" newline bitfld.long 0x0 1. "FE,FE" "0,1" bitfld.long 0x0 0. "PE,PE" "0,1" endif sif (cpuis("STM32MP151*")) group.long 0x0++0x3 line.long 0x0 "CR1,Control register 1" bitfld.long 0x0 31. "RXFFIE,RXFIFO Full interrupt enable" "0,1" bitfld.long 0x0 30. "TXFEIE,TXFIFO empty interrupt enable" "0,1" newline bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0,1" bitfld.long 0x0 28. "M1,Word length" "0,1" newline bitfld.long 0x0 27. "EOBIE,End of Block interrupt enable" "0,1" bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0,1" newline hexmask.long.byte 0x0 21.--25. 1. "DEAT,DEAT" hexmask.long.byte 0x0 16.--20. 1. "DEDT,DEDT" newline bitfld.long 0x0 15. "OVER8,Oversampling mode" "0,1" bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0,1" newline bitfld.long 0x0 13. "MME,Mute mode enable" "0,1" bitfld.long 0x0 12. "M0,Word length" "0,1" newline bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0,1" bitfld.long 0x0 10. "PCE,Parity control enable" "0,1" newline bitfld.long 0x0 9. "PS,Parity selection" "0,1" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0,1" newline bitfld.long 0x0 7. "TXEIE,interrupt enable" "0,1" bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0,1" newline bitfld.long 0x0 5. "RXNEIE,RXNE interrupt enable" "0,1" bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0,1" newline bitfld.long 0x0 3. "TE,Transmitter enable" "0,1" bitfld.long 0x0 2. "RE,Receiver enable" "0,1" newline bitfld.long 0x0 1. "UESM,USART enable in Stop mode" "0,1" bitfld.long 0x0 0. "UE,USART enable" "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "ISR,Interrupt & status register" bitfld.long 0x0 27. "TXFT,TXFIFO threshold flag" "0,1" bitfld.long 0x0 26. "RXFT,RXFIFO threshold flag" "0,1" newline bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time flag" "0,1" bitfld.long 0x0 24. "RXFF,RXFIFO Full" "0,1" newline bitfld.long 0x0 23. "TXFE,TXFIFO Empty" "0,1" bitfld.long 0x0 22. "REACK,REACK" "0,1" newline bitfld.long 0x0 21. "TEACK,TEACK" "0,1" bitfld.long 0x0 20. "WUF,WUF" "0,1" newline bitfld.long 0x0 19. "RWU,RWU" "0,1" bitfld.long 0x0 18. "SBKF,SBKF" "0,1" newline bitfld.long 0x0 17. "CMF,CMF" "0,1" bitfld.long 0x0 16. "BUSY,BUSY" "0,1" newline bitfld.long 0x0 15. "ABRF,ABRF" "0,1" bitfld.long 0x0 14. "ABRE,ABRE" "0,1" newline bitfld.long 0x0 13. "UDR,SPI slave underrun error flag" "0,1" bitfld.long 0x0 12. "EOBF,EOBF" "0,1" newline bitfld.long 0x0 11. "RTOF,RTOF" "0,1" bitfld.long 0x0 10. "CTS,CTS" "0,1" newline bitfld.long 0x0 9. "CTSIF,CTSIF" "0,1" bitfld.long 0x0 8. "LBDF,LBDF" "0,1" newline bitfld.long 0x0 7. "TXE,TXE" "0,1" bitfld.long 0x0 6. "TC,TC" "0,1" newline bitfld.long 0x0 5. "RXNE,RXNE" "0,1" bitfld.long 0x0 4. "IDLE,IDLE" "0,1" newline bitfld.long 0x0 3. "ORE,ORE" "0,1" bitfld.long 0x0 2. "NF,NF" "0,1" newline bitfld.long 0x0 1. "FE,FE" "0,1" bitfld.long 0x0 0. "PE,PE" "0,1" endif group.long 0x4++0x13 line.long 0x0 "CR2,Control register 2" hexmask.long.byte 0x0 28.--31. 1. "ADD4_7,Address of the USART node" hexmask.long.byte 0x0 24.--27. 1. "ADD0_3,Address of the USART node" bitfld.long 0x0 23. "RTOEN,Receiver timeout enable" "0,1" bitfld.long 0x0 21.--22. "ABRMOD,Auto baud rate mode" "0,1,2,3" bitfld.long 0x0 20. "ABREN,Auto baud rate enable" "0,1" bitfld.long 0x0 19. "MSBFIRST,Most significant bit first" "0,1" bitfld.long 0x0 18. "TAINV,Binary data inversion" "0,1" bitfld.long 0x0 17. "TXINV,TX pin active level inversion" "0,1" newline bitfld.long 0x0 16. "RXINV,RX pin active level inversion" "0,1" bitfld.long 0x0 15. "SWAP,Swap TX/RX pins" "0,1" bitfld.long 0x0 14. "LINEN,LIN mode enable" "0,1" bitfld.long 0x0 12.--13. "STOP,STOP bits" "0,1,2,3" bitfld.long 0x0 11. "CLKEN,Clock enable" "0,1" bitfld.long 0x0 10. "CPOL,Clock polarity" "0,1" bitfld.long 0x0 9. "CPHA,Clock phase" "0,1" bitfld.long 0x0 8. "LBCL,Last bit clock pulse" "0,1" newline bitfld.long 0x0 6. "LBDIE,LIN break detection interrupt enable" "0,1" bitfld.long 0x0 5. "LBDL,LIN break detection length" "0,1" bitfld.long 0x0 4. "ADDM7,7-bit Address Detection/4-bit Address Detection" "0,1" bitfld.long 0x0 3. "DIS_NSS,When the DSI_NSS bit is set the NSS pin input will be ignored" "0,1" bitfld.long 0x0 0. "SLVEN,Synchronous Slave mode enable" "0,1" line.long 0x4 "CR3,Control register 3" bitfld.long 0x4 29.--31. "TXFTCFG,TXFIFO threshold configuration" "0,1,2,3,4,5,6,7" bitfld.long 0x4 28. "RXFTIE,RXFIFO threshold interrupt enable" "0,1" bitfld.long 0x4 25.--27. "RXFTCFG,Receive FIFO threshold configuration" "0,1,2,3,4,5,6,7" bitfld.long 0x4 24. "TCBGTIE,Tr Complete before guard time interrupt enable" "0,1" bitfld.long 0x4 23. "TXFTIE,threshold interrupt enable" "0,1" bitfld.long 0x4 22. "WUFIE,Wakeup from Stop mode interrupt enable" "0,1" bitfld.long 0x4 20.--21. "WUS,Wakeup from Stop mode interrupt flag selection" "0,1,2,3" bitfld.long 0x4 17.--19. "SCARCNT,Smartcard auto-retry count" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 15. "DEP,Driver enable polarity selection" "0,1" bitfld.long 0x4 14. "DEM,Driver enable mode" "0,1" bitfld.long 0x4 13. "DDRE,DMA Disable on Reception Error" "0,1" bitfld.long 0x4 12. "OVRDIS,Overrun Disable" "0,1" bitfld.long 0x4 11. "ONEBIT,One sample bit method enable" "0,1" bitfld.long 0x4 10. "CTSIE,CTS interrupt enable" "0,1" bitfld.long 0x4 9. "CTSE,CTS enable" "0,1" bitfld.long 0x4 8. "RTSE,RTS enable" "0,1" newline bitfld.long 0x4 7. "DMAT,DMA enable transmitter" "0,1" bitfld.long 0x4 6. "DMAR,DMA enable receiver" "0,1" bitfld.long 0x4 5. "SCEN,Smartcard mode enable" "0,1" bitfld.long 0x4 4. "NACK,Smartcard NACK enable" "0,1" bitfld.long 0x4 3. "HDSEL,Half-duplex selection" "0,1" bitfld.long 0x4 2. "IRLP,Ir low-power" "0,1" bitfld.long 0x4 1. "IREN,Ir mode enable" "0,1" bitfld.long 0x4 0. "EIE,Error interrupt enable" "0,1" line.long 0x8 "BRR,Baud rate register" hexmask.long.word 0x8 4.--15. 1. "BRR_4_15,BRR_4_15" hexmask.long.byte 0x8 0.--3. 1. "BRR_0_3,BRR_0_3" line.long 0xC "GTPR,Guard time and prescaler register" hexmask.long.byte 0xC 8.--15. 1. "GT,Guard time value" hexmask.long.byte 0xC 0.--7. 1. "PSC,Prescaler value" line.long 0x10 "RTOR,Receiver timeout register" hexmask.long.byte 0x10 24.--31. 1. "BLEN,Block Length" hexmask.long.tbyte 0x10 0.--23. 1. "RTO,Receiver timeout value" wgroup.long 0x18++0x3 line.long 0x0 "RQR,Request register" bitfld.long 0x0 4. "TXFRQ,Transmit data flush request" "0,1" bitfld.long 0x0 3. "RXFRQ,Receive data flush request" "0,1" bitfld.long 0x0 2. "MMRQ,Mute mode request" "0,1" bitfld.long 0x0 1. "SBKRQ,Send break request" "0,1" bitfld.long 0x0 0. "ABRRQ,Auto baud rate request" "0,1" wgroup.long 0x20++0x3 line.long 0x0 "ICR,Interrupt flag clear register" bitfld.long 0x0 20. "WUCF,Wakeup from Stop mode clear flag" "0,1" bitfld.long 0x0 17. "CMCF,Character match clear flag" "0,1" bitfld.long 0x0 13. "UDRCF,SPI slave underrun clear flag" "0,1" bitfld.long 0x0 12. "EOBCF,End of block clear flag" "0,1" bitfld.long 0x0 11. "RTOCF,Receiver timeout clear flag" "0,1" bitfld.long 0x0 9. "CTSCF,CTS clear flag" "0,1" bitfld.long 0x0 8. "LBDCF,LIN break detection clear flag" "0,1" bitfld.long 0x0 7. "TCBGTCF,Transmission complete before Guard time clear flag" "0,1" newline bitfld.long 0x0 6. "TCCF,Transmission complete clear flag" "0,1" bitfld.long 0x0 5. "TXFECF,TXFIFO empty clear flag" "0,1" bitfld.long 0x0 4. "IDLECF,Idle line detected clear flag" "0,1" bitfld.long 0x0 3. "ORECF,Overrun error clear flag" "0,1" bitfld.long 0x0 2. "NCF,Noise detected clear flag" "0,1" bitfld.long 0x0 1. "FECF,Framing error clear flag" "0,1" bitfld.long 0x0 0. "PECF,Parity error clear flag" "0,1" rgroup.long 0x24++0x3 line.long 0x0 "RDR,Receive data register" hexmask.long.word 0x0 0.--8. 1. "RDR,Receive data value" group.long 0x28++0x7 line.long 0x0 "TDR,Transmit data register" hexmask.long.word 0x0 0.--8. 1. "TDR,Transmit data value" line.long 0x4 "PRESC,Prescaler register" hexmask.long.byte 0x4 0.--3. 1. "PRESCALER,Clock prescaler" rgroup.long 0x3EC++0x13 line.long 0x0 "HWCFGR2,USART Hardware Configuration register 2" hexmask.long.byte 0x0 4.--7. 1. "CFG2,CFG2" hexmask.long.byte 0x0 0.--3. 1. "CFG1,CFG1" line.long 0x4 "HWCFGR1,USART Hardware Configuration register 1" hexmask.long.byte 0x4 28.--31. 1. "CFG8,CFG8" hexmask.long.byte 0x4 24.--27. 1. "CFG7,CFG7" hexmask.long.byte 0x4 20.--23. 1. "CFG6,CFG6" hexmask.long.byte 0x4 16.--19. 1. "CFG5,CFG5" hexmask.long.byte 0x4 12.--15. 1. "CFG4,CFG4" hexmask.long.byte 0x4 8.--11. 1. "CFG3,CFG3" hexmask.long.byte 0x4 4.--7. 1. "CFG2,CFG2" hexmask.long.byte 0x4 0.--3. 1. "CFG1,CFG1" line.long 0x8 "VERR,EXTI IP Version register" hexmask.long.byte 0x8 4.--7. 1. "MAJREV,Major Revision number" hexmask.long.byte 0x8 0.--3. 1. "MINREV,Minor Revision number" line.long 0xC "IPIDR,EXTI Identification register" hexmask.long 0xC 0.--31. 1. "IPID,IP Identification" line.long 0x10 "SIDR,EXTI Size ID register" hexmask.long 0x10 0.--31. 1. "SID,Size Identification" tree.end endif sif (cpuis("STM32MP153*")) tree "USART1" base ad:0x5C000000 group.long 0x0++0x17 line.long 0x0 "CR1,Control register 1" bitfld.long 0x0 31. "RXFFIE,RXFIFO Full interrupt enable" "0,1" bitfld.long 0x0 30. "TXFEIE,TXFIFO empty interrupt enable" "0,1" bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0,1" bitfld.long 0x0 28. "M1,Word length" "0,1" bitfld.long 0x0 27. "EOBIE,End of Block interrupt enable" "0,1" bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0,1" hexmask.long.byte 0x0 21.--25. 1. "DEAT,DEAT" hexmask.long.byte 0x0 16.--20. 1. "DEDT,DEDT" newline bitfld.long 0x0 15. "OVER8,Oversampling mode" "0,1" bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0,1" bitfld.long 0x0 13. "MME,Mute mode enable" "0,1" bitfld.long 0x0 12. "M0,Word length" "0,1" bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0,1" bitfld.long 0x0 10. "PCE,Parity control enable" "0,1" bitfld.long 0x0 9. "PS,Parity selection" "0,1" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0,1" newline bitfld.long 0x0 7. "TXEIE,interrupt enable" "0,1" bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0,1" bitfld.long 0x0 5. "RXNEIE,RXNE interrupt enable" "0,1" bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0,1" bitfld.long 0x0 3. "TE,Transmitter enable" "0,1" bitfld.long 0x0 2. "RE,Receiver enable" "0,1" bitfld.long 0x0 1. "UESM,USART enable in Stop mode" "0,1" bitfld.long 0x0 0. "UE,USART enable" "0,1" line.long 0x4 "CR2,Control register 2" hexmask.long.byte 0x4 28.--31. 1. "ADD4_7,Address of the USART node" hexmask.long.byte 0x4 24.--27. 1. "ADD0_3,Address of the USART node" bitfld.long 0x4 23. "RTOEN,Receiver timeout enable" "0,1" bitfld.long 0x4 21.--22. "ABRMOD,Auto baud rate mode" "0,1,2,3" bitfld.long 0x4 20. "ABREN,Auto baud rate enable" "0,1" bitfld.long 0x4 19. "MSBFIRST,Most significant bit first" "0,1" bitfld.long 0x4 18. "TAINV,Binary data inversion" "0,1" bitfld.long 0x4 17. "TXINV,TX pin active level inversion" "0,1" newline bitfld.long 0x4 16. "RXINV,RX pin active level inversion" "0,1" bitfld.long 0x4 15. "SWAP,Swap TX/RX pins" "0,1" bitfld.long 0x4 14. "LINEN,LIN mode enable" "0,1" bitfld.long 0x4 12.--13. "STOP,STOP bits" "0,1,2,3" bitfld.long 0x4 11. "CLKEN,Clock enable" "0,1" bitfld.long 0x4 10. "CPOL,Clock polarity" "0,1" bitfld.long 0x4 9. "CPHA,Clock phase" "0,1" bitfld.long 0x4 8. "LBCL,Last bit clock pulse" "0,1" newline bitfld.long 0x4 6. "LBDIE,LIN break detection interrupt enable" "0,1" bitfld.long 0x4 5. "LBDL,LIN break detection length" "0,1" bitfld.long 0x4 4. "ADDM7,7-bit Address Detection/4-bit Address Detection" "0,1" bitfld.long 0x4 3. "DIS_NSS,When the DSI_NSS bit is set the NSS pin input will be ignored" "0,1" bitfld.long 0x4 0. "SLVEN,Synchronous Slave mode enable" "0,1" line.long 0x8 "CR3,Control register 3" bitfld.long 0x8 29.--31. "TXFTCFG,TXFIFO threshold configuration" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "RXFTIE,RXFIFO threshold interrupt enable" "0,1" bitfld.long 0x8 25.--27. "RXFTCFG,Receive FIFO threshold configuration" "0,1,2,3,4,5,6,7" bitfld.long 0x8 24. "TCBGTIE,Tr Complete before guard time interrupt enable" "0,1" bitfld.long 0x8 23. "TXFTIE,threshold interrupt enable" "0,1" bitfld.long 0x8 22. "WUFIE,Wakeup from Stop mode interrupt enable" "0,1" bitfld.long 0x8 20.--21. "WUS,Wakeup from Stop mode interrupt flag selection" "0,1,2,3" bitfld.long 0x8 17.--19. "SCARCNT,Smartcard auto-retry count" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 15. "DEP,Driver enable polarity selection" "0,1" bitfld.long 0x8 14. "DEM,Driver enable mode" "0,1" bitfld.long 0x8 13. "DDRE,DMA Disable on Reception Error" "0,1" bitfld.long 0x8 12. "OVRDIS,Overrun Disable" "0,1" bitfld.long 0x8 11. "ONEBIT,One sample bit method enable" "0,1" bitfld.long 0x8 10. "CTSIE,CTS interrupt enable" "0,1" bitfld.long 0x8 9. "CTSE,CTS enable" "0,1" bitfld.long 0x8 8. "RTSE,RTS enable" "0,1" newline bitfld.long 0x8 7. "DMAT,DMA enable transmitter" "0,1" bitfld.long 0x8 6. "DMAR,DMA enable receiver" "0,1" bitfld.long 0x8 5. "SCEN,Smartcard mode enable" "0,1" bitfld.long 0x8 4. "NACK,Smartcard NACK enable" "0,1" bitfld.long 0x8 3. "HDSEL,Half-duplex selection" "0,1" bitfld.long 0x8 2. "IRLP,Ir low-power" "0,1" bitfld.long 0x8 1. "IREN,Ir mode enable" "0,1" bitfld.long 0x8 0. "EIE,Error interrupt enable" "0,1" line.long 0xC "BRR,Baud rate register" hexmask.long.word 0xC 4.--15. 1. "BRR_4_15,BRR_4_15" hexmask.long.byte 0xC 0.--3. 1. "BRR_0_3,BRR_0_3" line.long 0x10 "GTPR,Guard time and prescaler register" hexmask.long.byte 0x10 8.--15. 1. "GT,Guard time value" hexmask.long.byte 0x10 0.--7. 1. "PSC,Prescaler value" line.long 0x14 "RTOR,Receiver timeout register" hexmask.long.byte 0x14 24.--31. 1. "BLEN,Block Length" hexmask.long.tbyte 0x14 0.--23. 1. "RTO,Receiver timeout value" wgroup.long 0x18++0x3 line.long 0x0 "RQR,Request register" bitfld.long 0x0 4. "TXFRQ,Transmit data flush request" "0,1" bitfld.long 0x0 3. "RXFRQ,Receive data flush request" "0,1" bitfld.long 0x0 2. "MMRQ,Mute mode request" "0,1" bitfld.long 0x0 1. "SBKRQ,Send break request" "0,1" bitfld.long 0x0 0. "ABRRQ,Auto baud rate request" "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "ISR,Interrupt & status register" bitfld.long 0x0 27. "TXFT,TXFIFO threshold flag" "0,1" bitfld.long 0x0 26. "RXFT,RXFIFO threshold flag" "0,1" bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time flag" "0,1" bitfld.long 0x0 24. "RXFF,RXFIFO Full" "0,1" bitfld.long 0x0 23. "TXFE,TXFIFO Empty" "0,1" bitfld.long 0x0 22. "REACK,REACK" "0,1" bitfld.long 0x0 21. "TEACK,TEACK" "0,1" bitfld.long 0x0 20. "WUF,WUF" "0,1" newline bitfld.long 0x0 19. "RWU,RWU" "0,1" bitfld.long 0x0 18. "SBKF,SBKF" "0,1" bitfld.long 0x0 17. "CMF,CMF" "0,1" bitfld.long 0x0 16. "BUSY,BUSY" "0,1" bitfld.long 0x0 15. "ABRF,ABRF" "0,1" bitfld.long 0x0 14. "ABRE,ABRE" "0,1" bitfld.long 0x0 13. "UDR,SPI slave underrun error flag" "0,1" bitfld.long 0x0 12. "EOBF,EOBF" "0,1" newline bitfld.long 0x0 11. "RTOF,RTOF" "0,1" bitfld.long 0x0 10. "CTS,CTS" "0,1" bitfld.long 0x0 9. "CTSIF,CTSIF" "0,1" bitfld.long 0x0 8. "LBDF,LBDF" "0,1" bitfld.long 0x0 7. "TXE,TXE" "0,1" bitfld.long 0x0 6. "TC,TC" "0,1" bitfld.long 0x0 5. "RXNE,RXNE" "0,1" bitfld.long 0x0 4. "IDLE,IDLE" "0,1" newline bitfld.long 0x0 3. "ORE,ORE" "0,1" bitfld.long 0x0 2. "NF,NF" "0,1" bitfld.long 0x0 1. "FE,FE" "0,1" bitfld.long 0x0 0. "PE,PE" "0,1" wgroup.long 0x20++0x3 line.long 0x0 "ICR,Interrupt flag clear register" bitfld.long 0x0 20. "WUCF,Wakeup from Stop mode clear flag" "0,1" bitfld.long 0x0 17. "CMCF,Character match clear flag" "0,1" bitfld.long 0x0 13. "UDRCF,SPI slave underrun clear flag" "0,1" bitfld.long 0x0 12. "EOBCF,End of block clear flag" "0,1" bitfld.long 0x0 11. "RTOCF,Receiver timeout clear flag" "0,1" bitfld.long 0x0 9. "CTSCF,CTS clear flag" "0,1" bitfld.long 0x0 8. "LBDCF,LIN break detection clear flag" "0,1" bitfld.long 0x0 7. "TCBGTCF,Transmission complete before Guard time clear flag" "0,1" newline bitfld.long 0x0 6. "TCCF,Transmission complete clear flag" "0,1" bitfld.long 0x0 5. "TXFECF,TXFIFO empty clear flag" "0,1" bitfld.long 0x0 4. "IDLECF,Idle line detected clear flag" "0,1" bitfld.long 0x0 3. "ORECF,Overrun error clear flag" "0,1" bitfld.long 0x0 2. "NCF,Noise detected clear flag" "0,1" bitfld.long 0x0 1. "FECF,Framing error clear flag" "0,1" bitfld.long 0x0 0. "PECF,Parity error clear flag" "0,1" rgroup.long 0x24++0x3 line.long 0x0 "RDR,Receive data register" hexmask.long.word 0x0 0.--8. 1. "RDR,Receive data value" group.long 0x28++0x7 line.long 0x0 "TDR,Transmit data register" hexmask.long.word 0x0 0.--8. 1. "TDR,Transmit data value" line.long 0x4 "PRESC,Prescaler register" hexmask.long.byte 0x4 0.--3. 1. "PRESCALER,Clock prescaler" rgroup.long 0x3EC++0x13 line.long 0x0 "HWCFGR2,USART Hardware Configuration register 2" hexmask.long.byte 0x0 4.--7. 1. "CFG2,CFG2" hexmask.long.byte 0x0 0.--3. 1. "CFG1,CFG1" line.long 0x4 "HWCFGR1,USART Hardware Configuration register 1" hexmask.long.byte 0x4 28.--31. 1. "CFG8,CFG8" hexmask.long.byte 0x4 24.--27. 1. "CFG7,CFG7" hexmask.long.byte 0x4 20.--23. 1. "CFG6,CFG6" hexmask.long.byte 0x4 16.--19. 1. "CFG5,CFG5" hexmask.long.byte 0x4 12.--15. 1. "CFG4,CFG4" hexmask.long.byte 0x4 8.--11. 1. "CFG3,CFG3" hexmask.long.byte 0x4 4.--7. 1. "CFG2,CFG2" hexmask.long.byte 0x4 0.--3. 1. "CFG1,CFG1" line.long 0x8 "VERR,EXTI IP Version register" hexmask.long.byte 0x8 4.--7. 1. "MAJREV,Major Revision number" hexmask.long.byte 0x8 0.--3. 1. "MINREV,Minor Revision number" line.long 0xC "IPIDR,EXTI Identification register" hexmask.long 0xC 0.--31. 1. "IPID,IP Identification" line.long 0x10 "SIDR,EXTI Size ID register" hexmask.long 0x10 0.--31. 1. "SID,Size Identification" tree.end endif sif (cpuis("STM32MP153*")) tree "USART2" base ad:0x4000E000 group.long 0x0++0x17 line.long 0x0 "CR1,Control register 1" bitfld.long 0x0 31. "RXFFIE,RXFIFO Full interrupt enable" "0,1" bitfld.long 0x0 30. "TXFEIE,TXFIFO empty interrupt enable" "0,1" bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0,1" bitfld.long 0x0 28. "M1,Word length" "0,1" bitfld.long 0x0 27. "EOBIE,End of Block interrupt enable" "0,1" bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0,1" hexmask.long.byte 0x0 21.--25. 1. "DEAT,DEAT" hexmask.long.byte 0x0 16.--20. 1. "DEDT,DEDT" newline bitfld.long 0x0 15. "OVER8,Oversampling mode" "0,1" bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0,1" bitfld.long 0x0 13. "MME,Mute mode enable" "0,1" bitfld.long 0x0 12. "M0,Word length" "0,1" bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0,1" bitfld.long 0x0 10. "PCE,Parity control enable" "0,1" bitfld.long 0x0 9. "PS,Parity selection" "0,1" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0,1" newline bitfld.long 0x0 7. "TXEIE,interrupt enable" "0,1" bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0,1" bitfld.long 0x0 5. "RXNEIE,RXNE interrupt enable" "0,1" bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0,1" bitfld.long 0x0 3. "TE,Transmitter enable" "0,1" bitfld.long 0x0 2. "RE,Receiver enable" "0,1" bitfld.long 0x0 1. "UESM,USART enable in Stop mode" "0,1" bitfld.long 0x0 0. "UE,USART enable" "0,1" line.long 0x4 "CR2,Control register 2" hexmask.long.byte 0x4 28.--31. 1. "ADD4_7,Address of the USART node" hexmask.long.byte 0x4 24.--27. 1. "ADD0_3,Address of the USART node" bitfld.long 0x4 23. "RTOEN,Receiver timeout enable" "0,1" bitfld.long 0x4 21.--22. "ABRMOD,Auto baud rate mode" "0,1,2,3" bitfld.long 0x4 20. "ABREN,Auto baud rate enable" "0,1" bitfld.long 0x4 19. "MSBFIRST,Most significant bit first" "0,1" bitfld.long 0x4 18. "TAINV,Binary data inversion" "0,1" bitfld.long 0x4 17. "TXINV,TX pin active level inversion" "0,1" newline bitfld.long 0x4 16. "RXINV,RX pin active level inversion" "0,1" bitfld.long 0x4 15. "SWAP,Swap TX/RX pins" "0,1" bitfld.long 0x4 14. "LINEN,LIN mode enable" "0,1" bitfld.long 0x4 12.--13. "STOP,STOP bits" "0,1,2,3" bitfld.long 0x4 11. "CLKEN,Clock enable" "0,1" bitfld.long 0x4 10. "CPOL,Clock polarity" "0,1" bitfld.long 0x4 9. "CPHA,Clock phase" "0,1" bitfld.long 0x4 8. "LBCL,Last bit clock pulse" "0,1" newline bitfld.long 0x4 6. "LBDIE,LIN break detection interrupt enable" "0,1" bitfld.long 0x4 5. "LBDL,LIN break detection length" "0,1" bitfld.long 0x4 4. "ADDM7,7-bit Address Detection/4-bit Address Detection" "0,1" bitfld.long 0x4 3. "DIS_NSS,When the DSI_NSS bit is set the NSS pin input will be ignored" "0,1" bitfld.long 0x4 0. "SLVEN,Synchronous Slave mode enable" "0,1" line.long 0x8 "CR3,Control register 3" bitfld.long 0x8 29.--31. "TXFTCFG,TXFIFO threshold configuration" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "RXFTIE,RXFIFO threshold interrupt enable" "0,1" bitfld.long 0x8 25.--27. "RXFTCFG,Receive FIFO threshold configuration" "0,1,2,3,4,5,6,7" bitfld.long 0x8 24. "TCBGTIE,Tr Complete before guard time interrupt enable" "0,1" bitfld.long 0x8 23. "TXFTIE,threshold interrupt enable" "0,1" bitfld.long 0x8 22. "WUFIE,Wakeup from Stop mode interrupt enable" "0,1" bitfld.long 0x8 20.--21. "WUS,Wakeup from Stop mode interrupt flag selection" "0,1,2,3" bitfld.long 0x8 17.--19. "SCARCNT,Smartcard auto-retry count" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 15. "DEP,Driver enable polarity selection" "0,1" bitfld.long 0x8 14. "DEM,Driver enable mode" "0,1" bitfld.long 0x8 13. "DDRE,DMA Disable on Reception Error" "0,1" bitfld.long 0x8 12. "OVRDIS,Overrun Disable" "0,1" bitfld.long 0x8 11. "ONEBIT,One sample bit method enable" "0,1" bitfld.long 0x8 10. "CTSIE,CTS interrupt enable" "0,1" bitfld.long 0x8 9. "CTSE,CTS enable" "0,1" bitfld.long 0x8 8. "RTSE,RTS enable" "0,1" newline bitfld.long 0x8 7. "DMAT,DMA enable transmitter" "0,1" bitfld.long 0x8 6. "DMAR,DMA enable receiver" "0,1" bitfld.long 0x8 5. "SCEN,Smartcard mode enable" "0,1" bitfld.long 0x8 4. "NACK,Smartcard NACK enable" "0,1" bitfld.long 0x8 3. "HDSEL,Half-duplex selection" "0,1" bitfld.long 0x8 2. "IRLP,Ir low-power" "0,1" bitfld.long 0x8 1. "IREN,Ir mode enable" "0,1" bitfld.long 0x8 0. "EIE,Error interrupt enable" "0,1" line.long 0xC "BRR,Baud rate register" hexmask.long.word 0xC 4.--15. 1. "BRR_4_15,BRR_4_15" hexmask.long.byte 0xC 0.--3. 1. "BRR_0_3,BRR_0_3" line.long 0x10 "GTPR,Guard time and prescaler register" hexmask.long.byte 0x10 8.--15. 1. "GT,Guard time value" hexmask.long.byte 0x10 0.--7. 1. "PSC,Prescaler value" line.long 0x14 "RTOR,Receiver timeout register" hexmask.long.byte 0x14 24.--31. 1. "BLEN,Block Length" hexmask.long.tbyte 0x14 0.--23. 1. "RTO,Receiver timeout value" wgroup.long 0x18++0x3 line.long 0x0 "RQR,Request register" bitfld.long 0x0 4. "TXFRQ,Transmit data flush request" "0,1" bitfld.long 0x0 3. "RXFRQ,Receive data flush request" "0,1" bitfld.long 0x0 2. "MMRQ,Mute mode request" "0,1" bitfld.long 0x0 1. "SBKRQ,Send break request" "0,1" bitfld.long 0x0 0. "ABRRQ,Auto baud rate request" "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "ISR,Interrupt & status register" bitfld.long 0x0 27. "TXFT,TXFIFO threshold flag" "0,1" bitfld.long 0x0 26. "RXFT,RXFIFO threshold flag" "0,1" bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time flag" "0,1" bitfld.long 0x0 24. "RXFF,RXFIFO Full" "0,1" bitfld.long 0x0 23. "TXFE,TXFIFO Empty" "0,1" bitfld.long 0x0 22. "REACK,REACK" "0,1" bitfld.long 0x0 21. "TEACK,TEACK" "0,1" bitfld.long 0x0 20. "WUF,WUF" "0,1" newline bitfld.long 0x0 19. "RWU,RWU" "0,1" bitfld.long 0x0 18. "SBKF,SBKF" "0,1" bitfld.long 0x0 17. "CMF,CMF" "0,1" bitfld.long 0x0 16. "BUSY,BUSY" "0,1" bitfld.long 0x0 15. "ABRF,ABRF" "0,1" bitfld.long 0x0 14. "ABRE,ABRE" "0,1" bitfld.long 0x0 13. "UDR,SPI slave underrun error flag" "0,1" bitfld.long 0x0 12. "EOBF,EOBF" "0,1" newline bitfld.long 0x0 11. "RTOF,RTOF" "0,1" bitfld.long 0x0 10. "CTS,CTS" "0,1" bitfld.long 0x0 9. "CTSIF,CTSIF" "0,1" bitfld.long 0x0 8. "LBDF,LBDF" "0,1" bitfld.long 0x0 7. "TXE,TXE" "0,1" bitfld.long 0x0 6. "TC,TC" "0,1" bitfld.long 0x0 5. "RXNE,RXNE" "0,1" bitfld.long 0x0 4. "IDLE,IDLE" "0,1" newline bitfld.long 0x0 3. "ORE,ORE" "0,1" bitfld.long 0x0 2. "NF,NF" "0,1" bitfld.long 0x0 1. "FE,FE" "0,1" bitfld.long 0x0 0. "PE,PE" "0,1" wgroup.long 0x20++0x3 line.long 0x0 "ICR,Interrupt flag clear register" bitfld.long 0x0 20. "WUCF,Wakeup from Stop mode clear flag" "0,1" bitfld.long 0x0 17. "CMCF,Character match clear flag" "0,1" bitfld.long 0x0 13. "UDRCF,SPI slave underrun clear flag" "0,1" bitfld.long 0x0 12. "EOBCF,End of block clear flag" "0,1" bitfld.long 0x0 11. "RTOCF,Receiver timeout clear flag" "0,1" bitfld.long 0x0 9. "CTSCF,CTS clear flag" "0,1" bitfld.long 0x0 8. "LBDCF,LIN break detection clear flag" "0,1" bitfld.long 0x0 7. "TCBGTCF,Transmission complete before Guard time clear flag" "0,1" newline bitfld.long 0x0 6. "TCCF,Transmission complete clear flag" "0,1" bitfld.long 0x0 5. "TXFECF,TXFIFO empty clear flag" "0,1" bitfld.long 0x0 4. "IDLECF,Idle line detected clear flag" "0,1" bitfld.long 0x0 3. "ORECF,Overrun error clear flag" "0,1" bitfld.long 0x0 2. "NCF,Noise detected clear flag" "0,1" bitfld.long 0x0 1. "FECF,Framing error clear flag" "0,1" bitfld.long 0x0 0. "PECF,Parity error clear flag" "0,1" rgroup.long 0x24++0x3 line.long 0x0 "RDR,Receive data register" hexmask.long.word 0x0 0.--8. 1. "RDR,Receive data value" group.long 0x28++0x7 line.long 0x0 "TDR,Transmit data register" hexmask.long.word 0x0 0.--8. 1. "TDR,Transmit data value" line.long 0x4 "PRESC,Prescaler register" hexmask.long.byte 0x4 0.--3. 1. "PRESCALER,Clock prescaler" rgroup.long 0x3EC++0x13 line.long 0x0 "HWCFGR2,USART Hardware Configuration register 2" hexmask.long.byte 0x0 4.--7. 1. "CFG2,CFG2" hexmask.long.byte 0x0 0.--3. 1. "CFG1,CFG1" line.long 0x4 "HWCFGR1,USART Hardware Configuration register 1" hexmask.long.byte 0x4 28.--31. 1. "CFG8,CFG8" hexmask.long.byte 0x4 24.--27. 1. "CFG7,CFG7" hexmask.long.byte 0x4 20.--23. 1. "CFG6,CFG6" hexmask.long.byte 0x4 16.--19. 1. "CFG5,CFG5" hexmask.long.byte 0x4 12.--15. 1. "CFG4,CFG4" hexmask.long.byte 0x4 8.--11. 1. "CFG3,CFG3" hexmask.long.byte 0x4 4.--7. 1. "CFG2,CFG2" hexmask.long.byte 0x4 0.--3. 1. "CFG1,CFG1" line.long 0x8 "VERR,EXTI IP Version register" hexmask.long.byte 0x8 4.--7. 1. "MAJREV,Major Revision number" hexmask.long.byte 0x8 0.--3. 1. "MINREV,Minor Revision number" line.long 0xC "IPIDR,EXTI Identification register" hexmask.long 0xC 0.--31. 1. "IPID,IP Identification" line.long 0x10 "SIDR,EXTI Size ID register" hexmask.long 0x10 0.--31. 1. "SID,Size Identification" tree.end tree "USART3" base ad:0x4000F000 group.long 0x0++0x17 line.long 0x0 "CR1,Control register 1" bitfld.long 0x0 31. "RXFFIE,RXFIFO Full interrupt enable" "0,1" bitfld.long 0x0 30. "TXFEIE,TXFIFO empty interrupt enable" "0,1" bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0,1" bitfld.long 0x0 28. "M1,Word length" "0,1" bitfld.long 0x0 27. "EOBIE,End of Block interrupt enable" "0,1" bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0,1" hexmask.long.byte 0x0 21.--25. 1. "DEAT,DEAT" hexmask.long.byte 0x0 16.--20. 1. "DEDT,DEDT" newline bitfld.long 0x0 15. "OVER8,Oversampling mode" "0,1" bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0,1" bitfld.long 0x0 13. "MME,Mute mode enable" "0,1" bitfld.long 0x0 12. "M0,Word length" "0,1" bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0,1" bitfld.long 0x0 10. "PCE,Parity control enable" "0,1" bitfld.long 0x0 9. "PS,Parity selection" "0,1" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0,1" newline bitfld.long 0x0 7. "TXEIE,interrupt enable" "0,1" bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0,1" bitfld.long 0x0 5. "RXNEIE,RXNE interrupt enable" "0,1" bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0,1" bitfld.long 0x0 3. "TE,Transmitter enable" "0,1" bitfld.long 0x0 2. "RE,Receiver enable" "0,1" bitfld.long 0x0 1. "UESM,USART enable in Stop mode" "0,1" bitfld.long 0x0 0. "UE,USART enable" "0,1" line.long 0x4 "CR2,Control register 2" hexmask.long.byte 0x4 28.--31. 1. "ADD4_7,Address of the USART node" hexmask.long.byte 0x4 24.--27. 1. "ADD0_3,Address of the USART node" bitfld.long 0x4 23. "RTOEN,Receiver timeout enable" "0,1" bitfld.long 0x4 21.--22. "ABRMOD,Auto baud rate mode" "0,1,2,3" bitfld.long 0x4 20. "ABREN,Auto baud rate enable" "0,1" bitfld.long 0x4 19. "MSBFIRST,Most significant bit first" "0,1" bitfld.long 0x4 18. "TAINV,Binary data inversion" "0,1" bitfld.long 0x4 17. "TXINV,TX pin active level inversion" "0,1" newline bitfld.long 0x4 16. "RXINV,RX pin active level inversion" "0,1" bitfld.long 0x4 15. "SWAP,Swap TX/RX pins" "0,1" bitfld.long 0x4 14. "LINEN,LIN mode enable" "0,1" bitfld.long 0x4 12.--13. "STOP,STOP bits" "0,1,2,3" bitfld.long 0x4 11. "CLKEN,Clock enable" "0,1" bitfld.long 0x4 10. "CPOL,Clock polarity" "0,1" bitfld.long 0x4 9. "CPHA,Clock phase" "0,1" bitfld.long 0x4 8. "LBCL,Last bit clock pulse" "0,1" newline bitfld.long 0x4 6. "LBDIE,LIN break detection interrupt enable" "0,1" bitfld.long 0x4 5. "LBDL,LIN break detection length" "0,1" bitfld.long 0x4 4. "ADDM7,7-bit Address Detection/4-bit Address Detection" "0,1" bitfld.long 0x4 3. "DIS_NSS,When the DSI_NSS bit is set the NSS pin input will be ignored" "0,1" bitfld.long 0x4 0. "SLVEN,Synchronous Slave mode enable" "0,1" line.long 0x8 "CR3,Control register 3" bitfld.long 0x8 29.--31. "TXFTCFG,TXFIFO threshold configuration" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "RXFTIE,RXFIFO threshold interrupt enable" "0,1" bitfld.long 0x8 25.--27. "RXFTCFG,Receive FIFO threshold configuration" "0,1,2,3,4,5,6,7" bitfld.long 0x8 24. "TCBGTIE,Tr Complete before guard time interrupt enable" "0,1" bitfld.long 0x8 23. "TXFTIE,threshold interrupt enable" "0,1" bitfld.long 0x8 22. "WUFIE,Wakeup from Stop mode interrupt enable" "0,1" bitfld.long 0x8 20.--21. "WUS,Wakeup from Stop mode interrupt flag selection" "0,1,2,3" bitfld.long 0x8 17.--19. "SCARCNT,Smartcard auto-retry count" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 15. "DEP,Driver enable polarity selection" "0,1" bitfld.long 0x8 14. "DEM,Driver enable mode" "0,1" bitfld.long 0x8 13. "DDRE,DMA Disable on Reception Error" "0,1" bitfld.long 0x8 12. "OVRDIS,Overrun Disable" "0,1" bitfld.long 0x8 11. "ONEBIT,One sample bit method enable" "0,1" bitfld.long 0x8 10. "CTSIE,CTS interrupt enable" "0,1" bitfld.long 0x8 9. "CTSE,CTS enable" "0,1" bitfld.long 0x8 8. "RTSE,RTS enable" "0,1" newline bitfld.long 0x8 7. "DMAT,DMA enable transmitter" "0,1" bitfld.long 0x8 6. "DMAR,DMA enable receiver" "0,1" bitfld.long 0x8 5. "SCEN,Smartcard mode enable" "0,1" bitfld.long 0x8 4. "NACK,Smartcard NACK enable" "0,1" bitfld.long 0x8 3. "HDSEL,Half-duplex selection" "0,1" bitfld.long 0x8 2. "IRLP,Ir low-power" "0,1" bitfld.long 0x8 1. "IREN,Ir mode enable" "0,1" bitfld.long 0x8 0. "EIE,Error interrupt enable" "0,1" line.long 0xC "BRR,Baud rate register" hexmask.long.word 0xC 4.--15. 1. "BRR_4_15,BRR_4_15" hexmask.long.byte 0xC 0.--3. 1. "BRR_0_3,BRR_0_3" line.long 0x10 "GTPR,Guard time and prescaler register" hexmask.long.byte 0x10 8.--15. 1. "GT,Guard time value" hexmask.long.byte 0x10 0.--7. 1. "PSC,Prescaler value" line.long 0x14 "RTOR,Receiver timeout register" hexmask.long.byte 0x14 24.--31. 1. "BLEN,Block Length" hexmask.long.tbyte 0x14 0.--23. 1. "RTO,Receiver timeout value" wgroup.long 0x18++0x3 line.long 0x0 "RQR,Request register" bitfld.long 0x0 4. "TXFRQ,Transmit data flush request" "0,1" bitfld.long 0x0 3. "RXFRQ,Receive data flush request" "0,1" bitfld.long 0x0 2. "MMRQ,Mute mode request" "0,1" bitfld.long 0x0 1. "SBKRQ,Send break request" "0,1" bitfld.long 0x0 0. "ABRRQ,Auto baud rate request" "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "ISR,Interrupt & status register" bitfld.long 0x0 27. "TXFT,TXFIFO threshold flag" "0,1" bitfld.long 0x0 26. "RXFT,RXFIFO threshold flag" "0,1" bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time flag" "0,1" bitfld.long 0x0 24. "RXFF,RXFIFO Full" "0,1" bitfld.long 0x0 23. "TXFE,TXFIFO Empty" "0,1" bitfld.long 0x0 22. "REACK,REACK" "0,1" bitfld.long 0x0 21. "TEACK,TEACK" "0,1" bitfld.long 0x0 20. "WUF,WUF" "0,1" newline bitfld.long 0x0 19. "RWU,RWU" "0,1" bitfld.long 0x0 18. "SBKF,SBKF" "0,1" bitfld.long 0x0 17. "CMF,CMF" "0,1" bitfld.long 0x0 16. "BUSY,BUSY" "0,1" bitfld.long 0x0 15. "ABRF,ABRF" "0,1" bitfld.long 0x0 14. "ABRE,ABRE" "0,1" bitfld.long 0x0 13. "UDR,SPI slave underrun error flag" "0,1" bitfld.long 0x0 12. "EOBF,EOBF" "0,1" newline bitfld.long 0x0 11. "RTOF,RTOF" "0,1" bitfld.long 0x0 10. "CTS,CTS" "0,1" bitfld.long 0x0 9. "CTSIF,CTSIF" "0,1" bitfld.long 0x0 8. "LBDF,LBDF" "0,1" bitfld.long 0x0 7. "TXE,TXE" "0,1" bitfld.long 0x0 6. "TC,TC" "0,1" bitfld.long 0x0 5. "RXNE,RXNE" "0,1" bitfld.long 0x0 4. "IDLE,IDLE" "0,1" newline bitfld.long 0x0 3. "ORE,ORE" "0,1" bitfld.long 0x0 2. "NF,NF" "0,1" bitfld.long 0x0 1. "FE,FE" "0,1" bitfld.long 0x0 0. "PE,PE" "0,1" wgroup.long 0x20++0x3 line.long 0x0 "ICR,Interrupt flag clear register" bitfld.long 0x0 20. "WUCF,Wakeup from Stop mode clear flag" "0,1" bitfld.long 0x0 17. "CMCF,Character match clear flag" "0,1" bitfld.long 0x0 13. "UDRCF,SPI slave underrun clear flag" "0,1" bitfld.long 0x0 12. "EOBCF,End of block clear flag" "0,1" bitfld.long 0x0 11. "RTOCF,Receiver timeout clear flag" "0,1" bitfld.long 0x0 9. "CTSCF,CTS clear flag" "0,1" bitfld.long 0x0 8. "LBDCF,LIN break detection clear flag" "0,1" bitfld.long 0x0 7. "TCBGTCF,Transmission complete before Guard time clear flag" "0,1" newline bitfld.long 0x0 6. "TCCF,Transmission complete clear flag" "0,1" bitfld.long 0x0 5. "TXFECF,TXFIFO empty clear flag" "0,1" bitfld.long 0x0 4. "IDLECF,Idle line detected clear flag" "0,1" bitfld.long 0x0 3. "ORECF,Overrun error clear flag" "0,1" bitfld.long 0x0 2. "NCF,Noise detected clear flag" "0,1" bitfld.long 0x0 1. "FECF,Framing error clear flag" "0,1" bitfld.long 0x0 0. "PECF,Parity error clear flag" "0,1" rgroup.long 0x24++0x3 line.long 0x0 "RDR,Receive data register" hexmask.long.word 0x0 0.--8. 1. "RDR,Receive data value" group.long 0x28++0x7 line.long 0x0 "TDR,Transmit data register" hexmask.long.word 0x0 0.--8. 1. "TDR,Transmit data value" line.long 0x4 "PRESC,Prescaler register" hexmask.long.byte 0x4 0.--3. 1. "PRESCALER,Clock prescaler" rgroup.long 0x3EC++0x13 line.long 0x0 "HWCFGR2,USART Hardware Configuration register 2" hexmask.long.byte 0x0 4.--7. 1. "CFG2,CFG2" hexmask.long.byte 0x0 0.--3. 1. "CFG1,CFG1" line.long 0x4 "HWCFGR1,USART Hardware Configuration register 1" hexmask.long.byte 0x4 28.--31. 1. "CFG8,CFG8" hexmask.long.byte 0x4 24.--27. 1. "CFG7,CFG7" hexmask.long.byte 0x4 20.--23. 1. "CFG6,CFG6" hexmask.long.byte 0x4 16.--19. 1. "CFG5,CFG5" hexmask.long.byte 0x4 12.--15. 1. "CFG4,CFG4" hexmask.long.byte 0x4 8.--11. 1. "CFG3,CFG3" hexmask.long.byte 0x4 4.--7. 1. "CFG2,CFG2" hexmask.long.byte 0x4 0.--3. 1. "CFG1,CFG1" line.long 0x8 "VERR,EXTI IP Version register" hexmask.long.byte 0x8 4.--7. 1. "MAJREV,Major Revision number" hexmask.long.byte 0x8 0.--3. 1. "MINREV,Minor Revision number" line.long 0xC "IPIDR,EXTI Identification register" hexmask.long 0xC 0.--31. 1. "IPID,IP Identification" line.long 0x10 "SIDR,EXTI Size ID register" hexmask.long 0x10 0.--31. 1. "SID,Size Identification" tree.end tree "USART4" base ad:0x40010000 group.long 0x0++0x17 line.long 0x0 "CR1,Control register 1" bitfld.long 0x0 31. "RXFFIE,RXFIFO Full interrupt enable" "0,1" bitfld.long 0x0 30. "TXFEIE,TXFIFO empty interrupt enable" "0,1" bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0,1" bitfld.long 0x0 28. "M1,Word length" "0,1" bitfld.long 0x0 27. "EOBIE,End of Block interrupt enable" "0,1" bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0,1" hexmask.long.byte 0x0 21.--25. 1. "DEAT,DEAT" hexmask.long.byte 0x0 16.--20. 1. "DEDT,DEDT" newline bitfld.long 0x0 15. "OVER8,Oversampling mode" "0,1" bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0,1" bitfld.long 0x0 13. "MME,Mute mode enable" "0,1" bitfld.long 0x0 12. "M0,Word length" "0,1" bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0,1" bitfld.long 0x0 10. "PCE,Parity control enable" "0,1" bitfld.long 0x0 9. "PS,Parity selection" "0,1" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0,1" newline bitfld.long 0x0 7. "TXEIE,interrupt enable" "0,1" bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0,1" bitfld.long 0x0 5. "RXNEIE,RXNE interrupt enable" "0,1" bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0,1" bitfld.long 0x0 3. "TE,Transmitter enable" "0,1" bitfld.long 0x0 2. "RE,Receiver enable" "0,1" bitfld.long 0x0 1. "UESM,USART enable in Stop mode" "0,1" bitfld.long 0x0 0. "UE,USART enable" "0,1" line.long 0x4 "CR2,Control register 2" hexmask.long.byte 0x4 28.--31. 1. "ADD4_7,Address of the USART node" hexmask.long.byte 0x4 24.--27. 1. "ADD0_3,Address of the USART node" bitfld.long 0x4 23. "RTOEN,Receiver timeout enable" "0,1" bitfld.long 0x4 21.--22. "ABRMOD,Auto baud rate mode" "0,1,2,3" bitfld.long 0x4 20. "ABREN,Auto baud rate enable" "0,1" bitfld.long 0x4 19. "MSBFIRST,Most significant bit first" "0,1" bitfld.long 0x4 18. "TAINV,Binary data inversion" "0,1" bitfld.long 0x4 17. "TXINV,TX pin active level inversion" "0,1" newline bitfld.long 0x4 16. "RXINV,RX pin active level inversion" "0,1" bitfld.long 0x4 15. "SWAP,Swap TX/RX pins" "0,1" bitfld.long 0x4 14. "LINEN,LIN mode enable" "0,1" bitfld.long 0x4 12.--13. "STOP,STOP bits" "0,1,2,3" bitfld.long 0x4 11. "CLKEN,Clock enable" "0,1" bitfld.long 0x4 10. "CPOL,Clock polarity" "0,1" bitfld.long 0x4 9. "CPHA,Clock phase" "0,1" bitfld.long 0x4 8. "LBCL,Last bit clock pulse" "0,1" newline bitfld.long 0x4 6. "LBDIE,LIN break detection interrupt enable" "0,1" bitfld.long 0x4 5. "LBDL,LIN break detection length" "0,1" bitfld.long 0x4 4. "ADDM7,7-bit Address Detection/4-bit Address Detection" "0,1" bitfld.long 0x4 3. "DIS_NSS,When the DSI_NSS bit is set the NSS pin input will be ignored" "0,1" bitfld.long 0x4 0. "SLVEN,Synchronous Slave mode enable" "0,1" line.long 0x8 "CR3,Control register 3" bitfld.long 0x8 29.--31. "TXFTCFG,TXFIFO threshold configuration" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "RXFTIE,RXFIFO threshold interrupt enable" "0,1" bitfld.long 0x8 25.--27. "RXFTCFG,Receive FIFO threshold configuration" "0,1,2,3,4,5,6,7" bitfld.long 0x8 24. "TCBGTIE,Tr Complete before guard time interrupt enable" "0,1" bitfld.long 0x8 23. "TXFTIE,threshold interrupt enable" "0,1" bitfld.long 0x8 22. "WUFIE,Wakeup from Stop mode interrupt enable" "0,1" bitfld.long 0x8 20.--21. "WUS,Wakeup from Stop mode interrupt flag selection" "0,1,2,3" bitfld.long 0x8 17.--19. "SCARCNT,Smartcard auto-retry count" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 15. "DEP,Driver enable polarity selection" "0,1" bitfld.long 0x8 14. "DEM,Driver enable mode" "0,1" bitfld.long 0x8 13. "DDRE,DMA Disable on Reception Error" "0,1" bitfld.long 0x8 12. "OVRDIS,Overrun Disable" "0,1" bitfld.long 0x8 11. "ONEBIT,One sample bit method enable" "0,1" bitfld.long 0x8 10. "CTSIE,CTS interrupt enable" "0,1" bitfld.long 0x8 9. "CTSE,CTS enable" "0,1" bitfld.long 0x8 8. "RTSE,RTS enable" "0,1" newline bitfld.long 0x8 7. "DMAT,DMA enable transmitter" "0,1" bitfld.long 0x8 6. "DMAR,DMA enable receiver" "0,1" bitfld.long 0x8 5. "SCEN,Smartcard mode enable" "0,1" bitfld.long 0x8 4. "NACK,Smartcard NACK enable" "0,1" bitfld.long 0x8 3. "HDSEL,Half-duplex selection" "0,1" bitfld.long 0x8 2. "IRLP,Ir low-power" "0,1" bitfld.long 0x8 1. "IREN,Ir mode enable" "0,1" bitfld.long 0x8 0. "EIE,Error interrupt enable" "0,1" line.long 0xC "BRR,Baud rate register" hexmask.long.word 0xC 4.--15. 1. "BRR_4_15,BRR_4_15" hexmask.long.byte 0xC 0.--3. 1. "BRR_0_3,BRR_0_3" line.long 0x10 "GTPR,Guard time and prescaler register" hexmask.long.byte 0x10 8.--15. 1. "GT,Guard time value" hexmask.long.byte 0x10 0.--7. 1. "PSC,Prescaler value" line.long 0x14 "RTOR,Receiver timeout register" hexmask.long.byte 0x14 24.--31. 1. "BLEN,Block Length" hexmask.long.tbyte 0x14 0.--23. 1. "RTO,Receiver timeout value" wgroup.long 0x18++0x3 line.long 0x0 "RQR,Request register" bitfld.long 0x0 4. "TXFRQ,Transmit data flush request" "0,1" bitfld.long 0x0 3. "RXFRQ,Receive data flush request" "0,1" bitfld.long 0x0 2. "MMRQ,Mute mode request" "0,1" bitfld.long 0x0 1. "SBKRQ,Send break request" "0,1" bitfld.long 0x0 0. "ABRRQ,Auto baud rate request" "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "ISR,Interrupt & status register" bitfld.long 0x0 27. "TXFT,TXFIFO threshold flag" "0,1" bitfld.long 0x0 26. "RXFT,RXFIFO threshold flag" "0,1" bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time flag" "0,1" bitfld.long 0x0 24. "RXFF,RXFIFO Full" "0,1" bitfld.long 0x0 23. "TXFE,TXFIFO Empty" "0,1" bitfld.long 0x0 22. "REACK,REACK" "0,1" bitfld.long 0x0 21. "TEACK,TEACK" "0,1" bitfld.long 0x0 20. "WUF,WUF" "0,1" newline bitfld.long 0x0 19. "RWU,RWU" "0,1" bitfld.long 0x0 18. "SBKF,SBKF" "0,1" bitfld.long 0x0 17. "CMF,CMF" "0,1" bitfld.long 0x0 16. "BUSY,BUSY" "0,1" bitfld.long 0x0 15. "ABRF,ABRF" "0,1" bitfld.long 0x0 14. "ABRE,ABRE" "0,1" bitfld.long 0x0 13. "UDR,SPI slave underrun error flag" "0,1" bitfld.long 0x0 12. "EOBF,EOBF" "0,1" newline bitfld.long 0x0 11. "RTOF,RTOF" "0,1" bitfld.long 0x0 10. "CTS,CTS" "0,1" bitfld.long 0x0 9. "CTSIF,CTSIF" "0,1" bitfld.long 0x0 8. "LBDF,LBDF" "0,1" bitfld.long 0x0 7. "TXE,TXE" "0,1" bitfld.long 0x0 6. "TC,TC" "0,1" bitfld.long 0x0 5. "RXNE,RXNE" "0,1" bitfld.long 0x0 4. "IDLE,IDLE" "0,1" newline bitfld.long 0x0 3. "ORE,ORE" "0,1" bitfld.long 0x0 2. "NF,NF" "0,1" bitfld.long 0x0 1. "FE,FE" "0,1" bitfld.long 0x0 0. "PE,PE" "0,1" wgroup.long 0x20++0x3 line.long 0x0 "ICR,Interrupt flag clear register" bitfld.long 0x0 20. "WUCF,Wakeup from Stop mode clear flag" "0,1" bitfld.long 0x0 17. "CMCF,Character match clear flag" "0,1" bitfld.long 0x0 13. "UDRCF,SPI slave underrun clear flag" "0,1" bitfld.long 0x0 12. "EOBCF,End of block clear flag" "0,1" bitfld.long 0x0 11. "RTOCF,Receiver timeout clear flag" "0,1" bitfld.long 0x0 9. "CTSCF,CTS clear flag" "0,1" bitfld.long 0x0 8. "LBDCF,LIN break detection clear flag" "0,1" bitfld.long 0x0 7. "TCBGTCF,Transmission complete before Guard time clear flag" "0,1" newline bitfld.long 0x0 6. "TCCF,Transmission complete clear flag" "0,1" bitfld.long 0x0 5. "TXFECF,TXFIFO empty clear flag" "0,1" bitfld.long 0x0 4. "IDLECF,Idle line detected clear flag" "0,1" bitfld.long 0x0 3. "ORECF,Overrun error clear flag" "0,1" bitfld.long 0x0 2. "NCF,Noise detected clear flag" "0,1" bitfld.long 0x0 1. "FECF,Framing error clear flag" "0,1" bitfld.long 0x0 0. "PECF,Parity error clear flag" "0,1" rgroup.long 0x24++0x3 line.long 0x0 "RDR,Receive data register" hexmask.long.word 0x0 0.--8. 1. "RDR,Receive data value" group.long 0x28++0x7 line.long 0x0 "TDR,Transmit data register" hexmask.long.word 0x0 0.--8. 1. "TDR,Transmit data value" line.long 0x4 "PRESC,Prescaler register" hexmask.long.byte 0x4 0.--3. 1. "PRESCALER,Clock prescaler" rgroup.long 0x3EC++0x13 line.long 0x0 "HWCFGR2,USART Hardware Configuration register 2" hexmask.long.byte 0x0 4.--7. 1. "CFG2,CFG2" hexmask.long.byte 0x0 0.--3. 1. "CFG1,CFG1" line.long 0x4 "HWCFGR1,USART Hardware Configuration register 1" hexmask.long.byte 0x4 28.--31. 1. "CFG8,CFG8" hexmask.long.byte 0x4 24.--27. 1. "CFG7,CFG7" hexmask.long.byte 0x4 20.--23. 1. "CFG6,CFG6" hexmask.long.byte 0x4 16.--19. 1. "CFG5,CFG5" hexmask.long.byte 0x4 12.--15. 1. "CFG4,CFG4" hexmask.long.byte 0x4 8.--11. 1. "CFG3,CFG3" hexmask.long.byte 0x4 4.--7. 1. "CFG2,CFG2" hexmask.long.byte 0x4 0.--3. 1. "CFG1,CFG1" line.long 0x8 "VERR,EXTI IP Version register" hexmask.long.byte 0x8 4.--7. 1. "MAJREV,Major Revision number" hexmask.long.byte 0x8 0.--3. 1. "MINREV,Minor Revision number" line.long 0xC "IPIDR,EXTI Identification register" hexmask.long 0xC 0.--31. 1. "IPID,IP Identification" line.long 0x10 "SIDR,EXTI Size ID register" hexmask.long 0x10 0.--31. 1. "SID,Size Identification" tree.end tree "USART5" base ad:0x40011000 group.long 0x0++0x17 line.long 0x0 "CR1,Control register 1" bitfld.long 0x0 31. "RXFFIE,RXFIFO Full interrupt enable" "0,1" bitfld.long 0x0 30. "TXFEIE,TXFIFO empty interrupt enable" "0,1" bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0,1" bitfld.long 0x0 28. "M1,Word length" "0,1" bitfld.long 0x0 27. "EOBIE,End of Block interrupt enable" "0,1" bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0,1" hexmask.long.byte 0x0 21.--25. 1. "DEAT,DEAT" hexmask.long.byte 0x0 16.--20. 1. "DEDT,DEDT" newline bitfld.long 0x0 15. "OVER8,Oversampling mode" "0,1" bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0,1" bitfld.long 0x0 13. "MME,Mute mode enable" "0,1" bitfld.long 0x0 12. "M0,Word length" "0,1" bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0,1" bitfld.long 0x0 10. "PCE,Parity control enable" "0,1" bitfld.long 0x0 9. "PS,Parity selection" "0,1" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0,1" newline bitfld.long 0x0 7. "TXEIE,interrupt enable" "0,1" bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0,1" bitfld.long 0x0 5. "RXNEIE,RXNE interrupt enable" "0,1" bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0,1" bitfld.long 0x0 3. "TE,Transmitter enable" "0,1" bitfld.long 0x0 2. "RE,Receiver enable" "0,1" bitfld.long 0x0 1. "UESM,USART enable in Stop mode" "0,1" bitfld.long 0x0 0. "UE,USART enable" "0,1" line.long 0x4 "CR2,Control register 2" hexmask.long.byte 0x4 28.--31. 1. "ADD4_7,Address of the USART node" hexmask.long.byte 0x4 24.--27. 1. "ADD0_3,Address of the USART node" bitfld.long 0x4 23. "RTOEN,Receiver timeout enable" "0,1" bitfld.long 0x4 21.--22. "ABRMOD,Auto baud rate mode" "0,1,2,3" bitfld.long 0x4 20. "ABREN,Auto baud rate enable" "0,1" bitfld.long 0x4 19. "MSBFIRST,Most significant bit first" "0,1" bitfld.long 0x4 18. "TAINV,Binary data inversion" "0,1" bitfld.long 0x4 17. "TXINV,TX pin active level inversion" "0,1" newline bitfld.long 0x4 16. "RXINV,RX pin active level inversion" "0,1" bitfld.long 0x4 15. "SWAP,Swap TX/RX pins" "0,1" bitfld.long 0x4 14. "LINEN,LIN mode enable" "0,1" bitfld.long 0x4 12.--13. "STOP,STOP bits" "0,1,2,3" bitfld.long 0x4 11. "CLKEN,Clock enable" "0,1" bitfld.long 0x4 10. "CPOL,Clock polarity" "0,1" bitfld.long 0x4 9. "CPHA,Clock phase" "0,1" bitfld.long 0x4 8. "LBCL,Last bit clock pulse" "0,1" newline bitfld.long 0x4 6. "LBDIE,LIN break detection interrupt enable" "0,1" bitfld.long 0x4 5. "LBDL,LIN break detection length" "0,1" bitfld.long 0x4 4. "ADDM7,7-bit Address Detection/4-bit Address Detection" "0,1" bitfld.long 0x4 3. "DIS_NSS,When the DSI_NSS bit is set the NSS pin input will be ignored" "0,1" bitfld.long 0x4 0. "SLVEN,Synchronous Slave mode enable" "0,1" line.long 0x8 "CR3,Control register 3" bitfld.long 0x8 29.--31. "TXFTCFG,TXFIFO threshold configuration" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "RXFTIE,RXFIFO threshold interrupt enable" "0,1" bitfld.long 0x8 25.--27. "RXFTCFG,Receive FIFO threshold configuration" "0,1,2,3,4,5,6,7" bitfld.long 0x8 24. "TCBGTIE,Tr Complete before guard time interrupt enable" "0,1" bitfld.long 0x8 23. "TXFTIE,threshold interrupt enable" "0,1" bitfld.long 0x8 22. "WUFIE,Wakeup from Stop mode interrupt enable" "0,1" bitfld.long 0x8 20.--21. "WUS,Wakeup from Stop mode interrupt flag selection" "0,1,2,3" bitfld.long 0x8 17.--19. "SCARCNT,Smartcard auto-retry count" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 15. "DEP,Driver enable polarity selection" "0,1" bitfld.long 0x8 14. "DEM,Driver enable mode" "0,1" bitfld.long 0x8 13. "DDRE,DMA Disable on Reception Error" "0,1" bitfld.long 0x8 12. "OVRDIS,Overrun Disable" "0,1" bitfld.long 0x8 11. "ONEBIT,One sample bit method enable" "0,1" bitfld.long 0x8 10. "CTSIE,CTS interrupt enable" "0,1" bitfld.long 0x8 9. "CTSE,CTS enable" "0,1" bitfld.long 0x8 8. "RTSE,RTS enable" "0,1" newline bitfld.long 0x8 7. "DMAT,DMA enable transmitter" "0,1" bitfld.long 0x8 6. "DMAR,DMA enable receiver" "0,1" bitfld.long 0x8 5. "SCEN,Smartcard mode enable" "0,1" bitfld.long 0x8 4. "NACK,Smartcard NACK enable" "0,1" bitfld.long 0x8 3. "HDSEL,Half-duplex selection" "0,1" bitfld.long 0x8 2. "IRLP,Ir low-power" "0,1" bitfld.long 0x8 1. "IREN,Ir mode enable" "0,1" bitfld.long 0x8 0. "EIE,Error interrupt enable" "0,1" line.long 0xC "BRR,Baud rate register" hexmask.long.word 0xC 4.--15. 1. "BRR_4_15,BRR_4_15" hexmask.long.byte 0xC 0.--3. 1. "BRR_0_3,BRR_0_3" line.long 0x10 "GTPR,Guard time and prescaler register" hexmask.long.byte 0x10 8.--15. 1. "GT,Guard time value" hexmask.long.byte 0x10 0.--7. 1. "PSC,Prescaler value" line.long 0x14 "RTOR,Receiver timeout register" hexmask.long.byte 0x14 24.--31. 1. "BLEN,Block Length" hexmask.long.tbyte 0x14 0.--23. 1. "RTO,Receiver timeout value" wgroup.long 0x18++0x3 line.long 0x0 "RQR,Request register" bitfld.long 0x0 4. "TXFRQ,Transmit data flush request" "0,1" bitfld.long 0x0 3. "RXFRQ,Receive data flush request" "0,1" bitfld.long 0x0 2. "MMRQ,Mute mode request" "0,1" bitfld.long 0x0 1. "SBKRQ,Send break request" "0,1" bitfld.long 0x0 0. "ABRRQ,Auto baud rate request" "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "ISR,Interrupt & status register" bitfld.long 0x0 27. "TXFT,TXFIFO threshold flag" "0,1" bitfld.long 0x0 26. "RXFT,RXFIFO threshold flag" "0,1" bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time flag" "0,1" bitfld.long 0x0 24. "RXFF,RXFIFO Full" "0,1" bitfld.long 0x0 23. "TXFE,TXFIFO Empty" "0,1" bitfld.long 0x0 22. "REACK,REACK" "0,1" bitfld.long 0x0 21. "TEACK,TEACK" "0,1" bitfld.long 0x0 20. "WUF,WUF" "0,1" newline bitfld.long 0x0 19. "RWU,RWU" "0,1" bitfld.long 0x0 18. "SBKF,SBKF" "0,1" bitfld.long 0x0 17. "CMF,CMF" "0,1" bitfld.long 0x0 16. "BUSY,BUSY" "0,1" bitfld.long 0x0 15. "ABRF,ABRF" "0,1" bitfld.long 0x0 14. "ABRE,ABRE" "0,1" bitfld.long 0x0 13. "UDR,SPI slave underrun error flag" "0,1" bitfld.long 0x0 12. "EOBF,EOBF" "0,1" newline bitfld.long 0x0 11. "RTOF,RTOF" "0,1" bitfld.long 0x0 10. "CTS,CTS" "0,1" bitfld.long 0x0 9. "CTSIF,CTSIF" "0,1" bitfld.long 0x0 8. "LBDF,LBDF" "0,1" bitfld.long 0x0 7. "TXE,TXE" "0,1" bitfld.long 0x0 6. "TC,TC" "0,1" bitfld.long 0x0 5. "RXNE,RXNE" "0,1" bitfld.long 0x0 4. "IDLE,IDLE" "0,1" newline bitfld.long 0x0 3. "ORE,ORE" "0,1" bitfld.long 0x0 2. "NF,NF" "0,1" bitfld.long 0x0 1. "FE,FE" "0,1" bitfld.long 0x0 0. "PE,PE" "0,1" wgroup.long 0x20++0x3 line.long 0x0 "ICR,Interrupt flag clear register" bitfld.long 0x0 20. "WUCF,Wakeup from Stop mode clear flag" "0,1" bitfld.long 0x0 17. "CMCF,Character match clear flag" "0,1" bitfld.long 0x0 13. "UDRCF,SPI slave underrun clear flag" "0,1" bitfld.long 0x0 12. "EOBCF,End of block clear flag" "0,1" bitfld.long 0x0 11. "RTOCF,Receiver timeout clear flag" "0,1" bitfld.long 0x0 9. "CTSCF,CTS clear flag" "0,1" bitfld.long 0x0 8. "LBDCF,LIN break detection clear flag" "0,1" bitfld.long 0x0 7. "TCBGTCF,Transmission complete before Guard time clear flag" "0,1" newline bitfld.long 0x0 6. "TCCF,Transmission complete clear flag" "0,1" bitfld.long 0x0 5. "TXFECF,TXFIFO empty clear flag" "0,1" bitfld.long 0x0 4. "IDLECF,Idle line detected clear flag" "0,1" bitfld.long 0x0 3. "ORECF,Overrun error clear flag" "0,1" bitfld.long 0x0 2. "NCF,Noise detected clear flag" "0,1" bitfld.long 0x0 1. "FECF,Framing error clear flag" "0,1" bitfld.long 0x0 0. "PECF,Parity error clear flag" "0,1" rgroup.long 0x24++0x3 line.long 0x0 "RDR,Receive data register" hexmask.long.word 0x0 0.--8. 1. "RDR,Receive data value" group.long 0x28++0x7 line.long 0x0 "TDR,Transmit data register" hexmask.long.word 0x0 0.--8. 1. "TDR,Transmit data value" line.long 0x4 "PRESC,Prescaler register" hexmask.long.byte 0x4 0.--3. 1. "PRESCALER,Clock prescaler" rgroup.long 0x3EC++0x13 line.long 0x0 "HWCFGR2,USART Hardware Configuration register 2" hexmask.long.byte 0x0 4.--7. 1. "CFG2,CFG2" hexmask.long.byte 0x0 0.--3. 1. "CFG1,CFG1" line.long 0x4 "HWCFGR1,USART Hardware Configuration register 1" hexmask.long.byte 0x4 28.--31. 1. "CFG8,CFG8" hexmask.long.byte 0x4 24.--27. 1. "CFG7,CFG7" hexmask.long.byte 0x4 20.--23. 1. "CFG6,CFG6" hexmask.long.byte 0x4 16.--19. 1. "CFG5,CFG5" hexmask.long.byte 0x4 12.--15. 1. "CFG4,CFG4" hexmask.long.byte 0x4 8.--11. 1. "CFG3,CFG3" hexmask.long.byte 0x4 4.--7. 1. "CFG2,CFG2" hexmask.long.byte 0x4 0.--3. 1. "CFG1,CFG1" line.long 0x8 "VERR,EXTI IP Version register" hexmask.long.byte 0x8 4.--7. 1. "MAJREV,Major Revision number" hexmask.long.byte 0x8 0.--3. 1. "MINREV,Minor Revision number" line.long 0xC "IPIDR,EXTI Identification register" hexmask.long 0xC 0.--31. 1. "IPID,IP Identification" line.long 0x10 "SIDR,EXTI Size ID register" hexmask.long 0x10 0.--31. 1. "SID,Size Identification" tree.end tree "USART6" base ad:0x44003000 group.long 0x0++0x17 line.long 0x0 "CR1,Control register 1" bitfld.long 0x0 31. "RXFFIE,RXFIFO Full interrupt enable" "0,1" bitfld.long 0x0 30. "TXFEIE,TXFIFO empty interrupt enable" "0,1" bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0,1" bitfld.long 0x0 28. "M1,Word length" "0,1" bitfld.long 0x0 27. "EOBIE,End of Block interrupt enable" "0,1" bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0,1" hexmask.long.byte 0x0 21.--25. 1. "DEAT,DEAT" hexmask.long.byte 0x0 16.--20. 1. "DEDT,DEDT" newline bitfld.long 0x0 15. "OVER8,Oversampling mode" "0,1" bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0,1" bitfld.long 0x0 13. "MME,Mute mode enable" "0,1" bitfld.long 0x0 12. "M0,Word length" "0,1" bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0,1" bitfld.long 0x0 10. "PCE,Parity control enable" "0,1" bitfld.long 0x0 9. "PS,Parity selection" "0,1" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0,1" newline bitfld.long 0x0 7. "TXEIE,interrupt enable" "0,1" bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0,1" bitfld.long 0x0 5. "RXNEIE,RXNE interrupt enable" "0,1" bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0,1" bitfld.long 0x0 3. "TE,Transmitter enable" "0,1" bitfld.long 0x0 2. "RE,Receiver enable" "0,1" bitfld.long 0x0 1. "UESM,USART enable in Stop mode" "0,1" bitfld.long 0x0 0. "UE,USART enable" "0,1" line.long 0x4 "CR2,Control register 2" hexmask.long.byte 0x4 28.--31. 1. "ADD4_7,Address of the USART node" hexmask.long.byte 0x4 24.--27. 1. "ADD0_3,Address of the USART node" bitfld.long 0x4 23. "RTOEN,Receiver timeout enable" "0,1" bitfld.long 0x4 21.--22. "ABRMOD,Auto baud rate mode" "0,1,2,3" bitfld.long 0x4 20. "ABREN,Auto baud rate enable" "0,1" bitfld.long 0x4 19. "MSBFIRST,Most significant bit first" "0,1" bitfld.long 0x4 18. "TAINV,Binary data inversion" "0,1" bitfld.long 0x4 17. "TXINV,TX pin active level inversion" "0,1" newline bitfld.long 0x4 16. "RXINV,RX pin active level inversion" "0,1" bitfld.long 0x4 15. "SWAP,Swap TX/RX pins" "0,1" bitfld.long 0x4 14. "LINEN,LIN mode enable" "0,1" bitfld.long 0x4 12.--13. "STOP,STOP bits" "0,1,2,3" bitfld.long 0x4 11. "CLKEN,Clock enable" "0,1" bitfld.long 0x4 10. "CPOL,Clock polarity" "0,1" bitfld.long 0x4 9. "CPHA,Clock phase" "0,1" bitfld.long 0x4 8. "LBCL,Last bit clock pulse" "0,1" newline bitfld.long 0x4 6. "LBDIE,LIN break detection interrupt enable" "0,1" bitfld.long 0x4 5. "LBDL,LIN break detection length" "0,1" bitfld.long 0x4 4. "ADDM7,7-bit Address Detection/4-bit Address Detection" "0,1" bitfld.long 0x4 3. "DIS_NSS,When the DSI_NSS bit is set the NSS pin input will be ignored" "0,1" bitfld.long 0x4 0. "SLVEN,Synchronous Slave mode enable" "0,1" line.long 0x8 "CR3,Control register 3" bitfld.long 0x8 29.--31. "TXFTCFG,TXFIFO threshold configuration" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "RXFTIE,RXFIFO threshold interrupt enable" "0,1" bitfld.long 0x8 25.--27. "RXFTCFG,Receive FIFO threshold configuration" "0,1,2,3,4,5,6,7" bitfld.long 0x8 24. "TCBGTIE,Tr Complete before guard time interrupt enable" "0,1" bitfld.long 0x8 23. "TXFTIE,threshold interrupt enable" "0,1" bitfld.long 0x8 22. "WUFIE,Wakeup from Stop mode interrupt enable" "0,1" bitfld.long 0x8 20.--21. "WUS,Wakeup from Stop mode interrupt flag selection" "0,1,2,3" bitfld.long 0x8 17.--19. "SCARCNT,Smartcard auto-retry count" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 15. "DEP,Driver enable polarity selection" "0,1" bitfld.long 0x8 14. "DEM,Driver enable mode" "0,1" bitfld.long 0x8 13. "DDRE,DMA Disable on Reception Error" "0,1" bitfld.long 0x8 12. "OVRDIS,Overrun Disable" "0,1" bitfld.long 0x8 11. "ONEBIT,One sample bit method enable" "0,1" bitfld.long 0x8 10. "CTSIE,CTS interrupt enable" "0,1" bitfld.long 0x8 9. "CTSE,CTS enable" "0,1" bitfld.long 0x8 8. "RTSE,RTS enable" "0,1" newline bitfld.long 0x8 7. "DMAT,DMA enable transmitter" "0,1" bitfld.long 0x8 6. "DMAR,DMA enable receiver" "0,1" bitfld.long 0x8 5. "SCEN,Smartcard mode enable" "0,1" bitfld.long 0x8 4. "NACK,Smartcard NACK enable" "0,1" bitfld.long 0x8 3. "HDSEL,Half-duplex selection" "0,1" bitfld.long 0x8 2. "IRLP,Ir low-power" "0,1" bitfld.long 0x8 1. "IREN,Ir mode enable" "0,1" bitfld.long 0x8 0. "EIE,Error interrupt enable" "0,1" line.long 0xC "BRR,Baud rate register" hexmask.long.word 0xC 4.--15. 1. "BRR_4_15,BRR_4_15" hexmask.long.byte 0xC 0.--3. 1. "BRR_0_3,BRR_0_3" line.long 0x10 "GTPR,Guard time and prescaler register" hexmask.long.byte 0x10 8.--15. 1. "GT,Guard time value" hexmask.long.byte 0x10 0.--7. 1. "PSC,Prescaler value" line.long 0x14 "RTOR,Receiver timeout register" hexmask.long.byte 0x14 24.--31. 1. "BLEN,Block Length" hexmask.long.tbyte 0x14 0.--23. 1. "RTO,Receiver timeout value" wgroup.long 0x18++0x3 line.long 0x0 "RQR,Request register" bitfld.long 0x0 4. "TXFRQ,Transmit data flush request" "0,1" bitfld.long 0x0 3. "RXFRQ,Receive data flush request" "0,1" bitfld.long 0x0 2. "MMRQ,Mute mode request" "0,1" bitfld.long 0x0 1. "SBKRQ,Send break request" "0,1" bitfld.long 0x0 0. "ABRRQ,Auto baud rate request" "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "ISR,Interrupt & status register" bitfld.long 0x0 27. "TXFT,TXFIFO threshold flag" "0,1" bitfld.long 0x0 26. "RXFT,RXFIFO threshold flag" "0,1" bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time flag" "0,1" bitfld.long 0x0 24. "RXFF,RXFIFO Full" "0,1" bitfld.long 0x0 23. "TXFE,TXFIFO Empty" "0,1" bitfld.long 0x0 22. "REACK,REACK" "0,1" bitfld.long 0x0 21. "TEACK,TEACK" "0,1" bitfld.long 0x0 20. "WUF,WUF" "0,1" newline bitfld.long 0x0 19. "RWU,RWU" "0,1" bitfld.long 0x0 18. "SBKF,SBKF" "0,1" bitfld.long 0x0 17. "CMF,CMF" "0,1" bitfld.long 0x0 16. "BUSY,BUSY" "0,1" bitfld.long 0x0 15. "ABRF,ABRF" "0,1" bitfld.long 0x0 14. "ABRE,ABRE" "0,1" bitfld.long 0x0 13. "UDR,SPI slave underrun error flag" "0,1" bitfld.long 0x0 12. "EOBF,EOBF" "0,1" newline bitfld.long 0x0 11. "RTOF,RTOF" "0,1" bitfld.long 0x0 10. "CTS,CTS" "0,1" bitfld.long 0x0 9. "CTSIF,CTSIF" "0,1" bitfld.long 0x0 8. "LBDF,LBDF" "0,1" bitfld.long 0x0 7. "TXE,TXE" "0,1" bitfld.long 0x0 6. "TC,TC" "0,1" bitfld.long 0x0 5. "RXNE,RXNE" "0,1" bitfld.long 0x0 4. "IDLE,IDLE" "0,1" newline bitfld.long 0x0 3. "ORE,ORE" "0,1" bitfld.long 0x0 2. "NF,NF" "0,1" bitfld.long 0x0 1. "FE,FE" "0,1" bitfld.long 0x0 0. "PE,PE" "0,1" wgroup.long 0x20++0x3 line.long 0x0 "ICR,Interrupt flag clear register" bitfld.long 0x0 20. "WUCF,Wakeup from Stop mode clear flag" "0,1" bitfld.long 0x0 17. "CMCF,Character match clear flag" "0,1" bitfld.long 0x0 13. "UDRCF,SPI slave underrun clear flag" "0,1" bitfld.long 0x0 12. "EOBCF,End of block clear flag" "0,1" bitfld.long 0x0 11. "RTOCF,Receiver timeout clear flag" "0,1" bitfld.long 0x0 9. "CTSCF,CTS clear flag" "0,1" bitfld.long 0x0 8. "LBDCF,LIN break detection clear flag" "0,1" bitfld.long 0x0 7. "TCBGTCF,Transmission complete before Guard time clear flag" "0,1" newline bitfld.long 0x0 6. "TCCF,Transmission complete clear flag" "0,1" bitfld.long 0x0 5. "TXFECF,TXFIFO empty clear flag" "0,1" bitfld.long 0x0 4. "IDLECF,Idle line detected clear flag" "0,1" bitfld.long 0x0 3. "ORECF,Overrun error clear flag" "0,1" bitfld.long 0x0 2. "NCF,Noise detected clear flag" "0,1" bitfld.long 0x0 1. "FECF,Framing error clear flag" "0,1" bitfld.long 0x0 0. "PECF,Parity error clear flag" "0,1" rgroup.long 0x24++0x3 line.long 0x0 "RDR,Receive data register" hexmask.long.word 0x0 0.--8. 1. "RDR,Receive data value" group.long 0x28++0x7 line.long 0x0 "TDR,Transmit data register" hexmask.long.word 0x0 0.--8. 1. "TDR,Transmit data value" line.long 0x4 "PRESC,Prescaler register" hexmask.long.byte 0x4 0.--3. 1. "PRESCALER,Clock prescaler" rgroup.long 0x3EC++0x13 line.long 0x0 "HWCFGR2,USART Hardware Configuration register 2" hexmask.long.byte 0x0 4.--7. 1. "CFG2,CFG2" hexmask.long.byte 0x0 0.--3. 1. "CFG1,CFG1" line.long 0x4 "HWCFGR1,USART Hardware Configuration register 1" hexmask.long.byte 0x4 28.--31. 1. "CFG8,CFG8" hexmask.long.byte 0x4 24.--27. 1. "CFG7,CFG7" hexmask.long.byte 0x4 20.--23. 1. "CFG6,CFG6" hexmask.long.byte 0x4 16.--19. 1. "CFG5,CFG5" hexmask.long.byte 0x4 12.--15. 1. "CFG4,CFG4" hexmask.long.byte 0x4 8.--11. 1. "CFG3,CFG3" hexmask.long.byte 0x4 4.--7. 1. "CFG2,CFG2" hexmask.long.byte 0x4 0.--3. 1. "CFG1,CFG1" line.long 0x8 "VERR,EXTI IP Version register" hexmask.long.byte 0x8 4.--7. 1. "MAJREV,Major Revision number" hexmask.long.byte 0x8 0.--3. 1. "MINREV,Minor Revision number" line.long 0xC "IPIDR,EXTI Identification register" hexmask.long 0xC 0.--31. 1. "IPID,IP Identification" line.long 0x10 "SIDR,EXTI Size ID register" hexmask.long 0x10 0.--31. 1. "SID,Size Identification" tree.end endif sif (cpuis("STM32MP153*")) tree "USART7" base ad:0x40018000 group.long 0x0++0x17 line.long 0x0 "CR1,Control register 1" bitfld.long 0x0 31. "RXFFIE,RXFIFO Full interrupt enable" "0,1" bitfld.long 0x0 30. "TXFEIE,TXFIFO empty interrupt enable" "0,1" bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0,1" bitfld.long 0x0 28. "M1,Word length" "0,1" bitfld.long 0x0 27. "EOBIE,End of Block interrupt enable" "0,1" bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0,1" hexmask.long.byte 0x0 21.--25. 1. "DEAT,DEAT" hexmask.long.byte 0x0 16.--20. 1. "DEDT,DEDT" newline bitfld.long 0x0 15. "OVER8,Oversampling mode" "0,1" bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0,1" bitfld.long 0x0 13. "MME,Mute mode enable" "0,1" bitfld.long 0x0 12. "M0,Word length" "0,1" bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0,1" bitfld.long 0x0 10. "PCE,Parity control enable" "0,1" bitfld.long 0x0 9. "PS,Parity selection" "0,1" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0,1" newline bitfld.long 0x0 7. "TXEIE,interrupt enable" "0,1" bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0,1" bitfld.long 0x0 5. "RXNEIE,RXNE interrupt enable" "0,1" bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0,1" bitfld.long 0x0 3. "TE,Transmitter enable" "0,1" bitfld.long 0x0 2. "RE,Receiver enable" "0,1" bitfld.long 0x0 1. "UESM,USART enable in Stop mode" "0,1" bitfld.long 0x0 0. "UE,USART enable" "0,1" line.long 0x4 "CR2,Control register 2" hexmask.long.byte 0x4 28.--31. 1. "ADD4_7,Address of the USART node" hexmask.long.byte 0x4 24.--27. 1. "ADD0_3,Address of the USART node" bitfld.long 0x4 23. "RTOEN,Receiver timeout enable" "0,1" bitfld.long 0x4 21.--22. "ABRMOD,Auto baud rate mode" "0,1,2,3" bitfld.long 0x4 20. "ABREN,Auto baud rate enable" "0,1" bitfld.long 0x4 19. "MSBFIRST,Most significant bit first" "0,1" bitfld.long 0x4 18. "TAINV,Binary data inversion" "0,1" bitfld.long 0x4 17. "TXINV,TX pin active level inversion" "0,1" newline bitfld.long 0x4 16. "RXINV,RX pin active level inversion" "0,1" bitfld.long 0x4 15. "SWAP,Swap TX/RX pins" "0,1" bitfld.long 0x4 14. "LINEN,LIN mode enable" "0,1" bitfld.long 0x4 12.--13. "STOP,STOP bits" "0,1,2,3" bitfld.long 0x4 11. "CLKEN,Clock enable" "0,1" bitfld.long 0x4 10. "CPOL,Clock polarity" "0,1" bitfld.long 0x4 9. "CPHA,Clock phase" "0,1" bitfld.long 0x4 8. "LBCL,Last bit clock pulse" "0,1" newline bitfld.long 0x4 6. "LBDIE,LIN break detection interrupt enable" "0,1" bitfld.long 0x4 5. "LBDL,LIN break detection length" "0,1" bitfld.long 0x4 4. "ADDM7,7-bit Address Detection/4-bit Address Detection" "0,1" bitfld.long 0x4 3. "DIS_NSS,When the DSI_NSS bit is set the NSS pin input will be ignored" "0,1" bitfld.long 0x4 0. "SLVEN,Synchronous Slave mode enable" "0,1" line.long 0x8 "CR3,Control register 3" bitfld.long 0x8 29.--31. "TXFTCFG,TXFIFO threshold configuration" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "RXFTIE,RXFIFO threshold interrupt enable" "0,1" bitfld.long 0x8 25.--27. "RXFTCFG,Receive FIFO threshold configuration" "0,1,2,3,4,5,6,7" bitfld.long 0x8 24. "TCBGTIE,Tr Complete before guard time interrupt enable" "0,1" bitfld.long 0x8 23. "TXFTIE,threshold interrupt enable" "0,1" bitfld.long 0x8 22. "WUFIE,Wakeup from Stop mode interrupt enable" "0,1" bitfld.long 0x8 20.--21. "WUS,Wakeup from Stop mode interrupt flag selection" "0,1,2,3" bitfld.long 0x8 17.--19. "SCARCNT,Smartcard auto-retry count" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 15. "DEP,Driver enable polarity selection" "0,1" bitfld.long 0x8 14. "DEM,Driver enable mode" "0,1" bitfld.long 0x8 13. "DDRE,DMA Disable on Reception Error" "0,1" bitfld.long 0x8 12. "OVRDIS,Overrun Disable" "0,1" bitfld.long 0x8 11. "ONEBIT,One sample bit method enable" "0,1" bitfld.long 0x8 10. "CTSIE,CTS interrupt enable" "0,1" bitfld.long 0x8 9. "CTSE,CTS enable" "0,1" bitfld.long 0x8 8. "RTSE,RTS enable" "0,1" newline bitfld.long 0x8 7. "DMAT,DMA enable transmitter" "0,1" bitfld.long 0x8 6. "DMAR,DMA enable receiver" "0,1" bitfld.long 0x8 5. "SCEN,Smartcard mode enable" "0,1" bitfld.long 0x8 4. "NACK,Smartcard NACK enable" "0,1" bitfld.long 0x8 3. "HDSEL,Half-duplex selection" "0,1" bitfld.long 0x8 2. "IRLP,Ir low-power" "0,1" bitfld.long 0x8 1. "IREN,Ir mode enable" "0,1" bitfld.long 0x8 0. "EIE,Error interrupt enable" "0,1" line.long 0xC "BRR,Baud rate register" hexmask.long.word 0xC 4.--15. 1. "BRR_4_15,BRR_4_15" hexmask.long.byte 0xC 0.--3. 1. "BRR_0_3,BRR_0_3" line.long 0x10 "GTPR,Guard time and prescaler register" hexmask.long.byte 0x10 8.--15. 1. "GT,Guard time value" hexmask.long.byte 0x10 0.--7. 1. "PSC,Prescaler value" line.long 0x14 "RTOR,Receiver timeout register" hexmask.long.byte 0x14 24.--31. 1. "BLEN,Block Length" hexmask.long.tbyte 0x14 0.--23. 1. "RTO,Receiver timeout value" wgroup.long 0x18++0x3 line.long 0x0 "RQR,Request register" bitfld.long 0x0 4. "TXFRQ,Transmit data flush request" "0,1" bitfld.long 0x0 3. "RXFRQ,Receive data flush request" "0,1" bitfld.long 0x0 2. "MMRQ,Mute mode request" "0,1" bitfld.long 0x0 1. "SBKRQ,Send break request" "0,1" bitfld.long 0x0 0. "ABRRQ,Auto baud rate request" "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "ISR,Interrupt & status register" bitfld.long 0x0 27. "TXFT,TXFIFO threshold flag" "0,1" bitfld.long 0x0 26. "RXFT,RXFIFO threshold flag" "0,1" bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time flag" "0,1" bitfld.long 0x0 24. "RXFF,RXFIFO Full" "0,1" bitfld.long 0x0 23. "TXFE,TXFIFO Empty" "0,1" bitfld.long 0x0 22. "REACK,REACK" "0,1" bitfld.long 0x0 21. "TEACK,TEACK" "0,1" bitfld.long 0x0 20. "WUF,WUF" "0,1" newline bitfld.long 0x0 19. "RWU,RWU" "0,1" bitfld.long 0x0 18. "SBKF,SBKF" "0,1" bitfld.long 0x0 17. "CMF,CMF" "0,1" bitfld.long 0x0 16. "BUSY,BUSY" "0,1" bitfld.long 0x0 15. "ABRF,ABRF" "0,1" bitfld.long 0x0 14. "ABRE,ABRE" "0,1" bitfld.long 0x0 13. "UDR,SPI slave underrun error flag" "0,1" bitfld.long 0x0 12. "EOBF,EOBF" "0,1" newline bitfld.long 0x0 11. "RTOF,RTOF" "0,1" bitfld.long 0x0 10. "CTS,CTS" "0,1" bitfld.long 0x0 9. "CTSIF,CTSIF" "0,1" bitfld.long 0x0 8. "LBDF,LBDF" "0,1" bitfld.long 0x0 7. "TXE,TXE" "0,1" bitfld.long 0x0 6. "TC,TC" "0,1" bitfld.long 0x0 5. "RXNE,RXNE" "0,1" bitfld.long 0x0 4. "IDLE,IDLE" "0,1" newline bitfld.long 0x0 3. "ORE,ORE" "0,1" bitfld.long 0x0 2. "NF,NF" "0,1" bitfld.long 0x0 1. "FE,FE" "0,1" bitfld.long 0x0 0. "PE,PE" "0,1" wgroup.long 0x20++0x3 line.long 0x0 "ICR,Interrupt flag clear register" bitfld.long 0x0 20. "WUCF,Wakeup from Stop mode clear flag" "0,1" bitfld.long 0x0 17. "CMCF,Character match clear flag" "0,1" bitfld.long 0x0 13. "UDRCF,SPI slave underrun clear flag" "0,1" bitfld.long 0x0 12. "EOBCF,End of block clear flag" "0,1" bitfld.long 0x0 11. "RTOCF,Receiver timeout clear flag" "0,1" bitfld.long 0x0 9. "CTSCF,CTS clear flag" "0,1" bitfld.long 0x0 8. "LBDCF,LIN break detection clear flag" "0,1" bitfld.long 0x0 7. "TCBGTCF,Transmission complete before Guard time clear flag" "0,1" newline bitfld.long 0x0 6. "TCCF,Transmission complete clear flag" "0,1" bitfld.long 0x0 5. "TXFECF,TXFIFO empty clear flag" "0,1" bitfld.long 0x0 4. "IDLECF,Idle line detected clear flag" "0,1" bitfld.long 0x0 3. "ORECF,Overrun error clear flag" "0,1" bitfld.long 0x0 2. "NCF,Noise detected clear flag" "0,1" bitfld.long 0x0 1. "FECF,Framing error clear flag" "0,1" bitfld.long 0x0 0. "PECF,Parity error clear flag" "0,1" rgroup.long 0x24++0x3 line.long 0x0 "RDR,Receive data register" hexmask.long.word 0x0 0.--8. 1. "RDR,Receive data value" group.long 0x28++0x7 line.long 0x0 "TDR,Transmit data register" hexmask.long.word 0x0 0.--8. 1. "TDR,Transmit data value" line.long 0x4 "PRESC,Prescaler register" hexmask.long.byte 0x4 0.--3. 1. "PRESCALER,Clock prescaler" rgroup.long 0x3EC++0x13 line.long 0x0 "HWCFGR2,USART Hardware Configuration register 2" hexmask.long.byte 0x0 4.--7. 1. "CFG2,CFG2" hexmask.long.byte 0x0 0.--3. 1. "CFG1,CFG1" line.long 0x4 "HWCFGR1,USART Hardware Configuration register 1" hexmask.long.byte 0x4 28.--31. 1. "CFG8,CFG8" hexmask.long.byte 0x4 24.--27. 1. "CFG7,CFG7" hexmask.long.byte 0x4 20.--23. 1. "CFG6,CFG6" hexmask.long.byte 0x4 16.--19. 1. "CFG5,CFG5" hexmask.long.byte 0x4 12.--15. 1. "CFG4,CFG4" hexmask.long.byte 0x4 8.--11. 1. "CFG3,CFG3" hexmask.long.byte 0x4 4.--7. 1. "CFG2,CFG2" hexmask.long.byte 0x4 0.--3. 1. "CFG1,CFG1" line.long 0x8 "VERR,EXTI IP Version register" hexmask.long.byte 0x8 4.--7. 1. "MAJREV,Major Revision number" hexmask.long.byte 0x8 0.--3. 1. "MINREV,Minor Revision number" line.long 0xC "IPIDR,EXTI Identification register" hexmask.long 0xC 0.--31. 1. "IPID,IP Identification" line.long 0x10 "SIDR,EXTI Size ID register" hexmask.long 0x10 0.--31. 1. "SID,Size Identification" tree.end tree "USART8" base ad:0x40019000 group.long 0x0++0x17 line.long 0x0 "CR1,Control register 1" bitfld.long 0x0 31. "RXFFIE,RXFIFO Full interrupt enable" "0,1" bitfld.long 0x0 30. "TXFEIE,TXFIFO empty interrupt enable" "0,1" bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0,1" bitfld.long 0x0 28. "M1,Word length" "0,1" bitfld.long 0x0 27. "EOBIE,End of Block interrupt enable" "0,1" bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0,1" hexmask.long.byte 0x0 21.--25. 1. "DEAT,DEAT" hexmask.long.byte 0x0 16.--20. 1. "DEDT,DEDT" newline bitfld.long 0x0 15. "OVER8,Oversampling mode" "0,1" bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0,1" bitfld.long 0x0 13. "MME,Mute mode enable" "0,1" bitfld.long 0x0 12. "M0,Word length" "0,1" bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0,1" bitfld.long 0x0 10. "PCE,Parity control enable" "0,1" bitfld.long 0x0 9. "PS,Parity selection" "0,1" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0,1" newline bitfld.long 0x0 7. "TXEIE,interrupt enable" "0,1" bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0,1" bitfld.long 0x0 5. "RXNEIE,RXNE interrupt enable" "0,1" bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0,1" bitfld.long 0x0 3. "TE,Transmitter enable" "0,1" bitfld.long 0x0 2. "RE,Receiver enable" "0,1" bitfld.long 0x0 1. "UESM,USART enable in Stop mode" "0,1" bitfld.long 0x0 0. "UE,USART enable" "0,1" line.long 0x4 "CR2,Control register 2" hexmask.long.byte 0x4 28.--31. 1. "ADD4_7,Address of the USART node" hexmask.long.byte 0x4 24.--27. 1. "ADD0_3,Address of the USART node" bitfld.long 0x4 23. "RTOEN,Receiver timeout enable" "0,1" bitfld.long 0x4 21.--22. "ABRMOD,Auto baud rate mode" "0,1,2,3" bitfld.long 0x4 20. "ABREN,Auto baud rate enable" "0,1" bitfld.long 0x4 19. "MSBFIRST,Most significant bit first" "0,1" bitfld.long 0x4 18. "TAINV,Binary data inversion" "0,1" bitfld.long 0x4 17. "TXINV,TX pin active level inversion" "0,1" newline bitfld.long 0x4 16. "RXINV,RX pin active level inversion" "0,1" bitfld.long 0x4 15. "SWAP,Swap TX/RX pins" "0,1" bitfld.long 0x4 14. "LINEN,LIN mode enable" "0,1" bitfld.long 0x4 12.--13. "STOP,STOP bits" "0,1,2,3" bitfld.long 0x4 11. "CLKEN,Clock enable" "0,1" bitfld.long 0x4 10. "CPOL,Clock polarity" "0,1" bitfld.long 0x4 9. "CPHA,Clock phase" "0,1" bitfld.long 0x4 8. "LBCL,Last bit clock pulse" "0,1" newline bitfld.long 0x4 6. "LBDIE,LIN break detection interrupt enable" "0,1" bitfld.long 0x4 5. "LBDL,LIN break detection length" "0,1" bitfld.long 0x4 4. "ADDM7,7-bit Address Detection/4-bit Address Detection" "0,1" bitfld.long 0x4 3. "DIS_NSS,When the DSI_NSS bit is set the NSS pin input will be ignored" "0,1" bitfld.long 0x4 0. "SLVEN,Synchronous Slave mode enable" "0,1" line.long 0x8 "CR3,Control register 3" bitfld.long 0x8 29.--31. "TXFTCFG,TXFIFO threshold configuration" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "RXFTIE,RXFIFO threshold interrupt enable" "0,1" bitfld.long 0x8 25.--27. "RXFTCFG,Receive FIFO threshold configuration" "0,1,2,3,4,5,6,7" bitfld.long 0x8 24. "TCBGTIE,Tr Complete before guard time interrupt enable" "0,1" bitfld.long 0x8 23. "TXFTIE,threshold interrupt enable" "0,1" bitfld.long 0x8 22. "WUFIE,Wakeup from Stop mode interrupt enable" "0,1" bitfld.long 0x8 20.--21. "WUS,Wakeup from Stop mode interrupt flag selection" "0,1,2,3" bitfld.long 0x8 17.--19. "SCARCNT,Smartcard auto-retry count" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 15. "DEP,Driver enable polarity selection" "0,1" bitfld.long 0x8 14. "DEM,Driver enable mode" "0,1" bitfld.long 0x8 13. "DDRE,DMA Disable on Reception Error" "0,1" bitfld.long 0x8 12. "OVRDIS,Overrun Disable" "0,1" bitfld.long 0x8 11. "ONEBIT,One sample bit method enable" "0,1" bitfld.long 0x8 10. "CTSIE,CTS interrupt enable" "0,1" bitfld.long 0x8 9. "CTSE,CTS enable" "0,1" bitfld.long 0x8 8. "RTSE,RTS enable" "0,1" newline bitfld.long 0x8 7. "DMAT,DMA enable transmitter" "0,1" bitfld.long 0x8 6. "DMAR,DMA enable receiver" "0,1" bitfld.long 0x8 5. "SCEN,Smartcard mode enable" "0,1" bitfld.long 0x8 4. "NACK,Smartcard NACK enable" "0,1" bitfld.long 0x8 3. "HDSEL,Half-duplex selection" "0,1" bitfld.long 0x8 2. "IRLP,Ir low-power" "0,1" bitfld.long 0x8 1. "IREN,Ir mode enable" "0,1" bitfld.long 0x8 0. "EIE,Error interrupt enable" "0,1" line.long 0xC "BRR,Baud rate register" hexmask.long.word 0xC 4.--15. 1. "BRR_4_15,BRR_4_15" hexmask.long.byte 0xC 0.--3. 1. "BRR_0_3,BRR_0_3" line.long 0x10 "GTPR,Guard time and prescaler register" hexmask.long.byte 0x10 8.--15. 1. "GT,Guard time value" hexmask.long.byte 0x10 0.--7. 1. "PSC,Prescaler value" line.long 0x14 "RTOR,Receiver timeout register" hexmask.long.byte 0x14 24.--31. 1. "BLEN,Block Length" hexmask.long.tbyte 0x14 0.--23. 1. "RTO,Receiver timeout value" wgroup.long 0x18++0x3 line.long 0x0 "RQR,Request register" bitfld.long 0x0 4. "TXFRQ,Transmit data flush request" "0,1" bitfld.long 0x0 3. "RXFRQ,Receive data flush request" "0,1" bitfld.long 0x0 2. "MMRQ,Mute mode request" "0,1" bitfld.long 0x0 1. "SBKRQ,Send break request" "0,1" bitfld.long 0x0 0. "ABRRQ,Auto baud rate request" "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "ISR,Interrupt & status register" bitfld.long 0x0 27. "TXFT,TXFIFO threshold flag" "0,1" bitfld.long 0x0 26. "RXFT,RXFIFO threshold flag" "0,1" bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time flag" "0,1" bitfld.long 0x0 24. "RXFF,RXFIFO Full" "0,1" bitfld.long 0x0 23. "TXFE,TXFIFO Empty" "0,1" bitfld.long 0x0 22. "REACK,REACK" "0,1" bitfld.long 0x0 21. "TEACK,TEACK" "0,1" bitfld.long 0x0 20. "WUF,WUF" "0,1" newline bitfld.long 0x0 19. "RWU,RWU" "0,1" bitfld.long 0x0 18. "SBKF,SBKF" "0,1" bitfld.long 0x0 17. "CMF,CMF" "0,1" bitfld.long 0x0 16. "BUSY,BUSY" "0,1" bitfld.long 0x0 15. "ABRF,ABRF" "0,1" bitfld.long 0x0 14. "ABRE,ABRE" "0,1" bitfld.long 0x0 13. "UDR,SPI slave underrun error flag" "0,1" bitfld.long 0x0 12. "EOBF,EOBF" "0,1" newline bitfld.long 0x0 11. "RTOF,RTOF" "0,1" bitfld.long 0x0 10. "CTS,CTS" "0,1" bitfld.long 0x0 9. "CTSIF,CTSIF" "0,1" bitfld.long 0x0 8. "LBDF,LBDF" "0,1" bitfld.long 0x0 7. "TXE,TXE" "0,1" bitfld.long 0x0 6. "TC,TC" "0,1" bitfld.long 0x0 5. "RXNE,RXNE" "0,1" bitfld.long 0x0 4. "IDLE,IDLE" "0,1" newline bitfld.long 0x0 3. "ORE,ORE" "0,1" bitfld.long 0x0 2. "NF,NF" "0,1" bitfld.long 0x0 1. "FE,FE" "0,1" bitfld.long 0x0 0. "PE,PE" "0,1" wgroup.long 0x20++0x3 line.long 0x0 "ICR,Interrupt flag clear register" bitfld.long 0x0 20. "WUCF,Wakeup from Stop mode clear flag" "0,1" bitfld.long 0x0 17. "CMCF,Character match clear flag" "0,1" bitfld.long 0x0 13. "UDRCF,SPI slave underrun clear flag" "0,1" bitfld.long 0x0 12. "EOBCF,End of block clear flag" "0,1" bitfld.long 0x0 11. "RTOCF,Receiver timeout clear flag" "0,1" bitfld.long 0x0 9. "CTSCF,CTS clear flag" "0,1" bitfld.long 0x0 8. "LBDCF,LIN break detection clear flag" "0,1" bitfld.long 0x0 7. "TCBGTCF,Transmission complete before Guard time clear flag" "0,1" newline bitfld.long 0x0 6. "TCCF,Transmission complete clear flag" "0,1" bitfld.long 0x0 5. "TXFECF,TXFIFO empty clear flag" "0,1" bitfld.long 0x0 4. "IDLECF,Idle line detected clear flag" "0,1" bitfld.long 0x0 3. "ORECF,Overrun error clear flag" "0,1" bitfld.long 0x0 2. "NCF,Noise detected clear flag" "0,1" bitfld.long 0x0 1. "FECF,Framing error clear flag" "0,1" bitfld.long 0x0 0. "PECF,Parity error clear flag" "0,1" rgroup.long 0x24++0x3 line.long 0x0 "RDR,Receive data register" hexmask.long.word 0x0 0.--8. 1. "RDR,Receive data value" group.long 0x28++0x7 line.long 0x0 "TDR,Transmit data register" hexmask.long.word 0x0 0.--8. 1. "TDR,Transmit data value" line.long 0x4 "PRESC,Prescaler register" hexmask.long.byte 0x4 0.--3. 1. "PRESCALER,Clock prescaler" rgroup.long 0x3EC++0x13 line.long 0x0 "HWCFGR2,USART Hardware Configuration register 2" hexmask.long.byte 0x0 4.--7. 1. "CFG2,CFG2" hexmask.long.byte 0x0 0.--3. 1. "CFG1,CFG1" line.long 0x4 "HWCFGR1,USART Hardware Configuration register 1" hexmask.long.byte 0x4 28.--31. 1. "CFG8,CFG8" hexmask.long.byte 0x4 24.--27. 1. "CFG7,CFG7" hexmask.long.byte 0x4 20.--23. 1. "CFG6,CFG6" hexmask.long.byte 0x4 16.--19. 1. "CFG5,CFG5" hexmask.long.byte 0x4 12.--15. 1. "CFG4,CFG4" hexmask.long.byte 0x4 8.--11. 1. "CFG3,CFG3" hexmask.long.byte 0x4 4.--7. 1. "CFG2,CFG2" hexmask.long.byte 0x4 0.--3. 1. "CFG1,CFG1" line.long 0x8 "VERR,EXTI IP Version register" hexmask.long.byte 0x8 4.--7. 1. "MAJREV,Major Revision number" hexmask.long.byte 0x8 0.--3. 1. "MINREV,Minor Revision number" line.long 0xC "IPIDR,EXTI Identification register" hexmask.long 0xC 0.--31. 1. "IPID,IP Identification" line.long 0x10 "SIDR,EXTI Size ID register" hexmask.long 0x10 0.--31. 1. "SID,Size Identification" tree.end endif sif (cpuis("STM32MP157*")) tree "USART1" base ad:0x5C000000 group.long 0x0++0x17 line.long 0x0 "CR1,Control register 1" bitfld.long 0x0 31. "RXFFIE,RXFIFO Full interrupt enable" "0,1" bitfld.long 0x0 30. "TXFEIE,TXFIFO empty interrupt enable" "0,1" bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0,1" bitfld.long 0x0 28. "M1,Word length" "0,1" bitfld.long 0x0 27. "EOBIE,End of Block interrupt enable" "0,1" bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0,1" hexmask.long.byte 0x0 21.--25. 1. "DEAT,DEAT" hexmask.long.byte 0x0 16.--20. 1. "DEDT,DEDT" newline bitfld.long 0x0 15. "OVER8,Oversampling mode" "0,1" bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0,1" bitfld.long 0x0 13. "MME,Mute mode enable" "0,1" bitfld.long 0x0 12. "M0,Word length" "0,1" bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0,1" bitfld.long 0x0 10. "PCE,Parity control enable" "0,1" bitfld.long 0x0 9. "PS,Parity selection" "0,1" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0,1" newline bitfld.long 0x0 7. "TXEIE,interrupt enable" "0,1" bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0,1" bitfld.long 0x0 5. "RXNEIE,RXNE interrupt enable" "0,1" bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0,1" bitfld.long 0x0 3. "TE,Transmitter enable" "0,1" bitfld.long 0x0 2. "RE,Receiver enable" "0,1" bitfld.long 0x0 1. "UESM,USART enable in Stop mode" "0,1" bitfld.long 0x0 0. "UE,USART enable" "0,1" line.long 0x4 "CR2,Control register 2" hexmask.long.byte 0x4 28.--31. 1. "ADD4_7,Address of the USART node" hexmask.long.byte 0x4 24.--27. 1. "ADD0_3,Address of the USART node" bitfld.long 0x4 23. "RTOEN,Receiver timeout enable" "0,1" bitfld.long 0x4 21.--22. "ABRMOD,Auto baud rate mode" "0,1,2,3" bitfld.long 0x4 20. "ABREN,Auto baud rate enable" "0,1" bitfld.long 0x4 19. "MSBFIRST,Most significant bit first" "0,1" bitfld.long 0x4 18. "TAINV,Binary data inversion" "0,1" bitfld.long 0x4 17. "TXINV,TX pin active level inversion" "0,1" newline bitfld.long 0x4 16. "RXINV,RX pin active level inversion" "0,1" bitfld.long 0x4 15. "SWAP,Swap TX/RX pins" "0,1" bitfld.long 0x4 14. "LINEN,LIN mode enable" "0,1" bitfld.long 0x4 12.--13. "STOP,STOP bits" "0,1,2,3" bitfld.long 0x4 11. "CLKEN,Clock enable" "0,1" bitfld.long 0x4 10. "CPOL,Clock polarity" "0,1" bitfld.long 0x4 9. "CPHA,Clock phase" "0,1" bitfld.long 0x4 8. "LBCL,Last bit clock pulse" "0,1" newline bitfld.long 0x4 6. "LBDIE,LIN break detection interrupt enable" "0,1" bitfld.long 0x4 5. "LBDL,LIN break detection length" "0,1" bitfld.long 0x4 4. "ADDM7,7-bit Address Detection/4-bit Address Detection" "0,1" bitfld.long 0x4 3. "DIS_NSS,When the DSI_NSS bit is set the NSS pin input will be ignored" "0,1" bitfld.long 0x4 0. "SLVEN,Synchronous Slave mode enable" "0,1" line.long 0x8 "CR3,Control register 3" bitfld.long 0x8 29.--31. "TXFTCFG,TXFIFO threshold configuration" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "RXFTIE,RXFIFO threshold interrupt enable" "0,1" bitfld.long 0x8 25.--27. "RXFTCFG,Receive FIFO threshold configuration" "0,1,2,3,4,5,6,7" bitfld.long 0x8 24. "TCBGTIE,Tr Complete before guard time interrupt enable" "0,1" bitfld.long 0x8 23. "TXFTIE,threshold interrupt enable" "0,1" bitfld.long 0x8 22. "WUFIE,Wakeup from Stop mode interrupt enable" "0,1" bitfld.long 0x8 20.--21. "WUS,Wakeup from Stop mode interrupt flag selection" "0,1,2,3" bitfld.long 0x8 17.--19. "SCARCNT,Smartcard auto-retry count" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 15. "DEP,Driver enable polarity selection" "0,1" bitfld.long 0x8 14. "DEM,Driver enable mode" "0,1" bitfld.long 0x8 13. "DDRE,DMA Disable on Reception Error" "0,1" bitfld.long 0x8 12. "OVRDIS,Overrun Disable" "0,1" bitfld.long 0x8 11. "ONEBIT,One sample bit method enable" "0,1" bitfld.long 0x8 10. "CTSIE,CTS interrupt enable" "0,1" bitfld.long 0x8 9. "CTSE,CTS enable" "0,1" bitfld.long 0x8 8. "RTSE,RTS enable" "0,1" newline bitfld.long 0x8 7. "DMAT,DMA enable transmitter" "0,1" bitfld.long 0x8 6. "DMAR,DMA enable receiver" "0,1" bitfld.long 0x8 5. "SCEN,Smartcard mode enable" "0,1" bitfld.long 0x8 4. "NACK,Smartcard NACK enable" "0,1" bitfld.long 0x8 3. "HDSEL,Half-duplex selection" "0,1" bitfld.long 0x8 2. "IRLP,Ir low-power" "0,1" bitfld.long 0x8 1. "IREN,Ir mode enable" "0,1" bitfld.long 0x8 0. "EIE,Error interrupt enable" "0,1" line.long 0xC "BRR,Baud rate register" hexmask.long.word 0xC 4.--15. 1. "BRR_4_15,BRR_4_15" hexmask.long.byte 0xC 0.--3. 1. "BRR_0_3,BRR_0_3" line.long 0x10 "GTPR,Guard time and prescaler register" hexmask.long.byte 0x10 8.--15. 1. "GT,Guard time value" hexmask.long.byte 0x10 0.--7. 1. "PSC,Prescaler value" line.long 0x14 "RTOR,Receiver timeout register" hexmask.long.byte 0x14 24.--31. 1. "BLEN,Block Length" hexmask.long.tbyte 0x14 0.--23. 1. "RTO,Receiver timeout value" wgroup.long 0x18++0x3 line.long 0x0 "RQR,Request register" bitfld.long 0x0 4. "TXFRQ,Transmit data flush request" "0,1" bitfld.long 0x0 3. "RXFRQ,Receive data flush request" "0,1" bitfld.long 0x0 2. "MMRQ,Mute mode request" "0,1" bitfld.long 0x0 1. "SBKRQ,Send break request" "0,1" bitfld.long 0x0 0. "ABRRQ,Auto baud rate request" "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "ISR,Interrupt & status register" bitfld.long 0x0 27. "TXFT,TXFIFO threshold flag" "0,1" bitfld.long 0x0 26. "RXFT,RXFIFO threshold flag" "0,1" bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time flag" "0,1" bitfld.long 0x0 24. "RXFF,RXFIFO Full" "0,1" bitfld.long 0x0 23. "TXFE,TXFIFO Empty" "0,1" bitfld.long 0x0 22. "REACK,REACK" "0,1" bitfld.long 0x0 21. "TEACK,TEACK" "0,1" bitfld.long 0x0 20. "WUF,WUF" "0,1" newline bitfld.long 0x0 19. "RWU,RWU" "0,1" bitfld.long 0x0 18. "SBKF,SBKF" "0,1" bitfld.long 0x0 17. "CMF,CMF" "0,1" bitfld.long 0x0 16. "BUSY,BUSY" "0,1" bitfld.long 0x0 15. "ABRF,ABRF" "0,1" bitfld.long 0x0 14. "ABRE,ABRE" "0,1" bitfld.long 0x0 13. "UDR,SPI slave underrun error flag" "0,1" bitfld.long 0x0 12. "EOBF,EOBF" "0,1" newline bitfld.long 0x0 11. "RTOF,RTOF" "0,1" bitfld.long 0x0 10. "CTS,CTS" "0,1" bitfld.long 0x0 9. "CTSIF,CTSIF" "0,1" bitfld.long 0x0 8. "LBDF,LBDF" "0,1" bitfld.long 0x0 7. "TXE,TXE" "0,1" bitfld.long 0x0 6. "TC,TC" "0,1" bitfld.long 0x0 5. "RXNE,RXNE" "0,1" bitfld.long 0x0 4. "IDLE,IDLE" "0,1" newline bitfld.long 0x0 3. "ORE,ORE" "0,1" bitfld.long 0x0 2. "NF,NF" "0,1" bitfld.long 0x0 1. "FE,FE" "0,1" bitfld.long 0x0 0. "PE,PE" "0,1" wgroup.long 0x20++0x3 line.long 0x0 "ICR,Interrupt flag clear register" bitfld.long 0x0 20. "WUCF,Wakeup from Stop mode clear flag" "0,1" bitfld.long 0x0 17. "CMCF,Character match clear flag" "0,1" bitfld.long 0x0 13. "UDRCF,SPI slave underrun clear flag" "0,1" bitfld.long 0x0 12. "EOBCF,End of block clear flag" "0,1" bitfld.long 0x0 11. "RTOCF,Receiver timeout clear flag" "0,1" bitfld.long 0x0 9. "CTSCF,CTS clear flag" "0,1" bitfld.long 0x0 8. "LBDCF,LIN break detection clear flag" "0,1" bitfld.long 0x0 7. "TCBGTCF,Transmission complete before Guard time clear flag" "0,1" newline bitfld.long 0x0 6. "TCCF,Transmission complete clear flag" "0,1" bitfld.long 0x0 5. "TXFECF,TXFIFO empty clear flag" "0,1" bitfld.long 0x0 4. "IDLECF,Idle line detected clear flag" "0,1" bitfld.long 0x0 3. "ORECF,Overrun error clear flag" "0,1" bitfld.long 0x0 2. "NCF,Noise detected clear flag" "0,1" bitfld.long 0x0 1. "FECF,Framing error clear flag" "0,1" bitfld.long 0x0 0. "PECF,Parity error clear flag" "0,1" rgroup.long 0x24++0x3 line.long 0x0 "RDR,Receive data register" hexmask.long.word 0x0 0.--8. 1. "RDR,Receive data value" group.long 0x28++0x7 line.long 0x0 "TDR,Transmit data register" hexmask.long.word 0x0 0.--8. 1. "TDR,Transmit data value" line.long 0x4 "PRESC,Prescaler register" hexmask.long.byte 0x4 0.--3. 1. "PRESCALER,Clock prescaler" rgroup.long 0x3EC++0x13 line.long 0x0 "HWCFGR2,USART Hardware Configuration register 2" hexmask.long.byte 0x0 4.--7. 1. "CFG2,CFG2" hexmask.long.byte 0x0 0.--3. 1. "CFG1,CFG1" line.long 0x4 "HWCFGR1,USART Hardware Configuration register 1" hexmask.long.byte 0x4 28.--31. 1. "CFG8,CFG8" hexmask.long.byte 0x4 24.--27. 1. "CFG7,CFG7" hexmask.long.byte 0x4 20.--23. 1. "CFG6,CFG6" hexmask.long.byte 0x4 16.--19. 1. "CFG5,CFG5" hexmask.long.byte 0x4 12.--15. 1. "CFG4,CFG4" hexmask.long.byte 0x4 8.--11. 1. "CFG3,CFG3" hexmask.long.byte 0x4 4.--7. 1. "CFG2,CFG2" hexmask.long.byte 0x4 0.--3. 1. "CFG1,CFG1" line.long 0x8 "VERR,EXTI IP Version register" hexmask.long.byte 0x8 4.--7. 1. "MAJREV,Major Revision number" hexmask.long.byte 0x8 0.--3. 1. "MINREV,Minor Revision number" line.long 0xC "IPIDR,EXTI Identification register" hexmask.long 0xC 0.--31. 1. "IPID,IP Identification" line.long 0x10 "SIDR,EXTI Size ID register" hexmask.long 0x10 0.--31. 1. "SID,Size Identification" tree.end endif sif (cpuis("STM32MP157*")) tree "USART2" base ad:0x4000E000 group.long 0x0++0x17 line.long 0x0 "CR1,Control register 1" bitfld.long 0x0 31. "RXFFIE,RXFIFO Full interrupt enable" "0,1" bitfld.long 0x0 30. "TXFEIE,TXFIFO empty interrupt enable" "0,1" bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0,1" bitfld.long 0x0 28. "M1,Word length" "0,1" bitfld.long 0x0 27. "EOBIE,End of Block interrupt enable" "0,1" bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0,1" hexmask.long.byte 0x0 21.--25. 1. "DEAT,DEAT" hexmask.long.byte 0x0 16.--20. 1. "DEDT,DEDT" newline bitfld.long 0x0 15. "OVER8,Oversampling mode" "0,1" bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0,1" bitfld.long 0x0 13. "MME,Mute mode enable" "0,1" bitfld.long 0x0 12. "M0,Word length" "0,1" bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0,1" bitfld.long 0x0 10. "PCE,Parity control enable" "0,1" bitfld.long 0x0 9. "PS,Parity selection" "0,1" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0,1" newline bitfld.long 0x0 7. "TXEIE,interrupt enable" "0,1" bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0,1" bitfld.long 0x0 5. "RXNEIE,RXNE interrupt enable" "0,1" bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0,1" bitfld.long 0x0 3. "TE,Transmitter enable" "0,1" bitfld.long 0x0 2. "RE,Receiver enable" "0,1" bitfld.long 0x0 1. "UESM,USART enable in Stop mode" "0,1" bitfld.long 0x0 0. "UE,USART enable" "0,1" line.long 0x4 "CR2,Control register 2" hexmask.long.byte 0x4 28.--31. 1. "ADD4_7,Address of the USART node" hexmask.long.byte 0x4 24.--27. 1. "ADD0_3,Address of the USART node" bitfld.long 0x4 23. "RTOEN,Receiver timeout enable" "0,1" bitfld.long 0x4 21.--22. "ABRMOD,Auto baud rate mode" "0,1,2,3" bitfld.long 0x4 20. "ABREN,Auto baud rate enable" "0,1" bitfld.long 0x4 19. "MSBFIRST,Most significant bit first" "0,1" bitfld.long 0x4 18. "TAINV,Binary data inversion" "0,1" bitfld.long 0x4 17. "TXINV,TX pin active level inversion" "0,1" newline bitfld.long 0x4 16. "RXINV,RX pin active level inversion" "0,1" bitfld.long 0x4 15. "SWAP,Swap TX/RX pins" "0,1" bitfld.long 0x4 14. "LINEN,LIN mode enable" "0,1" bitfld.long 0x4 12.--13. "STOP,STOP bits" "0,1,2,3" bitfld.long 0x4 11. "CLKEN,Clock enable" "0,1" bitfld.long 0x4 10. "CPOL,Clock polarity" "0,1" bitfld.long 0x4 9. "CPHA,Clock phase" "0,1" bitfld.long 0x4 8. "LBCL,Last bit clock pulse" "0,1" newline bitfld.long 0x4 6. "LBDIE,LIN break detection interrupt enable" "0,1" bitfld.long 0x4 5. "LBDL,LIN break detection length" "0,1" bitfld.long 0x4 4. "ADDM7,7-bit Address Detection/4-bit Address Detection" "0,1" bitfld.long 0x4 3. "DIS_NSS,When the DSI_NSS bit is set the NSS pin input will be ignored" "0,1" bitfld.long 0x4 0. "SLVEN,Synchronous Slave mode enable" "0,1" line.long 0x8 "CR3,Control register 3" bitfld.long 0x8 29.--31. "TXFTCFG,TXFIFO threshold configuration" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "RXFTIE,RXFIFO threshold interrupt enable" "0,1" bitfld.long 0x8 25.--27. "RXFTCFG,Receive FIFO threshold configuration" "0,1,2,3,4,5,6,7" bitfld.long 0x8 24. "TCBGTIE,Tr Complete before guard time interrupt enable" "0,1" bitfld.long 0x8 23. "TXFTIE,threshold interrupt enable" "0,1" bitfld.long 0x8 22. "WUFIE,Wakeup from Stop mode interrupt enable" "0,1" bitfld.long 0x8 20.--21. "WUS,Wakeup from Stop mode interrupt flag selection" "0,1,2,3" bitfld.long 0x8 17.--19. "SCARCNT,Smartcard auto-retry count" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 15. "DEP,Driver enable polarity selection" "0,1" bitfld.long 0x8 14. "DEM,Driver enable mode" "0,1" bitfld.long 0x8 13. "DDRE,DMA Disable on Reception Error" "0,1" bitfld.long 0x8 12. "OVRDIS,Overrun Disable" "0,1" bitfld.long 0x8 11. "ONEBIT,One sample bit method enable" "0,1" bitfld.long 0x8 10. "CTSIE,CTS interrupt enable" "0,1" bitfld.long 0x8 9. "CTSE,CTS enable" "0,1" bitfld.long 0x8 8. "RTSE,RTS enable" "0,1" newline bitfld.long 0x8 7. "DMAT,DMA enable transmitter" "0,1" bitfld.long 0x8 6. "DMAR,DMA enable receiver" "0,1" bitfld.long 0x8 5. "SCEN,Smartcard mode enable" "0,1" bitfld.long 0x8 4. "NACK,Smartcard NACK enable" "0,1" bitfld.long 0x8 3. "HDSEL,Half-duplex selection" "0,1" bitfld.long 0x8 2. "IRLP,Ir low-power" "0,1" bitfld.long 0x8 1. "IREN,Ir mode enable" "0,1" bitfld.long 0x8 0. "EIE,Error interrupt enable" "0,1" line.long 0xC "BRR,Baud rate register" hexmask.long.word 0xC 4.--15. 1. "BRR_4_15,BRR_4_15" hexmask.long.byte 0xC 0.--3. 1. "BRR_0_3,BRR_0_3" line.long 0x10 "GTPR,Guard time and prescaler register" hexmask.long.byte 0x10 8.--15. 1. "GT,Guard time value" hexmask.long.byte 0x10 0.--7. 1. "PSC,Prescaler value" line.long 0x14 "RTOR,Receiver timeout register" hexmask.long.byte 0x14 24.--31. 1. "BLEN,Block Length" hexmask.long.tbyte 0x14 0.--23. 1. "RTO,Receiver timeout value" wgroup.long 0x18++0x3 line.long 0x0 "RQR,Request register" bitfld.long 0x0 4. "TXFRQ,Transmit data flush request" "0,1" bitfld.long 0x0 3. "RXFRQ,Receive data flush request" "0,1" bitfld.long 0x0 2. "MMRQ,Mute mode request" "0,1" bitfld.long 0x0 1. "SBKRQ,Send break request" "0,1" bitfld.long 0x0 0. "ABRRQ,Auto baud rate request" "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "ISR,Interrupt & status register" bitfld.long 0x0 27. "TXFT,TXFIFO threshold flag" "0,1" bitfld.long 0x0 26. "RXFT,RXFIFO threshold flag" "0,1" bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time flag" "0,1" bitfld.long 0x0 24. "RXFF,RXFIFO Full" "0,1" bitfld.long 0x0 23. "TXFE,TXFIFO Empty" "0,1" bitfld.long 0x0 22. "REACK,REACK" "0,1" bitfld.long 0x0 21. "TEACK,TEACK" "0,1" bitfld.long 0x0 20. "WUF,WUF" "0,1" newline bitfld.long 0x0 19. "RWU,RWU" "0,1" bitfld.long 0x0 18. "SBKF,SBKF" "0,1" bitfld.long 0x0 17. "CMF,CMF" "0,1" bitfld.long 0x0 16. "BUSY,BUSY" "0,1" bitfld.long 0x0 15. "ABRF,ABRF" "0,1" bitfld.long 0x0 14. "ABRE,ABRE" "0,1" bitfld.long 0x0 13. "UDR,SPI slave underrun error flag" "0,1" bitfld.long 0x0 12. "EOBF,EOBF" "0,1" newline bitfld.long 0x0 11. "RTOF,RTOF" "0,1" bitfld.long 0x0 10. "CTS,CTS" "0,1" bitfld.long 0x0 9. "CTSIF,CTSIF" "0,1" bitfld.long 0x0 8. "LBDF,LBDF" "0,1" bitfld.long 0x0 7. "TXE,TXE" "0,1" bitfld.long 0x0 6. "TC,TC" "0,1" bitfld.long 0x0 5. "RXNE,RXNE" "0,1" bitfld.long 0x0 4. "IDLE,IDLE" "0,1" newline bitfld.long 0x0 3. "ORE,ORE" "0,1" bitfld.long 0x0 2. "NF,NF" "0,1" bitfld.long 0x0 1. "FE,FE" "0,1" bitfld.long 0x0 0. "PE,PE" "0,1" wgroup.long 0x20++0x3 line.long 0x0 "ICR,Interrupt flag clear register" bitfld.long 0x0 20. "WUCF,Wakeup from Stop mode clear flag" "0,1" bitfld.long 0x0 17. "CMCF,Character match clear flag" "0,1" bitfld.long 0x0 13. "UDRCF,SPI slave underrun clear flag" "0,1" bitfld.long 0x0 12. "EOBCF,End of block clear flag" "0,1" bitfld.long 0x0 11. "RTOCF,Receiver timeout clear flag" "0,1" bitfld.long 0x0 9. "CTSCF,CTS clear flag" "0,1" bitfld.long 0x0 8. "LBDCF,LIN break detection clear flag" "0,1" bitfld.long 0x0 7. "TCBGTCF,Transmission complete before Guard time clear flag" "0,1" newline bitfld.long 0x0 6. "TCCF,Transmission complete clear flag" "0,1" bitfld.long 0x0 5. "TXFECF,TXFIFO empty clear flag" "0,1" bitfld.long 0x0 4. "IDLECF,Idle line detected clear flag" "0,1" bitfld.long 0x0 3. "ORECF,Overrun error clear flag" "0,1" bitfld.long 0x0 2. "NCF,Noise detected clear flag" "0,1" bitfld.long 0x0 1. "FECF,Framing error clear flag" "0,1" bitfld.long 0x0 0. "PECF,Parity error clear flag" "0,1" rgroup.long 0x24++0x3 line.long 0x0 "RDR,Receive data register" hexmask.long.word 0x0 0.--8. 1. "RDR,Receive data value" group.long 0x28++0x7 line.long 0x0 "TDR,Transmit data register" hexmask.long.word 0x0 0.--8. 1. "TDR,Transmit data value" line.long 0x4 "PRESC,Prescaler register" hexmask.long.byte 0x4 0.--3. 1. "PRESCALER,Clock prescaler" rgroup.long 0x3EC++0x13 line.long 0x0 "HWCFGR2,USART Hardware Configuration register 2" hexmask.long.byte 0x0 4.--7. 1. "CFG2,CFG2" hexmask.long.byte 0x0 0.--3. 1. "CFG1,CFG1" line.long 0x4 "HWCFGR1,USART Hardware Configuration register 1" hexmask.long.byte 0x4 28.--31. 1. "CFG8,CFG8" hexmask.long.byte 0x4 24.--27. 1. "CFG7,CFG7" hexmask.long.byte 0x4 20.--23. 1. "CFG6,CFG6" hexmask.long.byte 0x4 16.--19. 1. "CFG5,CFG5" hexmask.long.byte 0x4 12.--15. 1. "CFG4,CFG4" hexmask.long.byte 0x4 8.--11. 1. "CFG3,CFG3" hexmask.long.byte 0x4 4.--7. 1. "CFG2,CFG2" hexmask.long.byte 0x4 0.--3. 1. "CFG1,CFG1" line.long 0x8 "VERR,EXTI IP Version register" hexmask.long.byte 0x8 4.--7. 1. "MAJREV,Major Revision number" hexmask.long.byte 0x8 0.--3. 1. "MINREV,Minor Revision number" line.long 0xC "IPIDR,EXTI Identification register" hexmask.long 0xC 0.--31. 1. "IPID,IP Identification" line.long 0x10 "SIDR,EXTI Size ID register" hexmask.long 0x10 0.--31. 1. "SID,Size Identification" tree.end tree "USART3" base ad:0x4000F000 group.long 0x0++0x17 line.long 0x0 "CR1,Control register 1" bitfld.long 0x0 31. "RXFFIE,RXFIFO Full interrupt enable" "0,1" bitfld.long 0x0 30. "TXFEIE,TXFIFO empty interrupt enable" "0,1" bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0,1" bitfld.long 0x0 28. "M1,Word length" "0,1" bitfld.long 0x0 27. "EOBIE,End of Block interrupt enable" "0,1" bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0,1" hexmask.long.byte 0x0 21.--25. 1. "DEAT,DEAT" hexmask.long.byte 0x0 16.--20. 1. "DEDT,DEDT" newline bitfld.long 0x0 15. "OVER8,Oversampling mode" "0,1" bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0,1" bitfld.long 0x0 13. "MME,Mute mode enable" "0,1" bitfld.long 0x0 12. "M0,Word length" "0,1" bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0,1" bitfld.long 0x0 10. "PCE,Parity control enable" "0,1" bitfld.long 0x0 9. "PS,Parity selection" "0,1" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0,1" newline bitfld.long 0x0 7. "TXEIE,interrupt enable" "0,1" bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0,1" bitfld.long 0x0 5. "RXNEIE,RXNE interrupt enable" "0,1" bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0,1" bitfld.long 0x0 3. "TE,Transmitter enable" "0,1" bitfld.long 0x0 2. "RE,Receiver enable" "0,1" bitfld.long 0x0 1. "UESM,USART enable in Stop mode" "0,1" bitfld.long 0x0 0. "UE,USART enable" "0,1" line.long 0x4 "CR2,Control register 2" hexmask.long.byte 0x4 28.--31. 1. "ADD4_7,Address of the USART node" hexmask.long.byte 0x4 24.--27. 1. "ADD0_3,Address of the USART node" bitfld.long 0x4 23. "RTOEN,Receiver timeout enable" "0,1" bitfld.long 0x4 21.--22. "ABRMOD,Auto baud rate mode" "0,1,2,3" bitfld.long 0x4 20. "ABREN,Auto baud rate enable" "0,1" bitfld.long 0x4 19. "MSBFIRST,Most significant bit first" "0,1" bitfld.long 0x4 18. "TAINV,Binary data inversion" "0,1" bitfld.long 0x4 17. "TXINV,TX pin active level inversion" "0,1" newline bitfld.long 0x4 16. "RXINV,RX pin active level inversion" "0,1" bitfld.long 0x4 15. "SWAP,Swap TX/RX pins" "0,1" bitfld.long 0x4 14. "LINEN,LIN mode enable" "0,1" bitfld.long 0x4 12.--13. "STOP,STOP bits" "0,1,2,3" bitfld.long 0x4 11. "CLKEN,Clock enable" "0,1" bitfld.long 0x4 10. "CPOL,Clock polarity" "0,1" bitfld.long 0x4 9. "CPHA,Clock phase" "0,1" bitfld.long 0x4 8. "LBCL,Last bit clock pulse" "0,1" newline bitfld.long 0x4 6. "LBDIE,LIN break detection interrupt enable" "0,1" bitfld.long 0x4 5. "LBDL,LIN break detection length" "0,1" bitfld.long 0x4 4. "ADDM7,7-bit Address Detection/4-bit Address Detection" "0,1" bitfld.long 0x4 3. "DIS_NSS,When the DSI_NSS bit is set the NSS pin input will be ignored" "0,1" bitfld.long 0x4 0. "SLVEN,Synchronous Slave mode enable" "0,1" line.long 0x8 "CR3,Control register 3" bitfld.long 0x8 29.--31. "TXFTCFG,TXFIFO threshold configuration" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "RXFTIE,RXFIFO threshold interrupt enable" "0,1" bitfld.long 0x8 25.--27. "RXFTCFG,Receive FIFO threshold configuration" "0,1,2,3,4,5,6,7" bitfld.long 0x8 24. "TCBGTIE,Tr Complete before guard time interrupt enable" "0,1" bitfld.long 0x8 23. "TXFTIE,threshold interrupt enable" "0,1" bitfld.long 0x8 22. "WUFIE,Wakeup from Stop mode interrupt enable" "0,1" bitfld.long 0x8 20.--21. "WUS,Wakeup from Stop mode interrupt flag selection" "0,1,2,3" bitfld.long 0x8 17.--19. "SCARCNT,Smartcard auto-retry count" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 15. "DEP,Driver enable polarity selection" "0,1" bitfld.long 0x8 14. "DEM,Driver enable mode" "0,1" bitfld.long 0x8 13. "DDRE,DMA Disable on Reception Error" "0,1" bitfld.long 0x8 12. "OVRDIS,Overrun Disable" "0,1" bitfld.long 0x8 11. "ONEBIT,One sample bit method enable" "0,1" bitfld.long 0x8 10. "CTSIE,CTS interrupt enable" "0,1" bitfld.long 0x8 9. "CTSE,CTS enable" "0,1" bitfld.long 0x8 8. "RTSE,RTS enable" "0,1" newline bitfld.long 0x8 7. "DMAT,DMA enable transmitter" "0,1" bitfld.long 0x8 6. "DMAR,DMA enable receiver" "0,1" bitfld.long 0x8 5. "SCEN,Smartcard mode enable" "0,1" bitfld.long 0x8 4. "NACK,Smartcard NACK enable" "0,1" bitfld.long 0x8 3. "HDSEL,Half-duplex selection" "0,1" bitfld.long 0x8 2. "IRLP,Ir low-power" "0,1" bitfld.long 0x8 1. "IREN,Ir mode enable" "0,1" bitfld.long 0x8 0. "EIE,Error interrupt enable" "0,1" line.long 0xC "BRR,Baud rate register" hexmask.long.word 0xC 4.--15. 1. "BRR_4_15,BRR_4_15" hexmask.long.byte 0xC 0.--3. 1. "BRR_0_3,BRR_0_3" line.long 0x10 "GTPR,Guard time and prescaler register" hexmask.long.byte 0x10 8.--15. 1. "GT,Guard time value" hexmask.long.byte 0x10 0.--7. 1. "PSC,Prescaler value" line.long 0x14 "RTOR,Receiver timeout register" hexmask.long.byte 0x14 24.--31. 1. "BLEN,Block Length" hexmask.long.tbyte 0x14 0.--23. 1. "RTO,Receiver timeout value" wgroup.long 0x18++0x3 line.long 0x0 "RQR,Request register" bitfld.long 0x0 4. "TXFRQ,Transmit data flush request" "0,1" bitfld.long 0x0 3. "RXFRQ,Receive data flush request" "0,1" bitfld.long 0x0 2. "MMRQ,Mute mode request" "0,1" bitfld.long 0x0 1. "SBKRQ,Send break request" "0,1" bitfld.long 0x0 0. "ABRRQ,Auto baud rate request" "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "ISR,Interrupt & status register" bitfld.long 0x0 27. "TXFT,TXFIFO threshold flag" "0,1" bitfld.long 0x0 26. "RXFT,RXFIFO threshold flag" "0,1" bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time flag" "0,1" bitfld.long 0x0 24. "RXFF,RXFIFO Full" "0,1" bitfld.long 0x0 23. "TXFE,TXFIFO Empty" "0,1" bitfld.long 0x0 22. "REACK,REACK" "0,1" bitfld.long 0x0 21. "TEACK,TEACK" "0,1" bitfld.long 0x0 20. "WUF,WUF" "0,1" newline bitfld.long 0x0 19. "RWU,RWU" "0,1" bitfld.long 0x0 18. "SBKF,SBKF" "0,1" bitfld.long 0x0 17. "CMF,CMF" "0,1" bitfld.long 0x0 16. "BUSY,BUSY" "0,1" bitfld.long 0x0 15. "ABRF,ABRF" "0,1" bitfld.long 0x0 14. "ABRE,ABRE" "0,1" bitfld.long 0x0 13. "UDR,SPI slave underrun error flag" "0,1" bitfld.long 0x0 12. "EOBF,EOBF" "0,1" newline bitfld.long 0x0 11. "RTOF,RTOF" "0,1" bitfld.long 0x0 10. "CTS,CTS" "0,1" bitfld.long 0x0 9. "CTSIF,CTSIF" "0,1" bitfld.long 0x0 8. "LBDF,LBDF" "0,1" bitfld.long 0x0 7. "TXE,TXE" "0,1" bitfld.long 0x0 6. "TC,TC" "0,1" bitfld.long 0x0 5. "RXNE,RXNE" "0,1" bitfld.long 0x0 4. "IDLE,IDLE" "0,1" newline bitfld.long 0x0 3. "ORE,ORE" "0,1" bitfld.long 0x0 2. "NF,NF" "0,1" bitfld.long 0x0 1. "FE,FE" "0,1" bitfld.long 0x0 0. "PE,PE" "0,1" wgroup.long 0x20++0x3 line.long 0x0 "ICR,Interrupt flag clear register" bitfld.long 0x0 20. "WUCF,Wakeup from Stop mode clear flag" "0,1" bitfld.long 0x0 17. "CMCF,Character match clear flag" "0,1" bitfld.long 0x0 13. "UDRCF,SPI slave underrun clear flag" "0,1" bitfld.long 0x0 12. "EOBCF,End of block clear flag" "0,1" bitfld.long 0x0 11. "RTOCF,Receiver timeout clear flag" "0,1" bitfld.long 0x0 9. "CTSCF,CTS clear flag" "0,1" bitfld.long 0x0 8. "LBDCF,LIN break detection clear flag" "0,1" bitfld.long 0x0 7. "TCBGTCF,Transmission complete before Guard time clear flag" "0,1" newline bitfld.long 0x0 6. "TCCF,Transmission complete clear flag" "0,1" bitfld.long 0x0 5. "TXFECF,TXFIFO empty clear flag" "0,1" bitfld.long 0x0 4. "IDLECF,Idle line detected clear flag" "0,1" bitfld.long 0x0 3. "ORECF,Overrun error clear flag" "0,1" bitfld.long 0x0 2. "NCF,Noise detected clear flag" "0,1" bitfld.long 0x0 1. "FECF,Framing error clear flag" "0,1" bitfld.long 0x0 0. "PECF,Parity error clear flag" "0,1" rgroup.long 0x24++0x3 line.long 0x0 "RDR,Receive data register" hexmask.long.word 0x0 0.--8. 1. "RDR,Receive data value" group.long 0x28++0x7 line.long 0x0 "TDR,Transmit data register" hexmask.long.word 0x0 0.--8. 1. "TDR,Transmit data value" line.long 0x4 "PRESC,Prescaler register" hexmask.long.byte 0x4 0.--3. 1. "PRESCALER,Clock prescaler" rgroup.long 0x3EC++0x13 line.long 0x0 "HWCFGR2,USART Hardware Configuration register 2" hexmask.long.byte 0x0 4.--7. 1. "CFG2,CFG2" hexmask.long.byte 0x0 0.--3. 1. "CFG1,CFG1" line.long 0x4 "HWCFGR1,USART Hardware Configuration register 1" hexmask.long.byte 0x4 28.--31. 1. "CFG8,CFG8" hexmask.long.byte 0x4 24.--27. 1. "CFG7,CFG7" hexmask.long.byte 0x4 20.--23. 1. "CFG6,CFG6" hexmask.long.byte 0x4 16.--19. 1. "CFG5,CFG5" hexmask.long.byte 0x4 12.--15. 1. "CFG4,CFG4" hexmask.long.byte 0x4 8.--11. 1. "CFG3,CFG3" hexmask.long.byte 0x4 4.--7. 1. "CFG2,CFG2" hexmask.long.byte 0x4 0.--3. 1. "CFG1,CFG1" line.long 0x8 "VERR,EXTI IP Version register" hexmask.long.byte 0x8 4.--7. 1. "MAJREV,Major Revision number" hexmask.long.byte 0x8 0.--3. 1. "MINREV,Minor Revision number" line.long 0xC "IPIDR,EXTI Identification register" hexmask.long 0xC 0.--31. 1. "IPID,IP Identification" line.long 0x10 "SIDR,EXTI Size ID register" hexmask.long 0x10 0.--31. 1. "SID,Size Identification" tree.end tree "USART4" base ad:0x40010000 group.long 0x0++0x17 line.long 0x0 "CR1,Control register 1" bitfld.long 0x0 31. "RXFFIE,RXFIFO Full interrupt enable" "0,1" bitfld.long 0x0 30. "TXFEIE,TXFIFO empty interrupt enable" "0,1" bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0,1" bitfld.long 0x0 28. "M1,Word length" "0,1" bitfld.long 0x0 27. "EOBIE,End of Block interrupt enable" "0,1" bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0,1" hexmask.long.byte 0x0 21.--25. 1. "DEAT,DEAT" hexmask.long.byte 0x0 16.--20. 1. "DEDT,DEDT" newline bitfld.long 0x0 15. "OVER8,Oversampling mode" "0,1" bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0,1" bitfld.long 0x0 13. "MME,Mute mode enable" "0,1" bitfld.long 0x0 12. "M0,Word length" "0,1" bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0,1" bitfld.long 0x0 10. "PCE,Parity control enable" "0,1" bitfld.long 0x0 9. "PS,Parity selection" "0,1" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0,1" newline bitfld.long 0x0 7. "TXEIE,interrupt enable" "0,1" bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0,1" bitfld.long 0x0 5. "RXNEIE,RXNE interrupt enable" "0,1" bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0,1" bitfld.long 0x0 3. "TE,Transmitter enable" "0,1" bitfld.long 0x0 2. "RE,Receiver enable" "0,1" bitfld.long 0x0 1. "UESM,USART enable in Stop mode" "0,1" bitfld.long 0x0 0. "UE,USART enable" "0,1" line.long 0x4 "CR2,Control register 2" hexmask.long.byte 0x4 28.--31. 1. "ADD4_7,Address of the USART node" hexmask.long.byte 0x4 24.--27. 1. "ADD0_3,Address of the USART node" bitfld.long 0x4 23. "RTOEN,Receiver timeout enable" "0,1" bitfld.long 0x4 21.--22. "ABRMOD,Auto baud rate mode" "0,1,2,3" bitfld.long 0x4 20. "ABREN,Auto baud rate enable" "0,1" bitfld.long 0x4 19. "MSBFIRST,Most significant bit first" "0,1" bitfld.long 0x4 18. "TAINV,Binary data inversion" "0,1" bitfld.long 0x4 17. "TXINV,TX pin active level inversion" "0,1" newline bitfld.long 0x4 16. "RXINV,RX pin active level inversion" "0,1" bitfld.long 0x4 15. "SWAP,Swap TX/RX pins" "0,1" bitfld.long 0x4 14. "LINEN,LIN mode enable" "0,1" bitfld.long 0x4 12.--13. "STOP,STOP bits" "0,1,2,3" bitfld.long 0x4 11. "CLKEN,Clock enable" "0,1" bitfld.long 0x4 10. "CPOL,Clock polarity" "0,1" bitfld.long 0x4 9. "CPHA,Clock phase" "0,1" bitfld.long 0x4 8. "LBCL,Last bit clock pulse" "0,1" newline bitfld.long 0x4 6. "LBDIE,LIN break detection interrupt enable" "0,1" bitfld.long 0x4 5. "LBDL,LIN break detection length" "0,1" bitfld.long 0x4 4. "ADDM7,7-bit Address Detection/4-bit Address Detection" "0,1" bitfld.long 0x4 3. "DIS_NSS,When the DSI_NSS bit is set the NSS pin input will be ignored" "0,1" bitfld.long 0x4 0. "SLVEN,Synchronous Slave mode enable" "0,1" line.long 0x8 "CR3,Control register 3" bitfld.long 0x8 29.--31. "TXFTCFG,TXFIFO threshold configuration" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "RXFTIE,RXFIFO threshold interrupt enable" "0,1" bitfld.long 0x8 25.--27. "RXFTCFG,Receive FIFO threshold configuration" "0,1,2,3,4,5,6,7" bitfld.long 0x8 24. "TCBGTIE,Tr Complete before guard time interrupt enable" "0,1" bitfld.long 0x8 23. "TXFTIE,threshold interrupt enable" "0,1" bitfld.long 0x8 22. "WUFIE,Wakeup from Stop mode interrupt enable" "0,1" bitfld.long 0x8 20.--21. "WUS,Wakeup from Stop mode interrupt flag selection" "0,1,2,3" bitfld.long 0x8 17.--19. "SCARCNT,Smartcard auto-retry count" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 15. "DEP,Driver enable polarity selection" "0,1" bitfld.long 0x8 14. "DEM,Driver enable mode" "0,1" bitfld.long 0x8 13. "DDRE,DMA Disable on Reception Error" "0,1" bitfld.long 0x8 12. "OVRDIS,Overrun Disable" "0,1" bitfld.long 0x8 11. "ONEBIT,One sample bit method enable" "0,1" bitfld.long 0x8 10. "CTSIE,CTS interrupt enable" "0,1" bitfld.long 0x8 9. "CTSE,CTS enable" "0,1" bitfld.long 0x8 8. "RTSE,RTS enable" "0,1" newline bitfld.long 0x8 7. "DMAT,DMA enable transmitter" "0,1" bitfld.long 0x8 6. "DMAR,DMA enable receiver" "0,1" bitfld.long 0x8 5. "SCEN,Smartcard mode enable" "0,1" bitfld.long 0x8 4. "NACK,Smartcard NACK enable" "0,1" bitfld.long 0x8 3. "HDSEL,Half-duplex selection" "0,1" bitfld.long 0x8 2. "IRLP,Ir low-power" "0,1" bitfld.long 0x8 1. "IREN,Ir mode enable" "0,1" bitfld.long 0x8 0. "EIE,Error interrupt enable" "0,1" line.long 0xC "BRR,Baud rate register" hexmask.long.word 0xC 4.--15. 1. "BRR_4_15,BRR_4_15" hexmask.long.byte 0xC 0.--3. 1. "BRR_0_3,BRR_0_3" line.long 0x10 "GTPR,Guard time and prescaler register" hexmask.long.byte 0x10 8.--15. 1. "GT,Guard time value" hexmask.long.byte 0x10 0.--7. 1. "PSC,Prescaler value" line.long 0x14 "RTOR,Receiver timeout register" hexmask.long.byte 0x14 24.--31. 1. "BLEN,Block Length" hexmask.long.tbyte 0x14 0.--23. 1. "RTO,Receiver timeout value" wgroup.long 0x18++0x3 line.long 0x0 "RQR,Request register" bitfld.long 0x0 4. "TXFRQ,Transmit data flush request" "0,1" bitfld.long 0x0 3. "RXFRQ,Receive data flush request" "0,1" bitfld.long 0x0 2. "MMRQ,Mute mode request" "0,1" bitfld.long 0x0 1. "SBKRQ,Send break request" "0,1" bitfld.long 0x0 0. "ABRRQ,Auto baud rate request" "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "ISR,Interrupt & status register" bitfld.long 0x0 27. "TXFT,TXFIFO threshold flag" "0,1" bitfld.long 0x0 26. "RXFT,RXFIFO threshold flag" "0,1" bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time flag" "0,1" bitfld.long 0x0 24. "RXFF,RXFIFO Full" "0,1" bitfld.long 0x0 23. "TXFE,TXFIFO Empty" "0,1" bitfld.long 0x0 22. "REACK,REACK" "0,1" bitfld.long 0x0 21. "TEACK,TEACK" "0,1" bitfld.long 0x0 20. "WUF,WUF" "0,1" newline bitfld.long 0x0 19. "RWU,RWU" "0,1" bitfld.long 0x0 18. "SBKF,SBKF" "0,1" bitfld.long 0x0 17. "CMF,CMF" "0,1" bitfld.long 0x0 16. "BUSY,BUSY" "0,1" bitfld.long 0x0 15. "ABRF,ABRF" "0,1" bitfld.long 0x0 14. "ABRE,ABRE" "0,1" bitfld.long 0x0 13. "UDR,SPI slave underrun error flag" "0,1" bitfld.long 0x0 12. "EOBF,EOBF" "0,1" newline bitfld.long 0x0 11. "RTOF,RTOF" "0,1" bitfld.long 0x0 10. "CTS,CTS" "0,1" bitfld.long 0x0 9. "CTSIF,CTSIF" "0,1" bitfld.long 0x0 8. "LBDF,LBDF" "0,1" bitfld.long 0x0 7. "TXE,TXE" "0,1" bitfld.long 0x0 6. "TC,TC" "0,1" bitfld.long 0x0 5. "RXNE,RXNE" "0,1" bitfld.long 0x0 4. "IDLE,IDLE" "0,1" newline bitfld.long 0x0 3. "ORE,ORE" "0,1" bitfld.long 0x0 2. "NF,NF" "0,1" bitfld.long 0x0 1. "FE,FE" "0,1" bitfld.long 0x0 0. "PE,PE" "0,1" wgroup.long 0x20++0x3 line.long 0x0 "ICR,Interrupt flag clear register" bitfld.long 0x0 20. "WUCF,Wakeup from Stop mode clear flag" "0,1" bitfld.long 0x0 17. "CMCF,Character match clear flag" "0,1" bitfld.long 0x0 13. "UDRCF,SPI slave underrun clear flag" "0,1" bitfld.long 0x0 12. "EOBCF,End of block clear flag" "0,1" bitfld.long 0x0 11. "RTOCF,Receiver timeout clear flag" "0,1" bitfld.long 0x0 9. "CTSCF,CTS clear flag" "0,1" bitfld.long 0x0 8. "LBDCF,LIN break detection clear flag" "0,1" bitfld.long 0x0 7. "TCBGTCF,Transmission complete before Guard time clear flag" "0,1" newline bitfld.long 0x0 6. "TCCF,Transmission complete clear flag" "0,1" bitfld.long 0x0 5. "TXFECF,TXFIFO empty clear flag" "0,1" bitfld.long 0x0 4. "IDLECF,Idle line detected clear flag" "0,1" bitfld.long 0x0 3. "ORECF,Overrun error clear flag" "0,1" bitfld.long 0x0 2. "NCF,Noise detected clear flag" "0,1" bitfld.long 0x0 1. "FECF,Framing error clear flag" "0,1" bitfld.long 0x0 0. "PECF,Parity error clear flag" "0,1" rgroup.long 0x24++0x3 line.long 0x0 "RDR,Receive data register" hexmask.long.word 0x0 0.--8. 1. "RDR,Receive data value" group.long 0x28++0x7 line.long 0x0 "TDR,Transmit data register" hexmask.long.word 0x0 0.--8. 1. "TDR,Transmit data value" line.long 0x4 "PRESC,Prescaler register" hexmask.long.byte 0x4 0.--3. 1. "PRESCALER,Clock prescaler" rgroup.long 0x3EC++0x13 line.long 0x0 "HWCFGR2,USART Hardware Configuration register 2" hexmask.long.byte 0x0 4.--7. 1. "CFG2,CFG2" hexmask.long.byte 0x0 0.--3. 1. "CFG1,CFG1" line.long 0x4 "HWCFGR1,USART Hardware Configuration register 1" hexmask.long.byte 0x4 28.--31. 1. "CFG8,CFG8" hexmask.long.byte 0x4 24.--27. 1. "CFG7,CFG7" hexmask.long.byte 0x4 20.--23. 1. "CFG6,CFG6" hexmask.long.byte 0x4 16.--19. 1. "CFG5,CFG5" hexmask.long.byte 0x4 12.--15. 1. "CFG4,CFG4" hexmask.long.byte 0x4 8.--11. 1. "CFG3,CFG3" hexmask.long.byte 0x4 4.--7. 1. "CFG2,CFG2" hexmask.long.byte 0x4 0.--3. 1. "CFG1,CFG1" line.long 0x8 "VERR,EXTI IP Version register" hexmask.long.byte 0x8 4.--7. 1. "MAJREV,Major Revision number" hexmask.long.byte 0x8 0.--3. 1. "MINREV,Minor Revision number" line.long 0xC "IPIDR,EXTI Identification register" hexmask.long 0xC 0.--31. 1. "IPID,IP Identification" line.long 0x10 "SIDR,EXTI Size ID register" hexmask.long 0x10 0.--31. 1. "SID,Size Identification" tree.end tree "USART5" base ad:0x40011000 group.long 0x0++0x17 line.long 0x0 "CR1,Control register 1" bitfld.long 0x0 31. "RXFFIE,RXFIFO Full interrupt enable" "0,1" bitfld.long 0x0 30. "TXFEIE,TXFIFO empty interrupt enable" "0,1" bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0,1" bitfld.long 0x0 28. "M1,Word length" "0,1" bitfld.long 0x0 27. "EOBIE,End of Block interrupt enable" "0,1" bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0,1" hexmask.long.byte 0x0 21.--25. 1. "DEAT,DEAT" hexmask.long.byte 0x0 16.--20. 1. "DEDT,DEDT" newline bitfld.long 0x0 15. "OVER8,Oversampling mode" "0,1" bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0,1" bitfld.long 0x0 13. "MME,Mute mode enable" "0,1" bitfld.long 0x0 12. "M0,Word length" "0,1" bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0,1" bitfld.long 0x0 10. "PCE,Parity control enable" "0,1" bitfld.long 0x0 9. "PS,Parity selection" "0,1" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0,1" newline bitfld.long 0x0 7. "TXEIE,interrupt enable" "0,1" bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0,1" bitfld.long 0x0 5. "RXNEIE,RXNE interrupt enable" "0,1" bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0,1" bitfld.long 0x0 3. "TE,Transmitter enable" "0,1" bitfld.long 0x0 2. "RE,Receiver enable" "0,1" bitfld.long 0x0 1. "UESM,USART enable in Stop mode" "0,1" bitfld.long 0x0 0. "UE,USART enable" "0,1" line.long 0x4 "CR2,Control register 2" hexmask.long.byte 0x4 28.--31. 1. "ADD4_7,Address of the USART node" hexmask.long.byte 0x4 24.--27. 1. "ADD0_3,Address of the USART node" bitfld.long 0x4 23. "RTOEN,Receiver timeout enable" "0,1" bitfld.long 0x4 21.--22. "ABRMOD,Auto baud rate mode" "0,1,2,3" bitfld.long 0x4 20. "ABREN,Auto baud rate enable" "0,1" bitfld.long 0x4 19. "MSBFIRST,Most significant bit first" "0,1" bitfld.long 0x4 18. "TAINV,Binary data inversion" "0,1" bitfld.long 0x4 17. "TXINV,TX pin active level inversion" "0,1" newline bitfld.long 0x4 16. "RXINV,RX pin active level inversion" "0,1" bitfld.long 0x4 15. "SWAP,Swap TX/RX pins" "0,1" bitfld.long 0x4 14. "LINEN,LIN mode enable" "0,1" bitfld.long 0x4 12.--13. "STOP,STOP bits" "0,1,2,3" bitfld.long 0x4 11. "CLKEN,Clock enable" "0,1" bitfld.long 0x4 10. "CPOL,Clock polarity" "0,1" bitfld.long 0x4 9. "CPHA,Clock phase" "0,1" bitfld.long 0x4 8. "LBCL,Last bit clock pulse" "0,1" newline bitfld.long 0x4 6. "LBDIE,LIN break detection interrupt enable" "0,1" bitfld.long 0x4 5. "LBDL,LIN break detection length" "0,1" bitfld.long 0x4 4. "ADDM7,7-bit Address Detection/4-bit Address Detection" "0,1" bitfld.long 0x4 3. "DIS_NSS,When the DSI_NSS bit is set the NSS pin input will be ignored" "0,1" bitfld.long 0x4 0. "SLVEN,Synchronous Slave mode enable" "0,1" line.long 0x8 "CR3,Control register 3" bitfld.long 0x8 29.--31. "TXFTCFG,TXFIFO threshold configuration" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "RXFTIE,RXFIFO threshold interrupt enable" "0,1" bitfld.long 0x8 25.--27. "RXFTCFG,Receive FIFO threshold configuration" "0,1,2,3,4,5,6,7" bitfld.long 0x8 24. "TCBGTIE,Tr Complete before guard time interrupt enable" "0,1" bitfld.long 0x8 23. "TXFTIE,threshold interrupt enable" "0,1" bitfld.long 0x8 22. "WUFIE,Wakeup from Stop mode interrupt enable" "0,1" bitfld.long 0x8 20.--21. "WUS,Wakeup from Stop mode interrupt flag selection" "0,1,2,3" bitfld.long 0x8 17.--19. "SCARCNT,Smartcard auto-retry count" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 15. "DEP,Driver enable polarity selection" "0,1" bitfld.long 0x8 14. "DEM,Driver enable mode" "0,1" bitfld.long 0x8 13. "DDRE,DMA Disable on Reception Error" "0,1" bitfld.long 0x8 12. "OVRDIS,Overrun Disable" "0,1" bitfld.long 0x8 11. "ONEBIT,One sample bit method enable" "0,1" bitfld.long 0x8 10. "CTSIE,CTS interrupt enable" "0,1" bitfld.long 0x8 9. "CTSE,CTS enable" "0,1" bitfld.long 0x8 8. "RTSE,RTS enable" "0,1" newline bitfld.long 0x8 7. "DMAT,DMA enable transmitter" "0,1" bitfld.long 0x8 6. "DMAR,DMA enable receiver" "0,1" bitfld.long 0x8 5. "SCEN,Smartcard mode enable" "0,1" bitfld.long 0x8 4. "NACK,Smartcard NACK enable" "0,1" bitfld.long 0x8 3. "HDSEL,Half-duplex selection" "0,1" bitfld.long 0x8 2. "IRLP,Ir low-power" "0,1" bitfld.long 0x8 1. "IREN,Ir mode enable" "0,1" bitfld.long 0x8 0. "EIE,Error interrupt enable" "0,1" line.long 0xC "BRR,Baud rate register" hexmask.long.word 0xC 4.--15. 1. "BRR_4_15,BRR_4_15" hexmask.long.byte 0xC 0.--3. 1. "BRR_0_3,BRR_0_3" line.long 0x10 "GTPR,Guard time and prescaler register" hexmask.long.byte 0x10 8.--15. 1. "GT,Guard time value" hexmask.long.byte 0x10 0.--7. 1. "PSC,Prescaler value" line.long 0x14 "RTOR,Receiver timeout register" hexmask.long.byte 0x14 24.--31. 1. "BLEN,Block Length" hexmask.long.tbyte 0x14 0.--23. 1. "RTO,Receiver timeout value" wgroup.long 0x18++0x3 line.long 0x0 "RQR,Request register" bitfld.long 0x0 4. "TXFRQ,Transmit data flush request" "0,1" bitfld.long 0x0 3. "RXFRQ,Receive data flush request" "0,1" bitfld.long 0x0 2. "MMRQ,Mute mode request" "0,1" bitfld.long 0x0 1. "SBKRQ,Send break request" "0,1" bitfld.long 0x0 0. "ABRRQ,Auto baud rate request" "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "ISR,Interrupt & status register" bitfld.long 0x0 27. "TXFT,TXFIFO threshold flag" "0,1" bitfld.long 0x0 26. "RXFT,RXFIFO threshold flag" "0,1" bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time flag" "0,1" bitfld.long 0x0 24. "RXFF,RXFIFO Full" "0,1" bitfld.long 0x0 23. "TXFE,TXFIFO Empty" "0,1" bitfld.long 0x0 22. "REACK,REACK" "0,1" bitfld.long 0x0 21. "TEACK,TEACK" "0,1" bitfld.long 0x0 20. "WUF,WUF" "0,1" newline bitfld.long 0x0 19. "RWU,RWU" "0,1" bitfld.long 0x0 18. "SBKF,SBKF" "0,1" bitfld.long 0x0 17. "CMF,CMF" "0,1" bitfld.long 0x0 16. "BUSY,BUSY" "0,1" bitfld.long 0x0 15. "ABRF,ABRF" "0,1" bitfld.long 0x0 14. "ABRE,ABRE" "0,1" bitfld.long 0x0 13. "UDR,SPI slave underrun error flag" "0,1" bitfld.long 0x0 12. "EOBF,EOBF" "0,1" newline bitfld.long 0x0 11. "RTOF,RTOF" "0,1" bitfld.long 0x0 10. "CTS,CTS" "0,1" bitfld.long 0x0 9. "CTSIF,CTSIF" "0,1" bitfld.long 0x0 8. "LBDF,LBDF" "0,1" bitfld.long 0x0 7. "TXE,TXE" "0,1" bitfld.long 0x0 6. "TC,TC" "0,1" bitfld.long 0x0 5. "RXNE,RXNE" "0,1" bitfld.long 0x0 4. "IDLE,IDLE" "0,1" newline bitfld.long 0x0 3. "ORE,ORE" "0,1" bitfld.long 0x0 2. "NF,NF" "0,1" bitfld.long 0x0 1. "FE,FE" "0,1" bitfld.long 0x0 0. "PE,PE" "0,1" wgroup.long 0x20++0x3 line.long 0x0 "ICR,Interrupt flag clear register" bitfld.long 0x0 20. "WUCF,Wakeup from Stop mode clear flag" "0,1" bitfld.long 0x0 17. "CMCF,Character match clear flag" "0,1" bitfld.long 0x0 13. "UDRCF,SPI slave underrun clear flag" "0,1" bitfld.long 0x0 12. "EOBCF,End of block clear flag" "0,1" bitfld.long 0x0 11. "RTOCF,Receiver timeout clear flag" "0,1" bitfld.long 0x0 9. "CTSCF,CTS clear flag" "0,1" bitfld.long 0x0 8. "LBDCF,LIN break detection clear flag" "0,1" bitfld.long 0x0 7. "TCBGTCF,Transmission complete before Guard time clear flag" "0,1" newline bitfld.long 0x0 6. "TCCF,Transmission complete clear flag" "0,1" bitfld.long 0x0 5. "TXFECF,TXFIFO empty clear flag" "0,1" bitfld.long 0x0 4. "IDLECF,Idle line detected clear flag" "0,1" bitfld.long 0x0 3. "ORECF,Overrun error clear flag" "0,1" bitfld.long 0x0 2. "NCF,Noise detected clear flag" "0,1" bitfld.long 0x0 1. "FECF,Framing error clear flag" "0,1" bitfld.long 0x0 0. "PECF,Parity error clear flag" "0,1" rgroup.long 0x24++0x3 line.long 0x0 "RDR,Receive data register" hexmask.long.word 0x0 0.--8. 1. "RDR,Receive data value" group.long 0x28++0x7 line.long 0x0 "TDR,Transmit data register" hexmask.long.word 0x0 0.--8. 1. "TDR,Transmit data value" line.long 0x4 "PRESC,Prescaler register" hexmask.long.byte 0x4 0.--3. 1. "PRESCALER,Clock prescaler" rgroup.long 0x3EC++0x13 line.long 0x0 "HWCFGR2,USART Hardware Configuration register 2" hexmask.long.byte 0x0 4.--7. 1. "CFG2,CFG2" hexmask.long.byte 0x0 0.--3. 1. "CFG1,CFG1" line.long 0x4 "HWCFGR1,USART Hardware Configuration register 1" hexmask.long.byte 0x4 28.--31. 1. "CFG8,CFG8" hexmask.long.byte 0x4 24.--27. 1. "CFG7,CFG7" hexmask.long.byte 0x4 20.--23. 1. "CFG6,CFG6" hexmask.long.byte 0x4 16.--19. 1. "CFG5,CFG5" hexmask.long.byte 0x4 12.--15. 1. "CFG4,CFG4" hexmask.long.byte 0x4 8.--11. 1. "CFG3,CFG3" hexmask.long.byte 0x4 4.--7. 1. "CFG2,CFG2" hexmask.long.byte 0x4 0.--3. 1. "CFG1,CFG1" line.long 0x8 "VERR,EXTI IP Version register" hexmask.long.byte 0x8 4.--7. 1. "MAJREV,Major Revision number" hexmask.long.byte 0x8 0.--3. 1. "MINREV,Minor Revision number" line.long 0xC "IPIDR,EXTI Identification register" hexmask.long 0xC 0.--31. 1. "IPID,IP Identification" line.long 0x10 "SIDR,EXTI Size ID register" hexmask.long 0x10 0.--31. 1. "SID,Size Identification" tree.end tree "USART6" base ad:0x44003000 group.long 0x0++0x17 line.long 0x0 "CR1,Control register 1" bitfld.long 0x0 31. "RXFFIE,RXFIFO Full interrupt enable" "0,1" bitfld.long 0x0 30. "TXFEIE,TXFIFO empty interrupt enable" "0,1" bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0,1" bitfld.long 0x0 28. "M1,Word length" "0,1" bitfld.long 0x0 27. "EOBIE,End of Block interrupt enable" "0,1" bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0,1" hexmask.long.byte 0x0 21.--25. 1. "DEAT,DEAT" hexmask.long.byte 0x0 16.--20. 1. "DEDT,DEDT" newline bitfld.long 0x0 15. "OVER8,Oversampling mode" "0,1" bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0,1" bitfld.long 0x0 13. "MME,Mute mode enable" "0,1" bitfld.long 0x0 12. "M0,Word length" "0,1" bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0,1" bitfld.long 0x0 10. "PCE,Parity control enable" "0,1" bitfld.long 0x0 9. "PS,Parity selection" "0,1" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0,1" newline bitfld.long 0x0 7. "TXEIE,interrupt enable" "0,1" bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0,1" bitfld.long 0x0 5. "RXNEIE,RXNE interrupt enable" "0,1" bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0,1" bitfld.long 0x0 3. "TE,Transmitter enable" "0,1" bitfld.long 0x0 2. "RE,Receiver enable" "0,1" bitfld.long 0x0 1. "UESM,USART enable in Stop mode" "0,1" bitfld.long 0x0 0. "UE,USART enable" "0,1" line.long 0x4 "CR2,Control register 2" hexmask.long.byte 0x4 28.--31. 1. "ADD4_7,Address of the USART node" hexmask.long.byte 0x4 24.--27. 1. "ADD0_3,Address of the USART node" bitfld.long 0x4 23. "RTOEN,Receiver timeout enable" "0,1" bitfld.long 0x4 21.--22. "ABRMOD,Auto baud rate mode" "0,1,2,3" bitfld.long 0x4 20. "ABREN,Auto baud rate enable" "0,1" bitfld.long 0x4 19. "MSBFIRST,Most significant bit first" "0,1" bitfld.long 0x4 18. "TAINV,Binary data inversion" "0,1" bitfld.long 0x4 17. "TXINV,TX pin active level inversion" "0,1" newline bitfld.long 0x4 16. "RXINV,RX pin active level inversion" "0,1" bitfld.long 0x4 15. "SWAP,Swap TX/RX pins" "0,1" bitfld.long 0x4 14. "LINEN,LIN mode enable" "0,1" bitfld.long 0x4 12.--13. "STOP,STOP bits" "0,1,2,3" bitfld.long 0x4 11. "CLKEN,Clock enable" "0,1" bitfld.long 0x4 10. "CPOL,Clock polarity" "0,1" bitfld.long 0x4 9. "CPHA,Clock phase" "0,1" bitfld.long 0x4 8. "LBCL,Last bit clock pulse" "0,1" newline bitfld.long 0x4 6. "LBDIE,LIN break detection interrupt enable" "0,1" bitfld.long 0x4 5. "LBDL,LIN break detection length" "0,1" bitfld.long 0x4 4. "ADDM7,7-bit Address Detection/4-bit Address Detection" "0,1" bitfld.long 0x4 3. "DIS_NSS,When the DSI_NSS bit is set the NSS pin input will be ignored" "0,1" bitfld.long 0x4 0. "SLVEN,Synchronous Slave mode enable" "0,1" line.long 0x8 "CR3,Control register 3" bitfld.long 0x8 29.--31. "TXFTCFG,TXFIFO threshold configuration" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "RXFTIE,RXFIFO threshold interrupt enable" "0,1" bitfld.long 0x8 25.--27. "RXFTCFG,Receive FIFO threshold configuration" "0,1,2,3,4,5,6,7" bitfld.long 0x8 24. "TCBGTIE,Tr Complete before guard time interrupt enable" "0,1" bitfld.long 0x8 23. "TXFTIE,threshold interrupt enable" "0,1" bitfld.long 0x8 22. "WUFIE,Wakeup from Stop mode interrupt enable" "0,1" bitfld.long 0x8 20.--21. "WUS,Wakeup from Stop mode interrupt flag selection" "0,1,2,3" bitfld.long 0x8 17.--19. "SCARCNT,Smartcard auto-retry count" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 15. "DEP,Driver enable polarity selection" "0,1" bitfld.long 0x8 14. "DEM,Driver enable mode" "0,1" bitfld.long 0x8 13. "DDRE,DMA Disable on Reception Error" "0,1" bitfld.long 0x8 12. "OVRDIS,Overrun Disable" "0,1" bitfld.long 0x8 11. "ONEBIT,One sample bit method enable" "0,1" bitfld.long 0x8 10. "CTSIE,CTS interrupt enable" "0,1" bitfld.long 0x8 9. "CTSE,CTS enable" "0,1" bitfld.long 0x8 8. "RTSE,RTS enable" "0,1" newline bitfld.long 0x8 7. "DMAT,DMA enable transmitter" "0,1" bitfld.long 0x8 6. "DMAR,DMA enable receiver" "0,1" bitfld.long 0x8 5. "SCEN,Smartcard mode enable" "0,1" bitfld.long 0x8 4. "NACK,Smartcard NACK enable" "0,1" bitfld.long 0x8 3. "HDSEL,Half-duplex selection" "0,1" bitfld.long 0x8 2. "IRLP,Ir low-power" "0,1" bitfld.long 0x8 1. "IREN,Ir mode enable" "0,1" bitfld.long 0x8 0. "EIE,Error interrupt enable" "0,1" line.long 0xC "BRR,Baud rate register" hexmask.long.word 0xC 4.--15. 1. "BRR_4_15,BRR_4_15" hexmask.long.byte 0xC 0.--3. 1. "BRR_0_3,BRR_0_3" line.long 0x10 "GTPR,Guard time and prescaler register" hexmask.long.byte 0x10 8.--15. 1. "GT,Guard time value" hexmask.long.byte 0x10 0.--7. 1. "PSC,Prescaler value" line.long 0x14 "RTOR,Receiver timeout register" hexmask.long.byte 0x14 24.--31. 1. "BLEN,Block Length" hexmask.long.tbyte 0x14 0.--23. 1. "RTO,Receiver timeout value" wgroup.long 0x18++0x3 line.long 0x0 "RQR,Request register" bitfld.long 0x0 4. "TXFRQ,Transmit data flush request" "0,1" bitfld.long 0x0 3. "RXFRQ,Receive data flush request" "0,1" bitfld.long 0x0 2. "MMRQ,Mute mode request" "0,1" bitfld.long 0x0 1. "SBKRQ,Send break request" "0,1" bitfld.long 0x0 0. "ABRRQ,Auto baud rate request" "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "ISR,Interrupt & status register" bitfld.long 0x0 27. "TXFT,TXFIFO threshold flag" "0,1" bitfld.long 0x0 26. "RXFT,RXFIFO threshold flag" "0,1" bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time flag" "0,1" bitfld.long 0x0 24. "RXFF,RXFIFO Full" "0,1" bitfld.long 0x0 23. "TXFE,TXFIFO Empty" "0,1" bitfld.long 0x0 22. "REACK,REACK" "0,1" bitfld.long 0x0 21. "TEACK,TEACK" "0,1" bitfld.long 0x0 20. "WUF,WUF" "0,1" newline bitfld.long 0x0 19. "RWU,RWU" "0,1" bitfld.long 0x0 18. "SBKF,SBKF" "0,1" bitfld.long 0x0 17. "CMF,CMF" "0,1" bitfld.long 0x0 16. "BUSY,BUSY" "0,1" bitfld.long 0x0 15. "ABRF,ABRF" "0,1" bitfld.long 0x0 14. "ABRE,ABRE" "0,1" bitfld.long 0x0 13. "UDR,SPI slave underrun error flag" "0,1" bitfld.long 0x0 12. "EOBF,EOBF" "0,1" newline bitfld.long 0x0 11. "RTOF,RTOF" "0,1" bitfld.long 0x0 10. "CTS,CTS" "0,1" bitfld.long 0x0 9. "CTSIF,CTSIF" "0,1" bitfld.long 0x0 8. "LBDF,LBDF" "0,1" bitfld.long 0x0 7. "TXE,TXE" "0,1" bitfld.long 0x0 6. "TC,TC" "0,1" bitfld.long 0x0 5. "RXNE,RXNE" "0,1" bitfld.long 0x0 4. "IDLE,IDLE" "0,1" newline bitfld.long 0x0 3. "ORE,ORE" "0,1" bitfld.long 0x0 2. "NF,NF" "0,1" bitfld.long 0x0 1. "FE,FE" "0,1" bitfld.long 0x0 0. "PE,PE" "0,1" wgroup.long 0x20++0x3 line.long 0x0 "ICR,Interrupt flag clear register" bitfld.long 0x0 20. "WUCF,Wakeup from Stop mode clear flag" "0,1" bitfld.long 0x0 17. "CMCF,Character match clear flag" "0,1" bitfld.long 0x0 13. "UDRCF,SPI slave underrun clear flag" "0,1" bitfld.long 0x0 12. "EOBCF,End of block clear flag" "0,1" bitfld.long 0x0 11. "RTOCF,Receiver timeout clear flag" "0,1" bitfld.long 0x0 9. "CTSCF,CTS clear flag" "0,1" bitfld.long 0x0 8. "LBDCF,LIN break detection clear flag" "0,1" bitfld.long 0x0 7. "TCBGTCF,Transmission complete before Guard time clear flag" "0,1" newline bitfld.long 0x0 6. "TCCF,Transmission complete clear flag" "0,1" bitfld.long 0x0 5. "TXFECF,TXFIFO empty clear flag" "0,1" bitfld.long 0x0 4. "IDLECF,Idle line detected clear flag" "0,1" bitfld.long 0x0 3. "ORECF,Overrun error clear flag" "0,1" bitfld.long 0x0 2. "NCF,Noise detected clear flag" "0,1" bitfld.long 0x0 1. "FECF,Framing error clear flag" "0,1" bitfld.long 0x0 0. "PECF,Parity error clear flag" "0,1" rgroup.long 0x24++0x3 line.long 0x0 "RDR,Receive data register" hexmask.long.word 0x0 0.--8. 1. "RDR,Receive data value" group.long 0x28++0x7 line.long 0x0 "TDR,Transmit data register" hexmask.long.word 0x0 0.--8. 1. "TDR,Transmit data value" line.long 0x4 "PRESC,Prescaler register" hexmask.long.byte 0x4 0.--3. 1. "PRESCALER,Clock prescaler" rgroup.long 0x3EC++0x13 line.long 0x0 "HWCFGR2,USART Hardware Configuration register 2" hexmask.long.byte 0x0 4.--7. 1. "CFG2,CFG2" hexmask.long.byte 0x0 0.--3. 1. "CFG1,CFG1" line.long 0x4 "HWCFGR1,USART Hardware Configuration register 1" hexmask.long.byte 0x4 28.--31. 1. "CFG8,CFG8" hexmask.long.byte 0x4 24.--27. 1. "CFG7,CFG7" hexmask.long.byte 0x4 20.--23. 1. "CFG6,CFG6" hexmask.long.byte 0x4 16.--19. 1. "CFG5,CFG5" hexmask.long.byte 0x4 12.--15. 1. "CFG4,CFG4" hexmask.long.byte 0x4 8.--11. 1. "CFG3,CFG3" hexmask.long.byte 0x4 4.--7. 1. "CFG2,CFG2" hexmask.long.byte 0x4 0.--3. 1. "CFG1,CFG1" line.long 0x8 "VERR,EXTI IP Version register" hexmask.long.byte 0x8 4.--7. 1. "MAJREV,Major Revision number" hexmask.long.byte 0x8 0.--3. 1. "MINREV,Minor Revision number" line.long 0xC "IPIDR,EXTI Identification register" hexmask.long 0xC 0.--31. 1. "IPID,IP Identification" line.long 0x10 "SIDR,EXTI Size ID register" hexmask.long 0x10 0.--31. 1. "SID,Size Identification" tree.end endif sif (cpuis("STM32MP157*")) tree "USART7" base ad:0x40018000 group.long 0x0++0x17 line.long 0x0 "CR1,Control register 1" bitfld.long 0x0 31. "RXFFIE,RXFIFO Full interrupt enable" "0,1" bitfld.long 0x0 30. "TXFEIE,TXFIFO empty interrupt enable" "0,1" bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0,1" bitfld.long 0x0 28. "M1,Word length" "0,1" bitfld.long 0x0 27. "EOBIE,End of Block interrupt enable" "0,1" bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0,1" hexmask.long.byte 0x0 21.--25. 1. "DEAT,DEAT" hexmask.long.byte 0x0 16.--20. 1. "DEDT,DEDT" newline bitfld.long 0x0 15. "OVER8,Oversampling mode" "0,1" bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0,1" bitfld.long 0x0 13. "MME,Mute mode enable" "0,1" bitfld.long 0x0 12. "M0,Word length" "0,1" bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0,1" bitfld.long 0x0 10. "PCE,Parity control enable" "0,1" bitfld.long 0x0 9. "PS,Parity selection" "0,1" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0,1" newline bitfld.long 0x0 7. "TXEIE,interrupt enable" "0,1" bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0,1" bitfld.long 0x0 5. "RXNEIE,RXNE interrupt enable" "0,1" bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0,1" bitfld.long 0x0 3. "TE,Transmitter enable" "0,1" bitfld.long 0x0 2. "RE,Receiver enable" "0,1" bitfld.long 0x0 1. "UESM,USART enable in Stop mode" "0,1" bitfld.long 0x0 0. "UE,USART enable" "0,1" line.long 0x4 "CR2,Control register 2" hexmask.long.byte 0x4 28.--31. 1. "ADD4_7,Address of the USART node" hexmask.long.byte 0x4 24.--27. 1. "ADD0_3,Address of the USART node" bitfld.long 0x4 23. "RTOEN,Receiver timeout enable" "0,1" bitfld.long 0x4 21.--22. "ABRMOD,Auto baud rate mode" "0,1,2,3" bitfld.long 0x4 20. "ABREN,Auto baud rate enable" "0,1" bitfld.long 0x4 19. "MSBFIRST,Most significant bit first" "0,1" bitfld.long 0x4 18. "TAINV,Binary data inversion" "0,1" bitfld.long 0x4 17. "TXINV,TX pin active level inversion" "0,1" newline bitfld.long 0x4 16. "RXINV,RX pin active level inversion" "0,1" bitfld.long 0x4 15. "SWAP,Swap TX/RX pins" "0,1" bitfld.long 0x4 14. "LINEN,LIN mode enable" "0,1" bitfld.long 0x4 12.--13. "STOP,STOP bits" "0,1,2,3" bitfld.long 0x4 11. "CLKEN,Clock enable" "0,1" bitfld.long 0x4 10. "CPOL,Clock polarity" "0,1" bitfld.long 0x4 9. "CPHA,Clock phase" "0,1" bitfld.long 0x4 8. "LBCL,Last bit clock pulse" "0,1" newline bitfld.long 0x4 6. "LBDIE,LIN break detection interrupt enable" "0,1" bitfld.long 0x4 5. "LBDL,LIN break detection length" "0,1" bitfld.long 0x4 4. "ADDM7,7-bit Address Detection/4-bit Address Detection" "0,1" bitfld.long 0x4 3. "DIS_NSS,When the DSI_NSS bit is set the NSS pin input will be ignored" "0,1" bitfld.long 0x4 0. "SLVEN,Synchronous Slave mode enable" "0,1" line.long 0x8 "CR3,Control register 3" bitfld.long 0x8 29.--31. "TXFTCFG,TXFIFO threshold configuration" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "RXFTIE,RXFIFO threshold interrupt enable" "0,1" bitfld.long 0x8 25.--27. "RXFTCFG,Receive FIFO threshold configuration" "0,1,2,3,4,5,6,7" bitfld.long 0x8 24. "TCBGTIE,Tr Complete before guard time interrupt enable" "0,1" bitfld.long 0x8 23. "TXFTIE,threshold interrupt enable" "0,1" bitfld.long 0x8 22. "WUFIE,Wakeup from Stop mode interrupt enable" "0,1" bitfld.long 0x8 20.--21. "WUS,Wakeup from Stop mode interrupt flag selection" "0,1,2,3" bitfld.long 0x8 17.--19. "SCARCNT,Smartcard auto-retry count" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 15. "DEP,Driver enable polarity selection" "0,1" bitfld.long 0x8 14. "DEM,Driver enable mode" "0,1" bitfld.long 0x8 13. "DDRE,DMA Disable on Reception Error" "0,1" bitfld.long 0x8 12. "OVRDIS,Overrun Disable" "0,1" bitfld.long 0x8 11. "ONEBIT,One sample bit method enable" "0,1" bitfld.long 0x8 10. "CTSIE,CTS interrupt enable" "0,1" bitfld.long 0x8 9. "CTSE,CTS enable" "0,1" bitfld.long 0x8 8. "RTSE,RTS enable" "0,1" newline bitfld.long 0x8 7. "DMAT,DMA enable transmitter" "0,1" bitfld.long 0x8 6. "DMAR,DMA enable receiver" "0,1" bitfld.long 0x8 5. "SCEN,Smartcard mode enable" "0,1" bitfld.long 0x8 4. "NACK,Smartcard NACK enable" "0,1" bitfld.long 0x8 3. "HDSEL,Half-duplex selection" "0,1" bitfld.long 0x8 2. "IRLP,Ir low-power" "0,1" bitfld.long 0x8 1. "IREN,Ir mode enable" "0,1" bitfld.long 0x8 0. "EIE,Error interrupt enable" "0,1" line.long 0xC "BRR,Baud rate register" hexmask.long.word 0xC 4.--15. 1. "BRR_4_15,BRR_4_15" hexmask.long.byte 0xC 0.--3. 1. "BRR_0_3,BRR_0_3" line.long 0x10 "GTPR,Guard time and prescaler register" hexmask.long.byte 0x10 8.--15. 1. "GT,Guard time value" hexmask.long.byte 0x10 0.--7. 1. "PSC,Prescaler value" line.long 0x14 "RTOR,Receiver timeout register" hexmask.long.byte 0x14 24.--31. 1. "BLEN,Block Length" hexmask.long.tbyte 0x14 0.--23. 1. "RTO,Receiver timeout value" wgroup.long 0x18++0x3 line.long 0x0 "RQR,Request register" bitfld.long 0x0 4. "TXFRQ,Transmit data flush request" "0,1" bitfld.long 0x0 3. "RXFRQ,Receive data flush request" "0,1" bitfld.long 0x0 2. "MMRQ,Mute mode request" "0,1" bitfld.long 0x0 1. "SBKRQ,Send break request" "0,1" bitfld.long 0x0 0. "ABRRQ,Auto baud rate request" "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "ISR,Interrupt & status register" bitfld.long 0x0 27. "TXFT,TXFIFO threshold flag" "0,1" bitfld.long 0x0 26. "RXFT,RXFIFO threshold flag" "0,1" bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time flag" "0,1" bitfld.long 0x0 24. "RXFF,RXFIFO Full" "0,1" bitfld.long 0x0 23. "TXFE,TXFIFO Empty" "0,1" bitfld.long 0x0 22. "REACK,REACK" "0,1" bitfld.long 0x0 21. "TEACK,TEACK" "0,1" bitfld.long 0x0 20. "WUF,WUF" "0,1" newline bitfld.long 0x0 19. "RWU,RWU" "0,1" bitfld.long 0x0 18. "SBKF,SBKF" "0,1" bitfld.long 0x0 17. "CMF,CMF" "0,1" bitfld.long 0x0 16. "BUSY,BUSY" "0,1" bitfld.long 0x0 15. "ABRF,ABRF" "0,1" bitfld.long 0x0 14. "ABRE,ABRE" "0,1" bitfld.long 0x0 13. "UDR,SPI slave underrun error flag" "0,1" bitfld.long 0x0 12. "EOBF,EOBF" "0,1" newline bitfld.long 0x0 11. "RTOF,RTOF" "0,1" bitfld.long 0x0 10. "CTS,CTS" "0,1" bitfld.long 0x0 9. "CTSIF,CTSIF" "0,1" bitfld.long 0x0 8. "LBDF,LBDF" "0,1" bitfld.long 0x0 7. "TXE,TXE" "0,1" bitfld.long 0x0 6. "TC,TC" "0,1" bitfld.long 0x0 5. "RXNE,RXNE" "0,1" bitfld.long 0x0 4. "IDLE,IDLE" "0,1" newline bitfld.long 0x0 3. "ORE,ORE" "0,1" bitfld.long 0x0 2. "NF,NF" "0,1" bitfld.long 0x0 1. "FE,FE" "0,1" bitfld.long 0x0 0. "PE,PE" "0,1" wgroup.long 0x20++0x3 line.long 0x0 "ICR,Interrupt flag clear register" bitfld.long 0x0 20. "WUCF,Wakeup from Stop mode clear flag" "0,1" bitfld.long 0x0 17. "CMCF,Character match clear flag" "0,1" bitfld.long 0x0 13. "UDRCF,SPI slave underrun clear flag" "0,1" bitfld.long 0x0 12. "EOBCF,End of block clear flag" "0,1" bitfld.long 0x0 11. "RTOCF,Receiver timeout clear flag" "0,1" bitfld.long 0x0 9. "CTSCF,CTS clear flag" "0,1" bitfld.long 0x0 8. "LBDCF,LIN break detection clear flag" "0,1" bitfld.long 0x0 7. "TCBGTCF,Transmission complete before Guard time clear flag" "0,1" newline bitfld.long 0x0 6. "TCCF,Transmission complete clear flag" "0,1" bitfld.long 0x0 5. "TXFECF,TXFIFO empty clear flag" "0,1" bitfld.long 0x0 4. "IDLECF,Idle line detected clear flag" "0,1" bitfld.long 0x0 3. "ORECF,Overrun error clear flag" "0,1" bitfld.long 0x0 2. "NCF,Noise detected clear flag" "0,1" bitfld.long 0x0 1. "FECF,Framing error clear flag" "0,1" bitfld.long 0x0 0. "PECF,Parity error clear flag" "0,1" rgroup.long 0x24++0x3 line.long 0x0 "RDR,Receive data register" hexmask.long.word 0x0 0.--8. 1. "RDR,Receive data value" group.long 0x28++0x7 line.long 0x0 "TDR,Transmit data register" hexmask.long.word 0x0 0.--8. 1. "TDR,Transmit data value" line.long 0x4 "PRESC,Prescaler register" hexmask.long.byte 0x4 0.--3. 1. "PRESCALER,Clock prescaler" rgroup.long 0x3EC++0x13 line.long 0x0 "HWCFGR2,USART Hardware Configuration register 2" hexmask.long.byte 0x0 4.--7. 1. "CFG2,CFG2" hexmask.long.byte 0x0 0.--3. 1. "CFG1,CFG1" line.long 0x4 "HWCFGR1,USART Hardware Configuration register 1" hexmask.long.byte 0x4 28.--31. 1. "CFG8,CFG8" hexmask.long.byte 0x4 24.--27. 1. "CFG7,CFG7" hexmask.long.byte 0x4 20.--23. 1. "CFG6,CFG6" hexmask.long.byte 0x4 16.--19. 1. "CFG5,CFG5" hexmask.long.byte 0x4 12.--15. 1. "CFG4,CFG4" hexmask.long.byte 0x4 8.--11. 1. "CFG3,CFG3" hexmask.long.byte 0x4 4.--7. 1. "CFG2,CFG2" hexmask.long.byte 0x4 0.--3. 1. "CFG1,CFG1" line.long 0x8 "VERR,EXTI IP Version register" hexmask.long.byte 0x8 4.--7. 1. "MAJREV,Major Revision number" hexmask.long.byte 0x8 0.--3. 1. "MINREV,Minor Revision number" line.long 0xC "IPIDR,EXTI Identification register" hexmask.long 0xC 0.--31. 1. "IPID,IP Identification" line.long 0x10 "SIDR,EXTI Size ID register" hexmask.long 0x10 0.--31. 1. "SID,Size Identification" tree.end tree "USART8" base ad:0x40019000 group.long 0x0++0x17 line.long 0x0 "CR1,Control register 1" bitfld.long 0x0 31. "RXFFIE,RXFIFO Full interrupt enable" "0,1" bitfld.long 0x0 30. "TXFEIE,TXFIFO empty interrupt enable" "0,1" bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0,1" bitfld.long 0x0 28. "M1,Word length" "0,1" bitfld.long 0x0 27. "EOBIE,End of Block interrupt enable" "0,1" bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0,1" hexmask.long.byte 0x0 21.--25. 1. "DEAT,DEAT" hexmask.long.byte 0x0 16.--20. 1. "DEDT,DEDT" newline bitfld.long 0x0 15. "OVER8,Oversampling mode" "0,1" bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0,1" bitfld.long 0x0 13. "MME,Mute mode enable" "0,1" bitfld.long 0x0 12. "M0,Word length" "0,1" bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0,1" bitfld.long 0x0 10. "PCE,Parity control enable" "0,1" bitfld.long 0x0 9. "PS,Parity selection" "0,1" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0,1" newline bitfld.long 0x0 7. "TXEIE,interrupt enable" "0,1" bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0,1" bitfld.long 0x0 5. "RXNEIE,RXNE interrupt enable" "0,1" bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0,1" bitfld.long 0x0 3. "TE,Transmitter enable" "0,1" bitfld.long 0x0 2. "RE,Receiver enable" "0,1" bitfld.long 0x0 1. "UESM,USART enable in Stop mode" "0,1" bitfld.long 0x0 0. "UE,USART enable" "0,1" line.long 0x4 "CR2,Control register 2" hexmask.long.byte 0x4 28.--31. 1. "ADD4_7,Address of the USART node" hexmask.long.byte 0x4 24.--27. 1. "ADD0_3,Address of the USART node" bitfld.long 0x4 23. "RTOEN,Receiver timeout enable" "0,1" bitfld.long 0x4 21.--22. "ABRMOD,Auto baud rate mode" "0,1,2,3" bitfld.long 0x4 20. "ABREN,Auto baud rate enable" "0,1" bitfld.long 0x4 19. "MSBFIRST,Most significant bit first" "0,1" bitfld.long 0x4 18. "TAINV,Binary data inversion" "0,1" bitfld.long 0x4 17. "TXINV,TX pin active level inversion" "0,1" newline bitfld.long 0x4 16. "RXINV,RX pin active level inversion" "0,1" bitfld.long 0x4 15. "SWAP,Swap TX/RX pins" "0,1" bitfld.long 0x4 14. "LINEN,LIN mode enable" "0,1" bitfld.long 0x4 12.--13. "STOP,STOP bits" "0,1,2,3" bitfld.long 0x4 11. "CLKEN,Clock enable" "0,1" bitfld.long 0x4 10. "CPOL,Clock polarity" "0,1" bitfld.long 0x4 9. "CPHA,Clock phase" "0,1" bitfld.long 0x4 8. "LBCL,Last bit clock pulse" "0,1" newline bitfld.long 0x4 6. "LBDIE,LIN break detection interrupt enable" "0,1" bitfld.long 0x4 5. "LBDL,LIN break detection length" "0,1" bitfld.long 0x4 4. "ADDM7,7-bit Address Detection/4-bit Address Detection" "0,1" bitfld.long 0x4 3. "DIS_NSS,When the DSI_NSS bit is set the NSS pin input will be ignored" "0,1" bitfld.long 0x4 0. "SLVEN,Synchronous Slave mode enable" "0,1" line.long 0x8 "CR3,Control register 3" bitfld.long 0x8 29.--31. "TXFTCFG,TXFIFO threshold configuration" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "RXFTIE,RXFIFO threshold interrupt enable" "0,1" bitfld.long 0x8 25.--27. "RXFTCFG,Receive FIFO threshold configuration" "0,1,2,3,4,5,6,7" bitfld.long 0x8 24. "TCBGTIE,Tr Complete before guard time interrupt enable" "0,1" bitfld.long 0x8 23. "TXFTIE,threshold interrupt enable" "0,1" bitfld.long 0x8 22. "WUFIE,Wakeup from Stop mode interrupt enable" "0,1" bitfld.long 0x8 20.--21. "WUS,Wakeup from Stop mode interrupt flag selection" "0,1,2,3" bitfld.long 0x8 17.--19. "SCARCNT,Smartcard auto-retry count" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 15. "DEP,Driver enable polarity selection" "0,1" bitfld.long 0x8 14. "DEM,Driver enable mode" "0,1" bitfld.long 0x8 13. "DDRE,DMA Disable on Reception Error" "0,1" bitfld.long 0x8 12. "OVRDIS,Overrun Disable" "0,1" bitfld.long 0x8 11. "ONEBIT,One sample bit method enable" "0,1" bitfld.long 0x8 10. "CTSIE,CTS interrupt enable" "0,1" bitfld.long 0x8 9. "CTSE,CTS enable" "0,1" bitfld.long 0x8 8. "RTSE,RTS enable" "0,1" newline bitfld.long 0x8 7. "DMAT,DMA enable transmitter" "0,1" bitfld.long 0x8 6. "DMAR,DMA enable receiver" "0,1" bitfld.long 0x8 5. "SCEN,Smartcard mode enable" "0,1" bitfld.long 0x8 4. "NACK,Smartcard NACK enable" "0,1" bitfld.long 0x8 3. "HDSEL,Half-duplex selection" "0,1" bitfld.long 0x8 2. "IRLP,Ir low-power" "0,1" bitfld.long 0x8 1. "IREN,Ir mode enable" "0,1" bitfld.long 0x8 0. "EIE,Error interrupt enable" "0,1" line.long 0xC "BRR,Baud rate register" hexmask.long.word 0xC 4.--15. 1. "BRR_4_15,BRR_4_15" hexmask.long.byte 0xC 0.--3. 1. "BRR_0_3,BRR_0_3" line.long 0x10 "GTPR,Guard time and prescaler register" hexmask.long.byte 0x10 8.--15. 1. "GT,Guard time value" hexmask.long.byte 0x10 0.--7. 1. "PSC,Prescaler value" line.long 0x14 "RTOR,Receiver timeout register" hexmask.long.byte 0x14 24.--31. 1. "BLEN,Block Length" hexmask.long.tbyte 0x14 0.--23. 1. "RTO,Receiver timeout value" wgroup.long 0x18++0x3 line.long 0x0 "RQR,Request register" bitfld.long 0x0 4. "TXFRQ,Transmit data flush request" "0,1" bitfld.long 0x0 3. "RXFRQ,Receive data flush request" "0,1" bitfld.long 0x0 2. "MMRQ,Mute mode request" "0,1" bitfld.long 0x0 1. "SBKRQ,Send break request" "0,1" bitfld.long 0x0 0. "ABRRQ,Auto baud rate request" "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "ISR,Interrupt & status register" bitfld.long 0x0 27. "TXFT,TXFIFO threshold flag" "0,1" bitfld.long 0x0 26. "RXFT,RXFIFO threshold flag" "0,1" bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time flag" "0,1" bitfld.long 0x0 24. "RXFF,RXFIFO Full" "0,1" bitfld.long 0x0 23. "TXFE,TXFIFO Empty" "0,1" bitfld.long 0x0 22. "REACK,REACK" "0,1" bitfld.long 0x0 21. "TEACK,TEACK" "0,1" bitfld.long 0x0 20. "WUF,WUF" "0,1" newline bitfld.long 0x0 19. "RWU,RWU" "0,1" bitfld.long 0x0 18. "SBKF,SBKF" "0,1" bitfld.long 0x0 17. "CMF,CMF" "0,1" bitfld.long 0x0 16. "BUSY,BUSY" "0,1" bitfld.long 0x0 15. "ABRF,ABRF" "0,1" bitfld.long 0x0 14. "ABRE,ABRE" "0,1" bitfld.long 0x0 13. "UDR,SPI slave underrun error flag" "0,1" bitfld.long 0x0 12. "EOBF,EOBF" "0,1" newline bitfld.long 0x0 11. "RTOF,RTOF" "0,1" bitfld.long 0x0 10. "CTS,CTS" "0,1" bitfld.long 0x0 9. "CTSIF,CTSIF" "0,1" bitfld.long 0x0 8. "LBDF,LBDF" "0,1" bitfld.long 0x0 7. "TXE,TXE" "0,1" bitfld.long 0x0 6. "TC,TC" "0,1" bitfld.long 0x0 5. "RXNE,RXNE" "0,1" bitfld.long 0x0 4. "IDLE,IDLE" "0,1" newline bitfld.long 0x0 3. "ORE,ORE" "0,1" bitfld.long 0x0 2. "NF,NF" "0,1" bitfld.long 0x0 1. "FE,FE" "0,1" bitfld.long 0x0 0. "PE,PE" "0,1" wgroup.long 0x20++0x3 line.long 0x0 "ICR,Interrupt flag clear register" bitfld.long 0x0 20. "WUCF,Wakeup from Stop mode clear flag" "0,1" bitfld.long 0x0 17. "CMCF,Character match clear flag" "0,1" bitfld.long 0x0 13. "UDRCF,SPI slave underrun clear flag" "0,1" bitfld.long 0x0 12. "EOBCF,End of block clear flag" "0,1" bitfld.long 0x0 11. "RTOCF,Receiver timeout clear flag" "0,1" bitfld.long 0x0 9. "CTSCF,CTS clear flag" "0,1" bitfld.long 0x0 8. "LBDCF,LIN break detection clear flag" "0,1" bitfld.long 0x0 7. "TCBGTCF,Transmission complete before Guard time clear flag" "0,1" newline bitfld.long 0x0 6. "TCCF,Transmission complete clear flag" "0,1" bitfld.long 0x0 5. "TXFECF,TXFIFO empty clear flag" "0,1" bitfld.long 0x0 4. "IDLECF,Idle line detected clear flag" "0,1" bitfld.long 0x0 3. "ORECF,Overrun error clear flag" "0,1" bitfld.long 0x0 2. "NCF,Noise detected clear flag" "0,1" bitfld.long 0x0 1. "FECF,Framing error clear flag" "0,1" bitfld.long 0x0 0. "PECF,Parity error clear flag" "0,1" rgroup.long 0x24++0x3 line.long 0x0 "RDR,Receive data register" hexmask.long.word 0x0 0.--8. 1. "RDR,Receive data value" group.long 0x28++0x7 line.long 0x0 "TDR,Transmit data register" hexmask.long.word 0x0 0.--8. 1. "TDR,Transmit data value" line.long 0x4 "PRESC,Prescaler register" hexmask.long.byte 0x4 0.--3. 1. "PRESCALER,Clock prescaler" rgroup.long 0x3EC++0x13 line.long 0x0 "HWCFGR2,USART Hardware Configuration register 2" hexmask.long.byte 0x0 4.--7. 1. "CFG2,CFG2" hexmask.long.byte 0x0 0.--3. 1. "CFG1,CFG1" line.long 0x4 "HWCFGR1,USART Hardware Configuration register 1" hexmask.long.byte 0x4 28.--31. 1. "CFG8,CFG8" hexmask.long.byte 0x4 24.--27. 1. "CFG7,CFG7" hexmask.long.byte 0x4 20.--23. 1. "CFG6,CFG6" hexmask.long.byte 0x4 16.--19. 1. "CFG5,CFG5" hexmask.long.byte 0x4 12.--15. 1. "CFG4,CFG4" hexmask.long.byte 0x4 8.--11. 1. "CFG3,CFG3" hexmask.long.byte 0x4 4.--7. 1. "CFG2,CFG2" hexmask.long.byte 0x4 0.--3. 1. "CFG1,CFG1" line.long 0x8 "VERR,EXTI IP Version register" hexmask.long.byte 0x8 4.--7. 1. "MAJREV,Major Revision number" hexmask.long.byte 0x8 0.--3. 1. "MINREV,Minor Revision number" line.long 0xC "IPIDR,EXTI Identification register" hexmask.long 0xC 0.--31. 1. "IPID,IP Identification" line.long 0x10 "SIDR,EXTI Size ID register" hexmask.long 0x10 0.--31. 1. "SID,Size Identification" tree.end endif tree.end tree "USBPHYC (USB HS PHY Controller)" base ad:0x5A006000 group.long 0x0++0x3 line.long 0x0 "USBPHYC_PLL,USBPHYC PLL control register" sif (cpuis("STM32MP13*")) bitfld.long 0x0 31. "PLLDITHEN1,PLL dither 1 (rectangular)" "0: Enables the rectangular PDF dither input to SDM..,1: Disables the rectangular PDF dither input to SDM.." bitfld.long 0x0 30. "PLLDITHEN0,PLL dither 2 (triangular)" "0: Enables the triangular PDF dither input to SDM..,1: Disables the triangular PDF dither input to SDM.." newline bitfld.long 0x0 29. "PLLFRACCTL,PLL fractional mode control" "0: Fractional mode off,1: Fractional mode on" bitfld.long 0x0 28. "PLLSTRBYP,PLL strobe bypass" "0: Do not bypass the strobe signal,1: Bypass the strobe signal" newline bitfld.long 0x0 27. "PLLSTRB,PLL strobe" "0: Strobe set to 0,1: Strobe set to 1" bitfld.long 0x0 26. "PLLEN,PLL enable" "0: PLL disabled,1: PLL enabled" newline endif sif (cpuis("STM32MP151*")) bitfld.long 0x0 31. "PLLDITHEN1,PLLDITHEN1" "0,1" bitfld.long 0x0 30. "PLLDITHEN0,PLLDITHEN0" "0,1" newline bitfld.long 0x0 29. "PLLFRACCTL,PLLFRACCTL" "0,1" bitfld.long 0x0 28. "PLLSTRBYP,PLLSTRBYP" "0,1" newline bitfld.long 0x0 27. "PLLSTRB,PLLSTRB" "0,1" bitfld.long 0x0 26. "PLLEN,PLLEN" "0,1" newline endif sif (cpuis("STM32MP153*")) bitfld.long 0x0 31. "PLLDITHEN1,PLLDITHEN1" "0,1" bitfld.long 0x0 30. "PLLDITHEN0,PLLDITHEN0" "0,1" newline bitfld.long 0x0 29. "PLLFRACCTL,PLLFRACCTL" "0,1" bitfld.long 0x0 28. "PLLSTRBYP,PLLSTRBYP" "0,1" newline bitfld.long 0x0 27. "PLLSTRB,PLLSTRB" "0,1" bitfld.long 0x0 26. "PLLEN,PLLEN" "0,1" newline endif sif (cpuis("STM32MP157*")) bitfld.long 0x0 31. "PLLDITHEN1,PLLDITHEN1" "0,1" bitfld.long 0x0 30. "PLLDITHEN0,PLLDITHEN0" "0,1" newline bitfld.long 0x0 29. "PLLFRACCTL,PLLFRACCTL" "0,1" bitfld.long 0x0 28. "PLLSTRBYP,PLLSTRBYP" "0,1" newline bitfld.long 0x0 27. "PLLSTRB,PLLSTRB" "0,1" bitfld.long 0x0 26. "PLLEN,PLLEN" "0,1" newline endif hexmask.long.word 0x0 10.--25. 1. "PLLFRACIN,PLL fractional input" bitfld.long 0x0 7.--9. "PLLODF,PLL output division factor" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 0.--6. 1. "PLLNDIV,Loop division factor of PLL (integer part)" group.long 0x8++0x3 line.long 0x0 "USBPHYC_MISC,USBPHYC misc control register" sif (cpuis("STM32MP13*")) bitfld.long 0x0 1.--2. "PPCKDIS,Intelligent per HS PHY port clock gating control" "0: No clock gating. PHY dedicated 60 MHz..,1: Intelligent clock gating for Port1. Port1 60 MHz..,2: Intelligent clock gating for Port2. Port2 60 MHz..,3: Intelligent clock gating for Port1 and Port2." bitfld.long 0x0 0. "SWITHOST,Switch host" "0: Select OTG controller for 2nd PHY port,1: Select Host controller for 2nd PHY port" newline endif sif (cpuis("STM32MP151*")) bitfld.long 0x0 1.--2. "PPCKDIS,PPCKDIS" "0,1,2,3" endif sif (cpuis("STM32MP153*")) bitfld.long 0x0 1.--2. "PPCKDIS,PPCKDIS" "0,1,2,3" newline bitfld.long 0x0 0. "SWITHOST,SWITHOST" "0,1" endif sif (cpuis("STM32MP157*")) bitfld.long 0x0 1.--2. "PPCKDIS,PPCKDIS" "0,1,2,3" newline bitfld.long 0x0 0. "SWITHOST,SWITHOST" "0,1" endif group.long 0x10C++0x3 line.long 0x0 "USBPHYC_TUNE1,USBPHYC PHY 1 TUNE register" sif (cpuis("STM32MP13*")) bitfld.long 0x0 27. "STAGSEL,Staggering selection" "0: Disable the basic staggering in HS Tx mode,1: Enable the basic staggering in HS Tx mode" bitfld.long 0x0 26. "SHTCCTCTLPROT,Short circuit control protection" "0: Short circuit protection disabled,1: Short circuit protection enabled" newline bitfld.long 0x0 25. "HSFALLPREEM,HS fall time pre-emphasis" "0: Control On,1: Control Off" bitfld.long 0x0 23.--24. "HSRXOFF,HS receiver offset adjustment" "0: No offset,1: Offset +5 mV,2: Offset +10 mV,3: Offset -5 mV" newline bitfld.long 0x0 22. "HDRXGNEQEN,Enable HS Rx gain equalizer" "0: Disable the gain equalizer,1: Enable the gain equalizer" bitfld.long 0x0 20.--21. "SQLCHCTL,Squelch control" "0: No shift in threshold,1: Squelch DC threshold shift by +7 mV,2: Squelch DC threshold shift by -5 mV,3: Squelch DC threshold shift by +14 mV" newline bitfld.long 0x0 13.--14. "HSDRVCHKZTRM,HS driver choke impedance trim" "0: No impedance offset,1: Reduce the impedance by 2 Ω,2: Reduce the impedance by 4 Ω,3: Reduce the impedance by 6 Ω" hexmask.long.byte 0x0 9.--12. 1. "HSDRVCHKITRM,HS driver choke current trim" newline bitfld.long 0x0 8. "HSDRVRFRED,High-speed rise-fall reduction enable" "0: Default rise/fall time,1: Increases the rise/fall time by 20%" bitfld.long 0x0 7. "FSDRVRFADJ,Tuning pin to adjust the full speed rise/fall time" "0: Disables the full speed rise/fall tuning option,1: Enables the full speed rise/fall tuning option" newline bitfld.long 0x0 6. "HSDRVCURINCR,Enable the HS driver current increase feature" "0: Disables the HSDRVDCLEV feature,1: Enables the HSDRVDCLEV feature" bitfld.long 0x0 5. "HSDRVDCLEV,HS driver DC level" "0: Increases the HS driver DC level by 5 to 7 mV if..,1: Increases the HS driver DC level by 10 to 14 mV.." newline bitfld.long 0x0 4. "HSDRVDCCUR,HS driver DC level" "0: Keeps the normal HS driver DC level,1: Decreases the HS driver DC level by 5 to 7 mV" bitfld.long 0x0 3. "HSDRVSLEW,HS driver slew rate" "0: Keeps the normal slew rate,1: Slows the driver slew rate by 10%" newline bitfld.long 0x0 2. "LFSCAPEN,Low full speed enable" "0: Disables the feedback capacitor.,1: Enables the feedback capacitor." bitfld.long 0x0 1. "INCURRINT,Current boosting value" "0: Provides a current boosting of 1mA if INCURREN =..,1: Provides a current boosting of 2mA if INCURREN =.." newline bitfld.long 0x0 0. "INCURREN,The bit enables the current boosting function." "0: Disables the current boosting,1: Enables the current boosting" endif sif (cpuis("STM32MP151*")) bitfld.long 0x0 27. "STAGSEL,STAGSEL" "0,1" newline bitfld.long 0x0 26. "SHTCCTCTLPROT,SHTCCTCTLPROT" "0,1" bitfld.long 0x0 25. "HSFALLPREEM,HSFALLPREEM" "0,1" newline bitfld.long 0x0 23.--24. "HSRXOFF,HSRXOFF" "0,1,2,3" bitfld.long 0x0 22. "HDRXGNEQEN,HDRXGNEQEN" "0,1" newline bitfld.long 0x0 20.--21. "SQLCHCTL,SQLCHCTL" "0,1,2,3" endif sif (cpuis("STM32MP153*")) bitfld.long 0x0 27. "STAGSEL,STAGSEL" "0,1" newline bitfld.long 0x0 26. "SHTCCTCTLPROT,SHTCCTCTLPROT" "0,1" bitfld.long 0x0 25. "HSFALLPREEM,HSFALLPREEM" "0,1" newline bitfld.long 0x0 23.--24. "HSRXOFF,HSRXOFF" "0,1,2,3" bitfld.long 0x0 22. "HDRXGNEQEN,HDRXGNEQEN" "0,1" newline bitfld.long 0x0 20.--21. "SQLCHCTL,SQLCHCTL" "0,1,2,3" endif sif (cpuis("STM32MP157*")) bitfld.long 0x0 27. "STAGSEL,STAGSEL" "0,1" newline bitfld.long 0x0 26. "SHTCCTCTLPROT,SHTCCTCTLPROT" "0,1" bitfld.long 0x0 25. "HSFALLPREEM,HSFALLPREEM" "0,1" newline bitfld.long 0x0 23.--24. "HSRXOFF,HSRXOFF" "0,1,2,3" bitfld.long 0x0 22. "HDRXGNEQEN,HDRXGNEQEN" "0,1" newline bitfld.long 0x0 20.--21. "SQLCHCTL,SQLCHCTL" "0,1,2,3" endif hexmask.long.byte 0x0 15.--19. 1. "OTPCOMP,OTP compensation code" newline sif (cpuis("STM32MP151*")) bitfld.long 0x0 13.--14. "HSDRVCHKZTRM,HSDRVCHKZTRM" "0,1,2,3" hexmask.long.byte 0x0 9.--12. 1. "HSDRVCHKITRM,HSDRVCHKITRM" newline bitfld.long 0x0 8. "HSDRVRFRED,HSDRVRFRED" "0,1" bitfld.long 0x0 7. "FSDRVRFADJ,FSDRVRFADJ" "0,1" newline bitfld.long 0x0 6. "HSDRVCURINCR,HSDRVCURINCR" "0,1" bitfld.long 0x0 5. "HSDRVDCLEV,HSDRVDCLEV" "0,1" newline bitfld.long 0x0 4. "HSDRVDCCUR,HSDRVDCCUR" "0,1" bitfld.long 0x0 3. "HSDRVSLEW,HSDRVSLEW" "0,1" newline bitfld.long 0x0 2. "LFSCAPEN,LFSCAPEN" "0,1" bitfld.long 0x0 1. "INCURRINT,INCURRINT" "0,1" newline endif sif (cpuis("STM32MP153*")) bitfld.long 0x0 13.--14. "HSDRVCHKZTRM,HSDRVCHKZTRM" "0,1,2,3" hexmask.long.byte 0x0 9.--12. 1. "HSDRVCHKITRM,HSDRVCHKITRM" newline bitfld.long 0x0 8. "HSDRVRFRED,HSDRVRFRED" "0,1" bitfld.long 0x0 7. "FSDRVRFADJ,FSDRVRFADJ" "0,1" newline bitfld.long 0x0 6. "HSDRVCURINCR,HSDRVCURINCR" "0,1" bitfld.long 0x0 5. "HSDRVDCLEV,HSDRVDCLEV" "0,1" newline bitfld.long 0x0 4. "HSDRVDCCUR,HSDRVDCCUR" "0,1" bitfld.long 0x0 3. "HSDRVSLEW,HSDRVSLEW" "0,1" newline bitfld.long 0x0 2. "LFSCAPEN,LFSCAPEN" "0,1" bitfld.long 0x0 1. "INCURRINT,INCURRINT" "0,1" newline bitfld.long 0x0 0. "INCURREN,INCURREN" "0,1" endif sif (cpuis("STM32MP157*")) bitfld.long 0x0 13.--14. "HSDRVCHKZTRM,HSDRVCHKZTRM" "0,1,2,3" newline hexmask.long.byte 0x0 9.--12. 1. "HSDRVCHKITRM,HSDRVCHKITRM" bitfld.long 0x0 8. "HSDRVRFRED,HSDRVRFRED" "0,1" newline bitfld.long 0x0 7. "FSDRVRFADJ,FSDRVRFADJ" "0,1" bitfld.long 0x0 6. "HSDRVCURINCR,HSDRVCURINCR" "0,1" newline bitfld.long 0x0 5. "HSDRVDCLEV,HSDRVDCLEV" "0,1" bitfld.long 0x0 4. "HSDRVDCCUR,HSDRVDCCUR" "0,1" newline bitfld.long 0x0 3. "HSDRVSLEW,HSDRVSLEW" "0,1" bitfld.long 0x0 2. "LFSCAPEN,LFSCAPEN" "0,1" newline bitfld.long 0x0 1. "INCURRINT,INCURRINT" "0,1" bitfld.long 0x0 0. "INCURREN,INCURREN" "0,1" endif group.long 0x20C++0x3 line.long 0x0 "USBPHYC_TUNE2,USBPHYC PHY 2 TUNE register" sif (cpuis("STM32MP13*")) bitfld.long 0x0 27. "STAGSEL,Staggering selection" "0: Disable the basic staggering in HS Tx mode,1: Enable the basic staggering in HS Tx mode" bitfld.long 0x0 26. "SHTCCTCTLPROT,Short circuit control protection" "0: Short circuit protection disabled,1: Short circuit protection enabled" newline bitfld.long 0x0 25. "HSFALLPREEM,HS fall time pre-emphasis" "0: Control On,1: Control Off" bitfld.long 0x0 23.--24. "HSRXOFF,HS receiver offset adjustment" "0: No offset,1: Offset +5 mV,2: Offset +10 mV,3: Offset -5 mV" newline bitfld.long 0x0 22. "HDRXGNEQEN,Enable HS Rx gain equalizer" "0: Disable the gain equalizer,1: Enable the gain equalizer" bitfld.long 0x0 20.--21. "SQLCHCTL,Squelch control" "0: No shift in threshold,1: Squelch DC threshold shift by +7 mV,2: Squelch DC threshold shift by -5 mV,3: Squelch DC threshold shift by +14 mV" newline bitfld.long 0x0 13.--14. "HSDRVCHKZTRM,HS driver choke impedance trim" "0: No impedance offset,1: Reduce the impedance by 2 Ω,2: Reduce the impedance by 4 Ω,3: Reduce the impedance by 6 Ω" hexmask.long.byte 0x0 9.--12. 1. "HSDRVCHKITRM,HS driver choke current trim" newline bitfld.long 0x0 8. "HSDRVRFRED,High-speed rise-fall reduction enable" "0: Default rise/fall time,1: Increases the rise/fall time by 20%" bitfld.long 0x0 7. "FSDRVRFADJ,Tuning pin to adjust the full speed rise/fall time" "0: Disables the full speed rise/fall tuning option,1: Enables the full speed rise/fall tuning option" newline bitfld.long 0x0 6. "HSDRVCURINCR,Enable the HS driver current increase feature" "0: Disables the HSDRVDCLEV feature,1: Enables the HSDRVDCLEV feature" bitfld.long 0x0 5. "HSDRVDCLEV,HS driver DC level" "0: Increases the HS driver DC level by 5 to 7 mV if..,1: Increases the HS driver DC level by 10 to 14 mV.." newline bitfld.long 0x0 4. "HSDRVDCCUR,HS driver DC level" "0: Keeps the normal HS driver DC level,1: Decreases the HS driver DC level by 5 to 7 mV" bitfld.long 0x0 3. "HSDRVSLEW,HS driver slew rate" "0: Keeps the normal slew rate,1: Slows the driver slew rate by 10%" newline bitfld.long 0x0 2. "LFSCAPEN,Low full speed enable" "0: Disables the feedback capacitor.,1: Enables the feedback capacitor." bitfld.long 0x0 1. "INCURRINT,Current boosting value" "0: Provides a current boosting of 1mA if INCURREN =..,1: Provides a current boosting of 2mA if INCURREN =.." newline bitfld.long 0x0 0. "INCURREN,The bit enables the current boosting function." "0: Disables the current boosting,1: Enables the current boosting" endif sif (cpuis("STM32MP151*")) bitfld.long 0x0 27. "STAGSEL,STAGSEL" "0,1" newline bitfld.long 0x0 26. "SHTCCTCTLPROT,SHTCCTCTLPROT" "0,1" bitfld.long 0x0 25. "HSFALLPREEM,HSFALLPREEM" "0,1" newline bitfld.long 0x0 23.--24. "HSRXOFF,HSRXOFF" "0,1,2,3" bitfld.long 0x0 22. "HDRXGNEQEN,HDRXGNEQEN" "0,1" newline bitfld.long 0x0 20.--21. "SQLCHCTL,SQLCHCTL" "0,1,2,3" endif sif (cpuis("STM32MP153*")) bitfld.long 0x0 27. "STAGSEL,STAGSEL" "0,1" newline bitfld.long 0x0 26. "SHTCCTCTLPROT,SHTCCTCTLPROT" "0,1" bitfld.long 0x0 25. "HSFALLPREEM,HSFALLPREEM" "0,1" newline bitfld.long 0x0 23.--24. "HSRXOFF,HSRXOFF" "0,1,2,3" bitfld.long 0x0 22. "HDRXGNEQEN,HDRXGNEQEN" "0,1" newline bitfld.long 0x0 20.--21. "SQLCHCTL,SQLCHCTL" "0,1,2,3" endif sif (cpuis("STM32MP157*")) bitfld.long 0x0 27. "STAGSEL,STAGSEL" "0,1" newline bitfld.long 0x0 26. "SHTCCTCTLPROT,SHTCCTCTLPROT" "0,1" bitfld.long 0x0 25. "HSFALLPREEM,HSFALLPREEM" "0,1" newline bitfld.long 0x0 23.--24. "HSRXOFF,HSRXOFF" "0,1,2,3" bitfld.long 0x0 22. "HDRXGNEQEN,HDRXGNEQEN" "0,1" newline bitfld.long 0x0 20.--21. "SQLCHCTL,SQLCHCTL" "0,1,2,3" endif hexmask.long.byte 0x0 15.--19. 1. "OTPCOMP,OTP compensation code" newline sif (cpuis("STM32MP151*")) bitfld.long 0x0 13.--14. "HSDRVCHKZTRM,HSDRVCHKZTRM" "0,1,2,3" hexmask.long.byte 0x0 9.--12. 1. "HSDRVCHKITRM,HSDRVCHKITRM" newline bitfld.long 0x0 8. "HSDRVRFRED,HSDRVRFRED" "0,1" bitfld.long 0x0 7. "FSDRVRFADJ,FSDRVRFADJ" "0,1" newline bitfld.long 0x0 6. "HSDRVCURINCR,HSDRVCURINCR" "0,1" bitfld.long 0x0 5. "HSDRVDCLEV,HSDRVDCLEV" "0,1" newline bitfld.long 0x0 4. "HSDRVDCCUR,HSDRVDCCUR" "0,1" bitfld.long 0x0 3. "HSDRVSLEW,HSDRVSLEW" "0,1" newline bitfld.long 0x0 2. "LFSCAPEN,LFSCAPEN" "0,1" bitfld.long 0x0 1. "INCURRINT,INCURRINT" "0,1" newline endif sif (cpuis("STM32MP153*")) bitfld.long 0x0 13.--14. "HSDRVCHKZTRM,HSDRVCHKZTRM" "0,1,2,3" hexmask.long.byte 0x0 9.--12. 1. "HSDRVCHKITRM,HSDRVCHKITRM" newline bitfld.long 0x0 8. "HSDRVRFRED,HSDRVRFRED" "0,1" bitfld.long 0x0 7. "FSDRVRFADJ,FSDRVRFADJ" "0,1" newline bitfld.long 0x0 6. "HSDRVCURINCR,HSDRVCURINCR" "0,1" bitfld.long 0x0 5. "HSDRVDCLEV,HSDRVDCLEV" "0,1" newline bitfld.long 0x0 4. "HSDRVDCCUR,HSDRVDCCUR" "0,1" bitfld.long 0x0 3. "HSDRVSLEW,HSDRVSLEW" "0,1" newline bitfld.long 0x0 2. "LFSCAPEN,LFSCAPEN" "0,1" bitfld.long 0x0 1. "INCURRINT,INCURRINT" "0,1" newline bitfld.long 0x0 0. "INCURREN,INCURREN" "0,1" endif sif (cpuis("STM32MP157*")) bitfld.long 0x0 13.--14. "HSDRVCHKZTRM,HSDRVCHKZTRM" "0,1,2,3" newline hexmask.long.byte 0x0 9.--12. 1. "HSDRVCHKITRM,HSDRVCHKITRM" bitfld.long 0x0 8. "HSDRVRFRED,HSDRVRFRED" "0,1" newline bitfld.long 0x0 7. "FSDRVRFADJ,FSDRVRFADJ" "0,1" bitfld.long 0x0 6. "HSDRVCURINCR,HSDRVCURINCR" "0,1" newline bitfld.long 0x0 5. "HSDRVDCLEV,HSDRVDCLEV" "0,1" bitfld.long 0x0 4. "HSDRVDCCUR,HSDRVDCCUR" "0,1" newline bitfld.long 0x0 3. "HSDRVSLEW,HSDRVSLEW" "0,1" bitfld.long 0x0 2. "LFSCAPEN,LFSCAPEN" "0,1" newline bitfld.long 0x0 1. "INCURRINT,INCURRINT" "0,1" bitfld.long 0x0 0. "INCURREN,INCURREN" "0,1" endif group.long 0xFFC++0x3 line.long 0x0 "USBPHYC_VERR,USBPHYC VERSION register" sif (cpuis("STM32MP13*")) hexmask.long.byte 0x0 4.--7. 1. "MAJREV,Major revision" hexmask.long.byte 0x0 0.--3. 1. "MINREV,Minor revision" newline endif sif (cpuis("STM32MP151*")) hexmask.long.byte 0x0 4.--7. 1. "MAJREV,MAJREV" hexmask.long.byte 0x0 0.--3. 1. "MINREV,MINREV" newline endif sif (cpuis("STM32MP153*")) hexmask.long.byte 0x0 4.--7. 1. "MAJREV,MAJREV" hexmask.long.byte 0x0 0.--3. 1. "MINREV,MINREV" newline endif sif (cpuis("STM32MP157*")) hexmask.long.byte 0x0 4.--7. 1. "MAJREV,MAJREV" hexmask.long.byte 0x0 0.--3. 1. "MINREV,MINREV" endif sif (cpuis("STM32MP151*")) rgroup.long 0xFFC++0x3 line.long 0x0 "USBPHYC_VERR,This register defines the version of this IP." endif sif (cpuis("STM32MP153*")) rgroup.long 0xFFC++0x3 line.long 0x0 "USBPHYC_VERR,This register defines the version of this IP." endif sif (cpuis("STM32MP157*")) rgroup.long 0xFFC++0x3 line.long 0x0 "USBPHYC_VERR,This register defines the version of this IP." endif tree.end tree "VREFBUF (Voltage Reference Buffer)" base ad:0x50025000 group.long 0x0++0x7 line.long 0x0 "VREFBUF_CSR,VREFBUF control and status register" bitfld.long 0x0 4.--6. "VRS,Voltage reference scale" "0: VREFBUF0 voltage selected,1: VREFBUF1 voltage selected,?,?,?,?,?,?" sif (cpuis("STM32MP13*")) rbitfld.long 0x0 3. "VRR,Voltage reference buffer ready" "0: the voltage reference buffer output is not ready.,1: the voltage reference buffer output reached the.." newline bitfld.long 0x0 1. "HIZ,High impedance mode" "0: VREF+ pin is internally connected to the voltage..,1: VREF+ pin is high impedance." bitfld.long 0x0 0. "ENVR,Voltage reference buffer mode enable" "0: Internal voltage reference mode disable..,1: Internal voltage reference mode (reference.." newline endif sif (cpuis("STM32MP151*")) rbitfld.long 0x0 3. "VRR,VRR" "0,1" endif sif (cpuis("STM32MP153*")) rbitfld.long 0x0 3. "VRR,VRR" "0,1" newline endif sif (cpuis("STM32MP157*")) rbitfld.long 0x0 3. "VRR,VRR" "0,1" endif sif (cpuis("STM32MP151*")) bitfld.long 0x0 1. "HIZ,HIZ" "0,1" newline endif sif (cpuis("STM32MP153*")) bitfld.long 0x0 1. "HIZ,HIZ" "0,1" bitfld.long 0x0 0. "ENVR,ENVR" "0,1" newline endif sif (cpuis("STM32MP157*")) bitfld.long 0x0 1. "HIZ,HIZ" "0,1" bitfld.long 0x0 0. "ENVR,ENVR" "0,1" endif line.long 0x4 "VREFBUF_CCR,VREFBUF calibration control register" hexmask.long.byte 0x4 0.--5. 1. "TRIM,Trimming code" tree.end sif (cpuis("STM32MP151*")||cpuis("STM32MP153*")||cpuis("STM32MP157*")) tree "WWDG (System Window Watchdog)" base ad:0x4000A000 group.long 0x0++0xB line.long 0x0 "WWDG_CR,Control register" bitfld.long 0x0 7. "WDGA,WDGA" "0,1" hexmask.long.byte 0x0 0.--6. 1. "T,T" line.long 0x4 "WWDG_CFR,Configuration register" bitfld.long 0x4 11.--13. "WDGTB,WDGTB" "0,1,2,3,4,5,6,7" bitfld.long 0x4 9. "EWI,EWI" "0,1" hexmask.long.byte 0x4 0.--6. 1. "W,W" line.long 0x8 "WWDG_SR,Status register" bitfld.long 0x8 0. "EWIF,EWIF" "0,1" rgroup.long 0x3F0++0xF line.long 0x0 "WWDG_HWCFGR,WWDG hardware configuration register" hexmask.long.word 0x0 0.--15. 1. "PREDIV,PREDIV" line.long 0x4 "WWDG_VERR,WWDG version register" hexmask.long.byte 0x4 4.--7. 1. "MAJREV,MAJREV" hexmask.long.byte 0x4 0.--3. 1. "MINREV,MINREV" line.long 0x8 "WWDG_IPIDR,WWDG ID register" hexmask.long 0x8 0.--31. 1. "ID,ID" line.long 0xC "WWDG_SIDR,WWDG size ID register" hexmask.long 0xC 0.--31. 1. "SID,SID" tree.end endif AUTOINDENT.OFF