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Customer/MOBIS/PRK3_(ADAS_Parking3)/Code/ARMStartup_CortexR52.c_txt.txt Normal file
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/**********************************************************************************************************************
* COPYRIGHT
* -------------------------------------------------------------------------------------------------------------------
* \verbatim
* Copyright (c) 2024 by Vector Informatik GmbH. All rights reserved.
*
* This software is copyright protected and proprietary to Vector Informatik GmbH.
* Vector Informatik GmbH grants to you only those rights as set out in the license conditions.
* All other rights remain with Vector Informatik GmbH.
* \endverbatim
* -------------------------------------------------------------------------------------------------------------------
* FILE DESCRIPTION
* -----------------------------------------------------------------------------------------------------------------*/
/** \file File: ARMStartup_CortexR52.c
* Project: Vector Basic Runtime System
* Module: BrsHw for all platforms with ARM core Cortex-R52
* Template: This file is reviewed according to Brs_Template@Implementation[1.03.09]
*
* \brief Description: This file contains the assembler part of the BRS StartUpCode.
*
* \attention Please note:
* The demo and example programs only show special aspects of the software. With regard to the fact
* that these programs are meant for demonstration purposes only, Vector Informatik liability shall be
* expressly excluded in cases of ordinary negligence, to the extent admissible by law or statute.
*********************************************************************************************************************/
/**********************************************************************************************************************
* REVISION HISTORY
* -------------------------------------------------------------------------------------------------------------------
* Refer to ARMBrsHw_CortexR52.h.
*********************************************************************************************************************/
/**********************************************************************************************************************
* EXAMPLE CODE ONLY
* -------------------------------------------------------------------------------------------------------------------
* This Example Code is only intended for illustrating an example of a possible BSW integration and BSW configuration.
* The Example Code has not passed any quality control measures and may be incomplete. The Example Code is neither
* intended nor qualified for use in series production. The Example Code as well as any of its modifications and/or
* implementations must be tested with diligent care and must comply with all quality requirements which are necessary
* according to the state of the art before their use.
*********************************************************************************************************************/
#define ARMSTARTUP_CORTEXR52_SOURCE
/**********************************************************************************************************************
* INCLUDES
*********************************************************************************************************************/
#include "BrsHw.h"
#if defined (BRS_FIRST_EXECUTION_INSTANCE)
/* This code is only needed for the first instance/executable in the system */
#include "vBrs_Lcfg.h"
#include "vLinkGen_Lcfg.h"
#include "ARMStartup_Platform.h"
#include "ARMStartup_CortexR52.h"
/**********************************************************************************************************************
* CONFIGURATION CHECK
*********************************************************************************************************************/
#if defined (BRS_COMP_ARM6)
#else
#error "Unknown compiler specified!"
#endif
#if (VLINKGEN_CFG_MAJOR_VERSION != 2u)
#error "This StartUpCode is dependent to the vLinkGen version! vLinkGen major version does not fit!"
#else
# if (VLINKGEN_CFG_MINOR_VERSION < 5u)
#error "This StartUpCode is dependent to the vLinkGen version! Your vLinkGen minor version is too old!"
# endif
#endif
/**********************************************************************************************************************
* DEFINITION + MACROS
*********************************************************************************************************************/
extern void intvect_CoreExceptions(void);
/**********************************************************************************************************************
* PROTOTYPES OF LOCAL FUNCTIONS
*********************************************************************************************************************/
BRS_LOCAL_PROTOTYPE(_start)
BRS_LOCAL_PROTOTYPE(brsStartupEntry)
BRS_LOCAL_PROTOTYPE(brsFirstCoreInit)
BRS_LOCAL_PROTOTYPE(brsStartupZeroInitLoop)
BRS_LOCAL_PROTOTYPE(brsStartupStackSearch)
BRS_LOCAL_PROTOTYPE(coreRegisterInit)
BRS_LOCAL_PROTOTYPE(coreRegisterInit2)
BRS_LOCAL_PROTOTYPE(coreRegisterInit3)
BRS_LOCAL_PROTOTYPE(stackPointerInit)
BRS_LOCAL_PROTOTYPE(brsInitialMPUconfig)
#if (BRS_ENABLE_HYPERVISOR_MODE_HANDLING == STD_ON)
/* =========================================================================== */
/* */
/* Description: Entry point for all cores in Hypervisor mode */
/* */
/* =========================================================================== */
# if (BRS_SET_T32_ENTRY_POINT == STD_ON)
BRS_THUMB_SECTION() /* Exception entry in T32 mode */
# endif
BRS_SECTION_CODE(brsStartupHyp)
BRS_GLOBAL(brsStartupEntryHyp)
BRS_MULTILINE_ASM_BEGIN()
BRS_LABEL(brsStartupEntryHyp)
/* Enhanced register initialization */
__as1(MOV r0, #0)
__as1(MOV r1, #0)
__as1(MOV r2, #0)
__as1(MOV r3, #0)
__as1(MOV r4, #0)
__as1(MOV r5, #0)
__as1(MOV r6, #0)
__as1(MOV r7, #0)
__as1(MOV r8, #0)
__as1(MOV r9, #0)
__as1(MOV r10, #0)
__as1(MOV r11, #0)
__as1(MOV r12, #0)
__as1(MOV lr, #0)
/* Switch to SVC mode with enhanced error checking */
__as1(MRS r0, CPSR) /* Read CPSR Register */
__as1(LDR r1, =MODE_SVC)
__as3(BFI r0, r1, #0, #5) /* Update CPSR Register */
# if (BRS_SET_T32_ENTRY_POINT == STD_ON)
__as2(ORR r0, r0, #(0x1 << 5)) /* Set T bit */
# endif
__as1(MSR SPSR_hyp, r0) /* Write SPSR Register */
/* Set initial vector table with proper barriers */
__as1(LDR r0, =CR_START_ADDRESS)
__as5(MCR p15, #0, r0, c12, c0, #0) /* Write to VBAR */
___asm(DSB) /* Ensure VBAR write completion */
___asm(ISB) /* Flush instruction pipeline */
/* =========================================================================== */
/* Enhanced MPU Configuration - Table 6.9 ROM Boot Memory Map Compliant */
/* Optimized for Exception Vector Table and Multi-core Systems */
/* =========================================================================== */
/* Step 1: Disable MPU with proper synchronization */
__as5(MRC p15, #0, r0, c1, c0, #0) /* Read SCTLR */
__as2(BIC r0, r0, #0x1) /* Clear MPU enable bit */
__as5(MCR p15, #0, r0, c1, c0, #0) /* Write SCTLR */
___asm(DSB)
___asm(ISB)
/* Step 2: Enhanced MAIR configuration for multi-core and ECC support */
/* MAIR0 - Memory Attribute Indirection Register 0 */
__as1(LDR r0, =0x00BB0444) /* MAIR0: Attr0=0x44, Attr1=0x04, Attr2=0xBB, Attr3=0x00 */
__as5(MCR p15, #0, r0, c10, c2, #0) /* Write MAIR0 */
/* MAIR1 - Extended attributes for specialized memory types */
__as1(LDR r0, =0x00000000) /* MAIR1: All attributes 0 */
__as5(MCR p15, #0, r0, c10, c2, #1) /* Write MAIR1 */
/* Critical: Memory barriers after MAIR configuration */
___asm(DSB)
___asm(ISB)
/* Step 3: MPU Region Configuration - Non-overlapping Design */
/* Region 0: Reserved for AUTOSAR OS Exception Vectors - Will be enabled by OS */
__as1(MOV r0, #0)
__as5(MCR p15, #0, r0, c6, c2, #1)
__as1(MOV r0, #0)
__as5(MCR p15, #0, r0, c6, c3, #0)
__as1(MOV r0, #0)
__as5(MCR p15, #0, r0, c6, c3, #1)
___asm(DSB)
___asm(ISB)
/* Region 1: Reserved for AUTOSAR OS - Disabled */
__as1(MOV r0, #1)
__as5(MCR p15, #0, r0, c6, c2, #1)
__as1(MOV r0, #0)
__as5(MCR p15, #0, r0, c6, c3, #0)
__as1(MOV r0, #0)
__as5(MCR p15, #0, r0, c6, c3, #1)
___asm(DSB)
___asm(ISB)
/* Region 2: Reserved for AUTOSAR OS - Disabled */
__as1(MOV r0, #2)
__as5(MCR p15, #0, r0, c6, c2, #1)
__as1(MOV r0, #0)
__as5(MCR p15, #0, r0, c6, c3, #0)
__as1(MOV r0, #0)
__as5(MCR p15, #0, r0, c6, c3, #1)
___asm(DSB)
___asm(ISB)
/* Region 3: Low Memory Range (0x00000000 - 0x3FFFFFFF) - 1GB */
__as1(MOV r0, #3)
__as5(MCR p15, #0, r0, c6, c2, #1)
__as1(LDR r0, =0x00000000)
__as2(ORR r0, r0, #0x03) /* XN=1, AP=00(RW), SH=00 (Non-shareable) */
__as5(MCR p15, #0, r0, c6, c3, #0)
__as1(LDR r0, =0x3FFFFFC0)
__as2(ORR r0, r0, #0x01) /* AttrIdx=0 (Non-cacheable), EN=1 */
__as5(MCR p15, #0, r0, c6, c3, #1)
___asm(DSB)
___asm(ISB)
/* Region 4: Complete CODE section (0x40100000 - 0x404FFFFF) - 4MB */
/* CRITICAL: Execute-Permitted, Read-Only for ALL, Inner-shareable for Vector AUTOSAR */
__as1(MOV r0, #4)
__as5(MCR p15, #0, r0, c6, c2, #1)
__as1(LDR r0, =0x40100000) /* Base includes Exception Vector Tables */
__as2(ORR r0, r0, #0x02) /* XN=0(Execute-never), AP=0b01(Read/write, at any privilege level), SH=0b10 (Outer-shareable) */
__as5(MCR p15, #0, r0, c6, c3, #0)
__as1(LDR r0, =0x404FFFC0) /* Covers all code sections and exception vectors */
__as2(ORR r0, r0, #0x05) /* AttrIdx=2 (Normal WT), EN=1 */
__as5(MCR p15, #0, r0, c6, c3, #1)
___asm(DSB)
___asm(ISB)
/* Region 5: Device Memory (0xC0000000 - 0xDFFFFFFF) - 512MB */
/* FIXED: Device memory should be Outer-shareable for proper hardware access */
__as1(MOV r0, #5)
__as5(MCR p15, #0, r0, c6, c2, #1)
__as1(LDR r0, =0xC0000000)
__as2(ORR r0, r0, #0x02) /* XN=0, AP=01(RW), SH=00 */
__as5(MCR p15, #0, r0, c6, c3, #0)
__as1(LDR r0, =0xDFFFFFC0)
__as2(ORR r0, r0, #0x03) /* AttrIdx=1(Device-nGnRnE), EN=1 */
__as5(MCR p15, #0, r0, c6, c3, #1)
___asm(DSB)
___asm(ISB)
/* Region 6: Normal Memory (0xE0000000 - 0xE3FFFFFF) - 64MB */
/* FIXED: Inner-shareable for multi-core data consistency */
__as1(MOV r0, #6)
__as5(MCR p15, #0, r0, c6, c2, #1)
__as1(LDR r0, =0xE0000000)
__as2(ORR r0, r0, #0x02) /* XN=0, AP=01(RW), SH=00 */
__as5(MCR p15, #0, r0, c6, c3, #0)
__as1(LDR r0, =0xE3FFFFC0)
__as2(ORR r0, r0, #0x01) /* AttrIdx=0(Non-cacheable), EN=1 */
__as5(MCR p15, #0, r0, c6, c3, #1)
___asm(DSB)
___asm(ISB)
/* Region 7: Realtime Core TCM Memory (0xE4000000 - 0xE4BFFFFF) - 12MB */
__as1(MOV r0, #7)
__as5(MCR p15, #0, r0, c6, c2, #1) /* Select region 7 */
__as1(LDR r0, =0xE4000000) /* Base = 0xE4000000 */
__as2(ORR r0, r0, #0x02) /* XN=0, AP=01(RW), SH=00 (Non-shareable) */
__as5(MCR p15, #0, r0, c6, c3, #0) /* Set base/attr */
__as1(LDR r0, =0xE4BFFFC0) /* Limit = 0xE4BFFFFF */
__as2(ORR r0, r0, #0x01) /* AttrIdx=0(Non-cacheable), EN=1 */
__as5(MCR p15, #0, r0, c6, c3, #1) /* Set limit/enable */
___asm(DSB)
___asm(ISB)
/* Region 8: Device Memory (0xE5000000 - 0xE62FFFFF) - ~19MB */
/* FIXED: Device memory with Outer-shareable */
__as1(MOV r0, #8)
__as5(MCR p15, #0, r0, c6, c2, #1)
__as1(LDR r0, =0xE5000000)
__as2(ORR r0, r0, #0x02) /* XN=1, AP=00(RW), SH=00 */
__as5(MCR p15, #0, r0, c6, c3, #0)
__as1(LDR r0, =0xE62FFFC0)
__as2(ORR r0, r0, #0x03) /* AttrIdx=1(Device-nGnRnE), EN=1 */
__as5(MCR p15, #0, r0, c6, c3, #1)
___asm(DSB)
___asm(ISB)
/* Region 9: V4H SystemRAM (0xE6300000 - 0xE63FFFFF) - 1MB */
/* FIXED: Corrected AP and shareable settings for multi-core shared memory */
__as1(MOV r0, #9)
__as5(MCR p15, #0, r0, c6, c2, #1)
__as1(LDR r0, =0xE6300000)
__as2(ORR r0, r0, #0x03) /* XN=1(Execute-always), AP=0b01(Read/write, at any privilege level), SH=0b10 (Outer-shareable) */
__as5(MCR p15, #0, r0, c6, c3, #0)
__as1(LDR r0, =0xE63FFFC0)
__as2(ORR r0, r0, #0x01) /* AttrIdx=0(Non-cacheable), EN=1 */
__as5(MCR p15, #0, r0, c6, c3, #1)
___asm(DSB)
___asm(ISB)
/* Region 10: Device Memory (0xE6400000 - 0xEB0FFFFF) - ~76MB */
/* FIXED: Device memory with Non-shareable (recommended for device registers) */
__as1(MOV r0, #10)
__as5(MCR p15, #0, r0, c6, c2, #1)
__as1(LDR r0, =0xE6400000)
__as2(ORR r0, r0, #0x03) /* XN=1, AP=00(RW), SH=00 (Non-shareable) - FIXED */
__as5(MCR p15, #0, r0, c6, c3, #0)
__as1(LDR r0, =0xEB0FFFC0)
__as2(ORR r0, r0, #0x03) /* AttrIdx=1(Device-nGnRnE), EN=1 */
__as5(MCR p15, #0, r0, c6, c3, #1)
___asm(DSB)
___asm(ISB)
/* Region 11: Normal Memory (0xEB100000 - 0xEB127FFF) - 160KB */
__as1(MOV r0, #11)
__as5(MCR p15, #0, r0, c6, c2, #1)
__as1(LDR r0, =0xEB100000)
__as2(ORR r0, r0, #0x02) /* XN=0, AP=00(RW), SH=00 */
__as5(MCR p15, #0, r0, c6, c3, #0)
__as1(LDR r0, =0xEB127FC0)
__as2(ORR r0, r0, #0x01) /* AttrIdx=0(Non-cacheable), EN=1 */
__as5(MCR p15, #0, r0, c6, c3, #1)
___asm(DSB)
___asm(ISB)
/* Region 12: Device Memory (0xEB128000 - 0xEB1FFFFF) - ~864KB */
/* FIXED: Device memory with Outer-shareable */
__as1(MOV r0, #12)
__as5(MCR p15, #0, r0, c6, c2, #1)
__as1(LDR r0, =0xEB128000)
__as2(ORR r0, r0, #0x03) /* XN=1, AP=00(RW), SH=00 */
__as5(MCR p15, #0, r0, c6, c3, #0)
__as1(LDR r0, =0xEB1FFFC0)
__as2(ORR r0, r0, #0x03) /* AttrIdx=1(Device-nGnRnE), EN=1 */
__as5(MCR p15, #0, r0, c6, c3, #1)
___asm(DSB)
___asm(ISB)
/* Region 13: Normal Memory (0xEB200000 - 0xEB2FFFFF) - 1MB */
/* FIXED: Inner-shareable for multi-core consistency */
__as1(MOV r0, #13)
__as5(MCR p15, #0, r0, c6, c2, #1)
__as1(LDR r0, =0xEB200000)
__as2(ORR r0, r0, #0x02) /* XN=0, AP=00(RW), SH=00 */
__as5(MCR p15, #0, r0, c6, c3, #0)
__as1(LDR r0, =0xEB2FFFC0)
__as2(ORR r0, r0, #0x05) /* AttrIdx=2(Normal WT), EN=1 */
__as5(MCR p15, #0, r0, c6, c3, #1)
___asm(DSB)
___asm(ISB)
/* Region 14: Device Memory (0xEB300000 - 0xFFFFFFFF) - ~320MB */
/* FIXED: Device memory with Outer-shareable */
__as1(MOV r0, #14)
__as5(MCR p15, #0, r0, c6, c2, #1)
__as1(LDR r0, =0xEB300000)
__as2(ORR r0, r0, #0x03) /* XN=1, AP=00(RW), SH=00 */
__as5(MCR p15, #0, r0, c6, c3, #0)
__as1(LDR r0, =0xFFFFFFC0)
__as2(ORR r0, r0, #0x03) /* AttrIdx=1(Device-nGnRnE), EN=1 */
__as5(MCR p15, #0, r0, c6, c3, #1)
___asm(DSB)
___asm(ISB)
/* Region 15: DATA section (0x40500000 - 0x405FFFFF) - 1MB */
/* FIXED: Read-Write for all modes, Execute-Never, Inner-shareable */
__as1(MOV r0, #15)
__as5(MCR p15, #0, r0, c6, c2, #1)
__as1(LDR r0, =0x40500000)
__as2(ORR r0, r0, #0x02) /* XN=0(Execute-never), AP=0b01(Read/write, at any privilege level), SH=0b10 (Outer-shareable) */
__as5(MCR p15, #0, r0, c6, c3, #0)
__as1(LDR r0, =0x405FFFC0)
__as2(ORR r0, r0, #0x05) /* AttrIdx=2(Normal WT), EN=1 */
__as5(MCR p15, #0, r0, c6, c3, #1)
___asm(DSB)
___asm(ISB)
/* Region 16: FINAL FIX - Vector AUTOSAR System Mode compatible */
__as1(MOV r0, #16)
__as5(MCR p15, #0, r0, c6, c2, #1)
__as1(LDR r0, =0x40700000)
__as2(ORR r0, r0, #0x02) /* XN=0(Execute-never), AP=0b01(Read/write, at any privilege level), SH=0b10 (Outer-shareable) */
__as5(MCR p15, #0, r0, c6, c3, #0)
__as1(LDR r0, =0x409FFFC0)
__as2(ORR r0, r0, #0x05) /* AttrIdx=2(Normal WT), EN=1 */
__as5(MCR p15, #0, r0, c6, c3, #1)
___asm(DSB)
___asm(ISB)
/* Region 17: Extended memory (0x80000000 - 0xBFFFFFFF) - 1GB */
/* FIXED: Read-Write for all modes, Execute-Permitted, Inner-shareable */
__as1(MOV r0, #17)
__as5(MCR p15, #0, r0, c6, c2, #1)
__as1(LDR r0, =0x80000000)
__as2(ORR r0, r0, #0x02) /* XN=0, AP=00, SH=00 */
__as5(MCR p15, #0, r0, c6, c3, #0)
__as1(LDR r0, =0xBFFFFFC0)
__as2(ORR r0, r0, #0x05) /* AttrIdx=2(Normal WT), EN=1 */
__as5(MCR p15, #0, r0, c6, c3, #1)
___asm(DSB)
___asm(ISB)
/* Region 18: Unused - Disabled */
__as1(MOV r0, #18) /* Region ID = 18 */
__as5(MCR p15, #0, r0, c6, c2, #1) /* Select region 18 */
__as1(MOV r0, #0) /* Base address = 0 */
__as5(MCR p15, #0, r0, c6, c3, #0) /* Write PRBAR */
__as1(MOV r0, #0) /* Limit address = 0, Enable=0 (Disabled) */
__as5(MCR p15, #0, r0, c6, c3, #1) /* Write PRLAR (EN=0, region disabled) */
___asm(DSB)
___asm(ISB)
/* Region 19: Unused - Disabled */
__as1(MOV r0, #19) /* Region ID = 19 */
__as5(MCR p15, #0, r0, c6, c2, #1) /* Select region 19 */
__as1(MOV r0, #0) /* Base address = 0 */
__as5(MCR p15, #0, r0, c6, c3, #0) /* Write PRBAR */
__as1(MOV r0, #0) /* Limit address = 0, Enable=0 (Disabled) */
__as5(MCR p15, #0, r0, c6, c3, #1) /* Write PRLAR (EN=0, region disabled) */
___asm(DSB)
___asm(ISB)
/* Region 20: Unused - Disabled */
__as1(MOV r0, #20) /* Region ID = 20 */
__as5(MCR p15, #0, r0, c6, c2, #1) /* Select region 20 */
__as1(MOV r0, #0) /* Base address = 0 */
__as5(MCR p15, #0, r0, c6, c3, #0) /* Write PRBAR */
__as1(MOV r0, #0) /* Limit address = 0, Enable=0 (Disabled) */
__as5(MCR p15, #0, r0, c6, c3, #1) /* Write PRLAR (EN=0, region disabled) */
___asm(DSB)
___asm(ISB)
/* Region 21: Unused - Disabled */
__as1(MOV r0, #21) /* Region ID = 21 */
__as5(MCR p15, #0, r0, c6, c2, #1) /* Select region 21 */
__as1(MOV r0, #0) /* Base address = 0 */
__as5(MCR p15, #0, r0, c6, c3, #0) /* Write PRBAR */
__as1(MOV r0, #0) /* Limit address = 0, Enable=0 (Disabled) */
__as5(MCR p15, #0, r0, c6, c3, #1) /* Write PRLAR (EN=0, region disabled) */
___asm(DSB)
___asm(ISB)
/* Region 22: Unused - Disabled */
__as1(MOV r0, #22) /* Region ID = 22 */
__as5(MCR p15, #0, r0, c6, c2, #1) /* Select region 22 */
__as1(MOV r0, #0) /* Base address = 0 */
__as5(MCR p15, #0, r0, c6, c3, #0) /* Write PRBAR */
__as1(MOV r0, #0) /* Limit address = 0, Enable=0 (Disabled) */
__as5(MCR p15, #0, r0, c6, c3, #1) /* Write PRLAR (EN=0, region disabled) */
___asm(DSB)
___asm(ISB)
/* Region 23: Unused - Disabled */
__as1(MOV r0, #23) /* Region ID = 23 */
__as5(MCR p15, #0, r0, c6, c2, #1) /* Select region 23 */
__as1(MOV r0, #0) /* Base address = 0 */
__as5(MCR p15, #0, r0, c6, c3, #0) /* Write PRBAR */
__as1(MOV r0, #0) /* Limit address = 0, Enable=0 (Disabled) */
__as5(MCR p15, #0, r0, c6, c3, #1) /* Write PRLAR (EN=0, region disabled) */
___asm(DSB)
___asm(ISB)
BRS_READ_COREID(R1)
__as1(MOV r3, #0) /* Default value */
__as1(CMP r1, #0)
__as1(LDREQ r3, =CR0_ATCM_BASE) /* Core 0 */
__as1(CMP r1, #1)
__as1(LDREQ r3, =CR1_ATCM_BASE) /* Core 1 */
__as1(CMP r1, #2)
__as1(LDREQ r3, =CR2_ATCM_BASE) /* Core 2 */
__as1(MOV r4, #3) /* 0x3: Full access (Privileged + User) */
__as5(MCR p15, #0, r4, c11, c0, #0) /* Write to IMP_SLAVEPCTLR */
___asm(DSB)
___asm(ISB)
__as1(MOV r4, #0)
__as1(LDR r5, =0xFFFFE000)
__as2(AND r6, r3, r5)
__as2(ORR r4, r4, r6)
__as2(ORR r4, r4, #0x18) /* SIZE=6 (0b00110 << 2 = 0x18) */
__as2(ORR r4, r4, #3) /* Enable ATCM access from EL2, EL1, and EL0 */
__as5(MCR p15, #0, r4, c9, c1, #0) /* Write to CP15 ATCM Region Register */
___asm(DSB)
___asm(ISB)
/* Step 5: Enable L1 caches with proper sequencing */
__as5(MRC p15, #0, r0, c1, c0, #0)
__as2(ORR r0, r0, #(0x1 << 2)) /* Set C bit (D-cache enable) */
__as2(ORR r0, r0, #(0x1 << 12)) /* Set I bit (I-cache enable) */
__as5(MCR p15, #0, r0, c1, c0, #0)
___asm(DSB)
___asm(ISB)
/* Step 6: Enable MPU background region */
__as5(MRC p15, #0, r0, c1, c0, #0) /* Read SCTLR */
__as2(ORR r0, r0, #(0x1 << 17)) /* Set background region enable bit */
__as5(MCR p15, #0, r0, c1, c0, #0) /* Write SCTLR */
___asm(DSB)
___asm(ISB)
/* Step 7: Enable MPU */
__as5(MRC p15, #0, r0, c1, c0, #0) /* Read SCTLR */
__as2(ORR r0, r0, #0x1) /* Set MPU enable bit */
__as5(MCR p15, #0, r0, c1, c0, #0) /* Write SCTLR */
___asm(DSB)
___asm(ISB)
/* Step 8: Configure Generic Timer */
/* Enable Generic Timer access for EL1 and EL0 */
__as5(MRC p15, #4, r0, c14, c1, #0) /* Read CNTHCTL */
__as2(ORR r0, r0, #0x3) /* EL1PCTEN | EL1PCEN */
__as5(MCR p15, #4, r0, c14, c1, #0) /* Write CNTHCTL */
/* Set Generic Timer frequency for R-Car */
__as1(LDR r0, =0xFE4FE8) /* R-Car timer frequency: 16,658,408 Hz */
__as5(MCR p15, #0, r0, c14, c0, #0) /* Write CNTFRQ */
__as1(MOV lr, r10) /* Restore return address */
/* Memory barriers to ensure MPU configuration takes effect */
___asm(DSB)
___asm(ISB)
__as1(LDR r0, =EL1_VectorTable) /* Load entry label */
__as1(MSR ELR_hyp, r0) /* Set the link register */
___asm(DSB)
___asm(ISB)
___asm(ERET) /* Trigger EL1 level */
# if defined (BRS_COMP_ARM6)
___asm(.align 4)
# else
___asm(.align 0x20)
# endif
BRS_GLOBAL(EL1_VectorTable)
BRS_LABEL(EL1_VectorTable) /* Temporary Interrupt Vector Table */
__as1(LDR PC, EL1_Reset_Addr)
__as1(LDR PC, EL1_Unhandled_Addr)
__as1(LDR PC, EL1_Unhandled_Addr)
__as1(LDR PC, EL1_Unhandled_Addr)
__as1(LDR PC, EL1_Unhandled_Addr)
__as1(LDR PC, EL1_Unhandled_Addr)
__as1(LDR PC, EL1_Unhandled_Addr)
__as1(LDR PC, EL1_Unhandled_Addr)
___asm(EL1_Reset_Addr: .word brsStartupEntry)
___asm(EL1_Unhandled_Addr: .word EL1_Unhandled_Handler)
BRS_LABEL(EL1_Unhandled_Handler)
___asm(B EL1_Unhandled_Handler)
BRS_MULTILINE_ASM_END()
BRS_GLOBAL_END()
#endif /*BRS_ENABLE_HYPERVISOR_MODE_HANDLING*/
/* =========================================================================== */
/* */
/* Description: Entry point for all cores in EL1 mode */
/* */
/* =========================================================================== */
/* Alternativ entry point from OS default config */
BRS_GLOBAL(_start)
BRS_MULTILINE_ASM_BEGIN()
BRS_LABEL(_start)
BRS_MULTILINE_ASM_END()
BRS_GLOBAL_END()
#if (BRS_SET_T32_ENTRY_POINT == STD_ON)
BRS_THUMB_SECTION() /* Exception entry in T32 mode */
#endif
BRS_SECTION_CODE(brsStartup)
BRS_GLOBAL(brsStartupEntry)
BRS_MULTILINE_ASM_BEGIN()
BRS_LABEL(brsStartupEntry)
#if ((BRS_CPU_CORE_AMOUNT>1) && defined (BRSHW_CORE_START_PATTERN))
BRS_READ_COREID(R0)
BRS_BRANCH_EQUAL(R0,#BRSHW_INIT_CORE_ID,EL1_Startup_Entry)
__as1(LDR R6, =BRSHW_CORE_START_PATTERN)
__as1(LDR R7, =BrsHw_CoreStart)
__as1(MOV R8, R0)
__as2(LSL R8, R8, #2)
__as2(ADD R7, R7, R8)
BRS_LABEL(coreWaitLoop)
__as1(LDR R8, [R7]) /* Load sync variable */
BRS_BRANCH_NOT_EQUAL(R6,R8,coreWaitLoop) /* If sync pattern is not present, loop again */
BRS_BRANCH_NOT_EQUAL(R0,#BRSHW_INIT_CORE_ID,clearStartPattern)
BRS_LABEL(clearStartPattern)
__as1(MOV R8, #0)
__as1(STR R8, [R7]) /* Clear sync pattern */
BRS_LABEL(EL1_Startup_Entry)
#endif /*BRS_CPU_CORE_AMOUNT>1&&BRSHW_CORE_START_PATTERN*/
#if defined (BRSHW_PRE_ASM_STARTUP_HOOK_AVAILABLE)
/* =========================================================================== */
/* */
/* Description: Optional hook for platform specific tasks */
/* */
/* =========================================================================== */
# if defined (BRS_COMP_ARM6)
BRS_BRANCH(brsPreAsmStartupHook)
# endif
#endif
BRS_GLOBAL(brsFirstCoreInit)
BRS_MULTILINE_ASM_BEGIN()
BRS_LABEL(brsFirstCoreInit)
BRS_BRANCH(brsInitialMPUconfig)
BRS_MULTILINE_ASM_END()
BRS_GLOBAL_END()
/* =========================================================================== */
/* */
/* Description: Initial configuration of MPU regions */
/* */
/* =========================================================================== */
BRS_GLOBAL(brsInitialMPUconfig)
BRS_MULTILINE_ASM_BEGIN()
BRS_LABEL(brsInitialMPUconfig)
BRS_BRANCH(coreRegisterInit)
BRS_MULTILINE_ASM_END()
BRS_GLOBAL_END()
/* =========================================================================== */
/* */
/* Description: Initialize core ID independent core registers */
/* */
/* =========================================================================== */
BRS_GLOBAL(coreRegisterInit)
BRS_MULTILINE_ASM_BEGIN()
BRS_LABEL(coreRegisterInit)
BRS_BRANCH(coreRegisterInit2)
BRS_MULTILINE_ASM_END()
BRS_GLOBAL_END()
/* =========================================================================== */
/* */
/* Description: Initialize all core ID dependent core registers */
/* Setup VBAR to program entry address */
/* */
/* =========================================================================== */
BRS_GLOBAL(coreRegisterInit2)
BRS_MULTILINE_ASM_BEGIN()
BRS_LABEL(coreRegisterInit2)
/* Initialize stack for SVC */
//ldr r0, .svc_stack
//mov sp, r0
/* Set EL1 Vectors */
__as1(LDR R2, =EL1_VectorTable)
__as5(MCR p15, #0, r2, c12, c0, #0)
/* Disable forwarding interrupt */
__as1(MOV r0, #0)
__as5(MRC p15, #0, r0, c12, c12, #7)
BRS_BRANCH(brsStartupZeroInitLoop)
BRS_MULTILINE_ASM_END()
BRS_GLOBAL_END()
/* =========================================================================== */
/* */
/* Description: Initialize memory blocks and groups with zero */
/* */
/* =========================================================================== */
BRS_GLOBAL(brsStartupZeroInitLoop)
BRS_MULTILINE_ASM_BEGIN()
BRS_LABEL(brsStartupZeroInitLoop)
BRS_READ_COREID(R0)
/* Initialize memory sections blocks with zeros */
#if defined (VLINKGEN_CFG_NUM_ZERO_INIT_EARLY_BLOCKS)
# if (VLINKGEN_CFG_NUM_ZERO_INIT_EARLY_BLOCKS>1uL)
__as1(LDR R1, =vLinkGen_ZeroInit_Early_Blocks)
BRS_LABEL(startup_block_zero_init_start)
__as1(MOV R2, R1)
__as2(ADD R1, R1, #16)
__as1(LDR R3, [R2]) /* vLinkGen_ZeroInit_Early_Blocks->start */
__as2(LDR R4, [R2, #4]) /* vLinkGen_ZeroInit_Early_Blocks->end */
__as2(LDR R5, [R2, #8]) /* vLinkGen_ZeroInit_Early_Blocks->core */
__as2(LDR R6, [R2, #12]) /* vLinkGen_ZeroInit_Early_Blocks->alignment */
/* Verify if the end of struct vLinkGen_ZeroInit_Early_Blocks is reached, by checking if start == 0, end == 0 and core == 0 */
__as1(MOV R7, #0)
__as2(ORR R7, R7, R3) /* Or with vLinkGen_ZeroInit_Early_Blocks->start */
__as2(ORR R7, R7, R4) /* Or with vLinkGen_ZeroInit_Early_Blocks->end */
__as2(ORR R7, R7, R5) /* Or with vLinkGen_ZeroInit_Early_Blocks->core */
BRS_BRANCH_EQUAL(R7, #0, startup_block_zero_init_end) /* If start address, end address and core are equal to zero -> Finished */
BRS_BRANCH_NOT_EQUAL(R0, R5, startup_block_zero_init_start) /* If InitCore is not running -> go to the next array entry */
__as1(MOV R7, #0) /* set R7 to '0', as value to write in memory later */
__as1(MOV R8, #0) /* set R8 to '0', as value to write in memory later */
BRS_BRANCH_EQUAL(R6, #8, startup_block_zero_init_8byte_loop_start) /* if block is 8-Byte aligned, use specific init loop */
BRS_LABEL(startup_block_zero_init_loop_start)
BRS_BRANCH_GREATER_THAN_OR_EQUAL(R3, R4, startup_block_zero_init_start) /* if start address is same with or higher than end address-> Finished. */
__as1(STR R7, [R3]) /* write value of R7 ('0') to address of R3 (4-byte access); must be an aligned memory access! */
__as2(ADD R3, R3, #4) /* increase address value of R3 by '4' */
/* End address of this block was not yet reached. Run through the loop again */
BRS_BRANCH(startup_block_zero_init_loop_start)
/* ================================================================ */
/* 8-Byte aligned initialization, to support 8-Byte aligned ECC RAM */
/* ================================================================ */
BRS_LABEL(startup_block_zero_init_8byte_loop_start)
BRS_BRANCH_GREATER_THAN_OR_EQUAL(R3, R4, startup_block_zero_init_start) /* if start address is same with or higher than end address-> Finished. */
/* Address stored in R3 must be 8 Byte aligned at this point! */
__as2(STMIA R3!, {R7, R8}) /* 8 Byte alignment store for ECC, R3 would be automatically updated after the write */
/* End address of this block was not yet reached. Run through the loop again */
BRS_BRANCH(startup_block_zero_init_8byte_loop_start)
/* Zero-Init loop of blocks end label */
BRS_LABEL(startup_block_zero_init_end)
# endif /*VLINKGEN_CFG_NUM_ZERO_INIT_EARLY_BLOCKS>1uL*/
#else
#error "Mandatory define VLINKGEN_CFG_NUM_ZERO_INIT_EARLY_BLOCKS missing within vLinkGen configuration!"
#endif /*VLINKGEN_CFG_NUM_ZERO_INIT_EARLY_BLOCKS*/
/* Initialize memory sections groups with zeros */
#if defined (VLINKGEN_CFG_NUM_ZERO_INIT_EARLY_GROUPS)
# if (VLINKGEN_CFG_NUM_ZERO_INIT_EARLY_GROUPS>1uL)
__as1(LDR R1, =vLinkGen_ZeroInit_Early_Groups)
BRS_LABEL(startup_group_zero_init_start)
__as1(MOV R2, R1)
__as2(ADD R1, R1, #16)
__as1(LDR R3, [R2]) /* vLinkGen_ZeroInit_Early_Groups->start */
__as2(LDR R4, [R2, #4]) /* vLinkGen_ZeroInit_Early_Groups->end */
__as2(LDR R5, [R2, #8]) /* vLinkGen_ZeroInit_Early_Groups->core */
__as2(LDR R6, [R2, #12]) /* vLinkGen_ZeroInit_Early_Groups->alignment */
/* Verify if the end of struct vLinkGen_ZeroInit_Early_Groups is reached, by checking if start == 0, end == 0 and core == 0 */
__as1(MOV R7, #0)
__as2(ORR R7, R7, R3) /* Or with vLinkGen_ZeroInit_Early_Groups->start */
__as2(ORR R7, R7, R4) /* Or with vLinkGen_ZeroInit_Early_Groups->end */
__as2(ORR R7, R7, R5) /* Or with vLinkGen_ZeroInit_Early_Groups->core */
BRS_BRANCH_EQUAL(R7, #0, startup_group_zero_init_end) /* If start address, end address and core are equal to zero -> Finished */
BRS_BRANCH_NOT_EQUAL(R0, R5, startup_group_zero_init_start) /* If InitCore is not running -> go to the next array entry */
__as1(MOV R7, #0) /* set R7 to '0', as value to write in memory later */
__as1(MOV R8, #0) /* set R8 to '0', as value to write in memory later */
BRS_BRANCH_EQUAL(R6, #8, startup_group_zero_init_8byte_loop_start) /* if group is 8-Byte aligned, use specific init loop */
BRS_LABEL(startup_group_zero_init_loop_start)
BRS_BRANCH_GREATER_THAN_OR_EQUAL(R3, R4, startup_group_zero_init_start) /* if start address is same with or higher than end address-> Finished. */
__as1(STR R7, [R3]) /* write value of R7 ('0') to address of R3 (4-byte access); must be an aligned memory access! */
__as2(ADD R3, R3, #4) /* increase address value of R3 by '4' */
/* End address of this group was not yet reached. Run through the loop again */
BRS_BRANCH(startup_group_zero_init_loop_start)
/* ================================================================ */
/* 8-Byte aligned initialization, to support 8-Byte aligned ECC RAM */
/* ================================================================ */
BRS_LABEL(startup_group_zero_init_8byte_loop_start)
BRS_BRANCH_GREATER_THAN_OR_EQUAL(R3, R4, startup_group_zero_init_start) /* if start address is same with or higher than end address-> Finished. */
/* Address stored in R3 must be 8 Byte aligned at this point! */
__as2(STMIA R3!, {R7, R8}) /* 8 Byte alignment store for ECC, R3 would be automatically updated after the write */
/* End address of this group was not yet reached. Run through the loop again */
BRS_BRANCH(startup_group_zero_init_8byte_loop_start)
/* Zero-Init loop of groups end label */
BRS_LABEL(startup_group_zero_init_end)
# endif /*VLINKGEN_CFG_NUM_ZERO_INIT_EARLY_GROUPS>1uL*/
#else
#error "Mandatory define VLINKGEN_CFG_NUM_ZERO_INIT_EARLY_GROUPS missing within vLinkGen configuration!"
#endif /*VLINKGEN_CFG_NUM_ZERO_INIT_EARLY_GROUPS*/
/* Jump to routine to search for valid startup stack pointer of actual running core */
BRS_BRANCH(brsStartupStackSearch)
BRS_MULTILINE_ASM_END()
BRS_GLOBAL_END()
/* =========================================================================== */
/* */
/* Description: Search for valid startup stack pointer of actual running core */
/* (vBRS is genearing the core specific configuration into the */
/* struct BrsMain_CoreConfig in vBrs_Lcfg.c) */
/* */
/* =========================================================================== */
BRS_GLOBAL(brsStartupStackSearch)
BRS_MULTILINE_ASM_BEGIN()
BRS_LABEL(brsStartupStackSearch)
__as1(LDR R1, =BrsMain_CoreConfig_Size)
BRS_LABEL(core_config_size_init)
__as1(LDR R5, [R1]) /* R5 = BrsMain_CoreConfig_Size */
BRS_READ_COREID(R0)
__as1(LDR R1, =BrsMain_CoreConfig)
BRS_LABEL(core_config_init_start)
/* Use R2 as count register in the loop. Initialize with zero. */
#if defined (BRS_COMP_ARM6)
__as1(MOV R2, 0)
#else
__as1(MOV R2, #0)
#endif
BRS_LABEL(brs_coreconfig_loop)
__as2(LDR R4, [R1,#4]) /* BrsMain_CoreConfig->PhysicalCoreId */
/* Check if core id (R0) matches to physical core id of BrsMain_CoreConfig entry (R4). */
BRS_BRANCH_EQUAL(R0, R4, stackPointerInit)
/* Increase count register by one. */
#if defined (BRS_COMP_ARM6)
__as2(ADD R2, R2, 1)
#else
__as2(ADD R2, R2, #1)
#endif
/* Set R1 to point to next entry of BrsMain_CoreConfig. */
#if defined (BRS_COMP_ARM6)
__as2(ADD R1, R1, 28)
#else
__as2(ADD R1, R1, #28)
#endif
/* Check if end of BrsMain_CoreConfig has been reached. */
BRS_BRANCH_NOT_EQUAL(R2, R5, brs_coreconfig_loop)
BRS_MULTILINE_ASM_END()
/* Branch to BrsMainExceptionStartup if there are no more entries in the array. */
BRS_EXTERN_BRANCH(BrsMainExceptionStartup)
BRS_GLOBAL_END()
/* =========================================================================== */
/* */
/* Description: Initialize all core registers of actual running core with */
/* specific init values */
/* */
/* =========================================================================== */
BRS_GLOBAL(stackPointerInit)
BRS_MULTILINE_ASM_BEGIN()
BRS_LABEL(stackPointerInit)
__as2(LDR R0, [R1,#8]) /* BrsMain_CoreConfig->StartupStackEndLabel */
/* Initialize stack pointers for different modes */
___asm(CPS #MODE_ABT)
__as1(MOV SP, r0)
___asm(CPS #MODE_IRQ)
__as2(SUB r0, r0, #MODE_STACK_SIZE)
__as1(MOV SP, r0)
___asm(CPS #MODE_FIQ)
__as2(SUB r0, r0, #MODE_STACK_SIZE)
__as1(MOV SP, r0)
___asm(CPS #MODE_UNDEF)
__as2(SUB r0, r0, #MODE_STACK_SIZE)
__as1(MOV SP, r0)
___asm(CPS #MODE_SVC)
__as2(SUB r0, r0, #MODE_STACK_SIZE)
__as1(MOV SP, r0)
___asm(CPS #MODE_SYS)
__as2(SUB r0, r0, #MODE_STACK_SIZE)
__as1(MOV SP, r0)
BRS_BRANCH(coreRegisterInit3)
BRS_MULTILINE_ASM_END()
BRS_GLOBAL_END()
/* =========================================================================== */
/* */
/* Description: Initialize additional core registers */
/* */
/* =========================================================================== */
BRS_GLOBAL(coreRegisterInit3)
BRS_MULTILINE_ASM_BEGIN()
BRS_LABEL(coreRegisterInit3)
BRS_MULTILINE_ASM_END()
/* =========================================================================== */
/* */
/* Description: Jump to Brs_PreMainStartup() (BrsMainStartup.c) */
/* */
/* =========================================================================== */
BRS_EXTERN_BRANCH(Brs_PreMainStartup)
/* =========================================================================== */
/* */
/* Description: Jump to BrsMainExceptionStartup() in case of an unexpected */
/* return from PreMain/main */
/* */
/* =========================================================================== */
BRS_EXTERN_BRANCH(BrsMainExceptionStartup)
BRS_GLOBAL_END()
#endif /*BRS_FIRST_EXECUTION_INSTANCE*/

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/**********************************************************************************************************************
* COPYRIGHT
* -------------------------------------------------------------------------------------------------------------------
* \verbatim
* Copyright (c) 2024 by Vector Informatik GmbH. All rights reserved.
*
* This software is copyright protected and proprietary to Vector Informatik GmbH.
* Vector Informatik GmbH grants to you only those rights as set out in the license conditions.
* All other rights remain with Vector Informatik GmbH.
* \endverbatim
* -------------------------------------------------------------------------------------------------------------------
* FILE DESCRIPTION
* -----------------------------------------------------------------------------------------------------------------*/
/** \file File: ARMBrsHw_CortexR52.h
* Project: Vector Basic Runtime System
* Module: BrsHw for all platforms with ARM core Cortex-R52
*
* \brief Description: This is a global, platform-independent header file for the ARM-BRS.
* This file includes all non-platform dependent functions.
* All the (platform depending) rest needs to be defined in BrsHw.c
*
* \attention Please note:
* The demo and example programs only show special aspects of the software. With regard to the fact
* that these programs are meant for demonstration purposes only, Vector Informatik liability shall be
* expressly excluded in cases of ordinary negligence, to the extent admissible by law or statute.
*********************************************************************************************************************/
/**********************************************************************************************************************
* REVISION HISTORY
* -------------------------------------------------------------------------------------------------------------------
* Version Date Author Change Id Description
* -------------------------------------------------------------------------------------------------------------------
* 01.00.00 2020-09-23 vismun Initial version with GHS, GNU and HIGHTEC compilers
* 01.01.00 2020-11-02 visbwa Added support for Arm6 compiler, removed AUTHOR IDENTITY
* 01.01.01 2020-12-17 visrgm Added disabling for Thumb mode exceptions in ARMStartup_CortexR52.c
* 01.01.02 2021-01-14 visbwa Fixed BRANCH to brsDisableMpuRegionsLoopStart and startup_block_zero_init_loop_start
* for ARM compilers in ARMStartup_CortexR52.c
* 01.02.00 2021-02-02 vismaa Added BrsHw_GetCore() from StellarS6 BrsHW implementation
* vismun Extended BrsHw_GetCore() implementation to be generic
* 2021-03-10 visbwa update to Brs_Template 1.02.00, moved revision history of all .c and .h files into
* ARMBrsHw_CortexR52.h, added SingleCore stubs for Read_COREID (always return 0),
* fixed branches to stack pointer init routines for MultiCore in ARMStartup_CortexR52.c
* 01.02.01 2021-03-18 visbwa Added check for BRSHW_NUM_CORES_PER_DOMAIN into ARMBrsHw_CortexR52.c
* 01.02.02 2021-03-18 vismaa Memory initialization process changed with vLinkGen vLinkGen_xxx_Blocks
* 01.02.03 2022-03-09 visbwa ESCAN00111447 Fixed zero_init loops in ARMStartup_CortexR52.c, renamed area_zero_init to group_zero_init,
* introduced BRS_BRANCH_GREATER_THAN_OR_EQUAL, added support for 8 byte aligned ECC initialization,
* fixed BrsHwDisableInterruptAtPowerOn() for Arm6 compiler
* 01.02.04 2022-03-11 visrgm Fixed alignment for GNU compiler and usage of MODE_SYS in ARMStartup_CortexR52.c
* 01.02.05 2022-03-14 visbwa ESCAN00111482 StartupCode is not mapped into specific section "brsStartup" for Arm6 compiler (ARMStartup_CortexR52.c)
* ESCAN00111483 StartupCode is using ARM_LIB_STACK instead of STACK_C0 to initialize stackpointer during startup (ARMStartup_CortexR.c),
* removed unused BRS_SECTION_DATA fragments from some compiler abstractions
* 01.03.00 2022-04-22 vishci Added LlvmHightec compiler support
* 01.03.01 2022-05-23 vishci Bugfix whithin BRS_SECTION_CODE LlvmHightec compiler
* 02.00.00 2022-03-22 visjhr Update to Brs_Template 1.03.04
* 2022-05-23 visbwa Removed fragments of several not supported compilers, fixed LlvmHightec support,
* fixed encapsulation of _start (alternative start symbol for OS)
* 2022-06-28 virrlu Small fixes in StartupCode
* 02.00.01 2022-07-06 visbwa Reverted changed MPU settings in StartupCode
* 02.00.02 2022-08-04 visbwa Fixed LlvmHightec support in ARMBrsHwIntTb_CortexR52.c, Brs_Template 1.03.05
* 02.01.00 2022-10-18 visbwa Introduction of BRS_ENABLE_HYPERVISOR_MODE_HANDLING
* 2022-10-19 xchen Introduction of BRS_THUMB_SECTION macro for thumb section; bugfix in entry point for
* all cores in EL1 mode and in brsStartupStackSearch (ARMStartup_CortexR52.c)
* 02.01.01 2022-10-28 xchen Clear TE bit in SCTLR_EL1 for all cores in EL1 and ARM mode (ARMStartup_CortexR52.c)
* 02.01.02 2022-11-28 xchen Added support for multicore platforms, where all cores are autostart (all cores,
* except the boot core, are halted at startup until the start pattern was set)
* 02.02.00 2022-01-19 visrgm Added support for implementation of brsPreAsmStartupHook in ARMStartup_CortexR52.c
* 2023-02-24 visbwa ESCAN00113944 Linking of brsExcVect and brsExcVectRam in ARMBrsHwIntTb_CortexR52.c not working with Arm6 compiler -> better use Brs_MemMap.h,
* introduction of BRS_MEMMAP_INLINE_ASSEMBLER_USED (needed for GHS compiler)
* 02.02.01 2023-03-03 visbwa Changed default memory attribute indirection registers in startup code from
* wright-through to non-cachable, to allow usage of DMA controllers (e.g. for DrvEth)
* 02.02.02 2023-05-16 visdri Clear SCTLR.TE bit in startup code to enter Exc in ARM mode even when compiling in Thumb mode
* 02.03.00 2023-05-23 visbwa Update to Brs_Template 1.03.09: mapping of BrsHw_CoreExceptionHandler() into startup
* code section in ARMBrsHwIntTb_CortexR52.c
* 02.04.00 2023-06-13 visbwa Added support for compiler GccNxp, changed BRS_READ_COREID macro fur multicore,
* updated description of brsTcmBase in ARMStartup_Platform.h and ARMStartup_CortexR52.c
* 02.05.00 2023-06-15 visrgm HALBE-9624 Changed ExceptionTable mechanism to use LDR
* 02.05.01 2023-10-19 vissgj BASEENV-10091 Modified the memory access register MAIR0 for peripheral access in ARMStartup_CortexR52.c to no Early Write Acknowledgement
* (to solve issues with access to CAN peripheral, occured on StellarSr6 platform)
* 02.05.02 2024-02-28 visbwa Added clearing of pending data abort exceptions in ARMStartup_CortexR52.c
* 2024-03-04 visqli Fixed GccNXP compiler error because of missing prefix(#) in StartupCode assembler
* 02.05.03 2024-03-07 visbwa Fixed additional GccNXP compiler error because of missing prefix(#) in StartupCode assembler
*********************************************************************************************************************/
#ifndef _ARMBRSHW_CORTEXR52_H_
#define _ARMBRSHW_CORTEXR52_H_
/**********************************************************************************************************************
* MODULE VERSION
*********************************************************************************************************************/
/*
* Description: This is the BrsHw main and bug fix version. The version numbers are BCD coded.
* E.g. a main version of 1.23 is coded with 0x0123, a bug fix version of 9 is coded 0x09.
*/
#define ARMBRSHW_CORTEXR52_VERSION 0x0205u
#define ARMBRSHW_CORTEXR52_BUGFIX_VERSION 0x03u
/**********************************************************************************************************************
* INCLUDES
*********************************************************************************************************************/
/*
* Description: The BrsCfg header is used to configure different types of
* tests and system setups. Therefore it must be included first
* in each BRS and test module.
* This file is part of the BRS.
*/
#include "vBrsCfg.h"
#include "BrsMain.h"
/**********************************************************************************************************************
* CONFIGURATION CHECK
*********************************************************************************************************************/
/* Configuration checks performed within platform specific code (BrsHw) */
/**********************************************************************************************************************
* GLOBAL CONSTANT MACROS
*********************************************************************************************************************/
/*
* Description: Macro for access to IO addresses
*/
#define BRSHW_IOS(type, address) (*((volatile type *)(address)))
#define BRSHWNOP10() do { \
__asm(" NOP"); \
__asm(" NOP"); \
__asm(" NOP"); \
__asm(" NOP"); \
__asm(" NOP"); \
__asm(" NOP"); \
__asm(" NOP"); \
__asm(" NOP"); \
__asm(" NOP"); \
__asm(" NOP"); \
} while(0)
/* CPU modes */
#define MODE_FIQ 0x11
#define MODE_IRQ 0x12
#define MODE_SVC 0x13
#define MODE_MON 0x16
#define MODE_ABT 0x17
#define MODE_UNDEF 0x1B
#define MODE_SYS 0x1F
#define MODE_STACK_SIZE 0x40
/* GICv3 Distributor (GICD) */
#define GICD_BASE brsHwGetImpCbar()
#define GICD_IGROUPR(n) BRSHW_IOS(uint32, GICD_BASE + 0x0080 + (4u * n)) /* n= [1:30] */
#define GICD_ISENABLER(n) BRSHW_IOS(uint32, GICD_BASE + 0x0100 + (4u * n)) /* n= [1:30] */
#define GICD_ICENABLER(n) BRSHW_IOS(uint32, GICD_BASE + 0x0180 + (4u * n)) /* n= [1:30] */
#define GICD_ISPENDR(n) BRSHW_IOS(uint32, GICD_BASE + 0x0200 + (4u * n)) /* n= [1:30] */
#define GICD_ICPENDR(n) BRSHW_IOS(uint32, GICD_BASE + 0x0280 + (4u * n)) /* n= [1:30] */
#define GICD_IPRIORITYR(n) BRSHW_IOS(uint32, GICD_BASE + 0x0400 + (4u * n)) /* n= [8:247] */
#define GICD_IROUTER(n) BRSHW_IOS(uint64, GICD_BASE + 0x6000 + (8u * n)) /* n= [32:991 */
/* GICv3 Reistributor for SGIs and PPIs (GICR) */
#define GICR_BASE(n) (GICD_BASE + 0x110000ul + (0x20000ul * n)) /* n= [0:3] */
#define GICR_IGROUP0(n) BRSHW_IOS(uint32, GICR_BASE(n) + 0x0080)
#define GICR_ISENABLER0(n) BRSHW_IOS(uint32, GICR_BASE(n) + 0x0100)
#define GICR_ICENABLER0(n) BRSHW_IOS(uint32, GICR_BASE(n) + 0x0180)
#define GICR_ISPENDR0(n) BRSHW_IOS(uint32, GICR_BASE(n) + 0x0200)
#define GICR_ICPENDR0(n) BRSHW_IOS(uint32, GICR_BASE(n) + 0x0280)
#define GICR_IPRIORITYR(n, m) BRSHW_IOS(uint32, GICR_BASE(n) + 0x0400 + (4u * m)) /* n= [0:7] */
/* Read Core Id. */
#if (BRS_CPU_CORE_AMOUNT>1)
#define BRS_READ_COREID(c) \
__asm( "MRC p15, 0, r0, c0, c0, 5 \n" \
"AND r1, r0, #0xFF00 \n" \
"LDR r2, =0x08 \n" \
"LSR r1, r1, r2" ); \
__as1(LDR r2, =BRSHW_NUM_CORES_PER_DOMAIN) \
__asm( "MUL r1, r1, r2 \n" \
"AND r0, r0, #0xF \n" \
"ADD r0, r0, r1" );
#else
/* Stub for SingleCore environments, always returns 0 */
#define BRS_READ_COREID(c) __as1(MOV c, 0)
#endif /*BRS_CPU_CORE_AMOUNT*/
/*
* Description: Macros used in vBRS generated vBrs_Lcfg.c.
*/
#if defined (BRS_COMP_ARM6)
# if defined (BRS_ENABLE_FBL_SUPPORT)
#define _Brs_ExcVectRam_START Image$$Brs_ExcVectRam$$Base
/* Special value, needed for SingleCore UseCase w/o OS (e.g. FBL). vBRS will generate "BRSHW_DEFINE_STARTUP_STACK(BRSHW_INIT_CORE_ID)"
for this. Configure here the valid value for the StartupStack pointer label of the boot core */
#define BRSHW_DEFINE_STARTUP_STACK(BRSHW_INIT_CORE_ID) Image$$STACK_C0$$Limit
# else
#define BRSHW_DEFINE_STARTUP_STACK(x) Image$$STACK_C##x##$$Limit
# endif
/* No separate ExcVec table on cortexR! OS is defining one interrupt table for exceptions + interrupts */
#define BRSHW_DEFINE_EXCVEC(x) Image$$OS_EXCVEC_CORE##x##_CODE$$Base
#define BRSHW_DEFINE_INTVEC(x) Image$$OS_EXCVEC_CORE##x##_CODE$$Base /* just as dummy to compile vBrs_Lcfg.c, not used in BrsHw_ExceptionTable_Init() */
#else
#define BRSHW_DEFINE_STARTUP_STACK(x) _STACK_C##x##_LIMIT
/* No separate ExcVec table on cortexR! OS is defining one interrupt table for exceptions + interrupts */
#define BRSHW_DEFINE_EXCVEC(x) _OS_EXCVEC_CORE##x##_CODE_START
#define BRSHW_DEFINE_INTVEC(x) _OS_EXCVEC_CORE##x##_CODE_START /* just as dummy to compile vBrs_Lcfg.c, not used in BrsHw_ExceptionTable_Init() */
#endif /*BRS_COMP_x*/
/* Special value, needed for SingleCore UseCase w/o OS (e.g. FBL). vBRS will generate "BRSHW_DEFINE_STARTUP_STACK(BRSHW_INIT_CORE_ID)"
for this. Configure here the valid value for the StartupStack pointer label of the boot core */
#define _STACK_CBRSHW_INIT_CORE_ID_LIMIT _STACK_C0_LIMIT /* this macro is not used with Arm6 compiler */
/**********************************************************************************************************************
* Compiler abstraction
*********************************************************************************************************************/
#if defined (BRS_COMP_ARM6)
#define ___asm(c) __asm_(c)
#define __asm_(c) __asm(#c);
#define __as1(c, d) __as1_(c, d)
#define __as1_(c, d) __asm( #c " , " #d);
#define __as2(c, d, e) __as2_(c, d, e)
#define __as2_(c, d, e) __asm( #c " , " #d " , " #e);
#define __as3(c, d, e, f) __as3_(c, d, e, f)
#define __as3_(c, d, e, f) __asm( #c " , " #d " , " #e " , " #f);
#define __as4(c, d, e, f, g) __as4_(c, d, e, f, g)
#define __as4_(c, d, e, f, g) __asm( #c " , " #d " , " #e " , " #f " , " #g);
#define __as5(c, d, e, f, g, h) __as5_(c, d, e, f, g, h)
#define __as5_(c, d, e, f, g, h) __asm( #c " , " #d " , " #e " , " #f " , " #g " , " #h);
#define BRS_MULTILINE_ASM_BEGIN()
#define BRS_MULTILINE_ASM_END()
#define BRS_ASM_EQU(Label, Value) __as1(.equ Label, Value)
#define BRS_ISR_KEYWORD __attribute__ ((interrupt("IRQ")))
# if defined (BRS_COMP_ARM6)
/* vLinkGen is not using the dot in front of the section names */
#define BRS_SECTION_CODE(c) __as1(.section c , "ax" )
# else
#define BRS_SECTION_CODE(c) __as1(.section .c , "ax" )
# endif
#define BRS_GLOBAL(c) ___asm(.globl c)
#define BRS_LOCAL_PROTOTYPE(c) void c (void);
#define BRS_LABEL(c) ___asm(c:)
#define BRS_GLOBAL_END()
/* Unconditional branch to c */
#define BRS_BRANCH(c) ___asm(B c)
#define BRS_EXTERN_BRANCH(c) ___asm(B c)
/* Branch to e if c and d are equal */
#define BRS_BRANCH_EQUAL(c,d,e) __as1(CMP c, d) \
___asm(BEQ e)
/* Branch to e if c and d are NOT equal */
#define BRS_BRANCH_NOT_EQUAL(c,d,e) __as1(CMP c, d) \
___asm(BNE e)
/* Branch to e if c is greater than d*/
#define BRS_BRANCH_GREATER_THAN(c,d,e) __as1(CMP c, d) \
___asm(BGT e)
/* Branch to e if c is greater or equal than d */
#define BRS_BRANCH_GREATER_THAN_OR_EQUAL(c,d,e) __as1(CMP c, d) \
___asm(BGE e)
/* Defines a thumb section */
#define BRS_THUMB_SECTION() ___asm(.thumb_func)
/* Multiprocessor affinity (MPIDR) */
static inline uint32 brsHwGetMpidr(void)
{
uint32 val;
__asm__ volatile( " MRC p15, 0, %0, c0, c0, 5 "
: "=r" (val)
:
: );
return val;
}
/* Configuration Base Address Register (IMP_CBAR). */
static inline uint32 brsHwGetImpCbar(void)
{
uint32 val;
__asm__ volatile( " MRC p15, 1, %0, c15, c3, 0 "
: "=r" (val)
:
: );
return val;
}
#else
#error "Compiler not yet supported"
#endif /*BRS_COMP_x*/
/**********************************************************************************************************************
* BrsHW configuration
*********************************************************************************************************************/
/**********************************************************************************************************************
* GLOBAL VARIABLES
*********************************************************************************************************************/
/**********************************************************************************************************************
* GLOBAL FUNCTION PROTOTYPES
*********************************************************************************************************************/
/*****************************************************************************/
/* @brief Disable the global system interrupt.
* @pre Must be the first function call in main@BrsMain
* @param[in] -
* @param[out] -
* @return -
* @context Function is called from main@BrsMain at power on initialization
*****************************************************************************/
void BrsHwDisableInterruptAtPowerOn(void);
/*****************************************************************************/
/* @brief Program the vector table base addresses
* @pre -
* @param[in] ExcVecLabel - address of the core exception table
* IntVecLabel - address of the interrupt vector table
* Use BRS_DEFINE_ADDRESS_UNUSED for unused values
* @param[out] -
* @return -
* @context Function is called from main@BrsMain at power on initialization
*****************************************************************************/
void BrsHw_ExceptionTable_Init(Brs_AddressOfConstType, Brs_AddressOfConstType);
/*****************************************************************************/
/* @brief This API is used for the BRS time measurement support to get a
* default time value for all measurements with this platform to
* be able to compare time measurements on different dates based
* on this time result.
* @pre Should be called with interrupts global disabled
* @param[in] -
* @param[out] -
* @return -
* @context Function is called from e.g. component testsuits for calibration
*****************************************************************************/
void BrsHwTime100NOP(void);
/*****************************************************************************/
/* @brief This API is used to read the core ID of the actual running core
* @pre -
* @param[in] -
* @param[out] -
* @return Core ID of the actual running core
* @context Function is e.g. called from main@BrsMain, to only call HW-init
* code once, on the boot core.
* In MultiCore setups, BRSHW_INIT_CORE_ID and
* BRSHW_NUM_CORES_PER_DOMAIN must be declared inside BrsHw.h to
* configure the proper core ID value of boot core and to
* define numbers of cores/domain respectively.
*****************************************************************************/
uint32 BrsHw_GetCore(void);
/*****************************************************************************/
/* @brief This API is used to enable an interrupt source in the core
* interrupt controller.
* @pre -
* @param[in] Source to be enabled on GIC controller (0 <= Source <= 991).
* @param[in] Priority level to be set.
* @param[out] -
* @return -
* @context Function is called from HlpTest and other test environments.
*****************************************************************************/
void BrsHw_EnableInterrupt(uint32, uint8);
/*****************************************************************************/
/* @brief This API is used to disable an interrupt source in the core
* interrupt controller.
* @pre -
* @param[in] Source to be disabled on GIC controller (0 <= Source <= 991).
* @param[out] -
* @return -
* @context Function is called from HlpTest and other test environments.
*****************************************************************************/
void BrsHw_DisableInterrupt(uint32);
/*****************************************************************************/
/* @brief This API is used to trigger the given software interrupt source.
* @pre
* @param[in] Source to be triggered (0 <= Source <= 991).
* @param[out] -
* @return -
* @context Function is called from HlpTest and other test environments.
*****************************************************************************/
void BrsHw_TriggerSoftwareInterrupt(uint32);
#endif /*_ARMBRSHW_CORTEXR52_H_*/

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/**********************************************************************************************************************
* COPYRIGHT
* -------------------------------------------------------------------------------------------------------------------
* \verbatim
* Copyright (c) 2023 by Vector Informatik GmbH. All rights reserved.
*
* This software is copyright protected and proprietary to Vector Informatik GmbH.
* Vector Informatik GmbH grants to you only those rights as set out in the license conditions.
* All other rights remain with Vector Informatik GmbH.
* \endverbatim
* -------------------------------------------------------------------------------------------------------------------
* FILE DESCRIPTION
* -----------------------------------------------------------------------------------------------------------------*/
/** \file File: ARMStartup_PlatformTemplate.h
* Project: Vector Basic Runtime System
* Module: BrsHw for platform Renesas R-Car_x4 Cortex-R52 core
*
* \brief Description: This file contains derivative memory mapping and optional Boot Header for BRS StartUpCode.
*
* \attention Please note:
* The demo and example programs only show special aspects of the software. With regard to the fact
* that these programs are meant for demonstration purposes only, Vector Informatik liability shall be
* expressly excluded in cases of ordinary negligence, to the extent admissible by law or statute.
*********************************************************************************************************************/
/**********************************************************************************************************************
* REVISION HISTORY
* -------------------------------------------------------------------------------------------------------------------
* Refer to BrsHw.h.
*********************************************************************************************************************/
#ifndef _ARMSTARTUP_PLATFORM_H_
#define _ARMSTARTUP_PLATFORM_H_
/* =========================================================================== */
/* GLOBAL CONSTANT MACROS */
/* =========================================================================== */
/*
* Configuration of MPU regions in the startup code.
* Code region base address is typically the flash base.
* Data region base address is typically the RAM base.
* TCM region base address is CORE0_TCMA base.
* Pheripheral region is mandatory and cannot be disabled.
*/
#define MPU_CODE_REGION STD_ON
#define MPU_CODE_REGION_START 0xE2100000UL //0xE2200000 //0xE6300000
#define MPU_CODE_REGION_END 0xE3BF0000UL //0xE3D00000//0xE633FFFF
#define MPU_DATA_REGION STD_OFF
#define MPU_DATA_REGION_START 0xE4200000 //0xE2000000
#define MPU_DATA_REGION_END 0xE5D00000 //0xE3FFFFFF
#define MPU_TCM_REGION STD_ON
#define MPU_TCM_REGION_START 0xE4000000
#define MPU_TCM_REGION_END 0xE4208000
/* Area 0 : H'E210 0000 - H'E22F FFC0
* Normal memory, Non-shareable, Write-Back, Read/Write Allocation
* Instruction permitted
* Setup in start.s
*/
#define MPU_REGION_00_START 0XE2100000UL
#define MPU_REGION_00_END 0xE22FFFC0UL
/* Area 1 : H'0000 00000 - H'07FF FFFF
* Normal memory, Non-shareable, Write-Back, Read/Write Allocation
* Instruction permitted
*/
#define MPU_REGION_01_START 0x00000000UL
#define MPU_REGION_01_END 0x07FFFFC0UL// 0x07FFFFFFUL
/* Area 2 : H'0800 00000 - H'0BFF FFFF
* Normal memory, Non-shareable, Non-cache
* Instruction permitted
*/
#define MPU_REGION_02_START 0x08000000UL
#define MPU_REGION_02_END 0x0BFFFFC0UL //0x0BFFFFFFUL
/* Area 3 : H'0C00 0000 - H'3FFF FFFF
* Normal memory, Non-shareable, Write-Back, Read/Write Allocation
* Instruction permitted
*/
#define MPU_REGION_03_START 0x0C000000UL
#define MPU_REGION_03_END 0x3FFFFFC0UL //0x3FFFFFFFUL
/* Area 4 : H'4000 00000 - H'402F FFFF
* Normal memory, Non-shareable, Write-Back, Read/Write Allocation
* Instruction permitted
*/
#define MPU_REGION_04_START 0x40000000UL
#define MPU_REGION_04_END 0x402FFFC0UL //0x402FFFFFUL
/* Area 5 : H'4030 0000 - H'BFFF FFFF
* Normal memory, Non-shareable, Write-Back, Read/Write Allocation
* Instruction permitted
*/
#define MPU_REGION_05_START 0x40300000UL
#define MPU_REGION_05_END 0xBFFFFFC0UL //0xBFFFFFFFUL
/* Area 6 : H'C000 00000 - H'DFFF FFFF
* Device-nGnRnE, Non-shareable
* Execute never
*/
#define MPU_REGION_06_START 0xC0000000UL
#define MPU_REGION_06_END 0xDFFFFFC0UL //0xDFFFFFFFUL
/* Area 7 : H'E22FFFC1 - H'E3FF FFFF
* Device-nGnRnE, Non-shareable
* Execute never
*/
#define MPU_REGION_07_START 0xE22FFFC1UL
#define MPU_REGION_07_END 0xE3FFFFC0UL //0xE3FFFFFFUL
/* Area 8 : H'E400 00000 - H'E42F FFFF
* Normal memory, Non-shareable, Write-Back, Read/Write Allocation
* Instruction permitted
*/
#define MPU_REGION_08_START 0xE4000000UL
#define MPU_REGION_08_END 0xE42FFFC0UL //0xE42FFFFFUL
/* Area 9 : H'E430 00000 - H'E62F FFFF
* Device-nGnRnE, Non-shareable
* Execute never
*/
#define MPU_REGION_09_START 0x00000000UL
#define MPU_REGION_09_END 0x07FFFFC0UL //0x07FFFFFFUL
/* Area 10 : H'E630 00000 - H'E63F FFFF
* Normal memory, Non-shareable, Write-Back, Read/Write Allocation
* Instruction permitted
*/
#define MPU_REGION_10_START 0xE6300000UL
#define MPU_REGION_10_END 0xE63FFFC0UL //0xE63FFFFFUL
/* Area 11 : H'E640 00000 - H'EB0F FFFF
* Device-nGnRnE, Non-shareable
* Execute never
*/
#define MPU_REGION_11_START 0xE6400000UL
#define MPU_REGION_11_END 0xEB0FFFC0UL //0xEB0FFFFFUL
/* Area 12 : H'EB10 00000 - H'EB12 7FFF
* Normal memory, Non-shareable, Write-Back, Read/Write Allocation
* Instruction permitted
*/
#define MPU_REGION_12_START 0xEB100000UL
#define MPU_REGION_12_END 0xEB127FC0UL //0xEB127FFFUL
/* Area 13 : H'EB12 80000 - H'EB1F FFFF
* Device-nGnRnE, Non-shareable
* Execute never
*/
#define MPU_REGION_13_START 0xEB128000UL
#define MPU_REGION_13_END 0xEB1FFFC0UL //0xEB1FFFFFUL
/* Area 14 : H'EB20 0000 - H'EB3F FFFF
* Normal memory, Non-shareable, Write-Back, Read/Write Allocation
* Instruction permitted
*/
#define MPU_REGION_14_START 0xEB200000UL
#define MPU_REGION_14_END 0xEB3FFFC0UL //0xEB3FFFFFUL
/* Area 15 : H'EB40 00000 - H'FFFF FFFF
* Device-nGnRnE, Non-shareable
* Execute never
*/
#define MPU_REGION_15_START 0xEB400000UL
#define MPU_REGION_15_END 0xFFFFFFC0UL //0xFFFFFFFFUL
/* Area 16 : H'E600 00000 - H'E62F FFFF
* Device-nGnRnE, Non-shareable
* Execute never
*/
#define MPU_REGION_16_START 0xE6000000UL
#define MPU_REGION_16_END 0xE62FFFC0UL //0xE62FFFFFUL
/* Pheripheral region is mandatory. */
#define MPU_PERIPHERAL_REGION_START 0xF0000000 /* Base address of peripheral region */
#define MPU_PERIPHERAL_REGION_END 0xFFFFFFFF /* End address of peripheral region */
/* Data and Instruction caches */
#define BRS_ENABLE_CACHE STD_ON //STD_OFF
/* Tightly Coupled Memory (TCM) */
#define BRS_ENABLE_TCM STD_ON
#define NUM_TCM_PER_CORE 2
/* Enable this, if the controller is entering the Brs startup code in hypervisor mode (EL2).
This will cause the startup code to provide an additional startup entry brsStartupHyp and to handle
the switch from EL2 to EL1 (and jump to brsStartupEntry) */
#define BRS_ENABLE_HYPERVISOR_MODE_HANDLING STD_ON
/* Set T32 instruction mode for EL2 and EL1 entry points */
#define BRS_SET_T32_ENTRY_POINT STD_OFF
/* =========================================================================== */
/* Global const variables */
/* =========================================================================== */
#if (BRS_ENABLE_TCM == STD_ON)
/*
* CortexR52 architecture supports up to three optional TCMs per core.
* Array that defines base address and size of each supported TCM/Core.
* Size must be encoded in bits 2 through 6 according to following scheme:
* 0b00000 --> No TCM present
* 0b00100 --> 8 KB
* 0b00101 --> 16 KB
* 0b00110 --> 32 KB
* 0b00111 --> 64 KB
* 0b01000 --> 128 KB
* 0b01001 --> 256 KB
* 0b01010 --> 512 KB
* 0b01011 --> 1 MB
*/
const uint32 brsTcmBase[BRS_CPU_CORE_AMOUNT][NUM_TCM_PER_CORE] = {
{
0xE4000018, /* CLUSTER0_CORE0_TCMA */
0xE4100018, /* CLUSTER0_CORE0_TCMB */
0xE4200018}, /* CLUSTER0_CORE0_TCMC */
#if defined (BRS_DERIVATIVE_GROUP_A)
{
0xE4400018, /* CLUSTER0_CORE1_TCMA */
0xE4500018, /* CLUSTER0_CORE1_TCMB */
0xE4600018}, /* CLUSTER0_CORE1_TCMC */
{
0xE4800018, /* CLUSTER0_CORE2_TCMA */
0xE4900018, /* CLUSTER0_CORE2_TCMB */
0xE4A00018}, /* CLUSTER0_CORE2_TCMB */
#endif
};
#endif /*BRS_ENABLE_TCM*/
/* =========================================================================== */
/* */
/* Description: Platform specific Boot Header (Optional) */
/* */
/* =========================================================================== */
BRS_SECTION_CODE(brsBootRecordHeader)
BRS_GLOBAL(brsBootRecord)
BRS_MULTILINE_ASM_BEGIN()
BRS_LABEL(brsBootRecord)
/*
* Some derivatives allocate the entry point to hypervisor mode (brsStartupEntryHyp)
* using boot header table that can be defined in this section.
*/
BRS_MULTILINE_ASM_END()
BRS_GLOBAL_END()
#endif /*_ARMSTARTUP_PLATFORM_H_*/

13
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<EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD>
MCU
IIC
WDG -> <20><><EFBFBD><EFBFBD> <20><><EFBFBD>ϴ<EFBFBD> <20><>
ICCOM
SPI
PORT
GPT
DIO
19.4.0 SPI<50><49> <20><><EFBFBD><EFBFBD><EFBFBD>ϴٰ<CFB4> <20><>Ƽ<EFBFBD><C6BC> <20>ö<EFBFBD><C3B6><EFBFBD><EFBFBD><EFBFBD> <20>ʴ<EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20>ִ<EFBFBD>.

68
Customer/MOBIS/PRK3_(ADAS_Parking3)/Code/PMIC_IIC_new.txt Normal file
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void PMIC_I2C_1Byte_Write_with_crc(uint8 slaveIdx, uint16 regAdd, uint8 data)
{
uint8 targetPage = (uint8)((regAdd >> 8) & 0xFF);
uint8 targetAddr = (uint8) (regAdd & 0xFF);
uint8 txBuf[3]; /* [Address, Data, CRC] */
uint8 crcInput[4]; /* Maximum 4 bytes for Read-back CRC */
uint8 slaveAddr = (uint8)CddIic_GaaSlaveConfig[slaveIdx].ulSlaveAddress;
/* 1. Page Switching Logic with CRC8 */
if (g_pmic_current_page[slaveIdx] != targetPage)
{
uint8 pgRxBuf[2];
txBuf[0] = 0x00; /* Page Selector Register */
txBuf[1] = targetPage; /* This is 0x01 */
crcInput[0] = (slaveAddr << 1) | 0x00U;
crcInput[1] = txBuf[0];
crcInput[2] = txBuf[1];
txBuf[2] = crc8(crcInput, 3);
/* [Spec] Page Write - 1st */
IIC_Reset();
CddIic_Ch0Write(&txBuf[0], 3, &CddIic_GaaSlaveConfig[slaveIdx]);
I2C_Communication_Complete();
/* [Spec] Page Write - 2nd */
IIC_Reset();
CddIic_Ch0Write(&txBuf[0], 3, &CddIic_GaaSlaveConfig[slaveIdx]);
I2C_Communication_Complete();
/* [Spec] Page Read-back Verification */
IIC_Reset();
CddIic_Ch0WriteRead(&txBuf[0], 1, &pgRxBuf[0], 2, &CddIic_GaaSlaveConfig[slaveIdx]);
I2C_Communication_Complete();
crcInput[0] = (slaveAddr << 1) | 0x00U;
crcInput[1] = 0x00;
crcInput[2] = (slaveAddr << 1) | 0x01U;
crcInput[3] = pgRxBuf[0];
if ((crc8(crcInput, 4) == pgRxBuf[1]) && (pgRxBuf[0] == targetPage))
{
g_pmic_current_page[slaveIdx] = targetPage;
}
else
{
g_pmic_current_page[slaveIdx] = 0xFF;
return;
}
}
/* 2. Actual Data Write with CRC8 */
/* RE-INITIALIZE txBuf and crcInput with correct values (targetAddr=0x07, data=0x84) */
txBuf[0] = targetAddr; /* 0x07 */
txBuf[1] = data; /* 0x84 - <20><><EFBFBD>ڷ<EFBFBD> <20><><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD> */
/* Calculate CRC specifically for this write operation */
crcInput[0] = (slaveAddr << 1) | 0x00U;
crcInput[1] = txBuf[0]; /* 0x07 */
crcInput[2] = txBuf[1]; /* 0x84 */
txBuf[2] = crc8(crcInput, 3);
IIC_Reset();
/* Expecting Packet: SlaveID + 0x07 + 0x84 + CRC */
CddIic_Ch0Write(&txBuf[0], 3, &CddIic_GaaSlaveConfig[slaveIdx]);
I2C_Communication_Complete();
}

70
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void PMIC_I2C_1Byte_Write_with_crc(uint8 slaveIdx, uint16 regAdd, uint8 data)
{
uint8 targetPage = (uint8)((regAdd >> 8) & 0xFF);
uint8 targetAddr = (uint8)(regAdd & 0xFF);
uint8 txBuf[3]; /* [Address, Data, CRC] */
uint8 crcInput[4]; /* Maximum 4 bytes for Read-back CRC */
uint8 slaveAddr = (uint8)CddIic_GaaSlaveConfig[slaveIdx].ulSlaveAddress;
/* 1. Page Switching Logic with CRC8 */
if (g_pmic_current_page[slaveIdx] != targetPage)
{
uint8 pgRxBuf[2]; /* [Data, CRC] */
/* Prepare Page Change Packet: Reg 0x00, Target Page */
txBuf[0] = 0x00; /* Page Selector Register */
txBuf[1] = targetPage;
/* CRC for Write: SlaveAddr(W) + RegAddr + Data */
crcInput[0] = (slaveAddr << 1) | 0x00U;
crcInput[1] = txBuf[0];
crcInput[2] = txBuf[1];
txBuf[2] = crc8(crcInput, 3);
/* [Spec] 1st Page Write with CRC */
IIC_Reset();
CddIic_Ch0Write(&txBuf[0], 3, &CddIic_GaaSlaveConfig[slaveIdx]);
I2C_Communication_Complete();
/* [Spec] 2nd Page Write with CRC */
IIC_Reset();
CddIic_Ch0Write(&txBuf[0], 3, &CddIic_GaaSlaveConfig[slaveIdx]);
I2C_Communication_Complete();
/* [Spec] Page Read-back Verification with CRC */
IIC_Reset();
/* Use WriteRead (Repeated Start) to read Reg 0x00 */
CddIic_Ch0WriteRead(&txBuf[0], 1, &pgRxBuf[0], 2, &CddIic_GaaSlaveConfig[slaveIdx]);
I2C_Communication_Complete();
/* [Modified] Verify Read-back CRC: SlaveAddr(W) + RegAddr + SlaveAddr(R) + Received Data */
crcInput[0] = (slaveAddr << 1) | 0x00U; /* Slave(W) */
crcInput[1] = 0x00; /* Register Address (Page Selector) */
crcInput[2] = (slaveAddr << 1) | 0x01U; /* Slave(R) */
crcInput[3] = pgRxBuf[0]; /* Received Page Value */
if ((crc8(crcInput, 4) == pgRxBuf[1]) && (pgRxBuf[0] == targetPage))
{
g_pmic_current_page[slaveIdx] = targetPage;
}
else
{
g_pmic_current_page[slaveIdx] = 0xFF; /* Switch failed or CRC error */
return;
}
}
/* 2. Actual Data Write with CRC8 */
txBuf[0] = targetAddr;
txBuf[1] = data;
/* CRC for Write: SlaveAddr(W) + RegAddr + Data */
crcInput[0] = (slaveAddr << 1) | 0x00U;
crcInput[1] = txBuf[0];
crcInput[2] = txBuf[1];
txBuf[2] = crc8(crcInput, 3);
IIC_Reset();
CddIic_Ch0Write(&txBuf[0], 3, &CddIic_GaaSlaveConfig[slaveIdx]);
I2C_Communication_Complete();
}

49
Customer/MOBIS/PRK3_(ADAS_Parking3)/Doc/On-Site_Support_Timetable/Onsite_20260511.txt Normal file
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(Priority1)<29><> Multicore SPI support for lower CPU usage(REKR_MOBIS-270)
<09><> Case1- Workaround(Short term solution)
Pham is currently modifying the source code within the customer's environment
<09><> Case2 - MCAL Multicore TYPE 4(Long term solution)
Support for Multi-core Type 4 is feasible; however, we need additional time to ensure a quality implementation.
Reference URL"2.5.6.4 MCAL Multi-Core Module Type IV"
https://www.autosar.org/fileadmin/standards/R19-11/CP/AUTOSAR_EXP_BSWDistributionGuide.pdf
(Priority1)<29><> I2C communication reset requirement: explanation the I2C patch to customer(REKR_MOBIS-943)
<09><> Binh to provide a technical explanation to the customer.
<09><> MCAL Version Verification
v19.1.0 -> we will check custemer's use ver.
v19.3.0 -> we will check custemer's use ver.
v19.4.0 -> The customer is planning to update to this version. Renesas will issue a patch based on this version.(Target Delivery Date: May 22th)
(Priority1)<29><> I2C communication reset requirement: Reset requirement discussion(REKR_MOBIS-995/957)
The customer tested after removing the Reset function(Reset I2C with SRCR and SRSTCLR),
but they reported that I2C Stuck occurred. (Note: This is verbal feedback; no formal logs are available yet.)
In today's meeting, Binh advised the customer that removing the Reset API is not recommended.
The customer's is that directly controlling H/W registers from the BSW (rather than using an API) is not an ideal implementation.
<09><> Requests to the H/W Team
Customer Requirement:
Please provide a detailed technical explanation of why the Reset(Reset I2C with SRCR and SRSTCLR) is mandatory for I2C communication.
We need clear reasoning to justify this to the customer.
<09><> Requests to the MCAL Team
Customer Requirement: The customer is requesting to have the I2C Reset integrated within the MCAL CDD Iic.
If we proceed with this integration, what would be the expected delivery schedule?
<EFBFBD><EFBFBD> AutoSAR architecture review
Meeting with the customer is scheduled for Tuesday, May 12th in the afternoon.
<EFBFBD><EFBFBD> Let's review the source code together to debug this issue.
<20><> CDD EMM notification(callback: REKR_MOBIS-1000)
<20><> IRQ model sample code(REKR_MOBIS-965)
<EFBFBD><EFBFBD> We need to verify the actual behavior of the CDD module
CRC: Verification is needed.
EMM: Verification is needed.
IPMMU: The customer will not use this feature as it conflicts with the existing configurations on the QNX side.
RFSO: Verification is needed.
THS: Verification is needed. 1<><31> <20><><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD>, but 4<><34> <20><><EFBFBD><EFBFBD> Notification<6F><6E> EMM<4D><4D><EFBFBD><EFBFBD> <20>ö<EFBFBD><C3B6><EFBFBD>.(<28><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> å<>Ӵ<EFBFBD> AP<41><50><EFBFBD><EFBFBD> 4<><34> <20><><EFBFBD>밡<EFBFBD><EBB0A1><EFBFBD><EFBFBD><EFBFBD><EFBFBD> Ȯ<><C8AE>)
ICCOM: The customer has completed the verification.
IIC: The customer has completed the verification.

32
Customer/MOBIS/PRK3_(ADAS_Parking3)/Doc/On-Site_Support_Timetable/Onsite_20260515.txt Normal file
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P1 P2
OEM 6/1 9/15
Mobis 5/15 6/30
Code Freeze
Tony. <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ʈ CPM Fully Type2 <20><>û
1<EFBFBD><EFBFBD> 7<><37><EFBFBD><EFBFBD>
Autosar SC1 : DDR Only <20><><EFBFBD><EFBFBD>
Autosar SC3 : SRAM <20>Ϻ<EFBFBD> + DDR <20><><EFBFBD><EFBFBD>
<EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20>غ<EFBFBD><D8BA><EFBFBD>Ȳ
1. MCAL 19.4.0 => Tony <20><><EFBFBD><EFBFBD> <20>Ϸ<EFBFBD>.
2. Autosar SC3
*SPI <20><><EFBFBD><EFBFBD>¡ Test
Mobis - Autosar SC3 + MCAL 19.1.0 + SPI Multi-Core Patch : <20>ݿ<EFBFBD><DDBF><EFBFBD> Start
Renesas - Autosar SC1 + P1 Environment + SPI Multi-Core Patch : <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> 16:00 Start
<EFBFBD>ʿ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
*<2A><><EFBFBD><EFBFBD> <20><>ġ<EFBFBD><C4A1> MCAL 19.4.0 Base<73><65><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD>Ǿ<EFBFBD><C7BE><EFBFBD><EFBFBD>Ѵ<EFBFBD>.
1. SPI Multi-Core(Like Type2) Patch <20>غ<EFBFBD>(<28>Ƹ<EFBFBD> Pham)
2. I2C Stuck <20><>ġ <20>غ<EFBFBD>(<28>Ƹ<EFBFBD> Pham)
3. I2C Reset API 1th <20><>ġ <20>غ<EFBFBD>(<28>Ƹ<EFBFBD> MCAL <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>)
4. I2C <20><> <20>⺻ Build <20><> <20><> <20>ְ<EFBFBD> RTE_xx <20><><EFBFBD><EFBFBD> <20><> <20><><EFBFBD><EFBFBD>(Binh<6E><68> MCAL <20><><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD> <20><>)
5. MCU Module PLL <20><>ȸ <20><><EFBFBD><EFBFBD>, Jira-487 <20><>ġ<EFBFBD><C4A1> <20>ʿ<EFBFBD>.
*ECM/EMM/RFSO <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD>̵尡 <20>ʿ<EFBFBD>.
*MTCI I2C Reset API <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD> <20>ʴ´<CAB4>.
*SPI Multi-Core Patch <20><> <20><><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD>
<EFBFBD>ڵ帮<EFBFBD><EFBFBD>X

BIN
Customer/MOBIS/PRK3_(ADAS_Parking3)/Doc/On-Site_Support_Timetable/Onsite_Support_AI_list_20260518.xlsx Normal file
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Binary file not shown.

BIN
Customer/MOBIS/PRK3_(ADAS_Parking3)/Doc/On-Site_Support_Timetable/Onsite_Support_AI_list_20260519.xlsx Normal file
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Binary file not shown.

22
Customer/MOBIS/PRK3_(ADAS_Parking3)/Issue/ECM_ERR/20260612_MTG.txt Normal file
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Normal: B+, <20>̱״ϼ<D7B4>,
B+, ON
<EFBFBD>̱״ϼ<EFBFBD>, OFF
-> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD>
<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
CAN <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> 10<31><30> <20><><EFBFBD><EFBFBD>
<EFBFBD>̳ʳ<EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> Ȯ<><C8AE>
<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>.
<EFBFBD>˴ٿ<EFBFBD> <20><><EFBFBD>μ<EFBFBD><CEBC><EFBFBD> <20><><EFBFBD>Խ<EFBFBD> <20>ϴ<EFBFBD> <20><><EFBFBD><EFBFBD>
<EFBFBD>Ŀ<EFBFBD> <20><><EFBFBD><EFBFBD> -> CANFD Pen <20><>ȣ<EFBFBD><C8A3> <20><><EFBFBD><EFBFBD><EFBFBD>ؼ<EFBFBD> <20>˴ٿ<CBB4>
PMIC<EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD>ؼ<EFBFBD> Ȯ<><C8AE><EFBFBD>ϴ<EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD>.
Preset Low -> PMIC <20><>Ʈ, SoC<6F><43> PMIC<49><43> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD>
ECMERRSTSR41
00800400

31
Customer/MOBIS/PRK3_(ADAS_Parking3)/Issue/External IRQ/20260526_GPIO_SET.txt Normal file
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<EFBFBD>ڼ<EFBFBD><EFBFBD><EFBFBD> å<>Ӵ<EFBFBD> Test
8<EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD> PMIC IRQ GP4_16 <20><><EFBFBD>ͷ<EFBFBD>Ʈ Test
8<EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD> SCL3 GP8_6 <20><><EFBFBD>ͷ<EFBFBD>Ʈ Test
Interrupt Mask Clear
Register MSKCLRn R/W H<><48>0000 0000 H<><48>19C 32
For some unknown reason, testing on GP1_20 showed that GP0_6 was being controlled instead.
Consequently, Mobis is planning to change the assignment once again from GP1_20 to GP4_16.
Will there be any issues if Mobis uses GP4_16 to receive the PMIC Interrupt?
Interrupt ID
>619 PortGroup0 0x028B GPIO0_port_group0.ch0
> + 32
> = 651
>623 PortGroup1 0x028F GPIO0_port_group1.ch0
> + 32
> = 655
>635 PortGroup4 0x029B GPIO2_port_group0.ch0
> + 32
> = 667
>651 PortGroup8 0x02AB GPIO3_port_group0.ch0
> + 32
> = 683
PER.Set.simple ASD:0xE605019C %Long 0x40

153
Customer/MOBIS/PRK3_(ADAS_Parking3)/Issue/External IRQ/20260528_IRQ디버깅.txt Normal file
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<EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD>ž<EFBFBD> <20><> <20><><EFBFBD><EFBFBD> GPSRn (General Purpose Select Register)<29><> IPiSRn (Pin Function Select Register)<29>Դϴ<D4B4>.
GPSR0 = 00001E00: Bit 6<><36> 0<>Դϴ<D4B4>. (GPIO <20><><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD>)
IOINTSEL0 = 00000000: Bit 6<><36> 0<>Դϴ<D4B4>. (<28><><EFBFBD>ͷ<EFBFBD>Ʈ<EFBFBD><C6AE> <20>ƴ<EFBFBD> <20>Ϲ<EFBFBD> I/O <20><><EFBFBD><EFBFBD>)
INOUTSEL0 = 000001C1: Bit 6<><36> 1<>Դϴ<D4B4>. (Output <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><>Ȯ<EFBFBD><C8AE> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>)
OUTDT0 = 00000141: Bit 6<><36> 1<>Դϴ<D4B4>. (<28><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> High <20><>ȣ<EFBFBD><C8A3> <20><><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD>)
INDT0 = 0002A171: Bit 6<><36> 1<>Դϴ<D4B4>. (<28><><EFBFBD><EFBFBD> <20><> <20><><EFBFBD>µ<EFBFBD> High<67><68> <20><> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD>)
<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><>,<2C><><EFBFBD><EFBFBD> <20><> (Hex),6<><36>° <20>ڸ<EFBFBD> <20><>,20<32><30> <20><>Ʈ <20><><EFBFBD><EFBFBD>,<2C>ؼ<EFBFBD> (<28>̰<EFBFBD><CCB0><EFBFBD> <20><>Ʈ<EFBFBD>Դϴ<D4B4>)
GPSR1,0x0E03F0FC,0 (0000),0,<2C><><EFBFBD><EFBFBD> <20>ֺ<EFBFBD><D6BA><EFBFBD>ġ(SSI)<29><> <20>ƴ<EFBFBD> <20>Ϻ<EFBFBD><CFBA><EFBFBD> <20><><EFBFBD><EFBFBD> GPIO <20><><EFBFBD><EFBFBD><EFBFBD>Դϴ<D4B4>.
IOINTSEL1,0x00000000,0 (0000),0,<2C><><EFBFBD>ͷ<EFBFBD>Ʈ <20><><EFBFBD>尡 <20>ƴ<EFBFBD> <20>Ϲ<EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>(I/O) <20><><EFBFBD><EFBFBD><EFBFBD>Դϴ<D4B4>.
INOUTSEL1,0x10D2005C,D (1101),1,<2C><>Ȯ<EFBFBD>ϰ<EFBFBD> Output(<28><><EFBFBD><EFBFBD>) <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> Ȱ<><C8B0>ȭ<EFBFBD>Ǿ<EFBFBD> <20>ֽ<EFBFBD><D6BD>ϴ<EFBFBD>.
OUTDT1,0x10900028,9 (1001),1,SoC<6F><43> <20><><EFBFBD><EFBFBD> <20><> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> High(1) <20><>ȣ<EFBFBD><C8A3> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD> <20><><EFBFBD>Դϴ<D4B4>.
INDT1,0x18132D82,1 (0001),1,<2C><><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD>(Read)<29><> High(1)<29><> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20>ֽ<EFBFBD><D6BD>ϴ<EFBFBD>.
PMMRn // LSI Multiplexed Pin Setting Mask Register
PMMERn // LSI Multiplexed Pin Setting Mask Enable Register
GPSRn // GPIO / Peripheral Function Select Register
IOINTSELn // General IO / Interrupt Switching Register
INOUTSELn // General Input/Output Switching Register
OUTDTn // General Output Register
INDTn // General Input Register
PMMR1 // LSI Multiplexed Pin Setting Mask Register -> <20><>Ʈ <20>ʱ<EFBFBD>ȭ<EFBFBD><C8AD> <20><><EFBFBD><EFBFBD>
PMMER1 // LSI Multiplexed Pin Setting Mask Enable Register -> <20><>Ʈ <20>ʱ<EFBFBD>ȭ<EFBFBD><C8AD> <20><><EFBFBD><EFBFBD>
GPSR1 // GPIO / Peripheral Function Select Register : <20>ֺ<EFBFBD><D6BA><EFBFBD>ġ <20><><EFBFBD>尡 <20>ƴ<EFBFBD> GPIO <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>(0x00000000) Ȯ<><C8AE>
IOINTSEL1 // General IO / Interrupt Switching Register : <20><><EFBFBD>ͷ<EFBFBD>Ʈ <20><><EFBFBD>尡 <20>ƴ<EFBFBD> <20>Ϲ<EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>(I/O) <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>(0x00000000) Ȯ<><C8AE>
INOUTSEL1 // General Input/Output Switching Register : Input(<28>Է<EFBFBD>(0)) or Output(<28><><EFBFBD><EFBFBD>(1)) <20><><EFBFBD><EFBFBD> Ȱ<><C8B0>ȭ Ȯ<><C8AE>
OUTDT1 // General Output Register : High(1) or Low(0) <20><>ȣ <20><><EFBFBD><EFBFBD> Ȯ<><C8AE>
INDT1 // General Input Register : High(1) or Low(0) <20><>ȣ <20>Է<EFBFBD> Ȯ<><C8AE>
INOUTSEL1_B0A0 10C2005C INOUTSEL 10C2005C
OUTDT1_B0A0 10900028 OUTDT 10900028
INDT1_B0A0 18132D82 INDT 18132D82
<EFBFBD>ܼ<EFBFBD> (Open Trace): <20><><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD> <20>߰<EFBFBD><DFB0><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ų<EFBFBD>, BGA <20><>(Ball) <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><> <20><> <20>ó<EFBFBD>(Cold Solder) <20><><EFBFBD><EFBFBD>.
<EFBFBD>̽<EFBFBD><EFBFBD><EFBFBD> (DNI): PMIC<49><43> SoC <20><><EFBFBD>̿<EFBFBD> <20>־<EFBFBD><D6BE><EFBFBD> <20><> 0<><30> <20><><EFBFBD><EFBFBD><EFBFBD>̳<EFBFBD> <20><><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD>Ͱ<EFBFBD> <20>ƿ<EFBFBD> <20><> <20>޷<EFBFBD> <20>ִ<EFBFBD> <20><><EFBFBD><EFBFBD>.
<EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD> (Wrong Net Routing): ȸ<>ε<EFBFBD><CEB5><EFBFBD><EFBFBD><EFBFBD> GP1_20<32><30><EFBFBD><EFBFBD> <20>׷<EFBFBD><D7B7><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>, <20><><EFBFBD><EFBFBD> PCB <20><>Ʈ<EFBFBD><C6AE> <20><><EFBFBD><EFBFBD><EFBFBD>ڰ<EFBFBD> <20><><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD> <20><> <20>Ǽ<EFBFBD><C7BC><EFBFBD> <20><> <20><>(GP1_19<31><39> GP1_21)<29><><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD>.
<EFBFBD>ֺ<EFBFBD> <20><><EFBFBD><EFBFBD> Ȯ<><C8AE><EFBFBD>ؼ<EFBFBD> <20>װ<EFBFBD><D7B0><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD>غ<EFBFBD><D8BA><EFBFBD>.<2E><>
8<EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD>͵<EFBFBD> <20><>Ʈ<EFBFBD><C6AE> <20>غ<EFBFBD><D8BA><EFBFBD>.
<EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>, <20><><EFBFBD>ݺ<EFBFBD><DDBA>ʹ<EFBFBD> '<27><><EFBFBD><EFBFBD>(Pinmux<75><78> <20><><EFBFBD><EFBFBD><EEB0A1> <20>༮)'<27><> ã<><C3A3> <20><><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20>մϴ<D5B4>. <20><><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> Ȯ<><C8AE><EFBFBD><EFBFBD> <20><><EFBFBD>ڽ<EFBFBD><DABD>ϴ<EFBFBD>.
### 1<>ܰ<EFBFBD>: <20><> <20><><EFBFBD><EFBFBD>ȭ(Pinmux)<29><> <20><><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD> Ȯ<><C8AE> (<28><><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD> <20>ؾ<EFBFBD> <20><> <20><>)
<EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20>ٺ<EFBFBD>ġ <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><> <20><><EFBFBD><20>ִ<EFBFBD><D6B4><EFBFBD>, <20>ƴϸ<C6B4> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD> <20>ٲ<EFBFBD>ġ<EFBFBD><C4A1><EFBFBD>ߴ<EFBFBD><DFB4><EFBFBD> Ȯ<><C8AE><EFBFBD>ϴ<EFBFBD> <20><><EFBFBD><EFBFBD> <20>켱<EFBFBD>Դϴ<D4B4>.
1. **<2A><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20>ּ<EFBFBD> Ȯ<><C8AE>:** <20>ϵ<EFBFBD><CFB5><EFBFBD><EFBFBD><EFBFBD> <20>Ŵ<EFBFBD><C5B4>󿡼<EFBFBD> `GP1_20`<60><> **`GPSR` (General Purpose Select Register)**, **`PMR` (Peripheral Mode Register)** <20>ּҸ<D6BC> ã<><C3A3><EFBFBD><EFBFBD><EFBFBD><EFBFBD>. (<28><><EFBFBD><EFBFBD> `0xE606XXXX` <20><>ó<EFBFBD>Դϴ<D4B4>.)
2. **<2A><> <20>б<EFBFBD>:** TRACE32<33><32><EFBFBD><EFBFBD> <20>ش<EFBFBD> <20>ּҵ<D6BC><D2B5><EFBFBD> <20>о<D0BE><EEBAB8><EFBFBD><EFBFBD>.
* **GPSR:** GPIO <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> Ư<><C6AF> <20><>Ʈ<EFBFBD><C6AE> `1`<60>̾<EFBFBD><CCBE><EFBFBD> <20>մϴ<D5B4>.
* **PMR:** GPIO <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> Ư<><C6AF> <20><>Ʈ<EFBFBD><C6AE> `0`<60>̾<EFBFBD><CCBE><EFBFBD> <20>մϴ<D5B4>.
* <20><><EFBFBD><EFBFBD> <20><> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> GPIO <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20>ƴ϶<C6B4><CFB6><EFBFBD>, **<2A><><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> Ư<><C6AF> <20><><EFBFBD><EFBFBD><EFBFBD>̹<EFBFBD><CCB9><EFBFBD> <20><> <20><><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD>æ <20><><EFBFBD>Դϴ<D4B4>.**
### 2<>ܰ<EFBFBD>: <20><> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> Żȯ <20>׽<EFBFBD>Ʈ
<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD> Ȯ<><C8AE><EFBFBD><EFBFBD> <20><>, <20><> <20><><EFBFBD><EFBFBD> GPIO<49><4F> <20>ƴ϶<C6B4><CFB6><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> GPIO<49><4F> <20>ٲ㺸<D9B2><E3BAB8><EFBFBD><EFBFBD>.
1. **<2A><><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD>:** `Data.Set ASD:<3A>ּ<EFBFBD> %Long (GPIO <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>)`<60><><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>͸<EFBFBD> <20><><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EEBEB2><EFBFBD><EFBFBD>.
2. **<2A><><EFBFBD><EFBFBD> Ȯ<><C8AE>:** <20>̷<EFBFBD><CCB7><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20>ٲ<EFBFBD> <20><><EFBFBD>Ŀ<EFBFBD> <20><><EFBFBD>Ƿν<C7B7><CEBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> `GP1_20` <20><><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD>ϴ<EFBFBD><CFB4><EFBFBD> Ȯ<><C8AE><EFBFBD>ϼ<EFBFBD><CFBC><EFBFBD>.
* **<2A><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD>Ѵٸ<D1B4>?** -> <20><> <20><>ü<EFBFBD><C3BC> <20><><EFBFBD><EFBFBD><EFBFBD>Դϴ<D4B4>. <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> **<2A><><EFBFBD><EFBFBD> <20><> <20><> <20><><EFBFBD><EFBFBD> SSI <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD>ϴ<EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>/SSI <20><><EFBFBD><EFBFBD><EFBFBD>̹<EFBFBD>**<2A>Դϴ<D4B4>.
* **<2A><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><> <20><><EFBFBD>Ѵٸ<D1B4>?** -> **<2A>̰<EFBFBD> 100% <20>ϵ<EFBFBD><CFB5><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD>(<28>ٸ<EFBFBD> <20><><EFBFBD>ڰ<EFBFBD> <20><><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD>)<29>Դϴ<D4B4>.**
### 3<>ܰ<EFBFBD>: <20><><EFBFBD><EFBFBD>(<28><><EFBFBD><EFBFBD><EFBFBD>̹<EFBFBD>) ã<><C3A3> (Software Conflict)
<EFBFBD><EFBFBD><EFBFBD><EFBFBD> 2<>ܰ迡<DCB0><E8BFA1> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> GPIO<49><4F> <20>ٲ<EFBFBD><D9B2><EFBFBD><EFBFBD><EFBFBD> <20><>ȣ<EFBFBD><C8A3> <20><> <20><><EFBFBD><EFBFBD><EFBFBD>ٸ<EFBFBD>, <20><><EFBFBD><EFBFBD> <20><20><><EFBFBD><EFBFBD><EFBFBD>̹<EFBFBD><CCB9><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> ã<>ƾ<EFBFBD> <20>մϴ<D5B4>.
1. **<2A>α<EFBFBD> <20>м<EFBFBD>:** <20>ʱ<EFBFBD>ȭ(Initialization) <20>ܰ<EFBFBD><DCB0><EFBFBD> <20>α׸<CEB1> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>. `SSI`, `Audio`, Ȥ<><C8A4> `I2C` <20><><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD>̹<EFBFBD><CCB9><EFBFBD> <20>ε<EFBFBD><CEB5>Ǵ<EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><> <20><><EFBFBD><EFBFBD> <20>޽<EFBFBD><DEBD><EFBFBD><EFBFBD><EFBFBD> <20>ߴ<EFBFBD><DFB4><EFBFBD> Ȯ<><C8AE><EFBFBD>ϼ<EFBFBD><CFBC><EFBFBD>.
2. **<2A>ڵ<EFBFBD> <20>˻<EFBFBD>:** <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ʈ <20>ҽ<EFBFBD><D2BD>ڵ<EFBFBD> <20><>ü<EFBFBD><C3BC><EFBFBD><EFBFBD> `GP1_20` <20>Ǵ<EFBFBD> <20>ش<EFBFBD> <20>ɰ<EFBFBD> <20><><EFBFBD>õ<EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20≯<EFBFBD><CCB8><EFBFBD> <20>˻<EFBFBD><CBBB><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>. <20><20><><EFBFBD>Ͽ<EFBFBD><CFBF><EFBFBD> <20><> <20><><EFBFBD><EFBFBD> <20>ǵ帮<C7B5><E5B8AE> <20>ִ<EFBFBD><D6B4><EFBFBD> <20><><EFBFBD>ɴϴ<C9B4>.
---
### ?? <20><> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD> <20>켱<EFBFBD><ECBCB1><EFBFBD><EFBFBD> üũ<C3BC><C5A9><EFBFBD><EFBFBD>Ʈ
| <20>켱<EFBFBD><ECBCB1><EFBFBD><EFBFBD> | <20>׸<EFBFBD> | <20><><EFBFBD><EFBFBD> |
| --- | --- | --- |
| **1 (<28>ʼ<EFBFBD>)** | **PFC <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><> <20>б<EFBFBD>** | <20><><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD> <20><20><><EFBFBD><EFBFBD>(GPIO vs SSI)<29><><EFBFBD><EFBFBD> Ȯ<><C8AE> |
| **2 (<28>ʼ<EFBFBD>)** | **<2A><>Ÿ<EFBFBD><C5B8> <20><><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD>** | <20><><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><>ȣ<EFBFBD><C8A3> <20><> <20><> <20>ִ<EFBFBD><D6B4><EFBFBD> Ȯ<><C8AE> |
| **3 (<28><><EFBFBD><EFBFBD>)** | **<2A>ڵ<EFBFBD>/<2F><><EFBFBD><EFBFBD><EFBFBD>̹<EFBFBD> <20>ε<EFBFBD> <20><><EFBFBD><EFBFBD> Ȯ<><C8AE>** | <20><><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> Ȯ<><C8AE> |
<EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD> TRACE32<33><32> <20>Ѽ<EFBFBD> 1<>ܰ<EFBFBD>(<28><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><> <20>б<EFBFBD>)<29><><EFBFBD><EFBFBD> <20>غ<EFBFBD><D8BA><EFBFBD><EFBFBD><EFBFBD>.
<EFBFBD>ּҸ<EFBFBD> ã<><C3A3> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ø<EFBFBD>, <20><><EFBFBD><EFBFBD> <20><><EFBFBD>ô<EFBFBD> **<2A>ϵ<EFBFBD><CFB5><EFBFBD><EFBFBD><EFBFBD> <20>Ŵ<EFBFBD><C5B4><EFBFBD><EFBFBD><EFBFBD> 'Pin Function' ǥ<><C7A5> ĸó<C4B8>ؼ<EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD>ֽø<D6BD>** <20><><EFBFBD><EFBFBD> <20>ٷ<EFBFBD> <20>ּҸ<D6BC> ¤<><C2A4><EFBFBD>帮<EFBFBD>ڽ<EFBFBD><DABD>ϴ<EFBFBD>. <20><20><> <20><><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD> Ȯ<><C8AE><EFBFBD>ϱ<EFBFBD> <20><><EFBFBD>ϽŰ<CFBD><C5B0><EFBFBD>?
????<3F><>? <20>ܰ躰 <20><><EFBFBD>ͷ<EFBFBD>Ʈ <20><><EFBFBD><EFBFBD> (TRACE32 <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>)
1<EFBFBD>ܰ<EFBFBD>: "<22>ʹ<EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD> <20>ִ°<D6B4>?" (<28><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD> Ȯ<><C8AE>)
<EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD>, PMIC<49><43> <20><>ȣ<EFBFBD><C8A3> SoC <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ͱ<EFBFBD><CDB1><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD>ϴ<EFBFBD><CFB4><EFBFBD> <20><><EFBFBD><EFBFBD> <20>մϴ<D5B4>.
Ȯ<EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>: INDT4
<EFBFBD>׼<EFBFBD>: PMIC <20><> <20><>ȣ<EFBFBD><C8A3> <20><><EFBFBD><EFBFBD><EFBFBD>鼭 TRACE32<33><32> INDT4 <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>͸<EFBFBD> <20>ǽð<C7BD> <20><><EFBFBD><EFBFBD><EFBFBD>͸<EFBFBD><CDB8><EFBFBD> <20><><EFBFBD>ʽÿ<CABD>.
üũ<EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ʈ: 16<31><36> <20><>Ʈ<EFBFBD><C6AE> PMIC <20><>ȣ<EFBFBD><C8A3> <20><><EFBFBD><EFBFBD> 1<><31> 0<><30><EFBFBD><EFBFBD> <20>ĵ<EFBFBD>ġ<EFBFBD><C4A1> <20><><EFBFBD>մϱ<D5B4>?
<EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><> <20><><EFBFBD>Ѵٸ<D1B4>: INEN4 (Input Enable) <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> 16<31><36> <20><>Ʈ<EFBFBD><C6AE> 1(Ȱ<><C8B0>ȭ)<29><> <20>Ǿ<EFBFBD> <20>ִ<EFBFBD><D6B4><EFBFBD> Ȯ<><C8AE><EFBFBD>Ͻʽÿ<CABD>. <20>Է<EFBFBD> <20><><EFBFBD>۰<EFBFBD> <20><><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><>ȣ<EFBFBD><C8A3> <20><> <20>޽<EFBFBD><DEBD>ϴ<EFBFBD>.
2<EFBFBD>ܰ<EFBFBD>: "<22><> <20><><EFBFBD><EFBFBD> <20><><EFBFBD>ͷ<EFBFBD>Ʈ<EFBFBD><C6AE><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD>ߴ°<DFB4>?" (<28><><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD>)
<EFBFBD><EFBFBD>ȣ<EFBFBD><EFBFBD> INDT4<54>δ<EFBFBD> <20><> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>µ<EFBFBD> ISR<53><52> <20><> <20><><EFBFBD>ٸ<EFBFBD>, <20><><EFBFBD><EFBFBD><EFBFBD>ȱ<EFBFBD> <20><> <20>༮<EFBFBD><E0BCAE> <20><><EFBFBD><EFBFBD><EFBFBD>Դϴ<D4B4>.
Ȯ<EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>: IOINTSEL4
üũ<EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ʈ: 16<31><36> <20><>Ʈ<EFBFBD><C6AE> 1 (Interrupt Input Mode)<29><> <20><><EFBFBD><EFBFBD><EFBFBD>Ǿ<EFBFBD> <20>ֽ<EFBFBD><D6BD>ϱ<EFBFBD>?
<EFBFBD><EFBFBD><EFBFBD><EFBFBD> 0<>̶<EFBFBD><CCB6><EFBFBD>: SoC<6F><43> <20><> <20><><EFBFBD><EFBFBD> <20>ܼ<EFBFBD><DCBC><EFBFBD> '<27><><EFBFBD><EFBFBD> Ȯ<>ο<EFBFBD> GPIO'<27>θ<EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD>Ͽ<EFBFBD>, <20><><EFBFBD><EFBFBD> <20><><EFBFBD>ص<EFBFBD> <20><><EFBFBD>ͷ<EFBFBD>Ʈ <20><>Ʈ<EFBFBD>ѷ<EFBFBD><D1B7><EFBFBD> <20><>ȣ<EFBFBD><C8A3> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20>ʽ<EFBFBD><CABD>ϴ<EFBFBD>. <20>ݵ<EFBFBD><DDB5><EFBFBD> 1<><31> <20><><EFBFBD>õǾ<C3B5><C7BE><EFBFBD> <20>մϴ<D5B4>.
3<EFBFBD>ܰ<EFBFBD>: "<22><><EFBFBD>Ƽ<EFBFBD>(Trigger) <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20>´°<C2B4>?" (<28><><EFBFBD><EFBFBD>/<2F><><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD>)
PMIC<EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD> <20><>ȣ<EFBFBD><C8A3> Ư<><C6AF><EFBFBD><EFBFBD> SoC<6F><43> <20><><EFBFBD>ٸ<EFBFBD><D9B8><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><>ġ<EFBFBD>ؾ<EFBFBD> <20><><EFBFBD>Ƽ谡 <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ϴ<EFBFBD>.
Ȯ<EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>: EDGLEVEL4 <20><> POSNEG4
üũ<EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ʈ: PMIC<49><43> IRQ Ư<><C6AF><EFBFBD><EFBFBD> <20>°<EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD>Ǿ<EFBFBD><C7BE><EFBFBD><EFBFBD><EFBFBD> Ȯ<><C8AE><EFBFBD>Ͻʽÿ<CABD>.
Falling Edge (<28>ϰ<EFBFBD> <20><><EFBFBD><EFBFBD>) Ʈ<><C6AE><EFBFBD>Ŷ<EFBFBD><C5B6><EFBFBD>: EDGLEVEL4 = 1, POSNEG4 = 1
Low Level (<28>ο<EFBFBD> <20><><EFBFBD><EFBFBD>) Ʈ<><C6AE><EFBFBD>Ŷ<EFBFBD><C5B6><EFBFBD>: EDGLEVEL4 = 0, POSNEG4 = 1
4<EFBFBD>ܰ<EFBFBD>: "<22><><EFBFBD>Ƽ<EFBFBD><C6BC><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>µ<EFBFBD> <20><><EFBFBD><EFBFBD>ũ(Mask)<29><> <20><><EFBFBD><EFBFBD><EFBFBD>°<EFBFBD>?" (<28>÷<EFBFBD><C3B7><EFBFBD> Ȯ<><C8AE>)
<EFBFBD><EFBFBD>ȣ<EFBFBD><EFBFBD> <20>°<EFBFBD> <20><><EFBFBD>Ƽ<EFBFBD> <20><><EFBFBD>ǵ<EFBFBD> <20>¾Ҵٸ<D2B4>, GPIO <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD>ͷ<EFBFBD>Ʈ <20><><EFBFBD><EFBFBD>(Flag)<29><> <20><><EFBFBD><EFBFBD> <20>ø<EFBFBD><C3B8>ϴ<EFBFBD>.
Ȯ<EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>: INTDT4 <20><> INTMSK4
<EFBFBD>׼<EFBFBD>: PMIC <20><><EFBFBD>ͷ<EFBFBD>Ʈ<EFBFBD><C6AE> <20>߻<EFBFBD><DFBB><EFBFBD>Ų <20><> INTDT4<54><34> Ȯ<><C8AE><EFBFBD>Ͻʽÿ<CABD>.
üũ<EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ʈ 1 (INTDT4): 16<31><36> <20><>Ʈ<EFBFBD><C6AE> 1<><31> <20>ٲ<EFBFBD><D9B2><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ϱ<EFBFBD>? (1<><31> <20>ٲ<EFBFBD><D9B2><EFBFBD><EFBFBD>ٸ<EFBFBD> GPIO <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD>ͷ<EFBFBD>Ʈ<EFBFBD><C6AE> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD>Դϴ<D4B4>.)
üũ<EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ʈ 2 (INTMSK4): 16<31><36> <20><>Ʈ<EFBFBD><C6AE> 0 (Unmasked)<29>̾<EFBFBD><CCBE><EFBFBD> <20>մϴ<D5B4>. <20><><EFBFBD><EFBFBD> 1 (Masked)<29>̶<EFBFBD><CCB6><EFBFBD>, <20>ⲯ <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD>ͷ<EFBFBD>Ʈ<EFBFBD><C6AE> <20>ܺ<EFBFBD>(GIC)<29><> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20>ʰ<EFBFBD> <20><><EFBFBD><EFBFBD> Ʋ<><EFBFBD><EEB8B7> <20>ִ<EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD>Դϴ<D4B4>.
5<EFBFBD>ܰ<EFBFBD>: "GIC (Generic Interrupt Controller) <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD>" (<28><><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD>)
<EFBFBD><EFBFBD><EFBFBD><EFBFBD> 4<>ܰ<EFBFBD><DCB0><EFBFBD><EFBFBD><EFBFBD> <20><> Ȯ<><C8AE><EFBFBD>ؼ<EFBFBD> INTDT4<54><34> <20>÷<EFBFBD><C3B7>װ<EFBFBD> <20><><EFBFBD><EFBFBD>, INTMSK4<4B><34> <20><><EFBFBD><EFBFBD>ũ<EFBFBD><C5A9> Ǯ<><C7AE><EFBFBD>ִµ<D6B4> ISR<53><52> <20><> <20><><EFBFBD><EFBFBD><EFBFBD>´ٸ<C2B4>? <20>̰<EFBFBD> GPIO <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20>߸<EFBFBD><DFB8><EFBFBD> <20>ƴմϴ<D5B4>. GIC(<28><><EFBFBD>ͷ<EFBFBD>Ʈ <20><>Ʈ<EFBFBD>ѷ<EFBFBD>) <20><><EFBFBD><EFBFBD> <20>Ǵ<EFBFBD> OS/MCAL <20><><EFBFBD><EFBFBD> <20><><EFBFBD>̺<EFBFBD> <20><><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD>Դϴ<D4B4>.
GP4_16<EFBFBD><EFBFBD> <20>ش<EFBFBD><D8B4>ϴ<EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> SPI (Shared Peripheral Interrupt) <20><>ȣ<EFBFBD><C8A3> <20>ֽ<EFBFBD><D6BD>ϴ<EFBFBD>.
AUTOSAR(MCAL) <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><> <20><><EFBFBD>ͷ<EFBFBD>Ʈ<EFBFBD><C6AE> Cortex-R52 <20>ھ<EFBFBD><DABE><EFBFBD> <20>ùٸ<C3B9><D9B8><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>(GICD_IROUTER <20>Ǵ<EFBFBD> GICD_ITARGETSR) <20>ǵ<EFBFBD><C7B5><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD>Ǿ<EFBFBD><C7BE><EFBFBD><EFBFBD><EFBFBD>, <20>׸<EFBFBD><D7B8><EFBFBD> GIC <20>ܿ<EFBFBD><DCBF><EFBFBD> <20>ش<EFBFBD> <20><><EFBFBD>ͷ<EFBFBD>Ʈ<EFBFBD><C6AE> Enable(GICD_ISENABLER) <20>Ǿ<EFBFBD> <20>ִ<EFBFBD><D6B4><EFBFBD> Ȯ<><C8AE><EFBFBD>ؾ<EFBFBD> <20>մϴ<D5B4>.

26
Customer/MOBIS/PRK3_(ADAS_Parking3)/Issue/External IRQ/20260605_debug_code/Code.txt
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@@ -257,5 +257,31 @@ ISR(PMIC_HW_ISR_CAT2_ISR)
#endif #endif
} }
void XXXX_Init(void)
{
Port_PostInitGpioIntClearSequence(PORT1_BASE_ADDR ,GP1_20_BIT);
}
ISR(PMIC_HW_ISR_CAT2_ISR)
{
volatile PortReg_t* pPORT;
u32_PMIC_IRQ_Count_flag++;
#if (PMIC_IRQ_GP1_20_BIT == STD_ON)
pPORT = (volatile PortReg_t*)PORT1_BASE_ADDR;
if (pPORT->INTDTn & GP1_20_BIT)
{
u32_PMIC_IRQ_Count++;
pPORT->INTCLRn = GP1_20_BIT;
}
#endif
Port_PostInitGpioIntClearSequence(PORT1_BASE_ADDR ,GP1_20_BIT);
}

BIN
Datasheet/PMIC/PMIC_Memory_Map_수정중.xlsx Normal file
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