From eef0056485d2f4860875323ab1dc072e3a179d52 Mon Sep 17 00:00:00 2001 From: woody Date: Mon, 15 Jun 2026 15:14:21 +0900 Subject: [PATCH] update --- .../Code/ARMStartup_CortexR52.c_txt.txt | 905 ++++++++++++++++++ .../Code/ARMStartup_CortexR52.h_txt.txt | 395 ++++++++ .../ARMStartup_PlatformTemplate.h_txt.txt | 250 +++++ .../Issue/ECM_ERR/20260612_MTG.txt | 22 + .../Issue/External IRQ/20260528_IRQ디버깅.txt | 153 +++ .../External IRQ/20260605_debug_code/Code.txt | 26 + 6 files changed, 1751 insertions(+) create mode 100644 Customer/MOBIS/PRK3_(ADAS_Parking3)/Code/ARMStartup_CortexR52.c_txt.txt create mode 100644 Customer/MOBIS/PRK3_(ADAS_Parking3)/Code/ARMStartup_CortexR52.h_txt.txt create mode 100644 Customer/MOBIS/PRK3_(ADAS_Parking3)/Code/ARMStartup_PlatformTemplate.h_txt.txt create mode 100644 Customer/MOBIS/PRK3_(ADAS_Parking3)/Issue/ECM_ERR/20260612_MTG.txt create mode 100644 Customer/MOBIS/PRK3_(ADAS_Parking3)/Issue/External IRQ/20260528_IRQ디버깅.txt diff --git a/Customer/MOBIS/PRK3_(ADAS_Parking3)/Code/ARMStartup_CortexR52.c_txt.txt b/Customer/MOBIS/PRK3_(ADAS_Parking3)/Code/ARMStartup_CortexR52.c_txt.txt new file mode 100644 index 00000000..4d3f9b1e --- /dev/null +++ b/Customer/MOBIS/PRK3_(ADAS_Parking3)/Code/ARMStartup_CortexR52.c_txt.txt @@ -0,0 +1,905 @@ +/********************************************************************************************************************** + * COPYRIGHT + * ------------------------------------------------------------------------------------------------------------------- + * \verbatim + * Copyright (c) 2024 by Vector Informatik GmbH. All rights reserved. + * + * This software is copyright protected and proprietary to Vector Informatik GmbH. + * Vector Informatik GmbH grants to you only those rights as set out in the license conditions. + * All other rights remain with Vector Informatik GmbH. + * \endverbatim + * ------------------------------------------------------------------------------------------------------------------- + * FILE DESCRIPTION + * -----------------------------------------------------------------------------------------------------------------*/ +/** \file File: ARMStartup_CortexR52.c + * Project: Vector Basic Runtime System + * Module: BrsHw for all platforms with ARM core Cortex-R52 + * Template: This file is reviewed according to Brs_Template@Implementation[1.03.09] + * + * \brief Description: This file contains the assembler part of the BRS StartUpCode. + * + * \attention Please note: + * The demo and example programs only show special aspects of the software. With regard to the fact + * that these programs are meant for demonstration purposes only, Vector Informatik liability shall be + * expressly excluded in cases of ordinary negligence, to the extent admissible by law or statute. + *********************************************************************************************************************/ + +/********************************************************************************************************************** + * REVISION HISTORY + * ------------------------------------------------------------------------------------------------------------------- + * Refer to ARMBrsHw_CortexR52.h. + *********************************************************************************************************************/ + +/********************************************************************************************************************** + * EXAMPLE CODE ONLY + * ------------------------------------------------------------------------------------------------------------------- + * This Example Code is only intended for illustrating an example of a possible BSW integration and BSW configuration. + * The Example Code has not passed any quality control measures and may be incomplete. The Example Code is neither + * intended nor qualified for use in series production. The Example Code as well as any of its modifications and/or + * implementations must be tested with diligent care and must comply with all quality requirements which are necessary + * according to the state of the art before their use. + *********************************************************************************************************************/ + +#define ARMSTARTUP_CORTEXR52_SOURCE + +/********************************************************************************************************************** + * INCLUDES + *********************************************************************************************************************/ +#include "BrsHw.h" + +#if defined (BRS_FIRST_EXECUTION_INSTANCE) +/* This code is only needed for the first instance/executable in the system */ + +#include "vBrs_Lcfg.h" +#include "vLinkGen_Lcfg.h" +#include "ARMStartup_Platform.h" +#include "ARMStartup_CortexR52.h" + +/********************************************************************************************************************** + * CONFIGURATION CHECK + *********************************************************************************************************************/ +#if defined (BRS_COMP_ARM6) + +#else + #error "Unknown compiler specified!" +#endif + +#if (VLINKGEN_CFG_MAJOR_VERSION != 2u) + #error "This StartUpCode is dependent to the vLinkGen version! vLinkGen major version does not fit!" +#else +# if (VLINKGEN_CFG_MINOR_VERSION < 5u) + #error "This StartUpCode is dependent to the vLinkGen version! Your vLinkGen minor version is too old!" +# endif +#endif + +/********************************************************************************************************************** + * DEFINITION + MACROS + *********************************************************************************************************************/ + + + +extern void intvect_CoreExceptions(void); + +/********************************************************************************************************************** + * PROTOTYPES OF LOCAL FUNCTIONS + *********************************************************************************************************************/ +BRS_LOCAL_PROTOTYPE(_start) +BRS_LOCAL_PROTOTYPE(brsStartupEntry) +BRS_LOCAL_PROTOTYPE(brsFirstCoreInit) +BRS_LOCAL_PROTOTYPE(brsStartupZeroInitLoop) +BRS_LOCAL_PROTOTYPE(brsStartupStackSearch) +BRS_LOCAL_PROTOTYPE(coreRegisterInit) +BRS_LOCAL_PROTOTYPE(coreRegisterInit2) +BRS_LOCAL_PROTOTYPE(coreRegisterInit3) +BRS_LOCAL_PROTOTYPE(stackPointerInit) +BRS_LOCAL_PROTOTYPE(brsInitialMPUconfig) + +#if (BRS_ENABLE_HYPERVISOR_MODE_HANDLING == STD_ON) +/* =========================================================================== */ +/* */ +/* Description: Entry point for all cores in Hypervisor mode */ +/* */ +/* =========================================================================== */ +# if (BRS_SET_T32_ENTRY_POINT == STD_ON) + BRS_THUMB_SECTION() /* Exception entry in T32 mode */ +# endif + +BRS_SECTION_CODE(brsStartupHyp) + BRS_GLOBAL(brsStartupEntryHyp) +BRS_MULTILINE_ASM_BEGIN() +BRS_LABEL(brsStartupEntryHyp) + +/* Enhanced register initialization */ + __as1(MOV r0, #0) + __as1(MOV r1, #0) + __as1(MOV r2, #0) + __as1(MOV r3, #0) + __as1(MOV r4, #0) + __as1(MOV r5, #0) + __as1(MOV r6, #0) + __as1(MOV r7, #0) + __as1(MOV r8, #0) + __as1(MOV r9, #0) + __as1(MOV r10, #0) + __as1(MOV r11, #0) + __as1(MOV r12, #0) + __as1(MOV lr, #0) + +/* Switch to SVC mode with enhanced error checking */ + __as1(MRS r0, CPSR) /* Read CPSR Register */ + __as1(LDR r1, =MODE_SVC) + __as3(BFI r0, r1, #0, #5) /* Update CPSR Register */ +# if (BRS_SET_T32_ENTRY_POINT == STD_ON) + __as2(ORR r0, r0, #(0x1 << 5)) /* Set T bit */ +# endif + __as1(MSR SPSR_hyp, r0) /* Write SPSR Register */ + +/* Set initial vector table with proper barriers */ + __as1(LDR r0, =CR_START_ADDRESS) + __as5(MCR p15, #0, r0, c12, c0, #0) /* Write to VBAR */ + ___asm(DSB) /* Ensure VBAR write completion */ + ___asm(ISB) /* Flush instruction pipeline */ + +/* =========================================================================== */ +/* Enhanced MPU Configuration - Table 6.9 ROM Boot Memory Map Compliant */ +/* Optimized for Exception Vector Table and Multi-core Systems */ +/* =========================================================================== */ + +/* Step 1: Disable MPU with proper synchronization */ + __as5(MRC p15, #0, r0, c1, c0, #0) /* Read SCTLR */ + __as2(BIC r0, r0, #0x1) /* Clear MPU enable bit */ + __as5(MCR p15, #0, r0, c1, c0, #0) /* Write SCTLR */ + ___asm(DSB) + ___asm(ISB) + +/* Step 2: Enhanced MAIR configuration for multi-core and ECC support */ +/* MAIR0 - Memory Attribute Indirection Register 0 */ +__as1(LDR r0, =0x00BB0444) /* MAIR0: Attr0=0x44, Attr1=0x04, Attr2=0xBB, Attr3=0x00 */ +__as5(MCR p15, #0, r0, c10, c2, #0) /* Write MAIR0 */ + +/* MAIR1 - Extended attributes for specialized memory types */ +__as1(LDR r0, =0x00000000) /* MAIR1: All attributes 0 */ +__as5(MCR p15, #0, r0, c10, c2, #1) /* Write MAIR1 */ + +/* Critical: Memory barriers after MAIR configuration */ +___asm(DSB) +___asm(ISB) + +/* Step 3: MPU Region Configuration - Non-overlapping Design */ + +/* Region 0: Reserved for AUTOSAR OS Exception Vectors - Will be enabled by OS */ + __as1(MOV r0, #0) + __as5(MCR p15, #0, r0, c6, c2, #1) + __as1(MOV r0, #0) + __as5(MCR p15, #0, r0, c6, c3, #0) + __as1(MOV r0, #0) + __as5(MCR p15, #0, r0, c6, c3, #1) +___asm(DSB) +___asm(ISB) + +/* Region 1: Reserved for AUTOSAR OS - Disabled */ + __as1(MOV r0, #1) + __as5(MCR p15, #0, r0, c6, c2, #1) + __as1(MOV r0, #0) + __as5(MCR p15, #0, r0, c6, c3, #0) + __as1(MOV r0, #0) + __as5(MCR p15, #0, r0, c6, c3, #1) +___asm(DSB) +___asm(ISB) + +/* Region 2: Reserved for AUTOSAR OS - Disabled */ + __as1(MOV r0, #2) + __as5(MCR p15, #0, r0, c6, c2, #1) + __as1(MOV r0, #0) + __as5(MCR p15, #0, r0, c6, c3, #0) + __as1(MOV r0, #0) + __as5(MCR p15, #0, r0, c6, c3, #1) +___asm(DSB) +___asm(ISB) + +/* Region 3: Low Memory Range (0x00000000 - 0x3FFFFFFF) - 1GB */ +__as1(MOV r0, #3) +__as5(MCR p15, #0, r0, c6, c2, #1) +__as1(LDR r0, =0x00000000) + __as2(ORR r0, r0, #0x03) /* XN=1, AP=00(RW), SH=00 (Non-shareable) */ +__as5(MCR p15, #0, r0, c6, c3, #0) +__as1(LDR r0, =0x3FFFFFC0) +__as2(ORR r0, r0, #0x01) /* AttrIdx=0 (Non-cacheable), EN=1 */ +__as5(MCR p15, #0, r0, c6, c3, #1) +___asm(DSB) +___asm(ISB) + +/* Region 4: Complete CODE section (0x40100000 - 0x404FFFFF) - 4MB */ +/* CRITICAL: Execute-Permitted, Read-Only for ALL, Inner-shareable for Vector AUTOSAR */ +__as1(MOV r0, #4) +__as5(MCR p15, #0, r0, c6, c2, #1) +__as1(LDR r0, =0x40100000) /* Base includes Exception Vector Tables */ +__as2(ORR r0, r0, #0x02) /* XN=0(Execute-never), AP=0b01(Read/write, at any privilege level), SH=0b10 (Outer-shareable) */ +__as5(MCR p15, #0, r0, c6, c3, #0) +__as1(LDR r0, =0x404FFFC0) /* Covers all code sections and exception vectors */ +__as2(ORR r0, r0, #0x05) /* AttrIdx=2 (Normal WT), EN=1 */ +__as5(MCR p15, #0, r0, c6, c3, #1) +___asm(DSB) +___asm(ISB) + +/* Region 5: Device Memory (0xC0000000 - 0xDFFFFFFF) - 512MB */ +/* FIXED: Device memory should be Outer-shareable for proper hardware access */ +__as1(MOV r0, #5) +__as5(MCR p15, #0, r0, c6, c2, #1) +__as1(LDR r0, =0xC0000000) + __as2(ORR r0, r0, #0x02) /* XN=0, AP=01(RW), SH=00 */ +__as5(MCR p15, #0, r0, c6, c3, #0) +__as1(LDR r0, =0xDFFFFFC0) +__as2(ORR r0, r0, #0x03) /* AttrIdx=1(Device-nGnRnE), EN=1 */ +__as5(MCR p15, #0, r0, c6, c3, #1) +___asm(DSB) +___asm(ISB) + +/* Region 6: Normal Memory (0xE0000000 - 0xE3FFFFFF) - 64MB */ +/* FIXED: Inner-shareable for multi-core data consistency */ +__as1(MOV r0, #6) +__as5(MCR p15, #0, r0, c6, c2, #1) +__as1(LDR r0, =0xE0000000) + __as2(ORR r0, r0, #0x02) /* XN=0, AP=01(RW), SH=00 */ +__as5(MCR p15, #0, r0, c6, c3, #0) +__as1(LDR r0, =0xE3FFFFC0) +__as2(ORR r0, r0, #0x01) /* AttrIdx=0(Non-cacheable), EN=1 */ +__as5(MCR p15, #0, r0, c6, c3, #1) +___asm(DSB) +___asm(ISB) + +/* Region 7: Realtime Core TCM Memory (0xE4000000 - 0xE4BFFFFF) - 12MB */ +__as1(MOV r0, #7) +__as5(MCR p15, #0, r0, c6, c2, #1) /* Select region 7 */ +__as1(LDR r0, =0xE4000000) /* Base = 0xE4000000 */ +__as2(ORR r0, r0, #0x02) /* XN=0, AP=01(RW), SH=00 (Non-shareable) */ +__as5(MCR p15, #0, r0, c6, c3, #0) /* Set base/attr */ +__as1(LDR r0, =0xE4BFFFC0) /* Limit = 0xE4BFFFFF */ +__as2(ORR r0, r0, #0x01) /* AttrIdx=0(Non-cacheable), EN=1 */ +__as5(MCR p15, #0, r0, c6, c3, #1) /* Set limit/enable */ +___asm(DSB) +___asm(ISB) + +/* Region 8: Device Memory (0xE5000000 - 0xE62FFFFF) - ~19MB */ +/* FIXED: Device memory with Outer-shareable */ +__as1(MOV r0, #8) +__as5(MCR p15, #0, r0, c6, c2, #1) +__as1(LDR r0, =0xE5000000) + __as2(ORR r0, r0, #0x02) /* XN=1, AP=00(RW), SH=00 */ +__as5(MCR p15, #0, r0, c6, c3, #0) +__as1(LDR r0, =0xE62FFFC0) +__as2(ORR r0, r0, #0x03) /* AttrIdx=1(Device-nGnRnE), EN=1 */ +__as5(MCR p15, #0, r0, c6, c3, #1) +___asm(DSB) +___asm(ISB) + +/* Region 9: V4H SystemRAM (0xE6300000 - 0xE63FFFFF) - 1MB */ +/* FIXED: Corrected AP and shareable settings for multi-core shared memory */ +__as1(MOV r0, #9) +__as5(MCR p15, #0, r0, c6, c2, #1) +__as1(LDR r0, =0xE6300000) +__as2(ORR r0, r0, #0x03) /* XN=1(Execute-always), AP=0b01(Read/write, at any privilege level), SH=0b10 (Outer-shareable) */ +__as5(MCR p15, #0, r0, c6, c3, #0) +__as1(LDR r0, =0xE63FFFC0) +__as2(ORR r0, r0, #0x01) /* AttrIdx=0(Non-cacheable), EN=1 */ +__as5(MCR p15, #0, r0, c6, c3, #1) +___asm(DSB) +___asm(ISB) + +/* Region 10: Device Memory (0xE6400000 - 0xEB0FFFFF) - ~76MB */ +/* FIXED: Device memory with Non-shareable (recommended for device registers) */ +__as1(MOV r0, #10) +__as5(MCR p15, #0, r0, c6, c2, #1) +__as1(LDR r0, =0xE6400000) +__as2(ORR r0, r0, #0x03) /* XN=1, AP=00(RW), SH=00 (Non-shareable) - FIXED */ +__as5(MCR p15, #0, r0, c6, c3, #0) +__as1(LDR r0, =0xEB0FFFC0) +__as2(ORR r0, r0, #0x03) /* AttrIdx=1(Device-nGnRnE), EN=1 */ +__as5(MCR p15, #0, r0, c6, c3, #1) +___asm(DSB) +___asm(ISB) + +/* Region 11: Normal Memory (0xEB100000 - 0xEB127FFF) - 160KB */ +__as1(MOV r0, #11) +__as5(MCR p15, #0, r0, c6, c2, #1) +__as1(LDR r0, =0xEB100000) + __as2(ORR r0, r0, #0x02) /* XN=0, AP=00(RW), SH=00 */ +__as5(MCR p15, #0, r0, c6, c3, #0) +__as1(LDR r0, =0xEB127FC0) +__as2(ORR r0, r0, #0x01) /* AttrIdx=0(Non-cacheable), EN=1 */ +__as5(MCR p15, #0, r0, c6, c3, #1) +___asm(DSB) +___asm(ISB) + +/* Region 12: Device Memory (0xEB128000 - 0xEB1FFFFF) - ~864KB */ +/* FIXED: Device memory with Outer-shareable */ +__as1(MOV r0, #12) +__as5(MCR p15, #0, r0, c6, c2, #1) +__as1(LDR r0, =0xEB128000) + __as2(ORR r0, r0, #0x03) /* XN=1, AP=00(RW), SH=00 */ +__as5(MCR p15, #0, r0, c6, c3, #0) +__as1(LDR r0, =0xEB1FFFC0) +__as2(ORR r0, r0, #0x03) /* AttrIdx=1(Device-nGnRnE), EN=1 */ +__as5(MCR p15, #0, r0, c6, c3, #1) +___asm(DSB) +___asm(ISB) + +/* Region 13: Normal Memory (0xEB200000 - 0xEB2FFFFF) - 1MB */ +/* FIXED: Inner-shareable for multi-core consistency */ +__as1(MOV r0, #13) +__as5(MCR p15, #0, r0, c6, c2, #1) +__as1(LDR r0, =0xEB200000) + __as2(ORR r0, r0, #0x02) /* XN=0, AP=00(RW), SH=00 */ +__as5(MCR p15, #0, r0, c6, c3, #0) +__as1(LDR r0, =0xEB2FFFC0) +__as2(ORR r0, r0, #0x05) /* AttrIdx=2(Normal WT), EN=1 */ +__as5(MCR p15, #0, r0, c6, c3, #1) +___asm(DSB) +___asm(ISB) + +/* Region 14: Device Memory (0xEB300000 - 0xFFFFFFFF) - ~320MB */ +/* FIXED: Device memory with Outer-shareable */ +__as1(MOV r0, #14) +__as5(MCR p15, #0, r0, c6, c2, #1) +__as1(LDR r0, =0xEB300000) + __as2(ORR r0, r0, #0x03) /* XN=1, AP=00(RW), SH=00 */ +__as5(MCR p15, #0, r0, c6, c3, #0) +__as1(LDR r0, =0xFFFFFFC0) +__as2(ORR r0, r0, #0x03) /* AttrIdx=1(Device-nGnRnE), EN=1 */ +__as5(MCR p15, #0, r0, c6, c3, #1) +___asm(DSB) +___asm(ISB) + +/* Region 15: DATA section (0x40500000 - 0x405FFFFF) - 1MB */ +/* FIXED: Read-Write for all modes, Execute-Never, Inner-shareable */ +__as1(MOV r0, #15) +__as5(MCR p15, #0, r0, c6, c2, #1) +__as1(LDR r0, =0x40500000) +__as2(ORR r0, r0, #0x02) /* XN=0(Execute-never), AP=0b01(Read/write, at any privilege level), SH=0b10 (Outer-shareable) */ +__as5(MCR p15, #0, r0, c6, c3, #0) +__as1(LDR r0, =0x405FFFC0) +__as2(ORR r0, r0, #0x05) /* AttrIdx=2(Normal WT), EN=1 */ +__as5(MCR p15, #0, r0, c6, c3, #1) +___asm(DSB) +___asm(ISB) + +/* Region 16: FINAL FIX - Vector AUTOSAR System Mode compatible */ +__as1(MOV r0, #16) +__as5(MCR p15, #0, r0, c6, c2, #1) +__as1(LDR r0, =0x40700000) +__as2(ORR r0, r0, #0x02) /* XN=0(Execute-never), AP=0b01(Read/write, at any privilege level), SH=0b10 (Outer-shareable) */ +__as5(MCR p15, #0, r0, c6, c3, #0) +__as1(LDR r0, =0x409FFFC0) +__as2(ORR r0, r0, #0x05) /* AttrIdx=2(Normal WT), EN=1 */ +__as5(MCR p15, #0, r0, c6, c3, #1) +___asm(DSB) +___asm(ISB) + +/* Region 17: Extended memory (0x80000000 - 0xBFFFFFFF) - 1GB */ +/* FIXED: Read-Write for all modes, Execute-Permitted, Inner-shareable */ +__as1(MOV r0, #17) +__as5(MCR p15, #0, r0, c6, c2, #1) +__as1(LDR r0, =0x80000000) +__as2(ORR r0, r0, #0x02) /* XN=0, AP=00, SH=00 */ +__as5(MCR p15, #0, r0, c6, c3, #0) +__as1(LDR r0, =0xBFFFFFC0) +__as2(ORR r0, r0, #0x05) /* AttrIdx=2(Normal WT), EN=1 */ +__as5(MCR p15, #0, r0, c6, c3, #1) +___asm(DSB) +___asm(ISB) + +/* Region 18: Unused - Disabled */ + __as1(MOV r0, #18) /* Region ID = 18 */ + __as5(MCR p15, #0, r0, c6, c2, #1) /* Select region 18 */ + __as1(MOV r0, #0) /* Base address = 0 */ + __as5(MCR p15, #0, r0, c6, c3, #0) /* Write PRBAR */ + __as1(MOV r0, #0) /* Limit address = 0, Enable=0 (Disabled) */ + __as5(MCR p15, #0, r0, c6, c3, #1) /* Write PRLAR (EN=0, region disabled) */ + ___asm(DSB) + ___asm(ISB) + +/* Region 19: Unused - Disabled */ + __as1(MOV r0, #19) /* Region ID = 19 */ + __as5(MCR p15, #0, r0, c6, c2, #1) /* Select region 19 */ + __as1(MOV r0, #0) /* Base address = 0 */ + __as5(MCR p15, #0, r0, c6, c3, #0) /* Write PRBAR */ + __as1(MOV r0, #0) /* Limit address = 0, Enable=0 (Disabled) */ + __as5(MCR p15, #0, r0, c6, c3, #1) /* Write PRLAR (EN=0, region disabled) */ + ___asm(DSB) + ___asm(ISB) + +/* Region 20: Unused - Disabled */ + __as1(MOV r0, #20) /* Region ID = 20 */ + __as5(MCR p15, #0, r0, c6, c2, #1) /* Select region 20 */ + __as1(MOV r0, #0) /* Base address = 0 */ + __as5(MCR p15, #0, r0, c6, c3, #0) /* Write PRBAR */ + __as1(MOV r0, #0) /* Limit address = 0, Enable=0 (Disabled) */ + __as5(MCR p15, #0, r0, c6, c3, #1) /* Write PRLAR (EN=0, region disabled) */ + ___asm(DSB) + ___asm(ISB) + +/* Region 21: Unused - Disabled */ + __as1(MOV r0, #21) /* Region ID = 21 */ + __as5(MCR p15, #0, r0, c6, c2, #1) /* Select region 21 */ + __as1(MOV r0, #0) /* Base address = 0 */ + __as5(MCR p15, #0, r0, c6, c3, #0) /* Write PRBAR */ + __as1(MOV r0, #0) /* Limit address = 0, Enable=0 (Disabled) */ + __as5(MCR p15, #0, r0, c6, c3, #1) /* Write PRLAR (EN=0, region disabled) */ + ___asm(DSB) + ___asm(ISB) + +/* Region 22: Unused - Disabled */ + __as1(MOV r0, #22) /* Region ID = 22 */ + __as5(MCR p15, #0, r0, c6, c2, #1) /* Select region 22 */ + __as1(MOV r0, #0) /* Base address = 0 */ + __as5(MCR p15, #0, r0, c6, c3, #0) /* Write PRBAR */ + __as1(MOV r0, #0) /* Limit address = 0, Enable=0 (Disabled) */ + __as5(MCR p15, #0, r0, c6, c3, #1) /* Write PRLAR (EN=0, region disabled) */ + ___asm(DSB) + ___asm(ISB) + +/* Region 23: Unused - Disabled */ + __as1(MOV r0, #23) /* Region ID = 23 */ + __as5(MCR p15, #0, r0, c6, c2, #1) /* Select region 23 */ + __as1(MOV r0, #0) /* Base address = 0 */ + __as5(MCR p15, #0, r0, c6, c3, #0) /* Write PRBAR */ + __as1(MOV r0, #0) /* Limit address = 0, Enable=0 (Disabled) */ + __as5(MCR p15, #0, r0, c6, c3, #1) /* Write PRLAR (EN=0, region disabled) */ + ___asm(DSB) + ___asm(ISB) + +BRS_READ_COREID(R1) + +__as1(MOV r3, #0) /* Default value */ +__as1(CMP r1, #0) +__as1(LDREQ r3, =CR0_ATCM_BASE) /* Core 0 */ +__as1(CMP r1, #1) +__as1(LDREQ r3, =CR1_ATCM_BASE) /* Core 1 */ +__as1(CMP r1, #2) +__as1(LDREQ r3, =CR2_ATCM_BASE) /* Core 2 */ + +__as1(MOV r4, #3) /* 0x3: Full access (Privileged + User) */ +__as5(MCR p15, #0, r4, c11, c0, #0) /* Write to IMP_SLAVEPCTLR */ +___asm(DSB) +___asm(ISB) + +__as1(MOV r4, #0) +__as1(LDR r5, =0xFFFFE000) +__as2(AND r6, r3, r5) +__as2(ORR r4, r4, r6) +__as2(ORR r4, r4, #0x18) /* SIZE=6 (0b00110 << 2 = 0x18) */ +__as2(ORR r4, r4, #3) /* Enable ATCM access from EL2, EL1, and EL0 */ +__as5(MCR p15, #0, r4, c9, c1, #0) /* Write to CP15 ATCM Region Register */ +___asm(DSB) +___asm(ISB) + +/* Step 5: Enable L1 caches with proper sequencing */ + __as5(MRC p15, #0, r0, c1, c0, #0) + __as2(ORR r0, r0, #(0x1 << 2)) /* Set C bit (D-cache enable) */ + __as2(ORR r0, r0, #(0x1 << 12)) /* Set I bit (I-cache enable) */ + __as5(MCR p15, #0, r0, c1, c0, #0) + ___asm(DSB) + ___asm(ISB) + +/* Step 6: Enable MPU background region */ + __as5(MRC p15, #0, r0, c1, c0, #0) /* Read SCTLR */ + __as2(ORR r0, r0, #(0x1 << 17)) /* Set background region enable bit */ + __as5(MCR p15, #0, r0, c1, c0, #0) /* Write SCTLR */ + ___asm(DSB) + ___asm(ISB) + +/* Step 7: Enable MPU */ + __as5(MRC p15, #0, r0, c1, c0, #0) /* Read SCTLR */ + __as2(ORR r0, r0, #0x1) /* Set MPU enable bit */ + __as5(MCR p15, #0, r0, c1, c0, #0) /* Write SCTLR */ + ___asm(DSB) + ___asm(ISB) + +/* Step 8: Configure Generic Timer */ +/* Enable Generic Timer access for EL1 and EL0 */ + __as5(MRC p15, #4, r0, c14, c1, #0) /* Read CNTHCTL */ + __as2(ORR r0, r0, #0x3) /* EL1PCTEN | EL1PCEN */ + __as5(MCR p15, #4, r0, c14, c1, #0) /* Write CNTHCTL */ + +/* Set Generic Timer frequency for R-Car */ + __as1(LDR r0, =0xFE4FE8) /* R-Car timer frequency: 16,658,408 Hz */ + __as5(MCR p15, #0, r0, c14, c0, #0) /* Write CNTFRQ */ + + __as1(MOV lr, r10) /* Restore return address */ + +/* Memory barriers to ensure MPU configuration takes effect */ + ___asm(DSB) + ___asm(ISB) + + __as1(LDR r0, =EL1_VectorTable) /* Load entry label */ + __as1(MSR ELR_hyp, r0) /* Set the link register */ + ___asm(DSB) + ___asm(ISB) + ___asm(ERET) /* Trigger EL1 level */ + +# if defined (BRS_COMP_ARM6) + ___asm(.align 4) +# else + ___asm(.align 0x20) +# endif + + BRS_GLOBAL(EL1_VectorTable) +BRS_LABEL(EL1_VectorTable) /* Temporary Interrupt Vector Table */ + __as1(LDR PC, EL1_Reset_Addr) + __as1(LDR PC, EL1_Unhandled_Addr) + __as1(LDR PC, EL1_Unhandled_Addr) + __as1(LDR PC, EL1_Unhandled_Addr) + __as1(LDR PC, EL1_Unhandled_Addr) + __as1(LDR PC, EL1_Unhandled_Addr) + __as1(LDR PC, EL1_Unhandled_Addr) + __as1(LDR PC, EL1_Unhandled_Addr) + + ___asm(EL1_Reset_Addr: .word brsStartupEntry) + ___asm(EL1_Unhandled_Addr: .word EL1_Unhandled_Handler) + +BRS_LABEL(EL1_Unhandled_Handler) + ___asm(B EL1_Unhandled_Handler) + +BRS_MULTILINE_ASM_END() +BRS_GLOBAL_END() +#endif /*BRS_ENABLE_HYPERVISOR_MODE_HANDLING*/ + +/* =========================================================================== */ +/* */ +/* Description: Entry point for all cores in EL1 mode */ +/* */ +/* =========================================================================== */ +/* Alternativ entry point from OS default config */ + BRS_GLOBAL(_start) +BRS_MULTILINE_ASM_BEGIN() +BRS_LABEL(_start) +BRS_MULTILINE_ASM_END() +BRS_GLOBAL_END() + +#if (BRS_SET_T32_ENTRY_POINT == STD_ON) + BRS_THUMB_SECTION() /* Exception entry in T32 mode */ +#endif + +BRS_SECTION_CODE(brsStartup) + BRS_GLOBAL(brsStartupEntry) +BRS_MULTILINE_ASM_BEGIN() +BRS_LABEL(brsStartupEntry) + +#if ((BRS_CPU_CORE_AMOUNT>1) && defined (BRSHW_CORE_START_PATTERN)) + BRS_READ_COREID(R0) + BRS_BRANCH_EQUAL(R0,#BRSHW_INIT_CORE_ID,EL1_Startup_Entry) + __as1(LDR R6, =BRSHW_CORE_START_PATTERN) + __as1(LDR R7, =BrsHw_CoreStart) + __as1(MOV R8, R0) + __as2(LSL R8, R8, #2) + __as2(ADD R7, R7, R8) + BRS_LABEL(coreWaitLoop) + __as1(LDR R8, [R7]) /* Load sync variable */ + BRS_BRANCH_NOT_EQUAL(R6,R8,coreWaitLoop) /* If sync pattern is not present, loop again */ + + BRS_BRANCH_NOT_EQUAL(R0,#BRSHW_INIT_CORE_ID,clearStartPattern) + + BRS_LABEL(clearStartPattern) + __as1(MOV R8, #0) + __as1(STR R8, [R7]) /* Clear sync pattern */ + + BRS_LABEL(EL1_Startup_Entry) +#endif /*BRS_CPU_CORE_AMOUNT>1&&BRSHW_CORE_START_PATTERN*/ + +#if defined (BRSHW_PRE_ASM_STARTUP_HOOK_AVAILABLE) +/* =========================================================================== */ +/* */ +/* Description: Optional hook for platform specific tasks */ +/* */ +/* =========================================================================== */ +# if defined (BRS_COMP_ARM6) + BRS_BRANCH(brsPreAsmStartupHook) +# endif +#endif + + BRS_GLOBAL(brsFirstCoreInit) +BRS_MULTILINE_ASM_BEGIN() +BRS_LABEL(brsFirstCoreInit) + BRS_BRANCH(brsInitialMPUconfig) +BRS_MULTILINE_ASM_END() +BRS_GLOBAL_END() + +/* =========================================================================== */ +/* */ +/* Description: Initial configuration of MPU regions */ +/* */ +/* =========================================================================== */ + BRS_GLOBAL(brsInitialMPUconfig) +BRS_MULTILINE_ASM_BEGIN() +BRS_LABEL(brsInitialMPUconfig) + BRS_BRANCH(coreRegisterInit) +BRS_MULTILINE_ASM_END() +BRS_GLOBAL_END() + +/* =========================================================================== */ +/* */ +/* Description: Initialize core ID independent core registers */ +/* */ +/* =========================================================================== */ + BRS_GLOBAL(coreRegisterInit) +BRS_MULTILINE_ASM_BEGIN() +BRS_LABEL(coreRegisterInit) + BRS_BRANCH(coreRegisterInit2) +BRS_MULTILINE_ASM_END() +BRS_GLOBAL_END() + +/* =========================================================================== */ +/* */ +/* Description: Initialize all core ID dependent core registers */ +/* Setup VBAR to program entry address */ +/* */ +/* =========================================================================== */ + BRS_GLOBAL(coreRegisterInit2) +BRS_MULTILINE_ASM_BEGIN() +BRS_LABEL(coreRegisterInit2) + + /* Initialize stack for SVC */ + //ldr r0, .svc_stack + //mov sp, r0 + + /* Set EL1 Vectors */ + __as1(LDR R2, =EL1_VectorTable) + __as5(MCR p15, #0, r2, c12, c0, #0) + + /* Disable forwarding interrupt */ + __as1(MOV r0, #0) + __as5(MRC p15, #0, r0, c12, c12, #7) + + BRS_BRANCH(brsStartupZeroInitLoop) +BRS_MULTILINE_ASM_END() +BRS_GLOBAL_END() + +/* =========================================================================== */ +/* */ +/* Description: Initialize memory blocks and groups with zero */ +/* */ +/* =========================================================================== */ + BRS_GLOBAL(brsStartupZeroInitLoop) +BRS_MULTILINE_ASM_BEGIN() +BRS_LABEL(brsStartupZeroInitLoop) + + BRS_READ_COREID(R0) + +/* Initialize memory sections blocks with zeros */ +#if defined (VLINKGEN_CFG_NUM_ZERO_INIT_EARLY_BLOCKS) +# if (VLINKGEN_CFG_NUM_ZERO_INIT_EARLY_BLOCKS>1uL) + __as1(LDR R1, =vLinkGen_ZeroInit_Early_Blocks) + +BRS_LABEL(startup_block_zero_init_start) + __as1(MOV R2, R1) + __as2(ADD R1, R1, #16) + __as1(LDR R3, [R2]) /* vLinkGen_ZeroInit_Early_Blocks->start */ + __as2(LDR R4, [R2, #4]) /* vLinkGen_ZeroInit_Early_Blocks->end */ + __as2(LDR R5, [R2, #8]) /* vLinkGen_ZeroInit_Early_Blocks->core */ + __as2(LDR R6, [R2, #12]) /* vLinkGen_ZeroInit_Early_Blocks->alignment */ + +/* Verify if the end of struct vLinkGen_ZeroInit_Early_Blocks is reached, by checking if start == 0, end == 0 and core == 0 */ + __as1(MOV R7, #0) + + __as2(ORR R7, R7, R3) /* Or with vLinkGen_ZeroInit_Early_Blocks->start */ + __as2(ORR R7, R7, R4) /* Or with vLinkGen_ZeroInit_Early_Blocks->end */ + __as2(ORR R7, R7, R5) /* Or with vLinkGen_ZeroInit_Early_Blocks->core */ + + BRS_BRANCH_EQUAL(R7, #0, startup_block_zero_init_end) /* If start address, end address and core are equal to zero -> Finished */ + BRS_BRANCH_NOT_EQUAL(R0, R5, startup_block_zero_init_start) /* If InitCore is not running -> go to the next array entry */ + + __as1(MOV R7, #0) /* set R7 to '0', as value to write in memory later */ + __as1(MOV R8, #0) /* set R8 to '0', as value to write in memory later */ + BRS_BRANCH_EQUAL(R6, #8, startup_block_zero_init_8byte_loop_start) /* if block is 8-Byte aligned, use specific init loop */ + +BRS_LABEL(startup_block_zero_init_loop_start) + BRS_BRANCH_GREATER_THAN_OR_EQUAL(R3, R4, startup_block_zero_init_start) /* if start address is same with or higher than end address-> Finished. */ + __as1(STR R7, [R3]) /* write value of R7 ('0') to address of R3 (4-byte access); must be an aligned memory access! */ + __as2(ADD R3, R3, #4) /* increase address value of R3 by '4' */ + +/* End address of this block was not yet reached. Run through the loop again */ + BRS_BRANCH(startup_block_zero_init_loop_start) + +/* ================================================================ */ +/* 8-Byte aligned initialization, to support 8-Byte aligned ECC RAM */ +/* ================================================================ */ +BRS_LABEL(startup_block_zero_init_8byte_loop_start) + BRS_BRANCH_GREATER_THAN_OR_EQUAL(R3, R4, startup_block_zero_init_start) /* if start address is same with or higher than end address-> Finished. */ + +/* Address stored in R3 must be 8 Byte aligned at this point! */ + __as2(STMIA R3!, {R7, R8}) /* 8 Byte alignment store for ECC, R3 would be automatically updated after the write */ + +/* End address of this block was not yet reached. Run through the loop again */ + BRS_BRANCH(startup_block_zero_init_8byte_loop_start) + +/* Zero-Init loop of blocks end label */ +BRS_LABEL(startup_block_zero_init_end) +# endif /*VLINKGEN_CFG_NUM_ZERO_INIT_EARLY_BLOCKS>1uL*/ + +#else + #error "Mandatory define VLINKGEN_CFG_NUM_ZERO_INIT_EARLY_BLOCKS missing within vLinkGen configuration!" +#endif /*VLINKGEN_CFG_NUM_ZERO_INIT_EARLY_BLOCKS*/ + +/* Initialize memory sections groups with zeros */ +#if defined (VLINKGEN_CFG_NUM_ZERO_INIT_EARLY_GROUPS) +# if (VLINKGEN_CFG_NUM_ZERO_INIT_EARLY_GROUPS>1uL) + __as1(LDR R1, =vLinkGen_ZeroInit_Early_Groups) + +BRS_LABEL(startup_group_zero_init_start) + __as1(MOV R2, R1) + __as2(ADD R1, R1, #16) + __as1(LDR R3, [R2]) /* vLinkGen_ZeroInit_Early_Groups->start */ + __as2(LDR R4, [R2, #4]) /* vLinkGen_ZeroInit_Early_Groups->end */ + __as2(LDR R5, [R2, #8]) /* vLinkGen_ZeroInit_Early_Groups->core */ + __as2(LDR R6, [R2, #12]) /* vLinkGen_ZeroInit_Early_Groups->alignment */ + +/* Verify if the end of struct vLinkGen_ZeroInit_Early_Groups is reached, by checking if start == 0, end == 0 and core == 0 */ + __as1(MOV R7, #0) + + __as2(ORR R7, R7, R3) /* Or with vLinkGen_ZeroInit_Early_Groups->start */ + __as2(ORR R7, R7, R4) /* Or with vLinkGen_ZeroInit_Early_Groups->end */ + __as2(ORR R7, R7, R5) /* Or with vLinkGen_ZeroInit_Early_Groups->core */ + + BRS_BRANCH_EQUAL(R7, #0, startup_group_zero_init_end) /* If start address, end address and core are equal to zero -> Finished */ + BRS_BRANCH_NOT_EQUAL(R0, R5, startup_group_zero_init_start) /* If InitCore is not running -> go to the next array entry */ + + __as1(MOV R7, #0) /* set R7 to '0', as value to write in memory later */ + __as1(MOV R8, #0) /* set R8 to '0', as value to write in memory later */ + BRS_BRANCH_EQUAL(R6, #8, startup_group_zero_init_8byte_loop_start) /* if group is 8-Byte aligned, use specific init loop */ + +BRS_LABEL(startup_group_zero_init_loop_start) + BRS_BRANCH_GREATER_THAN_OR_EQUAL(R3, R4, startup_group_zero_init_start) /* if start address is same with or higher than end address-> Finished. */ + + __as1(STR R7, [R3]) /* write value of R7 ('0') to address of R3 (4-byte access); must be an aligned memory access! */ + __as2(ADD R3, R3, #4) /* increase address value of R3 by '4' */ + +/* End address of this group was not yet reached. Run through the loop again */ + BRS_BRANCH(startup_group_zero_init_loop_start) + +/* ================================================================ */ +/* 8-Byte aligned initialization, to support 8-Byte aligned ECC RAM */ +/* ================================================================ */ +BRS_LABEL(startup_group_zero_init_8byte_loop_start) + BRS_BRANCH_GREATER_THAN_OR_EQUAL(R3, R4, startup_group_zero_init_start) /* if start address is same with or higher than end address-> Finished. */ + +/* Address stored in R3 must be 8 Byte aligned at this point! */ + __as2(STMIA R3!, {R7, R8}) /* 8 Byte alignment store for ECC, R3 would be automatically updated after the write */ + +/* End address of this group was not yet reached. Run through the loop again */ + BRS_BRANCH(startup_group_zero_init_8byte_loop_start) + +/* Zero-Init loop of groups end label */ +BRS_LABEL(startup_group_zero_init_end) +# endif /*VLINKGEN_CFG_NUM_ZERO_INIT_EARLY_GROUPS>1uL*/ + +#else + #error "Mandatory define VLINKGEN_CFG_NUM_ZERO_INIT_EARLY_GROUPS missing within vLinkGen configuration!" +#endif /*VLINKGEN_CFG_NUM_ZERO_INIT_EARLY_GROUPS*/ + +/* Jump to routine to search for valid startup stack pointer of actual running core */ + BRS_BRANCH(brsStartupStackSearch) +BRS_MULTILINE_ASM_END() +BRS_GLOBAL_END() + +/* =========================================================================== */ +/* */ +/* Description: Search for valid startup stack pointer of actual running core */ +/* (vBRS is genearing the core specific configuration into the */ +/* struct BrsMain_CoreConfig in vBrs_Lcfg.c) */ +/* */ +/* =========================================================================== */ + BRS_GLOBAL(brsStartupStackSearch) +BRS_MULTILINE_ASM_BEGIN() +BRS_LABEL(brsStartupStackSearch) + + __as1(LDR R1, =BrsMain_CoreConfig_Size) + +BRS_LABEL(core_config_size_init) + __as1(LDR R5, [R1]) /* R5 = BrsMain_CoreConfig_Size */ + + BRS_READ_COREID(R0) + + __as1(LDR R1, =BrsMain_CoreConfig) + +BRS_LABEL(core_config_init_start) + +/* Use R2 as count register in the loop. Initialize with zero. */ +#if defined (BRS_COMP_ARM6) + __as1(MOV R2, 0) +#else + __as1(MOV R2, #0) +#endif + +BRS_LABEL(brs_coreconfig_loop) + + __as2(LDR R4, [R1,#4]) /* BrsMain_CoreConfig->PhysicalCoreId */ +/* Check if core id (R0) matches to physical core id of BrsMain_CoreConfig entry (R4). */ + BRS_BRANCH_EQUAL(R0, R4, stackPointerInit) + +/* Increase count register by one. */ +#if defined (BRS_COMP_ARM6) + __as2(ADD R2, R2, 1) +#else + __as2(ADD R2, R2, #1) +#endif + +/* Set R1 to point to next entry of BrsMain_CoreConfig. */ +#if defined (BRS_COMP_ARM6) + __as2(ADD R1, R1, 28) +#else + __as2(ADD R1, R1, #28) +#endif + +/* Check if end of BrsMain_CoreConfig has been reached. */ + BRS_BRANCH_NOT_EQUAL(R2, R5, brs_coreconfig_loop) + +BRS_MULTILINE_ASM_END() + +/* Branch to BrsMainExceptionStartup if there are no more entries in the array. */ + BRS_EXTERN_BRANCH(BrsMainExceptionStartup) +BRS_GLOBAL_END() + +/* =========================================================================== */ +/* */ +/* Description: Initialize all core registers of actual running core with */ +/* specific init values */ +/* */ +/* =========================================================================== */ + BRS_GLOBAL(stackPointerInit) +BRS_MULTILINE_ASM_BEGIN() +BRS_LABEL(stackPointerInit) + __as2(LDR R0, [R1,#8]) /* BrsMain_CoreConfig->StartupStackEndLabel */ +/* Initialize stack pointers for different modes */ + ___asm(CPS #MODE_ABT) + __as1(MOV SP, r0) + ___asm(CPS #MODE_IRQ) + __as2(SUB r0, r0, #MODE_STACK_SIZE) + __as1(MOV SP, r0) + ___asm(CPS #MODE_FIQ) + __as2(SUB r0, r0, #MODE_STACK_SIZE) + __as1(MOV SP, r0) + ___asm(CPS #MODE_UNDEF) + __as2(SUB r0, r0, #MODE_STACK_SIZE) + __as1(MOV SP, r0) + ___asm(CPS #MODE_SVC) + __as2(SUB r0, r0, #MODE_STACK_SIZE) + __as1(MOV SP, r0) + ___asm(CPS #MODE_SYS) + __as2(SUB r0, r0, #MODE_STACK_SIZE) + __as1(MOV SP, r0) + + BRS_BRANCH(coreRegisterInit3) + +BRS_MULTILINE_ASM_END() +BRS_GLOBAL_END() + +/* =========================================================================== */ +/* */ +/* Description: Initialize additional core registers */ +/* */ +/* =========================================================================== */ + BRS_GLOBAL(coreRegisterInit3) +BRS_MULTILINE_ASM_BEGIN() +BRS_LABEL(coreRegisterInit3) +BRS_MULTILINE_ASM_END() + +/* =========================================================================== */ +/* */ +/* Description: Jump to Brs_PreMainStartup() (BrsMainStartup.c) */ +/* */ +/* =========================================================================== */ + BRS_EXTERN_BRANCH(Brs_PreMainStartup) + +/* =========================================================================== */ +/* */ +/* Description: Jump to BrsMainExceptionStartup() in case of an unexpected */ +/* return from PreMain/main */ +/* */ +/* =========================================================================== */ + BRS_EXTERN_BRANCH(BrsMainExceptionStartup) + +BRS_GLOBAL_END() + +#endif /*BRS_FIRST_EXECUTION_INSTANCE*/ + + \ No newline at end of file diff --git a/Customer/MOBIS/PRK3_(ADAS_Parking3)/Code/ARMStartup_CortexR52.h_txt.txt b/Customer/MOBIS/PRK3_(ADAS_Parking3)/Code/ARMStartup_CortexR52.h_txt.txt new file mode 100644 index 00000000..7a1e7ab9 --- /dev/null +++ b/Customer/MOBIS/PRK3_(ADAS_Parking3)/Code/ARMStartup_CortexR52.h_txt.txt @@ -0,0 +1,395 @@ +/********************************************************************************************************************** + * COPYRIGHT + * ------------------------------------------------------------------------------------------------------------------- + * \verbatim + * Copyright (c) 2024 by Vector Informatik GmbH. All rights reserved. + * + * This software is copyright protected and proprietary to Vector Informatik GmbH. + * Vector Informatik GmbH grants to you only those rights as set out in the license conditions. + * All other rights remain with Vector Informatik GmbH. + * \endverbatim + * ------------------------------------------------------------------------------------------------------------------- + * FILE DESCRIPTION + * -----------------------------------------------------------------------------------------------------------------*/ +/** \file File: ARMBrsHw_CortexR52.h + * Project: Vector Basic Runtime System + * Module: BrsHw for all platforms with ARM core Cortex-R52 + * + * \brief Description: This is a global, platform-independent header file for the ARM-BRS. + * This file includes all non-platform dependent functions. + * All the (platform depending) rest needs to be defined in BrsHw.c + * + * \attention Please note: + * The demo and example programs only show special aspects of the software. With regard to the fact + * that these programs are meant for demonstration purposes only, Vector Informatik liability shall be + * expressly excluded in cases of ordinary negligence, to the extent admissible by law or statute. + *********************************************************************************************************************/ + +/********************************************************************************************************************** + * REVISION HISTORY + * ------------------------------------------------------------------------------------------------------------------- + * Version Date Author Change Id Description + * ------------------------------------------------------------------------------------------------------------------- + * 01.00.00 2020-09-23 vismun Initial version with GHS, GNU and HIGHTEC compilers + * 01.01.00 2020-11-02 visbwa Added support for Arm6 compiler, removed AUTHOR IDENTITY + * 01.01.01 2020-12-17 visrgm Added disabling for Thumb mode exceptions in ARMStartup_CortexR52.c + * 01.01.02 2021-01-14 visbwa Fixed BRANCH to brsDisableMpuRegionsLoopStart and startup_block_zero_init_loop_start + * for ARM compilers in ARMStartup_CortexR52.c + * 01.02.00 2021-02-02 vismaa Added BrsHw_GetCore() from StellarS6 BrsHW implementation + * vismun Extended BrsHw_GetCore() implementation to be generic + * 2021-03-10 visbwa update to Brs_Template 1.02.00, moved revision history of all .c and .h files into + * ARMBrsHw_CortexR52.h, added SingleCore stubs for Read_COREID (always return 0), + * fixed branches to stack pointer init routines for MultiCore in ARMStartup_CortexR52.c + * 01.02.01 2021-03-18 visbwa Added check for BRSHW_NUM_CORES_PER_DOMAIN into ARMBrsHw_CortexR52.c + * 01.02.02 2021-03-18 vismaa Memory initialization process changed with vLinkGen vLinkGen_xxx_Blocks + * 01.02.03 2022-03-09 visbwa ESCAN00111447 Fixed zero_init loops in ARMStartup_CortexR52.c, renamed area_zero_init to group_zero_init, + * introduced BRS_BRANCH_GREATER_THAN_OR_EQUAL, added support for 8 byte aligned ECC initialization, + * fixed BrsHwDisableInterruptAtPowerOn() for Arm6 compiler + * 01.02.04 2022-03-11 visrgm Fixed alignment for GNU compiler and usage of MODE_SYS in ARMStartup_CortexR52.c + * 01.02.05 2022-03-14 visbwa ESCAN00111482 StartupCode is not mapped into specific section "brsStartup" for Arm6 compiler (ARMStartup_CortexR52.c) + * ESCAN00111483 StartupCode is using ARM_LIB_STACK instead of STACK_C0 to initialize stackpointer during startup (ARMStartup_CortexR.c), + * removed unused BRS_SECTION_DATA fragments from some compiler abstractions + * 01.03.00 2022-04-22 vishci Added LlvmHightec compiler support + * 01.03.01 2022-05-23 vishci Bugfix whithin BRS_SECTION_CODE LlvmHightec compiler + * 02.00.00 2022-03-22 visjhr Update to Brs_Template 1.03.04 + * 2022-05-23 visbwa Removed fragments of several not supported compilers, fixed LlvmHightec support, + * fixed encapsulation of _start (alternative start symbol for OS) + * 2022-06-28 virrlu Small fixes in StartupCode + * 02.00.01 2022-07-06 visbwa Reverted changed MPU settings in StartupCode + * 02.00.02 2022-08-04 visbwa Fixed LlvmHightec support in ARMBrsHwIntTb_CortexR52.c, Brs_Template 1.03.05 + * 02.01.00 2022-10-18 visbwa Introduction of BRS_ENABLE_HYPERVISOR_MODE_HANDLING + * 2022-10-19 xchen Introduction of BRS_THUMB_SECTION macro for thumb section; bugfix in entry point for + * all cores in EL1 mode and in brsStartupStackSearch (ARMStartup_CortexR52.c) + * 02.01.01 2022-10-28 xchen Clear TE bit in SCTLR_EL1 for all cores in EL1 and ARM mode (ARMStartup_CortexR52.c) + * 02.01.02 2022-11-28 xchen Added support for multicore platforms, where all cores are autostart (all cores, + * except the boot core, are halted at startup until the start pattern was set) + * 02.02.00 2022-01-19 visrgm Added support for implementation of brsPreAsmStartupHook in ARMStartup_CortexR52.c + * 2023-02-24 visbwa ESCAN00113944 Linking of brsExcVect and brsExcVectRam in ARMBrsHwIntTb_CortexR52.c not working with Arm6 compiler -> better use Brs_MemMap.h, + * introduction of BRS_MEMMAP_INLINE_ASSEMBLER_USED (needed for GHS compiler) + * 02.02.01 2023-03-03 visbwa Changed default memory attribute indirection registers in startup code from + * wright-through to non-cachable, to allow usage of DMA controllers (e.g. for DrvEth) + * 02.02.02 2023-05-16 visdri Clear SCTLR.TE bit in startup code to enter Exc in ARM mode even when compiling in Thumb mode + * 02.03.00 2023-05-23 visbwa Update to Brs_Template 1.03.09: mapping of BrsHw_CoreExceptionHandler() into startup + * code section in ARMBrsHwIntTb_CortexR52.c + * 02.04.00 2023-06-13 visbwa Added support for compiler GccNxp, changed BRS_READ_COREID macro fur multicore, + * updated description of brsTcmBase in ARMStartup_Platform.h and ARMStartup_CortexR52.c + * 02.05.00 2023-06-15 visrgm HALBE-9624 Changed ExceptionTable mechanism to use LDR + * 02.05.01 2023-10-19 vissgj BASEENV-10091 Modified the memory access register MAIR0 for peripheral access in ARMStartup_CortexR52.c to no Early Write Acknowledgement + * (to solve issues with access to CAN peripheral, occured on StellarSr6 platform) + * 02.05.02 2024-02-28 visbwa Added clearing of pending data abort exceptions in ARMStartup_CortexR52.c + * 2024-03-04 visqli Fixed GccNXP compiler error because of missing prefix(#) in StartupCode assembler + * 02.05.03 2024-03-07 visbwa Fixed additional GccNXP compiler error because of missing prefix(#) in StartupCode assembler + *********************************************************************************************************************/ + +#ifndef _ARMBRSHW_CORTEXR52_H_ +#define _ARMBRSHW_CORTEXR52_H_ + +/********************************************************************************************************************** + * MODULE VERSION + *********************************************************************************************************************/ +/* + * Description: This is the BrsHw main and bug fix version. The version numbers are BCD coded. + * E.g. a main version of 1.23 is coded with 0x0123, a bug fix version of 9 is coded 0x09. + */ +#define ARMBRSHW_CORTEXR52_VERSION 0x0205u +#define ARMBRSHW_CORTEXR52_BUGFIX_VERSION 0x03u + +/********************************************************************************************************************** + * INCLUDES + *********************************************************************************************************************/ +/* + * Description: The BrsCfg header is used to configure different types of + * tests and system setups. Therefore it must be included first + * in each BRS and test module. + * This file is part of the BRS. + */ +#include "vBrsCfg.h" + +#include "BrsMain.h" + +/********************************************************************************************************************** + * CONFIGURATION CHECK + *********************************************************************************************************************/ +/* Configuration checks performed within platform specific code (BrsHw) */ + +/********************************************************************************************************************** + * GLOBAL CONSTANT MACROS + *********************************************************************************************************************/ +/* + * Description: Macro for access to IO addresses + */ +#define BRSHW_IOS(type, address) (*((volatile type *)(address))) + +#define BRSHWNOP10() do { \ + __asm(" NOP"); \ + __asm(" NOP"); \ + __asm(" NOP"); \ + __asm(" NOP"); \ + __asm(" NOP"); \ + __asm(" NOP"); \ + __asm(" NOP"); \ + __asm(" NOP"); \ + __asm(" NOP"); \ + __asm(" NOP"); \ + } while(0) + +/* CPU modes */ +#define MODE_FIQ 0x11 +#define MODE_IRQ 0x12 +#define MODE_SVC 0x13 +#define MODE_MON 0x16 +#define MODE_ABT 0x17 +#define MODE_UNDEF 0x1B +#define MODE_SYS 0x1F +#define MODE_STACK_SIZE 0x40 + +/* GICv3 Distributor (GICD) */ +#define GICD_BASE brsHwGetImpCbar() +#define GICD_IGROUPR(n) BRSHW_IOS(uint32, GICD_BASE + 0x0080 + (4u * n)) /* n= [1:30] */ +#define GICD_ISENABLER(n) BRSHW_IOS(uint32, GICD_BASE + 0x0100 + (4u * n)) /* n= [1:30] */ +#define GICD_ICENABLER(n) BRSHW_IOS(uint32, GICD_BASE + 0x0180 + (4u * n)) /* n= [1:30] */ +#define GICD_ISPENDR(n) BRSHW_IOS(uint32, GICD_BASE + 0x0200 + (4u * n)) /* n= [1:30] */ +#define GICD_ICPENDR(n) BRSHW_IOS(uint32, GICD_BASE + 0x0280 + (4u * n)) /* n= [1:30] */ +#define GICD_IPRIORITYR(n) BRSHW_IOS(uint32, GICD_BASE + 0x0400 + (4u * n)) /* n= [8:247] */ +#define GICD_IROUTER(n) BRSHW_IOS(uint64, GICD_BASE + 0x6000 + (8u * n)) /* n= [32:991 */ + +/* GICv3 Reistributor for SGIs and PPIs (GICR) */ +#define GICR_BASE(n) (GICD_BASE + 0x110000ul + (0x20000ul * n)) /* n= [0:3] */ +#define GICR_IGROUP0(n) BRSHW_IOS(uint32, GICR_BASE(n) + 0x0080) +#define GICR_ISENABLER0(n) BRSHW_IOS(uint32, GICR_BASE(n) + 0x0100) +#define GICR_ICENABLER0(n) BRSHW_IOS(uint32, GICR_BASE(n) + 0x0180) +#define GICR_ISPENDR0(n) BRSHW_IOS(uint32, GICR_BASE(n) + 0x0200) +#define GICR_ICPENDR0(n) BRSHW_IOS(uint32, GICR_BASE(n) + 0x0280) +#define GICR_IPRIORITYR(n, m) BRSHW_IOS(uint32, GICR_BASE(n) + 0x0400 + (4u * m)) /* n= [0:7] */ + +/* Read Core Id. */ +#if (BRS_CPU_CORE_AMOUNT>1) + #define BRS_READ_COREID(c) \ + __asm( "MRC p15, 0, r0, c0, c0, 5 \n" \ + "AND r1, r0, #0xFF00 \n" \ + "LDR r2, =0x08 \n" \ + "LSR r1, r1, r2" ); \ + __as1(LDR r2, =BRSHW_NUM_CORES_PER_DOMAIN) \ + __asm( "MUL r1, r1, r2 \n" \ + "AND r0, r0, #0xF \n" \ + "ADD r0, r0, r1" ); + +#else + /* Stub for SingleCore environments, always returns 0 */ + #define BRS_READ_COREID(c) __as1(MOV c, 0) +#endif /*BRS_CPU_CORE_AMOUNT*/ + +/* + * Description: Macros used in vBRS generated vBrs_Lcfg.c. + */ +#if defined (BRS_COMP_ARM6) +# if defined (BRS_ENABLE_FBL_SUPPORT) + #define _Brs_ExcVectRam_START Image$$Brs_ExcVectRam$$Base + + /* Special value, needed for SingleCore UseCase w/o OS (e.g. FBL). vBRS will generate "BRSHW_DEFINE_STARTUP_STACK(BRSHW_INIT_CORE_ID)" + for this. Configure here the valid value for the StartupStack pointer label of the boot core */ + #define BRSHW_DEFINE_STARTUP_STACK(BRSHW_INIT_CORE_ID) Image$$STACK_C0$$Limit + +# else + #define BRSHW_DEFINE_STARTUP_STACK(x) Image$$STACK_C##x##$$Limit +# endif + + /* No separate ExcVec table on cortexR! OS is defining one interrupt table for exceptions + interrupts */ + #define BRSHW_DEFINE_EXCVEC(x) Image$$OS_EXCVEC_CORE##x##_CODE$$Base + #define BRSHW_DEFINE_INTVEC(x) Image$$OS_EXCVEC_CORE##x##_CODE$$Base /* just as dummy to compile vBrs_Lcfg.c, not used in BrsHw_ExceptionTable_Init() */ + +#else + #define BRSHW_DEFINE_STARTUP_STACK(x) _STACK_C##x##_LIMIT + + /* No separate ExcVec table on cortexR! OS is defining one interrupt table for exceptions + interrupts */ + #define BRSHW_DEFINE_EXCVEC(x) _OS_EXCVEC_CORE##x##_CODE_START + #define BRSHW_DEFINE_INTVEC(x) _OS_EXCVEC_CORE##x##_CODE_START /* just as dummy to compile vBrs_Lcfg.c, not used in BrsHw_ExceptionTable_Init() */ +#endif /*BRS_COMP_x*/ + +/* Special value, needed for SingleCore UseCase w/o OS (e.g. FBL). vBRS will generate "BRSHW_DEFINE_STARTUP_STACK(BRSHW_INIT_CORE_ID)" + for this. Configure here the valid value for the StartupStack pointer label of the boot core */ +#define _STACK_CBRSHW_INIT_CORE_ID_LIMIT _STACK_C0_LIMIT /* this macro is not used with Arm6 compiler */ + +/********************************************************************************************************************** + * Compiler abstraction + *********************************************************************************************************************/ +#if defined (BRS_COMP_ARM6) + #define ___asm(c) __asm_(c) + #define __asm_(c) __asm(#c); + #define __as1(c, d) __as1_(c, d) + #define __as1_(c, d) __asm( #c " , " #d); + #define __as2(c, d, e) __as2_(c, d, e) + #define __as2_(c, d, e) __asm( #c " , " #d " , " #e); + #define __as3(c, d, e, f) __as3_(c, d, e, f) + #define __as3_(c, d, e, f) __asm( #c " , " #d " , " #e " , " #f); + #define __as4(c, d, e, f, g) __as4_(c, d, e, f, g) + #define __as4_(c, d, e, f, g) __asm( #c " , " #d " , " #e " , " #f " , " #g); + #define __as5(c, d, e, f, g, h) __as5_(c, d, e, f, g, h) + #define __as5_(c, d, e, f, g, h) __asm( #c " , " #d " , " #e " , " #f " , " #g " , " #h); + + #define BRS_MULTILINE_ASM_BEGIN() + #define BRS_MULTILINE_ASM_END() + + #define BRS_ASM_EQU(Label, Value) __as1(.equ Label, Value) + + #define BRS_ISR_KEYWORD __attribute__ ((interrupt("IRQ"))) + +# if defined (BRS_COMP_ARM6) + /* vLinkGen is not using the dot in front of the section names */ + #define BRS_SECTION_CODE(c) __as1(.section c , "ax" ) +# else + #define BRS_SECTION_CODE(c) __as1(.section .c , "ax" ) +# endif + + #define BRS_GLOBAL(c) ___asm(.globl c) + #define BRS_LOCAL_PROTOTYPE(c) void c (void); + #define BRS_LABEL(c) ___asm(c:) + #define BRS_GLOBAL_END() + + /* Unconditional branch to c */ + #define BRS_BRANCH(c) ___asm(B c) + #define BRS_EXTERN_BRANCH(c) ___asm(B c) + + /* Branch to e if c and d are equal */ + #define BRS_BRANCH_EQUAL(c,d,e) __as1(CMP c, d) \ + ___asm(BEQ e) + + /* Branch to e if c and d are NOT equal */ + #define BRS_BRANCH_NOT_EQUAL(c,d,e) __as1(CMP c, d) \ + ___asm(BNE e) + + /* Branch to e if c is greater than d*/ + #define BRS_BRANCH_GREATER_THAN(c,d,e) __as1(CMP c, d) \ + ___asm(BGT e) + + /* Branch to e if c is greater or equal than d */ + #define BRS_BRANCH_GREATER_THAN_OR_EQUAL(c,d,e) __as1(CMP c, d) \ + ___asm(BGE e) + + /* Defines a thumb section */ + #define BRS_THUMB_SECTION() ___asm(.thumb_func) + + /* Multiprocessor affinity (MPIDR) */ + static inline uint32 brsHwGetMpidr(void) + { + uint32 val; + __asm__ volatile( " MRC p15, 0, %0, c0, c0, 5 " + : "=r" (val) + : + : ); + return val; + } + + /* Configuration Base Address Register (IMP_CBAR). */ + static inline uint32 brsHwGetImpCbar(void) + { + uint32 val; + __asm__ volatile( " MRC p15, 1, %0, c15, c3, 0 " + : "=r" (val) + : + : ); + return val; + } + +#else + #error "Compiler not yet supported" +#endif /*BRS_COMP_x*/ + +/********************************************************************************************************************** + * BrsHW configuration + *********************************************************************************************************************/ + +/********************************************************************************************************************** + * GLOBAL VARIABLES + *********************************************************************************************************************/ + +/********************************************************************************************************************** + * GLOBAL FUNCTION PROTOTYPES + *********************************************************************************************************************/ + +/*****************************************************************************/ +/* @brief Disable the global system interrupt. + * @pre Must be the first function call in main@BrsMain + * @param[in] - + * @param[out] - + * @return - + * @context Function is called from main@BrsMain at power on initialization + *****************************************************************************/ +void BrsHwDisableInterruptAtPowerOn(void); + +/*****************************************************************************/ +/* @brief Program the vector table base addresses + * @pre - + * @param[in] ExcVecLabel - address of the core exception table + * IntVecLabel - address of the interrupt vector table + * Use BRS_DEFINE_ADDRESS_UNUSED for unused values + * @param[out] - + * @return - + * @context Function is called from main@BrsMain at power on initialization + *****************************************************************************/ +void BrsHw_ExceptionTable_Init(Brs_AddressOfConstType, Brs_AddressOfConstType); + +/*****************************************************************************/ +/* @brief This API is used for the BRS time measurement support to get a + * default time value for all measurements with this platform to + * be able to compare time measurements on different dates based + * on this time result. + * @pre Should be called with interrupts global disabled + * @param[in] - + * @param[out] - + * @return - + * @context Function is called from e.g. component testsuits for calibration + *****************************************************************************/ +void BrsHwTime100NOP(void); + +/*****************************************************************************/ +/* @brief This API is used to read the core ID of the actual running core + * @pre - + * @param[in] - + * @param[out] - + * @return Core ID of the actual running core + * @context Function is e.g. called from main@BrsMain, to only call HW-init + * code once, on the boot core. + * In MultiCore setups, BRSHW_INIT_CORE_ID and + * BRSHW_NUM_CORES_PER_DOMAIN must be declared inside BrsHw.h to + * configure the proper core ID value of boot core and to + * define numbers of cores/domain respectively. + *****************************************************************************/ +uint32 BrsHw_GetCore(void); + +/*****************************************************************************/ +/* @brief This API is used to enable an interrupt source in the core + * interrupt controller. + * @pre - + * @param[in] Source to be enabled on GIC controller (0 <= Source <= 991). + * @param[in] Priority level to be set. + * @param[out] - + * @return - + * @context Function is called from HlpTest and other test environments. + *****************************************************************************/ +void BrsHw_EnableInterrupt(uint32, uint8); + +/*****************************************************************************/ +/* @brief This API is used to disable an interrupt source in the core + * interrupt controller. + * @pre - + * @param[in] Source to be disabled on GIC controller (0 <= Source <= 991). + * @param[out] - + * @return - + * @context Function is called from HlpTest and other test environments. + *****************************************************************************/ +void BrsHw_DisableInterrupt(uint32); + +/*****************************************************************************/ +/* @brief This API is used to trigger the given software interrupt source. + * @pre + * @param[in] Source to be triggered (0 <= Source <= 991). + * @param[out] - + * @return - + * @context Function is called from HlpTest and other test environments. + *****************************************************************************/ +void BrsHw_TriggerSoftwareInterrupt(uint32); + +#endif /*_ARMBRSHW_CORTEXR52_H_*/ + + \ No newline at end of file diff --git a/Customer/MOBIS/PRK3_(ADAS_Parking3)/Code/ARMStartup_PlatformTemplate.h_txt.txt b/Customer/MOBIS/PRK3_(ADAS_Parking3)/Code/ARMStartup_PlatformTemplate.h_txt.txt new file mode 100644 index 00000000..fbf1c2cb --- /dev/null +++ b/Customer/MOBIS/PRK3_(ADAS_Parking3)/Code/ARMStartup_PlatformTemplate.h_txt.txt @@ -0,0 +1,250 @@ +/********************************************************************************************************************** + * COPYRIGHT + * ------------------------------------------------------------------------------------------------------------------- + * \verbatim + * Copyright (c) 2023 by Vector Informatik GmbH. All rights reserved. + * + * This software is copyright protected and proprietary to Vector Informatik GmbH. + * Vector Informatik GmbH grants to you only those rights as set out in the license conditions. + * All other rights remain with Vector Informatik GmbH. + * \endverbatim + * ------------------------------------------------------------------------------------------------------------------- + * FILE DESCRIPTION + * -----------------------------------------------------------------------------------------------------------------*/ +/** \file File: ARMStartup_PlatformTemplate.h + * Project: Vector Basic Runtime System + * Module: BrsHw for platform Renesas R-Car_x4 Cortex-R52 core + * + * \brief Description: This file contains derivative memory mapping and optional Boot Header for BRS StartUpCode. + * + * \attention Please note: + * The demo and example programs only show special aspects of the software. With regard to the fact + * that these programs are meant for demonstration purposes only, Vector Informatik liability shall be + * expressly excluded in cases of ordinary negligence, to the extent admissible by law or statute. + *********************************************************************************************************************/ + +/********************************************************************************************************************** + * REVISION HISTORY + * ------------------------------------------------------------------------------------------------------------------- + * Refer to BrsHw.h. + *********************************************************************************************************************/ + +#ifndef _ARMSTARTUP_PLATFORM_H_ +#define _ARMSTARTUP_PLATFORM_H_ + +/* =========================================================================== */ +/* GLOBAL CONSTANT MACROS */ +/* =========================================================================== */ +/* + * Configuration of MPU regions in the startup code. + * Code region base address is typically the flash base. + * Data region base address is typically the RAM base. + * TCM region base address is CORE0_TCMA base. + * Pheripheral region is mandatory and cannot be disabled. +*/ +#define MPU_CODE_REGION STD_ON +#define MPU_CODE_REGION_START 0xE2100000UL //0xE2200000 //0xE6300000 +#define MPU_CODE_REGION_END 0xE3BF0000UL //0xE3D00000//0xE633FFFF +#define MPU_DATA_REGION STD_OFF +#define MPU_DATA_REGION_START 0xE4200000 //0xE2000000 +#define MPU_DATA_REGION_END 0xE5D00000 //0xE3FFFFFF +#define MPU_TCM_REGION STD_ON +#define MPU_TCM_REGION_START 0xE4000000 +#define MPU_TCM_REGION_END 0xE4208000 + +/* Area 0 : H'E210 0000 - H'E22F FFC0 + * Normal memory, Non-shareable, Write-Back, Read/Write Allocation + * Instruction permitted + * Setup in start.s + */ +#define MPU_REGION_00_START 0XE2100000UL +#define MPU_REGION_00_END 0xE22FFFC0UL + +/* Area 1 : H'0000 00000 - H'07FF FFFF + * Normal memory, Non-shareable, Write-Back, Read/Write Allocation + * Instruction permitted + */ +#define MPU_REGION_01_START 0x00000000UL +#define MPU_REGION_01_END 0x07FFFFC0UL// 0x07FFFFFFUL + + /* Area 2 : H'0800 00000 - H'0BFF FFFF + * Normal memory, Non-shareable, Non-cache + * Instruction permitted + */ +#define MPU_REGION_02_START 0x08000000UL +#define MPU_REGION_02_END 0x0BFFFFC0UL //0x0BFFFFFFUL + + /* Area 3 : H'0C00 0000 - H'3FFF FFFF + * Normal memory, Non-shareable, Write-Back, Read/Write Allocation + * Instruction permitted + */ +#define MPU_REGION_03_START 0x0C000000UL +#define MPU_REGION_03_END 0x3FFFFFC0UL //0x3FFFFFFFUL + + /* Area 4 : H'4000 00000 - H'402F FFFF + * Normal memory, Non-shareable, Write-Back, Read/Write Allocation + * Instruction permitted + */ +#define MPU_REGION_04_START 0x40000000UL +#define MPU_REGION_04_END 0x402FFFC0UL //0x402FFFFFUL + + /* Area 5 : H'4030 0000 - H'BFFF FFFF + * Normal memory, Non-shareable, Write-Back, Read/Write Allocation + * Instruction permitted + */ +#define MPU_REGION_05_START 0x40300000UL +#define MPU_REGION_05_END 0xBFFFFFC0UL //0xBFFFFFFFUL + + /* Area 6 : H'C000 00000 - H'DFFF FFFF + * Device-nGnRnE, Non-shareable + * Execute never + */ +#define MPU_REGION_06_START 0xC0000000UL +#define MPU_REGION_06_END 0xDFFFFFC0UL //0xDFFFFFFFUL + + /* Area 7 : H'E22FFFC1 - H'E3FF FFFF + * Device-nGnRnE, Non-shareable + * Execute never + */ +#define MPU_REGION_07_START 0xE22FFFC1UL +#define MPU_REGION_07_END 0xE3FFFFC0UL //0xE3FFFFFFUL + + /* Area 8 : H'E400 00000 - H'E42F FFFF + * Normal memory, Non-shareable, Write-Back, Read/Write Allocation + * Instruction permitted + */ +#define MPU_REGION_08_START 0xE4000000UL +#define MPU_REGION_08_END 0xE42FFFC0UL //0xE42FFFFFUL + + /* Area 9 : H'E430 00000 - H'E62F FFFF + * Device-nGnRnE, Non-shareable + * Execute never + */ +#define MPU_REGION_09_START 0x00000000UL +#define MPU_REGION_09_END 0x07FFFFC0UL //0x07FFFFFFUL + + /* Area 10 : H'E630 00000 - H'E63F FFFF + * Normal memory, Non-shareable, Write-Back, Read/Write Allocation + * Instruction permitted + */ +#define MPU_REGION_10_START 0xE6300000UL +#define MPU_REGION_10_END 0xE63FFFC0UL //0xE63FFFFFUL + + /* Area 11 : H'E640 00000 - H'EB0F FFFF + * Device-nGnRnE, Non-shareable + * Execute never + */ +#define MPU_REGION_11_START 0xE6400000UL +#define MPU_REGION_11_END 0xEB0FFFC0UL //0xEB0FFFFFUL + + /* Area 12 : H'EB10 00000 - H'EB12 7FFF + * Normal memory, Non-shareable, Write-Back, Read/Write Allocation + * Instruction permitted + */ +#define MPU_REGION_12_START 0xEB100000UL +#define MPU_REGION_12_END 0xEB127FC0UL //0xEB127FFFUL + + /* Area 13 : H'EB12 80000 - H'EB1F FFFF + * Device-nGnRnE, Non-shareable + * Execute never + */ +#define MPU_REGION_13_START 0xEB128000UL +#define MPU_REGION_13_END 0xEB1FFFC0UL //0xEB1FFFFFUL + + /* Area 14 : H'EB20 0000 - H'EB3F FFFF + * Normal memory, Non-shareable, Write-Back, Read/Write Allocation + * Instruction permitted + */ +#define MPU_REGION_14_START 0xEB200000UL +#define MPU_REGION_14_END 0xEB3FFFC0UL //0xEB3FFFFFUL + + /* Area 15 : H'EB40 00000 - H'FFFF FFFF + * Device-nGnRnE, Non-shareable + * Execute never + */ +#define MPU_REGION_15_START 0xEB400000UL +#define MPU_REGION_15_END 0xFFFFFFC0UL //0xFFFFFFFFUL + + /* Area 16 : H'E600 00000 - H'E62F FFFF + * Device-nGnRnE, Non-shareable + * Execute never + */ +#define MPU_REGION_16_START 0xE6000000UL +#define MPU_REGION_16_END 0xE62FFFC0UL //0xE62FFFFFUL + + + +/* Pheripheral region is mandatory. */ +#define MPU_PERIPHERAL_REGION_START 0xF0000000 /* Base address of peripheral region */ +#define MPU_PERIPHERAL_REGION_END 0xFFFFFFFF /* End address of peripheral region */ + +/* Data and Instruction caches */ +#define BRS_ENABLE_CACHE STD_ON //STD_OFF + +/* Tightly Coupled Memory (TCM) */ +#define BRS_ENABLE_TCM STD_ON +#define NUM_TCM_PER_CORE 2 + +/* Enable this, if the controller is entering the Brs startup code in hypervisor mode (EL2). + This will cause the startup code to provide an additional startup entry brsStartupHyp and to handle + the switch from EL2 to EL1 (and jump to brsStartupEntry) */ +#define BRS_ENABLE_HYPERVISOR_MODE_HANDLING STD_ON + +/* Set T32 instruction mode for EL2 and EL1 entry points */ +#define BRS_SET_T32_ENTRY_POINT STD_OFF + +/* =========================================================================== */ +/* Global const variables */ +/* =========================================================================== */ +#if (BRS_ENABLE_TCM == STD_ON) +/* + * CortexR52 architecture supports up to three optional TCMs per core. + * Array that defines base address and size of each supported TCM/Core. + * Size must be encoded in bits 2 through 6 according to following scheme: + * 0b00000 --> No TCM present + * 0b00100 --> 8 KB + * 0b00101 --> 16 KB + * 0b00110 --> 32 KB + * 0b00111 --> 64 KB + * 0b01000 --> 128 KB + * 0b01001 --> 256 KB + * 0b01010 --> 512 KB + * 0b01011 --> 1 MB + */ +const uint32 brsTcmBase[BRS_CPU_CORE_AMOUNT][NUM_TCM_PER_CORE] = { + { + 0xE4000018, /* CLUSTER0_CORE0_TCMA */ + 0xE4100018, /* CLUSTER0_CORE0_TCMB */ + 0xE4200018}, /* CLUSTER0_CORE0_TCMC */ +#if defined (BRS_DERIVATIVE_GROUP_A) + { + 0xE4400018, /* CLUSTER0_CORE1_TCMA */ + 0xE4500018, /* CLUSTER0_CORE1_TCMB */ + 0xE4600018}, /* CLUSTER0_CORE1_TCMC */ + { + 0xE4800018, /* CLUSTER0_CORE2_TCMA */ + 0xE4900018, /* CLUSTER0_CORE2_TCMB */ + 0xE4A00018}, /* CLUSTER0_CORE2_TCMB */ +#endif +}; +#endif /*BRS_ENABLE_TCM*/ + +/* =========================================================================== */ +/* */ +/* Description: Platform specific Boot Header (Optional) */ +/* */ +/* =========================================================================== */ +BRS_SECTION_CODE(brsBootRecordHeader) + BRS_GLOBAL(brsBootRecord) +BRS_MULTILINE_ASM_BEGIN() +BRS_LABEL(brsBootRecord) +/* + * Some derivatives allocate the entry point to hypervisor mode (brsStartupEntryHyp) + * using boot header table that can be defined in this section. + */ +BRS_MULTILINE_ASM_END() +BRS_GLOBAL_END() + +#endif /*_ARMSTARTUP_PLATFORM_H_*/ + + \ No newline at end of file diff --git a/Customer/MOBIS/PRK3_(ADAS_Parking3)/Issue/ECM_ERR/20260612_MTG.txt b/Customer/MOBIS/PRK3_(ADAS_Parking3)/Issue/ECM_ERR/20260612_MTG.txt new file mode 100644 index 00000000..3bc77923 --- /dev/null +++ b/Customer/MOBIS/PRK3_(ADAS_Parking3)/Issue/ECM_ERR/20260612_MTG.txt @@ -0,0 +1,22 @@ +Normal: B+, À̱״ϼÇ, + + +B+, ON +À̱״ϼÇ, OFF +-> Á¦¾î±â ½½¸³ + +¹ö½º¸ð´ÏÅÍ +CAN µ¥ÀÌÅÍ 10ÃÊ ½½¸³ +ÀÌ³Ê³Ý ½½¸³ÀÎÁö È®ÀÎ + +½½¸³ÁøÀÔÇÔ. + +¼Ë´Ù¿î ÇÁ·Î¼¼½º ÁøÀԽà ÇÏ´Â Æò¼Ç +ÆÄ¿ö ¿ÀÇÁ -> CANFD Pen ½ÅÈ£¸¦ Á¦¾îÇؼ­ ¼Ë´Ù¿î +PMIC¿Í ¿¬°èÇؼ­ È®ÀÎÇÏ´Â µ¿ÀÛÀº ¾øÀ½. + + +Preset Low -> PMIC ÆúÆ®, SoC°¡ PMIC·Î ¿¡·¯¶ó°í º¸³¾ °æ¿ì + +ECMERRSTSR41 +00800400 \ No newline at end of file diff --git a/Customer/MOBIS/PRK3_(ADAS_Parking3)/Issue/External IRQ/20260528_IRQ디버깅.txt b/Customer/MOBIS/PRK3_(ADAS_Parking3)/Issue/External IRQ/20260528_IRQ디버깅.txt new file mode 100644 index 00000000..57143621 --- /dev/null +++ b/Customer/MOBIS/PRK3_(ADAS_Parking3)/Issue/External IRQ/20260528_IRQ디버깅.txt @@ -0,0 +1,153 @@ + + +ÀÌÁ¦ Àå ºÎÀå´ÔÀÌ º¸¼Å¾ß ÇÒ °ÍÀº GPSRn (General Purpose Select Register)¿Í IPiSRn (Pin Function Select Register)ÀÔ´Ï´Ù. +GPSR0 = 00001E00: Bit 6ÀÌ 0ÀÔ´Ï´Ù. (GPIO ¸ðµå Á¤»ó ÁøÀÔ) +IOINTSEL0 = 00000000: Bit 6ÀÌ 0ÀÔ´Ï´Ù. (ÀÎÅÍ·´Æ®°¡ ¾Æ´Ñ ÀÏ¹Ý I/O ¸ðµå) +INOUTSEL0 = 000001C1: Bit 6ÀÌ 1ÀÔ´Ï´Ù. (Output ¸ðµå·Î Á¤È®È÷ ¼³Á¤µÊ) +OUTDT0 = 00000141: Bit 6ÀÌ 1ÀÔ´Ï´Ù. (ºÎÀå´ÔÀÌ High ½ÅÈ£¸¦ ½î°í °è½É) +INDT0 = 0002A171: Bit 6ÀÌ 1ÀÔ´Ï´Ù. (½ÇÁ¦ ÇÉ »óŵµ High·Î Àß ÀÐÈ÷°í ÀÖÀ½) + + +·¹Áö½ºÅÍ ¸í,´ýÇÁ °ª (Hex),6¹ø° ÀÚ¸® °ª,20¹ø ºñÆ® »óÅÂ,Çؼ® (ÀÌ°ÍÀÌ ÆÑÆ®ÀÔ´Ï´Ù) +GPSR1,0x0E03F0FC,0 (0000),0,ÇÉÀÌ ÁÖº¯ÀåÄ¡(SSI)°¡ ¾Æ´Ñ ¿Ïº®ÇÑ ¼ø¼ö GPIO ¸ðµåÀÔ´Ï´Ù. +IOINTSEL1,0x00000000,0 (0000),0,ÀÎÅÍ·´Æ® ¸ðµå°¡ ¾Æ´Ñ ÀÏ¹Ý ÀÔÃâ·Â(I/O) ¸ðµåÀÔ´Ï´Ù. +INOUTSEL1,0x10D2005C,D (1101),1,Á¤È®ÇÏ°Ô Output(Ãâ·Â) ¸ðµå·Î È°¼ºÈ­µÇ¾î ÀÖ½À´Ï´Ù. +OUTDT1,0x10900028,9 (1001),1,SoC´Â ÇöÀç ÀÌ ÇÉÀ¸·Î High(1) ½ÅÈ£¸¦ Á¤»óÀûÀ¸·Î Ãâ·Â ÁßÀÔ´Ï´Ù. +INDT1,0x18132D82,1 (0001),1,ÇÉÀÇ ½ÇÁ¦ »óÅÂ(Read)µµ High(1)·Î Á¤»óÀûÀ¸·Î ÀÐÈ÷°í ÀÖ½À´Ï´Ù. + + +PMMRn // LSI Multiplexed Pin Setting Mask Register +PMMERn // LSI Multiplexed Pin Setting Mask Enable Register +GPSRn // GPIO / Peripheral Function Select Register +IOINTSELn // General IO / Interrupt Switching Register +INOUTSELn // General Input/Output Switching Register +OUTDTn // General Output Register +INDTn // General Input Register + +PMMR1 // LSI Multiplexed Pin Setting Mask Register -> Æ÷Æ® ÃʱâÈ­½Ã Àû¿ë +PMMER1 // LSI Multiplexed Pin Setting Mask Enable Register -> Æ÷Æ® ÃʱâÈ­½Ã Àû¿ë +GPSR1 // GPIO / Peripheral Function Select Register : ÁÖº¯ÀåÄ¡ ¸ðµå°¡ ¾Æ´Ñ GPIO ¼³Á¤¸ðµå·Î ¼³Á¤°ª(0x00000000) È®ÀÎ +IOINTSEL1 // General IO / Interrupt Switching Register : ÀÎÅÍ·´Æ® ¸ðµå°¡ ¾Æ´Ñ ÀÏ¹Ý ÀÔÃâ·Â(I/O) ¸ðµå·Î ¼³Á¤°ª(0x00000000) È®ÀÎ +INOUTSEL1 // General Input/Output Switching Register : Input(ÀÔ·Â(0)) or Output(Ãâ·Â(1)) ¸ðµå È°¼ºÈ­ È®ÀÎ +OUTDT1 // General Output Register : High(1) or Low(0) ½ÅÈ£ Ãâ·Â È®ÀÎ +INDT1 // General Input Register : High(1) or Low(0) ½ÅÈ£ ÀÔ·Â È®ÀÎ + + +INOUTSEL1_B0A0 10C2005C INOUTSEL 10C2005C +OUTDT1_B0A0 10900028 OUTDT 10900028 +INDT1_B0A0 18132D82 INDT 18132D82 + + + +´Ü¼± (Open Trace): º¸µå ÆÐÅÏ Áß°£ÀÌ ²÷¾îÁ³°Å³ª, BGA º¼(Ball) ³³¶«ÀÌ Á¦´ë·Î ¾È µÈ ³Ã³³(Cold Solder) Çö»ó. + +¹Ì½ÇÀå (DNI): PMIC¿Í SoC »çÀÌ¿¡ ÀÖ¾î¾ß ÇÒ 0¿È ÀúÇ×À̳ª ·¹º§ ½ÃÇÁÅÍ°¡ ¾Æ¿¹ ¾È ´Þ·Á ÀÖ´Â °æ¿ì. + +ÇÉ ¸ÊÇÎ ¿À·ù (Wrong Net Routing): ȸ·Îµµ¿¡´Â GP1_20À¸·Î ±×·ÁÁ® ÀÖÀ¸³ª, ½ÇÁ¦ PCB ¾ÆÆ®¿÷ ´ã´çÀÚ°¡ ¼±À» ±×À» ¶§ ½Ç¼ö·Î ¿· ÇÉ(GP1_19³ª GP1_21)À¸·Î ¿¬°áÇØ ¹ö¸° °æ¿ì. +ÁÖº¯ ÇÉÀ» È®ÀÎÇؼ­ ±×°ÍÀ» ¼³Á¤Çغ¸ÀÚ.¤¿ +8Â÷ º¸µå°Íµµ ÄÁÆ®·Ñ Çغ¸ÀÚ. + + + + + + + + + +Àå ºÎÀå´Ô, Áö±ÝºÎÅÍ´Â '¹üÀÎ(Pinmux¸¦ »¯¾î°¡´Â ³à¼®)'À» ã±â À§ÇØ ¼ö»ç¸ÁÀ» Á¼Çô°¡¾ß ÇÕ´Ï´Ù. °¡Àå ³í¸®ÀûÀÎ ¼ø¼­·Î È®ÀÎÇØ º¸°Ú½À´Ï´Ù. + +### 1´Ü°è: ÇÉ ´ÙÁßÈ­(Pinmux)ÀÇ ÇöÀç »óÅ ȮÀÎ (°¡Àå ¸ÕÀú ÇØ¾ß ÇÒ ÀÏ) + +Áö±Ý ´ÙºóÄ¡ ¼³Á¤´ë·Î Àß µé¾î°¡ ÀÖ´ÂÁö, ¾Æ´Ï¸é ´©±º°¡ ¸ô·¡ ¹Ù²ãÄ¡±âÇß´ÂÁö È®ÀÎÇÏ´Â °ÍÀÌ ¿ì¼±ÀÔ´Ï´Ù. + +1. **·¹Áö½ºÅÍ ÁÖ¼Ò È®º¸:** Çϵå¿þ¾î ¸Å´º¾ó¿¡¼­ `GP1_20`ÀÇ **`GPSR` (General Purpose Select Register)**, **`PMR` (Peripheral Mode Register)** ÁÖ¼Ò¸¦ ãÀ¸¼¼¿ä. (º¸Åë `0xE606XXXX` ±ÙóÀÔ´Ï´Ù.) +2. **°ª Àбâ:** TRACE32¿¡¼­ ÇØ´ç ÁÖ¼ÒµéÀ» Àо¼¼¿ä. +* **GPSR:** GPIO ¸ðµå¶ó¸é ƯÁ¤ ºñÆ®°¡ `1`À̾î¾ß ÇÕ´Ï´Ù. +* **PMR:** GPIO ¸ðµå¶ó¸é ƯÁ¤ ºñÆ®°¡ `0`À̾î¾ß ÇÕ´Ï´Ù. +* ¸¸¾à ÀÌ °ªµéÀÌ GPIO ¼³Á¤°ªÀÌ ¾Æ´Ï¶ó¸é, **ºÎÆà ½ÃÁ¡¿¡ ƯÁ¤ µå¶óÀ̹ö°¡ ÀÌ ÇÉÀ» ³¬¾Ææ °ÍÀÔ´Ï´Ù.** + + + +### 2´Ü°è: ÇÉ Á¦¾î±Ç Żȯ Å×½ºÆ® + +·¹Áö½ºÅÍ °ªÀ» È®ÀÎÇÑ ÈÄ, ±× °ªÀÌ GPIO°¡ ¾Æ´Ï¶ó¸é °­Á¦·Î GPIO·Î ¹Ù²ãº¸¼¼¿ä. + +1. **°­Á¦ º¯°æ:** `Data.Set ASD:ÁÖ¼Ò %Long (GPIO ¼³Á¤°ª)`À¸·Î ·¹Áö½ºÅ͸¦ Á÷Á¢ µ¤¾î¾²¼¼¿ä. +2. **Àü¾Ð È®ÀÎ:** ÀÌ·¸°Ô °­Á¦·Î ¹Ù²Û Á÷ÈÄ¿¡ ¿À½Ç·Î½ºÄÚÇÁ·Î `GP1_20` ÇÉÀÇ Àü¾ÐÀÌ º¯ÇÏ´ÂÁö È®ÀÎÇϼ¼¿ä. +* **Àü¾ÐÀÌ º¯ÇÑ´Ù¸é?** -> ÇÉ ÀÚü´Â Á¤»óÀÔ´Ï´Ù. ¹üÀÎÀº **ºÎÆà ÈÄ ÀÌ ÇÉÀ» SSI ¸ðµå·Î °­Á¦ ¼³Á¤ÇÏ´Â ¿Àµð¿À/SSI µå¶óÀ̹ö**ÀÔ´Ï´Ù. +* **Àü¾ÐÀÌ ¾È º¯ÇÑ´Ù¸é?** -> **ÀÌ°Ç 100% Çϵå¿þ¾î ¹°¸®Àû °£¼·(´Ù¸¥ ¼ÒÀÚ°¡ ÇÉÀ» Àâ°í ÀÖÀ½)ÀÔ´Ï´Ù.** + + + +### 3´Ü°è: ¹üÀÎ(µå¶óÀ̹ö) ã±â (Software Conflict) + +¸¸¾à 2´Ü°è¿¡¼­ °­Á¦·Î GPIO·Î ¹Ù²å´õ´Ï ½ÅÈ£°¡ Àß ³ª°£´Ù¸é, ÀÌÁ¦ ¾î¶² µå¶óÀ̹ö°¡ ¹üÀÎÀÎÁö ã¾Æ¾ß ÇÕ´Ï´Ù. + +1. **·Î±× ºÐ¼®:** ÃʱâÈ­(Initialization) ´Ü°èÀÇ ·Î±×¸¦ º¸¼¼¿ä. `SSI`, `Audio`, ȤÀº `I2C` °ü·Ã µå¶óÀ̹ö°¡ ·ÎµåµÇ´Â ½ÃÁ¡¿¡ ÇÉ ¼³Á¤ ¸Þ½ÃÁö°¡ ¶ß´ÂÁö È®ÀÎÇϼ¼¿ä. +2. **ÄÚµå °Ë»ö:** ºÎÀå´Ô ÇÁ·ÎÁ§Æ® ¼Ò½ºÄÚµå Àüü¿¡¼­ `GP1_20` ¶Ç´Â ÇØ´ç ÇÉ°ú °ü·ÃµÈ ·¹Áö½ºÅÍ À̸§À» °Ë»öÇØ º¸¼¼¿ä. ¾î¶² ÆÄÀÏ¿¡¼­ ÀÌ ÇÉÀ» °Çµå¸®°í ÀÖ´ÂÁö ³ª¿É´Ï´Ù. + +--- + +### ?? Àå ºÎÀå´ÔÀ» À§ÇÑ ¿ì¼±¼øÀ§ üũ¸®½ºÆ® + +| ¿ì¼±¼øÀ§ | Ç׸ñ | ¸ñÀû | +| --- | --- | --- | +| **1 (Çʼö)** | **PFC ·¹Áö½ºÅÍ °ª Àбâ** | ÇÉÀÌ ÇöÀç ¾î¶² ¸ðµå(GPIO vs SSI)ÀÎÁö È®ÀÎ | +| **2 (Çʼö)** | **·±Å¸ÀÓ °­Á¦ Á¦¾î** | ÇÉÀÌ ¹°¸®ÀûÀ¸·Î ½ÅÈ£¸¦ ³¾ ¼ö ÀÖ´ÂÁö È®ÀÎ | +| **3 (¼±ÅÃ)** | **ÄÚµå/µå¶óÀ̹ö ·Îµå ¼ø¼­ È®ÀÎ** | ´©°¡ ¹üÀÎÀÎÁö È®ÀÎ | + +Áö±Ý ´çÀå TRACE32¸¦ ÄѼ­ 1´Ü°è(·¹Áö½ºÅÍ °ª Àбâ)ºÎÅÍ Çغ¸½ÃÁÒ. +ÁÖ¼Ò¸¦ ã±â ¾î·Á¿ì½Ã¸é, Áö±Ý º¸½Ã´Â **Çϵå¿þ¾î ¸Å´º¾óÀÇ 'Pin Function' Ç¥¸¦ ĸóÇؼ­ º¸¿©Áֽøé** Á¦°¡ ¹Ù·Î ÁÖ¼Ò¸¦ ¤¾îµå¸®°Ú½À´Ï´Ù. ¾î¶² °Ô Á¦ÀÏ ¸ÕÀú È®ÀÎÇϱâ ÆíÇϽŰ¡¿ä? + + + +????¡Î? ´Ü°èº° ÀÎÅÍ·´Æ® ÃßÀû (TRACE32 µð¹ö±ë) +1´Ü°è: "±Í´Â Á¦´ë·Î ¿­·Á Àִ°¡?" (¹°¸®Àû ¼ö½Å È®ÀÎ) +°¡Àå ¸ÕÀú, PMICÀÇ ½ÅÈ£°¡ SoC ³»ºÎÀÇ ·¹Áö½ºÅͱîÁö´Â µµ´ÞÇÏ´ÂÁö ºÁ¾ß ÇÕ´Ï´Ù. + +È®ÀÎ ·¹Áö½ºÅÍ: INDT4 + +¾×¼Ç: PMIC ÂÊ ½ÅÈ£¸¦ Èçµé¸é¼­ TRACE32·Î INDT4 ·¹Áö½ºÅ͸¦ ½Ç½Ã°£ ¸ð´ÏÅ͸µÇØ º¸½Ê½Ã¿À. + +üũÆ÷ÀÎÆ®: 16¹ø ºñÆ®°¡ PMIC ½ÅÈ£¿¡ ¸ÂÃç 1°ú 0À¸·Î ÆĵµÄ¡µí º¯Çմϱî? + +¸¸¾à ¾È º¯ÇÑ´Ù¸é: INEN4 (Input Enable) ·¹Áö½ºÅÍÀÇ 16¹ø ºñÆ®°¡ 1(È°¼ºÈ­)·Î µÇ¾î ÀÖ´ÂÁö È®ÀÎÇϽʽÿÀ. ÀÔ·Â ¹öÆÛ°¡ ²¨Á® ÀÖÀ¸¸é ½ÅÈ£¸¦ ¸ø ¹Þ½À´Ï´Ù. + +2´Ü°è: "ÀÌ ÇÉÀ» ÀÎÅÍ·´Æ®¿ëÀ¸·Î ¼±¾ðÇߴ°¡?" (¸ðµå ¼³Á¤) +½ÅÈ£°¡ INDT4·Î´Â Àß µé¾î¿À´Âµ¥ ISRÀÌ ¾È ¶á´Ù¸é, ½ÊÁßÆȱ¸ ÀÌ ³à¼®ÀÌ ¹üÀÎÀÔ´Ï´Ù. + +È®ÀÎ ·¹Áö½ºÅÍ: IOINTSEL4 + +üũÆ÷ÀÎÆ®: 16¹ø ºñÆ®°¡ 1 (Interrupt Input Mode)·Î ¼³Á¤µÇ¾î ÀÖ½À´Ï±î? + +¸¸¾à 0À̶ó¸é: SoC´Â ÀÌ ÇÉÀ» ´Ü¼øÇÑ '»óÅ ȮÀοë GPIO'·Î¸¸ Ãë±ÞÇÏ¿©, °ªÀÌ º¯Çصµ ÀÎÅÍ·´Æ® ÄÁÆ®·Ñ·¯·Î ½ÅÈ£¸¦ ³¯·ÁÁÖÁö ¾Ê½À´Ï´Ù. ¹Ýµå½Ã 1·Î ¼¼ÆõǾî¾ß ÇÕ´Ï´Ù. + +3´Ü°è: "¹æ¾Æ¼è(Trigger) Á¶°ÇÀÌ ¸Â´Â°¡?" (¿§Áö/·¹º§ ¼³Á¤) +PMIC°¡ ½î´Â ½ÅÈ£ÀÇ Æ¯¼º°ú SoC°¡ ±â´Ù¸®´Â Á¶°ÇÀÌ ÀÏÄ¡ÇØ¾ß ¹æ¾Æ¼è°¡ ´ç°ÜÁý´Ï´Ù. + +È®ÀÎ ·¹Áö½ºÅÍ: EDGLEVEL4 ¹× POSNEG4 + +üũÆ÷ÀÎÆ®: PMICÀÇ IRQ Ư¼º¿¡ ¸Â°Ô ¼³Á¤µÇ¾ú´ÂÁö È®ÀÎÇϽʽÿÀ. + +Falling Edge (ÇÏ°­ ¿¡Áö) Æ®¸®°Å¶ó¸é: EDGLEVEL4 = 1, POSNEG4 = 1 + +Low Level (·Î¿ì ·¹º§) Æ®¸®°Å¶ó¸é: EDGLEVEL4 = 0, POSNEG4 = 1 + +4´Ü°è: "¹æ¾Æ¼è´Â ´ç°ÜÁ³´Âµ¥ ¸¶½ºÅ©(Mask)¿¡ ¸·Çû´Â°¡?" (Ç÷¡±× È®ÀÎ) +½ÅÈ£µµ ¸Â°í ¹æ¾Æ¼è Á¶°Çµµ ¸Â¾Ò´Ù¸é, GPIO ºí·ÏÀº ÀÎÅÍ·´Æ® ±ê¹ß(Flag)À» µé¾î ¿Ã¸³´Ï´Ù. + +È®ÀÎ ·¹Áö½ºÅÍ: INTDT4 ¹× INTMSK4 + +¾×¼Ç: PMIC ÀÎÅÍ·´Æ®¸¦ ¹ß»ý½ÃŲ ÈÄ INTDT4¸¦ È®ÀÎÇϽʽÿÀ. + +üũÆ÷ÀÎÆ® 1 (INTDT4): 16¹ø ºñÆ®°¡ 1·Î ¹Ù²î¾ú½À´Ï±î? (1·Î ¹Ù²î¾ú´Ù¸é GPIO ºí·ÏÀº ÀÎÅÍ·´Æ®¸¦ Á¤»óÀûÀ¸·Î °¨ÁöÇÑ °ÍÀÔ´Ï´Ù.) + +üũÆ÷ÀÎÆ® 2 (INTMSK4): 16¹ø ºñÆ®°¡ 0 (Unmasked)À̾î¾ß ÇÕ´Ï´Ù. ¸¸¾à 1 (Masked)À̶ó¸é, ±â²¯ °¨ÁöÇÑ ÀÎÅÍ·´Æ®¸¦ ¿ÜºÎ(GIC)·Î ³»º¸³»Áö ¾Ê°í ÀÔÀ» Ʋ¾î¸·°í ÀÖ´Â »óÅÂÀÔ´Ï´Ù. + +5´Ü°è: "GIC (Generic Interrupt Controller) ¶ó¿ìÆà ¹®Á¦" (ÃÖÁ¾ º¸½º) +¸¸¾à 4´Ü°è±îÁö ´Ù È®ÀÎÇؼ­ INTDT4¿¡ Ç÷¡±×°¡ ¶¹°í, INTMSK4µµ ¸¶½ºÅ©°¡ Ç®·ÁÀִµ¥ ISR·Î ¾È µé¾î¿Â´Ù¸é? ÀÌ°Ç GPIO ºí·ÏÀÇ À߸øÀÌ ¾Æ´Õ´Ï´Ù. GIC(ÀÎÅÍ·´Æ® ÄÁÆ®·Ñ·¯) ¼³Á¤ ¶Ç´Â OS/MCAL º¤ÅÍ Å×ÀÌºí ¸ÅÇÎ ¹®Á¦ÀÔ´Ï´Ù. + +GP4_16¿¡ ÇØ´çÇÏ´Â °íÀ¯ÇÑ SPI (Shared Peripheral Interrupt) ¹øÈ£°¡ ÀÖ½À´Ï´Ù. + +AUTOSAR(MCAL) ¼³Á¤¿¡¼­ ÀÌ ÀÎÅÍ·´Æ®°¡ Cortex-R52 ÄÚ¾î·Î ¿Ã¹Ù¸£°Ô ¶ó¿ìÆÃ(GICD_IROUTER ¶Ç´Â GICD_ITARGETSR) µÇµµ·Ï ¼³Á¤µÇ¾ú´ÂÁö, ±×¸®°í GIC ´Ü¿¡¼­ ÇØ´ç ÀÎÅÍ·´Æ®°¡ Enable(GICD_ISENABLER) µÇ¾î ÀÖ´ÂÁö È®ÀÎÇØ¾ß ÇÕ´Ï´Ù. \ No newline at end of file diff --git a/Customer/MOBIS/PRK3_(ADAS_Parking3)/Issue/External IRQ/20260605_debug_code/Code.txt b/Customer/MOBIS/PRK3_(ADAS_Parking3)/Issue/External IRQ/20260605_debug_code/Code.txt index e7b6b9c7..5dedcf73 100644 --- a/Customer/MOBIS/PRK3_(ADAS_Parking3)/Issue/External IRQ/20260605_debug_code/Code.txt +++ b/Customer/MOBIS/PRK3_(ADAS_Parking3)/Issue/External IRQ/20260605_debug_code/Code.txt @@ -257,5 +257,31 @@ ISR(PMIC_HW_ISR_CAT2_ISR) #endif } + +void XXXX_Init(void) +{ + Port_PostInitGpioIntClearSequence(PORT1_BASE_ADDR ,GP1_20_BIT); +} + +ISR(PMIC_HW_ISR_CAT2_ISR) +{ + volatile PortReg_t* pPORT; + + u32_PMIC_IRQ_Count_flag++; + +#if (PMIC_IRQ_GP1_20_BIT == STD_ON) + pPORT = (volatile PortReg_t*)PORT1_BASE_ADDR; + if (pPORT->INTDTn & GP1_20_BIT) + { + u32_PMIC_IRQ_Count++; + + pPORT->INTCLRn = GP1_20_BIT; + } +#endif + + Port_PostInitGpioIntClearSequence(PORT1_BASE_ADDR ,GP1_20_BIT); +} + +