From c7342a414c96665e9b4644e776493dd08a879ccd Mon Sep 17 00:00:00 2001 From: woody Date: Fri, 19 Jun 2026 20:59:08 +0900 Subject: [PATCH] add --- ...rtos_V4H.ttl => Flash_Write_WoodyRtos.ttl} | 0 .../V4H/19_11/include/Can_Cfg.h | 467 + .../V4H/19_11/src/Can_Lcfg.c | 395 + .../V4H/19_11/src/Can_PBcfg.c | 786 + .../V4H/19_11/include/CDD_Crc_Cbk.h | 143 + .../V4H/19_11/include/CDD_Crc_Cfg.h | 595 + .../V4H/19_11/src/CDD_Crc_PBcfg.c | 2365 +++ .../V4H/19_11/include/CDD_Emm_Cfg.h | 3840 ++++ .../V4H/19_11/src/CDD_Emm_PBcfg.c | 15203 ++++++++++++++++ .../V4H/19_11/include/CDD_Iccom_Cbk.h | 158 + .../V4H/19_11/include/CDD_Iccom_Cfg.h | 274 + .../V4H/19_11/src/CDD_Iccom_PBcfg.c | 558 + .../V4H/19_11/include/CDD_Iic_Cbk.h | 167 + .../V4H/19_11/include/CDD_Iic_Cfg.h | 232 + .../V4H/19_11/src/CDD_Iic_PBcfg.c | 1149 ++ .../V4H/19_11/include/CDD_Ipmmu_Cbk.h | 148 + .../V4H/19_11/include/CDD_Ipmmu_Cfg.h | 190 + .../V4H/19_11/include/CDD_Ipmmu_Hardware.h | 1091 ++ .../V4H/19_11/src/CDD_Ipmmu_PBcfg.c | 642 + .../V4H/19_11/include/CDD_Rfso_Cbk.h | 142 + .../V4H/19_11/include/CDD_Rfso_Cfg.h | 219 + .../V4H/19_11/src/CDD_Rfso_PBcfg.c | 277 + .../V4H/19_11/include/CDD_Ths_Cfg.h | 221 + .../V4H/19_11/include/CDD_Ths_Reg.h | 240 + .../V4H/19_11/src/CDD_Ths_PBcfg.c | 251 + .../V4H/19_11/include/Dio_Cfg.h | 218 + .../V4H/19_11/src/Dio_Lcfg.c | 363 + .../V4H/19_11/include/Eth_Cfg.h | 369 + .../V4H/19_11/src/Eth_PBcfg.c | 1369 ++ .../V4H/19_11/include/Fls_Cfg.h | 452 + .../V4H/19_11/src/Fls_PbCfg.c | 1089 ++ .../V4H/19_11/include/Gpt_Cbk.h | 168 + .../V4H/19_11/include/Gpt_Cfg.h | 274 + .../V4H/19_11/src/Gpt_PBcfg.c | 588 + .../V4H/19_11/include/Mcu_Cfg.h | 319 + .../V4H/19_11/src/Mcu_PBcfg.c | 1279 ++ .../V4H/19_11/include/Port_Cfg.h | 387 + .../V4H/19_11/src/Port_PBcfg.c | 2770 +++ .../V4H/19_11/include/Spi_Cfg.h | 369 + .../V4H/19_11/src/Spi_Lcfg.c | 249 + .../V4H/19_11/src/Spi_PBcfg.c | 851 + .../V4H/19_11/include/Wdg_Cfg.h | 287 + .../V4H/19_11/src/Wdg_PBcfg.c | 201 + .../include/App_Woody_Common_Sample.h | 53 + .../src/App_Woody_Common_Sample.c | 11 +- ...rv4h-cr52_sieve_smp_offchip_trace_sram.cmm | 178 + .../V4H/Tr32_Script/EVB/Woody_Debug.cmm | 43 + .../V4H/Tr32_Script/EVB/Woody_HW_Reset.cmm | 2 + .../EVB/Woody_r_carv4h-cr52_warm_reset.cmm | 51 + .../0_Doc/scripts/V4H/EVB/Debug.cmm | 27 - 50 files changed, 41686 insertions(+), 34 deletions(-) rename Src/0_Tool/FW_Write/EVB/V4H/{Flash_Bootloader_Dummyrtos_V4H.ttl => Flash_Write_WoodyRtos.ttl} (100%) create mode 100644 Src/Gen4_R-Car_MCAL/2_Trunk/V4H/MCAL-v4h_19.4.0.D_release/rel/modules/can/sample_application/V4H/19_11/include/Can_Cfg.h create mode 100644 Src/Gen4_R-Car_MCAL/2_Trunk/V4H/MCAL-v4h_19.4.0.D_release/rel/modules/can/sample_application/V4H/19_11/src/Can_Lcfg.c create mode 100644 Src/Gen4_R-Car_MCAL/2_Trunk/V4H/MCAL-v4h_19.4.0.D_release/rel/modules/can/sample_application/V4H/19_11/src/Can_PBcfg.c create mode 100644 Src/Gen4_R-Car_MCAL/2_Trunk/V4H/MCAL-v4h_19.4.0.D_release/rel/modules/cddcrc/sample_application/V4H/19_11/include/CDD_Crc_Cbk.h create mode 100644 Src/Gen4_R-Car_MCAL/2_Trunk/V4H/MCAL-v4h_19.4.0.D_release/rel/modules/cddcrc/sample_application/V4H/19_11/include/CDD_Crc_Cfg.h create mode 100644 Src/Gen4_R-Car_MCAL/2_Trunk/V4H/MCAL-v4h_19.4.0.D_release/rel/modules/cddcrc/sample_application/V4H/19_11/src/CDD_Crc_PBcfg.c create mode 100644 Src/Gen4_R-Car_MCAL/2_Trunk/V4H/MCAL-v4h_19.4.0.D_release/rel/modules/cddemm/sample_application/V4H/19_11/include/CDD_Emm_Cfg.h create mode 100644 Src/Gen4_R-Car_MCAL/2_Trunk/V4H/MCAL-v4h_19.4.0.D_release/rel/modules/cddemm/sample_application/V4H/19_11/src/CDD_Emm_PBcfg.c create mode 100644 Src/Gen4_R-Car_MCAL/2_Trunk/V4H/MCAL-v4h_19.4.0.D_release/rel/modules/cddiccom/sample_application/V4H/19_11/include/CDD_Iccom_Cbk.h create mode 100644 Src/Gen4_R-Car_MCAL/2_Trunk/V4H/MCAL-v4h_19.4.0.D_release/rel/modules/cddiccom/sample_application/V4H/19_11/include/CDD_Iccom_Cfg.h create mode 100644 Src/Gen4_R-Car_MCAL/2_Trunk/V4H/MCAL-v4h_19.4.0.D_release/rel/modules/cddiccom/sample_application/V4H/19_11/src/CDD_Iccom_PBcfg.c create mode 100644 Src/Gen4_R-Car_MCAL/2_Trunk/V4H/MCAL-v4h_19.4.0.D_release/rel/modules/cddiic/sample_application/V4H/19_11/include/CDD_Iic_Cbk.h create mode 100644 Src/Gen4_R-Car_MCAL/2_Trunk/V4H/MCAL-v4h_19.4.0.D_release/rel/modules/cddiic/sample_application/V4H/19_11/include/CDD_Iic_Cfg.h create mode 100644 Src/Gen4_R-Car_MCAL/2_Trunk/V4H/MCAL-v4h_19.4.0.D_release/rel/modules/cddiic/sample_application/V4H/19_11/src/CDD_Iic_PBcfg.c create mode 100644 Src/Gen4_R-Car_MCAL/2_Trunk/V4H/MCAL-v4h_19.4.0.D_release/rel/modules/cddipmmu/sample_application/V4H/19_11/include/CDD_Ipmmu_Cbk.h create mode 100644 Src/Gen4_R-Car_MCAL/2_Trunk/V4H/MCAL-v4h_19.4.0.D_release/rel/modules/cddipmmu/sample_application/V4H/19_11/include/CDD_Ipmmu_Cfg.h create mode 100644 Src/Gen4_R-Car_MCAL/2_Trunk/V4H/MCAL-v4h_19.4.0.D_release/rel/modules/cddipmmu/sample_application/V4H/19_11/include/CDD_Ipmmu_Hardware.h create mode 100644 Src/Gen4_R-Car_MCAL/2_Trunk/V4H/MCAL-v4h_19.4.0.D_release/rel/modules/cddipmmu/sample_application/V4H/19_11/src/CDD_Ipmmu_PBcfg.c create mode 100644 Src/Gen4_R-Car_MCAL/2_Trunk/V4H/MCAL-v4h_19.4.0.D_release/rel/modules/cddrfso/sample_application/V4H/19_11/include/CDD_Rfso_Cbk.h create mode 100644 Src/Gen4_R-Car_MCAL/2_Trunk/V4H/MCAL-v4h_19.4.0.D_release/rel/modules/cddrfso/sample_application/V4H/19_11/include/CDD_Rfso_Cfg.h create mode 100644 Src/Gen4_R-Car_MCAL/2_Trunk/V4H/MCAL-v4h_19.4.0.D_release/rel/modules/cddrfso/sample_application/V4H/19_11/src/CDD_Rfso_PBcfg.c create mode 100644 Src/Gen4_R-Car_MCAL/2_Trunk/V4H/MCAL-v4h_19.4.0.D_release/rel/modules/cddths/sample_application/V4H/19_11/include/CDD_Ths_Cfg.h create mode 100644 Src/Gen4_R-Car_MCAL/2_Trunk/V4H/MCAL-v4h_19.4.0.D_release/rel/modules/cddths/sample_application/V4H/19_11/include/CDD_Ths_Reg.h create mode 100644 Src/Gen4_R-Car_MCAL/2_Trunk/V4H/MCAL-v4h_19.4.0.D_release/rel/modules/cddths/sample_application/V4H/19_11/src/CDD_Ths_PBcfg.c create mode 100644 Src/Gen4_R-Car_MCAL/2_Trunk/V4H/MCAL-v4h_19.4.0.D_release/rel/modules/dio/sample_application/V4H/19_11/include/Dio_Cfg.h create mode 100644 Src/Gen4_R-Car_MCAL/2_Trunk/V4H/MCAL-v4h_19.4.0.D_release/rel/modules/dio/sample_application/V4H/19_11/src/Dio_Lcfg.c create mode 100644 Src/Gen4_R-Car_MCAL/2_Trunk/V4H/MCAL-v4h_19.4.0.D_release/rel/modules/eth/sample_application/V4H/19_11/include/Eth_Cfg.h create mode 100644 Src/Gen4_R-Car_MCAL/2_Trunk/V4H/MCAL-v4h_19.4.0.D_release/rel/modules/eth/sample_application/V4H/19_11/src/Eth_PBcfg.c create mode 100644 Src/Gen4_R-Car_MCAL/2_Trunk/V4H/MCAL-v4h_19.4.0.D_release/rel/modules/fls/sample_application/V4H/19_11/include/Fls_Cfg.h create mode 100644 Src/Gen4_R-Car_MCAL/2_Trunk/V4H/MCAL-v4h_19.4.0.D_release/rel/modules/fls/sample_application/V4H/19_11/src/Fls_PbCfg.c create mode 100644 Src/Gen4_R-Car_MCAL/2_Trunk/V4H/MCAL-v4h_19.4.0.D_release/rel/modules/gpt/sample_application/V4H/19_11/include/Gpt_Cbk.h create mode 100644 Src/Gen4_R-Car_MCAL/2_Trunk/V4H/MCAL-v4h_19.4.0.D_release/rel/modules/gpt/sample_application/V4H/19_11/include/Gpt_Cfg.h create mode 100644 Src/Gen4_R-Car_MCAL/2_Trunk/V4H/MCAL-v4h_19.4.0.D_release/rel/modules/gpt/sample_application/V4H/19_11/src/Gpt_PBcfg.c create mode 100644 Src/Gen4_R-Car_MCAL/2_Trunk/V4H/MCAL-v4h_19.4.0.D_release/rel/modules/mcu/sample_application/V4H/19_11/include/Mcu_Cfg.h create mode 100644 Src/Gen4_R-Car_MCAL/2_Trunk/V4H/MCAL-v4h_19.4.0.D_release/rel/modules/mcu/sample_application/V4H/19_11/src/Mcu_PBcfg.c create mode 100644 Src/Gen4_R-Car_MCAL/2_Trunk/V4H/MCAL-v4h_19.4.0.D_release/rel/modules/port/sample_application/V4H/19_11/include/Port_Cfg.h create mode 100644 Src/Gen4_R-Car_MCAL/2_Trunk/V4H/MCAL-v4h_19.4.0.D_release/rel/modules/port/sample_application/V4H/19_11/src/Port_PBcfg.c create mode 100644 Src/Gen4_R-Car_MCAL/2_Trunk/V4H/MCAL-v4h_19.4.0.D_release/rel/modules/spi/sample_application/V4H/19_11/include/Spi_Cfg.h create mode 100644 Src/Gen4_R-Car_MCAL/2_Trunk/V4H/MCAL-v4h_19.4.0.D_release/rel/modules/spi/sample_application/V4H/19_11/src/Spi_Lcfg.c create mode 100644 Src/Gen4_R-Car_MCAL/2_Trunk/V4H/MCAL-v4h_19.4.0.D_release/rel/modules/spi/sample_application/V4H/19_11/src/Spi_PBcfg.c create mode 100644 Src/Gen4_R-Car_MCAL/2_Trunk/V4H/MCAL-v4h_19.4.0.D_release/rel/modules/wdg/sample_application/V4H/19_11/include/Wdg_Cfg.h create mode 100644 Src/Gen4_R-Car_MCAL/2_Trunk/V4H/MCAL-v4h_19.4.0.D_release/rel/modules/wdg/sample_application/V4H/19_11/src/Wdg_PBcfg.c create mode 100644 Src/Gen4_R-Car_MCAL/2_Trunk/V4H/Tr32_Script/EVB/Lauterbach/Woody_r_carv4h-cr52_sieve_smp_offchip_trace_sram.cmm create mode 100644 Src/Gen4_R-Car_MCAL/2_Trunk/V4H/Tr32_Script/EVB/Woody_Debug.cmm create mode 100644 Src/Gen4_R-Car_MCAL/2_Trunk/V4H/Tr32_Script/EVB/Woody_HW_Reset.cmm create mode 100644 Src/Gen4_R-Car_MCAL/2_Trunk/V4H/Tr32_Script/EVB/Woody_r_carv4h-cr52_warm_reset.cmm delete mode 100644 Src/Gen4_R-Car_Trace32/0_Doc/scripts/V4H/EVB/Debug.cmm diff --git a/Src/0_Tool/FW_Write/EVB/V4H/Flash_Bootloader_Dummyrtos_V4H.ttl b/Src/0_Tool/FW_Write/EVB/V4H/Flash_Write_WoodyRtos.ttl similarity index 100% rename from Src/0_Tool/FW_Write/EVB/V4H/Flash_Bootloader_Dummyrtos_V4H.ttl rename to Src/0_Tool/FW_Write/EVB/V4H/Flash_Write_WoodyRtos.ttl diff --git a/Src/Gen4_R-Car_MCAL/2_Trunk/V4H/MCAL-v4h_19.4.0.D_release/rel/modules/can/sample_application/V4H/19_11/include/Can_Cfg.h b/Src/Gen4_R-Car_MCAL/2_Trunk/V4H/MCAL-v4h_19.4.0.D_release/rel/modules/can/sample_application/V4H/19_11/include/Can_Cfg.h new file mode 100644 index 00000000..75bc680c --- /dev/null +++ b/Src/Gen4_R-Car_MCAL/2_Trunk/V4H/MCAL-v4h_19.4.0.D_release/rel/modules/can/sample_application/V4H/19_11/include/Can_Cfg.h @@ -0,0 +1,467 @@ +/*============================================================================*/ +/* Project = AUTOSAR Renesas MCAL Components */ +/* Module = Can_Cfg.h */ +/*============================================================================*/ +/* COPYRIGHT */ +/*============================================================================*/ +/* Copyright(c) 2026 Renesas Electronics Corporation. */ +/*============================================================================*/ +/* Purpose: */ +/* This file contains pre-compile time parameters. */ +/* AUTOMATICALLY GENERATED FILE - DO NOT EDIT */ +/* */ +/*============================================================================*/ +/* */ +/* Unless otherwise agreed upon in writing between your company and */ +/* Renesas Electronics Corporation the following shall apply! */ +/* */ +/* Warranty Disclaimer */ +/* */ +/* There is no warranty of any kind whatsoever granted by Renesas. Any */ +/* warranty is expressly disclaimed and excluded by Renesas, either expressed */ +/* or implied, including but not limited to those for non-infringement of */ +/* intellectual property, merchantability and/or fitness for the particular */ +/* purpose. */ +/* */ +/* Renesas shall not have any obligation to maintain, service or provide bug */ +/* fixes for the supplied Product(s) and/or the Application. */ +/* */ +/* Each User is solely responsible for determining the appropriateness of */ +/* using the Product(s) and assumes all risks associated with its exercise */ +/* of rights under this Agreement, including, but not limited to the risks */ +/* and costs of program errors, compliance with applicable laws, damage to */ +/* or loss of data, programs or equipment, and unavailability or */ +/* interruption of operations. */ +/* */ +/* Limitation of Liability */ +/* */ +/* In no event shall Renesas be liable to the User for any incidental, */ +/* consequential, indirect, or punitive damage (including but not limited */ +/* to lost profits) regardless of whether such liability is based on breach */ +/* of contract, tort, strict liability, breach of warranties, failure of */ +/* essential purpose or otherwise and even if advised of the possibility of */ +/* such damages. Renesas shall not be liable for any services or products */ +/* provided by third party vendors, developers or consultants identified or */ +/* referred to the User by Renesas in connection with the Product(s) and/or */ +/* the Application. */ +/* */ +/*============================================================================*/ +/* Environment: */ +/* Devices: V4H */ +/*============================================================================*/ + + +/******************************************************************************* +** Revision Control History ** +*******************************************************************************/ + + + +/******************************************************************************* +** Generation Tool Version ** +*******************************************************************************/ +/* */ +/* TOOL VERSION: CanRCAR.dll version: 1.1.0, MCALConfGen.exe version: 1.2.3 */ +/* */ + + +/******************************************************************************* +** Input File ** +*******************************************************************************/ +/* + * INPUT FILE: C:\Work\Src\Gen4_R-Car_MCAL\2_Trunk\V4H\MCAL-v4h_19.4.0.D_release\rel\modules\can\sample_application\V4H\19_11\config\App_CAN_V4H_Sample.arxml + * C:\Work\Src\Gen4_R-Car_MCAL\2_Trunk\V4H\MCAL-v4h_19.4.0.D_release\rel\modules\can\generator\V4H\R1911_CAN_V4H_BSWMDT.arxml + * C:\Work\Src\Gen4_R-Car_MCAL\2_Trunk\V4H\MCAL-v4h_19.4.0.D_release\rel\V4H\common_family\config\V4H\19_11\MCU_CAN_V4H.arxml + * C:\Work\Src\Gen4_R-Car_MCAL\2_Trunk\V4H\MCAL-v4h_19.4.0.D_release\rel\common\generic\stubs\19_11\Dem\xml\Dem_Can.arxml + * C:\Work\Src\Gen4_R-Car_MCAL\2_Trunk\V4H\MCAL-v4h_19.4.0.D_release\rel\common\generic\stubs\19_11\EcuM\xml\EcuM_Can.arxml + * C:\Work\Src\Gen4_R-Car_MCAL\2_Trunk\V4H\MCAL-v4h_19.4.0.D_release\rel\common\generic\stubs\19_11\Os\xml\Os_Can.arxml + * C:\Work\Src\Gen4_R-Car_MCAL\2_Trunk\V4H\MCAL-v4h_19.4.0.D_release\rel\V4H\common_family\generator\arm\Sample_Application_V4H.trxml + * GENERATED ON: 19 6 2026 - 05:11:38 + */ + + +#ifndef CAN_CFG_H +#define CAN_CFG_H + + +/******************************************************************************* +** Include Section ** +*******************************************************************************/ +#include "ComStack_Types.h" + + +/******************************************************************************* +** MISRA C Rule Violations ** +*******************************************************************************/ +/* 1. MISRA C RULE VIOLATION: */ +/* Message : (7:0791) [U] Macro identifier does not differ from other */ +/* macro identifier(s) (e.g. */ +/* 'CanConf_CanController_CanController') within the */ +/* specified number of significant characters. */ +/* Rule : MISRA-C:2012 Rule-5.4, CERTCCM DCL23 */ +/* Justification : This macro identifier is following AUTOSAR standard rule */ +/* (Symbolic Name or Published Macro's name), */ +/* so this is accepted. */ +/* Verification : However, part of the code is verified manually and it is */ +/* not having any impact. */ +/* Reference : Look for START Msg(7:0791)-1 and */ +/* END Msg(7:0791)-1 tags in the code. */ +/******************************************************************************/ + + +/******************************************************************************* +** Version Information ** +*******************************************************************************/ +/* Autosar Release Version Information. */ +#define CAN_CFG_AR_RELEASE_MAJOR_VERSION 4U +#define CAN_CFG_AR_RELEASE_MINOR_VERSION 5U +#define CAN_CFG_AR_RELEASE_REVISION_VERSION 0U +/* File Version Information. */ +#define CAN_CFG_SW_MAJOR_VERSION 1U +#define CAN_CFG_SW_MINOR_VERSION 2U +#define CAN_AR_VERSION CAN_AR_1911_VERSION + +/******************************************************************************* +** Common Published Information ** +*******************************************************************************/ +#define CAN_AR_RELEASE_MAJOR_VERSION_VALUE 4U +#define CAN_AR_RELEASE_MINOR_VERSION_VALUE 5U +#define CAN_AR_RELEASE_REVISION_VERSION_VALUE 0U +#define CAN_SW_MAJOR_VERSION_VALUE 1U +#define CAN_SW_MINOR_VERSION_VALUE 2U +#define CAN_SW_PATCH_VERSION_VALUE 0U +#define CAN_VENDOR_ID_VALUE 59U +#define CAN_MODULE_ID_VALUE 80U + +/******************************************************************************* +** Global Symbols ** +*******************************************************************************/ + + +/* Pre-compile macro for V4H device */ +#define CAN_V4H_PROC + +/* Pre-compile option for DEM for CAN Driver for Time out value */ +#define CAN_E_TIMEOUT_FAILURE \ + DemConf_DemEventParameter_DemEventParameter + +#define CAN_E_INTERRUPT_CONTROLLER_FAILURE \ + DemConf_DemEventParameter_DemEventParameter_001 + +/* Pre-compile option for Set baudrate API */ +#define CAN_SET_BAUDRATE_API STD_ON + +/* Pre-compile option for Version Info API */ +#define CAN_VERSION_INFO_API STD_ON + +/* Pre-compile option for Development Error Detect */ +#define CAN_DEV_ERROR_DETECT STD_OFF + +/* Pre-compile option for allowing re-initialization with Can_Init API. */ +#define CAN_ALREADY_INIT_DET_CHECK STD_ON + +/* Pre-compile option for Critical Section Protection */ +#define CAN_CRITICAL_SECTION_PROTECTION STD_ON + +/* Pre-compile option for External Module Version Check */ +#define CAN_VERSION_CHECK_EXT_MODULES STD_ON + +/* Enables/Disables the unintended interrupt check in the ISRs */ +#define CAN_UNINTENDED_INTERRUPT_CHECK STD_ON + +/* Pre-compile option for public Icom support */ +#define CAN_PUBLIC_ICOM_SUPPORT STD_ON + +/* Enables/Disables the Error Correct Code safety mechanism. */ +#define CAN_ECC_ERROR_CORRECT STD_ON + +/* Enables/Disables the macro CAN_CR52_PROC for specific device */ +#define CAN_CR52_PROC STD_ON + +/* Pre-compile option for Number of configured Can Module. */ +#define CAN_NO_OF_UNITS 1U + +/* Pre-compile option for Maximum number of Controllers */ +#define CAN_MAX_NUMBER_OF_CONTROLLER (uint8)2 + +/* Pre-compile option for Os Counter ID */ +#define CAN_OS_COUNTER_ID OsCounter + +/* Pre-compile option for Number of configured hardware object handles */ +#define CAN_NO_OF_HOHS 4U + +/* Pre-compile number of CanIcom configuration */ +#define CAN_ICOM_NOCONFIG 1U + +/* Controller ID offset */ +#define CAN_CONTROLLER_OFFSET 0U + +/* Pre-compile option for Can_CheckWakeup API */ +#define CAN_CHECK_WAKEUP_API STD_OFF + +/* Pre-compile option for Change baudrate API */ +#define CAN_CHANGE_BAUDRATE_API STD_OFF + +/* Pre-compile option for RSCANFDn handling */ +#define CAN_RSCANFD_CONFIGURED STD_ON + +/* Pre-compile option for RSCANn handling */ +#define CAN_RSCAN_CONFIGURED STD_OFF + +/* Pre-compile option for Can Wakeup Support */ +#define CAN_WAKEUP_SUPPORT STD_OFF + +/* Pre-compile option for name of callout function */ +#define CAN_LPDU_RECEIVE_CALLOUT_FUNCTION UserCalloutFunction + +/* Pre-compile option for Wakeup Interrupt */ +#define CAN_WAKEUP_POLLING STD_ON + +/* Pre-compile option for Busoff Interrupt */ +#define CAN_BUSOFF_POLLING STD_ON + +/* Pre-compile option for Rx Interrupt */ +#define CAN_RX_POLLING STD_ON + +/* Pre-compile option for Tx Interrupt */ +#define CAN_TX_POLLING STD_ON + +/* Pre-compile option for Receive BUFFER is configured */ +#define CAN_RX_BUFFER STD_ON + +/* Pre-compile option for Transmit BUFFER is configured */ +#define CAN_TX_BUFFER STD_ON + +/* Pre-compile option for Receive FIFO is configured */ +#define CAN_RX_FIFO STD_OFF + +/* Pre-compile option for Receive FIFO is configured in Tx/RX FIFO */ +#define CAN_RX_COMFIFO STD_ON + +/* Pre-compile option for Transmit FIFO is configured in Tx/RX FIFO */ +#define CAN_TX_COMFIFO STD_OFF + +/* Pre-compile option for GATEWAY is configured in Tx/RX FIFO */ +#define CAN_GATEWAY_COMFIFO STD_OFF + +/* Pre-compile option for Transmit QUEUE is configured */ +#define CAN_TX_QUEUE STD_OFF + +/* Pre-compile option for GATEWAY is configured in Transmit QUEUE */ +#define CAN_GATEWAY_QUEUE STD_OFF + +/* Pre-compile option for Receive Object is configured */ +#define CAN_RX_OBJECT STD_ON + +/* The number of main function periods used */ +#define CAN_NUMBER_OF_MAINFUNCTIONS 1U + +/* Pre-compile option for trigger transmit function is configured */ +#define CAN_TRIGGER_TRANSMIT_FUNCTION STD_OFF + +/* CAT2 ISR category using */ +#define CAN_ISR_CATEGORY_2 STD_OFF + +/* Enables/Disables the interrupt consistency check in the ISRs */ +#define CAN_INTERRUPT_CONSISTENCY_CHECK STD_OFF + +/* Enables/Disables the Wakeup Factor Clear in the ISR */ +#define CAN_WAKE_UP_FACTOR_CLEAR_ISR STD_OFF + +/* Enables/Disables Virtual Machine in the ISR */ +#define CAN_VIRTUAL_MACHINE_ENABLE STD_OFF + +/* Enables/Disables hardware for FFI mode */ +#define CAN_ACCESS_HW_ENABLE STD_ON + +/* Enables/Disables Can RAM test API */ +#define CAN_RAMTEST_API STD_ON + +/* Enables/Disables Can Self Test API */ +#define CAN_SELFTEST_API STD_ON + +/* Can Maximum RAM Pages Hardware */ +#define CAN_MAX_RAMPAGES_HARDWARE 868U + +/* Pre-compile option for Can Time Sync Capture feature */ +#define CAN_TIME_SYNC_CAPTURE_EN STD_OFF + +/* Pre-compile option for IcomPayloadLengthError */ +#define CAN_ICOM_PAYLOAD_LENGTH_ERROR_SUPPORT STD_ON + +/* Pre-compile option for name of ICOM callout function */ +#define CAN_ICOM_CALLOUT_FUNCTION Can_IcomCallOut + +/* Pre-compile option for Timeout Count */ +#define CAN_TIMEOUT_COUNT 10000U + +/* Pre-compile option for OS Counter Max Value */ +#define CAN_OS_COUNTER_MAX_VALUE 4294967295U + +/* maximum value of all number configured CanIcomRxMessage */ +#define CAN_ICOM_MAX_CONFIGURED_RX_MSG (uint8)3 + +/* Pre-compile option for hardware unit configured */ +#define CAN_PHYIDX_UNIT0 0U + +/* Pre-compile option for Rx FIFO Interrupt */ +#define CAN_RSCAN0_RXFIFO_INTERRUPT STD_OFF +#define CAN_RSCAN1_RXFIFO_INTERRUPT STD_OFF + +/* Pre-compile option for Global Error Interrupt */ + +/* Pre-compile option for Busoff Interrupt */ +#define CAN_CONTROLLER0_BUSOFF_INTERRUPT STD_OFF +#define CAN_CONTROLLER1_BUSOFF_INTERRUPT STD_OFF +#define CAN_CONTROLLER2_BUSOFF_INTERRUPT STD_OFF +#define CAN_CONTROLLER3_BUSOFF_INTERRUPT STD_OFF +#define CAN_CONTROLLER4_BUSOFF_INTERRUPT STD_OFF +#define CAN_CONTROLLER5_BUSOFF_INTERRUPT STD_OFF +#define CAN_CONTROLLER6_BUSOFF_INTERRUPT STD_OFF +#define CAN_CONTROLLER7_BUSOFF_INTERRUPT STD_OFF +#define CAN_CONTROLLER8_BUSOFF_INTERRUPT STD_OFF +#define CAN_CONTROLLER9_BUSOFF_INTERRUPT STD_OFF +#define CAN_CONTROLLER10_BUSOFF_INTERRUPT STD_OFF +#define CAN_CONTROLLER11_BUSOFF_INTERRUPT STD_OFF +#define CAN_CONTROLLER12_BUSOFF_INTERRUPT STD_OFF +#define CAN_CONTROLLER13_BUSOFF_INTERRUPT STD_OFF +#define CAN_CONTROLLER14_BUSOFF_INTERRUPT STD_OFF +#define CAN_CONTROLLER15_BUSOFF_INTERRUPT STD_OFF + +/* Pre-compile option for Wakeup Interrupt */ +#define CAN_CONTROLLER0_WAKEUP_INTERRUPT STD_OFF +#define CAN_CONTROLLER1_WAKEUP_INTERRUPT STD_OFF +#define CAN_CONTROLLER2_WAKEUP_INTERRUPT STD_OFF +#define CAN_CONTROLLER3_WAKEUP_INTERRUPT STD_OFF +#define CAN_CONTROLLER4_WAKEUP_INTERRUPT STD_OFF +#define CAN_CONTROLLER5_WAKEUP_INTERRUPT STD_OFF +#define CAN_CONTROLLER6_WAKEUP_INTERRUPT STD_OFF +#define CAN_CONTROLLER7_WAKEUP_INTERRUPT STD_OFF +#define CAN_CONTROLLER8_WAKEUP_INTERRUPT STD_OFF +#define CAN_CONTROLLER9_WAKEUP_INTERRUPT STD_OFF +#define CAN_CONTROLLER10_WAKEUP_INTERRUPT STD_OFF +#define CAN_CONTROLLER11_WAKEUP_INTERRUPT STD_OFF +#define CAN_CONTROLLER12_WAKEUP_INTERRUPT STD_OFF +#define CAN_CONTROLLER13_WAKEUP_INTERRUPT STD_OFF +#define CAN_CONTROLLER14_WAKEUP_INTERRUPT STD_OFF +#define CAN_CONTROLLER15_WAKEUP_INTERRUPT STD_OFF + +/* Pre-compile option for Rx Interrupt */ +#define CAN_CONTROLLER0_RX_INTERRUPT STD_OFF +#define CAN_CONTROLLER1_RX_INTERRUPT STD_ON +#define CAN_CONTROLLER2_RX_INTERRUPT STD_OFF +#define CAN_CONTROLLER3_RX_INTERRUPT STD_OFF +#define CAN_CONTROLLER4_RX_INTERRUPT STD_OFF +#define CAN_CONTROLLER5_RX_INTERRUPT STD_OFF +#define CAN_CONTROLLER6_RX_INTERRUPT STD_OFF +#define CAN_CONTROLLER7_RX_INTERRUPT STD_OFF +#define CAN_CONTROLLER8_RX_INTERRUPT STD_OFF +#define CAN_CONTROLLER9_RX_INTERRUPT STD_OFF +#define CAN_CONTROLLER10_RX_INTERRUPT STD_OFF +#define CAN_CONTROLLER11_RX_INTERRUPT STD_OFF +#define CAN_CONTROLLER12_RX_INTERRUPT STD_OFF +#define CAN_CONTROLLER13_RX_INTERRUPT STD_OFF +#define CAN_CONTROLLER14_RX_INTERRUPT STD_OFF +#define CAN_CONTROLLER15_RX_INTERRUPT STD_OFF + +/* Pre-compile option for Tx Interrupt */ +#define CAN_CONTROLLER0_TX_INTERRUPT STD_OFF +#define CAN_CONTROLLER1_TX_INTERRUPT STD_ON +#define CAN_CONTROLLER2_TX_INTERRUPT STD_OFF +#define CAN_CONTROLLER3_TX_INTERRUPT STD_OFF +#define CAN_CONTROLLER4_TX_INTERRUPT STD_OFF +#define CAN_CONTROLLER5_TX_INTERRUPT STD_OFF +#define CAN_CONTROLLER6_TX_INTERRUPT STD_OFF +#define CAN_CONTROLLER7_TX_INTERRUPT STD_OFF +#define CAN_CONTROLLER8_TX_INTERRUPT STD_OFF +#define CAN_CONTROLLER9_TX_INTERRUPT STD_OFF +#define CAN_CONTROLLER10_TX_INTERRUPT STD_OFF +#define CAN_CONTROLLER11_TX_INTERRUPT STD_OFF +#define CAN_CONTROLLER12_TX_INTERRUPT STD_OFF +#define CAN_CONTROLLER13_TX_INTERRUPT STD_OFF +#define CAN_CONTROLLER14_TX_INTERRUPT STD_OFF +#define CAN_CONTROLLER15_TX_INTERRUPT STD_OFF + +/* Pre-compile option for Rx VM Interrupt */ +#define CAN_VM0_RX_INTERRUPT STD_OFF +#define CAN_VM1_RX_INTERRUPT STD_OFF +#define CAN_VM2_RX_INTERRUPT STD_OFF +#define CAN_VM3_RX_INTERRUPT STD_OFF +#define CAN_VM4_RX_INTERRUPT STD_OFF +#define CAN_VM5_RX_INTERRUPT STD_OFF +#define CAN_VM6_RX_INTERRUPT STD_OFF +#define CAN_VM7_RX_INTERRUPT STD_OFF +#define CAN_VM8_RX_INTERRUPT STD_OFF +#define CAN_VM9_RX_INTERRUPT STD_OFF +#define CAN_VM10_RX_INTERRUPT STD_OFF +#define CAN_VM11_RX_INTERRUPT STD_OFF +#define CAN_VM12_RX_INTERRUPT STD_OFF +#define CAN_VM13_RX_INTERRUPT STD_OFF +#define CAN_VM14_RX_INTERRUPT STD_OFF +#define CAN_VM15_RX_INTERRUPT STD_OFF + +/* Pre-compile option for Tx VM Interrupt */ +#define CAN_VM0_TX_INTERRUPT STD_OFF +#define CAN_VM1_TX_INTERRUPT STD_OFF +#define CAN_VM2_TX_INTERRUPT STD_OFF +#define CAN_VM3_TX_INTERRUPT STD_OFF +#define CAN_VM4_TX_INTERRUPT STD_OFF +#define CAN_VM5_TX_INTERRUPT STD_OFF +#define CAN_VM6_TX_INTERRUPT STD_OFF +#define CAN_VM7_TX_INTERRUPT STD_OFF +#define CAN_VM8_TX_INTERRUPT STD_OFF +#define CAN_VM9_TX_INTERRUPT STD_OFF +#define CAN_VM10_TX_INTERRUPT STD_OFF +#define CAN_VM11_TX_INTERRUPT STD_OFF +#define CAN_VM12_TX_INTERRUPT STD_OFF +#define CAN_VM13_TX_INTERRUPT STD_OFF +#define CAN_VM14_TX_INTERRUPT STD_OFF +#define CAN_VM15_TX_INTERRUPT STD_OFF + + +/******************************************************************************* +** Global Data Types ** +*******************************************************************************/ + + + +/******************************************************************************* +** Global Data ** +*******************************************************************************/ + + + +/******************************************************************************* +** Function Prototypes ** +*******************************************************************************/ + + +/* CAN Controller Configuration Handle */ +#define CanConf_CanController_CanController0 (uint8)0 +/* MISRA Violation: START Msg(7:0791)-1 */ +#define CanConf_CanController_CanController1 (uint8)1 +/* END Msg(7:0791)-1 */ + +/* Hardware Objects Configuration Handle */ +#define CanConf_CanHardwareObject_CanHardwareObject0 (Can_HwHandleType)0 +/* MISRA Violation: START Msg(7:0791)-1 */ +#define CanConf_CanHardwareObject_CanHardwareObject1 (Can_HwHandleType)1 +/* END Msg(7:0791)-1 */ +/* MISRA Violation: START Msg(7:0791)-1 */ +#define CanConf_CanHardwareObject_CanHardwareObject2 (Can_HwHandleType)2 +/* END Msg(7:0791)-1 */ +/* MISRA Violation: START Msg(7:0791)-1 */ +#define CanConf_CanHardwareObject_CanHardwareObject3 (Can_HwHandleType)3 +/* END Msg(7:0791)-1 */ + +/* Configuration Set Handles */ +#define Can_Config (&Can_GaaConfig[0]) + + +#endif /* CAN_CFG_H */ + + +/******************************************************************************* +** End of File ** +*******************************************************************************/ + diff --git a/Src/Gen4_R-Car_MCAL/2_Trunk/V4H/MCAL-v4h_19.4.0.D_release/rel/modules/can/sample_application/V4H/19_11/src/Can_Lcfg.c b/Src/Gen4_R-Car_MCAL/2_Trunk/V4H/MCAL-v4h_19.4.0.D_release/rel/modules/can/sample_application/V4H/19_11/src/Can_Lcfg.c new file mode 100644 index 00000000..fecb586e --- /dev/null +++ b/Src/Gen4_R-Car_MCAL/2_Trunk/V4H/MCAL-v4h_19.4.0.D_release/rel/modules/can/sample_application/V4H/19_11/src/Can_Lcfg.c @@ -0,0 +1,395 @@ +/*============================================================================*/ +/* Project = AUTOSAR Renesas MCAL Components */ +/* Module = Can_Lcfg.c */ +/*============================================================================*/ +/* COPYRIGHT */ +/*============================================================================*/ +/* Copyright(c) 2026 Renesas Electronics Corporation. */ +/*============================================================================*/ +/* Purpose: */ +/* This file contains link time parameters. */ +/* AUTOMATICALLY GENERATED FILE - DO NOT EDIT */ +/* */ +/*============================================================================*/ +/* */ +/* Unless otherwise agreed upon in writing between your company and */ +/* Renesas Electronics Corporation the following shall apply! */ +/* */ +/* Warranty Disclaimer */ +/* */ +/* There is no warranty of any kind whatsoever granted by Renesas. Any */ +/* warranty is expressly disclaimed and excluded by Renesas, either expressed */ +/* or implied, including but not limited to those for non-infringement of */ +/* intellectual property, merchantability and/or fitness for the particular */ +/* purpose. */ +/* */ +/* Renesas shall not have any obligation to maintain, service or provide bug */ +/* fixes for the supplied Product(s) and/or the Application. */ +/* */ +/* Each User is solely responsible for determining the appropriateness of */ +/* using the Product(s) and assumes all risks associated with its exercise */ +/* of rights under this Agreement, including, but not limited to the risks */ +/* and costs of program errors, compliance with applicable laws, damage to */ +/* or loss of data, programs or equipment, and unavailability or */ +/* interruption of operations. */ +/* */ +/* Limitation of Liability */ +/* */ +/* In no event shall Renesas be liable to the User for any incidental, */ +/* consequential, indirect, or punitive damage (including but not limited */ +/* to lost profits) regardless of whether such liability is based on breach */ +/* of contract, tort, strict liability, breach of warranties, failure of */ +/* essential purpose or otherwise and even if advised of the possibility of */ +/* such damages. Renesas shall not be liable for any services or products */ +/* provided by third party vendors, developers or consultants identified or */ +/* referred to the User by Renesas in connection with the Product(s) and/or */ +/* the Application. */ +/* */ +/*============================================================================*/ +/* Environment: */ +/* Devices: V4H */ +/*============================================================================*/ + + +/******************************************************************************* +** Revision Control History ** +*******************************************************************************/ + + + +/******************************************************************************* +** Generation Tool Version ** +*******************************************************************************/ +/* */ +/* TOOL VERSION: CanRCAR.dll version: 1.1.0, MCALConfGen.exe version: 1.2.3 */ +/* */ + + +/******************************************************************************* +** Input File ** +*******************************************************************************/ +/* + * INPUT FILE: C:\Work\Src\Gen4_R-Car_MCAL\2_Trunk\V4H\MCAL-v4h_19.4.0.D_release\rel\modules\can\sample_application\V4H\19_11\config\App_CAN_V4H_Sample.arxml + * C:\Work\Src\Gen4_R-Car_MCAL\2_Trunk\V4H\MCAL-v4h_19.4.0.D_release\rel\modules\can\generator\V4H\R1911_CAN_V4H_BSWMDT.arxml + * C:\Work\Src\Gen4_R-Car_MCAL\2_Trunk\V4H\MCAL-v4h_19.4.0.D_release\rel\V4H\common_family\config\V4H\19_11\MCU_CAN_V4H.arxml + * C:\Work\Src\Gen4_R-Car_MCAL\2_Trunk\V4H\MCAL-v4h_19.4.0.D_release\rel\common\generic\stubs\19_11\Dem\xml\Dem_Can.arxml + * C:\Work\Src\Gen4_R-Car_MCAL\2_Trunk\V4H\MCAL-v4h_19.4.0.D_release\rel\common\generic\stubs\19_11\EcuM\xml\EcuM_Can.arxml + * C:\Work\Src\Gen4_R-Car_MCAL\2_Trunk\V4H\MCAL-v4h_19.4.0.D_release\rel\common\generic\stubs\19_11\Os\xml\Os_Can.arxml + * C:\Work\Src\Gen4_R-Car_MCAL\2_Trunk\V4H\MCAL-v4h_19.4.0.D_release\rel\V4H\common_family\generator\arm\Sample_Application_V4H.trxml + * GENERATED ON: 19 6 2026 - 05:11:38 + */ + + +/******************************************************************************* +** Instance Index ** +*******************************************************************************/ + +/******************************************************************************* +** Include Section ** +*******************************************************************************/ +/* CAN Post Build configuration header */ +/* MISRA Violation: START Msg(2:0857)-2 */ +#include "Can.h" +#include "Can_LTTypes.h" +/* END Msg(2:0857)-2 */ + + +/******************************************************************************* +** MISRA C Rule Violations ** +*******************************************************************************/ +/* 1. MISRA C RULE VIOLATION: */ +/* Message : (7:0791) [U] Macro identifier does not differ from other */ +/* macro identifier(s) (e.g. */ +/* 'CanConf_CanController_CanController') within the */ +/* specified number of significant characters. */ +/* Rule : MISRA-C:2012 Rule-5.4, CERTCCM DCL23 */ +/* Justification : This macro identifier is following AUTOSAR standard rule */ +/* (Symbolic Name or Published Macro's name), */ +/* so this is accepted. */ +/* Verification : However, part of the code is verified manually and it is */ +/* not having any impact. */ +/* Reference : Look for START Msg(7:0791)-1 and */ +/* END Msg(7:0791)-1 tags in the code. */ +/******************************************************************************/ +/* 2. MISRA C RULE VIOLATION: */ +/* Message : (2:0857) [L] Number of macro definitions exceeds 1024 - */ +/* program does not conform strictly to ISO:C90. */ +/* Rule : MISRA-C:2012 Dir-1.1 */ +/* Justification : The number of macro depend on module code size. There is */ +/* no issue when number of macro is over 1024 */ +/* Verification : However, part of the code is verified manually and it is */ +/* not having any impact. */ +/* Reference : Look for START Msg(2:0857)-2 and */ +/* END Msg(2:0857)-2 tags in the code. */ +/******************************************************************************/ +/* 3. MISRA C RULE VIOLATION: */ +/* Message : (4:5087) Use of #include directive after code fragment. */ +/* Rule : MISRA-C:2012 Rule-20.1 */ +/* Justification : This is done as per Memory Requirement, */ +/* (MEMMAP003 - Specification of Memory Mapping). */ +/* Verification : However, part of the code is verified manually and it is */ +/* not having any impact. */ +/* Reference : Look for START Msg(4:5087)-3 and */ +/* END Msg(4:5087)-3 tags in the code. */ +/******************************************************************************/ +/* 4. MISRA C RULE VIOLATION: */ +/* Message : (2:0303) Cast between a pointer to volatile object and an */ +/* integral type. */ +/* Rule : MISRA-C:2012 Rule-11.4, CERTCCM INT36, CWE-398, CWE-569 */ +/* Justification : Typecasting is done as per the register size, */ +/* to access hardware registers. */ +/* Verification : However, part of the code is verified manually and it is */ +/* not having any impact. */ +/* Reference : Look for START Msg(2:0303)-4 and */ +/* END Msg(2:0303)-4 tags in the code. */ +/******************************************************************************/ +/* 5. MISRA C RULE VIOLATION: */ +/* Message : (1:1531) The object '%s' is referenced in only one */ +/* translation unit - but not the one in which it is defined. */ +/* Rule : MISRA-C:2012 Rule-8.7, CERTCCM DCL15, DCL19, CWE-398, */ +/* CWE-569. */ +/* Justification : Followed coding rules, the objects (global variable/const) */ +/* is define in separated source file, */ +/* so this could be accepted */ +/* Verification : However, part of the code is verified manually and it is */ +/* not having any impact. */ +/* Reference : Look for START Msg(1:1531)-5 and */ +/* END Msg(1:1531)-5 tags in the code. */ +/******************************************************************************/ +/* 6. MISRA C RULE VIOLATION: */ +/* Message : (2:3432) Simple macro argument expression is not */ +/* parenthesized. */ +/* Rule : MISRA-C:2012 Rule-20.7, CWE-398, CWE-569 */ +/* Justification : Compiler keyword (macro) is defined and used followed */ +/* AUTOSAR standard rule. It is accepted. */ +/* Verification : However, part of the code is verified manually */ +/* and it is not having any impact. */ +/* Reference : Look for START Msg(2:3432)-6 and */ +/* END Msg(2:3432)-6 tags in the code. */ +/******************************************************************************/ + + +/******************************************************************************* +** Version Information ** +*******************************************************************************/ +/* Autosar Release Version Information */ +#define CAN_LCFG_C_AR_RELEASE_MAJOR_VERSION 4U +#define CAN_LCFG_C_AR_RELEASE_MINOR_VERSION 5U +#define CAN_LCFG_C_AR_RELEASE_REVISION_VERSION 0U +/* File Version Information */ +#define CAN_LCFG_C_SW_MAJOR_VERSION 1U +#define CAN_LCFG_C_SW_MINOR_VERSION 2U + +/******************************************************************************* +** Version Check ** +*******************************************************************************/ +#if (CAN_LTTYPES_AR_RELEASE_MAJOR_VERSION != \ + CAN_LCFG_C_AR_RELEASE_MAJOR_VERSION) + #error "Can_Lcfg.c : Mismatch in Release Major Version" +#endif + +#if (CAN_LTTYPES_AR_RELEASE_MINOR_VERSION != \ + CAN_LCFG_C_AR_RELEASE_MINOR_VERSION) + #error "Can_Lcfg.c : Mismatch in Release Minor Version" +#endif + +#if (CAN_LTTYPES_AR_RELEASE_REVISION_VERSION != \ + CAN_LCFG_C_AR_RELEASE_REVISION_VERSION) + #error "Can_Lcfg.c : Mismatch in Release Revision Version" +#endif + +#if (CAN_LTTYPES_SW_MAJOR_VERSION != CAN_LCFG_C_SW_MAJOR_VERSION) + #error "Can_Lcfg.c : Mismatch in Software Major Version" +#endif + +#if (CAN_LTTYPES_SW_MINOR_VERSION != CAN_LCFG_C_SW_MINOR_VERSION) + #error "Can_Lcfg.c : Mismatch in Software Minor Version" +#endif + + +/******************************************************************************* +** Global Data Types ** +*******************************************************************************/ +/* MISRA Violation: START Msg(7:0791)-1 */ +#define CAN_RSCAN_START_SEC_CONFIG_DATA_8 +/* END Msg(7:0791)-1 */ +#include "Can_MemMap.h" + + + +/* Table to acquire index of config table from physical controller number */ +/* MISRA Violation: START Msg(1:1531)-3 */ +CONST(uint8, CAN_RSCAN_CONST) Can_GaaPhysicalControllerToIndex0[] = +{ + /* Index 0 */ + 0x00U, + + /* Index 1 */ + 0x01U +}; +/* END Msg(1:1531)-3 */ + + + +/* MISRA Violation: START Msg(7:0791)-1 */ +#define CAN_RSCAN_STOP_SEC_CONFIG_DATA_8 +/* END Msg(7:0791)-1 */ +/* MISRA Violation: START Msg(4:5087)-3 */ +#include "Can_MemMap.h" +/* END Msg(4:5087)-3 */ + + +#define CAN_RSCAN_START_SEC_CONFIG_DATA_UNSPECIFIED +/* MISRA Violation: START Msg(4:5087)-3 */ +#include "Can_MemMap.h" +/* END Msg(4:5087)-3 */ + + +/* Global array for ControllerConfigType structure */ +/* MISRA Violation: START Msg(1:1531)-5 */ +CONST(Can_ControllerPCConfigType, CAN_CONFIG_DATA) Can_GaaControllerPCConfig0[] + = +{ + /* Index: 0 - CanController0 */ + { + /* blActivation */ + CAN_TRUE, + + /* ucUnit */ + 0x00U, + + /* ucCh */ + 0x00U, + + /* ucIntEnable */ + CAN_INT_DISABLED, + + /* ulCTR */ + CAN_RSCAN_BOM_HALT_BUSOFF_ENTRY, + + /* ulTHLCC */ + CAN_RSCAN_THLDTE, + + /* pICRec */ + /* MISRA Violation: START Msg(2:0303)-4 */ + /* MISRA Violation: START Msg(2:3432)-6 */ + (P2VAR(volatile uint16, AUTOMATIC, REGSPACE))0xF1000134UL, + /* END Msg(2:3432)-6 */ + /* END Msg(2:0303)-4 */ + + /* pICTx */ + /* MISRA Violation: START Msg(2:0303)-4 */ + /* MISRA Violation: START Msg(2:3432)-6 */ + (P2VAR(volatile uint16, AUTOMATIC, REGSPACE))0xF1000134UL, + /* END Msg(2:3432)-6 */ + /* END Msg(2:0303)-4 */ + + /* pICErr */ + /* MISRA Violation: START Msg(2:0303)-4 */ + /* MISRA Violation: START Msg(2:3432)-6 */ + (P2VAR(volatile uint16, AUTOMATIC, REGSPACE))0xF1000134UL + /* END Msg(2:3432)-6 */ + /* END Msg(2:0303)-4 */ + }, + /* Index: 1 - CanController1 */ + { + /* blActivation */ + CAN_TRUE, + + /* ucUnit */ + 0x00U, + + /* ucCh */ + 0x01U, + + /* ucIntEnable */ + CAN_CHECK_INT_TX | + CAN_CHECK_INT_RX, + + /* ulCTR */ + CAN_RSCAN_BOM_HALT_BUSOFF_ENTRY, + + /* ulTHLCC */ + CAN_RSCAN_THLDTE, + + /* pICRec */ + /* MISRA Violation: START Msg(2:0303)-4 */ + /* MISRA Violation: START Msg(2:3432)-6 */ + (P2VAR(volatile uint16, AUTOMATIC, REGSPACE))0xF1000134UL, + /* END Msg(2:3432)-6 */ + /* END Msg(2:0303)-4 */ + + /* pICTx */ + /* MISRA Violation: START Msg(2:0303)-4 */ + /* MISRA Violation: START Msg(2:3432)-6 */ + (P2VAR(volatile uint16, AUTOMATIC, REGSPACE))0xF1000134UL, + /* END Msg(2:3432)-6 */ + /* END Msg(2:0303)-4 */ + + /* pICErr */ + /* MISRA Violation: START Msg(2:0303)-4 */ + /* MISRA Violation: START Msg(2:3432)-6 */ + (P2VAR(volatile uint16, AUTOMATIC, REGSPACE))0xF1000134UL + /* END Msg(2:3432)-6 */ + /* END Msg(2:0303)-4 */ + } +}; +/* END Msg(1:1531)-5 */ + +/* Register Address Configuration */ +CONST(Can_RegisterSetType, CAN_CONFIG_DATA) Can_GaaRegs[] = +{ + /* Index: 0 - RSCANFD0 */ + { + /* enMacroType */ + CAN_MACRO_RSCANFD, + + /* pCmn */ + /* MISRA Violation: START Msg(2:0303)-4 */ + /* MISRA Violation: START Msg(2:3432)-6 */ + (P2VAR(volatile Can_CommonRegType, AUTOMATIC, REGSPACE))0xE6660000UL, + /* END Msg(2:3432)-6 */ + /* END Msg(2:0303)-4 */ + + /* pRR */ + /* MISRA Violation: START Msg(2:0303)-4 */ + /* MISRA Violation: START Msg(2:3432)-6 */ + (P2VAR(volatile Can_RRuleRegType, AUTOMATIC, REGSPACE))0xE6661800UL, + /* END Msg(2:3432)-6 */ + /* END Msg(2:0303)-4 */ + + /* pFD */ + /* MISRA Violation: START Msg(2:0303)-4 */ + /* MISRA Violation: START Msg(2:3432)-6 */ + (P2VAR(volatile Can_FDRegType, AUTOMATIC, REGSPACE))0xE6661400UL, + /* END Msg(2:3432)-6 */ + /* END Msg(2:0303)-4 */ + + /* pEC710CTLReg */ + /* MISRA Violation: START Msg(2:0303)-4 */ + /* MISRA Violation: START Msg(2:3432)-6 */ + (P2VAR(volatile uint32, AUTOMATIC, REGSPACE))0xE66C8000UL + /* END Msg(2:3432)-6 */ + /* END Msg(2:0303)-4 */ + } +}; + +#define CAN_RSCAN_STOP_SEC_CONFIG_DATA_UNSPECIFIED +/* MISRA Violation: START Msg(4:5087)-3 */ +#include "Can_MemMap.h" +/* END Msg(4:5087)-3 */ + + + +/******************************************************************************* +** Global Data ** +*******************************************************************************/ + +/******************************************************************************* +** Function Definitions ** +*******************************************************************************/ + +/******************************************************************************* +** End of File ** +*******************************************************************************/ + diff --git a/Src/Gen4_R-Car_MCAL/2_Trunk/V4H/MCAL-v4h_19.4.0.D_release/rel/modules/can/sample_application/V4H/19_11/src/Can_PBcfg.c b/Src/Gen4_R-Car_MCAL/2_Trunk/V4H/MCAL-v4h_19.4.0.D_release/rel/modules/can/sample_application/V4H/19_11/src/Can_PBcfg.c new file mode 100644 index 00000000..7a4a12af --- /dev/null +++ b/Src/Gen4_R-Car_MCAL/2_Trunk/V4H/MCAL-v4h_19.4.0.D_release/rel/modules/can/sample_application/V4H/19_11/src/Can_PBcfg.c @@ -0,0 +1,786 @@ +/*============================================================================*/ +/* Project = AUTOSAR Renesas MCAL Components */ +/* Module = Can_PBcfg.c */ +/*============================================================================*/ +/* COPYRIGHT */ +/*============================================================================*/ +/* Copyright(c) 2026 Renesas Electronics Corporation. */ +/*============================================================================*/ +/* Purpose: */ +/* This file contains post-build time parameters. */ +/* AUTOMATICALLY GENERATED FILE - DO NOT EDIT */ +/* */ +/*============================================================================*/ +/* */ +/* Unless otherwise agreed upon in writing between your company and */ +/* Renesas Electronics Corporation the following shall apply! */ +/* */ +/* Warranty Disclaimer */ +/* */ +/* There is no warranty of any kind whatsoever granted by Renesas. Any */ +/* warranty is expressly disclaimed and excluded by Renesas, either expressed */ +/* or implied, including but not limited to those for non-infringement of */ +/* intellectual property, merchantability and/or fitness for the particular */ +/* purpose. */ +/* */ +/* Renesas shall not have any obligation to maintain, service or provide bug */ +/* fixes for the supplied Product(s) and/or the Application. */ +/* */ +/* Each User is solely responsible for determining the appropriateness of */ +/* using the Product(s) and assumes all risks associated with its exercise */ +/* of rights under this Agreement, including, but not limited to the risks */ +/* and costs of program errors, compliance with applicable laws, damage to */ +/* or loss of data, programs or equipment, and unavailability or */ +/* interruption of operations. */ +/* */ +/* Limitation of Liability */ +/* */ +/* In no event shall Renesas be liable to the User for any incidental, */ +/* consequential, indirect, or punitive damage (including but not limited */ +/* to lost profits) regardless of whether such liability is based on breach */ +/* of contract, tort, strict liability, breach of warranties, failure of */ +/* essential purpose or otherwise and even if advised of the possibility of */ +/* such damages. Renesas shall not be liable for any services or products */ +/* provided by third party vendors, developers or consultants identified or */ +/* referred to the User by Renesas in connection with the Product(s) and/or */ +/* the Application. */ +/* */ +/*============================================================================*/ +/* Environment: */ +/* Devices: V4H */ +/*============================================================================*/ + + +/******************************************************************************* +** Revision Control History ** +*******************************************************************************/ + + + +/******************************************************************************* +** Generation Tool Version ** +*******************************************************************************/ +/* */ +/* TOOL VERSION: CanRCAR.dll version: 1.1.0, MCALConfGen.exe version: 1.2.3 */ +/* */ + + +/******************************************************************************* +** Input File ** +*******************************************************************************/ +/* + * INPUT FILE: C:\Work\Src\Gen4_R-Car_MCAL\2_Trunk\V4H\MCAL-v4h_19.4.0.D_release\rel\modules\can\sample_application\V4H\19_11\config\App_CAN_V4H_Sample.arxml + * C:\Work\Src\Gen4_R-Car_MCAL\2_Trunk\V4H\MCAL-v4h_19.4.0.D_release\rel\modules\can\generator\V4H\R1911_CAN_V4H_BSWMDT.arxml + * C:\Work\Src\Gen4_R-Car_MCAL\2_Trunk\V4H\MCAL-v4h_19.4.0.D_release\rel\V4H\common_family\config\V4H\19_11\MCU_CAN_V4H.arxml + * C:\Work\Src\Gen4_R-Car_MCAL\2_Trunk\V4H\MCAL-v4h_19.4.0.D_release\rel\common\generic\stubs\19_11\Dem\xml\Dem_Can.arxml + * C:\Work\Src\Gen4_R-Car_MCAL\2_Trunk\V4H\MCAL-v4h_19.4.0.D_release\rel\common\generic\stubs\19_11\EcuM\xml\EcuM_Can.arxml + * C:\Work\Src\Gen4_R-Car_MCAL\2_Trunk\V4H\MCAL-v4h_19.4.0.D_release\rel\common\generic\stubs\19_11\Os\xml\Os_Can.arxml + * C:\Work\Src\Gen4_R-Car_MCAL\2_Trunk\V4H\MCAL-v4h_19.4.0.D_release\rel\V4H\common_family\generator\arm\Sample_Application_V4H.trxml + * GENERATED ON: 19 6 2026 - 05:11:38 + */ + + +/******************************************************************************* +** Instance Index ** +*******************************************************************************/ + +/******************************************************************************* +** Include Section ** +*******************************************************************************/ +/* CAN Post Build configuration header */ +/* MISRA Violation: START Msg(2:0857)-2 */ +#include "Can.h" +#include "Can_PBTypes.h" +/* END Msg(2:0857)-2 */ +#include "Can_LTTypes.h" + + +/******************************************************************************* +** MISRA C Rule Violations ** +*******************************************************************************/ +/* 1. MISRA C RULE VIOLATION: */ +/* Message : (2:0315) [I] Implicit conversion from a pointer to */ +/* object type to a pointer to void. */ +/* Rule : MISRA-C:2012 Dir-1.1, CWE-188, CWE-398, CWE-569 */ +/* Justification : Typecasting is done as per the register size, */ +/* to access hardware registers. */ +/* Verification : However, part of the code is verified manually and */ +/* it is not having any impact. */ +/* Reference : Look for START Msg(2:0315)-1 and */ +/* END Msg(2:0315)-1 tags in the code. */ +/******************************************************************************/ +/* 2. MISRA C RULE VIOLATION: */ +/* Message : (2:0857) [L] Number of macro definitions exceeds 1024 */ +/* - program does not conform strictly to ISO:C90. */ +/* Rule : MISRA-C:2012 Dir-1.1 */ +/* Justification : The number of macro depend on module code size. There is */ +/* no issue when number of macro is over 1024. */ +/* Verification : However, part of the code is verified manually */ +/* and it is not having any impact. */ +/* Reference : Look for START Msg(2:0857)-2 and */ +/* END Msg(2:0857)-2 tags in the code. */ +/******************************************************************************/ +/* 3. MISRA C RULE VIOLATION: */ +/* Message : (4:5087) Use of #include directive after code fragment. */ +/* Rule : MISRA-C:2012 Rule-20.1 */ +/* Justification : This is done as per Memory Requirement, (MEMMAP003 - */ +/* Specification of Memory Mapping). */ +/* Verification : However, part of the code is verified manually */ +/* and it is not having any impact. */ +/* Reference : Look for START Msg(4:5087)-3 and */ +/* END Msg(4:5087)-3 tags in the code. */ +/******************************************************************************/ +/* 4. MISRA C RULE VIOLATION: */ +/* Message : (1:1502) The object '%1s' is defined but */ +/* is not used within this project. */ +/* Rule : MISRA C:2012 Rule-2.8, CWE Rule CWE-398, CWE-569, */ +/* CERTC Rule MSC13 */ +/* Justification : Array is used in another part of driver code. */ +/* There is no problem in use */ +/* Verification : However, part of the code is verified manually */ +/* and it is not having any impact. */ +/* Reference : Look for START Msg(1:1502)-4 and */ +/* END Msg(1:1502)-4 tags in the code. */ +/******************************************************************************/ + + +/******************************************************************************* +** Version Information ** +*******************************************************************************/ +/* Autosar Release Version Information */ +#define CAN_PBCFG_C_AR_RELEASE_MAJOR_VERSION 4U +#define CAN_PBCFG_C_AR_RELEASE_MINOR_VERSION 5U +#define CAN_PBCFG_C_AR_RELEASE_REVISION_VERSION 0U +/* File Version Information */ +#define CAN_PBCFG_C_SW_MAJOR_VERSION 1U +#define CAN_PBCFG_C_SW_MINOR_VERSION 2U + +/******************************************************************************* +** Version Check ** +*******************************************************************************/ +#if (CAN_PBTYPES_AR_RELEASE_MAJOR_VERSION != \ + CAN_PBCFG_C_AR_RELEASE_MAJOR_VERSION) + #error "Can_PBcfg.c : Mismatch in Release Major Version" +#endif + +#if (CAN_PBTYPES_AR_RELEASE_MINOR_VERSION != \ + CAN_PBCFG_C_AR_RELEASE_MINOR_VERSION) + #error "Can_PBcfg.c : Mismatch in Release Minor Version" +#endif + +#if (CAN_PBTYPES_AR_RELEASE_REVISION_VERSION != \ + CAN_PBCFG_C_AR_RELEASE_REVISION_VERSION) + #error "Can_PBcfg.c : Mismatch in Release Revision Version" +#endif + +#if (CAN_PBTYPES_SW_MAJOR_VERSION != CAN_PBCFG_C_SW_MAJOR_VERSION) + #error "Can_PBcfg.c : Mismatch in Software Major Version" +#endif + +#if (CAN_PBTYPES_SW_MINOR_VERSION != CAN_PBCFG_C_SW_MINOR_VERSION) + #error "Can_PBcfg.c : Mismatch in Software Minor Version" +#endif + + +/******************************************************************************* +** Global Data Types ** +*******************************************************************************/ +#define CAN_RSCAN_START_SEC_DBTOC_DATA_UNSPECIFIED +#include "Can_MemMap.h" + + + +static CONST(uint32, CAN_RSCAN_CONFIG_DATA) Can_GaaGAFLCFGConfig00[] = +{ + /* Index 0 */ + 0x00020001UL, + + /* Index 1 */ + 0x00000000UL, + + /* Index 2 */ + 0x00000000UL, + + /* Index 3 */ + 0x00000000UL +}; +static CONST(uint32, CAN_RSCAN_CONFIG_DATA) Can_GaaTMIEConfig00[] = +{ + /* Index 0 */ + 0x00000000UL, + + /* Index 1 */ + 0x00000000UL, + + /* Index 2 */ + 0x00000001UL, + + /* Index 3 */ + 0x00000000UL, + + /* Index 4 */ + 0x00000000UL, + + /* Index 5 */ + 0x00000000UL, + + /* Index 6 */ + 0x00000000UL, + + /* Index 7 */ + 0x00000000UL, + + /* Index 8 */ + 0x00000000UL, + + /* Index 9 */ + 0x00000000UL, + + /* Index 10 */ + 0x00000000UL, + + /* Index 11 */ + 0x00000000UL, + + /* Index 12 */ + 0x00000000UL, + + /* Index 13 */ + 0x00000000UL, + + /* Index 14 */ + 0x00000000UL, + + /* Index 15 */ + 0x00000000UL +}; +#define CAN_RSCAN_STOP_SEC_DBTOC_DATA_UNSPECIFIED +/* MISRA Violation: START Msg(4:5087)-3 */ +#include "Can_MemMap.h" +/* END Msg(4:5087)-3 */ + + +#define CAN_RSCAN_START_SEC_DBTOC_DATA_UNSPECIFIED +/* MISRA Violation: START Msg(4:5087)-3 */ +#include "Can_MemMap.h" +/* END Msg(4:5087)-3 */ + + +/* Array for Baudrate Configuration */ +STATIC CONST(Can_BaudrateConfigType, CAN_CONFIG_DATA) Can_GaaBaudrateConfig00[] + = +{ + /* Index: 0 - CanControllerBaudrateConfig0 */ + { + /* usBaudrateConfigID */ + 0x0000U, + + /* ulCFG */ + CAN_RSCAN_NSJW(1) | CAN_RSCAN_NTSEG1(13) | CAN_RSCAN_NTSEG2(6) | + CAN_RSCAN_NBRP(7), + + /* ulDCFG */ + CAN_RSCAN_SJW(1) | CAN_RSCAN_TSEG1(13) | CAN_RSCAN_TSEG2(6) | + CAN_RSCAN_BRP(7), + + /* ulFDCFG */ + 0UL, + + /* blBRS */ + CAN_TRUE, + + /* blFdConfigured */ + CAN_TRUE + }, + /* Index: 1 - CanControllerBaudrateConfig1 */ + { + /* usBaudrateConfigID */ + 0x0001U, + + /* ulCFG */ + CAN_RSCAN_NSJW(1) | CAN_RSCAN_NTSEG1(13) | CAN_RSCAN_NTSEG2(6) | + CAN_RSCAN_NBRP(3), + + /* ulDCFG */ + CAN_RSCAN_SJW(1) | CAN_RSCAN_TSEG1(13) | CAN_RSCAN_TSEG2(6) | + CAN_RSCAN_BRP(3), + + /* ulFDCFG */ + 0UL, + + /* blBRS */ + CAN_FALSE, + + /* blFdConfigured */ + CAN_FALSE + } +}; + +STATIC CONST(Can_BaudrateConfigType, CAN_CONFIG_DATA) Can_GaaBaudrateConfig01[] + = +{ + /* Index: 0 - CanControllerBaudrateConfig0 */ + { + /* usBaudrateConfigID */ + 0x0000U, + + /* ulCFG */ + CAN_RSCAN_NSJW(1) | CAN_RSCAN_NTSEG1(13) | CAN_RSCAN_NTSEG2(6) | + CAN_RSCAN_NBRP(7), + + /* ulDCFG */ + CAN_RSCAN_SJW(1) | CAN_RSCAN_TSEG1(13) | CAN_RSCAN_TSEG2(6) | + CAN_RSCAN_BRP(7), + + /* ulFDCFG */ + 0UL, + + /* blBRS */ + CAN_FALSE, + + /* blFdConfigured */ + CAN_FALSE + }, + /* Index: 1 - CanControllerBaudrateConfig1 */ + { + /* usBaudrateConfigID */ + 0x0001U, + + /* ulCFG */ + CAN_RSCAN_NSJW(1) | CAN_RSCAN_NTSEG1(13) | CAN_RSCAN_NTSEG2(6) | + CAN_RSCAN_NBRP(3), + + /* ulDCFG */ + CAN_RSCAN_SJW(1) | CAN_RSCAN_TSEG1(13) | CAN_RSCAN_TSEG2(6) | + CAN_RSCAN_BRP(3), + + /* ulFDCFG */ + 0UL, + + /* blBRS */ + CAN_TRUE, + + /* blFdConfigured */ + CAN_TRUE + } +}; + +/* Array for Controller Configuration (Post-build time) */ +STATIC CONST(Can_ControllerPBConfigType, CAN_CONFIG_DATA) + Can_GaaControllerPBConfig0[] = +{ + /* Index: 0 - CanController0 */ + { + /* ucMainFunctionWIndex */ + 0U, + + /* usNoOfBaudrate */ + 0x0002U, + + /* pBaudrateConfig */ + &Can_GaaBaudrateConfig00[0] + }, + /* Index: 1 - CanController1 */ + { + /* ucMainFunctionWIndex */ + 0U, + + /* usNoOfBaudrate */ + 0x0002U, + + /* pBaudrateConfig */ + &Can_GaaBaudrateConfig01[0] + } +}; + +/* Array for Hardware Object Handle */ +STATIC CONST(Can_HohConfigType, CAN_CONFIG_DATA) Can_GaaHohConfig0[] = +{ + /* Index: 0 - CanHardwareObject0 -> RXBUFFER[0] */ + { + /* enHoh */ + CAN_HOH_HRH, + + /* ucMainFunctionRIndex */ + 0U, + + /* ucController */ + 0x00U, + + /* ucTMDLC */ + 0x00U, + + /* usHohId */ + 0x0000U, + + /* enBufferType */ + CAN_BUFFERTYPE_BUFFER, + + /* usBufferIndex */ + 0x0000U, + + /* ucPaddingValue */ + 0x00U, + + /* ulXXCCRegValue */ + 0UL, + + /* ulXXCCERegValue */ + 0UL, + + /* blObjectUsesPolling */ + CAN_FALSE + }, + /* Index: 1 - CanHardwareObject1 -> TXRXBUFFER(RX)[3] */ + { + /* enHoh */ + CAN_HOH_HRH, + + /* ucMainFunctionRIndex */ + 0U, + + /* ucController */ + 0x01U, + + /* ucTMDLC */ + 0x00U, + + /* usHohId */ + 0x0001U, + + /* enBufferType */ + CAN_BUFFERTYPE_TXRXFIFO, + + /* usBufferIndex */ + 0x0003U, + + /* ucPaddingValue */ + 0x00U, + + /* ulXXCCRegValue */ + CAN_RSCAN_CFM_RX | + CAN_RSCAN_CFIM | CAN_RSCAN_CFRXIE | + CAN_RSCAN_CFDC_4 | CAN_RSCAN_CFPLS_8, + + /* ulXXCCERegValue */ + 0UL, + + /* blObjectUsesPolling */ + CAN_FALSE + }, + /* Index: 2 - CanHardwareObject2 -> TXBUFFER[0] */ + { + /* enHoh */ + CAN_HOH_HTH, + + /* ucMainFunctionRIndex */ + 0U, + + /* ucController */ + 0x00U, + + /* ucTMDLC */ + 0x40U, + + /* usHohId */ + 0x0002U, + + /* enBufferType */ + CAN_BUFFERTYPE_BUFFER, + + /* usBufferIndex */ + 0x0000U, + + /* ucPaddingValue */ + 0x00U, + + /* ulXXCCRegValue */ + 0UL, + + /* ulXXCCERegValue */ + 0UL, + + /* blObjectUsesPolling */ + CAN_FALSE + }, + /* Index: 3 - CanHardwareObject3 -> TXBUFFER[64] */ + { + /* enHoh */ + CAN_HOH_HTH, + + /* ucMainFunctionRIndex */ + 0U, + + /* ucController */ + 0x01U, + + /* ucTMDLC */ + 0x40U, + + /* usHohId */ + 0x0003U, + + /* enBufferType */ + CAN_BUFFERTYPE_BUFFER, + + /* usBufferIndex */ + 0x0040U, + + /* ucPaddingValue */ + 0x00U, + + /* ulXXCCRegValue */ + 0UL, + + /* ulXXCCERegValue */ + 0UL, + + /* blObjectUsesPolling */ + CAN_FALSE + } +}; + +/* Array for Acceptance Filter Receive Rule Configuration */ +STATIC CONST(Can_FilterType, CAN_CONFIG_DATA) Can_GaaFilterConfig0[] = +{ + /* Index: 0 - CanHardwareObject0/CanHwFilter: RSCANFD00 -> RXBUFFER[0] */ + { + /* ulGAFLID */ + 0x00000100UL, + + /* ulGAFLM */ + 0xC00007FFUL, + + /* aaGAFLP */ + { + CAN_RSCAN_GAFLRMV | + CAN_RSCAN_GAFLRMDP(0) | + CAN_RSCAN_GAFLDLC_0, + 0UL + } + }, + /* Index: 1 - CanHardwareObject0/CanHwFilter_001: RSCANFD00 -> RXBUFFER[0] */ + { + /* ulGAFLID */ + 0x00000101UL, + + /* ulGAFLM */ + 0xC00007FFUL, + + /* aaGAFLP */ + { + CAN_RSCAN_GAFLRMV | + CAN_RSCAN_GAFLRMDP(0) | + CAN_RSCAN_GAFLDLC_0, + 0UL + } + }, + /* Index: 2 - CanHardwareObject1/CanHwFilter: RSCANFD01 -> TXRXFIFO[3] */ + { + /* ulGAFLID */ + 0x00000068UL, + + /* ulGAFLM */ + 0xC00007FFUL, + + /* aaGAFLP */ + { + CAN_RSCAN_GAFLDLC_0, + CAN_RSCAN_GAFLFDP_TXRXFIFO(3) + } + } +}; + +/* Array for Can Hardware Configuration Table */ +STATIC CONST(Can_HWUnitInfoType, CAN_CONFIG_DATA) Can_GaaHWUnitInfo0[] = +{ + /* Index: 0 - Registers for RSCAN unit 0 */ + { + /* ucNoOfTMIEC */ + 0x10U, + + /* ucNoOfGAFLCFG */ + 0x04U, + + /* usNoOfFilters */ + 0x0003U, + + /* ulRMNB */ + 0x00000001UL, + + /* ulGCFG */ + CAN_RSCAN_ITRCP(8) | + CAN_RSCAN_DCE, + + /* pGAFLCFG */ + &Can_GaaGAFLCFGConfig00[0], + + /* pTMIEC */ + &Can_GaaTMIEConfig00[0], + + /* pFilterConfig */ + &Can_GaaFilterConfig0[0] + } +}; + + + + +/* Global array for Icom Rx message Config Structure */ +STATIC CONST(Can_IcomRxMsgType, CAN_CONFIG_DATA) Can_GaaIcomRxMsgConfig1[] = +{ + /* Index: 0 - CanIcomRxMessage */ + { + /* pIcomRxMessageSignal */ + NULL_PTR, + + /* ulMsgIdMask */ + 0x000007FFUL, + + /* ulMsgIdCode */ + 0x00000111UL, + + /* ulCounterValue */ + 0x00000002UL, + + /* blPayloadLengthError */ + CAN_TRUE, + + /* ucPayloadLengthValue */ + CAN_RSCAN_GPFLDLC_0, + + /* ucNoOfMsgSignal */ + 0x00U + }, + /* Index: 1 - CanIcomRxMessage_001 */ + { + /* pIcomRxMessageSignal */ + NULL_PTR, + + /* ulMsgIdMask */ + 0x000007FFUL, + + /* ulMsgIdCode */ + 0x00000112UL, + + /* ulCounterValue */ + 0x00000001UL, + + /* blPayloadLengthError */ + CAN_FALSE, + + /* ucPayloadLengthValue */ + CAN_RSCAN_GPFLDLC_8, + + /* ucNoOfMsgSignal */ + 0x00U + }, + /* Index: 2 - CanIcomRxMessage_002 */ + { + /* pIcomRxMessageSignal */ + NULL_PTR, + + /* ulMsgIdMask */ + 0x1FFFFFFFUL, + + /* ulMsgIdCode */ + 0x00000000UL, + + /* ulCounterValue */ + 0x00000001UL, + + /* blPayloadLengthError */ + CAN_FALSE, + + /* ucPayloadLengthValue */ + CAN_RSCAN_GPFLDLC_0, + + /* ucNoOfMsgSignal */ + 0x00U + } +}; + +/* Global array for Icom Config Structure */ +STATIC CONST(Can_IcomConfigType, CAN_CONFIG_DATA) Can_GaaIcomConfig0[] = +{ + /* Index: 0 - CanIcomConfig */ + { + /* pIcomRxMessage */ + &Can_GaaIcomRxMsgConfig1[0], + + /* ucIcomNoOfRxMessage */ + 0x03U, + + /* blIcomWakeOnBusOff */ + CAN_TRUE + } +}; + +/* Global array for Config Structure */ +/* QAC Warning: START Msg(1:1502)-4 */ +CONST(Can_ConfigType, CAN_CONFIG_DATA) Can_GaaConfig[] = +{ + /* Index: 0 - CanConfigSet0 */ + { + /* ulStartOfDbToc */ + 0x0ED40110UL, + + /* ucNoOfUnits */ + 0x01U, + + /* ucNoOfControllers */ + 0x02U, + + /* usNoOfHohs */ + 0x0004U, + + /* pHWUnitInfo */ + /* MISRA Violation: START Msg(2:0315)-1 */ + &Can_GaaHWUnitInfo0[0], + /* END Msg(2:0315)-1 */ + + /* pControllerPCConfig */ + /* MISRA Violation: START Msg(2:0315)-1 */ + &Can_GaaControllerPCConfig0[0], + /* END Msg(2:0315)-1 */ + + /* pControllerPBConfig */ + /* MISRA Violation: START Msg(2:0315)-1 */ + &Can_GaaControllerPBConfig0[0], + /* END Msg(2:0315)-1 */ + + /* pHohConfig */ + /* MISRA Violation: START Msg(2:0315)-1 */ + &Can_GaaHohConfig0[0], + /* END Msg(2:0315)-1 */ + + /* pIcomConfig */ + /* MISRA Violation: START Msg(2:0315)-1 */ + &Can_GaaIcomConfig0[0], + /* END Msg(2:0315)-1 */ + + /* pPhysicalControllerToIndex */ + &Can_GaaPhysicalControllerToIndex0[0] + } +}; +/* END Msg(1:1502)-4 */ + +#define CAN_RSCAN_STOP_SEC_DBTOC_DATA_UNSPECIFIED +/* MISRA Violation: START Msg(4:5087)-3 */ +#include "Can_MemMap.h" +/* END Msg(4:5087)-3 */ + + + +/******************************************************************************* +** Global Data ** +*******************************************************************************/ + +/******************************************************************************* +** Function Definitions ** +*******************************************************************************/ + +/******************************************************************************* +** End of File ** +*******************************************************************************/ + diff --git a/Src/Gen4_R-Car_MCAL/2_Trunk/V4H/MCAL-v4h_19.4.0.D_release/rel/modules/cddcrc/sample_application/V4H/19_11/include/CDD_Crc_Cbk.h b/Src/Gen4_R-Car_MCAL/2_Trunk/V4H/MCAL-v4h_19.4.0.D_release/rel/modules/cddcrc/sample_application/V4H/19_11/include/CDD_Crc_Cbk.h new file mode 100644 index 00000000..35c331eb --- /dev/null +++ b/Src/Gen4_R-Car_MCAL/2_Trunk/V4H/MCAL-v4h_19.4.0.D_release/rel/modules/cddcrc/sample_application/V4H/19_11/include/CDD_Crc_Cbk.h @@ -0,0 +1,143 @@ +/*============================================================================*/ +/* Project = AUTOSAR Renesas MCAL Components */ +/* Module = CDD_Crc_Cbk.h */ +/*============================================================================*/ +/* COPYRIGHT */ +/*============================================================================*/ +/* Copyright(c) 2026 Renesas Electronics Corporation. */ +/*============================================================================*/ +/* Purpose: */ +/* This file contains callback function declaration. */ +/* AUTOMATICALLY GENERATED FILE - DO NOT EDIT */ +/* */ +/*============================================================================*/ +/* */ +/* Unless otherwise agreed upon in writing between your company and */ +/* Renesas Electronics Corporation the following shall apply! */ +/* */ +/* Warranty Disclaimer */ +/* */ +/* There is no warranty of any kind whatsoever granted by Renesas. Any */ +/* warranty is expressly disclaimed and excluded by Renesas, either expressed */ +/* or implied, including but not limited to those for non-infringement of */ +/* intellectual property, merchantability and/or fitness for the particular */ +/* purpose. */ +/* */ +/* Renesas shall not have any obligation to maintain, service or provide bug */ +/* fixes for the supplied Product(s) and/or the Application. */ +/* */ +/* Each User is solely responsible for determining the appropriateness of */ +/* using the Product(s) and assumes all risks associated with its exercise */ +/* of rights under this Agreement, including, but not limited to the risks */ +/* and costs of program errors, compliance with applicable laws, damage to */ +/* or loss of data, programs or equipment, and unavailability or */ +/* interruption of operations. */ +/* */ +/* Limitation of Liability */ +/* */ +/* In no event shall Renesas be liable to the User for any incidental, */ +/* consequential, indirect, or punitive damage (including but not limited */ +/* to lost profits) regardless of whether such liability is based on breach */ +/* of contract, tort, strict liability, breach of warranties, failure of */ +/* essential purpose or otherwise and even if advised of the possibility of */ +/* such damages. Renesas shall not be liable for any services or products */ +/* provided by third party vendors, developers or consultants identified or */ +/* referred to the User by Renesas in connection with the Product(s) and/or */ +/* the Application. */ +/* */ +/*============================================================================*/ +/* Environment: */ +/* Devices: V4H */ +/*============================================================================*/ + + +/******************************************************************************* +** Revision Control History ** +*******************************************************************************/ + + + +/******************************************************************************* +** Generation Tool Version ** +*******************************************************************************/ +/* */ +/* TOOL VERSION: CddCrcRCAR.dll version: 1.0.5, MCALConfGen.exe version: 1.2.3 */ +/* */ + + +/******************************************************************************* +** Input File ** +*******************************************************************************/ +/* + * INPUT FILE: C:\Work\Src\Gen4_R-Car_MCAL\2_Trunk\V4H\MCAL-v4h_19.4.0.D_release\rel\modules\cddcrc\sample_application\V4H\19_11\config\App_CDD_CRC_V4H_Sample.arxml + * C:\Work\Src\Gen4_R-Car_MCAL\2_Trunk\V4H\MCAL-v4h_19.4.0.D_release\rel\modules\cddcrc\generator\V4H\R1911_CDD_CRC_V4H_BSWMDT.arxml + * C:\Work\Src\Gen4_R-Car_MCAL\2_Trunk\V4H\MCAL-v4h_19.4.0.D_release\rel\common\generic\stubs\19_11\Dem\xml\Dem_CDD_Crc.arxml + * C:\Work\Src\Gen4_R-Car_MCAL\2_Trunk\V4H\MCAL-v4h_19.4.0.D_release\rel\V4H\common_family\generator\arm\Sample_Application_V4H.trxml + * GENERATED ON: 19 6 2026 - 05:12:15 + */ + + +#ifndef CDD_CRC_CBK_H +#define CDD_CRC_CBK_H + + +/******************************************************************************* +** Include Section ** +*******************************************************************************/ +#include "CDD_Crc_Cfg.h" +#include "CDD_Crc_Types.h" + + +/******************************************************************************* +** Version Information ** +*******************************************************************************/ +#define CDDCRC_CBK_AR_RELEASE_MAJOR_VERSION 4U +#define CDDCRC_CBK_AR_RELEASE_MINOR_VERSION 5U +#define CDDCRC_CBK_AR_RELEASE_REVISION_VERSION 0U +#define CDDCRC_CBK_SW_MAJOR_VERSION 1U +#define CDDCRC_CBK_SW_MINOR_VERSION 0U + +/******************************************************************************* +** Global Symbols ** +*******************************************************************************/ + + + +/******************************************************************************* +** Global Data Types ** +*******************************************************************************/ + + + +/******************************************************************************* +** Global Data ** +*******************************************************************************/ + + + +/******************************************************************************* +** Function Prototypes ** +*******************************************************************************/ +#define CDDCRC_START_SEC_APPL_CODE +#include "CddCrc_MemMap.h" + + +extern FUNC(void, CDDCRC_APPL_CODE) CompareEndNotiCh0 +( + CddCrc_CompareResultType LddResult +); + + +#define CDDCRC_STOP_SEC_APPL_CODE +#include "CddCrc_MemMap.h" + + + + +#endif /* CDD_CRC_CBK_H */ + + +/******************************************************************************* +** End of File ** +*******************************************************************************/ + diff --git a/Src/Gen4_R-Car_MCAL/2_Trunk/V4H/MCAL-v4h_19.4.0.D_release/rel/modules/cddcrc/sample_application/V4H/19_11/include/CDD_Crc_Cfg.h b/Src/Gen4_R-Car_MCAL/2_Trunk/V4H/MCAL-v4h_19.4.0.D_release/rel/modules/cddcrc/sample_application/V4H/19_11/include/CDD_Crc_Cfg.h new file mode 100644 index 00000000..dca5c6e1 --- /dev/null +++ b/Src/Gen4_R-Car_MCAL/2_Trunk/V4H/MCAL-v4h_19.4.0.D_release/rel/modules/cddcrc/sample_application/V4H/19_11/include/CDD_Crc_Cfg.h @@ -0,0 +1,595 @@ +/*============================================================================*/ +/* Project = AUTOSAR Renesas MCAL Components */ +/* Module = CDD_Crc_Cfg.h */ +/*============================================================================*/ +/* COPYRIGHT */ +/*============================================================================*/ +/* Copyright(c) 2026 Renesas Electronics Corporation. */ +/*============================================================================*/ +/* Purpose: */ +/* This file contains pre-compile time parameters */ +/* AUTOMATICALLY GENERATED FILE - DO NOT EDIT */ +/* */ +/*============================================================================*/ +/* */ +/* Unless otherwise agreed upon in writing between your company and */ +/* Renesas Electronics Corporation the following shall apply! */ +/* */ +/* Warranty Disclaimer */ +/* */ +/* There is no warranty of any kind whatsoever granted by Renesas. Any */ +/* warranty is expressly disclaimed and excluded by Renesas, either expressed */ +/* or implied, including but not limited to those for non-infringement of */ +/* intellectual property, merchantability and/or fitness for the particular */ +/* purpose. */ +/* */ +/* Renesas shall not have any obligation to maintain, service or provide bug */ +/* fixes for the supplied Product(s) and/or the Application. */ +/* */ +/* Each User is solely responsible for determining the appropriateness of */ +/* using the Product(s) and assumes all risks associated with its exercise */ +/* of rights under this Agreement, including, but not limited to the risks */ +/* and costs of program errors, compliance with applicable laws, damage to */ +/* or loss of data, programs or equipment, and unavailability or */ +/* interruption of operations. */ +/* */ +/* Limitation of Liability */ +/* */ +/* In no event shall Renesas be liable to the User for any incidental, */ +/* consequential, indirect, or punitive damage (including but not limited */ +/* to lost profits) regardless of whether such liability is based on breach */ +/* of contract, tort, strict liability, breach of warranties, failure of */ +/* essential purpose or otherwise and even if advised of the possibility of */ +/* such damages. Renesas shall not be liable for any services or products */ +/* provided by third party vendors, developers or consultants identified or */ +/* referred to the User by Renesas in connection with the Product(s) and/or */ +/* the Application. */ +/* */ +/*============================================================================*/ +/* Environment: */ +/* Devices: V4H */ +/*============================================================================*/ + + +/******************************************************************************* +** Revision Control History ** +*******************************************************************************/ + + + +/******************************************************************************* +** Generation Tool Version ** +*******************************************************************************/ +/* */ +/* TOOL VERSION: CddCrcRCAR.dll version: 1.0.5, MCALConfGen.exe version: 1.2.3 */ +/* */ + + +/******************************************************************************* +** Input File ** +*******************************************************************************/ +/* + * INPUT FILE: C:\Work\Src\Gen4_R-Car_MCAL\2_Trunk\V4H\MCAL-v4h_19.4.0.D_release\rel\modules\cddcrc\sample_application\V4H\19_11\config\App_CDD_CRC_V4H_Sample.arxml + * C:\Work\Src\Gen4_R-Car_MCAL\2_Trunk\V4H\MCAL-v4h_19.4.0.D_release\rel\modules\cddcrc\generator\V4H\R1911_CDD_CRC_V4H_BSWMDT.arxml + * C:\Work\Src\Gen4_R-Car_MCAL\2_Trunk\V4H\MCAL-v4h_19.4.0.D_release\rel\common\generic\stubs\19_11\Dem\xml\Dem_CDD_Crc.arxml + * C:\Work\Src\Gen4_R-Car_MCAL\2_Trunk\V4H\MCAL-v4h_19.4.0.D_release\rel\V4H\common_family\generator\arm\Sample_Application_V4H.trxml + * GENERATED ON: 19 6 2026 - 05:12:15 + */ + + +#ifndef CDD_CRC_CFG_H +#define CDD_CRC_CFG_H + + +/******************************************************************************* +** Include Section ** +*******************************************************************************/ + +/******************************************************************************* +** QAC Warning ** +*******************************************************************************/ + + + +/******************************************************************************* +** MISRA C Rule Violations ** +*******************************************************************************/ +/* 1. MISRA C RULE VIOLATION: */ +/* Message : (7:0791) [U] Macro identifier does not differ from other */ +/* macro identifier(s) (e.g. '%s') within the specified */ +/* number of significant characters. */ +/* Rule : MISRA C:2012 Rule-5.4 */ +/* REFERENCE - ISO:C90-6.1.2 Identifiers */ +/* Implementation Limits */ +/* CERTCCM DCL23 */ +/* Justification : This macro identifier is following AUTOSAR standard rule */ +/* (Symbolic Name or Published Macro's name), */ +/* so this is accepted. */ +/* Verification : However, part of the code is verified manually and it is */ +/* not having any impact. */ +/* Reference : Look for START Msg(7:0791)-1 and */ +/* END Msg(7:0791)-1 tags in the code. */ +/******************************************************************************/ + + +/******************************************************************************* +** Version Information ** +*******************************************************************************/ +#define CDDCRC_CFG_AR_RELEASE_MAJOR_VERSION 4U +#define CDDCRC_CFG_AR_RELEASE_MINOR_VERSION 5U +#define CDDCRC_CFG_AR_RELEASE_REVISION_VERSION 0U +#define CDDCRC_CFG_SW_MAJOR_VERSION 1U +#define CDDCRC_CFG_SW_MINOR_VERSION 0U + +/******************************************************************************* +** Common Published Information ** +*******************************************************************************/ +#define CDDCRC_AR_RELEASE_MAJOR_VERSION_VALUE 4U +#define CDDCRC_AR_RELEASE_MINOR_VERSION_VALUE 5U +#define CDDCRC_AR_RELEASE_REVISION_VERSION_VALUE 0U +#define CDDCRC_SW_MAJOR_VERSION_VALUE 1U +#define CDDCRC_SW_MINOR_VERSION_VALUE 0U +#define CDDCRC_SW_PATCH_VERSION_VALUE 8U +#define CDDCRC_VENDOR_ID_VALUE 59U +#define CDDCRC_MODULE_ID_VALUE 255U + +/******************************************************************************* +** Global Symbols ** +*******************************************************************************/ + + +/* Pre-compile option for Already Initialized check */ +#define CDDCRC_ALREADY_INIT_DET_CHECK STD_ON + +/* Pre-compile option for Critical section protection */ +#define CDDCRC_CRITICAL_SECTION_PROTECTION STD_ON + +/* Pre-compile option for Development Error Detect */ +#define CDDCRC_DEV_ERROR_DETECT STD_OFF + +/* Pre-compile option for Register Write Verify */ +#define CDDCRC_REGISTER_WRITE_VERIFY STD_ON + +/* Pre-compile option for Dependencies version check */ +#define CDDCRC_VERSION_CHECK_EXT_MODULES STD_ON + +/* Pre-compile option for common EDC function */ +#define CDDCRC_EDC_ERROR_DETECT STD_ON + +/* Pre-compile option for unintended module stop check function */ +#define CDDCRC_UNINTENDED_MODULE_STOP_CHECK STD_ON + +/* Pre-compile option for unintended interrupt check function */ +#define CDDCRC_UNINTENDED_INTERRUPT_CHECK STD_ON + +/* Pre-compile option for KCRC supporting */ +#define CDDCRC_KCRC STD_ON + +/* Pre-compile option for Version Info API */ +#define CDDCRC_VERSION_INFO_API STD_ON + +/* Pre-compile option for DEM hardware error event */ +#define CDDCRC_E_HARDWARE_ERROR \ + DemConf_DemEventParameter_CDDCRC_E_HARDWARE_ERROR + +/* Pre-compile option for DEM register write verify error event */ +#define CDDCRC_E_WRITE_VERIFY \ + DemConf_DemEventParameter_CDDCRC_E_WRITE_VERIFY + +/* Pre-compile option for DEM unintended module stop failure event */ +#define CDDCRC_E_UNINTENDED_MODULE_STOP_FAILURE \ + DemConf_DemEventParameter_CDDCRC_E_UNINTENDED_MODULE_STOP_FAILURE + +/* Pre-compile option for DEM unintended interrupt controller failure event */ +#define CDDCRC_E_INTERRUPT_CONTROLLER_FAILURE \ + DemConf_DemEventParameter_CDDCRC_E_INTERRUPT_CONTROLLER_FAILURE + +/* Pre-compile option for total CRC channel configured */ +#define CDDCRC_TOTAL_CHANNELS_CONFIG 16U + +/* Pre-compile option for total WCRC module channel configured */ +#define CDDCRC_TOTAL_WCRC_CHANNELS_CONFIG 4U + +/* Pre-compile option for total DMA unit configured */ +#define CDDCRC_TOTAL_DMA_UNITS_CONFIG 4U + + +/* Channel Handles */ +/* MISRA Violation: START Msg(7:0791)-1 */ +#define CddCrcConf_CddCrcChannelConfiguration_CddCrcChannelConfiguration \ + (CddCrc_ChannelType) 0U +/* END Msg(7:0791)-1 */ +/* MISRA Violation: START Msg(7:0791)-1 */ +#define CddCrcConf_CddCrcChannelConfiguration_CddCrcChannelConfiguration_001 \ + (CddCrc_ChannelType) 1U +/* END Msg(7:0791)-1 */ +/* MISRA Violation: START Msg(7:0791)-1 */ +#define CddCrcConf_CddCrcChannelConfiguration_CddCrcChannelConfiguration_002 \ + (CddCrc_ChannelType) 2U +/* END Msg(7:0791)-1 */ +/* MISRA Violation: START Msg(7:0791)-1 */ +#define CddCrcConf_CddCrcChannelConfiguration_CddCrcChannelConfiguration_003 \ + (CddCrc_ChannelType) 3U +/* END Msg(7:0791)-1 */ +/* MISRA Violation: START Msg(7:0791)-1 */ +#define CddCrcConf_CddCrcChannelConfiguration_CddCrcChannelConfiguration_004 \ + (CddCrc_ChannelType) 4U +/* END Msg(7:0791)-1 */ +/* MISRA Violation: START Msg(7:0791)-1 */ +#define CddCrcConf_CddCrcChannelConfiguration_CddCrcChannelConfiguration_005 \ + (CddCrc_ChannelType) 5U +/* END Msg(7:0791)-1 */ +/* MISRA Violation: START Msg(7:0791)-1 */ +#define CddCrcConf_CddCrcChannelConfiguration_CddCrcChannelConfiguration_006 \ + (CddCrc_ChannelType) 6U +/* END Msg(7:0791)-1 */ +/* MISRA Violation: START Msg(7:0791)-1 */ +#define CddCrcConf_CddCrcChannelConfiguration_CddCrcChannelConfiguration_007 \ + (CddCrc_ChannelType) 7U +/* END Msg(7:0791)-1 */ +/* MISRA Violation: START Msg(7:0791)-1 */ +#define CddCrcConf_CddCrcChannelConfiguration_CddCrcChannelConfiguration_008 \ + (CddCrc_ChannelType) 8U +/* END Msg(7:0791)-1 */ +/* MISRA Violation: START Msg(7:0791)-1 */ +#define CddCrcConf_CddCrcChannelConfiguration_CddCrcChannelConfiguration_009 \ + (CddCrc_ChannelType) 9U +/* END Msg(7:0791)-1 */ +/* MISRA Violation: START Msg(7:0791)-1 */ +#define CddCrcConf_CddCrcChannelConfiguration_CddCrcChannelConfiguration_010 \ + (CddCrc_ChannelType) 10U +/* END Msg(7:0791)-1 */ +/* MISRA Violation: START Msg(7:0791)-1 */ +#define CddCrcConf_CddCrcChannelConfiguration_CddCrcChannelConfiguration_011 \ + (CddCrc_ChannelType) 11U +/* END Msg(7:0791)-1 */ +/* MISRA Violation: START Msg(7:0791)-1 */ +#define CddCrcConf_CddCrcChannelConfiguration_CddCrcChannelConfiguration_012 \ + (CddCrc_ChannelType) 12U +/* END Msg(7:0791)-1 */ +/* MISRA Violation: START Msg(7:0791)-1 */ +#define CddCrcConf_CddCrcChannelConfiguration_CddCrcChannelConfiguration_013 \ + (CddCrc_ChannelType) 13U +/* END Msg(7:0791)-1 */ +/* MISRA Violation: START Msg(7:0791)-1 */ +#define CddCrcConf_CddCrcChannelConfiguration_CddCrcChannelConfiguration_014 \ + (CddCrc_ChannelType) 14U +/* END Msg(7:0791)-1 */ +/* MISRA Violation: START Msg(7:0791)-1 */ +#define CddCrcConf_CddCrcChannelConfiguration_CddCrcChannelConfiguration_015 \ + (CddCrc_ChannelType) 15U +/* END Msg(7:0791)-1 */ + +/* Configuration Handles */ + +#define CddCrc_Config &CddCrc_GstConfiguration + +/* Mapping to HW Channel */ + +#define CDDCRC_CRC_CH0 0U + +#define CDDCRC_CRC_CH1 4U + +#define CDDCRC_CRC_CH2 5U + +#define CDDCRC_CRC_CH3 6U + +#define CDDCRC_KCRC_CH0 1U + +#define CDDCRC_KCRC_CH1 7U + +#define CDDCRC_KCRC_CH2 8U + +#define CDDCRC_KCRC_CH3 9U + +#define CDDCRC_AES_ACC_CH0 2U + +#define CDDCRC_AES_ACC_CH1 3U + +#define CDDCRC_AES_ACC_CH2 10U + +#define CDDCRC_AES_ACC_CH3 11U + +#define CDDCRC_AES_ACC_CH4 12U + +#define CDDCRC_AES_ACC_CH5 13U + +#define CDDCRC_AES_ACC_CH6 14U + +#define CDDCRC_AES_ACC_CH7 15U + +/* Mapping to WCRC Channel */ + +#define CDDCRC_WCRC_CH0 0U + +#define CDDCRC_WCRC_CH1 1U + +#define CDDCRC_WCRC_CH2 2U + +#define CDDCRC_WCRC_CH3 3U + +/* Mapping to DMA Channel */ + +#define CDDCRC_DMA_CH01 0U + +#define CDDCRC_DMA_CH00 1U + +#define CDDCRC_DMA_CH02 2U + +#define CDDCRC_DMA_CH48 3U + +#define CDDCRC_DMA_CH05 4U + +#define CDDCRC_DMA_CH03 5U + +#define CDDCRC_DMA_CH04 6U + +#define CDDCRC_DMA_CH49 7U + +#define CDDCRC_DMA_CH08 8U + +#define CDDCRC_DMA_CH06 9U + +#define CDDCRC_DMA_CH07 10U + +#define CDDCRC_DMA_CH50 11U + +#define CDDCRC_DMA_CH11 12U + +#define CDDCRC_DMA_CH09 13U + +#define CDDCRC_DMA_CH10 14U + +#define CDDCRC_DMA_CH51 15U + +#define CDDCRC_DMA_CH14 16U + +#define CDDCRC_DMA_CH12 17U + +#define CDDCRC_DMA_CH13 18U + +#define CDDCRC_DMA_CH52 19U + +#define CDDCRC_DMA_CH17 20U + +#define CDDCRC_DMA_CH15 21U + +#define CDDCRC_DMA_CH16 22U + +#define CDDCRC_DMA_CH53 23U + +#define CDDCRC_DMA_CH20 24U + +#define CDDCRC_DMA_CH18 25U + +#define CDDCRC_DMA_CH19 26U + +#define CDDCRC_DMA_CH54 27U + +#define CDDCRC_DMA_CH23 28U + +#define CDDCRC_DMA_CH21 29U + +#define CDDCRC_DMA_CH22 30U + +#define CDDCRC_DMA_CH55 31U + +#define CDDCRC_DMA_CH26 32U + +#define CDDCRC_DMA_CH24 33U + +#define CDDCRC_DMA_CH25 34U + +#define CDDCRC_DMA_CH56 35U + +#define CDDCRC_DMA_CH29 36U + +#define CDDCRC_DMA_CH27 37U + +#define CDDCRC_DMA_CH28 38U + +#define CDDCRC_DMA_CH57 39U + +#define CDDCRC_DMA_CH32 40U + +#define CDDCRC_DMA_CH30 41U + +#define CDDCRC_DMA_CH31 42U + +#define CDDCRC_DMA_CH58 43U + +#define CDDCRC_DMA_CH35 44U + +#define CDDCRC_DMA_CH33 45U + +#define CDDCRC_DMA_CH34 46U + +#define CDDCRC_DMA_CH59 47U + +#define CDDCRC_DMA_CH38 48U + +#define CDDCRC_DMA_CH36 49U + +#define CDDCRC_DMA_CH37 50U + +#define CDDCRC_DMA_CH60 51U + +#define CDDCRC_DMA_CH41 52U + +#define CDDCRC_DMA_CH39 53U + +#define CDDCRC_DMA_CH40 54U + +#define CDDCRC_DMA_CH61 55U + +#define CDDCRC_DMA_CH44 56U + +#define CDDCRC_DMA_CH42 57U + +#define CDDCRC_DMA_CH43 58U + +#define CDDCRC_DMA_CH62 59U + +#define CDDCRC_DMA_CH45 60U + +#define CDDCRC_DMA_CH46 61U + +#define CDDCRC_DMA_CH47 62U + +#define CDDCRC_DMA_CH63 63U + +/* Hardware Dma Channel Used */ + +#define CDDCRC_DMA00_USED STD_ON + +#define CDDCRC_DMA01_USED STD_ON + +#define CDDCRC_DMA02_USED STD_ON + +#define CDDCRC_DMA03_USED STD_ON + +#define CDDCRC_DMA04_USED STD_ON + +#define CDDCRC_DMA05_USED STD_ON + +#define CDDCRC_DMA06_USED STD_ON + +#define CDDCRC_DMA07_USED STD_ON + +#define CDDCRC_DMA08_USED STD_ON + +#define CDDCRC_DMA09_USED STD_ON + +#define CDDCRC_DMA10_USED STD_ON + +#define CDDCRC_DMA11_USED STD_ON + +#define CDDCRC_DMA12_USED STD_ON + +#define CDDCRC_DMA13_USED STD_ON + +#define CDDCRC_DMA14_USED STD_ON + +#define CDDCRC_DMA15_USED STD_ON + +#define CDDCRC_DMA16_USED STD_ON + +#define CDDCRC_DMA17_USED STD_ON + +#define CDDCRC_DMA18_USED STD_ON + +#define CDDCRC_DMA19_USED STD_ON + +#define CDDCRC_DMA20_USED STD_ON + +#define CDDCRC_DMA21_USED STD_ON + +#define CDDCRC_DMA22_USED STD_ON + +#define CDDCRC_DMA23_USED STD_ON + +#define CDDCRC_DMA24_USED STD_ON + +#define CDDCRC_DMA25_USED STD_ON + +#define CDDCRC_DMA26_USED STD_ON + +#define CDDCRC_DMA27_USED STD_ON + +#define CDDCRC_DMA28_USED STD_ON + +#define CDDCRC_DMA29_USED STD_ON + +#define CDDCRC_DMA30_USED STD_ON + +#define CDDCRC_DMA31_USED STD_ON + +#define CDDCRC_DMA32_USED STD_ON + +#define CDDCRC_DMA33_USED STD_ON + +#define CDDCRC_DMA34_USED STD_ON + +#define CDDCRC_DMA35_USED STD_ON + +#define CDDCRC_DMA36_USED STD_ON + +#define CDDCRC_DMA37_USED STD_ON + +#define CDDCRC_DMA38_USED STD_ON + +#define CDDCRC_DMA39_USED STD_ON + +#define CDDCRC_DMA40_USED STD_ON + +#define CDDCRC_DMA41_USED STD_ON + +#define CDDCRC_DMA42_USED STD_ON + +#define CDDCRC_DMA43_USED STD_ON + +#define CDDCRC_DMA44_USED STD_ON + +#define CDDCRC_DMA45_USED STD_ON + +#define CDDCRC_DMA46_USED STD_ON + +#define CDDCRC_DMA47_USED STD_ON + +#define CDDCRC_DMA48_USED STD_ON + +#define CDDCRC_DMA49_USED STD_ON + +#define CDDCRC_DMA50_USED STD_ON + +#define CDDCRC_DMA51_USED STD_ON + +#define CDDCRC_DMA52_USED STD_ON + +#define CDDCRC_DMA53_USED STD_ON + +#define CDDCRC_DMA54_USED STD_ON + +#define CDDCRC_DMA55_USED STD_ON + +#define CDDCRC_DMA56_USED STD_ON + +#define CDDCRC_DMA57_USED STD_ON + +#define CDDCRC_DMA58_USED STD_ON + +#define CDDCRC_DMA59_USED STD_ON + +#define CDDCRC_DMA60_USED STD_ON + +#define CDDCRC_DMA61_USED STD_ON + +#define CDDCRC_DMA62_USED STD_ON + +#define CDDCRC_DMA63_USED STD_ON + +/******************************************************************************* +** Global Data Types ** +*******************************************************************************/ + + + +/******************************************************************************* +** Global Data ** +*******************************************************************************/ + + + +/******************************************************************************* +** Function Prototypes ** +*******************************************************************************/ + + + +#endif /* CDD_CRC_CFG_H */ + + +/******************************************************************************* +** End of File ** +*******************************************************************************/ + diff --git a/Src/Gen4_R-Car_MCAL/2_Trunk/V4H/MCAL-v4h_19.4.0.D_release/rel/modules/cddcrc/sample_application/V4H/19_11/src/CDD_Crc_PBcfg.c b/Src/Gen4_R-Car_MCAL/2_Trunk/V4H/MCAL-v4h_19.4.0.D_release/rel/modules/cddcrc/sample_application/V4H/19_11/src/CDD_Crc_PBcfg.c new file mode 100644 index 00000000..e0c4e21b --- /dev/null +++ b/Src/Gen4_R-Car_MCAL/2_Trunk/V4H/MCAL-v4h_19.4.0.D_release/rel/modules/cddcrc/sample_application/V4H/19_11/src/CDD_Crc_PBcfg.c @@ -0,0 +1,2365 @@ +/*============================================================================*/ +/* Project = AUTOSAR Renesas MCAL Components */ +/* Module = CDD_Crc_PBcfg.c */ +/*============================================================================*/ +/* COPYRIGHT */ +/*============================================================================*/ +/* Copyright(c) 2026 Renesas Electronics Corporation. */ +/*============================================================================*/ +/* Purpose: */ +/* This file contains post build parameters */ +/* AUTOMATICALLY GENERATED FILE - DO NOT EDIT */ +/* */ +/*============================================================================*/ +/* */ +/* Unless otherwise agreed upon in writing between your company and */ +/* Renesas Electronics Corporation the following shall apply! */ +/* */ +/* Warranty Disclaimer */ +/* */ +/* There is no warranty of any kind whatsoever granted by Renesas. Any */ +/* warranty is expressly disclaimed and excluded by Renesas, either expressed */ +/* or implied, including but not limited to those for non-infringement of */ +/* intellectual property, merchantability and/or fitness for the particular */ +/* purpose. */ +/* */ +/* Renesas shall not have any obligation to maintain, service or provide bug */ +/* fixes for the supplied Product(s) and/or the Application. */ +/* */ +/* Each User is solely responsible for determining the appropriateness of */ +/* using the Product(s) and assumes all risks associated with its exercise */ +/* of rights under this Agreement, including, but not limited to the risks */ +/* and costs of program errors, compliance with applicable laws, damage to */ +/* or loss of data, programs or equipment, and unavailability or */ +/* interruption of operations. */ +/* */ +/* Limitation of Liability */ +/* */ +/* In no event shall Renesas be liable to the User for any incidental, */ +/* consequential, indirect, or punitive damage (including but not limited */ +/* to lost profits) regardless of whether such liability is based on breach */ +/* of contract, tort, strict liability, breach of warranties, failure of */ +/* essential purpose or otherwise and even if advised of the possibility of */ +/* such damages. Renesas shall not be liable for any services or products */ +/* provided by third party vendors, developers or consultants identified or */ +/* referred to the User by Renesas in connection with the Product(s) and/or */ +/* the Application. */ +/* */ +/*============================================================================*/ +/* Environment: */ +/* Devices: V4H */ +/*============================================================================*/ + + +/******************************************************************************* +** Revision Control History ** +*******************************************************************************/ + + + +/******************************************************************************* +** Generation Tool Version ** +*******************************************************************************/ +/* */ +/* TOOL VERSION: CddCrcRCAR.dll version: 1.0.5, MCALConfGen.exe version: 1.2.3 */ +/* */ + + +/******************************************************************************* +** Input File ** +*******************************************************************************/ +/* + * INPUT FILE: C:\Work\Src\Gen4_R-Car_MCAL\2_Trunk\V4H\MCAL-v4h_19.4.0.D_release\rel\modules\cddcrc\sample_application\V4H\19_11\config\App_CDD_CRC_V4H_Sample.arxml + * C:\Work\Src\Gen4_R-Car_MCAL\2_Trunk\V4H\MCAL-v4h_19.4.0.D_release\rel\modules\cddcrc\generator\V4H\R1911_CDD_CRC_V4H_BSWMDT.arxml + * C:\Work\Src\Gen4_R-Car_MCAL\2_Trunk\V4H\MCAL-v4h_19.4.0.D_release\rel\common\generic\stubs\19_11\Dem\xml\Dem_CDD_Crc.arxml + * C:\Work\Src\Gen4_R-Car_MCAL\2_Trunk\V4H\MCAL-v4h_19.4.0.D_release\rel\V4H\common_family\generator\arm\Sample_Application_V4H.trxml + * GENERATED ON: 19 6 2026 - 05:12:15 + */ + + +/******************************************************************************* +** Instance Index ** +*******************************************************************************/ + +/******************************************************************************* +** Include Section ** +*******************************************************************************/ +/* QAC Warning: START Msg(2:0857)-5 */ +#include "CDD_Crc.h" +/* END Msg(2:0857)-5 */ +#include "CDD_Crc_PBTypes.h" +#include "CDD_Crc_Ram.h" +#include "CDD_Crc_Cbk.h" + + +/******************************************************************************* +** QAC Warning ** +*******************************************************************************/ +/******************************************************************************/ +/* 1. QAC Warning: */ +/* Message : (1:1504) The object '%1s' is only referenced in the */ +/* translation unit where it is defined. */ +/* Rule : MISRA-C:2012 Rule-8.7 */ +/* CERTCCM DCL15, DCL19, CWE-398, CWE-569 */ +/* Justification : This is accepted, due to following coding rule, internal */ +/* function can be defined in other C source files. */ +/* Verification : However, part of the code is verified manually and it is */ +/* not having any impact. */ +/* Reference : Look for START Msg(1:1504)-1 and */ +/* END Msg(1:1504)-1 tags in the code. */ +/******************************************************************************/ +/* 2. QAC Warning: */ +/* Message : (2:0303) [I] Cast between a pointer to volatile object */ +/* and an integral type. */ +/* Rule : MISRA C:2012 Rule-11.4 */ +/* REFERENCE - ISO:C90-6.3.4 Cast Operators - Semantics */ +/* CERTCCM INT36, CWE-398, CWE-569 */ +/* Justification : Typecasting is done as per the register size, to access */ +/* hardware registers. */ +/* Verification : However, part of the code is verified manually and it is */ +/* not having any impact. */ +/* Reference : Look for START Msg(2:0303)-2 and */ +/* END Msg(2:0303)-2 tags in the code. */ +/******************************************************************************/ +/* 3. QAC Warning: */ +/* Message : (1:1531) The object '%1s' is referenced in only one */ +/* translation unit - but not the one in which it is defined. */ +/* Rule : MISRA C:2012 Rule-8.7 */ +/* CERTCCM DCL15, DCL19, CWE-398, CWE-569 */ +/* Justification : Followed coding rules, the objects (global variable/const) */ +/* is define in separated source file, so this could be */ +/* accepted */ +/* Verification : However, part of the code is verified manually and it is */ +/* not having any impact. */ +/* Reference : Look for START Msg(1:1531)-3 and */ +/* END Msg(1:1531)-3 tags in the code. */ +/******************************************************************************/ +/* 4. QAC Warning: */ +/* Message : (2:0315) [I] Implicit conversion from a pointer to object */ +/* type to a pointer to void. */ +/* Rule : MISRA C:2012 Dir-1.1 */ +/* REFERENCE - ISO:C90-6.3.4 Cast Operators - Semantics */ +/* CWE-188, CWE-398, CWE-569 */ +/* Justification : Typecasting is done as per the register size, to access */ +/* hardware registers. */ +/* Verification : However, part of the code is verified manually and it is */ +/* not having any impact. */ +/* Reference : Look for START Msg(2:0315)-4 and */ +/* END Msg(2:0315)-4 tags in the code. */ +/******************************************************************************/ +/* 5. QAC Warning: */ +/* Message : (2:0857) [L] Number of macro definitions exceeds 1024 - */ +/* program does not conform strictly to ISO:C90. */ +/* Rule : MISRA C:2012 Dir-1.1 */ +/* REFERENCE - ISO:C90-5.2.4.1 Translation Limits */ +/* Justification : The number of macro depend on module code size. There is */ +/* no issue when number of macro is over 1024 */ +/* Verification : However, part of the code is verified manually and it is */ +/* not having any impact. */ +/* Reference : Look for START Msg(2:0857)-5 and */ +/* END Msg(2:0857)-5 tags in the code. */ +/******************************************************************************/ + + +/******************************************************************************* +** MISRA C Rule Violations ** +*******************************************************************************/ +/* 1. MISRA C RULE VIOLATION: */ +/* Message : (4:5087) Use of #include directive after code fragment. */ +/* Rule : MISRA-C:2012 Rule-20.1 */ +/* Justification : This is done as per Memory Requirement, (MEMMAP003 - */ +/* Specification of Memory Mapping). */ +/* Verification : However, part of the code is verified manually */ +/* and it is not having any impact. */ +/* Reference : Look for START Msg(4:5087)-1 and */ +/* END Msg(4:5087)-1 tags in the code. */ +/******************************************************************************/ +/* 2. MISRA C RULE VIOLATION: */ +/* Message : (2:3432) Simple macro argument expression is not */ +/* parenthesized. */ +/* Rule : MISRA-C:2012 Rule 20.7 */ +/* REFERENCE - ISO:C90-6.3.1 Primary Expressions */ +/* CWE-398, CWE-569 */ +/* Justification : Compiler keyword (macro) is defined and used followed */ +/* AUTOSAR standard rule. It is accepted. */ +/* Verification : However, part of the code is verified manually and it is */ +/* not having any impact. */ +/* Reference : Look for START Msg(2:3432)-2 and */ +/* END Msg(2:3432)-2 tags in the code. */ +/******************************************************************************/ + + +/******************************************************************************* +** Version Information ** +*******************************************************************************/ +#define CDDCRC_PBCFG_C_AR_RELEASE_MAJOR_VERSION 4U +#define CDDCRC_PBCFG_C_AR_RELEASE_MINOR_VERSION 5U +#define CDDCRC_PBCFG_C_AR_RELEASE_REVISION_VERSION 0U +#define CDDCRC_PBCFG_C_SW_MAJOR_VERSION 1U +#define CDDCRC_PBCFG_C_SW_MINOR_VERSION 0U + +/******************************************************************************* +** Version Check ** +*******************************************************************************/ +#if (CDDCRC_PBTYPES_AR_RELEASE_MAJOR_VERSION != \ + CDDCRC_PBCFG_C_AR_RELEASE_MAJOR_VERSION) + #error "CDD_Crc_PBcfg.c: Mismatch in Release Major Version" +#endif +#if (CDDCRC_PBTYPES_AR_RELEASE_MINOR_VERSION != \ + CDDCRC_PBCFG_C_AR_RELEASE_MINOR_VERSION) + #error "CDD_Crc_PBcfg.c: Mismatch in Release Minor Version" +#endif +#if (CDDCRC_PBTYPES_AR_RELEASE_REVISION_VERSION != \ + CDDCRC_PBCFG_C_AR_RELEASE_REVISION_VERSION) + #error "CDD_Crc_PBcfg.c: Mismatch in Release Revision Version" +#endif + +#if (CDDCRC_SW_MAJOR_VERSION != CDDCRC_PBCFG_C_SW_MAJOR_VERSION) + #error "CDD_Crc_PBcfg.c: Mismatch in Software Major Version" +#endif +#if (CDDCRC_SW_MINOR_VERSION != CDDCRC_PBCFG_C_SW_MINOR_VERSION) + #error "CDD_Crc_PBcfg.c: Mismatch in Software Minor Version" +#endif + + +/******************************************************************************* +** Global Data Types ** +*******************************************************************************/ + +/******************************************************************************* +** Global Data ** +*******************************************************************************/ +#define CDDCRC_START_SEC_CONFIG_DATA_UNSPECIFIED +/* MISRA Violation: START Msg(4:5087)-1 */ +#include "CddCrc_MemMap.h" +/* END Msg(4:5087)-1 */ + +/* Global array for CRC Channel Config structure */ +/* MISRA Violation: START Msg(1:1504)-1 */ +CONST(CddCrc_CrcModuleConfigType, CDDCRC_CONFIG_DATA) + CddCrc_GaaCrcChannelConfig[] = +{ + /* Index: 0 - CRC0 */ + { + /* pDCRAnCINReg */ + /* MISRA Violation: START Msg(2:0303)-2 */ + /* MISRA Violation: START Msg(2:3432)-2 */ + (P2VAR(volatile uint32, TYPEDEF, REGSPACE))0xE6F00000UL, + /* END Msg(2:3432)-2 */ + /* END Msg(2:0303)-2 */ + + /* pDCRAnCOUTReg */ + /* MISRA Violation: START Msg(2:0303)-2 */ + /* MISRA Violation: START Msg(2:3432)-2 */ + (P2VAR(volatile uint32, TYPEDEF, REGSPACE))0xE6F00004UL, + /* END Msg(2:3432)-2 */ + /* END Msg(2:0303)-2 */ + + /* pDCRAnCTLReg */ + /* MISRA Violation: START Msg(2:0303)-2 */ + /* MISRA Violation: START Msg(2:3432)-2 */ + (P2VAR(volatile uint32, TYPEDEF, REGSPACE))0xE6F00020UL, + /* END Msg(2:3432)-2 */ + /* END Msg(2:0303)-2 */ + + /* pDCRAnCTL2Reg */ + /* MISRA Violation: START Msg(2:0303)-2 */ + /* MISRA Violation: START Msg(2:3432)-2 */ + (P2VAR(volatile uint32, TYPEDEF, REGSPACE))0xE6F00040UL, + /* END Msg(2:3432)-2 */ + /* END Msg(2:0303)-2 */ + + /* enPoly */ + CDDCRC_POLY_32_ETH, + + /* ulDCRAnCTL2 */ + CDDCRC_BYTESWAPMODE(0) | + CDDCRC_BYTESWAPINMODE(0) + }, + /* Index: 1 - CRC1 */ + { + /* pDCRAnCINReg */ + /* MISRA Violation: START Msg(2:0303)-2 */ + /* MISRA Violation: START Msg(2:3432)-2 */ + (P2VAR(volatile uint32, TYPEDEF, REGSPACE))0xE6F10000UL, + /* END Msg(2:3432)-2 */ + /* END Msg(2:0303)-2 */ + + /* pDCRAnCOUTReg */ + /* MISRA Violation: START Msg(2:0303)-2 */ + /* MISRA Violation: START Msg(2:3432)-2 */ + (P2VAR(volatile uint32, TYPEDEF, REGSPACE))0xE6F10004UL, + /* END Msg(2:3432)-2 */ + /* END Msg(2:0303)-2 */ + + /* pDCRAnCTLReg */ + /* MISRA Violation: START Msg(2:0303)-2 */ + /* MISRA Violation: START Msg(2:3432)-2 */ + (P2VAR(volatile uint32, TYPEDEF, REGSPACE))0xE6F10020UL, + /* END Msg(2:3432)-2 */ + /* END Msg(2:0303)-2 */ + + /* pDCRAnCTL2Reg */ + /* MISRA Violation: START Msg(2:0303)-2 */ + /* MISRA Violation: START Msg(2:3432)-2 */ + (P2VAR(volatile uint32, TYPEDEF, REGSPACE))0xE6F10040UL, + /* END Msg(2:3432)-2 */ + /* END Msg(2:0303)-2 */ + + /* enPoly */ + CDDCRC_POLY_16_CCITT, + + /* ulDCRAnCTL2 */ + CDDCRC_BYTESWAPMODE(1) | + CDDCRC_BYTESWAPINMODE(0) + }, + /* Index: 2 - CRC2 */ + { + /* pDCRAnCINReg */ + /* MISRA Violation: START Msg(2:0303)-2 */ + /* MISRA Violation: START Msg(2:3432)-2 */ + (P2VAR(volatile uint32, TYPEDEF, REGSPACE))0xE7000000UL, + /* END Msg(2:3432)-2 */ + /* END Msg(2:0303)-2 */ + + /* pDCRAnCOUTReg */ + /* MISRA Violation: START Msg(2:0303)-2 */ + /* MISRA Violation: START Msg(2:3432)-2 */ + (P2VAR(volatile uint32, TYPEDEF, REGSPACE))0xE7000004UL, + /* END Msg(2:3432)-2 */ + /* END Msg(2:0303)-2 */ + + /* pDCRAnCTLReg */ + /* MISRA Violation: START Msg(2:0303)-2 */ + /* MISRA Violation: START Msg(2:3432)-2 */ + (P2VAR(volatile uint32, TYPEDEF, REGSPACE))0xE7000020UL, + /* END Msg(2:3432)-2 */ + /* END Msg(2:0303)-2 */ + + /* pDCRAnCTL2Reg */ + /* MISRA Violation: START Msg(2:0303)-2 */ + /* MISRA Violation: START Msg(2:3432)-2 */ + (P2VAR(volatile uint32, TYPEDEF, REGSPACE))0xE7000040UL, + /* END Msg(2:3432)-2 */ + /* END Msg(2:0303)-2 */ + + /* enPoly */ + CDDCRC_POLY_17_1685B, + + /* ulDCRAnCTL2 */ + CDDCRC_BYTESWAPMODE(0) | + CDDCRC_BYTESWAPINMODE(0) + }, + /* Index: 3 - CRC3 */ + { + /* pDCRAnCINReg */ + /* MISRA Violation: START Msg(2:0303)-2 */ + /* MISRA Violation: START Msg(2:3432)-2 */ + (P2VAR(volatile uint32, TYPEDEF, REGSPACE))0xE7010000UL, + /* END Msg(2:3432)-2 */ + /* END Msg(2:0303)-2 */ + + /* pDCRAnCOUTReg */ + /* MISRA Violation: START Msg(2:0303)-2 */ + /* MISRA Violation: START Msg(2:3432)-2 */ + (P2VAR(volatile uint32, TYPEDEF, REGSPACE))0xE7010004UL, + /* END Msg(2:3432)-2 */ + /* END Msg(2:0303)-2 */ + + /* pDCRAnCTLReg */ + /* MISRA Violation: START Msg(2:0303)-2 */ + /* MISRA Violation: START Msg(2:3432)-2 */ + (P2VAR(volatile uint32, TYPEDEF, REGSPACE))0xE7010020UL, + /* END Msg(2:3432)-2 */ + /* END Msg(2:0303)-2 */ + + /* pDCRAnCTL2Reg */ + /* MISRA Violation: START Msg(2:0303)-2 */ + /* MISRA Violation: START Msg(2:3432)-2 */ + (P2VAR(volatile uint32, TYPEDEF, REGSPACE))0xE7010040UL, + /* END Msg(2:3432)-2 */ + /* END Msg(2:0303)-2 */ + + /* enPoly */ + CDDCRC_POLY_21_102899, + + /* ulDCRAnCTL2 */ + CDDCRC_BYTESWAPMODE(0) | + CDDCRC_BYTESWAPINMODE(0) + } +}; +/* END Msg(1:1504)-1 */ + +/* Global array for KCRC Channel Config structure */ +/* MISRA Violation: START Msg(1:1504)-1 */ +CONST(CddCrc_KcrcModuleConfigType, CDDCRC_CONFIG_DATA) + CddCrc_GaaKcrcChannelConfig[] = +{ + /* Index: 0 - KCRC0 */ + { + /* pKCRCmDINReg */ + /* MISRA Violation: START Msg(2:0303)-2 */ + /* MISRA Violation: START Msg(2:3432)-2 */ + (P2VAR(volatile uint32, TYPEDEF, REGSPACE))0xE7020000UL, + /* END Msg(2:3432)-2 */ + /* END Msg(2:0303)-2 */ + + /* pKCRCmDOUTReg */ + /* MISRA Violation: START Msg(2:0303)-2 */ + /* MISRA Violation: START Msg(2:3432)-2 */ + (P2VAR(volatile uint32, TYPEDEF, REGSPACE))0xE7020080UL, + /* END Msg(2:3432)-2 */ + /* END Msg(2:0303)-2 */ + + /* pKCRCmCTLReg */ + /* MISRA Violation: START Msg(2:0303)-2 */ + /* MISRA Violation: START Msg(2:3432)-2 */ + (P2VAR(volatile uint32, TYPEDEF, REGSPACE))0xE7020090UL, + /* END Msg(2:3432)-2 */ + /* END Msg(2:0303)-2 */ + + /* pKCRCmPOLYReg */ + /* MISRA Violation: START Msg(2:0303)-2 */ + /* MISRA Violation: START Msg(2:3432)-2 */ + (P2VAR(volatile uint32, TYPEDEF, REGSPACE))0xE70200A0UL, + /* END Msg(2:3432)-2 */ + /* END Msg(2:0303)-2 */ + + /* pKCRCmXORReg */ + /* MISRA Violation: START Msg(2:0303)-2 */ + /* MISRA Violation: START Msg(2:3432)-2 */ + (P2VAR(volatile uint32, TYPEDEF, REGSPACE))0xE70200B0UL, + /* END Msg(2:3432)-2 */ + /* END Msg(2:0303)-2 */ + + /* enPoly */ + CDDCRC_POLY_16_CCITT, + + /* ulCMDValue */ + CDDCRC_KCRC_CMD0 | CDDCRC_KCRC_CMD1, + + /* ulKCRCmXOR */ + 0x0000FFFFUL + }, + /* Index: 1 - KCRC1 */ + { + /* pKCRCmDINReg */ + /* MISRA Violation: START Msg(2:0303)-2 */ + /* MISRA Violation: START Msg(2:3432)-2 */ + (P2VAR(volatile uint32, TYPEDEF, REGSPACE))0xE7030000UL, + /* END Msg(2:3432)-2 */ + /* END Msg(2:0303)-2 */ + + /* pKCRCmDOUTReg */ + /* MISRA Violation: START Msg(2:0303)-2 */ + /* MISRA Violation: START Msg(2:3432)-2 */ + (P2VAR(volatile uint32, TYPEDEF, REGSPACE))0xE7030080UL, + /* END Msg(2:3432)-2 */ + /* END Msg(2:0303)-2 */ + + /* pKCRCmCTLReg */ + /* MISRA Violation: START Msg(2:0303)-2 */ + /* MISRA Violation: START Msg(2:3432)-2 */ + (P2VAR(volatile uint32, TYPEDEF, REGSPACE))0xE7030090UL, + /* END Msg(2:3432)-2 */ + /* END Msg(2:0303)-2 */ + + /* pKCRCmPOLYReg */ + /* MISRA Violation: START Msg(2:0303)-2 */ + /* MISRA Violation: START Msg(2:3432)-2 */ + (P2VAR(volatile uint32, TYPEDEF, REGSPACE))0xE70300A0UL, + /* END Msg(2:3432)-2 */ + /* END Msg(2:0303)-2 */ + + /* pKCRCmXORReg */ + /* MISRA Violation: START Msg(2:0303)-2 */ + /* MISRA Violation: START Msg(2:3432)-2 */ + (P2VAR(volatile uint32, TYPEDEF, REGSPACE))0xE70300B0UL, + /* END Msg(2:3432)-2 */ + /* END Msg(2:0303)-2 */ + + /* enPoly */ + CDDCRC_POLY_32_1EDC6F41, + + /* ulCMDValue */ + CDDCRC_KCRC_CMD0 | CDDCRC_KCRC_CMD1 | CDDCRC_KCRC_CMD2, + + /* ulKCRCmXOR */ + 0xFFFFFFFFUL + }, + /* Index: 2 - KCRC2 */ + { + /* pKCRCmDINReg */ + /* MISRA Violation: START Msg(2:0303)-2 */ + /* MISRA Violation: START Msg(2:3432)-2 */ + (P2VAR(volatile uint32, TYPEDEF, REGSPACE))0xE7040000UL, + /* END Msg(2:3432)-2 */ + /* END Msg(2:0303)-2 */ + + /* pKCRCmDOUTReg */ + /* MISRA Violation: START Msg(2:0303)-2 */ + /* MISRA Violation: START Msg(2:3432)-2 */ + (P2VAR(volatile uint32, TYPEDEF, REGSPACE))0xE7040080UL, + /* END Msg(2:3432)-2 */ + /* END Msg(2:0303)-2 */ + + /* pKCRCmCTLReg */ + /* MISRA Violation: START Msg(2:0303)-2 */ + /* MISRA Violation: START Msg(2:3432)-2 */ + (P2VAR(volatile uint32, TYPEDEF, REGSPACE))0xE7040090UL, + /* END Msg(2:3432)-2 */ + /* END Msg(2:0303)-2 */ + + /* pKCRCmPOLYReg */ + /* MISRA Violation: START Msg(2:0303)-2 */ + /* MISRA Violation: START Msg(2:3432)-2 */ + (P2VAR(volatile uint32, TYPEDEF, REGSPACE))0xE70400A0UL, + /* END Msg(2:3432)-2 */ + /* END Msg(2:0303)-2 */ + + /* pKCRCmXORReg */ + /* MISRA Violation: START Msg(2:0303)-2 */ + /* MISRA Violation: START Msg(2:3432)-2 */ + (P2VAR(volatile uint32, TYPEDEF, REGSPACE))0xE70400B0UL, + /* END Msg(2:3432)-2 */ + /* END Msg(2:0303)-2 */ + + /* enPoly */ + CDDCRC_POLY_32_ETH, + + /* ulCMDValue */ + CDDCRC_KCRC_CMD0 | CDDCRC_KCRC_CMD1 | CDDCRC_KCRC_CMD2, + + /* ulKCRCmXOR */ + 0xFFFFFFFFUL + }, + /* Index: 3 - KCRC3 */ + { + /* pKCRCmDINReg */ + /* MISRA Violation: START Msg(2:0303)-2 */ + /* MISRA Violation: START Msg(2:3432)-2 */ + (P2VAR(volatile uint32, TYPEDEF, REGSPACE))0xE7050000UL, + /* END Msg(2:3432)-2 */ + /* END Msg(2:0303)-2 */ + + /* pKCRCmDOUTReg */ + /* MISRA Violation: START Msg(2:0303)-2 */ + /* MISRA Violation: START Msg(2:3432)-2 */ + (P2VAR(volatile uint32, TYPEDEF, REGSPACE))0xE7050080UL, + /* END Msg(2:3432)-2 */ + /* END Msg(2:0303)-2 */ + + /* pKCRCmCTLReg */ + /* MISRA Violation: START Msg(2:0303)-2 */ + /* MISRA Violation: START Msg(2:3432)-2 */ + (P2VAR(volatile uint32, TYPEDEF, REGSPACE))0xE7050090UL, + /* END Msg(2:3432)-2 */ + /* END Msg(2:0303)-2 */ + + /* pKCRCmPOLYReg */ + /* MISRA Violation: START Msg(2:0303)-2 */ + /* MISRA Violation: START Msg(2:3432)-2 */ + (P2VAR(volatile uint32, TYPEDEF, REGSPACE))0xE70500A0UL, + /* END Msg(2:3432)-2 */ + /* END Msg(2:0303)-2 */ + + /* pKCRCmXORReg */ + /* MISRA Violation: START Msg(2:0303)-2 */ + /* MISRA Violation: START Msg(2:3432)-2 */ + (P2VAR(volatile uint32, TYPEDEF, REGSPACE))0xE70500B0UL, + /* END Msg(2:3432)-2 */ + /* END Msg(2:0303)-2 */ + + /* enPoly */ + CDDCRC_POLY_8_0x2F, + + /* ulCMDValue */ + 0x00000000UL, + + /* ulKCRCmXOR */ + 0xAABBCCDDUL + } +}; +/* END Msg(1:1504)-1 */ + +/* Global array for WCRC Channel Config structure */ +/* MISRA Violation: START Msg(1:1504)-1 */ +CONST(CddCrc_WcrcChannelConfigType, CDDCRC_CONFIG_DATA) + CddCrc_GaaWcrcChannelConfig[] = +{ + /* Index: 0 - WCRC0 */ + { + /* pECMEN */ + /* MISRA Violation: START Msg(2:0303)-2 */ + /* MISRA Violation: START Msg(2:3432)-2 */ + (P2VAR(volatile uint32, TYPEDEF, REGSPACE))0xE7080F80UL + /* END Msg(2:3432)-2 */ + /* END Msg(2:0303)-2 */ + }, + /* Index: 1 - WCRC1 */ + { + /* pECMEN */ + /* MISRA Violation: START Msg(2:0303)-2 */ + /* MISRA Violation: START Msg(2:3432)-2 */ + (P2VAR(volatile uint32, TYPEDEF, REGSPACE))0xE7090F80UL + /* END Msg(2:3432)-2 */ + /* END Msg(2:0303)-2 */ + }, + /* Index: 2 - WCRC2 */ + { + /* pECMEN */ + /* MISRA Violation: START Msg(2:0303)-2 */ + /* MISRA Violation: START Msg(2:3432)-2 */ + (P2VAR(volatile uint32, TYPEDEF, REGSPACE))0xE70A0F80UL + /* END Msg(2:3432)-2 */ + /* END Msg(2:0303)-2 */ + }, + /* Index: 3 - WCRC3 */ + { + /* pECMEN */ + /* MISRA Violation: START Msg(2:0303)-2 */ + /* MISRA Violation: START Msg(2:3432)-2 */ + (P2VAR(volatile uint32, TYPEDEF, REGSPACE))0xE70B0F80UL + /* END Msg(2:3432)-2 */ + /* END Msg(2:0303)-2 */ + } +}; +/* END Msg(1:1504)-1 */ + +/* Global array for DMA Channel Config structure */ +/* MISRA Violation: START Msg(1:1504)-1 */ +CONST(CddCrc_DmaConfigType, CDDCRC_CONFIG_DATA) CddCrc_GaaDmaChannelConfig[] = +{ + /* Index: 0 - CddCrcDmaResultChannel */ + { + /* ucChannelIdx */ + 0U, + + /* pDmaRegs */ + /* MISRA Violation: START Msg(2:0303)-2 */ + /* MISRA Violation: START Msg(2:3432)-2 */ + (P2VAR(volatile CddCrc_DmaRegType, TYPEDEF, REGSPACE))0xFFC11000UL, + /* END Msg(2:3432)-2 */ + /* END Msg(2:0303)-2 */ + + /* usDMRS */ + 0x18U + }, + /* Index: 1 - CddCrcDmaDataInChannel */ + { + /* ucChannelIdx */ + 0U, + + /* pDmaRegs */ + /* MISRA Violation: START Msg(2:0303)-2 */ + /* MISRA Violation: START Msg(2:3432)-2 */ + (P2VAR(volatile CddCrc_DmaRegType, TYPEDEF, REGSPACE))0xFFC10000UL, + /* END Msg(2:3432)-2 */ + /* END Msg(2:0303)-2 */ + + /* usDMRS */ + 0x19U + }, + /* Index: 2 - CddCrcDmaDataOutChannel */ + { + /* ucChannelIdx */ + 0U, + + /* pDmaRegs */ + /* MISRA Violation: START Msg(2:0303)-2 */ + /* MISRA Violation: START Msg(2:3432)-2 */ + (P2VAR(volatile CddCrc_DmaRegType, TYPEDEF, REGSPACE))0xFFC12000UL, + /* END Msg(2:3432)-2 */ + /* END Msg(2:0303)-2 */ + + /* usDMRS */ + 0x1AU + }, + /* Index: 3 - CddCrcDmaCommandChannel */ + { + /* ucChannelIdx */ + 0U, + + /* pDmaRegs */ + /* MISRA Violation: START Msg(2:0303)-2 */ + /* MISRA Violation: START Msg(2:3432)-2 */ + (P2VAR(volatile CddCrc_DmaRegType, TYPEDEF, REGSPACE))0xFFD80000UL, + /* END Msg(2:3432)-2 */ + /* END Msg(2:0303)-2 */ + + /* usDMRS */ + 0x19U + }, + /* Index: 4 - CddCrcDmaResultChannel */ + { + /* ucChannelIdx */ + 1U, + + /* pDmaRegs */ + /* MISRA Violation: START Msg(2:0303)-2 */ + /* MISRA Violation: START Msg(2:3432)-2 */ + (P2VAR(volatile CddCrc_DmaRegType, TYPEDEF, REGSPACE))0xFFC15000UL, + /* END Msg(2:3432)-2 */ + /* END Msg(2:0303)-2 */ + + /* usDMRS */ + 0x1CU + }, + /* Index: 5 - CddCrcDmaDataInChannel */ + { + /* ucChannelIdx */ + 1U, + + /* pDmaRegs */ + /* MISRA Violation: START Msg(2:0303)-2 */ + /* MISRA Violation: START Msg(2:3432)-2 */ + (P2VAR(volatile CddCrc_DmaRegType, TYPEDEF, REGSPACE))0xFFC13000UL, + /* END Msg(2:3432)-2 */ + /* END Msg(2:0303)-2 */ + + /* usDMRS */ + 0x1DU + }, + /* Index: 6 - CddCrcDmaDataOutChannel */ + { + /* ucChannelIdx */ + 1U, + + /* pDmaRegs */ + /* MISRA Violation: START Msg(2:0303)-2 */ + /* MISRA Violation: START Msg(2:3432)-2 */ + (P2VAR(volatile CddCrc_DmaRegType, TYPEDEF, REGSPACE))0xFFC14000UL, + /* END Msg(2:3432)-2 */ + /* END Msg(2:0303)-2 */ + + /* usDMRS */ + 0x1EU + }, + /* Index: 7 - CddCrcDmaCommandChannel */ + { + /* ucChannelIdx */ + 1U, + + /* pDmaRegs */ + /* MISRA Violation: START Msg(2:0303)-2 */ + /* MISRA Violation: START Msg(2:3432)-2 */ + (P2VAR(volatile CddCrc_DmaRegType, TYPEDEF, REGSPACE))0xFFD81000UL, + /* END Msg(2:3432)-2 */ + /* END Msg(2:0303)-2 */ + + /* usDMRS */ + 0x1DU + }, + /* Index: 8 - CddCrcDmaResultChannel */ + { + /* ucChannelIdx */ + 2U, + + /* pDmaRegs */ + /* MISRA Violation: START Msg(2:0303)-2 */ + /* MISRA Violation: START Msg(2:3432)-2 */ + (P2VAR(volatile CddCrc_DmaRegType, TYPEDEF, REGSPACE))0xFFC18000UL, + /* END Msg(2:3432)-2 */ + /* END Msg(2:0303)-2 */ + + /* usDMRS */ + 0x10U + }, + /* Index: 9 - CddCrcDmaDataInChannel */ + { + /* ucChannelIdx */ + 2U, + + /* pDmaRegs */ + /* MISRA Violation: START Msg(2:0303)-2 */ + /* MISRA Violation: START Msg(2:3432)-2 */ + (P2VAR(volatile CddCrc_DmaRegType, TYPEDEF, REGSPACE))0xFFC16000UL, + /* END Msg(2:3432)-2 */ + /* END Msg(2:0303)-2 */ + + /* usDMRS */ + 0x11U + }, + /* Index: 10 - CddCrcDmaDataOutChannel */ + { + /* ucChannelIdx */ + 2U, + + /* pDmaRegs */ + /* MISRA Violation: START Msg(2:0303)-2 */ + /* MISRA Violation: START Msg(2:3432)-2 */ + (P2VAR(volatile CddCrc_DmaRegType, TYPEDEF, REGSPACE))0xFFC17000UL, + /* END Msg(2:3432)-2 */ + /* END Msg(2:0303)-2 */ + + /* usDMRS */ + 0x12U + }, + /* Index: 11 - CddCrcDmaCommandChannel */ + { + /* ucChannelIdx */ + 2U, + + /* pDmaRegs */ + /* MISRA Violation: START Msg(2:0303)-2 */ + /* MISRA Violation: START Msg(2:3432)-2 */ + (P2VAR(volatile CddCrc_DmaRegType, TYPEDEF, REGSPACE))0xFFD82000UL, + /* END Msg(2:3432)-2 */ + /* END Msg(2:0303)-2 */ + + /* usDMRS */ + 0x11U + }, + /* Index: 12 - CddCrcDmaResultChannel */ + { + /* ucChannelIdx */ + 3U, + + /* pDmaRegs */ + /* MISRA Violation: START Msg(2:0303)-2 */ + /* MISRA Violation: START Msg(2:3432)-2 */ + (P2VAR(volatile CddCrc_DmaRegType, TYPEDEF, REGSPACE))0xFFC1B000UL, + /* END Msg(2:3432)-2 */ + /* END Msg(2:0303)-2 */ + + /* usDMRS */ + 0x14U + }, + /* Index: 13 - CddCrcDmaDataInChannel */ + { + /* ucChannelIdx */ + 3U, + + /* pDmaRegs */ + /* MISRA Violation: START Msg(2:0303)-2 */ + /* MISRA Violation: START Msg(2:3432)-2 */ + (P2VAR(volatile CddCrc_DmaRegType, TYPEDEF, REGSPACE))0xFFC19000UL, + /* END Msg(2:3432)-2 */ + /* END Msg(2:0303)-2 */ + + /* usDMRS */ + 0x15U + }, + /* Index: 14 - CddCrcDmaDataOutChannel */ + { + /* ucChannelIdx */ + 3U, + + /* pDmaRegs */ + /* MISRA Violation: START Msg(2:0303)-2 */ + /* MISRA Violation: START Msg(2:3432)-2 */ + (P2VAR(volatile CddCrc_DmaRegType, TYPEDEF, REGSPACE))0xFFC1A000UL, + /* END Msg(2:3432)-2 */ + /* END Msg(2:0303)-2 */ + + /* usDMRS */ + 0x16U + }, + /* Index: 15 - CddCrcDmaCommandChannel */ + { + /* ucChannelIdx */ + 3U, + + /* pDmaRegs */ + /* MISRA Violation: START Msg(2:0303)-2 */ + /* MISRA Violation: START Msg(2:3432)-2 */ + (P2VAR(volatile CddCrc_DmaRegType, TYPEDEF, REGSPACE))0xFFD83000UL, + /* END Msg(2:3432)-2 */ + /* END Msg(2:0303)-2 */ + + /* usDMRS */ + 0x15U + }, + /* Index: 16 - CddCrcDmaResultChannel */ + { + /* ucChannelIdx */ + 4U, + + /* pDmaRegs */ + /* MISRA Violation: START Msg(2:0303)-2 */ + /* MISRA Violation: START Msg(2:3432)-2 */ + (P2VAR(volatile CddCrc_DmaRegType, TYPEDEF, REGSPACE))0xFFC1E000UL, + /* END Msg(2:3432)-2 */ + /* END Msg(2:0303)-2 */ + + /* usDMRS */ + 0x48U + }, + /* Index: 17 - CddCrcDmaDataInChannel */ + { + /* ucChannelIdx */ + 4U, + + /* pDmaRegs */ + /* MISRA Violation: START Msg(2:0303)-2 */ + /* MISRA Violation: START Msg(2:3432)-2 */ + (P2VAR(volatile CddCrc_DmaRegType, TYPEDEF, REGSPACE))0xFFC1C000UL, + /* END Msg(2:3432)-2 */ + /* END Msg(2:0303)-2 */ + + /* usDMRS */ + 0x49U + }, + /* Index: 18 - CddCrcDmaDataOutChannel */ + { + /* ucChannelIdx */ + 4U, + + /* pDmaRegs */ + /* MISRA Violation: START Msg(2:0303)-2 */ + /* MISRA Violation: START Msg(2:3432)-2 */ + (P2VAR(volatile CddCrc_DmaRegType, TYPEDEF, REGSPACE))0xFFC1D000UL, + /* END Msg(2:3432)-2 */ + /* END Msg(2:0303)-2 */ + + /* usDMRS */ + 0x4AU + }, + /* Index: 19 - CddCrcDmaCommandChannel */ + { + /* ucChannelIdx */ + 4U, + + /* pDmaRegs */ + /* MISRA Violation: START Msg(2:0303)-2 */ + /* MISRA Violation: START Msg(2:3432)-2 */ + (P2VAR(volatile CddCrc_DmaRegType, TYPEDEF, REGSPACE))0xFFD84000UL, + /* END Msg(2:3432)-2 */ + /* END Msg(2:0303)-2 */ + + /* usDMRS */ + 0x49U + }, + /* Index: 20 - CddCrcDmaResultChannel */ + { + /* ucChannelIdx */ + 5U, + + /* pDmaRegs */ + /* MISRA Violation: START Msg(2:0303)-2 */ + /* MISRA Violation: START Msg(2:3432)-2 */ + (P2VAR(volatile CddCrc_DmaRegType, TYPEDEF, REGSPACE))0xFFC21000UL, + /* END Msg(2:3432)-2 */ + /* END Msg(2:0303)-2 */ + + /* usDMRS */ + 0x88U + }, + /* Index: 21 - CddCrcDmaDataInChannel */ + { + /* ucChannelIdx */ + 5U, + + /* pDmaRegs */ + /* MISRA Violation: START Msg(2:0303)-2 */ + /* MISRA Violation: START Msg(2:3432)-2 */ + (P2VAR(volatile CddCrc_DmaRegType, TYPEDEF, REGSPACE))0xFFC1F000UL, + /* END Msg(2:3432)-2 */ + /* END Msg(2:0303)-2 */ + + /* usDMRS */ + 0x89U + }, + /* Index: 22 - CddCrcDmaDataOutChannel */ + { + /* ucChannelIdx */ + 5U, + + /* pDmaRegs */ + /* MISRA Violation: START Msg(2:0303)-2 */ + /* MISRA Violation: START Msg(2:3432)-2 */ + (P2VAR(volatile CddCrc_DmaRegType, TYPEDEF, REGSPACE))0xFFC20000UL, + /* END Msg(2:3432)-2 */ + /* END Msg(2:0303)-2 */ + + /* usDMRS */ + 0x8AU + }, + /* Index: 23 - CddCrcDmaCommandChannel */ + { + /* ucChannelIdx */ + 5U, + + /* pDmaRegs */ + /* MISRA Violation: START Msg(2:0303)-2 */ + /* MISRA Violation: START Msg(2:3432)-2 */ + (P2VAR(volatile CddCrc_DmaRegType, TYPEDEF, REGSPACE))0xFFD85000UL, + /* END Msg(2:3432)-2 */ + /* END Msg(2:0303)-2 */ + + /* usDMRS */ + 0x89U + }, + /* Index: 24 - CddCrcDmaResultChannel */ + { + /* ucChannelIdx */ + 6U, + + /* pDmaRegs */ + /* MISRA Violation: START Msg(2:0303)-2 */ + /* MISRA Violation: START Msg(2:3432)-2 */ + (P2VAR(volatile CddCrc_DmaRegType, TYPEDEF, REGSPACE))0xFFC24000UL, + /* END Msg(2:3432)-2 */ + /* END Msg(2:0303)-2 */ + + /* usDMRS */ + 0xC8U + }, + /* Index: 25 - CddCrcDmaDataInChannel */ + { + /* ucChannelIdx */ + 6U, + + /* pDmaRegs */ + /* MISRA Violation: START Msg(2:0303)-2 */ + /* MISRA Violation: START Msg(2:3432)-2 */ + (P2VAR(volatile CddCrc_DmaRegType, TYPEDEF, REGSPACE))0xFFC22000UL, + /* END Msg(2:3432)-2 */ + /* END Msg(2:0303)-2 */ + + /* usDMRS */ + 0xC9U + }, + /* Index: 26 - CddCrcDmaDataOutChannel */ + { + /* ucChannelIdx */ + 6U, + + /* pDmaRegs */ + /* MISRA Violation: START Msg(2:0303)-2 */ + /* MISRA Violation: START Msg(2:3432)-2 */ + (P2VAR(volatile CddCrc_DmaRegType, TYPEDEF, REGSPACE))0xFFC23000UL, + /* END Msg(2:3432)-2 */ + /* END Msg(2:0303)-2 */ + + /* usDMRS */ + 0xCAU + }, + /* Index: 27 - CddCrcDmaCommandChannel */ + { + /* ucChannelIdx */ + 6U, + + /* pDmaRegs */ + /* MISRA Violation: START Msg(2:0303)-2 */ + /* MISRA Violation: START Msg(2:3432)-2 */ + (P2VAR(volatile CddCrc_DmaRegType, TYPEDEF, REGSPACE))0xFFD86000UL, + /* END Msg(2:3432)-2 */ + /* END Msg(2:0303)-2 */ + + /* usDMRS */ + 0xC9U + }, + /* Index: 28 - CddCrcDmaResultChannel */ + { + /* ucChannelIdx */ + 7U, + + /* pDmaRegs */ + /* MISRA Violation: START Msg(2:0303)-2 */ + /* MISRA Violation: START Msg(2:3432)-2 */ + (P2VAR(volatile CddCrc_DmaRegType, TYPEDEF, REGSPACE))0xFFC27000UL, + /* END Msg(2:3432)-2 */ + /* END Msg(2:0303)-2 */ + + /* usDMRS */ + 0x4CU + }, + /* Index: 29 - CddCrcDmaDataInChannel */ + { + /* ucChannelIdx */ + 7U, + + /* pDmaRegs */ + /* MISRA Violation: START Msg(2:0303)-2 */ + /* MISRA Violation: START Msg(2:3432)-2 */ + (P2VAR(volatile CddCrc_DmaRegType, TYPEDEF, REGSPACE))0xFFC25000UL, + /* END Msg(2:3432)-2 */ + /* END Msg(2:0303)-2 */ + + /* usDMRS */ + 0x4DU + }, + /* Index: 30 - CddCrcDmaDataOutChannel */ + { + /* ucChannelIdx */ + 7U, + + /* pDmaRegs */ + /* MISRA Violation: START Msg(2:0303)-2 */ + /* MISRA Violation: START Msg(2:3432)-2 */ + (P2VAR(volatile CddCrc_DmaRegType, TYPEDEF, REGSPACE))0xFFC26000UL, + /* END Msg(2:3432)-2 */ + /* END Msg(2:0303)-2 */ + + /* usDMRS */ + 0x4EU + }, + /* Index: 31 - CddCrcDmaCommandChannel */ + { + /* ucChannelIdx */ + 7U, + + /* pDmaRegs */ + /* MISRA Violation: START Msg(2:0303)-2 */ + /* MISRA Violation: START Msg(2:3432)-2 */ + (P2VAR(volatile CddCrc_DmaRegType, TYPEDEF, REGSPACE))0xFFD87000UL, + /* END Msg(2:3432)-2 */ + /* END Msg(2:0303)-2 */ + + /* usDMRS */ + 0x4DU + }, + /* Index: 32 - CddCrcDmaResultChannel */ + { + /* ucChannelIdx */ + 8U, + + /* pDmaRegs */ + /* MISRA Violation: START Msg(2:0303)-2 */ + /* MISRA Violation: START Msg(2:3432)-2 */ + (P2VAR(volatile CddCrc_DmaRegType, TYPEDEF, REGSPACE))0xFFC2A000UL, + /* END Msg(2:3432)-2 */ + /* END Msg(2:0303)-2 */ + + /* usDMRS */ + 0x8CU + }, + /* Index: 33 - CddCrcDmaDataInChannel */ + { + /* ucChannelIdx */ + 8U, + + /* pDmaRegs */ + /* MISRA Violation: START Msg(2:0303)-2 */ + /* MISRA Violation: START Msg(2:3432)-2 */ + (P2VAR(volatile CddCrc_DmaRegType, TYPEDEF, REGSPACE))0xFFC28000UL, + /* END Msg(2:3432)-2 */ + /* END Msg(2:0303)-2 */ + + /* usDMRS */ + 0x8DU + }, + /* Index: 34 - CddCrcDmaDataOutChannel */ + { + /* ucChannelIdx */ + 8U, + + /* pDmaRegs */ + /* MISRA Violation: START Msg(2:0303)-2 */ + /* MISRA Violation: START Msg(2:3432)-2 */ + (P2VAR(volatile CddCrc_DmaRegType, TYPEDEF, REGSPACE))0xFFC29000UL, + /* END Msg(2:3432)-2 */ + /* END Msg(2:0303)-2 */ + + /* usDMRS */ + 0x8EU + }, + /* Index: 35 - CddCrcDmaCommandChannel */ + { + /* ucChannelIdx */ + 8U, + + /* pDmaRegs */ + /* MISRA Violation: START Msg(2:0303)-2 */ + /* MISRA Violation: START Msg(2:3432)-2 */ + (P2VAR(volatile CddCrc_DmaRegType, TYPEDEF, REGSPACE))0xFFD88000UL, + /* END Msg(2:3432)-2 */ + /* END Msg(2:0303)-2 */ + + /* usDMRS */ + 0x8DU + }, + /* Index: 36 - CddCrcDmaResultChannel */ + { + /* ucChannelIdx */ + 9U, + + /* pDmaRegs */ + /* MISRA Violation: START Msg(2:0303)-2 */ + /* MISRA Violation: START Msg(2:3432)-2 */ + (P2VAR(volatile CddCrc_DmaRegType, TYPEDEF, REGSPACE))0xFFC2D000UL, + /* END Msg(2:3432)-2 */ + /* END Msg(2:0303)-2 */ + + /* usDMRS */ + 0xCCU + }, + /* Index: 37 - CddCrcDmaDataInChannel */ + { + /* ucChannelIdx */ + 9U, + + /* pDmaRegs */ + /* MISRA Violation: START Msg(2:0303)-2 */ + /* MISRA Violation: START Msg(2:3432)-2 */ + (P2VAR(volatile CddCrc_DmaRegType, TYPEDEF, REGSPACE))0xFFC2B000UL, + /* END Msg(2:3432)-2 */ + /* END Msg(2:0303)-2 */ + + /* usDMRS */ + 0xCDU + }, + /* Index: 38 - CddCrcDmaDataOutChannel */ + { + /* ucChannelIdx */ + 9U, + + /* pDmaRegs */ + /* MISRA Violation: START Msg(2:0303)-2 */ + /* MISRA Violation: START Msg(2:3432)-2 */ + (P2VAR(volatile CddCrc_DmaRegType, TYPEDEF, REGSPACE))0xFFC2C000UL, + /* END Msg(2:3432)-2 */ + /* END Msg(2:0303)-2 */ + + /* usDMRS */ + 0xCEU + }, + /* Index: 39 - CddCrcDmaCommandChannel */ + { + /* ucChannelIdx */ + 9U, + + /* pDmaRegs */ + /* MISRA Violation: START Msg(2:0303)-2 */ + /* MISRA Violation: START Msg(2:3432)-2 */ + (P2VAR(volatile CddCrc_DmaRegType, TYPEDEF, REGSPACE))0xFFD89000UL, + /* END Msg(2:3432)-2 */ + /* END Msg(2:0303)-2 */ + + /* usDMRS */ + 0xCDU + }, + /* Index: 40 - CddCrcDmaResultChannel */ + { + /* ucChannelIdx */ + 10U, + + /* pDmaRegs */ + /* MISRA Violation: START Msg(2:0303)-2 */ + /* MISRA Violation: START Msg(2:3432)-2 */ + (P2VAR(volatile CddCrc_DmaRegType, TYPEDEF, REGSPACE))0xFFD70000UL, + /* END Msg(2:3432)-2 */ + /* END Msg(2:0303)-2 */ + + /* usDMRS */ + 0x40U + }, + /* Index: 41 - CddCrcDmaDataInChannel */ + { + /* ucChannelIdx */ + 10U, + + /* pDmaRegs */ + /* MISRA Violation: START Msg(2:0303)-2 */ + /* MISRA Violation: START Msg(2:3432)-2 */ + (P2VAR(volatile CddCrc_DmaRegType, TYPEDEF, REGSPACE))0xFFC2E000UL, + /* END Msg(2:3432)-2 */ + /* END Msg(2:0303)-2 */ + + /* usDMRS */ + 0x41U + }, + /* Index: 42 - CddCrcDmaDataOutChannel */ + { + /* ucChannelIdx */ + 10U, + + /* pDmaRegs */ + /* MISRA Violation: START Msg(2:0303)-2 */ + /* MISRA Violation: START Msg(2:3432)-2 */ + (P2VAR(volatile CddCrc_DmaRegType, TYPEDEF, REGSPACE))0xFFC2F000UL, + /* END Msg(2:3432)-2 */ + /* END Msg(2:0303)-2 */ + + /* usDMRS */ + 0x42U + }, + /* Index: 43 - CddCrcDmaCommandChannel */ + { + /* ucChannelIdx */ + 10U, + + /* pDmaRegs */ + /* MISRA Violation: START Msg(2:0303)-2 */ + /* MISRA Violation: START Msg(2:3432)-2 */ + (P2VAR(volatile CddCrc_DmaRegType, TYPEDEF, REGSPACE))0xFFD8A000UL, + /* END Msg(2:3432)-2 */ + /* END Msg(2:0303)-2 */ + + /* usDMRS */ + 0x41U + }, + /* Index: 44 - CddCrcDmaResultChannel */ + { + /* ucChannelIdx */ + 11U, + + /* pDmaRegs */ + /* MISRA Violation: START Msg(2:0303)-2 */ + /* MISRA Violation: START Msg(2:3432)-2 */ + (P2VAR(volatile CddCrc_DmaRegType, TYPEDEF, REGSPACE))0xFFD73000UL, + /* END Msg(2:3432)-2 */ + /* END Msg(2:0303)-2 */ + + /* usDMRS */ + 0x44U + }, + /* Index: 45 - CddCrcDmaDataInChannel */ + { + /* ucChannelIdx */ + 11U, + + /* pDmaRegs */ + /* MISRA Violation: START Msg(2:0303)-2 */ + /* MISRA Violation: START Msg(2:3432)-2 */ + (P2VAR(volatile CddCrc_DmaRegType, TYPEDEF, REGSPACE))0xFFD71000UL, + /* END Msg(2:3432)-2 */ + /* END Msg(2:0303)-2 */ + + /* usDMRS */ + 0x45U + }, + /* Index: 46 - CddCrcDmaDataOutChannel */ + { + /* ucChannelIdx */ + 11U, + + /* pDmaRegs */ + /* MISRA Violation: START Msg(2:0303)-2 */ + /* MISRA Violation: START Msg(2:3432)-2 */ + (P2VAR(volatile CddCrc_DmaRegType, TYPEDEF, REGSPACE))0xFFD72000UL, + /* END Msg(2:3432)-2 */ + /* END Msg(2:0303)-2 */ + + /* usDMRS */ + 0x46U + }, + /* Index: 47 - CddCrcDmaCommandChannel */ + { + /* ucChannelIdx */ + 11U, + + /* pDmaRegs */ + /* MISRA Violation: START Msg(2:0303)-2 */ + /* MISRA Violation: START Msg(2:3432)-2 */ + (P2VAR(volatile CddCrc_DmaRegType, TYPEDEF, REGSPACE))0xFFD8B000UL, + /* END Msg(2:3432)-2 */ + /* END Msg(2:0303)-2 */ + + /* usDMRS */ + 0x45U + }, + /* Index: 48 - CddCrcDmaResultChannel */ + { + /* ucChannelIdx */ + 12U, + + /* pDmaRegs */ + /* MISRA Violation: START Msg(2:0303)-2 */ + /* MISRA Violation: START Msg(2:3432)-2 */ + (P2VAR(volatile CddCrc_DmaRegType, TYPEDEF, REGSPACE))0xFFD76000UL, + /* END Msg(2:3432)-2 */ + /* END Msg(2:0303)-2 */ + + /* usDMRS */ + 0x80U + }, + /* Index: 49 - CddCrcDmaDataInChannel */ + { + /* ucChannelIdx */ + 12U, + + /* pDmaRegs */ + /* MISRA Violation: START Msg(2:0303)-2 */ + /* MISRA Violation: START Msg(2:3432)-2 */ + (P2VAR(volatile CddCrc_DmaRegType, TYPEDEF, REGSPACE))0xFFD74000UL, + /* END Msg(2:3432)-2 */ + /* END Msg(2:0303)-2 */ + + /* usDMRS */ + 0x81U + }, + /* Index: 50 - CddCrcDmaDataOutChannel */ + { + /* ucChannelIdx */ + 12U, + + /* pDmaRegs */ + /* MISRA Violation: START Msg(2:0303)-2 */ + /* MISRA Violation: START Msg(2:3432)-2 */ + (P2VAR(volatile CddCrc_DmaRegType, TYPEDEF, REGSPACE))0xFFD75000UL, + /* END Msg(2:3432)-2 */ + /* END Msg(2:0303)-2 */ + + /* usDMRS */ + 0x82U + }, + /* Index: 51 - CddCrcDmaCommandChannel */ + { + /* ucChannelIdx */ + 12U, + + /* pDmaRegs */ + /* MISRA Violation: START Msg(2:0303)-2 */ + /* MISRA Violation: START Msg(2:3432)-2 */ + (P2VAR(volatile CddCrc_DmaRegType, TYPEDEF, REGSPACE))0xFFD8C000UL, + /* END Msg(2:3432)-2 */ + /* END Msg(2:0303)-2 */ + + /* usDMRS */ + 0x81U + }, + /* Index: 52 - CddCrcDmaResultChannel */ + { + /* ucChannelIdx */ + 13U, + + /* pDmaRegs */ + /* MISRA Violation: START Msg(2:0303)-2 */ + /* MISRA Violation: START Msg(2:3432)-2 */ + (P2VAR(volatile CddCrc_DmaRegType, TYPEDEF, REGSPACE))0xFFD79000UL, + /* END Msg(2:3432)-2 */ + /* END Msg(2:0303)-2 */ + + /* usDMRS */ + 0x84U + }, + /* Index: 53 - CddCrcDmaDataInChannel */ + { + /* ucChannelIdx */ + 13U, + + /* pDmaRegs */ + /* MISRA Violation: START Msg(2:0303)-2 */ + /* MISRA Violation: START Msg(2:3432)-2 */ + (P2VAR(volatile CddCrc_DmaRegType, TYPEDEF, REGSPACE))0xFFD77000UL, + /* END Msg(2:3432)-2 */ + /* END Msg(2:0303)-2 */ + + /* usDMRS */ + 0x85U + }, + /* Index: 54 - CddCrcDmaDataOutChannel */ + { + /* ucChannelIdx */ + 13U, + + /* pDmaRegs */ + /* MISRA Violation: START Msg(2:0303)-2 */ + /* MISRA Violation: START Msg(2:3432)-2 */ + (P2VAR(volatile CddCrc_DmaRegType, TYPEDEF, REGSPACE))0xFFD78000UL, + /* END Msg(2:3432)-2 */ + /* END Msg(2:0303)-2 */ + + /* usDMRS */ + 0x86U + }, + /* Index: 55 - CddCrcDmaCommandChannel */ + { + /* ucChannelIdx */ + 13U, + + /* pDmaRegs */ + /* MISRA Violation: START Msg(2:0303)-2 */ + /* MISRA Violation: START Msg(2:3432)-2 */ + (P2VAR(volatile CddCrc_DmaRegType, TYPEDEF, REGSPACE))0xFFD8D000UL, + /* END Msg(2:3432)-2 */ + /* END Msg(2:0303)-2 */ + + /* usDMRS */ + 0x85U + }, + /* Index: 56 - CddCrcDmaResultChannel */ + { + /* ucChannelIdx */ + 14U, + + /* pDmaRegs */ + /* MISRA Violation: START Msg(2:0303)-2 */ + /* MISRA Violation: START Msg(2:3432)-2 */ + (P2VAR(volatile CddCrc_DmaRegType, TYPEDEF, REGSPACE))0xFFD7C000UL, + /* END Msg(2:3432)-2 */ + /* END Msg(2:0303)-2 */ + + /* usDMRS */ + 0xC0U + }, + /* Index: 57 - CddCrcDmaDataInChannel */ + { + /* ucChannelIdx */ + 14U, + + /* pDmaRegs */ + /* MISRA Violation: START Msg(2:0303)-2 */ + /* MISRA Violation: START Msg(2:3432)-2 */ + (P2VAR(volatile CddCrc_DmaRegType, TYPEDEF, REGSPACE))0xFFD7A000UL, + /* END Msg(2:3432)-2 */ + /* END Msg(2:0303)-2 */ + + /* usDMRS */ + 0xC1U + }, + /* Index: 58 - CddCrcDmaDataOutChannel */ + { + /* ucChannelIdx */ + 14U, + + /* pDmaRegs */ + /* MISRA Violation: START Msg(2:0303)-2 */ + /* MISRA Violation: START Msg(2:3432)-2 */ + (P2VAR(volatile CddCrc_DmaRegType, TYPEDEF, REGSPACE))0xFFD7B000UL, + /* END Msg(2:3432)-2 */ + /* END Msg(2:0303)-2 */ + + /* usDMRS */ + 0xC2U + }, + /* Index: 59 - CddCrcDmaCommandChannel */ + { + /* ucChannelIdx */ + 14U, + + /* pDmaRegs */ + /* MISRA Violation: START Msg(2:0303)-2 */ + /* MISRA Violation: START Msg(2:3432)-2 */ + (P2VAR(volatile CddCrc_DmaRegType, TYPEDEF, REGSPACE))0xFFD8E000UL, + /* END Msg(2:3432)-2 */ + /* END Msg(2:0303)-2 */ + + /* usDMRS */ + 0xC1U + }, + /* Index: 60 - CddCrcDmaResultChannel */ + { + /* ucChannelIdx */ + 15U, + + /* pDmaRegs */ + /* MISRA Violation: START Msg(2:0303)-2 */ + /* MISRA Violation: START Msg(2:3432)-2 */ + (P2VAR(volatile CddCrc_DmaRegType, TYPEDEF, REGSPACE))0xFFD7D000UL, + /* END Msg(2:3432)-2 */ + /* END Msg(2:0303)-2 */ + + /* usDMRS */ + 0xC4U + }, + /* Index: 61 - CddCrcDmaDataInChannel */ + { + /* ucChannelIdx */ + 15U, + + /* pDmaRegs */ + /* MISRA Violation: START Msg(2:0303)-2 */ + /* MISRA Violation: START Msg(2:3432)-2 */ + (P2VAR(volatile CddCrc_DmaRegType, TYPEDEF, REGSPACE))0xFFD7E000UL, + /* END Msg(2:3432)-2 */ + /* END Msg(2:0303)-2 */ + + /* usDMRS */ + 0xC5U + }, + /* Index: 62 - CddCrcDmaDataOutChannel */ + { + /* ucChannelIdx */ + 15U, + + /* pDmaRegs */ + /* MISRA Violation: START Msg(2:0303)-2 */ + /* MISRA Violation: START Msg(2:3432)-2 */ + (P2VAR(volatile CddCrc_DmaRegType, TYPEDEF, REGSPACE))0xFFD7F000UL, + /* END Msg(2:3432)-2 */ + /* END Msg(2:0303)-2 */ + + /* usDMRS */ + 0xC6U + }, + /* Index: 63 - CddCrcDmaCommandChannel */ + { + /* ucChannelIdx */ + 15U, + + /* pDmaRegs */ + /* MISRA Violation: START Msg(2:0303)-2 */ + /* MISRA Violation: START Msg(2:3432)-2 */ + (P2VAR(volatile CddCrc_DmaRegType, TYPEDEF, REGSPACE))0xFFD8F000UL, + /* END Msg(2:3432)-2 */ + /* END Msg(2:0303)-2 */ + + /* usDMRS */ + 0xC5U + } +}; +/* END Msg(1:1504)-1 */ + +/* HWIP function table */ +/* MISRA Violation: START Msg(1:1531)-3 */ +CONSTP2CONST(CddCrc_HwFuncTableType, CDDCRC_CONST, CDDCRC_CONFIG_DATA) + CddCrc_GaaHWFunc[] = +{ + /* Pointer to CRC function */ + &CddCrc_Func, + /* Pointer to KCRC function */ + &CddCrc_KcrcFunc, + /* Pointer to AES_ACC function */ + NULL_PTR +}; +/* END Msg(1:1531)-3 */ + +/* Channel configuration */ +/* MISRA Violation: START Msg(1:1504)-1 */ +CONST(CddCrc_ChannelConfigType, CDDCRC_CONFIG_DATA) CddCrc_GaaChannelConfig[] = +{ + /* Index: 0 - CRC0 */ + { + /* ucHWIPType */ + CDDCRC_HWIP_CRC, + + /* pChannelConfig */ + /* MISRA Violation: START Msg(2:0315)-4 */ + &CddCrc_GaaCrcChannelConfig[0], + /* END Msg(2:0315)-4 */ + + /* ucWcrcIndex */ + 0U, + + /* pWcrcRegs */ + /* MISRA Violation: START Msg(2:0303)-2 */ + /* MISRA Violation: START Msg(2:3432)-2 */ + (P2VAR(volatile CddCrc_CommonRegType, TYPEDEF, REGSPACE))0xE7080800UL, + /* END Msg(2:3432)-2 */ + /* END Msg(2:0303)-2 */ + + /* pFifoRegs */ + /* MISRA Violation: START Msg(2:0303)-2 */ + /* MISRA Violation: START Msg(2:3432)-2 */ + (P2CONST(volatile CddCrc_FifoRegType, TYPEDEF, REGSPACE))0xFFFF0800UL, + /* END Msg(2:3432)-2 */ + /* END Msg(2:0303)-2 */ + + /* ucResDmaIndex */ + 0U, + + /* ucInDmaIndex */ + 1U, + + /* ucOutDmaIndex */ + 2U, + + /* ucCmdDmaIndex */ + 3U, + + /* pCompareEndNotification */ + &CompareEndNotiCh0 + }, + /* Index: 1 - KCRC0 */ + { + /* ucHWIPType */ + CDDCRC_HWIP_KCRC, + + /* pChannelConfig */ + /* MISRA Violation: START Msg(2:0315)-4 */ + &CddCrc_GaaKcrcChannelConfig[0], + /* END Msg(2:0315)-4 */ + + /* ucWcrcIndex */ + 0U, + + /* pWcrcRegs */ + /* MISRA Violation: START Msg(2:0303)-2 */ + /* MISRA Violation: START Msg(2:3432)-2 */ + (P2VAR(volatile CddCrc_CommonRegType, TYPEDEF, REGSPACE))0xE7080C00UL, + /* END Msg(2:3432)-2 */ + /* END Msg(2:0303)-2 */ + + /* pFifoRegs */ + /* MISRA Violation: START Msg(2:0303)-2 */ + /* MISRA Violation: START Msg(2:3432)-2 */ + (P2CONST(volatile CddCrc_FifoRegType, TYPEDEF, REGSPACE))0xFFFF0C00UL, + /* END Msg(2:3432)-2 */ + /* END Msg(2:0303)-2 */ + + /* ucResDmaIndex */ + 4U, + + /* ucInDmaIndex */ + 5U, + + /* ucOutDmaIndex */ + 6U, + + /* ucCmdDmaIndex */ + 7U, + + /* pCompareEndNotification */ + NULL_PTR + }, + /* Index: 2 - AES_ACC0 */ + { + /* ucHWIPType */ + CDDCRC_HWIP_AES_ACC, + + /* pChannelConfig */ + NULL_PTR, + + /* ucWcrcIndex */ + 0U, + + /* pWcrcRegs */ + /* MISRA Violation: START Msg(2:0303)-2 */ + /* MISRA Violation: START Msg(2:3432)-2 */ + (P2VAR(volatile CddCrc_CommonRegType, TYPEDEF, REGSPACE))0xE7080000UL, + /* END Msg(2:3432)-2 */ + /* END Msg(2:0303)-2 */ + + /* pFifoRegs */ + /* MISRA Violation: START Msg(2:0303)-2 */ + /* MISRA Violation: START Msg(2:3432)-2 */ + (P2CONST(volatile CddCrc_FifoRegType, TYPEDEF, REGSPACE))0xFFFF0000UL, + /* END Msg(2:3432)-2 */ + /* END Msg(2:0303)-2 */ + + /* ucResDmaIndex */ + 8U, + + /* ucInDmaIndex */ + 9U, + + /* ucOutDmaIndex */ + 10U, + + /* ucCmdDmaIndex */ + 11U, + + /* pCompareEndNotification */ + NULL_PTR + }, + /* Index: 3 - AES_ACC1 */ + { + /* ucHWIPType */ + CDDCRC_HWIP_AES_ACC, + + /* pChannelConfig */ + NULL_PTR, + + /* ucWcrcIndex */ + 0U, + + /* pWcrcRegs */ + /* MISRA Violation: START Msg(2:0303)-2 */ + /* MISRA Violation: START Msg(2:3432)-2 */ + (P2VAR(volatile CddCrc_CommonRegType, TYPEDEF, REGSPACE))0xE7080400UL, + /* END Msg(2:3432)-2 */ + /* END Msg(2:0303)-2 */ + + /* pFifoRegs */ + /* MISRA Violation: START Msg(2:0303)-2 */ + /* MISRA Violation: START Msg(2:3432)-2 */ + (P2CONST(volatile CddCrc_FifoRegType, TYPEDEF, REGSPACE))0xFFFF0400UL, + /* END Msg(2:3432)-2 */ + /* END Msg(2:0303)-2 */ + + /* ucResDmaIndex */ + 12U, + + /* ucInDmaIndex */ + 13U, + + /* ucOutDmaIndex */ + 14U, + + /* ucCmdDmaIndex */ + 15U, + + /* pCompareEndNotification */ + NULL_PTR + }, + /* Index: 4 - CRC1 */ + { + /* ucHWIPType */ + CDDCRC_HWIP_CRC, + + /* pChannelConfig */ + /* MISRA Violation: START Msg(2:0315)-4 */ + &CddCrc_GaaCrcChannelConfig[1], + /* END Msg(2:0315)-4 */ + + /* ucWcrcIndex */ + 1U, + + /* pWcrcRegs */ + /* MISRA Violation: START Msg(2:0303)-2 */ + /* MISRA Violation: START Msg(2:3432)-2 */ + (P2VAR(volatile CddCrc_CommonRegType, TYPEDEF, REGSPACE))0xE7090800UL, + /* END Msg(2:3432)-2 */ + /* END Msg(2:0303)-2 */ + + /* pFifoRegs */ + /* MISRA Violation: START Msg(2:0303)-2 */ + /* MISRA Violation: START Msg(2:3432)-2 */ + (P2CONST(volatile CddCrc_FifoRegType, TYPEDEF, REGSPACE))0xFFFF4800UL, + /* END Msg(2:3432)-2 */ + /* END Msg(2:0303)-2 */ + + /* ucResDmaIndex */ + 16U, + + /* ucInDmaIndex */ + 17U, + + /* ucOutDmaIndex */ + 18U, + + /* ucCmdDmaIndex */ + 19U, + + /* pCompareEndNotification */ + NULL_PTR + }, + /* Index: 5 - CRC2 */ + { + /* ucHWIPType */ + CDDCRC_HWIP_CRC, + + /* pChannelConfig */ + /* MISRA Violation: START Msg(2:0315)-4 */ + &CddCrc_GaaCrcChannelConfig[2], + /* END Msg(2:0315)-4 */ + + /* ucWcrcIndex */ + 2U, + + /* pWcrcRegs */ + /* MISRA Violation: START Msg(2:0303)-2 */ + /* MISRA Violation: START Msg(2:3432)-2 */ + (P2VAR(volatile CddCrc_CommonRegType, TYPEDEF, REGSPACE))0xE70A0800UL, + /* END Msg(2:3432)-2 */ + /* END Msg(2:0303)-2 */ + + /* pFifoRegs */ + /* MISRA Violation: START Msg(2:0303)-2 */ + /* MISRA Violation: START Msg(2:3432)-2 */ + (P2CONST(volatile CddCrc_FifoRegType, TYPEDEF, REGSPACE))0xFFFF8800UL, + /* END Msg(2:3432)-2 */ + /* END Msg(2:0303)-2 */ + + /* ucResDmaIndex */ + 20U, + + /* ucInDmaIndex */ + 21U, + + /* ucOutDmaIndex */ + 22U, + + /* ucCmdDmaIndex */ + 23U, + + /* pCompareEndNotification */ + NULL_PTR + }, + /* Index: 6 - CRC3 */ + { + /* ucHWIPType */ + CDDCRC_HWIP_CRC, + + /* pChannelConfig */ + /* MISRA Violation: START Msg(2:0315)-4 */ + &CddCrc_GaaCrcChannelConfig[3], + /* END Msg(2:0315)-4 */ + + /* ucWcrcIndex */ + 3U, + + /* pWcrcRegs */ + /* MISRA Violation: START Msg(2:0303)-2 */ + /* MISRA Violation: START Msg(2:3432)-2 */ + (P2VAR(volatile CddCrc_CommonRegType, TYPEDEF, REGSPACE))0xE70B0800UL, + /* END Msg(2:3432)-2 */ + /* END Msg(2:0303)-2 */ + + /* pFifoRegs */ + /* MISRA Violation: START Msg(2:0303)-2 */ + /* MISRA Violation: START Msg(2:3432)-2 */ + (P2CONST(volatile CddCrc_FifoRegType, TYPEDEF, REGSPACE))0xFFFFC800UL, + /* END Msg(2:3432)-2 */ + /* END Msg(2:0303)-2 */ + + /* ucResDmaIndex */ + 24U, + + /* ucInDmaIndex */ + 25U, + + /* ucOutDmaIndex */ + 26U, + + /* ucCmdDmaIndex */ + 27U, + + /* pCompareEndNotification */ + NULL_PTR + }, + /* Index: 7 - KCRC1 */ + { + /* ucHWIPType */ + CDDCRC_HWIP_KCRC, + + /* pChannelConfig */ + /* MISRA Violation: START Msg(2:0315)-4 */ + &CddCrc_GaaKcrcChannelConfig[1], + /* END Msg(2:0315)-4 */ + + /* ucWcrcIndex */ + 1U, + + /* pWcrcRegs */ + /* MISRA Violation: START Msg(2:0303)-2 */ + /* MISRA Violation: START Msg(2:3432)-2 */ + (P2VAR(volatile CddCrc_CommonRegType, TYPEDEF, REGSPACE))0xE7090C00UL, + /* END Msg(2:3432)-2 */ + /* END Msg(2:0303)-2 */ + + /* pFifoRegs */ + /* MISRA Violation: START Msg(2:0303)-2 */ + /* MISRA Violation: START Msg(2:3432)-2 */ + (P2CONST(volatile CddCrc_FifoRegType, TYPEDEF, REGSPACE))0xFFFF4C00UL, + /* END Msg(2:3432)-2 */ + /* END Msg(2:0303)-2 */ + + /* ucResDmaIndex */ + 28U, + + /* ucInDmaIndex */ + 29U, + + /* ucOutDmaIndex */ + 30U, + + /* ucCmdDmaIndex */ + 31U, + + /* pCompareEndNotification */ + NULL_PTR + }, + /* Index: 8 - KCRC2 */ + { + /* ucHWIPType */ + CDDCRC_HWIP_KCRC, + + /* pChannelConfig */ + /* MISRA Violation: START Msg(2:0315)-4 */ + &CddCrc_GaaKcrcChannelConfig[2], + /* END Msg(2:0315)-4 */ + + /* ucWcrcIndex */ + 2U, + + /* pWcrcRegs */ + /* MISRA Violation: START Msg(2:0303)-2 */ + /* MISRA Violation: START Msg(2:3432)-2 */ + (P2VAR(volatile CddCrc_CommonRegType, TYPEDEF, REGSPACE))0xE70A0C00UL, + /* END Msg(2:3432)-2 */ + /* END Msg(2:0303)-2 */ + + /* pFifoRegs */ + /* MISRA Violation: START Msg(2:0303)-2 */ + /* MISRA Violation: START Msg(2:3432)-2 */ + (P2CONST(volatile CddCrc_FifoRegType, TYPEDEF, REGSPACE))0xFFFF8C00UL, + /* END Msg(2:3432)-2 */ + /* END Msg(2:0303)-2 */ + + /* ucResDmaIndex */ + 32U, + + /* ucInDmaIndex */ + 33U, + + /* ucOutDmaIndex */ + 34U, + + /* ucCmdDmaIndex */ + 35U, + + /* pCompareEndNotification */ + NULL_PTR + }, + /* Index: 9 - KCRC3 */ + { + /* ucHWIPType */ + CDDCRC_HWIP_KCRC, + + /* pChannelConfig */ + /* MISRA Violation: START Msg(2:0315)-4 */ + &CddCrc_GaaKcrcChannelConfig[3], + /* END Msg(2:0315)-4 */ + + /* ucWcrcIndex */ + 3U, + + /* pWcrcRegs */ + /* MISRA Violation: START Msg(2:0303)-2 */ + /* MISRA Violation: START Msg(2:3432)-2 */ + (P2VAR(volatile CddCrc_CommonRegType, TYPEDEF, REGSPACE))0xE70B0C00UL, + /* END Msg(2:3432)-2 */ + /* END Msg(2:0303)-2 */ + + /* pFifoRegs */ + /* MISRA Violation: START Msg(2:0303)-2 */ + /* MISRA Violation: START Msg(2:3432)-2 */ + (P2CONST(volatile CddCrc_FifoRegType, TYPEDEF, REGSPACE))0xFFFFCC00UL, + /* END Msg(2:3432)-2 */ + /* END Msg(2:0303)-2 */ + + /* ucResDmaIndex */ + 36U, + + /* ucInDmaIndex */ + 37U, + + /* ucOutDmaIndex */ + 38U, + + /* ucCmdDmaIndex */ + 39U, + + /* pCompareEndNotification */ + NULL_PTR + }, + /* Index: 10 - AES_ACC2 */ + { + /* ucHWIPType */ + CDDCRC_HWIP_AES_ACC, + + /* pChannelConfig */ + NULL_PTR, + + /* ucWcrcIndex */ + 1U, + + /* pWcrcRegs */ + /* MISRA Violation: START Msg(2:0303)-2 */ + /* MISRA Violation: START Msg(2:3432)-2 */ + (P2VAR(volatile CddCrc_CommonRegType, TYPEDEF, REGSPACE))0xE7090000UL, + /* END Msg(2:3432)-2 */ + /* END Msg(2:0303)-2 */ + + /* pFifoRegs */ + /* MISRA Violation: START Msg(2:0303)-2 */ + /* MISRA Violation: START Msg(2:3432)-2 */ + (P2CONST(volatile CddCrc_FifoRegType, TYPEDEF, REGSPACE))0xFFFF4000UL, + /* END Msg(2:3432)-2 */ + /* END Msg(2:0303)-2 */ + + /* ucResDmaIndex */ + 40U, + + /* ucInDmaIndex */ + 41U, + + /* ucOutDmaIndex */ + 42U, + + /* ucCmdDmaIndex */ + 43U, + + /* pCompareEndNotification */ + NULL_PTR + }, + /* Index: 11 - AES_ACC3 */ + { + /* ucHWIPType */ + CDDCRC_HWIP_AES_ACC, + + /* pChannelConfig */ + NULL_PTR, + + /* ucWcrcIndex */ + 1U, + + /* pWcrcRegs */ + /* MISRA Violation: START Msg(2:0303)-2 */ + /* MISRA Violation: START Msg(2:3432)-2 */ + (P2VAR(volatile CddCrc_CommonRegType, TYPEDEF, REGSPACE))0xE7090400UL, + /* END Msg(2:3432)-2 */ + /* END Msg(2:0303)-2 */ + + /* pFifoRegs */ + /* MISRA Violation: START Msg(2:0303)-2 */ + /* MISRA Violation: START Msg(2:3432)-2 */ + (P2CONST(volatile CddCrc_FifoRegType, TYPEDEF, REGSPACE))0xFFFF4400UL, + /* END Msg(2:3432)-2 */ + /* END Msg(2:0303)-2 */ + + /* ucResDmaIndex */ + 44U, + + /* ucInDmaIndex */ + 45U, + + /* ucOutDmaIndex */ + 46U, + + /* ucCmdDmaIndex */ + 47U, + + /* pCompareEndNotification */ + NULL_PTR + }, + /* Index: 12 - AES_ACC4 */ + { + /* ucHWIPType */ + CDDCRC_HWIP_AES_ACC, + + /* pChannelConfig */ + NULL_PTR, + + /* ucWcrcIndex */ + 2U, + + /* pWcrcRegs */ + /* MISRA Violation: START Msg(2:0303)-2 */ + /* MISRA Violation: START Msg(2:3432)-2 */ + (P2VAR(volatile CddCrc_CommonRegType, TYPEDEF, REGSPACE))0xE70A0000UL, + /* END Msg(2:3432)-2 */ + /* END Msg(2:0303)-2 */ + + /* pFifoRegs */ + /* MISRA Violation: START Msg(2:0303)-2 */ + /* MISRA Violation: START Msg(2:3432)-2 */ + (P2CONST(volatile CddCrc_FifoRegType, TYPEDEF, REGSPACE))0xFFFF8000UL, + /* END Msg(2:3432)-2 */ + /* END Msg(2:0303)-2 */ + + /* ucResDmaIndex */ + 48U, + + /* ucInDmaIndex */ + 49U, + + /* ucOutDmaIndex */ + 50U, + + /* ucCmdDmaIndex */ + 51U, + + /* pCompareEndNotification */ + NULL_PTR + }, + /* Index: 13 - AES_ACC5 */ + { + /* ucHWIPType */ + CDDCRC_HWIP_AES_ACC, + + /* pChannelConfig */ + NULL_PTR, + + /* ucWcrcIndex */ + 2U, + + /* pWcrcRegs */ + /* MISRA Violation: START Msg(2:0303)-2 */ + /* MISRA Violation: START Msg(2:3432)-2 */ + (P2VAR(volatile CddCrc_CommonRegType, TYPEDEF, REGSPACE))0xE70A0400UL, + /* END Msg(2:3432)-2 */ + /* END Msg(2:0303)-2 */ + + /* pFifoRegs */ + /* MISRA Violation: START Msg(2:0303)-2 */ + /* MISRA Violation: START Msg(2:3432)-2 */ + (P2CONST(volatile CddCrc_FifoRegType, TYPEDEF, REGSPACE))0xFFFF8400UL, + /* END Msg(2:3432)-2 */ + /* END Msg(2:0303)-2 */ + + /* ucResDmaIndex */ + 52U, + + /* ucInDmaIndex */ + 53U, + + /* ucOutDmaIndex */ + 54U, + + /* ucCmdDmaIndex */ + 55U, + + /* pCompareEndNotification */ + NULL_PTR + }, + /* Index: 14 - AES_ACC6 */ + { + /* ucHWIPType */ + CDDCRC_HWIP_AES_ACC, + + /* pChannelConfig */ + NULL_PTR, + + /* ucWcrcIndex */ + 3U, + + /* pWcrcRegs */ + /* MISRA Violation: START Msg(2:0303)-2 */ + /* MISRA Violation: START Msg(2:3432)-2 */ + (P2VAR(volatile CddCrc_CommonRegType, TYPEDEF, REGSPACE))0xE70B0000UL, + /* END Msg(2:3432)-2 */ + /* END Msg(2:0303)-2 */ + + /* pFifoRegs */ + /* MISRA Violation: START Msg(2:0303)-2 */ + /* MISRA Violation: START Msg(2:3432)-2 */ + (P2CONST(volatile CddCrc_FifoRegType, TYPEDEF, REGSPACE))0xFFFFC000UL, + /* END Msg(2:3432)-2 */ + /* END Msg(2:0303)-2 */ + + /* ucResDmaIndex */ + 56U, + + /* ucInDmaIndex */ + 57U, + + /* ucOutDmaIndex */ + 58U, + + /* ucCmdDmaIndex */ + 59U, + + /* pCompareEndNotification */ + NULL_PTR + }, + /* Index: 15 - AES_ACC7 */ + { + /* ucHWIPType */ + CDDCRC_HWIP_AES_ACC, + + /* pChannelConfig */ + NULL_PTR, + + /* ucWcrcIndex */ + 3U, + + /* pWcrcRegs */ + /* MISRA Violation: START Msg(2:0303)-2 */ + /* MISRA Violation: START Msg(2:3432)-2 */ + (P2VAR(volatile CddCrc_CommonRegType, TYPEDEF, REGSPACE))0xE70B0400UL, + /* END Msg(2:3432)-2 */ + /* END Msg(2:0303)-2 */ + + /* pFifoRegs */ + /* MISRA Violation: START Msg(2:0303)-2 */ + /* MISRA Violation: START Msg(2:3432)-2 */ + (P2CONST(volatile CddCrc_FifoRegType, TYPEDEF, REGSPACE))0xFFFFC400UL, + /* END Msg(2:3432)-2 */ + /* END Msg(2:0303)-2 */ + + /* ucResDmaIndex */ + 60U, + + /* ucInDmaIndex */ + 61U, + + /* ucOutDmaIndex */ + 62U, + + /* ucCmdDmaIndex */ + 63U, + + /* pCompareEndNotification */ + NULL_PTR + } +}; +/* END Msg(1:1504)-1 */ + +/* DMA unit configuration */ +/* MISRA Violation: START Msg(1:1504)-1 */ +CONST(CddCrc_DmaUnitConfigType, CDDCRC_CONFIG_DATA) CddCrc_GaaDmaUnitConfig[] = +{ + /* Index: 0 - RT-DMAC0 */ + { + /* pRDMOR */ + /* MISRA Violation: START Msg(2:0303)-2 */ + /* MISRA Violation: START Msg(2:3432)-2 */ + (P2VAR(volatile uint16, TYPEDEF, REGSPACE))0xFFD60060UL + /* END Msg(2:3432)-2 */ + /* END Msg(2:0303)-2 */ + }, + /* Index: 1 - RT-DMAC1 */ + { + /* pRDMOR */ + /* MISRA Violation: START Msg(2:0303)-2 */ + /* MISRA Violation: START Msg(2:3432)-2 */ + (P2VAR(volatile uint16, TYPEDEF, REGSPACE))0xFFD61060UL + /* END Msg(2:3432)-2 */ + /* END Msg(2:0303)-2 */ + }, + /* Index: 2 - RT-DMAC2 */ + { + /* pRDMOR */ + /* MISRA Violation: START Msg(2:0303)-2 */ + /* MISRA Violation: START Msg(2:3432)-2 */ + (P2VAR(volatile uint16, TYPEDEF, REGSPACE))0xFFD62060UL + /* END Msg(2:3432)-2 */ + /* END Msg(2:0303)-2 */ + }, + /* Index: 3 - RT-DMAC3 */ + { + /* pRDMOR */ + /* MISRA Violation: START Msg(2:0303)-2 */ + /* MISRA Violation: START Msg(2:3432)-2 */ + (P2VAR(volatile uint16, TYPEDEF, REGSPACE))0xFFD63060UL + /* END Msg(2:3432)-2 */ + /* END Msg(2:0303)-2 */ + } +}; +/* END Msg(1:1504)-1 */ + +#define CDDCRC_STOP_SEC_CONFIG_DATA_UNSPECIFIED +/* MISRA Violation: START Msg(4:5087)-1 */ +#include "CddCrc_MemMap.h" +/* END Msg(4:5087)-1 */ + +#define CDDCRC_START_SEC_DBTOC_DATA_UNSPECIFIED +/* MISRA Violation: START Msg(4:5087)-1 */ +#include "CddCrc_MemMap.h" +/* END Msg(4:5087)-1 */ + +/* Global array for Global ConfigSet Structure */ +CONST(CddCrc_ConfigType, CDDCRC_CONFIG_DATA) CddCrc_GstConfiguration = +{ + /* ulStartOfDbToc */ + 0x0EFFC100UL, + /* pChannelConfig */ + /* MISRA Violation: START Msg(2:3432)-2 */ + (P2CONST(CddCrc_ChannelConfigType, TYPEDEF, CDDCRC_CONFIG_DATA)) \ + &CddCrc_GaaChannelConfig[0], + /* END Msg(2:3432)-2 */ + /* pWcrcChannelConfig */ + /* MISRA Violation: START Msg(2:3432)-2 */ + (P2CONST(CddCrc_WcrcChannelConfigType, TYPEDEF, CDDCRC_CONFIG_DATA)) \ + &CddCrc_GaaWcrcChannelConfig[0], + /* END Msg(2:3432)-2 */ + /* pDmaChannelConfig */ + /* MISRA Violation: START Msg(2:3432)-2 */ + (P2CONST(CddCrc_DmaConfigType, TYPEDEF, CDDCRC_CONFIG_DATA)) \ + &CddCrc_GaaDmaChannelConfig[0], + /* END Msg(2:3432)-2 */ + /* pDmaUnitConfig */ + /* MISRA Violation: START Msg(2:3432)-2 */ + (P2CONST(CddCrc_DmaUnitConfigType, TYPEDEF, CDDCRC_CONFIG_DATA)) \ + &CddCrc_GaaDmaUnitConfig[0] + /* END Msg(2:3432)-2 */ +}; +#define CDDCRC_STOP_SEC_DBTOC_DATA_UNSPECIFIED +/* MISRA Violation: START Msg(4:5087)-1 */ +#include "CddCrc_MemMap.h" +/* END Msg(4:5087)-1 */ + + +/******************************************************************************* +** Function Definitions ** +*******************************************************************************/ + +/******************************************************************************* +** End of File ** +*******************************************************************************/ + diff --git a/Src/Gen4_R-Car_MCAL/2_Trunk/V4H/MCAL-v4h_19.4.0.D_release/rel/modules/cddemm/sample_application/V4H/19_11/include/CDD_Emm_Cfg.h b/Src/Gen4_R-Car_MCAL/2_Trunk/V4H/MCAL-v4h_19.4.0.D_release/rel/modules/cddemm/sample_application/V4H/19_11/include/CDD_Emm_Cfg.h new file mode 100644 index 00000000..85092c60 --- /dev/null +++ b/Src/Gen4_R-Car_MCAL/2_Trunk/V4H/MCAL-v4h_19.4.0.D_release/rel/modules/cddemm/sample_application/V4H/19_11/include/CDD_Emm_Cfg.h @@ -0,0 +1,3840 @@ +/*============================================================================*/ +/* Project = AUTOSAR Renesas MCAL Components */ +/* Module = CDD_Emm_Cfg.h */ +/*============================================================================*/ +/* COPYRIGHT */ +/*============================================================================*/ +/* Copyright(c) 2026 Renesas Electronics Corporation. */ +/*============================================================================*/ +/* Purpose: */ +/* This file contains pre-compile time parameters */ +/* AUTOMATICALLY GENERATED FILE - DO NOT EDIT */ +/* */ +/*============================================================================*/ +/* */ +/* Unless otherwise agreed upon in writing between your company and */ +/* Renesas Electronics Corporation the following shall apply! */ +/* */ +/* Warranty Disclaimer */ +/* */ +/* There is no warranty of any kind whatsoever granted by Renesas. Any */ +/* warranty is expressly disclaimed and excluded by Renesas, either expressed */ +/* or implied, including but not limited to those for non-infringement of */ +/* intellectual property, merchantability and/or fitness for the particular */ +/* purpose. */ +/* */ +/* Renesas shall not have any obligation to maintain, service or provide bug */ +/* fixes for the supplied Product(s) and/or the Application. */ +/* */ +/* Each User is solely responsible for determining the appropriateness of */ +/* using the Product(s) and assumes all risks associated with its exercise */ +/* of rights under this Agreement, including, but not limited to the risks */ +/* and costs of program errors, compliance with applicable laws, damage to */ +/* or loss of data, programs or equipment, and unavailability or */ +/* interruption of operations. */ +/* */ +/* Limitation of Liability */ +/* */ +/* In no event shall Renesas be liable to the User for any incidental, */ +/* consequential, indirect, or punitive damage (including but not limited */ +/* to lost profits) regardless of whether such liability is based on breach */ +/* of contract, tort, strict liability, breach of warranties, failure of */ +/* essential purpose or otherwise and even if advised of the possibility of */ +/* such damages. Renesas shall not be liable for any services or products */ +/* provided by third party vendors, developers or consultants identified or */ +/* referred to the User by Renesas in connection with the Product(s) and/or */ +/* the Application. */ +/* */ +/*============================================================================*/ +/* Environment: */ +/* Devices: V4H */ +/*============================================================================*/ + + +/******************************************************************************* +** Revision Control History ** +*******************************************************************************/ + + + +/******************************************************************************* +** Generation Tool Version ** +*******************************************************************************/ +/* */ +/* TOOL VERSION: CddEmmRCAR.dll version: 1.0.9, MCALConfGen.exe version: 1.2.3 */ +/* */ + + +/******************************************************************************* +** Input File ** +*******************************************************************************/ +/* + * INPUT FILE: C:\Work\Src\Gen4_R-Car_MCAL\2_Trunk\V4H\MCAL-v4h_19.4.0.D_release\rel\modules\cddemm\sample_application\V4H\19_11\config\App_CDD_EMM_V4H_Sample.arxml + * C:\Work\Src\Gen4_R-Car_MCAL\2_Trunk\V4H\MCAL-v4h_19.4.0.D_release\rel\modules\cddemm\generator\V4H\R1911_CDD_EMM_V4H_BSWMDT.arxml + * C:\Work\Src\Gen4_R-Car_MCAL\2_Trunk\V4H\MCAL-v4h_19.4.0.D_release\rel\common\generic\stubs\19_11\Dem\xml\Dem_CDD_Emm.arxml + * C:\Work\Src\Gen4_R-Car_MCAL\2_Trunk\V4H\MCAL-v4h_19.4.0.D_release\rel\V4H\common_family\generator\arm\Sample_Application_V4H.trxml + * GENERATED ON: 19 6 2026 - 05:12:32 + */ + + +#ifndef CDD_EMM_CFG_H +#define CDD_EMM_CFG_H + + +/******************************************************************************* +** Include Section ** +*******************************************************************************/ + +/******************************************************************************* +** MISRA C Rule Violations ** +*******************************************************************************/ +/******************************************************************************/ +/* 1. MISRA C RULE VIOLATION: */ +/* Message : (7:0791) [U] Macro identifier does not differ from */ +/* other macro identifier(s) (e.g. '%s') within the */ +/* specified number of significant characters. */ +/* Rule : MISRA C:2012 Rule-5.4 */ +/* REFERENCE - ISO:C90-6.1.2 Identifiers - Implementation */ +/* Limits. */ +/* Justification : This macro identifier is following AUTOSAR standard rule */ +/* (Symbolic Name or Published Macro's name), */ +/* so this is accepted. */ +/* Verification : However, part of the code is verified manually */ +/* and it is not having any impact. */ +/* Reference : Look for START Msg(7:0791)-1 and */ +/* END Msg(7:0791)-1 tags in the code. */ +/******************************************************************************/ + + +/******************************************************************************* +** Version Information ** +*******************************************************************************/ +/* Autosar Release Version Information */ +#define CDDEMM_CFG_AR_RELEASE_MAJOR_VERSION 4U +#define CDDEMM_CFG_AR_RELEASE_MINOR_VERSION 5U +#define CDDEMM_CFG_AR_RELEASE_REVISION_VERSION 0U +/* File Version Information */ +#define CDDEMM_CFG_SW_MAJOR_VERSION 1U +#define CDDEMM_CFG_SW_MINOR_VERSION 0U +#define CDDEMM_AR_VERSION CDDEMM_AR_1911_VERSION + +/******************************************************************************* +** Common Published Information ** +*******************************************************************************/ +#define CDDEMM_AR_RELEASE_MAJOR_VERSION_VALUE 4U +#define CDDEMM_AR_RELEASE_MINOR_VERSION_VALUE 5U +#define CDDEMM_AR_RELEASE_REVISION_VERSION_VALUE 0U +#define CDDEMM_SW_MAJOR_VERSION_VALUE 1U +#define CDDEMM_SW_MINOR_VERSION_VALUE 0U +#define CDDEMM_SW_PATCH_VERSION_VALUE 9U +#define CDDEMM_VENDOR_ID_VALUE 59U +#define CDDEMM_MODULE_ID_VALUE 255U + +/******************************************************************************* +** Global Symbols ** +*******************************************************************************/ + + +/* Pre-compile option for Already Init Check */ +#define CDDEMM_ALREADY_INIT_DET_CHECK STD_ON + +/* Pre-compile option for Critical Section */ +#define CDDEMM_CRITICAL_SECTION_PROTECTION STD_ON + +/* Pre-compile option for Development Error Detect */ +#define CDDEMM_DEV_ERROR_DETECT STD_OFF + +/* Pre-compile option for Dependencies Version Check */ +#define CDDEMM_VERSION_CHECK_EXT_MODULES STD_ON + +/* Pre-compile option for Unintended Interrupt Check */ +#define CDDEMM_UNINTENDED_INTERRUPT_CHECK STD_ON + +/* Pre-compile option for Register Write Error Report */ +#define CDDEMM_WRITE_VERIFY_CHECK WV_RUNTIME + +/* Pre-compile option for Version Info API */ +#define CDDEMM_VERSION_INFO_API STD_ON + +/* Pre-compile option for Pseudo Error API */ +#define CDDEMM_PSEUDO_ERROR_API STD_ON + +/* Error Count Function API */ +#define CDDEMM_ERROR_COUNT_API STD_ON + +/* Pre-compile option for Software Generate Error API of the CDDEMM Driver */ +#define CDDEMM_SOFTWARE_ERROR_API STD_ON + +/* Pre-compile option for Control External Error Request API */ +#define CDDEMM_CONTROL_EXTERNAL_ERROR_REQUEST_API STD_ON + +/* Pre-compile option for DEM Unintended Interrupt Check Error Event */ +#define CDDEMM_E_INTERRUPT_CONTROLLER_FAILURE \ + DemConf_DemEventParameter_CDDEMM_E_INTERRUPT_CONTROLLER_FAILURE + +/* Pre-compile option for DEM Register Write Verify Error Event */ +#define CDDEMM_E_WRITE_VERIFY_FAILURE \ + DemConf_DemEventParameter_CDDEMM_E_WRITE_VERIFY_FAILURE + +/* Pre-compile option for Instance ID of the CDDEMM Driver */ +#define CDDEMM_INSTANCE_ID_VALUE 0U + +/* Supported Device Name */ +#define CDDEMM_DEVICE_NAME V4H + +/* ECM Error Domain 0 Use */ +#define CDDEMM_DOMAIN0_USE STD_ON + +/* ECM Error Domain 1 Use */ +#define CDDEMM_DOMAIN1_USE STD_ON + +/* ECM Error Domain 2 Use */ +#define CDDEMM_DOMAIN2_USE STD_ON + +/* ECM Error Domain 3 Use */ +#define CDDEMM_DOMAIN3_USE STD_ON + +/* ECM Error Domain 4 Use */ +#define CDDEMM_DOMAIN4_USE STD_ON + +/* ECM Error Domain 5 Use */ +#define CDDEMM_DOMAIN5_USE STD_ON + +/* ECM Error Domain 6 Use */ +#define CDDEMM_DOMAIN6_USE STD_ON + +/* ECM Error Domain 7 Use */ +#define CDDEMM_DOMAIN7_USE STD_ON + +/* ECM Error Domain 8 Use */ +#define CDDEMM_DOMAIN8_USE STD_ON + +/* ECM Error Domain 9 Use */ +#define CDDEMM_DOMAIN9_USE STD_ON + +/* ECM Error Domain 10 Use */ +#define CDDEMM_DOMAIN10_USE STD_ON + +/* ECM Error Domain 11 Use */ +#define CDDEMM_DOMAIN11_USE STD_ON + +/* ECM Error Domain 12 Use */ +#define CDDEMM_DOMAIN12_USE STD_ON + +/* ECM Error Domain 13 Use */ +#define CDDEMM_DOMAIN13_USE STD_ON + +/* ECM Error Domain 16 Use */ +#define CDDEMM_DOMAIN16_USE STD_ON + +/* ECM Error Domain 17 Use */ +#define CDDEMM_DOMAIN17_USE STD_ON + +/* ECM Error Domain 18 Use */ +#define CDDEMM_DOMAIN18_USE STD_ON + +/* ECM Error Domain 19 Use */ +#define CDDEMM_DOMAIN19_USE STD_ON + +/* ECM Error Domain 20 Use */ +#define CDDEMM_DOMAIN20_USE STD_ON + +/* ECM Error Domain 21 Use */ +#define CDDEMM_DOMAIN21_USE STD_ON + +/* ECM Error Domain 22 Use */ +#define CDDEMM_DOMAIN22_USE STD_ON + +/* ECM Error Domain 23 Use */ +#define CDDEMM_DOMAIN23_USE STD_ON + +/* ECM Error Domain 24 Use */ +#define CDDEMM_DOMAIN24_USE STD_ON + +/* ECM Error Domain 25 Use */ +#define CDDEMM_DOMAIN25_USE STD_ON + +/* ECM Error Domain 26 Use */ +#define CDDEMM_DOMAIN26_USE STD_ON + +/* ECM Error Domain 27 Use */ +#define CDDEMM_DOMAIN27_USE STD_ON + +/* ECM Error Domain 28 Use */ +#define CDDEMM_DOMAIN28_USE STD_ON + +/* ECM Error Domain 29 Use */ +#define CDDEMM_DOMAIN29_USE STD_ON + +/* ECM Error Domain 30 Use */ +#define CDDEMM_DOMAIN30_USE STD_ON + +/* ECM Error Domain 31 Use */ +#define CDDEMM_DOMAIN31_USE STD_ON + +/* ECM Error Domain 32 Use */ +#define CDDEMM_DOMAIN32_USE STD_ON + +/* ECM Error Domain 33 Use */ +#define CDDEMM_DOMAIN33_USE STD_ON + +/* ECM Error Domain 34 Use */ +#define CDDEMM_DOMAIN34_USE STD_ON + +/* ECM Error Domain 35 Use */ +#define CDDEMM_DOMAIN35_USE STD_ON + +/* ECM Error Domain 36 Use */ +#define CDDEMM_DOMAIN36_USE STD_ON + +/* ECM Error Domain 38 Use */ +#define CDDEMM_DOMAIN38_USE STD_ON + +/* ECM Error Domain 39 Use */ +#define CDDEMM_DOMAIN39_USE STD_ON + +/* ECM Error Domain 40 Use */ +#define CDDEMM_DOMAIN40_USE STD_ON + +/* ECM Error Domain 41 Use */ +#define CDDEMM_DOMAIN41_USE STD_ON + +/* ECM Error Domain 42 Use */ +#define CDDEMM_DOMAIN42_USE STD_ON + +/* Maximum number of error register */ +#define CDDEMM_MAX_ERROR_REGISTER 40 + +/* Maximum number of error count register */ +#define CDDEMM_MAX_ERROR_COUNT_REGISTER 49 + +/* Maximum number of error signals enabled */ +#define CDDEMM_MAX_ERROR_ENABLE 833 + + +/******************************************************************************* +** Global Data Types ** +*******************************************************************************/ + + + +/******************************************************************************* +** Global Data ** +*******************************************************************************/ + + + +/******************************************************************************* +** Function Prototypes ** +*******************************************************************************/ + + +/* Error Signal ID */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain0_CddEmmBit0DBSC5DFIDomainDCLSErrDbs0 \ + (uint32)0x00000000UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain0_CddEmmBit1DBSC5AXIDomainDCLSErrDbs0 \ + (uint32)0x00000001UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain0_CddEmmBit2DBSC5DFIDomainDCLSErrDbs1 \ + (uint32)0x00000002UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain0_CddEmmBit3DBSC5AXIDomainDCLSErrDbs1 \ + (uint32)0x00000003UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain0_CddEmmBit12SYSCIsolationCellErr \ + (uint32)0x00000004UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain0_CddEmmBit13FusesmRedundantComparitionErr \ + (uint32)0x00000005UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain0_CddEmmBit14FSFailErr (uint32)0x00000006UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain0_CddEmmBit15FSTimeOutErr (uint32)0x00000007UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain0_CddEmmBit16FSScanAXIbusErr (uint32)0x00000008UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain0_CddEmmBit17ICUMXWdtOverFlowErr \ + (uint32)0x00000009UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain0_CddEmmBit18ICUMXBusAesOusideDmacEdcErr \ + (uint32)0x0000000AUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain0_CddEmmBit19ICUMXAesDmaLockstepErr \ + (uint32)0x0000000BUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain0_CddEmmBit20APSysGenericCounterOperationErr \ + (uint32)0x0000000CUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain0_CddEmmBit21APSysGenericCounterComparisonErr \ + (uint32)0x0000000DUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain0_CddEmmBit22SYSCWriteAcessProtectionErr \ + (uint32)0x0000000EUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain0_CddEmmBit23SYSCHWRedundantErr \ + (uint32)0x0000000FUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain0_CddEmmBit24BootROMMultiBitErr \ + (uint32)0x00000010UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain0_CddEmmBit25BootROMSingleBitErr \ + (uint32)0x00000011UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain0_CddEmmBit26BootROMMultiBitErr2 \ + (uint32)0x00000012UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain0_CddEmmBit27BootROMSingleBitErr2 \ + (uint32)0x00000013UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain0_CddEmmBit28BootROMAccessICUMXErr \ + (uint32)0x00000014UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain0_CddEmmBit29CPGIllegalAccessErr \ + (uint32)0x00000015UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain0_CddEmmBit30CPGFreqErr (uint32)0x00000016UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain0_CddEmmBit31WriteProtectFailerReset \ + (uint32)0x00000017UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain1_CddEmmBit14APSysCciAceProtocolErr \ + (uint32)0x00000018UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain1_CddEmmBit15APSysCciADB400MIChkGenErr \ + (uint32)0x00000019UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain1_CddEmmBit19WWDTch6CountErr (uint32)0x0000001AUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain1_CddEmmBit20WWDTch5CountErr (uint32)0x0000001BUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain1_CddEmmBit21WWDTch4CountErr (uint32)0x0000001CUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain1_CddEmmBit22WWDTch3CountErr (uint32)0x0000001DUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain1_CddEmmBit23WWDTch2CountErr (uint32)0x0000001EUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain1_CddEmmBit24WWDTch1CountErr (uint32)0x0000001FUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain1_CddEmmBit25WWDTch0CountErr (uint32)0x00000020UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain1_CddEmmBit26APSysCciAxiProtocolErr \ + (uint32)0x00000021UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain1_CddEmmBit27APSysCciSFRAMEccSedErr \ + (uint32)0x00000022UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain1_CddEmmBit28APSysCciSFRAMEccDedErr \ + (uint32)0x00000023UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain1_CddEmmBit29APSysCciDCLSCompare0Err \ + (uint32)0x00000024UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain1_CddEmmBit30APSysCciIrqFunctionErr \ + (uint32)0x00000025UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain1_CddEmmBit31APSysCciDCLSCompare1Err \ + (uint32)0x00000026UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain2_CddEmmBit0INTCtpWDTmonitorIMNTRSR0Err \ + (uint32)0x00000027UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain2_CddEmmBit1INTCtpWDTmonitorIMNTRSR1Err \ + (uint32)0x00000028UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain2_CddEmmBit2INTCtpWDTmonitorIMNTRSR2Err \ + (uint32)0x00000029UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain2_CddEmmBit3INTCtpWDTmonitorIMNTRSR3Err \ + (uint32)0x0000002AUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain2_CddEmmBit4INTCtpWDTmonitorIMNTRSR4Err \ + (uint32)0x0000002BUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain2_CddEmmBit5INTCtpWDTmonitorIMNTRSR5Err \ + (uint32)0x0000002CUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain2_CddEmmBit6INTCtpWDTmonitorIMNTRSR6Err \ + (uint32)0x0000002DUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain2_CddEmmBit7INTCtpWDTmonitorIMNTRSR7Err \ + (uint32)0x0000002EUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain2_CddEmmBit8INTCtpWDTmonitorIMNTRSR8Err \ + (uint32)0x0000002FUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain2_CddEmmBit9INTCtpWDTmonitorIMNTRSR9Err \ + (uint32)0x00000030UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain2_CddEmmBit10INTCtpWDTmonitorIMNTRSR10Err \ + (uint32)0x00000031UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain2_CddEmmBit11INTCtpWDTmonitorIMNTRSR11Err \ + (uint32)0x00000032UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain2_CddEmmBit12INTCtpWDTmonitorIMNTRSR12Err \ + (uint32)0x00000033UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain2_CddEmmBit13INTCtpWDTmonitorIMNTRSR13Err \ + (uint32)0x00000034UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain2_CddEmmBit14INTCtpWDTmonitorIMNTRSR14Err \ + (uint32)0x00000035UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain2_CddEmmBit15INTCtpWDTmonitorIMNTRSR15Err \ + (uint32)0x00000036UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain2_CddEmmBit16INTCtpWDTmonitorIMNTRSR16Err \ + (uint32)0x00000037UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain2_CddEmmBit17INTCtpWDTmonitorIMNTRSR17Err \ + (uint32)0x00000038UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain2_CddEmmBit18INTCtpWDTmonitorIMNTRSR18Err \ + (uint32)0x00000039UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain2_CddEmmBit19INTCtpWDTmonitorIMNTRSR19Err \ + (uint32)0x0000003AUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain2_CddEmmBit20INTCtpWDTmonitorIMNTRSR20Err \ + (uint32)0x0000003BUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain2_CddEmmBit21INTCtpWDTmonitorIMNTRSR21Err \ + (uint32)0x0000003CUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain2_CddEmmBit22INTCtpWDTmonitorIMNTRSR22Err \ + (uint32)0x0000003DUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain2_CddEmmBit23INTCtpWDTmonitorIMNTRSR23Err \ + (uint32)0x0000003EUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain2_CddEmmBit24INTCtpWDTmonitorIMNTRSR24Err \ + (uint32)0x0000003FUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain2_CddEmmBit25INTCtpWDTmonitorIMNTRSR25Err \ + (uint32)0x00000040UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain2_CddEmmBit26INTCtpWDTmonitorIMNTRSR26Err \ + (uint32)0x00000041UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain2_CddEmmBit27INTCtpWDTmonitorIMNTRSR27Err \ + (uint32)0x00000042UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain2_CddEmmBit28INTCtpWDTmonitorIMNTRSR28Err \ + (uint32)0x00000043UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain2_CddEmmBit29INTCtpWDTmonitorIMNTRSR29Err \ + (uint32)0x00000044UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain2_CddEmmBit30INTCtpWDTmonitorIMNTRSR30Err \ + (uint32)0x00000045UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain2_CddEmmBit31INTCtpWDTmonitorIMNTRSR31Err \ + (uint32)0x00000046UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain3_CddEmmBit0INTCtpWDTmonitorIMNTRSR32Err \ + (uint32)0x00000047UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain3_CddEmmBit1INTCtpWDTmonitorIMNTRSR33Err \ + (uint32)0x00000048UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain3_CddEmmBit2INTCtpWDTmonitorIMNTRSR34Err \ + (uint32)0x00000049UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain3_CddEmmBit3INTCtpWDTmonitorIMNTRSR35Err \ + (uint32)0x0000004AUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain3_CddEmmBit4INTCtpWDTmonitorIMNTRSR36Err \ + (uint32)0x0000004BUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain3_CddEmmBit5INTCtpWDTmonitorIMNTRSR37Err \ + (uint32)0x0000004CUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain3_CddEmmBit6INTCtpWDTmonitorIMNTRSR38Err \ + (uint32)0x0000004DUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain3_CddEmmBit7INTCtpWDTmonitorIMNTRSR39Err \ + (uint32)0x0000004EUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain3_CddEmmBit8INTCtpWDTmonitorIMNTRSR40Err \ + (uint32)0x0000004FUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain3_CddEmmBit9INTCtpWDTmonitorIMNTRSR41Err \ + (uint32)0x00000050UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain3_CddEmmBit10INTCtpWDTmonitorIMNTRSR42Err \ + (uint32)0x00000051UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain3_CddEmmBit11INTCtpWDTmonitorIMNTRSR43Err \ + (uint32)0x00000052UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain3_CddEmmBit12INTCtpWDTmonitorIMNTRSR44Err \ + (uint32)0x00000053UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain3_CddEmmBit13INTCtpWDTmonitorIMNTRSR45Err \ + (uint32)0x00000054UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain3_CddEmmBit14INTCtpWDTmonitorIMNTRSR46Err \ + (uint32)0x00000055UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain3_CddEmmBit15INTCtpWDTmonitorIMNTRSR47Err \ + (uint32)0x00000056UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain3_CddEmmBit16INTCtpWDTmonitorIMNTRSR48Err \ + (uint32)0x00000057UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain3_CddEmmBit17INTCtpWDTmonitorIMNTRSR49Err \ + (uint32)0x00000058UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain3_CddEmmBit18INTCtpWDTmonitorIMNTRSR50Err \ + (uint32)0x00000059UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain3_CddEmmBit19INTCtpWDTmonitorIMNTRSR51Err \ + (uint32)0x0000005AUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain3_CddEmmBit20INTCtpWDTmonitorIMNTRSR52Err \ + (uint32)0x0000005BUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain3_CddEmmBit21INTCtpWDTmonitorIMNTRSR53Err \ + (uint32)0x0000005CUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain3_CddEmmBit22INTCtpWDTmonitorIMNTRSR54Err \ + (uint32)0x0000005DUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain3_CddEmmBit23INTCtpWDTmonitorIMNTRSR55Err \ + (uint32)0x0000005EUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain3_CddEmmBit24INTCtpWDTmonitorIMNTRSR56Err \ + (uint32)0x0000005FUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain3_CddEmmBit25INTCtpWDTmonitorIMNTRSR57Err \ + (uint32)0x00000060UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain3_CddEmmBit26INTCtpWDTmonitorIMNTRSR58Err \ + (uint32)0x00000061UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain3_CddEmmBit27INTCtpWDTmonitorIMNTRSR59Err \ + (uint32)0x00000062UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain3_CddEmmBit28INTCtpWDTmonitorIMNTRSR60Err \ + (uint32)0x00000063UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain3_CddEmmBit29INTCtpWDTmonitorIMNTRSR61Err \ + (uint32)0x00000064UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain3_CddEmmBit30INTCtpWDTmonitorIMNTRSR62Err \ + (uint32)0x00000065UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain3_CddEmmBit31INTCtpWDTmonitorIMNTRSR63Err \ + (uint32)0x00000066UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain4_CddEmmBit0INTCtpWDTmonitorIMNTRSR64Err \ + (uint32)0x00000067UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain4_CddEmmBit1INTCtpWDTmonitorIMNTRSR65Err \ + (uint32)0x00000068UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain4_CddEmmBit2INTCtpWDTmonitorIMNTRSR66Err \ + (uint32)0x00000069UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain4_CddEmmBit3INTCtpWDTmonitorIMNTRSR67Err \ + (uint32)0x0000006AUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain4_CddEmmBit4INTCtpWDTmonitorIMNTRSR68Err \ + (uint32)0x0000006BUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain4_CddEmmBit5INTCtpWDTmonitorIMNTRSR69Err \ + (uint32)0x0000006CUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain4_CddEmmBit6INTCtpWDTmonitorIMNTRSR70Err \ + (uint32)0x0000006DUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain4_CddEmmBit7INTCtpWDTmonitorIMNTRSR71Err \ + (uint32)0x0000006EUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain4_CddEmmBit8INTCtpWDTmonitorIMNTRSR72Err \ + (uint32)0x0000006FUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain4_CddEmmBit9INTCtpWDTmonitorIMNTRSR73Err \ + (uint32)0x00000070UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain4_CddEmmBit10INTCtpWDTmonitorIMNTRSR74Err \ + (uint32)0x00000071UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain4_CddEmmBit11INTCtpWDTmonitorIMNTRSR75Err \ + (uint32)0x00000072UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain4_CddEmmBit12INTCtpWDTmonitorIMNTRSR76Err \ + (uint32)0x00000073UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain4_CddEmmBit13INTCtpWDTmonitorIMNTRSR77Err \ + (uint32)0x00000074UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain4_CddEmmBit14INTCtpWDTmonitorIMNTRSR78Err \ + (uint32)0x00000075UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain4_CddEmmBit15INTCtpWDTmonitorIMNTRSR79Err \ + (uint32)0x00000076UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain4_CddEmmBit16INTCtpWDTmonitorIMNTRSR80Err \ + (uint32)0x00000077UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain4_CddEmmBit17INTCtpWDTmonitorIMNTRSR81Err \ + (uint32)0x00000078UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain4_CddEmmBit18INTCtpWDTmonitorIMNTRSR82Err \ + (uint32)0x00000079UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain4_CddEmmBit19INTCtpWDTmonitorIMNTRSR83Err \ + (uint32)0x0000007AUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain4_CddEmmBit20INTCtpWDTmonitorIMNTRSR84Err \ + (uint32)0x0000007BUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain4_CddEmmBit21INTCtpWDTmonitorIMNTRSR85Err \ + (uint32)0x0000007CUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain4_CddEmmBit22INTCtpWDTmonitorIMNTRSR86Err \ + (uint32)0x0000007DUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain4_CddEmmBit23INTCtpWDTmonitorIMNTRSR87Err \ + (uint32)0x0000007EUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain4_CddEmmBit24INTCtpWDTmonitorIMNTRSR88Err \ + (uint32)0x0000007FUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain4_CddEmmBit25INTCtpWDTmonitorIMNTRSR89Err \ + (uint32)0x00000080UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain4_CddEmmBit26INTCtpWDTmonitorIMNTRSR90Err \ + (uint32)0x00000081UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain4_CddEmmBit27INTCtpWDTmonitorIMNTRSR91Err \ + (uint32)0x00000082UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain4_CddEmmBit28INTCtpWDTmonitorIMNTRSR92Err \ + (uint32)0x00000083UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain4_CddEmmBit29INTCtpWDTmonitorIMNTRSR93Err \ + (uint32)0x00000084UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain4_CddEmmBit30INTCtpWDTmonitorIMNTRSR94Err \ + (uint32)0x00000085UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain4_CddEmmBit31INTCtpWDTmonitorIMNTRSR95Err \ + (uint32)0x00000086UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain5_CddEmmBit0INTCtpWDTmonitorIMNTRSR96Err \ + (uint32)0x00000087UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain5_CddEmmBit1INTCtpWDTmonitorIMNTRSR97Err \ + (uint32)0x00000088UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain5_CddEmmBit2INTCtpWDTmonitorIMNTRSR98Err \ + (uint32)0x00000089UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain5_CddEmmBit3INTCtpWDTmonitorIMNTRSR99Err \ + (uint32)0x0000008AUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain5_CddEmmBit4INTCtpWDTmonitorIMNTRSR100Err \ + (uint32)0x0000008BUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain5_CddEmmBit5INTCtpWDTmonitorIMNTRSR101Err \ + (uint32)0x0000008CUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain5_CddEmmBit6INTCtpWDTmonitorIMNTRSR102Err \ + (uint32)0x0000008DUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain5_CddEmmBit7INTCtpWDTmonitorIMNTRSR103Err \ + (uint32)0x0000008EUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain5_CddEmmBit8INTCtpWDTmonitorIMNTRSR104Err \ + (uint32)0x0000008FUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain5_CddEmmBit9INTCtpWDTmonitorIMNTRSR105Err \ + (uint32)0x00000090UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain5_CddEmmBit10INTCtpWDTmonitorIMNTRSR106Err \ + (uint32)0x00000091UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain5_CddEmmBit11INTCtpWDTmonitorIMNTRSR107Err \ + (uint32)0x00000092UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain5_CddEmmBit12INTCtpWDTmonitorIMNTRSR108Err \ + (uint32)0x00000093UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain5_CddEmmBit13INTCtpWDTmonitorIMNTRSR109Err \ + (uint32)0x00000094UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain5_CddEmmBit14INTCtpWDTmonitorIMNTRSR110Err \ + (uint32)0x00000095UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain5_CddEmmBit15INTCtpWDTmonitorIMNTRSR111Err \ + (uint32)0x00000096UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain5_CddEmmBit16INTCtpWDTmonitorIMNTRSR112Err \ + (uint32)0x00000097UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain5_CddEmmBit17INTCtpWDTmonitorIMNTRSR113Err \ + (uint32)0x00000098UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain5_CddEmmBit18INTCtpWDTmonitorIMNTRSR114Err \ + (uint32)0x00000099UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain5_CddEmmBit19INTCtpWDTmonitorIMNTRSR115Err \ + (uint32)0x0000009AUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain5_CddEmmBit20INTCtpWDTmonitorIMNTRSR116Err \ + (uint32)0x0000009BUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain5_CddEmmBit21INTCtpWDTmonitorIMNTRSR117Err \ + (uint32)0x0000009CUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain5_CddEmmBit22INTCtpWDTmonitorIMNTRSR118Err \ + (uint32)0x0000009DUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain5_CddEmmBit23INTCtpWDTmonitorIMNTRSR119Err \ + (uint32)0x0000009EUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain5_CddEmmBit24INTCtpWDTmonitorIMNTRSR120Err \ + (uint32)0x0000009FUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain5_CddEmmBit25RTCore0EL1controlledMemoryAccessErr \ + (uint32)0x000000A0UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain5_CddEmmBit26RTCoreProcessorLivelockErr \ + (uint32)0x000000A1UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain5_CddEmmBit27RTCore0SWRunInEL2UnlockTESTR1Err \ + (uint32)0x000000A2UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain5_CddEmmBit28INTCtpEDCAXI4stream3 \ + (uint32)0x000000A3UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain5_CddEmmBit29INTCtpEDCAXI4stream2 \ + (uint32)0x000000A4UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain5_CddEmmBit30INTCtpEDCAXI4stream1 \ + (uint32)0x000000A5UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain5_CddEmmBit31INTCtpEDCAXI4stream0 \ + (uint32)0x000000A6UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain6_CddEmmBit7VIPInternalDOFErr \ + (uint32)0x000000A7UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain6_CddEmmBit9VIPInternalSMPSErr \ + (uint32)0x000000A8UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain6_CddEmmBit11VIPInternalSMPOErr \ + (uint32)0x000000A9UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain6_CddEmmBit24IMPX7SRAMEDCErr (uint32)0x000000AAUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain6_CddEmmBit25IMPX7SRAMECCErr (uint32)0x000000ABUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain6_CddEmmBit26IMPX7BusErr (uint32)0x000000ACUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain6_CddEmmBit27IMPX7ScratchpadMemoryDCLSErr \ + (uint32)0x000000ADUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain6_CddEmmBit28APMUCortexR52Core0ResetControlErr \ + (uint32)0x000000AEUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain6_CddEmmBit29APMUAccessProtectErr \ + (uint32)0x000000AFUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain6_CddEmmBit30APMUDCLSErr (uint32)0x000000B0UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain6_CddEmmBit31MFISCheckerCoreComparisonErr \ + (uint32)0x000000B1UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain7_CddEmmBit0INTCapFaultHandlingInterrupt \ + (uint32)0x000000B2UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain7_CddEmmBit1INTCapErrorHandlingInterrupt \ + (uint32)0x000000B3UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain7_CddEmmBit2AXIBusECMVIP0 (uint32)0x000000B4UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain7_CddEmmBit3AXIBusECMVIO0 (uint32)0x000000B5UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain7_CddEmmBit4AXIBusECMVC0 (uint32)0x000000B6UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain7_CddEmmBit5AXIBusECM3DG (uint32)0x000000B7UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain7_CddEmmBit6AXIBusECMTOP0 (uint32)0x000000B8UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain7_CddEmmBit7AXIBusECMRT0 (uint32)0x000000B9UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain7_CddEmmBit8AXIBusECMHSC (uint32)0x000000BAUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain7_CddEmmBit9AXIBusECMPER00 (uint32)0x000000BBUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain7_CddEmmBit10AXIBusECMMM (uint32)0x000000BCUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain7_CddEmmBit11AXIBusECMIMP (uint32)0x000000BDUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain7_CddEmmBit12VSP2VSPX0InternalSRAMEDCWDTErr \ + (uint32)0x000000BEUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain7_CddEmmBit13VSP2VSPX1InternalSRAMEDCWDTErr \ + (uint32)0x000000BFUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain7_CddEmmBit19RTVRAM0SafetyAccessProtectionErr \ + (uint32)0x000000C0UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain7_CddEmmBit20RTVRAM0SecureAccessProtectionErr \ + (uint32)0x000000C1UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain7_CddEmmBit23RTVRAM0TimeoutErr \ + (uint32)0x000000C2UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain7_CddEmmBit24INTCapCA76Core3RequestOrderErr \ + (uint32)0x000000C3UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain7_CddEmmBit25INTCapCA76Core2RequestOrderErr \ + (uint32)0x000000C4UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain7_CddEmmBit26INTCapCA76Core1RequestOrderErr \ + (uint32)0x000000C5UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain7_CddEmmBit27INTCapCA76Core0RequestOrderErr \ + (uint32)0x000000C6UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain7_CddEmmBit29RTVRAM0EdcMultibitErr \ + (uint32)0x000000C7UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain7_CddEmmBit30RTVRAM0Edc1bitErr \ + (uint32)0x000000C8UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain8_CddEmmBit20DSItxlink1EdcErr \ + (uint32)0x000000C9UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain8_CddEmmBit21DSItxlink0EdcErr \ + (uint32)0x000000CAUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain8_CddEmmBit22APSysCciTransactionOrderCheckMI2Err \ + (uint32)0x000000CBUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain8_CddEmmBit23APSysCciTransactionOrderCheckMI1Err \ + (uint32)0x000000CCUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain8_CddEmmBit24FCPCSInternalSRAMEdcErrr \ + (uint32)0x000000CDUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain8_CddEmmBit25VCPL4CEInternalSRAMEdcErr \ + (uint32)0x000000CEUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain8_CddEmmBit26VCPL4VLCInternalSRAMEdcErr \ + (uint32)0x000000CFUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain8_CddEmmBit27VSP2VSPD1DISCOMUnmatchedWdtErr \ + (uint32)0x000000D0UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain8_CddEmmBit28VSP2VSPD1DISCOMFrozenErrWdt \ + (uint32)0x000000D1UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain8_CddEmmBit29VSP2VSPD0DISCOMUnmatchedWdtErr \ + (uint32)0x000000D2UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain8_CddEmmBit30VSP2VSPD0DISCOMFrozenErr \ + (uint32)0x000000D3UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain8_CddEmmBit31DSCEdcErr (uint32)0x000000D4UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain9_CddEmmBit24ECMSwGenID0Err (uint32)0x000000D5UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain9_CddEmmBit25ECMSwGenID1Err (uint32)0x000000D6UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain9_CddEmmBit26ECMSwGenID2Err (uint32)0x000000D7UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain9_CddEmmBit27ECMSwGenID3Err (uint32)0x000000D8UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain9_CddEmmBit28ECMSwGenID4Err (uint32)0x000000D9UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain9_CddEmmBit29ECMSwGenID5Err (uint32)0x000000DAUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain9_CddEmmBit30ECMSwGenID6Err (uint32)0x000000DBUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain9_CddEmmBit31ECMSwGenID7Err (uint32)0x000000DCUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain10_CddEmmBit0APSysCciEccSedErrCounter \ + (uint32)0x000000DDUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain10_CddEmmBit1APSysCciEccEdcErrCounter \ + (uint32)0x000000DEUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain10_CddEmmBit2RTVRAMRTVRAM0Edc1bitErr \ + (uint32)0x000000DFUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain10_CddEmmBit3RTVRAMRTVRAM0EdcMulbitErr \ + (uint32)0x000000E0UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain10_CddEmmBit6RTCore0TCMCorrectableErrCounter \ + (uint32)0x000000E1UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain10_CddEmmBit8RTCore0InstructionCacheErrCounter \ + (uint32)0x000000E2UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain10_CddEmmBit10RTCore0DataCacheErrCounter \ + (uint32)0x000000E3UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain10_CddEmmBit12RTCore0AXISICorrectableErrCounter \ + (uint32)0x000000E4UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain10_CddEmmBit14RTCore0AXIMICorrectableErrCounter \ + (uint32)0x000000E5UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain10_CddEmmBit16RTCore0ErrCounter \ + (uint32)0x000000E6UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain10_CddEmmBit18RTVRAM1Edc1bitCountupErr \ + (uint32)0x000000E7UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain10_CddEmmBit19RTVRAM1EdcMulbitErr \ + (uint32)0x000000E8UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain10_CddEmmBit20IPMMUmmTLBRAMEdc1bitCountupErr \ + (uint32)0x000000E9UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain10_CddEmmBit21IPMMUmmTLBRAMEdcMultibitCountupErr \ + (uint32)0x000000EAUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain10_CddEmmBit22RTCore1AXIMICorrectableErrCounter \ + (uint32)0x000000EBUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain10_CddEmmBit24RTCore1AXISICorrectableErrCounter \ + (uint32)0x000000ECUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain10_CddEmmBit26RTCore1DataCacheErrCounter \ + (uint32)0x000000EDUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain10_CddEmmBit28RTCore1InstructionCacheErrCounter \ + (uint32)0x000000EEUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain10_CddEmmBit30RTCore1ErrCounter \ + (uint32)0x000000EFUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain11_CddEmmBit0RTCore1TCMCorrectableErrCounter \ + (uint32)0x000000F0UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain11_CddEmmBit2RTCore2AXIMICorrectableErrCounter \ + (uint32)0x000000F1UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain11_CddEmmBit4RTCore2AXISICorrectableErrCounter \ + (uint32)0x000000F2UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain11_CddEmmBit6RTCore2DataCacheErrCounter \ + (uint32)0x000000F3UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain11_CddEmmBit8RTCore2InstructionCacheErrCounter \ + (uint32)0x000000F4UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain11_CddEmmBit10RTCore2ErrCounter \ + (uint32)0x000000F5UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain11_CddEmmBit12RTCore2TCMCorrectableErrCounter \ + (uint32)0x000000F6UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain11_CddEmmBit18APSysCA76Core3L1IL1DL2MmuCorrectedErrCounter \ + (uint32)0x000000F7UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain11_CddEmmBit19APSysCA76Core3L1IL1DL2MmuUncorrectedErrCounter \ + (uint32)0x000000F8UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain11_CddEmmBit20APSysCA76Core2L1IL1DL2MmuCorrectedErrCounter \ + (uint32)0x000000F9UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain11_CddEmmBit21APSysCA76Core2L1IL1DL2MmuUncorrectedErrCounter \ + (uint32)0x000000FAUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain11_CddEmmBit22APSysL3Cl1CorrectedErrCounter \ + (uint32)0x000000FBUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain11_CddEmmBit23APSysL3Cl1UnCorrectedErrCounter \ + (uint32)0x000000FCUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain11_CddEmmBit24APSysCA76Core1L1IL1DL2MmuCorrectedErrCounter \ + (uint32)0x000000FDUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain11_CddEmmBit25APSysCA76Core1L1IL1DL2MmuUncorrectedErrCounter \ + (uint32)0x000000FEUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain11_CddEmmBit26APSysCA76Core0L1IL1DL2MmuCorrectedErrCounter \ + (uint32)0x000000FFUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain11_CddEmmBit27APSysCA76Core0L1IL1DL2MmuUncorrectedErrCounter \ + (uint32)0x00000100UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain11_CddEmmBit28APSysL3Cl0correctedErrCounter \ + (uint32)0x00000101UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain11_CddEmmBit29APSysL3Cl0UncorrectedErrCounter \ + (uint32)0x00000102UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain11_CddEmmBit30CANFDRAMEcc1bitErrCounter \ + (uint32)0x00000103UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain11_CddEmmBit31CANFDRAMEcc2bitErrCounter \ + (uint32)0x00000104UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain12_CddEmmBit0FLEXRAYTBF2InterruptNotificationEccErrCounter \ + (uint32)0x00000105UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain12_CddEmmBit1FLEXRAYTBF2InterruptNotificationEdcErrCounter \ + (uint32)0x00000106UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain12_CddEmmBit2FLEXRAYTBF1InterruptNotificationEccErrCounter \ + (uint32)0x00000107UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain12_CddEmmBit3FLEXRAYTBF1InterruptNotificationEdcErrCounter \ + (uint32)0x00000108UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain12_CddEmmBit4FLEXRAYMBFInterruptNotificationEccErrCounter \ + (uint32)0x00000109UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain12_CddEmmBit5FLEXRAYMBFInterruptNotificationEdcErrCounter \ + (uint32)0x0000010AUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain12_CddEmmBit6EtherAVB2TXRAMEcc1bitErrCounter \ + (uint32)0x0000010BUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain12_CddEmmBit7EtherAVB2TXRAMEccMultibitErrCounter \ + (uint32)0x0000010CUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain12_CddEmmBit8EtherAVB2RXRAMEcc1bitErrCounter \ + (uint32)0x0000010DUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain12_CddEmmBit9EtherAVB2RXRAMEccMultibitErrCounter \ + (uint32)0x0000010EUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain12_CddEmmBit10EtherAVB1TXRAMEcc1bitErrCounter \ + (uint32)0x0000010FUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain12_CddEmmBit11EtherAVB1TXRAMEccMultibitErrCounter \ + (uint32)0x00000110UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain12_CddEmmBit12EtherAVB1RXRAMEcc1bitErrCounter \ + (uint32)0x00000111UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain12_CddEmmBit13EtherAVB1RXRAMEccMultibitErrCounter \ + (uint32)0x00000112UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain12_CddEmmBit14EtherAVB0TXRAMEcc1bitErrCounter \ + (uint32)0x00000113UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain12_CddEmmBit15EtherAVB0TXRAMEccMultibitErrCounter \ + (uint32)0x00000114UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain12_CddEmmBit16EtherAVB0RXRAMEcc1bitErrCounter \ + (uint32)0x00000115UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain12_CddEmmBit17EtherAVB0RXRAMEccMultibitErrCounter \ + (uint32)0x00000116UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain12_CddEmmBit18EtherTSNRxDataSRAMEDCErrCounter \ + (uint32)0x00000117UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain12_CddEmmBit20EtherTSNRxCtrlSRAMEDCErrCounter \ + (uint32)0x00000118UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain12_CddEmmBit22EtherTSNTxDataSRAMEDCErrCounter \ + (uint32)0x00000119UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain12_CddEmmBit24EtherTSNTxCtrlSRAMEDCErrCounter \ + (uint32)0x0000011AUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain12_CddEmmBit26EtherTSNTASCtrlListSRAMEDCErrCounter \ + (uint32)0x0000011BUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain12_CddEmmBit28EtherTSNPSFPCtrlListSRAMEDCErrCounter \ + (uint32)0x0000011CUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain12_CddEmmBit30EtherTSNRxDescriptionrAdrrSRAMEDCErrCounter \ + (uint32)0x0000011DUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain13_CddEmmBit0EtherTSNTxDescriptionrAdrrSRAMEDCErrCounter \ + (uint32)0x0000011EUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain13_CddEmmBit2EtherTSNTxBufferAdrrSRAMEDCErrCounter \ + (uint32)0x0000011FUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain13_CddEmmBit4EtherTSNRxEFrameBufferAdrrSRAMEDCErrCounter \ + (uint32)0x00000120UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain13_CddEmmBit6EtherTSNRxPFrameBufferAdrrSRAMEDCErrCounter \ + (uint32)0x00000121UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain16_CddEmmBit0RTCore0EDCBtwRTCPUAXISlavebridgeErr \ + (uint32)0x00000122UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain16_CddEmmBit1RTCore0TCMMemoriesFatalErr \ + (uint32)0x00000123UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain16_CddEmmBit2RTCore0TCMCorrectableErr \ + (uint32)0x00000124UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain16_CddEmmBit3RTCore0EDCBtwRTCPUWritebufferErr \ + (uint32)0x00000125UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain16_CddEmmBit4RTCore0AXISILockstepComparator0Err \ + (uint32)0x00000126UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain16_CddEmmBit5RTCore0InstructionCacheErr \ + (uint32)0x00000127UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain16_CddEmmBit6RTCore0DataCacheErr \ + (uint32)0x00000128UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain16_CddEmmBit7RTCore0AXISILockstepComparator1Err \ + (uint32)0x00000129UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain16_CddEmmBit8RTCore0AXIMIDECERRSLVERRBusErr \ + (uint32)0x0000012AUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain16_CddEmmBit9RTCore0AXISIFatalErr \ + (uint32)0x0000012BUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain16_CddEmmBit10RTCore0AXISICorrectableErr \ + (uint32)0x0000012CUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain16_CddEmmBit11RTCore0AXIMIFatalErr \ + (uint32)0x0000012DUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain16_CddEmmBit12RTCore0AXIMICorrectableErr \ + (uint32)0x0000012EUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain16_CddEmmBit13RTCore0NonSafetySwitchingComparator0Err \ + (uint32)0x0000012FUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain16_CddEmmBit14THSTsc4TempExceedsThreshold3 \ + (uint32)0x00000130UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain16_CddEmmBit15THSTsc4TempExceedsThreshold2 \ + (uint32)0x00000131UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain16_CddEmmBit16THSTsc4TempExceedsThreshold1 \ + (uint32)0x00000132UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain16_CddEmmBit17THSTsc3TempExceedsThreshold3 \ + (uint32)0x00000133UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain16_CddEmmBit18THSTsc3TempExceedsThreshold2 \ + (uint32)0x00000134UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain16_CddEmmBit19THSTsc3TempExceedsThreshold1 \ + (uint32)0x00000135UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain16_CddEmmBit20THSTsc2TempExceedsThreshold3 \ + (uint32)0x00000136UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain16_CddEmmBit21THSTsc2TempExceedsThreshold2 \ + (uint32)0x00000137UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain16_CddEmmBit22THSTsc2TempExceedsThreshold1 \ + (uint32)0x00000138UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain16_CddEmmBit23THSTsc1TempExceedsThreshold3 \ + (uint32)0x00000139UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain16_CddEmmBit24THSTsc1TempExceedsThreshold2 \ + (uint32)0x0000013AUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain16_CddEmmBit25THSTsc1TempExceedsThreshold1 \ + (uint32)0x0000013BUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain16_CddEmmBit26THSTsc4DetectsFailure \ + (uint32)0x0000013CUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain16_CddEmmBit27THSTsc3DetectsFailure \ + (uint32)0x0000013DUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain16_CddEmmBit28THSTsc2DetectsFailure \ + (uint32)0x0000013EUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain16_CddEmmBit29THSTsc1DetectsFailure \ + (uint32)0x0000013FUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain17_CddEmmBit5RTCore0NonSafetySwitchingComparator1Err \ + (uint32)0x00000140UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain17_CddEmmBit6RTCore0AsynchronousTransferErr \ + (uint32)0x00000141UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain17_CddEmmBit7RTCore0IllegalAxSIZEAxBURSTErr \ + (uint32)0x00000142UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain17_CddEmmBit10RTCore0FatalErrCannotRecorded \ + (uint32)0x00000143UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain17_CddEmmBit11RTCore0CorrectableNotRecordedErr \ + (uint32)0x00000144UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain17_CddEmmBit15RTVRAM0CRCErr (uint32)0x00000145UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain17_CddEmmBit16RTVRAM0CheckerCoreComparitionErr \ + (uint32)0x00000146UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain17_CddEmmBit17RTVRAM1CheckerCoreComparitionErr \ + (uint32)0x00000147UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain17_CddEmmBit18RTVRAM1EdcMultibitErr \ + (uint32)0x00000148UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain17_CddEmmBit19RTVRAM1Edc1bitErr \ + (uint32)0x00000149UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain17_CddEmmBit20RTVRAM1CRCErr (uint32)0x0000014AUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain17_CddEmmBit21RTVRAM1SafetyAccessProtectionErr \ + (uint32)0x0000014BUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain17_CddEmmBit22RTVRAM1SecureAccessProtectionErr \ + (uint32)0x0000014CUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain17_CddEmmBit23RTVRAM1TimeOutErr \ + (uint32)0x0000014DUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain17_CddEmmBit24FCPRCInternaSRAMEdcErr \ + (uint32)0x0000014EUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain17_CddEmmBit25FCPRCDCLSErr (uint32)0x0000014FUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain17_CddEmmBit26FCPRSInternalSRAMEdcErr \ + (uint32)0x00000150UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain17_CddEmmBit27FCPRSDCLSErr (uint32)0x00000151UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain17_CddEmmBit29VIPFCPRMInternalSRAMEdcErr \ + (uint32)0x00000152UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain18_CddEmmBit0RFSOCFE0ErrCh8 (uint32)0x00000153UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain18_CddEmmBit1RFSOCFE0ErrCh9 (uint32)0x00000154UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain18_CddEmmBit2RFSOCFE0ErrCh10 (uint32)0x00000155UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain18_CddEmmBit3RFSOCFE1ErrCh8 (uint32)0x00000156UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain18_CddEmmBit4RFSOCFE1ErrCh9 (uint32)0x00000157UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain18_CddEmmBit5RFSOCFE1ErrCh10 (uint32)0x00000158UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain18_CddEmmBit6RFSOTOEErrCh8 (uint32)0x00000159UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain18_CddEmmBit7RFSOTOEErrCh9 (uint32)0x0000015AUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain18_CddEmmBit8RFSOTOEErrCh10 (uint32)0x0000015BUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain18_CddEmmBit9APMUCortexR52Core2ResetControlErr \ + (uint32)0x0000015CUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain18_CddEmmBit10APMUCortexR52Core1ResetControlErr \ + (uint32)0x0000015DUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain18_CddEmmBit11APMUCA76Cl1PowerControlErr \ + (uint32)0x0000015EUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain18_CddEmmBit12APMUCA76Cl0PowerControlErr \ + (uint32)0x0000015FUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain18_CddEmmBit13iVCP1EInternalSRAMEdcErr \ + (uint32)0x00000160UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain18_CddEmmBit18ISPChSelectorErrCh1 \ + (uint32)0x00000161UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain18_CddEmmBit19ISPCoreErrCh1 (uint32)0x00000162UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain18_CddEmmBit20ISPChSelectorErrCh0 \ + (uint32)0x00000163UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain18_CddEmmBit21ISPCoreErrCh0 (uint32)0x00000164UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain18_CddEmmBit22IMRLX6Ch1EcmErr \ + (uint32)0x00000165UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain18_CddEmmBit23IMRLX6Ch0EcmErr \ + (uint32)0x00000166UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain18_CddEmmBit25IMRLX6Ch4EcmErr \ + (uint32)0x00000167UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain18_CddEmmBit26IMRLX6Ch3EcmErr \ + (uint32)0x00000168UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain18_CddEmmBit27IMRLX6Ch2EcmErr \ + (uint32)0x00000169UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain19_CddEmmBit0DMAC2SYSSecurityAccessErr \ + (uint32)0x0000016AUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain19_CddEmmBit3APSysCciSFRAMAddrFeedbackComparatorErr \ + (uint32)0x0000016BUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain19_CddEmmBit4DBSC5DFIDomaindclsECMErrDbs0 \ + (uint32)0x0000016CUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain19_CddEmmBit5DBSC5AXIDomaindclsECMrrDbs0 \ + (uint32)0x0000016DUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain19_CddEmmBit6DBSC5DFIDomaindclsECMErrDbs1 \ + (uint32)0x0000016EUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain19_CddEmmBit7DBSC5AXIDomaindclsECMErrDbs1 \ + (uint32)0x0000016FUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain19_CddEmmBit8RFSOCFE1ErrCh0 (uint32)0x00000170UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain19_CddEmmBit9RFSOCFE1ErrCh1 (uint32)0x00000171UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain19_CddEmmBit10RFSOCFE1ErrCh2 (uint32)0x00000172UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain19_CddEmmBit11RFSOCFE1ErrCh3 (uint32)0x00000173UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain19_CddEmmBit12RFSOCFE1ErrCh4 (uint32)0x00000174UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain19_CddEmmBit13RFSOCFE1ErrCh5 (uint32)0x00000175UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain19_CddEmmBit14RFSOCFE1ErrCh6 (uint32)0x00000176UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain19_CddEmmBit15RFSOCFE1ErrCh7 (uint32)0x00000177UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain19_CddEmmBit16RFSOCFE0ErrCh0 (uint32)0x00000178UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain19_CddEmmBit17RFSOCFE0ErrCh1 (uint32)0x00000179UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain19_CddEmmBit18RFSOCFE0ErrCh2 (uint32)0x0000017AUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain19_CddEmmBit19RFSOCFE0ErrCh3 (uint32)0x0000017BUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain19_CddEmmBit20RFSOCFE0ErrCh4 (uint32)0x0000017CUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain19_CddEmmBit21RFSOCFE0ErrCh5 (uint32)0x0000017DUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain19_CddEmmBit22RFSOCFE0ErrCh6 (uint32)0x0000017EUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain19_CddEmmBit23RFSOCFE0ErrCh7 (uint32)0x0000017FUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain19_CddEmmBit24RFSOTOEErrCh0 (uint32)0x00000180UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain19_CddEmmBit25RFSOTOEErrCh1 (uint32)0x00000181UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain19_CddEmmBit26RFSOTOEErrCh2 (uint32)0x00000182UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain19_CddEmmBit27RFSOTOEErrCh3 (uint32)0x00000183UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain19_CddEmmBit28RFSOTOEErrCh4 (uint32)0x00000184UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain19_CddEmmBit29RFSOTOEErrCh5 (uint32)0x00000185UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain19_CddEmmBit30RFSOTOEErrCh6 (uint32)0x00000186UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain19_CddEmmBit31RFSOTOEErrCh7 (uint32)0x00000187UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain20_CddEmmBit1IPMMUirCoreComparitionErr \ + (uint32)0x00000188UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain20_CddEmmBit2IPMMUrt0CoreComparitionErr \ + (uint32)0x00000189UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain20_CddEmmBit3IPMMUmmoreComparitionErr \ + (uint32)0x0000018AUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain20_CddEmmBit4IPMMUds0CoreComparitionErr \ + (uint32)0x0000018BUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain20_CddEmmBit5DMAC0RTFusaDCLSComparisonErr \ + (uint32)0x0000018CUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain20_CddEmmBit6DMAC0RTSecurityAccessErr \ + (uint32)0x0000018DUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain20_CddEmmBit9DMAC1RTFusaDCLSComparisonErr \ + (uint32)0x0000018EUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain20_CddEmmBit10DMAC1RTSecurityAccessErr \ + (uint32)0x0000018FUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain20_CddEmmBit13DMAC2RTFusaDCLSComparisonErr \ + (uint32)0x00000190UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain20_CddEmmBit14DMAC2RTSecurityAccessErr \ + (uint32)0x00000191UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain20_CddEmmBit17DMAC3RTFusaDCLSComparisonErr \ + (uint32)0x00000192UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain20_CddEmmBit18DMAC3RTSecurityAccessErr \ + (uint32)0x00000193UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain20_CddEmmBit21DMAC1SYSFusaDCLSComparisonErr \ + (uint32)0x00000194UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain20_CddEmmBit22DMAC1SYSSecurityAccessErr \ + (uint32)0x00000195UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain20_CddEmmBit25DMAC2SYSFusaDCLSComparisonErr \ + (uint32)0x00000196UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain20_CddEmmBit26RTCore0LongHypervisorInterruptErr \ + (uint32)0x00000197UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain20_CddEmmBit27RTCore0HypervisorModeFatalErr \ + (uint32)0x00000198UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain20_CddEmmBit28RTCore0EL2ControlledabortExceptionErr \ + (uint32)0x00000199UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain20_CddEmmBit29RTCore0EL1ControlledAbortExceptionErr \ + (uint32)0x0000019AUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain20_CddEmmBit30RTCore0UndefinedExceptionErr \ + (uint32)0x0000019BUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain20_CddEmmBit31RTCore0AXIMITimeoutErr \ + (uint32)0x0000019CUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain21_CddEmmBit0CPGPLLCBFUSAFreqErr \ + (uint32)0x0000019DUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain21_CddEmmBit1CPGSlAccessBusFreqErr \ + (uint32)0x0000019EUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain21_CddEmmBit2CPGRTckmcr52FreqErr \ + (uint32)0x0000019FUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain21_CddEmmBit3CPGHSCFreqErr (uint32)0x000001A0UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain21_CddEmmBit9CPGMMFreqErr (uint32)0x000001A1UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain21_CddEmmBit10CPGIMPFreqErr (uint32)0x000001A2UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain21_CddEmmBit11CPGVipFreqErr (uint32)0x000001A3UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain21_CddEmmBit12CPGVcFreqErr (uint32)0x000001A4UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain21_CddEmmBit13CPGVioFreqErr (uint32)0x000001A5UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain21_CddEmmBit15CPGPeripheralFreqErr \ + (uint32)0x000001A6UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain21_CddEmmBit16CPGRTckmrtFreqErr \ + (uint32)0x000001A7UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain21_CddEmmBit17CPGGsxFreqErr (uint32)0x000001A8UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain21_CddEmmBit21IPMMUmmTLBRAMEcc1bitlErr \ + (uint32)0x000001A9UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain21_CddEmmBit22IPMMUmmTLBRAMEccMultibitErr \ + (uint32)0x000001AAUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain21_CddEmmBit23IPMMUvip1CoreComparitionErr \ + (uint32)0x000001ABUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain21_CddEmmBit24IPMMUvip0CoreComparitionErr \ + (uint32)0x000001ACUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain21_CddEmmBit25IPMMUvi1CoreComparitionErr \ + (uint32)0x000001ADUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain21_CddEmmBit26IPMMUvi0CoreComparitionErr \ + (uint32)0x000001AEUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain21_CddEmmBit27IPMMUvcCoreComparitionErr \ + (uint32)0x000001AFUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain21_CddEmmBit28IPMMUrt1CoreComparitionErr \ + (uint32)0x000001B0UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain21_CddEmmBit29IPMMU3dgCoreComparitionErr \ + (uint32)0x000001B1UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain21_CddEmmBit31IPMMUhcCoreComparitionErr \ + (uint32)0x000001B2UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain22_CddEmmBit28ICUMXclockmonitorErr \ + (uint32)0x000001B3UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain23_CddEmmBit3FSIRHierarchyCnn0TimeoutErr \ + (uint32)0x000001B4UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain23_CddEmmBit14FSIRHierarchyDSP0TimeoutErr \ + (uint32)0x000001B5UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain23_CddEmmBit15FSIRHierarchyDSP1TimeoutErr \ + (uint32)0x000001B6UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain23_CddEmmBit16FSIRHierarchyDSP2TimeoutErr \ + (uint32)0x000001B7UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain23_CddEmmBit17FSIRHierarchyDSP3TimeoutErr \ + (uint32)0x000001B8UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain23_CddEmmBit20FSIRHierarchyCNRAM0TimeoutErr \ + (uint32)0x000001B9UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain23_CddEmmBit21FSIRHierarchySlimdmac0TimeoutErr \ + (uint32)0x000001BAUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain23_CddEmmBit22FSIRHierarchySlimdmac1TimeoutErr \ + (uint32)0x000001BBUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain23_CddEmmBit23FSIRHierarchyIMPRAM0TimeoutErr \ + (uint32)0x000001BCUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain23_CddEmmBit25FS3DGHierarchyRASCALTimeoutErr \ + (uint32)0x000001BDUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain23_CddEmmBit26FS3DGHierarchyDUSTATimeoutErr \ + (uint32)0x000001BEUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain23_CddEmmBit27FS3DGHierarchySLCSIDEKICKTimeoutErr \ + (uint32)0x000001BFUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain23_CddEmmBit28FS3DGHierarchyexceptRGXcoreTimeoutErr \ + (uint32)0x000001C0UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain23_CddEmmBit29FS3DGHierarchyXonstTimeoutErr \ + (uint32)0x000001C1UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain23_CddEmmBit30FSMMHierarchyDDRTimeoutErr \ + (uint32)0x000001C2UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain24_CddEmmBit0FSVCHierarchyIMR1TimeoutErr \ + (uint32)0x000001C3UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain24_CddEmmBit1FSVCHierarchyIMR2TimeoutErr \ + (uint32)0x000001C4UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain24_CddEmmBit3FSVCHierarchyIMS0TimeoutErr \ + (uint32)0x000001C5UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain24_CddEmmBit4FSVCHierarchyIMS1TimeoutErr \ + (uint32)0x000001C6UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain24_CddEmmBit6FSVIPHierarchyTimeoutErr \ + (uint32)0x000001C7UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain24_CddEmmBit7FSVIPHierarchyDULTimeoutErr \ + (uint32)0x000001C8UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain24_CddEmmBit9FSVIPHierarchyUMFL0TimeoutErr \ + (uint32)0x000001C9UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain24_CddEmmBit11FSVIPHierarchySMPS0TimeoutErr \ + (uint32)0x000001CAUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain24_CddEmmBit15FSVIPHierarchySMPO0TimeoutErr \ + (uint32)0x000001CBUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain24_CddEmmBit17FSVIPHierarchy2CLE0TimeoutErr \ + (uint32)0x000001CCUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain24_CddEmmBit18FSVIPHierarchy2CLE1TimeoutErr \ + (uint32)0x000001CDUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain24_CddEmmBit19FSIRHierarchyTimeoutErr \ + (uint32)0x000001CEUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain24_CddEmmBit20FSIRHierarchyA3IRBusWrapperTimeoutErr \ + (uint32)0x000001CFUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain24_CddEmmBit21FSIRHierarchyIMP0TimeoutErr \ + (uint32)0x000001D0UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain24_CddEmmBit22FSIRHierarchyIMP1TimeoutErr \ + (uint32)0x000001D1UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain24_CddEmmBit23FSIRHierarchyIMP2TimeoutErr \ + (uint32)0x000001D2UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain24_CddEmmBit24FSIRHierarchyIMP3TimeoutErr \ + (uint32)0x000001D3UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain24_CddEmmBit25FSIRHierarchyPSC0DMAC0RepeatTimeoutErr \ + (uint32)0x000001D4UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain24_CddEmmBit26FSIRHierarchyDMAC2DMAC1RepeatTimeoutErr \ + (uint32)0x000001D5UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain24_CddEmmBit27FSIRHierarchyOCV0TimeoutErr \ + (uint32)0x000001D6UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain24_CddEmmBit28FSIRHierarchyOCV1TimeoutErr \ + (uint32)0x000001D7UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain24_CddEmmBit29FSIRHierarchyOCV2TimeoutErr \ + (uint32)0x000001D8UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain24_CddEmmBit30FSIRHierarchyOCV3TimeoutErr \ + (uint32)0x000001D9UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain25_CddEmmBit0FSTOPHierarchyTimeoutErr \ + (uint32)0x000001DAUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain25_CddEmmBit1FSMMHierarchyTimeoutErr \ + (uint32)0x000001DBUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain25_CddEmmBit2FSMMHierarchyDBSC0TimeoutErr \ + (uint32)0x000001DCUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain25_CddEmmBit3FSMMHierarchyDBSC1TimeoutErr \ + (uint32)0x000001DDUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain25_CddEmmBit4FSrtCPUHierarchyTimeoutErr \ + (uint32)0x000001DEUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain25_CddEmmBit5FSrtCPUHierarchyCR52TimeoutErr \ + (uint32)0x000001DFUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain25_CddEmmBit6FSCCIHierarchyTimeoutErr \ + (uint32)0x000001E0UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain25_CddEmmBit7FSCPU0HierarchyC4TimeoutErr \ + (uint32)0x000001E1UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain25_CddEmmBit8FSCPU0HierarchyA3ETimeoutErr \ + (uint32)0x000001E2UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain25_CddEmmBit9FSCPU0HierarchyCl0L3CacheTimeoutErr \ + (uint32)0x000001E3UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain25_CddEmmBit10FSCPU0HierarchyCl1L3CacheTimeoutErr \ + (uint32)0x000001E4UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain25_CddEmmBit11FSCPU0HierarchyCl0CPU0TimeoutErr \ + (uint32)0x000001E5UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain25_CddEmmBit12FSCPU0HierarchyCl0CPU1TimeoutErr \ + (uint32)0x000001E6UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain25_CddEmmBit13FSCPU0HierarchyCl1CPU0TimeoutErr \ + (uint32)0x000001E7UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain25_CddEmmBit14FSCPU0HierarchyCl1CPU1TimeoutErr \ + (uint32)0x000001E8UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain25_CddEmmBit23FSPeripheralDMACHierarchy0TimeoutErr \ + (uint32)0x000001E9UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain25_CddEmmBit24FSHSpeedComHierarchyTimeoutErr \ + (uint32)0x000001EAUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain25_CddEmmBit25FSVIOHierarchyTimeoutErr \ + (uint32)0x000001EBUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain25_CddEmmBit26FSVIOHierarchyISP0TimeoutErr \ + (uint32)0x000001ECUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain25_CddEmmBit27FSVIOHierarchyISP1TimeoutErr \ + (uint32)0x000001EDUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain25_CddEmmBit30FSVCHierarchyTimeoutErr \ + (uint32)0x000001EEUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain25_CddEmmBit31FSVCHierarchyIMR0TimeoutErr \ + (uint32)0x000001EFUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain26_CddEmmBit3FSSIRHierarchyCnn0FailErr \ + (uint32)0x000001F0UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain26_CddEmmBit14FSFSIRHierarchyDSP0FailErr \ + (uint32)0x000001F1UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain26_CddEmmBit15FSFSIRHierarchyDSP1FailErr \ + (uint32)0x000001F2UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain26_CddEmmBit16FSFSIRHierarchyDSP2FailErr \ + (uint32)0x000001F3UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain26_CddEmmBit17FSFSIRHierarchyDSP3FailErr \ + (uint32)0x000001F4UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain26_CddEmmBit20FSFSIRHierarchyCNRAM0FailErr \ + (uint32)0x000001F5UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain26_CddEmmBit21FSFSIRHierarchySlimdmac0FailErr \ + (uint32)0x000001F6UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain26_CddEmmBit22FSFSIRHierarchySlimdmac1FailErr \ + (uint32)0x000001F7UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain26_CddEmmBit23FSFSIRHierarchyIMPRAM0FailErr \ + (uint32)0x000001F8UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain26_CddEmmBit25FSFS3DGHierarchyRASCALFailErr \ + (uint32)0x000001F9UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain26_CddEmmBit26FSFS3DGHierarchyDUSTAFailErr \ + (uint32)0x000001FAUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain26_CddEmmBit27FSFS3DGHierarchySLCSIDEKICKFailErr \ + (uint32)0x000001FBUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain26_CddEmmBit28FSFS3DGHierarchyexceptRGXcoreFailErr \ + (uint32)0x000001FCUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain26_CddEmmBit29FSFS3DGHierarchyXonstFailErr \ + (uint32)0x000001FDUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain26_CddEmmBit30FSFSMMHierarchyDDRFailErr \ + (uint32)0x000001FEUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain27_CddEmmBit0FSSVCHierarchyIMR1FailErr \ + (uint32)0x000001FFUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain27_CddEmmBit1FSSVCHierarchyIMR2FailErr \ + (uint32)0x00000200UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain27_CddEmmBit3FSSVCHierarchyIMS0FailErr \ + (uint32)0x00000201UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain27_CddEmmBit4FSSVCHierarchyIMS1FailErr \ + (uint32)0x00000202UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain27_CddEmmBit6FSSVIPHierarchyFailErr \ + (uint32)0x00000203UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain27_CddEmmBit7FSSVIPHierarchyDULFailErr \ + (uint32)0x00000204UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain27_CddEmmBit9FSSVIPHierarchyUMFL0FailErr \ + (uint32)0x00000205UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain27_CddEmmBit11FSFSVIPHierarchySMPS0FailErr \ + (uint32)0x00000206UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain27_CddEmmBit15FSFSVIPHierarchySMPO0FailErr \ + (uint32)0x00000207UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain27_CddEmmBit17FSFSVIPHierarchy2CLE0FailErr \ + (uint32)0x00000208UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain27_CddEmmBit18FSFSVIPHierarchy2CLE1FailErr \ + (uint32)0x00000209UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain27_CddEmmBit19FSFSIRHierarchyFailErr \ + (uint32)0x0000020AUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain27_CddEmmBit20FSFSIRHierarchyA3IRBusWrapperFailErr \ + (uint32)0x0000020BUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain27_CddEmmBit21FSFSIRHierarchyIMP0FailErr \ + (uint32)0x0000020CUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain27_CddEmmBit22FSFSIRHierarchyIMP1FailErr \ + (uint32)0x0000020DUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain27_CddEmmBit23FSFSIRHierarchyIMP2FailErr \ + (uint32)0x0000020EUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain27_CddEmmBit24FSFSIRHierarchyIMP3FailErr \ + (uint32)0x0000020FUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain27_CddEmmBit25FSFSIRHierarchyPSC0DMAC0RepeatFailErr \ + (uint32)0x00000210UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain27_CddEmmBit26FSFSIRHierarchyDMAC2DMAC1RepeatFailErr \ + (uint32)0x00000211UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain27_CddEmmBit27FSFSIRHierarchyOCV0FailErr \ + (uint32)0x00000212UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain27_CddEmmBit28FSFSIRHierarchyOCV1FailErr \ + (uint32)0x00000213UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain27_CddEmmBit29FSFSIRHierarchyOCV2FailErr \ + (uint32)0x00000214UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain27_CddEmmBit30FSFSIRHierarchyOCV3FailErr \ + (uint32)0x00000215UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain28_CddEmmBit0FSFSTOPHierarchyFailErr \ + (uint32)0x00000216UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain28_CddEmmBit1FSFSMMHierarchyFailErr \ + (uint32)0x00000217UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain28_CddEmmBit2FSFSMMHierarchyDBSC0FailErr \ + (uint32)0x00000218UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain28_CddEmmBit3FSFSMMHierarchyDBSC1FailErr \ + (uint32)0x00000219UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain28_CddEmmBit4FSFSrtCPUHierarchyFailErr \ + (uint32)0x0000021AUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain28_CddEmmBit5FSFSrtCPUHierarchyCR52FailErr \ + (uint32)0x0000021BUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain28_CddEmmBit6FSFSCCIHierarchyFailErr \ + (uint32)0x0000021CUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain28_CddEmmBit7FSFSCPU0HierarchyC4FailErr \ + (uint32)0x0000021DUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain28_CddEmmBit8FSFSCPU0HierarchyA3EFailErr \ + (uint32)0x0000021EUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain28_CddEmmBit9FSFSCPU0HierarchyCl0L3CacheFailErr \ + (uint32)0x0000021FUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain28_CddEmmBit10FSFSCPU0HierarchyCl1L3CacheFailErr \ + (uint32)0x00000220UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain28_CddEmmBit11FSFSCPU0HierarchyCl0CPU0FailErr \ + (uint32)0x00000221UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain28_CddEmmBit12FSFSCPU0HierarchyCl0CPU1FailErr \ + (uint32)0x00000222UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain28_CddEmmBit13FSFSCPU0HierarchyCl1CPU0FailErr \ + (uint32)0x00000223UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain28_CddEmmBit14FSFSCPU0HierarchyCl1CPU1FailErr \ + (uint32)0x00000224UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain28_CddEmmBit23FSFSPeripheralDMACHierarchy0FailErr \ + (uint32)0x00000225UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain28_CddEmmBit24FSFSHSpeedComHierarchyFailErr \ + (uint32)0x00000226UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain28_CddEmmBit25FSFSVIOHierarchyFailErr \ + (uint32)0x00000227UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain28_CddEmmBit26FSFSVIOHierarchyISP0FailErr \ + (uint32)0x00000228UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain28_CddEmmBit27FSFSVIOHierarchyISP1FailErr \ + (uint32)0x00000229UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain28_CddEmmBit30FSFSVCHierarchyFailErr \ + (uint32)0x0000022AUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain28_CddEmmBit31FSFSVCHierarchyIMR0FailErr \ + (uint32)0x0000022BUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain29_CddEmmBit3FSRHierarchyCnn0SCanAXibusErr \ + (uint32)0x0000022CUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain29_CddEmmBit14FSIRHierarchyDSP0SCanAXibusErr \ + (uint32)0x0000022DUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain29_CddEmmBit15FSIRHierarchyDSP1SCanAXibusErr \ + (uint32)0x0000022EUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain29_CddEmmBit16FSIRHierarchyDSP2SCanAXibusErr \ + (uint32)0x0000022FUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain29_CddEmmBit17FSIRHierarchyDSP3SCanAXibusErr \ + (uint32)0x00000230UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain29_CddEmmBit20FSIRHierarchyCNRAM0SCanAXibusErr \ + (uint32)0x00000231UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain29_CddEmmBit21FSIRHierarchySlimdmac0SCanAXibusErr \ + (uint32)0x00000232UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain29_CddEmmBit22FSIRHierarchySlimdmac1SCanAXibusErr \ + (uint32)0x00000233UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain30_CddEmmBit0FSSVCHierarchyIMR1SCanAXiBusErr \ + (uint32)0x00000234UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain30_CddEmmBit1FSSVCHierarchyIMR2SCanAXiBusErr \ + (uint32)0x00000235UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain30_CddEmmBit3FSSVCHierarchyIMS0SCanAXiBusErr \ + (uint32)0x00000236UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain30_CddEmmBit4FSSVCHierarchyIMS1SCanAXiBusErr \ + (uint32)0x00000237UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain30_CddEmmBit7FSSVIPHierarchyDULSCanAXiBusErr \ + (uint32)0x00000238UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain30_CddEmmBit9FSSVIPHierarchyUMFL0SCanAXiBusErr \ + (uint32)0x00000239UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain30_CddEmmBit11FSFSVIPHierarchySMPS0SCanAXibusErr \ + (uint32)0x0000023AUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain30_CddEmmBit15FSFSVIPHierarchySMPO0SCanAXibusErr \ + (uint32)0x0000023BUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain30_CddEmmBit17FSFSVIPHierarchy2CLE0SCanAXibusErr \ + (uint32)0x0000023CUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain30_CddEmmBit18FSFSVIPHierarchy2CLE1SCanAXibusErr \ + (uint32)0x0000023DUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain30_CddEmmBit21FSIRHierarchyIMP0SCanAXibusErr \ + (uint32)0x0000023EUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain30_CddEmmBit22FSIRHierarchyIMP1SCanAXibusErr \ + (uint32)0x0000023FUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain30_CddEmmBit23FSIRHierarchyIMP2SCanAXibusErr \ + (uint32)0x00000240UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain30_CddEmmBit24FSIRHierarchyIMP3SCanAXibusErr \ + (uint32)0x00000241UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain30_CddEmmBit25FSIRHierarchyPSC0DMAC0RepeatSCanAXibusErr \ + (uint32)0x00000242UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain30_CddEmmBit26FSIRHierarchyDMAC2DMAC1RepeatSCanAXibusErr \ + (uint32)0x00000243UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain30_CddEmmBit27FSIRHierarchyOCV0SCanAXibusErr \ + (uint32)0x00000244UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain30_CddEmmBit28FSIRHierarchyOCV1SCanAXibusErr \ + (uint32)0x00000245UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain30_CddEmmBit29FSIRHierarchyOCV2SCanAXibusErr \ + (uint32)0x00000246UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain30_CddEmmBit30FSIRHierarchyOCV3SCanAXibusErr \ + (uint32)0x00000247UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain31_CddEmmBit9FSFSCPU0HierarchyCl0L3CacheSCanAXiBusErr \ + (uint32)0x00000248UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain31_CddEmmBit10FSFSCPU0HierarchyCl1L3CacheSCanAXiBusErr \ + (uint32)0x00000249UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain31_CddEmmBit11FSFSCPU0HierarchyCl0CPU0SCanAXiBusErr \ + (uint32)0x0000024AUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain31_CddEmmBit12FSFSCPU0HierarchyCl0CPU1SCanAXiBusErr \ + (uint32)0x0000024BUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain31_CddEmmBit13FSFSCPU0HierarchyCl1CPU0SCanAXiBusErr \ + (uint32)0x0000024CUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain31_CddEmmBit14FSFSCPU0HierarchyCl1CPU1SCanAXiBusErr \ + (uint32)0x0000024DUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain31_CddEmmBit26FSFSVIOHierarchyISP0SCanAXiBusErr \ + (uint32)0x0000024EUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain31_CddEmmBit27FSFSVIOHierarchyISP1SCanAXiBusErr \ + (uint32)0x0000024FUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain31_CddEmmBit31FSFSVCHierarchyIMR0SCanAXiBusErr \ + (uint32)0x00000250UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain32_CddEmmBit0RTCore1AXIMICorrectableErr \ + (uint32)0x00000251UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain32_CddEmmBit1RTCore1AXIMIFatalErr \ + (uint32)0x00000252UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain32_CddEmmBit2RTCore1AXIMITimeoutErr \ + (uint32)0x00000253UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain32_CddEmmBit3RTCore1AXISICorrectableErr \ + (uint32)0x00000254UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain32_CddEmmBit4RTCore1AXISIFatalErr \ + (uint32)0x00000255UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain32_CddEmmBit5RTCore1AXISILockstepComparator1Err \ + (uint32)0x00000256UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain32_CddEmmBit6RTCore1DataCacheErr \ + (uint32)0x00000257UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain32_CddEmmBit7RTCore1EL1ControlledAbortExceptionErr \ + (uint32)0x00000258UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain32_CddEmmBit8RTCore1EL2ControlledabortExceptionErr \ + (uint32)0x00000259UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain32_CddEmmBit9RTCore1SWRunInEL2UnlockTESTR1Err \ + (uint32)0x0000025AUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain32_CddEmmBit10RTCore1AsynchronousTransferErr \ + (uint32)0x0000025BUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain32_CddEmmBit11RTCore1InstructionCacheErr \ + (uint32)0x0000025CUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain32_CddEmmBit12RTCore1CorrectableNotRecordedErr \ + (uint32)0x0000025DUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain32_CddEmmBit13RTCore1FatalErrCannotRecorded \ + (uint32)0x0000025EUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain32_CddEmmBit14RTCore1ProcessorLivelockErr \ + (uint32)0x0000025FUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain32_CddEmmBit15RTCore1LongHypervisorInterruptErr \ + (uint32)0x00000260UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain32_CddEmmBit16RTCore1AXISILockstepComparator0Err \ + (uint32)0x00000261UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain32_CddEmmBit17RTCore1HypervisorModeFatalErr \ + (uint32)0x00000262UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain32_CddEmmBit18RTCore1EL1controlledMemoryAccessErr \ + (uint32)0x00000263UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain32_CddEmmBit19RTCore1EDCBtwRTCPUWritebufferErr \ + (uint32)0x00000264UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain32_CddEmmBit20RTCore1AXIMIDECERRSLVERRBusErr \ + (uint32)0x00000265UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain32_CddEmmBit21RTCore1NonSafetySwitchingComparator1Err \ + (uint32)0x00000266UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain32_CddEmmBit22RTCore1NonSafetySwitchingComparator0Err \ + (uint32)0x00000267UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain32_CddEmmBit23RTCore1TCMCorrectableErr \ + (uint32)0x00000268UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain32_CddEmmBit24RTCore1TCMMemoriesFatalErr \ + (uint32)0x00000269UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain32_CddEmmBit25RTCore1EDCBtwRTCPUAXISlavebridgeErr \ + (uint32)0x0000026AUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain32_CddEmmBit26RTCore1IllegalAxSIZEAxBURSTErr \ + (uint32)0x0000026BUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain32_CddEmmBit27RTCore1UndefinedExceptionErr \ + (uint32)0x0000026CUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain32_CddEmmBit30CSI21Err (uint32)0x0000026DUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain32_CddEmmBit31CSI20Err (uint32)0x0000026EUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain33_CddEmmBit0RTCore2AXIMICorrectableErr \ + (uint32)0x0000026FUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain33_CddEmmBit1RTCore2AXIMIFatalErr \ + (uint32)0x00000270UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain33_CddEmmBit2RTCore2AXIMITimeoutErr \ + (uint32)0x00000271UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain33_CddEmmBit3RTCore2AXISICorrectableErr \ + (uint32)0x00000272UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain33_CddEmmBit4RTCore2AXISIFatalErr \ + (uint32)0x00000273UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain33_CddEmmBit5RTCore2AXISILockstepComparator1Err \ + (uint32)0x00000274UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain33_CddEmmBit6RTCore2DataCacheErr \ + (uint32)0x00000275UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain33_CddEmmBit7RTCore2EL1ControlledAbortExceptionErr \ + (uint32)0x00000276UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain33_CddEmmBit8RTCore2EL2ControlledabortExceptionErr \ + (uint32)0x00000277UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain33_CddEmmBit9RTCore2SWRunInEL2UnlockTESTR1Err \ + (uint32)0x00000278UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain33_CddEmmBit10RTCore2AsynchronousTransferErr \ + (uint32)0x00000279UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain33_CddEmmBit11RTCore2InstructionCacheErr \ + (uint32)0x0000027AUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain33_CddEmmBit12RTCore2CorrectableNotRecordedErr \ + (uint32)0x0000027BUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain33_CddEmmBit13RTCore2FatalErrCannotRecorded \ + (uint32)0x0000027CUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain33_CddEmmBit14RTCore2ProcessorLivelockErr \ + (uint32)0x0000027DUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain33_CddEmmBit15RTCore2LongHypervisorInterruptErr \ + (uint32)0x0000027EUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain33_CddEmmBit16RTCore2AXISILockstepComparator0Err \ + (uint32)0x0000027FUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain33_CddEmmBit17RTCore2HypervisorModeFatalErr \ + (uint32)0x00000280UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain33_CddEmmBit18RTCore2EL1controlledMemoryAccessErr \ + (uint32)0x00000281UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain33_CddEmmBit19RTCore2EDCBtwRTCPUWritebufferErr \ + (uint32)0x00000282UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain33_CddEmmBit20RTCore2AXIMIDECERRSLVERRBusErr \ + (uint32)0x00000283UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain33_CddEmmBit21RTCore2NonSafetySwitchingComparator1Err \ + (uint32)0x00000284UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain33_CddEmmBit22RTCore2NonSafetySwitchingComparator0Err \ + (uint32)0x00000285UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain33_CddEmmBit23RTCore2TCMCorrectableErr \ + (uint32)0x00000286UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain33_CddEmmBit24RTCore2TCMMemoriesFatalErr \ + (uint32)0x00000287UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain33_CddEmmBit25RTCore2EDCBtwRTCPUAXISlavebridgeErr \ + (uint32)0x00000288UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain33_CddEmmBit26RTCore2IllegalAxSIZEAxBURSTErr \ + (uint32)0x00000289UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain33_CddEmmBit27RTCore2UndefinedExceptionErr \ + (uint32)0x0000028AUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain34_CddEmmBit0PWMLoopbackFunctionErrch0 \ + (uint32)0x0000028BUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain34_CddEmmBit1PWMLoopbackFunctionErrch1 \ + (uint32)0x0000028CUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain34_CddEmmBit2PWMLoopbackFunctionErrch2 \ + (uint32)0x0000028DUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain34_CddEmmBit3PWMLoopbackFunctionErrch3 \ + (uint32)0x0000028EUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain34_CddEmmBit4PWMLoopbackFunctionErrch4 \ + (uint32)0x0000028FUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain34_CddEmmBit5PWMLoopbackFunctionErrch5 \ + (uint32)0x00000290UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain34_CddEmmBit6PWMLoopbackFunctionErrch6 \ + (uint32)0x00000291UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain34_CddEmmBit7PWMLoopbackFunctionErrch7 \ + (uint32)0x00000292UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain34_CddEmmBit8PWMLoopbackFunctionErrch8 \ + (uint32)0x00000293UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain34_CddEmmBit9PWMLoopbackFunctionErrch9 \ + (uint32)0x00000294UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain35_CddEmmBit6APSysApmuCA76Cl1PchProtocolInterfaceErr \ + (uint32)0x00000295UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain35_CddEmmBit7APSysApmuCA76Cl0PchProtocolInterfaceErr \ + (uint32)0x00000296UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain35_CddEmmBit8APSysAXI4StreambusINTAPCA76Cl1RequestOrderErr \ + (uint32)0x00000297UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain35_CddEmmBit9APSysAXI4StreambusINTAPCA76Cl0RequestOrderErr \ + (uint32)0x00000298UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain35_CddEmmBit10APSysAXI4StreambusINTAPCA76Cl1EdcErr \ + (uint32)0x00000299UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain35_CddEmmBit11APSysAXI4StreambusINTAPCA76Cl0EdcErr \ + (uint32)0x0000029AUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain35_CddEmmBit12APSysArmgcCA76Cl1CounterInterfeceErr \ + (uint32)0x0000029BUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain35_CddEmmBit13APSysArmgcCA76Cl0CounterInterfeceErr \ + (uint32)0x0000029CUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain35_CddEmmBit14APSysCA76Core3L1IL1DL2MmuCorrectedErr \ + (uint32)0x0000029DUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain35_CddEmmBit15APSysCA76Core2L1IL1DL2MmuCorrectedErr \ + (uint32)0x0000029EUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain35_CddEmmBit16APSysL3Cl1correctedErr \ + (uint32)0x0000029FUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain35_CddEmmBit17APSysCA76Core1L1IL1DL2MmuCorrectedErr \ + (uint32)0x000002A0UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain35_CddEmmBit18APSysCA76Core0L1IL1DL2MmuCorrectedErr \ + (uint32)0x000002A1UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain35_CddEmmBit19APSysL3Cl0correctedErr \ + (uint32)0x000002A2UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain35_CddEmmBit20APSysCA76Core3L1IL1DL2MmuUncorrectedErr \ + (uint32)0x000002A3UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain35_CddEmmBit21APSysCA76Core2L1IL1DL2MmuUncorrectedErr \ + (uint32)0x000002A4UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain35_CddEmmBit22APSysL3Cl1UncorrectedErr \ + (uint32)0x000002A5UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain35_CddEmmBit23APSysCA76Core1L1IL1DL2MmuUncorrectedErr \ + (uint32)0x000002A6UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain35_CddEmmBit24APSysCA76Core0L1IL1DL2MmuUncorrectedErr \ + (uint32)0x000002A7UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain35_CddEmmBit25APSysL3Cl0UncorrectedErr \ + (uint32)0x000002A8UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain35_CddEmmBit26APSysCA76Cl0RedundantErr \ + (uint32)0x000002A9UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain35_CddEmmBit27APSysCA76Cl0LockstepErr \ + (uint32)0x000002AAUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain35_CddEmmBit28APSysAcebusCciCA76Cl1RequestOrderErr \ + (uint32)0x000002ABUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain35_CddEmmBit29APSysAcebusCciCA76Cl0RequestOrderErr \ + (uint32)0x000002ACUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain35_CddEmmBit30APSysAcebusCciCA76Cl1EdcErr \ + (uint32)0x000002ADUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain35_CddEmmBit31APSysAcebusCciCA76Cl0EdcErr \ + (uint32)0x000002AEUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain36_CddEmmBit0VINCh15ModuleCombinedEdcErr \ + (uint32)0x000002AFUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain36_CddEmmBit1VINCh15ModuleCombinedSafetyErr \ + (uint32)0x000002B0UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain36_CddEmmBit2VINCh14ModuleCombinedEdcErr \ + (uint32)0x000002B1UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain36_CddEmmBit3VINCh14ModuleCombinedSafetyErr \ + (uint32)0x000002B2UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain36_CddEmmBit4VINCh13ModuleCombinedEdcErr \ + (uint32)0x000002B3UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain36_CddEmmBit5VINCh13ModuleCombinedSafetyErr \ + (uint32)0x000002B4UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain36_CddEmmBit6VINCh12ModuleCombinedEdcErr \ + (uint32)0x000002B5UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain36_CddEmmBit7VINCh12ModuleCombinedSafetyErr \ + (uint32)0x000002B6UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain36_CddEmmBit8VINCh11ModuleCombinedEdcErr \ + (uint32)0x000002B7UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain36_CddEmmBit9VINCh11ModuleCombinedSafetyErr \ + (uint32)0x000002B8UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain36_CddEmmBit10VINCh10ModuleCombinedEdcErr \ + (uint32)0x000002B9UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain36_CddEmmBit11VINCh10ModuleCombinedSafetyErr \ + (uint32)0x000002BAUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain36_CddEmmBit12VINCh9ModuleCombinedEdcErr \ + (uint32)0x000002BBUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain36_CddEmmBit13VINCh9ModuleCombinedSafetyErr \ + (uint32)0x000002BCUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain36_CddEmmBit14VINCh8ModuleCombinedEdcErr \ + (uint32)0x000002BDUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain36_CddEmmBit15VINCh8ModuleCombinedSafetyErr \ + (uint32)0x000002BEUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain36_CddEmmBit16VINCh7ModuleCombinedEdcErr \ + (uint32)0x000002BFUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain36_CddEmmBit17VINCh7ModuleCombinedSafetyErr \ + (uint32)0x000002C0UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain36_CddEmmBit18VINCh6ModuleCombinedEdcErr \ + (uint32)0x000002C1UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain36_CddEmmBit19VINCh6ModuleCombinedSafetyErr \ + (uint32)0x000002C2UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain36_CddEmmBit20VINCh5ModuleCombinedEdcErr \ + (uint32)0x000002C3UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain36_CddEmmBit21VINCh5ModuleCombinedSafetyErr \ + (uint32)0x000002C4UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain36_CddEmmBit22VINCh4ModuleCombinedEdcErr \ + (uint32)0x000002C5UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain36_CddEmmBit23VINCh4ModuleCombinedSafetyErr \ + (uint32)0x000002C6UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain36_CddEmmBit24VINCh3ModuleCombinedEdcErr \ + (uint32)0x000002C7UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain36_CddEmmBit25VINCh3ModuleCombinedSafetyErr \ + (uint32)0x000002C8UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain36_CddEmmBit26VINCh2ModuleCombinedEdcErr \ + (uint32)0x000002C9UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain36_CddEmmBit27VINCh2ModuleCombinedSafetyErr \ + (uint32)0x000002CAUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain36_CddEmmBit28VINCh1ModuleCombinedEdcErr \ + (uint32)0x000002CBUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain36_CddEmmBit29VINCh1ModuleCombinedSafetyErr \ + (uint32)0x000002CCUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain36_CddEmmBit30VINCh0ModuleCombinedEdcErr \ + (uint32)0x000002CDUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain36_CddEmmBit31VINCh0ModuleCombinedSafetyErr \ + (uint32)0x000002CEUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain38_CddEmmBit0CANFDRAMEcc1bitErr \ + (uint32)0x000002CFUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain38_CddEmmBit1CANFDRAMEcc2bitErr \ + (uint32)0x000002D0UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain38_CddEmmBit2FLEXRAYTBF2InterruptNotificationEdcErr \ + (uint32)0x000002D1UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain38_CddEmmBit3FLEXRAYTBF2InterruptNotificationEccErr \ + (uint32)0x000002D2UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain38_CddEmmBit4FLEXRAYTBF1InterruptNotificationEdcErr \ + (uint32)0x000002D3UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain38_CddEmmBit5FLEXRAYTBF1InterruptNotificationEccErr \ + (uint32)0x000002D4UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain38_CddEmmBit6FLEXRAYMBFInterruptNotificationEdcErr \ + (uint32)0x000002D5UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain38_CddEmmBit7FLEXRAYMBFInterruptNotificationEccErr \ + (uint32)0x000002D6UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain38_CddEmmBit20EtherAVB2TXRAMEccMultibitErr \ + (uint32)0x000002D7UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain38_CddEmmBit21EtherAVB2RXRAMEccMultibitErr \ + (uint32)0x000002D8UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain38_CddEmmBit22EtherAVB2TXRAMEcc1bitErr \ + (uint32)0x000002D9UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain38_CddEmmBit23EtherAVB2RXRAMEcc1bitErr \ + (uint32)0x000002DAUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain38_CddEmmBit24EtherAVB1TXRAMEccMultibitErr \ + (uint32)0x000002DBUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain38_CddEmmBit25EtherAVB1RXRAMEccMultibitErr \ + (uint32)0x000002DCUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain38_CddEmmBit26EtherAVB1TXRAMEcc1bitErr \ + (uint32)0x000002DDUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain38_CddEmmBit27EtherAVB1RXRAMEcc1bitErr \ + (uint32)0x000002DEUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain38_CddEmmBit28EtherAVB0TXRAMEccMultibitErr \ + (uint32)0x000002DFUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain38_CddEmmBit29EtherAVB0RXRAMEccMultibitErr \ + (uint32)0x000002E0UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain38_CddEmmBit30EtherAVB0TXRAMEcc1bitErr \ + (uint32)0x000002E1UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain38_CddEmmBit31EtherAVB0RXRAMEcc1bitErr \ + (uint32)0x000002E2UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain39_CddEmmBit16AXIBusECMRT2 (uint32)0x000002E3UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain39_CddEmmBit17AXIBusECMRT1 (uint32)0x000002E4UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain39_CddEmmBit18AXIBusECMRT3 (uint32)0x000002E5UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain39_CddEmmBit19AXIBusECMTOP2 (uint32)0x000002E6UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain39_CddEmmBit20AXIBusECMPER01 (uint32)0x000002E7UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain39_CddEmmBit21AXIBusECMPER02 (uint32)0x000002E8UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain39_CddEmmBit22AXIBusECMPER03 (uint32)0x000002E9UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain39_CddEmmBit23AXIBusECMTOP1 (uint32)0x000002EAUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain39_CddEmmBit24AXIBusECMTOP3 (uint32)0x000002EBUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain39_CddEmmBit25AXIBusECMVC1 (uint32)0x000002ECUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain39_CddEmmBit26AXIBusECMVIP1 (uint32)0x000002EDUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain39_CddEmmBit27AXIBusECMVIO1 (uint32)0x000002EEUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain39_CddEmmBit28AXIBusECMVIO2 (uint32)0x000002EFUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain40_CddEmmBit0CPGCBFUSAGsxFreqErr \ + (uint32)0x000002F0UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain40_CddEmmBit1CPGCBFUSARTckmrtFreqErr \ + (uint32)0x000002F1UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain40_CddEmmBit2CPGCBFUSARTckmrtFreqErr \ + (uint32)0x000002F2UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain40_CddEmmBit3CPGCBFUSAPeripheralFreqErr \ + (uint32)0x000002F3UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain40_CddEmmBit4CPGCBFUSAHscFreqErr \ + (uint32)0x000002F4UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain40_CddEmmBit5CPGCBFUSAVioFreqErr \ + (uint32)0x000002F5UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain40_CddEmmBit6CPGCBFUSAVcFreqErr \ + (uint32)0x000002F6UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain40_CddEmmBit7CPGCBFUSAVipFreqErr \ + (uint32)0x000002F7UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain40_CddEmmBit8CPGCBFUSAIMPckmirFreqErr \ + (uint32)0x000002F8UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain40_CddEmmBit9CPGIMPckmcnrFreqErr \ + (uint32)0x000002F9UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain40_CddEmmBit10CPGCBFUSAIMPckmcnrFreqErr \ + (uint32)0x000002FAUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain40_CddEmmBit11CPGCBFUSAIMPckmdspFreqErr \ + (uint32)0x000002FBUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain40_CddEmmBit12CPGCBFUSAIMPckmdspFreqErr \ + (uint32)0x000002FCUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain40_CddEmmBit13CPGLCBFUSAMMFreqErr \ + (uint32)0x000002FDUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain40_CddEmmBit14CPGLCBFUSASlAccessBusFreqErr \ + (uint32)0x000002FEUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain40_CddEmmBit18EtherTSNRxDataSRAMEDCErr \ + (uint32)0x000002FFUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain40_CddEmmBit19EtherTSNRxCtrlSRAMEDCErr \ + (uint32)0x00000300UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain40_CddEmmBit20EtherTSNTxDataSRAMEDCErr \ + (uint32)0x00000301UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain40_CddEmmBit21EtherTSNTxCtrlSRAMEDCErr \ + (uint32)0x00000302UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain40_CddEmmBit22EtherTSNTASCtrlListSRAMEDCErr \ + (uint32)0x00000303UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain40_CddEmmBit23EtherTSNPSFPCtrlListSRAMEDCErr \ + (uint32)0x00000304UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain40_CddEmmBit24EtherTSNRxDescriptionrAdrrSRAMEDCErr \ + (uint32)0x00000305UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain40_CddEmmBit25EtherTSNTxDescriptionrAdrrSRAMEDCErr \ + (uint32)0x00000306UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain40_CddEmmBit26EtherTSNTxBufferAdrrSRAMEDCErr \ + (uint32)0x00000307UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain40_CddEmmBit27EtherTSNRxEFrameBufferAdrrSRAMEDCErr \ + (uint32)0x00000308UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain40_CddEmmBit28EtherTSNRxPFrameBufferAdrrSRAMEDCErr \ + (uint32)0x00000309UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain41_CddEmmBit0PAPeccErr (uint32)0x0000030AUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain41_CddEmmBit4OTPFfDClsApbRedundantComparatorComparisonErr \ + (uint32)0x0000030BUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain41_CddEmmBit5OTPEcc1bitCorrectedErr \ + (uint32)0x0000030CUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain41_CddEmmBit6OTPEccMultibitUncorrectedErr \ + (uint32)0x0000030DUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain41_CddEmmBit7OTPTMRTripleModularRedundancy1bitCorrectedErr \ + (uint32)0x0000030EUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain41_CddEmmBit8OTPRedundantComparatorComparisonErr \ + (uint32)0x0000030FUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain41_CddEmmBit9VDSPA2arbIntreqEcm \ + (uint32)0x00000310UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain41_CddEmmBit10VDSP0ErrreqCorepmssUncorr \ + (uint32)0x00000311UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain41_CddEmmBit11VDSP0ErrreqCorepmssCorr \ + (uint32)0x00000312UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain41_CddEmmBit12VDSP0ErrreqDmssUncorr \ + (uint32)0x00000313UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain41_CddEmmBit13VDSP0ErrreqDmssCorr \ + (uint32)0x00000314UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain41_CddEmmBit14VDSP0ErrreqIrrecoverable \ + (uint32)0x00000315UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain41_CddEmmBit16VDSP0ErrreqPreciseSafetyUncorr \ + (uint32)0x00000316UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain41_CddEmmBit17VDSP0ErrreqEppWdogViol \ + (uint32)0x00000317UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain41_CddEmmBit18VDSP0ErrreqIopWdogViol \ + (uint32)0x00000318UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain41_CddEmmBit19VDSP0ErrreqEdpWdogViol \ + (uint32)0x00000319UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain41_CddEmmBit20VDSP0ErrreqAxim0WdogViol \ + (uint32)0x0000031AUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain41_CddEmmBit21VDSP0ErrreqSysWdInt \ + (uint32)0x0000031BUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain41_CddEmmBit22VDSP0ErrreqIcuWdogViol \ + (uint32)0x0000031CUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain41_CddEmmBit23VDSP1ErrreqCorepmssUncorr \ + (uint32)0x0000031DUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain41_CddEmmBit24VDSP1ErrreqCorepmssCorr \ + (uint32)0x0000031EUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain41_CddEmmBit25VDSP1ErrreqDmssUncorr \ + (uint32)0x0000031FUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain41_CddEmmBit26VDSP1ErrreqDmssCorr \ + (uint32)0x00000320UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain41_CddEmmBit27VDSP1ErrreqIrrecoverable \ + (uint32)0x00000321UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain41_CddEmmBit29VDSP1ErrreqPreciseSafetyUncorr \ + (uint32)0x00000322UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain41_CddEmmBit30VDSP1ErrreqEppWdogviol \ + (uint32)0x00000323UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain41_CddEmmBit31VDSP1ErrreqIopWdogviol \ + (uint32)0x00000324UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain42_CddEmmBit0VDSP1ErrreqEdpWdogViol \ + (uint32)0x00000325UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain42_CddEmmBit1VDSP1ErrreqAxim0WdogViol \ + (uint32)0x00000326UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain42_CddEmmBit2VDSP1ErrreqSysWdInt \ + (uint32)0x00000327UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain42_CddEmmBit3VDSP1ErrreqIcuWdogViol \ + (uint32)0x00000328UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain42_CddEmmBit4VDSP3ErrreqCorepmssUncorr \ + (uint32)0x00000329UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain42_CddEmmBit5VDSP3ErrreqCorepmssCorr \ + (uint32)0x0000032AUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain42_CddEmmBit6VDSP3ErrreqDmssUncorr \ + (uint32)0x0000032BUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain42_CddEmmBit7VDSP3ErrreqDmssCorr \ + (uint32)0x0000032CUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain42_CddEmmBit8VDSP3ErrreqIrrecoverable \ + (uint32)0x0000032DUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain42_CddEmmBit10VDSP2ErrreqPreciseSafetyUncorr \ + (uint32)0x0000032EUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain42_CddEmmBit11VDSP2ErrreqEppWdogViol \ + (uint32)0x0000032FUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain42_CddEmmBit12VDSP2ErrreqIopWdogViol \ + (uint32)0x00000330UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain42_CddEmmBit13VDSP2ErrreqEdpWdogViol \ + (uint32)0x00000331UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain42_CddEmmBit14VDSP2ErrreqAxim0WdogViol \ + (uint32)0x00000332UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain42_CddEmmBit15VDSP2ErrreqSysWdInt \ + (uint32)0x00000333UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain42_CddEmmBit16VDSP2ErrreqIcuWdogViol \ + (uint32)0x00000334UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain42_CddEmmBit17VDSP3ErrreqCorepmssUncorr \ + (uint32)0x00000335UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain42_CddEmmBit18VDSP3ErrreqCorepmssCorr \ + (uint32)0x00000336UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain42_CddEmmBit19VDSP3ErrreqDmssUncorr \ + (uint32)0x00000337UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain42_CddEmmBit20VDSP3ErrreqDmssCorr \ + (uint32)0x00000338UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain42_CddEmmBit21VDSP3ErrreqIrrecoverable \ + (uint32)0x00000339UL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain42_CddEmmBit23VDSP3ErrreqPreciseSafetyUncorr \ + (uint32)0x0000033AUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain42_CddEmmBit24VDSP3ErrreqEppWdogViol \ + (uint32)0x0000033BUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain42_CddEmmBit25VDSP3ErrreqIopWdogViol \ + (uint32)0x0000033CUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain42_CddEmmBit26VDSP3ErrreqEdpWdogViol \ + (uint32)0x0000033DUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain42_CddEmmBit27VDSP3ErrreqAxim0WdogViol \ + (uint32)0x0000033EUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain42_CddEmmBit28VDSP3ErrreqSysWdInt \ + (uint32)0x0000033FUL +/* END Msg(7:0791)-1 */ +/* MISRA Violation : START Msg(7:0791)-1 */ +#define CddEmm_CddEmmDomain42_CddEmmBit29VDSP3ErrreqIcuWdogViol \ + (uint32)0x00000340UL +/* END Msg(7:0791)-1 */ + +/* ECM Error Control Register Address */ +#define CDDEMM_ECMERRCTLR0_ADDR (uint32)0xE6250000UL +#define CDDEMM_ECMERRCTLR1_ADDR (uint32)0xE6250004UL +#define CDDEMM_ECMERRCTLR2_ADDR (uint32)0xE6250008UL +#define CDDEMM_ECMERRCTLR3_ADDR (uint32)0xE625000CUL +#define CDDEMM_ECMERRCTLR4_ADDR (uint32)0xE6250010UL +#define CDDEMM_ECMERRCTLR5_ADDR (uint32)0xE6250014UL +#define CDDEMM_ECMERRCTLR6_ADDR (uint32)0xE6250018UL +#define CDDEMM_ECMERRCTLR7_ADDR (uint32)0xE625001CUL +#define CDDEMM_ECMERRCTLR8_ADDR (uint32)0xE6250020UL +#define CDDEMM_ECMERRCTLR9_ADDR (uint32)0xE6250024UL +#define CDDEMM_ECMERRCTLR10_ADDR (uint32)0xE6250028UL +#define CDDEMM_ECMERRCTLR11_ADDR (uint32)0xE625002CUL +#define CDDEMM_ECMERRCTLR12_ADDR (uint32)0xE6250030UL +#define CDDEMM_ECMERRCTLR13_ADDR (uint32)0xE6250034UL +#define CDDEMM_ECMERRCTLR14_ADDR (uint32)0xE6250038UL +#define CDDEMM_ECMERRCTLR15_ADDR (uint32)0xE625003CUL +#define CDDEMM_ECMERRCTLR16_ADDR (uint32)0xE6250040UL +#define CDDEMM_ECMERRCTLR17_ADDR (uint32)0xE6250044UL +#define CDDEMM_ECMERRCTLR18_ADDR (uint32)0xE6250048UL +#define CDDEMM_ECMERRCTLR19_ADDR (uint32)0xE625004CUL +#define CDDEMM_ECMERRCTLR20_ADDR (uint32)0xE6250050UL +#define CDDEMM_ECMERRCTLR21_ADDR (uint32)0xE6250054UL +#define CDDEMM_ECMERRCTLR22_ADDR (uint32)0xE6250058UL +#define CDDEMM_ECMERRCTLR23_ADDR (uint32)0xE625005CUL +#define CDDEMM_ECMERRCTLR24_ADDR (uint32)0xE6250060UL +#define CDDEMM_ECMERRCTLR25_ADDR (uint32)0xE6250064UL +#define CDDEMM_ECMERRCTLR26_ADDR (uint32)0xE6250068UL +#define CDDEMM_ECMERRCTLR27_ADDR (uint32)0xE625006CUL +#define CDDEMM_ECMERRCTLR28_ADDR (uint32)0xE6250070UL +#define CDDEMM_ECMERRCTLR29_ADDR (uint32)0xE6250074UL +#define CDDEMM_ECMERRCTLR30_ADDR (uint32)0xE6250078UL +#define CDDEMM_ECMERRCTLR31_ADDR (uint32)0xE625007CUL +#define CDDEMM_ECMERRCTLR32_ADDR (uint32)0xE6250080UL +#define CDDEMM_ECMERRCTLR33_ADDR (uint32)0xE6250084UL +#define CDDEMM_ECMERRCTLR34_ADDR (uint32)0xE6250088UL +#define CDDEMM_ECMERRCTLR35_ADDR (uint32)0xE625008CUL +#define CDDEMM_ECMERRCTLR36_ADDR (uint32)0xE6250090UL +#define CDDEMM_ECMERRCTLR37_ADDR (uint32)0xE6250094UL +#define CDDEMM_ECMERRCTLR38_ADDR (uint32)0xE6250098UL +#define CDDEMM_ECMERRCTLR39_ADDR (uint32)0xE625009CUL +#define CDDEMM_ECMERRCTLR40_ADDR (uint32)0xE62500A0UL +#define CDDEMM_ECMERRCTLR41_ADDR (uint32)0xE62500A4UL +#define CDDEMM_ECMERRCTLR42_ADDR (uint32)0xE62500A8UL + +/* ECM Error Status Register Address */ +#define CDDEMM_ECMERRSTSR0_ADDR (uint32)0xE6250100UL +#define CDDEMM_ECMERRSTSR1_ADDR (uint32)0xE6250104UL +#define CDDEMM_ECMERRSTSR2_ADDR (uint32)0xE6250108UL +#define CDDEMM_ECMERRSTSR3_ADDR (uint32)0xE625010CUL +#define CDDEMM_ECMERRSTSR4_ADDR (uint32)0xE6250110UL +#define CDDEMM_ECMERRSTSR5_ADDR (uint32)0xE6250114UL +#define CDDEMM_ECMERRSTSR6_ADDR (uint32)0xE6250118UL +#define CDDEMM_ECMERRSTSR7_ADDR (uint32)0xE625011CUL +#define CDDEMM_ECMERRSTSR8_ADDR (uint32)0xE6250120UL +#define CDDEMM_ECMERRSTSR9_ADDR (uint32)0xE6250124UL +#define CDDEMM_ECMERRSTSR10_ADDR (uint32)0xE6250128UL +#define CDDEMM_ECMERRSTSR11_ADDR (uint32)0xE625012CUL +#define CDDEMM_ECMERRSTSR12_ADDR (uint32)0xE6250130UL +#define CDDEMM_ECMERRSTSR13_ADDR (uint32)0xE6250134UL +#define CDDEMM_ECMERRSTSR14_ADDR (uint32)0xE6250138UL +#define CDDEMM_ECMERRSTSR15_ADDR (uint32)0xE625013CUL +#define CDDEMM_ECMERRSTSR16_ADDR (uint32)0xE6250140UL +#define CDDEMM_ECMERRSTSR17_ADDR (uint32)0xE6250144UL +#define CDDEMM_ECMERRSTSR18_ADDR (uint32)0xE6250148UL +#define CDDEMM_ECMERRSTSR19_ADDR (uint32)0xE625014CUL +#define CDDEMM_ECMERRSTSR20_ADDR (uint32)0xE6250150UL +#define CDDEMM_ECMERRSTSR21_ADDR (uint32)0xE6250154UL +#define CDDEMM_ECMERRSTSR22_ADDR (uint32)0xE6250158UL +#define CDDEMM_ECMERRSTSR23_ADDR (uint32)0xE625015CUL +#define CDDEMM_ECMERRSTSR24_ADDR (uint32)0xE6250160UL +#define CDDEMM_ECMERRSTSR25_ADDR (uint32)0xE6250164UL +#define CDDEMM_ECMERRSTSR26_ADDR (uint32)0xE6250168UL +#define CDDEMM_ECMERRSTSR27_ADDR (uint32)0xE625016CUL +#define CDDEMM_ECMERRSTSR28_ADDR (uint32)0xE6250170UL +#define CDDEMM_ECMERRSTSR29_ADDR (uint32)0xE6250174UL +#define CDDEMM_ECMERRSTSR30_ADDR (uint32)0xE6250178UL +#define CDDEMM_ECMERRSTSR31_ADDR (uint32)0xE625017CUL +#define CDDEMM_ECMERRSTSR32_ADDR (uint32)0xE6250180UL +#define CDDEMM_ECMERRSTSR33_ADDR (uint32)0xE6250184UL +#define CDDEMM_ECMERRSTSR34_ADDR (uint32)0xE6250188UL +#define CDDEMM_ECMERRSTSR35_ADDR (uint32)0xE625018CUL +#define CDDEMM_ECMERRSTSR36_ADDR (uint32)0xE6250190UL +#define CDDEMM_ECMERRSTSR37_ADDR (uint32)0xE6250194UL +#define CDDEMM_ECMERRSTSR38_ADDR (uint32)0xE6250198UL +#define CDDEMM_ECMERRSTSR39_ADDR (uint32)0xE625019CUL +#define CDDEMM_ECMERRSTSR40_ADDR (uint32)0xE62501A0UL +#define CDDEMM_ECMERRSTSR41_ADDR (uint32)0xE62501A4UL +#define CDDEMM_ECMERRSTSR42_ADDR (uint32)0xE62501A8UL + +/* ECM Error Target Register Address */ +#define CDDEMM_ECMERRTGTR0_ADDR (uint32)0xE6250200UL +#define CDDEMM_ECMERRTGTR1_ADDR (uint32)0xE6250204UL +#define CDDEMM_ECMERRTGTR2_ADDR (uint32)0xE6250208UL +#define CDDEMM_ECMERRTGTR3_ADDR (uint32)0xE625020CUL +#define CDDEMM_ECMERRTGTR4_ADDR (uint32)0xE6250210UL +#define CDDEMM_ECMERRTGTR5_ADDR (uint32)0xE6250214UL +#define CDDEMM_ECMERRTGTR6_ADDR (uint32)0xE6250218UL +#define CDDEMM_ECMERRTGTR7_ADDR (uint32)0xE625021CUL +#define CDDEMM_ECMERRTGTR8_ADDR (uint32)0xE6250220UL +#define CDDEMM_ECMERRTGTR9_ADDR (uint32)0xE6250224UL +#define CDDEMM_ECMERRTGTR10_ADDR (uint32)0xE6250228UL +#define CDDEMM_ECMERRTGTR11_ADDR (uint32)0xE625022CUL +#define CDDEMM_ECMERRTGTR12_ADDR (uint32)0xE6250230UL +#define CDDEMM_ECMERRTGTR13_ADDR (uint32)0xE6250234UL +#define CDDEMM_ECMERRTGTR14_ADDR (uint32)0xE6250238UL +#define CDDEMM_ECMERRTGTR15_ADDR (uint32)0xE625023CUL +#define CDDEMM_ECMERRTGTR16_ADDR (uint32)0xE6250240UL +#define CDDEMM_ECMERRTGTR17_ADDR (uint32)0xE6250244UL +#define CDDEMM_ECMERRTGTR18_ADDR (uint32)0xE6250248UL +#define CDDEMM_ECMERRTGTR19_ADDR (uint32)0xE625024CUL +#define CDDEMM_ECMERRTGTR20_ADDR (uint32)0xE6250250UL +#define CDDEMM_ECMERRTGTR21_ADDR (uint32)0xE6250254UL +#define CDDEMM_ECMERRTGTR22_ADDR (uint32)0xE6250258UL +#define CDDEMM_ECMERRTGTR23_ADDR (uint32)0xE625025CUL +#define CDDEMM_ECMERRTGTR24_ADDR (uint32)0xE6250260UL +#define CDDEMM_ECMERRTGTR25_ADDR (uint32)0xE6250264UL +#define CDDEMM_ECMERRTGTR26_ADDR (uint32)0xE6250268UL +#define CDDEMM_ECMERRTGTR27_ADDR (uint32)0xE625026CUL +#define CDDEMM_ECMERRTGTR28_ADDR (uint32)0xE6250270UL +#define CDDEMM_ECMERRTGTR29_ADDR (uint32)0xE6250274UL +#define CDDEMM_ECMERRTGTR30_ADDR (uint32)0xE6250278UL +#define CDDEMM_ECMERRTGTR31_ADDR (uint32)0xE625027CUL +#define CDDEMM_ECMERRTGTR32_ADDR (uint32)0xE6250280UL +#define CDDEMM_ECMERRTGTR33_ADDR (uint32)0xE6250284UL +#define CDDEMM_ECMERRTGTR34_ADDR (uint32)0xE6250288UL +#define CDDEMM_ECMERRTGTR35_ADDR (uint32)0xE625028CUL +#define CDDEMM_ECMERRTGTR36_ADDR (uint32)0xE6250290UL +#define CDDEMM_ECMERRTGTR37_ADDR (uint32)0xE6250294UL +#define CDDEMM_ECMERRTGTR38_ADDR (uint32)0xE6250298UL +#define CDDEMM_ECMERRTGTR39_ADDR (uint32)0xE625029CUL +#define CDDEMM_ECMERRTGTR40_ADDR (uint32)0xE62502A0UL +#define CDDEMM_ECMERRTGTR41_ADDR (uint32)0xE62502A4UL +#define CDDEMM_ECMERRTGTR42_ADDR (uint32)0xE62502A8UL + +/* ECM ERROR Count Register Address */ +#define CDDEMM_ECMERRCNTR0_ADDR (uint32)0xE6250400UL +#define CDDEMM_ECMERRCNTR1_ADDR (uint32)0xE6250404UL +#define CDDEMM_ECMERRCNTR2_ADDR (uint32)0xE6250408UL +#define CDDEMM_ECMERRCNTR3_ADDR (uint32)0xE625040CUL +#define CDDEMM_ECMERRCNTR4_ADDR (uint32)0xE6250410UL +#define CDDEMM_ECMERRCNTR5_ADDR (uint32)0xE6250414UL +#define CDDEMM_ECMERRCNTR6_ADDR (uint32)0xE6250418UL +#define CDDEMM_ECMERRCNTR7_ADDR (uint32)0xE625041CUL +#define CDDEMM_ECMERRCNTR8_ADDR (uint32)0xE6250420UL +#define CDDEMM_ECMERRCNTR9_ADDR (uint32)0xE6250424UL +#define CDDEMM_ECMERRCNTR10_ADDR (uint32)0xE6250428UL +#define CDDEMM_ECMERRCNTR11_ADDR (uint32)0xE625042CUL +#define CDDEMM_ECMERRCNTR12_ADDR (uint32)0xE6250430UL +#define CDDEMM_ECMERRCNTR13_ADDR (uint32)0xE6250434UL +#define CDDEMM_ECMERRCNTR14_ADDR (uint32)0xE6250438UL +#define CDDEMM_ECMERRCNTR15_ADDR (uint32)0xE625043CUL +#define CDDEMM_ECMERRCNTR16_ADDR (uint32)0xE6250440UL +#define CDDEMM_ECMERRCNTR17_ADDR (uint32)0xE6250444UL +#define CDDEMM_ECMERRCNTR18_ADDR (uint32)0xE6250448UL +#define CDDEMM_ECMERRCNTR19_ADDR (uint32)0xE625044CUL +#define CDDEMM_ECMERRCNTR20_ADDR (uint32)0xE6250450UL +#define CDDEMM_ECMERRCNTR21_ADDR (uint32)0xE6250454UL +#define CDDEMM_ECMERRCNTR22_ADDR (uint32)0xE6250458UL +#define CDDEMM_ECMERRCNTR23_ADDR (uint32)0xE625045CUL +#define CDDEMM_ECMERRCNTR24_ADDR (uint32)0xE6250460UL +#define CDDEMM_ECMERRCNTR25_ADDR (uint32)0xE6250464UL +#define CDDEMM_ECMERRCNTR26_ADDR (uint32)0xE6250468UL +#define CDDEMM_ECMERRCNTR27_ADDR (uint32)0xE625046CUL +#define CDDEMM_ECMERRCNTR28_ADDR (uint32)0xE6250470UL +#define CDDEMM_ECMERRCNTR29_ADDR (uint32)0xE6250474UL +#define CDDEMM_ECMERRCNTR30_ADDR (uint32)0xE6250478UL +#define CDDEMM_ECMERRCNTR31_ADDR (uint32)0xE625047CUL +#define CDDEMM_ECMERRCNTR32_ADDR (uint32)0xE6250480UL +#define CDDEMM_ECMERRCNTR33_ADDR (uint32)0xE6250484UL +#define CDDEMM_ECMERRCNTR34_ADDR (uint32)0xE6250488UL +#define CDDEMM_ECMERRCNTR35_ADDR (uint32)0xE625048CUL +#define CDDEMM_ECMERRCNTR36_ADDR (uint32)0xE6250490UL +#define CDDEMM_ECMERRCNTR37_ADDR (uint32)0xE6250494UL +#define CDDEMM_ECMERRCNTR38_ADDR (uint32)0xE6250498UL +#define CDDEMM_ECMERRCNTR39_ADDR (uint32)0xE625049CUL +#define CDDEMM_ECMERRCNTR40_ADDR (uint32)0xE62504A0UL +#define CDDEMM_ECMERRCNTR41_ADDR (uint32)0xE62504A4UL +#define CDDEMM_ECMERRCNTR42_ADDR (uint32)0xE62504A8UL +#define CDDEMM_ECMERRCNTR43_ADDR (uint32)0xE62504ACUL +#define CDDEMM_ECMERRCNTR44_ADDR (uint32)0xE62504B0UL +#define CDDEMM_ECMERRCNTR45_ADDR (uint32)0xE62504B4UL +#define CDDEMM_ECMERRCNTR46_ADDR (uint32)0xE62504B8UL +#define CDDEMM_ECMERRCNTR47_ADDR (uint32)0xE62504BCUL +#define CDDEMM_ECMERRCNTR48_ADDR (uint32)0xE62504C0UL +#define CDDEMM_ECMERRCNTR49_ADDR (uint32)0xE62504C4UL +#define CDDEMM_ECMERRCNTR50_ADDR (uint32)0xE62504C8UL +#define CDDEMM_ECMERRCNTR51_ADDR (uint32)0xE62504CCUL + +/* Safety Error Insertion Control Register */ +#define CDDEMM_SAFCTLR_ADDR (uint32)0xE6250948UL + +/* Safety Error Insertion Status Register */ +#define CDDEMM_SAFSTSR_ADDR (uint32)0xE625094CUL + +/* Safety Set Error Insertion Enable Register */ +#define CDDEMM_SAFSTERRENR_ADDR (uint32)0xE6250944UL + +/* Safety Clear Error Insertion Enable Register */ +#define CDDEMM_SAFCLERRENR_ADDR (uint32)0xE6250940UL + +/* ECM Software Generate Error Interrupt Register */ +#define CDDEMM_ECMGEIIDR_ADDR (uint32)0xE6250928UL + +/* External Error Request Hold Control Register */ +#define CDDEMM_ECMEXTRQHLDCNTR_ADDR (uint32)0xE6250A10UL + +/* External Error Request Mask Control Register */ +#define CDDEMM_ECMEXTRQMSKCNTR_ADDR (uint32)0xE6250A14UL + +/* Mask value for error count 1-bit type */ +#define CDDEMM_ONE_BIT_ECMERRCNTRn_MASK 0xE0FFFFFFUL + +/* Mask value for error count multi-bit type */ +#define CDDEMM_MULTI_BIT_ECMERRCNTRn_MASK 0xFFFFE0FFUL + +/* Fill Mask value for REGSEL[5:0] bits in SAFCTLR register */ +#define CDDEMM_SAFCTLR_CLEAR 0xFFFFFFC0UL + +/* Fill Mask value of SAFCTLR register */ +#define CDDEMM_SAFCTLR_MASK 0x8000003FUL + +/* User address to save error status at Interrupt Handler */ +#define CDDEMM_DOMAIN0_USER_ADDR (uint32)0x50000000UL +#define CDDEMM_DOMAIN1_USER_ADDR (uint32)0x50000004UL +#define CDDEMM_DOMAIN2_USER_ADDR (uint32)0x50000008UL +#define CDDEMM_DOMAIN3_USER_ADDR (uint32)0x5000000CUL +#define CDDEMM_DOMAIN4_USER_ADDR (uint32)0x50000010UL +#define CDDEMM_DOMAIN5_USER_ADDR (uint32)0x50000014UL +#define CDDEMM_DOMAIN6_USER_ADDR (uint32)0x50000018UL +#define CDDEMM_DOMAIN7_USER_ADDR (uint32)0x5000001CUL +#define CDDEMM_DOMAIN8_USER_ADDR (uint32)0x50000020UL +#define CDDEMM_DOMAIN9_USER_ADDR (uint32)0x50000024UL +#define CDDEMM_DOMAIN10_USER_ADDR (uint32)0x50000028UL +#define CDDEMM_DOMAIN11_USER_ADDR (uint32)0x5000002CUL +#define CDDEMM_DOMAIN12_USER_ADDR (uint32)0x50000030UL +#define CDDEMM_DOMAIN13_USER_ADDR (uint32)0x50000034UL +#define CDDEMM_DOMAIN16_USER_ADDR (uint32)0x50000040UL +#define CDDEMM_DOMAIN17_USER_ADDR (uint32)0x50000044UL +#define CDDEMM_DOMAIN18_USER_ADDR (uint32)0x50000048UL +#define CDDEMM_DOMAIN19_USER_ADDR (uint32)0x5000004CUL +#define CDDEMM_DOMAIN20_USER_ADDR (uint32)0x50000050UL +#define CDDEMM_DOMAIN21_USER_ADDR (uint32)0x50000054UL +#define CDDEMM_DOMAIN22_USER_ADDR (uint32)0x50000058UL +#define CDDEMM_DOMAIN23_USER_ADDR (uint32)0x50000060UL +#define CDDEMM_DOMAIN24_USER_ADDR (uint32)0x50000064UL +#define CDDEMM_DOMAIN25_USER_ADDR (uint32)0x50000068UL +#define CDDEMM_DOMAIN26_USER_ADDR (uint32)0x5000006CUL +#define CDDEMM_DOMAIN27_USER_ADDR (uint32)0x50000070UL +#define CDDEMM_DOMAIN28_USER_ADDR (uint32)0x50000074UL +#define CDDEMM_DOMAIN29_USER_ADDR (uint32)0x50000078UL +#define CDDEMM_DOMAIN30_USER_ADDR (uint32)0x5000007CUL +#define CDDEMM_DOMAIN31_USER_ADDR (uint32)0x50000080UL +#define CDDEMM_DOMAIN32_USER_ADDR (uint32)0x50000084UL +#define CDDEMM_DOMAIN33_USER_ADDR (uint32)0x50000088UL +#define CDDEMM_DOMAIN34_USER_ADDR (uint32)0x5000008CUL +#define CDDEMM_DOMAIN35_USER_ADDR (uint32)0x50000090UL +#define CDDEMM_DOMAIN36_USER_ADDR (uint32)0x50000094UL +#define CDDEMM_DOMAIN38_USER_ADDR (uint32)0x5000009CUL +#define CDDEMM_DOMAIN39_USER_ADDR (uint32)0x500000A0UL +#define CDDEMM_DOMAIN40_USER_ADDR (uint32)0x500000A4UL +#define CDDEMM_DOMAIN41_USER_ADDR (uint32)0x500000A8UL +#define CDDEMM_DOMAIN42_USER_ADDR (uint32)0x500000ACUL + +#endif /* CDD_EMM_CFG_H */ + + +/******************************************************************************* +** End of File ** +*******************************************************************************/ + diff --git a/Src/Gen4_R-Car_MCAL/2_Trunk/V4H/MCAL-v4h_19.4.0.D_release/rel/modules/cddemm/sample_application/V4H/19_11/src/CDD_Emm_PBcfg.c b/Src/Gen4_R-Car_MCAL/2_Trunk/V4H/MCAL-v4h_19.4.0.D_release/rel/modules/cddemm/sample_application/V4H/19_11/src/CDD_Emm_PBcfg.c new file mode 100644 index 00000000..980e6d00 --- /dev/null +++ b/Src/Gen4_R-Car_MCAL/2_Trunk/V4H/MCAL-v4h_19.4.0.D_release/rel/modules/cddemm/sample_application/V4H/19_11/src/CDD_Emm_PBcfg.c @@ -0,0 +1,15203 @@ +/*============================================================================*/ +/* Project = AUTOSAR Renesas MCAL Components */ +/* Module = CDD_Emm_PBcfg.c */ +/*============================================================================*/ +/* COPYRIGHT */ +/*============================================================================*/ +/* Copyright(c) 2026 Renesas Electronics Corporation. */ +/*============================================================================*/ +/* Purpose: */ +/* This file contains post build parameters */ +/* AUTOMATICALLY GENERATED FILE - DO NOT EDIT */ +/* */ +/*============================================================================*/ +/* */ +/* Unless otherwise agreed upon in writing between your company and */ +/* Renesas Electronics Corporation the following shall apply! */ +/* */ +/* Warranty Disclaimer */ +/* */ +/* There is no warranty of any kind whatsoever granted by Renesas. Any */ +/* warranty is expressly disclaimed and excluded by Renesas, either expressed */ +/* or implied, including but not limited to those for non-infringement of */ +/* intellectual property, merchantability and/or fitness for the particular */ +/* purpose. */ +/* */ +/* Renesas shall not have any obligation to maintain, service or provide bug */ +/* fixes for the supplied Product(s) and/or the Application. */ +/* */ +/* Each User is solely responsible for determining the appropriateness of */ +/* using the Product(s) and assumes all risks associated with its exercise */ +/* of rights under this Agreement, including, but not limited to the risks */ +/* and costs of program errors, compliance with applicable laws, damage to */ +/* or loss of data, programs or equipment, and unavailability or */ +/* interruption of operations. */ +/* */ +/* Limitation of Liability */ +/* */ +/* In no event shall Renesas be liable to the User for any incidental, */ +/* consequential, indirect, or punitive damage (including but not limited */ +/* to lost profits) regardless of whether such liability is based on breach */ +/* of contract, tort, strict liability, breach of warranties, failure of */ +/* essential purpose or otherwise and even if advised of the possibility of */ +/* such damages. Renesas shall not be liable for any services or products */ +/* provided by third party vendors, developers or consultants identified or */ +/* referred to the User by Renesas in connection with the Product(s) and/or */ +/* the Application. */ +/* */ +/*============================================================================*/ +/* Environment: */ +/* Devices: V4H */ +/*============================================================================*/ + + +/******************************************************************************* +** Revision Control History ** +*******************************************************************************/ + + + +/******************************************************************************* +** Generation Tool Version ** +*******************************************************************************/ +/* */ +/* TOOL VERSION: CddEmmRCAR.dll version: 1.0.9, MCALConfGen.exe version: 1.2.3 */ +/* */ + + +/******************************************************************************* +** Input File ** +*******************************************************************************/ +/* + * INPUT FILE: C:\Work\Src\Gen4_R-Car_MCAL\2_Trunk\V4H\MCAL-v4h_19.4.0.D_release\rel\modules\cddemm\sample_application\V4H\19_11\config\App_CDD_EMM_V4H_Sample.arxml + * C:\Work\Src\Gen4_R-Car_MCAL\2_Trunk\V4H\MCAL-v4h_19.4.0.D_release\rel\modules\cddemm\generator\V4H\R1911_CDD_EMM_V4H_BSWMDT.arxml + * C:\Work\Src\Gen4_R-Car_MCAL\2_Trunk\V4H\MCAL-v4h_19.4.0.D_release\rel\common\generic\stubs\19_11\Dem\xml\Dem_CDD_Emm.arxml + * C:\Work\Src\Gen4_R-Car_MCAL\2_Trunk\V4H\MCAL-v4h_19.4.0.D_release\rel\V4H\common_family\generator\arm\Sample_Application_V4H.trxml + * GENERATED ON: 19 6 2026 - 05:12:32 + */ + + +/******************************************************************************* +** Instance Index ** +*******************************************************************************/ + +/******************************************************************************* +** Include Section ** +*******************************************************************************/ +/* CDD EMM Post Build configuration header */ +/* MISRA Violation : START Msg(2:0857)-7 */ +#include "CDD_Emm.h" +/* END Msg(2:0857)-7 */ +#include "CDD_Emm_Cfg.h" + + + +/******************************************************************************* +** MISRA C Rule Violations ** +*******************************************************************************/ +/******************************************************************************/ +/* 1. MISRA C RULE VIOLATION: */ +/* Message : (2:0306) [I] Cast between a pointer to object and */ +/* an integral type. */ +/* Rule : MISRA-C:2012 Rule 11.4, CWE-398, CWE-569, CWE-738 */ +/* Justification : Typecasting is done as per the register size, to access */ +/* hardware registers. */ +/* Verification : However, part of the code is verified manually and it is */ +/* not having any impact. */ +/* Reference : Look for START Msg(2:0306)-1 and */ +/* END Msg(2:0306)-1 tags in the code. */ +/******************************************************************************/ +/* 2. MISRA C RULE VIOLATION: */ +/* Message : (4:5087) Use of #include directive after code fragment. */ +/* Rule : MISRA-C:2012 Rule 20.1 */ +/* Justification : This is done as per Memory Requirement, */ +/* (MEMMAP003 - Specification of Memory Mapping). */ +/* Verification : However, part of the code is verified manually and it is */ +/* not having any impact. */ +/* Reference : Look for START Msg(4:5087)-2 and */ +/* END Msg(4:5087)-2 tags in the code. */ +/******************************************************************************/ +/* 3. MISRA C RULE VIOLATION: */ +/* Message : (2:3432) Simple macro argument expression is not */ +/* parenthesized. */ +/* Rule : MISRA C:2012 Rule-20.7, CWE-398, CWE-569 */ +/* REFERENCE - ISO:C90-6.3.1 Primary Expressions. */ +/* Justification : Compiler keyword (macro) is defined and used followed */ +/* AUTOSAR standard rule. It is accepted. */ +/* Verification : However, part of the code is verified manually */ +/* and it is not having any impact. */ +/* Reference : Look for START Msg(2:3432)-3 and */ +/* END Msg(2:3432)-3 tags in the code. */ +/******************************************************************************/ +/* 4. MISRA C RULE VIOLATION: */ +/* Message : (1:1504) The object '%1s' is only referenced in */ +/* the translation unit where it is defined. */ +/* Rule : MISRA C:2012 Rule-8.7, CWE-398, CWE-569 */ +/* Justification : This is accepted, due to following coding rule, */ +/* internal function can be defined in other C source files */ +/* Verification : However, part of the code is verified manually and it is */ +/* not having any impact. */ +/* Reference : Look for START Msg(1:1504)-4 and */ +/* END Msg(1:1504)-4 tags in the code. */ +/******************************************************************************/ +/* 5. MISRA C RULE VIOLATION: */ +/* Message : (2:0315) [I] Implicit conversion from a pointer to object */ +/* type to a pointer to void. */ +/* Rule : MISRA C:2012 Dir-1.1, CWE-188, CWE-398, CWE-569 */ +/* Justification : Typecasting is done as per the register size, to access */ +/* hardware registers. */ +/* Verification : However, part of the code is verified manually and it is */ +/* not having any impact. */ +/* Reference : Look for START Msg(2:0315)-6 and */ +/* END Msg(2:0315)-6 tags in the code. */ +/******************************************************************************/ +/* 6. MISRA C RULE VIOLATION: */ +/* Message : (2:0857) [L] Number of macro definitions exceeds 1024 */ +/* - program does not conform strictly to ISO:C90. */ +/* Rule : MISRA C:2012 Dir-1.1 */ +/* Justification : The number of macro depend on module code size. */ +/* There is no issue when number of macro is over 1024 */ +/* Verification : However, part of the code is verified manually and */ +/* it is not having any impact. */ +/* Reference : Look for START Msg(2:0857)-7 and */ +/* END Msg(2:0857)-7 tags in the code. */ +/******************************************************************************/ + + +/******************************************************************************* +** Version Information ** +*******************************************************************************/ +/* Autosar Release Version Information */ +#define CDDEMM_PBCFG_C_AR_RELEASE_MAJOR_VERSION 4U +#define CDDEMM_PBCFG_C_AR_RELEASE_MINOR_VERSION 5U +#define CDDEMM_PBCFG_C_AR_RELEASE_REVISION_VERSION 0U +/* File Version Information */ +#define CDDEMM_PBCFG_C_SW_MAJOR_VERSION 1U +#define CDDEMM_PBCFG_C_SW_MINOR_VERSION 0U + +/******************************************************************************* +** Version Check ** +*******************************************************************************/ +#if (CDDEMM_PBTYPES_AR_RELEASE_MAJOR_VERSION != \ + CDDEMM_PBCFG_C_AR_RELEASE_MAJOR_VERSION) + #error "CDD_Emm_PBcfg.c: Mismatch in Release Major Version" +#endif +#if (CDDEMM_PBTYPES_AR_RELEASE_MINOR_VERSION != \ + CDDEMM_PBCFG_C_AR_RELEASE_MINOR_VERSION) + #error "CDD_Emm_PBcfg.c: Mismatch in Release Minor Version" +#endif +#if (CDDEMM_PBTYPES_AR_RELEASE_REVISION_VERSION != \ + CDDEMM_PBCFG_C_AR_RELEASE_REVISION_VERSION) + #error "CDD_Emm_PBcfg.c: Mismatch in Release Revision Version" +#endif + +#if (CDDEMM_SW_MAJOR_VERSION != CDDEMM_PBCFG_C_SW_MAJOR_VERSION) + #error "CDD_Emm_PBcfg.c: Mismatch in Software Major Version" +#endif +#if (CDDEMM_SW_MINOR_VERSION != CDDEMM_PBCFG_C_SW_MINOR_VERSION) + #error "CDD_Emm_PBcfg.c: Mismatch in Software Minor Version" +#endif + + +/******************************************************************************* +** Global Data Types ** +*******************************************************************************/ + +/******************************************************************************* +** Global Data ** +*******************************************************************************/ +#define CDDEMM_START_SEC_CONFIG_DATA_32 +#include "CddEmm_MemMap.h" + +/* Global array for Global ConfigSet structure */ +CONST(CddEmm_ConfigType, CDDEMM_CONFIG_DATA) CddEmm_GstConfiguration[] = +{ + /* Index: 0 - 0 */ + { + /* ulStartOfDbToc */ + 0x0EFFC100UL, + + /* *pErrorRegisterInitialSetting */ + /* MISRA Violation: START Msg(2:0315)-6 */ + &CddEmm_GstErrorRegisterInitialSetting[0], + /* END Msg(2:0315)-6 */ + + /* *pErrorSignalConfig */ + /* MISRA Violation: START Msg(2:0315)-6 */ + &CddEmm_GstErrorSignalConfig[0], + /* END Msg(2:0315)-6 */ + + /* *pErrorCountInitialSetting */ + /* MISRA Violation: START Msg(2:0315)-6 */ + &CddEmm_GstErrorCountInitialSetting[0], + /* END Msg(2:0315)-6 */ + + /* ucNoOfErrorCount */ + 0x45U + } +}; + +/* Global array for error register information structure */ +/* MISRA Violation: START Msg(1:1504)-4 */ +CONST(CddEmm_ErrorRegisterInitialSettingType, CDDEMM_CONFIG_DATA) + CddEmm_GstErrorRegisterInitialSetting[CDDEMM_MAX_ERROR_REGISTER] = +{ + /* Index: 0 - CddEmmDomain0 */ + { + /* *pErrStatusRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250100UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *pErrControlRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250000UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250200UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ulErrControlVal */ + (VAR(uint32, TYPEDEF)) 0xFFFFF00FUL, + + /* *ulErrTargetVal */ + (VAR(uint32, TYPEDEF)) 0x00000000UL, + + /* *ulErrControlMask */ + (VAR(uint32, TYPEDEF)) 0xFFFFF00FUL + }, + /* Index: 1 - CddEmmDomain1 */ + { + /* *pErrStatusRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250104UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *pErrControlRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250004UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250204UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ulErrControlVal */ + (VAR(uint32, TYPEDEF)) 0xFFF8C000UL, + + /* *ulErrTargetVal */ + (VAR(uint32, TYPEDEF)) 0x00000000UL, + + /* *ulErrControlMask */ + (VAR(uint32, TYPEDEF)) 0xFFF8C000UL + }, + /* Index: 2 - CddEmmDomain2 */ + { + /* *pErrStatusRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250108UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *pErrControlRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250008UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250208UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ulErrControlVal */ + (VAR(uint32, TYPEDEF)) 0xFFFFFFFFUL, + + /* *ulErrTargetVal */ + (VAR(uint32, TYPEDEF)) 0x00000000UL, + + /* *ulErrControlMask */ + (VAR(uint32, TYPEDEF)) 0xFFFFFFFFUL + }, + /* Index: 3 - CddEmmDomain3 */ + { + /* *pErrStatusRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE625010CUL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *pErrControlRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE625000CUL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE625020CUL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ulErrControlVal */ + (VAR(uint32, TYPEDEF)) 0xFFFFFFFFUL, + + /* *ulErrTargetVal */ + (VAR(uint32, TYPEDEF)) 0x00000000UL, + + /* *ulErrControlMask */ + (VAR(uint32, TYPEDEF)) 0xFFFFFFFFUL + }, + /* Index: 4 - CddEmmDomain4 */ + { + /* *pErrStatusRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250110UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *pErrControlRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250010UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250210UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ulErrControlVal */ + (VAR(uint32, TYPEDEF)) 0xFFFFFFFFUL, + + /* *ulErrTargetVal */ + (VAR(uint32, TYPEDEF)) 0x01000000UL, + + /* *ulErrControlMask */ + (VAR(uint32, TYPEDEF)) 0xFFFFFFFFUL + }, + /* Index: 5 - CddEmmDomain5 */ + { + /* *pErrStatusRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250114UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *pErrControlRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250014UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250214UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ulErrControlVal */ + (VAR(uint32, TYPEDEF)) 0xFFFFFFFFUL, + + /* *ulErrTargetVal */ + (VAR(uint32, TYPEDEF)) 0x40000000UL, + + /* *ulErrControlMask */ + (VAR(uint32, TYPEDEF)) 0xFFFFFFFFUL + }, + /* Index: 6 - CddEmmDomain6 */ + { + /* *pErrStatusRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250118UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *pErrControlRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250018UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250218UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ulErrControlVal */ + (VAR(uint32, TYPEDEF)) 0xFF000A80UL, + + /* *ulErrTargetVal */ + (VAR(uint32, TYPEDEF)) 0x00000800UL, + + /* *ulErrControlMask */ + (VAR(uint32, TYPEDEF)) 0xFF000A80UL + }, + /* Index: 7 - CddEmmDomain7 */ + { + /* *pErrStatusRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE625011CUL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *pErrControlRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE625001CUL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE625021CUL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ulErrControlVal */ + (VAR(uint32, TYPEDEF)) 0x6F983FFFUL, + + /* *ulErrTargetVal */ + (VAR(uint32, TYPEDEF)) 0x40000000UL, + + /* *ulErrControlMask */ + (VAR(uint32, TYPEDEF)) 0x6F983FFFUL + }, + /* Index: 8 - CddEmmDomain8 */ + { + /* *pErrStatusRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250120UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *pErrControlRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250020UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250220UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ulErrControlVal */ + (VAR(uint32, TYPEDEF)) 0xFFF00000UL, + + /* *ulErrTargetVal */ + (VAR(uint32, TYPEDEF)) 0x00000000UL, + + /* *ulErrControlMask */ + (VAR(uint32, TYPEDEF)) 0xFFF00000UL + }, + /* Index: 9 - CddEmmDomain9 */ + { + /* *pErrStatusRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250124UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *pErrControlRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250024UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250224UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ulErrControlVal */ + (VAR(uint32, TYPEDEF)) 0xFF000000UL, + + /* *ulErrTargetVal */ + (VAR(uint32, TYPEDEF)) 0x00000000UL, + + /* *ulErrControlMask */ + (VAR(uint32, TYPEDEF)) 0xFF000000UL + }, + /* Index: 10 - CddEmmDomain10 */ + { + /* *pErrStatusRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250128UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *pErrControlRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250028UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250228UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ulErrControlVal */ + (VAR(uint32, TYPEDEF)) 0x557D554FUL, + + /* *ulErrTargetVal */ + (VAR(uint32, TYPEDEF)) 0x00000000UL, + + /* *ulErrControlMask */ + (VAR(uint32, TYPEDEF)) 0x557D554FUL + }, + /* Index: 11 - CddEmmDomain11 */ + { + /* *pErrStatusRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE625012CUL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *pErrControlRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE625002CUL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE625022CUL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ulErrControlVal */ + (VAR(uint32, TYPEDEF)) 0xFFFC1555UL, + + /* *ulErrTargetVal */ + (VAR(uint32, TYPEDEF)) 0x00000000UL, + + /* *ulErrControlMask */ + (VAR(uint32, TYPEDEF)) 0xFFFC1555UL + }, + /* Index: 12 - CddEmmDomain12 */ + { + /* *pErrStatusRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250130UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *pErrControlRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250030UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250230UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ulErrControlVal */ + (VAR(uint32, TYPEDEF)) 0x5557FFFFUL, + + /* *ulErrTargetVal */ + (VAR(uint32, TYPEDEF)) 0x00400000UL, + + /* *ulErrControlMask */ + (VAR(uint32, TYPEDEF)) 0x5557FFFFUL + }, + /* Index: 13 - CddEmmDomain13 */ + { + /* *pErrStatusRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250134UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *pErrControlRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250034UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250234UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ulErrControlVal */ + (VAR(uint32, TYPEDEF)) 0x00000055UL, + + /* *ulErrTargetVal */ + (VAR(uint32, TYPEDEF)) 0x00000004UL, + + /* *ulErrControlMask */ + (VAR(uint32, TYPEDEF)) 0x00000055UL + }, + /* Index: 14 - CddEmmDomain16 */ + { + /* *pErrStatusRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250140UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *pErrControlRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250040UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250240UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ulErrControlVal */ + (VAR(uint32, TYPEDEF)) 0x3FFFFFFFUL, + + /* *ulErrTargetVal */ + (VAR(uint32, TYPEDEF)) 0x00000001UL, + + /* *ulErrControlMask */ + (VAR(uint32, TYPEDEF)) 0x3FFFFFFFUL + }, + /* Index: 15 - CddEmmDomain17 */ + { + /* *pErrStatusRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250144UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *pErrControlRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250044UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250244UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ulErrControlVal */ + (VAR(uint32, TYPEDEF)) 0x2FFF8CE0UL, + + /* *ulErrTargetVal */ + (VAR(uint32, TYPEDEF)) 0x00800000UL, + + /* *ulErrControlMask */ + (VAR(uint32, TYPEDEF)) 0x2FFF8CE0UL + }, + /* Index: 16 - CddEmmDomain18 */ + { + /* *pErrStatusRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250148UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *pErrControlRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250048UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250248UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ulErrControlVal */ + (VAR(uint32, TYPEDEF)) 0x0EFC3FFFUL, + + /* *ulErrTargetVal */ + (VAR(uint32, TYPEDEF)) 0x00400000UL, + + /* *ulErrControlMask */ + (VAR(uint32, TYPEDEF)) 0x0EFC3FFFUL + }, + /* Index: 17 - CddEmmDomain19 */ + { + /* *pErrStatusRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE625014CUL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *pErrControlRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE625004CUL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE625024CUL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ulErrControlVal */ + (VAR(uint32, TYPEDEF)) 0xFFFFFFF9UL, + + /* *ulErrTargetVal */ + (VAR(uint32, TYPEDEF)) 0x00000400UL, + + /* *ulErrControlMask */ + (VAR(uint32, TYPEDEF)) 0xFFFFFFF9UL + }, + /* Index: 18 - CddEmmDomain20 */ + { + /* *pErrStatusRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250150UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *pErrControlRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250050UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250250UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ulErrControlVal */ + (VAR(uint32, TYPEDEF)) 0xFE66667EUL, + + /* *ulErrTargetVal */ + (VAR(uint32, TYPEDEF)) 0x00000040UL, + + /* *ulErrControlMask */ + (VAR(uint32, TYPEDEF)) 0xFE66667EUL + }, + /* Index: 19 - CddEmmDomain21 */ + { + /* *pErrStatusRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250154UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *pErrControlRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250054UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250254UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ulErrControlVal */ + (VAR(uint32, TYPEDEF)) 0xBFE3BE0FUL, + + /* *ulErrTargetVal */ + (VAR(uint32, TYPEDEF)) 0x00200000UL, + + /* *ulErrControlMask */ + (VAR(uint32, TYPEDEF)) 0xBFE3BE0FUL + }, + /* Index: 20 - CddEmmDomain22 */ + { + /* *pErrStatusRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250158UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *pErrControlRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250058UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250258UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ulErrControlVal */ + (VAR(uint32, TYPEDEF)) 0x10000000UL, + + /* *ulErrTargetVal */ + (VAR(uint32, TYPEDEF)) 0x10000000UL, + + /* *ulErrControlMask */ + (VAR(uint32, TYPEDEF)) 0x10000000UL + }, + /* Index: 21 - CddEmmDomain23 */ + { + /* *pErrStatusRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE625015CUL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *pErrControlRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE625005CUL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE625025CUL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ulErrControlVal */ + (VAR(uint32, TYPEDEF)) 0x7EF3C008UL, + + /* *ulErrTargetVal */ + (VAR(uint32, TYPEDEF)) 0x08000000UL, + + /* *ulErrControlMask */ + (VAR(uint32, TYPEDEF)) 0x7EF3C008UL + }, + /* Index: 22 - CddEmmDomain24 */ + { + /* *pErrStatusRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250160UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *pErrControlRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250060UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250260UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ulErrControlVal */ + (VAR(uint32, TYPEDEF)) 0x7FFE8ADBUL, + + /* *ulErrTargetVal */ + (VAR(uint32, TYPEDEF)) 0x00000040UL, + + /* *ulErrControlMask */ + (VAR(uint32, TYPEDEF)) 0x7FFE8ADBUL + }, + /* Index: 23 - CddEmmDomain25 */ + { + /* *pErrStatusRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250164UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *pErrControlRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250064UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250264UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ulErrControlVal */ + (VAR(uint32, TYPEDEF)) 0xCF807FFFUL, + + /* *ulErrTargetVal */ + (VAR(uint32, TYPEDEF)) 0x02000000UL, + + /* *ulErrControlMask */ + (VAR(uint32, TYPEDEF)) 0xCF807FFFUL + }, + /* Index: 24 - CddEmmDomain26 */ + { + /* *pErrStatusRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250168UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *pErrControlRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250068UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250268UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ulErrControlVal */ + (VAR(uint32, TYPEDEF)) 0x7EF3C008UL, + + /* *ulErrTargetVal */ + (VAR(uint32, TYPEDEF)) 0x00008000UL, + + /* *ulErrControlMask */ + (VAR(uint32, TYPEDEF)) 0x7EF3C008UL + }, + /* Index: 25 - CddEmmDomain27 */ + { + /* *pErrStatusRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE625016CUL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *pErrControlRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE625006CUL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE625026CUL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ulErrControlVal */ + (VAR(uint32, TYPEDEF)) 0x7FFE8ADBUL, + + /* *ulErrTargetVal */ + (VAR(uint32, TYPEDEF)) 0x00000010UL, + + /* *ulErrControlMask */ + (VAR(uint32, TYPEDEF)) 0x7FFE8ADBUL + }, + /* Index: 26 - CddEmmDomain28 */ + { + /* *pErrStatusRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250170UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *pErrControlRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250070UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250270UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ulErrControlVal */ + (VAR(uint32, TYPEDEF)) 0xCF807FFFUL, + + /* *ulErrTargetVal */ + (VAR(uint32, TYPEDEF)) 0x00800000UL, + + /* *ulErrControlMask */ + (VAR(uint32, TYPEDEF)) 0xCF807FFFUL + }, + /* Index: 27 - CddEmmDomain29 */ + { + /* *pErrStatusRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250174UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *pErrControlRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250074UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250274UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ulErrControlVal */ + (VAR(uint32, TYPEDEF)) 0x0073C008UL, + + /* *ulErrTargetVal */ + (VAR(uint32, TYPEDEF)) 0x00008000UL, + + /* *ulErrControlMask */ + (VAR(uint32, TYPEDEF)) 0x0073C008UL + }, + /* Index: 28 - CddEmmDomain30 */ + { + /* *pErrStatusRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250178UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *pErrControlRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250078UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250278UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ulErrControlVal */ + (VAR(uint32, TYPEDEF)) 0x7FE68A9BUL, + + /* *ulErrTargetVal */ + (VAR(uint32, TYPEDEF)) 0x00000002UL, + + /* *ulErrControlMask */ + (VAR(uint32, TYPEDEF)) 0x7FE68A9BUL + }, + /* Index: 29 - CddEmmDomain31 */ + { + /* *pErrStatusRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE625017CUL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *pErrControlRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE625007CUL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE625027CUL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ulErrControlVal */ + (VAR(uint32, TYPEDEF)) 0x8C007E00UL, + + /* *ulErrTargetVal */ + (VAR(uint32, TYPEDEF)) 0x80000000UL, + + /* *ulErrControlMask */ + (VAR(uint32, TYPEDEF)) 0x8C007E00UL + }, + /* Index: 30 - CddEmmDomain32 */ + { + /* *pErrStatusRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250180UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *pErrControlRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250080UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250280UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ulErrControlVal */ + (VAR(uint32, TYPEDEF)) 0xCFFFFFFFUL, + + /* *ulErrTargetVal */ + (VAR(uint32, TYPEDEF)) 0x80000000UL, + + /* *ulErrControlMask */ + (VAR(uint32, TYPEDEF)) 0xCFFFFFFFUL + }, + /* Index: 31 - CddEmmDomain33 */ + { + /* *pErrStatusRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250184UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *pErrControlRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250084UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250284UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ulErrControlVal */ + (VAR(uint32, TYPEDEF)) 0x0FFFFFFFUL, + + /* *ulErrTargetVal */ + (VAR(uint32, TYPEDEF)) 0x00000040UL, + + /* *ulErrControlMask */ + (VAR(uint32, TYPEDEF)) 0x0FFFFFFFUL + }, + /* Index: 32 - CddEmmDomain34 */ + { + /* *pErrStatusRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250188UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *pErrControlRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250088UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250288UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ulErrControlVal */ + (VAR(uint32, TYPEDEF)) 0x000003FFUL, + + /* *ulErrTargetVal */ + (VAR(uint32, TYPEDEF)) 0x00000200UL, + + /* *ulErrControlMask */ + (VAR(uint32, TYPEDEF)) 0x000003FFUL + }, + /* Index: 33 - CddEmmDomain35 */ + { + /* *pErrStatusRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE625018CUL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *pErrControlRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE625008CUL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE625028CUL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ulErrControlVal */ + (VAR(uint32, TYPEDEF)) 0xFFFFFFC0UL, + + /* *ulErrTargetVal */ + (VAR(uint32, TYPEDEF)) 0x08000000UL, + + /* *ulErrControlMask */ + (VAR(uint32, TYPEDEF)) 0xFFFFFFC0UL + }, + /* Index: 34 - CddEmmDomain36 */ + { + /* *pErrStatusRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250190UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *pErrControlRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250090UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250290UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ulErrControlVal */ + (VAR(uint32, TYPEDEF)) 0xFFFFFFFFUL, + + /* *ulErrTargetVal */ + (VAR(uint32, TYPEDEF)) 0x00008000UL, + + /* *ulErrControlMask */ + (VAR(uint32, TYPEDEF)) 0xFFFFFFFFUL + }, + /* Index: 35 - CddEmmDomain38 */ + { + /* *pErrStatusRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250198UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *pErrControlRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250098UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250298UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ulErrControlVal */ + (VAR(uint32, TYPEDEF)) 0xFFF000FFUL, + + /* *ulErrTargetVal */ + (VAR(uint32, TYPEDEF)) 0x00000002UL, + + /* *ulErrControlMask */ + (VAR(uint32, TYPEDEF)) 0xFFF000FFUL + }, + /* Index: 36 - CddEmmDomain39 */ + { + /* *pErrStatusRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE625019CUL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *pErrControlRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE625009CUL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE625029CUL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ulErrControlVal */ + (VAR(uint32, TYPEDEF)) 0x1FFF0000UL, + + /* *ulErrTargetVal */ + (VAR(uint32, TYPEDEF)) 0x00010000UL, + + /* *ulErrControlMask */ + (VAR(uint32, TYPEDEF)) 0x1FFF0000UL + }, + /* Index: 37 - CddEmmDomain40 */ + { + /* *pErrStatusRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE62501A0UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *pErrControlRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE62500A0UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE62502A0UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ulErrControlVal */ + (VAR(uint32, TYPEDEF)) 0x1FFC7FFFUL, + + /* *ulErrTargetVal */ + (VAR(uint32, TYPEDEF)) 0x00080000UL, + + /* *ulErrControlMask */ + (VAR(uint32, TYPEDEF)) 0xFFFC7FFFUL + }, + /* Index: 38 - CddEmmDomain41 */ + { + /* *pErrStatusRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE62501A4UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *pErrControlRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE62500A4UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE62502A4UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ulErrControlVal */ + (VAR(uint32, TYPEDEF)) 0xEFFF7FF1UL, + + /* *ulErrTargetVal */ + (VAR(uint32, TYPEDEF)) 0x02000000UL, + + /* *ulErrControlMask */ + (VAR(uint32, TYPEDEF)) 0xEFFF7FFBUL + }, + /* Index: 39 - CddEmmDomain42 */ + { + /* *pErrStatusRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE62501A8UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *pErrControlRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE62500A8UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE62502A8UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ulErrControlVal */ + (VAR(uint32, TYPEDEF)) 0x3FBFFDFFUL, + + /* *ulErrTargetVal */ + (VAR(uint32, TYPEDEF)) 0x04000000UL, + + /* *ulErrControlMask */ + (VAR(uint32, TYPEDEF)) 0x3FBFFDFFUL + } +}; +/* END Msg(1:1504)-4 */ + +/* Global array for error signal information structure */ +/* MISRA Violation: START Msg(1:1504)-4 */ +CONST(CddEmm_ErrorSignalConfigType, CDDEMM_CONFIG_DATA) + CddEmm_GstErrorSignalConfig[] = +{ + /* Index: 0 - CddEmmDomain0_CddEmmBit0DBSC5DFIDomainDCLSErrDbs0 */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250200UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 0, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 0 + }, + /* Index: 1 - CddEmmDomain0_CddEmmBit1DBSC5AXIDomainDCLSErrDbs0 */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250200UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 1, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 0 + }, + /* Index: 2 - CddEmmDomain0_CddEmmBit2DBSC5DFIDomainDCLSErrDbs1 */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250200UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 2, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 0 + }, + /* Index: 3 - CddEmmDomain0_CddEmmBit3DBSC5AXIDomainDCLSErrDbs1 */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250200UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 3, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 0 + }, + /* Index: 4 - CddEmmDomain0_CddEmmBit12SYSCIsolationCellErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250200UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 12, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 0 + }, + /* Index: 5 - CddEmmDomain0_CddEmmBit13FusesmRedundantComparitionErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250200UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 13, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 0 + }, + /* Index: 6 - CddEmmDomain0_CddEmmBit14FSFailErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250200UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 14, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 0 + }, + /* Index: 7 - CddEmmDomain0_CddEmmBit15FSTimeOutErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250200UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 15, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 0 + }, + /* Index: 8 - CddEmmDomain0_CddEmmBit16FSScanAXIbusErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250200UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 16, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 0 + }, + /* Index: 9 - CddEmmDomain0_CddEmmBit17ICUMXWdtOverFlowErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250200UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 17, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 0 + }, + /* Index: 10 - CddEmmDomain0_CddEmmBit18ICUMXBusAesOusideDmacEdcErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250200UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 18, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 0 + }, + /* Index: 11 - CddEmmDomain0_CddEmmBit19ICUMXAesDmaLockstepErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250200UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 19, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 0 + }, + /* Index: 12 - CddEmmDomain0_CddEmmBit20APSysGenericCounterOperationErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250200UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 20, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 0 + }, + /* Index: 13 - CddEmmDomain0_CddEmmBit21APSysGenericCounterComparisonErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250200UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 21, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 0 + }, + /* Index: 14 - CddEmmDomain0_CddEmmBit22SYSCWriteAcessProtectionErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250200UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 22, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 0 + }, + /* Index: 15 - CddEmmDomain0_CddEmmBit23SYSCHWRedundantErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250200UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 23, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 0 + }, + /* Index: 16 - CddEmmDomain0_CddEmmBit24BootROMMultiBitErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250200UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 24, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 0 + }, + /* Index: 17 - CddEmmDomain0_CddEmmBit25BootROMSingleBitErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250200UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 25, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 0 + }, + /* Index: 18 - CddEmmDomain0_CddEmmBit26BootROMMultiBitErr2 */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250200UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 26, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 0 + }, + /* Index: 19 - CddEmmDomain0_CddEmmBit27BootROMSingleBitErr2 */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250200UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 27, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 0 + }, + /* Index: 20 - CddEmmDomain0_CddEmmBit28BootROMAccessICUMXErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250200UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 28, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 0 + }, + /* Index: 21 - CddEmmDomain0_CddEmmBit29CPGIllegalAccessErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250200UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 29, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 0 + }, + /* Index: 22 - CddEmmDomain0_CddEmmBit30CPGFreqErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250200UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 30, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 0 + }, + /* Index: 23 - CddEmmDomain0_CddEmmBit31WriteProtectFailerReset */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250200UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 31, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 0 + }, + /* Index: 24 - CddEmmDomain1_CddEmmBit14APSysCciAceProtocolErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250204UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 14, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 1 + }, + /* Index: 25 - CddEmmDomain1_CddEmmBit15APSysCciADB400MIChkGenErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250204UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 15, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 1 + }, + /* Index: 26 - CddEmmDomain1_CddEmmBit19WWDTch6CountErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250204UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 19, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 1 + }, + /* Index: 27 - CddEmmDomain1_CddEmmBit20WWDTch5CountErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250204UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 20, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 1 + }, + /* Index: 28 - CddEmmDomain1_CddEmmBit21WWDTch4CountErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250204UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 21, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 1 + }, + /* Index: 29 - CddEmmDomain1_CddEmmBit22WWDTch3CountErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250204UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 22, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 1 + }, + /* Index: 30 - CddEmmDomain1_CddEmmBit23WWDTch2CountErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250204UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 23, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 1 + }, + /* Index: 31 - CddEmmDomain1_CddEmmBit24WWDTch1CountErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250204UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 24, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 1 + }, + /* Index: 32 - CddEmmDomain1_CddEmmBit25WWDTch0CountErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250204UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 25, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 1 + }, + /* Index: 33 - CddEmmDomain1_CddEmmBit26APSysCciAxiProtocolErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250204UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 26, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 1 + }, + /* Index: 34 - CddEmmDomain1_CddEmmBit27APSysCciSFRAMEccSedErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250204UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 27, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 1 + }, + /* Index: 35 - CddEmmDomain1_CddEmmBit28APSysCciSFRAMEccDedErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250204UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 28, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 1 + }, + /* Index: 36 - CddEmmDomain1_CddEmmBit29APSysCciDCLSCompare0Err */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250204UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 29, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 1 + }, + /* Index: 37 - CddEmmDomain1_CddEmmBit30APSysCciIrqFunctionErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250204UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 30, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 1 + }, + /* Index: 38 - CddEmmDomain1_CddEmmBit31APSysCciDCLSCompare1Err */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250204UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 31, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 1 + }, + /* Index: 39 - CddEmmDomain2_CddEmmBit0INTCtpWDTmonitorIMNTRSR0Err */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250208UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 0, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 2 + }, + /* Index: 40 - CddEmmDomain2_CddEmmBit1INTCtpWDTmonitorIMNTRSR1Err */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250208UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 1, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 2 + }, + /* Index: 41 - CddEmmDomain2_CddEmmBit2INTCtpWDTmonitorIMNTRSR2Err */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250208UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 2, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 2 + }, + /* Index: 42 - CddEmmDomain2_CddEmmBit3INTCtpWDTmonitorIMNTRSR3Err */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250208UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 3, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 2 + }, + /* Index: 43 - CddEmmDomain2_CddEmmBit4INTCtpWDTmonitorIMNTRSR4Err */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250208UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 4, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 2 + }, + /* Index: 44 - CddEmmDomain2_CddEmmBit5INTCtpWDTmonitorIMNTRSR5Err */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250208UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 5, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 2 + }, + /* Index: 45 - CddEmmDomain2_CddEmmBit6INTCtpWDTmonitorIMNTRSR6Err */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250208UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 6, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 2 + }, + /* Index: 46 - CddEmmDomain2_CddEmmBit7INTCtpWDTmonitorIMNTRSR7Err */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250208UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 7, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 2 + }, + /* Index: 47 - CddEmmDomain2_CddEmmBit8INTCtpWDTmonitorIMNTRSR8Err */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250208UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 8, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 2 + }, + /* Index: 48 - CddEmmDomain2_CddEmmBit9INTCtpWDTmonitorIMNTRSR9Err */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250208UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 9, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 2 + }, + /* Index: 49 - CddEmmDomain2_CddEmmBit10INTCtpWDTmonitorIMNTRSR10Err */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250208UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 10, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 2 + }, + /* Index: 50 - CddEmmDomain2_CddEmmBit11INTCtpWDTmonitorIMNTRSR11Err */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250208UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 11, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 2 + }, + /* Index: 51 - CddEmmDomain2_CddEmmBit12INTCtpWDTmonitorIMNTRSR12Err */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250208UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 12, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 2 + }, + /* Index: 52 - CddEmmDomain2_CddEmmBit13INTCtpWDTmonitorIMNTRSR13Err */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250208UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 13, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 2 + }, + /* Index: 53 - CddEmmDomain2_CddEmmBit14INTCtpWDTmonitorIMNTRSR14Err */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250208UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 14, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 2 + }, + /* Index: 54 - CddEmmDomain2_CddEmmBit15INTCtpWDTmonitorIMNTRSR15Err */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250208UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 15, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 2 + }, + /* Index: 55 - CddEmmDomain2_CddEmmBit16INTCtpWDTmonitorIMNTRSR16Err */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250208UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 16, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 2 + }, + /* Index: 56 - CddEmmDomain2_CddEmmBit17INTCtpWDTmonitorIMNTRSR17Err */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250208UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 17, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 2 + }, + /* Index: 57 - CddEmmDomain2_CddEmmBit18INTCtpWDTmonitorIMNTRSR18Err */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250208UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 18, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 2 + }, + /* Index: 58 - CddEmmDomain2_CddEmmBit19INTCtpWDTmonitorIMNTRSR19Err */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250208UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 19, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 2 + }, + /* Index: 59 - CddEmmDomain2_CddEmmBit20INTCtpWDTmonitorIMNTRSR20Err */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250208UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 20, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 2 + }, + /* Index: 60 - CddEmmDomain2_CddEmmBit21INTCtpWDTmonitorIMNTRSR21Err */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250208UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 21, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 2 + }, + /* Index: 61 - CddEmmDomain2_CddEmmBit22INTCtpWDTmonitorIMNTRSR22Err */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250208UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 22, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 2 + }, + /* Index: 62 - CddEmmDomain2_CddEmmBit23INTCtpWDTmonitorIMNTRSR23Err */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250208UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 23, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 2 + }, + /* Index: 63 - CddEmmDomain2_CddEmmBit24INTCtpWDTmonitorIMNTRSR24Err */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250208UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 24, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 2 + }, + /* Index: 64 - CddEmmDomain2_CddEmmBit25INTCtpWDTmonitorIMNTRSR25Err */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250208UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 25, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 2 + }, + /* Index: 65 - CddEmmDomain2_CddEmmBit26INTCtpWDTmonitorIMNTRSR26Err */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250208UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 26, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 2 + }, + /* Index: 66 - CddEmmDomain2_CddEmmBit27INTCtpWDTmonitorIMNTRSR27Err */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250208UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 27, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 2 + }, + /* Index: 67 - CddEmmDomain2_CddEmmBit28INTCtpWDTmonitorIMNTRSR28Err */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250208UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 28, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 2 + }, + /* Index: 68 - CddEmmDomain2_CddEmmBit29INTCtpWDTmonitorIMNTRSR29Err */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250208UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 29, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 2 + }, + /* Index: 69 - CddEmmDomain2_CddEmmBit30INTCtpWDTmonitorIMNTRSR30Err */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250208UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 30, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 2 + }, + /* Index: 70 - CddEmmDomain2_CddEmmBit31INTCtpWDTmonitorIMNTRSR31Err */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250208UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 31, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 2 + }, + /* Index: 71 - CddEmmDomain3_CddEmmBit0INTCtpWDTmonitorIMNTRSR32Err */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE625020CUL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 0, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 3 + }, + /* Index: 72 - CddEmmDomain3_CddEmmBit1INTCtpWDTmonitorIMNTRSR33Err */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE625020CUL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 1, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 3 + }, + /* Index: 73 - CddEmmDomain3_CddEmmBit2INTCtpWDTmonitorIMNTRSR34Err */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE625020CUL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 2, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 3 + }, + /* Index: 74 - CddEmmDomain3_CddEmmBit3INTCtpWDTmonitorIMNTRSR35Err */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE625020CUL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 3, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 3 + }, + /* Index: 75 - CddEmmDomain3_CddEmmBit4INTCtpWDTmonitorIMNTRSR36Err */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE625020CUL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 4, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 3 + }, + /* Index: 76 - CddEmmDomain3_CddEmmBit5INTCtpWDTmonitorIMNTRSR37Err */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE625020CUL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 5, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 3 + }, + /* Index: 77 - CddEmmDomain3_CddEmmBit6INTCtpWDTmonitorIMNTRSR38Err */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE625020CUL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 6, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 3 + }, + /* Index: 78 - CddEmmDomain3_CddEmmBit7INTCtpWDTmonitorIMNTRSR39Err */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE625020CUL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 7, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 3 + }, + /* Index: 79 - CddEmmDomain3_CddEmmBit8INTCtpWDTmonitorIMNTRSR40Err */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE625020CUL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 8, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 3 + }, + /* Index: 80 - CddEmmDomain3_CddEmmBit9INTCtpWDTmonitorIMNTRSR41Err */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE625020CUL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 9, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 3 + }, + /* Index: 81 - CddEmmDomain3_CddEmmBit10INTCtpWDTmonitorIMNTRSR42Err */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE625020CUL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 10, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 3 + }, + /* Index: 82 - CddEmmDomain3_CddEmmBit11INTCtpWDTmonitorIMNTRSR43Err */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE625020CUL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 11, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 3 + }, + /* Index: 83 - CddEmmDomain3_CddEmmBit12INTCtpWDTmonitorIMNTRSR44Err */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE625020CUL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 12, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 3 + }, + /* Index: 84 - CddEmmDomain3_CddEmmBit13INTCtpWDTmonitorIMNTRSR45Err */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE625020CUL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 13, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 3 + }, + /* Index: 85 - CddEmmDomain3_CddEmmBit14INTCtpWDTmonitorIMNTRSR46Err */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE625020CUL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 14, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 3 + }, + /* Index: 86 - CddEmmDomain3_CddEmmBit15INTCtpWDTmonitorIMNTRSR47Err */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE625020CUL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 15, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 3 + }, + /* Index: 87 - CddEmmDomain3_CddEmmBit16INTCtpWDTmonitorIMNTRSR48Err */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE625020CUL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 16, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 3 + }, + /* Index: 88 - CddEmmDomain3_CddEmmBit17INTCtpWDTmonitorIMNTRSR49Err */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE625020CUL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 17, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 3 + }, + /* Index: 89 - CddEmmDomain3_CddEmmBit18INTCtpWDTmonitorIMNTRSR50Err */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE625020CUL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 18, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 3 + }, + /* Index: 90 - CddEmmDomain3_CddEmmBit19INTCtpWDTmonitorIMNTRSR51Err */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE625020CUL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 19, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 3 + }, + /* Index: 91 - CddEmmDomain3_CddEmmBit20INTCtpWDTmonitorIMNTRSR52Err */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE625020CUL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 20, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 3 + }, + /* Index: 92 - CddEmmDomain3_CddEmmBit21INTCtpWDTmonitorIMNTRSR53Err */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE625020CUL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 21, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 3 + }, + /* Index: 93 - CddEmmDomain3_CddEmmBit22INTCtpWDTmonitorIMNTRSR54Err */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE625020CUL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 22, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 3 + }, + /* Index: 94 - CddEmmDomain3_CddEmmBit23INTCtpWDTmonitorIMNTRSR55Err */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE625020CUL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 23, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 3 + }, + /* Index: 95 - CddEmmDomain3_CddEmmBit24INTCtpWDTmonitorIMNTRSR56Err */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE625020CUL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 24, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 3 + }, + /* Index: 96 - CddEmmDomain3_CddEmmBit25INTCtpWDTmonitorIMNTRSR57Err */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE625020CUL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 25, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 3 + }, + /* Index: 97 - CddEmmDomain3_CddEmmBit26INTCtpWDTmonitorIMNTRSR58Err */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE625020CUL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 26, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 3 + }, + /* Index: 98 - CddEmmDomain3_CddEmmBit27INTCtpWDTmonitorIMNTRSR59Err */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE625020CUL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 27, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 3 + }, + /* Index: 99 - CddEmmDomain3_CddEmmBit28INTCtpWDTmonitorIMNTRSR60Err */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE625020CUL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 28, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 3 + }, + /* Index: 100 - CddEmmDomain3_CddEmmBit29INTCtpWDTmonitorIMNTRSR61Err */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE625020CUL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 29, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 3 + }, + /* Index: 101 - CddEmmDomain3_CddEmmBit30INTCtpWDTmonitorIMNTRSR62Err */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE625020CUL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 30, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 3 + }, + /* Index: 102 - CddEmmDomain3_CddEmmBit31INTCtpWDTmonitorIMNTRSR63Err */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE625020CUL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 31, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 3 + }, + /* Index: 103 - CddEmmDomain4_CddEmmBit0INTCtpWDTmonitorIMNTRSR64Err */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250210UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 0, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 4 + }, + /* Index: 104 - CddEmmDomain4_CddEmmBit1INTCtpWDTmonitorIMNTRSR65Err */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250210UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 1, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 4 + }, + /* Index: 105 - CddEmmDomain4_CddEmmBit2INTCtpWDTmonitorIMNTRSR66Err */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250210UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 2, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 4 + }, + /* Index: 106 - CddEmmDomain4_CddEmmBit3INTCtpWDTmonitorIMNTRSR67Err */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250210UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 3, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 4 + }, + /* Index: 107 - CddEmmDomain4_CddEmmBit4INTCtpWDTmonitorIMNTRSR68Err */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250210UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 4, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 4 + }, + /* Index: 108 - CddEmmDomain4_CddEmmBit5INTCtpWDTmonitorIMNTRSR69Err */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250210UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 5, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 4 + }, + /* Index: 109 - CddEmmDomain4_CddEmmBit6INTCtpWDTmonitorIMNTRSR70Err */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250210UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 6, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 4 + }, + /* Index: 110 - CddEmmDomain4_CddEmmBit7INTCtpWDTmonitorIMNTRSR71Err */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250210UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 7, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 4 + }, + /* Index: 111 - CddEmmDomain4_CddEmmBit8INTCtpWDTmonitorIMNTRSR72Err */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250210UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 8, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 4 + }, + /* Index: 112 - CddEmmDomain4_CddEmmBit9INTCtpWDTmonitorIMNTRSR73Err */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250210UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 9, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 4 + }, + /* Index: 113 - CddEmmDomain4_CddEmmBit10INTCtpWDTmonitorIMNTRSR74Err */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250210UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 10, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 4 + }, + /* Index: 114 - CddEmmDomain4_CddEmmBit11INTCtpWDTmonitorIMNTRSR75Err */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250210UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 11, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 4 + }, + /* Index: 115 - CddEmmDomain4_CddEmmBit12INTCtpWDTmonitorIMNTRSR76Err */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250210UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 12, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 4 + }, + /* Index: 116 - CddEmmDomain4_CddEmmBit13INTCtpWDTmonitorIMNTRSR77Err */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250210UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 13, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 4 + }, + /* Index: 117 - CddEmmDomain4_CddEmmBit14INTCtpWDTmonitorIMNTRSR78Err */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250210UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 14, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 4 + }, + /* Index: 118 - CddEmmDomain4_CddEmmBit15INTCtpWDTmonitorIMNTRSR79Err */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250210UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 15, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 4 + }, + /* Index: 119 - CddEmmDomain4_CddEmmBit16INTCtpWDTmonitorIMNTRSR80Err */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250210UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 16, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 4 + }, + /* Index: 120 - CddEmmDomain4_CddEmmBit17INTCtpWDTmonitorIMNTRSR81Err */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250210UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 17, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 4 + }, + /* Index: 121 - CddEmmDomain4_CddEmmBit18INTCtpWDTmonitorIMNTRSR82Err */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250210UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 18, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 4 + }, + /* Index: 122 - CddEmmDomain4_CddEmmBit19INTCtpWDTmonitorIMNTRSR83Err */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250210UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 19, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 4 + }, + /* Index: 123 - CddEmmDomain4_CddEmmBit20INTCtpWDTmonitorIMNTRSR84Err */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250210UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 20, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 4 + }, + /* Index: 124 - CddEmmDomain4_CddEmmBit21INTCtpWDTmonitorIMNTRSR85Err */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250210UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 21, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 4 + }, + /* Index: 125 - CddEmmDomain4_CddEmmBit22INTCtpWDTmonitorIMNTRSR86Err */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250210UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 22, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 4 + }, + /* Index: 126 - CddEmmDomain4_CddEmmBit23INTCtpWDTmonitorIMNTRSR87Err */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250210UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 23, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 4 + }, + /* Index: 127 - CddEmmDomain4_CddEmmBit24INTCtpWDTmonitorIMNTRSR88Err */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250210UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 24, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 4 + }, + /* Index: 128 - CddEmmDomain4_CddEmmBit25INTCtpWDTmonitorIMNTRSR89Err */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250210UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 25, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 4 + }, + /* Index: 129 - CddEmmDomain4_CddEmmBit26INTCtpWDTmonitorIMNTRSR90Err */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250210UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 26, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 4 + }, + /* Index: 130 - CddEmmDomain4_CddEmmBit27INTCtpWDTmonitorIMNTRSR91Err */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250210UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 27, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 4 + }, + /* Index: 131 - CddEmmDomain4_CddEmmBit28INTCtpWDTmonitorIMNTRSR92Err */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250210UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 28, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 4 + }, + /* Index: 132 - CddEmmDomain4_CddEmmBit29INTCtpWDTmonitorIMNTRSR93Err */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250210UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 29, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 4 + }, + /* Index: 133 - CddEmmDomain4_CddEmmBit30INTCtpWDTmonitorIMNTRSR94Err */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250210UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 30, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 4 + }, + /* Index: 134 - CddEmmDomain4_CddEmmBit31INTCtpWDTmonitorIMNTRSR95Err */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250210UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 31, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 4 + }, + /* Index: 135 - CddEmmDomain5_CddEmmBit0INTCtpWDTmonitorIMNTRSR96Err */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250214UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 0, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 5 + }, + /* Index: 136 - CddEmmDomain5_CddEmmBit1INTCtpWDTmonitorIMNTRSR97Err */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250214UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 1, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 5 + }, + /* Index: 137 - CddEmmDomain5_CddEmmBit2INTCtpWDTmonitorIMNTRSR98Err */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250214UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 2, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 5 + }, + /* Index: 138 - CddEmmDomain5_CddEmmBit3INTCtpWDTmonitorIMNTRSR99Err */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250214UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 3, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 5 + }, + /* Index: 139 - CddEmmDomain5_CddEmmBit4INTCtpWDTmonitorIMNTRSR100Err */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250214UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 4, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 5 + }, + /* Index: 140 - CddEmmDomain5_CddEmmBit5INTCtpWDTmonitorIMNTRSR101Err */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250214UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 5, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 5 + }, + /* Index: 141 - CddEmmDomain5_CddEmmBit6INTCtpWDTmonitorIMNTRSR102Err */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250214UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 6, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 5 + }, + /* Index: 142 - CddEmmDomain5_CddEmmBit7INTCtpWDTmonitorIMNTRSR103Err */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250214UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 7, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 5 + }, + /* Index: 143 - CddEmmDomain5_CddEmmBit8INTCtpWDTmonitorIMNTRSR104Err */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250214UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 8, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 5 + }, + /* Index: 144 - CddEmmDomain5_CddEmmBit9INTCtpWDTmonitorIMNTRSR105Err */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250214UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 9, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 5 + }, + /* Index: 145 - CddEmmDomain5_CddEmmBit10INTCtpWDTmonitorIMNTRSR106Err */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250214UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 10, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 5 + }, + /* Index: 146 - CddEmmDomain5_CddEmmBit11INTCtpWDTmonitorIMNTRSR107Err */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250214UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 11, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 5 + }, + /* Index: 147 - CddEmmDomain5_CddEmmBit12INTCtpWDTmonitorIMNTRSR108Err */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250214UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 12, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 5 + }, + /* Index: 148 - CddEmmDomain5_CddEmmBit13INTCtpWDTmonitorIMNTRSR109Err */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250214UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 13, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 5 + }, + /* Index: 149 - CddEmmDomain5_CddEmmBit14INTCtpWDTmonitorIMNTRSR110Err */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250214UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 14, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 5 + }, + /* Index: 150 - CddEmmDomain5_CddEmmBit15INTCtpWDTmonitorIMNTRSR111Err */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250214UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 15, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 5 + }, + /* Index: 151 - CddEmmDomain5_CddEmmBit16INTCtpWDTmonitorIMNTRSR112Err */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250214UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 16, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 5 + }, + /* Index: 152 - CddEmmDomain5_CddEmmBit17INTCtpWDTmonitorIMNTRSR113Err */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250214UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 17, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 5 + }, + /* Index: 153 - CddEmmDomain5_CddEmmBit18INTCtpWDTmonitorIMNTRSR114Err */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250214UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 18, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 5 + }, + /* Index: 154 - CddEmmDomain5_CddEmmBit19INTCtpWDTmonitorIMNTRSR115Err */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250214UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 19, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 5 + }, + /* Index: 155 - CddEmmDomain5_CddEmmBit20INTCtpWDTmonitorIMNTRSR116Err */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250214UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 20, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 5 + }, + /* Index: 156 - CddEmmDomain5_CddEmmBit21INTCtpWDTmonitorIMNTRSR117Err */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250214UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 21, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 5 + }, + /* Index: 157 - CddEmmDomain5_CddEmmBit22INTCtpWDTmonitorIMNTRSR118Err */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250214UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 22, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 5 + }, + /* Index: 158 - CddEmmDomain5_CddEmmBit23INTCtpWDTmonitorIMNTRSR119Err */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250214UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 23, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 5 + }, + /* Index: 159 - CddEmmDomain5_CddEmmBit24INTCtpWDTmonitorIMNTRSR120Err */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250214UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 24, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 5 + }, + /* Index: 160 - CddEmmDomain5_CddEmmBit25RTCore0EL1controlledMemoryAccessErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250214UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 25, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 5 + }, + /* Index: 161 - CddEmmDomain5_CddEmmBit26RTCoreProcessorLivelockErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250214UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 26, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 5 + }, + /* Index: 162 - CddEmmDomain5_CddEmmBit27RTCore0SWRunInEL2UnlockTESTR1Err */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250214UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 27, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 5 + }, + /* Index: 163 - CddEmmDomain5_CddEmmBit28INTCtpEDCAXI4stream3 */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250214UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 28, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 5 + }, + /* Index: 164 - CddEmmDomain5_CddEmmBit29INTCtpEDCAXI4stream2 */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250214UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 29, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 5 + }, + /* Index: 165 - CddEmmDomain5_CddEmmBit30INTCtpEDCAXI4stream1 */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250214UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 30, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 5 + }, + /* Index: 166 - CddEmmDomain5_CddEmmBit31INTCtpEDCAXI4stream0 */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250214UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 31, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 5 + }, + /* Index: 167 - CddEmmDomain6_CddEmmBit7VIPInternalDOFErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250218UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 7, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 6 + }, + /* Index: 168 - CddEmmDomain6_CddEmmBit9VIPInternalSMPSErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250218UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 9, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 6 + }, + /* Index: 169 - CddEmmDomain6_CddEmmBit11VIPInternalSMPOErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250218UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 11, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 6 + }, + /* Index: 170 - CddEmmDomain6_CddEmmBit24IMPX7SRAMEDCErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250218UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 24, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 6 + }, + /* Index: 171 - CddEmmDomain6_CddEmmBit25IMPX7SRAMECCErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250218UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 25, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 6 + }, + /* Index: 172 - CddEmmDomain6_CddEmmBit26IMPX7BusErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250218UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 26, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 6 + }, + /* Index: 173 - CddEmmDomain6_CddEmmBit27IMPX7ScratchpadMemoryDCLSErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250218UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 27, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 6 + }, + /* Index: 174 - CddEmmDomain6_CddEmmBit28APMUCortexR52Core0ResetControlErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250218UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 28, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 6 + }, + /* Index: 175 - CddEmmDomain6_CddEmmBit29APMUAccessProtectErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250218UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 29, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 6 + }, + /* Index: 176 - CddEmmDomain6_CddEmmBit30APMUDCLSErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250218UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 30, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 6 + }, + /* Index: 177 - CddEmmDomain6_CddEmmBit31MFISCheckerCoreComparisonErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250218UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 31, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 6 + }, + /* Index: 178 - CddEmmDomain7_CddEmmBit0INTCapFaultHandlingInterrupt */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE625021CUL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 0, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 7 + }, + /* Index: 179 - CddEmmDomain7_CddEmmBit1INTCapErrorHandlingInterrupt */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE625021CUL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 1, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 7 + }, + /* Index: 180 - CddEmmDomain7_CddEmmBit2AXIBusECMVIP0 */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE625021CUL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 2, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 7 + }, + /* Index: 181 - CddEmmDomain7_CddEmmBit3AXIBusECMVIO0 */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE625021CUL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 3, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 7 + }, + /* Index: 182 - CddEmmDomain7_CddEmmBit4AXIBusECMVC0 */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE625021CUL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 4, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 7 + }, + /* Index: 183 - CddEmmDomain7_CddEmmBit5AXIBusECM3DG */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE625021CUL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 5, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 7 + }, + /* Index: 184 - CddEmmDomain7_CddEmmBit6AXIBusECMTOP0 */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE625021CUL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 6, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 7 + }, + /* Index: 185 - CddEmmDomain7_CddEmmBit7AXIBusECMRT0 */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE625021CUL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 7, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 7 + }, + /* Index: 186 - CddEmmDomain7_CddEmmBit8AXIBusECMHSC */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE625021CUL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 8, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 7 + }, + /* Index: 187 - CddEmmDomain7_CddEmmBit9AXIBusECMPER00 */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE625021CUL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 9, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 7 + }, + /* Index: 188 - CddEmmDomain7_CddEmmBit10AXIBusECMMM */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE625021CUL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 10, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 7 + }, + /* Index: 189 - CddEmmDomain7_CddEmmBit11AXIBusECMIMP */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE625021CUL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 11, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 7 + }, + /* Index: 190 - CddEmmDomain7_CddEmmBit12VSP2VSPX0InternalSRAMEDCWDTErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE625021CUL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 12, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 7 + }, + /* Index: 191 - CddEmmDomain7_CddEmmBit13VSP2VSPX1InternalSRAMEDCWDTErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE625021CUL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 13, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 7 + }, + /* Index: 192 - CddEmmDomain7_CddEmmBit19RTVRAM0SafetyAccessProtectionErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE625021CUL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 19, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 7 + }, + /* Index: 193 - CddEmmDomain7_CddEmmBit20RTVRAM0SecureAccessProtectionErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE625021CUL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 20, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 7 + }, + /* Index: 194 - CddEmmDomain7_CddEmmBit23RTVRAM0TimeoutErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE625021CUL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 23, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 7 + }, + /* Index: 195 - CddEmmDomain7_CddEmmBit24INTCapCA76Core3RequestOrderErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE625021CUL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 24, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 7 + }, + /* Index: 196 - CddEmmDomain7_CddEmmBit25INTCapCA76Core2RequestOrderErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE625021CUL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 25, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 7 + }, + /* Index: 197 - CddEmmDomain7_CddEmmBit26INTCapCA76Core1RequestOrderErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE625021CUL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 26, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 7 + }, + /* Index: 198 - CddEmmDomain7_CddEmmBit27INTCapCA76Core0RequestOrderErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE625021CUL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 27, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 7 + }, + /* Index: 199 - CddEmmDomain7_CddEmmBit29RTVRAM0EdcMultibitErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE625021CUL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 29, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 7 + }, + /* Index: 200 - CddEmmDomain7_CddEmmBit30RTVRAM0Edc1bitErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE625021CUL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 30, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 7 + }, + /* Index: 201 - CddEmmDomain8_CddEmmBit20DSItxlink1EdcErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250220UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 20, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 8 + }, + /* Index: 202 - CddEmmDomain8_CddEmmBit21DSItxlink0EdcErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250220UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 21, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 8 + }, + /* Index: 203 - CddEmmDomain8_CddEmmBit22APSysCciTransactionOrderCheckMI2Err */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250220UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 22, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 8 + }, + /* Index: 204 - CddEmmDomain8_CddEmmBit23APSysCciTransactionOrderCheckMI1Err */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250220UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 23, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 8 + }, + /* Index: 205 - CddEmmDomain8_CddEmmBit24FCPCSInternalSRAMEdcErrr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250220UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 24, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 8 + }, + /* Index: 206 - CddEmmDomain8_CddEmmBit25VCPL4CEInternalSRAMEdcErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250220UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 25, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 8 + }, + /* Index: 207 - CddEmmDomain8_CddEmmBit26VCPL4VLCInternalSRAMEdcErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250220UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 26, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 8 + }, + /* Index: 208 - CddEmmDomain8_CddEmmBit27VSP2VSPD1DISCOMUnmatchedWdtErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250220UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 27, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 8 + }, + /* Index: 209 - CddEmmDomain8_CddEmmBit28VSP2VSPD1DISCOMFrozenErrWdt */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250220UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 28, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 8 + }, + /* Index: 210 - CddEmmDomain8_CddEmmBit29VSP2VSPD0DISCOMUnmatchedWdtErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250220UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 29, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 8 + }, + /* Index: 211 - CddEmmDomain8_CddEmmBit30VSP2VSPD0DISCOMFrozenErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250220UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 30, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 8 + }, + /* Index: 212 - CddEmmDomain8_CddEmmBit31DSCEdcErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250220UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 31, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 8 + }, + /* Index: 213 - CddEmmDomain9_CddEmmBit24ECMSwGenID0Err */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250224UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 24, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 9 + }, + /* Index: 214 - CddEmmDomain9_CddEmmBit25ECMSwGenID1Err */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250224UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 25, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 9 + }, + /* Index: 215 - CddEmmDomain9_CddEmmBit26ECMSwGenID2Err */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250224UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 26, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 9 + }, + /* Index: 216 - CddEmmDomain9_CddEmmBit27ECMSwGenID3Err */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250224UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 27, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 9 + }, + /* Index: 217 - CddEmmDomain9_CddEmmBit28ECMSwGenID4Err */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250224UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 28, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 9 + }, + /* Index: 218 - CddEmmDomain9_CddEmmBit29ECMSwGenID5Err */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250224UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 29, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 9 + }, + /* Index: 219 - CddEmmDomain9_CddEmmBit30ECMSwGenID6Err */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250224UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 30, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 9 + }, + /* Index: 220 - CddEmmDomain9_CddEmmBit31ECMSwGenID7Err */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250224UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 31, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 9 + }, + /* Index: 221 - CddEmmDomain10_CddEmmBit0APSysCciEccSedErrCounter */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250228UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 0, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 10 + }, + /* Index: 222 - CddEmmDomain10_CddEmmBit1APSysCciEccEdcErrCounter */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250228UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 1, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 10 + }, + /* Index: 223 - CddEmmDomain10_CddEmmBit2RTVRAMRTVRAM0Edc1bitErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250228UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 2, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 10 + }, + /* Index: 224 - CddEmmDomain10_CddEmmBit3RTVRAMRTVRAM0EdcMulbitErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250228UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 3, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 10 + }, + /* Index: 225 - CddEmmDomain10_CddEmmBit6RTCore0TCMCorrectableErrCounter */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250228UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 6, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 10 + }, + /* Index: 226 - CddEmmDomain10_CddEmmBit8RTCore0InstructionCacheErrCounter */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250228UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 8, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 10 + }, + /* Index: 227 - CddEmmDomain10_CddEmmBit10RTCore0DataCacheErrCounter */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250228UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 10, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 10 + }, + /* Index: 228 - CddEmmDomain10_CddEmmBit12RTCore0AXISICorrectableErrCounter */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250228UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 12, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 10 + }, + /* Index: 229 - CddEmmDomain10_CddEmmBit14RTCore0AXIMICorrectableErrCounter */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250228UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 14, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 10 + }, + /* Index: 230 - CddEmmDomain10_CddEmmBit16RTCore0ErrCounter */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250228UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 16, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 10 + }, + /* Index: 231 - CddEmmDomain10_CddEmmBit18RTVRAM1Edc1bitCountupErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250228UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 18, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 10 + }, + /* Index: 232 - CddEmmDomain10_CddEmmBit19RTVRAM1EdcMulbitErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250228UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 19, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 10 + }, + /* Index: 233 - CddEmmDomain10_CddEmmBit20IPMMUmmTLBRAMEdc1bitCountupErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250228UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 20, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 10 + }, + /* Index: 234 - CddEmmDomain10_CddEmmBit21IPMMUmmTLBRAMEdcMultibitCountupErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250228UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 21, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 10 + }, + /* Index: 235 - CddEmmDomain10_CddEmmBit22RTCore1AXIMICorrectableErrCounter */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250228UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 22, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 10 + }, + /* Index: 236 - CddEmmDomain10_CddEmmBit24RTCore1AXISICorrectableErrCounter */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250228UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 24, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 10 + }, + /* Index: 237 - CddEmmDomain10_CddEmmBit26RTCore1DataCacheErrCounter */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250228UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 26, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 10 + }, + /* Index: 238 - CddEmmDomain10_CddEmmBit28RTCore1InstructionCacheErrCounter */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250228UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 28, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 10 + }, + /* Index: 239 - CddEmmDomain10_CddEmmBit30RTCore1ErrCounter */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250228UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 30, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 10 + }, + /* Index: 240 - CddEmmDomain11_CddEmmBit0RTCore1TCMCorrectableErrCounter */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE625022CUL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 0, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 11 + }, + /* Index: 241 - CddEmmDomain11_CddEmmBit2RTCore2AXIMICorrectableErrCounter */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE625022CUL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 2, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 11 + }, + /* Index: 242 - CddEmmDomain11_CddEmmBit4RTCore2AXISICorrectableErrCounter */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE625022CUL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 4, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 11 + }, + /* Index: 243 - CddEmmDomain11_CddEmmBit6RTCore2DataCacheErrCounter */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE625022CUL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 6, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 11 + }, + /* Index: 244 - CddEmmDomain11_CddEmmBit8RTCore2InstructionCacheErrCounter */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE625022CUL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 8, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 11 + }, + /* Index: 245 - CddEmmDomain11_CddEmmBit10RTCore2ErrCounter */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE625022CUL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 10, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 11 + }, + /* Index: 246 - CddEmmDomain11_CddEmmBit12RTCore2TCMCorrectableErrCounter */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE625022CUL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 12, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 11 + }, + /* Index: 247 - */ +/* CddEmmDomain11_CddEmmBit18APSysCA76Core3L1IL1DL2MmuCorrectedErrCounter */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE625022CUL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 18, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 11 + }, + /* Index: 248 - */ +/* CddEmmDomain11_CddEmmBit19APSysCA76Core3L1IL1DL2MmuUncorrectedErrCounter */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE625022CUL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 19, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 11 + }, + /* Index: 249 - */ +/* CddEmmDomain11_CddEmmBit20APSysCA76Core2L1IL1DL2MmuCorrectedErrCounter */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE625022CUL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 20, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 11 + }, + /* Index: 250 - */ +/* CddEmmDomain11_CddEmmBit21APSysCA76Core2L1IL1DL2MmuUncorrectedErrCounter */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE625022CUL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 21, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 11 + }, + /* Index: 251 - CddEmmDomain11_CddEmmBit22APSysL3Cl1CorrectedErrCounter */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE625022CUL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 22, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 11 + }, + /* Index: 252 - CddEmmDomain11_CddEmmBit23APSysL3Cl1UnCorrectedErrCounter */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE625022CUL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 23, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 11 + }, + /* Index: 253 - */ +/* CddEmmDomain11_CddEmmBit24APSysCA76Core1L1IL1DL2MmuCorrectedErrCounter */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE625022CUL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 24, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 11 + }, + /* Index: 254 - */ +/* CddEmmDomain11_CddEmmBit25APSysCA76Core1L1IL1DL2MmuUncorrectedErrCounter */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE625022CUL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 25, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 11 + }, + /* Index: 255 - */ +/* CddEmmDomain11_CddEmmBit26APSysCA76Core0L1IL1DL2MmuCorrectedErrCounter */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE625022CUL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 26, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 11 + }, + /* Index: 256 - */ +/* CddEmmDomain11_CddEmmBit27APSysCA76Core0L1IL1DL2MmuUncorrectedErrCounter */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE625022CUL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 27, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 11 + }, + /* Index: 257 - CddEmmDomain11_CddEmmBit28APSysL3Cl0correctedErrCounter */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE625022CUL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 28, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 11 + }, + /* Index: 258 - CddEmmDomain11_CddEmmBit29APSysL3Cl0UncorrectedErrCounter */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE625022CUL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 29, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 11 + }, + /* Index: 259 - CddEmmDomain11_CddEmmBit30CANFDRAMEcc1bitErrCounter */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE625022CUL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 30, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 11 + }, + /* Index: 260 - CddEmmDomain11_CddEmmBit31CANFDRAMEcc2bitErrCounter */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE625022CUL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 31, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 11 + }, + /* Index: 261 - */ +/* CddEmmDomain12_CddEmmBit0FLEXRAYTBF2InterruptNotificationEccErrCounter */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250230UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 0, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 12 + }, + /* Index: 262 - */ +/* CddEmmDomain12_CddEmmBit1FLEXRAYTBF2InterruptNotificationEdcErrCounter */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250230UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 1, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 12 + }, + /* Index: 263 - */ +/* CddEmmDomain12_CddEmmBit2FLEXRAYTBF1InterruptNotificationEccErrCounter */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250230UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 2, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 12 + }, + /* Index: 264 - */ +/* CddEmmDomain12_CddEmmBit3FLEXRAYTBF1InterruptNotificationEdcErrCounter */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250230UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 3, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 12 + }, + /* Index: 265 - */ +/* CddEmmDomain12_CddEmmBit4FLEXRAYMBFInterruptNotificationEccErrCounter */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250230UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 4, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 12 + }, + /* Index: 266 - */ +/* CddEmmDomain12_CddEmmBit5FLEXRAYMBFInterruptNotificationEdcErrCounter */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250230UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 5, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 12 + }, + /* Index: 267 - CddEmmDomain12_CddEmmBit6EtherAVB2TXRAMEcc1bitErrCounter */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250230UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 6, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 12 + }, + /* Index: 268 - CddEmmDomain12_CddEmmBit7EtherAVB2TXRAMEccMultibitErrCounter */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250230UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 7, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 12 + }, + /* Index: 269 - CddEmmDomain12_CddEmmBit8EtherAVB2RXRAMEcc1bitErrCounter */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250230UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 8, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 12 + }, + /* Index: 270 - CddEmmDomain12_CddEmmBit9EtherAVB2RXRAMEccMultibitErrCounter */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250230UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 9, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 12 + }, + /* Index: 271 - CddEmmDomain12_CddEmmBit10EtherAVB1TXRAMEcc1bitErrCounter */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250230UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 10, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 12 + }, + /* Index: 272 - */ +/* CddEmmDomain12_CddEmmBit11EtherAVB1TXRAMEccMultibitErrCounter */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250230UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 11, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 12 + }, + /* Index: 273 - CddEmmDomain12_CddEmmBit12EtherAVB1RXRAMEcc1bitErrCounter */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250230UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 12, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 12 + }, + /* Index: 274 - */ +/* CddEmmDomain12_CddEmmBit13EtherAVB1RXRAMEccMultibitErrCounter */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250230UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 13, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 12 + }, + /* Index: 275 - CddEmmDomain12_CddEmmBit14EtherAVB0TXRAMEcc1bitErrCounter */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250230UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 14, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 12 + }, + /* Index: 276 - */ +/* CddEmmDomain12_CddEmmBit15EtherAVB0TXRAMEccMultibitErrCounter */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250230UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 15, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 12 + }, + /* Index: 277 - CddEmmDomain12_CddEmmBit16EtherAVB0RXRAMEcc1bitErrCounter */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250230UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 16, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 12 + }, + /* Index: 278 - */ +/* CddEmmDomain12_CddEmmBit17EtherAVB0RXRAMEccMultibitErrCounter */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250230UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 17, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 12 + }, + /* Index: 279 - CddEmmDomain12_CddEmmBit18EtherTSNRxDataSRAMEDCErrCounter */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250230UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 18, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 12 + }, + /* Index: 280 - CddEmmDomain12_CddEmmBit20EtherTSNRxCtrlSRAMEDCErrCounter */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250230UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 20, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 12 + }, + /* Index: 281 - CddEmmDomain12_CddEmmBit22EtherTSNTxDataSRAMEDCErrCounter */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250230UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 22, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 12 + }, + /* Index: 282 - CddEmmDomain12_CddEmmBit24EtherTSNTxCtrlSRAMEDCErrCounter */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250230UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 24, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 12 + }, + /* Index: 283 - */ +/* CddEmmDomain12_CddEmmBit26EtherTSNTASCtrlListSRAMEDCErrCounter */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250230UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 26, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 12 + }, + /* Index: 284 - */ +/* CddEmmDomain12_CddEmmBit28EtherTSNPSFPCtrlListSRAMEDCErrCounter */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250230UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 28, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 12 + }, + /* Index: 285 - */ +/* CddEmmDomain12_CddEmmBit30EtherTSNRxDescriptionrAdrrSRAMEDCErrCounter */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250230UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 30, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 12 + }, + /* Index: 286 - */ +/* CddEmmDomain13_CddEmmBit0EtherTSNTxDescriptionrAdrrSRAMEDCErrCounter */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250234UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 0, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 13 + }, + /* Index: 287 - */ +/* CddEmmDomain13_CddEmmBit2EtherTSNTxBufferAdrrSRAMEDCErrCounter */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250234UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 2, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 13 + }, + /* Index: 288 - */ +/* CddEmmDomain13_CddEmmBit4EtherTSNRxEFrameBufferAdrrSRAMEDCErrCounter */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250234UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 4, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 13 + }, + /* Index: 289 - */ +/* CddEmmDomain13_CddEmmBit6EtherTSNRxPFrameBufferAdrrSRAMEDCErrCounter */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250234UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 6, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 13 + }, + /* Index: 290 - CddEmmDomain16_CddEmmBit0RTCore0EDCBtwRTCPUAXISlavebridgeErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250240UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 0, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 16 + }, + /* Index: 291 - CddEmmDomain16_CddEmmBit1RTCore0TCMMemoriesFatalErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250240UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 1, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 16 + }, + /* Index: 292 - CddEmmDomain16_CddEmmBit2RTCore0TCMCorrectableErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250240UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 2, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 16 + }, + /* Index: 293 - CddEmmDomain16_CddEmmBit3RTCore0EDCBtwRTCPUWritebufferErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250240UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 3, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 16 + }, + /* Index: 294 - CddEmmDomain16_CddEmmBit4RTCore0AXISILockstepComparator0Err */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250240UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 4, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 16 + }, + /* Index: 295 - CddEmmDomain16_CddEmmBit5RTCore0InstructionCacheErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250240UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 5, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 16 + }, + /* Index: 296 - CddEmmDomain16_CddEmmBit6RTCore0DataCacheErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250240UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 6, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 16 + }, + /* Index: 297 - CddEmmDomain16_CddEmmBit7RTCore0AXISILockstepComparator1Err */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250240UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 7, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 16 + }, + /* Index: 298 - CddEmmDomain16_CddEmmBit8RTCore0AXIMIDECERRSLVERRBusErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250240UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 8, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 16 + }, + /* Index: 299 - CddEmmDomain16_CddEmmBit9RTCore0AXISIFatalErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250240UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 9, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 16 + }, + /* Index: 300 - CddEmmDomain16_CddEmmBit10RTCore0AXISICorrectableErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250240UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 10, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 16 + }, + /* Index: 301 - CddEmmDomain16_CddEmmBit11RTCore0AXIMIFatalErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250240UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 11, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 16 + }, + /* Index: 302 - CddEmmDomain16_CddEmmBit12RTCore0AXIMICorrectableErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250240UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 12, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 16 + }, + /* Index: 303 - */ +/* CddEmmDomain16_CddEmmBit13RTCore0NonSafetySwitchingComparator0Err */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250240UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 13, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 16 + }, + /* Index: 304 - CddEmmDomain16_CddEmmBit14THSTsc4TempExceedsThreshold3 */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250240UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 14, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 16 + }, + /* Index: 305 - CddEmmDomain16_CddEmmBit15THSTsc4TempExceedsThreshold2 */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250240UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 15, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 16 + }, + /* Index: 306 - CddEmmDomain16_CddEmmBit16THSTsc4TempExceedsThreshold1 */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250240UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 16, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 16 + }, + /* Index: 307 - CddEmmDomain16_CddEmmBit17THSTsc3TempExceedsThreshold3 */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250240UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 17, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 16 + }, + /* Index: 308 - CddEmmDomain16_CddEmmBit18THSTsc3TempExceedsThreshold2 */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250240UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 18, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 16 + }, + /* Index: 309 - CddEmmDomain16_CddEmmBit19THSTsc3TempExceedsThreshold1 */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250240UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 19, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 16 + }, + /* Index: 310 - CddEmmDomain16_CddEmmBit20THSTsc2TempExceedsThreshold3 */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250240UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 20, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 16 + }, + /* Index: 311 - CddEmmDomain16_CddEmmBit21THSTsc2TempExceedsThreshold2 */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250240UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 21, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 16 + }, + /* Index: 312 - CddEmmDomain16_CddEmmBit22THSTsc2TempExceedsThreshold1 */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250240UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 22, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 16 + }, + /* Index: 313 - CddEmmDomain16_CddEmmBit23THSTsc1TempExceedsThreshold3 */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250240UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 23, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 16 + }, + /* Index: 314 - CddEmmDomain16_CddEmmBit24THSTsc1TempExceedsThreshold2 */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250240UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 24, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 16 + }, + /* Index: 315 - CddEmmDomain16_CddEmmBit25THSTsc1TempExceedsThreshold1 */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250240UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 25, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 16 + }, + /* Index: 316 - CddEmmDomain16_CddEmmBit26THSTsc4DetectsFailure */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250240UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 26, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 16 + }, + /* Index: 317 - CddEmmDomain16_CddEmmBit27THSTsc3DetectsFailure */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250240UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 27, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 16 + }, + /* Index: 318 - CddEmmDomain16_CddEmmBit28THSTsc2DetectsFailure */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250240UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 28, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 16 + }, + /* Index: 319 - CddEmmDomain16_CddEmmBit29THSTsc1DetectsFailure */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250240UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 29, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 16 + }, + /* Index: 320 - */ +/* CddEmmDomain17_CddEmmBit5RTCore0NonSafetySwitchingComparator1Err */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250244UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 5, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 17 + }, + /* Index: 321 - CddEmmDomain17_CddEmmBit6RTCore0AsynchronousTransferErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250244UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 6, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 17 + }, + /* Index: 322 - CddEmmDomain17_CddEmmBit7RTCore0IllegalAxSIZEAxBURSTErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250244UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 7, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 17 + }, + /* Index: 323 - CddEmmDomain17_CddEmmBit10RTCore0FatalErrCannotRecorded */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250244UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 10, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 17 + }, + /* Index: 324 - CddEmmDomain17_CddEmmBit11RTCore0CorrectableNotRecordedErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250244UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 11, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 17 + }, + /* Index: 325 - CddEmmDomain17_CddEmmBit15RTVRAM0CRCErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250244UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 15, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 17 + }, + /* Index: 326 - CddEmmDomain17_CddEmmBit16RTVRAM0CheckerCoreComparitionErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250244UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 16, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 17 + }, + /* Index: 327 - CddEmmDomain17_CddEmmBit17RTVRAM1CheckerCoreComparitionErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250244UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 17, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 17 + }, + /* Index: 328 - CddEmmDomain17_CddEmmBit18RTVRAM1EdcMultibitErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250244UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 18, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 17 + }, + /* Index: 329 - CddEmmDomain17_CddEmmBit19RTVRAM1Edc1bitErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250244UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 19, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 17 + }, + /* Index: 330 - CddEmmDomain17_CddEmmBit20RTVRAM1CRCErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250244UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 20, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 17 + }, + /* Index: 331 - CddEmmDomain17_CddEmmBit21RTVRAM1SafetyAccessProtectionErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250244UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 21, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 17 + }, + /* Index: 332 - CddEmmDomain17_CddEmmBit22RTVRAM1SecureAccessProtectionErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250244UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 22, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 17 + }, + /* Index: 333 - CddEmmDomain17_CddEmmBit23RTVRAM1TimeOutErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250244UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 23, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 17 + }, + /* Index: 334 - CddEmmDomain17_CddEmmBit24FCPRCInternaSRAMEdcErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250244UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 24, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 17 + }, + /* Index: 335 - CddEmmDomain17_CddEmmBit25FCPRCDCLSErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250244UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 25, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 17 + }, + /* Index: 336 - CddEmmDomain17_CddEmmBit26FCPRSInternalSRAMEdcErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250244UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 26, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 17 + }, + /* Index: 337 - CddEmmDomain17_CddEmmBit27FCPRSDCLSErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250244UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 27, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 17 + }, + /* Index: 338 - CddEmmDomain17_CddEmmBit29VIPFCPRMInternalSRAMEdcErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250244UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 29, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 17 + }, + /* Index: 339 - CddEmmDomain18_CddEmmBit0RFSOCFE0ErrCh8 */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250248UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 0, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 18 + }, + /* Index: 340 - CddEmmDomain18_CddEmmBit1RFSOCFE0ErrCh9 */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250248UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 1, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 18 + }, + /* Index: 341 - CddEmmDomain18_CddEmmBit2RFSOCFE0ErrCh10 */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250248UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 2, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 18 + }, + /* Index: 342 - CddEmmDomain18_CddEmmBit3RFSOCFE1ErrCh8 */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250248UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 3, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 18 + }, + /* Index: 343 - CddEmmDomain18_CddEmmBit4RFSOCFE1ErrCh9 */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250248UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 4, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 18 + }, + /* Index: 344 - CddEmmDomain18_CddEmmBit5RFSOCFE1ErrCh10 */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250248UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 5, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 18 + }, + /* Index: 345 - CddEmmDomain18_CddEmmBit6RFSOTOEErrCh8 */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250248UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 6, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 18 + }, + /* Index: 346 - CddEmmDomain18_CddEmmBit7RFSOTOEErrCh9 */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250248UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 7, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 18 + }, + /* Index: 347 - CddEmmDomain18_CddEmmBit8RFSOTOEErrCh10 */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250248UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 8, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 18 + }, + /* Index: 348 - CddEmmDomain18_CddEmmBit9APMUCortexR52Core2ResetControlErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250248UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 9, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 18 + }, + /* Index: 349 - CddEmmDomain18_CddEmmBit10APMUCortexR52Core1ResetControlErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250248UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 10, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 18 + }, + /* Index: 350 - CddEmmDomain18_CddEmmBit11APMUCA76Cl1PowerControlErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250248UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 11, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 18 + }, + /* Index: 351 - CddEmmDomain18_CddEmmBit12APMUCA76Cl0PowerControlErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250248UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 12, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 18 + }, + /* Index: 352 - CddEmmDomain18_CddEmmBit13iVCP1EInternalSRAMEdcErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250248UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 13, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 18 + }, + /* Index: 353 - CddEmmDomain18_CddEmmBit18ISPChSelectorErrCh1 */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250248UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 18, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 18 + }, + /* Index: 354 - CddEmmDomain18_CddEmmBit19ISPCoreErrCh1 */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250248UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 19, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 18 + }, + /* Index: 355 - CddEmmDomain18_CddEmmBit20ISPChSelectorErrCh0 */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250248UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 20, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 18 + }, + /* Index: 356 - CddEmmDomain18_CddEmmBit21ISPCoreErrCh0 */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250248UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 21, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 18 + }, + /* Index: 357 - CddEmmDomain18_CddEmmBit22IMRLX6Ch1EcmErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250248UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 22, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 18 + }, + /* Index: 358 - CddEmmDomain18_CddEmmBit23IMRLX6Ch0EcmErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250248UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 23, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 18 + }, + /* Index: 359 - CddEmmDomain18_CddEmmBit25IMRLX6Ch4EcmErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250248UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 25, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 18 + }, + /* Index: 360 - CddEmmDomain18_CddEmmBit26IMRLX6Ch3EcmErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250248UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 26, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 18 + }, + /* Index: 361 - CddEmmDomain18_CddEmmBit27IMRLX6Ch2EcmErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250248UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 27, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 18 + }, + /* Index: 362 - CddEmmDomain19_CddEmmBit0DMAC2SYSSecurityAccessErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE625024CUL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 0, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 19 + }, + /* Index: 363 - */ +/* CddEmmDomain19_CddEmmBit3APSysCciSFRAMAddrFeedbackComparatorErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE625024CUL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 3, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 19 + }, + /* Index: 364 - CddEmmDomain19_CddEmmBit4DBSC5DFIDomaindclsECMErrDbs0 */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE625024CUL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 4, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 19 + }, + /* Index: 365 - CddEmmDomain19_CddEmmBit5DBSC5AXIDomaindclsECMrrDbs0 */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE625024CUL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 5, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 19 + }, + /* Index: 366 - CddEmmDomain19_CddEmmBit6DBSC5DFIDomaindclsECMErrDbs1 */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE625024CUL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 6, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 19 + }, + /* Index: 367 - CddEmmDomain19_CddEmmBit7DBSC5AXIDomaindclsECMErrDbs1 */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE625024CUL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 7, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 19 + }, + /* Index: 368 - CddEmmDomain19_CddEmmBit8RFSOCFE1ErrCh0 */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE625024CUL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 8, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 19 + }, + /* Index: 369 - CddEmmDomain19_CddEmmBit9RFSOCFE1ErrCh1 */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE625024CUL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 9, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 19 + }, + /* Index: 370 - CddEmmDomain19_CddEmmBit10RFSOCFE1ErrCh2 */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE625024CUL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 10, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 19 + }, + /* Index: 371 - CddEmmDomain19_CddEmmBit11RFSOCFE1ErrCh3 */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE625024CUL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 11, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 19 + }, + /* Index: 372 - CddEmmDomain19_CddEmmBit12RFSOCFE1ErrCh4 */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE625024CUL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 12, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 19 + }, + /* Index: 373 - CddEmmDomain19_CddEmmBit13RFSOCFE1ErrCh5 */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE625024CUL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 13, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 19 + }, + /* Index: 374 - CddEmmDomain19_CddEmmBit14RFSOCFE1ErrCh6 */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE625024CUL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 14, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 19 + }, + /* Index: 375 - CddEmmDomain19_CddEmmBit15RFSOCFE1ErrCh7 */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE625024CUL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 15, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 19 + }, + /* Index: 376 - CddEmmDomain19_CddEmmBit16RFSOCFE0ErrCh0 */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE625024CUL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 16, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 19 + }, + /* Index: 377 - CddEmmDomain19_CddEmmBit17RFSOCFE0ErrCh1 */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE625024CUL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 17, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 19 + }, + /* Index: 378 - CddEmmDomain19_CddEmmBit18RFSOCFE0ErrCh2 */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE625024CUL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 18, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 19 + }, + /* Index: 379 - CddEmmDomain19_CddEmmBit19RFSOCFE0ErrCh3 */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE625024CUL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 19, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 19 + }, + /* Index: 380 - CddEmmDomain19_CddEmmBit20RFSOCFE0ErrCh4 */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE625024CUL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 20, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 19 + }, + /* Index: 381 - CddEmmDomain19_CddEmmBit21RFSOCFE0ErrCh5 */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE625024CUL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 21, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 19 + }, + /* Index: 382 - CddEmmDomain19_CddEmmBit22RFSOCFE0ErrCh6 */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE625024CUL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 22, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 19 + }, + /* Index: 383 - CddEmmDomain19_CddEmmBit23RFSOCFE0ErrCh7 */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE625024CUL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 23, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 19 + }, + /* Index: 384 - CddEmmDomain19_CddEmmBit24RFSOTOEErrCh0 */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE625024CUL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 24, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 19 + }, + /* Index: 385 - CddEmmDomain19_CddEmmBit25RFSOTOEErrCh1 */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE625024CUL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 25, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 19 + }, + /* Index: 386 - CddEmmDomain19_CddEmmBit26RFSOTOEErrCh2 */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE625024CUL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 26, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 19 + }, + /* Index: 387 - CddEmmDomain19_CddEmmBit27RFSOTOEErrCh3 */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE625024CUL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 27, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 19 + }, + /* Index: 388 - CddEmmDomain19_CddEmmBit28RFSOTOEErrCh4 */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE625024CUL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 28, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 19 + }, + /* Index: 389 - CddEmmDomain19_CddEmmBit29RFSOTOEErrCh5 */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE625024CUL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 29, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 19 + }, + /* Index: 390 - CddEmmDomain19_CddEmmBit30RFSOTOEErrCh6 */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE625024CUL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 30, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 19 + }, + /* Index: 391 - CddEmmDomain19_CddEmmBit31RFSOTOEErrCh7 */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE625024CUL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 31, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 19 + }, + /* Index: 392 - CddEmmDomain20_CddEmmBit1IPMMUirCoreComparitionErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250250UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 1, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 20 + }, + /* Index: 393 - CddEmmDomain20_CddEmmBit2IPMMUrt0CoreComparitionErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250250UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 2, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 20 + }, + /* Index: 394 - CddEmmDomain20_CddEmmBit3IPMMUmmoreComparitionErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250250UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 3, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 20 + }, + /* Index: 395 - CddEmmDomain20_CddEmmBit4IPMMUds0CoreComparitionErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250250UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 4, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 20 + }, + /* Index: 396 - CddEmmDomain20_CddEmmBit5DMAC0RTFusaDCLSComparisonErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250250UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 5, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 20 + }, + /* Index: 397 - CddEmmDomain20_CddEmmBit6DMAC0RTSecurityAccessErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250250UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 6, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 20 + }, + /* Index: 398 - CddEmmDomain20_CddEmmBit9DMAC1RTFusaDCLSComparisonErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250250UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 9, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 20 + }, + /* Index: 399 - CddEmmDomain20_CddEmmBit10DMAC1RTSecurityAccessErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250250UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 10, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 20 + }, + /* Index: 400 - CddEmmDomain20_CddEmmBit13DMAC2RTFusaDCLSComparisonErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250250UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 13, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 20 + }, + /* Index: 401 - CddEmmDomain20_CddEmmBit14DMAC2RTSecurityAccessErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250250UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 14, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 20 + }, + /* Index: 402 - CddEmmDomain20_CddEmmBit17DMAC3RTFusaDCLSComparisonErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250250UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 17, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 20 + }, + /* Index: 403 - CddEmmDomain20_CddEmmBit18DMAC3RTSecurityAccessErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250250UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 18, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 20 + }, + /* Index: 404 - CddEmmDomain20_CddEmmBit21DMAC1SYSFusaDCLSComparisonErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250250UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 21, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 20 + }, + /* Index: 405 - CddEmmDomain20_CddEmmBit22DMAC1SYSSecurityAccessErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250250UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 22, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 20 + }, + /* Index: 406 - CddEmmDomain20_CddEmmBit25DMAC2SYSFusaDCLSComparisonErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250250UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 25, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 20 + }, + /* Index: 407 - CddEmmDomain20_CddEmmBit26RTCore0LongHypervisorInterruptErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250250UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 26, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 20 + }, + /* Index: 408 - CddEmmDomain20_CddEmmBit27RTCore0HypervisorModeFatalErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250250UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 27, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 20 + }, + /* Index: 409 - */ +/* CddEmmDomain20_CddEmmBit28RTCore0EL2ControlledabortExceptionErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250250UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 28, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 20 + }, + /* Index: 410 - */ +/* CddEmmDomain20_CddEmmBit29RTCore0EL1ControlledAbortExceptionErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250250UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 29, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 20 + }, + /* Index: 411 - CddEmmDomain20_CddEmmBit30RTCore0UndefinedExceptionErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250250UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 30, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 20 + }, + /* Index: 412 - CddEmmDomain20_CddEmmBit31RTCore0AXIMITimeoutErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250250UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 31, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 20 + }, + /* Index: 413 - CddEmmDomain21_CddEmmBit0CPGPLLCBFUSAFreqErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250254UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 0, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 21 + }, + /* Index: 414 - CddEmmDomain21_CddEmmBit1CPGSlAccessBusFreqErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250254UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 1, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 21 + }, + /* Index: 415 - CddEmmDomain21_CddEmmBit2CPGRTckmcr52FreqErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250254UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 2, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 21 + }, + /* Index: 416 - CddEmmDomain21_CddEmmBit3CPGHSCFreqErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250254UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 3, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 21 + }, + /* Index: 417 - CddEmmDomain21_CddEmmBit9CPGMMFreqErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250254UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 9, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 21 + }, + /* Index: 418 - CddEmmDomain21_CddEmmBit10CPGIMPFreqErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250254UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 10, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 21 + }, + /* Index: 419 - CddEmmDomain21_CddEmmBit11CPGVipFreqErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250254UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 11, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 21 + }, + /* Index: 420 - CddEmmDomain21_CddEmmBit12CPGVcFreqErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250254UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 12, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 21 + }, + /* Index: 421 - CddEmmDomain21_CddEmmBit13CPGVioFreqErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250254UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 13, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 21 + }, + /* Index: 422 - CddEmmDomain21_CddEmmBit15CPGPeripheralFreqErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250254UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 15, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 21 + }, + /* Index: 423 - CddEmmDomain21_CddEmmBit16CPGRTckmrtFreqErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250254UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 16, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 21 + }, + /* Index: 424 - CddEmmDomain21_CddEmmBit17CPGGsxFreqErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250254UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 17, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 21 + }, + /* Index: 425 - CddEmmDomain21_CddEmmBit21IPMMUmmTLBRAMEcc1bitlErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250254UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 21, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 21 + }, + /* Index: 426 - CddEmmDomain21_CddEmmBit22IPMMUmmTLBRAMEccMultibitErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250254UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 22, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 21 + }, + /* Index: 427 - CddEmmDomain21_CddEmmBit23IPMMUvip1CoreComparitionErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250254UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 23, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 21 + }, + /* Index: 428 - CddEmmDomain21_CddEmmBit24IPMMUvip0CoreComparitionErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250254UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 24, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 21 + }, + /* Index: 429 - CddEmmDomain21_CddEmmBit25IPMMUvi1CoreComparitionErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250254UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 25, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 21 + }, + /* Index: 430 - CddEmmDomain21_CddEmmBit26IPMMUvi0CoreComparitionErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250254UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 26, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 21 + }, + /* Index: 431 - CddEmmDomain21_CddEmmBit27IPMMUvcCoreComparitionErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250254UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 27, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 21 + }, + /* Index: 432 - CddEmmDomain21_CddEmmBit28IPMMUrt1CoreComparitionErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250254UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 28, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 21 + }, + /* Index: 433 - CddEmmDomain21_CddEmmBit29IPMMU3dgCoreComparitionErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250254UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 29, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 21 + }, + /* Index: 434 - CddEmmDomain21_CddEmmBit31IPMMUhcCoreComparitionErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250254UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 31, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 21 + }, + /* Index: 435 - CddEmmDomain22_CddEmmBit28ICUMXclockmonitorErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250258UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 28, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 22 + }, + /* Index: 436 - CddEmmDomain23_CddEmmBit3FSIRHierarchyCnn0TimeoutErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE625025CUL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 3, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 23 + }, + /* Index: 437 - CddEmmDomain23_CddEmmBit14FSIRHierarchyDSP0TimeoutErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE625025CUL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 14, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 23 + }, + /* Index: 438 - CddEmmDomain23_CddEmmBit15FSIRHierarchyDSP1TimeoutErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE625025CUL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 15, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 23 + }, + /* Index: 439 - CddEmmDomain23_CddEmmBit16FSIRHierarchyDSP2TimeoutErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE625025CUL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 16, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 23 + }, + /* Index: 440 - CddEmmDomain23_CddEmmBit17FSIRHierarchyDSP3TimeoutErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE625025CUL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 17, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 23 + }, + /* Index: 441 - CddEmmDomain23_CddEmmBit20FSIRHierarchyCNRAM0TimeoutErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE625025CUL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 20, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 23 + }, + /* Index: 442 - CddEmmDomain23_CddEmmBit21FSIRHierarchySlimdmac0TimeoutErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE625025CUL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 21, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 23 + }, + /* Index: 443 - CddEmmDomain23_CddEmmBit22FSIRHierarchySlimdmac1TimeoutErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE625025CUL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 22, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 23 + }, + /* Index: 444 - CddEmmDomain23_CddEmmBit23FSIRHierarchyIMPRAM0TimeoutErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE625025CUL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 23, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 23 + }, + /* Index: 445 - CddEmmDomain23_CddEmmBit25FS3DGHierarchyRASCALTimeoutErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE625025CUL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 25, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 23 + }, + /* Index: 446 - CddEmmDomain23_CddEmmBit26FS3DGHierarchyDUSTATimeoutErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE625025CUL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 26, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 23 + }, + /* Index: 447 - */ +/* CddEmmDomain23_CddEmmBit27FS3DGHierarchySLCSIDEKICKTimeoutErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE625025CUL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 27, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 23 + }, + /* Index: 448 - */ +/* CddEmmDomain23_CddEmmBit28FS3DGHierarchyexceptRGXcoreTimeoutErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE625025CUL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 28, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 23 + }, + /* Index: 449 - CddEmmDomain23_CddEmmBit29FS3DGHierarchyXonstTimeoutErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE625025CUL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 29, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 23 + }, + /* Index: 450 - CddEmmDomain23_CddEmmBit30FSMMHierarchyDDRTimeoutErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE625025CUL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 30, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 23 + }, + /* Index: 451 - CddEmmDomain24_CddEmmBit0FSVCHierarchyIMR1TimeoutErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250260UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 0, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 24 + }, + /* Index: 452 - CddEmmDomain24_CddEmmBit1FSVCHierarchyIMR2TimeoutErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250260UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 1, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 24 + }, + /* Index: 453 - CddEmmDomain24_CddEmmBit3FSVCHierarchyIMS0TimeoutErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250260UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 3, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 24 + }, + /* Index: 454 - CddEmmDomain24_CddEmmBit4FSVCHierarchyIMS1TimeoutErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250260UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 4, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 24 + }, + /* Index: 455 - CddEmmDomain24_CddEmmBit6FSVIPHierarchyTimeoutErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250260UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 6, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 24 + }, + /* Index: 456 - CddEmmDomain24_CddEmmBit7FSVIPHierarchyDULTimeoutErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250260UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 7, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 24 + }, + /* Index: 457 - CddEmmDomain24_CddEmmBit9FSVIPHierarchyUMFL0TimeoutErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250260UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 9, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 24 + }, + /* Index: 458 - CddEmmDomain24_CddEmmBit11FSVIPHierarchySMPS0TimeoutErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250260UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 11, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 24 + }, + /* Index: 459 - CddEmmDomain24_CddEmmBit15FSVIPHierarchySMPO0TimeoutErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250260UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 15, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 24 + }, + /* Index: 460 - CddEmmDomain24_CddEmmBit17FSVIPHierarchy2CLE0TimeoutErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250260UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 17, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 24 + }, + /* Index: 461 - CddEmmDomain24_CddEmmBit18FSVIPHierarchy2CLE1TimeoutErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250260UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 18, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 24 + }, + /* Index: 462 - CddEmmDomain24_CddEmmBit19FSIRHierarchyTimeoutErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250260UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 19, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 24 + }, + /* Index: 463 - */ +/* CddEmmDomain24_CddEmmBit20FSIRHierarchyA3IRBusWrapperTimeoutErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250260UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 20, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 24 + }, + /* Index: 464 - CddEmmDomain24_CddEmmBit21FSIRHierarchyIMP0TimeoutErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250260UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 21, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 24 + }, + /* Index: 465 - CddEmmDomain24_CddEmmBit22FSIRHierarchyIMP1TimeoutErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250260UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 22, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 24 + }, + /* Index: 466 - CddEmmDomain24_CddEmmBit23FSIRHierarchyIMP2TimeoutErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250260UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 23, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 24 + }, + /* Index: 467 - CddEmmDomain24_CddEmmBit24FSIRHierarchyIMP3TimeoutErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250260UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 24, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 24 + }, + /* Index: 468 - */ +/* CddEmmDomain24_CddEmmBit25FSIRHierarchyPSC0DMAC0RepeatTimeoutErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250260UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 25, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 24 + }, + /* Index: 469 - */ +/* CddEmmDomain24_CddEmmBit26FSIRHierarchyDMAC2DMAC1RepeatTimeoutErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250260UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 26, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 24 + }, + /* Index: 470 - CddEmmDomain24_CddEmmBit27FSIRHierarchyOCV0TimeoutErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250260UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 27, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 24 + }, + /* Index: 471 - CddEmmDomain24_CddEmmBit28FSIRHierarchyOCV1TimeoutErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250260UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 28, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 24 + }, + /* Index: 472 - CddEmmDomain24_CddEmmBit29FSIRHierarchyOCV2TimeoutErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250260UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 29, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 24 + }, + /* Index: 473 - CddEmmDomain24_CddEmmBit30FSIRHierarchyOCV3TimeoutErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250260UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 30, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 24 + }, + /* Index: 474 - CddEmmDomain25_CddEmmBit0FSTOPHierarchyTimeoutErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250264UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 0, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 25 + }, + /* Index: 475 - CddEmmDomain25_CddEmmBit1FSMMHierarchyTimeoutErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250264UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 1, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 25 + }, + /* Index: 476 - CddEmmDomain25_CddEmmBit2FSMMHierarchyDBSC0TimeoutErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250264UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 2, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 25 + }, + /* Index: 477 - CddEmmDomain25_CddEmmBit3FSMMHierarchyDBSC1TimeoutErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250264UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 3, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 25 + }, + /* Index: 478 - CddEmmDomain25_CddEmmBit4FSrtCPUHierarchyTimeoutErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250264UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 4, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 25 + }, + /* Index: 479 - CddEmmDomain25_CddEmmBit5FSrtCPUHierarchyCR52TimeoutErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250264UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 5, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 25 + }, + /* Index: 480 - CddEmmDomain25_CddEmmBit6FSCCIHierarchyTimeoutErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250264UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 6, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 25 + }, + /* Index: 481 - CddEmmDomain25_CddEmmBit7FSCPU0HierarchyC4TimeoutErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250264UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 7, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 25 + }, + /* Index: 482 - CddEmmDomain25_CddEmmBit8FSCPU0HierarchyA3ETimeoutErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250264UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 8, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 25 + }, + /* Index: 483 - CddEmmDomain25_CddEmmBit9FSCPU0HierarchyCl0L3CacheTimeoutErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250264UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 9, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 25 + }, + /* Index: 484 - */ +/* CddEmmDomain25_CddEmmBit10FSCPU0HierarchyCl1L3CacheTimeoutErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250264UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 10, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 25 + }, + /* Index: 485 - CddEmmDomain25_CddEmmBit11FSCPU0HierarchyCl0CPU0TimeoutErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250264UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 11, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 25 + }, + /* Index: 486 - CddEmmDomain25_CddEmmBit12FSCPU0HierarchyCl0CPU1TimeoutErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250264UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 12, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 25 + }, + /* Index: 487 - CddEmmDomain25_CddEmmBit13FSCPU0HierarchyCl1CPU0TimeoutErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250264UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 13, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 25 + }, + /* Index: 488 - CddEmmDomain25_CddEmmBit14FSCPU0HierarchyCl1CPU1TimeoutErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250264UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 14, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 25 + }, + /* Index: 489 - */ +/* CddEmmDomain25_CddEmmBit23FSPeripheralDMACHierarchy0TimeoutErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250264UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 23, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 25 + }, + /* Index: 490 - CddEmmDomain25_CddEmmBit24FSHSpeedComHierarchyTimeoutErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250264UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 24, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 25 + }, + /* Index: 491 - CddEmmDomain25_CddEmmBit25FSVIOHierarchyTimeoutErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250264UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 25, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 25 + }, + /* Index: 492 - CddEmmDomain25_CddEmmBit26FSVIOHierarchyISP0TimeoutErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250264UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 26, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 25 + }, + /* Index: 493 - CddEmmDomain25_CddEmmBit27FSVIOHierarchyISP1TimeoutErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250264UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 27, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 25 + }, + /* Index: 494 - CddEmmDomain25_CddEmmBit30FSVCHierarchyTimeoutErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250264UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 30, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 25 + }, + /* Index: 495 - CddEmmDomain25_CddEmmBit31FSVCHierarchyIMR0TimeoutErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250264UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 31, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 25 + }, + /* Index: 496 - CddEmmDomain26_CddEmmBit3FSSIRHierarchyCnn0FailErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250268UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 3, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 26 + }, + /* Index: 497 - CddEmmDomain26_CddEmmBit14FSFSIRHierarchyDSP0FailErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250268UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 14, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 26 + }, + /* Index: 498 - CddEmmDomain26_CddEmmBit15FSFSIRHierarchyDSP1FailErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250268UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 15, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 26 + }, + /* Index: 499 - CddEmmDomain26_CddEmmBit16FSFSIRHierarchyDSP2FailErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250268UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 16, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 26 + }, + /* Index: 500 - CddEmmDomain26_CddEmmBit17FSFSIRHierarchyDSP3FailErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250268UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 17, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 26 + }, + /* Index: 501 - CddEmmDomain26_CddEmmBit20FSFSIRHierarchyCNRAM0FailErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250268UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 20, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 26 + }, + /* Index: 502 - CddEmmDomain26_CddEmmBit21FSFSIRHierarchySlimdmac0FailErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250268UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 21, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 26 + }, + /* Index: 503 - CddEmmDomain26_CddEmmBit22FSFSIRHierarchySlimdmac1FailErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250268UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 22, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 26 + }, + /* Index: 504 - CddEmmDomain26_CddEmmBit23FSFSIRHierarchyIMPRAM0FailErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250268UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 23, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 26 + }, + /* Index: 505 - CddEmmDomain26_CddEmmBit25FSFS3DGHierarchyRASCALFailErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250268UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 25, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 26 + }, + /* Index: 506 - CddEmmDomain26_CddEmmBit26FSFS3DGHierarchyDUSTAFailErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250268UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 26, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 26 + }, + /* Index: 507 - CddEmmDomain26_CddEmmBit27FSFS3DGHierarchySLCSIDEKICKFailErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250268UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 27, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 26 + }, + /* Index: 508 - */ +/* CddEmmDomain26_CddEmmBit28FSFS3DGHierarchyexceptRGXcoreFailErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250268UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 28, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 26 + }, + /* Index: 509 - CddEmmDomain26_CddEmmBit29FSFS3DGHierarchyXonstFailErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250268UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 29, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 26 + }, + /* Index: 510 - CddEmmDomain26_CddEmmBit30FSFSMMHierarchyDDRFailErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250268UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 30, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 26 + }, + /* Index: 511 - CddEmmDomain27_CddEmmBit0FSSVCHierarchyIMR1FailErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE625026CUL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 0, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 27 + }, + /* Index: 512 - CddEmmDomain27_CddEmmBit1FSSVCHierarchyIMR2FailErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE625026CUL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 1, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 27 + }, + /* Index: 513 - CddEmmDomain27_CddEmmBit3FSSVCHierarchyIMS0FailErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE625026CUL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 3, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 27 + }, + /* Index: 514 - CddEmmDomain27_CddEmmBit4FSSVCHierarchyIMS1FailErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE625026CUL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 4, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 27 + }, + /* Index: 515 - CddEmmDomain27_CddEmmBit6FSSVIPHierarchyFailErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE625026CUL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 6, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 27 + }, + /* Index: 516 - CddEmmDomain27_CddEmmBit7FSSVIPHierarchyDULFailErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE625026CUL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 7, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 27 + }, + /* Index: 517 - CddEmmDomain27_CddEmmBit9FSSVIPHierarchyUMFL0FailErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE625026CUL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 9, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 27 + }, + /* Index: 518 - CddEmmDomain27_CddEmmBit11FSFSVIPHierarchySMPS0FailErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE625026CUL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 11, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 27 + }, + /* Index: 519 - CddEmmDomain27_CddEmmBit15FSFSVIPHierarchySMPO0FailErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE625026CUL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 15, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 27 + }, + /* Index: 520 - CddEmmDomain27_CddEmmBit17FSFSVIPHierarchy2CLE0FailErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE625026CUL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 17, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 27 + }, + /* Index: 521 - CddEmmDomain27_CddEmmBit18FSFSVIPHierarchy2CLE1FailErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE625026CUL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 18, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 27 + }, + /* Index: 522 - CddEmmDomain27_CddEmmBit19FSFSIRHierarchyFailErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE625026CUL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 19, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 27 + }, + /* Index: 523 - */ +/* CddEmmDomain27_CddEmmBit20FSFSIRHierarchyA3IRBusWrapperFailErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE625026CUL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 20, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 27 + }, + /* Index: 524 - CddEmmDomain27_CddEmmBit21FSFSIRHierarchyIMP0FailErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE625026CUL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 21, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 27 + }, + /* Index: 525 - CddEmmDomain27_CddEmmBit22FSFSIRHierarchyIMP1FailErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE625026CUL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 22, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 27 + }, + /* Index: 526 - CddEmmDomain27_CddEmmBit23FSFSIRHierarchyIMP2FailErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE625026CUL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 23, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 27 + }, + /* Index: 527 - CddEmmDomain27_CddEmmBit24FSFSIRHierarchyIMP3FailErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE625026CUL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 24, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 27 + }, + /* Index: 528 - */ +/* CddEmmDomain27_CddEmmBit25FSFSIRHierarchyPSC0DMAC0RepeatFailErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE625026CUL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 25, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 27 + }, + /* Index: 529 - */ +/* CddEmmDomain27_CddEmmBit26FSFSIRHierarchyDMAC2DMAC1RepeatFailErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE625026CUL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 26, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 27 + }, + /* Index: 530 - CddEmmDomain27_CddEmmBit27FSFSIRHierarchyOCV0FailErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE625026CUL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 27, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 27 + }, + /* Index: 531 - CddEmmDomain27_CddEmmBit28FSFSIRHierarchyOCV1FailErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE625026CUL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 28, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 27 + }, + /* Index: 532 - CddEmmDomain27_CddEmmBit29FSFSIRHierarchyOCV2FailErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE625026CUL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 29, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 27 + }, + /* Index: 533 - CddEmmDomain27_CddEmmBit30FSFSIRHierarchyOCV3FailErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE625026CUL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 30, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 27 + }, + /* Index: 534 - CddEmmDomain28_CddEmmBit0FSFSTOPHierarchyFailErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250270UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 0, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 28 + }, + /* Index: 535 - CddEmmDomain28_CddEmmBit1FSFSMMHierarchyFailErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250270UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 1, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 28 + }, + /* Index: 536 - CddEmmDomain28_CddEmmBit2FSFSMMHierarchyDBSC0FailErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250270UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 2, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 28 + }, + /* Index: 537 - CddEmmDomain28_CddEmmBit3FSFSMMHierarchyDBSC1FailErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250270UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 3, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 28 + }, + /* Index: 538 - CddEmmDomain28_CddEmmBit4FSFSrtCPUHierarchyFailErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250270UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 4, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 28 + }, + /* Index: 539 - CddEmmDomain28_CddEmmBit5FSFSrtCPUHierarchyCR52FailErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250270UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 5, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 28 + }, + /* Index: 540 - CddEmmDomain28_CddEmmBit6FSFSCCIHierarchyFailErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250270UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 6, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 28 + }, + /* Index: 541 - CddEmmDomain28_CddEmmBit7FSFSCPU0HierarchyC4FailErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250270UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 7, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 28 + }, + /* Index: 542 - CddEmmDomain28_CddEmmBit8FSFSCPU0HierarchyA3EFailErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250270UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 8, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 28 + }, + /* Index: 543 - CddEmmDomain28_CddEmmBit9FSFSCPU0HierarchyCl0L3CacheFailErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250270UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 9, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 28 + }, + /* Index: 544 - CddEmmDomain28_CddEmmBit10FSFSCPU0HierarchyCl1L3CacheFailErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250270UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 10, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 28 + }, + /* Index: 545 - CddEmmDomain28_CddEmmBit11FSFSCPU0HierarchyCl0CPU0FailErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250270UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 11, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 28 + }, + /* Index: 546 - CddEmmDomain28_CddEmmBit12FSFSCPU0HierarchyCl0CPU1FailErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250270UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 12, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 28 + }, + /* Index: 547 - CddEmmDomain28_CddEmmBit13FSFSCPU0HierarchyCl1CPU0FailErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250270UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 13, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 28 + }, + /* Index: 548 - CddEmmDomain28_CddEmmBit14FSFSCPU0HierarchyCl1CPU1FailErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250270UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 14, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 28 + }, + /* Index: 549 - */ +/* CddEmmDomain28_CddEmmBit23FSFSPeripheralDMACHierarchy0FailErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250270UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 23, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 28 + }, + /* Index: 550 - CddEmmDomain28_CddEmmBit24FSFSHSpeedComHierarchyFailErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250270UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 24, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 28 + }, + /* Index: 551 - CddEmmDomain28_CddEmmBit25FSFSVIOHierarchyFailErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250270UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 25, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 28 + }, + /* Index: 552 - CddEmmDomain28_CddEmmBit26FSFSVIOHierarchyISP0FailErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250270UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 26, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 28 + }, + /* Index: 553 - CddEmmDomain28_CddEmmBit27FSFSVIOHierarchyISP1FailErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250270UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 27, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 28 + }, + /* Index: 554 - CddEmmDomain28_CddEmmBit30FSFSVCHierarchyFailErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250270UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 30, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 28 + }, + /* Index: 555 - CddEmmDomain28_CddEmmBit31FSFSVCHierarchyIMR0FailErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250270UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 31, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 28 + }, + /* Index: 556 - CddEmmDomain29_CddEmmBit3FSRHierarchyCnn0SCanAXibusErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250274UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 3, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 29 + }, + /* Index: 557 - CddEmmDomain29_CddEmmBit14FSIRHierarchyDSP0SCanAXibusErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250274UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 14, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 29 + }, + /* Index: 558 - CddEmmDomain29_CddEmmBit15FSIRHierarchyDSP1SCanAXibusErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250274UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 15, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 29 + }, + /* Index: 559 - CddEmmDomain29_CddEmmBit16FSIRHierarchyDSP2SCanAXibusErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250274UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 16, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 29 + }, + /* Index: 560 - CddEmmDomain29_CddEmmBit17FSIRHierarchyDSP3SCanAXibusErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250274UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 17, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 29 + }, + /* Index: 561 - CddEmmDomain29_CddEmmBit20FSIRHierarchyCNRAM0SCanAXibusErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250274UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 20, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 29 + }, + /* Index: 562 - */ +/* CddEmmDomain29_CddEmmBit21FSIRHierarchySlimdmac0SCanAXibusErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250274UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 21, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 29 + }, + /* Index: 563 - */ +/* CddEmmDomain29_CddEmmBit22FSIRHierarchySlimdmac1SCanAXibusErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250274UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 22, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 29 + }, + /* Index: 564 - CddEmmDomain30_CddEmmBit0FSSVCHierarchyIMR1SCanAXiBusErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250278UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 0, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 30 + }, + /* Index: 565 - CddEmmDomain30_CddEmmBit1FSSVCHierarchyIMR2SCanAXiBusErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250278UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 1, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 30 + }, + /* Index: 566 - CddEmmDomain30_CddEmmBit3FSSVCHierarchyIMS0SCanAXiBusErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250278UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 3, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 30 + }, + /* Index: 567 - CddEmmDomain30_CddEmmBit4FSSVCHierarchyIMS1SCanAXiBusErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250278UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 4, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 30 + }, + /* Index: 568 - CddEmmDomain30_CddEmmBit7FSSVIPHierarchyDULSCanAXiBusErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250278UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 7, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 30 + }, + /* Index: 569 - CddEmmDomain30_CddEmmBit9FSSVIPHierarchyUMFL0SCanAXiBusErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250278UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 9, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 30 + }, + /* Index: 570 - CddEmmDomain30_CddEmmBit11FSFSVIPHierarchySMPS0SCanAXibusErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250278UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 11, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 30 + }, + /* Index: 571 - CddEmmDomain30_CddEmmBit15FSFSVIPHierarchySMPO0SCanAXibusErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250278UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 15, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 30 + }, + /* Index: 572 - CddEmmDomain30_CddEmmBit17FSFSVIPHierarchy2CLE0SCanAXibusErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250278UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 17, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 30 + }, + /* Index: 573 - CddEmmDomain30_CddEmmBit18FSFSVIPHierarchy2CLE1SCanAXibusErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250278UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 18, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 30 + }, + /* Index: 574 - CddEmmDomain30_CddEmmBit21FSIRHierarchyIMP0SCanAXibusErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250278UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 21, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 30 + }, + /* Index: 575 - CddEmmDomain30_CddEmmBit22FSIRHierarchyIMP1SCanAXibusErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250278UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 22, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 30 + }, + /* Index: 576 - CddEmmDomain30_CddEmmBit23FSIRHierarchyIMP2SCanAXibusErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250278UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 23, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 30 + }, + /* Index: 577 - CddEmmDomain30_CddEmmBit24FSIRHierarchyIMP3SCanAXibusErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250278UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 24, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 30 + }, + /* Index: 578 - */ +/* CddEmmDomain30_CddEmmBit25FSIRHierarchyPSC0DMAC0RepeatSCanAXibusErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250278UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 25, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 30 + }, + /* Index: 579 - */ +/* CddEmmDomain30_CddEmmBit26FSIRHierarchyDMAC2DMAC1RepeatSCanAXibusErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250278UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 26, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 30 + }, + /* Index: 580 - CddEmmDomain30_CddEmmBit27FSIRHierarchyOCV0SCanAXibusErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250278UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 27, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 30 + }, + /* Index: 581 - CddEmmDomain30_CddEmmBit28FSIRHierarchyOCV1SCanAXibusErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250278UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 28, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 30 + }, + /* Index: 582 - CddEmmDomain30_CddEmmBit29FSIRHierarchyOCV2SCanAXibusErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250278UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 29, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 30 + }, + /* Index: 583 - CddEmmDomain30_CddEmmBit30FSIRHierarchyOCV3SCanAXibusErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250278UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 30, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 30 + }, + /* Index: 584 - */ +/* CddEmmDomain31_CddEmmBit9FSFSCPU0HierarchyCl0L3CacheSCanAXiBusErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE625027CUL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 9, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 31 + }, + /* Index: 585 - */ +/* CddEmmDomain31_CddEmmBit10FSFSCPU0HierarchyCl1L3CacheSCanAXiBusErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE625027CUL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 10, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 31 + }, + /* Index: 586 - */ +/* CddEmmDomain31_CddEmmBit11FSFSCPU0HierarchyCl0CPU0SCanAXiBusErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE625027CUL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 11, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 31 + }, + /* Index: 587 - */ +/* CddEmmDomain31_CddEmmBit12FSFSCPU0HierarchyCl0CPU1SCanAXiBusErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE625027CUL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 12, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 31 + }, + /* Index: 588 - */ +/* CddEmmDomain31_CddEmmBit13FSFSCPU0HierarchyCl1CPU0SCanAXiBusErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE625027CUL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 13, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 31 + }, + /* Index: 589 - */ +/* CddEmmDomain31_CddEmmBit14FSFSCPU0HierarchyCl1CPU1SCanAXiBusErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE625027CUL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 14, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 31 + }, + /* Index: 590 - CddEmmDomain31_CddEmmBit26FSFSVIOHierarchyISP0SCanAXiBusErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE625027CUL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 26, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 31 + }, + /* Index: 591 - CddEmmDomain31_CddEmmBit27FSFSVIOHierarchyISP1SCanAXiBusErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE625027CUL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 27, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 31 + }, + /* Index: 592 - CddEmmDomain31_CddEmmBit31FSFSVCHierarchyIMR0SCanAXiBusErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE625027CUL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 31, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 31 + }, + /* Index: 593 - CddEmmDomain32_CddEmmBit0RTCore1AXIMICorrectableErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250280UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 0, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 32 + }, + /* Index: 594 - CddEmmDomain32_CddEmmBit1RTCore1AXIMIFatalErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250280UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 1, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 32 + }, + /* Index: 595 - CddEmmDomain32_CddEmmBit2RTCore1AXIMITimeoutErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250280UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 2, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 32 + }, + /* Index: 596 - CddEmmDomain32_CddEmmBit3RTCore1AXISICorrectableErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250280UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 3, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 32 + }, + /* Index: 597 - CddEmmDomain32_CddEmmBit4RTCore1AXISIFatalErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250280UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 4, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 32 + }, + /* Index: 598 - CddEmmDomain32_CddEmmBit5RTCore1AXISILockstepComparator1Err */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250280UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 5, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 32 + }, + /* Index: 599 - CddEmmDomain32_CddEmmBit6RTCore1DataCacheErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250280UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 6, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 32 + }, + /* Index: 600 - */ +/* CddEmmDomain32_CddEmmBit7RTCore1EL1ControlledAbortExceptionErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250280UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 7, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 32 + }, + /* Index: 601 - */ +/* CddEmmDomain32_CddEmmBit8RTCore1EL2ControlledabortExceptionErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250280UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 8, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 32 + }, + /* Index: 602 - CddEmmDomain32_CddEmmBit9RTCore1SWRunInEL2UnlockTESTR1Err */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250280UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 9, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 32 + }, + /* Index: 603 - CddEmmDomain32_CddEmmBit10RTCore1AsynchronousTransferErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250280UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 10, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 32 + }, + /* Index: 604 - CddEmmDomain32_CddEmmBit11RTCore1InstructionCacheErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250280UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 11, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 32 + }, + /* Index: 605 - CddEmmDomain32_CddEmmBit12RTCore1CorrectableNotRecordedErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250280UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 12, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 32 + }, + /* Index: 606 - CddEmmDomain32_CddEmmBit13RTCore1FatalErrCannotRecorded */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250280UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 13, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 32 + }, + /* Index: 607 - CddEmmDomain32_CddEmmBit14RTCore1ProcessorLivelockErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250280UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 14, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 32 + }, + /* Index: 608 - CddEmmDomain32_CddEmmBit15RTCore1LongHypervisorInterruptErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250280UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 15, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 32 + }, + /* Index: 609 - CddEmmDomain32_CddEmmBit16RTCore1AXISILockstepComparator0Err */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250280UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 16, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 32 + }, + /* Index: 610 - CddEmmDomain32_CddEmmBit17RTCore1HypervisorModeFatalErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250280UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 17, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 32 + }, + /* Index: 611 - */ +/* CddEmmDomain32_CddEmmBit18RTCore1EL1controlledMemoryAccessErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250280UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 18, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 32 + }, + /* Index: 612 - CddEmmDomain32_CddEmmBit19RTCore1EDCBtwRTCPUWritebufferErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250280UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 19, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 32 + }, + /* Index: 613 - CddEmmDomain32_CddEmmBit20RTCore1AXIMIDECERRSLVERRBusErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250280UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 20, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 32 + }, + /* Index: 614 - */ +/* CddEmmDomain32_CddEmmBit21RTCore1NonSafetySwitchingComparator1Err */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250280UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 21, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 32 + }, + /* Index: 615 - */ +/* CddEmmDomain32_CddEmmBit22RTCore1NonSafetySwitchingComparator0Err */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250280UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 22, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 32 + }, + /* Index: 616 - CddEmmDomain32_CddEmmBit23RTCore1TCMCorrectableErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250280UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 23, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 32 + }, + /* Index: 617 - CddEmmDomain32_CddEmmBit24RTCore1TCMMemoriesFatalErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250280UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 24, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 32 + }, + /* Index: 618 - */ +/* CddEmmDomain32_CddEmmBit25RTCore1EDCBtwRTCPUAXISlavebridgeErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250280UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 25, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 32 + }, + /* Index: 619 - CddEmmDomain32_CddEmmBit26RTCore1IllegalAxSIZEAxBURSTErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250280UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 26, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 32 + }, + /* Index: 620 - CddEmmDomain32_CddEmmBit27RTCore1UndefinedExceptionErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250280UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 27, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 32 + }, + /* Index: 621 - CddEmmDomain32_CddEmmBit30CSI21Err */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250280UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 30, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 32 + }, + /* Index: 622 - CddEmmDomain32_CddEmmBit31CSI20Err */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250280UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 31, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 32 + }, + /* Index: 623 - CddEmmDomain33_CddEmmBit0RTCore2AXIMICorrectableErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250284UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 0, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 33 + }, + /* Index: 624 - CddEmmDomain33_CddEmmBit1RTCore2AXIMIFatalErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250284UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 1, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 33 + }, + /* Index: 625 - CddEmmDomain33_CddEmmBit2RTCore2AXIMITimeoutErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250284UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 2, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 33 + }, + /* Index: 626 - CddEmmDomain33_CddEmmBit3RTCore2AXISICorrectableErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250284UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 3, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 33 + }, + /* Index: 627 - CddEmmDomain33_CddEmmBit4RTCore2AXISIFatalErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250284UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 4, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 33 + }, + /* Index: 628 - CddEmmDomain33_CddEmmBit5RTCore2AXISILockstepComparator1Err */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250284UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 5, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 33 + }, + /* Index: 629 - CddEmmDomain33_CddEmmBit6RTCore2DataCacheErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250284UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 6, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 33 + }, + /* Index: 630 - */ +/* CddEmmDomain33_CddEmmBit7RTCore2EL1ControlledAbortExceptionErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250284UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 7, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 33 + }, + /* Index: 631 - */ +/* CddEmmDomain33_CddEmmBit8RTCore2EL2ControlledabortExceptionErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250284UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 8, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 33 + }, + /* Index: 632 - CddEmmDomain33_CddEmmBit9RTCore2SWRunInEL2UnlockTESTR1Err */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250284UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 9, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 33 + }, + /* Index: 633 - CddEmmDomain33_CddEmmBit10RTCore2AsynchronousTransferErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250284UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 10, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 33 + }, + /* Index: 634 - CddEmmDomain33_CddEmmBit11RTCore2InstructionCacheErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250284UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 11, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 33 + }, + /* Index: 635 - CddEmmDomain33_CddEmmBit12RTCore2CorrectableNotRecordedErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250284UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 12, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 33 + }, + /* Index: 636 - CddEmmDomain33_CddEmmBit13RTCore2FatalErrCannotRecorded */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250284UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 13, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 33 + }, + /* Index: 637 - CddEmmDomain33_CddEmmBit14RTCore2ProcessorLivelockErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250284UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 14, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 33 + }, + /* Index: 638 - CddEmmDomain33_CddEmmBit15RTCore2LongHypervisorInterruptErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250284UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 15, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 33 + }, + /* Index: 639 - CddEmmDomain33_CddEmmBit16RTCore2AXISILockstepComparator0Err */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250284UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 16, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 33 + }, + /* Index: 640 - CddEmmDomain33_CddEmmBit17RTCore2HypervisorModeFatalErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250284UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 17, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 33 + }, + /* Index: 641 - */ +/* CddEmmDomain33_CddEmmBit18RTCore2EL1controlledMemoryAccessErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250284UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 18, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 33 + }, + /* Index: 642 - CddEmmDomain33_CddEmmBit19RTCore2EDCBtwRTCPUWritebufferErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250284UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 19, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 33 + }, + /* Index: 643 - CddEmmDomain33_CddEmmBit20RTCore2AXIMIDECERRSLVERRBusErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250284UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 20, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 33 + }, + /* Index: 644 - */ +/* CddEmmDomain33_CddEmmBit21RTCore2NonSafetySwitchingComparator1Err */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250284UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 21, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 33 + }, + /* Index: 645 - */ +/* CddEmmDomain33_CddEmmBit22RTCore2NonSafetySwitchingComparator0Err */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250284UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 22, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 33 + }, + /* Index: 646 - CddEmmDomain33_CddEmmBit23RTCore2TCMCorrectableErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250284UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 23, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 33 + }, + /* Index: 647 - CddEmmDomain33_CddEmmBit24RTCore2TCMMemoriesFatalErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250284UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 24, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 33 + }, + /* Index: 648 - */ +/* CddEmmDomain33_CddEmmBit25RTCore2EDCBtwRTCPUAXISlavebridgeErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250284UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 25, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 33 + }, + /* Index: 649 - CddEmmDomain33_CddEmmBit26RTCore2IllegalAxSIZEAxBURSTErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250284UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 26, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 33 + }, + /* Index: 650 - CddEmmDomain33_CddEmmBit27RTCore2UndefinedExceptionErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250284UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 27, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 33 + }, + /* Index: 651 - CddEmmDomain34_CddEmmBit0PWMLoopbackFunctionErrch0 */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250288UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 0, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 34 + }, + /* Index: 652 - CddEmmDomain34_CddEmmBit1PWMLoopbackFunctionErrch1 */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250288UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 1, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 34 + }, + /* Index: 653 - CddEmmDomain34_CddEmmBit2PWMLoopbackFunctionErrch2 */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250288UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 2, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 34 + }, + /* Index: 654 - CddEmmDomain34_CddEmmBit3PWMLoopbackFunctionErrch3 */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250288UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 3, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 34 + }, + /* Index: 655 - CddEmmDomain34_CddEmmBit4PWMLoopbackFunctionErrch4 */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250288UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 4, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 34 + }, + /* Index: 656 - CddEmmDomain34_CddEmmBit5PWMLoopbackFunctionErrch5 */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250288UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 5, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 34 + }, + /* Index: 657 - CddEmmDomain34_CddEmmBit6PWMLoopbackFunctionErrch6 */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250288UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 6, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 34 + }, + /* Index: 658 - CddEmmDomain34_CddEmmBit7PWMLoopbackFunctionErrch7 */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250288UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 7, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 34 + }, + /* Index: 659 - CddEmmDomain34_CddEmmBit8PWMLoopbackFunctionErrch8 */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250288UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 8, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 34 + }, + /* Index: 660 - CddEmmDomain34_CddEmmBit9PWMLoopbackFunctionErrch9 */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250288UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 9, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 34 + }, + /* Index: 661 - */ +/* CddEmmDomain35_CddEmmBit6APSysApmuCA76Cl1PchProtocolInterfaceErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE625028CUL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 6, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 35 + }, + /* Index: 662 - */ +/* CddEmmDomain35_CddEmmBit7APSysApmuCA76Cl0PchProtocolInterfaceErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE625028CUL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 7, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 35 + }, + /* Index: 663 - */ +/* CddEmmDomain35_CddEmmBit8APSysAXI4StreambusINTAPCA76Cl1RequestOrderErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE625028CUL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 8, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 35 + }, + /* Index: 664 - */ +/* CddEmmDomain35_CddEmmBit9APSysAXI4StreambusINTAPCA76Cl0RequestOrderErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE625028CUL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 9, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 35 + }, + /* Index: 665 - */ +/* CddEmmDomain35_CddEmmBit10APSysAXI4StreambusINTAPCA76Cl1EdcErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE625028CUL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 10, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 35 + }, + /* Index: 666 - */ +/* CddEmmDomain35_CddEmmBit11APSysAXI4StreambusINTAPCA76Cl0EdcErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE625028CUL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 11, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 35 + }, + /* Index: 667 - */ +/* CddEmmDomain35_CddEmmBit12APSysArmgcCA76Cl1CounterInterfeceErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE625028CUL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 12, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 35 + }, + /* Index: 668 - */ +/* CddEmmDomain35_CddEmmBit13APSysArmgcCA76Cl0CounterInterfeceErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE625028CUL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 13, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 35 + }, + /* Index: 669 - */ +/* CddEmmDomain35_CddEmmBit14APSysCA76Core3L1IL1DL2MmuCorrectedErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE625028CUL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 14, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 35 + }, + /* Index: 670 - */ +/* CddEmmDomain35_CddEmmBit15APSysCA76Core2L1IL1DL2MmuCorrectedErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE625028CUL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 15, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 35 + }, + /* Index: 671 - CddEmmDomain35_CddEmmBit16APSysL3Cl1correctedErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE625028CUL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 16, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 35 + }, + /* Index: 672 - */ +/* CddEmmDomain35_CddEmmBit17APSysCA76Core1L1IL1DL2MmuCorrectedErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE625028CUL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 17, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 35 + }, + /* Index: 673 - */ +/* CddEmmDomain35_CddEmmBit18APSysCA76Core0L1IL1DL2MmuCorrectedErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE625028CUL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 18, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 35 + }, + /* Index: 674 - CddEmmDomain35_CddEmmBit19APSysL3Cl0correctedErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE625028CUL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 19, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 35 + }, + /* Index: 675 - */ +/* CddEmmDomain35_CddEmmBit20APSysCA76Core3L1IL1DL2MmuUncorrectedErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE625028CUL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 20, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 35 + }, + /* Index: 676 - */ +/* CddEmmDomain35_CddEmmBit21APSysCA76Core2L1IL1DL2MmuUncorrectedErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE625028CUL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 21, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 35 + }, + /* Index: 677 - CddEmmDomain35_CddEmmBit22APSysL3Cl1UncorrectedErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE625028CUL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 22, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 35 + }, + /* Index: 678 - */ +/* CddEmmDomain35_CddEmmBit23APSysCA76Core1L1IL1DL2MmuUncorrectedErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE625028CUL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 23, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 35 + }, + /* Index: 679 - */ +/* CddEmmDomain35_CddEmmBit24APSysCA76Core0L1IL1DL2MmuUncorrectedErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE625028CUL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 24, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 35 + }, + /* Index: 680 - CddEmmDomain35_CddEmmBit25APSysL3Cl0UncorrectedErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE625028CUL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 25, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 35 + }, + /* Index: 681 - CddEmmDomain35_CddEmmBit26APSysCA76Cl0RedundantErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE625028CUL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 26, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 35 + }, + /* Index: 682 - CddEmmDomain35_CddEmmBit27APSysCA76Cl0LockstepErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE625028CUL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 27, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 35 + }, + /* Index: 683 - */ +/* CddEmmDomain35_CddEmmBit28APSysAcebusCciCA76Cl1RequestOrderErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE625028CUL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 28, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 35 + }, + /* Index: 684 - */ +/* CddEmmDomain35_CddEmmBit29APSysAcebusCciCA76Cl0RequestOrderErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE625028CUL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 29, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 35 + }, + /* Index: 685 - CddEmmDomain35_CddEmmBit30APSysAcebusCciCA76Cl1EdcErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE625028CUL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 30, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 35 + }, + /* Index: 686 - CddEmmDomain35_CddEmmBit31APSysAcebusCciCA76Cl0EdcErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE625028CUL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 31, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 35 + }, + /* Index: 687 - CddEmmDomain36_CddEmmBit0VINCh15ModuleCombinedEdcErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250290UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 0, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 36 + }, + /* Index: 688 - CddEmmDomain36_CddEmmBit1VINCh15ModuleCombinedSafetyErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250290UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 1, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 36 + }, + /* Index: 689 - CddEmmDomain36_CddEmmBit2VINCh14ModuleCombinedEdcErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250290UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 2, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 36 + }, + /* Index: 690 - CddEmmDomain36_CddEmmBit3VINCh14ModuleCombinedSafetyErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250290UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 3, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 36 + }, + /* Index: 691 - CddEmmDomain36_CddEmmBit4VINCh13ModuleCombinedEdcErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250290UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 4, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 36 + }, + /* Index: 692 - CddEmmDomain36_CddEmmBit5VINCh13ModuleCombinedSafetyErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250290UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 5, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 36 + }, + /* Index: 693 - CddEmmDomain36_CddEmmBit6VINCh12ModuleCombinedEdcErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250290UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 6, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 36 + }, + /* Index: 694 - CddEmmDomain36_CddEmmBit7VINCh12ModuleCombinedSafetyErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250290UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 7, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 36 + }, + /* Index: 695 - CddEmmDomain36_CddEmmBit8VINCh11ModuleCombinedEdcErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250290UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 8, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 36 + }, + /* Index: 696 - CddEmmDomain36_CddEmmBit9VINCh11ModuleCombinedSafetyErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250290UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 9, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 36 + }, + /* Index: 697 - CddEmmDomain36_CddEmmBit10VINCh10ModuleCombinedEdcErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250290UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 10, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 36 + }, + /* Index: 698 - CddEmmDomain36_CddEmmBit11VINCh10ModuleCombinedSafetyErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250290UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 11, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 36 + }, + /* Index: 699 - CddEmmDomain36_CddEmmBit12VINCh9ModuleCombinedEdcErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250290UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 12, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 36 + }, + /* Index: 700 - CddEmmDomain36_CddEmmBit13VINCh9ModuleCombinedSafetyErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250290UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 13, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 36 + }, + /* Index: 701 - CddEmmDomain36_CddEmmBit14VINCh8ModuleCombinedEdcErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250290UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 14, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 36 + }, + /* Index: 702 - CddEmmDomain36_CddEmmBit15VINCh8ModuleCombinedSafetyErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250290UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 15, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 36 + }, + /* Index: 703 - CddEmmDomain36_CddEmmBit16VINCh7ModuleCombinedEdcErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250290UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 16, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 36 + }, + /* Index: 704 - CddEmmDomain36_CddEmmBit17VINCh7ModuleCombinedSafetyErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250290UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 17, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 36 + }, + /* Index: 705 - CddEmmDomain36_CddEmmBit18VINCh6ModuleCombinedEdcErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250290UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 18, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 36 + }, + /* Index: 706 - CddEmmDomain36_CddEmmBit19VINCh6ModuleCombinedSafetyErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250290UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 19, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 36 + }, + /* Index: 707 - CddEmmDomain36_CddEmmBit20VINCh5ModuleCombinedEdcErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250290UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 20, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 36 + }, + /* Index: 708 - CddEmmDomain36_CddEmmBit21VINCh5ModuleCombinedSafetyErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250290UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 21, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 36 + }, + /* Index: 709 - CddEmmDomain36_CddEmmBit22VINCh4ModuleCombinedEdcErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250290UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 22, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 36 + }, + /* Index: 710 - CddEmmDomain36_CddEmmBit23VINCh4ModuleCombinedSafetyErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250290UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 23, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 36 + }, + /* Index: 711 - CddEmmDomain36_CddEmmBit24VINCh3ModuleCombinedEdcErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250290UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 24, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 36 + }, + /* Index: 712 - CddEmmDomain36_CddEmmBit25VINCh3ModuleCombinedSafetyErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250290UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 25, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 36 + }, + /* Index: 713 - CddEmmDomain36_CddEmmBit26VINCh2ModuleCombinedEdcErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250290UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 26, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 36 + }, + /* Index: 714 - CddEmmDomain36_CddEmmBit27VINCh2ModuleCombinedSafetyErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250290UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 27, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 36 + }, + /* Index: 715 - CddEmmDomain36_CddEmmBit28VINCh1ModuleCombinedEdcErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250290UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 28, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 36 + }, + /* Index: 716 - CddEmmDomain36_CddEmmBit29VINCh1ModuleCombinedSafetyErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250290UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 29, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 36 + }, + /* Index: 717 - CddEmmDomain36_CddEmmBit30VINCh0ModuleCombinedEdcErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250290UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 30, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 36 + }, + /* Index: 718 - CddEmmDomain36_CddEmmBit31VINCh0ModuleCombinedSafetyErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250290UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 31, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 36 + }, + /* Index: 719 - CddEmmDomain38_CddEmmBit0CANFDRAMEcc1bitErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250298UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 0, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 38 + }, + /* Index: 720 - CddEmmDomain38_CddEmmBit1CANFDRAMEcc2bitErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250298UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 1, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 38 + }, + /* Index: 721 - */ +/* CddEmmDomain38_CddEmmBit2FLEXRAYTBF2InterruptNotificationEdcErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250298UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 2, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 38 + }, + /* Index: 722 - */ +/* CddEmmDomain38_CddEmmBit3FLEXRAYTBF2InterruptNotificationEccErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250298UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 3, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 38 + }, + /* Index: 723 - */ +/* CddEmmDomain38_CddEmmBit4FLEXRAYTBF1InterruptNotificationEdcErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250298UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 4, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 38 + }, + /* Index: 724 - */ +/* CddEmmDomain38_CddEmmBit5FLEXRAYTBF1InterruptNotificationEccErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250298UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 5, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 38 + }, + /* Index: 725 - */ +/* CddEmmDomain38_CddEmmBit6FLEXRAYMBFInterruptNotificationEdcErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250298UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 6, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 38 + }, + /* Index: 726 - */ +/* CddEmmDomain38_CddEmmBit7FLEXRAYMBFInterruptNotificationEccErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250298UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 7, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 38 + }, + /* Index: 727 - CddEmmDomain38_CddEmmBit20EtherAVB2TXRAMEccMultibitErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250298UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 20, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 38 + }, + /* Index: 728 - CddEmmDomain38_CddEmmBit21EtherAVB2RXRAMEccMultibitErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250298UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 21, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 38 + }, + /* Index: 729 - CddEmmDomain38_CddEmmBit22EtherAVB2TXRAMEcc1bitErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250298UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 22, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 38 + }, + /* Index: 730 - CddEmmDomain38_CddEmmBit23EtherAVB2RXRAMEcc1bitErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250298UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 23, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 38 + }, + /* Index: 731 - CddEmmDomain38_CddEmmBit24EtherAVB1TXRAMEccMultibitErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250298UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 24, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 38 + }, + /* Index: 732 - CddEmmDomain38_CddEmmBit25EtherAVB1RXRAMEccMultibitErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250298UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 25, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 38 + }, + /* Index: 733 - CddEmmDomain38_CddEmmBit26EtherAVB1TXRAMEcc1bitErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250298UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 26, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 38 + }, + /* Index: 734 - CddEmmDomain38_CddEmmBit27EtherAVB1RXRAMEcc1bitErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250298UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 27, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 38 + }, + /* Index: 735 - CddEmmDomain38_CddEmmBit28EtherAVB0TXRAMEccMultibitErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250298UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 28, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 38 + }, + /* Index: 736 - CddEmmDomain38_CddEmmBit29EtherAVB0RXRAMEccMultibitErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250298UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 29, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 38 + }, + /* Index: 737 - CddEmmDomain38_CddEmmBit30EtherAVB0TXRAMEcc1bitErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250298UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 30, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 38 + }, + /* Index: 738 - CddEmmDomain38_CddEmmBit31EtherAVB0RXRAMEcc1bitErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250298UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 31, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 38 + }, + /* Index: 739 - CddEmmDomain39_CddEmmBit16AXIBusECMRT2 */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE625029CUL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 16, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 39 + }, + /* Index: 740 - CddEmmDomain39_CddEmmBit17AXIBusECMRT1 */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE625029CUL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 17, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 39 + }, + /* Index: 741 - CddEmmDomain39_CddEmmBit18AXIBusECMRT3 */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE625029CUL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 18, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 39 + }, + /* Index: 742 - CddEmmDomain39_CddEmmBit19AXIBusECMTOP2 */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE625029CUL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 19, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 39 + }, + /* Index: 743 - CddEmmDomain39_CddEmmBit20AXIBusECMPER01 */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE625029CUL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 20, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 39 + }, + /* Index: 744 - CddEmmDomain39_CddEmmBit21AXIBusECMPER02 */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE625029CUL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 21, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 39 + }, + /* Index: 745 - CddEmmDomain39_CddEmmBit22AXIBusECMPER03 */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE625029CUL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 22, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 39 + }, + /* Index: 746 - CddEmmDomain39_CddEmmBit23AXIBusECMTOP1 */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE625029CUL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 23, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 39 + }, + /* Index: 747 - CddEmmDomain39_CddEmmBit24AXIBusECMTOP3 */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE625029CUL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 24, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 39 + }, + /* Index: 748 - CddEmmDomain39_CddEmmBit25AXIBusECMVC1 */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE625029CUL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 25, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 39 + }, + /* Index: 749 - CddEmmDomain39_CddEmmBit26AXIBusECMVIP1 */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE625029CUL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 26, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 39 + }, + /* Index: 750 - CddEmmDomain39_CddEmmBit27AXIBusECMVIO1 */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE625029CUL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 27, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 39 + }, + /* Index: 751 - CddEmmDomain39_CddEmmBit28AXIBusECMVIO2 */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE625029CUL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 28, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 39 + }, + /* Index: 752 - CddEmmDomain40_CddEmmBit0CPGCBFUSAGsxFreqErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE62502A0UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 0, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 40 + }, + /* Index: 753 - CddEmmDomain40_CddEmmBit1CPGCBFUSARTckmrtFreqErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE62502A0UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 1, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 40 + }, + /* Index: 754 - CddEmmDomain40_CddEmmBit2CPGCBFUSARTckmrtFreqErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE62502A0UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 2, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 40 + }, + /* Index: 755 - CddEmmDomain40_CddEmmBit3CPGCBFUSAPeripheralFreqErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE62502A0UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 3, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 40 + }, + /* Index: 756 - CddEmmDomain40_CddEmmBit4CPGCBFUSAHscFreqErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE62502A0UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 4, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 40 + }, + /* Index: 757 - CddEmmDomain40_CddEmmBit5CPGCBFUSAVioFreqErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE62502A0UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 5, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 40 + }, + /* Index: 758 - CddEmmDomain40_CddEmmBit6CPGCBFUSAVcFreqErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE62502A0UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 6, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 40 + }, + /* Index: 759 - CddEmmDomain40_CddEmmBit7CPGCBFUSAVipFreqErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE62502A0UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 7, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 40 + }, + /* Index: 760 - CddEmmDomain40_CddEmmBit8CPGCBFUSAIMPckmirFreqErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE62502A0UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 8, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 40 + }, + /* Index: 761 - CddEmmDomain40_CddEmmBit9CPGIMPckmcnrFreqErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE62502A0UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 9, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 40 + }, + /* Index: 762 - CddEmmDomain40_CddEmmBit10CPGCBFUSAIMPckmcnrFreqErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE62502A0UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 10, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 40 + }, + /* Index: 763 - CddEmmDomain40_CddEmmBit11CPGCBFUSAIMPckmdspFreqErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE62502A0UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 11, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 40 + }, + /* Index: 764 - CddEmmDomain40_CddEmmBit12CPGCBFUSAIMPckmdspFreqErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE62502A0UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 12, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 40 + }, + /* Index: 765 - CddEmmDomain40_CddEmmBit13CPGLCBFUSAMMFreqErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE62502A0UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 13, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 40 + }, + /* Index: 766 - CddEmmDomain40_CddEmmBit14CPGLCBFUSASlAccessBusFreqErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE62502A0UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 14, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 40 + }, + /* Index: 767 - CddEmmDomain40_CddEmmBit18EtherTSNRxDataSRAMEDCErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE62502A0UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 18, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 40 + }, + /* Index: 768 - CddEmmDomain40_CddEmmBit19EtherTSNRxCtrlSRAMEDCErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE62502A0UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 19, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 40 + }, + /* Index: 769 - CddEmmDomain40_CddEmmBit20EtherTSNTxDataSRAMEDCErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE62502A0UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 20, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 40 + }, + /* Index: 770 - CddEmmDomain40_CddEmmBit21EtherTSNTxCtrlSRAMEDCErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE62502A0UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 21, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 40 + }, + /* Index: 771 - CddEmmDomain40_CddEmmBit22EtherTSNTASCtrlListSRAMEDCErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE62502A0UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 22, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 40 + }, + /* Index: 772 - CddEmmDomain40_CddEmmBit23EtherTSNPSFPCtrlListSRAMEDCErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE62502A0UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 23, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 40 + }, + /* Index: 773 - */ +/* CddEmmDomain40_CddEmmBit24EtherTSNRxDescriptionrAdrrSRAMEDCErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE62502A0UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 24, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 40 + }, + /* Index: 774 - */ +/* CddEmmDomain40_CddEmmBit25EtherTSNTxDescriptionrAdrrSRAMEDCErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE62502A0UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 25, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 40 + }, + /* Index: 775 - CddEmmDomain40_CddEmmBit26EtherTSNTxBufferAdrrSRAMEDCErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE62502A0UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 26, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 40 + }, + /* Index: 776 - */ +/* CddEmmDomain40_CddEmmBit27EtherTSNRxEFrameBufferAdrrSRAMEDCErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE62502A0UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 27, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 40 + }, + /* Index: 777 - */ +/* CddEmmDomain40_CddEmmBit28EtherTSNRxPFrameBufferAdrrSRAMEDCErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE62502A0UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 28, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 40 + }, + /* Index: 778 - CddEmmDomain41_CddEmmBit0PAPeccErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE62502A4UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 0, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 41 + }, + /* Index: 779 - */ +/* CddEmmDomain41_CddEmmBit4OTPFfDClsApbRedundantComparatorComparisonErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE62502A4UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 4, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 41 + }, + /* Index: 780 - CddEmmDomain41_CddEmmBit5OTPEcc1bitCorrectedErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE62502A4UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 5, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 41 + }, + /* Index: 781 - CddEmmDomain41_CddEmmBit6OTPEccMultibitUncorrectedErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE62502A4UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 6, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 41 + }, + /* Index: 782 - */ +/* CddEmmDomain41_CddEmmBit7OTPTMRTripleModularRedundancy1bitCorrectedErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE62502A4UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 7, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 41 + }, + /* Index: 783 - CddEmmDomain41_CddEmmBit8OTPRedundantComparatorComparisonErr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE62502A4UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 8, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 41 + }, + /* Index: 784 - CddEmmDomain41_CddEmmBit9VDSPA2arbIntreqEcm */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE62502A4UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 9, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 41 + }, + /* Index: 785 - CddEmmDomain41_CddEmmBit10VDSP0ErrreqCorepmssUncorr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE62502A4UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 10, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 41 + }, + /* Index: 786 - CddEmmDomain41_CddEmmBit11VDSP0ErrreqCorepmssCorr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE62502A4UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 11, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 41 + }, + /* Index: 787 - CddEmmDomain41_CddEmmBit12VDSP0ErrreqDmssUncorr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE62502A4UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 12, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 41 + }, + /* Index: 788 - CddEmmDomain41_CddEmmBit13VDSP0ErrreqDmssCorr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE62502A4UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 13, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 41 + }, + /* Index: 789 - CddEmmDomain41_CddEmmBit14VDSP0ErrreqIrrecoverable */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE62502A4UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 14, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 41 + }, + /* Index: 790 - CddEmmDomain41_CddEmmBit16VDSP0ErrreqPreciseSafetyUncorr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE62502A4UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 16, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 41 + }, + /* Index: 791 - CddEmmDomain41_CddEmmBit17VDSP0ErrreqEppWdogViol */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE62502A4UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 17, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 41 + }, + /* Index: 792 - CddEmmDomain41_CddEmmBit18VDSP0ErrreqIopWdogViol */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE62502A4UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 18, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 41 + }, + /* Index: 793 - CddEmmDomain41_CddEmmBit19VDSP0ErrreqEdpWdogViol */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE62502A4UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 19, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 41 + }, + /* Index: 794 - CddEmmDomain41_CddEmmBit20VDSP0ErrreqAxim0WdogViol */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE62502A4UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 20, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 41 + }, + /* Index: 795 - CddEmmDomain41_CddEmmBit21VDSP0ErrreqSysWdInt */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE62502A4UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 21, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 41 + }, + /* Index: 796 - CddEmmDomain41_CddEmmBit22VDSP0ErrreqIcuWdogViol */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE62502A4UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 22, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 41 + }, + /* Index: 797 - CddEmmDomain41_CddEmmBit23VDSP1ErrreqCorepmssUncorr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE62502A4UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 23, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 41 + }, + /* Index: 798 - CddEmmDomain41_CddEmmBit24VDSP1ErrreqCorepmssCorr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE62502A4UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 24, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 41 + }, + /* Index: 799 - CddEmmDomain41_CddEmmBit25VDSP1ErrreqDmssUncorr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE62502A4UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 25, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 41 + }, + /* Index: 800 - CddEmmDomain41_CddEmmBit26VDSP1ErrreqDmssCorr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE62502A4UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 26, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 41 + }, + /* Index: 801 - CddEmmDomain41_CddEmmBit27VDSP1ErrreqIrrecoverable */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE62502A4UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 27, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 41 + }, + /* Index: 802 - CddEmmDomain41_CddEmmBit29VDSP1ErrreqPreciseSafetyUncorr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE62502A4UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 29, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 41 + }, + /* Index: 803 - CddEmmDomain41_CddEmmBit30VDSP1ErrreqEppWdogviol */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE62502A4UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 30, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 41 + }, + /* Index: 804 - CddEmmDomain41_CddEmmBit31VDSP1ErrreqIopWdogviol */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE62502A4UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 31, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 41 + }, + /* Index: 805 - CddEmmDomain42_CddEmmBit0VDSP1ErrreqEdpWdogViol */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE62502A8UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 0, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 42 + }, + /* Index: 806 - CddEmmDomain42_CddEmmBit1VDSP1ErrreqAxim0WdogViol */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE62502A8UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 1, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 42 + }, + /* Index: 807 - CddEmmDomain42_CddEmmBit2VDSP1ErrreqSysWdInt */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE62502A8UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 2, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 42 + }, + /* Index: 808 - CddEmmDomain42_CddEmmBit3VDSP1ErrreqIcuWdogViol */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE62502A8UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 3, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 42 + }, + /* Index: 809 - CddEmmDomain42_CddEmmBit4VDSP3ErrreqCorepmssUncorr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE62502A8UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 4, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 42 + }, + /* Index: 810 - CddEmmDomain42_CddEmmBit5VDSP3ErrreqCorepmssCorr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE62502A8UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 5, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 42 + }, + /* Index: 811 - CddEmmDomain42_CddEmmBit6VDSP3ErrreqDmssUncorr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE62502A8UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 6, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 42 + }, + /* Index: 812 - CddEmmDomain42_CddEmmBit7VDSP3ErrreqDmssCorr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE62502A8UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 7, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 42 + }, + /* Index: 813 - CddEmmDomain42_CddEmmBit8VDSP3ErrreqIrrecoverable */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE62502A8UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 8, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 42 + }, + /* Index: 814 - CddEmmDomain42_CddEmmBit10VDSP2ErrreqPreciseSafetyUncorr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE62502A8UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 10, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 42 + }, + /* Index: 815 - CddEmmDomain42_CddEmmBit11VDSP2ErrreqEppWdogViol */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE62502A8UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 11, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 42 + }, + /* Index: 816 - CddEmmDomain42_CddEmmBit12VDSP2ErrreqIopWdogViol */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE62502A8UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 12, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 42 + }, + /* Index: 817 - CddEmmDomain42_CddEmmBit13VDSP2ErrreqEdpWdogViol */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE62502A8UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 13, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 42 + }, + /* Index: 818 - CddEmmDomain42_CddEmmBit14VDSP2ErrreqAxim0WdogViol */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE62502A8UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 14, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 42 + }, + /* Index: 819 - CddEmmDomain42_CddEmmBit15VDSP2ErrreqSysWdInt */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE62502A8UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 15, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 42 + }, + /* Index: 820 - CddEmmDomain42_CddEmmBit16VDSP2ErrreqIcuWdogViol */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE62502A8UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 16, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 42 + }, + /* Index: 821 - CddEmmDomain42_CddEmmBit17VDSP3ErrreqCorepmssUncorr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE62502A8UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 17, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 42 + }, + /* Index: 822 - CddEmmDomain42_CddEmmBit18VDSP3ErrreqCorepmssCorr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE62502A8UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 18, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 42 + }, + /* Index: 823 - CddEmmDomain42_CddEmmBit19VDSP3ErrreqDmssUncorr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE62502A8UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 19, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 42 + }, + /* Index: 824 - CddEmmDomain42_CddEmmBit20VDSP3ErrreqDmssCorr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE62502A8UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 20, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 42 + }, + /* Index: 825 - CddEmmDomain42_CddEmmBit21VDSP3ErrreqIrrecoverable */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE62502A8UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 21, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 42 + }, + /* Index: 826 - CddEmmDomain42_CddEmmBit23VDSP3ErrreqPreciseSafetyUncorr */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE62502A8UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 23, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 42 + }, + /* Index: 827 - CddEmmDomain42_CddEmmBit24VDSP3ErrreqEppWdogViol */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE62502A8UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 24, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 42 + }, + /* Index: 828 - CddEmmDomain42_CddEmmBit25VDSP3ErrreqIopWdogViol */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE62502A8UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 25, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 42 + }, + /* Index: 829 - CddEmmDomain42_CddEmmBit26VDSP3ErrreqEdpWdogViol */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE62502A8UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 26, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 42 + }, + /* Index: 830 - CddEmmDomain42_CddEmmBit27VDSP3ErrreqAxim0WdogViol */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE62502A8UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 27, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 42 + }, + /* Index: 831 - CddEmmDomain42_CddEmmBit28VDSP3ErrreqSysWdInt */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE62502A8UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 28, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 42 + }, + /* Index: 832 - CddEmmDomain42_CddEmmBit29VDSP3ErrreqIcuWdogViol */ + { + /* *pErrTargetRegAddr */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE62502A8UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucErrorTargetBitNo */ + (VAR(uint8, TYPEDEF)) 29, + + /* *ucErrorStatusRegNo */ + (VAR(uint8, TYPEDEF)) 42 + } +}; +/* END Msg(1:1504)-4 */ + +/* Global array for error count initial setting structure */ +/* MISRA Violation: START Msg(1:1504)-4 */ +CONST(CddEmm_ErrorCountInitialSettingType, CDDEMM_CONFIG_DATA) + CddEmm_GstErrorCountInitialSetting[] = +{ + /* Index: 0 - CddEmmDomain10_CddEmmBit0APSysCciEccSedErrCounter */ + { + /* *pECMERRCNTRnReg */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250400UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucCountVal */ + (VAR(uint8, TYPEDEF)) 1, + + /* *enErrorCountType */ + (VAR(CddEmm_ErrorCountType, TYPEDEF)) CDDEMM_ERROR_1_BIT + }, + /* Index: 1 - CddEmmDomain10_CddEmmBit1APSysCciEccEdcErrCounter */ + { + /* *pECMERRCNTRnReg */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250400UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucCountVal */ + (VAR(uint8, TYPEDEF)) 1, + + /* *enErrorCountType */ + (VAR(CddEmm_ErrorCountType, TYPEDEF)) CDDEMM_ERROR_MULTI_BIT + }, + /* Index: 2 - CddEmmDomain10_CddEmmBit2RTVRAMRTVRAM0Edc1bitErr */ + { + /* *pECMERRCNTRnReg */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250404UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucCountVal */ + (VAR(uint8, TYPEDEF)) 1, + + /* *enErrorCountType */ + (VAR(CddEmm_ErrorCountType, TYPEDEF)) CDDEMM_ERROR_1_BIT + }, + /* Index: 3 - CddEmmDomain10_CddEmmBit3RTVRAMRTVRAM0EdcMulbitErr */ + { + /* *pECMERRCNTRnReg */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250404UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucCountVal */ + (VAR(uint8, TYPEDEF)) 1, + + /* *enErrorCountType */ + (VAR(CddEmm_ErrorCountType, TYPEDEF)) CDDEMM_ERROR_MULTI_BIT + }, + /* Index: 4 - CddEmmDomain10_CddEmmBit6RTCore0TCMCorrectableErrCounter */ + { + /* *pECMERRCNTRnReg */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE625040CUL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucCountVal */ + (VAR(uint8, TYPEDEF)) 1, + + /* *enErrorCountType */ + (VAR(CddEmm_ErrorCountType, TYPEDEF)) CDDEMM_ERROR_1_BIT + }, + /* Index: 5 - CddEmmDomain10_CddEmmBit8RTCore0InstructionCacheErrCounter */ + { + /* *pECMERRCNTRnReg */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250410UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucCountVal */ + (VAR(uint8, TYPEDEF)) 1, + + /* *enErrorCountType */ + (VAR(CddEmm_ErrorCountType, TYPEDEF)) CDDEMM_ERROR_1_BIT + }, + /* Index: 6 - CddEmmDomain10_CddEmmBit10RTCore0DataCacheErrCounter */ + { + /* *pECMERRCNTRnReg */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250414UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucCountVal */ + (VAR(uint8, TYPEDEF)) 1, + + /* *enErrorCountType */ + (VAR(CddEmm_ErrorCountType, TYPEDEF)) CDDEMM_ERROR_1_BIT + }, + /* Index: 7 - CddEmmDomain10_CddEmmBit12RTCore0AXISICorrectableErrCounter */ + { + /* *pECMERRCNTRnReg */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250418UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucCountVal */ + (VAR(uint8, TYPEDEF)) 1, + + /* *enErrorCountType */ + (VAR(CddEmm_ErrorCountType, TYPEDEF)) CDDEMM_ERROR_1_BIT + }, + /* Index: 8 - CddEmmDomain10_CddEmmBit14RTCore0AXIMICorrectableErrCounter */ + { + /* *pECMERRCNTRnReg */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE625041CUL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucCountVal */ + (VAR(uint8, TYPEDEF)) 1, + + /* *enErrorCountType */ + (VAR(CddEmm_ErrorCountType, TYPEDEF)) CDDEMM_ERROR_1_BIT + }, + /* Index: 9 - CddEmmDomain10_CddEmmBit16RTCore0ErrCounter */ + { + /* *pECMERRCNTRnReg */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250420UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucCountVal */ + (VAR(uint8, TYPEDEF)) 1, + + /* *enErrorCountType */ + (VAR(CddEmm_ErrorCountType, TYPEDEF)) CDDEMM_ERROR_1_BIT + }, + /* Index: 10 - CddEmmDomain10_CddEmmBit18RTVRAM1Edc1bitCountupErr */ + { + /* *pECMERRCNTRnReg */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250424UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucCountVal */ + (VAR(uint8, TYPEDEF)) 1, + + /* *enErrorCountType */ + (VAR(CddEmm_ErrorCountType, TYPEDEF)) CDDEMM_ERROR_1_BIT + }, + /* Index: 11 - CddEmmDomain10_CddEmmBit19RTVRAM1EdcMulbitErr */ + { + /* *pECMERRCNTRnReg */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250424UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucCountVal */ + (VAR(uint8, TYPEDEF)) 1, + + /* *enErrorCountType */ + (VAR(CddEmm_ErrorCountType, TYPEDEF)) CDDEMM_ERROR_MULTI_BIT + }, + /* Index: 12 - CddEmmDomain10_CddEmmBit20IPMMUmmTLBRAMEdc1bitCountupErr */ + { + /* *pECMERRCNTRnReg */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250428UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucCountVal */ + (VAR(uint8, TYPEDEF)) 1, + + /* *enErrorCountType */ + (VAR(CddEmm_ErrorCountType, TYPEDEF)) CDDEMM_ERROR_1_BIT + }, + /* Index: 13 - CddEmmDomain10_CddEmmBit21IPMMUmmTLBRAMEdcMultibitCountupErr */ + { + /* *pECMERRCNTRnReg */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250428UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucCountVal */ + (VAR(uint8, TYPEDEF)) 1, + + /* *enErrorCountType */ + (VAR(CddEmm_ErrorCountType, TYPEDEF)) CDDEMM_ERROR_MULTI_BIT + }, + /* Index: 14 - CddEmmDomain10_CddEmmBit22RTCore1AXIMICorrectableErrCounter */ + { + /* *pECMERRCNTRnReg */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE625042CUL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucCountVal */ + (VAR(uint8, TYPEDEF)) 1, + + /* *enErrorCountType */ + (VAR(CddEmm_ErrorCountType, TYPEDEF)) CDDEMM_ERROR_1_BIT + }, + /* Index: 15 - CddEmmDomain10_CddEmmBit24RTCore1AXISICorrectableErrCounter */ + { + /* *pECMERRCNTRnReg */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250430UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucCountVal */ + (VAR(uint8, TYPEDEF)) 1, + + /* *enErrorCountType */ + (VAR(CddEmm_ErrorCountType, TYPEDEF)) CDDEMM_ERROR_1_BIT + }, + /* Index: 16 - CddEmmDomain10_CddEmmBit26RTCore1DataCacheErrCounter */ + { + /* *pECMERRCNTRnReg */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250434UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucCountVal */ + (VAR(uint8, TYPEDEF)) 1, + + /* *enErrorCountType */ + (VAR(CddEmm_ErrorCountType, TYPEDEF)) CDDEMM_ERROR_1_BIT + }, + /* Index: 17 - CddEmmDomain10_CddEmmBit28RTCore1InstructionCacheErrCounter */ + { + /* *pECMERRCNTRnReg */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250438UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucCountVal */ + (VAR(uint8, TYPEDEF)) 1, + + /* *enErrorCountType */ + (VAR(CddEmm_ErrorCountType, TYPEDEF)) CDDEMM_ERROR_1_BIT + }, + /* Index: 18 - CddEmmDomain10_CddEmmBit30RTCore1ErrCounter */ + { + /* *pECMERRCNTRnReg */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE625043CUL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucCountVal */ + (VAR(uint8, TYPEDEF)) 1, + + /* *enErrorCountType */ + (VAR(CddEmm_ErrorCountType, TYPEDEF)) CDDEMM_ERROR_1_BIT + }, + /* Index: 19 - CddEmmDomain11_CddEmmBit0RTCore1TCMCorrectableErrCounter */ + { + /* *pECMERRCNTRnReg */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250440UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucCountVal */ + (VAR(uint8, TYPEDEF)) 1, + + /* *enErrorCountType */ + (VAR(CddEmm_ErrorCountType, TYPEDEF)) CDDEMM_ERROR_1_BIT + }, + /* Index: 20 - CddEmmDomain11_CddEmmBit2RTCore2AXIMICorrectableErrCounter */ + { + /* *pECMERRCNTRnReg */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250444UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucCountVal */ + (VAR(uint8, TYPEDEF)) 1, + + /* *enErrorCountType */ + (VAR(CddEmm_ErrorCountType, TYPEDEF)) CDDEMM_ERROR_1_BIT + }, + /* Index: 21 - CddEmmDomain11_CddEmmBit4RTCore2AXISICorrectableErrCounter */ + { + /* *pECMERRCNTRnReg */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250448UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucCountVal */ + (VAR(uint8, TYPEDEF)) 1, + + /* *enErrorCountType */ + (VAR(CddEmm_ErrorCountType, TYPEDEF)) CDDEMM_ERROR_1_BIT + }, + /* Index: 22 - CddEmmDomain11_CddEmmBit6RTCore2DataCacheErrCounter */ + { + /* *pECMERRCNTRnReg */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE625044CUL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucCountVal */ + (VAR(uint8, TYPEDEF)) 1, + + /* *enErrorCountType */ + (VAR(CddEmm_ErrorCountType, TYPEDEF)) CDDEMM_ERROR_1_BIT + }, + /* Index: 23 - CddEmmDomain11_CddEmmBit8RTCore2InstructionCacheErrCounter */ + { + /* *pECMERRCNTRnReg */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250450UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucCountVal */ + (VAR(uint8, TYPEDEF)) 1, + + /* *enErrorCountType */ + (VAR(CddEmm_ErrorCountType, TYPEDEF)) CDDEMM_ERROR_1_BIT + }, + /* Index: 24 - CddEmmDomain11_CddEmmBit10RTCore2ErrCounter */ + { + /* *pECMERRCNTRnReg */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250454UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucCountVal */ + (VAR(uint8, TYPEDEF)) 1, + + /* *enErrorCountType */ + (VAR(CddEmm_ErrorCountType, TYPEDEF)) CDDEMM_ERROR_1_BIT + }, + /* Index: 25 - CddEmmDomain11_CddEmmBit12RTCore2TCMCorrectableErrCounter */ + { + /* *pECMERRCNTRnReg */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250458UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucCountVal */ + (VAR(uint8, TYPEDEF)) 1, + + /* *enErrorCountType */ + (VAR(CddEmm_ErrorCountType, TYPEDEF)) CDDEMM_ERROR_1_BIT + }, + /* Index: 26 - */ +/* CddEmmDomain11_CddEmmBit18APSysCA76Core3L1IL1DL2MmuCorrectedErrCounter */ + { + /* *pECMERRCNTRnReg */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250464UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucCountVal */ + (VAR(uint8, TYPEDEF)) 1, + + /* *enErrorCountType */ + (VAR(CddEmm_ErrorCountType, TYPEDEF)) CDDEMM_ERROR_1_BIT + }, + /* Index: 27 - */ +/* CddEmmDomain11_CddEmmBit19APSysCA76Core3L1IL1DL2MmuUncorrectedErrCounter */ + { + /* *pECMERRCNTRnReg */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250464UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucCountVal */ + (VAR(uint8, TYPEDEF)) 1, + + /* *enErrorCountType */ + (VAR(CddEmm_ErrorCountType, TYPEDEF)) CDDEMM_ERROR_MULTI_BIT + }, + /* Index: 28 - */ +/* CddEmmDomain11_CddEmmBit20APSysCA76Core2L1IL1DL2MmuCorrectedErrCounter */ + { + /* *pECMERRCNTRnReg */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250468UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucCountVal */ + (VAR(uint8, TYPEDEF)) 1, + + /* *enErrorCountType */ + (VAR(CddEmm_ErrorCountType, TYPEDEF)) CDDEMM_ERROR_1_BIT + }, + /* Index: 29 - */ +/* CddEmmDomain11_CddEmmBit21APSysCA76Core2L1IL1DL2MmuUncorrectedErrCounter */ + { + /* *pECMERRCNTRnReg */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250468UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucCountVal */ + (VAR(uint8, TYPEDEF)) 1, + + /* *enErrorCountType */ + (VAR(CddEmm_ErrorCountType, TYPEDEF)) CDDEMM_ERROR_MULTI_BIT + }, + /* Index: 30 - CddEmmDomain11_CddEmmBit22APSysL3Cl1CorrectedErrCounter */ + { + /* *pECMERRCNTRnReg */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE625046CUL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucCountVal */ + (VAR(uint8, TYPEDEF)) 1, + + /* *enErrorCountType */ + (VAR(CddEmm_ErrorCountType, TYPEDEF)) CDDEMM_ERROR_1_BIT + }, + /* Index: 31 - CddEmmDomain11_CddEmmBit23APSysL3Cl1UnCorrectedErrCounter */ + { + /* *pECMERRCNTRnReg */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE625046CUL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucCountVal */ + (VAR(uint8, TYPEDEF)) 1, + + /* *enErrorCountType */ + (VAR(CddEmm_ErrorCountType, TYPEDEF)) CDDEMM_ERROR_MULTI_BIT + }, + /* Index: 32 - */ +/* CddEmmDomain11_CddEmmBit24APSysCA76Core1L1IL1DL2MmuCorrectedErrCounter */ + { + /* *pECMERRCNTRnReg */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250470UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucCountVal */ + (VAR(uint8, TYPEDEF)) 1, + + /* *enErrorCountType */ + (VAR(CddEmm_ErrorCountType, TYPEDEF)) CDDEMM_ERROR_1_BIT + }, + /* Index: 33 - */ +/* CddEmmDomain11_CddEmmBit25APSysCA76Core1L1IL1DL2MmuUncorrectedErrCounter */ + { + /* *pECMERRCNTRnReg */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250470UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucCountVal */ + (VAR(uint8, TYPEDEF)) 1, + + /* *enErrorCountType */ + (VAR(CddEmm_ErrorCountType, TYPEDEF)) CDDEMM_ERROR_MULTI_BIT + }, + /* Index: 34 - */ +/* CddEmmDomain11_CddEmmBit26APSysCA76Core0L1IL1DL2MmuCorrectedErrCounter */ + { + /* *pECMERRCNTRnReg */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250474UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucCountVal */ + (VAR(uint8, TYPEDEF)) 1, + + /* *enErrorCountType */ + (VAR(CddEmm_ErrorCountType, TYPEDEF)) CDDEMM_ERROR_1_BIT + }, + /* Index: 35 - */ +/* CddEmmDomain11_CddEmmBit27APSysCA76Core0L1IL1DL2MmuUncorrectedErrCounter */ + { + /* *pECMERRCNTRnReg */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250474UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucCountVal */ + (VAR(uint8, TYPEDEF)) 1, + + /* *enErrorCountType */ + (VAR(CddEmm_ErrorCountType, TYPEDEF)) CDDEMM_ERROR_MULTI_BIT + }, + /* Index: 36 - CddEmmDomain11_CddEmmBit28APSysL3Cl0correctedErrCounter */ + { + /* *pECMERRCNTRnReg */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250478UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucCountVal */ + (VAR(uint8, TYPEDEF)) 1, + + /* *enErrorCountType */ + (VAR(CddEmm_ErrorCountType, TYPEDEF)) CDDEMM_ERROR_1_BIT + }, + /* Index: 37 - CddEmmDomain11_CddEmmBit29APSysL3Cl0UncorrectedErrCounter */ + { + /* *pECMERRCNTRnReg */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250478UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucCountVal */ + (VAR(uint8, TYPEDEF)) 1, + + /* *enErrorCountType */ + (VAR(CddEmm_ErrorCountType, TYPEDEF)) CDDEMM_ERROR_MULTI_BIT + }, + /* Index: 38 - CddEmmDomain11_CddEmmBit30CANFDRAMEcc1bitErrCounter */ + { + /* *pECMERRCNTRnReg */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE625047CUL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucCountVal */ + (VAR(uint8, TYPEDEF)) 1, + + /* *enErrorCountType */ + (VAR(CddEmm_ErrorCountType, TYPEDEF)) CDDEMM_ERROR_1_BIT + }, + /* Index: 39 - CddEmmDomain11_CddEmmBit31CANFDRAMEcc2bitErrCounter */ + { + /* *pECMERRCNTRnReg */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE625047CUL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucCountVal */ + (VAR(uint8, TYPEDEF)) 1, + + /* *enErrorCountType */ + (VAR(CddEmm_ErrorCountType, TYPEDEF)) CDDEMM_ERROR_MULTI_BIT + }, + /* Index: 40 - */ +/* CddEmmDomain12_CddEmmBit0FLEXRAYTBF2InterruptNotificationEccErrCounter */ + { + /* *pECMERRCNTRnReg */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250480UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucCountVal */ + (VAR(uint8, TYPEDEF)) 1, + + /* *enErrorCountType */ + (VAR(CddEmm_ErrorCountType, TYPEDEF)) CDDEMM_ERROR_1_BIT + }, + /* Index: 41 - */ +/* CddEmmDomain12_CddEmmBit1FLEXRAYTBF2InterruptNotificationEdcErrCounter */ + { + /* *pECMERRCNTRnReg */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250480UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucCountVal */ + (VAR(uint8, TYPEDEF)) 1, + + /* *enErrorCountType */ + (VAR(CddEmm_ErrorCountType, TYPEDEF)) CDDEMM_ERROR_MULTI_BIT + }, + /* Index: 42 - */ +/* CddEmmDomain12_CddEmmBit2FLEXRAYTBF1InterruptNotificationEccErrCounter */ + { + /* *pECMERRCNTRnReg */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250484UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucCountVal */ + (VAR(uint8, TYPEDEF)) 1, + + /* *enErrorCountType */ + (VAR(CddEmm_ErrorCountType, TYPEDEF)) CDDEMM_ERROR_1_BIT + }, + /* Index: 43 - */ +/* CddEmmDomain12_CddEmmBit3FLEXRAYTBF1InterruptNotificationEdcErrCounter */ + { + /* *pECMERRCNTRnReg */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250484UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucCountVal */ + (VAR(uint8, TYPEDEF)) 1, + + /* *enErrorCountType */ + (VAR(CddEmm_ErrorCountType, TYPEDEF)) CDDEMM_ERROR_MULTI_BIT + }, + /* Index: 44 - */ +/* CddEmmDomain12_CddEmmBit4FLEXRAYMBFInterruptNotificationEccErrCounter */ + { + /* *pECMERRCNTRnReg */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250488UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucCountVal */ + (VAR(uint8, TYPEDEF)) 1, + + /* *enErrorCountType */ + (VAR(CddEmm_ErrorCountType, TYPEDEF)) CDDEMM_ERROR_1_BIT + }, + /* Index: 45 - */ +/* CddEmmDomain12_CddEmmBit5FLEXRAYMBFInterruptNotificationEdcErrCounter */ + { + /* *pECMERRCNTRnReg */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250488UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucCountVal */ + (VAR(uint8, TYPEDEF)) 1, + + /* *enErrorCountType */ + (VAR(CddEmm_ErrorCountType, TYPEDEF)) CDDEMM_ERROR_MULTI_BIT + }, + /* Index: 46 - CddEmmDomain12_CddEmmBit6EtherAVB2TXRAMEcc1bitErrCounter */ + { + /* *pECMERRCNTRnReg */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE625048CUL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucCountVal */ + (VAR(uint8, TYPEDEF)) 1, + + /* *enErrorCountType */ + (VAR(CddEmm_ErrorCountType, TYPEDEF)) CDDEMM_ERROR_1_BIT + }, + /* Index: 47 - CddEmmDomain12_CddEmmBit7EtherAVB2TXRAMEccMultibitErrCounter */ + { + /* *pECMERRCNTRnReg */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE625048CUL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucCountVal */ + (VAR(uint8, TYPEDEF)) 1, + + /* *enErrorCountType */ + (VAR(CddEmm_ErrorCountType, TYPEDEF)) CDDEMM_ERROR_MULTI_BIT + }, + /* Index: 48 - CddEmmDomain12_CddEmmBit8EtherAVB2RXRAMEcc1bitErrCounter */ + { + /* *pECMERRCNTRnReg */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250490UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucCountVal */ + (VAR(uint8, TYPEDEF)) 1, + + /* *enErrorCountType */ + (VAR(CddEmm_ErrorCountType, TYPEDEF)) CDDEMM_ERROR_1_BIT + }, + /* Index: 49 - CddEmmDomain12_CddEmmBit9EtherAVB2RXRAMEccMultibitErrCounter */ + { + /* *pECMERRCNTRnReg */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250490UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucCountVal */ + (VAR(uint8, TYPEDEF)) 1, + + /* *enErrorCountType */ + (VAR(CddEmm_ErrorCountType, TYPEDEF)) CDDEMM_ERROR_MULTI_BIT + }, + /* Index: 50 - CddEmmDomain12_CddEmmBit10EtherAVB1TXRAMEcc1bitErrCounter */ + { + /* *pECMERRCNTRnReg */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250494UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucCountVal */ + (VAR(uint8, TYPEDEF)) 1, + + /* *enErrorCountType */ + (VAR(CddEmm_ErrorCountType, TYPEDEF)) CDDEMM_ERROR_1_BIT + }, + /* Index: 51 - CddEmmDomain12_CddEmmBit11EtherAVB1TXRAMEccMultibitErrCounter */ + { + /* *pECMERRCNTRnReg */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250494UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucCountVal */ + (VAR(uint8, TYPEDEF)) 1, + + /* *enErrorCountType */ + (VAR(CddEmm_ErrorCountType, TYPEDEF)) CDDEMM_ERROR_MULTI_BIT + }, + /* Index: 52 - CddEmmDomain12_CddEmmBit12EtherAVB1RXRAMEcc1bitErrCounter */ + { + /* *pECMERRCNTRnReg */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250498UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucCountVal */ + (VAR(uint8, TYPEDEF)) 1, + + /* *enErrorCountType */ + (VAR(CddEmm_ErrorCountType, TYPEDEF)) CDDEMM_ERROR_1_BIT + }, + /* Index: 53 - CddEmmDomain12_CddEmmBit13EtherAVB1RXRAMEccMultibitErrCounter */ + { + /* *pECMERRCNTRnReg */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6250498UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucCountVal */ + (VAR(uint8, TYPEDEF)) 1, + + /* *enErrorCountType */ + (VAR(CddEmm_ErrorCountType, TYPEDEF)) CDDEMM_ERROR_MULTI_BIT + }, + /* Index: 54 - CddEmmDomain12_CddEmmBit14EtherAVB0TXRAMEcc1bitErrCounter */ + { + /* *pECMERRCNTRnReg */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE625049CUL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucCountVal */ + (VAR(uint8, TYPEDEF)) 1, + + /* *enErrorCountType */ + (VAR(CddEmm_ErrorCountType, TYPEDEF)) CDDEMM_ERROR_1_BIT + }, + /* Index: 55 - CddEmmDomain12_CddEmmBit15EtherAVB0TXRAMEccMultibitErrCounter */ + { + /* *pECMERRCNTRnReg */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE625049CUL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucCountVal */ + (VAR(uint8, TYPEDEF)) 1, + + /* *enErrorCountType */ + (VAR(CddEmm_ErrorCountType, TYPEDEF)) CDDEMM_ERROR_MULTI_BIT + }, + /* Index: 56 - CddEmmDomain12_CddEmmBit16EtherAVB0RXRAMEcc1bitErrCounter */ + { + /* *pECMERRCNTRnReg */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE62504A0UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucCountVal */ + (VAR(uint8, TYPEDEF)) 1, + + /* *enErrorCountType */ + (VAR(CddEmm_ErrorCountType, TYPEDEF)) CDDEMM_ERROR_1_BIT + }, + /* Index: 57 - CddEmmDomain12_CddEmmBit17EtherAVB0RXRAMEccMultibitErrCounter */ + { + /* *pECMERRCNTRnReg */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE62504A0UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucCountVal */ + (VAR(uint8, TYPEDEF)) 1, + + /* *enErrorCountType */ + (VAR(CddEmm_ErrorCountType, TYPEDEF)) CDDEMM_ERROR_MULTI_BIT + }, + /* Index: 58 - CddEmmDomain12_CddEmmBit18EtherTSNRxDataSRAMEDCErrCounter */ + { + /* *pECMERRCNTRnReg */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE62504A4UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucCountVal */ + (VAR(uint8, TYPEDEF)) 1, + + /* *enErrorCountType */ + (VAR(CddEmm_ErrorCountType, TYPEDEF)) CDDEMM_ERROR_1_BIT + }, + /* Index: 59 - CddEmmDomain12_CddEmmBit20EtherTSNRxCtrlSRAMEDCErrCounter */ + { + /* *pECMERRCNTRnReg */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE62504A8UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucCountVal */ + (VAR(uint8, TYPEDEF)) 1, + + /* *enErrorCountType */ + (VAR(CddEmm_ErrorCountType, TYPEDEF)) CDDEMM_ERROR_1_BIT + }, + /* Index: 60 - CddEmmDomain12_CddEmmBit22EtherTSNTxDataSRAMEDCErrCounter */ + { + /* *pECMERRCNTRnReg */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE62504ACUL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucCountVal */ + (VAR(uint8, TYPEDEF)) 1, + + /* *enErrorCountType */ + (VAR(CddEmm_ErrorCountType, TYPEDEF)) CDDEMM_ERROR_1_BIT + }, + /* Index: 61 - CddEmmDomain12_CddEmmBit24EtherTSNTxCtrlSRAMEDCErrCounter */ + { + /* *pECMERRCNTRnReg */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE62504B0UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucCountVal */ + (VAR(uint8, TYPEDEF)) 1, + + /* *enErrorCountType */ + (VAR(CddEmm_ErrorCountType, TYPEDEF)) CDDEMM_ERROR_1_BIT + }, + /* Index: 62 - */ +/* CddEmmDomain12_CddEmmBit26EtherTSNTASCtrlListSRAMEDCErrCounter */ + { + /* *pECMERRCNTRnReg */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE62504B4UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucCountVal */ + (VAR(uint8, TYPEDEF)) 1, + + /* *enErrorCountType */ + (VAR(CddEmm_ErrorCountType, TYPEDEF)) CDDEMM_ERROR_1_BIT + }, + /* Index: 63 - */ +/* CddEmmDomain12_CddEmmBit28EtherTSNPSFPCtrlListSRAMEDCErrCounter */ + { + /* *pECMERRCNTRnReg */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE62504B8UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucCountVal */ + (VAR(uint8, TYPEDEF)) 1, + + /* *enErrorCountType */ + (VAR(CddEmm_ErrorCountType, TYPEDEF)) CDDEMM_ERROR_1_BIT + }, + /* Index: 64 - */ +/* CddEmmDomain12_CddEmmBit30EtherTSNRxDescriptionrAdrrSRAMEDCErrCounter */ + { + /* *pECMERRCNTRnReg */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE62504BCUL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucCountVal */ + (VAR(uint8, TYPEDEF)) 1, + + /* *enErrorCountType */ + (VAR(CddEmm_ErrorCountType, TYPEDEF)) CDDEMM_ERROR_1_BIT + }, + /* Index: 65 - */ +/* CddEmmDomain13_CddEmmBit0EtherTSNTxDescriptionrAdrrSRAMEDCErrCounter */ + { + /* *pECMERRCNTRnReg */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE62504C0UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucCountVal */ + (VAR(uint8, TYPEDEF)) 1, + + /* *enErrorCountType */ + (VAR(CddEmm_ErrorCountType, TYPEDEF)) CDDEMM_ERROR_1_BIT + }, + /* Index: 66 - */ +/* CddEmmDomain13_CddEmmBit2EtherTSNTxBufferAdrrSRAMEDCErrCounter */ + { + /* *pECMERRCNTRnReg */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE62504C4UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucCountVal */ + (VAR(uint8, TYPEDEF)) 1, + + /* *enErrorCountType */ + (VAR(CddEmm_ErrorCountType, TYPEDEF)) CDDEMM_ERROR_1_BIT + }, + /* Index: 67 - */ +/* CddEmmDomain13_CddEmmBit4EtherTSNRxEFrameBufferAdrrSRAMEDCErrCounter */ + { + /* *pECMERRCNTRnReg */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE62504C8UL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucCountVal */ + (VAR(uint8, TYPEDEF)) 1, + + /* *enErrorCountType */ + (VAR(CddEmm_ErrorCountType, TYPEDEF)) CDDEMM_ERROR_1_BIT + }, + /* Index: 68 - */ +/* CddEmmDomain13_CddEmmBit6EtherTSNRxPFrameBufferAdrrSRAMEDCErrCounter */ + { + /* *pECMERRCNTRnReg */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-3 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE62504CCUL, + /* END Msg(2:3432)-3 */ + /* END Msg(2:0306)-1 */ + + /* *ucCountVal */ + (VAR(uint8, TYPEDEF)) 1, + + /* *enErrorCountType */ + (VAR(CddEmm_ErrorCountType, TYPEDEF)) CDDEMM_ERROR_1_BIT + } +}; +/* END Msg(1:1504)-4 */ + +#define CDDEMM_STOP_SEC_CONFIG_DATA_32 +/* MISRA Violation : START Msg(4:5087)-3 */ +#include "CddEmm_MemMap.h" +/* END Msg(4:5087)-3 */ + + + +/******************************************************************************* +** Function Definitions ** +*******************************************************************************/ + +/******************************************************************************* +** End of File ** +*******************************************************************************/ + diff --git a/Src/Gen4_R-Car_MCAL/2_Trunk/V4H/MCAL-v4h_19.4.0.D_release/rel/modules/cddiccom/sample_application/V4H/19_11/include/CDD_Iccom_Cbk.h b/Src/Gen4_R-Car_MCAL/2_Trunk/V4H/MCAL-v4h_19.4.0.D_release/rel/modules/cddiccom/sample_application/V4H/19_11/include/CDD_Iccom_Cbk.h new file mode 100644 index 00000000..c4a471fd --- /dev/null +++ b/Src/Gen4_R-Car_MCAL/2_Trunk/V4H/MCAL-v4h_19.4.0.D_release/rel/modules/cddiccom/sample_application/V4H/19_11/include/CDD_Iccom_Cbk.h @@ -0,0 +1,158 @@ +/*============================================================================*/ +/* Project = AUTOSAR Renesas MCAL Components */ +/* Module = CDD_Iccom_Cbk.h */ +/*============================================================================*/ +/* COPYRIGHT */ +/*============================================================================*/ +/* Copyright(c) 2026 Renesas Electronics Corporation. */ +/*============================================================================*/ +/* Purpose: */ +/* This file contains call-back functions declaration */ +/* AUTOMATICALLY GENERATED FILE - DO NOT EDIT */ +/* */ +/*============================================================================*/ +/* */ +/* Unless otherwise agreed upon in writing between your company and */ +/* Renesas Electronics Corporation the following shall apply! */ +/* */ +/* Warranty Disclaimer */ +/* */ +/* There is no warranty of any kind whatsoever granted by Renesas. Any */ +/* warranty is expressly disclaimed and excluded by Renesas, either expressed */ +/* or implied, including but not limited to those for non-infringement of */ +/* intellectual property, merchantability and/or fitness for the particular */ +/* purpose. */ +/* */ +/* Renesas shall not have any obligation to maintain, service or provide bug */ +/* fixes for the supplied Product(s) and/or the Application. */ +/* */ +/* Each User is solely responsible for determining the appropriateness of */ +/* using the Product(s) and assumes all risks associated with its exercise */ +/* of rights under this Agreement, including, but not limited to the risks */ +/* and costs of program errors, compliance with applicable laws, damage to */ +/* or loss of data, programs or equipment, and unavailability or */ +/* interruption of operations. */ +/* */ +/* Limitation of Liability */ +/* */ +/* In no event shall Renesas be liable to the User for any incidental, */ +/* consequential, indirect, or punitive damage (including but not limited */ +/* to lost profits) regardless of whether such liability is based on breach */ +/* of contract, tort, strict liability, breach of warranties, failure of */ +/* essential purpose or otherwise and even if advised of the possibility of */ +/* such damages. Renesas shall not be liable for any services or products */ +/* provided by third party vendors, developers or consultants identified or */ +/* referred to the User by Renesas in connection with the Product(s) and/or */ +/* the Application. */ +/* */ +/*============================================================================*/ +/* Environment: */ +/* Devices: V4H */ +/*============================================================================*/ + + +/******************************************************************************* +** Revision Control History ** +*******************************************************************************/ + + + +/******************************************************************************* +** Generation Tool Version ** +*******************************************************************************/ +/* */ +/* TOOL VERSION: CddIccomRCAR.dll version: 1.0.10, MCALConfGen.exe version: 1.2.3 */ +/* */ + + +/******************************************************************************* +** Input File ** +*******************************************************************************/ +/* + * INPUT FILE: C:\Work\Src\Gen4_R-Car_MCAL\2_Trunk\V4H\MCAL-v4h_19.4.0.D_release\rel\modules\cddiccom\sample_application\V4H\19_11\config\App_CDD_ICCOM_V4H_Sample.arxml + * C:\Work\Src\Gen4_R-Car_MCAL\2_Trunk\V4H\MCAL-v4h_19.4.0.D_release\rel\modules\cddiccom\generator\V4H\R1911_CDD_ICCOM_V4H_BSWMDT.arxml + * C:\Work\Src\Gen4_R-Car_MCAL\2_Trunk\V4H\MCAL-v4h_19.4.0.D_release\rel\common\generic\stubs\19_11\Dem\xml\Dem_CDD_Iccom.arxml + * C:\Work\Src\Gen4_R-Car_MCAL\2_Trunk\V4H\MCAL-v4h_19.4.0.D_release\rel\common\generic\stubs\19_11\Os\xml\Os_CDD_Iccom.arxml + * C:\Work\Src\Gen4_R-Car_MCAL\2_Trunk\V4H\MCAL-v4h_19.4.0.D_release\rel\V4H\common_family\generator\arm\Sample_Application_V4H.trxml + * GENERATED ON: 19 6 2026 - 05:11:57 + */ + + +#ifndef CDD_ICCOM_CBK_H +#define CDD_ICCOM_CBK_H + + +/******************************************************************************* +** Include Section ** +*******************************************************************************/ + +/******************************************************************************* +** Version Information ** +*******************************************************************************/ +#define CDDICCOM_CBK_AR_RELEASE_MAJOR_VERSION 4U +#define CDDICCOM_CBK_AR_RELEASE_MINOR_VERSION 5U +#define CDDICCOM_CBK_AR_RELEASE_REVISION_VERSION 0U +#define CDDICCOM_CBK_SW_MAJOR_VERSION 1U +#define CDDICCOM_CBK_SW_MINOR_VERSION 1U + +/******************************************************************************* +** Global Symbols ** +*******************************************************************************/ + + + +/******************************************************************************* +** Global Data Types ** +*******************************************************************************/ + + + +/******************************************************************************* +** Global Data ** +*******************************************************************************/ + + + +/******************************************************************************* +** Function Prototypes ** +*******************************************************************************/ + + +#define CddIccom_START_SEC_CODE +#include "CddIccom_MemMap.h" + +extern FUNC(void, CddIccom_CODE) CddIccom_Ch0NoticeCallback +( + IccomNoticeType LenType, + uint32 LulMsg +); + +extern FUNC(void, CddIccom_CODE) CddIccom_Ch1NoticeCallback +( + IccomNoticeType LenType, + uint32 LulMsg +); + +extern FUNC(void, CddIccom_CODE) CddIccom_Ch2NoticeCallback +( + IccomNoticeType LenType, + uint32 LulMsg +); + +extern FUNC(void, CddIccom_CODE) CddIccom_Ch3NoticeCallback +( + IccomNoticeType LenType, + uint32 LulMsg +); + +#define CddIccom_STOP_SEC_CODE +#include "CddIccom_MemMap.h" + + +#endif /* CDD_ICCOM_CBK_H */ + + +/******************************************************************************* +** End of File ** +*******************************************************************************/ + diff --git a/Src/Gen4_R-Car_MCAL/2_Trunk/V4H/MCAL-v4h_19.4.0.D_release/rel/modules/cddiccom/sample_application/V4H/19_11/include/CDD_Iccom_Cfg.h b/Src/Gen4_R-Car_MCAL/2_Trunk/V4H/MCAL-v4h_19.4.0.D_release/rel/modules/cddiccom/sample_application/V4H/19_11/include/CDD_Iccom_Cfg.h new file mode 100644 index 00000000..bcd3c898 --- /dev/null +++ b/Src/Gen4_R-Car_MCAL/2_Trunk/V4H/MCAL-v4h_19.4.0.D_release/rel/modules/cddiccom/sample_application/V4H/19_11/include/CDD_Iccom_Cfg.h @@ -0,0 +1,274 @@ +/*============================================================================*/ +/* Project = AUTOSAR Renesas MCAL Components */ +/* Module = CDD_Iccom_Cfg.h */ +/*============================================================================*/ +/* COPYRIGHT */ +/*============================================================================*/ +/* Copyright(c) 2026 Renesas Electronics Corporation. */ +/*============================================================================*/ +/* Purpose: */ +/* This file contains pre-compile time parameters */ +/* AUTOMATICALLY GENERATED FILE - DO NOT EDIT */ +/* */ +/*============================================================================*/ +/* */ +/* Unless otherwise agreed upon in writing between your company and */ +/* Renesas Electronics Corporation the following shall apply! */ +/* */ +/* Warranty Disclaimer */ +/* */ +/* There is no warranty of any kind whatsoever granted by Renesas. Any */ +/* warranty is expressly disclaimed and excluded by Renesas, either expressed */ +/* or implied, including but not limited to those for non-infringement of */ +/* intellectual property, merchantability and/or fitness for the particular */ +/* purpose. */ +/* */ +/* Renesas shall not have any obligation to maintain, service or provide bug */ +/* fixes for the supplied Product(s) and/or the Application. */ +/* */ +/* Each User is solely responsible for determining the appropriateness of */ +/* using the Product(s) and assumes all risks associated with its exercise */ +/* of rights under this Agreement, including, but not limited to the risks */ +/* and costs of program errors, compliance with applicable laws, damage to */ +/* or loss of data, programs or equipment, and unavailability or */ +/* interruption of operations. */ +/* */ +/* Limitation of Liability */ +/* */ +/* In no event shall Renesas be liable to the User for any incidental, */ +/* consequential, indirect, or punitive damage (including but not limited */ +/* to lost profits) regardless of whether such liability is based on breach */ +/* of contract, tort, strict liability, breach of warranties, failure of */ +/* essential purpose or otherwise and even if advised of the possibility of */ +/* such damages. Renesas shall not be liable for any services or products */ +/* provided by third party vendors, developers or consultants identified or */ +/* referred to the User by Renesas in connection with the Product(s) and/or */ +/* the Application. */ +/* */ +/*============================================================================*/ +/* Environment: */ +/* Devices: V4H */ +/*============================================================================*/ + + +/******************************************************************************* +** Revision Control History ** +*******************************************************************************/ + + + +/******************************************************************************* +** Generation Tool Version ** +*******************************************************************************/ +/* */ +/* TOOL VERSION: CddIccomRCAR.dll version: 1.0.10, MCALConfGen.exe version: 1.2.3 */ +/* */ + + +/******************************************************************************* +** Input File ** +*******************************************************************************/ +/* + * INPUT FILE: C:\Work\Src\Gen4_R-Car_MCAL\2_Trunk\V4H\MCAL-v4h_19.4.0.D_release\rel\modules\cddiccom\sample_application\V4H\19_11\config\App_CDD_ICCOM_V4H_Sample.arxml + * C:\Work\Src\Gen4_R-Car_MCAL\2_Trunk\V4H\MCAL-v4h_19.4.0.D_release\rel\modules\cddiccom\generator\V4H\R1911_CDD_ICCOM_V4H_BSWMDT.arxml + * C:\Work\Src\Gen4_R-Car_MCAL\2_Trunk\V4H\MCAL-v4h_19.4.0.D_release\rel\common\generic\stubs\19_11\Dem\xml\Dem_CDD_Iccom.arxml + * C:\Work\Src\Gen4_R-Car_MCAL\2_Trunk\V4H\MCAL-v4h_19.4.0.D_release\rel\common\generic\stubs\19_11\Os\xml\Os_CDD_Iccom.arxml + * C:\Work\Src\Gen4_R-Car_MCAL\2_Trunk\V4H\MCAL-v4h_19.4.0.D_release\rel\V4H\common_family\generator\arm\Sample_Application_V4H.trxml + * GENERATED ON: 19 6 2026 - 05:11:57 + */ + + +#ifndef CDD_ICCOM_CFG_H +#define CDD_ICCOM_CFG_H + + +/******************************************************************************* +** Include Section ** +*******************************************************************************/ + +/******************************************************************************* +** MISRA C Rule Violations ** +*******************************************************************************/ +/* 1. MISRA C RULE VIOLATION: */ +/* Message : (7:0791) [U] Macro identifier does not differ from */ +/* other macro identifier(s) (e.g. '%s') within the */ +/* specified number of significant characters. */ +/* Rule : MISRA C:2012 Rule-5.4 */ +/* REFERENCE - ISO:C90-6.1.2 Identifiers - Implementation */ +/* Limits. */ +/* Justification : This macro identifier is following AUTOSAR standard rule */ +/* (Symbolic Name or Published Macro's name), */ +/* so this is accepted. */ +/* Verification : However, part of the code is verified manually */ +/* and it is not having any impact. */ +/* Reference : Look for START Msg(7:0791)-1 and */ +/* END Msg(7:0791)-1 tags in the code. */ +/******************************************************************************/ + + +/******************************************************************************* +** Version Information ** +*******************************************************************************/ +#define CDDICCOM_CFG_AR_RELEASE_MAJOR_VERSION 4U +#define CDDICCOM_CFG_AR_RELEASE_MINOR_VERSION 5U +#define CDDICCOM_CFG_AR_RELEASE_REVISION_VERSION 0U +#define CDDICCOM_CFG_SW_MAJOR_VERSION 1U +#define CDDICCOM_CFG_SW_MINOR_VERSION 1U + +/******************************************************************************* +** Common Published Information ** +*******************************************************************************/ +#define CDDICCOM_AR_RELEASE_MAJOR_VERSION_VALUE 4U +#define CDDICCOM_AR_RELEASE_MINOR_VERSION_VALUE 5U +#define CDDICCOM_AR_RELEASE_REVISION_VERSION_VALUE 0U +#define CDDICCOM_SW_MAJOR_VERSION_VALUE 1U +#define CDDICCOM_SW_MINOR_VERSION_VALUE 1U +#define CDDICCOM_SW_PATCH_VERSION_VALUE 9U +#define CDDICCOM_VENDOR_ID_VALUE 59U +#define CDDICCOM_MODULE_ID_VALUE 255U + +/******************************************************************************* +** Global Symbols ** +*******************************************************************************/ + + +/* Pre-compile option for Already Init Check */ +#define CDDICCOM_ALREADY_INIT_DET_CHECK STD_ON + +/* Pre-compile option for Critical Section */ +#define CDDICCOM_CRITICAL_SECTION_PROTECTION STD_ON + +/* Pre-compile option for Development Error Detect */ +#define CDDICCOM_DEV_ERROR_DETECT STD_OFF + +/* Pre-compile option for Write Verify Check Error Report */ +#define CDDICCOM_WRITE_VERIFY_CHECK STD_ON + +/* Pre-compile option for Dependencies Version Check */ +#define CDDICCOM_VERSION_CHECK_EXT_MODULES STD_ON + +/* Pre-compile option for Interrupt Consistency Check */ +#define CDDICCOM_INTERRUPT_CONSISTENCY_CHECK STD_OFF + +/* Pre-compile option for Unintended Interrupt Check */ +#define CDDICCOM_UNINTENDED_INTERRUPT_CHECK STD_ON + +/* Pre-compile option for Initialization Notification */ +#define CDDICCOM_INIT_NOTIFICATION STD_OFF + +/* Pre-compile option for Version Info API */ +#define CDDICCOM_VERSION_INFO_API STD_ON + +/* Pre-compile option for DEM Fatal Error Event */ +#define CDDICCOM_E_FATAL \ + DemConf_DemEventParameter_CDDICCOM_E_FATAL + +/* Pre-compile option for DEM Init Negotiation Error Event */ +#define CDDICCOM_E_INIT_NEGOTIATION \ + DemConf_DemEventParameter_CDDICCOM_E_INIT_NEGOTIATION + +/* Pre-compile option for DEM Time-Out Error Event */ +#define CDDICCOM_E_TIMEOUT \ + DemConf_DemEventParameter_CDDICCOM_E_TIMEOUT + +/* Pre-compile option for DEM Write Verify Check Error Event */ +#define CDDICCOM_E_WRITE_VERIFY_FAILURE \ + DemConf_DemEventParameter_CDDICCOM_E_WRITE_VERIFY_FAILURE + +/* Pre-compile option for DEM Invalid Ack Event */ +#define CDDICCOM_E_INVALID_ACK \ + DemConf_DemEventParameter_CDDICCOM_E_INVALID_ACK + +/* Pre-compile option for DEM Unintended Interrupt Check Error Event */ +#define CDDICCOM_E_INTERRUPT_CONTROLLER_FAILURE \ + DemConf_DemEventParameter_CDDICCOM_E_INTERRUPT_CONTROLLER_FAILURE + +/* Pre-compile option for Instance ID of the CDDICCOM Driver */ +#define CDDICCOM_INSTANCE_ID_VALUE 0U + +/* Total number of Configured Channels */ +#define CDDICCOM_TOTAL_CHANNELS_CONFIG 4U + +/* The order cores of CR52 */ +#define CDDICCOM_CR_NUMBER 0U + +/* Supported Device Name */ +#define CDDICCOM_DEVICE_NAME CDDICCOM_V4H + +/* CDDICCOM Channel Selection */ +#define CDDICCOM_CH0_USED STD_ON +#define CDDICCOM_CH1_USED STD_ON +#define CDDICCOM_CH2_USED STD_ON +#define CDDICCOM_CH3_USED STD_ON +#define CDDICCOM_CH4_USED STD_OFF +#define CDDICCOM_CH5_USED STD_OFF +#define CDDICCOM_CH6_USED STD_OFF +#define CDDICCOM_CH7_USED STD_OFF +#define CDDICCOM_CH8_USED STD_OFF +#define CDDICCOM_CH9_USED STD_OFF + +/* MFIS Channel Selection */ +#define CDDICCOM_AP_MFIS0_USED STD_ON +#define CDDICCOM_AP_MFIS1_USED STD_ON +#define CDDICCOM_AP_MFIS2_USED STD_ON +#define CDDICCOM_AP_MFIS3_USED STD_ON +#define CDDICCOM_AP_MFIS4_USED STD_OFF +#define CDDICCOM_AP_MFIS5_USED STD_OFF +#define CDDICCOM_AP_MFIS6_USED STD_OFF +#define CDDICCOM_AP_MFIS7_USED STD_OFF +#define CDDICCOM_CR_G4MH_MFIS0_USED STD_OFF +#define CDDICCOM_CR_G4MH_MFIS1_USED STD_OFF + +/* MFIS Channel Mapping */ +#define CDDICCOM_AP_MFIS0_CHANNEL (CddIccom_ChannelType)0U +#define CDDICCOM_AP_MFIS1_CHANNEL (CddIccom_ChannelType)1U +#define CDDICCOM_AP_MFIS2_CHANNEL (CddIccom_ChannelType)2U +#define CDDICCOM_AP_MFIS3_CHANNEL (CddIccom_ChannelType)3U + +/* CDDICCOM Channel Mapping Handles */ +#define CDDICCOM_CH0 (CddIccom_ChannelType)0U +#define CDDICCOM_CH1 (CddIccom_ChannelType)1U +#define CDDICCOM_CH2 (CddIccom_ChannelType)2U +#define CDDICCOM_CH3 (CddIccom_ChannelType)3U + +/* Channel Handles */ +#define CddIccomConf_CddIccomChannel_CddIccomChannel_000 \ + (CddIccom_ChannelType)0x00U +/* MISRA Violation: START Msg(7:0791)-1 */ +#define CddIccomConf_CddIccomChannel_CddIccomChannel_001 \ + (CddIccom_ChannelType)0x01U +/* END Msg(7:0791)-1 */ +/* MISRA Violation: START Msg(7:0791)-1 */ +#define CddIccomConf_CddIccomChannel_CddIccomChannel_002 \ + (CddIccom_ChannelType)0x02U +/* END Msg(7:0791)-1 */ +/* MISRA Violation: START Msg(7:0791)-1 */ +#define CddIccomConf_CddIccomChannel_CddIccomChannel_003 \ + (CddIccom_ChannelType)0x03U +/* END Msg(7:0791)-1 */ + +/******************************************************************************* +** Global Data Types ** +*******************************************************************************/ + + + +/******************************************************************************* +** Global Data ** +*******************************************************************************/ + + + +/******************************************************************************* +** Function Prototypes ** +*******************************************************************************/ + + + +#endif /* CDD_ICCOM_CFG_H */ + + +/******************************************************************************* +** End of File ** +*******************************************************************************/ + diff --git a/Src/Gen4_R-Car_MCAL/2_Trunk/V4H/MCAL-v4h_19.4.0.D_release/rel/modules/cddiccom/sample_application/V4H/19_11/src/CDD_Iccom_PBcfg.c b/Src/Gen4_R-Car_MCAL/2_Trunk/V4H/MCAL-v4h_19.4.0.D_release/rel/modules/cddiccom/sample_application/V4H/19_11/src/CDD_Iccom_PBcfg.c new file mode 100644 index 00000000..5b113663 --- /dev/null +++ b/Src/Gen4_R-Car_MCAL/2_Trunk/V4H/MCAL-v4h_19.4.0.D_release/rel/modules/cddiccom/sample_application/V4H/19_11/src/CDD_Iccom_PBcfg.c @@ -0,0 +1,558 @@ +/*============================================================================*/ +/* Project = AUTOSAR Renesas MCAL Components */ +/* Module = CDD_Iccom_PBcfg.c */ +/*============================================================================*/ +/* COPYRIGHT */ +/*============================================================================*/ +/* Copyright(c) 2026 Renesas Electronics Corporation. */ +/*============================================================================*/ +/* Purpose: */ +/* This file contains post build parameters */ +/* AUTOMATICALLY GENERATED FILE - DO NOT EDIT */ +/* */ +/*============================================================================*/ +/* */ +/* Unless otherwise agreed upon in writing between your company and */ +/* Renesas Electronics Corporation the following shall apply! */ +/* */ +/* Warranty Disclaimer */ +/* */ +/* There is no warranty of any kind whatsoever granted by Renesas. Any */ +/* warranty is expressly disclaimed and excluded by Renesas, either expressed */ +/* or implied, including but not limited to those for non-infringement of */ +/* intellectual property, merchantability and/or fitness for the particular */ +/* purpose. */ +/* */ +/* Renesas shall not have any obligation to maintain, service or provide bug */ +/* fixes for the supplied Product(s) and/or the Application. */ +/* */ +/* Each User is solely responsible for determining the appropriateness of */ +/* using the Product(s) and assumes all risks associated with its exercise */ +/* of rights under this Agreement, including, but not limited to the risks */ +/* and costs of program errors, compliance with applicable laws, damage to */ +/* or loss of data, programs or equipment, and unavailability or */ +/* interruption of operations. */ +/* */ +/* Limitation of Liability */ +/* */ +/* In no event shall Renesas be liable to the User for any incidental, */ +/* consequential, indirect, or punitive damage (including but not limited */ +/* to lost profits) regardless of whether such liability is based on breach */ +/* of contract, tort, strict liability, breach of warranties, failure of */ +/* essential purpose or otherwise and even if advised of the possibility of */ +/* such damages. Renesas shall not be liable for any services or products */ +/* provided by third party vendors, developers or consultants identified or */ +/* referred to the User by Renesas in connection with the Product(s) and/or */ +/* the Application. */ +/* */ +/*============================================================================*/ +/* Environment: */ +/* Devices: V4H */ +/*============================================================================*/ + + +/******************************************************************************* +** Revision Control History ** +*******************************************************************************/ + + + +/******************************************************************************* +** Generation Tool Version ** +*******************************************************************************/ +/* */ +/* TOOL VERSION: CddIccomRCAR.dll version: 1.0.10, MCALConfGen.exe version: 1.2.3 */ +/* */ + + +/******************************************************************************* +** Input File ** +*******************************************************************************/ +/* + * INPUT FILE: C:\Work\Src\Gen4_R-Car_MCAL\2_Trunk\V4H\MCAL-v4h_19.4.0.D_release\rel\modules\cddiccom\sample_application\V4H\19_11\config\App_CDD_ICCOM_V4H_Sample.arxml + * C:\Work\Src\Gen4_R-Car_MCAL\2_Trunk\V4H\MCAL-v4h_19.4.0.D_release\rel\modules\cddiccom\generator\V4H\R1911_CDD_ICCOM_V4H_BSWMDT.arxml + * C:\Work\Src\Gen4_R-Car_MCAL\2_Trunk\V4H\MCAL-v4h_19.4.0.D_release\rel\common\generic\stubs\19_11\Dem\xml\Dem_CDD_Iccom.arxml + * C:\Work\Src\Gen4_R-Car_MCAL\2_Trunk\V4H\MCAL-v4h_19.4.0.D_release\rel\common\generic\stubs\19_11\Os\xml\Os_CDD_Iccom.arxml + * C:\Work\Src\Gen4_R-Car_MCAL\2_Trunk\V4H\MCAL-v4h_19.4.0.D_release\rel\V4H\common_family\generator\arm\Sample_Application_V4H.trxml + * GENERATED ON: 19 6 2026 - 05:11:57 + */ + + +/******************************************************************************* +** Instance Index ** +*******************************************************************************/ + +/******************************************************************************* +** Include Section ** +*******************************************************************************/ +#include "CDD_Iccom.h" +#include "CDD_Iccom_PBTypes.h" +#include "CDD_Iccom_Ram.h" +#include "CDD_Iccom_Cbk.h" + + +/******************************************************************************* +** MISRA C Rule Violations ** +*******************************************************************************/ +/* 1. MISRA C RULE VIOLATION: */ +/* Message : (2:3432) Simple macro argument expression is not */ +/* parenthesized. */ +/* Rule : MISRA C:2012 Rule-20.7, CWE Rule CWE-398, CWE-569 */ +/* REFERENCE - ISO:C90-6.3.1 Primary Expressions. */ +/* Justification : Compiler keyword (macro) is defined and used followed */ +/* AUTOSAR standard rule. It is accepted. */ +/* Verification : However, part of the code is verified manually */ +/* and it is not having any impact. */ +/* Reference : Look for START Msg(2:3432)-1 and */ +/* END Msg(2:3432)-1 tags in the code. */ +/******************************************************************************/ +/* 2. MISRA C RULE VIOLATION: */ +/* Message : (1:1504) The object '%1s' is only referenced in */ +/* the translation unit where it is defined. */ +/* Rule : MISRA C:2012 Rule-8.7, CWE Rule CWE-398, CWE-569 */ +/* Justification : This is accepted, due to following coding rule, */ +/* internal function can be defined in other C source files */ +/* Verification : However, part of the code is verified manually and it is */ +/* not having any impact. */ +/* Reference : Look for START Msg(1:1504)-2 and */ +/* END Msg(1:1504)-2 tags in the code. */ +/******************************************************************************/ +/* 3. MISRA C RULE VIOLATION: */ +/* Message : (2:0306) [I] Cast between a pointer to object and */ +/* an integral type. */ +/* Rule : MISRA C:2012 Rule-11.4, CWE Rule CWE-398, CWE-569, CWE-738 */ +/* REFERENCE - ISO:C90-6.3.4 Cast Operators - Semantics */ +/* Justification : Typecasting is done as per the register size, */ +/* to access hardware registers. */ +/* Verification : However, part of the code is verified manually and it is */ +/* not having any impact. */ +/* Reference : Look for START Msg(2:0306)-3 and */ +/* END Msg(2:0306)-3 tags in the code. */ +/******************************************************************************/ +/* 4. MISRA C RULE VIOLATION: */ +/* Message : (4:5087) Use of #include directive after code fragment. */ +/* Rule : MISRA-C:2012 Rule-20.1 */ +/* Justification : This is done as per Memory Requirement, */ +/* (MEMMAP003 - Specification of Memory Mapping). */ +/* Verification : However, part of the code is verified manually */ +/* and it is not having any impact. */ +/* Reference : Look for START Msg(4:5087)-4 and */ +/* END Msg(4:5087)-4 tags in the code. */ +/******************************************************************************/ + + +/******************************************************************************* +** Version Information ** +*******************************************************************************/ +#define CDDICCOM_PBCFG_C_AR_RELEASE_MAJOR_VERSION 4U +#define CDDICCOM_PBCFG_C_AR_RELEASE_MINOR_VERSION 5U +#define CDDICCOM_PBCFG_C_AR_RELEASE_REVISION_VERSION 0U +#define CDDICCOM_PBCFG_C_SW_MAJOR_VERSION 1U +#define CDDICCOM_PBCFG_C_SW_MINOR_VERSION 1U + +/******************************************************************************* +** Version Check ** +*******************************************************************************/ +#if (CDDICCOM_PBTYPES_AR_RELEASE_MAJOR_VERSION != \ + CDDICCOM_PBCFG_C_AR_RELEASE_MAJOR_VERSION) + #error "CDD_Iccom_PBcfg.c: Mismatch in Release Major Version" +#endif +#if (CDDICCOM_PBTYPES_AR_RELEASE_MINOR_VERSION != \ + CDDICCOM_PBCFG_C_AR_RELEASE_MINOR_VERSION) + #error "CDD_Iccom_PBcfg.c: Mismatch in Release Minor Version" +#endif +#if (CDDICCOM_PBTYPES_AR_RELEASE_REVISION_VERSION != \ + CDDICCOM_PBCFG_C_AR_RELEASE_REVISION_VERSION) + #error "CDD_Iccom_PBcfg.c: Mismatch in Release Revision Version" +#endif + +#if (CDDICCOM_SW_MAJOR_VERSION != CDDICCOM_PBCFG_C_SW_MAJOR_VERSION) + #error "CDD_Iccom_PBcfg.c: Mismatch in Software Major Version" +#endif +#if (CDDICCOM_SW_MINOR_VERSION != CDDICCOM_PBCFG_C_SW_MINOR_VERSION) + #error "CDD_Iccom_PBcfg.c: Mismatch in Software Minor Version" +#endif + + +/******************************************************************************* +** Global Data Types ** +*******************************************************************************/ + +/******************************************************************************* +** Global Data ** +*******************************************************************************/ +#define CDDICCOM_START_SEC_CONFIG_DATA_32 +#include "CddIccom_MemMap.h" + +/* Global array for Global ConfigSet structure */ +CONST(CddIccom_ConfigType, CDDICCOM_CONFIG_DATA) CddIccom_GstConfiguration[] = +{ + /* Index: 0 - 0 */ + { + /* ulStartOfDbToc */ + 0x0EFFC108UL, + + /* pChannelConfig */ + /* MISRA Violation: START Msg(2:3432)-1 */ + (P2CONST(CddIccom_ChannelConfigType, TYPEDEF, CDDICCOM_APPL_CONST)) \ + &CddIccom_GstChannelConfig[0], + /* END Msg(2:3432)-1 */ + + /* pChannelStatus */ + /* MISRA Violation: START Msg(2:3432)-1 */ + (P2VAR(CddIccom_ChannelStatusType, TYPEDEF, CDDICCOM_APPL_DATA)) \ + &CddIccom_GstChannelStatus[0] + /* END Msg(2:3432)-1 */ + } +}; + +/* Global array for Channel Configuration structure */ +/* MISRA Violation: START Msg(1:1504)-2 */ +CONST(CddIccom_ChannelConfigType, CDDICCOM_CONFIG_DATA) + CddIccom_GstChannelConfig[] = +{ + /* Index: 0 - 0 */ + { + /* *pMFISxICRnReg */ + /* MISRA Violation: START Msg(2:0306)-3 */ + /* MISRA Violation: START Msg(2:3432)-1 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6261400UL, + /* END Msg(2:3432)-1 */ + /* END Msg(2:0306)-3 */ + + /* *pMFISyICRnReg */ + /* MISRA Violation: START Msg(2:0306)-3 */ + /* MISRA Violation: START Msg(2:3432)-1 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6269404UL, + /* END Msg(2:3432)-1 */ + /* END Msg(2:0306)-3 */ + + /* *pMFISxMBRnReg */ + /* MISRA Violation: START Msg(2:0306)-3 */ + /* MISRA Violation: START Msg(2:3432)-1 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6261440UL, + /* END Msg(2:3432)-1 */ + /* END Msg(2:0306)-3 */ + + /* *pMFISyMBRnReg */ + /* MISRA Violation: START Msg(2:0306)-3 */ + /* MISRA Violation: START Msg(2:3432)-1 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6269460UL, + /* END Msg(2:3432)-1 */ + /* END Msg(2:0306)-3 */ + + /* *pCtaRxUpper */ + /* MISRA Violation: START Msg(2:0306)-3 */ + /* MISRA Violation: START Msg(2:3432)-1 */ + (P2CONST(uint8, TYPEDEF, CDDICCOM_APPL_DATA)) 0x47FC7000UL, + /* END Msg(2:3432)-1 */ + /* END Msg(2:0306)-3 */ + + /* *pCtaRxBottom */ + /* MISRA Violation: START Msg(2:0306)-3 */ + /* MISRA Violation: START Msg(2:3432)-1 */ + (P2CONST(uint8, TYPEDEF, CDDICCOM_APPL_DATA)) 0x47FC7800UL, + /* END Msg(2:3432)-1 */ + /* END Msg(2:0306)-3 */ + + /* *pCtaTxUpper */ + /* MISRA Violation: START Msg(2:0306)-3 */ + /* MISRA Violation: START Msg(2:3432)-1 */ + (P2VAR(uint8, TYPEDEF, CDDICCOM_APPL_DATA)) 0x47FC8000UL, + /* END Msg(2:3432)-1 */ + /* END Msg(2:0306)-3 */ + + /* *pCtaTxBottom */ + /* MISRA Violation: START Msg(2:0306)-3 */ + /* MISRA Violation: START Msg(2:3432)-1 */ + (P2VAR(uint8, TYPEDEF, CDDICCOM_APPL_DATA)) 0x47FC8800UL, + /* END Msg(2:3432)-1 */ + /* END Msg(2:0306)-3 */ + + /* uiCtaPartSize */ + 0x00000800UL, + + /* *ddTimeoutCntId */ + OsCounter, + + /* uiTimeout */ + 0x000100FDUL, + + /* *pNotification */ + &CddIccom_Ch0NoticeCallback, + + /* *pEnterRegProtect */ + &SchM_Enter_CddIccom_CDDICCOM_INTERRUPT_CONTROL_PROTECTION0, + + /* *pExitRegProtect */ + &SchM_Exit_CddIccom_CDDICCOM_INTERRUPT_CONTROL_PROTECTION0, + + /* *pEnterGlbProtect */ + &SchM_Enter_CddIccom_CDDICCOM_RAM_DATA_PROTECTION0, + + /* *pExitGlbProtect */ + &SchM_Exit_CddIccom_CDDICCOM_RAM_DATA_PROTECTION0 + }, + /* Index: 1 - 1 */ + { + /* *pMFISxICRnReg */ + /* MISRA Violation: START Msg(2:0306)-3 */ + /* MISRA Violation: START Msg(2:3432)-1 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6262408UL, + /* END Msg(2:3432)-1 */ + /* END Msg(2:0306)-3 */ + + /* *pMFISyICRnReg */ + /* MISRA Violation: START Msg(2:0306)-3 */ + /* MISRA Violation: START Msg(2:3432)-1 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE626940CUL, + /* END Msg(2:3432)-1 */ + /* END Msg(2:0306)-3 */ + + /* *pMFISxMBRnReg */ + /* MISRA Violation: START Msg(2:0306)-3 */ + /* MISRA Violation: START Msg(2:3432)-1 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6262444UL, + /* END Msg(2:3432)-1 */ + /* END Msg(2:0306)-3 */ + + /* *pMFISyMBRnReg */ + /* MISRA Violation: START Msg(2:0306)-3 */ + /* MISRA Violation: START Msg(2:3432)-1 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6269464UL, + /* END Msg(2:3432)-1 */ + /* END Msg(2:0306)-3 */ + + /* *pCtaRxUpper */ + /* MISRA Violation: START Msg(2:0306)-3 */ + /* MISRA Violation: START Msg(2:3432)-1 */ + (P2CONST(uint8, TYPEDEF, CDDICCOM_APPL_DATA)) 0x47FC9000UL, + /* END Msg(2:3432)-1 */ + /* END Msg(2:0306)-3 */ + + /* *pCtaRxBottom */ + /* MISRA Violation: START Msg(2:0306)-3 */ + /* MISRA Violation: START Msg(2:3432)-1 */ + (P2CONST(uint8, TYPEDEF, CDDICCOM_APPL_DATA)) 0x47FC9800UL, + /* END Msg(2:3432)-1 */ + /* END Msg(2:0306)-3 */ + + /* *pCtaTxUpper */ + /* MISRA Violation: START Msg(2:0306)-3 */ + /* MISRA Violation: START Msg(2:3432)-1 */ + (P2VAR(uint8, TYPEDEF, CDDICCOM_APPL_DATA)) 0x47FCA000UL, + /* END Msg(2:3432)-1 */ + /* END Msg(2:0306)-3 */ + + /* *pCtaTxBottom */ + /* MISRA Violation: START Msg(2:0306)-3 */ + /* MISRA Violation: START Msg(2:3432)-1 */ + (P2VAR(uint8, TYPEDEF, CDDICCOM_APPL_DATA)) 0x47FCA800UL, + /* END Msg(2:3432)-1 */ + /* END Msg(2:0306)-3 */ + + /* uiCtaPartSize */ + 0x00000800UL, + + /* *ddTimeoutCntId */ + OsCounter, + + /* uiTimeout */ + 0x000100FDUL, + + /* *pNotification */ + &CddIccom_Ch1NoticeCallback, + + /* *pEnterRegProtect */ + &SchM_Enter_CddIccom_CDDICCOM_INTERRUPT_CONTROL_PROTECTION1, + + /* *pExitRegProtect */ + &SchM_Exit_CddIccom_CDDICCOM_INTERRUPT_CONTROL_PROTECTION1, + + /* *pEnterGlbProtect */ + &SchM_Enter_CddIccom_CDDICCOM_RAM_DATA_PROTECTION1, + + /* *pExitGlbProtect */ + &SchM_Exit_CddIccom_CDDICCOM_RAM_DATA_PROTECTION1 + }, + /* Index: 2 - 2 */ + { + /* *pMFISxICRnReg */ + /* MISRA Violation: START Msg(2:0306)-3 */ + /* MISRA Violation: START Msg(2:3432)-1 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6263410UL, + /* END Msg(2:3432)-1 */ + /* END Msg(2:0306)-3 */ + + /* *pMFISyICRnReg */ + /* MISRA Violation: START Msg(2:0306)-3 */ + /* MISRA Violation: START Msg(2:3432)-1 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6269414UL, + /* END Msg(2:3432)-1 */ + /* END Msg(2:0306)-3 */ + + /* *pMFISxMBRnReg */ + /* MISRA Violation: START Msg(2:0306)-3 */ + /* MISRA Violation: START Msg(2:3432)-1 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6263448UL, + /* END Msg(2:3432)-1 */ + /* END Msg(2:0306)-3 */ + + /* *pMFISyMBRnReg */ + /* MISRA Violation: START Msg(2:0306)-3 */ + /* MISRA Violation: START Msg(2:3432)-1 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6269468UL, + /* END Msg(2:3432)-1 */ + /* END Msg(2:0306)-3 */ + + /* *pCtaRxUpper */ + /* MISRA Violation: START Msg(2:0306)-3 */ + /* MISRA Violation: START Msg(2:3432)-1 */ + (P2CONST(uint8, TYPEDEF, CDDICCOM_APPL_DATA)) 0x47FCB000UL, + /* END Msg(2:3432)-1 */ + /* END Msg(2:0306)-3 */ + + /* *pCtaRxBottom */ + /* MISRA Violation: START Msg(2:0306)-3 */ + /* MISRA Violation: START Msg(2:3432)-1 */ + (P2CONST(uint8, TYPEDEF, CDDICCOM_APPL_DATA)) 0x47FCB800UL, + /* END Msg(2:3432)-1 */ + /* END Msg(2:0306)-3 */ + + /* *pCtaTxUpper */ + /* MISRA Violation: START Msg(2:0306)-3 */ + /* MISRA Violation: START Msg(2:3432)-1 */ + (P2VAR(uint8, TYPEDEF, CDDICCOM_APPL_DATA)) 0x47FCC000UL, + /* END Msg(2:3432)-1 */ + /* END Msg(2:0306)-3 */ + + /* *pCtaTxBottom */ + /* MISRA Violation: START Msg(2:0306)-3 */ + /* MISRA Violation: START Msg(2:3432)-1 */ + (P2VAR(uint8, TYPEDEF, CDDICCOM_APPL_DATA)) 0x47FCC800UL, + /* END Msg(2:3432)-1 */ + /* END Msg(2:0306)-3 */ + + /* uiCtaPartSize */ + 0x00000800UL, + + /* *ddTimeoutCntId */ + OsCounter, + + /* uiTimeout */ + 0x000100FDUL, + + /* *pNotification */ + &CddIccom_Ch2NoticeCallback, + + /* *pEnterRegProtect */ + &SchM_Enter_CddIccom_CDDICCOM_INTERRUPT_CONTROL_PROTECTION2, + + /* *pExitRegProtect */ + &SchM_Exit_CddIccom_CDDICCOM_INTERRUPT_CONTROL_PROTECTION2, + + /* *pEnterGlbProtect */ + &SchM_Enter_CddIccom_CDDICCOM_RAM_DATA_PROTECTION2, + + /* *pExitGlbProtect */ + &SchM_Exit_CddIccom_CDDICCOM_RAM_DATA_PROTECTION2 + }, + /* Index: 3 - 3 */ + { + /* *pMFISxICRnReg */ + /* MISRA Violation: START Msg(2:0306)-3 */ + /* MISRA Violation: START Msg(2:3432)-1 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6264418UL, + /* END Msg(2:3432)-1 */ + /* END Msg(2:0306)-3 */ + + /* *pMFISyICRnReg */ + /* MISRA Violation: START Msg(2:0306)-3 */ + /* MISRA Violation: START Msg(2:3432)-1 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE626941CUL, + /* END Msg(2:3432)-1 */ + /* END Msg(2:0306)-3 */ + + /* *pMFISxMBRnReg */ + /* MISRA Violation: START Msg(2:0306)-3 */ + /* MISRA Violation: START Msg(2:3432)-1 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE626444CUL, + /* END Msg(2:3432)-1 */ + /* END Msg(2:0306)-3 */ + + /* *pMFISyMBRnReg */ + /* MISRA Violation: START Msg(2:0306)-3 */ + /* MISRA Violation: START Msg(2:3432)-1 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE626946CUL, + /* END Msg(2:3432)-1 */ + /* END Msg(2:0306)-3 */ + + /* *pCtaRxUpper */ + /* MISRA Violation: START Msg(2:0306)-3 */ + /* MISRA Violation: START Msg(2:3432)-1 */ + (P2CONST(uint8, TYPEDEF, CDDICCOM_APPL_DATA)) 0x47FCD000UL, + /* END Msg(2:3432)-1 */ + /* END Msg(2:0306)-3 */ + + /* *pCtaRxBottom */ + /* MISRA Violation: START Msg(2:0306)-3 */ + /* MISRA Violation: START Msg(2:3432)-1 */ + (P2CONST(uint8, TYPEDEF, CDDICCOM_APPL_DATA)) 0x47FCD800UL, + /* END Msg(2:3432)-1 */ + /* END Msg(2:0306)-3 */ + + /* *pCtaTxUpper */ + /* MISRA Violation: START Msg(2:0306)-3 */ + /* MISRA Violation: START Msg(2:3432)-1 */ + (P2VAR(uint8, TYPEDEF, CDDICCOM_APPL_DATA)) 0x47FCE000UL, + /* END Msg(2:3432)-1 */ + /* END Msg(2:0306)-3 */ + + /* *pCtaTxBottom */ + /* MISRA Violation: START Msg(2:0306)-3 */ + /* MISRA Violation: START Msg(2:3432)-1 */ + (P2VAR(uint8, TYPEDEF, CDDICCOM_APPL_DATA)) 0x47FCE800UL, + /* END Msg(2:3432)-1 */ + /* END Msg(2:0306)-3 */ + + /* uiCtaPartSize */ + 0x00000800UL, + + /* *ddTimeoutCntId */ + OsCounter, + + /* uiTimeout */ + 0x000100FDUL, + + /* *pNotification */ + &CddIccom_Ch3NoticeCallback, + + /* *pEnterRegProtect */ + &SchM_Enter_CddIccom_CDDICCOM_INTERRUPT_CONTROL_PROTECTION3, + + /* *pExitRegProtect */ + &SchM_Exit_CddIccom_CDDICCOM_INTERRUPT_CONTROL_PROTECTION3, + + /* *pEnterGlbProtect */ + &SchM_Enter_CddIccom_CDDICCOM_RAM_DATA_PROTECTION3, + + /* *pExitGlbProtect */ + &SchM_Exit_CddIccom_CDDICCOM_RAM_DATA_PROTECTION3 + } +}; +/* END Msg(1:1504)-2 */ + +#define CDDICCOM_STOP_SEC_CONFIG_DATA_32 +/* MISRA Violation: START Msg(4:5087)-4 */ +#include "CddIccom_MemMap.h" +/* END Msg(4:5087)-4 */ + + +/******************************************************************************* +** Function Definitions ** +*******************************************************************************/ + +/******************************************************************************* +** End of File ** +*******************************************************************************/ + diff --git a/Src/Gen4_R-Car_MCAL/2_Trunk/V4H/MCAL-v4h_19.4.0.D_release/rel/modules/cddiic/sample_application/V4H/19_11/include/CDD_Iic_Cbk.h b/Src/Gen4_R-Car_MCAL/2_Trunk/V4H/MCAL-v4h_19.4.0.D_release/rel/modules/cddiic/sample_application/V4H/19_11/include/CDD_Iic_Cbk.h new file mode 100644 index 00000000..7fd8eef0 --- /dev/null +++ b/Src/Gen4_R-Car_MCAL/2_Trunk/V4H/MCAL-v4h_19.4.0.D_release/rel/modules/cddiic/sample_application/V4H/19_11/include/CDD_Iic_Cbk.h @@ -0,0 +1,167 @@ +/*============================================================================*/ +/* Project = AUTOSAR Renesas MCAL Components */ +/* Module = CDD_Iic_Cbk.h */ +/*============================================================================*/ +/* COPYRIGHT */ +/*============================================================================*/ +/* Copyright(c) 2026 Renesas Electronics Corporation. */ +/*============================================================================*/ +/* Purpose: */ +/* This file contains call-back functions declaration */ +/* AUTOMATICALLY GENERATED FILE - DO NOT EDIT */ +/* */ +/*============================================================================*/ +/* */ +/* Unless otherwise agreed upon in writing between your company and */ +/* Renesas Electronics Corporation the following shall apply! */ +/* */ +/* Warranty Disclaimer */ +/* */ +/* There is no warranty of any kind whatsoever granted by Renesas. Any */ +/* warranty is expressly disclaimed and excluded by Renesas, either expressed */ +/* or implied, including but not limited to those for non-infringement of */ +/* intellectual property, merchantability and/or fitness for the particular */ +/* purpose. */ +/* */ +/* Renesas shall not have any obligation to maintain, service or provide bug */ +/* fixes for the supplied Product(s) and/or the Application. */ +/* */ +/* Each User is solely responsible for determining the appropriateness of */ +/* using the Product(s) and assumes all risks associated with its exercise */ +/* of rights under this Agreement, including, but not limited to the risks */ +/* and costs of program errors, compliance with applicable laws, damage to */ +/* or loss of data, programs or equipment, and unavailability or */ +/* interruption of operations. */ +/* */ +/* Limitation of Liability */ +/* */ +/* In no event shall Renesas be liable to the User for any incidental, */ +/* consequential, indirect, or punitive damage (including but not limited */ +/* to lost profits) regardless of whether such liability is based on breach */ +/* of contract, tort, strict liability, breach of warranties, failure of */ +/* essential purpose or otherwise and even if advised of the possibility of */ +/* such damages. Renesas shall not be liable for any services or products */ +/* provided by third party vendors, developers or consultants identified or */ +/* referred to the User by Renesas in connection with the Product(s) and/or */ +/* the Application. */ +/* */ +/*============================================================================*/ +/* Environment: */ +/* Devices: V4H */ +/*============================================================================*/ + + +/******************************************************************************* +** Revision Control History ** +*******************************************************************************/ + + +/******************************************************************************* +** 1.0.0 16-Mar-2022 Initial Version ** +*******************************************************************************/ + + +/******************************************************************************* +** Generation Tool Version ** +*******************************************************************************/ +/* */ +/* TOOL VERSION: CddIicRCAR.dll version: 1.0.10, MCALConfGen.exe version: 1.2.3 */ +/* */ + + +/******************************************************************************* +** Input File ** +*******************************************************************************/ +/* + * INPUT FILE: C:\Work\Src\Gen4_R-Car_MCAL\2_Trunk\V4H\MCAL-v4h_19.4.0.D_release\rel\modules\cddiic\sample_application\V4H\19_11\config\App_CDD_IIC_V4H_Sample.arxml + * C:\Work\Src\Gen4_R-Car_MCAL\2_Trunk\V4H\MCAL-v4h_19.4.0.D_release\rel\modules\cddiic\generator\V4H\R1911_CDD_IIC_V4H_BSWMDT.arxml + * C:\Work\Src\Gen4_R-Car_MCAL\2_Trunk\V4H\MCAL-v4h_19.4.0.D_release\rel\common\generic\stubs\19_11\Dem\xml\Dem_CDD_Iic.arxml + * C:\Work\Src\Gen4_R-Car_MCAL\2_Trunk\V4H\MCAL-v4h_19.4.0.D_release\rel\V4H\common_family\generator\arm\Sample_Application_V4H.trxml + * GENERATED ON: 19 6 2026 - 05:12:06 + */ + + +#ifndef CDD_IIC_CBK_H +#define CDD_IIC_CBK_H + + +/******************************************************************************* +** Include Section ** +*******************************************************************************/ + +/******************************************************************************* +** Version Information ** +*******************************************************************************/ +#define CDDIIC_CBK_AR_RELEASE_MAJOR_VERSION 4U +#define CDDIIC_CBK_AR_RELEASE_MINOR_VERSION 5U +#define CDDIIC_CBK_AR_RELEASE_REVISION_VERSION 0U +#define CDDIIC_CBK_SW_MAJOR_VERSION 1U +#define CDDIIC_CBK_SW_MINOR_VERSION 1U + +/******************************************************************************* +** Global Symbols ** +*******************************************************************************/ + + + +/******************************************************************************* +** Global Data Types ** +*******************************************************************************/ + + + +/******************************************************************************* +** Global Data ** +*******************************************************************************/ + + + +/******************************************************************************* +** Function Prototypes ** +*******************************************************************************/ + + +#define CddIic_START_SEC_CODE +#include "CddIic_MemMap.h" + +extern FUNC(void, CddIic_CODE) CddIic_Ch0NoticeCallBack +( + IicNotification LstNoticInfo +); + +extern FUNC(void, CddIic_CODE) CddIic_Ch1NoticeCallBack +( + IicNotification LstNoticInfo +); + +extern FUNC(void, CddIic_CODE) CddIic_Ch2NoticeCallBack +( + IicNotification LstNoticInfo +); + +extern FUNC(void, CddIic_CODE) CddIic_Ch3NoticeCallBack +( + IicNotification LstNoticInfo +); + +extern FUNC(void, CddIic_CODE) CddIic_Ch4NoticeCallBack +( + IicNotification LstNoticInfo +); + +extern FUNC(void, CddIic_CODE) CddIic_Ch5NoticeCallBack +( + IicNotification LstNoticInfo +); + +#define CddIic_STOP_SEC_CODE +#include "CddIic_MemMap.h" + + +#endif /* CDD_IIC_CBK_H */ + + +/******************************************************************************* +** End of File ** +*******************************************************************************/ + diff --git a/Src/Gen4_R-Car_MCAL/2_Trunk/V4H/MCAL-v4h_19.4.0.D_release/rel/modules/cddiic/sample_application/V4H/19_11/include/CDD_Iic_Cfg.h b/Src/Gen4_R-Car_MCAL/2_Trunk/V4H/MCAL-v4h_19.4.0.D_release/rel/modules/cddiic/sample_application/V4H/19_11/include/CDD_Iic_Cfg.h new file mode 100644 index 00000000..623fd537 --- /dev/null +++ b/Src/Gen4_R-Car_MCAL/2_Trunk/V4H/MCAL-v4h_19.4.0.D_release/rel/modules/cddiic/sample_application/V4H/19_11/include/CDD_Iic_Cfg.h @@ -0,0 +1,232 @@ +/*============================================================================*/ +/* Project = AUTOSAR Renesas MCAL Components */ +/* Module = CDD_Iic_Cfg.h */ +/*============================================================================*/ +/* COPYRIGHT */ +/*============================================================================*/ +/* Copyright(c) 2026 Renesas Electronics Corporation. */ +/*============================================================================*/ +/* Purpose: */ +/* This file contains pre-compile time parameters */ +/* AUTOMATICALLY GENERATED FILE - DO NOT EDIT */ +/* */ +/*============================================================================*/ +/* */ +/* Unless otherwise agreed upon in writing between your company and */ +/* Renesas Electronics Corporation the following shall apply! */ +/* */ +/* Warranty Disclaimer */ +/* */ +/* There is no warranty of any kind whatsoever granted by Renesas. Any */ +/* warranty is expressly disclaimed and excluded by Renesas, either expressed */ +/* or implied, including but not limited to those for non-infringement of */ +/* intellectual property, merchantability and/or fitness for the particular */ +/* purpose. */ +/* */ +/* Renesas shall not have any obligation to maintain, service or provide bug */ +/* fixes for the supplied Product(s) and/or the Application. */ +/* */ +/* Each User is solely responsible for determining the appropriateness of */ +/* using the Product(s) and assumes all risks associated with its exercise */ +/* of rights under this Agreement, including, but not limited to the risks */ +/* and costs of program errors, compliance with applicable laws, damage to */ +/* or loss of data, programs or equipment, and unavailability or */ +/* interruption of operations. */ +/* */ +/* Limitation of Liability */ +/* */ +/* In no event shall Renesas be liable to the User for any incidental, */ +/* consequential, indirect, or punitive damage (including but not limited */ +/* to lost profits) regardless of whether such liability is based on breach */ +/* of contract, tort, strict liability, breach of warranties, failure of */ +/* essential purpose or otherwise and even if advised of the possibility of */ +/* such damages. Renesas shall not be liable for any services or products */ +/* provided by third party vendors, developers or consultants identified or */ +/* referred to the User by Renesas in connection with the Product(s) and/or */ +/* the Application. */ +/* */ +/*============================================================================*/ +/* Environment: */ +/* Devices: V4H */ +/*============================================================================*/ + + +/******************************************************************************* +** Revision Control History ** +*******************************************************************************/ + + +/******************************************************************************* +** 1.0.0 16-Mar-2022 Initial Version ** +*******************************************************************************/ + + +/******************************************************************************* +** Generation Tool Version ** +*******************************************************************************/ +/* */ +/* TOOL VERSION: CddIicRCAR.dll version: 1.0.10, MCALConfGen.exe version: 1.2.3 */ +/* */ + + +/******************************************************************************* +** Input File ** +*******************************************************************************/ +/* + * INPUT FILE: C:\Work\Src\Gen4_R-Car_MCAL\2_Trunk\V4H\MCAL-v4h_19.4.0.D_release\rel\modules\cddiic\sample_application\V4H\19_11\config\App_CDD_IIC_V4H_Sample.arxml + * C:\Work\Src\Gen4_R-Car_MCAL\2_Trunk\V4H\MCAL-v4h_19.4.0.D_release\rel\modules\cddiic\generator\V4H\R1911_CDD_IIC_V4H_BSWMDT.arxml + * C:\Work\Src\Gen4_R-Car_MCAL\2_Trunk\V4H\MCAL-v4h_19.4.0.D_release\rel\common\generic\stubs\19_11\Dem\xml\Dem_CDD_Iic.arxml + * C:\Work\Src\Gen4_R-Car_MCAL\2_Trunk\V4H\MCAL-v4h_19.4.0.D_release\rel\V4H\common_family\generator\arm\Sample_Application_V4H.trxml + * GENERATED ON: 19 6 2026 - 05:12:06 + */ + + +#ifndef CDD_IIC_CFG_H +#define CDD_IIC_CFG_H + + +/******************************************************************************* +** Include Section ** +*******************************************************************************/ + +/******************************************************************************* +** Version Information ** +*******************************************************************************/ +/* AUTOSAR release version information */ +#define CDDIIC_CFG_AR_RELEASE_MAJOR_VERSION 4U +#define CDDIIC_CFG_AR_RELEASE_MINOR_VERSION 5U +#define CDDIIC_CFG_AR_RELEASE_REVISION_VERSION 0U +/* File Version Information */ +#define CDDIIC_CFG_SW_MAJOR_VERSION 1U +#define CDDIIC_CFG_SW_MINOR_VERSION 1U + +/******************************************************************************* +** Common Published Information ** +*******************************************************************************/ +#define CDDIIC_AR_RELEASE_MAJOR_VERSION_VALUE 4U +#define CDDIIC_AR_RELEASE_MINOR_VERSION_VALUE 5U +#define CDDIIC_AR_RELEASE_REVISION_VERSION_VALUE 0U +#define CDDIIC_SW_MAJOR_VERSION_VALUE 1U +#define CDDIIC_SW_MINOR_VERSION_VALUE 1U +#define CDDIIC_SW_PATCH_VERSION_VALUE 0U +#define CDDIIC_VENDOR_ID_VALUE 59U +#define CDDIIC_MODULE_ID_VALUE 255U + +/******************************************************************************* +** Global Symbols ** +*******************************************************************************/ + + +/* Pre-compile option for Already Init Check */ +#define CDDIIC_ALREADY_INIT_DET_CHECK STD_ON + +/* Pre-compile option for Development Error Detect */ +#define CDDIIC_DEV_ERROR_DETECT STD_OFF + +/* Pre-compile option for Register Write Error Report */ +#define CDDIIC_REGISTER_WRITE_VERIFY STD_OFF + +/* Pre-compile option for Dependencies Version Check */ +#define CDDIIC_VERSION_CHECK_EXT_MODULES STD_ON + +/* Pre-compile option for Critical Section */ +#define CDDIIC_CRITICAL_SECTION_PROTECTION STD_ON + +/* Pre-compile option for Unintended Interrupt Check */ +#define CDDIIC_UNINTENDED_INTERRUPT_CHECK STD_OFF + +/* Pre-compile option for Version Info API */ +#define CDDIIC_VERSION_INFO_API STD_ON + +/* Pre-compile option for DEM for non-acknowledgement event */ +#define CDDIIC_E_NON_ACKNOWLEDGEMENT \ + DemConf_DemEventParameter_CDDIIC_E_NON_ACKNOWLEDGEMENT + + +/* Total number of configured channels */ +#define CDDIIC_TOTAL_CHANNELS_CONFIG 6U + +/* Total number of slave configurations */ +#define CDDIIC_TOTAL_SLAVES_CONFIG 1U + +/* Total number of DMA configuration */ +#define CDDIIC_TOTAL_DMA_CONFIG 0U + +/* Supported Device Name */ +#define CDDIIC_DEVICE_NAME V4H + +/* CDDIIC channel selection */ +#define CDDIIC_CH0_USED STD_ON +#define CDDIIC_CH1_USED STD_ON +#define CDDIIC_CH2_USED STD_ON +#define CDDIIC_CH3_USED STD_ON +#define CDDIIC_CH4_USED STD_ON +#define CDDIIC_CH5_USED STD_ON +#define CDDIIC_CH6_USED STD_OFF + +/* CDDIIC hardware channel selection */ +#define CDDIIC_HW_IIC0_USED STD_ON +#define CDDIIC_HW_IIC1_USED STD_ON +#define CDDIIC_HW_IIC2_USED STD_ON +#define CDDIIC_HW_IIC3_USED STD_ON +#define CDDIIC_HW_IIC4_USED STD_ON +#define CDDIIC_HW_IIC5_USED STD_ON +#define CDDIIC_HW_IIC6_USED STD_OFF + +/* CDDIIC hardware channel mapping */ +#define CDDIIC_HW_IIC0_CHANNEL (CddIic_ChannelType)0U +#define CDDIIC_HW_IIC1_CHANNEL (CddIic_ChannelType)1U +#define CDDIIC_HW_IIC2_CHANNEL (CddIic_ChannelType)2U +#define CDDIIC_HW_IIC3_CHANNEL (CddIic_ChannelType)3U +#define CDDIIC_HW_IIC4_CHANNEL (CddIic_ChannelType)4U +#define CDDIIC_HW_IIC5_CHANNEL (CddIic_ChannelType)5U + +/* DMA CDDIIC Channel mapping */ + +/* CDDIIC channel interface */ +#define CDDIIC_CH0_INTERFACE CDDIIC_MASTER_INTERFACE +#define CDDIIC_CH1_INTERFACE CDDIIC_SLAVE_INTERFACE +#define CDDIIC_CH2_INTERFACE CDDIIC_MASTER_INTERFACE +#define CDDIIC_CH3_INTERFACE CDDIIC_MASTER_INTERFACE +#define CDDIIC_CH4_INTERFACE CDDIIC_MASTER_INTERFACE +#define CDDIIC_CH5_INTERFACE CDDIIC_MASTER_INTERFACE + +/* Configuration Set Handles */ +#define CddIicConf_CddConfigSet_CddConfigSet \ + (&CddIic_GaaConfiguration[0]) + +/* Slave Handles */ +#define CddIicConf_CddIicSlaves_CddIicSlave \ + (&CddIic_GaaSlaveConfig[0]) + +/* Bus mode configure */ +#define CDDIIC_FAST_MODE_PLUS STD_ON + +/* Dummy read configure */ +#define CDDIIC_DUMMY_READ_IRQ_STATUS STD_ON + +/******************************************************************************* +** Global Data Types ** +*******************************************************************************/ + + + +/******************************************************************************* +** Global Data ** +*******************************************************************************/ + + + +/******************************************************************************* +** Function Prototypes ** +*******************************************************************************/ + + + +#endif /* CDD_IIC_CFG_H */ + + +/******************************************************************************* +** End of File ** +*******************************************************************************/ + diff --git a/Src/Gen4_R-Car_MCAL/2_Trunk/V4H/MCAL-v4h_19.4.0.D_release/rel/modules/cddiic/sample_application/V4H/19_11/src/CDD_Iic_PBcfg.c b/Src/Gen4_R-Car_MCAL/2_Trunk/V4H/MCAL-v4h_19.4.0.D_release/rel/modules/cddiic/sample_application/V4H/19_11/src/CDD_Iic_PBcfg.c new file mode 100644 index 00000000..ae14b634 --- /dev/null +++ b/Src/Gen4_R-Car_MCAL/2_Trunk/V4H/MCAL-v4h_19.4.0.D_release/rel/modules/cddiic/sample_application/V4H/19_11/src/CDD_Iic_PBcfg.c @@ -0,0 +1,1149 @@ +/*============================================================================*/ +/* Project = AUTOSAR Renesas MCAL Components */ +/* Module = CDD_Iic_PBcfg.c */ +/*============================================================================*/ +/* COPYRIGHT */ +/*============================================================================*/ +/* Copyright(c) 2026 Renesas Electronics Corporation. */ +/*============================================================================*/ +/* Purpose: */ +/* This file contains post build parameters */ +/* AUTOMATICALLY GENERATED FILE - DO NOT EDIT */ +/* */ +/*============================================================================*/ +/* */ +/* Unless otherwise agreed upon in writing between your company and */ +/* Renesas Electronics Corporation the following shall apply! */ +/* */ +/* Warranty Disclaimer */ +/* */ +/* There is no warranty of any kind whatsoever granted by Renesas. Any */ +/* warranty is expressly disclaimed and excluded by Renesas, either expressed */ +/* or implied, including but not limited to those for non-infringement of */ +/* intellectual property, merchantability and/or fitness for the particular */ +/* purpose. */ +/* */ +/* Renesas shall not have any obligation to maintain, service or provide bug */ +/* fixes for the supplied Product(s) and/or the Application. */ +/* */ +/* Each User is solely responsible for determining the appropriateness of */ +/* using the Product(s) and assumes all risks associated with its exercise */ +/* of rights under this Agreement, including, but not limited to the risks */ +/* and costs of program errors, compliance with applicable laws, damage to */ +/* or loss of data, programs or equipment, and unavailability or */ +/* interruption of operations. */ +/* */ +/* Limitation of Liability */ +/* */ +/* In no event shall Renesas be liable to the User for any incidental, */ +/* consequential, indirect, or punitive damage (including but not limited */ +/* to lost profits) regardless of whether such liability is based on breach */ +/* of contract, tort, strict liability, breach of warranties, failure of */ +/* essential purpose or otherwise and even if advised of the possibility of */ +/* such damages. Renesas shall not be liable for any services or products */ +/* provided by third party vendors, developers or consultants identified or */ +/* referred to the User by Renesas in connection with the Product(s) and/or */ +/* the Application. */ +/* */ +/*============================================================================*/ +/* Environment: */ +/* Devices: V4H */ +/*============================================================================*/ + + +/******************************************************************************* +** Revision Control History ** +*******************************************************************************/ + + +/******************************************************************************* +** 1.0.0 16-Mar-2022 Initial Version ** +** 1.0.1 08-Aug-2022 Update CWE rule ** +** 1.0.2 05-Oct-2022 Update memclass of variable in ** +** CddIic_GaaChannelConfig[], ** +** CddIic_GaaDmaConfig[] from CDDIIC_VAR to ** +** TYPEDEF ** +** Add MISRA message Msg(2:3432) for ** +** *pChannelConfig ** +** 1.0.3 07-Nov-2022 Update *pEnterRegProtect, *pExitRegProtect ** +** *pEnterGlbProtect, *pExitGlbProtect function** +** pointer to unify the critical section ** +*******************************************************************************/ + + +/******************************************************************************* +** Generation Tool Version ** +*******************************************************************************/ +/* */ +/* TOOL VERSION: CddIicRCAR.dll version: 1.0.10, MCALConfGen.exe version: 1.2.3 */ +/* */ + + +/******************************************************************************* +** Input File ** +*******************************************************************************/ +/* + * INPUT FILE: C:\Work\Src\Gen4_R-Car_MCAL\2_Trunk\V4H\MCAL-v4h_19.4.0.D_release\rel\modules\cddiic\sample_application\V4H\19_11\config\App_CDD_IIC_V4H_Sample.arxml + * C:\Work\Src\Gen4_R-Car_MCAL\2_Trunk\V4H\MCAL-v4h_19.4.0.D_release\rel\modules\cddiic\generator\V4H\R1911_CDD_IIC_V4H_BSWMDT.arxml + * C:\Work\Src\Gen4_R-Car_MCAL\2_Trunk\V4H\MCAL-v4h_19.4.0.D_release\rel\common\generic\stubs\19_11\Dem\xml\Dem_CDD_Iic.arxml + * C:\Work\Src\Gen4_R-Car_MCAL\2_Trunk\V4H\MCAL-v4h_19.4.0.D_release\rel\V4H\common_family\generator\arm\Sample_Application_V4H.trxml + * GENERATED ON: 19 6 2026 - 05:12:06 + */ + + +/******************************************************************************* +** Instance Index ** +*******************************************************************************/ + +/******************************************************************************* +** Include Section ** +*******************************************************************************/ +/* CDD IIC Post Build configuration header */ +/* QAC Warning: START Msg(2:0857)-2 */ +#include "CDD_Iic.h" +/* END Msg(2:0857)-2 */ +#include "CDD_Iic_PBTypes.h" +#include "CDD_Iic_Ram.h" +#include "CDD_Iic_Cbk.h" + + +/******************************************************************************* +** MISRA C Rule Violations ** +*******************************************************************************/ +/* 1. MISRA C RULE VIOLATION: */ +/* Message : (2:0306) [I] Cast between a pointer to object and an */ +/* integral type. */ +/* Rule : MISRA-C:2004 Rule 11.3, CWE-398, CWE-569, CWE-738 */ +/* REFERENCE - ISO:C90-6.11 - Pointer type conversion */ +/* Justification : Typecasting is done as per the register size, to access */ +/* hardware registers. */ +/* Verification : However, part of the code is verified manually and it is */ +/* not having any impact. */ +/* Reference : Look for START Msg(4:0306)-1 and */ +/* END Msg(4:0306)-1 tags in the code. */ +/******************************************************************************/ +/* 2. MISRA C RULE VIOLATION: */ +/* Message : (2:0857) [L] Number of macro definitions exceeds 1024 */ +/* - program does not conform strictly to ISO:C90. */ +/* Rule : MISRA-C:2004 Rule 1.1 */ +/* Justification : The number of macro depend on module code size. There is */ +/* no issue when number of macro is over 1024 */ +/* Verification : However, part of the code is verified manually and it is */ +/* not having any impact. */ +/* Reference : Look for START Msg(2:0857)-2 and */ +/* END Msg(2:0857)-2 tags in the code. */ +/******************************************************************************/ +/* 3. MISRA C RULE VIOLATION: */ +/* Message : (4:5087) Use of #include directive after code fragment. */ +/* Rule : MISRA-C:2004 Rule 19.1 */ +/* Justification : This is done as per Memory Requirement, (MEMMAP003 - */ +/* Specification of Memory Mapping). */ +/* Verification : However, part of the code is verified manually and it is */ +/* not having any impact. */ +/* Reference : Look for START Msg(4:5087)-3 and */ +/* END Msg(4:5087)-3 tags in the code. */ +/******************************************************************************/ +/* 4. MISRA C RULE VIOLATION: */ +/* Message : (2:3432) Simple macro argument expression is not */ +/* parenthesized. */ +/* Rule : MISRA C:2012 Rule-20.7, CWE-398, CWE-569 */ +/* REFERENCE - ISO:C90-6.3.1 Primary Expressions */ +/* Justification : Compiler keyword (macro) is defined and used followed */ +/* AUTOSAR standard rule. It is accepted. */ +/* Verification : However, part of the code is verified manually and it is */ +/* not having any impact. */ +/* Reference : Look for START Msg(2:3432)-5 and */ +/* END Msg(2:3432)-5 tags in the code. */ +/******************************************************************************/ +/******************************************************************************/ +/* 5. MISRA C RULE VIOLATION: */ +/* Message : (4:0311) Dangerous pointer cast results in loss of const */ +/* qualification. */ +/* Rule : MISRA C:2012 Rule-11.8 */ +/* Justification : This is to achieve throughput in the code. */ +/* Verification : However, part of the code is verified manually and it is */ +/* not having any impact. */ +/* Reference : Look for START Msg(4:0311)-6 and */ +/* END Msg(4:0311)-6 tags in the code. */ +/******************************************************************************/ +/* 6. MISRA C RULE VIOLATION: */ +/* Message : (1:1504) The object '%1s' is only referenced in the */ +/* translation unit where it is defined. */ +/* Rule : MISRA C:2012 Rule-8.7, CWE-398, CWE-569 */ +/* Justification : This is accepted, due to following coding rule, internal */ +/* function can be defined in other C source files */ +/* Verification : However, part of the code is verified manually and it is */ +/* not having any impact. */ +/* Reference : Look for START Msg(1:1504)-7 and */ +/* END Msg(1:1504)-7 tags in the code. */ +/******************************************************************************/ +/* 7. MISRA C RULE VIOLATION: */ +/* Message : (1:1502) The object '%1s' is defined but is not used */ +/* within this project. */ +/* Rule : MISRA C:2012 Rule-2.8, CWE-398, CWE-569 */ +/* Justification : This is accepted, Due to it is use throught point variable */ +/* Verification : However, part of the code is verified manually and it is */ +/* not having any impact. */ +/* Reference : Look for START Msg(1:1502)-7 and */ +/* END Msg(1:1504)-7 tags in the code. */ + + +/******************************************************************************* +** Version Information ** +*******************************************************************************/ +#define CDDIIC_PBCFG_C_AR_RELEASE_MAJOR_VERSION 4U +#define CDDIIC_PBCFG_C_AR_RELEASE_MINOR_VERSION 5U +#define CDDIIC_PBCFG_C_AR_RELEASE_REVISION_VERSION 0U +#define CDDIIC_PBCFG_C_SW_MAJOR_VERSION 1U +#define CDDIIC_PBCFG_C_SW_MINOR_VERSION 1U + +/******************************************************************************* +** Version Check ** +*******************************************************************************/ +#if (CDDIIC_PBTYPES_AR_RELEASE_MAJOR_VERSION != \ + CDDIIC_PBCFG_C_AR_RELEASE_MAJOR_VERSION) + #error "CDD_Iic_PBcfg.c: Mismatch in Release Major Version" +#endif +#if (CDDIIC_PBTYPES_AR_RELEASE_MINOR_VERSION != \ + CDDIIC_PBCFG_C_AR_RELEASE_MINOR_VERSION) + #error "CDD_Iic_PBcfg.c: Mismatch in Release Minor Version" +#endif +#if (CDDIIC_PBTYPES_AR_RELEASE_REVISION_VERSION != \ + CDDIIC_PBCFG_C_AR_RELEASE_REVISION_VERSION) + #error "CDD_Iic_PBcfg.c: Mismatch in Release Revision Version" +#endif + +#if (CDDIIC_SW_MAJOR_VERSION != CDDIIC_PBCFG_C_SW_MAJOR_VERSION) + #error "CDD_Iic_PBcfg.c: Mismatch in Software Major Version" +#endif +#if (CDDIIC_SW_MINOR_VERSION != CDDIIC_PBCFG_C_SW_MINOR_VERSION) + #error "CDD_Iic_PBcfg.c: Mismatch in Software Minor Version" +#endif + + +/******************************************************************************* +** Global Data Types ** +*******************************************************************************/ + +/******************************************************************************* +** Global Data ** +*******************************************************************************/ +#define CDDIIC_START_SEC_CONFIG_DATA_32 +/*QAC Warning: START Msg(4:5087)-3 */ +#include "CddIic_MemMap.h" +/* END Msg(4:5087)-3 */ + +/* Global array for Global ConfigSet Structure */ +/* QAC Warning: START Msg(1:1502)-7 */ +CONST(CddIic_ConfigType, CDDIIC_CONFIG_DATA) CddIic_GaaConfiguration[] = +{ + /* Index: 0 - 0 */ + { + /* ulStartOfDbToc */ + 0x0EFFC108UL, + + /* *pChannelConfig */ + /* MISRA Violation: START Msg(2:3432)-5 */ + (P2CONST(CddIic_ChannelConfigType, TYPEDEF, CDDIIC_CONFIG_CONST))\ + &CddIic_GaaChannelConfig[0], + /* END Msg(2:3432)-5 */ + + /* *pChannelStatus */ + /* MISRA Violation: START Msg(2:3432)-5 */ + (P2VAR(CddIic_ChannelStatusType, TYPEDEF, CDDIIC_CONFIG_DATA))\ + &CddIic_GaaChannelStatus[0] + /* END Msg(2:3432)-5 */ + } +}; +/* END Msg(1:1502)-7 */ + +/* Global array for Channel Config structure */ +/* MISRA Violation: START Msg(1:1504)-7 */ +CONST(CddIic_ChannelConfigType, CDDIIC_CONFIG_DATA) CddIic_GaaChannelConfig[] = +{ + /* Index: 0 - 0 */ + { + /* *pICMCRnReg */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-5 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6500004UL, + /* END Msg(2:3432)-5 */ + /* END Msg(2:0306)-1 */ + + /* *pICMSRnReg */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-5 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE650000CUL, + /* END Msg(2:3432)-5 */ + /* END Msg(2:0306)-1 */ + + /* *pICMIERnReg */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-5 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6500014UL, + /* END Msg(2:3432)-5 */ + /* END Msg(2:0306)-1 */ + + /* *pICMARnReg */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-5 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6500020UL, + /* END Msg(2:3432)-5 */ + /* END Msg(2:0306)-1 */ + + /* *pICTXRXDnReg */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-5 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6500024UL, + /* END Msg(2:3432)-5 */ + /* END Msg(2:0306)-1 */ + + /* *pICSCRnReg */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-5 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6500000UL, + /* END Msg(2:3432)-5 */ + /* END Msg(2:0306)-1 */ + + /* *pICSSRnReg */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-5 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6500008UL, + /* END Msg(2:3432)-5 */ + /* END Msg(2:0306)-1 */ + + /* *pICSIERnReg */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-5 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6500010UL, + /* END Msg(2:3432)-5 */ + /* END Msg(2:0306)-1 */ + + /* *pICSARnReg */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-5 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE650001CUL, + /* END Msg(2:3432)-5 */ + /* END Msg(2:0306)-1 */ + + /* *pICCCRnReg */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-5 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6500018UL, + /* END Msg(2:3432)-5 */ + /* END Msg(2:0306)-1 */ + + /* *pICCCR2nReg */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-5 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6500028UL, + /* END Msg(2:3432)-5 */ + /* END Msg(2:0306)-1 */ + + /* *pICMPRnReg */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-5 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE650002CUL, + /* END Msg(2:3432)-5 */ + /* END Msg(2:0306)-1 */ + + /* *pICHPRnReg */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-5 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6500030UL, + /* END Msg(2:3432)-5 */ + /* END Msg(2:0306)-1 */ + + /* *pICLPRnReg */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-5 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6500034UL, + /* END Msg(2:3432)-5 */ + /* END Msg(2:0306)-1 */ + + /* *pICDMAERnReg */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-5 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE650003CUL, + /* END Msg(2:3432)-5 */ + /* END Msg(2:0306)-1 */ + + /* *pICFBSCRnReg */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-5 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6500038UL, + /* END Msg(2:3432)-5 */ + /* END Msg(2:0306)-1 */ + + /* *pDmaConfiguration */ + NULL_PTR, + + /* *pNotification */ + &CddIic_Ch0NoticeCallBack, + + /* *pEnterRegProtect */ + &SchM_Enter_CddIic_CDDIIC_INTERRUPT_CONTROL_PROTECTION, + + /* *pExitRegProtect */ + &SchM_Exit_CddIic_CDDIIC_INTERRUPT_CONTROL_PROTECTION, + + /* *pEnterGlbProtect */ + &SchM_Enter_CddIic_CDDIIC_RAM_DATA_PROTECTION, + + /* *pExitGlbProtect */ + &SchM_Exit_CddIic_CDDIIC_RAM_DATA_PROTECTION, + + /* enInterface */ + CDDIIC_MASTER_IF, + + /* enDmaMode */ + CDDIIC_DMA_DISABLED + }, + /* Index: 1 - 1 */ + { + /* *pICMCRnReg */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-5 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6508004UL, + /* END Msg(2:3432)-5 */ + /* END Msg(2:0306)-1 */ + + /* *pICMSRnReg */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-5 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE650800CUL, + /* END Msg(2:3432)-5 */ + /* END Msg(2:0306)-1 */ + + /* *pICMIERnReg */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-5 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6508014UL, + /* END Msg(2:3432)-5 */ + /* END Msg(2:0306)-1 */ + + /* *pICMARnReg */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-5 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6508020UL, + /* END Msg(2:3432)-5 */ + /* END Msg(2:0306)-1 */ + + /* *pICTXRXDnReg */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-5 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6508024UL, + /* END Msg(2:3432)-5 */ + /* END Msg(2:0306)-1 */ + + /* *pICSCRnReg */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-5 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6508000UL, + /* END Msg(2:3432)-5 */ + /* END Msg(2:0306)-1 */ + + /* *pICSSRnReg */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-5 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6508008UL, + /* END Msg(2:3432)-5 */ + /* END Msg(2:0306)-1 */ + + /* *pICSIERnReg */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-5 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6508010UL, + /* END Msg(2:3432)-5 */ + /* END Msg(2:0306)-1 */ + + /* *pICSARnReg */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-5 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE650801CUL, + /* END Msg(2:3432)-5 */ + /* END Msg(2:0306)-1 */ + + /* *pICCCRnReg */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-5 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6508018UL, + /* END Msg(2:3432)-5 */ + /* END Msg(2:0306)-1 */ + + /* *pICCCR2nReg */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-5 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6508028UL, + /* END Msg(2:3432)-5 */ + /* END Msg(2:0306)-1 */ + + /* *pICMPRnReg */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-5 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE650802CUL, + /* END Msg(2:3432)-5 */ + /* END Msg(2:0306)-1 */ + + /* *pICHPRnReg */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-5 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6508030UL, + /* END Msg(2:3432)-5 */ + /* END Msg(2:0306)-1 */ + + /* *pICLPRnReg */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-5 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6508034UL, + /* END Msg(2:3432)-5 */ + /* END Msg(2:0306)-1 */ + + /* *pICDMAERnReg */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-5 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE650803CUL, + /* END Msg(2:3432)-5 */ + /* END Msg(2:0306)-1 */ + + /* *pICFBSCRnReg */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-5 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6508038UL, + /* END Msg(2:3432)-5 */ + /* END Msg(2:0306)-1 */ + + /* *pDmaConfiguration */ + NULL_PTR, + + /* *pNotification */ + &CddIic_Ch1NoticeCallBack, + + /* *pEnterRegProtect */ + &SchM_Enter_CddIic_CDDIIC_INTERRUPT_CONTROL_PROTECTION, + + /* *pExitRegProtect */ + &SchM_Exit_CddIic_CDDIIC_INTERRUPT_CONTROL_PROTECTION, + + /* *pEnterGlbProtect */ + &SchM_Enter_CddIic_CDDIIC_RAM_DATA_PROTECTION, + + /* *pExitGlbProtect */ + &SchM_Exit_CddIic_CDDIIC_RAM_DATA_PROTECTION, + + /* enInterface */ + CDDIIC_SLAVE_IF, + + /* enDmaMode */ + CDDIIC_DMA_DISABLED + }, + /* Index: 2 - 2 */ + { + /* *pICMCRnReg */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-5 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6510004UL, + /* END Msg(2:3432)-5 */ + /* END Msg(2:0306)-1 */ + + /* *pICMSRnReg */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-5 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE651000CUL, + /* END Msg(2:3432)-5 */ + /* END Msg(2:0306)-1 */ + + /* *pICMIERnReg */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-5 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6510014UL, + /* END Msg(2:3432)-5 */ + /* END Msg(2:0306)-1 */ + + /* *pICMARnReg */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-5 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6510020UL, + /* END Msg(2:3432)-5 */ + /* END Msg(2:0306)-1 */ + + /* *pICTXRXDnReg */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-5 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6510024UL, + /* END Msg(2:3432)-5 */ + /* END Msg(2:0306)-1 */ + + /* *pICSCRnReg */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-5 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6510000UL, + /* END Msg(2:3432)-5 */ + /* END Msg(2:0306)-1 */ + + /* *pICSSRnReg */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-5 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6510008UL, + /* END Msg(2:3432)-5 */ + /* END Msg(2:0306)-1 */ + + /* *pICSIERnReg */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-5 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6510010UL, + /* END Msg(2:3432)-5 */ + /* END Msg(2:0306)-1 */ + + /* *pICSARnReg */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-5 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE651001CUL, + /* END Msg(2:3432)-5 */ + /* END Msg(2:0306)-1 */ + + /* *pICCCRnReg */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-5 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6510018UL, + /* END Msg(2:3432)-5 */ + /* END Msg(2:0306)-1 */ + + /* *pICCCR2nReg */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-5 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6510028UL, + /* END Msg(2:3432)-5 */ + /* END Msg(2:0306)-1 */ + + /* *pICMPRnReg */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-5 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE651002CUL, + /* END Msg(2:3432)-5 */ + /* END Msg(2:0306)-1 */ + + /* *pICHPRnReg */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-5 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6510030UL, + /* END Msg(2:3432)-5 */ + /* END Msg(2:0306)-1 */ + + /* *pICLPRnReg */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-5 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6510034UL, + /* END Msg(2:3432)-5 */ + /* END Msg(2:0306)-1 */ + + /* *pICDMAERnReg */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-5 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE651003CUL, + /* END Msg(2:3432)-5 */ + /* END Msg(2:0306)-1 */ + + /* *pICFBSCRnReg */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-5 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE6510038UL, + /* END Msg(2:3432)-5 */ + /* END Msg(2:0306)-1 */ + + /* *pDmaConfiguration */ + NULL_PTR, + + /* *pNotification */ + &CddIic_Ch2NoticeCallBack, + + /* *pEnterRegProtect */ + &SchM_Enter_CddIic_CDDIIC_INTERRUPT_CONTROL_PROTECTION, + + /* *pExitRegProtect */ + &SchM_Exit_CddIic_CDDIIC_INTERRUPT_CONTROL_PROTECTION, + + /* *pEnterGlbProtect */ + &SchM_Enter_CddIic_CDDIIC_RAM_DATA_PROTECTION, + + /* *pExitGlbProtect */ + &SchM_Exit_CddIic_CDDIIC_RAM_DATA_PROTECTION, + + /* enInterface */ + CDDIIC_MASTER_IF, + + /* enDmaMode */ + CDDIIC_DMA_DISABLED + }, + /* Index: 3 - 3 */ + { + /* *pICMCRnReg */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-5 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE66D0004UL, + /* END Msg(2:3432)-5 */ + /* END Msg(2:0306)-1 */ + + /* *pICMSRnReg */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-5 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE66D000CUL, + /* END Msg(2:3432)-5 */ + /* END Msg(2:0306)-1 */ + + /* *pICMIERnReg */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-5 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE66D0014UL, + /* END Msg(2:3432)-5 */ + /* END Msg(2:0306)-1 */ + + /* *pICMARnReg */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-5 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE66D0020UL, + /* END Msg(2:3432)-5 */ + /* END Msg(2:0306)-1 */ + + /* *pICTXRXDnReg */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-5 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE66D0024UL, + /* END Msg(2:3432)-5 */ + /* END Msg(2:0306)-1 */ + + /* *pICSCRnReg */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-5 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE66D0000UL, + /* END Msg(2:3432)-5 */ + /* END Msg(2:0306)-1 */ + + /* *pICSSRnReg */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-5 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE66D0008UL, + /* END Msg(2:3432)-5 */ + /* END Msg(2:0306)-1 */ + + /* *pICSIERnReg */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-5 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE66D0010UL, + /* END Msg(2:3432)-5 */ + /* END Msg(2:0306)-1 */ + + /* *pICSARnReg */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-5 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE66D001CUL, + /* END Msg(2:3432)-5 */ + /* END Msg(2:0306)-1 */ + + /* *pICCCRnReg */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-5 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE66D0018UL, + /* END Msg(2:3432)-5 */ + /* END Msg(2:0306)-1 */ + + /* *pICCCR2nReg */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-5 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE66D0028UL, + /* END Msg(2:3432)-5 */ + /* END Msg(2:0306)-1 */ + + /* *pICMPRnReg */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-5 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE66D002CUL, + /* END Msg(2:3432)-5 */ + /* END Msg(2:0306)-1 */ + + /* *pICHPRnReg */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-5 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE66D0030UL, + /* END Msg(2:3432)-5 */ + /* END Msg(2:0306)-1 */ + + /* *pICLPRnReg */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-5 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE66D0034UL, + /* END Msg(2:3432)-5 */ + /* END Msg(2:0306)-1 */ + + /* *pICDMAERnReg */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-5 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE66D003CUL, + /* END Msg(2:3432)-5 */ + /* END Msg(2:0306)-1 */ + + /* *pICFBSCRnReg */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-5 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE66D0038UL, + /* END Msg(2:3432)-5 */ + /* END Msg(2:0306)-1 */ + + /* *pDmaConfiguration */ + NULL_PTR, + + /* *pNotification */ + &CddIic_Ch3NoticeCallBack, + + /* *pEnterRegProtect */ + &SchM_Enter_CddIic_CDDIIC_INTERRUPT_CONTROL_PROTECTION, + + /* *pExitRegProtect */ + &SchM_Exit_CddIic_CDDIIC_INTERRUPT_CONTROL_PROTECTION, + + /* *pEnterGlbProtect */ + &SchM_Enter_CddIic_CDDIIC_RAM_DATA_PROTECTION, + + /* *pExitGlbProtect */ + &SchM_Exit_CddIic_CDDIIC_RAM_DATA_PROTECTION, + + /* enInterface */ + CDDIIC_MASTER_IF, + + /* enDmaMode */ + CDDIIC_DMA_DISABLED + }, + /* Index: 4 - 4 */ + { + /* *pICMCRnReg */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-5 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE66D8004UL, + /* END Msg(2:3432)-5 */ + /* END Msg(2:0306)-1 */ + + /* *pICMSRnReg */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-5 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE66D800CUL, + /* END Msg(2:3432)-5 */ + /* END Msg(2:0306)-1 */ + + /* *pICMIERnReg */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-5 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE66D8014UL, + /* END Msg(2:3432)-5 */ + /* END Msg(2:0306)-1 */ + + /* *pICMARnReg */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-5 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE66D8020UL, + /* END Msg(2:3432)-5 */ + /* END Msg(2:0306)-1 */ + + /* *pICTXRXDnReg */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-5 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE66D8024UL, + /* END Msg(2:3432)-5 */ + /* END Msg(2:0306)-1 */ + + /* *pICSCRnReg */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-5 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE66D8000UL, + /* END Msg(2:3432)-5 */ + /* END Msg(2:0306)-1 */ + + /* *pICSSRnReg */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-5 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE66D8008UL, + /* END Msg(2:3432)-5 */ + /* END Msg(2:0306)-1 */ + + /* *pICSIERnReg */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-5 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE66D8010UL, + /* END Msg(2:3432)-5 */ + /* END Msg(2:0306)-1 */ + + /* *pICSARnReg */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-5 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE66D801CUL, + /* END Msg(2:3432)-5 */ + /* END Msg(2:0306)-1 */ + + /* *pICCCRnReg */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-5 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE66D8018UL, + /* END Msg(2:3432)-5 */ + /* END Msg(2:0306)-1 */ + + /* *pICCCR2nReg */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-5 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE66D8028UL, + /* END Msg(2:3432)-5 */ + /* END Msg(2:0306)-1 */ + + /* *pICMPRnReg */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-5 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE66D802CUL, + /* END Msg(2:3432)-5 */ + /* END Msg(2:0306)-1 */ + + /* *pICHPRnReg */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-5 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE66D8030UL, + /* END Msg(2:3432)-5 */ + /* END Msg(2:0306)-1 */ + + /* *pICLPRnReg */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-5 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE66D8034UL, + /* END Msg(2:3432)-5 */ + /* END Msg(2:0306)-1 */ + + /* *pICDMAERnReg */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-5 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE66D803CUL, + /* END Msg(2:3432)-5 */ + /* END Msg(2:0306)-1 */ + + /* *pICFBSCRnReg */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-5 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE66D8038UL, + /* END Msg(2:3432)-5 */ + /* END Msg(2:0306)-1 */ + + /* *pDmaConfiguration */ + NULL_PTR, + + /* *pNotification */ + &CddIic_Ch4NoticeCallBack, + + /* *pEnterRegProtect */ + &SchM_Enter_CddIic_CDDIIC_INTERRUPT_CONTROL_PROTECTION, + + /* *pExitRegProtect */ + &SchM_Exit_CddIic_CDDIIC_INTERRUPT_CONTROL_PROTECTION, + + /* *pEnterGlbProtect */ + &SchM_Enter_CddIic_CDDIIC_RAM_DATA_PROTECTION, + + /* *pExitGlbProtect */ + &SchM_Exit_CddIic_CDDIIC_RAM_DATA_PROTECTION, + + /* enInterface */ + CDDIIC_MASTER_IF, + + /* enDmaMode */ + CDDIIC_DMA_DISABLED + }, + /* Index: 5 - 5 */ + { + /* *pICMCRnReg */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-5 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE66E0004UL, + /* END Msg(2:3432)-5 */ + /* END Msg(2:0306)-1 */ + + /* *pICMSRnReg */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-5 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE66E000CUL, + /* END Msg(2:3432)-5 */ + /* END Msg(2:0306)-1 */ + + /* *pICMIERnReg */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-5 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE66E0014UL, + /* END Msg(2:3432)-5 */ + /* END Msg(2:0306)-1 */ + + /* *pICMARnReg */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-5 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE66E0020UL, + /* END Msg(2:3432)-5 */ + /* END Msg(2:0306)-1 */ + + /* *pICTXRXDnReg */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-5 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE66E0024UL, + /* END Msg(2:3432)-5 */ + /* END Msg(2:0306)-1 */ + + /* *pICSCRnReg */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-5 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE66E0000UL, + /* END Msg(2:3432)-5 */ + /* END Msg(2:0306)-1 */ + + /* *pICSSRnReg */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-5 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE66E0008UL, + /* END Msg(2:3432)-5 */ + /* END Msg(2:0306)-1 */ + + /* *pICSIERnReg */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-5 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE66E0010UL, + /* END Msg(2:3432)-5 */ + /* END Msg(2:0306)-1 */ + + /* *pICSARnReg */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-5 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE66E001CUL, + /* END Msg(2:3432)-5 */ + /* END Msg(2:0306)-1 */ + + /* *pICCCRnReg */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-5 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE66E0018UL, + /* END Msg(2:3432)-5 */ + /* END Msg(2:0306)-1 */ + + /* *pICCCR2nReg */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-5 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE66E0028UL, + /* END Msg(2:3432)-5 */ + /* END Msg(2:0306)-1 */ + + /* *pICMPRnReg */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-5 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE66E002CUL, + /* END Msg(2:3432)-5 */ + /* END Msg(2:0306)-1 */ + + /* *pICHPRnReg */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-5 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE66E0030UL, + /* END Msg(2:3432)-5 */ + /* END Msg(2:0306)-1 */ + + /* *pICLPRnReg */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-5 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE66E0034UL, + /* END Msg(2:3432)-5 */ + /* END Msg(2:0306)-1 */ + + /* *pICDMAERnReg */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-5 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE66E003CUL, + /* END Msg(2:3432)-5 */ + /* END Msg(2:0306)-1 */ + + /* *pICFBSCRnReg */ + /* MISRA Violation: START Msg(2:0306)-1 */ + /* MISRA Violation: START Msg(2:3432)-5 */ + (P2VAR(uint32, TYPEDEF, REGSPACE)) 0xE66E0038UL, + /* END Msg(2:3432)-5 */ + /* END Msg(2:0306)-1 */ + + /* *pDmaConfiguration */ + NULL_PTR, + + /* *pNotification */ + &CddIic_Ch5NoticeCallBack, + + /* *pEnterRegProtect */ + &SchM_Enter_CddIic_CDDIIC_INTERRUPT_CONTROL_PROTECTION, + + /* *pExitRegProtect */ + &SchM_Exit_CddIic_CDDIIC_INTERRUPT_CONTROL_PROTECTION, + + /* *pEnterGlbProtect */ + &SchM_Enter_CddIic_CDDIIC_RAM_DATA_PROTECTION, + + /* *pExitGlbProtect */ + &SchM_Exit_CddIic_CDDIIC_RAM_DATA_PROTECTION, + + /* enInterface */ + CDDIIC_MASTER_IF, + + /* enDmaMode */ + CDDIIC_DMA_DISABLED + } +}; +/* END Msg(1:1504)-7 */ + +/* Global array for slave configuration structure */ +/* QAC Warning: START Msg(1:1502)-7 */ +CONST(CddIic_SlaveConfigType, CDDIIC_CONFIG_DATA) CddIic_GaaSlaveConfig[] = +{ + /* Index: 0 - 0 */ + { + /* ulSCLHighPeriod */ + 0x0000008CUL, + + /* ulSCLLowPeriod */ + 0x0000007DUL, + + /* ulTargetClockFreq */ + 0x000DBBA0UL, + + /* ulExtLoadTime */ + 0x00000001UL, + + /* ucSlaveAddress */ + 0x03DU, + + /* ucSlaveID */ + 0x000U, + + /* ucFisrtBitSetupCycle */ + 0x0DU, + + /* ucSclClkGenDiv */ + 0x00U, + + /* enAddressMode */ + CDDIIC_SEVEN_BIT_ADDR, + + /* enClockMode */ + CDDIIC_FIXED_DUTY + } +}; +/* END Msg(1:1502)-7 */ + +/* Global array for DMA configuration structure */ + +#define CDDIIC_STOP_SEC_CONFIG_DATA_32 +/* QAC Warning: START Msg(4:5087)-3 */ +#include "CddIic_MemMap.h" +/* END Msg(4:5087)-3 */ + + +/******************************************************************************* +** Function Definitions ** +*******************************************************************************/ + +/******************************************************************************* +** End of File ** +*******************************************************************************/ + diff --git a/Src/Gen4_R-Car_MCAL/2_Trunk/V4H/MCAL-v4h_19.4.0.D_release/rel/modules/cddipmmu/sample_application/V4H/19_11/include/CDD_Ipmmu_Cbk.h b/Src/Gen4_R-Car_MCAL/2_Trunk/V4H/MCAL-v4h_19.4.0.D_release/rel/modules/cddipmmu/sample_application/V4H/19_11/include/CDD_Ipmmu_Cbk.h new file mode 100644 index 00000000..069580f2 --- /dev/null +++ b/Src/Gen4_R-Car_MCAL/2_Trunk/V4H/MCAL-v4h_19.4.0.D_release/rel/modules/cddipmmu/sample_application/V4H/19_11/include/CDD_Ipmmu_Cbk.h @@ -0,0 +1,148 @@ +/*============================================================================*/ +/* Project = AUTOSAR Renesas MCAL Components */ +/* Module = CDD_Ipmmu_Cbk.h */ +/*============================================================================*/ +/* COPYRIGHT */ +/*============================================================================*/ +/* Copyright(c) 2026 Renesas Electronics Corporation. */ +/*============================================================================*/ +/* Purpose: */ +/* This file contains callback function for IPMMU */ +/* AUTOMATICALLY GENERATED FILE - DO NOT EDIT */ +/* */ +/*============================================================================*/ +/* */ +/* Unless otherwise agreed upon in writing between your company and */ +/* Renesas Electronics Corporation the following shall apply! */ +/* */ +/* Warranty Disclaimer */ +/* */ +/* There is no warranty of any kind whatsoever granted by Renesas. Any */ +/* warranty is expressly disclaimed and excluded by Renesas, either expressed */ +/* or implied, including but not limited to those for non-infringement of */ +/* intellectual property, merchantability and/or fitness for the particular */ +/* purpose. */ +/* */ +/* Renesas shall not have any obligation to maintain, service or provide bug */ +/* fixes for the supplied Product(s) and/or the Application. */ +/* */ +/* Each User is solely responsible for determining the appropriateness of */ +/* using the Product(s) and assumes all risks associated with its exercise */ +/* of rights under this Agreement, including, but not limited to the risks */ +/* and costs of program errors, compliance with applicable laws, damage to */ +/* or loss of data, programs or equipment, and unavailability or */ +/* interruption of operations. */ +/* */ +/* Limitation of Liability */ +/* */ +/* In no event shall Renesas be liable to the User for any incidental, */ +/* consequential, indirect, or punitive damage (including but not limited */ +/* to lost profits) regardless of whether such liability is based on breach */ +/* of contract, tort, strict liability, breach of warranties, failure of */ +/* essential purpose or otherwise and even if advised of the possibility of */ +/* such damages. Renesas shall not be liable for any services or products */ +/* provided by third party vendors, developers or consultants identified or */ +/* referred to the User by Renesas in connection with the Product(s) and/or */ +/* the Application. */ +/* */ +/*============================================================================*/ +/* Environment: */ +/* Devices: V4H */ +/*============================================================================*/ + + +/******************************************************************************* +** Revision Control History ** +*******************************************************************************/ + + + +/******************************************************************************* +** Generation Tool Version ** +*******************************************************************************/ +/* */ +/* TOOL VERSION: CddIpmmuRCAR.dll version: 1.0.7, MCALConfGen.exe version: 1.2.3 */ +/* */ + + +/******************************************************************************* +** Input File ** +*******************************************************************************/ +/* + * INPUT FILE: C:\Work\Src\Gen4_R-Car_MCAL\2_Trunk\V4H\MCAL-v4h_19.4.0.D_release\rel\modules\cddipmmu\sample_application\V4H\19_11\config\App_CDD_IPMMU_V4H_Sample.arxml + * C:\Work\Src\Gen4_R-Car_MCAL\2_Trunk\V4H\MCAL-v4h_19.4.0.D_release\rel\modules\cddipmmu\generator\V4H\R1911_CDD_IPMMU_V4H_BSWMDT.arxml + * C:\Work\Src\Gen4_R-Car_MCAL\2_Trunk\V4H\MCAL-v4h_19.4.0.D_release\rel\common\generic\stubs\19_11\Dem\xml\Dem_CDD_Ipmmu.arxml + * C:\Work\Src\Gen4_R-Car_MCAL\2_Trunk\V4H\MCAL-v4h_19.4.0.D_release\rel\V4H\common_family\generator\arm\Sample_Application_V4H.trxml + * GENERATED ON: 19 6 2026 - 05:12:41 + */ + + +#ifndef CDD_IPMMU_CBK_H +#define CDD_IPMMU_CBK_H + + +/******************************************************************************* +** Include Section ** +*******************************************************************************/ + +/******************************************************************************* +** Version Information ** +*******************************************************************************/ +/* AUTOSAR release version information */ +#define CDDIPMMU_CBK_AR_RELEASE_MAJOR_VERSION 4U +#define CDDIPMMU_CBK_AR_RELEASE_MINOR_VERSION 5U +#define CDDIPMMU_CBK_AR_RELEASE_REVISION_VERSION 0U + +/* File version information */ +#define CDDIPMMU_CBK_SW_MAJOR_VERSION 1U +#define CDDIPMMU_CBK_SW_MINOR_VERSION 0U + +/******************************************************************************* +** Global Symbols ** +*******************************************************************************/ + + + +/******************************************************************************* +** Global Data Types ** +*******************************************************************************/ + + + +/******************************************************************************* +** Global Data ** +*******************************************************************************/ + + + +/******************************************************************************* +** Function Prototypes ** +*******************************************************************************/ + + +#define CDDIPMMU_START_SEC_APPL_CODE +#include "CddIpmmu_MemMap.h" + +extern FUNC(void, CDDIPMMU_APPL_CODE) CddIpmmu_MmuCallBackFunction0 +( + uint8 Mmu, + CddIpmmu_ErrorCodeType ErrorCode, + boolean MultiHit, + boolean Abort, + boolean PageFault, + boolean TransFault, + uint32 ErrorAddr, + uint8 UpperErrorAddr +); + +#define CDDIPMMU_STOP_SEC_APPL_CODE +#include "CddIpmmu_MemMap.h" + + +#endif /* CDD_IPMMU_CBK_H */ + + +/******************************************************************************* +** End of File ** +*******************************************************************************/ + diff --git a/Src/Gen4_R-Car_MCAL/2_Trunk/V4H/MCAL-v4h_19.4.0.D_release/rel/modules/cddipmmu/sample_application/V4H/19_11/include/CDD_Ipmmu_Cfg.h b/Src/Gen4_R-Car_MCAL/2_Trunk/V4H/MCAL-v4h_19.4.0.D_release/rel/modules/cddipmmu/sample_application/V4H/19_11/include/CDD_Ipmmu_Cfg.h new file mode 100644 index 00000000..ceea19a2 --- /dev/null +++ b/Src/Gen4_R-Car_MCAL/2_Trunk/V4H/MCAL-v4h_19.4.0.D_release/rel/modules/cddipmmu/sample_application/V4H/19_11/include/CDD_Ipmmu_Cfg.h @@ -0,0 +1,190 @@ +/*============================================================================*/ +/* Project = AUTOSAR Renesas MCAL Components */ +/* Module = CDD_Ipmmu_Cfg.h */ +/*============================================================================*/ +/* COPYRIGHT */ +/*============================================================================*/ +/* Copyright(c) 2026 Renesas Electronics Corporation. */ +/*============================================================================*/ +/* Purpose: */ +/* This file contains pre-compile time parameters */ +/* AUTOMATICALLY GENERATED FILE - DO NOT EDIT */ +/* */ +/*============================================================================*/ +/* */ +/* Unless otherwise agreed upon in writing between your company and */ +/* Renesas Electronics Corporation the following shall apply! */ +/* */ +/* Warranty Disclaimer */ +/* */ +/* There is no warranty of any kind whatsoever granted by Renesas. Any */ +/* warranty is expressly disclaimed and excluded by Renesas, either expressed */ +/* or implied, including but not limited to those for non-infringement of */ +/* intellectual property, merchantability and/or fitness for the particular */ +/* purpose. */ +/* */ +/* Renesas shall not have any obligation to maintain, service or provide bug */ +/* fixes for the supplied Product(s) and/or the Application. */ +/* */ +/* Each User is solely responsible for determining the appropriateness of */ +/* using the Product(s) and assumes all risks associated with its exercise */ +/* of rights under this Agreement, including, but not limited to the risks */ +/* and costs of program errors, compliance with applicable laws, damage to */ +/* or loss of data, programs or equipment, and unavailability or */ +/* interruption of operations. */ +/* */ +/* Limitation of Liability */ +/* */ +/* In no event shall Renesas be liable to the User for any incidental, */ +/* consequential, indirect, or punitive damage (including but not limited */ +/* to lost profits) regardless of whether such liability is based on breach */ +/* of contract, tort, strict liability, breach of warranties, failure of */ +/* essential purpose or otherwise and even if advised of the possibility of */ +/* such damages. Renesas shall not be liable for any services or products */ +/* provided by third party vendors, developers or consultants identified or */ +/* referred to the User by Renesas in connection with the Product(s) and/or */ +/* the Application. */ +/* */ +/*============================================================================*/ +/* Environment: */ +/* Devices: V4H */ +/*============================================================================*/ + + +/******************************************************************************* +** Revision Control History ** +*******************************************************************************/ + + + +/******************************************************************************* +** Generation Tool Version ** +*******************************************************************************/ +/* */ +/* TOOL VERSION: CddIpmmuRCAR.dll version: 1.0.7, MCALConfGen.exe version: 1.2.3 */ +/* */ + + +/******************************************************************************* +** Input File ** +*******************************************************************************/ +/* + * INPUT FILE: C:\Work\Src\Gen4_R-Car_MCAL\2_Trunk\V4H\MCAL-v4h_19.4.0.D_release\rel\modules\cddipmmu\sample_application\V4H\19_11\config\App_CDD_IPMMU_V4H_Sample.arxml + * C:\Work\Src\Gen4_R-Car_MCAL\2_Trunk\V4H\MCAL-v4h_19.4.0.D_release\rel\modules\cddipmmu\generator\V4H\R1911_CDD_IPMMU_V4H_BSWMDT.arxml + * C:\Work\Src\Gen4_R-Car_MCAL\2_Trunk\V4H\MCAL-v4h_19.4.0.D_release\rel\common\generic\stubs\19_11\Dem\xml\Dem_CDD_Ipmmu.arxml + * C:\Work\Src\Gen4_R-Car_MCAL\2_Trunk\V4H\MCAL-v4h_19.4.0.D_release\rel\V4H\common_family\generator\arm\Sample_Application_V4H.trxml + * GENERATED ON: 19 6 2026 - 05:12:41 + */ + + +#ifndef CDD_IPMMU_CFG_H +#define CDD_IPMMU_CFG_H + + +/******************************************************************************* +** Include Section ** +*******************************************************************************/ + +/******************************************************************************* +** Version Information ** +*******************************************************************************/ +/* AUTOSAR release version information */ +#define CDDIPMMU_CFG_AR_RELEASE_MAJOR_VERSION 4U +#define CDDIPMMU_CFG_AR_RELEASE_MINOR_VERSION 5U +#define CDDIPMMU_CFG_AR_RELEASE_REVISION_VERSION 0U + +/* File version information */ +#define CDDIPMMU_CFG_SW_MAJOR_VERSION 1U +#define CDDIPMMU_CFG_SW_MINOR_VERSION 0U + +/******************************************************************************* +** Common Published Information ** +*******************************************************************************/ +#define CDDIPMMU_AR_RELEASE_MAJOR_VERSION_VALUE 4U +#define CDDIPMMU_AR_RELEASE_MINOR_VERSION_VALUE 5U +#define CDDIPMMU_AR_RELEASE_REVISION_VERSION_VALUE 0U + +#define CDDIPMMU_SW_MAJOR_VERSION_VALUE 1U +#define CDDIPMMU_SW_MINOR_VERSION_VALUE 0U +#define CDDIPMMU_SW_PATCH_VERSION_VALUE 8U + +#define CDDIPMMU_VENDOR_ID_VALUE 59U +#define CDDIPMMU_MODULE_ID_VALUE 255U + +/******************************************************************************* +** Global Symbols ** +*******************************************************************************/ + + +/* Pre-compile option for Version information */ +#define CDDIPMMU_AR_VERSION CDDIPMMU_AR_1911_VERSION + +/* Pre-compile option for Instance ID of the CDDIPMMU Driver */ +#define CDDIPMMU_INSTANCE_ID_VALUE 0x0U + +/* Supported Device Name */ +#define CDDIPMMU_DEVICE_NAME V4H + +/* Pre-compile option for Development Error Detect */ +#define CDDIPMMU_DEV_ERROR_DETECT STD_OFF + +/* Pre-compile option for Critical Section */ +#define CDDIPMMU_CRITICAL_SECTION_PROTECTION STD_ON + +/* Pre-compile option for selection register read-back functionality of */ +/* static and dynamic registers */ +#define CDDIPMMU_WRITE_VERIFY_CHECK STD_ON + +/* Pre-compile option for Already Init Check */ +#define CDDIPMMU_ALREADY_INIT_DET_CHECK STD_ON + +/* Pre-compile option for Dependencies Version Check */ +#define CDDIPMMU_VERSION_CHECK_EXT_MODULES STD_ON + +/* Pre-compile option for selection enable or disable unintended interrupt */ +/* detection */ +#define CDDIPMMU_UNINTENDED_INTERRUPT_CHECK STD_ON + +/* Pre-compile option for EDC Error Detect */ +#define CDDIPMMU_EDC_ERROR_DETECT STD_ON + +/* Pre-compile option for IR Domain support */ +#define CDDIPMMU_IR_DOMAIN_SUPPORT STD_ON + +/* Pre-compile option for Version Info API */ +#define CDDIPMMU_VERSION_INFO_API STD_ON + +/* Pre-compile option for DEM Register Write Verify Error Event */ +#define CDDIPMMU_E_WRITE_VERIFY_FAILURE \ + DemConf_DemEventParameter_CDDIPMMU_E_WRITE_VERIFY_FAILURE + +/* Pre-compile option for DEM Unintended Interrupt Check Error Event */ +#define CDDIPMMU_E_INTERRUPT_CONTROLLER_FAILURE \ + DemConf_DemEventParameter_CDDIPMMU_E_INTERRUPT_CONTROLLER_FAILURE + + +/******************************************************************************* +** Global Data Types ** +*******************************************************************************/ + + + +/******************************************************************************* +** Global Data ** +*******************************************************************************/ + + + +/******************************************************************************* +** Function Prototypes ** +*******************************************************************************/ + + + +#endif /* CDD_IPMMU_CFG_H */ + + +/******************************************************************************* +** End of File ** +*******************************************************************************/ + diff --git a/Src/Gen4_R-Car_MCAL/2_Trunk/V4H/MCAL-v4h_19.4.0.D_release/rel/modules/cddipmmu/sample_application/V4H/19_11/include/CDD_Ipmmu_Hardware.h b/Src/Gen4_R-Car_MCAL/2_Trunk/V4H/MCAL-v4h_19.4.0.D_release/rel/modules/cddipmmu/sample_application/V4H/19_11/include/CDD_Ipmmu_Hardware.h new file mode 100644 index 00000000..6485f1a5 --- /dev/null +++ b/Src/Gen4_R-Car_MCAL/2_Trunk/V4H/MCAL-v4h_19.4.0.D_release/rel/modules/cddipmmu/sample_application/V4H/19_11/include/CDD_Ipmmu_Hardware.h @@ -0,0 +1,1091 @@ +/*============================================================================*/ +/* Project = AUTOSAR Renesas MCAL Components */ +/* Module = CDD_Ipmmu_Hardware.h */ +/*============================================================================*/ +/* COPYRIGHT */ +/*============================================================================*/ +/* Copyright(c) 2026 Renesas Electronics Corporation. */ +/*============================================================================*/ +/* Purpose: */ +/* This file contains hardware base address and some structure used in IPMMU */ +/* AUTOMATICALLY GENERATED FILE - DO NOT EDIT */ +/* */ +/*============================================================================*/ +/* */ +/* Unless otherwise agreed upon in writing between your company and */ +/* Renesas Electronics Corporation the following shall apply! */ +/* */ +/* Warranty Disclaimer */ +/* */ +/* There is no warranty of any kind whatsoever granted by Renesas. Any */ +/* warranty is expressly disclaimed and excluded by Renesas, either expressed */ +/* or implied, including but not limited to those for non-infringement of */ +/* intellectual property, merchantability and/or fitness for the particular */ +/* purpose. */ +/* */ +/* Renesas shall not have any obligation to maintain, service or provide bug */ +/* fixes for the supplied Product(s) and/or the Application. */ +/* */ +/* Each User is solely responsible for determining the appropriateness of */ +/* using the Product(s) and assumes all risks associated with its exercise */ +/* of rights under this Agreement, including, but not limited to the risks */ +/* and costs of program errors, compliance with applicable laws, damage to */ +/* or loss of data, programs or equipment, and unavailability or */ +/* interruption of operations. */ +/* */ +/* Limitation of Liability */ +/* */ +/* In no event shall Renesas be liable to the User for any incidental, */ +/* consequential, indirect, or punitive damage (including but not limited */ +/* to lost profits) regardless of whether such liability is based on breach */ +/* of contract, tort, strict liability, breach of warranties, failure of */ +/* essential purpose or otherwise and even if advised of the possibility of */ +/* such damages. Renesas shall not be liable for any services or products */ +/* provided by third party vendors, developers or consultants identified or */ +/* referred to the User by Renesas in connection with the Product(s) and/or */ +/* the Application. */ +/* */ +/*============================================================================*/ +/* Environment: */ +/* Devices: V4H */ +/*============================================================================*/ + + +/******************************************************************************* +** Revision Control History ** +*******************************************************************************/ + + + +/******************************************************************************* +** Generation Tool Version ** +*******************************************************************************/ +/* */ +/* TOOL VERSION: CddIpmmuRCAR.dll version: 1.0.7, MCALConfGen.exe version: 1.2.3 */ +/* */ + + +/******************************************************************************* +** Input File ** +*******************************************************************************/ +/* + * INPUT FILE: C:\Work\Src\Gen4_R-Car_MCAL\2_Trunk\V4H\MCAL-v4h_19.4.0.D_release\rel\modules\cddipmmu\sample_application\V4H\19_11\config\App_CDD_IPMMU_V4H_Sample.arxml + * C:\Work\Src\Gen4_R-Car_MCAL\2_Trunk\V4H\MCAL-v4h_19.4.0.D_release\rel\modules\cddipmmu\generator\V4H\R1911_CDD_IPMMU_V4H_BSWMDT.arxml + * C:\Work\Src\Gen4_R-Car_MCAL\2_Trunk\V4H\MCAL-v4h_19.4.0.D_release\rel\common\generic\stubs\19_11\Dem\xml\Dem_CDD_Ipmmu.arxml + * C:\Work\Src\Gen4_R-Car_MCAL\2_Trunk\V4H\MCAL-v4h_19.4.0.D_release\rel\V4H\common_family\generator\arm\Sample_Application_V4H.trxml + * GENERATED ON: 19 6 2026 - 05:12:42 + */ + + +#ifndef CDD_IPMMU_HARDWARE_H +#define CDD_IPMMU_HARDWARE_H + + +/******************************************************************************* +** Include Section ** +*******************************************************************************/ + +/******************************************************************************* +** MISRA C Rule Violations ** +*******************************************************************************/ +/* 1. MISRA C RULE VIOLATION: */ +/* Message : (2:3472) All toplevel uses of this function-like macro */ +/* look like they could be replaced by */ +/* equivalent function calls. */ +/* Rule : MISRA C:2012 Dir-4.9 */ +/* Justification : This message indicates that a candidate macro may be */ +/* suitable for replacement by a function, based on an */ +/* actual call-site and the arguments passed to it there */ +/* Verification : However, part of the code is verified manually and it is */ +/* not having any impact. */ +/* Reference : Look for START Msg(2:3472)-1 and */ +/* END Msg(2:3472)-1 tags in the code. */ +/******************************************************************************/ +/* 2. MISRA C RULE VIOLATION: */ +/* Message : (2:0750) A union type specifier has been defined. */ +/* Rule : MISRA C:2012 Rule-19.2, CWE-843 */ +/* Justification : This union type is used for register accessing */ +/* and there is no issue with this usage.. */ +/* Verification : However, part of the code is verified manually and it is */ +/* not having any impact. */ +/* Reference : Look for START Msg(2:0750)-2 and */ +/* END Msg(2:0750)-2 tags in the code. */ +/******************************************************************************/ +/* 3. MISRA C RULE VIOLATION: */ +/* Message : (2:0635) [E] Bit-field %s in %s has been declared */ +/* with a type not explicitly supported. */ +/* Rule : MISRA C:2012 Dir-1.1, Rule-1.2, Rule-6.1 */ +/* Justification : To access bit wise from register. */ +/* Verification : However, part of the code is verified manually and it is */ +/* not having any impact. */ +/* Reference : Look for START Msg(2:0635)-3 and */ +/* END Msg(2:0635)-3 tags in the code. */ +/******************************************************************************/ +/* 4. MISRA C RULE VIOLATION: */ +/* Message : (7:0791) [U] Macro identifier does not differ from other */ +/* macro identifier(s) */ +/* Rule : MISRA C:2012 Rule-5.4 */ +/* Justification : This macro identifier is following AUTOSAR standard rule */ +/* (Symbolic Name or Published Macro's name), so this is */ +/* accepted. */ +/* Verification : However, part of the code is verified manually and it is */ +/* not having any impact. */ +/* Reference : Look for START Msg(7:0791)-4 and */ +/* END Msg(7:0791)-4 tags in the code. */ +/******************************************************************************/ + + +/******************************************************************************* +** Version Information ** +*******************************************************************************/ +/* AUTOSAR release version information */ +#define CDDIPMMU_HDR_AR_RELEASE_MAJOR_VERSION 4U +#define CDDIPMMU_HDR_AR_RELEASE_MINOR_VERSION 5U +#define CDDIPMMU_HDR_AR_RELEASE_REVISION_VERSION 0U + +/* File version information */ +#define CDDIPMMU_HDR_SW_MAJOR_VERSION 1U +#define CDDIPMMU_HDR_SW_MINOR_VERSION 0U + +/******************************************************************************* +** Global Symbols ** +*******************************************************************************/ + + +/* Base Address (each BUS-Domain) */ +#define CDD_IPMMU_REG_BADRR_MM (uint32)0xEEFC0000UL +#define CDD_IPMMU_REG_BADRR_VI0 (uint32)0xEEE80000UL +#define CDD_IPMMU_REG_BADRR_IR (uint32)0xEED80000UL +#define CDD_IPMMU_REG_BADRR_RT (uint32)0xEE480000UL +#define CDD_IPMMU_REG_BADRR_VC0 (uint32)0xEEDC0000UL +#define CDD_IPMMU_REG_BADRR_VI1 (uint32)0xEEEC0000UL +#define CDD_IPMMU_REG_BADRR_VIP0 (uint32)0xEEF00000UL +#define CDD_IPMMU_REG_BADRR_VIP1 (uint32)0xEEF40000UL +#define CDD_IPMMU_REG_BADRR_RT1 (uint32)0xEE4C0000UL +#define CDD_IPMMU_REG_BADRR_3DG (uint32)0xEEE00000UL +#define CDD_IPMMU_REG_BADRR_DS0 (uint32)0xEED00000UL +#define CDD_IPMMU_REG_BADRR_HC (uint32)0xEED40000UL + +/* Register offset */ +#define CDD_IPMMU_REG_OFST_IMCTRnL (uint32)0x00010000UL +#define CDD_IPMMU_REG_OFST_IMTTBCRnL (uint32)0x00010008UL +#define CDD_IPMMU_REG_OFST_IMTTLBR0nL (uint32)0x00010010UL +#define CDD_IPMMU_REG_OFST_IMTTUBR0nL (uint32)0x00010014UL +#define CDD_IPMMU_REG_OFST_IMTTLBR1nL (uint32)0x00010018UL +#define CDD_IPMMU_REG_OFST_IMTTUBR1nL (uint32)0x0001001CUL +#define CDD_IPMMU_REG_OFST_IMSTRnL (uint32)0x00010020UL +#define CDD_IPMMU_REG_OFST_IMMAIR0nL (uint32)0x00010028UL +#define CDD_IPMMU_REG_OFST_IMMAIR1nL (uint32)0x0001002CUL +#define CDD_IPMMU_REG_OFST_IMELARnL (uint32)0x00010030UL +#define CDD_IPMMU_REG_OFST_IMEUARnL (uint32)0x00010034UL +#define CDD_IPMMU_REG_OFST_IMCTRnU (uint32)0x00010800UL +#define CDD_IPMMU_REG_OFST_IMTTBCRnU (uint32)0x00010808UL +#define CDD_IPMMU_REG_OFST_IMTTLBR0nU (uint32)0x00010810UL +#define CDD_IPMMU_REG_OFST_IMTTUBR0nU (uint32)0x00010814UL +#define CDD_IPMMU_REG_OFST_IMTTLBR1nU (uint32)0x00010818UL +#define CDD_IPMMU_REG_OFST_IMTTUBR1nU (uint32)0x0001081CUL +#define CDD_IPMMU_REG_OFST_IMSTRnU (uint32)0x00010820UL +#define CDD_IPMMU_REG_OFST_IMMAIR0nU (uint32)0x00010828UL +#define CDD_IPMMU_REG_OFST_IMMAIR1nU (uint32)0x0001082CUL +#define CDD_IPMMU_REG_OFST_IMELARnU (uint32)0x00010830UL +#define CDD_IPMMU_REG_OFST_IMEUARnU (uint32)0x00010834UL +#define CDD_IPMMU_REG_OFST_IMSCTLR (uint32)0x00001500UL +#define CDD_IPMMU_REG_OFST_IMRAM0ERRCTR0 (uint32)0x000005C0UL +/* MISRA Violation: START Msg(7:0791)-4 */ +#define CDD_IPMMU_REG_OFST_IMRAM0ERRCTR1 (uint32)0x000005C4UL +/* END Msg(7:0791)-4 */ +#define CDD_IPMMU_REG_OFST_IMPCTR (uint32)0x00002200UL +#define CDD_IPMMU_REG_OFST_IMPSTR (uint32)0x00002208UL +#define CDD_IPMMU_REG_OFST_IMPEAR (uint32)0x0000220CUL +#define CDD_IPMMU_REG_OFST_IMPMBAn (uint32)0x00002280UL +#define CDD_IPMMU_REG_OFST_IMPMBDn (uint32)0x000022C0UL +#define CDD_IPMMU_REG_OFST_IMUCTRnL (uint32)0x00003300UL +#define CDD_IPMMU_REG_OFST_MUASIDnL (uint32)0x00003308UL +#define CDD_IPMMU_REG_OFST_IMUCTRnU (uint32)0x00003600UL +#define CDD_IPMMU_REG_OFST_MUASIDnU (uint32)0x00003608UL + +/* Specific macro */ +#define CDD_IPMMU_REG_ENT_MMU 0x00001040UL +#define CDD_IPMMU_REG_ENT_PMB 0x00000004UL +#define CDD_IPMMU_REG_ENT_uTLB 0x00000010UL +#define CDD_IPMMU_ENT_MAX_MMU 0x10U +#define CDD_IPMMU_ENT_MAX_PMB 0x10U +#define CDD_IPMMU_ENT_MAX_UTLB 0x40U +#define CDD_IPMMU_ENT_MAX_UTLB_SPLIT 0x00000020UL +#define CDD_IPMMU_ENT_MAX_MMU_SPLIT 0x00000008UL +#define CDD_IPMMU_REG_ENT_MMU_EXT 0x1000U +#define CDD_IPMMU_REG_ENT_MMU_U 0x00000040UL + +/* Translation Table Selection Value */ +#define CDD_IPMMU_MMU0 (uint8)(0x00U) +#define CDD_IPMMU_MMU1 (uint8)(0x01U) +#define CDD_IPMMU_MMU2 (uint8)(0x02U) +#define CDD_IPMMU_MMU3 (uint8)(0x03U) +#define CDD_IPMMU_MMU4 (uint8)(0x04U) +#define CDD_IPMMU_MMU5 (uint8)(0x05U) +#define CDD_IPMMU_MMU6 (uint8)(0x06U) +#define CDD_IPMMU_MMU7 (uint8)(0x07U) +#define CDD_IPMMU_MMU8 (uint8)(0x08U) +#define CDD_IPMMU_MMU9 (uint8)(0x09U) +#define CDD_IPMMU_MMU10 (uint8)(0x0AU) +#define CDD_IPMMU_MMU11 (uint8)(0x0BU) +#define CDD_IPMMU_MMU12 (uint8)(0x0CU) +#define CDD_IPMMU_MMU13 (uint8)(0x0DU) +#define CDD_IPMMU_MMU14 (uint8)(0x0EU) +#define CDD_IPMMU_MMU15 (uint8)(0x0FU) +#define CDD_IPMMU_PMB (uint8)(0x10U) + +/* Calculate Register Address */ +/* MISRA Violation: START Msg(2:3472)-1 */ +#define CDD_IPMMU_REG_IMCTRn(BA, CH) \ + (((uint32)(CH)