diff --git a/Src/Gen4_R-Car_Vector/2_Trunk/Mobis_V4H/Project_Folder/Surface_EVB/Config/ECUC/Surface_EVB.ecuc.arxml b/Src/Gen4_R-Car_Vector/2_Trunk/Mobis_V4H/Project_Folder/Surface_EVB/Config/ECUC/Surface_EVB.ecuc.arxml
index b6b5d93b..89d5ad6b 100644
--- a/Src/Gen4_R-Car_Vector/2_Trunk/Mobis_V4H/Project_Folder/Surface_EVB/Config/ECUC/Surface_EVB.ecuc.arxml
+++ b/Src/Gen4_R-Car_Vector/2_Trunk/Mobis_V4H/Project_Folder/Surface_EVB/Config/ECUC/Surface_EVB.ecuc.arxml
@@ -10,9 +10,6 @@
/ActiveEcuC/Can
-
- /ActiveEcuC/Cdd
-
/ActiveEcuC/Dio
@@ -37,6 +34,9 @@
/ActiveEcuC/Wdg
+
+ /ActiveEcuC/Cdd
+
diff --git a/Src/Gen4_R-Car_Vector/2_Trunk/Mobis_V4H/Project_Folder/Surface_EVB/Config/ECUC/Surface_EVB_Cdd_Cdd_ecuc.arxml b/Src/Gen4_R-Car_Vector/2_Trunk/Mobis_V4H/Project_Folder/Surface_EVB/Config/ECUC/Surface_EVB_Cdd_Cdd_ecuc.arxml
index 7bdd1dd5..264af647 100644
--- a/Src/Gen4_R-Car_Vector/2_Trunk/Mobis_V4H/Project_Folder/Surface_EVB/Config/ECUC/Surface_EVB_Cdd_Cdd_ecuc.arxml
+++ b/Src/Gen4_R-Car_Vector/2_Trunk/Mobis_V4H/Project_Folder/Surface_EVB/Config/ECUC/Surface_EVB_Cdd_Cdd_ecuc.arxml
@@ -4,7 +4,7 @@
ActiveEcuC
-
+
Cdd
@@ -13,227 +13,12513 @@
- /Renesas/EcucDefs_CddIccom/Cdd
+ /Renesas/EcucDefs_CddEmm/Cdd
VARIANT-POST-BUILD
- /Renesas/BswModuleDescriptions_CddIccom/CddIccom_Impl
+ /Renesas/BswModuleDescriptions_CddEmm/CddEmm_Impl
-
+
CddGeneral
- /Renesas/EcucDefs_CddIccom/Cdd/CddGeneral
+ /Renesas/EcucDefs_CddEmm/Cdd/CddGeneral
- /Renesas/EcucDefs_CddIccom/Cdd/CddGeneral/CddInstanceId
+ /Renesas/EcucDefs_CddEmm/Cdd/CddGeneral/CddInstanceId
0
- /Renesas/EcucDefs_CddIccom/Cdd/CddGeneral/CddIccomVersionInfoApi
- true
-
-
- /Renesas/EcucDefs_CddIccom/Cdd/CddGeneral/CddIccomCriticalSectionProtection
- true
-
-
- /Renesas/EcucDefs_CddIccom/Cdd/CddGeneral/CddIccomDevErrorDetect
+ /Renesas/EcucDefs_CddEmm/Cdd/CddGeneral/CddEmmDevErrorDetect
false
- /Renesas/EcucDefs_CddIccom/Cdd/CddGeneral/CddIccomAlreadyInitDetCheck
+ /Renesas/EcucDefs_CddEmm/Cdd/CddGeneral/CddEmmAlreadyInitDetCheck
true
- /Renesas/EcucDefs_CddIccom/Cdd/CddGeneral/CddIccomDeviceName
+ /Renesas/EcucDefs_CddEmm/Cdd/CddGeneral/CddEmmDeviceName
V4H
- /Renesas/EcucDefs_CddIccom/Cdd/CddGeneral/CddIccomVersionCheckExternalModules
+ /Renesas/EcucDefs_CddEmm/Cdd/CddGeneral/CddEmmVersionCheckExternalModules
true
- /Renesas/EcucDefs_CddIccom/Cdd/CddGeneral/CddIccomUnintendedInterruptCheck
+ /Renesas/EcucDefs_CddEmm/Cdd/CddGeneral/CddEmmCriticalSectionProtection
true
- /Renesas/EcucDefs_CddIccom/Cdd/CddGeneral/CddIccomCrNumber
- 0
-
-
- /Renesas/EcucDefs_CddIccom/Cdd/CddGeneral/CddIccomWriteVerifyCheck
+ /Renesas/EcucDefs_CddEmm/Cdd/CddGeneral/CddEmmVersionInfoApi
true
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddGeneral/CddEmmPseudoErrorApi
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddGeneral/CddEmmUnintendedInterruptCheck
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddGeneral/CddEmmWriteVerifyCheck
+ WV_RUNTIME
+
-
- CddIccomChannel_000
- /Renesas/EcucDefs_CddIccom/Cdd/CddIccomChannel
+
+ CddEmmDomain0
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain0
- /Renesas/EcucDefs_CddIccom/Cdd/CddIccomChannel/CddIccomChannelId
- 0
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain0/CddEmmAddressToSaveErrorStatus
+ 1342177280
-
- /Renesas/EcucDefs_CddIccom/Cdd/CddIccomChannel/CddIccomChannelCtaAddress
- 1207726080
-
-
- /Renesas/EcucDefs_CddIccom/Cdd/CddIccomChannel/CddIccomChannelCtaPartitionSize
- 2048
-
-
- /Renesas/EcucDefs_CddIccom/Cdd/CddIccomChannel/CddIccomChannelMfisSelection
- AP_MFIS0
-
-
- /Renesas/EcucDefs_CddIccom/Cdd/CddIccomChannel/CddIccomChannelTimeoutDuration
- 0.5
-
-
- /Renesas/EcucDefs_CddIccom/Cdd/CddIccomChannel/CddIccomChannelNotification
- CddIccom_Ch0NoticeCallback
-
-
-
- /Renesas/EcucDefs_CddIccom/Cdd/CddIccomChannel/CddIccomChannelTimeoutCounterRef
- /ActiveEcuC/Os/OsCounter
-
-
+
+
+ CddEmmBit0DBSC5DFIDomainDCLSErrDbs0
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain0/CddEmmBit0DBSC5DFIDomainDCLSErrDbs0
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain0/CddEmmBit0DBSC5DFIDomainDCLSErrDbs0/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain0/CddEmmBit0DBSC5DFIDomainDCLSErrDbs0/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit1DBSC5AXIDomainDCLSErrDbs0
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain0/CddEmmBit1DBSC5AXIDomainDCLSErrDbs0
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain0/CddEmmBit1DBSC5AXIDomainDCLSErrDbs0/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain0/CddEmmBit1DBSC5AXIDomainDCLSErrDbs0/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit2DBSC5DFIDomainDCLSErrDbs1
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain0/CddEmmBit2DBSC5DFIDomainDCLSErrDbs1
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain0/CddEmmBit2DBSC5DFIDomainDCLSErrDbs1/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain0/CddEmmBit2DBSC5DFIDomainDCLSErrDbs1/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit3DBSC5AXIDomainDCLSErrDbs1
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain0/CddEmmBit3DBSC5AXIDomainDCLSErrDbs1
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain0/CddEmmBit3DBSC5AXIDomainDCLSErrDbs1/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain0/CddEmmBit3DBSC5AXIDomainDCLSErrDbs1/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit12SYSCIsolationCellErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain0/CddEmmBit12SYSCIsolationCellErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain0/CddEmmBit12SYSCIsolationCellErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain0/CddEmmBit12SYSCIsolationCellErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit13FusesmRedundantComparitionErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain0/CddEmmBit13FusesmRedundantComparitionErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain0/CddEmmBit13FusesmRedundantComparitionErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain0/CddEmmBit13FusesmRedundantComparitionErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit14FSFailErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain0/CddEmmBit14FSFailErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain0/CddEmmBit14FSFailErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain0/CddEmmBit14FSFailErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit15FSTimeOutErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain0/CddEmmBit15FSTimeOutErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain0/CddEmmBit15FSTimeOutErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain0/CddEmmBit15FSTimeOutErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit16FSScanAXIbusErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain0/CddEmmBit16FSScanAXIbusErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain0/CddEmmBit16FSScanAXIbusErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain0/CddEmmBit16FSScanAXIbusErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit17ICUMXWdtOverFlowErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain0/CddEmmBit17ICUMXWdtOverFlowErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain0/CddEmmBit17ICUMXWdtOverFlowErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain0/CddEmmBit17ICUMXWdtOverFlowErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit18ICUMXBusAesOusideDmacEdcErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain0/CddEmmBit18ICUMXBusAesOusideDmacEdcErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain0/CddEmmBit18ICUMXBusAesOusideDmacEdcErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain0/CddEmmBit18ICUMXBusAesOusideDmacEdcErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit19ICUMXAesDmaLockstepErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain0/CddEmmBit19ICUMXAesDmaLockstepErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain0/CddEmmBit19ICUMXAesDmaLockstepErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain0/CddEmmBit19ICUMXAesDmaLockstepErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit20APSysGenericCounterOperationErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain0/CddEmmBit20APSysGenericCounterOperationErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain0/CddEmmBit20APSysGenericCounterOperationErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain0/CddEmmBit20APSysGenericCounterOperationErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit21APSysGenericCounterComparisonErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain0/CddEmmBit21APSysGenericCounterComparisonErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain0/CddEmmBit21APSysGenericCounterComparisonErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain0/CddEmmBit21APSysGenericCounterComparisonErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit22SYSCWriteAcessProtectionErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain0/CddEmmBit22SYSCWriteAcessProtectionErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain0/CddEmmBit22SYSCWriteAcessProtectionErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain0/CddEmmBit22SYSCWriteAcessProtectionErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit23SYSCHWRedundantErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain0/CddEmmBit23SYSCHWRedundantErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain0/CddEmmBit23SYSCHWRedundantErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain0/CddEmmBit23SYSCHWRedundantErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit24BootROMMultiBitErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain0/CddEmmBit24BootROMMultiBitErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain0/CddEmmBit24BootROMMultiBitErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain0/CddEmmBit24BootROMMultiBitErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit25BootROMSingleBitErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain0/CddEmmBit25BootROMSingleBitErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain0/CddEmmBit25BootROMSingleBitErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain0/CddEmmBit25BootROMSingleBitErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit26BootROMMultiBitErr2
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain0/CddEmmBit26BootROMMultiBitErr2
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain0/CddEmmBit26BootROMMultiBitErr2/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain0/CddEmmBit26BootROMMultiBitErr2/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit27BootROMSingleBitErr2
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain0/CddEmmBit27BootROMSingleBitErr2
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain0/CddEmmBit27BootROMSingleBitErr2/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain0/CddEmmBit27BootROMSingleBitErr2/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit28BootROMAccessICUMXErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain0/CddEmmBit28BootROMAccessICUMXErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain0/CddEmmBit28BootROMAccessICUMXErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain0/CddEmmBit28BootROMAccessICUMXErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit29CPGIllegalAccessErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain0/CddEmmBit29CPGIllegalAccessErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain0/CddEmmBit29CPGIllegalAccessErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain0/CddEmmBit29CPGIllegalAccessErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit30CPGFreqErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain0/CddEmmBit30CPGFreqErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain0/CddEmmBit30CPGFreqErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain0/CddEmmBit30CPGFreqErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit31WriteProtectFailerReset
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain0/CddEmmBit31WriteProtectFailerReset
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain0/CddEmmBit31WriteProtectFailerReset/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain0/CddEmmBit31WriteProtectFailerReset/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
-
- CddIccomDemEventParameterRefs
- /Renesas/EcucDefs_CddIccom/Cdd/CddIccomDemEventParameterRefs
-
-
- /Renesas/EcucDefs_CddIccom/Cdd/CddIccomDemEventParameterRefs/CDDICCOM_E_FATAL
- /ActiveEcuC/Dem/DemConfigSet/CDDICCOM_E_FATAL
-
-
- /Renesas/EcucDefs_CddIccom/Cdd/CddIccomDemEventParameterRefs/CDDICCOM_E_INIT_NEGOTIATION
- /ActiveEcuC/Dem/DemConfigSet/CDDICCOM_E_INIT_NEGOTIATION
-
-
- /Renesas/EcucDefs_CddIccom/Cdd/CddIccomDemEventParameterRefs/CDDICCOM_E_TIMEOUT
- /ActiveEcuC/Dem/DemConfigSet/CDDICCOM_E_TIMEOUT
-
-
- /Renesas/EcucDefs_CddIccom/Cdd/CddIccomDemEventParameterRefs/CDDICCOM_E_INVALID_ACK
- /ActiveEcuC/Dem/DemConfigSet/CDDICCOM_E_INVALID_ACK
-
-
- /Renesas/EcucDefs_CddIccom/Cdd/CddIccomDemEventParameterRefs/CDDICCOM_E_WRITE_VERIFY_FAILURE
- /ActiveEcuC/Dem/DemConfigSet/CDDICCOM_E_WRITE_VERIFY_FAILURE
-
-
- /Renesas/EcucDefs_CddIccom/Cdd/CddIccomDemEventParameterRefs/CDDICCOM_E_INTERRUPT_CONTROLLER_FAILURE
- /ActiveEcuC/Dem/DemConfigSet/CDDICCOM_E_INTERRUPT_CONTROLLER_FAILURE
-
-
-
-
- CddIccomChannel_001
- /Renesas/EcucDefs_CddIccom/Cdd/CddIccomChannel
+
+ CddEmmDomain1
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain1
- /Renesas/EcucDefs_CddIccom/Cdd/CddIccomChannel/CddIccomChannelId
- 1
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain1/CddEmmAddressToSaveErrorStatus
+ 1342177284
-
- /Renesas/EcucDefs_CddIccom/Cdd/CddIccomChannel/CddIccomChannelCtaAddress
- 1207734272
-
-
- /Renesas/EcucDefs_CddIccom/Cdd/CddIccomChannel/CddIccomChannelCtaPartitionSize
- 2048
-
-
- /Renesas/EcucDefs_CddIccom/Cdd/CddIccomChannel/CddIccomChannelMfisSelection
- AP_MFIS1
-
-
- /Renesas/EcucDefs_CddIccom/Cdd/CddIccomChannel/CddIccomChannelTimeoutDuration
- 0.5
-
-
- /Renesas/EcucDefs_CddIccom/Cdd/CddIccomChannel/CddIccomChannelNotification
- CddIccom_Ch1NoticeCallback
-
-
-
- /Renesas/EcucDefs_CddIccom/Cdd/CddIccomChannel/CddIccomChannelTimeoutCounterRef
- /ActiveEcuC/Os/OsCounter
-
-
+
+
+ CddEmmBit14APSysCciAceProtocolErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain1/CddEmmBit14APSysCciAceProtocolErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain1/CddEmmBit14APSysCciAceProtocolErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain1/CddEmmBit14APSysCciAceProtocolErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit15APSysCciADB400MIChkGenErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain1/CddEmmBit15APSysCciADB400MIChkGenErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain1/CddEmmBit15APSysCciADB400MIChkGenErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain1/CddEmmBit15APSysCciADB400MIChkGenErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit19WWDTch6CountErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain1/CddEmmBit19WWDTch6CountErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain1/CddEmmBit19WWDTch6CountErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain1/CddEmmBit19WWDTch6CountErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit20WWDTch5CountErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain1/CddEmmBit20WWDTch5CountErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain1/CddEmmBit20WWDTch5CountErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain1/CddEmmBit20WWDTch5CountErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit21WWDTch4CountErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain1/CddEmmBit21WWDTch4CountErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain1/CddEmmBit21WWDTch4CountErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain1/CddEmmBit21WWDTch4CountErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit22WWDTch3CountErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain1/CddEmmBit22WWDTch3CountErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain1/CddEmmBit22WWDTch3CountErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain1/CddEmmBit22WWDTch3CountErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit23WWDTch2CountErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain1/CddEmmBit23WWDTch2CountErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain1/CddEmmBit23WWDTch2CountErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain1/CddEmmBit23WWDTch2CountErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit24WWDTch1CountErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain1/CddEmmBit24WWDTch1CountErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain1/CddEmmBit24WWDTch1CountErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain1/CddEmmBit24WWDTch1CountErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit25WWDTch0CountErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain1/CddEmmBit25WWDTch0CountErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain1/CddEmmBit25WWDTch0CountErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain1/CddEmmBit25WWDTch0CountErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit26APSysCciAxiProtocolErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain1/CddEmmBit26APSysCciAxiProtocolErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain1/CddEmmBit26APSysCciAxiProtocolErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain1/CddEmmBit26APSysCciAxiProtocolErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit27APSysCciSFRAMEccSedErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain1/CddEmmBit27APSysCciSFRAMEccSedErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain1/CddEmmBit27APSysCciSFRAMEccSedErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain1/CddEmmBit27APSysCciSFRAMEccSedErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit28APSysCciSFRAMEccDedErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain1/CddEmmBit28APSysCciSFRAMEccDedErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain1/CddEmmBit28APSysCciSFRAMEccDedErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain1/CddEmmBit28APSysCciSFRAMEccDedErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit29APSysCciDCLSCompare0Err
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain1/CddEmmBit29APSysCciDCLSCompare0Err
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain1/CddEmmBit29APSysCciDCLSCompare0Err/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain1/CddEmmBit29APSysCciDCLSCompare0Err/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit30APSysCciIrqFunctionErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain1/CddEmmBit30APSysCciIrqFunctionErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain1/CddEmmBit30APSysCciIrqFunctionErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain1/CddEmmBit30APSysCciIrqFunctionErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit31APSysCciDCLSCompare1Err
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain1/CddEmmBit31APSysCciDCLSCompare1Err
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain1/CddEmmBit31APSysCciDCLSCompare1Err/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain1/CddEmmBit31APSysCciDCLSCompare1Err/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
-
- CddIccomChannel_002
- /Renesas/EcucDefs_CddIccom/Cdd/CddIccomChannel
+
+ CddEmmDomain2
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain2
- /Renesas/EcucDefs_CddIccom/Cdd/CddIccomChannel/CddIccomChannelId
- 2
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain2/CddEmmAddressToSaveErrorStatus
+ 1342177288
-
- /Renesas/EcucDefs_CddIccom/Cdd/CddIccomChannel/CddIccomChannelCtaAddress
- 1207742464
-
-
- /Renesas/EcucDefs_CddIccom/Cdd/CddIccomChannel/CddIccomChannelCtaPartitionSize
- 2048
-
-
- /Renesas/EcucDefs_CddIccom/Cdd/CddIccomChannel/CddIccomChannelMfisSelection
- AP_MFIS2
-
-
- /Renesas/EcucDefs_CddIccom/Cdd/CddIccomChannel/CddIccomChannelTimeoutDuration
- 0.5
-
-
- /Renesas/EcucDefs_CddIccom/Cdd/CddIccomChannel/CddIccomChannelNotification
- CddIccom_Ch2NoticeCallback
-
-
-
- /Renesas/EcucDefs_CddIccom/Cdd/CddIccomChannel/CddIccomChannelTimeoutCounterRef
- /ActiveEcuC/Os/OsCounter
-
-
+
+
+ CddEmmBit0INTCtpWDTmonitorIMNTRSR0Err
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain2/CddEmmBit0INTCtpWDTmonitorIMNTRSR0Err
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain2/CddEmmBit0INTCtpWDTmonitorIMNTRSR0Err/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain2/CddEmmBit0INTCtpWDTmonitorIMNTRSR0Err/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit1INTCtpWDTmonitorIMNTRSR1Err
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain2/CddEmmBit1INTCtpWDTmonitorIMNTRSR1Err
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain2/CddEmmBit1INTCtpWDTmonitorIMNTRSR1Err/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain2/CddEmmBit1INTCtpWDTmonitorIMNTRSR1Err/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit2INTCtpWDTmonitorIMNTRSR2Err
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain2/CddEmmBit2INTCtpWDTmonitorIMNTRSR2Err
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain2/CddEmmBit2INTCtpWDTmonitorIMNTRSR2Err/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain2/CddEmmBit2INTCtpWDTmonitorIMNTRSR2Err/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit3INTCtpWDTmonitorIMNTRSR3Err
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain2/CddEmmBit3INTCtpWDTmonitorIMNTRSR3Err
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain2/CddEmmBit3INTCtpWDTmonitorIMNTRSR3Err/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain2/CddEmmBit3INTCtpWDTmonitorIMNTRSR3Err/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit4INTCtpWDTmonitorIMNTRSR4Err
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain2/CddEmmBit4INTCtpWDTmonitorIMNTRSR4Err
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain2/CddEmmBit4INTCtpWDTmonitorIMNTRSR4Err/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain2/CddEmmBit4INTCtpWDTmonitorIMNTRSR4Err/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit5INTCtpWDTmonitorIMNTRSR5Err
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain2/CddEmmBit5INTCtpWDTmonitorIMNTRSR5Err
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain2/CddEmmBit5INTCtpWDTmonitorIMNTRSR5Err/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain2/CddEmmBit5INTCtpWDTmonitorIMNTRSR5Err/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit6INTCtpWDTmonitorIMNTRSR6Err
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain2/CddEmmBit6INTCtpWDTmonitorIMNTRSR6Err
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain2/CddEmmBit6INTCtpWDTmonitorIMNTRSR6Err/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain2/CddEmmBit6INTCtpWDTmonitorIMNTRSR6Err/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit7INTCtpWDTmonitorIMNTRSR7Err
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain2/CddEmmBit7INTCtpWDTmonitorIMNTRSR7Err
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain2/CddEmmBit7INTCtpWDTmonitorIMNTRSR7Err/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain2/CddEmmBit7INTCtpWDTmonitorIMNTRSR7Err/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit8INTCtpWDTmonitorIMNTRSR8Err
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain2/CddEmmBit8INTCtpWDTmonitorIMNTRSR8Err
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain2/CddEmmBit8INTCtpWDTmonitorIMNTRSR8Err/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain2/CddEmmBit8INTCtpWDTmonitorIMNTRSR8Err/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit9INTCtpWDTmonitorIMNTRSR9Err
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain2/CddEmmBit9INTCtpWDTmonitorIMNTRSR9Err
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain2/CddEmmBit9INTCtpWDTmonitorIMNTRSR9Err/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain2/CddEmmBit9INTCtpWDTmonitorIMNTRSR9Err/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit10INTCtpWDTmonitorIMNTRSR10Err
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain2/CddEmmBit10INTCtpWDTmonitorIMNTRSR10Err
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain2/CddEmmBit10INTCtpWDTmonitorIMNTRSR10Err/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain2/CddEmmBit10INTCtpWDTmonitorIMNTRSR10Err/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit11INTCtpWDTmonitorIMNTRSR11Err
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain2/CddEmmBit11INTCtpWDTmonitorIMNTRSR11Err
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain2/CddEmmBit11INTCtpWDTmonitorIMNTRSR11Err/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain2/CddEmmBit11INTCtpWDTmonitorIMNTRSR11Err/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit12INTCtpWDTmonitorIMNTRSR12Err
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain2/CddEmmBit12INTCtpWDTmonitorIMNTRSR12Err
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain2/CddEmmBit12INTCtpWDTmonitorIMNTRSR12Err/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain2/CddEmmBit12INTCtpWDTmonitorIMNTRSR12Err/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit13INTCtpWDTmonitorIMNTRSR13Err
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain2/CddEmmBit13INTCtpWDTmonitorIMNTRSR13Err
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain2/CddEmmBit13INTCtpWDTmonitorIMNTRSR13Err/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain2/CddEmmBit13INTCtpWDTmonitorIMNTRSR13Err/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit14INTCtpWDTmonitorIMNTRSR14Err
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain2/CddEmmBit14INTCtpWDTmonitorIMNTRSR14Err
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain2/CddEmmBit14INTCtpWDTmonitorIMNTRSR14Err/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain2/CddEmmBit14INTCtpWDTmonitorIMNTRSR14Err/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit15INTCtpWDTmonitorIMNTRSR15Err
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain2/CddEmmBit15INTCtpWDTmonitorIMNTRSR15Err
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain2/CddEmmBit15INTCtpWDTmonitorIMNTRSR15Err/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain2/CddEmmBit15INTCtpWDTmonitorIMNTRSR15Err/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit16INTCtpWDTmonitorIMNTRSR16Err
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain2/CddEmmBit16INTCtpWDTmonitorIMNTRSR16Err
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain2/CddEmmBit16INTCtpWDTmonitorIMNTRSR16Err/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain2/CddEmmBit16INTCtpWDTmonitorIMNTRSR16Err/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit17INTCtpWDTmonitorIMNTRSR17Err
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain2/CddEmmBit17INTCtpWDTmonitorIMNTRSR17Err
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain2/CddEmmBit17INTCtpWDTmonitorIMNTRSR17Err/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain2/CddEmmBit17INTCtpWDTmonitorIMNTRSR17Err/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit18INTCtpWDTmonitorIMNTRSR18Err
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain2/CddEmmBit18INTCtpWDTmonitorIMNTRSR18Err
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain2/CddEmmBit18INTCtpWDTmonitorIMNTRSR18Err/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain2/CddEmmBit18INTCtpWDTmonitorIMNTRSR18Err/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit19INTCtpWDTmonitorIMNTRSR19Err
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain2/CddEmmBit19INTCtpWDTmonitorIMNTRSR19Err
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain2/CddEmmBit19INTCtpWDTmonitorIMNTRSR19Err/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain2/CddEmmBit19INTCtpWDTmonitorIMNTRSR19Err/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit20INTCtpWDTmonitorIMNTRSR20Err
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain2/CddEmmBit20INTCtpWDTmonitorIMNTRSR20Err
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain2/CddEmmBit20INTCtpWDTmonitorIMNTRSR20Err/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain2/CddEmmBit20INTCtpWDTmonitorIMNTRSR20Err/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit21INTCtpWDTmonitorIMNTRSR21Err
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain2/CddEmmBit21INTCtpWDTmonitorIMNTRSR21Err
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain2/CddEmmBit21INTCtpWDTmonitorIMNTRSR21Err/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain2/CddEmmBit21INTCtpWDTmonitorIMNTRSR21Err/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit22INTCtpWDTmonitorIMNTRSR22Err
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain2/CddEmmBit22INTCtpWDTmonitorIMNTRSR22Err
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain2/CddEmmBit22INTCtpWDTmonitorIMNTRSR22Err/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain2/CddEmmBit22INTCtpWDTmonitorIMNTRSR22Err/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit23INTCtpWDTmonitorIMNTRSR23Err
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain2/CddEmmBit23INTCtpWDTmonitorIMNTRSR23Err
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain2/CddEmmBit23INTCtpWDTmonitorIMNTRSR23Err/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain2/CddEmmBit23INTCtpWDTmonitorIMNTRSR23Err/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit24INTCtpWDTmonitorIMNTRSR24Err
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain2/CddEmmBit24INTCtpWDTmonitorIMNTRSR24Err
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain2/CddEmmBit24INTCtpWDTmonitorIMNTRSR24Err/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain2/CddEmmBit24INTCtpWDTmonitorIMNTRSR24Err/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit25INTCtpWDTmonitorIMNTRSR25Err
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain2/CddEmmBit25INTCtpWDTmonitorIMNTRSR25Err
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain2/CddEmmBit25INTCtpWDTmonitorIMNTRSR25Err/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain2/CddEmmBit25INTCtpWDTmonitorIMNTRSR25Err/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit26INTCtpWDTmonitorIMNTRSR26Err
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain2/CddEmmBit26INTCtpWDTmonitorIMNTRSR26Err
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain2/CddEmmBit26INTCtpWDTmonitorIMNTRSR26Err/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain2/CddEmmBit26INTCtpWDTmonitorIMNTRSR26Err/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit27INTCtpWDTmonitorIMNTRSR27Err
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain2/CddEmmBit27INTCtpWDTmonitorIMNTRSR27Err
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain2/CddEmmBit27INTCtpWDTmonitorIMNTRSR27Err/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain2/CddEmmBit27INTCtpWDTmonitorIMNTRSR27Err/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit28INTCtpWDTmonitorIMNTRSR28Err
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain2/CddEmmBit28INTCtpWDTmonitorIMNTRSR28Err
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain2/CddEmmBit28INTCtpWDTmonitorIMNTRSR28Err/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain2/CddEmmBit28INTCtpWDTmonitorIMNTRSR28Err/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit29INTCtpWDTmonitorIMNTRSR29Err
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain2/CddEmmBit29INTCtpWDTmonitorIMNTRSR29Err
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain2/CddEmmBit29INTCtpWDTmonitorIMNTRSR29Err/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain2/CddEmmBit29INTCtpWDTmonitorIMNTRSR29Err/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit30INTCtpWDTmonitorIMNTRSR30Err
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain2/CddEmmBit30INTCtpWDTmonitorIMNTRSR30Err
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain2/CddEmmBit30INTCtpWDTmonitorIMNTRSR30Err/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain2/CddEmmBit30INTCtpWDTmonitorIMNTRSR30Err/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit31INTCtpWDTmonitorIMNTRSR31Err
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain2/CddEmmBit31INTCtpWDTmonitorIMNTRSR31Err
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain2/CddEmmBit31INTCtpWDTmonitorIMNTRSR31Err/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain2/CddEmmBit31INTCtpWDTmonitorIMNTRSR31Err/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
-
- CddIccomChannel_003
- /Renesas/EcucDefs_CddIccom/Cdd/CddIccomChannel
+
+ CddEmmDomain3
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain3
- /Renesas/EcucDefs_CddIccom/Cdd/CddIccomChannel/CddIccomChannelId
- 3
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain3/CddEmmAddressToSaveErrorStatus
+ 1342177292
-
- /Renesas/EcucDefs_CddIccom/Cdd/CddIccomChannel/CddIccomChannelCtaAddress
- 1207750656
-
-
- /Renesas/EcucDefs_CddIccom/Cdd/CddIccomChannel/CddIccomChannelCtaPartitionSize
- 2048
-
-
- /Renesas/EcucDefs_CddIccom/Cdd/CddIccomChannel/CddIccomChannelMfisSelection
- AP_MFIS3
-
-
- /Renesas/EcucDefs_CddIccom/Cdd/CddIccomChannel/CddIccomChannelTimeoutDuration
- 0.5
-
-
- /Renesas/EcucDefs_CddIccom/Cdd/CddIccomChannel/CddIccomChannelNotification
- CddIccom_Ch3NoticeCallback
-
+
+
+ CddEmmBit0INTCtpWDTmonitorIMNTRSR32Err
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain3/CddEmmBit0INTCtpWDTmonitorIMNTRSR32Err
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain3/CddEmmBit0INTCtpWDTmonitorIMNTRSR32Err/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain3/CddEmmBit0INTCtpWDTmonitorIMNTRSR32Err/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit1INTCtpWDTmonitorIMNTRSR33Err
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain3/CddEmmBit1INTCtpWDTmonitorIMNTRSR33Err
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain3/CddEmmBit1INTCtpWDTmonitorIMNTRSR33Err/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain3/CddEmmBit1INTCtpWDTmonitorIMNTRSR33Err/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit2INTCtpWDTmonitorIMNTRSR34Err
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain3/CddEmmBit2INTCtpWDTmonitorIMNTRSR34Err
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain3/CddEmmBit2INTCtpWDTmonitorIMNTRSR34Err/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain3/CddEmmBit2INTCtpWDTmonitorIMNTRSR34Err/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit3INTCtpWDTmonitorIMNTRSR35Err
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain3/CddEmmBit3INTCtpWDTmonitorIMNTRSR35Err
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain3/CddEmmBit3INTCtpWDTmonitorIMNTRSR35Err/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain3/CddEmmBit3INTCtpWDTmonitorIMNTRSR35Err/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit4INTCtpWDTmonitorIMNTRSR36Err
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain3/CddEmmBit4INTCtpWDTmonitorIMNTRSR36Err
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain3/CddEmmBit4INTCtpWDTmonitorIMNTRSR36Err/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain3/CddEmmBit4INTCtpWDTmonitorIMNTRSR36Err/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit5INTCtpWDTmonitorIMNTRSR37Err
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain3/CddEmmBit5INTCtpWDTmonitorIMNTRSR37Err
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain3/CddEmmBit5INTCtpWDTmonitorIMNTRSR37Err/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain3/CddEmmBit5INTCtpWDTmonitorIMNTRSR37Err/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit6INTCtpWDTmonitorIMNTRSR38Err
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain3/CddEmmBit6INTCtpWDTmonitorIMNTRSR38Err
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain3/CddEmmBit6INTCtpWDTmonitorIMNTRSR38Err/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain3/CddEmmBit6INTCtpWDTmonitorIMNTRSR38Err/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit7INTCtpWDTmonitorIMNTRSR39Err
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain3/CddEmmBit7INTCtpWDTmonitorIMNTRSR39Err
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain3/CddEmmBit7INTCtpWDTmonitorIMNTRSR39Err/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain3/CddEmmBit7INTCtpWDTmonitorIMNTRSR39Err/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit8INTCtpWDTmonitorIMNTRSR40Err
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain3/CddEmmBit8INTCtpWDTmonitorIMNTRSR40Err
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain3/CddEmmBit8INTCtpWDTmonitorIMNTRSR40Err/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain3/CddEmmBit8INTCtpWDTmonitorIMNTRSR40Err/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit9INTCtpWDTmonitorIMNTRSR41Err
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain3/CddEmmBit9INTCtpWDTmonitorIMNTRSR41Err
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain3/CddEmmBit9INTCtpWDTmonitorIMNTRSR41Err/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain3/CddEmmBit9INTCtpWDTmonitorIMNTRSR41Err/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit10INTCtpWDTmonitorIMNTRSR42Err
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain3/CddEmmBit10INTCtpWDTmonitorIMNTRSR42Err
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain3/CddEmmBit10INTCtpWDTmonitorIMNTRSR42Err/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain3/CddEmmBit10INTCtpWDTmonitorIMNTRSR42Err/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit11INTCtpWDTmonitorIMNTRSR43Err
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain3/CddEmmBit11INTCtpWDTmonitorIMNTRSR43Err
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain3/CddEmmBit11INTCtpWDTmonitorIMNTRSR43Err/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain3/CddEmmBit11INTCtpWDTmonitorIMNTRSR43Err/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit12INTCtpWDTmonitorIMNTRSR44Err
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain3/CddEmmBit12INTCtpWDTmonitorIMNTRSR44Err
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain3/CddEmmBit12INTCtpWDTmonitorIMNTRSR44Err/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain3/CddEmmBit12INTCtpWDTmonitorIMNTRSR44Err/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit13INTCtpWDTmonitorIMNTRSR45Err
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain3/CddEmmBit13INTCtpWDTmonitorIMNTRSR45Err
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain3/CddEmmBit13INTCtpWDTmonitorIMNTRSR45Err/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain3/CddEmmBit13INTCtpWDTmonitorIMNTRSR45Err/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit14INTCtpWDTmonitorIMNTRSR46Err
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain3/CddEmmBit14INTCtpWDTmonitorIMNTRSR46Err
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain3/CddEmmBit14INTCtpWDTmonitorIMNTRSR46Err/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain3/CddEmmBit14INTCtpWDTmonitorIMNTRSR46Err/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit15INTCtpWDTmonitorIMNTRSR47Err
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain3/CddEmmBit15INTCtpWDTmonitorIMNTRSR47Err
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain3/CddEmmBit15INTCtpWDTmonitorIMNTRSR47Err/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain3/CddEmmBit15INTCtpWDTmonitorIMNTRSR47Err/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit16INTCtpWDTmonitorIMNTRSR48Err
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain3/CddEmmBit16INTCtpWDTmonitorIMNTRSR48Err
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain3/CddEmmBit16INTCtpWDTmonitorIMNTRSR48Err/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain3/CddEmmBit16INTCtpWDTmonitorIMNTRSR48Err/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit17INTCtpWDTmonitorIMNTRSR49Err
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain3/CddEmmBit17INTCtpWDTmonitorIMNTRSR49Err
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain3/CddEmmBit17INTCtpWDTmonitorIMNTRSR49Err/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain3/CddEmmBit17INTCtpWDTmonitorIMNTRSR49Err/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit18INTCtpWDTmonitorIMNTRSR50Err
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain3/CddEmmBit18INTCtpWDTmonitorIMNTRSR50Err
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain3/CddEmmBit18INTCtpWDTmonitorIMNTRSR50Err/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain3/CddEmmBit18INTCtpWDTmonitorIMNTRSR50Err/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit19INTCtpWDTmonitorIMNTRSR51Err
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain3/CddEmmBit19INTCtpWDTmonitorIMNTRSR51Err
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain3/CddEmmBit19INTCtpWDTmonitorIMNTRSR51Err/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain3/CddEmmBit19INTCtpWDTmonitorIMNTRSR51Err/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit20INTCtpWDTmonitorIMNTRSR52Err
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain3/CddEmmBit20INTCtpWDTmonitorIMNTRSR52Err
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain3/CddEmmBit20INTCtpWDTmonitorIMNTRSR52Err/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain3/CddEmmBit20INTCtpWDTmonitorIMNTRSR52Err/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit21INTCtpWDTmonitorIMNTRSR53Err
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain3/CddEmmBit21INTCtpWDTmonitorIMNTRSR53Err
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain3/CddEmmBit21INTCtpWDTmonitorIMNTRSR53Err/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain3/CddEmmBit21INTCtpWDTmonitorIMNTRSR53Err/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit22INTCtpWDTmonitorIMNTRSR54Err
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain3/CddEmmBit22INTCtpWDTmonitorIMNTRSR54Err
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain3/CddEmmBit22INTCtpWDTmonitorIMNTRSR54Err/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain3/CddEmmBit22INTCtpWDTmonitorIMNTRSR54Err/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit23INTCtpWDTmonitorIMNTRSR55Err
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain3/CddEmmBit23INTCtpWDTmonitorIMNTRSR55Err
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain3/CddEmmBit23INTCtpWDTmonitorIMNTRSR55Err/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain3/CddEmmBit23INTCtpWDTmonitorIMNTRSR55Err/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit24INTCtpWDTmonitorIMNTRSR56Err
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain3/CddEmmBit24INTCtpWDTmonitorIMNTRSR56Err
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain3/CddEmmBit24INTCtpWDTmonitorIMNTRSR56Err/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain3/CddEmmBit24INTCtpWDTmonitorIMNTRSR56Err/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit25INTCtpWDTmonitorIMNTRSR57Err
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain3/CddEmmBit25INTCtpWDTmonitorIMNTRSR57Err
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain3/CddEmmBit25INTCtpWDTmonitorIMNTRSR57Err/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain3/CddEmmBit25INTCtpWDTmonitorIMNTRSR57Err/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit26INTCtpWDTmonitorIMNTRSR58Err
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain3/CddEmmBit26INTCtpWDTmonitorIMNTRSR58Err
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain3/CddEmmBit26INTCtpWDTmonitorIMNTRSR58Err/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain3/CddEmmBit26INTCtpWDTmonitorIMNTRSR58Err/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit27INTCtpWDTmonitorIMNTRSR59Err
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain3/CddEmmBit27INTCtpWDTmonitorIMNTRSR59Err
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain3/CddEmmBit27INTCtpWDTmonitorIMNTRSR59Err/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain3/CddEmmBit27INTCtpWDTmonitorIMNTRSR59Err/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit28INTCtpWDTmonitorIMNTRSR60Err
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain3/CddEmmBit28INTCtpWDTmonitorIMNTRSR60Err
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain3/CddEmmBit28INTCtpWDTmonitorIMNTRSR60Err/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain3/CddEmmBit28INTCtpWDTmonitorIMNTRSR60Err/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit29INTCtpWDTmonitorIMNTRSR61Err
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain3/CddEmmBit29INTCtpWDTmonitorIMNTRSR61Err
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain3/CddEmmBit29INTCtpWDTmonitorIMNTRSR61Err/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain3/CddEmmBit29INTCtpWDTmonitorIMNTRSR61Err/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit30INTCtpWDTmonitorIMNTRSR62Err
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain3/CddEmmBit30INTCtpWDTmonitorIMNTRSR62Err
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain3/CddEmmBit30INTCtpWDTmonitorIMNTRSR62Err/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain3/CddEmmBit30INTCtpWDTmonitorIMNTRSR62Err/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit31INTCtpWDTmonitorIMNTRSR63Err
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain3/CddEmmBit31INTCtpWDTmonitorIMNTRSR63Err
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain3/CddEmmBit31INTCtpWDTmonitorIMNTRSR63Err/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain3/CddEmmBit31INTCtpWDTmonitorIMNTRSR63Err/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+
+
+ CddEmmDomain4
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain4
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain4/CddEmmAddressToSaveErrorStatus
+ 1342177296
+
+
+
+
+ CddEmmBit0INTCtpWDTmonitorIMNTRSR64Err
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain4/CddEmmBit0INTCtpWDTmonitorIMNTRSR64Err
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain4/CddEmmBit0INTCtpWDTmonitorIMNTRSR64Err/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain4/CddEmmBit0INTCtpWDTmonitorIMNTRSR64Err/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit1INTCtpWDTmonitorIMNTRSR65Err
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain4/CddEmmBit1INTCtpWDTmonitorIMNTRSR65Err
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain4/CddEmmBit1INTCtpWDTmonitorIMNTRSR65Err/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain4/CddEmmBit1INTCtpWDTmonitorIMNTRSR65Err/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit2INTCtpWDTmonitorIMNTRSR66Err
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain4/CddEmmBit2INTCtpWDTmonitorIMNTRSR66Err
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain4/CddEmmBit2INTCtpWDTmonitorIMNTRSR66Err/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain4/CddEmmBit2INTCtpWDTmonitorIMNTRSR66Err/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit3INTCtpWDTmonitorIMNTRSR67Err
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain4/CddEmmBit3INTCtpWDTmonitorIMNTRSR67Err
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain4/CddEmmBit3INTCtpWDTmonitorIMNTRSR67Err/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain4/CddEmmBit3INTCtpWDTmonitorIMNTRSR67Err/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit4INTCtpWDTmonitorIMNTRSR68Err
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain4/CddEmmBit4INTCtpWDTmonitorIMNTRSR68Err
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain4/CddEmmBit4INTCtpWDTmonitorIMNTRSR68Err/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain4/CddEmmBit4INTCtpWDTmonitorIMNTRSR68Err/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit5INTCtpWDTmonitorIMNTRSR69Err
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain4/CddEmmBit5INTCtpWDTmonitorIMNTRSR69Err
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain4/CddEmmBit5INTCtpWDTmonitorIMNTRSR69Err/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain4/CddEmmBit5INTCtpWDTmonitorIMNTRSR69Err/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit6INTCtpWDTmonitorIMNTRSR70Err
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain4/CddEmmBit6INTCtpWDTmonitorIMNTRSR70Err
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain4/CddEmmBit6INTCtpWDTmonitorIMNTRSR70Err/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain4/CddEmmBit6INTCtpWDTmonitorIMNTRSR70Err/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit7INTCtpWDTmonitorIMNTRSR71Err
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain4/CddEmmBit7INTCtpWDTmonitorIMNTRSR71Err
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain4/CddEmmBit7INTCtpWDTmonitorIMNTRSR71Err/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain4/CddEmmBit7INTCtpWDTmonitorIMNTRSR71Err/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit8INTCtpWDTmonitorIMNTRSR72Err
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain4/CddEmmBit8INTCtpWDTmonitorIMNTRSR72Err
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain4/CddEmmBit8INTCtpWDTmonitorIMNTRSR72Err/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain4/CddEmmBit8INTCtpWDTmonitorIMNTRSR72Err/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit9INTCtpWDTmonitorIMNTRSR73Err
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain4/CddEmmBit9INTCtpWDTmonitorIMNTRSR73Err
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain4/CddEmmBit9INTCtpWDTmonitorIMNTRSR73Err/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain4/CddEmmBit9INTCtpWDTmonitorIMNTRSR73Err/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit10INTCtpWDTmonitorIMNTRSR74Err
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain4/CddEmmBit10INTCtpWDTmonitorIMNTRSR74Err
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain4/CddEmmBit10INTCtpWDTmonitorIMNTRSR74Err/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain4/CddEmmBit10INTCtpWDTmonitorIMNTRSR74Err/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit11INTCtpWDTmonitorIMNTRSR75Err
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain4/CddEmmBit11INTCtpWDTmonitorIMNTRSR75Err
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain4/CddEmmBit11INTCtpWDTmonitorIMNTRSR75Err/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain4/CddEmmBit11INTCtpWDTmonitorIMNTRSR75Err/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit12INTCtpWDTmonitorIMNTRSR76Err
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain4/CddEmmBit12INTCtpWDTmonitorIMNTRSR76Err
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain4/CddEmmBit12INTCtpWDTmonitorIMNTRSR76Err/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain4/CddEmmBit12INTCtpWDTmonitorIMNTRSR76Err/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit13INTCtpWDTmonitorIMNTRSR77Err
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain4/CddEmmBit13INTCtpWDTmonitorIMNTRSR77Err
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain4/CddEmmBit13INTCtpWDTmonitorIMNTRSR77Err/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain4/CddEmmBit13INTCtpWDTmonitorIMNTRSR77Err/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit14INTCtpWDTmonitorIMNTRSR78Err
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain4/CddEmmBit14INTCtpWDTmonitorIMNTRSR78Err
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain4/CddEmmBit14INTCtpWDTmonitorIMNTRSR78Err/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain4/CddEmmBit14INTCtpWDTmonitorIMNTRSR78Err/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit15INTCtpWDTmonitorIMNTRSR79Err
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain4/CddEmmBit15INTCtpWDTmonitorIMNTRSR79Err
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain4/CddEmmBit15INTCtpWDTmonitorIMNTRSR79Err/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain4/CddEmmBit15INTCtpWDTmonitorIMNTRSR79Err/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit16INTCtpWDTmonitorIMNTRSR80Err
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain4/CddEmmBit16INTCtpWDTmonitorIMNTRSR80Err
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain4/CddEmmBit16INTCtpWDTmonitorIMNTRSR80Err/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain4/CddEmmBit16INTCtpWDTmonitorIMNTRSR80Err/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit17INTCtpWDTmonitorIMNTRSR81Err
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain4/CddEmmBit17INTCtpWDTmonitorIMNTRSR81Err
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain4/CddEmmBit17INTCtpWDTmonitorIMNTRSR81Err/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain4/CddEmmBit17INTCtpWDTmonitorIMNTRSR81Err/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit18INTCtpWDTmonitorIMNTRSR82Err
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain4/CddEmmBit18INTCtpWDTmonitorIMNTRSR82Err
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain4/CddEmmBit18INTCtpWDTmonitorIMNTRSR82Err/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain4/CddEmmBit18INTCtpWDTmonitorIMNTRSR82Err/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit19INTCtpWDTmonitorIMNTRSR83Err
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain4/CddEmmBit19INTCtpWDTmonitorIMNTRSR83Err
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain4/CddEmmBit19INTCtpWDTmonitorIMNTRSR83Err/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain4/CddEmmBit19INTCtpWDTmonitorIMNTRSR83Err/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit20INTCtpWDTmonitorIMNTRSR84Err
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain4/CddEmmBit20INTCtpWDTmonitorIMNTRSR84Err
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain4/CddEmmBit20INTCtpWDTmonitorIMNTRSR84Err/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain4/CddEmmBit20INTCtpWDTmonitorIMNTRSR84Err/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit21INTCtpWDTmonitorIMNTRSR85Err
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain4/CddEmmBit21INTCtpWDTmonitorIMNTRSR85Err
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain4/CddEmmBit21INTCtpWDTmonitorIMNTRSR85Err/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain4/CddEmmBit21INTCtpWDTmonitorIMNTRSR85Err/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit22INTCtpWDTmonitorIMNTRSR86Err
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain4/CddEmmBit22INTCtpWDTmonitorIMNTRSR86Err
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain4/CddEmmBit22INTCtpWDTmonitorIMNTRSR86Err/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain4/CddEmmBit22INTCtpWDTmonitorIMNTRSR86Err/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit23INTCtpWDTmonitorIMNTRSR87Err
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain4/CddEmmBit23INTCtpWDTmonitorIMNTRSR87Err
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain4/CddEmmBit23INTCtpWDTmonitorIMNTRSR87Err/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain4/CddEmmBit23INTCtpWDTmonitorIMNTRSR87Err/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit24INTCtpWDTmonitorIMNTRSR88Err
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain4/CddEmmBit24INTCtpWDTmonitorIMNTRSR88Err
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain4/CddEmmBit24INTCtpWDTmonitorIMNTRSR88Err/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain4/CddEmmBit24INTCtpWDTmonitorIMNTRSR88Err/CddEmmErrorSignalTarget
+ INTC
+
+
+
+
+ CddEmmBit25INTCtpWDTmonitorIMNTRSR89Err
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain4/CddEmmBit25INTCtpWDTmonitorIMNTRSR89Err
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain4/CddEmmBit25INTCtpWDTmonitorIMNTRSR89Err/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain4/CddEmmBit25INTCtpWDTmonitorIMNTRSR89Err/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit26INTCtpWDTmonitorIMNTRSR90Err
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain4/CddEmmBit26INTCtpWDTmonitorIMNTRSR90Err
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain4/CddEmmBit26INTCtpWDTmonitorIMNTRSR90Err/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain4/CddEmmBit26INTCtpWDTmonitorIMNTRSR90Err/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit27INTCtpWDTmonitorIMNTRSR91Err
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain4/CddEmmBit27INTCtpWDTmonitorIMNTRSR91Err
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain4/CddEmmBit27INTCtpWDTmonitorIMNTRSR91Err/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain4/CddEmmBit27INTCtpWDTmonitorIMNTRSR91Err/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit28INTCtpWDTmonitorIMNTRSR92Err
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain4/CddEmmBit28INTCtpWDTmonitorIMNTRSR92Err
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain4/CddEmmBit28INTCtpWDTmonitorIMNTRSR92Err/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain4/CddEmmBit28INTCtpWDTmonitorIMNTRSR92Err/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit29INTCtpWDTmonitorIMNTRSR93Err
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain4/CddEmmBit29INTCtpWDTmonitorIMNTRSR93Err
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain4/CddEmmBit29INTCtpWDTmonitorIMNTRSR93Err/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain4/CddEmmBit29INTCtpWDTmonitorIMNTRSR93Err/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit30INTCtpWDTmonitorIMNTRSR94Err
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain4/CddEmmBit30INTCtpWDTmonitorIMNTRSR94Err
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain4/CddEmmBit30INTCtpWDTmonitorIMNTRSR94Err/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain4/CddEmmBit30INTCtpWDTmonitorIMNTRSR94Err/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit31INTCtpWDTmonitorIMNTRSR95Err
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain4/CddEmmBit31INTCtpWDTmonitorIMNTRSR95Err
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain4/CddEmmBit31INTCtpWDTmonitorIMNTRSR95Err/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain4/CddEmmBit31INTCtpWDTmonitorIMNTRSR95Err/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+
+
+ CddEmmDomain5
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain5
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain5/CddEmmAddressToSaveErrorStatus
+ 1342177300
+
+
+
+
+ CddEmmBit0INTCtpWDTmonitorIMNTRSR96Err
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain5/CddEmmBit0INTCtpWDTmonitorIMNTRSR96Err
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain5/CddEmmBit0INTCtpWDTmonitorIMNTRSR96Err/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain5/CddEmmBit0INTCtpWDTmonitorIMNTRSR96Err/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit1INTCtpWDTmonitorIMNTRSR97Err
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain5/CddEmmBit1INTCtpWDTmonitorIMNTRSR97Err
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain5/CddEmmBit1INTCtpWDTmonitorIMNTRSR97Err/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain5/CddEmmBit1INTCtpWDTmonitorIMNTRSR97Err/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit2INTCtpWDTmonitorIMNTRSR98Err
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain5/CddEmmBit2INTCtpWDTmonitorIMNTRSR98Err
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain5/CddEmmBit2INTCtpWDTmonitorIMNTRSR98Err/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain5/CddEmmBit2INTCtpWDTmonitorIMNTRSR98Err/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit3INTCtpWDTmonitorIMNTRSR99Err
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain5/CddEmmBit3INTCtpWDTmonitorIMNTRSR99Err
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain5/CddEmmBit3INTCtpWDTmonitorIMNTRSR99Err/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain5/CddEmmBit3INTCtpWDTmonitorIMNTRSR99Err/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit4INTCtpWDTmonitorIMNTRSR100Err
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain5/CddEmmBit4INTCtpWDTmonitorIMNTRSR100Err
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain5/CddEmmBit4INTCtpWDTmonitorIMNTRSR100Err/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain5/CddEmmBit4INTCtpWDTmonitorIMNTRSR100Err/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit5INTCtpWDTmonitorIMNTRSR101Err
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain5/CddEmmBit5INTCtpWDTmonitorIMNTRSR101Err
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain5/CddEmmBit5INTCtpWDTmonitorIMNTRSR101Err/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain5/CddEmmBit5INTCtpWDTmonitorIMNTRSR101Err/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit6INTCtpWDTmonitorIMNTRSR102Err
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain5/CddEmmBit6INTCtpWDTmonitorIMNTRSR102Err
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain5/CddEmmBit6INTCtpWDTmonitorIMNTRSR102Err/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain5/CddEmmBit6INTCtpWDTmonitorIMNTRSR102Err/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit7INTCtpWDTmonitorIMNTRSR103Err
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain5/CddEmmBit7INTCtpWDTmonitorIMNTRSR103Err
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain5/CddEmmBit7INTCtpWDTmonitorIMNTRSR103Err/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain5/CddEmmBit7INTCtpWDTmonitorIMNTRSR103Err/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit8INTCtpWDTmonitorIMNTRSR104Err
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain5/CddEmmBit8INTCtpWDTmonitorIMNTRSR104Err
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain5/CddEmmBit8INTCtpWDTmonitorIMNTRSR104Err/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain5/CddEmmBit8INTCtpWDTmonitorIMNTRSR104Err/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit9INTCtpWDTmonitorIMNTRSR105Err
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain5/CddEmmBit9INTCtpWDTmonitorIMNTRSR105Err
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain5/CddEmmBit9INTCtpWDTmonitorIMNTRSR105Err/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain5/CddEmmBit9INTCtpWDTmonitorIMNTRSR105Err/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit10INTCtpWDTmonitorIMNTRSR106Err
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain5/CddEmmBit10INTCtpWDTmonitorIMNTRSR106Err
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain5/CddEmmBit10INTCtpWDTmonitorIMNTRSR106Err/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain5/CddEmmBit10INTCtpWDTmonitorIMNTRSR106Err/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit11INTCtpWDTmonitorIMNTRSR107Err
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain5/CddEmmBit11INTCtpWDTmonitorIMNTRSR107Err
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain5/CddEmmBit11INTCtpWDTmonitorIMNTRSR107Err/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain5/CddEmmBit11INTCtpWDTmonitorIMNTRSR107Err/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit12INTCtpWDTmonitorIMNTRSR108Err
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain5/CddEmmBit12INTCtpWDTmonitorIMNTRSR108Err
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain5/CddEmmBit12INTCtpWDTmonitorIMNTRSR108Err/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain5/CddEmmBit12INTCtpWDTmonitorIMNTRSR108Err/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit13INTCtpWDTmonitorIMNTRSR109Err
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain5/CddEmmBit13INTCtpWDTmonitorIMNTRSR109Err
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain5/CddEmmBit13INTCtpWDTmonitorIMNTRSR109Err/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain5/CddEmmBit13INTCtpWDTmonitorIMNTRSR109Err/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit14INTCtpWDTmonitorIMNTRSR110Err
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain5/CddEmmBit14INTCtpWDTmonitorIMNTRSR110Err
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain5/CddEmmBit14INTCtpWDTmonitorIMNTRSR110Err/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain5/CddEmmBit14INTCtpWDTmonitorIMNTRSR110Err/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit15INTCtpWDTmonitorIMNTRSR111Err
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain5/CddEmmBit15INTCtpWDTmonitorIMNTRSR111Err
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain5/CddEmmBit15INTCtpWDTmonitorIMNTRSR111Err/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain5/CddEmmBit15INTCtpWDTmonitorIMNTRSR111Err/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit16INTCtpWDTmonitorIMNTRSR112Err
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain5/CddEmmBit16INTCtpWDTmonitorIMNTRSR112Err
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain5/CddEmmBit16INTCtpWDTmonitorIMNTRSR112Err/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain5/CddEmmBit16INTCtpWDTmonitorIMNTRSR112Err/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit17INTCtpWDTmonitorIMNTRSR113Err
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain5/CddEmmBit17INTCtpWDTmonitorIMNTRSR113Err
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain5/CddEmmBit17INTCtpWDTmonitorIMNTRSR113Err/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain5/CddEmmBit17INTCtpWDTmonitorIMNTRSR113Err/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit18INTCtpWDTmonitorIMNTRSR114Err
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain5/CddEmmBit18INTCtpWDTmonitorIMNTRSR114Err
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain5/CddEmmBit18INTCtpWDTmonitorIMNTRSR114Err/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain5/CddEmmBit18INTCtpWDTmonitorIMNTRSR114Err/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit19INTCtpWDTmonitorIMNTRSR115Err
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain5/CddEmmBit19INTCtpWDTmonitorIMNTRSR115Err
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain5/CddEmmBit19INTCtpWDTmonitorIMNTRSR115Err/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain5/CddEmmBit19INTCtpWDTmonitorIMNTRSR115Err/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit20INTCtpWDTmonitorIMNTRSR116Err
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain5/CddEmmBit20INTCtpWDTmonitorIMNTRSR116Err
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain5/CddEmmBit20INTCtpWDTmonitorIMNTRSR116Err/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain5/CddEmmBit20INTCtpWDTmonitorIMNTRSR116Err/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit21INTCtpWDTmonitorIMNTRSR117Err
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain5/CddEmmBit21INTCtpWDTmonitorIMNTRSR117Err
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain5/CddEmmBit21INTCtpWDTmonitorIMNTRSR117Err/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain5/CddEmmBit21INTCtpWDTmonitorIMNTRSR117Err/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit22INTCtpWDTmonitorIMNTRSR118Err
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain5/CddEmmBit22INTCtpWDTmonitorIMNTRSR118Err
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain5/CddEmmBit22INTCtpWDTmonitorIMNTRSR118Err/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain5/CddEmmBit22INTCtpWDTmonitorIMNTRSR118Err/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit23INTCtpWDTmonitorIMNTRSR119Err
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain5/CddEmmBit23INTCtpWDTmonitorIMNTRSR119Err
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain5/CddEmmBit23INTCtpWDTmonitorIMNTRSR119Err/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain5/CddEmmBit23INTCtpWDTmonitorIMNTRSR119Err/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit24INTCtpWDTmonitorIMNTRSR120Err
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain5/CddEmmBit24INTCtpWDTmonitorIMNTRSR120Err
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain5/CddEmmBit24INTCtpWDTmonitorIMNTRSR120Err/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain5/CddEmmBit24INTCtpWDTmonitorIMNTRSR120Err/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit25RTCore0EL1controlledMemoryAccessErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain5/CddEmmBit25RTCore0EL1controlledMemoryAccessErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain5/CddEmmBit25RTCore0EL1controlledMemoryAccessErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain5/CddEmmBit25RTCore0EL1controlledMemoryAccessErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit26RTCoreProcessorLivelockErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain5/CddEmmBit26RTCoreProcessorLivelockErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain5/CddEmmBit26RTCoreProcessorLivelockErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain5/CddEmmBit26RTCoreProcessorLivelockErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit27RTCore0SWRunInEL2UnlockTESTR1Err
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain5/CddEmmBit27RTCore0SWRunInEL2UnlockTESTR1Err
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain5/CddEmmBit27RTCore0SWRunInEL2UnlockTESTR1Err/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain5/CddEmmBit27RTCore0SWRunInEL2UnlockTESTR1Err/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit28INTCtpEDCAXI4stream3
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain5/CddEmmBit28INTCtpEDCAXI4stream3
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain5/CddEmmBit28INTCtpEDCAXI4stream3/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain5/CddEmmBit28INTCtpEDCAXI4stream3/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit29INTCtpEDCAXI4stream2
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain5/CddEmmBit29INTCtpEDCAXI4stream2
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain5/CddEmmBit29INTCtpEDCAXI4stream2/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain5/CddEmmBit29INTCtpEDCAXI4stream2/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit30INTCtpEDCAXI4stream1
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain5/CddEmmBit30INTCtpEDCAXI4stream1
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain5/CddEmmBit30INTCtpEDCAXI4stream1/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain5/CddEmmBit30INTCtpEDCAXI4stream1/CddEmmErrorSignalTarget
+ INTC
+
+
+
+
+ CddEmmBit31INTCtpEDCAXI4stream0
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain5/CddEmmBit31INTCtpEDCAXI4stream0
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain5/CddEmmBit31INTCtpEDCAXI4stream0/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain5/CddEmmBit31INTCtpEDCAXI4stream0/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+
+
+ CddEmmDomain6
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain6
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain6/CddEmmAddressToSaveErrorStatus
+ 1342177304
+
+
+
+
+ CddEmmBit7VIPInternalDOFErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain6/CddEmmBit7VIPInternalDOFErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain6/CddEmmBit7VIPInternalDOFErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain6/CddEmmBit7VIPInternalDOFErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit9VIPInternalSMPSErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain6/CddEmmBit9VIPInternalSMPSErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain6/CddEmmBit9VIPInternalSMPSErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain6/CddEmmBit9VIPInternalSMPSErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit11VIPInternalSMPOErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain6/CddEmmBit11VIPInternalSMPOErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain6/CddEmmBit11VIPInternalSMPOErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain6/CddEmmBit11VIPInternalSMPOErr/CddEmmErrorSignalTarget
+ INTC
+
+
+
+
+ CddEmmBit24IMPX7SRAMEDCErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain6/CddEmmBit24IMPX7SRAMEDCErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain6/CddEmmBit24IMPX7SRAMEDCErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain6/CddEmmBit24IMPX7SRAMEDCErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit25IMPX7SRAMECCErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain6/CddEmmBit25IMPX7SRAMECCErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain6/CddEmmBit25IMPX7SRAMECCErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain6/CddEmmBit25IMPX7SRAMECCErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit26IMPX7BusErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain6/CddEmmBit26IMPX7BusErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain6/CddEmmBit26IMPX7BusErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain6/CddEmmBit26IMPX7BusErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit27IMPX7ScratchpadMemoryDCLSErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain6/CddEmmBit27IMPX7ScratchpadMemoryDCLSErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain6/CddEmmBit27IMPX7ScratchpadMemoryDCLSErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain6/CddEmmBit27IMPX7ScratchpadMemoryDCLSErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit28APMUCortexR52Core0ResetControlErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain6/CddEmmBit28APMUCortexR52Core0ResetControlErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain6/CddEmmBit28APMUCortexR52Core0ResetControlErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain6/CddEmmBit28APMUCortexR52Core0ResetControlErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit29APMUAccessProtectErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain6/CddEmmBit29APMUAccessProtectErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain6/CddEmmBit29APMUAccessProtectErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain6/CddEmmBit29APMUAccessProtectErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit30APMUDCLSErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain6/CddEmmBit30APMUDCLSErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain6/CddEmmBit30APMUDCLSErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain6/CddEmmBit30APMUDCLSErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit31MFISCheckerCoreComparisonErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain6/CddEmmBit31MFISCheckerCoreComparisonErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain6/CddEmmBit31MFISCheckerCoreComparisonErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain6/CddEmmBit31MFISCheckerCoreComparisonErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+
+
+ CddEmmDomain7
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain7
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain7/CddEmmAddressToSaveErrorStatus
+ 1342177308
+
+
+
+
+ CddEmmBit0INTCapFaultHandlingInterrupt
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain7/CddEmmBit0INTCapFaultHandlingInterrupt
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain7/CddEmmBit0INTCapFaultHandlingInterrupt/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain7/CddEmmBit0INTCapFaultHandlingInterrupt/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit1INTCapErrorHandlingInterrupt
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain7/CddEmmBit1INTCapErrorHandlingInterrupt
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain7/CddEmmBit1INTCapErrorHandlingInterrupt/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain7/CddEmmBit1INTCapErrorHandlingInterrupt/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit2AXIBusECMVIP0
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain7/CddEmmBit2AXIBusECMVIP0
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain7/CddEmmBit2AXIBusECMVIP0/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain7/CddEmmBit2AXIBusECMVIP0/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit3AXIBusECMVIO0
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain7/CddEmmBit3AXIBusECMVIO0
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain7/CddEmmBit3AXIBusECMVIO0/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain7/CddEmmBit3AXIBusECMVIO0/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit4AXIBusECMVC0
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain7/CddEmmBit4AXIBusECMVC0
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain7/CddEmmBit4AXIBusECMVC0/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain7/CddEmmBit4AXIBusECMVC0/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit5AXIBusECM3DG
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain7/CddEmmBit5AXIBusECM3DG
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain7/CddEmmBit5AXIBusECM3DG/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain7/CddEmmBit5AXIBusECM3DG/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit6AXIBusECMTOP0
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain7/CddEmmBit6AXIBusECMTOP0
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain7/CddEmmBit6AXIBusECMTOP0/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain7/CddEmmBit6AXIBusECMTOP0/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit7AXIBusECMRT0
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain7/CddEmmBit7AXIBusECMRT0
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain7/CddEmmBit7AXIBusECMRT0/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain7/CddEmmBit7AXIBusECMRT0/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit8AXIBusECMHSC
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain7/CddEmmBit8AXIBusECMHSC
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain7/CddEmmBit8AXIBusECMHSC/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain7/CddEmmBit8AXIBusECMHSC/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit9AXIBusECMPER00
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain7/CddEmmBit9AXIBusECMPER00
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain7/CddEmmBit9AXIBusECMPER00/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain7/CddEmmBit9AXIBusECMPER00/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit10AXIBusECMMM
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain7/CddEmmBit10AXIBusECMMM
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain7/CddEmmBit10AXIBusECMMM/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain7/CddEmmBit10AXIBusECMMM/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit11AXIBusECMIMP
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain7/CddEmmBit11AXIBusECMIMP
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain7/CddEmmBit11AXIBusECMIMP/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain7/CddEmmBit11AXIBusECMIMP/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit12VSP2VSPX0InternalSRAMEDCWDTErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain7/CddEmmBit12VSP2VSPX0InternalSRAMEDCWDTErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain7/CddEmmBit12VSP2VSPX0InternalSRAMEDCWDTErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain7/CddEmmBit12VSP2VSPX0InternalSRAMEDCWDTErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit13VSP2VSPX1InternalSRAMEDCWDTErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain7/CddEmmBit13VSP2VSPX1InternalSRAMEDCWDTErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain7/CddEmmBit13VSP2VSPX1InternalSRAMEDCWDTErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain7/CddEmmBit13VSP2VSPX1InternalSRAMEDCWDTErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit19RTVRAM0SafetyAccessProtectionErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain7/CddEmmBit19RTVRAM0SafetyAccessProtectionErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain7/CddEmmBit19RTVRAM0SafetyAccessProtectionErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain7/CddEmmBit19RTVRAM0SafetyAccessProtectionErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit20RTVRAM0SecureAccessProtectionErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain7/CddEmmBit20RTVRAM0SecureAccessProtectionErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain7/CddEmmBit20RTVRAM0SecureAccessProtectionErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain7/CddEmmBit20RTVRAM0SecureAccessProtectionErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit23RTVRAM0TimeoutErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain7/CddEmmBit23RTVRAM0TimeoutErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain7/CddEmmBit23RTVRAM0TimeoutErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain7/CddEmmBit23RTVRAM0TimeoutErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit24INTCapCA76Core3RequestOrderErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain7/CddEmmBit24INTCapCA76Core3RequestOrderErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain7/CddEmmBit24INTCapCA76Core3RequestOrderErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain7/CddEmmBit24INTCapCA76Core3RequestOrderErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit25INTCapCA76Core2RequestOrderErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain7/CddEmmBit25INTCapCA76Core2RequestOrderErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain7/CddEmmBit25INTCapCA76Core2RequestOrderErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain7/CddEmmBit25INTCapCA76Core2RequestOrderErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit26INTCapCA76Core1RequestOrderErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain7/CddEmmBit26INTCapCA76Core1RequestOrderErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain7/CddEmmBit26INTCapCA76Core1RequestOrderErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain7/CddEmmBit26INTCapCA76Core1RequestOrderErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit27INTCapCA76Core0RequestOrderErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain7/CddEmmBit27INTCapCA76Core0RequestOrderErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain7/CddEmmBit27INTCapCA76Core0RequestOrderErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain7/CddEmmBit27INTCapCA76Core0RequestOrderErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit29RTVRAM0EdcMultibitErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain7/CddEmmBit29RTVRAM0EdcMultibitErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain7/CddEmmBit29RTVRAM0EdcMultibitErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain7/CddEmmBit29RTVRAM0EdcMultibitErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit30RTVRAM0Edc1bitErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain7/CddEmmBit30RTVRAM0Edc1bitErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain7/CddEmmBit30RTVRAM0Edc1bitErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain7/CddEmmBit30RTVRAM0Edc1bitErr/CddEmmErrorSignalTarget
+ INTC
+
+
+
+
+
+
+ CddEmmDomain8
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain8
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain8/CddEmmAddressToSaveErrorStatus
+ 1342177312
+
+
+
+
+ CddEmmBit20DSItxlink1EdcErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain8/CddEmmBit20DSItxlink1EdcErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain8/CddEmmBit20DSItxlink1EdcErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain8/CddEmmBit20DSItxlink1EdcErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit21DSItxlink0EdcErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain8/CddEmmBit21DSItxlink0EdcErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain8/CddEmmBit21DSItxlink0EdcErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain8/CddEmmBit21DSItxlink0EdcErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit22APSysCciTransactionOrderCheckMI2Err
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain8/CddEmmBit22APSysCciTransactionOrderCheckMI2Err
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain8/CddEmmBit22APSysCciTransactionOrderCheckMI2Err/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain8/CddEmmBit22APSysCciTransactionOrderCheckMI2Err/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit23APSysCciTransactionOrderCheckMI1Err
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain8/CddEmmBit23APSysCciTransactionOrderCheckMI1Err
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain8/CddEmmBit23APSysCciTransactionOrderCheckMI1Err/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain8/CddEmmBit23APSysCciTransactionOrderCheckMI1Err/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit24FCPCSInternalSRAMEdcErrr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain8/CddEmmBit24FCPCSInternalSRAMEdcErrr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain8/CddEmmBit24FCPCSInternalSRAMEdcErrr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain8/CddEmmBit24FCPCSInternalSRAMEdcErrr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit25VCPL4CEInternalSRAMEdcErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain8/CddEmmBit25VCPL4CEInternalSRAMEdcErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain8/CddEmmBit25VCPL4CEInternalSRAMEdcErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain8/CddEmmBit25VCPL4CEInternalSRAMEdcErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit26VCPL4VLCInternalSRAMEdcErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain8/CddEmmBit26VCPL4VLCInternalSRAMEdcErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain8/CddEmmBit26VCPL4VLCInternalSRAMEdcErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain8/CddEmmBit26VCPL4VLCInternalSRAMEdcErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit27VSP2VSPD1DISCOMUnmatchedWdtErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain8/CddEmmBit27VSP2VSPD1DISCOMUnmatchedWdtErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain8/CddEmmBit27VSP2VSPD1DISCOMUnmatchedWdtErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain8/CddEmmBit27VSP2VSPD1DISCOMUnmatchedWdtErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit28VSP2VSPD1DISCOMFrozenErrWdt
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain8/CddEmmBit28VSP2VSPD1DISCOMFrozenErrWdt
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain8/CddEmmBit28VSP2VSPD1DISCOMFrozenErrWdt/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain8/CddEmmBit28VSP2VSPD1DISCOMFrozenErrWdt/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit29VSP2VSPD0DISCOMUnmatchedWdtErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain8/CddEmmBit29VSP2VSPD0DISCOMUnmatchedWdtErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain8/CddEmmBit29VSP2VSPD0DISCOMUnmatchedWdtErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain8/CddEmmBit29VSP2VSPD0DISCOMUnmatchedWdtErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit30VSP2VSPD0DISCOMFrozenErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain8/CddEmmBit30VSP2VSPD0DISCOMFrozenErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain8/CddEmmBit30VSP2VSPD0DISCOMFrozenErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain8/CddEmmBit30VSP2VSPD0DISCOMFrozenErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit31DSCEdcErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain8/CddEmmBit31DSCEdcErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain8/CddEmmBit31DSCEdcErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain8/CddEmmBit31DSCEdcErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+
+
+ CddEmmDomain9
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain9
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain9/CddEmmAddressToSaveErrorStatus
+ 1342177316
+
+
+
+
+ CddEmmBit24ECMSwGenID0Err
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain9/CddEmmBit24ECMSwGenID0Err
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain9/CddEmmBit24ECMSwGenID0Err/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain9/CddEmmBit24ECMSwGenID0Err/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit25ECMSwGenID1Err
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain9/CddEmmBit25ECMSwGenID1Err
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain9/CddEmmBit25ECMSwGenID1Err/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain9/CddEmmBit25ECMSwGenID1Err/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit26ECMSwGenID2Err
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain9/CddEmmBit26ECMSwGenID2Err
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain9/CddEmmBit26ECMSwGenID2Err/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain9/CddEmmBit26ECMSwGenID2Err/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit27ECMSwGenID3Err
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain9/CddEmmBit27ECMSwGenID3Err
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain9/CddEmmBit27ECMSwGenID3Err/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain9/CddEmmBit27ECMSwGenID3Err/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit28ECMSwGenID4Err
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain9/CddEmmBit28ECMSwGenID4Err
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain9/CddEmmBit28ECMSwGenID4Err/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain9/CddEmmBit28ECMSwGenID4Err/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit29ECMSwGenID5Err
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain9/CddEmmBit29ECMSwGenID5Err
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain9/CddEmmBit29ECMSwGenID5Err/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain9/CddEmmBit29ECMSwGenID5Err/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit30ECMSwGenID6Err
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain9/CddEmmBit30ECMSwGenID6Err
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain9/CddEmmBit30ECMSwGenID6Err/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain9/CddEmmBit30ECMSwGenID6Err/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit31ECMSwGenID7Err
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain9/CddEmmBit31ECMSwGenID7Err
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain9/CddEmmBit31ECMSwGenID7Err/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain9/CddEmmBit31ECMSwGenID7Err/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+
+
+ CddEmmDomain10
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain10
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain10/CddEmmAddressToSaveErrorStatus
+ 1342177320
+
+
+
+
+ CddEmmBit0APSysCciEccSedErrCounter
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain10/CddEmmBit0APSysCciEccSedErrCounter
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain10/CddEmmBit0APSysCciEccSedErrCounter/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain10/CddEmmBit0APSysCciEccSedErrCounter/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain10/CddEmmBit0APSysCciEccSedErrCounter/CddEmmErrorMaxCount
+ 1
+
+
+
+
+ CddEmmBit1APSysCciEccEdcErrCounter
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain10/CddEmmBit1APSysCciEccEdcErrCounter
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain10/CddEmmBit1APSysCciEccEdcErrCounter/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain10/CddEmmBit1APSysCciEccEdcErrCounter/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain10/CddEmmBit1APSysCciEccEdcErrCounter/CddEmmErrorMaxCount
+ 1
+
+
+
+
+ CddEmmBit2RTVRAMRTVRAM0Edc1bitErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain10/CddEmmBit2RTVRAMRTVRAM0Edc1bitErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain10/CddEmmBit2RTVRAMRTVRAM0Edc1bitErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain10/CddEmmBit2RTVRAMRTVRAM0Edc1bitErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain10/CddEmmBit2RTVRAMRTVRAM0Edc1bitErr/CddEmmErrorMaxCount
+ 1
+
+
+
+
+ CddEmmBit3RTVRAMRTVRAM0EdcMulbitErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain10/CddEmmBit3RTVRAMRTVRAM0EdcMulbitErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain10/CddEmmBit3RTVRAMRTVRAM0EdcMulbitErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain10/CddEmmBit3RTVRAMRTVRAM0EdcMulbitErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain10/CddEmmBit3RTVRAMRTVRAM0EdcMulbitErr/CddEmmErrorMaxCount
+ 1
+
+
+
+
+ CddEmmBit6RTCore0TCMCorrectableErrCounter
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain10/CddEmmBit6RTCore0TCMCorrectableErrCounter
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain10/CddEmmBit6RTCore0TCMCorrectableErrCounter/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain10/CddEmmBit6RTCore0TCMCorrectableErrCounter/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain10/CddEmmBit6RTCore0TCMCorrectableErrCounter/CddEmmErrorMaxCount
+ 1
+
+
+
+
+ CddEmmBit8RTCore0InstructionCacheErrCounter
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain10/CddEmmBit8RTCore0InstructionCacheErrCounter
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain10/CddEmmBit8RTCore0InstructionCacheErrCounter/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain10/CddEmmBit8RTCore0InstructionCacheErrCounter/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain10/CddEmmBit8RTCore0InstructionCacheErrCounter/CddEmmErrorMaxCount
+ 1
+
+
+
+
+ CddEmmBit10RTCore0DataCacheErrCounter
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain10/CddEmmBit10RTCore0DataCacheErrCounter
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain10/CddEmmBit10RTCore0DataCacheErrCounter/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain10/CddEmmBit10RTCore0DataCacheErrCounter/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain10/CddEmmBit10RTCore0DataCacheErrCounter/CddEmmErrorMaxCount
+ 1
+
+
+
+
+ CddEmmBit12RTCore0AXISICorrectableErrCounter
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain10/CddEmmBit12RTCore0AXISICorrectableErrCounter
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain10/CddEmmBit12RTCore0AXISICorrectableErrCounter/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain10/CddEmmBit12RTCore0AXISICorrectableErrCounter/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain10/CddEmmBit12RTCore0AXISICorrectableErrCounter/CddEmmErrorMaxCount
+ 1
+
+
+
+
+ CddEmmBit14RTCore0AXIMICorrectableErrCounter
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain10/CddEmmBit14RTCore0AXIMICorrectableErrCounter
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain10/CddEmmBit14RTCore0AXIMICorrectableErrCounter/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain10/CddEmmBit14RTCore0AXIMICorrectableErrCounter/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain10/CddEmmBit14RTCore0AXIMICorrectableErrCounter/CddEmmErrorMaxCount
+ 1
+
+
+
+
+ CddEmmBit16RTCore0ErrCounter
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain10/CddEmmBit16RTCore0ErrCounter
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain10/CddEmmBit16RTCore0ErrCounter/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain10/CddEmmBit16RTCore0ErrCounter/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain10/CddEmmBit16RTCore0ErrCounter/CddEmmErrorMaxCount
+ 1
+
+
+
+
+ CddEmmBit18RTVRAM1Edc1bitCountupErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain10/CddEmmBit18RTVRAM1Edc1bitCountupErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain10/CddEmmBit18RTVRAM1Edc1bitCountupErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain10/CddEmmBit18RTVRAM1Edc1bitCountupErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain10/CddEmmBit18RTVRAM1Edc1bitCountupErr/CddEmmErrorMaxCount
+ 1
+
+
+
+
+ CddEmmBit19RTVRAM1EdcMulbitErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain10/CddEmmBit19RTVRAM1EdcMulbitErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain10/CddEmmBit19RTVRAM1EdcMulbitErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain10/CddEmmBit19RTVRAM1EdcMulbitErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain10/CddEmmBit19RTVRAM1EdcMulbitErr/CddEmmErrorMaxCount
+ 1
+
+
+
+
+ CddEmmBit20IPMMUmmTLBRAMEdc1bitCountupErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain10/CddEmmBit20IPMMUmmTLBRAMEdc1bitCountupErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain10/CddEmmBit20IPMMUmmTLBRAMEdc1bitCountupErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain10/CddEmmBit20IPMMUmmTLBRAMEdc1bitCountupErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain10/CddEmmBit20IPMMUmmTLBRAMEdc1bitCountupErr/CddEmmErrorMaxCount
+ 1
+
+
+
+
+ CddEmmBit21IPMMUmmTLBRAMEdcMultibitCountupErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain10/CddEmmBit21IPMMUmmTLBRAMEdcMultibitCountupErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain10/CddEmmBit21IPMMUmmTLBRAMEdcMultibitCountupErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain10/CddEmmBit21IPMMUmmTLBRAMEdcMultibitCountupErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain10/CddEmmBit21IPMMUmmTLBRAMEdcMultibitCountupErr/CddEmmErrorMaxCount
+ 1
+
+
+
+
+ CddEmmBit22RTCore1AXIMICorrectableErrCounter
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain10/CddEmmBit22RTCore1AXIMICorrectableErrCounter
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain10/CddEmmBit22RTCore1AXIMICorrectableErrCounter/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain10/CddEmmBit22RTCore1AXIMICorrectableErrCounter/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain10/CddEmmBit22RTCore1AXIMICorrectableErrCounter/CddEmmErrorMaxCount
+ 1
+
+
+
+
+ CddEmmBit24RTCore1AXISICorrectableErrCounter
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain10/CddEmmBit24RTCore1AXISICorrectableErrCounter
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain10/CddEmmBit24RTCore1AXISICorrectableErrCounter/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain10/CddEmmBit24RTCore1AXISICorrectableErrCounter/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain10/CddEmmBit24RTCore1AXISICorrectableErrCounter/CddEmmErrorMaxCount
+ 1
+
+
+
+
+ CddEmmBit26RTCore1DataCacheErrCounter
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain10/CddEmmBit26RTCore1DataCacheErrCounter
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain10/CddEmmBit26RTCore1DataCacheErrCounter/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain10/CddEmmBit26RTCore1DataCacheErrCounter/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain10/CddEmmBit26RTCore1DataCacheErrCounter/CddEmmErrorMaxCount
+ 1
+
+
+
+
+ CddEmmBit28RTCore1InstructionCacheErrCounter
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain10/CddEmmBit28RTCore1InstructionCacheErrCounter
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain10/CddEmmBit28RTCore1InstructionCacheErrCounter/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain10/CddEmmBit28RTCore1InstructionCacheErrCounter/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain10/CddEmmBit28RTCore1InstructionCacheErrCounter/CddEmmErrorMaxCount
+ 1
+
+
+
+
+ CddEmmBit30RTCore1ErrCounter
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain10/CddEmmBit30RTCore1ErrCounter
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain10/CddEmmBit30RTCore1ErrCounter/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain10/CddEmmBit30RTCore1ErrCounter/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain10/CddEmmBit30RTCore1ErrCounter/CddEmmErrorMaxCount
+ 1
+
+
+
+
+
+
+ CddEmmDomain11
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain11
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain11/CddEmmAddressToSaveErrorStatus
+ 1342177324
+
+
+
+
+ CddEmmBit0RTCore1TCMCorrectableErrCounter
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain11/CddEmmBit0RTCore1TCMCorrectableErrCounter
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain11/CddEmmBit0RTCore1TCMCorrectableErrCounter/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain11/CddEmmBit0RTCore1TCMCorrectableErrCounter/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain11/CddEmmBit0RTCore1TCMCorrectableErrCounter/CddEmmErrorMaxCount
+ 1
+
+
+
+
+ CddEmmBit2RTCore2AXIMICorrectableErrCounter
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain11/CddEmmBit2RTCore2AXIMICorrectableErrCounter
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain11/CddEmmBit2RTCore2AXIMICorrectableErrCounter/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain11/CddEmmBit2RTCore2AXIMICorrectableErrCounter/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain11/CddEmmBit2RTCore2AXIMICorrectableErrCounter/CddEmmErrorMaxCount
+ 1
+
+
+
+
+ CddEmmBit4RTCore2AXISICorrectableErrCounter
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain11/CddEmmBit4RTCore2AXISICorrectableErrCounter
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain11/CddEmmBit4RTCore2AXISICorrectableErrCounter/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain11/CddEmmBit4RTCore2AXISICorrectableErrCounter/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain11/CddEmmBit4RTCore2AXISICorrectableErrCounter/CddEmmErrorMaxCount
+ 1
+
+
+
+
+ CddEmmBit6RTCore2DataCacheErrCounter
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain11/CddEmmBit6RTCore2DataCacheErrCounter
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain11/CddEmmBit6RTCore2DataCacheErrCounter/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain11/CddEmmBit6RTCore2DataCacheErrCounter/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain11/CddEmmBit6RTCore2DataCacheErrCounter/CddEmmErrorMaxCount
+ 1
+
+
+
+
+ CddEmmBit8RTCore2InstructionCacheErrCounter
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain11/CddEmmBit8RTCore2InstructionCacheErrCounter
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain11/CddEmmBit8RTCore2InstructionCacheErrCounter/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain11/CddEmmBit8RTCore2InstructionCacheErrCounter/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain11/CddEmmBit8RTCore2InstructionCacheErrCounter/CddEmmErrorMaxCount
+ 1
+
+
+
+
+ CddEmmBit10RTCore2ErrCounter
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain11/CddEmmBit10RTCore2ErrCounter
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain11/CddEmmBit10RTCore2ErrCounter/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain11/CddEmmBit10RTCore2ErrCounter/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain11/CddEmmBit10RTCore2ErrCounter/CddEmmErrorMaxCount
+ 1
+
+
+
+
+ CddEmmBit12RTCore2TCMCorrectableErrCounter
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain11/CddEmmBit12RTCore2TCMCorrectableErrCounter
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain11/CddEmmBit12RTCore2TCMCorrectableErrCounter/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain11/CddEmmBit12RTCore2TCMCorrectableErrCounter/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain11/CddEmmBit12RTCore2TCMCorrectableErrCounter/CddEmmErrorMaxCount
+ 1
+
+
+
+
+ CddEmmBit18APSysCA76Core3L1IL1DL2MmuCorrectedErrCounter
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain11/CddEmmBit18APSysCA76Core3L1IL1DL2MmuCorrectedErrCounter
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain11/CddEmmBit18APSysCA76Core3L1IL1DL2MmuCorrectedErrCounter/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain11/CddEmmBit18APSysCA76Core3L1IL1DL2MmuCorrectedErrCounter/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain11/CddEmmBit18APSysCA76Core3L1IL1DL2MmuCorrectedErrCounter/CddEmmErrorMaxCount
+ 1
+
+
+
+
+ CddEmmBit19APSysCA76Core3L1IL1DL2MmuUncorrectedErrCounter
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain11/CddEmmBit19APSysCA76Core3L1IL1DL2MmuUncorrectedErrCounter
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain11/CddEmmBit19APSysCA76Core3L1IL1DL2MmuUncorrectedErrCounter/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain11/CddEmmBit19APSysCA76Core3L1IL1DL2MmuUncorrectedErrCounter/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain11/CddEmmBit19APSysCA76Core3L1IL1DL2MmuUncorrectedErrCounter/CddEmmErrorMaxCount
+ 1
+
+
+
+
+ CddEmmBit20APSysCA76Core2L1IL1DL2MmuCorrectedErrCounter
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain11/CddEmmBit20APSysCA76Core2L1IL1DL2MmuCorrectedErrCounter
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain11/CddEmmBit20APSysCA76Core2L1IL1DL2MmuCorrectedErrCounter/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain11/CddEmmBit20APSysCA76Core2L1IL1DL2MmuCorrectedErrCounter/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain11/CddEmmBit20APSysCA76Core2L1IL1DL2MmuCorrectedErrCounter/CddEmmErrorMaxCount
+ 1
+
+
+
+
+ CddEmmBit21APSysCA76Core2L1IL1DL2MmuUncorrectedErrCounter
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain11/CddEmmBit21APSysCA76Core2L1IL1DL2MmuUncorrectedErrCounter
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain11/CddEmmBit21APSysCA76Core2L1IL1DL2MmuUncorrectedErrCounter/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain11/CddEmmBit21APSysCA76Core2L1IL1DL2MmuUncorrectedErrCounter/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain11/CddEmmBit21APSysCA76Core2L1IL1DL2MmuUncorrectedErrCounter/CddEmmErrorMaxCount
+ 1
+
+
+
+
+ CddEmmBit22APSysL3Cl1CorrectedErrCounter
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain11/CddEmmBit22APSysL3Cl1CorrectedErrCounter
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain11/CddEmmBit22APSysL3Cl1CorrectedErrCounter/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain11/CddEmmBit22APSysL3Cl1CorrectedErrCounter/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain11/CddEmmBit22APSysL3Cl1CorrectedErrCounter/CddEmmErrorMaxCount
+ 1
+
+
+
+
+ CddEmmBit23APSysL3Cl1UnCorrectedErrCounter
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain11/CddEmmBit23APSysL3Cl1UnCorrectedErrCounter
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain11/CddEmmBit23APSysL3Cl1UnCorrectedErrCounter/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain11/CddEmmBit23APSysL3Cl1UnCorrectedErrCounter/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain11/CddEmmBit23APSysL3Cl1UnCorrectedErrCounter/CddEmmErrorMaxCount
+ 1
+
+
+
+
+ CddEmmBit24APSysCA76Core1L1IL1DL2MmuCorrectedErrCounter
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain11/CddEmmBit24APSysCA76Core1L1IL1DL2MmuCorrectedErrCounter
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain11/CddEmmBit24APSysCA76Core1L1IL1DL2MmuCorrectedErrCounter/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain11/CddEmmBit24APSysCA76Core1L1IL1DL2MmuCorrectedErrCounter/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain11/CddEmmBit24APSysCA76Core1L1IL1DL2MmuCorrectedErrCounter/CddEmmErrorMaxCount
+ 1
+
+
+
+
+ CddEmmBit25APSysCA76Core1L1IL1DL2MmuUncorrectedErrCounter
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain11/CddEmmBit25APSysCA76Core1L1IL1DL2MmuUncorrectedErrCounter
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain11/CddEmmBit25APSysCA76Core1L1IL1DL2MmuUncorrectedErrCounter/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain11/CddEmmBit25APSysCA76Core1L1IL1DL2MmuUncorrectedErrCounter/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain11/CddEmmBit25APSysCA76Core1L1IL1DL2MmuUncorrectedErrCounter/CddEmmErrorMaxCount
+ 1
+
+
+
+
+ CddEmmBit26APSysCA76Core0L1IL1DL2MmuCorrectedErrCounter
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain11/CddEmmBit26APSysCA76Core0L1IL1DL2MmuCorrectedErrCounter
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain11/CddEmmBit26APSysCA76Core0L1IL1DL2MmuCorrectedErrCounter/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain11/CddEmmBit26APSysCA76Core0L1IL1DL2MmuCorrectedErrCounter/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain11/CddEmmBit26APSysCA76Core0L1IL1DL2MmuCorrectedErrCounter/CddEmmErrorMaxCount
+ 1
+
+
+
+
+ CddEmmBit27APSysCA76Core0L1IL1DL2MmuUncorrectedErrCounter
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain11/CddEmmBit27APSysCA76Core0L1IL1DL2MmuUncorrectedErrCounter
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain11/CddEmmBit27APSysCA76Core0L1IL1DL2MmuUncorrectedErrCounter/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain11/CddEmmBit27APSysCA76Core0L1IL1DL2MmuUncorrectedErrCounter/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain11/CddEmmBit27APSysCA76Core0L1IL1DL2MmuUncorrectedErrCounter/CddEmmErrorMaxCount
+ 1
+
+
+
+
+ CddEmmBit28APSysL3Cl0correctedErrCounter
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain11/CddEmmBit28APSysL3Cl0correctedErrCounter
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain11/CddEmmBit28APSysL3Cl0correctedErrCounter/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain11/CddEmmBit28APSysL3Cl0correctedErrCounter/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain11/CddEmmBit28APSysL3Cl0correctedErrCounter/CddEmmErrorMaxCount
+ 1
+
+
+
+
+ CddEmmBit29APSysL3Cl0UncorrectedErrCounter
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain11/CddEmmBit29APSysL3Cl0UncorrectedErrCounter
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain11/CddEmmBit29APSysL3Cl0UncorrectedErrCounter/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain11/CddEmmBit29APSysL3Cl0UncorrectedErrCounter/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain11/CddEmmBit29APSysL3Cl0UncorrectedErrCounter/CddEmmErrorMaxCount
+ 1
+
+
+
+
+ CddEmmBit30CANFDRAMEcc1bitErrCounter
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain11/CddEmmBit30CANFDRAMEcc1bitErrCounter
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain11/CddEmmBit30CANFDRAMEcc1bitErrCounter/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain11/CddEmmBit30CANFDRAMEcc1bitErrCounter/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain11/CddEmmBit30CANFDRAMEcc1bitErrCounter/CddEmmErrorMaxCount
+ 1
+
+
+
+
+ CddEmmBit31CANFDRAMEcc2bitErrCounter
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain11/CddEmmBit31CANFDRAMEcc2bitErrCounter
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain11/CddEmmBit31CANFDRAMEcc2bitErrCounter/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain11/CddEmmBit31CANFDRAMEcc2bitErrCounter/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain11/CddEmmBit31CANFDRAMEcc2bitErrCounter/CddEmmErrorMaxCount
+ 1
+
+
+
+
+
+
+ CddEmmDomain12
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain12
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain12/CddEmmAddressToSaveErrorStatus
+ 1342177328
+
+
+
+
+ CddEmmBit0FLEXRAYTBF2InterruptNotificationEccErrCounter
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain12/CddEmmBit0FLEXRAYTBF2InterruptNotificationEccErrCounter
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain12/CddEmmBit0FLEXRAYTBF2InterruptNotificationEccErrCounter/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain12/CddEmmBit0FLEXRAYTBF2InterruptNotificationEccErrCounter/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain12/CddEmmBit0FLEXRAYTBF2InterruptNotificationEccErrCounter/CddEmmErrorMaxCount
+ 1
+
+
+
+
+ CddEmmBit1FLEXRAYTBF2InterruptNotificationEdcErrCounter
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain12/CddEmmBit1FLEXRAYTBF2InterruptNotificationEdcErrCounter
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain12/CddEmmBit1FLEXRAYTBF2InterruptNotificationEdcErrCounter/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain12/CddEmmBit1FLEXRAYTBF2InterruptNotificationEdcErrCounter/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain12/CddEmmBit1FLEXRAYTBF2InterruptNotificationEdcErrCounter/CddEmmErrorMaxCount
+ 1
+
+
+
+
+ CddEmmBit2FLEXRAYTBF1InterruptNotificationEccErrCounter
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain12/CddEmmBit2FLEXRAYTBF1InterruptNotificationEccErrCounter
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain12/CddEmmBit2FLEXRAYTBF1InterruptNotificationEccErrCounter/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain12/CddEmmBit2FLEXRAYTBF1InterruptNotificationEccErrCounter/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain12/CddEmmBit2FLEXRAYTBF1InterruptNotificationEccErrCounter/CddEmmErrorMaxCount
+ 1
+
+
+
+
+ CddEmmBit3FLEXRAYTBF1InterruptNotificationEdcErrCounter
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain12/CddEmmBit3FLEXRAYTBF1InterruptNotificationEdcErrCounter
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain12/CddEmmBit3FLEXRAYTBF1InterruptNotificationEdcErrCounter/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain12/CddEmmBit3FLEXRAYTBF1InterruptNotificationEdcErrCounter/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain12/CddEmmBit3FLEXRAYTBF1InterruptNotificationEdcErrCounter/CddEmmErrorMaxCount
+ 1
+
+
+
+
+ CddEmmBit4FLEXRAYMBFInterruptNotificationEccErrCounter
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain12/CddEmmBit4FLEXRAYMBFInterruptNotificationEccErrCounter
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain12/CddEmmBit4FLEXRAYMBFInterruptNotificationEccErrCounter/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain12/CddEmmBit4FLEXRAYMBFInterruptNotificationEccErrCounter/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain12/CddEmmBit4FLEXRAYMBFInterruptNotificationEccErrCounter/CddEmmErrorMaxCount
+ 1
+
+
+
+
+ CddEmmBit5FLEXRAYMBFInterruptNotificationEdcErrCounter
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain12/CddEmmBit5FLEXRAYMBFInterruptNotificationEdcErrCounter
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain12/CddEmmBit5FLEXRAYMBFInterruptNotificationEdcErrCounter/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain12/CddEmmBit5FLEXRAYMBFInterruptNotificationEdcErrCounter/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain12/CddEmmBit5FLEXRAYMBFInterruptNotificationEdcErrCounter/CddEmmErrorMaxCount
+ 1
+
+
+
+
+ CddEmmBit6EtherAVB2TXRAMEcc1bitErrCounter
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain12/CddEmmBit6EtherAVB2TXRAMEcc1bitErrCounter
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain12/CddEmmBit6EtherAVB2TXRAMEcc1bitErrCounter/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain12/CddEmmBit6EtherAVB2TXRAMEcc1bitErrCounter/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain12/CddEmmBit6EtherAVB2TXRAMEcc1bitErrCounter/CddEmmErrorMaxCount
+ 1
+
+
+
+
+ CddEmmBit7EtherAVB2TXRAMEccMultibitErrCounter
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain12/CddEmmBit7EtherAVB2TXRAMEccMultibitErrCounter
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain12/CddEmmBit7EtherAVB2TXRAMEccMultibitErrCounter/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain12/CddEmmBit7EtherAVB2TXRAMEccMultibitErrCounter/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain12/CddEmmBit7EtherAVB2TXRAMEccMultibitErrCounter/CddEmmErrorMaxCount
+ 1
+
+
+
+
+ CddEmmBit8EtherAVB2RXRAMEcc1bitErrCounter
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain12/CddEmmBit8EtherAVB2RXRAMEcc1bitErrCounter
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain12/CddEmmBit8EtherAVB2RXRAMEcc1bitErrCounter/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain12/CddEmmBit8EtherAVB2RXRAMEcc1bitErrCounter/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain12/CddEmmBit8EtherAVB2RXRAMEcc1bitErrCounter/CddEmmErrorMaxCount
+ 1
+
+
+
+
+ CddEmmBit9EtherAVB2RXRAMEccMultibitErrCounter
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain12/CddEmmBit9EtherAVB2RXRAMEccMultibitErrCounter
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain12/CddEmmBit9EtherAVB2RXRAMEccMultibitErrCounter/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain12/CddEmmBit9EtherAVB2RXRAMEccMultibitErrCounter/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain12/CddEmmBit9EtherAVB2RXRAMEccMultibitErrCounter/CddEmmErrorMaxCount
+ 1
+
+
+
+
+ CddEmmBit10EtherAVB1TXRAMEcc1bitErrCounter
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain12/CddEmmBit10EtherAVB1TXRAMEcc1bitErrCounter
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain12/CddEmmBit10EtherAVB1TXRAMEcc1bitErrCounter/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain12/CddEmmBit10EtherAVB1TXRAMEcc1bitErrCounter/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain12/CddEmmBit10EtherAVB1TXRAMEcc1bitErrCounter/CddEmmErrorMaxCount
+ 1
+
+
+
+
+ CddEmmBit11EtherAVB1TXRAMEccMultibitErrCounter
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain12/CddEmmBit11EtherAVB1TXRAMEccMultibitErrCounter
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain12/CddEmmBit11EtherAVB1TXRAMEccMultibitErrCounter/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain12/CddEmmBit11EtherAVB1TXRAMEccMultibitErrCounter/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain12/CddEmmBit11EtherAVB1TXRAMEccMultibitErrCounter/CddEmmErrorMaxCount
+ 1
+
+
+
+
+ CddEmmBit12EtherAVB1RXRAMEcc1bitErrCounter
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain12/CddEmmBit12EtherAVB1RXRAMEcc1bitErrCounter
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain12/CddEmmBit12EtherAVB1RXRAMEcc1bitErrCounter/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain12/CddEmmBit12EtherAVB1RXRAMEcc1bitErrCounter/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain12/CddEmmBit12EtherAVB1RXRAMEcc1bitErrCounter/CddEmmErrorMaxCount
+ 1
+
+
+
+
+ CddEmmBit13EtherAVB1RXRAMEccMultibitErrCounter
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain12/CddEmmBit13EtherAVB1RXRAMEccMultibitErrCounter
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain12/CddEmmBit13EtherAVB1RXRAMEccMultibitErrCounter/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain12/CddEmmBit13EtherAVB1RXRAMEccMultibitErrCounter/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain12/CddEmmBit13EtherAVB1RXRAMEccMultibitErrCounter/CddEmmErrorMaxCount
+ 1
+
+
+
+
+ CddEmmBit14EtherAVB0TXRAMEcc1bitErrCounter
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain12/CddEmmBit14EtherAVB0TXRAMEcc1bitErrCounter
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain12/CddEmmBit14EtherAVB0TXRAMEcc1bitErrCounter/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain12/CddEmmBit14EtherAVB0TXRAMEcc1bitErrCounter/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain12/CddEmmBit14EtherAVB0TXRAMEcc1bitErrCounter/CddEmmErrorMaxCount
+ 1
+
+
+
+
+ CddEmmBit15EtherAVB0TXRAMEccMultibitErrCounter
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain12/CddEmmBit15EtherAVB0TXRAMEccMultibitErrCounter
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain12/CddEmmBit15EtherAVB0TXRAMEccMultibitErrCounter/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain12/CddEmmBit15EtherAVB0TXRAMEccMultibitErrCounter/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain12/CddEmmBit15EtherAVB0TXRAMEccMultibitErrCounter/CddEmmErrorMaxCount
+ 1
+
+
+
+
+ CddEmmBit16EtherAVB0RXRAMEcc1bitErrCounter
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain12/CddEmmBit16EtherAVB0RXRAMEcc1bitErrCounter
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain12/CddEmmBit16EtherAVB0RXRAMEcc1bitErrCounter/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain12/CddEmmBit16EtherAVB0RXRAMEcc1bitErrCounter/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain12/CddEmmBit16EtherAVB0RXRAMEcc1bitErrCounter/CddEmmErrorMaxCount
+ 1
+
+
+
+
+ CddEmmBit17EtherAVB0RXRAMEccMultibitErrCounter
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain12/CddEmmBit17EtherAVB0RXRAMEccMultibitErrCounter
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain12/CddEmmBit17EtherAVB0RXRAMEccMultibitErrCounter/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain12/CddEmmBit17EtherAVB0RXRAMEccMultibitErrCounter/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain12/CddEmmBit17EtherAVB0RXRAMEccMultibitErrCounter/CddEmmErrorMaxCount
+ 1
+
+
+
+
+ CddEmmBit18EtherTSNRxDataSRAMEDCErrCounter
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain12/CddEmmBit18EtherTSNRxDataSRAMEDCErrCounter
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain12/CddEmmBit18EtherTSNRxDataSRAMEDCErrCounter/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain12/CddEmmBit18EtherTSNRxDataSRAMEDCErrCounter/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain12/CddEmmBit18EtherTSNRxDataSRAMEDCErrCounter/CddEmmErrorMaxCount
+ 1
+
+
+
+
+ CddEmmBit20EtherTSNRxCtrlSRAMEDCErrCounter
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain12/CddEmmBit20EtherTSNRxCtrlSRAMEDCErrCounter
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain12/CddEmmBit20EtherTSNRxCtrlSRAMEDCErrCounter/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain12/CddEmmBit20EtherTSNRxCtrlSRAMEDCErrCounter/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain12/CddEmmBit20EtherTSNRxCtrlSRAMEDCErrCounter/CddEmmErrorMaxCount
+ 1
+
+
+
+
+ CddEmmBit22EtherTSNTxDataSRAMEDCErrCounter
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain12/CddEmmBit22EtherTSNTxDataSRAMEDCErrCounter
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain12/CddEmmBit22EtherTSNTxDataSRAMEDCErrCounter/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain12/CddEmmBit22EtherTSNTxDataSRAMEDCErrCounter/CddEmmErrorSignalTarget
+ INTC
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain12/CddEmmBit22EtherTSNTxDataSRAMEDCErrCounter/CddEmmErrorMaxCount
+ 1
+
+
+
+
+ CddEmmBit24EtherTSNTxCtrlSRAMEDCErrCounter
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain12/CddEmmBit24EtherTSNTxCtrlSRAMEDCErrCounter
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain12/CddEmmBit24EtherTSNTxCtrlSRAMEDCErrCounter/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain12/CddEmmBit24EtherTSNTxCtrlSRAMEDCErrCounter/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain12/CddEmmBit24EtherTSNTxCtrlSRAMEDCErrCounter/CddEmmErrorMaxCount
+ 1
+
+
+
+
+ CddEmmBit26EtherTSNTASCtrlListSRAMEDCErrCounter
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain12/CddEmmBit26EtherTSNTASCtrlListSRAMEDCErrCounter
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain12/CddEmmBit26EtherTSNTASCtrlListSRAMEDCErrCounter/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain12/CddEmmBit26EtherTSNTASCtrlListSRAMEDCErrCounter/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain12/CddEmmBit26EtherTSNTASCtrlListSRAMEDCErrCounter/CddEmmErrorMaxCount
+ 1
+
+
+
+
+ CddEmmBit28EtherTSNPSFPCtrlListSRAMEDCErrCounter
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain12/CddEmmBit28EtherTSNPSFPCtrlListSRAMEDCErrCounter
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain12/CddEmmBit28EtherTSNPSFPCtrlListSRAMEDCErrCounter/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain12/CddEmmBit28EtherTSNPSFPCtrlListSRAMEDCErrCounter/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain12/CddEmmBit28EtherTSNPSFPCtrlListSRAMEDCErrCounter/CddEmmErrorMaxCount
+ 1
+
+
+
+
+ CddEmmBit30EtherTSNRxDescriptionrAdrrSRAMEDCErrCounter
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain12/CddEmmBit30EtherTSNRxDescriptionrAdrrSRAMEDCErrCounter
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain12/CddEmmBit30EtherTSNRxDescriptionrAdrrSRAMEDCErrCounter/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain12/CddEmmBit30EtherTSNRxDescriptionrAdrrSRAMEDCErrCounter/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain12/CddEmmBit30EtherTSNRxDescriptionrAdrrSRAMEDCErrCounter/CddEmmErrorMaxCount
+ 1
+
+
+
+
+
+
+ CddEmmDomain13
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain13
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain13/CddEmmAddressToSaveErrorStatus
+ 1342177332
+
+
+
+
+ CddEmmBit0EtherTSNTxDescriptionrAdrrSRAMEDCErrCounter
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain13/CddEmmBit0EtherTSNTxDescriptionrAdrrSRAMEDCErrCounter
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain13/CddEmmBit0EtherTSNTxDescriptionrAdrrSRAMEDCErrCounter/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain13/CddEmmBit0EtherTSNTxDescriptionrAdrrSRAMEDCErrCounter/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain13/CddEmmBit0EtherTSNTxDescriptionrAdrrSRAMEDCErrCounter/CddEmmErrorMaxCount
+ 1
+
+
+
+
+ CddEmmBit2EtherTSNTxBufferAdrrSRAMEDCErrCounter
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain13/CddEmmBit2EtherTSNTxBufferAdrrSRAMEDCErrCounter
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain13/CddEmmBit2EtherTSNTxBufferAdrrSRAMEDCErrCounter/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain13/CddEmmBit2EtherTSNTxBufferAdrrSRAMEDCErrCounter/CddEmmErrorSignalTarget
+ INTC
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain13/CddEmmBit2EtherTSNTxBufferAdrrSRAMEDCErrCounter/CddEmmErrorMaxCount
+ 1
+
+
+
+
+ CddEmmBit4EtherTSNRxEFrameBufferAdrrSRAMEDCErrCounter
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain13/CddEmmBit4EtherTSNRxEFrameBufferAdrrSRAMEDCErrCounter
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain13/CddEmmBit4EtherTSNRxEFrameBufferAdrrSRAMEDCErrCounter/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain13/CddEmmBit4EtherTSNRxEFrameBufferAdrrSRAMEDCErrCounter/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain13/CddEmmBit4EtherTSNRxEFrameBufferAdrrSRAMEDCErrCounter/CddEmmErrorMaxCount
+ 1
+
+
+
+
+ CddEmmBit6EtherTSNRxPFrameBufferAdrrSRAMEDCErrCounter
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain13/CddEmmBit6EtherTSNRxPFrameBufferAdrrSRAMEDCErrCounter
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain13/CddEmmBit6EtherTSNRxPFrameBufferAdrrSRAMEDCErrCounter/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain13/CddEmmBit6EtherTSNRxPFrameBufferAdrrSRAMEDCErrCounter/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain13/CddEmmBit6EtherTSNRxPFrameBufferAdrrSRAMEDCErrCounter/CddEmmErrorMaxCount
+ 1
+
+
+
+
+
+
+ CddEmmDomain16
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain16
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain16/CddEmmAddressToSaveErrorStatus
+ 1342177344
+
+
+
+
+ CddEmmBit0RTCore0EDCBtwRTCPUAXISlavebridgeErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain16/CddEmmBit0RTCore0EDCBtwRTCPUAXISlavebridgeErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain16/CddEmmBit0RTCore0EDCBtwRTCPUAXISlavebridgeErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain16/CddEmmBit0RTCore0EDCBtwRTCPUAXISlavebridgeErr/CddEmmErrorSignalTarget
+ INTC
+
+
+
+
+ CddEmmBit1RTCore0TCMMemoriesFatalErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain16/CddEmmBit1RTCore0TCMMemoriesFatalErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain16/CddEmmBit1RTCore0TCMMemoriesFatalErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain16/CddEmmBit1RTCore0TCMMemoriesFatalErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit2RTCore0TCMCorrectableErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain16/CddEmmBit2RTCore0TCMCorrectableErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain16/CddEmmBit2RTCore0TCMCorrectableErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain16/CddEmmBit2RTCore0TCMCorrectableErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit3RTCore0EDCBtwRTCPUWritebufferErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain16/CddEmmBit3RTCore0EDCBtwRTCPUWritebufferErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain16/CddEmmBit3RTCore0EDCBtwRTCPUWritebufferErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain16/CddEmmBit3RTCore0EDCBtwRTCPUWritebufferErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit4RTCore0AXISILockstepComparator0Err
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain16/CddEmmBit4RTCore0AXISILockstepComparator0Err
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain16/CddEmmBit4RTCore0AXISILockstepComparator0Err/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain16/CddEmmBit4RTCore0AXISILockstepComparator0Err/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit5RTCore0InstructionCacheErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain16/CddEmmBit5RTCore0InstructionCacheErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain16/CddEmmBit5RTCore0InstructionCacheErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain16/CddEmmBit5RTCore0InstructionCacheErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit6RTCore0DataCacheErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain16/CddEmmBit6RTCore0DataCacheErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain16/CddEmmBit6RTCore0DataCacheErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain16/CddEmmBit6RTCore0DataCacheErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit7RTCore0AXISILockstepComparator1Err
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain16/CddEmmBit7RTCore0AXISILockstepComparator1Err
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain16/CddEmmBit7RTCore0AXISILockstepComparator1Err/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain16/CddEmmBit7RTCore0AXISILockstepComparator1Err/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit8RTCore0AXIMIDECERRSLVERRBusErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain16/CddEmmBit8RTCore0AXIMIDECERRSLVERRBusErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain16/CddEmmBit8RTCore0AXIMIDECERRSLVERRBusErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain16/CddEmmBit8RTCore0AXIMIDECERRSLVERRBusErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit9RTCore0AXISIFatalErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain16/CddEmmBit9RTCore0AXISIFatalErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain16/CddEmmBit9RTCore0AXISIFatalErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain16/CddEmmBit9RTCore0AXISIFatalErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit10RTCore0AXISICorrectableErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain16/CddEmmBit10RTCore0AXISICorrectableErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain16/CddEmmBit10RTCore0AXISICorrectableErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain16/CddEmmBit10RTCore0AXISICorrectableErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit11RTCore0AXIMIFatalErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain16/CddEmmBit11RTCore0AXIMIFatalErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain16/CddEmmBit11RTCore0AXIMIFatalErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain16/CddEmmBit11RTCore0AXIMIFatalErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit12RTCore0AXIMICorrectableErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain16/CddEmmBit12RTCore0AXIMICorrectableErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain16/CddEmmBit12RTCore0AXIMICorrectableErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain16/CddEmmBit12RTCore0AXIMICorrectableErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit13RTCore0NonSafetySwitchingComparator0Err
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain16/CddEmmBit13RTCore0NonSafetySwitchingComparator0Err
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain16/CddEmmBit13RTCore0NonSafetySwitchingComparator0Err/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain16/CddEmmBit13RTCore0NonSafetySwitchingComparator0Err/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit14THSTsc4TempExceedsThreshold3
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain16/CddEmmBit14THSTsc4TempExceedsThreshold3
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain16/CddEmmBit14THSTsc4TempExceedsThreshold3/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain16/CddEmmBit14THSTsc4TempExceedsThreshold3/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit15THSTsc4TempExceedsThreshold2
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain16/CddEmmBit15THSTsc4TempExceedsThreshold2
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain16/CddEmmBit15THSTsc4TempExceedsThreshold2/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain16/CddEmmBit15THSTsc4TempExceedsThreshold2/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit16THSTsc4TempExceedsThreshold1
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain16/CddEmmBit16THSTsc4TempExceedsThreshold1
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain16/CddEmmBit16THSTsc4TempExceedsThreshold1/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain16/CddEmmBit16THSTsc4TempExceedsThreshold1/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit17THSTsc3TempExceedsThreshold3
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain16/CddEmmBit17THSTsc3TempExceedsThreshold3
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain16/CddEmmBit17THSTsc3TempExceedsThreshold3/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain16/CddEmmBit17THSTsc3TempExceedsThreshold3/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit18THSTsc3TempExceedsThreshold2
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain16/CddEmmBit18THSTsc3TempExceedsThreshold2
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain16/CddEmmBit18THSTsc3TempExceedsThreshold2/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain16/CddEmmBit18THSTsc3TempExceedsThreshold2/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit19THSTsc3TempExceedsThreshold1
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain16/CddEmmBit19THSTsc3TempExceedsThreshold1
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain16/CddEmmBit19THSTsc3TempExceedsThreshold1/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain16/CddEmmBit19THSTsc3TempExceedsThreshold1/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit20THSTsc2TempExceedsThreshold3
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain16/CddEmmBit20THSTsc2TempExceedsThreshold3
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain16/CddEmmBit20THSTsc2TempExceedsThreshold3/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain16/CddEmmBit20THSTsc2TempExceedsThreshold3/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit21THSTsc2TempExceedsThreshold2
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain16/CddEmmBit21THSTsc2TempExceedsThreshold2
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain16/CddEmmBit21THSTsc2TempExceedsThreshold2/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain16/CddEmmBit21THSTsc2TempExceedsThreshold2/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit22THSTsc2TempExceedsThreshold1
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain16/CddEmmBit22THSTsc2TempExceedsThreshold1
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain16/CddEmmBit22THSTsc2TempExceedsThreshold1/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain16/CddEmmBit22THSTsc2TempExceedsThreshold1/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit23THSTsc1TempExceedsThreshold3
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain16/CddEmmBit23THSTsc1TempExceedsThreshold3
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain16/CddEmmBit23THSTsc1TempExceedsThreshold3/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain16/CddEmmBit23THSTsc1TempExceedsThreshold3/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit24THSTsc1TempExceedsThreshold2
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain16/CddEmmBit24THSTsc1TempExceedsThreshold2
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain16/CddEmmBit24THSTsc1TempExceedsThreshold2/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain16/CddEmmBit24THSTsc1TempExceedsThreshold2/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit25THSTsc1TempExceedsThreshold1
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain16/CddEmmBit25THSTsc1TempExceedsThreshold1
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain16/CddEmmBit25THSTsc1TempExceedsThreshold1/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain16/CddEmmBit25THSTsc1TempExceedsThreshold1/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit26THSTsc4DetectsFailure
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain16/CddEmmBit26THSTsc4DetectsFailure
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain16/CddEmmBit26THSTsc4DetectsFailure/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain16/CddEmmBit26THSTsc4DetectsFailure/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit27THSTsc3DetectsFailure
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain16/CddEmmBit27THSTsc3DetectsFailure
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain16/CddEmmBit27THSTsc3DetectsFailure/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain16/CddEmmBit27THSTsc3DetectsFailure/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit28THSTsc2DetectsFailure
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain16/CddEmmBit28THSTsc2DetectsFailure
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain16/CddEmmBit28THSTsc2DetectsFailure/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain16/CddEmmBit28THSTsc2DetectsFailure/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit29THSTsc1DetectsFailure
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain16/CddEmmBit29THSTsc1DetectsFailure
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain16/CddEmmBit29THSTsc1DetectsFailure/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain16/CddEmmBit29THSTsc1DetectsFailure/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+
+
+ CddEmmDomain17
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain17
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain17/CddEmmAddressToSaveErrorStatus
+ 1342177348
+
+
+
+
+ CddEmmBit5RTCore0NonSafetySwitchingComparator1Err
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain17/CddEmmBit5RTCore0NonSafetySwitchingComparator1Err
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain17/CddEmmBit5RTCore0NonSafetySwitchingComparator1Err/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain17/CddEmmBit5RTCore0NonSafetySwitchingComparator1Err/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit6RTCore0AsynchronousTransferErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain17/CddEmmBit6RTCore0AsynchronousTransferErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain17/CddEmmBit6RTCore0AsynchronousTransferErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain17/CddEmmBit6RTCore0AsynchronousTransferErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit7RTCore0IllegalAxSIZEAxBURSTErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain17/CddEmmBit7RTCore0IllegalAxSIZEAxBURSTErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain17/CddEmmBit7RTCore0IllegalAxSIZEAxBURSTErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain17/CddEmmBit7RTCore0IllegalAxSIZEAxBURSTErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit10RTCore0FatalErrCannotRecorded
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain17/CddEmmBit10RTCore0FatalErrCannotRecorded
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain17/CddEmmBit10RTCore0FatalErrCannotRecorded/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain17/CddEmmBit10RTCore0FatalErrCannotRecorded/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit11RTCore0CorrectableNotRecordedErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain17/CddEmmBit11RTCore0CorrectableNotRecordedErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain17/CddEmmBit11RTCore0CorrectableNotRecordedErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain17/CddEmmBit11RTCore0CorrectableNotRecordedErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit15RTVRAM0CRCErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain17/CddEmmBit15RTVRAM0CRCErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain17/CddEmmBit15RTVRAM0CRCErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain17/CddEmmBit15RTVRAM0CRCErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit16RTVRAM0CheckerCoreComparitionErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain17/CddEmmBit16RTVRAM0CheckerCoreComparitionErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain17/CddEmmBit16RTVRAM0CheckerCoreComparitionErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain17/CddEmmBit16RTVRAM0CheckerCoreComparitionErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit17RTVRAM1CheckerCoreComparitionErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain17/CddEmmBit17RTVRAM1CheckerCoreComparitionErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain17/CddEmmBit17RTVRAM1CheckerCoreComparitionErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain17/CddEmmBit17RTVRAM1CheckerCoreComparitionErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit18RTVRAM1EdcMultibitErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain17/CddEmmBit18RTVRAM1EdcMultibitErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain17/CddEmmBit18RTVRAM1EdcMultibitErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain17/CddEmmBit18RTVRAM1EdcMultibitErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit19RTVRAM1Edc1bitErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain17/CddEmmBit19RTVRAM1Edc1bitErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain17/CddEmmBit19RTVRAM1Edc1bitErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain17/CddEmmBit19RTVRAM1Edc1bitErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit20RTVRAM1CRCErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain17/CddEmmBit20RTVRAM1CRCErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain17/CddEmmBit20RTVRAM1CRCErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain17/CddEmmBit20RTVRAM1CRCErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit21RTVRAM1SafetyAccessProtectionErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain17/CddEmmBit21RTVRAM1SafetyAccessProtectionErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain17/CddEmmBit21RTVRAM1SafetyAccessProtectionErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain17/CddEmmBit21RTVRAM1SafetyAccessProtectionErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit22RTVRAM1SecureAccessProtectionErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain17/CddEmmBit22RTVRAM1SecureAccessProtectionErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain17/CddEmmBit22RTVRAM1SecureAccessProtectionErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain17/CddEmmBit22RTVRAM1SecureAccessProtectionErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit23RTVRAM1TimeOutErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain17/CddEmmBit23RTVRAM1TimeOutErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain17/CddEmmBit23RTVRAM1TimeOutErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain17/CddEmmBit23RTVRAM1TimeOutErr/CddEmmErrorSignalTarget
+ INTC
+
+
+
+
+ CddEmmBit24FCPRCInternaSRAMEdcErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain17/CddEmmBit24FCPRCInternaSRAMEdcErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain17/CddEmmBit24FCPRCInternaSRAMEdcErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain17/CddEmmBit24FCPRCInternaSRAMEdcErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit25FCPRCDCLSErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain17/CddEmmBit25FCPRCDCLSErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain17/CddEmmBit25FCPRCDCLSErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain17/CddEmmBit25FCPRCDCLSErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit26FCPRSInternalSRAMEdcErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain17/CddEmmBit26FCPRSInternalSRAMEdcErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain17/CddEmmBit26FCPRSInternalSRAMEdcErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain17/CddEmmBit26FCPRSInternalSRAMEdcErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit27FCPRSDCLSErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain17/CddEmmBit27FCPRSDCLSErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain17/CddEmmBit27FCPRSDCLSErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain17/CddEmmBit27FCPRSDCLSErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit29VIPFCPRMInternalSRAMEdcErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain17/CddEmmBit29VIPFCPRMInternalSRAMEdcErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain17/CddEmmBit29VIPFCPRMInternalSRAMEdcErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain17/CddEmmBit29VIPFCPRMInternalSRAMEdcErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+
+
+ CddEmmDomain18
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain18
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain18/CddEmmAddressToSaveErrorStatus
+ 1342177352
+
+
+
+
+ CddEmmBit0RFSOCFE0ErrCh8
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain18/CddEmmBit0RFSOCFE0ErrCh8
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain18/CddEmmBit0RFSOCFE0ErrCh8/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain18/CddEmmBit0RFSOCFE0ErrCh8/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit1RFSOCFE0ErrCh9
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain18/CddEmmBit1RFSOCFE0ErrCh9
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain18/CddEmmBit1RFSOCFE0ErrCh9/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain18/CddEmmBit1RFSOCFE0ErrCh9/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit2RFSOCFE0ErrCh10
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain18/CddEmmBit2RFSOCFE0ErrCh10
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain18/CddEmmBit2RFSOCFE0ErrCh10/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain18/CddEmmBit2RFSOCFE0ErrCh10/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit3RFSOCFE1ErrCh8
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain18/CddEmmBit3RFSOCFE1ErrCh8
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain18/CddEmmBit3RFSOCFE1ErrCh8/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain18/CddEmmBit3RFSOCFE1ErrCh8/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit4RFSOCFE1ErrCh9
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain18/CddEmmBit4RFSOCFE1ErrCh9
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain18/CddEmmBit4RFSOCFE1ErrCh9/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain18/CddEmmBit4RFSOCFE1ErrCh9/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit5RFSOCFE1ErrCh10
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain18/CddEmmBit5RFSOCFE1ErrCh10
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain18/CddEmmBit5RFSOCFE1ErrCh10/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain18/CddEmmBit5RFSOCFE1ErrCh10/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit6RFSOTOEErrCh8
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain18/CddEmmBit6RFSOTOEErrCh8
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain18/CddEmmBit6RFSOTOEErrCh8/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain18/CddEmmBit6RFSOTOEErrCh8/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit7RFSOTOEErrCh9
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain18/CddEmmBit7RFSOTOEErrCh9
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain18/CddEmmBit7RFSOTOEErrCh9/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain18/CddEmmBit7RFSOTOEErrCh9/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit8RFSOTOEErrCh10
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain18/CddEmmBit8RFSOTOEErrCh10
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain18/CddEmmBit8RFSOTOEErrCh10/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain18/CddEmmBit8RFSOTOEErrCh10/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit9APMUCortexR52Core2ResetControlErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain18/CddEmmBit9APMUCortexR52Core2ResetControlErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain18/CddEmmBit9APMUCortexR52Core2ResetControlErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain18/CddEmmBit9APMUCortexR52Core2ResetControlErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit10APMUCortexR52Core1ResetControlErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain18/CddEmmBit10APMUCortexR52Core1ResetControlErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain18/CddEmmBit10APMUCortexR52Core1ResetControlErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain18/CddEmmBit10APMUCortexR52Core1ResetControlErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit11APMUCA76Cl1PowerControlErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain18/CddEmmBit11APMUCA76Cl1PowerControlErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain18/CddEmmBit11APMUCA76Cl1PowerControlErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain18/CddEmmBit11APMUCA76Cl1PowerControlErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit12APMUCA76Cl0PowerControlErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain18/CddEmmBit12APMUCA76Cl0PowerControlErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain18/CddEmmBit12APMUCA76Cl0PowerControlErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain18/CddEmmBit12APMUCA76Cl0PowerControlErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit13iVCP1EInternalSRAMEdcErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain18/CddEmmBit13iVCP1EInternalSRAMEdcErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain18/CddEmmBit13iVCP1EInternalSRAMEdcErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain18/CddEmmBit13iVCP1EInternalSRAMEdcErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit18ISPChSelectorErrCh1
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain18/CddEmmBit18ISPChSelectorErrCh1
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain18/CddEmmBit18ISPChSelectorErrCh1/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain18/CddEmmBit18ISPChSelectorErrCh1/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit19ISPCoreErrCh1
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain18/CddEmmBit19ISPCoreErrCh1
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain18/CddEmmBit19ISPCoreErrCh1/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain18/CddEmmBit19ISPCoreErrCh1/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit20ISPChSelectorErrCh0
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain18/CddEmmBit20ISPChSelectorErrCh0
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain18/CddEmmBit20ISPChSelectorErrCh0/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain18/CddEmmBit20ISPChSelectorErrCh0/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit21ISPCoreErrCh0
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain18/CddEmmBit21ISPCoreErrCh0
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain18/CddEmmBit21ISPCoreErrCh0/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain18/CddEmmBit21ISPCoreErrCh0/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit22IMRLX6Ch1EcmErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain18/CddEmmBit22IMRLX6Ch1EcmErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain18/CddEmmBit22IMRLX6Ch1EcmErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain18/CddEmmBit22IMRLX6Ch1EcmErr/CddEmmErrorSignalTarget
+ INTC
+
+
+
+
+ CddEmmBit23IMRLX6Ch0EcmErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain18/CddEmmBit23IMRLX6Ch0EcmErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain18/CddEmmBit23IMRLX6Ch0EcmErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain18/CddEmmBit23IMRLX6Ch0EcmErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit25IMRLX6Ch4EcmErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain18/CddEmmBit25IMRLX6Ch4EcmErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain18/CddEmmBit25IMRLX6Ch4EcmErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain18/CddEmmBit25IMRLX6Ch4EcmErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit26IMRLX6Ch3EcmErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain18/CddEmmBit26IMRLX6Ch3EcmErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain18/CddEmmBit26IMRLX6Ch3EcmErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain18/CddEmmBit26IMRLX6Ch3EcmErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit27IMRLX6Ch2EcmErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain18/CddEmmBit27IMRLX6Ch2EcmErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain18/CddEmmBit27IMRLX6Ch2EcmErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain18/CddEmmBit27IMRLX6Ch2EcmErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+
+
+ CddEmmDomain19
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain19
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain19/CddEmmAddressToSaveErrorStatus
+ 1342177356
+
+
+
+
+ CddEmmBit0DMAC2SYSSecurityAccessErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain19/CddEmmBit0DMAC2SYSSecurityAccessErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain19/CddEmmBit0DMAC2SYSSecurityAccessErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain19/CddEmmBit0DMAC2SYSSecurityAccessErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit3APSysCciSFRAMAddrFeedbackComparatorErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain19/CddEmmBit3APSysCciSFRAMAddrFeedbackComparatorErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain19/CddEmmBit3APSysCciSFRAMAddrFeedbackComparatorErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain19/CddEmmBit3APSysCciSFRAMAddrFeedbackComparatorErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit4DBSC5DFIDomaindclsECMErrDbs0
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain19/CddEmmBit4DBSC5DFIDomaindclsECMErrDbs0
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain19/CddEmmBit4DBSC5DFIDomaindclsECMErrDbs0/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain19/CddEmmBit4DBSC5DFIDomaindclsECMErrDbs0/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit5DBSC5AXIDomaindclsECMrrDbs0
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain19/CddEmmBit5DBSC5AXIDomaindclsECMrrDbs0
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain19/CddEmmBit5DBSC5AXIDomaindclsECMrrDbs0/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain19/CddEmmBit5DBSC5AXIDomaindclsECMrrDbs0/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit6DBSC5DFIDomaindclsECMErrDbs1
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain19/CddEmmBit6DBSC5DFIDomaindclsECMErrDbs1
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain19/CddEmmBit6DBSC5DFIDomaindclsECMErrDbs1/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain19/CddEmmBit6DBSC5DFIDomaindclsECMErrDbs1/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit7DBSC5AXIDomaindclsECMErrDbs1
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain19/CddEmmBit7DBSC5AXIDomaindclsECMErrDbs1
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain19/CddEmmBit7DBSC5AXIDomaindclsECMErrDbs1/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain19/CddEmmBit7DBSC5AXIDomaindclsECMErrDbs1/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit8RFSOCFE1ErrCh0
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain19/CddEmmBit8RFSOCFE1ErrCh0
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain19/CddEmmBit8RFSOCFE1ErrCh0/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain19/CddEmmBit8RFSOCFE1ErrCh0/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit9RFSOCFE1ErrCh1
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain19/CddEmmBit9RFSOCFE1ErrCh1
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain19/CddEmmBit9RFSOCFE1ErrCh1/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain19/CddEmmBit9RFSOCFE1ErrCh1/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit10RFSOCFE1ErrCh2
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain19/CddEmmBit10RFSOCFE1ErrCh2
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain19/CddEmmBit10RFSOCFE1ErrCh2/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain19/CddEmmBit10RFSOCFE1ErrCh2/CddEmmErrorSignalTarget
+ INTC
+
+
+
+
+ CddEmmBit11RFSOCFE1ErrCh3
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain19/CddEmmBit11RFSOCFE1ErrCh3
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain19/CddEmmBit11RFSOCFE1ErrCh3/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain19/CddEmmBit11RFSOCFE1ErrCh3/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit12RFSOCFE1ErrCh4
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain19/CddEmmBit12RFSOCFE1ErrCh4
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain19/CddEmmBit12RFSOCFE1ErrCh4/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain19/CddEmmBit12RFSOCFE1ErrCh4/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit13RFSOCFE1ErrCh5
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain19/CddEmmBit13RFSOCFE1ErrCh5
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain19/CddEmmBit13RFSOCFE1ErrCh5/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain19/CddEmmBit13RFSOCFE1ErrCh5/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit14RFSOCFE1ErrCh6
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain19/CddEmmBit14RFSOCFE1ErrCh6
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain19/CddEmmBit14RFSOCFE1ErrCh6/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain19/CddEmmBit14RFSOCFE1ErrCh6/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit15RFSOCFE1ErrCh7
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain19/CddEmmBit15RFSOCFE1ErrCh7
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain19/CddEmmBit15RFSOCFE1ErrCh7/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain19/CddEmmBit15RFSOCFE1ErrCh7/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit16RFSOCFE0ErrCh0
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain19/CddEmmBit16RFSOCFE0ErrCh0
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain19/CddEmmBit16RFSOCFE0ErrCh0/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain19/CddEmmBit16RFSOCFE0ErrCh0/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit17RFSOCFE0ErrCh1
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain19/CddEmmBit17RFSOCFE0ErrCh1
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain19/CddEmmBit17RFSOCFE0ErrCh1/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain19/CddEmmBit17RFSOCFE0ErrCh1/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit18RFSOCFE0ErrCh2
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain19/CddEmmBit18RFSOCFE0ErrCh2
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain19/CddEmmBit18RFSOCFE0ErrCh2/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain19/CddEmmBit18RFSOCFE0ErrCh2/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit19RFSOCFE0ErrCh3
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain19/CddEmmBit19RFSOCFE0ErrCh3
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain19/CddEmmBit19RFSOCFE0ErrCh3/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain19/CddEmmBit19RFSOCFE0ErrCh3/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit20RFSOCFE0ErrCh4
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain19/CddEmmBit20RFSOCFE0ErrCh4
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain19/CddEmmBit20RFSOCFE0ErrCh4/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain19/CddEmmBit20RFSOCFE0ErrCh4/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit21RFSOCFE0ErrCh5
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain19/CddEmmBit21RFSOCFE0ErrCh5
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain19/CddEmmBit21RFSOCFE0ErrCh5/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain19/CddEmmBit21RFSOCFE0ErrCh5/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit22RFSOCFE0ErrCh6
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain19/CddEmmBit22RFSOCFE0ErrCh6
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain19/CddEmmBit22RFSOCFE0ErrCh6/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain19/CddEmmBit22RFSOCFE0ErrCh6/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit23RFSOCFE0ErrCh7
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain19/CddEmmBit23RFSOCFE0ErrCh7
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain19/CddEmmBit23RFSOCFE0ErrCh7/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain19/CddEmmBit23RFSOCFE0ErrCh7/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit24RFSOTOEErrCh0
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain19/CddEmmBit24RFSOTOEErrCh0
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain19/CddEmmBit24RFSOTOEErrCh0/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain19/CddEmmBit24RFSOTOEErrCh0/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit25RFSOTOEErrCh1
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain19/CddEmmBit25RFSOTOEErrCh1
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain19/CddEmmBit25RFSOTOEErrCh1/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain19/CddEmmBit25RFSOTOEErrCh1/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit26RFSOTOEErrCh2
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain19/CddEmmBit26RFSOTOEErrCh2
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain19/CddEmmBit26RFSOTOEErrCh2/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain19/CddEmmBit26RFSOTOEErrCh2/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit27RFSOTOEErrCh3
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain19/CddEmmBit27RFSOTOEErrCh3
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain19/CddEmmBit27RFSOTOEErrCh3/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain19/CddEmmBit27RFSOTOEErrCh3/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit28RFSOTOEErrCh4
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain19/CddEmmBit28RFSOTOEErrCh4
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain19/CddEmmBit28RFSOTOEErrCh4/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain19/CddEmmBit28RFSOTOEErrCh4/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit29RFSOTOEErrCh5
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain19/CddEmmBit29RFSOTOEErrCh5
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain19/CddEmmBit29RFSOTOEErrCh5/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain19/CddEmmBit29RFSOTOEErrCh5/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit30RFSOTOEErrCh6
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain19/CddEmmBit30RFSOTOEErrCh6
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain19/CddEmmBit30RFSOTOEErrCh6/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain19/CddEmmBit30RFSOTOEErrCh6/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit31RFSOTOEErrCh7
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain19/CddEmmBit31RFSOTOEErrCh7
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain19/CddEmmBit31RFSOTOEErrCh7/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain19/CddEmmBit31RFSOTOEErrCh7/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+
+
+ CddEmmDomain20
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain20
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain20/CddEmmAddressToSaveErrorStatus
+ 1342177360
+
+
+
+
+ CddEmmBit1IPMMUirCoreComparitionErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain20/CddEmmBit1IPMMUirCoreComparitionErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain20/CddEmmBit1IPMMUirCoreComparitionErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain20/CddEmmBit1IPMMUirCoreComparitionErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit2IPMMUrt0CoreComparitionErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain20/CddEmmBit2IPMMUrt0CoreComparitionErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain20/CddEmmBit2IPMMUrt0CoreComparitionErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain20/CddEmmBit2IPMMUrt0CoreComparitionErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit3IPMMUmmoreComparitionErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain20/CddEmmBit3IPMMUmmoreComparitionErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain20/CddEmmBit3IPMMUmmoreComparitionErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain20/CddEmmBit3IPMMUmmoreComparitionErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit4IPMMUds0CoreComparitionErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain20/CddEmmBit4IPMMUds0CoreComparitionErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain20/CddEmmBit4IPMMUds0CoreComparitionErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain20/CddEmmBit4IPMMUds0CoreComparitionErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit5DMAC0RTFusaDCLSComparisonErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain20/CddEmmBit5DMAC0RTFusaDCLSComparisonErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain20/CddEmmBit5DMAC0RTFusaDCLSComparisonErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain20/CddEmmBit5DMAC0RTFusaDCLSComparisonErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit6DMAC0RTSecurityAccessErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain20/CddEmmBit6DMAC0RTSecurityAccessErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain20/CddEmmBit6DMAC0RTSecurityAccessErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain20/CddEmmBit6DMAC0RTSecurityAccessErr/CddEmmErrorSignalTarget
+ INTC
+
+
+
+
+ CddEmmBit9DMAC1RTFusaDCLSComparisonErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain20/CddEmmBit9DMAC1RTFusaDCLSComparisonErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain20/CddEmmBit9DMAC1RTFusaDCLSComparisonErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain20/CddEmmBit9DMAC1RTFusaDCLSComparisonErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit10DMAC1RTSecurityAccessErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain20/CddEmmBit10DMAC1RTSecurityAccessErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain20/CddEmmBit10DMAC1RTSecurityAccessErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain20/CddEmmBit10DMAC1RTSecurityAccessErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit13DMAC2RTFusaDCLSComparisonErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain20/CddEmmBit13DMAC2RTFusaDCLSComparisonErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain20/CddEmmBit13DMAC2RTFusaDCLSComparisonErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain20/CddEmmBit13DMAC2RTFusaDCLSComparisonErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit14DMAC2RTSecurityAccessErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain20/CddEmmBit14DMAC2RTSecurityAccessErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain20/CddEmmBit14DMAC2RTSecurityAccessErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain20/CddEmmBit14DMAC2RTSecurityAccessErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit17DMAC3RTFusaDCLSComparisonErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain20/CddEmmBit17DMAC3RTFusaDCLSComparisonErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain20/CddEmmBit17DMAC3RTFusaDCLSComparisonErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain20/CddEmmBit17DMAC3RTFusaDCLSComparisonErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit18DMAC3RTSecurityAccessErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain20/CddEmmBit18DMAC3RTSecurityAccessErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain20/CddEmmBit18DMAC3RTSecurityAccessErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain20/CddEmmBit18DMAC3RTSecurityAccessErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit21DMAC1SYSFusaDCLSComparisonErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain20/CddEmmBit21DMAC1SYSFusaDCLSComparisonErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain20/CddEmmBit21DMAC1SYSFusaDCLSComparisonErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain20/CddEmmBit21DMAC1SYSFusaDCLSComparisonErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit22DMAC1SYSSecurityAccessErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain20/CddEmmBit22DMAC1SYSSecurityAccessErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain20/CddEmmBit22DMAC1SYSSecurityAccessErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain20/CddEmmBit22DMAC1SYSSecurityAccessErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit25DMAC2SYSFusaDCLSComparisonErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain20/CddEmmBit25DMAC2SYSFusaDCLSComparisonErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain20/CddEmmBit25DMAC2SYSFusaDCLSComparisonErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain20/CddEmmBit25DMAC2SYSFusaDCLSComparisonErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit26RTCore0LongHypervisorInterruptErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain20/CddEmmBit26RTCore0LongHypervisorInterruptErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain20/CddEmmBit26RTCore0LongHypervisorInterruptErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain20/CddEmmBit26RTCore0LongHypervisorInterruptErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit27RTCore0HypervisorModeFatalErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain20/CddEmmBit27RTCore0HypervisorModeFatalErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain20/CddEmmBit27RTCore0HypervisorModeFatalErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain20/CddEmmBit27RTCore0HypervisorModeFatalErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit28RTCore0EL2ControlledabortExceptionErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain20/CddEmmBit28RTCore0EL2ControlledabortExceptionErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain20/CddEmmBit28RTCore0EL2ControlledabortExceptionErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain20/CddEmmBit28RTCore0EL2ControlledabortExceptionErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit29RTCore0EL1ControlledAbortExceptionErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain20/CddEmmBit29RTCore0EL1ControlledAbortExceptionErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain20/CddEmmBit29RTCore0EL1ControlledAbortExceptionErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain20/CddEmmBit29RTCore0EL1ControlledAbortExceptionErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit30RTCore0UndefinedExceptionErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain20/CddEmmBit30RTCore0UndefinedExceptionErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain20/CddEmmBit30RTCore0UndefinedExceptionErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain20/CddEmmBit30RTCore0UndefinedExceptionErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit31RTCore0AXIMITimeoutErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain20/CddEmmBit31RTCore0AXIMITimeoutErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain20/CddEmmBit31RTCore0AXIMITimeoutErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain20/CddEmmBit31RTCore0AXIMITimeoutErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+
+
+ CddEmmDomain21
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain21
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain21/CddEmmAddressToSaveErrorStatus
+ 1342177364
+
+
+
+
+ CddEmmBit0CPGPLLCBFUSAFreqErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain21/CddEmmBit0CPGPLLCBFUSAFreqErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain21/CddEmmBit0CPGPLLCBFUSAFreqErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain21/CddEmmBit0CPGPLLCBFUSAFreqErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit1CPGSlAccessBusFreqErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain21/CddEmmBit1CPGSlAccessBusFreqErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain21/CddEmmBit1CPGSlAccessBusFreqErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain21/CddEmmBit1CPGSlAccessBusFreqErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit2CPGRTckmcr52FreqErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain21/CddEmmBit2CPGRTckmcr52FreqErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain21/CddEmmBit2CPGRTckmcr52FreqErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain21/CddEmmBit2CPGRTckmcr52FreqErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit3CPGHSCFreqErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain21/CddEmmBit3CPGHSCFreqErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain21/CddEmmBit3CPGHSCFreqErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain21/CddEmmBit3CPGHSCFreqErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit9CPGMMFreqErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain21/CddEmmBit9CPGMMFreqErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain21/CddEmmBit9CPGMMFreqErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain21/CddEmmBit9CPGMMFreqErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit10CPGIMPFreqErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain21/CddEmmBit10CPGIMPFreqErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain21/CddEmmBit10CPGIMPFreqErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain21/CddEmmBit10CPGIMPFreqErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit11CPGVipFreqErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain21/CddEmmBit11CPGVipFreqErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain21/CddEmmBit11CPGVipFreqErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain21/CddEmmBit11CPGVipFreqErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit12CPGVcFreqErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain21/CddEmmBit12CPGVcFreqErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain21/CddEmmBit12CPGVcFreqErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain21/CddEmmBit12CPGVcFreqErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit13CPGVioFreqErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain21/CddEmmBit13CPGVioFreqErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain21/CddEmmBit13CPGVioFreqErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain21/CddEmmBit13CPGVioFreqErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit15CPGPeripheralFreqErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain21/CddEmmBit15CPGPeripheralFreqErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain21/CddEmmBit15CPGPeripheralFreqErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain21/CddEmmBit15CPGPeripheralFreqErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit16CPGRTckmrtFreqErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain21/CddEmmBit16CPGRTckmrtFreqErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain21/CddEmmBit16CPGRTckmrtFreqErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain21/CddEmmBit16CPGRTckmrtFreqErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit17CPGGsxFreqErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain21/CddEmmBit17CPGGsxFreqErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain21/CddEmmBit17CPGGsxFreqErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain21/CddEmmBit17CPGGsxFreqErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit21IPMMUmmTLBRAMEcc1bitlErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain21/CddEmmBit21IPMMUmmTLBRAMEcc1bitlErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain21/CddEmmBit21IPMMUmmTLBRAMEcc1bitlErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain21/CddEmmBit21IPMMUmmTLBRAMEcc1bitlErr/CddEmmErrorSignalTarget
+ INTC
+
+
+
+
+ CddEmmBit22IPMMUmmTLBRAMEccMultibitErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain21/CddEmmBit22IPMMUmmTLBRAMEccMultibitErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain21/CddEmmBit22IPMMUmmTLBRAMEccMultibitErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain21/CddEmmBit22IPMMUmmTLBRAMEccMultibitErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit23IPMMUvip1CoreComparitionErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain21/CddEmmBit23IPMMUvip1CoreComparitionErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain21/CddEmmBit23IPMMUvip1CoreComparitionErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain21/CddEmmBit23IPMMUvip1CoreComparitionErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit24IPMMUvip0CoreComparitionErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain21/CddEmmBit24IPMMUvip0CoreComparitionErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain21/CddEmmBit24IPMMUvip0CoreComparitionErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain21/CddEmmBit24IPMMUvip0CoreComparitionErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit25IPMMUvi1CoreComparitionErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain21/CddEmmBit25IPMMUvi1CoreComparitionErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain21/CddEmmBit25IPMMUvi1CoreComparitionErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain21/CddEmmBit25IPMMUvi1CoreComparitionErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit26IPMMUvi0CoreComparitionErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain21/CddEmmBit26IPMMUvi0CoreComparitionErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain21/CddEmmBit26IPMMUvi0CoreComparitionErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain21/CddEmmBit26IPMMUvi0CoreComparitionErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit27IPMMUvcCoreComparitionErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain21/CddEmmBit27IPMMUvcCoreComparitionErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain21/CddEmmBit27IPMMUvcCoreComparitionErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain21/CddEmmBit27IPMMUvcCoreComparitionErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit28IPMMUrt1CoreComparitionErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain21/CddEmmBit28IPMMUrt1CoreComparitionErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain21/CddEmmBit28IPMMUrt1CoreComparitionErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain21/CddEmmBit28IPMMUrt1CoreComparitionErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit29IPMMU3dgCoreComparitionErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain21/CddEmmBit29IPMMU3dgCoreComparitionErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain21/CddEmmBit29IPMMU3dgCoreComparitionErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain21/CddEmmBit29IPMMU3dgCoreComparitionErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit31IPMMUhcCoreComparitionErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain21/CddEmmBit31IPMMUhcCoreComparitionErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain21/CddEmmBit31IPMMUhcCoreComparitionErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain21/CddEmmBit31IPMMUhcCoreComparitionErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+
+
+ CddEmmDomain22
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain22
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain22/CddEmmAddressToSaveErrorStatus
+ 1342177368
+
+
+
+
+ CddEmmBit28ICUMXclockmonitorErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain22/CddEmmBit28ICUMXclockmonitorErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain22/CddEmmBit28ICUMXclockmonitorErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain22/CddEmmBit28ICUMXclockmonitorErr/CddEmmErrorSignalTarget
+ INTC
+
+
+
+
+
+
+ CddEmmDomain23
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain23
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain23/CddEmmAddressToSaveErrorStatus
+ 1342177376
+
+
+
+
+ CddEmmBit3FSIRHierarchyCnn0TimeoutErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain23/CddEmmBit3FSIRHierarchyCnn0TimeoutErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain23/CddEmmBit3FSIRHierarchyCnn0TimeoutErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain23/CddEmmBit3FSIRHierarchyCnn0TimeoutErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit14FSIRHierarchyDSP0TimeoutErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain23/CddEmmBit14FSIRHierarchyDSP0TimeoutErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain23/CddEmmBit14FSIRHierarchyDSP0TimeoutErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain23/CddEmmBit14FSIRHierarchyDSP0TimeoutErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit15FSIRHierarchyDSP1TimeoutErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain23/CddEmmBit15FSIRHierarchyDSP1TimeoutErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain23/CddEmmBit15FSIRHierarchyDSP1TimeoutErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain23/CddEmmBit15FSIRHierarchyDSP1TimeoutErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit16FSIRHierarchyDSP2TimeoutErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain23/CddEmmBit16FSIRHierarchyDSP2TimeoutErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain23/CddEmmBit16FSIRHierarchyDSP2TimeoutErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain23/CddEmmBit16FSIRHierarchyDSP2TimeoutErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit17FSIRHierarchyDSP3TimeoutErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain23/CddEmmBit17FSIRHierarchyDSP3TimeoutErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain23/CddEmmBit17FSIRHierarchyDSP3TimeoutErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain23/CddEmmBit17FSIRHierarchyDSP3TimeoutErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit20FSIRHierarchyCNRAM0TimeoutErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain23/CddEmmBit20FSIRHierarchyCNRAM0TimeoutErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain23/CddEmmBit20FSIRHierarchyCNRAM0TimeoutErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain23/CddEmmBit20FSIRHierarchyCNRAM0TimeoutErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit21FSIRHierarchySlimdmac0TimeoutErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain23/CddEmmBit21FSIRHierarchySlimdmac0TimeoutErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain23/CddEmmBit21FSIRHierarchySlimdmac0TimeoutErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain23/CddEmmBit21FSIRHierarchySlimdmac0TimeoutErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit22FSIRHierarchySlimdmac1TimeoutErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain23/CddEmmBit22FSIRHierarchySlimdmac1TimeoutErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain23/CddEmmBit22FSIRHierarchySlimdmac1TimeoutErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain23/CddEmmBit22FSIRHierarchySlimdmac1TimeoutErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit23FSIRHierarchyIMPRAM0TimeoutErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain23/CddEmmBit23FSIRHierarchyIMPRAM0TimeoutErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain23/CddEmmBit23FSIRHierarchyIMPRAM0TimeoutErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain23/CddEmmBit23FSIRHierarchyIMPRAM0TimeoutErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit25FS3DGHierarchyRASCALTimeoutErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain23/CddEmmBit25FS3DGHierarchyRASCALTimeoutErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain23/CddEmmBit25FS3DGHierarchyRASCALTimeoutErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain23/CddEmmBit25FS3DGHierarchyRASCALTimeoutErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit26FS3DGHierarchyDUSTATimeoutErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain23/CddEmmBit26FS3DGHierarchyDUSTATimeoutErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain23/CddEmmBit26FS3DGHierarchyDUSTATimeoutErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain23/CddEmmBit26FS3DGHierarchyDUSTATimeoutErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit27FS3DGHierarchySLCSIDEKICKTimeoutErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain23/CddEmmBit27FS3DGHierarchySLCSIDEKICKTimeoutErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain23/CddEmmBit27FS3DGHierarchySLCSIDEKICKTimeoutErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain23/CddEmmBit27FS3DGHierarchySLCSIDEKICKTimeoutErr/CddEmmErrorSignalTarget
+ INTC
+
+
+
+
+ CddEmmBit28FS3DGHierarchyexceptRGXcoreTimeoutErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain23/CddEmmBit28FS3DGHierarchyexceptRGXcoreTimeoutErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain23/CddEmmBit28FS3DGHierarchyexceptRGXcoreTimeoutErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain23/CddEmmBit28FS3DGHierarchyexceptRGXcoreTimeoutErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit29FS3DGHierarchyXonstTimeoutErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain23/CddEmmBit29FS3DGHierarchyXonstTimeoutErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain23/CddEmmBit29FS3DGHierarchyXonstTimeoutErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain23/CddEmmBit29FS3DGHierarchyXonstTimeoutErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit30FSMMHierarchyDDRTimeoutErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain23/CddEmmBit30FSMMHierarchyDDRTimeoutErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain23/CddEmmBit30FSMMHierarchyDDRTimeoutErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain23/CddEmmBit30FSMMHierarchyDDRTimeoutErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+
+
+ CddEmmDomain24
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain24
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain24/CddEmmAddressToSaveErrorStatus
+ 1342177380
+
+
+
+
+ CddEmmBit0FSVCHierarchyIMR1TimeoutErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain24/CddEmmBit0FSVCHierarchyIMR1TimeoutErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain24/CddEmmBit0FSVCHierarchyIMR1TimeoutErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain24/CddEmmBit0FSVCHierarchyIMR1TimeoutErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit1FSVCHierarchyIMR2TimeoutErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain24/CddEmmBit1FSVCHierarchyIMR2TimeoutErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain24/CddEmmBit1FSVCHierarchyIMR2TimeoutErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain24/CddEmmBit1FSVCHierarchyIMR2TimeoutErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit3FSVCHierarchyIMS0TimeoutErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain24/CddEmmBit3FSVCHierarchyIMS0TimeoutErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain24/CddEmmBit3FSVCHierarchyIMS0TimeoutErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain24/CddEmmBit3FSVCHierarchyIMS0TimeoutErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit4FSVCHierarchyIMS1TimeoutErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain24/CddEmmBit4FSVCHierarchyIMS1TimeoutErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain24/CddEmmBit4FSVCHierarchyIMS1TimeoutErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain24/CddEmmBit4FSVCHierarchyIMS1TimeoutErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit6FSVIPHierarchyTimeoutErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain24/CddEmmBit6FSVIPHierarchyTimeoutErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain24/CddEmmBit6FSVIPHierarchyTimeoutErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain24/CddEmmBit6FSVIPHierarchyTimeoutErr/CddEmmErrorSignalTarget
+ INTC
+
+
+
+
+ CddEmmBit7FSVIPHierarchyDULTimeoutErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain24/CddEmmBit7FSVIPHierarchyDULTimeoutErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain24/CddEmmBit7FSVIPHierarchyDULTimeoutErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain24/CddEmmBit7FSVIPHierarchyDULTimeoutErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit9FSVIPHierarchyUMFL0TimeoutErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain24/CddEmmBit9FSVIPHierarchyUMFL0TimeoutErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain24/CddEmmBit9FSVIPHierarchyUMFL0TimeoutErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain24/CddEmmBit9FSVIPHierarchyUMFL0TimeoutErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit11FSVIPHierarchySMPS0TimeoutErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain24/CddEmmBit11FSVIPHierarchySMPS0TimeoutErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain24/CddEmmBit11FSVIPHierarchySMPS0TimeoutErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain24/CddEmmBit11FSVIPHierarchySMPS0TimeoutErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit15FSVIPHierarchySMPO0TimeoutErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain24/CddEmmBit15FSVIPHierarchySMPO0TimeoutErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain24/CddEmmBit15FSVIPHierarchySMPO0TimeoutErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain24/CddEmmBit15FSVIPHierarchySMPO0TimeoutErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit17FSVIPHierarchy2CLE0TimeoutErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain24/CddEmmBit17FSVIPHierarchy2CLE0TimeoutErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain24/CddEmmBit17FSVIPHierarchy2CLE0TimeoutErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain24/CddEmmBit17FSVIPHierarchy2CLE0TimeoutErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit18FSVIPHierarchy2CLE1TimeoutErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain24/CddEmmBit18FSVIPHierarchy2CLE1TimeoutErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain24/CddEmmBit18FSVIPHierarchy2CLE1TimeoutErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain24/CddEmmBit18FSVIPHierarchy2CLE1TimeoutErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit19FSIRHierarchyTimeoutErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain24/CddEmmBit19FSIRHierarchyTimeoutErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain24/CddEmmBit19FSIRHierarchyTimeoutErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain24/CddEmmBit19FSIRHierarchyTimeoutErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit20FSIRHierarchyA3IRBusWrapperTimeoutErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain24/CddEmmBit20FSIRHierarchyA3IRBusWrapperTimeoutErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain24/CddEmmBit20FSIRHierarchyA3IRBusWrapperTimeoutErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain24/CddEmmBit20FSIRHierarchyA3IRBusWrapperTimeoutErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit21FSIRHierarchyIMP0TimeoutErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain24/CddEmmBit21FSIRHierarchyIMP0TimeoutErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain24/CddEmmBit21FSIRHierarchyIMP0TimeoutErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain24/CddEmmBit21FSIRHierarchyIMP0TimeoutErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit22FSIRHierarchyIMP1TimeoutErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain24/CddEmmBit22FSIRHierarchyIMP1TimeoutErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain24/CddEmmBit22FSIRHierarchyIMP1TimeoutErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain24/CddEmmBit22FSIRHierarchyIMP1TimeoutErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit23FSIRHierarchyIMP2TimeoutErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain24/CddEmmBit23FSIRHierarchyIMP2TimeoutErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain24/CddEmmBit23FSIRHierarchyIMP2TimeoutErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain24/CddEmmBit23FSIRHierarchyIMP2TimeoutErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit24FSIRHierarchyIMP3TimeoutErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain24/CddEmmBit24FSIRHierarchyIMP3TimeoutErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain24/CddEmmBit24FSIRHierarchyIMP3TimeoutErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain24/CddEmmBit24FSIRHierarchyIMP3TimeoutErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit25FSIRHierarchyPSC0DMAC0RepeatTimeoutErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain24/CddEmmBit25FSIRHierarchyPSC0DMAC0RepeatTimeoutErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain24/CddEmmBit25FSIRHierarchyPSC0DMAC0RepeatTimeoutErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain24/CddEmmBit25FSIRHierarchyPSC0DMAC0RepeatTimeoutErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit26FSIRHierarchyDMAC2DMAC1RepeatTimeoutErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain24/CddEmmBit26FSIRHierarchyDMAC2DMAC1RepeatTimeoutErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain24/CddEmmBit26FSIRHierarchyDMAC2DMAC1RepeatTimeoutErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain24/CddEmmBit26FSIRHierarchyDMAC2DMAC1RepeatTimeoutErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit27FSIRHierarchyOCV0TimeoutErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain24/CddEmmBit27FSIRHierarchyOCV0TimeoutErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain24/CddEmmBit27FSIRHierarchyOCV0TimeoutErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain24/CddEmmBit27FSIRHierarchyOCV0TimeoutErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit28FSIRHierarchyOCV1TimeoutErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain24/CddEmmBit28FSIRHierarchyOCV1TimeoutErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain24/CddEmmBit28FSIRHierarchyOCV1TimeoutErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain24/CddEmmBit28FSIRHierarchyOCV1TimeoutErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit29FSIRHierarchyOCV2TimeoutErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain24/CddEmmBit29FSIRHierarchyOCV2TimeoutErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain24/CddEmmBit29FSIRHierarchyOCV2TimeoutErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain24/CddEmmBit29FSIRHierarchyOCV2TimeoutErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit30FSIRHierarchyOCV3TimeoutErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain24/CddEmmBit30FSIRHierarchyOCV3TimeoutErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain24/CddEmmBit30FSIRHierarchyOCV3TimeoutErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain24/CddEmmBit30FSIRHierarchyOCV3TimeoutErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+
+
+ CddEmmDomain25
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain25
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain25/CddEmmAddressToSaveErrorStatus
+ 1342177384
+
+
+
+
+ CddEmmBit0FSTOPHierarchyTimeoutErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain25/CddEmmBit0FSTOPHierarchyTimeoutErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain25/CddEmmBit0FSTOPHierarchyTimeoutErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain25/CddEmmBit0FSTOPHierarchyTimeoutErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit1FSMMHierarchyTimeoutErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain25/CddEmmBit1FSMMHierarchyTimeoutErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain25/CddEmmBit1FSMMHierarchyTimeoutErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain25/CddEmmBit1FSMMHierarchyTimeoutErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit2FSMMHierarchyDBSC0TimeoutErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain25/CddEmmBit2FSMMHierarchyDBSC0TimeoutErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain25/CddEmmBit2FSMMHierarchyDBSC0TimeoutErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain25/CddEmmBit2FSMMHierarchyDBSC0TimeoutErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit3FSMMHierarchyDBSC1TimeoutErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain25/CddEmmBit3FSMMHierarchyDBSC1TimeoutErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain25/CddEmmBit3FSMMHierarchyDBSC1TimeoutErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain25/CddEmmBit3FSMMHierarchyDBSC1TimeoutErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit4FSrtCPUHierarchyTimeoutErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain25/CddEmmBit4FSrtCPUHierarchyTimeoutErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain25/CddEmmBit4FSrtCPUHierarchyTimeoutErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain25/CddEmmBit4FSrtCPUHierarchyTimeoutErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit5FSrtCPUHierarchyCR52TimeoutErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain25/CddEmmBit5FSrtCPUHierarchyCR52TimeoutErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain25/CddEmmBit5FSrtCPUHierarchyCR52TimeoutErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain25/CddEmmBit5FSrtCPUHierarchyCR52TimeoutErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit6FSCCIHierarchyTimeoutErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain25/CddEmmBit6FSCCIHierarchyTimeoutErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain25/CddEmmBit6FSCCIHierarchyTimeoutErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain25/CddEmmBit6FSCCIHierarchyTimeoutErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit7FSCPU0HierarchyC4TimeoutErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain25/CddEmmBit7FSCPU0HierarchyC4TimeoutErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain25/CddEmmBit7FSCPU0HierarchyC4TimeoutErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain25/CddEmmBit7FSCPU0HierarchyC4TimeoutErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit8FSCPU0HierarchyA3ETimeoutErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain25/CddEmmBit8FSCPU0HierarchyA3ETimeoutErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain25/CddEmmBit8FSCPU0HierarchyA3ETimeoutErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain25/CddEmmBit8FSCPU0HierarchyA3ETimeoutErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit9FSCPU0HierarchyCl0L3CacheTimeoutErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain25/CddEmmBit9FSCPU0HierarchyCl0L3CacheTimeoutErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain25/CddEmmBit9FSCPU0HierarchyCl0L3CacheTimeoutErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain25/CddEmmBit9FSCPU0HierarchyCl0L3CacheTimeoutErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit10FSCPU0HierarchyCl1L3CacheTimeoutErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain25/CddEmmBit10FSCPU0HierarchyCl1L3CacheTimeoutErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain25/CddEmmBit10FSCPU0HierarchyCl1L3CacheTimeoutErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain25/CddEmmBit10FSCPU0HierarchyCl1L3CacheTimeoutErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit11FSCPU0HierarchyCl0CPU0TimeoutErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain25/CddEmmBit11FSCPU0HierarchyCl0CPU0TimeoutErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain25/CddEmmBit11FSCPU0HierarchyCl0CPU0TimeoutErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain25/CddEmmBit11FSCPU0HierarchyCl0CPU0TimeoutErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit12FSCPU0HierarchyCl0CPU1TimeoutErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain25/CddEmmBit12FSCPU0HierarchyCl0CPU1TimeoutErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain25/CddEmmBit12FSCPU0HierarchyCl0CPU1TimeoutErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain25/CddEmmBit12FSCPU0HierarchyCl0CPU1TimeoutErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit13FSCPU0HierarchyCl1CPU0TimeoutErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain25/CddEmmBit13FSCPU0HierarchyCl1CPU0TimeoutErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain25/CddEmmBit13FSCPU0HierarchyCl1CPU0TimeoutErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain25/CddEmmBit13FSCPU0HierarchyCl1CPU0TimeoutErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit14FSCPU0HierarchyCl1CPU1TimeoutErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain25/CddEmmBit14FSCPU0HierarchyCl1CPU1TimeoutErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain25/CddEmmBit14FSCPU0HierarchyCl1CPU1TimeoutErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain25/CddEmmBit14FSCPU0HierarchyCl1CPU1TimeoutErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit23FSPeripheralDMACHierarchy0TimeoutErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain25/CddEmmBit23FSPeripheralDMACHierarchy0TimeoutErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain25/CddEmmBit23FSPeripheralDMACHierarchy0TimeoutErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain25/CddEmmBit23FSPeripheralDMACHierarchy0TimeoutErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit24FSHSpeedComHierarchyTimeoutErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain25/CddEmmBit24FSHSpeedComHierarchyTimeoutErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain25/CddEmmBit24FSHSpeedComHierarchyTimeoutErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain25/CddEmmBit24FSHSpeedComHierarchyTimeoutErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit25FSVIOHierarchyTimeoutErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain25/CddEmmBit25FSVIOHierarchyTimeoutErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain25/CddEmmBit25FSVIOHierarchyTimeoutErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain25/CddEmmBit25FSVIOHierarchyTimeoutErr/CddEmmErrorSignalTarget
+ INTC
+
+
+
+
+ CddEmmBit26FSVIOHierarchyISP0TimeoutErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain25/CddEmmBit26FSVIOHierarchyISP0TimeoutErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain25/CddEmmBit26FSVIOHierarchyISP0TimeoutErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain25/CddEmmBit26FSVIOHierarchyISP0TimeoutErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit27FSVIOHierarchyISP1TimeoutErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain25/CddEmmBit27FSVIOHierarchyISP1TimeoutErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain25/CddEmmBit27FSVIOHierarchyISP1TimeoutErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain25/CddEmmBit27FSVIOHierarchyISP1TimeoutErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit30FSVCHierarchyTimeoutErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain25/CddEmmBit30FSVCHierarchyTimeoutErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain25/CddEmmBit30FSVCHierarchyTimeoutErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain25/CddEmmBit30FSVCHierarchyTimeoutErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit31FSVCHierarchyIMR0TimeoutErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain25/CddEmmBit31FSVCHierarchyIMR0TimeoutErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain25/CddEmmBit31FSVCHierarchyIMR0TimeoutErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain25/CddEmmBit31FSVCHierarchyIMR0TimeoutErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+
+
+ CddEmmDomain26
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain26
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain26/CddEmmAddressToSaveErrorStatus
+ 1342177388
+
+
+
+
+ CddEmmBit3FSSIRHierarchyCnn0FailErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain26/CddEmmBit3FSSIRHierarchyCnn0FailErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain26/CddEmmBit3FSSIRHierarchyCnn0FailErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain26/CddEmmBit3FSSIRHierarchyCnn0FailErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit14FSFSIRHierarchyDSP0FailErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain26/CddEmmBit14FSFSIRHierarchyDSP0FailErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain26/CddEmmBit14FSFSIRHierarchyDSP0FailErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain26/CddEmmBit14FSFSIRHierarchyDSP0FailErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit15FSFSIRHierarchyDSP1FailErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain26/CddEmmBit15FSFSIRHierarchyDSP1FailErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain26/CddEmmBit15FSFSIRHierarchyDSP1FailErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain26/CddEmmBit15FSFSIRHierarchyDSP1FailErr/CddEmmErrorSignalTarget
+ INTC
+
+
+
+
+ CddEmmBit16FSFSIRHierarchyDSP2FailErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain26/CddEmmBit16FSFSIRHierarchyDSP2FailErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain26/CddEmmBit16FSFSIRHierarchyDSP2FailErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain26/CddEmmBit16FSFSIRHierarchyDSP2FailErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit17FSFSIRHierarchyDSP3FailErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain26/CddEmmBit17FSFSIRHierarchyDSP3FailErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain26/CddEmmBit17FSFSIRHierarchyDSP3FailErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain26/CddEmmBit17FSFSIRHierarchyDSP3FailErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit20FSFSIRHierarchyCNRAM0FailErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain26/CddEmmBit20FSFSIRHierarchyCNRAM0FailErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain26/CddEmmBit20FSFSIRHierarchyCNRAM0FailErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain26/CddEmmBit20FSFSIRHierarchyCNRAM0FailErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit21FSFSIRHierarchySlimdmac0FailErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain26/CddEmmBit21FSFSIRHierarchySlimdmac0FailErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain26/CddEmmBit21FSFSIRHierarchySlimdmac0FailErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain26/CddEmmBit21FSFSIRHierarchySlimdmac0FailErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit22FSFSIRHierarchySlimdmac1FailErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain26/CddEmmBit22FSFSIRHierarchySlimdmac1FailErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain26/CddEmmBit22FSFSIRHierarchySlimdmac1FailErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain26/CddEmmBit22FSFSIRHierarchySlimdmac1FailErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit23FSFSIRHierarchyIMPRAM0FailErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain26/CddEmmBit23FSFSIRHierarchyIMPRAM0FailErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain26/CddEmmBit23FSFSIRHierarchyIMPRAM0FailErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain26/CddEmmBit23FSFSIRHierarchyIMPRAM0FailErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit25FSFS3DGHierarchyRASCALFailErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain26/CddEmmBit25FSFS3DGHierarchyRASCALFailErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain26/CddEmmBit25FSFS3DGHierarchyRASCALFailErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain26/CddEmmBit25FSFS3DGHierarchyRASCALFailErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit26FSFS3DGHierarchyDUSTAFailErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain26/CddEmmBit26FSFS3DGHierarchyDUSTAFailErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain26/CddEmmBit26FSFS3DGHierarchyDUSTAFailErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain26/CddEmmBit26FSFS3DGHierarchyDUSTAFailErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit27FSFS3DGHierarchySLCSIDEKICKFailErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain26/CddEmmBit27FSFS3DGHierarchySLCSIDEKICKFailErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain26/CddEmmBit27FSFS3DGHierarchySLCSIDEKICKFailErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain26/CddEmmBit27FSFS3DGHierarchySLCSIDEKICKFailErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit28FSFS3DGHierarchyexceptRGXcoreFailErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain26/CddEmmBit28FSFS3DGHierarchyexceptRGXcoreFailErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain26/CddEmmBit28FSFS3DGHierarchyexceptRGXcoreFailErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain26/CddEmmBit28FSFS3DGHierarchyexceptRGXcoreFailErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit29FSFS3DGHierarchyXonstFailErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain26/CddEmmBit29FSFS3DGHierarchyXonstFailErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain26/CddEmmBit29FSFS3DGHierarchyXonstFailErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain26/CddEmmBit29FSFS3DGHierarchyXonstFailErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit30FSFSMMHierarchyDDRFailErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain26/CddEmmBit30FSFSMMHierarchyDDRFailErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain26/CddEmmBit30FSFSMMHierarchyDDRFailErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain26/CddEmmBit30FSFSMMHierarchyDDRFailErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+
+
+ CddEmmDomain27
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain27
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain27/CddEmmAddressToSaveErrorStatus
+ 1342177392
+
+
+
+
+ CddEmmBit0FSSVCHierarchyIMR1FailErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain27/CddEmmBit0FSSVCHierarchyIMR1FailErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain27/CddEmmBit0FSSVCHierarchyIMR1FailErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain27/CddEmmBit0FSSVCHierarchyIMR1FailErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit1FSSVCHierarchyIMR2FailErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain27/CddEmmBit1FSSVCHierarchyIMR2FailErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain27/CddEmmBit1FSSVCHierarchyIMR2FailErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain27/CddEmmBit1FSSVCHierarchyIMR2FailErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit3FSSVCHierarchyIMS0FailErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain27/CddEmmBit3FSSVCHierarchyIMS0FailErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain27/CddEmmBit3FSSVCHierarchyIMS0FailErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain27/CddEmmBit3FSSVCHierarchyIMS0FailErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit4FSSVCHierarchyIMS1FailErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain27/CddEmmBit4FSSVCHierarchyIMS1FailErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain27/CddEmmBit4FSSVCHierarchyIMS1FailErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain27/CddEmmBit4FSSVCHierarchyIMS1FailErr/CddEmmErrorSignalTarget
+ INTC
+
+
+
+
+ CddEmmBit6FSSVIPHierarchyFailErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain27/CddEmmBit6FSSVIPHierarchyFailErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain27/CddEmmBit6FSSVIPHierarchyFailErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain27/CddEmmBit6FSSVIPHierarchyFailErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit7FSSVIPHierarchyDULFailErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain27/CddEmmBit7FSSVIPHierarchyDULFailErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain27/CddEmmBit7FSSVIPHierarchyDULFailErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain27/CddEmmBit7FSSVIPHierarchyDULFailErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit9FSSVIPHierarchyUMFL0FailErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain27/CddEmmBit9FSSVIPHierarchyUMFL0FailErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain27/CddEmmBit9FSSVIPHierarchyUMFL0FailErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain27/CddEmmBit9FSSVIPHierarchyUMFL0FailErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit11FSFSVIPHierarchySMPS0FailErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain27/CddEmmBit11FSFSVIPHierarchySMPS0FailErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain27/CddEmmBit11FSFSVIPHierarchySMPS0FailErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain27/CddEmmBit11FSFSVIPHierarchySMPS0FailErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit15FSFSVIPHierarchySMPO0FailErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain27/CddEmmBit15FSFSVIPHierarchySMPO0FailErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain27/CddEmmBit15FSFSVIPHierarchySMPO0FailErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain27/CddEmmBit15FSFSVIPHierarchySMPO0FailErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit17FSFSVIPHierarchy2CLE0FailErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain27/CddEmmBit17FSFSVIPHierarchy2CLE0FailErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain27/CddEmmBit17FSFSVIPHierarchy2CLE0FailErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain27/CddEmmBit17FSFSVIPHierarchy2CLE0FailErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit18FSFSVIPHierarchy2CLE1FailErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain27/CddEmmBit18FSFSVIPHierarchy2CLE1FailErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain27/CddEmmBit18FSFSVIPHierarchy2CLE1FailErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain27/CddEmmBit18FSFSVIPHierarchy2CLE1FailErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit19FSFSIRHierarchyFailErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain27/CddEmmBit19FSFSIRHierarchyFailErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain27/CddEmmBit19FSFSIRHierarchyFailErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain27/CddEmmBit19FSFSIRHierarchyFailErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit20FSFSIRHierarchyA3IRBusWrapperFailErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain27/CddEmmBit20FSFSIRHierarchyA3IRBusWrapperFailErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain27/CddEmmBit20FSFSIRHierarchyA3IRBusWrapperFailErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain27/CddEmmBit20FSFSIRHierarchyA3IRBusWrapperFailErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit21FSFSIRHierarchyIMP0FailErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain27/CddEmmBit21FSFSIRHierarchyIMP0FailErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain27/CddEmmBit21FSFSIRHierarchyIMP0FailErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain27/CddEmmBit21FSFSIRHierarchyIMP0FailErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit22FSFSIRHierarchyIMP1FailErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain27/CddEmmBit22FSFSIRHierarchyIMP1FailErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain27/CddEmmBit22FSFSIRHierarchyIMP1FailErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain27/CddEmmBit22FSFSIRHierarchyIMP1FailErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit23FSFSIRHierarchyIMP2FailErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain27/CddEmmBit23FSFSIRHierarchyIMP2FailErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain27/CddEmmBit23FSFSIRHierarchyIMP2FailErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain27/CddEmmBit23FSFSIRHierarchyIMP2FailErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit24FSFSIRHierarchyIMP3FailErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain27/CddEmmBit24FSFSIRHierarchyIMP3FailErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain27/CddEmmBit24FSFSIRHierarchyIMP3FailErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain27/CddEmmBit24FSFSIRHierarchyIMP3FailErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit25FSFSIRHierarchyPSC0DMAC0RepeatFailErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain27/CddEmmBit25FSFSIRHierarchyPSC0DMAC0RepeatFailErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain27/CddEmmBit25FSFSIRHierarchyPSC0DMAC0RepeatFailErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain27/CddEmmBit25FSFSIRHierarchyPSC0DMAC0RepeatFailErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit26FSFSIRHierarchyDMAC2DMAC1RepeatFailErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain27/CddEmmBit26FSFSIRHierarchyDMAC2DMAC1RepeatFailErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain27/CddEmmBit26FSFSIRHierarchyDMAC2DMAC1RepeatFailErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain27/CddEmmBit26FSFSIRHierarchyDMAC2DMAC1RepeatFailErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit27FSFSIRHierarchyOCV0FailErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain27/CddEmmBit27FSFSIRHierarchyOCV0FailErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain27/CddEmmBit27FSFSIRHierarchyOCV0FailErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain27/CddEmmBit27FSFSIRHierarchyOCV0FailErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit28FSFSIRHierarchyOCV1FailErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain27/CddEmmBit28FSFSIRHierarchyOCV1FailErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain27/CddEmmBit28FSFSIRHierarchyOCV1FailErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain27/CddEmmBit28FSFSIRHierarchyOCV1FailErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit29FSFSIRHierarchyOCV2FailErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain27/CddEmmBit29FSFSIRHierarchyOCV2FailErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain27/CddEmmBit29FSFSIRHierarchyOCV2FailErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain27/CddEmmBit29FSFSIRHierarchyOCV2FailErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit30FSFSIRHierarchyOCV3FailErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain27/CddEmmBit30FSFSIRHierarchyOCV3FailErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain27/CddEmmBit30FSFSIRHierarchyOCV3FailErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain27/CddEmmBit30FSFSIRHierarchyOCV3FailErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+
+
+ CddEmmDomain28
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain28
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain28/CddEmmAddressToSaveErrorStatus
+ 1342177396
+
+
+
+
+ CddEmmBit0FSFSTOPHierarchyFailErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain28/CddEmmBit0FSFSTOPHierarchyFailErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain28/CddEmmBit0FSFSTOPHierarchyFailErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain28/CddEmmBit0FSFSTOPHierarchyFailErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit1FSFSMMHierarchyFailErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain28/CddEmmBit1FSFSMMHierarchyFailErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain28/CddEmmBit1FSFSMMHierarchyFailErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain28/CddEmmBit1FSFSMMHierarchyFailErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit2FSFSMMHierarchyDBSC0FailErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain28/CddEmmBit2FSFSMMHierarchyDBSC0FailErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain28/CddEmmBit2FSFSMMHierarchyDBSC0FailErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain28/CddEmmBit2FSFSMMHierarchyDBSC0FailErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit3FSFSMMHierarchyDBSC1FailErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain28/CddEmmBit3FSFSMMHierarchyDBSC1FailErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain28/CddEmmBit3FSFSMMHierarchyDBSC1FailErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain28/CddEmmBit3FSFSMMHierarchyDBSC1FailErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit4FSFSrtCPUHierarchyFailErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain28/CddEmmBit4FSFSrtCPUHierarchyFailErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain28/CddEmmBit4FSFSrtCPUHierarchyFailErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain28/CddEmmBit4FSFSrtCPUHierarchyFailErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit5FSFSrtCPUHierarchyCR52FailErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain28/CddEmmBit5FSFSrtCPUHierarchyCR52FailErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain28/CddEmmBit5FSFSrtCPUHierarchyCR52FailErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain28/CddEmmBit5FSFSrtCPUHierarchyCR52FailErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit6FSFSCCIHierarchyFailErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain28/CddEmmBit6FSFSCCIHierarchyFailErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain28/CddEmmBit6FSFSCCIHierarchyFailErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain28/CddEmmBit6FSFSCCIHierarchyFailErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit7FSFSCPU0HierarchyC4FailErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain28/CddEmmBit7FSFSCPU0HierarchyC4FailErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain28/CddEmmBit7FSFSCPU0HierarchyC4FailErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain28/CddEmmBit7FSFSCPU0HierarchyC4FailErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit8FSFSCPU0HierarchyA3EFailErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain28/CddEmmBit8FSFSCPU0HierarchyA3EFailErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain28/CddEmmBit8FSFSCPU0HierarchyA3EFailErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain28/CddEmmBit8FSFSCPU0HierarchyA3EFailErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit9FSFSCPU0HierarchyCl0L3CacheFailErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain28/CddEmmBit9FSFSCPU0HierarchyCl0L3CacheFailErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain28/CddEmmBit9FSFSCPU0HierarchyCl0L3CacheFailErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain28/CddEmmBit9FSFSCPU0HierarchyCl0L3CacheFailErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit10FSFSCPU0HierarchyCl1L3CacheFailErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain28/CddEmmBit10FSFSCPU0HierarchyCl1L3CacheFailErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain28/CddEmmBit10FSFSCPU0HierarchyCl1L3CacheFailErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain28/CddEmmBit10FSFSCPU0HierarchyCl1L3CacheFailErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit11FSFSCPU0HierarchyCl0CPU0FailErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain28/CddEmmBit11FSFSCPU0HierarchyCl0CPU0FailErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain28/CddEmmBit11FSFSCPU0HierarchyCl0CPU0FailErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain28/CddEmmBit11FSFSCPU0HierarchyCl0CPU0FailErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit12FSFSCPU0HierarchyCl0CPU1FailErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain28/CddEmmBit12FSFSCPU0HierarchyCl0CPU1FailErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain28/CddEmmBit12FSFSCPU0HierarchyCl0CPU1FailErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain28/CddEmmBit12FSFSCPU0HierarchyCl0CPU1FailErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit13FSFSCPU0HierarchyCl1CPU0FailErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain28/CddEmmBit13FSFSCPU0HierarchyCl1CPU0FailErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain28/CddEmmBit13FSFSCPU0HierarchyCl1CPU0FailErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain28/CddEmmBit13FSFSCPU0HierarchyCl1CPU0FailErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit14FSFSCPU0HierarchyCl1CPU1FailErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain28/CddEmmBit14FSFSCPU0HierarchyCl1CPU1FailErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain28/CddEmmBit14FSFSCPU0HierarchyCl1CPU1FailErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain28/CddEmmBit14FSFSCPU0HierarchyCl1CPU1FailErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit23FSFSPeripheralDMACHierarchy0FailErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain28/CddEmmBit23FSFSPeripheralDMACHierarchy0FailErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain28/CddEmmBit23FSFSPeripheralDMACHierarchy0FailErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain28/CddEmmBit23FSFSPeripheralDMACHierarchy0FailErr/CddEmmErrorSignalTarget
+ INTC
+
+
+
+
+ CddEmmBit24FSFSHSpeedComHierarchyFailErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain28/CddEmmBit24FSFSHSpeedComHierarchyFailErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain28/CddEmmBit24FSFSHSpeedComHierarchyFailErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain28/CddEmmBit24FSFSHSpeedComHierarchyFailErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit25FSFSVIOHierarchyFailErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain28/CddEmmBit25FSFSVIOHierarchyFailErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain28/CddEmmBit25FSFSVIOHierarchyFailErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain28/CddEmmBit25FSFSVIOHierarchyFailErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit26FSFSVIOHierarchyISP0FailErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain28/CddEmmBit26FSFSVIOHierarchyISP0FailErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain28/CddEmmBit26FSFSVIOHierarchyISP0FailErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain28/CddEmmBit26FSFSVIOHierarchyISP0FailErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit27FSFSVIOHierarchyISP1FailErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain28/CddEmmBit27FSFSVIOHierarchyISP1FailErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain28/CddEmmBit27FSFSVIOHierarchyISP1FailErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain28/CddEmmBit27FSFSVIOHierarchyISP1FailErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit30FSFSVCHierarchyFailErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain28/CddEmmBit30FSFSVCHierarchyFailErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain28/CddEmmBit30FSFSVCHierarchyFailErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain28/CddEmmBit30FSFSVCHierarchyFailErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit31FSFSVCHierarchyIMR0FailErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain28/CddEmmBit31FSFSVCHierarchyIMR0FailErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain28/CddEmmBit31FSFSVCHierarchyIMR0FailErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain28/CddEmmBit31FSFSVCHierarchyIMR0FailErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+
+
+ CddEmmDomain29
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain29
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain29/CddEmmAddressToSaveErrorStatus
+ 1342177400
+
+
+
+
+ CddEmmBit3FSRHierarchyCnn0SCanAXibusErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain29/CddEmmBit3FSRHierarchyCnn0SCanAXibusErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain29/CddEmmBit3FSRHierarchyCnn0SCanAXibusErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain29/CddEmmBit3FSRHierarchyCnn0SCanAXibusErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit14FSIRHierarchyDSP0SCanAXibusErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain29/CddEmmBit14FSIRHierarchyDSP0SCanAXibusErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain29/CddEmmBit14FSIRHierarchyDSP0SCanAXibusErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain29/CddEmmBit14FSIRHierarchyDSP0SCanAXibusErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit15FSIRHierarchyDSP1SCanAXibusErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain29/CddEmmBit15FSIRHierarchyDSP1SCanAXibusErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain29/CddEmmBit15FSIRHierarchyDSP1SCanAXibusErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain29/CddEmmBit15FSIRHierarchyDSP1SCanAXibusErr/CddEmmErrorSignalTarget
+ INTC
+
+
+
+
+ CddEmmBit16FSIRHierarchyDSP2SCanAXibusErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain29/CddEmmBit16FSIRHierarchyDSP2SCanAXibusErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain29/CddEmmBit16FSIRHierarchyDSP2SCanAXibusErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain29/CddEmmBit16FSIRHierarchyDSP2SCanAXibusErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit17FSIRHierarchyDSP3SCanAXibusErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain29/CddEmmBit17FSIRHierarchyDSP3SCanAXibusErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain29/CddEmmBit17FSIRHierarchyDSP3SCanAXibusErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain29/CddEmmBit17FSIRHierarchyDSP3SCanAXibusErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit20FSIRHierarchyCNRAM0SCanAXibusErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain29/CddEmmBit20FSIRHierarchyCNRAM0SCanAXibusErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain29/CddEmmBit20FSIRHierarchyCNRAM0SCanAXibusErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain29/CddEmmBit20FSIRHierarchyCNRAM0SCanAXibusErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit21FSIRHierarchySlimdmac0SCanAXibusErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain29/CddEmmBit21FSIRHierarchySlimdmac0SCanAXibusErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain29/CddEmmBit21FSIRHierarchySlimdmac0SCanAXibusErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain29/CddEmmBit21FSIRHierarchySlimdmac0SCanAXibusErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit22FSIRHierarchySlimdmac1SCanAXibusErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain29/CddEmmBit22FSIRHierarchySlimdmac1SCanAXibusErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain29/CddEmmBit22FSIRHierarchySlimdmac1SCanAXibusErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain29/CddEmmBit22FSIRHierarchySlimdmac1SCanAXibusErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+
+
+ CddEmmDomain30
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain30
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain30/CddEmmAddressToSaveErrorStatus
+ 1342177404
+
+
+
+
+ CddEmmBit0FSSVCHierarchyIMR1SCanAXiBusErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain30/CddEmmBit0FSSVCHierarchyIMR1SCanAXiBusErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain30/CddEmmBit0FSSVCHierarchyIMR1SCanAXiBusErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain30/CddEmmBit0FSSVCHierarchyIMR1SCanAXiBusErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit1FSSVCHierarchyIMR2SCanAXiBusErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain30/CddEmmBit1FSSVCHierarchyIMR2SCanAXiBusErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain30/CddEmmBit1FSSVCHierarchyIMR2SCanAXiBusErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain30/CddEmmBit1FSSVCHierarchyIMR2SCanAXiBusErr/CddEmmErrorSignalTarget
+ INTC
+
+
+
+
+ CddEmmBit3FSSVCHierarchyIMS0SCanAXiBusErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain30/CddEmmBit3FSSVCHierarchyIMS0SCanAXiBusErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain30/CddEmmBit3FSSVCHierarchyIMS0SCanAXiBusErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain30/CddEmmBit3FSSVCHierarchyIMS0SCanAXiBusErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit4FSSVCHierarchyIMS1SCanAXiBusErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain30/CddEmmBit4FSSVCHierarchyIMS1SCanAXiBusErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain30/CddEmmBit4FSSVCHierarchyIMS1SCanAXiBusErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain30/CddEmmBit4FSSVCHierarchyIMS1SCanAXiBusErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit7FSSVIPHierarchyDULSCanAXiBusErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain30/CddEmmBit7FSSVIPHierarchyDULSCanAXiBusErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain30/CddEmmBit7FSSVIPHierarchyDULSCanAXiBusErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain30/CddEmmBit7FSSVIPHierarchyDULSCanAXiBusErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit9FSSVIPHierarchyUMFL0SCanAXiBusErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain30/CddEmmBit9FSSVIPHierarchyUMFL0SCanAXiBusErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain30/CddEmmBit9FSSVIPHierarchyUMFL0SCanAXiBusErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain30/CddEmmBit9FSSVIPHierarchyUMFL0SCanAXiBusErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit11FSFSVIPHierarchySMPS0SCanAXibusErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain30/CddEmmBit11FSFSVIPHierarchySMPS0SCanAXibusErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain30/CddEmmBit11FSFSVIPHierarchySMPS0SCanAXibusErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain30/CddEmmBit11FSFSVIPHierarchySMPS0SCanAXibusErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit15FSFSVIPHierarchySMPO0SCanAXibusErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain30/CddEmmBit15FSFSVIPHierarchySMPO0SCanAXibusErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain30/CddEmmBit15FSFSVIPHierarchySMPO0SCanAXibusErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain30/CddEmmBit15FSFSVIPHierarchySMPO0SCanAXibusErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit17FSFSVIPHierarchy2CLE0SCanAXibusErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain30/CddEmmBit17FSFSVIPHierarchy2CLE0SCanAXibusErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain30/CddEmmBit17FSFSVIPHierarchy2CLE0SCanAXibusErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain30/CddEmmBit17FSFSVIPHierarchy2CLE0SCanAXibusErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit18FSFSVIPHierarchy2CLE1SCanAXibusErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain30/CddEmmBit18FSFSVIPHierarchy2CLE1SCanAXibusErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain30/CddEmmBit18FSFSVIPHierarchy2CLE1SCanAXibusErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain30/CddEmmBit18FSFSVIPHierarchy2CLE1SCanAXibusErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit21FSIRHierarchyIMP0SCanAXibusErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain30/CddEmmBit21FSIRHierarchyIMP0SCanAXibusErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain30/CddEmmBit21FSIRHierarchyIMP0SCanAXibusErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain30/CddEmmBit21FSIRHierarchyIMP0SCanAXibusErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit22FSIRHierarchyIMP1SCanAXibusErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain30/CddEmmBit22FSIRHierarchyIMP1SCanAXibusErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain30/CddEmmBit22FSIRHierarchyIMP1SCanAXibusErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain30/CddEmmBit22FSIRHierarchyIMP1SCanAXibusErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit23FSIRHierarchyIMP2SCanAXibusErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain30/CddEmmBit23FSIRHierarchyIMP2SCanAXibusErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain30/CddEmmBit23FSIRHierarchyIMP2SCanAXibusErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain30/CddEmmBit23FSIRHierarchyIMP2SCanAXibusErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit24FSIRHierarchyIMP3SCanAXibusErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain30/CddEmmBit24FSIRHierarchyIMP3SCanAXibusErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain30/CddEmmBit24FSIRHierarchyIMP3SCanAXibusErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain30/CddEmmBit24FSIRHierarchyIMP3SCanAXibusErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit25FSIRHierarchyPSC0DMAC0RepeatSCanAXibusErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain30/CddEmmBit25FSIRHierarchyPSC0DMAC0RepeatSCanAXibusErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain30/CddEmmBit25FSIRHierarchyPSC0DMAC0RepeatSCanAXibusErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain30/CddEmmBit25FSIRHierarchyPSC0DMAC0RepeatSCanAXibusErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit26FSIRHierarchyDMAC2DMAC1RepeatSCanAXibusErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain30/CddEmmBit26FSIRHierarchyDMAC2DMAC1RepeatSCanAXibusErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain30/CddEmmBit26FSIRHierarchyDMAC2DMAC1RepeatSCanAXibusErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain30/CddEmmBit26FSIRHierarchyDMAC2DMAC1RepeatSCanAXibusErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit27FSIRHierarchyOCV0SCanAXibusErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain30/CddEmmBit27FSIRHierarchyOCV0SCanAXibusErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain30/CddEmmBit27FSIRHierarchyOCV0SCanAXibusErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain30/CddEmmBit27FSIRHierarchyOCV0SCanAXibusErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit28FSIRHierarchyOCV1SCanAXibusErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain30/CddEmmBit28FSIRHierarchyOCV1SCanAXibusErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain30/CddEmmBit28FSIRHierarchyOCV1SCanAXibusErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain30/CddEmmBit28FSIRHierarchyOCV1SCanAXibusErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit29FSIRHierarchyOCV2SCanAXibusErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain30/CddEmmBit29FSIRHierarchyOCV2SCanAXibusErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain30/CddEmmBit29FSIRHierarchyOCV2SCanAXibusErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain30/CddEmmBit29FSIRHierarchyOCV2SCanAXibusErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit30FSIRHierarchyOCV3SCanAXibusErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain30/CddEmmBit30FSIRHierarchyOCV3SCanAXibusErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain30/CddEmmBit30FSIRHierarchyOCV3SCanAXibusErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain30/CddEmmBit30FSIRHierarchyOCV3SCanAXibusErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+
+
+ CddEmmDomain31
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain31
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain31/CddEmmAddressToSaveErrorStatus
+ 1342177408
+
+
+
+
+ CddEmmBit9FSFSCPU0HierarchyCl0L3CacheSCanAXiBusErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain31/CddEmmBit9FSFSCPU0HierarchyCl0L3CacheSCanAXiBusErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain31/CddEmmBit9FSFSCPU0HierarchyCl0L3CacheSCanAXiBusErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain31/CddEmmBit9FSFSCPU0HierarchyCl0L3CacheSCanAXiBusErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit10FSFSCPU0HierarchyCl1L3CacheSCanAXiBusErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain31/CddEmmBit10FSFSCPU0HierarchyCl1L3CacheSCanAXiBusErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain31/CddEmmBit10FSFSCPU0HierarchyCl1L3CacheSCanAXiBusErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain31/CddEmmBit10FSFSCPU0HierarchyCl1L3CacheSCanAXiBusErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit11FSFSCPU0HierarchyCl0CPU0SCanAXiBusErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain31/CddEmmBit11FSFSCPU0HierarchyCl0CPU0SCanAXiBusErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain31/CddEmmBit11FSFSCPU0HierarchyCl0CPU0SCanAXiBusErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain31/CddEmmBit11FSFSCPU0HierarchyCl0CPU0SCanAXiBusErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit12FSFSCPU0HierarchyCl0CPU1SCanAXiBusErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain31/CddEmmBit12FSFSCPU0HierarchyCl0CPU1SCanAXiBusErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain31/CddEmmBit12FSFSCPU0HierarchyCl0CPU1SCanAXiBusErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain31/CddEmmBit12FSFSCPU0HierarchyCl0CPU1SCanAXiBusErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit13FSFSCPU0HierarchyCl1CPU0SCanAXiBusErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain31/CddEmmBit13FSFSCPU0HierarchyCl1CPU0SCanAXiBusErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain31/CddEmmBit13FSFSCPU0HierarchyCl1CPU0SCanAXiBusErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain31/CddEmmBit13FSFSCPU0HierarchyCl1CPU0SCanAXiBusErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit14FSFSCPU0HierarchyCl1CPU1SCanAXiBusErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain31/CddEmmBit14FSFSCPU0HierarchyCl1CPU1SCanAXiBusErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain31/CddEmmBit14FSFSCPU0HierarchyCl1CPU1SCanAXiBusErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain31/CddEmmBit14FSFSCPU0HierarchyCl1CPU1SCanAXiBusErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit26FSFSVIOHierarchyISP0SCanAXiBusErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain31/CddEmmBit26FSFSVIOHierarchyISP0SCanAXiBusErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain31/CddEmmBit26FSFSVIOHierarchyISP0SCanAXiBusErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain31/CddEmmBit26FSFSVIOHierarchyISP0SCanAXiBusErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit27FSFSVIOHierarchyISP1SCanAXiBusErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain31/CddEmmBit27FSFSVIOHierarchyISP1SCanAXiBusErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain31/CddEmmBit27FSFSVIOHierarchyISP1SCanAXiBusErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain31/CddEmmBit27FSFSVIOHierarchyISP1SCanAXiBusErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit31FSFSVCHierarchyIMR0SCanAXiBusErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain31/CddEmmBit31FSFSVCHierarchyIMR0SCanAXiBusErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain31/CddEmmBit31FSFSVCHierarchyIMR0SCanAXiBusErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain31/CddEmmBit31FSFSVCHierarchyIMR0SCanAXiBusErr/CddEmmErrorSignalTarget
+ INTC
+
+
+
+
+
+
+ CddEmmDomain32
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain32
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain32/CddEmmAddressToSaveErrorStatus
+ 1342177412
+
+
+
+
+ CddEmmBit0RTCore1AXIMICorrectableErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain32/CddEmmBit0RTCore1AXIMICorrectableErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain32/CddEmmBit0RTCore1AXIMICorrectableErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain32/CddEmmBit0RTCore1AXIMICorrectableErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit1RTCore1AXIMIFatalErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain32/CddEmmBit1RTCore1AXIMIFatalErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain32/CddEmmBit1RTCore1AXIMIFatalErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain32/CddEmmBit1RTCore1AXIMIFatalErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit2RTCore1AXIMITimeoutErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain32/CddEmmBit2RTCore1AXIMITimeoutErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain32/CddEmmBit2RTCore1AXIMITimeoutErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain32/CddEmmBit2RTCore1AXIMITimeoutErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit3RTCore1AXISICorrectableErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain32/CddEmmBit3RTCore1AXISICorrectableErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain32/CddEmmBit3RTCore1AXISICorrectableErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain32/CddEmmBit3RTCore1AXISICorrectableErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit4RTCore1AXISIFatalErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain32/CddEmmBit4RTCore1AXISIFatalErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain32/CddEmmBit4RTCore1AXISIFatalErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain32/CddEmmBit4RTCore1AXISIFatalErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit5RTCore1AXISILockstepComparator1Err
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain32/CddEmmBit5RTCore1AXISILockstepComparator1Err
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain32/CddEmmBit5RTCore1AXISILockstepComparator1Err/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain32/CddEmmBit5RTCore1AXISILockstepComparator1Err/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit6RTCore1DataCacheErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain32/CddEmmBit6RTCore1DataCacheErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain32/CddEmmBit6RTCore1DataCacheErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain32/CddEmmBit6RTCore1DataCacheErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit7RTCore1EL1ControlledAbortExceptionErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain32/CddEmmBit7RTCore1EL1ControlledAbortExceptionErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain32/CddEmmBit7RTCore1EL1ControlledAbortExceptionErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain32/CddEmmBit7RTCore1EL1ControlledAbortExceptionErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit8RTCore1EL2ControlledabortExceptionErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain32/CddEmmBit8RTCore1EL2ControlledabortExceptionErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain32/CddEmmBit8RTCore1EL2ControlledabortExceptionErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain32/CddEmmBit8RTCore1EL2ControlledabortExceptionErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit9RTCore1SWRunInEL2UnlockTESTR1Err
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain32/CddEmmBit9RTCore1SWRunInEL2UnlockTESTR1Err
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain32/CddEmmBit9RTCore1SWRunInEL2UnlockTESTR1Err/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain32/CddEmmBit9RTCore1SWRunInEL2UnlockTESTR1Err/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit10RTCore1AsynchronousTransferErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain32/CddEmmBit10RTCore1AsynchronousTransferErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain32/CddEmmBit10RTCore1AsynchronousTransferErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain32/CddEmmBit10RTCore1AsynchronousTransferErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit11RTCore1InstructionCacheErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain32/CddEmmBit11RTCore1InstructionCacheErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain32/CddEmmBit11RTCore1InstructionCacheErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain32/CddEmmBit11RTCore1InstructionCacheErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit12RTCore1CorrectableNotRecordedErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain32/CddEmmBit12RTCore1CorrectableNotRecordedErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain32/CddEmmBit12RTCore1CorrectableNotRecordedErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain32/CddEmmBit12RTCore1CorrectableNotRecordedErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit13RTCore1FatalErrCannotRecorded
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain32/CddEmmBit13RTCore1FatalErrCannotRecorded
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain32/CddEmmBit13RTCore1FatalErrCannotRecorded/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain32/CddEmmBit13RTCore1FatalErrCannotRecorded/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit14RTCore1ProcessorLivelockErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain32/CddEmmBit14RTCore1ProcessorLivelockErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain32/CddEmmBit14RTCore1ProcessorLivelockErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain32/CddEmmBit14RTCore1ProcessorLivelockErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit15RTCore1LongHypervisorInterruptErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain32/CddEmmBit15RTCore1LongHypervisorInterruptErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain32/CddEmmBit15RTCore1LongHypervisorInterruptErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain32/CddEmmBit15RTCore1LongHypervisorInterruptErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit16RTCore1AXISILockstepComparator0Err
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain32/CddEmmBit16RTCore1AXISILockstepComparator0Err
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain32/CddEmmBit16RTCore1AXISILockstepComparator0Err/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain32/CddEmmBit16RTCore1AXISILockstepComparator0Err/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit17RTCore1HypervisorModeFatalErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain32/CddEmmBit17RTCore1HypervisorModeFatalErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain32/CddEmmBit17RTCore1HypervisorModeFatalErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain32/CddEmmBit17RTCore1HypervisorModeFatalErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit18RTCore1EL1controlledMemoryAccessErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain32/CddEmmBit18RTCore1EL1controlledMemoryAccessErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain32/CddEmmBit18RTCore1EL1controlledMemoryAccessErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain32/CddEmmBit18RTCore1EL1controlledMemoryAccessErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit19RTCore1EDCBtwRTCPUWritebufferErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain32/CddEmmBit19RTCore1EDCBtwRTCPUWritebufferErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain32/CddEmmBit19RTCore1EDCBtwRTCPUWritebufferErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain32/CddEmmBit19RTCore1EDCBtwRTCPUWritebufferErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit20RTCore1AXIMIDECERRSLVERRBusErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain32/CddEmmBit20RTCore1AXIMIDECERRSLVERRBusErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain32/CddEmmBit20RTCore1AXIMIDECERRSLVERRBusErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain32/CddEmmBit20RTCore1AXIMIDECERRSLVERRBusErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit21RTCore1NonSafetySwitchingComparator1Err
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain32/CddEmmBit21RTCore1NonSafetySwitchingComparator1Err
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain32/CddEmmBit21RTCore1NonSafetySwitchingComparator1Err/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain32/CddEmmBit21RTCore1NonSafetySwitchingComparator1Err/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit22RTCore1NonSafetySwitchingComparator0Err
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain32/CddEmmBit22RTCore1NonSafetySwitchingComparator0Err
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain32/CddEmmBit22RTCore1NonSafetySwitchingComparator0Err/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain32/CddEmmBit22RTCore1NonSafetySwitchingComparator0Err/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit23RTCore1TCMCorrectableErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain32/CddEmmBit23RTCore1TCMCorrectableErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain32/CddEmmBit23RTCore1TCMCorrectableErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain32/CddEmmBit23RTCore1TCMCorrectableErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit24RTCore1TCMMemoriesFatalErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain32/CddEmmBit24RTCore1TCMMemoriesFatalErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain32/CddEmmBit24RTCore1TCMMemoriesFatalErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain32/CddEmmBit24RTCore1TCMMemoriesFatalErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit25RTCore1EDCBtwRTCPUAXISlavebridgeErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain32/CddEmmBit25RTCore1EDCBtwRTCPUAXISlavebridgeErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain32/CddEmmBit25RTCore1EDCBtwRTCPUAXISlavebridgeErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain32/CddEmmBit25RTCore1EDCBtwRTCPUAXISlavebridgeErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit26RTCore1IllegalAxSIZEAxBURSTErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain32/CddEmmBit26RTCore1IllegalAxSIZEAxBURSTErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain32/CddEmmBit26RTCore1IllegalAxSIZEAxBURSTErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain32/CddEmmBit26RTCore1IllegalAxSIZEAxBURSTErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit27RTCore1UndefinedExceptionErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain32/CddEmmBit27RTCore1UndefinedExceptionErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain32/CddEmmBit27RTCore1UndefinedExceptionErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain32/CddEmmBit27RTCore1UndefinedExceptionErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit30CSI21Err
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain32/CddEmmBit30CSI21Err
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain32/CddEmmBit30CSI21Err/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain32/CddEmmBit30CSI21Err/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit31CSI20Err
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain32/CddEmmBit31CSI20Err
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain32/CddEmmBit31CSI20Err/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain32/CddEmmBit31CSI20Err/CddEmmErrorSignalTarget
+ INTC
+
+
+
+
+
+
+ CddEmmDomain33
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain33
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain33/CddEmmAddressToSaveErrorStatus
+ 1342177416
+
+
+
+
+ CddEmmBit0RTCore2AXIMICorrectableErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain33/CddEmmBit0RTCore2AXIMICorrectableErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain33/CddEmmBit0RTCore2AXIMICorrectableErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain33/CddEmmBit0RTCore2AXIMICorrectableErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit1RTCore2AXIMIFatalErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain33/CddEmmBit1RTCore2AXIMIFatalErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain33/CddEmmBit1RTCore2AXIMIFatalErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain33/CddEmmBit1RTCore2AXIMIFatalErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit2RTCore2AXIMITimeoutErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain33/CddEmmBit2RTCore2AXIMITimeoutErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain33/CddEmmBit2RTCore2AXIMITimeoutErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain33/CddEmmBit2RTCore2AXIMITimeoutErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit3RTCore2AXISICorrectableErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain33/CddEmmBit3RTCore2AXISICorrectableErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain33/CddEmmBit3RTCore2AXISICorrectableErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain33/CddEmmBit3RTCore2AXISICorrectableErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit4RTCore2AXISIFatalErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain33/CddEmmBit4RTCore2AXISIFatalErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain33/CddEmmBit4RTCore2AXISIFatalErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain33/CddEmmBit4RTCore2AXISIFatalErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit5RTCore2AXISILockstepComparator1Err
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain33/CddEmmBit5RTCore2AXISILockstepComparator1Err
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain33/CddEmmBit5RTCore2AXISILockstepComparator1Err/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain33/CddEmmBit5RTCore2AXISILockstepComparator1Err/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit6RTCore2DataCacheErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain33/CddEmmBit6RTCore2DataCacheErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain33/CddEmmBit6RTCore2DataCacheErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain33/CddEmmBit6RTCore2DataCacheErr/CddEmmErrorSignalTarget
+ INTC
+
+
+
+
+ CddEmmBit7RTCore2EL1ControlledAbortExceptionErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain33/CddEmmBit7RTCore2EL1ControlledAbortExceptionErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain33/CddEmmBit7RTCore2EL1ControlledAbortExceptionErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain33/CddEmmBit7RTCore2EL1ControlledAbortExceptionErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit8RTCore2EL2ControlledabortExceptionErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain33/CddEmmBit8RTCore2EL2ControlledabortExceptionErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain33/CddEmmBit8RTCore2EL2ControlledabortExceptionErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain33/CddEmmBit8RTCore2EL2ControlledabortExceptionErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit9RTCore2SWRunInEL2UnlockTESTR1Err
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain33/CddEmmBit9RTCore2SWRunInEL2UnlockTESTR1Err
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain33/CddEmmBit9RTCore2SWRunInEL2UnlockTESTR1Err/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain33/CddEmmBit9RTCore2SWRunInEL2UnlockTESTR1Err/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit10RTCore2AsynchronousTransferErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain33/CddEmmBit10RTCore2AsynchronousTransferErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain33/CddEmmBit10RTCore2AsynchronousTransferErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain33/CddEmmBit10RTCore2AsynchronousTransferErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit11RTCore2InstructionCacheErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain33/CddEmmBit11RTCore2InstructionCacheErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain33/CddEmmBit11RTCore2InstructionCacheErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain33/CddEmmBit11RTCore2InstructionCacheErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit12RTCore2CorrectableNotRecordedErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain33/CddEmmBit12RTCore2CorrectableNotRecordedErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain33/CddEmmBit12RTCore2CorrectableNotRecordedErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain33/CddEmmBit12RTCore2CorrectableNotRecordedErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit13RTCore2FatalErrCannotRecorded
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain33/CddEmmBit13RTCore2FatalErrCannotRecorded
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain33/CddEmmBit13RTCore2FatalErrCannotRecorded/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain33/CddEmmBit13RTCore2FatalErrCannotRecorded/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit14RTCore2ProcessorLivelockErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain33/CddEmmBit14RTCore2ProcessorLivelockErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain33/CddEmmBit14RTCore2ProcessorLivelockErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain33/CddEmmBit14RTCore2ProcessorLivelockErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit15RTCore2LongHypervisorInterruptErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain33/CddEmmBit15RTCore2LongHypervisorInterruptErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain33/CddEmmBit15RTCore2LongHypervisorInterruptErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain33/CddEmmBit15RTCore2LongHypervisorInterruptErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit16RTCore2AXISILockstepComparator0Err
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain33/CddEmmBit16RTCore2AXISILockstepComparator0Err
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain33/CddEmmBit16RTCore2AXISILockstepComparator0Err/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain33/CddEmmBit16RTCore2AXISILockstepComparator0Err/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit17RTCore2HypervisorModeFatalErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain33/CddEmmBit17RTCore2HypervisorModeFatalErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain33/CddEmmBit17RTCore2HypervisorModeFatalErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain33/CddEmmBit17RTCore2HypervisorModeFatalErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit18RTCore2EL1controlledMemoryAccessErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain33/CddEmmBit18RTCore2EL1controlledMemoryAccessErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain33/CddEmmBit18RTCore2EL1controlledMemoryAccessErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain33/CddEmmBit18RTCore2EL1controlledMemoryAccessErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit19RTCore2EDCBtwRTCPUWritebufferErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain33/CddEmmBit19RTCore2EDCBtwRTCPUWritebufferErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain33/CddEmmBit19RTCore2EDCBtwRTCPUWritebufferErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain33/CddEmmBit19RTCore2EDCBtwRTCPUWritebufferErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit20RTCore2AXIMIDECERRSLVERRBusErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain33/CddEmmBit20RTCore2AXIMIDECERRSLVERRBusErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain33/CddEmmBit20RTCore2AXIMIDECERRSLVERRBusErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain33/CddEmmBit20RTCore2AXIMIDECERRSLVERRBusErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit21RTCore2NonSafetySwitchingComparator1Err
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain33/CddEmmBit21RTCore2NonSafetySwitchingComparator1Err
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain33/CddEmmBit21RTCore2NonSafetySwitchingComparator1Err/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain33/CddEmmBit21RTCore2NonSafetySwitchingComparator1Err/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit22RTCore2NonSafetySwitchingComparator0Err
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain33/CddEmmBit22RTCore2NonSafetySwitchingComparator0Err
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain33/CddEmmBit22RTCore2NonSafetySwitchingComparator0Err/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain33/CddEmmBit22RTCore2NonSafetySwitchingComparator0Err/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit23RTCore2TCMCorrectableErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain33/CddEmmBit23RTCore2TCMCorrectableErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain33/CddEmmBit23RTCore2TCMCorrectableErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain33/CddEmmBit23RTCore2TCMCorrectableErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit24RTCore2TCMMemoriesFatalErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain33/CddEmmBit24RTCore2TCMMemoriesFatalErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain33/CddEmmBit24RTCore2TCMMemoriesFatalErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain33/CddEmmBit24RTCore2TCMMemoriesFatalErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit25RTCore2EDCBtwRTCPUAXISlavebridgeErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain33/CddEmmBit25RTCore2EDCBtwRTCPUAXISlavebridgeErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain33/CddEmmBit25RTCore2EDCBtwRTCPUAXISlavebridgeErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain33/CddEmmBit25RTCore2EDCBtwRTCPUAXISlavebridgeErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit26RTCore2IllegalAxSIZEAxBURSTErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain33/CddEmmBit26RTCore2IllegalAxSIZEAxBURSTErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain33/CddEmmBit26RTCore2IllegalAxSIZEAxBURSTErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain33/CddEmmBit26RTCore2IllegalAxSIZEAxBURSTErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit27RTCore2UndefinedExceptionErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain33/CddEmmBit27RTCore2UndefinedExceptionErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain33/CddEmmBit27RTCore2UndefinedExceptionErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain33/CddEmmBit27RTCore2UndefinedExceptionErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+
+
+ CddEmmDomain34
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain34
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain34/CddEmmAddressToSaveErrorStatus
+ 1342177420
+
+
+
+
+ CddEmmBit0PWMLoopbackFunctionErrch0
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain34/CddEmmBit0PWMLoopbackFunctionErrch0
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain34/CddEmmBit0PWMLoopbackFunctionErrch0/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain34/CddEmmBit0PWMLoopbackFunctionErrch0/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit1PWMLoopbackFunctionErrch1
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain34/CddEmmBit1PWMLoopbackFunctionErrch1
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain34/CddEmmBit1PWMLoopbackFunctionErrch1/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain34/CddEmmBit1PWMLoopbackFunctionErrch1/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit2PWMLoopbackFunctionErrch2
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain34/CddEmmBit2PWMLoopbackFunctionErrch2
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain34/CddEmmBit2PWMLoopbackFunctionErrch2/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain34/CddEmmBit2PWMLoopbackFunctionErrch2/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit3PWMLoopbackFunctionErrch3
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain34/CddEmmBit3PWMLoopbackFunctionErrch3
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain34/CddEmmBit3PWMLoopbackFunctionErrch3/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain34/CddEmmBit3PWMLoopbackFunctionErrch3/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit4PWMLoopbackFunctionErrch4
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain34/CddEmmBit4PWMLoopbackFunctionErrch4
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain34/CddEmmBit4PWMLoopbackFunctionErrch4/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain34/CddEmmBit4PWMLoopbackFunctionErrch4/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit5PWMLoopbackFunctionErrch5
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain34/CddEmmBit5PWMLoopbackFunctionErrch5
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain34/CddEmmBit5PWMLoopbackFunctionErrch5/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain34/CddEmmBit5PWMLoopbackFunctionErrch5/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit6PWMLoopbackFunctionErrch6
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain34/CddEmmBit6PWMLoopbackFunctionErrch6
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain34/CddEmmBit6PWMLoopbackFunctionErrch6/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain34/CddEmmBit6PWMLoopbackFunctionErrch6/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit7PWMLoopbackFunctionErrch7
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain34/CddEmmBit7PWMLoopbackFunctionErrch7
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain34/CddEmmBit7PWMLoopbackFunctionErrch7/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain34/CddEmmBit7PWMLoopbackFunctionErrch7/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit8PWMLoopbackFunctionErrch8
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain34/CddEmmBit8PWMLoopbackFunctionErrch8
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain34/CddEmmBit8PWMLoopbackFunctionErrch8/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain34/CddEmmBit8PWMLoopbackFunctionErrch8/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit9PWMLoopbackFunctionErrch9
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain34/CddEmmBit9PWMLoopbackFunctionErrch9
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain34/CddEmmBit9PWMLoopbackFunctionErrch9/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain34/CddEmmBit9PWMLoopbackFunctionErrch9/CddEmmErrorSignalTarget
+ INTC
+
+
+
+
+
+
+ CddEmmDomain35
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain35
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain35/CddEmmAddressToSaveErrorStatus
+ 1342177424
+
+
+
+
+ CddEmmBit6APSysApmuCA76Cl1PchProtocolInterfaceErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain35/CddEmmBit6APSysApmuCA76Cl1PchProtocolInterfaceErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain35/CddEmmBit6APSysApmuCA76Cl1PchProtocolInterfaceErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain35/CddEmmBit6APSysApmuCA76Cl1PchProtocolInterfaceErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit7APSysApmuCA76Cl0PchProtocolInterfaceErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain35/CddEmmBit7APSysApmuCA76Cl0PchProtocolInterfaceErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain35/CddEmmBit7APSysApmuCA76Cl0PchProtocolInterfaceErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain35/CddEmmBit7APSysApmuCA76Cl0PchProtocolInterfaceErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit8APSysAXI4StreambusINTAPCA76Cl1RequestOrderErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain35/CddEmmBit8APSysAXI4StreambusINTAPCA76Cl1RequestOrderErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain35/CddEmmBit8APSysAXI4StreambusINTAPCA76Cl1RequestOrderErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain35/CddEmmBit8APSysAXI4StreambusINTAPCA76Cl1RequestOrderErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit9APSysAXI4StreambusINTAPCA76Cl0RequestOrderErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain35/CddEmmBit9APSysAXI4StreambusINTAPCA76Cl0RequestOrderErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain35/CddEmmBit9APSysAXI4StreambusINTAPCA76Cl0RequestOrderErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain35/CddEmmBit9APSysAXI4StreambusINTAPCA76Cl0RequestOrderErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit10APSysAXI4StreambusINTAPCA76Cl1EdcErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain35/CddEmmBit10APSysAXI4StreambusINTAPCA76Cl1EdcErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain35/CddEmmBit10APSysAXI4StreambusINTAPCA76Cl1EdcErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain35/CddEmmBit10APSysAXI4StreambusINTAPCA76Cl1EdcErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit11APSysAXI4StreambusINTAPCA76Cl0EdcErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain35/CddEmmBit11APSysAXI4StreambusINTAPCA76Cl0EdcErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain35/CddEmmBit11APSysAXI4StreambusINTAPCA76Cl0EdcErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain35/CddEmmBit11APSysAXI4StreambusINTAPCA76Cl0EdcErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit12APSysArmgcCA76Cl1CounterInterfeceErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain35/CddEmmBit12APSysArmgcCA76Cl1CounterInterfeceErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain35/CddEmmBit12APSysArmgcCA76Cl1CounterInterfeceErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain35/CddEmmBit12APSysArmgcCA76Cl1CounterInterfeceErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit13APSysArmgcCA76Cl0CounterInterfeceErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain35/CddEmmBit13APSysArmgcCA76Cl0CounterInterfeceErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain35/CddEmmBit13APSysArmgcCA76Cl0CounterInterfeceErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain35/CddEmmBit13APSysArmgcCA76Cl0CounterInterfeceErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit14APSysCA76Core3L1IL1DL2MmuCorrectedErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain35/CddEmmBit14APSysCA76Core3L1IL1DL2MmuCorrectedErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain35/CddEmmBit14APSysCA76Core3L1IL1DL2MmuCorrectedErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain35/CddEmmBit14APSysCA76Core3L1IL1DL2MmuCorrectedErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit15APSysCA76Core2L1IL1DL2MmuCorrectedErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain35/CddEmmBit15APSysCA76Core2L1IL1DL2MmuCorrectedErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain35/CddEmmBit15APSysCA76Core2L1IL1DL2MmuCorrectedErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain35/CddEmmBit15APSysCA76Core2L1IL1DL2MmuCorrectedErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit16APSysL3Cl1correctedErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain35/CddEmmBit16APSysL3Cl1correctedErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain35/CddEmmBit16APSysL3Cl1correctedErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain35/CddEmmBit16APSysL3Cl1correctedErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit17APSysCA76Core1L1IL1DL2MmuCorrectedErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain35/CddEmmBit17APSysCA76Core1L1IL1DL2MmuCorrectedErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain35/CddEmmBit17APSysCA76Core1L1IL1DL2MmuCorrectedErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain35/CddEmmBit17APSysCA76Core1L1IL1DL2MmuCorrectedErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit18APSysCA76Core0L1IL1DL2MmuCorrectedErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain35/CddEmmBit18APSysCA76Core0L1IL1DL2MmuCorrectedErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain35/CddEmmBit18APSysCA76Core0L1IL1DL2MmuCorrectedErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain35/CddEmmBit18APSysCA76Core0L1IL1DL2MmuCorrectedErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit19APSysL3Cl0correctedErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain35/CddEmmBit19APSysL3Cl0correctedErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain35/CddEmmBit19APSysL3Cl0correctedErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain35/CddEmmBit19APSysL3Cl0correctedErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit20APSysCA76Core3L1IL1DL2MmuUncorrectedErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain35/CddEmmBit20APSysCA76Core3L1IL1DL2MmuUncorrectedErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain35/CddEmmBit20APSysCA76Core3L1IL1DL2MmuUncorrectedErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain35/CddEmmBit20APSysCA76Core3L1IL1DL2MmuUncorrectedErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit21APSysCA76Core2L1IL1DL2MmuUncorrectedErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain35/CddEmmBit21APSysCA76Core2L1IL1DL2MmuUncorrectedErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain35/CddEmmBit21APSysCA76Core2L1IL1DL2MmuUncorrectedErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain35/CddEmmBit21APSysCA76Core2L1IL1DL2MmuUncorrectedErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit22APSysL3Cl1UncorrectedErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain35/CddEmmBit22APSysL3Cl1UncorrectedErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain35/CddEmmBit22APSysL3Cl1UncorrectedErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain35/CddEmmBit22APSysL3Cl1UncorrectedErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit23APSysCA76Core1L1IL1DL2MmuUncorrectedErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain35/CddEmmBit23APSysCA76Core1L1IL1DL2MmuUncorrectedErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain35/CddEmmBit23APSysCA76Core1L1IL1DL2MmuUncorrectedErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain35/CddEmmBit23APSysCA76Core1L1IL1DL2MmuUncorrectedErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit24APSysCA76Core0L1IL1DL2MmuUncorrectedErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain35/CddEmmBit24APSysCA76Core0L1IL1DL2MmuUncorrectedErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain35/CddEmmBit24APSysCA76Core0L1IL1DL2MmuUncorrectedErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain35/CddEmmBit24APSysCA76Core0L1IL1DL2MmuUncorrectedErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit25APSysL3Cl0UncorrectedErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain35/CddEmmBit25APSysL3Cl0UncorrectedErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain35/CddEmmBit25APSysL3Cl0UncorrectedErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain35/CddEmmBit25APSysL3Cl0UncorrectedErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit26APSysCA76Cl0RedundantErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain35/CddEmmBit26APSysCA76Cl0RedundantErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain35/CddEmmBit26APSysCA76Cl0RedundantErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain35/CddEmmBit26APSysCA76Cl0RedundantErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit27APSysCA76Cl0LockstepErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain35/CddEmmBit27APSysCA76Cl0LockstepErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain35/CddEmmBit27APSysCA76Cl0LockstepErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain35/CddEmmBit27APSysCA76Cl0LockstepErr/CddEmmErrorSignalTarget
+ INTC
+
+
+
+
+ CddEmmBit28APSysAcebusCciCA76Cl1RequestOrderErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain35/CddEmmBit28APSysAcebusCciCA76Cl1RequestOrderErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain35/CddEmmBit28APSysAcebusCciCA76Cl1RequestOrderErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain35/CddEmmBit28APSysAcebusCciCA76Cl1RequestOrderErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit29APSysAcebusCciCA76Cl0RequestOrderErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain35/CddEmmBit29APSysAcebusCciCA76Cl0RequestOrderErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain35/CddEmmBit29APSysAcebusCciCA76Cl0RequestOrderErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain35/CddEmmBit29APSysAcebusCciCA76Cl0RequestOrderErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit30APSysAcebusCciCA76Cl1EdcErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain35/CddEmmBit30APSysAcebusCciCA76Cl1EdcErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain35/CddEmmBit30APSysAcebusCciCA76Cl1EdcErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain35/CddEmmBit30APSysAcebusCciCA76Cl1EdcErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit31APSysAcebusCciCA76Cl0EdcErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain35/CddEmmBit31APSysAcebusCciCA76Cl0EdcErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain35/CddEmmBit31APSysAcebusCciCA76Cl0EdcErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain35/CddEmmBit31APSysAcebusCciCA76Cl0EdcErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+
+
+ CddEmmDomain36
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain36
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain36/CddEmmAddressToSaveErrorStatus
+ 1342177428
+
+
+
+
+ CddEmmBit0VINCh15ModuleCombinedEdcErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain36/CddEmmBit0VINCh15ModuleCombinedEdcErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain36/CddEmmBit0VINCh15ModuleCombinedEdcErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain36/CddEmmBit0VINCh15ModuleCombinedEdcErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit1VINCh15ModuleCombinedSafetyErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain36/CddEmmBit1VINCh15ModuleCombinedSafetyErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain36/CddEmmBit1VINCh15ModuleCombinedSafetyErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain36/CddEmmBit1VINCh15ModuleCombinedSafetyErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit2VINCh14ModuleCombinedEdcErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain36/CddEmmBit2VINCh14ModuleCombinedEdcErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain36/CddEmmBit2VINCh14ModuleCombinedEdcErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain36/CddEmmBit2VINCh14ModuleCombinedEdcErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit3VINCh14ModuleCombinedSafetyErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain36/CddEmmBit3VINCh14ModuleCombinedSafetyErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain36/CddEmmBit3VINCh14ModuleCombinedSafetyErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain36/CddEmmBit3VINCh14ModuleCombinedSafetyErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit4VINCh13ModuleCombinedEdcErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain36/CddEmmBit4VINCh13ModuleCombinedEdcErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain36/CddEmmBit4VINCh13ModuleCombinedEdcErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain36/CddEmmBit4VINCh13ModuleCombinedEdcErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit5VINCh13ModuleCombinedSafetyErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain36/CddEmmBit5VINCh13ModuleCombinedSafetyErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain36/CddEmmBit5VINCh13ModuleCombinedSafetyErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain36/CddEmmBit5VINCh13ModuleCombinedSafetyErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit6VINCh12ModuleCombinedEdcErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain36/CddEmmBit6VINCh12ModuleCombinedEdcErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain36/CddEmmBit6VINCh12ModuleCombinedEdcErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain36/CddEmmBit6VINCh12ModuleCombinedEdcErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit7VINCh12ModuleCombinedSafetyErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain36/CddEmmBit7VINCh12ModuleCombinedSafetyErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain36/CddEmmBit7VINCh12ModuleCombinedSafetyErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain36/CddEmmBit7VINCh12ModuleCombinedSafetyErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit8VINCh11ModuleCombinedEdcErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain36/CddEmmBit8VINCh11ModuleCombinedEdcErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain36/CddEmmBit8VINCh11ModuleCombinedEdcErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain36/CddEmmBit8VINCh11ModuleCombinedEdcErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit9VINCh11ModuleCombinedSafetyErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain36/CddEmmBit9VINCh11ModuleCombinedSafetyErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain36/CddEmmBit9VINCh11ModuleCombinedSafetyErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain36/CddEmmBit9VINCh11ModuleCombinedSafetyErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit10VINCh10ModuleCombinedEdcErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain36/CddEmmBit10VINCh10ModuleCombinedEdcErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain36/CddEmmBit10VINCh10ModuleCombinedEdcErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain36/CddEmmBit10VINCh10ModuleCombinedEdcErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit11VINCh10ModuleCombinedSafetyErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain36/CddEmmBit11VINCh10ModuleCombinedSafetyErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain36/CddEmmBit11VINCh10ModuleCombinedSafetyErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain36/CddEmmBit11VINCh10ModuleCombinedSafetyErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit12VINCh9ModuleCombinedEdcErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain36/CddEmmBit12VINCh9ModuleCombinedEdcErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain36/CddEmmBit12VINCh9ModuleCombinedEdcErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain36/CddEmmBit12VINCh9ModuleCombinedEdcErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit13VINCh9ModuleCombinedSafetyErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain36/CddEmmBit13VINCh9ModuleCombinedSafetyErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain36/CddEmmBit13VINCh9ModuleCombinedSafetyErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain36/CddEmmBit13VINCh9ModuleCombinedSafetyErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit14VINCh8ModuleCombinedEdcErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain36/CddEmmBit14VINCh8ModuleCombinedEdcErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain36/CddEmmBit14VINCh8ModuleCombinedEdcErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain36/CddEmmBit14VINCh8ModuleCombinedEdcErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit15VINCh8ModuleCombinedSafetyErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain36/CddEmmBit15VINCh8ModuleCombinedSafetyErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain36/CddEmmBit15VINCh8ModuleCombinedSafetyErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain36/CddEmmBit15VINCh8ModuleCombinedSafetyErr/CddEmmErrorSignalTarget
+ INTC
+
+
+
+
+ CddEmmBit16VINCh7ModuleCombinedEdcErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain36/CddEmmBit16VINCh7ModuleCombinedEdcErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain36/CddEmmBit16VINCh7ModuleCombinedEdcErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain36/CddEmmBit16VINCh7ModuleCombinedEdcErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit17VINCh7ModuleCombinedSafetyErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain36/CddEmmBit17VINCh7ModuleCombinedSafetyErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain36/CddEmmBit17VINCh7ModuleCombinedSafetyErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain36/CddEmmBit17VINCh7ModuleCombinedSafetyErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit18VINCh6ModuleCombinedEdcErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain36/CddEmmBit18VINCh6ModuleCombinedEdcErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain36/CddEmmBit18VINCh6ModuleCombinedEdcErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain36/CddEmmBit18VINCh6ModuleCombinedEdcErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit19VINCh6ModuleCombinedSafetyErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain36/CddEmmBit19VINCh6ModuleCombinedSafetyErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain36/CddEmmBit19VINCh6ModuleCombinedSafetyErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain36/CddEmmBit19VINCh6ModuleCombinedSafetyErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit20VINCh5ModuleCombinedEdcErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain36/CddEmmBit20VINCh5ModuleCombinedEdcErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain36/CddEmmBit20VINCh5ModuleCombinedEdcErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain36/CddEmmBit20VINCh5ModuleCombinedEdcErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit21VINCh5ModuleCombinedSafetyErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain36/CddEmmBit21VINCh5ModuleCombinedSafetyErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain36/CddEmmBit21VINCh5ModuleCombinedSafetyErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain36/CddEmmBit21VINCh5ModuleCombinedSafetyErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit22VINCh4ModuleCombinedEdcErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain36/CddEmmBit22VINCh4ModuleCombinedEdcErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain36/CddEmmBit22VINCh4ModuleCombinedEdcErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain36/CddEmmBit22VINCh4ModuleCombinedEdcErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit23VINCh4ModuleCombinedSafetyErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain36/CddEmmBit23VINCh4ModuleCombinedSafetyErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain36/CddEmmBit23VINCh4ModuleCombinedSafetyErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain36/CddEmmBit23VINCh4ModuleCombinedSafetyErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit24VINCh3ModuleCombinedEdcErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain36/CddEmmBit24VINCh3ModuleCombinedEdcErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain36/CddEmmBit24VINCh3ModuleCombinedEdcErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain36/CddEmmBit24VINCh3ModuleCombinedEdcErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit25VINCh3ModuleCombinedSafetyErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain36/CddEmmBit25VINCh3ModuleCombinedSafetyErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain36/CddEmmBit25VINCh3ModuleCombinedSafetyErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain36/CddEmmBit25VINCh3ModuleCombinedSafetyErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit26VINCh2ModuleCombinedEdcErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain36/CddEmmBit26VINCh2ModuleCombinedEdcErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain36/CddEmmBit26VINCh2ModuleCombinedEdcErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain36/CddEmmBit26VINCh2ModuleCombinedEdcErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit27VINCh2ModuleCombinedSafetyErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain36/CddEmmBit27VINCh2ModuleCombinedSafetyErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain36/CddEmmBit27VINCh2ModuleCombinedSafetyErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain36/CddEmmBit27VINCh2ModuleCombinedSafetyErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit28VINCh1ModuleCombinedEdcErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain36/CddEmmBit28VINCh1ModuleCombinedEdcErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain36/CddEmmBit28VINCh1ModuleCombinedEdcErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain36/CddEmmBit28VINCh1ModuleCombinedEdcErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit29VINCh1ModuleCombinedSafetyErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain36/CddEmmBit29VINCh1ModuleCombinedSafetyErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain36/CddEmmBit29VINCh1ModuleCombinedSafetyErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain36/CddEmmBit29VINCh1ModuleCombinedSafetyErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit30VINCh0ModuleCombinedEdcErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain36/CddEmmBit30VINCh0ModuleCombinedEdcErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain36/CddEmmBit30VINCh0ModuleCombinedEdcErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain36/CddEmmBit30VINCh0ModuleCombinedEdcErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit31VINCh0ModuleCombinedSafetyErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain36/CddEmmBit31VINCh0ModuleCombinedSafetyErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain36/CddEmmBit31VINCh0ModuleCombinedSafetyErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain36/CddEmmBit31VINCh0ModuleCombinedSafetyErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+
+
+ CddEmmDomain38
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain38
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain38/CddEmmAddressToSaveErrorStatus
+ 1342177436
+
+
+
+
+ CddEmmBit0CANFDRAMEcc1bitErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain38/CddEmmBit0CANFDRAMEcc1bitErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain38/CddEmmBit0CANFDRAMEcc1bitErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain38/CddEmmBit0CANFDRAMEcc1bitErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit1CANFDRAMEcc2bitErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain38/CddEmmBit1CANFDRAMEcc2bitErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain38/CddEmmBit1CANFDRAMEcc2bitErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain38/CddEmmBit1CANFDRAMEcc2bitErr/CddEmmErrorSignalTarget
+ INTC
+
+
+
+
+ CddEmmBit2FLEXRAYTBF2InterruptNotificationEdcErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain38/CddEmmBit2FLEXRAYTBF2InterruptNotificationEdcErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain38/CddEmmBit2FLEXRAYTBF2InterruptNotificationEdcErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain38/CddEmmBit2FLEXRAYTBF2InterruptNotificationEdcErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit3FLEXRAYTBF2InterruptNotificationEccErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain38/CddEmmBit3FLEXRAYTBF2InterruptNotificationEccErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain38/CddEmmBit3FLEXRAYTBF2InterruptNotificationEccErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain38/CddEmmBit3FLEXRAYTBF2InterruptNotificationEccErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit4FLEXRAYTBF1InterruptNotificationEdcErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain38/CddEmmBit4FLEXRAYTBF1InterruptNotificationEdcErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain38/CddEmmBit4FLEXRAYTBF1InterruptNotificationEdcErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain38/CddEmmBit4FLEXRAYTBF1InterruptNotificationEdcErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit5FLEXRAYTBF1InterruptNotificationEccErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain38/CddEmmBit5FLEXRAYTBF1InterruptNotificationEccErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain38/CddEmmBit5FLEXRAYTBF1InterruptNotificationEccErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain38/CddEmmBit5FLEXRAYTBF1InterruptNotificationEccErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit6FLEXRAYMBFInterruptNotificationEdcErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain38/CddEmmBit6FLEXRAYMBFInterruptNotificationEdcErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain38/CddEmmBit6FLEXRAYMBFInterruptNotificationEdcErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain38/CddEmmBit6FLEXRAYMBFInterruptNotificationEdcErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit7FLEXRAYMBFInterruptNotificationEccErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain38/CddEmmBit7FLEXRAYMBFInterruptNotificationEccErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain38/CddEmmBit7FLEXRAYMBFInterruptNotificationEccErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain38/CddEmmBit7FLEXRAYMBFInterruptNotificationEccErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit20EtherAVB2TXRAMEccMultibitErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain38/CddEmmBit20EtherAVB2TXRAMEccMultibitErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain38/CddEmmBit20EtherAVB2TXRAMEccMultibitErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain38/CddEmmBit20EtherAVB2TXRAMEccMultibitErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit21EtherAVB2RXRAMEccMultibitErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain38/CddEmmBit21EtherAVB2RXRAMEccMultibitErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain38/CddEmmBit21EtherAVB2RXRAMEccMultibitErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain38/CddEmmBit21EtherAVB2RXRAMEccMultibitErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit22EtherAVB2TXRAMEcc1bitErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain38/CddEmmBit22EtherAVB2TXRAMEcc1bitErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain38/CddEmmBit22EtherAVB2TXRAMEcc1bitErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain38/CddEmmBit22EtherAVB2TXRAMEcc1bitErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit23EtherAVB2RXRAMEcc1bitErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain38/CddEmmBit23EtherAVB2RXRAMEcc1bitErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain38/CddEmmBit23EtherAVB2RXRAMEcc1bitErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain38/CddEmmBit23EtherAVB2RXRAMEcc1bitErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit24EtherAVB1TXRAMEccMultibitErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain38/CddEmmBit24EtherAVB1TXRAMEccMultibitErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain38/CddEmmBit24EtherAVB1TXRAMEccMultibitErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain38/CddEmmBit24EtherAVB1TXRAMEccMultibitErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit25EtherAVB1RXRAMEccMultibitErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain38/CddEmmBit25EtherAVB1RXRAMEccMultibitErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain38/CddEmmBit25EtherAVB1RXRAMEccMultibitErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain38/CddEmmBit25EtherAVB1RXRAMEccMultibitErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit26EtherAVB1TXRAMEcc1bitErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain38/CddEmmBit26EtherAVB1TXRAMEcc1bitErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain38/CddEmmBit26EtherAVB1TXRAMEcc1bitErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain38/CddEmmBit26EtherAVB1TXRAMEcc1bitErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit27EtherAVB1RXRAMEcc1bitErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain38/CddEmmBit27EtherAVB1RXRAMEcc1bitErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain38/CddEmmBit27EtherAVB1RXRAMEcc1bitErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain38/CddEmmBit27EtherAVB1RXRAMEcc1bitErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit28EtherAVB0TXRAMEccMultibitErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain38/CddEmmBit28EtherAVB0TXRAMEccMultibitErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain38/CddEmmBit28EtherAVB0TXRAMEccMultibitErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain38/CddEmmBit28EtherAVB0TXRAMEccMultibitErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit29EtherAVB0RXRAMEccMultibitErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain38/CddEmmBit29EtherAVB0RXRAMEccMultibitErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain38/CddEmmBit29EtherAVB0RXRAMEccMultibitErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain38/CddEmmBit29EtherAVB0RXRAMEccMultibitErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit30EtherAVB0TXRAMEcc1bitErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain38/CddEmmBit30EtherAVB0TXRAMEcc1bitErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain38/CddEmmBit30EtherAVB0TXRAMEcc1bitErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain38/CddEmmBit30EtherAVB0TXRAMEcc1bitErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit31EtherAVB0RXRAMEcc1bitErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain38/CddEmmBit31EtherAVB0RXRAMEcc1bitErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain38/CddEmmBit31EtherAVB0RXRAMEcc1bitErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain38/CddEmmBit31EtherAVB0RXRAMEcc1bitErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+
+
+ CddEmmDomain39
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain39
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain39/CddEmmAddressToSaveErrorStatus
+ 1342177440
+
+
+
+
+ CddEmmBit16AXIBusECMRT2
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain39/CddEmmBit16AXIBusECMRT2
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain39/CddEmmBit16AXIBusECMRT2/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain39/CddEmmBit16AXIBusECMRT2/CddEmmErrorSignalTarget
+ INTC
+
+
+
+
+ CddEmmBit17AXIBusECMRT1
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain39/CddEmmBit17AXIBusECMRT1
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain39/CddEmmBit17AXIBusECMRT1/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain39/CddEmmBit17AXIBusECMRT1/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit18AXIBusECMRT3
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain39/CddEmmBit18AXIBusECMRT3
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain39/CddEmmBit18AXIBusECMRT3/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain39/CddEmmBit18AXIBusECMRT3/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit19AXIBusECMTOP2
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain39/CddEmmBit19AXIBusECMTOP2
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain39/CddEmmBit19AXIBusECMTOP2/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain39/CddEmmBit19AXIBusECMTOP2/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit20AXIBusECMPER01
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain39/CddEmmBit20AXIBusECMPER01
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain39/CddEmmBit20AXIBusECMPER01/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain39/CddEmmBit20AXIBusECMPER01/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit21AXIBusECMPER02
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain39/CddEmmBit21AXIBusECMPER02
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain39/CddEmmBit21AXIBusECMPER02/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain39/CddEmmBit21AXIBusECMPER02/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit22AXIBusECMPER03
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain39/CddEmmBit22AXIBusECMPER03
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain39/CddEmmBit22AXIBusECMPER03/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain39/CddEmmBit22AXIBusECMPER03/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit23AXIBusECMTOP1
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain39/CddEmmBit23AXIBusECMTOP1
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain39/CddEmmBit23AXIBusECMTOP1/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain39/CddEmmBit23AXIBusECMTOP1/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit24AXIBusECMTOP3
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain39/CddEmmBit24AXIBusECMTOP3
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain39/CddEmmBit24AXIBusECMTOP3/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain39/CddEmmBit24AXIBusECMTOP3/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit25AXIBusECMVC1
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain39/CddEmmBit25AXIBusECMVC1
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain39/CddEmmBit25AXIBusECMVC1/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain39/CddEmmBit25AXIBusECMVC1/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit26AXIBusECMVIP1
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain39/CddEmmBit26AXIBusECMVIP1
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain39/CddEmmBit26AXIBusECMVIP1/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain39/CddEmmBit26AXIBusECMVIP1/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit27AXIBusECMVIO1
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain39/CddEmmBit27AXIBusECMVIO1
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain39/CddEmmBit27AXIBusECMVIO1/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain39/CddEmmBit27AXIBusECMVIO1/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit28AXIBusECMVIO2
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain39/CddEmmBit28AXIBusECMVIO2
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain39/CddEmmBit28AXIBusECMVIO2/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain39/CddEmmBit28AXIBusECMVIO2/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+
+
+ CddEmmDomain40
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain40
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain40/CddEmmAddressToSaveErrorStatus
+ 1342177444
+
+
+
+
+ CddEmmBit0CPGCBFUSAGsxFreqErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain40/CddEmmBit0CPGCBFUSAGsxFreqErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain40/CddEmmBit0CPGCBFUSAGsxFreqErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain40/CddEmmBit0CPGCBFUSAGsxFreqErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit1CPGCBFUSARTckmrtFreqErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain40/CddEmmBit1CPGCBFUSARTckmrtFreqErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain40/CddEmmBit1CPGCBFUSARTckmrtFreqErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain40/CddEmmBit1CPGCBFUSARTckmrtFreqErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit2CPGCBFUSARTckmrtFreqErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain40/CddEmmBit2CPGCBFUSARTckmrtFreqErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain40/CddEmmBit2CPGCBFUSARTckmrtFreqErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain40/CddEmmBit2CPGCBFUSARTckmrtFreqErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit3CPGCBFUSAPeripheralFreqErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain40/CddEmmBit3CPGCBFUSAPeripheralFreqErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain40/CddEmmBit3CPGCBFUSAPeripheralFreqErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain40/CddEmmBit3CPGCBFUSAPeripheralFreqErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit4CPGCBFUSAHscFreqErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain40/CddEmmBit4CPGCBFUSAHscFreqErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain40/CddEmmBit4CPGCBFUSAHscFreqErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain40/CddEmmBit4CPGCBFUSAHscFreqErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit5CPGCBFUSAVioFreqErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain40/CddEmmBit5CPGCBFUSAVioFreqErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain40/CddEmmBit5CPGCBFUSAVioFreqErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain40/CddEmmBit5CPGCBFUSAVioFreqErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit6CPGCBFUSAVcFreqErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain40/CddEmmBit6CPGCBFUSAVcFreqErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain40/CddEmmBit6CPGCBFUSAVcFreqErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain40/CddEmmBit6CPGCBFUSAVcFreqErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit7CPGCBFUSAVipFreqErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain40/CddEmmBit7CPGCBFUSAVipFreqErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain40/CddEmmBit7CPGCBFUSAVipFreqErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain40/CddEmmBit7CPGCBFUSAVipFreqErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit8CPGCBFUSAIMPckmirFreqErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain40/CddEmmBit8CPGCBFUSAIMPckmirFreqErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain40/CddEmmBit8CPGCBFUSAIMPckmirFreqErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain40/CddEmmBit8CPGCBFUSAIMPckmirFreqErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit9CPGIMPckmcnrFreqErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain40/CddEmmBit9CPGIMPckmcnrFreqErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain40/CddEmmBit9CPGIMPckmcnrFreqErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain40/CddEmmBit9CPGIMPckmcnrFreqErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit10CPGCBFUSAIMPckmcnrFreqErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain40/CddEmmBit10CPGCBFUSAIMPckmcnrFreqErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain40/CddEmmBit10CPGCBFUSAIMPckmcnrFreqErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain40/CddEmmBit10CPGCBFUSAIMPckmcnrFreqErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit11CPGCBFUSAIMPckmdspFreqErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain40/CddEmmBit11CPGCBFUSAIMPckmdspFreqErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain40/CddEmmBit11CPGCBFUSAIMPckmdspFreqErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain40/CddEmmBit11CPGCBFUSAIMPckmdspFreqErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit12CPGCBFUSAIMPckmdspFreqErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain40/CddEmmBit12CPGCBFUSAIMPckmdspFreqErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain40/CddEmmBit12CPGCBFUSAIMPckmdspFreqErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain40/CddEmmBit12CPGCBFUSAIMPckmdspFreqErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit13CPGLCBFUSAMMFreqErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain40/CddEmmBit13CPGLCBFUSAMMFreqErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain40/CddEmmBit13CPGLCBFUSAMMFreqErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain40/CddEmmBit13CPGLCBFUSAMMFreqErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit14CPGLCBFUSASlAccessBusFreqErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain40/CddEmmBit14CPGLCBFUSASlAccessBusFreqErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain40/CddEmmBit14CPGLCBFUSASlAccessBusFreqErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain40/CddEmmBit14CPGLCBFUSASlAccessBusFreqErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit18EtherTSNRxDataSRAMEDCErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain40/CddEmmBit18EtherTSNRxDataSRAMEDCErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain40/CddEmmBit18EtherTSNRxDataSRAMEDCErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain40/CddEmmBit18EtherTSNRxDataSRAMEDCErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit19EtherTSNRxCtrlSRAMEDCErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain40/CddEmmBit19EtherTSNRxCtrlSRAMEDCErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain40/CddEmmBit19EtherTSNRxCtrlSRAMEDCErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain40/CddEmmBit19EtherTSNRxCtrlSRAMEDCErr/CddEmmErrorSignalTarget
+ INTC
+
+
+
+
+ CddEmmBit20EtherTSNTxDataSRAMEDCErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain40/CddEmmBit20EtherTSNTxDataSRAMEDCErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain40/CddEmmBit20EtherTSNTxDataSRAMEDCErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain40/CddEmmBit20EtherTSNTxDataSRAMEDCErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit21EtherTSNTxCtrlSRAMEDCErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain40/CddEmmBit21EtherTSNTxCtrlSRAMEDCErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain40/CddEmmBit21EtherTSNTxCtrlSRAMEDCErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain40/CddEmmBit21EtherTSNTxCtrlSRAMEDCErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit22EtherTSNTASCtrlListSRAMEDCErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain40/CddEmmBit22EtherTSNTASCtrlListSRAMEDCErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain40/CddEmmBit22EtherTSNTASCtrlListSRAMEDCErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain40/CddEmmBit22EtherTSNTASCtrlListSRAMEDCErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit23EtherTSNPSFPCtrlListSRAMEDCErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain40/CddEmmBit23EtherTSNPSFPCtrlListSRAMEDCErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain40/CddEmmBit23EtherTSNPSFPCtrlListSRAMEDCErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain40/CddEmmBit23EtherTSNPSFPCtrlListSRAMEDCErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit24EtherTSNRxDescriptionrAdrrSRAMEDCErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain40/CddEmmBit24EtherTSNRxDescriptionrAdrrSRAMEDCErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain40/CddEmmBit24EtherTSNRxDescriptionrAdrrSRAMEDCErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain40/CddEmmBit24EtherTSNRxDescriptionrAdrrSRAMEDCErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit25EtherTSNTxDescriptionrAdrrSRAMEDCErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain40/CddEmmBit25EtherTSNTxDescriptionrAdrrSRAMEDCErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain40/CddEmmBit25EtherTSNTxDescriptionrAdrrSRAMEDCErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain40/CddEmmBit25EtherTSNTxDescriptionrAdrrSRAMEDCErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit26EtherTSNTxBufferAdrrSRAMEDCErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain40/CddEmmBit26EtherTSNTxBufferAdrrSRAMEDCErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain40/CddEmmBit26EtherTSNTxBufferAdrrSRAMEDCErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain40/CddEmmBit26EtherTSNTxBufferAdrrSRAMEDCErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit27EtherTSNRxEFrameBufferAdrrSRAMEDCErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain40/CddEmmBit27EtherTSNRxEFrameBufferAdrrSRAMEDCErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain40/CddEmmBit27EtherTSNRxEFrameBufferAdrrSRAMEDCErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain40/CddEmmBit27EtherTSNRxEFrameBufferAdrrSRAMEDCErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit28EtherTSNRxPFrameBufferAdrrSRAMEDCErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain40/CddEmmBit28EtherTSNRxPFrameBufferAdrrSRAMEDCErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain40/CddEmmBit28EtherTSNRxPFrameBufferAdrrSRAMEDCErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain40/CddEmmBit28EtherTSNRxPFrameBufferAdrrSRAMEDCErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+
+
+ CddEmmDomain41
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain41
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain41/CddEmmAddressToSaveErrorStatus
+ 1342177448
+
+
+
+
+ CddEmmBit0PAPeccErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain41/CddEmmBit0PAPeccErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain41/CddEmmBit0PAPeccErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain41/CddEmmBit0PAPeccErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit1PAPedcErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain41/CddEmmBit1PAPedcErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain41/CddEmmBit1PAPedcErr/CddEmmErrorSignalEnable
+ false
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain41/CddEmmBit1PAPedcErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit3PAPSDMACedcErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain41/CddEmmBit3PAPSDMACedcErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain41/CddEmmBit3PAPSDMACedcErr/CddEmmErrorSignalEnable
+ false
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain41/CddEmmBit3PAPSDMACedcErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit4OTPFfDClsApbRedundantComparatorComparisonErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain41/CddEmmBit4OTPFfDClsApbRedundantComparatorComparisonErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain41/CddEmmBit4OTPFfDClsApbRedundantComparatorComparisonErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain41/CddEmmBit4OTPFfDClsApbRedundantComparatorComparisonErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit5OTPEcc1bitCorrectedErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain41/CddEmmBit5OTPEcc1bitCorrectedErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain41/CddEmmBit5OTPEcc1bitCorrectedErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain41/CddEmmBit5OTPEcc1bitCorrectedErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit6OTPEccMultibitUncorrectedErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain41/CddEmmBit6OTPEccMultibitUncorrectedErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain41/CddEmmBit6OTPEccMultibitUncorrectedErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain41/CddEmmBit6OTPEccMultibitUncorrectedErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit7OTPTMRTripleModularRedundancy1bitCorrectedErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain41/CddEmmBit7OTPTMRTripleModularRedundancy1bitCorrectedErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain41/CddEmmBit7OTPTMRTripleModularRedundancy1bitCorrectedErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain41/CddEmmBit7OTPTMRTripleModularRedundancy1bitCorrectedErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit8OTPRedundantComparatorComparisonErr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain41/CddEmmBit8OTPRedundantComparatorComparisonErr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain41/CddEmmBit8OTPRedundantComparatorComparisonErr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain41/CddEmmBit8OTPRedundantComparatorComparisonErr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit9VDSPA2arbIntreqEcm
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain41/CddEmmBit9VDSPA2arbIntreqEcm
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain41/CddEmmBit9VDSPA2arbIntreqEcm/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain41/CddEmmBit9VDSPA2arbIntreqEcm/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit10VDSP0ErrreqCorepmssUncorr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain41/CddEmmBit10VDSP0ErrreqCorepmssUncorr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain41/CddEmmBit10VDSP0ErrreqCorepmssUncorr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain41/CddEmmBit10VDSP0ErrreqCorepmssUncorr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit11VDSP0ErrreqCorepmssCorr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain41/CddEmmBit11VDSP0ErrreqCorepmssCorr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain41/CddEmmBit11VDSP0ErrreqCorepmssCorr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain41/CddEmmBit11VDSP0ErrreqCorepmssCorr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit12VDSP0ErrreqDmssUncorr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain41/CddEmmBit12VDSP0ErrreqDmssUncorr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain41/CddEmmBit12VDSP0ErrreqDmssUncorr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain41/CddEmmBit12VDSP0ErrreqDmssUncorr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit13VDSP0ErrreqDmssCorr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain41/CddEmmBit13VDSP0ErrreqDmssCorr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain41/CddEmmBit13VDSP0ErrreqDmssCorr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain41/CddEmmBit13VDSP0ErrreqDmssCorr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit14VDSP0ErrreqIrrecoverable
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain41/CddEmmBit14VDSP0ErrreqIrrecoverable
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain41/CddEmmBit14VDSP0ErrreqIrrecoverable/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain41/CddEmmBit14VDSP0ErrreqIrrecoverable/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit16VDSP0ErrreqPreciseSafetyUncorr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain41/CddEmmBit16VDSP0ErrreqPreciseSafetyUncorr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain41/CddEmmBit16VDSP0ErrreqPreciseSafetyUncorr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain41/CddEmmBit16VDSP0ErrreqPreciseSafetyUncorr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit17VDSP0ErrreqEppWdogViol
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain41/CddEmmBit17VDSP0ErrreqEppWdogViol
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain41/CddEmmBit17VDSP0ErrreqEppWdogViol/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain41/CddEmmBit17VDSP0ErrreqEppWdogViol/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit18VDSP0ErrreqIopWdogViol
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain41/CddEmmBit18VDSP0ErrreqIopWdogViol
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain41/CddEmmBit18VDSP0ErrreqIopWdogViol/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain41/CddEmmBit18VDSP0ErrreqIopWdogViol/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit19VDSP0ErrreqEdpWdogViol
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain41/CddEmmBit19VDSP0ErrreqEdpWdogViol
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain41/CddEmmBit19VDSP0ErrreqEdpWdogViol/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain41/CddEmmBit19VDSP0ErrreqEdpWdogViol/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit20VDSP0ErrreqAxim0WdogViol
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain41/CddEmmBit20VDSP0ErrreqAxim0WdogViol
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain41/CddEmmBit20VDSP0ErrreqAxim0WdogViol/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain41/CddEmmBit20VDSP0ErrreqAxim0WdogViol/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit21VDSP0ErrreqSysWdInt
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain41/CddEmmBit21VDSP0ErrreqSysWdInt
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain41/CddEmmBit21VDSP0ErrreqSysWdInt/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain41/CddEmmBit21VDSP0ErrreqSysWdInt/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit22VDSP0ErrreqIcuWdogViol
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain41/CddEmmBit22VDSP0ErrreqIcuWdogViol
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain41/CddEmmBit22VDSP0ErrreqIcuWdogViol/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain41/CddEmmBit22VDSP0ErrreqIcuWdogViol/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit23VDSP1ErrreqCorepmssUncorr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain41/CddEmmBit23VDSP1ErrreqCorepmssUncorr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain41/CddEmmBit23VDSP1ErrreqCorepmssUncorr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain41/CddEmmBit23VDSP1ErrreqCorepmssUncorr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit24VDSP1ErrreqCorepmssCorr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain41/CddEmmBit24VDSP1ErrreqCorepmssCorr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain41/CddEmmBit24VDSP1ErrreqCorepmssCorr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain41/CddEmmBit24VDSP1ErrreqCorepmssCorr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit25VDSP1ErrreqDmssUncorr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain41/CddEmmBit25VDSP1ErrreqDmssUncorr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain41/CddEmmBit25VDSP1ErrreqDmssUncorr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain41/CddEmmBit25VDSP1ErrreqDmssUncorr/CddEmmErrorSignalTarget
+ INTC
+
+
+
+
+ CddEmmBit26VDSP1ErrreqDmssCorr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain41/CddEmmBit26VDSP1ErrreqDmssCorr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain41/CddEmmBit26VDSP1ErrreqDmssCorr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain41/CddEmmBit26VDSP1ErrreqDmssCorr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit27VDSP1ErrreqIrrecoverable
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain41/CddEmmBit27VDSP1ErrreqIrrecoverable
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain41/CddEmmBit27VDSP1ErrreqIrrecoverable/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain41/CddEmmBit27VDSP1ErrreqIrrecoverable/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit29VDSP1ErrreqPreciseSafetyUncorr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain41/CddEmmBit29VDSP1ErrreqPreciseSafetyUncorr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain41/CddEmmBit29VDSP1ErrreqPreciseSafetyUncorr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain41/CddEmmBit29VDSP1ErrreqPreciseSafetyUncorr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit30VDSP1ErrreqEppWdogviol
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain41/CddEmmBit30VDSP1ErrreqEppWdogviol
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain41/CddEmmBit30VDSP1ErrreqEppWdogviol/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain41/CddEmmBit30VDSP1ErrreqEppWdogviol/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit31VDSP1ErrreqIopWdogviol
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain41/CddEmmBit31VDSP1ErrreqIopWdogviol
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain41/CddEmmBit31VDSP1ErrreqIopWdogviol/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain41/CddEmmBit31VDSP1ErrreqIopWdogviol/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+
+
+ CddEmmDomain42
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain42
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain42/CddEmmAddressToSaveErrorStatus
+ 1342177452
+
+
+
+
+ CddEmmBit0VDSP1ErrreqEdpWdogViol
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain42/CddEmmBit0VDSP1ErrreqEdpWdogViol
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain42/CddEmmBit0VDSP1ErrreqEdpWdogViol/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain42/CddEmmBit0VDSP1ErrreqEdpWdogViol/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit1VDSP1ErrreqAxim0WdogViol
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain42/CddEmmBit1VDSP1ErrreqAxim0WdogViol
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain42/CddEmmBit1VDSP1ErrreqAxim0WdogViol/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain42/CddEmmBit1VDSP1ErrreqAxim0WdogViol/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit2VDSP1ErrreqSysWdInt
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain42/CddEmmBit2VDSP1ErrreqSysWdInt
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain42/CddEmmBit2VDSP1ErrreqSysWdInt/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain42/CddEmmBit2VDSP1ErrreqSysWdInt/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit3VDSP1ErrreqIcuWdogViol
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain42/CddEmmBit3VDSP1ErrreqIcuWdogViol
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain42/CddEmmBit3VDSP1ErrreqIcuWdogViol/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain42/CddEmmBit3VDSP1ErrreqIcuWdogViol/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit4VDSP3ErrreqCorepmssUncorr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain42/CddEmmBit4VDSP3ErrreqCorepmssUncorr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain42/CddEmmBit4VDSP3ErrreqCorepmssUncorr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain42/CddEmmBit4VDSP3ErrreqCorepmssUncorr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit5VDSP3ErrreqCorepmssCorr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain42/CddEmmBit5VDSP3ErrreqCorepmssCorr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain42/CddEmmBit5VDSP3ErrreqCorepmssCorr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain42/CddEmmBit5VDSP3ErrreqCorepmssCorr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit6VDSP3ErrreqDmssUncorr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain42/CddEmmBit6VDSP3ErrreqDmssUncorr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain42/CddEmmBit6VDSP3ErrreqDmssUncorr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain42/CddEmmBit6VDSP3ErrreqDmssUncorr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit7VDSP3ErrreqDmssCorr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain42/CddEmmBit7VDSP3ErrreqDmssCorr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain42/CddEmmBit7VDSP3ErrreqDmssCorr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain42/CddEmmBit7VDSP3ErrreqDmssCorr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit8VDSP3ErrreqIrrecoverable
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain42/CddEmmBit8VDSP3ErrreqIrrecoverable
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain42/CddEmmBit8VDSP3ErrreqIrrecoverable/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain42/CddEmmBit8VDSP3ErrreqIrrecoverable/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit10VDSP2ErrreqPreciseSafetyUncorr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain42/CddEmmBit10VDSP2ErrreqPreciseSafetyUncorr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain42/CddEmmBit10VDSP2ErrreqPreciseSafetyUncorr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain42/CddEmmBit10VDSP2ErrreqPreciseSafetyUncorr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit11VDSP2ErrreqEppWdogViol
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain42/CddEmmBit11VDSP2ErrreqEppWdogViol
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain42/CddEmmBit11VDSP2ErrreqEppWdogViol/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain42/CddEmmBit11VDSP2ErrreqEppWdogViol/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit12VDSP2ErrreqIopWdogViol
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain42/CddEmmBit12VDSP2ErrreqIopWdogViol
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain42/CddEmmBit12VDSP2ErrreqIopWdogViol/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain42/CddEmmBit12VDSP2ErrreqIopWdogViol/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit13VDSP2ErrreqEdpWdogViol
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain42/CddEmmBit13VDSP2ErrreqEdpWdogViol
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain42/CddEmmBit13VDSP2ErrreqEdpWdogViol/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain42/CddEmmBit13VDSP2ErrreqEdpWdogViol/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit14VDSP2ErrreqAxim0WdogViol
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain42/CddEmmBit14VDSP2ErrreqAxim0WdogViol
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain42/CddEmmBit14VDSP2ErrreqAxim0WdogViol/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain42/CddEmmBit14VDSP2ErrreqAxim0WdogViol/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit15VDSP2ErrreqSysWdInt
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain42/CddEmmBit15VDSP2ErrreqSysWdInt
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain42/CddEmmBit15VDSP2ErrreqSysWdInt/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain42/CddEmmBit15VDSP2ErrreqSysWdInt/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit16VDSP2ErrreqIcuWdogViol
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain42/CddEmmBit16VDSP2ErrreqIcuWdogViol
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain42/CddEmmBit16VDSP2ErrreqIcuWdogViol/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain42/CddEmmBit16VDSP2ErrreqIcuWdogViol/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit17VDSP3ErrreqCorepmssUncorr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain42/CddEmmBit17VDSP3ErrreqCorepmssUncorr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain42/CddEmmBit17VDSP3ErrreqCorepmssUncorr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain42/CddEmmBit17VDSP3ErrreqCorepmssUncorr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit18VDSP3ErrreqCorepmssCorr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain42/CddEmmBit18VDSP3ErrreqCorepmssCorr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain42/CddEmmBit18VDSP3ErrreqCorepmssCorr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain42/CddEmmBit18VDSP3ErrreqCorepmssCorr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit19VDSP3ErrreqDmssUncorr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain42/CddEmmBit19VDSP3ErrreqDmssUncorr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain42/CddEmmBit19VDSP3ErrreqDmssUncorr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain42/CddEmmBit19VDSP3ErrreqDmssUncorr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit20VDSP3ErrreqDmssCorr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain42/CddEmmBit20VDSP3ErrreqDmssCorr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain42/CddEmmBit20VDSP3ErrreqDmssCorr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain42/CddEmmBit20VDSP3ErrreqDmssCorr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit21VDSP3ErrreqIrrecoverable
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain42/CddEmmBit21VDSP3ErrreqIrrecoverable
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain42/CddEmmBit21VDSP3ErrreqIrrecoverable/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain42/CddEmmBit21VDSP3ErrreqIrrecoverable/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit23VDSP3ErrreqPreciseSafetyUncorr
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain42/CddEmmBit23VDSP3ErrreqPreciseSafetyUncorr
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain42/CddEmmBit23VDSP3ErrreqPreciseSafetyUncorr/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain42/CddEmmBit23VDSP3ErrreqPreciseSafetyUncorr/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit24VDSP3ErrreqEppWdogViol
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain42/CddEmmBit24VDSP3ErrreqEppWdogViol
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain42/CddEmmBit24VDSP3ErrreqEppWdogViol/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain42/CddEmmBit24VDSP3ErrreqEppWdogViol/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit25VDSP3ErrreqIopWdogViol
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain42/CddEmmBit25VDSP3ErrreqIopWdogViol
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain42/CddEmmBit25VDSP3ErrreqIopWdogViol/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain42/CddEmmBit25VDSP3ErrreqIopWdogViol/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit26VDSP3ErrreqEdpWdogViol
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain42/CddEmmBit26VDSP3ErrreqEdpWdogViol
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain42/CddEmmBit26VDSP3ErrreqEdpWdogViol/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain42/CddEmmBit26VDSP3ErrreqEdpWdogViol/CddEmmErrorSignalTarget
+ INTC
+
+
+
+
+ CddEmmBit27VDSP3ErrreqAxim0WdogViol
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain42/CddEmmBit27VDSP3ErrreqAxim0WdogViol
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain42/CddEmmBit27VDSP3ErrreqAxim0WdogViol/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain42/CddEmmBit27VDSP3ErrreqAxim0WdogViol/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit28VDSP3ErrreqSysWdInt
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain42/CddEmmBit28VDSP3ErrreqSysWdInt
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain42/CddEmmBit28VDSP3ErrreqSysWdInt/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain42/CddEmmBit28VDSP3ErrreqSysWdInt/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+ CddEmmBit29VDSP3ErrreqIcuWdogViol
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain42/CddEmmBit29VDSP3ErrreqIcuWdogViol
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain42/CddEmmBit29VDSP3ErrreqIcuWdogViol/CddEmmErrorSignalEnable
+ true
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDomain42/CddEmmBit29VDSP3ErrreqIcuWdogViol/CddEmmErrorSignalTarget
+ ERROROUT
+
+
+
+
+
+
+ CddEmmDemEventParameterRefs
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDemEventParameterRefs
- /Renesas/EcucDefs_CddIccom/Cdd/CddIccomChannel/CddIccomChannelTimeoutCounterRef
- /ActiveEcuC/Os/OsCounter
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDemEventParameterRefs/CDDEMM_E_INTERRUPT_CONTROLLER_FAILURE
+ /ActiveEcuC/Dem/DemConfigSet/CDDEMM_E_INTERRUPT_CONTROLLER_FAILURE
+
+
+ /Renesas/EcucDefs_CddEmm/Cdd/CddEmmDemEventParameterRefs/CDDEMM_E_WRITE_VERIFY_FAILURE
+ /ActiveEcuC/Dem/DemConfigSet/CDDEMM_E_WRITE_VERIFY_FAILURE
diff --git a/Src/Gen4_R-Car_Vector/2_Trunk/Mobis_V4H/Project_Folder/Surface_EVB/Surface_EVB.dpa b/Src/Gen4_R-Car_Vector/2_Trunk/Mobis_V4H/Project_Folder/Surface_EVB/Surface_EVB.dpa
index dfae65e4..895f853f 100644
--- a/Src/Gen4_R-Car_Vector/2_Trunk/Mobis_V4H/Project_Folder/Surface_EVB/Surface_EVB.dpa
+++ b/Src/Gen4_R-Car_Vector/2_Trunk/Mobis_V4H/Project_Folder/Surface_EVB/Surface_EVB.dpa
@@ -52,9 +52,6 @@
-
-
-
@@ -79,6 +76,9 @@
+
+
+
false
true
diff --git a/Src/Gen4_R-Car_Vector/2_Trunk/Mobis_V4H/Project_Folder/Surface_EVB/Surface_EVB.solun.silent.dcusr b/Src/Gen4_R-Car_Vector/2_Trunk/Mobis_V4H/Project_Folder/Surface_EVB/Surface_EVB.solun.silent.dcusr
index 63cbebd8..484f333a 100644
--- a/Src/Gen4_R-Car_Vector/2_Trunk/Mobis_V4H/Project_Folder/Surface_EVB/Surface_EVB.solun.silent.dcusr
+++ b/Src/Gen4_R-Car_Vector/2_Trunk/Mobis_V4H/Project_Folder/Surface_EVB/Surface_EVB.solun.silent.dcusr
@@ -140,8 +140,8 @@
-
-
+
+
@@ -310,5 +310,15 @@
+
+
+
+
+
+
+
+
+
+