woody/Work
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

add

Browse Source
This commit is contained in:
woody
2026-06-19 21:13:06 +09:00
parent c7342a414c
commit 883241097f
161 changed files with 37562 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

17
Src/0_Tool/FW_Write/Customer/Mobis/FW_Update방법.txt Normal file
View File

@@ -0,0 +1,17 @@
1. Blank IC <20><><EFBFBD>¿<EFBFBD><C2BF><EFBFBD> F/W Update
20251016 <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> Flash_Bootloader_PRK3.ttl<74><6C> <20><><EFBFBD><EFBFBD> <20>̶<EFBFBD> <20>߰<EFBFBD><DFB0><EFBFBD> "setbaud 115200" <20><><EFBFBD><EFBFBD><EFBFBD>ϸ<EFBFBD> <20>ȵ<EFBFBD>.
<09><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> "setbaud 115200" <20><><EFBFBD><EFBFBD><EFBFBD>ϴ<EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD>ߴµ<DFB4>, F/W <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ʈ <20><> <20>ȵǾ Test <20><><EFBFBD><EFBFBD>
10<EFBFBD><EFBFBD> <20><><EFBFBD>忡<EFBFBD><E5BFA1><EFBFBD><EFBFBD>
<EFBFBD><EFBFBD><EFBFBD>۸<EFBFBD> <20>ѵ<EFBFBD>(2,5)
FT4222<EFBFBD><EFBFBD> USB<53><42> <20><><EFBFBD><EFBFBD><EFBFBD>ϸ<EFBFBD> SCIF <20><><EFBFBD>尡 <20>ƴ<EFBFBD> Nomal <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD>̵<EFBFBD>.
<EFBFBD><EFBFBD> <20>Ʒ<EFBFBD> <20><><EFBFBD>忡<EFBFBD><E5BFA1><EFBFBD><EFBFBD> Flash_Bootloader_PRK3.ttl<74><6C> <20>̿<EFBFBD><CCBF>ؼ<EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ʈ
2. IPL Update.
Flash_IPL_PRK3.ttl<74><6C> <20>̿<EFBFBD><CCBF>ؼ<EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ʈ
3. MCU Update.
<EFBFBD><EFBFBD><EFBFBD><EFBFBD>
10<EFBFBD><EFBFBD> <20><><EFBFBD>忡<EFBFBD><E5BFA1> Debug <20><><EFBFBD>忡 <20><><EFBFBD><EFBFBD> <20>߿<EFBFBD><DFBF> Write<74>ɶ<EFBFBD><C9B6><EFBFBD> <20>ְ<EFBFBD> <20>ȵ<EFBFBD> <20><><EFBFBD><EFBFBD> <20>ִ<EFBFBD>.

646
Src/0_Tool/Gen4_R-Car_IPL/SDK/v3_46_0/Gen4_ICUMX_Loader/Makefile Normal file
View File

@@ -0,0 +1,646 @@
#/*******************************************************************************
# * DISCLAIMER
# * This software is supplied by Renesas Electronics Corporation and is only
# * intended for use with Renesas products. No other uses are authorized. This
# * software is owned by Renesas Electronics Corporation and is protected under
# * all applicable laws, including copyright laws.
# * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
# * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
# * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
# * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
# * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
# * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
# * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
# * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
# * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
# * Renesas reserves the right, without notice, to make changes to this software
# * and to discontinue the availability of this software. By using this software,
# * you agree to the additional terms and conditions found by accessing the
# * following link:
# * http://www.renesas.com/disclaimer
# * Copyright 2022-2025 Renesas Electronics Corporation All rights reserved.
# *******************************************************************************/
#
# *******************************************************************************
# * DESCRIPTION : makefile for Loader
# ******************************************************************************
define add_define
DEFINES += -D$(1)$(if $(value $(1)),=$(value $(1)),)
endef
INCLUDE_DIR = -Iinclude \
-Iip/ddr
OUTDIR := build
# LSI setting common define
RCAR_S4 := 0
RCAR_V4H := 1
RCAR_V4M := 2
$(eval $(call add_define,RCAR_S4))
$(eval $(call add_define,RCAR_V4H))
$(eval $(call add_define,RCAR_V4M))
#/* Select LSI("S4" or "V4H" or "V4M" )********************************
ifeq ("$(LSI)", "")
LSI = S4
endif
ifeq (${LSI},S4)
RCAR_LSI:=${RCAR_S4}
DIR_NAME_SA9 = s4
OBJ_FILE += loader/loader_main_s4.o \
cnf_tbl/cnf_tbl_s4.o \
ip/qos/qos.o \
ip/rtvram/rtvram.o \
ip/ddr/s4/lpddr4x/ecc_enable_s4.o
INCLUDE_DIR += -Imcu
include ip/ddr/ddr.mk
else ifeq (${LSI},V4H)
RCAR_LSI:=${RCAR_V4H}
DIR_NAME_SA9 = v4h
OBJ_FILE += loader/loader_main_v4h.o \
ip/fcpr/fcpr.o \
cnf_tbl/cnf_tbl_v4h.o \
ip/ddr/v4h/lpddr5/ecc_enable_v4h.o \
ip/ddr/v4h/lpddr5/ecm_enable_v4h.o
else ifeq (${LSI},V4M)
RCAR_LSI:=${RCAR_V4M}
DIR_NAME_SA9 = v4m
OBJ_FILE += loader/loader_main_v4m.o \
ip/fcpr/fcpr.o \
cnf_tbl/cnf_tbl_v4m.o \
ip/sysc/sysc.o \
ip/avs/avs.o \
ip/i2c/i2c.o \
ip/ddr/v4m/lpddr5/ecc_enable_v4m.o \
ip/ddr/v4m/lpddr5/ecm_enable_v4m.o
else
$(error "Error: ${LSI} is not supported.")
endif
$(eval $(call add_define,RCAR_LSI))
#output file name
FILE_NAME = icumx_loader
FILE_NAME_SA0 = bootparam_sa0
FILE_NAME_SA9 = cert_header_sa9
FILE_NAME_TFMV_TBL = tfmv_ver_tbl
FILE_NAME_NTFMV_TBL = ntfmv_ver_tbl
OUTPUT_FILE = $(FILE_NAME).elf
OUTPUT_FILE_SA0 = $(FILE_NAME_SA0).elf
OUTPUT_FILE_SA9 = $(FILE_NAME_SA9).elf
OUTPUT_FILE_TFMV_TBL = $(FILE_NAME_TFMV_TBL).elf
OUTPUT_FILE_NTFMV_TBL = $(FILE_NAME_NTFMV_TBL).elf
#object file name
OBJ_FILE += cpu_on/cpu_on.o \
common/log/log.o \
common/log/scif.o \
common/timer/micro_wait.o \
image_load/image_load.o \
intc/intc.o \
intc/vecttbl.o \
intc/vect_set.o \
ip/ip_control.o \
ip/cpg/cpg.o \
ip/emmc/emmc_boot.o \
ip/wdt/wdt.o \
loader/loader.o \
loader/loader_main_common.o \
protect/ram_protection.o \
protect/region_id.o \
protect/stack_protect.o \
remap/remap.o \
rom_api/rom_api.o
OBJ_FILE_SA0 = tools/dummy_create/sa0.o
OBJ_FILE_SA9 = tools/dummy_create/$(DIR_NAME_SA9)/sa9.o
OBJ_FILE_TFMV_TBL = tools/sw_min_ver_tbl/tfmv_ver_tbl.o
OBJ_FILE_NTFMV_TBL = tools/sw_min_ver_tbl/ntfmv_ver_tbl.o
#linker script name
ifeq (${LSI},V4M)
MEMORY_DEF = loader/icumx_loader_v4m.ld
else
MEMORY_DEF = loader/icumx_loader.ld
endif
MEMORY_DEF_SA0 = tools/dummy_create/sa0.ld
MEMORY_DEF_SA9 = tools/dummy_create/$(DIR_NAME_SA9)/sa9.ld
MEMORY_DEF_TFMV_TBL = tools/sw_min_ver_tbl/tfmv_ver_tbl.ld
MEMORY_DEF_NTFMV_TBL = tools/sw_min_ver_tbl/ntfmv_ver_tbl.ld
###################################################
# Debug build
DEBUG:=0
# Process DEBUG flag
$(eval $(call assert_boolean,DEBUG))
$(eval $(call add_define,DEBUG))
ifeq (${DEBUG},0)
$(eval $(call add_define,NDEBUG))
CFLAGS += -Onone
else
ASFLAGS += -G -dwarf2
CFLAGS += -G -dwarf2 -Odebug
endif
# MISRA Option
#------ MISRA ------
ifndef MISRA
MISRA := MANDATORY
endif
ifeq ("$(MISRA)", "DISABLE")
MISRA_OPTION = DISABLE
else ifeq ("$(MISRA)", "FULL")
MISRA_OPTION = FULL
else ifeq ("$(MISRA)", "MANDATORY")
MISRA_OPTION = MANDATORY
else ifeq ("$(MISRA)", "REQUIRED")
MISRA_OPTION = REQUIRED
endif
CFLAGS_MISRA_FULL = \
--misra_adv=warn \
--misra_req=warn \
--misra_mand=warn \
--no_misra_runtime \
--misra_2012=all,-R1.1 # MISRA 2012 Rule 1.1 not allowed with non-strict -c99 or later
CFLAGS_MISRA_REQUIRED = \
--misra_adv=silent \
--misra_req=warn \
--misra_mand=warn \
--no_misra_runtime \
--misra_2012=all,-R1.1 # MISRA 2012 Rule 1.1 not allowed with non-strict -c99 or later
CFLAGS_MISRA_MANDATORY = \
--misra_adv=silent \
--misra_req=silent \
--misra_mand=warn \
--no_misra_runtime \
--misra_2012=all,-R1.1,-R3.1 # MISRA 2012 Rule 1.1 not allowed with non-strict -c99 or later
# MISRA 2012 Rule 3.1 is confirmed with static analysis
ifeq ("$(MISRA_OPTION)", "FULL")
CFLAGS += $(CFLAGS_MISRA_FULL)
else ifeq ("$(MISRA)", "REQUIRED")
CFLAGS += $(CFLAGS_MISRA_REQUIRED)
else ifeq ("$(MISRA)", "MANDATORY")
CFLAGS += $(CFLAGS_MISRA_MANDATORY)
endif
# Process LOG_LEVEL
ifndef LOG_LEVEL
LOG_LEVEL := 2
endif
$(eval $(call add_define,LOG_LEVEL))
ifeq (${LOG_LEVEL},0)
LDFLAGS += -nostdlib
endif
# Process SET_FCPR_PARAM flag
# 0:Disable, 1:Enable (Support V4H / V4M Linux OS)
ifeq ($(filter ${LSI},V4H V4M),${LSI})
ifndef SET_FCPR_PARAM
SET_FCPR_PARAM := 0
$(eval $(call add_define,SET_FCPR_PARAM))
else
ifeq (${SET_FCPR_PARAM},0)
$(eval $(call add_define,SET_FCPR_PARAM))
else ifeq (${SET_FCPR_PARAM},1)
$(eval $(call add_define,SET_FCPR_PARAM))
else
$(error "Error:SET_FCPR_PARAM=${SET_FCPR_PARAM} is not supported.")
endif
endif
else
SET_FCPR_PARAM := 0
$(eval $(call add_define,SET_FCPR_PARAM))
endif
# Process BOOT_MCU flag (S4 only)
# 0:None, 1:G4MH, 2:Reserved, 3:G4MH+ICUMH
ifeq (${LSI},S4)
ifndef BOOT_MCU
BOOT_MCU :=3
$(eval $(call add_define,BOOT_MCU))
else
ifeq (${BOOT_MCU},0)
$(eval $(call add_define,BOOT_MCU))
else ifeq (${BOOT_MCU},1)
$(eval $(call add_define,BOOT_MCU))
else ifeq (${BOOT_MCU},2)
$(eval $(call add_define,BOOT_MCU))
else ifeq (${BOOT_MCU},3)
$(eval $(call add_define,BOOT_MCU))
else
$(error "Error:BOOT_MCU=${BOOT_MCU} is not supported.")
endif
endif
else
BOOT_MCU :=0
$(eval $(call add_define,BOOT_MCU))
endif
ifneq (${BOOT_MCU},0)
OBJ_FILE += mcu/cpu_on_for_mcu.o \
mcu/sdmac.o \
mcu/loader_main_mcu.o \
mcu/image_load_for_mcu.o \
mcu/codesram_ecc.o
endif
# Process RTVRAM_EXTEND flag
ifeq (${LSI},S4)
ifndef RTVRAM_EXTEND
RTVRAM_EXTEND := 1
$(eval $(call add_define,RTVRAM_EXTEND))
else
ifeq (${RTVRAM_EXTEND},0)
$(eval $(call add_define,RTVRAM_EXTEND))
else ifeq (${RTVRAM_EXTEND},1)
$(eval $(call add_define,RTVRAM_EXTEND))
else
$(error "Error:RTVRAM_EXTEND=${RTVRAM_EXTEND} is not supported.")
endif
endif
endif
# Process QSPI_DDR_MODE flag
# 0:SDR, 1:DDR
ifndef QSPI_DDR_MODE
QSPI_DDR_MODE := 0
$(eval $(call add_define,QSPI_DDR_MODE))
else
ifeq (${QSPI_DDR_MODE},0)
$(eval $(call add_define,QSPI_DDR_MODE))
else ifeq (${QSPI_DDR_MODE},1)
$(eval $(call add_define,QSPI_DDR_MODE))
else
$(error "Error:QSPI_DDR_MODE=${QSPI_DDR_MODE} is not supported.")
endif
endif
# RCAR_QSPI_DDR_DUMMY_CYCLE
ifndef RCAR_QSPI_DDR_DUMMY_CYCLE
RCAR_QSPI_DDR_DUMMY_CYCLE := 9
endif
$(eval $(call add_define,RCAR_QSPI_DDR_DUMMY_CYCLE))
# Process RCAR_SA9_TYPE flag
# 0:Flash, 1:eMMC
ifeq (${LSI},S4)
ifndef RCAR_SA9_TYPE
RCAR_SA9_TYPE := 0
$(eval $(call add_define,RCAR_SA9_TYPE))
else
ifeq (${RCAR_SA9_TYPE},0)
$(eval $(call add_define,RCAR_SA9_TYPE))
else ifeq (${RCAR_SA9_TYPE},1)
$(eval $(call add_define,RCAR_SA9_TYPE))
else
$(error "Error:RCAR_SA9_TYPE=${RCAR_SA9_TYPE} is not supported.")
endif
endif
else ifeq ($(filter ${LSI},V4H V4M),${LSI})
RCAR_SA9_TYPE := 0
$(eval $(call add_define,RCAR_SA9_TYPE))
endif
ifeq (${RCAR_SA9_TYPE},1)
OBJ_FILE += image_load/image_load_emmc.o \
ip/emmc/emmc_cmd.o \
ip/emmc/emmc_init.o \
ip/emmc/emmc_interrupt.o \
ip/emmc/emmc_mount.o \
ip/emmc/emmc_multiboot.o \
ip/emmc/emmc_read.o \
ip/emmc/emmc_utility.o
else ifeq (${RCAR_SA9_TYPE},0)
OBJ_FILE += image_load/image_load_flash.o \
ip/dma/dma.o \
ip/rpc/rpc.o \
ip/mfis/mfis.o
endif
# Process CA_LOAD_TYPE flag
# 0:CA Loader 1:BL31 (or Secure Monitor)
ifeq (${LSI},S4)
ifndef CA_LOAD_TYPE
CA_LOAD_TYPE := 0
$(eval $(call add_define,CA_LOAD_TYPE))
else
ifeq (${CA_LOAD_TYPE},0)
$(eval $(call add_define,CA_LOAD_TYPE))
else ifeq (${CA_LOAD_TYPE},1)
$(eval $(call add_define,CA_LOAD_TYPE))
else
$(error "Error:CA_LOAD_TYPE=${CA_LOAD_TYPE} is not supported.")
endif
endif
else ifeq ($(filter ${LSI},V4H V4M),${LSI})
CA_LOAD_TYPE := 0
$(eval $(call add_define,CA_LOAD_TYPE))
endif
ifeq (${RCAR_SA9_TYPE},1)
ifeq (${CA_LOAD_TYPE},0)
$(error "Error:RCAR_SA9_TYPE=1 and CA_LOAD_TYPE=0 is not supported.")
endif
endif
# Process MCU_SECURE_BOOT flag (S4 only)
ifndef MCU_SECURE_BOOT
MCU_SECURE_BOOT := 0
$(eval $(call add_define,MCU_SECURE_BOOT))
else
ifeq (${MCU_SECURE_BOOT},0)
$(eval $(call add_define,MCU_SECURE_BOOT))
else ifeq (${MCU_SECURE_BOOT},1)
ifeq (${BOOT_MCU},0)
$(error "Error:MCU_SECURE_BOOT=${MCU_SECURE_BOOT} and BOOT_MCU=${BOOT_MCU} is not supported.")
else
$(eval $(call add_define,MCU_SECURE_BOOT))
endif
else
$(error "Error:MCU_SECURE_BOOT=${MCU_SECURE_BOOT} is not supported.")
endif
endif
# Process SW_VERSION_CHECK flag
# 0:Disable 1:Enable
ifndef SW_VERSION_CHECK
SW_VERSION_CHECK := 0
$(eval $(call add_define,SW_VERSION_CHECK))
else
ifeq (${SW_VERSION_CHECK},0)
$(eval $(call add_define,SW_VERSION_CHECK))
else ifeq (${SW_VERSION_CHECK},1)
$(eval $(call add_define,SW_VERSION_CHECK))
else
$(error "Error:SW_VERSION_CHECK=${SW_VERSION_CHECK} is not supported.")
endif
endif
# Process access protection flag
# 0:Disable 1:Enable
ifndef ACC_PROT_ENABLE
ACC_PROT_ENABLE := 0
$(eval $(call add_define,ACC_PROT_ENABLE))
else
ifeq (${ACC_PROT_ENABLE},0)
$(eval $(call add_define,ACC_PROT_ENABLE))
else ifeq (${ACC_PROT_ENABLE},1)
$(eval $(call add_define,ACC_PROT_ENABLE))
else
$(error "Error:ACC_PROT_ENABLE=${ACC_PROT_ENABLE} is not supported.")
endif
endif
ifeq (${MCU_SECURE_BOOT},1)
include mcu_secureboot/mcu_secureboot.mk
endif
# Process ADD_HOTPLUG_MAGIC flag
ifndef ADD_HOTPLUG_MAGIC
ADD_HOTPLUG_MAGIC := 0
$(eval $(call add_define,ADD_HOTPLUG_MAGIC))
else
ifeq (${ADD_HOTPLUG_MAGIC},0)
$(eval $(call add_define,ADD_HOTPLUG_MAGIC))
else ifeq (${ADD_HOTPLUG_MAGIC},1)
$(eval $(call add_define,ADD_HOTPLUG_MAGIC))
else
$(error "Error:ADD_HOTPLUG_MAGIC=${ADD_HOTPLUG_MAGIC} is not supported.")
endif
endif
# Process STACK_PROTECT flag
ifndef STACK_PROTECT
STACK_PROTECT := 0
$(eval $(call add_define,STACK_PROTECT))
else
ifeq (${STACK_PROTECT},0)
$(eval $(call add_define,STACK_PROTECT))
else ifeq (${STACK_PROTECT},1)
$(eval $(call add_define,STACK_PROTECT))
CFLAGS += -stack_protector
else
$(error "Error:STACK_PROTECT=${STACK_PROTECT} is not supported.")
endif
endif
# Process RTOS_LOAD_NUM flag
# 1:RTOS#0 only 3:RTOS#0,#1,#2
ifndef RTOS_LOAD_NUM
RTOS_LOAD_NUM := 1
$(eval $(call add_define,RTOS_LOAD_NUM))
else
ifeq (${RTOS_LOAD_NUM},1)
$(eval $(call add_define,RTOS_LOAD_NUM))
else ifeq (${RTOS_LOAD_NUM},3)
$(eval $(call add_define,RTOS_LOAD_NUM))
else
$(error "Error:RTOS_LOAD_NUM=${RTOS_LOAD_NUM} is not supported.")
endif
endif
# Process OPTEE_LOAD_ENABLE flag
ifeq ($(filter ${LSI},V4H V4M),${LSI})
ifndef OPTEE_LOAD_ENABLE
OPTEE_LOAD_ENABLE := 1
$(eval $(call add_define,OPTEE_LOAD_ENABLE))
else
ifeq (${OPTEE_LOAD_ENABLE},0)
$(eval $(call add_define,OPTEE_LOAD_ENABLE))
else ifeq (${OPTEE_LOAD_ENABLE},1)
$(eval $(call add_define,OPTEE_LOAD_ENABLE))
else
$(error "Error:OPTEE_LOAD_ENABLE=${OPTEE_LOAD_ENABLE} is not supported.")
endif
endif
endif
###################################################
# pass SecureMonitor parametor
###################################################
# Process SET_CA_PARAM flag
ifeq (${LSI},S4)
ifndef SET_CA_PARAM
SET_CA_PARAM := 1
$(eval $(call add_define,SET_CA_PARAM))
else
ifeq (${SET_CA_PARAM},0)
$(eval $(call add_define,SET_CA_PARAM))
else ifeq (${SET_CA_PARAM},1)
$(eval $(call add_define,SET_CA_PARAM))
else
$(error "Error:SET_CA_PARAM=${SET_CA_PARAM} is not supported.")
endif
endif
endif
# Process ECM_ENABLE
ifndef ECM_ENABLE
ECM_ENABLE:= 0
$(eval $(call add_define,ECM_ENABLE))
else
ifeq (${ECM_ENABLE},0)
$(eval $(call add_define,ECM_ENABLE))
else ifeq (${ECM_ENABLE},1)
$(eval $(call add_define,ECM_ENABLE))
else
$(error "Error: ECM_ENABLE=${ECM_ENABLE} is not supported.")
endif
endif
# Process ECM_ERROR_ENABLE flag
ifndef ECM_ERROR_ENABLE
ECM_ERROR_ENABLE := 1
$(eval $(call add_define,ECM_ERROR_ENABLE))
else
ifeq (${ECM_ERROR_ENABLE},0)
$(eval $(call add_define,ECM_ERROR_ENABLE))
else ifeq (${ECM_ERROR_ENABLE},1)
$(eval $(call add_define,ECM_ERROR_ENABLE))
else
$(error "Error:ECM_ERROR_ENABLE=${ECM_ERROR_ENABLE} is not supported.")
endif
endif
# Process DBSC HUNGUP WA
ifndef WA_OTLINT5579
WA_OTLINT5579:= 1
endif
$(eval $(call add_define,WA_OTLINT5579))
###################################################
OUTDIR_REL := $(OUTDIR)/release
OUTDIR_OBJ := $(OUTDIR)/obj
OBJ_FILE := $(OBJ_FILE:%.o=$(OUTDIR_OBJ)/%.o)
OBJ_FILE_SA0 := $(OBJ_FILE_SA0:%.o=$(OUTDIR_OBJ)/%.o)
OBJ_FILE_SA9 := $(OBJ_FILE_SA9:%.o=$(OUTDIR_OBJ)/%.o)
OBJ_FILE_TFMV_TBL := $(OBJ_FILE_TFMV_TBL:%.o=$(OUTDIR_OBJ)/%.o)
OBJ_FILE_NTFMV_TBL := $(OBJ_FILE_NTFMV_TBL:%.o=$(OUTDIR_OBJ)/%.o)
CC = cxrh850
AS = cxrh850
LD = cxrh850
OC = gsrec
OD = gdump
ASFLAGS += -asm="-preprocess_assembly_files" \
-asm="-nostartfiles" \
-D__ASSEMBLY \
$(INCLUDE_DIR) $(DEFINES)
CFLAGS += -nostartfiles \
-c99 \
$(INCLUDE_DIR) $(DEFINES) \
--ghstd=last \
-Wundef \
--diag_error=193 \
--prototype_errors
# --ghstd=last : Enable Green Hills Standard Mode
# -Wundef : Output warning if there are any undefined symbols
# --diag_error=193 : Error if zero is applied to undefined symbol
# --prototype_errors : Error if there are no any prototype declaration
ifeq (${LOG_LEVEL},0)
# There are no any additional options
else
CFLAGS += --diag_suppress=1932 # There is warning that format string parameter in sprintf is not constant
endif
LDFLAGS += -nostartfiles -Mu
BUILD_MESSAGE_TIMESTAMP ?= __TIME__", "__DATE__
###################################################
.SUFFIXES : .s .c .o
###################################################
# command
.PHONY: all
all: $(OUTPUT_FILE) $(OUTPUT_FILE_SA0) $(OUTPUT_FILE_SA9) $(OUTPUT_FILE_TFMV_TBL) $(OUTPUT_FILE_NTFMV_TBL)
###################################################
# Linker
###################################################
$(OUTPUT_FILE) : $(MEMORY_DEF) $(OBJ_FILE)
@echo 'const char build_message[] = "Built : "$(BUILD_MESSAGE_TIMESTAMP);' > $(OUTDIR_OBJ)/build_message.c
@$(CC) $(CFLAGS) -o $(OUTDIR_OBJ)/build_message.o -c $(OUTDIR_OBJ)/build_message.c
@$(LD) $(OBJ_FILE) $(OUTDIR_OBJ)/build_message.o \
-T $(MEMORY_DEF) \
-o $(OUTDIR_REL)/$(OUTPUT_FILE) \
$(LDFLAGS) \
-map=$(OUTDIR_REL)/$(FILE_NAME).map
@$(OC) -S3 -bytes 16 -noS5 $(OUTDIR_REL)/$(OUTPUT_FILE) > $(OUTDIR_REL)/$(FILE_NAME).srec
@$(OD) -full -ysec $(OUTDIR_REL)/$(OUTPUT_FILE) > $(OUTDIR_REL)/$(FILE_NAME).dump
@gmemfile $(OUTDIR_REL)/$(OUTPUT_FILE) -o $(OUTDIR_REL)/$(OUTPUT_FILE:%.elf=%.bin)
$(OUTPUT_FILE_SA0) : $(MEMORY_DEF_SA0) $(OBJ_FILE_SA0)
@$(LD) $(OBJ_FILE_SA0) \
-T $(MEMORY_DEF_SA0) \
-o $(OUTDIR_REL)/$(OUTPUT_FILE_SA0) \
-map=$(OUTDIR_REL)/$(FILE_NAME_SA0).map \
-nostdlib
@$(OC) -S3 -bytes 16 -noS5 $(OUTDIR_REL)/$(OUTPUT_FILE_SA0) > $(OUTDIR_REL)/$(FILE_NAME_SA0).srec
@gmemfile $(OUTDIR_REL)/$(OUTPUT_FILE_SA0) -o $(OUTDIR_REL)/$(OUTPUT_FILE_SA0:%.elf=%.bin)
$(OUTPUT_FILE_SA9) : $(MEMORY_DEF_SA9) $(OBJ_FILE_SA9)
@$(LD) $(OBJ_FILE_SA9) \
-T $(MEMORY_DEF_SA9) \
-o $(OUTDIR_REL)/$(OUTPUT_FILE_SA9) \
-map=$(OUTDIR_REL)/$(FILE_NAME_SA9).map \
-nostdlib
@$(OC) -S3 -bytes 16 -noS5 $(OUTDIR_REL)/$(OUTPUT_FILE_SA9) > $(OUTDIR_REL)/$(FILE_NAME_SA9).srec
@gmemfile $(OUTDIR_REL)/$(OUTPUT_FILE_SA9) -o $(OUTDIR_REL)/$(OUTPUT_FILE_SA9:%.elf=%.bin)
$(OUTPUT_FILE_TFMV_TBL) : $(MEMORY_DEF_TFMV_TBL) $(OBJ_FILE_TFMV_TBL)
@$(LD) $(OBJ_FILE_TFMV_TBL) \
-T $(MEMORY_DEF_TFMV_TBL) \
-o $(OUTDIR_REL)/$(OUTPUT_FILE_TFMV_TBL) \
-map=$(OUTDIR_REL)/$(FILE_NAME_TFMV_TBL).map \
-nostdlib
@gmemfile $(OUTDIR_REL)/$(OUTPUT_FILE_TFMV_TBL) -o $(OUTDIR_REL)/$(OUTPUT_FILE_TFMV_TBL:%.elf=%.bin)
$(OUTPUT_FILE_NTFMV_TBL) : $(MEMORY_DEF_NTFMV_TBL) $(OBJ_FILE_NTFMV_TBL)
@$(LD) $(OBJ_FILE_NTFMV_TBL) \
-T $(MEMORY_DEF_NTFMV_TBL) \
-o $(OUTDIR_REL)/$(OUTPUT_FILE_NTFMV_TBL) \
-map=$(OUTDIR_REL)/$(FILE_NAME_NTFMV_TBL).map \
-nostdlib
@gmemfile $(OUTDIR_REL)/$(OUTPUT_FILE_NTFMV_TBL) -o $(OUTDIR_REL)/$(OUTPUT_FILE_NTFMV_TBL:%.elf=%.bin)
###################################################
# Compile
###################################################
$(OUTDIR_OBJ)/%.o:%.c
@if [ ! -e `dirname $@` ]; then mkdir -p `dirname $@`; fi
@$(CC) $(CFLAGS) -o $@ -c $<
$(OUTDIR_OBJ)/%.o:%.S
@if [ ! -e `dirname $@` ]; then mkdir -p `dirname $@`; fi
@$(AS) $(ASFLAGS) -o $@ -c $<
.PHONY: clean
clean:
@rm -rf $(OUTDIR)

2468
Src/0_Tool/Gen4_R-Car_IPL/SDK/v3_46_0/Gen4_ICUMX_Loader/cnf_tbl/cnf_tbl_s4.c Normal file
View File

File diff suppressed because it is too large Load Diff

4122
Src/0_Tool/Gen4_R-Car_IPL/SDK/v3_46_0/Gen4_ICUMX_Loader/cnf_tbl/cnf_tbl_v4h.c Normal file
View File

File diff suppressed because it is too large Load Diff

3585
Src/0_Tool/Gen4_R-Car_IPL/SDK/v3_46_0/Gen4_ICUMX_Loader/cnf_tbl/cnf_tbl_v4m.c Normal file
View File

File diff suppressed because it is too large Load Diff

100
Src/0_Tool/Gen4_R-Car_IPL/SDK/v3_46_0/Gen4_ICUMX_Loader/common/log/log.c Normal file
View File

@@ -0,0 +1,100 @@
/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright 2021-2023 Renesas Electronics Corporation All rights reserved.
*******************************************************************************/
/*******************************************************************************
* DESCRIPTION : Log driver
******************************************************************************/
/******************************************************************************
* @file log.c
* - Version : 0.03
* @brief Log driver.
* .
*****************************************************************************/
/******************************************************************************
* History : DD.MM.YYYY Version Description
* : 28.07.2021 0.01 First Release
* : 06.01.2022 0.02 Static analysis support
* : 04,04,2023 0.03 Fixed to not use the standard input/output
* library when LOG_LEVEL=0.
*****************************************************************************/
#include <stdint.h>
#include <log.h>
#include <scif.h>
#if LOG_LEVEL >= LOG_ERROR
#include <stdarg.h>
#define VSPRINTF_OK (0)
void local_printf(const char *fmt, ...)
{
va_list ap;
static char s_buffer[1024];
int32_t num;
uint32_t loop;
/* Convert all arguments to one string */
va_start(ap, fmt);
num = vsprintf(s_buffer, fmt, ap);
va_end(ap);
/* String output */
if (VSPRINTF_OK <= num)
{
for (loop = 0U; loop < num; loop++)
{
(void)console_putc((uint8_t)s_buffer[loop]);
/* If the outputted character is LF, output CR */
if (s_buffer[loop] == 0x0A) /* \n */
{
(void)console_putc((uint8_t)'\r');
}
}
}
else
{
while(1)
{
/* loop due to error detection. */
}
}
}
/* End of function local_printf(const char *fmt, ...) */
#endif
void panic_printf(const char *str)
{
const uint8_t *p = (const uint8_t *)str;
/* Output one character at a time until the data in the argument is null-terminated string. */
while(*p != (uint8_t)'\0')
{
(void)console_putc(*p);
p++;
}
/* output character is CR and LF */
(void)console_putc((uint8_t)'\r');
(void)console_putc((uint8_t)'\n');
}
/* End of function panic_printf(const char *str) */

618
Src/0_Tool/Gen4_R-Car_IPL/SDK/v3_46_0/Gen4_ICUMX_Loader/common/log/scif.c Normal file
View File

@@ -0,0 +1,618 @@
/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright 2021-2023 Renesas Electronics Corporation All rights reserved.
*******************************************************************************/
/*******************************************************************************
* DESCRIPTION : SCIF driver
******************************************************************************/
/******************************************************************************
* @file scif.c
* - Version : 0.08
* @brief 1. Initial setting of SCIF.
* 2. Initial setting of HSCIF.
* 3. Log output function.
* .
*****************************************************************************/
/******************************************************************************
* History : DD.MM.YYYY Version Description
* : 28.07.2021 0.01 First Release
* : 03.09.2021 0.02 Modify the timing of MODEMR judgement.
* : 15.10.2021 0.03 Modify register access to read modify write.
* : 03.12.2021 0.04 Fix incorrect configuration process.
* : 06.01.2022 0.05 Static analysis support
* : 23.05.2022 0.06 Integration of S4 and V4H
* : 20.12.2022 0.07 Modify writing bit size to SCBRR register.
* : 21.08.2023 0.08 Add support for V4M.
*****************************************************************************/
#include <stdint.h>
#include <types.h>
#include <cpg.h>
#include <pfc.h>
#include <scif.h>
#include <mem_io.h>
#include <micro_wait.h>
#include <rst_register.h>
/* Define */
#define SCIF_SCSCR_TE_EN (uint16_t)((uint16_t)1U << 5U)
#define SCIF_SCSCR_RE_EN (uint16_t)((uint16_t)1U << 4U)
#define SCIF_SCSCR_CKE_EXT_CLK (uint16_t)((uint16_t)2U << 0U)
#define SCIF_SCSCR_INIT_DATA (uint16_t)(SCIF_SCSCR_TE_EN | SCIF_SCSCR_RE_EN)
#define SCIF_SCSCR_HW_INIT (uint16_t)(0x0000U)
#define SCIF_SCFCR_TFRST_EN (uint16_t)((uint16_t)1U << 2U)
#define SCIF_SCFCR_RFRS_EN (uint16_t)((uint16_t)1U << 1U)
#define SCIF_SCFCR_RESET_FIFO (uint16_t)(SCIF_SCFCR_TFRST_EN | SCIF_SCFCR_RFRS_EN)
#define SCIF_SCFSR_TEND (uint16_t)((uint16_t)1U << 6U)
#define SCIF_SCFSR_TDFE (uint16_t)((uint16_t)1U << 5U)
#define TRANS_END_CHECK (uint16_t)(SCIF_SCFSR_TEND | SCIF_SCFSR_TDFE)
#define SCIF_SCFSR_INIT_DATA (uint16_t)(0x0000U)
#define SCIF_SCLSR_INIT_DATA (uint16_t)(0x0000U)
#define SCIF_SCSMR_CHR (uint16_t)((uint16_t)1U << 6U)
#define SCIF_SCSMR_PE (uint16_t)((uint16_t)1U << 5U)
#define SCIF_SCSMR_STOP (uint16_t)((uint16_t)1U << 3U)
#define SCIF_SCSMR_CKS (uint16_t)((uint16_t)3U << 0U)
#define SCIF_SCSMR_INIT_DATA ~((uint16_t)(SCIF_SCSMR_CHR | SCIF_SCSMR_PE | SCIF_SCSMR_STOP | SCIF_SCSMR_CKS))
/* Pclk(66MHz)/1, 115.2kbps*/
/* N = 66/(66/2*115200)*10^4-1 =17=> 0x11 */
#define SCIF_SCBRR_115200BPS (uint8_t)(0x11U)
/* Pclk(266MHz)/1, 921.6kbps*/
/* N = 266/(8*2*921600)*10^6-1 =17=> 0x11 */
#define HSCIF_SCBRR_921600BPS (uint8_t)(0x11U)
/* Pclk(266MHz)/1, 1.8432Mbps*/
/* N = 266/(8*2*1843200)*10^6-1 =8=> 0x08 */
#define HSCIF_SCBRR_1843200BPS (uint8_t)(0x08U)
#define HSCIF_HSSRR_SRE (uint16_t)(1U << 15U)
#define HSCIF_HSSRR_SRCYC (uint16_t)(0x1FU << 0U)
#define HSCIF_HSSRR_SRCYC8 (uint16_t)(7U << 0U) /* Sampling rate 8-1 */
#define HSCIF_HSSRR_VAL (uint16_t)(HSCIF_HSSRR_SRE | HSCIF_HSSRR_SRCYC8)
#define HSCIF_DL_DIV1 (uint16_t)(1U << 0U)
#define HSCIF_CKS_CKS (uint16_t)(1U << 15U)
#define HSCIF_CKS_XIN (uint16_t)(1U << 14U)
#define HSCIF_CKS_SC_CLK_EXT ~((uint16_t)(HSCIF_CKS_CKS | HSCIF_CKS_XIN))
/* module start setting value */
#if (RCAR_LSI == RCAR_S4)
#define CPG_MSTPCR_HSCIF (((uint32_t)1U) << 14U)
#define CPG_MSTPCR_SCIF (((uint32_t)1U) << 4U)
#elif ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M))
#define CPG_MSTPCR_HSCIF (((uint32_t)1U) << 14U)
#define CPG_MSTPCR_SCIF (((uint32_t)1U) << 2U)
#endif /* RCAR_LSI == RCAR_S4 */
/* Pin function setting value */
#if (RCAR_LSI == RCAR_S4)
#define GPSR_TX ((uint32_t)1U << 3U) /* HTX0 / TX3 */
#define GPSR_RX ((uint32_t)1U << 2U) /* HRX0 / RX3 */
#define IPSR_RX_VAL ((uint32_t)1U << 8U) /* RX3 */
#define IPSR_TX_VAL ((uint32_t)1U << 12U) /* TX3 */
#define POC_TX_33V ((uint32_t)1U << 3U) /* HTX0 / TX3 3.3V setting value */
#define POC_RX_33V ((uint32_t)1U << 2U) /* HRX0 / RX3 3.3V setting value */
#define IPSR_RX_MASK ((uint32_t)0xFU << 8U) /* IPSR bit[11:8] */
#define IPSR_TX_MASK ((uint32_t)0xFU << 12U) /* IPSR bit[15:12] */
#define PFC_GPSR_SCIF_MASK (uint32_t)(0x0000000CU) /* SCIF3/HSCIF0 RX/TX */
#define PFC_GPSR_SCIF_VAL (uint32_t)(GPSR_TX | GPSR_RX) /* SCIF3/HSCIF0 RX/TX */
#define PFC_IPSR_SCIF_MASK (uint32_t)(IPSR_RX_MASK | IPSR_TX_MASK) /* Mask value of IPSR (SCIF3/HSCIF0 RX/TX) */
#define PFC_IPSR_SCIF_VAL (uint32_t)(IPSR_RX_VAL | IPSR_TX_VAL) /* SCIF3 RX/TX */
#define PFC_IPSR_HSCIF_VAL (uint32_t)(0x00000000U) /* HSCIF0 RX/TX */
#define PFC_POC_SCIF_MASK (uint32_t)(0x0000000CU) /* SCIF3/HSCIF0 RX/TX */
#define PFC_POC_SCIF_33V (uint32_t)(POC_TX_33V | POC_RX_33V) /* SCIF3/HSCIF0 RX/TX */
#define PFC_IPSR_SCIF_EXTCLK_MASK (uint32_t)(0xFU << 0U) /* Mask value of IPSR (External Clock) */
#define PFC_IPSR_SCIF_EXTCLK_VAL (uint32_t)(0x0U << 0U) /* IPSR (External Clock) */
#define PFC_GPSR_SCIF_EXTCLK_MASK (uint32_t)(0x00000001U) /* Mask value of IPSR (External Clock) */
#define PFC_GPSR_SCIF_EXTCLK_VAL (uint32_t)(1U << 0U) /* IPSR (External Clock) */
#elif ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M))
#define GPSR_TX ((uint32_t)1U << 12U) /* HTX0 / TX0 */
#define GPSR_RX ((uint32_t)1U << 16U) /* HRX0 / RX0 */
#define IPSR_RX_VAL ((uint32_t)1U << 0U) /* RX0 */
#define IPSR_TX_VAL ((uint32_t)1U << 16U) /* TX0 */
#define POC_TX_33V ((uint32_t)1U << 12U) /* HTX0 / TX0 3.3V setting value */
#define POC_RX_33V ((uint32_t)1U << 16U) /* HRX0 / RX0 3.3V setting value */
#define POC_TX_18V ((uint32_t)0U << 12U) /* HTX0 / TX0 1.8V setting value */
#define POC_RX_18V ((uint32_t)0U << 16U) /* HRX0 / RX0 1.8V setting value */
#define IPSR_RX_MASK ((uint32_t)0xFU << 0U) /* IPSR bit[3:0] */
#define IPSR_TX_MASK ((uint32_t)0xFU << 16U) /* IPSR bit[19:16] */
#define PFC_GPSR_SCIF_MASK (uint32_t)(0x00011000U) /* SCIF0/HSCIF0 RX/TX */
#define PFC_GPSR_SCIF_VAL (uint32_t)(GPSR_TX | GPSR_RX) /* SCIF0/HSCIF0 RX/TX */
#define PFC_IPSR_SCIF_MASK1 (uint32_t)(IPSR_TX_MASK) /* Mask value of IPSR (SCIF0/HSCIF0 TX) */
#define PFC_IPSR_SCIF_VAL1 (uint32_t)(IPSR_TX_VAL) /* SCIF0 TX */
#define PFC_IPSR_SCIF_MASK2 (uint32_t)(IPSR_RX_MASK) /* Mask value of IPSR (SCIF3/HSCIF0 RX) */
#define PFC_IPSR_SCIF_VAL2 (uint32_t)(IPSR_RX_VAL) /* SCIF0 RX */
#define PFC_IPSR_HSCIF_VAL1 (uint32_t)(0x00000000U) /* HSCIF0 TX */
#define PFC_IPSR_HSCIF_VAL2 (uint32_t)(0x00000000U) /* HSCIF0 RX */
#define PFC_POC_SCIF_MASK (uint32_t)(0x00011000U) /* SCIF0/HSCIF0 RX/TX */
#define PFC_POC_SCIF_33V (uint32_t)(POC_TX_33V | POC_RX_33V) /* SCIF0/HSCIF0 RX/TX */
#define PFC_IPSR_SCIF_EXTCLK_MASK (uint32_t)(0xFU << 4U) /* Mask value of IPSR (External Clock) */
#define PFC_IPSR_SCIF_EXTCLK_VAL (uint32_t)(0x0U << 4U) /* IPSR (External Clock) */
#define PFC_GPSR_SCIF_EXTCLK_MASK (uint32_t)(0x00020000U) /* Mask value of IPSR (External Clock) */
#endif /* RCAR_LSI == RCAR_S4 */
static void (*rcar_putc)(uint8_t outchar);
static void scif_module_start(uint32_t modemr);
static void scif_pfc_init(uint32_t modemr);
static void scif_console_init(uint32_t modemr);
static void scif_console_putc(uint8_t outchar);
static void hscif_console_putc(uint8_t outchar);
static void scif_module_start(uint32_t modemr)
{
uint32_t reg;
if(modemr == MODEMR_SCIF_DLMODE)
{
reg = mem_read32(CPG_MSTPSR7D0);
/* If supply of clock to SCIF0 is stopped */
if (FALSE != (CPG_MSTPCR_SCIF & reg))
{
/* Supply of clock to SCIF0 is start */
reg &= ~(CPG_MSTPCR_SCIF);
cpg_reg_write(CPG_MSTPCR7D0, CPG_MSTPSR7D0, reg);
}
}
else
{
reg = mem_read32(CPG_MSTPSR5D0);
/* If supply of clock to SCIF0 is stopped */
if (FALSE != (CPG_MSTPCR_HSCIF & reg))
{
/* Supply of clock to SCIF0 is start */
reg &= ~(CPG_MSTPCR_HSCIF);
cpg_reg_write(CPG_MSTPCR5D0, CPG_MSTPSR5D0, reg);
}
}
}
/* End of function scif_module_start(void) */
static void scif_pfc_init(uint32_t modemr)
{
uint32_t reg;
#if (RCAR_LSI == RCAR_S4)
if(modemr == MODEMR_SCIF_DLMODE)
{
/* Set RX / TX of SCIF 0. */
reg = mem_read32(PFC_IP0SR0_RW);
reg &= (~(PFC_IPSR_SCIF_MASK));
reg |= PFC_IPSR_SCIF_VAL;
pfc_reg_write(PFC_IP0SR0_RW, reg);
/* Set Voltage setting of 1.8V. */
reg = mem_read32(PFC_POC0_RW);
reg &= (~(PFC_POC_SCIF_MASK));
pfc_reg_write(PFC_POC0_RW, reg);
}
else if(modemr == MODEMR_HSCIF_DLMODE_921600)
{
/* Set HRX / HTX of HSCIF 0. */
reg = mem_read32(PFC_IP0SR0_RW);
reg &= (~(PFC_IPSR_SCIF_MASK));
reg |= PFC_IPSR_HSCIF_VAL;
pfc_reg_write(PFC_IP0SR0_RW, reg);
/* Set Voltage setting of 3.3V. */
reg = mem_read32(PFC_POC0_RW);
reg &= (~(PFC_POC_SCIF_MASK));
reg |= PFC_POC_SCIF_33V;
pfc_reg_write(PFC_POC0_RW, reg);
}
else if(modemr == MODEMR_HSCIF_DLMODE_1843200)
{
/* Set HRX / HTX of HSCIF 0. */
reg = mem_read32(PFC_IP0SR0_RW);
reg &= (~(PFC_IPSR_SCIF_MASK));
reg |= PFC_IPSR_HSCIF_VAL;
pfc_reg_write(PFC_IP0SR0_RW, reg);
/* Set Voltage setting of 1.8V. */
reg = mem_read32(PFC_POC0_RW);
reg &= (~(PFC_POC_SCIF_MASK));
pfc_reg_write(PFC_POC0_RW, reg);
}
else if(modemr == MODEMR_HSCIF_DLMODE_3000000)
{
/* Set HRX / HTX of HSCIF 0. */
reg = mem_read32(PFC_IP0SR0_RW);
reg &= (~(PFC_IPSR_SCIF_MASK));
reg |= PFC_IPSR_HSCIF_VAL;
pfc_reg_write(PFC_IP0SR0_RW, reg);
/* Set Voltage setting of 1.8V. */
reg = mem_read32(PFC_POC0_RW);
reg &= (~(PFC_POC_SCIF_MASK));
pfc_reg_write(PFC_POC0_RW, reg);
/* Set External Clock. */
reg = mem_read32(PFC_IP0SR0_RW);
reg &= (~(PFC_IPSR_SCIF_EXTCLK_MASK));
reg |= PFC_IPSR_SCIF_EXTCLK_VAL;
pfc_reg_write(PFC_IP0SR0_RW, reg);
reg = mem_read32(PFC_GPSR0_RW);
reg &= (~(PFC_GPSR_SCIF_EXTCLK_MASK));
reg |= PFC_GPSR_SCIF_EXTCLK_MASK;
pfc_reg_write(PFC_GPSR0_RW, reg);
}
else
{
/* no process */
}
reg = mem_read32(PFC_GPSR0_RW);
reg &= (~(PFC_GPSR_SCIF_MASK));
reg |= PFC_GPSR_SCIF_VAL;
pfc_reg_write(PFC_GPSR0_RW, reg);
#elif ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M))
if(modemr == MODEMR_SCIF_DLMODE)
{
/* Set TX of SCIF 0. */
reg = mem_read32(PFC_IP1SR1_RW);
reg &= (~(PFC_IPSR_SCIF_MASK1));
reg |= PFC_IPSR_SCIF_VAL1;
pfc_reg_write(PFC_IP1SR1_RW, reg);
/* Set RX of SCIF 0. */
reg = mem_read32(PFC_IP2SR1_RW);
reg &= (~(PFC_IPSR_SCIF_MASK2));
reg |= PFC_IPSR_SCIF_VAL2;
pfc_reg_write(PFC_IP2SR1_RW, reg);
/* Set Voltage setting of 1.8V. */
reg = mem_read32(PFC_POC1_RW);
reg &= (~(PFC_POC_SCIF_MASK));
pfc_reg_write(PFC_POC1_RW, reg);
}
else if(modemr == MODEMR_HSCIF_DLMODE_921600)
{
/* Set HTX of HSCIF 0. */
reg = mem_read32(PFC_IP1SR1_RW);
reg &= (~(PFC_IPSR_SCIF_MASK1));
reg |= PFC_IPSR_HSCIF_VAL1;
pfc_reg_write(PFC_IP1SR1_RW, reg);
/* Set HRX of HSCIF 0. */
reg = mem_read32(PFC_IP2SR1_RW);
reg &= (~(PFC_IPSR_SCIF_MASK2));
reg |= PFC_IPSR_HSCIF_VAL2;
pfc_reg_write(PFC_IP2SR1_RW, reg);
/* Set Voltage setting of 3.3V. */
reg = mem_read32(PFC_POC1_RW);
reg &= (~(PFC_POC_SCIF_MASK));
reg |= PFC_POC_SCIF_33V;
pfc_reg_write(PFC_POC1_RW, reg);
}
else if(modemr == MODEMR_HSCIF_DLMODE_1843200)
{
/* Set HTX of HSCIF 0. */
reg = mem_read32(PFC_IP1SR1_RW);
reg &= (~(PFC_IPSR_SCIF_MASK1));
reg |= PFC_IPSR_HSCIF_VAL1;
pfc_reg_write(PFC_IP1SR1_RW, reg);
/* Set HRX of HSCIF 0. */
reg = mem_read32(PFC_IP2SR1_RW);
reg &= (~(PFC_IPSR_SCIF_MASK2));
reg |= PFC_IPSR_HSCIF_VAL2;
pfc_reg_write(PFC_IP2SR1_RW, reg);
/* Set Voltage setting of 1.8V. */
reg = mem_read32(PFC_POC1_RW);
reg &= (~(PFC_POC_SCIF_MASK));
pfc_reg_write(PFC_POC1_RW, reg);
}
else if(modemr == MODEMR_HSCIF_DLMODE_3000000)
{
/* Set HTX of HSCIF 0. */
reg = mem_read32(PFC_IP1SR1_RW);
reg &= (~(PFC_IPSR_SCIF_MASK1));
reg |= PFC_IPSR_HSCIF_VAL1;
pfc_reg_write(PFC_IP1SR1_RW, reg);
/* Set HRX of HSCIF 0. */
reg = mem_read32(PFC_IP2SR1_RW);
reg &= (~(PFC_IPSR_SCIF_MASK2));
reg |= PFC_IPSR_HSCIF_VAL2;
pfc_reg_write(PFC_IP2SR1_RW, reg);
/* Set Voltage setting of 1.8V. */
reg = mem_read32(PFC_POC1_RW);
reg &= (~(PFC_POC_SCIF_MASK));
pfc_reg_write(PFC_POC1_RW, reg);
/* Set External Clock. */
reg = mem_read32(PFC_IP2SR1_RW);
reg &= (~(PFC_IPSR_SCIF_EXTCLK_MASK));
reg |= PFC_IPSR_SCIF_EXTCLK_VAL;
pfc_reg_write(PFC_IP2SR1_RW, reg);
reg = mem_read32(PFC_GPSR1_RW);
reg &= (~(PFC_GPSR_SCIF_EXTCLK_MASK));
reg |= PFC_GPSR_SCIF_EXTCLK_MASK;
pfc_reg_write(PFC_GPSR1_RW, reg);
}
else
{
/* no process */
}
reg = mem_read32(PFC_GPSR1_RW);
reg &= (~(PFC_GPSR_SCIF_MASK));
reg |= PFC_GPSR_SCIF_VAL;
pfc_reg_write(PFC_GPSR1_RW, reg);
#endif /* RCAR_LSI == RCAR_S4 */
}
/* End of function scif_pfc_init(void) */
static void scif_console_init(uint32_t modemr)
{
uint16_t reg;
switch(modemr)
{
case MODEMR_HSCIF_DLMODE_3000000:
{
/* clear SCR.TE & SCR.RE*/
mem_write16(HSCIF_HSSCR, SCIF_SCSCR_HW_INIT);
/* reset tx-fifo, reset rx-fifo. */
reg = mem_read16(HSCIF_HSFCR);
reg |= SCIF_SCFCR_RESET_FIFO;
mem_write16(HSCIF_HSFCR, reg);
/* clear ORER bit */
mem_write16(HSCIF_HSLSR, SCIF_SCLSR_INIT_DATA);
/* clear all error bit */
mem_write16(HSCIF_HSFSR, SCIF_SCFSR_INIT_DATA);
/* external clock, SC_CLK pin used for output pin */
mem_write16(HSCIF_HSSCR, SCIF_SCSCR_CKE_EXT_CLK);
/* 8bit data, no-parity, 1 stop, Po/1 */
reg = mem_read16(HSCIF_HSSMR);
reg &= SCIF_SCSMR_INIT_DATA;
mem_write16(HSCIF_HSSMR, reg);
/* 24MHz / (3000000 * 8) = 1 */
mem_write16(HSCIF_DL, HSCIF_DL_DIV1);
reg = mem_read16(HSCIF_CKS);
reg &= HSCIF_CKS_SC_CLK_EXT;
mem_write16(HSCIF_CKS, reg);
/* Sampling rate 8 */
reg = mem_read16(HSCIF_HSSRR);
reg &= ~(HSCIF_HSSRR_SRE | HSCIF_HSSRR_SRCYC);
reg |= HSCIF_HSSRR_VAL;
mem_write16(HSCIF_HSSRR, reg);
micro_wait(10U); /* 10us */
/* reset-off tx-fifo, rx-fifo. */
reg = mem_read16(HSCIF_HSFCR);
reg &= ~(SCIF_SCFCR_RESET_FIFO);
mem_write16(HSCIF_HSFCR, reg);
/* enable TE, RE; SC_CLK=external */
reg = mem_read16(HSCIF_HSSCR);
reg |= SCIF_SCSCR_INIT_DATA;
mem_write16(HSCIF_HSSCR, reg);
/* Set the pointer to a function that outputs one character. */
rcar_putc = hscif_console_putc;
break;
}
case MODEMR_HSCIF_DLMODE_1843200:
{
/* clear SCR.TE & SCR.RE*/
mem_write16(HSCIF_HSSCR, SCIF_SCSCR_HW_INIT);
/* reset tx-fifo, reset rx-fifo. */
reg = mem_read16(HSCIF_HSFCR);
reg |= SCIF_SCFCR_RESET_FIFO;
mem_write16(HSCIF_HSFCR, reg);
/* clear ORER bit */
mem_write16(HSCIF_HSLSR, SCIF_SCLSR_INIT_DATA);
/* clear all error bit */
mem_write16(HSCIF_HSFSR, SCIF_SCFSR_INIT_DATA);
/* internal clock, SC_CLK pin unused for output pin */
mem_write16(HSCIF_HSSCR, SCIF_SCSCR_HW_INIT);
/* 8bit data, no-parity, 1 stop, Po/1 */
reg = mem_read16(HSCIF_HSSMR);
reg &= SCIF_SCSMR_INIT_DATA;
mem_write16(HSCIF_HSSMR, reg);
/* Sampling rate 8 */
mem_write16(HSCIF_HSSRR, HSCIF_HSSRR_VAL);
/* Baud rate 1843200bps*/
mem_write8(HSCIF_HSBRR, HSCIF_SCBRR_1843200BPS);
micro_wait(10U); /* 10us */
/* reset-off tx-fifo, rx-fifo. */
reg = mem_read16(HSCIF_HSFCR);
reg &= ~(SCIF_SCFCR_RESET_FIFO);
mem_write16(HSCIF_HSFCR, reg);
/* enable TE, RE; SC_CLK=external */
reg = mem_read16(HSCIF_HSSCR);
reg |= SCIF_SCSCR_INIT_DATA;
mem_write16(HSCIF_HSSCR, reg);
/* Set the pointer to a function that outputs one character. */
rcar_putc = hscif_console_putc;
break;
}
case MODEMR_HSCIF_DLMODE_921600:
{
/* clear SCR.TE & SCR.RE*/
mem_write16(HSCIF_HSSCR, SCIF_SCSCR_HW_INIT);
/* reset tx-fifo, reset rx-fifo. */
reg = mem_read16(HSCIF_HSFCR);
reg |= SCIF_SCFCR_RESET_FIFO;
mem_write16(HSCIF_HSFCR, reg);
/* clear ORER bit */
mem_write16(HSCIF_HSLSR, SCIF_SCLSR_INIT_DATA);
/* clear all error bit */
mem_write16(HSCIF_HSFSR, SCIF_SCFSR_INIT_DATA);
/* internal clock, SC_CLK pin unused for output pin */
mem_write16(HSCIF_HSSCR, SCIF_SCSCR_HW_INIT);
/* 8bit data, no-parity, 1 stop, Po/1 */
reg = mem_read16(HSCIF_HSSMR);
reg &= SCIF_SCSMR_INIT_DATA;
mem_write16(HSCIF_HSSMR, reg);
/* Sampling rate 8 */
mem_write16(HSCIF_HSSRR, HSCIF_HSSRR_VAL);
/* Baud rate 921600bps*/
mem_write8(HSCIF_HSBRR, HSCIF_SCBRR_921600BPS);
micro_wait(10U); /* 10us */
/* reset-off tx-fifo, rx-fifo. */
reg = mem_read16(HSCIF_HSFCR);
reg &= ~(SCIF_SCFCR_RESET_FIFO);
mem_write16(HSCIF_HSFCR, reg);
/* enable TE, RE; SC_CLK=external */
reg = mem_read16(HSCIF_HSSCR);
reg |= SCIF_SCSCR_INIT_DATA;
mem_write16(HSCIF_HSSCR, reg);
/* Set the pointer to a function that outputs one character. */
rcar_putc = hscif_console_putc;
break;
}
case MODEMR_SCIF_DLMODE:
default:
{
/* clear SCR.TE & SCR.RE*/
mem_write16(SCIF_SCSCR, SCIF_SCSCR_HW_INIT);
/* reset tx-fifo, reset rx-fifo. */
reg = mem_read16(SCIF_SCFCR);
reg |= SCIF_SCFCR_RESET_FIFO;
mem_write16(SCIF_SCFCR, reg);
/* clear ORER bit */
mem_write16(SCIF_SCLSR, SCIF_SCLSR_INIT_DATA);
/* clear all error bit */
mem_write16(SCIF_SCFSR, SCIF_SCFSR_INIT_DATA);
/* internal clock, SC_CLK pin unused for output pin */
mem_write16(SCIF_SCSCR, SCIF_SCSCR_HW_INIT);
/* 8bit data, no-parity, 1 stop, Po/1 */
reg = mem_read16(SCIF_SCSMR);
reg &= SCIF_SCSMR_INIT_DATA;
mem_write16(SCIF_SCSMR, reg);
/* Baud rate 115200bps*/
mem_write8(SCIF_SCBRR, SCIF_SCBRR_115200BPS);
micro_wait(10U); /* 10us */
/* reset-off tx-fifo, rx-fifo. */
reg = mem_read16(SCIF_SCFCR);
reg &= ~(SCIF_SCFCR_RESET_FIFO);
mem_write16(SCIF_SCFCR, reg);
/* enable TE, RE; SC_CLK=no output */
reg = mem_read16(SCIF_SCSCR);
reg |= SCIF_SCSCR_INIT_DATA;
mem_write16(SCIF_SCSCR, reg);
/* Set the pointer to a function that outputs one character. */
rcar_putc = scif_console_putc;
break;
}
}
}
/* End of function scif_console_init(void) */
void scif_init(void)
{
uint32_t modemr;
modemr = ((mem_read32(RST_MODEMR0) & RST_MODEMR0_MD31) >> 31U);
modemr |= ((mem_read32(RST_MODEMR1) & RST_MODEMR1_MD32) << 1U);
scif_module_start(modemr);
scif_pfc_init(modemr);
scif_console_init(modemr);
}
/* End of function scif_init(void) */
void console_putc(uint8_t outchar)
{
rcar_putc(outchar);
}
/* End of function console_putc(void) */
static void scif_console_putc(uint8_t outchar)
{
uint16_t reg;
/* Check that transfer of SCIF0 is completed */
while (!((TRANS_END_CHECK & mem_read16(SCIF_SCFSR)) == TRANS_END_CHECK))
{
;
}
mem_write8(SCIF_SCFTDR, outchar); /* Transfer one character */
reg = mem_read16(SCIF_SCFSR);
reg &= (uint16_t)(~(TRANS_END_CHECK)); /* TEND,TDFE clear */
mem_write16(SCIF_SCFSR, reg);
/* Check that transfer of SCIF0 is completed */
while (!((TRANS_END_CHECK & mem_read16(SCIF_SCFSR)) == TRANS_END_CHECK))
{
;
}
}
/* End of function scif_console_putc(uint8_t outchar) */
static void hscif_console_putc(uint8_t outchar)
{
uint16_t reg;
/* Check that transfer of SCIF0 is completed */
while (!((TRANS_END_CHECK & mem_read16(HSCIF_HSFSR)) == TRANS_END_CHECK))
{
;
}
mem_write8(HSCIF_HSFTDR, outchar); /* Transfer one character */
reg = mem_read16(HSCIF_HSFSR);
reg &= (uint16_t)(~(TRANS_END_CHECK)); /* TEND,TDFE clear */
mem_write16(HSCIF_HSFSR, reg);
/* Check that transfer of SCIF0 is completed */
while (!((TRANS_END_CHECK & mem_read16(HSCIF_HSFSR)) == TRANS_END_CHECK))
{
;
}
}
/* End of function hscif_console_putc(uint8_t outchar) */

109
Src/0_Tool/Gen4_R-Car_IPL/SDK/v3_46_0/Gen4_ICUMX_Loader/common/timer/micro_wait.c Normal file
View File

@@ -0,0 +1,109 @@
/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright 2021-2022 Renesas Electronics Corporation All rights reserved.
*******************************************************************************/
/*******************************************************************************
* DESCRIPTION : Time wait driver
******************************************************************************/
/******************************************************************************
* @file micro_wait.c
* - Version : 0.03
* @brief Wait of micro second
* .
*****************************************************************************/
/******************************************************************************
* History : DD.MM.YYYY Version Description
* : 28.07.2021 0.01 First Release
* : 15.10.2021 0.02 modify register access to read modify write.
* : 03.12.2021 0.03 fix incorrect configuration process.
*****************************************************************************/
#include <stdint.h>
#include <micro_wait.h>
#include <mem_io.h>
/************************************************************************************************/
/* Definitions */
/************************************************************************************************/
#define INTICUOSTM0 (0xFFFEEA14U)
#define INTCR_RF ((uint16_t)1U << 12U)
#define INTCR_RF_NO_REQ ((uint16_t)0U << 12U)
#define OSTM0_BASE (0xFFFEE000U)
#define OSTM0CMP (OSTM0_BASE)
#define OSTM0TS (OSTM0_BASE + 0x0014U)
#define OSTM0TT (OSTM0_BASE + 0x0018U)
#define OSTM0CTL (OSTM0_BASE + 0x0020U)
#define OSTM0TS_TS (uint8_t)(0x01U) /* b0:1: Start */
#define OSTM0TT_TT (uint8_t)(0x01U) /* b0:1: Stop */
#define OSTM0CMP_MICRO_VALUE (0x00000190U) /* PCLK=400MHz(400=0x190 = 1us) */
#define OSTM0CTL_MD10 (uint8_t)(0x02U) /* b1:1: Free-run compare mode(Start:0 Counting Direction:up) */
/* b0:0: Interrupts when counting starts are enabled */
#define MAX_MICRO_WAIT (10737418U) /* 0xFFFFFFFF / 400 */
void micro_wait(uint32_t count_us)
{
uint32_t val;
uint16_t reg16;
uint8_t reg8;
if (count_us != 0U)
{
/* When the timer count is an argument that exceeds 0xFFFFFFFF */
if(MAX_MICRO_WAIT < count_us)
{
count_us = MAX_MICRO_WAIT;
}
val = count_us * OSTM0CMP_MICRO_VALUE;
/* timer start */
reg8 = mem_read8(OSTM0TT);
reg8 |= OSTM0TT_TT;
mem_write8(OSTM0TT, reg8);
mem_write32(OSTM0CMP, val);
reg8 = mem_read8(OSTM0CTL);
reg8 |= OSTM0CTL_MD10;
mem_write8(OSTM0CTL, reg8);
reg8 = mem_read8(OSTM0TS);
reg8 |= OSTM0TS_TS;
mem_write8(OSTM0TS, reg8);
while (1)
{
reg16 = mem_read16(INTICUOSTM0);
if ((reg16 & (INTCR_RF)) != INTCR_RF_NO_REQ)
{
/* timer stop */
reg16 = (reg16 & (uint16_t)(~(INTCR_RF)));
mem_write16(INTICUOSTM0, reg16);
reg8 = mem_read8(OSTM0TT);
reg8 |= OSTM0TT_TT;
mem_write8(OSTM0TT, reg8);
break;
}
}
}
}
/* End of function micro_wait(uint32_t count_us) */

276
Src/0_Tool/Gen4_R-Car_IPL/SDK/v3_46_0/Gen4_ICUMX_Loader/cpu_on/cpu_on.c Normal file
View File

@@ -0,0 +1,276 @@
/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright 2021-2024 Renesas Electronics Corporation All rights reserved.
*******************************************************************************/
/*******************************************************************************
* DESCRIPTION : Power management driver
******************************************************************************/
/******************************************************************************
* @file cpu_on.c
* - Version : 0.10
* @brief Boot process of ARM CPU core.
* .
*****************************************************************************/
/******************************************************************************
* History : DD.MM.YYYY Version Description
* : 28.07.2021 0.01 First Release
* : 03.09.2021 0.02 Modify macro definition name.
* : 08.09.2021 0.03 Removed the reset process of BOOT_CTRL and
* OPBT_CTRL register.
* : 06.01.2022 0.04 Static analysis support
* : 23.05.2022 0.05 Integration of S4 and V4H
* : 21.06.2022 0.06 Remove functions for MCU.
* : 21.08.2023 0.07 Add support for V4M.
* : 17.11.2023 0.08 Move a part of definitions to cpu_on.h.
* : 09.12.2024 0.09 Update OTP_MEM_OTPMONITOR60 register to
* OTP_MEM_OTPMONITOR17 register for V4M.
* And Improve the adj_cr_variant_freq function.
* : 21.10.2025 0.10 Update the setting process for V4H-3/V4M-3/V4M-2.
*****************************************************************************/
#include <stdint.h>
#include <types.h>
#include <mem_io.h>
#include <cpu_on.h>
#include <cpg.h>
#include <cpg_register.h>
#include <ap_system_core_register.h>
#include <inline_asm.h>
/* ARM */
#define CA_CORE0_WUP_REQ (0x00000001U)
#define CA_CORE0_VLD_RVBARP (0x00000001U)
#define CR_VLD_BARP (0x00000001U << 0U)
#define CR_BAREN_VALID (0x00000001U << 4U)
#define CRRST_BIT (0x00000001U)
#if (RCAR_LSI == RCAR_V4H)
#define V4H_7_NI_CR (0x53U) /* 1400[MHz] = 50/3[MHz] x (0x53 + 0x1) */
#define V4H_5_NI_CR (0x41U) /* 1100[MHz] = 50/3[MHz] x (0x41 + 0x1) */
#define V4H_3_NI_CR (0x47U) /* 1200[MHz] = 50/3[MHz] x (0x47 + 0x1) */
#define V4H_RT_CPU_DIV (0x08U) /* 900[MHz] = 1200[MHz] x ((32-8)/32) */
#elif (RCAR_LSI == RCAR_V4M)
#define V4M_7_NI_CR (0x53U) /* 1400[MHz] = 50/3[MHz] x (0x53 + 0x1) */
#define V4M_5_NI_CR (0x41U) /* 1100[MHz] = 50/3[MHz] x (0x41 + 0x1) */
#define V4M_3_NI_CR (0x47U) /* 1200[MHz] = 50/3[MHz] x (0x47 + 0x1) */
#define V4M_2_NI_CR (0x47U) /* 1200[MHz] = 50/3[MHz] x (0x47 + 0x1) */
#define V4M_RT_CPU_DIV (0x08U) /* 900[MHz] = 1200[MHz] x ((32-8)/32) */
# endif /* RCAR_LSI == RCAR_V4H */
#define CPG_PLL6CR0_KICK_BIT (0x80000000U)
#define CPG_PLLECR_PLL6ST_BIT (0x00008000U)
#define CPG_FRQCRB_KICK_BIT (0x80000000U)
#define AP_CORE_APSREG_P_CCI500_AUX_ASPRTM (0x00000001U << 1U)
static void arm_cpu_set_address(uint32_t target, uint32_t boot_addr);
static void arm_cpu_set_address(uint32_t target, uint32_t boot_addr)
{
if(RCAR_PWR_TARGET_CR == target)
{
/* CR Boot address set */
mem_write32(APMU_CRBARP, (uint32_t)(boot_addr | CR_VLD_BARP));
mem_write32(APMU_CRBARP, (uint32_t)(boot_addr | CR_VLD_BARP | CR_BAREN_VALID));
}
else if(RCAR_PWR_TARGET_CA == target)
{
/* CA Boot address set */
mem_write32(APMU_RVBARPLC0, boot_addr | CA_CORE0_VLD_RVBARP);
mem_write32(APMU_RVBARPHC0, 0x00000000U);
}
else
{
/* No Process */
}
}
/* End of function arm_cpu_set_address(uint32_t target, uint32_t boot_addr) */
void arm_cpu_on(uint32_t target, uint32_t boot_addr)
{
uint32_t res_data;
if(RCAR_PWR_TARGET_CR == target)
{
/* CR Boot address set. */
arm_cpu_set_address(target, boot_addr);
synci();
/* CR reset. */
res_data = mem_read32(APMU_CRRSTCTRL);
res_data &= ~(CRRST_BIT);
mem_write32(APMU_CRRSTCTRL, res_data);
}
else if(RCAR_PWR_TARGET_CA == target)
{
/* CA Boot address set. */
arm_cpu_set_address(target, boot_addr);
/* AP-System core initialize */
res_data = mem_read32(ap_core_get_ap_cluster_n_aux0_addr(0U));
res_data |= AP_CORE_APSREG_AP_CLUSTER_N_AUX0_INIT;
mem_write32(ap_core_get_ap_cluster_n_aux0_addr(0U), res_data);
res_data = mem_read32(AP_CORE_APSREG_CCI500_AUX);
res_data |= AP_CORE_APSREG_CCI500_AUX_ACTDIS;
mem_write32(AP_CORE_APSREG_CCI500_AUX, res_data);
#if (RCAR_LSI == RCAR_V4H)
res_data = mem_read32(AP_CORE_APSREG_P_CCI500_AUX);
res_data |= AP_CORE_APSREG_P_CCI500_AUX_ASPRTM;
mem_write32(AP_CORE_APSREG_P_CCI500_AUX, res_data);
#endif /* RCAR_LSI == RCAR_V4H */
synci();
/* CA core0 wake up sequence. */
res_data = mem_read32(APMU_PWRCTRLC0);
res_data |= CA_CORE0_WUP_REQ;
mem_write32(APMU_PWRCTRLC0, res_data);
/* Wait until CA core0 wake up sequence finished. */
do
{
res_data = mem_read32(APMU_PWRCTRLC0);
}while(FALSE != (CA_CORE0_WUP_REQ & res_data));
}
else
{
/* No Process */
}
}
/* End of function arm_cpu_on(uint32_t target, uint32_t boot_addr) */
void adj_cr_variant_freq(void)
{
uint32_t product = mem_read32(OTP_MEM_OTPMONITOR17) & OTP_MEM_PRODUCT_MASK;
uint32_t pll6_freq = mem_read32(CPG_PLL6CR0);
uint32_t div_rt_cpu0 = mem_read32(CPG_FRQCRC0);
uint32_t div_rt_cpu1 = mem_read32(CPG_FRQCRC1);
uint32_t kick_rt_div = mem_read32(CPG_FRQCRB);
#if (RCAR_LSI == RCAR_V4H)
/* Set the CPU frequency division ratio according to the type of variant. */
switch (product)
{
case VARIANT_V4H_7:
/* Default value, do nothing */;
break;
case VARIANT_V4H_5:
pll6_freq = (pll6_freq & ~(0xFFU << 20U));
pll6_freq = (pll6_freq | (V4H_5_NI_CR << 20U));
break;
case VARIANT_V4H_3:
pll6_freq = (pll6_freq & ~(0xFFU << 20U));
pll6_freq = (pll6_freq | (V4H_3_NI_CR << 20U));
div_rt_cpu0 = (div_rt_cpu0 | (V4H_RT_CPU_DIV << 24U) | (V4H_RT_CPU_DIV << 16U));
div_rt_cpu1 = (div_rt_cpu1 | (V4H_RT_CPU_DIV << 16U));
break;
default:
; /* Do nothing */
break;
}
if (VARIANT_V4H_5 == product || VARIANT_V4H_3 == product)
{
mem_write32(CPG_CPGWPR, ~(pll6_freq));
mem_write32(CPG_PLL6CR0, pll6_freq);
/* Write Division value to FRQCRC0/FRQCRC1 register */
if (VARIANT_V4H_3 == product)
{
/* Setting value of the RT-CPU divider0/1/2 */
mem_write32(CPG_CPGWPR, ~(div_rt_cpu0));
mem_write32(CPG_FRQCRC0, div_rt_cpu0);
mem_write32(CPG_CPGWPR, ~(div_rt_cpu1));
mem_write32(CPG_FRQCRC1, div_rt_cpu1);
/* Kick the RT-CPU divider0/1/2 setting */
mem_write32(CPG_CPGWPR, ~(CPG_FRQCRB_KICK_BIT|kick_rt_div));
mem_write32(CPG_FRQCRB, (CPG_FRQCRB_KICK_BIT|kick_rt_div));
}
/* Update the PLL6 configuration settings */
mem_write32(CPG_CPGWPR, ~(mem_read32(CPG_PLL6CR0) | CPG_PLL6CR0_KICK_BIT));
mem_write32(CPG_PLL6CR0, (mem_read32(CPG_PLL6CR0) | CPG_PLL6CR0_KICK_BIT));
/* Wait for completion of updating */
while ((mem_read32(CPG_PLLECR) & CPG_PLLECR_PLL6ST_BIT) != CPG_PLLECR_PLL6ST_BIT)
{
;
}
}
#elif (RCAR_LSI == RCAR_V4M)
/* Set the CPU frequency division ratio according to the type of variant. */
switch (product)
{
case VARIANT_V4M_7:
/* Default value, do nothing */;
break;
case VARIANT_V4M_5:
pll6_freq = (pll6_freq & ~(0xFFU << 20U));
pll6_freq = (pll6_freq | (V4M_5_NI_CR << 20U));
break;
case VARIANT_V4M_3:
pll6_freq = (pll6_freq & ~(0xFFU << 20U));
pll6_freq = (pll6_freq | (V4M_3_NI_CR << 20U));
div_rt_cpu0 = (div_rt_cpu0 | (V4M_RT_CPU_DIV << 24U) | (V4M_RT_CPU_DIV << 16U));
div_rt_cpu1 = (div_rt_cpu1 | (V4M_RT_CPU_DIV << 16U));
break;
case VARIANT_V4M_2:
pll6_freq = (pll6_freq & ~(0xFFU << 20U));
pll6_freq = (pll6_freq | (V4M_2_NI_CR << 20U));
div_rt_cpu0 = (div_rt_cpu0 | (V4M_RT_CPU_DIV << 24U) | (V4M_RT_CPU_DIV << 16U));
div_rt_cpu1 = (div_rt_cpu1 | (V4M_RT_CPU_DIV << 16U));
break;
default:
; /* Do nothing */
break;
}
if (VARIANT_V4M_5 == product || VARIANT_V4M_3 == product || VARIANT_V4M_2 == product)
{
mem_write32(CPG_CPGWPR, ~(pll6_freq));
mem_write32(CPG_PLL6CR0, pll6_freq);
/* Write Division value to FRQCRC0/FRQCRC1 register */
if (VARIANT_V4M_3 == product || VARIANT_V4M_2 == product)
{
/* Setting value of the RT-CPU divider0/1/2 */
mem_write32(CPG_CPGWPR, ~(div_rt_cpu0));
mem_write32(CPG_FRQCRC0, div_rt_cpu0);
mem_write32(CPG_CPGWPR, ~(div_rt_cpu1));
mem_write32(CPG_FRQCRC1, div_rt_cpu1);
/* Kick the RT-CPU divider0/1/2 setting */
mem_write32(CPG_CPGWPR, ~(CPG_FRQCRB_KICK_BIT|kick_rt_div));
mem_write32(CPG_FRQCRB, (CPG_FRQCRB_KICK_BIT|kick_rt_div));
}
/* Update the PLL6 configuration settings */
mem_write32(CPG_CPGWPR, ~(mem_read32(CPG_PLL6CR0) | CPG_PLL6CR0_KICK_BIT));
mem_write32(CPG_PLL6CR0, (mem_read32(CPG_PLL6CR0) | CPG_PLL6CR0_KICK_BIT));
/* Wait for completion of updating */
while ((mem_read32(CPG_PLLECR) & CPG_PLLECR_PLL6ST_BIT) != CPG_PLLECR_PLL6ST_BIT)
{
;
}
}
#endif /* RCAR_LSI == RCAR_V4H */
}
/* End of function adj_cpu_variant_freq(void) */

525
Src/0_Tool/Gen4_R-Car_IPL/SDK/v3_46_0/Gen4_ICUMX_Loader/image_load/image_load.c Normal file
View File

@@ -0,0 +1,525 @@
/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright 2021-2025 Renesas Electronics Corporation All rights reserved.
*******************************************************************************/
/*******************************************************************************
* DESCRIPTION : Image load function
******************************************************************************/
/******************************************************************************
* @file image_load.c
* - Version : 0.14
* @brief Loading image driver.
* .
*****************************************************************************/
/******************************************************************************
* History : DD.MM.YYYY Version Description
* : 28.07.2021 0.01 First Release
* : 03.09.2021 0.02 Modify macro definition name.
* : 30.09.2021 0.03 Support of eMMC boot.
* : 15.10.2021 0.04 Fix a problem with overwriting the load area
* information in RTOS.
* modify Error log of check_load_area.
* Modify the process of outputting load
* information of Optionbyte to function.
* : 03.12.2021 0.05 Modify function "check_load_area" to check the
* boundary value of RT-VRAM(for virtual buffer).
* Fixed judgment of the top/end of the
* forwarding destination.
* : 06.01.2022 0.06 Support for two-stage boot of G4MH.
* : 23.05.2022 0.07 Support for updating the memory map.
* : 21.06.2022 0.08 Modify some function's arguments and add
* macros.
* : 05.08.2022 0.09 Add TFMV/NTFMV minimum version table
* information to load_init function.
* : 22.09.2022 0.10 Fix address range check for V4H.
* : 21.08.2023 0.11 Add support for V4M.
* : 15.01.2024 0.12 Add image_id initialization to load_init
* function.
* : 19.12.2024 0.13 Add RTOS#1, RTOS#2 image.
* : 26.05.2025 0.14 Change key cert address of [CA_OPTIONAL_ID+2].
*****************************************************************************/
/* indelude */
#include <stdint.h>
#include <image_load.h>
#include <remap.h>
#include <mem_io.h>
#include <log.h>
#include <rom_api.h>
#include <ram_def.h>
#if (RCAR_SA9_TYPE == FLASH_BOOT)
#include <image_load_flash.h>
#include <dma.h>
#elif (RCAR_SA9_TYPE == EMMC_BOOT)
#include <image_load_emmc.h>
#include <emmc_multiboot.h>
#include <emmc_def.h>
#endif
#define KEY_SIZE_FLG_MSK (0x00000003U)
#define KEY_SIZE_4096 (0x00000002U)
#define KEY_SIZE_3072 (0x00000001U)
#define KEY_SIZE_2048 (0x00000000U)
#define WORD_TO_BYTE (4U)
#define ERROR_PARAM (0U)
#define NOT_OVERLAP_FLAG (0U)
#define OVERLAP_FLAG (1U)
#define RAM_RANGE_OK (0U)
#define RAM_RANGE_NG (1U)
#if (BOOT_MCU != 0U)
#define RAM_MAX (5U)
#else
#define RAM_MAX (4U)
#endif /* (BOOT_MCU != 0U) */
/* Load Parameter of Secure data */
#define SRC_ADDR_OF_SECURE_DATA_FOR_ICUMXB (SRC_TOP + 0x00340000U)
#define DST_ADDR_OF_SECURE_DATA_FOR_ICUMXB (0xEB2E0000U)
#if (BOOT_MCU != 0U)
#define SRC_ADDR_OF_SECURE_DATA_FOR_ICUMH (SRC_TOP + 0x00440000U)
/* The destination address of Flash to RAM in the ICUMH Secure data is the top address of RT-VRAM. */
#endif
static void get_info_from_cert(uint32_t cert_addr, uint32_t *size,
uint32_t *dest_addr);
static void check_src_addr_range(uint32_t src, uint32_t len, uint32_t src_end);
static void check_dst_addr_range(uint32_t dst, uint32_t len, uint32_t dst_end);
static void check_overlap_images(uint32_t dst, uint32_t len, uint32_t dst_end);
uint32_t load_content_cert(void)
{
uint32_t load_num;
#if (RCAR_SA9_TYPE == FLASH_BOOT)
load_num = load_content_cert_for_flash();
#elif (RCAR_SA9_TYPE == EMMC_BOOT)
load_num = load_content_cert_for_emmc();
#else
/* NoProcess */
#endif
return load_num;
}
/* End of function load_content_cert(void) */
void load_image(LOAD_INFO* li)
{
/* log output of load image for information */
#if (RCAR_SA9_TYPE == FLASH_BOOT)
load_image_info_print_for_flash(li);
#elif (RCAR_SA9_TYPE == EMMC_BOOT)
load_image_info_print_for_emmc(li);
#endif
/* Check transfer range of image. */
check_load_area(li);
/* Image load start. */
load_start(li);
}
/* End of function load_image(LOAD_INFO* li) */
void load_init(LOAD_INFO* li)
{
uint32_t loop;
uint32_t buf;
const char *image_name[MAX_PLACED] = {
[SECURE_FW_ID] = "Secure FW",
[RTOS_ID] = "RTOS",
[CA_PROGRAM_ID] = "Cx IPL",
[ICUMH_PROGRAM_ID] = "ICUMH",
[G4MH_PROGRAM_ID] = "G4MH(1st)",
[G4MH_PROGRAM_ID + 1] = "G4MH(2nd)",
[CA_OPTIONAL_ID] = "CA Program #1",
[CA_OPTIONAL_ID + 1] = "CA Program #2",
[CA_OPTIONAL_ID + 2] = "CA Program #3",
[CA_OPTIONAL_ID + 3] = "CA Program #4",
[CA_OPTIONAL_ID + 4] = "CA Program #5",
[CA_OPTIONAL_ID + 5] = "CA Program #6",
[CA_OPTIONAL_ID + 6] = "CA Program #7",
[CA_OPTIONAL_ID + 7] = "CA Program #8",
[TFMV_MIN_VER_TBL_ID] = "TFMV minimum version table",
[NTFMV_MIN_VER_TBL_ID] = "NTFMV minimum version table",
#if (RTOS_LOAD_NUM == RTOS_LOAD_NUM_3)
[RTOS1_ID] = "RTOS#1",
[RTOS2_ID] = "RTOS#2"
#endif /* RTOS_LOAD_NUM == RTOS_LOAD_NUM_3 */
};
const uint32_t key_cert[MAX_PLACED] = {
[SECURE_FW_ID] = TFMV_KEY_CERT_ADDR,
[RTOS_ID] = TFMV_KEY_CERT_ADDR,
[CA_PROGRAM_ID] = TFMV_KEY_CERT_ADDR,
[ICUMH_PROGRAM_ID] = TFMV_KEY_CERT_ADDR,
[G4MH_PROGRAM_ID] = TFMV_KEY_CERT_ADDR,
[G4MH_PROGRAM_ID + 1] = TFMV_KEY_CERT_ADDR,
[CA_OPTIONAL_ID] = TFMV_KEY_CERT_ADDR,
#if (RCAR_LSI == RCAR_S4)
[CA_OPTIONAL_ID + 1] = TFMV_KEY_CERT_ADDR,
#elif ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M))
[CA_OPTIONAL_ID + 1] = NTFMV_KEY_CERT_ADDR,
#endif
#if (OPTEE_LOAD_ENABLE == OPTEE_DISABLE)
[CA_OPTIONAL_ID + 2] = NTFMV_KEY_CERT_ADDR,
#else
[CA_OPTIONAL_ID + 2] = TFMV_KEY_CERT_ADDR,
#endif
[CA_OPTIONAL_ID + 3] = NTFMV_KEY_CERT_ADDR,
[CA_OPTIONAL_ID + 4] = NTFMV_KEY_CERT_ADDR,
[CA_OPTIONAL_ID + 5] = NTFMV_KEY_CERT_ADDR,
[CA_OPTIONAL_ID + 6] = NTFMV_KEY_CERT_ADDR,
[CA_OPTIONAL_ID + 7] = NTFMV_KEY_CERT_ADDR,
[TFMV_MIN_VER_TBL_ID] = TFMV_KEY_CERT_ADDR,
[NTFMV_MIN_VER_TBL_ID] = NTFMV_KEY_CERT_ADDR,
#if (RTOS_LOAD_NUM == RTOS_LOAD_NUM_3)
[RTOS1_ID] = TFMV_KEY_CERT_ADDR,
[RTOS2_ID] = TFMV_KEY_CERT_ADDR
#endif /* RTOS_LOAD_NUM == RTOS_LOAD_NUM_3 */
};
/* Set Load info parameter */
for (loop = 0; loop < MAX_PLACED; loop++)
{
li[loop].name = image_name[loop];
li[loop].key_cert_addr = key_cert[loop];
li[loop].cnt_cert_addr = get_logic_cont_cert_addr(loop);
get_info_from_cert(li[loop].cnt_cert_addr, &li[loop].image_size, &li[loop].boot_addr);
buf = get_src_addr_offset_in_cert(loop);
li[loop].src_addr = (SRC_TOP + mem_read32(buf));
li[loop].image_id = loop;
#if (RCAR_SA9_TYPE == EMMC_BOOT)
buf = get_part_num_in_cert(loop);
li[loop].part_num = mem_read32(buf);
#endif
}
}/* End of function load_init(LOAD_INFO* li) */
void check_load_area(const LOAD_INFO* li)
{
uint32_t src;
uint32_t dst;
uint32_t len;
uint32_t src_end;
uint32_t dst_end;
src = li->src_addr;
dst = li->boot_addr;
len = li->image_size;
/* Check whether source is overflow. */
check_overflow(src, len, &src_end, __func__);
/* Check whether destination is overflow. */
check_overflow(dst, len, &dst_end, __func__);
/* Check source address range. */
check_src_addr_range(src, len, src_end);
/* Check destination address range. */
check_dst_addr_range(dst, len, dst_end);
/* Check whether overlap destination address and images that have been loaded. */
check_overlap_images(dst, len, dst_end);
}
/* End of function check_load_area(const LOAD_INFO* li) */
static void get_info_from_cert(uint32_t cert_addr, uint32_t *size,
uint32_t *dest_addr)
{
uint32_t val;
uint32_t certInfo1;
uint32_t pSize;
uint32_t pDestL;
/* Get key length of content certificate. */
val = mem_read32(cert_addr + CERT_INFO_FLG_OFFSET);
certInfo1 = (val >> KEY_SIZE_BIT_SHIFT) & KEY_SIZE_FLG_MSK;
/* Get the transfer address and transfer size from
the certificate in accordance with the key length. */
if (KEY_SIZE_4096 == certInfo1) /* key size = 4096 */
{
pSize = cert_addr + CERT_INFO_SIZE_OFFSET2;
*size = mem_read32(pSize) * WORD_TO_BYTE;
pDestL = cert_addr + CERT_INFO_DST_OFFSET2;
*dest_addr = mem_read32(pDestL);
}
else if (KEY_SIZE_3072 == certInfo1) /* key size = 3072 */
{
pSize = cert_addr + CERT_INFO_SIZE_OFFSET1;
*size = mem_read32(pSize) * WORD_TO_BYTE;
pDestL = cert_addr + CERT_INFO_DST_OFFSET1;
*dest_addr = mem_read32(pDestL);
}
else if (KEY_SIZE_2048 == certInfo1) /* key size = 2048 */
{
pSize = cert_addr + CERT_INFO_SIZE_OFFSET;
*size = mem_read32(pSize) * WORD_TO_BYTE;
pDestL = cert_addr + CERT_INFO_DST_OFFSET;
*dest_addr = mem_read32(pDestL);
}
else
{
*size = ERROR_PARAM;
*dest_addr = ERROR_PARAM;
}
}
/* End of function get_info_from_cert(uint32_t cert_addr, uint32_t *size, uint32_t *dest_addr) */
void load_start(const LOAD_INFO* li)
{
#if (RCAR_SA9_TYPE == FLASH_BOOT)
dma_trans_start(li->boot_addr, li->src_addr, li->image_size);
#elif (RCAR_SA9_TYPE == EMMC_BOOT)
uint32_t rtn_val;
uint32_t sector_count;
uint32_t fraction;
/* Converted to number of sectors transferred. */
sector_count = li->image_size >> EMMC_SECTOR_SIZE_SHIFT;
fraction = li->image_size % EMMC_SECTOR_SIZE;
/* Add 1 if there is a fraction */
if(0U != fraction)
{
sector_count += 1U;
}
rtn_val = emmc_trans_data(li->part_num, (li->src_addr >> EMMC_SECTOR_SIZE_SHIFT),
li->boot_addr, sector_count);
if(EMMC_DEV_OK != rtn_val)
{
ERROR("load_start(emmc_trans_data error).\r\n");
panic;
}
#else
/* NoProcess */
#endif
}/* End of function load_start(LOAD_INFO* li) */
void load_end(void)
{
#if (RCAR_SA9_TYPE == FLASH_BOOT)
dma_trans_end_check();
#else
/* NoProcess */
#endif
}/* End of function load_end(void) */
void load_securedata(uint32_t target_id)
{
LOAD_INFO tmp_li;
if(target_id == SECURE_FW_ID) /* When secure data transfer for ICUMXB FW. */
{
tmp_li.image_size = SECUREDATA_SIZE;
tmp_li.src_addr = SRC_ADDR_OF_SECURE_DATA_FOR_ICUMXB;
tmp_li.boot_addr =DST_ADDR_OF_SECURE_DATA_FOR_ICUMXB;
#if (RCAR_SA9_TYPE == EMMC_BOOT)
tmp_li.part_num = EMMC_PARTITION_1;
#endif
}
#if (BOOT_MCU != 0U)
else if(target_id == ICUMH_PROGRAM_ID) /* When secure data transfer for ICUMH FW. */
{
tmp_li.image_size = SECUREDATA_SIZE;
tmp_li.src_addr = SRC_ADDR_OF_SECURE_DATA_FOR_ICUMH;
tmp_li.boot_addr = RTVRAM_BASE;
#if (RCAR_SA9_TYPE == EMMC_BOOT)
tmp_li.part_num = EMMC_PARTITION_1;
#endif
}
#endif
else
{
ERROR("Failed input parameter.\n");
panic;
}
load_start(&tmp_li);
}/* End of function load_securedata(uint32_t target_id) */
void check_overflow(uint32_t addr, uint32_t len, uint32_t *end_addr, const char *func_name)
{
/* Pre confirmation */
if (addr > (UINT32_MAX - len))
{
ERROR("1:overflow is occurred in %s.\n", func_name);
ERROR("1:address = 0x%x size = 0x%x\n", addr, len);
panic;
}
else
{
*end_addr = addr + len - 1U;
}
/* Post confirmation */
if (*end_addr < addr)
{
ERROR("2:overflow is occurred in %s.\n", func_name);
ERROR("2:address = 0x%x size = 0x%x\n", addr, len);
panic;
}
}
/* End of function check_overflow(uint32_t addr, uint32_t len, uint32_t *end_addr, char *func_name) */
static void check_src_addr_range(uint32_t src, uint32_t len, uint32_t src_end)
{
/* Check image size */
if (len == 0U)
{
ERROR("image size error\n");
panic;
}
#if (RCAR_SA9_TYPE == FLASH_BOOT)
if ((src < SRC_TOP) || (SRC_END < src_end))
#elif (RCAR_SA9_TYPE == EMMC_BOOT)
if (SRC_END < src_end)
#endif
{
ERROR("check load area (source address)\n");
ERROR("source address = 0x%x image size = 0x%x\n", src, len);
panic;
}
}
/* End of function check_src_addr_range(uint32_t src, uint32_t len, uint32_t src_end) */
static void check_dst_addr_range(uint32_t dst, uint32_t len, uint32_t dst_end)
{
uint32_t rge_chk_flg;
uint32_t loop;
/* The memory range of destination. */
const ADDRESS_RANGE add_list[RAM_MAX] = {
[TARGET_MEM_DRAM] = {DRAM_BASE, DRAM_END},
[TARGET_MEM_RTSRAM] = {RTSRAM_BASE, RTSRAM_END},
[TARGET_MEM_RTVRAM] = {RTVRAM_VBUF_TOP, RTVRAM_VBUF_END},
[TARGET_MEM_SYSRAM] = {SYSRAM_BASE, SYSRAM_END},
#if (BOOT_MCU != 0U)
[TARGET_MEM_CODESRAM] = {CODESRAM_BASE, CODESRAM_END}
#endif /* (BOOT_MCU != 0U) */
};
/* Check image size */
if (len == 0U)
{
ERROR("image size error\n");
panic;
}
rge_chk_flg = RAM_RANGE_NG;
for(loop = 0; loop < RAM_MAX; loop++)
{
if (add_list[loop].topadd <= dst)
{
if(dst_end <= add_list[loop].endadd)
{
rge_chk_flg = RAM_RANGE_OK;
break;
}
}
}
if(rge_chk_flg != RAM_RANGE_OK)
{
ERROR("check load area (destination address)\n");
ERROR("destination address = 0x%x image size = 0x%x\n", dst, len);
panic;
}
}
/* End of function check_dst_addr_range(uint32_t dst, uint32_t len, uint32_t dst_end) */
static void check_overlap_images(uint32_t dst, uint32_t len, uint32_t dst_end)
{
uint32_t overlap;
uint32_t loop;
static uint32_t s_num = 1U;
static ADDRESS_RANGE s_placed_image[MAX_PLACED + 1] = {
[0] = {IPL_TOP, IPL_END},
[1] = {0U,0U},
[2] = {0U,0U},
[3] = {0U,0U},
[4] = {0U,0U},
[5] = {0U,0U},
[6] = {0U,0U},
[7] = {0U,0U},
[8] = {0U,0U},
[9] = {0U,0U},
[10] = {0U,0U},
[11] = {0U,0U},
[12] = {0U,0U},
[13] = {0U,0U},
[14] = {0U,0U},
[15] = {0U,0U},
[16] = {0U,0U}
};
overlap = NOT_OVERLAP_FLAG;
loop = 0U;
do
{
/* check overlap */
if ((dst >= s_placed_image[loop].topadd) && (dst <= s_placed_image[loop].endadd))
{
overlap = OVERLAP_FLAG;
}
else if ((dst_end >= s_placed_image[loop].topadd) && (dst_end <= s_placed_image[loop].endadd))
{
overlap = OVERLAP_FLAG;
}
else if ((dst < s_placed_image[loop].topadd) && (s_placed_image[loop].endadd < dst_end))
{
overlap = OVERLAP_FLAG;
}
else
{
loop++;
}
} while ((loop < s_num) && (overlap == NOT_OVERLAP_FLAG));
/* Check the overlap flag. *
* Parameters are error if overwrite occurred. *
* Otherwise, add parameters of the image to be loaded into Placed_image. */
if (overlap == NOT_OVERLAP_FLAG)
{
s_placed_image[s_num].topadd = dst;
s_placed_image[s_num].endadd = dst_end;
INFO("[0x%x] topadd = 0x%x endadd = 0x%x\n", s_num,
s_placed_image[s_num].topadd, s_placed_image[s_num].endadd);
s_num++;
}
else
{
ERROR("check load area (overlap)\n");
ERROR("destination address = 0x%x image size = 0x%x\n", dst, len);
ERROR("overlapped image is [%x]\n", loop);
ERROR("top address = 0x%x end address = 0x%x\n",
s_placed_image[loop].topadd, s_placed_image[loop].endadd);
panic;
}
}
/* End of function check_overlap_images(uint32_t dst, uint32_t len, uint32_t dst_end) */

145
Src/0_Tool/Gen4_R-Car_IPL/SDK/v3_46_0/Gen4_ICUMX_Loader/image_load/image_load_emmc.c Normal file
View File

@@ -0,0 +1,145 @@
/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright 2021-2022 Renesas Electronics Corporation All rights reserved.
*******************************************************************************/
/*******************************************************************************
* DESCRIPTION : Image load for emmc function
******************************************************************************/
/******************************************************************************
* @file image_load_emmc.c
* - Version : 0.04
* @brief Image load for emmc function.
* .
*****************************************************************************/
/******************************************************************************
* History : DD.MM.YYYY Version Description
* : 30.09.2021 0.01 First Release
* : 23.05.2022 0.02 Support for updating the memory map.
* : 05.08.2022 0.03 Add load_ver_tbl_cert_for_emmc function.
* : 30.09.2022 0.04 Modify size output in
* load_ver_tbl_cert_for_emmc function.
*****************************************************************************/
/* indelude */
#include <stdint.h>
#include <image_load.h>
#include <image_load_emmc.h>
#include <remap.h>
#include <log.h>
#include <mem_io.h>
#include <rom_api.h>
#include <emmc_multiboot.h>
#include <emmc_hal.h>
#include <emmc_std.h>
static void load_ver_tbl_cert_for_emmc(void);
uint32_t load_content_cert_for_emmc(void)
{
uint32_t load_num;
uint32_t phys_dst;
uint32_t phys_src;
uint32_t size;
uint32_t part;
/* source address.(0x00240000/sector:0x1200) */
phys_src = EMMC_CONTENT_CERT_SECTOR_NUMBER;
/* Get physical address of transfer destination. */
phys_dst = remap_get_phys_addr(SA9_DEST_ADDR);
/* transfer size(number of secters) */
size = CONTENT_CERT_INFO_SIZE >> EMMC_SECTOR_SIZE_SHIFT;
/* The partition that contains A. */
part = (uint32_t)PARTITION_ID_BOOT_1;
/* Load content cert header */
(void)emmc_trans_data(part, phys_src, phys_dst, size);
NOTICE(
"======== content cert info ========\n"
"destination address:0x%08x\n"
"physical destination address:0x%08x\n"
"source address:(p:%d)0x%08x\n"
"size:0x%08x\n", SA9_DEST_ADDR, phys_dst,
PARTITION_ID_BOOT_1, EMMC_CONTENT_CERT_ADDR, CONTENT_CERT_INFO_SIZE);
load_num = mem_read32(SA9_DEST_ADDR);
/* Check number of image load.
In case of number of image load is 0, error of transfer parameter.
In case of number of image loads is higher than 8,
the transfer parameter error. */
if ((load_num == 0U) || (load_num > CA_MAX_IMAGE))
{
ERROR("Content cert info 'load image num' fault.\n");
ERROR("load image num = %d\n",load_num);
panic;
}
/* Increase forwarding address by the size of cert header */
phys_src += (CONTENT_CERT_INFO_SIZE >> EMMC_SECTOR_SIZE_SHIFT);
phys_dst += CONTENT_CERT_INFO_SIZE;
/* Transfer size calculation for SA9 *
* TFMV key + NTFMV key + minimum version table + (content cert * number of loads) */
size = ((KEY_CERT_SIZE * 2U) + MIN_VER_TBL_SIZE
+ ((NUM_OF_ALWAYS_LOAD_CERT + load_num) * CONTENT_CERT_SIZE));
(void)emmc_trans_data(part, phys_src, phys_dst, size >> EMMC_SECTOR_SIZE_SHIFT);
NOTICE(
"======== content cert ========\n"
"address:0x%08x size:0x%08x\n", phys_dst, size);
/* Load content cert of Software minimum version table */
load_ver_tbl_cert_for_emmc();
return load_num;
}
/* End of function load_content_cert_for_emmc(void) */
static void load_ver_tbl_cert_for_emmc(void)
{
#if (SW_VERSION_CHECK == OPT_VERSION_CHECK_ENABLE)
uint32_t phys_dst;
uint32_t phys_src;
uint32_t size;
uint32_t part;
/* source address.(0x0024D000/sector:0x1268) */
phys_src = EMMC_VER_TBL_CNT_CERT_SEC_NUM;
/* Get physical address of transfer destination. */
phys_dst = remap_get_phys_addr(SA9_DEST_ADDR + EMMC_VER_TBL_OFFSET);
/* transfer size(number of secters) */
size = (CONTENT_CERT_SIZE * 2U) >> EMMC_SECTOR_SIZE_SHIFT;
/* The partition that contains content cert of Software minimum version table. */
part = (uint32_t)PARTITION_ID_BOOT_1;
/* Load content cert of Software minimum version table */
(void)emmc_trans_data(part, phys_src, phys_dst, size);
NOTICE("======== content cert of SW version table ========\n"
"address:0x%08x size:0x%08x\n", phys_dst, (size << EMMC_SECTOR_SIZE_SHIFT));
#endif /* (SW_VERSION_CHECK == OPT_VERSION_CHECK_ENABLE) */
}
/* End of function load_ver_tbl_cert_for_emmc(void) */

180
Src/0_Tool/Gen4_R-Car_IPL/SDK/v3_46_0/Gen4_ICUMX_Loader/image_load/image_load_flash.c Normal file
View File

@@ -0,0 +1,180 @@
/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright 2021-2024 Renesas Electronics Corporation All rights reserved.
*******************************************************************************/
/*******************************************************************************
* DESCRIPTION : Image load for Flash function
******************************************************************************/
/******************************************************************************
* @file image_load_flash.c
* - Version : 0.04
* @brief Image load for Flash function.
* .
*****************************************************************************/
/******************************************************************************
* History : DD.MM.YYYY Version Description
* : 30.09.2021 0.01 First Release
* : 23.05.2022 0.02 Support for updating the memory map.
* : 05.08.2022 0.03 Add load_ver_tbl_cert_for_flash function.
* : 20.12.2024 0.04 Add support for booting CR52 3 cores.
*****************************************************************************/
/* indelude */
#include <stdint.h>
#include <image_load_flash.h>
#include <dma.h>
#include <remap.h>
#include <mem_io.h>
#include <rom_api.h>
#include "image_load.h"
#if (RTOS_LOAD_NUM == RTOS_LOAD_NUM_3)
static void load_rtos12_cert_for_flash(void);
#endif /* RTOS_LOAD_NUM == RTOS_LOAD_NUM_3 */
static void load_ver_tbl_cert_for_flash(void);
uint32_t load_content_cert_for_flash(void)
{
uint32_t load_num;
uint32_t phys_dst;
uint32_t phys_src;
uint32_t size;
/* source address.(0x08240000) */
phys_src = FLASH_CONTENT_CERT_ADDR;
/* Get physical address of transfer destination. */
phys_dst = remap_get_phys_addr(SA9_DEST_ADDR);
/* transfer size */
size = CONTENT_CERT_INFO_SIZE;
/* Load content cert header */
dma_trans_start(phys_dst, phys_src, size);
NOTICE(
"======== content cert info ========\n"
"destination address:0x%08x\n"
"physical destination address:0x%08x\n"
"source address:0x%08x\n"
"size:0x%08x\n", SA9_DEST_ADDR, phys_dst, phys_src, size);
/* End loading cert header */
load_end();
load_num = mem_read32(SA9_DEST_ADDR);
/* Check number of image load.
In case of number of image load is 0, error of transfer parameter.
In case of number of image loads is higher than 8,
the transfer parameter error. */
if ((load_num == 0U) || (load_num > CA_MAX_IMAGE))
{
ERROR("Content cert info 'load image num' fault.\n");
ERROR("load image num = %d\n",load_num);
panic;
}
/* Increase forwarding address by the size of cert header */
phys_src += CONTENT_CERT_INFO_SIZE;
phys_dst += CONTENT_CERT_INFO_SIZE;
/* Transfer size calculation for SA9 *
* TFMV key + NTFMV key + TFMV/NTFMV minimum version table + (content cert * number of loads) */
size = ((KEY_CERT_SIZE * 2U) + MIN_VER_TBL_SIZE
+ ((NUM_OF_ALWAYS_LOAD_CERT + load_num) * CONTENT_CERT_SIZE));
/* Load SA9. */
dma_trans_start(phys_dst, phys_src, size);
/* End loading content cert */
load_end();
NOTICE("======== content of SA9 ========\n"
"address:0x%08x size:0x%08x\n", phys_dst, size);
/* Load content cert of Software minimum version table */
load_ver_tbl_cert_for_flash();
#if (RTOS_LOAD_NUM == RTOS_LOAD_NUM_3)
/* Load content cert of RTOS#1 and RTOS#2 */
load_rtos12_cert_for_flash();
#endif /* RTOS_LOAD_NUM == RTOS_LOAD_NUM_3 */
return load_num;
}
/* End of function load_content_cert_for_flash(void) */
static void load_ver_tbl_cert_for_flash(void)
{
#if (SW_VERSION_CHECK == OPT_VERSION_CHECK_ENABLE)
uint32_t phys_dst;
uint32_t phys_src;
uint32_t size;
/* Source address.(0x0824D000) */
phys_src = FLASH_VER_TBL_CNT_CERT_ADDR;
/* Get physical address of transfer destination. */
phys_dst = remap_get_phys_addr(SA9_DEST_ADDR + VER_TBL_CNT_CERT_OFFSET);
/* transfer size */
size = CONTENT_CERT_SIZE * 2U;
/* Load content cert of Software minimum version table. */
dma_trans_start(phys_dst, phys_src, size);
/* End loading content cert */
load_end();
NOTICE("======== content cert of SW version table ========\n"
"address:0x%08x size:0x%08x\n", phys_dst, size);
#endif /* (SW_VERSION_CHECK == OPT_VERSION_CHECK_ENABLE) */
}
/* End of function load_ver_tbl_cert_for_flash(void) */
#if (RTOS_LOAD_NUM == RTOS_LOAD_NUM_3)
static void load_rtos12_cert_for_flash(void)
{
uint32_t phys_dst;
uint32_t phys_src;
uint32_t size;
/* Source address.(0x0824E000) */
phys_src = FLASH_RTOS12_CNT_CERT_ADDR;
/* Get physical address of transfer destination. */
phys_dst = remap_get_phys_addr(SA9_DEST_ADDR + RTOS12_CNT_CERT_OFFSET);
/* transfer size */
size = CONTENT_CERT_SIZE * 2U; /* RTOS#1 and RTOS#2 */
/* Load content cert of Software minimum version table. */
dma_trans_start(phys_dst, phys_src, size);
/* End loading content cert */
load_end();
NOTICE("======== content cert of RTOS#1 and RTOS#2 ========\n"
"address:0x%08x size:0x%08x\n", phys_dst, size);
}
/* End of function load_rtos12_cert_for_flash(void) */
#endif /* RTOS_LOAD_NUM == RTOS_LOAD_NUM_3 */

53
Src/0_Tool/Gen4_R-Car_IPL/SDK/v3_46_0/Gen4_ICUMX_Loader/include/access_protection.h Normal file
View File

@@ -0,0 +1,53 @@
/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright 2022-2025 Renesas Electronics Corporation All rights reserved.
*******************************************************************************/
/*******************************************************************************
* DESCRIPTION : Access Protection function header
******************************************************************************/
#include <stdint.h>
#ifndef ACCESS_PROTECTION_ID_H__
#define ACCESS_PROTECTION_ID_H__
#define PROTECTION_DISABLE (0U)
#define PROTECTION_ENABLE (1U)
#define RGID_0 (0U)
#define RGID_1 (1U)
#define RGID_2 (2U)
#define RGID_INVALID (0xFFFFFFFFU)
#define CPG_PROTECTION (63U)
#define SYSC_PROTECTION (5U)
#define RESET_PROTECTION (29U)
#define WRITE_ENABLE (0xFFFFFFFFU)
void rgid_protection(void);
void ram_protection(void);
void rgid_protection_final(void);
void ram_protection_final(void);
void set_master_rgid_4_tfr_mod(void);
void icu_remove_write_access(void);
#endif /* ACCESS_PROTECTION_ID_H__ */

43
Src/0_Tool/Gen4_R-Car_IPL/SDK/v3_46_0/Gen4_ICUMX_Loader/include/ap_system_core_register.h Normal file
View File

@@ -0,0 +1,43 @@
/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright 2021-2022 Renesas Electronics Corporation All rights reserved.
*******************************************************************************/
/*******************************************************************************
* DESCRIPTION : AP-System Core register header
******************************************************************************/
#ifndef AP_SYSTEM_CORE_REGISTER_H_
#define AP_SYSTEM_CORE_REGISTER_H_
#include <remap_register.h>
#define AP_CORE_BASE (BASE_AP_CORE_ADDR) /* 0xE6280000 */
#define AP_CORE_APSREG_CCI500_AUX (AP_CORE_BASE + 0x00009010U)
#define AP_CORE_APSREG_P_CCI500_AUX (AP_CORE_BASE + 0x00029010U)
static inline uint32_t ap_core_get_ap_cluster_n_aux0_addr(uint32_t num)
{
return (AP_CORE_BASE + 0x00000010U + (num * 0x1000U));
}
#endif /* AP_SYSTEM_CORE_REGISTER_H_ */

34
Src/0_Tool/Gen4_R-Car_IPL/SDK/v3_46_0/Gen4_ICUMX_Loader/include/avs.h Normal file
View File

@@ -0,0 +1,34 @@
/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright 2023 Renesas Electronics Corporation All rights reserved.
*******************************************************************************/
/*******************************************************************************
* DESCRIPTION : AVS driver header
******************************************************************************/
#ifndef AVS_DRIVER_H__
#define AVS_DRIVER_H__
void avs_low_power_mode_setting(void);
#endif /* AVS_DRIVER_H__ */

82
Src/0_Tool/Gen4_R-Car_IPL/SDK/v3_46_0/Gen4_ICUMX_Loader/include/axmm_register.h Normal file
View File

@@ -0,0 +1,82 @@
/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright 2023 Renesas Electronics Corporation All rights reserved.
*******************************************************************************/
/*******************************************************************************
* DESCRIPTION : AXMM register header
******************************************************************************/
#ifndef AXMM_REGISTER_H__
#define AXMM_REGISTER_H__
#include <stdint.h>
#include <remap_register.h>
/* RT-SRAM register base address */
#define AXMM_BASE (BASE_AXMM_ADDR)
#define AXMM_DPTDIVCR (AXMM_BASE + 0x6000U)
#define AXMM_DPTRGNCR (AXMM_BASE + 0x6100U)
#define AXMM_DPTSECCR (AXMM_BASE + 0x6200U)
#define AXMM_SPTDIVCR (AXMM_BASE + 0x6300U)
#define AXMM_SPTRGNCR (AXMM_BASE + 0x6400U)
#define AXMM_SPTSECCR (AXMM_BASE + 0x6500U)
#define AXMM_DPTDIVCR_DIVADDR_MASK (0x003FFFFFU)
#define AXMM_DPTSECCR_SECGRP_MASK (0x00000F00U)
#define AXMM_DPTSECCR_SECGWP_MASK (0x0000000FU)
#define AXMM_SPTDIVCR_DIVADDR_MASK (0x000FFFFFU)
#define AXMM_SPTSECCR_SECGRP_MASK (0x00000F00U)
#define AXMM_SPTSECCR_SECGWP_MASK (0x0000000FU)
static inline uint32_t get_dptdivcr_addr(uint32_t num)
{
return ((AXMM_DPTDIVCR + (num * 4U)));
}
static inline uint32_t get_dptrgncr_addr(uint32_t num)
{
return ((AXMM_DPTRGNCR + (num * 4U)));
}
static inline uint32_t get_dptseccr_addr(uint32_t num)
{
return ((AXMM_DPTSECCR + (num * 4U)));
}
static inline uint32_t get_sptdivcr_addr(uint32_t num)
{
return ((AXMM_SPTDIVCR + (num * 4U)));
}
static inline uint32_t get_sptrgncr_addr(uint32_t num)
{
return ((AXMM_SPTRGNCR + (num * 4U)));
}
static inline uint32_t get_sptseccr_addr(uint32_t num)
{
return ((AXMM_SPTSECCR + (num * 4U)));
}
#endif /* AXMM_REGISTER_H__ */

171
Src/0_Tool/Gen4_R-Car_IPL/SDK/v3_46_0/Gen4_ICUMX_Loader/include/cnf_tbl.h Normal file
View File

@@ -0,0 +1,171 @@
/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright 2021-2025 Renesas Electronics Corporation All rights reserved.
*******************************************************************************/
/*******************************************************************************
* DESCRIPTION : Configuration table header
******************************************************************************/
#ifndef CNF_TBL_H_
#define CNF_TBL_H_
#include <stdint.h>
#include <dma_register.h>
typedef struct{
uint32_t reg_addr; /* register address(for SIC remap) */
uint32_t value; /* setting value */
} CONFIGURATION_SETTING_TABLE;
typedef struct{
uint64_t fix;
uint64_t be;
} QOS_SETTING_TABLE;
typedef struct{
uint32_t addr; /* address of Region ID registers.(for SIC Remap) */
uint32_t value; /* setting value of Region ID registers. */
} REGION_ID_SETTING_TABLE;
typedef struct{
uint32_t size; /* setting size of Region ID registers. */
} REGION_ID_SIZE_TABLE;
typedef struct {
uint32_t rw_val;
uint32_t sec_val;
}RAM_PROTECTION_VALUE_FORMAT;
typedef struct {
uint32_t read_val;
uint32_t write_val;
}RTRAM_PROTECTION_VALUE_FORMAT;
typedef struct {
uint32_t addr;
RTRAM_PROTECTION_VALUE_FORMAT setting_value;
}RTRAM_PROTECTION_STRUCTUR;
typedef struct {
uint32_t addr;
RAM_PROTECTION_VALUE_FORMAT setting_value;
}SYSTEM_RAM_PROTECTION_STRUCTUR;
typedef struct {
uint64_t addr;
RAM_PROTECTION_VALUE_FORMAT setting_value;
}DRAM_PROTECTION_STRUCTUR;
#if (RCAR_LSI == RCAR_S4)
#define QOS_TBL_MAX (48U) /* Max setting number of QoS Bank registers. */
#elif ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M))
#define QOS_TBL_MAX (125U) /* Max setting number of QoS Bank registers. */
#endif /* RCAR_LSI == RCAR_S4 */
#if (RCAR_LSI == RCAR_S4)
#define RGID_M_MAX (44U) /* Max number of Region registers. (Master) */
#define RGID_R_MAX (606U) /* Max number of Region registers. (Read) */
#define RGID_W_MAX (606U) /* Max number of Region registers. (Write) */
#define RGID_SEC_MAX (633U) /* Max number of Region registers. (Secure) */
#define RGID_AXI_MAX (54U) /* Max number of Region registers. (Read/Write for AXI-bus) */
#elif (RCAR_LSI == RCAR_V4H)
#define RGID_M_MAX (77U) /* Max number of Region registers. (Master) */
#define RGID_R_MAX (909U) /* Max number of Region registers. (Read) */
#define RGID_W_MAX (908U) /* Max number of Region registers. (Write) */
#define RGID_SEC_MAX (958U) /* Max number of Region registers. (Secure) */
#define RGID_AXI_MAX (98U) /* Max number of Region registers. (Read/Write for AXI-bus) */
#define RGID_GID_MAX (2U) /* Max number of Region registers. (CCI MPU GID register) */
#elif (RCAR_LSI == RCAR_V4M)
#define RGID_M_MAX (85U) /* Max number of Region registers. (Master) */
#define RGID_R_MAX (806U) /* Max number of Region registers. (Read) */
#define RGID_W_MAX (805U) /* Max number of Region registers. (Write) */
#define RGID_SEC_MAX (820U) /* Max number of Region registers. (Secure) */
#define RGID_AXI_MAX (90U) /* Max number of Region registers. (Read/Write for AXI-bus) */
#define RGID_GID_MAX (1U) /* Max number of Region registers. (CCI MPU GID register) */
#endif /* (RCAR_LSI == RCAR_S4) */
#if (RCAR_LSI == RCAR_V4H)
#define RGID_SIZE_MAX (9U) /* Max number of Region ID table. */
#elif (RCAR_LSI == RCAR_V4M)
#define RGID_SIZE_MAX (7U) /* Max number of Region ID table. */
#endif /* (RCAR_LSI == RCAR_V4H) */
#define RAM_PROTECTION_MAX (16U) /* Max number of RAM Protection registers. (RT-SRAM/RT-VRAM/SystemRAM) */
#define DRAM_PROTECTION_MAX (64U) /* Max number of RAM Protection registers. (SDRAM) */
#if (RCAR_LSI == RCAR_S4)
#define FDT_REG_MAX (102U)
#elif (RCAR_LSI == RCAR_V4H)
#define FDT_REG_MAX (120U)
#elif (RCAR_LSI == RCAR_V4M)
#define FDT_REG_MAX (73U)
#endif
#if (RCAR_LSI == RCAR_V4H)
#define INTEN_REG_MAX (401U)
#elif (RCAR_LSI == RCAR_V4M)
#define INTEN_REG_MAX (375U)
#endif /* (RCAR_LSI == RCAR_V4H) */
#if (RCAR_LSI == RCAR_V4H)
#define IMP_MASTER_MAX (19U)
#define IMP_SLAVE_MAX (35U)
#endif /* (RCAR_LSI == RCAR_V4H) */
#if (RCAR_LSI == RCAR_V4H)
#define IPMMU_RGID_MAX (11U)
#elif (RCAR_LSI == RCAR_V4M)
#define IPMMU_RGID_MAX (10U)
#endif /* (RCAR_LSI == RCAR_V4H) */
extern const QOS_SETTING_TABLE g_qosbw_tbl[QOS_TBL_MAX];
extern const QOS_SETTING_TABLE g_qoswt_tbl[QOS_TBL_MAX];
extern const REGION_ID_SIZE_TABLE g_rgid_size_tbl[RGID_SIZE_MAX];
extern const REGION_ID_SETTING_TABLE g_rgid_m_tbl[RGID_M_MAX];
extern const REGION_ID_SETTING_TABLE g_rgid_r_tbl[RGID_R_MAX];
extern const REGION_ID_SETTING_TABLE g_rgid_w_tbl[RGID_W_MAX];
extern const REGION_ID_SETTING_TABLE g_rgid_sec_tbl[RGID_SEC_MAX];
extern const REGION_ID_SETTING_TABLE g_rgid_axi_tbl[RGID_AXI_MAX];
extern const REGION_ID_SETTING_TABLE g_rgid_gid_tbl[RGID_GID_MAX];
extern const uint32_t g_rgid_rtdma_setting_value[RTDMA_MODULE_MAX][RTDMA_CH_MAX][2U];
extern const uint32_t g_rgid_sysdma_setting_value[SYSDMA_MODULE_MAX][SYSDMA_CH_MAX][2U];
extern const RTRAM_PROTECTION_STRUCTUR g_rtsram_protection_table[RAM_PROTECTION_MAX];
extern const RTRAM_PROTECTION_STRUCTUR g_rtvram1_protection_table_1[RAM_PROTECTION_MAX];
#if (RCAR_LSI == RCAR_S4)
extern const RTRAM_PROTECTION_STRUCTUR g_rtvram1_protection_table_2[RAM_PROTECTION_MAX];
#endif
extern const SYSTEM_RAM_PROTECTION_STRUCTUR g_system_ram_protection_table[RAM_PROTECTION_MAX];
extern const DRAM_PROTECTION_STRUCTUR g_dram_protection_table[DRAM_PROTECTION_MAX];
extern const CONFIGURATION_SETTING_TABLE g_fdt_tbl[FDT_REG_MAX];
extern const CONFIGURATION_SETTING_TABLE g_inten_tbl[INTEN_REG_MAX];
#if (RCAR_LSI == RCAR_V4H)
extern const REGION_ID_SETTING_TABLE g_imp_rgid_m_tbl[IMP_MASTER_MAX];
extern const REGION_ID_SETTING_TABLE g_imp_rgid_s_tbl[IMP_SLAVE_MAX];
#endif /* (RCAR_LSI == RCAR_V4H) */
extern const REGION_ID_SETTING_TABLE g_ipmmu_rgid_tbl[IPMMU_RGID_MAX];
extern const REGION_ID_SETTING_TABLE g_ipmmu_rgid_sec_tbl[IPMMU_RGID_MAX];
extern const REGION_ID_SETTING_TABLE g_ipmmu_rgid_en_tbl[IPMMU_RGID_MAX];
/* Now go back to default rules */
#pragma ghs section rodata=default
#endif /* CNF_TBL_H_ */

57
Src/0_Tool/Gen4_R-Car_IPL/SDK/v3_46_0/Gen4_ICUMX_Loader/include/cpg.h Normal file
View File

@@ -0,0 +1,57 @@
/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright 2021-2022 Renesas Electronics Corporation All rights reserved.
*******************************************************************************/
/*******************************************************************************
* DESCRIPTION : CPG driver header
******************************************************************************/
#ifndef CPG_H_
#define CPG_H_
#include <stdint.h>
#include <mem_io.h>
#include <cpg_register.h>
#define RPC_CLK_160MHZ (0x00000013U) /* RPCphi = 160MHz RPCD2phi = 80MHZ */
/* Prototype */
void cpg_init(void);
/* Inline function */
static inline void cpg_reg_write(uint32_t mstpcr, uint32_t mstpsr, uint32_t data)
{
mem_write32(CPG_CPGWPR, ~data);
mem_write32(mstpcr, data);
while ((mem_read32(mstpsr) & ~(uint32_t)(data)) != 0U)
{
/* Loop to wait for confirmation that changes to "MSTPCRn" are reflected in "MSTPSRn". */
}
}
/* Inline function */
static inline void apmu_reg_write(uint32_t reg, uint32_t data)
{
mem_write32(APMU_WPR, ~data);
mem_write32(reg, data);
}
#endif /* CPG_H_ */

124
Src/0_Tool/Gen4_R-Car_IPL/SDK/v3_46_0/Gen4_ICUMX_Loader/include/cpg_register.h Normal file
View File

@@ -0,0 +1,124 @@
/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright 2021-2025 Renesas Electronics Corporation All rights reserved.
*******************************************************************************/
/*******************************************************************************
* DESCRIPTION : CPG register header
******************************************************************************/
#ifndef CPG_REGISTER_H__
#define CPG_REGISTER_H__
#include <remap_register.h>
/* CPG base address */
/* 0xE6150000 */
#define CPG_BASE (BASE_CPG_ADDR)
/* Domain Offset Addresses */
#define D0 (0x4000U * 0U)
#define D1 (0x4000U * 1U)
#define D2 (0x4000U * 2U)
#define D3 (0x4000U * 3U)
/* CPG write protect */
#define CPG_CPGWPR (CPG_BASE + 0x0000U + D0)
/* CPG write protect control */
#define CPG_CPGWPCR (CPG_BASE + 0x0004U + D0)
/* Module Stop Control register */
/* Registers of domain 0 */
#define CPG_MSTPCR5D0 (CPG_BASE + 0x2D14U + D0) /* HSCIF0, I2C3 */
#define CPG_MSTPCR7D0 (CPG_BASE + 0x2D1CU + D0) /* SCIF0 */
#define CPG_MSTPCR28D0 (CPG_BASE + 0x2D70U + D0) /* FCPR */
/* Module Stop Status register */
/* Registers of domain 0 */
#define CPG_MSTPSR5D0 (CPG_BASE + 0x2E14U + D0) /* HSCIF0, I2C3 */
#define CPG_MSTPSR7D0 (CPG_BASE + 0x2E1CU + D0) /* SCIF0 */
#define CPG_MSTPSR28D0 (CPG_BASE + 0x2E70U + D0) /* FCPR */
/* Module standby , Software reset */
#define CPG_SRCR11 (CPG_BASE + 0x2C2CU)
#define CPG_SRSTCLR11 (CPG_BASE + 0x2CACU)
#if (RCAR_LSI == RCAR_V4H)
#define CPG_SRCR28 (CPG_BASE + 0x2C70U)
#define CPG_SRCR29 (CPG_BASE + 0x2C74U)
#endif /* RCAR_LSI == RCAR_V4H */
#define CPGSRCR_PDR11 (0x00002000U) /* Bit13 */
#if (RCAR_LSI == RCAR_V4H)
#define CPGSRCR28_VAL (0xCF600000U)
#define CPGSRCR29_VAL (0x007B3D9EU)
#endif /* RCAR_LSI == RCAR_V4H */
#define CPG_D1WACRA00 (CPG_BASE + 0x3900U)
#define CPG_D2WACRA00 (CPG_BASE + 0x3A00U)
#define CPG_D3WACRA00 (CPG_BASE + 0x3B00U)
#define CPG_D1WACR_MSTPCR0 (CPG_BASE + 0x3100U)
#define CPG_D1WACR_RAHSR0 (CPG_BASE + 0x3180U)
#define CPG_D1WACR_SRCR0 (CPG_BASE + 0x3500U)
#define CPG_D1WACR_SRSTCLR0 (CPG_BASE + 0x3580U)
#define CPG_D2WACR_MSTPCR0 (CPG_BASE + 0x3200U)
#define CPG_D2WACR_RAHSR0 (CPG_BASE + 0x3280U)
#define CPG_D2WACR_SRCR0 (CPG_BASE + 0x3600U)
#define CPG_D2WACR_SRSTCLR0 (CPG_BASE + 0x3680U)
#define CPG_D3WACR_MSTPCR0 (CPG_BASE + 0x3300U)
#define CPG_D3WACR_RAHSR0 (CPG_BASE + 0x3380U)
#define CPG_D3WACR_SRCR0 (CPG_BASE + 0x3700U)
#define CPG_D3WACR_SRSTCLR0 (CPG_BASE + 0x3780U)
/* APMU */
#define APMU_BASE (BASE_APMU_ADDR)
#if (RCAR_LSI == RCAR_S4)
#define CORTEX_R_CORE (0U) /* Target Cortex R52 cores (0 only) */
#elif ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M))
#define CORTEX_R_CORE (1U) /* Target Cortex R52 cores (0 to 2) */
#endif /* RCAR_LSI == RCAR_S4 */
#define APMU_WPR (APMU_BASE + 0x0004U) /* Write protection register */
#define APMU_D0_ACCENR (APMU_BASE + 0x0010U) /* Domain0 Access enable register */
#define APMU_D1_ACCENR (APMU_BASE + 0x0014U) /* Domain1 Access enable register */
#define APMU_D2_ACCENR (APMU_BASE + 0x0018U) /* Domain2 Access enable register */
#define APMU_D3_ACCENR (APMU_BASE + 0x001CU) /* Domain3 Access enable register */
#define APMU_CRRSTCTRL (APMU_BASE + (CORTEX_R_CORE * 0x40U) + 0x0304U) /* Cortex-R Reset Control Register */
#define APMU_CRBAR (APMU_BASE + (CORTEX_R_CORE * 0x40U) + 0x0334U) /* Cortex-R Boot Address Register */
#define APMU_CRBARP (APMU_BASE + (CORTEX_R_CORE * 0x40U) + 0x033CU) /* Cortex-R Boot Address Register Protected */
#define APMU_PWRCTRLC0 (APMU_BASE + 0x0800U) /* Power Control Register for Core 0 */
#define APMU_RVBARPLC0 (APMU_BASE + 0x0838U) /* Reset Vector Base Address Register Protected Low for Core 0 */
#define APMU_RVBARPHC0 (APMU_BASE + 0x083CU) /* Reset Vector Base Address Register Protected High for Core 0 */
/* SD-IF */
#define CPG_SD0CKCR0 (CPG_BASE + 0x0870U)
/* RPC */
#define CPG_RPCCKCR (CPG_BASE + 0x0874U)
#define CPG_PLL6CR0 (CPG_BASE + 0x084CU)
#define CPG_PLLECR (CPG_BASE + 0x0820U)
#define CPG_FRQCRC0 (CPG_BASE + 0x0808U)
#define CPG_FRQCRC1 (CPG_BASE + 0x08E0U)
#define CPG_FRQCRB (CPG_BASE + 0x0804U)
#endif /* CPG_REGISTER_H__ */

103
Src/0_Tool/Gen4_R-Car_IPL/SDK/v3_46_0/Gen4_ICUMX_Loader/include/cpu.h Normal file
View File

@@ -0,0 +1,103 @@
/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright 2022 Renesas Electronics Corporation All rights reserved.
*******************************************************************************/
/*******************************************************************************
* DESCRIPTION : CPU register access list header
******************************************************************************/
#ifndef CPU_H_
#define CPU_H_
/*
* Groups
*/
/* Name Reg, Group Comment */
#define EIPC 0, 0 /* Status save registers when acknowledging EI level exception SV */
#define EIPSW 1, 0 /* Status save registers when acknowledging EI level exception SV */
#define FEPC 2, 0 /* Status save registers when acknowledging FE level exception SV */
#define FEPSW 3, 0 /* Status save registers when acknowledging FE level exception SV */
#define PSW 5, 0 /* Program status word Note 1 */
#define EIIC 13, 0 /* EI level exception cause SV */
#define FEIC 14, 0 /* FE level exception cause SV */
#define CTPC 16, 0 /* CALLT execution status save register UM */
#define CTPSW 17, 0 /* CALLT execution status save register UM */
#define CTBP 20, 0 /* CALLT base pointer UM */
#define EIWR 28, 0 /* EI level exception working register SV */
#define FEWR 29, 0 /* FE level exception working register SV */
#define BSEL 31, 0 /* (Reserved for backward compatibility with V850E2 series)Note 2 SV */
#define MCFG0 0, 1 /* Machine configuration SV */
#define RBASE 2, 1 /* Reset vector base address SV */
#define EBASE 3, 1 /* Exception handler vector address SV */
#define INTBP 4, 1 /* Base address of the interrupt handler table SV */
#define MCTL 5, 1 /* CPU control SV */
#define PID 6, 1 /* Processor ID SV */
#define SCCFG 11, 1 /* SYSCALL operation setting SV */
#define SCBP 12, 1 /* SYSCALL base pointer SV */
#define HTCFG0 0, 2 /* Thread configuration SV */
#define MEA 6, 2 /* Memory error address SV */
#define ASID 7, 2 /* Address space ID SV */
#define MEI 8, 2 /* Memory error information SV */
#define ISPR 10, 2 /* Priority of interrupt being serviced SV */
#define PMR 11, 2 /* Interrupt priority masking SV */
#define ICSR 12, 2 /* Interrupt control status SV */
#define INTCFG 13, 2 /* Interrupt function setting SV */
#define MPM 0, 5 /* Memory protection operation mode setting SV */
#define MPRC 1, 5 /* MPU region control SV */
#define MPBRGN 4, 5 /* MPU base region number SV */
#define MPTRGN 5, 5 /* MPU end region number SV */
#define MCA 8, 5 /* Memory protection setting check address SV */
#define MCS 9, 5 /* Memory protection setting check size SV */
#define MCC 10, 5 /* Memory protection setting check command SV */
#define MCR 11, 5 /* Memory protection setting check result SV */
#define MPLA0 0, 6 /* Protection area minimum address SV */
#define MPUA0 1, 6 /* Protection area maximum address SV */
#define MPAT0 2, 6 /* Protection area attribute SV */
#define MPLA1 4, 6 /* Protection area minimum address SV */
#define MPUA1 5, 6 /* Protection area maximum address SV */
#define MPAT1 6, 6 /* Protection area attribute SV */
#define MPLA2 8, 6 /* Lower address of the protection area SV */
#define MPUA2 9, 6 /* Protection area maximum address SV */
#define MPAT2 10, 6 /* Protection area attribute SV */
#define MPLA3 12, 6 /* Protection area minimum address SV */
#define MPUA3 13, 6 /* Protection area maximum address SV */
#define MPAT3 14, 6 /* Protection area attribute SV */
#define MPLA4 16, 6 /* Protection area minimum address SV */
#define MPUA4 17, 6 /* Protection area maximum address SV */
#define MPAT4 18, 6 /* Protection area attribute SV */
#define MPLA5 20, 6 /* Protection area minimum address SV */
#define MPUA5 21, 6 /* Protection area maximum address SV */
#define MPAT5 22, 6 /* Protection area attribute SV */
#define MPLA6 24, 6 /* Protection area minimum address SV */
#define MPUA6 25, 6 /* Protection area maximum address SV */
#define MPAT6 26, 6 /* Protection area attribute SV */
#define MLUA7 28, 6 /* Protection area minimum address SV */
#define MPUA7 29, 6 /* Protection area maximum address SV */
#define MPAT7 30, 6 /* Protection area attribute SV */
#endif /* CPU_H_ */

62
Src/0_Tool/Gen4_R-Car_IPL/SDK/v3_46_0/Gen4_ICUMX_Loader/include/cpu_on.h Normal file
View File

@@ -0,0 +1,62 @@
/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright 2021-2024 Renesas Electronics Corporation All rights reserved.
*******************************************************************************/
/*******************************************************************************
* DESCRIPTION : Power management driver header
******************************************************************************/
#ifndef CPU_ON_H__
#define CPU_ON_H__
#include "remap_register.h"
#define RCAR_PWR_TARGET_CR (0U)
#define RCAR_PWR_TARGET_CA (1U)
#define AP_CORE_APSREG_AP_CLUSTER_N_AUX0_ACTDIS1 (0x00000001U << 1U)
#define AP_CORE_APSREG_AP_CLUSTER_N_AUX0_ACTDIS0 (0x00000001U << 0U)
#define AP_CORE_APSREG_CCI500_AUX_ACTDIS (0x00000001U << 0U)
#define AP_CORE_APSREG_AP_CLUSTER_N_AUX0_INIT (AP_CORE_APSREG_AP_CLUSTER_N_AUX0_ACTDIS1 | AP_CORE_APSREG_AP_CLUSTER_N_AUX0_ACTDIS0)
#define OTP_MEM_1_BASE (BASE_OTP_MEM_ADDR)
#define OTP_MEM_OTPMONITOR17 (OTP_MEM_1_BASE + 0x0144U)
#define OTP_MEM_PRODUCT_MASK (0x000000FFU)
#if (RCAR_LSI == RCAR_V4H)
#define VARIANT_V4H_7 (0x00U)
#define VARIANT_V4H_5 (0x01U)
#define VARIANT_V4H_3 (0x02U)
#elif (RCAR_LSI == RCAR_V4M)
#define VARIANT_V4M_7 (0x00U)
#define VARIANT_V4M_5 (0x01U)
#define VARIANT_V4M_3 (0x02U)
#define VARIANT_V4M_2 (0x04U)
#endif /* RCAR_LSI == RCAR_V4H */
/*******************************************************************************
* Function & variable prototypes
******************************************************************************/
void arm_cpu_on(uint32_t target, uint32_t boot_addr);
void adj_cr_variant_freq(void);
#endif /* CPU_ON_H__ */

56
Src/0_Tool/Gen4_R-Car_IPL/SDK/v3_46_0/Gen4_ICUMX_Loader/include/dma.h Normal file
View File

@@ -0,0 +1,56 @@
/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright 2021-2022 Renesas Electronics Corporation All rights reserved.
*******************************************************************************/
/*******************************************************************************
* DESCRIPTION : DMA driver header
******************************************************************************/
#ifndef DMA_DRIVER_H__
#define DMA_DRIVER_H__
#include <stdint.h>
#include <dma_register.h>
#include <log.h>
/* fraction mask for 64-byte units */
#define FRACTION_MASK_64_BYTE (0x0000003FU)
/* Prototype */
void dma_init(void);
void dma_trans_start(uint32_t dst, uint32_t src, uint32_t len);
void dma_trans_end_check(void);
void dma_release(void);
/* Inline function */
/* Check address align when RT-DMAC/SDMAC transfer */
static inline void dma_address_align_check(uint32_t dst_addr, uint32_t src_addr)
{
if (((src_addr & FRACTION_MASK_64_BYTE) != 0U) || ((dst_addr & FRACTION_MASK_64_BYTE) != 0U))
{
/* src_addr or dst_addr are not 64-byte alignment. */
ERROR("Not 64-byte alignment in DMA transfer\n");
panic;
}
}
#endif /* DMA_DRIVER_H__ */

154
Src/0_Tool/Gen4_R-Car_IPL/SDK/v3_46_0/Gen4_ICUMX_Loader/include/dma_register.h Normal file
View File

@@ -0,0 +1,154 @@
/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright 2021-2023 Renesas Electronics Corporation All rights reserved.
*******************************************************************************/
/*******************************************************************************
* DESCRIPTION : DMA register header
******************************************************************************/
#ifndef DMA_REGISTER_H_
#define DMA_REGISTER_H_
#include <remap_register.h>
#include <log.h>
#define DMACH (0U) /* The range of DMA ch is 0-15. */
#if ((RCAR_LSI == RCAR_S4) || (RCAR_LSI == RCAR_V4H))
#define RTDMA_MODULE_MAX (4U)
#define RTDMA_CH_MAX (16U)
#define SYSDMA_MODULE_MAX (2U)
#define SYSDMA_CH_MAX (16U)
#elif (RCAR_LSI == RCAR_V4M)
#define RTDMA_MODULE_MAX (2U)
#define RTDMA_CH_MAX (16U)
#define SYSDMA_MODULE_MAX (2U)
#define SYSDMA_CH_MAX (16U)
#endif
/* RT-DMA Control */
#define RTDMACTL_BASE (BASE_RTDMACTL_ADDR)
#define RTDMA_DMOR (RTDMACTL_BASE + 0x0060U) /* DMA operation register */
/* RT-DMAC0(for RPC) */
#define RTDMA0_BASE (BASE_RTDMA0_ADDR)
#define RTDMA1_BASE (RTDMA0_BASE + 0x00010000U)
#define RTDMA2_BASE (RTDMA0_BASE + 0x00160000U)
#define RTDMA3_BASE (RTDMA0_BASE + 0x00170000U)
/* SYSDMAC */
#define SYSDMA0_BASE (BASE_DMA_ADDR)
#define SYSDMA1_BASE (SYSDMA0_BASE + 0x00010000U)
#define RTDMA_DMSEC (RTDMA0_BASE + 0x00B0U)
#define DMA_REGIONID_MASK (0x0000000FU)
static inline uint32_t dma_get_rtdma_sar_addr(uint32_t num)
{
return (RTDMA0_BASE + 0x0000U + (num * 0x1000U));
}
static inline uint32_t dma_get_rtdma_dar_addr(uint32_t num)
{
return (RTDMA0_BASE + 0x0004U + (num * 0x1000U));
}
static inline uint32_t dma_get_rtdma_tcr_addr(uint32_t num)
{
return (RTDMA0_BASE + 0x0008U + (num * 0x1000U));
}
static inline uint32_t dma_get_rtdma_chcr_addr(uint32_t num)
{
return (RTDMA0_BASE + 0x000CU + (num * 0x1000U));
}
static inline uint32_t dma_get_rtdma_module_base_addr(uint32_t module)
{
uint32_t ret;
if(module == 0U)
{
ret = RTDMA0_BASE;
}
else if(module == 1U)
{
ret = RTDMA1_BASE;
}
#if ((RCAR_LSI == RCAR_S4) || (RCAR_LSI == RCAR_V4H))
else if(module ==2U)
{
ret = RTDMA2_BASE;
}
else if(module == 3U)
{
ret = RTDMA3_BASE;
}
#endif /* ((RCAR_LSI == RCAR_S4) || (RCAR_LSI == RCAR_V4H)) */
else
{
ERROR("Invalid DMA module value!\n");
panic;
}
return ret;
}
static inline uint32_t dma_get_rtdma_regionid_addr(uint32_t module, uint32_t ch)
{
uint32_t base;
base = dma_get_rtdma_module_base_addr(module);
return (base + 0x0078U + (ch * 0x1000U));
}
static inline uint32_t dma_get_sysdma_module_base_addr(uint32_t module)
{
uint32_t ret;
if(module == 0U)
{
ret = SYSDMA0_BASE;
}
else if(module == 1U)
{
ret = SYSDMA1_BASE;
}
else
{
ERROR("Invalid DMA module value!\n");
panic;
}
return ret;
}
static inline uint32_t dma_get_sysdma_regionid_addr(uint32_t module, uint32_t ch)
{
uint32_t base;
base = dma_get_sysdma_module_base_addr(module);
return (base + 0x0078U + (ch * 0x1000U));
}
#endif /* DMAREGISTER_H_ */

41
Src/0_Tool/Gen4_R-Car_IPL/SDK/v3_46_0/Gen4_ICUMX_Loader/include/emmc_boot.h Normal file
View File

@@ -0,0 +1,41 @@
/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright 2021-2022 Renesas Electronics Corporation All rights reserved.
*******************************************************************************/
/*******************************************************************************
* DESCRIPTION : eMMC boot header
******************************************************************************/
#ifndef EMMC_BOOT_
#define EMMC_BOOT_
#include <stdint.h>
#define FLASH_BOOT (0U)
#define EMMC_BOOT (1U)
#define CA_IPL (0U)
#define BL31 (1U)
void emmc_initialize( void );
#endif /* EMMC_BOOT_ */

82
Src/0_Tool/Gen4_R-Car_IPL/SDK/v3_46_0/Gen4_ICUMX_Loader/include/emmc_config.h Normal file
View File

@@ -0,0 +1,82 @@
/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright 2021-2023 Renesas Electronics Corporation All rights reserved.
*******************************************************************************/
/*******************************************************************************
* DESCRIPTION : eMMC Config header
******************************************************************************/
#ifndef EMMC_CONFIG_H__
#define EMMC_CONFIG_H__
/* ************************ HEADER (INCLUDE) SECTION *********************** */
#include "cpg_register.h"
#include "pfc_register.h"
#include "cpg.h"
#include "pfc.h"
/* ***************** MACROS, CONSTANTS, COMPILATION FLAGS ****************** */
/* MMC driver config */
#define EMMC_RCA (1U) /* RCA */
#define EMMC_RW_DATA_TIMEOUT (0x40U) /* 314ms (freq = 400KHz, timeout Counter = 0x04(SDCLK * 2^17) */
#define EMMC_CMD_MAX (60U) /* Don't change. */
/* etc */
#define LOADIMAGE_FLAGS_DMA_ENABLE (0x00000001U)
/* Module stop */
#define CPG_MSTPCR_SDHI (1U << 6U)
/* clock */
#define CPG_SD0CKCR0_STP0HCK (1U << 9U)
#define CPG_SD0CKCR0_SDSRCFC_MASK (7U << 2U)
#define CPG_SD0CKCR0_SDSRCFC_000 (0U << 2U)
#define CPG_SD0CKCR0_SDSRCFC_010 (2U << 2U)
#define CPG_SD0CKCR0_SD0FC_MASK (3U << 0U)
#define CPG_SD0CKCR0_SD0FC_DIV2 (0U << 0U)
#define CPG_SD0CKCR0_SD0FC_DIV4 (1U << 0U)
#define CPG_SD0CKCR0_100MHZ (CPG_SD0CKCR0_STP0HCK | CPG_SD0CKCR0_SDSRCFC_010 | CPG_SD0CKCR0_SD0FC_DIV2)
#define CPG_SD0CKCR0_200MHZ (CPG_SD0CKCR0_STP0HCK | CPG_SD0CKCR0_SDSRCFC_000 | CPG_SD0CKCR0_SD0FC_DIV4)
#if (RCAR_LSI == RCAR_S4)
#define PFC_POC_MMC_RW (PFC_POC1_RW)
#define PFC_POC_MMC_MASK (0x007FF000U)
#define PFC_POC_MMC_VAL (0x00000000U)
#elif ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M))
#define PFC_POC_MMC_RW (PFC_POC3_RW)
#define PFC_POC_MMC_MASK (0x000007FFU)
#define PFC_POC_MMC_VAL (0x00000000U)
#endif /* RCAR_LSI == RCAR_S4 */
/* ********************** STRUCTURES, TYPE DEFINITIONS ********************* */
/* ********************** DECLARATION OF EXTERNAL DATA ********************* */
/* ************************** FUNCTION PROTOTYPES ************************** */
/* ********************************* CODE ********************************** */
#endif /* #ifndef EMMC_CONFIG_H__ */
/* ******************************** END ************************************ */

74
Src/0_Tool/Gen4_R-Car_IPL/SDK/v3_46_0/Gen4_ICUMX_Loader/include/emmc_def.h Normal file
View File

@@ -0,0 +1,74 @@
/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright 2021-2022 Renesas Electronics Corporation All rights reserved.
*******************************************************************************/
/*******************************************************************************
* DESCRIPTION : eMMC Define header
******************************************************************************/
#ifndef EMMC_DEF_H__
#define EMMC_DEF_H__
/* ************************ HEADER (INCLUDE) SECTION *********************** */
#include "emmc_std.h"
/* ***************** MACROS, CONSTANTS, COMPILATION FLAGS ****************** */
#define EMMC_DEV_OK (0x525F4F4BU) /* "R_OK" */
#define EMMC_DEV_ERR (0xFFFFFFFFU)
#define EMMC_DEV_ERR_HW (0x00000004U)
#define EMMC_DEV_ERR_FAULT_INJECTION (0x00000005U)
/* ********************** STRUCTURES, TYPE DEFINITIONS ********************* */
/* ********************** DECLARATION OF EXTERNAL DATA ********************* */
extern st_mmc_base mmc_drv_obj;
/* ************************** FUNCTION PROTOTYPES ************************** */
/* eMMC driver API */
EMMC_ERROR_CODE emmc_init(void);
EMMC_ERROR_CODE emmc_terminate(void);
EMMC_ERROR_CODE emmc_memcard_power(uint32_t mode);
EMMC_ERROR_CODE emmc_mount(void);
EMMC_ERROR_CODE emmc_set_request_mmc_clock(const uint32_t *freq);
EMMC_ERROR_CODE emmc_send_idle_cmd (uint32_t arg);
EMMC_ERROR_CODE emmc_select_partition(EMMC_PARTITION_ID id);
EMMC_ERROR_CODE emmc_read_sector(uint32_t *buff_address_virtual, uint32_t sector_number, uint32_t count, uint32_t feature_flags);
uint32_t emmc_bit_field (const uint8_t *data, uint32_t top, uint32_t bottom);
/* interrupt service */
uint32_t emmc_interrupt(void);
/* send command API */
EMMC_ERROR_CODE emmc_exec_cmd (uint32_t error_mask, uint32_t *response);
void emmc_make_nontrans_cmd (HAL_MEMCARD_COMMAND cmd, uint32_t arg);
void emmc_make_trans_cmd (HAL_MEMCARD_COMMAND cmd, uint32_t arg, uint32_t *buff_address_virtual,
uint32_t len, HAL_MEMCARD_OPERATION dir, HAL_MEMCARD_DATA_TRANSFER_MODE transfer_mode);
EMMC_ERROR_CODE emmc_set_ext_csd(uint32_t arg);
/* ********************************* CODE ********************************** */
#endif /* #define EMMC_DEF_H__ */
/* ******************************** END ************************************ */

162
Src/0_Tool/Gen4_R-Car_IPL/SDK/v3_46_0/Gen4_ICUMX_Loader/include/emmc_hal.h Normal file
View File

@@ -0,0 +1,162 @@
/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright 2021-2022 Renesas Electronics Corporation All rights reserved.
*******************************************************************************/
/*******************************************************************************
* DESCRIPTION : eMMC HAL driverd header
******************************************************************************/
#ifndef EMMC_HAL_H__
#define EMMC_HAL_H__
/* ************************ HEADER (INCLUDE) SECTION *********************** */
#include <types.h>
/* ***************** MACROS, CONSTANTS, COMPILATION FLAGS ****************** */
/* Memory card response types */
#define HAL_MEMCARD_COMMAND_INDEX_MASK (0x0003fU)
/* ********************** STRUCTURES, TYPE DEFINITIONS ********************* */
/* memory access operation */
typedef enum
{
HAL_MEMCARD_READ = 0U, /**< read */
HAL_MEMCARD_WRITE = 1U /**< write */
} HAL_MEMCARD_OPERATION;
/* Type of data width on memorycard bus */
typedef enum
{
HAL_MEMCARD_DATA_WIDTH_1_BIT = 0U,
HAL_MEMCARD_DATA_WIDTH_4_BIT = 1U,
HAL_MEMCARD_DATA_WIDTH_8_BIT = 2U
} HAL_MEMCARD_DATA_WIDTH; /**< data (bus) width types */
/* mode of data transfer */
typedef enum
{
HAL_MEMCARD_DMA = 0U,
HAL_MEMCARD_NOT_DMA = 1U
} HAL_MEMCARD_DATA_TRANSFER_MODE;
/* Memory card response types. */
typedef enum hal_memcard_response_type
{
HAL_MEMCARD_RESPONSE_NONE = 0x00000U,
HAL_MEMCARD_RESPONSE_R1 = 0x00100U,
HAL_MEMCARD_RESPONSE_R1b = 0x00200U,
HAL_MEMCARD_RESPONSE_R2 = 0x00300U,
HAL_MEMCARD_RESPONSE_R3 = 0x00400U,
HAL_MEMCARD_RESPONSE_R4 = 0x00500U,
HAL_MEMCARD_RESPONSE_R5 = 0x00600U,
HAL_MEMCARD_RESPONSE_R6 = 0x00700U,
HAL_MEMCARD_RESPONSE_R7 = 0x00800U,
HAL_MEMCARD_RESPONSE_TYPE_MASK = 0x00f00U
} HAL_MEMCARD_RESPONSE_TYPE;
/* Memory card command types. */
typedef enum hal_memcard_command_type
{
HAL_MEMCARD_COMMAND_TYPE_BC = 0x00000U,
HAL_MEMCARD_COMMAND_TYPE_BCR = 0x01000U,
HAL_MEMCARD_COMMAND_TYPE_AC = 0x02000U,
HAL_MEMCARD_COMMAND_TYPE_ADTC_WRITE = 0x03000U,
HAL_MEMCARD_COMMAND_TYPE_ADTC_READ = 0x04000U,
HAL_MEMCARD_COMMAND_TYPE_MASK = 0x07000U
} HAL_MEMCARD_COMMAND_TYPE;
/* Type of memory card */
typedef enum hal_memcard_command_card_type
{
HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON = 0x00000U,
HAL_MEMCARD_COMMAND_CARD_TYPE_MMC = 0x08000U,
HAL_MEMCARD_COMMAND_CARD_TYPE_SD = 0x10000U,
HAL_MEMCARD_COMMAND_CARD_TYPE_MASK = 0x18000U
} HAL_MEMCARD_COMMAND_CARD_TYPE;
/* Memory card application command. */
typedef enum hal_memcard_command_app_norm
{
HAL_MEMCARD_COMMAND_NORMAL = 0x00000U,
HAL_MEMCARD_COMMAND_APP = 0x20000U,
HAL_MEMCARD_COMMAND_APP_NORM_MASK = 0x20000U
} HAL_MEMCARD_COMMAND_APP_NORM;
/* Memory card command codes. */
typedef enum
{
/* class 0 and class 1 */
CMD0_GO_IDLE_STATE = 0 | HAL_MEMCARD_RESPONSE_NONE | HAL_MEMCARD_COMMAND_TYPE_BC | HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | HAL_MEMCARD_COMMAND_NORMAL, /* CMD0 */
CMD1_SEND_OP_COND = 1 | HAL_MEMCARD_RESPONSE_R3 | HAL_MEMCARD_COMMAND_TYPE_BCR | HAL_MEMCARD_COMMAND_CARD_TYPE_MMC | HAL_MEMCARD_COMMAND_NORMAL, /* CMD1 */
CMD2_ALL_SEND_CID_MMC = 2 | HAL_MEMCARD_RESPONSE_R2 | HAL_MEMCARD_COMMAND_TYPE_BCR | HAL_MEMCARD_COMMAND_CARD_TYPE_MMC | HAL_MEMCARD_COMMAND_NORMAL, /* CMD2 */
CMD2_ALL_SEND_CID_SD = 2 | HAL_MEMCARD_RESPONSE_R2 | HAL_MEMCARD_COMMAND_TYPE_BCR | HAL_MEMCARD_COMMAND_CARD_TYPE_SD | HAL_MEMCARD_COMMAND_NORMAL,
CMD3_SET_RELATIVE_ADDR = 3 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_MMC | HAL_MEMCARD_COMMAND_NORMAL, /* CMD3 */
CMD3_SEND_RELATIVE_ADDR = 3 | HAL_MEMCARD_RESPONSE_R6 | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_SD | HAL_MEMCARD_COMMAND_NORMAL,
CMD4_SET_DSR = 4 | HAL_MEMCARD_RESPONSE_NONE | HAL_MEMCARD_COMMAND_TYPE_BC | HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | HAL_MEMCARD_COMMAND_NORMAL, /* CMD4 */
CMD5_SLEEP_AWAKE = 5 | HAL_MEMCARD_RESPONSE_R1b | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_MMC | HAL_MEMCARD_COMMAND_NORMAL, /* CMD5 */
CMD6_SWITCH = 6 | HAL_MEMCARD_RESPONSE_R1b | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_MMC | HAL_MEMCARD_COMMAND_NORMAL, /* CMD6 */
CMD6_SWITCH_FUNC = 6 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_SD | HAL_MEMCARD_COMMAND_NORMAL,
ACMD6_SET_BUS_WIDTH = 6 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_SD | HAL_MEMCARD_COMMAND_APP,
CMD7_SELECT_CARD = 7 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | HAL_MEMCARD_COMMAND_NORMAL, /* CMD7 */
CMD7_SELECT_CARD_PROG = 7 | HAL_MEMCARD_RESPONSE_R1b | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | HAL_MEMCARD_COMMAND_NORMAL, /* CMD7(from Disconnected State to Programming State) */
CMD7_DESELECT_CARD = 7 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | HAL_MEMCARD_COMMAND_NORMAL,
CMD8_SEND_EXT_CSD = 8 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_ADTC_READ | HAL_MEMCARD_COMMAND_CARD_TYPE_MMC | HAL_MEMCARD_COMMAND_NORMAL, /* CMD8 */
CMD8_SEND_IF_COND = 8 | HAL_MEMCARD_RESPONSE_R7 | HAL_MEMCARD_COMMAND_TYPE_BCR | HAL_MEMCARD_COMMAND_CARD_TYPE_SD | HAL_MEMCARD_COMMAND_NORMAL,
CMD9_SEND_CSD = 9 | HAL_MEMCARD_RESPONSE_R2 | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | HAL_MEMCARD_COMMAND_NORMAL, /* CMD9 */
CMD10_SEND_CID = 10 | HAL_MEMCARD_RESPONSE_R2 | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | HAL_MEMCARD_COMMAND_NORMAL, /* CMD10 */
CMD11_READ_DAT_UNTIL_STOP = 11 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_ADTC_READ | HAL_MEMCARD_COMMAND_CARD_TYPE_SD | HAL_MEMCARD_COMMAND_NORMAL, /* CMD11 */
CMD12_STOP_TRANSMISSION = 12 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | HAL_MEMCARD_COMMAND_NORMAL, /* CMD12 */
CMD12_STOP_TRANSMISSION_WRITE = 12 | HAL_MEMCARD_RESPONSE_R1b | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | HAL_MEMCARD_COMMAND_NORMAL, /* CMD12 R1b : write case */
CMD13_SEND_STATUS = 13 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | HAL_MEMCARD_COMMAND_NORMAL, /* CMD13 */
ACMD13_SD_STATUS = 13 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_ADTC_READ | HAL_MEMCARD_COMMAND_CARD_TYPE_SD | HAL_MEMCARD_COMMAND_APP,
CMD14_BUSTEST_R = 14 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_ADTC_READ | HAL_MEMCARD_COMMAND_CARD_TYPE_MMC | HAL_MEMCARD_COMMAND_NORMAL, /* CMD14 */
CMD15_GO_INACTIVE_STATE = 15 | HAL_MEMCARD_RESPONSE_NONE | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | HAL_MEMCARD_COMMAND_NORMAL, /* CMD15 */
/* class 2 */
CMD16_SET_BLOCKLEN = 16 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | HAL_MEMCARD_COMMAND_NORMAL, /* CMD16 */
CMD17_READ_SINGLE_BLOCK = 17 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_ADTC_READ | HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | HAL_MEMCARD_COMMAND_NORMAL, /* CMD17 */
CMD18_READ_MULTIPLE_BLOCK = 18 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_ADTC_READ | HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | HAL_MEMCARD_COMMAND_NORMAL, /* CMD18 */
CMD19_BUS_TEST_W = 19 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_ADTC_WRITE | HAL_MEMCARD_COMMAND_CARD_TYPE_MMC | HAL_MEMCARD_COMMAND_NORMAL, /* CMD19 */
/* class 3 */
CMD20_WRITE_DAT_UNTIL_STOP = 20 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_ADTC_WRITE | HAL_MEMCARD_COMMAND_CARD_TYPE_MMC | HAL_MEMCARD_COMMAND_NORMAL, /* CMD20 */
CMD21 = 21, /* CMD21 */
CMD22 = 22, /* CMD22 */
ACMD22_SEND_NUM_WR_BLOCKS = 22 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_SD | HAL_MEMCARD_COMMAND_APP,
/* class 4 */
CMD23_SET_BLOCK_COUNT = 23 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_MMC | HAL_MEMCARD_COMMAND_NORMAL /* CMD23 */
} HAL_MEMCARD_COMMAND;
/* ********************** DECLARATION OF EXTERNAL DATA ********************* */
/* ************************** FUNCTION PROTOTYPES ************************** */
/* ********************************* CODE ********************************** */
#endif /* EMMC_HAL_H__ */
/* ******************************** END ************************************ */

44
Src/0_Tool/Gen4_R-Car_IPL/SDK/v3_46_0/Gen4_ICUMX_Loader/include/emmc_multiboot.h Normal file
View File

@@ -0,0 +1,44 @@
/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright 2021-2022 Renesas Electronics Corporation All rights reserved.
*******************************************************************************/
/*******************************************************************************
* DESCRIPTION : eMMC Multi boot header
******************************************************************************/
#ifndef EMMC_MULTIBOOT_H_
#define EMMC_MULTIBOOT_H_
/* ************************ HEADER (INCLUDE) SECTION *********************** */
/* ***************** MACROS, CONSTANTS, COMPILATION FLAGS ****************** */
/* ********************** STRUCTURES, TYPE DEFINITIONS ********************* */
/* ********************** DECLARATION OF EXTERNAL DATA ********************* */
/* ************************** FUNCTION PROTOTYPES ************************** */
uint32_t emmc_trans_data(uint32_t next_bootPartition, uintptr_t sourceSct, uintptr_t targetAd, uint32_t sectorSize);
/* ******************************** END ************************************ */
#endif /* #ifndef EMMC_MULTIBOOT_H_*/

146
Src/0_Tool/Gen4_R-Car_IPL/SDK/v3_46_0/Gen4_ICUMX_Loader/include/emmc_registers.h Normal file
View File

@@ -0,0 +1,146 @@
/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright 2021-2022 Renesas Electronics Corporation All rights reserved.
*******************************************************************************/
/*******************************************************************************
* DESCRIPTION : eMMC register header
******************************************************************************/
#ifndef EMMC_REGISTERS_H__
#define EMMC_REGISTERS_H__
/* ************************ HEADER (INCLUDE) SECTION *********************** */
#include <remap_register.h>
/* ***************** MACROS, CONSTANTS, COMPILATION FLAGS ****************** */
/* MMC0 channel */
#define MMC0_SD_BASE (BASE_MMC0_ADDR) /* reg addr is 0xEE140000U */
#define SD_CMD (MMC0_SD_BASE + 0x0000U)
#define SD_ARG (MMC0_SD_BASE + 0x0010U)
#define SD_STOP (MMC0_SD_BASE + 0x0020U)
#define SD_SECCNT (MMC0_SD_BASE + 0x0028U)
#define SD_RSP10 (MMC0_SD_BASE + 0x0030U)
#define SD_RSP32 (MMC0_SD_BASE + 0x0040U)
#define SD_RSP54 (MMC0_SD_BASE + 0x0050U)
#define SD_RSP76 (MMC0_SD_BASE + 0x0060U)
#define SD_INFO1 (MMC0_SD_BASE + 0x0070U)
#define SD_INFO2 (MMC0_SD_BASE + 0x0078U)
#define SD_INFO1_MASK (MMC0_SD_BASE + 0x0080U)
#define SD_INFO2_MASK (MMC0_SD_BASE + 0x0088U)
#define SD_CLK_CTRL (MMC0_SD_BASE + 0x0090U)
#define SD_SIZE (MMC0_SD_BASE + 0x0098U)
#define SD_OPTION (MMC0_SD_BASE + 0x00A0U)
#define SD_ERR_STS1 (MMC0_SD_BASE + 0x00B0U)
#define SD_ERR_STS2 (MMC0_SD_BASE + 0x00B8U)
#define SD_BUF0 (MMC0_SD_BASE + 0x00C0U)
#define CC_EXT_MODE (MMC0_SD_BASE + 0x0360U)
#define SOFT_RST (MMC0_SD_BASE + 0x0380U)
#define HOST_MODE (MMC0_SD_BASE + 0x0390U)
#define DM_CM_DTRAN_MODE (MMC0_SD_BASE + 0x0820U)
#define DM_CM_DTRAN_CTRL (MMC0_SD_BASE + 0x0828U)
#define DM_CM_INFO1 (MMC0_SD_BASE + 0x0840U)
#define DM_CM_INFO1_MASK (MMC0_SD_BASE + 0x0848U)
#define DM_CM_INFO2 (MMC0_SD_BASE + 0x0850U)
#define DM_CM_INFO2_MASK (MMC0_SD_BASE + 0x0858U)
#define DM_DTRAN_ADDR (MMC0_SD_BASE + 0x0880U)
/* SD_INFO1 Registers */
#define SD_INFO1_INFO2 (0x00000004U) /* Access end */
#define SD_INFO1_INFO0 (0x00000001U) /* Response end */
/* SD_INFO2 Registers */
#define SD_INFO2_CBSY (0x00004000U) /* Command Type Register Busy */
#define SD_INFO2_BWE (0x00000200U) /* SD_BUF Write Enable */
#define SD_INFO2_BRE (0x00000100U) /* SD_BUF Read Enable */
#define SD_INFO2_DAT0 (0x00000080U) /* SDDAT0 */
#define SD_INFO2_ALL_ERR (0x0000807FU)
#define SD_INFO2_CLEAR (0x00000800U) /* BIT11 The write value should always be 1. HWM_0003 */
/* DM_INFO1 Registers */
#define DM_CM_INFO_DTRANEND0 (0x00010000U) /* DMAC Channel 0 Transfer End */
#define DM_CM_INFO_DTRANEND1 (0x00020000U) /* DMAC Channel 0 Transfer End */
/* SOFT_RST */
#define SOFT_RST_SDRST (0x00000001U)
/* SD_CLK_CTRL */
#define SD_CLK_CTRL_CLKDIV_MASK (0x000000FFU)
#define SD_CLK_WRITE_MASK (0x000003FFU)
/* SD_OPTION */
#define SD_OPTION_WIDTH (0x00008000U)
#define SD_OPTION_WIDTH8 (0x00002000U)
#define SD_OPTION_TIMEOUT_CNT_MASK (0x000000F0U)
/* MMC Clock Frequency
* 200MHz * 1/x = output clock
*/
#define MMC_400KHZ (512U) /* 200MHz * 1/512 = 390 KHz */
#define MMC_20MHZ (16U) /* 200MHz * 1/16 = 12.5 MHz Normal speed mode */
#define MMC_26MHZ (8U) /* 200MHz * 1/8 = 25 MHz High speed mode 26Mhz */
#define MMC_52MHZ (4U) /* 200MHz * 1/4 = 50 MHz High speed mode 52Mhz */
#define MMC_FREQ_52MHZ (52000000U)
#define MMC_FREQ_26MHZ (26000000U)
#define MMC_FREQ_20MHZ (20000000U)
/* MMC Clock DIV */
#define MMC_SD_CLK_START (0x00000100U) /* CLOCK On */
#define MMC_SD_CLK_STOP (~0x00000100UL) /* CLOCK stop */
/* DM_CM_DTRAN_MODE */
#define DM_CM_DTRAN_MODE_CH0 (0x00000000U) /* CH0 : downstream */
#define DM_CM_DTRAN_MODE_CH1 (0x00010000U) /* CH1 : upstream */
#define DM_CM_DTRAN_MODE_BIT_WIDTH (0x00000030U)
/* CC_EXT_MODE */
#define CC_EXT_MODE_DMASDRW_ENABLE (0x00000002U) /* SD_BUF Read/Write DMA Transfer */
#define CC_EXT_MODE_CLEAR (0x00001010U) /* BIT 12 & 4 always 1. */
/* DM_CM_INFO_MASK */
#define DM_CM_INFO_MASK_CLEAR (0xFFFCFFFEU)
#define DM_CM_INFO_CH0_ENABLE (0x00010001U)
#define DM_CM_INFO_CH1_ENABLE (0x00020001U)
/* DM_DTRAN_ADDR */
#define DM_DTRAN_ADDR_WRITE_MASK (0xFFFFFFF8U)
/*DM_CM_DTRAN_CTRL */
#define DM_CM_DTRAN_CTRL_START (0x00000001U)
/* ********************** STRUCTURES, TYPE DEFINITIONS ********************* */
/* ********************** DECLARATION OF EXTERNAL DATA ********************* */
/* ************************** FUNCTION PROTOTYPES ************************** */
/* ********************************* CODE ********************************** */
#endif /* EMMC_REGISTERS_H__ */
/* ******************************** END ************************************ */

263
Src/0_Tool/Gen4_R-Car_IPL/SDK/v3_46_0/Gen4_ICUMX_Loader/include/emmc_std.h Normal file
View File

@@ -0,0 +1,263 @@
/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright 2021-2022 Renesas Electronics Corporation All rights reserved.
*******************************************************************************/
/*******************************************************************************
* DESCRIPTION : eMMC standard header
******************************************************************************/
#ifndef EMMC_STD_H__
#define EMMC_STD_H__
/* ************************ HEADER (INCLUDE) SECTION *********************** */
#include "emmc_hal.h"
#include "emmc_registers.h"
/* ***************** MACROS, CONSTANTS, COMPILATION FLAGS ****************** */
/*CSD register Macros */
#define EMMC_CSD_SPEC_VARS() (emmc_bit_field(mmc_drv_obj.csd_data, 125,122))
#define EMMC_CSD_TRAN_SPEED() (emmc_bit_field(mmc_drv_obj.csd_data, 103,96))
/* for sector access */
#define EMMC_SECTOR_SIZE_SHIFT (9U) /* 512 = 2^9 */
#define EMMC_SECTOR_PADD_MASK ((1U << EMMC_SECTOR_SIZE_SHIFT) - 1U)
#define EMMC_SECTOR_SIZE (512U)
#define EMMC_BLOCK_LENGTH (512U)
#define EMMC_BLOCK_LENGTH_DW (128U)
/* EMMC driver error code. (extended HAL_MEMCARD_RETURN) */
typedef enum
{
EMMC_ERR = 0U, /**< unknown error */
EMMC_SUCCESS , /**< OK */
EMMC_ERR_FROM_DMAC , /**< DMAC allocation error */
EMMC_ERR_FROM_DMAC_TRANSFER , /**< DMAC transfer error */
EMMC_ERR_CARD_STATUS_BIT , /**< card status error. Non-masked error bit was set in the card status */
EMMC_ERR_CMD_TIMEOUT , /**< command timeout error */
EMMC_ERR_DATA_TIMEOUT , /**< data timeout error */
EMMC_ERR_CMD_CRC , /**< command CRC error */
EMMC_ERR_DATA_CRC , /**< data CRC error */
EMMC_ERR_PARAM , /**< parameter error */
EMMC_ERR_RESPONSE , /**< response error */
EMMC_ERR_RESPONSE_BUSY , /**< response busy error */
EMMC_ERR_TRANSFER , /**< data transfer error */
EMMC_ERR_READ_SECTOR , /**< read sector error */
EMMC_ERR_WRITE_SECTOR , /**< write sector error */
EMMC_ERR_STATE , /**< state error */
EMMC_ERR_TIMEOUT , /**< timeout error */
EMMC_ERR_ILLEGAL_CARD , /**< illegal card */
EMMC_ERR_CARD_BUSY , /**< Busy state */
EMMC_ERR_CARD_STATE , /**< card state error */
EMMC_ERR_SET_TRACE , /**< trace information error */
EMMC_ERR_FROM_TIMER , /**< Timer error */
EMMC_ERR_FORCE_TERMINATE , /**< Force terminate */
EMMC_ERR_CARD_POWER , /**< card power fail */
EMMC_ERR_ERASE_SECTOR , /**< erase sector error */
EMMC_ERR_INFO2 /**< exec cmd error info2 */
} EMMC_ERROR_CODE;
/* Response */
/** R1 */
#define EMMC_R1_ERROR_MASK (0xFDBFE080U) /* Type 'E' bit and bit14(must be 0). ignore bit22 */
#define EMMC_R1_ERROR_MASK_WITHOUT_CRC (0xFD3FE080U) /* Ignore bit23 (Not check CRC error) */
#define EMMC_R1_STATE_MASK (0x00001E00U) /* [12:9] */
#define EMMC_R1_READY (0x00000100U) /* bit8 */
#define EMMC_R1_STATE_SHIFT (9U)
/** R4 */
#define EMMC_R4_STATUS (0x00008000U)
/** CSD */
#define EMMC_TRANSPEED_FREQ_UNIT_MASK (0x07U) /* bit[2:0] */
#define EMMC_TRANSPEED_MULT_MASK (0x78U) /* bit[6:3] */
#define EMMC_TRANSPEED_MULT_SHIFT (3U)
/** OCR */
#define EMMC_HOST_OCR_VALUE (0x40FF8080U)
#define EMMC_OCR_STATUS_BIT (0x80000000U) /* Card power up status bit */
#define EMMC_OCR_ACCESS_MODE_MASK (0x60000000U) /* bit[30:29] */
#define EMMC_OCR_ACCESS_MODE_SECT (0x40000000U)
/** EXT_CSD */
#define EMMC_EXT_CSD_CARD_TYPE (196U)
#define EMMC_EXT_CSD_PARTITION_CONFIG (179U)
#define EMMC_EXT_CSD_CARD_TYPE_26MHZ (0x01U)
#define EMMC_EXT_CSD_CARD_TYPE_52MHZ (0x02U)
/** SWITCH (CMD6) argument */
#define EXTCSD_ACCESS_BYTE (0x03000000U)
#define HS_TIMING_ADD (185U<<16U) /* H'b9 */
#define HS_TIMING_1 (1U<<8U)
#define BUS_WIDTH_ADD (183U<<16U) /* H'b7 */
#define BUS_WIDTH_1 (0U<<8U)
#define EMMC_SWITCH_HS_TIMING (EXTCSD_ACCESS_BYTE|HS_TIMING_ADD|HS_TIMING_1) /**< H'03b90100 */
#define EMMC_SWITCH_BUS_WIDTH_1 (EXTCSD_ACCESS_BYTE|BUS_WIDTH_ADD|BUS_WIDTH_1) /**< H'03b70000 */
#define EMMC_SWITCH_PARTITION_CONFIG 0x03B30000UL /**< Partition config = 0x00 */
/** for st_mmc_base */
#define EMMC_MAX_RESPONSE_LENGTH (17U)
#define EMMC_MAX_CID_LENGTH (16U)
#define EMMC_MAX_CSD_LENGTH (16U)
#define EMMC_MAX_EXT_CSD_LENGTH (512U)
/* ********************** STRUCTURES, TYPE DEFINITIONS ********************* */
/* Partition id */
typedef enum
{
PARTITION_ID_USER = 0x0, /**< User Area */
PARTITION_ID_BOOT_1 = 0x1, /**< boot partition 1 */
PARTITION_ID_BOOT_2 = 0x2, /**< boot partition 2 */
PARTITION_ID_RPMB = 0x3, /**< Replay Protected Memory Block */
PARTITION_ID_GP_1 = 0x4, /**< General Purpose partition 1 */
PARTITION_ID_GP_2 = 0x5, /**< General Purpose partition 2 */
PARTITION_ID_GP_3 = 0x6, /**< General Purpose partition 3 */
PARTITION_ID_GP_4 = 0x7, /**< General Purpose partition 4 */
PARTITION_ID_MASK = 0x7 /**< [2:0] */
} EMMC_PARTITION_ID;
/* card state in R1 response [12:9] */
typedef enum
{
EMMC_R1_STATE_IDLE = 0,
EMMC_R1_STATE_READY,
EMMC_R1_STATE_IDENT,
EMMC_R1_STATE_STBY,
EMMC_R1_STATE_TRAN,
EMMC_R1_STATE_DATA,
EMMC_R1_STATE_RCV,
EMMC_R1_STATE_PRG,
EMMC_R1_STATE_DIS,
EMMC_R1_STATE_BTST,
EMMC_R1_STATE_SLEP
} EMMC_R1_STATE;
typedef enum{
ESTATE_BEGIN = 0,
ESTATE_ISSUE_CMD,
ESTATE_NON_RESP_CMD,
ESTATE_RCV_RESP,
ESTATE_RCV_RESPONSE_BUSY,
ESTATE_CHECK_RESPONSE_COMPLETE,
ESTATE_DATA_TRANSFER,
ESTATE_DATA_TRANSFER_COMPLETE,
ESTATE_ACCESS_END,
ESTATE_TRANSFER_ERROR,
ESTATE_ERROR,
ESTATE_END
}EMMC_INT_STATE;
/* eMMC boot driver error information */
typedef struct
{
volatile uint32_t info1; /**< SD_INFO1 register value. (hardware dependence) */
volatile uint32_t info2; /**< SD_INFO2 register value. (hardware dependence) */
volatile uint32_t status1; /**< SD_ERR_STS1 register value. (hardware dependence) */
volatile uint32_t status2; /**< SD_ERR_STS2 register value. (hardware dependence) */
volatile uint32_t dm_info1; /**< DM_CM_INFO1 register value. (hardware dependence) */
volatile uint32_t dm_info2; /**< DM_CM_INFO2 register value. (hardware dependence) */
} st_error_info;
/* Command information */
typedef struct
{
HAL_MEMCARD_COMMAND cmd; /**< Command information */
uint32_t arg; /**< argument */
HAL_MEMCARD_OPERATION dir; /**< direction */
uint32_t hw; /**< H/W dependence. SD_CMD register value. */
} st_command_info;
/* MMC driver base */
typedef struct
{
st_error_info error_info; /**< error information */
st_command_info cmd_info; /**< command information */
/* for data transfer */
uint32_t *buff_address_virtual; /**< Dest or Src buff */
uint32_t *buff_address_physical; /**< Dest or Src buff */
HAL_MEMCARD_DATA_WIDTH bus_width; /**< bus width */
uint32_t trans_size; /**< transfer size for this command */
uint32_t remain_size; /**< remain size for this command */
uint32_t response_length; /**< response length for this command */
/* clock */
uint32_t max_freq; /**< Max frequency (Card Spec)[Hz]. It changes dynamically by CSD and EXT_CSD. */
uint32_t current_freq; /**< current MMC clock[Hz] (the closest frequency supported by HW) */
/* state flag */
uint32_t card_power_enable; /**< True : Power ON */
uint32_t clock_enable; /**< True : Clock ON */
uint32_t initialize; /**< True : initialize complete. */
uint32_t mount; /**< True : mount complete. */
uint32_t selected; /**< True : selected card. */
HAL_MEMCARD_DATA_TRANSFER_MODE transfer_mode; /**< 0: DMA, 1:PIO */
EMMC_R1_STATE current_state; /**< card state */
volatile uint32_t during_transfer; /**< True : during transfer */
volatile uint32_t during_dma_transfer; /**< True : during transfer (DMA)*/
volatile uint32_t dma_error_flag; /**< True : occurred DMAC error */
volatile uint32_t force_terminate; /**< force terminate flag */
volatile uint32_t state_machine_blocking; /**< state machine blocking flag : True or False */
/* timeout */
uint32_t data_timeout; /**< read and write data timeout.*/
/* interrupt */
volatile uint32_t int_event1; /**< interrupt SD_INFO1 Event */
volatile uint32_t int_event2; /**< interrupt SD_INFO2 Event */
volatile uint32_t dm_event1; /**< interrupt DM_CM_INFO1 Event */
volatile uint32_t dm_event2; /**< interrupt DM_CM_INFO2 Event */
/* response */
uint32_t *response; /**< pointer to buffer for executing command. */
uint32_t r1_card_status; /**< R1 response data */
uint32_t r3_ocr; /**< R3 response data */
uint32_t r4_resp; /**< R4 response data */
uint32_t r5_resp; /**< R5 response data */
/* Card registers (4byte align) */
uint8_t csd_data[EMMC_MAX_CSD_LENGTH]; /**< CSD */
uint8_t cid_data[EMMC_MAX_CID_LENGTH]; /**< CID */
uint8_t ext_csd_data[EMMC_MAX_EXT_CSD_LENGTH]; /**< EXT_CSD */
uint8_t response_data[EMMC_MAX_RESPONSE_LENGTH]; /**< other response */
/* SDHI base address */
uintptr_t base_address;
} st_mmc_base;
/* ********************** DECLARATION OF EXTERNAL DATA ********************* */
/* ************************** FUNCTION PROTOTYPES ************************** */
/* ********************************* CODE ********************************** */
/* ******************************** END ************************************ */
#endif /* EMMC_STD_H__ */
/* EMMC_STD_H__ */

48
Src/0_Tool/Gen4_R-Car_IPL/SDK/v3_46_0/Gen4_ICUMX_Loader/include/fcpr.h Normal file
View File

@@ -0,0 +1,48 @@
/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright 2022-2025 Renesas Electronics Corporation All rights reserved.
*******************************************************************************/
/*******************************************************************************
* DESCRIPTION : FCPR driver header
******************************************************************************/
#ifndef FCPR_H__
#define FCPR_H__
#include <fcpr_register.h>
/************************************************************************************************/
/* Definitions */
/************************************************************************************************/
#define FCPR_DISABLE (0U)
#define FCPR_ENABLE (1U)
#if (SET_FCPR_PARAM == FCPR_ENABLE)
#define COMPRESSION_START_ADDR (0x80000000U)
#define COMPRESSION_END_ADDR (0xA2FFFFFFU)
#define COMPRESSION_ENABLE (0x00000001U)
#define AXI_FCPRC_ENABLE (0x00000001U) /* Bit0 */
#endif /* (SET_FCPR_PARAM == FCPR_ENABLE) */
void fcpr_init(void);
#endif /* FCPR_H__ */

47
Src/0_Tool/Gen4_R-Car_IPL/SDK/v3_46_0/Gen4_ICUMX_Loader/include/fcpr_register.h Normal file
View File

@@ -0,0 +1,47 @@
/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright 2022 Renesas Electronics Corporation All rights reserved.
*******************************************************************************/
/*******************************************************************************
* DESCRIPTION : FCPR register header
******************************************************************************/
#ifndef FCPR_REGISTER_H__
#define FCPR_REGISTER_H__
#include <remap_register.h>
/************************************************************************************************/
/* Definitions */
/************************************************************************************************/
/* CPG base address */
/* 0xE6785700 */
#define FCPR_BASE (BASE_FCPR_ADDR)
/* FCPR */
#define FCPR_CMP_CTRL (BASE_FCPR_ADDR + 0x0030U)
#define FCPR_CMP_SPACE (BASE_FCPR_ADDR + 0x0080U)
#define FCPR_CMP_STADR (BASE_FCPR_ADDR + 0x0084U)
#define FCPR_CMP_EDADR (BASE_FCPR_ADDR + 0x0088U)
#define QOS_AXI_FCPRC (BASE_QOS_ADDR + 0x10090U)
#endif /* FCPR_REGISTER_H__ */

49
Src/0_Tool/Gen4_R-Car_IPL/SDK/v3_46_0/Gen4_ICUMX_Loader/include/hscif_register.h Normal file
View File

@@ -0,0 +1,49 @@
/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright 2021-2022 Renesas Electronics Corporation All rights reserved.
*******************************************************************************/
/*******************************************************************************
* DESCRIPTION : HSCIF register header
******************************************************************************/
#ifndef HSCIF_REGISTER_H_
#define HSCIF_REGISTER_H_
#include <remap_register.h>
/* HSCIF0 base address */
/* 0xE6540000U */
#define HSCIF0_BASE (BASE_HSCIF_ADDR)
#define HSCIF_HSSMR (HSCIF0_BASE + 0x0000U) /* 16 Serial mode register */
#define HSCIF_HSBRR (HSCIF0_BASE + 0x0004U) /* 8 Bit rate register */
#define HSCIF_HSSCR (HSCIF0_BASE + 0x0008U) /* 16 Serial control register */
#define HSCIF_HSFTDR (HSCIF0_BASE + 0x000CU) /* 8 Transmit FIFO data register */
#define HSCIF_HSFSR (HSCIF0_BASE + 0x0010U) /* 16 Serial status register */
#define HSCIF_HSFCR (HSCIF0_BASE + 0x0018U) /* 16 FIFO control register */
#define HSCIF_HSLSR (HSCIF0_BASE + 0x0024U) /* 16 Line status register */
#define HSCIF_DL (HSCIF0_BASE + 0x0030U) /* 16 Frequency division register */
#define HSCIF_CKS (HSCIF0_BASE + 0x0034U) /* 16 Clock Select register */
#define HSCIF_HSSRR (HSCIF0_BASE + 0x0040U) /* 16 Sampling rate register */
#endif /* HSCIF_REGISTER_H_ */

65
Src/0_Tool/Gen4_R-Car_IPL/SDK/v3_46_0/Gen4_ICUMX_Loader/include/i2c.h Normal file
View File

@@ -0,0 +1,65 @@
/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright 2024 Renesas Electronics Corporation All rights reserved.
*******************************************************************************/
/*******************************************************************************
* DESCRIPTION : I2C driver header
******************************************************************************/
#ifndef I2C_DRIVER_H__
#define I2C_DRIVER_H__
#define FLG_RW (0x00000001U)
#define I2C_OK (0x00000000U)
#define I2C_NG (0x00000001U)
#define SET_SCGD (0x00000018U)
#define SET_CDF (0x00000007U)
#define FLAG_MDBS (0x00000080U)
#define FLAG_FSCL (0x00000040U)
#define FLAG_FSDA (0x00000020U)
#define FLAG_MIE (0x00000008U)
#define FLAG_FSB (0x00000002U)
#define FLAG_ESG (0x00000001U)
#define FLAG_MNR (0x00000040U)
#define FLAG_MAL (0x00000020U)
#define FLAG_MST (0x00000010U)
#define FLAG_MDE (0x00000008U)
#define FLAG_MDT (0x00000004U)
#define FLAG_MDR (0x00000002U)
#define FLAG_MAT (0x00000001U)
#define FLAG_NONE (0U)
#define ERR_MAX (1U)
void i2c3_init(void);
void i2c3_write(uint32_t slaveAdd, uint32_t regAdd, uint32_t setData);
void i2c3_read(uint32_t slaveAdd, uint32_t regAdd, uint32_t *revData);
uint32_t i2c3_err_check(uint32_t first, uint32_t second, uint32_t error);
void i2c3_release(void);
#endif /* I2C_DRIVER_H__ */

62
Src/0_Tool/Gen4_R-Car_IPL/SDK/v3_46_0/Gen4_ICUMX_Loader/include/i2c_register.h Normal file
View File

@@ -0,0 +1,62 @@
/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright 2023 Renesas Electronics Corporation All rights reserved.
*******************************************************************************/
/*******************************************************************************
* DESCRIPTION : I2C register header
******************************************************************************/
#ifndef I2C_REGISTER_H__
#define I2C_REGISTER_H__
#include <remap_register.h>
/* I2C ch6 base address */
#define I2C3_BASE (BASE_I2C3_ADDR) /* Physical address:0xE66D0000, Logical address:0xFDCD0000 */
/* Slave control register */
#define I2C3_ICSCR (I2C3_BASE + 0x0000U)
/* Master control register */
#define I2C3_ICMCR (I2C3_BASE + 0x0004U)
/* Slave status register */
#define I2C3_ICSSR (I2C3_BASE + 0x0008U)
/* Master status register */
#define I2C3_ICMSR (I2C3_BASE + 0x000CU)
/* Slave interrupt enable register */
#define I2C3_ICSIER (I2C3_BASE + 0x0010U)
/* Master interrupt enable register */
#define I2C3_ICMIER (I2C3_BASE + 0x0014U)
/* Clock control register */
#define I2C3_ICCCR (I2C3_BASE + 0x0018U)
/* Slave address register */
#define I2C3_ICSAR (I2C3_BASE + 0x001CU)
/* Master address register */
#define I2C3_ICMAR (I2C3_BASE + 0x0020U)
/* Recieve data register */
#define I2C3_ICRXD (I2C3_BASE + 0x0024U)
/* Transmit data register */
#define I2C3_ICTXD (I2C3_BASE + 0x0024U)
/* Clock control register 2 */
#define I2C3_ICCCR2 (I2C3_BASE + 0x0028U)
#endif /* I2C_REGISTER_H__ */

150
Src/0_Tool/Gen4_R-Car_IPL/SDK/v3_46_0/Gen4_ICUMX_Loader/include/image_load.h Normal file
View File

@@ -0,0 +1,150 @@
/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright 2021-2025 Renesas Electronics Corporation All rights reserved.
*******************************************************************************/
/*******************************************************************************
* DESCRIPTION : Image load function header
******************************************************************************/
#ifndef LOAD_IMAGE_H_
#define LOAD_IMAGE_H_
/* define */
/* For Build Option RTOS_LOAD_NUM */
#define RTOS_LOAD_NUM_1 (1U) /* RTOS is RTOS#0 only. */
#define RTOS_LOAD_NUM_3 (3U) /* RTOS are RTOS#0, RTOS#1, and RTOS#2. */
/* For Build Option OPTEE_LOAD_ENABLE */
#define OPTEE_DISABLE (0U) /* Load OP-TEE image disable. */
#define OPTEE_ENABLE (1U) /* Load OP-TEE image enable. */
/* ICUMX Loader */
#define IPL_TOP (0xEB210000U)
#define IPL_SIZE (128U * 1024U)
#define IPL_END ((IPL_TOP +IPL_SIZE) - 1U)
#define MCU_OFFSET (0x0200U) /* 512byte */
/* Certificate logical address */
extern char __ghsbegin_sa9_load[];
#define SA9_DEST_ADDR (uintptr_t)(&__ghsbegin_sa9_load[0])
#define CONTENT_CERT_OFFSET (0x6000U)
/* key cert address */
#define TFMV_KEY_CERT_ADDR (SA9_DEST_ADDR + CONTENT_CERT_INFO_SIZE) /* 0xFDE31000 */
#define NTFMV_KEY_CERT_ADDR (TFMV_KEY_CERT_ADDR + KEY_CERT_SIZE) /* 0xFDE33000 */
/* Size of each content contained in SA9. */
#define KEY_CERT_SIZE (0x00002000U) /* Key cert size(8KiB) */
#define CONTENT_CERT_INFO_SIZE (0x00001000U) /* Content cert header size(4KiB) */
#define CONTENT_CERT_SIZE (0x00000800U) /* content cert src size(2KiB) */
#define MIN_VER_TBL_SIZE (0x00001000U) /* Software minimum version table */
/* Load ID */
#define SECURE_FW_ID (0U) /* 0:Secure Firmware */
#define RTOS_ID (1U) /* 1:RTOS#0 */
#define CA_PROGRAM_ID (2U) /* 2:CX 2nd IPL */
#define ICUMH_PROGRAM_ID (3U) /* 3:ICUMH program */
#define G4MH_PROGRAM_ID (4U) /* 4:G4MH program(1st) 5:G4MH program(2nd) */
#define CA_OPTIONAL_ID (6U) /* 6:CA Program#1, 7:CA Program#2 ... 13:CA Program#8 */
#define TFMV_MIN_VER_TBL_ID (14U) /* 14:TFMV Software minimum version table */
#define NTFMV_MIN_VER_TBL_ID (15U) /* 15:NTFMV Software minimum version table */
#if (RTOS_LOAD_NUM == RTOS_LOAD_NUM_3)
#define RTOS1_ID (16U) /* 16:RTOS#1 */
#define RTOS2_ID (17U) /* 17:RTOS#2 */
#endif /* RTOS_LOAD_NUM == RTOS_LOAD_NUM_3 */
/* Number of Max loading image */
#define NUM_OF_ALWAYS_LOAD_CERT (6U) /* Secure FW + RTOS + Cx IPL + ICUMH + (G4MH * 2) */
#define CA_MAX_IMAGE (8U) /* CA program MAX image num */
#if (RTOS_LOAD_NUM == RTOS_LOAD_NUM_1)
#define MAX_PLACED (16U) /* IPL (or minimum version table) + Secure FW + RTOS *
* + Cx IPL + (CA program * 8) + ICUMH + G4MH */
#elif (RTOS_LOAD_NUM == RTOS_LOAD_NUM_3)
#define MAX_PLACED (18U) /* IPL (or minimum version table) + Secure FW + RTOS#0 *
* + Cx IPL + (CA program * 8) + ICUMH + G4MH + RTOS#1 + RTOS#2 */
#endif /* RTOS_LOAD_NUM == RTOS_LOAD_NUM_1 */
#define TARGET_MEM_DRAM (0U)
#define TARGET_MEM_RTSRAM (1U)
#define TARGET_MEM_RTVRAM (2U)
#define TARGET_MEM_SYSRAM (3U)
#define TARGET_MEM_CODESRAM (4U)
/* get info from cert address offset */
#define CERT_INFO_SIZE_OFFSET (0x00000264U) /* Offset Type1 */
#define CERT_INFO_DST_OFFSET (0x00000154U) /* Offset Type1 */
#define CERT_INFO_SIZE_OFFSET1 (0x00000364U) /* Offset Type2 */
#define CERT_INFO_DST_OFFSET1 (0x000001D4U) /* Offset Type2 */
#define CERT_INFO_SIZE_OFFSET2 (0x00000464U) /* Offset Type2 */
#define CERT_INFO_DST_OFFSET2 (0x00000254U) /* Offset Type2 */
#define FLASH_BOOT (0U)
#define EMMC_BOOT (1U)
#define CERT_INFO_FLG_OFFSET (0x0000000CU)
#define KEY_SIZE_BIT_SHIFT (21U)
/* Parameter info of secure data (for ICUM FW) */
#define SECUREDATA_SIZE (112U * 1024U) /* 112KB */
/* struct */
/* load address range */
typedef struct {
uint32_t topadd;
uint32_t endadd;
} ADDRESS_RANGE;
/* load info */
typedef struct{
const char *name; /* store load image name */
uint32_t image_size; /* store image size */
uint32_t boot_addr; /* store boot address of image */
uint32_t key_cert_addr; /* store key cert address */
uint32_t cnt_cert_addr; /* store content cert address */
uint32_t src_addr; /* store source address */
uint32_t part_num; /* store eMMC partition number */
uint32_t image_id; /* store image ID */
} LOAD_INFO;
static inline uint32_t get_src_addr_offset_in_cert(uint32_t id)
{
return (SA9_DEST_ADDR + ((id * 0x10U) + 0x8U));
}
static inline uint32_t get_logic_cont_cert_addr(uint32_t num)
{
return (SA9_DEST_ADDR + CONTENT_CERT_OFFSET + (num * CONTENT_CERT_SIZE));
}
/* Prototype */
uint32_t load_content_cert(void);
void load_image(LOAD_INFO* li);
void load_init(LOAD_INFO* li);
void check_load_area(const LOAD_INFO* li);
void load_start(const LOAD_INFO* li);
void load_end(void);
void check_overflow(uint32_t addr, uint32_t len, uint32_t *end_addr, const char *func_name);
void load_securedata(uint32_t target_id);
#endif /* LOAD_IMAGE_H_ */

73
Src/0_Tool/Gen4_R-Car_IPL/SDK/v3_46_0/Gen4_ICUMX_Loader/include/image_load_emmc.h Normal file
View File

@@ -0,0 +1,73 @@
/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright 2021-2022 Renesas Electronics Corporation All rights reserved.
*******************************************************************************/
/*******************************************************************************
* DESCRIPTION : Image load function for eMMC header
******************************************************************************/
#ifndef LOAD_IMAGE_EMMC_H_
#define LOAD_IMAGE_EMMC_H_
#include <image_load.h>
#include <ram_def.h>
#include <log.h>
#include <rom_api.h>
/* define */
/* eMMC */
#define EMMC_TOP (0x00000000U)
#define EMMC_BOOT_PART_SIZE (31U * 1024U * 1024U) /* 31MB */
#define EMMC_END ((EMMC_TOP + EMMC_BOOT_PART_SIZE) - 1U)
#define SRC_TOP (EMMC_TOP)
#define SRC_END (EMMC_END)
/* For eMMC */
#define EMMC_SECTOR_SIZE (512U)
#define EMMC_SECTOR_SIZE_SHIFT (9U) /* 512 = 2^9 */
#define EMMC_CONTENT_CERT_ADDR (0x00240000U)
#define EMMC_CONTENT_CERT_SECTOR_NUMBER (EMMC_CONTENT_CERT_ADDR >> EMMC_SECTOR_SIZE_SHIFT)
#define EMMC_PARTITION_1 (1U)
#if (SW_VERSION_CHECK == OPT_VERSION_CHECK_ENABLE)
#define EMMC_VER_TBL_OFFSET (0x0000D000U)
#define EMMC_VER_TBL_CNT_CERT_ADDR (EMMC_CONTENT_CERT_ADDR + EMMC_VER_TBL_OFFSET)
#define EMMC_VER_TBL_CNT_CERT_SEC_NUM (EMMC_VER_TBL_CNT_CERT_ADDR >> EMMC_SECTOR_SIZE_SHIFT)
#endif /* (SW_VERSION_CHECK == OPT_VERSION_CHECK_ENABLE) */
static inline void load_image_info_print_for_emmc(const LOAD_INFO* li)
{
NOTICE("======== %s image load info ========\n"
"load address \t= 0x%08x\n" "image size \t= 0x%08x\n"
"source address \t= (p:%d)0x%08x\n",
li->name, li->boot_addr, li->image_size,
li->part_num, li->src_addr);
}
static inline uint32_t get_part_num_in_cert(uint32_t id)
{
return (SA9_DEST_ADDR + ((id + 1U) * 0x10U));
}
/* Prototype */
uint32_t load_content_cert_for_emmc(void);
#endif /* LOAD_IMAGE_EMMC_H_ */

68
Src/0_Tool/Gen4_R-Car_IPL/SDK/v3_46_0/Gen4_ICUMX_Loader/include/image_load_flash.h Normal file
View File

@@ -0,0 +1,68 @@
/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright 2021-2024 Renesas Electronics Corporation All rights reserved.
*******************************************************************************/
/*******************************************************************************
* DESCRIPTION : Image load function for eMMC header
******************************************************************************/
#ifndef LOAD_IMAGE_FLASH_H_
#define LOAD_IMAGE_FLASH_H_
#include <image_load.h>
#include <ram_def.h>
#include <log.h>
#include <rom_api.h>
/* define */
/* Flash address */
#define FLASH_BASE (0x08000000U)
#define FLASH_SIZE (0x04000000U)
#define FLASH_END ((FLASH_BASE + FLASH_SIZE) - 1U)
#define SRC_TOP (FLASH_BASE)
#define SRC_END (FLASH_END)
/* Flash address of content certificate */
#define CONTENT_CERT_SA (9U) /* Content Cert SA9 */
#define SA_SIZE (0x00040000U)
#define FLASH_CONTENT_CERT_ADDR (uint32_t)(FLASH_BASE + (SA_SIZE * CONTENT_CERT_SA)) /* FLASH Base + SA9 offset */
#if (SW_VERSION_CHECK == OPT_VERSION_CHECK_ENABLE)
#define VER_TBL_CNT_CERT_OFFSET (0x0000D000U)
#define FLASH_VER_TBL_CNT_CERT_ADDR (FLASH_CONTENT_CERT_ADDR + VER_TBL_CNT_CERT_OFFSET) /* SA9 top + offset */
#endif /* (SW_VERSION_CHECK == OPT_VERSION_CHECK_ENABLE) */
#if (RTOS_LOAD_NUM == RTOS_LOAD_NUM_3)
#define RTOS12_CNT_CERT_OFFSET (0x0000E000U)
#define FLASH_RTOS12_CNT_CERT_ADDR (FLASH_CONTENT_CERT_ADDR + RTOS12_CNT_CERT_OFFSET) /* SA9 top + offset */
#endif /* RTOS_LOAD_NUM == RTOS_LOAD_NUM_3 */
static inline void load_image_info_print_for_flash(const LOAD_INFO* li)
{
NOTICE("======== %s image load info ========\n"
"load address \t= 0x%08x\n" "image size \t= 0x%08x\n"
"source address \t= 0x%08x\n",
li->name, li->boot_addr, li->image_size, li->src_addr);
}
/* Prototype */
uint32_t load_content_cert_for_flash(void);
#endif /* LOAD_IMAGE_FLASH_H_ */

41
Src/0_Tool/Gen4_R-Car_IPL/SDK/v3_46_0/Gen4_ICUMX_Loader/include/inline_asm.h Normal file
View File

@@ -0,0 +1,41 @@
/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright 2022 Renesas Electronics Corporation All rights reserved.
*******************************************************************************/
/*******************************************************************************
* DESCRIPTION : inline asm func header
******************************************************************************/
#ifndef INLINE_ASM_H__
#define INLINE_ASM_H__
static inline void syncm(void)
{
__asm__ __volatile__ ("SYNCM");
}
static inline void synci(void)
{
__asm__ __volatile__ ("SYNCI");
}
#endif /* INLINE_ASM_H__ */

58
Src/0_Tool/Gen4_R-Car_IPL/SDK/v3_46_0/Gen4_ICUMX_Loader/include/intc.h Normal file
View File

@@ -0,0 +1,58 @@
/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright 2022 Renesas Electronics Corporation All rights reserved.
*******************************************************************************/
/*******************************************************************************
* DESCRIPTION : window watchdog timer function header
******************************************************************************/
#ifndef INTC_H__
#define INTC_H__
/************************************************************************************************/
/* Definitions */
/************************************************************************************************/
#define INTC1_BASE (0xFFFEEA00UL)
#define INTC2_BASE (0xFFFEF000UL)
typedef void (* INT_HANDLER)(uint32_t int_no, uint32_t arg);
static inline uint32_t get_icumx_ic_addr(uint32_t id)
{
uint32_t ret;
if(id < 32U)
{
ret = INTC1_BASE + (0x02U * (id % 32U));
}
else
{
ret = (INTC2_BASE + 0x40U) + (0x02U * (id % 32U));
}
return ret;
}
void intc_set_interrupt(uint32_t int_no, uint32_t level, INT_HANDLER cb);
void intc_disable_interrupt(uint32_t int_no);
void intc_handler(void);
#endif /* INTC_H__ */

71
Src/0_Tool/Gen4_R-Car_IPL/SDK/v3_46_0/Gen4_ICUMX_Loader/include/intc_id.h Normal file
View File

@@ -0,0 +1,71 @@
/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright 2022 Renesas Electronics Corporation All rights reserved.
*******************************************************************************/
/*******************************************************************************
* DESCRIPTION : Interrupt controler ID header
******************************************************************************/
#ifndef INTC_ID_H_
#define INTC_ID_H_
#define ECC_ERR_LRAM (0U) /* ECC Error Detection for Local RAM */
#define ECC_ERR_CACHE (1U) /* ECC Error Detection for Cache RAM */
#define EDC_ERR_INT_AXI (2U) /* EDC Error interrupt of AXI */
#define ECC_ERR_INT_AXIAB (3U) /* ECC Error interrupt of AXIAB */
#define ECC_ERR_INT_PKCC (4U) /* ECC Error interrupt of PKCC */
#define CORTEX_INT_REQ_SINGLE_CORE (5U) /* Cortex-R/A interrupt request (single main core) */
#define CORTEX_INT_REQ_SEL_SINGLE_CORE (6U) /* Cortex-R/A interrupt request (selected single main core) */
#define COMPLETION_AES (7U) /* Completion of AES encryption or decryption */
/* ID 8 Reserved */
#define COMPLETION_RAND_NUMBER (9U) /* Random number generation complete */
#define OSTIMER0_OVERFLOW (10U) /* OS Timer 0 overflow */
#define OSTIMER1_OVERFLOW (11U) /* OS Timer 1 overflow */
#define WDT0_INT (12U) /* Watchdog Timer 0 interrupt (at 75%) */
#define COMPLETION_PKCC (13U) /* Completion of PKCC operation */
#define COMPLETION_DMAC_CH5CH6 (14U) /* Interrupt request by transfer completion for channel-5/6 */
#define INT_REQ_BRESP_RRESP_ERR_AXI (15U) /* Interrupt request by BRESP/RRESP-error for AXI */
/* ID 16 Reserved */
#define REQ_SHAA0 (17U) /* Input data request for SHAA0 */
#define COMPLETION_SHAA0 (18U) /* Completion or suspension of SHAA0 data output */
#define REQ_CHALLENGE_DATA_FOR_ARM_DEBUG (19U) /* Challenge data request for ARM Debugger */
#define REQ_RES_COMP_FOR_ARM_DEBUG (20U) /* Response data compare request for ARM Debugger */
#define REQ_CHALLENGE_DATA_FOR_RH850_DEBUG (21U) /* Challenge data request for RH850 Debugger */
#define REQ_RES_COMP_FOR_RH850_DEBUG (22U) /* Response data compare request for RH850 Debugger */
#define REQ_CHALLENGE_DATA_FOR_RH850_DEBUG_R (23U) /* Challenge data request for RH850 Debugger r */
/* Reserved */
#define ACC_ERR_MASKROM_RTSRAM (25U) /* Data access error detection of Mask ROM or RTSRAM area */
#define ACC_ERR_EXCEPT_MASKROM_RTSRAM (26U) /* Data access error detection except Mask ROM and RT-SRAM area */
/* ID 27 Reserved */
/* ID 28 Reserved */
#define RTSRAM_SAFETY_ERR (29U) /* RT-SRAM Error Safety Error Detection */
#define RTSRAM_SECURE_ERR (30U) /* RT-SRAM Error Secure Error Detection */
#define RTSRAM_EDC_ERR (31U) /* RT-SRAM Error EDC Error Detection */
#define RTSRAM_DUPLEX_ERR (32U) /* RT-SRAM Error Duplex circuit Error Detection */
#define RTSRAM_SYSRAM_2BIT_ERR (33U) /* RT-SRAM Error SYSRAM 2bit Error Detection */
#define RTSRAM_SYSRAM_1BIT_ERR (34U) /* RT-SRAM Error SYSRAM 1bit Error Detection */
#define SECROM_SYSRAM_2BIT_ERR (35U) /* Sec ROM Error SYSRAM 2bit Error Detection */
#define SECROM_SYSRAM_1BIT_ERR (36U) /* Sec ROM Error SYSRAM 1bit Error Detection */
#define COMPLETION_SECURE_BOOT_ENGINE_CALC (37U) /* Completion of secure boot engine calculation */
/* ID 38 -- 63 Reserved */
#endif /* INTC_ID_H_ */

34
Src/0_Tool/Gen4_R-Car_IPL/SDK/v3_46_0/Gen4_ICUMX_Loader/include/ip_control.h Normal file
View File

@@ -0,0 +1,34 @@
/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright 2021-2022 Renesas Electronics Corporation All rights reserved.
*******************************************************************************/
/*******************************************************************************
* DESCRIPTION : IP's control header
******************************************************************************/
#ifndef IP_CONTROL_H_
#define IP_CONTROL_H_
/* Prototype */
void ip_init(void);
void ip_release(void);
#endif /* IP_CONTROL_H_ */

36
Src/0_Tool/Gen4_R-Car_IPL/SDK/v3_46_0/Gen4_ICUMX_Loader/include/loader_main.h Normal file
View File

@@ -0,0 +1,36 @@
/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright 2021-2022 Renesas Electronics Corporation All rights reserved.
*******************************************************************************/
/*******************************************************************************
* DESCRIPTION : Loader main header
******************************************************************************/
#ifndef LOADER_MAIN_H_
#define LOADER_MAIN_H_
/* prototype */
uint32_t loader_main(void);
#if (RCAR_LSI == RCAR_V4H)
void clear_ecm_st_axi(void);
#endif
#endif /* LOAD_MAIN_H_ */

44
Src/0_Tool/Gen4_R-Car_IPL/SDK/v3_46_0/Gen4_ICUMX_Loader/include/loader_main_common.h Normal file
View File

@@ -0,0 +1,44 @@
/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright 2022-2025 Renesas Electronics Corporation All rights reserved.
*******************************************************************************/
/*******************************************************************************
* DESCRIPTION : Loader main common header
******************************************************************************/
#ifndef LOADER_MAIN_COMMON_H_
#define LOADER_MAIN_COMMON_H_
/* define */
#define IPL_VERSION "1.60.2"
#define ADD_MAGIC_NUMBER (1U)
/* Global */
extern const char build_message[];
/* prototype */
void print_boot_msg(void);
void wa_setting_apmu(void);
#endif /* LOADER_MAIN_COMMON_H_ */

86
Src/0_Tool/Gen4_R-Car_IPL/SDK/v3_46_0/Gen4_ICUMX_Loader/include/log.h Normal file
View File

@@ -0,0 +1,86 @@
/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright 2021-2023 Renesas Electronics Corporation All rights reserved.
*******************************************************************************/
/*******************************************************************************
* DESCRIPTION : Log driver header
******************************************************************************/
#ifndef LOG_H__
#define LOG_H__
#include <stdint.h>
#include <stdbool.h>
#define LOG_NONE (0)
#define LOG_ERROR (1)
#define LOG_NOTICE (2)
#define LOG_WARNING (3)
#define LOG_INFO (4)
#define LOG_VERBOSE (5)
#if LOG_LEVEL >= LOG_ERROR
#include <stdio.h>
#endif
#if LOG_LEVEL >= LOG_VERBOSE
# define VERBOSE(...) local_printf("V:" __VA_ARGS__)
#else
# define VERBOSE(...)
#endif
#if LOG_LEVEL >= LOG_INFO
# define INFO(...) local_printf("I:" __VA_ARGS__)
#else
# define INFO(...)
#endif
#if LOG_LEVEL >= LOG_WARNING
# define WARN(...) local_printf("W:" __VA_ARGS__)
#else
# define WARN(...)
#endif
#if LOG_LEVEL >= LOG_ERROR
# define ERROR(...) local_printf("E:" __VA_ARGS__)
#else
# define ERROR(...)
#endif
#if LOG_LEVEL >= LOG_NOTICE
# define NOTICE(...) local_printf("N:" __VA_ARGS__)
#else
# define NOTICE(...)
#endif
#define panic \
do { \
panic_printf(__func__); \
while(true){} \
} while (false)
#if LOG_LEVEL >= LOG_ERROR
void local_printf(const char *fmt, ...);
#endif
void panic_printf(const char *str);
#endif /* LOG_H__ */

125
Src/0_Tool/Gen4_R-Car_IPL/SDK/v3_46_0/Gen4_ICUMX_Loader/include/mcu_register.h Normal file
View File

@@ -0,0 +1,125 @@
/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright 2021-2023 Renesas Electronics Corporation All rights reserved.
*******************************************************************************/
/*******************************************************************************
* DESCRIPTION : MCU register header
******************************************************************************/
#ifndef MCU_REGISTER_H_
#define MCU_REGISTER_H_
#include <remap_register.h>
/* The Base is remapped in the IPL, and the address is calculated and accessed
* by adding the offset to the remapped address. */
#define MCU_BASE (BASE_MCU_ADDR)
/* SCDS0 (0xD8F00800) */
#define MCU_ICUM_OPBT0 (MCU_BASE + 0x09C0U)
#define MCU_ICUM_OPBT1 (MCU_BASE + 0x09C4U)
#define MCU_ICUM_OPBT2 (MCU_BASE + 0x09C8U)
#define MCU_ICUM_OPBT4 (MCU_BASE + 0x09D0U)
#define MCU_ICUM_OPBT5 (MCU_BASE + 0x09D4U)
#define MCU_ICUM_OPBT6 (MCU_BASE + 0x09D8U)
#define MCU_ICUM_OPBT7 (MCU_BASE + 0x09DCU)
#define MCU_GREG120 (MCU_BASE + 0x09E0U)
/* SCDS2 (0xD8F00C00) */
#define MCU_RESET_VECTOR_PE0 (MCU_BASE + 0x0C00U)
#define MCU_RESET_VECTOR_PE1 (MCU_BASE + 0x0C04U)
#define MCU_OPBT0 (MCU_BASE + 0x0C20U)
#define MCU_OPBT1 (MCU_BASE + 0x0C24U)
#define MCU_OPBT2 (MCU_BASE + 0x0C28U)
#define MCU_OPBT3 (MCU_BASE + 0x0C2CU)
#define MCU_OPBT4 (MCU_BASE + 0x0C30U)
#define MCU_OPBT6 (MCU_BASE + 0x0C38U)
#define MCU_OPBT7 (MCU_BASE + 0x0C3CU)
#define MCU_OPBT8 (MCU_BASE + 0x0C40U)
#define MCU_OPBT9 (MCU_BASE + 0x0C44U)
#define MCU_OPBT96 (MCU_BASE + 0x0CA0U)
/* MCCR_SELB0 (0xD8F01000) */
#define MCU_OPBT_STAT (MCU_BASE + 0x1000U)
#define MCU_OPBT_CTRL (MCU_BASE + 0x1004U)
#define MCU_G4MH_BOOT_CTLR (MCU_BASE + 0x1008U)
#define MCU_ICUMH_BOOT_CTLR (MCU_BASE + 0x100CU)
#define MCU_BOOT_STAT (MCU_BASE + 0x1024U)
/* MCCR_SELB1 (0xD8F02000) */
/* HBG (0xD8F12000) */
#define MCU_HBG_CS0_HBGPROT0 (MCU_BASE + 0x00012000U)
#define MCU_HBG_CS1_HBGPROT0 (MCU_BASE + 0x00012100U)
#define MCU_HBG_CS2_HBGPROT0 (MCU_BASE + 0x00012200U)
#define MCU_HBG_CS3_HBGPROT0 (MCU_BASE + 0x00012300U)
#define MCU_HBG_CS4_HBGPROT0 (MCU_BASE + 0x00012400U)
#define MCU_HBG_CS5_HBGPROT0 (MCU_BASE + 0x00012500U)
#define MCU_HBG_DS_HBGPROT0 (MCU_BASE + 0x00012600U)
#define MCU_HBG_PFS_HBGPROT0 (MCU_BASE + 0x00012700U)
#define MCU_HBG_SOCM_HBGPROT0 (MCU_BASE + 0x00012800U)
#define MCU_HBG_SOCS_HBGPROT0 (MCU_BASE + 0x00012900U)
/* HBGSLVER (0xD8F19000) */
#define MCU_HBGSLVER_CS0_HBGKCPROT (MCU_BASE + 0x00019018U)
#define MCU_HBGSLVER_CS1_HBGKCPROT (MCU_BASE + 0x00019118U)
#define MCU_HBGSLVER_CS2_HBGKCPROT (MCU_BASE + 0x00019218U)
#define MCU_HBGSLVER_CS3_HBGKCPROT (MCU_BASE + 0x00019318U)
#define MCU_HBGSLVER_CS4_HBGKCPROT (MCU_BASE + 0x00019418U)
#define MCU_HBGSLVER_CS5_HBGKCPROT (MCU_BASE + 0x00019518U)
#define MCU_HBGSLVER_DS_HBGKCPROT (MCU_BASE + 0x00019618U)
#define MCU_HBGSLVER_PFS_HBGKCPROT (MCU_BASE + 0x00019718U)
#define MCU_HBGSLVER_SOCM_HBGKCPROT (MCU_BASE + 0x00019818U)
#define MCU_HBGSLVER_SOCS_HBGKCPROT (MCU_BASE + 0x00019918U)
/* PBG (0xD8F01800) */
#define MCUAXI_PBG_PBGPROT0_0 (MCU_BASE + 0x1800U)
#define MCUAXI_PBG_PBGPROT0_1 (MCU_BASE + 0x1808U)
#define MCUAXI_PBG_PBGPROT0_2 (MCU_BASE + 0x1810U)
#define MCUAXI_PBG_PBGPROT0_3 (MCU_BASE + 0x1818U)
#define MCUAXI_PBG_PBGPROT0_4 (MCU_BASE + 0x1820U)
#define MCUAXI_PBG_PBGPROT0_5 (MCU_BASE + 0x1828U)
#define MCUAXI_PBG_PBGPROT0_6 (MCU_BASE + 0x1830U)
#define MCUAXI_PBG_ERRSLV_PBGKCPROT (MCU_BASE + 0x00018118U)
/* CSRM (0xD8F10000) */
#define MCU_CSRM0ECCCTL (MCU_BASE + 0x00010000U)
#define MCU_CSRM1ECCCTL (MCU_BASE + 0x00010100U)
#define MCU_CSRM2ECCCTL (MCU_BASE + 0x00010200U)
#define MCU_CSRM3ECCCTL (MCU_BASE + 0x00010300U)
#define MCU_CSRM4ECCCTL (MCU_BASE + 0x00010400U)
#define MCU_CSRM5ECCCTL (MCU_BASE + 0x00010500U)
#define MCU_CSRM0APCTL (MCU_BASE + 0x00010050U)
#define MCU_CSRM1APCTL (MCU_BASE + 0x00010150U)
#define MCU_CSRM2APCTL (MCU_BASE + 0x00010250U)
#define MCU_CSRM3APCTL (MCU_BASE + 0x00010350U)
#define MCU_CSRM4APCTL (MCU_BASE + 0x00010450U)
#define MCU_CSRM5APCTL (MCU_BASE + 0x00010550U)
#define MCU_CSRM0CSIFCODE (MCU_BASE + 0x00010080U)
#define MCU_CSRM1CSIFCODE (MCU_BASE + 0x00010180U)
#define MCU_CSRM2CSIFCODE (MCU_BASE + 0x00010280U)
#define MCU_CSRM3CSIFCODE (MCU_BASE + 0x00010380U)
#define MCU_CSRM4CSIFCODE (MCU_BASE + 0x00010480U)
#define MCU_CSRM5CSIFCODE (MCU_BASE + 0x00010580U)
#endif /* MCU_REGISTER_H_ */

84
Src/0_Tool/Gen4_R-Car_IPL/SDK/v3_46_0/Gen4_ICUMX_Loader/include/mem_io.h Normal file
View File

@@ -0,0 +1,84 @@
/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright 2021-2022 Renesas Electronics Corporation All rights reserved.
*******************************************************************************/
/*******************************************************************************
* DESCRIPTION : Memory access driver header
******************************************************************************/
#ifndef MEM_IO_H_
#define MEM_IO_H_
#include <stdint.h>
static inline void mem_write8(uintptr_t addr, uint8_t data)
{
*(volatile uint8_t*)addr = data;
}
static inline uint8_t mem_read8(uintptr_t addr)
{
return (*(volatile uint8_t*)addr);
}
static inline void mem_write16(uintptr_t addr, uint16_t data)
{
*(volatile uint16_t*)addr = data;
}
static inline uint16_t mem_read16(uintptr_t addr)
{
return (*(volatile uint16_t*)addr);
}
static inline void mem_write32(uintptr_t addr, uint32_t data)
{
*(volatile uint32_t*)addr = data;
}
static inline uint32_t mem_read32(uintptr_t addr)
{
return (*(volatile uint32_t*)addr);
}
static inline void mem_write64(uintptr_t addr, uint64_t data)
{
*(volatile uint64_t*)addr = data;
}
static inline uint64_t mem_read64(uintptr_t addr)
{
return (*(volatile uint64_t*)addr);
}
static inline void mem_bitclrset32(uintptr_t addr, uint32_t clr, uint32_t set)
{
mem_write32(addr, (mem_read32(addr) & ~clr) | set);
}
#if defined(__RH850G3K__)
#define mmio_write_32(a,b) mem_write32(a,b)
#define mmio_read_32(a) mem_read32(a)
#define mmio_clrsetbits_32(a,b,c) mem_bitclrset32(a,b,c)
#endif
#endif /* MEM_IO_H_ */

39
Src/0_Tool/Gen4_R-Car_IPL/SDK/v3_46_0/Gen4_ICUMX_Loader/include/mfis.h Normal file
View File

@@ -0,0 +1,39 @@
/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright 2022 Renesas Electronics Corporation All rights reserved.
*******************************************************************************/
/*******************************************************************************
* DESCRIPTION : MFIS driver header
******************************************************************************/
#ifndef MFIS_H__
#define MFIS_H__
/************************************************************************************************/
/* Definitions */
/************************************************************************************************/
void mfis_init(void);
void mfis_lock(void);
void mfis_unlock(void);
#endif /* MFIS_H__ */

45
Src/0_Tool/Gen4_R-Car_IPL/SDK/v3_46_0/Gen4_ICUMX_Loader/include/mfis_register.h Normal file
View File

@@ -0,0 +1,45 @@
/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright 2022 Renesas Electronics Corporation All rights reserved.
*******************************************************************************/
/*******************************************************************************
* DESCRIPTION : MFIS register header
******************************************************************************/
#ifndef MFIS_REGISTER_H__
#define MFIS_REGISTER_H__
#include <remap_register.h>
/* The Base is remapped in the IPL, and the address is calculated and accessed
* by adding the offset to the remapped address. */
#define MFIS_BASE (BASE_MFIS_ADDR)
#define MFISLCKR_ADDRESS (0x0800U) /* MFISLCKR[j] Address 0x724 +(4U*(63U-8U)) */
/* Register Definition */
#define MFIS_LCKR (MFIS_BASE + MFISLCKR_ADDRESS) /* MFIS Lock Register */
#define MFIS_WPCNTR (MFIS_BASE + 0x0900U) /* Write Protection Control Register */
#define MFIS_WACNTR (MFIS_BASE + 0x0904U) /* Write Access Control Register */
#endif /* MFIS_REGISTER_H__ */

39
Src/0_Tool/Gen4_R-Car_IPL/SDK/v3_46_0/Gen4_ICUMX_Loader/include/micro_wait.h Normal file
View File

@@ -0,0 +1,39 @@
/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright 2021-2022 Renesas Electronics Corporation All rights reserved.
*******************************************************************************/
/*******************************************************************************
* DESCRIPTION : Time wait driver header
******************************************************************************/
#ifndef MICRO_WAIT_H_
#define MICRO_WAIT_H_
#include <stdint.h>
/* Define */
/* Prototype */
void micro_wait(uint32_t count_us);
#endif /* MICRO_WAIT_H_ */

41
Src/0_Tool/Gen4_R-Car_IPL/SDK/v3_46_0/Gen4_ICUMX_Loader/include/pfc.h Normal file
View File

@@ -0,0 +1,41 @@
/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright 2021-2022 Renesas Electronics Corporation All rights reserved.
*******************************************************************************/
/*******************************************************************************
* DESCRIPTION : PFC driver header
******************************************************************************/
#ifndef PFC_H__
#define PFC_H__
#include <stdint.h>
#include <mem_io.h>
#include <pfc_register.h>
static inline void pfc_reg_write(uint32_t addr, uint32_t data)
{
mem_write32(get_pmmr_addr(addr), ~data);
mem_write32(addr, data);
}
#endif /* PFC_H__ */

135
Src/0_Tool/Gen4_R-Car_IPL/SDK/v3_46_0/Gen4_ICUMX_Loader/include/pfc_register.h Normal file
View File

@@ -0,0 +1,135 @@
/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright 2021-2025 Renesas Electronics Corporation All rights reserved.
*******************************************************************************/
/*******************************************************************************
* DESCRIPTION : PFC register header
******************************************************************************/
#ifndef PFC_REGISTER_H__
#define PFC_REGISTER_H__
#include <stdint.h>
#include <remap_register.h>
/* PFC / GPIO base address */
/* 0xE6050000 */
#define PFC_BASE (BASE_PFC_ADDR)
#define PFC_RW_OFFSET (0x0000U)
#define PFC_SET_OFFSET (0x0200U)
#define PFC_CLR_OFFSET (0x0400U)
#if (RCAR_LSI == RCAR_S4)
#define PFC_MCU_BASE (BASE_PFCMCU_ADDR)
#define PFC_PORT_GRP0 (0x00000000U) /* Port Group0/4 */
#define PFC_PORT_GRP1 (0x00000800U) /* Port Group1/5 */
#define PFC_PORT_GRP2 (0x00001000U) /* Port Group2/6 */
#define PFC_PORT_GRP3 (0x00001800U) /* Port Group3/7 */
#define PFC_SYS_GRP (0x00028000U) /* System Group0/1 */
#elif ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M))
#define PFC_PORT_GRP0 (0x00000000U) /* Port Group0 */
#define PFC_PORT_GRP1 (0x00000800U) /* Port Group1 */
#define PFC_PORT_GRP2 (0x00008000U) /* Port Group2 */
#define PFC_PORT_GRP3 (0x00008800U) /* Port Group3 */
#define PFC_PORT_GRP4 (0x00010000U) /* Port Group4 */
#define PFC_PORT_GRP5 (0x00010800U) /* Port Group5 */
#define PFC_PORT_GRP6 (0x00011000U) /* Port Group6 */
#define PFC_PORT_GRP7 (0x00011800U) /* Port Group7 */
#if (RCAR_LSI == RCAR_V4H)
#define PFC_PORT_GRP8 (0x00018000U) /* Port Group8 */
#endif
#define PFC_SYS_GRP (0x00028000U) /* System Group0 */
#endif
/* PFC / GPIO registers */
/* Read/Write registers */
#define PFC_PORT_GRP_MASK (0xFFFFF800U)
/* Port Group0 */
#define PFC_DM1PR0_RW (PFC_BASE + PFC_PORT_GRP0 + PFC_RW_OFFSET + 0x0024U)
#define PFC_DM2PR0_RW (PFC_BASE + PFC_PORT_GRP0 + PFC_RW_OFFSET + 0x0028U)
#define PFC_DM3PR0_RW (PFC_BASE + PFC_PORT_GRP0 + PFC_RW_OFFSET + 0x002CU)
#define PFC_GPSR0_RW (PFC_BASE + PFC_PORT_GRP0 + PFC_RW_OFFSET + 0x0040U)
#define PFC_IP0SR0_RW (PFC_BASE + PFC_PORT_GRP0 + PFC_RW_OFFSET + 0x0060U)
#define PFC_POC0_RW (PFC_BASE + PFC_PORT_GRP0 + PFC_RW_OFFSET + 0x00A0U)
/* Port Group1 */
#define PFC_DM1PR1_RW (PFC_BASE + PFC_PORT_GRP1 + PFC_RW_OFFSET + 0x0024U)
#define PFC_DM2PR1_RW (PFC_BASE + PFC_PORT_GRP1 + PFC_RW_OFFSET + 0x0028U)
#define PFC_DM3PR1_RW (PFC_BASE + PFC_PORT_GRP1 + PFC_RW_OFFSET + 0x002CU)
#define PFC_GPSR1_RW (PFC_BASE + PFC_PORT_GRP1 + PFC_RW_OFFSET + 0x0040U)
#define PFC_IP1SR1_RW (PFC_BASE + PFC_PORT_GRP1 + PFC_RW_OFFSET + 0x0064U)
#define PFC_IP2SR1_RW (PFC_BASE + PFC_PORT_GRP1 + PFC_RW_OFFSET + 0x0068U)
#define PFC_POC1_RW (PFC_BASE + PFC_PORT_GRP1 + PFC_RW_OFFSET + 0x00A0U)
/* Port Group2 */
#define PFC_DM1PR2_RW (PFC_BASE + PFC_PORT_GRP2 + PFC_RW_OFFSET + 0x0024U)
#define PFC_DM2PR2_RW (PFC_BASE + PFC_PORT_GRP2 + PFC_RW_OFFSET + 0x0028U)
#define PFC_DM3PR2_RW (PFC_BASE + PFC_PORT_GRP2 + PFC_RW_OFFSET + 0x002CU)
/* Port Group3 */
#define PFC_DM1PR3_RW (PFC_BASE + PFC_PORT_GRP3 + PFC_RW_OFFSET + 0x0024U)
#define PFC_DM2PR3_RW (PFC_BASE + PFC_PORT_GRP3 + PFC_RW_OFFSET + 0x0028U)
#define PFC_DM3PR3_RW (PFC_BASE + PFC_PORT_GRP3 + PFC_RW_OFFSET + 0x002CU)
#define PFC_POC3_RW (PFC_BASE + PFC_PORT_GRP3 + PFC_RW_OFFSET + 0x00A0U)
#define PFC_PUEN3_RW (PFC_BASE + PFC_PORT_GRP3 + PFC_RW_OFFSET + 0x00C0U)
/* Port Group4 */
#define PFC_DM1PR4_RW (PFC_BASE + PFC_PORT_GRP4 + PFC_RW_OFFSET + 0x0024U)
#define PFC_DM2PR4_RW (PFC_BASE + PFC_PORT_GRP4 + PFC_RW_OFFSET + 0x0028U)
#define PFC_DM3PR4_RW (PFC_BASE + PFC_PORT_GRP4 + PFC_RW_OFFSET + 0x002CU)
/* Physical address:0xE6060040, Logical address:0x0xFDA60040 */
#define PFC_GPSR4_RW (PFC_BASE + PFC_PORT_GRP4 + PFC_RW_OFFSET + 0x0040U)
/* Physical address:0xE6060060, Logical address:0x0xFDA60060 */
#define PFC_IP0SR4_RW (PFC_BASE + PFC_PORT_GRP4 + PFC_RW_OFFSET + 0x0060U)
/* Physical address:0xE60600C0, Logical address:0x0xFDA600C0 */
#define PFC_PUEN4_RW (PFC_BASE + PFC_PORT_GRP4 + PFC_RW_OFFSET + 0x00C0U)
/* Physical address:0xE6060100, Logical address:0x0xFDA60100 */
#define PFC_MODSEL4_RW (PFC_BASE + PFC_PORT_GRP4 + PFC_RW_OFFSET + 0x0100U)
/* Port Group5 */
#define PFC_DM1PR5_RW (PFC_BASE + PFC_PORT_GRP5 + PFC_RW_OFFSET + 0x0024U)
#define PFC_DM2PR5_RW (PFC_BASE + PFC_PORT_GRP5 + PFC_RW_OFFSET + 0x0028U)
#define PFC_DM3PR5_RW (PFC_BASE + PFC_PORT_GRP5 + PFC_RW_OFFSET + 0x002CU)
/* Port Group6 */
#define PFC_DM1PR6_RW (PFC_BASE + PFC_PORT_GRP6 + PFC_RW_OFFSET + 0x0024U)
#define PFC_DM2PR6_RW (PFC_BASE + PFC_PORT_GRP6 + PFC_RW_OFFSET + 0x0028U)
#define PFC_DM3PR6_RW (PFC_BASE + PFC_PORT_GRP6 + PFC_RW_OFFSET + 0x002CU)
/* Port Group7 */
#define PFC_DM1PR7_RW (PFC_BASE + PFC_PORT_GRP7 + PFC_RW_OFFSET + 0x0024U)
#define PFC_DM2PR7_RW (PFC_BASE + PFC_PORT_GRP7 + PFC_RW_OFFSET + 0x0028U)
#define PFC_DM3PR7_RW (PFC_BASE + PFC_PORT_GRP7 + PFC_RW_OFFSET + 0x002CU)
#if (RCAR_LSI == RCAR_V4H)
/* Port Group8 */
#define PFC_DM1PR8_RW (PFC_BASE + PFC_PORT_GRP8 + PFC_RW_OFFSET + 0x0024U)
#define PFC_DM2PR8_RW (PFC_BASE + PFC_PORT_GRP8 + PFC_RW_OFFSET + 0x0028U)
#define PFC_DM3PR8_RW (PFC_BASE + PFC_PORT_GRP8 + PFC_RW_OFFSET + 0x002CU)
#endif
/* System Group */
#define PFC_DM1PRSYS_RW (PFC_BASE + PFC_SYS_GRP + PFC_RW_OFFSET + 0x0024U)
#define PFC_DM2PRSYS_RW (PFC_BASE + PFC_SYS_GRP + PFC_RW_OFFSET + 0x0028U)
#define PFC_DM3PRSYS_RW (PFC_BASE + PFC_SYS_GRP + PFC_RW_OFFSET + 0x002CU)
static inline uint32_t get_pmmr_addr(uint32_t addr)
{
return (addr & PFC_PORT_GRP_MASK);
}
#endif /* PFC_REGISTER_H__ */

33
Src/0_Tool/Gen4_R-Car_IPL/SDK/v3_46_0/Gen4_ICUMX_Loader/include/qos.h Normal file
View File

@@ -0,0 +1,33 @@
/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright 2021-2022 Renesas Electronics Corporation All rights reserved.
*******************************************************************************/
/*******************************************************************************
* DESCRIPTION : QoS driver header
******************************************************************************/
#ifndef QOS_INIT_H_
#define QOS_INIT_H_
extern void qos_init(void);
#endif /* QOS_INIT_H_ */

80
Src/0_Tool/Gen4_R-Car_IPL/SDK/v3_46_0/Gen4_ICUMX_Loader/include/ram_def.h Normal file
View File

@@ -0,0 +1,80 @@
/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright 2021-2022 Renesas Electronics Corporation All rights reserved.
*******************************************************************************/
/*******************************************************************************
* DESCRIPTION : R-Car RAM header
******************************************************************************/
#ifndef RAM_DEF_H_
#define RAM_DEF_H_
#include "remap_register.h"
/* DRAM address */
#define DRAM_BASE (0x40000000U)
#define DRAM_SIZE (0x80000000U)
#define DRAM_END ((DRAM_BASE + DRAM_SIZE) - 1U)
#define SDRAM_40BIT_ADDR_TOP (0x0400000000ULL)
/* RT-SRAM */
#define RTSRAM_BASE (0xEB200000U)
#define RTSRAM_SIZE ((1024U - 16U) * 1024U) /* 1MB - 16KB(stack size) */
#define RTSRAM_END ((RTSRAM_BASE + RTSRAM_SIZE) - 1U)
/* RT-VRAM */
#define RTVRAM_BASE (0xE2000000U)
#define RTVRAM_SIZE (1024U * 1024U) /* 1MB */
#define RTVRAM_END ((RTVRAM_BASE + RTVRAM_SIZE) - 1U)
/* RT-VRAM extend mode */
#define RTVRAM_VBUF_TOP (RTVRAM_BASE + RTVRAM_SIZE) /* 0xE2100000 */
#define RTVRAM_VBUF_4M (4U) /* 4MB */
#define RTVRAM_VBUF_8M (8U) /* 8MB */
#define RTVRAM_VBUF_12M (12U) /* 12MB */
#define RTVRAM_VBUF_16M (16U) /* 16MB */
#define RTVRAM_VBUF_20M (20U) /* 20MB */
#define RTVRAM_VBUF_24M (24U) /* 24MB */
#define RTVRAM_VBUF_28M (28U) /* 28MB */
#define RTVRAM_VBUF_SIZE ((RTVRAM_VBUF_28M - 1U) * 1024U * 1024U) /* 3MB to 27MB (The first 1MB is actual RAM.) */
#define RTVRAM_VBUF_AREA_SIZE (4U * 1024U * 1024U) /* 4MB */
#define RTVRAM_VBUF_END ((RTVRAM_VBUF_TOP + RTVRAM_VBUF_SIZE) - 1U)
/* Code SRAM */
#if (BOOT_MCU != 0U)
#define CODESRAM_BASE (0x10000000U)
#define CODESRAM_SIZE (6U * 1024U * 1024U) /* 6MB */
#define CODESRAM_END ((CODESRAM_BASE + CODESRAM_SIZE) - 1U)
#endif /* (BOOT_MCU != 0U) */
/* System RAM */
#define SYSRAM_BASE (0xE6300000U)
#define SYSRAM_SIZE (384U * 1024U) /* 384KB */
#define SYSRAM_END ((SYSRAM_BASE + SYSRAM_SIZE) - 1U)
/* Local RAM */
#define LOCAL_RAM_BASE (0xFEDE0000U)
#define LOCAL_RAM_SIZE (0x00020000U) /* 128KB */
#define LOCAL_RAM_END ((LOCAL_RAM_BASE + LOCAL_RAM_SIZE) - 1U)
/* Data-SRAM */
#define DATA_SRAM_BASE (0xDF200000U)
#endif /* RAM_DEF_H_ */

162
Src/0_Tool/Gen4_R-Car_IPL/SDK/v3_46_0/Gen4_ICUMX_Loader/include/ram_protection.h Normal file
View File

@@ -0,0 +1,162 @@
/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright 2023-2025 Renesas Electronics Corporation All rights reserved.
*******************************************************************************/
/*******************************************************************************
* DESCRIPTION : RAM protection driver header
******************************************************************************/
#ifndef RAM_PROTECTION_H_
#define RAM_PROTECTION_H_
#include <stdint.h>
#include <image_load.h>
#define RTSRAM_AREA1_TOP (0xE0040000U)
#define RTSRAM_ADDR_END (0xE0100000U)
#if (RCAR_LSI == RCAR_S4)
#define RTSRAM_ADDR_OFFSET_MASK (0x000FF000U)
#else
#define RTSRAM_ADDR_OFFSET_MASK (0xFFFFF000U)
#endif
#define RTVRAM_AREA1_TOP (0xE2010000U)
#define RTVRAM_AREA2_TOP (0xE2100000U)
#define RTVRAM_ADDR_END (0xE3C00000U)
#define RTVRAM_ADDR_MASK (0xFFFFF000U)
#if (RCAR_LSI == RCAR_S4)
#define SYSTEM_RAM_ADDR_END (0xE6360000U)
#else /* (RCAR_LSI == RCAR_S4) */
/* For V4H/V4M */
#define SYSTEM_RAM_AREA1_TOP (0xE635E000U)
#define SYSTEM_RAM_AREA2_TOP (0xE6360000U)
#define SYSTEM_RAM_ADDR_END (0xE6400000U)
#endif /* (RCAR_LSI == RCAR_S4) */
#define SYSTEM_RAM_ADDR_MASK (0xFFFFF000U)
#if ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M))
#define DRAM_ADDR_AREA1 (0x0401C00000ULL)
#define DRAM_ADDR_AREA2 (0x0401D00000ULL)
#if (OPTEE_LOAD_ENABLE == OPTEE_DISABLE)
#define DRAM_ADDR_AREA3 (0x0406400000ULL)
#define DRAM_ADDR_AREA4 (0x0406440000ULL)
#define DRAM_ADDR_AREA5 (0x0407FC0000ULL)
#define DRAM_ADDR_AREA6 (0x0408000000ULL)
#define DRAM_ADDR_AREA7 (0x041DC00000ULL)
#define DRAM_ADDR_AREA8 (0x0420000000ULL)
#define DRAM_ADDR_AREA9 (0x0440000000ULL)
#define DRAM_ADDR_AREA10 (0x0460000000ULL)
#define DRAM_ADDR_AREA11 (0x0480000000ULL)
#define DRAM_ADDR_AREA12 (0x0500000000ULL)
#define DRAM_ADDR_AREA13 (0x0600000000ULL)
#else
#define DRAM_ADDR_AREA3 (0x0404100000ULL)
#define DRAM_ADDR_AREA4 (0x0406400000ULL)
#define DRAM_ADDR_AREA5 (0x0406440000ULL)
#define DRAM_ADDR_AREA6 (0x0407E00000ULL)
#define DRAM_ADDR_AREA7 (0x0407F00000ULL)
#define DRAM_ADDR_AREA8 (0x0407FC0000ULL)
#define DRAM_ADDR_AREA9 (0x0408000000ULL)
#define DRAM_ADDR_AREA10 (0x041DC00000ULL)
#define DRAM_ADDR_AREA11 (0x0420000000ULL)
#define DRAM_ADDR_AREA12 (0x0440000000ULL)
#define DRAM_ADDR_AREA13 (0x0460000000ULL)
#define DRAM_ADDR_AREA14 (0x0480000000ULL)
#define DRAM_ADDR_AREA15 (0x0500000000ULL)
#define DRAM_ADDR_AREA16 (0x0600000000ULL)
#endif /* OPTEE_LOAD_ENABLE == OPTEE_DISABLE */
#else
#define DRAM_ADDR_AREA1 (0x0401C00000ULL)
#define DRAM_ADDR_AREA2 (0x0406400000ULL)
#define DRAM_ADDR_AREA3 (0x0406440000ULL)
#endif /* ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M)) */
#define DRAM_ADDR_END (0x0700000000ULL)
#define SDRAM_ADDR_MASK (0x3FFFFF0000ULL)
#define NOT_USED_VALUE (0x00000000U)
/* For System RAM protection setting */
#define REGIONID0_WRITE_PRIVILEGE (0x00000001U) /* bit0 */
/* RAM DIVISION AREA ID */
/* RT-SRAM */
#define RTSRAM_ICUMX_IPL_AREA (0U) /* 0xE0000000 -- 0xE003FFFF */
#define RTSRAM_ICUMX_FW_AREA (1U) /* 0xE0040000 -- 0xE00FFFFF */
/* RT-VRAM */
#define RTVRAM_BLANK_AREA (0U) /* 0xE2000000 -- 0xE200FFFF */
#define RTVRAM_EXTEND_CACHE_AREA (1U) /* 0xE2010000 -- 0xE20FFFFF */
#define RTVRAM_RTOS_AREA (2U) /* 0xE2100000 -- 0xE3BFFFFF */
/* System RAM */
#define SYSTEM_RAM_CX_2ND_IPL (0U) /* 0xE6300000 -- 0xE635DFFF */
#define SYSTEM_RAM_SHARED_MEM (1U) /* 0xE635E000 -- 0xE635FFFF */
/* SDRAM */
#if ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M))
#define RTVRAM_EXTEND_AREA (0U) /* 0x04_00000000 -- 0x04_01BFFFFF */
#define CR_FW_SHARED_AREA (1U) /* 0x04_01C00000 -- 0x04_01CFFFFF */
#define SDRAM_BLANK_AREA (2U) /* OPTEE_DISABLE:0x04_01D00000 -- 0x04_063FFFFF
* OPTEE_ENABLE :0x04_01D00000 -- 0x04_040FFFFF */
#define SDRAM_PROTECT_AREA (3U) /* OPTEE_DISABLE:0x04_06400000 -- 0x04_0643FFFF
* OPTEE_ENABLE :0x04_04100000 -- 0x04_0643FFFF */
#if (OPTEE_LOAD_ENABLE == OPTEE_DISABLE)
#define SDRAM_PUBLIC_AREA (4U) /* 0x04_06440000 -- 0x04_07FBFFFF */
#define ICCOM_USED_AREA (5U) /* 0x04_07FC0000 -- 0x04_07FFFFFF */
#define LINUX_USED_AREA (6U) /* 0x04_08000000 -- 0x04_1DBFFFFF */
#define CAAREA2_USED_AREA (7U) /* 0x04_1DC00000 -- 0x04_1FFFFFFF */
#define CR52_USED_AREA (8U) /* 0x04_20000000 -- 0x04_3FFFFFFF */
#define CAAREA3_USED_AREA (9U) /* 0x04_40000000 -- 0x04_5FFFFFFF */
#define CAAREA2_USED_AREA2 (10U) /* 0x04_60000000 -- 0x04_7FFFFFFF */
#define CAAREA1_USED_AREA (11U) /* 0x04_80000000 -- 0x04_FFFFFFFF */
#else
#define SDRAM_PROTECT_AREA2 (4U) /* 0x04_06400000 -- 0x04_0643FFFF */
#define SDRAM_BLANK_AREA2 (5U) /* 0x04_06440000 -- 0x04_07DFFFFF */
#define OPTEE_SHARED_AREA (6U) /* 0x04_07E00000 -- 0x04_07EFFFFF */
#define SDRAM_BLANK_AREA3 (7U) /* 0x04_07F00000 -- 0x04_07FBFFFF */
#define ICCOM_USED_AREA (8U) /* 0x04_07FC0000 -- 0x04_07FFFFFF */
#define LINUX_USED_AREA (9U) /* 0x04_08000000 -- 0x04_1DBFFFFF */
#define CAAREA2_USED_AREA (10U) /* 0x04_1DC00000 -- 0x04_1FFFFFFF */
#define CR52_USED_AREA (11U) /* 0x04_20000000 -- 0x04_3FFFFFFF */
#define CAAREA3_USED_AREA (12U) /* 0x04_40000000 -- 0x04_5FFFFFFF */
#define CAAREA2_USED_AREA2 (13U) /* 0x04_60000000 -- 0x04_7FFFFFFF */
#define CAAREA1_USED_AREA (14U) /* 0x04_80000000 -- 0x04_FFFFFFFF */
#endif /* OPTEE_LOAD_ENABLE == OPTEE_DISABLE */
#if (RCAR_LSI == RCAR_V4H)
#if (OPTEE_LOAD_ENABLE == OPTEE_DISABLE)
#define RESERVERD_AREA (12U) /* 0x05_00000000 -- 0x05_FFFFFFFF */
#define CAAREA1_USED_AREA2 (13U) /* 0x06_00000000 -- 0x06_FFFFFFFF */
#else
#define RESERVERD_AREA (15U) /* 0x05_00000000 -- 0x05_FFFFFFFF */
#define CAAREA1_USED_AREA2 (16U) /* 0x06_00000000 -- 0x06_FFFFFFFF */
#endif /* OPTEE_LOAD_ENABLE == OPTEE_DISABLE */
#elif (RCAR_LSI == RCAR_V4M)
#if (OPTEE_LOAD_ENABLE == OPTEE_DISABLE)
#define CAAREA1_USED_AREA2 (12U) /* 0x05_00000000 -- 0x05_FFFFFFFF */
#define RESERVERD_AREA (13U) /* 0x06_00000000 -- 0x06_FFFFFFFF */
#else
#define CAAREA1_USED_AREA2 (15U) /* 0x05_00000000 -- 0x05_FFFFFFFF */
#define RESERVERD_AREA (16U) /* 0x06_00000000 -- 0x06_FFFFFFFF */
#endif /* OPTEE_LOAD_ENABLE == OPTEE_DISABLE */
#endif /* RCAR_LSI == RCAR_V4H */
#else
#define RTVRAM_EXTEND_AREA (0U) /* 0x04_00000000 -- 0x04_01BFFFFF */
#define SDRAM_BLANK_AREA (1U) /* 0x04_01C00000 -- 0x04_063FFFFF */
#define SDRAM_PROTECT_AREA (2U) /* 0x04_06400000 -- 0x04_0643FFFF */
#define SDRAM_PUBLIC_AREA (3U) /* 0x04_06440000 -- 0x06_FFFFFFFF */
#endif /* ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M)) */
#endif /* RAM_PROTECTION_H_ */

53
Src/0_Tool/Gen4_R-Car_IPL/SDK/v3_46_0/Gen4_ICUMX_Loader/include/rcar_def.h Normal file
View File

@@ -0,0 +1,53 @@
/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright 2021-2025 Renesas Electronics Corporation All rights reserved.
*******************************************************************************/
/*******************************************************************************
* DESCRIPTION : R-Car common header
******************************************************************************/
#ifndef RCAR_DEF_H_
#define RCAR_DEF_H_
#include "remap_register.h"
#include <fcpr.h>
/* Product Register */
#define PRR (0xFFF00044U) /* PRR register */
#define PRR_CA_CL3_STATE_MASK (0x80000000U) /* Cortex-A Cluster 3 State */
#define PRR_PRODUCT_MASK (0x00007F00U) /* Product mask */
#define PRR_CUT_MASK (0x000000FFU) /* Cut Number bit mask */
#define PRR_MAJOR_MASK (0x000000F0U) /* Major bit mask */
#define PRR_MINOR_MASK (0x0000000FU) /* Minor bit mask */
#define PRR_MAJOR_SHIFT (4U) /* Major bit shift */
#define PRR_MAJOR_OFFSET (1U)
#define PRR_PRODUCT_S4 (0x00005A00U) /* R-Car S4 */
#define PRR_PRODUCT_V4H (0x00005C00U) /* R-Car V4H */
#define PRR_PRODUCT_V4M (0x00005D00U) /* R-Car V4M */
#define PRR_PRODUCT_10 (0x00000000U) /* ver 1.0 */
#define PRR_PRODUCT_11 (0x00000001U) /* ver 1.1 */
#define PRR_PRODUCT_20 (0x00000010U) /* ver 2.0 */
#define PRR_PRODUCT_21 (0x00000011U) /* ver 2.1 */
#endif /* RCAR_DEF_H_ */

48
Src/0_Tool/Gen4_R-Car_IPL/SDK/v3_46_0/Gen4_ICUMX_Loader/include/remap.h Normal file
View File

@@ -0,0 +1,48 @@
/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright 2021-2023 Renesas Electronics Corporation All rights reserved.
*******************************************************************************/
/*******************************************************************************
* DESCRIPTION : remap driver header
******************************************************************************/
#ifndef REMAP_H_
#define REMAP_H_
#define ICUMX_CTLREG_BASE (0xFFFEE200U)
#define ICUMX_CFREMAP (ICUMX_CTLREG_BASE + 0x4CU)
#define CFREMAP_AREA_SIZE (0x02000000U)
#include <remap_register.h>
typedef struct{
uint32_t base_addr; /* Base address of Region ID registers. */
uint32_t rmp_addr; /* Stores the address converted from the Region ID base address to SICREMAP address. */
} REMAP_TABLE;
uint32_t remap_get_phys_addr(uint32_t remap_addr);
uint32_t get_cfremap_addr(uint32_t fetch_addr);
uint32_t remap_get_remap_addr(uint32_t phys_addr);
void remap_register(uint32_t addr, uint32_t *remap_addr);
void remap_unregister(uint32_t remap_addr);
void set_sicremap_s4v10(void);
void set_sicremap_fcpr(void);
#endif /* REMAP_H_ */

275
Src/0_Tool/Gen4_R-Car_IPL/SDK/v3_46_0/Gen4_ICUMX_Loader/include/remap_register.h Normal file
View File

@@ -0,0 +1,275 @@
/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright 2021-2025 Renesas Electronics Corporation All rights reserved.
*******************************************************************************/
/*******************************************************************************
* DESCRIPTION : remap register header
******************************************************************************/
#ifndef REMAP_REGISTER_H_
#define REMAP_REGISTER_H_
#include <stdint.h>
#define REMAP_BASE (0xFF1FC400U)
#define ICUMX_PROT0PCMD (0xFFFEE090U)
#define ICUMX_PROT0PS (0xFFFEE094U)
#define PROTCMD_START (0xA5U)
#define PROTS0ERR (0x01U)
#define ICU_REMAP0 (0xFC000000U)
/* REMAP setting */
/* Remap ID(0 -- 15) */
#define ICU_REMAP_NUM_RTRAM (15U) /* RTRAM */
#define ICU_REMAP_NUM_CC (14U) /* CC63S,AXMM,QoS for S4 / V4H */
#define ICU_REMAP_NUM_FCPR (14U) /* FCPR for V4M */
#define ICU_REMAP_NUM_PFC (13U) /* PFC,GPIO,CPGA,RESET */
#define ICU_REMAP_NUM_ECM (12U) /* ECM,AP-System Core */
#define ICU_REMAP_NUM_RPC (11U) /* RPC */
#define ICU_REMAP_NUM_RTDMAC (10U) /* RT-DMAC0,PFC(MCU) */
#define ICU_REMAP_NUM_SCIF (9U) /* SCIF */
#define ICU_REMAP_NUM_MMC (8U) /* MMC */
#define ICU_REMAP_NUM_HSCIF (7U) /* HSCIF */
#define ICU_REMAP_NUM_DMAC (6U) /* SYS-DMAC0 */
#define ICU_REMAP_NUM_RGID (5U) /* Region ID */
#if (RCAR_LSI == RCAR_S4)
#define ICU_REMAP_NUM_MCU (4U) /* MCU */
#endif
/* SICREMAP2M15 */
#define ICU_REMAP_RTSRAM (0xEB200000U) /* RT-SRAM */
/* SICREMAP2M14 */
#define ICU_REMAP_CC (0xE6600000U) /* CC63S,AXMM,QoS,FCPR for S4 / V4H */
/* SICREMAP2M14 */
#define ICU_REMAP_FCPR (0xE6600000U) /* FCPR for V4M */
/* SICREMAP2M13 */
#define ICU_REMAP_PFC (0xE6000000U) /* PFC,GPIO,CPGA,RESET */
/* SICREMAP2M12 */
#define ICU_REMAP_ECM (0xE6200000U) /* ECM,AP-System Core */
/* SICREMAP2M11 */
#define ICU_REMAP_RPC (0xEE200000U) /* RPC */
/* SICREMAP2M10 */
#define ICU_REMAP_RTDMAC (0xFFC00000U) /* RT-DMAC0,PFC(MCU) */
/* SICREMAP2M9 */
#if (RCAR_LSI == RCAR_S4)
#define ICU_REMAP_SCIF (0xE6C00000U) /* SCIF3 */
#elif ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M))
#define ICU_REMAP_SCIF (0xE6E00000U) /* SCIF0 */
#endif /* RCAR_LSI == RCAR_S4 */
/* SICREMAP2M8 */
#define ICU_REMAP_MMC (0xEE000000U) /* MMC */
/* SICREMAP2M7 */
#define ICU_REMAP_HSCIF (0xE6400000U) /* HSCIF */
/* SICREMAP2M6 */
#define ICU_REMAP_DMAC (0xE7200000U) /* SYS-DMAC0 */
/* SICREMAP2M5 */
#define ICU_REMAP_RGID (0xE7600000U) /* Region ID */
#if (RCAR_LSI == RCAR_S4)
/* SICREMAP2M4 */
#define ICU_REMAP_MCU (0xD8E00000U) /* MCU */
#endif
#define ICU_REMAP15_BASE (ICU_REMAP_RTRAM) /* RTRAM */
#define ICU_REMAP14_BASE (ICU_REMAP_CC) /* CC63S,AXMM,QoS,FCPR */
#define ICU_REMAP13_BASE (ICU_REMAP_PFC) /* PFC,GPIO,CPGA,RESET */
#define ICU_REMAP12_BASE (ICU_REMAP_ECM) /* ECM,AP-System Core */
#define ICU_REMAP11_BASE (ICU_REMAP_RPC) /* RPC */
#define ICU_REMAP10_BASE (ICU_REMAP_RTDMAC) /* RT-DMAC0 */
#define ICU_REMAP9_BASE (ICU_REMAP_SCIF) /* SCIF */
#define ICU_REMAP8_BASE (ICU_REMAP_MMC) /* MMC */
#define ICU_REMAP7_BASE (ICU_REMAP_HSCIF) /* HSCIF */
#define ICU_REMAP6_BASE (ICU_REMAP_DMAC) /* SYS-DMAC0 */
#define ICU_REMAP5_BASE (ICU_REMAP_RGID) /* Region ID */
#if (RCAR_LSI == RCAR_S4)
#define ICU_REMAP4_BASE (ICU_REMAP_MCU) /* MCU */
#elif ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M))
#define ICU_REMAP4_BASE (0x00000000U) /* Reserved */
#endif
#define ICU_REMAP3_BASE (0x00000000U) /* Reserved */
#define ICU_REMAP2_BASE (0x00000000U) /* Reserved */
#define ICU_REMAP1_BASE (0x00000000U) /* Reserved */
#define ICU_REMAP0_BASE (0x00000000U) /* Reserved */
/* Base address offset of each register after remap */
/* REMAP15(0xEB200000U) */
/* RT-SRAM */
#define ICU_REMAP_OFFSET_RTSRAM (0x00000000U)
/* REMAP14(0xE6600000U) */
#define ICU_REMAP_OFFSET_CC63S (0x00000000U)
#define ICU_REMAP_OFFSET_DBSC (0x00190000U) /* (0xE6790000U) */
#define ICU_REMAP_OFFSET_AXMM (0x00180000U) /* (0xE6780000U) */
#if (RCAR_LSI == RCAR_S4)
#define ICU_REMAP_OFFSET_CCI (0x001a0000U) /* (0xE67A0000U) */
#define ICU_REMAP_OFFSET_QOS (0x001e0000U) /* (0xE67E0000U) */
#elif ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M))
#define ICU_REMAP_OFFSET_FCPR (0x00185700U) /* (0xE6785700U) */
#if (RCAR_LSI == RCAR_V4M)
#define ICU_REMAP_OFFSET_I2C3 (0x000D0000U) /* (0xE66D0000U) */
#define ICU_REMAP_OFFSET_QOS (0x001e0000U) /* (0xE67E0000U) */
#endif /* (RCAR_LSI == RCAR_V4M) */
#endif /* (RCAR_LSI == RCAR_S4) */
/* REMAP13(0xE6000000U) */
/* PFC */
#define ICU_REMAP_OFFSET_PFC (0x00050000U)
/* EFUSE */
#define ICU_REMAP_OFFSET_EFUSE (0x00078800U)
/* CPGA */
#define ICU_REMAP_OFFSET_CPGA (0x00150000U)
/* RESET */
#define ICU_REMAP_OFFSET_RESET (0x00160000U)
/* APMU */
#define ICU_REMAP_OFFSET_APMU (0x00170000U)
/* SYSC */
#define ICU_REMAP_OFFSET_SYSC (0x00180000U)
/* OTP */
#define ICU_REMAP_OFFSET_OTP (0x001BF000U)
#if (RCAR_LSI == RCAR_V4M)
#define ICU_REMAP_OFFSET_AVS (0x000A0000U) /* (0xE60A0000U) */
#endif /* (RCAR_LSI == RCAR_V4M) */
/* REMAP12(0xE6200000U) */
/* ECM */
#define ICU_REMAP_OFFSET_MFIS (0x00060000U)
#define ICU_REMAP_OFFSET_SDRAM_ECC (0x00050000U)
#define ICU_REMAP_OFFSET_AP_CORE (0x00080000U)
/* REMAP11(0xEE200000U) */
/*RPC*/
#define ICU_REMAP_OFFSET_RPC (0x00000000U)
/* REMAP10(0xFFC00000U) */
/* RT-DMA */
#define ICU_REMAP_OFFSET_RTDMA0 (0x00010000U)
#define ICU_REMAP_OFFSET_RTDMACTL (0x00160000U)
#define ICU_REMAP_OFFSET_PFCMCU (0x00190000U)
#if (RCAR_LSI == RCAR_S4)
/* REMAP9(0xE6C00000U) */
/*SCIF*/
#define ICU_REMAP_OFFSET_SCIF3 (0x00050000U)
#elif ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M))
/* REMAP9(0xE6E00000U) */
/*SCIF*/
#define ICU_REMAP_OFFSET_SCIF0 (0x00060000U)
#endif /* RCAR_LSI == RCAR_S4 */
/* REMAP8(0xEE000000U) */
/* SDHI2/MMC0 */
#define ICU_REMAP_OFFSET_SDHI (0x00140000U)
/* REMAP7(0xE6400000U) */
/* HSCIF */
#define ICU_REMAP_OFFSET_HSCIF0 (0x00140000U)
/* REMAP6(0xE7200000U) */
/* SYS-DMAC */
#define ICU_REMAP_OFFSET_SYSDMAC (0x00100000U)
/* REMAP5(0xE7600000U) */
/* Region ID */
#if ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M))
#define ICU_REMAP_OFFSET_ICISTP (0x00100000U)
#endif
#define ICU_REMAP_OFFSET_RGID (0x00150000U)
#if (RCAR_LSI == RCAR_S4)
/* REMAP4(0xD8E00000U) */
/* MCU */
#define ICU_REMAP_OFFSET_MCU (0x00100000U)
#endif
/* REMAP15(0xEB200000U) */
#define BASE_RTSRAM_ADDR (icu_remap_calc(ICU_REMAP_NUM_RTRAM) + ICU_REMAP_OFFSET_RTSRAM)
/* REMAP14(0xE6600000U) */
#define BASE_DBSC_ADDR (icu_remap_calc(ICU_REMAP_NUM_CC) + ICU_REMAP_OFFSET_DBSC)
#define BASE_AXMM_ADDR (icu_remap_calc(ICU_REMAP_NUM_CC) + ICU_REMAP_OFFSET_AXMM)
#if (RCAR_LSI == RCAR_S4)
#define BASE_CCI_ADDR (icu_remap_calc(ICU_REMAP_NUM_CC) + ICU_REMAP_OFFSET_CCI)
#define BASE_QOS_ADDR (icu_remap_calc(ICU_REMAP_NUM_CC) + ICU_REMAP_OFFSET_QOS)
#elif ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M))
#define BASE_FCPR_ADDR (icu_remap_calc(ICU_REMAP_NUM_CC) + ICU_REMAP_OFFSET_FCPR)
#if (RCAR_LSI == RCAR_V4M)
#define BASE_I2C3_ADDR (icu_remap_calc(ICU_REMAP_NUM_CC) + ICU_REMAP_OFFSET_I2C3)
#define BASE_QOS_ADDR (icu_remap_calc(ICU_REMAP_NUM_CC) + ICU_REMAP_OFFSET_QOS)
#endif /* (RCAR_LSI == RCAR_V4M) */
#endif /* (RCAR_LSI == RCAR_S4) */
/* REMAP13(0xE6000000U) */
#define BASE_EFUSE_ADDR (icu_remap_calc(ICU_REMAP_NUM_PFC) + ICU_REMAP_OFFSET_EFUSE)
#define BASE_PFC_ADDR (icu_remap_calc(ICU_REMAP_NUM_PFC) + ICU_REMAP_OFFSET_PFC)
#define BASE_CPG_ADDR (icu_remap_calc(ICU_REMAP_NUM_PFC) + ICU_REMAP_OFFSET_CPGA)
#define BASE_RESET_ADDR (icu_remap_calc(ICU_REMAP_NUM_PFC) + ICU_REMAP_OFFSET_RESET)
#define BASE_APMU_ADDR (icu_remap_calc(ICU_REMAP_NUM_PFC) + ICU_REMAP_OFFSET_APMU)
#define BASE_SYSC_ADDR (icu_remap_calc(ICU_REMAP_NUM_PFC) + ICU_REMAP_OFFSET_SYSC)
#define BASE_OTP_MEM_ADDR (icu_remap_calc(ICU_REMAP_NUM_PFC) + ICU_REMAP_OFFSET_OTP)
#if (RCAR_LSI == RCAR_V4M)
#define BASE_AVS_ADDR (icu_remap_calc(ICU_REMAP_NUM_PFC) + ICU_REMAP_OFFSET_AVS)
#endif /* (RCAR_LSI == RCAR_V4M) */
/* REMAP12(0xE6200000U) */
#if ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M))
#define BASE_ECM_ADDR (icu_remap_calc(ICU_REMAP_NUM_ECM))
#endif
#define BASE_MFIS_ADDR (icu_remap_calc(ICU_REMAP_NUM_ECM) + ICU_REMAP_OFFSET_MFIS)
#define BASE_ECC_ADDR (icu_remap_calc(ICU_REMAP_NUM_ECM) + ICU_REMAP_OFFSET_SDRAM_ECC)
#define BASE_AP_CORE_ADDR (icu_remap_calc(ICU_REMAP_NUM_ECM) + ICU_REMAP_OFFSET_AP_CORE)
/* REMAP11(0xEE200000U) */
#define BASE_RPC_ADDR (icu_remap_calc(ICU_REMAP_NUM_RPC) + ICU_REMAP_OFFSET_RPC)
/* REMAP10(0xFFC00000U) */
#define BASE_RTDMA0_ADDR (icu_remap_calc(ICU_REMAP_NUM_RTDMAC) + ICU_REMAP_OFFSET_RTDMA0)
#define BASE_RTDMACTL_ADDR (icu_remap_calc(ICU_REMAP_NUM_RTDMAC) + ICU_REMAP_OFFSET_RTDMACTL)
#if (RCAR_LSI == RCAR_S4)
#define BASE_PFCMCU_ADDR (icu_remap_calc(ICU_REMAP_NUM_RTDMAC) + ICU_REMAP_OFFSET_PFCMCU)
#endif
#if (RCAR_LSI == RCAR_S4)
/* REMAP9(0xE6C00000U) */
#define BASE_SCIF_ADDR (icu_remap_calc(ICU_REMAP_NUM_SCIF) + ICU_REMAP_OFFSET_SCIF3)
#elif ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M))
/* REMAP9(0xE6E00000U) */
#define BASE_SCIF_ADDR (icu_remap_calc(ICU_REMAP_NUM_SCIF) + ICU_REMAP_OFFSET_SCIF0)
#endif /* RCAR_LSI == RCAR_S4 */
/* REMAP8(0xEE000000U) */
#define BASE_MMC0_ADDR (icu_remap_calc(ICU_REMAP_NUM_MMC) + ICU_REMAP_OFFSET_SDHI)
/* REMAP7(0xE6400000U) */
#define BASE_HSCIF_ADDR (icu_remap_calc(ICU_REMAP_NUM_HSCIF) + ICU_REMAP_OFFSET_HSCIF0)
/* REMAP6(0xE7200000U) */
#define BASE_DMA_ADDR (icu_remap_calc(ICU_REMAP_NUM_DMAC) + ICU_REMAP_OFFSET_SYSDMAC)
/* REMAP5(0xE7600000U) */
#if ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M))
#define BASE_ICISTP_ADDR (icu_remap_calc(ICU_REMAP_NUM_RGID) + ICU_REMAP_OFFSET_ICISTP)
#endif
#define BASE_RGID_ADDR (icu_remap_calc(ICU_REMAP_NUM_RGID) + ICU_REMAP_OFFSET_RGID)
#if (RCAR_LSI == RCAR_S4)
/* REMAP4(0xD8E00000U) */
#define BASE_MCU_ADDR (icu_remap_calc(ICU_REMAP_NUM_MCU) + ICU_REMAP_OFFSET_MCU)
#endif
/* Calculate the base address of each register after remapping */
static inline uint32_t icu_remap_calc(uint32_t num)
{
return (ICU_REMAP0 + (num * 0x00200000U));
}
/* End of function icu_remap_calc(uint32_t num) */
#endif /* REMAP_REGISTER_H_ */

73
Src/0_Tool/Gen4_R-Car_IPL/SDK/v3_46_0/Gen4_ICUMX_Loader/include/rom_api.h Normal file
View File

@@ -0,0 +1,73 @@
/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright 2021-2022 Renesas Electronics Corporation All rights reserved.
*******************************************************************************/
/*******************************************************************************
* DESCRIPTION : boot ROM API header
******************************************************************************/
#ifndef ROM_API_H__
#define ROM_API_H__
#include <stdint.h>
#include <image_load.h>
#define SECURE_BOOT (0x0U)
#define NORMAL_BOOT (0x211883DFU)
#define ROMAPI_OK (0x00000000U)
#define ROM_ERR_IMG_VERIFIER_NO_ENCRYPT_IMG (0xF100001DU)
#define LCS_CM (0x00000000U) /* CM */
#define LCS_DM (0x00000001U) /* DM */
#define LCS_SD (0x00000003U) /* SD */
#define LCS_SE (0x00000005U) /* SE */
#define LCS_FA (0x00000007U) /* FA */
/* BOOTROM API address */
#define ROM_GETLCS (0x01104418U)
#define ROM_SECUREBOOT_VERIFY (0x011044C8U)
#define ROM_SECUREBOOT_DECRYPT (0x011044D0U)
#define ROM_SECUREBOOT_COMPARE (0x011044D8U)
/* For build option SW_VERSION_CHECK */
#define OPT_VERSION_CHECK_ENABLE (1U)
typedef uint32_t (*ROM_SECUREBOOT_VERIFY_API)(uint32_t *pKeyCert, uint32_t *pContentCert);
typedef uint32_t (*ROM_SECUREBOOT_DECRYPT_API)(uint32_t *pContentCert);
typedef uint32_t (*ROM_SECUREBOOT_COMPARE_API)(uint32_t *pContentCert,
uint32_t *hash,
uint32_t hash_size);
typedef uint32_t (*ROM_GETLCS_API)(uint32_t *pLcs, uint32_t lcs_size);
static inline uint32_t get_load_info_id(const LOAD_INFO *li)
{
return ((li->cnt_cert_addr - (SA9_DEST_ADDR + CONTENT_CERT_OFFSET)) / CONTENT_CERT_SIZE);
}
/* End of function get_load_info_id(LOAD_INFO *li) */
void rom_secureboot(LOAD_INFO* li);
uint32_t call_ROM_GetLcs(uint32_t *pLcs, uint32_t lcs_size);
void sw_version_check(const LOAD_INFO* li);
void auth_min_ver_tbl(LOAD_INFO* li);
void preload_verify_cntcert(const LOAD_INFO* li);
#endif /* ROM_API_H__ */

87
Src/0_Tool/Gen4_R-Car_IPL/SDK/v3_46_0/Gen4_ICUMX_Loader/include/rpc.h Normal file
View File

@@ -0,0 +1,87 @@
/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright 2021-2022 Renesas Electronics Corporation All rights reserved.
*******************************************************************************/
/*******************************************************************************
* DESCRIPTION : RPC driver header
******************************************************************************/
#ifndef RPC_H__
#define RPC_H__
#include <stdint.h>
#include <rpc_register.h>
/* If user customizes for another vendor's QSPI Flash, set to 1. */
#define USER_ADDED_QSPI (0U) /* 0:Disable 1:Enable */
/* The number of Flash vendor */
#if USER_ADDED_QSPI == 0
#define VENDOR_NUM (1U)
#endif /* USER_ADDED_QSPI == 0 */
/* Command for S25FS512S */
#define S25FS512S_READ_32BIT_ADDR (0x13U) /* read 32bit address */
#define S25FS512S_DDR_QUAD_IO_READ_32BIT_ADDR (0xEEU) /* DDR quad I/O read 32bit address */
#if USER_ADDED_QSPI == 1
/* User can customize for another vendor's QSPI Flash. */
#define VENDOR_NUM (2U)
/* Command for XXXXXXXXX */
#define XXXXXXXXX_READ_32BIT_ADDR (0x00U) /* read 32bit address */
#define XXXXXXXXX_DDR_QUAD_IO_READ_32BIT_ADDR (0x00U) /* DDR quad I/O read 32bit address */
#endif /* USER_ADDED_QSPI == 1 */
typedef struct {
uint32_t read_32bit_addr;
uint32_t ddr_quad_io_read_32bit_addr;
} st_qspi_cmd_tbl_t;
static const st_qspi_cmd_tbl_t qspi_cmd_tbls[VENDOR_NUM] =
{
/* Command table for S25FS512S */
{
S25FS512S_READ_32BIT_ADDR, /* read 32bit address */
S25FS512S_DDR_QUAD_IO_READ_32BIT_ADDR /* DDR quad I/O read 32bit address */
},
#if USER_ADDED_QSPI == 1
/* Command table for XXXXXXXXX */
/* User can customize for another vendor's QSPI Flash. */
{
XXXXXXXXX_READ_32BIT_ADDR, /* read 32bit address */
XXXXXXXXX_DDR_QUAD_IO_READ_32BIT_ADDR /* DDR quad I/O read 32bit address */
}
#endif /* USER_ADDED_QSPI == 1 */
};
void rpc_init(void);
void rpc_release(void);
void rpc_end_state_check(void);
#if (QSPI_DDR_MODE==1)
void qspi_ddr_transfer_mode(uint32_t command);
#else
void qspi_sdr_transfer_mode(uint32_t command);
#endif
#endif /* RPC_H__ */

54
Src/0_Tool/Gen4_R-Car_IPL/SDK/v3_46_0/Gen4_ICUMX_Loader/include/rpc_register.h Normal file
View File

@@ -0,0 +1,54 @@
/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright 2021-2022 Renesas Electronics Corporation All rights reserved.
*******************************************************************************/
/*******************************************************************************
* DESCRIPTION : RPC register header
******************************************************************************/
#ifndef RPC_REGISTER_H_
#define RPC_REGISTER_H_
#include <remap_register.h>
/* RPC base address */
/* 0xEE200000 */
#define RPC_BASE (BASE_RPC_ADDR)
#define RPC_CMNCR (RPC_BASE + 0x0000U) /* Common control register */
#define RPC_DRCR (RPC_BASE + 0x000CU) /* Data read control register */
#define RPC_DRCMR (RPC_BASE + 0x0010U) /* Data read command setting register */
#define RPC_DREAR (RPC_BASE + 0x0014U) /* Data read extended address register */
#define RPC_DRENR (RPC_BASE + 0x001CU) /* Data read enable setting register */
#define RPC_SMCR (RPC_BASE + 0x0020U) /* Manual mode control register */
#define RPC_SMCMR (RPC_BASE + 0x0024U) /* Manual mode command setting register */
#define RPC_SMENR (RPC_BASE + 0x0030U) /* Manual mode enable setting register */
#define RPC_SMRDR0 (RPC_BASE + 0x0038U) /* Manual mode read data register 0 */
#define RPC_CMNSR (RPC_BASE + 0x0048U) /* Common status register */
#define RPC_DRDMCR (RPC_BASE + 0x0058U) /* Data read Dummy Cycle setting register */
#define RPC_DRDRENR (RPC_BASE + 0x005CU) /* Data read DDR enable register */
#define RPC_SMDRENR (RPC_BASE + 0x0064U) /* Manual mode DDR enable register */
#define RPC_PHYCNT (RPC_BASE + 0x007CU) /* PHY control register */
#define RPC_PHYOFFSET1 (RPC_BASE + 0x0080U) /* PHY Timing Offset Register 1 */
#endif /* RPC_REGISTER_H_ */

53
Src/0_Tool/Gen4_R-Car_IPL/SDK/v3_46_0/Gen4_ICUMX_Loader/include/rst_register.h Normal file
View File

@@ -0,0 +1,53 @@
/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright 2021-2022 Renesas Electronics Corporation All rights reserved.
*******************************************************************************/
/*******************************************************************************
* DESCRIPTION : RST register header
******************************************************************************/
#ifndef RST_REGISTER_H_
#define RST_REGISTER_H_
#include <remap_register.h>
#define RST_BASE (BASE_RESET_ADDR) /* 0xE6160000 */
#define RST_MODEMR0 (RST_BASE + 0x0000U) /* Mode pin register0 */
#define RST_MODEMR1 (RST_BASE + 0x0004U) /* Mode pin register1 */
#define RST_MODEMR0_MD31 (1U << 31U)
#define RST_MODEMR1_MD32 (1U << 0U)
#define RST_MODEMR0_BOOT_DEV_MASK (0x0000001EU)
#define RST_MODEMR0_BOOT_DEV_HYPERFLASH160 (0x00000004U)
#define RST_MODEMR0_BOOT_DEV_HYPERFLASH80 (0x00000006U)
#define RST_MODEMR0_BOOT_DEV_QSPI_FLASH40 (0x00000008U)
#define RST_MODEMR0_BOOT_DEV_EMMC_50X8 (0x0000001AU)
#define RST_WDTRSTCR (RST_BASE + 0x0010U)
/* SCIF / HSCIF clock speed */
#define MODEMR_SCIF_DLMODE (0x00000000U)
#define MODEMR_HSCIF_DLMODE_921600 (0x00000001U)
#define MODEMR_HSCIF_DLMODE_1843200 (0x00000002U)
#define MODEMR_HSCIF_DLMODE_3000000 (0x00000003U)
#endif /* RST_REGISTER_H_ */

65
Src/0_Tool/Gen4_R-Car_IPL/SDK/v3_46_0/Gen4_ICUMX_Loader/include/rtsram_register.h Normal file
View File

@@ -0,0 +1,65 @@
/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright 2023 Renesas Electronics Corporation All rights reserved.
*******************************************************************************/
/*******************************************************************************
* DESCRIPTION : RT-SRAM register header
******************************************************************************/
#ifndef RTSRAM_REGISTER_H__
#define RTSRAM_REGISTER_H__
#include <stdint.h>
/* RT-SRAM register base address */
#define RTSRAM_REG_BASE (0xFFE90000U)
#define RTSRAM_SECDIVD (RTSRAM_REG_BASE + 0x0000U)
#define RTSRAM_SECCTRRD (RTSRAM_REG_BASE + 0x0040U)
#define RTSRAM_SECCTRWD (RTSRAM_REG_BASE + 0x0340U)
#if (RCAR_LSI == RCAR_S4)
#define RTSRAM_SECDIVD_DIVADDR_MASK (0x000000FFU)
#else
#define RTSRAM_SECDIVD_DIVADDR_MASK (0x000FFFFFU)
#endif
#define RTSRAM_SECCTRRD_SECGRP_MASK (0x000F0000U)
#define RTSRAM_SECCTRRD_SAFGRP_MASK (0x0000FFFFU)
#define RTSRAM_SECCTRWD_SECGRP_MASK (0x000F0000U)
#define RTSRAM_SECCTRWD_SAFGRP_MASK (0x0000FFFFU)
static inline uint32_t get_rtsram_secdivd_addr(uint32_t num)
{
return ((RTSRAM_SECDIVD + (num * 4U)));
}
static inline uint32_t get_rtsram_secctrrd_addr(uint32_t num)
{
return ((RTSRAM_SECCTRRD + (num * 4U)));
}
static inline uint32_t get_rtsram_secctrwd_addr(uint32_t num)
{
return ((RTSRAM_SECCTRWD + (num * 4U)));
}
#endif /* RTSRAM_REGISTER_H__ */

35
Src/0_Tool/Gen4_R-Car_IPL/SDK/v3_46_0/Gen4_ICUMX_Loader/include/rtvram.h Normal file
View File

@@ -0,0 +1,35 @@
/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright 2021-2022 Renesas Electronics Corporation All rights reserved.
*******************************************************************************/
/*******************************************************************************
* DESCRIPTION : RT-VRAM driver header
******************************************************************************/
#ifndef RTVRAM_H_
#define RTVRAM_H_
#include <rtvram_register.h>
void rtvram_extendmode(void);
#endif /* RTVRAM_H__ */

70
Src/0_Tool/Gen4_R-Car_IPL/SDK/v3_46_0/Gen4_ICUMX_Loader/include/rtvram_register.h Normal file
View File

@@ -0,0 +1,70 @@
/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright 2021-2023 Renesas Electronics Corporation All rights reserved.
*******************************************************************************/
/*******************************************************************************
* DESCRIPTION : RT-VRAM register header
******************************************************************************/
#ifndef RTVRAM_REGISTER_H__
#define RTVRAM_REGISTER_H__
#include <stdint.h>
/* RT-VRAM register base address */
#define RTVRAM_REG_BASE (0xFFEC0000U)
#define RTVRAM_SECDIVD (RTVRAM_REG_BASE + 0x0000U)
#define RTVRAM_SECCTRRD (RTVRAM_REG_BASE + 0x0040U)
#define RTVRAM_SECCTRWD (RTVRAM_REG_BASE + 0x0340U)
#define RTVRAM_EXT_MODE (RTVRAM_REG_BASE + 0x8500U)
#define RTVRAM_VBUF_CFG (RTVRAM_REG_BASE + 0x6504U)
#define RTVRAM_CACHE_FLUSH (RTVRAM_REG_BASE + 0x4530U)
#define RTVRAM_VBUF_BADDR (RTVRAM_REG_BASE + 0xC580U)
#define RTVRAM_SECDIVD_DIVADDR_MASK (0x000FFFFFU)
#define RTVRAM_SECCTRRD_SECGRP_MASK (0x000F0000U)
#define RTVRAM_SECCTRRD_SAFGRP_MASK (0x0000FFFFU)
#define RTVRAM_SECCTRWD_SECGRP_MASK (0x000F0000U)
#define RTVRAM_SECCTRWD_SAFGRP_MASK (0x0000FFFFU)
static inline uint32_t get_rtvram_secdivd_addr(uint32_t num)
{
return ((RTVRAM_SECDIVD + (num * 4U)));
}
static inline uint32_t get_rtvram_secctrrd_addr(uint32_t num)
{
return ((RTVRAM_SECCTRRD + (num * 4U)));
}
static inline uint32_t get_rtvram_secctrwd_addr(uint32_t num)
{
return ((RTVRAM_SECCTRWD + (num * 4U)));
}
static inline uint32_t get_vbuf_baddr_addr(uint32_t num)
{
return ((RTVRAM_VBUF_BADDR + (num * 4U)));
}
#endif /* RTVRAM_REGISTER_H__ */

38
Src/0_Tool/Gen4_R-Car_IPL/SDK/v3_46_0/Gen4_ICUMX_Loader/include/scif.h Normal file
View File

@@ -0,0 +1,38 @@
/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright 2021-2022 Renesas Electronics Corporation All rights reserved.
*******************************************************************************/
/*******************************************************************************
* DESCRIPTION : SCIF driver header
******************************************************************************/
#ifndef SCIF_H_
#define SCIF_H_
#include <scif_register.h>
#include <hscif_register.h>
/* Prototype */
void scif_init(void);
void console_putc(uint8_t outchar);
#endif /* SCIF_H_ */

47
Src/0_Tool/Gen4_R-Car_IPL/SDK/v3_46_0/Gen4_ICUMX_Loader/include/scif_register.h Normal file
View File

@@ -0,0 +1,47 @@
/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright 2021-2022 Renesas Electronics Corporation All rights reserved.
*******************************************************************************/
/*******************************************************************************
* DESCRIPTION : SCIF register header
******************************************************************************/
#ifndef SCIF_REGISTER_H_
#define SCIF_REGISTER_H_
#include <remap_register.h>
/* SCIF base address */
/* S4:0xE6C50000(CH3), V4H:0xE6E60000(CH0) */
#define SCIF_BASE (BASE_SCIF_ADDR)
#define SCIF_SCSMR (SCIF_BASE + 0x0000U) /* 16 Serial mode register */
#define SCIF_SCBRR (SCIF_BASE + 0x0004U) /* 8 Bit rate register */
#define SCIF_SCSCR (SCIF_BASE + 0x0008U) /* 16 Serial control register */
#define SCIF_SCFTDR (SCIF_BASE + 0x000CU) /* 8 Transmit FIFO data register */
#define SCIF_SCFSR (SCIF_BASE + 0x0010U) /* 16 Serial status register */
#define SCIF_SCFCR (SCIF_BASE + 0x0018U) /* 16 FIFO control register */
#define SCIF_SCLSR (SCIF_BASE + 0x0024U) /* 16 Line status register */
#define SCIF_CKS (SCIF_BASE + 0x0034U) /* 16 Clock Select register */
#endif /* SCIF_REGISTER_H_ */

71
Src/0_Tool/Gen4_R-Car_IPL/SDK/v3_46_0/Gen4_ICUMX_Loader/include/sysc.h Normal file
View File

@@ -0,0 +1,71 @@
/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright 2023-2025 Renesas Electronics Corporation All rights reserved.
*******************************************************************************/
/*******************************************************************************
* DESCRIPTION : sysc header
******************************************************************************/
/******************************************************************************
* @file sysc.h
* - Version : 0.02
* @brief
* .
*****************************************************************************/
/******************************************************************************
* History : DD.MM.YYYY Version Description
* : 29.09.2023 0.01 First Release
* : 08.01.2025 0.02 Add write protection register definition.
*****************************************************************************/
#ifndef SYSC_H_
#define SYSC_H_
#include <stdint.h>
#include <remap_register.h>
#define BASE_SYSC (BASE_SYSC_ADDR) /* SYSC logical address 0xFDB80000 */
/* SYSC physical address 0xE6180000 */
#if (RCAR_LSI == RCAR_V4M)
#define SYSC_SYSCSR (BASE_SYSC + 0x0000U)
#define SYSC_SYSCISCR0 (BASE_SYSC + 0x0810U)
#define SYSC_SYSCIER0 (BASE_SYSC + 0x0820U)
#define SYSC_SYSCIMR0 (BASE_SYSC + 0x0830U)
#define SYSC_PDRONCR31 (BASE_SYSC + 0x1004U + (31U * 64U)) /* Power Domain:C4 */
#endif /* RCAR_LSI == RCAR_V4M */
#define SYSC_SYSCD1WACR0 (BASE_SYSC + 0x3020U)
#define SYSC_SYSCD2WACR0 (BASE_SYSC + 0x3040U)
#define SYSC_SYSCD3WACR0 (BASE_SYSC + 0x3060U)
#if (RCAR_LSI == RCAR_V4M)
#define SYSCIER0_PDR31 (0x80000000U) /* Bit31 */
#define SYSCIMR0_PDR31 (0x80000000U) /* Bit31 */
#define SYSCISCR0_PDR31 (0x80000000U) /* Bit31 */
#define SYSCSR_BUSY1 (0x00000002U) /* Bit1 */
#define PDRONCR31_PWRON (0x00000001U) /* Bit0 */
#endif /* RCAR_LSI == RCAR_V4M */
/* Prototype */
#if (RCAR_LSI == RCAR_V4M)
void sysc_c4_power_on(void);
#endif /* RCAR_LSI == RCAR_V4M */
#endif /* SYSC_H_ */

57
Src/0_Tool/Gen4_R-Car_IPL/SDK/v3_46_0/Gen4_ICUMX_Loader/include/types.h Normal file
View File

@@ -0,0 +1,57 @@
/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright 2021-2022 Renesas Electronics Corporation All rights reserved.
*******************************************************************************/
/*******************************************************************************
* DESCRIPTION : Types Define header
******************************************************************************/
#ifndef TYPES_H
#define TYPES_H
#ifdef __cplusplus
extern "C"
{
#endif
/****************************************************************************
* File Name: types.h
* Contents : Types Define
****************************************************************************/
#include <stdint.h>
#include <stddef.h>
#ifndef FALSE
#define FALSE (0U)
#endif
#ifndef TRUE
#define TRUE (1U)
#endif
#ifdef __cplusplus
}
#endif
#endif

35
Src/0_Tool/Gen4_R-Car_IPL/SDK/v3_46_0/Gen4_ICUMX_Loader/include/vect_set.h Normal file
View File

@@ -0,0 +1,35 @@
/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright 2022 Renesas Electronics Corporation All rights reserved.
*******************************************************************************/
/*******************************************************************************
* DESCRIPTION : Set vector table function header
******************************************************************************/
#ifndef VECT_SET_H__
#define VECT_SET_H__
extern char __ghsbegin_EIINTTBL_ICU[];
void set_vect_table(void);
#endif /* VECT_SET_H__ */

36
Src/0_Tool/Gen4_R-Car_IPL/SDK/v3_46_0/Gen4_ICUMX_Loader/include/wdt.h Normal file
View File

@@ -0,0 +1,36 @@
/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright 2022 Renesas Electronics Corporation All rights reserved.
*******************************************************************************/
/*******************************************************************************
* DESCRIPTION : window watchdog timer function header
******************************************************************************/
#ifndef WDT_H__
#define WDT_H__
void wdt_init(void);
void wdt_restart(void);
void wdt_handler(void);
#endif /* WDT_H__ */

155
Src/0_Tool/Gen4_R-Car_IPL/SDK/v3_46_0/Gen4_ICUMX_Loader/intc/intc.c Normal file
View File

@@ -0,0 +1,155 @@
/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright 2022-2023 Renesas Electronics Corporation All rights reserved.
*******************************************************************************/
/*******************************************************************************
* DESCRIPTION : Interrupt controler driver
******************************************************************************/
/******************************************************************************
* @file intc.c
* - Version : 0.02
* @brief Interrupt controler driver.
* .
*****************************************************************************/
/******************************************************************************
* History : DD.MM.YYYY Version Description
* : 06.01.2022 0.01 First Release
* : 05,04.2023 0.02 Remove string.h
*****************************************************************************/
#include <v800_ghs.h>
#include <stdint.h>
#include <mem_io.h>
#include <rst_register.h>
#include <intc.h>
#include <log.h>
#include <cpu.h>
#include <intc.h>
#define INTC_EI_MAX (64U)
#define INTC_EI_ID_MASK (0xFFU)
#define ICUMX_IC_MK_BIT (0x0080U) /* Interrupt request mask */
#define ICUMX_IC_TB_BIT (0x0040U) /* Vector table selection system */
#define ICUMX_IC_PRIORITY_MASK (0x0007U)
#define INT_FLG_ENABLE (0x10U)
#define INT_FLG_DISABLE (0x00U)
#define EXCEPTION_SOURCE_CODE_BIT (0x1000U)
typedef struct {
INT_HANDLER handler;
uint32_t arg;
uint32_t flg;
} INTC_HDR_TBL;
static INTC_HDR_TBL s_intc_tbl[INTC_EI_MAX];
void intc_set_interrupt(uint32_t int_no, uint32_t level, INT_HANDLER cb)
{
uint16_t reg;
__DI();
/* check Exception Source code */
if (INTC_EI_MAX <= int_no)
{
ERROR("Undefined Exception Source code error.(0x%x)\n", int_no);
panic;
}
/* set interrupt handler */
s_intc_tbl[int_no].handler = cb;
s_intc_tbl[int_no].flg = INT_FLG_ENABLE;
/* the interrupt enable */
reg = mem_read16(get_icumx_ic_addr(int_no));
reg &= (~(ICUMX_IC_MK_BIT) | ICUMX_IC_PRIORITY_MASK);
reg |= (ICUMX_IC_TB_BIT | (level & ICUMX_IC_PRIORITY_MASK));
mem_write16(get_icumx_ic_addr(int_no), reg);
__EI();
}
/* End of function intc_set_interrupt(uint32_t int_no, uint32_t level, INT_HANDLER cb) */
void intc_disable_interrupt(uint32_t int_no)
{
uint16_t reg;
__DI();
/* check Exception Source code */
if (INTC_EI_MAX <= int_no)
{
ERROR("Undefined Exception Source code error.(0x%x)\n", int_no);
panic;
}
/* check interrupt enable flag */
if (INT_FLG_DISABLE == (s_intc_tbl[int_no].flg & INT_FLG_ENABLE))
{
ERROR("Execption disabled.(0x%x)\n", int_no);
panic;
}
/* the interrupt disable */
s_intc_tbl[int_no].flg &= ~INT_FLG_ENABLE;
reg = mem_read16(get_icumx_ic_addr(int_no));
reg &= ~(ICUMX_IC_TB_BIT);
reg |= ICUMX_IC_MK_BIT;
mem_write16(get_icumx_ic_addr(int_no), reg);
__EI();
}
/* End of function intc_disable_interrupt(uint32_t int_no) */
#pragma ghs interrupt(nonreentrant)
void intc_handler(void)
{
uint32_t reg;
uint32_t int_no;
reg = __STSR(EIIC);
/* check Exception Source code */
if ((reg & EXCEPTION_SOURCE_CODE_BIT) == 0U)
{
ERROR("Undefined Exception Source code error.(0x%x)\n", reg);
panic;
}
int_no = reg & INTC_EI_ID_MASK;
if (INTC_EI_MAX <= int_no)
{
ERROR("Undefined Exception Source code error.(0x%x)\n", int_no);
panic;
}
/* check interrupt enable flag */
if (INT_FLG_DISABLE == (s_intc_tbl[int_no].flg & INT_FLG_ENABLE))
{
ERROR("Execption disabled.(0x%x)\n", int_no);
panic;
}
/* execute interrupt handler */
s_intc_tbl[int_no].handler(int_no, s_intc_tbl[int_no].arg);
}
/* End of function intc_handler(void) */

50
Src/0_Tool/Gen4_R-Car_IPL/SDK/v3_46_0/Gen4_ICUMX_Loader/intc/vect_set.c Normal file
View File

@@ -0,0 +1,50 @@
/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright 2022 Renesas Electronics Corporation All rights reserved.
*******************************************************************************/
/*******************************************************************************
* DESCRIPTION : Set vector table function
******************************************************************************/
/******************************************************************************
* @file vect_set.c
* - Version : 0.01
* @brief Set vector table function.
* .
*****************************************************************************/
/******************************************************************************
* History : DD.MM.YYYY Version Description
* : 06.01.2022 0.01 First Release
*****************************************************************************/
#include <stdint.h>
#include <v800_ghs.h>
#include "intc.h"
#include "vect_set.h"
#include "cpu.h"
#include "rst_register.h"
#include "mem_io.h"
void set_vect_table(void)
{
/* set interrupt table */
__LDSR(INTBP, (uint32_t)&__ghsbegin_EIINTTBL_ICU[0]);
}
/* End of function set_vect_table(void) */

181
Src/0_Tool/Gen4_R-Car_IPL/SDK/v3_46_0/Gen4_ICUMX_Loader/intc/vecttbl.S Normal file
View File

@@ -0,0 +1,181 @@
/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright 2022 Renesas Electronics Corporation All rights reserved.
*******************************************************************************/
/*******************************************************************************
* DESCRIPTION : Loader vector table
******************************************************************************/
.global code_start
.global intc_handler
.section ".reset"
.align 512
.align 16
_start:
jr32 code_start //RESET
.align 16
jr32 _Dummy //SYSERR
.align 16
jr32 _Dummy //HVTRAP
.align 16
jr32 _Dummy //FETRAP
.align 16
jr32 _Dummy //TRAP0
.align 16
jr32 _Dummy //TRAP1
.align 16
jr32 _Dummy //RIE
.align 16
jr32 _Dummy //FPP/FPI
.align 16
jr32 _Dummy //UCPOP
.align 16
jr32 _Dummy //MIP/MDP
.align 16
jr32 _Dummy //PIE
.align 16
jr32 _Dummy //Debug
.align 16
jr32 _Dummy //MAE
.align 16
jr32 _Dummy //(R.F.U)
.align 16
jr32 _Dummy //FENMI
.align 16
jr32 _Dummy //FEINT
.align 16
jr32 _Dummy //INTn(priority0)
.align 16
jr32 _Dummy //INTn(priority1)
.align 16
jr32 _Dummy //INTn(priority2)
.align 16
jr32 _Dummy //INTn(priority3)
.align 16
jr32 _Dummy //INTn(priority4)
.align 16
jr32 _Dummy //INTn(priority5)
.align 16
jr32 _Dummy //INTn(priority6)
.align 16
jr32 _Dummy //INTn(priority7)
.align 16
jr32 _Dummy //INTn(priority8)
.align 16
jr32 _Dummy //INTn(priority9)
.align 16
jr32 _Dummy //INTn(priority10)
.align 16
jr32 _Dummy //INTn(priority11)
.align 16
jr32 _Dummy //INTn(priority12)
.align 16
jr32 _Dummy //INTn(priority13)
.align 16
jr32 _Dummy //INTn(priority14)
.align 16
jr32 _Dummy //INTn(priority15)
.section ".EIINTTBL_ICU", const
.align 512
.offset 0x0000
.word _intc_handler /* 0 : INTICUECCLRAM */
.offset 0x0004
.word _intc_handler /* 1 : INTICUECCCRAM */
.offset 0x0008
.word _intc_handler /* 2 : INTICUEDCAXI */
.offset 0x000C
.word _intc_handler /* 3 : INTICUECCAXIAB */
.offset 0x0010
.word _intc_handler /* 4 : INTICUECCPKRAM */
.offset 0x0014
.word _intc_handler /* 5 : INTPES */
.offset 0x0018
.word _intc_handler /* 6 : INTPE */
.offset 0x001C
.word _intc_handler /* 7 : INTICUAESD0RD */
.offset 0x0020
.word _intc_handler /* 8 : Reserved */
.offset 0x0024
.word _intc_handler /* 9 : INTICUTRNGE0 */
.offset 0x0028
.word _intc_handler /* 10 : INTICUOSTM0 */
.offset 0x002C
.word _intc_handler /* 11 : INTICUOSTM1 */
.offset 0x0030
.word _intc_handler /* 12 : INTICUWDTA0 */
.offset 0x0034
.word _intc_handler /* 13 : INTICUPKCCA0 */
.offset 0x0038
.word _intc_handler /* 14 : INTICUDMACA0 */
.offset 0x003C
.word _intc_handler /* 15 : INTICUDMACA0AXI */
.offset 0x0040
.word _intc_handler /* 16 : Reserved */
.offset 0x0044
.word _intc_handler /* 17 : INTICUSHAA0IREQ */
.offset 0x0048
.word _intc_handler /* 18 : INTICUSHAA0OEND */
.offset 0x004C
.word _intc_handler /* 19 : INTICUCRCDRQA */
.offset 0x0050
.word _intc_handler /* 20 : INTICUCRRDRQA */
.offset 0x0054
.word _intc_handler /* 21 : INTICUCRCDRQ1 */
.offset 0x0058
.word _intc_handler /* 22 : INTICUCRRDRQ */
.offset 0x005C
.word _intc_handler /* 23 : INTICUCRCDRQ2 */
.offset 0x0060
.word _intc_handler /* 24 : Reserved */
.offset 0x0064
.word _intc_handler /* 25 : INTICUERRCFDA */
.offset 0x0068
.word _intc_handler /* 26 : INTICUERRDFDA */
.offset 0x006C
.word _intc_handler /* 27 : Reserved */
.offset 0x0070
.word _intc_handler /* 28 : Reserved */
.offset 0x0074
.word _intc_handler /* 29 : INTSAFRTRAMERR */
.offset 0x0078
.word _intc_handler /* 30 : INTSECRTRAMERR */
.offset 0x007C
.word _intc_handler /* 31 : INTEDCRTRAMERR */
.offset 0x0080
.word _intc_handler /* 32 : INTECCRTRAMCMPE */
.offset 0x0084
.word _intc_handler /* 33 : INTECCMRTRAMERR */
.offset 0x0088
.word _intc_handler /* 34 : INTECCSRTRAMERR */
.offset 0x008C
.word _intc_handler /* 35 : INTEDCMSECROMER */
.offset 0x0090
.word _intc_handler /* 36 : INTEDCSSECROMER */
.offset 0x0094
.word _intc_handler /* 37 : INTSCEGCALEND */
.section ".text"
.align 2
_Dummy:
br _Dummy

115
Src/0_Tool/Gen4_R-Car_IPL/SDK/v3_46_0/Gen4_ICUMX_Loader/ip/avs/avs.c Normal file
View File

@@ -0,0 +1,115 @@
/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright 2023 Renesas Electronics Corporation All rights reserved.
*******************************************************************************/
/*******************************************************************************
* DESCRIPTION : AVS driver
******************************************************************************/
/******************************************************************************
* @file avs.c
* - Version : 0.01
* @brief AVS driver.
* .
*****************************************************************************/
/******************************************************************************
* History : DD.MM.YYYY Version Description
* : 16.11.2023 0.01 First Release
*****************************************************************************/
#include <stdint.h>
#include <avs.h>
#include <i2c.h>
#include <log.h>
#include <mem_io.h>
#include <remap_register.h>
#define AVS_BASE (BASE_AVS_ADDR) /* Physical address:0xE60A0000, Logical address:0xFDAA0000 */
#define AVS_ADVADJP (AVS_BASE + 0x0080U)
#define ADVADJP_VOLCOND_MASK (0x000001FFU)
#define VOLCOND_NUM (5U) /* Array number */
#define VOLCOND_FLAG_4 (4U)
#define VOLCOND_FLAG_2 (2U)
/* I2C Slave Address */
#define SLAVE_RW_ADDR (0x000000C8U)
/* PMIC register Address */
#define BUCK1_DVS0CFG1 (0x00000072U)
#define BUCK1_DVS0CFG0 (0x00000073U)
#define DVS_CFG_NUM (2U) /* Array number */
/* PMIC register setting value */
#define BUCK1_DVS0CFG1_VOLCOND2 (0x0000009FU) /* Setting value for 0.7575[V] */
#define BUCK1_DVS0CFG0_VOLCOND2 (0x000000C0U) /* Setting value for 0.7575[V] */
#define BUCK1_DVS0CFG1_VOLCOND4 (0x0000009AU) /* Setting value for 0.7325[V] */
#define BUCK1_DVS0CFG0_VOLCOND4 (0x00000080U) /* Setting value for 0.7325[V] */
void avs_low_power_mode_setting(void)
{
uint32_t volcond;
/* Initialize I2C ch3. */
i2c3_init();
/* Confirm VOLCOND in ADVADJP register. */
volcond = mem_read32(AVS_ADVADJP);
volcond &= ADVADJP_VOLCOND_MASK;
NOTICE("Low Power Mode setting(AVS) VOLCOND=%d\n", volcond);
switch (volcond)
{
case VOLCOND_FLAG_2:
{
/* In case of VOLCOND=2, set supply voltage to 0.7575[V]. */
i2c3_write(SLAVE_RW_ADDR, BUCK1_DVS0CFG1, BUCK1_DVS0CFG1_VOLCOND2);
i2c3_write(SLAVE_RW_ADDR, BUCK1_DVS0CFG0, BUCK1_DVS0CFG0_VOLCOND2);
INFO("VOLCOND=0x%x SET Slave=0x%x Register=0x%x Value=0x%x\n",
volcond, SLAVE_RW_ADDR, BUCK1_DVS0CFG1, BUCK1_DVS0CFG1_VOLCOND2);
INFO("VOLCOND=0x%x SET Slave=0x%x Register=0x%x Value=0x%x\n",
volcond, SLAVE_RW_ADDR, BUCK1_DVS0CFG0, BUCK1_DVS0CFG0_VOLCOND2);
break;
}
case VOLCOND_FLAG_4:
{
/* In case of VOLCOND=4, set supply voltage to 0.7325[V]. */
i2c3_write(SLAVE_RW_ADDR, BUCK1_DVS0CFG1, BUCK1_DVS0CFG1_VOLCOND4);
i2c3_write(SLAVE_RW_ADDR, BUCK1_DVS0CFG0, BUCK1_DVS0CFG0_VOLCOND4);
INFO("VOLCOND=0x%x SET Slave=0x%x Register=0x%x Value=0x%x\n",
volcond, SLAVE_RW_ADDR, BUCK1_DVS0CFG1, BUCK1_DVS0CFG1_VOLCOND4);
INFO("VOLCOND=0x%x SET Slave=0x%x Register=0x%x Value=0x%x\n",
volcond, SLAVE_RW_ADDR, BUCK1_DVS0CFG0, BUCK1_DVS0CFG0_VOLCOND4);
break;
}
default:
{
/* Other than VOLCOND = 2 or 4, nothing to do. */
break;
}
}
/* Release I2C ch3 */
i2c3_release();
}
/* End of function avs_low_power_mode_setting(void) */

83
Src/0_Tool/Gen4_R-Car_IPL/SDK/v3_46_0/Gen4_ICUMX_Loader/ip/cpg/cpg.c Normal file
View File

@@ -0,0 +1,83 @@
/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright 2021-2024 Renesas Electronics Corporation All rights reserved.
*******************************************************************************/
/*******************************************************************************
* DESCRIPTION : CPG initialize
******************************************************************************/
/******************************************************************************
* @file cpg.c
* - Version : 0.03
* @brief Initial setting process of CPG.
* .
*****************************************************************************/
/******************************************************************************
* History : DD.MM.YYYY Version Description
* : 28.07.2021 0.01 First Release
* : 03.09.2021 0.02 Move cpg_reg_write function to cpg.h.
* : 27.12.2024 0.03 Add set_srcr function.
*****************************************************************************/
#include <cpg.h>
#include <cnf_tbl.h>
#if (RCAR_LSI == RCAR_V4H)
#include <cpg_register.h>
#endif /* RCAR_LSI == RCAR_V4H */
/* CPG write protect value */
#define CPGWPCR_PASSWORD (0xA5A50000U)
#define CPGWPCR_WPE ((uint32_t)1U << 0U)
#define CPGWPCR_WPE_VALID (0U)
#if (RCAR_LSI == RCAR_V4H)
static void set_srcr(void);
#endif /* RCAR_LSI == RCAR_V4H */
void cpg_init(void)
{
/* Release CPG write protect */
if((mem_read32(CPG_CPGWPCR) & CPGWPCR_WPE) != CPGWPCR_WPE_VALID)
{
mem_write32(CPG_CPGWPR, ~(uint32_t)(CPGWPCR_PASSWORD));
mem_write32(CPG_CPGWPCR, CPGWPCR_PASSWORD);
/* bit in WPE = 0? */
while ((mem_read32(CPG_CPGWPCR) & CPGWPCR_WPE) != CPGWPCR_WPE_VALID)
{
;
}
}
#if (RCAR_LSI == RCAR_V4H)
set_srcr();
#endif /* RCAR_LSI == RCAR_V4H */
}
/* End of function cpg_init(void) */
#if (RCAR_LSI == RCAR_V4H)
static void set_srcr(void)
{
mem_write32(CPG_SRCR28, CPGSRCR28_VAL);
mem_write32(CPG_SRCR29, CPGSRCR29_VAL);
}
/* End of function set_srcr(void) */
#endif /* RCAR_LSI == RCAR_V4H */

16
Src/0_Tool/Gen4_R-Car_IPL/SDK/v3_46_0/Gen4_ICUMX_Loader/ip/ddr/boot_init_dram.h Normal file
View File

@@ -0,0 +1,16 @@
/*
* Copyright (c) 2015-2019, Renesas Electronics Corporation All rights reserved.
*/
#ifndef __BOOT_INIT_DRAM_
#define __BOOT_INIT_DRAM_
extern int32_t InitDram(void);
#define INITDRAM_OK (0)
#define INITDRAM_NG (0xffffffff)
#define INITDRAM_ERR_I (0xffffffff)
#define INITDRAM_ERR_O (0xfffffffe)
#define INITDRAM_ERR_T (0xfffffff0)
#endif /* __BOOT_INIT_DRAM_*/

6
Src/0_Tool/Gen4_R-Car_IPL/SDK/v3_46_0/Gen4_ICUMX_Loader/ip/ddr/ddr.mk Normal file
View File

@@ -0,0 +1,6 @@
#
# Copyright (c) 2015-2022, Renesas Electronics Corporation All rights reserved.
#
OBJ_FILE += ip/ddr/s4/lpddr4x/boot_init_dram.o
OBJ_FILE += ip/ddr/dram_sub_func.o

17
Src/0_Tool/Gen4_R-Car_IPL/SDK/v3_46_0/Gen4_ICUMX_Loader/ip/ddr/dram_sub_func.c Normal file
View File

@@ -0,0 +1,17 @@
/*
* Copyright (c) 2015-2018, Renesas Electronics Corporation All rights reserved.
*/
#include <stdint.h>
#include "dram_sub_func.h"
void dram_get_boot_status(uint32_t *status)
{
*status = DRAM_BOOT_STATUS_COLD;
}
int32_t dram_update_boot_status(uint32_t status)
{
int32_t ret = 0;
return ret;
}

16
Src/0_Tool/Gen4_R-Car_IPL/SDK/v3_46_0/Gen4_ICUMX_Loader/ip/ddr/dram_sub_func.h Normal file
View File

@@ -0,0 +1,16 @@
/*
* Copyright (c) 2015-2019, Renesas Electronics Corporation All rights reserved.
*/
#ifndef DRAM_SUB_FUNC_H_
#define DRAM_SUB_FUNC_H_
#define DRAM_BOOT_STATUS_COLD (0U)
#define DRAM_BOOT_STATUS_WARM (1U)
#define DRAM_UPDATE_STATUS_ERR (-1)
void dram_get_boot_status(uint32_t *status);
int32_t dram_update_boot_status(uint32_t status);
#endif /* DRAM_SUB_FUNC_H_ */

2243
Src/0_Tool/Gen4_R-Car_IPL/SDK/v3_46_0/Gen4_ICUMX_Loader/ip/ddr/s4/lpddr4x/boot_init_dram.c Normal file
View File

File diff suppressed because it is too large Load Diff

254
Src/0_Tool/Gen4_R-Car_IPL/SDK/v3_46_0/Gen4_ICUMX_Loader/ip/ddr/s4/lpddr4x/boot_init_dram_config.c Normal file
View File

@@ -0,0 +1,254 @@
/*******************************************************************************
* Copyright (c) 2021-2022 Renesas Electronics Corporation. All rights reserved.
*
* RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY
*
* This software is provided as reference/sample code under the license
* agreement between Renesas Electronics Corporation and licensee (the
* "License Agreement") and shall be treated as specified in the License
* Agreement.
* These instructions, statements, and software are the confidential
* information of Renesas Electronics Corporation. They must be used and
* modified solely for the purpose for which it was furnished by Renesas
* Electronics Corporation. All or part of these instructions, statements and
* software must not be reproduced nor disclosed to any third party in any
* form, unless permitted by the License Agreement.
*
* THIS SOFTWARE IS PROVIDED BY RENESAS ELEOCTRONICS CORPORATION "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
* SATISFACTORY QUALITY, ACCURACY, TITLE AND NON-INFRINGEMENT ARE DISCLAIMED.
* IN NO EVENT SHALL RENESAS ELECTRONICS CORPORATION BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, PUNITIVE, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
* DAMAGE.
******************************************************************************/
/*******************************************************************************
* DRAM Param setting
******************************************************************************/
#define JS2_DERATE 0
#define DBSC_REFINT 1920 /* Average periodic refresh interval/Average Refresh Interval [ns] */
#define DBSC_REFINTS 0 /* 0: Average interval is REFINT. / 1: Average interval is 1/2 REFINT. */
#define REWT_TRAINING_INTERVAL 20000 /* Periodic-WriteDQ Training Interval [us] */
/*******************************************************************************
* NUMBER OF BOARD CONFIGRATION
* PLEASE DEFINE
******************************************************************************/
#define BOARDNUM 3 /* Add User platform BOARD */
/*******************************************************************************
* PLEASE SET board number or board judge function
******************************************************************************/
#define BOARD_JUDGE_AUTO
#ifdef BOARD_JUDGE_AUTO
static uint32_t _board_judge(void);
static uint32_t boardcnf_get_brd_type(void) {
return _board_judge();
}
#else /* BOARD_JUDGE_AUTO */
static uint32_t boardcnf_get_brd_type(void) {
return (0);
}
#endif /* BOARD_JUDGE_AUTO */
/*******************************************************************************
* BOARD CONFIGRATION
* PLEASE DEFINE boardcnfs[]
******************************************************************************/
struct _boardcnf_ch {
/*
0x00...0000B: 4Gb dual channel die / 2Gb single channel die
0x01...0001B: 6Gb dual channel die / 3Gb single channel die
0x02...0010B: 8Gb dual channel die / 4Gb single channel die
0x03...0011B: 12Gb dual channel die / 6Gb single channel die
0x04...0100B: 16Gb dual channel die / 8Gb single channel die
0xff...NO_MEMORY
*/
uint8_t ddr_density[CS_CNT];
/* SoC caX([5][4][3][2][1][0]) -> MEM caY: */
uint32_t ca_swap;
/* SoC dqsX([3][2][1][0]) -> MEM dqsY: */
uint16_t dqs_swap;
/* SoC dq([7][6][5][4][3][2][1][0]) -> MEM dqY/dm: (8 means DM) */
uint32_t dq_swap[SLICE_CNT];
/* SoC dm -> MEM dqY/dm: (8 means DM) */
uint8_t dm_swap[SLICE_CNT];
};
struct _boardcnf {
/* ch in use */
uint16_t phyvalid;
/* Read vref (SoC) training range : [15:8]stop / [7:0]start, 0x0000 = default val */
uint16_t vref_r;
/* Write vref (MR14) training range : [15:8]stop / [7:0]start, 0x0000 = default val */
uint16_t vref_w;
/* CA vref (MR12) training range : [15:8]stop / [7:0]start, 0x0000 = default val */
uint16_t vref_ca;
struct _boardcnf_ch ch[2];
};
static const struct _boardcnf boardcnfs[BOARDNUM] = {
/*
* boardcnf[0] RENESAS S4 Spider (16Gbit 2rank)
*/
{
0x03, /* phyvalid */
0x0000, /* vref_r */
0x0000, /* vref_w */
0x0000, /* vref_ca */
{
/* ch[0] */ { /* M0CAxB/M0DQ[23:16],M0DQ[31:24] */
/* ddr_density[] */ { 0x04, 0x04 },
/* ca_swap */ 0x243510U,
/* dqs_swap */ 0x10,
/* dq_swap[] */ { 0x21706345, 0x23510746 },
/* dm_swap[] */ { 0x08, 0x08 }
},
/* ch[1] */ { /* M0CAxA/M0DQ[15: 0] */
/* ddr_density[] */ { 0x04, 0x04 },
/* ca_swap */ 0x345210U,
/* dqs_swap */ 0x10,
/* dq_swap[] */ { 0x30124675, 0x53126047 },
/* dm_swap[] */ { 0x08, 0x08 }
}
}
},
/*
* boardcnf[1] RENESAS S4-N Spider (16Gbit 2rank)
*/
{
0x03, /* phyvalid */
0x0000, /* vref_r */
0x0000, /* vref_w */
0x0000, /* vref_ca */
{
/* ch[0] */ { /* M0CAxB/M0DQ[23:16],M0DQ[31:24] */
/* ddr_density[] */ { 0x04, 0x04 },
/* ca_swap */ 0x243510U,
/* dqs_swap */ 0x10,
/* dq_swap[] */ { 0x21705634, 0x23516048 },
/* dm_swap[] */ { 0x08, 0x07 }
},
/* ch[1] */ { /* M0CAxA/M0DQ[15: 0] */
/* ddr_density[] */ { 0x04, 0x04 },
/* ca_swap */ 0x345201U,
/* dqs_swap */ 0x10,
/* dq_swap[] */ { 0x03124675, 0x35126047 },
/* dm_swap[] */ { 0x08, 0x08 }
}
}
},
/*
* boardcnf[2] RENESAS S4(2ch)
*/
{
0x03, /* phyvalid */
0x0000, /* vref_r */
0x0000, /* vref_w */
0x0000, /* vref_ca */
{
/* ch[0] */ {
/* ddr_density[] */ { 0x04, 0x04 },
/* ca_swap */ 0x00543210U,
/* dqs_swap */ 0x10,
/* dq_swap[] */ { 0x76543210, 0x76543210 },
/* dm_swap[] */ { 0x08, 0x08 }
},
/* ch[1] */ {
/* ddr_density[] */ { 0x04, 0x04 },
/* ca_swap */ 0x00543210U,
/* dqs_swap */ 0x10,
/* dq_swap[] */ { 0x76543210, 0x76543210 },
/* dm_swap[] */ { 0x08, 0x08 }
}
}
}
};
/*******************************************************************************
* EXTAL CLOCK DEFINITION
* PLEASE DEFINE HOW TO JUDGE BORAD CLK
******************************************************************************/
/*
* RENESAS SPIDER BOARD EXAMPLE
* judge by md14/md13
*
* 16.00MHz CLK,DIV= 48,3 (md14,md13==0,0)
* 20.00MHz CLK,DIV= 60,3 (md14,md13==0,1)
* 40.00MHz CLK,DIV=120,3 (md14,md13==1,1)
*/
void boardcnf_get_brd_clk(uint32_t brd, uint32_t *clk, uint32_t *div) {
uint32_t md;
md = (mmio_read_32(RST_MODEMR0) >> 13) & 0x3;
switch(md) {
case 0x0 : *clk = 48; *div = 3; break; /* 48 / 3 = 16.00MHz */
case 0x1 : *clk = 60; *div = 3; break; /* 60 / 3 = 20.00MHz */
/* case 0x2 : *clk = 75; *div = 3; break; */ /* Not supported */
case 0x3 : *clk =120; *div = 3; break; /* 120 / 3 = 40.00MHz */
}
(void)brd;
}
/*******************************************************************************
* DDR MBPS TARGET
* PLEASE DEFINE HOW TO JUDGE DDR BPS
******************************************************************************/
/*
DDRxxxx (judge by md17) : Mbps
SSCG enable / disable for PLL1 (judge by md37/md36)
*/
void boardcnf_get_ddr_mbps(uint32_t brd, uint32_t *mbps, uint32_t *div) {
uint32_t md;
uint32_t sscg;
md = (mmio_read_32(RST_MODEMR0) >> 17) & 0x01U;
sscg = (mmio_read_32(RST_MODEMR1) >> 4) & 0x03U;
switch(sscg) {
case 0x0 :
switch(md) {
case 0x0 : *mbps = 3200; *div = 1; break;
case 0x1 : *mbps = 2120; *div = 1; break;
}
break;
case 0x1 :
switch(md) {
case 0x0 : *mbps = 3120; *div = 1; break;
case 0x1 : *mbps = 2120; *div = 1; break;
}
break;
case 0x2 :
switch(md) {
case 0x0 : *mbps = 3040; *div = 1; break;
case 0x1 : *mbps = 2120; *div = 1; break;
}
break;
case 0x3 :
switch(md) {
case 0x0 : *mbps = 3000; *div = 1; break;
case 0x1 : *mbps = 2120; *div = 1; break;
}
break;
}
(void)brd;
}
#ifdef BOARD_JUDGE_AUTO
/*******************************************************************************
* SAMPLE board detect function
******************************************************************************/
static uint32_t _board_judge(void) {
uint32_t brd;
brd = 0; /* spider (16Gbit 2rank)*/
return brd;
}
#endif

73
Src/0_Tool/Gen4_R-Car_IPL/SDK/v3_46_0/Gen4_ICUMX_Loader/ip/ddr/s4/lpddr4x/boot_init_dram_config.h Normal file
View File

@@ -0,0 +1,73 @@
/*******************************************************************************
* File Name : boot_init_dram_config.h
* Version : 1.0
* Description : This file containing structure definitions for board settings
******************************************************************************/
/*****************************************************************************
* History : Please refer the readme.txt
*
******************************************************************************/
/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* © 2020-2023 Renesas Electronics Corporation All rights reserved.
*******************************************************************************/
#ifndef BOOT_INIT_DRAM_CONFIG
#define BOOT_INIT_DRAM_CONFIG
#include <stdint.h>
#include "boot_init_dram_regdef.h"
/*******************************************************************************
* DRAM Param setting
* this parameter is depending on the user
******************************************************************************/
#define JS2_DERATE 0
#define BOARDNUM 5
#define USE_BOARD 0
/*******************************************************************************
* BOARD CONFIGRATION
* PLEASE DEFINE boardcnfs[]
******************************************************************************/
struct board_cfg_t
{
uint32_t phyvalid;
uint32_t vref_r;
uint32_t vref_w;
uint32_t vref_ca;
uint32_t ddr_density[CH_CNT][CS_CNT];
uint32_t ca_swap[CH_CNT];
uint32_t dqs_swap[CH_CNT];
uint32_t dq_swap[CH_CNT][SLICE_CNT];
uint32_t dm_swap[CH_CNT][SLICE_CNT];
};
void judge_board_clk_freq(uint32_t* board_clk, uint32_t* board_clkdiv, uint32_t* board_clkdiva);
void judge_ddr_ope_freq(uint32_t* ddr_mbps, uint32_t* ddr_mbpsdiv);
void judge_bus_clk_freq(uint32_t* bus_mbps, uint32_t* bus_mbpsdiv, const uint32_t* board_clk, const uint32_t* board_clkdiv);
extern const struct board_cfg_t board_cfg[BOARDNUM];
#endif /* BOOT_INIT_DRAM_CONFIG */

260
Src/0_Tool/Gen4_R-Car_IPL/SDK/v3_46_0/Gen4_ICUMX_Loader/ip/ddr/s4/lpddr4x/boot_init_dram_regdef.h Normal file
View File

@@ -0,0 +1,260 @@
/*******************************************************************************
* Copyright (c) 2021-2022 Renesas Electronics Corporation. All rights reserved.
*
* RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY
*
* This software is provided as reference/sample code under the license
* agreement between Renesas Electronics Corporation and licensee (the
* "License Agreement") and shall be treated as specified in the License
* Agreement.
* These instructions, statements, and software are the confidential
* information of Renesas Electronics Corporation. They must be used and
* modified solely for the purpose for which it was furnished by Renesas
* Electronics Corporation. All or part of these instructions, statements and
* software must not be reproduced nor disclosed to any third party in any
* form, unless permitted by the License Agreement.
*
* THIS SOFTWARE IS PROVIDED BY RENESAS ELEOCTRONICS CORPORATION "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
* SATISFACTORY QUALITY, ACCURACY, TITLE AND NON-INFRINGEMENT ARE DISCLAIMED.
* IN NO EVENT SHALL RENESAS ELECTRONICS CORPORATION BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, PUNITIVE, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
* DAMAGE.
******************************************************************************/
#if defined(__RH850G3K__)
#include "remap_register.h"
#endif
#define RCAR_DDR_VERSION "rev.0.30rc7"
#define DRAM_CH_CNT 0x02
#define SLICE_CNT 0x02
#define CS_CNT 0x02
/* for pll setting */
#define CLK_DIV(a, diva, b, divb) (((a) * (divb)) / ((b) * (diva)))
#define CLK_MUL(a, diva, b, divb) (((a) * (b)) / ((diva) * (divb)))
/* for ddr density setting */
#define DBMEMCONF_REG(d3, row, bank, col, dw) (((d3) << 30) | ((row) << 24) | ((bank) << 16) | ((col) << 8) | (dw))
#define DBMEMCONF_REGD(density) (DBMEMCONF_REG((density) % 2, ((density) + 1) / 2 + (28 - 3 - 10 - 1), 3, 10, 1)) /* 16bit */
#define DBMEMCONF_VAL(ch,cs) (DBMEMCONF_REGD(DBMEMCONF_DENS(ch, cs)))
/* system registers : CPG */
#define CPG_FRQCRD_KICK_BIT (1U << 31)
#define CPG_PLL3CR_KICK_BIT (1U << 31)
#define CPG_PLLECR_PLL3E_BIT (1U << 3)
#define CPG_PLLECR_PLL3ST_BIT (1U << 11)
#if defined(__RH850G3K__)
#define CPG_BASE (BASE_CPG_ADDR)
#else
#define CPG_BASE (0xE6150000U)
#endif
#define CPG_CPGWPR (CPG_BASE + 0x0000U)
#define CPG_CPGWPCR (CPG_BASE + 0x0004U)
#define CPG_FRQCRA (CPG_BASE + 0x0800U)
#define CPG_FRQCRB (CPG_BASE + 0x0804U)
#define CPG_FRQCRC (CPG_BASE + 0x0808U)
#define CPG_FRQCRD (CPG_BASE + 0x080CU)
#define CPG_PLLECR (CPG_BASE + 0x0820U)
#define CPG_PLL3CR0 (CPG_BASE + 0x083CU)
#define CPG_PLL3CR1 (CPG_BASE + 0x08C0U)
#define CPG_Z0CKKSCR (CPG_BASE + 0x08A8U)
#define CPG_Z1CKKSCR (CPG_BASE + 0x08ACU)
#define CPG_SRST4 (CPG_BASE + 0x2C10U)
#define CPG_SRSTCLR4 (CPG_BASE + 0x2C90U)
#define CPG_FSRCHKRA4 (CPG_BASE + 0x0410U)
#define CPG_FSRCHKSETR4 (CPG_BASE + 0x0510U)
#define CPG_FSRCHKCLRR4 (CPG_BASE + 0x0590U)
#if defined(__RH850G3K__)
#define RST_BASE (BASE_RESET_ADDR)
#else
#define RST_BASE (0xE6160000U)
#endif
#define RST_MODEMR0 (RST_BASE + 0x0000U)
#define RST_MODEMR1 (RST_BASE + 0x0004U)
/* Product Register */
#define PRR (0xFFF00044U)
#define PRR_PRODUCT_MASK (0x00007F00U)
#define PRR_CUT_MASK (0x000000FFU)
#define PRR_PRODUCT_S4 (0x00005A00U) /* R-Car S4 */
#define PRR_PRODUCT_10 (0x00000000U) /* ver 1.0 */
#define PRR_PRODUCT_11 (0x00000001U) /* ver 1.1 */
#define PRR_PRODUCT_12 (0x00000002U) /* ver 1.2 */
/* DBSC registers */
#if defined(__RH850G3K__)
#define DBSC_BASE (BASE_DBSC_ADDR)
#else
#define DBSC_BASE (0xE6790000U)
#endif
#define DBSC_DBSYSCONF0 (DBSC_BASE + 0x0000U)
#define DBSC_DBSYSCONF1 (DBSC_BASE + 0x0004U)
#define DBSC_DBSYSCONF1A (DBSC_BASE + 0x0008U)
#define DBSC_DBSYSCONF2 (DBSC_BASE + 0x000CU)
#define DBSC_DBPHYCONF0 (DBSC_BASE + 0x0010U)
#define DBSC_DBSYSCONF2A (DBSC_BASE + 0x0014U)
#define DBSC_DBKIND (DBSC_BASE + 0x0020U)
#define DBSC_DBKINDA (DBSC_BASE + 0x0024U)
#define DBSC_DBMEMCONF(ch, cs) (DBSC_BASE + 0x0030U + 0x2000U * (ch & 0x04U) + 0x10U * (ch & 0x03U) + 0x04U * cs)
#define DBSC_DBMEMCONF_0_0 (DBSC_BASE + 0x0030U)
#define DBSC_DBMEMCONF_0_1 (DBSC_BASE + 0x0034U)
#define DBSC_DBMEMCONF_0_2 (DBSC_BASE + 0x0038U)
#define DBSC_DBMEMCONF_0_3 (DBSC_BASE + 0x003CU)
#define DBSC_DBMEMCONF_1_0 (DBSC_BASE + 0x0040U)
#define DBSC_DBMEMCONF_1_1 (DBSC_BASE + 0x0044U)
#define DBSC_DBMEMCONF_1_2 (DBSC_BASE + 0x0048U)
#define DBSC_DBMEMCONF_1_3 (DBSC_BASE + 0x004CU)
#define DBSC_DBMEMCONF_2_0 (DBSC_BASE + 0x0050U)
#define DBSC_DBMEMCONF_2_1 (DBSC_BASE + 0x0054U)
#define DBSC_DBMEMCONF_2_2 (DBSC_BASE + 0x0058U)
#define DBSC_DBMEMCONF_2_3 (DBSC_BASE + 0x005CU)
#define DBSC_DBMEMCONF_3_0 (DBSC_BASE + 0x0060U)
#define DBSC_DBMEMCONF_3_1 (DBSC_BASE + 0x0064U)
#define DBSC_DBMEMCONF_3_2 (DBSC_BASE + 0x0068U)
#define DBSC_DBMEMCONF_3_3 (DBSC_BASE + 0x006CU)
#define DBSC_DBMEMCONFA(ch, cs) (DBSC_BASE + 0x0070U + 0x2000U * (ch & 0x04U) + 0x10U * (ch & 0x03U) + 0x04U * cs)
#define DBSC_DBMEMCONF_0_0A (DBSC_BASE + 0x0070U)
#define DBSC_DBMEMCONF_0_1A (DBSC_BASE + 0x0074U)
#define DBSC_DBMEMCONF_0_2A (DBSC_BASE + 0x0078U)
#define DBSC_DBMEMCONF_0_3A (DBSC_BASE + 0x007CU)
#define DBSC_DBMEMCONF_1_0A (DBSC_BASE + 0x0080U)
#define DBSC_DBMEMCONF_1_1A (DBSC_BASE + 0x0084U)
#define DBSC_DBMEMCONF_1_2A (DBSC_BASE + 0x0088U)
#define DBSC_DBMEMCONF_1_3A (DBSC_BASE + 0x008CU)
#define DBSC_DBMEMCONF_2_0A (DBSC_BASE + 0x0090U)
#define DBSC_DBMEMCONF_2_1A (DBSC_BASE + 0x0094U)
#define DBSC_DBMEMCONF_2_2A (DBSC_BASE + 0x0098U)
#define DBSC_DBMEMCONF_2_3A (DBSC_BASE + 0x009CU)
#define DBSC_DBMEMCONF_3_0A (DBSC_BASE + 0x00A0U)
#define DBSC_DBMEMCONF_3_1A (DBSC_BASE + 0x00A4U)
#define DBSC_DBMEMCONF_3_2A (DBSC_BASE + 0x00A8U)
#define DBSC_DBMEMCONF_3_3A (DBSC_BASE + 0x00ACU)
#define DBSC_DBSYSCNT0 (DBSC_BASE + 0x0100U)
#define DBSC_DBSYSCNT0A (DBSC_BASE + 0x0108U)
#define DBSC_DBACEN (DBSC_BASE + 0x0200U)
#define DBSC_DBRFEN (DBSC_BASE + 0x0204U)
#define DBSC_DBCMD (DBSC_BASE + 0x0208U)
#define DBSC_DBWAIT (DBSC_BASE + 0x0210U)
#define DBSC_DBTR(x) (DBSC_BASE + 0x0300U + 0x04U * (x))
#define DBSC_DBTR0 (DBSC_BASE + 0x0300U)
#define DBSC_DBTR1 (DBSC_BASE + 0x0304U)
#define DBSC_DBTR3 (DBSC_BASE + 0x030CU)
#define DBSC_DBTR4 (DBSC_BASE + 0x0310U)
#define DBSC_DBTR5 (DBSC_BASE + 0x0314U)
#define DBSC_DBTR6 (DBSC_BASE + 0x0318U)
#define DBSC_DBTR7 (DBSC_BASE + 0x031CU)
#define DBSC_DBTR8 (DBSC_BASE + 0x0320U)
#define DBSC_DBTR9 (DBSC_BASE + 0x0324U)
#define DBSC_DBTR10 (DBSC_BASE + 0x0328U)
#define DBSC_DBTR11 (DBSC_BASE + 0x032CU)
#define DBSC_DBTR12 (DBSC_BASE + 0x0330U)
#define DBSC_DBTR13 (DBSC_BASE + 0x0334U)
#define DBSC_DBTR14 (DBSC_BASE + 0x0338U)
#define DBSC_DBTR15 (DBSC_BASE + 0x033CU)
#define DBSC_DBTR16 (DBSC_BASE + 0x0340U)
#define DBSC_DBTR17 (DBSC_BASE + 0x0344U)
#define DBSC_DBTR18 (DBSC_BASE + 0x0348U)
#define DBSC_DBTR19 (DBSC_BASE + 0x034CU)
#define DBSC_DBTR20 (DBSC_BASE + 0x0350U)
#define DBSC_DBTR21 (DBSC_BASE + 0x0354U)
#define DBSC_DBTR22 (DBSC_BASE + 0x0358U)
#define DBSC_DBTR23 (DBSC_BASE + 0x035CU)
#define DBSC_DBTR24 (DBSC_BASE + 0x0360U)
#define DBSC_DBTR25 (DBSC_BASE + 0x0364U)
#define DBSC_DBTR26 (DBSC_BASE + 0x0368U)
#define DBSC_DBBL (DBSC_BASE + 0x0400U)
#define DBSC_DBBLA (DBSC_BASE + 0x0404U)
#define DBSC_DBRFCNF1 (DBSC_BASE + 0x0414U)
#define DBSC_DBRFCNF2 (DBSC_BASE + 0x0418U)
#define DBSC_DBCALCNF (DBSC_BASE + 0x0424U)
#define DBSC_DBRNK(x) (DBSC_BASE + 0x0430U + 0x04U * (x))
#define DBSC_DBRNK2 (DBSC_BASE + 0x0438U)
#define DBSC_DBRNK3 (DBSC_BASE + 0x043CU)
#define DBSC_DBRNK4 (DBSC_BASE + 0x0440U)
#define DBSC_DBRNK5 (DBSC_BASE + 0x0444U)
#define DBSC_DBDBICNT (DBSC_BASE + 0x0518U)
#define DBSC_DBDFIPMSTRCNF (DBSC_BASE + 0x0520U)
#define DBSC_DBDFICUPDCNF (DBSC_BASE + 0x052CU)
#define DBSC_DBDFISTAT(ch) (DBSC_BASE + 0x0600U + 0x2000U * (ch & 0x04U) + 0x40U * (ch & 0x03U))
#define DBSC_DBDFISTAT_0 (DBSC_BASE + 0x0600U)
#define DBSC_DBDFISTAT_1 (DBSC_BASE + 0x0640U)
#define DBSC_DBDFISTAT_2 (DBSC_BASE + 0x0680U)
#define DBSC_DBDFISTAT_3 (DBSC_BASE + 0x06C0U)
#define DBSC_DBDFICNT(ch) (DBSC_BASE + 0x0604U + 0x2000U * (ch & 0x04U) + 0x40U * (ch & 0x03U))
#define DBSC_DBDFICNT_0 (DBSC_BASE + 0x0604U)
#define DBSC_DBDFICNT_1 (DBSC_BASE + 0x0644U)
#define DBSC_DBDFICNT_2 (DBSC_BASE + 0x0684U)
#define DBSC_DBDFICNT_3 (DBSC_BASE + 0x06C4U)
#define DBSC_DBPDCNT2(ch) (DBSC_BASE + 0x0618U + 0x2000U * (ch & 0x04U) + 0x40U * (ch & 0x03U))
#define DBSC_DBPDCNT2_0 (DBSC_BASE + 0x0618U)
#define DBSC_DBPDCNT2_1 (DBSC_BASE + 0x0658U)
#define DBSC_DBPDCNT2_2 (DBSC_BASE + 0x0698U)
#define DBSC_DBPDCNT2_3 (DBSC_BASE + 0x06D8U)
#define DBSC_DBPDCNT3(ch) (DBSC_BASE + 0x061CU + 0x2000U * (ch & 0x04U) + 0x40U * (ch & 0x03U))
#define DBSC_DBPDCNT3_0 (DBSC_BASE + 0x061CU)
#define DBSC_DBPDCNT3_1 (DBSC_BASE + 0x065CU)
#define DBSC_DBPDCNT3_2 (DBSC_BASE + 0x069CU)
#define DBSC_DBPDCNT3_3 (DBSC_BASE + 0x06DCU)
#define DBSC_DBPDLK(ch) (DBSC_BASE + 0x0620U + 0x2000U * (ch & 0x04U) + 0x40U * (ch & 0x03U))
#define DBSC_DBPDLK_0 (DBSC_BASE + 0x0620U)
#define DBSC_DBPDLK_1 (DBSC_BASE + 0x0660U)
#define DBSC_DBPDLK_2 (DBSC_BASE + 0x06a0U)
#define DBSC_DBPDLK_3 (DBSC_BASE + 0x06e0U)
#define DBSC_DBPDRGA(ch) (DBSC_BASE + 0x0624U + 0x2000U * (ch & 0x04U) + 0x40U * (ch & 0x03U))
#define DBSC_DBPDRGA_0 (DBSC_BASE + 0x0624U)
#define DBSC_DBPDRGA_1 (DBSC_BASE + 0x0664U)
#define DBSC_DBPDRGA_2 (DBSC_BASE + 0x06A4U)
#define DBSC_DBPDRGA_3 (DBSC_BASE + 0x06E4U)
#define DBSC_DBPDRGD(ch) (DBSC_BASE + 0x0628U + 0x2000U * (ch & 0x04U) + 0x40U * (ch & 0x03U))
#define DBSC_DBPDRGD_0 (DBSC_BASE + 0x0628U)
#define DBSC_DBPDRGD_1 (DBSC_BASE + 0x0668U)
#define DBSC_DBPDRGD_2 (DBSC_BASE + 0x06A8U)
#define DBSC_DBPDRGD_3 (DBSC_BASE + 0x06E8U)
#define DBSC_DBPDSTAT(ch) (DBSC_BASE + 0x0630U + 0x2000U * (ch & 0x04U) + 0x40U * (ch & 0x03U))
#define DBSC_DBPDSTAT_0 (DBSC_BASE + 0x0630U)
#define DBSC_DBPDSTAT_1 (DBSC_BASE + 0x0670U)
#define DBSC_DBPDSTAT_2 (DBSC_BASE + 0x06B0U)
#define DBSC_DBPDSTAT_3 (DBSC_BASE + 0x06F0U)
#define DBSC_DBPDSTAT1(ch) (DBSC_BASE + 0x0634U + 0x2000U * (ch & 0x04U) + 0x40U * (ch & 0x03U))
#define DBSC_DBBUS0CNF0 (DBSC_BASE + 0x0800U)
#define DBSC_DBBUS0CNF1 (DBSC_BASE + 0x0804U)
#define DBSC_DBBCAMDIS (DBSC_BASE + 0x09FCU)
#define DBSC_DBSCHRW1 (DBSC_BASE + 0x1024U)
#define DBSC_SCFCTST0 (DBSC_BASE + 0x1700U)
#define DBSC_SCFCTST1 (DBSC_BASE + 0x1708U)

1320
Src/0_Tool/Gen4_R-Car_IPL/SDK/v3_46_0/Gen4_ICUMX_Loader/ip/ddr/s4/lpddr4x/ddr_regdef.h Normal file
View File

File diff suppressed because it is too large Load Diff

354
Src/0_Tool/Gen4_R-Car_IPL/SDK/v3_46_0/Gen4_ICUMX_Loader/ip/ddr/s4/lpddr4x/ecc_enable_s4.c Normal file
View File

@@ -0,0 +1,354 @@
/*******************************************************************************
* Copyright (c) 2022-2023 Renesas Electronics Corporation. All rights reserved.
*
* RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY
*
* This software is provided as reference/sample code under the license
* agreement between Renesas Electronics Corporation and licensee (the
* "License Agreement") and shall be treated as specified in the License
* Agreement.
* These instructions, statements, and software are the confidential
* information of Renesas Electronics Corporation. They must be used and
* modified solely for the purpose for which it was furnished by Renesas
* Electronics Corporation. All or part of these instructions, statements and
* software must not be reproduced nor disclosed to any third party in any
* form, unless permitted by the License Agreement.
*
* THIS SOFTWARE IS PROVIDED BY RENESAS ELEOCTRONICS CORPORATION "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
* SATISFACTORY QUALITY, ACCURACY, TITLE AND NON-INFRINGEMENT ARE DISCLAIMED.
* IN NO EVENT SHALL RENESAS ELECTRONICS CORPORATION BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, PUNITIVE, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
* DAMAGE.
******************************************************************************/
/*******************************************************************************
* DESCRIPTION : ECC setting function
******************************************************************************/
/******************************************************************************
* @file ecc_enable_s4.c
* - Version : 0.02
* @brief Enable setting process of ECC for DRAM.
* .
*****************************************************************************/
/******************************************************************************
* History : DD.MM.YYYY Version Description
* : 09.08.2022 0.01 First Release
* : 04.04.2023 0.02 Removed stdio.h and string.h.
*****************************************************************************/
#include <stdint.h>
static void ecm_unlock(void);
static void ecm_write(uint32_t adr, uint32_t val);
static void ecm_lock(void);
#include "boot_init_dram_regdef.h"
#include "ecc_enable_s4.h"
static void ecm_unlock(void)
{
uint32_t tmp_adr;
tmp_adr = ((0xACCEU << 16U) | (ECMWPCNTR & 0xffffU));
mem_write32(ECMWACNTR, tmp_adr);
mem_write32(ECMWPCNTR, 0xACCE0001);
}
static void ecm_write(uint32_t adr, uint32_t val)
{
mem_write32(ECMWACNTR, ((0xACCEU << 16U) | (adr & 0xffffU)));
mem_write32(adr, val);
}
static void ecm_lock(void)
{
mem_write32(ECMWACNTR, ((0xACCEU << 16U) | (ECMWACNTR & 0xffffU)));
mem_write32(ECMWPCNTR, 0xACCE0000U);
}
void enable_ecc(void)
{
NOTICE("ECC for DRAM is enable.\n");
uint32_t ecm_tmp;
/* Unlock the access protect for DBSC registers */
mem_write32(DBSC_DBSYSCNT0, 0x00001234U);
mem_write32(DBSC_DBSYSCNT0A, 0x00001234U);
/* (A) Initialization for DRAM */
mmio_write_32(DBSC_DBACEN, 0x00000000U);
/* Unlock the write protect of ECM registers */
ecm_unlock();
/* (1) Set the corresponding bits of the ECMERRTGTR, ECMERRCTLR and ECMERRFATALR registers to inform
the control domain of the fatal error. */
ecm_tmp = mem_read32(ECMERRTGTR0);
ecm_tmp &= ~(0x3U);
ecm_write(ECMERRTGTR0, ecm_tmp);
ecm_tmp = mem_read32(ECMERRCTLR0);
ecm_tmp |= 0x3U;
ecm_write(ECMERRCTLR0, ecm_tmp);
ecm_tmp = mem_read32(ECMERRFATALR0);
ecm_tmp |= 0x3U;
ecm_write(ECMERRFATALR0, ecm_tmp);
/* (B) Setting ECC protection area */
/* Set the bottom row address of the ECC protection area */
mem_write32(DBFSDRAMECCAREA00, ECC_PROT_SIZE0);
mem_write32(DBFSDRAMECCAREA01, ECC_PROT_SIZE1);
/* (2) Initialization for DRAM connected to DBSCCORE */
/* Specify RANK0 as the initialization target */
ecm_tmp = mem_read32(DBFSCONF00A);
ecm_tmp = 0x0U;
mem_write32(DBFSCONF00A, ecm_tmp);
/* Set the start and end row address of the initialization area */
mem_write32(DBFSCONF01A, START_ECC_INIT_AREA0);
mem_write32(DBFSCONF05A, END_ECC_INIT_AREA0);
/* Set 0x1 to start initialization */
ecm_tmp = mem_read32(DBFSCTRL01A);
ecm_tmp |= 0x01U;
mem_write32(DBFSCTRL01A, ecm_tmp);
/* Wait until to DRAM initialization is complete */
NOTICE("DRAM rank 0 is initializing.......\n");
do
{
ecm_tmp = mem_read32(DBFSSTAT01A);
} while ((ecm_tmp & 0x01U) != 0x01U);
/* If DRAM is connected to RANK1, Initialize RANK1 */
/* Specify RANK0 as the initialization target */
ecm_tmp = mem_read32(DBFSCONF00A);
ecm_tmp |= 0x1U;
mem_write32(DBFSCONF00A, ecm_tmp);
/* Set the start and end row address of the initialization area */
mem_write32(DBFSCONF01A, START_ECC_INIT_AREA1);
mem_write32(DBFSCONF05A, END_ECC_INIT_AREA1);
/* Set 0x1 to start initialization */
ecm_tmp = mem_read32(DBFSCTRL01A);
ecm_tmp |= 0x01U;
mem_write32(DBFSCTRL01A, ecm_tmp);
/* Wait until to DRAM initialization is complete */
NOTICE("DRAM rank 1 is initializing.......\n");
do
{
ecm_tmp = mem_read32(DBFSSTAT01A);
} while ((ecm_tmp & 0x01U) != 0x01U);
/* (C) Setting ECC protection enable */
ecm_tmp = mem_read32(DBFSCONFAXI0);
ecm_tmp |= (0x3 << 8U);
mem_write32(DBFSCONFAXI0, ecm_tmp);
/* (D) System RAM initialization */
/* Wait for initialization of System RAM */
NOTICE("System RAM is initializing.......\n");
do
{
;
} while ((mem_read32(DBFSSTAT00A) & 0x1U) != 0x1U);
/* (E) Setting for ECC error interrupt */
/* (1) Set the ECC error interrupt for read data. */
mem_write32(DBFSINTENB02A, 0xFF00U);
/* (2) Set the ECC error interrupt during RMW operation for System RAM. */
ecm_tmp = mem_read32(DBFSINTENB02A);
ecm_tmp |= (0xFFU << 24U);
mem_write32(DBFSINTENB02A, ecm_tmp);
/* (3) Set the ECC error interrupt during RMW operation for DRAM. */
mem_write32(DBFSINTENB04A, 0xFFFFU);
/* Lock the ECM registers */
ecm_lock();
/* Enable the write protect of ECM registers */
mmio_write_32(DBSC_DBACEN, 0x00000001U);
/* Enable the access protect for DBSC registers */
mem_write32(DBSC_DBSYSCNT0, 0x00000000U);
mem_write32(DBSC_DBSYSCNT0A, 0x00000000U);
}
void ecc_rtsram_enable(void)
{
uint32_t ecc_tmp;
/* Unlock the write protect of ECM registers */
ecm_unlock();
/* (1) Set the corresponding bits of the ECMERRTGTR, ECMERRCTLR and
ECMERRFATALR registers to inform the control domain of the fatal error. */
/* Set bit 29 of ECMERRTGTR7 to 0 and bit 29 of ECMERRCTLR7 to 1.
(RT-SRAM ecc 2-bit error) */
ecc_tmp = mem_read32(ECMERRTGTR7);
ecc_tmp |= (1U << 29U) ;
ecm_write(ECMERRTGTR7, ecc_tmp);
ecc_tmp = mem_read32(ECMERRCTLR7);
ecc_tmp |= (1U << 29U);
ecm_write(ECMERRCTLR7, ecc_tmp);
/* Set bit 19 of ECMERRTGTR7 to 0 and bit 19 of ECMERRCTLR7 to 1.
(RT-SRAM ecc 2-bit error (for ICUMX)) */
ecc_tmp = mem_read32(ECMERRTGTR7);
ecc_tmp |= (1U << 19U);
ecm_write(ECMERRTGTR7, ecc_tmp);
ecc_tmp = mem_read32(ECMERRCTLR7);
ecc_tmp |= (1U << 19U);
ecm_write(ECMERRCTLR7, ecc_tmp);
/* Set bit 29 and 19 of ECMERRFATALR7 to 1. (Notification of fatal error) */
ecc_tmp = mem_read32(ECMERRFATALR7);
ecc_tmp |= ((1U << 29U) | (1U << 19U));
ecm_write(ECMERRFATALR7, ecc_tmp);
/* (2) Set the corresponding bits of the ECMERRTGTR and ECMERRCTLR registers to
notify the correctable error to software. */
/* Set bit 30 of ECMERRTGTR7 to 1 and bit 30 of ECMERRCTLR7 to 1.
(RT-SRAM ecc 1-bit error) */
ecc_tmp = mem_read32(ECMERRTGTR7);
ecc_tmp |= (1U << 30U);
ecm_write(ECMERRTGTR7, ecc_tmp);
ecc_tmp = mem_read32(ECMERRCTLR7);
ecc_tmp |= (1U << 30U);
ecm_write(ECMERRCTLR7, ecc_tmp);
/* Set bit 20 of ECMERRTGTR7 to 1 and bit 20 of ECMERRCTLR7 to 1.
(RT-SRAM ecc 1-bit error (for ICUMX)) */
ecc_tmp = mem_read32(ECMERRTGTR7);
ecc_tmp |= (1U << 20U);
ecm_write(ECMERRTGTR7, ecc_tmp);
ecc_tmp = mem_read32(ECMERRCTLR7);
ecc_tmp |= (1U << 20U);
ecm_write(ECMERRCTLR7, ecc_tmp);
/* Lock the ECM registers */
ecm_lock();
}
void edc_axi_enable(void)
{
uint32_t edc_tmp;
/* Unlock the write protect of ECM registers */
ecm_unlock();
/* (1) Set the corresponding bits of the ECMERRTGTR, ECMERRCTLR
and ECMERRFATALR registers to inform the control domain of the fatal error. */
/* Set bit 10 - bit 6 of ECMERRTGTR7 to all 0 and bit 10 - bit 6 of
ECMERRCTLR7 to 1. (Error of AXI-Bus ECM of each hierarchy) */
edc_tmp = mem_read32(ECMERRTGTR7);
edc_tmp &= ~(0x1fU << 6U);
ecm_write(ECMERRTGTR7, edc_tmp);
edc_tmp = mem_read32(ECMERRCTLR7);
edc_tmp |= (0x1fU << 6U);
ecm_write(ECMERRCTLR7, edc_tmp);
/* Set bit 23 - bit 16 of ECMERRTGTR39 to all 0 and bit 23 - bit 16 of
ECMERRCTLR39 to 1. (Error of AXI-Bus ECM of each hierarchy) */
edc_tmp = mem_read32(ECMERRTGTR39);
edc_tmp &= ~(0xffU << 16U);
ecm_write(ECMERRTGTR39, edc_tmp);
edc_tmp = mem_read32(ECMERRCTLR39);
edc_tmp |= (0xffU << 6U);
ecm_write(ECMERRCTLR39, edc_tmp);
/* Set bit 26 of ECMERRTGTR1 to 0 and bit 26 of
ECMERRCTLR1 to 1. (CCI bus EDC error) */
edc_tmp = mem_read32(ECMERRTGTR1);
edc_tmp &= ~(0x1U << 26U);
ecm_write(ECMERRTGTR1, edc_tmp);
edc_tmp = mem_read32(ECMERRCTLR1);
edc_tmp |= (0x1U << 26U);
ecm_write(ECMERRCTLR1, edc_tmp);
/* Set bit 10 - bit 6 of ECMERRFATALR7 to 1.
(Notification of fatal error) */
edc_tmp = mem_read32(ECMERRFATALR7);
edc_tmp |= (0x1fU << 6U);
ecm_write(ECMERRFATALR7, edc_tmp);
/* Set bit 23 - bit 16 of ECMERRFATALR39 to 1.
(Notification of fatal error) */
edc_tmp = mem_read32(ECMERRFATALR39);
edc_tmp |= (0xffU << 16U);
ecm_write(ECMERRFATALR39, edc_tmp);
/* Set bit 26 of ECMERRFATALR1 to 1.
(Notification of fatal error) */
edc_tmp = mem_read32(ECMERRFATALR1);
edc_tmp |= (0x1U << 26U);
ecm_write(ECMERRFATALR1, edc_tmp);
/* Lock the ECM registers */
ecm_lock();
}
void edc_vram_enable(void)
{
uint32_t edc_tmp;
/* Unlock the write protect of ECM registers */
ecm_unlock();
/* (1) Set the corresponding bits of the ECMERRTGTR, ECMERRCTLR and
ECMERRFATALR registers to inform the control domain of the fatal error. */
/* Set bit 19 of ECMERRTGTR17 to 0 and bit 19 of ECMERRCTLR17 to 1.
(RT-VRAM edc 1-bit error) */
edc_tmp = mem_read32(ECMERRTGTR17);
edc_tmp &= ~(0x1U << 19U);
ecm_write(ECMERRTGTR17, edc_tmp);
edc_tmp = mem_read32(ECMERRCTLR17);
edc_tmp |= (0x1U << 19U);
ecm_write(ECMERRCTLR17, edc_tmp);
/* Set bit 18 of ECMERRTGTR17 to 0 and bit 18 of ECMERRCTLR17 to 1.
(RT-VRAM edc multi-bit error) */
edc_tmp = mem_read32(ECMERRTGTR17);
edc_tmp &= ~(0x1U << 18U);
ecm_write(ECMERRTGTR17, edc_tmp);
edc_tmp = mem_read32(ECMERRCTLR17);
edc_tmp |= (0x1U << 18U);
ecm_write(ECMERRCTLR17, edc_tmp);
/* Set bit 19, 18 of ECMERRFATALR17 to 1. (Notification of fatal error) */
edc_tmp = mem_read32(ECMERRFATALR17);
edc_tmp |= (0x3U << 18U);
ecm_write(ECMERRFATALR17, edc_tmp);
/* Set bit 0 of EDC_CFG to 1. (EDC Error Control) */
edc_tmp = mem_read32(EDC_CFG);
edc_tmp |= (0x1U << 0U);
ecm_write(EDC_CFG, edc_tmp);
/* Lock the ECM registers */
ecm_lock();
}

104
Src/0_Tool/Gen4_R-Car_IPL/SDK/v3_46_0/Gen4_ICUMX_Loader/ip/ddr/s4/lpddr4x/ecc_enable_s4.h Normal file
View File

@@ -0,0 +1,104 @@
/*******************************************************************************
* Copyright (c) 2022 Renesas Electronics Corporation. All rights reserved.
*
* RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY
*
* This software is provided as reference/sample code under the license
* agreement between Renesas Electronics Corporation and licensee (the
* "License Agreement") and shall be treated as specified in the License
* Agreement.
* These instructions, statements, and software are the confidential
* information of Renesas Electronics Corporation. They must be used and
* modified solely for the purpose for which it was furnished by Renesas
* Electronics Corporation. All or part of these instructions, statements and
* software must not be reproduced nor disclosed to any third party in any
* form, unless permitted by the License Agreement.
*
* THIS SOFTWARE IS PROVIDED BY RENESAS ELEOCTRONICS CORPORATION "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
* SATISFACTORY QUALITY, ACCURACY, TITLE AND NON-INFRINGEMENT ARE DISCLAIMED.
* IN NO EVENT SHALL RENESAS ELECTRONICS CORPORATION BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, PUNITIVE, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
* DAMAGE.
******************************************************************************/
/*******************************************************************************
* DESCRIPTION : ECC driver header
******************************************************************************/
#ifndef ECC_PROTECT
#define ECC_PROTECT
#include "remap_register.h"
#if(__RH850__)
#include "mem_io.h"
#include "log.h"
#define ECM_BASE (BASE_ECC_ADDR)
#define DBSC_BASE (BASE_DBSC_ADDR)
#else
#include <mmio.h>
#include <debug.h>
#define ECM_BASE (0xE6250000U)
#define DBSC_BASE (0xE6790000U)
#endif/* __RH850__ */
#define RTVRAM_REG_BASE (0xFFEC0000U)
void enable_ecc(void);
void ecc_rtsram_enable(void);
void edc_axi_enable(void);
void edc_vram_enable(void);
#define DBSC_DBACEN (DBSC_BASE + 0x0200U)
#define ECMWACNTR (ECM_BASE + 0x0A04U)
#define ECMWPCNTR (ECM_BASE + 0x0A00U)
#define ECMERRTGTR0 (ECM_BASE + 0x0200U)
#define ECMERRCTLR0 (ECM_BASE + 0x0000U)
#define ECMERRTGTR1 (ECM_BASE + 0x0200U + 0x4U * 1U)
#define ECMERRCTLR1 (ECM_BASE + 0x0000U + 0x4U * 1U)
#define ECMERRTGTR7 (ECM_BASE + 0x0200U + 0x4U * 7U)
#define ECMERRCTLR7 (ECM_BASE + 0x0000U + 0x4U * 7U)
#define ECMERRTGTR17 (ECM_BASE + 0x0200U + 0x4U * 17U)
#define ECMERRCTLR17 (ECM_BASE + 0x0000U + 0x4U * 17U)
#define ECMERRTGTR39 (ECM_BASE + 0x0200U + 0x4U * 39U)
#define ECMERRCTLR39 (ECM_BASE + 0x0000U + 0x4U * 39U)
#define ECMERRFATALR0 (ECM_BASE + 0x0600U)
#define ECMERRFATALR1 (ECM_BASE + 0x0600U + 0x4U * 1U)
#define ECMERRFATALR7 (ECM_BASE + 0x0600U + 0x4U * 7U)
#define ECMERRFATALR17 (ECM_BASE + 0x0600U + 0x4U * 17U)
#define ECMERRFATALR39 (ECM_BASE + 0x0600U + 0x4U * 39U)
#define DBFSCONF00A (DBSC_BASE + 0x7640U)
#define DBFSCONF01A (DBSC_BASE + 0x7644U)
#define DBFSCONF05A (DBSC_BASE + 0x7654U)
#define DBFSCTRL01A (DBSC_BASE + 0x7604U)
#define DBFSSTAT01A (DBSC_BASE + 0x7684U)
#define DBFSSTAT00A (DBSC_BASE + 0x7680U)
#define DBFSINTENB02A (DBSC_BASE + 0x7088U)
#define DBFSINTENB04A (DBSC_BASE + 0x7090U)
#define DBFSDRAMECCAREA00 (DBSC_BASE + 0x7450U)
#define DBFSDRAMECCAREA01 (DBSC_BASE + 0x7454U)
#define DBFSCONFAXI0 (DBSC_BASE + 0x7400U)
#define EDC_CFG (RTVRAM_REG_BASE + 0x4110U)
/********************* Set by the user *********************/
/* The row address of ECC Protection Area Size for memory rank 0/1 */
#define ECC_PROT_SIZE0 (0x2000U)
#define ECC_PROT_SIZE1 (0x2000U)
/* Start and End row address of ECC Protection area for rank0 */
#define START_ECC_INIT_AREA0 (0x00000000U)
#define END_ECC_INIT_AREA0 (0x00001FFFU)
/* Start and End row address of ECC Protection area for rank1 */
#define START_ECC_INIT_AREA1 (0x00000000U)
#define END_ECC_INIT_AREA1 (0x00001FFFU)
/*********** Other settings cannot be changed ***************/
#endif/* ECC_PROTECT */

615
Src/0_Tool/Gen4_R-Car_IPL/SDK/v3_46_0/Gen4_ICUMX_Loader/ip/ddr/s4/lpddr4x/init_dram_tbl_s4.h Normal file
View File

@@ -0,0 +1,615 @@
/*******************************************************************************
* Copyright (c) 2021-2022 Renesas Electronics Corporation. All rights reserved.
*
* RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY
*
* This software is provided as reference/sample code under the license
* agreement between Renesas Electronics Corporation and licensee (the
* "License Agreement") and shall be treated as specified in the License
* Agreement.
* These instructions, statements, and software are the confidential
* information of Renesas Electronics Corporation. They must be used and
* modified solely for the purpose for which it was furnished by Renesas
* Electronics Corporation. All or part of these instructions, statements and
* software must not be reproduced nor disclosed to any third party in any
* form, unless permitted by the License Agreement.
*
* THIS SOFTWARE IS PROVIDED BY RENESAS ELEOCTRONICS CORPORATION "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
* SATISFACTORY QUALITY, ACCURACY, TITLE AND NON-INFRINGEMENT ARE DISCLAIMED.
* IN NO EVENT SHALL RENESAS ELECTRONICS CORPORATION BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, PUNITIVE, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
* DAMAGE.
******************************************************************************/
#define DDR_PHY_SLICE_REGSET_OFS_S4 0x1000
#define DDR_PHY_ADR_V_REGSET_OFS_S4 0x1200
#define DDR_PHY_ADR_G_REGSET_OFS_S4 0x1300
#define DDR_PI_REGSET_OFS_S4 0x0800
#define DDR_PHY_SLICE_REGSET_SIZE_S4 0x100
#define DDR_PHY_ADR_V_REGSET_SIZE_S4 0x80
#define DDR_PHY_ADR_G_REGSET_SIZE_S4 0x100
#define DDR_PI_REGSET_SIZE_S4 0x100
#define DDR_PHY_SLICE_REGSET_NUM_S4 140
#define DDR_PHY_ADR_V_REGSET_NUM_S4 54
#define DDR_PHY_ADR_G_REGSET_NUM_S4 143
#define DDR_PI_REGSET_NUM_S4 223
static const uint32_t DDR_PHY_SLICE_REGSET_S4[DDR_PHY_SLICE_REGSET_NUM_S4] = {
/*1000*/ 0x000004F0,
/*1001*/ 0x00000000,
/*1002*/ 0x00030200,
/*1003*/ 0x00000000,
/*1004*/ 0x00000000,
/*1005*/ 0x01030000,
/*1006*/ 0x00010000,
/*1007*/ 0x01030004,
/*1008*/ 0x00000000,
/*1009*/ 0x00000000,
/*100a*/ 0x00000000,
/*100b*/ 0x01000001,
/*100c*/ 0x00000200,
/*100d*/ 0x000800C0,
/*100e*/ 0x06010190,
/*100f*/ 0x00030030,
/*1010*/ 0x00000000,
/*1011*/ 0x00000000,
/*1012*/ 0x55555A3C,
/*1013*/ 0x00005555,
/*1014*/ 0x0000B5B5,
/*1015*/ 0x00004A4A,
/*1016*/ 0x00005656,
/*1017*/ 0x0000A9A9,
/*1018*/ 0x0000A9A9,
/*1019*/ 0x0000B5B5,
/*101a*/ 0x00000000,
/*101b*/ 0x00000000,
/*101c*/ 0x2A000000,
/*101d*/ 0x00000808,
/*101e*/ 0x04000000,
/*101f*/ 0x00000408,
/*1020*/ 0x10600000,
/*1021*/ 0x0C008006,
/*1022*/ 0x00000000,
/*1023*/ 0x00000000,
/*1024*/ 0x55AA55AA,
/*1025*/ 0x33CC33CC,
/*1026*/ 0x0FF00FF0,
/*1027*/ 0x0F0FF0F0,
/*1028*/ 0x00008E38,
/*1029*/ 0x01000100,
/*102a*/ 0x00800180,
/*102b*/ 0x00000001,
/*102c*/ 0x00000000,
/*102d*/ 0x00000000,
/*102e*/ 0x00000000,
/*102f*/ 0x00000000,
/*1030*/ 0x00000000,
/*1031*/ 0x00000000,
/*1032*/ 0x00000000,
/*1033*/ 0x00000000,
/*1034*/ 0x00000000,
/*1035*/ 0x00000000,
/*1036*/ 0x00000000,
/*1037*/ 0x00000000,
/*1038*/ 0x00000000,
/*1039*/ 0x00000000,
/*103a*/ 0x00000000,
/*103b*/ 0x00000000,
/*103c*/ 0x00000000,
/*103d*/ 0x00000000,
/*103e*/ 0x00000000,
/*103f*/ 0x00000000,
/*1040*/ 0x00000000,
/*1041*/ 0x00000000,
/*1042*/ 0x00000104,
/*1043*/ 0x00000120,
/*1044*/ 0x00000000,
/*1045*/ 0x00000000,
/*1046*/ 0x00000000,
/*1047*/ 0x00000000,
/*1048*/ 0x00000000,
/*1049*/ 0x00000000,
/*104a*/ 0x00000000,
/*104b*/ 0x00000000,
/*104c*/ 0x07FF0000,
/*104d*/ 0x00800800,
/*104e*/ 0x00081020,
/*104f*/ 0x04010000,
/*1050*/ 0x00000000,
/*1051*/ 0x00000000,
/*1052*/ 0x00000000,
/*1053*/ 0x00000000,
/*1054*/ 0x01CC0C01,
/*1055*/ 0x2003CC0C,
/*1056*/ 0x20000139,
/*1057*/ 0x07FF0200,
/*1058*/ 0x0100DD01,
/*1059*/ 0x00000103,
/*105a*/ 0x00000000,
/*105b*/ 0x00000000,
/*105c*/ 0x00060000,
/*105d*/ 0x00A000A0,
/*105e*/ 0x00A000A0,
/*105f*/ 0x00A000A0,
/*1060*/ 0x00A000A0,
/*1061*/ 0x000500A0,
/*1062*/ 0x51517042,
/*1063*/ 0x31C08000,
/*1064*/ 0x09AD0064,
/*1065*/ 0x00C0C001,
/*1066*/ 0x0E0C0101,
/*1067*/ 0x10001000,
/*1068*/ 0x0C073E42,
/*1069*/ 0x0F0C3708,
/*106a*/ 0x01C00190,
/*106b*/ 0x04000420,
/*106c*/ 0x00000322,
/*106d*/ 0x0A0000D0,
/*106e*/ 0x00030200,
/*106f*/ 0x02800000,
/*1070*/ 0x80800000,
/*1071*/ 0x000E0010,
/*1072*/ 0x76543210,
/*1073*/ 0x00000008,
/*1074*/ 0x02800280,
/*1075*/ 0x02800280,
/*1076*/ 0x02800280,
/*1077*/ 0x02800280,
/*1078*/ 0x00000280,
/*1079*/ 0x0000A000,
/*107a*/ 0x00A000A0,
/*107b*/ 0x00A000A0,
/*107c*/ 0x00A000A0,
/*107d*/ 0x00A000A0,
/*107e*/ 0x00A000A0,
/*107f*/ 0x00A000A0,
/*1080*/ 0x00A000A0,
/*1081*/ 0x00A000A0,
/*1082*/ 0x01C200A0,
/*1083*/ 0x01A00005,
/*1084*/ 0x00000000,
/*1085*/ 0x00000000,
/*1086*/ 0x00080200,
/*1087*/ 0x00000000,
/*1088*/ 0x20202020,
/*1089*/ 0x20202020,
/*108a*/ 0x01012020,
/*108b*/ 0x00000000
};
static const uint32_t DDR_PHY_ADR_V_REGSET_S4[DDR_PHY_ADR_V_REGSET_NUM_S4] = {
/*1200*/ 0x00000000,
/*1201*/ 0x00000000,
/*1202*/ 0x00000000,
/*1203*/ 0x00000000,
/*1204*/ 0x00000000,
/*1205*/ 0x00000100,
/*1206*/ 0x00000200,
/*1207*/ 0x00000000,
/*1208*/ 0x00000000,
/*1209*/ 0x00000000,
/*120a*/ 0x00000000,
/*120b*/ 0x00800200,
/*120c*/ 0x00000080,
/*120d*/ 0x00DCBA98,
/*120e*/ 0x01000000,
/*120f*/ 0x00200003,
/*1210*/ 0x00000000,
/*1211*/ 0x00000000,
/*1212*/ 0x00000000,
/*1213*/ 0x00000000,
/*1214*/ 0x00000000,
/*1215*/ 0x00000000,
/*1216*/ 0x00000000,
/*1217*/ 0x0000002A,
/*1218*/ 0x00000015,
/*1219*/ 0x00000015,
/*121a*/ 0x0000002A,
/*121b*/ 0x00000033,
/*121c*/ 0x0000000C,
/*121d*/ 0x0000000C,
/*121e*/ 0x00000033,
/*121f*/ 0x00543210,
/*1220*/ 0x003F0000,
/*1221*/ 0x0000013F,
/*1222*/ 0x20202003,
/*1223*/ 0x00202020,
/*1224*/ 0x20008008,
/*1225*/ 0x00000810,
/*1226*/ 0x00000F00,
/*1227*/ 0x00000000,
/*1228*/ 0x00000000,
/*1229*/ 0x00000000,
/*122a*/ 0x000605CC,
/*122b*/ 0x00030000,
/*122c*/ 0x00000300,
/*122d*/ 0x00000300,
/*122e*/ 0x00000300,
/*122f*/ 0x00000300,
/*1230*/ 0x00000300,
/*1231*/ 0x42080010,
/*1232*/ 0x0000803E,
/*1233*/ 0x00000008,
/*1234*/ 0x01000001,
/*1235*/ 0x00008000
};
static const uint32_t DDR_PHY_ADR_G_REGSET_S4[DDR_PHY_ADR_G_REGSET_NUM_S4] = {
/*1300*/ 0x00000000,
/*1301*/ 0x00000100,
/*1302*/ 0x00000000,
/*1303*/ 0x00000000,
/*1304*/ 0x00050000,
/*1305*/ 0x04000000,
/*1306*/ 0x00000020,
/*1307*/ 0x00000000,
/*1308*/ 0x00000000,
/*1309*/ 0x00000000,
/*130a*/ 0x00000000,
/*130b*/ 0x00002001,
/*130c*/ 0x00004003,
/*130d*/ 0x00010028,
/*130e*/ 0x01010100,
/*130f*/ 0x00800800,
/*1310*/ 0x08102000,
/*1311*/ 0x00000000,
/*1312*/ 0x00000000,
/*1313*/ 0x00010E06,
/*1314*/ 0x00000000,
/*1315*/ 0x00000000,
/*1316*/ 0x00000000,
/*1317*/ 0x00000000,
/*1318*/ 0x00040000,
/*1319*/ 0x00000000,
/*131a*/ 0x00000000,
/*131b*/ 0x00000064,
/*131c*/ 0x00000000,
/*131d*/ 0x00000100,
/*131e*/ 0x00000200,
/*131f*/ 0x80012000,
/*1320*/ 0x00041B42,
/*1321*/ 0x05000000,
/*1322*/ 0x00000000,
/*1323*/ 0x00000000,
/*1324*/ 0x00000000,
/*1325*/ 0x01000000,
/*1326*/ 0x01070501,
/*1327*/ 0x00000054,
/*1328*/ 0x00004410,
/*1329*/ 0x00004410,
/*132a*/ 0x00004410,
/*132b*/ 0x00004410,
/*132c*/ 0x00004410,
/*132d*/ 0x00004410,
/*132e*/ 0x00004410,
/*132f*/ 0x00004410,
/*1330*/ 0x00004410,
/*1331*/ 0x00000000,
/*1332*/ 0x00000000,
/*1333*/ 0x00000000,
/*1334*/ 0x00060000,
/*1335*/ 0x00000000,
/*1336*/ 0x00000090,
/*1337*/ 0x0000A25A,
/*1338*/ 0x00000008,
/*1339*/ 0x00000000,
/*133a*/ 0x00000000,
/*133b*/ 0x00000000,
/*133c*/ 0x00000000,
/*133d*/ 0x00000000,
/*133e*/ 0x03000000,
/*133f*/ 0x00000000,
/*1340*/ 0x00000000,
/*1341*/ 0x00000000,
/*1342*/ 0x04102000,
/*1343*/ 0x00041020,
/*1344*/ 0x00C98C98,
/*1345*/ 0x3F400000,
/*1346*/ 0x3F3F1F3F,
/*1347*/ 0x0000001F,
/*1348*/ 0x00000000,
/*1349*/ 0x00000000,
/*134a*/ 0x00000000,
/*134b*/ 0x00010000,
/*134c*/ 0x00000000,
/*134d*/ 0x00000000,
/*134e*/ 0x00000000,
/*134f*/ 0x00000100,
/*1350*/ 0x00000000,
/*1351*/ 0x00000000,
/*1352*/ 0x00040700,
/*1353*/ 0x00000000,
/*1354*/ 0x00000000,
/*1355*/ 0x00000000,
/*1356*/ 0x00000002,
/*1357*/ 0x00000100,
/*1358*/ 0x00000000,
/*1359*/ 0x00000000,
/*135a*/ 0x00001F00,
/*135b*/ 0x00000000,
/*135c*/ 0x00000000,
/*135d*/ 0x00080000,
/*135e*/ 0x000007FF,
/*135f*/ 0x00000000,
/*1360*/ 0x00000000,
/*1361*/ 0x00000000,
/*1362*/ 0x00000000,
/*1363*/ 0x00000000,
/*1364*/ 0x000FFFFF,
/*1365*/ 0x000FFFFF,
/*1366*/ 0x0000FFFF,
/*1367*/ 0xFFFFFFF0,
/*1368*/ 0x030FFFFF,
/*1369*/ 0x01FFFFFF,
/*136a*/ 0x0000FFFF,
/*136b*/ 0x00000000,
/*136c*/ 0x00000000,
/*136d*/ 0x00000000,
/*136e*/ 0x00000000,
/*136f*/ 0x00000000,
/*1370*/ 0x00000006,
/*1371*/ 0x00000000,
/*1372*/ 0x00001142,
/*1373*/ 0x08010600,
/*1374*/ 0x00000080,
/*1375*/ 0x03000300,
/*1376*/ 0x03000300,
/*1377*/ 0x00000300,
/*1378*/ 0x00000300,
/*1379*/ 0x00000300,
/*137a*/ 0x00000300,
/*137b*/ 0x00000005,
/*137c*/ 0x0004BFCC,
/*137d*/ 0x0000010C,
/*137e*/ 0x0000027F,
/*137f*/ 0x00000000,
/*1380*/ 0x0000027F,
/*1381*/ 0x00000000,
/*1382*/ 0x00127F00,
/*1383*/ 0x0089FF00,
/*1384*/ 0x00827FCC,
/*1385*/ 0x00000000,
/*1386*/ 0x00127F80,
/*1387*/ 0x01980000,
/*1388*/ 0x00127F80,
/*1389*/ 0x01980000,
/*138a*/ 0x00127F00,
/*138b*/ 0x01980000,
/*138c*/ 0x00127F00,
/*138d*/ 0x01980000,
/*138e*/ 0x20040006
};
static const uint32_t DDR_PI_REGSET_S4[DDR_PI_REGSET_NUM_S4] = {
/*0800*/ 0x00000B00,
/*0801*/ 0x00000000,
/*0802*/ 0x00000000,
/*0803*/ 0x00000101,
/*0804*/ 0x00640000,
/*0805*/ 0x00000001,
/*0806*/ 0x00000000,
/*0807*/ 0x00000000,
/*0808*/ 0x00000000,
/*0809*/ 0x00000000,
/*080a*/ 0x00000003,
/*080b*/ 0x00010100,
/*080c*/ 0x08000003,
/*080d*/ 0x00000103,
/*080e*/ 0x00000000,
/*080f*/ 0x00000000,
/*0810*/ 0x00000000,
/*0811*/ 0x00000000,
/*0812*/ 0x00000000,
/*0813*/ 0x00000000,
/*0814*/ 0x0A000000,
/*0815*/ 0x00000028,
/*0816*/ 0x00000100,
/*0817*/ 0x00320003,
/*0818*/ 0x00000000,
/*0819*/ 0x00000000,
/*081a*/ 0x01010102,
/*081b*/ 0x00000000,
/*081c*/ 0x55555A3C,
/*081d*/ 0x00000055,
/*081e*/ 0x000000B5,
/*081f*/ 0x0000004A,
/*0820*/ 0x00000056,
/*0821*/ 0x000000A9,
/*0822*/ 0x000000A9,
/*0823*/ 0x000000B5,
/*0824*/ 0x01000000,
/*0825*/ 0x00010000,
/*0826*/ 0x00030300,
/*0827*/ 0x0000001A,
/*0828*/ 0x000007D0,
/*0829*/ 0x00000300,
/*082a*/ 0x00000000,
/*082b*/ 0x00000000,
/*082c*/ 0x01080000,
/*082d*/ 0x00010101,
/*082e*/ 0x00000000,
/*082f*/ 0x00030000,
/*0830*/ 0x03000100,
/*0831*/ 0x00000017,
/*0832*/ 0x00000000,
/*0833*/ 0x00000000,
/*0834*/ 0x00000000,
/*0835*/ 0x0A0A140A,
/*0836*/ 0x10020300,
/*0837*/ 0x00020805,
/*0838*/ 0x00000404,
/*0839*/ 0x00000000,
/*083a*/ 0x00000000,
/*083b*/ 0x01000101,
/*083c*/ 0x00020203,
/*083d*/ 0x00340000,
/*083e*/ 0x00000000,
/*083f*/ 0x00000000,
/*0840*/ 0x01000000,
/*0841*/ 0x00000000,
/*0842*/ 0x00000800,
/*0843*/ 0x00020002,
/*0844*/ 0x00010001,
/*0845*/ 0x00010000,
/*0846*/ 0x00020002,
/*0847*/ 0x00000002,
/*0848*/ 0x00000000,
/*0849*/ 0x00000000,
/*084a*/ 0x00000000,
/*084b*/ 0x00000000,
/*084c*/ 0x00000000,
/*084d*/ 0x00000000,
/*084e*/ 0x00000000,
/*084f*/ 0x00000000,
/*0850*/ 0x00100400,
/*0851*/ 0x08010100,
/*0852*/ 0x08000000,
/*0853*/ 0x00000100,
/*0854*/ 0x00000000,
/*0855*/ 0x0000AA00,
/*0856*/ 0x00000000,
/*0857*/ 0x00010000,
/*0858*/ 0x00000000,
/*0859*/ 0x00000000,
/*085a*/ 0x00000000,
/*085b*/ 0x00000000,
/*085c*/ 0x00000000,
/*085d*/ 0x00000000,
/*085e*/ 0x00000000,
/*085f*/ 0x00000000,
/*0860*/ 0x00000000,
/*0861*/ 0x00000000,
/*0862*/ 0x00000000,
/*0863*/ 0x00000000,
/*0864*/ 0x00000000,
/*0865*/ 0x00000000,
/*0866*/ 0x00000000,
/*0867*/ 0x00000000,
/*0868*/ 0x00000000,
/*0869*/ 0x00000000,
/*086a*/ 0x00000000,
/*086b*/ 0x00000000,
/*086c*/ 0x00000000,
/*086d*/ 0x00000000,
/*086e*/ 0x00000000,
/*086f*/ 0x00000000,
/*0870*/ 0x00000000,
/*0871*/ 0x00000000,
/*0872*/ 0x00000000,
/*0873*/ 0x00000000,
/*0874*/ 0x00000000,
/*0875*/ 0x00000000,
/*0876*/ 0x00000000,
/*0877*/ 0x00000002,
/*0878*/ 0x01010001,
/*0879*/ 0x00010200,
/*087a*/ 0x04000103,
/*087b*/ 0x01050001,
/*087c*/ 0x00010600,
/*087d*/ 0x00000107,
/*087e*/ 0x00000000,
/*087f*/ 0x00000000,
/*0880*/ 0x00000100,
/*0881*/ 0x00000000,
/*0882*/ 0x00000000,
/*0883*/ 0x00000000,
/*0884*/ 0x00040100,
/*0885*/ 0x00000000,
/*0886*/ 0x00000000,
/*0887*/ 0x01000000,
/*0888*/ 0x00002B2B,
/*0889*/ 0x00000034,
/*088a*/ 0x0000006C,
/*088b*/ 0x120C046C,
/*088c*/ 0x00481248,
/*088d*/ 0x00000006,
/*088e*/ 0x00000046,
/*088f*/ 0x00000256,
/*0890*/ 0x00002073,
/*0891*/ 0x00000256,
/*0892*/ 0x04002073,
/*0893*/ 0x00000404,
/*0894*/ 0x00002A00,
/*0895*/ 0x002A002A,
/*0896*/ 0x01000100,
/*0897*/ 0x00000100,
/*0898*/ 0x00000000,
/*0899*/ 0x00000000,
/*089a*/ 0x00010000,
/*089b*/ 0x00010100,
/*089c*/ 0x00010100,
/*089d*/ 0x15040100,
/*089e*/ 0x0E0E0215,
/*089f*/ 0x00040402,
/*08a0*/ 0x000C0034,
/*08a1*/ 0x00210049,
/*08a2*/ 0x00210049,
/*08a3*/ 0x01000001,
/*08a4*/ 0x00040005,
/*08a5*/ 0x00040216,
/*08a6*/ 0x01000216,
/*08a7*/ 0x00060006,
/*08a8*/ 0x02170100,
/*08a9*/ 0x01000217,
/*08aa*/ 0x02170217,
/*08ab*/ 0x11111111,
/*08ac*/ 0x00001111,
/*08ad*/ 0x0A070600,
/*08ae*/ 0x1F130A0D,
/*08af*/ 0x1F130A14,
/*08b0*/ 0x0000C014,
/*08b1*/ 0x00C01000,
/*08b2*/ 0x00C01000,
/*08b3*/ 0x00021000,
/*08b4*/ 0x00240005,
/*08b5*/ 0x00240216,
/*08b6*/ 0x003E0216,
/*08b7*/ 0x1609003A,
/*08b8*/ 0x00000007,
/*08b9*/ 0x003A003E,
/*08ba*/ 0x00071609,
/*08bb*/ 0x00003E00,
/*08bc*/ 0x1609003A,
/*08bd*/ 0x08000007,
/*08be*/ 0x04010404,
/*08bf*/ 0x01030277,
/*08c0*/ 0x0A0A0320,
/*08c1*/ 0x18272D10,
/*08c2*/ 0x5A752F28,
/*08c3*/ 0x1E202008,
/*08c4*/ 0x272D1016,
/*08c5*/ 0x752F2818,
/*08c6*/ 0x2020085A,
/*08c7*/ 0x0000161E,
/*08c8*/ 0x0000008C,
/*08c9*/ 0x00000578,
/*08ca*/ 0x000040E6,
/*08cb*/ 0x000288FC,
/*08cc*/ 0x000040E6,
/*08cd*/ 0x000288FC,
/*08ce*/ 0x02660006,
/*08cf*/ 0x04040266,
/*08d0*/ 0xC83CC804,
/*08d1*/ 0x0000003C,
/*08d2*/ 0x00040000,
/*08d3*/ 0x0F1166F1,
/*08d4*/ 0x3F740006,
/*08d5*/ 0x0F1166F1,
/*08d6*/ 0x3F740006,
/*08d7*/ 0x0F1166F1,
/*08d8*/ 0x00040006,
/*08d9*/ 0x0F1166F1,
/*08da*/ 0x3F74002E,
/*08db*/ 0x0F1166F1,
/*08dc*/ 0x3F74002E,
/*08dd*/ 0x0F1166F1,
/*08de*/ 0x0000002E
};

302
Src/0_Tool/Gen4_R-Car_IPL/SDK/v3_46_0/Gen4_ICUMX_Loader/ip/ddr/v4h/lpddr5/boot_init_dram_regdef.h Normal file
View File

@@ -0,0 +1,302 @@
/*******************************************************************************
* Copyright (c) 2015-2022 Renesas Electronics Corporation. All rights reserved.
*
* RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY
*
* This software is provided as reference/sample code under the license
* agreement between Renesas Electronics Corporation and licensee (the
* "License Agreement") and shall be treated as specified in the License
* Agreement.
* These instructions, statements, and software are the confidential
* information of Renesas Electronics Corporation. They must be used and
* modified solely for the purpose for which it was furnished by Renesas
* Electronics Corporation. All or part of these instructions, statements and
* software must not be reproduced nor disclosed to any third party in any
* form, unless permitted by the License Agreement.
*
* THIS SOFTWARE IS PROVIDED BY RENESAS ELEOCTRONICS CORPORATION "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
* SATISFACTORY QUALITY, ACCURACY, TITLE AND NON-INFRINGEMENT ARE DISCLAIMED.
* IN NO EVENT SHALL RENESAS ELECTRONICS CORPORATION BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, PUNITIVE, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
* DAMAGE.
******************************************************************************/
#if defined(__RH850G3K__)
#include "remap_register.h"
#endif
#define RCAR_DDR_VERSION "rev.0.08rc7"
#define DRAM_CH_CNT 0x04
#define SLICE_CNT 0x02
#define CS_CNT 0x02
/* for pll setting */
#define CLK_DIV(a, diva, b, divb) (((a) * (divb)) / ((b) * (diva)))
#define CLK_MUL(a, diva, b, divb) (((a) * (b)) / ((diva) * (divb)))
/* for ddr density setting */
#define DBMEMCONF_REG(d3, row, BG, bank, col, dw) (((d3) << 30) | ((row) << 24) | ((BG) << 20) | ((bank) << 16) | ((col) << 8) | (dw))
#define DBMEMCONF_REGD(density) (DBMEMCONF_REG((density) % 2, ((density) + 1) / 2 + (28 - 2 - 2 - 10 - 1), 2, 2, 10, 1)) /* 16bit */
#define DBMEMCONF_VAL(ch,cs) (DBMEMCONF_REGD(DBMEMCONF_DENS(ch, cs)))
/* system registers : CPG */
#define CPG_FRQCRD_KICK_BIT (1U << 31)
#define CPG_PLL3CR0_KICK_BIT (1U << 31)
#define CPG_PLLECR_PLL3E_BIT (1U << 3)
#define CPG_PLLECR_PLL3ST_BIT (1U << 11)
#if defined(__RH850G3K__)
#define CPG_BASE (BASE_CPG_ADDR)
#else
#define CPG_BASE (0xE6150000U)
#endif
#define CPG_CPGWPR (CPG_BASE + 0x0000U)
#define CPG_CPGWPCR (CPG_BASE + 0x0004U)
#define CPG_FRQCRA (CPG_BASE + 0x0800U)
#define CPG_FRQCRB (CPG_BASE + 0x0804U)
#define CPG_FRQCRC (CPG_BASE + 0x0808U)
#define CPG_FRQCRD0 (CPG_BASE + 0x080CU)
#define CPG_PLLECR (CPG_BASE + 0x0820U)
#define CPG_PLL3CR0 (CPG_BASE + 0x083CU)
#define CPG_PLL3CR1 (CPG_BASE + 0x08C0U)
#define CPG_FSRCHKCLRR4 (CPG_BASE + 0x0590U)
#define CPG_FSRCHKSETR4 (CPG_BASE + 0x0510U)
#define CPG_FSRCHKRA4 (CPG_BASE + 0x0410U)
#define CPG_SRCR4 (CPG_BASE + 0x2C10U)
#define CPG_SRSTCLR4 (CPG_BASE + 0x2C90U)
#define CPG_PLL3FBCKMCSR (CPG_BASE + 0x0C60U)
#define CPG_PLL3FBCKMECR (CPG_BASE + 0x0C64U)
#define CPG_PLL3FBCKMLCH (CPG_BASE + 0x0C68U)
#define CPG_PLL3FBCKMLCL (CPG_BASE + 0x0C6CU)
#define CPG_PLL3FBCKMCNT (CPG_BASE + 0x0C70U)
#define CPG_PLL3FBCKMCNTE (CPG_BASE + 0x0C74U)
#if defined(__RH850G3K__)
#define RST_BASE (BASE_RESET_ADDR)
#else
#define RST_BASE (0xE6160000U)
#endif
#define RST_MODEMR0 (RST_BASE + 0x0000U)
#define RST_MODEMR1 (RST_BASE + 0x0004U)
/* Product Register */
#define PRR (0xFFF00044U)
#define PRR_PRODUCT_MASK (0x00007F00U)
#define PRR_CUT_MASK (0x000000FFU)
#define PRR_PRODUCT_V4H (0x00005C00U) /* R-Car V4H */
#define PRR_PRODUCT_10 (0x00000000U) /* ver 1.0 */
#define PRR_PRODUCT_20 (0x00000010U) /* ver 2.0 */
/* DBSC registers */
#if defined(__RH850G3K__)
#define DBSC_D_BASE (BASE_DBSC_ADDR + 0x14000U) /* forV4H DBSC0 clk_dbsc region DBSC1_D_BASE = 0xE67A8000U */
#define DBSC_A_BASE (BASE_DBSC_ADDR) /* forV4H DBSC0 clk_axim region DBSC1_A_BASE = 0xE6798000U */
#else
#define DBSC_D_BASE (0xE67A4000U) /* forV4H DBSC0 clk_dbsc region DBSC1_D_BASE = 0xE67A8000U */
#define DBSC_A_BASE (0xE6790000U) /* forV4H DBSC0 clk_axim region DBSC1_A_BASE = 0xE6798000U */
#endif
#define DBSC_DBSYSCONF0 (DBSC_A_BASE + 0x0000U)
#define DBSC_DBSYSCONF1 (DBSC_D_BASE + 0x0000U)
#define DBSC_DBSYSCONF1A (DBSC_A_BASE + 0x0004U)
#define DBSC_DBSYSCONF2 (DBSC_D_BASE + 0x0004U)
#define DBSC_DBPHYCONF0 (DBSC_D_BASE + 0x0008U)
#define DBSC_DBSYSCONF2A (DBSC_A_BASE + 0x0008U)
#define DBSC_DBMEMKIND (DBSC_D_BASE + 0x0020U)
#define DBSC_DBMEMKINDA (DBSC_A_BASE + 0x0020U)
#define DBSC_DBMEMCONF(ch,cs) (DBSC_D_BASE + 0x0030U + 0x10U * (ch) + 0x04U * (cs))
#define DBSC_DBMEMCONF_0_0 (DBSC_D_BASE + 0x0030U)
#define DBSC_DBMEMCONF_0_1 (DBSC_D_BASE + 0x0034U)
#define DBSC_DBMEMCONF_0_2 (DBSC_D_BASE + 0x0038U)
#define DBSC_DBMEMCONF_0_3 (DBSC_D_BASE + 0x003CU)
#define DBSC_DBMEMCONF_1_0 (DBSC_D_BASE + 0x0040U)
#define DBSC_DBMEMCONF_1_1 (DBSC_D_BASE + 0x0044U)
#define DBSC_DBMEMCONF_1_2 (DBSC_D_BASE + 0x0048U)
#define DBSC_DBMEMCONF_1_3 (DBSC_D_BASE + 0x004CU)
#define DBSC_DBMEMCONF_2_0 (DBSC_D_BASE + 0x0050U)
#define DBSC_DBMEMCONF_2_1 (DBSC_D_BASE + 0x0054U)
#define DBSC_DBMEMCONF_2_2 (DBSC_D_BASE + 0x0058U)
#define DBSC_DBMEMCONF_2_3 (DBSC_D_BASE + 0x005CU)
#define DBSC_DBMEMCONF_3_0 (DBSC_D_BASE + 0x0060U)
#define DBSC_DBMEMCONF_3_1 (DBSC_D_BASE + 0x0064U)
#define DBSC_DBMEMCONF_3_2 (DBSC_D_BASE + 0x0068U)
#define DBSC_DBMEMCONF_3_3 (DBSC_D_BASE + 0x006CU)
#define DBSC_DBMEMCONFA(ch,cs) (DBSC_A_BASE + 0x0030U + 0x10U * (ch) + 0x04U * (cs))
#define DBSC_DBMEMCONF_0_0A (DBSC_A_BASE + 0x0030U)
#define DBSC_DBMEMCONF_0_1A (DBSC_A_BASE + 0x0034U)
#define DBSC_DBMEMCONF_0_2A (DBSC_A_BASE + 0x0038U)
#define DBSC_DBMEMCONF_0_3A (DBSC_A_BASE + 0x003CU)
#define DBSC_DBMEMCONF_1_0A (DBSC_A_BASE + 0x0040U)
#define DBSC_DBMEMCONF_1_1A (DBSC_A_BASE + 0x0044U)
#define DBSC_DBMEMCONF_1_2A (DBSC_A_BASE + 0x0048U)
#define DBSC_DBMEMCONF_1_3A (DBSC_A_BASE + 0x004CU)
#define DBSC_DBMEMCONF_2_0A (DBSC_A_BASE + 0x0050U)
#define DBSC_DBMEMCONF_2_1A (DBSC_A_BASE + 0x0054U)
#define DBSC_DBMEMCONF_2_2A (DBSC_A_BASE + 0x0058U)
#define DBSC_DBMEMCONF_2_3A (DBSC_A_BASE + 0x005CU)
#define DBSC_DBMEMCONF_3_0A (DBSC_A_BASE + 0x0060U)
#define DBSC_DBMEMCONF_3_1A (DBSC_A_BASE + 0x0064U)
#define DBSC_DBMEMCONF_3_2A (DBSC_A_BASE + 0x0068U)
#define DBSC_DBMEMCONF_3_3A (DBSC_A_BASE + 0x006CU)
#define DBSC_DBSYSCNT0 (DBSC_D_BASE + 0x0100U)
#define DBSC_DBSYSCNT0A (DBSC_A_BASE + 0x0100U)
#define DBSC_DBACEN (DBSC_A_BASE + 0x0200U)
#define DBSC_DBRFEN (DBSC_D_BASE + 0x0204U)
#define DBSC_DBCMD (DBSC_D_BASE + 0x0208U)
#define DBSC_DBWAIT (DBSC_D_BASE + 0x0210U)
#define DBSC_DBTR(x) (DBSC_D_BASE + 0x0300U + 0x04U * (x))
#define DBSC_DBTR0 (DBSC_D_BASE + 0x0300U)
#define DBSC_DBTR1 (DBSC_D_BASE + 0x0304U)
#define DBSC_DBTR2 (DBSC_D_BASE + 0x0308U)
#define DBSC_DBTR3 (DBSC_D_BASE + 0x030CU)
#define DBSC_DBTR4 (DBSC_D_BASE + 0x0310U)
#define DBSC_DBTR5 (DBSC_D_BASE + 0x0314U)
#define DBSC_DBTR6 (DBSC_D_BASE + 0x0318U)
#define DBSC_DBTR7 (DBSC_D_BASE + 0x031CU)
#define DBSC_DBTR8 (DBSC_D_BASE + 0x0320U)
#define DBSC_DBTR9 (DBSC_D_BASE + 0x0324U)
#define DBSC_DBTR10 (DBSC_D_BASE + 0x0328U)
#define DBSC_DBTR11 (DBSC_D_BASE + 0x032CU)
#define DBSC_DBTR12 (DBSC_D_BASE + 0x0330U)
#define DBSC_DBTR13 (DBSC_D_BASE + 0x0334U)
#define DBSC_DBTR14 (DBSC_D_BASE + 0x0338U)
#define DBSC_DBTR15 (DBSC_D_BASE + 0x033CU)
#define DBSC_DBTR16 (DBSC_D_BASE + 0x0340U)
#define DBSC_DBTR17 (DBSC_D_BASE + 0x0344U)
#define DBSC_DBTR18 (DBSC_D_BASE + 0x0348U)
#define DBSC_DBTR19 (DBSC_D_BASE + 0x034CU)
#define DBSC_DBTR20 (DBSC_D_BASE + 0x0350U)
#define DBSC_DBTR21 (DBSC_D_BASE + 0x0354U)
#define DBSC_DBTR22 (DBSC_D_BASE + 0x0358U)
#define DBSC_DBTR23 (DBSC_D_BASE + 0x035CU)
#define DBSC_DBTR24 (DBSC_D_BASE + 0x0360U)
#define DBSC_DBTR25 (DBSC_D_BASE + 0x0364U)
#define DBSC_DBTR26 (DBSC_D_BASE + 0x0368U)
#define DBSC_DBTR27 (DBSC_D_BASE + 0x036CU)
#define DBSC_DBTR28 (DBSC_D_BASE + 0x0370U)
#define DBSC_DBTR29 (DBSC_D_BASE + 0x0374U)
#define DBSC_DBTR30 (DBSC_D_BASE + 0x0378U)
#define DBSC_DBTR31 (DBSC_D_BASE + 0x037CU)
#define DBSC_DBTR32 (DBSC_D_BASE + 0x0380U)
#define DBSC_DBTR33 (DBSC_D_BASE + 0x0384U)
#define DBSC_DBTR34 (DBSC_D_BASE + 0x0388U)
#define DBSC_DBTR35 (DBSC_D_BASE + 0x038CU)
#define DBSC_DBTR36 (DBSC_D_BASE + 0x0390U)
#define DBSC_DBTR37 (DBSC_D_BASE + 0x0394U)
#define DBSC_DBBL (DBSC_D_BASE + 0x0400U)
#define DBSC_DBBLA (DBSC_A_BASE + 0x0400U)
#define DBSC_DBRFCNF1 (DBSC_D_BASE + 0x0414U)
#define DBSC_DBRFCNF2 (DBSC_D_BASE + 0x0418U)
#define DBSC_DBCALCNF (DBSC_D_BASE + 0x0424U)
#define DBSC_DBRNK(x) (DBSC_D_BASE + 0x0430U + 0x04U * (x))
#define DBSC_DBRNK2 (DBSC_D_BASE + 0x0438U)
#define DBSC_DBRNK3 (DBSC_D_BASE + 0x043CU)
#define DBSC_DBRNK4 (DBSC_D_BASE + 0x0440U)
#define DBSC_DBRNK5 (DBSC_D_BASE + 0x0444U)
#define DBSC_DBDBICNT (DBSC_D_BASE + 0x0518U)
#define DBSC_DBDFIPMSTRCNF (DBSC_D_BASE + 0x0520U)
#define DBSC_DBDFICUPDCNF (DBSC_D_BASE + 0x0540U)
#define DBSC_DBDFISTAT(ch) (DBSC_D_BASE + 0x0600U + 0x2000U * (ch & 0x02U) + 0x40U * (ch & 0x01U))
#define DBSC_DBDFISTAT_0 (DBSC_D_BASE + 0x0600U)
#define DBSC_DBDFISTAT_1 (DBSC_D_BASE + 0x0640U)
#define DBSC_DBDFISTAT_2 (DBSC_D_BASE + 0x0680U)
#define DBSC_DBDFISTAT_3 (DBSC_D_BASE + 0x06C0U)
#define DBSC_DBDFICNT(ch) (DBSC_D_BASE + 0x0604U + 0x2000U * (ch & 0x02U) + 0x40U * (ch & 0x01U))
#define DBSC_DBDFICNT_0 (DBSC_D_BASE + 0x0604U)
#define DBSC_DBDFICNT_1 (DBSC_D_BASE + 0x0644U)
#define DBSC_DBDFICNT_2 (DBSC_D_BASE + 0x0684U)
#define DBSC_DBDFICNT_3 (DBSC_D_BASE + 0x06C4U)
#define DBSC_DBPDCNT0_0 (DBSC_D_BASE + 0x0610U)
#define DBSC_DBPDCNT0_1 (DBSC_D_BASE + 0x0614U)
#define DBSC_DBPDCNT0_2 (DBSC_D_BASE + 0x0618U)
#define DBSC_DBPDCNT0_3 (DBSC_D_BASE + 0x061CU)
#define DBSC_DBPDCNT1_0 (DBSC_D_BASE + 0x0650U)
#define DBSC_DBPDCNT1_1 (DBSC_D_BASE + 0x0654U)
#define DBSC_DBPDCNT1_2 (DBSC_D_BASE + 0x0658U)
#define DBSC_DBPDCNT1_3 (DBSC_D_BASE + 0x065CU)
#define DBSC_DBPDCNT2(ch) (DBSC_D_BASE + 0x0618U + 0x2000U * (ch & 0x02U) + 0x40U * (ch & 0x01U))
#define DBSC_DBPDCNT2_0 (DBSC_D_BASE + 0x0690U)
#define DBSC_DBPDCNT2_1 (DBSC_D_BASE + 0x0694U)
#define DBSC_DBPDCNT2_2 (DBSC_D_BASE + 0x0698U)
#define DBSC_DBPDCNT2_3 (DBSC_D_BASE + 0x069CU)
#define DBSC_DBPDCNT3_0 (DBSC_D_BASE + 0x06D0U)
#define DBSC_DBPDCNT3_1 (DBSC_D_BASE + 0x06D4U)
#define DBSC_DBPDCNT3_2 (DBSC_D_BASE + 0x06D8U)
#define DBSC_DBPDCNT3_3 (DBSC_D_BASE + 0x06DCU)
#define DBSC_DBPDLK(ch) (DBSC_D_BASE + 0x0620U + 0x2000U * (ch & 0x02U) + 0x40U * (ch & 0x01U))
#define DBSC_DBPDLK_0 (DBSC_D_BASE + 0x0620U)
#define DBSC_DBPDLK_1 (DBSC_D_BASE + 0x0660U)
#define DBSC_DBPDLK_2 (DBSC_D_BASE + 0x06a0U)
#define DBSC_DBPDLK_3 (DBSC_D_BASE + 0x06e0U)
#define DBSC_DBPDRGA(ch) (DBSC_D_BASE + 0x0624U + 0x2000U * (ch & 0x02U) + 0x40U * (ch & 0x01U))
#define DBSC_DBPDRGA_0 (DBSC_D_BASE + 0x0624U)
#define DBSC_DBPDRGA_1 (DBSC_D_BASE + 0x0664U)
#define DBSC_DBPDRGA_2 (DBSC_D_BASE + 0x06A4U)
#define DBSC_DBPDRGA_3 (DBSC_D_BASE + 0x06E4U)
#define DBSC_DBPDRGD(ch) (DBSC_D_BASE + 0x0628U + 0x2000U * (ch & 0x02U) + 0x40U * (ch & 0x01U))
#define DBSC_DBPDRGD_0 (DBSC_D_BASE + 0x0628U)
#define DBSC_DBPDRGD_1 (DBSC_D_BASE + 0x0668U)
#define DBSC_DBPDRGD_2 (DBSC_D_BASE + 0x06A8U)
#define DBSC_DBPDRGD_3 (DBSC_D_BASE + 0x06E8U)
#define DBSC_DBPDSTAT0(ch) (DBSC_D_BASE + 0x0630U + 0x2000U * (ch & 0x02U) + 0x40U * (ch & 0x01U))
#define DBSC_DBPDSTAT0_0 (DBSC_D_BASE + 0x0630U)
#define DBSC_DBPDSTAT1_0 (DBSC_D_BASE + 0x0670U)
#define DBSC_DBPDSTAT1(ch) (DBSC_D_BASE + 0x0634U + 0x2000U * (ch & 0x02U) + 0x40U * (ch & 0x01U))
#define DBSC_DBPDSTAT0_1 (DBSC_D_BASE + 0x0634U)
#define DBSC_DBPDSTA1T_1 (DBSC_D_BASE + 0x0674U)
#define DBSC_DBCAM0CTRL0 (DBSC_A_BASE + 0x0940U)
#define DBSC_DBCAMSTAT0(x) (DBSC_A_BASE + 0x0980U + 0x4000U *(x & 0x02U) + 0x10U * (x & 0x01U))
#define DBSC_DBCAM0STAT0 (DBSC_A_BASE + 0x0980U)
#define DBSC_DBCAM1STAT0 (DBSC_A_BASE + 0x0990U)
#define DBSC_DBCAM2STAT0 (DBSC_A_BASE + 0x09A0U)
#define DBSC_DBCAM3STAT0 (DBSC_A_BASE + 0x09B0U)
#define DBSC_DBCAMSTAT1(x) (DBSC_A_BASE + 0x0984U + 0x4000U *(x & 0x02U) + 0x10U * (x & 0x01U))
#define DBSC_DBCAM0STAT1 (DBSC_A_BASE + 0x0984U)
#define DBSC_DBCAM1STAT1 (DBSC_A_BASE + 0x0994U)
#define DBSC_DBCAM2STAT1 (DBSC_A_BASE + 0x09A4U)
#define DBSC_DBCAM3STAT1 (DBSC_A_BASE + 0x09B4U)
#define DBSC_DBBCAMDIS (DBSC_A_BASE + 0x09FCU)
#define DBSC_DBSCHRW1 (DBSC_A_BASE + 0x1024U)
#define DBSC_DBSCHTR0 (DBSC_A_BASE + 0x1030U)
#define DBSC_DBSCHFCTST01(x) (DBSC_A_BASE + 0x1040U + 0x04U * (x))
#define DBSC_DBSCHFCTST0 (DBSC_A_BASE + 0x1040U)
#define DBSC_DBSCHFCTST1 (DBSC_A_BASE + 0x1044U)
#define DBSC_DBSCHQOS(x,y) (DBSC_A_BASE + 0x1100U + 0x10U * (x) + 0x04U * (y))

232
Src/0_Tool/Gen4_R-Car_IPL/SDK/v3_46_0/Gen4_ICUMX_Loader/ip/ddr/v4h/lpddr5/ecc_enable_v4h.c Normal file
View File

@@ -0,0 +1,232 @@
/*******************************************************************************
* Copyright (c) 2022-2025 Renesas Electronics Corporation. All rights reserved.
*
* RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY
*
* This software is provided as reference/sample code under the license
* agreement between Renesas Electronics Corporation and licensee (the
* "License Agreement") and shall be treated as specified in the License
* Agreement.
* These instructions, statements, and software are the confidential
* information of Renesas Electronics Corporation. They must be used and
* modified solely for the purpose for which it was furnished by Renesas
* Electronics Corporation. All or part of these instructions, statements and
* software must not be reproduced nor disclosed to any third party in any
* form, unless permitted by the License Agreement.
*
* THIS SOFTWARE IS PROVIDED BY RENESAS ELEOCTRONICS CORPORATION "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
* SATISFACTORY QUALITY, ACCURACY, TITLE AND NON-INFRINGEMENT ARE DISCLAIMED.
* IN NO EVENT SHALL RENESAS ELECTRONICS CORPORATION BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, PUNITIVE, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
* DAMAGE.
******************************************************************************/
/*******************************************************************************
* DESCRIPTION : ECC setting function
******************************************************************************/
/******************************************************************************
* @file ecc_enable_v4h.c
* - Version : 0.07
* @brief Enable setting process of ECC for DRAM.
* .
*****************************************************************************/
/******************************************************************************
* History : DD.MM.YYYY Version Description
* : 09.08.2022 0.01 First Release
* : 22.03.2023 0.02 Added AXI Timeout setting
* : 04.04.2023 0.03 Removed stdio.h and string.h.
* : 24.08.2023 0.04 Removed enable_ecc function.
* : 13.06.2024 0.05 Fix register setting for EDC_CFG, and revise
* : the ecm_lock()/ecm_unlock() process.
* : 07.04.2025 0.06 Remove unused functions.
* : 10.06.2025 0.07 Added ECMERRTGTR41/ECMERRCTLR41 register
* operations.
*****************************************************************************/
#include <stdint.h>
#include <cnf_tbl.h>
#include <remap.h>
#include <wdt.h>
#if (ECM_ENABLE == 1)
#include "ecc_enable_v4h.h"
#include "v4h/lpddr5/boot_init_dram_regdef.h"
#include "ecm_enable_v4h.h"
#define AXI_SICREMAP_NUM (5U)
#define RGID_BASE1 (0xFE600000U)
#define RGID_BASE2 (0xE7A00000U)
#define RGID_BASE3 (0xEB800000U)
#define RGID_BASE4 (0xFD800000U)
#define RGID_BASE5 (0xFEA00000U)
#define FDT_COUNTER_MASK (0x0000FFFFU)
static void axi_timeout_setting(void);
void edc_axi_enable(void)
{
uint32_t edc_tmp;
/* Unlock the write protect of ECM registers */
ecm_unlock();
/* (1) Set the corresponding bits of the ECMERRTGTR and ECMERRCTLR registers
to inform the external device of the error via the ERROROUT# pin. */
/* Set bit 11 - bit 2 of ECMERRTGTR7 to all 0 and bit 11 - bit 2 of
ECMERRCTLR7 to 1. (Error of AXI-Bus ECM of each hierarchy) */
edc_tmp = mem_read32(ECMERRTGTR7);
edc_tmp &= ~(0x3FFU << 2U);
ecm_write(ECMERRTGTR7, edc_tmp);
edc_tmp = mem_read32(ECMERRCTLR7);
edc_tmp |= (0x3FFU << 2U);
ecm_write(ECMERRCTLR7, edc_tmp);
/* Set bit 28 - bit 16 of ECMERRTGTR39 to all 0 and bit 28 - bit 16 of
ECMERRCTLR39 to 1. (Error of AXI-Bus ECM of each hierarchy) */
edc_tmp = mem_read32(ECMERRTGTR39);
edc_tmp &= ~(0x1FFFU << 16U);
ecm_write(ECMERRTGTR39, edc_tmp);
edc_tmp = mem_read32(ECMERRCTLR39);
edc_tmp |= (0x1FFFU << 16U);
ecm_write(ECMERRCTLR39, edc_tmp);
/* Set bit 26 of ECMERRTGTR1 to 0 and bit 26 of
ECMERRCTLR1 to 1. (CCI bus EDC error) */
edc_tmp = mem_read32(ECMERRTGTR1);
edc_tmp &= ~(0x1U << 26U);
ecm_write(ECMERRTGTR1, edc_tmp);
edc_tmp = mem_read32(ECMERRCTLR1);
edc_tmp |= (0x1U << 26U);
ecm_write(ECMERRCTLR1, edc_tmp);
/* Set bit 9 of ECMERRTGTR41 to 0 and bit 9 of
ECMERRCTLR41 to 1. (Error of AXI-Bus ECM of VDSP hierarchy) */
edc_tmp = mem_read32(ECMERRTGTR41);
edc_tmp &= ~(0x1U << 9U);
ecm_write(ECMERRTGTR41, edc_tmp);
edc_tmp = mem_read32(ECMERRCTLR41);
edc_tmp |= (0x1U << 9U);
ecm_write(ECMERRCTLR41, edc_tmp);
axi_timeout_setting();
/* Lock the ECM registers */
ecm_lock();
}
void edc_vram_enable(void)
{
uint32_t edc_tmp;
/* Unlock the write protect of ECM registers */
ecm_unlock();
/* (1) Set the corresponding bits of the ECMERRTGTR and ECMERRCTLR registers
to inform the external device of the error via the ERROROUT# pin. */
/* Set bit 30 of ECMERRTGTR7 to 0 and bit 30 of ECMERRCTLR7 to 1.
(RT-VRAM edc 1-bit error) */
edc_tmp = mem_read32(ECMERRTGTR7);
edc_tmp &= ~(0x1U << 30U);
ecm_write(ECMERRTGTR7, edc_tmp);
edc_tmp = mem_read32(ECMERRCTLR7);
edc_tmp |= (0x1U << 30U);
ecm_write(ECMERRCTLR7, edc_tmp);
/* Set bit 29 of ECMERRTGTR7 to 0 and bit 29 of ECMERRCTLR7 to 1.
(RT-VRAM edc multi-bit error) */
edc_tmp = mem_read32(ECMERRTGTR7);
edc_tmp &= ~(0x1U << 29U);
ecm_write(ECMERRTGTR7, edc_tmp);
edc_tmp = mem_read32(ECMERRCTLR7);
edc_tmp |= (0x1U << 29U);
ecm_write(ECMERRCTLR7, edc_tmp);
/* Set bit 19 of ECMERRTGTR17 to 0 and bit 19 of ECMERRCTLR17 to 1.
(RT-VRAM edc 1-bit error) */
edc_tmp = mem_read32(ECMERRTGTR17);
edc_tmp &= ~(0x1U << 19U);
ecm_write(ECMERRTGTR17, edc_tmp);
edc_tmp = mem_read32(ECMERRCTLR17);
edc_tmp |= (0x1U << 19U);
ecm_write(ECMERRCTLR17, edc_tmp);
/* Set bit 18 of ECMERRTGTR17 to 0 and bit 18 of ECMERRCTLR17 to 1.
(RT-VRAM edc multi-bit error) */
edc_tmp = mem_read32(ECMERRTGTR17);
edc_tmp &= ~(0x1U << 18U);
ecm_write(ECMERRTGTR17, edc_tmp);
edc_tmp = mem_read32(ECMERRCTLR17);
edc_tmp |= (0x1U << 18U);
ecm_write(ECMERRCTLR17, edc_tmp);
/* Set bit 0 of EDC_CFG to 1. (EDC Error Control) */
edc_tmp = mem_read32(EDC_CFG);
edc_tmp |= (0x1U << 0U);
mem_write32(EDC_CFG, edc_tmp);
/* Lock the ECM registers */
ecm_lock();
}
static void axi_timeout_setting(void)
{
uint32_t reg;
uint32_t loop;
REMAP_TABLE axi_remap_tbl[AXI_SICREMAP_NUM] = {
{RGID_BASE1, 0U},
{RGID_BASE2, 0U},
{RGID_BASE3, 0U},
{RGID_BASE4, 0U},
{RGID_BASE5, 0U},
};
/* Register of AXI Base */
for (loop = 0U; loop < AXI_SICREMAP_NUM; loop++)
{
remap_register(axi_remap_tbl[loop].base_addr, &axi_remap_tbl[loop].rmp_addr);
}
/* Set the COUNTER bits of the FDT_* registers for all safety-related modules to minimum value with 1ms or more. */
for (loop = 0U; loop < FDT_REG_MAX; loop++)
{
reg = mem_read32(g_fdt_tbl[loop].reg_addr);
reg &= ~(FDT_COUNTER_MASK);
reg |= g_fdt_tbl[loop].value;
mem_write32(g_fdt_tbl[loop].reg_addr, reg);
INFO("FDT[%d] =\t0x%08x \tsetting value = 0x%08x\n", loop, mem_read32(g_fdt_tbl[loop].reg_addr), g_fdt_tbl[loop].value);
}
for(loop = 0U; loop < INTEN_REG_MAX; loop++)
{
/* Set access protection setting value of Region ID (AXI bus of Region ID register) */
mem_write32(g_inten_tbl[loop].reg_addr, g_inten_tbl[loop].value);
INFO("INTEN[%d] =\t0x%08x \tsetting value = 0x%08x\n", loop, mem_read32(g_inten_tbl[loop].reg_addr), g_inten_tbl[loop].value);
}
/* Unregister of AXI Base */
for (loop = 0U; loop < AXI_SICREMAP_NUM; loop++)
{
remap_unregister(axi_remap_tbl[loop].rmp_addr);
}
wdt_restart();
}
#endif /* ECM_ENABLE == 1 */

125
Src/0_Tool/Gen4_R-Car_IPL/SDK/v3_46_0/Gen4_ICUMX_Loader/ip/ddr/v4h/lpddr5/ecc_enable_v4h.h Normal file
View File

@@ -0,0 +1,125 @@
/*******************************************************************************
* Copyright (c) 2022-2025 Renesas Electronics Corporation. All rights reserved.
*
* RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY
*
* This software is provided as reference/sample code under the license
* agreement between Renesas Electronics Corporation and licensee (the
* "License Agreement") and shall be treated as specified in the License
* Agreement.
* These instructions, statements, and software are the confidential
* information of Renesas Electronics Corporation. They must be used and
* modified solely for the purpose for which it was furnished by Renesas
* Electronics Corporation. All or part of these instructions, statements and
* software must not be reproduced nor disclosed to any third party in any
* form, unless permitted by the License Agreement.
*
* THIS SOFTWARE IS PROVIDED BY RENESAS ELEOCTRONICS CORPORATION "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
* SATISFACTORY QUALITY, ACCURACY, TITLE AND NON-INFRINGEMENT ARE DISCLAIMED.
* IN NO EVENT SHALL RENESAS ELECTRONICS CORPORATION BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, PUNITIVE, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
* DAMAGE.
******************************************************************************/
/*******************************************************************************
* DESCRIPTION : ECC driver header
******************************************************************************/
#ifndef ECC_PROTECT
#define ECC_PROTECT
#include "remap_register.h"
/* DBSC registers */
#if defined(__RH850G3K__)
#include "mem_io.h"
#include "log.h"
#define DBSC_D_BASE (BASE_DBSC_ADDR + 0x14000U) /* forV4H DBSC0 clk_dbsc region DBSC1_D_BASE = 0xE67A8000U */
#define DBSC_A_BASE (BASE_DBSC_ADDR) /* forV4H DBSC0 clk_axim region DBSC1_A_BASE = 0xE6798000U */
#define ECM_BASE (BASE_ECC_ADDR)
#else
#include <mmio.h>
#include <debug.h>
#define DBSC_D_BASE (0xE67A4000U) /* forV4H DBSC0 clk_dbsc region DBSC1_D_BASE = 0xE67A8000U */
#define DBSC_A_BASE (0xE6790000U) /* forV4H DBSC0 clk_axim region DBSC1_A_BASE = 0xE6798000U */
#define ECM_BASE (0xE6250000U)
#endif/* defined(__RH850G3K__) */
#define RTVRAM_REG_BASE (0xFFEC0000U)
void edc_axi_enable(void);
void edc_vram_enable(void);
#define DB0SYSCNT0 (DBSC_D_BASE + 0x0100U)
#define DB0SYSCNT0A (DBSC_A_BASE + 0x0100U)
#define DB1SYSCNT0 (DB0SYSCNT0 + 0x4000U)
#define DB1SYSCNT0A (DB0SYSCNT0A + 0x8000U)
#define DBSC_DBACEN0 (DBSC_A_BASE + 0x0200U)
#define DBSC_DBACEN1 (DBSC_DBACEN0 + 0x8000U)
#define ECMWACNTR (ECM_BASE + 0x0A04U)
#define ECMWPCNTR (ECM_BASE + 0x0A00U)
#define ECMERRTGTR0 (ECM_BASE + 0x0200U)
#define ECMERRCTLR0 (ECM_BASE + 0x0000U)
#define ECMERRTGTR1 (ECM_BASE + 0x0200U + 0x4U * 1U)
#define ECMERRCTLR1 (ECM_BASE + 0x0000U + 0x4U * 1U)
#define ECMERRTGTR7 (ECM_BASE + 0x0200U + 0x4U * 7U)
#define ECMERRCTLR7 (ECM_BASE + 0x0000U + 0x4U * 7U)
#define ECMERRTGTR17 (ECM_BASE + 0x0200U + 0x4U * 17U)
#define ECMERRCTLR17 (ECM_BASE + 0x0000U + 0x4U * 17U)
#define ECMERRTGTR39 (ECM_BASE + 0x0200U + 0x4U * 39U)
#define ECMERRCTLR39 (ECM_BASE + 0x0000U + 0x4U * 39U)
#define ECMERRTGTR41 (ECM_BASE + 0x0200U + 0x4U * 41U)
#define ECMERRCTLR41 (ECM_BASE + 0x0000U + 0x4U * 41U)
#define DB0FSCONF00A (DBSC_A_BASE + 0x7640U)
#define DB1FSCONF00A (DB0FSCONF00A + 0x8000U)
#define DB0FSCONF01A (DBSC_A_BASE + 0x7644U)
#define DB1FSCONF01A (DB0FSCONF01A + 0x8000U)
#define DB0FSCONF02A (DBSC_A_BASE + 0x7648U)
#define DB1FSCONF02A (DB0FSCONF02A + 0x8000U)
#define DB0FSCTRL01A (DBSC_A_BASE + 0x7604U)
#define DB1FSCTRL01A (DB0FSCTRL01A + 0x8000U)
#define DB0FSSTAT01A (DBSC_A_BASE + 0x7684U)
#define DB1FSSTAT01A (DB0FSSTAT01A + 0x8000U)
#define DB0FSSTAT00A (DBSC_A_BASE + 0x7680U)
#define DB1FSSTAT00A (DB0FSSTAT00A + 0x8000U)
#define DB0FSINTENB02A (DBSC_A_BASE + 0x7088U)
#define DB1FSINTENB02A (DB0FSINTENB02A + 0x8000U)
#define DB0FSINTENB04A (DBSC_A_BASE + 0x7090U)
#define DB1FSINTENB04A (DB0FSINTENB04A + 0x8000U)
#define DB0FSDRAMECCAREA0 (DBSC_A_BASE + 0x7450U)
#define DB0FSDRAMECCAREA1 (DBSC_A_BASE + 0x7454U)
#define DB1FSDRAMECCAREA0 (DB0FSDRAMECCAREA0 + 0x8000U)
#define DB1FSDRAMECCAREA1 (DB0FSDRAMECCAREA1 + 0x8000U)
#define DB0FSCONFAXI0 (DBSC_A_BASE + 0x7400U)
#define DB1FSCONFAXI0 (DB0FSCONFAXI0 + 0x8000U)
#define EDC_CFG (RTVRAM_REG_BASE + 0x4110U)
/********************* Set by the user *********************/
/* The row address of ECC Protection Area Size for memory rank 0/1 of DBSC0/1 */
#define ECC_PROT_SIZE00 (0x1000U)
#define ECC_PROT_SIZE01 (0x1000U)
#define ECC_PROT_SIZE10 (0x1000U)
#define ECC_PROT_SIZE11 (0x1000U)
/* Start and End row address of ECC Protection area for rank0 of DBSC0/1 */
#define START_ECC_INIT_AREA00 (0x00000000U)
#define START_ECC_INIT_AREA10 (0x00000000U)
#define END_ECC_INIT_AREA00 (0x00000FFFU)
#define END_ECC_INIT_AREA10 (0x00000FFFU)
/* Start and End row address of ECC Protection area for rank1 of DBSC0/1 */
#define START_ECC_INIT_AREA01 (0x00000000U)
#define START_ECC_INIT_AREA11 (0x00000000U)
#define END_ECC_INIT_AREA01 (0x00000FFFU)
#define END_ECC_INIT_AREA11 (0x00000FFFU)
/*********** Other settings cannot be changed ***************/
#endif/* ECC_PROTECT */

531
Src/0_Tool/Gen4_R-Car_IPL/SDK/v3_46_0/Gen4_ICUMX_Loader/ip/ddr/v4h/lpddr5/ecm_enable_v4h.c Normal file
View File

@@ -0,0 +1,531 @@
/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright 2025 Renesas Electronics Corporation All rights reserved.
*******************************************************************************/
/*******************************************************************************
* DESCRIPTION : ECM initialize function
******************************************************************************/
/******************************************************************************
* @file ecm_enable_v4h.c
* - Version : 0.01
* @brief ECM setting.
* .
*****************************************************************************/
/******************************************************************************
* History : DD.MM.YYYY Version Description
* : 29.01.2025 0.01 First Release
*****************************************************************************/
#include <stdint.h>
#include "ecm_enable_v4h.h"
#if (ECM_ERROR_ENABLE == 1)
#include "log.h"
#endif /* ECM_ERROR_ENABLE == 1 */
#if ((ECM_ERROR_ENABLE == 1) || (ECM_ENABLE == 1))
#include "ecc_enable_v4h.h"
#include "mem_io.h"
#endif /* (ECM_ERROR_ENABLE == 1) || (ECM_ENABLE == 1) */
#if (ECM_ERROR_ENABLE == 1)
#define TYPE1_ECM_REG_MAX (13U)
#define TYPE2_ECM_REG_MAX (22U)
#define TYPE3_ECM_CTLREG_MAX (1U)
#define TYPE3_ECM_TGTREG_MAX (2U)
typedef struct{
uint32_t phys_addr; /* Physical address of ECM registers. */
uint32_t value; /* Setting value of ECM registers. */
} ECM_ERROR_TABLE;
#endif /* ECM_ERROR_ENABLE == 1 */
#if ((ECM_ERROR_ENABLE == 1) || (ECM_ENABLE == 1))
void ecm_unlock(void)
{
mem_write32(ECMWPCNTR, 0xACCE0001U);
}
void ecm_write(uint32_t adr, uint32_t val)
{
mem_write32(ECMWACNTR, ((0xACCEU << 16U) | (adr & 0xffffU)));
mem_write32(adr, val);
}
void ecm_lock(void)
{
mem_write32(ECMWPCNTR, 0xACCE0000U);
}
#endif /* (ECM_ERROR_ENABLE == 1) || (ECM_ENABLE == 1) */
#if (ECM_ERROR_ENABLE == 1)
void ecm_init_setting(void)
{
uint32_t reg;
uint32_t loop;
const ECM_ERROR_TABLE ecmerrctlr_type1_tbl[TYPE1_ECM_REG_MAX] = {
[0] = {0xFD850000U, 0x00381000U}, /* ECMERRCTLR0 */
[1] = {0xFD850004U, 0xA400C000U}, /* ECMERRCTLR1 */
/* Skip ECMERRCTLR2 setting */
/* Skip ECMERRCTLR3 setting */
/* Skip ECMERRCTLR4 setting */
/* Skip ECMERRCTLR5 setting */
[2] = {0xFD850018U, 0xCC000000U}, /* ECMERRCTLR6 */
[3] = {0xFD85001CU, 0x0C000000U}, /* ECMERRCTLR7 */
/* Skip ECMERRCTLR8 setting */
/* Skip ECMERRCTLR9 setting */
/* Skip ECMERRCTLR10 setting */
/* Skip ECMERRCTLR11 setting */
/* Skip ECMERRCTLR12 setting */
/* Skip ECMERRCTLR13 setting */
/* Skip ECMERRCTLR14 setting */
/* Skip ECMERRCTLR15 setting */
/* Skip ECMERRCTLR16 setting */
[4] = {0xFD850044U, 0x2D000000U}, /* ECMERRCTLR17 */
[5] = {0xFD850048U, 0x0EC0003FU}, /* ECMERRCTLR18 */
[6] = {0xFD85004CU, 0x00FFFF08U}, /* ECMERRCTLR19 */
[7] = {0xFD850050U, 0x0000001EU}, /* ECMERRCTLR20 */
[8] = {0xFD850054U, 0x9F800000U}, /* ECMERRCTLR21 */
/* Skip ECMERRCTLR22 setting */
/* Skip ECMERRCTLR23 setting */
/* Skip ECMERRCTLR24 setting */
/* Skip ECMERRCTLR25 setting */
/* Skip ECMERRCTLR26 setting */
/* Skip ECMERRCTLR27 setting */
/* Skip ECMERRCTLR28 setting */
/* Skip ECMERRCTLR29 setting */
/* Skip ECMERRCTLR30 setting */
/* Skip ECMERRCTLR31 setting */
/* Skip ECMERRCTLR32 setting */
/* Skip ECMERRCTLR33 setting */
/* Skip ECMERRCTLR34 setting */
[9] = {0xFD85008CU, 0x300003C0U}, /* ECMERRCTLR35 */
/* Skip ECMERRCTLR36 setting */
/* Skip ECMERRCTLR37 setting */
[10] = {0xFD850098U, 0x33300054U}, /* ECMERRCTLR38 */
/* Skip ECMERRCTLR39 setting */
/* Skip ECMERRCTLR40 setting */
[11] = {0xFD8500A4U, 0x01000880U}, /* ECMERRCTLR41 */
[12] = {0xFD8500A8U, 0x00040020U}, /* ECMERRCTLR42 */
};
const ECM_ERROR_TABLE ecmerrtgtr_type1_tbl[TYPE1_ECM_REG_MAX] = {
[0] = {0xFD850200U, 0x00381000U}, /* ECMERRTGTR0 */
[1] = {0xFD850204U, 0xA400C000U}, /* ECMERRTGTR1 */
/* Skip ECMERRTGTR2 setting */
/* Skip ECMERRTGTR3 setting */
/* Skip ECMERRTGTR4 setting */
/* Skip ECMERRTGTR5 setting */
[2] = {0xFD850218U, 0xCC000000U}, /* ECMERRTGTR6 */
[3] = {0xFD85021CU, 0x0C000000U}, /* ECMERRTGTR7 */
/* Skip ECMERRTGTR8 setting */
/* Skip ECMERRTGTR9 setting */
/* Skip ECMERRTGTR10 setting */
/* Skip ECMERRTGTR11 setting */
/* Skip ECMERRTGTR12 setting */
/* Skip ECMERRTGTR13 setting */
/* Skip ECMERRTGTR14 setting */
/* Skip ECMERRTGTR15 setting */
/* Skip ECMERRTGTR16 setting */
[4] = {0xFD850244U, 0x2D000000U}, /* ECMERRTGTR17 */
[5] = {0xFD850248U, 0x0EC0003FU}, /* ECMERRTGTR18 */
[6] = {0xFD85024CU, 0x00FFFF08U}, /* ECMERRTGTR19 */
[7] = {0xFD850250U, 0x0000001EU}, /* ECMERRTGTR20 */
[8] = {0xFD850254U, 0x9F800000U}, /* ECMERRTGTR21 */
/* Skip ECMERRTGTR22 setting */
/* Skip ECMERRTGTR23 setting */
/* Skip ECMERRTGTR24 setting */
/* Skip ECMERRTGTR25 setting */
/* Skip ECMERRTGTR26 setting */
/* Skip ECMERRTGTR27 setting */
/* Skip ECMERRTGTR28 setting */
/* Skip ECMERRTGTR29 setting */
/* Skip ECMERRTGTR30 setting */
/* Skip ECMERRTGTR31 setting */
/* Skip ECMERRTGTR32 setting */
/* Skip ECMERRTGTR33 setting */
/* Skip ECMERRTGTR34 setting */
[9] = {0xFD85028CU, 0x300003C0U}, /* ECMERRTGTR35 */
/* Skip ECMERRTGTR36 setting */
/* Skip ECMERRTGTR37 setting */
[10] = {0xFD850298U, 0x33300054U}, /* ECMERRTGTR38 */
/* Skip ECMERRTGTR39 setting */
/* Skip ECMERRTGTR40 setting */
[11] = {0xFD8502A4U, 0x01000880U}, /* ECMERRTGTR41 */
[12] = {0xFD8502A8U, 0x00040020U}, /* ECMERRTGTR42 */
};
const ECM_ERROR_TABLE ecmerrctlr_type2_tbl[TYPE2_ECM_REG_MAX] = {
[0] = {0xFD850000U, 0x4000000FU}, /* ECMERRCTLR0 */
[1] = {0xFD850004U, 0x1C004000U}, /* ECMERRCTLR1 */
[2] = {0xFD850008U, 0xFFFFFFFFU}, /* ECMERRCTLR2 */
[3] = {0xFD85000CU, 0xFFFFFFFFU}, /* ECMERRCTLR3 */
[4] = {0xFD850010U, 0xFFFFFFFFU}, /* ECMERRCTLR4 */
[5] = {0xFD850014U, 0xC1FFFFFFU}, /* ECMERRCTLR5 */
[6] = {0xFD850018U, 0x15000A80U}, /* ECMERRCTLR6 */
[7] = {0xFD85001CU, 0x00803481U}, /* ECMERRCTLR7 */
/* Skip ECMERRCTLR8 setting */
/* Skip ECMERRCTLR9 setting */
/* Skip ECMERRCTLR10 setting */
/* Skip ECMERRCTLR11 setting */
/* Skip ECMERRCTLR12 setting */
/* Skip ECMERRCTLR13 setting */
/* Skip ECMERRCTLR14 setting */
/* Skip ECMERRCTLR15 setting */
[8] = {0xFD850040U, 0x00003E9FU}, /* ECMERRCTLR16 */
[9] = {0xFD850044U, 0x00938060U}, /* ECMERRCTLR17 */
[10] = {0xFD850048U, 0x003C1FC0U}, /* ECMERRCTLR18 */
[11] = {0xFD85004CU, 0xFF0000F0U}, /* ECMERRCTLR19 */
[12] = {0xFD850050U, 0x02222220U}, /* ECMERRCTLR20 */
[13] = {0xFD850054U, 0x0061BE0FU}, /* ECMERRCTLR21 */
/* Skip ECMERRCTLR22 setting */
/* Skip ECMERRCTLR23 setting */
/* Skip ECMERRCTLR24 setting */
/* Skip ECMERRCTLR25 setting */
/* Skip ECMERRCTLR26 setting */
/* Skip ECMERRCTLR27 setting */
/* Skip ECMERRCTLR28 setting */
/* Skip ECMERRCTLR29 setting */
/* Skip ECMERRCTLR30 setting */
/* Skip ECMERRCTLR31 setting */
[14] = {0xFD850080U, 0x03E9043BU}, /* ECMERRCTLR32 */
[15] = {0xFD850084U, 0x03E9043BU}, /* ECMERRCTLR33 */
/* Skip ECMERRCTLR34 setting */
[16] = {0xFD85008CU, 0xC3F00C00U}, /* ECMERRCTLR35 */
[17] = {0xFD850090U, 0xFFFFFFFFU}, /* ECMERRCTLR36 */
/* Skip ECMERRCTLR37 setting */
[18] = {0xFD850098U, 0x00000002U}, /* ECMERRCTLR38 */
/* Skip ECMERRCTLR39 setting */
[19] = {0xFD8500A0U, 0x000067FEU}, /* ECMERRCTLR40 */
[20] = {0xFD8500A4U, 0x20010000U}, /* ECMERRCTLR41 */
[21] = {0xFD8500A8U, 0x00800400U}, /* ECMERRCTLR42 */
};
const ECM_ERROR_TABLE ecmerrtgtr_type2_tbl[TYPE2_ECM_REG_MAX] = {
[0] = {0xFD850200U, 0x4000000FU}, /* ECMERRTGTR0 */
[1] = {0xFD850204U, 0x1C004000U}, /* ECMERRTGTR1 */
[2] = {0xFD850208U, 0xFFFFFFFFU}, /* ECMERRTGTR2 */
[3] = {0xFD85020CU, 0xFFFFFFFFU}, /* ECMERRTGTR3 */
[4] = {0xFD850210U, 0xFFFFFFFFU}, /* ECMERRTGTR4 */
[5] = {0xFD850214U, 0xC1FFFFFFU}, /* ECMERRTGTR5 */
[6] = {0xFD850218U, 0x15000A80U}, /* ECMERRTGTR6 */
[7] = {0xFD85021CU, 0x00803481U}, /* ECMERRTGTR7 */
/* Skip ECMERRTGTR8 setting */
/* Skip ECMERRTGTR9 setting */
/* Skip ECMERRTGTR10 setting */
/* Skip ECMERRTGTR11 setting */
/* Skip ECMERRTGTR12 setting */
/* Skip ECMERRTGTR13 setting */
/* Skip ECMERRTGTR14 setting */
/* Skip ECMERRTGTR15 setting */
[8] = {0xFD850240U, 0x00003E9FU}, /* ECMERRTGTR16 */
[9] = {0xFD850244U, 0x00938060U}, /* ECMERRTGTR17 */
[10] = {0xFD850248U, 0x003C1FC0U}, /* ECMERRTGTR18 */
[11] = {0xFD85024CU, 0xFF0000F0U}, /* ECMERRTGTR19 */
[12] = {0xFD850250U, 0x02222220U}, /* ECMERRTGTR20 */
[13] = {0xFD850254U, 0x0061BE0FU}, /* ECMERRTGTR21 */
/* Skip ECMERRTGTR22 setting */
/* Skip ECMERRTGTR23 setting */
/* Skip ECMERRTGTR24 setting */
/* Skip ECMERRTGTR25 setting */
/* Skip ECMERRTGTR26 setting */
/* Skip ECMERRTGTR27 setting */
/* Skip ECMERRTGTR28 setting */
/* Skip ECMERRTGTR29 setting */
/* Skip ECMERRTGTR30 setting */
/* Skip ECMERRTGTR31 setting */
[14] = {0xFD850280U, 0x03E9043BU}, /* ECMERRTGTR32 */
[15] = {0xFD850284U, 0x03E9043BU}, /* ECMERRTGTR33 */
/* Skip ECMERRTGTR34 setting */
[16] = {0xFD85028CU, 0xC3F00C00U}, /* ECMERRTGTR35 */
[17] = {0xFD850290U, 0xFFFFFFFFU}, /* ECMERRTGTR36 */
/* Skip ECMERRTGTR37 setting */
[18] = {0xFD850298U, 0x00000002U}, /* ECMERRTGTR38 */
/* Skip ECMERRTGTR39 setting */
[19] = {0xFD8502A0U, 0x000067FEU}, /* ECMERRTGTR40 */
[20] = {0xFD8502A4U, 0x20010000U}, /* ECMERRTGTR41 */
[21] = {0xFD8502A8U, 0x00800400U}, /* ECMERRTGTR42 */
};
const ECM_ERROR_TABLE ecmerrctlr_type3_tbl[TYPE3_ECM_CTLREG_MAX] = {
/* Skip ECMERRCTLR0 setting */
/* Skip ECMERRCTLR1 setting */
/* Skip ECMERRCTLR2 setting */
/* Skip ECMERRCTLR3 setting */
/* Skip ECMERRCTLR4 setting */
/* Skip ECMERRCTLR5 setting */
/* Skip ECMERRCTLR6 setting */
/* Skip ECMERRCTLR7 setting */
/* Skip ECMERRCTLR8 setting */
/* Skip ECMERRCTLR9 setting */
/* Skip ECMERRCTLR10 setting */
/* Skip ECMERRCTLR11 setting */
/* Skip ECMERRCTLR12 setting */
/* Skip ECMERRCTLR13 setting */
/* Skip ECMERRCTLR14 setting */
/* Skip ECMERRCTLR15 setting */
[0] = {0xFD850040U, 0x3FFFC000U}, /* ECMERRCTLR16 */
/* Skip ECMERRCTLR17 setting */
/* Skip ECMERRCTLR18 setting */
/* Skip ECMERRCTLR19 setting */
/* Skip ECMERRCTLR20 setting */
/* Skip ECMERRCTLR21 setting */
/* Skip ECMERRCTLR22 setting */
/* Skip ECMERRCTLR23 setting */
/* Skip ECMERRCTLR24 setting */
/* Skip ECMERRCTLR25 setting */
/* Skip ECMERRCTLR26 setting */
/* Skip ECMERRCTLR27 setting */
/* Skip ECMERRCTLR28 setting */
/* Skip ECMERRCTLR29 setting */
/* Skip ECMERRCTLR30 setting */
/* Skip ECMERRCTLR31 setting */
/* Skip ECMERRCTLR32 setting */
/* Skip ECMERRCTLR33 setting */
/* Skip ECMERRCTLR34 setting */
/* Skip ECMERRCTLR35 setting */
/* Skip ECMERRCTLR36 setting */
/* Skip ECMERRCTLR37 setting */
/* Skip ECMERRCTLR38 setting */
/* Skip ECMERRCTLR39 setting */
/* Skip ECMERRCTLR40 setting */
/* Skip ECMERRCTLR41 setting */
/* Skip ECMERRCTLR42 setting */
};
const ECM_ERROR_TABLE ecmerrtgtr_type3_tbl[TYPE3_ECM_TGTREG_MAX] = {
[0] = {0xFD850200U, 0x80000000U}, /* ECMERRTGTR0 */
/* Skip ECMERRTGTR1 setting */
/* Skip ECMERRTGTR2 setting */
/* Skip ECMERRTGTR3 setting */
/* Skip ECMERRTGTR4 setting */
/* Skip ECMERRTGTR5 setting */
/* Skip ECMERRTGTR6 setting */
/* Skip ECMERRTGTR7 setting */
/* Skip ECMERRTGTR8 setting */
/* Skip ECMERRTGTR9 setting */
/* Skip ECMERRTGTR10 setting */
/* Skip ECMERRTGTR11 setting */
/* Skip ECMERRTGTR12 setting */
/* Skip ECMERRTGTR13 setting */
/* Skip ECMERRTGTR14 setting */
/* Skip ECMERRTGTR15 setting */
[1] = {0xFD850240U, 0x3FFFC000U}, /* ECMERRTGTR16 */
/* Skip ECMERRTGTR17 setting */
/* Skip ECMERRTGTR18 setting */
/* Skip ECMERRTGTR19 setting */
/* Skip ECMERRTGTR20 setting */
/* Skip ECMERRTGTR21 setting */
/* Skip ECMERRTGTR22 setting */
/* Skip ECMERRTGTR23 setting */
/* Skip ECMERRTGTR24 setting */
/* Skip ECMERRTGTR25 setting */
/* Skip ECMERRTGTR26 setting */
/* Skip ECMERRTGTR27 setting */
/* Skip ECMERRTGTR28 setting */
/* Skip ECMERRTGTR29 setting */
/* Skip ECMERRTGTR30 setting */
/* Skip ECMERRTGTR31 setting */
/* Skip ECMERRTGTR32 setting */
/* Skip ECMERRTGTR33 setting */
/* Skip ECMERRTGTR34 setting */
/* Skip ECMERRTGTR35 setting */
/* Skip ECMERRTGTR36 setting */
/* Skip ECMERRTGTR37 setting */
/* Skip ECMERRTGTR38 setting */
/* Skip ECMERRTGTR39 setting */
/* Skip ECMERRTGTR40 setting */
/* Skip ECMERRTGTR41 setting */
/* Skip ECMERRTGTR42 setting */
};
/* Unlock the write protect of ECM registers */
ecm_unlock();
NOTICE("ECMERRCTLR and ECMERRTGTR register initial setting.\n");
/* For the initial setting flow for Type-1, please refer to the following
* section in the "SAN(Safety Application Note)."
* Section 4.1.2.5 : (1)
* Section 4.1.4.5 : (1)
* Section 4.12.1.5 : (1)
* Section 4.13.1.5 : (1)
* Section 4.14.5 : (1)
* Section 4.16.5 : (1)
* Section 4.18.5 : (1)
* Section 4.2.7.5 : (1)
* Section 4.2.9.5 : (1)
* Section 4.23.5 : (1)
* Section 4.3.11.5 : (1)
* Section 4.3.12.5 : (1)
* Section 4.3.14.5 : (1)
* Section 4.3.19.5 : (1)
* Section 4.3.21.5 : (1)
* Section 4.4.14.5 : (1)
* Section 4.4.16.5 : (3)
* Section 4.4.18.5 : (1)
* Section 4.4.20.5 : (1)
* Section 4.4.3.5 : (1)
* Section 4.4.4.5 : (1)
* Section 4.4.6.5 : (1)
* Section 4.4.7.5 : (1)
* Section 4.4.9.5 : (1)
* Section 4.5.1.5 : (1)
* Section 4.7.1.5 : (1)
* Section 4.7.10.5 : (1)
* Section 4.7.3.5 : (1)
* Section 4.7.4.5 : (1)
* Section 4.7.7.5 : (1)
* Section 4.7.8.5 : (1)
* Section 5.6.5 : (1)
* Section 5.8.1.5 : (1)
*/
for (loop = 0U; loop < TYPE1_ECM_REG_MAX; loop++)
{
reg = mem_read32(ecmerrctlr_type1_tbl[loop].phys_addr);
reg |= (ecmerrctlr_type1_tbl[loop].value);
ecm_write(ecmerrctlr_type1_tbl[loop].phys_addr, reg);
INFO("[Type-1]ECMERRCTLR[\t%d]\t(0x%08x) =\t0x%08x \tsetting value = 0x%08x\n",
loop,
ecmerrctlr_type1_tbl[loop].phys_addr,
mem_read32(ecmerrctlr_type1_tbl[loop].phys_addr),
ecmerrctlr_type1_tbl[loop].value);
}
for (loop = 0U; loop < TYPE1_ECM_REG_MAX; loop++)
{
reg = mem_read32(ecmerrtgtr_type1_tbl[loop].phys_addr);
reg &= ~(ecmerrtgtr_type1_tbl[loop].value);
ecm_write(ecmerrtgtr_type1_tbl[loop].phys_addr, reg);
INFO("[Type-1]ECMERRTGTR[\t%d]\t(0x%08x) =\t0x%08x \tsetting value = 0x%08x\n",
loop,
ecmerrtgtr_type1_tbl[loop].phys_addr,
mem_read32(ecmerrtgtr_type1_tbl[loop].phys_addr),
ecmerrtgtr_type1_tbl[loop].value);
}
/* For the initial setting flow for Type-2, please refer to the following
* section in the "SAN(Safety Application Note)."
* Section 4.1.1.5 : (1)
* Section 4.12.2.5 : (1)
* Section 4.12.3.5 : (1)
* Section 4.15.5 : (1)
* Section 4.16.5 : (1)
* Section 4.2.1.5 : (1)
* Section 4.2.10.5 : (1)
* Section 4.2.12.5 : (1)
* Section 4.2.2.5 : (1)
* Section 4.2.4.5 : (1)
* Section 4.2.8.5 : (1)
* Section 4.3.1.5 : (1)
* Section 4.3.10.5 : (1)
* Section 4.3.11.5 : (1)
* Section 4.3.12.5 : (1)
* Section 4.3.13.5 : (1)
* Section 4.3.15.5 : (1)
* Section 4.3.16.5 : (1)
* Section 4.3.2.5 : (1)
* Section 4.3.5.5 : (1)
* Section 4.3.7.5 : (1)
* Section 4.3.8.5 : (1)
* Section 4.4.10.5 : (1)
* Section 4.4.12.5 : (8)
* Section 4.4.13.5 : (1)
* Section 4.4.15.5 : (1)
* Section 4.4.2.5 : (1)
* Section 4.5.3.5 : (1)
* Section 4.6.5 : (1)
* Section 4.7.2.5 : (1)
* Section 5.11.5 : (1)
* Section 5.12.5 : (1)
* Section 5.13.5 : (1)
* Section 5.4.5 : (1)
* Section 5.8.2.5 : (1)
*/
for (loop = 0U; loop < TYPE2_ECM_REG_MAX; loop++)
{
/* Initial Setting Type-2 for ECMERRCTLR registers */
reg = mem_read32(ecmerrctlr_type2_tbl[loop].phys_addr);
reg |= (ecmerrctlr_type2_tbl[loop].value);
ecm_write(ecmerrctlr_type2_tbl[loop].phys_addr, reg);
INFO("[Type-2]ECMERRCTLR[\t%d]\t(0x%08x) =\t0x%08x \tsetting value = 0x%08x\n",
loop,
ecmerrctlr_type2_tbl[loop].phys_addr,
mem_read32(ecmerrctlr_type2_tbl[loop].phys_addr),
ecmerrctlr_type2_tbl[loop].value);
}
for (loop = 0U; loop < TYPE2_ECM_REG_MAX; loop++)
{
/* Initial Setting Type-2 for ECMERRTGTR registers */
reg = mem_read32(ecmerrtgtr_type2_tbl[loop].phys_addr);
reg &= ~(ecmerrtgtr_type2_tbl[loop].value);
ecm_write(ecmerrtgtr_type2_tbl[loop].phys_addr, reg);
INFO("[Type-2]ECMERRTGTR[\t%d]\t(0x%08x) =\t0x%08x \tsetting value = 0x%08x\n",
loop,
ecmerrtgtr_type2_tbl[loop].phys_addr,
mem_read32(ecmerrtgtr_type2_tbl[loop].phys_addr),
ecmerrtgtr_type2_tbl[loop].value);
}
/* For the initial setting flow for Type-3, please refer to the following
* section in the "SAN(Safety Application Note)."
* Section 4.19.1.5 : (3)
* Section 6.2.5 : (12)
*/
for (loop = 0U; loop < TYPE3_ECM_CTLREG_MAX; loop++)
{
/* Initial Setting Type-3 for ECMERRCTLR registers */
reg = mem_read32(ecmerrctlr_type3_tbl[loop].phys_addr);
reg |= (ecmerrctlr_type3_tbl[loop].value);
ecm_write(ecmerrctlr_type3_tbl[loop].phys_addr, reg);
INFO("[Type-3]ECMERRCTLR[\t%d]\t(0x%08x) =\t0x%08x \tsetting value = 0x%08x\n",
loop,
ecmerrctlr_type3_tbl[loop].phys_addr,
mem_read32(ecmerrctlr_type3_tbl[loop].phys_addr),
ecmerrctlr_type3_tbl[loop].value);
}
for (loop = 0U; loop < TYPE3_ECM_TGTREG_MAX; loop++)
{
/* Initial Setting Type-3 for ECMERRTGTR registers */
reg = mem_read32(ecmerrtgtr_type3_tbl[loop].phys_addr);
reg &= ~(ecmerrtgtr_type3_tbl[loop].value);
ecm_write(ecmerrtgtr_type3_tbl[loop].phys_addr, reg);
INFO("[Type-3]ECMERRTGTR[\t%d]\t(0x%08x) =\t0x%08x \tsetting value = 0x%08x\n",
loop,
ecmerrtgtr_type3_tbl[loop].phys_addr,
mem_read32(ecmerrtgtr_type3_tbl[loop].phys_addr),
ecmerrtgtr_type3_tbl[loop].value);
}
/* Lock the ECM registers */
ecm_lock();
}
/* End of function ecm_init_setting(void) */
#endif /* ECM_ERROR_ENABLE == 1 */

42
Src/0_Tool/Gen4_R-Car_IPL/SDK/v3_46_0/Gen4_ICUMX_Loader/ip/ddr/v4h/lpddr5/ecm_enable_v4h.h Normal file
View File

@@ -0,0 +1,42 @@
/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright 2025 Renesas Electronics Corporation All rights reserved.
*******************************************************************************/
/*******************************************************************************
* DESCRIPTION : ECM driver header
******************************************************************************/
#ifndef ECM_ENABLE_V4H
#define ECM_ENABLE_V4H
#if ((ECM_ERROR_ENABLE == 1) || (ECM_ENABLE == 1))
void ecm_unlock(void);
void ecm_write(uint32_t adr, uint32_t val);
void ecm_lock(void);
#endif /* (ECM_ERROR_ENABLE == 1) || (ECM_ENABLE == 1) */
#if (ECM_ERROR_ENABLE == 1)
void ecm_init_setting(void);
#endif /* ECM_ERROR_ENABLE == 1 */
#endif/* ECM_ENABLE_V4H */

302
Src/0_Tool/Gen4_R-Car_IPL/SDK/v3_46_0/Gen4_ICUMX_Loader/ip/ddr/v4m/lpddr5/boot_init_dram_regdef.h Normal file
View File

@@ -0,0 +1,302 @@
/*******************************************************************************
* Copyright (c) 2015-2022 Renesas Electronics Corporation. All rights reserved.
*
* RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY
*
* This software is provided as reference/sample code under the license
* agreement between Renesas Electronics Corporation and licensee (the
* "License Agreement") and shall be treated as specified in the License
* Agreement.
* These instructions, statements, and software are the confidential
* information of Renesas Electronics Corporation. They must be used and
* modified solely for the purpose for which it was furnished by Renesas
* Electronics Corporation. All or part of these instructions, statements and
* software must not be reproduced nor disclosed to any third party in any
* form, unless permitted by the License Agreement.
*
* THIS SOFTWARE IS PROVIDED BY RENESAS ELEOCTRONICS CORPORATION "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
* SATISFACTORY QUALITY, ACCURACY, TITLE AND NON-INFRINGEMENT ARE DISCLAIMED.
* IN NO EVENT SHALL RENESAS ELECTRONICS CORPORATION BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, PUNITIVE, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
* DAMAGE.
******************************************************************************/
#if defined(__RH850G3K__)
#include "remap_register.h"
#endif
#define RCAR_DDR_VERSION "rev.0.08rc7"
#define DRAM_CH_CNT 0x04
#define SLICE_CNT 0x02
#define CS_CNT 0x02
/* for pll setting */
#define CLK_DIV(a, diva, b, divb) (((a) * (divb)) / ((b) * (diva)))
#define CLK_MUL(a, diva, b, divb) (((a) * (b)) / ((diva) * (divb)))
/* for ddr density setting */
#define DBMEMCONF_REG(d3, row, BG, bank, col, dw) (((d3) << 30) | ((row) << 24) | ((BG) << 20) | ((bank) << 16) | ((col) << 8) | (dw))
#define DBMEMCONF_REGD(density) (DBMEMCONF_REG((density) % 2, ((density) + 1) / 2 + (28 - 2 - 2 - 10 - 1), 2, 2, 10, 1)) /* 16bit */
#define DBMEMCONF_VAL(ch,cs) (DBMEMCONF_REGD(DBMEMCONF_DENS(ch, cs)))
/* system registers : CPG */
#define CPG_FRQCRD_KICK_BIT (1U << 31)
#define CPG_PLL3CR0_KICK_BIT (1U << 31)
#define CPG_PLLECR_PLL3E_BIT (1U << 3)
#define CPG_PLLECR_PLL3ST_BIT (1U << 11)
#if defined(__RH850G3K__)
#define CPG_BASE (BASE_CPG_ADDR)
#else
#define CPG_BASE (0xE6150000U)
#endif
#define CPG_CPGWPR (CPG_BASE + 0x0000U)
#define CPG_CPGWPCR (CPG_BASE + 0x0004U)
#define CPG_FRQCRA (CPG_BASE + 0x0800U)
#define CPG_FRQCRB (CPG_BASE + 0x0804U)
#define CPG_FRQCRC (CPG_BASE + 0x0808U)
#define CPG_FRQCRD0 (CPG_BASE + 0x080CU)
#define CPG_PLLECR (CPG_BASE + 0x0820U)
#define CPG_PLL3CR0 (CPG_BASE + 0x083CU)
#define CPG_PLL3CR1 (CPG_BASE + 0x08C0U)
#define CPG_FSRCHKCLRR4 (CPG_BASE + 0x0590U)
#define CPG_FSRCHKSETR4 (CPG_BASE + 0x0510U)
#define CPG_FSRCHKRA4 (CPG_BASE + 0x0410U)
#define CPG_SRCR4 (CPG_BASE + 0x2C10U)
#define CPG_SRSTCLR4 (CPG_BASE + 0x2C90U)
#define CPG_PLL3FBCKMCSR (CPG_BASE + 0x0C60U)
#define CPG_PLL3FBCKMECR (CPG_BASE + 0x0C64U)
#define CPG_PLL3FBCKMLCH (CPG_BASE + 0x0C68U)
#define CPG_PLL3FBCKMLCL (CPG_BASE + 0x0C6CU)
#define CPG_PLL3FBCKMCNT (CPG_BASE + 0x0C70U)
#define CPG_PLL3FBCKMCNTE (CPG_BASE + 0x0C74U)
#if defined(__RH850G3K__)
#define RST_BASE (BASE_RESET_ADDR)
#else
#define RST_BASE (0xE6160000U)
#endif
#define RST_MODEMR0 (RST_BASE + 0x0000U)
#define RST_MODEMR1 (RST_BASE + 0x0004U)
/* Product Register */
#define PRR (0xFFF00044U)
#define PRR_PRODUCT_MASK (0x00007F00U)
#define PRR_CUT_MASK (0x000000FFU)
#define PRR_PRODUCT_V4H (0x00005C00U) /* R-Car V4H */
#define PRR_PRODUCT_10 (0x00000000U) /* ver 1.0 */
#define PRR_PRODUCT_20 (0x00000010U) /* ver 2.0 */
/* DBSC registers */
#if defined(__RH850G3K__)
#define DBSC_D_BASE (BASE_DBSC_ADDR + 0x14000U) /* forV4H DBSC0 clk_dbsc region DBSC1_D_BASE = 0xE67A8000U */
#define DBSC_A_BASE (BASE_DBSC_ADDR) /* forV4H DBSC0 clk_axim region DBSC1_A_BASE = 0xE6798000U */
#else
#define DBSC_D_BASE (0xE67A4000U) /* forV4H DBSC0 clk_dbsc region DBSC1_D_BASE = 0xE67A8000U */
#define DBSC_A_BASE (0xE6790000U) /* forV4H DBSC0 clk_axim region DBSC1_A_BASE = 0xE6798000U */
#endif
#define DBSC_DBSYSCONF0 (DBSC_A_BASE + 0x0000U)
#define DBSC_DBSYSCONF1 (DBSC_D_BASE + 0x0000U)
#define DBSC_DBSYSCONF1A (DBSC_A_BASE + 0x0004U)
#define DBSC_DBSYSCONF2 (DBSC_D_BASE + 0x0004U)
#define DBSC_DBPHYCONF0 (DBSC_D_BASE + 0x0008U)
#define DBSC_DBSYSCONF2A (DBSC_A_BASE + 0x0008U)
#define DBSC_DBMEMKIND (DBSC_D_BASE + 0x0020U)
#define DBSC_DBMEMKINDA (DBSC_A_BASE + 0x0020U)
#define DBSC_DBMEMCONF(ch,cs) (DBSC_D_BASE + 0x0030U + 0x10U * (ch) + 0x04U * (cs))
#define DBSC_DBMEMCONF_0_0 (DBSC_D_BASE + 0x0030U)
#define DBSC_DBMEMCONF_0_1 (DBSC_D_BASE + 0x0034U)
#define DBSC_DBMEMCONF_0_2 (DBSC_D_BASE + 0x0038U)
#define DBSC_DBMEMCONF_0_3 (DBSC_D_BASE + 0x003CU)
#define DBSC_DBMEMCONF_1_0 (DBSC_D_BASE + 0x0040U)
#define DBSC_DBMEMCONF_1_1 (DBSC_D_BASE + 0x0044U)
#define DBSC_DBMEMCONF_1_2 (DBSC_D_BASE + 0x0048U)
#define DBSC_DBMEMCONF_1_3 (DBSC_D_BASE + 0x004CU)
#define DBSC_DBMEMCONF_2_0 (DBSC_D_BASE + 0x0050U)
#define DBSC_DBMEMCONF_2_1 (DBSC_D_BASE + 0x0054U)
#define DBSC_DBMEMCONF_2_2 (DBSC_D_BASE + 0x0058U)
#define DBSC_DBMEMCONF_2_3 (DBSC_D_BASE + 0x005CU)
#define DBSC_DBMEMCONF_3_0 (DBSC_D_BASE + 0x0060U)
#define DBSC_DBMEMCONF_3_1 (DBSC_D_BASE + 0x0064U)
#define DBSC_DBMEMCONF_3_2 (DBSC_D_BASE + 0x0068U)
#define DBSC_DBMEMCONF_3_3 (DBSC_D_BASE + 0x006CU)
#define DBSC_DBMEMCONFA(ch,cs) (DBSC_A_BASE + 0x0030U + 0x10U * (ch) + 0x04U * (cs))
#define DBSC_DBMEMCONF_0_0A (DBSC_A_BASE + 0x0030U)
#define DBSC_DBMEMCONF_0_1A (DBSC_A_BASE + 0x0034U)
#define DBSC_DBMEMCONF_0_2A (DBSC_A_BASE + 0x0038U)
#define DBSC_DBMEMCONF_0_3A (DBSC_A_BASE + 0x003CU)
#define DBSC_DBMEMCONF_1_0A (DBSC_A_BASE + 0x0040U)
#define DBSC_DBMEMCONF_1_1A (DBSC_A_BASE + 0x0044U)
#define DBSC_DBMEMCONF_1_2A (DBSC_A_BASE + 0x0048U)
#define DBSC_DBMEMCONF_1_3A (DBSC_A_BASE + 0x004CU)
#define DBSC_DBMEMCONF_2_0A (DBSC_A_BASE + 0x0050U)
#define DBSC_DBMEMCONF_2_1A (DBSC_A_BASE + 0x0054U)
#define DBSC_DBMEMCONF_2_2A (DBSC_A_BASE + 0x0058U)
#define DBSC_DBMEMCONF_2_3A (DBSC_A_BASE + 0x005CU)
#define DBSC_DBMEMCONF_3_0A (DBSC_A_BASE + 0x0060U)
#define DBSC_DBMEMCONF_3_1A (DBSC_A_BASE + 0x0064U)
#define DBSC_DBMEMCONF_3_2A (DBSC_A_BASE + 0x0068U)
#define DBSC_DBMEMCONF_3_3A (DBSC_A_BASE + 0x006CU)
#define DBSC_DBSYSCNT0 (DBSC_D_BASE + 0x0100U)
#define DBSC_DBSYSCNT0A (DBSC_A_BASE + 0x0100U)
#define DBSC_DBACEN (DBSC_A_BASE + 0x0200U)
#define DBSC_DBRFEN (DBSC_D_BASE + 0x0204U)
#define DBSC_DBCMD (DBSC_D_BASE + 0x0208U)
#define DBSC_DBWAIT (DBSC_D_BASE + 0x0210U)
#define DBSC_DBTR(x) (DBSC_D_BASE + 0x0300U + 0x04U * (x))
#define DBSC_DBTR0 (DBSC_D_BASE + 0x0300U)
#define DBSC_DBTR1 (DBSC_D_BASE + 0x0304U)
#define DBSC_DBTR2 (DBSC_D_BASE + 0x0308U)
#define DBSC_DBTR3 (DBSC_D_BASE + 0x030CU)
#define DBSC_DBTR4 (DBSC_D_BASE + 0x0310U)
#define DBSC_DBTR5 (DBSC_D_BASE + 0x0314U)
#define DBSC_DBTR6 (DBSC_D_BASE + 0x0318U)
#define DBSC_DBTR7 (DBSC_D_BASE + 0x031CU)
#define DBSC_DBTR8 (DBSC_D_BASE + 0x0320U)
#define DBSC_DBTR9 (DBSC_D_BASE + 0x0324U)
#define DBSC_DBTR10 (DBSC_D_BASE + 0x0328U)
#define DBSC_DBTR11 (DBSC_D_BASE + 0x032CU)
#define DBSC_DBTR12 (DBSC_D_BASE + 0x0330U)
#define DBSC_DBTR13 (DBSC_D_BASE + 0x0334U)
#define DBSC_DBTR14 (DBSC_D_BASE + 0x0338U)
#define DBSC_DBTR15 (DBSC_D_BASE + 0x033CU)
#define DBSC_DBTR16 (DBSC_D_BASE + 0x0340U)
#define DBSC_DBTR17 (DBSC_D_BASE + 0x0344U)
#define DBSC_DBTR18 (DBSC_D_BASE + 0x0348U)
#define DBSC_DBTR19 (DBSC_D_BASE + 0x034CU)
#define DBSC_DBTR20 (DBSC_D_BASE + 0x0350U)
#define DBSC_DBTR21 (DBSC_D_BASE + 0x0354U)
#define DBSC_DBTR22 (DBSC_D_BASE + 0x0358U)
#define DBSC_DBTR23 (DBSC_D_BASE + 0x035CU)
#define DBSC_DBTR24 (DBSC_D_BASE + 0x0360U)
#define DBSC_DBTR25 (DBSC_D_BASE + 0x0364U)
#define DBSC_DBTR26 (DBSC_D_BASE + 0x0368U)
#define DBSC_DBTR27 (DBSC_D_BASE + 0x036CU)
#define DBSC_DBTR28 (DBSC_D_BASE + 0x0370U)
#define DBSC_DBTR29 (DBSC_D_BASE + 0x0374U)
#define DBSC_DBTR30 (DBSC_D_BASE + 0x0378U)
#define DBSC_DBTR31 (DBSC_D_BASE + 0x037CU)
#define DBSC_DBTR32 (DBSC_D_BASE + 0x0380U)
#define DBSC_DBTR33 (DBSC_D_BASE + 0x0384U)
#define DBSC_DBTR34 (DBSC_D_BASE + 0x0388U)
#define DBSC_DBTR35 (DBSC_D_BASE + 0x038CU)
#define DBSC_DBTR36 (DBSC_D_BASE + 0x0390U)
#define DBSC_DBTR37 (DBSC_D_BASE + 0x0394U)
#define DBSC_DBBL (DBSC_D_BASE + 0x0400U)
#define DBSC_DBBLA (DBSC_A_BASE + 0x0400U)
#define DBSC_DBRFCNF1 (DBSC_D_BASE + 0x0414U)
#define DBSC_DBRFCNF2 (DBSC_D_BASE + 0x0418U)
#define DBSC_DBCALCNF (DBSC_D_BASE + 0x0424U)
#define DBSC_DBRNK(x) (DBSC_D_BASE + 0x0430U + 0x04U * (x))
#define DBSC_DBRNK2 (DBSC_D_BASE + 0x0438U)
#define DBSC_DBRNK3 (DBSC_D_BASE + 0x043CU)
#define DBSC_DBRNK4 (DBSC_D_BASE + 0x0440U)
#define DBSC_DBRNK5 (DBSC_D_BASE + 0x0444U)
#define DBSC_DBDBICNT (DBSC_D_BASE + 0x0518U)
#define DBSC_DBDFIPMSTRCNF (DBSC_D_BASE + 0x0520U)
#define DBSC_DBDFICUPDCNF (DBSC_D_BASE + 0x0540U)
#define DBSC_DBDFISTAT(ch) (DBSC_D_BASE + 0x0600U + 0x2000U * (ch & 0x02U) + 0x40U * (ch & 0x01U))
#define DBSC_DBDFISTAT_0 (DBSC_D_BASE + 0x0600U)
#define DBSC_DBDFISTAT_1 (DBSC_D_BASE + 0x0640U)
#define DBSC_DBDFISTAT_2 (DBSC_D_BASE + 0x0680U)
#define DBSC_DBDFISTAT_3 (DBSC_D_BASE + 0x06C0U)
#define DBSC_DBDFICNT(ch) (DBSC_D_BASE + 0x0604U + 0x2000U * (ch & 0x02U) + 0x40U * (ch & 0x01U))
#define DBSC_DBDFICNT_0 (DBSC_D_BASE + 0x0604U)
#define DBSC_DBDFICNT_1 (DBSC_D_BASE + 0x0644U)
#define DBSC_DBDFICNT_2 (DBSC_D_BASE + 0x0684U)
#define DBSC_DBDFICNT_3 (DBSC_D_BASE + 0x06C4U)
#define DBSC_DBPDCNT0_0 (DBSC_D_BASE + 0x0610U)
#define DBSC_DBPDCNT0_1 (DBSC_D_BASE + 0x0614U)
#define DBSC_DBPDCNT0_2 (DBSC_D_BASE + 0x0618U)
#define DBSC_DBPDCNT0_3 (DBSC_D_BASE + 0x061CU)
#define DBSC_DBPDCNT1_0 (DBSC_D_BASE + 0x0650U)
#define DBSC_DBPDCNT1_1 (DBSC_D_BASE + 0x0654U)
#define DBSC_DBPDCNT1_2 (DBSC_D_BASE + 0x0658U)
#define DBSC_DBPDCNT1_3 (DBSC_D_BASE + 0x065CU)
#define DBSC_DBPDCNT2(ch) (DBSC_D_BASE + 0x0618U + 0x2000U * (ch & 0x02U) + 0x40U * (ch & 0x01U))
#define DBSC_DBPDCNT2_0 (DBSC_D_BASE + 0x0690U)
#define DBSC_DBPDCNT2_1 (DBSC_D_BASE + 0x0694U)
#define DBSC_DBPDCNT2_2 (DBSC_D_BASE + 0x0698U)
#define DBSC_DBPDCNT2_3 (DBSC_D_BASE + 0x069CU)
#define DBSC_DBPDCNT3_0 (DBSC_D_BASE + 0x06D0U)
#define DBSC_DBPDCNT3_1 (DBSC_D_BASE + 0x06D4U)
#define DBSC_DBPDCNT3_2 (DBSC_D_BASE + 0x06D8U)
#define DBSC_DBPDCNT3_3 (DBSC_D_BASE + 0x06DCU)
#define DBSC_DBPDLK(ch) (DBSC_D_BASE + 0x0620U + 0x2000U * (ch & 0x02U) + 0x40U * (ch & 0x01U))
#define DBSC_DBPDLK_0 (DBSC_D_BASE + 0x0620U)
#define DBSC_DBPDLK_1 (DBSC_D_BASE + 0x0660U)
#define DBSC_DBPDLK_2 (DBSC_D_BASE + 0x06a0U)
#define DBSC_DBPDLK_3 (DBSC_D_BASE + 0x06e0U)
#define DBSC_DBPDRGA(ch) (DBSC_D_BASE + 0x0624U + 0x2000U * (ch & 0x02U) + 0x40U * (ch & 0x01U))
#define DBSC_DBPDRGA_0 (DBSC_D_BASE + 0x0624U)
#define DBSC_DBPDRGA_1 (DBSC_D_BASE + 0x0664U)
#define DBSC_DBPDRGA_2 (DBSC_D_BASE + 0x06A4U)
#define DBSC_DBPDRGA_3 (DBSC_D_BASE + 0x06E4U)
#define DBSC_DBPDRGD(ch) (DBSC_D_BASE + 0x0628U + 0x2000U * (ch & 0x02U) + 0x40U * (ch & 0x01U))
#define DBSC_DBPDRGD_0 (DBSC_D_BASE + 0x0628U)
#define DBSC_DBPDRGD_1 (DBSC_D_BASE + 0x0668U)
#define DBSC_DBPDRGD_2 (DBSC_D_BASE + 0x06A8U)
#define DBSC_DBPDRGD_3 (DBSC_D_BASE + 0x06E8U)
#define DBSC_DBPDSTAT0(ch) (DBSC_D_BASE + 0x0630U + 0x2000U * (ch & 0x02U) + 0x40U * (ch & 0x01U))
#define DBSC_DBPDSTAT0_0 (DBSC_D_BASE + 0x0630U)
#define DBSC_DBPDSTAT1_0 (DBSC_D_BASE + 0x0670U)
#define DBSC_DBPDSTAT1(ch) (DBSC_D_BASE + 0x0634U + 0x2000U * (ch & 0x02U) + 0x40U * (ch & 0x01U))
#define DBSC_DBPDSTAT0_1 (DBSC_D_BASE + 0x0634U)
#define DBSC_DBPDSTA1T_1 (DBSC_D_BASE + 0x0674U)
#define DBSC_DBCAM0CTRL0 (DBSC_A_BASE + 0x0940U)
#define DBSC_DBCAMSTAT0(x) (DBSC_A_BASE + 0x0980U + 0x4000U *(x & 0x02U) + 0x10U * (x & 0x01U))
#define DBSC_DBCAM0STAT0 (DBSC_A_BASE + 0x0980U)
#define DBSC_DBCAM1STAT0 (DBSC_A_BASE + 0x0990U)
#define DBSC_DBCAM2STAT0 (DBSC_A_BASE + 0x09A0U)
#define DBSC_DBCAM3STAT0 (DBSC_A_BASE + 0x09B0U)
#define DBSC_DBCAMSTAT1(x) (DBSC_A_BASE + 0x0984U + 0x4000U *(x & 0x02U) + 0x10U * (x & 0x01U))
#define DBSC_DBCAM0STAT1 (DBSC_A_BASE + 0x0984U)
#define DBSC_DBCAM1STAT1 (DBSC_A_BASE + 0x0994U)
#define DBSC_DBCAM2STAT1 (DBSC_A_BASE + 0x09A4U)
#define DBSC_DBCAM3STAT1 (DBSC_A_BASE + 0x09B4U)
#define DBSC_DBBCAMDIS (DBSC_A_BASE + 0x09FCU)
#define DBSC_DBSCHRW1 (DBSC_A_BASE + 0x1024U)
#define DBSC_DBSCHTR0 (DBSC_A_BASE + 0x1030U)
#define DBSC_DBSCHFCTST01(x) (DBSC_A_BASE + 0x1040U + 0x04U * (x))
#define DBSC_DBSCHFCTST0 (DBSC_A_BASE + 0x1040U)
#define DBSC_DBSCHFCTST1 (DBSC_A_BASE + 0x1044U)
#define DBSC_DBSCHQOS(x,y) (DBSC_A_BASE + 0x1100U + 0x10U * (x) + 0x04U * (y))

229
Src/0_Tool/Gen4_R-Car_IPL/SDK/v3_46_0/Gen4_ICUMX_Loader/ip/ddr/v4m/lpddr5/ecc_enable_v4m.c Normal file
View File

@@ -0,0 +1,229 @@
/*******************************************************************************
* Copyright (c) 2023-2025 Renesas Electronics Corporation. All rights reserved.
*
* RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY
*
* This software is provided as reference/sample code under the license
* agreement between Renesas Electronics Corporation and licensee (the
* "License Agreement") and shall be treated as specified in the License
* Agreement.
* These instructions, statements, and software are the confidential
* information of Renesas Electronics Corporation. They must be used and
* modified solely for the purpose for which it was furnished by Renesas
* Electronics Corporation. All or part of these instructions, statements and
* software must not be reproduced nor disclosed to any third party in any
* form, unless permitted by the License Agreement.
*
* THIS SOFTWARE IS PROVIDED BY RENESAS ELEOCTRONICS CORPORATION "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
* SATISFACTORY QUALITY, ACCURACY, TITLE AND NON-INFRINGEMENT ARE DISCLAIMED.
* IN NO EVENT SHALL RENESAS ELECTRONICS CORPORATION BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, PUNITIVE, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
* DAMAGE.
******************************************************************************/
/*******************************************************************************
* DESCRIPTION : ECC setting function
******************************************************************************/
/******************************************************************************
* @file ecc_enable_v4m.c
* - Version : 0.04
* @brief Enable setting process of ECC for DRAM.
* .
*****************************************************************************/
/******************************************************************************
* History : DD.MM.YYYY Version Description
* : 21.08.2023 0.01 First Release
* : 13.06.2024 0.02 Fix register setting for EDC_CFG, and revise
* : the ecm_lock()/ecm_unlock() process.
* : 07.04.2025 0.03 Remove unused functions.
* : 10.06.2025 0.04 Added ECMERRTGTR41/ECMERRCTLR41 register
* operations.
*****************************************************************************/
#include <stdint.h>
#include <cnf_tbl.h>
#include <remap.h>
#include <wdt.h>
#if (ECM_ENABLE == 1)
#include "ecc_enable_v4m.h"
#include "v4m/lpddr5/boot_init_dram_regdef.h"
#include "ecm_enable_v4m.h"
#define AXI_SICREMAP_NUM (5U)
#define RGID_BASE1 (0xFE600000U)
#define RGID_BASE2 (0xE7A00000U)
#define RGID_BASE3 (0xEB800000U)
#define RGID_BASE4 (0xFD800000U)
#define RGID_BASE5 (0xFEA00000U)
#define FDT_COUNTER_MASK (0x0000FFFFU)
static void axi_timeout_setting(void);
void edc_axi_enable(void)
{
uint32_t edc_tmp;
/* Unlock the write protect of ECM registers */
ecm_unlock();
/* (1) Set the corresponding bits of the ECMERRTGTR and ECMERRCTLR registers
to inform the external device of the error via the ERROROUT# pin. */
/* Set bit 11 - bit 2 of ECMERRTGTR7 to all 0 and bit 11 - bit 2 of
ECMERRCTLR7 to 1. (Error of AXI-Bus ECM of each hierarchy) */
edc_tmp = mem_read32(ECMERRTGTR7);
edc_tmp &= ~(0x3FFU << 2U);
ecm_write(ECMERRTGTR7, edc_tmp);
edc_tmp = mem_read32(ECMERRCTLR7);
edc_tmp |= (0x3FFU << 2U);
ecm_write(ECMERRCTLR7, edc_tmp);
/* Set bit 28 - bit 16 of ECMERRTGTR39 to all 0 and bit 28 - bit 16 of
ECMERRCTLR39 to 1. (Error of AXI-Bus ECM of each hierarchy) */
edc_tmp = mem_read32(ECMERRTGTR39);
edc_tmp &= ~(0x1FFFU << 16U);
ecm_write(ECMERRTGTR39, edc_tmp);
edc_tmp = mem_read32(ECMERRCTLR39);
edc_tmp |= (0x1FFFU << 16U);
ecm_write(ECMERRCTLR39, edc_tmp);
/* Set bit 26 of ECMERRTGTR1 to 0 and bit 26 of
ECMERRCTLR1 to 1. (CCI bus EDC error) */
edc_tmp = mem_read32(ECMERRTGTR1);
edc_tmp &= ~(0x1U << 26U);
ecm_write(ECMERRTGTR1, edc_tmp);
edc_tmp = mem_read32(ECMERRCTLR1);
edc_tmp |= (0x1U << 26U);
ecm_write(ECMERRCTLR1, edc_tmp);
/* Set bit 9 of ECMERRTGTR41 to 0 and bit 9 of
ECMERRCTLR41 to 1. (Error of AXI-Bus ECM of VDSP hierarchy) */
edc_tmp = mem_read32(ECMERRTGTR41);
edc_tmp &= ~(0x1U << 9U);
ecm_write(ECMERRTGTR41, edc_tmp);
edc_tmp = mem_read32(ECMERRCTLR41);
edc_tmp |= (0x1U << 9U);
ecm_write(ECMERRCTLR41, edc_tmp);
axi_timeout_setting();
/* Lock the ECM registers */
ecm_lock();
}
void edc_vram_enable(void)
{
uint32_t edc_tmp;
/* Unlock the write protect of ECM registers */
ecm_unlock();
/* (1) Set the corresponding bits of the ECMERRTGTR and ECMERRCTLR registers
to inform the external device of the error via the ERROROUT# pin. */
/* Set bit 30 of ECMERRTGTR7 to 0 and bit 30 of ECMERRCTLR7 to 1.
(RT-VRAM edc 1-bit error) */
edc_tmp = mem_read32(ECMERRTGTR7);
edc_tmp &= ~(0x1U << 30U);
ecm_write(ECMERRTGTR7, edc_tmp);
edc_tmp = mem_read32(ECMERRCTLR7);
edc_tmp |= (0x1U << 30U);
ecm_write(ECMERRCTLR7, edc_tmp);
/* Set bit 29 of ECMERRTGTR7 to 0 and bit 29 of ECMERRCTLR7 to 1.
(RT-VRAM edc multi-bit error) */
edc_tmp = mem_read32(ECMERRTGTR7);
edc_tmp &= ~(0x1U << 29U);
ecm_write(ECMERRTGTR7, edc_tmp);
edc_tmp = mem_read32(ECMERRCTLR7);
edc_tmp |= (0x1U << 29U);
ecm_write(ECMERRCTLR7, edc_tmp);
/* Set bit 19 of ECMERRTGTR17 to 0 and bit 19 of ECMERRCTLR17 to 1.
(RT-VRAM edc 1-bit error) */
edc_tmp = mem_read32(ECMERRTGTR17);
edc_tmp &= ~(0x1U << 19U);
ecm_write(ECMERRTGTR17, edc_tmp);
edc_tmp = mem_read32(ECMERRCTLR17);
edc_tmp |= (0x1U << 19U);
ecm_write(ECMERRCTLR17, edc_tmp);
/* Set bit 18 of ECMERRTGTR17 to 0 and bit 18 of ECMERRCTLR17 to 1.
(RT-VRAM edc multi-bit error) */
edc_tmp = mem_read32(ECMERRTGTR17);
edc_tmp &= ~(0x1U << 18U);
ecm_write(ECMERRTGTR17, edc_tmp);
edc_tmp = mem_read32(ECMERRCTLR17);
edc_tmp |= (0x1U << 18U);
ecm_write(ECMERRCTLR17, edc_tmp);
/* Set bit 0 of EDC_CFG to 1. (EDC Error Control) */
edc_tmp = mem_read32(EDC_CFG);
edc_tmp |= (0x1U << 0U);
mem_write32(EDC_CFG, edc_tmp);
/* Lock the ECM registers */
ecm_lock();
}
static void axi_timeout_setting(void)
{
uint32_t reg;
uint32_t loop;
REMAP_TABLE axi_remap_tbl[AXI_SICREMAP_NUM] = {
{RGID_BASE1, 0U},
{RGID_BASE2, 0U},
{RGID_BASE3, 0U},
{RGID_BASE4, 0U},
{RGID_BASE5, 0U},
};
/* Register of AXI Base */
for (loop = 0U; loop < AXI_SICREMAP_NUM; loop++)
{
remap_register(axi_remap_tbl[loop].base_addr, &axi_remap_tbl[loop].rmp_addr);
}
/* Set the COUNTER bits of the FDT_* registers for all safety-related modules to minimum value with 1ms or more. */
for (loop = 0U; loop < FDT_REG_MAX; loop++)
{
reg = mem_read32(g_fdt_tbl[loop].reg_addr);
reg &= ~(FDT_COUNTER_MASK);
reg |= g_fdt_tbl[loop].value;
mem_write32(g_fdt_tbl[loop].reg_addr, reg);
INFO("FDT[%d] =\t0x%08x \tsetting value = 0x%08x\n", loop, mem_read32(g_fdt_tbl[loop].reg_addr), g_fdt_tbl[loop].value);
}
for(loop = 0U; loop < INTEN_REG_MAX; loop++)
{
/* Set access protection setting value of Region ID (AXI bus of Region ID register) */
mem_write32(g_inten_tbl[loop].reg_addr, g_inten_tbl[loop].value);
INFO("INTEN[%d] =\t0x%08x \tsetting value = 0x%08x\n", loop, mem_read32(g_inten_tbl[loop].reg_addr), g_inten_tbl[loop].value);
}
/* Unregister of AXI Base */
for (loop = 0U; loop < AXI_SICREMAP_NUM; loop++)
{
remap_unregister(axi_remap_tbl[loop].rmp_addr);
}
wdt_restart();
}
#endif /* ECM_ENABLE == 1 */

125
Src/0_Tool/Gen4_R-Car_IPL/SDK/v3_46_0/Gen4_ICUMX_Loader/ip/ddr/v4m/lpddr5/ecc_enable_v4m.h Normal file
View File

@@ -0,0 +1,125 @@
/*******************************************************************************
* Copyright (c) 2022-2025 Renesas Electronics Corporation. All rights reserved.
*
* RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY
*
* This software is provided as reference/sample code under the license
* agreement between Renesas Electronics Corporation and licensee (the
* "License Agreement") and shall be treated as specified in the License
* Agreement.
* These instructions, statements, and software are the confidential
* information of Renesas Electronics Corporation. They must be used and
* modified solely for the purpose for which it was furnished by Renesas
* Electronics Corporation. All or part of these instructions, statements and
* software must not be reproduced nor disclosed to any third party in any
* form, unless permitted by the License Agreement.
*
* THIS SOFTWARE IS PROVIDED BY RENESAS ELEOCTRONICS CORPORATION "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
* SATISFACTORY QUALITY, ACCURACY, TITLE AND NON-INFRINGEMENT ARE DISCLAIMED.
* IN NO EVENT SHALL RENESAS ELECTRONICS CORPORATION BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, PUNITIVE, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
* DAMAGE.
******************************************************************************/
/*******************************************************************************
* DESCRIPTION : ECC driver header
******************************************************************************/
#ifndef ECC_PROTECT
#define ECC_PROTECT
#include "remap_register.h"
/* DBSC registers */
#if defined(__RH850G3K__)
#include "mem_io.h"
#include "log.h"
#define DBSC_D_BASE (BASE_DBSC_ADDR + 0x14000U) /* forV4H DBSC0 clk_dbsc region DBSC1_D_BASE = 0xE67A8000U */
#define DBSC_A_BASE (BASE_DBSC_ADDR) /* forV4H DBSC0 clk_axim region DBSC1_A_BASE = 0xE6798000U */
#define ECM_BASE (BASE_ECC_ADDR)
#else
#include <mmio.h>
#include <debug.h>
#define DBSC_D_BASE (0xE67A4000U) /* forV4H DBSC0 clk_dbsc region DBSC1_D_BASE = 0xE67A8000U */
#define DBSC_A_BASE (0xE6790000U) /* forV4H DBSC0 clk_axim region DBSC1_A_BASE = 0xE6798000U */
#define ECM_BASE (0xE6250000U)
#endif/* defined(__RH850G3K__) */
#define RTVRAM_REG_BASE (0xFFEC0000U)
void edc_axi_enable(void);
void edc_vram_enable(void);
#define DB0SYSCNT0 (DBSC_D_BASE + 0x0100U)
#define DB0SYSCNT0A (DBSC_A_BASE + 0x0100U)
#define DB1SYSCNT0 (DB0SYSCNT0 + 0x4000U)
#define DB1SYSCNT0A (DB0SYSCNT0A + 0x8000U)
#define DBSC_DBACEN0 (DBSC_A_BASE + 0x0200U)
#define DBSC_DBACEN1 (DBSC_DBACEN0 + 0x8000U)
#define ECMWACNTR (ECM_BASE + 0x0A04U)
#define ECMWPCNTR (ECM_BASE + 0x0A00U)
#define ECMERRTGTR0 (ECM_BASE + 0x0200U)
#define ECMERRCTLR0 (ECM_BASE + 0x0000U)
#define ECMERRTGTR1 (ECM_BASE + 0x0200U + 0x4U * 1U)
#define ECMERRCTLR1 (ECM_BASE + 0x0000U + 0x4U * 1U)
#define ECMERRTGTR7 (ECM_BASE + 0x0200U + 0x4U * 7U)
#define ECMERRCTLR7 (ECM_BASE + 0x0000U + 0x4U * 7U)
#define ECMERRTGTR17 (ECM_BASE + 0x0200U + 0x4U * 17U)
#define ECMERRCTLR17 (ECM_BASE + 0x0000U + 0x4U * 17U)
#define ECMERRTGTR39 (ECM_BASE + 0x0200U + 0x4U * 39U)
#define ECMERRCTLR39 (ECM_BASE + 0x0000U + 0x4U * 39U)
#define ECMERRTGTR41 (ECM_BASE + 0x0200U + 0x4U * 41U)
#define ECMERRCTLR41 (ECM_BASE + 0x0000U + 0x4U * 41U)
#define DB0FSCONF00A (DBSC_A_BASE + 0x7640U)
#define DB1FSCONF00A (DB0FSCONF00A + 0x8000U)
#define DB0FSCONF01A (DBSC_A_BASE + 0x7644U)
#define DB1FSCONF01A (DB0FSCONF01A + 0x8000U)
#define DB0FSCONF02A (DBSC_A_BASE + 0x7648U)
#define DB1FSCONF02A (DB0FSCONF02A + 0x8000U)
#define DB0FSCTRL01A (DBSC_A_BASE + 0x7604U)
#define DB1FSCTRL01A (DB0FSCTRL01A + 0x8000U)
#define DB0FSSTAT01A (DBSC_A_BASE + 0x7684U)
#define DB1FSSTAT01A (DB0FSSTAT01A + 0x8000U)
#define DB0FSSTAT00A (DBSC_A_BASE + 0x7680U)
#define DB1FSSTAT00A (DB0FSSTAT00A + 0x8000U)
#define DB0FSINTENB02A (DBSC_A_BASE + 0x7088U)
#define DB1FSINTENB02A (DB0FSINTENB02A + 0x8000U)
#define DB0FSINTENB04A (DBSC_A_BASE + 0x7090U)
#define DB1FSINTENB04A (DB0FSINTENB04A + 0x8000U)
#define DB0FSDRAMECCAREA0 (DBSC_A_BASE + 0x7450U)
#define DB0FSDRAMECCAREA1 (DBSC_A_BASE + 0x7454U)
#define DB1FSDRAMECCAREA0 (DB0FSDRAMECCAREA0 + 0x8000U)
#define DB1FSDRAMECCAREA1 (DB0FSDRAMECCAREA1 + 0x8000U)
#define DB0FSCONFAXI0 (DBSC_A_BASE + 0x7400U)
#define DB1FSCONFAXI0 (DB0FSCONFAXI0 + 0x8000U)
#define EDC_CFG (RTVRAM_REG_BASE + 0x4110U)
/********************* Set by the user *********************/
/* The row address of ECC Protection Area Size for memory rank 0/1 of DBSC0/1 */
#define ECC_PROT_SIZE00 (0x1000U)
#define ECC_PROT_SIZE01 (0x1000U)
#define ECC_PROT_SIZE10 (0x1000U)
#define ECC_PROT_SIZE11 (0x1000U)
/* Start and End row address of ECC Protection area for rank0 of DBSC0/1 */
#define START_ECC_INIT_AREA00 (0x00000000U)
#define START_ECC_INIT_AREA10 (0x00000000U)
#define END_ECC_INIT_AREA00 (0x00000FFFU)
#define END_ECC_INIT_AREA10 (0x00000FFFU)
/* Start and End row address of ECC Protection area for rank1 of DBSC0/1 */
#define START_ECC_INIT_AREA01 (0x00000000U)
#define START_ECC_INIT_AREA11 (0x00000000U)
#define END_ECC_INIT_AREA01 (0x00000FFFU)
#define END_ECC_INIT_AREA11 (0x00000FFFU)
/*********** Other settings cannot be changed ***************/
#endif/* ECC_PROTECT */

534
Src/0_Tool/Gen4_R-Car_IPL/SDK/v3_46_0/Gen4_ICUMX_Loader/ip/ddr/v4m/lpddr5/ecm_enable_v4m.c Normal file
View File

@@ -0,0 +1,534 @@
/*******************************************************************************
* Copyright (c) 2025 Renesas Electronics Corporation. All rights reserved.
*
* RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY
*
* This software is provided as reference/sample code under the license
* agreement between Renesas Electronics Corporation and licensee (the
* "License Agreement") and shall be treated as specified in the License
* Agreement.
* These instructions, statements, and software are the confidential
* information of Renesas Electronics Corporation. They must be used and
* modified solely for the purpose for which it was furnished by Renesas
* Electronics Corporation. All or part of these instructions, statements and
* software must not be reproduced nor disclosed to any third party in any
* form, unless permitted by the License Agreement.
*
* THIS SOFTWARE IS PROVIDED BY RENESAS ELEOCTRONICS CORPORATION "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
* SATISFACTORY QUALITY, ACCURACY, TITLE AND NON-INFRINGEMENT ARE DISCLAIMED.
* IN NO EVENT SHALL RENESAS ELECTRONICS CORPORATION BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, PUNITIVE, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
* DAMAGE.
******************************************************************************/
/*******************************************************************************
* DESCRIPTION : ECM initialize function
******************************************************************************/
/******************************************************************************
* @file ecm_enable_v4m.c
* - Version : 0.01
* @brief ECM setting.
* .
*****************************************************************************/
/******************************************************************************
* History : DD.MM.YYYY Version Description
* : 29.01.2025 0.01 First Release
*****************************************************************************/
#include <stdint.h>
#include "ecm_enable_v4m.h"
#if (ECM_ERROR_ENABLE == 1)
#include "log.h"
#endif /* ECM_ERROR_ENABLE == 1 */
#if ((ECM_ERROR_ENABLE == 1) || (ECM_ENABLE == 1))
#include "ecc_enable_v4m.h"
#include "mem_io.h"
#endif /* (ECM_ERROR_ENABLE == 1) || (ECM_ENABLE == 1) */
#if (ECM_ERROR_ENABLE == 1)
#define TYPE1_ECM_REG_MAX (14U)
#define TYPE2_ECM_REG_MAX (21U)
#define TYPE3_ECM_CTLREG_MAX (1U)
#define TYPE3_ECM_TGTREG_MAX (2U)
typedef struct{
uint32_t phys_addr; /* Physical address of ECM registers. */
uint32_t value; /* Setting value of ECM registers. */
} ECM_ERROR_TABLE;
#endif /* ECM_ERROR_ENABLE == 1 */
#if ((ECM_ERROR_ENABLE == 1) || (ECM_ENABLE == 1))
void ecm_unlock(void)
{
mem_write32(ECMWPCNTR, 0xACCE0001U);
}
void ecm_write(uint32_t adr, uint32_t val)
{
mem_write32(ECMWACNTR, ((0xACCEU << 16U) | (adr & 0xffffU)));
mem_write32(adr, val);
}
void ecm_lock(void)
{
mem_write32(ECMWPCNTR, 0xACCE0000U);
}
#endif /* (ECM_ERROR_ENABLE == 1) || (ECM_ENABLE == 1) */
#if (ECM_ERROR_ENABLE == 1)
void ecm_init_setting(void)
{
uint32_t reg;
uint32_t loop;
const ECM_ERROR_TABLE ecmerrctlr_type1_tbl[TYPE1_ECM_REG_MAX] = {
[0] = {0xFD850000U, 0x00381000U}, /* ECMERRCTLR0 */
[1] = {0xFD850004U, 0xA400C000U}, /* ECMERRCTLR1 */
/* Skip ECMERRCTLR2 setting */
/* Skip ECMERRCTLR3 setting */
/* Skip ECMERRCTLR4 setting */
/* Skip ECMERRCTLR5 setting */
[2] = {0xFD850018U, 0xCC000000U}, /* ECMERRCTLR6 */
[3] = {0xFD85001CU, 0x08000000U}, /* ECMERRCTLR7 */
/* Skip ECMERRCTLR8 setting */
/* Skip ECMERRCTLR9 setting */
/* Skip ECMERRCTLR10 setting */
/* Skip ECMERRCTLR11 setting */
/* Skip ECMERRCTLR12 setting */
/* Skip ECMERRCTLR13 setting */
/* Skip ECMERRCTLR14 setting */
/* Skip ECMERRCTLR15 setting */
/* Skip ECMERRCTLR16 setting */
[4] = {0xFD850044U, 0x2D001000U}, /* ECMERRCTLR17 */
[5] = {0xFD850048U, 0x0CC001FFU}, /* ECMERRCTLR18 */
[6] = {0xFD85004CU, 0xFFF80000U}, /* ECMERRCTLR19 */
[7] = {0xFD850050U, 0x0000001EU}, /* ECMERRCTLR20 */
[8] = {0xFD850054U, 0x9F000000U}, /* ECMERRCTLR21 */
/* Skip ECMERRCTLR22 setting */
/* Skip ECMERRCTLR23 setting */
/* Skip ECMERRCTLR24 setting */
/* Skip ECMERRCTLR25 setting */
/* Skip ECMERRCTLR26 setting */
/* Skip ECMERRCTLR27 setting */
/* Skip ECMERRCTLR28 setting */
/* Skip ECMERRCTLR29 setting */
/* Skip ECMERRCTLR30 setting */
/* Skip ECMERRCTLR31 setting */
[9] = {0xFD850080U, 0x10000000U}, /* ECMERRCTLR32 */
[10] = {0xFD850084U, 0x10000000U}, /* ECMERRCTLR33 */
/* Skip ECMERRCTLR34 setting */
[11] = {0xFD85008CU, 0x20002280U}, /* ECMERRCTLR35 */
/* Skip ECMERRCTLR36 setting */
/* Skip ECMERRCTLR37 setting */
[12] = {0xFD850098U, 0x33300054U}, /* ECMERRCTLR38 */
/* Skip ECMERRCTLR39 setting */
/* Skip ECMERRCTLR40 setting */
[13] = {0xFD8500A4U, 0x01000880U}, /* ECMERRCTLR41 */
/* Skip ECMERRCTLR42 setting */
};
const ECM_ERROR_TABLE ecmerrtgtr_type1_tbl[TYPE1_ECM_REG_MAX] = {
[0] = {0xFD850200U, 0x00381000U}, /* ECMERRTGTR0 */
[1] = {0xFD850204U, 0xA400C000U}, /* ECMERRTGTR1 */
/* Skip ECMERRTGTR2 setting */
/* Skip ECMERRTGTR3 setting */
/* Skip ECMERRTGTR4 setting */
/* Skip ECMERRTGTR5 setting */
[2] = {0xFD850218U, 0xCC000000U}, /* ECMERRTGTR6 */
[3] = {0xFD85021CU, 0x08000000U}, /* ECMERRTGTR7 */
/* Skip ECMERRTGTR8 setting */
/* Skip ECMERRTGTR9 setting */
/* Skip ECMERRTGTR10 setting */
/* Skip ECMERRTGTR11 setting */
/* Skip ECMERRTGTR12 setting */
/* Skip ECMERRTGTR13 setting */
/* Skip ECMERRTGTR14 setting */
/* Skip ECMERRTGTR15 setting */
/* Skip ECMERRTGTR16 setting */
[4] = {0xFD850244U, 0x2D001000U}, /* ECMERRTGTR17 */
[5] = {0xFD850248U, 0x0CC001FFU}, /* ECMERRTGTR18 */
[6] = {0xFD85024CU, 0xFFF80000U}, /* ECMERRTGTR19 */
[7] = {0xFD850250U, 0x0000001EU}, /* ECMERRTGTR20 */
[8] = {0xFD850254U, 0x9F000000U}, /* ECMERRTGTR21 */
/* Skip ECMERRTGTR22 setting */
/* Skip ECMERRTGTR23 setting */
/* Skip ECMERRTGTR24 setting */
/* Skip ECMERRTGTR25 setting */
/* Skip ECMERRTGTR26 setting */
/* Skip ECMERRTGTR27 setting */
/* Skip ECMERRTGTR28 setting */
/* Skip ECMERRTGTR29 setting */
/* Skip ECMERRTGTR30 setting */
/* Skip ECMERRTGTR31 setting */
[9] = {0xFD850280U, 0x10000000U}, /* ECMERRTGTR32 */
[10] = {0xFD850284U, 0x10000000U}, /* ECMERRTGTR33 */
/* Skip ECMERRTGTR34 setting */
[11] = {0xFD85028CU, 0x20002280U}, /* ECMERRTGTR35 */
/* Skip ECMERRTGTR36 setting */
/* Skip ECMERRTGTR37 setting */
[12] = {0xFD850298U, 0x33300054U}, /* ECMERRTGTR38 */
/* Skip ECMERRTGTR39 setting */
/* Skip ECMERRTGTR40 setting */
[13] = {0xFD8502A4U, 0x01000880U}, /* ECMERRTGTR41 */
/* Skip ECMERRTGTR42 setting */
};
const ECM_ERROR_TABLE ecmerrctlr_type2_tbl[TYPE2_ECM_REG_MAX] = {
[0] = {0xFD850000U, 0x40000003U}, /* ECMERRCTLR0 */
[1] = {0xFD850004U, 0x04004000U}, /* ECMERRCTLR1 */
[2] = {0xFD850008U, 0xFFFFFFFFU}, /* ECMERRCTLR2 */
[3] = {0xFD85000CU, 0xFFFFFFFFU}, /* ECMERRCTLR3 */
[4] = {0xFD850010U, 0xFFFFFFFFU}, /* ECMERRCTLR4 */
[5] = {0xFD850014U, 0x81FFFFFFU}, /* ECMERRCTLR5 */
[6] = {0xFD850018U, 0x15000A80U}, /* ECMERRCTLR6 */
[7] = {0xFD85001CU, 0x00801481U}, /* ECMERRCTLR7 */
/* Skip ECMERRCTLR8 setting */
/* Skip ECMERRCTLR9 setting */
/* Skip ECMERRCTLR10 setting */
/* Skip ECMERRCTLR11 setting */
/* Skip ECMERRCTLR12 setting */
/* Skip ECMERRCTLR13 setting */
/* Skip ECMERRCTLR14 setting */
/* Skip ECMERRCTLR15 setting */
[8] = {0xFD850040U, 0x00003E9FU}, /* ECMERRCTLR16 */
[9] = {0xFD850044U, 0x00938060U}, /* ECMERRCTLR17 */
[10] = {0xFD850048U, 0x00341600U}, /* ECMERRCTLR18 */
[11] = {0xFD85004CU, 0x0007FF30U}, /* ECMERRCTLR19 */
[12] = {0xFD850050U, 0x02200220U}, /* ECMERRCTLR20 */
[13] = {0xFD850054U, 0x0061820FU}, /* ECMERRCTLR21 */
/* Skip ECMERRCTLR22 setting */
/* Skip ECMERRCTLR23 setting */
/* Skip ECMERRCTLR24 setting */
/* Skip ECMERRCTLR25 setting */
/* Skip ECMERRCTLR26 setting */
/* Skip ECMERRCTLR27 setting */
/* Skip ECMERRCTLR28 setting */
/* Skip ECMERRCTLR29 setting */
/* Skip ECMERRCTLR30 setting */
/* Skip ECMERRCTLR31 setting */
[14] = {0xFD850080U, 0x03E9043BU}, /* ECMERRCTLR32 */
[15] = {0xFD850084U, 0x03E9043BU}, /* ECMERRCTLR33 */
/* Skip ECMERRCTLR34 setting */
[16] = {0xFD85008CU, 0x83B00800U}, /* ECMERRCTLR35 */
[17] = {0xFD850090U, 0xFFFFFFFFU}, /* ECMERRCTLR36 */
/* Skip ECMERRCTLR37 setting */
[18] = {0xFD850098U, 0x00000002U}, /* ECMERRCTLR38 */
/* Skip ECMERRCTLR39 setting */
[19] = {0xFD8500A0U, 0x0000601EU}, /* ECMERRCTLR40 */
[20] = {0xFD8500A4U, 0x20010000U}, /* ECMERRCTLR41 */
/* Skip ECMERRCTLR42 setting */
};
const ECM_ERROR_TABLE ecmerrtgtr_type2_tbl[TYPE2_ECM_REG_MAX] = {
[0] = {0xFD850200U, 0x40000003U}, /* ECMERRTGTR0 */
[1] = {0xFD850204U, 0x04004000U}, /* ECMERRTGTR1 */
[2] = {0xFD850208U, 0xFFFFFFFFU}, /* ECMERRTGTR2 */
[3] = {0xFD85020CU, 0xFFFFFFFFU}, /* ECMERRTGTR3 */
[4] = {0xFD850210U, 0xFFFFFFFFU}, /* ECMERRTGTR4 */
[5] = {0xFD850214U, 0x81FFFFFFU}, /* ECMERRTGTR5 */
[6] = {0xFD850218U, 0x15000A80U}, /* ECMERRTGTR6 */
[7] = {0xFD85021CU, 0x00801481U}, /* ECMERRTGTR7 */
/* Skip ECMERRTGTR8 setting */
/* Skip ECMERRTGTR9 setting */
/* Skip ECMERRTGTR10 setting */
/* Skip ECMERRTGTR11 setting */
/* Skip ECMERRTGTR12 setting */
/* Skip ECMERRTGTR13 setting */
/* Skip ECMERRTGTR14 setting */
/* Skip ECMERRTGTR15 setting */
[8] = {0xFD850240U, 0x00003E9FU}, /* ECMERRTGTR16 */
[9] = {0xFD850244U, 0x00938060U}, /* ECMERRTGTR17 */
[10] = {0xFD850248U, 0x00341600U}, /* ECMERRTGTR18 */
[11] = {0xFD85024CU, 0x0007FF30U}, /* ECMERRTGTR19 */
[12] = {0xFD850250U, 0x02200220U}, /* ECMERRTGTR20 */
[13] = {0xFD850254U, 0x0061820FU}, /* ECMERRTGTR21 */
/* Skip ECMERRTGTR22 setting */
/* Skip ECMERRTGTR23 setting */
/* Skip ECMERRTGTR24 setting */
/* Skip ECMERRTGTR25 setting */
/* Skip ECMERRTGTR26 setting */
/* Skip ECMERRTGTR27 setting */
/* Skip ECMERRTGTR28 setting */
/* Skip ECMERRTGTR29 setting */
/* Skip ECMERRTGTR30 setting */
/* Skip ECMERRTGTR31 setting */
[14] = {0xFD850280U, 0x03E9043BU}, /* ECMERRTGTR32 */
[15] = {0xFD850284U, 0x03E9043BU}, /* ECMERRTGTR33 */
/* Skip ECMERRTGTR34 setting */
[16] = {0xFD85028CU, 0x83B00800U}, /* ECMERRTGTR35 */
[17] = {0xFD850290U, 0xFFFFFFFFU}, /* ECMERRTGTR36 */
/* Skip ECMERRTGTR37 setting */
[18] = {0xFD850298U, 0x00000002U}, /* ECMERRTGTR38 */
/* Skip ECMERRTGTR39 setting */
[19] = {0xFD8502A0U, 0x0000601EU}, /* ECMERRTGTR40 */
[20] = {0xFD8502A4U, 0x20010000U}, /* ECMERRTGTR41 */
/* Skip ECMERRTGTR42 setting */
};
const ECM_ERROR_TABLE ecmerrctlr_type3_tbl[TYPE3_ECM_CTLREG_MAX] = {
/* Skip ECMERRCTLR0 setting */
/* Skip ECMERRCTLR1 setting */
/* Skip ECMERRCTLR2 setting */
/* Skip ECMERRCTLR3 setting */
/* Skip ECMERRCTLR4 setting */
/* Skip ECMERRCTLR5 setting */
/* Skip ECMERRCTLR6 setting */
/* Skip ECMERRCTLR7 setting */
/* Skip ECMERRCTLR8 setting */
/* Skip ECMERRCTLR9 setting */
/* Skip ECMERRCTLR10 setting */
/* Skip ECMERRCTLR11 setting */
/* Skip ECMERRCTLR12 setting */
/* Skip ECMERRCTLR13 setting */
/* Skip ECMERRCTLR14 setting */
/* Skip ECMERRCTLR15 setting */
[0] = {0xFD850040U, 0x33F00000U}, /* ECMERRCTLR16 */
/* Skip ECMERRCTLR17 setting */
/* Skip ECMERRCTLR18 setting */
/* Skip ECMERRCTLR19 setting */
/* Skip ECMERRCTLR20 setting */
/* Skip ECMERRCTLR21 setting */
/* Skip ECMERRCTLR22 setting */
/* Skip ECMERRCTLR23 setting */
/* Skip ECMERRCTLR24 setting */
/* Skip ECMERRCTLR25 setting */
/* Skip ECMERRCTLR26 setting */
/* Skip ECMERRCTLR27 setting */
/* Skip ECMERRCTLR28 setting */
/* Skip ECMERRCTLR29 setting */
/* Skip ECMERRCTLR30 setting */
/* Skip ECMERRCTLR31 setting */
/* Skip ECMERRCTLR32 setting */
/* Skip ECMERRCTLR33 setting */
/* Skip ECMERRCTLR34 setting */
/* Skip ECMERRCTLR35 setting */
/* Skip ECMERRCTLR36 setting */
/* Skip ECMERRCTLR37 setting */
/* Skip ECMERRCTLR38 setting */
/* Skip ECMERRCTLR39 setting */
/* Skip ECMERRCTLR40 setting */
/* Skip ECMERRCTLR41 setting */
/* Skip ECMERRCTLR42 setting */
};
const ECM_ERROR_TABLE ecmerrtgtr_type3_tbl[TYPE3_ECM_TGTREG_MAX] = {
[0] = {0xFD850200U, 0x80000000U}, /* ECMERRTGTR0 */
/* Skip ECMERRTGTR1 setting */
/* Skip ECMERRTGTR2 setting */
/* Skip ECMERRTGTR3 setting */
/* Skip ECMERRTGTR4 setting */
/* Skip ECMERRTGTR5 setting */
/* Skip ECMERRTGTR6 setting */
/* Skip ECMERRTGTR7 setting */
/* Skip ECMERRTGTR8 setting */
/* Skip ECMERRTGTR9 setting */
/* Skip ECMERRTGTR10 setting */
/* Skip ECMERRTGTR11 setting */
/* Skip ECMERRTGTR12 setting */
/* Skip ECMERRTGTR13 setting */
/* Skip ECMERRTGTR14 setting */
/* Skip ECMERRTGTR15 setting */
[1] = {0xFD850240U, 0x33F00000U}, /* ECMERRTGTR16 */
/* Skip ECMERRTGTR17 setting */
/* Skip ECMERRTGTR18 setting */
/* Skip ECMERRTGTR19 setting */
/* Skip ECMERRTGTR20 setting */
/* Skip ECMERRTGTR21 setting */
/* Skip ECMERRTGTR22 setting */
/* Skip ECMERRTGTR23 setting */
/* Skip ECMERRTGTR24 setting */
/* Skip ECMERRTGTR25 setting */
/* Skip ECMERRTGTR26 setting */
/* Skip ECMERRTGTR27 setting */
/* Skip ECMERRTGTR28 setting */
/* Skip ECMERRTGTR29 setting */
/* Skip ECMERRTGTR30 setting */
/* Skip ECMERRTGTR31 setting */
/* Skip ECMERRTGTR32 setting */
/* Skip ECMERRTGTR33 setting */
/* Skip ECMERRTGTR34 setting */
/* Skip ECMERRTGTR35 setting */
/* Skip ECMERRTGTR36 setting */
/* Skip ECMERRTGTR37 setting */
/* Skip ECMERRTGTR38 setting */
/* Skip ECMERRTGTR39 setting */
/* Skip ECMERRTGTR40 setting */
/* Skip ECMERRTGTR41 setting */
/* Skip ECMERRTGTR42 setting */
};
/* Unlock the write protect of ECM registers */
ecm_unlock();
NOTICE("ECMERRCTLR and ECMERRTGTR register initial setting.\n");
/* For the initial setting flow for Type-1, please refer to the following
* section in the "SAN(Safety Application Note)."
* Section 4.1.2.5 : (1)
* Section 4.1.4.5 : (1)
* Section 4.12.1.5 : (1)
* Section 4.14.5 : (1)
* Section 4.2.7.5 : (1)
* Section 4.2.9.5 : (1)
* Section 4.23.5 : (1)
* Section 4.25.5 : (1)
* Section 4.3.14.5 : (1)
* Section 4.3.19.5 : (1)
* Section 4.3.21.5 : (1)
* Section 4.4.16.5 : (1)
* Section 4.4.18.5 : (1)
* Section 4.4.20.5 : (1)
* Section 4.4.3.5 : (1)
* Section 4.4.4.5 : (1)
* Section 4.4.6.5 : (1)
* Section 4.4.7.5 : (1)
* Section 4.4.9.5 : (1)
* Section 4.5.1.5 : (1)
* Section 4.7.1.5 : (1)
* Section 4.7.10.5 : (1)
* Section 4.7.3.5 : (1)
* Section 4.7.4.5 : (1)
* Section 4.7.7.5 : (1)
* Section 4.7.8.5 : (1)
* Section 5.8.1.5 : (1)
*/
for (loop = 0U; loop < TYPE1_ECM_REG_MAX; loop++)
{
/* Initial Setting Type-1 for ECMERRCTLR registers */
reg = mem_read32(ecmerrctlr_type1_tbl[loop].phys_addr);
reg |= (ecmerrctlr_type1_tbl[loop].value);
ecm_write(ecmerrctlr_type1_tbl[loop].phys_addr, reg);
INFO("[Type-1]ECMERRCTLR[\t%d]\t(0x%x) =\t0x%x \tsetting value = 0x%x\n",
loop,
ecmerrctlr_type1_tbl[loop].phys_addr,
mem_read32(ecmerrctlr_type1_tbl[loop].phys_addr),
ecmerrctlr_type1_tbl[loop].value);
}
for (loop = 0U; loop < TYPE1_ECM_REG_MAX; loop++)
{
/* Initial Setting Type-1 for ECMERRTGTR registers */
reg = mem_read32(ecmerrtgtr_type1_tbl[loop].phys_addr);
reg &= ~(ecmerrtgtr_type1_tbl[loop].value);
ecm_write(ecmerrtgtr_type1_tbl[loop].phys_addr, reg);
INFO("[Type-1]ECMERRTGTR[\t%d]\t(0x%x) =\t0x%x \tsetting value = 0x%x\n",
loop,
ecmerrtgtr_type1_tbl[loop].phys_addr,
mem_read32(ecmerrtgtr_type1_tbl[loop].phys_addr),
ecmerrtgtr_type1_tbl[loop].value);
}
/* For the initial setting flow for Type-2, please refer to the following
* section in the "SAN(Safety Application Note)."
* Section 4.1.1.5 : (1)
* Section 4.12.2.5 : (1)
* Section 4.12.3.5 : (1)
* Section 4.15.5 : (1)
* Section 4.16.5 : (1)
* Section 4.18.5 : (1)
* Section 4.2.1.5 : (1)
* Section 4.2.10.5 : (1)
* Section 4.2.12.5 : (1)
* Section 4.2.2.5 : (1)
* Section 4.2.4.5 : (1)
* Section 4.2.8.5 : (1)
* Section 4.3.1.5 : (1)
* Section 4.3.10.5 : (1)
* Section 4.3.11.5 : (1)
* Section 4.3.12.5 : (1)
* Section 4.3.13.5 : (1)
* Section 4.3.15.5 : (1)
* Section 4.3.16.5 : (1)
* Section 4.3.2.5 : (1)
* Section 4.3.5.5 : (1)
* Section 4.3.7.5 : (1)
* Section 4.3.8.5 : (1)
* Section 4.4.10.5 : (1)
* Section 4.4.12.5 : (6)
* Section 4.4.13.5 : (1)
* Section 4.4.14.5 : (1)
* Section 4.4.15.5 : (1)
* Section 4.4.2.5 : (1)
* Section 4.5.3.5 : (1)
* Section 4.6.5 : (1)
* Section 4.7.2.5 : (1)
* Section 5.11.5 : (1)
* Section 5.12.5 : (1)
* Section 5.13.5 : (1)
* Section 5.4.5 : (1)
* Section 5.6.5 : (1)
* Section 5.8.2.5 : (1)
*/
for (loop = 0U; loop < TYPE2_ECM_REG_MAX; loop++)
{
/* Initial Setting Type-2 for ECMERRCTLR registers */
reg = mem_read32(ecmerrctlr_type2_tbl[loop].phys_addr);
reg |= (ecmerrctlr_type2_tbl[loop].value);
ecm_write(ecmerrctlr_type2_tbl[loop].phys_addr, reg);
INFO("[Type-2]ECMERRCTLR[\t%d]\t(0x%x) =\t0x%x \tsetting value = 0x%x\n",
loop,
ecmerrctlr_type2_tbl[loop].phys_addr,
mem_read32(ecmerrctlr_type2_tbl[loop].phys_addr),
ecmerrctlr_type2_tbl[loop].value);
}
for (loop = 0U; loop < TYPE2_ECM_REG_MAX; loop++)
{
/* Initial Setting Type-2 for ECMERRTGTR registers */
reg = mem_read32(ecmerrtgtr_type2_tbl[loop].phys_addr);
reg &= ~(ecmerrtgtr_type2_tbl[loop].value);
ecm_write(ecmerrtgtr_type2_tbl[loop].phys_addr, reg);
INFO("[Type-2]ECMERRTGTR[\t%d]\t(0x%x) =\t0x%x \tsetting value = 0x%x\n",
loop,
ecmerrtgtr_type2_tbl[loop].phys_addr,
mem_read32(ecmerrtgtr_type2_tbl[loop].phys_addr),
ecmerrtgtr_type2_tbl[loop].value);
}
/* For the initial setting flow for Type-3, please refer to the following
* section in the "SAN(Safety Application Note)."
* Section 4.19.1.5 : (3)
* Section 6.2.5 : (12)
*/
for (loop = 0U; loop < TYPE3_ECM_CTLREG_MAX; loop++)
{
/* Initial Setting Type-3 for ECMERRCTLR registers */
reg = mem_read32(ecmerrctlr_type3_tbl[loop].phys_addr);
reg |= (ecmerrctlr_type3_tbl[loop].value);
ecm_write(ecmerrctlr_type3_tbl[loop].phys_addr, reg);
INFO("[Type-3]ECMERRCTLR[\t%d]\t(0x%x) =\t0x%x \tsetting value = 0x%x\n",
loop,
ecmerrctlr_type3_tbl[loop].phys_addr,
mem_read32(ecmerrctlr_type3_tbl[loop].phys_addr),
ecmerrctlr_type3_tbl[loop].value);
}
for (loop = 0U; loop < TYPE3_ECM_TGTREG_MAX; loop++)
{
/* Initial Setting Type-3 for ECMERRTGTR registers */
reg = mem_read32(ecmerrtgtr_type3_tbl[loop].phys_addr);
reg &= ~(ecmerrtgtr_type3_tbl[loop].value);
ecm_write(ecmerrtgtr_type3_tbl[loop].phys_addr, reg);
INFO("[Type-3]ECMERRTGTR[\t%d]\t(0x%x) =\t0x%x \tsetting value = 0x%x\n",
loop,
ecmerrtgtr_type3_tbl[loop].phys_addr,
mem_read32(ecmerrtgtr_type3_tbl[loop].phys_addr),
ecmerrtgtr_type3_tbl[loop].value);
}
/* Lock the ECM registers */
ecm_lock();
}
/* End of function ecm_init_setting(void) */
#endif /* ECM_ERROR_ENABLE == 1 */

47
Src/0_Tool/Gen4_R-Car_IPL/SDK/v3_46_0/Gen4_ICUMX_Loader/ip/ddr/v4m/lpddr5/ecm_enable_v4m.h Normal file
View File

@@ -0,0 +1,47 @@
/*******************************************************************************
* Copyright (c) 2025 Renesas Electronics Corporation. All rights reserved.
*
* RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY
*
* This software is provided as reference/sample code under the license
* agreement between Renesas Electronics Corporation and licensee (the
* "License Agreement") and shall be treated as specified in the License
* Agreement.
* These instructions, statements, and software are the confidential
* information of Renesas Electronics Corporation. They must be used and
* modified solely for the purpose for which it was furnished by Renesas
* Electronics Corporation. All or part of these instructions, statements and
* software must not be reproduced nor disclosed to any third party in any
* form, unless permitted by the License Agreement.
*
* THIS SOFTWARE IS PROVIDED BY RENESAS ELEOCTRONICS CORPORATION "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
* SATISFACTORY QUALITY, ACCURACY, TITLE AND NON-INFRINGEMENT ARE DISCLAIMED.
* IN NO EVENT SHALL RENESAS ELECTRONICS CORPORATION BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, PUNITIVE, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
* DAMAGE.
******************************************************************************/
/*******************************************************************************
* DESCRIPTION : ECM driver header
******************************************************************************/
#ifndef ECM_ENABLE_V4M
#define ECM_ENABLE_V4M
#if ((ECM_ERROR_ENABLE == 1) || (ECM_ENABLE == 1))
void ecm_unlock(void);
void ecm_write(uint32_t adr, uint32_t val);
void ecm_lock(void);
#endif /* (ECM_ERROR_ENABLE == 1) || (ECM_ENABLE == 1) */
#if (ECM_ERROR_ENABLE == 1)
void ecm_init_setting(void);
#endif /* ECM_ERROR_ENABLE == 1 */
#endif/* ECM_ENABLE_V4M */

182
Src/0_Tool/Gen4_R-Car_IPL/SDK/v3_46_0/Gen4_ICUMX_Loader/ip/dma/dma.c Normal file
View File

@@ -0,0 +1,182 @@
/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright 2021-2022 Renesas Electronics Corporation All rights reserved.
*******************************************************************************/
/*******************************************************************************
* DESCRIPTION : DMA driver
******************************************************************************/
/******************************************************************************
* @file dma.c
* - Version : 0.07
* @brief DMA driver.
* .
*****************************************************************************/
/******************************************************************************
* History : DD.MM.YYYY Version Description
* : 28.07.2021 0.01 First Release
* : 30.09.2021 0.02 Change function name load_start and
* load_end function.
* : 15.10.2021 0.03 modified to not use CHCLR.
* : 06.01.2022 0.04 Add exception handling for ICUMX_WDTA.
* : 02.02.2022 0.05 Add MFIS Lock/Unlock.
* : 22.06.2022 0.06 Replace address align check to function.
* : Remove some defines.
* : 20.12.2022 0.07 Add mask when writing to TCR register.
*****************************************************************************/
#include <stdint.h>
#include <mem_io.h>
#include <dma.h>
#include <rpc.h>
#include <log.h>
#include <wdt.h>
#include <mfis.h>
#define DMOR_INIT (uint16_t)(0x0301U)
#define DMOR_HW_INIT (uint16_t)(0x0000U)
#define TCR_CNT_SHIFT (6U)
#define TCR_UPPER8BIT_MASK (0x00FFFFFFU)
#define CHCR_TRN_MODE (0x00105409U)
#define CHCR_TE_BIT (0x00000002U)
#define TE_FLAG (0x00000000U)
#define CHCR_CAE_BIT (0x80000000U)
#define CHCR_CAE_BIT_NOERROR (0x00000000U)
#define CHCR_CAIE_BIT (0x40000000U)
#define CHCR_DPM_BIT (0x30000000U)
#define CHCR_RPT_BIT (0x0F000000U)
#define CHCR_WAIT_BIT (0x00800000U)
#define CHCR_DPB_BIT (0x00400000U)
#define CHCR_DSE_BIT (0x00080000U)
#define CHCR_DSIE_BIT (0x00040000U)
#define CHCR_DM_BIT (0x0000C000U)
#define CHCR_SM_BIT (0x00003000U)
#define CHCR_RS_BIT (0x00000F00U)
#define CHCR_TS_BIT (0x00300018U)
#define CHCR_IE_BIT (0x00000004U)
#define CHCR_TE_BIT (0x00000002U)
#define CHCR_DE_BIT (0x00000001U)
#define CHCR_CONF_MASK (CHCR_TS_BIT | CHCR_DM_BIT | CHCR_SM_BIT | CHCR_RS_BIT | CHCR_DE_BIT)
#define CHCR_DESCRIPTOR_CONF_MASK (CHCR_DPM_BIT | CHCR_RPT_BIT | CHCR_WAIT_BIT | CHCR_DPB_BIT)
#define CHCR_INTERRUPT_MASK (CHCR_CAIE_BIT | CHCR_DSIE_BIT | CHCR_IE_BIT)
#define CHCR_FLAG_MASK (CHCR_CAE_BIT | CHCR_DSE_BIT | CHCR_TE_BIT)
#define CHCR_ALL_BIT_MASK (CHCR_CONF_MASK | CHCR_DESCRIPTOR_CONF_MASK | CHCR_INTERRUPT_MASK | CHCR_FLAG_MASK)
#define DAR_HW_INIT (0x00000000U)
#define SAR_HW_INIT (0x00000000U)
#define TCR_HW_INIT (0x00000000U)
/* fraction mask for 256-byte units */
#define FRACTION_MASK_256_BYTE (0x000000FFU)
void dma_init(void)
{
uint32_t reg;
/* DMA operation */
mem_write16(RTDMA_DMOR, DMOR_INIT);
/* DMA secure control register */
reg = mem_read32(RTDMA_DMSEC);
reg |= ((uint32_t)1U << DMACH);
mem_write32(RTDMA_DMSEC, reg);
reg = mem_read32(dma_get_rtdma_chcr_addr(DMACH));
reg &= ~(CHCR_ALL_BIT_MASK);
mem_write32(dma_get_rtdma_chcr_addr(DMACH), reg);
}
/* End of function dma_init(void) */
void dma_trans_start(uint32_t dst, uint32_t src, uint32_t len)
{
uint32_t reg;
/* dst and src must be 64-byte boundary. */
dma_address_align_check(dst, src);
/* round up 256 byte alignment */
len += FRACTION_MASK_256_BYTE;
len &= (~(uint32_t)(FRACTION_MASK_256_BYTE));
/* DMA destination address */
mem_write32(dma_get_rtdma_dar_addr(DMACH), dst);
/* DMA source address */
mem_write32(dma_get_rtdma_sar_addr(DMACH), src);
/* DMA 64bytes-unit transfer count */
mem_write32(dma_get_rtdma_tcr_addr(DMACH), ((len >> TCR_CNT_SHIFT) & TCR_UPPER8BIT_MASK));
/* Lock to avoid conflict with RPC */
mfis_lock();
/* DMA channel control */
reg = mem_read32(dma_get_rtdma_chcr_addr(DMACH));
reg |= CHCR_TRN_MODE;
mem_write32(dma_get_rtdma_chcr_addr(DMACH), reg);
}
/* End of function dma_trans_start(uint32_t dst, uint32_t src, uint32_t len) */
void dma_trans_end_check(void)
{
uint32_t reg;
/* Check end of DMA transfer. */
do
{
wdt_restart();
reg = mem_read32(dma_get_rtdma_chcr_addr(DMACH));
/* Check error of DMA transfer */
if ((reg & CHCR_CAE_BIT) != CHCR_CAE_BIT_NOERROR)
{
ERROR("DMA - Channel Address Error\n");
panic;
}
} while ((reg & CHCR_TE_BIT) == TE_FLAG);
reg = mem_read32(dma_get_rtdma_chcr_addr(DMACH));
reg &= ~(CHCR_ALL_BIT_MASK);
mem_write32(dma_get_rtdma_chcr_addr(DMACH), reg);
rpc_end_state_check();
/* Unlock to avoid conflict with RPC */
mfis_unlock();
}
/* End of function dma_trans_end_check(void) */
void dma_release(void)
{
uint32_t reg;
/* DMA channel control */
reg = mem_read32(dma_get_rtdma_chcr_addr(DMACH));
reg &= ~(CHCR_ALL_BIT_MASK);
mem_write32(dma_get_rtdma_chcr_addr(DMACH), reg);
/* DMA destination address */
mem_write32(dma_get_rtdma_dar_addr(DMACH), DAR_HW_INIT);
/* DMA source address */
mem_write32(dma_get_rtdma_sar_addr(DMACH), SAR_HW_INIT);
/* DMA 64bytes-unit transfer count */
mem_write32(dma_get_rtdma_tcr_addr(DMACH), TCR_HW_INIT);
reg = mem_read32(RTDMA_DMSEC);
reg &= (~((uint32_t)1U << DMACH));
mem_write32(RTDMA_DMSEC, reg);
/* DMA operation */
mem_write16(RTDMA_DMOR, DMOR_HW_INIT);
}
/* End of function dma_release(void) */

249
Src/0_Tool/Gen4_R-Car_IPL/SDK/v3_46_0/Gen4_ICUMX_Loader/ip/emmc/emmc_boot.c Normal file
View File

@@ -0,0 +1,249 @@
/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright 2021-2024 Renesas Electronics Corporation All rights reserved.
*******************************************************************************/
/*******************************************************************************
* DESCRIPTION : eMMC boot
******************************************************************************/
/******************************************************************************
* @file emmc_boot.c
* - Version : 0.07
* @brief eMMC initialze interface.
* .
*****************************************************************************/
/******************************************************************************
* History : DD.MM.YYYY Version Description
* : 30.09.2021 0.01 First Release
* : 22.10.2021 0.02 Remove unnecessary code
* : 22.12.2021 0.03 Support static analysis
* : 06.01.2022 0.04 Add WWDT timer reset function
* : 06.04.2022 0.05 Fix Set SDCLK to 200MHz
* : 23.05.2022 0.06 Integration of S4 and V4H
* : 24.06.2024 0.07 Add process that set SDHI_D1.8/3.3V to 1.8V.
*****************************************************************************/
#include "emmc_boot.h"
#include "mem_io.h"
#include "log.h"
#include "rom_api.h"
#include "image_load_emmc.h"
#include "emmc_hal.h"
#include "emmc_std.h"
#include "emmc_multiboot.h"
#include "emmc_def.h"
#include "emmc_config.h"
#if (RCAR_LSI == RCAR_V4M) /* Gray Hawk */
#include "i2c.h"
#include "remap.h"
#endif /* (RCAR_LSI == RCAR_V4M) */
/************************************************************************************************/
/* Definitions */
/************************************************************************************************/
/************************************************************************************************/
/* Unions */
/************************************************************************************************/
/************************************************************************************************/
/* Structs */
/************************************************************************************************/
/************************************************************************************************/
/* Globals */
/************************************************************************************************/
/************************************************************************************************/
/* Macros */
/************************************************************************************************/
/************************************************************************************************/
/* Prototypes */
/************************************************************************************************/
static void power_on_mmc(void);
static void set_sd_clock(void);
static void init_mmc_pin_function(void);
#if (RCAR_LSI == RCAR_V4M) /* Gray Hawk */
static void sdhi_random_address_read_pmic(uint32_t sl_add, uint32_t access_add, uint32_t *rd_buf);
static void sdhi_page_write_pmic(uint32_t sl_add, uint32_t access_add, uint32_t *wr_buf);
static void pmic_set_sdhi_vdd18(void);
#endif /* (RCAR_LSI == RCAR_V4M) */
void emmc_initialize( void )
{
#if (RCAR_LSI == RCAR_V4M) /* Gray Hawk */
/* Register I2C base address(physical:0xE6600000) to SIC REMAP14 for V4M. */
set_sicremap_fcpr();
pmic_set_sdhi_vdd18();
#endif /* (RCAR_LSI == RCAR_V4M) */
/*****************************************************************
PFC setting
*****************************************************************/
init_mmc_pin_function();
/*****************************************************************
CPG setting
*****************************************************************/
power_on_mmc();
set_sd_clock();
#if (RCAR_SA9_TYPE == EMMC_BOOT)
EMMC_ERROR_CODE result;
/* eMMC driver initialize */
(void)emmc_init(); /* Normal clock mode */
/* Card power on */
(void)emmc_memcard_power(TRUE);
/* Card mount */
result = emmc_mount();
if (result != EMMC_SUCCESS)
{
NOTICE("eMMC initialize error!!\n");
panic;
}
#endif /* (RCAR_SA9_TYPE == EMMC_BOOT) */
} /* End of function emmc_initialize( void ) */
/************************************************************************************************/
/* Func power_on_mmc */
/************************************************************************************************/
static void power_on_mmc(void)
{
uint32_t reg;
uint32_t tmp_val;
tmp_val = CPG_MSTPCR_SDHI;
reg = mem_read32(CPG_MSTPCR7D0);
if ((reg & tmp_val) != 0x0U)
{
reg &= ~(tmp_val);
cpg_reg_write(CPG_MSTPCR7D0, CPG_MSTPSR7D0, reg);
}
do
{
reg = mem_read32(CPG_MSTPCR7D0);
}
while ((reg & tmp_val) != 0x0U); /* wait tmp_val=0 */
} /* End of function power_on_mmc(void) */
/************************************************************************************************/
/* Func set_sd_clock */
/************************************************************************************************/
static void set_sd_clock(void)
{
uint32_t reg;
reg = mem_read32(CPG_SD0CKCR0);
reg &= (~(CPG_SD0CKCR0_STP0HCK | CPG_SD0CKCR0_SDSRCFC_MASK | CPG_SD0CKCR0_SD0FC_MASK));
reg |= CPG_SD0CKCR0_200MHZ;
cpg_reg_write(CPG_SD0CKCR0, CPG_SD0CKCR0, reg); /* Stop SDnH clock & SDn=200MHz */
} /* End of function set_sd_clock(void) */
/************************************************************************************************/
/* Func init_mmc_pin_function */
/************************************************************************************************/
static void init_mmc_pin_function(void)
{
uint32_t reg;
reg = mem_read32(PFC_POC_MMC_RW);
reg &= (~(PFC_POC_MMC_MASK));
reg |= PFC_POC_MMC_VAL;
pfc_reg_write(PFC_POC_MMC_RW, reg);
} /* End of function init_mmc_pin_function(void) */
#if (RCAR_LSI == RCAR_V4M) /* Gray Hawk */
static void sdhi_random_address_read_pmic(uint32_t sl_add, uint32_t access_add, uint32_t *rd_buf)
{
uint32_t data;
/* for PMIC_RAA271005 */
data = (access_add & 0x300U) >> 8U;
i2c3_write(sl_add, 0x00U, data); /* Bank Set */
i2c3_read(sl_add, (access_add & 0x0FFU), rd_buf);
}
/* End of function sdhi_random_address_read_pmic(uint32_t sl_add, uint32_t access_add, uint32_t *rd_buf) */
static void sdhi_page_write_pmic(uint32_t sl_add, uint32_t access_add, uint32_t *wr_buf)
{
uint32_t data;
/* for PMIC_RAA271005 */
data = (access_add & 0x300U) >> 8U;
i2c3_write(sl_add, 0x00U, data); /* Bank Set */
i2c3_read(sl_add, (access_add & 0x0FFU), wr_buf);
}
/* End of function sdhi_page_write_pmic(uint32_t sl_add, uint32_t access_add, uint32_t *wr_buf) */
static void pmic_set_sdhi_vdd18(void)
{
/* In case of Gray Hawk board, change SDHI_18/33 voltage. */
uint32_t slv_addr = 0xA8U; /* for PMIC-RAA271005: "reg 0xA8 0xA9 prot 0xAA 0xAB" */
uint32_t data;
/* Init I2C */
i2c3_init();
/* Setting 1.8V to SDHI_D1.8/3.3V(VDDQ18_33_SDHI) on PMIC-RAA271005 */
data = 0x1U;
i2c3_write(slv_addr, 0x00U, data); /* Write IO_PAGE. Chenge BANK1 */
i2c3_read(slv_addr, 0x3BU, &data);
if ((data & 0x0CU) != 0x0U)
{
data &= ~(0x0CU);
i2c3_write(slv_addr, 0x3BU, data);
}
sdhi_random_address_read_pmic(slv_addr, 0x02U, &data);
if ((data & 0xF0U) == 0xB0U)
{
// RAA271005 rev.B only
data = 0x1U;
sdhi_page_write_pmic(slv_addr, 0x00U, &data); /* Write IO_PAGE. Chenge BANK1 */
sdhi_random_address_read_pmic(slv_addr, 0x3BU, &data); /* Read FLT_CTRL1 */
data &= 0xF3U; /* LDO1 Fault remove */
sdhi_page_write_pmic(slv_addr, 0x3BU, &data); /* Write FLT_CTRL1 */
data = 0x0U;
sdhi_page_write_pmic(slv_addr, 0x00U, &data); /* Write IO_PAGE. Chenge BANK0 */
}
data = 0x75U; /* LDO voltage 1.8V Value */
i2c3_write(slv_addr, 0xBAU, data);
sdhi_random_address_read_pmic(slv_addr, 0xBAU, &data);
}
/* End of function pmic_set_sdhi_vdd18(void) */
#endif /* (RCAR_LSI == RCAR_V4M) */

Some files were not shown because too many files have changed in this diff Show More