diff --git a/Customer/MOBIS/PRK3_(ADAS_Parking3)/0_MTG/20260312_Mobis.txt b/Customer/MOBIS/PRK3_(ADAS_Parking3)/0_MTG/20260312_Mobis.txt
new file mode 100644
index 00000000..4200355f
--- /dev/null
+++ b/Customer/MOBIS/PRK3_(ADAS_Parking3)/0_MTG/20260312_Mobis.txt
@@ -0,0 +1,1196 @@
+/*****************************************************************************
+**                                    MOBIS
+**
+** MOBIS owns all the rights to this work. This work shall not be copied,
+** reproduced, used, modified or its information disclosed without the prior
+** written authorization of MOBIS.
+**
+*****************************************************************************/
+/****************************************************************************
+**  FILE NAME               :   Cdd_PMIC.c
+**  MODULE NAME             :  
+*****************************************************************************
+*****************************************************************************
+** Description              :  * @brief   PMIC (Power Management IC) driver implementation.
+                               * @details Provides initialization, I2C communication\n
+                                 CRC calculation, and watchdog Q&A serving mechansim for the RAA271005 PMIC.
+ 
+** Product                  :  
+** ENVIRONMENT              :
+** Controller               :  Renesas R-CAR V4H
+** Compiler                 :  
+** Linker                   :
+** Assembler                :
+** Version Number           :  
+** Routines in this file    :  
+** Configuration Identifier :   ADAS_PRK3
+** Revision History         :
+** Created by               :   Tharun Sripathi / Abul Fazal    Date : 2025/07/22
+** Description              :  
+** Modified by              :   NA                              Date : NA
+** Description              :   NA
+** Platform Dependent[yes/no]           :   No
+** To be changed by USER [yes/no]       :   No
+*****************************************************************************/
+ 
+/*******************************************************************************
+*                              Include Files
+******************************************************************************/
+ 
+#include "Cdd_PMIC.h"
+#include "CDD_Iic_Cbk.h"
+#include "Platform_Types.h"
+#include "CDD_Iic.h"
+#include "Dio.h"
+#include "Dio_Cfg.h"
+#include "rtwtypes.h"
+ 
+/*******************************************************************************
+*                              Macro Definitions
+******************************************************************************/
+ 
+#define IIC_TIME_MAX                1000U
+#define CPGWPR                      *((volatile uint32 *)(0xE6150000UL))
+#define SRCR5                       *(volatile uint32 *) 0xE6152C14UL
+#define SRSTCLR5                    *(volatile uint32 *) 0xE6152C94UL
+#define CDDIIC_HW_CH5_RESET         (1 << 23)
+#define CRC8_POLY                   0x07U  /* CRC-8 polynomial: x^8 + x^2 + x^1 + 1 */
+ 
+ 
+/*******************************************************************************
+*                              Global Variables
+******************************************************************************/
+ 
+/**
+ * @brief   End notice flag for I2C operations.
+ */
+volatile uint8 END_NOTICE_Flag;
+ 
+/**
+ * @brief   Register read values.
+ */
+extern uint8 read_reg_0x11D;
+ 
+/**
+ * @brief   Counters for QnA serve cases.
+ */
+uint32 serve_cnt_case_Q0 = 0U;
+uint32 serve_cnt_case_Q1 = 0U;
+uint32 serve_cnt_case_Q2 = 0U;
+uint32 serve_cnt_case_Q3 = 0U;
+ 
+/**
+ * @brief   QnA state variable: 0 to read question, 1 to write answer.
+ */
+uint8 Var_Question_Ans = 0U;
+ 
+/**
+ * @brief   Correct answer flag for QnA.
+ */
+uint8 correct_answer = 1U;
+ 
+/**
+ * @brief   Timeout counter and maximum value for I2C operations.
+ */
+uint32 timeout_cnt = 0U;
+ 
+/**
+ * @brief   Data buffers for I2C communication.
+ */
+static uint8 LucSendData[32] = {0U};
+static uint8 LucRcvData[32] = {0U};
+ 
+// IIC Write
+static uint8 pgTxBuf[3] = {0U};     /* [Page Address, Data, CRC] */
+static uint8 pgRxBuf[2] = {0U};     /* [Data, CRC] */
+static uint8 pgCrcIn[4] = {0U};     /* [SlaveAddr(W), Address, SlaveAddr(R), Data] */
+static uint8 dataTxBuf[3] = {0U};
+static uint8 dataCrcIn[3] = {0U};
+ 
+// IIC Read
+static uint8 txBuf[1] = {0U};
+static uint8 rxBuf[2] = {0U};      /* [Read Data, CRC from PMIC] */
+static uint8 crcInput[4] = {0U};   /* [SlaveAddr(W), RegAddr, SlaveAddr(R), Read Data] */
+/**
+ * @brief   QnA question and answer temporary variables.
+ */
+uint8 qawdt_question_register;
+uint8 qawdt_question_tmp;
+uint8 qawdt_answer_tmp;
+ 
+uint8 buffer[256] = {0x00};
+uint8 crc_input[256] = {0x00};
+ 
+/*******************************************************************************
+*                              Function Prototypes
+******************************************************************************/
+/**
+* @brief   Calculate CRC-8 for a data buffer.
+* @param   data    Pointer to the data buffer.
+* @param   length  Number of bytes in the buffer.
+* @return  CRC-8 value.
+*/
+ 
+uint8 crc8(const uint8 *data, uint32 length)
+{
+    uint8 crc = 0x00U;  /* Initial value */
+ 
+    for (uint8 i = 0U; i < length; ++i) {
+        crc ^= data[i];  /* XOR byte into CRC */
+        for (uint8 j = 0U; j < 8U; ++j) {
+            if (crc & 0x80U) {
+                crc = (crc << 1) ^ CRC8_POLY;
+            } else {
+                crc <<= 1;
+            }
+        }
+    }
+    return crc;
+}
+ 
+/**
+* @brief   Write data with CRC over I2C.
+* @param   data            Pointer to data buffer.
+* @param   length          Number of bytes to send.
+* @param   LpSlaveConfig   Pointer to I2C slave configuration.
+*/
+ 
+volatile uint32 Iic_Write_Call_Cnt = 1;
+volatile uint32 Iic_Write_Ret_Cnt = 1;
+ 
+void IIC_Write_with_crc_Protection(const uint8 *data, uint32 length, IicSlaveConfigPtr LpSlaveConfig)
+{
+    uint8 address_byte = 0x00U;
+   
+    if (length + 1 > sizeof(buffer)) {
+        return;  /* Prevent overflow */
+    }
+ 
+    for (uint32 i = 0U; i < length; ++i) {
+        buffer[i] = data[i];
+    }
+    address_byte = (PMIC_PROTECTION_SLAVE_ADDR << 1) | 0x00U;  /* Write operation */
+    crc_input[0] = address_byte;
+    for (uint32 i = 0U; i < length; ++i) {
+        crc_input[i + 1] = data[i];
+    }
+    buffer[length] = crc8(crc_input, length + 1);
+    /* ...existing code... */
+    SOC_to_PMIC_I2C_Message_Count(length, LpSlaveConfig);  /* I2C message count */
+    //Iic_Write_Call_Cnt += 5;
+    CddIic_Ch5Write(&buffer[0], length + 1, LpSlaveConfig);
+    //Iic_Write_Ret_Cnt += 5;
+}
+ 
+void IIC_Write_with_crc_Regulation(const uint8 *data, uint32 length, IicSlaveConfigPtr LpSlaveConfig) {
+    //uint8 buffer[256]; // Ensure this is large enough
+    uint8 address_byte  = 0x00 ;
+   
+    if (length + 1 > sizeof(buffer)) return; // Prevent overflow
+ 
+    for (uint32 i = 0; i < length; ++i) {
+        buffer[i] = data[i];
+    }
+     address_byte = ( PMIC_REGULATION_SLAVE_ADDR << 1) | 0x00; // Write operation
+    crc_input[0] = address_byte; // Write operation
+    for (uint32 i = 0; i < length; ++i) {
+        crc_input[i + 1] = data[i];
+    }
+    buffer[length] = crc8(crc_input, length + 1);
+    // Copy data
+    SOC_to_PMIC_I2C_Message_Count(length,LpSlaveConfig); /*I2C message count */
+    CddIic_Ch5Write(&buffer[0], length + 1, LpSlaveConfig);
+}
+ 
+void IIC_Read_with_crc_Protection(const uint8 *data, uint32 length, IicSlaveConfigPtr LpSlaveConfig)
+{
+    uint8 address_byte  = 0x00 ;
+ 
+    if (length + 1 > sizeof(buffer)) return; // +1 for CRC
+    for (uint32 i = 0; i < length; ++i) {
+        buffer[i] = data[i];
+    }
+     address_byte = ( PMIC_PROTECTION_SLAVE_ADDR << 1) | 0x01; // Write operation
+    crc_input[0] = address_byte; // Write operation
+    for (uint32 i = 0; i < length; ++i) {
+        crc_input[i + 1] = data[i];
+    }
+    // Calculate and append CRC
+    buffer[length] = crc8(crc_input, length + 1);
+    SOC_to_PMIC_I2C_Message_Count(length,LpSlaveConfig); /*I2C message count */
+    CddIic_Ch5Read(&buffer[0], length + 1, LpSlaveConfig);
+}
+void IIC_Read_with_crc_Regulation(const uint8 *data, uint32 length, IicSlaveConfigPtr LpSlaveConfig)
+{
+    uint8 address_byte  = 0x00 ;
+   
+    if (length + 1 > sizeof(buffer)) return; // +1 for CRC
+    for (uint32 i = 0; i < length; ++i) {
+        buffer[i] = data[i];
+    }
+     address_byte = ( PMIC_REGULATION_SLAVE_ADDR << 1) | 0x01; // Write operation
+    crc_input[0] = address_byte; // Write operation
+    for (uint32 i = 0; i < length; ++i) {
+        crc_input[i + 1] = data[i];
+    }
+    // Calculate and append CRC
+    buffer[length] = crc8(crc_input, length + 1);
+    SOC_to_PMIC_I2C_Message_Count(length,LpSlaveConfig); /*I2C message count */
+    CddIic_Ch5Read(&buffer[0], length + 1, LpSlaveConfig);
+}
+ 
+/**
+* @brief   Perform I2C write operation to a register.
+* @param   LucSendData     Pointer to data buffer.
+* @return  Value read from the register.
+*/
+ 
+uint8 IIC_WritetoProtReg_operation(uint8 *LucSendData)
+{  
+    uint8 read_LucSendData[32];
+    read_LucSendData[0] = LucSendData[0];
+    read_LucSendData[1] = LucSendData[1];
+    read_LucSendData[2] = LucSendData[2];      
+    read_LucSendData[3] = LucSendData[3];    
+ 
+    IIC_CH5_Reset();
+    END_NOTICE_Flag = 0;
+    SOC_to_PMIC_I2C_Message_Count(2,&CddIic_GaaSlaveConfig[1]); /*I2C message count */
+    CddIic_Ch5Write(&read_LucSendData[0], 2, &CddIic_GaaSlaveConfig[1]);
+    IIC_WaitForCompletion();
+   
+    SOC_to_PMIC_I2C_Message_Count(2,&CddIic_GaaSlaveConfig[1]); /*I2C message count */          
+    //IO_PAGE
+    CddIic_Ch5Write(&read_LucSendData[0], 2, &CddIic_GaaSlaveConfig[1]);
+    IIC_WaitForCompletion();
+   
+    SOC_to_PMIC_I2C_Message_Count(2,&CddIic_GaaSlaveConfig[1]); /*I2C message count */
+    //value update
+    CddIic_Ch5Write(&read_LucSendData[2], 2, &CddIic_GaaSlaveConfig[1]);
+    IIC_WaitForCompletion();
+   
+    #if (PMIC_REG_WRITE_VERIFY == STD_ON)
+    CddIic_Ch5Write(&read_LucSendData[2], 1, &CddIic_GaaSlaveConfig[1]);
+    IIC_WaitForCompletion();
+   
+    CddIic_Ch5Read(&LucRcvData[0], 1, &CddIic_GaaSlaveConfig[1]);
+    IIC_WaitForCompletion();
+    #endif
+return LucRcvData[0] ;
+}
+ 
+uint8 IIC_CRC_WritetoProtReg_operation(uint8 *LucSendData)
+{  
+    uint8 read_LucSendData[32];
+    read_LucSendData[0] = LucSendData[0];
+    read_LucSendData[1] = LucSendData[1];
+    read_LucSendData[2] = LucSendData[2];      
+    read_LucSendData[3] = LucSendData[3];
+    IIC_CH5_Reset();
+    END_NOTICE_Flag = 0;
+    IIC_Write_with_crc_Protection(&read_LucSendData[0], 2, &CddIic_GaaSlaveConfig[1]);
+    IIC_WaitForCompletion();
+    IIC_Write_with_crc_Protection(&read_LucSendData[0], 2, &CddIic_GaaSlaveConfig[1]);
+    IIC_WaitForCompletion();
+    IIC_Write_with_crc_Protection(&read_LucSendData[2], 2, &CddIic_GaaSlaveConfig[1]);
+    IIC_WaitForCompletion();
+    #if (PMIC_REG_WRITE_VERIFY == STD_ON)
+    CddIic_Ch5Write(&read_LucSendData[2], 1, &CddIic_GaaSlaveConfig[1]);
+    IIC_WaitForCompletion();
+    IIC_Read_with_crc_Protection(&LucRcvData[0], 1, &CddIic_GaaSlaveConfig[1]);
+    IIC_WaitForCompletion();
+    #endif
+    return LucRcvData[0] ;
+}
+ 
+ 
+ 
+uint8 IIC_ReadFromProtReg_operation(uint8 *LucSendData0)
+{  
+    uint8 read_LucSendData[32];
+    read_LucSendData[0] = LucSendData0[0];
+    read_LucSendData[1] = LucSendData0[1];
+    read_LucSendData[2] = LucSendData0[2];
+    IIC_CH5_Reset();
+    END_NOTICE_Flag = 0;    
+    SOC_to_PMIC_I2C_Message_Count(2,&CddIic_GaaSlaveConfig[1]); /*I2C message count */
+    CddIic_Ch5Write(&read_LucSendData[0], 2, &CddIic_GaaSlaveConfig[1]);
+    IIC_WaitForCompletion();
+    SOC_to_PMIC_I2C_Message_Count(2,&CddIic_GaaSlaveConfig[1]); /*I2C message count */
+    CddIic_Ch5Write(&read_LucSendData[0], 2, &CddIic_GaaSlaveConfig[1]);
+    IIC_WaitForCompletion();
+    #if (PMIC_REG_WRITE_VERIFY == STD_ON)
+    CddIic_Ch5Write(&read_LucSendData[2], 1, &CddIic_GaaSlaveConfig[1]);
+    IIC_WaitForCompletion();
+    CddIic_Ch5Read(&LucRcvData[0], 1, &CddIic_GaaSlaveConfig[1]);
+    IIC_WaitForCompletion();
+    #endif  
+return LucRcvData[0] ;
+}
+ 
+uint8 IIC_CRC_ReadFromProtReg_operation(uint8 *LucSendData0)
+{  
+    uint8 read_LucSendData[32];
+    read_LucSendData[0] = LucSendData0[0];
+    read_LucSendData[1] = LucSendData0[1];
+    read_LucSendData[2] = LucSendData0[2];
+    IIC_CH5_Reset();
+    END_NOTICE_Flag = 0;    
+    IIC_Write_with_crc_Protection(&read_LucSendData[0], 2, &CddIic_GaaSlaveConfig[1]);
+    IIC_WaitForCompletion();
+    IIC_Write_with_crc_Protection(&read_LucSendData[0], 2, &CddIic_GaaSlaveConfig[1]);
+    IIC_WaitForCompletion();
+    #if (PMIC_REG_WRITE_VERIFY == STD_ON)
+    CddIic_Ch5Write(&read_LucSendData[2], 1, &CddIic_GaaSlaveConfig[1]);
+    IIC_WaitForCompletion();
+    IIC_Read_with_crc_Protection(&LucRcvData[0], 1, &CddIic_GaaSlaveConfig[1]);
+    IIC_WaitForCompletion();
+    #endif  
+return LucRcvData[0] ;
+}
+ 
+uint8 IIC_CRC_ReadFromReguReg_operation(uint8 *LucSendData0)
+{  
+    uint8 read_LucSendData[32];
+    read_LucSendData[0] = LucSendData0[0];
+    read_LucSendData[1] = LucSendData0[1];
+    read_LucSendData[2] = LucSendData0[2];
+    IIC_CH5_Reset();
+    END_NOTICE_Flag = 0;    
+    IIC_Write_with_crc_Regulation(&read_LucSendData[0], 2, &CddIic_GaaSlaveConfig[0]);
+    IIC_WaitForCompletion();
+    IIC_Write_with_crc_Regulation(&read_LucSendData[0], 2, &CddIic_GaaSlaveConfig[0]);
+    IIC_WaitForCompletion();
+    #if (PMIC_REG_WRITE_VERIFY == STD_ON)
+    CddIic_Ch5Write(&read_LucSendData[2], 1, &CddIic_GaaSlaveConfig[0]);
+    IIC_WaitForCompletion();
+    IIC_Read_with_crc_Regulation(&LucRcvData[0], 1, &CddIic_GaaSlaveConfig[0]);
+    IIC_WaitForCompletion();
+    #endif  
+return LucRcvData[0] ;
+}
+ 
+void PMIC_RAA271005_FORCE_ERROR_ST()
+{
+ LucSendData[0] = 0x00;
+ LucSendData[1] = 0x00;
+ LucSendData[2] = 0x0C;
+ LucSendData[3] = 0x00;
+ IIC_CRC_WritetoProtReg_operation(LucSendData);
+ LucSendData[0] = 0x00;
+ LucSendData[1] = 0x00;
+ LucSendData[2] = 0x0C;
+ LucSendData[3] = 0x05;
+ IIC_CRC_WritetoProtReg_operation(LucSendData);
+}
+/**
+* @brief   Main entry point for PMIC RAA271005.
+*/
+ 
+uint8 RAA271005_WDG_Enable(void)
+{
+ 
+         uint8 retVal = PMIC_RETVAL_FAIL;
+         uint8 read_reg_retval = 0;
+ 
+         /*0x107 - WDT_CFG0 Enable WDG*/
+        LucSendData[0] = PMIC_REG_IO_PAGE_8_BIT_REG;
+        LucSendData[1] = PMIC_REG_GET_PAGE(PMIC_REG_WDT_CFG0);
+        LucSendData[2] = PMIC_REG_GET_ADDR(PMIC_REG_WDT_CFG0);
+        LucSendData[3] = PMIC_REG_WDT_CFG0_WWDT_EN_Enable | PMIC_REG_WDT_CFG0_WWDT_ADV_4Q | PMIC_REG_WDT_CFG0_ADV_MODE; //0x05
+ 
+        read_reg_retval = IIC_CRC_WritetoProtReg_operation(LucSendData);
+        #if (PMIC_REG_WRITE_VERIFY == STD_ON)
+        if(read_reg_retval != LucSendData[3])
+               {
+                #if (PMIC_SM_DEBUG_ENABLE == STD_ON)
+                    CtCdLog_AddMsg(LOG_DEFERRED, " WDG Enable failed \r\n");
+                #endif
+                    retVal = PMIC_RETVAL_FAIL;
+               }
+        else
+            {
+            retVal = PMIC_RETVAL_PASS;
+            }
+        #endif
+       
+        return retVal;
+}
+ 
+uint8 RAA271005_WDG_Disable(void)
+{
+        uint8 retVal = PMIC_RETVAL_FAIL;
+        uint8 read_reg_retval = 0;
+ 
+         /*0x107 - WDT_CFG0 Enable WDG*/
+        LucSendData[0] = PMIC_REG_IO_PAGE_8_BIT_REG;
+        LucSendData[1] = PMIC_REG_GET_PAGE(PMIC_REG_WDT_CFG0);
+        LucSendData[2] = PMIC_REG_GET_ADDR(PMIC_REG_WDT_CFG0);
+        LucSendData[3] = PMIC_REG_WDT_CFG0_WWDT_EN_Disable | PMIC_REG_WDT_CFG0_WWDT_ADV_4Q | PMIC_REG_WDT_CFG0_ADV_MODE; //0x05
+ 
+        read_reg_retval = IIC_CRC_WritetoProtReg_operation(LucSendData);
+        #if (PMIC_REG_WRITE_VERIFY == STD_ON)
+        if(read_reg_retval != LucSendData[3])
+               {
+                #if (PMIC_SM_DEBUG_ENABLE == STD_ON)
+                    CtCdLog_AddMsg(LOG_DEFERRED, " WDG Disable failed \r\n");
+                #endif
+                    retVal = PMIC_RETVAL_FAIL;
+               }
+        else
+            {
+            retVal = PMIC_RETVAL_PASS;
+            }
+        #endif
+        LucSendData[0] = 0x00;
+        LucSendData[1] = 0x01;
+        LucSendData[2] = 0x02;
+        LucSendData[3] = 0x65;
+       
+        read_reg_retval = IIC_CRC_WritetoProtReg_operation(LucSendData);
+        return retVal;
+}
+ 
+ 
+uint8 Pmic_RAA271005_Main(void)
+{
+    Pmic_RAA271005_Init();
+}
+ 
+/**
+* @brief   Initialize the RAA271005 PMIC.
+*/
+uint8 Pmic_RAA271005_Init(void)
+{
+        uint8 retVal = PMIC_RETVAL_FAIL;
+        uint8 read_reg_retval = 0;
+       
+        /*108 WDT_CFG1
+        WDT_ULCNT value : 2
+        WDT_LLCNT value : 10 */
+        LucSendData[0] = PMIC_REG_IO_PAGE_8_BIT_REG;
+        LucSendData[1] = PMIC_REG_GET_PAGE(PMIC_REG_WDT_CFG1);
+        LucSendData[2] = PMIC_REG_GET_ADDR(PMIC_REG_WDT_CFG1);
+        LucSendData[3] = 0xA5; // 0x2A;
+ 
+        read_reg_retval = IIC_CRC_WritetoProtReg_operation(LucSendData);
+       
+        #if (PMIC_REG_WRITE_VERIFY == STD_ON)
+        if(read_reg_retval != LucSendData[3])
+            {
+        #if (PMIC_SM_DEBUG_ENABLE == STD_ON)
+            CtCdLog_AddMsg(LOG_DEFERRED, " register WDT_CFG1 write failed \r\n");
+        #endif
+            retVal = PMIC_RETVAL_FAIL;
+            }
+        else
+            {
+            retVal = PMIC_RETVAL_PASS;
+            }
+        #endif
+       
+   
+        /*109 WDT_CFG2
+        WDT_WWDT_ACC_TH 15
+        WDT_ULTICK 10ms
+        WDT_LLTICK 1ms*/
+        LucSendData[0]= PMIC_REG_IO_PAGE_8_BIT_REG;
+        LucSendData[1]= PMIC_REG_GET_PAGE(PMIC_REG_WDT_CFG2);
+        LucSendData[2]= PMIC_REG_GET_ADDR(PMIC_REG_WDT_CFG2);
+        LucSendData[3]= 0x64; //0x63
+   
+        read_reg_retval = IIC_CRC_WritetoProtReg_operation(LucSendData);
+       
+        #if (PMIC_REG_WRITE_VERIFY == STD_ON)
+        if(read_reg_retval != LucSendData[3])
+            {
+        #if (PMIC_SM_DEBUG_ENABLE == STD_ON)
+            CtCdLog_AddMsg(LOG_DEFERRED, " register WDT_CFG2 write failed \r\n");
+        #endif
+            retVal = PMIC_RETVAL_FAIL;
+            }
+        else
+            {
+            retVal = PMIC_RETVAL_PASS;
+            }
+        #endif
+ 
+        /*0x12C - FLT_MASK_B*/
+       //LucSendData[0] = PMIC_REG_IO_PAGE_8_BIT_REG; // IO_PAGE 0x00
+       //LucSendData[1] = PMIC_REG_GET_PAGE(PMIC_REG_FLT_MASK_B); // Page number for FLT_MASK_B
+       //LucSendData[2] = PMIC_REG_GET_ADDR(PMIC_REG_FLT_MASK_B); // Register address for FLT_MASK_B
+       //LucSendData[3] = PMIC_REG_FLT_MASK_B_ALL_UNMASKED; // 0x00
+ 
+       //read_reg_retval = IIC_CRC_WritetoProtReg_operation(LucSendData);
+        //#if (PMIC_REG_WRITE_VERIFY == STD_ON)
+        //if(read_reg_retval != LucSendData[3])
+        //     {
+       //   #if (PMIC_SM_DEBUG_ENABLE == STD_ON)
+        //     CtCdLog_AddMsg(LOG_DEFERRED, " register FLT_MASK_B write failed \r\n");
+       //   #endif
+        //     retVal = PMIC_RETVAL_FAIL;
+        //     }
+        //else
+        //  {
+        //  retVal = PMIC_RETVAL_PASS;
+        //  }
+        //#endif
+       
+        //   LucSendData[0] = PMIC_REG_IO_PAGE_8_BIT_REG; // IO_PAGE 0x00
+        //   LucSendData[1] = PMIC_REG_GET_PAGE(PMIC_REG_FUSA_CTRL_D); // Page number for FUSA_CTRL_D
+        //   LucSendData[2] = PMIC_REG_GET_ADDR(PMIC_REG_FUSA_CTRL_D); // Register address for FUSA_CTRL_D
+        //   LucSendData[3] = (PMIC_REG_FUSA_CTRL_D_EXTPINCHK2_ALL_ENABLE | PMIC_REG_FUSA_CTRL_D_PRESET_CHECK_DIS); // 0x5F
+           
+        //   read_reg_0x11D = IIC_CRC_WritetoProtReg_operation(LucSendData);
+        //   #if (PMIC_REG_WRITE_VERIFY == STD_ON)
+        //   if(read_reg_0x11D != LucSendData[3])
+        //     {
+        //      #if (PMIC_SM_DEBUG_ENABLE == STD_ON)
+        //          CtCdLog_AddMsg(LOG_DEFERRED, " register FUSA_CTRL_D write failed \r\n");
+        //      #endif
+        //          retVal = PMIC_RETVAL_FAIL;
+        //     }
+        //else
+        //  {
+        //  retVal = PMIC_RETVAL_PASS;
+        //  }
+        //#endif
+ 
+         /*0x116 - FUSA_TIMER_1
+         TIMEOUT_MIN_ERROR_ST = 130ms */
+ 
+       //LucSendData[0] = PMIC_REG_IO_PAGE_8_BIT_REG;
+       //LucSendData[1] = PMIC_REG_GET_PAGE(PMIC_REG_FUSA_TIMER_1);
+       //LucSendData[2] = PMIC_REG_GET_ADDR(PMIC_REG_FUSA_TIMER_1);
+       //LucSendData[3] = PMIC_REG_FUSA_TIMER_1_PRESETOUT_128US | PMIC_REG_FUSA_TIMER_1_ERROR_130MS | PMIC_REG_FUSA_TIMER_1_SELFDIAG_2MS; //0x54 - default value
+ 
+       //read_reg_retval = IIC_CRC_WritetoProtReg_operation(LucSendData);
+ 
+        //#if (PMIC_REG_WRITE_VERIFY == STD_ON)
+        //if(read_reg_retval != LucSendData[3])
+        //     {
+        //      #if (PMIC_SM_DEBUG_ENABLE == STD_ON)
+        //          CtCdLog_AddMsg(LOG_DEFERRED, " register FUSA_TIMER_1 write failed \r\n");
+        //      #endif
+        //          retVal = PMIC_RETVAL_FAIL;
+        //     }
+        //else
+        //  {
+        //  retVal = PMIC_RETVAL_PASS;
+        //  }
+        //    #endif
+ 
+        /*0x107 - WDT_CFG0 Enable WDG*/
+        LucSendData[0] = PMIC_REG_IO_PAGE_8_BIT_REG;
+        LucSendData[1] = PMIC_REG_GET_PAGE(PMIC_REG_WDT_CFG0);
+        LucSendData[2] = PMIC_REG_GET_ADDR(PMIC_REG_WDT_CFG0);
+        LucSendData[3] = PMIC_REG_WDT_CFG0_WWDT_EN_Enable | PMIC_REG_WDT_CFG0_WWDT_ADV_4Q | PMIC_REG_WDT_CFG0_ADV_MODE; //0x05
+ 
+        read_reg_retval = IIC_CRC_WritetoProtReg_operation(LucSendData);
+                #if (PMIC_REG_WRITE_VERIFY == STD_ON)
+        if(read_reg_retval != LucSendData[3])
+               {
+        #if (PMIC_SM_DEBUG_ENABLE == STD_ON)
+            CtCdLog_AddMsg(LOG_DEFERRED, " register WDT_CFG0 write failed \r\n");
+        #endif
+            retVal = PMIC_RETVAL_FAIL;
+               }
+        else
+            {
+            retVal = PMIC_RETVAL_PASS;
+            }
+        #endif
+ 
+return retVal;
+ 
+}
+ 
+/**
+* @brief   Serve the 4Q&A Watchdog for RAA271005 PMIC.
+*/
+ 
+void Pmic_RAA271005_QnA4_WDT_serve_question(void)
+{
+    /* WDT_LFSR - Question register for Advance mode WDT Read back this register to get question sent by part. */
+    LucSendData[0] = PMIC_REG_IO_PAGE_8_BIT_REG;
+    LucSendData[1] = PMIC_REG_GET_PAGE(PMIC_REG_WDT_LFSR);
+    LucSendData[2] = PMIC_REG_GET_ADDR(PMIC_REG_WDT_LFSR);
+ 
+    // qawdt_question_register = IIC_Operation_PageSwitch(LucSendData);
+    IIC_CH5_Reset();
+    END_NOTICE_Flag = 0;
+    IIC_Write_with_crc_Protection(&LucSendData[0], 2, &CddIic_GaaSlaveConfig[1]);
+    IIC_WaitForCompletion();
+    // IO_PAGE
+    IIC_Write_with_crc_Protection(&LucSendData[0], 2, &CddIic_GaaSlaveConfig[1]);
+    IIC_WaitForCompletion();
+ 
+    CddIic_Ch5Write(&LucSendData[2], 1, &CddIic_GaaSlaveConfig[1]);
+    IIC_WaitForCompletion();
+    CddIic_Ch5Read(&LucRcvData[0], 2, &CddIic_GaaSlaveConfig[1]);
+    IIC_WaitForCompletion();
+    qawdt_question_register = LucRcvData[0];
+    qawdt_question_tmp = qawdt_question_register >> 6;
+    qawdt_answer_tmp = qawdt_question_register & (0x3F);
+ 
+    LucSendData[0] =    0x00;
+    LucSendData[1] =    0x01;
+    LucSendData[2] =    0x0A;
+    IIC_CRC_ReadFromProtReg_operation(LucSendData);
+}
+ 
+void Pmic_RAA271005_QnA4_WDT_serve_answer(void)
+{
+    /* WDT_LFSR - Question register for Advance mode WDT Read back this register to get question sent by part. */
+    LucSendData[0] = PMIC_REG_IO_PAGE_8_BIT_REG;
+    LucSendData[1] = PMIC_REG_GET_PAGE(PMIC_REG_WDT_LFSR);
+    LucSendData[2] = PMIC_REG_GET_ADDR(PMIC_REG_WDT_LFSR);    
+ 
+ 
+    if (qawdt_question_tmp == 0x00) // copy question bit 5-0 for answer bit 5-0
+    {
+        // delay_1ms();
+        serve_cnt_case_Q0++;
+        LucSendData[0] = PMIC_REG_IO_PAGE_8_BIT_REG;
+        LucSendData[1] = PMIC_REG_GET_PAGE(PMIC_REG_WDT_KICK_REG);
+        LucSendData[2] = PMIC_REG_GET_ADDR(PMIC_REG_WDT_KICK_REG);
+        LucSendData[3] = qawdt_answer_tmp;
+       
+        IIC_CH5_Reset();
+        END_NOTICE_Flag = 0;
+        IIC_Write_with_crc_Protection(&LucSendData[0], 2, &CddIic_GaaSlaveConfig[1]);
+        IIC_WaitForCompletion();
+        // IO_PAGE
+        IIC_Write_with_crc_Protection(&LucSendData[0], 2, &CddIic_GaaSlaveConfig[1]);
+        IIC_WaitForCompletion();
+        // value update
+        IIC_Write_with_crc_Protection(&LucSendData[2], 2, &CddIic_GaaSlaveConfig[1]);
+        IIC_WaitForCompletion();
+    }
+    if (qawdt_question_tmp == 0x01) // shift question bit 5-0 to left by 1 for answer bit 5-0
+    {
+        // delay_1ms();
+        serve_cnt_case_Q1++;
+        LucSendData[0] = PMIC_REG_IO_PAGE_8_BIT_REG;
+        LucSendData[1] = PMIC_REG_GET_PAGE(PMIC_REG_WDT_KICK_REG);
+        LucSendData[2] = PMIC_REG_GET_ADDR(PMIC_REG_WDT_KICK_REG);
+        LucSendData[3] = ((qawdt_answer_tmp << 1) | (qawdt_question_tmp << 6));
+        IIC_CH5_Reset();
+        END_NOTICE_Flag = 0;
+        IIC_Write_with_crc_Protection(&LucSendData[0], 2, &CddIic_GaaSlaveConfig[1]);
+        IIC_WaitForCompletion();
+        // IO_PAGE
+        IIC_Write_with_crc_Protection(&LucSendData[0], 2, &CddIic_GaaSlaveConfig[1]);
+        IIC_WaitForCompletion();
+        // value update
+        IIC_Write_with_crc_Protection(&LucSendData[2], 2, &CddIic_GaaSlaveConfig[1]);
+        IIC_WaitForCompletion();
+    }
+    if (qawdt_question_tmp == 0x02) // shift question bit 5-0 to right by 1 for answer bit 5-0
+    {
+        // delay_1ms();
+        serve_cnt_case_Q2++;
+        LucSendData[0] = PMIC_REG_IO_PAGE_8_BIT_REG;
+        LucSendData[1] = PMIC_REG_GET_PAGE(PMIC_REG_WDT_KICK_REG);
+        LucSendData[2] = PMIC_REG_GET_ADDR(PMIC_REG_WDT_KICK_REG);
+        LucSendData[3] = ((qawdt_answer_tmp >> 1) | (qawdt_question_tmp << 6));
+        IIC_CH5_Reset();
+        END_NOTICE_Flag = 0;
+        IIC_Write_with_crc_Protection(&LucSendData[0], 2, &CddIic_GaaSlaveConfig[1]);
+        IIC_WaitForCompletion();
+        // IO_PAGE
+        IIC_Write_with_crc_Protection(&LucSendData[0], 2, &CddIic_GaaSlaveConfig[1]);
+        IIC_WaitForCompletion();
+        // value update
+        IIC_Write_with_crc_Protection(&LucSendData[2], 2, &CddIic_GaaSlaveConfig[1]);
+        IIC_WaitForCompletion();
+    }
+    if (qawdt_question_tmp == 0x03) // Invert the question bit 5-0 for answer bit 5-0
+    {
+        // delay_1ms();
+        serve_cnt_case_Q3++;
+        LucSendData[0] = PMIC_REG_IO_PAGE_8_BIT_REG;
+        LucSendData[1] = PMIC_REG_GET_PAGE(PMIC_REG_WDT_KICK_REG);
+        LucSendData[2] = PMIC_REG_GET_ADDR(PMIC_REG_WDT_KICK_REG);
+        LucSendData[3] = ((~qawdt_answer_tmp) | (qawdt_question_tmp << 6));
+        IIC_CH5_Reset();
+        END_NOTICE_Flag = 0;
+        IIC_Write_with_crc_Protection(&LucSendData[0], 2, &CddIic_GaaSlaveConfig[1]);
+        IIC_WaitForCompletion();
+        // IO_PAGE
+        IIC_Write_with_crc_Protection(&LucSendData[0], 2, &CddIic_GaaSlaveConfig[1]);
+        IIC_WaitForCompletion();
+        // value update
+        IIC_Write_with_crc_Protection(&LucSendData[2], 2, &CddIic_GaaSlaveConfig[1]);
+        IIC_WaitForCompletion();
+    }
+ 
+    // read error count
+    //LucSendData[0] =  0x00;
+    //LucSendData[1] =  0x01;
+    //LucSendData[2] =  0x0A;
+    //IIC_CRC_ReadFromProtReg_operation(LucSendData);
+}
+ 
+/*******************************************************************************
+*                              Function Prototypes
+******************************************************************************/
+ 
+/**
+* @brief   Wait for I2C operation completion with timeout.
+* @details Waits for END_NOTICE_Flag to become 3 or timeout to expire.
+* @param   timeout_counter  Pointer to timeout counter variable
+* @param   timeout_max      Maximum timeout value
+*/
+volatile static uint32 CddIicCh5_Count = 0;
+void IIC_WaitForCompletion_WithTimeout(uint32 *timeout_counter, uint32 timeout_max)
+{
+    while ((END_NOTICE_Flag != 3) && (*timeout_counter < timeout_max))
+    {
+        (*timeout_counter)++;
+        CddIicCh5_Count++;
+    }
+    *timeout_counter = 0;
+    CddIicCh5_Count = 0;
+ 
+    //Woody_IIC_Delay_us(250);
+ 
+    // Reset IIC channel and flag after completion    
+    IIC_CH5_Reset();
+    END_NOTICE_Flag = 0;
+    //Woody_IIC_Force_Status_Reset(5);
+ 
+    // Woody
+    //if (CDDIIC_CH_SENDING == CddIic_GpChannelStatus[5].enChSta ){
+    //    CddIicCh5_Count++;
+    //    CddIic_GpChannelStatus[5].enChSta = CDDIIC_CH_IDLE;
+    //}
+}
+ 
+/**
+* @brief   Wait for I2C operation completion with default timeout.
+* @details Waits for END_NOTICE_Flag to become 3 or timeout to expire using default timeout settings.
+*/
+void IIC_WaitForCompletion(void)
+{
+    IIC_WaitForCompletion_WithTimeout(&timeout_cnt, IIC_TIME_MAX);
+}
+ 
+ 
+/*I2C message counter, Counting Number of I2C attempts from SOC end  */
+ 
+uint8 u8_slave_id=0;
+uint8 u8_temp_buf[50];
+uint16 u16_PMIC_write_cnt=0;
+ 
+void SOC_to_PMIC_I2C_Message_Count(uint32 length,uint8* LpSlaveConfig )
+{
+  u8_slave_id=LpSlaveConfig[16];
+  if((u8_slave_id == 0x55) && (length==2)) /* 0x55-> Protected Block, length 2->  mean 1 proper Message count resecptive with the PMIC count */
+    {
+       u16_PMIC_write_cnt++;
+      if(u16_PMIC_write_cnt == RESET_SOC_COUNTER) /* Reset the count, It reached the thershold as per SAN */
+        {
+          u16_PMIC_write_cnt=0;
+        }
+     
+    }
+}
+ 
+void Woody_IIC_Delay_us(uint32 us)
+{
+    volatile uint32 count;
+    volatile uint32 loop_limit;
+ 
+    loop_limit = us * 2UL;
+ 
+    for (count = 0; count < loop_limit; count++)
+    {
+        __asm__("nop");
+    }
+ 
+}
+ 
+void Woody_RAA271005_WDG_Init(void)
+{
+    /*0x107 - WDT_CFG0 Disable WDG*/
+    Woody_PMIC_I2C_1Byte_Write_with_crc(PMIC_ADDR_PROTECTION, 0x107, 0x84);
+ 
+    /*0x109 - WDT_CFG2 Disable WDG*/
+    Woody_PMIC_I2C_1Byte_Write_with_crc(PMIC_ADDR_PROTECTION, 0x109, 0x64);
+ 
+    /*0x108 - WDT_CFG1 Disable WDG*/
+    Woody_PMIC_I2C_1Byte_Write_with_crc(PMIC_ADDR_PROTECTION, 0x108, 0xA5);
+ 
+    /*0x107 - WDT_CFG0 Enable WDG*/
+    Woody_PMIC_I2C_1Byte_Write_with_crc(PMIC_ADDR_PROTECTION, 0x107, 0x85);
+   
+}
+ 
+void Woody_Pmic_RAA271005_QnA4_WDT_serve_question_answer(void)
+{
+    /* WDT_LFSR - Question register for Advance mode WDT Read back this register to get question sent by part. */
+    LucSendData[0] = PMIC_REG_GET_ADDR(PMIC_REG_WDT_LFSR);
+    LucSendData[1] = 0x77;
+    LucSendData[2] = 0x88;
+    LucSendData[3] = 0x99;
+ 
+    Woody_PMIC_I2C_1Byte_Read_with_crc(PMIC_ADDR_PROTECTION, 0x0096, &LucRcvData[0]);
+ 
+    qawdt_question_register = LucRcvData[0];
+    qawdt_question_tmp = qawdt_question_register >> 6;
+    qawdt_answer_tmp = qawdt_question_register & (0x3F);
+ 
+    /* WDT_KICK_REG - Answer register */
+    if (qawdt_question_tmp == 0x00) // copy question bit 5-0 for answer bit 5-0
+    {
+        serve_cnt_case_Q0++;        
+        LucSendData[1] = qawdt_answer_tmp;
+       
+        Woody_PMIC_I2C_1Byte_Write_with_crc(PMIC_ADDR_PROTECTION, 0x0095, LucSendData[1]);
+    }
+    if (qawdt_question_tmp == 0x01) // shift question bit 5-0 to left by 1 for answer bit 5-0
+    {
+        serve_cnt_case_Q1++;
+        LucSendData[1] = ((qawdt_answer_tmp << 1) | (qawdt_question_tmp << 6));
+ 
+        Woody_PMIC_I2C_1Byte_Write_with_crc(PMIC_ADDR_PROTECTION, 0x0095, LucSendData[1]);
+    }
+    if (qawdt_question_tmp == 0x02) // shift question bit 5-0 to right by 1 for answer bit 5-0
+    {
+        serve_cnt_case_Q2++;
+        LucSendData[1] = ((qawdt_answer_tmp >> 1) | (qawdt_question_tmp << 6));
+ 
+        Woody_PMIC_I2C_1Byte_Write_with_crc(PMIC_ADDR_PROTECTION, 0x0095, LucSendData[1]);
+    }
+    if (qawdt_question_tmp == 0x03) // Invert the question bit 5-0 for answer bit 5-0
+    {
+        serve_cnt_case_Q3++;
+        LucSendData[1] = ((~qawdt_answer_tmp) | (qawdt_question_tmp << 6));
+ 
+        Woody_PMIC_I2C_1Byte_Write_with_crc(PMIC_ADDR_PROTECTION, 0x0095, LucSendData[1]);
+    }
+}
+ 
+void Woody_IIC_Force_Status_Reset(uint32 LddChannel)
+{
+    /* Initialize enChSta */
+    CddIic_GpChannelStatus[LddChannel].enChSta = CDDIIC_CH_IDLE;
+    /* Initialize ulSndByteNumber */
+    CddIic_GpChannelStatus[LddChannel].ulSndByteNumber = CDDIIC_ZERO_32;
+    /* Initialize ulSndByteSent */
+    CddIic_GpChannelStatus[LddChannel].ulSndByteSent = CDDIIC_ZERO_32;
+    /* Initialize ulRcvByteNumber */
+    CddIic_GpChannelStatus[LddChannel].ulRcvByteNumber = CDDIIC_ZERO_32;
+    /* Initialize ulRcvByteReceieved */
+    CddIic_GpChannelStatus[LddChannel].ulRcvByteReceieved = CDDIIC_ZERO_32;
+    /* Initialize enSlaveAddressMode */
+    CddIic_GpChannelStatus[LddChannel].enSlaveAddressMode = CDDIIC_SEVEN_BIT_ADDR;
+    /* Initialize enDmaStatus */
+    CddIic_GpChannelStatus[LddChannel].enDmaStatus = CDDIIC_DMA_IDLE;
+    /* Initialize enRepeatStartSta */
+    CddIic_GpChannelStatus[LddChannel].enRepeatStartSta = CDDIIC_SND_RPT_STR_RCV_DISABLE;
+}
+ 
+// Do not Test
+void Woody_PMIC_I2C_1Byte_Write(uint8 slaveIdx, uint16 regAdd, uint8 data)
+{
+    uint8 targetPage = (uint8)((regAdd >> 8) & 0xFF);
+    uint8 targetAddr = (uint8)(regAdd & 0xFF);
+    uint8 txBuf[2];
+    uint8 rxBuf[1] = { 0 };
+ 
+    /* 1. Page Switching Logic */
+    if (g_pmic_current_page[slaveIdx] != targetPage)
+    {
+        txBuf[0] = 0x00;        /* Page Selector Register Address */
+        txBuf[1] = targetPage;  /* New Page Value */
+        /* [Hardware Requirement] Reset before 1st Write */
+        Woody_IIC_CH5_Reset();
+        CddIic_Ch5Write(&txBuf[0], 2, &CddIic_GaaSlaveConfig[1]);
+        Woody_I2C_Communication_Complete();
+ 
+        /* [Hardware Requirement] Reset before 2nd Write */
+        Woody_IIC_CH5_Reset();        
+        CddIic_Ch5Write(&txBuf[0], 2, &CddIic_GaaSlaveConfig[1]);
+        Woody_I2C_Communication_Complete();
+ 
+        /* [Hardware Requirement] Reset before Read-back check */
+        Woody_IIC_CH5_Reset();
+        /* Using WriteRead (Repeated Start) for efficient verification */
+        CddIic_Ch5WriteRead(&txBuf[0], 1, &rxBuf[0], 1, &CddIic_GaaSlaveConfig[1]);
+        Woody_I2C_Communication_Complete();
+ 
+        if (rxBuf[0] == targetPage)
+        {
+            g_pmic_current_page[slaveIdx] = targetPage;
+        }
+        else
+        {
+            /* Error Handling: Page switch failed */
+            g_pmic_current_page[slaveIdx] = 0xFF;
+            return;
+        }
+    }
+ 
+    /* 2. Actual Data Write (e.g., Watchdog Kick) */
+    txBuf[0] = targetAddr;
+    txBuf[1] = data;
+    /* [Hardware Requirement] Reset before the final data transmission */
+    Woody_IIC_CH5_Reset();
+    CddIic_Ch5Write(&txBuf[0], 2, &CddIic_GaaSlaveConfig[1]);
+    Woody_I2C_Communication_Complete();
+ 
+}
+ 
+// Do not Test
+void Woody_PMIC_I2C_1Byte_Read(uint8 slaveIdx, uint16 regAdd, uint8 *pData)
+{
+    uint8 targetPage = (uint8)((regAdd >> 8) & 0xFF);
+    uint8 targetAddr = (uint8)(regAdd & 0xFF);
+    uint8 txBuf[1];
+ 
+    /* 1. Page Switching Logic (Same as Write) */
+    if (g_pmic_current_page[slaveIdx] != targetPage)
+    {
+        uint8 pgTxBuf[2];
+        uint8 pgRxBuf[1] = { 0 };
+ 
+        pgTxBuf[0] = 0x00;        /* Page Selector Register Address */
+        pgTxBuf[1] = targetPage;  /* New Page Value */
+ 
+        Woody_IIC_CH5_Reset();
+        CddIic_Ch5Write(&pgTxBuf[0], 2, &CddIic_GaaSlaveConfig[1]);
+        Woody_I2C_Communication_Complete();
+ 
+        Woody_IIC_CH5_Reset();
+        CddIic_Ch5Write(&pgTxBuf[0], 2, &CddIic_GaaSlaveConfig[1]);
+        Woody_I2C_Communication_Complete();
+ 
+        Woody_IIC_CH5_Reset();
+        CddIic_Ch5WriteRead(&pgTxBuf[0], 1, &pgRxBuf[0], 1, &CddIic_GaaSlaveConfig[1]);
+        Woody_I2C_Communication_Complete();
+ 
+        if (pgRxBuf[0] == targetPage)
+        {
+            g_pmic_current_page[slaveIdx] = targetPage;
+        }
+        else
+        {
+            g_pmic_current_page[slaveIdx] = 0xFF; /* Reset cache on failure */
+            return;
+        }
+    }
+ 
+    /* 2. Actual Data Read Logic */
+    txBuf[0] = targetAddr; /* Set register address to read */
+ 
+    /* [Hardware Requirement] Reset before reading */
+    Woody_IIC_CH5_Reset();
+ 
+    CddIic_Ch5WriteRead(&txBuf[0], 1, pData, 1, &CddIic_GaaSlaveConfig[slaveIdx]);
+    /* Wait for the combined Write-Read transaction to finish */
+    Woody_I2C_Communication_Complete();
+}
+ 
+void Woody_PMIC_I2C_1Byte_Write_with_crc(uint8 slaveIdx, uint16 regAdd, uint8 data)
+{
+    uint8 targetPage = (uint8)((regAdd >> 8) & 0xFF);
+    uint8 targetAddr = (uint8)(regAdd & 0xFF);
+    uint8 slaveAddr = 0xFF;
+ 
+    /* 0. SlaveID */
+    if( slaveIdx == PMIC_ADDR_REGULATION ){
+        slaveAddr = PMIC_REGULATION_SLAVE_ADDR;
+    }else{
+        slaveAddr = PMIC_PROTECTION_SLAVE_ADDR;
+    }
+ 
+    /* 1. Page Switching Logic with CRC8 */
+    if (g_pmic_current_page[slaveIdx] != targetPage)
+    {
+        /* Prepare Page Change Packet: Reg 0x00, Target Page */
+        pgTxBuf[0] = 0x00;
+        pgTxBuf[1] = targetPage;
+ 
+        /* CRC for Write: SlaveAddr(w) + RegAddr + Data */
+        pgCrcIn[0] = (slaveAddr << 1) | 0x00U;
+        pgCrcIn[1] = pgTxBuf[0];
+        pgCrcIn[2] = pgTxBuf[1];
+        pgTxBuf[2] = crc8(pgCrcIn, 3);
+ 
+        /* [PMIC Spec] 1st Page Write with CRC */
+        Woody_IIC_CH5_Reset();
+        CddIic_Ch5Write(&pgTxBuf[0], 3, &CddIic_GaaSlaveConfig[slaveIdx]);
+        Woody_I2C_Communication_Complete();
+ 
+        /* [PMIC Spec] 2nd Page Write with CRC */
+        Woody_IIC_CH5_Reset();
+        CddIic_Ch5Write(&pgTxBuf[0], 3, &CddIic_GaaSlaveConfig[slaveIdx]);
+        Woody_I2C_Communication_Complete();
+ 
+        /* [PMIC Spec] Page Read-back Verification with CRC */
+        #if 0
+            /* [V4H IC Spec] */
+            Woody_IIC_CH5_Reset();
+ 
+            /* Write Reg 0x00, then Read 2 bytes (Data + CRC) */
+            CddIic_Ch5WriteRead(&pgTxBuf[0], 1, &pgRxBuf[0], 2, &CddIic_GaaSlaveConfig[slaveIdx]);
+            Woody_IIC_Delay_us(250);
+            Woody_I2C_Communication_Complete();
+        #else
+            Woody_IIC_CH5_Reset();
+            CddIic_Ch5Write(&pgTxBuf[0], 1, &CddIic_GaaSlaveConfig[slaveIdx]);
+            Woody_I2C_Communication_Complete();
+ 
+            Woody_IIC_CH5_Reset();
+            CddIic_Ch5Read(&pgRxBuf[0], 2, &CddIic_GaaSlaveConfig[slaveIdx]);
+            Woody_I2C_Communication_Complete();
+        #endif
+ 
+        /* Verify Read-back CRC: SlaveAddr(W) + RegAddr + SlaveAddr(R) + Received Data */
+        pgCrcIn[0] = (slaveAddr << 1) | 0x00U;
+        pgCrcIn[1] = 0x00;
+        pgCrcIn[2] = (slaveAddr << 1) | 0x01U;
+        pgCrcIn[3] = pgRxBuf[0];
+        if ((crc8(pgCrcIn, 4) == pgRxBuf[1]) && (pgRxBuf[0] == targetPage))
+        {
+            g_pmic_current_page[slaveIdx] = targetPage;
+        }
+        else
+        {
+            g_pmic_current_page[slaveIdx] = 0xFF; /* Switch failed */
+            return;
+        }
+    }
+ 
+    /* 2. Actual Data Write with CRC8 */
+    dataTxBuf[0] = targetAddr;
+    dataTxBuf[1] = data;
+ 
+    /* CRC for Write: SlaveAddr(w) + RegAddr + Data */
+    dataCrcIn[0] = (slaveAddr << 1) | 0x00U;
+    dataCrcIn[1] = dataTxBuf[0];
+    dataCrcIn[2] = dataTxBuf[1];
+    dataTxBuf[2] = crc8(dataCrcIn, 3);
+ 
+    Woody_IIC_CH5_Reset();
+    CddIic_Ch5Write(&dataTxBuf[0], 3, &CddIic_GaaSlaveConfig[slaveIdx]);
+    Woody_I2C_Communication_Complete();
+}
+ 
+void Woody_PMIC_I2C_1Byte_Read_with_crc(uint8 slaveIdx, uint16 regAdd, uint8 *pData)
+{
+    uint8 targetPage = (uint8)((regAdd >> 8) & 0xFF);
+    uint8 targetAddr = (uint8)(regAdd & 0xFF);
+ 
+    uint8 slaveAddr = 0xFF;
+ 
+    /* 0. SlaveID */
+    if( slaveIdx == PMIC_ADDR_REGULATION ){
+        slaveAddr = PMIC_REGULATION_SLAVE_ADDR;
+    }else{
+        slaveAddr = PMIC_PROTECTION_SLAVE_ADDR;
+    }
+ 
+    /* 1. Page Switching Logic (Uses the same full-range CRC logic) */
+    if (g_pmic_current_page[slaveIdx] != targetPage)
+    {
+        Woody_PMIC_I2C_1Byte_Write_with_crc(slaveIdx, (uint16)(targetPage << 8), targetPage);
+        if (g_pmic_current_page[slaveIdx] != targetPage) return;
+    }
+ 
+    /* 2. Actual Data Read with Full-Range CRC8 */
+    #if 1
+        txBuf[0] = targetAddr;
+        Woody_IIC_CH5_Reset();
+   
+        /* Combined Transaction: START + Slave(W) + targetAddr + SR + Slave(R) + Read Data + CRC */
+        CddIic_Ch5WriteRead(&txBuf[0], 1, &rxBuf[0], 2, &CddIic_GaaSlaveConfig[slaveIdx]);
+        Woody_IIC_Delay_us(250);
+        Woody_I2C_Communication_Complete();
+    #else
+        Woody_IIC_CH5_Reset();
+        CddIic_Ch5Write(&txBuf[0], 1, &CddIic_GaaSlaveConfig[slaveIdx]);
+        Woody_I2C_Communication_Complete();
+ 
+        Woody_IIC_CH5_Reset();
+        CddIic_Ch5Read(&rxBuf[0], 2, &CddIic_GaaSlaveConfig[slaveIdx]);
+        Woody_I2C_Communication_Complete();
+    #endif
+ 
+    /* [CRC Calculation based on your spec]
+       Full sequence: SlaveAddr(W) + RegAddr + SlaveAddr(R) + ReadData */
+    crcInput[0] = (slaveAddr << 1) | 0x00U; /* Slave Address + Write Bit */
+    crcInput[1] = txBuf[0];                /* Register Address */
+    crcInput[2] = (slaveAddr << 1) | 0x01U; /* Slave Address + Read Bit */
+    crcInput[3] = rxBuf[0];                /* Data Received from PMIC */
+ 
+    /* Verify if calculated CRC matches the one sent by PMIC */
+    if (crc8(crcInput, 4) == rxBuf[1])
+    {
+        *pData = rxBuf[0];
+    }else{
+        /* CRC Error: Reset page cache to force re-sync and exit */
+        g_pmic_current_page[slaveIdx] = 0xFF;
+        // Optional: Log "Full Range CRC Error"
+        return;
+    }
+}
+ 
+void Woody_IIC_CH5_Reset(void)
+{
+    uint32 val = (uint32)(CDDIIC_HW_CH5_RESET);
+    uint32 timeout = 0x1000UL;
+    volatile uint32 loop_cnt;
+    uint8 ch_idx;
+ 
+    /* 1. Request Hardware Reset */
+    CPGWPR = ~val;
+    SRCR5  = val;
+ 
+    /* 2. Wait until the reset bit is reflected in the register */
+    while (((SRCR5 & val) != val) && (timeout > 0UL))
+    {
+        timeout--;
+    }
+ 
+    /* 3. Release Hardware Reset */
+    CPGWPR   = ~val;
+    SRSTCLR5 = val;
+ 
+    /* 4. Wait for 1us to stabilize the IP (Mandatory for R-Car V4H & V4M)
+    * Based on R52 core @ 1GHz, 1000 iterations of NOP provide approx. 1us.
+    * Use 'asm' to prevent compiler optimization. */
+    for (loop_cnt = 0; loop_cnt < 1000UL; loop_cnt++)
+    {
+        __asm("nop");
+    }
+ 
+    /* 5. Initialize Global Status Variable */    
+    END_NOTICE_Flag = 0;
+ 
+    /* 6. Initialize Software Status Variables for BOTH channels
+    * Since both channels are reset by 'val', both status structures must be cleared. */  
+    CddIic_GpChannelStatus[5].enChSta = CDDIIC_CH_IDLE;
+    CddIic_GpChannelStatus[5].ulSndByteNumber = CDDIIC_ZERO_32;
+    CddIic_GpChannelStatus[5].ulSndByteSent = CDDIIC_ZERO_32;
+    CddIic_GpChannelStatus[5].ulRcvByteNumber = CDDIIC_ZERO_32;
+    CddIic_GpChannelStatus[5].ulRcvByteReceieved = CDDIIC_ZERO_32;
+    CddIic_GpChannelStatus[5].enSlaveAddressMode = CDDIIC_SEVEN_BIT_ADDR;
+    CddIic_GpChannelStatus[5].enDmaStatus = CDDIIC_DMA_IDLE;
+}
+ 
+void Woody_I2C_Communication_Complete(void)
+{
+    uint32 timeout = 0x1000UL;
+ 
+    /* Wait for transfer end notice */
+    while ((END_NOTICE_Flag != 3) && (timeout > 0UL))
+    {
+        timeout--;
+    }
+ 
+}
+ 
+ 
\ No newline at end of file
diff --git a/Customer/MOBIS/PRK3_(ADAS_Parking3)/0_MTG/20260318.txt b/Customer/MOBIS/PRK3_(ADAS_Parking3)/0_MTG/20260318.txt
new file mode 100644
index 00000000..8585b4b5
--- /dev/null
+++ b/Customer/MOBIS/PRK3_(ADAS_Parking3)/0_MTG/20260318.txt
@@ -0,0 +1,9 @@
+
+ÀÎÅÍ·´Æ® ¿ì¼±¼øÀ§
+
+PMIC ¿¡·¯ ¾Æ¿ôDz ¹ÞÀ¸¸é ¹Ù·Î ¸®¼Â. ÀÌ°Å ¸®¼Â ¾ÈÇÏ´Â ¹æ¹ý Àִ°¡?
+CVM ÄÚµå ¾îµð¼­ ®´ÂÁö?
+
+I2C ÇöÀç ¹®Á¦ÀÌ°Å º£Æ®³².
+
+Äھ ¾ÆÅ°ÅØÃÄ ¼³¸í ÀÚ·áÀÛ¼º
\ No newline at end of file
diff --git a/Customer/MOBIS/PRK3_(ADAS_Parking3)/0_MTG/20260320.txt b/Customer/MOBIS/PRK3_(ADAS_Parking3)/0_MTG/20260320.txt
new file mode 100644
index 00000000..17af834f
--- /dev/null
+++ b/Customer/MOBIS/PRK3_(ADAS_Parking3)/0_MTG/20260320.txt
@@ -0,0 +1,19 @@
+
+
+PMIC ¿¡·¯ ¾Æ¿ôDz ¹ÞÀ¸¸é ¹Ù·Î ¸®¼Â. ÀÌ°Å ¸®¼Â ¾ÈÇÏ´Â ¹æ¹ý Àִ°¡?
+
+CVM ÄÚµå ¾îµð¼­ ®´ÂÁö? 
+
+Äھ ¾ÆÅ°ÅØÃÄ ¼³¸í ÀÚ·áÀÛ¼º -> ±èÁ¤¼ö Ã¥ÀÓ´ÔÀÇ Çǵå¹é ¹× Q&A Á¤¸®°¡ ÇÊ¿ä
+
+CVM ÄÚµå ºÐ¼®
+
+I2C
+ - MCAL ÆÀ »ùÇà Test -> Çǵå¹éÇÔ.
+Ãß°¡ ÀÌ°Í Àú°Í TestÇشٶó´Âµ¥ ºôµå ´Ù½Ã Çؼ­ TestÇÒ±î?
+
+
+For your reference, the code is as follows:
+
+I2C ¼³Á¤Çϴµ¥ ¹º°¡ ºüÁø °ÍÀº ¾ø´Â°¡ ? ¹» È®ÀÎÀ» ÇؾߤÁÇϴ°¡?
+Àü¿ªº¯¼ö? Ŭ·°? MPU? µîµî.??
diff --git a/Customer/MOBIS/PRK3_(ADAS_Parking3)/0_MTG/20260324_Mobisì •ë¡€.txt b/Customer/MOBIS/PRK3_(ADAS_Parking3)/0_MTG/20260324_Mobisì •ë¡€.txt
new file mode 100644
index 00000000..4bc782aa
--- /dev/null
+++ b/Customer/MOBIS/PRK3_(ADAS_Parking3)/0_MTG/20260324_Mobisì •ë¡€.txt
@@ -0,0 +1,31 @@
+
+THS -> V4H´Â 4°³ÀÇ THS Placed point°¡ ÀÖ´Ù.
+
+±×¸®°í 4°³ÀÇ TSC¸¦ °¡Áö°í ÀÖ´Ù.
+ÇÏÁö¸¸ MCALÀº 4°³ Áß¿¡¼­ 1°³ÀÇ TSC¸¸ ¼³Á¤ÇÒ ¼ö ÀÖ´Â °Í °°´Ù?
+³»°¡ ÀÌÇØÇÑ °ÍÀÌ ¸Â´Â°¡?
+4°³¸¦ ÀüºÎ »ç¿ëÇÒ ¼ö´Â ¾ø´Â°¡?
+CddThsPtat1~CddThsPtat3¿Í CddThsThcode1~CddThsThcode3´Â ¹«¾ùÀ» ÀǹÌÇϴ°¡?
+¸¸¾à 1°³¸¸ »ç¿ëÇÑ´Ù¸é, TSC1ÀÌ THS1Àΰ¡? Placed point 1
+
+
+CVM ->ÀÌ°Å ¾îµð¼­ ±â´É ±¸ÇöÇؾßÇϳª? Autosar? IPL? -> Áö¶ó¿¡ ¹®ÀÇÇÔ.
+µ¿¿µ»ó °øÀ¯
+½ÃÅ¥Æ÷Å»
+
+
+
+CR-Core Issue
+1. I2C -> ¿öÅ©¾î¶ó¿îµå´Â Àû¿ëµÊ. ¸¶½ºÅÍÄ«¿¡´Â ¹ÌÀû¿ë.
+EVB¿¡¼­´Â ÀçÇöÀÌ µÇ¾ú´Âµ¥. ¿Ö ÇØ°áÀÌ ¾ÈµÇÁö?
+Á» ´Ù¸¥°¡?
+2. CVM -> ¿ÀÅä»ç¿¡¼­ µ¹¾Æ¾ß Çϳª? Á¤È®ÇÏ°Ô ¹¹³Ä?
+3. ÀÎÅÍ·´Æ® ÇÉ
+4. PMIC OTP26.68 °¡ Àß µ¿ÀÛ ÇÏÁö ¾Ê´Â °Í °°À½.
+OTP26.69 »ùÇÃÀº À̹ø´Þ¸» Mobis¿¡ ÀÔ°íµÉ ¿¹Á¤.
+
+AUTOSAR Áö¶ó À̽´¸®½ºÆ® Á¤¸®
+986Àº ¿À´Ã µî·ÏµÈ À̽´.
+921Àº Ä«¸Þ¶ó ÃʱâÈ­ I2C.
+
+±â´É¾ÈÀü À̽´(Fusa)´Â Â÷µ¿ÈÆ Ã¥ÀÓ´Ô
\ No newline at end of file
diff --git a/Customer/MOBIS/PRK3_(ADAS_Parking3)/0_MTG/20260331_Mobisì •ë¡€.txt b/Customer/MOBIS/PRK3_(ADAS_Parking3)/0_MTG/20260331_Mobisì •ë¡€.txt
new file mode 100644
index 00000000..3aaea7fb
--- /dev/null
+++ b/Customer/MOBIS/PRK3_(ADAS_Parking3)/0_MTG/20260331_Mobisì •ë¡€.txt
@@ -0,0 +1,30 @@
+CR-Core Issue
+1. I2C(¿öÅ©¾î¶ó¿îµå·Î ³ª°¨)
+±èÁ¤¼ö Ã¥ÀÓÂÊ¿¡¼­ ¿öÅ©¾î¶ó¿îµåÀû¿ë.
+º£Æ®³² ´ã´çÀÚ°¡ ¿À¸é ¿øÀÎÆľǿ¹Á¤
+
+2. CVM(¿ì¼±¼øÀ§)
+
+3. ÀÎÅÍ·´Æ® ÇÉ
+
+4. PMIC OTP26.68
+ÀÏ´Ü 
+4¿ù 10ÀÏ 26.69 º¸µåÁ¦ÀÛ
+À̹øÁÖ 26.68·Î º¸µå Ãß°¡ Á¦ÀÛ
+
+DV2Â÷´Â 5¿ù Áß¼ø±îÁö. ÀÌÈÄ P1µé¾î°¨
+
+26.68 ÃÖÁ¾ 
+ÃÖÁ¾º¸µå&ÃÖÁ¾ OTP
+
+
+20260331 Á¶¸íÁ¦ ¿¬±¸¿ø Meeting
+
+¸ØÃã
+26.65(8Â÷º¸µå), Àú¿Â¿¡¼­ ºÎÆÃÇϴµ¥ IPL ÀÌ DDRÀ» Àß ¸ø ÄÁÆ®·Ñ ÇÏ°í ÀÖ´Â °Í °°´Ù.
+
+CVM ¸ÕÀú º¸±â
+26.68 ÃÖÁ¾ 
+ÃÖÁ¾º¸µå&ÃÖÁ¾ OTP
+
+PMIC´Â ÈļøÀ§
diff --git a/Customer/MOBIS/PRK3_(ADAS_Parking3)/0_MTG/20260407.txt b/Customer/MOBIS/PRK3_(ADAS_Parking3)/0_MTG/20260407.txt
new file mode 100644
index 00000000..0a46a9e0
--- /dev/null
+++ b/Customer/MOBIS/PRK3_(ADAS_Parking3)/0_MTG/20260407.txt
@@ -0,0 +1,16 @@
+SMA °è¾à½Ã, MCAL ¼­Æ÷Æ®´Â º°µµ Áö¶ó »ý¼ºµÇ´ÂÁö È®ÀÎ.
+
+
+I2C Test¿äû¿Ï·á
+Ãß°¡·Î ¸£³×»ç½º MCAL Ÿ ¸ðµâ(Emm, Iccom, Rfso, Dio, Gpt, Mcu, Port, Spi, Wdg) ¿¡ ´ëÇؼ­µµ ¹®Á¦°¡ ¾øÀ»Áö 
+
+
+EVB·Î ÀÎÅÍ·´Æ® È®ÀÎ ÇÊ¿ä
+
+2. SAN, 6.24.2 => 
+	Start up THS Test -> CR-Core52
+	4.19.1.6 Fault Detection of Safety Mechanism / 6.24.2 Start-up Test for THS
+
+
+EMM
+THS
diff --git a/Customer/MOBIS/PRK3_(ADAS_Parking3)/0_MTG/20260407_Mobisì •ë¡€.txt b/Customer/MOBIS/PRK3_(ADAS_Parking3)/0_MTG/20260407_Mobisì •ë¡€.txt
new file mode 100644
index 00000000..a64dcc59
--- /dev/null
+++ b/Customer/MOBIS/PRK3_(ADAS_Parking3)/0_MTG/20260407_Mobisì •ë¡€.txt
@@ -0,0 +1,9 @@
+
+1. ÀÎÅÍ·´Æ®
+
+2. SAN, 6.24.2 => 
+Start up THS Test -> CR-Core52
+
+3. PMIC IPL Test
+
+4. SoC CVM Test : ÀÌ°Ç ¾î´À ºÎºÐ¸¸ ÇÒ Áö Â÷µ¿ÈÆ Ã¥ÀÓ´ÔÀÌ Á¤¸® ÇÊ¿ä.ÀÓ.
\ No newline at end of file
diff --git a/Customer/MOBIS/PRK3_(ADAS_Parking3)/0_MTG/20260409.txt b/Customer/MOBIS/PRK3_(ADAS_Parking3)/0_MTG/20260409.txt
new file mode 100644
index 00000000..342d7220
--- /dev/null
+++ b/Customer/MOBIS/PRK3_(ADAS_Parking3)/0_MTG/20260409.txt
@@ -0,0 +1,48 @@
+Â÷µ¿ÈÆ Ã¥ÀÓ
+CVM/Thermal Error È®ÀÎÁß(Woody)
+
+1. IPL TEST(Close)
+¿ÍÄ¡µ¶ disable
+
+3. I2C.
+º¸µå ÆíÂ÷ÀÖÀ½.(ÇöÀç »ç¿ëº¸µå´Â OTP26.65)
+¼öÁ¤Àü ÀçÇö(ÀçÇöÇÔ)
+¼öÁ¤ÈÄ ¿¡ÀÌ¡.(Test Start)
+
+3. ÀÎÅÍ·´Æ®
+IRQ0 -> ÀÛ¾÷
+
+4. ICUMX
+MCALÀº ¾ÈµÊ.
+
+5. EMM
+ÀÎÅÍ·´Æ® À¯Àú°¡ Á÷Á¢ Á¦¾î´Â ¾ÈµÊ.
+ISR_common ·ÎÁ÷¿¡¼­ Ŭ¸®¾î¸¦ Çϴµ¥ 
+¾î´À ºÎºÐ¿¡¼­ °è¼Ó ¿¡·¯°¡ ¹ß»ýÇÏ°í ÀÖÀ½.
+
+Çö»óÀº ¾îµð¼±°¡ °è¼Ó ¿¡·¯°¡ ³ª¼­ ISR_common ¿¡¼­ Ŭ¸®¾î¸¦ÇÔ.
+
+¾îÇ÷δ ¾Ë·ÁÁÖÁö ¾ÊÀ½ -> ¾î¶»°Ô ¾îÇÃÀÌ ¾ËÁö?
+
+¶Ç´Ù½Ã ¿¡·¯°¡ ¹ß»ýÇؼ­ ¹«ÇÑ ·çÇÁ.
+
+6.SPI
+ÄÚ¾î2¿¡¼­ ÃÊÀ½ÆÄ.
+0  eep ¿äûÇÒ ¶§¸¸ »ç¿ë
+core0 1 adc 10ms Task, ÀÌ°É ²ô¸é core2 ·Îµå°¡ ÁÙ¾îµë. ·Îµå°¡ 50~60%
+core2 5 ÃÊÀ½ÆÄ  2¸¶ÀÌÅ©·Î Å×½ºÅ© -> ÀÎÅÍ·´Æ® ¿ì¼±¼øÀ§°¡ Á¦ÀÏ ³ôÀ½, cpu·Îµå°¡ ¸¹ÀÌ ³ôÀ½. DDR¶§¹®¿¡ AP¿Í ¿¬°áµÇ¾î ÀÖÀ½.
+µ¥ÀÌÅÍ¿¡´ëÇؼ­¸¸ ½ºÇɶô ¼³Á¤ÇÔ.
+MCAL SPIÅë½Å
+ÃÊÀ½ÆÄ°¡, °æº¸¿òÀÌ 
+Áß°£¿¡ µ¥ÀÌÅÍ ºüÁö´Â °Íµµ À̽´ÀÓ.
+ŸÀ̹ÖÀÌ Á¶±Ý¸¸ Ʋ¾îÁ®µµ ¾ÈµÊ. À̽´ÀÓ.
+Åë½ÅÀÌ ¾ÈµÇ´Â °ÍÀ½ ¾Èµ¼. ÄÚ¾î ·Îµå°¡ 95% -> 90% º°·Î ¼ºÀû¼­¸¦ Á¦ÃâÇؾßÇÔ.
+T1 Tool, Äھ·Î ·ÎµåÃøÁ¤ Task(10msTaskÀִµ¥, 20ms·Î ¼öÇàµÊ), ÀÎÅÍ·´Æ®,
+70%~80%°¡ µÇ¾î¾ßÇÔ.
+ÃÊÀ½ÆÄÂÊ¿¡ ·Îµå¸¦ ÁÙÀÏ ¼ö ÀÖ´Â ¹æ¹ý. ·Îµå
+ÃÊÀ½ÆÄ µ¥ÀÌÅÍ°¡ ·Î½º µÇ°Å³ª µô·¹ÀÌ µÇ¸é ¾ÈµÊ.
+SPI ¸ÖƼ ÄÚ¾î Áö¿øÀÌ µÇ¾î¾ßÇÔ.(½ºÇɶô, ÃÊÀ½ÆÄ, µ¥ÀÌÅÍ ·Î½º, µô·¹ÀÌ) -> ¾ç»ê ºÒ°¡.
+Á¶±Ý¾¿ ²÷±èÀÌ ¹ß»ý.
+
+7.QOS ¼³Á¤ ¹æ¹ý
+(¹®¼­, µ¿ÀÛ ·ÎÁ÷ ¼³¸í),
\ No newline at end of file
diff --git a/Customer/MOBIS/PRK3_(ADAS_Parking3)/0_MTG/20260413_eng.txt b/Customer/MOBIS/PRK3_(ADAS_Parking3)/0_MTG/20260413_eng.txt
new file mode 100644
index 00000000..4910c612
--- /dev/null
+++ b/Customer/MOBIS/PRK3_(ADAS_Parking3)/0_MTG/20260413_eng.txt
@@ -0,0 +1,56 @@
+We are currently discussing the mass production of five upcoming models (including Korea¡¯s top-tier premium flagship) based on the Hyundai Mobis V4H solution. 
+To ensure a successful SOP, the following CR-Core issues must be resolved and closed with the highest priority.
+I have summarized the current CR-Core issues, including the I2C Stuck case, as follows. 
+To ensure smooth mass production, these issues must be closed. 
+The list is categorized by priority (1: Top).
+
+¡á Ultrasonic sensor SPI communication issue (Jira#270), Priority 1
+Current Status: 
+	Excessive CPU load (90-95%) on Core 2 and loss of ultrasonic data.
+Cause:
+	Core 2¡¯s ultrasonic sensor interrupt has the highest priority and takes up a large portion of processing. 
+	Communication delays and disconnections occur due to spinlock application during inter-core SPI communication. 
+	Performance constraints exist due to the DDR and AP connection structure.
+Goal:
+	Achieve core load of 70-80% and ensure data integrity based on the customer¡¯s performance measurement tool.
+Customer Requirement:
+	Implementation of SPI multi-core support is mandatory to prevent ultrasonic data loss/delay. (Mass production is impossible if unresolved)
+
+¡á Inquiry regarding Cortex-R52 Memory Mapping and BAR-based RAM Mirroring for SC3 Environment (Jira#1011), Priority 2
+
+¡á I2C Communication with PMIC (Jira#943, 957), Priority 3
+Status:
+	I have been testing with my own board for 3 days, but the issue was not reproduced. 
+	Therefore, I started an aging test on the customer's reproduction board last Friday evening (April 10th). 
+	I plan to visit the customer site on Tuesday afternoon (April 14th) to check the results.
+
+¡á Functional Safety Verification on CR-Core (Jira#925)
+Status: 
+	1. CVM (4.19.2 Core Voltage Monitor, 6.24.3 Start-up Test for CVM): Woody needs debugging support for this issue.
+	2. THS (Thermal Sensor): Woody needs debugging support for this issue.
+
+¡á Query regarding User-defined Notification/Callback for ECM Interrupts in CDD EMM (Jira#1000)
+Status: 
+	Checking with the MCAL team if the interrupt can be received in a wrapper function.
+
+¡á Request for guidance on External Interrupt (IRQ) implementation without ICU MCAL module (Jira#965)
+Status: 
+	MCAL Team will provide another sample code which does not modify the driver for the customer to consider.
+
+¡á Interface Guidance between CR-Core and ICUMX (Jira#997)
+Status: 
+	Waiting for a response from Renesas on Jira.
+
+¡á AUTOSAR Architecture Review for CR-Core (Jira#942)
+Status:
+	Customer review and Renesas review required.
+
+¡á Documentation regarding QoS, such as an explanation of the operational logic (Jira#998)
+
+¡á PMIC OTP26.68¿¡¼­ Soc Reset Çö»ó ÀÚÁÖ ¹ß»ý
+ÀÌÁØÈ­ Ã¥ÀÓ´Ô IPL FW·Î µ¿ÀÛÈ®ÀÎ ÇÊ¿ä.
+
+
+
+
+
diff --git a/Customer/MOBIS/PRK3_(ADAS_Parking3)/0_MTG/20260413_kr.txt b/Customer/MOBIS/PRK3_(ADAS_Parking3)/0_MTG/20260413_kr.txt
new file mode 100644
index 00000000..869e2310
--- /dev/null
+++ b/Customer/MOBIS/PRK3_(ADAS_Parking3)/0_MTG/20260413_kr.txt
@@ -0,0 +1,95 @@
+¾÷µ¥ÀÌÆ®°¡ ´Ê¾î ¹Ì¾ÈÇÏ´Ù.
+Çö´ë ¸ðºñ½ºÀÇ V4H ¼Ö·ç¼ÇÀ¸·Î Çѱ¹ ³» ÃÖ°í±Þ Â÷Á¾ Æ÷ÇÔ 5 ¸ðµ¨ ¾ç»êÀ» ³íÀÇÇÏ°í ÀÖ´Ù.
+ÇöÀç I2C Stuck °Ç Æ÷ÇÔÇؼ­, CR-CoreÀÇ À̽´¸¦ ¾Æ·¡¿Í °°ÀÌ °£·«ÇÏ°Ô Á¤¸®Çß´Ù.
+¿øÈ°ÇÑ ¾ç»êÀ» À§Çؼ­´Â ÇöÀç ¾Æ·¡ÀÇ À̽´¸¦ Close ÇؾßÇÑ´Ù.
+¿ì¼± ¼øÀ§(1:Top) º°¾Æ·¡¿Í °°´Ù.
+
+I am sorry for the late update.
+We are currently discussing the mass production of five models, including Korea¡¯s most premium vehicle, using Hyundai Mobis's V4H solution.
+I have briefly summarized the CR-Core issues, including the I2C Stuck case, as follows.
+To ensure smooth mass production, these issues must be closed.
+The list is as follows, categorized by priority (1: Top).
+
+¡á Ultrasonic sensor SPI communication issue.(Jira#270), Priority 1
+ÄÚ¾î2¿¡¼­ ÃÊÀ½ÆÄ.
+0  eep ¿äûÇÒ ¶§¸¸ »ç¿ë
+Core0- MSIOF5, ADC IC 10ms Task, ÀÌ°É ²ô¸é core2 ·Îµå°¡ ÁÙ¾îµë. ·Îµå°¡ 50~60%
+          MSIOF4, EEPROM
+Core2- ¤ÑMSIOF1, ÃÊÀ½Æļ¾¼­  2¸¶ÀÌÅ©·Î Å×½ºÅ© -> ÀÎÅÍ·´Æ® ¿ì¼±¼øÀ§°¡ Á¦ÀÏ ³ôÀ½, cpu·Îµå°¡ ¸¹ÀÌ ³ôÀ½. DDR¶§¹®¿¡ AP¿Í ¿¬°áµÇ¾î ÀÖÀ½.
+µ¥ÀÌÅÍ¿¡´ëÇؼ­¸¸ ½ºÇɶô ¼³Á¤ÇÔ.
+MCAL SPIÅë½Å
+ÃÊÀ½ÆÄ°¡, °æº¸¿òÀÌ 
+Áß°£¿¡ µ¥ÀÌÅÍ ºüÁö´Â °Íµµ À̽´ÀÓ.
+ŸÀ̹ÖÀÌ Á¶±Ý¸¸ Ʋ¾îÁ®µµ ¾ÈµÊ. À̽´ÀÓ.
+Åë½ÅÀÌ ¾ÈµÇ´Â °ÍÀ½ ¾Èµ¼. ÄÚ¾î ·Îµå°¡ 95% -> 90% º°·Î ¼ºÀû¼­¸¦ Á¦ÃâÇؾßÇÔ.
+T1 Tool, Äھ·Î ·ÎµåÃøÁ¤ Task(10msTaskÀִµ¥, 20ms·Î ¼öÇàµÊ), ÀÎÅÍ·´Æ®,
+70%~80%°¡ µÇ¾î¾ßÇÔ.
+ÃÊÀ½ÆÄÂÊ¿¡ ·Îµå¸¦ ÁÙÀÏ ¼ö ÀÖ´Â ¹æ¹ý. ·Îµå
+ÃÊÀ½ÆÄ µ¥ÀÌÅÍ°¡ ·Î½º µÇ°Å³ª µô·¹ÀÌ µÇ¸é ¾ÈµÊ.
+SPI ¸ÖƼ ÄÚ¾î Áö¿øÀÌ µÇ¾î¾ßÇÔ.(½ºÇɶô, ÃÊÀ½ÆÄ, µ¥ÀÌÅÍ ·Î½º, µô·¹ÀÌ) -> ¾ç»ê ºÒ°¡.
+Á¶±Ý¾¿ ²÷±èÀÌ ¹ß»ý.
+°á±¹ °¢ Äھ¼­ SPI Åë½ÅÇÏ´Àµ¥ ÀÖ¾î, ½ºÇɶôÀÌ Àû¿ëµÇ¾î ÃÊÀ½ÆÄ ¼¾¼­ÀÇ SPIÅë½ÅÀÌ ´Ê¾îÁö°Å³ª, ²÷±â°Å³ª ÇÏ´Â Çö»óÀÌ ¹ß»ýÇÒ ¼ö ÀÖ´Ù.
+°í°´Àº ÇöÀç ´Ù¸¥ ¹æ¾ÈÀÌ ¾ø°í, SPI°¡ ¸ÖƼÄÚ¾î Áö¿øÀÌ µÇ¾î¾ßµÈ´Ù°í ÇÑ´Ù.
+
+ÃÊÀ½ÆÄ ¼¾¼­ SPI Åë½Å À̽´
+ÇöȲ: Core 2 CPU ·Îµå °ú´Ù(90~95%) ¹× ÃÊÀ½ÆÄ µ¥ÀÌÅÍ À¯½Ç ¹ß»ý.
+¿øÀÎ: Core 2ÀÇ ÃÊÀ½ÆÄ ¼¾¼­ ÀÎÅÍ·´Æ® ¿ì¼±¼øÀ§°¡ °¡Àå ³ô°í ó¸® ºñÁßÀÌ Å­.
+ÄÚ¾î °£ SPI Åë½Å ½Ã ½ºÇɶô Àû¿ëÀ¸·Î ÀÎÇÑ Åë½Å Áö¿¬ ¹× ²÷±è Çö»ó ¹ß»ý.
+DDR ¹× AP ¿¬°á ±¸Á¶¿¡ µû¸¥ ¼º´É Á¦¾à.
+¸ñÇ¥: °í°´»ç ¼º´É ÃøÁ¤ Tool ±âÁØ, ÄÚ¾î ·Îµå 70~80% ´Þ¼º ¹× µ¥ÀÌÅÍ ¹«°á¼º È®º¸.
+°í°´»ç ¿ä±¸»çÇ×: ÃÊÀ½ÆÄ µ¥ÀÌÅÍÀÇ ·Î½º/µô·¹ÀÌ ¹æÁö¸¦ À§ÇÑ SPI ¸ÖƼÄÚ¾î Áö¿ø ±â´É ±¸Çö Çʼö. (¹ÌÇØ°á ½Ã ¾ç»ê ºÒ°¡)
+
+Current Status: Excessive CPU load (90-95%) on Core 2 and loss of ultrasonic data.
+Cause: Core 2¡¯s ultrasonic sensor interrupt has the highest priority and takes up a large portion of processing. Communication delays and disconnections occur due to spinlock application during inter-core SPI communication. Performance constraints exist due to the DDR and AP connection structure.
+Goal: Achieve core load of 70-80% and ensure data integrity based on the customer¡¯s performance measurement tool.
+Customer Requirement: Implementation of SPI multi-core support is mandatory to prevent ultrasonic data loss/delay. (Mass production is impossible if unresolved)
+
+¡á Inquiry regarding Cortex-R52 Memory Mapping and BAR-based RAM Mirroring for SC3 Environment(Jira#1011), Priority 2
+
+¡á I2C Communication with PMIC (Jira#943,957), Priority 3
+[Status description]
+I have been testing with my own board for 3 days, but the issue was not reproduced. 
+Therefore, I started an aging test on the customer's reproduction board last Friday evening (April 10th). 
+I plan to visit the customer site on Tuesday afternoon (April 14th) to check the results.
+
+Woody °¡ °¡Áö°í ÀÖ´Â º¸µå¿¡¼­´Â 3ÀÏ µ¿¾È Test Çߴµ¥ ÀçÇö ¾ÈµÊ.
+°í°´ÀÌ °¡Áö°í ÀÖ´Â ÀçÇö ÀߵǴ º¸µå·Î 4¿ù 10ÀÏ(±Ý) Àú³á, ¿¡ÀÌ¡ Test Start, 4¿ù 14(È­) PM¿¡ ¹æ¹®Çؼ­ °á°ú È®ÀÎ ¿¹Á¤.
+
+¡á Functional Safety Verification on CR-Core (Jira#925)
+	1. CVM(4.19.2 Core Voltage Monitor, 6.24.3 Start-up Test for CVM) : Woody needs debugging support for this issue.
+	2. THS (Thermal Sensor): Woody needs debugging support for this issue.
+
+¡á Query regarding User-defined Notification/Callback for ECM Interrupts in CDD EMM (Jira#1000)
+[Status description]
+20260413 - Checking with the MCAL team if the interrupt can be received in a wrapper function.
+ÀÎÅÍ·´Æ® À¯Àú°¡ Á÷Á¢ Á¦¾î´Â ¾ÈµÊ.
+ISR_common ·ÎÁ÷¿¡¼­ Ŭ¸®¾î¸¦ Çϴµ¥ 
+¾î´À ºÎºÐ¿¡¼­ °è¼Ó ¿¡·¯°¡ ¹ß»ýÇÏ°í ÀÖÀ½.
+
+Çö»óÀº ¾îµð¼±°¡ °è¼Ó ¿¡·¯°¡ ³ª¼­ ISR_common ¿¡¼­ Ŭ¸®¾î¸¦ÇÔ.
+
+¾îÇ÷δ ¾Ë·ÁÁÖÁö ¾ÊÀ½ -> ¾î¶»°Ô ¾îÇÃÀÌ ¾ËÁö?
+
+¶Ç´Ù½Ã ¿¡·¯°¡ ¹ß»ýÇؼ­ ¹«ÇÑ ·çÇÁ.
+
+
+¡á Request for guidance on External Interrupt (IRQ) implementation without ICU MCAL module (Jira#965)
+[Status description]
+GP4_16, GP1_20(Y34)ÀÌ Function1ÀÌ IRQ0 »ç¿ë°¡´ÉÇÑÁö È®ÀÎ.
+MCAL Team will provide an other sample code which not modify driver for customer to consider.
+20260413 - MCAL Team will provide an other sample code which not modify driver for customer to consider.
+
+
+¡á Interface Guidance between CR-Core and ICUMX (Jira#997)
+Waiting for a response from Renesas on Jira.
+
+¡á AUTOSAR Architecture Review for CR-Core (Jira#942)
+[Status description]
+Customer review and Renesas review required.
+°í°´»ç ¸®ºä ¹× Renesas ¸®ºä ÇÊ¿ä
+
+¡á Documentation regarding QoS, such as an explanation of the operational logic.(Jira#998)
+
+
+¡á PMIC OTP26.68¿¡¼­ Soc Reset Çö»ó ÀÚÁÖ ¹ß»ý
+ÀÌÁØÈ­ Ã¥ÀÓ´Ô IPL FW·Î µ¿ÀÛÈ®ÀÎ ÇÊ¿ä.