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woody
2026-06-26 08:03:05 +09:00
parent d90e8cb6a2
commit 48608c9d1f
52 changed files with 15284 additions and 34406 deletions
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Customer/MOBIS/PRK3_(ADAS_Parking3)/Issue/SPI_Multi_Core/Full_Type2/RCar_V4H_Development_19_4_0_SupportMultiCore_Patch_v1.0 2.zip Normal file
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Customer/MOBIS/PRK3_(ADAS_Parking3)/Issue/SPI_Multi_Core/Patch_MCAL_Ver_19.1.0/Multi_Core_SPI_patch_20260514.zip → Customer/MOBIS/PRK3_(ADAS_Parking3)/Issue/SPI_Multi_Core/Like_Type2/Patch_MCAL_Ver_19.1.0/Multi_Core_SPI_patch_20260514.zip
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Customer/MOBIS/PRK3_(ADAS_Parking3)/Issue/SPI_Multi_Core/Patch_MCAL_Ver_19.4.0/Multi_Core_SPI_Patch_20260519.zip → Customer/MOBIS/PRK3_(ADAS_Parking3)/Issue/SPI_Multi_Core/Like_Type2/Patch_MCAL_Ver_19.4.0/Multi_Core_SPI_Patch_20260519.zip
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Customer/MOBIS/PRK3_(ADAS_Parking3)/Issue/SPI_Multi_Core/Patch_MCAL_Ver_19.4.0/Multi_Core_SPI_Patch_20260521.zip → Customer/MOBIS/PRK3_(ADAS_Parking3)/Issue/SPI_Multi_Core/Like_Type2/Patch_MCAL_Ver_19.4.0/Multi_Core_SPI_Patch_20260521.zip
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Customer/MOBIS/PRK3_(ADAS_Parking3)/Issue/SPI_Multi_Core/Patch_MCAL_Ver_19.4.0/Multi_Core_SPI_Patch_20260521/spi_patch_v2_19_4_0.patch
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@@ -1,863 +0,0 @@
diff --git a/rel/modules/spi/include/Spi_Ram.h b/rel/modules/spi/include/Spi_Ram.h
index 8a37e48a36..cdaafc3c7e 100644
--- a/rel/modules/spi/include/Spi_Ram.h
+++ b/rel/modules/spi/include/Spi_Ram.h
@@ -205,6 +205,31 @@ extern volatile VAR(Spi_EBDataType, SPI_VAR_NO_INIT)
#define SPI_START_SEC_VAR_NO_INIT_32
#include "Spi_MemMap.h"
+#if (SPI_SUPPORT_CONCURRENT_ASYNC_TRANSMIT == STD_ON)
+/* Phase 02: per-HW-unit arrays replacing the packed scalar bitmask.
+ * Each element stores 0U (inactive) or 1U (active) for that HW unit index.
+ * No cache-line padding <20> SchM critical sections remain the cross-core guard.
+ * Precedent: Spi_GaaHWStatus uses the same volatile VAR(uint32,...) pattern. */
+
+/* Per-HW-unit sync-active flags (index = ucHWUnitIndex) */
+extern volatile VAR(uint32, SPI_VAR_NO_INIT) Spi_GaaSyncActiveHWUnits[SPI_MAX_HWUNIT];
+/* Per-HW-unit async-active flags (index = ucHWUnitIndex) */
+extern volatile VAR(uint32, SPI_VAR_NO_INIT) Spi_GaaAsyncActiveHWUnits[SPI_MAX_HWUNIT];
+
+#if ((SPI_LEVEL_DELIVERED == SPI_LEVEL_1) || (SPI_LEVEL_DELIVERED == SPI_LEVEL_2))
+/* Per-queue active flags (index = queue index; slot 0 is reserved, never read/written) */
+extern volatile VAR(uint32, SPI_VAR_NO_INIT) Spi_GaaAllQueueSts[SPI_MAX_QUEUE];
+#endif
+
+#if ((SPI_LEVEL_DELIVERED == SPI_LEVEL_2) && (SPI_FORCE_CANCEL_API == STD_ON))
+/* Per-HW-unit cancel flags */
+extern volatile VAR(uint32, SPI_VAR_NO_INIT) Spi_GaaCancelingHWUnits[SPI_MAX_HWUNIT];
+#endif
+
+#else /* SPI_SUPPORT_CONCURRENT_ASYNC_TRANSMIT == STD_OFF */
+/* Legacy scalar bitmask storage <20> byte-identical to pre-Phase-02 behaviour.
+ * Bit layout: lower 16 bits = sync-active per HW unit, upper 16 bits = async-active. */
+
/* Bit array indicates active HW unit index
- The lower 16-bits are for synchronous transmission
- The upper 16-bits are for asynchronous transmission */
@@ -214,10 +239,26 @@ extern volatile VAR(uint32, SPI_VAR_NO_INIT) Spi_GulActiveHWUnits;
(SPI_LEVEL_DELIVERED == SPI_LEVEL_2))
/* Bit array indicates active Queues */
extern volatile VAR(uint32, SPI_VAR_NO_INIT) Spi_GulAllQueueSts;
+#endif
+
+#if ((SPI_LEVEL_DELIVERED == SPI_LEVEL_2) && (SPI_FORCE_CANCEL_API == STD_ON))
+/* Bit array indicates HWUnits is being canceled by Spi_ForceCacel */
+extern volatile VAR(uint32, SPI_VAR_NO_INIT) Spi_GulCancelingHWUnits;
+#endif
+
+#endif /* SPI_SUPPORT_CONCURRENT_ASYNC_TRANSMIT */
+
/* Bit array indicates active Sequences */
+#if ((SPI_LEVEL_DELIVERED == SPI_LEVEL_1) || \
+ (SPI_LEVEL_DELIVERED == SPI_LEVEL_2))
+#if (SPI_SUPPORT_CONCURRENT_ASYNC_TRANSMIT == STD_ON)
+extern volatile VAR(uint32, SPI_VAR_NO_INIT)
+ Spi_GaaActiveSequence[SPI_MAX_HWUNIT][SPI_BITS_TO_WORDS(SPI_MAX_SEQUENCE)];
+#else
extern volatile VAR(uint32, SPI_VAR_NO_INIT)
Spi_GaaActiveSequence[SPI_BITS_TO_WORDS(SPI_MAX_SEQUENCE)];
#endif
+#endif
#if (SPI_MAX_CHANNEL_BUFFER_SIZE > 0U)
/* Channel buffer, includes all tx and rx buffers for all channels
@@ -231,14 +272,379 @@ extern volatile VAR(uint32, SPI_VAR_NO_INIT)
extern volatile VAR(uint32, SPI_VAR_NO_INIT) Spi_GulDmaRxData;
#endif
-#if ((SPI_LEVEL_DELIVERED == SPI_LEVEL_2) && (SPI_FORCE_CANCEL_API == STD_ON))
-/* Bit array indicates HWUnits is being canceled by Spi_ForceCacel */
-extern volatile VAR(uint32, SPI_VAR_NO_INIT) Spi_GulCancelingHWUnits;
-#endif
-
+/*===========================================================================*/
+/* CRITICAL FIX: Close the VAR_NO_INIT_32 section HERE <20> before any inline */
+/* function definitions. Inline functions must NOT be inside a MemMap */
+/* section, as they are code, not data. Placing SPI_STOP_SEC_VAR_NO_INIT_32 */
+/* inside a conditional #if block (as in the broken version) causes the */
+/* section to remain open when that condition is false, which puts the */
+/* static inline functions into the data section and triggers the */
+/* "section type conflict" error from the compiler. */
+/*===========================================================================*/
#define SPI_STOP_SEC_VAR_NO_INIT_32
#include "Spi_MemMap.h"
+/*******************************************************************************
+** Phase 02: Macro abstraction layer <20> diverges on SPI_SUPPORT_CONCURRENT_ **
+** ASYNC_TRANSMIT. STD_ON uses per-HW-unit arrays; STD_OFF uses the legacy **
+** packed scalar bitmask. Call sites are identical in both configurations. **
+** **
+** NOTE: All inline functions and macros below are intentionally placed **
+** OUTSIDE any MemMap section bracket. **
+*******************************************************************************/
+
+#define SPI_START_SEC_PRIVATE_CODE
+#include "Spi_MemMap.h"
+#if (SPI_SUPPORT_CONCURRENT_ASYNC_TRANSMIT == STD_ON)
+
+/* ---- Inline helper functions (STD_ON only) --------------------------------
+ * Placed here (header) so they are available to all TUs that include Spi_Ram.h.
+ * Using 'static' since LOCAL_INLINE is not defined in this module's headers.
+ * Each helper is O(SPI_MAX_HWUNIT) <20> bounded small N; used in MainFunction-class
+ * paths only. */
+
+/* Returns TRUE if any element of Spi_GaaSyncActiveHWUnits is non-zero. */
+static inline FUNC(boolean, SPI_PRIVATE_CODE) Spi_AnySyncActive(void)
+{
+ uint32 LulIdx;
+ boolean LboResult = FALSE;
+ for (LulIdx = 0U; LulIdx < (uint32)SPI_MAX_HWUNIT; LulIdx++)
+ {
+ if (Spi_GaaSyncActiveHWUnits[LulIdx] != 0U)
+ {
+ LboResult = TRUE;
+ break;
+ }
+ }
+ return LboResult;
+}
+
+/* Returns TRUE if any HW unit set in LulMask (HW-unit bitmask) is sync-active. */
+static inline FUNC(boolean, SPI_PRIVATE_CODE) Spi_AnySyncActiveIn(uint32 LulMask)
+{
+ uint32 LulIdx;
+ boolean LboResult = FALSE;
+ for (LulIdx = 0U; LulIdx < (uint32)SPI_MAX_HWUNIT; LulIdx++)
+ {
+ if ((LulMask & (1UL << LulIdx)) != 0UL)
+ {
+ if (Spi_GaaSyncActiveHWUnits[LulIdx] != 0U)
+ {
+ LboResult = TRUE;
+ break;
+ }
+ }
+ }
+ return LboResult;
+}
+
+/* Sets sync-active flag for every HW unit set in LulMask. */
+static inline FUNC(void, SPI_PRIVATE_CODE) Spi_ApplySyncMaskSet(uint32 LulMask)
+{
+ uint32 LulIdx;
+ for (LulIdx = 0U; LulIdx < (uint32)SPI_MAX_HWUNIT; LulIdx++)
+ {
+ if ((LulMask & (1UL << LulIdx)) != 0UL)
+ {
+ Spi_GaaSyncActiveHWUnits[LulIdx] = 1U;
+ }
+ }
+}
+
+/* Clears sync-active flag for every HW unit set in LulMask. */
+static inline FUNC(void, SPI_PRIVATE_CODE) Spi_ApplySyncMaskClr(uint32 LulMask)
+{
+ uint32 LulIdx;
+ for (LulIdx = 0U; LulIdx < (uint32)SPI_MAX_HWUNIT; LulIdx++)
+ {
+ if ((LulMask & (1UL << LulIdx)) != 0UL)
+ {
+ Spi_GaaSyncActiveHWUnits[LulIdx] = 0U;
+ }
+ }
+}
+
+/* Returns TRUE if any element of Spi_GaaAsyncActiveHWUnits is non-zero. */
+static inline FUNC(boolean, SPI_PRIVATE_CODE) Spi_AnyAsyncActive(void)
+{
+ uint32 LulIdx;
+ boolean LboResult = FALSE;
+ for (LulIdx = 0U; LulIdx < (uint32)SPI_MAX_HWUNIT; LulIdx++)
+ {
+ if (Spi_GaaAsyncActiveHWUnits[LulIdx] != 0U)
+ {
+ LboResult = TRUE;
+ break;
+ }
+ }
+ return LboResult;
+}
+
+/* Returns TRUE if any HW unit set in LulMask (HW-unit bitmask) is async-active. */
+static inline FUNC(boolean, SPI_PRIVATE_CODE) Spi_AnyAsyncActiveIn(uint32 LulMask)
+{
+ uint32 LulIdx;
+ boolean LboResult = FALSE;
+ for (LulIdx = 0U; LulIdx < (uint32)SPI_MAX_HWUNIT; LulIdx++)
+ {
+ if ((LulMask & (1UL << LulIdx)) != 0UL)
+ {
+ if (Spi_GaaAsyncActiveHWUnits[LulIdx] != 0U)
+ {
+ LboResult = TRUE;
+ break;
+ }
+ }
+ }
+ return LboResult;
+}
+
+#if ((SPI_LEVEL_DELIVERED == SPI_LEVEL_1) || (SPI_LEVEL_DELIVERED == SPI_LEVEL_2))
+/* Returns TRUE if any queue slot [1..SPI_MAX_QUEUE) is active.
+ * Slot 0 is reserved/unused and intentionally skipped. */
+static inline FUNC(boolean, SPI_PRIVATE_CODE) Spi_AnyQueueActive(void)
+{
+ uint32 LulIdx;
+ boolean LboResult = FALSE;
+ for (LulIdx = 1U; LulIdx < (uint32)SPI_MAX_QUEUE; LulIdx++)
+ {
+ if (Spi_GaaAllQueueSts[LulIdx] != 0U)
+ {
+ LboResult = TRUE;
+ break;
+ }
+ }
+ return LboResult;
+}
+#endif /* (SPI_LEVEL_DELIVERED == SPI_LEVEL_1) || (SPI_LEVEL_DELIVERED == SPI_LEVEL_2) */
+
+#if ((SPI_LEVEL_DELIVERED == SPI_LEVEL_2) && (SPI_FORCE_CANCEL_API == STD_ON))
+/* Returns TRUE if any element of Spi_GaaCancelingHWUnits is non-zero. */
+static inline FUNC(boolean, SPI_PRIVATE_CODE) Spi_AnyCancelHW(void)
+{
+ uint32 LulIdx;
+ boolean LboResult = FALSE;
+ for (LulIdx = 0U; LulIdx < (uint32)SPI_MAX_HWUNIT; LulIdx++)
+ {
+ if (Spi_GaaCancelingHWUnits[LulIdx] != 0U)
+ {
+ LboResult = TRUE;
+ break;
+ }
+ }
+ return LboResult;
+}
+
+/* Sets cancel flag for every HW unit set in LulMask. */
+static inline FUNC(void, SPI_PRIVATE_CODE) Spi_ApplyCancelMaskSet(uint32 LulMask)
+{
+ uint32 LulIdx;
+ for (LulIdx = 0U; LulIdx < (uint32)SPI_MAX_HWUNIT; LulIdx++)
+ {
+ if ((LulMask & (1UL << LulIdx)) != 0UL)
+ {
+ Spi_GaaCancelingHWUnits[LulIdx] = 1U;
+ }
+ }
+}
+
+/* Clears cancel flag for every HW unit set in LulMask. */
+static inline FUNC(void, SPI_PRIVATE_CODE) Spi_ApplyCancelMaskClr(uint32 LulMask)
+{
+ uint32 LulIdx;
+ for (LulIdx = 0U; LulIdx < (uint32)SPI_MAX_HWUNIT; LulIdx++)
+ {
+ if ((LulMask & (1UL << LulIdx)) != 0UL)
+ {
+ Spi_GaaCancelingHWUnits[LulIdx] = 0U;
+ }
+ }
+}
+#endif /* (SPI_LEVEL_DELIVERED == SPI_LEVEL_2) && (SPI_FORCE_CANCEL_API == STD_ON) */
+
+#if ((SPI_LEVEL_DELIVERED == SPI_LEVEL_1) || (SPI_LEVEL_DELIVERED == SPI_LEVEL_2))
+/* Returns the index of the primary (lowest-bit) HW unit assigned to a
+ * sequence in Spi_GpFirstSeq[seq].ulUsingHWUnits. Used to pick the row
+ * for set/clear so they target the SAME storage word.
+ * Caller guarantees ulUsingHWUnits != 0 (generator output). */
+static inline FUNC(uint32, SPI_PRIVATE_CODE)
+ Spi_SeqPrimaryHwUnit(uint32 LulSeqIndex)
+{
+ uint32 LulMask = Spi_GpFirstSeq[LulSeqIndex].ulUsingHWUnits;
+ uint32 LulIdx = 0U;
+ while (0U == (LulMask & 1UL))
+ {
+ LulMask >>= 1;
+ LulIdx++;
+ }
+ return LulIdx;
+}
+
+/* Returns the OR of word LulWordIdx across all HW-unit rows. Read path
+ * for the active-sequence bitmask. */
+static inline FUNC(uint32, SPI_PRIVATE_CODE)
+ Spi_GetActiveSeqWord(uint32 LulWordIdx)
+{
+ uint32 LulHw;
+ uint32 LulOr = 0U;
+ for (LulHw = 0U; LulHw < (uint32)SPI_MAX_HWUNIT; LulHw++)
+ {
+ LulOr |= Spi_GaaActiveSequence[LulHw][LulWordIdx];
+ }
+ return LulOr;
+}
+#endif /* (SPI_LEVEL_DELIVERED == SPI_LEVEL_1) || (SPI_LEVEL_DELIVERED == SPI_LEVEL_2) */
+
+/* ---- Macro layer (STD_ON) <20> per-cell direct access + helper calls --------- */
+
+/* SYNC active HW units */
+#define SPI_GET_SYNC_ACTIVE(hw) (Spi_GaaSyncActiveHWUnits[(hw)])
+#define SPI_SET_SYNC_ACTIVE(hw) (Spi_GaaSyncActiveHWUnits[(hw)] = 1U)
+#define SPI_CLR_SYNC_ACTIVE(hw) (Spi_GaaSyncActiveHWUnits[(hw)] = 0U)
+#define SPI_APPLY_SYNC_MASK_SET(mask) Spi_ApplySyncMaskSet(mask)
+#define SPI_APPLY_SYNC_MASK_CLR(mask) Spi_ApplySyncMaskClr(mask)
+#define SPI_ANY_SYNC_ACTIVE() Spi_AnySyncActive()
+#define SPI_ANY_SYNC_ACTIVE_IN(mask) Spi_AnySyncActiveIn(mask)
+
+/* ASYNC active HW units */
+#define SPI_GET_ASYNC_ACTIVE(hw) (Spi_GaaAsyncActiveHWUnits[(hw)])
+#define SPI_SET_ASYNC_ACTIVE(hw) (Spi_GaaAsyncActiveHWUnits[(hw)] = 1U)
+#define SPI_CLR_ASYNC_ACTIVE(hw) (Spi_GaaAsyncActiveHWUnits[(hw)] = 0U)
+#define SPI_ANY_ASYNC_ACTIVE() Spi_AnyAsyncActive()
+#define SPI_ANY_ASYNC_ACTIVE_IN(mask) Spi_AnyAsyncActiveIn(mask)
+
+/* Combined: any HW unit active (sync or async) */
+#define SPI_ANY_HW_ACTIVE() (Spi_AnySyncActive() || Spi_AnyAsyncActive())
+
+/* Queue status (per-queue-index; slot 0 is reserved <20> callers must use index >= 1) */
+#define SPI_GET_QUEUE_STATUS(q) (Spi_GaaAllQueueSts[(q)])
+#define SPI_SET_QUEUE_STATUS(q) (Spi_GaaAllQueueSts[(q)] = 1U)
+#define SPI_CLR_QUEUE_STATUS(q) (Spi_GaaAllQueueSts[(q)] = 0U)
+#define SPI_ANY_QUEUE_ACTIVE() Spi_AnyQueueActive()
+
+/* Canceling HW units */
+#define SPI_GET_CANCEL_HW(hw) (Spi_GaaCancelingHWUnits[(hw)])
+#define SPI_APPLY_CANCEL_MASK_SET(mask) Spi_ApplyCancelMaskSet(mask)
+#define SPI_APPLY_CANCEL_MASK_CLR(mask) Spi_ApplyCancelMaskClr(mask)
+#define SPI_ANY_CANCEL_HW() Spi_AnyCancelHW()
+
+/* Init macros (STD_ON) <20> zero-fill all cells including reserved slot 0 of queue array */
+#define SPI_INIT_ACTIVE_HWUNITS() \
+ do { \
+ uint32 LulInitIdx; \
+ for (LulInitIdx = 0U; LulInitIdx < (uint32)SPI_MAX_HWUNIT; LulInitIdx++) \
+ { \
+ Spi_GaaSyncActiveHWUnits[LulInitIdx] = 0U; \
+ Spi_GaaAsyncActiveHWUnits[LulInitIdx] = 0U; \
+ } \
+ } while (0)
+
+#define SPI_INIT_ALLQUEUE_STS() \
+ do { \
+ uint32 LulInitIdx; \
+ for (LulInitIdx = 0U; LulInitIdx < (uint32)SPI_MAX_QUEUE; LulInitIdx++) \
+ { \
+ Spi_GaaAllQueueSts[LulInitIdx] = 0U; \
+ } \
+ } while (0)
+
+#define SPI_INIT_CANCEL_HWUNITS() \
+ do { \
+ uint32 LulInitIdx; \
+ for (LulInitIdx = 0U; LulInitIdx < (uint32)SPI_MAX_HWUNIT; LulInitIdx++) \
+ { \
+ Spi_GaaCancelingHWUnits[LulInitIdx] = 0U; \
+ } \
+ } while (0)
+
+/* Active sequence bitmask <20> per-HW-unit rows (STD_ON).
+ * Read merges across rows; set/clear target the primary HW-unit row so
+ * a sequence's bit lives in exactly one row, eliminating bit leaks for
+ * sequences whose ulUsingHWUnits spans multiple HW units. */
+#define SPI_ACTIVE_SEQ_WORD(w) Spi_GetActiveSeqWord(w)
+#define SPI_SET_ACTIVE_SEQ(seq) \
+ (Spi_GaaActiveSequence[Spi_SeqPrimaryHwUnit((uint32)(seq))] \
+ [(uint32)(seq) / (uint32)SPI_UINT32_BITS] |= \
+ (1UL << ((uint32)(seq) & ((uint32)SPI_UINT32_BITS - 1U))))
+#define SPI_CLR_ACTIVE_SEQ(seq) \
+ (Spi_GaaActiveSequence[Spi_SeqPrimaryHwUnit((uint32)(seq))] \
+ [(uint32)(seq) / (uint32)SPI_UINT32_BITS] &= \
+ ~(1UL << ((uint32)(seq) & ((uint32)SPI_UINT32_BITS - 1U))))
+#define SPI_INIT_ACTIVE_SEQ() \
+ do { \
+ uint32 LulHw; \
+ uint32 LulW; \
+ for (LulHw = 0U; LulHw < (uint32)SPI_MAX_HWUNIT; LulHw++) \
+ { \
+ for (LulW = 0U; LulW < SPI_BITS_TO_WORDS(SPI_MAX_SEQUENCE); LulW++) \
+ { \
+ Spi_GaaActiveSequence[LulHw][LulW] = 0U; \
+ } \
+ } \
+ } while (0)
+
+#else /* SPI_SUPPORT_CONCURRENT_ASYNC_TRANSMIT == STD_OFF */
+/* Legacy scalar bitmask macro layer <20> byte-identical to pre-Phase-01 behaviour. */
+
+/* SYNC active HW units (low 16 bits of Spi_GulActiveHWUnits) */
+#define SPI_GET_SYNC_ACTIVE(hw) (Spi_GulActiveHWUnits & (1UL << (hw)))
+#define SPI_SET_SYNC_ACTIVE(hw) (Spi_GulActiveHWUnits |= (1UL << (hw)))
+#define SPI_CLR_SYNC_ACTIVE(hw) (Spi_GulActiveHWUnits &= ~(1UL << (hw)))
+#define SPI_APPLY_SYNC_MASK_SET(mask) (Spi_GulActiveHWUnits |= (mask))
+#define SPI_APPLY_SYNC_MASK_CLR(mask) (Spi_GulActiveHWUnits &= ~(mask))
+#define SPI_ANY_SYNC_ACTIVE() ((Spi_GulActiveHWUnits & 0x0000FFFFUL) != 0UL)
+/* Test whether any HW unit in mask (HW-unit bitmask) is currently sync-active. */
+#define SPI_ANY_SYNC_ACTIVE_IN(mask) ((Spi_GulActiveHWUnits & (mask)) != 0UL)
+
+/* ASYNC active HW units (high 16 bits of Spi_GulActiveHWUnits via SPI_ACTIVE_HW_BITS shift) */
+#define SPI_GET_ASYNC_ACTIVE(hw) (Spi_GulActiveHWUnits & ((1UL << (hw)) << SPI_ACTIVE_HW_BITS))
+#define SPI_SET_ASYNC_ACTIVE(hw) (Spi_GulActiveHWUnits |= ((1UL << (hw)) << SPI_ACTIVE_HW_BITS))
+#define SPI_CLR_ASYNC_ACTIVE(hw) (Spi_GulActiveHWUnits &= ~((1UL << (hw)) << SPI_ACTIVE_HW_BITS))
+#define SPI_ANY_ASYNC_ACTIVE() ((Spi_GulActiveHWUnits & 0xFFFF0000UL) != 0UL)
+/* Symmetric helper for the async half (mask is the HW-unit bitmask, NOT pre-shifted). */
+#define SPI_ANY_ASYNC_ACTIVE_IN(mask) ((Spi_GulActiveHWUnits & ((mask) << SPI_ACTIVE_HW_BITS)) != 0UL)
+
+/* Combined: any HW unit active (sync or async) */
+#define SPI_ANY_HW_ACTIVE() (Spi_GulActiveHWUnits != 0UL)
+
+/* Queue status (per-queue-index, range [1, SPI_MAX_QUEUE)) */
+#define SPI_GET_QUEUE_STATUS(q) (Spi_GulAllQueueSts & (1UL << (q)))
+#define SPI_SET_QUEUE_STATUS(q) (Spi_GulAllQueueSts |= (1UL << (q)))
+#define SPI_CLR_QUEUE_STATUS(q) (Spi_GulAllQueueSts &= ~(1UL << (q)))
+#define SPI_ANY_QUEUE_ACTIVE() (Spi_GulAllQueueSts != 0UL)
+
+/* Canceling HW units (per-HW-unit) */
+#define SPI_GET_CANCEL_HW(hw) (Spi_GulCancelingHWUnits & (1UL << (hw)))
+#define SPI_APPLY_CANCEL_MASK_SET(mask) (Spi_GulCancelingHWUnits |= (mask))
+#define SPI_APPLY_CANCEL_MASK_CLR(mask) (Spi_GulCancelingHWUnits &= ~(mask))
+#define SPI_ANY_CANCEL_HW() (Spi_GulCancelingHWUnits != 0UL)
+
+/* Init macros (STD_OFF) <20> scalar zero-assignment, byte-identical to original init code */
+#define SPI_INIT_ACTIVE_HWUNITS() (Spi_GulActiveHWUnits = 0U)
+#define SPI_INIT_ALLQUEUE_STS() (Spi_GulAllQueueSts = 0U)
+#define SPI_INIT_CANCEL_HWUNITS() (Spi_GulCancelingHWUnits = 0UL)
+
+/* Active sequence bitmask <20> legacy single-row layout (STD_OFF). */
+#define SPI_ACTIVE_SEQ_WORD(w) (Spi_GaaActiveSequence[(w)])
+#define SPI_SET_ACTIVE_SEQ(seq) \
+ (Spi_GaaActiveSequence[(uint32)(seq) / (uint32)SPI_UINT32_BITS] |= \
+ (1UL << ((uint32)(seq) & ((uint32)SPI_UINT32_BITS - 1U))))
+#define SPI_CLR_ACTIVE_SEQ(seq) \
+ (Spi_GaaActiveSequence[(uint32)(seq) / (uint32)SPI_UINT32_BITS] &= \
+ ~(1UL << ((uint32)(seq) & ((uint32)SPI_UINT32_BITS - 1U))))
+#define SPI_INIT_ACTIVE_SEQ() \
+ do { \
+ uint32 LulW; \
+ for (LulW = 0U; LulW < SPI_BITS_TO_WORDS(SPI_MAX_SEQUENCE); LulW++) \
+ { \
+ Spi_GaaActiveSequence[LulW] = 0U; \
+ } \
+ } while (0)
+
+#endif /* SPI_SUPPORT_CONCURRENT_ASYNC_TRANSMIT */
+#define SPI_STOP_SEC_PRIVATE_CODE
+#include "Spi_MemMap.h"
+
/*******************************************************************************
** Function Prototypes **
*******************************************************************************/
diff --git a/rel/modules/spi/src/MSIOF/Spi_MSIOF_LLDriver.c b/rel/modules/spi/src/MSIOF/Spi_MSIOF_LLDriver.c
index 9188b8441e..21d321a215 100644
--- a/rel/modules/spi/src/MSIOF/Spi_MSIOF_LLDriver.c
+++ b/rel/modules/spi/src/MSIOF/Spi_MSIOF_LLDriver.c
@@ -2666,7 +2666,7 @@ STATIC FUNC(void, SPI_PRIVATE_CODE) Spi_MSIOFProcessEndJob(
#if (SPI_LEVEL_DELIVERED == SPI_LEVEL_2)
/* QAC Warning: START Msg(2:2814)-7 */
- if (0UL != (Spi_GulActiveHWUnits & (1UL << LpJobConfig->ucHWUnitIndex)))
+ if (SPI_GET_SYNC_ACTIVE(LpJobConfig->ucHWUnitIndex))
/* END Msg(2:2814)-7 */
{
/* When SyncTransmit, scheduling is done by Spi_SyncTransmit */
@@ -2980,9 +2980,7 @@ STATIC FUNC(void, SPI_PRIVATE_CODE) Spi_MSIOFMainFunction_Handling(void)
/* MISRA Violation: START Msg(2:3432)-6 */
P2CONST(Spi_JobConfigType, AUTOMATIC, SPI_CONFIG_DATA) LpJobConfig;
/* END Msg(2:3432)-6 */
- /* MISRA Violation: START Msg(1:1710)-3 */
uint32 LulDmaIndex;
- /* END Msg(1:1710)-3 */
uint32 LulDmaIntFlag;
uint32 LulJobIndex;
#endif
@@ -3008,8 +3006,7 @@ STATIC FUNC(void, SPI_PRIVATE_CODE) Spi_MSIOFMainFunction_Handling(void)
/* END Msg(2:3469)-12 */
if (
#if (SPI_FORCE_CANCEL_API == STD_ON)
- (0UL ==
- (Spi_GulCancelingHWUnits & (1UL << LpDmaConfig->ucSPIHWUnit))) &&
+ (!SPI_GET_CANCEL_HW(LpDmaConfig->ucSPIHWUnit)) &&
#endif
(0UL != LulDmaIntFlag))
{
@@ -3056,7 +3053,7 @@ STATIC FUNC(void, SPI_PRIVATE_CODE) Spi_MSIOFMainFunction_Handling(void)
* modifying Spi_GulActiveHWUnits. Therefore the re-entrancy between
* Spi_AsyncTransmit and Spi_MainFunction_Handling is not affected.
*/
- if ((0UL == (Spi_GulActiveHWUnits & (1UL << LulHWUnitIndex)))
+ if ((!SPI_GET_SYNC_ACTIVE(LulHWUnitIndex))
#if (SPI_FORCE_CANCEL_API == STD_ON)
/*
*Spi_GulCancelingHWUnits is modified by Spi_ForceCancel,
@@ -3067,7 +3064,7 @@ STATIC FUNC(void, SPI_PRIVATE_CODE) Spi_MSIOFMainFunction_Handling(void)
*Spi_MainFunction_Handling, so Spi_GulCancelHWUnits is never changed
*while this function is executing.
*/
- && (0UL == (Spi_GulCancelingHWUnits & (1UL << LulHWUnitIndex)))
+ && (!SPI_GET_CANCEL_HW(LulHWUnitIndex))
#endif
#if (SPI_DMA_CONFIGURED == STD_ON)
/* Check if HW unit is not configured with DMA */
diff --git a/rel/modules/spi/src/Spi.c b/rel/modules/spi/src/Spi.c
index 6302eeccc2..d11e66961a 100644
--- a/rel/modules/spi/src/Spi.c
+++ b/rel/modules/spi/src/Spi.c
@@ -541,11 +541,11 @@ FUNC(void, SPI_PUBLIC_CODE) Spi_Init(
#endif
/* Global variable for active HW unit indexes used by a request transmission */
- Spi_GulActiveHWUnits = 0U;
+ SPI_INIT_ACTIVE_HWUNITS();
#if ((SPI_LEVEL_DELIVERED == SPI_LEVEL_1) || (SPI_LEVEL_DELIVERED == SPI_LEVEL_2))
/* Initialize Queues */
- Spi_GulAllQueueSts = 0U;
+ SPI_INIT_ALLQUEUE_STS();
/* MISRA Violation: START Msg(6:2877)-6 */
for (LulIndex = 0U; (uint32)SPI_MAX_QUEUE > LulIndex; LulIndex++)
/* END Msg(6:2877)-6 */
@@ -563,15 +563,9 @@ FUNC(void, SPI_PUBLIC_CODE) Spi_Init(
}
}
- /* MISRA Violation: START Msg(6:2877)-6 */
- /* MISRA Violation: START Msg(2:3469)-8 */
- for (LulIndex = 0U;
- SPI_BITS_TO_WORDS(SPI_MAX_SEQUENCE) > LulIndex; LulIndex++)
- /* END Msg(2:3469)-8 */
- /* END Msg(6:2877)-6 */
- {
- Spi_GaaActiveSequence[LulIndex] = 0U;
- }
+ /* Active-sequence bitmask init: STD_ON zeros all per-HW rows; STD_OFF
+ * zeros the single legacy row. */
+ SPI_INIT_ACTIVE_SEQ();
#endif
/* Initialize HW status */
@@ -698,7 +692,7 @@ FUNC(void, SPI_PUBLIC_CODE) Spi_Init(
#if ((SPI_LEVEL_DELIVERED == SPI_LEVEL_2) && (SPI_FORCE_CANCEL_API == STD_ON))
/* HWUnits under processing by Spi_ForceCancel */
- Spi_GulCancelingHWUnits = 0UL;
+ SPI_INIT_CANCEL_HWUNITS();
#endif
/* Set Initialized flag */
@@ -762,7 +756,7 @@ FUNC(Std_ReturnType, SPI_PUBLIC_CODE) Spi_DeInit(void)
#endif
/* QAC Warning: START Msg(3:3416)-5 */
/* Check if there is no HW unit activated */
- if (0UL == Spi_GulActiveHWUnits)
+ if (!SPI_ANY_HW_ACTIVE())
/* END Msg(3:3416)-5 */
{
/* Update the SPI driver status as uninitialized */
@@ -985,10 +979,7 @@ FUNC(Std_ReturnType, SPI_PUBLIC_CODE) Spi_AsyncTransmit(
(SPI_AR_VERSION == SPI_AR_1911_VERSION)) && \
(SPI_LEVEL_DELIVERED == SPI_LEVEL_2))
/* Check if sequence is already used for sync transmission */
- /* MISRA Violation: START Msg(7:0404)-9 */
- if (0UL != (Spi_GulActiveHWUnits &
- Spi_GpFirstSeq[Sequence].ulUsingHWUnits))
- /* END Msg(7:0404)-9 */
+ if (SPI_ANY_SYNC_ACTIVE_IN(Spi_GpFirstSeq[Sequence].ulUsingHWUnits))
{
/* This function shall return with value E_NOT_OK */
LucReturnValue = E_NOT_OK;
@@ -1013,10 +1004,8 @@ FUNC(Std_ReturnType, SPI_PUBLIC_CODE) Spi_AsyncTransmit(
/* END Msg(2:3469)-8 */
/* END Msg(6:2877)-6 */
{
- /* MISRA Violation: START Msg(7:0404)-9 */
- if (0UL != (Spi_GaaActiveSequence[LulCount] &
+ if (0UL != (SPI_ACTIVE_SEQ_WORD(LulCount) &
Spi_GpFirstSeq[Sequence].aaJobSharedSequences[LulCount]))
- /* END Msg(7:0404)-9 */
{
LucReturnValue = E_NOT_OK;
}
@@ -1031,8 +1020,7 @@ FUNC(Std_ReturnType, SPI_PUBLIC_CODE) Spi_AsyncTransmit(
{
/* QAC Warning: START Msg(2:2844)-1 */
/* Set active sequence bit for check shared job in a sub-sequence */
- Spi_GaaActiveSequence[(uint32)Sequence / (uint32)SPI_UINT32_BITS] |=
- (1UL << ((uint32)Sequence & (uint32)(SPI_UINT32_BITS - 1U)));
+ SPI_SET_ACTIVE_SEQ(Sequence);
/* Set sequence status as pending */
Spi_GaaSeqStatus[Sequence].enResult = SPI_SEQ_PENDING;
#if (SPI_CANCEL_API == STD_ON)
@@ -1343,7 +1331,7 @@ FUNC(Spi_StatusType, SPI_PUBLIC_CODE) Spi_GetStatus(void)
LenRetValue = SPI_UNINIT;
}
/* QAC Warning: START Msg(3:3416)-5 */
- else if (0UL != Spi_GulActiveHWUnits)
+ else if (SPI_ANY_HW_ACTIVE())
/* END Msg(3:3416)-5 */
{
LenRetValue = SPI_BUSY;
@@ -1639,6 +1627,51 @@ FUNC(Std_ReturnType, SPI_PUBLIC_CODE) Spi_SyncTransmit(
SPI_ENTER_CRITICAL_SECTION(SPI_RAM_DATA_PROTECTION);
/* QAC Warning: START Msg(2:2814)-2 */
/* QAC Warning: START Msg(2:2844)-1 */
+#if (SPI_SUPPORT_CONCURRENT_ASYNC_TRANSMIT == STD_ON)
+ {
+ boolean LboBlocked = FALSE;
+#if (SPI_SUPPORT_CONCURRENT_SYNC_TRANSMIT == STD_ON)
+ /* Check if any HW unit used by this sequence is on-going in a sync transmission */
+ if (SPI_ANY_SYNC_ACTIVE_IN(LpSeqConfig->ulUsingHWUnits))
+ {
+ LboBlocked = TRUE;
+ }
+#else
+ /* Check if any sync transmission is on-going (no per-HW filtering) */
+ if (SPI_ANY_SYNC_ACTIVE())
+ {
+ LboBlocked = TRUE;
+ }
+#endif
+#if (((SPI_AR_VERSION == SPI_AR_431_VERSION) || \
+ (SPI_AR_VERSION == SPI_AR_1911_VERSION)) && \
+ (SPI_LEVEL_DELIVERED == SPI_LEVEL_2))
+ /* Check if any HW unit used by this sequence is on-going in an async transmission */
+ if (SPI_ANY_ASYNC_ACTIVE_IN(LpSeqConfig->ulUsingHWUnits))
+ {
+ LboBlocked = TRUE;
+ }
+#endif
+ if ((FALSE == LboBlocked)
+#if (((SPI_AR_VERSION == SPI_AR_431_VERSION) || \
+ (SPI_AR_VERSION == SPI_AR_1911_VERSION)) && \
+ (SPI_LEVEL_DELIVERED == SPI_LEVEL_2))
+ /* Check if a sequence status is not pending */
+ && (SPI_SEQ_PENDING != Spi_GaaSeqStatus[Sequence].enResult)
+#endif
+ )
+ /* END Msg(2:2844)-1 */
+ /* END Msg(2:2814)-2 */
+ {
+ SPI_APPLY_SYNC_MASK_SET(LpSeqConfig->ulUsingHWUnits);
+ LucReturnValue = E_OK;
+ }
+ else
+ {
+ LucReturnValue = E_NOT_OK;
+ }
+ }
+#else /* SPI_SUPPORT_CONCURRENT_ASYNC_TRANSMIT == STD_OFF */
if ((0UL == (Spi_GulActiveHWUnits &
#if (SPI_SUPPORT_CONCURRENT_SYNC_TRANSMIT == STD_ON)
/* Check if a HW unit in the sequence is on-going in a sync transmission */
@@ -1664,13 +1697,14 @@ FUNC(Std_ReturnType, SPI_PUBLIC_CODE) Spi_SyncTransmit(
/* END Msg(2:2844)-1 */
/* END Msg(2:2814)-2 */
{
- Spi_GulActiveHWUnits |= LpSeqConfig->ulUsingHWUnits;
+ SPI_APPLY_SYNC_MASK_SET(LpSeqConfig->ulUsingHWUnits);
LucReturnValue = E_OK;
}
else
{
LucReturnValue = E_NOT_OK;
}
+#endif /* SPI_SUPPORT_CONCURRENT_ASYNC_TRANSMIT */
SPI_EXIT_CRITICAL_SECTION(SPI_RAM_DATA_PROTECTION);
if (E_OK != LucReturnValue)
@@ -1689,7 +1723,7 @@ FUNC(Std_ReturnType, SPI_PUBLIC_CODE) Spi_SyncTransmit(
/* Release locked HWUnits */
SPI_ENTER_CRITICAL_SECTION(SPI_RAM_DATA_PROTECTION);
- Spi_GulActiveHWUnits &= ~(LpSeqConfig->ulUsingHWUnits);
+ SPI_APPLY_SYNC_MASK_CLR(LpSeqConfig->ulUsingHWUnits);
SPI_EXIT_CRITICAL_SECTION(SPI_RAM_DATA_PROTECTION);
}
}
@@ -1860,10 +1894,7 @@ FUNC(void, SPI_PUBLIC_CODE) Spi_Cancel(Spi_SequenceType Sequence)
#if ((SPI_AR_VERSION == SPI_AR_431_VERSION) || \
(SPI_AR_VERSION == SPI_AR_1911_VERSION))
/* Check if sequence is already used for sync transmission */
- /* MISRA Violation: START Msg(7:0404)-9 */
- if (0UL != (Spi_GulActiveHWUnits &
- Spi_GpFirstSeq[Sequence].ulUsingHWUnits))
- /* END Msg(7:0404)-9 */
+ if (SPI_ANY_SYNC_ACTIVE_IN(Spi_GpFirstSeq[Sequence].ulUsingHWUnits))
{
/* Report to DET */
SPI_DET_REPORT_RUNTIME_ERROR(SPI_MODULE_ID, SPI_INSTANCE_ID,
@@ -1939,7 +1970,7 @@ FUNC(Std_ReturnType, SPI_PUBLIC_CODE) Spi_SetAsyncMode(Spi_AsyncModeType Mode)
{
/* QAC Warning: START Msg(3:3416)-5 */
/* Confirm no async task is operating */
- if (0UL != Spi_GulAllQueueSts)
+ if (SPI_ANY_QUEUE_ACTIVE())
/* END Msg(3:3416)-5 */
{
LucReturnValue = E_NOT_OK;
@@ -2130,10 +2161,7 @@ FUNC(void, SPI_PUBLIC_CODE) Spi_ForceCancel(const Spi_SequenceType LucSequence)
#if ((SPI_AR_VERSION == SPI_AR_431_VERSION)|| \
(SPI_AR_VERSION == SPI_AR_1911_VERSION))
/* Check if sequence is already used for sync transmission */
- /* MISRA Violation: START Msg(7:0404)-9 */
- if (0UL != (Spi_GulActiveHWUnits &
- Spi_GpFirstSeq[LucSequence].ulUsingHWUnits))
- /* END Msg(7:0404)-9 */
+ if (SPI_ANY_SYNC_ACTIVE_IN(Spi_GpFirstSeq[LucSequence].ulUsingHWUnits))
{
/* Report to DET */
SPI_DET_REPORT_RUNTIME_ERROR(SPI_MODULE_ID, SPI_INSTANCE_ID,
diff --git a/rel/modules/spi/src/Spi_Ram.c b/rel/modules/spi/src/Spi_Ram.c
index 7d95b77ef6..b9ea5748a6 100644
--- a/rel/modules/spi/src/Spi_Ram.c
+++ b/rel/modules/spi/src/Spi_Ram.c
@@ -293,6 +293,37 @@ volatile VAR(Spi_EBDataType, SPI_VAR_NO_INIT)
#include "Spi_MemMap.h"
/* END Msg(4:5087)-2 */
+#if (SPI_SUPPORT_CONCURRENT_ASYNC_TRANSMIT == STD_ON)
+/* Phase 02: per-HW-unit arrays replacing the packed scalar bitmask.
+ * Each element stores 0U (inactive) or 1U (active) for that HW unit index. */
+
+/* Per-HW-unit sync-active flags */
+/* MISRA Violation: START Msg(1:1531)-1 */
+volatile VAR(uint32, SPI_VAR_NO_INIT) Spi_GaaSyncActiveHWUnits[SPI_MAX_HWUNIT];
+/* END Msg(1:1531)-1 */
+
+/* Per-HW-unit async-active flags */
+/* MISRA Violation: START Msg(1:1531)-1 */
+volatile VAR(uint32, SPI_VAR_NO_INIT) Spi_GaaAsyncActiveHWUnits[SPI_MAX_HWUNIT];
+/* END Msg(1:1531)-1 */
+
+#if ((SPI_LEVEL_DELIVERED == SPI_LEVEL_1) || (SPI_LEVEL_DELIVERED == SPI_LEVEL_2))
+/* Per-queue active flags (slot 0 is reserved/unused) */
+/* MISRA Violation: START Msg(1:1531)-1 */
+volatile VAR(uint32, SPI_VAR_NO_INIT) Spi_GaaAllQueueSts[SPI_MAX_QUEUE];
+/* END Msg(1:1531)-1 */
+#endif
+
+#if ((SPI_LEVEL_DELIVERED == SPI_LEVEL_2) && (SPI_FORCE_CANCEL_API == STD_ON))
+/* Per-HW-unit cancel flags */
+/* MISRA Violation: START Msg(1:1531)-1 */
+volatile VAR(uint32, SPI_VAR_NO_INIT) Spi_GaaCancelingHWUnits[SPI_MAX_HWUNIT];
+/* END Msg(1:1531)-1 */
+#endif
+
+#else /* SPI_SUPPORT_CONCURRENT_ASYNC_TRANSMIT == STD_OFF */
+/* Legacy scalar bitmask storage <20> byte-identical to pre-Phase-02 behaviour. */
+
/* Bit array indicates active HW unit index
- The lower 16-bits are for synchronous transmission
- The upper 16-bits are for asynchronous transmission */
@@ -304,10 +335,26 @@ volatile VAR(uint32, SPI_VAR_NO_INIT) Spi_GulActiveHWUnits;
(SPI_LEVEL_DELIVERED == SPI_LEVEL_2))
/* Bit array indicates active Queues */
volatile VAR(uint32, SPI_VAR_NO_INIT) Spi_GulAllQueueSts;
-/* Bit array indicates active Sequences */
+#endif
+
+#if ((SPI_LEVEL_DELIVERED == SPI_LEVEL_2) && (SPI_FORCE_CANCEL_API == STD_ON))
+
+volatile VAR(uint32, SPI_VAR_NO_INIT) Spi_GulCancelingHWUnits;
+#endif
+
+#endif /* SPI_SUPPORT_CONCURRENT_ASYNC_TRANSMIT */
+
+/* Bit array indicates active Sequences <20> shared between both legs */
+#if ((SPI_LEVEL_DELIVERED == SPI_LEVEL_1) || \
+ (SPI_LEVEL_DELIVERED == SPI_LEVEL_2))
+#if (SPI_SUPPORT_CONCURRENT_ASYNC_TRANSMIT == STD_ON)
+volatile VAR(uint32, SPI_VAR_NO_INIT)
+ Spi_GaaActiveSequence[SPI_MAX_HWUNIT][SPI_BITS_TO_WORDS(SPI_MAX_SEQUENCE)];
+#else
volatile VAR(uint32, SPI_VAR_NO_INIT)
Spi_GaaActiveSequence[SPI_BITS_TO_WORDS(SPI_MAX_SEQUENCE)];
#endif
+#endif
#if (SPI_MAX_CHANNEL_BUFFER_SIZE > 0U)
/* Channel buffer, includes all tx and rx buffers for all channels
@@ -325,11 +372,6 @@ volatile VAR(uint32, SPI_VAR_NO_INIT) Spi_GulDmaRxData;
/* END Msg(1:1533)-4 */
#endif
-#if ((SPI_LEVEL_DELIVERED == SPI_LEVEL_2) && (SPI_FORCE_CANCEL_API == STD_ON))
-/* Bit array indicates HWUnits is being canceled by Spi_ForceCancel */
-volatile VAR(uint32, SPI_VAR_NO_INIT) Spi_GulCancelingHWUnits;
-#endif
-
#define SPI_STOP_SEC_VAR_NO_INIT_32
/* MISRA Violation: START Msg(4:5087)-2 */
#include "Spi_MemMap.h"
diff --git a/rel/modules/spi/src/Spi_Scheduler.c b/rel/modules/spi/src/Spi_Scheduler.c
index ee7f993096..1abee88e7e 100644
--- a/rel/modules/spi/src/Spi_Scheduler.c
+++ b/rel/modules/spi/src/Spi_Scheduler.c
@@ -1144,11 +1144,11 @@ FUNC(void, SPI_PRIVATE_CODE) Spi_StartTransmission(uint32 LulSeqIndex)
{
/* Push this sequence to the queue */
Spi_PushToQueue(LulQueueIndex, LulSeqIndex);
- if (0UL == (Spi_GulAllQueueSts & (1UL << LulQueueIndex)))
+ if (!SPI_GET_QUEUE_STATUS(LulQueueIndex))
{
/* If queue is not running, initiation is required */
LblNeedToInitiate = SPI_TRUE;
- Spi_GulAllQueueSts |= (1UL << LulQueueIndex);
+ SPI_SET_QUEUE_STATUS(LulQueueIndex);
/* Pop the first job */
/* MISRA Violation: START Msg(2:1339)-3 */
(void)Spi_PopFromQueue(LulQueueIndex, &LulSeqIndex, &LulJobIndex);
@@ -1169,7 +1169,7 @@ FUNC(void, SPI_PRIVATE_CODE) Spi_StartTransmission(uint32 LulSeqIndex)
(Spi_JobType)LulJobIndex;
/* END Msg(2:2814)-5 */
/* END Msg(2:2844)-6 */
- Spi_GulActiveHWUnits |= (1UL << LpJobConfig->ucHWUnitIndex) << SPI_ACTIVE_HW_BITS;
+ SPI_SET_ASYNC_ACTIVE(LpJobConfig->ucHWUnitIndex);
/* QAC Warning: START Msg(2:2844)-6 */
#if (SPI_HW_STATUS_API == STD_ON)
Spi_GaaHWStatus[LpJobConfig->ucHWUnitIndex].blActive = SPI_TRUE;
@@ -1380,9 +1380,9 @@ FUNC(void, SPI_PRIVATE_CODE) Spi_ProcessSequence(const uint32 LulHWUnitIndex)
else
{
/* If the Queue is empty, clear the active flag of this Queue */
- Spi_GulAllQueueSts &= ~(1UL << LulQueueIndex);
+ SPI_CLR_QUEUE_STATUS(LulQueueIndex);
/* De-active HW unit bit */
- Spi_GulActiveHWUnits &= ~((1UL << LulHWUnitIndex) << SPI_ACTIVE_HW_BITS);
+ SPI_CLR_ASYNC_ACTIVE(LulHWUnitIndex);
#if (SPI_HW_STATUS_API == STD_ON)
/* Set HW unit status bit as False */
/* QAC Warning: START Msg(2:2844)-6 */
@@ -1652,8 +1652,7 @@ FUNC(void, SPI_PRIVATE_CODE) Spi_CancelSequence(
LblRequireSeqEndNotification = SPI_TRUE;
/* Clear sequence active bit for checking job sharing */
/* QAC Warning: START Msg(2:2844)-6 */
- Spi_GaaActiveSequence[LulSeqIndex / (uint32)SPI_UINT32_BITS] &=
- ~(1UL << (LulSeqIndex & (SPI_UINT32_BITS - 1U)));
+ SPI_CLR_ACTIVE_SEQ(LulSeqIndex);
/* END Msg(2:2844)-6 */
}
else
@@ -1782,12 +1781,12 @@ STATIC FUNC(void, SPI_PRIVATE_CODE) Spi_MaskSequenceInterrupts(
if (SPI_TRUE == LblMask)
{
/* QAC Warning: START Msg(2:2814)-5 */
- Spi_GulCancelingHWUnits |= LpSeqConfig->ulUsingHWUnits;
+ SPI_APPLY_CANCEL_MASK_SET(LpSeqConfig->ulUsingHWUnits);
/* END Msg(2:2814)-5 */
}
else
{
- Spi_GulCancelingHWUnits &= ~LpSeqConfig->ulUsingHWUnits;
+ SPI_APPLY_CANCEL_MASK_CLR(LpSeqConfig->ulUsingHWUnits);
}
SPI_EXIT_CRITICAL_SECTION(SPI_INTERRUPT_CONTROL_PROTECTION);
}
@@ -2069,8 +2068,7 @@ STATIC FUNC(boolean, SPI_PRIVATE_CODE) Spi_CheckSeqFinish(
LblSeqFinished = SPI_TRUE;
/* Clear Sequence active bit */
/* QAC Warning: START Msg(2:2844)-6 */
- Spi_GaaActiveSequence[LulSeqIndex / (uint32)SPI_UINT32_BITS] &=
- ~(1UL << (LulSeqIndex & (SPI_UINT32_BITS - 1U)));
+ SPI_CLR_ACTIVE_SEQ(LulSeqIndex);
/* END Msg(2:2844)-6 */
/* Update Sequence Result */
/* QAC Warning: START Msg(2:2844)-6 */