282 lines
12 KiB
C
282 lines
12 KiB
C
/*******************************************************************************
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* DISCLAIMER
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* This software is supplied by Renesas Electronics Corporation and is only
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* intended for use with Renesas products. No other uses are authorized. This
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* software is owned by Renesas Electronics Corporation and is protected under
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* all applicable laws, including copyright laws.
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* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
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* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
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* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
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* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
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* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
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* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
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* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
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* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
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* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
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* Renesas reserves the right, without notice, to make changes to this software
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* and to discontinue the availability of this software. By using this software,
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* you agree to the additional terms and conditions found by accessing the
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* following link:
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* http://www.renesas.com/disclaimer
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* Copyright 2021-2023 Renesas Electronics Corporation All rights reserved.
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*******************************************************************************/
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/*******************************************************************************
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* DESCRIPTION : remap register header
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******************************************************************************/
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#ifndef REMAP_REGISTER_H_
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#define REMAP_REGISTER_H_
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#include <stdint.h>
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#define REMAP_BASE (0xFF1FC400U)
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#define ICUMX_PROT0PCMD (0xFFFEE090U)
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#define ICUMX_PROT0PS (0xFFFEE094U)
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#define PROTCMD_START (0xA5U)
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#define PROTS0ERR (0x01U)
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#define ICU_REMAP0 (0xFC000000U)
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/* REMAP setting */
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/* Remap ID(0 -- 15) */
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#define ICU_REMAP_NUM_RTRAM (15U) /* RTRAM */
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#define ICU_REMAP_NUM_CC (14U) /* CC63S,AXMM,QoS for S4 / V4H */
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#define ICU_REMAP_NUM_FCPR (14U) /* FCPR for V4M */
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#define ICU_REMAP_NUM_PFC (13U) /* PFC,GPIO,CPGA,RESET */
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#define ICU_REMAP_NUM_ECM (12U) /* ECM,AP-System Core */
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#define ICU_REMAP_NUM_RPC (11U) /* RPC */
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#define ICU_REMAP_NUM_RTDMAC (10U) /* RT-DMAC0,PFC(MCU) */
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#define ICU_REMAP_NUM_SCIF (9U) /* SCIF */
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#define ICU_REMAP_NUM_MMC (8U) /* MMC */
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#define ICU_REMAP_NUM_HSCIF (7U) /* HSCIF */
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#define ICU_REMAP_NUM_DMAC (6U) /* SYS-DMAC0 */
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#define ICU_REMAP_NUM_RGID (5U) /* Region ID */
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#if (RCAR_LSI == RCAR_S4)
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#define ICU_REMAP_NUM_MCU (4U) /* MCU */
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#endif
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/* SICREMAP2M15 */
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#define ICU_REMAP_RTSRAM (0xEB200000U) /* RT-SRAM */
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/* SICREMAP2M14 */
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#define ICU_REMAP_CC (0xE6600000U) /* CC63S,AXMM,QoS,FCPR for S4 / V4H */
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/* SICREMAP2M14 */
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#define ICU_REMAP_FCPR (0xE6600000U) /* FCPR for V4M */
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/* SICREMAP2M13 */
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#define ICU_REMAP_PFC (0xE6000000U) /* PFC,GPIO,CPGA,RESET */
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/* SICREMAP2M12 */
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#define ICU_REMAP_ECM (0xE6200000U) /* ECM,AP-System Core */
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/* SICREMAP2M11 */
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#define ICU_REMAP_RPC (0xEE200000U) /* RPC */
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/* SICREMAP2M10 */
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#define ICU_REMAP_RTDMAC (0xFFC00000U) /* RT-DMAC0,PFC(MCU) */
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/* SICREMAP2M9 */
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#if (RCAR_LSI == RCAR_S4)
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#define ICU_REMAP_SCIF (0xE6C00000U) /* SCIF3 */
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#elif ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M))
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#define ICU_REMAP_SCIF (0xE6E00000U) /* SCIF0 */
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#endif /* RCAR_LSI == RCAR_S4 */
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/* SICREMAP2M8 */
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#define ICU_REMAP_MMC (0xEE000000U) /* MMC */
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/* SICREMAP2M7 */
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#define ICU_REMAP_HSCIF (0xE6400000U) /* HSCIF */
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/* SICREMAP2M6 */
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#define ICU_REMAP_DMAC (0xE7200000U) /* SYS-DMAC0 */
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/* SICREMAP2M5 */
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#define ICU_REMAP_RGID (0xE7600000U) /* Region ID */
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#if (RCAR_LSI == RCAR_S4)
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/* SICREMAP2M4 */
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#define ICU_REMAP_MCU (0xD8E00000U) /* MCU */
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#endif
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#define ICU_REMAP15_BASE (ICU_REMAP_RTRAM) /* RTRAM */
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#define ICU_REMAP14_BASE (ICU_REMAP_CC) /* CC63S,AXMM,QoS,FCPR */
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#define ICU_REMAP13_BASE (ICU_REMAP_PFC) /* PFC,GPIO,CPGA,RESET */
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#define ICU_REMAP12_BASE (ICU_REMAP_ECM) /* ECM,AP-System Core */
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#define ICU_REMAP11_BASE (ICU_REMAP_RPC) /* RPC */
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#define ICU_REMAP10_BASE (ICU_REMAP_RTDMAC) /* RT-DMAC0 */
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#define ICU_REMAP9_BASE (ICU_REMAP_SCIF) /* SCIF */
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#define ICU_REMAP8_BASE (ICU_REMAP_MMC) /* MMC */
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#define ICU_REMAP7_BASE (ICU_REMAP_HSCIF) /* HSCIF */
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#define ICU_REMAP6_BASE (ICU_REMAP_DMAC) /* SYS-DMAC0 */
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#define ICU_REMAP5_BASE (ICU_REMAP_RGID) /* Region ID */
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#if (RCAR_LSI == RCAR_S4)
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#define ICU_REMAP4_BASE (ICU_REMAP_MCU) /* MCU */
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#elif ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M))
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#define ICU_REMAP4_BASE (0x00000000U) /* Reserved */
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#endif
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#define ICU_REMAP3_BASE (0x00000000U) /* Reserved */
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#define ICU_REMAP2_BASE (0x00000000U) /* Reserved */
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#define ICU_REMAP1_BASE (0x00000000U) /* Reserved */
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#define ICU_REMAP0_BASE (0x00000000U) /* Reserved */
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/* Base address offset of each register after remap */
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/* REMAP15(0xEB200000U) */
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/* RT-SRAM */
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#define ICU_REMAP_OFFSET_RTSRAM (0x00000000U)
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/* REMAP14(0xE6600000U) */
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#define ICU_REMAP_OFFSET_CC63S (0x00000000U)
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#define ICU_REMAP_OFFSET_DBSC (0x00190000U) /* (0xE6790000U) */
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#define ICU_REMAP_OFFSET_AXMM (0x00180000U) /* (0xE6780000U) */
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#if (RCAR_LSI == RCAR_S4)
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#define ICU_REMAP_OFFSET_CCI (0x001a0000U) /* (0xE67A0000U) */
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#define ICU_REMAP_OFFSET_QOS (0x001e0000U) /* (0xE67E0000U) */
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#elif ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M))
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#define ICU_REMAP_OFFSET_FCPR (0x00185700U) /* (0xE6785700U) */
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#if (RCAR_LSI == RCAR_V4M)
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#define ICU_REMAP_OFFSET_I2C3 (0x000D0000U) /* (0xE66D0000U) */
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#endif /* (RCAR_LSI == RCAR_V4M) */
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#define ICU_REMAP_OFFSET_I2C5 (0x000E0000U) /* (0xE66E0000U) */
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#endif /* (RCAR_LSI == RCAR_S4) */
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/* REMAP13(0xE6000000U) */
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/* RWDT */
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#define ICU_REMAP_OFFSET_RWDT (0x00020000U)
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/* SWDT */
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#define ICU_REMAP_OFFSET_SWDT (0x00030000U)
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/* PFC */
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#define ICU_REMAP_OFFSET_PFC (0x00050000U)
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/* EFUSE */
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#define ICU_REMAP_OFFSET_EFUSE (0x00078800U)
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/* CPGA */
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#define ICU_REMAP_OFFSET_CPGA (0x00150000U)
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/* RESET */
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#define ICU_REMAP_OFFSET_RESET (0x00160000U)
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/* APMU */
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#define ICU_REMAP_OFFSET_APMU (0x00170000U)
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/* SYSC */
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#define ICU_REMAP_OFFSET_SYSC (0x00180000U)
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/* OTP */
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#define ICU_REMAP_OFFSET_OTP (0x001BF000U)
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#if (RCAR_LSI == RCAR_V4M)
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#define ICU_REMAP_OFFSET_AVS (0x000A0000U) /* (0xE60A0000U) */
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#endif /* (RCAR_LSI == RCAR_V4M) */
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/* REMAP12(0xE6200000U) */
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/* ECM */
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#define ICU_REMAP_OFFSET_MFIS (0x00060000U)
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#define ICU_REMAP_OFFSET_SDRAM_ECC (0x00050000U)
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#define ICU_REMAP_OFFSET_AP_CORE (0x00080000U)
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/* REMAP11(0xEE200000U) */
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/*RPC*/
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#define ICU_REMAP_OFFSET_RPC (0x00000000U)
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/* REMAP10(0xFFC00000U) */
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/* RT-DMA */
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#define ICU_REMAP_OFFSET_RTDMA0 (0x00010000U)
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#define ICU_REMAP_OFFSET_RTDMACTL (0x00160000U)
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#define ICU_REMAP_OFFSET_PFCMCU (0x00190000U)
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#if (RCAR_LSI == RCAR_S4)
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/* REMAP9(0xE6C00000U) */
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/*SCIF*/
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#define ICU_REMAP_OFFSET_SCIF3 (0x00050000U)
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#elif ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M))
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/* REMAP9(0xE6E00000U) */
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/*SCIF*/
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#define ICU_REMAP_OFFSET_SCIF0 (0x00060000U)
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#endif /* RCAR_LSI == RCAR_S4 */
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/* REMAP8(0xEE000000U) */
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/* SDHI2/MMC0 */
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#define ICU_REMAP_OFFSET_SDHI (0x00140000U)
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/* REMAP7(0xE6400000U) */
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/* HSCIF */
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#define ICU_REMAP_OFFSET_HSCIF0 (0x00140000U)
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/* REMAP6(0xE7200000U) */
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/* SYS-DMAC */
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#define ICU_REMAP_OFFSET_SYSDMAC (0x00100000U)
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/* REMAP5(0xE7600000U) */
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/* Region ID */
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#if ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M))
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#define ICU_REMAP_OFFSET_ICISTP (0x00100000U)
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#endif
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#define ICU_REMAP_OFFSET_RGID (0x00150000U)
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#if (RCAR_LSI == RCAR_S4)
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/* REMAP4(0xD8E00000U) */
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/* MCU */
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#define ICU_REMAP_OFFSET_MCU (0x00100000U)
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#endif
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/* REMAP15(0xEB200000U) */
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#define BASE_RTSRAM_ADDR (icu_remap_calc(ICU_REMAP_NUM_RTRAM) + ICU_REMAP_OFFSET_RTSRAM)
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/* REMAP14(0xE6600000U) */
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#define BASE_DBSC_ADDR (icu_remap_calc(ICU_REMAP_NUM_CC) + ICU_REMAP_OFFSET_DBSC)
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#define BASE_AXMM_ADDR (icu_remap_calc(ICU_REMAP_NUM_CC) + ICU_REMAP_OFFSET_AXMM)
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#if (RCAR_LSI == RCAR_S4)
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#define BASE_CCI_ADDR (icu_remap_calc(ICU_REMAP_NUM_CC) + ICU_REMAP_OFFSET_CCI)
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#define BASE_QOS_ADDR (icu_remap_calc(ICU_REMAP_NUM_CC) + ICU_REMAP_OFFSET_QOS)
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#elif ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M))
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#define BASE_FCPR_ADDR (icu_remap_calc(ICU_REMAP_NUM_CC) + ICU_REMAP_OFFSET_FCPR)
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#if (RCAR_LSI == RCAR_V4M)
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#define BASE_I2C3_ADDR (icu_remap_calc(ICU_REMAP_NUM_CC) + ICU_REMAP_OFFSET_I2C3)
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#endif /* (RCAR_LSI == RCAR_V4M) */
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#define BASE_I2C5_ADDR (icu_remap_calc(ICU_REMAP_NUM_CC) + ICU_REMAP_OFFSET_I2C5)
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#endif /* (RCAR_LSI == RCAR_S4) */
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/* REMAP13(0xE6000000U) */
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#define BASE_RWDT_ADDR (icu_remap_calc(ICU_REMAP_NUM_PFC) + ICU_REMAP_OFFSET_RWDT)
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#define BASE_SWDT_ADDR (icu_remap_calc(ICU_REMAP_NUM_PFC) + ICU_REMAP_OFFSET_SWDT)
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#define BASE_EFUSE_ADDR (icu_remap_calc(ICU_REMAP_NUM_PFC) + ICU_REMAP_OFFSET_EFUSE)
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#define BASE_PFC_ADDR (icu_remap_calc(ICU_REMAP_NUM_PFC) + ICU_REMAP_OFFSET_PFC)
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#define BASE_CPG_ADDR (icu_remap_calc(ICU_REMAP_NUM_PFC) + ICU_REMAP_OFFSET_CPGA)
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#define BASE_RESET_ADDR (icu_remap_calc(ICU_REMAP_NUM_PFC) + ICU_REMAP_OFFSET_RESET)
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#define BASE_APMU_ADDR (icu_remap_calc(ICU_REMAP_NUM_PFC) + ICU_REMAP_OFFSET_APMU)
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#define BASE_SYSC_ADDR (icu_remap_calc(ICU_REMAP_NUM_PFC) + ICU_REMAP_OFFSET_SYSC)
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#define BASE_OTP_MEM_ADDR (icu_remap_calc(ICU_REMAP_NUM_PFC) + ICU_REMAP_OFFSET_OTP)
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#if (RCAR_LSI == RCAR_V4M)
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#define BASE_AVS_ADDR (icu_remap_calc(ICU_REMAP_NUM_PFC) + ICU_REMAP_OFFSET_AVS)
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#endif /* (RCAR_LSI == RCAR_V4M) */
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/* REMAP12(0xE6200000U) */
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#if ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M))
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#define BASE_ECM_ADDR (icu_remap_calc(ICU_REMAP_NUM_ECM))
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#endif
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#define BASE_MFIS_ADDR (icu_remap_calc(ICU_REMAP_NUM_ECM) + ICU_REMAP_OFFSET_MFIS)
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#define BASE_ECC_ADDR (icu_remap_calc(ICU_REMAP_NUM_ECM) + ICU_REMAP_OFFSET_SDRAM_ECC)
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#define BASE_AP_CORE_ADDR (icu_remap_calc(ICU_REMAP_NUM_ECM) + ICU_REMAP_OFFSET_AP_CORE)
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/* REMAP11(0xEE200000U) */
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#define BASE_RPC_ADDR (icu_remap_calc(ICU_REMAP_NUM_RPC) + ICU_REMAP_OFFSET_RPC)
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/* REMAP10(0xFFC00000U) */
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#define BASE_RTDMA0_ADDR (icu_remap_calc(ICU_REMAP_NUM_RTDMAC) + ICU_REMAP_OFFSET_RTDMA0)
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#define BASE_RTDMACTL_ADDR (icu_remap_calc(ICU_REMAP_NUM_RTDMAC) + ICU_REMAP_OFFSET_RTDMACTL)
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#if (RCAR_LSI == RCAR_S4)
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#define BASE_PFCMCU_ADDR (icu_remap_calc(ICU_REMAP_NUM_RTDMAC) + ICU_REMAP_OFFSET_PFCMCU)
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#endif
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#if (RCAR_LSI == RCAR_S4)
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/* REMAP9(0xE6C00000U) */
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#define BASE_SCIF_ADDR (icu_remap_calc(ICU_REMAP_NUM_SCIF) + ICU_REMAP_OFFSET_SCIF3)
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#elif ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M))
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/* REMAP9(0xE6E00000U) */
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#define BASE_SCIF_ADDR (icu_remap_calc(ICU_REMAP_NUM_SCIF) + ICU_REMAP_OFFSET_SCIF0)
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#endif /* RCAR_LSI == RCAR_S4 */
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/* REMAP8(0xEE000000U) */
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#define BASE_MMC0_ADDR (icu_remap_calc(ICU_REMAP_NUM_MMC) + ICU_REMAP_OFFSET_SDHI)
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/* REMAP7(0xE6400000U) */
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#define BASE_HSCIF_ADDR (icu_remap_calc(ICU_REMAP_NUM_HSCIF) + ICU_REMAP_OFFSET_HSCIF0)
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/* REMAP6(0xE7200000U) */
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#define BASE_DMA_ADDR (icu_remap_calc(ICU_REMAP_NUM_DMAC) + ICU_REMAP_OFFSET_SYSDMAC)
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/* REMAP5(0xE7600000U) */
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#if ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M))
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#define BASE_ICISTP_ADDR (icu_remap_calc(ICU_REMAP_NUM_RGID) + ICU_REMAP_OFFSET_ICISTP)
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#endif
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#define BASE_RGID_ADDR (icu_remap_calc(ICU_REMAP_NUM_RGID) + ICU_REMAP_OFFSET_RGID)
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#if (RCAR_LSI == RCAR_S4)
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/* REMAP4(0xD8E00000U) */
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#define BASE_MCU_ADDR (icu_remap_calc(ICU_REMAP_NUM_MCU) + ICU_REMAP_OFFSET_MCU)
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#endif
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/* Calculate the base address of each register after remapping */
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static inline uint32_t icu_remap_calc(uint32_t num)
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{
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return (ICU_REMAP0 + (num * 0x00200000U));
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}
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/* End of function icu_remap_calc(uint32_t num) */
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#endif /* REMAP_REGISTER_H_ */
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