163 lines
8.7 KiB
C
163 lines
8.7 KiB
C
/*******************************************************************************
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* DISCLAIMER
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* This software is supplied by Renesas Electronics Corporation and is only
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* intended for use with Renesas products. No other uses are authorized. This
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* software is owned by Renesas Electronics Corporation and is protected under
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* all applicable laws, including copyright laws.
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* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
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* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
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* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
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* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
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* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
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* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
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* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
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* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
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* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
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* Renesas reserves the right, without notice, to make changes to this software
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* and to discontinue the availability of this software. By using this software,
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* you agree to the additional terms and conditions found by accessing the
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* following link:
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* http://www.renesas.com/disclaimer
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* Copyright 2023-2025 Renesas Electronics Corporation All rights reserved.
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*******************************************************************************/
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/*******************************************************************************
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* DESCRIPTION : RAM protection driver header
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******************************************************************************/
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#ifndef RAM_PROTECTION_H_
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#define RAM_PROTECTION_H_
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#include <stdint.h>
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#include <image_load.h>
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#define RTSRAM_AREA1_TOP (0xE0040000U)
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#define RTSRAM_ADDR_END (0xE0100000U)
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#if (RCAR_LSI == RCAR_S4)
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#define RTSRAM_ADDR_OFFSET_MASK (0x000FF000U)
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#else
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#define RTSRAM_ADDR_OFFSET_MASK (0xFFFFF000U)
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#endif
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#define RTVRAM_AREA1_TOP (0xE2010000U)
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#define RTVRAM_AREA2_TOP (0xE2100000U)
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#define RTVRAM_ADDR_END (0xE3C00000U)
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#define RTVRAM_ADDR_MASK (0xFFFFF000U)
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#if (RCAR_LSI == RCAR_S4)
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#define SYSTEM_RAM_ADDR_END (0xE6360000U)
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#else /* (RCAR_LSI == RCAR_S4) */
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/* For V4H/V4M */
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#define SYSTEM_RAM_AREA1_TOP (0xE635E000U)
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#define SYSTEM_RAM_AREA2_TOP (0xE6360000U)
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#define SYSTEM_RAM_ADDR_END (0xE6400000U)
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#endif /* (RCAR_LSI == RCAR_S4) */
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#define SYSTEM_RAM_ADDR_MASK (0xFFFFF000U)
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#if ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M))
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#define DRAM_ADDR_AREA1 (0x0401C00000ULL)
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#define DRAM_ADDR_AREA2 (0x0401D00000ULL)
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#if (OPTEE_LOAD_ENABLE == OPTEE_DISABLE)
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#define DRAM_ADDR_AREA3 (0x0406400000ULL)
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#define DRAM_ADDR_AREA4 (0x0406440000ULL)
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#define DRAM_ADDR_AREA5 (0x0407FC0000ULL)
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#define DRAM_ADDR_AREA6 (0x0408000000ULL)
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#define DRAM_ADDR_AREA7 (0x041DC00000ULL)
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#define DRAM_ADDR_AREA8 (0x0420000000ULL)
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#define DRAM_ADDR_AREA9 (0x0440000000ULL)
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#define DRAM_ADDR_AREA10 (0x0460000000ULL)
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#define DRAM_ADDR_AREA11 (0x0480000000ULL)
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#define DRAM_ADDR_AREA12 (0x0500000000ULL)
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#define DRAM_ADDR_AREA13 (0x0600000000ULL)
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#else
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#define DRAM_ADDR_AREA3 (0x0404100000ULL)
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#define DRAM_ADDR_AREA4 (0x0406400000ULL)
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#define DRAM_ADDR_AREA5 (0x0406440000ULL)
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#define DRAM_ADDR_AREA6 (0x0407E00000ULL)
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#define DRAM_ADDR_AREA7 (0x0407F00000ULL)
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#define DRAM_ADDR_AREA8 (0x0407FC0000ULL)
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#define DRAM_ADDR_AREA9 (0x0408000000ULL)
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#define DRAM_ADDR_AREA10 (0x041DC00000ULL)
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#define DRAM_ADDR_AREA11 (0x0420000000ULL)
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#define DRAM_ADDR_AREA12 (0x0440000000ULL)
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#define DRAM_ADDR_AREA13 (0x0460000000ULL)
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#define DRAM_ADDR_AREA14 (0x0480000000ULL)
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#define DRAM_ADDR_AREA15 (0x0500000000ULL)
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#define DRAM_ADDR_AREA16 (0x0600000000ULL)
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#endif /* OPTEE_LOAD_ENABLE == OPTEE_DISABLE */
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#else
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#define DRAM_ADDR_AREA1 (0x0401C00000ULL)
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#define DRAM_ADDR_AREA2 (0x0406400000ULL)
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#define DRAM_ADDR_AREA3 (0x0406440000ULL)
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#endif /* ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M)) */
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#define DRAM_ADDR_END (0x0700000000ULL)
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#define SDRAM_ADDR_MASK (0x3FFFFF0000ULL)
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#define NOT_USED_VALUE (0x00000000U)
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/* For System RAM protection setting */
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#define REGIONID0_WRITE_PRIVILEGE (0x00000001U) /* bit0 */
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/* RAM DIVISION AREA ID */
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/* RT-SRAM */
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#define RTSRAM_ICUMX_IPL_AREA (0U) /* 0xE0000000 -- 0xE003FFFF */
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#define RTSRAM_ICUMX_FW_AREA (1U) /* 0xE0040000 -- 0xE00FFFFF */
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/* RT-VRAM */
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#define RTVRAM_BLANK_AREA (0U) /* 0xE2000000 -- 0xE200FFFF */
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#define RTVRAM_EXTEND_CACHE_AREA (1U) /* 0xE2010000 -- 0xE20FFFFF */
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#define RTVRAM_RTOS_AREA (2U) /* 0xE2100000 -- 0xE3BFFFFF */
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/* System RAM */
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#define SYSTEM_RAM_CX_2ND_IPL (0U) /* 0xE6300000 -- 0xE635DFFF */
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#define SYSTEM_RAM_SHARED_MEM (1U) /* 0xE635E000 -- 0xE635FFFF */
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/* SDRAM */
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#if ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M))
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#define RTVRAM_EXTEND_AREA (0U) /* 0x04_00000000 -- 0x04_01BFFFFF */
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#define CR_FW_SHARED_AREA (1U) /* 0x04_01C00000 -- 0x04_01CFFFFF */
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#define SDRAM_BLANK_AREA (2U) /* OPTEE_DISABLE:0x04_01D00000 -- 0x04_063FFFFF
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* OPTEE_ENABLE :0x04_01D00000 -- 0x04_040FFFFF */
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#define SDRAM_PROTECT_AREA (3U) /* OPTEE_DISABLE:0x04_06400000 -- 0x04_0643FFFF
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* OPTEE_ENABLE :0x04_04100000 -- 0x04_0643FFFF */
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#if (OPTEE_LOAD_ENABLE == OPTEE_DISABLE)
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#define SDRAM_PUBLIC_AREA (4U) /* 0x04_06440000 -- 0x04_07FBFFFF */
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#define ICCOM_USED_AREA (5U) /* 0x04_07FC0000 -- 0x04_07FFFFFF */
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#define LINUX_USED_AREA (6U) /* 0x04_08000000 -- 0x04_1DBFFFFF */
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#define CAAREA2_USED_AREA (7U) /* 0x04_1DC00000 -- 0x04_1FFFFFFF */
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#define CR52_USED_AREA (8U) /* 0x04_20000000 -- 0x04_3FFFFFFF */
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#define CAAREA3_USED_AREA (9U) /* 0x04_40000000 -- 0x04_5FFFFFFF */
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#define CAAREA2_USED_AREA2 (10U) /* 0x04_60000000 -- 0x04_7FFFFFFF */
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#define CAAREA1_USED_AREA (11U) /* 0x04_80000000 -- 0x04_FFFFFFFF */
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#else
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#define SDRAM_PROTECT_AREA2 (4U) /* 0x04_06400000 -- 0x04_0643FFFF */
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#define SDRAM_BLANK_AREA2 (5U) /* 0x04_06440000 -- 0x04_07DFFFFF */
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#define OPTEE_SHARED_AREA (6U) /* 0x04_07E00000 -- 0x04_07EFFFFF */
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#define SDRAM_BLANK_AREA3 (7U) /* 0x04_07F00000 -- 0x04_07FBFFFF */
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#define ICCOM_USED_AREA (8U) /* 0x04_07FC0000 -- 0x04_07FFFFFF */
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#define LINUX_USED_AREA (9U) /* 0x04_08000000 -- 0x04_1DBFFFFF */
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#define CAAREA2_USED_AREA (10U) /* 0x04_1DC00000 -- 0x04_1FFFFFFF */
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#define CR52_USED_AREA (11U) /* 0x04_20000000 -- 0x04_3FFFFFFF */
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#define CAAREA3_USED_AREA (12U) /* 0x04_40000000 -- 0x04_5FFFFFFF */
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#define CAAREA2_USED_AREA2 (13U) /* 0x04_60000000 -- 0x04_7FFFFFFF */
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#define CAAREA1_USED_AREA (14U) /* 0x04_80000000 -- 0x04_FFFFFFFF */
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#endif /* OPTEE_LOAD_ENABLE == OPTEE_DISABLE */
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#if (RCAR_LSI == RCAR_V4H)
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#if (OPTEE_LOAD_ENABLE == OPTEE_DISABLE)
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#define RESERVERD_AREA (12U) /* 0x05_00000000 -- 0x05_FFFFFFFF */
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#define CAAREA1_USED_AREA2 (13U) /* 0x06_00000000 -- 0x06_FFFFFFFF */
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#else
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#define RESERVERD_AREA (15U) /* 0x05_00000000 -- 0x05_FFFFFFFF */
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#define CAAREA1_USED_AREA2 (16U) /* 0x06_00000000 -- 0x06_FFFFFFFF */
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#endif /* OPTEE_LOAD_ENABLE == OPTEE_DISABLE */
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#elif (RCAR_LSI == RCAR_V4M)
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#if (OPTEE_LOAD_ENABLE == OPTEE_DISABLE)
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#define CAAREA1_USED_AREA2 (12U) /* 0x05_00000000 -- 0x05_FFFFFFFF */
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#define RESERVERD_AREA (13U) /* 0x06_00000000 -- 0x06_FFFFFFFF */
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#else
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#define CAAREA1_USED_AREA2 (15U) /* 0x05_00000000 -- 0x05_FFFFFFFF */
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#define RESERVERD_AREA (16U) /* 0x06_00000000 -- 0x06_FFFFFFFF */
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#endif /* OPTEE_LOAD_ENABLE == OPTEE_DISABLE */
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#endif /* RCAR_LSI == RCAR_V4H */
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#else
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#define RTVRAM_EXTEND_AREA (0U) /* 0x04_00000000 -- 0x04_01BFFFFF */
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#define SDRAM_BLANK_AREA (1U) /* 0x04_01C00000 -- 0x04_063FFFFF */
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#define SDRAM_PROTECT_AREA (2U) /* 0x04_06400000 -- 0x04_0643FFFF */
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#define SDRAM_PUBLIC_AREA (3U) /* 0x04_06440000 -- 0x06_FFFFFFFF */
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#endif /* ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M)) */
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#endif /* RAM_PROTECTION_H_ */
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