155 lines
8.3 KiB
C
155 lines
8.3 KiB
C
/*******************************************************************************
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* DISCLAIMER
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* This software is supplied by Renesas Electronics Corporation and is only
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* intended for use with Renesas products. No other uses are authorized. This
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* software is owned by Renesas Electronics Corporation and is protected under
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* all applicable laws, including copyright laws.
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* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
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* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
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* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
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* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
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* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
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* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
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* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
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* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
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* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
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* Renesas reserves the right, without notice, to make changes to this software
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* and to discontinue the availability of this software. By using this software,
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* you agree to the additional terms and conditions found by accessing the
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* following link:
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* http://www.renesas.com/disclaimer
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* Copyright 2021-2025 Renesas Electronics Corporation All rights reserved.
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*******************************************************************************/
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/*******************************************************************************
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* DESCRIPTION : PFC register header
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******************************************************************************/
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#ifndef PFC_REGISTER_H__
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#define PFC_REGISTER_H__
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#include <stdint.h>
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#include <remap_register.h>
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/* PFC / GPIO base address */
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/* 0xE6050000 */
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#define PFC_BASE (BASE_PFC_ADDR)
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#define PFC_RW_OFFSET (0x0000U)
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#define PFC_SET_OFFSET (0x0200U)
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#define PFC_CLR_OFFSET (0x0400U)
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#if (RCAR_LSI == RCAR_S4)
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#define PFC_MCU_BASE (BASE_PFCMCU_ADDR)
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#define PFC_PORT_GRP0 (0x00000000U) /* Port Group0/4 */
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#define PFC_PORT_GRP1 (0x00000800U) /* Port Group1/5 */
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#define PFC_PORT_GRP2 (0x00001000U) /* Port Group2/6 */
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#define PFC_PORT_GRP3 (0x00001800U) /* Port Group3/7 */
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#define PFC_SYS_GRP (0x00028000U) /* System Group0/1 */
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#elif ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M))
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#define PFC_PORT_GRP0 (0x00000000U) /* Port Group0 */
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#define PFC_PORT_GRP1 (0x00000800U) /* Port Group1 */
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#define PFC_PORT_GRP2 (0x00008000U) /* Port Group2 */
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#define PFC_PORT_GRP3 (0x00008800U) /* Port Group3 */
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#define PFC_PORT_GRP4 (0x00010000U) /* Port Group4 */
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#define PFC_PORT_GRP5 (0x00010800U) /* Port Group5 */
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#define PFC_PORT_GRP6 (0x00011000U) /* Port Group6 */
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#define PFC_PORT_GRP7 (0x00011800U) /* Port Group7 */
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#if (RCAR_LSI == RCAR_V4H)
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#define PFC_PORT_GRP8 (0x00018000U) /* Port Group8 */
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#endif
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#define PFC_SYS_GRP (0x00028000U) /* System Group0 */
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#endif
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/* PFC / GPIO registers */
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/* Read/Write registers */
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#define PFC_PORT_GRP_MASK (0xFFFFF800U)
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/* Port Group0 */
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#define PFC_DM1PR0_RW (PFC_BASE + PFC_PORT_GRP0 + PFC_RW_OFFSET + 0x0024U)
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#define PFC_DM2PR0_RW (PFC_BASE + PFC_PORT_GRP0 + PFC_RW_OFFSET + 0x0028U)
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#define PFC_DM3PR0_RW (PFC_BASE + PFC_PORT_GRP0 + PFC_RW_OFFSET + 0x002CU)
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#define PFC_GPSR0_RW (PFC_BASE + PFC_PORT_GRP0 + PFC_RW_OFFSET + 0x0040U)
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#define PFC_IP0SR0_RW (PFC_BASE + PFC_PORT_GRP0 + PFC_RW_OFFSET + 0x0060U)
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#define PFC_POC0_RW (PFC_BASE + PFC_PORT_GRP0 + PFC_RW_OFFSET + 0x00A0U)
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/* Port Group1 */
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#define PFC_DM1PR1_RW (PFC_BASE + PFC_PORT_GRP1 + PFC_RW_OFFSET + 0x0024U)
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#define PFC_DM2PR1_RW (PFC_BASE + PFC_PORT_GRP1 + PFC_RW_OFFSET + 0x0028U)
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#define PFC_DM3PR1_RW (PFC_BASE + PFC_PORT_GRP1 + PFC_RW_OFFSET + 0x002CU)
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#define PFC_GPSR1_RW (PFC_BASE + PFC_PORT_GRP1 + PFC_RW_OFFSET + 0x0040U)
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#define PFC_IP1SR1_RW (PFC_BASE + PFC_PORT_GRP1 + PFC_RW_OFFSET + 0x0064U)
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#define PFC_IP2SR1_RW (PFC_BASE + PFC_PORT_GRP1 + PFC_RW_OFFSET + 0x0068U)
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#define PFC_POC1_RW (PFC_BASE + PFC_PORT_GRP1 + PFC_RW_OFFSET + 0x00A0U)
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/* Port Group2 */
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#define PFC_DM1PR2_RW (PFC_BASE + PFC_PORT_GRP2 + PFC_RW_OFFSET + 0x0024U)
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#define PFC_DM2PR2_RW (PFC_BASE + PFC_PORT_GRP2 + PFC_RW_OFFSET + 0x0028U)
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#define PFC_DM3PR2_RW (PFC_BASE + PFC_PORT_GRP2 + PFC_RW_OFFSET + 0x002CU)
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/* Port Group3 */
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#define PFC_DM1PR3_RW (PFC_BASE + PFC_PORT_GRP3 + PFC_RW_OFFSET + 0x0024U)
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#define PFC_DM2PR3_RW (PFC_BASE + PFC_PORT_GRP3 + PFC_RW_OFFSET + 0x0028U)
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#define PFC_DM3PR3_RW (PFC_BASE + PFC_PORT_GRP3 + PFC_RW_OFFSET + 0x002CU)
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#define PFC_POC3_RW (PFC_BASE + PFC_PORT_GRP3 + PFC_RW_OFFSET + 0x00A0U)
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#define PFC_PUEN3_RW (PFC_BASE + PFC_PORT_GRP3 + PFC_RW_OFFSET + 0x00C0U)
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/* Port Group4 */
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#define PFC_DM1PR4_RW (PFC_BASE + PFC_PORT_GRP4 + PFC_RW_OFFSET + 0x0024U)
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#define PFC_DM2PR4_RW (PFC_BASE + PFC_PORT_GRP4 + PFC_RW_OFFSET + 0x0028U)
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#define PFC_DM3PR4_RW (PFC_BASE + PFC_PORT_GRP4 + PFC_RW_OFFSET + 0x002CU)
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/* Physical address:0xE6060040, Logical address:0x0xFDA60040 */
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#define PFC_GPSR4_RW (PFC_BASE + PFC_PORT_GRP4 + PFC_RW_OFFSET + 0x0040U)
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/* Physical address:0xE6060060, Logical address:0x0xFDA60060 */
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#define PFC_IP0SR4_RW (PFC_BASE + PFC_PORT_GRP4 + PFC_RW_OFFSET + 0x0060U)
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/* Physical address:0xE60600C0, Logical address:0x0xFDA600C0 */
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#define PFC_PUEN4_RW (PFC_BASE + PFC_PORT_GRP4 + PFC_RW_OFFSET + 0x00C0U)
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/* Physical address:0xE6060100, Logical address:0x0xFDA60100 */
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#define PFC_MODSEL4_RW (PFC_BASE + PFC_PORT_GRP4 + PFC_RW_OFFSET + 0x0100U)
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#define PFC_IOINTSEL4_RW (PFC_BASE + PFC_PORT_GRP4 + PFC_RW_OFFSET + 0x0180U)
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#define PFC_INOUTSEL4_RW (PFC_BASE + PFC_PORT_GRP4 + PFC_RW_OFFSET + 0x0184U)
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#define PFC_OUTDT4_RW (PFC_BASE + PFC_PORT_GRP4 + PFC_RW_OFFSET + 0x0188U)
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#define PFC_INDT4_R (PFC_BASE + PFC_PORT_GRP4 + PFC_RW_OFFSET + 0x018CU)
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#define PFC_POSNEG4_RW (PFC_BASE + PFC_PORT_GRP4 + PFC_RW_OFFSET + 0x01A0U)
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#define PFC_OUTDTSEL4_RW (PFC_BASE + PFC_PORT_GRP4 + PFC_RW_OFFSET + 0x01C0U)
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#define PFC_OUTDTH4_RW (PFC_BASE + PFC_PORT_GRP4 + PFC_RW_OFFSET + 0x01C4U)
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#define PFC_OUTDTL4_RW (PFC_BASE + PFC_PORT_GRP4 + PFC_RW_OFFSET + 0x01C8U)
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#define PFC_INEN4_RW (PFC_BASE + PFC_PORT_GRP4 + PFC_RW_OFFSET + 0x01D0U)
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/* Port Group5 */
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#define PFC_DM1PR5_RW (PFC_BASE + PFC_PORT_GRP5 + PFC_RW_OFFSET + 0x0024U)
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#define PFC_DM2PR5_RW (PFC_BASE + PFC_PORT_GRP5 + PFC_RW_OFFSET + 0x0028U)
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#define PFC_DM3PR5_RW (PFC_BASE + PFC_PORT_GRP5 + PFC_RW_OFFSET + 0x002CU)
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/* Port Group6 */
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#define PFC_DM1PR6_RW (PFC_BASE + PFC_PORT_GRP6 + PFC_RW_OFFSET + 0x0024U)
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#define PFC_DM2PR6_RW (PFC_BASE + PFC_PORT_GRP6 + PFC_RW_OFFSET + 0x0028U)
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#define PFC_DM3PR6_RW (PFC_BASE + PFC_PORT_GRP6 + PFC_RW_OFFSET + 0x002CU)
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/* Port Group7 */
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#define PFC_DM1PR7_RW (PFC_BASE + PFC_PORT_GRP7 + PFC_RW_OFFSET + 0x0024U)
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#define PFC_DM2PR7_RW (PFC_BASE + PFC_PORT_GRP7 + PFC_RW_OFFSET + 0x0028U)
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#define PFC_DM3PR7_RW (PFC_BASE + PFC_PORT_GRP7 + PFC_RW_OFFSET + 0x002CU)
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#if (RCAR_LSI == RCAR_V4H)
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/* Port Group8 */
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#define PFC_DM1PR8_RW (PFC_BASE + PFC_PORT_GRP8 + PFC_RW_OFFSET + 0x0024U)
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#define PFC_DM2PR8_RW (PFC_BASE + PFC_PORT_GRP8 + PFC_RW_OFFSET + 0x0028U)
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#define PFC_DM3PR8_RW (PFC_BASE + PFC_PORT_GRP8 + PFC_RW_OFFSET + 0x002CU)
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#define PFC_INOUTSEL8_RW (PFC_BASE + PFC_PORT_GRP8 + PFC_RW_OFFSET + 0x0184U)
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#define PFC_OUTDT8_RW (PFC_BASE + PFC_PORT_GRP8 + PFC_RW_OFFSET + 0x0188U)
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#endif
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/* System Group */
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#define PFC_DM1PRSYS_RW (PFC_BASE + PFC_SYS_GRP + PFC_RW_OFFSET + 0x0024U)
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#define PFC_DM2PRSYS_RW (PFC_BASE + PFC_SYS_GRP + PFC_RW_OFFSET + 0x0028U)
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#define PFC_DM3PRSYS_RW (PFC_BASE + PFC_SYS_GRP + PFC_RW_OFFSET + 0x002CU)
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#if ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M))
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/* Physical address:0xE6068040 */
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#define PFC_GPSR8_RW (PFC_BASE + PFC_PORT_GRP8 + PFC_RW_OFFSET + 0x0040U)
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#define PFC_IP1SR8_RW (PFC_BASE + PFC_PORT_GRP8 + PFC_RW_OFFSET + 0x0064U)
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#define PFC_PUEN8_RW (PFC_BASE + PFC_PORT_GRP8 + PFC_RW_OFFSET + 0x00C0U)
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#define PFC_MODSEL8_RW (PFC_BASE + PFC_PORT_GRP8 + PFC_RW_OFFSET + 0x0100U)
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#endif
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static inline uint32_t get_pmmr_addr(uint32_t addr)
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{
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return (addr & PFC_PORT_GRP_MASK);
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}
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#endif /* PFC_REGISTER_H__ */
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