72 lines
4.6 KiB
C
72 lines
4.6 KiB
C
/*******************************************************************************
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* DISCLAIMER
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* This software is supplied by Renesas Electronics Corporation and is only
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* intended for use with Renesas products. No other uses are authorized. This
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* software is owned by Renesas Electronics Corporation and is protected under
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* all applicable laws, including copyright laws.
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* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
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* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
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* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
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* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
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* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
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* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
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* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
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* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
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* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
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* Renesas reserves the right, without notice, to make changes to this software
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* and to discontinue the availability of this software. By using this software,
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* you agree to the additional terms and conditions found by accessing the
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* following link:
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* http://www.renesas.com/disclaimer
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* Copyright 2022 Renesas Electronics Corporation All rights reserved.
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*******************************************************************************/
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/*******************************************************************************
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* DESCRIPTION : Interrupt controler ID header
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******************************************************************************/
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#ifndef INTC_ID_H_
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#define INTC_ID_H_
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#define ECC_ERR_LRAM (0U) /* ECC Error Detection for Local RAM */
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#define ECC_ERR_CACHE (1U) /* ECC Error Detection for Cache RAM */
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#define EDC_ERR_INT_AXI (2U) /* EDC Error interrupt of AXI */
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#define ECC_ERR_INT_AXIAB (3U) /* ECC Error interrupt of AXIAB */
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#define ECC_ERR_INT_PKCC (4U) /* ECC Error interrupt of PKCC */
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#define CORTEX_INT_REQ_SINGLE_CORE (5U) /* Cortex-R/A interrupt request (single main core) */
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#define CORTEX_INT_REQ_SEL_SINGLE_CORE (6U) /* Cortex-R/A interrupt request (selected single main core) */
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#define COMPLETION_AES (7U) /* Completion of AES encryption or decryption */
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/* ID 8 Reserved */
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#define COMPLETION_RAND_NUMBER (9U) /* Random number generation complete */
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#define OSTIMER0_OVERFLOW (10U) /* OS Timer 0 overflow */
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#define OSTIMER1_OVERFLOW (11U) /* OS Timer 1 overflow */
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#define WDT0_INT (12U) /* Watchdog Timer 0 interrupt (at 75%) */
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#define COMPLETION_PKCC (13U) /* Completion of PKCC operation */
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#define COMPLETION_DMAC_CH5CH6 (14U) /* Interrupt request by transfer completion for channel-5/6 */
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#define INT_REQ_BRESP_RRESP_ERR_AXI (15U) /* Interrupt request by BRESP/RRESP-error for AXI */
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/* ID 16 Reserved */
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#define REQ_SHAA0 (17U) /* Input data request for SHAA0 */
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#define COMPLETION_SHAA0 (18U) /* Completion or suspension of SHAA0 data output */
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#define REQ_CHALLENGE_DATA_FOR_ARM_DEBUG (19U) /* Challenge data request for ARM Debugger */
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#define REQ_RES_COMP_FOR_ARM_DEBUG (20U) /* Response data compare request for ARM Debugger */
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#define REQ_CHALLENGE_DATA_FOR_RH850_DEBUG (21U) /* Challenge data request for RH850 Debugger */
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#define REQ_RES_COMP_FOR_RH850_DEBUG (22U) /* Response data compare request for RH850 Debugger */
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#define REQ_CHALLENGE_DATA_FOR_RH850_DEBUG_R (23U) /* Challenge data request for RH850 Debugger r */
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/* Reserved */
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#define ACC_ERR_MASKROM_RTSRAM (25U) /* Data access error detection of Mask ROM or RTSRAM area */
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#define ACC_ERR_EXCEPT_MASKROM_RTSRAM (26U) /* Data access error detection except Mask ROM and RT-SRAM area */
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/* ID 27 Reserved */
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/* ID 28 Reserved */
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#define RTSRAM_SAFETY_ERR (29U) /* RT-SRAM Error Safety Error Detection */
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#define RTSRAM_SECURE_ERR (30U) /* RT-SRAM Error Secure Error Detection */
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#define RTSRAM_EDC_ERR (31U) /* RT-SRAM Error EDC Error Detection */
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#define RTSRAM_DUPLEX_ERR (32U) /* RT-SRAM Error Duplex circuit Error Detection */
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#define RTSRAM_SYSRAM_2BIT_ERR (33U) /* RT-SRAM Error SYSRAM 2bit Error Detection */
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#define RTSRAM_SYSRAM_1BIT_ERR (34U) /* RT-SRAM Error SYSRAM 1bit Error Detection */
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#define SECROM_SYSRAM_2BIT_ERR (35U) /* Sec ROM Error SYSRAM 2bit Error Detection */
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#define SECROM_SYSRAM_1BIT_ERR (36U) /* Sec ROM Error SYSRAM 1bit Error Detection */
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#define COMPLETION_SECURE_BOOT_ENGINE_CALC (37U) /* Completion of secure boot engine calculation */
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/* ID 38 -- 63 Reserved */
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#endif /* INTC_ID_H_ */
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