Files
Tool/IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/emmc_config.h
2025-12-24 17:21:08 +09:00

83 lines
3.7 KiB
C

/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
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* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
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* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
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* you agree to the additional terms and conditions found by accessing the
* following link:
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* Copyright 2021-2023 Renesas Electronics Corporation All rights reserved.
*******************************************************************************/
/*******************************************************************************
* DESCRIPTION : eMMC Config header
******************************************************************************/
#ifndef EMMC_CONFIG_H__
#define EMMC_CONFIG_H__
/* ************************ HEADER (INCLUDE) SECTION *********************** */
#include "cpg_register.h"
#include "pfc_register.h"
#include "cpg.h"
#include "pfc.h"
/* ***************** MACROS, CONSTANTS, COMPILATION FLAGS ****************** */
/* MMC driver config */
#define EMMC_RCA (1U) /* RCA */
#define EMMC_RW_DATA_TIMEOUT (0x40U) /* 314ms (freq = 400KHz, timeout Counter = 0x04(SDCLK * 2^17) */
#define EMMC_CMD_MAX (60U) /* Don't change. */
/* etc */
#define LOADIMAGE_FLAGS_DMA_ENABLE (0x00000001U)
/* Module stop */
#define CPG_MSTPCR_SDHI (1U << 6U)
/* clock */
#define CPG_SD0CKCR0_STP0HCK (1U << 9U)
#define CPG_SD0CKCR0_SDSRCFC_MASK (7U << 2U)
#define CPG_SD0CKCR0_SDSRCFC_000 (0U << 2U)
#define CPG_SD0CKCR0_SDSRCFC_010 (2U << 2U)
#define CPG_SD0CKCR0_SD0FC_MASK (3U << 0U)
#define CPG_SD0CKCR0_SD0FC_DIV2 (0U << 0U)
#define CPG_SD0CKCR0_SD0FC_DIV4 (1U << 0U)
#define CPG_SD0CKCR0_100MHZ (CPG_SD0CKCR0_STP0HCK | CPG_SD0CKCR0_SDSRCFC_010 | CPG_SD0CKCR0_SD0FC_DIV2)
#define CPG_SD0CKCR0_200MHZ (CPG_SD0CKCR0_STP0HCK | CPG_SD0CKCR0_SDSRCFC_000 | CPG_SD0CKCR0_SD0FC_DIV4)
#if (RCAR_LSI == RCAR_S4)
#define PFC_POC_MMC_RW (PFC_POC1_RW)
#define PFC_POC_MMC_MASK (0x007FF000U)
#define PFC_POC_MMC_VAL (0x00000000U)
#elif ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M))
#define PFC_POC_MMC_RW (PFC_POC3_RW)
#define PFC_POC_MMC_MASK (0x000007FFU)
#define PFC_POC_MMC_VAL (0x00000000U)
#endif /* RCAR_LSI == RCAR_S4 */
/* ********************** STRUCTURES, TYPE DEFINITIONS ********************* */
/* ********************** DECLARATION OF EXTERNAL DATA ********************* */
/* ************************** FUNCTION PROTOTYPES ************************** */
/* ********************************* CODE ********************************** */
#endif /* #ifndef EMMC_CONFIG_H__ */
/* ******************************** END ************************************ */