285 lines
16 KiB
C
285 lines
16 KiB
C
/**********************************************************/
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/* Sample program : VMSA Table Generate */
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/* File Name : vmsatable.c */
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/* Copyright (C) Renesas Electronics Corp. 2015. */
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/**********************************************************/
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// #include "common.h"
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#include <stdint.h>
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#include "vmsatable.h"
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#include "d_armasm.h"
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#ifdef AArch64
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extern const char MMU_BASE_CPU0[];
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#endif
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#ifdef AArch32
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#define MMU_BASE_CPU0 0xE6300000
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#endif
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#define TBL_SIZE 4096
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#define TBL_NUM (TBL_SIZE/8)
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#define Lvl1VmsaTbl ((uintptr_t)MMU_BASE_CPU0+0x0000) // +0kB
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#define Lvl2VmsaTbl ((uintptr_t)MMU_BASE_CPU0+0x1000) // +4kB
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#define Lvl3VmsaTbl ((uintptr_t)MMU_BASE_CPU0+0x2000) // +8kB
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#define Lvl1StartAddr (0x0000000000)
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#define Lvl1BlockSize (0x0040000000) // 1GB
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#define Lvl1BlockShift (30) // BIT30
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#define Lvl2StartAddr (0x00C0000000)
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#define Lvl2BlockSize (0x0000200000) // 2MB
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#define Lvl2BlockShift (21) // BIT21
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#define Lvl3StartAddr (0x00E6200000)
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#define Lvl3BlockSize (0x0000001000) // 4KB
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#define Lvl3BlockShift (12) // BIT12
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#define BIT47_12 0x0000FFFFFFFFF000
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typedef struct vmsaTable{
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uint64_t vAddr;
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uint64_t pAddr;
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uint64_t unit;
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uint64_t upperAttr;
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uint64_t lowerAttr;
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}vmsaTable;
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//------------------------------------------------------------------
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// Referenced: DDI0487A_f_armv8_arm.pdf
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// D4.4 VMSAv8-64 translation table format descriptors
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//------------------------------------------------------------------
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#define ATTR_TBL 0x444444FF0C080400 // MAIR_EL1
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// // [63:56]Attr7=0x44 : ----------------- (Blank)
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// // [55:48]Attr6=0x44 : ----------------- (Blank)
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// // [47:40]Attr5=0x44 : NORMAL_NON_CACHEABLE Normal Memory Non-Cacheable
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// // [39:32]Attr4=0x77 : NORMAL_WRITE_BACK Normal Memory Write-back transient
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// // [31:24]Attr3=0x0C : DEVICE_GRE_MEM Device-GRE memory
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// // [23:16]Attr2=0x08 : DEVICE_NGRE_MEM Device-nGRE memory
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// // [15: 8]Attr1=0x04 : DEVICE_NGNRE_MEM Device-nGnRE memory
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// // [ 7: 0]Attr0=0x00 : DEVICE_NGNRNE_MEM Device-nGnRnE memory
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// CPU0 VMSA table Level1 (4kB)
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// Virtual address == Physical Address
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const vmsaTable ArmVmsaTblLvl1Cpu0ForDDR4ch[] = {
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// [MEM]Memory Address ...BIT[1:0]=01
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// [TBL]Next Level Table Address ...BIT[1:0]=11
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// Virtual Address Physical Address BLOCK Upper Lower Attr
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// (Input) or units, Attributes Attributes nG AF SH AP NS Indx [1:0]
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// Next Level Table (1GBxN) [63:52] [11:00] [1:0][2:1] [2:0]
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{ 0x0000000000, 0x0000000000, 1, 0x000, 0x411 }, // [MEM]CS0/1,PCIe 1GB 0 1 00 00 0 100 01 (Normal Memory Write-back transient)
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{ 0x0040000000, 0x0040000000, 1, 0x000, 0x411 }, // [MEM]DRAM 1st 1GB 0 1 00 00 0 100 01 (Normal Memory Write-back transient)
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{ 0x0080000000, 0x0080000000, 1, 0x000, 0x411 }, // [MEM]DRAM 2nd 1GB 0 1 00 00 0 100 01 (Normal Memory Write-back transient)
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{ 0x00C0000000, Lvl2VmsaTbl , 1, 0x000, 0x003 }, // [TBL]IPs 1GB 0 0 00 00 0 000 11 (Next Level Table)
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{ 0x0400000000, 0x0400000000, 4, 0x000, 0x411 }, // [MEM]DDR0 4GB 0 1 10 00 0 100 01 (Normal Memory Write-back transient)
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{ 0x0500000000, 0x0500000000, 4, 0x000, 0x411 }, // [MEM]DDR1 4GB 0 1 10 00 0 100 01 (Normal Memory Write-back transient)
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{ 0x0600000000, 0x0600000000, 4, 0x000, 0x411 }, // [MEM]DDR2 4GB 0 1 10 00 0 100 01 (Normal Memory Write-back transient)
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{ 0x0700000000, 0x0700000000, 4, 0x000, 0x411 }, // [MEM]DDR3 4GB 0 1 10 00 0 100 01 (Normal Memory Write-back transient)
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{ 0x0000000000, 0x0000000000, 0, 0x000, 0x000 }, // ---------- END of Table ----------
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};
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// CPU0 VMSA table Level1 (4kB)
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// Virtual address == Physical Address
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const vmsaTable ArmVmsaTblLvl1Cpu0ForDDR2ch[] = {
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// [MEM]Memory Address ...BIT[1:0]=01
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// [TBL]Next Level Table Address ...BIT[1:0]=11
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// Virtual Address Physical Address BLOCK Upper Lower Attr
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// (Input) or units, Attributes Attributes nG AF SH AP NS Indx [1:0]
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// Next Level Table (1GBxN) [63:52] [11:00] [1:0][2:1] [2:0]
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{ 0x0000000000, 0x0000000000, 1, 0x000, 0x411 }, // [MEM]CS0/1,PCIe 1GB 0 1 00 00 0 100 01 (Normal Memory Write-back transient)
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{ 0x0040000000, 0x0040000000, 1, 0x000, 0x411 }, // [MEM]DRAM 1st 1GB 0 1 00 00 0 100 01 (Normal Memory Write-back transient)
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{ 0x0080000000, 0x0080000000, 1, 0x000, 0x411 }, // [MEM]DRAM 2nd 1GB 0 1 00 00 0 100 01 (Normal Memory Write-back transient)
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{ 0x00C0000000, Lvl2VmsaTbl , 1, 0x000, 0x003 }, // [TBL]IPs 1GB 0 0 00 00 0 000 11 (Next Level Table)
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{ 0x0400000000, 0x0400000000, 4, 0x000, 0x411 }, // [MEM]DDR0 4GB 0 1 10 00 0 100 01 (Normal Memory Write-back transient)
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{ 0x0600000000, 0x0600000000, 4, 0x000, 0x411 }, // [MEM]DDR2 4GB 0 1 10 00 0 100 01 (Normal Memory Write-back transient)
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{ 0x0000000000, 0x0000000000, 0, 0x000, 0x000 }, // ---------- END of Table ----------
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};
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// CPU0 VMSA table Level1 (4kB)
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// Virtual address == Physical Address
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const vmsaTable ArmVmsaTblLvl1Cpu0ForDDR1ch[] = {
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// [MEM]Memory Address ...BIT[1:0]=01
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// [TBL]Next Level Table Address ...BIT[1:0]=11
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// Virtual Address Physical Address BLOCK Upper Lower Attr
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// (Input) or units, Attributes Attributes nG AF SH AP NS Indx [1:0]
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// Next Level Table (1GBxN) [63:52] [11:00] [1:0][2:1] [2:0]
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{ 0x0000000000, 0x0000000000, 1, 0x000, 0x411 }, // [MEM]CS0/1,PCIe 1GB 0 1 00 00 0 100 01 (Normal Memory Write-back transient)
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{ 0x0040000000, 0x0040000000, 1, 0x000, 0x411 }, // [MEM]DRAM 1st 1GB 0 1 00 00 0 100 01 (Normal Memory Write-back transient)
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{ 0x0080000000, 0x0080000000, 1, 0x000, 0x411 }, // [MEM]DRAM 2nd 1GB 0 1 00 00 0 100 01 (Normal Memory Write-back transient)
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{ 0x00C0000000, Lvl2VmsaTbl , 1, 0x000, 0x003 }, // [TBL]IPs 1GB 0 0 00 00 0 000 11 (Next Level Table)
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{ 0x0400000000, 0x0400000000, 4, 0x000, 0x411 }, // [MEM]DDR0 4GB 0 1 10 00 0 100 01 (Normal Memory Write-back transient)
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{ 0x0000000000, 0x0000000000, 0, 0x000, 0x000 }, // ---------- END of Table ----------
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};
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// CPU0 VMSA table Level2 (4kB)
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// Virtual address == Physical Address
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const vmsaTable ArmVmsaTblLvl2Cpu0[] = {
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// [MEM]Memory Address ...BIT[1:0]=01
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// [TBL]Next Level Table Address ...BIT[1:0]=11
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// Virtual Address Physical Address BLOCK Upper Lower Attr
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// (Input) or units, Attributes Attributes nG AF SH AP NS Indx [1:0]
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// Next Level Table (2MBxN) [63:52] [11:00] [1:0][2:1] [2:0]
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{ 0x00E6200000, Lvl3VmsaTbl , 1, 0x000, 0x003 }, // [TBL]IPs 2MB 0 0 00 00 0 000 11 (Next Level Table)
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{ 0x00EB200000, 0x00EB200000, 1, 0x000, 0x411 }, // [MEM]RT-SRAM 2MB 0 1 00 00 0 100 01 (Normal Memory Write-back transient) @V3U
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{ 0x0000000000, 0x0000000000, 0, 0x000, 0x000 }, // ---------- END of Table ----------
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};
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#ifdef SYSTEM_DEF_FALCON
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// CPU0 VMSA table Level3 (4kB) @V3U CPUボード到着後に上のvmsaTable ArmVmsaTblLvl3Cpu0[]と入れ替え
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// Virtual address == Physical Address
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const vmsaTable ArmVmsaTblLvl3Cpu0[] = {
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// [INV]Invalid ...BIT[1:0]=x0
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// [RES]Reserved ...BIT[1:0]=01
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// [MEM]Memory Address ...BIT[1:0]=11 <-- Select
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// Virtual Address Physical Address BLOCK Upper Lower Attr
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// (Input) or units, Attributes Attributes nG AF SH AP NS Indx [1:0]
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// Next Level Table (4KBxN) [63:52] [11:00] [1:0][2:1] [2:0]
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{ 0x00E6200000, 0x00E6200000, 256, 0x000, 0x403 }, // [MEM]IPs 1MB 0 1 00 00 0 000 11 (Device-nGnRnE memory)
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{ 0x00E6300000, 0x00E6300000, 256, 0x000, 0x413 }, // [MEM]SystemRAM 1MB 0 1 00 00 0 100 11 (Normal Memory Write-back transient) @V3U
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{ 0x0000000000, 0x0000000000, 0, 0x000, 0x000 }, // ---------- END of Table ----------
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};
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#else
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// CPU0 VMSA table Level3 (4kB) @V3H
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// Virtual address == Physical Address
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const vmsaTable ArmVmsaTblLvl3Cpu0[] = {
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// [INV]Invalid ...BIT[1:0]=x0
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// [RES]Reserved ...BIT[1:0]=01
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// [MEM]Memory Address ...BIT[1:0]=11 <-- Select
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// Virtual Address Physical Address BLOCK Upper Lower Attr
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// (Input) or units, Attributes Attributes nG AF SH AP NS Indx [1:0]
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// Next Level Table (4KBxN) [63:52] [11:00] [1:0][2:1] [2:0]
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{ 0x00E6200000, 0x00E6200000, 256, 0x000, 0x403 }, // [MEM]IPs 1MB 0 1 00 00 0 000 11 (Device-nGnRnE memory)
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{ 0x00E6300000, 0x00E6300000, 48, 0x000, 0x413 }, // [MEM]SystemRAM 192KB 0 1 00 00 0 100 11 (Normal Memory Write-back transient)
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{ 0x00E6330000, 0x00E6330000, 48, 0x000, 0x413 }, // [MEM]SystemRAM 192KB 0 1 00 00 0 100 11 (Normal Memory Write-back transient)
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{ 0x00E6360000, 0x00E6360000, 160, 0x000, 0x403 }, // [MEM]SystemRAM 640KB 0 1 00 00 0 000 11 (Device-nGnRnE memory)
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{ 0x0000000000, 0x0000000000, 0, 0x000, 0x000 }, // ---------- END of Table ----------
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};
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#endif
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static void MakeVmsaTable(uint64_t *vmsaTblSadd, vmsaTable *vmsaSrcTbl, uint64_t startAddr, uint64_t blockShift);
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uint32_t SetVmsaTable(void)
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{
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uint64_t *vmsaTblSadd;
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vmsaTable *vmsaSrcTbl;
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uint64_t startAddr;
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uint64_t blockShift;
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// TCR_EL3, Translation Control Register (EL3)
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// [31] Reserved-1: 1
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// [30:29] Reserved-0: 0
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//
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// When ARMv8.2-TTPBHA is implemented
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// [28] HWU62 : 0 :Bit[62] of each stage 1 translation table Block or Page entry cannot be used by hardware for an IMPLEMENTATION DEFINED purpose.
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// [27] HWU61 : 0 :Bit[61] of each stage 1 translation table Block or Page entry cannot be used by hardware for an IMPLEMENTATION DEFINED purpose.
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// [26] HWU60 : 0 :Bit[60] of each stage 1 translation table Block or Page entry cannot be used by hardware for an IMPLEMENTATION DEFINED purpose.
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// [25] HWU59 : 0 :Bit[59] of each stage 1 translation table Block or Page entry cannot be used by hardware for an IMPLEMENTATION DEFINED purpose.
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// -The Effective value of this field is 0 if the value of TCR_EL3.HPD is 0.
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// -This field resets to an architecturally UNKNOWN value.
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// [24] HPD : 0 :Hierarchical Permission Disables.
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// Otherwise
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// [28:24] Reserved-0: 00000
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//
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// [23] Reserved-1: 1
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// When ARMv8.1-TTHM is implemented
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// [22] HD : 0 :Hardware management of dirty state in stage 1 translations from EL3.
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// [21] HA : 0 :Hardware Access flag update in stage 1 translations from EL3.
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// Otherwise
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// [22:21] Reserved-0: 00
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//
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// [20] TBI : 0 : Top Byte used in the address calculation.
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// [19] Reserved-0: 0
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// [18:16] PS : 001 : Physical Address Size 000=32bit, 001=36bit, 010=40bit, 011=42bit, 100=44bit, 101=48bit
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// [15:14] TG0 : 00 : translation table 00=4KB, 01=64KB, 10=16KB
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// [13:12] SH0 : 10 : translation table memory 00=Non-shareable, 10=Outer Shareable, 11=Inner Shareable
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// [11:10] ORGN0 : 01 : Outer 01=Write-Back Write-Allocate Cacheable
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// [09:08] IRGN0 : 01 : Inner 01=Write-Back Write-Allocate Cacheable
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// [07:06] Reserved : 00
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// [05:00] T0SZ : 011100 : The region size is 2^(64-T0SZ) byte. 2^(64-28)=2^36=0x10_0000_0000
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WriteTCR_EL3(0x8081251C);
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WriteMAIR_EL3(ATTR_TBL);
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WriteTTBR0_EL3((uint64_t)Lvl1VmsaTbl); // ASID=0
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#ifdef SYSTEM_DEF_FALCON
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// VMSA Table Level1 for Main
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vmsaSrcTbl = (vmsaTable*)ArmVmsaTblLvl1Cpu0ForDDR4ch;
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#else
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// VMSA Table Level1 for Main
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// if( CHK_H3 && (!CHK_H3N) ){ vmsaSrcTbl = (vmsaTable*)ArmVmsaTblLvl1Cpu0ForDDR4ch; } // 4ch : H3
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// else if( CHK_M3 ){ vmsaSrcTbl = (vmsaTable*)ArmVmsaTblLvl1Cpu0ForDDR2ch; } // 2ch : M3
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// else if( CHK_H3N ){ vmsaSrcTbl = (vmsaTable*)ArmVmsaTblLvl1Cpu0ForDDR2ch; } // 2ch : H3N
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// else { vmsaSrcTbl = (vmsaTable*)ArmVmsaTblLvl1Cpu0ForDDR1ch; } // 1ch : M3N,V3H,V3M,D3,E3
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#endif
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vmsaSrcTbl = (vmsaTable*)ArmVmsaTblLvl1Cpu0ForDDR4ch;
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vmsaTblSadd = (uint64_t*)Lvl1VmsaTbl;
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startAddr = Lvl1StartAddr;
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blockShift = Lvl1BlockShift;
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MakeVmsaTable(vmsaTblSadd, vmsaSrcTbl, startAddr, blockShift);
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// VMSA Table Level2 for IPs
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vmsaSrcTbl = (vmsaTable*)ArmVmsaTblLvl2Cpu0;
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vmsaTblSadd = (uint64_t*)Lvl2VmsaTbl;
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startAddr = Lvl2StartAddr;
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blockShift = Lvl2BlockShift;
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MakeVmsaTable(vmsaTblSadd, vmsaSrcTbl, startAddr, blockShift);
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// VMSA Table Level3 for IPs
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vmsaSrcTbl = (vmsaTable*)ArmVmsaTblLvl3Cpu0;
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vmsaTblSadd = (uint64_t*)Lvl3VmsaTbl;
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startAddr = Lvl3StartAddr;
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blockShift = Lvl3BlockShift;
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MakeVmsaTable(vmsaTblSadd, vmsaSrcTbl, startAddr, blockShift);
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return 0;
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}
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static void MakeVmsaTable(uint64_t *vmsaTblSadd, vmsaTable *vmsaSrcTbl, uint64_t startAddr, uint64_t blockShift)
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{
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uint32_t i,j;
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uint64_t setData;
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uint64_t *setAddr;
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uint64_t upperAttr; // Attribute fields for VMSAv8-64 ([63:52])
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uint64_t lowerAttr; // Attribute fields for VMSAv8-64 ([11:0])
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uint64_t virAdd;
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uint64_t phyAdd;
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uint64_t block;
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uint64_t blockSize;
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blockSize = (1<<blockShift);
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// Level1 : make default table (non-cacheable)
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upperAttr = 0x000; // [63:52] : [52]=Contiguous=1? (T.B.D.)
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lowerAttr = 0x401; // [11:0] : nG=0, AF=1, SH=00, AP=00, NS=0, AttrIndx=000, [1:0]=01
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setAddr = vmsaTblSadd;
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setData = (upperAttr<<52)|(startAddr&BIT47_12)|(lowerAttr);
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for(i=0;i<TBL_NUM;i++){
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*setAddr = setData;
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setAddr++; // Virtual Address (+1GB)(+2MB)
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setData += blockSize; // Physical Address (+1GB)(+2MB)
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}
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// Level1 :
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// Descriptor Address[47:12] = TTBR[47:12]
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// Descriptor Address[11:03] = Input Address[38:30]
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// Descriptor Address[02:00] = 0,0,0
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// ----------
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// Descriptor[47:12] = Physical Address[47:12] or Level2 table address[47:12]
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for(i=0; vmsaSrcTbl[i].unit!=0 ;i++){
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virAdd = vmsaSrcTbl[i].vAddr;
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phyAdd = vmsaSrcTbl[i].pAddr;
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setAddr = (uint64_t*)(uintptr_t)((uintptr_t)vmsaTblSadd + ((virAdd-startAddr)>>(blockShift-3)));
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setData = vmsaSrcTbl[i].upperAttr<<52; // [63:52]
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setData |= phyAdd; // [47:12]
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setData |= vmsaSrcTbl[i].lowerAttr; // [11:00]
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block = vmsaSrcTbl[i].unit;
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for(j=0; j<block; j++){
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*setAddr = setData;
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setAddr++; // Virtual Address (+1GB)(+2MB)
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setData += blockSize; // Physical Address (+1GB)(+2MB)
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}
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}
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}
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