576 lines
21 KiB
C
576 lines
21 KiB
C
/*******************************************************************************
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* DISCLAIMER
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* This software is supplied by Renesas Electronics Corporation and is only
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* intended for use with Renesas products. No other uses are authorized. This
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* software is owned by Renesas Electronics Corporation and is protected under
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* all applicable laws, including copyright laws.
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* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
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* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
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* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
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* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
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* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
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* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
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* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
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* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
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* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
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* Renesas reserves the right, without notice, to make changes to this software
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* and to discontinue the availability of this software. By using this software,
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* you agree to the additional terms and conditions found by accessing the
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* following link:
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* http://www.renesas.com/disclaimer
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* Copyright 2018-2025 Renesas Electronics Corporation All rights reserved.
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*******************************************************************************/
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/*******************************************************************************
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* DESCRIPTION : Loader main function
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******************************************************************************/
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/******************************************************************************
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* @file loader_main.c
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* - Version : 0.17
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* @brief 1. IP initialization.
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* 2. Transfer image.
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* 3. Release of used resources.
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* .
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*****************************************************************************/
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/******************************************************************************
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* History : DD.MM.YYYY Version Description
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* : 30.11.2021 0.01 First Release
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* : 14.02.2022 0.02 Changed log output
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* Added device version log output
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* Removed Include in micro_wait.h
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* Removed the parameter setting process to BL31
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* Removed LCS judgement
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* Memory map change
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* : 17.02.2022 0.03 Support AArch32
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* : 22.03.2022 0.04 Support for GSCE[5.4a, 5.4b],[10.3b]
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* Support for coverity
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* cid:3430806, 3307617, 3430797
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* Changed comment
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* : 10.05.2022 0.05 Integrated processing
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* Changed to processing for each device
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* Change log output
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* Add argument of load_init()
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* : 16.06.2022 0.06 Change log output
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* Support secure boot for S4
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* : 31.10.2022 0.07 License notation change.
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* : 07.11.2022 0.08 Added the parameter setting process to BL31
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* Added DDR initialization/QOS initialization
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* : 07.12.2022 0.09 Warning support when log output is disabled
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* : 15.12.2022 0.10 Support RegionID check
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* : 04.04.2023 0.11 Removed stdio.h.
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* : 21.08.2023 0.12 Add support for V4M.
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* : 23.01.2024 0.13 Add calling of ram_protection_check function.
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* Move calling of final_hash_cmp function.
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* : 10.09.2024 0.14 Updated Region ID and RAM protection setting
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* for QNX.
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* : 11.10.2024 0.15 Updated Region ID and RAM protection setting
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* for QNX for V4M.
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* : 19.12.2024 0.16 Add loading RTOS#1 and RTOS#2 process.
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* Add calling ecm_error_enable() function.
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* : 26.05.2025 0.17 Add argument of OP-TEE boot address to
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* smoni_set_param function.
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*****************************************************************************/
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#include <stdint.h>
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#include <loader_main.h>
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#include <rst_register.h>
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#include <image_load.h>
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#include <ip_control.h>
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#include <rcar_def.h>
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#include <mem_io.h>
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#include <log.h>
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#include <string.h>
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#if ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M))
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#include "cpu_on.h"
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#include "qos.h"
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#include "rtvram.h"
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#include "loader_main_common.h"
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#include "../ip/ddr/boot_init_dram.h"
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#include "access_protection.h"
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#if (ECC_ENABLE == 1)
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#if (RCAR_LSI == RCAR_V4H)
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#include "../ip/ddr/v4h/lpddr5/ecc_enable_v4h.h"
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#elif (RCAR_LSI == RCAR_V4M)
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#include "../ip/ddr/v4m/lpddr5/ecc_enable_v4m.h"
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#endif /* RCAR_LSI == RCAR_V4H */
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#endif /* ECC_ENABLE == 1 */
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#endif /* RCAR_LSI == RCAR_V4H || RCAR_LSI == RCAR_V4M */
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#if (BOOT_MODE == SECURE)
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#include "secure_boot.h"
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#endif /* BOOT_MODE == SECURE */
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/* Time analysis */
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#if (1 == (MEASURE_TIME))
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#include <scmt.h>
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#include <scmt_checkpoint.h>
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#else
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#define scmt_wait_ticks(x)
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#define store_time_checkpoint(x,y)
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#define print_time_checkpoints(x)
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#endif
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#if (ACC_PROT_ENABLE == PROTECTION_ENABLE)
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#include "axmm_register.h"
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#include "ram_protection.h"
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#endif
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#if (ECM_ERROR_ENABLE == 1)
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#if (RCAR_LSI == RCAR_V4H)
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#include "../ip/ddr/v4h/lpddr5/ecm_enable_v4h.h"
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#elif (RCAR_LSI == RCAR_V4M)
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#include "../ip/ddr/v4m/lpddr5/ecm_enable_v4m.h"
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#endif /* RCAR_LSI == RCAR_V4H */
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#endif /* ECM_ERROR_ENABLE == 1 */
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#include <android_ab.h>
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#include <emmc_def.h>
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#include <emmc_boot.h>
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#if (ACC_PROT_ENABLE == PROTECTION_ENABLE)
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#define AXMM_DPTSECCR_NUM (SDRAM_PROTECT_AREA) /* set 0 to 15 */
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#if (OPTEE_LOAD_ENABLE == OPTEE_ENABLE)
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#define AXMM_DPTSECCR_NUM2 (SDRAM_PROTECT_AREA2) /* set 0 to 15 */
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#endif /* OPTEE_LOAD_ENABLE == OPTEE_ENABLE */
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#define AXMM_DPTSECCR_SECGRP_MASK (0x00000F00U)
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#define AXMM_DPTSECCR_SECGRP_SEC (0x00000400U)
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#define AXMM_DPTSECCR_SECGWP_MASK (0x0000000FU)
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#define AXMM_DPTSECCR_SECGWP_SEC (0x00000004U)
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#if ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M))
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#if (OPTEE_LOAD_ENABLE == OPTEE_DISABLE)
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#define DPTRGNCR_PROTECT_AREA (3U)
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#define DPTRGNCR_LINUX_AREA (6U)
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#else
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#define DPTRGNCR_PROTECT_AREA (4U)
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#define DPTRGNCR_LINUX_AREA (9U)
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#endif /* OPTEE_LOAD_ENABLE == OPTEE_DISABLE */
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#define SECCTRWD_AREA0 (0U)
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#define SECCTRWD_AREA2 (2U)
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#define AXMM_DPTRGNCR_RGN0RP_MASK (0x00010000U)
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#define AXMM_DPTRGNCR_RGN0RP (0x00010000U)
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#define AXMM_DPTRGNCR_RGN0WP_MASK (0x00000001U)
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#define AXMM_DPTRGNCR_RGN0WP (0x00000001U)
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#define SECCTRWD_SAFG15WP_MASK (0x00000005U)
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#define SECCTRWD_SAFG15WP (0x00000005U)
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static void remove_rgid0_previlege(void);
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#endif /* ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M)) */
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static void sdram_protection(uint32_t num);
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#endif /* ACC_PROT_ENABLE == PROTECTION_ENABLE */
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uint32_t loader_main(void)
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{
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uint32_t ca_load_num; /* number of load for CA program */
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uint32_t loop;
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uint32_t reg; /* store register value */
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#ifdef MOBIS_PRK3
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int slot = 0;
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#endif
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#if ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M))
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int32_t result; /* store result of ddr_init() */
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#endif /* RCAR_LSI == RCAR_V4H || RCAR_LSI == RCAR_V4M */
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__attribute__((unused))const char *str;
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#if (RCAR_LSI == RCAR_S4)
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const char *product_s4 = "S4";
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#elif (RCAR_LSI == RCAR_V4H)
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const char *product_v4h = "V4H";
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#elif (RCAR_LSI == RCAR_V4M)
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const char *product_v4m = "V4M";
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#endif /* RCAR_LSI == RCAR_S4 */
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const char *unknown = "unknown";
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#if (BOOT_MODE == SECURE)
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uint32_t bootmode; /* store boot mode */
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#endif /* BOOT_MODE == SECURE */
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LOAD_INFO li[MAX_PLACED];
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#if (1 == (MEASURE_TIME))
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scmt_module_start();
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store_time_checkpoint("loader_main", 0);
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#endif
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/*****************************************************************************
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* Initialize Hardware
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*****************************************************************************/
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/* IP initialize */
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ip_init();
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/*****************************************************************************
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* Output boot message
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*****************************************************************************/
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#if (RCAR_LSI == RCAR_S4)
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NOTICE("CA55 Loader Program Rev.%s\n", IPL_VERSION);
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#elif ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M))
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NOTICE("CR52 Loader Program Rev.%s\n", IPL_VERSION);
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#endif /* RCAR_LSI == RCAR_S4 */
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NOTICE("%s\n", build_message);
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/* Get PRR */
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reg = mem_read32(PRR);
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switch (reg & PRR_PRODUCT_MASK)
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{
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#if (RCAR_LSI == RCAR_S4)
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case PRR_PRODUCT_S4:
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{
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str = product_s4;
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break;
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}
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#elif (RCAR_LSI == RCAR_V4H)
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case PRR_PRODUCT_V4H:
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{
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str = product_v4h;
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break;
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}
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#elif (RCAR_LSI == RCAR_V4M)
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case PRR_PRODUCT_V4M:
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{
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str = product_v4m;
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break;
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}
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#endif /* RCAR_LSI == RCAR_S4 */
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default:
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{
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str = unknown;
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break;
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}
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}
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NOTICE("PRR is R-Car %s Ver.%d.%d\n", str,
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((int)(reg & PRR_MAJOR_MASK) >> PRR_MAJOR_SHIFT)
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+ PRR_MAJOR_OFFSET, (int)(reg & PRR_MINOR_MASK));
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#if ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M))
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#if (ACC_PROT_ENABLE == PROTECTION_ENABLE)
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/* Notice the ecc enable */
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NOTICE("Access Protection Enable\n");
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#endif /* ACC_PROT_ENABLE == PROTECTION_ENABLE */
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#endif /* RCAR_LSI == RCAR_V4H || RCAR_LSI == RCAR_V4M */
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store_time_checkpoint("init_done", 0);
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/*****************************************************************************
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* DDR Initialization
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*****************************************************************************/
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#if ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M))
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/* DDR initialize */
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result = R_DRAM_Init();
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if (INITDRAM_OK != result)
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{
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ERROR("Failed to DRAM initialize (%d).\n", (int)result);
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panic;
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}
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#if (ECM_ERROR_ENABLE == 1)
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ecm_error_enable();
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#endif /* ECM_ERROR_ENABLE == 1 */
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#if (ECC_ENABLE == 1)
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/* ECC Protection */
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ecc_sdram_enable();
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#endif /* ECC_ENABLE == 1 */
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/* QoS configuration */
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qos_init();
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/* RT-VRAM Extend mode */
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rtvram_extendmode();
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/* memory copy */
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memcpy((void *)DISK_BUFFER_ADDR, (void *)DISK_BUFFER__IPL, 4096);
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memset((void *)DISK_BUFFER__IPL, 0xFF, 4096);
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memcpy((void *)AB_INFO_FLAG_ADDR, (void *)AB_INFO_FLAG__IPL, 4);
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memset((void *)AB_INFO_FLAG__IPL, 0xFF, 4);
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#endif /* RCAR_LSI == RCAR_V4H || RCAR_LSI == RCAR_V4M */
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store_time_checkpoint("DDR_and_Bus_init_done", 0);
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/*****************************************************************************
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* Load Certficate
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*****************************************************************************/
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/* Load content certificate */
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ca_load_num = mem_read32(CONTENT_CERT_DEST_ADDR);
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/* Get load information */
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load_init(li, ca_load_num);
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#if (BOOT_MODE == SECURE)
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/*****************************************************************************
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* Check SecureBoot
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*****************************************************************************/
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secureboot_init();
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/* LCS judgement for secure boot */
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bootmode = judge_bootmode();
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if (NORMAL_BOOT != bootmode)
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{
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/* Content cert certification */
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#if (BL2_LOAD_ENABLE == BL2_DISABLE)
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secureboot_verify(li, CA_OPTIONAL_ID, CA_OPTIONAL_ID + ca_load_num);
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#else
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secureboot_verify(li, CA_BL2_ID, CA_BL2_ID + 1);
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#endif
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store_time_checkpoint("verify_cert_done", 0);
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}
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#endif /* BOOT_MODE == SECURE */
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#if (RTOS_LOAD_NUM == RTOS_LOAD_NUM_3)
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/*****************************************************************************
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* Load RTOS#2
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*****************************************************************************/
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/* Start loading RTOS#2 image */
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load_image(&li[RTOS2_ID]);
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store_time_checkpoint("load_RTOS#2_done", li[RTOS2_ID].image_size);
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#if (BOOT_MODE == SECURE)
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/* Decryption image and Image cerfification */
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if (NORMAL_BOOT != bootmode)
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{
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secureboot_image(&li[RTOS2_ID], 1);
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store_time_checkpoint("verify_RTOS#2_done", 0);
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}
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#endif /* BOOT_MODE == SECURE */
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/* boot CR core2 */
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arm_cpu_on(RCAR_PWR_TARGET_CR, li[RTOS2_ID].boot_addr, 2);
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store_time_checkpoint("started_RTOS#2", 0);
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#endif /* RTOS_LOAD_NUM == RTOS_LOAD_NUM_3 */
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#if ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M))
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/*****************************************************************************
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* Load RTOS#0
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*****************************************************************************/
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#define _IPL_END (0xEB22FFF4)
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#ifdef MOBIS_PRK3
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emmc_initialize();
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store_time_checkpoint("emmc_initialize", 0);
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#if (BL2_LOAD_ENABLE == BL2_ENABLE) /* do not clear eMMC */
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export_mmc_drv_obj();
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#endif
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reg = mem_read32(AB_INFO_FLAG_ADDR);
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if (reg & AB_INFO_SELECT_2nd)
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slot = 1;
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// slot = ab_select_slot();
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load_update_part_num(li, ca_load_num, slot);
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NOTICE("slot: %d\n", slot);
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mem_write32(_IPL_END, 0x0);
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#endif
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/* Start loading RTOS#0 image */
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load_image(&li[RTOS_ID]);
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store_time_checkpoint("load_RTOS#0_done", li[RTOS_ID].image_size);
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#if (BOOT_MODE == SECURE)
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/* Decryption image and Image cerfification */
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if (NORMAL_BOOT != bootmode)
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{
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/* WARNING! WARNING! WARNING! WARNING! */
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/* TODO: set 1 to panic! later */
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secureboot_image(&li[RTOS_ID], 0);
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store_time_checkpoint("verify_RTOS#0_done", 0);
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}
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#endif /* BOOT_MODE == SECURE */
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/* boot CR core0 */
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arm_cpu_on(RCAR_PWR_TARGET_CR, li[RTOS_ID].boot_addr, -1);
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#ifdef MOBIS_PRK3
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/* enable CR-52 Core 2 */
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arm_cpu_on(RCAR_PWR_TARGET_CR, li[RTOS_ID].boot_addr, 2);
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store_time_checkpoint("started_RTOS#0", 0);
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#endif
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#if (BOOT_TIME_CHECK != 0)
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gpio_N1305(2);
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#endif
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#endif /* RCAR_LSI == RCAR_V4H || RCAR_LSI == RCAR_V4M */
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/*****************************************************************************
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* Load CA Program#2--#8
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*****************************************************************************/
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#if (BL2_LOAD_ENABLE == BL2_DISABLE)
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/* Start loading CA Program#n image */
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for (loop = 0U; loop < ca_load_num; loop++)
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#else
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/* load bl2 */
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loop = (CA_BL2_ID - CA_OPTIONAL_ID);
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#endif
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{
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/* Loading start */
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NOTICE("Loading %s...\n", li[CA_OPTIONAL_ID + loop].name);
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load_image(&li[CA_OPTIONAL_ID + loop]);
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store_time_checkpoint("load_CA_#_done", li[CA_OPTIONAL_ID + loop].image_size);
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#if (BOOT_MODE == SECURE)
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/* Decryption image and Image certification */
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if (NORMAL_BOOT != bootmode)
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{
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secureboot_image(&li[CA_OPTIONAL_ID + loop], 1);
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store_time_checkpoint("verify_CA_#_done", 0);
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}
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#endif /* BOOT_MODE == SECURE */
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}
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#if ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M))
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/* Set Secure Monitor parameter */
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#if (OPTEE_LOAD_ENABLE == OPTEE_DISABLE)
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smoni_set_param(li[CA_OPTIONAL_ID].boot_addr, /* BL31 */
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li[CA_OPTIONAL_ID + 1U].boot_addr); /* U-Boot */
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#else
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#if (BL2_LOAD_ENABLE == BL2_DISABLE) /* BL2 will load these */
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smoni_set_param(li[CA_OPTIONAL_ID].boot_addr, /* BL31 */
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li[CA_OPTIONAL_ID + 1U].boot_addr, /* U-Boot */
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li[CA_OPTIONAL_ID + 2U].boot_addr); /* OP-TEE */
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#endif
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#endif /* OPTEE_LOAD_ENABLE == OPTEE_DISABLE */
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/* Before Boot CPU, Set the division ratio for CPU operating frequency */
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adj_ca_variant_freq();
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/* boot CA */
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#if (BL2_LOAD_ENABLE == BL2_DISABLE)
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arm_cpu_on(RCAR_PWR_TARGET_CA, li[CA_OPTIONAL_ID].boot_addr, -1);
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#else /* run BL2, not BL31 */
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arm_cpu_on(RCAR_PWR_TARGET_CA, li[CA_BL2_ID].boot_addr, -1);
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#endif
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store_time_checkpoint("started_CA_core", 0);
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#if (RTOS_LOAD_NUM == RTOS_LOAD_NUM_3)
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/*****************************************************************************
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* Load RTOS#1
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*****************************************************************************/
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|
/* Start loading RTOS#1 image */
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|
load_image(&li[RTOS1_ID]);
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|
store_time_checkpoint("load_RTOS#1_done", li[RTOS1_ID].image_size);
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|
|
|
#if (BOOT_MODE == SECURE)
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|
/* Decryption image and Image cerfification */
|
|
if (NORMAL_BOOT != bootmode)
|
|
{
|
|
secureboot_image(&li[RTOS1_ID], 1);
|
|
store_time_checkpoint("verify_RTOS#1_done", 0);
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|
}
|
|
#endif /* BOOT_MODE == SECURE */
|
|
|
|
#endif /* RTOS_LOAD_NUM == RTOS_LOAD_NUM_3 */
|
|
|
|
#if (ACC_PROT_ENABLE == PROTECTION_ENABLE)
|
|
sdram_protection(AXMM_DPTSECCR_NUM);
|
|
#if (OPTEE_LOAD_ENABLE == OPTEE_ENABLE)
|
|
sdram_protection(AXMM_DPTSECCR_NUM2);
|
|
#endif /* OPTEE_LOAD_ENABLE == OPTEE_ENABLE */
|
|
remove_rgid0_previlege();
|
|
/*
|
|
* SAN(Safety Application Note) 6.23.5 Operation
|
|
* Checker processor :
|
|
* Check RegionID/LifeC & memory area protection settings (including order & content of intermediate updates)
|
|
* done by ICUMX.
|
|
*/
|
|
rgid_protection_check();
|
|
ram_protection_check();
|
|
#endif /* ACC_PROT_ENABLE == PROTECTION_ENABLE */
|
|
|
|
#if (BOOT_MODE == SECURE)
|
|
if (NORMAL_BOOT != bootmode)
|
|
{
|
|
/* Compare Hash verified at ICUMX IPL (V4H only). (Target images are Secure FW and Cx 2nd IPL.) */
|
|
/*
|
|
* SAN(Safety Application Note) 6.23.5 Operation
|
|
* Checker processor :
|
|
* Re-do comparison of hash in Flash vs hash generated by ICUMX to confirm proper comparison.
|
|
*/
|
|
final_hash_cmp();
|
|
store_time_checkpoint("final_verify_done", 0);
|
|
}
|
|
#endif /* BOOT_MODE == SECURE */
|
|
|
|
NOTICE("Load finish.(CR52 Loader)\n");
|
|
|
|
#elif (RCAR_LSI == RCAR_S4)
|
|
#if (ACC_PROT_ENABLE == PROTECTION_ENABLE)
|
|
sdram_protection(AXMM_DPTSECCR_NUM);
|
|
#endif /* ACC_PROT_ENABLE == PROTECTION_ENABLE */
|
|
NOTICE("Load finish.(CA55 Loader)\n");
|
|
#endif /* RCAR_LSI == RCAR_V4H || RCAR_LSI == RCAR_V4M */
|
|
// ip_release();
|
|
|
|
store_time_checkpoint("Cx_done_starting_RTOS#1", 0);
|
|
// scmt_wait_ticks(SCMT_MS2TICKS(1000));
|
|
print_time_checkpoints();
|
|
#if (BOOT_TIME_CHECK != 0)
|
|
gpio_N1305(2);
|
|
#endif
|
|
|
|
#if (RTOS_LOAD_NUM == RTOS_LOAD_NUM_1)
|
|
#ifdef MOBIS_PRK3
|
|
return li[RTOS_ID].boot_addr;
|
|
#else
|
|
return li[CA_OPTIONAL_ID].boot_addr;
|
|
#endif
|
|
#elif (RTOS_LOAD_NUM == RTOS_LOAD_NUM_3)
|
|
return li[RTOS1_ID].boot_addr;
|
|
#endif /* RTOS_LOAD_NUM == RTOS_LOAD_NUM_3 */
|
|
}
|
|
/* End of function loader_main(void) */
|
|
|
|
|
|
#if (ACC_PROT_ENABLE == PROTECTION_ENABLE)
|
|
static void sdram_protection(uint32_t num)
|
|
{
|
|
uint32_t val;
|
|
uint32_t addr;
|
|
|
|
/* Calculation of the address of the DPTSECCR register. */
|
|
addr = (AXMM_DPTSECCR + (num * 4U));
|
|
|
|
val = mem_read32(addr);
|
|
val &= ~(AXMM_DPTSECCR_SECGRP_MASK | AXMM_DPTSECCR_SECGWP_MASK);
|
|
val |= (AXMM_DPTSECCR_SECGRP_SEC | AXMM_DPTSECCR_SECGWP_SEC);
|
|
mem_write32(addr, val);
|
|
}/* End of function void sdram_protection(void) */
|
|
|
|
#if ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M))
|
|
static void remove_rgid0_previlege(void)
|
|
{
|
|
uint32_t val;
|
|
uint32_t addr;
|
|
|
|
/* Calculation of the address of the DPTRGNCR register. */
|
|
addr = get_dptrgncr_addr(DPTRGNCR_PROTECT_AREA);
|
|
|
|
val = mem_read32(addr);
|
|
val &= ~(AXMM_DPTRGNCR_RGN0RP_MASK | AXMM_DPTRGNCR_RGN0WP_MASK);
|
|
val |= (AXMM_DPTRGNCR_RGN0RP| AXMM_DPTRGNCR_RGN0WP); /* Remove RGID0 read/write previlege on SDRAM Area. */
|
|
mem_write32(addr, val);
|
|
|
|
/* Calculation of the address of the DPTRGNCR register. */
|
|
addr = get_dptrgncr_addr(DPTRGNCR_LINUX_AREA);
|
|
|
|
val = mem_read32(addr);
|
|
val &= ~(AXMM_DPTRGNCR_RGN0RP_MASK | AXMM_DPTRGNCR_RGN0WP_MASK);
|
|
val |= (AXMM_DPTRGNCR_RGN0RP| AXMM_DPTRGNCR_RGN0WP); /* Remove RGID0 read/write previlege on SDRAM Area. */
|
|
mem_write32(addr, val);
|
|
|
|
/* Calculation of the address of the SECCTRW0D_1 register. */
|
|
addr = get_rtvram1_secctrwd_addr(SECCTRWD_AREA0);
|
|
|
|
val = mem_read32(addr);
|
|
val &= ~(SECCTRWD_SAFG15WP_MASK);
|
|
val |= SECCTRWD_SAFG15WP; /* Remove RGID0/2 write previlege on RT-VRAM1 Area0. */
|
|
mem_write32(addr, val);
|
|
|
|
/* Calculation of the address of the SECCTRW2D_1 register. */
|
|
addr = get_rtvram1_secctrwd_addr(SECCTRWD_AREA2);
|
|
|
|
val = mem_read32(addr);
|
|
val &= ~(SECCTRWD_SAFG15WP_MASK);
|
|
val |= SECCTRWD_SAFG15WP; /* Remove RGID0/2 write previlege on RT-VRAM1 Area2. */
|
|
mem_write32(addr, val);
|
|
}
|
|
/* End of function void remove_rgid0_previlege(void) */
|
|
#endif /* ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M)) */
|
|
|
|
#endif /* ACC_PROT_ENABLE == PROTECTION_ENABLE */
|