103 lines
3.6 KiB
C
103 lines
3.6 KiB
C
/*******************************************************************************
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* DESCRIPTION : GPIO Control function
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******************************************************************************/
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/******************************************************************************
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* @file gpio.c
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* - Version : 0.01
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* @brief
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* .
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*****************************************************************************/
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/******************************************************************************
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* History : DD.MM.YYYY Version Description
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* : 18.11.2024 0.01 First Release
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*****************************************************************************/
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#if defined(__CX_IPL__) /* V4H_Cx_Loader */
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#include "mem_io.h"
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#include "rcar_def.h"
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#include "rcar_register.h"
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#include "gic.h"
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#include "ip_control.h"
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#include "timer.h"
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#define GP0_8_BASE (BASE_PFC0_ADDR + 0x0180U)
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#define GP1_24_BASE (PFC_GP1_BASE + 0x0180U)
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#else /* Gen4_ICUMX_Loader */
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#include <stdint.h>
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#include <types.h>
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#include <cpg.h>
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#include <pfc.h>
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#include <mem_io.h>
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#include <micro_wait.h>
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#include <rst_register.h>
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#define GPIO_BASE (PFC_BASE + PFC_PORT_GRP0)
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#define GP0_8_BASE (PFC_BASE + PFC_PORT_GRP0 + 0x0180)
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#define GP1_24_BASE (PFC_BASE + PFC_PORT_GRP1 + 0x0180)
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#endif
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#define GP1_23_BASE GP1_24_BASE
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#define GPIO_IOINTSEL 0x00 /* General IO/Interrupt Switching Register */
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#define GPIO_INOUTSEL 0x04 /* General Input/Output Switching Register */
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#define GPIO_OUTDT 0x08 /* General Output Register */
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#define GPIO_INDT 0x0c /* General Input Register */
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#define GPIO_INTDT 0x10 /* Interrupt Display Register */
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#define GPIO_INTCLR 0x14 /* Interrupt Clear Register */
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#define GPIO_INTMSK 0x18 /* Interrupt Mask Register */
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#define GPIO_MSKCLR 0x1c /* Interrupt Mask Clear Register */
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#define GPIO_POSNEG 0x20 /* Positive/Negative Logic Select Register */
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#define GPIO_EDGLEVEL 0x24 /* Edge/level Select Register */
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#define GPIO_FILONOFF 0x28 /* Chattering Prevention On/Off Register */
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#define GPIO_BOTHEDGE 0x4c /* One Edge/Both Edge Select Register */
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#define GPIO_INEN 0x50 /* General Input Enable Register */
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#define BIT(nr) (1 << (nr))
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void gpio_output_clr_set(uintptr_t regs, int offset, int set)
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{
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if (set)
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mem_bitclrset32(regs + GPIO_OUTDT, 0x0, BIT(offset)); /* set */
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else
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mem_bitclrset32(regs + GPIO_OUTDT, BIT(offset), 0x0); /* clear */
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mem_bitclrset32(regs + GPIO_POSNEG, BIT(offset), 0x0);
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mem_bitclrset32(regs + GPIO_INEN, BIT(offset), 0x0);
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mem_bitclrset32(regs + GPIO_IOINTSEL, BIT(offset), 0x0);
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mem_bitclrset32(regs + GPIO_INOUTSEL, 0x0, BIT(offset)); /* set output */
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}
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/* End of function gpio_output_clr_set(uintptr_t regs, int offset, int set) */
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#if (BOOT_TIME_CHECK != 0)
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void gpio_N1307(int set) {
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if (set == 2) {
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gpio_output_clr_set(GP0_8_BASE, 8, 0);
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gpio_output_clr_set(GP0_8_BASE, 8, 1);
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micro_wait(10U);
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gpio_output_clr_set(GP0_8_BASE, 8, 0);
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} else if (set)
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gpio_output_clr_set(GP0_8_BASE, 8, 1);
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else
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gpio_output_clr_set(GP0_8_BASE, 8, 0);
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}
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void gpio_N1305(int set) {
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if (set == 2) {
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gpio_output_clr_set(GP1_24_BASE, 24, 0);
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micro_wait(10U);
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gpio_output_clr_set(GP1_24_BASE, 24, 1);
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micro_wait(10U);
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// gpio_output_clr_set(GP1_24_BASE, 24, 0);
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} else if (set)
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gpio_output_clr_set(GP1_24_BASE, 24, 1);
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else
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gpio_output_clr_set(GP1_24_BASE, 24, 0);
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}
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#endif
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void gpio_V4H_SERDES_1V8_en(int set) {
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if (set) {
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gpio_output_clr_set(GP1_23_BASE, 23, 1);
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} else {
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gpio_output_clr_set(GP1_23_BASE, 23, 0);
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}
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}
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