166 lines
2.7 KiB
ArmAsm
166 lines
2.7 KiB
ArmAsm
/*
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* Copyright (c) 2018 Renesas Electronics Corporation. All rights reserved.
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*/
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;# W0-W30 : 32bit Register (W30=Link Register)
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;# X0-X30 : 64bit Register (X30=Link Register)
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;# WZR : 32bit Zero Register
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;# XZR : 64bit Zero Register
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;# WSP : 32bit Stack Pointer
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;# SP : 64bit Stack Pointer
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.INCLUDE "boot_mon.h"
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.ALIGN 4
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;# Initialize registers
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Register_init:
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LDR X0, =0
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LDR X1, =0
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LDR X2, =0
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LDR X3, =0
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LDR X4, =0
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LDR X5, =0
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LDR X6, =0
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LDR X7, =0
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LDR X8, =0
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LDR X9, =0
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LDR X10, =0
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LDR X11, =0
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LDR X12, =0
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LDR X13, =0
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LDR X14, =0
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LDR X15, =0
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LDR X16, =0
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LDR X17, =0
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LDR X18, =0
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LDR X19, =0
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LDR X20, =0
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LDR X21, =0
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LDR X22, =0
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LDR X23, =0
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LDR X24, =0
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LDR X25, =0
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LDR X26, =0
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LDR X27, =0
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LDR X28, =0
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LDR X29, =0
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LDR X30, =0
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Set_EnableRAM:
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;# LDR X0, =0xE67F0018
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;# LDR W1, =0x00000001 ;#Enable DRAM/SECRAM/PUBRAM
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;# STR W1, [X0]
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MRS X0, CurrentEL
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CMP X0, #0x0000000C
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BEQ current_EL3
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current_EL1:
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;# Loader
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LDR x0, =__STACKS_END__
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;# MSR SP_EL0,x0
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;# MSR SP_EL1,x0
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;# MSR SP_EL2,x0
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MOV sp,x0
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MOV x0, #0x50000000
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MSR ELR_EL1,x0
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;# MSR ELR_EL2,x0
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;# MSR ELR_EL3,x0
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MOV x0, #0x03C5
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MSR SPSR_EL1,x0
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;# MSR SPSR_EL2,x0
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;# MSR SPSR_EL3,x0
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;# Enable cache
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;# mov x1, #(SCTLR_I_BIT | SCTLR_A_BIT | SCTLR_SA_BIT)
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mrs x0, sctlr_el1
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orr x0, x0, #(0x1 << 12)
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orr x0, x0, #(0x1 << 1)
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orr x0, x0, #(0x1 << 3)
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msr sctlr_el1, x0
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isb
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b bss_clr
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current_EL3:
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;# Loader
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LDR x0, =__STACKS_END__
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;# MSR SP_EL0,x0
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;# MSR SP_EL1,x0
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;# MSR SP_EL2,x0
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MOV sp,x0
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MOV x0, #0xE38
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MSR SCR_EL3, x0
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MOV x0, #0x44100000
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;# MSR ELR_EL1,x0
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;# MSR ELR_EL2,x0
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MSR ELR_EL3,x0
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MOV x0, #0x03C5
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;# MSR SPSR_EL1,x0
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;# MSR SPSR_EL2,x0
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MSR SPSR_EL3,x0
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;# Board Initialize
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.ifdef Area0Boot
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Init_set_WDT:
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LDR W0, =RWDT_RWTCSRA
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LDR W1, =0xA5A5A500 ;#Timer disabled
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STR W1, [X0]
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Init_set_SYSWDT:
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LDR W0, =SYSWDT_WTCSRA
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LDR W1, =0xA5A5A500 ;#Timer disabled (Enable -> disabled)
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STR W1, [X0]
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.endif
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;# Enable cache
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;# mov x1, #(SCTLR_I_BIT | SCTLR_A_BIT | SCTLR_SA_BIT)
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mrs x0, sctlr_el3
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orr x0, x0, #(0x1 << 12)
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orr x0, x0, #(0x1 << 1)
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orr x0, x0, #(0x1 << 3)
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msr sctlr_el3, x0
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isb
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/* clear bss section */
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bss_clr:
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mov X0, #0x0
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ldr X1, =__BSS_START__
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ldr X2, =__BSS_SIZE__
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bss_loop:
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subs X2, X2, #4
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bcc bss_end
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str W0, [X1, X2]
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b bss_loop
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bss_end:
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.ifdef Area0Boot
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/* copy data section */
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ldr X0, =__DATA_COPY_START__
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ldr X1, =__DATA_START__
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ldr X2, =__DATA_SIZE__
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data_loop:
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subs X2, X2, #4
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bcc data_end
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ldr W3, [X0, X2]
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str W3, [X1, X2]
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b data_loop
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.endif
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data_end:
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;# BL InitScif
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BL Main
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mov X1, #0x50000000
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BR X1
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.END
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