229 lines
9.6 KiB
C
229 lines
9.6 KiB
C
/*******************************************************************************
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* DISCLAIMER
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* This software is supplied by Renesas Electronics Corporation and is only
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* intended for use with Renesas products. No other uses are authorized. This
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* software is owned by Renesas Electronics Corporation and is protected under
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* all applicable laws, including copyright laws.
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* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
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* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
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* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
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* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
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* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
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* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
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* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
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* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
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* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
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* Renesas reserves the right, without notice, to make changes to this software
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* and to discontinue the availability of this software. By using this software,
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* you agree to the additional terms and conditions found by accessing the
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* following link:
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* http://www.renesas.com/disclaimer
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* Copyright 2023 Renesas Electronics Corporation All rights reserved.
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*******************************************************************************/
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/*******************************************************************************
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* DESCRIPTION : Control ECC and Address parity check for CodeSRAM
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******************************************************************************/
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/******************************************************************************
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* @file codesram_ecc.c
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* - Version : 0.01
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* @brief 1. Enable / Disable ECC and Address parity check for CodeSRAM.
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* .
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*****************************************************************************/
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/******************************************************************************
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* History : DD.MM.YYYY Version Description
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* : 19.01.2023 0.01 First Release
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*****************************************************************************/
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#include <stdint.h>
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#include <codesram_ecc.h>
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#include <mem_io.h>
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#include <log.h>
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#include <mcu_register.h>
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#include <cpu_on_for_mcu.h>
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#define CSRM_ECCCTL_EMCA_EN_MOD (0x00004000U)
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#define CSRM_ECCCTL_APERR (0x00001000U)
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#define CSRM_ECCCTL_ECERVF (0x00000040U)
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#define CSRM_ECCCTL_EC1ECP (0x00000020U)
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#define CSRM_ECCCTL_ECER2F (0x00000004U)
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#define CSRM_ECCCTL_ECER1F (0x00000002U)
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#define CSRM_APCTL_APCEN (0x00000001U)
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#define CSRM_NO_ERROR (0x00000000U)
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#define CODESRAM_BUS_NUM_SHIFT (20U)
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void disable_codesram_ecc_parity(uint32_t boot_addr, uint32_t size)
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{
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uint32_t loop;
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uint32_t bus_num;
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uint32_t set_num;
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uint32_t reg;
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/* Code-SRAMn ECC Control Register */
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const uint32_t eccctl_reg[MCU_CSRM_MAX] = { MCU_CSRM0ECCCTL,
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MCU_CSRM1ECCCTL,
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MCU_CSRM2ECCCTL,
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MCU_CSRM3ECCCTL,
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MCU_CSRM4ECCCTL,
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MCU_CSRM5ECCCTL};
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/* Code-SRAMn Address Parity Control Register */
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const uint32_t apctl_reg[MCU_CSRM_MAX] = { MCU_CSRM0APCTL,
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MCU_CSRM1APCTL,
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MCU_CSRM2APCTL,
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MCU_CSRM3APCTL,
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MCU_CSRM4APCTL,
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MCU_CSRM5APCTL};
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/* Calculate the area used by Code SRAM. */
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bus_num = ((boot_addr & CODESRAM_BUS_NUM_MASK) >> CODESRAM_BUS_NUM_SHIFT);
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set_num = ((size & CODESRAM_BUS_NUM_MASK) >> CODESRAM_BUS_NUM_SHIFT);
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for (loop = 0U; loop < set_num; loop++)
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{
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/* Disable ECC error detection and error correction for CodeSRAM. */
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reg = mem_read32(eccctl_reg[bus_num + loop]);
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reg &= ~(CSRM_ECCCTL_ECERVF);
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reg |= CSRM_ECCCTL_EMCA_EN_MOD;
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reg |= CSRM_ECCCTL_EC1ECP;
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mem_write32(eccctl_reg[bus_num + loop], reg);
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/* Disable Address parity check for CodeSRAM. */
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reg = mem_read32(apctl_reg[bus_num + loop]);
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reg &= ~(CSRM_APCTL_APCEN);
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mem_write32(apctl_reg[bus_num + loop], reg);
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}
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}
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/* End of function disable_codesram_ecc_parity */
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void enable_codesram_ecc_parity(uint32_t boot_addr, uint32_t size)
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{
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uint32_t loop;
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uint32_t bus_num;
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uint32_t set_num;
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uint32_t reg;
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/* Code-SRAMn ECC Control Register */
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const uint32_t eccctl_reg[MCU_CSRM_MAX] = { MCU_CSRM0ECCCTL,
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MCU_CSRM1ECCCTL,
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MCU_CSRM2ECCCTL,
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MCU_CSRM3ECCCTL,
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MCU_CSRM4ECCCTL,
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MCU_CSRM5ECCCTL};
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/* Code-SRAMn Address Parity Control Register */
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const uint32_t apctl_reg[MCU_CSRM_MAX] = { MCU_CSRM0APCTL,
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MCU_CSRM1APCTL,
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MCU_CSRM2APCTL,
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MCU_CSRM3APCTL,
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MCU_CSRM4APCTL,
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MCU_CSRM5APCTL};
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/* Calculate the area used by Code SRAM. */
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bus_num = ((boot_addr & CODESRAM_BUS_NUM_MASK) >> CODESRAM_BUS_NUM_SHIFT);
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set_num = ((size & CODESRAM_BUS_NUM_MASK) >> CODESRAM_BUS_NUM_SHIFT);
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for (loop = 0U; loop < set_num; loop++)
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{
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/* Enable ECC error detection and error correction for CodeSRAM. */
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reg = mem_read32(eccctl_reg[bus_num + loop]);
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reg &= ~(CSRM_ECCCTL_EC1ECP);
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reg |= CSRM_ECCCTL_ECERVF;
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reg |= CSRM_ECCCTL_EMCA_EN_MOD;
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mem_write32(eccctl_reg[bus_num + loop], reg);
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/* Enable Address parity check for CodeSRAM. */
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reg = mem_read32(apctl_reg[bus_num + loop]);
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reg |= CSRM_APCTL_APCEN;
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mem_write32(apctl_reg[bus_num + loop], reg);
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}
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}
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/* End of function enable_codesram_ecc_parity */
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void chk_codesram_ecc_parity(uint32_t boot_addr, uint32_t size)
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{
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uint32_t loop;
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uint32_t bus_num;
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uint32_t set_num;
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uint32_t reg;
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uint32_t err_chk;
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/* Code-SRAMn ECC Control Register */
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const uint32_t eccctl_reg[MCU_CSRM_MAX] = { MCU_CSRM0ECCCTL,
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MCU_CSRM1ECCCTL,
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MCU_CSRM2ECCCTL,
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MCU_CSRM3ECCCTL,
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MCU_CSRM4ECCCTL,
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MCU_CSRM5ECCCTL};
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/* Calculate the area used by Code SRAM. */
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bus_num = ((boot_addr & CODESRAM_BUS_NUM_MASK) >> CODESRAM_BUS_NUM_SHIFT);
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set_num = ((size & CODESRAM_BUS_NUM_MASK) >> CODESRAM_BUS_NUM_SHIFT);
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/* Check ECC error and Address parity error for CodeSRAM. */
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for (loop = 0U; loop < set_num; loop++)
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{
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reg = mem_read32(eccctl_reg[bus_num + loop]);
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err_chk = reg;
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err_chk &= (CSRM_ECCCTL_ECER2F | CSRM_ECCCTL_ECER1F);
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if(err_chk != CSRM_NO_ERROR)
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{
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/* ECC error occurred. */
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ERROR("CodeSRAM ECC error detected !!\n");
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panic;
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}
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err_chk = reg;
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err_chk &= CSRM_ECCCTL_APERR;
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if(err_chk != CSRM_NO_ERROR)
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{
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/* Address parity error occurred. */
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ERROR("CodeSRAM Address parity error detected !!\n");
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panic;
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}
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}
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}
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/* End of function chk_codesram_ecc_parity */
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void initialize_codesram_ecc_parity(uint32_t boot_addr, uint32_t size)
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{
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uint32_t loop;
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uint32_t bus_num;
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uint32_t set_num;
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uint32_t reg;
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/* Code-SRAMn ECC Control Register */
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const uint32_t eccctl_reg[MCU_CSRM_MAX] = { MCU_CSRM0ECCCTL,
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MCU_CSRM1ECCCTL,
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MCU_CSRM2ECCCTL,
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MCU_CSRM3ECCCTL,
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MCU_CSRM4ECCCTL,
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MCU_CSRM5ECCCTL};
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/* Code-SRAMn Address Parity Control Register */
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const uint32_t apctl_reg[MCU_CSRM_MAX] = { MCU_CSRM0APCTL,
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MCU_CSRM1APCTL,
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MCU_CSRM2APCTL,
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MCU_CSRM3APCTL,
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MCU_CSRM4APCTL,
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MCU_CSRM5APCTL};
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/* Calculate the area used by Code SRAM. */
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bus_num = ((boot_addr & CODESRAM_BUS_NUM_MASK) >> CODESRAM_BUS_NUM_SHIFT);
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set_num = ((size & CODESRAM_BUS_NUM_MASK) >> CODESRAM_BUS_NUM_SHIFT);
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for (loop = 0U; loop < set_num; loop++)
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{
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/* Initialize ECC error detection and error correction setting for CodeSRAM. */
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reg = mem_read32(eccctl_reg[bus_num + loop]);
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reg &= ~(CSRM_ECCCTL_EC1ECP | CSRM_ECCCTL_ECERVF);
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reg |= CSRM_ECCCTL_EMCA_EN_MOD;
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mem_write32(eccctl_reg[bus_num + loop], reg);
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/* Initialize Address parity check setting for CodeSRAM. */
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reg = mem_read32(apctl_reg[bus_num + loop]);
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reg |= CSRM_APCTL_APCEN;
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mem_write32(apctl_reg[bus_num + loop], reg);
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}
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}
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/* End of function initialize_codesram_ecc_parity */
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