Tool/IPL/Customer/Mobis/Gen4_ICUMX_Loader/loader/loader.S

/*******************************************************************************
 * DISCLAIMER
 * This software is supplied by Renesas Electronics Corporation and is only
 * intended for use with Renesas products. No other uses are authorized. This
 * software is owned by Renesas Electronics Corporation and is protected under
 * all applicable laws, including copyright laws.
 * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
 * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
 * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
 * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
 * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
 * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
 * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
 * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
 * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
 * Renesas reserves the right, without notice, to make changes to this software
 * and to discontinue the availability of this software. By using this software,
 * you agree to the additional terms and conditions found by accessing the
 * following link:
 * http://www.renesas.com/disclaimer
 * Copyright 2021-2023 Renesas Electronics Corporation All rights reserved.
 *******************************************************************************/

/*******************************************************************************
 * DESCRIPTION   : Loader start code
 ******************************************************************************/

    .global code_start
    .global _loader_main
    .global ___ghsend_RT_stack  /* RT-SRAM stack Logical end address    */
    .global ___ghs_set_stack_chk_guard

    BOOTROM_CODE_START_ADDRESS          .set    0x01104000  /* Boot ROM start address */
    BOOTROM_CODE_END_ADDRESS            .set    0x0112CFFC  /* Boot ROM end address */
    SICREMAP_WINDOW_AREA_START_ADDRESS  .set    0xFC000000  /* Remap 0 start address */
    SICREMAP_WINDOW_AREA_END_ADDRESS    .set    0xFEBFFFFC  /* SIC area end address */
    ICU_REGISTER_AREA_START_ADDRESS     .set    0xFEDE0000  /* ICUMXB register area start address */
    ICU_REGISTER_AREA_END_ADDRESS       .set    0xFFFEFFFC  /* ICUMXB register area end address */

    MPAT_SX_SR_ENABLE                   .set    0x000000E8  /* SV mode Read/Execution enable */
    MPAT_SW_SR_ENABLE                   .set    0x000000D8  /* SV mode Read/Writer enable */
    MPRC_E3_TO_E0_ENABLE                .set    0x0000000F  /* E0,E1,E2,E3 enable */
    MPM_SVP_MPE_ENABLE                  .set    0x00000003  /* SV mode protect enable, MPU enable */
    MPAT_ALL_DISABLE                    .set    0x00000040
    MPM_ALL_DISABLE                     .set    0x00000000

    .section ".reset", "ax"
    .align 2


code_start:
/* ; initialize registers */
    mov r0, r1
    mov r0, r2
    mov r0, r3
    mov r0, r4
    mov r0, r5
    mov r0, r6
    mov r0, r7
    mov r0, r8
    mov r0, r9
    mov r0, r10
    mov r0, r11
    mov r0, r12
    mov r0, r13
    mov r0, r14
    mov r0, r15
    mov r0, r16
    mov r0, r17
    mov r0, r18
    mov r0, r19
    mov r0, r20
    mov r0, r21
    mov r0, r22
    mov r0, r23
    mov r0, r24
    mov r0, r25
    mov r0, r26
    mov r0, r27
    mov r0, r28
    mov r0, r29
    ldsr    r0, 0, 0
    ldsr    r0, 16, 0

/* set global pointer *
    mov ___ghsbegin_sdabase, gp
/* set stack pointer */
    mov ___ghsend_RT_stack, sp

/* MPU Disable */
    stsr    0, r6 ,5
    andi    0xFFFE, r6, r6
    ldsr    r6, 0, 5
    SYNCM

/* MPU setting */
    mov BOOTROM_CODE_START_ADDRESS, r12         /* MPLA0 */
    ldsr r12, 0, 6
    mov BOOTROM_CODE_END_ADDRESS, r12           /* MPUA0 */
    ldsr r12, 1, 6
    mov ___ghsbegin_reset, r12                  /* MPLA1 */
    ldsr r12, 4, 6
    mov ___ghsend_rom_end, r12                  /* MPUA1 */
    ldsr r12, 5, 6
    mov SICREMAP_WINDOW_AREA_START_ADDRESS, r12 /* MPLA2 */
    ldsr r12, 8, 6
    mov SICREMAP_WINDOW_AREA_END_ADDRESS, r12   /* MPUA2 */
    ldsr r12, 9, 6
    mov ICU_REGISTER_AREA_START_ADDRESS, r12    /* MPLA3 */
    ldsr r12, 12, 6
    mov ICU_REGISTER_AREA_END_ADDRESS, r12      /* MPUA3 */
    ldsr r12, 13, 6
    mov MPAT_SX_SR_ENABLE, r12                  /* MPAT0 */
    ldsr r12, 2, 6
    mov MPAT_SX_SR_ENABLE, r12                  /* MPAT1 */
    ldsr r12, 6, 6
    mov MPAT_SW_SR_ENABLE, r12                  /* MPAT2 */
    ldsr r12, 10, 6
    mov MPAT_SW_SR_ENABLE, r12                  /* MPAT3 */
    ldsr r12, 14, 6
    mov MPRC_E3_TO_E0_ENABLE, r12               /* MPRC */
    ldsr r12, 1, 5
    mov MPM_SVP_MPE_ENABLE, r12                 /* MPM */
    ldsr r12, 0, 5
    SYNCM

/* BSS clear */
    mov     ___ghsbegin_bss, r6
    mov     ___ghsend_bss, r7
    mov     r0, r1
loop_clear:
    st.dw   r0, 0[r6]
    addi    8, r6, r6
    cmp     r7, r6
    bl      loop_clear

/* Set canary before jump another function.                       */
/* Don't call functions before calling __ghs_set_stack_chk_guard. */
    jarl    ___ghs_set_stack_chk_guard, lp

    mov _loader_main, r2
    jarl    [r2], lp

/* Release MPU setting */
    mov MPM_ALL_DISABLE, r12
    ldsr r12, 0, 5                  /* MPM */
    ldsr zero, 1, 5                 /* MPRC */
    mov MPAT_ALL_DISABLE, r12
    ldsr r12, 2, 6                  /* MPAT0 */
    ldsr r12, 6, 6                  /* MPAT1 */
    ldsr r12, 10, 6                 /* MPAT2 */
    ldsr r12, 14, 6                 /* MPAT3 */
    ldsr zero, 0, 6                 /* MPLA0 */
    ldsr zero, 1, 6                 /* MPUA0 */
    ldsr zero, 4, 6                 /* MPLA1 */
    ldsr zero, 5, 6                 /* MPUA1 */
    ldsr zero, 8, 6                 /* MPLA2 */
    ldsr zero, 9, 6                 /* MPUA2 */
    ldsr zero, 12, 6                /* MPLA3 */
    ldsr zero, 13, 6                /* MPUA3 */
    SYNCM

    jmp     [r10]
    nop
    halt

	.section ".padding"
	.align 4