810 lines
25 KiB
C
810 lines
25 KiB
C
/*******************************************************************************
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* DISCLAIMER
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* This software is supplied by Renesas Electronics Corporation and is only
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* intended for use with Renesas products. No other uses are authorized. This
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* software is owned by Renesas Electronics Corporation and is protected under
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* all applicable laws, including copyright laws.
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* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
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* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
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* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
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* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
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* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
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* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
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* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
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* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
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* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
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* Renesas reserves the right, without notice, to make changes to this software
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* and to discontinue the availability of this software. By using this software,
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* you agree to the additional terms and conditions found by accessing the
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* following link:
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* http://www.renesas.com/disclaimer
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* Copyright 2015-2022 Renesas Electronics Corporation All rights reserved.
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*******************************************************************************/
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/*******************************************************************************
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* DESCRIPTION : RPC driver for QSPI Flash
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******************************************************************************/
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/******************************************************************************
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* @file rpcqspidrv.c
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* - Version : 0.07
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* @brief RPC driver for QSPI Flash.
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* .
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*****************************************************************************/
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/******************************************************************************
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* History : DD.MM.YYYY Version Description
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* : 15.10.2021 0.01 First Release
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* : 16.02.2022 0.02 Modify how to write to RPC_WRBUF register.
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* : 15.03.2022 0.03 Modify to use inline function in mem_io.h
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* : when access to register.
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* : 18.03.2022 0.04 Modify to read modify write when write to
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* : register.
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* : 23.03.2022 0.05 Modify command for QSPI Flash to refer to
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* : command table.
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* : 01.04.2022 0.06 Modify magic number to definition.
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* : 09.11.2022 0.07 License notation change.
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*****************************************************************************/
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#include <stdint.h>
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#include <stddef.h>
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#include <remap.h>
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#include <mem_io.h>
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#include <micro_wait.h>
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#include <cpg_register.h>
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#include <rpc_register.h>
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#include <rpcqspidrv.h>
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#include <rpc.h>
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#include <wdt.h>
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#include <log.h>
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#include "dma2.h"
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static uint32_t read_register_qspi_flash(uint32_t cmd, uint32_t *readData);
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void init_rpc_qspi_flash_4fastread_ext_mode(void)
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{
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uint32_t reg;
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reg = mem_read32(RPC_PHYCNT);
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reg |= (RPC_PHYCNT_STRTIM3
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| RPC_PHYCNT_STRTIM2
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| RPC_PHYCNT_STRTIM1
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| RPC_PHYCNT_STRTIM0);
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reg &= ~(RPC_PHYCNT_HS
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| RPC_PHYCNT_WBUF2
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| RPC_PHYCNT_WBUF
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| RPC_PHYCNT_PHYMEM_HYP);
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mem_write32(RPC_PHYCNT, reg);
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reg |= RPC_PHYCNT_CAL;
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mem_write32(RPC_PHYCNT, reg);
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reg = mem_read32(RPC_CMNCR);
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reg &= ~(CMNCR_MD_MANUAL /* External address space read mode */
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| CMNCR_BSZ_MASK); /* Data Bus Size: Serial flash memory x 1*/
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reg |= (CMNCR_MOIIO3_HIZ
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| CMNCR_MOIIO2_HIZ
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| CMNCR_MOIIO1_HIZ
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| CMNCR_MOIIO0_HIZ
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| CMNCR_IO0FV_HIZ);
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mem_write32(RPC_CMNCR, reg);
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/* bit31 MD = 0 : External address space read mode */
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/* bit1-0 BSZ[1:0] = 00 : QSPI Flash x 1 */
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reg = mem_read32(RPC_DRCR);
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reg &= ~(DRCR_SSLN
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| DRCR_RCF
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| DRCR_SSLE);
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reg |= (DRCR_RBURST_32UNITS
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| DRCR_RBE_BURST);
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mem_write32(RPC_DRCR, reg);
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/* bit20-16 RBURST[4:0] = 11111 : 32 continuous data unit */
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/* bit8 RBE = 1 : Burst read */
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reg = mem_read32(RPC_DRCMR);
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reg &= ~(DRCMR_CMD_MASK
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| DRCMR_OCMD_MASK);
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reg |= ((gp_qspi_cmd_tbl -> read_fast) << DRCMR_SMCMR_CMD_SHIFT);
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mem_write32(RPC_DRCMR, reg);
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/* bit23-16 CMD[7:0] = 0x0C : 4FAST_READ 0Ch Command 4-byte address command */
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reg = mem_read32(RPC_DREAR);
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reg &= ~(DREAR_EAV_MASK
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| DREAR_EAC_MASK);
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reg |= DREAR_EAC_26BITS;
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mem_write32(RPC_DREAR, reg);
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/* bit23-16 EAV[7:0] = 0 : ADR[32:26] output set0 */
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/* bit2-0 EAC[2:0] = 001 : ADR[25:0 ] Enable */
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reg = mem_read32(RPC_DRENR);
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reg &= ~(DRENR_CDB_MASK
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| DRENR_OCDB_MASK
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| DRENR_ADB_MASK
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| DRENR_OPDB_MASK
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| DRENR_DRDB_MASK
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| DRENR_OCDE_EN
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| DRENR_ADE_MASK
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| DRENR_OPDE_MASK);
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reg |= (DRENR_DME_EN
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| DRENR_CDE_EN
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| DRENR_ADE_ONE_SERIAL);
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mem_write32(RPC_DRENR, reg);
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/* bit31-30 CDB[1:0] = 00 : 1bit width command (QSPI0_MOSI) */
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/* bit25-24 ADB[1:0] = 00 : 1bit width address (QSPI0_MOSI) */
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/* bit17-16 DRDB[1:0] = 00 : 1bit width transfer data (QSPI0_IO0) */
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/* bit15 DME = 1 : dummy cycle enable */
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/* bit14 CDE = 1 : Command enable */
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/* bit11-8 ADE[3:0] = 1111 : ADR[31:0] output (32 Bit Address) */
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reg = mem_read32(RPC_DRDMCR);
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reg &= ~(DRDMCR_DMCYC_MASK);
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reg |= DRDMCR_DMCYC_8;
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mem_write32(RPC_DRDMCR, reg);
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/* bit2-0 DMCYC[2:0] = 111 : 8 cycle dummy wait */
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reg = mem_read32(RPC_DRDRENR);
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reg &= ~(DRDRENR_HYPE_MASK
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| DRDRENR_ADDRE
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| DRDRENR_OPDRE
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| DRDRENR_DRDRE);
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mem_write32(RPC_DRDRENR, reg);
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/* bit8 ADDRE = 0 : Address SDR transfer */
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/* bit0 DRDRE = 0 : DATA SDR transfer */
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}
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/* End of function init_rpc_qspi_flash_4fastread_ext_mode */
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void init_rpc_qspi_flash(void)
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{
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uint32_t reg;
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power_on_rpc();
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set_rpc_clock_mode(RPC_CLK_80M);
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reset_rpc();
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set_rpc_ssl_delay();
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reg = mem_read32(RPC_OFFSET1);
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reg &= ~(PHYOFFSET1_MASK);
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reg |= PHYOFFSET1_DMA_QSPI;
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mem_write32(RPC_OFFSET1, reg);
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}
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/* End of function init_rpc_qspi_flash */
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/* 4SE DCh 4-byte address */
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void sector_erase_4byte_qspi_flash(uint32_t sector_addr)
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{
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uint32_t reg;
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reg = mem_read32(RPC_PHYCNT);
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reg |= (RPC_PHYCNT_CAL
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| RPC_PHYCNT_STRTIM3
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| RPC_PHYCNT_STRTIM2
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| RPC_PHYCNT_STRTIM1
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| RPC_PHYCNT_STRTIM0);
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reg &= ~(RPC_PHYCNT_HS
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| RPC_PHYCNT_WBUF2
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| RPC_PHYCNT_WBUF
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| RPC_PHYCNT_PHYMEM_HYP);
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mem_write32(RPC_PHYCNT, reg);
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/* bit31 CAL = 1 : PHY calibration */
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/* bit1-0 PHYMEM[1:0] = 00 : QSPI-SDR */
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reg = mem_read32(RPC_CMNCR);
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reg &= ~(CMNCR_BSZ_MASK);
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reg |= (CMNCR_MD_MANUAL
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| CMNCR_MOIIO3_HIZ
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| CMNCR_MOIIO2_HIZ
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| CMNCR_MOIIO1_HIZ
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| CMNCR_MOIIO0_HIZ
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| CMNCR_IO0FV_HIZ);
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mem_write32(RPC_CMNCR, reg);
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/* bit31 MD = 1 : Manual mode */
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/* bit1-0 BSZ[1:0] = 00 : QSPI Flash x 1 */
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reg = mem_read32(RPC_SMCMR);
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reg &= ~(SMCMR_CMD_MASK
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| SMCMR_OCMD_MASK);
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reg |= ((gp_qspi_cmd_tbl -> sector_erase_4byte_addr) << DRCMR_SMCMR_CMD_SHIFT);
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mem_write32(RPC_SMCMR, reg);
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/* bit23-16 CMD[7:0] = 0xDC : Sector Erase 4-byte address command */
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mem_write32(RPC_SMADR, sector_addr);
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reg = mem_read32(RPC_SMDRENR);
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reg &= ~(SMDRENR_HYPE_MASK
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| SMDRENR_ADDRE
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| SMDRENR_OPDRE
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| SMDRENR_SPIDRE);
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mem_write32(RPC_SMDRENR, reg);
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/* bit8 ADDRE = 0 : Address SDR transfer */
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/* bit0 SPIDRE = 0 : DATA SDR transfer */
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reg = mem_read32(RPC_SMENR);
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reg &= ~(SMENR_CDB_MASK
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| SMENR_OCDB_MASK
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| SMENR_ADB_MASK
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| SMENR_OPDB_MASK
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| SMENR_SPIDB_MASK
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| SMENR_DME_EN
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| SMENR_OCDE_EN
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| SMENR_ADE_MASK
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| SMENR_OPDE_MASK
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| SMENR_SPIDE_MASK);
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reg |= (SMENR_CDE_EN
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| SMENR_ADE_SERIAL_31);
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mem_write32(RPC_SMENR, reg);
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/* bit31-30 CDB[1:0] = 00 : 1bit width command (QSPI0_MOSI) */
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/* bit25-24 ADB[1:0] = 00 : 1bit width address (QSPI0_MOSI) */
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/* bit17-16 SPIDB[1:0] = 00 : 1bit width transfer data (QSPI0_MISO) */
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/* bit15 DME = 0 : No dummy cycle */
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/* bit14 CDE = 1 : Command enable */
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/* bit11-8 ADE[3:0] = 1111 : ADR[31:0] output (32 Bit Address) */
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/* bit3-0 SPIDE[3:0] = 0000 : No transfer */
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reg = mem_read32(RPC_SMCR);
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reg &= ~(SMCR_SSLKP
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| SMCR_SPIRE
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| SMCR_SPIWE);
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reg |= SMCR_SPIE;
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mem_write32(RPC_SMCR, reg);
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/* bit2 SPIRE = 0 : Data read disable */
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/* bit1 SPIWE = 0 : Data write disable */
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/* bit0 SPIE = 1 : SPI transfer start */
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wait_rpc_tx_end();
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}
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/* End of function sector_erase_4byte_qspi_flash */
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/* 4P4E 21h 4-byte address */
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void parameter_sector_erase_4kb_qspi_flash(uint32_t sector_addr)
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{
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uint32_t reg;
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reg = mem_read32(RPC_PHYCNT);
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reg |= (RPC_PHYCNT_CAL
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| RPC_PHYCNT_STRTIM3
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| RPC_PHYCNT_STRTIM2
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| RPC_PHYCNT_STRTIM1
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| RPC_PHYCNT_STRTIM0);
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reg &= ~(RPC_PHYCNT_HS
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| RPC_PHYCNT_WBUF2
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| RPC_PHYCNT_WBUF
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| RPC_PHYCNT_PHYMEM_HYP);
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mem_write32(RPC_PHYCNT, reg);
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/* bit31 CAL = 1 : PHY calibration */
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/* bit1-0 PHYMEM[1:0] = 00 : QSPI-SDR */
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reg = mem_read32(RPC_CMNCR);
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reg &= ~(CMNCR_BSZ_MASK);
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reg |= (CMNCR_MD_MANUAL
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| CMNCR_MOIIO3_HIZ
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| CMNCR_MOIIO2_HIZ
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| CMNCR_MOIIO1_HIZ
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| CMNCR_MOIIO0_HIZ
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| CMNCR_IO0FV_HIZ);
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mem_write32(RPC_CMNCR, reg);
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/* bit31 MD = 1 : Manual mode */
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/* bit1-0 BSZ[1:0] = 00 : QSPI Flash x 1 */
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reg = mem_read32(RPC_SMCMR);
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reg &= ~(SMCMR_CMD_MASK
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| SMCMR_OCMD_MASK);
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reg |= ((gp_qspi_cmd_tbl -> parameter_4kbyte_erase) << DRCMR_SMCMR_CMD_SHIFT);
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mem_write32(RPC_SMCMR, reg);
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/* bit23-16 CMD[7:0] = 0x21 : Parameter 4-kB Sector Erasecommand */
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mem_write32(RPC_SMADR, sector_addr);
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reg = mem_read32(RPC_SMDRENR);
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reg &= ~(SMDRENR_HYPE_MASK
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| SMDRENR_ADDRE
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| SMDRENR_OPDRE
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| SMDRENR_SPIDRE);
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mem_write32(RPC_SMDRENR, reg);
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/* bit8 ADDRE = 0 : Address SDR transfer */
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/* bit0 SPIDRE = 0 : DATA SDR transfer */
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reg = mem_read32(RPC_SMENR);
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reg &= ~(SMENR_CDB_MASK
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| SMENR_OCDB_MASK
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| SMENR_ADB_MASK
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| SMENR_OPDB_MASK
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| SMENR_SPIDB_MASK
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| SMENR_DME_EN
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| SMENR_OCDE_EN
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| SMENR_ADE_MASK
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| SMENR_OPDE_MASK
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| SMENR_SPIDE_MASK);
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reg |= (SMENR_CDE_EN
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| SMENR_ADE_SERIAL_31);
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mem_write32(RPC_SMENR, reg);
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/* bit31-30 CDB[1:0] = 00 : 1bit width command (QSPI0_MOSI) */
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/* bit25-24 ADB[1:0] = 00 : 1bit width address (QSPI0_MOSI) */
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/* bit17-16 SPIDB[1:0] = 00 : 1bit width transfer data (QSPI0_MISO) */
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/* bit15 DME = 0 : No dummy cycle */
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/* bit14 CDE = 1 : Command enable */
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/* bit11-8 ADE[3:0] = 1111 : ADR[31:0] output (32 Bit Address) */
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/* bit3-0 SPIDE[3:0] = 0000 : No transfer */
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reg = mem_read32(RPC_SMCR);
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reg &= ~(SMCR_SSLKP
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| SMCR_SPIRE
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| SMCR_SPIWE);
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reg |= SMCR_SPIE;
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mem_write32(RPC_SMCR, reg);
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/* bit2 SPIRE = 0 : Data read disable */
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/* bit1 SPIWE = 0 : Data write disable */
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/* bit0 SPIE = 1 : SPI transfer start */
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wait_rpc_tx_end();
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}
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/* End of function parameter_sector_erase_4kb_qspi_flash */
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/* Page Program (4PP:12h) 4-byte address */
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void write_data_4pp_with_buf_qspi_flash(uint32_t addr, uint32_t source_addr)
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{
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uintptr_t i=0;
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uint32_t reg;
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reg = mem_read32(RPC_DRCR);
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reg |= (DRCR_SSLN
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| DRCR_RBURST_32UNITS
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| DRCR_RCF
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| DRCR_RBE_BURST
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| DRCR_SSLE);
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mem_write32(RPC_DRCR, reg);
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/* bit9 RCF = 1 : Read Cache Clear */
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reg = mem_read32(RPC_PHYCNT);
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reg |= (RPC_PHYCNT_CAL
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| RPC_PHYCNT_STRTIM3
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| RPC_PHYCNT_STRTIM2
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| RPC_PHYCNT_STRTIM1
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| RPC_PHYCNT_STRTIM0
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| RPC_PHYCNT_WBUF2
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| RPC_PHYCNT_WBUF);
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reg &= ~(RPC_PHYCNT_HS
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| RPC_PHYCNT_PHYMEM_HYP);
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mem_write32(RPC_PHYCNT, reg);
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/* bit31 CAL = 1 : PHY calibration */
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/* bit2 WBUF = 1 : Write Buffer Enable */
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/* bit1-0 PHYMEM[1:0] = 00 : QSPI-SDR */
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for(i = 0; i < RPC_WRITE_BUF_SIZE; i = i + TRANS_SIZE_64BYTE)
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{
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dma2_start_xbyte(RPC_WRBUF_PHYS+i, source_addr+i, TRANS_SIZE_64BYTE, TRANS_UNIT_64BYTES);
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dma2_end();
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// dma_trans_start(RPC_WRBUF_PHYS+i, source_addr+i, TRANS_SIZE_64BYTE);
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// dma_trans_end_check();
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}
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reg = mem_read32(RPC_CMNCR);
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reg &= ~(CMNCR_BSZ_MASK);
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reg |= (CMNCR_MD_MANUAL
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| CMNCR_MOIIO3_HIZ
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| CMNCR_MOIIO2_HIZ
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| CMNCR_MOIIO1_HIZ
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| CMNCR_MOIIO0_HIZ
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| CMNCR_IO0FV_HIZ);
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mem_write32(RPC_CMNCR, reg);
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/* bit31 MD = 1 : Manual mode */
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/* bit1-0 BSZ[1:0] = 00 : QSPI Flash x 1 */
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reg = mem_read32(RPC_SMCMR);
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reg &= ~(SMCMR_CMD_MASK
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| SMCMR_OCMD_MASK);
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reg |= ((gp_qspi_cmd_tbl -> pp_4byte_addr) << DRCMR_SMCMR_CMD_SHIFT);
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mem_write32(RPC_SMCMR, reg);
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/* bit23-16 CMD[7:0] = 0x12 : Page Program 4-byte address */
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mem_write32(RPC_SMADR, addr);
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reg = mem_read32(RPC_SMDRENR);
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reg &= ~(SMDRENR_HYPE_MASK
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| SMDRENR_ADDRE
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| SMDRENR_OPDRE
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| SMDRENR_SPIDRE);
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mem_write32(RPC_SMDRENR, reg);
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/* bit8 ADDRE = 0 : Address SDR transfer */
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/* bit0 SPIDRE = 0 : DATA SDR transfer */
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reg = mem_read32(RPC_SMENR);
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reg &= ~(SMENR_CDB_MASK
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| SMENR_OCDB_MASK
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| SMENR_ADB_MASK
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| SMENR_OPDB_MASK
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| SMENR_SPIDB_MASK
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| SMENR_DME_EN
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| SMENR_OCDE_EN
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| SMENR_ADE_MASK
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| SMENR_OPDE_MASK
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| SMENR_SPIDE_MASK);
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reg |= (SMENR_CDE_EN
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| SMENR_ADE_SERIAL_31
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| SMENR_SPIDE_SPI_32);
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mem_write32(RPC_SMENR, reg);
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/* bit31-30 CDB[1:0] = 00 : 1bit width command (QSPI0_MOSI) */
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/* bit25-24 ADB[1:0] = 00 : 1bit width address (QSPI0_MOSI) */
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/* bit17-16 SPIDB[1:0] = 00 : 1bit width transfer data (QSPI0_MISO) */
|
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/* bit15 DME = 0 : No dummy cycle */
|
|
/* bit14 CDE = 1 : Command enable */
|
|
/* bit11-8 ADE[3:0] = 1111 : ADR[31:0] is output */
|
|
/* bit3-0 SPIDE[3:0] = 1111 : 32bit transfer */
|
|
|
|
reg = mem_read32(RPC_SMCR);
|
|
reg &= ~(SMCR_SSLKP
|
|
| SMCR_SPIRE);
|
|
reg |= (SMCR_SPIWE
|
|
| SMCR_SPIE);
|
|
mem_write32(RPC_SMCR, reg);
|
|
/* bit2 SPIRE = 0 : Data read disable */
|
|
/* bit1 SPIWE = 1 : Data write enable */
|
|
/* bit0 SPIE = 1 : SPI transfer start */
|
|
|
|
wait_rpc_tx_end();
|
|
|
|
reg = mem_read32(RPC_PHYCNT);
|
|
reg |= (RPC_PHYCNT_STRTIM3
|
|
| RPC_PHYCNT_STRTIM2
|
|
| RPC_PHYCNT_STRTIM1
|
|
| RPC_PHYCNT_STRTIM0
|
|
| RPC_PHYCNT_WBUF2);
|
|
reg &= ~(RPC_PHYCNT_HS
|
|
| RPC_PHYCNT_WBUF
|
|
| RPC_PHYCNT_PHYMEM_HYP);
|
|
mem_write32(RPC_PHYCNT, reg);
|
|
/* bit31 CAL = 0 : No PHY calibration */
|
|
/* bit2 WBUF = 0 : Write Buffer Disable */
|
|
/* bit1-0 PHYMEM[1:0] = 00 : QSPI-SDR */
|
|
|
|
reg = mem_read32(RPC_DRCR);
|
|
reg |= (DRCR_SSLN
|
|
| DRCR_RBURST_32UNITS
|
|
| DRCR_RCF
|
|
| DRCR_RBE_BURST
|
|
| DRCR_SSLE);
|
|
mem_write32(RPC_DRCR, reg);
|
|
/* bit9 RCF = 1 : Read Cache Clear */
|
|
}
|
|
/* End of function write_data_4pp_with_buf_qspi_flash */
|
|
|
|
/* OnBoard QspiFlash(MT25QU01GB) */
|
|
uint32_t read_wip_status_register(uint32_t *readData) /* for QSPIx1ch */
|
|
{
|
|
return read_register_qspi_flash(gp_qspi_cmd_tbl -> read_any_register, readData);
|
|
}
|
|
|
|
#define RDCR_cmd 0x15
|
|
uint32_t read_configuration_register(uint32_t *readData) /* for QSPIx1ch */
|
|
{
|
|
return read_register_qspi_flash(RDCR_cmd, readData);
|
|
}
|
|
|
|
#define WRSR_cmd 0x01
|
|
void write_status_register(uint16_t stat_conf)
|
|
{
|
|
uint32_t reg;
|
|
|
|
reg = mem_read32(RPC_PHYCNT);
|
|
reg |= (RPC_PHYCNT_CAL
|
|
| RPC_PHYCNT_STRTIM3
|
|
| RPC_PHYCNT_STRTIM2
|
|
| RPC_PHYCNT_STRTIM1
|
|
| RPC_PHYCNT_STRTIM0);
|
|
reg &= ~(RPC_PHYCNT_HS
|
|
| RPC_PHYCNT_WBUF2
|
|
| RPC_PHYCNT_WBUF
|
|
| RPC_PHYCNT_PHYMEM_HYP);
|
|
mem_write32(RPC_PHYCNT, reg);
|
|
/* bit31 CAL = 1 : PHY calibration */
|
|
/* bit1-0 PHYMEM[1:0] = 00 : QSPI-SDR */
|
|
|
|
reg = mem_read32(RPC_CMNCR);
|
|
reg &= ~(CMNCR_BSZ_MASK);
|
|
reg |= (CMNCR_MD_MANUAL
|
|
| CMNCR_MOIIO3_HIZ
|
|
| CMNCR_MOIIO2_HIZ
|
|
| CMNCR_MOIIO1_HIZ
|
|
| CMNCR_MOIIO0_HIZ
|
|
| CMNCR_IO0FV_HIZ);
|
|
mem_write32(RPC_CMNCR, reg);
|
|
/* bit31 MD = 1 : Manual mode */
|
|
/* bit1-0 BSZ[1:0] = 00 : QSPI Flash x 1 */
|
|
|
|
reg = mem_read32(RPC_SMCMR);
|
|
reg &= ~(SMCMR_CMD_MASK
|
|
| SMCMR_OCMD_MASK);
|
|
reg |= ((WRSR_cmd) << DRCMR_SMCMR_CMD_SHIFT);
|
|
mem_write32(RPC_SMCMR, reg);
|
|
/* bit23-16 CMD[7:0] = 0x01 : write status/configuration register command */
|
|
|
|
reg = mem_read32(RPC_SMENR);
|
|
reg &= ~(SMENR_CDB_MASK
|
|
| SMENR_OCDB_MASK
|
|
| SMENR_ADB_MASK
|
|
| SMENR_OPDB_MASK
|
|
| SMENR_SPIDB_MASK
|
|
| SMENR_DME_EN
|
|
| SMENR_OCDE_EN
|
|
| SMENR_ADE_MASK
|
|
| SMENR_OPDE_MASK
|
|
| SMENR_SPIDE_MASK);
|
|
reg |= (SMENR_CDE_EN
|
|
| SMENR_SPIDE_SPI_16);
|
|
mem_write32(RPC_SMENR, reg);
|
|
/* bit31-30 CDB[1:0] = 00 : 1bit width command (QSPI0_MOSI) */
|
|
/* bit25-24 ADB[1:0] = 00 : 1bit width address (QSPI0_MOSI) */
|
|
/* bit17-16 SPIDB[1:0] = 00 : 1bit width transfer data (QSPI0_MISO) */
|
|
/* bit15 DME = 0 : No dummy cycle */
|
|
/* bit14 CDE = 1 : Command enable */
|
|
/* bit11-8 ADE[3:0] = 0000 : Address output disable */
|
|
/* bit3-0 SPIDE[3:0] = 1100 : 16bit transfer */
|
|
|
|
mem_write16(RPC_SMWDR0, stat_conf);
|
|
|
|
reg = mem_read32(RPC_SMCR);
|
|
reg &= ~(SMCR_SSLKP
|
|
| SMCR_SPIRE);
|
|
reg |= (SMCR_SPIWE
|
|
| SMCR_SPIE);
|
|
mem_write32(RPC_SMCR, reg);
|
|
/* bit2 SPIRE = 0 : Data read disable */
|
|
/* bit1 SPIWE = 1 : Data write enable */
|
|
/* bit0 SPIE = 1 : SPI transfer start */
|
|
|
|
wait_rpc_tx_end();
|
|
}
|
|
|
|
void set_rpc_clock_mode(uint32_t mode)
|
|
{
|
|
uint32_t dataL=0;
|
|
uint32_t reg;
|
|
|
|
if(mode == RPC_CLK_160M){
|
|
dataL = RPCCKCR_RPCFC_160M; /* RPC clock 160MHz */
|
|
}else if(mode == RPC_CLK_80M){
|
|
dataL = RPCCKCR_RPCFC_80M; /* RPC clock 80MHz */
|
|
}else{
|
|
dataL = RPCCKCR_RPCFC_40M; /* RPC clock 40MHz */
|
|
}
|
|
|
|
reg = mem_read32(CPG_RPCCKCR);
|
|
reg &= ~(RPCCKCR_RPCFC_MASK);
|
|
dataL |= reg;
|
|
mem_write32(CPG_CPGWPR, ~dataL);
|
|
mem_write32(CPG_RPCCKCR, dataL);
|
|
|
|
(void)mem_read32(CPG_RPCCKCR); /* dummy read */
|
|
}
|
|
/* End of function set_rpc_clock_mode */
|
|
|
|
void wait_rpc_tx_end(void)
|
|
{
|
|
uint32_t dataL=0;
|
|
|
|
while(1)
|
|
{
|
|
wdt_restart();
|
|
dataL = mem_read32(RPC_CMNSR);
|
|
if(dataL & BIT0) break;
|
|
/* Wait for TEND = 1 */
|
|
}
|
|
}
|
|
/* End of function wait_rpc_tx_end */
|
|
|
|
void reset_rpc(void)
|
|
{
|
|
mem_write32(CPG_CPGWPR, ~BIT29);
|
|
mem_write32(CPG_SRCR6, BIT29);
|
|
/* wait: tRLRH Reset# low pulse width 10us */
|
|
micro_wait(20); /* wait 20us */
|
|
|
|
mem_write32(CPG_CPGWPR, ~BIT29);
|
|
mem_write32(CPG_SRSTCLR6, BIT29);
|
|
/* wait: tREADY1(35us) - tRHSL(10us) = 25us */
|
|
micro_wait(40); /* wait 40us */
|
|
}
|
|
/* End of function reset_rpc */
|
|
|
|
void set_rpc_ssl_delay(void)
|
|
{
|
|
uint32_t reg;
|
|
|
|
reg = mem_read32(RPC_SSLDR);
|
|
reg |= SSLDR_SLNDL;
|
|
mem_write32(RPC_SSLDR, reg);
|
|
/* bit10-8 SLNDL[2:0] = 100 : 5.5 cycles of QSPIn_SPCLK */
|
|
}
|
|
/* End of function set_rpc_ssl_delay */
|
|
|
|
void power_on_rpc(void)
|
|
{
|
|
uint32_t dataL=0;
|
|
dataL = mem_read32(CPG_MSTPSR6);
|
|
if(dataL & BIT29){ /* case RPC(QSPI) Standby */
|
|
dataL &= ~BIT29;
|
|
mem_write32(CPG_CPGWPR, ~dataL);
|
|
mem_write32(CPG_MSTPCR6, dataL);
|
|
while( BIT29 & mem_read32(CPG_MSTPSR6) ); /* wait bit=0 */
|
|
}
|
|
}
|
|
/* End of function power_on_rpc */
|
|
|
|
uint32_t read_qspi_flash_id(uint32_t *readData) /* for QSPIx1ch */
|
|
{
|
|
return read_register_qspi_flash(FLASH_CMD_READ_ID, readData);
|
|
}
|
|
|
|
uint32_t read_status_qspi_flash(uint32_t *readData) {
|
|
return read_register_qspi_flash(gp_qspi_cmd_tbl -> read_stts_register, readData);
|
|
}
|
|
|
|
static uint32_t read_register_qspi_flash(uint32_t cmd, uint32_t *readData) /* for QSPIx1ch */
|
|
{
|
|
uint32_t reg;
|
|
|
|
reg = mem_read32(RPC_PHYCNT);
|
|
reg |= (RPC_PHYCNT_STRTIM3
|
|
| RPC_PHYCNT_STRTIM2
|
|
| RPC_PHYCNT_STRTIM1
|
|
| RPC_PHYCNT_STRTIM0);
|
|
reg &= ~(RPC_PHYCNT_HS
|
|
| RPC_PHYCNT_WBUF2
|
|
| RPC_PHYCNT_WBUF
|
|
| RPC_PHYCNT_PHYMEM_HYP);
|
|
mem_write32(RPC_PHYCNT, reg);
|
|
reg |= RPC_PHYCNT_CAL;
|
|
mem_write32(RPC_PHYCNT, reg);
|
|
/* bit31 CAL = 1 : PHY calibration */
|
|
/* bit1-0 PHYMEM[1:0] = 00 : QSPI-SDR */
|
|
|
|
reg = mem_read32(RPC_CMNCR);
|
|
reg &= ~(CMNCR_BSZ_MASK);
|
|
reg |= (CMNCR_MD_MANUAL
|
|
| CMNCR_MOIIO3_HIZ
|
|
| CMNCR_MOIIO2_HIZ
|
|
| CMNCR_MOIIO1_HIZ
|
|
| CMNCR_MOIIO0_HIZ
|
|
| CMNCR_IO0FV_HIZ);
|
|
mem_write32(RPC_CMNCR, reg);
|
|
/* bit31 MD = 1 : Manual mode */
|
|
/* bit1-0 BSZ[1:0] = 00 : QSPI Flash x 1 */
|
|
|
|
reg = mem_read32(RPC_SMCMR);
|
|
reg &= ~(SMCMR_CMD_MASK
|
|
| SMCMR_OCMD_MASK);
|
|
reg |= ((cmd) << DRCMR_SMCMR_CMD_SHIFT);
|
|
mem_write32(RPC_SMCMR, reg);
|
|
/* bit23-16 CMD[7:0] = 0x05 : Status Read command (for Palladium QSPI model) */
|
|
|
|
reg = mem_read32(RPC_SMDRENR);
|
|
reg &= ~(SMDRENR_HYPE_MASK
|
|
| SMDRENR_ADDRE
|
|
| SMDRENR_OPDRE
|
|
| SMDRENR_SPIDRE);
|
|
mem_write32(RPC_SMDRENR, reg);
|
|
/* bit8 ADDRE = 0 : Address SDR transfer */
|
|
/* bit0 SPIDRE = 0 : DATA SDR transfer */
|
|
|
|
reg = mem_read32(RPC_SMENR);
|
|
reg &= ~(SMENR_CDB_MASK
|
|
| SMENR_OCDB_MASK
|
|
| SMENR_ADB_MASK
|
|
| SMENR_OPDB_MASK
|
|
| SMENR_SPIDB_MASK
|
|
| SMENR_DME_EN
|
|
| SMENR_OCDE_EN
|
|
| SMENR_ADE_MASK
|
|
| SMENR_OPDE_MASK
|
|
| SMENR_SPIDE_MASK);
|
|
reg |= (SMENR_CDE_EN
|
|
| SMENR_SPIDE_SPI_32);
|
|
mem_write32(RPC_SMENR, reg);
|
|
/* bit31-30 CDB[1:0] = 00 : 1bit width command (QSPI0_MOSI) */
|
|
/* bit25-24 ADB[1:0] = 00 : 1bit width address (QSPI0_MOSI) */
|
|
/* bit17-16 SPIDB[1:0] = 00 : 1bit width transfer data (QSPI0_MISO) */
|
|
/* bit15 DME = 0 : No dummy cycle */
|
|
/* bit14 CDE = 1 : Command enable */
|
|
/* bit11-8 ADE[3:0] = 0000 : Address output disable */
|
|
/* bit3-0 SPIDE[3:0] = 1111 : 32bit transfer */
|
|
|
|
reg = mem_read32(RPC_SMCR);
|
|
reg &= ~(SMCR_SSLKP
|
|
| SMCR_SPIWE);
|
|
reg |= (SMCR_SPIRE
|
|
| SMCR_SPIE);
|
|
mem_write32(RPC_SMCR, reg);
|
|
/* bit2 SPIRE = 1 : Data read enable */
|
|
/* bit1 SPIWE = 0 : Data write disable */
|
|
/* bit0 SPIE = 1 : SPI transfer start */
|
|
|
|
wait_rpc_tx_end();
|
|
|
|
readData[0] = mem_read32(RPC_SMRDR0); /* read data[31:0] */
|
|
|
|
return(readData[0]);
|
|
}
|
|
/* End of function read_register_qspi_flash */
|
|
|
|
void write_command_qspi_flash(uint32_t command) /* for QSPIx1ch */
|
|
{
|
|
uint32_t reg;
|
|
|
|
reg = mem_read32(RPC_PHYCNT);
|
|
reg |= (RPC_PHYCNT_CAL
|
|
| RPC_PHYCNT_STRTIM3
|
|
| RPC_PHYCNT_STRTIM2
|
|
| RPC_PHYCNT_STRTIM1
|
|
| RPC_PHYCNT_STRTIM0);
|
|
reg &= ~(RPC_PHYCNT_HS
|
|
| RPC_PHYCNT_WBUF2
|
|
| RPC_PHYCNT_WBUF
|
|
| RPC_PHYCNT_PHYMEM_HYP);
|
|
mem_write32(RPC_PHYCNT, reg);
|
|
/* bit31 CAL = 1 : PHY calibration */
|
|
/* bit1-0 PHYMEM[1:0] = 00 : QSPI-SDR */
|
|
|
|
reg = mem_read32(RPC_CMNCR);
|
|
reg &= ~(CMNCR_BSZ_MASK);
|
|
reg |= (CMNCR_MD_MANUAL
|
|
| CMNCR_MOIIO3_HIZ
|
|
| CMNCR_MOIIO2_HIZ
|
|
| CMNCR_MOIIO1_HIZ
|
|
| CMNCR_MOIIO0_HIZ
|
|
| CMNCR_IO0FV_HIZ);
|
|
mem_write32(RPC_CMNCR, reg);
|
|
/* bit31 MD = 1 : Manual mode */
|
|
/* bit1-0 BSZ[1:0] = 00 : QSPI Flash x 1 */
|
|
|
|
reg = mem_read32(RPC_SMCMR);
|
|
reg &= ~(SMCMR_CMD_MASK
|
|
| SMCMR_OCMD_MASK);
|
|
reg |= (command & (SMCMR_CMD_MASK | SMCMR_OCMD_MASK));
|
|
mem_write32(RPC_SMCMR, reg);
|
|
/* bit23-16 CMD[7:0] : command */
|
|
|
|
reg = mem_read32(RPC_SMDRENR);
|
|
reg &= ~(SMDRENR_HYPE_MASK
|
|
| SMDRENR_ADDRE
|
|
| SMDRENR_OPDRE
|
|
| SMDRENR_SPIDRE);
|
|
mem_write32(RPC_SMDRENR, reg);
|
|
/* bit8 ADDRE = 0 : Address SDR transfer */
|
|
/* bit0 SPIDRE = 0 : DATA SDR transfer */
|
|
|
|
reg = mem_read32(RPC_SMENR);
|
|
reg &= ~(SMENR_CDB_MASK
|
|
| SMENR_OCDB_MASK
|
|
| SMENR_ADB_MASK
|
|
| SMENR_OPDB_MASK
|
|
| SMENR_SPIDB_MASK
|
|
| SMENR_DME_EN
|
|
| SMENR_OCDE_EN
|
|
| SMENR_ADE_MASK
|
|
| SMENR_ADE_MASK
|
|
| SMENR_OPDE_MASK
|
|
| SMENR_SPIDE_MASK);
|
|
reg |= SMENR_CDE_EN;
|
|
mem_write32(RPC_SMENR, reg);
|
|
/* bit31-30 CDB[1:0] = 00 : 1bit width command (QSPI0_MOSI) */
|
|
/* bit25-24 ADB[1:0] = 00 : 1bit width address (QSPI0_MOSI) */
|
|
/* bit17-16 SPIDB[1:0] = 00 : 1bit width transfer data (QSPI0_MISO) */
|
|
/* bit15 DME = 0 : No dummy cycle */
|
|
/* bit14 CDE = 1 : Command enable */
|
|
/* bit11-8 ADE[3:0] = 0000 : Address output disable */
|
|
/* bit3-0 SPIDE[3:0] = 0000 : No transfer */
|
|
|
|
reg = mem_read32(RPC_SMCR);
|
|
reg &= ~(SMCR_SSLKP
|
|
| SMCR_SPIRE
|
|
| SMCR_SPIWE);
|
|
reg |= SMCR_SPIE;
|
|
mem_write32(RPC_SMCR, reg);
|
|
/* bit2 SPIRE = 0 : Data read disable */
|
|
/* bit1 SPIWE = 0 : Data write disable */
|
|
/* bit0 SPIE = 1 : SPI transfer start */
|
|
|
|
wait_rpc_tx_end();
|
|
|
|
}
|
|
/* End of function write_command_qspi_flash */
|
|
|