104 lines
6.2 KiB
C
104 lines
6.2 KiB
C
/*******************************************************************************
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* DISCLAIMER
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* This software is supplied by Renesas Electronics Corporation and is only
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* intended for use with Renesas products. No other uses are authorized. This
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* software is owned by Renesas Electronics Corporation and is protected under
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* all applicable laws, including copyright laws.
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* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
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* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
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* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
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* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
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* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
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* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
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* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
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* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
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* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
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* Renesas reserves the right, without notice, to make changes to this software
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* and to discontinue the availability of this software. By using this software,
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* you agree to the additional terms and conditions found by accessing the
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* following link:
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* http://www.renesas.com/disclaimer
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* Copyright 2022 Renesas Electronics Corporation All rights reserved.
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*******************************************************************************/
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/*******************************************************************************
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* DESCRIPTION : CPU register access list header
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******************************************************************************/
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#ifndef CPU_H_
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#define CPU_H_
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/*
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* Groups
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*/
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/* Name Reg, Group Comment */
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#define EIPC 0, 0 /* Status save registers when acknowledging EI level exception SV */
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#define EIPSW 1, 0 /* Status save registers when acknowledging EI level exception SV */
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#define FEPC 2, 0 /* Status save registers when acknowledging FE level exception SV */
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#define FEPSW 3, 0 /* Status save registers when acknowledging FE level exception SV */
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#define PSW 5, 0 /* Program status word Note 1 */
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#define EIIC 13, 0 /* EI level exception cause SV */
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#define FEIC 14, 0 /* FE level exception cause SV */
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#define CTPC 16, 0 /* CALLT execution status save register UM */
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#define CTPSW 17, 0 /* CALLT execution status save register UM */
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#define CTBP 20, 0 /* CALLT base pointer UM */
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#define EIWR 28, 0 /* EI level exception working register SV */
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#define FEWR 29, 0 /* FE level exception working register SV */
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#define BSEL 31, 0 /* (Reserved for backward compatibility with V850E2 series)Note 2 SV */
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#define MCFG0 0, 1 /* Machine configuration SV */
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#define RBASE 2, 1 /* Reset vector base address SV */
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#define EBASE 3, 1 /* Exception handler vector address SV */
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#define INTBP 4, 1 /* Base address of the interrupt handler table SV */
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#define MCTL 5, 1 /* CPU control SV */
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#define PID 6, 1 /* Processor ID SV */
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#define SCCFG 11, 1 /* SYSCALL operation setting SV */
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#define SCBP 12, 1 /* SYSCALL base pointer SV */
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#define HTCFG0 0, 2 /* Thread configuration SV */
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#define MEA 6, 2 /* Memory error address SV */
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#define ASID 7, 2 /* Address space ID SV */
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#define MEI 8, 2 /* Memory error information SV */
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#define ISPR 10, 2 /* Priority of interrupt being serviced SV */
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#define PMR 11, 2 /* Interrupt priority masking SV */
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#define ICSR 12, 2 /* Interrupt control status SV */
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#define INTCFG 13, 2 /* Interrupt function setting SV */
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#define MPM 0, 5 /* Memory protection operation mode setting SV */
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#define MPRC 1, 5 /* MPU region control SV */
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#define MPBRGN 4, 5 /* MPU base region number SV */
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#define MPTRGN 5, 5 /* MPU end region number SV */
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#define MCA 8, 5 /* Memory protection setting check address SV */
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#define MCS 9, 5 /* Memory protection setting check size SV */
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#define MCC 10, 5 /* Memory protection setting check command SV */
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#define MCR 11, 5 /* Memory protection setting check result SV */
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#define MPLA0 0, 6 /* Protection area minimum address SV */
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#define MPUA0 1, 6 /* Protection area maximum address SV */
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#define MPAT0 2, 6 /* Protection area attribute SV */
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#define MPLA1 4, 6 /* Protection area minimum address SV */
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#define MPUA1 5, 6 /* Protection area maximum address SV */
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#define MPAT1 6, 6 /* Protection area attribute SV */
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#define MPLA2 8, 6 /* Lower address of the protection area SV */
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#define MPUA2 9, 6 /* Protection area maximum address SV */
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#define MPAT2 10, 6 /* Protection area attribute SV */
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#define MPLA3 12, 6 /* Protection area minimum address SV */
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#define MPUA3 13, 6 /* Protection area maximum address SV */
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#define MPAT3 14, 6 /* Protection area attribute SV */
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#define MPLA4 16, 6 /* Protection area minimum address SV */
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#define MPUA4 17, 6 /* Protection area maximum address SV */
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#define MPAT4 18, 6 /* Protection area attribute SV */
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#define MPLA5 20, 6 /* Protection area minimum address SV */
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#define MPUA5 21, 6 /* Protection area maximum address SV */
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#define MPAT5 22, 6 /* Protection area attribute SV */
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#define MPLA6 24, 6 /* Protection area minimum address SV */
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#define MPUA6 25, 6 /* Protection area maximum address SV */
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#define MPAT6 26, 6 /* Protection area attribute SV */
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#define MLUA7 28, 6 /* Protection area minimum address SV */
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#define MPUA7 29, 6 /* Protection area maximum address SV */
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#define MPAT7 30, 6 /* Protection area attribute SV */
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#endif /* CPU_H_ */
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