/******************************************************************************* * Copyright (c) 2018 Renesas Electronics Corporation. All rights reserved. * * DESCRIPTION : RST register header ******************************************************************************/ #ifndef RST_REGISTER_H_ #define RST_REGISTER_H_ #include #define RST_BASE (BASE_RESET_ADDR) /* 0xE6160000 */ #define RST_WDTRSTCR (RST_BASE + 0x0054U) #define RST_CR7BAR (RST_BASE + 0x0070U) #define RST_CR7BAR_BAREN ((uint32_t)1U << 4) #define WDTRSTCR_PASSWORD (0xA55A0000U) #define WDTRSTCR_RWDT_RSTMSK ((uint32_t)1U << 0U) #define RST_ICUMXBAR (RST_BASE + 0x0078U) #define RST_ICUMXBAR_BAREN ((uint32_t)1U << 4) #define RST_MODEMR (RST_BASE + 0x0060U) /* Mode pin register */ #define RST_MODEMR_A (RST_BASE + 0x0060U) /* Mode pin register for Assembly language */ #define RST_MODEMR2 (RST_BASE + 0x0068U) /* Mode Monitor Register2 */ #define RST_CA57RESCNT (RST_BASE + 0x0040U) /* Reset control register for A57 */ #define RST_CA53RESCNT (RST_BASE + 0x0044U) /* Reset control register for A53 */ #define RST_CA57CPU0BARL (RST_BASE + 0x00C4U) #define RST_CA57CPU0BARH (RST_BASE + 0x00C0U) #define RST_CA53CPU0BARL (RST_BASE + 0x0084U) #define RST_CA53CPU0BARH (RST_BASE + 0x0080U) #define MODEMR_BOOT_CPU_MASK (0x000000C0U) #define MODEMR_BOOT_CPU_CR7 (0x000000C0U) #define MODEMR_BOOT_CPU_CA57 (0x00000000U) #define MODEMR_BOOT_CPU_CA53 (0x00000040U) #define MODEMR_BOOT_DEV_MASK (0x0000001EU) #define MODEMR_BOOT_DEV_HYPERFLASH160 (0x00000004U) #define MODEMR_BOOT_DEV_HYPERFLASH80 (0x00000006U) #define MODEMR_BOOT_DEV_QSPI_FLASH40 (0x00000008U) #define MODEMR_BOOT_DEV_QSPI_FLASH80 (0x0000000CU) #define MODEMR_BOOT_DEV_OCTAL_FLASH (0x0000000EU) #define MODEMR_BOOT_DEV_EMMC_25X1 (0x0000000AU) #define MODEMR_BOOT_DEV_EMMC_50X8 (0x0000001AU) #define MODEMR_BOOT_DEV_SCIF_DOWNLOAD (0x0000001EU) #define MODEMR_BOOT_DEV_USB_DOWNLOAD (0x0000001CU) #endif /* RST_REGISTER_H_ */