/******************************************************************************* * DISCLAIMER * This software is supplied by Renesas Electronics Corporation and is only * intended for use with Renesas products. No other uses are authorized. This * software is owned by Renesas Electronics Corporation and is protected under * all applicable laws, including copyright laws. * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. * Renesas reserves the right, without notice, to make changes to this software * and to discontinue the availability of this software. By using this software, * you agree to the additional terms and conditions found by accessing the * following link: * http://www.renesas.com/disclaimer * Copyright 2021-2024 Renesas Electronics Corporation All rights reserved. *******************************************************************************/ /******************************************************************************* * DESCRIPTION : QoS initialize function ******************************************************************************/ /****************************************************************************** * @file qos.c * - Version : 0.14 * @brief Initial setting process of QoS. * . *****************************************************************************/ /****************************************************************************** * History : DD.MM.YYYY Version Description * : 28.07.2021 0.01 First Release * : 23.05.2022 0.02 Integration of S4 and V4H * Update QoS setting rev.0.02 (for S4) * Update QoS setting rev.0.03 (for V4H) * : 20.01.2023 0.03 Add DBSC W/A 1,2,3 (OTLINT-5579) * : 19.04.2023 0.04 Update the setting version from v6.1 to v7.0(for V4H). * : 22.05.2023 0.05 Update the setting version from v7.0 to v7.1.1(for V4H). * : 22.05.2023 0.06 Update the setting version from v7.1.1 to v8.0.0(for V4H). * : 08.06.2023 0.07 Update the setting version from v8.0.0 to v8.0.1(for V4H). * : 15.06.2023 0.08 Update the setting version from v8.0.1 to v8.0.2(for V4H). * : 21.08.2023 0.09 Add support for V4M. * : 20.09.2023 0.10 Update the setting version from v9.0.1 to v10.0.0(for V4M). * : 20.09.2023 0.11 Update the setting version from v10.0.0 to v10.1.0(for V4H). * : 11.10.2023 0.12 Update the setting version from v10.1.0 to v10.2.1(for V4H/V4M). * : 17.01.2024 0.13 Update the setting version from v10.1.0 to v11.0.0(for V4H/V4M). * : 05.04.2024 0.14 Update the setting version from v11.0.0 to v12.0.0(for V4H/V4M). *****************************************************************************/ #include #if defined(__RH850G3K__) #include #include #include #else #include #include #endif #include #include #include #include #if (RCAR_LSI == RCAR_S4) #define RCAR_QOS_VERSION "base_v6.1" #elif ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M)) #define RCAR_QOS_VERSION "v12.0.0" #endif /* RCAR_LSI == RCAR_S4 */ #define RCAR_DRAM_SPLIT_DISABLE (0U) #define RCAR_DRAM_SPLIT_ENABLE (1U) #define RCAR_REWT_TRAINING_DISABLE (0U) #define RCAR_REWT_TRAINING_ENABLE (1U) #if defined(__RH850G3K__) #define AXMM_BASE (BASE_AXMM_ADDR) #else #define AXMM_BASE (0xE6780000U) #endif #define AXMM_MMCR (AXMM_BASE + 0x4300U) #define AXMM_ADSPLCR0 (AXMM_BASE + 0x4008U) #define AXMM_ADSPLCR1 (AXMM_BASE + 0x400CU) #define AXMM_ADSPLCR2 (AXMM_BASE + 0x4010U) #define AXMM_ADSPLCR3 (AXMM_BASE + 0x4014U) #define AXMM_TR3CR (AXMM_BASE + 0x5100CU) #if (RCAR_LSI == RCAR_S4) #if defined(__RH850G3K__) #define DBSC_BASE (BASE_DBSC_ADDR) #else #define DBSC_BASE (0xE6790000U) #endif #define DBSC_CH_NUM (1U) /* Number of DBSCx */ #define DBSC_A_CH_OFFSET (0U) /* 1ch only (for S4)*/ #define DBSC_D_CH_OFFSET (0U) /* 1ch only (for S4)*/ #define DBSC_SYSCNT0 (DBSC_BASE + 0x0100U) #define DBSC_SYSCNT0A (DBSC_BASE + 0x0108U) #define DBSC_DBBUS0CNF2 (DBSC_BASE + 0x0808U) #define DBSC_DBCAM0CNF1 (DBSC_BASE + 0x0904U) #define DBSC_DBCAM0CNF2 (DBSC_BASE + 0x0908U) #define DBSC_DBCAM0CNF3 (DBSC_BASE + 0x090CU) #define DBSC_DBCAMDIS (DBSC_BASE + 0x09FCU) #define DBSC_DBSCHCNT0 (DBSC_BASE + 0x1000U) #define DBSC_DBSCHSZ0 (DBSC_BASE + 0x1010U) #define DBSC_DBSCHRW0 (DBSC_BASE + 0x1020U) #define DBSC_DBSCHQOS_0_0 (DBSC_BASE + 0x1030U) #define DBSC_DBSCHQOS_0_1 (DBSC_BASE + 0x1034U) #define DBSC_DBSCHQOS_0_2 (DBSC_BASE + 0x1038U) #define DBSC_DBSCHQOS_0_3 (DBSC_BASE + 0x103CU) #define DBSC_DBSCHQOS_4_0 (DBSC_BASE + 0x1070U) #define DBSC_DBSCHQOS_4_1 (DBSC_BASE + 0x1074U) #define DBSC_DBSCHQOS_4_2 (DBSC_BASE + 0x1078U) #define DBSC_DBSCHQOS_4_3 (DBSC_BASE + 0x107CU) #define DBSC_DBSCHQOS_9_0 (DBSC_BASE + 0x10C0U) #define DBSC_DBSCHQOS_9_1 (DBSC_BASE + 0x10C4U) #define DBSC_DBSCHQOS_9_2 (DBSC_BASE + 0x10C8U) #define DBSC_DBSCHQOS_9_3 (DBSC_BASE + 0x10CCU) #define DBSC_DBSCHQOS_12_0 (DBSC_BASE + 0x10F0U) #define DBSC_DBSCHQOS_12_1 (DBSC_BASE + 0x10F4U) #define DBSC_DBSCHQOS_12_2 (DBSC_BASE + 0x10F8U) #define DBSC_DBSCHQOS_12_3 (DBSC_BASE + 0x10FCU) #define DBSC_DBSCHQOS_13_0 (DBSC_BASE + 0x1100U) #define DBSC_DBSCHQOS_13_1 (DBSC_BASE + 0x1104U) #define DBSC_DBSCHQOS_13_2 (DBSC_BASE + 0x1108U) #define DBSC_DBSCHQOS_13_3 (DBSC_BASE + 0x110CU) #define DBSC_DBSCHQOS_14_0 (DBSC_BASE + 0x1110U) #define DBSC_DBSCHQOS_14_1 (DBSC_BASE + 0x1114U) #define DBSC_DBSCHQOS_14_2 (DBSC_BASE + 0x1118U) #define DBSC_DBSCHQOS_14_3 (DBSC_BASE + 0x111CU) #define DBSC_DBSCHQOS_15_0 (DBSC_BASE + 0x1120U) #define DBSC_DBSCHQOS_15_1 (DBSC_BASE + 0x1124U) #define DBSC_DBSCHQOS_15_2 (DBSC_BASE + 0x1128U) #define DBSC_DBSCHQOS_15_3 (DBSC_BASE + 0x112CU) #define DBSC_SCFCTST2 (DBSC_BASE + 0x170CU) #elif ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M)) #if defined(__RH850G3K__) #define DBSC_D_BASE (BASE_DBSC_ADDR + 0x14000U) #define DBSC_A_BASE (BASE_DBSC_ADDR) #else #define DBSC_D_BASE (0xE67A4000U) #define DBSC_A_BASE (0xE6790000U) #endif #if (RCAR_LSI == RCAR_V4H) #define DBSC_CH_NUM (2U) /* ch number of DBSCx */ #elif (RCAR_LSI == RCAR_V4M) #define DBSC_CH_NUM (1U) /* ch number of DBSCx */ #endif #define DBSC_A_CH_OFFSET (0x8000U) #define DBSC_D_CH_OFFSET (0x4000U) #define DBSC_SYSCNT0 (DBSC_D_BASE + 0x0100U) #define DBSC_SYSCNT1 (DBSC_A_BASE + 0x0104U) #define DBSC_SYSCNT0A (DBSC_A_BASE + 0x0100U) #define DBSC_DBBUS0CNF2 (DBSC_A_BASE + 0x0808U) #define DBSC_DBCAM0CNF1 (DBSC_A_BASE + 0x0904U) #define DBSC_DBCAM0CNF2 (DBSC_A_BASE + 0x0908U) #define DBSC_DBCAMDIS (DBSC_A_BASE + 0x09FCU) #define DBSC_DBCAM0CNF3 (DBSC_A_BASE + 0x090CU) #define DBSC_DBSCHCNT0 (DBSC_A_BASE + 0x1000U) #define DBSC_DBSCHSZ0 (DBSC_A_BASE + 0x1010U) #define DBSC_DBSCHRW0 (DBSC_A_BASE + 0x1020U) #define DBSC_DBSCHQOS_0_0 (DBSC_A_BASE + 0x1100U) #define DBSC_DBSCHQOS_0_1 (DBSC_A_BASE + 0x1104U) #define DBSC_DBSCHQOS_0_2 (DBSC_A_BASE + 0x1108U) #define DBSC_DBSCHQOS_0_3 (DBSC_A_BASE + 0x110CU) #define DBSC_DBSCHQOS_4_0 (DBSC_A_BASE + 0x1140U) #define DBSC_DBSCHQOS_4_1 (DBSC_A_BASE + 0x1144U) #define DBSC_DBSCHQOS_4_2 (DBSC_A_BASE + 0x1148U) #define DBSC_DBSCHQOS_4_3 (DBSC_A_BASE + 0x114CU) #define DBSC_DBSCHQOS_9_0 (DBSC_A_BASE + 0x1190U) #define DBSC_DBSCHQOS_9_1 (DBSC_A_BASE + 0x1194U) #define DBSC_DBSCHQOS_9_2 (DBSC_A_BASE + 0x1198U) #define DBSC_DBSCHQOS_9_3 (DBSC_A_BASE + 0x119CU) #define DBSC_DBSCHQOS_12_0 (DBSC_A_BASE + 0x11C0U) #define DBSC_DBSCHQOS_12_1 (DBSC_A_BASE + 0x11C4U) #define DBSC_DBSCHQOS_12_2 (DBSC_A_BASE + 0x11C8U) #define DBSC_DBSCHQOS_12_3 (DBSC_A_BASE + 0x11CCU) #define DBSC_DBSCHQOS_13_0 (DBSC_A_BASE + 0x11D0U) #define DBSC_DBSCHQOS_13_1 (DBSC_A_BASE + 0x11D4U) #define DBSC_DBSCHQOS_13_2 (DBSC_A_BASE + 0x11D8U) #define DBSC_DBSCHQOS_13_3 (DBSC_A_BASE + 0x11DCU) #define DBSC_DBSCHQOS_14_0 (DBSC_A_BASE + 0x11E0U) #define DBSC_DBSCHQOS_14_1 (DBSC_A_BASE + 0x11E4U) #define DBSC_DBSCHQOS_14_2 (DBSC_A_BASE + 0x11E8U) #define DBSC_DBSCHQOS_14_3 (DBSC_A_BASE + 0x11ECU) #define DBSC_DBSCHQOS_15_0 (DBSC_A_BASE + 0x11F0U) #define DBSC_DBSCHQOS_15_1 (DBSC_A_BASE + 0x11F4U) #define DBSC_DBSCHQOS_15_2 (DBSC_A_BASE + 0x11F8U) #define DBSC_DBSCHQOS_15_3 (DBSC_A_BASE + 0x11FCU) #define DBSC_SCFCTST2 (DBSC_A_BASE + 0x1048U) #define AXMM_TR0CR0 (AXMM_BASE + 0x51000U) #define AXMM_TR1CR0 (AXMM_BASE + 0x51004U) #define AXMM_TR2CR0 (AXMM_BASE + 0x51008U) #define AXMM_TR3CR0 (AXMM_BASE + 0x5100CU) #define AXMM_TR0CR1 (AXMM_BASE + 0x51100U) #define AXMM_TR1CR1 (AXMM_BASE + 0x51104U) #define AXMM_TR2CR1 (AXMM_BASE + 0x51108U) #define AXMM_TR3CR1 (AXMM_BASE + 0x5110CU) #define AXMM_TR0CR2 (AXMM_BASE + 0x51200U) #define AXMM_TR1CR2 (AXMM_BASE + 0x51204U) #define AXMM_TR2CR2 (AXMM_BASE + 0x51208U) #define AXMM_TR3CR2 (AXMM_BASE + 0x5120CU) #define DBSC_FCPRSCTRL (DBSC_A_BASE + 0x0110U) #define ACTEXT_RT0_R (0xFFC50800U) #define ACTEXT_RT0_W (0xFFC51800U) #define ACTEXT_IR0_R (0xFF890800U) #define ACTEXT_IR0_W (0xFF891800U) #define ACTEXT_IR1_R (0xFF892800U) #define ACTEXT_IR1_W (0xFF893800U) #define SI0_RW_MAX (0xF1201110U) #define SI1_RW_MAX (0xF1202110U) #endif /* RCAR_LSI == RCAR_S4 */ #if defined(__RH850G3K__) #define QOS_BASE (BASE_QOS_ADDR) #else #define QOS_BASE (0xE67E0000U) #endif #define QOS_FIX_QOS_BANK0 (QOS_BASE + 0x00000000U) #define QOS_FIX_QOS_BANK1 (QOS_BASE + 0x00001000U) #define QOS_BE_QOS_BANK0 (QOS_BASE + 0x00002000U) #define QOS_BE_QOS_BANK1 (QOS_BASE + 0x00003000U) #define QOS_SL_INIT (QOS_BASE + 0x00008000U) #define QOS_REF_ARS (QOS_BASE + 0x00008004U) #define QOS_STATQC (QOS_BASE + 0x00008008U) #define QOS_REF_ENBL (QOS_BASE + 0x00008044U) #define QOS_BWG (QOS_BASE + 0x0000804CU) #if RCAR_PERIODIC_WRITE_TRAINING != RCAR_REWT_TRAINING_DISABLE #define QOSWT_FIX_QOS_BANK0 (QOS_BASE + 0x00000800U) #define QOSWT_FIX_QOS_BANK1 (QOS_BASE + 0x00001800U) #define QOSWT_BE_QOS_BANK0 (QOS_BASE + 0x00002800U) #define QOSWT_BE_QOS_BANK1 (QOS_BASE + 0x00003800U) #define QOSWT_WTEN (QOS_BASE + 0x00008030U) #define QOSWT_WTREF (QOS_BASE + 0x00008034U) #define QOSWT_WTSET0 (QOS_BASE + 0x00008038U) #define QOSWT_WTSET1 (QOS_BASE + 0x0000803CU) #endif /* RCAR_PERIODIC_WRITE_TRAINING != RCAR_REWT_TRAINING_DISABLE */ #define QOS_RAS (QOS_BASE + 0x00010000U) #define QOS_RAEN (QOS_BASE + 0x00010018U) #define QOS_DANN_LOW (QOS_BASE + 0x00010030U) #define QOS_DANN_HIGH (QOS_BASE + 0x00010034U) #define QOS_DANT (QOS_BASE + 0x00010038U) #define QOS_EMS_LOW (QOS_BASE + 0x00010040U) #define QOS_EMS_HIGH (QOS_BASE + 0x00010044U) #define QOS_FSS (QOS_BASE + 0x00010048U) #define QOS_INSFC (QOS_BASE + 0x00010050U) #define QOS_EARLYR (QOS_BASE + 0x00010060U) #define QOS_RACNT0 (QOS_BASE + 0x00010080U) #define QOS_STATGEN0 (QOS_BASE + 0x00010088U) #define CCI_BASE (BASE_CCI_ADDR) #define CCIQOS00 (CCI_BASE + 0xC020U) #define CCIQOS01 (CCI_BASE + 0xC024U) #define CCIQOS10 (CCI_BASE + 0xD000U) #define CCIQOS11 (CCI_BASE + 0xD004U) #if (RCAR_LSI == RCAR_S4) #define CCIQOS12 (CCI_BASE + 0xD008U) #define CCIQOS13 (CCI_BASE + 0xD00CU) #endif static void dbsc_setting(void) { for(uint32_t loop = 0; loop < DBSC_CH_NUM; loop++) { /* DBSC CAM, Scheduling Setting */ mem_write32((DBSC_SYSCNT0 + (DBSC_D_CH_OFFSET * loop)), 0x00001234U); mem_write32((DBSC_SYSCNT0A + (DBSC_A_CH_OFFSET * loop)), 0x00001234U); mem_write32((DBSC_DBCAM0CNF1 + (DBSC_A_CH_OFFSET * loop)), 0x00048218U); /* dbcam0cnf1 */ #if ((ECC_ENABLE == 1) && (RCAR_LSI == RCAR_V4H)) /* For WA for DBSC5 Hang5 issue. */ if ((mem_read32(PRR) & PRR_CUT_MASK) <= PRR_PRODUCT_21) { mem_write32((DBSC_DBCAM0CNF2 + (DBSC_A_CH_OFFSET * loop)), 0x000002C4U); /* dbcam0cnf2 */ } else { mem_write32((DBSC_DBCAM0CNF2 + (DBSC_A_CH_OFFSET * loop)), 0x000001C4U); /* dbcam0cnf2 */ } #elif (RCAR_LSI == RCAR_V4M) mem_write32((DBSC_DBCAM0CNF2 + (DBSC_A_CH_OFFSET * loop)), 0x000001C4U); /* dbcam0cnf2 */ #else mem_write32((DBSC_DBCAM0CNF2 + (DBSC_A_CH_OFFSET * loop)), 0x000001C4U); /* dbcam0cnf2 */ #endif mem_write32((DBSC_DBCAM0CNF3 + (DBSC_A_CH_OFFSET * loop)), 0x00000003U); /* dbcam0cnf3 */ #if (RCAR_LSI == RCAR_S4) #if ((WA_OTLINT5579 == 1) && (ECC_ENABLE == 1)) mem_write32((DBSC_DBCAMDIS + (DBSC_A_CH_OFFSET * loop)), 0x00000002U); /* OTLINT-5579: V4H DBSC W/A-1,2 */ #else mem_write32((DBSC_DBCAMDIS + (DBSC_A_CH_OFFSET * loop)), 0x00000000U); #endif #elif (RCAR_LSI == RCAR_V4H) #if ((WA_OTLINT5579 == 1) && (ECC_ENABLE == 1)) if((mem_read32(PRR) & PRR_CUT_MASK) <= PRR_PRODUCT_21) { mem_write32((DBSC_DBCAMDIS + (DBSC_A_CH_OFFSET * loop)), 0x00000013U); /* OTLINT-5579: V4H DBSC W/A-1,2,3 */ } else if((mem_read32(PRR) & PRR_CUT_MASK) == PRR_PRODUCT_22) { mem_write32((DBSC_DBCAMDIS + (DBSC_A_CH_OFFSET * loop)), 0x00000012U); } else { mem_write32((DBSC_DBCAMDIS + (DBSC_A_CH_OFFSET * loop)), 0x00000010U); } #elif ((WA_OTLINT5579 == 1) && (ECC_ENABLE == 0)) if((mem_read32(PRR) & PRR_CUT_MASK) <= PRR_PRODUCT_21) { mem_write32((DBSC_DBCAMDIS + (DBSC_A_CH_OFFSET * loop)), 0x00000011U); /* OTLINT-5579: V4H DBSC W/A-3 */ } else { mem_write32((DBSC_DBCAMDIS + (DBSC_A_CH_OFFSET * loop)), 0x00000010U); } #else mem_write32((DBSC_DBCAMDIS + (DBSC_A_CH_OFFSET * loop)), 0x00000010U); #endif #elif (RCAR_LSI == RCAR_V4M) # if (ECC_ENABLE == 1) mem_write32((DBSC_DBCAMDIS + (DBSC_A_CH_OFFSET * loop)), 0x00000012U); #else mem_write32((DBSC_DBCAMDIS + (DBSC_A_CH_OFFSET * loop)), 0x00000010U); # endif #endif mem_write32((DBSC_DBSCHCNT0 + (DBSC_A_CH_OFFSET * loop)), 0x000F0037U); /* dbschcnt0 */ mem_write32((DBSC_DBSCHSZ0 + (DBSC_A_CH_OFFSET * loop)), 0x00000001U); /* dbschsz0 */ mem_write32((DBSC_DBSCHRW0 + (DBSC_A_CH_OFFSET * loop)), 0xF7311111U); /* dbschrw0 */ mem_write32((DBSC_SCFCTST2 + (DBSC_A_CH_OFFSET * loop)), 0x111F1FFFU); #if (((RCAR_LSI == RCAR_V4H) && (WA_OTLINT5579 == 1)) || (RCAR_LSI == RCAR_V4M)) mem_write32((DBSC_DBBUS0CNF2 + (DBSC_A_CH_OFFSET * loop)), 0x00000007U); /* OTLINT-5579: V4H DBSC WA3 */ #else mem_write32((DBSC_DBBUS0CNF2 + (DBSC_A_CH_OFFSET * loop)), 0x00000003U); /* S4, V4H w/o DBSC WA3 */ #endif /* DBSC QoS Setting */ mem_write32((DBSC_DBSCHQOS_0_0 + (DBSC_A_CH_OFFSET * loop)), 0x0000FFFFU); mem_write32((DBSC_DBSCHQOS_0_1 + (DBSC_A_CH_OFFSET * loop)), 0x00000480U); mem_write32((DBSC_DBSCHQOS_0_2 + (DBSC_A_CH_OFFSET * loop)), 0x00000300U); mem_write32((DBSC_DBSCHQOS_0_3 + (DBSC_A_CH_OFFSET * loop)), 0x00000180U); mem_write32((DBSC_DBSCHQOS_4_0 + (DBSC_A_CH_OFFSET * loop)), 0x00000400U); mem_write32((DBSC_DBSCHQOS_4_1 + (DBSC_A_CH_OFFSET * loop)), 0x00000300U); mem_write32((DBSC_DBSCHQOS_4_2 + (DBSC_A_CH_OFFSET * loop)), 0x00000200U); mem_write32((DBSC_DBSCHQOS_4_3 + (DBSC_A_CH_OFFSET * loop)), 0x00000100U); mem_write32((DBSC_DBSCHQOS_9_0 + (DBSC_A_CH_OFFSET * loop)), 0x00000300U); mem_write32((DBSC_DBSCHQOS_9_1 + (DBSC_A_CH_OFFSET * loop)), 0x00000240U); mem_write32((DBSC_DBSCHQOS_9_2 + (DBSC_A_CH_OFFSET * loop)), 0x00000180U); mem_write32((DBSC_DBSCHQOS_9_3 + (DBSC_A_CH_OFFSET * loop)), 0x000000C0U); mem_write32((DBSC_DBSCHQOS_12_0 + (DBSC_A_CH_OFFSET * loop)), 0x00000040U); mem_write32((DBSC_DBSCHQOS_12_1 + (DBSC_A_CH_OFFSET * loop)), 0x00000030U); mem_write32((DBSC_DBSCHQOS_12_2 + (DBSC_A_CH_OFFSET * loop)), 0x00000020U); mem_write32((DBSC_DBSCHQOS_12_3 + (DBSC_A_CH_OFFSET * loop)), 0x00000010U); mem_write32((DBSC_DBSCHQOS_13_0 + (DBSC_A_CH_OFFSET * loop)), 0x00000300U); mem_write32((DBSC_DBSCHQOS_13_1 + (DBSC_A_CH_OFFSET * loop)), 0x00000240U); mem_write32((DBSC_DBSCHQOS_13_2 + (DBSC_A_CH_OFFSET * loop)), 0x00000180U); mem_write32((DBSC_DBSCHQOS_13_3 + (DBSC_A_CH_OFFSET * loop)), 0x000000C0U); mem_write32((DBSC_DBSCHQOS_14_0 + (DBSC_A_CH_OFFSET * loop)), 0x00000200U); mem_write32((DBSC_DBSCHQOS_14_1 + (DBSC_A_CH_OFFSET * loop)), 0x00000180U); mem_write32((DBSC_DBSCHQOS_14_2 + (DBSC_A_CH_OFFSET * loop)), 0x00000100U); mem_write32((DBSC_DBSCHQOS_14_3 + (DBSC_A_CH_OFFSET * loop)), 0x00000080U); mem_write32((DBSC_DBSCHQOS_15_0 + (DBSC_A_CH_OFFSET * loop)), 0x00000100U); mem_write32((DBSC_DBSCHQOS_15_1 + (DBSC_A_CH_OFFSET * loop)), 0x000000C0U); mem_write32((DBSC_DBSCHQOS_15_2 + (DBSC_A_CH_OFFSET * loop)), 0x00000080U); mem_write32((DBSC_DBSCHQOS_15_3 + (DBSC_A_CH_OFFSET * loop)), 0x00000040U); if (loop == 0) /* Target register is only DBSC0 side. */ { mem_write32(DBSC_FCPRSCTRL, 0x00000001U); } mem_write32((DBSC_SYSCNT1 + (DBSC_A_CH_OFFSET * loop)), 0x00000001U); mem_write32((DBSC_SYSCNT0 + (DBSC_D_CH_OFFSET * loop)), 0x00000000U); mem_write32((DBSC_SYSCNT0A + (DBSC_A_CH_OFFSET * loop)), 0x00000000U); } } /* End of function dbsc_setting(void) */ void qos_init(void) { uint32_t i; /* Setting the register of DBSC4 for QoS initialize */ dbsc_setting(); NOTICE("QoS setting(%s)\n", RCAR_QOS_VERSION); NOTICE("DRAM refresh interval 1.91 usec\n"); #if RCAR_PERIODIC_WRITE_TRAINING != RCAR_REWT_TRAINING_DISABLE NOTICE("Periodic Write DQ Training\n"); #endif /* RCAR_PERIODIC_WRITE_TRAINING != RCAR_REWT_TRAINING_DISABLE */ #if (RCAR_LSI == RCAR_S4) /* Resource Alloc setting */ mem_write32(QOS_RAS, 0x00000028U); mem_write32(QOS_DANN_LOW, 0x02020201U); mem_write32(QOS_DANN_HIGH, 0x04040200U); mem_write32(QOS_DANT, 0x00181004U); mem_write32(QOS_EMS_LOW, 0x00000000U); mem_write32(QOS_EMS_HIGH, 0x00000000U); mem_write32(QOS_FSS, 0x0000000AU); mem_write32(QOS_INSFC, 0x030F0001U); mem_write32(QOS_EARLYR, 0x00000000U); mem_write32(QOS_RACNT0, 0x00050003U); mem_write32(QOS_STATGEN0, 0x00000000U); /* QoS MSTAT setting */ mem_write32(QOS_SL_INIT, 0x00050100U); mem_write32(QOS_REF_ARS, 0x00FB0000U); mem_write32(QOS_REF_ENBL, 0x00000012U); mem_write32(QOS_BWG, 0x00000002U); mem_write32(AXMM_MMCR, 0x00010000U); mem_write32(CCIQOS00, 0x08000000); mem_write32(CCIQOS01, 0x08000000); mem_write32(CCIQOS10, 0x00000001); mem_write32(CCIQOS11, 0x00000001); mem_write32(CCIQOS12, 0x00000001); mem_write32(CCIQOS13, 0x00000001); #elif ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M)) #if (RCAR_LSI == RCAR_V4H) #if (RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_ENABLE) /* Address Split 2ch */ mem_write32(AXMM_ADSPLCR0, 0x00000000U); mem_write32(AXMM_ADSPLCR1, 0x00FF1B0CU); mem_write32(AXMM_ADSPLCR2, 0x00000000U); mem_write32(AXMM_ADSPLCR3, 0x00000000U); #endif #endif #if (RCAR_LSI == RCAR_V4H) mem_write32(CCIQOS00, 0x08000000); mem_write32(CCIQOS01, 0x08000000); if ((mem_read32(PRR) & PRR_CUT_MASK) >= PRR_PRODUCT_20) { mem_write32(CCIQOS10, 0x00000001U); mem_write32(CCIQOS11, 0x00000001U); } else { mem_write32(CCIQOS10, 0x00000000U); mem_write32(CCIQOS11, 0x00000000U); } #endif /* Resource Alloc setting */ #if (RCAR_LSI == RCAR_V4H) mem_write32(QOS_RAS, 0x00000048U); #elif (RCAR_LSI == RCAR_V4M) mem_write32(QOS_RAS, 0x00000030U); #endif mem_write32(QOS_DANN_LOW, 0x02020201U); mem_write32(QOS_DANN_HIGH, 0x04040200U); mem_write32(QOS_DANT, 0x00181008U); mem_write32(QOS_EMS_LOW, 0x00000000U); mem_write32(QOS_EMS_HIGH, 0x00000000U); mem_write32(QOS_FSS, 0x0000000AU); mem_write32(QOS_INSFC, 0x030F0001U); mem_write32(QOS_EARLYR, 0x00000000U); mem_write32(QOS_RACNT0, 0x00050003U); mem_write32(QOS_STATGEN0, 0x00000000U); /* QoS MSTAT setting */ mem_write32(QOS_SL_INIT, 0x00070120U); mem_write32(QOS_REF_ARS, 0x011B0000U); mem_write32(QOS_REF_ENBL, 0x00000012U); mem_write32(QOS_BWG, 0x00000004U); #if ((RCAR_LSI == RCAR_V4H) && (WA_OTLINT5579 == 1)) if ((mem_read32(PRR) & PRR_CUT_MASK) <= PRR_PRODUCT_21) { mem_write32(AXMM_MMCR, 0x00000000U); /* OTLINT-5579: V4H DBSC WA3 */ } else { mem_write32(AXMM_MMCR, 0x00010000U); /* OTLINT-5579: V4H DBSC WA3 */ } #elif (RCAR_LSI == RCAR_V4M) mem_write32(AXMM_MMCR, 0x00010000U); #else mem_write32(AXMM_MMCR, 0x00010000U); #endif mem_write32(ACTEXT_RT0_R, 0x00000003U); mem_write32(ACTEXT_RT0_W, 0x00000003U); mem_write32(ACTEXT_IR0_R, 0x00000003U); mem_write32(ACTEXT_IR0_W, 0x00000003U); mem_write32(ACTEXT_IR1_R, 0x00000003U); mem_write32(ACTEXT_IR1_W, 0x00000003U); #if (RCAR_LSI == RCAR_V4H) mem_write32(AXMM_TR3CR, 0x00010000U); #endif #if (RCAR_LSI == RCAR_V4M) mem_write32(AXMM_TR0CR0, 0x00000000U); mem_write32(AXMM_TR1CR0, 0x00000000U); mem_write32(AXMM_TR2CR0, 0x00000000U); mem_write32(AXMM_TR3CR0, 0x00000000U); mem_write32(AXMM_TR0CR1, 0x70707070U); mem_write32(AXMM_TR1CR1, 0x70707070U); mem_write32(AXMM_TR2CR1, 0x70707070U); mem_write32(AXMM_TR3CR1, 0x70707070U); mem_write32(AXMM_TR0CR2, 0x70707070U); mem_write32(AXMM_TR1CR2, 0x70707070U); mem_write32(AXMM_TR2CR2, 0x70707070U); mem_write32(AXMM_TR3CR2, 0x70707070U); #endif #if (RCAR_LSI == RCAR_V4H) if ((mem_read32(PRR) & PRR_CUT_MASK) >= PRR_PRODUCT_20) { /* WA1 patch for IPL CA76 hang-up issue, REL_TRI_DN-7592 */ mem_write32(SI0_RW_MAX, 0x00000038U); mem_write32(SI1_RW_MAX, 0x00000038U); } #endif #endif /* RCAR_LSI == RCAR_S4 */ for (i = 0U; i < QOS_TBL_MAX; i++) { mem_write64((QOS_FIX_QOS_BANK0 + (i * 8U)), g_qosbw_tbl[i].fix); mem_write64((QOS_FIX_QOS_BANK1 + (i * 8U)), g_qosbw_tbl[i].fix); mem_write64((QOS_BE_QOS_BANK0 + (i * 8U)), g_qosbw_tbl[i].be); mem_write64((QOS_BE_QOS_BANK1 + (i * 8U)), g_qosbw_tbl[i].be); } #if RCAR_PERIODIC_WRITE_TRAINING != RCAR_REWT_TRAINING_DISABLE for (i = 0U; i < QOS_TBL_MAX; i++) { mem_write64((QOSWT_FIX_QOS_BANK0 + (i * 8U)), g_qoswt_tbl[i].fix); mem_write64((QOSWT_FIX_QOS_BANK1 + (i * 8U)), g_qoswt_tbl[i].fix); mem_write64((QOSWT_BE_QOS_BANK0 + (i * 8U)), g_qoswt_tbl[i].be); mem_write64((QOSWT_BE_QOS_BANK1 + (i * 8U)), g_qoswt_tbl[i].be); } #endif /* RCAR_PERIODIC_WRITE_TRAINING != RCAR_REWT_TRAINING_DISABLE */ /* QoS SRAM setting */ mem_write32(QOS_RAEN, 0x00000001U); #if RCAR_PERIODIC_WRITE_TRAINING != RCAR_REWT_TRAINING_DISABLE mem_write32(QOSWT_WTREF, 0x02080208U); mem_write32(QOSWT_WTSET0, 0x0D90050FU); mem_write32(QOSWT_WTSET1, 0x0D90050FU); mem_write32(QOSWT_WTEN, 0x00000001U); #endif /* RCAR_PERIODIC_WRITE_TRAINING != RCAR_REWT_TRAINING_DISABLE */ mem_write32(QOS_STATQC, 0x00000101U); } /* End of function qos_init(void) */