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/*******************************************************************************
 * DESCRIPTION   : HSCIF register header
 ******************************************************************************/
/******************************************************************************
 * @file          hscif_register.h
 * - Version      : 0.02
 * @brief         
 * .
 *****************************************************************************/
/******************************************************************************
 * History : DD.MM.YYYY Version  Description
 *         : 02.02.2022 0.01     First Release
 *         : 31.10.2022 0.02     License notation change.
 *****************************************************************************/

#ifndef HSCIF_REGISTER_H_
#define HSCIF_REGISTER_H_

#include <rcar_register.h>

/* HSCIF0 base address */
/* 0xE6540000U */
#define HSCIF0_BASE     (BASE_HSCIF_ADDR)

#define HSCIF_HSSMR     (HSCIF0_BASE + 0x0000U) /*  16  Serial mode register */
#define HSCIF_HSBRR     (HSCIF0_BASE + 0x0004U) /*  8   Bit rate register */
#define HSCIF_HSSCR     (HSCIF0_BASE + 0x0008U) /*  16  Serial control register */
#define HSCIF_HSFTDR    (HSCIF0_BASE + 0x000CU) /*  8   Transmit FIFO data register */
#define HSCIF_HSFSR     (HSCIF0_BASE + 0x0010U) /*  16  Serial status register */
#define HSCIF_HSFCR     (HSCIF0_BASE + 0x0018U) /*  16  FIFO control register */
#define HSCIF_HSLSR     (HSCIF0_BASE + 0x0024U) /*  16  Line status register */
#define HSCIF_DL        (HSCIF0_BASE + 0x0030U) /*  16  Frequency division register */
#define HSCIF_CKS       (HSCIF0_BASE + 0x0034U) /*  16  Clock Select register */
#define HSCIF_HSSRR     (HSCIF0_BASE + 0x0040U) /*  16  Sampling rate register */

#endif /* HSCIF_REGISTER_H_ */