diff --git a/Gen4_ICUMX_Loader/dos.mk b/Gen4_ICUMX_Loader/dos.mk
index 9ec4e05..ca8e2a5 100644
--- a/Gen4_ICUMX_Loader/dos.mk
+++ b/Gen4_ICUMX_Loader/dos.mk
@@ -86,12 +86,6 @@ else
 endif
 $(eval $(call add_define,RCAR_LSI))
 
-#/* PRK3 board revision ("0" for EVB, other for PRK3) ***********************
-ifeq ("$(PRK3)", "")
-PRK3 = 0
-endif
-$(eval $(call add_define,PRK3))
-
 # timing measurement
 ifeq ("$(MEASURE_TIME)", "")
     MEASURE_TIME = 0
@@ -363,6 +357,7 @@ OBJ_FILE    +=  image_load/image_load_flash.o   \
                 ip/dma/dma.o                    \
                 ip/rpc/rpc.o                    \
                 ip/rpc/qspi_xdr_mode.o          \
+                ip/rpc/dma2.o                   \
                 ip/rpc/rpcqspidrv.o             \
                 ip/rpc/spiflash2drv.o           \
                 ip/mfis/mfis.o
diff --git a/Gen4_ICUMX_Loader/env.ini b/Gen4_ICUMX_Loader/env.ini
index 9032153..dd0a92b 100644
--- a/Gen4_ICUMX_Loader/env.ini
+++ b/Gen4_ICUMX_Loader/env.ini
@@ -4,5 +4,4 @@ OPTEE_LOAD_ENABLE=1 \
 BL2_LOAD_ENABLE=1 \
 QNX_OS_LOAD_ENABLE=1 \
 STACK_PROTECT=1 \
-PRK3=4 \
 "
diff --git a/Gen4_ICUMX_Loader/include/rpcqspidrv.h b/Gen4_ICUMX_Loader/include/rpcqspidrv.h
index a306dce..769fda0 100644
--- a/Gen4_ICUMX_Loader/include/rpcqspidrv.h
+++ b/Gen4_ICUMX_Loader/include/rpcqspidrv.h
@@ -41,7 +41,7 @@
 #define RPCQSPIDRV_H__
 
 #include <stdint.h>
-// #include "reg_rcar.h"
+#include <bit.h>
 
 #define SPI_IOADDRESS_TOP		0x08000000		/* RPC memory space 0x08000000-0x0BFFFFFF = 64MBytes */
 #define RPC_CLK_40M				0x01
@@ -51,11 +51,7 @@
 #define DEVICE_ID_MASK          (0x00FFFFFFU)
 
 #define RPC_WRITE_BUF_SIZE      (0x100U)        /* 256byte:RPC Write Buffer size */
-#if (PRK3 > 0)
 #define FLASH_SECTOR_SIZE       (0x00010000U)   /* Flash 1sector is 64KiB */
-#else
-#define FLASH_SECTOR_SIZE       (0x00040000U)   /* Flash 1sector is 256KiB */
-#endif
 #define FLASH_SECTOR_MASK       ((~(FLASH_SECTOR_SIZE-1)) & 0xFFFFFFFFU)
 
 #define DRCMR_SMCMR_CMD_SHIFT           (16U)
diff --git a/Gen4_ICUMX_Loader/ip/rpc/rpc.c b/Gen4_ICUMX_Loader/ip/rpc/rpc.c
index 9519c2c..68310af 100644
--- a/Gen4_ICUMX_Loader/ip/rpc/rpc.c
+++ b/Gen4_ICUMX_Loader/ip/rpc/rpc.c
@@ -47,18 +47,17 @@
 
 #include <stdint.h>
 #include <stddef.h>
-#include <rpc.h>
-#include <rpc_register.h>
+#include <remap.h>
 #include <mem_io.h>
 #include <rst_register.h>
-#include <image_load_flash.h>
 #include <cpg_register.h>
 #include <cpg.h>
-#include <remap.h>
-#include <log.h>
-#include <pfc.h>
-#include <bit.h>
+#include <rpc_register.h>
 #include <rpcqspidrv.h>
+#include <rpc.h>
+#include <image_load_flash.h>
+#include <pfc.h>
+#include <log.h>
 
 #define RST_MODEMR0_BOOTMODE            (0xFU << 1U)
 #define BOOTMODE_QSPI_SINGLE_40MHZ      (0x4U)
@@ -145,7 +144,6 @@ static const uint32_t dev_id_index[VENDOR_NUM] =
 };
 
 const st_qspi_cmd_tbl_t* gp_qspi_cmd_tbl;
-uint8_t prk3_rev = 3;
 
 static void rpc_save_hw_init_val(void);
 static uint32_t init_qspi_cmd(uint32_t device_id);
@@ -190,7 +188,6 @@ void qspi_flash_rw_init(void)
             ERROR("QSPI Flash command initialization error!!\n");
             panic;
         }
-      	init_rpc_qspi_flash_4fastread_ext_mode();
 
 #if (QSPI_DDR_MODE==1)
         /* Initialize for QSPI DDR transfer mode */
@@ -253,6 +250,7 @@ static void rpc_save_hw_init_val(void)
     }
 }
 
+uint8_t prk3_rev = 3;
 static uint32_t init_qspi_cmd(uint32_t device_id)
 {
     uint32_t    i = 0U;
diff --git a/Gen4_ICUMX_Loader/ip/rpc/rpcqspidrv.c b/Gen4_ICUMX_Loader/ip/rpc/rpcqspidrv.c
index f4343ce..d4ba398 100644
--- a/Gen4_ICUMX_Loader/ip/rpc/rpcqspidrv.c
+++ b/Gen4_ICUMX_Loader/ip/rpc/rpcqspidrv.c
@@ -44,20 +44,19 @@
  *         : 09.11.2022 0.07     License notation change.
  *****************************************************************************/
 
-// #include "common.h"
 #include <stdint.h>
 #include <stddef.h>
-#include "rpcqspidrv.h"
-// #include "reg_rcar.h"
-#include <rpc_register.h>
+#include <remap.h>
+#include <mem_io.h>
+#include <micro_wait.h>
 #include <cpg_register.h>
-#include "bit.h"
-#include "micro_wait.h"
-#include "remap.h"
-#include "mem_io.h"
-#include "dma.h"
-// #include "qspi_cmd.h"
+#include <rpc_register.h>
+#include <rpcqspidrv.h>
 #include <rpc.h>
+#include <wdt.h>
+#include <log.h>
+
+#include "dma2.h"
 
 static uint32_t read_register_qspi_flash(uint32_t cmd, uint32_t *readData);
 
@@ -371,10 +370,10 @@ void write_data_4pp_with_buf_qspi_flash(uint32_t addr, uint32_t source_addr)
 
 	for(i = 0; i < RPC_WRITE_BUF_SIZE; i = i + TRANS_SIZE_64BYTE)
 	{
-        // dma_start_xbyte(RPC_WRBUF_PHYS+i, source_addr+i, TRANS_SIZE_64BYTE, TRANS_UNIT_64BYTES);
-        dma_trans_start(RPC_WRBUF_PHYS+i, source_addr+i, TRANS_SIZE_64BYTE);
-        // dma_end();
-        dma_trans_end_check();
+		dma2_start_xbyte(RPC_WRBUF_PHYS+i, source_addr+i, TRANS_SIZE_64BYTE, TRANS_UNIT_64BYTES);
+		dma2_end();
+		// dma_trans_start(RPC_WRBUF_PHYS+i, source_addr+i, TRANS_SIZE_64BYTE);
+		// dma_trans_end_check();
 	}
 
     reg =  mem_read32(RPC_CMNCR);
@@ -467,7 +466,6 @@ void write_data_4pp_with_buf_qspi_flash(uint32_t addr, uint32_t source_addr)
 }
 /* End of function write_data_4pp_with_buf_qspi_flash */
 
-#if (PRK3 > 0)
 /* OnBoard QspiFlash(MT25QU01GB) */
 uint32_t read_wip_status_register(uint32_t *readData)	/* for QSPIx1ch */
 {
@@ -554,216 +552,6 @@ void write_status_register(uint16_t stat_conf)
 
 	wait_rpc_tx_end();
 }
-#else   /* PRK3 == 0 */
-/* OnBoard QspiFlash(S25FS128S) */
-/* 65h Read Any Register command (RADR 65h) */
-void read_any_register_qspi_flash(uint32_t addr, unsigned char *readData)		/* Add24bit,Data8bit */
-{
-	uint32_t reg;
-
-	reg = mem_read32(RPC_PHYCNT);
-	reg |= (RPC_PHYCNT_STRTIM3
-			| RPC_PHYCNT_STRTIM2
-			| RPC_PHYCNT_STRTIM1
-			| RPC_PHYCNT_STRTIM0);
-	reg &= ~(RPC_PHYCNT_HS
-			| RPC_PHYCNT_WBUF2
-			| RPC_PHYCNT_WBUF
-			| RPC_PHYCNT_PHYMEM_HYP);
-	mem_write32(RPC_PHYCNT, reg);
-	reg |= RPC_PHYCNT_CAL;
-	mem_write32(RPC_PHYCNT, reg);
-		/* bit31  CAL         =  1 : PHY calibration */
-		/* bit1-0 PHYMEM[1:0] = 00 : QSPI-SDR */
-
-    reg =  mem_read32(RPC_CMNCR);
-    reg &= ~(CMNCR_BSZ_MASK);
-    reg |= (CMNCR_MD_MANUAL
-            | CMNCR_MOIIO3_HIZ
-            | CMNCR_MOIIO2_HIZ
-            | CMNCR_MOIIO1_HIZ
-            | CMNCR_MOIIO0_HIZ
-            | CMNCR_IO0FV_HIZ);
-    mem_write32(RPC_CMNCR, reg);
-		/* bit31  MD       =  1 : Manual mode */
-		/* bit1-0 BSZ[1:0] = 00 : QSPI Flash x 1 */
-
-    reg =  mem_read32(RPC_SMCMR);
-    reg &= ~(SMCMR_CMD_MASK
-            | SMCMR_OCMD_MASK);
-    reg |= ((gp_qspi_cmd_tbl -> read_any_register) << DRCMR_SMCMR_CMD_SHIFT);
-    mem_write32(RPC_SMCMR, reg);
-		/* bit23-16 CMD[7:0] = 0x65 :        Read Any Register command (RADR 65h) */
-
-	mem_write32(RPC_SMADR,  addr);
-
-    reg =  mem_read32(RPC_SMDMCR);
-    reg &= ~(SMDMCR_DMCYC_MASK);
-    reg |= SMDMCR_DMCYC_8;
-    mem_write32(RPC_SMDMCR, reg);
-		/* bit2-0 DMCYC[2:0] = 111 : 8 cycle dummy wait */
-
-    reg =  mem_read32(RPC_SMDRENR);
-    reg &= ~(SMDRENR_HYPE_MASK
-            | SMDRENR_ADDRE
-            | SMDRENR_OPDRE
-            | SMDRENR_SPIDRE);
-    mem_write32(RPC_SMDRENR, reg);
-		/* bit8 ADDRE  = 0 : Address SDR transfer */
-		/* bit0 SPIDRE = 0 : DATA SDR transfer */
-
-    reg =  mem_read32(RPC_SMENR);
-    reg &= ~(SMENR_CDB_MASK
-            | SMENR_OCDB_MASK
-            | SMENR_ADB_MASK
-            | SMENR_OPDB_MASK
-            | SMENR_SPIDB_MASK
-            | SMENR_OCDE_EN
-            | SMENR_ADE_MASK
-            | SMENR_OPDE_MASK
-            | SMENR_SPIDE_MASK);
-    reg |= (SMENR_DME_EN
-            | SMENR_CDE_EN
-            | SMENR_ADE_SERIAL_23
-            | SMENR_SPIDE_SPI_8);
-    mem_write32(RPC_SMENR, reg);
-		/* bit31-30 CDB[1:0]   =   00 : 1bit width command (QSPI0_MOSI) */
-		/* bit25-24 ADB[1:0]   =   00 : 1bit width address (QSPI0_MOSI) */
-		/* bit17-16 SPIDB[1:0] =   00 : 1bit width transfer data (QSPI0_MISO) */
-		/* bit15    DME        =    1 : dummy cycle enable */
-		/* bit14    CDE        =    1 : Command enable */
-		/* bit11-8  ADE[3:0]   = 0111 : ADR[23:0] output (24 Bit Address) */
-		/* bit3-0   SPIDE[3:0] = 1000 : 8bit transfer */
-
-    reg =  mem_read32(RPC_SMCR);
-    reg &= ~(SMCR_SSLKP
-            | SMCR_SPIWE);
-    reg |= (SMCR_SPIRE
-            | SMCR_SPIE);
-    mem_write32(RPC_SMCR, reg);
-		/* bit2     SPIRE      = 1 : Data read enable */
-		/* bit1     SPIWE      = 0 : Data write disable */
-		/* bit0     SPIE       = 1 : SPI transfer start */
-
-	wait_rpc_tx_end();
-
-	*readData   = mem_read8(RPC_SMRDR0);	/* read data[7:0] */
-}
-/* End of function read_any_register_qspi_flash */
-
-/* OnBoard QspiFlash(S25FS128S) */
-/* 71h Write Any Register command (WRAR 71h) */
-void write_any_register_qspi_flash(uint32_t addr, unsigned char writeData)			/* Add24bit,Data8bit */
-{
-	uint32_t reg;
-
-	reg = mem_read32(RPC_PHYCNT);
-	reg |= (RPC_PHYCNT_CAL
-			| RPC_PHYCNT_STRTIM3
-			| RPC_PHYCNT_STRTIM2
-			| RPC_PHYCNT_STRTIM1
-			| RPC_PHYCNT_STRTIM0);
-	reg &= ~(RPC_PHYCNT_HS
-			| RPC_PHYCNT_WBUF2
-			| RPC_PHYCNT_WBUF
-			| RPC_PHYCNT_PHYMEM_HYP);
-	mem_write32(RPC_PHYCNT, reg);
-		/* bit31  CAL         =  1 : PHY calibration */
-		/* bit1-0 PHYMEM[1:0] = 00 : QSPI-SDR */
-
-    reg =  mem_read32(RPC_CMNCR);
-    reg &= ~(CMNCR_BSZ_MASK);
-    reg |= (CMNCR_MD_MANUAL
-            | CMNCR_MOIIO3_HIZ
-            | CMNCR_MOIIO2_HIZ
-            | CMNCR_MOIIO1_HIZ
-            | CMNCR_MOIIO0_HIZ
-            | CMNCR_IO0FV_HIZ);
-    mem_write32(RPC_CMNCR, reg);
-		/* bit31  MD       =  1 : Manual mode */
-		/* bit1-0 BSZ[1:0] = 00 : QSPI Flash x 1 */
-
-    reg =  mem_read32(RPC_SMCMR);
-    reg &= ~(SMCMR_CMD_MASK
-            | SMCMR_OCMD_MASK);
-    reg |= ((gp_qspi_cmd_tbl -> write_any_register) << DRCMR_SMCMR_CMD_SHIFT);
-    mem_write32(RPC_SMCMR, reg);
-		/* bit23-16 CMD[7:0] = 0x71 : Write Any   Register Command  (WRAR) */
-
-	mem_write32(RPC_SMADR,   addr);
-
-    reg =  mem_read32(RPC_SMDRENR);
-    reg &= ~(SMDRENR_HYPE_MASK
-            | SMDRENR_ADDRE
-            | SMDRENR_OPDRE
-            | SMDRENR_SPIDRE);
-    mem_write32(RPC_SMDRENR, reg);
-		/* bit8 ADDRE  = 0 : Address SDR transfer */
-		/* bit0 SPIDRE = 0 : DATA SDR transfer */
-
-    reg =  mem_read32(RPC_SMENR);
-    reg &= ~(SMENR_CDB_MASK
-            | SMENR_OCDB_MASK
-            | SMENR_ADB_MASK
-            | SMENR_OPDB_MASK
-            | SMENR_SPIDB_MASK
-            | SMENR_DME_EN
-            | SMENR_OCDE_EN
-            | SMENR_ADE_MASK
-            | SMENR_OPDE_MASK
-            | SMENR_SPIDE_MASK);
-    reg |= (SMENR_CDE_EN
-            | SMENR_ADE_SERIAL_23
-            | SMENR_SPIDE_SPI_8);
-    mem_write32(RPC_SMENR, reg);
-		/* bit31-30 CDB[1:0]   =   00 : 1bit width command (QSPI0_MOSI) */
-		/* bit25-24 ADB[1:0]   =   00 : 1bit width address (QSPI0_MOSI) */
-		/* bit17-16 SPIDB[1:0] =   00 : 1bit width transfer data (QSPI0_MISO) */
-		/* bit15    DME        =    0 : No dummy cycle */
-		/* bit14    CDE        =    1 : Command enable */
-		/* bit11-8  ADE[3:0]   = 0111 : ADR[24:0] is output */
-		/* bit3-0   SPIDE[3:0] = 1000 : 8bit transfer */
-
-	mem_write8(RPC_SMWDR0, writeData);
-
-    reg =  mem_read32(RPC_SMCR);
-    reg &= ~(SMCR_SSLKP
-            | SMCR_SPIRE);
-    reg |= (SMCR_SPIWE
-            | SMCR_SPIE);
-    mem_write32(RPC_SMCR, reg);
-		/* bit2     SPIRE      = 0 : Data read disable */
-		/* bit1     SPIWE      = 1 : Data write disable */
-		/* bit0     SPIE       = 1 : SPI transfer start */
-
-	wait_rpc_tx_end();
-
-	reg = mem_read32(RPC_PHYCNT);
-	reg |= (RPC_PHYCNT_STRTIM3
-			| RPC_PHYCNT_STRTIM2
-			| RPC_PHYCNT_STRTIM1
-			| RPC_PHYCNT_STRTIM0
-			| RPC_PHYCNT_WBUF2);
-	reg &= ~(RPC_PHYCNT_HS
-			| RPC_PHYCNT_WBUF
-			| RPC_PHYCNT_PHYMEM_HYP);
-	mem_write32(RPC_PHYCNT, reg);
-		/* bit31  CAL         =  0 : No PHY calibration */
-		/* bit2   WBUF        =  0 : Write Buffer Disable */
-		/* bit1-0 PHYMEM[1:0] = 00 : QSPI-SDR */
-
-    reg =  mem_read32(RPC_DRCR);
-    reg |= (DRCR_SSLN
-            | DRCR_RBURST_32UNITS
-            | DRCR_RCF
-            | DRCR_RBE_BURST
-            | DRCR_SSLE);
-    mem_write32(RPC_DRCR, reg);
-		/* bit9   RCF         =  1 : Read Cache Clear */
-
-}
-/* End of function write_any_register_qspi_flash */
-#endif /* PRK3 > 0 */
 
 void set_rpc_clock_mode(uint32_t mode)
 {
@@ -794,6 +582,7 @@ void wait_rpc_tx_end(void)
 
 	while(1)
 	{
+		wdt_restart();
 		dataL = mem_read32(RPC_CMNSR);
 		if(dataL & BIT0)	break;
 		/*  Wait for TEND = 1 */
diff --git a/Gen4_ICUMX_Loader/ip/rpc/spiflash2drv.c b/Gen4_ICUMX_Loader/ip/rpc/spiflash2drv.c
index 30b1a50..31359fc 100644
--- a/Gen4_ICUMX_Loader/ip/rpc/spiflash2drv.c
+++ b/Gen4_ICUMX_Loader/ip/rpc/spiflash2drv.c
@@ -39,18 +39,14 @@
  *         : 09.11.2022 0.04     License notation change.
  *****************************************************************************/
 
-// #include "common.h"
 #include <stdint.h>
 #include <stddef.h>
-#include <log.h>
-#include "bit.h"
-#include "spiflash2drv.h"
-#include "rpcqspidrv.h"
-// #include "dgtable.h"
-// #include "dgflash.h"
-// #include "qspi_cmd.h"
+#include <spiflash2drv.h>
+#include <rpcqspidrv.h>
 #include <rpc.h>
-#include <dma.h>
+#include <log.h>
+
+#include "dma2.h"
 
 #define QSPI_PARAM_SEC_SIZE    (0x1000U)
 #define QSPI_PARAM_SEC_MASK    (0xFFFFF000U)
@@ -63,8 +59,11 @@ void fast_rd_qspi_flash(uint32_t sourceSpiAdd, uint32_t destinationAdd, uint32_t
 
 	sourceAdd = SPI_IOADDRESS_TOP + sourceSpiAdd;
 
-    dma_trans_start(destinationAdd, sourceAdd, byteCount);
-    dma_trans_end_check();
+	// dma_trans_start(destinationAdd, sourceAdd, byteCount);
+	// dma_trans_end_check();
+	// dma2_init();
+	dma2_start(destinationAdd, sourceAdd, byteCount, DMA_MODE_SRC_INC);
+	dma2_end();
 }
 /* End of function fast_rd_qspi_flash */
 
@@ -138,11 +137,7 @@ void page_program_with_buf_qspi_flash_s25s512s(uint32_t addr, uint32_t source_ad
 	/* Add */
 	while(1)
 	{
-#if (PRK3 > 0)
 		read_wip_status_register(&status);
-#else
-		read_status_qspi_flash(&status);
-#endif
 		if( !(status & BIT0) )
 		{
 			break;
@@ -197,9 +192,7 @@ void sector_erase_qspi_flash(uint32_t EraseStatAdd,uint32_t EraseEndAdd)
 	for(sectorAd = SectorStatTopAdd; sectorAd <= SectorEndTopAdd; sectorAd += FLASH_SECTOR_SIZE)
 	{
 		sector_erase_NNNkb_qspi_flash_s25s512s(sectorAd);
-		NOTICE(".");
 	}
-	NOTICE("Erase Completed\n");
 }
 /* End of function sector_erase_qspi_flash_s25s512s */
 
@@ -215,8 +208,6 @@ void parameter_sector_erase_qspi_flash(uint32_t EraseStatAdd,uint32_t EraseEndAd
 	for(sectorAd = SectorStatTopAdd; sectorAd <= SectorEndTopAdd; sectorAd += QSPI_PARAM_SEC_SIZE)
 	{
 		parameter_sector_erase_4kb_qspi_flash_s25s512s(sectorAd);
-		NOTICE(".");
 	}
-	NOTICE("Erase Completed\n");
 }
 /* End of function parameter_sector_erase_qspi_flash */