/******************************************************************************* * DISCLAIMER * This software is supplied by Renesas Electronics Corporation and is only * intended for use with Renesas products. No other uses are authorized. This * software is owned by Renesas Electronics Corporation and is protected under * all applicable laws, including copyright laws. * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. * Renesas reserves the right, without notice, to make changes to this software * and to discontinue the availability of this software. By using this software, * you agree to the additional terms and conditions found by accessing the * following link: * http://www.renesas.com/disclaimer * Copyright 2023 Renesas Electronics Corporation All rights reserved. *******************************************************************************/ /******************************************************************************* * DESCRIPTION : RT-SRAM register header ******************************************************************************/ #ifndef RTSRAM_REGISTER_H__ #define RTSRAM_REGISTER_H__ #include /* RT-SRAM register base address */ #define RTSRAM_REG_BASE (0xFFE90000U) #define RTSRAM_SECDIVD (RTSRAM_REG_BASE + 0x0000U) #define RTSRAM_SECCTRRD (RTSRAM_REG_BASE + 0x0040U) #define RTSRAM_SECCTRWD (RTSRAM_REG_BASE + 0x0340U) #if (RCAR_LSI == RCAR_S4) #define RTSRAM_SECDIVD_DIVADDR_MASK (0x000000FFU) #else #define RTSRAM_SECDIVD_DIVADDR_MASK (0x000FFFFFU) #endif #define RTSRAM_SECCTRRD_SECGRP_MASK (0x000F0000U) #define RTSRAM_SECCTRRD_SAFGRP_MASK (0x0000FFFFU) #define RTSRAM_SECCTRWD_SECGRP_MASK (0x000F0000U) #define RTSRAM_SECCTRWD_SAFGRP_MASK (0x0000FFFFU) static inline uint32_t get_rtsram_secdivd_addr(uint32_t num) { return ((RTSRAM_SECDIVD + (num * 4U))); } static inline uint32_t get_rtsram_secctrrd_addr(uint32_t num) { return ((RTSRAM_SECCTRRD + (num * 4U))); } static inline uint32_t get_rtsram_secctrwd_addr(uint32_t num) { return ((RTSRAM_SECCTRWD + (num * 4U))); } #endif /* RTSRAM_REGISTER_H__ */