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 * Copyright 2021-2023 Renesas Electronics Corporation All rights reserved.
 *******************************************************************************/

/*******************************************************************************
 * DESCRIPTION   : DMA register header
 ******************************************************************************/

#ifndef DMA_REGISTER_H_
#define DMA_REGISTER_H_

#include <remap_register.h>
#include <log.h>

#define DMACH   (0U)    /* The range of DMA ch is 0-15. */

#if ((RCAR_LSI == RCAR_S4) || (RCAR_LSI == RCAR_V4H))
#define RTDMA_MODULE_MAX    (4U)
#define RTDMA_CH_MAX        (16U)
#define SYSDMA_MODULE_MAX   (2U)
#define SYSDMA_CH_MAX       (16U)
#elif (RCAR_LSI == RCAR_V4M)
#define RTDMA_MODULE_MAX        (2U)
#define RTDMA_CH_MAX            (16U)
#define SYSDMA_MODULE_MAX       (2U)
#define SYSDMA_CH_MAX           (16U)
#endif

/* RT-DMA Control */
#define RTDMACTL_BASE       (BASE_RTDMACTL_ADDR)

#define RTDMA_DMOR          (RTDMACTL_BASE + 0x0060U)   /* DMA operation register */

/* RT-DMAC0(for RPC) */
#define RTDMA0_BASE         (BASE_RTDMA0_ADDR)
#define RTDMA1_BASE         (RTDMA0_BASE + 0x00010000U)
#define RTDMA2_BASE         (RTDMA0_BASE + 0x00160000U)
#define RTDMA3_BASE         (RTDMA0_BASE + 0x00170000U)
/* SYSDMAC */
#define SYSDMA0_BASE        (BASE_DMA_ADDR)
#define SYSDMA1_BASE        (SYSDMA0_BASE + 0x00010000U)

#define RTDMA_DMSEC         (RTDMA0_BASE + 0x00B0U)

#define DMA_REGIONID_MASK   (0x0000000FU)


static inline uint32_t dma_get_rtdma_sar_addr(uint32_t num)
{
    return (RTDMA0_BASE + 0x0000U + (num * 0x1000U));
}

static inline uint32_t dma_get_rtdma_dar_addr(uint32_t num)
{
    return (RTDMA0_BASE + 0x0004U + (num * 0x1000U));
}

static inline uint32_t dma_get_rtdma_tcr_addr(uint32_t num)
{
    return (RTDMA0_BASE + 0x0008U + (num * 0x1000U));
}

static inline uint32_t dma_get_rtdma_chcr_addr(uint32_t num)
{
    return (RTDMA0_BASE + 0x000CU + (num * 0x1000U));
}

static inline uint32_t dma_get_rtdma_module_base_addr(uint32_t module)
{
    uint32_t ret;

    if(module == 0U)
    {
        ret = RTDMA0_BASE;
    }
    else if(module == 1U)
    {
        ret = RTDMA1_BASE;
    }
#if ((RCAR_LSI == RCAR_S4) || (RCAR_LSI == RCAR_V4H))
    else if(module ==2U)
    {
        ret = RTDMA2_BASE;
    }
    else if(module == 3U)
    {
        ret = RTDMA3_BASE;
    }
#endif /* ((RCAR_LSI == RCAR_S4) || (RCAR_LSI == RCAR_V4H)) */
    else
    {
        ERROR("Invalid DMA module value!\n");
        panic;
    }
    return ret;
}

static inline uint32_t dma_get_rtdma_regionid_addr(uint32_t module, uint32_t ch)
{
    uint32_t base;
    base = dma_get_rtdma_module_base_addr(module);

    return (base + 0x0078U + (ch * 0x1000U));
}

static inline uint32_t dma_get_sysdma_module_base_addr(uint32_t module)
{
    uint32_t ret;

    if(module == 0U)
    {
        ret = SYSDMA0_BASE;
    }
    else if(module == 1U)
    {
        ret = SYSDMA1_BASE;
    }
    else
    {
        ERROR("Invalid DMA module value!\n");
        panic;
    }

    return ret;
}

static inline uint32_t dma_get_sysdma_regionid_addr(uint32_t module, uint32_t ch)
{
    uint32_t base;
    base = dma_get_sysdma_module_base_addr(module);

    return (base + 0x0078U + (ch * 0x1000U));
}

#endif /* DMAREGISTER_H_ */