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* DISCLAIMER
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* intended for use with Renesas products. No other uses are authorized. This
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*******************************************************************************/



/*******************************************************************************
 * DESCRIPTION   : Loader linker directive
 ******************************************************************************/
/******************************************************************************
 * @file          loader,ld
 * - Version      : 0.07
 * @brief         
 * .
 *****************************************************************************/
/******************************************************************************
 * History : DD.MM.YYYY Version  Description
 *         : 02.02.2022 0.01     First Release
 *         : 21.02.2022 0.02     Changed section name
 *         : 10.05.2022 0.03     Changed section name
 *                               Added memory
 *                               Change binary size to multiples of 16
 *         : 20.06.2022 0.04     Support secure boot for S4
 *         : 02.08.2022 0.05     Support WDT
 *         : 31.10.2022 0.06     License notation change.
 *         : 13.02.2023 0.07     Added sections for MMU table.
 *****************************************************************************/

OUTPUT_FORMAT("elf64-littleaarch64")
OUTPUT_ARCH(aarch64)
ENTRY(Startup)

MEMORY {
	SYSRAM  (rwxa): ORIGIN = 0xE6300000, LENGTH = 0x00030000

	/* Must match with MMU_TBL_SYSRAM_ADDR defined in loader_mmu_table.c. */
	MMU_LV3_STAT   (rwa):  ORIGIN = 0xE6310000, LENGTH = 0x00001000  /* level3:4KiB   */
	/* Must match with MMU_TBL_ADDR defined in loader_mmu_table.c. */
	MMU_LV2_STAT   (rwa):  ORIGIN = 0xE6311000, LENGTH = 0x00001000  /* level2:4KiB   */
	MMU_LV1_STAT   (rwa):  ORIGIN = 0xE6312000, LENGTH = 0x00000100  /* level1:32byte */
	CXIPLDATA  (rwa):  ORIGIN = 0xE6330000, LENGTH = 0x00001000
	CXIPLSTACK  (rwa):  ORIGIN = 0xE6331000, LENGTH = 0x00002000
	SHARED_RAM  (rwa):  ORIGIN = 0x41C00000, LENGTH = 0x0000C000
	SHARED_SDRAM  (rwa):  ORIGIN = 0x41E00000, LENGTH = 0x00200000
}

SECTIONS
{
	.loader_start : {
		__RO_START__ = .;
		build/obj/loader/loader_s4.o(.text*)
		. = NEXT(2048);
		*(.vectors)
		. = ALIGN(4096);
	} > SYSRAM

	.loader_ro : {
		*(.text*)
		*(.rodata*)
		. = ALIGN(8);
		__CONST_START__ = .;
		*(.constdata.CONFIG_DATA)
		__RO_END_UNALIGNED__ = .;
		. = NEXT(4096);
		__RO_END__ = .;
		__DATA_COPY_START__ = .;
	} > SYSRAM

	.lv3_tbl : {
		build/obj/loader/loader_mmu_table.o(.rodata)
	} > MMU_LV3_STAT

	.lv2_tbl : {
		build/obj/loader/loader_mmu_table.o(.rodata)
	} > MMU_LV2_STAT

	.lv1_tbl : {
		build/obj/loader/loader_mmu_table.o(.rodata)
	} > MMU_LV1_STAT

	.data : {
		__DATA_START__ = .;
		*(.data*)
        . = NEXT(16);
		__DATA_END__ = .;
	} > CXIPLDATA AT > SYSRAM

	__DATA_SIZE__ = SIZEOF(.data);

	stacks (NOLOAD) : ALIGN(16) {
		__STACKS_START__ = .;
		KEEP(*(Cx_loader_stack))
		__STACKS_END__ = .;
	} > CXIPLSTACK

	.bss.SHARED_TOP : {
		__SHARED_TOP_START__ = .;
		*(.bss.SHARED_TOP)
		*(.bss.SHARED_LCS)
		*(.bss.SHARED_CMAC)
		*(.bss.SHARED_HASH)
		. = NEXT(0x00200000);
		__SHARED__END__ = .;
	} > SHARED_SDRAM

	.SHARED_RAM : {
		__FWRAM_START__ = .;
		. += 0;
		. = NEXT(0x0000C000);
		__FWRAM_END__ = .;
	} > SHARED_RAM

	.bss : ALIGN(16) {
		__BSS_START__ = .;
		*(SORT_BY_ALIGNMENT(.bss*))
		*(COMMON)
		__BSS_END__ = .;
	} > CXIPLDATA

	__BSS_SIZE__ = SIZEOF(.bss);
}