/******************************************************************************* * DISCLAIMER * This software is supplied by Renesas Electronics Corporation and is only * intended for use with Renesas products. No other uses are authorized. This * software is owned by Renesas Electronics Corporation and is protected under * all applicable laws, including copyright laws. * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. * Renesas reserves the right, without notice, to make changes to this software * and to discontinue the availability of this software. By using this software, * you agree to the additional terms and conditions found by accessing the * following link: * http://www.renesas.com/disclaimer * Copyright 2022 Renesas Electronics Corporation All rights reserved. *******************************************************************************/ /******************************************************************************* * DESCRIPTION : Image load function by SDMAC on ICUMX header ******************************************************************************/ #ifndef SDMAC_H__ #define SDMAC_H__ #include #include /* Prototype */ void icu_sdmac_trans_start(const LOAD_INFO *li); void icu_sdmac_trans_end(void); /* Definitions */ #define ICUMX_DMACHRST_CLR_CH0 (0x00000001U) #define ICUMX_DMACHRST_CLR_CH1 (0x00000002U) #define ICUMX_DMACHRST_CLR_CH2 (0x00000004U) #define ICUMX_DMACHFCR_CAEC (0x00000008U) #define ICUMX_DMACHFCR_TEC (0x00000002U) #define ICUMX_DMACHFCR_DEC (0x00000001U) #define ICUMX_DMACHFCR_INIT (ICUMX_DMACHFCR_CAEC | ICUMX_DMACHFCR_TEC | ICUMX_DMACHFCR_DEC) #define ICUMX_DMAOR_PR_ROUND_ROBIN (0x0300U) #define ICUMX_DMAOR_DME_ENABLE (0x0001U) #define ICUMX_DMAOR_INIT (ICUMX_DMAOR_PR_ROUND_ROBIN | ICUMX_DMAOR_DME_ENABLE) #define ICUMX_DMATMR_SLM_NORMAL (0x00000000U) #define ICUMX_DMATMR_PRI_DISABLE (0x00000000U) #define ICUMX_DMATMR_TRS_AT_REQ (0x00000000U) #define ICUMX_DMATMR_TRS_HARD_REQ (0x00001000U) #define ICUMX_DMATMR_DM_INC (0x00000400U) #define ICUMX_DMATMR_SM_INC (0x00000100U) #define ICUMX_DMATMR_DTS_64B (0x00000060U) #define ICUMX_DMATMR_STS_64B (0x00000006U) #define ICUMX_DMATMR_0_INIT (ICUMX_DMATMR_SLM_NORMAL | ICUMX_DMATMR_PRI_DISABLE | ICUMX_DMATMR_TRS_AT_REQ \ | ICUMX_DMATMR_DM_INC | ICUMX_DMATMR_SM_INC | ICUMX_DMATMR_DTS_64B \ | ICUMX_DMATMR_STS_64B) #define ICUMX_DMATMR_1_INIT (ICUMX_DMATMR_SLM_NORMAL | ICUMX_DMATMR_PRI_DISABLE \ | ICUMX_DMATMR_TRS_HARD_REQ | ICUMX_DMATMR_SM_INC | ICUMX_DMATMR_DTS_64B \ | ICUMX_DMATMR_STS_64B) #define ICUMX_DMATMR_2_INIT (ICUMX_DMATMR_SLM_NORMAL | ICUMX_DMATMR_PRI_DISABLE \ | ICUMX_DMATMR_TRS_HARD_REQ | ICUMX_DMATMR_DM_INC | ICUMX_DMATMR_DTS_64B \ | ICUMX_DMATMR_STS_64B) #define ICUMX_DMACHCR_CAEE_ENABLE (0x0010U) #define ICUMX_DMACHCR_CAIE_ENABLE (0x0008U) #define ICUMX_DMACHCR_IE_ENABLE (0x0002U) #define ICUMX_DMACHCR_DE_ENABLE (0x0001U) #define ICUMX_DMACHCR_0_START (ICUMX_DMACHCR_CAEE_ENABLE | ICUMX_DMACHCR_DE_ENABLE) #define ICUMX_DMACHCR_1_START (ICUMX_DMACHCR_CAEE_ENABLE | ICUMX_DMACHCR_CAIE_ENABLE \ | ICUMX_DMACHCR_DE_ENABLE) #define ICUMX_DMACHCR_2_START (ICUMX_DMACHCR_CAEE_ENABLE | ICUMX_DMACHCR_CAIE_ENABLE \ | ICUMX_DMACHCR_IE_ENABLE | ICUMX_DMACHCR_DE_ENABLE) #define ICUMX_DMACHSTA_CAE (0x00000008U) #define ICUMX_DMACHSTA_TE (0x00000002U) #define DMACHSTA_CAE_BIT_NOERROR (0x00000000U) #define DMACHSTA_TE_END_DMA (0x00000002U) #define ICUMX_DMARS_TC_1 (0x00010000U) #define ICUMX_DMARS_TL_TMR_DTS (0x00001000U) #define ICUMX_DMARS_TL_TMR_STS (0x00000000U) #define ICUMX_DMARS_FPT_DE_IS_1 (0x00000000U) #define ICUMX_DMARS_PLE_ENABLE (0x00000400U) #define ICUMX_DMARS_PLE_DISABLE (0x00000000U) #define ICUMX_DMARS_RS_FOR_CH2 (0x00000001U) #define ICUMX_DMARS_1_INIT (ICUMX_DMARS_TC_1 | ICUMX_DMARS_TL_TMR_DTS | ICUMX_DMARS_FPT_DE_IS_1 \ | ICUMX_DMARS_PLE_ENABLE) #define ICUMX_DMARS_2_INIT (ICUMX_DMARS_TC_1 | ICUMX_DMARS_TL_TMR_STS | ICUMX_DMARS_FPT_DE_IS_1 \ | ICUMX_DMARS_PLE_DISABLE | ICUMX_DMARS_RS_FOR_CH2) #define SDMAC_FRACTION_MASK_64_BYTE (0x3FU) #endif /* SDMAC_H__ */