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/*******************************************************************************
 * DESCRIPTION   : sysc header
 ******************************************************************************/
/******************************************************************************
 * @file          sysc.h
 * - Version      : 0.02
 * @brief         
 * .
 *****************************************************************************/
/******************************************************************************
 * History : DD.MM.YYYY Version  Description
 *         : 29.09.2023 0.01     First Release
 *         : 08.01.2025 0.02     Add write protection register definition.
 *****************************************************************************/
#ifndef SYSC_H_
#define SYSC_H_

#include <stdint.h>
#include <remap_register.h>

#define BASE_SYSC              (BASE_SYSC_ADDR)     /* SYSC logical address  0xFDB80000 */
                                                    /* SYSC physical address 0xE6180000 */
#if (RCAR_LSI == RCAR_V4M)
#define SYSC_SYSCSR            (BASE_SYSC + 0x0000U)
#define SYSC_SYSCISCR0         (BASE_SYSC + 0x0810U)
#define SYSC_SYSCIER0          (BASE_SYSC + 0x0820U)
#define SYSC_SYSCIMR0          (BASE_SYSC + 0x0830U)
#define SYSC_PDRONCR31         (BASE_SYSC + 0x1004U + (31U * 64U))   /* Power Domain:C4 */
#endif /* RCAR_LSI == RCAR_V4M */
#define SYSC_SYSCD1WACR0       (BASE_SYSC + 0x3020U)
#define SYSC_SYSCD2WACR0       (BASE_SYSC + 0x3040U)
#define SYSC_SYSCD3WACR0       (BASE_SYSC + 0x3060U)

#if (RCAR_LSI == RCAR_V4M)
#define SYSCIER0_PDR31         (0x80000000U)   /* Bit31 */
#define SYSCIMR0_PDR31         (0x80000000U)   /* Bit31 */
#define SYSCISCR0_PDR31        (0x80000000U)   /* Bit31 */
#define SYSCSR_BUSY1           (0x00000002U)   /* Bit1 */
#define PDRONCR31_PWRON        (0x00000001U)   /* Bit0 */
#endif /* RCAR_LSI == RCAR_V4M */

/* Prototype */
#if (RCAR_LSI == RCAR_V4M)
void sysc_c4_power_on(void);
#endif /* RCAR_LSI == RCAR_V4M */
#endif /* SYSC_H_ */