/*******************************************************************************
 * DISCLAIMER
 * This software is supplied by Renesas Electronics Corporation and is only
 * intended for use with Renesas products. No other uses are authorized. This
 * software is owned by Renesas Electronics Corporation and is protected under
 * all applicable laws, including copyright laws.
 * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
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 * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
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 * Renesas reserves the right, without notice, to make changes to this software
 * and to discontinue the availability of this software. By using this software,
 * you agree to the additional terms and conditions found by accessing the
 * following link:
 * http://www.renesas.com/disclaimer
 * Copyright 2021-2022 Renesas Electronics Corporation All rights reserved.
 *******************************************************************************/

/*******************************************************************************
 * DESCRIPTION   : RPC driver header
 ******************************************************************************/

#ifndef RPC_H__
#define RPC_H__

#include <stdint.h>
// #include <rpc_register.h>

/* If user customizes for another vendor's QSPI Flash, set to 1. */
#define USER_ADDED_QSPI         (1U)    /* 0:Disable 1:Enable */

/* For return value */
#define QSPI_CMD_INIT_SUCCESS   (0x00000000U)
#define QSPI_CMD_INIT_ERROR     (0xFFFFFFFFU)
/* Common command for QSPI Flash */
#define FLASH_CMD_READ_ID       (0x9FU)
/* Device ID mask for QSPI Flash */
#define DEVICE_ID_MASK          (0x00FFFFFFU)

/* QSPI Flash device ID */
#define DEVID_MT25QU01GB        (0x0021BB20U)  /* MT25QU01GB for PRK3 rev3 */
#if USER_ADDED_QSPI == 1
#define DEVID_XXXXXXXXX         (0x003B25C2U)  /* MX66U1G45G for PRK3 rev4 */
#endif /* USER_ADDED_QSPI == 1 */

typedef struct {
    uint32_t    read_fast;
    uint32_t    sector_erase_4byte_addr;
    uint32_t    parameter_4kbyte_erase;
    uint32_t    pp_4byte_addr;
    uint32_t    read_any_register;
    uint32_t    read_stts_register;
    uint32_t    write_enable;
    uint32_t    read_32bit_addr;
    uint32_t    ddr_quad_io_read_32bit_addr;
} st_qspi_cmd_tbl_t;

extern const st_qspi_cmd_tbl_t* gp_qspi_cmd_tbl;
extern uint8_t prk3_rev;

void rpc_init(void);
void rpc_release(void);
void rpc_end_state_check(void);
void qspi_flash_rw_init(void);
int check_Erase_Fail(uint32_t status);

void qspi_ddr_transfer_mode(uint32_t command);
void qspi_sdr_transfer_mode(uint32_t command);
#endif  /* RPC_H__ */