/******************************************************************************* * DISCLAIMER * This software is supplied by Renesas Electronics Corporation and is only * intended for use with Renesas products. No other uses are authorized. This * software is owned by Renesas Electronics Corporation and is protected under * all applicable laws, including copyright laws. * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. * Renesas reserves the right, without notice, to make changes to this software * and to discontinue the availability of this software. By using this software, * you agree to the additional terms and conditions found by accessing the * following link: * http://www.renesas.com/disclaimer * Copyright 2023-2025 Renesas Electronics Corporation All rights reserved. *******************************************************************************/ /******************************************************************************* * DESCRIPTION : RAM protection driver header ******************************************************************************/ #ifndef RAM_PROTECTION_H_ #define RAM_PROTECTION_H_ #include #include #define RTSRAM_AREA1_TOP (0xE0040000U) #define RTSRAM_ADDR_END (0xE0100000U) #if (RCAR_LSI == RCAR_S4) #define RTSRAM_ADDR_OFFSET_MASK (0x000FF000U) #else #define RTSRAM_ADDR_OFFSET_MASK (0xFFFFF000U) #endif #define RTVRAM_AREA1_TOP (0xE2010000U) #define RTVRAM_AREA2_TOP (0xE2100000U) #define RTVRAM_ADDR_END (0xE3C00000U) #define RTVRAM_ADDR_MASK (0xFFFFF000U) #if (RCAR_LSI == RCAR_S4) #define SYSTEM_RAM_ADDR_END (0xE6360000U) #else /* (RCAR_LSI == RCAR_S4) */ /* For V4H/V4M */ #define SYSTEM_RAM_AREA1_TOP (0xE635E000U) #define SYSTEM_RAM_AREA2_TOP (0xE6360000U) #define SYSTEM_RAM_ADDR_END (0xE6400000U) #endif /* (RCAR_LSI == RCAR_S4) */ #define SYSTEM_RAM_ADDR_MASK (0xFFFFF000U) #if ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M)) #define DRAM_ADDR_AREA1 (0x0401C00000ULL) #define DRAM_ADDR_AREA2 (0x0401D00000ULL) #if (OPTEE_LOAD_ENABLE == OPTEE_DISABLE) #define DRAM_ADDR_AREA3 (0x0406400000ULL) #define DRAM_ADDR_AREA4 (0x0406440000ULL) #define DRAM_ADDR_AREA5 (0x0407FC0000ULL) #define DRAM_ADDR_AREA6 (0x0408000000ULL) #define DRAM_ADDR_AREA7 (0x041DC00000ULL) #define DRAM_ADDR_AREA8 (0x0420000000ULL) #define DRAM_ADDR_AREA9 (0x0440000000ULL) #define DRAM_ADDR_AREA10 (0x0460000000ULL) #define DRAM_ADDR_AREA11 (0x0480000000ULL) #define DRAM_ADDR_AREA12 (0x0500000000ULL) #define DRAM_ADDR_AREA13 (0x0600000000ULL) #else #define DRAM_ADDR_AREA3 (0x0404100000ULL) #define DRAM_ADDR_AREA4 (0x0406400000ULL) #define DRAM_ADDR_AREA5 (0x0406440000ULL) #define DRAM_ADDR_AREA6 (0x0407E00000ULL) #define DRAM_ADDR_AREA7 (0x0407F00000ULL) #define DRAM_ADDR_AREA8 (0x0407FC0000ULL) #define DRAM_ADDR_AREA9 (0x0408000000ULL) #define DRAM_ADDR_AREA10 (0x041DC00000ULL) #define DRAM_ADDR_AREA11 (0x0420000000ULL) #define DRAM_ADDR_AREA12 (0x0440000000ULL) #define DRAM_ADDR_AREA13 (0x0460000000ULL) #define DRAM_ADDR_AREA14 (0x0480000000ULL) #define DRAM_ADDR_AREA15 (0x0500000000ULL) #define DRAM_ADDR_AREA16 (0x0600000000ULL) #endif /* OPTEE_LOAD_ENABLE == OPTEE_DISABLE */ #else #define DRAM_ADDR_AREA1 (0x0401C00000ULL) #define DRAM_ADDR_AREA2 (0x0406400000ULL) #define DRAM_ADDR_AREA3 (0x0406440000ULL) #endif /* ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M)) */ #define DRAM_ADDR_END (0x0700000000ULL) #define SDRAM_ADDR_MASK (0x3FFFFF0000ULL) #define NOT_USED_VALUE (0x00000000U) /* For System RAM protection setting */ #define REGIONID0_WRITE_PRIVILEGE (0x00000001U) /* bit0 */ /* RAM DIVISION AREA ID */ /* RT-SRAM */ #define RTSRAM_ICUMX_IPL_AREA (0U) /* 0xE0000000 -- 0xE003FFFF */ #define RTSRAM_ICUMX_FW_AREA (1U) /* 0xE0040000 -- 0xE00FFFFF */ /* RT-VRAM */ #define RTVRAM_BLANK_AREA (0U) /* 0xE2000000 -- 0xE200FFFF */ #define RTVRAM_EXTEND_CACHE_AREA (1U) /* 0xE2010000 -- 0xE20FFFFF */ #define RTVRAM_RTOS_AREA (2U) /* 0xE2100000 -- 0xE3BFFFFF */ /* System RAM */ #define SYSTEM_RAM_CX_2ND_IPL (0U) /* 0xE6300000 -- 0xE635DFFF */ #define SYSTEM_RAM_SHARED_MEM (1U) /* 0xE635E000 -- 0xE635FFFF */ /* SDRAM */ #if ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M)) #define RTVRAM_EXTEND_AREA (0U) /* 0x04_00000000 -- 0x04_01BFFFFF */ #define CR_FW_SHARED_AREA (1U) /* 0x04_01C00000 -- 0x04_01CFFFFF */ #define SDRAM_BLANK_AREA (2U) /* OPTEE_DISABLE:0x04_01D00000 -- 0x04_063FFFFF * OPTEE_ENABLE :0x04_01D00000 -- 0x04_040FFFFF */ #define SDRAM_PROTECT_AREA (3U) /* OPTEE_DISABLE:0x04_06400000 -- 0x04_0643FFFF * OPTEE_ENABLE :0x04_04100000 -- 0x04_0643FFFF */ #if (OPTEE_LOAD_ENABLE == OPTEE_DISABLE) #define SDRAM_PUBLIC_AREA (4U) /* 0x04_06440000 -- 0x04_07FBFFFF */ #define ICCOM_USED_AREA (5U) /* 0x04_07FC0000 -- 0x04_07FFFFFF */ #define LINUX_USED_AREA (6U) /* 0x04_08000000 -- 0x04_1DBFFFFF */ #define CAAREA2_USED_AREA (7U) /* 0x04_1DC00000 -- 0x04_1FFFFFFF */ #define CR52_USED_AREA (8U) /* 0x04_20000000 -- 0x04_3FFFFFFF */ #define CAAREA3_USED_AREA (9U) /* 0x04_40000000 -- 0x04_5FFFFFFF */ #define CAAREA2_USED_AREA2 (10U) /* 0x04_60000000 -- 0x04_7FFFFFFF */ #define CAAREA1_USED_AREA (11U) /* 0x04_80000000 -- 0x04_FFFFFFFF */ #else #define SDRAM_PROTECT_AREA2 (4U) /* 0x04_06400000 -- 0x04_0643FFFF */ #define SDRAM_BLANK_AREA2 (5U) /* 0x04_06440000 -- 0x04_07DFFFFF */ #define OPTEE_SHARED_AREA (6U) /* 0x04_07E00000 -- 0x04_07EFFFFF */ #define SDRAM_BLANK_AREA3 (7U) /* 0x04_07F00000 -- 0x04_07FBFFFF */ #define ICCOM_USED_AREA (8U) /* 0x04_07FC0000 -- 0x04_07FFFFFF */ #define LINUX_USED_AREA (9U) /* 0x04_08000000 -- 0x04_1DBFFFFF */ #define CAAREA2_USED_AREA (10U) /* 0x04_1DC00000 -- 0x04_1FFFFFFF */ #define CR52_USED_AREA (11U) /* 0x04_20000000 -- 0x04_3FFFFFFF */ #define CAAREA3_USED_AREA (12U) /* 0x04_40000000 -- 0x04_5FFFFFFF */ #define CAAREA2_USED_AREA2 (13U) /* 0x04_60000000 -- 0x04_7FFFFFFF */ #define CAAREA1_USED_AREA (14U) /* 0x04_80000000 -- 0x04_FFFFFFFF */ #endif /* OPTEE_LOAD_ENABLE == OPTEE_DISABLE */ #if (RCAR_LSI == RCAR_V4H) #if (OPTEE_LOAD_ENABLE == OPTEE_DISABLE) #define RESERVERD_AREA (12U) /* 0x05_00000000 -- 0x05_FFFFFFFF */ #define CAAREA1_USED_AREA2 (13U) /* 0x06_00000000 -- 0x06_FFFFFFFF */ #else #define RESERVERD_AREA (15U) /* 0x05_00000000 -- 0x05_FFFFFFFF */ #define CAAREA1_USED_AREA2 (16U) /* 0x06_00000000 -- 0x06_FFFFFFFF */ #endif /* OPTEE_LOAD_ENABLE == OPTEE_DISABLE */ #elif (RCAR_LSI == RCAR_V4M) #if (OPTEE_LOAD_ENABLE == OPTEE_DISABLE) #define CAAREA1_USED_AREA2 (12U) /* 0x05_00000000 -- 0x05_FFFFFFFF */ #define RESERVERD_AREA (13U) /* 0x06_00000000 -- 0x06_FFFFFFFF */ #else #define CAAREA1_USED_AREA2 (15U) /* 0x05_00000000 -- 0x05_FFFFFFFF */ #define RESERVERD_AREA (16U) /* 0x06_00000000 -- 0x06_FFFFFFFF */ #endif /* OPTEE_LOAD_ENABLE == OPTEE_DISABLE */ #endif /* RCAR_LSI == RCAR_V4H */ #else #define RTVRAM_EXTEND_AREA (0U) /* 0x04_00000000 -- 0x04_01BFFFFF */ #define SDRAM_BLANK_AREA (1U) /* 0x04_01C00000 -- 0x04_063FFFFF */ #define SDRAM_PROTECT_AREA (2U) /* 0x04_06400000 -- 0x04_0643FFFF */ #define SDRAM_PUBLIC_AREA (3U) /* 0x04_06440000 -- 0x06_FFFFFFFF */ #endif /* ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M)) */ #endif /* RAM_PROTECTION_H_ */