/******************************************************************************* * DISCLAIMER * This software is supplied by Renesas Electronics Corporation and is only * intended for use with Renesas products. No other uses are authorized. This * software is owned by Renesas Electronics Corporation and is protected under * all applicable laws, including copyright laws. * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. * Renesas reserves the right, without notice, to make changes to this software * and to discontinue the availability of this software. By using this software, * you agree to the additional terms and conditions found by accessing the * following link: * http://www.renesas.com/disclaimer * Copyright 2021-2024 Renesas Electronics Corporation All rights reserved. *******************************************************************************/ /******************************************************************************* * DESCRIPTION : Power management driver header ******************************************************************************/ #ifndef CPU_ON_H__ #define CPU_ON_H__ #include "remap_register.h" #define RCAR_PWR_TARGET_CR (0U) #define RCAR_PWR_TARGET_CA (1U) #define AP_CORE_APSREG_AP_CLUSTER_N_AUX0_ACTDIS1 (0x00000001U << 1U) #define AP_CORE_APSREG_AP_CLUSTER_N_AUX0_ACTDIS0 (0x00000001U << 0U) #define AP_CORE_APSREG_CCI500_AUX_ACTDIS (0x00000001U << 0U) #define AP_CORE_APSREG_AP_CLUSTER_N_AUX0_INIT (AP_CORE_APSREG_AP_CLUSTER_N_AUX0_ACTDIS1 | AP_CORE_APSREG_AP_CLUSTER_N_AUX0_ACTDIS0) #define OTP_MEM_1_BASE (BASE_OTP_MEM_ADDR) #define OTP_MEM_OTPMONITOR17 (OTP_MEM_1_BASE + 0x0144U) #define OTP_MEM_PRODUCT_MASK (0x000000FFU) #if (RCAR_LSI == RCAR_V4H) #define VARIANT_V4H_7 (0x00U) #define VARIANT_V4H_5 (0x01U) #define VARIANT_V4H_3 (0x02U) #elif (RCAR_LSI == RCAR_V4M) #define VARIANT_V4M_7 (0x00U) #define VARIANT_V4M_5 (0x01U) #define VARIANT_V4M_3 (0x02U) #define VARIANT_V4M_2 (0x04U) #endif /* RCAR_LSI == RCAR_V4H */ /******************************************************************************* * Function & variable prototypes ******************************************************************************/ void arm_cpu_on(uint32_t target, uint32_t boot_addr); void adj_cr_variant_freq(void); #endif /* CPU_ON_H__ */