/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
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* Copyright 2018-2024 Renesas Electronics Corporation All rights reserved.
*******************************************************************************/

#ifndef DDR_REGDEF
#define DDR_REGDEF

#define PHY_LP4_BOOT_RX_PCLK_CLK_SEL                        0x10031000U
#define PHY_PER_CS_TRAINING_MULTICAST_EN                    0x10011006U
#define PHY_VREF_INITIAL_STEPSIZE                           0x1808100DU
#define PHY_RDLVL_BEST_THRSHLD                              0x0004100EU
#define PHY_RDLVL_VREF_OUTLIER                              0x1003100EU
#define PHY_RDLVL_RDDQS_DQ_OBS_SELECT                       0x1005102CU
#define PHY_CALVL_VREF_DRIVING_SLICE                        0x18011030U
#define PHY_WRLVL_HARD0_DELAY_OBS                           0x000A1038U
#define PHY_WRLVL_HARD1_DELAY_OBS                           0x100A1038U
#define PHY_WRLVL_STATUS_OBS                                0x001C1039U
#define PHY_WRLVL_ERROR_OBS                                 0x0010103BU
#define PHY_GTLVL_STATUS_OBS                                0x0012103DU
#define PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS                       0x1009103EU
#define PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS                       0x0009103FU
#define PHY_WDQLVL_STATUS_OBS                               0x00201043U
#define PHY_DATA_DC_CAL_START                               0x1801104DU
#define PHY_SLV_DLY_CTRL_GATE_DISABLE                       0x1001104EU
#define PHY_REGULATOR_EN_CNT                                0x18061050U
#define PHY_VREF_INITIAL_START_POINT                        0x00091055U
#define PHY_VREF_INITIAL_STOP_POINT                         0x10091055U
#define PHY_VREF_TRAINING_CTRL                              0x00021056U
#define PHY_RDDQ0_SLAVE_DELAY                               0x0009105DU
#define PHY_RDDQ1_SLAVE_DELAY                               0x1009105DU
#define PHY_RDDQ2_SLAVE_DELAY                               0x0009105EU
#define PHY_RDDQ3_SLAVE_DELAY                               0x1009105EU
#define PHY_RDDQ4_SLAVE_DELAY                               0x0009105FU
#define PHY_RDDQ5_SLAVE_DELAY                               0x1009105FU
#define PHY_RDDQ6_SLAVE_DELAY                               0x00091060U
#define PHY_RDDQ7_SLAVE_DELAY                               0x10091060U
#define PHY_RDDM_SLAVE_DELAY                                0x00091061U
#define PHY_RX_CAL_ALL_DLY                                  0x18061061U
#define PHY_RX_PCLK_CLK_SEL                                 0x00031062U
#define PHY_DATA_DC_CAL_CLK_SEL                             0x18031063U
#define PHY_PAD_VREF_CTRL_DQ                                0x000E1067U
#define PHY_PER_CS_TRAINING_EN                              0x00011068U
#define PHY_RDDATA_EN_TSEL_DLY                              0x18051069U
#define PHY_RDDATA_EN_OE_DLY                                0x0005106AU
#define PHY_RPTR_UPDATE                                     0x1004106CU
#define PHY_WRLVL_RESP_WAIT_CNT                             0x0806106DU
#define PHY_RDLVL_DLY_STEP                                  0x08041070U
#define PHY_RDLVL_MAX_EDGE                                  0x00091071U
#define PHY_RDDATA_EN_DLY                                   0x10051076U
#define PHY_DQ_DM_SWIZZLE0                                  0x00201077U
#define PHY_DQ_DM_SWIZZLE1                                  0x00041078U
#define PHY_CLK_WRDQS_SLAVE_DELAY                           0x0009107EU
#define PHY_WRITE_PATH_LAT_DEC                              0x1001107EU
#define PHY_RDDQS_GATE_SLAVE_DELAY                          0x00091088U
#define PHY_RDDQS_LATENCY_ADJUST                            0x10051088U
#define PHY_WRITE_PATH_LAT_ADD                              0x18031088U
#define PHY_WRITE_PATH_LAT_FRAC                             0x00081089U
#define PHY_GTLVL_LAT_ADJ_START                             0x0005108AU
#define PHY_ADR_CALVL_SWIZZLE0                              0x00201202U
#define PHY_ADR_MEAS_DLY_STEP_ENABLE                        0x10011203U
#define PHY_ADR_CALVL_RANK_CTRL                             0x18021205U
#define PHY_ADR_CALVL_OBS1                                  0x0020120AU
#define PHY_ADR_CALVL_OBS2                                  0x0020120BU
#define PHY_ADR_CALVL_DLY_STEP                              0x00041210U
#define PHY_CS_ACS_ALLOCATION_BIT2_2                        0x08021215U
#define PHY_CS_ACS_ALLOCATION_BIT3_2                        0x10021215U
#define PHY_CSLVL_OBS1                                      0x00201221U
#define PHY_CLK_DC_CAL_CLK_SEL                              0x0803123AU
#define PHY_FREQ_SEL_MULTICAST_EN                           0x08011301U
#define PHY_FREQ_SEL_INDEX                                  0x10021301U
#define SC_PHY_MANUAL_UPDATE                                0x18011304U
#define PHY_SET_DFI_INPUT_RST_PAD                           0x18011311U
#define PHY_CAL_MODE_0                                      0x000D132CU
#define PHY_CAL_INTERVAL_COUNT_0                            0x0020132DU
#define PHY_DATA_BYTE_ORDER_SEL                             0x0020133EU
#define PHY_PAD_ACS_RX_PCLK_CLK_SEL                         0x10031348U
#define PHY_PLL_CTRL                                        0x000E134BU
#define PHY_PLL_CTRL_8X                                     0x100E134BU
#define PHY_CAL_CLK_SELECT_0                                0x00031360U
#define SC_PHY_WCK_CALC                                     0x1801101AU
#define PI_START                                            0x00010800U
#define PI_TRAIN_ALL_FREQ_REQ                               0x18010802U
#define PI_CS_MAP                                           0x08020813U
#define PI_WRLVL_REQ                                        0x1001081CU
#define PI_WRLVL_CS_SW                                      0x1802081CU
#define PI_RDLVL_REQ                                        0x18010824U
#define PI_RDLVL_GATE_REQ                                   0x00010825U
#define PI_RDLVL_CS_SW                                      0x08020825U
#define PI_DRAMDCA_FLIP_MASK                                0x0802083BU
#define PI_DRAMDCA_LVL_REQ                                  0x1001083DU
#define PI_DCMLVL_CS_SW                                     0x1802083DU
#define PI_WRDCM_LVL_EN_F1                                  0x0002083FU
#define PI_DRAMDCA_LVL_EN_F1                                0x0802083FU
#define PI_WRDCM_LVL_EN_F2                                  0x1802083FU
#define PI_DRAMDCA_LVL_EN_F2                                0x00020840U
#define PI_TCKCKEL_F2                                       0x1804089DU
#define PI_INT_STATUS                                       0x00200900U
#define PI_INT_ACK_0                                        0x00200902U
#define PI_INT_ACK_1                                        0x00030903U
#define PI_ADDR_MUX_0                                       0x00030910U
#define PI_ADDR_MUX_1                                       0x08030910U
#define PI_ADDR_MUX_2                                       0x10030910U
#define PI_ADDR_MUX_3                                       0x18030910U
#define PI_ADDR_MUX_4                                       0x00030911U
#define PI_ADDR_MUX_5                                       0x08030911U
#define PI_ADDR_MUX_6                                       0x10030911U
#define PI_DATA_BYTE_SWAP_EN                                0x18010911U
#define PI_DATA_BYTE_SWAP_SLICE0                            0x00010912U
#define PI_DATA_BYTE_SWAP_SLICE1                            0x08010912U
#define PI_TDELAY_RDWR_2_BUS_IDLE_F2                        0x00080964U
#define PI_WRLAT_F2                                         0x1007096AU
#define PI_TWCKENL_WR_ADJ_F2                                0x1806096AU
#define PI_TWCKENL_RD_ADJ_F2                                0x0006096BU
#define PI_TWCKPRE_STATIC_F2                                0x0806096BU
#define PI_TWCKPRE_TOGGLE_RD_F2                             0x1806096BU
#define PI_TWCKENL_FS_ADJ_F2                                0x0006096CU
#define PI_CASLAT_F2                                        0x0807096CU
#define PI_TRFC_F2                                          0x000A0971U
#define PI_TREF_F2                                          0x00140972U
#define PI_TDFI_WRLVL_WW_F0                                 0x000A0974U
#define PI_TDFI_WRLVL_WW_F1                                 0x000A0975U
#define PI_WRLVL_EN_F2                                      0x18020975U
#define PI_TDFI_WRLVL_WW_F2                                 0x000A0976U
#define PI_WRLVL_WCKOFF_F2                                  0x10080976U
#define PI_RDLVL_EN_F2                                      0x1802097AU
#define PI_RDLVL_GATE_EN_F2                                 0x0002097BU
#define PI_RDLVL_VREF_EN_F0                                 0x1004097BU
#define PI_RDLVL_VREF_EN_F1                                 0x0004097DU
#define PI_RDLVL_VREF_EN_F2                                 0x1004097EU
#define PI_RDLAT_ADJ_F2                                     0x00090981U
#define PI_WRLAT_ADJ_F2                                     0x00070982U
#define PI_TDFI_CALVL_CC_F2                                 0x000A0985U
#define PI_TDFI_CALVL_CAPTURE_F2                            0x100A0985U
#define PI_CALVL_EN_F2                                      0x10020986U
#define PI_TCAENT_F2                                        0x000E0989U
#define PI_TVREF_SHORT_F2                                   0x000A098FU
#define PI_TVREF_LONG_F2                                    0x100A098FU
#define PI_TVRCG_ENABLE_F2                                  0x000A0990U
#define PI_TVRCG_DISABLE_F2                                 0x100A0990U
#define PI_CALVL_VREF_INITIAL_START_POINT_F0                0x00070991U
#define PI_CALVL_VREF_INITIAL_STOP_POINT_F0                 0x08070991U
#define PI_CALVL_VREF_INITIAL_START_POINT_F1                0x18070991U
#define PI_CALVL_VREF_INITIAL_STOP_POINT_F1                 0x00070992U
#define PI_CALVL_VREF_INITIAL_START_POINT_F2                0x10070992U
#define PI_CALVL_VREF_INITIAL_STOP_POINT_F2                 0x18070992U
#define PI_TDFI_CALVL_STROBE_F2                             0x08040995U
#define PI_TXP_F2                                           0x10050995U
#define PI_TMRWCKEL_F2                                      0x18080995U
#define PI_TCKEHDQS_F2                                      0x1006099DU
#define PI_TFC_F2                                           0x000A099EU
#define PI_WDQLVL_VREF_INITIAL_START_POINT_F0               0x100709A0U
#define PI_WDQLVL_VREF_INITIAL_STOP_POINT_F0                0x180709A0U
#define PI_WDQLVL_VREF_INITIAL_START_POINT_F1               0x000709A4U
#define PI_WDQLVL_VREF_INITIAL_STOP_POINT_F1                0x080709A4U
#define PI_TDFI_WDQLVL_WR_F2                                0x000A09A6U
#define PI_TDFI_WDQLVL_RW_F2                                0x100A09A6U
#define PI_WDQLVL_VREF_INITIAL_START_POINT_F2               0x000709A7U
#define PI_WDQLVL_VREF_INITIAL_STOP_POINT_F2                0x080709A7U
#define PI_WDQLVL_EN_F2                                     0x180209A7U
#define PI_MBIST_RDLAT_ADJ_F2                               0x080909A8U
#define PI_MBIST_TWCKENL_RD_ADJ_F2                          0x180609A8U
#define PI_TRTP_F2                                          0x180809B3U
#define PI_TRP_F2                                           0x000809B4U
#define PI_TRCD_F2                                          0x080809B4U
#define PI_TWTR_S_F2                                        0x180609B4U
#define PI_TWTR_L_F2                                        0x000609B5U
#define PI_TWTR_F2                                          0x100609B5U
#define PI_TWR_F2                                           0x180809B5U
#define PI_TRAS_MIN_F2                                      0x100909B6U
#define PI_TDQSCK_MAX_F2                                    0x000409B7U
#define PI_TSR_F2                                           0x100809B7U
#define PI_TMRD_F2                                          0x180809B7U
#define PI_TDFI_CTRLUPD_MAX_F2                              0x001509BCU
#define PI_TDFI_CTRLUPD_INTERVAL_F2                         0x002009BDU
#define PI_TINIT_F2                                         0x001809CCU
#define PI_TINIT1_F2                                        0x001809CDU
#define PI_TINIT3_F2                                        0x001809CEU
#define PI_TINIT4_F2                                        0x001809CFU
#define PI_TINIT5_F2                                        0x001809D0U
#define PI_TXSNR_F2                                         0x001009D1U
#define PI_TZQCAL_F2                                        0x100C09D6U
#define PI_TZQLAT_F2                                        0x000709D7U
#define PI_ZQRESET_F2                                       0x100C09D8U
#define PI_TDQ72DQ_F2                                       0x100A09DDU
#define PI_TCBTRTW_F2                                       0x000609DEU
#define PI_MC_TRFC_F2                                       0x000A09E1U
#define PI_CKE_MUX_0                                        0x000309E6U
#define PI_CKE_MUX_1                                        0x080309E6U
#define PI_SEQ_DEC_SW_CS                                    0x00020A4EU
#define PI_SW_SEQ_START                                     0x10010A4EU
#define PI_SW_SEQ_0                                         0x001B0BF1U
#define PI_SW_SEQ_1                                         0x001B0BF2U
#define PI_DFS_ENTRY_SEQ_0                                  0x001D0BFBU
#define PI_DFS_INITIALIZATION_SEQ_1                         0x001D0C24U
#define PI_DFS_INITIALIZATION_SEQ_9                         0x001D0C2CU
#define PI_DFS_INITIALIZATION_SEQ_10                        0x001D0C2DU
#define PI_SEQ_WAIT_16_F2                                   0x00180C77U
#define PI_SEQ_WAIT_17_F2                                   0x00180C7AU
#define PI_SEQ_WAIT_18_F2                                   0x00180C7DU
#define PI_SEQ_WAIT_19_F2                                   0x00180C80U
#define PI_SEQ_WAIT_20_F2                                   0x00180C83U
#define PI_SEQ_WAIT_21_F2                                   0x00180C86U
#define PI_SEQ_WAIT_22_F2                                   0x00180C89U
#define PI_SEQ_WAIT_23_F2                                   0x00180C8CU
#define PI_SEQ_WAIT_24_F2                                   0x00180C8FU
#define PI_SEQ_WAIT_25_F2                                   0x00180C92U
#define PI_SEQ_WAIT_26_F2                                   0x00180C95U
#define PI_SEQ_WAIT_30_F2                                   0x00180CA1U
#define PI_DARRAY3_0_CS0_F0                                 0x00080D0BU
#define PI_DARRAY3_1_CS0_F0                                 0x08080D0BU
#define PI_DARRAY3_0_CS0_F1                                 0x00080D15U
#define PI_DARRAY3_1_CS0_F1                                 0x08080D15U
#define PI_DARRAY3_0_CS0_F2                                 0x00080D1FU
#define PI_DARRAY3_1_CS0_F2                                 0x08080D1FU
#define PI_DARRAY3_4_CS0_F2                                 0x00080D20U
#define PI_DARRAY3_20_CS0_F2                                0x00080D24U
#define PI_DARRAY3_0_CS1_F0                                 0x00080D29U
#define PI_DARRAY3_1_CS1_F0                                 0x08080D29U
#define PI_DARRAY3_0_CS1_F1                                 0x00080D33U
#define PI_DARRAY3_1_CS1_F1                                 0x08080D33U
#define PI_DARRAY3_0_CS1_F2                                 0x00080D3DU
#define PI_DARRAY3_1_CS1_F2                                 0x08080D3DU
#define PI_DARRAY3_4_CS1_F2                                 0x00080D3EU
#define PI_DARRAY3_20_CS1_F2                                0x00080D42U
#define PI_DLL_RST                                          0x00010941U
#define PI_PWRUP_SREFRESH_EXIT                              0x1801093DU
#define PI_PWRUP_SREFRESH_EXIT                              0x1801093DU
#define PI_RDLVL_TRAIN_SEQ_1                                0x001B0C42U
#define PI_RDLVL_TRAIN_SEQ_2                                0x001B0C43U
#define PI_RDLVL_TRAIN_SEQ_3                                0x001B0C44U
#define PI_RDLVL_TRAIN_SEQ_4                                0x001B0C45U
#define PI_RDLVL_TRAIN_SEQ_5                                0x001B0C46U
#define PI_WDQLVL_VREF_EN                                   0x0804089EU
#define PI_DRAMDCA_LVL_ACTIVE_SEQ_2                         0x001B0868U
#define PI_DRAMDCA_LVL_ACTIVE_SEQ_3                         0x001B0869U
#define PI_DRAMDCA_LVL_ACTIVE_SEQ_4                         0x001B086AU
#define PHY_PER_CS_TRAINING_INDEX                           0x18011006U
#define PHY_DATA_DC_DQS_CLK_ADJUST                          0x0008108CU
#define PHY_DATA_DC_WDQLVL_ENABLE                           0x08021075U
#define PI_WDQLVL_PERIODIC                                  0x000108A0U
#define PHY_MEAS_DLY_STEP_ENABLE                            0x08061076U
#define PI_RDLVL_PERIODIC                                   0x0801082EU
#define PI_LONG_COUNT_MASK                                  0x1005090FU
#define PI_WDQLVL_INTERVAL                                  0x001008A4U
#define PI_RDLVL_INTERVAL                                   0x08100835U
#define DDR_REGDEF_ADR(regdef)  ((regdef)        & 0xFFFFU)
#define DDR_REGDEF_LEN(regdef)  (((regdef) >> 16)  & 0xFFU)
#define DDR_REGDEF_LSB(regdef)  (((regdef) >> 24)  & 0xFFU)

#endif /* DDR_REGDEF */
