/*******************************************************************************
 * DISCLAIMER
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 *******************************************************************************/

/*******************************************************************************
 * DESCRIPTION   : I2C register header
 ******************************************************************************/

#ifndef I2C_REGISTER_H__
#define I2C_REGISTER_H__

#include <remap_register.h>

/* I2C ch6 base address */
#define I2C3_BASE       (BASE_I2C3_ADDR)    /* Physical address:0xE66D0000, Logical address:0xFDCD0000 */

/* Slave control register */
#define I2C3_ICSCR      (I2C3_BASE + 0x0000U)
/* Master control register */
#define I2C3_ICMCR      (I2C3_BASE + 0x0004U)
/* Slave status register */
#define I2C3_ICSSR      (I2C3_BASE + 0x0008U)
/* Master status register */
#define I2C3_ICMSR      (I2C3_BASE + 0x000CU)
/* Slave interrupt enable register */
#define I2C3_ICSIER     (I2C3_BASE + 0x0010U)
/* Master interrupt enable register */
#define I2C3_ICMIER     (I2C3_BASE + 0x0014U)
/* Clock control register */
#define I2C3_ICCCR      (I2C3_BASE + 0x0018U)
/* Slave address register */
#define I2C3_ICSAR      (I2C3_BASE + 0x001CU)
/* Master address register */
#define I2C3_ICMAR      (I2C3_BASE + 0x0020U)
/* Recieve data register */
#define I2C3_ICRXD      (I2C3_BASE + 0x0024U)
/* Transmit data register */
#define I2C3_ICTXD      (I2C3_BASE + 0x0024U)
/* Clock control register 2 */
#define I2C3_ICCCR2     (I2C3_BASE + 0x0028U)

#endif  /* I2C_REGISTER_H__ */

