/*******************************************************************************
 * DISCLAIMER
 * This software is supplied by Renesas Electronics Corporation and is only
 * intended for use with Renesas products. No other uses are authorized. This
 * software is owned by Renesas Electronics Corporation and is protected under
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 * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
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 * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
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 * Renesas reserves the right, without notice, to make changes to this software
 * and to discontinue the availability of this software. By using this software,
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 * Copyright 2022 Renesas Electronics Corporation All rights reserved.
 *******************************************************************************/

/*******************************************************************************
 * DESCRIPTION   : CPU register access list header
 ******************************************************************************/


#ifndef CPU_H_
#define CPU_H_

/*
 * Groups
 */

/*      Name      Reg, Group        Comment */
#define EIPC         0, 0        /* Status save registers when acknowledging EI level exception SV */
#define EIPSW        1, 0        /* Status save registers when acknowledging EI level exception SV */
#define FEPC         2, 0        /* Status save registers when acknowledging FE level exception SV */
#define FEPSW        3, 0        /* Status save registers when acknowledging FE level exception SV */
#define PSW          5, 0        /* Program status word Note 1 */
#define EIIC        13, 0        /* EI level exception cause SV */
#define FEIC        14, 0        /* FE level exception cause SV */
#define CTPC        16, 0        /* CALLT execution status save register UM */
#define CTPSW       17, 0        /* CALLT execution status save register UM */
#define CTBP        20, 0        /* CALLT base pointer UM */
#define EIWR        28, 0        /* EI level exception working register SV */
#define FEWR        29, 0        /* FE level exception working register SV */
#define BSEL        31, 0        /* (Reserved for backward compatibility with V850E2 series)Note 2 SV */

#define MCFG0        0, 1        /* Machine configuration SV */
#define RBASE        2, 1        /* Reset vector base address SV */
#define EBASE        3, 1        /* Exception handler vector address SV */
#define INTBP        4, 1        /* Base address of the interrupt handler table SV */
#define MCTL         5, 1        /* CPU control SV */
#define PID          6, 1        /* Processor ID SV */
#define SCCFG       11, 1        /* SYSCALL operation setting SV */
#define SCBP        12, 1        /* SYSCALL base pointer SV */

#define HTCFG0       0, 2        /* Thread configuration SV */
#define MEA          6, 2        /* Memory error address SV */
#define ASID         7, 2        /* Address space ID SV */
#define MEI          8, 2        /* Memory error information SV */
#define ISPR        10, 2        /* Priority of interrupt being serviced SV */
#define PMR         11, 2        /* Interrupt priority masking SV */
#define ICSR        12, 2        /* Interrupt control status SV */
#define INTCFG      13, 2        /* Interrupt function setting SV */

#define MPM          0, 5        /* Memory protection operation mode setting SV */
#define MPRC         1, 5        /* MPU region control SV */
#define MPBRGN       4, 5        /* MPU base region number SV */
#define MPTRGN       5, 5        /* MPU end region number SV */
#define MCA          8, 5        /* Memory protection setting check address SV */
#define MCS          9, 5        /* Memory protection setting check size SV */
#define MCC         10, 5        /* Memory protection setting check command SV */
#define MCR         11, 5        /* Memory protection setting check result SV */

#define MPLA0        0, 6        /* Protection area minimum address SV */
#define MPUA0        1, 6        /* Protection area maximum address SV */
#define MPAT0        2, 6        /* Protection area attribute SV */
#define MPLA1        4, 6        /* Protection area minimum address SV */
#define MPUA1        5, 6        /* Protection area maximum address SV */
#define MPAT1        6, 6        /* Protection area attribute SV */
#define MPLA2        8, 6        /* Lower address of the protection area SV */
#define MPUA2        9, 6        /* Protection area maximum address SV */
#define MPAT2       10, 6        /* Protection area attribute SV */
#define MPLA3       12, 6        /* Protection area minimum address SV */
#define MPUA3       13, 6        /* Protection area maximum address SV */
#define MPAT3       14, 6        /* Protection area attribute SV */
#define MPLA4       16, 6        /* Protection area minimum address SV */
#define MPUA4       17, 6        /* Protection area maximum address SV */
#define MPAT4       18, 6        /* Protection area attribute SV */
#define MPLA5       20, 6        /* Protection area minimum address SV */
#define MPUA5       21, 6        /* Protection area maximum address SV */
#define MPAT5       22, 6        /* Protection area attribute SV */
#define MPLA6       24, 6        /* Protection area minimum address SV */
#define MPUA6       25, 6        /* Protection area maximum address SV */
#define MPAT6       26, 6        /* Protection area attribute SV */
#define MLUA7       28, 6        /* Protection area minimum address SV */
#define MPUA7       29, 6        /* Protection area maximum address SV */
#define MPAT7       30, 6        /* Protection area attribute SV */

#endif /* CPU_H_ */
