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*******************************************************************************/



/*******************************************************************************
 * DESCRIPTION   : System Controller function
 ******************************************************************************/
/******************************************************************************
 * @file          sysc.c
 * - Version      : 0.04
 * @brief
 * .
 *****************************************************************************/
/******************************************************************************
 * History : DD.MM.YYYY Version  Description
 *         : 29.09.2023 0.01     First Release
 *         : 13.11.2023 0.02     Add software reset 
 *         : 16.11.2023 0.03     Add APSREG initialization process.
 *         : 22.10.2024 0.04     Update the C4 power domain setting process.
*****************************************************************************/
#include "mem_io.h"
#include "sysc.h"
#include "cpg_register.h"
#include "log.h"
#include "cpu_on.h"
#include "ap_system_core_register.h"

/*
 * V4M turns on C4 power before starting CA
 * V4M HWM:SYSC:Operation:Power Control of Non Arm CPU Modules
 */
#if (RCAR_LSI == RCAR_V4M)
void sysc_c4_power_on(void)
{
    uint32_t reg;

    /* 
     * Need to execute APSREG initialization before C4 power on according to
     * R-Car V4M Series User's Manual '5.4.3 Register Initialization Before C4 power on'.
     */
    reg  = mem_read32(ap_core_get_ap_cluster_n_aux0_addr(0U));
    reg |= AP_CORE_APSREG_AP_CLUSTER_N_AUX0_INIT;
    mem_write32(ap_core_get_ap_cluster_n_aux0_addr(0U), reg);

    reg  = mem_read32(AP_CORE_APSREG_CCI500_AUX);
    reg |= AP_CORE_APSREG_CCI500_AUX_ACTDIS;
    mem_write32(AP_CORE_APSREG_CCI500_AUX, reg);

    /* 1.Write the set value in SYSCIER0 and SYSCIMR0 */
    reg = mem_read32(SYSC_SYSCIER0);
    mem_write32(SYSC_SYSCIER0, reg | SYSCIER0_PDR31);
    reg = mem_read32(SYSC_SYSCIMR0);
    mem_write32(SYSC_SYSCIMR0, reg | SYSCIMR0_PDR31);

    /* 2.Confirm that SYSCSR.BUSY[1] becomes 1.*/
    while (true)
    {
        reg = mem_read32(SYSC_SYSCSR);
        if (SYSCSR_BUSY1 == (reg & SYSCSR_BUSY1))
        {
            break;
        }
    }

     /* 3.Write the reset value in SRCR11 and SESTCLR11 */
    reg = mem_read32(CPG_SRCR11);
    mem_write32(CPG_SRCR11, reg | CPGSRCR_PDR11);
    mem_write32(CPG_SRSTCLR11, CPGSRCR_PDR11);

    /* 4.Write the set value in PDRONCR31 */
    mem_write32(SYSC_PDRONCR31, PDRONCR31_PWRON);

    /* 5.Confirm that SYSCISCR0.PDR[31] becomes 1.*/
    while (true)
    {
        reg = mem_read32(SYSC_SYSCISCR0);
        if (SYSCISCR0_PDR31 == (reg & SYSCISCR0_PDR31))
        {
            break;
        }
    }

    /* 6.Clear the bit31(PDR[31]) in SYSCISCR0 to 0. */
    mem_write32(SYSC_SYSCISCR0, SYSCISCR0_PDR31);
}
/* End of function sysc_c4_power_on(void) */
#endif /* RCAR_LSI == RCAR_V4M */

