/*******************************************************************************
 * Copyright (c) 2018 Renesas Electronics Corporation. All rights reserved.
 *
 * DESCRIPTION   : SCIF register header
 ******************************************************************************/


#ifndef SCIF_REGISTER_H_
#define SCIF_REGISTER_H_

#include <remap_register.h>

/* SCIF0 base address */
/* 0xE6E60000 */
#define SCIF_BASE_0	(BASE_SCIF_ADDR_0)

#define	SCIF_SCSMR_0	(SCIF_BASE_0 + 0x00U)		/*  16	Serial mode register */
#define	SCIF_SCBRR_0	(SCIF_BASE_0 + 0x04U)		/*  8	Bit rate register */
#define	SCIF_SCSCR_0	(SCIF_BASE_0 + 0x08U)		/*  16	Serial control register */
#define	SCIF_SCFTDR_0	(SCIF_BASE_0 + 0x0CU)		/*  8	Transmit FIFO data register */
#define	SCIF_SCFSR_0	(SCIF_BASE_0 + 0x10U)		/*  16	Serial status register */
#define	SCIF_SCFRDR_0	(SCIF_BASE_0 + 0x14U)		/*  8	Receive FIFO data register */
#define	SCIF_SCFCR_0	(SCIF_BASE_0 + 0x18U)		/*  16	FIFO control register */
#define	SCIF_SCFDR_0	(SCIF_BASE_0 + 0x1CU)		/*  16	FIFO data count register */
#define	SCIF_SCSPTR_0	(SCIF_BASE_0 + 0x20U)		/*  16	Serial port register */
#define	SCIF_SCLSR_0	(SCIF_BASE_0 + 0x24U)		/*  16	Line status register */
#define	SCIF_DL_0		(SCIF_BASE_0 + 0x30U)		/*  16	Frequency division register */
#define	SCIF_CKS_0		(SCIF_BASE_0 + 0x34U)		/*  16	Clock Select register */
#define	SCIF_SCFER_0	(SCIF_BASE_0 + 0x44U)		/*  16	FIFO error count register */
#define	SCIF_SCSMRIR_0	(SCIF_BASE_0 + 0x40U)		/*  16	Serial mode register */

/* SCIF3 base address */
/* 0xE6C50000 */
#define SCIF_BASE_3	(BASE_SCIF_ADDR_3)

#define	SCIF_SCSMR_3	(SCIF_BASE_3 + 0x00U)		/*  16	Serial mode register */
#define	SCIF_SCBRR_3	(SCIF_BASE_3 + 0x04U)		/*  8	Bit rate register */
#define	SCIF_SCSCR_3	(SCIF_BASE_3 + 0x08U)		/*  16	Serial control register */
#define	SCIF_SCFTDR_3	(SCIF_BASE_3 + 0x0CU)		/*  8	Transmit FIFO data register */
#define	SCIF_SCFSR_3	(SCIF_BASE_3 + 0x10U)		/*  16	Serial status register */
#define	SCIF_SCFRDR_3	(SCIF_BASE_3 + 0x14U)		/*  8	Receive FIFO data register */
#define	SCIF_SCFCR_3	(SCIF_BASE_3 + 0x18U)		/*  16	FIFO control register */
#define	SCIF_SCFDR_3	(SCIF_BASE_3 + 0x1CU)		/*  16	FIFO data count register */
#define	SCIF_SCSPTR_3	(SCIF_BASE_3 + 0x20U)		/*  16	Serial port register */
#define	SCIF_SCLSR_3	(SCIF_BASE_3 + 0x24U)		/*  16	Line status register */
#define	SCIF_DL_3		(SCIF_BASE_3 + 0x30U)		/*  16	Frequency division register */
#define	SCIF_CKS_3		(SCIF_BASE_3 + 0x34U)		/*  16	Clock Select register */
#define	SCIF_SCFER_3	(SCIF_BASE_3 + 0x44U)		/*  16	FIFO error count register */
#define	SCIF_SCSMRIR_3	(SCIF_BASE_3 + 0x40U)		/*  16	Serial mode register */


/*HSCIF0 base address*/
/* 0xE6540000 */
#define	HSCIF_BASE	(BASE_HSCIF_ADDR)

#define	HSCIF_HSSMR	(HSCIF_BASE + 0x00U)		/*  16	Serial mode register */
#define	HSCIF_HSBRR	(HSCIF_BASE + 0x04U)		/*  8	Bit rate register */
#define	HSCIF_HSSCR	(HSCIF_BASE + 0x08U)		/*  16	Serial control register */
#define	HSCIF_HSFTDR	(HSCIF_BASE + 0x0CU)		/*  8	Transmit FIFO data register */
#define	HSCIF_HSFSR	(HSCIF_BASE + 0x10U)		/*  16	Serial status register */
#define	HSCIF_HSFRDR	(HSCIF_BASE + 0x14U)		/*  8	Receive FIFO data register */
#define	HSCIF_HSFCR	(HSCIF_BASE + 0x18U)		/*  16	FIFO control register */
#define	HSCIF_HSFDR	(HSCIF_BASE + 0x1CU)		/*  16	FIFO data count register */
#define	HSCIF_HSSPTR	(HSCIF_BASE + 0x20U)		/*  16	Serial port register */
#define	HSCIF_HSLSR	(HSCIF_BASE + 0x24U)		/*  16	Line status register */

#define	HSCIF_HSSRR	(HSCIF_BASE + 0x40U)		/*  16	Sampling rate register */
#define	HSCIF_HSRER	(HSCIF_BASE + 0x44U)		/*  16	Serial error register */
#define	HSCIF_HSRTGR	(HSCIF_BASE + 0x50U)		/*  16	RTS output active trigger register */
#define	HSCIF_HSRTRGR	(HSCIF_BASE + 0x54U)		/*  16	Receive FIFO data count trigger register */
#define	HSCIF_HSTTRGR	(HSCIF_BASE + 0x58U)		/*  16	Transmit FIFO data count trigger register */

#define	HSCIF_DL	(HSCIF_BASE + 0x30U)		/*  16	Frequency division register */
#define	HSCIF_CKS	(HSCIF_BASE + 0x34U)		/*  16	Clock Select register */


#endif /* SCIF_REGISTER_H_ */
