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/*******************************************************************************
 * DESCRIPTION   : Power management driver
 ******************************************************************************/
/******************************************************************************
 * @file          cpu_on.c
 * - Version      : 0.12
 * @brief         1. Boot process of ARM CPU core.
 * .
 *****************************************************************************/
/******************************************************************************
 * History : DD.MM.YYYY Version  Description
 *         : 17.02.2022 0.01     First Release
 *         : 25.02.2022 0.02     Changed to boot Cortex-R on Core 0.
 *         : 23.03.2022 0.03     Removed unnecessary header file inclusions
 *         : 09.05.2022 0.04     Removed unnecessary processing
 *                               Removed unnecessary cast
 *         : 31.10.2022 0.05     License notation change.
 *         : 21.08.2023 0.06     Add support for V4M.
 *         : 16.11.2023 0.07     Changed not to execute ASPREG setting
 *                               in case of V4M.
 *         : 10.09.2024 0.08     Updated Region ID and RAM protection setting
 *                               for QNX.
 *         : 11.10.2024 0.09     Updated Region ID and RAM protection setting
 *                               for QNX for V4M.
 *         : 09.12.2024 0.10     Updated OTP_MEM_OTPMONITOR60 register to
 *                               OTP_MEM_OTPMONITOR17 register for V4M.
 *                               And Improve the adj_ca_variant_freq function.
 *         : 19.12.2024 0.11     Add support for booting CR52 core2.
 *         : 18.03.2025 0.12     Add INTC initialization process.
 *****************************************************************************/

#include <stdint.h>
#include <mem_io.h>
#include <cpu_on.h>
#include <rst_register.h>
#if ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M))
#include "access_protection.h"
#endif /* ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M)) */

/* ARM */
#define CA_CORE0_WUP_REQ      (0x00000001U)
#define CA_CORE0_VLD_RVBARP   (0x00000001U)
#define CR_BTMD_RBAR          (0x00000000U)
#define CR_VLD_BARP           (0x00000001U << 0U)
#define CR_BAREN_VALID        (0x00000001U << 4U)
#define CRRST                 (0x00000000U)

#define AP_CORE_APSREG_AP_CLUSTER_N_AUX0_ACTDIS1    (0x00000001U << 1U)
#define AP_CORE_APSREG_AP_CLUSTER_N_AUX0_ACTDIS0    (0x00000001U << 0U)
#define AP_CORE_APSREG_CCI500_AUX_ACTDIS            (0x00000001U << 0U)
#define AP_CORE_APSREG_P_CCI500_AUX_ASPRTM          (0x00000001U << 1U)

/* APMU */
#define APMU_BASE           (BASE_APMU_ADDR)
#define CORTEX_R_CORE       (0U)                                               /* Target is Cortex R52 core0  */
#define APMU_CRRSTCTRL      (APMU_BASE + (CORTEX_R_CORE * 0x40U) + 0x0304U)    /* Cortex-R Reset Control Register0  */
#define APMU_CRBARP         (APMU_BASE + (CORTEX_R_CORE * 0x40U) + 0x033CU)    /* Cortex-R Reset Control Register0  */
#if (RTOS_LOAD_NUM == RTOS_LOAD_NUM_3)
#define CORTEX_R_CORE2      (2U)                                               /* Target is Cortex R52 core2  */
#define APMU_CRRSTCTRL2     (APMU_BASE + (CORTEX_R_CORE2 * 0x40U) + 0x0304U)   /* Cortex-R Reset Control Register2  */
#define APMU_CRBARP2        (APMU_BASE + (CORTEX_R_CORE2 * 0x40U) + 0x033CU)   /* Cortex-R Reset Control Register2  */
#endif /* RTOS_LOAD_NUM == RTOS_LOAD_NUM_3 */

#define APMU_PWRCTRLC0      (APMU_BASE + 0x0800U)   /* Power Control Register for Core 0    */
#define APMU_RVBARPLC0      (APMU_BASE + 0x0838U)   /* Reset Vector Base Address Register Protected Low for Core 0  */
#define APMU_RVBARPHC0      (APMU_BASE + 0x083CU)   /* Reset Vector Base Address Register Protected High for Core 0 */

#define AP_CORE_BASE        (BASE_AP_CORE_ADDR)     /* 0xE6280000 */

#define AP_CORE_APSREG_AP_CLUSTER_N_AUX0(x) (AP_CORE_BASE + 0x00000010U + ((uint8_t)(x) * 0x1000U))
#define AP_CORE_APSREG_CCI500_AUX           (AP_CORE_BASE + 0x00009010U)
#define AP_CORE_APSREG_P_CCI500_AUX         (AP_CORE_BASE + 0x00029010U)

#define AP_CORE_APSREG_AP_CLUSTER_N_AUX0_INIT       (AP_CORE_APSREG_AP_CLUSTER_N_AUX0_ACTDIS1 | AP_CORE_APSREG_AP_CLUSTER_N_AUX0_ACTDIS0)

#if (RCAR_LSI == RCAR_V4H)
#define V4H_5_NI_CA           (0x53U) /* 1400[MHz] = 50/3[MHz] x (0x53 + 0x1) */
#define V4H_3_NI_CA           (0x5FU) /* 1600[MHz] = 50/3[MHz] x (0x5F + 0x1) */
#elif (RCAR_LSI == RCAR_V4M)
#define V4M_5_NI_CA           (0x5FU) /* 3200/4[MHz] = 50/3[MHz] x (0x5F + 0x1) */
#define V4M_3_NI_CA           (0x6FU) /* 3732/4[MHz] = 50/3[MHz] x (0x6F + 0x1) */
#define V4M_2_NI_CA           (0x6FU) /* 3732/4[MHz] = 50/3[MHz] x (0x6F + 0x1) */
#endif /* RCAR_LSI == RCAR_V4H */

#define CPG_PLL2CR0_KICK_BIT  (0x80000000U)
#define CPG_PLLECR_PLL2ST_BIT (0x00000200U)

#if (RCAR_LSI == RCAR_V4M)
#define CPG_BASE              (BASE_CPG_ADDR)
#define CPG_SRSTCLR5          (CPG_BASE + 0x2C94U)
#define CPG_SRSTCLR11         (CPG_BASE + 0x2CACU)
#define CPG_MSTPCR5           (CPG_BASE + 0x2D14U)
#define CPG_SRSTCLR5_VAL      (0x80000000U)
#define CPG_SRSTCLR11_VAL     (0x00080000U)
#define CPG_MSTPCR5_VAL       (0x80000000U)
#endif /* RCAR_LSI == RCAR_V4M */

static void arm_cpu_set_address(uint32_t target, uint32_t boot_addr);
#if (RCAR_LSI == RCAR_V4M)
static void intc_init(void);
#endif /* RCAR_LSI == RCAR_V4M */

static void arm_cpu_set_address(uint32_t target, uint32_t boot_addr)
{
    if(RCAR_PWR_TARGET_CR == target)
    {
        /* CR52 core0 Boot address set */
        mem_write32(APMU_CRBARP, (boot_addr | CR_VLD_BARP));
        mem_write32(APMU_CRBARP, (boot_addr | CR_VLD_BARP | CR_BAREN_VALID));
    }
#if (RTOS_LOAD_NUM == RTOS_LOAD_NUM_3)
    else if(RCAR_PWR_TARGET_CR2 == target)
    {
        /* CR52 core2 Boot address set */
        mem_write32(APMU_CRBARP2, (boot_addr | CR_VLD_BARP));
        mem_write32(APMU_CRBARP2, (boot_addr | CR_VLD_BARP | CR_BAREN_VALID));
    }
#endif /* RTOS_LOAD_NUM == RTOS_LOAD_NUM_3 */
    else
    {
        /* CA Boot address set */
        mem_write32(APMU_RVBARPLC0, boot_addr | CA_CORE0_VLD_RVBARP);
#if ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M))
#if (ACC_PROT_ENABLE == PROTECTION_ENABLE)
        mem_write32(APMU_RVBARPHC0, 0x00000020U);   /* CA boot address 0x20_XXXXXXXX */
#elif (ACC_PROT_ENABLE == PROTECTION_DISABLE)
        mem_write32(APMU_RVBARPHC0, 0x00000000U);
#endif
#else
        mem_write32(APMU_RVBARPHC0, 0x00000000U);
#endif /* ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M)) */
    }
}
/* End of function arm_cpu_set_address(uint32_t target, uint32_t boot_addr) */

void arm_cpu_on(uint32_t target, uint32_t boot_addr)
{
    uint32_t res_data;

    if(RCAR_PWR_TARGET_CR == target)
    {
        /* CR Boot address set. */
        arm_cpu_set_address(target, boot_addr);

        /* CR reset. */
        mem_write32(APMU_CRRSTCTRL, CRRST);
    }
#if (RTOS_LOAD_NUM == RTOS_LOAD_NUM_3)
    else if(RCAR_PWR_TARGET_CR2 == target)
    {
        /* CR Boot address set. */
        arm_cpu_set_address(target, boot_addr);

        /* CR reset. */
        mem_write32(APMU_CRRSTCTRL2, CRRST);
    }
#endif /* RTOS_LOAD_NUM == RTOS_LOAD_NUM_3 */
    else
    {
#if (RCAR_LSI == RCAR_V4M)
        /* For the initial setting flow of INTC, see Section 15.4.5 in
         * "R-Car Series, V4M Series User's Manual".
         */
        /* INTC initialize */
        intc_init();
#endif /* RCAR_LSI == RCAR_V4M */

        /* CA Boot address set. */
        arm_cpu_set_address(target, boot_addr);
        
#if (RCAR_LSI == RCAR_V4H)
        /*
         * In case of V4M, doesn't execute following process at Cx 2nd IPL.
         * Because following register setting is needed to execute before C4 power on.
         */
        /* AP-System core initialize */
        res_data = mem_read32(AP_CORE_APSREG_AP_CLUSTER_N_AUX0(0U));
        res_data |= AP_CORE_APSREG_AP_CLUSTER_N_AUX0_INIT;
        mem_write32(AP_CORE_APSREG_AP_CLUSTER_N_AUX0(0U), res_data);
        
        res_data = mem_read32(AP_CORE_APSREG_CCI500_AUX);
        res_data |= AP_CORE_APSREG_CCI500_AUX_ACTDIS;
        mem_write32(AP_CORE_APSREG_CCI500_AUX, res_data);
        /* AP_CORE_APSREG_P_CCI500_AUX setting is only for V4H. */
        res_data = mem_read32(AP_CORE_APSREG_P_CCI500_AUX);
        res_data |= AP_CORE_APSREG_P_CCI500_AUX_ASPRTM;
        mem_write32(AP_CORE_APSREG_P_CCI500_AUX, res_data);
#endif /* RCAR_LSI == RCAR_V4H */
    	/* CA core0 wake up sequence. */
        mem_write32(APMU_PWRCTRLC0, CA_CORE0_WUP_REQ);
        /* Wait until CA core0 wake up sequence finished. */
        do
        {
            res_data = mem_read32(APMU_PWRCTRLC0);
        }while(CA_CORE0_WUP_REQ & res_data);
    }
}
/* End of function arm_cpu_on(uint32_t target, uint32_t boot_addr) */

void adj_ca_variant_freq(void)
{
    uint32_t product   = mem_read32(OTP_MEM_OTPMONITOR17) & OTP_MEM_PRODUCT_MASK;
    uint32_t pll2_freq = mem_read32(CPG_PLL2CR0);

#if (RCAR_LSI == RCAR_V4H)
    /* Set the CPU frequency division ratio according to the type of variant. */
    switch (product)
    {
    case VARIANT_V4H_7:
        /* Default value, do nothing */;
        break;
    case VARIANT_V4H_5:
        pll2_freq = (pll2_freq & ~(0xFFU << 20U));
        pll2_freq = (pll2_freq | (V4H_5_NI_CA << 20U));
        break;
    case VARIANT_V4H_3:
        pll2_freq = (pll2_freq & ~(0xFFU << 20U));
        pll2_freq = (pll2_freq | (V4H_3_NI_CA << 20U));
        break;
    default:
        ; /* Do nothing */
        break;
    }

    if (VARIANT_V4H_5 == product || VARIANT_V4H_3 == product)
    {
        /* Write Division value to FRQCRC0 register */
        mem_write32(CPG_CPGWPR,  ~(pll2_freq));
        mem_write32(CPG_PLL2CR0, pll2_freq);

        mem_write32(CPG_CPGWPR, ~(mem_read32(CPG_PLL2CR0) | CPG_PLL2CR0_KICK_BIT));
        mem_write32(CPG_PLL2CR0, (mem_read32(CPG_PLL2CR0) | CPG_PLL2CR0_KICK_BIT));

        while ((mem_read32(CPG_PLLECR) & CPG_PLLECR_PLL2ST_BIT) != CPG_PLLECR_PLL2ST_BIT)
        {
            ;
        }
    }
#elif (RCAR_LSI == RCAR_V4M)
    /* Set the CPU frequency division ratio according to the type of variant. */
    switch (product)
    {
    case VARIANT_V4M_7:
        /* Default value, do nothing */;
        break;
    case VARIANT_V4M_5:
        pll2_freq = (pll2_freq & ~(0xFFU << 20U));
        pll2_freq = (pll2_freq | (V4M_5_NI_CA << 20U));
        break;
    case VARIANT_V4M_3:
        pll2_freq = (pll2_freq & ~(0xFFU << 20U));
        pll2_freq = (pll2_freq | (V4M_3_NI_CA << 20U));
        break;
    case VARIANT_V4M_2:
        pll2_freq = (pll2_freq & ~(0xFFU << 20U));
        pll2_freq = (pll2_freq | (V4M_2_NI_CA << 20U));
        break;
    default:
        ; /* Do nothing */
        break;
    }

    if (VARIANT_V4M_5 == product || VARIANT_V4M_3 == product || VARIANT_V4M_2 == product)
    {
        /* Write Division value to FRQCRC0 register */
        mem_write32(CPG_CPGWPR,  ~(pll2_freq));
        mem_write32(CPG_PLL2CR0, pll2_freq);

        mem_write32(CPG_CPGWPR, ~(mem_read32(CPG_PLL2CR0) | CPG_PLL2CR0_KICK_BIT));
        mem_write32(CPG_PLL2CR0, (mem_read32(CPG_PLL2CR0) | CPG_PLL2CR0_KICK_BIT));

        while ((mem_read32(CPG_PLLECR) & CPG_PLLECR_PLL2ST_BIT) != CPG_PLLECR_PLL2ST_BIT)
        {
            ;
        }
    }
#endif /* RCAR_LSI == RCAR_V4H */
}
/* End of function adj_cpu_variant_freq(void) */

#if (RCAR_LSI == RCAR_V4M)
static void intc_init(void)
{
    uint32_t reg;

    mem_write32(CPG_CPGWPR, ~(CPG_SRSTCLR5_VAL));
    mem_write32(CPG_SRSTCLR5, CPG_SRSTCLR5_VAL);

    mem_write32(CPG_CPGWPR, ~(CPG_SRSTCLR11_VAL));
    mem_write32(CPG_SRSTCLR11, CPG_SRSTCLR11_VAL);

    mem_write32(CPG_CPGWPR, ~(CPG_MSTPCR5_VAL));
    reg = mem_read32(CPG_MSTPCR5);
    reg |= CPG_MSTPCR5_VAL;
    mem_write32(CPG_MSTPCR5, reg);
}
/* End of function intc_init(void) */
#endif /* RCAR_LSI == RCAR_V4M */
