/*
 * Copyright (c) 2018-2025 Renesas Electronics Corporation. All rights reserved.
 */

#ifndef REG_RCARGEN3_H
#define REG_RCARGEN3_H

#define	RCAR_CNTC_BASE			(0xE6080000)					/* The base addess of generic timer control register */
#define CNTFID_OFF			0x020
#define CNTCR_OFF			0x000


//CPG for S4
#define CPG_BASE						(0xE6150000U)
#define	CPG_CPGWPCR						(CPG_BASE + 0x0004U)	// R/W	32	CPG Write Protect Control Register
#define	CPG_CPGWPR						(CPG_BASE + 0x0000U)	// R/W	32	CPG Write Protect Register
#define	CPG_SD0CKCR						(CPG_BASE + 0x0870U)	// R/W	32	SD-IF0 clock frequency control register
#define	CPG_RPCCKCR						(CPG_BASE + 0x0874U)	// R/W	32	RPC clock frequency control register
//MSTPRST
#define	CPG_SRCR0						(CPG_BASE + 0x2C00U)	// R/W	32	Software reset register 0 
#define	CPG_SRCR1						(CPG_BASE + 0x2C04U)	// R/W	32	Software reset register 1 
#define	CPG_SRCR2						(CPG_BASE + 0x2C08U)	// R/W	32	Software reset register 2 
#define	CPG_SRCR3						(CPG_BASE + 0x2C0CU)	// R/W	32	Software reset register 3 
#define	CPG_SRCR4						(CPG_BASE + 0x2C10U)	// R/W	32	Software reset register 4 
#define	CPG_SRCR5						(CPG_BASE + 0x2C14U)	// R/W	32	Software reset register 5 
#define	CPG_SRCR6						(CPG_BASE + 0x2C18U)	// R/W	32	Software reset register 6 
#define	CPG_SRCR7						(CPG_BASE + 0x2C1CU)	// R/W	32	Software reset register 7 
#define	CPG_SRCR8						(CPG_BASE + 0x2C20U)	// R/W	32	Software reset register 8 
#define	CPG_SRCR9						(CPG_BASE + 0x2C24U)	// R/W	32	Software reset register 9 
#define	CPG_SRCR10						(CPG_BASE + 0x2C28U)	// R/W	32	Software reset register 10 
#define	CPG_SRCR11						(CPG_BASE + 0x2C2CU)	// R/W	32	Software reset register 11 
#define	CPG_SRCR12						(CPG_BASE + 0x2C30U)	// R/W	32	Software reset register 12 
#define	CPG_SRCR13						(CPG_BASE + 0x2C34U)	// R/W	32	Software reset register 13
#define	CPG_SRCR14						(CPG_BASE + 0x2C38U)	// R/W	32	Software reset register 14 
#define	CPG_SRCR15						(CPG_BASE + 0x2C3CU)	// R/W	32	Software reset register 15 
#define	CPG_SRCR16						(CPG_BASE + 0x2C40U)	// R/W	32	Software reset register 16
#define	CPG_SRCR17						(CPG_BASE + 0x2C44U)	// R/W	32	Software reset register 17
#define	CPG_SRCR18						(CPG_BASE + 0x2C48U)	// R/W	32	Software reset register 18 
#define	CPG_SRCR19						(CPG_BASE + 0x2C4CU)	// R/W	32	Software reset register 19
#define	CPG_SRCR20						(CPG_BASE + 0x2C50U)	// R/W	32	Software reset register 20
#define	CPG_SRCR21						(CPG_BASE + 0x2C54U)	// R/W	32	Software reset register 21
#define	CPG_SRCR22						(CPG_BASE + 0x2C58U)	// R/W	32	Software reset register 22 
#define	CPG_SRCR23						(CPG_BASE + 0x2C5CU)	// R/W	32	Software reset register 23
#define	CPG_SRSTCLR0					(CPG_BASE + 0x2C80U)	// W	32	Software reset clearing register 0
#define	CPG_SRSTCLR1					(CPG_BASE + 0x2C84U)	// W	32	Software reset clearing register 1
#define	CPG_SRSTCLR2					(CPG_BASE + 0x2C88U)	// W	32	Software reset clearing register 2
#define	CPG_SRSTCLR3					(CPG_BASE + 0x2C8CU)	// W	32	Software reset clearing register 3
#define	CPG_SRSTCLR4					(CPG_BASE + 0x2C90U)	// W	32	Software reset clearing register 4
#define	CPG_SRSTCLR5					(CPG_BASE + 0x2C94U)	// W	32	Software reset clearing register 5
#define	CPG_SRSTCLR6					(CPG_BASE + 0x2C98U)	// W	32	Software reset clearing register 6
#define	CPG_SRSTCLR7					(CPG_BASE + 0x2C9CU)	// W	32	Software reset clearing register 7
#define	CPG_SRSTCLR8					(CPG_BASE + 0x2CA0U)	// W	32	Software reset clearing register 8
#define	CPG_SRSTCLR9					(CPG_BASE + 0x2CA4U)	// W	32	Software reset clearing register 9
#define	CPG_SRSTCLR10					(CPG_BASE + 0x2CA8U)	// W	32	Software reset clearing register 10
#define	CPG_SRSTCLR11					(CPG_BASE + 0x2CACU)	// W	32	Software reset clearing register 11
#define	CPG_SRSTCLR12					(CPG_BASE + 0x2CB0U)	// W	32	Software reset clearing register 12
#define	CPG_SRSTCLR13					(CPG_BASE + 0x2CB4U)	// W	32	Software reset clearing register 13
#define	CPG_SRSTCLR14					(CPG_BASE + 0x2CB8U)	// W	32	Software reset clearing register 14
#define	CPG_SRSTCLR15					(CPG_BASE + 0x2CBCU)	// W	32	Software reset clearing register 15
#define	CPG_SRSTCLR16					(CPG_BASE + 0x2CC0U)	// W	32	Software reset clearing register 16
#define	CPG_SRSTCLR17					(CPG_BASE + 0x2CC4U)	// W	32	Software reset clearing register 17
#define	CPG_SRSTCLR18					(CPG_BASE + 0x2CC8U)	// W	32	Software reset clearing register 18
#define	CPG_SRSTCLR19					(CPG_BASE + 0x2CCCU)	// W	32	Software reset clearing register 19
#define	CPG_SRSTCLR20					(CPG_BASE + 0x2CD0U)	// W	32	Software reset clearing register 20
#define	CPG_SRSTCLR21					(CPG_BASE + 0x2CD4U)	// W	32	Software reset clearing register 21
#define	CPG_SRSTCLR22					(CPG_BASE + 0x2CD8U)	// W	32	Software reset clearing register 22
#define	CPG_SRSTCLR23					(CPG_BASE + 0x2CDCU)	// W	32	Software reset clearing register 23
#define	CPG_MSTPCR0						(CPG_BASE + 0x2D00U)	// R/W	32	Domain0 module stop control register 0
#define	CPG_MSTPCR1						(CPG_BASE + 0x2D04U)	// R/W	32	Domain0 module stop control register 1
#define	CPG_MSTPCR2						(CPG_BASE + 0x2D08U)	// R/W	32	Domain0 module stop control register 2
#define	CPG_MSTPCR3						(CPG_BASE + 0x2D0CU)	// R/W	32	Domain0 module stop control register 3
#define	CPG_MSTPCR4						(CPG_BASE + 0x2D10U)	// R/W	32	Domain0 module stop control register 4
#define	CPG_MSTPCR5						(CPG_BASE + 0x2D14U)	// R/W	32	Domain0 module stop control register 5
#define	CPG_MSTPCR6						(CPG_BASE + 0x2D18U)	// R/W	32	Domain0 module stop control register 6
#define	CPG_MSTPCR7						(CPG_BASE + 0x2D1CU)	// R/W	32	Domain0 module stop control register 7
#define	CPG_MSTPCR8						(CPG_BASE + 0x2D20U)	// R/W	32	Domain0 module stop control register 8
#define	CPG_MSTPCR9						(CPG_BASE + 0x2D24U)	// R/W	32	Domain0 module stop control register 9
#define	CPG_MSTPCR10					(CPG_BASE + 0x2D28U)	// R/W	32	Domain0 module stop control register 10
#define	CPG_MSTPCR11					(CPG_BASE + 0x2D2CU)	// R/W	32	Domain0 module stop control register 11
#define	CPG_MSTPCR12					(CPG_BASE + 0x2D30U)	// R/W	32	Domain0 module stop control register 12
#define	CPG_MSTPCR13					(CPG_BASE + 0x2D34U)	// R/W	32	Domain0 module stop control register 13
#define	CPG_MSTPCR14					(CPG_BASE + 0x2D38U)	// R/W	32	Domain0 module stop control register 14
#define	CPG_MSTPCR15					(CPG_BASE + 0x2D3CU)	// R/W	32	Domain0 module stop control register 15
#define	CPG_MSTPCR16					(CPG_BASE + 0x2D40U)	// R/W	32	Domain0 module stop control register 16
#define	CPG_MSTPCR17					(CPG_BASE + 0x2D44U)	// R/W	32	Domain0 module stop control register 17
#define	CPG_MSTPCR18					(CPG_BASE + 0x2D48U)	// R/W	32	Domain0 module stop control register 18
#define	CPG_MSTPCR19					(CPG_BASE + 0x2D4CU)	// R/W	32	Domain0 module stop control register 19
#define	CPG_MSTPCR20					(CPG_BASE + 0x2D50U)	// R/W	32	Domain0 module stop control register 20
#define	CPG_MSTPCR21					(CPG_BASE + 0x2D54U)	// R/W	32	Domain0 module stop control register 21
#define	CPG_MSTPCR22					(CPG_BASE + 0x2D58U)	// R/W	32	Domain0 module stop control register 22
#define	CPG_MSTPCR23					(CPG_BASE + 0x2D5CU)	// R/W	32	Domain0 module stop control register 23
#define	CPG_MSTPSR0						(CPG_BASE + 0x2E00U)	// R	32	Module stop status register 0
#define	CPG_MSTPSR1						(CPG_BASE + 0x2E04U)	// R	32	Module stop status register 1
#define	CPG_MSTPSR2						(CPG_BASE + 0x2E08U)	// R	32	Module stop status register 2
#define	CPG_MSTPSR3						(CPG_BASE + 0x2E0CU)	// R	32	Module stop status register 3
#define	CPG_MSTPSR4						(CPG_BASE + 0x2E10U)	// R	32	Module stop status register 4
#define	CPG_MSTPSR5						(CPG_BASE + 0x2E14U)	// R	32	Module stop status register 5
#define	CPG_MSTPSR6						(CPG_BASE + 0x2E18U)	// R	32	Module stop status register 6
#define	CPG_MSTPSR7						(CPG_BASE + 0x2E1CU)	// R	32	Module stop status register 7
#define	CPG_MSTPSR8						(CPG_BASE + 0x2E20U)	// R	32	Module stop status register 8
#define	CPG_MSTPSR9						(CPG_BASE + 0x2E24U)	// R	32	Module stop status register 9
#define	CPG_MSTPSR10					(CPG_BASE + 0x2E28U)	// R	32	Module stop status register 10
#define	CPG_MSTPSR11					(CPG_BASE + 0x2E2CU)	// R	32	Module stop status register 11
#define	CPG_MSTPSR12					(CPG_BASE + 0x2E30U)	// R	32	Module stop status register 12
#define	CPG_MSTPSR13					(CPG_BASE + 0x2E34U)	// R	32	Module stop status register 13
#define	CPG_MSTPSR14					(CPG_BASE + 0x2E38U)	// R	32	Module stop status register 14
#define	CPG_MSTPSR15					(CPG_BASE + 0x2E3CU)	// R	32	Module stop status register 15
#define	CPG_MSTPSR16					(CPG_BASE + 0x2E40U)	// R	32	Module stop status register 16
#define	CPG_MSTPSR17					(CPG_BASE + 0x2E44U)	// R	32	Module stop status register 17
#define	CPG_MSTPSR18					(CPG_BASE + 0x2E48U)	// R	32	Module stop status register 18
#define	CPG_MSTPSR19					(CPG_BASE + 0x2E4CU)	// R	32	Module stop status register 19
#define	CPG_MSTPSR20					(CPG_BASE + 0x2E50U)	// R	32	Module stop status register 20
#define	CPG_MSTPSR21					(CPG_BASE + 0x2E54U)	// R	32	Module stop status register 21
#define	CPG_MSTPSR22					(CPG_BASE + 0x2E58U)	// R	32	Module stop status register 22
#define	CPG_MSTPSR23					(CPG_BASE + 0x2E5CU)	// R	32	Module stop status register 23


//LBSC.h
#define	LBSC_CS0CTRL					0xEE220200	// R/W	32	Area 0 control register
#define	LBSC_CS1CTRL					0xEE220204	// R/W	32	Area 1 control register
#define	LBSC_CSWCR0						0xEE220230	// R/W	32	Area 0 RD/WE pulse control register
#define	LBSC_CSWCR1						0xEE220234	// R/W	32	Area 1 RD/WE pulse control register
#define	LBSC_CSPWCR0					0xEE220280	// R/W	32	Area 0 external wait control register
#define	LBSC_CSPWCR1					0xEE220284	// R/W	32	Area 1 external wait control register
#define	LBSC_EXWTSYNC					0xEE2202A0	// R/W	32	External wait input control register
#define	LBSC_CS0BSTCTL					0xEE2202B0	// R/W	32	Area 0 burst control register
#define	LBSC_CS0BTPH					0xEE2202B4	// R/W	32	Area 0 burst pitch set register
#define	LBSC_CS1GDST					0xEE2202C0	// R/W	32	Area 1 guard setting register
#define	LBSC_BCINTSR					0xEE220330	// R	32	BSC interrupt source status register
#define	LBSC_BCINTCR					0xEE220334	// -/WC1	32	BSC interrupt source clear register
#define	LBSC_BCINTMR					0xEE220338	// R/W	32	BSC interrupt enable register
#define	LBSC_EXWTSTS					0xEE220344	// R	32	External wait status register
#define	LBSC_EXBCT						0xEE2203C0	// R/W	32	EX-BUS wait timeout detection base counter register
#define	LBSC_EXTCT						0xEE2203C4	// R/W	32	EX-BUS wait timeout detection counter register
#define	LBSC_EXTSR						0xEE220010	// R/WC1	32	EX-BUS wait timeout detection access source indication register
#define	LBSC_EXTADR						0xEE220014	// R/W	32	EX-BUS wait timeout detection address indication register



//PFC for S4
#define PFC_BASE						(0xE6050000)
#define PFC_MCU_BASE					(0xFFD90000)

#define PFC_PORT_GRP0					(0x00000000U)   /* Port Group0/4 */
#define PFC_PORT_GRP1					(0x00000800U)   /* Port Group1/5 */
#define PFC_PORT_GRP2					(0x00001000U)   /* Port Group2/6 */
#define PFC_PORT_GRP3					(0x00001800U)   /* Port Group3/7 */
#define PFC_SYS_GRP						(0x00008000U)
#define PFC_PORT_GRP_MASK				(0xFFFFF800U)
#define PFC_PMMR(addr)					((addr) & PFC_PORT_GRP_MASK + 0x0000U)

/* Port Group0 */
#define PFC_PMMR0						(PFC_BASE + PFC_PORT_GRP0 + 0x0000U)
#define PFC_GPSR0						(PFC_BASE + PFC_PORT_GRP0 + 0x0040U)
#define PFC_IP0SR0						(PFC_BASE + PFC_PORT_GRP0 + 0x0060U)
#define PFC_IP1SR0						(PFC_BASE + PFC_PORT_GRP0 + 0x0064U)
#define PFC_IP2SR0						(PFC_BASE + PFC_PORT_GRP0 + 0x0068U)
#define PFC_IP3SR0						(PFC_BASE + PFC_PORT_GRP0 + 0x006CU)
#define PFC_DRV0CTRL0					(PFC_BASE + PFC_PORT_GRP0 + 0x0080U)
#define PFC_DRV1CTRL0					(PFC_BASE + PFC_PORT_GRP0 + 0x0084U)
#define PFC_DRV2CTRL0					(PFC_BASE + PFC_PORT_GRP0 + 0x0088U)
#define PFC_DRV3CTRL0					(PFC_BASE + PFC_PORT_GRP0 + 0x008CU)
#define PFC_POC0						(PFC_BASE + PFC_PORT_GRP0 + 0x00A0U)
#define PFC_PUEN0						(PFC_BASE + PFC_PORT_GRP0 + 0x00C0U)
#define PFC_PUD0						(PFC_BASE + PFC_PORT_GRP0 + 0x00E0U)
#define PFC_MOD_SEL0					(PFC_BASE + PFC_PORT_GRP0 + 0x0100U)
#define GPIO_IOINTSEL0					(PFC_BASE + PFC_PORT_GRP0 + 0x0180U)
#define GPIO_INOUTSEL0					(PFC_BASE + PFC_PORT_GRP0 + 0x0184U)
#define GPIO_OUTDT0						(PFC_BASE + PFC_PORT_GRP0 + 0x0188U)
#define GPIO_INDT0						(PFC_BASE + PFC_PORT_GRP0 + 0x018CU)
#define GPIO_INTDT0						(PFC_BASE + PFC_PORT_GRP0 + 0x0190U)
#define GPIO_INTCLR0					(PFC_BASE + PFC_PORT_GRP0 + 0x0194U)
#define GPIO_INTMSK0					(PFC_BASE + PFC_PORT_GRP0 + 0x0198U)
#define GPIO_MSKCLR0					(PFC_BASE + PFC_PORT_GRP0 + 0x019CU)
#define GPIO_POSNEG0					(PFC_BASE + PFC_PORT_GRP0 + 0x01A0U)
/* Port Group1 */
#define PFC_PMMR1		(PFC_BASE + PFC_PORT_GRP1 + 0x0000U)
#define PFC_GPSR1		(PFC_BASE + PFC_PORT_GRP1 + 0x0040U)
#define PFC_IP0SR1		(PFC_BASE + PFC_PORT_GRP1 + 0x0060U)
#define PFC_IP1SR1		(PFC_BASE + PFC_PORT_GRP1 + 0x0064U)
#define PFC_IP2SR1		(PFC_BASE + PFC_PORT_GRP1 + 0x0068U)
#define PFC_IP3SR1		(PFC_BASE + PFC_PORT_GRP1 + 0x006CU)
#define PFC_DRV0CTRL1		(PFC_BASE + PFC_PORT_GRP1 + 0x0080U)
#define PFC_DRV1CTRL1		(PFC_BASE + PFC_PORT_GRP1 + 0x0084U)
#define PFC_DRV2CTRL1		(PFC_BASE + PFC_PORT_GRP1 + 0x0088U)
#define PFC_DRV3CTRL1		(PFC_BASE + PFC_PORT_GRP1 + 0x008CU)
#define PFC_POC1		(PFC_BASE + PFC_PORT_GRP1 + 0x00A0U)
#define PFC_PUEN1		(PFC_BASE + PFC_PORT_GRP1 + 0x00C0U)
#define PFC_PUD1		(PFC_BASE + PFC_PORT_GRP1 + 0x00E0U)
#define PFC_MOD_SEL1		(PFC_BASE + PFC_PORT_GRP1 + 0x0100U)
#define GPIO_IOINTSEL1		(PFC_BASE + PFC_PORT_GRP1 + 0x0180U)
#define GPIO_INOUTSEL1		(PFC_BASE + PFC_PORT_GRP1 + 0x0184U)
#define GPIO_OUTDT1		(PFC_BASE + PFC_PORT_GRP1 + 0x0188U)
#define GPIO_INDT1		(PFC_BASE + PFC_PORT_GRP1 + 0x018CU)
#define GPIO_INTDT1		(PFC_BASE + PFC_PORT_GRP1 + 0x0190U)
#define GPIO_INTCLR1		(PFC_BASE + PFC_PORT_GRP1 + 0x0194U)
#define GPIO_INTMSK1		(PFC_BASE + PFC_PORT_GRP1 + 0x0198U)
#define GPIO_MSKCLR1		(PFC_BASE + PFC_PORT_GRP1 + 0x019CU)
#define GPIO_POSNEG1		(PFC_BASE + PFC_PORT_GRP1 + 0x01A0U)
/* Port Group2 */
#define PFC_PMMR2		(PFC_BASE + PFC_PORT_GRP2 + 0x0000U)
#define PFC_GPSR2		(PFC_BASE + PFC_PORT_GRP2 + 0x0040U)
#define PFC_IP0SR2		(PFC_BASE + PFC_PORT_GRP2 + 0x0060U)
#define PFC_IP1SR2		(PFC_BASE + PFC_PORT_GRP2 + 0x0064U)
#define PFC_IP2SR2		(PFC_BASE + PFC_PORT_GRP2 + 0x0068U)
#define PFC_IP3SR2		(PFC_BASE + PFC_PORT_GRP2 + 0x006CU)
#define PFC_DRV0CTRL2		(PFC_BASE + PFC_PORT_GRP2 + 0x0080U)
#define PFC_DRV1CTRL2		(PFC_BASE + PFC_PORT_GRP2 + 0x0084U)
#define PFC_DRV2CTRL2		(PFC_BASE + PFC_PORT_GRP2 + 0x0088U)
#define PFC_DRV3CTRL2		(PFC_BASE + PFC_PORT_GRP2 + 0x008CU)
#define PFC_POC2		(PFC_BASE + PFC_PORT_GRP2 + 0x00A0U)
#define PFC_PUEN2		(PFC_BASE + PFC_PORT_GRP2 + 0x00C0U)
#define PFC_PUD2		(PFC_BASE + PFC_PORT_GRP2 + 0x00E0U)
#define PFC_MOD_SEL2		(PFC_BASE + PFC_PORT_GRP2 + 0x0100U)
#define GPIO_IOINTSEL2		(PFC_BASE + PFC_PORT_GRP2 + 0x0180U)
#define GPIO_INOUTSEL2		(PFC_BASE + PFC_PORT_GRP2 + 0x0184U)
#define GPIO_OUTDT2		(PFC_BASE + PFC_PORT_GRP2 + 0x0188U)
#define GPIO_INDT2		(PFC_BASE + PFC_PORT_GRP2 + 0x018CU)
#define GPIO_INTDT2		(PFC_BASE + PFC_PORT_GRP2 + 0x0190U)
#define GPIO_INTCLR2		(PFC_BASE + PFC_PORT_GRP2 + 0x0194U)
#define GPIO_INTMSK2		(PFC_BASE + PFC_PORT_GRP2 + 0x0198U)
#define GPIO_MSKCLR2		(PFC_BASE + PFC_PORT_GRP2 + 0x019CU)
#define GPIO_POSNEG2		(PFC_BASE + PFC_PORT_GRP2 + 0x01A0U)
/* Port Group3 */
#define PFC_PMMR3		(PFC_BASE + PFC_PORT_GRP3 + 0x0000U)
#define PFC_GPSR3		(PFC_BASE + PFC_PORT_GRP3 + 0x0040U)
#define PFC_IP0SR3		(PFC_BASE + PFC_PORT_GRP3 + 0x0060U)
#define PFC_IP1SR3		(PFC_BASE + PFC_PORT_GRP3 + 0x0064U)
#define PFC_IP2SR3		(PFC_BASE + PFC_PORT_GRP3 + 0x0068U)
#define PFC_IP3SR3		(PFC_BASE + PFC_PORT_GRP3 + 0x006CU)
#define PFC_DRV0CTRL3		(PFC_BASE + PFC_PORT_GRP3 + 0x0080U)
#define PFC_DRV1CTRL3		(PFC_BASE + PFC_PORT_GRP3 + 0x0084U)
#define PFC_DRV2CTRL3		(PFC_BASE + PFC_PORT_GRP3 + 0x0088U)
#define PFC_DRV3CTRL3		(PFC_BASE + PFC_PORT_GRP3 + 0x008CU)
#define PFC_POC3		(PFC_BASE + PFC_PORT_GRP3 + 0x00A0U)
#define PFC_PUEN3		(PFC_BASE + PFC_PORT_GRP3 + 0x00C0U)
#define PFC_PUD3		(PFC_BASE + PFC_PORT_GRP3 + 0x00E0U)
#define PFC_MOD_SEL3		(PFC_BASE + PFC_PORT_GRP3 + 0x0100U)
#define GPIO_IOINTSEL3		(PFC_BASE + PFC_PORT_GRP3 + 0x0180U)
#define GPIO_INOUTSEL3		(PFC_BASE + PFC_PORT_GRP3 + 0x0184U)
#define GPIO_OUTDT3		(PFC_BASE + PFC_PORT_GRP3 + 0x0188U)
#define GPIO_INDT3		(PFC_BASE + PFC_PORT_GRP3 + 0x018CU)
#define GPIO_INTDT3		(PFC_BASE + PFC_PORT_GRP3 + 0x0190U)
#define GPIO_INTCLR3		(PFC_BASE + PFC_PORT_GRP3 + 0x0194U)
#define GPIO_INTMSK3		(PFC_BASE + PFC_PORT_GRP3 + 0x0198U)
#define GPIO_MSKCLR3		(PFC_BASE + PFC_PORT_GRP3 + 0x019CU)
#define GPIO_POSNEG3		(PFC_BASE + PFC_PORT_GRP3 + 0x01A0U)
/* Port Group4 */
#define PFC_PMMR4		(PFC_MCU_BASE + PFC_PORT_GRP0 + 0x0000U)
#define PFC_GPSR4		(PFC_MCU_BASE + PFC_PORT_GRP0 + 0x0040U)
#define PFC_IP0SR4		(PFC_MCU_BASE + PFC_PORT_GRP0 + 0x0060U)
#define PFC_IP1SR4		(PFC_MCU_BASE + PFC_PORT_GRP0 + 0x0064U)
#define PFC_IP2SR4		(PFC_MCU_BASE + PFC_PORT_GRP0 + 0x0068U)
#define PFC_IP3SR4		(PFC_MCU_BASE + PFC_PORT_GRP0 + 0x006CU)
#define PFC_DRV0CTRL4		(PFC_MCU_BASE + PFC_PORT_GRP0 + 0x0080U)
#define PFC_DRV1CTRL4		(PFC_MCU_BASE + PFC_PORT_GRP0 + 0x0084U)
#define PFC_DRV2CTRL4		(PFC_MCU_BASE + PFC_PORT_GRP0 + 0x0088U)
#define PFC_DRV3CTRL4		(PFC_MCU_BASE + PFC_PORT_GRP0 + 0x008CU)
#define PFC_POC4		(PFC_MCU_BASE + PFC_PORT_GRP0 + 0x00A0U)
#define PFC_PUEN4		(PFC_MCU_BASE + PFC_PORT_GRP0 + 0x00C0U)
#define PFC_PUD4		(PFC_MCU_BASE + PFC_PORT_GRP0 + 0x00E0U)
#define PFC_MOD_SEL4		(PFC_MCU_BASE + PFC_PORT_GRP0 + 0x0100U)
#define GPIO_IOINTSEL4		(PFC_MCU_BASE + PFC_PORT_GRP0 + 0x0180U)
#define GPIO_INOUTSEL4		(PFC_MCU_BASE + PFC_PORT_GRP0 + 0x0184U)
#define GPIO_OUTDT4		(PFC_MCU_BASE + PFC_PORT_GRP0 + 0x0188U)
#define GPIO_INDT4		(PFC_MCU_BASE + PFC_PORT_GRP0 + 0x018CU)
#define GPIO_INTDT4		(PFC_MCU_BASE + PFC_PORT_GRP0 + 0x0190U)
#define GPIO_INTCLR4		(PFC_MCU_BASE + PFC_PORT_GRP0 + 0x0194U)
#define GPIO_INTMSK4		(PFC_MCU_BASE + PFC_PORT_GRP0 + 0x0198U)
#define GPIO_MSKCLR4		(PFC_MCU_BASE + PFC_PORT_GRP0 + 0x019CU)
#define GPIO_POSNEG4		(PFC_MCU_BASE + PFC_PORT_GRP0 + 0x01A0U)
/* Port Group5 */
#define PFC_PMMR5		(PFC_MCU_BASE + PFC_PORT_GRP1 + 0x0000U)
#define PFC_GPSR5		(PFC_MCU_BASE + PFC_PORT_GRP1 + 0x0040U)
#define PFC_IP0SR5		(PFC_MCU_BASE + PFC_PORT_GRP1 + 0x0060U)
#define PFC_IP1SR5		(PFC_MCU_BASE + PFC_PORT_GRP1 + 0x0064U)
#define PFC_IP2SR5		(PFC_MCU_BASE + PFC_PORT_GRP1 + 0x0068U)
#define PFC_IP3SR5		(PFC_MCU_BASE + PFC_PORT_GRP1 + 0x006CU)
#define PFC_DRV0CTRL5		(PFC_MCU_BASE + PFC_PORT_GRP1 + 0x0080U)
#define PFC_DRV1CTRL5		(PFC_MCU_BASE + PFC_PORT_GRP1 + 0x0084U)
#define PFC_DRV2CTRL5		(PFC_MCU_BASE + PFC_PORT_GRP1 + 0x0088U)
#define PFC_DRV3CTRL5		(PFC_MCU_BASE + PFC_PORT_GRP1 + 0x008CU)
#define PFC_POC5		(PFC_MCU_BASE + PFC_PORT_GRP1 + 0x00A0U)
#define PFC_PUEN5		(PFC_MCU_BASE + PFC_PORT_GRP1 + 0x00C0U)
#define PFC_PUD5		(PFC_MCU_BASE + PFC_PORT_GRP1 + 0x00E0U)
#define PFC_MOD_SEL5		(PFC_MCU_BASE + PFC_PORT_GRP1 + 0x0100U)
#define GPIO_IOINTSEL5		(PFC_MCU_BASE + PFC_PORT_GRP1 + 0x0180U)
#define GPIO_INOUTSEL5		(PFC_MCU_BASE + PFC_PORT_GRP1 + 0x0184U)
#define GPIO_OUTDT5		(PFC_MCU_BASE + PFC_PORT_GRP1 + 0x0188U)
#define GPIO_INDT5		(PFC_MCU_BASE + PFC_PORT_GRP1 + 0x018CU)
#define GPIO_INTDT5		(PFC_MCU_BASE + PFC_PORT_GRP1 + 0x0190U)
#define GPIO_INTCLR5		(PFC_MCU_BASE + PFC_PORT_GRP1 + 0x0194U)
#define GPIO_INTMSK5		(PFC_MCU_BASE + PFC_PORT_GRP1 + 0x0198U)
#define GPIO_MSKCLR5		(PFC_MCU_BASE + PFC_PORT_GRP1 + 0x019CU)
#define GPIO_POSNEG5		(PFC_MCU_BASE + PFC_PORT_GRP1 + 0x01A0U)
/* Port Group6 */
#define PFC_PMMR6		(PFC_MCU_BASE + PFC_PORT_GRP2 + 0x0000U)
#define PFC_GPSR6		(PFC_MCU_BASE + PFC_PORT_GRP2 + 0x0040U)
#define PFC_IP0SR6		(PFC_MCU_BASE + PFC_PORT_GRP2 + 0x0060U)
#define PFC_IP1SR6		(PFC_MCU_BASE + PFC_PORT_GRP2 + 0x0064U)
#define PFC_IP2SR6		(PFC_MCU_BASE + PFC_PORT_GRP2 + 0x0068U)
#define PFC_IP3SR6		(PFC_MCU_BASE + PFC_PORT_GRP2 + 0x006CU)
#define PFC_DRV0CTRL6		(PFC_MCU_BASE + PFC_PORT_GRP2 + 0x0080U)
#define PFC_DRV1CTRL6		(PFC_MCU_BASE + PFC_PORT_GRP2 + 0x0084U)
#define PFC_DRV2CTRL6		(PFC_MCU_BASE + PFC_PORT_GRP2 + 0x0088U)
#define PFC_DRV3CTRL6		(PFC_MCU_BASE + PFC_PORT_GRP2 + 0x008CU)
#define PFC_POC6		(PFC_MCU_BASE + PFC_PORT_GRP2 + 0x00A0U)
#define PFC_PUEN6		(PFC_MCU_BASE + PFC_PORT_GRP2 + 0x00C0U)
#define PFC_PUD6		(PFC_MCU_BASE + PFC_PORT_GRP2 + 0x00E0U)
#define PFC_MOD_SEL6		(PFC_MCU_BASE + PFC_PORT_GRP2 + 0x0100U)
#define GPIO_IOINTSEL6		(PFC_MCU_BASE + PFC_PORT_GRP2 + 0x0180U)
#define GPIO_INOUTSEL6		(PFC_MCU_BASE + PFC_PORT_GRP2 + 0x0184U)
#define GPIO_OUTDT6		(PFC_MCU_BASE + PFC_PORT_GRP2 + 0x0188U)
#define GPIO_INDT6		(PFC_MCU_BASE + PFC_PORT_GRP2 + 0x018CU)
#define GPIO_INTDT6		(PFC_MCU_BASE + PFC_PORT_GRP2 + 0x0190U)
#define GPIO_INTCLR6		(PFC_MCU_BASE + PFC_PORT_GRP2 + 0x0194U)
#define GPIO_INTMSK6		(PFC_MCU_BASE + PFC_PORT_GRP2 + 0x0198U)
#define GPIO_MSKCLR6		(PFC_MCU_BASE + PFC_PORT_GRP2 + 0x019CU)
#define GPIO_POSNEG6		(PFC_MCU_BASE + PFC_PORT_GRP2 + 0x01A0U)
/* Port Group7 */
#define PFC_PMMR7		(PFC_MCU_BASE + PFC_PORT_GRP3 + 0x0000U)
#define PFC_GPSR7		(PFC_MCU_BASE + PFC_PORT_GRP3 + 0x0040U)
#define PFC_IP0SR7		(PFC_MCU_BASE + PFC_PORT_GRP3 + 0x0060U)
#define PFC_IP1SR7		(PFC_MCU_BASE + PFC_PORT_GRP3 + 0x0064U)
#define PFC_IP2SR7		(PFC_MCU_BASE + PFC_PORT_GRP3 + 0x0068U)
#define PFC_IP3SR7		(PFC_MCU_BASE + PFC_PORT_GRP3 + 0x006CU)
#define PFC_DRV0CTRL7		(PFC_MCU_BASE + PFC_PORT_GRP3 + 0x0080U)
#define PFC_DRV1CTRL7		(PFC_MCU_BASE + PFC_PORT_GRP3 + 0x0084U)
#define PFC_DRV2CTRL7		(PFC_MCU_BASE + PFC_PORT_GRP3 + 0x0088U)
#define PFC_DRV3CTRL7		(PFC_MCU_BASE + PFC_PORT_GRP3 + 0x008CU)
#define PFC_POC7		(PFC_MCU_BASE + PFC_PORT_GRP3 + 0x00A0U)
#define PFC_PUEN7		(PFC_MCU_BASE + PFC_PORT_GRP3 + 0x00C0U)
#define PFC_PUD7		(PFC_MCU_BASE + PFC_PORT_GRP3 + 0x00E0U)
#define PFC_MOD_SEL7		(PFC_MCU_BASE + PFC_PORT_GRP3 + 0x0100U)
#define GPIO_IOINTSEL7		(PFC_MCU_BASE + PFC_PORT_GRP3 + 0x0180U)
#define GPIO_INOUTSEL7		(PFC_MCU_BASE + PFC_PORT_GRP3 + 0x0184U)
#define GPIO_OUTDT7		(PFC_MCU_BASE + PFC_PORT_GRP3 + 0x0188U)
#define GPIO_INDT7		(PFC_MCU_BASE + PFC_PORT_GRP3 + 0x018CU)
#define GPIO_INTDT7		(PFC_MCU_BASE + PFC_PORT_GRP3 + 0x0190U)
#define GPIO_INTCLR7		(PFC_MCU_BASE + PFC_PORT_GRP3 + 0x0194U)
#define GPIO_INTMSK7		(PFC_MCU_BASE + PFC_PORT_GRP3 + 0x0198U)
#define GPIO_MSKCLR7		(PFC_MCU_BASE + PFC_PORT_GRP3 + 0x019CU)
#define GPIO_POSNEG7		(PFC_MCU_BASE + PFC_PORT_GRP3 + 0x01A0U)
/* System Group0 */
#define PFC_PMMR8		(PFC_BASE + PFC_SYS_GRP + 0x0000U)
#define PFC_GPSR8		(PFC_BASE + PFC_SYS_GRP + 0x0040U)
#define PFC_IP0SR8		(PFC_BASE + PFC_SYS_GRP + 0x0060U)
#define PFC_IP1SR8		(PFC_BASE + PFC_SYS_GRP + 0x0064U)
#define PFC_IP2SR8		(PFC_BASE + PFC_SYS_GRP + 0x0068U)
#define PFC_IP3SR8		(PFC_BASE + PFC_SYS_GRP + 0x006CU)
#define PFC_DRV0CTRL8		(PFC_BASE + PFC_SYS_GRP + 0x0080U)
#define PFC_DRV1CTRL8		(PFC_BASE + PFC_SYS_GRP + 0x0084U)
#define PFC_DRV2CTRL8		(PFC_BASE + PFC_SYS_GRP + 0x0088U)
#define PFC_DRV3CTRL8		(PFC_BASE + PFC_SYS_GRP + 0x008CU)
#define PFC_POC8		(PFC_BASE + PFC_SYS_GRP + 0x00A0U)
#define PFC_PUEN8		(PFC_BASE + PFC_SYS_GRP + 0x00C0U)
#define PFC_PUD8		(PFC_BASE + PFC_SYS_GRP + 0x00E0U)
#define PFC_MOD_SEL8		(PFC_BASE + PFC_SYS_GRP + 0x0100U)
#define GPIO_IOINTSEL8		(PFC_BASE + PFC_SYS_GRP + 0x0180U)
#define GPIO_INOUTSEL8		(PFC_BASE + PFC_SYS_GRP + 0x0184U)
#define GPIO_OUTDT8		(PFC_BASE + PFC_SYS_GRP + 0x0188U)
#define GPIO_INDT8		(PFC_BASE + PFC_SYS_GRP + 0x018CU)
#define GPIO_INTDT8		(PFC_BASE + PFC_SYS_GRP + 0x0190U)
#define GPIO_INTCLR8		(PFC_BASE + PFC_SYS_GRP + 0x0194U)
#define GPIO_INTMSK8		(PFC_BASE + PFC_SYS_GRP + 0x0198U)
#define GPIO_MSKCLR8		(PFC_BASE + PFC_SYS_GRP + 0x019CU)
#define GPIO_POSNEG8		(PFC_BASE + PFC_SYS_GRP + 0x01A0U)
/* System Group1 */
#define PFC_PMMR9		(PFC_MCU_BASE + PFC_SYS_GRP + 0x0000U)
#define PFC_GPSR9		(PFC_MCU_BASE + PFC_SYS_GRP + 0x0040U)
#define PFC_IP0SR9		(PFC_MCU_BASE + PFC_SYS_GRP + 0x0060U)
#define PFC_IP1SR9		(PFC_MCU_BASE + PFC_SYS_GRP + 0x0064U)
#define PFC_IP2SR9		(PFC_MCU_BASE + PFC_SYS_GRP + 0x0068U)
#define PFC_IP3SR9		(PFC_MCU_BASE + PFC_SYS_GRP + 0x006CU)
#define PFC_DRV0CTRL9		(PFC_MCU_BASE + PFC_SYS_GRP + 0x0080U)
#define PFC_DRV1CTRL9		(PFC_MCU_BASE + PFC_SYS_GRP + 0x0084U)
#define PFC_DRV2CTRL9		(PFC_MCU_BASE + PFC_SYS_GRP + 0x0088U)
#define PFC_DRV3CTRL9		(PFC_MCU_BASE + PFC_SYS_GRP + 0x008CU)
#define PFC_POC9		(PFC_MCU_BASE + PFC_SYS_GRP + 0x00A0U)
#define PFC_PUEN9		(PFC_MCU_BASE + PFC_SYS_GRP + 0x00C0U)
#define PFC_PUD9		(PFC_MCU_BASE + PFC_SYS_GRP + 0x00E0U)
#define PFC_MOD_SEL9		(PFC_MCU_BASE + PFC_SYS_GRP + 0x0100U)
#define GPIO_IOINTSEL9		(PFC_MCU_BASE + PFC_SYS_GRP + 0x0180U)
#define GPIO_INOUTSEL9		(PFC_MCU_BASE + PFC_SYS_GRP + 0x0184U)
#define GPIO_OUTDT9		(PFC_MCU_BASE + PFC_SYS_GRP + 0x0188U)
#define GPIO_INDT9		(PFC_MCU_BASE + PFC_SYS_GRP + 0x018CU)
#define GPIO_INTDT9		(PFC_MCU_BASE + PFC_SYS_GRP + 0x0190U)
#define GPIO_INTCLR9		(PFC_MCU_BASE + PFC_SYS_GRP + 0x0194U)
#define GPIO_INTMSK9		(PFC_MCU_BASE + PFC_SYS_GRP + 0x0198U)
#define GPIO_MSKCLR9		(PFC_MCU_BASE + PFC_SYS_GRP + 0x019CU)
#define GPIO_POSNEG9		(PFC_MCU_BASE + PFC_SYS_GRP + 0x01A0U)

//V3M
#define	PFC_IOCTRL30					0xE6060380	// R/W	32	MPOC control register 0
#define	PFC_IOCTRL31					0xE6060384	// R/W	32	MPOC control register 0
#define	PFC_IOCTRL32					0xE6060388	// R/W	32	MPOC control register 0
#define	PFC_IOCTRL40					0xE60603C0	// R/W	32	MPOC control register 0


//RST
#if ACC_PROT_ENABLE == 0
#define	RST_MODEMR0						0xE6160000	// R	32	Mode Monitor Register
#define RST_MODEMR1						0xE6160004	// R	32	Mode Monitor Register2
#else
/* Change to RGID2 when ACC_PROT_ENABLE ==1 */
#define	RST_MODEMR0						0x20E6160000	// R	32	Mode Monitor Register
#define RST_MODEMR1						0x20E6160004	// R	32	Mode Monitor Register2
#endif /* ACC_PROT_ENABLE == 0 */
#define	RST_MODEMR						0xE6160060	// R	32	Mode Monitor Register
#define	RST_CA57RESCNT					0xE6160040	// R/W	32	CA57 Reset Control Register
#define	RST_CA53RESCNT					0xE6160044	// R/W	32	CA53 Reset Control Register
#define	RST_WDTRSTCR					0xE6160054	// R/W	32	Watchdog Timer Reset Control Register
#define	RST_RSTOUTCR					0xE6160058	// R/W	32	PRESETOUT# Control Register
#define	RST_SBAR						0xE6160010	// R/W	32	SYS Boot Address Register
#define	RST_SBAR2						0xE6160014	// R/W	32	SYS Boot Address Register2
#define	RST_CA53BAR						0xE6160030	// R/W	32	CA53 Boot Address Register
#define	RST_CA53BAR2					0xE6160034	// R/W	32	CA53 Boot Address Register2
#define	RST_CA57BAR						0xE6160020	// R/W	32	CA57 Boot Address Register
#define	RST_CA57BAR2					0xE6160024	// R/W	32	CA57 Boot Address Register2
#define	RST_CR7BAR						0xE6160070	// R/W	32	CR7 Boot Address Register
#define	RST_CR7BAR2						0xE6160074	// R/W	32	CR7 Boot Address Register2
#define	RST_CA57CPU0BARH				0xE61600C0	// R/W	32	CA57 CPU0 Boot Address Register for 64-bit mode H
#define	RST_CA57CPU0BARL				0xE61600C4	// R/W	32	CA57 CPU0 Boot Address Register for 64-bit mode L
#define	RST_CA57CPU1BARH				0xE61600D0	// R/W	32	CA57 CPU1 Boot Address Register for 64-bit mode H
#define	RST_CA57CPU1BARL				0xE61600D4	// R/W	32	CA57 CPU1 Boot Address Register for 64-bit mode L
#define	RST_CA57CPU2BARH				0xE61600E0	// R/W	32	CA57 CPU2 Boot Address Register for 64-bit mode H
#define	RST_CA57CPU2BARL				0xE61600E4	// R/W	32	CA57 CPU2 Boot Address Register for 64-bit mode L
#define	RST_CA57CPU3BARH				0xE61600F0	// R/W	32	CA57 CPU3 Boot Address Register for 64-bit mode H
#define	RST_CA57CPU3BARL				0xE61600F4	// R/W	32	CA57 CPU3 Boot Address Register for 64-bit mode L
#define	RST_CA53CPU0BARH				0xE6160080	// R/W	32	CA53 CPU0 Boot Address Register for 64-bit mode H
#define	RST_CA53CPU0BARL				0xE6160084	// R/W	32	CA53 CPU0 Boot Address Register for 64-bit mode L
#define	RST_CA53CPU1BARH				0xE6160090	// R/W	32	CA53 CPU1 Boot Address Register for 64-bit mode H
#define	RST_CA53CPU1BARL				0xE6160094	// R/W	32	CA53 CPU1 Boot Address Register for 64-bit mode L
#define	RST_CA53CPU2BARH				0xE61600A0	// R/W	32	CA53 CPU2 Boot Address Register for 64-bit mode H
#define	RST_CA53CPU2BARL				0xE61600A4	// R/W	32	CA53 CPU2 Boot Address Register for 64-bit mode L
#define	RST_CA53CPU3BARH				0xE61600B0	// R/W	32	CA53 CPU3 Boot Address Register for 64-bit mode H
#define	RST_CA53CPU3BARL				0xE61600B4	// R/W	32	CA53 CPU3 Boot Address Register for 64-bit mode L
#define	RST_APBSFTYCHKR					0xE616005C	// R/W	32	APB bus Safety Check Register
#define	RST_STBCHR0						0xE6160100	// R/W	32	Standby Flag Register 0
#define	RST_STBCHR1						0xE6160104	// R/W	32	Standby Flag Register 1
#define	RST_STBCHR2						0xE6160108	// R/W	32	Standby Flag Register 2
#define	RST_STBCHR3						0xE616010C	// R/W	32	Standby Flag Register 3
#define	RST_STBCHR4						0xE6160120	// R/W	32	Standby Flag Register 4
#define	RST_STBCHR5						0xE6160124	// R/W	32	Standby Flag Register 5
#define	RST_STBCHR6						0xE6160128	// R/W	32	Standby Flag Register 6
#define	RST_STBCHR7						0xE616012C	// R/W	32	Standby Flag Register 7
#define	RST_SRESCR						0xE6160110	// R/W	32	Soft Power On Reset Control Register
#define	RST_RRSTFR						0xE6160114	// R/W	32	RT Reset Flag Register
#define	RST_SRSTFR						0xE6160118	// R/W	32	SYS Reset Flag Register
#define	RST_SCPTCSR						0xE6160180	// R/W	32	Secure Protect Control/Status Register
#define	RST_SCERMIDR					0xE6160184	// R	32	Secure Error Master ID Register
#define	RST_SCERADR						0xE6160188	// R	32	Secure Error Address Register
#define	RST_SAPTCSR						0xE6160190	// R/W	32	Safety Protect Control/Status Register
#define	RST_SAERMIDR					0xE6160194	// R	32	Safety Error Master ID Register
#define	RST_SAERADR						0xE6160198	// R	32	Safety Error Address Register

#define MODEMR_BOOT_CPU_MASK		(0x000000C0U)
#define MODEMR_BOOT_CPU_CR7		(0x000000C0U)
#define MODEMR_BOOT_CPU_CA57		(0x00000000U)
#define MODEMR_BOOT_CPU_CA53		(0x00000040U)
#define MODEMR_BOOT_DEV_MASK		(0x0000001EU)
#define MODEMR_BOOT_DEV_HYPERFLASH160	(0x00000004U)
#define MODEMR_BOOT_DEV_HYPERFLASH80	(0x00000006U)
#define MODEMR_BOOT_DEV_QSPI_FLASH40	(0x00000008U)
#define MODEMR_BOOT_DEV_QSPI_FLASH80	(0x0000000CU)
#define MODEMR_BOOT_DEV_OCTAL_FLASH	(0x0000000EU)
#define MODEMR_BOOT_DEV_EMMC_25X1	(0x0000000AU)
#define MODEMR_BOOT_DEV_EMMC_50X8	(0x0000001AU)
#define MODEMR_BOOT_DEV_SCIF_DOWNLOAD	(0x0000001EU)
#define MODEMR_BOOT_DEV_USB_DOWNLOAD	(0x0000001CU)
#define MODEMR_BOOT_PLL_MASK		(0x00006000U)
#define MODEMR_BOOT_PLL_SHIFT		(13U)


#define	MD14_MD13_TYPE_0	U(0x0000)	/* MD14=0 MD13=0 */
#define	MD14_MD13_TYPE_1	U(0x2000)	/* MD14=0 MD13=1 */
#define	MD14_MD13_TYPE_2	U(0x4000)	/* MD14=1 MD13=0 */
#define	MD14_MD13_TYPE_3	U(0x6000)	/* MD14=1 MD13=1 */

#define MODEMR0_MD31_V3U			(0x80000000U)
#define MODEMR1_MD32_V3U			(0x00000001U)
#define MODEMR_SCIF_115200_V3U		(0x00000000U)
#define MODEMR_SCIF_921600_V3U		(0x80000000U)
#define MODEMR_SCIF_1843200_V3U		(0x00000001U)
#define MODEMR_SCIF_3000000_V3U		(0x80000001U)

#define MODEMR0_MD31_GEN4			(0x80000000U)
#define MODEMR1_MD32_GEN4			(0x00000001U)
#define MODEMR_SCIF_115200_GEN4		(0x00000000U)
#define MODEMR_SCIF_921600_GEN4		(0x80000000U)
#define MODEMR_SCIF_1843200_GEN4	(0x00000001U)
#define MODEMR_SCIF_3000000_GEN4	(0x80000001U)


//
#define MFIS_SOFTMDR			(0xE6260600U)


//SCIF0
#define	SCIF0_SCSMR						0xE6E60000	// R/W	16	Serial mode register
#define	SCIF0_SCBRR						0xE6E60004	// R/W	8	Bit rate register
#define	SCIF0_SCSCR						0xE6E60008	// R/W	16	Serial control register
#if ACC_PROT_ENABLE == 0
#define	SCIF0_SCFTDR					0xE6E6000C	// W	8	Transmit FIFO data register
#define	SCIF0_SCFSR						0xE6E60010	// R/W	16	Serial status register
#else
/* Change to RGID2 when ACC_PROT_ENABLE ==1 */
#define	SCIF0_SCFTDR					0x20E6E6000C	// W	8	Transmit FIFO data register
#define	SCIF0_SCFSR						0x20E6E60010	// R/W	16	Serial status register
#endif /* ACC_PROT_ENABLE == 0 */
#define	SCIF0_SCFRDR					0xE6E60014	// R	8	Receive FIFO data register
#define	SCIF0_SCFCR						0xE6E60018	// R/W	16	FIFO control register
#define	SCIF0_SCFDR						0xE6E6001C	// R	16	FIFO data count register
#define	SCIF0_SCSPTR					0xE6E60020	// R/W	16	Serial port register
#define	SCIF0_SCLSR						0xE6E60024	// R/W	16	Line status register
#define	SCIF0_DL						0xE6E60030	// R/W	16	Frequency division register
#define	SCIF0_CKS						0xE6E60034	// R/W	16	Clock Select register


//SCIF2
#define	SCIF2_SCSMR						0xE6E88000	// R/W	16	Serial mode register
#define	SCIF2_SCBRR						0xE6E88004	// R/W	8	Bit rate register
#define	SCIF2_SCSCR						0xE6E88008	// R/W	16	Serial control register
#define	SCIF2_SCFTDR					0xE6E8800C	// W	8	Transmit FIFO data register
#define	SCIF2_SCFSR						0xE6E88010	// R/W	16	Serial status register
#define	SCIF2_SCFRDR					0xE6E88014	// R	8	Receive FIFO data register
#define	SCIF2_SCFCR						0xE6E88018	// R/W	16	FIFO control register
#define	SCIF2_SCFDR						0xE6E8801C	// R	16	FIFO data count register
#define	SCIF2_SCSPTR					0xE6E88020	// R/W	16	Serial port register
#define	SCIF2_SCLSR						0xE6E88024	// R/W	16	Line status register
#define	SCIF2_DL						0xE6E88030	// R/W	16	Frequency division register
#define	SCIF2_CKS						0xE6E88034	// R/W	16	Clock Select register

//SCIF3
#if ACC_PROT_ENABLE == 0
#define SCIF3_BASE						(0xE6C50000)
#else
/* Change to RGID2 when ACC_PROT_ENABLE ==1 */
#define SCIF3_BASE						(0x20E6C50000)
#endif /* ACC_PROT_ENABLE == 0 */
#define	SCIF3_SCSMR						(SCIF3_BASE + 0x0000U)	// R/W	16	Serial mode register
#define	SCIF3_SCBRR						(SCIF3_BASE + 0x0004U)	// R/W	8	Bit rate register
#define	SCIF3_SCSCR						(SCIF3_BASE + 0x0008U)	// R/W	16	Serial control register
#define	SCIF3_SCFTDR					(SCIF3_BASE + 0x000CU)	// W	8	Transmit FIFO data register
#define	SCIF3_SCFSR						(SCIF3_BASE + 0x0010U)	// R/W	16	Serial status register
#define	SCIF3_SCFRDR					(SCIF3_BASE + 0x0014U)	// R	8	Receive FIFO data register
#define	SCIF3_SCFCR						(SCIF3_BASE + 0x0018U)	// R/W	16	FIFO control register
#define	SCIF3_SCFDR						(SCIF3_BASE + 0x001CU)	// R	16	FIFO data count register
#define	SCIF3_SCSPTR					(SCIF3_BASE + 0x0020U)	// R/W	16	Serial port register
#define	SCIF3_SCLSR						(SCIF3_BASE + 0x0024U)	// R/W	16	Line status register
#define	SCIF3_DL						(SCIF3_BASE + 0x0030U)	// R/W	16	Frequency division register 
#define	SCIF3_CKS						(SCIF3_BASE + 0x0034U)	// R/W	16	Clock Select register 

/* HSCIF0 */
#define	HSCIF0_HSSMR					(0xE6540000U)	// R/W	16	Serial mode register
#define	HSCIF0_HSBRR					(0xE6540004U)	// R/W	8	Bit rate register
#define	HSCIF0_HSSCR					(0xE6540008U)	// R/W	16	Serial control register
#if ACC_PROT_ENABLE == 0
#define	HSCIF0_HSFTDR					(0xE654000CU)	// W	8	Transmit FIFO data register
#define	HSCIF0_HSFSR					(0xE6540010U)	// R/W	16	Serial status register
#else
/* Change to RGID2 when ACC_PROT_ENABLE ==1 */
#define	HSCIF0_HSFTDR					(0x20E654000CU)	// W	8	Transmit FIFO data register
#define	HSCIF0_HSFSR					(0x20E6540010U)	// R/W	16	Serial status register
#endif /* ACC_PROT_ENABLE == 0 */
#define	HSCIF0_HSFRDR					(0xE6540014U)	// R	8	Receive FIFO data register
#define	HSCIF0_HSFCR					(0xE6540018U)	// R/W	16	FIFO control register
#define	HSCIF0_HSFDR					(0xE654001CU)	// R	16	FIFO data count register
#define	HSCIF0_HSSPTR					(0xE6540020U)	// R/W	16	Serial port register
#define	HSCIF0_HSLSR					(0xE6540024U)	// R/W	16	Line status register
#define HSCIF0_HSSRR					(0xE6540040U)	// R/W	16	Sampling rate register
/* BRG */
#define	HSCIF0_DL					(0xE6540030U)	// R/W	16	Frequency division register
#define	HSCIF0_CKS					(0xE6540034U)	// R/W	16	Clock select register


/* Appendix A.	*/
#if ACC_PROT_ENABLE == 0
#define	PRR			(0xFFF00044)	/* Product Register */
#else
/* Change to RGID2 when ACC_PROT_ENABLE ==1 */
#define	PRR			(0x20FFF00044)	/* Product Register */
#endif /* ACC_PROT_ENABLE == 0 */
#define PRR_PRODUCT_MASK	(0x00007F00U)
#define PRR_CUT_MASK		(0x000000FFU)
#define PRR_PRODUCT_H3		(0x00004F00U)	/* R-Car H3  */
#define PRR_PRODUCT_M3		(0x00005200U)	/* R-Car M3  */
#define PRR_PRODUCT_M3N		(0x00005500U)	/* R-Car M3N */
#define PRR_PRODUCT_E3		(0x00005700U)	/* R-Car E3  */
#define PRR_PRODUCT_D3		(0x00005800U)	/* R-Car D3  */
#define PRR_PRODUCT_V3M		(0x00005400U)	/* R-Car V3M */
#define PRR_PRODUCT_V3H		(0x00005600U)	/* R-Car V3H */
#define PRR_PRODUCT_V3U		(0x00005900U)	/* R-Car V3U */
#define PRR_PRODUCT_S4		(0x00005A00U)	/* R-Car S4  */
#define PRR_PRODUCT_V4H		(0x00005C00U)	/* R-Car V4H */
#define PRR_PRODUCT_V4M		(0x00005D00U)	/* R-Car V4M */
#define PRR_CUT_10		(0x00U)
#define PRR_CUT_11		(0x01U)
#define PRR_CUT_20		(0x10U)
#define PRR_CUT_30		(0x20U)
#define PRR_CUT_MAJOR_MASK	(0x000000F0U)
#define PRR_CUT_MINOR_MASK	(0x0000000FU)
#define PRR_PRODUCT_SHIFT	(8U)
#define PRR_MAJOR_SHIFT		(4U)
#define PRR_MINOR_SHIFT		(0U)
#define PRR_MAJOR_OFFSET	(1U)

#endif /* REG_RCARGEN3_H */
