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 * DISCLAIMER
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 * software is owned by Renesas Electronics Corporation and is protected under
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 *******************************************************************************/

/*******************************************************************************
 * DESCRIPTION   : Interrupt controler ID header
 ******************************************************************************/

#ifndef INTC_ID_H_
#define INTC_ID_H_

#define	ECC_ERR_LRAM				(0U)		/* ECC Error Detection for Local RAM */
#define	ECC_ERR_CACHE				(1U)		/* ECC Error Detection for Cache RAM */
#define	EDC_ERR_INT_AXI				(2U)		/* EDC Error interrupt of AXI */
#define	ECC_ERR_INT_AXIAB			(3U)		/* ECC Error interrupt of AXIAB */
#define	ECC_ERR_INT_PKCC			(4U)		/* ECC Error interrupt of PKCC */
#define	CORTEX_INT_REQ_SINGLE_CORE		(5U)		/* Cortex-R/A interrupt request (single main core) */
#define	CORTEX_INT_REQ_SEL_SINGLE_CORE		(6U)		/* Cortex-R/A interrupt request (selected single main core) */
#define	COMPLETION_AES				(7U)		/* Completion of AES encryption or decryption */
								/* ID 8 Reserved */
#define	COMPLETION_RAND_NUMBER			(9U)		/* Random number generation complete */
#define	OSTIMER0_OVERFLOW			(10U)		/* OS Timer 0 overflow */
#define	OSTIMER1_OVERFLOW			(11U)		/* OS Timer 1 overflow */
#define	WDT0_INT				(12U)		/* Watchdog Timer 0 interrupt (at 75%) */
#define	COMPLETION_PKCC				(13U)		/* Completion of PKCC operation */
#define	COMPLETION_DMAC_CH5CH6			(14U)		/* Interrupt request by transfer completion for channel-5/6 */
#define	INT_REQ_BRESP_RRESP_ERR_AXI		(15U)		/* Interrupt request by BRESP/RRESP-error for AXI */
								/* ID 16 Reserved */
#define	REQ_SHAA0				(17U)		/* Input data request for SHAA0 */
#define	COMPLETION_SHAA0			(18U)		/* Completion or suspension of SHAA0 data output */
#define	REQ_CHALLENGE_DATA_FOR_ARM_DEBUG	(19U)		/* Challenge data request for ARM Debugger */
#define	REQ_RES_COMP_FOR_ARM_DEBUG		(20U)		/* Response data compare request for ARM Debugger */
#define	REQ_CHALLENGE_DATA_FOR_RH850_DEBUG	(21U)		/* Challenge data request for RH850 Debugger */
#define	REQ_RES_COMP_FOR_RH850_DEBUG		(22U)		/* Response data compare request for RH850 Debugger */
#define	REQ_CHALLENGE_DATA_FOR_RH850_DEBUG_R	(23U)		/* Challenge data request for RH850 Debugger r */
								/* Reserved */
#define	ACC_ERR_MASKROM_RTSRAM			(25U)		/* Data access error detection of Mask ROM or RTSRAM area */
#define	ACC_ERR_EXCEPT_MASKROM_RTSRAM		(26U)		/* Data access error detection except Mask ROM and RT-SRAM area */
								/* ID 27 Reserved */
								/* ID 28 Reserved */
#define	RTSRAM_SAFETY_ERR			(29U)		/* RT-SRAM Error Safety Error Detection */
#define	RTSRAM_SECURE_ERR			(30U)		/* RT-SRAM Error Secure Error Detection */
#define	RTSRAM_EDC_ERR				(31U)		/* RT-SRAM Error EDC Error Detection */
#define	RTSRAM_DUPLEX_ERR			(32U)		/* RT-SRAM Error Duplex circuit Error Detection */
#define	RTSRAM_SYSRAM_2BIT_ERR			(33U)		/* RT-SRAM Error SYSRAM 2bit Error Detection */
#define	RTSRAM_SYSRAM_1BIT_ERR			(34U)		/* RT-SRAM Error SYSRAM 1bit Error Detection */
#define	SECROM_SYSRAM_2BIT_ERR			(35U)		/* Sec ROM Error SYSRAM 2bit Error Detection */
#define	SECROM_SYSRAM_1BIT_ERR			(36U)		/* Sec ROM Error SYSRAM 1bit Error Detection */
#define	COMPLETION_SECURE_BOOT_ENGINE_CALC	(37U)		/* Completion of secure boot engine calculation */
								/* ID 38 -- 63 Reserved */

#endif /* INTC_ID_H_ */
