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#ifndef BOOT_INIT_DRAM_REGDEF_H_
#define BOOT_INIT_DRAM_REGDEF_H_

#if defined(__RH850G3K__)
#include "remap_register.h"
#endif

#define RCAR_DDR_VERSION             "rev.1.00"
#define DRAM_CH_CNT                  0x02U
#define SLICE_CNT                    0x02U
#define CS_CNT                       0x02U

/* for pll setting */
#define CLK_DIV(a, diva, b, divb)    (((a) * (divb)) / ((b) * (diva)))

/* for ddr density setting */
#define DBMEMCONF_REG(d3, row, BG, bank, col, dw)    (((d3) << 30U) | ((row) << 24U) | ((BG) << 20U) | ((bank) << 16U) | ((col) << 8U) | (dw))
#define DBMEMCONF_REGD(density)      (DBMEMCONF_REG((density % 2U), (((density + 1U) / 2U) + (28U - 2U - 2U - 10U - 1U)), 2U, 2U, 10U, 1U))    /* 16bit */

/* system registers : CPG */
#define CPG_FRQCRD_KICK_BIT          (1U << 31)
#define CPG_PLL3CR0_KICK_BIT         (1U << 31)
#define CPG_PLLECR_PLL3ST_BIT        (1U << 11)

#if defined(__RH850G3K__)
#define CPG_BASE                     (BASE_CPG_ADDR)
#else
#define CPG_BASE                     (0xE6150000U)
#endif
#define CPG_CPGWPR                   (CPG_BASE + 0x0000U)
#define CPG_FRQCRD0                  (CPG_BASE + 0x080CU)
#define CPG_PLLECR                   (CPG_BASE + 0x0820U)
#define CPG_PLL3CR0                  (CPG_BASE + 0x083CU)
#define CPG_PLL3CR1                  (CPG_BASE + 0x08C0U)
#define CPG_FSRCHKCLRR4              (CPG_BASE + 0x0590U)
#define CPG_FSRCHKSETR4              (CPG_BASE + 0x0510U)
#define CPG_FSRCHKRA4                (CPG_BASE + 0x0410U)
#define CPG_SRCR4                    (CPG_BASE + 0x2C10U)
#define CPG_SRSTCLR4                 (CPG_BASE + 0x2C90U)

#if defined(__RH850G3K__)
#define RST_BASE                     (BASE_RESET_ADDR)
#else
#define RST_BASE                     (0xE6160000U)
#endif
#define RST_MODEMR0                  (RST_BASE + 0x0000U)
#define RST_MODEMR1                  (RST_BASE + 0x0004U)

#if defined(__RH850G3K__)
#define OTP_MEM_1_BASE               (BASE_OTP_MEM_ADDR)
#else
#define OTP_MEM_1_BASE               (0xE61BF000U)
#endif
#define OTP_MEM_OTPMONITOR17         (OTP_MEM_1_BASE + 0x0144U)
#define OTP_MEM_PRODUCT_MASK         (0x000000FFU)

/* Product Register */
#define PRR                          (0xFFF00044U)
#define PRR_PRODUCT_MASK             (0x00007F00U)
#define PRR_CUT_MASK                 (0x000000FFU)

#define PRR_PRODUCT_V4M              (0x00005D00U)    /* R-Car V4M */

#define PRR_PRODUCT_10               (0x00000000U)    /* ver 1.0 */
#define PRR_PRODUCT_20               (0x00000010U)    /* ver 2.0 */

/* DBSC registers */
#if defined(__RH850G3K__)
#define DBSC_D_BASE                  (BASE_DBSC_ADDR + 0x14000U)    /* forV4M DBSC0 clk_dbsc region */
#define DBSC_A_BASE                  (BASE_DBSC_ADDR)               /* forV4M DBSC0 clk_axim region */
#else
#define DBSC_D_BASE                  (0xE67A4000U)    /* forV4M DBSC0 clk_dbsc region */
#define DBSC_A_BASE                  (0xE6790000U)    /* forV4M DBSC0 clk_axim region */
#endif

#define DBSC_DBSYSCONF0              (DBSC_A_BASE    +    0x0000U)
#define DBSC_DBSYSCONF1              (DBSC_D_BASE    +    0x0000U)
#define DBSC_DBSYSCONF1A             (DBSC_A_BASE    +    0x0004U)
#define DBSC_DBSYSCONF2              (DBSC_D_BASE    +    0x0004U)
#define DBSC_DBPHYCONF0              (DBSC_D_BASE    +    0x0008U)
#define DBSC_DBSYSCONF2A             (DBSC_A_BASE    +    0x0008U)
#define DBSC_DBMEMKIND               (DBSC_D_BASE    +    0x0020U)
#define DBSC_DBMEMKINDA              (DBSC_A_BASE    +    0x0020U)

#define DBSC_DBMEMCONF(ch,cs)        (DBSC_D_BASE    +    0x0030U + (0x2000U * (ch & 0x02U)) + (0x10U * (ch & 0x01U)) + (0x04U * (cs)))

#define DBSC_DBMEMCONFA(ch,cs)       (DBSC_A_BASE    +    0x0030U + (0x4000U * (ch & 0x02U)) + (0x10U * (ch & 0x01U)) + (0x04U * (cs)))

#define DBSC_DBSYSCNT0               (DBSC_D_BASE    +    0x0100U)
#define DBSC_DBSYSCNT0A              (DBSC_A_BASE    +    0x0100U)

#define DBSC_DBACEN                  (DBSC_A_BASE    +    0x0200U)
#define DBSC_DBRFEN                  (DBSC_D_BASE    +    0x0204U)
#define DBSC_DBCMD                   (DBSC_D_BASE    +    0x0208U)
#define DBSC_DBWAIT                  (DBSC_D_BASE    +    0x0210U)

#define DBSC_DBTR(x)                 (DBSC_D_BASE    +    0x0300U + (0x04U * (x)))

#define DBSC_DBBL                    (DBSC_D_BASE    +    0x0400U)
#define DBSC_DBBLA                   (DBSC_A_BASE    +    0x0400U)

#define DBSC_DBRFCNF1                (DBSC_D_BASE    +    0x0414U)
#define DBSC_DBRFCNF2                (DBSC_D_BASE    +    0x0418U)

#define DBSC_DBCALCNF                (DBSC_D_BASE    +    0x0424U)

#define DBSC_DBRNK(x)                (DBSC_D_BASE    +    0x0430U + (0x04U * (x)))

#define DBSC_DBDBICNT                (DBSC_D_BASE    +    0x0518U)
#define DBSC_DBDFIPMSTRCNF           (DBSC_D_BASE    +    0x0520U)
#define DBSC_DBDFICUPDCNF            (DBSC_D_BASE    +    0x0540U)

#define DBSC_DBDFISTAT(ch)           (DBSC_D_BASE    +    0x0600U + (0x2000U * (ch & 0x02U)) + (0x40U * (ch & 0x01U)))

#define DBSC_DBDFICNT(ch)            (DBSC_D_BASE    +    0x0604U + (0x2000U * (ch & 0x02U)) + (0x40U * (ch & 0x01U)))

#define DBSC_DBPDCNT2(ch)            (DBSC_D_BASE    +    0x0618U + (0x2000U * (ch & 0x02U)) + (0x40U * (ch & 0x01U)))

#define DBSC_DBPDLK(ch)              (DBSC_D_BASE    +    0x0620U + (0x2000U * (ch & 0x02U)) + (0x40U * (ch & 0x01U)))

#define DBSC_DBPDRGA(ch)             (DBSC_D_BASE    +    0x0624U + (0x2000U * (ch & 0x02U)) + (0x40U * (ch & 0x01U)))

#define DBSC_DBPDRGD(ch)             (DBSC_D_BASE    +    0x0628U + (0x2000U * (ch & 0x02U)) + (0x40U * (ch & 0x01U)))

#define DBSC_DBPDRGM(ch)             (DBSC_D_BASE    +    0x062CU + (0x2000U * (ch & 0x02U)) + (0x40U * (ch & 0x01U)))

#define DBSC_DBPDSTAT0(ch)           (DBSC_D_BASE    +    0x0630U + (0x2000U * (ch & 0x02U)) + (0x40U * (ch & 0x01U)))

#define DBSC_DBPDSTAT1(ch)           (DBSC_D_BASE    +    0x0634U + (0x2000U * (ch & 0x02U)) + (0x40U * (ch & 0x01U)))

#define DBSC_DBBUS0CNF1              (DBSC_A_BASE    +    0x0804U)

#define DBSC_DBBCAMDIS               (DBSC_A_BASE    +    0x09FCU)

#define DBSC_DBSCHRW1                (DBSC_A_BASE    +    0x1024U)

#define DBSC_DBSCHTR0                (DBSC_A_BASE    +    0x1030U)

#define DBSC_DBSCHFCTST0             (DBSC_A_BASE    +    0x1040U)
#define DBSC_DBSCHFCTST1             (DBSC_A_BASE    +    0x1044U)

#endif /* BOOT_INIT_DRAM_REGDEF_H_ */
