/*******************************************************************************
 * Copyright (c) 2018-2021 Renesas Electronics Corporation. All rights reserved.
 *
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 *
 * This software is provided as reference/sample code under the license
 * agreement between Renesas Electronics Corporation and licensee (the
 * "License Agreement") and shall be treated as specified in the License
 * Agreement.
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 * information of Renesas Electronics Corporation. They must be used and
 * modified solely for the purpose for which it was furnished by Renesas
 * Electronics Corporation. All or part of these instructions, statements and
 * software must not be reproduced nor disclosed to any third party in any
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 * THIS SOFTWARE IS PROVIDED BY RENESAS ELEOCTRONICS CORPORATION "AS IS" AND
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 ******************************************************************************/

/*******************************************************************************
 * DESCRIPTION   : Memory Access Protection header
 ******************************************************************************/
#ifndef ACC_PROT_MEMORY_H_
#define ACC_PROT_MEMORY_H_

#include <stdint.h>
#include <remap_register.h>

#define SECDIVnD_BASE       (0xFFE90000U)
#define SECDIVnD(base, a)   ((uint32_t)(base) + (0x0004U * (uint32_t)(a)))
#define SECCTRnD(base, a)   ((uint32_t)(base) + (0x0004U * (uint32_t)(a)) + 0x0040U)

#define SPTDIVCRn_BASE      (BASE_AXI_ADDR + 0x0500U)/* 0xE6784500U */
#define SPTDIVCR(a)         ((SPTDIVCRn_BASE) + (0x0004U * (uint32_t)(a)))
#define SPTCR(a)            ((SPTDIVCRn_BASE) + (0x0004U * (uint32_t)(a)) + 0x40U)

#define DPTDIVCRn_BASE      (BASE_AXI_ADDR + 0x0400U)/* 0xE6784400U */
#define DPTDIVCR(a)         ((DPTDIVCRn_BASE) + (0x0004U * (uint32_t)(a)))
#define DPTCR(a)            ((DPTDIVCRn_BASE) + (0x0004U * (uint32_t)(a)) + 0x40U)

#define PROT_GRP0_R_    (uint8_t)(1U << 7U)
#define PROT_GRP0__W    (uint8_t)(1U << 3U)
#define PROT_GRP0_RW    (PROT_GRP0_R | PROT_GRP0_W)
#define PROT_GRP1_R_    (uint8_t)(1U << 6U)
#define PROT_GRP1__W    (uint8_t)(1U << 2U)
#define PROT_GRP1_RW    (PROT_GRP1_R | PROT_GRP1_W)
#define PROT_GRP2_R_    (uint8_t)(1U << 5U)
#define PROT_GRP2__W    (uint8_t)(1U << 1U)
#define PROT_GRP2_RW    (PROT_GRP2_R | PROT_GRP2_W)
#define PROT_GRP3_R_    (uint8_t)(1U << 4U)
#define PROT_GRP3__W    (uint8_t)(1U << 0U)
#define PROT_GRP3_RW    (PROT_GRP3_R | PROT_GRP3_W)

#define PROT_GRP_ALL    (PROT_GRP0__W | PROT_GRP1__W | PROT_GRP2__W | PROT_GRP3__W)
/*    3210  */
#define R_NNNN      (PROT_GRP3_R_ | PROT_GRP2_R_ | PROT_GRP1_R_ | PROT_GRP0_R_)
#define R_NNNY      (PROT_GRP3_R_ | PROT_GRP2_R_ | PROT_GRP1_R_               )
#define R_NNYN      (PROT_GRP3_R_ | PROT_GRP2_R_                | PROT_GRP0_R_)
#define R_NNYY      (PROT_GRP3_R_ | PROT_GRP2_R_                              )
#define R_NYNN      (PROT_GRP3_R_ |                PROT_GRP1_R_ | PROT_GRP0_R_)
#define R_NYNY      (PROT_GRP3_R_ |                PROT_GRP1_R_               )
#define R_NYYN      (PROT_GRP3_R_ |                               PROT_GRP0_R_)
#define R_NYYY      (PROT_GRP3_R_                                             )
#define R_YNNN      (               PROT_GRP2_R_ | PROT_GRP1_R_ | PROT_GRP0_R_)
#define R_YNNY      (               PROT_GRP2_R_ | PROT_GRP1_R_ |             )
#define R_YNYN      (               PROT_GRP2_R_                | PROT_GRP0_R_)
#define R_YNYY      (               PROT_GRP2_R_                              )
#define R_YYNN      (                              PROT_GRP1_R_ | PROT_GRP0_R_)
#define R_YYNY      (                              PROT_GRP1_R_               )
#define R_YYYN      (                                             PROT_GRP0_R_)
#define R_YYYY      ( 0U                                                      )
/*    3210  */
#define W_NNNN      (PROT_GRP3__W | PROT_GRP2__W | PROT_GRP1__W | PROT_GRP0__W)
#define W_NNNY      (PROT_GRP3__W | PROT_GRP2__W | PROT_GRP1__W               )
#define W_NNYN      (PROT_GRP3__W | PROT_GRP2__W                | PROT_GRP0__W)
#define W_NNYY      (PROT_GRP3__W | PROT_GRP2__W                              )
#define W_NYNN      (PROT_GRP3__W |                PROT_GRP1__W | PROT_GRP0__W)
#define W_NYNY      (PROT_GRP3__W |                PROT_GRP1__W               )
#define W_NYYN      (PROT_GRP3__W |                               PROT_GRP0__W)
#define W_NYYY      (PROT_GRP3__W                                             )
#define W_YNNN      (               PROT_GRP2__W | PROT_GRP1__W | PROT_GRP0__W)
#define W_YNNY      (               PROT_GRP2__W | PROT_GRP1__W |             )
#define W_YNYN      (               PROT_GRP2__W                | PROT_GRP0__W)
#define W_YNYY      (               PROT_GRP2__W                              )
#define W_YYNN      (                              PROT_GRP1__W | PROT_GRP0__W)
#define W_YYNY      (                              PROT_GRP1__W               )
#define W_YYYN      (                                             PROT_GRP0__W)
#define W_YYYY      ( 0U                                                      )

#define RT_SRAM_ADDR_END    (0x000FF000U)
#define SYSTEM_RAM_ADDR_END (0xFFFFF000U)
#define DRAM_ADDR_END       (0x0000002FFFFF0000ULL)


typedef struct {
    uint8_t reg_sec;
    uint8_t reg_saf;
    uint8_t acc_sec;
    uint8_t acc_saf;
}RAM_GROUP;

typedef struct {
    uint32_t addr_off;      /* RT_SRAM_PROT[0] is must be 0x00000000 */
    RAM_GROUP prot;
}RT_SRAM_PROT;

typedef struct {
    uint32_t addr;          /* SYSTEM_RAM_PROT[0] is must be 0xE6300000 */
    RAM_GROUP prot;
}SYSTEM_RAM_PROT;


typedef struct {
    uint64_t addr;          /* DRAM_PROT[0] is must be 0x00000040_00000000 */
    RAM_GROUP prot;
}DRAM_PROT;

void acc_prot_rt_sram(void);
void acc_prot_system_ram(void);
void acc_prot_dram(void);

#endif /* ACC_PROT_LIFEC_H__ */
