/*******************************************************************************
 * Copyright (c) 2021-2022 Renesas Electronics Corporation. All rights reserved.
 *
 *     RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY
 *
 * This software is provided as reference/sample code under the license
 * agreement between Renesas Electronics Corporation and licensee (the
 * "License Agreement") and shall be treated as specified in the License
 * Agreement.
 * These instructions, statements, and software are the confidential
 * information of Renesas Electronics Corporation. They must be used and
 * modified solely for the purpose for which it was furnished by Renesas
 * Electronics Corporation. All or part of these instructions, statements and
 * software must not be reproduced nor disclosed to any third party in any
 * form, unless permitted by the License Agreement.
 *
 * THIS SOFTWARE IS PROVIDED BY RENESAS ELEOCTRONICS CORPORATION "AS IS" AND
 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
 * SATISFACTORY QUALITY, ACCURACY, TITLE AND NON-INFRINGEMENT ARE DISCLAIMED.
 * IN NO EVENT SHALL RENESAS ELECTRONICS CORPORATION BE LIABLE FOR ANY DIRECT,
 * INDIRECT, INCIDENTAL, SPECIAL, PUNITIVE, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
 * DAMAGE.
 ******************************************************************************/

#define _reg_PHY_CLK_WR_BYPASS_SLAVE_DELAY                 0x000b1000U
#define _reg_PHY_IO_PAD_DELAY_TIMING_BYPASS                0x10041000U
#define _reg_PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS              0x000a1001U
#define _reg_PHY_WRITE_PATH_LAT_ADD_BYPASS                 0x10031001U
#define _reg_PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY             0x000a1002U
#define _reg_PHY_BYPASS_TWO_CYC_PREAMBLE                   0x10021002U
#define _reg_PHY_CLK_BYPASS_OVERRIDE                       0x18011002U
#define _reg_PHY_SW_WRDQ0_SHIFT                            0x00061003U
#define _reg_PHY_SW_WRDQ1_SHIFT                            0x08061003U
#define _reg_PHY_SW_WRDQ2_SHIFT                            0x10061003U
#define _reg_PHY_SW_WRDQ3_SHIFT                            0x18061003U
#define _reg_PHY_SW_WRDQ4_SHIFT                            0x00061004U
#define _reg_PHY_SW_WRDQ5_SHIFT                            0x08061004U
#define _reg_PHY_SW_WRDQ6_SHIFT                            0x10061004U
#define _reg_PHY_SW_WRDQ7_SHIFT                            0x18061004U
#define _reg_PHY_SW_WRDM_SHIFT                             0x00061005U
#define _reg_PHY_SW_WRDQS_SHIFT                            0x08041005U
#define _reg_PHY_PER_RANK_CS_MAP                           0x10021005U
#define _reg_PHY_PER_CS_TRAINING_MULTICAST_EN              0x18011005U
#define _reg_PHY_PER_CS_TRAINING_INDEX                     0x00011006U
#define _reg_PHY_LP4_BOOT_RDDATA_EN_IE_DLY                 0x08021006U
#define _reg_PHY_LP4_BOOT_RDDATA_EN_DLY                    0x10051006U
#define _reg_PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY               0x18051006U
#define _reg_PHY_LP4_BOOT_RPTR_UPDATE                      0x00041007U
#define _reg_PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST             0x08041007U
#define _reg_PHY_LP4_BOOT_WRPATH_GATE_DISABLE              0x10021007U
#define _reg_PHY_LP4_BOOT_RDDATA_EN_OE_DLY                 0x18051007U
#define _reg_PHY_CTRL_LPBK_EN                              0x00021008U
#define _reg_PHY_LPBK_CONTROL                              0x08091008U
#define _reg_PHY_LPBK_DFX_TIMEOUT_EN                       0x18011008U
#define _reg_PHY_AUTO_TIMING_MARGIN_CONTROL                0x00201009U
#define _reg_PHY_AUTO_TIMING_MARGIN_OBS                    0x001c100aU
#define _reg_PHY_PRBS_PATTERN_START                        0x0007100bU
#define _reg_PHY_PRBS_PATTERN_MASK                         0x0809100bU
#define _reg_PHY_RDLVL_MULTI_PATT_ENABLE                   0x1801100bU
#define _reg_PHY_RDLVL_MULTI_PATT_RST_DISABLE              0x0001100cU
#define _reg_PHY_VREF_INITIAL_STEPSIZE                     0x0806100cU
#define _reg_PHY_VREF_TRAIN_OBS                            0x1007100cU
#define _reg_PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY               0x000a100dU
#define _reg_PHY_GATE_ERROR_DELAY_SELECT                   0x1004100dU
#define _reg_SC_PHY_SNAP_OBS_REGS                          0x1801100dU
#define _reg_PHY_GATE_SMPL1_SLAVE_DELAY                    0x0009100eU
#define _reg_PHY_LPDDR                                     0x1001100eU
#define _reg_PHY_MEM_CLASS                                 0x1803100eU
#define _reg_PHY_GATE_SMPL2_SLAVE_DELAY                    0x0009100fU
#define _reg_ON_FLY_GATE_ADJUST_EN                         0x1002100fU
#define _reg_PHY_GATE_TRACKING_OBS                         0x00201010U
#define _reg_PHY_DFI40_POLARITY                            0x00011011U
#define _reg_PHY_LP4_PST_AMBLE                             0x08021011U
#define _reg_PHY_RDLVL_PATT8                               0x00201012U
#define _reg_PHY_RDLVL_PATT9                               0x00201013U
#define _reg_PHY_RDLVL_PATT10                              0x00201014U
#define _reg_PHY_RDLVL_PATT11                              0x00201015U
#define _reg_PHY_RDLVL_PATT12                              0x00201016U
#define _reg_PHY_RDLVL_PATT13                              0x00201017U
#define _reg_PHY_RDLVL_PATT14                              0x00201018U
#define _reg_PHY_RDLVL_PATT15                              0x00201019U
#define _reg_PHY_SLAVE_LOOP_CNT_UPDATE                     0x0003101aU
#define _reg_PHY_SW_FIFO_PTR_RST_DISABLE                   0x0801101aU
#define _reg_PHY_MASTER_DLY_LOCK_OBS_SELECT                0x1004101aU
#define _reg_PHY_RDDQ_ENC_OBS_SELECT                       0x1803101aU
#define _reg_PHY_RDDQS_DQ_ENC_OBS_SELECT                   0x0004101bU
#define _reg_PHY_WR_ENC_OBS_SELECT                         0x0804101bU
#define _reg_PHY_WR_SHIFT_OBS_SELECT                       0x1004101bU
#define _reg_PHY_FIFO_PTR_OBS_SELECT                       0x1804101bU
#define _reg_PHY_LVL_DEBUG_MODE                            0x0001101cU
#define _reg_SC_PHY_LVL_DEBUG_CONT                         0x0801101cU
#define _reg_PHY_WRLVL_ALGO                                0x1002101cU
#define _reg_PHY_WRLVL_PER_START                           0x1808101cU
#define _reg_PHY_WRLVL_CAPTURE_CNT                         0x0006101dU
#define _reg_PHY_WRLVL_UPDT_WAIT_CNT                       0x0804101dU
#define _reg_PHY_DQ_MASK                                   0x1008101dU
#define _reg_PHY_GTLVL_PER_START                           0x000a101eU
#define _reg_PHY_GTLVL_CAPTURE_CNT                         0x1006101eU
#define _reg_PHY_GTLVL_UPDT_WAIT_CNT                       0x1804101eU
#define _reg_PHY_RDLVL_CAPTURE_CNT                         0x0006101fU
#define _reg_PHY_RDLVL_UPDT_WAIT_CNT                       0x0804101fU
#define _reg_PHY_RDLVL_OP_MODE                             0x1002101fU
#define _reg_PHY_RDLVL_RDDQS_DQ_OBS_SELECT                 0x1805101fU
#define _reg_PHY_RDLVL_PERIODIC_OBS_SELECT                 0x00081020U
#define _reg_PHY_RDLVL_DATA_MASK                           0x08081020U
#define _reg_PHY_WDQLVL_CLK_JITTER_TOLERANCE               0x10081020U
#define _reg_PHY_WDQLVL_BURST_CNT                          0x18061020U
#define _reg_PHY_WDQLVL_PATT                               0x00031021U
#define _reg_PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET           0x080b1021U
#define _reg_PHY_WDQLVL_UPDT_WAIT_CNT                      0x18041021U
#define _reg_PHY_WDQLVL_DQDM_OBS_SELECT                    0x00041022U
#define _reg_PHY_WDQLVL_PERIODIC_OBS_SELECT                0x08081022U
#define _reg_SC_PHY_WDQLVL_CLR_PREV_RESULTS                0x10011022U
#define _reg_PHY_WDQLVL_DATADM_MASK                        0x00091023U
#define _reg_PHY_USER_PATT0                                0x00201024U
#define _reg_PHY_USER_PATT1                                0x00201025U
#define _reg_PHY_USER_PATT2                                0x00201026U
#define _reg_PHY_USER_PATT3                                0x00201027U
#define _reg_PHY_USER_PATT4                                0x00101028U
#define _reg_PHY_NTP_MULT_TRAIN                            0x10011028U
#define _reg_PHY_NTP_EARLY_THRESHOLD                       0x000a1029U
#define _reg_PHY_NTP_PERIOD_THRESHOLD                      0x100a1029U
#define _reg_PHY_NTP_PERIOD_THRESHOLD_MIN                  0x000a102aU
#define _reg_PHY_NTP_PERIOD_THRESHOLD_MAX                  0x100a102aU
#define _reg_PHY_CALVL_VREF_DRIVING_SLICE                  0x0001102bU
#define _reg_SC_PHY_MANUAL_CLEAR                           0x0806102bU
#define _reg_PHY_FIFO_PTR_OBS                              0x1008102bU
#define _reg_PHY_LPBK_RESULT_OBS                           0x0020102cU
#define _reg_PHY_LPBK_ERROR_COUNT_OBS                      0x0010102dU
#define _reg_PHY_MASTER_DLY_LOCK_OBS                       0x100b102dU
#define _reg_PHY_RDDQ_SLV_DLY_ENC_OBS                      0x0007102eU
#define _reg_PHY_RDDQS_BASE_SLV_DLY_ENC_OBS                0x0807102eU
#define _reg_PHY_MEAS_DLY_STEP_VALUE                       0x1008102eU
#define _reg_PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS       0x1808102eU
#define _reg_PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS       0x0008102fU
#define _reg_PHY_RDDQS_GATE_SLV_DLY_ENC_OBS                0x080b102fU
#define _reg_PHY_WRDQS_BASE_SLV_DLY_ENC_OBS                0x1807102fU
#define _reg_PHY_WRDQ_BASE_SLV_DLY_ENC_OBS                 0x00081030U
#define _reg_PHY_WR_ADDER_SLV_DLY_ENC_OBS                  0x08081030U
#define _reg_PHY_WR_SHIFT_OBS                              0x10031030U
#define _reg_PHY_WRLVL_HARD0_DELAY_OBS                     0x000a1031U
#define _reg_PHY_WRLVL_HARD1_DELAY_OBS                     0x100a1031U
#define _reg_PHY_WRLVL_STATUS_OBS                          0x00111032U
#define _reg_PHY_GATE_SMPL1_SLV_DLY_ENC_OBS                0x000a1033U
#define _reg_PHY_GATE_SMPL2_SLV_DLY_ENC_OBS                0x100a1033U
#define _reg_PHY_WRLVL_ERROR_OBS                           0x00101034U
#define _reg_PHY_GTLVL_HARD0_DELAY_OBS                     0x100e1034U
#define _reg_PHY_GTLVL_HARD1_DELAY_OBS                     0x000e1035U
#define _reg_PHY_GTLVL_STATUS_OBS                          0x00121036U
#define _reg_PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS                 0x000a1037U
#define _reg_PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS                 0x100a1037U
#define _reg_PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS            0x00021038U
#define _reg_PHY_RDLVL_STATUS_OBS                          0x00201039U
#define _reg_PHY_RDLVL_PERIODIC_OBS                        0x0020103aU
#define _reg_PHY_WDQLVL_DQDM_LE_DLY_OBS                    0x000b103bU
#define _reg_PHY_WDQLVL_DQDM_TE_DLY_OBS                    0x100b103bU
#define _reg_PHY_WDQLVL_STATUS_OBS                         0x0020103cU
#define _reg_PHY_WDQLVL_PERIODIC_OBS                       0x0020103dU
#define _reg_PHY_DDL_MODE                                  0x001f103eU
#define _reg_PHY_DDL_MASK                                  0x0006103fU
#define _reg_PHY_DDL_TEST_OBS                              0x00201040U
#define _reg_PHY_DDL_TEST_MSTR_DLY_OBS                     0x00201041U
#define _reg_PHY_DDL_TRACK_UPD_THRESHOLD                   0x00081042U
#define _reg_PHY_LP4_WDQS_OE_EXTEND                        0x08011042U
#define _reg_SC_PHY_RX_CAL_START                           0x10011042U
#define _reg_PHY_RX_CAL_OVERRIDE                           0x18011042U
#define _reg_PHY_RX_CAL_SAMPLE_WAIT                        0x00081043U
#define _reg_PHY_SLICE_RXCAL_SHUTOFF_FDBK_OE               0x08011043U
#define _reg_PHY_RX_CAL_DQ0                                0x10091043U
#define _reg_PHY_RX_CAL_DQ1                                0x00091044U
#define _reg_PHY_RX_CAL_DQ2                                0x10091044U
#define _reg_PHY_RX_CAL_DQ3                                0x00091045U
#define _reg_PHY_RX_CAL_DQ4                                0x10091045U
#define _reg_PHY_RX_CAL_DQ5                                0x00091046U
#define _reg_PHY_RX_CAL_DQ6                                0x10091046U
#define _reg_PHY_RX_CAL_DQ7                                0x00091047U
#define _reg_PHY_RX_CAL_DM                                 0x00121048U
#define _reg_PHY_RX_CAL_DQS                                0x00091049U
#define _reg_PHY_RX_CAL_FDBK                               0x10091049U
#define _reg_PHY_RX_CAL_OBS                                0x000b104aU
#define _reg_PHY_RX_CAL_LOCK_OBS                           0x1009104aU
#define _reg_PHY_RX_CAL_DISABLE                            0x0001104bU
#define _reg_PHY_RX_CAL_SE_ADJUST                          0x0807104bU
#define _reg_PHY_RX_CAL_DIFF_ADJUST                        0x1007104bU
#define _reg_PHY_RX_CAL_COMP_VAL                           0x1801104bU
#define _reg_PHY_RX_CAL_INDEX_MASK                         0x000c104cU
#define _reg_PHY_PAD_RX_BIAS_EN                            0x100b104cU
#define _reg_PHY_STATIC_TOG_DISABLE                        0x0005104dU
#define _reg_PHY_DATA_DC_CAL_SAMPLE_WAIT                   0x0808104dU
#define _reg_PHY_DATA_DC_CAL_TIMEOUT                       0x1008104dU
#define _reg_PHY_DATA_DC_WEIGHT                            0x1802104dU
#define _reg_PHY_DATA_DC_ADJUST_START                      0x0006104eU
#define _reg_PHY_DATA_DC_ADJUST_SAMPLE_CNT                 0x0808104eU
#define _reg_PHY_DATA_DC_ADJUST_THRSHLD                    0x1008104eU
#define _reg_PHY_DATA_DC_ADJUST_DIRECT                     0x1801104eU
#define _reg_PHY_DATA_DC_CAL_POLARITY                      0x0001104fU
#define _reg_PHY_DATA_DC_CAL_START                         0x0801104fU
#define _reg_PHY_DATA_DC_SW_RANK                           0x1002104fU
#define _reg_PHY_FDBK_PWR_CTRL                             0x1803104fU
#define _reg_PHY_SLV_DLY_CTRL_GATE_DISABLE                 0x00011050U
#define _reg_PHY_RDPATH_GATE_DISABLE                       0x08011050U
#define _reg_PHY_DCC_RXCAL_CTRL_GATE_DISABLE               0x10011050U
#define _reg_PHY_SLICE_PWR_RDC_DISABLE                     0x18011050U
#define _reg_PHY_PARITY_ERROR_REGIF                        0x000b1051U
#define _reg_PHY_DS_FSM_ERROR_INFO                         0x100e1051U
#define _reg_PHY_DS_FSM_ERROR_INFO_MASK                    0x000e1052U
#define _reg_SC_PHY_DS_FSM_ERROR_INFO_WOCLR                0x100e1052U
#define _reg_PHY_DS_TRAIN_CALIB_ERROR_INFO                 0x00051053U
#define _reg_PHY_DS_TRAIN_CALIB_ERROR_INFO_MASK            0x08051053U
#define _reg_SC_PHY_DS_TRAIN_CALIB_ERROR_INFO_WOCLR        0x10051053U
#define _reg_PHY_DQ_TSEL_ENABLE                            0x00031054U
#define _reg_PHY_DQ_TSEL_SELECT                            0x08101054U
#define _reg_PHY_DQS_TSEL_ENABLE                           0x18031054U
#define _reg_PHY_DQS_TSEL_SELECT                           0x00101055U
#define _reg_PHY_TWO_CYC_PREAMBLE                          0x10021055U
#define _reg_PHY_VREF_INITIAL_START_POINT                  0x18071055U
#define _reg_PHY_VREF_INITIAL_STOP_POINT                   0x00071056U
#define _reg_PHY_VREF_TRAINING_CTRL                        0x08021056U
#define _reg_PHY_NTP_TRAIN_EN                              0x10011056U
#define _reg_PHY_NTP_WDQ_STEP_SIZE                         0x18081056U
#define _reg_PHY_NTP_WDQ_START                             0x000b1057U
#define _reg_PHY_NTP_WDQ_STOP                              0x100b1057U
#define _reg_PHY_NTP_WDQ_BIT_EN                            0x00081058U
#define _reg_PHY_WDQLVL_DVW_MIN                            0x080a1058U
#define _reg_PHY_SW_WDQLVL_DVW_MIN_EN                      0x18011058U
#define _reg_PHY_WDQLVL_PER_START_OFFSET                   0x00061059U
#define _reg_PHY_FAST_LVL_EN                               0x08041059U
#define _reg_PHY_PAD_TX_DCD                                0x10051059U
#define _reg_PHY_PAD_RX_DCD_0                              0x18051059U
#define _reg_PHY_PAD_RX_DCD_1                              0x0005105aU
#define _reg_PHY_PAD_RX_DCD_2                              0x0805105aU
#define _reg_PHY_PAD_RX_DCD_3                              0x1005105aU
#define _reg_PHY_PAD_RX_DCD_4                              0x1805105aU
#define _reg_PHY_PAD_RX_DCD_5                              0x0005105bU
#define _reg_PHY_PAD_RX_DCD_6                              0x0805105bU
#define _reg_PHY_PAD_RX_DCD_7                              0x1005105bU
#define _reg_PHY_PAD_DM_RX_DCD                             0x1805105bU
#define _reg_PHY_PAD_DQS_RX_DCD                            0x0005105cU
#define _reg_PHY_PAD_FDBK_RX_DCD                           0x0805105cU
#define _reg_PHY_PAD_DSLICE_IO_CFG                         0x1006105cU
#define _reg_PHY_RDDQ0_SLAVE_DELAY                         0x000a105dU
#define _reg_PHY_RDDQ1_SLAVE_DELAY                         0x100a105dU
#define _reg_PHY_RDDQ2_SLAVE_DELAY                         0x000a105eU
#define _reg_PHY_RDDQ3_SLAVE_DELAY                         0x100a105eU
#define _reg_PHY_RDDQ4_SLAVE_DELAY                         0x000a105fU
#define _reg_PHY_RDDQ5_SLAVE_DELAY                         0x100a105fU
#define _reg_PHY_RDDQ6_SLAVE_DELAY                         0x000a1060U
#define _reg_PHY_RDDQ7_SLAVE_DELAY                         0x100a1060U
#define _reg_PHY_RDDM_SLAVE_DELAY                          0x000a1061U
#define _reg_PHY_DATA_DC_CAL_CLK_SEL                       0x10031061U
#define _reg_PHY_DQ_OE_TIMING                              0x00081062U
#define _reg_PHY_DQ_TSEL_RD_TIMING                         0x08081062U
#define _reg_PHY_DQ_TSEL_WR_TIMING                         0x10081062U
#define _reg_PHY_DQS_OE_TIMING                             0x18081062U
#define _reg_PHY_IO_PAD_DELAY_TIMING                       0x00041063U
#define _reg_PHY_DQS_TSEL_RD_TIMING                        0x08081063U
#define _reg_PHY_DQS_OE_RD_TIMING                          0x10081063U
#define _reg_PHY_DQS_TSEL_WR_TIMING                        0x18081063U
#define _reg_PHY_VREF_SETTING_TIME                         0x00101064U
#define _reg_PHY_PAD_VREF_CTRL_DQ                          0x100c1064U
#define _reg_PHY_PER_CS_TRAINING_EN                        0x00011065U
#define _reg_PHY_DQ_IE_TIMING                              0x08081065U
#define _reg_PHY_DQS_IE_TIMING                             0x10081065U
#define _reg_PHY_RDDATA_EN_IE_DLY                          0x18021065U
#define _reg_PHY_IE_MODE                                   0x00021066U
#define _reg_PHY_DBI_MODE                                  0x08011066U
#define _reg_PHY_RDDATA_EN_TSEL_DLY                        0x10051066U
#define _reg_PHY_RDDATA_EN_OE_DLY                          0x18051066U
#define _reg_PHY_SW_MASTER_MODE                            0x00041067U
#define _reg_PHY_MASTER_DELAY_START                        0x080b1067U
#define _reg_PHY_MASTER_DELAY_STEP                         0x18061067U
#define _reg_PHY_MASTER_DELAY_WAIT                         0x00081068U
#define _reg_PHY_MASTER_DELAY_HALF_MEASURE                 0x08081068U
#define _reg_PHY_RPTR_UPDATE                               0x10041068U
#define _reg_PHY_WRLVL_DLY_STEP                            0x18081068U
#define _reg_PHY_WRLVL_DLY_FINE_STEP                       0x00041069U
#define _reg_PHY_WRLVL_RESP_WAIT_CNT                       0x08061069U
#define _reg_PHY_GTLVL_DLY_STEP                            0x10041069U
#define _reg_PHY_GTLVL_RESP_WAIT_CNT                       0x18051069U
#define _reg_PHY_GTLVL_BACK_STEP                           0x000a106aU
#define _reg_PHY_GTLVL_FINAL_STEP                          0x100a106aU
#define _reg_PHY_WDQLVL_DLY_STEP                           0x0008106bU
#define _reg_PHY_WDQLVL_QTR_DLY_STEP                       0x0804106bU
#define _reg_PHY_TOGGLE_PRE_SUPPORT                        0x1001106bU
#define _reg_PHY_RDLVL_DLY_STEP                            0x1804106bU
#define _reg_PHY_RDLVL_MAX_EDGE                            0x000a106cU
#define _reg_PHY_RDLVL_DVW_MIN                             0x000a106dU
#define _reg_PHY_SW_RDLVL_DVW_MIN_EN                       0x1001106dU
#define _reg_PHY_RDLVL_PER_START_OFFSET                    0x1806106dU
#define _reg_PHY_WRPATH_GATE_DISABLE                       0x0002106eU
#define _reg_PHY_WRPATH_GATE_TIMING                        0x0803106eU
#define _reg_PHY_DATA_DC_INIT_DISABLE                      0x1002106eU
#define _reg_PHY_DATA_DC_DQS_INIT_SLV_DELAY                0x000a106fU
#define _reg_PHY_DATA_DC_DQ_INIT_SLV_DELAY                 0x100b106fU
#define _reg_PHY_DATA_DC_WRLVL_ENABLE                      0x00011070U
#define _reg_PHY_DATA_DC_WDQLVL_ENABLE                     0x08011070U
#define _reg_PHY_DATA_DC_DM_CLK_SE_THRSHLD                 0x10081070U
#define _reg_PHY_DATA_DC_DM_CLK_DIFF_THRSHLD               0x18081070U
#define _reg_PHY_WDQ_OSC_DELTA                             0x00071071U
#define _reg_PHY_MEAS_DLY_STEP_ENABLE                      0x08061071U
#define _reg_PHY_RDDATA_EN_DLY                             0x10051071U
#define _reg_PHY_DQ_DM_SWIZZLE0                            0x00201072U
#define _reg_PHY_DQ_DM_SWIZZLE1                            0x00041073U
#define _reg_PHY_CLK_WRDQ0_SLAVE_DELAY                     0x000b1074U
#define _reg_PHY_CLK_WRDQ1_SLAVE_DELAY                     0x100b1074U
#define _reg_PHY_CLK_WRDQ2_SLAVE_DELAY                     0x000b1075U
#define _reg_PHY_CLK_WRDQ3_SLAVE_DELAY                     0x100b1075U
#define _reg_PHY_CLK_WRDQ4_SLAVE_DELAY                     0x000b1076U
#define _reg_PHY_CLK_WRDQ5_SLAVE_DELAY                     0x100b1076U
#define _reg_PHY_CLK_WRDQ6_SLAVE_DELAY                     0x000b1077U
#define _reg_PHY_CLK_WRDQ7_SLAVE_DELAY                     0x100b1077U
#define _reg_PHY_CLK_WRDM_SLAVE_DELAY                      0x000b1078U
#define _reg_PHY_CLK_WRDQS_SLAVE_DELAY                     0x100a1078U
#define _reg_PHY_WRLVL_THRESHOLD_ADJUST                    0x00021079U
#define _reg_PHY_RDDQS_DQ0_RISE_SLAVE_DELAY                0x080a1079U
#define _reg_PHY_RDDQS_DQ0_FALL_SLAVE_DELAY                0x000a107aU
#define _reg_PHY_RDDQS_DQ1_RISE_SLAVE_DELAY                0x100a107aU
#define _reg_PHY_RDDQS_DQ1_FALL_SLAVE_DELAY                0x000a107bU
#define _reg_PHY_RDDQS_DQ2_RISE_SLAVE_DELAY                0x100a107bU
#define _reg_PHY_RDDQS_DQ2_FALL_SLAVE_DELAY                0x000a107cU
#define _reg_PHY_RDDQS_DQ3_RISE_SLAVE_DELAY                0x100a107cU
#define _reg_PHY_RDDQS_DQ3_FALL_SLAVE_DELAY                0x000a107dU
#define _reg_PHY_RDDQS_DQ4_RISE_SLAVE_DELAY                0x100a107dU
#define _reg_PHY_RDDQS_DQ4_FALL_SLAVE_DELAY                0x000a107eU
#define _reg_PHY_RDDQS_DQ5_RISE_SLAVE_DELAY                0x100a107eU
#define _reg_PHY_RDDQS_DQ5_FALL_SLAVE_DELAY                0x000a107fU
#define _reg_PHY_RDDQS_DQ6_RISE_SLAVE_DELAY                0x100a107fU
#define _reg_PHY_RDDQS_DQ6_FALL_SLAVE_DELAY                0x000a1080U
#define _reg_PHY_RDDQS_DQ7_RISE_SLAVE_DELAY                0x100a1080U
#define _reg_PHY_RDDQS_DQ7_FALL_SLAVE_DELAY                0x000a1081U
#define _reg_PHY_RDDQS_DM_RISE_SLAVE_DELAY                 0x100a1081U
#define _reg_PHY_RDDQS_DM_FALL_SLAVE_DELAY                 0x000a1082U
#define _reg_PHY_RDDQS_GATE_SLAVE_DELAY                    0x100a1082U
#define _reg_PHY_RDDQS_LATENCY_ADJUST                      0x00041083U
#define _reg_PHY_WRITE_PATH_LAT_ADD                        0x08031083U
#define _reg_PHY_WRLVL_DELAY_EARLY_THRESHOLD               0x100a1083U
#define _reg_PHY_WRLVL_DELAY_PERIOD_THRESHOLD              0x000a1084U
#define _reg_PHY_WRLVL_EARLY_FORCE_ZERO                    0x10011084U
#define _reg_PHY_GTLVL_RDDQS_SLV_DLY_START                 0x000a1085U
#define _reg_PHY_GTLVL_LAT_ADJ_START                       0x10041085U
#define _reg_PHY_WDQLVL_DQDM_SLV_DLY_START                 0x000b1086U
#define _reg_PHY_NTP_WRLAT_START                           0x10041086U
#define _reg_PHY_NTP_PASS                                  0x18011086U
#define _reg_PHY_RDLVL_RDDQS_DQ_SLV_DLY_START              0x000a1087U
#define _reg_PHY_DATA_DC_DQS_CLK_ADJUST                    0x00081088U
#define _reg_PHY_DATA_DC_DQ0_CLK_ADJUST                    0x08081088U
#define _reg_PHY_DATA_DC_DQ1_CLK_ADJUST                    0x10081088U
#define _reg_PHY_DATA_DC_DQ2_CLK_ADJUST                    0x18081088U
#define _reg_PHY_DATA_DC_DQ3_CLK_ADJUST                    0x00081089U
#define _reg_PHY_DATA_DC_DQ4_CLK_ADJUST                    0x08081089U
#define _reg_PHY_DATA_DC_DQ5_CLK_ADJUST                    0x10081089U
#define _reg_PHY_DATA_DC_DQ6_CLK_ADJUST                    0x18081089U
#define _reg_PHY_DATA_DC_DQ7_CLK_ADJUST                    0x0008108aU
#define _reg_PHY_DATA_DC_DM_CLK_ADJUST                     0x0808108aU
#define _reg_PHY_DSLICE_PAD_BOOSTPN_SETTING                0x1010108aU
#define _reg_PHY_DSLICE_PAD_RX_CTLE_SETTING                0x0006108bU
#define _reg_PHY_DQ_FFE                                    0x0802108bU
#define _reg_PHY_DQS_FFE                                   0x1002108bU
#define _reg_PHY_ADR_CLK_WR_BYPASS_SLAVE_DELAY_0           0x000b1200U
#define _reg_PHY_ADR_CLK_BYPASS_OVERRIDE_0                 0x10011200U
#define _reg_SC_PHY_ADR_MANUAL_CLEAR_0                     0x18031200U
#define _reg_PHY_ADR_LPBK_RESULT_OBS_0                     0x00201201U
#define _reg_PHY_ADR_LPBK_ERROR_COUNT_OBS_0                0x00101202U
#define _reg_PHY_ADR_MEAS_DLY_STEP_VALUE_0                 0x10081202U
#define _reg_PHY_ADR_MASTER_DLY_LOCK_OBS_SELECT_0          0x18041202U
#define _reg_PHY_ADR_MASTER_DLY_LOCK_OBS_0                 0x000b1203U
#define _reg_PHY_ADR_BASE_SLV_DLY_ENC_OBS_0                0x10071203U
#define _reg_PHY_ADR_ADDER_SLV_DLY_ENC_OBS_0               0x18081203U
#define _reg_PHY_ADR_SLAVE_LOOP_CNT_UPDATE_0               0x00031204U
#define _reg_PHY_ADR_SLV_DLY_ENC_OBS_SELECT_0              0x08031204U
#define _reg_SC_PHY_ADR_SNAP_OBS_REGS_0                    0x10011204U
#define _reg_PHY_ADR_TSEL_ENABLE_0                         0x18011204U
#define _reg_PHY_ADR_LPBK_CONTROL_0                        0x00071205U
#define _reg_PHY_ADR_PRBS_PATTERN_START_0                  0x08071205U
#define _reg_PHY_ADR_PRBS_PATTERN_MASK_0                   0x10051205U
#define _reg_PHY_ADR_PWR_RDC_DISABLE_0                     0x18011205U
#define _reg_PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_0           0x00011206U
#define _reg_PHY_ADR_TYPE_0                                0x08021206U
#define _reg_PHY_ADR_WRADDR_SHIFT_OBS_0                    0x10031206U
#define _reg_PHY_ADR_IE_MODE_0                             0x18011206U
#define _reg_PHY_ADR_DDL_MODE_0                            0x001b1207U
#define _reg_PHY_ADR_DDL_MASK_0                            0x00061208U
#define _reg_PHY_ADR_DDL_TEST_OBS_0                        0x00201209U
#define _reg_PHY_ADR_DDL_TEST_MSTR_DLY_OBS_0               0x0020120aU
#define _reg_PHY_ADR_CALVL_START_0                         0x000b120bU
#define _reg_PHY_ADR_CALVL_COARSE_DLY_0                    0x100b120bU
#define _reg_PHY_ADR_CALVL_QTR_0                           0x000b120cU
#define _reg_PHY_ADR_CALVL_SWIZZLE0_0                      0x0018120dU
#define _reg_PHY_ADR_CALVL_SWIZZLE1_0                      0x0018120eU
#define _reg_PHY_ADR_CALVL_RANK_CTRL_0                     0x1802120eU
#define _reg_PHY_ADR_CALVL_NUM_PATTERNS_0                  0x0002120fU
#define _reg_PHY_ADR_CALVL_RESP_WAIT_CNT_0                 0x0804120fU
#define _reg_PHY_ADR_CALVL_PERIODIC_START_OFFSET_0         0x1009120fU
#define _reg_PHY_ADR_CALVL_DEBUG_MODE_0                    0x00011210U
#define _reg_SC_PHY_ADR_CALVL_DEBUG_CONT_0                 0x08011210U
#define _reg_SC_PHY_ADR_CALVL_ERROR_CLR_0                  0x10011210U
#define _reg_PHY_ADR_CALVL_OBS_SELECT_0                    0x18031210U
#define _reg_PHY_ADR_CALVL_CH0_OBS0_0                      0x00201211U
#define _reg_PHY_ADR_CALVL_CH1_OBS0_0                      0x00201212U
#define _reg_PHY_ADR_CALVL_CH2_OBS0_0                      0x00201213U
#define _reg_PHY_ADR_CALVL_CH3_OBS0_0                      0x00201214U
#define _reg_PHY_ADR_CALVL_OBS1_0                          0x00201215U
#define _reg_PHY_ADR_CALVL_OBS2_0                          0x00201216U
#define _reg_PHY_ADR_CALVL_FG_0_0                          0x00141217U
#define _reg_PHY_ADR_CALVL_BG_0_0                          0x00141218U
#define _reg_PHY_ADR_CALVL_FG_1_0                          0x00141219U
#define _reg_PHY_ADR_CALVL_BG_1_0                          0x0014121aU
#define _reg_PHY_ADR_CALVL_FG_2_0                          0x0014121bU
#define _reg_PHY_ADR_CALVL_BG_2_0                          0x0014121cU
#define _reg_PHY_ADR_CALVL_FG_3_0                          0x0014121dU
#define _reg_PHY_ADR_CALVL_BG_3_0                          0x0014121eU
#define _reg_PHY_ADR_ADDR_SEL_0                            0x0018121fU
#define _reg_PHY_ADR_LP4_BOOT_SLV_DELAY_0                  0x000a1220U
#define _reg_PHY_ADR_BIT_MASK_0                            0x10061220U
#define _reg_PHY_ADR_SEG_MASK_0                            0x18061220U
#define _reg_PHY_ADR_CALVL_TRAIN_MASK_0                    0x00061221U
#define _reg_PHY_ADR_CSLVL_TRAIN_MASK_0                    0x08061221U
#define _reg_PHY_ADR_STATIC_TOG_DISABLE_0                  0x10041221U
#define _reg_PHY_ADR_SW_TXIO_CTRL_0                        0x18061221U
#define _reg_PHY_ADR_DC_INIT_DISABLE_0                     0x00021222U
#define _reg_PHY_ADR_DC_ADR0_CLK_ADJUST_0                  0x08081222U
#define _reg_PHY_ADR_DC_ADR1_CLK_ADJUST_0                  0x10081222U
#define _reg_PHY_ADR_DC_ADR2_CLK_ADJUST_0                  0x18081222U
#define _reg_PHY_ADR_DC_ADR3_CLK_ADJUST_0                  0x00081223U
#define _reg_PHY_ADR_DC_ADR4_CLK_ADJUST_0                  0x08081223U
#define _reg_PHY_ADR_DC_ADR5_CLK_ADJUST_0                  0x10081223U
#define _reg_PHY_ADR_DCC_RXCAL_CTRL_GATE_DISABLE_0         0x18011223U
#define _reg_PHY_ADR_DC_CAL_SAMPLE_WAIT_0                  0x00081224U
#define _reg_PHY_ADR_DC_CAL_TIMEOUT_0                      0x08081224U
#define _reg_PHY_ADR_DC_WEIGHT_0                           0x10021224U
#define _reg_PHY_ADR_DC_ADJUST_START_0                     0x18061224U
#define _reg_PHY_ADR_DC_ADJUST_SAMPLE_CNT_0                0x00081225U
#define _reg_PHY_ADR_DC_ADJUST_THRSHLD_0                   0x08081225U
#define _reg_PHY_ADR_DC_ADJUST_DIRECT_0                    0x10011225U
#define _reg_PHY_ADR_DC_CAL_POLARITY_0                     0x18011225U
#define _reg_PHY_ADR_DC_CAL_START_0                        0x00011226U
#define _reg_PHY_ADR_SW_TXPWR_CTRL_0                       0x08061226U
#define _reg_PHY_PARITY_ERROR_REGIF_ADR_0                  0x100b1226U
#define _reg_PHY_AS_FSM_ERROR_INFO_0                       0x00091227U
#define _reg_PHY_AS_FSM_ERROR_INFO_MASK_0                  0x10091227U
#define _reg_SC_PHY_AS_FSM_ERROR_INFO_WOCLR_0              0x00091228U
#define _reg_PHY_AS_TRAIN_CALIB_ERROR_INFO_0               0x10011228U
#define _reg_PHY_AS_TRAIN_CALIB_ERROR_INFO_MASK_0          0x18011228U
#define _reg_SC_PHY_AS_TRAIN_CALIB_ERROR_INFO_WOCLR_0      0x00011229U
#define _reg_PHY_ADR_TSEL_SELECT_0                         0x0008122aU
#define _reg_PHY_ADR_DC_CAL_CLK_SEL_0                      0x0803122aU
#define _reg_PHY_PAD_ADR_IO_CFG_0                          0x100b122aU
#define _reg_PHY_ADR0_SW_WRADDR_SHIFT_0                    0x0005122bU
#define _reg_PHY_ADR0_CLK_WR_SLAVE_DELAY_0                 0x080b122bU
#define _reg_PHY_ADR1_SW_WRADDR_SHIFT_0                    0x1805122bU
#define _reg_PHY_ADR1_CLK_WR_SLAVE_DELAY_0                 0x000b122cU
#define _reg_PHY_ADR2_SW_WRADDR_SHIFT_0                    0x1005122cU
#define _reg_PHY_ADR2_CLK_WR_SLAVE_DELAY_0                 0x000b122dU
#define _reg_PHY_ADR3_SW_WRADDR_SHIFT_0                    0x1005122dU
#define _reg_PHY_ADR3_CLK_WR_SLAVE_DELAY_0                 0x000b122eU
#define _reg_PHY_ADR4_SW_WRADDR_SHIFT_0                    0x1005122eU
#define _reg_PHY_ADR4_CLK_WR_SLAVE_DELAY_0                 0x000b122fU
#define _reg_PHY_ADR5_SW_WRADDR_SHIFT_0                    0x1005122fU
#define _reg_PHY_ADR5_CLK_WR_SLAVE_DELAY_0                 0x000b1230U
#define _reg_PHY_ADR_SW_MASTER_MODE_0                      0x10041230U
#define _reg_PHY_ADR_MASTER_DELAY_START_0                  0x000b1231U
#define _reg_PHY_ADR_MASTER_DELAY_STEP_0                   0x10061231U
#define _reg_PHY_ADR_MASTER_DELAY_WAIT_0                   0x18081231U
#define _reg_PHY_ADR_MASTER_DELAY_HALF_MEASURE_0           0x00081232U
#define _reg_PHY_ADR_SW_CALVL_DVW_MIN_0                    0x080a1232U
#define _reg_PHY_ADR_SW_CALVL_DVW_MIN_EN_0                 0x18011232U
#define _reg_PHY_ADR_CALVL_DLY_STEP_0                      0x00041233U
#define _reg_PHY_ADR_CALVL_CAPTURE_CNT_0                   0x00041234U
#define _reg_PHY_ADR_MEAS_DLY_STEP_ENABLE_0                0x08011234U
#define _reg_PHY_ADR_DC_INIT_SLV_DELAY_0                   0x100a1234U
#define _reg_PHY_ADR_DC_CALVL_ENABLE_0                     0x00011235U
#define _reg_PHY_ADR_DC_DM_CLK_THRSHLD_0                   0x08081235U
#define _reg_PHY_FREQ_SEL                                  0x00031300U
#define _reg_PHY_FREQ_SEL_FROM_REGIF                       0x00011301U
#define _reg_PHY_FREQ_SEL_MULTICAST_EN                     0x08011301U
#define _reg_PHY_FREQ_SEL_INDEX                            0x10021301U
#define _reg_PHY_SW_GRP0_SHIFT_0                           0x18051301U
#define _reg_PHY_SW_GRP1_SHIFT_0                           0x00051302U
#define _reg_PHY_SW_GRP2_SHIFT_0                           0x08051302U
#define _reg_PHY_SW_GRP3_SHIFT_0                           0x10051302U
#define _reg_PHY_SW_GRP0_SHIFT_1                           0x18051302U
#define _reg_PHY_SW_GRP1_SHIFT_1                           0x00051303U
#define _reg_PHY_SW_GRP2_SHIFT_1                           0x08051303U
#define _reg_PHY_SW_GRP3_SHIFT_1                           0x10051303U
#define _reg_PHY_GRP_BYPASS_SLAVE_DELAY                    0x000b1304U
#define _reg_PHY_SW_GRP_BYPASS_SHIFT                       0x10051304U
#define _reg_PHY_GRP_BYPASS_OVERRIDE                       0x18011304U
#define _reg_SC_PHY_MANUAL_UPDATE                          0x00011305U
#define _reg_PHY_MANUAL_UPDATE_PHYUPD_ENABLE               0x08011305U
#define _reg_PHY_CSLVL_START                               0x100b1305U
#define _reg_PHY_CSLVL_COARSE_DLY                          0x000b1306U
#define _reg_PHY_CSLVL_DEBUG_MODE                          0x10011306U
#define _reg_SC_PHY_CSLVL_DEBUG_CONT                       0x18011306U
#define _reg_SC_PHY_CSLVL_ERROR_CLR                        0x00011307U
#define _reg_PHY_CSLVL_OBS0                                0x00201308U
#define _reg_PHY_CSLVL_OBS1                                0x00201309U
#define _reg_PHY_CSLVL_OBS2                                0x0020130aU
#define _reg_PHY_CSLVL_ENABLE                              0x0001130bU
#define _reg_PHY_CSLVL_PERIODIC_START_OFFSET               0x0809130bU
#define _reg_PHY_LP4_BOOT_DISABLE                          0x1801130bU
#define _reg_PHY_CSLVL_CS_MAP                              0x0002130cU
#define _reg_PHY_CSLVL_QTR                                 0x080b130cU
#define _reg_PHY_CSLVL_COARSE_CHK                          0x000b130dU
#define _reg_PHY_CSLVL_COARSE_CAPTURE_CNT                  0x1004130dU
#define _reg_PHY_ADRCTL_SLAVE_LOOP_CNT_UPDATE              0x1803130dU
#define _reg_PHY_ADRCTL_SNAP_OBS_REGS                      0x0001130eU
#define _reg_PHY_DFI_PHYUPD_TYPE                           0x0802130eU
#define _reg_PHY_ADRCTL_LPDDR                              0x1001130eU
#define _reg_PHY_LP4_ACTIVE                                0x1801130eU
#define _reg_PHY_LPDDR3_CS                                 0x0001130fU
#define _reg_PHY_CLK_DC_CAL_SAMPLE_WAIT                    0x0808130fU
#define _reg_PHY_CLK_DC_CAL_TIMEOUT                        0x1008130fU
#define _reg_PHY_CLK_DC_WEIGHT                             0x1802130fU
#define _reg_PHY_CLK_DC_FREQ_CHG_ADJ                       0x00011310U
#define _reg_PHY_CLK_DC_ADJUST_START                       0x08061310U
#define _reg_PHY_CLK_DC_ADJUST_SAMPLE_CNT                  0x10081310U
#define _reg_PHY_CLK_DC_ADJUST_THRSHLD                     0x18081310U
#define _reg_PHY_CLK_DC_ADJUST_DIRECT                      0x00011311U
#define _reg_PHY_CLK_DC_CAL_POLARITY                       0x08011311U
#define _reg_PHY_CLK_DC_CAL_START                          0x10011311U
#define _reg_SC_PHY_UPDATE_CLK_CAL_VALUES                  0x18011311U
#define _reg_PHY_CONTINUOUS_CLK_CAL_UPDATE                 0x00011312U
#define _reg_PHY_SW_TXIO_CTRL_0                            0x08041312U
#define _reg_PHY_SW_TXIO_CTRL_1                            0x10041312U
#define _reg_PHY_MEMCLK_SW_TXIO_CTRL                       0x18011312U
#define _reg_PHY_ADRCTL_SW_TXPWR_CTRL_0                    0x00041313U
#define _reg_PHY_ADRCTL_SW_TXPWR_CTRL_1                    0x08041313U
#define _reg_PHY_MEMCLK_SW_TXPWR_CTRL                      0x10011313U
#define _reg_PHY_USER_DEF_REG_AC_0                         0x00201314U
#define _reg_PHY_USER_DEF_REG_AC_1                         0x00201315U
#define _reg_PHY_USER_DEF_REG_AC_2                         0x00201316U
#define _reg_PHY_USER_DEF_REG_AC_3                         0x00201317U
#define _reg_PHY_TOP_STATIC_TOG_DISABLE                    0x00011318U
#define _reg_PHY_BYTE_DISABLE_STATIC_TOG_DISABLE           0x08011318U
#define _reg_PHY_STATIC_TOG_CONTROL                        0x10101318U
#define _reg_PHY_ADRCTL_STATIC_TOG_DISABLE                 0x00041319U
#define _reg_PHY_MEMCLK_STATIC_TOG_DISABLE                 0x08011319U
#define _reg_PHY_LP4_BOOT_PLL_BYPASS                       0x10011319U
#define _reg_PHY_CLK_SWITCH_OBS                            0x0020131aU
#define _reg_PHY_PLL_WAIT                                  0x0010131bU
#define _reg_PHY_SW_PLL_BYPASS                             0x0001131cU
#define _reg_PHY_SET_DFI_INPUT_RST_PAD                     0x0001131dU
#define _reg_PHY_CS_ACS_ALLOCATION_BIT0_0                  0x0802131dU
#define _reg_PHY_CS_ACS_ALLOCATION_BIT1_0                  0x1002131dU
#define _reg_PHY_CS_ACS_ALLOCATION_BIT2_0                  0x1802131dU
#define _reg_PHY_CS_ACS_ALLOCATION_BIT3_0                  0x0002131eU
#define _reg_PHY_CS_ACS_ALLOCATION_BIT0_1                  0x0802131eU
#define _reg_PHY_CS_ACS_ALLOCATION_BIT1_1                  0x1002131eU
#define _reg_PHY_CS_ACS_ALLOCATION_BIT2_1                  0x1802131eU
#define _reg_PHY_CS_ACS_ALLOCATION_BIT3_1                  0x0002131fU
#define _reg_PHY_CLK_DC_ADJUST_0                           0x0808131fU
#define _reg_PHY_CLK_DC_INIT_DISABLE                       0x1001131fU
#define _reg_PHY_CLK_DC_DM_THRSHLD                         0x1808131fU
#define _reg_PHY_LP4_BOOT_PLL_CTRL                         0x000d1320U
#define _reg_PHY_PLL_CTRL_OVERRIDE                         0x10101320U
#define _reg_PHY_USE_PLL_DSKEWCALLOCK                      0x00011321U
#define _reg_PHY_PLL_SPO_CAL_CTRL                          0x08131321U
#define _reg_SC_PHY_PLL_SPO_CAL_SNAP_OBS                   0x00021322U
#define _reg_PHY_PLL_OBS_0                                 0x08101322U
#define _reg_PHY_PLL_SPO_CAL_OBS_0                         0x00111323U
#define _reg_PHY_PLL_OBS_1                                 0x00101324U
#define _reg_PHY_PLL_SPO_CAL_OBS_1                         0x00111325U
#define _reg_PHY_PLL_TESTOUT_SEL                           0x18011325U
#define _reg_PHY_LP4_BOOT_LOW_FREQ_SEL                     0x00011326U
#define _reg_PHY_TCKSRE_WAIT                               0x08041326U
#define _reg_PHY_LP_WAKEUP                                 0x10081326U
#define _reg_PHY_LS_IDLE_EN                                0x18011326U
#define _reg_PHY_LP_CTRLUPD_CNTR_CFG                       0x000a1327U
#define _reg_PHY_TDFI_PHY_WRDELAY                          0x10011327U
#define _reg_PHY_PAD_FDBK_TERM                             0x00121328U
#define _reg_PHY_PAD_DATA_TERM                             0x00111329U
#define _reg_PHY_PAD_DQS_TERM                              0x0011132aU
#define _reg_PHY_PAD_ADDR_TERM                             0x0012132bU
#define _reg_PHY_PAD_CLK_TERM                              0x0012132cU
#define _reg_PHY_PAD_CKE_TERM                              0x0012132dU
#define _reg_PHY_PAD_RST_TERM                              0x0012132eU
#define _reg_PHY_PAD_CS_TERM                               0x0012132fU
#define _reg_PHY_PAD_ODT_TERM                              0x00121330U
#define _reg_PHY_ADRCTL_RX_CAL                             0x000a1331U
#define _reg_PHY_ADRCTL_LP3_RX_CAL                         0x100d1331U
#define _reg_PHY_TST_CLK_PAD_CTRL                          0x00201332U
#define _reg_PHY_TST_CLK_PAD_CTRL2                         0x00171333U
#define _reg_PHY_TST_CLK_PAD_CTRL3                         0x00171334U
#define _reg_PHY_TST_CLK_PAD_CTRL4                         0x001b1335U
#define _reg_PHY_CAL_MODE_0                                0x000d1336U
#define _reg_PHY_CAL_CLEAR_0                               0x10011336U
#define _reg_PHY_CAL_START_0                               0x18011336U
#define _reg_PHY_CAL_INTERVAL_COUNT_0                      0x00201337U
#define _reg_PHY_CAL_SAMPLE_WAIT_0                         0x00081338U
#define _reg_PHY_LP4_BOOT_CAL_CLK_SELECT_0                 0x08031338U
#define _reg_PHY_CAL_RESULT_OBS_0                          0x00181339U
#define _reg_PHY_CAL_RESULT2_OBS_0                         0x0018133aU
#define _reg_PHY_CAL_RESULT4_OBS_0                         0x0018133bU
#define _reg_PHY_CAL_RESULT5_OBS_0                         0x0018133cU
#define _reg_PHY_CAL_RESULT6_OBS_0                         0x0018133dU
#define _reg_PHY_CAL_RESULT7_OBS_0                         0x0018133eU
#define _reg_PHY_CAL_CPTR_CNT_0                            0x1807133eU
#define _reg_PHY_CAL_PU_FINE_ADJ_0                         0x0008133fU
#define _reg_PHY_CAL_PD_FINE_ADJ_0                         0x0808133fU
#define _reg_PHY_CAL_RCV_FINE_ADJ_0                        0x1008133fU
#define _reg_PHY_CAL_DBG_CFG_0                             0x1801133fU
#define _reg_SC_PHY_PAD_DBG_CONT_0                         0x00011340U
#define _reg_PHY_CAL_RESULT3_OBS_0                         0x00201341U
#define _reg_PHY_ADRCTL_PVT_MAP_0                          0x00071342U
#define _reg_PHY_CAL_SLOPE_ADJ_0                           0x08141342U
#define _reg_PHY_CAL_SLOPE_ADJ_PASS2_0                     0x00141343U
#define _reg_PHY_CAL_TWO_PASS_CFG_0                        0x00191344U
#define _reg_PHY_CAL_SW_CAL_CFG_0                          0x00171345U
#define _reg_PHY_CAL_RANGE_PASS1_PU_MAX_DELTA_0            0x18061345U
#define _reg_PHY_CAL_RANGE_PASS1_PD_MAX_DELTA_0            0x00061346U
#define _reg_PHY_CAL_RANGE_PASS1_RX_MAX_DELTA_0            0x08051346U
#define _reg_PHY_CAL_RANGE_PASS2_PU_MAX_DELTA_0            0x10061346U
#define _reg_PHY_CAL_RANGE_PASS2_PD_MAX_DELTA_0            0x18061346U
#define _reg_PHY_CAL_RANGE_PASS2_RX_MAX_DELTA_0            0x00051347U
#define _reg_PHY_CAL_RANGE_PASS1_PU_MIN_DELTA_0            0x08061347U
#define _reg_PHY_CAL_RANGE_PASS1_PD_MIN_DELTA_0            0x10061347U
#define _reg_PHY_CAL_RANGE_PASS1_RX_MIN_DELTA_0            0x18051347U
#define _reg_PHY_CAL_RANGE_PASS2_PU_MIN_DELTA_0            0x00061348U
#define _reg_PHY_CAL_RANGE_PASS2_PD_MIN_DELTA_0            0x08061348U
#define _reg_PHY_CAL_RANGE_PASS2_RX_MIN_DELTA_0            0x10051348U
#define _reg_PHY_PAD_ATB_CTRL                              0x00101349U
#define _reg_PHY_PARITY_ERROR_REGIF_AC                     0x100b1349U
#define _reg_PHY_ADRCTL_MANUAL_UPDATE                      0x0001134aU
#define _reg_PHY_AC_LPBK_ERR_CLEAR                         0x0801134aU
#define _reg_PHY_AC_LPBK_OBS_SELECT                        0x1001134aU
#define _reg_PHY_AC_LPBK_ENABLE                            0x1802134aU
#define _reg_PHY_AC_LPBK_CONTROL                           0x0009134bU
#define _reg_PHY_AC_PRBS_PATTERN_START                     0x1007134bU
#define _reg_PHY_AC_PRBS_PATTERN_MASK                      0x1804134bU
#define _reg_PHY_AC_LPBK_RESULT_OBS                        0x0020134cU
#define _reg_PHY_AC_CLK_LPBK_OBS_SELECT                    0x0001134dU
#define _reg_PHY_AC_CLK_LPBK_ENABLE                        0x0801134dU
#define _reg_PHY_AC_CLK_LPBK_CONTROL                       0x1006134dU
#define _reg_PHY_AC_CLK_LPBK_RESULT_OBS                    0x0010134eU
#define _reg_PHY_AC_PWR_RDC_DISABLE                        0x1001134eU
#define _reg_PHY_TOP_PWR_RDC_DISABLE                       0x1801134eU
#define _reg_PHY_AC_SLV_DLY_CTRL_GATE_DISABLE              0x0001134fU
#define _reg_PHY_CALVL_DEVICE_MAP                          0x0805134fU
#define _reg_PHY_ADRCTL_MSTR_DLY_ENC_SEL_0                 0x1002134fU
#define _reg_PHY_ADRCTL_MSTR_DLY_ENC_SEL_1                 0x1802134fU
#define _reg_PHY_DDL_AC_ENABLE                             0x00201350U
#define _reg_PHY_DDL_AC_MODE                               0x001a1351U
#define _reg_PHY_DDL_AC_MASK                               0x00061352U
#define _reg_PHY_INIT_UPDATE_CONFIG                        0x08031352U
#define _reg_PHY_DDL_TRACK_UPD_THRESHOLD_AC                0x10081352U
#define _reg_PHY_ERR_MASK_EN                               0x18031352U
#define _reg_PHY_ERR_STATUS                                0x00031353U
#define _reg_PHY_DS0_DQS_ERR_COUNTER                       0x00201354U
#define _reg_PHY_DS1_DQS_ERR_COUNTER                       0x00201355U
#define _reg_PHY_DLL_RST_EN                                0x00021356U
#define _reg_PHY_AC_INIT_COMPLETE_OBS                      0x080a1356U
#define _reg_PHY_DS_INIT_COMPLETE_OBS                      0x18021356U
#define _reg_PHY_UPDATE_MASK                               0x00011357U
#define _reg_PHY_AC_DCC_RXCAL_CTRL_GATE_DISABLE            0x08011357U
#define _reg_PHY_GRP_SLV_DLY_ENC_OBS_SELECT                0x10041357U
#define _reg_PHY_GRP_SHIFT_OBS_SELECT                      0x18031357U
#define _reg_PHY_GRP_SLV_DLY_ENC_OBS                       0x000b1358U
#define _reg_PHY_GRP_SHIFT_OBS                             0x10031358U
#define _reg_PHY_PARITY_ERROR_INJECTION_ENABLE             0x00011359U
#define _reg_PHY_PARITY_ERROR_REGIF_PS                     0x080b1359U
#define _reg_PHY_PLL_LOCK_DEASSERT_MASK                    0x18031359U
#define _reg_PHY_PARITY_ERROR_INFO                         0x0005135aU
#define _reg_PHY_PARITY_ERROR_INFO_MASK                    0x0805135aU
#define _reg_SC_PHY_PARITY_ERROR_INFO_WOCLR                0x1005135aU
#define _reg_PHY_TIMEOUT_ERROR_INFO                        0x000e135bU
#define _reg_PHY_TIMEOUT_ERROR_INFO_MASK                   0x100e135bU
#define _reg_SC_PHY_TIMEOUT_ERROR_INFO_WOCLR               0x000e135cU
#define _reg_PHY_PLL_FREQUENCY_ERROR                       0x1004135cU
#define _reg_PHY_PLL_FREQUENCY_ERROR_MASK                  0x1806135cU
#define _reg_SC_PHY_PLL_FREQUENCY_ERROR_WOCLR              0x0006135dU
#define _reg_PHY_PLL_DSKEWCALOUT_MIN                       0x080c135dU
#define _reg_PHY_PLL_DSKEWCALOUT_MAX                       0x000c135eU
#define _reg_PHY_PLL_DSKEWCALOUT_ERROR_INFO                0x1002135eU
#define _reg_PHY_PLL_DSKEWCALOUT_ERROR_INFO_MASK           0x1802135eU
#define _reg_SC_PHY_PLL_DSKEWCALOUT_ERROR_INFO_WOCLR       0x0002135fU
#define _reg_PHY_TOP_FSM_ERROR_INFO                        0x0809135fU
#define _reg_PHY_TOP_FSM_ERROR_INFO_MASK                   0x00091360U
#define _reg_SC_PHY_TOP_FSM_ERROR_INFO_WOCLR               0x10091360U
#define _reg_PHY_FSM_TRANSIENT_ERROR_INFO                  0x00081361U
#define _reg_PHY_FSM_TRANSIENT_ERROR_INFO_MASK             0x08081361U
#define _reg_SC_PHY_FSM_TRANSIENT_ERROR_INFO_WOCLR         0x10081361U
#define _reg_PHY_TOP_TRAIN_CALIB_ERROR_INFO                0x18021361U
#define _reg_PHY_TOP_TRAIN_CALIB_ERROR_INFO_MASK           0x00021362U
#define _reg_SC_PHY_TOP_TRAIN_CALIB_ERROR_INFO_WOCLR       0x08021362U
#define _reg_PHY_TRAIN_CALIB_ERROR_INFO                    0x10051362U
#define _reg_PHY_TRAIN_CALIB_ERROR_INFO_MASK               0x18051362U
#define _reg_SC_PHY_TRAIN_CALIB_ERROR_INFO_WOCLR           0x00051363U
#define _reg_PHY_GLOBAL_ERROR_INFO                         0x08061363U
#define _reg_PHY_GLOBAL_ERROR_INFO_MASK                    0x10061363U
#define _reg_PHY_TRAINING_TIMEOUT_VALUE                    0x00141364U
#define _reg_PHY_INIT_TIMEOUT_VALUE                        0x00141365U
#define _reg_PHY_LP_TIMEOUT_VALUE                          0x00101366U
#define _reg_PHY_PHYUPD_TIMEOUT_VALUE                      0x00201367U
#define _reg_PHY_PHYMSTR_TIMEOUT_VALUE                     0x00141368U
#define _reg_PHY_PLL_LOCK_0_MIN_VALUE                      0x18051368U
#define _reg_PHY_PLL_LOCK_TIMEOUT_VALUE                    0x00101369U
#define _reg_PHY_RDDATA_VALID_TIMEOUT_VALUE                0x10081369U
#define _reg_PHY_PLL_FREQUENCY_DELTA                       0x18041369U
#define _reg_PHY_PLL_FREQUENCY_COMPARE_INTERVAL            0x0010136aU
#define _reg_PHY_ADRCTL_FSM_ERROR_INFO_0                   0x100e136aU
#define _reg_PHY_ADRCTL_FSM_ERROR_INFO_MASK_0              0x000e136bU
#define _reg_SC_PHY_ADRCTL_FSM_ERROR_INFO_WOCLR_0          0x100e136bU
#define _reg_PHY_ADRCTL_FSM_ERROR_INFO_1                   0x000e136cU
#define _reg_PHY_ADRCTL_FSM_ERROR_INFO_MASK_1              0x100e136cU
#define _reg_SC_PHY_ADRCTL_FSM_ERROR_INFO_WOCLR_1          0x000e136dU
#define _reg_PHY_MEMCLK_FSM_ERROR_INFO_0                   0x100e136dU
#define _reg_PHY_MEMCLK_FSM_ERROR_INFO_MASK_0              0x000e136eU
#define _reg_SC_PHY_MEMCLK_FSM_ERROR_INFO_WOCLR_0          0x100e136eU
#define _reg_PHY_PAD_CAL_IO_CFG_0                          0x0012136fU
#define _reg_PHY_PAD_ACS_IO_CFG                            0x000d1370U
#define _reg_PHY_PLL_BYPASS                                0x00011371U
#define _reg_PHY_PLL_CTRL                                  0x000d1372U
#define _reg_PHY_LOW_FREQ_SEL                              0x10011372U
#define _reg_PHY_PAD_VREF_CTRL_AC                          0x000c1373U
#define _reg_PHY_CSLVL_CAPTURE_CNT                         0x10041373U
#define _reg_PHY_CSLVL_DLY_STEP                            0x18041373U
#define _reg_PHY_SW_CSLVL_DVW_MIN                          0x00091374U
#define _reg_PHY_SW_CSLVL_DVW_MIN_EN                       0x10011374U
#define _reg_PHY_LVL_MEAS_DLY_STEP_ENABLE                  0x18011374U
#define _reg_PHY_GRP0_SLAVE_DELAY_0                        0x000b1375U
#define _reg_PHY_GRP1_SLAVE_DELAY_0                        0x100b1375U
#define _reg_PHY_GRP2_SLAVE_DELAY_0                        0x000b1376U
#define _reg_PHY_GRP3_SLAVE_DELAY_0                        0x100b1376U
#define _reg_PHY_GRP0_SLAVE_DELAY_1                        0x000b1377U
#define _reg_PHY_GRP1_SLAVE_DELAY_1                        0x000b1378U
#define _reg_PHY_GRP2_SLAVE_DELAY_1                        0x000b1379U
#define _reg_PHY_GRP3_SLAVE_DELAY_1                        0x000b137aU
#define _reg_PHY_CLK_DC_CAL_CLK_SEL                        0x0003137bU
#define _reg_PHY_PAD_FDBK_DRIVE                            0x001e137cU
#define _reg_PHY_PAD_FDBK_DRIVE2                           0x0013137dU
#define _reg_PHY_PAD_DATA_DRIVE                            0x001f137eU
#define _reg_PHY_PAD_DATA_DRIVE2                           0x0001137fU
#define _reg_PHY_PAD_DQS_DRIVE                             0x00201380U
#define _reg_PHY_PAD_DQS_DRIVE2                            0x00011381U
#define _reg_PHY_PAD_ADDR_DRIVE                            0x001e1382U
#define _reg_PHY_PAD_ADDR_DRIVE2                           0x001c1383U
#define _reg_PHY_PAD_CLK_DRIVE                             0x00201384U
#define _reg_PHY_PAD_CLK_DRIVE2                            0x00131385U
#define _reg_PHY_PAD_CKE_DRIVE                             0x001e1386U
#define _reg_PHY_PAD_CKE_DRIVE2                            0x001c1387U
#define _reg_PHY_PAD_RST_DRIVE                             0x001e1388U
#define _reg_PHY_PAD_RST_DRIVE2                            0x001c1389U
#define _reg_PHY_PAD_CS_DRIVE                              0x001e138aU
#define _reg_PHY_PAD_CS_DRIVE2                             0x001c138bU
#define _reg_PHY_PAD_ODT_DRIVE                             0x001e138cU
#define _reg_PHY_PAD_ODT_DRIVE2                            0x001c138dU
#define _reg_PHY_CAL_CLK_SELECT_0                          0x0003138eU
#define _reg_PHY_CAL_VREF_SWITCH_TIMER_0                   0x0810138eU
#define _reg_PHY_CAL_SETTLING_PRD_0                        0x1807138eU
#define _reg_PI_START                                      0x00010800U
#define _reg_PI_DRAM_CLASS                                 0x08040800U
#define _reg_PI_VERSION                                    0x00200801U
#define _reg_PI_ID                                         0x00100802U
#define _reg_PI_NORMAL_LVL_SEQ                             0x00010803U
#define _reg_PI_INIT_LVL_EN                                0x08010803U
#define _reg_PI_NOTCARE_PHYUPD                             0x10010803U
#define _reg_PI_TCMD_GAP                                   0x00100804U
#define _reg_RESERVED_R0                                   0x10080804U
#define _reg_PI_TRAIN_ALL_FREQ_REQ                         0x18010804U
#define _reg_PI_DFI_VERSION                                0x00010805U
#define _reg_PI_DFI_PHYMSTR_TYPE                           0x08020805U
#define _reg_PI_DFI_PHYMSTR_CS_STATE_R                     0x10010805U
#define _reg_PI_DFI_PHYMSTR_STATE_SEL_R                    0x18010805U
#define _reg_PI_TDFI_PHYMSTR_MAX                           0x00200806U
#define _reg_PI_TDFI_PHYMSTR_RESP                          0x00140807U
#define _reg_PI_TDFI_PHYUPD_RESP                           0x00140808U
#define _reg_PI_TDFI_PHYUPD_MAX                            0x00200809U
#define _reg_PI_FREQ_MAP                                   0x0020080aU
#define _reg_PI_INIT_WORK_FREQ                             0x0005080bU
#define _reg_PI_INIT_DFS_CALVL_ONLY                        0x0801080bU
#define _reg_PI_SW_RST_N                                   0x1001080bU
#define _reg_RESERVED_V3U                                  0x1801080bU
#define _reg_PI_CS_MAP                                     0x0002080cU
#define _reg_PI_RANK_NUM_PER_CKE                           0x0805080cU
#define _reg_PI_SRX_LVL_TARGET_CS_EN                       0x1001080cU
#define _reg_PI_TMRR                                       0x1804080cU
#define _reg_PI_PREAMBLE_SUPPORT                           0x0002080dU
#define _reg_PI_MCAREF_FORWARD_ONLY                        0x0801080dU
#define _reg_PI_WRLVL_MRR_DQ_RETURN_HIZ                    0x1001080dU
#define _reg_PI_ON_DFIBUS                                  0x1801080dU
#define _reg_PI_SWLVL_LOAD                                 0x0001080eU
#define _reg_PI_SWLVL_OP_DONE                              0x0801080eU
#define _reg_PI_SW_WRLVL_RESP_0                            0x1001080eU
#define _reg_PI_SW_WRLVL_RESP_1                            0x1801080eU
#define _reg_PI_SW_RDLVL_RESP_0                            0x0002080fU
#define _reg_PI_SW_RDLVL_RESP_1                            0x0802080fU
#define _reg_PI_SW_CALVL_RESP_0                            0x1002080fU
#define _reg_PI_SW_LEVELING_MODE                           0x1803080fU
#define _reg_PI_SWLVL_START                                0x00010810U
#define _reg_PI_SWLVL_EXIT                                 0x08010810U
#define _reg_PI_SWLVL_WR_SLICE_0                           0x10010810U
#define _reg_PI_SWLVL_RD_SLICE_0                           0x18010810U
#define _reg_PI_SWLVL_VREF_UPDATE_SLICE_0                  0x00010811U
#define _reg_PI_SW_WDQLVL_RESP_0                           0x08020811U
#define _reg_PI_SWLVL_WR_SLICE_1                           0x10010811U
#define _reg_PI_SWLVL_RD_SLICE_1                           0x18010811U
#define _reg_PI_SWLVL_VREF_UPDATE_SLICE_1                  0x00010812U
#define _reg_PI_SW_WDQLVL_RESP_1                           0x08020812U
#define _reg_PI_SWLVL_SM2_START                            0x10010812U
#define _reg_PI_SWLVL_SM2_WR                               0x18010812U
#define _reg_PI_SWLVL_SM2_RD                               0x00010813U
#define _reg_PI_SEQUENTIAL_LVL_REQ                         0x08010813U
#define _reg_PI_DFS_PERIOD_EN                              0x10010813U
#define _reg_PI_SRE_PERIOD_EN                              0x18010813U
#define _reg_PI_DFI40_POLARITY                             0x00010814U
#define _reg_PI_WRLVL_REQ                                  0x08010814U
#define _reg_PI_WRLVL_CS                                   0x10010814U
#define _reg_PI_WLDQSEN                                    0x18060814U
#define _reg_PI_WLMRD                                      0x00060815U
#define _reg_PI_WRLVL_INTERVAL                             0x08100815U
#define _reg_PI_WRLVL_PERIODIC                             0x18010815U
#define _reg_PI_WRLVL_ON_SREF_EXIT                         0x00010816U
#define _reg_PI_WRLVL_DISABLE_DFS                          0x08010816U
#define _reg_PI_WRLVL_RESP_MASK                            0x10020816U
#define _reg_PI_WRLVL_ROTATE                               0x18010816U
#define _reg_PI_WRLVL_CS_MAP                               0x00020817U
#define _reg_PI_WRLVL_ERROR_STATUS                         0x08010817U
#define _reg_PI_TDFI_WRLVL_EN                              0x10080817U
#define _reg_PI_TDFI_WRLVL_RESP                            0x00200818U
#define _reg_PI_TDFI_WRLVL_MAX                             0x00200819U
#define _reg_PI_WRLVL_STROBE_NUM                           0x0005081aU
#define _reg_PI_TODTH_WR                                   0x0804081aU
#define _reg_PI_TODTH_RD                                   0x1004081aU
#define _reg_PI_ODT_VALUE                                  0x1802081aU
#define _reg_PI_RDLVL_REQ                                  0x0001081bU
#define _reg_PI_RDLVL_GATE_REQ                             0x0801081bU
#define _reg_PI_RDLVL_CS                                   0x1001081bU
#define _reg_PI_RDLVL_PAT_0                                0x0020081cU
#define _reg_PI_RDLVL_PAT_1                                0x0020081dU
#define _reg_PI_RDLVL_PAT_2                                0x0020081eU
#define _reg_PI_RDLVL_PAT_3                                0x0020081fU
#define _reg_PI_RDLVL_PAT_4                                0x00200820U
#define _reg_PI_RDLVL_PAT_5                                0x00200821U
#define _reg_PI_RDLVL_PAT_6                                0x00200822U
#define _reg_PI_RDLVL_PAT_7                                0x00200823U
#define _reg_PI_RDLVL_SEQ_EN                               0x00040824U
#define _reg_PI_RDLVL_PERIODIC                             0x08010824U
#define _reg_PI_RDLVL_ON_SREF_EXIT                         0x10010824U
#define _reg_PI_RDLVL_DISABLE_DFS                          0x18010824U
#define _reg_PI_RDLVL_GATE_PERIODIC                        0x00010825U
#define _reg_PI_RDLVL_GATE_ON_SREF_EXIT                    0x08010825U
#define _reg_PI_RDLVL_GATE_DISABLE_DFS                     0x10010825U
#define _reg_PI_RDLVL_ROTATE                               0x18010825U
#define _reg_PI_RDLVL_GATE_ROTATE                          0x00010826U
#define _reg_PI_RDLVL_CS_MAP                               0x08020826U
#define _reg_PI_RDLVL_GATE_CS_MAP                          0x10020826U
#define _reg_PI_TDFI_RDLVL_RR                              0x000a0827U
#define _reg_PI_TDFI_RDLVL_RESP                            0x00200828U
#define _reg_PI_RDLVL_RESP_MASK                            0x00020829U
#define _reg_PI_TDFI_RDLVL_EN                              0x08080829U
#define _reg_PI_TDFI_RDLVL_MAX                             0x0020082aU
#define _reg_PI_RDLVL_ERROR_STATUS                         0x0001082bU
#define _reg_PI_RDLVL_INTERVAL                             0x0810082bU
#define _reg_PI_RDLVL_GATE_INTERVAL                        0x0010082cU
#define _reg_PI_RDLVL_PATTERN_START                        0x1004082cU
#define _reg_PI_RDLVL_PATTERN_NUM                          0x1804082cU
#define _reg_PI_RDLVL_STROBE_NUM                           0x0005082dU
#define _reg_PI_RDLVL_GATE_STROBE_NUM                      0x0805082dU
#define _reg_PI_RD_PREAMBLE_TRAINING_EN                    0x1001082dU
#define _reg_PI_REG_DIMM_ENABLE                            0x1801082dU
#define _reg_PI_TDFI_RDDATA_EN                             0x0007082eU
#define _reg_PI_TDFI_PHY_WRLAT                             0x0807082eU
#define _reg_PI_CALVL_REQ                                  0x1001082eU
#define _reg_PI_CALVL_CS                                   0x1801082eU
#define _reg_PI_WRLVL_EN_DEASSERT_2_MRR                    0x0001082fU
#define _reg_RESERVED_R1                                   0x0804082fU
#define _reg_PI_CALVL_SEQ_EN                               0x1002082fU
#define _reg_PI_CALVL_PERIODIC                             0x1801082fU
#define _reg_PI_CALVL_ON_SREF_EXIT                         0x00010830U
#define _reg_PI_CALVL_DISABLE_DFS                          0x08010830U
#define _reg_PI_CALVL_ROTATE                               0x10010830U
#define _reg_PI_CALVL_CS_MAP                               0x18020830U
#define _reg_PI_TDFI_CALVL_EN                              0x00080831U
#define _reg_PI_TDFI_CALVL_RESP                            0x00200832U
#define _reg_PI_TDFI_CALVL_MAX                             0x00200833U
#define _reg_PI_CALVL_RESP_MASK                            0x00010834U
#define _reg_PI_CALVL_ERROR_STATUS                         0x08020834U
#define _reg_PI_CALVL_INTERVAL                             0x10100834U
#define _reg_PI_TCACKEL                                    0x00050835U
#define _reg_PI_TCAMRD                                     0x08060835U
#define _reg_PI_TCACKEH                                    0x10050835U
#define _reg_PI_TCAEXT                                     0x18050835U
#define _reg_PI_CA_TRAIN_VREF_EN                           0x00010836U
#define _reg_PI_CALVL_VREF_INITIAL_STEPSIZE                0x08040836U
#define _reg_PI_CALVL_VREF_NORMAL_STEPSIZE                 0x10040836U
#define _reg_PI_TDFI_INIT_START_MIN                        0x18080836U
#define _reg_PI_TDFI_INIT_COMPLETE_MIN                     0x00080837U
#define _reg_PI_TCKCKEH                                    0x08040837U
#define _reg_PI_CALVL_STROBE_NUM                           0x10050837U
#define _reg_PI_SW_CA_TRAIN_VREF                           0x18070837U
#define _reg_PI_CLKDISABLE_2_INIT_START                    0x00080838U
#define _reg_PI_INIT_STARTORCOMPLETE_2_CLKDISABLE          0x08080838U
#define _reg_PI_DRAM_CLK_DISABLE_DEASSERT_SEL              0x10010838U
#define _reg_PI_REFRESH_BETWEEN_SEGMENT_DISABLE            0x18010838U
#define _reg_PI_MC_DFS_PI_SET_VREF_ENABLE                  0x00010839U
#define _reg_PI_FSM_ERROR_INFO_MASK                        0x080d0839U
#define _reg_PI_SC_FSM_ERROR_INFO_WOCLR                    0x000d083aU
#define _reg_PI_FSM_ERROR_INFO                             0x100d083aU
#define _reg_PI_WDQLVL_VREF_EN                             0x0001083bU
#define _reg_PI_WDQLVL_BST_NUM                             0x0803083bU
#define _reg_PI_WDQLVL_RESP_MASK                           0x1002083bU
#define _reg_PI_WDQLVL_ROTATE                              0x1801083bU
#define _reg_PI_WDQLVL_CS_MAP                              0x0002083cU
#define _reg_PI_WDQLVL_VREF_INITIAL_STEPSIZE               0x0805083cU
#define _reg_PI_WDQLVL_VREF_NORMAL_STEPSIZE                0x1005083cU
#define _reg_PI_WDQLVL_PERIODIC                            0x1801083cU
#define _reg_PI_WDQLVL_REQ                                 0x0001083dU
#define _reg_PI_WDQLVL_CS                                  0x0801083dU
#define _reg_PI_TDFI_WDQLVL_EN                             0x1008083dU
#define _reg_PI_TDFI_WDQLVL_RESP                           0x0020083eU
#define _reg_PI_TDFI_WDQLVL_MAX                            0x0020083fU
#define _reg_PI_WDQLVL_INTERVAL                            0x00100840U
#define _reg_PI_WDQLVL_ON_SREF_EXIT                        0x10010840U
#define _reg_PI_WDQLVL_DISABLE_DFS                         0x18010840U
#define _reg_PI_WDQLVL_ERROR_STATUS                        0x00020841U
#define _reg_PI_WDQLVL_OSC_EN                              0x08010841U
#define _reg_PI_DQS_OSC_PERIOD_EN                          0x10010841U
#define _reg_PI_BANK_DIFF                                  0x18020841U
#define _reg_PI_ROW_DIFF                                   0x00030842U
#define _reg_PI_TCCD                                       0x08050842U
#define _reg_RESERVED_R2                                   0x10040842U
#define _reg_RESERVED_R3                                   0x18040842U
#define _reg_RESERVED_R4                                   0x00040843U
#define _reg_RESERVED_R5                                   0x08040843U
#define _reg_RESERVED_R6                                   0x10040843U
#define _reg_RESERVED_R7                                   0x18040843U
#define _reg_RESERVED_R8                                   0x00040844U
#define _reg_RESERVED_R9                                   0x08040844U
#define _reg_RESERVED_R10                                  0x10040844U
#define _reg_RESERVED_R11                                  0x18040844U
#define _reg_RESERVED_R12                                  0x00040845U
#define _reg_RESERVED_R13                                  0x08040845U
#define _reg_RESERVED_R14                                  0x10040845U
#define _reg_RESERVED_R15                                  0x18040845U
#define _reg_RESERVED_R16                                  0x00040846U
#define _reg_RESERVED_R17                                  0x08040846U
#define _reg_RESERVED_R18                                  0x10040846U
#define _reg_RESERVED_R19                                  0x18040846U
#define _reg_RESERVED_R20                                  0x00040847U
#define _reg_RESERVED_R21                                  0x08040847U
#define _reg_PI_INT_STATUS                                 0x00170848U
#define _reg_PI_INT_ACK                                    0x00160849U
#define _reg_PI_INT_MASK                                   0x0017084aU
#define _reg_PI_BIST_EXP_DATA_P0                           0x0020084bU
#define _reg_PI_BIST_EXP_DATA_P1                           0x0020084cU
#define _reg_PI_BIST_FAIL_DATA_P0                          0x0020084dU
#define _reg_PI_BIST_FAIL_DATA_P1                          0x0020084eU
#define _reg_PI_BIST_FAIL_ADDR_P0                          0x0020084fU
#define _reg_PI_BIST_FAIL_ADDR_P1                          0x00010850U
#define _reg_PI_BSTLEN                                     0x08050850U
#define _reg_PI_LONG_COUNT_MASK                            0x10050850U
#define _reg_PI_DATA_BYTE_SWAP_EN                          0x18010850U
#define _reg_PI_DATA_BYTE_SWAP_SLICE0                      0x00010851U
#define _reg_PI_DATA_BYTE_SWAP_SLICE1                      0x08010851U
#define _reg_PI_CTRLUPD_REQ_PER_AREF_EN                    0x10010851U
#define _reg_PI_TDFI_CTRLUPD_MIN                           0x18080851U
#define _reg_PI_UPDATE_ERROR_STATUS                        0x00020852U
#define _reg_PI_BIST_GO                                    0x08010852U
#define _reg_PI_BIST_RESULT                                0x10020852U
#define _reg_PI_ADDR_SPACE                                 0x18060852U
#define _reg_PI_BIST_DATA_CHECK                            0x00010853U
#define _reg_PI_BIST_ADDR_CHECK                            0x08010853U
#define _reg_PI_BIST_START_ADDRESS_P0                      0x00200854U
#define _reg_PI_BIST_START_ADDRESS_P1                      0x00010855U
#define _reg_PI_MBIST_INIT_PATTERN                         0x08080855U
#define _reg_PI_BIST_DATA_MASK                             0x00200856U
#define _reg_PI_BIST_ERR_COUNT                             0x000c0857U
#define _reg_PI_BIST_ERR_STOP                              0x100c0857U
#define _reg_PI_BIST_ADDR_MASK_0_P0                        0x00200858U
#define _reg_PI_BIST_ADDR_MASK_0_P1                        0x00020859U
#define _reg_PI_BIST_ADDR_MASK_1_P0                        0x0020085aU
#define _reg_PI_BIST_ADDR_MASK_1_P1                        0x0002085bU
#define _reg_PI_BIST_ADDR_MASK_2_P0                        0x0020085cU
#define _reg_PI_BIST_ADDR_MASK_2_P1                        0x0002085dU
#define _reg_PI_BIST_ADDR_MASK_3_P0                        0x0020085eU
#define _reg_PI_BIST_ADDR_MASK_3_P1                        0x0002085fU
#define _reg_PI_BIST_ADDR_MASK_4_P0                        0x00200860U
#define _reg_PI_BIST_ADDR_MASK_4_P1                        0x00020861U
#define _reg_PI_BIST_ADDR_MASK_5_P0                        0x00200862U
#define _reg_PI_BIST_ADDR_MASK_5_P1                        0x00020863U
#define _reg_PI_BIST_ADDR_MASK_6_P0                        0x00200864U
#define _reg_PI_BIST_ADDR_MASK_6_P1                        0x00020865U
#define _reg_PI_BIST_ADDR_MASK_7_P0                        0x00200866U
#define _reg_PI_BIST_ADDR_MASK_7_P1                        0x00020867U
#define _reg_PI_BIST_ADDR_MASK_8_P0                        0x00200868U
#define _reg_PI_BIST_ADDR_MASK_8_P1                        0x00020869U
#define _reg_PI_BIST_ADDR_MASK_9_P0                        0x0020086aU
#define _reg_PI_BIST_ADDR_MASK_9_P1                        0x0002086bU
#define _reg_PI_BIST_MODE                                  0x0803086bU
#define _reg_PI_BIST_ADDR_MODE                             0x1002086bU
#define _reg_PI_BIST_PAT_MODE                              0x1802086bU
#define _reg_PI_BIST_USER_PAT_P0                           0x0020086cU
#define _reg_PI_BIST_USER_PAT_P1                           0x0020086dU
#define _reg_PI_BIST_PAT_NUM                               0x0004086eU
#define _reg_PI_BIST_STAGE_0                               0x001e086fU
#define _reg_PI_BIST_STAGE_1                               0x001e0870U
#define _reg_PI_BIST_STAGE_2                               0x001e0871U
#define _reg_PI_BIST_STAGE_3                               0x001e0872U
#define _reg_PI_BIST_STAGE_4                               0x001e0873U
#define _reg_PI_BIST_STAGE_5                               0x001e0874U
#define _reg_PI_BIST_STAGE_6                               0x001e0875U
#define _reg_PI_BIST_STAGE_7                               0x001e0876U
#define _reg_PI_COL_DIFF                                   0x00040877U
#define _reg_PI_SELF_REFRESH_EN                            0x08010877U
#define _reg_PI_PWRUP_SREFRESH_EXIT                        0x10010877U
#define _reg_PI_MONITOR_SRC_SEL_0                          0x18040877U
#define _reg_PI_MONITOR_CAP_SEL_0                          0x00010878U
#define _reg_PI_MONITOR_0                                  0x08080878U
#define _reg_PI_MONITOR_SRC_SEL_1                          0x10040878U
#define _reg_PI_MONITOR_CAP_SEL_1                          0x18010878U
#define _reg_PI_MONITOR_1                                  0x00080879U
#define _reg_PI_MONITOR_SRC_SEL_2                          0x08040879U
#define _reg_PI_MONITOR_CAP_SEL_2                          0x10010879U
#define _reg_PI_MONITOR_2                                  0x18080879U
#define _reg_PI_MONITOR_SRC_SEL_3                          0x0004087aU
#define _reg_PI_MONITOR_CAP_SEL_3                          0x0801087aU
#define _reg_PI_MONITOR_3                                  0x1008087aU
#define _reg_PI_MONITOR_SRC_SEL_4                          0x1804087aU
#define _reg_PI_MONITOR_CAP_SEL_4                          0x0001087bU
#define _reg_PI_MONITOR_4                                  0x0808087bU
#define _reg_PI_MONITOR_SRC_SEL_5                          0x1004087bU
#define _reg_PI_MONITOR_CAP_SEL_5                          0x1801087bU
#define _reg_PI_MONITOR_5                                  0x0008087cU
#define _reg_PI_MONITOR_SRC_SEL_6                          0x0804087cU
#define _reg_PI_MONITOR_CAP_SEL_6                          0x1001087cU
#define _reg_PI_MONITOR_6                                  0x1808087cU
#define _reg_PI_MONITOR_SRC_SEL_7                          0x0004087dU
#define _reg_PI_MONITOR_CAP_SEL_7                          0x0801087dU
#define _reg_PI_MONITOR_7                                  0x1008087dU
#define _reg_PI_MONITOR_STROBE                             0x0008087eU
#define _reg_PI_DLL_LOCK                                   0x0001087fU
#define _reg_PI_FREQ_NUMBER_STATUS                         0x0805087fU
#define _reg_RESERVED_R22                                  0x1001087fU
#define _reg_PI_PHYMSTR_TYPE                               0x1802087fU
#define _reg_RESERVED_R23                                  0x00010880U
#define _reg_PI_POWER_REDUC_EN                             0x08010880U
#define _reg_RESERVED_R24                                  0x10010880U
#define _reg_RESERVED_R25                                  0x18010880U
#define _reg_RESERVED_R26                                  0x00010881U
#define _reg_RESERVED_R27                                  0x08010881U
#define _reg_RESERVED_R28                                  0x10010881U
#define _reg_RESERVED_R29                                  0x18010881U
#define _reg_RESERVED_R30                                  0x00010882U
#define _reg_RESERVED_R31                                  0x08010882U
#define _reg_RESERVED_R32                                  0x10010882U
#define _reg_RESERVED_R33                                  0x18010882U
#define _reg_RESERVED_R34                                  0x00010883U
#define _reg_RESERVED_R35                                  0x08010883U
#define _reg_RESERVED_R36                                  0x10010883U
#define _reg_RESERVED_R37                                  0x18010883U
#define _reg_RESERVED_R38                                  0x00010884U
#define _reg_PI_WRLVL_MAX_STROBE_PEND                      0x08080884U
#define _reg_PI_TREFBW_THR                                 0x10090884U
#define _reg_PI_FREQ_CHANGE_REG_COPY                       0x00050885U
#define _reg_PI_FREQ_SEL_FROM_REGIF                        0x00010886U
#define _reg_RESERVED_R39                                  0x08050886U
#define _reg_PI_CATR                                       0x10020886U
#define _reg_PI_NO_CATR_READ                               0x18010886U
#define _reg_PI_MASK_INIT_COMPLETE                         0x00010887U
#define _reg_PI_DISCONNECT_MC                              0x08010887U
#define _reg_PI_TRACE_MC_MR13                              0x10010887U
#define _reg_PI_TSDO_F0                                    0x18080887U
#define _reg_PI_TSDO_F1                                    0x00080888U
#define _reg_PI_TSDO_F2                                    0x08080888U
#define _reg_PI_TDELAY_RDWR_2_BUS_IDLE_F0                  0x00080889U
#define _reg_PI_TDELAY_RDWR_2_BUS_IDLE_F1                  0x0008088aU
#define _reg_PI_TDELAY_RDWR_2_BUS_IDLE_F2                  0x0008088bU
#define _reg_PI_WRLAT_F0                                   0x0807088bU
#define _reg_PI_CASLAT_LIN_F0                              0x1007088bU
#define _reg_PI_WRLAT_F1                                   0x1807088bU
#define _reg_PI_CASLAT_LIN_F1                              0x0007088cU
#define _reg_PI_WRLAT_F2                                   0x0807088cU
#define _reg_PI_CASLAT_LIN_F2                              0x1007088cU
#define _reg_PI_TRFC_F0                                    0x000a088dU
#define _reg_PI_TREF_F0                                    0x0014088eU
#define _reg_PI_TRFC_F1                                    0x000a088fU
#define _reg_PI_TREF_F1                                    0x00140890U
#define _reg_PI_TRFC_F2                                    0x000a0891U
#define _reg_PI_TREF_F2                                    0x00140892U
#define _reg_PI_TDFI_CTRL_DELAY_F0                         0x18040892U
#define _reg_PI_TDFI_CTRL_DELAY_F1                         0x00040893U
#define _reg_PI_TDFI_CTRL_DELAY_F2                         0x08040893U
#define _reg_PI_WRLVL_EN_F0                                0x10020893U
#define _reg_PI_WRLVL_EN_F1                                0x18020893U
#define _reg_PI_WRLVL_EN_F2                                0x00020894U
#define _reg_PI_TDFI_WRLVL_WW_F0                           0x080a0894U
#define _reg_PI_TDFI_WRLVL_WW_F1                           0x000a0895U
#define _reg_PI_TDFI_WRLVL_WW_F2                           0x100a0895U
#define _reg_PI_TODTL_2CMD_F0                              0x00080896U
#define _reg_PI_ODT_EN_F0                                  0x08010896U
#define _reg_PI_TODTL_2CMD_F1                              0x10080896U
#define _reg_PI_ODT_EN_F1                                  0x18010896U
#define _reg_PI_TODTL_2CMD_F2                              0x00080897U
#define _reg_PI_ODT_EN_F2                                  0x08010897U
#define _reg_PI_ODTLON_F0                                  0x10040897U
#define _reg_PI_TODTON_MIN_F0                              0x18040897U
#define _reg_PI_ODTLON_F1                                  0x00040898U
#define _reg_PI_TODTON_MIN_F1                              0x08040898U
#define _reg_PI_ODTLON_F2                                  0x10040898U
#define _reg_PI_TODTON_MIN_F2                              0x18040898U
#define _reg_PI_RDLVL_EN_F0                                0x00020899U
#define _reg_PI_RDLVL_GATE_EN_F0                           0x08020899U
#define _reg_PI_RDLVL_EN_F1                                0x10020899U
#define _reg_PI_RDLVL_GATE_EN_F1                           0x18020899U
#define _reg_PI_RDLVL_EN_F2                                0x0002089aU
#define _reg_PI_RDLVL_GATE_EN_F2                           0x0802089aU
#define _reg_PI_RDLVL_PAT0_EN_F0                           0x1002089aU
#define _reg_PI_RDLVL_RXCAL_EN_F0                          0x1802089aU
#define _reg_PI_RDLVL_DFE_EN_F0                            0x0002089bU
#define _reg_PI_RDLVL_MULTI_EN_F0                          0x0802089bU
#define _reg_PI_RDLVL_PAT0_EN_F1                           0x1002089bU
#define _reg_PI_RDLVL_RXCAL_EN_F1                          0x1802089bU
#define _reg_PI_RDLVL_DFE_EN_F1                            0x0002089cU
#define _reg_PI_RDLVL_MULTI_EN_F1                          0x0802089cU
#define _reg_PI_RDLVL_PAT0_EN_F2                           0x1002089cU
#define _reg_PI_RDLVL_RXCAL_EN_F2                          0x1802089cU
#define _reg_PI_RDLVL_DFE_EN_F2                            0x0002089dU
#define _reg_PI_RDLVL_MULTI_EN_F2                          0x0802089dU
#define _reg_PI_RDLAT_ADJ_F0                               0x1007089dU
#define _reg_PI_RDLAT_ADJ_F1                               0x1807089dU
#define _reg_PI_RDLAT_ADJ_F2                               0x0007089eU
#define _reg_PI_WRLAT_ADJ_F0                               0x0807089eU
#define _reg_PI_WRLAT_ADJ_F1                               0x1007089eU
#define _reg_PI_WRLAT_ADJ_F2                               0x1807089eU
#define _reg_PI_TDFI_PHY_WRDATA_F0                         0x0003089fU
#define _reg_PI_TDFI_PHY_WRDATA_F1                         0x0803089fU
#define _reg_PI_TDFI_PHY_WRDATA_F2                         0x1003089fU
#define _reg_PI_TDFI_CALVL_CC_F0                           0x000a08a0U
#define _reg_PI_TDFI_CALVL_CAPTURE_F0                      0x100a08a0U
#define _reg_PI_TDFI_CALVL_CC_F1                           0x000a08a1U
#define _reg_PI_TDFI_CALVL_CAPTURE_F1                      0x100a08a1U
#define _reg_PI_TDFI_CALVL_CC_F2                           0x000a08a2U
#define _reg_PI_TDFI_CALVL_CAPTURE_F2                      0x100a08a2U
#define _reg_PI_CALVL_EN_F0                                0x000208a3U
#define _reg_PI_CALVL_EN_F1                                0x080208a3U
#define _reg_PI_CALVL_EN_F2                                0x100208a3U
#define _reg_PI_TMRZ_F0                                    0x180508a3U
#define _reg_PI_TCAENT_F0                                  0x000e08a4U
#define _reg_PI_TMRZ_F1                                    0x100508a4U
#define _reg_PI_TCAENT_F1                                  0x000e08a5U
#define _reg_PI_TMRZ_F2                                    0x100508a5U
#define _reg_PI_TCAENT_F2                                  0x000e08a6U
#define _reg_PI_TDFI_CACSCA_F0                             0x100508a6U
#define _reg_PI_TDFI_CASEL_F0                              0x180508a6U
#define _reg_PI_TVREF_SHORT_F0                             0x000a08a7U
#define _reg_PI_TVREF_LONG_F0                              0x100a08a7U
#define _reg_PI_TDFI_CACSCA_F1                             0x000508a8U
#define _reg_PI_TDFI_CASEL_F1                              0x080508a8U
#define _reg_PI_TVREF_SHORT_F1                             0x100a08a8U
#define _reg_PI_TVREF_LONG_F1                              0x000a08a9U
#define _reg_PI_TDFI_CACSCA_F2                             0x100508a9U
#define _reg_PI_TDFI_CASEL_F2                              0x180508a9U
#define _reg_PI_TVREF_SHORT_F2                             0x000a08aaU
#define _reg_PI_TVREF_LONG_F2                              0x100a08aaU
#define _reg_PI_CALVL_VREF_INITIAL_START_POINT_F0          0x000708abU
#define _reg_PI_CALVL_VREF_INITIAL_STOP_POINT_F0           0x080708abU
#define _reg_PI_CALVL_VREF_INITIAL_START_POINT_F1          0x100708abU
#define _reg_PI_CALVL_VREF_INITIAL_STOP_POINT_F1           0x180708abU
#define _reg_PI_CALVL_VREF_INITIAL_START_POINT_F2          0x000708acU
#define _reg_PI_CALVL_VREF_INITIAL_STOP_POINT_F2           0x080708acU
#define _reg_PI_CALVL_VREF_DELTA_F0                        0x100408acU
#define _reg_PI_CALVL_VREF_DELTA_F1                        0x180408acU
#define _reg_PI_CALVL_VREF_DELTA_F2                        0x000408adU
#define _reg_PI_TDFI_CALVL_STROBE_F0                       0x080408adU
#define _reg_PI_TXP_F0                                     0x100508adU
#define _reg_PI_TMRWCKEL_F0                                0x180808adU
#define _reg_PI_TCKELCK_F0                                 0x000508aeU
#define _reg_PI_TDFI_CALVL_STROBE_F1                       0x080408aeU
#define _reg_PI_TXP_F1                                     0x100508aeU
#define _reg_PI_TMRWCKEL_F1                                0x180808aeU
#define _reg_PI_TCKELCK_F1                                 0x000508afU
#define _reg_PI_TDFI_CALVL_STROBE_F2                       0x080408afU
#define _reg_PI_TXP_F2                                     0x100508afU
#define _reg_PI_TMRWCKEL_F2                                0x180808afU
#define _reg_PI_TCKELCK_F2                                 0x000508b0U
#define _reg_PI_TDFI_INIT_START_F0                         0x080a08b0U
#define _reg_PI_TDFI_INIT_COMPLETE_F0                      0x001008b1U
#define _reg_PI_TDFI_INIT_START_F1                         0x100a08b1U
#define _reg_PI_TDFI_INIT_COMPLETE_F1                      0x001008b2U
#define _reg_PI_TDFI_INIT_START_F2                         0x100a08b2U
#define _reg_PI_TDFI_INIT_COMPLETE_F2                      0x001008b3U
#define _reg_PI_TCKEHDQS_F0                                0x100608b3U
#define _reg_PI_TFC_F0                                     0x000a08b4U
#define _reg_PI_TCKEHDQS_F1                                0x100608b4U
#define _reg_PI_TFC_F1                                     0x000a08b5U
#define _reg_PI_TCKEHDQS_F2                                0x100608b5U
#define _reg_PI_TFC_F2                                     0x000a08b6U
#define _reg_PI_TDFI_WDQLVL_WR_F0                          0x100a08b6U
#define _reg_PI_TDFI_WDQLVL_RW_F0                          0x000a08b7U
#define _reg_PI_WDQLVL_VREF_INITIAL_START_POINT_F0         0x100708b7U
#define _reg_PI_WDQLVL_VREF_INITIAL_STOP_POINT_F0          0x180708b7U
#define _reg_PI_WDQLVL_VREF_DELTA_F0                       0x000408b8U
#define _reg_PI_WDQLVL_EN_F0                               0x080208b8U
#define _reg_PI_NTP_TRAIN_EN_F0                            0x100208b8U
#define _reg_PI_TDFI_WDQLVL_WR_F1                          0x000a08b9U
#define _reg_PI_TDFI_WDQLVL_RW_F1                          0x100a08b9U
#define _reg_PI_WDQLVL_VREF_INITIAL_START_POINT_F1         0x000708baU
#define _reg_PI_WDQLVL_VREF_INITIAL_STOP_POINT_F1          0x080708baU
#define _reg_PI_WDQLVL_VREF_DELTA_F1                       0x100408baU
#define _reg_PI_WDQLVL_EN_F1                               0x180208baU
#define _reg_PI_NTP_TRAIN_EN_F1                            0x000208bbU
#define _reg_PI_TDFI_WDQLVL_WR_F2                          0x080a08bbU
#define _reg_PI_TDFI_WDQLVL_RW_F2                          0x000a08bcU
#define _reg_PI_WDQLVL_VREF_INITIAL_START_POINT_F2         0x100708bcU
#define _reg_PI_WDQLVL_VREF_INITIAL_STOP_POINT_F2          0x180708bcU
#define _reg_PI_WDQLVL_VREF_DELTA_F2                       0x000408bdU
#define _reg_PI_WDQLVL_EN_F2                               0x080208bdU
#define _reg_PI_NTP_TRAIN_EN_F2                            0x100208bdU
#define _reg_PI_TRTP_F0                                    0x180808bdU
#define _reg_PI_TRP_F0                                     0x000808beU
#define _reg_PI_TRCD_F0                                    0x080808beU
#define _reg_PI_TWTR_F0                                    0x100608beU
#define _reg_PI_TWR_F0                                     0x180808beU
#define _reg_PI_TRAS_MAX_F0                                0x001008bfU
#define _reg_PI_TRAS_MIN_F0                                0x100808bfU
#define _reg_PI_TDQSCK_MAX_F0                              0x180408bfU
#define _reg_PI_TCCDMW_F0                                  0x000608c0U
#define _reg_PI_TSR_F0                                     0x080808c0U
#define _reg_PI_TMRD_F0                                    0x100808c0U
#define _reg_PI_TMRW_F0                                    0x180808c0U
#define _reg_PI_TRTP_F1                                    0x000808c1U
#define _reg_PI_TRP_F1                                     0x080808c1U
#define _reg_PI_TRCD_F1                                    0x100808c1U
#define _reg_PI_TWTR_F1                                    0x180608c1U
#define _reg_PI_TWR_F1                                     0x000808c2U
#define _reg_PI_TRAS_MAX_F1                                0x081008c2U
#define _reg_PI_TRAS_MIN_F1                                0x180808c2U
#define _reg_PI_TDQSCK_MAX_F1                              0x000408c3U
#define _reg_PI_TCCDMW_F1                                  0x080608c3U
#define _reg_PI_TSR_F1                                     0x100808c3U
#define _reg_PI_TMRD_F1                                    0x180808c3U
#define _reg_PI_TMRW_F1                                    0x000808c4U
#define _reg_PI_TRTP_F2                                    0x080808c4U
#define _reg_PI_TRP_F2                                     0x100808c4U
#define _reg_PI_TRCD_F2                                    0x180808c4U
#define _reg_PI_TWTR_F2                                    0x000608c5U
#define _reg_PI_TWR_F2                                     0x080808c5U
#define _reg_PI_TRAS_MAX_F2                                0x101008c5U
#define _reg_PI_TRAS_MIN_F2                                0x000808c6U
#define _reg_PI_TDQSCK_MAX_F2                              0x080408c6U
#define _reg_PI_TCCDMW_F2                                  0x100608c6U
#define _reg_PI_TSR_F2                                     0x180808c6U
#define _reg_PI_TMRD_F2                                    0x000808c7U
#define _reg_PI_TMRW_F2                                    0x080808c7U
#define _reg_PI_TDFI_CTRLUPD_MAX_F0                        0x001508c8U
#define _reg_PI_TDFI_CTRLUPD_INTERVAL_F0                   0x002008c9U
#define _reg_PI_TDFI_CTRLUPD_MAX_F1                        0x001508caU
#define _reg_PI_TDFI_CTRLUPD_INTERVAL_F1                   0x002008cbU
#define _reg_PI_TDFI_CTRLUPD_MAX_F2                        0x001508ccU
#define _reg_PI_TDFI_CTRLUPD_INTERVAL_F2                   0x002008cdU
#define _reg_PI_TXSR_F0                                    0x001008ceU
#define _reg_PI_TXSR_F1                                    0x101008ceU
#define _reg_PI_TXSR_F2                                    0x001008cfU
#define _reg_PI_WDQ_OSC_DELTA_INDEX_F0                     0x100408cfU
#define _reg_PI_WDQ_OSC_DELTA_INDEX_F1                     0x180408cfU
#define _reg_PI_WDQ_OSC_DELTA_INDEX_F2                     0x000408d0U
#define _reg_PI_MR13_DATA_0                                0x080808d0U
#define _reg_PI_MR40_DATA_0                                0x100808d0U
#define _reg_PI_MR13_DATA_1                                0x180808d0U
#define _reg_PI_MR40_DATA_1                                0x000808d1U
#define _reg_PI_DQS_OSC_BASE_VALUE_0_0                     0x081008d1U
#define _reg_PI_DQS_OSC_BASE_VALUE_0_1                     0x001008d2U
#define _reg_PI_MR1_DATA_F0_0                              0x100808d2U
#define _reg_PI_MR2_DATA_F0_0                              0x180808d2U
#define _reg_PI_MR3_DATA_F0_0                              0x000808d3U
#define _reg_PI_MR11_DATA_F0_0                             0x080808d3U
#define _reg_PI_MR12_DATA_F0_0                             0x100808d3U
#define _reg_PI_MR14_DATA_F0_0                             0x180808d3U
#define _reg_PI_MR22_DATA_F0_0                             0x000808d4U
#define _reg_PI_MR23_DATA_F0_0                             0x080808d4U
#define _reg_PI_MR1_DATA_F1_0                              0x100808d4U
#define _reg_PI_MR2_DATA_F1_0                              0x180808d4U
#define _reg_PI_MR3_DATA_F1_0                              0x000808d5U
#define _reg_PI_MR11_DATA_F1_0                             0x080808d5U
#define _reg_PI_MR12_DATA_F1_0                             0x100808d5U
#define _reg_PI_MR14_DATA_F1_0                             0x180808d5U
#define _reg_PI_MR22_DATA_F1_0                             0x000808d6U
#define _reg_PI_MR23_DATA_F1_0                             0x080808d6U
#define _reg_PI_MR1_DATA_F2_0                              0x100808d6U
#define _reg_PI_MR2_DATA_F2_0                              0x180808d6U
#define _reg_PI_MR3_DATA_F2_0                              0x000808d7U
#define _reg_PI_MR11_DATA_F2_0                             0x080808d7U
#define _reg_PI_MR12_DATA_F2_0                             0x100808d7U
#define _reg_PI_MR14_DATA_F2_0                             0x180808d7U
#define _reg_PI_MR22_DATA_F2_0                             0x000808d8U
#define _reg_PI_MR23_DATA_F2_0                             0x080808d8U
#define _reg_PI_MR1_DATA_F0_1                              0x100808d8U
#define _reg_PI_MR2_DATA_F0_1                              0x180808d8U
#define _reg_PI_MR3_DATA_F0_1                              0x000808d9U
#define _reg_PI_MR11_DATA_F0_1                             0x080808d9U
#define _reg_PI_MR12_DATA_F0_1                             0x100808d9U
#define _reg_PI_MR14_DATA_F0_1                             0x180808d9U
#define _reg_PI_MR22_DATA_F0_1                             0x000808daU
#define _reg_PI_MR23_DATA_F0_1                             0x080808daU
#define _reg_PI_MR1_DATA_F1_1                              0x100808daU
#define _reg_PI_MR2_DATA_F1_1                              0x180808daU
#define _reg_PI_MR3_DATA_F1_1                              0x000808dbU
#define _reg_PI_MR11_DATA_F1_1                             0x080808dbU
#define _reg_PI_MR12_DATA_F1_1                             0x100808dbU
#define _reg_PI_MR14_DATA_F1_1                             0x180808dbU
#define _reg_PI_MR22_DATA_F1_1                             0x000808dcU
#define _reg_PI_MR23_DATA_F1_1                             0x080808dcU
#define _reg_PI_MR1_DATA_F2_1                              0x100808dcU
#define _reg_PI_MR2_DATA_F2_1                              0x180808dcU
#define _reg_PI_MR3_DATA_F2_1                              0x000808ddU
#define _reg_PI_MR11_DATA_F2_1                             0x080808ddU
#define _reg_PI_MR12_DATA_F2_1                             0x100808ddU
#define _reg_PI_MR14_DATA_F2_1                             0x180808ddU
#define _reg_PI_MR22_DATA_F2_1                             0x000808deU
#define _reg_PI_MR23_DATA_F2_1                             0x080808deU
#define _reg_PI_PARITY_ERROR_REGIF                         0x100b08deU

#define DDR_REGDEF_ADR(regdef) ((regdef)&0xffff)
#define DDR_REGDEF_LEN(regdef) (((regdef)>>16)&0xff)
#define DDR_REGDEF_LSB(regdef) (((regdef)>>24)&0xff)

