/*
 * Copyright (c) 2018 Renesas Electronics Corporation. All rights reserved.
 */

#include "common.h"
#include "scifdrv2.h"
#include "bit.h"
#include "reg_rcargen3.h"


//////////////////////////////////////////////////////////////////////////////////
//                                                                              //
//	Debug Seirial(SCIF2)														//
//																				//
//////////////////////////////////////////////////////////////////////////////////
int32_t PutCharSCIF2(char outChar)
{
	while(!(0x60 & *((volatile uint16_t*)SCIF2_SCFSR) ));
	*((volatile unsigned char*)SCIF2_SCFTDR) = outChar;
	*((volatile uint16_t*)SCIF2_SCFSR) &= ~0x60;	/* TEND,TDFE clear */
	return(0);
}

void PowerOnScif2(void)
{
	uint32_t dataL;

	dataL = *((volatile uint32_t*)CPG_MSTPSR3);
	if(dataL & BIT10){	// case SCIF2(IrDA) Standby
		dataL &= ~BIT10;
		*((volatile uint32_t*)CPG_CPGWPR)    = ~dataL;
		*((volatile uint32_t*)CPG_SMSTPCR3)  =  dataL;
		while( BIT10 & *((volatile uint32_t*)CPG_MSTPSR3) );  // wait bit=0
	}
}

void WaitPutScif2SendEnd(void)
{
	uint16_t dataW;
    uint32_t loop;

	loop=1;
    while(loop){
		dataW = *((volatile uint16_t*)SCIF2_SCFSR);
		if(dataW & BIT6)	loop = 0;
	}
}

void InitScif2PinFunction(void)
{
	uint32_t dataL;

	/* SCIF2 */
	dataL = *((volatile uint32_t*)PFC_IPSR13);
	dataL &= ~0x000000FF; /* IP13[7:4]=4'b0000, IP13[3:0]=4'b0000 */
	*((volatile uint32_t*)PFC_PMMR) = ~dataL;
	*((volatile uint32_t*)PFC_IPSR13) = dataL;

	dataL = *((volatile uint32_t*)PFC_GPSR5);
	dataL |= 0x00000C00; /* GP5[11],GP5[10] */
	*((volatile uint32_t*)PFC_PMMR) = ~dataL;
	*((volatile uint32_t*)PFC_GPSR5) = dataL;
}

void InitScif2_SCIFCLK(void)
{
	uint16_t dataW;
	uint32_t prr;

	PowerOnScif2();

	InitScif2PinFunction();

	dataW = *((volatile uint16_t*)SCIF2_SCLSR);	/* dummy read     		*/
	*((volatile uint16_t*)SCIF2_SCLSR) = 0x0000;	/* clear ORER bit 		*/
	*((volatile uint16_t*)SCIF2_SCFSR) = 0x0000;	/* clear all error bit	*/

	*((volatile uint16_t*)SCIF2_SCSCR) = 0x0000;	/* clear SCR.TE & SCR.RE*/
	*((volatile uint16_t*)SCIF2_SCFCR) = 0x0006;	/* reset tx-fifo, reset rx-fifo. */
	*((volatile uint16_t*)SCIF2_SCFSR) = 0x0000;	/* clear ER, TEND, TDFE, BRK, RDF, DR */

	*((volatile uint16_t*)SCIF2_SCSCR) = 0x0000;	/* internal clock, SC_CLK pin used for input pin */
	*((volatile uint16_t*)SCIF2_SCSMR) = 0x0000;	/* 8bit data, no-parity, 1 stop, Po/1 */
	SoftDelay(100);

#ifdef Writer
	*((volatile uint8_t*)SCIF2_SCBRR)  = 0x11;	/* 115200bps@66MHz */
#else  /* Writer */
	prr = *((volatile uint32_t*)PRR);
	prr &= (PRR_PRODUCT_MASK | PRR_CUT_MASK);

	if (prr == PRR_PRODUCT_H3 | PRR_CUT_10) {
		*((volatile uint8_t*)SCIF2_SCBRR)  = 0x08;	/* 115200bps@33MHz */
	} else {
		*((volatile uint8_t*)SCIF2_SCBRR)  = 0x11;	/* 115200bps@66MHz */
	}
#endif /* Writer */

	SoftDelay(100);
	*((volatile uint16_t*)SCIF2_SCFCR) = 0x0000;	/* reset-off tx-fifo, rx-fifo. */
	*((volatile uint16_t*)SCIF2_SCSCR) = 0x0030;	/* enable TE, RE; SC_CLK=input */

	SoftDelay(100);
}

void InitScif2PinFunction_D3(void)
{
	uint32_t dataL;

	/* SCIF2 */
	dataL = *((volatile uint32_t*)PFC_IPSR12);
	dataL &= ~0x00000F00U; /* IP12[11:8]=4'b0000 */
	*((volatile uint32_t*)PFC_PMMR) = ~dataL;
	*((volatile uint32_t*)PFC_IPSR12) = dataL;

	dataL = *((volatile uint32_t*)PFC_GPSR4);
	dataL |= 0x0C000000U; /* GP4[27],GP4[26] */
	*((volatile uint32_t*)PFC_PMMR) = ~dataL;
	*((volatile uint32_t*)PFC_GPSR4) = dataL;

}

void InitScif2_SCIFCLK_D3(void)
{
	uint16_t dataW;
	uint32_t md;
	uint32_t sscg;

	PowerOnScif2();

	InitScif2PinFunction_D3();

	md = *((volatile uint32_t*)RST_MODEMR);
	sscg = (md & 0x00001000) >> 12;

	dataW = *((volatile uint16_t*)SCIF2_SCLSR);	/* dummy read     		*/
	*((volatile uint16_t*)SCIF2_SCLSR) = 0x0000;	/* clear ORER bit 		*/
	*((volatile uint16_t*)SCIF2_SCFSR) = 0x0000;	/* clear all error bit	*/

	*((volatile uint16_t*)SCIF2_SCSCR) = 0x0000;	/* clear SCR.TE & SCR.RE*/
	*((volatile uint16_t*)SCIF2_SCFCR) = 0x0006;	/* reset tx-fifo, reset rx-fifo. */
	*((volatile uint16_t*)SCIF2_SCFSR) = 0x0000;	/* clear ER, TEND, TDFE, BRK, RDF, DR */

	*((volatile uint16_t*)SCIF2_SCSCR) = 0x0000;	/* internal clock, SC_CLK pin used for input pin */
	*((volatile uint16_t*)SCIF2_SCSMR) = 0x0000;	/* 8bit data, no-parity, 1 stop, S3D4/1 */
	SoftDelay(100);

	if(sscg == 0x0){								//MD12=0 (SSCG off) : S3D4C=66.6MHz
		*((volatile uint8_t*)SCIF2_SCBRR)  = 0x11;	/* 115200 bit-rate */
	}
	else if(sscg == 0x1){							//MD12=1 (SSCG on)  : S3D4C=62.5MHz
		*((volatile uint8_t*)SCIF2_SCBRR)  = 0x10;	/* 115200 bit-rate */
	}
	SoftDelay(100);
	*((volatile uint16_t*)SCIF2_SCFCR) = 0x0000;	/* reset-off tx-fifo, rx-fifo. */
	*((volatile uint16_t*)SCIF2_SCSCR) = 0x0030;	/* enable TE, RE; SCK pin is not used */
	SoftDelay(100);
}
