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/*******************************************************************************
 * DESCRIPTION   : Power management driver
 ******************************************************************************/
 /******************************************************************************
 * @file          cpu_on.c
 * - Version      : 0.09
 * @brief         Boot process of ARM CPU core.
 * .
 *****************************************************************************/
/******************************************************************************
 * History : DD.MM.YYYY Version  Description
 *         : 28.07.2021 0.01     First Release
 *         : 03.09.2021 0.02     Modify macro definition name.
 *         : 08.09.2021 0.03     Removed the reset process of BOOT_CTRL and
 *                               OPBT_CTRL register.
 *         : 06.01.2022 0.04     Static analysis support
 *         : 23.05.2022 0.05     Integration of S4 and V4H
 *         : 21.06.2022 0.06     Remove functions for MCU.
 *         : 21.08.2023 0.07     Add support for V4M.
 *         : 17.11.2023 0.08     Move a part of definitions to cpu_on.h.
 *         : 09.12.2024 0.09     Update OTP_MEM_OTPMONITOR60 register to
 *                               OTP_MEM_OTPMONITOR17 register for V4M.
 *                               And Improve the adj_cr_variant_freq function.
 *****************************************************************************/

#include <stdint.h>
#include <types.h>
#include <mem_io.h>
#include <cpu_on.h>
#include <cpg.h>
#include <cpg_register.h>
#include <ap_system_core_register.h>
#include <inline_asm.h>

/* ARM */
#define CA_CORE0_WUP_REQ      (0x00000001U)
#define CA_CORE0_VLD_RVBARP   (0x00000001U)
#define CR_VLD_BARP           (0x00000001U << 0U)
#define CR_BAREN_VALID        (0x00000001U << 4U)
#define CRRST_BIT             (0x00000001U)

#if (RCAR_LSI == RCAR_V4H)
#define V4H_7_NI_CR           (0x53U) /* 1400[MHz] = 50/3[MHz] x (0x53 + 0x1) */
#define V4H_5_NI_CR           (0x41U) /* 1100[MHz] = 50/3[MHz] x (0x41 + 0x1) */
#define V4H_3_NI_CR           (0x35U) /*  900[MHz] = 50/3[MHz] x (0x35 + 0x1) */
#elif (RCAR_LSI == RCAR_V4M)
#define V4M_7_NI_CR           (0x53U) /* 1400[MHz] = 50/3[MHz] x (0x53 + 0x1) */
#define V4M_5_NI_CR           (0x41U) /* 1100[MHz] = 50/3[MHz] x (0x41 + 0x1) */
#define V4M_3_NI_CR           (0x35U) /*  900[MHz] = 50/3[MHz] x (0x35 + 0x1) */
#define V4M_2_NI_CR           (0x35U) /*  900[MHz] = 50/3[MHz] x (0x35 + 0x1) */
# endif /* RCAR_LSI == RCAR_V4H */

#define CPG_PLL6CR0_KICK_BIT  (0x80000000U)
#define CPG_PLLECR_PLL6ST_BIT (0x00008000U)

#define AP_CORE_APSREG_P_CCI500_AUX_ASPRTM          (0x00000001U << 1U)

static void arm_cpu_set_address(uint32_t target, uint32_t boot_addr);

static void arm_cpu_set_address(uint32_t target, uint32_t boot_addr)
{
    if(RCAR_PWR_TARGET_CR == target)
    {
        /* CR Boot address set */
        mem_write32(APMU_CRBARP, (uint32_t)(boot_addr | CR_VLD_BARP));
        mem_write32(APMU_CRBARP, (uint32_t)(boot_addr | CR_VLD_BARP | CR_BAREN_VALID));
    }
    else if(RCAR_PWR_TARGET_CA == target)
    {
        /* CA Boot address set */
        mem_write32(APMU_RVBARPLC0, boot_addr | CA_CORE0_VLD_RVBARP);
        mem_write32(APMU_RVBARPHC0, 0x00000000U);
    }
    else
    {
        /* No Process */
    }
}
/* End of function arm_cpu_set_address(uint32_t target, uint32_t boot_addr) */

void arm_cpu_on(uint32_t target, uint32_t boot_addr)
{
    uint32_t res_data;

    if(RCAR_PWR_TARGET_CR == target)
    {
        /* CR Boot address set. */
        arm_cpu_set_address(target, boot_addr);

        synci();

        /* CR reset. */
        res_data = mem_read32(APMU_CRRSTCTRL);
        res_data &= ~(CRRST_BIT);
        mem_write32(APMU_CRRSTCTRL, res_data);
    }
    else if(RCAR_PWR_TARGET_CA == target)
    {
        /* CA Boot address set. */
        arm_cpu_set_address(target, boot_addr);

        /* AP-System core initialize */
        res_data = mem_read32(ap_core_get_ap_cluster_n_aux0_addr(0U));
        res_data |= AP_CORE_APSREG_AP_CLUSTER_N_AUX0_INIT;
        mem_write32(ap_core_get_ap_cluster_n_aux0_addr(0U), res_data);

        res_data = mem_read32(AP_CORE_APSREG_CCI500_AUX);
        res_data |= AP_CORE_APSREG_CCI500_AUX_ACTDIS;
        mem_write32(AP_CORE_APSREG_CCI500_AUX, res_data);
#if (RCAR_LSI == RCAR_V4H)
        res_data = mem_read32(AP_CORE_APSREG_P_CCI500_AUX);
        res_data |= AP_CORE_APSREG_P_CCI500_AUX_ASPRTM;
        mem_write32(AP_CORE_APSREG_P_CCI500_AUX, res_data);
#endif /* RCAR_LSI == RCAR_V4H */
        synci();

        /* CA core0 wake up sequence. */
        res_data = mem_read32(APMU_PWRCTRLC0);
        res_data |= CA_CORE0_WUP_REQ;
        mem_write32(APMU_PWRCTRLC0, res_data);
        /* Wait until CA core0 wake up sequence finished. */
        do
        {
            res_data = mem_read32(APMU_PWRCTRLC0);
        }while(FALSE != (CA_CORE0_WUP_REQ & res_data));
    }
    else
    {
        /* No Process */
    }
}
/* End of function arm_cpu_on(uint32_t target, uint32_t boot_addr) */


void adj_cr_variant_freq(void)
{
    uint32_t product   = mem_read32(OTP_MEM_OTPMONITOR17) & OTP_MEM_PRODUCT_MASK;
    uint32_t pll6_freq = mem_read32(CPG_PLL6CR0);

#if (RCAR_LSI == RCAR_V4H)
    /* Set the CPU frequency division ratio according to the type of variant. */
    switch (product)
    {
    case VARIANT_V4H_7:
        /* Default value, do nothing */;
        break;
    case VARIANT_V4H_5:
        pll6_freq = (pll6_freq & ~(0xFFU << 20U));
        pll6_freq = (pll6_freq | (V4H_5_NI_CR << 20U));
        break;
    case VARIANT_V4H_3:
        pll6_freq = (pll6_freq & ~(0xFFU << 20U));
        pll6_freq = (pll6_freq | (V4H_3_NI_CR << 20U));
        break;
    default:
        ; /* Do nothing */
        break;
    }

    if (VARIANT_V4H_5 == product || VARIANT_V4H_3 == product)
    {
        /* Write Division value to FRQCRC0 register */
        mem_write32(CPG_CPGWPR,  ~(pll6_freq));
        mem_write32(CPG_PLL6CR0, pll6_freq);

        mem_write32(CPG_CPGWPR, ~(mem_read32(CPG_PLL6CR0) | CPG_PLL6CR0_KICK_BIT));
        mem_write32(CPG_PLL6CR0, (mem_read32(CPG_PLL6CR0) | CPG_PLL6CR0_KICK_BIT));

        while ((mem_read32(CPG_PLLECR) & CPG_PLLECR_PLL6ST_BIT) != CPG_PLLECR_PLL6ST_BIT)
        {
            ;
        }
    }
#elif (RCAR_LSI == RCAR_V4M)
    /* Set the CPU frequency division ratio according to the type of variant. */
    switch (product)
    {
    case VARIANT_V4M_7:
        /* Default value, do nothing */;
        break;
    case VARIANT_V4M_5:
        pll6_freq = (pll6_freq & ~(0xFFU << 20U));
        pll6_freq = (pll6_freq | (V4M_5_NI_CR << 20U));
        break;
    case VARIANT_V4M_3:
        pll6_freq = (pll6_freq & ~(0xFFU << 20U));
        pll6_freq = (pll6_freq | (V4M_3_NI_CR << 20U));
        break;
    case VARIANT_V4M_2:
        pll6_freq = (pll6_freq & ~(0xFFU << 20U));
        pll6_freq = (pll6_freq | (V4M_2_NI_CR << 20U));
        break;
    default:
        ; /* Do nothing */
        break;
    }

    if (VARIANT_V4M_5 == product || VARIANT_V4M_3 == product || VARIANT_V4M_2 == product)
    {
        /* Write Division value to FRQCRC0 register */
        mem_write32(CPG_CPGWPR,  ~(pll6_freq));
        mem_write32(CPG_PLL6CR0, pll6_freq);

        mem_write32(CPG_CPGWPR, ~(mem_read32(CPG_PLL6CR0) | CPG_PLL6CR0_KICK_BIT));
        mem_write32(CPG_PLL6CR0, (mem_read32(CPG_PLL6CR0) | CPG_PLL6CR0_KICK_BIT));

        while ((mem_read32(CPG_PLLECR) & CPG_PLLECR_PLL6ST_BIT) != CPG_PLLECR_PLL6ST_BIT)
        {
            ;
        }
    }
#endif /* RCAR_LSI == RCAR_V4H */
}
/* End of function adj_cpu_variant_freq(void) */
