/*
 * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
 * Copyright (c) 2015-2021, Renesas Electronics Corporation. All rights reserved.
 *
 * SPDX-License-Identifier: BSD-3-Clause
 */

#ifndef RCAR_PWRC_H__
#define RCAR_PWRC_H__

/* RCAR Power controller register offset etc */
#define PPOFFR_OFF      0x0
#define PPONR_OFF       0x4
#define PCOFFR_OFF      0x8
#define PWKUPR_OFF      0xc
#define PSYSR_OFF       0x10

#define PWKUPR_WEN      (1ull << 31)

#define PSYSR_AFF_L2        (1 << 31)
#define PSYSR_AFF_L1        (1 << 30)
#define PSYSR_AFF_L0        (1 << 29)
#define PSYSR_WEN       (1 << 28)
#define PSYSR_PC        (1 << 27)
#define PSYSR_PP        (1 << 26)

#define PSYSR_WK_SHIFT      (24)
#define PSYSR_WK_MASK       (0x3)
#define PSYSR_WK(x)     (((x) >> PSYSR_WK_SHIFT) & PSYSR_WK_MASK)

#define WKUP_COLD       0x0
#define WKUP_RESET      0x1
#define WKUP_PPONR      0x2
#define WKUP_GICREQ     0x3

#define RCAR_INVALID        (0xffffffffU)
#define PSYSR_INVALID       0xffffffff

#ifndef __ASSEMBLY__

/*******************************************************************************
 * Function & variable prototypes
 ******************************************************************************/
void rcar_pwrc_cpuon(uint32_t boot_addr);

#endif /*__ASSEMBLY__*/

#endif /* RCAR_PWRC_H__ */
