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/*******************************************************************************
 * DESCRIPTION   : RT-SRAM register header
 ******************************************************************************/

#ifndef RTSRAM_REGISTER_H_
#define RTSRAM_REGISTER_H_

#include <remap_register.h>

/* AXI base address */
#define RTSRAM_REG__BASE    (BASE_RTSRAM_REG_ADDR)


/* RT-SRAM protection */
#define SECDIV0D    (RTSRAM_REG__BASE + 0x0000U)    /* RT-SRAM protected area division 0 */
#define SECDIV1D    (RTSRAM_REG__BASE + 0x0004U)    /* RT-SRAM protected area division 1 */
#define SECDIV2D    (RTSRAM_REG__BASE + 0x0008U)    /* RT-SRAM protected area division 2 */
#define SECDIV3D    (RTSRAM_REG__BASE + 0x000CU)    /* RT-SRAM protected area division 3 */
#define SECDIV4D    (RTSRAM_REG__BASE + 0x0010U)    /* RT-SRAM protected area division 4 */
#define SECDIV5D    (RTSRAM_REG__BASE + 0x0014U)    /* RT-SRAM protected area division 5 */
#define SECDIV6D    (RTSRAM_REG__BASE + 0x0018U)    /* RT-SRAM protected area division 6 */
#define SECDIV7D    (RTSRAM_REG__BASE + 0x001CU)    /* RT-SRAM protected area division 7 */
#define SECDIV8D    (RTSRAM_REG__BASE + 0x0020U)    /* RT-SRAM protected area division 8 */
#define SECDIV9D    (RTSRAM_REG__BASE + 0x0024U)    /* RT-SRAM protected area division 9 */
#define SECDIV10D   (RTSRAM_REG__BASE + 0x0028U)    /* RT-SRAM protected area division 10 */
#define SECDIV11D   (RTSRAM_REG__BASE + 0x002CU)    /* RT-SRAM protected area division 11 */
#define SECDIV12D   (RTSRAM_REG__BASE + 0x0030U)    /* RT-SRAM protected area division 12 */
#define SECDIV13D   (RTSRAM_REG__BASE + 0x0034U)    /* RT-SRAM protected area division 13 */
#define SECDIV14D   (RTSRAM_REG__BASE + 0x0038U)    /* RT-SRAM protected area division 14 */

#define SECCTR0D    (RTSRAM_REG__BASE + 0x0040U)    /* RT-SRAM protected area setting 0 */
#define SECCTR1D    (RTSRAM_REG__BASE + 0x0044U)    /* RT-SRAM protected area setting 1 */
#define SECCTR2D    (RTSRAM_REG__BASE + 0x0048U)    /* RT-SRAM protected area setting 2 */
#define SECCTR3D    (RTSRAM_REG__BASE + 0x004CU)    /* RT-SRAM protected area setting 3 */
#define SECCTR4D    (RTSRAM_REG__BASE + 0x0050U)    /* RT-SRAM protected area setting 4 */
#define SECCTR5D    (RTSRAM_REG__BASE + 0x0054U)    /* RT-SRAM protected area setting 5 */
#define SECCTR6D    (RTSRAM_REG__BASE + 0x0058U)    /* RT-SRAM protected area setting 6 */
#define SECCTR7D    (RTSRAM_REG__BASE + 0x005CU)    /* RT-SRAM protected area setting 7 */
#define SECCTR8D    (RTSRAM_REG__BASE + 0x0060U)    /* RT-SRAM protected area setting 8 */
#define SECCTR9D    (RTSRAM_REG__BASE + 0x0064U)    /* RT-SRAM protected area setting 9 */
#define SECCTR10D   (RTSRAM_REG__BASE + 0x0068U)    /* RT-SRAM protected area setting 10 */
#define SECCTR11D   (RTSRAM_REG__BASE + 0x006CU)    /* RT-SRAM protected area setting 11 */
#define SECCTR12D   (RTSRAM_REG__BASE + 0x0070U)    /* RT-SRAM protected area setting 12 */
#define SECCTR13D   (RTSRAM_REG__BASE + 0x0074U)    /* RT-SRAM protected area setting 13 */
#define SECCTR14D   (RTSRAM_REG__BASE + 0x0078U)    /* RT-SRAM protected area setting 14 */
#define SECCTR15D   (RTSRAM_REG__BASE + 0x007CU)    /* RT-SRAM protected area setting 15 */

#endif /* RTSRAM_REGISTER_H_ */
