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/*******************************************************************************
 * DESCRIPTION   : rcar register header
 ******************************************************************************/
/******************************************************************************
 * @file          rcar_register.h
 * - Version      : 0.07
 * @brief         
 * .
 *****************************************************************************/
/******************************************************************************
 * History : DD.MM.YYYY Version  Description
 *         : 02.02.2022 0.01     First Release
 *         : 17.02.2022 0.02     Add APMU
 *                               Support AArch32
 *         : 09.05.2022 0.03     Changed to processing for each device
 *         : 24.10.2022 0.04     Add supports for HS200/400
 *         : 31.10.2022 0.05     License notation change.
 *         : 07.11.2022 0.06     Added QOS and RTVRAM related registers.
 *         : 21.08.2023 0.07     Add support for V4M.
 *****************************************************************************/

#ifndef RCAR_REGISTER_H_
#define RCAR_REGISTER_H_

#include <stdint.h>

#define BASE_ADDR_PFC           (0xE6000000U)   /* PFC,GPIO,LIFC,CPGA,RESET */
#define BASE_ADDR_RPC           (0xEE200000U)   /* RPC */
#if (RCAR_LSI == RCAR_S4)
#define BASE_ADDR_SCIF          (0xE6C00000U)   /* SCIF */
#elif ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M))
#define BASE_ADDR_SCIF          (0xE6E00000U)   /* SCIF */
#endif /* RCAR_LSI == RCAR_S4 */
#define BASE_ADDR_MMC           (0xEE000000U)   /* MMC */
#define BASE_ADDR_HSCIF         (0xE6400000U)   /* HSCIF */
#define BASE_AP_CORE_ADDR       (0xE6280000U)   /* ECM */

/* Base address offset of each register */
/* CPGA */
#define OFFSET_CPGA             (0x00150000U)
/* RESET */
#define OFFSET_RESET            (0x00160000U)
/* APMU */
#define OFFSET_APMU             (0x00170000U)

/*RPC*/
#define OFFSET_RPC              (0x00000000U)

/*SCIF*/
#if (RCAR_LSI == RCAR_S4)
#define OFFSET_SCIF3            (0x00050000U)
#elif ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M))
#define OFFSET_SCIF0            (0x00060000U)
#endif /* RCAR_LSI == RCAR_S4 */

/* SDHI2/MMC0 */
#define OFFSET_SDHI             (0x00140000U)

/* HSCIF */
#define OFFSET_HSCIF0           (0x00140000U)

/* PFC0 */
#define OFFSET_PFC0             (0x00050000U)

/* PFC1 */
#if (RCAR_LSI == RCAR_S4)
#define OFFSET_PFC1             (0x00051000U)
#elif ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M))
#define OFFSET_PFC1             (0x00058000U)
#endif /* RCAR_LSI == RCAR_S4 */

/* Port Group */
#define OFFSET_PORTGR           (0x00000800U)

/* CPGWPR */
#define OFFSET_CPG_CPGWPR   	(0x00000000U)

/* SD0CKCR */
#define OFFSET_CPG_SD0CKCR      (0x00000870U)

/* PLL2CR0 */
#define OFFSET_CPG_PLL2CR0      (0x00000834U)

/* PLLECR */
#define OFFSET_CPG_PLLECR       (0x00000820U)

/* QOS */
#define ICU_CC                  (0xE6600000U)   /* CC63S,I2C,AXMM,QoS */
#define ICU_OFFSET_CCI          (0x001a0000U)   /* (0xE67A0000U) */
#define BASE_CCI_ADDR           (ICU_CC + ICU_OFFSET_CCI)

/* RTVRAM */
#define SDRAM_40BIT_ADDR_TOP    (0x0400000000ULL)
#define RTVRAM_VBUF_AREA_SIZE   (4U * 1024U * 1024U)    /* 4MB */

#define BASE_CPG_ADDR           (BASE_ADDR_PFC + OFFSET_CPGA)
#define BASE_RESET_ADDR         (BASE_ADDR_PFC + OFFSET_RESET)
#define BASE_APMU_ADDR          (BASE_ADDR_PFC + OFFSET_APMU)
#define BASE_RPC_ADDR           (BASE_ADDR_RPC + OFFSET_RPC)
#if (RCAR_LSI == RCAR_S4)
#define BASE_SCIF_ADDR          (BASE_ADDR_SCIF + OFFSET_SCIF3)
#elif ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M))
#define BASE_SCIF_ADDR          (BASE_ADDR_SCIF + OFFSET_SCIF0)
#endif /* RCAR_LSI == RCAR_S4 */
#define BASE_MMC0_ADDR          (BASE_ADDR_MMC + OFFSET_SDHI)
#define BASE_HSCIF_ADDR         (BASE_ADDR_HSCIF + OFFSET_HSCIF0)
#define BASE_PFC0_ADDR          (BASE_ADDR_PFC + OFFSET_PFC0)
#define BASE_PFC1_ADDR          (BASE_ADDR_PFC + OFFSET_PFC1)
#define BASE_CPG_ADDR           (BASE_ADDR_PFC + OFFSET_CPGA)
#define PFC_GP1_BASE			(BASE_PFC0_ADDR + OFFSET_PORTGR)
#define PFC_GP3_BASE			(BASE_PFC1_ADDR + OFFSET_PORTGR)
#define CPG_CPGWPR				(BASE_CPG_ADDR + OFFSET_CPG_CPGWPR)
#define CPG_PLL2CR0				(BASE_CPG_ADDR + OFFSET_CPG_PLL2CR0)
#define CPG_PLLECR              (BASE_CPG_ADDR + OFFSET_CPG_PLLECR)
#define CPG_SD0CKCR				(BASE_CPG_ADDR + OFFSET_CPG_SD0CKCR)
#define CPG_FRQCRC0             (BASE_CPG_ADDR  + OFFSET_CPG_FRQCRC0 0x0808U)

#define OFFSET_PFC_DRV0CTRL		(0x00000080U)
#define OFFSET_PFC_DRV1CTRL     (0x00000084U)
#define OFFSET_PFC_DRV2CTRL     (0x00000088U)

#if (RCAR_LSI == RCAR_S4)
#define	PFC_DRVCTRL1_GP1_DM0	(PFC_GP1_BASE + OFFSET_PFC_DRV1CTRL)	// R/W	32	POC control register0 PortGroup 3
#define	PFC_DRVCTRL2_GP1_DM0	(PFC_GP1_BASE + OFFSET_PFC_DRV2CTRL)	// R/W	32	POC control register1 PortGroup 3
#elif ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M))
#define	PFC_DRVCTRL0_GP3_DM0	(PFC_GP3_BASE + OFFSET_PFC_DRV0CTRL)	// R/W	32	POC control register0 PortGroup 3
#define	PFC_DRVCTRL1_GP3_DM0	(PFC_GP3_BASE + OFFSET_PFC_DRV1CTRL)	// R/W	32	POC control register1 PortGroup 3
#endif /* RCAR_LSI == RCAR_S4 */

#define	PFC_PMMR(addr)			((addr) & (uintptr_t)0xFFFFF800U)	// R/W	32	LSI Multiplexed Pin Setting Mask Register

#endif /* RCAR_REGISTER_H_ */
