/*******************************************************************************
 * Copyright (c) 2018-2021 Renesas Electronics Corporation. All rights reserved.
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 *
 * This software is provided as reference/sample code under the license
 * agreement between Renesas Electronics Corporation and licensee (the
 * "License Agreement") and shall be treated as specified in the License
 * Agreement.
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/*******************************************************************************
 * DESCRIPTION   : SYSC register header
 ******************************************************************************/

#ifndef SYSC_REGISTER_H_
#define SYSC_REGISTER_H_

#include "mem_io.h"
#include "remap_register.h"

#define SYSC_BASE   (BASE_SYSC_ADDR)    /* (0xE6180000U) */

#define SYSC_PWRSR3     (SYSC_BASE + 0x0140U)   /* Power status register CA53-SCU       */
#define SYSC_PWRSR7     (SYSC_BASE + 0x0240U)   /* Power status register 7 (CR7)        */
#define SYSC_SYSCIER    (SYSC_BASE + 0x000CU)   /* Interrupt enable register            */
#define SYSC_SYSCIMR    (SYSC_BASE + 0x0010U)   /* Interrupt mask register          */
#define SYSC_SYSCSR     (SYSC_BASE + 0x0000U)   /* SYSC status register             */
#define SYSC_PWRONCR3   (SYSC_BASE + 0x014CU)   /* Power resume control register CA53-SCU   */
#define SYSC_PWRONCR7   (SYSC_BASE + 0x024CU)   /* Power resume control register 7 (CR7)    */
#define SYSC_PWRER3     (SYSC_BASE + 0x0154U)   /* Power shutoff/resume error register CA53-SCU */
#define SYSC_PWRER7     (SYSC_BASE + 0x0254U)   /* Power shutoff/resume error register 7 (CR7)  */
#define SYSC_SYSCISR    (SYSC_BASE + 0x0004U)   /* Interrupt status register            */
#define SYSC_SYSCISCR   (SYSC_BASE + 0x0008U)   /* Interrupt status clear register      */
#define SYSC_WUPMSKCA53 (SYSC_BASE + 0x0018U)   /* Wake-up mask register for A53        */

#endif /* SYSC_REGISTER_H_ */
