/*
 * Copyright (c) 2015-2021, Renesas Electronics Corporation
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions are met:
 *
 *   - Redistributions of source code must retain the above copyright notice,
 *     this list of conditions and the following disclaimer.
 *
 *   - Redistributions in binary form must reproduce the above copyright
 *     notice, this list of conditions and the following disclaimer in the
 *     documentation and/or other materials provided with the distribution.
 *
 *   - Neither the name of Renesas nor the names of its contributors may be
 *     used to endorse or promote products derived from this software without
 *     specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
 * POSSIBILITY OF SUCH DAMAGE.
 */

//
//*******************************************************************************//
//      Program name : V3M DDR initial sequence                                  //
//*******************************************************************************//
// Rev  Date       Content
// 0.1 2017.06.08 Start revision control
//                  (ref. R-CarGen3_V3Mddr_init_seq_rev0.1.docx)
// 0.2 2017.09.29 Add Initial Sequence
//                            init_ddr_v3m1583, init_ddr_v3m1316
//                Add Pll3 Freq Change Sequence
//                            pll3_freq_change_bypmode_1316, pll3_freq_change_bypmode_1583
// 0.3 2018.07.27 Modify Initial Sequence based on UM 0.81
// 0.4 2018.10.19 Add additinal Workaround for DRAM limitation
// 0.5 2018.10.23 Correct syntax warning strictly (add parentheses at 6 sentences of same contents)
//                  from: WriteReg_32(DBSC_V3M_DBPDRGD0, (RegVal_R6 - RegVal_R12) & 0X000000FF | RegVal_R2);
//                  to:   WriteReg_32(DBSC_V3M_DBPDRGD0, ((RegVal_R6 - RegVal_R12) & 0X000000FF) | RegVal_R2);
// 0.6 2019.06.19 Change the default of following registers by changing refresh rate (tREFI) from 7.8us to 3.9us.
//                  DBPDRGD0(DBPDRGA0=0x00000004), DBPDRGD0(DBPDRGA0=0x00000029), DBCALCNF, DBRFCNF1
//                Modified original 7.8us setting (which is comment out)as follows,
//                  init_ddr_v3m1600 : DBCALCNF : 0x0100200E => 0x0100200D
//                  init_ddr_v3m1333 : DBCALCNF : 0x0100200E => 0x0100200D
//                  init_ddr_v3m1333 : DBRFCNF1 : 0x00081450 => 0x0008144F
//                  init_ddr_v3m1316 : DBRFCNF1 : 0x0008140F => 0x0008140E
//                  init_ddr_v3m1316(memory size(device density): less than 8Gb) : DBPDRGD0(DBPDRGA0=0x00000004) : 0x07309EE8 => 0x07309EE7
//                  init_ddr_v3m1583(memory size(device density): 8Gb) : DBPDRGD0(DBPDRGA0=0x00000004) : 0x08A0BF67 => 0x08B0BF67
//                  init_ddr_v3m1580(memory size(device density): 8Gb) : DBPDRGD0(DBPDRGA0=0x00000004) : 0x08A0BF00 => 0x08B0BF00
//                  init_ddr_v3m1320(memory size(device density): 8Gb) : DBPDRGD0(DBPDRGA0=0x00000004) : 0x07309F50 => 0x07409F50
//                  init_ddr_v3m1316(memory size(device density): 8Gb) : DBPDRGD0(DBPDRGA0=0x00000004) : 0x07309EE7 => 0x07409EE7
// 0.7 2021.07.05 Add refresh rate (tREFI) 1.95us.
// 0.8 2021.07.05 Add the compiler option "V3MSK_2GB" for the R-car V3M starter kit.
//*******************************************************************************//

#include <stdint.h>
//#include "mmio_v3m.h"
#include "boot_init_dram_regdef_v3m.h"

#define RCAR_REF_DEFAULT    (0U)
#define RCAR_REF_7800       (1U)
#define RCAR_REF_1950       (2U)

static void WriteReg_32(uint32_t a, uint32_t v)
{
    (*(volatile uint32_t*)a) = v;
}

static uint32_t ReadReg_32(uint32_t a)
{
    uint32_t w = (*(volatile uint32_t*)a);
    return w;
}

uint32_t init_ddr_v3m1600(void)
{
    // modified last, 2018.10.11
    uint32_t RegVal_R2, RegVal_R5, RegVal_R6, RegVal_R7, RegVal_R12, i;

    uint32_t RegVal,j;
    uint32_t dqsgd_0c, bdlcount_0c, bdlcount_0c_div2, bdlcount_0c_div4, bdlcount_0c_div8, bdlcount_0c_div16;
    uint32_t gatesl_0c, rdqsd_0c, rdqsnd_0c, rbd_0c[4];

/* Initial setting ===============================================*/
    WriteReg_32(DBSC_V3M_DBSYSCNT0,0x00001234);
    WriteReg_32(DBSC_V3M_DBKIND,0x00000007);
#if V3MSK_2GB == 0
    WriteReg_32(DBSC_V3M_DBMEMCONF00,0x0f030a02);//Eagle board
#else
    WriteReg_32(DBSC_V3M_DBMEMCONF00,0x10030a02);//V3MSK board
#endif
    WriteReg_32(DBSC_V3M_DBPHYCONF0,0x00000001);
    WriteReg_32(DBSC_V3M_DBTR0,0x0000000B);
    WriteReg_32(DBSC_V3M_DBTR1,0x00000008);
    WriteReg_32(DBSC_V3M_DBTR2,0x00000000);
    WriteReg_32(DBSC_V3M_DBTR3,0x0000000B);
    WriteReg_32(DBSC_V3M_DBTR4,0x000B000B);
    WriteReg_32(DBSC_V3M_DBTR5,0x00000027);
    WriteReg_32(DBSC_V3M_DBTR6,0x0000001C);
    WriteReg_32(DBSC_V3M_DBTR7,0x00060006);
    WriteReg_32(DBSC_V3M_DBTR8,0x00000020);
    WriteReg_32(DBSC_V3M_DBTR9,0x00000006);
    WriteReg_32(DBSC_V3M_DBTR10,0x0000000C);
    WriteReg_32(DBSC_V3M_DBTR11,0x0000000A); //0x0000000B -> 0x0000000A
    WriteReg_32(DBSC_V3M_DBTR12,0x00120012);
#if V3MSK_2GB == 0
    WriteReg_32(DBSC_V3M_DBTR13,0x000000D0);//Eagle board
#else
    WriteReg_32(DBSC_V3M_DBTR13,0x00000118);//V3MSK board
#endif
    WriteReg_32(DBSC_V3M_DBTR14,0x00140005);
    WriteReg_32(DBSC_V3M_DBTR15,0x00050004);
    WriteReg_32(DBSC_V3M_DBTR16,0x071F0305);
    WriteReg_32(DBSC_V3M_DBTR17,0x040C0000);
    WriteReg_32(DBSC_V3M_DBTR18,0x00000200);
    WriteReg_32(DBSC_V3M_DBTR19,0x01000040);
#if V3MSK_2GB == 0
    WriteReg_32(DBSC_V3M_DBTR20,0x020000D8);//Eagle board
#else
    WriteReg_32(DBSC_V3M_DBTR20,0x02000120);//V3MSK board
#endif
    WriteReg_32(DBSC_V3M_DBTR21,0x00040004);
    WriteReg_32(DBSC_V3M_DBBL,0x00000000);
    WriteReg_32(DBSC_V3M_DBODT0,0x00000001);
    WriteReg_32(DBSC_V3M_DBADJ0,0x00000001);
    WriteReg_32(DBSC_V3M_DBSYSCONF1,0x00000002);
    WriteReg_32(DBSC_V3M_DBDFICNT0,0x00000010);
    WriteReg_32(DBSC_V3M_DBBCAMDIS,0x00000001);
#if V3MSK_2GB == 0
    WriteReg_32(DBSC_V3M_DBSCHRW1,0x00000046);//Eagle board
#else
    WriteReg_32(DBSC_V3M_DBSCHRW1,0x0000005E);//V3MSK board
#endif
    WriteReg_32(DBSC_V3M_SCFCTST0,0x0D050B03); //0x0D060C04 -> 0x0D050B03
    WriteReg_32(DBSC_V3M_SCFCTST1,0x0306030C); //0x0406040C -> 0x0306030C

    WriteReg_32(DBSC_V3M_DBPDLK0,0X0000A55A);
    WriteReg_32(DBSC_V3M_DBCMD,0x01000001);
    WriteReg_32(DBSC_V3M_DBCMD,0x08000000);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000001);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X80010000);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000006);
    while ( (BIT0 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 );

    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000008);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X000B8000);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000090);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X04058904);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000091);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X0007BB6D);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000095);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X0007BB6B);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000099);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X0007BB6D);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000090);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X04058900);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000021);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X0024641E);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000001);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X00010073);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000006);
    while ( (BIT0 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 );

    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000090);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X0C058900);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000090);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X04058900);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000006);
    while ( (BIT0 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 );

    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000003);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X0780C720); //0x0780C700 -> 0x0780C720
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000007);
    while ( (BIT30& ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 );

    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000004);
#if (RCAR_REF_INT == RCAR_REF_DEFAULT)	//REF 3.9usec
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X08C05FF0); //tREFI=3.9us
#elif (RCAR_REF_INT == RCAR_REF_7800)
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X08C0C170); //tREFI=7.8us
#elif (RCAR_REF_INT == RCAR_REF_1950)
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X08C02BAC); //tREFI=1.95us
#else
    #error "Don't set out of range of RCAR_REF_INT."
#endif
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000022);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X1000040B);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000023);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X2D9C0B66);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000024);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X2A88C400);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000025);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X30005200);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000026);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X0014A9C9);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000027);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X00000D70);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000028);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X00000004);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000029);
#if (RCAR_REF_INT == RCAR_REF_DEFAULT)	//REF 3.9usec
	WriteReg_32(DBSC_V3M_DBPDRGD0,0X00000098); //tREFI=3.9us
#elif (RCAR_REF_INT == RCAR_REF_7800)
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X00000018); //tREFI=7.8us
#elif (RCAR_REF_INT == RCAR_REF_1950)
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X00000098); //tREFI=1.95us
#else
    #error "Don't set out of range of RCAR_REF_INT."
#endif
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X0000002C);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X81003047);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000020);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X00181884);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X0000001A);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X33C03C10);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000006);
    while ( (BIT0 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 );

    WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000A7);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X0D0D0D0D);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000A8);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X0D0D0D0D);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000A9);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X000D0D0D);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000C7);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X0D0D0D0D);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000C8);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X0D0D0D0D);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000C9);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X000D0D0D);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000E7);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X0D0D0D0D);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000E8);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X0D0D0D0D);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000E9);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X000D0D0D);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000107);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X0D0D0D0D);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000108);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X0D0D0D0D);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000109);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X000D0D0D);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000001);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X00010181);
    WriteReg_32(DBSC_V3M_DBCMD,0x08000001);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000006);
    while ( (BIT0 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 );

    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000001);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X00010601);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000006);
    while ( (BIT0 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 );

    for (i=0;i<4;i++)
    {
        WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B1 + i*0x20);
        RegVal_R5 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0x0000FF00 ) >> 8;
        WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B4 + i*0x20);
        RegVal_R6 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0x000000FF ) ;
        WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B3 + i*0x20);
        RegVal_R7 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0x00000007 ) ;
        if ( RegVal_R6 > 0 )
        {
            WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B2 + i*0x20);
            RegVal_R2 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0XFFFFFFF8 ) ;

            WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B2 + i*0x20);
            WriteReg_32(DBSC_V3M_DBPDRGD0,((RegVal_R7+1)&0X00000007) | RegVal_R2);
            WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B0 + i*0x20);
            RegVal_R2 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0XFFFFFF00 ) ;
            WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B0 + i*0x20);
            WriteReg_32(DBSC_V3M_DBPDRGD0,RegVal_R2 | RegVal_R6);
        } else
        {
            WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B2 + i*0x20);
            RegVal_R2 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0XFFFFFFF8 ) ;
            WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B2 + i*0x20);
            WriteReg_32(DBSC_V3M_DBPDRGD0,RegVal_R2 | RegVal_R7);

            WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B0 + i*0x20);
            RegVal_R2 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0XFFFFFF00 ) ;
            WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B0 + i*0x20);
            WriteReg_32(DBSC_V3M_DBPDRGD0,(((RegVal_R5<<1) + RegVal_R6 ) & 0X000000FF )| RegVal_R2);
        }
    }

    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000005);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0XC1AA00C0);
//    WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000A0);
//    WriteReg_32(DBSC_V3M_DBPDRGD0,0X7C0002C5);
//    WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000C0);
//    WriteReg_32(DBSC_V3M_DBPDRGD0,0X7C0002C5);
//    WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000E0);
//    WriteReg_32(DBSC_V3M_DBPDRGD0,0X7C0002C5);
//    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000100);
//    WriteReg_32(DBSC_V3M_DBPDRGD0,0X7C0002C5);

// PDR always off        add 2018/10/11
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000A3);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000008);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000C3);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000008);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000E3);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000008);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000103);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000008);

    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000001);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X00010801);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000006);
    while ( (BIT0 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 );

    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000005);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0XC1AA00D8);
//    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000001);
//    WriteReg_32(DBSC_V3M_DBPDRGD0,0X0001F001);
//    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000006);
//    while ( (BIT0 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 );

    WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000001);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x00011001);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000006);
    while ( (BIT0 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 );

    WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000A0);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x7C0002C5);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000C0);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x7C0002C5);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000E0);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x7C0002C5);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000100);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x7C0002C5);

// PDR default(dynamic)  add 2018/10/11
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000A3);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000000);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000C3);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000000);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000E3);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000000);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000103);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000000);

    WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000001);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x00012001);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000006);
    while ( (BIT0 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 );

    WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000A0);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x7C000285);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000C0);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x7C000285);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000E0);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x7C000285);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000100);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x7C000285);

// PDR always off        add 2018/10/11
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000A3);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000008);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000C3);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000008);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000E3);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000008);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000103);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000008);

    WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000001);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x00014001);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000006);
    while ( (BIT0 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 );

    WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000A0);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x7C0002C5);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000C0);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x7C0002C5);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000E0);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x7C0002C5);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000100);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x7C0002C5);

// PDR default(dynamic)  add 2018/10/11
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000A3);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000000);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000C3);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000000);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000E3);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000000);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000103);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000000);

    WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000001);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x00018001);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000006);
    while ( (BIT0 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 );

    WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000A0);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X7C000285);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000C0);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X7C000285);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000E0);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X7C000285);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000100);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X7C000285);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X0000002C);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X81003087);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000001);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X00010401);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000006);
    while ( (BIT0 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 );

    for (i=0;i<4;i++)
    {
        WriteReg_32(DBSC_V3M_DBPDRGA0, 0X000000B1 + i * 0x20);
        RegVal_R5 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0x0000FF00) >> 8;
        WriteReg_32(DBSC_V3M_DBPDRGA0, 0X000000B4 + i * 0x20);
        RegVal_R6 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0x000000FF);

        WriteReg_32(DBSC_V3M_DBPDRGA0, 0X000000B3 + i * 0x20);
        RegVal_R7 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0x00000007);
        RegVal_R12 = (RegVal_R5 >> 2);
        if (RegVal_R6 - RegVal_R12 > 0)
        {
            WriteReg_32(DBSC_V3M_DBPDRGA0, 0X000000B2 + i * 0x20);
            RegVal_R2 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0XFFFFFFF8);

            WriteReg_32(DBSC_V3M_DBPDRGA0, 0X000000B2 + i * 0x20);
            WriteReg_32(DBSC_V3M_DBPDRGD0, ((RegVal_R7 + 1) & 0X00000007) | RegVal_R2);
            WriteReg_32(DBSC_V3M_DBPDRGA0, 0X000000B0 + i * 0x20);
            RegVal_R2 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0XFFFFFF00);

            WriteReg_32(DBSC_V3M_DBPDRGA0, 0X000000B0 + i * 0x20);
            WriteReg_32(DBSC_V3M_DBPDRGD0, ((RegVal_R6 - RegVal_R12) & 0X000000FF) | RegVal_R2);
        }
        else
        {
            WriteReg_32(DBSC_V3M_DBPDRGA0, 0X000000B2 + i * 0x20);
            RegVal_R2 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0XFFFFFFF8);
            WriteReg_32(DBSC_V3M_DBPDRGA0, 0X000000B2 + i * 0x20);
            WriteReg_32(DBSC_V3M_DBPDRGD0, (RegVal_R7 & 0X00000007) | RegVal_R2);
            WriteReg_32(DBSC_V3M_DBPDRGA0, 0X000000B0 + i * 0x20);
            RegVal_R2 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0XFFFFFF00);
            WriteReg_32(DBSC_V3M_DBPDRGA0, 0X000000B0 + i * 0x20);
            WriteReg_32(DBSC_V3M_DBPDRGD0, ((RegVal_R6 + RegVal_R5 + (RegVal_R5 >> 1) + RegVal_R12) & 0X000000FF) | RegVal_R2);
        }
    }

//    WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000A0);
//    WriteReg_32(DBSC_V3M_DBPDRGD0,0X7C0002C5);
//    WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000C0);
//    WriteReg_32(DBSC_V3M_DBPDRGD0,0X7C0002C5);
//    WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000E0);
//    WriteReg_32(DBSC_V3M_DBPDRGD0,0X7C0002C5);
//    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000100);
//    WriteReg_32(DBSC_V3M_DBPDRGD0,0X7C0002C5);

// PDR always off        add 2018/10/11
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000A3);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000008);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000C3);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000008);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000E3);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000008);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000103);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000008);

    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000001);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X00015001);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000006);
    while ( (BIT0 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 );

    for (i=0; i< 4; i++) {
        WriteReg_32(DBSC_V3M_DBPDRGA0, 0x000000B0 + i * 0x20);
        dqsgd_0c = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0x000000FF);

        WriteReg_32(DBSC_V3M_DBPDRGA0, 0x000000B1 + i * 0x20);
        bdlcount_0c = ((ReadReg_32(DBSC_V3M_DBPDRGD0) & 0x0000FF00) >> 8);

        bdlcount_0c_div2  = (bdlcount_0c >> 1);
        bdlcount_0c_div4  = (bdlcount_0c >> 2);
        bdlcount_0c_div8  = (bdlcount_0c >> 3);
        bdlcount_0c_div16 = (bdlcount_0c >> 4);

        if (dqsgd_0c > bdlcount_0c_div2 + bdlcount_0c_div4 + bdlcount_0c_div8) {
            if (dqsgd_0c <= bdlcount_0c + bdlcount_0c_div4 + bdlcount_0c_div16) {
                WriteReg_32(DBSC_V3M_DBPDRGA0, 0x000000B0 + i * 0x20);
                RegVal = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0xFFFFFF00);
                WriteReg_32(DBSC_V3M_DBPDRGD0,((dqsgd_0c - bdlcount_0c_div8) | RegVal));
            } else {
                WriteReg_32(DBSC_V3M_DBPDRGA0, 0x000000B0 + i * 0x20);
                RegVal = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0xFFFFFF00);
                WriteReg_32(DBSC_V3M_DBPDRGD0, RegVal);
                WriteReg_32(DBSC_V3M_DBPDRGA0, 0x000000B2 + i * 0x20);
                gatesl_0c = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0x00000007);
                WriteReg_32(DBSC_V3M_DBPDRGA0, 0x000000B2 + i * 0x20);
                RegVal = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0xFFFFFFF8);
                WriteReg_32(DBSC_V3M_DBPDRGD0, (RegVal|(gatesl_0c + 1)));
                WriteReg_32(DBSC_V3M_DBPDRGA0, 0x000000AF + i * 0x20);
                RegVal = (ReadReg_32(DBSC_V3M_DBPDRGD0));
                rdqsd_0c = (RegVal & 0x0000FF00) >> 8;
                rdqsnd_0c = (RegVal & 0x00FF0000) >> 16;
                WriteReg_32(DBSC_V3M_DBPDRGA0, 0x000000AF + i * 0x20);
                WriteReg_32(DBSC_V3M_DBPDRGD0, ((RegVal & 0xFF0000FF)|((rdqsd_0c + bdlcount_0c_div4) << 8)|((rdqsnd_0c + bdlcount_0c_div4) << 16)));
                WriteReg_32(DBSC_V3M_DBPDRGA0, 0x000000AA + i * 0x20);
                RegVal = (ReadReg_32(DBSC_V3M_DBPDRGD0));
                rbd_0c[0] = (RegVal      ) & 0x0000001f;
                rbd_0c[1] = (RegVal >>  8) & 0x0000001f;
                rbd_0c[2] = (RegVal >> 16) & 0x0000001f;
                rbd_0c[3] = (RegVal >> 24) & 0x0000001f;

                WriteReg_32(DBSC_V3M_DBPDRGA0, 0x000000AA + i * 0x20);
                RegVal = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0xE0E0E0E0);
                for (j=0; j< 4; j++) {
                    rbd_0c[j] = (rbd_0c[j] + bdlcount_0c_div4);
                    if (rbd_0c[j] > 0x1F) rbd_0c[j] = 0x1F;
                    RegVal = RegVal | (rbd_0c[j] <<8*j);
                }
                WriteReg_32(DBSC_V3M_DBPDRGD0, RegVal);
                WriteReg_32(DBSC_V3M_DBPDRGA0, 0x000000AB + i * 0x20);
                RegVal = (ReadReg_32(DBSC_V3M_DBPDRGD0));
                rbd_0c[0] = (RegVal      ) & 0x0000001f;
                rbd_0c[1] = (RegVal >>  8) & 0x0000001f;
                rbd_0c[2] = (RegVal >> 16) & 0x0000001f;
                rbd_0c[3] = (RegVal >> 24) & 0x0000001f;

                WriteReg_32(DBSC_V3M_DBPDRGA0, 0x000000AB + i * 0x20);
                RegVal = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0xE0E0E0E0);
                for (j=0; j< 4; j++) {
                    rbd_0c[j] = (rbd_0c[j] + bdlcount_0c_div4);
                    if (rbd_0c[j] > 0x1F) rbd_0c[j] = 0x1F;
                    RegVal = RegVal | (rbd_0c[j] <<8*j);
                }
                WriteReg_32(DBSC_V3M_DBPDRGD0, RegVal);
            }
        }
    }
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000002);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x07D81E37);

    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000003);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X0380C720); //0x0380C700 -> 0x0380C720
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000007);
    while ( (BIT30& ReadReg_32(DBSC_V3M_DBPDRGD0)) != 0 );

    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000021);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X0024643E);

    WriteReg_32(DBSC_V3M_DBBUS0CNF1,0x00000000);
#if (RCAR_REF_INT == RCAR_REF_DEFAULT)	//REF 3.9usec
    WriteReg_32(DBSC_V3M_DBCALCNF,0x0100401A); //tREFI=3.9us
    WriteReg_32(DBSC_V3M_DBRFCNF1,0x00080C30); //tREFI=3.9us
    WriteReg_32(DBSC_V3M_DBRFCNF2,0x00010000); //tREFI=3.9us
#elif (RCAR_REF_INT == RCAR_REF_7800)
    WriteReg_32(DBSC_V3M_DBCALCNF,0x0100200D); //tREFI=7.8us, 0x0100200E => 0x0100200D
    WriteReg_32(DBSC_V3M_DBRFCNF1,0x00081860); //tREFI=7.8us
    WriteReg_32(DBSC_V3M_DBRFCNF2,0x00010000); //tREFI=7.8us
#elif (RCAR_REF_INT == RCAR_REF_1950)
    WriteReg_32(DBSC_V3M_DBCALCNF,0x0100401A); //tREFI=1.95us
    WriteReg_32(DBSC_V3M_DBRFCNF1,0x00080C30); //tREFI=1.95us
    WriteReg_32(DBSC_V3M_DBRFCNF2,0x00010001); //tREFI=1.95us
#else
    #error "Don't set out of range of RCAR_REF_INT."
#endif
    WriteReg_32(DBSC_V3M_DBDFICUPDCNF,0x40100001);
    WriteReg_32(DBSC_V3M_DBRFEN,0x00000001);
    WriteReg_32(DBSC_V3M_DBACEN,0x00000001);

    WriteReg_32(0xE67F0018,0x00000001);
    RegVal = ReadReg_32(0x40000000);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000000);
    WriteReg_32(DBSC_V3M_DBPDRGD0,RegVal);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000A0);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x7C0002C5);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000C0);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x7C0002C5);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000E0);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x7C0002C5);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000100);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x7C0002C5);

// PDR default(dynamic)  add 2018/10/11
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000A3);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000000);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000C3);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000000);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000E3);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000000);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000103);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000000);

    WriteReg_32(DBSC_V3M_DBPDLK0,0X00000000);
    WriteReg_32(DBSC_V3M_DBSYSCNT0,0x00000000);

#ifdef ddr_qos_init_setting // only for non qos_init:add 2018.01.25
    WriteReg_32(DBSC_V3M_DBSYSCNT0,0x00001234);
    WriteReg_32(DBSC_V3M_DBCAM0CNF1,0x00043218);
    WriteReg_32(DBSC_V3M_DBCAM0CNF2,0x000000F4);
    WriteReg_32(DBSC_V3M_DBSCHCNT0,0x000f0037);
    WriteReg_32(DBSC_V3M_DBSCHSZ0,0x00000001);
    WriteReg_32(DBSC_V3M_DBSCHRW0,0x22421111);
    WriteReg_32(DBSC_V3M_SCFCTST2,0x012F1123);
    WriteReg_32(DBSC_V3M_DBSCHQOS00,0x00000F00);
    WriteReg_32(DBSC_V3M_DBSCHQOS01,0x00000B00);
    WriteReg_32(DBSC_V3M_DBSCHQOS02,0x00000000);
    WriteReg_32(DBSC_V3M_DBSCHQOS03,0x00000000);
    WriteReg_32(DBSC_V3M_DBSCHQOS40,0x00000300);
    WriteReg_32(DBSC_V3M_DBSCHQOS41,0x000002F0);
    WriteReg_32(DBSC_V3M_DBSCHQOS42,0x00000200);
    WriteReg_32(DBSC_V3M_DBSCHQOS43,0x00000100);
    WriteReg_32(DBSC_V3M_DBSCHQOS90,0x00000300);
    WriteReg_32(DBSC_V3M_DBSCHQOS91,0x000002F0);
    WriteReg_32(DBSC_V3M_DBSCHQOS92,0x00000200);
    WriteReg_32(DBSC_V3M_DBSCHQOS93,0x00000100);
    WriteReg_32(DBSC_V3M_DBSCHQOS130,0x00000100);
    WriteReg_32(DBSC_V3M_DBSCHQOS131,0x000000F0);
    WriteReg_32(DBSC_V3M_DBSCHQOS132,0x000000A0);
    WriteReg_32(DBSC_V3M_DBSCHQOS133,0x00000040);
    WriteReg_32(DBSC_V3M_DBSCHQOS140,0x000000C0);
    WriteReg_32(DBSC_V3M_DBSCHQOS141,0x000000B0);
    WriteReg_32(DBSC_V3M_DBSCHQOS142,0x00000080);
    WriteReg_32(DBSC_V3M_DBSCHQOS143,0x00000040);
    WriteReg_32(DBSC_V3M_DBSCHQOS150,0x00000040);
    WriteReg_32(DBSC_V3M_DBSCHQOS151,0x00000030);
    WriteReg_32(DBSC_V3M_DBSCHQOS152,0x00000020);
    WriteReg_32(DBSC_V3M_DBSCHQOS153,0x00000010);
//    WriteReg_32(0xE67F0018,0X00000001);        //move
    WriteReg_32(DBSC_V3M_DBSYSCNT0,0x00000000);
#endif

    return 1;
}

uint32_t init_ddr_v3m1333(void)
{
    // modified last, 2018.10.11
    uint32_t RegVal_R2, RegVal_R5, RegVal_R6, RegVal_R7, RegVal_R12, i;

    uint32_t RegVal,j;
    uint32_t dqsgd_0c, bdlcount_0c, bdlcount_0c_div4, bdlcount_0c_div8;
    uint32_t gatesl_0c, rdqsd_0c, rdqsnd_0c, rbd_0c[4];

/* Initial setting ===============================================*/
    WriteReg_32(DBSC_V3M_DBSYSCNT0,0x00001234);
    WriteReg_32(DBSC_V3M_DBKIND,0x00000007);
#if V3MSK_2GB == 0
    WriteReg_32(DBSC_V3M_DBMEMCONF00,0x0f030a02);//Eagle board
#else
    WriteReg_32(DBSC_V3M_DBMEMCONF00,0x10030a02);//V3MSK board
#endif
    WriteReg_32(DBSC_V3M_DBPHYCONF0,0x00000001);
    WriteReg_32(DBSC_V3M_DBTR0,0x00000009);
    WriteReg_32(DBSC_V3M_DBTR1,0x00000007);
    WriteReg_32(DBSC_V3M_DBTR2,0x00000000);
    WriteReg_32(DBSC_V3M_DBTR3,0x00000009);
    WriteReg_32(DBSC_V3M_DBTR4,0x00090009);
    WriteReg_32(DBSC_V3M_DBTR5,0x00000021);
    WriteReg_32(DBSC_V3M_DBTR6,0x00000018);
    WriteReg_32(DBSC_V3M_DBTR7,0x00050005);
    WriteReg_32(DBSC_V3M_DBTR8,0x0000001E);
    WriteReg_32(DBSC_V3M_DBTR9,0x00000005);
    WriteReg_32(DBSC_V3M_DBTR10,0x0000000A);
    WriteReg_32(DBSC_V3M_DBTR11,0x00000009); //0x0000000A -> 0x00000009
    WriteReg_32(DBSC_V3M_DBTR12,0x00100010);
#if V3MSK_2GB == 0
    WriteReg_32(DBSC_V3M_DBTR13,0x000000AE);//Eagle board
#else
    WriteReg_32(DBSC_V3M_DBTR13,0x000000EA);//V3MSK board
#endif
    WriteReg_32(DBSC_V3M_DBTR14,0x00100004);
    WriteReg_32(DBSC_V3M_DBTR15,0x00040004); //0x00050004 -> 0x00040004
    WriteReg_32(DBSC_V3M_DBTR16,0x051B0305);
    WriteReg_32(DBSC_V3M_DBTR17,0x040C0000);
    WriteReg_32(DBSC_V3M_DBTR18,0x00000200);
    WriteReg_32(DBSC_V3M_DBTR19,0x01000040);
#if V3MSK_2GB == 0
    WriteReg_32(DBSC_V3M_DBTR20,0x020000B4);//Eagle board
#else
    WriteReg_32(DBSC_V3M_DBTR20,0x020000F0);//V3MSK board
#endif
    WriteReg_32(DBSC_V3M_DBTR21,0x00040004);
    WriteReg_32(DBSC_V3M_DBBL,0x00000000);
    WriteReg_32(DBSC_V3M_DBODT0,0x00000001);
    WriteReg_32(DBSC_V3M_DBADJ0,0x00000001);
    WriteReg_32(DBSC_V3M_DBSYSCONF1,0x00000002);
    WriteReg_32(DBSC_V3M_DBDFICNT0,0x00000010);
    WriteReg_32(DBSC_V3M_DBBCAMDIS,0x00000001);
#if V3MSK_2GB == 0
    WriteReg_32(DBSC_V3M_DBSCHRW1,0x00000046);//Eagle board
#else
    WriteReg_32(DBSC_V3M_DBSCHRW1,0x0000005E);//V3MSK board
#endif
    WriteReg_32(DBSC_V3M_SCFCTST0,0x0D050C03); //0x0E060C04 -> 0x0D050C03
    WriteReg_32(DBSC_V3M_SCFCTST1,0x0306030C); //0x0407040D -> 0x0306030C

    WriteReg_32(DBSC_V3M_DBPDLK0,0X0000A55A);
    WriteReg_32(DBSC_V3M_DBCMD,0x01000001);
    WriteReg_32(DBSC_V3M_DBCMD,0x08000000);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000001);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X80010000);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000006);
    while ( (BIT0 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 );

    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000008);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X000B8000);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000090);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X04058904);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000091);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X0007BB6D);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000095);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X0007BB6B);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000099);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X0007BB6D);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000090);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X04058900);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000021);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X0024641E);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000001);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X00010073);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000006);
    while ( (BIT0 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 );

    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000090);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X0C058900);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000090);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X04058900);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000006);
    while ( (BIT0 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 );

    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000003);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X0780C720); //0x0780C700 -> 0x0780C720
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000007);
    while ( (BIT30& ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 );

    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000004);
#if (RCAR_REF_INT == RCAR_REF_DEFAULT)	//REF 3.9usec
    #if V3MSK_2GB == 0
        WriteReg_32(DBSC_V3M_DBPDRGD0,0X07404FAF); //Eagle board,tREFI=3.9us,memory size : less than 8Gb
    #else
        WriteReg_32(DBSC_V3M_DBPDRGD0,0X07504FAF); //V3MSK board,tREFI=3.9us,memory size : 8Gb
    #endif
#elif (RCAR_REF_INT == RCAR_REF_7800)
    #if V3MSK_2GB == 0
        WriteReg_32(DBSC_V3M_DBPDRGD0,0X0740A0EF); //Eagle board,tREFI=7.8us,memory size : less than 8Gb
    #else
        WriteReg_32(DBSC_V3M_DBPDRGD0,0X0750A0EF); //V3MSK board,tREFI=7.8us,memory size : 8Gb
    #endif
#elif (RCAR_REF_INT == RCAR_REF_1950)
    #if V3MSK_2GB == 0
        WriteReg_32(DBSC_V3M_DBPDRGD0,0X0740238B); //Eagle board,tREFI=1.95us,memory size : less than 8Gb
    #else
        WriteReg_32(DBSC_V3M_DBPDRGD0,0X0750238B); //V3MSK board,tREFI=1.95us,memory size : 8Gb
    #endif
#else
    #error "Don't set out of range of RCAR_REF_INT."
#endif
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000022);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X1000040B);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000023);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X25580955);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000024);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X268753C0);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000025);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X30004200);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000026);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X0014A849);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000027);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X00000B50);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000028);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X00000004);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000029);
#if (RCAR_REF_INT == RCAR_REF_DEFAULT)	//REF 3.9usec
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X00000090); //tREFI=3.9us
#elif (RCAR_REF_INT == RCAR_REF_7800)
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X00000010); //tREFI=7.8us
#elif (RCAR_REF_INT == RCAR_REF_1950)
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X00000090); //tREFI=1.95us
#else
	#error "Don't set out of range of RCAR_REWT_TRAINING."
#endif
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X0000002C);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X81003047);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000020);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X00181884);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X0000001A);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X33C03C10);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000006);
    while ( (BIT0 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 );

    WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000A7);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X0D0D0D0D);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000A8);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X0D0D0D0D);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000A9);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X000D0D0D);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000C7);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X0D0D0D0D);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000C8);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X0D0D0D0D);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000C9);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X000D0D0D);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000E7);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X0D0D0D0D);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000E8);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X0D0D0D0D);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000E9);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X000D0D0D);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000107);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X0D0D0D0D);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000108);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X0D0D0D0D);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000109);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X000D0D0D);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000001);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X00010181);
    WriteReg_32(DBSC_V3M_DBCMD,0x08000001);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000006);
    while ( (BIT0 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 );

    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000001);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X00010601);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000006);
    while ( (BIT0 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 );

    for (i=0;i<4;i++)
    {
        WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B1 + i*0x20);
        RegVal_R5 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0x0000FF00 ) >> 8;
        WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B4 + i*0x20);
        RegVal_R6 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0x000000FF ) ;
        WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B3 + i*0x20);
        RegVal_R7 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0x00000007 ) ;
        if ( RegVal_R6 > 0 )
        {
            WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B2 + i*0x20);
            RegVal_R2 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0XFFFFFFF8 ) ;

            WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B2 + i*0x20);
            WriteReg_32(DBSC_V3M_DBPDRGD0,((RegVal_R7+1)&0X00000007) | RegVal_R2);
            WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B0 + i*0x20);
            RegVal_R2 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0XFFFFFF00 ) ;
            WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B0 + i*0x20);
            WriteReg_32(DBSC_V3M_DBPDRGD0,RegVal_R2 | RegVal_R6);
        } else
        {
            WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B2 + i*0x20);
            RegVal_R2 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0XFFFFFFF8 ) ;
            WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B2 + i*0x20);
            WriteReg_32(DBSC_V3M_DBPDRGD0,RegVal_R2 | RegVal_R7);

            WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B0 + i*0x20);
            RegVal_R2 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0XFFFFFF00 ) ;
            WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B0 + i*0x20);
            WriteReg_32(DBSC_V3M_DBPDRGD0,(((RegVal_R5<<1) + RegVal_R6 ) & 0X000000FF )| RegVal_R2);
        }
    }

    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000005);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0XC1AA00A0);
//    WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000A0);
//    WriteReg_32(DBSC_V3M_DBPDRGD0,0X7C0002C5);
//    WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000C0);
//    WriteReg_32(DBSC_V3M_DBPDRGD0,0X7C0002C5);
//    WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000E0);
//    WriteReg_32(DBSC_V3M_DBPDRGD0,0X7C0002C5);
//    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000100);
//    WriteReg_32(DBSC_V3M_DBPDRGD0,0X7C0002C5);

// PDR always off        add 2018/10/11
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000A3);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000008);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000C3);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000008);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000E3);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000008);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000103);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000008);

    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000001);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X00010801);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000006);
    while ( (BIT0 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 );

    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000005);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0XC1AA00B8);
//    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000001);
//    WriteReg_32(DBSC_V3M_DBPDRGD0,0X0001F001);
//    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000006);
//    while ( (BIT0 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 );

    WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000001);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x00011001);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000006);
    while ( (BIT0 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 );

    WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000A0);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x7C0002C5);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000C0);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x7C0002C5);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000E0);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x7C0002C5);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000100);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x7C0002C5);

// PDR default(dynamic)  add 2018/10/11
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000A3);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000000);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000C3);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000000);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000E3);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000000);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000103);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000000);

    WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000001);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x00012001);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000006);
    while ( (BIT0 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 );

    WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000A0);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x7C000285);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000C0);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x7C000285);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000E0);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x7C000285);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000100);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x7C000285);

// PDR always off        add 2018/10/11
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000A3);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000008);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000C3);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000008);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000E3);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000008);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000103);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000008);

    WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000001);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x00014001);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000006);
    while ( (BIT0 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 );

    WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000A0);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x7C0002C5);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000C0);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x7C0002C5);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000E0);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x7C0002C5);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000100);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x7C0002C5);

// PDR default(dynamic)  add 2018/10/11
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000A3);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000000);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000C3);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000000);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000E3);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000000);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000103);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000000);

    WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000001);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x00018001);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000006);
    while ( (BIT0 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 );

    WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000A0);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X7C000285);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000C0);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X7C000285);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000E0);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X7C000285);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000100);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X7C000285);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X0000002C);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X81003087);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000001);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X00010401);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000006);
    while ( (BIT0 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 );

    for (i=0;i<4;i++)
    {
        WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B1+ i*0x20);
        RegVal_R5 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0x0000FF00 ) >> 8;
        WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B4+ i*0x20);
        RegVal_R6 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0x000000FF ) ;

        WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B3+ i*0x20);
        RegVal_R7 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0x00000007 ) ;
        RegVal_R12= (RegVal_R5 >> 2 ) ;
        if ( RegVal_R6 - RegVal_R12 > 0 )
        {
            WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B2+ i*0x20);
            RegVal_R2 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0XFFFFFFF8 ) ;

            WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B2+ i*0x20);
            WriteReg_32(DBSC_V3M_DBPDRGD0,((RegVal_R7 + 1)&0X00000007) | RegVal_R2);
            WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B0+ i*0x20);
            RegVal_R2 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0XFFFFFF00 ) ;

            WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B0+ i*0x20);
            WriteReg_32(DBSC_V3M_DBPDRGD0,((RegVal_R6 - RegVal_R12)&0X000000FF) | RegVal_R2);
        } else
        {
            WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B2+ i*0x20);
            RegVal_R2 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0XFFFFFFF8 ) ;
            WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B2+ i*0x20);
            WriteReg_32(DBSC_V3M_DBPDRGD0,(RegVal_R7&0X00000007) | RegVal_R2);
            WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B0+ i*0x20);
            RegVal_R2 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0XFFFFFF00 ) ;
            WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B0+ i*0x20);
            WriteReg_32(DBSC_V3M_DBPDRGD0,((RegVal_R6 + RegVal_R5 + (RegVal_R5>>1) + RegVal_R12) & 0X000000FF) | RegVal_R2 );
        }
    }

//    WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000A0);
//    WriteReg_32(DBSC_V3M_DBPDRGD0,0X7C0002C5);
//    WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000C0);
//    WriteReg_32(DBSC_V3M_DBPDRGD0,0X7C0002C5);
//    WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000E0);
//    WriteReg_32(DBSC_V3M_DBPDRGD0,0X7C0002C5);
//    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000100);
//    WriteReg_32(DBSC_V3M_DBPDRGD0,0X7C0002C5);

// PDR always off        add 2018/10/11
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000A3);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000008);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000C3);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000008);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000E3);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000008);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000103);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000008);

    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000001);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X00015001);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000006);
    while ( (BIT0 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 );

    for (i=0; i< 4; i++) {
        WriteReg_32(DBSC_V3M_DBPDRGA0, 0x000000B0 + i * 0x20);
        dqsgd_0c = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0x000000FF);

        WriteReg_32(DBSC_V3M_DBPDRGA0, 0x000000B1 + i * 0x20);
        bdlcount_0c = ((ReadReg_32(DBSC_V3M_DBPDRGD0) & 0x0000FF00) >> 8);

        bdlcount_0c_div4  = (bdlcount_0c >> 2);
        bdlcount_0c_div8  = (bdlcount_0c >> 3);

        if (dqsgd_0c > bdlcount_0c) {
            if (dqsgd_0c <= bdlcount_0c + bdlcount_0c_div4 + bdlcount_0c_div8) {
                WriteReg_32(DBSC_V3M_DBPDRGA0, 0x000000B0 + i * 0x20);
                RegVal = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0xFFFFFF00);
                WriteReg_32(DBSC_V3M_DBPDRGD0,((dqsgd_0c - bdlcount_0c_div8) | RegVal));
            } else {
                WriteReg_32(DBSC_V3M_DBPDRGA0, 0x000000B0 + i * 0x20);
                RegVal = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0xFFFFFF00);
                WriteReg_32(DBSC_V3M_DBPDRGD0, RegVal);
                WriteReg_32(DBSC_V3M_DBPDRGA0, 0x000000B2 + i * 0x20);
                gatesl_0c = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0x00000007);
                WriteReg_32(DBSC_V3M_DBPDRGA0, 0x000000B2 + i * 0x20);
                RegVal = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0xFFFFFFF8);
                WriteReg_32(DBSC_V3M_DBPDRGD0, (RegVal|(gatesl_0c + 1)));
                WriteReg_32(DBSC_V3M_DBPDRGA0, 0x000000AF + i * 0x20);
                RegVal = (ReadReg_32(DBSC_V3M_DBPDRGD0));
                rdqsd_0c = (RegVal & 0x0000FF00) >> 8;
                rdqsnd_0c = (RegVal & 0x00FF0000) >> 16;
                WriteReg_32(DBSC_V3M_DBPDRGA0, 0x000000AF + i * 0x20);
                WriteReg_32(DBSC_V3M_DBPDRGD0, ((RegVal & 0xFF0000FF)|((rdqsd_0c + bdlcount_0c_div8) << 8)|((rdqsnd_0c + bdlcount_0c_div8) << 16)));
                WriteReg_32(DBSC_V3M_DBPDRGA0, 0x000000AA + i * 0x20);
                RegVal = (ReadReg_32(DBSC_V3M_DBPDRGD0));
                rbd_0c[0] = (RegVal      ) & 0x0000001f;
                rbd_0c[1] = (RegVal >>  8) & 0x0000001f;
                rbd_0c[2] = (RegVal >> 16) & 0x0000001f;
                rbd_0c[3] = (RegVal >> 24) & 0x0000001f;

                WriteReg_32(DBSC_V3M_DBPDRGA0, 0x000000AA + i * 0x20);
                RegVal = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0xE0E0E0E0);
                for (j=0; j< 4; j++) {
                    rbd_0c[j] = (rbd_0c[j] + bdlcount_0c_div8);
                    if (rbd_0c[j] > 0x1F) rbd_0c[j] = 0x1F;
                    RegVal = RegVal | (rbd_0c[j] <<8*j);
                }
                WriteReg_32(DBSC_V3M_DBPDRGD0, RegVal);
                WriteReg_32(DBSC_V3M_DBPDRGA0, 0x000000AB + i * 0x20);
                RegVal = (ReadReg_32(DBSC_V3M_DBPDRGD0));
                rbd_0c[0] = (RegVal      ) & 0x0000001f;
                rbd_0c[1] = (RegVal >>  8) & 0x0000001f;
                rbd_0c[2] = (RegVal >> 16) & 0x0000001f;
                rbd_0c[3] = (RegVal >> 24) & 0x0000001f;

                WriteReg_32(DBSC_V3M_DBPDRGA0, 0x000000AB + i * 0x20);
                RegVal = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0xE0E0E0E0);
                for (j=0; j< 4; j++) {
                    rbd_0c[j] = (rbd_0c[j] + bdlcount_0c_div8);
                    if (rbd_0c[j] > 0x1F) rbd_0c[j] = 0x1F;
                    RegVal = RegVal | (rbd_0c[j] <<8*j);
                }
                WriteReg_32(DBSC_V3M_DBPDRGD0, RegVal);
            }
        }
    }
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000002);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x07D81E37);

    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000003);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X0380C720); //0x0380C700 -> 0x0380C720
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000007);
    while ( (BIT30& ReadReg_32(DBSC_V3M_DBPDRGD0)) != 0 );

    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000021);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X0024643E);

    WriteReg_32(DBSC_V3M_DBBUS0CNF1,0x00000000);
#if (RCAR_REF_INT == RCAR_REF_DEFAULT)	//REF 3.9usec
    WriteReg_32(DBSC_V3M_DBCALCNF,0x0100401A); //tREFI=3.9us
    WriteReg_32(DBSC_V3M_DBRFCNF1,0x00080A27); //tREFI=3.9us
    WriteReg_32(DBSC_V3M_DBRFCNF2,0x00010000); //tREFI=3.9us
#elif (RCAR_REF_INT == RCAR_REF_7800)
    WriteReg_32(DBSC_V3M_DBCALCNF,0x0100200D); //tREFI=7.8us, 0x0100200E => 0x0100200D
    WriteReg_32(DBSC_V3M_DBRFCNF1,0x0008144F); //tREFI=7.8us, 0x00081450 => 0x0008144F
    WriteReg_32(DBSC_V3M_DBRFCNF2,0x00010000); //tREFI=7.8us
#elif (RCAR_REF_INT == RCAR_REF_1950)
    WriteReg_32(DBSC_V3M_DBCALCNF,0x0100401A); //tREFI=1.95us
    WriteReg_32(DBSC_V3M_DBRFCNF1,0x00080A27); //tREFI=1.95us
    WriteReg_32(DBSC_V3M_DBRFCNF2,0x00010001); //tREFI=1.95us
#else
    #error "Don't set out of range of RCAR_REF_INT."
#endif
    WriteReg_32(DBSC_V3M_DBDFICUPDCNF,0x40100001);
    WriteReg_32(DBSC_V3M_DBRFEN,0x00000001);
    WriteReg_32(DBSC_V3M_DBACEN,0x00000001);

    WriteReg_32(0xE67F0018,0x00000001);
    RegVal = ReadReg_32(0x40000000);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000000);
    WriteReg_32(DBSC_V3M_DBPDRGD0,RegVal);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000A0);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x7C0002C5);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000C0);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x7C0002C5);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000E0);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x7C0002C5);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000100);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x7C0002C5);

// PDR default(dynamic)  add 2018/10/11
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000A3);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000000);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000C3);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000000);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000E3);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000000);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000103);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000000);

    WriteReg_32(DBSC_V3M_DBPDLK0,0X00000000);
    WriteReg_32(DBSC_V3M_DBSYSCNT0,0x00000000);

#ifdef ddr_qos_init_setting // only for non qos_init:add 2018.01.25
    WriteReg_32(DBSC_V3M_DBSYSCNT0,0x00001234);
    WriteReg_32(DBSC_V3M_DBCAM0CNF1,0x00043218);
    WriteReg_32(DBSC_V3M_DBCAM0CNF2,0x000000F4);
    WriteReg_32(DBSC_V3M_DBSCHCNT0,0x000f0037);
    WriteReg_32(DBSC_V3M_DBSCHSZ0,0x00000001);
    WriteReg_32(DBSC_V3M_DBSCHRW0,0x22421111);
    WriteReg_32(DBSC_V3M_SCFCTST2,0x012F1123);
    WriteReg_32(DBSC_V3M_DBSCHQOS00,0x00000F00);
    WriteReg_32(DBSC_V3M_DBSCHQOS01,0x00000B00);
    WriteReg_32(DBSC_V3M_DBSCHQOS02,0x00000000);
    WriteReg_32(DBSC_V3M_DBSCHQOS03,0x00000000);
    WriteReg_32(DBSC_V3M_DBSCHQOS40,0x00000300);
    WriteReg_32(DBSC_V3M_DBSCHQOS41,0x000002F0);
    WriteReg_32(DBSC_V3M_DBSCHQOS42,0x00000200);
    WriteReg_32(DBSC_V3M_DBSCHQOS43,0x00000100);
    WriteReg_32(DBSC_V3M_DBSCHQOS90,0x00000300);
    WriteReg_32(DBSC_V3M_DBSCHQOS91,0x000002F0);
    WriteReg_32(DBSC_V3M_DBSCHQOS92,0x00000200);
    WriteReg_32(DBSC_V3M_DBSCHQOS93,0x00000100);
    WriteReg_32(DBSC_V3M_DBSCHQOS130,0x00000100);
    WriteReg_32(DBSC_V3M_DBSCHQOS131,0x000000F0);
    WriteReg_32(DBSC_V3M_DBSCHQOS132,0x000000A0);
    WriteReg_32(DBSC_V3M_DBSCHQOS133,0x00000040);
    WriteReg_32(DBSC_V3M_DBSCHQOS140,0x000000C0);
    WriteReg_32(DBSC_V3M_DBSCHQOS141,0x000000B0);
    WriteReg_32(DBSC_V3M_DBSCHQOS142,0x00000080);
    WriteReg_32(DBSC_V3M_DBSCHQOS143,0x00000040);
    WriteReg_32(DBSC_V3M_DBSCHQOS150,0x00000040);
    WriteReg_32(DBSC_V3M_DBSCHQOS151,0x00000030);
    WriteReg_32(DBSC_V3M_DBSCHQOS152,0x00000020);
    WriteReg_32(DBSC_V3M_DBSCHQOS153,0x00000010);
//    WriteReg_32(0xE67F0018,0X00000001);        //move
    WriteReg_32(DBSC_V3M_DBSYSCNT0,0x00000000);
#endif

    return 1;
}

uint32_t init_ddr_v3m1583(void)
{
    // modified last, 2018.10.11
    uint32_t RegVal_R2, RegVal_R5, RegVal_R6, RegVal_R7, RegVal_R12, i;

    uint32_t RegVal,j;
    uint32_t dqsgd_0c, bdlcount_0c, bdlcount_0c_div2, bdlcount_0c_div4, bdlcount_0c_div8, bdlcount_0c_div16;
    uint32_t gatesl_0c, rdqsd_0c, rdqsnd_0c, rbd_0c[4];

/* Initial setting ===============================================*/
    WriteReg_32(DBSC_V3M_DBSYSCNT0,0x00001234);
    WriteReg_32(DBSC_V3M_DBKIND,0x00000007);
#if V3MSK_2GB == 0
    WriteReg_32(DBSC_V3M_DBMEMCONF00,0x0f030a02);//Eagle board
#else
    WriteReg_32(DBSC_V3M_DBMEMCONF00,0x10030a02);//V3MSK board
#endif
    WriteReg_32(DBSC_V3M_DBPHYCONF0,0x00000001);
    WriteReg_32(DBSC_V3M_DBTR0,0x0000000B);
    WriteReg_32(DBSC_V3M_DBTR1,0x00000008);
    WriteReg_32(DBSC_V3M_DBTR2,0x00000000);
    WriteReg_32(DBSC_V3M_DBTR3,0x0000000B);
    WriteReg_32(DBSC_V3M_DBTR4,0x000B000B);
    WriteReg_32(DBSC_V3M_DBTR5,0x00000027);
    WriteReg_32(DBSC_V3M_DBTR6,0x0000001C);
    WriteReg_32(DBSC_V3M_DBTR7,0x00060006);
    WriteReg_32(DBSC_V3M_DBTR8,0x00000020);
    WriteReg_32(DBSC_V3M_DBTR9,0x00000006);
    WriteReg_32(DBSC_V3M_DBTR10,0x0000000C);
    WriteReg_32(DBSC_V3M_DBTR11,0x0000000A);
    WriteReg_32(DBSC_V3M_DBTR12,0x00120012);
#if V3MSK_2GB == 0
    WriteReg_32(DBSC_V3M_DBTR13,0x000000CE);//Eagle board
#else
    WriteReg_32(DBSC_V3M_DBTR13,0x00000116);//V3MSK board,0x00000118 -> 0x00000116
#endif
    WriteReg_32(DBSC_V3M_DBTR14,0x00130005);//0x00140005 -> 0x00130005
    WriteReg_32(DBSC_V3M_DBTR15,0x00050004);
    WriteReg_32(DBSC_V3M_DBTR16,0x071F0305);
    WriteReg_32(DBSC_V3M_DBTR17,0x040C0000);
    WriteReg_32(DBSC_V3M_DBTR18,0x00000200);
    WriteReg_32(DBSC_V3M_DBTR19,0x01000040);
#if V3MSK_2GB == 0
    WriteReg_32(DBSC_V3M_DBTR20,0x020000D6);//Eagle board
#else
    WriteReg_32(DBSC_V3M_DBTR20,0x0200011D);//V3MSK board,0x02000120 -> 0x0200011D
#endif
    WriteReg_32(DBSC_V3M_DBTR21,0x00040004);
    WriteReg_32(DBSC_V3M_DBBL,0x00000000);
    WriteReg_32(DBSC_V3M_DBODT0,0x00000001);
    WriteReg_32(DBSC_V3M_DBADJ0,0x00000001);
    WriteReg_32(DBSC_V3M_DBSYSCONF1,0x00000002);
    WriteReg_32(DBSC_V3M_DBDFICNT0,0x00000010);
    WriteReg_32(DBSC_V3M_DBBCAMDIS,0x00000001);
#if V3MSK_2GB == 0
    WriteReg_32(DBSC_V3M_DBSCHRW1,0x00000046);//Eagle board
#else
    WriteReg_32(DBSC_V3M_DBSCHRW1,0x0000005E);//V3MSK board
#endif
    WriteReg_32(DBSC_V3M_SCFCTST0,0x0D050B03);//0x0D060C04 -> 0x0D050B03
    WriteReg_32(DBSC_V3M_SCFCTST1,0x0306030C);//0x0406040C -> 0x0306030C

    WriteReg_32(DBSC_V3M_DBPDLK0,0X0000A55A);
    WriteReg_32(DBSC_V3M_DBCMD,0x01000001);
    WriteReg_32(DBSC_V3M_DBCMD,0x08000000);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000001);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X80010000);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000006);
    while ( (BIT0 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 );

    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000008);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X000B8000);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000090);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X04058904);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000091);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X0007BB6D);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000095);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X0007BB6B);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000099);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X0007BB6D);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000090);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X04058900);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000021);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X0024641E);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000001);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X00010073);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000006);
    while ( (BIT0 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 );

    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000090);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X0C058900);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000090);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X04058900);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000006);
    while ( (BIT0 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 );

    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000003);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X0780C720); //0x0780C700 -> 0x0780C720
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000007);
    while ( (BIT30& ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 );

    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000004);
#if (RCAR_REF_INT == RCAR_REF_DEFAULT)	//REF 3.9usec
    #if V3MSK_2GB == 0
        WriteReg_32(DBSC_V3M_DBPDRGD0,0X08A05EEB);//Eagle board,tREFI=3.9us,memory size : less than 8Gb
    #else
        WriteReg_32(DBSC_V3M_DBPDRGD0,0X08B05EEB);//V3MSK board,tREFI=3.9us,memory size : 8Gb
    #endif
#elif (RCAR_REF_INT == RCAR_REF_7800)
    #if V3MSK_2GB == 0
        WriteReg_32(DBSC_V3M_DBPDRGD0,0X08A0BF67);//Eagle board,tREFI=7.8us,memory size : less than 8Gb
    #else
        WriteReg_32(DBSC_V3M_DBPDRGD0,0X08B0BF67);//V3MSK board,tREFI=7.8us,memory size : 8Gb
    #endif
#elif (RCAR_REF_INT == RCAR_REF_1950)
    #if V3MSK_2GB == 0
        WriteReg_32(DBSC_V3M_DBPDRGD0,0X08A02B29);//Eagle board,tREFI=1.95us,memory size : less than 8Gb
    #else
        WriteReg_32(DBSC_V3M_DBPDRGD0,0X08B02B29);//V3MSK board,tREFI=1.95us,memory size : 8Gb
    #endif
#else
    #error "Don't set out of range of RCAR_REF_INT."
#endif
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000022);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X1000040B);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000023);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X2D9C0B66);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000024);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X2A88B400);//0x2A88C400 -> 0x2A88B400
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000025);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X30004E00);//0x30005200 -> 0X30004E00
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000026);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X0014A9C9);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000027);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X00000D70);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000028);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X00000004);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000029);
#if (RCAR_REF_INT == RCAR_REF_DEFAULT)	//REF 3.9usec
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X00000098);//tREFI=3.9us
#elif (RCAR_REF_INT == RCAR_REF_7800)
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X00000018);//tREFI=7.8us
#elif (RCAR_REF_INT == RCAR_REF_1950)
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X00000098);//tREFI=1.95us
#else
    #error "Don't set out of range of RCAR_REF_INT."
#endif
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X0000002C);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X81003047);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000020);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X00181884);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X0000001A);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X33C03C10);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000006);
    while ( (BIT0 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 );

    WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000A7);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X0D0D0D0D);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000A8);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X0D0D0D0D);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000A9);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X000D0D0D);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000C7);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X0D0D0D0D);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000C8);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X0D0D0D0D);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000C9);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X000D0D0D);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000E7);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X0D0D0D0D);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000E8);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X0D0D0D0D);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000E9);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X000D0D0D);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000107);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X0D0D0D0D);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000108);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X0D0D0D0D);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000109);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X000D0D0D);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000001);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X00010181);
    WriteReg_32(DBSC_V3M_DBCMD,0x08000001);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000006);
    while ( (BIT0 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 );

    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000001);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X00010601);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000006);
    while ( (BIT0 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 );

    for (i=0;i<4;i++)
    {
        WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B1 + i*0x20);
        RegVal_R5 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0x0000FF00 ) >> 8;
        WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B4 + i*0x20);
        RegVal_R6 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0x000000FF ) ;
        WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B3 + i*0x20);
        RegVal_R7 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0x00000007 ) ;
        if ( RegVal_R6 > 0 )
        {
            WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B2 + i*0x20);
            RegVal_R2 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0XFFFFFFF8 ) ;

            WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B2 + i*0x20);
            WriteReg_32(DBSC_V3M_DBPDRGD0,((RegVal_R7+1)&0X00000007) | RegVal_R2);
            WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B0 + i*0x20);
            RegVal_R2 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0XFFFFFF00 ) ;
            WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B0 + i*0x20);
            WriteReg_32(DBSC_V3M_DBPDRGD0,RegVal_R2 | RegVal_R6);
        } else
        {
            WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B2 + i*0x20);
            RegVal_R2 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0XFFFFFFF8 ) ;
            WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B2 + i*0x20);
            WriteReg_32(DBSC_V3M_DBPDRGD0,RegVal_R2 | RegVal_R7);

            WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B0 + i*0x20);
            RegVal_R2 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0XFFFFFF00 ) ;
            WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B0 + i*0x20);
            WriteReg_32(DBSC_V3M_DBPDRGD0,(((RegVal_R5<<1) + RegVal_R6 ) & 0X000000FF )| RegVal_R2);
        }
    }

    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000005);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0XC1AA00C0);
//    WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000A0);
//    WriteReg_32(DBSC_V3M_DBPDRGD0,0X7C0002C5);
//    WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000C0);
//    WriteReg_32(DBSC_V3M_DBPDRGD0,0X7C0002C5);
//    WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000E0);
//    WriteReg_32(DBSC_V3M_DBPDRGD0,0X7C0002C5);
//    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000100);
//    WriteReg_32(DBSC_V3M_DBPDRGD0,0X7C0002C5);

// PDR always off        add 2018/10/11
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000A3);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000008);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000C3);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000008);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000E3);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000008);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000103);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000008);

    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000001);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X00010801);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000006);
    while ( (BIT0 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 );

    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000005);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0XC1AA00D8);
//    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000001);
//    WriteReg_32(DBSC_V3M_DBPDRGD0,0X0001F001);
//    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000006);
//    while ( (BIT0 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 );

    WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000001);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x00011001);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000006);
    while ( (BIT0 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 );

    WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000A0);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x7C0002C5);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000C0);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x7C0002C5);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000E0);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x7C0002C5);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000100);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x7C0002C5);

// PDR default(dynamic)  add 2018/10/11
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000A3);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000000);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000C3);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000000);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000E3);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000000);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000103);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000000);

    WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000001);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x00012001);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000006);
    while ( (BIT0 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 );

    WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000A0);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x7C000285);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000C0);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x7C000285);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000E0);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x7C000285);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000100);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x7C000285);

// PDR always off        add 2018/10/11
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000A3);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000008);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000C3);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000008);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000E3);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000008);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000103);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000008);

    WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000001);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x00014001);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000006);
    while ( (BIT0 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 );

    WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000A0);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x7C0002C5);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000C0);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x7C0002C5);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000E0);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x7C0002C5);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000100);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x7C0002C5);

// PDR default(dynamic)  add 2018/10/11
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000A3);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000000);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000C3);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000000);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000E3);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000000);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000103);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000000);

    WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000001);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x00018001);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000006);
    while ( (BIT0 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 );

    WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000A0);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X7C000285);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000C0);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X7C000285);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000E0);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X7C000285);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000100);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X7C000285);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X0000002C);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X81003087);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000001);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X00010401);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000006);
    while ( (BIT0 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 );

    for (i=0;i<4;i++)
    {
        WriteReg_32(DBSC_V3M_DBPDRGA0, 0X000000B1 + i * 0x20);
        RegVal_R5 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0x0000FF00) >> 8;
        WriteReg_32(DBSC_V3M_DBPDRGA0, 0X000000B4 + i * 0x20);
        RegVal_R6 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0x000000FF);

        WriteReg_32(DBSC_V3M_DBPDRGA0, 0X000000B3 + i * 0x20);
        RegVal_R7 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0x00000007);
        RegVal_R12 = (RegVal_R5 >> 2);
        if (RegVal_R6 - RegVal_R12 > 0)
        {
            WriteReg_32(DBSC_V3M_DBPDRGA0, 0X000000B2 + i * 0x20);
            RegVal_R2 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0XFFFFFFF8);

            WriteReg_32(DBSC_V3M_DBPDRGA0, 0X000000B2 + i * 0x20);
            WriteReg_32(DBSC_V3M_DBPDRGD0, ((RegVal_R7 + 1) & 0X00000007) | RegVal_R2);
            WriteReg_32(DBSC_V3M_DBPDRGA0, 0X000000B0 + i * 0x20);
            RegVal_R2 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0XFFFFFF00);

            WriteReg_32(DBSC_V3M_DBPDRGA0, 0X000000B0 + i * 0x20);
            WriteReg_32(DBSC_V3M_DBPDRGD0, ((RegVal_R6 - RegVal_R12) & 0X000000FF) | RegVal_R2);
        }
        else
        {
            WriteReg_32(DBSC_V3M_DBPDRGA0, 0X000000B2 + i * 0x20);
            RegVal_R2 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0XFFFFFFF8);
            WriteReg_32(DBSC_V3M_DBPDRGA0, 0X000000B2 + i * 0x20);
            WriteReg_32(DBSC_V3M_DBPDRGD0, (RegVal_R7 & 0X00000007) | RegVal_R2);
            WriteReg_32(DBSC_V3M_DBPDRGA0, 0X000000B0 + i * 0x20);
            RegVal_R2 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0XFFFFFF00);
            WriteReg_32(DBSC_V3M_DBPDRGA0, 0X000000B0 + i * 0x20);
            WriteReg_32(DBSC_V3M_DBPDRGD0, ((RegVal_R6 + RegVal_R5 + (RegVal_R5 >> 1) + RegVal_R12) & 0X000000FF) | RegVal_R2);
        }
    }

//    WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000A0);
//    WriteReg_32(DBSC_V3M_DBPDRGD0,0X7C0002C5);
//    WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000C0);
//    WriteReg_32(DBSC_V3M_DBPDRGD0,0X7C0002C5);
//    WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000E0);
//    WriteReg_32(DBSC_V3M_DBPDRGD0,0X7C0002C5);
//    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000100);
//    WriteReg_32(DBSC_V3M_DBPDRGD0,0X7C0002C5);

// PDR always off        add 2018/10/11
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000A3);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000008);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000C3);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000008);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000E3);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000008);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000103);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000008);

    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000001);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X00015001);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000006);
    while ( (BIT0 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 );

    for (i=0; i< 4; i++) {
        WriteReg_32(DBSC_V3M_DBPDRGA0, 0x000000B0 + i * 0x20);
        dqsgd_0c = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0x000000FF);

        WriteReg_32(DBSC_V3M_DBPDRGA0, 0x000000B1 + i * 0x20);
        bdlcount_0c = ((ReadReg_32(DBSC_V3M_DBPDRGD0) & 0x0000FF00) >> 8);

        bdlcount_0c_div2  = (bdlcount_0c >> 1);
        bdlcount_0c_div4  = (bdlcount_0c >> 2);
        bdlcount_0c_div8  = (bdlcount_0c >> 3);
        bdlcount_0c_div16 = (bdlcount_0c >> 4);

        if (dqsgd_0c > bdlcount_0c_div2 + bdlcount_0c_div4 + bdlcount_0c_div8) {
            if (dqsgd_0c <= bdlcount_0c + bdlcount_0c_div4 + bdlcount_0c_div16) {
                WriteReg_32(DBSC_V3M_DBPDRGA0, 0x000000B0 + i * 0x20);
                RegVal = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0xFFFFFF00);
                WriteReg_32(DBSC_V3M_DBPDRGD0,((dqsgd_0c - bdlcount_0c_div8) | RegVal));
            } else {
                WriteReg_32(DBSC_V3M_DBPDRGA0, 0x000000B0 + i * 0x20);
                RegVal = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0xFFFFFF00);
                WriteReg_32(DBSC_V3M_DBPDRGD0, RegVal);
                WriteReg_32(DBSC_V3M_DBPDRGA0, 0x000000B2 + i * 0x20);
                gatesl_0c = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0x00000007);
                WriteReg_32(DBSC_V3M_DBPDRGA0, 0x000000B2 + i * 0x20);
                RegVal = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0xFFFFFFF8);
                WriteReg_32(DBSC_V3M_DBPDRGD0, (RegVal|(gatesl_0c + 1)));
                WriteReg_32(DBSC_V3M_DBPDRGA0, 0x000000AF + i * 0x20);
                RegVal = (ReadReg_32(DBSC_V3M_DBPDRGD0));
                rdqsd_0c = (RegVal & 0x0000FF00) >> 8;
                rdqsnd_0c = (RegVal & 0x00FF0000) >> 16;
                WriteReg_32(DBSC_V3M_DBPDRGA0, 0x000000AF + i * 0x20);
                WriteReg_32(DBSC_V3M_DBPDRGD0, ((RegVal & 0xFF0000FF)|((rdqsd_0c + bdlcount_0c_div4) << 8)|((rdqsnd_0c + bdlcount_0c_div4) << 16)));
                WriteReg_32(DBSC_V3M_DBPDRGA0, 0x000000AA + i * 0x20);
                RegVal = (ReadReg_32(DBSC_V3M_DBPDRGD0));
                rbd_0c[0] = (RegVal      ) & 0x0000001f;
                rbd_0c[1] = (RegVal >>  8) & 0x0000001f;
                rbd_0c[2] = (RegVal >> 16) & 0x0000001f;
                rbd_0c[3] = (RegVal >> 24) & 0x0000001f;

                WriteReg_32(DBSC_V3M_DBPDRGA0, 0x000000AA + i * 0x20);
                RegVal = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0xE0E0E0E0);
                for (j=0; j< 4; j++) {
                    rbd_0c[j] = (rbd_0c[j] + bdlcount_0c_div4);
                    if (rbd_0c[j] > 0x1F) rbd_0c[j] = 0x1F;
                    RegVal = RegVal | (rbd_0c[j] <<8*j);
                }
                WriteReg_32(DBSC_V3M_DBPDRGD0, RegVal);
                WriteReg_32(DBSC_V3M_DBPDRGA0, 0x000000AB + i * 0x20);
                RegVal = (ReadReg_32(DBSC_V3M_DBPDRGD0));
                rbd_0c[0] = (RegVal      ) & 0x0000001f;
                rbd_0c[1] = (RegVal >>  8) & 0x0000001f;
                rbd_0c[2] = (RegVal >> 16) & 0x0000001f;
                rbd_0c[3] = (RegVal >> 24) & 0x0000001f;

                WriteReg_32(DBSC_V3M_DBPDRGA0, 0x000000AB + i * 0x20);
                RegVal = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0xE0E0E0E0);
                for (j=0; j< 4; j++) {
                    rbd_0c[j] = (rbd_0c[j] + bdlcount_0c_div4);
                    if (rbd_0c[j] > 0x1F) rbd_0c[j] = 0x1F;
                    RegVal = RegVal | (rbd_0c[j] <<8*j);
                }
                WriteReg_32(DBSC_V3M_DBPDRGD0, RegVal);
            }
        }
    }
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000002);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x07D81E37);

    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000003);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X0380C720); //0x0380C700 -> 0x0380C720
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000007);
    while ( (BIT30& ReadReg_32(DBSC_V3M_DBPDRGD0)) != 0 );

    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000021);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X0024643E);

    WriteReg_32(DBSC_V3M_DBBUS0CNF1,0x00000000);
#if (RCAR_REF_INT == RCAR_REF_DEFAULT)	//REF 3.9usec
    WriteReg_32(DBSC_V3M_DBCALCNF,0x0100401A);//tREFI=3.9us
    WriteReg_32(DBSC_V3M_DBRFCNF1,0x00080C0F);//tREFI=3.9us
    WriteReg_32(DBSC_V3M_DBRFCNF2,0x00010000);//tREFI=3.9us
#elif (RCAR_REF_INT == RCAR_REF_7800)
    WriteReg_32(DBSC_V3M_DBCALCNF,0x0100200D);//tREFI=7.8us
    WriteReg_32(DBSC_V3M_DBRFCNF1,0x0008181E);//tREFI=7.8us
    WriteReg_32(DBSC_V3M_DBRFCNF2,0x00010000);//tREFI=7.8us
#elif (RCAR_REF_INT == RCAR_REF_1950)
    WriteReg_32(DBSC_V3M_DBCALCNF,0x0100401A);//tREFI=1.95us
    WriteReg_32(DBSC_V3M_DBRFCNF1,0x00080C0F);//tREFI=1.95us
    WriteReg_32(DBSC_V3M_DBRFCNF2,0x00010001);//tREFI=1.95us
#else
    #error "Don't set out of range of RCAR_REF_INT."
#endif
    WriteReg_32(DBSC_V3M_DBDFICUPDCNF,0x40100001);
    WriteReg_32(DBSC_V3M_DBRFEN,0x00000001);
    WriteReg_32(DBSC_V3M_DBACEN,0x00000001);

    WriteReg_32(0xE67F0018,0x00000001);
    RegVal = ReadReg_32(0x40000000);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000000);
    WriteReg_32(DBSC_V3M_DBPDRGD0,RegVal);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000A0);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x7C0002C5);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000C0);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x7C0002C5);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000E0);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x7C0002C5);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000100);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x7C0002C5);

// PDR default(dynamic)  add 2018/10/11
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000A3);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000000);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000C3);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000000);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000E3);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000000);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000103);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000000);

    WriteReg_32(DBSC_V3M_DBPDLK0,0X00000000);
    WriteReg_32(DBSC_V3M_DBSYSCNT0,0x00000000);

#ifdef ddr_qos_init_setting // only for non qos_init:add 2018.01.25
    WriteReg_32(DBSC_V3M_DBSYSCNT0,0x00001234);
    WriteReg_32(DBSC_V3M_DBCAM0CNF1,0x00043218);
    WriteReg_32(DBSC_V3M_DBCAM0CNF2,0x000000F4);
    WriteReg_32(DBSC_V3M_DBSCHCNT0,0x000f0037);
    WriteReg_32(DBSC_V3M_DBSCHSZ0,0x00000001);
    WriteReg_32(DBSC_V3M_DBSCHRW0,0x22421111);
    WriteReg_32(DBSC_V3M_SCFCTST2,0x012F1123);
    WriteReg_32(DBSC_V3M_DBSCHQOS00,0x00000F00);
    WriteReg_32(DBSC_V3M_DBSCHQOS01,0x00000B00);
    WriteReg_32(DBSC_V3M_DBSCHQOS02,0x00000000);
    WriteReg_32(DBSC_V3M_DBSCHQOS03,0x00000000);
    WriteReg_32(DBSC_V3M_DBSCHQOS40,0x00000300);
    WriteReg_32(DBSC_V3M_DBSCHQOS41,0x000002F0);
    WriteReg_32(DBSC_V3M_DBSCHQOS42,0x00000200);
    WriteReg_32(DBSC_V3M_DBSCHQOS43,0x00000100);
    WriteReg_32(DBSC_V3M_DBSCHQOS90,0x00000300);
    WriteReg_32(DBSC_V3M_DBSCHQOS91,0x000002F0);
    WriteReg_32(DBSC_V3M_DBSCHQOS92,0x00000200);
    WriteReg_32(DBSC_V3M_DBSCHQOS93,0x00000100);
    WriteReg_32(DBSC_V3M_DBSCHQOS130,0x00000100);
    WriteReg_32(DBSC_V3M_DBSCHQOS131,0x000000F0);
    WriteReg_32(DBSC_V3M_DBSCHQOS132,0x000000A0);
    WriteReg_32(DBSC_V3M_DBSCHQOS133,0x00000040);
    WriteReg_32(DBSC_V3M_DBSCHQOS140,0x000000C0);
    WriteReg_32(DBSC_V3M_DBSCHQOS141,0x000000B0);
    WriteReg_32(DBSC_V3M_DBSCHQOS142,0x00000080);
    WriteReg_32(DBSC_V3M_DBSCHQOS143,0x00000040);
    WriteReg_32(DBSC_V3M_DBSCHQOS150,0x00000040);
    WriteReg_32(DBSC_V3M_DBSCHQOS151,0x00000030);
    WriteReg_32(DBSC_V3M_DBSCHQOS152,0x00000020);
    WriteReg_32(DBSC_V3M_DBSCHQOS153,0x00000010);
//    WriteReg_32(0xE67F0018,0X00000001);        //move
    WriteReg_32(DBSC_V3M_DBSYSCNT0,0x00000000);
#endif

    return 1;
}

uint32_t init_ddr_v3m1316(void)
{
    // modified last, 2018.10.11
    uint32_t RegVal_R2, RegVal_R5, RegVal_R6, RegVal_R7, RegVal_R12, i;

    uint32_t RegVal,j;
    uint32_t dqsgd_0c, bdlcount_0c, bdlcount_0c_div4, bdlcount_0c_div8;
    uint32_t gatesl_0c, rdqsd_0c, rdqsnd_0c, rbd_0c[4];

/* Initial setting ===============================================*/
    WriteReg_32(DBSC_V3M_DBSYSCNT0,0x00001234);
    WriteReg_32(DBSC_V3M_DBKIND,0x00000007);
#if V3MSK_2GB == 0
    WriteReg_32(DBSC_V3M_DBMEMCONF00,0x0f030a02);//Eagle board
#else
    WriteReg_32(DBSC_V3M_DBMEMCONF00,0x10030a02);//V3MSK board
#endif
    WriteReg_32(DBSC_V3M_DBPHYCONF0,0x00000001);
    WriteReg_32(DBSC_V3M_DBTR0,0x00000009);
    WriteReg_32(DBSC_V3M_DBTR1,0x00000007);
    WriteReg_32(DBSC_V3M_DBTR2,0x00000000);
    WriteReg_32(DBSC_V3M_DBTR3,0x00000009);
    WriteReg_32(DBSC_V3M_DBTR4,0x00090009);
    WriteReg_32(DBSC_V3M_DBTR5,0x00000021);
    WriteReg_32(DBSC_V3M_DBTR6,0x00000018);
    WriteReg_32(DBSC_V3M_DBTR7,0x00050005);
    WriteReg_32(DBSC_V3M_DBTR8,0x0000001E);
    WriteReg_32(DBSC_V3M_DBTR9,0x00000005);
    WriteReg_32(DBSC_V3M_DBTR10,0x0000000A);
    WriteReg_32(DBSC_V3M_DBTR11,0x00000009);
    WriteReg_32(DBSC_V3M_DBTR12,0x00100010);
#if V3MSK_2GB == 0
    WriteReg_32(DBSC_V3M_DBTR13,0x000000AC);//Eagle board
#else
    WriteReg_32(DBSC_V3M_DBTR13,0x000000E7);//V3MSK board,0x000000EA -> 0x000000E7
#endif
    WriteReg_32(DBSC_V3M_DBTR14,0x00100004);
    WriteReg_32(DBSC_V3M_DBTR15,0x00040004);
    WriteReg_32(DBSC_V3M_DBTR16,0x051B0305);
    WriteReg_32(DBSC_V3M_DBTR17,0x040C0000);
    WriteReg_32(DBSC_V3M_DBTR18,0x00000200);
    WriteReg_32(DBSC_V3M_DBTR19,0x01000040);
#if V3MSK_2GB == 0
    WriteReg_32(DBSC_V3M_DBTR20,0x020000B2);//Eagle board
#else
    WriteReg_32(DBSC_V3M_DBTR20,0x020000ED);//V3MSK board
#endif
    WriteReg_32(DBSC_V3M_DBTR21,0x00040004);
    WriteReg_32(DBSC_V3M_DBBL,0x00000000);
    WriteReg_32(DBSC_V3M_DBODT0,0x00000001);
    WriteReg_32(DBSC_V3M_DBADJ0,0x00000001);
    WriteReg_32(DBSC_V3M_DBSYSCONF1,0x00000002);
    WriteReg_32(DBSC_V3M_DBDFICNT0,0x00000010);
    WriteReg_32(DBSC_V3M_DBBCAMDIS,0x00000001);
#if V3MSK_2GB == 0
    WriteReg_32(DBSC_V3M_DBSCHRW1,0x00000046);//Eagle board
#else
    WriteReg_32(DBSC_V3M_DBSCHRW1,0x0000005E);//V3MSK board
#endif
    WriteReg_32(DBSC_V3M_SCFCTST0,0x0D050C03);
    WriteReg_32(DBSC_V3M_SCFCTST1,0x0306030C);

    WriteReg_32(DBSC_V3M_DBPDLK0,0X0000A55A);
    WriteReg_32(DBSC_V3M_DBCMD,0x01000001);
    WriteReg_32(DBSC_V3M_DBCMD,0x08000000);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000001);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X80010000);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000006);
    while ( (BIT0 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 );

    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000008);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X000B8000);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000090);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X04058904);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000091);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X0007BB6D);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000095);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X0007BB6B);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000099);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X0007BB6D);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000090);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X04058900);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000021);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X0024641E);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000001);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X00010073);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000006);
    while ( (BIT0 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 );

    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000090);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X0C058900);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000090);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X04058900);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000006);
    while ( (BIT0 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 );

    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000003);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X0780C720); //0x0780C700 -> 0x0780C720
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000007);
    while ( (BIT30& ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 );

    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000004);
#if (RCAR_REF_INT == RCAR_REF_DEFAULT)	//REF 3.9usec
    #if V3MSK_2GB == 0
        WriteReg_32(DBSC_V3M_DBPDRGD0,0X07304EAB);//Eagle board,tREFI=3.9us,memory size : less than 8Gb
    #else
        WriteReg_32(DBSC_V3M_DBPDRGD0,0X07404EAB);//V3MSK board,tREFI=3.9us,memory size : 8Gb
    #endif
#elif (RCAR_REF_INT == RCAR_REF_7800)
    #if V3MSK_2GB == 0
        WriteReg_32(DBSC_V3M_DBPDRGD0,0X07309EE7);//Eagle board,tREFI=7.8us,memory size : less than 8Gb
    #else
        WriteReg_32(DBSC_V3M_DBPDRGD0,0X07409EE7);//V3MSK board,tREFI=7.8us,memory size : 8Gb
    #endif
#elif (RCAR_REF_INT == RCAR_REF_1950)
    #if V3MSK_2GB == 0
        WriteReg_32(DBSC_V3M_DBPDRGD0,0X07302309);//Eagle board,tREFI=1.95us,memory size : less than 8Gb
    #else
        WriteReg_32(DBSC_V3M_DBPDRGD0,0X07402309);//V3MSK board,tREFI=1.95us,memory size : 8Gb
    #endif
#else
    #error "Don't set out of range of RCAR_REF_INT."
#endif
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000022);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X1000040B);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000023);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X25580955);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000024);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X26873BC0);//0X268753C0 -> 0x26873BC0
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000025);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X30004200);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000026);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X0014A849);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000027);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X00000B50);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000028);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X00000004);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000029);
#if (RCAR_REF_INT == RCAR_REF_DEFAULT)	//REF 3.9usec
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X00000090);//tREFI=3.9us
#elif (RCAR_REF_INT == RCAR_REF_7800)
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X00000010);//tREFI=7.8us
#elif (RCAR_REF_INT == RCAR_REF_1950)
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X00000090);//tREFI=1.95us
#else
    #error "Don't set out of range of RCAR_REF_INT."
#endif
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X0000002C);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X81003047);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000020);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X00181884);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X0000001A);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X33C03C10);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000006);
    while ( (BIT0 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 );

    WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000A7);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X0D0D0D0D);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000A8);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X0D0D0D0D);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000A9);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X000D0D0D);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000C7);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X0D0D0D0D);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000C8);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X0D0D0D0D);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000C9);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X000D0D0D);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000E7);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X0D0D0D0D);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000E8);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X0D0D0D0D);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000E9);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X000D0D0D);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000107);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X0D0D0D0D);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000108);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X0D0D0D0D);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000109);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X000D0D0D);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000001);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X00010181);
    WriteReg_32(DBSC_V3M_DBCMD,0x08000001);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000006);
    while ( (BIT0 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 );

    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000001);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X00010601);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000006);
    while ( (BIT0 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 );

    for(i=0;i<4;i++)
    {
        WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B1 + i*0x20);
        RegVal_R5 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0x0000FF00 ) >> 8;
        WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B4 + i*0x20);
        RegVal_R6 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0x000000FF ) ;
        WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B3 + i*0x20);
        RegVal_R7 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0x00000007 ) ;
        if ( RegVal_R6 > 0 )
        {
            WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B2 + i*0x20);
            RegVal_R2 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0XFFFFFFF8 ) ;

            WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B2 + i*0x20);
            WriteReg_32(DBSC_V3M_DBPDRGD0,((RegVal_R7+1)&0X00000007) | RegVal_R2);
            WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B0 + i*0x20);
            RegVal_R2 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0XFFFFFF00 ) ;
            WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B0 + i*0x20);
            WriteReg_32(DBSC_V3M_DBPDRGD0,RegVal_R2 | RegVal_R6);
        } else
        {
            WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B2 + i*0x20);
            RegVal_R2 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0XFFFFFFF8 ) ;
            WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B2 + i*0x20);
            WriteReg_32(DBSC_V3M_DBPDRGD0,RegVal_R2 | RegVal_R7);

            WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B0 + i*0x20);
            RegVal_R2 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0XFFFFFF00 ) ;
            WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B0 + i*0x20);
            WriteReg_32(DBSC_V3M_DBPDRGD0,(((RegVal_R5<<1) + RegVal_R6 ) & 0X000000FF )| RegVal_R2);
        }
    }

    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000005);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0XC1AA00A0);
//    WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000A0);
//    WriteReg_32(DBSC_V3M_DBPDRGD0,0X7C0002C5);
//    WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000C0);
//    WriteReg_32(DBSC_V3M_DBPDRGD0,0X7C0002C5);
//    WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000E0);
//    WriteReg_32(DBSC_V3M_DBPDRGD0,0X7C0002C5);
//    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000100);
//    WriteReg_32(DBSC_V3M_DBPDRGD0,0X7C0002C5);

// PDR always off        add 2018/10/11
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000A3);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000008);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000C3);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000008);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000E3);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000008);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000103);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000008);

    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000001);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X00010801);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000006);
    while ( (BIT0 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 );

    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000005);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0XC1AA00B8);
//    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000001);
//    WriteReg_32(DBSC_V3M_DBPDRGD0,0X0001F001);
//    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000006);
//    while ( (BIT0 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 );

    WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000001);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x00011001);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000006);
    while ( (BIT0 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 );

    WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000A0);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x7C0002C5);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000C0);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x7C0002C5);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000E0);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x7C0002C5);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000100);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x7C0002C5);

// PDR default(dynamic)  add 2018/10/11
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000A3);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000000);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000C3);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000000);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000E3);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000000);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000103);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000000);

    WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000001);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x00012001);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000006);
    while ( (BIT0 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 );

    WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000A0);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x7C000285);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000C0);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x7C000285);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000E0);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x7C000285);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000100);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x7C000285);

// PDR always off        add 2018/10/11
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000A3);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000008);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000C3);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000008);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000E3);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000008);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000103);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000008);

    WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000001);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x00014001);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000006);
    while ( (BIT0 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 );

    WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000A0);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x7C0002C5);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000C0);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x7C0002C5);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000E0);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x7C0002C5);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000100);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x7C0002C5);

// PDR default(dynamic)  add 2018/10/11
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000A3);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000000);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000C3);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000000);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000E3);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000000);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000103);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000000);

    WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000001);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x00018001);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000006);
    while ( (BIT0 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 );

    WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000A0);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X7C000285);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000C0);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X7C000285);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000E0);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X7C000285);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000100);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X7C000285);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X0000002C);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X81003087);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000001);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X00010401);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000006);
    while ( (BIT0 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 );

    for (i=0;i<4;i++)
    {
        WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B1+ i*0x20);
        RegVal_R5 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0x0000FF00 ) >> 8;
        WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B4+ i*0x20);
        RegVal_R6 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0x000000FF ) ;

        WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B3+ i*0x20);
        RegVal_R7 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0x00000007 ) ;
        RegVal_R12= (RegVal_R5 >> 2 ) ;
        if ( RegVal_R6 - RegVal_R12 > 0 )
        {
            WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B2+ i*0x20);
            RegVal_R2 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0XFFFFFFF8 ) ;

            WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B2+ i*0x20);
            WriteReg_32(DBSC_V3M_DBPDRGD0,((RegVal_R7 + 1)&0X00000007) | RegVal_R2);
            WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B0+ i*0x20);
            RegVal_R2 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0XFFFFFF00 ) ;

            WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B0+ i*0x20);
            WriteReg_32(DBSC_V3M_DBPDRGD0,((RegVal_R6 - RegVal_R12)&0X000000FF) | RegVal_R2);
        } else
        {
            WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B2+ i*0x20);
            RegVal_R2 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0XFFFFFFF8 ) ;
            WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B2+ i*0x20);
            WriteReg_32(DBSC_V3M_DBPDRGD0,(RegVal_R7&0X00000007) | RegVal_R2);
            WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B0+ i*0x20);
            RegVal_R2 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0XFFFFFF00 ) ;
            WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B0+ i*0x20);
            WriteReg_32(DBSC_V3M_DBPDRGD0,((RegVal_R6 + RegVal_R5 + (RegVal_R5>>1) + RegVal_R12) & 0X000000FF) | RegVal_R2 );
        }
    }

//    WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000A0);
//    WriteReg_32(DBSC_V3M_DBPDRGD0,0X7C0002C5);
//    WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000C0);
//    WriteReg_32(DBSC_V3M_DBPDRGD0,0X7C0002C5);
//    WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000E0);
//    WriteReg_32(DBSC_V3M_DBPDRGD0,0X7C0002C5);
//    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000100);
//    WriteReg_32(DBSC_V3M_DBPDRGD0,0X7C0002C5);

// PDR always off        add 2018/10/11
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000A3);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000008);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000C3);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000008);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000E3);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000008);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000103);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000008);

    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000001);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X00015001);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000006);
    while ( (BIT0 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 );

    for (i=0; i< 4; i++) {
        WriteReg_32(DBSC_V3M_DBPDRGA0, 0x000000B0 + i * 0x20);
        dqsgd_0c = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0x000000FF);

        WriteReg_32(DBSC_V3M_DBPDRGA0, 0x000000B1 + i * 0x20);
        bdlcount_0c = ((ReadReg_32(DBSC_V3M_DBPDRGD0) & 0x0000FF00) >> 8);

        bdlcount_0c_div4  = (bdlcount_0c >> 2);
        bdlcount_0c_div8  = (bdlcount_0c >> 3);

        if (dqsgd_0c > bdlcount_0c) {
            if (dqsgd_0c <= bdlcount_0c + bdlcount_0c_div4 + bdlcount_0c_div8) {
                WriteReg_32(DBSC_V3M_DBPDRGA0, 0x000000B0 + i * 0x20);
                RegVal = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0xFFFFFF00);
                WriteReg_32(DBSC_V3M_DBPDRGD0,((dqsgd_0c - bdlcount_0c_div8) | RegVal));
            } else {
                WriteReg_32(DBSC_V3M_DBPDRGA0, 0x000000B0 + i * 0x20);
                RegVal = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0xFFFFFF00);
                WriteReg_32(DBSC_V3M_DBPDRGD0, RegVal);
                WriteReg_32(DBSC_V3M_DBPDRGA0, 0x000000B2 + i * 0x20);
                gatesl_0c = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0x00000007);
                WriteReg_32(DBSC_V3M_DBPDRGA0, 0x000000B2 + i * 0x20);
                RegVal = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0xFFFFFFF8);
                WriteReg_32(DBSC_V3M_DBPDRGD0, (RegVal|(gatesl_0c + 1)));
                WriteReg_32(DBSC_V3M_DBPDRGA0, 0x000000AF + i * 0x20);
                RegVal = (ReadReg_32(DBSC_V3M_DBPDRGD0));
                rdqsd_0c = (RegVal & 0x0000FF00) >> 8;
                rdqsnd_0c = (RegVal & 0x00FF0000) >> 16;
                WriteReg_32(DBSC_V3M_DBPDRGA0, 0x000000AF + i * 0x20);
                WriteReg_32(DBSC_V3M_DBPDRGD0, ((RegVal & 0xFF0000FF)|((rdqsd_0c + bdlcount_0c_div8) << 8)|((rdqsnd_0c + bdlcount_0c_div8) << 16)));
                WriteReg_32(DBSC_V3M_DBPDRGA0, 0x000000AA + i * 0x20);
                RegVal = (ReadReg_32(DBSC_V3M_DBPDRGD0));
                rbd_0c[0] = (RegVal      ) & 0x0000001f;
                rbd_0c[1] = (RegVal >>  8) & 0x0000001f;
                rbd_0c[2] = (RegVal >> 16) & 0x0000001f;
                rbd_0c[3] = (RegVal >> 24) & 0x0000001f;

                WriteReg_32(DBSC_V3M_DBPDRGA0, 0x000000AA + i * 0x20);
                RegVal = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0xE0E0E0E0);
                for (j=0; j< 4; j++) {
                    rbd_0c[j] = (rbd_0c[j] + bdlcount_0c_div8);
                    if (rbd_0c[j] > 0x1F) rbd_0c[j] = 0x1F;
                    RegVal = RegVal | (rbd_0c[j] <<8*j);
                }
                WriteReg_32(DBSC_V3M_DBPDRGD0, RegVal);
                WriteReg_32(DBSC_V3M_DBPDRGA0, 0x000000AB + i * 0x20);
                RegVal = (ReadReg_32(DBSC_V3M_DBPDRGD0));
                rbd_0c[0] = (RegVal      ) & 0x0000001f;
                rbd_0c[1] = (RegVal >>  8) & 0x0000001f;
                rbd_0c[2] = (RegVal >> 16) & 0x0000001f;
                rbd_0c[3] = (RegVal >> 24) & 0x0000001f;

                WriteReg_32(DBSC_V3M_DBPDRGA0, 0x000000AB + i * 0x20);
                RegVal = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0xE0E0E0E0);
                for (j=0; j< 4; j++) {
                    rbd_0c[j] = (rbd_0c[j] + bdlcount_0c_div8);
                    if (rbd_0c[j] > 0x1F) rbd_0c[j] = 0x1F;
                    RegVal = RegVal | (rbd_0c[j] <<8*j);
                }
                WriteReg_32(DBSC_V3M_DBPDRGD0, RegVal);
            }
        }
    }
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000002);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x07D81E37);

    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000003);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X0380C720); //0x0380C700 -> 0x0380C720
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000007);
    while ( (BIT30& ReadReg_32(DBSC_V3M_DBPDRGD0)) != 0 );

    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000021);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X0024643E);

    WriteReg_32(DBSC_V3M_DBBUS0CNF1,0x00000000);
#if (RCAR_REF_INT == RCAR_REF_DEFAULT)	//REF 3.9usec
    WriteReg_32(DBSC_V3M_DBCALCNF,0x0100401A);//tREFI=3.9us
    WriteReg_32(DBSC_V3M_DBRFCNF1,0x00080A07);//tREFI=3.9us
    WriteReg_32(DBSC_V3M_DBRFCNF2,0x00010000);//tREFI=3.9us
#elif (RCAR_REF_INT == RCAR_REF_7800)
    WriteReg_32(DBSC_V3M_DBCALCNF,0x0100200D);//tREFI=7.8us
    WriteReg_32(DBSC_V3M_DBRFCNF1,0x0008140E);//tREFI=7.8us, 0x0008140F => 0x0008140E
    WriteReg_32(DBSC_V3M_DBRFCNF2,0x00010000);//tREFI=7.8us
#elif (RCAR_REF_INT == RCAR_REF_1950)
    WriteReg_32(DBSC_V3M_DBCALCNF,0x0100401A);//tREFI=1.95us
    WriteReg_32(DBSC_V3M_DBRFCNF1,0x00080A07);//tREFI=1.95us
    WriteReg_32(DBSC_V3M_DBRFCNF2,0x00010001);//tREFI=1.95us
#else
    #error "Don't set out of range of RCAR_REF_INT."
#endif
    WriteReg_32(DBSC_V3M_DBDFICUPDCNF,0x40100001);
    WriteReg_32(DBSC_V3M_DBRFEN,0x00000001);
    WriteReg_32(DBSC_V3M_DBACEN,0x00000001);

    WriteReg_32(0xE67F0018,0x00000001);
    RegVal = ReadReg_32(0x40000000);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000000);
    WriteReg_32(DBSC_V3M_DBPDRGD0,RegVal);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000A0);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x7C0002C5);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000C0);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x7C0002C5);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000E0);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x7C0002C5);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000100);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x7C0002C5);

// PDR default(dynamic)  add 2018/10/11
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000A3);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000000);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000C3);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000000);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000E3);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000000);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000103);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000000);

    WriteReg_32(DBSC_V3M_DBPDLK0,0X00000000);
    WriteReg_32(DBSC_V3M_DBSYSCNT0,0x00000000);

#ifdef ddr_qos_init_setting // only for non qos_init:add 2018.01.25
    WriteReg_32(DBSC_V3M_DBSYSCNT0,0x00001234);
    WriteReg_32(DBSC_V3M_DBCAM0CNF1,0x00043218);
    WriteReg_32(DBSC_V3M_DBCAM0CNF2,0x000000F4);
    WriteReg_32(DBSC_V3M_DBSCHCNT0,0x000f0037);
    WriteReg_32(DBSC_V3M_DBSCHSZ0,0x00000001);
    WriteReg_32(DBSC_V3M_DBSCHRW0,0x22421111);
    WriteReg_32(DBSC_V3M_SCFCTST2,0x012F1123);
    WriteReg_32(DBSC_V3M_DBSCHQOS00,0x00000F00);
    WriteReg_32(DBSC_V3M_DBSCHQOS01,0x00000B00);
    WriteReg_32(DBSC_V3M_DBSCHQOS02,0x00000000);
    WriteReg_32(DBSC_V3M_DBSCHQOS03,0x00000000);
    WriteReg_32(DBSC_V3M_DBSCHQOS40,0x00000300);
    WriteReg_32(DBSC_V3M_DBSCHQOS41,0x000002F0);
    WriteReg_32(DBSC_V3M_DBSCHQOS42,0x00000200);
    WriteReg_32(DBSC_V3M_DBSCHQOS43,0x00000100);
    WriteReg_32(DBSC_V3M_DBSCHQOS90,0x00000300);
    WriteReg_32(DBSC_V3M_DBSCHQOS91,0x000002F0);
    WriteReg_32(DBSC_V3M_DBSCHQOS92,0x00000200);
    WriteReg_32(DBSC_V3M_DBSCHQOS93,0x00000100);
    WriteReg_32(DBSC_V3M_DBSCHQOS130,0x00000100);
    WriteReg_32(DBSC_V3M_DBSCHQOS131,0x000000F0);
    WriteReg_32(DBSC_V3M_DBSCHQOS132,0x000000A0);
    WriteReg_32(DBSC_V3M_DBSCHQOS133,0x00000040);
    WriteReg_32(DBSC_V3M_DBSCHQOS140,0x000000C0);
    WriteReg_32(DBSC_V3M_DBSCHQOS141,0x000000B0);
    WriteReg_32(DBSC_V3M_DBSCHQOS142,0x00000080);
    WriteReg_32(DBSC_V3M_DBSCHQOS143,0x00000040);
    WriteReg_32(DBSC_V3M_DBSCHQOS150,0x00000040);
    WriteReg_32(DBSC_V3M_DBSCHQOS151,0x00000030);
    WriteReg_32(DBSC_V3M_DBSCHQOS152,0x00000020);
    WriteReg_32(DBSC_V3M_DBSCHQOS153,0x00000010);
//    WriteReg_32(0xE67F0018,0X00000001);        //move
    WriteReg_32(DBSC_V3M_DBSYSCNT0,0x00000000);
#endif

    return 1;

}

uint32_t init_ddr_v3m1580(void)
{
    // modified last, 2018.10.11
    uint32_t RegVal_R2, RegVal_R5, RegVal_R6, RegVal_R7, RegVal_R12, i;

    uint32_t RegVal,j;
    uint32_t dqsgd_0c, bdlcount_0c, bdlcount_0c_div2, bdlcount_0c_div4, bdlcount_0c_div8, bdlcount_0c_div16;
    uint32_t gatesl_0c, rdqsd_0c, rdqsnd_0c, rbd_0c[4];

/* Initial setting ===============================================*/
    WriteReg_32(DBSC_V3M_DBSYSCNT0,0x00001234);
    WriteReg_32(DBSC_V3M_DBKIND,0x00000007);
#if V3MSK_2GB == 0
    WriteReg_32(DBSC_V3M_DBMEMCONF00,0x0f030a02);//Eagle board
#else
    WriteReg_32(DBSC_V3M_DBMEMCONF00,0x10030a02);//V3MSK board
#endif
    WriteReg_32(DBSC_V3M_DBPHYCONF0,0x00000001);
    WriteReg_32(DBSC_V3M_DBTR0,0x0000000B);
    WriteReg_32(DBSC_V3M_DBTR1,0x00000008);
    WriteReg_32(DBSC_V3M_DBTR2,0x00000000);
    WriteReg_32(DBSC_V3M_DBTR3,0x0000000B);
    WriteReg_32(DBSC_V3M_DBTR4,0x000B000B);
    WriteReg_32(DBSC_V3M_DBTR5,0x00000027);
    WriteReg_32(DBSC_V3M_DBTR6,0x0000001C);
    WriteReg_32(DBSC_V3M_DBTR7,0x00060006);
    WriteReg_32(DBSC_V3M_DBTR8,0x00000020);
    WriteReg_32(DBSC_V3M_DBTR9,0x00000006);
    WriteReg_32(DBSC_V3M_DBTR10,0x0000000C);
    WriteReg_32(DBSC_V3M_DBTR11,0x0000000A);
    WriteReg_32(DBSC_V3M_DBTR12,0x00120012);
#if V3MSK_2GB == 0
    WriteReg_32(DBSC_V3M_DBTR13,0x000000CE);//Eagle board
#else
    WriteReg_32(DBSC_V3M_DBTR13,0x00000115);//V3MSK board,0x00000116 -> 0x00000115
#endif
    WriteReg_32(DBSC_V3M_DBTR14,0x00130005);
    WriteReg_32(DBSC_V3M_DBTR15,0x00050004);
    WriteReg_32(DBSC_V3M_DBTR16,0x071F0305);
    WriteReg_32(DBSC_V3M_DBTR17,0x040C0000);
    WriteReg_32(DBSC_V3M_DBTR18,0x00000200);
    WriteReg_32(DBSC_V3M_DBTR19,0x01000040);
#if V3MSK_2GB == 0
    WriteReg_32(DBSC_V3M_DBTR20,0x020000D6);//Eagle board
#else
    WriteReg_32(DBSC_V3M_DBTR20,0x0200011D);//V3MSK board
#endif
    WriteReg_32(DBSC_V3M_DBTR21,0x00040004);
    WriteReg_32(DBSC_V3M_DBBL,0x00000000);
    WriteReg_32(DBSC_V3M_DBODT0,0x00000001);
    WriteReg_32(DBSC_V3M_DBADJ0,0x00000001);
    WriteReg_32(DBSC_V3M_DBSYSCONF1,0x00000002);
    WriteReg_32(DBSC_V3M_DBDFICNT0,0x00000010);
    WriteReg_32(DBSC_V3M_DBBCAMDIS,0x00000001);
#if V3MSK_2GB == 0
    WriteReg_32(DBSC_V3M_DBSCHRW1,0x00000046);//Eagle board
#else
    WriteReg_32(DBSC_V3M_DBSCHRW1,0x0000005E);//V3MSK board
#endif
    WriteReg_32(DBSC_V3M_SCFCTST0,0x0D050B03);
    WriteReg_32(DBSC_V3M_SCFCTST1,0x0306030C);

    WriteReg_32(DBSC_V3M_DBPDLK0,0X0000A55A);
    WriteReg_32(DBSC_V3M_DBCMD,0x01000001);
    WriteReg_32(DBSC_V3M_DBCMD,0x08000000);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000001);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X80010000);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000006);
    while ( (BIT0 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 );

    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000008);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X000B8000);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000090);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X04058904);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000091);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X0007BB6D);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000095);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X0007BB6B);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000099);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X0007BB6D);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000090);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X04058900);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000021);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X0024641E);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000001);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X00010073);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000006);
    while ( (BIT0 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 );

    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000090);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X0C058900);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000090);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X04058900);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000006);
    while ( (BIT0 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 );

    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000003);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X0780C720); //0x0780C700 -> 0x0780C720
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000007);
    while ( (BIT30& ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 );

    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000004);
#if (RCAR_REF_INT == RCAR_REF_DEFAULT)	//REF 3.9usec
    #if V3MSK_2GB == 0
        WriteReg_32(DBSC_V3M_DBPDRGD0,0X08A05EB8);//Eagle board,tREFI=3.9us,memory size : less than 8Gb
    #else
        WriteReg_32(DBSC_V3M_DBPDRGD0,0X08B05EB8);//V3MSK board,tREFI=3.9us,memory size : 8Gb
    #endif
#elif (RCAR_REF_INT == RCAR_REF_7800)
    #if V3MSK_2GB == 0
        WriteReg_32(DBSC_V3M_DBPDRGD0,0X08A0BF00);//Eagle board,tREFI=7.8us,memory size : less than 8Gb
    #else
        WriteReg_32(DBSC_V3M_DBPDRGD0,0X08B0BF00);//V3MSK board,tREFI=7.8us,memory size : 8Gb
    #endif
#elif (RCAR_REF_INT == RCAR_REF_1950)
    #if V3MSK_2GB == 0
        WriteReg_32(DBSC_V3M_DBPDRGD0,0X08A02B10);//Eagle board,tREFI=1.95us,memory size : less than 8Gb
    #else
        WriteReg_32(DBSC_V3M_DBPDRGD0,0X08B02B10);//V3MSK board,tREFI=1.95us,memory size : 8Gb
    #endif
#else
    #error "Don't set out of range of RCAR_REF_INT."
#endif
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000022);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X1000040B);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000023);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X2D9C0B66);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000024);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X2A88AC00);//0x2A88B400 -> 0x2A88AC00
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000025);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X30004E00);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000026);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X0014A9C9);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000027);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X00000D70);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000028);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X00000004);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000029);
#if (RCAR_REF_INT == RCAR_REF_DEFAULT)	//REF 3.9usec
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X00000098);//tREFI=3.9us
#elif (RCAR_REF_INT == RCAR_REF_7800)
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X00000018); //tREFI=7.8us
#elif (RCAR_REF_INT == RCAR_REF_1950)
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X00000098);//tREFI=1.95us
#else
    #error "Don't set out of range of RCAR_REF_INT."
#endif
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X0000002C);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X81003047);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000020);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X00181884);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X0000001A);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X33C03C10);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000006);
    while ( (BIT0 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 );

    WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000A7);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X0D0D0D0D);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000A8);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X0D0D0D0D);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000A9);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X000D0D0D);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000C7);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X0D0D0D0D);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000C8);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X0D0D0D0D);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000C9);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X000D0D0D);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000E7);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X0D0D0D0D);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000E8);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X0D0D0D0D);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000E9);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X000D0D0D);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000107);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X0D0D0D0D);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000108);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X0D0D0D0D);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000109);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X000D0D0D);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000001);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X00010181);
    WriteReg_32(DBSC_V3M_DBCMD,0x08000001);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000006);
    while ( (BIT0 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 );

    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000001);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X00010601);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000006);
    while ( (BIT0 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 );

    for (i=0;i<4;i++)
    {
        WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B1 + i*0x20);
        RegVal_R5 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0x0000FF00 ) >> 8;
        WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B4 + i*0x20);
        RegVal_R6 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0x000000FF ) ;
        WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B3 + i*0x20);
        RegVal_R7 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0x00000007 ) ;
        if ( RegVal_R6 > 0 )
        {
            WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B2 + i*0x20);
            RegVal_R2 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0XFFFFFFF8 ) ;

            WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B2 + i*0x20);
            WriteReg_32(DBSC_V3M_DBPDRGD0,((RegVal_R7+1)&0X00000007) | RegVal_R2);
            WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B0 + i*0x20);
            RegVal_R2 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0XFFFFFF00 ) ;
            WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B0 + i*0x20);
            WriteReg_32(DBSC_V3M_DBPDRGD0,RegVal_R2 | RegVal_R6);
        } else
        {
            WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B2 + i*0x20);
            RegVal_R2 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0XFFFFFFF8 ) ;
            WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B2 + i*0x20);
            WriteReg_32(DBSC_V3M_DBPDRGD0,RegVal_R2 | RegVal_R7);

            WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B0 + i*0x20);
            RegVal_R2 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0XFFFFFF00 ) ;
            WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B0 + i*0x20);
            WriteReg_32(DBSC_V3M_DBPDRGD0,(((RegVal_R5<<1) + RegVal_R6 ) & 0X000000FF )| RegVal_R2);
        }
    }

    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000005);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0XC1AA00C0);
//    WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000A0);
//    WriteReg_32(DBSC_V3M_DBPDRGD0,0X7C0002C5);
//    WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000C0);
//    WriteReg_32(DBSC_V3M_DBPDRGD0,0X7C0002C5);
//    WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000E0);
//    WriteReg_32(DBSC_V3M_DBPDRGD0,0X7C0002C5);
//    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000100);
//    WriteReg_32(DBSC_V3M_DBPDRGD0,0X7C0002C5);

// PDR always off        add 2018/10/11
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000A3);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000008);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000C3);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000008);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000E3);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000008);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000103);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000008);

    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000001);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X00010801);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000006);
    while ( (BIT0 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 );

    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000005);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0XC1AA00D8);
//    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000001);
//    WriteReg_32(DBSC_V3M_DBPDRGD0,0X0001F001);
//    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000006);
//    while ( (BIT0 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 );

    WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000001);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x00011001);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000006);
    while ( (BIT0 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 );

    WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000A0);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x7C0002C5);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000C0);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x7C0002C5);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000E0);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x7C0002C5);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000100);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x7C0002C5);

// PDR default(dynamic)  add 2018/10/11
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000A3);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000000);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000C3);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000000);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000E3);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000000);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000103);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000000);

    WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000001);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x00012001);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000006);
    while ( (BIT0 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 );

    WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000A0);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x7C000285);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000C0);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x7C000285);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000E0);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x7C000285);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000100);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x7C000285);

// PDR always off        add 2018/10/11
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000A3);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000008);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000C3);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000008);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000E3);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000008);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000103);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000008);

    WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000001);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x00014001);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000006);
    while ( (BIT0 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 );

    WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000A0);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x7C0002C5);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000C0);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x7C0002C5);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000E0);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x7C0002C5);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000100);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x7C0002C5);

// PDR default(dynamic)  add 2018/10/11
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000A3);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000000);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000C3);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000000);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000E3);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000000);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000103);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000000);

    WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000001);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x00018001);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000006);
    while ( (BIT0 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 );

    WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000A0);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X7C000285);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000C0);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X7C000285);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000E0);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X7C000285);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000100);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X7C000285);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X0000002C);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X81003087);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000001);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X00010401);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000006);
    while ( (BIT0 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 );

    for (i=0;i<4;i++)
    {
        WriteReg_32(DBSC_V3M_DBPDRGA0, 0X000000B1 + i * 0x20);
        RegVal_R5 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0x0000FF00) >> 8;
        WriteReg_32(DBSC_V3M_DBPDRGA0, 0X000000B4 + i * 0x20);
        RegVal_R6 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0x000000FF);

        WriteReg_32(DBSC_V3M_DBPDRGA0, 0X000000B3 + i * 0x20);
        RegVal_R7 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0x00000007);
        RegVal_R12 = (RegVal_R5 >> 2);
        if (RegVal_R6 - RegVal_R12 > 0)
        {
            WriteReg_32(DBSC_V3M_DBPDRGA0, 0X000000B2 + i * 0x20);
            RegVal_R2 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0XFFFFFFF8);

            WriteReg_32(DBSC_V3M_DBPDRGA0, 0X000000B2 + i * 0x20);
            WriteReg_32(DBSC_V3M_DBPDRGD0, ((RegVal_R7 + 1) & 0X00000007) | RegVal_R2);
            WriteReg_32(DBSC_V3M_DBPDRGA0, 0X000000B0 + i * 0x20);
            RegVal_R2 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0XFFFFFF00);

            WriteReg_32(DBSC_V3M_DBPDRGA0, 0X000000B0 + i * 0x20);
            WriteReg_32(DBSC_V3M_DBPDRGD0, ((RegVal_R6 - RegVal_R12) & 0X000000FF) | RegVal_R2);
        }
        else
        {
            WriteReg_32(DBSC_V3M_DBPDRGA0, 0X000000B2 + i * 0x20);
            RegVal_R2 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0XFFFFFFF8);
            WriteReg_32(DBSC_V3M_DBPDRGA0, 0X000000B2 + i * 0x20);
            WriteReg_32(DBSC_V3M_DBPDRGD0, (RegVal_R7 & 0X00000007) | RegVal_R2);
            WriteReg_32(DBSC_V3M_DBPDRGA0, 0X000000B0 + i * 0x20);
            RegVal_R2 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0XFFFFFF00);
            WriteReg_32(DBSC_V3M_DBPDRGA0, 0X000000B0 + i * 0x20);
            WriteReg_32(DBSC_V3M_DBPDRGD0, ((RegVal_R6 + RegVal_R5 + (RegVal_R5 >> 1) + RegVal_R12) & 0X000000FF) | RegVal_R2);
        }
    }

//    WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000A0);
//    WriteReg_32(DBSC_V3M_DBPDRGD0,0X7C0002C5);
//    WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000C0);
//    WriteReg_32(DBSC_V3M_DBPDRGD0,0X7C0002C5);
//    WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000E0);
//    WriteReg_32(DBSC_V3M_DBPDRGD0,0X7C0002C5);
//    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000100);
//    WriteReg_32(DBSC_V3M_DBPDRGD0,0X7C0002C5);

// PDR always off        add 2018/10/11
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000A3);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000008);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000C3);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000008);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000E3);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000008);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000103);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000008);

    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000001);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X00015001);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000006);
    while ( (BIT0 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 );

    for (i=0; i< 4; i++) {
        WriteReg_32(DBSC_V3M_DBPDRGA0, 0x000000B0 + i * 0x20);
        dqsgd_0c = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0x000000FF);

        WriteReg_32(DBSC_V3M_DBPDRGA0, 0x000000B1 + i * 0x20);
        bdlcount_0c = ((ReadReg_32(DBSC_V3M_DBPDRGD0) & 0x0000FF00) >> 8);

        bdlcount_0c_div2  = (bdlcount_0c >> 1);
        bdlcount_0c_div4  = (bdlcount_0c >> 2);
        bdlcount_0c_div8  = (bdlcount_0c >> 3);
        bdlcount_0c_div16 = (bdlcount_0c >> 4);

        if (dqsgd_0c > bdlcount_0c_div2 + bdlcount_0c_div4 + bdlcount_0c_div8) {
            if (dqsgd_0c <= bdlcount_0c + bdlcount_0c_div4 + bdlcount_0c_div16) {
                WriteReg_32(DBSC_V3M_DBPDRGA0, 0x000000B0 + i * 0x20);
                RegVal = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0xFFFFFF00);
                WriteReg_32(DBSC_V3M_DBPDRGD0,((dqsgd_0c - bdlcount_0c_div8) | RegVal));
            } else {
                WriteReg_32(DBSC_V3M_DBPDRGA0, 0x000000B0 + i * 0x20);
                RegVal = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0xFFFFFF00);
                WriteReg_32(DBSC_V3M_DBPDRGD0, RegVal);
                WriteReg_32(DBSC_V3M_DBPDRGA0, 0x000000B2 + i * 0x20);
                gatesl_0c = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0x00000007);
                WriteReg_32(DBSC_V3M_DBPDRGA0, 0x000000B2 + i * 0x20);
                RegVal = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0xFFFFFFF8);
                WriteReg_32(DBSC_V3M_DBPDRGD0, (RegVal|(gatesl_0c + 1)));
                WriteReg_32(DBSC_V3M_DBPDRGA0, 0x000000AF + i * 0x20);
                RegVal = (ReadReg_32(DBSC_V3M_DBPDRGD0));
                rdqsd_0c = (RegVal & 0x0000FF00) >> 8;
                rdqsnd_0c = (RegVal & 0x00FF0000) >> 16;
                WriteReg_32(DBSC_V3M_DBPDRGA0, 0x000000AF + i * 0x20);
                WriteReg_32(DBSC_V3M_DBPDRGD0, ((RegVal & 0xFF0000FF)|((rdqsd_0c + bdlcount_0c_div4) << 8)|((rdqsnd_0c + bdlcount_0c_div4) << 16)));
                WriteReg_32(DBSC_V3M_DBPDRGA0, 0x000000AA + i * 0x20);
                RegVal = (ReadReg_32(DBSC_V3M_DBPDRGD0));
                rbd_0c[0] = (RegVal      ) & 0x0000001f;
                rbd_0c[1] = (RegVal >>  8) & 0x0000001f;
                rbd_0c[2] = (RegVal >> 16) & 0x0000001f;
                rbd_0c[3] = (RegVal >> 24) & 0x0000001f;

                WriteReg_32(DBSC_V3M_DBPDRGA0, 0x000000AA + i * 0x20);
                RegVal = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0xE0E0E0E0);
                for (j=0; j< 4; j++) {
                    rbd_0c[j] = (rbd_0c[j] + bdlcount_0c_div4);
                    if (rbd_0c[j] > 0x1F) rbd_0c[j] = 0x1F;
                    RegVal = RegVal | (rbd_0c[j] <<8*j);
                }
                WriteReg_32(DBSC_V3M_DBPDRGD0, RegVal);
                WriteReg_32(DBSC_V3M_DBPDRGA0, 0x000000AB + i * 0x20);
                RegVal = (ReadReg_32(DBSC_V3M_DBPDRGD0));
                rbd_0c[0] = (RegVal      ) & 0x0000001f;
                rbd_0c[1] = (RegVal >>  8) & 0x0000001f;
                rbd_0c[2] = (RegVal >> 16) & 0x0000001f;
                rbd_0c[3] = (RegVal >> 24) & 0x0000001f;

                WriteReg_32(DBSC_V3M_DBPDRGA0, 0x000000AB + i * 0x20);
                RegVal = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0xE0E0E0E0);
                for (j=0; j< 4; j++) {
                    rbd_0c[j] = (rbd_0c[j] + bdlcount_0c_div4);
                    if (rbd_0c[j] > 0x1F) rbd_0c[j] = 0x1F;
                    RegVal = RegVal | (rbd_0c[j] <<8*j);
                }
                WriteReg_32(DBSC_V3M_DBPDRGD0, RegVal);
            }
        }
    }
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000002);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x07D81E37);

    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000003);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X0380C720); //0x0380C700 -> 0x0380C720
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000007);
    while ( (BIT30& ReadReg_32(DBSC_V3M_DBPDRGD0)) != 0 );

    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000021);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X0024643E);

    WriteReg_32(DBSC_V3M_DBBUS0CNF1,0x00000000);
#if (RCAR_REF_INT == RCAR_REF_DEFAULT)	//REF 3.9usec
    WriteReg_32(DBSC_V3M_DBCALCNF,0x0100401A); //tREFI=3.9us
    WriteReg_32(DBSC_V3M_DBRFCNF1,0x00080C09); //tREFI=3.9us
    WriteReg_32(DBSC_V3M_DBRFCNF2,0x00010000); //tREFI=3.9us
#elif (RCAR_REF_INT == RCAR_REF_7800)
    WriteReg_32(DBSC_V3M_DBCALCNF,0x0100200D); //tREFI=7.8us
    WriteReg_32(DBSC_V3M_DBRFCNF1,0x00081812); //tREFI=7.8us
    WriteReg_32(DBSC_V3M_DBRFCNF2,0x00010000); //tREFI=7.8us
#elif (RCAR_REF_INT == RCAR_REF_1950)
    WriteReg_32(DBSC_V3M_DBCALCNF,0x0100401A); //tREFI=1.95us
    WriteReg_32(DBSC_V3M_DBRFCNF1,0x00080C09);//tREFI=1.95us
    WriteReg_32(DBSC_V3M_DBRFCNF2,0x00010001);//tREFI=1.95us
#else
    #error "Don't set out of range of RCAR_REF_INT."
#endif
    WriteReg_32(DBSC_V3M_DBDFICUPDCNF,0x40100001);
    WriteReg_32(DBSC_V3M_DBRFEN,0x00000001);
    WriteReg_32(DBSC_V3M_DBACEN,0x00000001);

    WriteReg_32(0xE67F0018,0x00000001);
    RegVal = ReadReg_32(0x40000000);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000000);
    WriteReg_32(DBSC_V3M_DBPDRGD0,RegVal);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000A0);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x7C0002C5);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000C0);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x7C0002C5);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000E0);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x7C0002C5);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000100);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x7C0002C5);

// PDR default(dynamic)  add 2018/10/11
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000A3);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000000);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000C3);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000000);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000E3);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000000);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000103);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000000);

    WriteReg_32(DBSC_V3M_DBPDLK0,0X00000000);
    WriteReg_32(DBSC_V3M_DBSYSCNT0,0x00000000);

#ifdef ddr_qos_init_setting // only for non qos_init:add 2018.01.25
    WriteReg_32(DBSC_V3M_DBSYSCNT0,0x00001234);
    WriteReg_32(DBSC_V3M_DBCAM0CNF1,0x00043218);
    WriteReg_32(DBSC_V3M_DBCAM0CNF2,0x000000F4);
    WriteReg_32(DBSC_V3M_DBSCHCNT0,0x000f0037);
    WriteReg_32(DBSC_V3M_DBSCHSZ0,0x00000001);
    WriteReg_32(DBSC_V3M_DBSCHRW0,0x22421111);
    WriteReg_32(DBSC_V3M_SCFCTST2,0x012F1123);
    WriteReg_32(DBSC_V3M_DBSCHQOS00,0x00000F00);
    WriteReg_32(DBSC_V3M_DBSCHQOS01,0x00000B00);
    WriteReg_32(DBSC_V3M_DBSCHQOS02,0x00000000);
    WriteReg_32(DBSC_V3M_DBSCHQOS03,0x00000000);
    WriteReg_32(DBSC_V3M_DBSCHQOS40,0x00000300);
    WriteReg_32(DBSC_V3M_DBSCHQOS41,0x000002F0);
    WriteReg_32(DBSC_V3M_DBSCHQOS42,0x00000200);
    WriteReg_32(DBSC_V3M_DBSCHQOS43,0x00000100);
    WriteReg_32(DBSC_V3M_DBSCHQOS90,0x00000300);
    WriteReg_32(DBSC_V3M_DBSCHQOS91,0x000002F0);
    WriteReg_32(DBSC_V3M_DBSCHQOS92,0x00000200);
    WriteReg_32(DBSC_V3M_DBSCHQOS93,0x00000100);
    WriteReg_32(DBSC_V3M_DBSCHQOS130,0x00000100);
    WriteReg_32(DBSC_V3M_DBSCHQOS131,0x000000F0);
    WriteReg_32(DBSC_V3M_DBSCHQOS132,0x000000A0);
    WriteReg_32(DBSC_V3M_DBSCHQOS133,0x00000040);
    WriteReg_32(DBSC_V3M_DBSCHQOS140,0x000000C0);
    WriteReg_32(DBSC_V3M_DBSCHQOS141,0x000000B0);
    WriteReg_32(DBSC_V3M_DBSCHQOS142,0x00000080);
    WriteReg_32(DBSC_V3M_DBSCHQOS143,0x00000040);
    WriteReg_32(DBSC_V3M_DBSCHQOS150,0x00000040);
    WriteReg_32(DBSC_V3M_DBSCHQOS151,0x00000030);
    WriteReg_32(DBSC_V3M_DBSCHQOS152,0x00000020);
    WriteReg_32(DBSC_V3M_DBSCHQOS153,0x00000010);
//    WriteReg_32(0xE67F0018,0X00000001);        //move
    WriteReg_32(DBSC_V3M_DBSYSCNT0,0x00000000);
#endif

    return 1;

}

uint32_t init_ddr_v3m1320(void)
{
    // modified last, 2018.10.11
    uint32_t RegVal_R2, RegVal_R5, RegVal_R6, RegVal_R7, RegVal_R12, i;

    uint32_t RegVal,j;
    uint32_t dqsgd_0c, bdlcount_0c, bdlcount_0c_div4, bdlcount_0c_div8;
    uint32_t gatesl_0c, rdqsd_0c, rdqsnd_0c, rbd_0c[4];

/* Initial setting ===============================================*/
    WriteReg_32(DBSC_V3M_DBSYSCNT0,0x00001234);
    WriteReg_32(DBSC_V3M_DBKIND,0x00000007);
#if V3MSK_2GB == 0
    WriteReg_32(DBSC_V3M_DBMEMCONF00,0x0f030a02);//Eagle board
#else
    WriteReg_32(DBSC_V3M_DBMEMCONF00,0x10030a02);//V3MSK board
#endif
    WriteReg_32(DBSC_V3M_DBPHYCONF0,0x00000001);
    WriteReg_32(DBSC_V3M_DBTR0,0x00000009);
    WriteReg_32(DBSC_V3M_DBTR1,0x00000007);
    WriteReg_32(DBSC_V3M_DBTR2,0x00000000);
    WriteReg_32(DBSC_V3M_DBTR3,0x00000009);
    WriteReg_32(DBSC_V3M_DBTR4,0x00090009);
    WriteReg_32(DBSC_V3M_DBTR5,0x00000021);
    WriteReg_32(DBSC_V3M_DBTR6,0x00000018);
    WriteReg_32(DBSC_V3M_DBTR7,0x00050005);
    WriteReg_32(DBSC_V3M_DBTR8,0x0000001E);
    WriteReg_32(DBSC_V3M_DBTR9,0x00000005);
    WriteReg_32(DBSC_V3M_DBTR10,0x0000000A);
    WriteReg_32(DBSC_V3M_DBTR11,0x00000009);
    WriteReg_32(DBSC_V3M_DBTR12,0x00100010);
#if V3MSK_2GB == 0
    WriteReg_32(DBSC_V3M_DBTR13,0x000000AC);//Eagle board
#else
    WriteReg_32(DBSC_V3M_DBTR13,0x000000E7);//V3MSK board
#endif
    WriteReg_32(DBSC_V3M_DBTR14,0x00100004);
    WriteReg_32(DBSC_V3M_DBTR15,0x00040004);
    WriteReg_32(DBSC_V3M_DBTR16,0x051B0305);
    WriteReg_32(DBSC_V3M_DBTR17,0x040C0000);
    WriteReg_32(DBSC_V3M_DBTR18,0x00000200);
    WriteReg_32(DBSC_V3M_DBTR19,0x01000040);
#if V3MSK_2GB == 0
    WriteReg_32(DBSC_V3M_DBTR20,0x020000B3);//Eagle board
#else
    WriteReg_32(DBSC_V3M_DBTR20,0x020000EE);//V3MSK board
#endif
    WriteReg_32(DBSC_V3M_DBTR21,0x00040004);
    WriteReg_32(DBSC_V3M_DBBL,0x00000000);
    WriteReg_32(DBSC_V3M_DBODT0,0x00000001);
    WriteReg_32(DBSC_V3M_DBADJ0,0x00000001);
    WriteReg_32(DBSC_V3M_DBSYSCONF1,0x00000002);
    WriteReg_32(DBSC_V3M_DBDFICNT0,0x00000010);
    WriteReg_32(DBSC_V3M_DBBCAMDIS,0x00000001);
#if V3MSK_2GB == 0
    WriteReg_32(DBSC_V3M_DBSCHRW1,0x00000046);//Eagle board
#else
    WriteReg_32(DBSC_V3M_DBSCHRW1,0x0000005E);//V3MSK board
#endif
    WriteReg_32(DBSC_V3M_SCFCTST0,0x0D050C03);
    WriteReg_32(DBSC_V3M_SCFCTST1,0x0306030C);

    WriteReg_32(DBSC_V3M_DBPDLK0,0X0000A55A);
    WriteReg_32(DBSC_V3M_DBCMD,0x01000001);
    WriteReg_32(DBSC_V3M_DBCMD,0x08000000);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000001);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X80010000);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000006);
    while ( (BIT0 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 );

    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000008);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X000B8000);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000090);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X04058904);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000091);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X0007BB6D);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000095);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X0007BB6B);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000099);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X0007BB6D);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000090);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X04058900);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000021);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X0024641E);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000001);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X00010073);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000006);
    while ( (BIT0 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 );

    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000090);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X0C058900);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000090);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X04058900);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000006);
    while ( (BIT0 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 );

    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000003);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X0780C720); //0x0780C700 -> 0x0780C720
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000007);
    while ( (BIT30& ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 );

    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000004);
#if (RCAR_REF_INT == RCAR_REF_DEFAULT)	//REF 3.9usec
    #if V3MSK_2GB == 0
        WriteReg_32(DBSC_V3M_DBPDRGD0,0X07304EE0);//Eagle board,tREFI=3.9us,memory size : less than 8Gb
    #else
        WriteReg_32(DBSC_V3M_DBPDRGD0,0X07404EE0);//V3MSK board,tREFI=3.9us,memory size : 8Gb
    #endif
#elif (RCAR_REF_INT == RCAR_REF_7800)
    #if V3MSK_2GB == 0
        WriteReg_32(DBSC_V3M_DBPDRGD0,0X07309F50);//Eagle board,tREFI=7.8us,memory size : less than 8Gb
    #else
        WriteReg_32(DBSC_V3M_DBPDRGD0,0X07409F50);//V3MSK board,tREFI=7.8us,memory size : 8Gb
    #endif
#elif (RCAR_REF_INT == RCAR_REF_1950)
    #if V3MSK_2GB == 0
        WriteReg_32(DBSC_V3M_DBPDRGD0,0X07302324);//Eagle board,tREFI=1.95us,memory size : less than 8Gb
    #else
        WriteReg_32(DBSC_V3M_DBPDRGD0,0X07402324);//V3MSK board,tREFI=1.95us,memory size : 8Gb
    #endif
#else
    #error "Don't set out of range of RCAR_REF_INT."
#endif
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000022);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X1000040B);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000023);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X25580955);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000024);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X26873BC0);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000025);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X30004200);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000026);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X0014A849);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000027);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X00000B50);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000028);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X00000004);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000029);
#if (RCAR_REF_INT == RCAR_REF_DEFAULT)	//REF 3.9usec
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X00000090);//tREFI=3.9us
#elif (RCAR_REF_INT == RCAR_REF_7800)
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X00000010);//tREFI=7.8us
#elif (RCAR_REF_INT == RCAR_REF_1950)
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X00000090);//tREFI=1.95us
#else
    #error "Don't set out of range of RCAR_REF_INT."
#endif
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X0000002C);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X81003047);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000020);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X00181884);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X0000001A);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X33C03C10);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000006);
    while ( (BIT0 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 );

    WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000A7);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X0D0D0D0D);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000A8);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X0D0D0D0D);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000A9);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X000D0D0D);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000C7);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X0D0D0D0D);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000C8);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X0D0D0D0D);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000C9);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X000D0D0D);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000E7);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X0D0D0D0D);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000E8);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X0D0D0D0D);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000E9);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X000D0D0D);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000107);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X0D0D0D0D);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000108);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X0D0D0D0D);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000109);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X000D0D0D);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000001);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X00010181);
    WriteReg_32(DBSC_V3M_DBCMD,0x08000001);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000006);
    while ( (BIT0 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 );

    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000001);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X00010601);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000006);
    while ( (BIT0 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 );

    for(i=0;i<4;i++)
    {
        WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B1 + i*0x20);
        RegVal_R5 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0x0000FF00 ) >> 8;
        WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B4 + i*0x20);
        RegVal_R6 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0x000000FF ) ;
        WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B3 + i*0x20);
        RegVal_R7 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0x00000007 ) ;
        if ( RegVal_R6 > 0 )
        {
            WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B2 + i*0x20);
            RegVal_R2 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0XFFFFFFF8 ) ;

            WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B2 + i*0x20);
            WriteReg_32(DBSC_V3M_DBPDRGD0,((RegVal_R7+1)&0X00000007) | RegVal_R2);
            WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B0 + i*0x20);
            RegVal_R2 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0XFFFFFF00 ) ;
            WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B0 + i*0x20);
            WriteReg_32(DBSC_V3M_DBPDRGD0,RegVal_R2 | RegVal_R6);
        } else
        {
            WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B2 + i*0x20);
            RegVal_R2 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0XFFFFFFF8 ) ;
            WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B2 + i*0x20);
            WriteReg_32(DBSC_V3M_DBPDRGD0,RegVal_R2 | RegVal_R7);

            WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B0 + i*0x20);
            RegVal_R2 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0XFFFFFF00 ) ;
            WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B0 + i*0x20);
            WriteReg_32(DBSC_V3M_DBPDRGD0,(((RegVal_R5<<1) + RegVal_R6 ) & 0X000000FF )| RegVal_R2);
        }
    }

    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000005);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0XC1AA00A0);
//    WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000A0);
//    WriteReg_32(DBSC_V3M_DBPDRGD0,0X7C0002C5);
//    WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000C0);
//    WriteReg_32(DBSC_V3M_DBPDRGD0,0X7C0002C5);
//    WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000E0);
//    WriteReg_32(DBSC_V3M_DBPDRGD0,0X7C0002C5);
//    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000100);
//    WriteReg_32(DBSC_V3M_DBPDRGD0,0X7C0002C5);

// PDR always off        add 2018/10/11
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000A3);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000008);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000C3);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000008);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000E3);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000008);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000103);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000008);

    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000001);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X00010801);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000006);
    while ( (BIT0 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 );

    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000005);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0XC1AA00B8);
//    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000001);
//    WriteReg_32(DBSC_V3M_DBPDRGD0,0X0001F001);
//    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000006);
//    while ( (BIT0 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 );

    WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000001);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x00011001);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000006);
    while ( (BIT0 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 );

    WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000A0);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x7C0002C5);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000C0);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x7C0002C5);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000E0);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x7C0002C5);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000100);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x7C0002C5);

// PDR default(dynamic)  add 2018/10/11
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000A3);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000000);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000C3);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000000);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000E3);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000000);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000103);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000000);

    WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000001);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x00012001);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000006);
    while ( (BIT0 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 );

    WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000A0);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x7C000285);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000C0);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x7C000285);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000E0);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x7C000285);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000100);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x7C000285);

// PDR always off        add 2018/10/11
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000A3);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000008);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000C3);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000008);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000E3);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000008);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000103);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000008);

    WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000001);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x00014001);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000006);
    while ( (BIT0 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 );

    WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000A0);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x7C0002C5);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000C0);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x7C0002C5);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000E0);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x7C0002C5);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000100);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x7C0002C5);

// PDR default(dynamic)  add 2018/10/11
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000A3);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000000);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000C3);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000000);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000E3);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000000);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000103);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000000);

    WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000001);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x00018001);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000006);
    while ( (BIT0 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 );

    WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000A0);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X7C000285);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000C0);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X7C000285);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000E0);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X7C000285);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000100);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X7C000285);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X0000002C);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X81003087);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000001);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X00010401);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000006);
    while ( (BIT0 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 );

    for (i=0;i<4;i++)
    {
        WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B1+ i*0x20);
        RegVal_R5 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0x0000FF00 ) >> 8;
        WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B4+ i*0x20);
        RegVal_R6 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0x000000FF ) ;

        WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B3+ i*0x20);
        RegVal_R7 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0x00000007 ) ;
        RegVal_R12= (RegVal_R5 >> 2 ) ;
        if ( RegVal_R6 - RegVal_R12 > 0 )
        {
            WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B2+ i*0x20);
            RegVal_R2 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0XFFFFFFF8 ) ;

            WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B2+ i*0x20);
            WriteReg_32(DBSC_V3M_DBPDRGD0,((RegVal_R7 + 1)&0X00000007) | RegVal_R2);
            WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B0+ i*0x20);
            RegVal_R2 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0XFFFFFF00 ) ;

            WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B0+ i*0x20);
            WriteReg_32(DBSC_V3M_DBPDRGD0,((RegVal_R6 - RegVal_R12)&0X000000FF) | RegVal_R2);
        } else
        {
            WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B2+ i*0x20);
            RegVal_R2 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0XFFFFFFF8 ) ;
            WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B2+ i*0x20);
            WriteReg_32(DBSC_V3M_DBPDRGD0,(RegVal_R7&0X00000007) | RegVal_R2);
            WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B0+ i*0x20);
            RegVal_R2 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0XFFFFFF00 ) ;
            WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B0+ i*0x20);
            WriteReg_32(DBSC_V3M_DBPDRGD0,((RegVal_R6 + RegVal_R5 + (RegVal_R5>>1) + RegVal_R12) & 0X000000FF) | RegVal_R2 );
        }
    }

//    WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000A0);
//    WriteReg_32(DBSC_V3M_DBPDRGD0,0X7C0002C5);
//    WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000C0);
//    WriteReg_32(DBSC_V3M_DBPDRGD0,0X7C0002C5);
//    WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000E0);
//    WriteReg_32(DBSC_V3M_DBPDRGD0,0X7C0002C5);
//    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000100);
//    WriteReg_32(DBSC_V3M_DBPDRGD0,0X7C0002C5);

// PDR always off        add 2018/10/11
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000A3);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000008);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000C3);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000008);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000E3);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000008);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000103);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000008);

    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000001);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X00015001);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000006);
    while ( (BIT0 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 );

    for (i=0; i< 4; i++) {
        WriteReg_32(DBSC_V3M_DBPDRGA0, 0x000000B0 + i * 0x20);
        dqsgd_0c = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0x000000FF);

        WriteReg_32(DBSC_V3M_DBPDRGA0, 0x000000B1 + i * 0x20);
        bdlcount_0c = ((ReadReg_32(DBSC_V3M_DBPDRGD0) & 0x0000FF00) >> 8);

        bdlcount_0c_div4  = (bdlcount_0c >> 2);
        bdlcount_0c_div8  = (bdlcount_0c >> 3);

        if (dqsgd_0c > bdlcount_0c) {
            if (dqsgd_0c <= bdlcount_0c + bdlcount_0c_div4 + bdlcount_0c_div8) {
                WriteReg_32(DBSC_V3M_DBPDRGA0, 0x000000B0 + i * 0x20);
                RegVal = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0xFFFFFF00);
                WriteReg_32(DBSC_V3M_DBPDRGD0,((dqsgd_0c - bdlcount_0c_div8) | RegVal));
            } else {
                WriteReg_32(DBSC_V3M_DBPDRGA0, 0x000000B0 + i * 0x20);
                RegVal = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0xFFFFFF00);
                WriteReg_32(DBSC_V3M_DBPDRGD0, RegVal);
                WriteReg_32(DBSC_V3M_DBPDRGA0, 0x000000B2 + i * 0x20);
                gatesl_0c = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0x00000007);
                WriteReg_32(DBSC_V3M_DBPDRGA0, 0x000000B2 + i * 0x20);
                RegVal = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0xFFFFFFF8);
                WriteReg_32(DBSC_V3M_DBPDRGD0, (RegVal|(gatesl_0c + 1)));
                WriteReg_32(DBSC_V3M_DBPDRGA0, 0x000000AF + i * 0x20);
                RegVal = (ReadReg_32(DBSC_V3M_DBPDRGD0));
                rdqsd_0c = (RegVal & 0x0000FF00) >> 8;
                rdqsnd_0c = (RegVal & 0x00FF0000) >> 16;
                WriteReg_32(DBSC_V3M_DBPDRGA0, 0x000000AF + i * 0x20);
                WriteReg_32(DBSC_V3M_DBPDRGD0, ((RegVal & 0xFF0000FF)|((rdqsd_0c + bdlcount_0c_div8) << 8)|((rdqsnd_0c + bdlcount_0c_div8) << 16)));
                WriteReg_32(DBSC_V3M_DBPDRGA0, 0x000000AA + i * 0x20);
                RegVal = (ReadReg_32(DBSC_V3M_DBPDRGD0));
                rbd_0c[0] = (RegVal      ) & 0x0000001f;
                rbd_0c[1] = (RegVal >>  8) & 0x0000001f;
                rbd_0c[2] = (RegVal >> 16) & 0x0000001f;
                rbd_0c[3] = (RegVal >> 24) & 0x0000001f;

                WriteReg_32(DBSC_V3M_DBPDRGA0, 0x000000AA + i * 0x20);
                RegVal = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0xE0E0E0E0);
                for (j=0; j< 4; j++) {
                    rbd_0c[j] = (rbd_0c[j] + bdlcount_0c_div8);
                    if (rbd_0c[j] > 0x1F) rbd_0c[j] = 0x1F;
                    RegVal = RegVal | (rbd_0c[j] <<8*j);
                }
                WriteReg_32(DBSC_V3M_DBPDRGD0, RegVal);
                WriteReg_32(DBSC_V3M_DBPDRGA0, 0x000000AB + i * 0x20);
                RegVal = (ReadReg_32(DBSC_V3M_DBPDRGD0));
                rbd_0c[0] = (RegVal      ) & 0x0000001f;
                rbd_0c[1] = (RegVal >>  8) & 0x0000001f;
                rbd_0c[2] = (RegVal >> 16) & 0x0000001f;
                rbd_0c[3] = (RegVal >> 24) & 0x0000001f;

                WriteReg_32(DBSC_V3M_DBPDRGA0, 0x000000AB + i * 0x20);
                RegVal = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0xE0E0E0E0);
                for (j=0; j< 4; j++) {
                    rbd_0c[j] = (rbd_0c[j] + bdlcount_0c_div8);
                    if (rbd_0c[j] > 0x1F) rbd_0c[j] = 0x1F;
                    RegVal = RegVal | (rbd_0c[j] <<8*j);
                }
                WriteReg_32(DBSC_V3M_DBPDRGD0, RegVal);
            }
        }
    }
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000002);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x07D81E37);

    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000003);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X0380C720); //0x0380C700 -> 0x0380C720
    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000007);
    while ( (BIT30& ReadReg_32(DBSC_V3M_DBPDRGD0)) != 0 );

    WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000021);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0X0024643E);

    WriteReg_32(DBSC_V3M_DBBUS0CNF1,0x00000000);
#if (RCAR_REF_INT == RCAR_REF_DEFAULT)	//REF 3.9usec
    WriteReg_32(DBSC_V3M_DBCALCNF,0x0100401A);//tREFI=3.9us
    WriteReg_32(DBSC_V3M_DBRFCNF1,0x00080A0E);//tREFI=3.9us
    WriteReg_32(DBSC_V3M_DBRFCNF2,0x00010000);//tREFI=3.9us
#elif (RCAR_REF_INT == RCAR_REF_7800)
    WriteReg_32(DBSC_V3M_DBCALCNF,0x0100200D);//tREFI=7.8us
    WriteReg_32(DBSC_V3M_DBRFCNF1,0x0008141C);//tREFI=7.8us
    WriteReg_32(DBSC_V3M_DBRFCNF2,0x00010000);//tREFI=7.8us
#elif (RCAR_REF_INT == RCAR_REF_1950)
    WriteReg_32(DBSC_V3M_DBCALCNF,0x0100401A);//tREFI=1.95us
    WriteReg_32(DBSC_V3M_DBRFCNF1,0x00080A0E);//tREFI=1.95us
    WriteReg_32(DBSC_V3M_DBRFCNF2,0x00010001);//tREFI=1.95us
#else
    #error "Don't set out of range of RCAR_REF_INT."
#endif
    WriteReg_32(DBSC_V3M_DBDFICUPDCNF,0x40100001);
    WriteReg_32(DBSC_V3M_DBRFEN,0x00000001);
    WriteReg_32(DBSC_V3M_DBACEN,0x00000001);

    WriteReg_32(0xE67F0018,0x00000001);
    RegVal = ReadReg_32(0x40000000);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000000);
    WriteReg_32(DBSC_V3M_DBPDRGD0,RegVal);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000A0);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x7C0002C5);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000C0);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x7C0002C5);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000E0);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x7C0002C5);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000100);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x7C0002C5);

// PDR default(dynamic)  add 2018/10/11
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000A3);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000000);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000C3);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000000);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000E3);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000000);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000103);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000000);

    WriteReg_32(DBSC_V3M_DBPDLK0,0X00000000);
    WriteReg_32(DBSC_V3M_DBSYSCNT0,0x00000000);

#ifdef ddr_qos_init_setting // only for non qos_init:add 2018.01.25
    WriteReg_32(DBSC_V3M_DBSYSCNT0,0x00001234);
    WriteReg_32(DBSC_V3M_DBCAM0CNF1,0x00043218);
    WriteReg_32(DBSC_V3M_DBCAM0CNF2,0x000000F4);
    WriteReg_32(DBSC_V3M_DBSCHCNT0,0x000f0037);
    WriteReg_32(DBSC_V3M_DBSCHSZ0,0x00000001);
    WriteReg_32(DBSC_V3M_DBSCHRW0,0x22421111);
    WriteReg_32(DBSC_V3M_SCFCTST2,0x012F1123);
    WriteReg_32(DBSC_V3M_DBSCHQOS00,0x00000F00);
    WriteReg_32(DBSC_V3M_DBSCHQOS01,0x00000B00);
    WriteReg_32(DBSC_V3M_DBSCHQOS02,0x00000000);
    WriteReg_32(DBSC_V3M_DBSCHQOS03,0x00000000);
    WriteReg_32(DBSC_V3M_DBSCHQOS40,0x00000300);
    WriteReg_32(DBSC_V3M_DBSCHQOS41,0x000002F0);
    WriteReg_32(DBSC_V3M_DBSCHQOS42,0x00000200);
    WriteReg_32(DBSC_V3M_DBSCHQOS43,0x00000100);
    WriteReg_32(DBSC_V3M_DBSCHQOS90,0x00000300);
    WriteReg_32(DBSC_V3M_DBSCHQOS91,0x000002F0);
    WriteReg_32(DBSC_V3M_DBSCHQOS92,0x00000200);
    WriteReg_32(DBSC_V3M_DBSCHQOS93,0x00000100);
    WriteReg_32(DBSC_V3M_DBSCHQOS130,0x00000100);
    WriteReg_32(DBSC_V3M_DBSCHQOS131,0x000000F0);
    WriteReg_32(DBSC_V3M_DBSCHQOS132,0x000000A0);
    WriteReg_32(DBSC_V3M_DBSCHQOS133,0x00000040);
    WriteReg_32(DBSC_V3M_DBSCHQOS140,0x000000C0);
    WriteReg_32(DBSC_V3M_DBSCHQOS141,0x000000B0);
    WriteReg_32(DBSC_V3M_DBSCHQOS142,0x00000080);
    WriteReg_32(DBSC_V3M_DBSCHQOS143,0x00000040);
    WriteReg_32(DBSC_V3M_DBSCHQOS150,0x00000040);
    WriteReg_32(DBSC_V3M_DBSCHQOS151,0x00000030);
    WriteReg_32(DBSC_V3M_DBSCHQOS152,0x00000020);
    WriteReg_32(DBSC_V3M_DBSCHQOS153,0x00000010);
//    WriteReg_32(0xE67F0018,0X00000001);        //move
    WriteReg_32(DBSC_V3M_DBSYSCNT0,0x00000000);
#endif

    return 1;

}

uint32_t pll3_freq_change_bypmode_1316(void)
{
/* CPG & PHY setting ===============================================*/
    while ( (BIT11 & ReadReg_32(0xE61500D0)) == 0 );
    WriteReg_32(DBSC_V3M_CPGWPR,0x5A5AFFFF);
    WriteReg_32(DBSC_V3M_CPGWPCR,0xA5A50000);
    WriteReg_32(DBSC_V3M_DBSYSCNT0,0x00001234);
    WriteReg_32(DBSC_V3M_DBPDLK0,0x0000A55A);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000006);
    while ( (BIT31 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 );
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000A4);
    while ( (BIT15 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 );
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000E4);
    while ( (BIT15 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 );

    WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000008);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x802F8800);
    while ( (0x000003FF & ReadReg_32(0xE6150108)) != 0x00000030 );
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000006);
    while ( (BIT31 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 1 );
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000A4);
    while ( (BIT15 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 1 );
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000E4);
    while ( (BIT15 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 1 );

    WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000008);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x802B8000);

    WriteReg_32(0xE6150380,0x00000C00);
    WriteReg_32(0xE61500DC,0x4E000000);
    while ( (0x000003FF & ReadReg_32(0xE6150108)) != 0x00000030 );
    WriteReg_32(0xE61500E4,0x00000000);
    WriteReg_32(0xE6150004,0x80321235);
    while ( (BIT31 & ReadReg_32(0xE6150004)) == 1 );
    while ( (0x000003FF & ReadReg_32(0xE6150108)) != 0x00000030 );
    WriteReg_32(0xE61500E4,0x00040202);
    WriteReg_32(0xE6150004,0x80321235);
    while ( (BIT31 & ReadReg_32(0xE6150004)) == 1 );
    WriteReg_32(0xE6150380,0x00000000);
    while ( (BIT11 & ReadReg_32(0xE61500D0)) == 0 );

    WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000008);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x002F8800);

    /*== add 20171106 ====================================*/
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000006);
    while ( (BIT31 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 1 );
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000A4);
    while ( (BIT15 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 1 );
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000E4);
    while ( (BIT15 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 1 );
    /*====================================================*/

    while ( (0x000003FF & ReadReg_32(0xE6150108)) != 0x00000030 );

    /*== add 20171106 ====================================*/
    while ( (BIT11 & ReadReg_32(0xE61500D0)) == 0 );
    /*====================================================*/

    WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000008);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x000F8800);

    /*== add 20171106 ====================================*/
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000006);
    while ( (BIT31 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 1 );
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000A4);
    while ( (BIT15 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 1 );
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000E4);
    while ( (BIT15 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 1 );
    /*====================================================*/

    while ( (0x000003FF & ReadReg_32(0xE6150108)) != 0x00000030 );

    /*== add 20171106 ====================================*/
    while ( (BIT11 & ReadReg_32(0xE61500D0)) == 0 );
    /*====================================================*/

    WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000008);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x000F8000);
    while ( (0x000003FF & ReadReg_32(0xE6150108)) != 0x00000030 );
    /*== add 20171106 ====================================*/
    while ( (BIT11 & ReadReg_32(0xE61500D0)) == 0 );
    /*====================================================*/

    WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000008);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x000B8000);

    WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000006);
    while ( (BIT31 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 );
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000A4);
    while ( (BIT15 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 );
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000E4);
    while ( (BIT15 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 );
    WriteReg_32(DBSC_V3M_CPGWPCR,0xA5A50001);
    WriteReg_32(DBSC_V3M_DBPDLK0,0x00000000);
    WriteReg_32(DBSC_V3M_DBSYSCNT0,0x00000000);

    return 1;

}

uint32_t pll3_freq_change_bypmode_1583(void)
{
/* CPG & PHY setting ===============================================*/
    while ( (BIT11 & ReadReg_32(0xE61500D0)) == 0 );
    WriteReg_32(DBSC_V3M_CPGWPR,0x5A5AFFFF);
    WriteReg_32(DBSC_V3M_CPGWPCR,0xA5A50000);
    WriteReg_32(DBSC_V3M_DBSYSCNT0,0x00001234);
    WriteReg_32(DBSC_V3M_DBPDLK0,0x0000A55A);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000006);
    while ( (BIT31 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 );
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000A4);
    while ( (BIT15 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 );
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000E4);
    while ( (BIT15 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 );
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000008);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x802F8800);
    while ( (0x000003FF & ReadReg_32(0xE6150108)) != 0x00000030 );
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000006);
    while ( (BIT31 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 1 );
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000A4);
    while ( (BIT15 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 1 );
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000E4);
    while ( (BIT15 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 1 );
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000008);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x802B8000);
    WriteReg_32(0xE6150380,0x00000C00);
    WriteReg_32(0xE61500DC,0x5E000000);
    while ( (0x000003FF & ReadReg_32(0xE6150108)) != 0x00000030 );
    WriteReg_32(0xE61500E4,0x00000000);
    WriteReg_32(0xE6150004,0x80321235);
    while ( (BIT31 & ReadReg_32(0xE6150004)) == 1 );
    while ( (0x000003FF & ReadReg_32(0xE6150108)) != 0x00000030 );
    WriteReg_32(0xE61500E4,0x00040202);
    WriteReg_32(0xE6150004,0x80321235);
    while ( (BIT31 & ReadReg_32(0xE6150004)) == 1 );
    WriteReg_32(0xE6150380,0x00000000);
    while ( (BIT11 & ReadReg_32(0xE61500D0)) == 0 );

    WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000008);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x002F8800);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000006);
    while ( (BIT31 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 1 );
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000A4);
    while ( (BIT15 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 1 );
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000E4);
    while ( (BIT15 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 1 );
    while ( (0x000003FF & ReadReg_32(0xE6150108)) != 0x00000030 );
    while ( (BIT11 & ReadReg_32(0xE61500D0)) == 0 );

    WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000008);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x000F8800);
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000006);
    while ( (BIT31 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 1 );
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000A4);
    while ( (BIT15 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 1 );
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000E4);
    while ( (BIT15 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 1 );
    while ( (0x000003FF & ReadReg_32(0xE6150108)) != 0x00000030 );
    while ( (BIT11 & ReadReg_32(0xE61500D0)) == 0 );

    WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000008);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x000F8000);
    while ( (0x000003FF & ReadReg_32(0xE6150108)) != 0x00000030 );
    while ( (BIT11 & ReadReg_32(0xE61500D0)) == 0 );

    WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000008);
    WriteReg_32(DBSC_V3M_DBPDRGD0,0x000B8000);

    WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000006);
    while ( (BIT31 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 );
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000A4);
    while ( (BIT15 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 );
    WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000E4);
    while ( (BIT15 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 );
    WriteReg_32(DBSC_V3M_CPGWPCR,0xA5A50001);
    WriteReg_32(DBSC_V3M_DBPDLK0,0x00000000);
    WriteReg_32(DBSC_V3M_DBSYSCNT0,0x00000000);

    return 1;

}
