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 *
 * This software is provided as reference/sample code under the license
 * agreement between Renesas Electronics Corporation and licensee (the
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/*******************************************************************************
 * DESCRIPTION   : SCIF register header
 ******************************************************************************/


#ifndef SCIF_REGISTER_H_
#define SCIF_REGISTER_H_

#include <remap_register.h>

/* SCIF0 base address */
/* 0xE6E60000 */
#define SCIF0_BASE  (BASE_SCIF_ADDR)

#define SCIF_SCSMR  (SCIF0_BASE + 0x0000U)      /*  16  Serial mode register */
#define SCIF_SCBRR  (SCIF0_BASE + 0x0004U)      /*  8   Bit rate register */
#define SCIF_SCSCR  (SCIF0_BASE + 0x0008U)      /*  16  Serial control register */
#define SCIF_SCFTDR (SCIF0_BASE + 0x000CU)      /*  8   Transmit FIFO data register */
#define SCIF_SCFSR  (SCIF0_BASE + 0x0010U)      /*  16  Serial status register */
#define SCIF_SCFRDR (SCIF0_BASE + 0x0014U)      /*  8   Receive FIFO data register */
#define SCIF_SCFCR  (SCIF0_BASE + 0x0018U)      /*  16  FIFO control register */
#define SCIF_SCFDR  (SCIF0_BASE + 0x001CU)      /*  16  FIFO data count register */
#define SCIF_SCSPTR (SCIF0_BASE + 0x0020U)      /*  16  Serial port register */
#define SCIF_SCLSR  (SCIF0_BASE + 0x0024U)      /*  16  Line status register */
#define SCIF_DL     (SCIF0_BASE + 0x0030U)      /*  16  Frequency division register */
#define SCIF_CKS    (SCIF0_BASE + 0x0034U)      /*  16  Clock Select register */

#endif /* SCIF_REGISTER_H_ */
