/*******************************************************************************
 * DISCLAIMER
 * This software is supplied by Renesas Electronics Corporation and is only
 * intended for use with Renesas products. No other uses are authorized. This
 * software is owned by Renesas Electronics Corporation and is protected under
 * all applicable laws, including copyright laws.
 * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
 * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
 * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
 * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
 * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
 * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
 * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
 * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
 * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
 * Renesas reserves the right, without notice, to make changes to this software
 * and to discontinue the availability of this software. By using this software,
 * you agree to the additional terms and conditions found by accessing the
 * following link:
 * http://www.renesas.com/disclaimer
 * Copyright 2021-2022 Renesas Electronics Corporation All rights reserved.
 *******************************************************************************/

/*******************************************************************************
 * DESCRIPTION   : eMMC register header
 ******************************************************************************/

#ifndef EMMC_REGISTERS_H__
#define EMMC_REGISTERS_H__

/* ************************ HEADER (INCLUDE) SECTION *********************** */
#include <remap_register.h>
/* ***************** MACROS, CONSTANTS, COMPILATION FLAGS ****************** */
/* MMC0 channel */
#define MMC0_SD_BASE	(BASE_MMC0_ADDR)	/* reg addr is 0xEE140000U */

#define SD_CMD			(MMC0_SD_BASE + 0x0000U)
#define SD_ARG			(MMC0_SD_BASE + 0x0010U)
#define SD_STOP			(MMC0_SD_BASE + 0x0020U)
#define SD_SECCNT		(MMC0_SD_BASE + 0x0028U)
#define SD_RSP10		(MMC0_SD_BASE + 0x0030U)
#define SD_RSP32		(MMC0_SD_BASE + 0x0040U)
#define SD_RSP54		(MMC0_SD_BASE + 0x0050U)
#define SD_RSP76		(MMC0_SD_BASE + 0x0060U)
#define SD_INFO1		(MMC0_SD_BASE + 0x0070U)
#define SD_INFO2		(MMC0_SD_BASE + 0x0078U)
#define SD_INFO1_MASK		(MMC0_SD_BASE + 0x0080U)
#define SD_INFO2_MASK		(MMC0_SD_BASE + 0x0088U)
#define SD_CLK_CTRL		(MMC0_SD_BASE + 0x0090U)
#define SD_SIZE			(MMC0_SD_BASE + 0x0098U)
#define SD_OPTION		(MMC0_SD_BASE + 0x00A0U)
#define SD_ERR_STS1		(MMC0_SD_BASE + 0x00B0U)
#define SD_ERR_STS2		(MMC0_SD_BASE + 0x00B8U)
#define SD_BUF0			(MMC0_SD_BASE + 0x00C0U)
#define CC_EXT_MODE		(MMC0_SD_BASE + 0x0360U)
#define SOFT_RST		(MMC0_SD_BASE + 0x0380U)
#define HOST_MODE		(MMC0_SD_BASE + 0x0390U)
#define DM_CM_DTRAN_MODE	(MMC0_SD_BASE + 0x0820U)
#define DM_CM_DTRAN_CTRL	(MMC0_SD_BASE + 0x0828U)
#define DM_CM_INFO1		(MMC0_SD_BASE + 0x0840U)
#define DM_CM_INFO1_MASK	(MMC0_SD_BASE + 0x0848U)
#define DM_CM_INFO2		(MMC0_SD_BASE + 0x0850U)
#define DM_CM_INFO2_MASK	(MMC0_SD_BASE + 0x0858U)
#define DM_DTRAN_ADDR		(MMC0_SD_BASE + 0x0880U)



/* SD_INFO1 Registers */
#define SD_INFO1_INFO2				(0x00000004U)		/* Access end						*/
#define SD_INFO1_INFO0				(0x00000001U)		/* Response end						*/

/* SD_INFO2 Registers */
#define SD_INFO2_CBSY				(0x00004000U)		/* Command Type Register Busy	*/
#define SD_INFO2_BWE				(0x00000200U)		/* SD_BUF Write Enable			*/
#define SD_INFO2_BRE				(0x00000100U)		/* SD_BUF Read Enable			*/
#define SD_INFO2_DAT0				(0x00000080U)		/* SDDAT0						*/
#define SD_INFO2_ALL_ERR			(0x0000807FU)
#define SD_INFO2_CLEAR				(0x00000800U)		/* BIT11 The write value should always be 1. HWM_0003 */

/* DM_INFO1 Registers */
#define DM_CM_INFO_DTRANEND0        (0x00010000U)       /* DMAC Channel 0 Transfer End */
#define DM_CM_INFO_DTRANEND1        (0x00020000U)       /* DMAC Channel 0 Transfer End */

/* SOFT_RST */
#define SOFT_RST_SDRST				(0x00000001U)

/* SD_CLK_CTRL */
#define SD_CLK_CTRL_CLKDIV_MASK     (0x000000FFU)
#define SD_CLK_WRITE_MASK           (0x000003FFU)

/* SD_OPTION */
#define SD_OPTION_WIDTH             (0x00008000U)
#define SD_OPTION_WIDTH8            (0x00002000U)
#define SD_OPTION_TIMEOUT_CNT_MASK	(0x000000F0U)


/* MMC Clock Frequency
 * 200MHz * 1/x = output clock
 */
#define MMC_400KHZ			(512U)			/* 200MHz * 1/512 = 390 KHz 				*/
#define MMC_20MHZ			(16U)			/* 200MHz * 1/16  = 12.5 MHz Normal speed mode		*/
#define MMC_26MHZ			(8U)			/* 200MHz * 1/8   = 25 MHz High speed mode 26Mhz	*/
#define MMC_52MHZ			(4U)			/* 200MHz * 1/4   = 50 MHz High speed mode 52Mhz	*/


#define MMC_FREQ_52MHZ		(52000000U)
#define MMC_FREQ_26MHZ		(26000000U)
#define MMC_FREQ_20MHZ		(20000000U)


/* MMC Clock DIV */
#define MMC_SD_CLK_START	(0x00000100U)	/* CLOCK On     */
#define MMC_SD_CLK_STOP		(~0x00000100UL)	/* CLOCK stop   */

/* DM_CM_DTRAN_MODE */
#define DM_CM_DTRAN_MODE_CH0		(0x00000000U)		/* CH0 : downstream	*/
#define DM_CM_DTRAN_MODE_CH1		(0x00010000U)		/* CH1 : upstream	*/
#define DM_CM_DTRAN_MODE_BIT_WIDTH	(0x00000030U)

/* CC_EXT_MODE */
#define CC_EXT_MODE_DMASDRW_ENABLE	(0x00000002U)		/* SD_BUF Read/Write DMA Transfer */
#define CC_EXT_MODE_CLEAR			(0x00001010U)		/* BIT 12 & 4 always 1. */

/* DM_CM_INFO_MASK */
#define DM_CM_INFO_MASK_CLEAR		(0xFFFCFFFEU)
#define DM_CM_INFO_CH0_ENABLE		(0x00010001U)
#define DM_CM_INFO_CH1_ENABLE		(0x00020001U)

/* DM_DTRAN_ADDR */
#define DM_DTRAN_ADDR_WRITE_MASK	(0xFFFFFFF8U)

/*DM_CM_DTRAN_CTRL */
#define DM_CM_DTRAN_CTRL_START		(0x00000001U)


/* ********************** STRUCTURES, TYPE DEFINITIONS ********************* */

/* ********************** DECLARATION OF EXTERNAL DATA ********************* */

/* ************************** FUNCTION PROTOTYPES ************************** */

/* ********************************* CODE ********************************** */

#endif /* EMMC_REGISTERS_H__ */
/* ******************************** END ************************************ */

