/*******************************************************************************
 * DISCLAIMER
 * This software is supplied by Renesas Electronics Corporation and is only
 * intended for use with Renesas products. No other uses are authorized. This
 * software is owned by Renesas Electronics Corporation and is protected under
 * all applicable laws, including copyright laws.
 * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
 * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
 * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
 * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
 * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
 * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
 * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
 * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
 * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
 * Renesas reserves the right, without notice, to make changes to this software
 * and to discontinue the availability of this software. By using this software,
 * you agree to the additional terms and conditions found by accessing the
 * following link:
 * http://www.renesas.com/disclaimer
 * Copyright 2021-2022 Renesas Electronics Corporation All rights reserved.
 *******************************************************************************/

/*******************************************************************************
 * DESCRIPTION   : RPC register header
 ******************************************************************************/

#ifndef RPC_REGISTER_H_
#define RPC_REGISTER_H_


#include <remap_register.h>

/* RPC base address */
/* 0xEE200000 */
#define RPC_BASE    (BASE_RPC_ADDR)

#define RPC_CMNCR       (RPC_BASE + 0x0000U)    /*  Common control register */
#define	RPC_SSLDR		(RPC_BASE + 0x0004U)	/*  R/W */
#define RPC_DRCR        (RPC_BASE + 0x000CU)    /*  Data read control register */
#define RPC_DRCMR       (RPC_BASE + 0x0010U)    /*  Data read command setting register */
#define RPC_DREAR       (RPC_BASE + 0x0014U)    /*  Data read extended address register */
#define RPC_DRENR       (RPC_BASE + 0x001CU)    /*  Data read enable setting register */
#define RPC_SMCR        (RPC_BASE + 0x0020U)    /*  Manual mode control register */
#define RPC_SMCMR       (RPC_BASE + 0x0024U)    /*  Manual mode command setting register */
#define	RPC_SMADR		(RPC_BASE + 0x0028U)	/*  R/W */
#define	RPC_SMOPR		(RPC_BASE + 0x002CU)	/*  R/W */
#define RPC_SMENR       (RPC_BASE + 0x0030U)    /*  Manual mode enable setting register */
#define RPC_SMRDR0      (RPC_BASE + 0x0038U)    /*  Manual mode read data register 0 */
#define	RPC_SMRDR1		(RPC_BASE + 0x003CU)	/*  R   */
#define	RPC_SMWDR0		(RPC_BASE + 0x0040U)	/*  R/W */
#define RPC_CMNSR       (RPC_BASE + 0x0048U)    /*  Common status register */
#define RPC_DRDMCR      (RPC_BASE + 0x0058U)    /*  Data read Dummy Cycle setting register */
#define RPC_DRDRENR     (RPC_BASE + 0x005CU)    /*  Data read DDR enable register */
#define	RPC_SMDMCR		(RPC_BASE + 0x0060U)	/*  R/W */
#define RPC_SMDRENR     (RPC_BASE + 0x0064U)    /*  Manual mode DDR enable register */
#define RPC_PHYCNT      (RPC_BASE + 0x007CU)    /*  PHY control register */
#define RPC_PHYOFFSET1  (RPC_BASE + 0x0080U)    /*  PHY Timing Offset Register 1 */
#define RPC_OFFSET1     RPC_PHYOFFSET1
#define	RPC_PHYINT		(RPC_BASE + 0x0088U)	/*  R/W */
#define	RPC_WRBUF		(RPC_BASE + 0x8000U)	/*  W	RPC Write buffer (Access size=4/8/16/32/64Byte) */
#define RPC_WRBUF_PHYS  (0xEE208000)

/* for RPC register setting */
#define RPC_PHYCNT_CAL			(1U << 31U)
#define RPC_PHYCNT_STRTIM3		(1U << 27U)
#define RPC_PHYCNT_HS			(1U << 18U)
#define RPC_PHYCNT_STRTIM2		(1U << 17U)
#define RPC_PHYCNT_STRTIM1		(1U << 16U)
#define RPC_PHYCNT_STRTIM0		(1U << 15U)
#define RPC_PHYCNT_WBUF2		(1U <<  4U)
#define RPC_PHYCNT_WBUF			(1U <<  2U)
#define RPC_PHYCNT_PHYMEM_HYP	(3U <<  0U)
#define CMNCR_MD_MANUAL             (1U << 31U)
#define CMNCR_MOIIO3_HIZ            (3U << 22U)
#define CMNCR_MOIIO2_HIZ            (3U << 20U)
#define CMNCR_MOIIO1_HIZ            (3U << 18U)
#define CMNCR_MOIIO0_HIZ            (3U << 16U)
#define CMNCR_IO0FV_HIZ             (3U <<  8U)
#define CMNCR_BSZ_HYP               (1U <<  0U)
#define CMNCR_BSZ_MASK              (3U <<  0U)
#define SSLDR_SLNDL                 (4U <<  8U)
#define DRCR_SSLN                   (1U << 24U)
#define DRCR_RBURST_32UNITS         (0x1FU << 16U)
#define DRCR_RCF                    (1U <<  9U)
#define DRCR_RBE_BURST              (1U <<  8U)
#define DRCR_SSLE                   (1U <<  0U)
#define DRCMR_S26KS512S             (0xA0U << 16U)
#define DRCMR_CMD_MASK              (0xFFU << 16U)
#define DRCMR_OCMD_MASK             (0xFFU <<  0U)
#define DREAR_EAC_26BITS            (1U <<  0U)
#define DREAR_EAV_MASK              (0xFFU << 16U)
#define DREAR_EAC_MASK              (7U <<  0U)
#define DRENR_CDB_4BITS             (2U << 30U)
#define DRENR_OCDB_4BITS            (2U << 28U)
#define DRENR_ADB_4BITS             (2U << 24U)
#define DRENR_OPDB_4BITS            (2U << 20U)
#define DRENR_DRDB_4BITS            (2U << 16U)
#define DRENR_DME_EN                (1U << 15U)
#define DRENR_CDE_EN                (1U << 14U)
#define DRENR_OCDE_EN               (1U << 12U)
#define DRENR_ADE_HYPER             (4U <<  8U)
#define DRENR_ADE_ONE_SERIAL        (0xFU << 8U)
#define DRENR_CDB_MASK              (3U << 30U)
#define DRENR_OCDB_MASK             (3U << 28U)
#define DRENR_ADB_MASK              (3U << 24U)
#define DRENR_OPDB_MASK             (3U << 20U)
#define DRENR_DRDB_MASK             (3U << 16U)
#define DRENR_ADE_MASK              (0xFU << 8U)
#define DRENR_OPDE_MASK             (0xFU << 4U)
#define SMCR_SSLKP                  (1U <<  8U)
#define SMCR_SPIRE                  (1U <<  2U)
#define SMCR_SPIWE                  (1U <<  1U)
#define SMCR_SPIE                   (1U <<  0U)
#define SMCMR_HYP_READ              (0x80U << 16U)
#define SMCMR_HYP_WRITE             (0x00U << 16U)
#define SMCMR_CMD_MASK              (0xFFU << 16U)
#define SMCMR_OCMD_MASK             (0xFFU <<  0U)
#define SMOPR_OPD3_MASK             (0xFFU << 24U)
#define SMOPR_OPD2_MASK             (0xFFU << 16U)
#define SMOPR_OPD1_MASK             (0xFFU <<  8U)
#define SMOPR_OPD0_MASK             (0xFFU <<  0U)
#define SMENR_CDB_4BITS             (2U << 30U)
#define SMENR_OCDB_4BITS            (2U << 28U)
#define SMENR_ADB_4BITS             (2U << 24U)
#define SMENR_OPDB_4BITS            (2U << 20U)
#define SMENR_SPIDB_4BITS           (2U << 16U)
#define SMENR_DME_EN                (1U << 15U)
#define SMENR_CDE_EN                (1U << 14U)
#define SMENR_OCDE_EN               (1U << 12U)
#define SMENR_ADE_HYPER             (4U <<  8U)
#define SMENR_ADE_SERIAL_31         (0xFU << 8U)
#define SMENR_ADE_SERIAL_23         (7U << 8U)
#define SMENR_SPIDE_HYP_16          (8U <<  0U)
#define SMENR_SPIDE_HYP_32          (0xCU <<  0U)
#define SMENR_SPIDE_HYP_64          (0xFU <<  0U)
#define SMENR_SPIDE_SPI_8           (8U <<  0U)
#define SMENR_SPIDE_SPI_16          (0xCU <<  0U)
#define SMENR_SPIDE_SPI_32          (0xFU <<  0U)
#define SMENR_CDB_MASK              (3U << 30U)
#define SMENR_OCDB_MASK             (3U << 28U)
#define SMENR_ADB_MASK              (3U << 24U)
#define SMENR_OPDB_MASK             (3U << 20U)
#define SMENR_SPIDB_MASK            (3U << 16U)
#define SMENR_ADE_MASK              (0xFU << 8U)
#define SMENR_OPDE_MASK             (0xFU << 4U)
#define SMENR_SPIDE_MASK            (0xFU << 0U)
#define CMNSR_TEND                  (0x00000001U)
#define DRDMCR_DMCYC_15             (0xEU << 0U)
#define DRDMCR_DMCYC_8              (7U <<  0U)
#define DRDMCR_DMCYC_MASK           (0x1FU << 0U)
#define DRDRENR_HYPE_HYPER          (5U << 12U)
#define DRDRENR_ADDRE               (1U <<  8U)
#define DRDRENR_OPDRE               (1U <<  4U)
#define DRDRENR_DRDRE               (1U <<  0U)
#define DRDRENR_HYPE_MASK           (7U << 12U)
#define SMDMCR_DMCYC_15             (0xEU << 0U)
#define SMDMCR_DMCYC_8              (7U <<  0U)
#define SMDMCR_DMCYC_MASK           (0x1FU << 0U)
#define SMDRENR_HYPE_HYPER          (5U << 12U)
#define SMDRENR_ADDRE               (1U <<  8U)
#define SMDRENR_OPDRE               (1U <<  4U)
#define SMDRENR_SPIDRE              (1U <<  0U)
#define SMDRENR_HYPE_MASK           (7U << 12U)
#define PHYOFFSET1_HYPER            (0x21511144U)
#define PHYOFFSET1_DMA_QSPI         (0x31511144U)
#define PHYOFFSET1_MASK             (0xFFFFFFFFU)
#define PHYINT_HYPER                (0x07070002U)
#define PHYINT_MASK                 (0xFFFFFFFFU)

#endif /* RPC_REGISTER_H_ */
