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/*******************************************************************************
 * DESCRIPTION   : ECC driver header
 ******************************************************************************/

#ifndef ECC_PROTECT
#define ECC_PROTECT
/* DBSC registers */
#if defined(__RH850G3K__)
#include "remap_register.h"
#include "mem_io.h"
#include "log.h"
#define DBSC_D_BASE			  (BASE_DBSC_ADDR + 0x14000U)	/* forV4H DBSC0 clk_dbsc region	DBSC1_D_BASE = 0xE67A8000U */
#define DBSC_A_BASE			  (BASE_DBSC_ADDR)	            /* forV4H DBSC0 clk_axim region	DBSC1_A_BASE = 0xE6798000U */
#define ECM_BASE              (BASE_ECC_ADDR)
#else
#if (ECC_ENABLE == 1)
#include "mem_io.h"
#include "log.h"
#define DBSC_D_BASE			  (0xE67A4000U)	                /* forV4H DBSC0 clk_dbsc region	DBSC1_D_BASE = 0xE67A8000U */
#define DBSC_A_BASE			  (0xE6790000U)	                /* forV4H DBSC0 clk_axim region	DBSC1_A_BASE = 0xE6798000U */
#endif /* ECC_ENABLE == 1 */
#define ECM_BASE              (0xE6250000U)
#endif/* defined(__RH850G3K__) */

#if (ECC_ENABLE == 1)
void ecc_sdram_enable(void);

#define DB0SYSCNT0            (DBSC_D_BASE + 0x0100U)
#define DB0SYSCNT0A           (DBSC_A_BASE + 0x0100U)
#define DB1SYSCNT0            (DB0SYSCNT0 +  0x4000U)
#define DB1SYSCNT0A           (DB0SYSCNT0A + 0x8000U)

#define	DBSC_DB0ACEN		  (DBSC_A_BASE + 0x0200U)
#define	DBSC_DB1ACEN		  (DBSC_DB0ACEN + 0x8000U)
#endif /* ECC_ENABLE == 1 */

#define ECMWACNTR             (ECM_BASE + 0x0A04U)
#define ECMWPCNTR             (ECM_BASE + 0x0A00U)
#if (ECC_ENABLE == 1)
#define ECMERRTGTR0           (ECM_BASE + 0x0200U)
#define ECMERRCTLR0           (ECM_BASE + 0x0000U)
#define DB0FSCONF00A          (DBSC_A_BASE    + 0x7640U)
#define DB1FSCONF00A          (DB0FSCONF00A   + 0x8000U)
#define DB0FSCONF01A          (DBSC_A_BASE    + 0x7644U)
#define DB1FSCONF01A          (DB0FSCONF01A   + 0x8000U)
#define DB0FSCONF02A          (DBSC_A_BASE    + 0x7648U)
#define DB1FSCONF02A          (DB0FSCONF02A   + 0x8000U)
#define DB0FSCTRL01A          (DBSC_A_BASE    + 0x7604U)
#define DB1FSCTRL01A          (DB0FSCTRL01A   + 0x8000U)
#define DB0FSSTAT01A          (DBSC_A_BASE    + 0x7684U)
#define DB1FSSTAT01A          (DB0FSSTAT01A   + 0x8000U)
#define DB0FSSTAT00A          (DBSC_A_BASE    + 0x7680U)
#define DB1FSSTAT00A          (DB0FSSTAT00A   + 0x8000U)
#define DB0FSINTENB02A        (DBSC_A_BASE    + 0x7088U)
#define DB1FSINTENB02A        (DB0FSINTENB02A + 0x8000U)
#define DB0FSINTENB04A        (DBSC_A_BASE    + 0x7090U)
#define DB1FSINTENB04A        (DB0FSINTENB04A + 0x8000U)

#define DB0FSDRAMECCAREA00     (DBSC_A_BASE + 0x7450U)
#define DB0FSDRAMECCAREA01     (DBSC_A_BASE + 0x7454U)
#define DB1FSDRAMECCAREA00     (DB0FSDRAMECCAREA00 + 0x8000U)
#define DB1FSDRAMECCAREA01     (DB0FSDRAMECCAREA01 + 0x8000U)

#define DB0FSCONFAXI0        (DBSC_A_BASE   + 0x7400U)
#define DB1FSCONFAXI0        (DB0FSCONFAXI0 + 0x8000U)

/********************* Set by the user *********************/
/* The row address of ECC Protection Area Size for memory rank 0/1 of DBSC0/1 */
#define ECC_PROT_SIZE00        (0xCCCCU)
#define ECC_PROT_SIZE01        (0xCCCCU)
#define ECC_PROT_SIZE10        (0xCCCCU)
#define ECC_PROT_SIZE11        (0xCCCCU)

/* Start and End row address of ECC Protection area for rank0 of DBSC0/1 */
#define START_ECC_INIT_AREA00   (0x00000000U)
#define START_ECC_INIT_AREA10   (0x00000000U)
#define END_ECC_INIT_AREA00     (0x0000CCCBU)
#define END_ECC_INIT_AREA10     (0x0000CCCBU)

/* Start and End row address of ECC Protection area for rank1 of DBSC0/1 */
#define START_ECC_INIT_AREA01   (0x00000000U)
#define START_ECC_INIT_AREA11   (0x00000000U)
#define END_ECC_INIT_AREA01     (0x0000CCCBU)
#define END_ECC_INIT_AREA11     (0x0000CCCBU)
/***********  Other settings cannot be changed ***************/
#endif /* ECC_ENABLE == 1 */

#endif/* ECC_PROTECT */
