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 *******************************************************************************/

#ifndef BOOT_INIT_DRAM_CONFIG_H_
#define BOOT_INIT_DRAM_CONFIG_H_

/*******************************************************************************
 * DRAM Param setting
 ******************************************************************************/
#define JS2_DERATE                    0U
#define DBSC_REFINT                   1920U     /* Average periodic refresh interval/Average Refresh Interval [ns] */
#ifndef DBSC_REFINTS
#define DBSC_REFINTS                  0U        /* 0: Average interval is REFINT. / 1: Average interval is 1/2 REFINT. */
#endif
#define PERIODIC_TRAINING_INTERVAL    20000U    /* Periodic-WriteDQ/ReadDQ Training Interval [us] */

/*******************************************************************************
 *    NUMBER OF BOARD CONFIGURATION
 *    PLEASE DEFINE
 ******************************************************************************/
#define BOARDNUM    2U    /* Add User platform BOARD */

/*******************************************************************************
 *    Prototypes
 ******************************************************************************/
uint32_t r_boardcnf_get_brd_type(void);
void r_boardcnf_get_brd_clk(uint32_t brd, uint32_t *clk, uint32_t *clk_div);
void r_boardcnf_get_ddr_mbps(uint32_t brd, uint32_t *mbps, uint32_t *mbps_div, uint32_t *sscg, uint32_t *med_freq_en);

/*******************************************************************************
 *    BOARD CONFIGURATION
 *    PLEASE DEFINE boardcnfs[]
 ******************************************************************************/
typedef struct
{
    /*
     0x00...0000B:  4Gb dual channel die /  2Gb single channel die
     0x01...0001B:  6Gb dual channel die /  3Gb single channel die
     0x02...0010B:  8Gb dual channel die /  4Gb single channel die
     0x03...0011B: 12Gb dual channel die /  6Gb single channel die
     0x04...0100B: 16Gb dual channel die /  8Gb single channel die
     0x05...0101B: 24Gb dual channel die / 12Gb single channel die
     0x06...0110B: 32Gb dual channel die / 16Gb single channel die
     0x07...0111B: 24Gb single channel die
     0x08...1000B: 32Gb single channel die
     0xFF...NO_MEMORY
    */
    uint8_t bdcfg_ddr_density[CS_CNT];
    /* SoC caX([6][5][4][3][2][1][0]) -> MEM caY: */
    uint32_t bdcfg_ca_swap;
    /* SoC dqsX([1][0]) -> MEM dqsY: */
    uint8_t bdcfg_dqs_swap;
    /* SoC dq([7][6][5][4][3][2][1][0]) -> MEM dqY/dm:  (8 means DM) */
    uint32_t bdcfg_dq_swap[SLICE_CNT];
    /* SoC dm -> MEM dqY/dm:  (8 means DM) */
    uint8_t bdcfg_dm_swap[SLICE_CNT];
    /* SoC ckeX([1][0]) -> MEM csY */
    uint8_t bdcfg_cs_swap;
} st_boardcnf_ch_t;

typedef struct
{
    /* ch in use */
    uint8_t bdcfg_phyvalid;
    /* Read vref (SoC) training range         : [23:16]step  / [15:8]stop  / [7:0]start,  0x00000000 = default val */
    uint32_t bdcfg_vref_r;
    /* Write vref (MR14, MR15) training range : [15:8]stop   / [7:0]start,  0x0000 = default val */
    uint16_t bdcfg_vref_w;
    /* CA vref (MR12) training range          : [15:8]stop   / [7:0]start,  0x0000 = default val */
    uint16_t bdcfg_vref_ca;
    /* RFM required check                     : 0x01 = check enable, 0x00 = check disable */
    uint8_t bdcfg_rfm_chk;

    st_boardcnf_ch_t ch[2];
} st_boardcnf_t;

static const st_boardcnf_t boardcnfs[BOARDNUM] = {
/*
 * boardcnf[0] RENESAS V4M Gray Hawk (64Gbit 2rank)
 */
{
    0x03U,          /* bdcfg_phyvalid */
    0x00000000U,    /* bdcfg_vref_r */
    0x0000U,        /* bdcfg_vref_w */
    0x0000U,        /* bdcfg_vref_ca */
    0x01U,          /* bdcfg_rfm_chk */
    {
/* ch[0] */    {
/* bdcfg_ddr_density[] */    { 0x06U, 0x06U },
/* bdcfg_ca_swap */            0x06235104U,
/* bdcfg_dqs_swap */           0x01U,
/* bdcfg_dq_swap[] */        { 0x43061257U, 0x30721685U },
/* bdcfg_dm_swap[] */        { 0x08U, 0x04U },
/* bdcfg_cs_swap */            0x10U
        },
/* ch[1] */    {
/* bdcfg_ddr_density[] */    { 0x06U, 0x06U },
/* bdcfg_ca_swap */            0x04012653U,
/* bdcfg_dqs_swap */           0x10U,
/* bdcfg_dq_swap[] */        { 0x58147026U, 0x70132685U },
/* bdcfg_dm_swap[] */        { 0x03U, 0x04U },
/* bdcfg_cs_swap */            0x10U
        }
    }
},
/*
 * boardcnf[1] RENESAS V4M (2ch)
 */
{
    0x03U,          /* bdcfg_phyvalid */
    0x00000000U,    /* bdcfg_vref_r */
    0x0000U,        /* bdcfg_vref_w */
    0x0000U,        /* bdcfg_vref_ca */
    0x01U,          /* bdcfg_rfm_chk */
    {
/* ch[0] */    {
/* bdcfg_ddr_density[] */    { 0x06U, 0x06U },
/* bdcfg_ca_swap */            0x06543210U,
/* bdcfg_dqs_swap */           0x10U,
/* bdcfg_dq_swap[] */        { 0x76543210U, 0x76543210U },
/* bdcfg_dm_swap[] */        { 0x08U, 0x08U },
/* bdcfg_cs_swap */            0x10U
        },
/* ch[1] */    {
/* bdcfg_ddr_density[] */    { 0x06U, 0x06U },
/* bdcfg_ca_swap */            0x06543210U,
/* bdcfg_dqs_swap */           0x10U,
/* bdcfg_dq_swap[] */        { 0x76543210U, 0x76543210U },
/* bdcfg_dm_swap[] */        { 0x08U, 0x08U },
/* bdcfg_cs_swap */            0x10U
        }
    }
}
};

#endif /* BOOT_INIT_DRAM_CONFIG_H_ */
