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 *
 * This software is provided as reference/sample code under the license
 * agreement between Renesas Electronics Corporation and licensee (the
 * "License Agreement") and shall be treated as specified in the License
 * Agreement.
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 * information of Renesas Electronics Corporation. They must be used and
 * modified solely for the purpose for which it was furnished by Renesas
 * Electronics Corporation. All or part of these instructions, statements and
 * software must not be reproduced nor disclosed to any third party in any
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 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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 ******************************************************************************/

/*******************************************************************************
 * DESCRIPTION   : ECC driver header
 ******************************************************************************/

#ifndef ECC_PROTECT
#define ECC_PROTECT
#include "remap_register.h"
#if(__RH850__)
	#include "mem_io.h"
	#include "log.h"
	#define ECM_BASE  (BASE_ECC_ADDR)
	#define DBSC_BASE (BASE_DBSC_ADDR)
#else
	#include <mmio.h>
	#include <debug.h>
	#define ECM_BASE  (0xE6250000U)
	#define DBSC_BASE (0xE6790000U)
#endif/* __RH850__ */

#define RTVRAM_REG_BASE    (0xFFEC0000U)

void enable_ecc(void);
void ecc_rtsram_enable(void);
void edc_axi_enable(void);
void edc_vram_enable(void);

#define DBSC_DBACEN	       	  (DBSC_BASE + 0x0200U)

#define ECMWACNTR             (ECM_BASE + 0x0A04U)
#define ECMWPCNTR             (ECM_BASE + 0x0A00U)
#define ECMERRTGTR0           (ECM_BASE + 0x0200U)
#define ECMERRCTLR0           (ECM_BASE + 0x0000U)
#define ECMERRTGTR1           (ECM_BASE + 0x0200U + 0x4U * 1U)
#define ECMERRCTLR1           (ECM_BASE + 0x0000U + 0x4U * 1U)
#define ECMERRTGTR7           (ECM_BASE + 0x0200U + 0x4U * 7U)
#define ECMERRCTLR7           (ECM_BASE + 0x0000U + 0x4U * 7U)
#define ECMERRTGTR17          (ECM_BASE + 0x0200U + 0x4U * 17U)
#define ECMERRCTLR17          (ECM_BASE + 0x0000U + 0x4U * 17U)
#define ECMERRTGTR39          (ECM_BASE + 0x0200U + 0x4U * 39U)
#define ECMERRCTLR39          (ECM_BASE + 0x0000U + 0x4U * 39U)
#define ECMERRFATALR0         (ECM_BASE + 0x0600U)
#define ECMERRFATALR1         (ECM_BASE + 0x0600U + 0x4U * 1U)
#define ECMERRFATALR7         (ECM_BASE + 0x0600U + 0x4U * 7U)
#define ECMERRFATALR17        (ECM_BASE + 0x0600U + 0x4U * 17U)
#define ECMERRFATALR39        (ECM_BASE + 0x0600U + 0x4U * 39U)

#define DBFSCONF00A           (DBSC_BASE + 0x7640U)
#define DBFSCONF01A           (DBSC_BASE + 0x7644U)
#define DBFSCONF05A           (DBSC_BASE + 0x7654U)
#define DBFSCTRL01A           (DBSC_BASE + 0x7604U)
#define DBFSSTAT01A           (DBSC_BASE + 0x7684U)
#define DBFSSTAT00A           (DBSC_BASE + 0x7680U)
#define DBFSINTENB02A         (DBSC_BASE + 0x7088U)
#define DBFSINTENB04A         (DBSC_BASE + 0x7090U)

#define DBFSDRAMECCAREA00     (DBSC_BASE + 0x7450U)
#define DBFSDRAMECCAREA01     (DBSC_BASE + 0x7454U)
#define DBFSCONFAXI0          (DBSC_BASE + 0x7400U)

#define EDC_CFG	              (RTVRAM_REG_BASE + 0x4110U)

/********************* Set by the user *********************/
/* The row address of ECC Protection Area Size for memory rank 0/1 */
#define ECC_PROT_SIZE0        (0x2000U)
#define ECC_PROT_SIZE1        (0x2000U)

/* Start and End row address of ECC Protection area for rank0 */
#define START_ECC_INIT_AREA0   (0x00000000U)
#define END_ECC_INIT_AREA0     (0x00001FFFU)

/* Start and End row address of ECC Protection area for rank1 */
#define START_ECC_INIT_AREA1   (0x00000000U)
#define END_ECC_INIT_AREA1     (0x00001FFFU)
/***********  Other settings cannot be changed ***************/

#endif/* ECC_PROTECT */
