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 * DISCLAIMER
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 *******************************************************************************/

/*******************************************************************************
 * DESCRIPTION   : remap register header
 ******************************************************************************/

#ifndef REMAP_REGISTER_H_
#define REMAP_REGISTER_H_

#include <stdint.h>

#define REMAP_BASE      (0xFF1FC400U)

#define ICUMX_PROT0PCMD (0xFFFEE090U)
#define ICUMX_PROT0PS   (0xFFFEE094U)
#define PROTCMD_START   (0xA5U)
#define PROTS0ERR       (0x01U)

#define ICU_REMAP0      (0xFC000000U)

/* REMAP setting */
/* Remap ID(0 -- 15) */
#define ICU_REMAP_NUM_RTRAM     (15U)   /* RTRAM */
#define ICU_REMAP_NUM_CC        (14U)   /* CC63S,AXMM,QoS for S4 / V4H */
#define ICU_REMAP_NUM_FCPR      (14U)   /* FCPR for V4M */
#define ICU_REMAP_NUM_PFC       (13U)   /* PFC,GPIO,CPGA,RESET */
#define ICU_REMAP_NUM_ECM       (12U)   /* ECM,AP-System Core */
#define ICU_REMAP_NUM_RPC       (11U)   /* RPC */
#define ICU_REMAP_NUM_RTDMAC    (10U)   /* RT-DMAC0,PFC(MCU) */
#define ICU_REMAP_NUM_SCIF      (9U)    /* SCIF */
#define ICU_REMAP_NUM_MMC       (8U)    /* MMC */
#define ICU_REMAP_NUM_HSCIF     (7U)    /* HSCIF */
#define ICU_REMAP_NUM_DMAC      (6U)    /* SYS-DMAC0 */
#define ICU_REMAP_NUM_RGID      (5U)    /* Region ID */
#if (RCAR_LSI == RCAR_S4)
#define ICU_REMAP_NUM_MCU       (4U)    /* MCU */
#endif

/* SICREMAP2M15 */
#define ICU_REMAP_RTSRAM        (0xEB200000U)   /* RT-SRAM */
/* SICREMAP2M14 */
#define ICU_REMAP_CC            (0xE6600000U)   /* CC63S,AXMM,QoS,FCPR for S4 / V4H */
/* SICREMAP2M14 */
#define ICU_REMAP_FCPR          (0xE6600000U)   /* FCPR for V4M */
/* SICREMAP2M13 */
#define ICU_REMAP_PFC           (0xE6000000U)   /* PFC,GPIO,CPGA,RESET */
/* SICREMAP2M12 */
#define ICU_REMAP_ECM           (0xE6200000U)   /* ECM,AP-System Core */
/* SICREMAP2M11 */
#define ICU_REMAP_RPC           (0xEE200000U)   /* RPC */
/* SICREMAP2M10 */
#define ICU_REMAP_RTDMAC        (0xFFC00000U)   /* RT-DMAC0,PFC(MCU) */
/* SICREMAP2M9 */
#if (RCAR_LSI == RCAR_S4)
#define ICU_REMAP_SCIF          (0xE6C00000U)   /* SCIF3 */
#elif ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M))
#define ICU_REMAP_SCIF          (0xE6E00000U)   /* SCIF0 */
#endif /* RCAR_LSI == RCAR_S4 */
/* SICREMAP2M8 */
#define ICU_REMAP_MMC           (0xEE000000U)   /* MMC */
/* SICREMAP2M7 */
#define ICU_REMAP_HSCIF         (0xE6400000U)   /* HSCIF */
/* SICREMAP2M6 */
#define ICU_REMAP_DMAC          (0xE7200000U)   /* SYS-DMAC0 */
/* SICREMAP2M5 */
#define ICU_REMAP_RGID          (0xE7600000U)   /* Region ID */
#if (RCAR_LSI == RCAR_S4)
/* SICREMAP2M4 */
#define ICU_REMAP_MCU          (0xD8E00000U)   /* MCU */
#endif

#define ICU_REMAP15_BASE        (ICU_REMAP_RTRAM)   /* RTRAM */
#define ICU_REMAP14_BASE        (ICU_REMAP_CC)      /* CC63S,AXMM,QoS,FCPR */
#define ICU_REMAP13_BASE        (ICU_REMAP_PFC)     /* PFC,GPIO,CPGA,RESET */
#define ICU_REMAP12_BASE        (ICU_REMAP_ECM)     /* ECM,AP-System Core */
#define ICU_REMAP11_BASE        (ICU_REMAP_RPC)     /* RPC */
#define ICU_REMAP10_BASE        (ICU_REMAP_RTDMAC)  /* RT-DMAC0 */
#define ICU_REMAP9_BASE         (ICU_REMAP_SCIF)    /* SCIF */
#define ICU_REMAP8_BASE         (ICU_REMAP_MMC)     /* MMC */
#define ICU_REMAP7_BASE         (ICU_REMAP_HSCIF)   /* HSCIF */
#define ICU_REMAP6_BASE         (ICU_REMAP_DMAC)    /* SYS-DMAC0 */
#define ICU_REMAP5_BASE         (ICU_REMAP_RGID)    /* Region ID */
#if (RCAR_LSI == RCAR_S4)
#define ICU_REMAP4_BASE         (ICU_REMAP_MCU)     /* MCU */
#elif ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M))
#define ICU_REMAP4_BASE         (0x00000000U)       /* Reserved */
#endif
#define ICU_REMAP3_BASE         (0x00000000U)       /* Reserved */
#define ICU_REMAP2_BASE         (0x00000000U)       /* Reserved */
#define ICU_REMAP1_BASE         (0x00000000U)       /* Reserved */
#define ICU_REMAP0_BASE         (0x00000000U)       /* Reserved */

/* Base address offset of each register after remap */
/* REMAP15(0xEB200000U) */
/* RT-SRAM */
#define ICU_REMAP_OFFSET_RTSRAM     (0x00000000U)

/* REMAP14(0xE6600000U) */
#define ICU_REMAP_OFFSET_CC63S      (0x00000000U)
#define ICU_REMAP_OFFSET_DBSC       (0x00190000U)   /* (0xE6790000U) */
#define ICU_REMAP_OFFSET_AXMM       (0x00180000U)   /* (0xE6780000U) */
#if (RCAR_LSI == RCAR_S4)
#define ICU_REMAP_OFFSET_CCI        (0x001a0000U)   /* (0xE67A0000U) */
#define ICU_REMAP_OFFSET_QOS        (0x001e0000U)   /* (0xE67E0000U) */
#elif ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M))
#define ICU_REMAP_OFFSET_FCPR       (0x00185700U)   /* (0xE6785700U) */
 #if (RCAR_LSI == RCAR_V4M)
 #define ICU_REMAP_OFFSET_I2C3      (0x000D0000U)   /* (0xE66D0000U) */
 #endif /* (RCAR_LSI == RCAR_V4M) */
#endif /* (RCAR_LSI == RCAR_S4) */

/* REMAP13(0xE6000000U) */
/* PFC */
#define ICU_REMAP_OFFSET_PFC        (0x00050000U)
/* EFUSE */
#define ICU_REMAP_OFFSET_EFUSE      (0x00078800U)
/* CPGA */
#define ICU_REMAP_OFFSET_CPGA       (0x00150000U)
/* RESET */
#define ICU_REMAP_OFFSET_RESET      (0x00160000U)
/* APMU */
#define ICU_REMAP_OFFSET_APMU       (0x00170000U)
/* SYSC */
#define ICU_REMAP_OFFSET_SYSC       (0x00180000U)
/* OTP */
#define ICU_REMAP_OFFSET_OTP        (0x001BF000U)
#if (RCAR_LSI == RCAR_V4M)
#define ICU_REMAP_OFFSET_AVS        (0x000A0000U)   /* (0xE60A0000U) */
#endif /* (RCAR_LSI == RCAR_V4M) */

/* REMAP12(0xE6200000U) */
/* ECM */
#define ICU_REMAP_OFFSET_MFIS       (0x00060000U)
#define ICU_REMAP_OFFSET_SDRAM_ECC  (0x00050000U)
#define ICU_REMAP_OFFSET_AP_CORE    (0x00080000U)

/* REMAP11(0xEE200000U) */
/*RPC*/
#define ICU_REMAP_OFFSET_RPC        (0x00000000U)

/* REMAP10(0xFFC00000U) */
/* RT-DMA */
#define ICU_REMAP_OFFSET_RTDMA0     (0x00010000U)
#define ICU_REMAP_OFFSET_RTDMACTL   (0x00160000U)
#define ICU_REMAP_OFFSET_PFCMCU     (0x00190000U)

#if (RCAR_LSI == RCAR_S4)
/* REMAP9(0xE6C00000U) */
/*SCIF*/
#define ICU_REMAP_OFFSET_SCIF3      (0x00050000U)
#elif ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M))
/* REMAP9(0xE6E00000U) */
/*SCIF*/
#define ICU_REMAP_OFFSET_SCIF0      (0x00060000U)
#endif /* RCAR_LSI == RCAR_S4 */

/* REMAP8(0xEE000000U) */
/* SDHI2/MMC0 */
#define ICU_REMAP_OFFSET_SDHI       (0x00140000U)

/* REMAP7(0xE6400000U) */
/* HSCIF */
#define ICU_REMAP_OFFSET_HSCIF0     (0x00140000U)

/* REMAP6(0xE7200000U) */
/* SYS-DMAC */
#define ICU_REMAP_OFFSET_SYSDMAC    (0x00100000U)

/* REMAP5(0xE7600000U) */
/* Region ID */
#if ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M))
#define ICU_REMAP_OFFSET_ICISTP     (0x00100000U)
#endif
#define ICU_REMAP_OFFSET_RGID       (0x00150000U)

#if (RCAR_LSI == RCAR_S4)
/* REMAP4(0xD8E00000U) */
/* MCU */
#define ICU_REMAP_OFFSET_MCU        (0x00100000U)
#endif

/* REMAP15(0xEB200000U) */
#define BASE_RTSRAM_ADDR        (icu_remap_calc(ICU_REMAP_NUM_RTRAM) + ICU_REMAP_OFFSET_RTSRAM)
/* REMAP14(0xE6600000U) */
#define BASE_DBSC_ADDR          (icu_remap_calc(ICU_REMAP_NUM_CC) + ICU_REMAP_OFFSET_DBSC)
#define BASE_AXMM_ADDR          (icu_remap_calc(ICU_REMAP_NUM_CC) + ICU_REMAP_OFFSET_AXMM)
#if (RCAR_LSI == RCAR_S4)
#define BASE_CCI_ADDR           (icu_remap_calc(ICU_REMAP_NUM_CC) + ICU_REMAP_OFFSET_CCI)
#define BASE_QOS_ADDR           (icu_remap_calc(ICU_REMAP_NUM_CC) + ICU_REMAP_OFFSET_QOS)
#elif ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M))
#define BASE_FCPR_ADDR          (icu_remap_calc(ICU_REMAP_NUM_CC) + ICU_REMAP_OFFSET_FCPR)
 #if (RCAR_LSI == RCAR_V4M)
 #define BASE_I2C3_ADDR         (icu_remap_calc(ICU_REMAP_NUM_CC) + ICU_REMAP_OFFSET_I2C3)
 #endif /* (RCAR_LSI == RCAR_V4M) */
#endif /* (RCAR_LSI == RCAR_S4) */
/* REMAP13(0xE6000000U) */
#define BASE_EFUSE_ADDR         (icu_remap_calc(ICU_REMAP_NUM_PFC) + ICU_REMAP_OFFSET_EFUSE)
#define BASE_PFC_ADDR           (icu_remap_calc(ICU_REMAP_NUM_PFC) + ICU_REMAP_OFFSET_PFC)
#define BASE_CPG_ADDR           (icu_remap_calc(ICU_REMAP_NUM_PFC) + ICU_REMAP_OFFSET_CPGA)
#define BASE_RESET_ADDR         (icu_remap_calc(ICU_REMAP_NUM_PFC) + ICU_REMAP_OFFSET_RESET)
#define BASE_APMU_ADDR          (icu_remap_calc(ICU_REMAP_NUM_PFC) + ICU_REMAP_OFFSET_APMU)
#define BASE_SYSC_ADDR          (icu_remap_calc(ICU_REMAP_NUM_PFC) + ICU_REMAP_OFFSET_SYSC)
#define BASE_OTP_MEM_ADDR       (icu_remap_calc(ICU_REMAP_NUM_PFC) + ICU_REMAP_OFFSET_OTP)
#if (RCAR_LSI == RCAR_V4M)
#define BASE_AVS_ADDR           (icu_remap_calc(ICU_REMAP_NUM_PFC) + ICU_REMAP_OFFSET_AVS)
#endif /* (RCAR_LSI == RCAR_V4M) */
/* REMAP12(0xE6200000U) */
#if ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M))
#define BASE_ECM_ADDR           (icu_remap_calc(ICU_REMAP_NUM_ECM))
#endif
#define BASE_MFIS_ADDR          (icu_remap_calc(ICU_REMAP_NUM_ECM) + ICU_REMAP_OFFSET_MFIS)
#define BASE_ECC_ADDR           (icu_remap_calc(ICU_REMAP_NUM_ECM) + ICU_REMAP_OFFSET_SDRAM_ECC)
#define BASE_AP_CORE_ADDR       (icu_remap_calc(ICU_REMAP_NUM_ECM) + ICU_REMAP_OFFSET_AP_CORE)
/* REMAP11(0xEE200000U) */
#define BASE_RPC_ADDR           (icu_remap_calc(ICU_REMAP_NUM_RPC) + ICU_REMAP_OFFSET_RPC)
/* REMAP10(0xFFC00000U) */
#define BASE_RTDMA0_ADDR        (icu_remap_calc(ICU_REMAP_NUM_RTDMAC) + ICU_REMAP_OFFSET_RTDMA0)
#define BASE_RTDMACTL_ADDR      (icu_remap_calc(ICU_REMAP_NUM_RTDMAC) + ICU_REMAP_OFFSET_RTDMACTL)
#if (RCAR_LSI == RCAR_S4)
#define BASE_PFCMCU_ADDR        (icu_remap_calc(ICU_REMAP_NUM_RTDMAC) + ICU_REMAP_OFFSET_PFCMCU)
#endif
#if (RCAR_LSI == RCAR_S4)
/* REMAP9(0xE6C00000U) */
#define BASE_SCIF_ADDR          (icu_remap_calc(ICU_REMAP_NUM_SCIF) + ICU_REMAP_OFFSET_SCIF3)
#elif ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M))
/* REMAP9(0xE6E00000U) */
#define BASE_SCIF_ADDR          (icu_remap_calc(ICU_REMAP_NUM_SCIF) + ICU_REMAP_OFFSET_SCIF0)
#endif /* RCAR_LSI == RCAR_S4 */
/* REMAP8(0xEE000000U) */
#define BASE_MMC0_ADDR          (icu_remap_calc(ICU_REMAP_NUM_MMC) + ICU_REMAP_OFFSET_SDHI)
/* REMAP7(0xE6400000U) */
#define BASE_HSCIF_ADDR         (icu_remap_calc(ICU_REMAP_NUM_HSCIF) + ICU_REMAP_OFFSET_HSCIF0)
/* REMAP6(0xE7200000U) */
#define BASE_DMA_ADDR           (icu_remap_calc(ICU_REMAP_NUM_DMAC) + ICU_REMAP_OFFSET_SYSDMAC)
/* REMAP5(0xE7600000U) */
#if ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M))
#define BASE_ICISTP_ADDR        (icu_remap_calc(ICU_REMAP_NUM_RGID) + ICU_REMAP_OFFSET_ICISTP)
#endif
#define BASE_RGID_ADDR          (icu_remap_calc(ICU_REMAP_NUM_RGID) + ICU_REMAP_OFFSET_RGID)
#if (RCAR_LSI == RCAR_S4)
/* REMAP4(0xD8E00000U) */
#define BASE_MCU_ADDR           (icu_remap_calc(ICU_REMAP_NUM_MCU) + ICU_REMAP_OFFSET_MCU)
#endif

/* Calculate the base address of each register after remapping */
static inline uint32_t icu_remap_calc(uint32_t num)
{
    return (ICU_REMAP0 + (num * 0x00200000U));
}
/* End of function icu_remap_calc(uint32_t num) */

#endif /* REMAP_REGISTER_H_ */
