/*
 * Copyright (c) 2015-2021, Renesas Electronics Corporation
 * All rights reserved.
 */

#ifndef DMA_REGISTER_H__
#define DMA_REGISTER_H__

#include "cpg_register.h"

#define DMACH   1U  /* DMA CH setting (1-15) */

#define CPG_RMSTPCR0    (CPG_BASE + 0x0110U)
#define RT_DMAC_BIT (0x00200000U)
#define DMA_BASE    (0xFFC10000U)

/* DMA operation 0 */
#define DMA_RDMOR   (DMA_BASE + 0x0060U)
/* DMA secure control */
#define DMA_RDMSEC  (DMA_BASE + 0x0030U)
/* DMA channel clear */
#define DMA_RDMCHCLR    (DMA_BASE + 0x0080U)
/* DMA source address */
#define DMA_RDMSAR  (DMA_BASE + (DMACH * 0x80U) + 0x8000U)
/* DMA destination address */
#define DMA_RDMDAR  (DMA_BASE + (DMACH * 0x80U) + 0x8004U)
/* DMA transfer count */
#define DMA_RDMTCR  (DMA_BASE + (DMACH * 0x80U) + 0x8008U)
/* DMA channel control */
#define DMA_RDMCHCR (DMA_BASE + (DMACH * 0x80U) + 0x800CU)

#endif  /* DMA_REGISTER_H__ */

