/*******************************************************************************
 * Copyright (c) 2018-2021 Renesas Electronics Corporation. All rights reserved.
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 *
 * This software is provided as reference/sample code under the license
 * agreement between Renesas Electronics Corporation and licensee (the
 * "License Agreement") and shall be treated as specified in the License
 * Agreement.
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 ******************************************************************************/

/*******************************************************************************
 * DESCRIPTION   : AXI-Bus register header
 ******************************************************************************/

#ifndef AXI_REGISTER_H_
#define AXI_REGISTER_H_

#include <remap_register.h>

/* AXI base address */
#define AXI_BASE    (BASE_AXI_ADDR)

/* SDRAM protection */
#define DPTDIVCR0   (AXI_BASE + 0x4400U)    /* AXI dram protected area division 0 */
#define DPTDIVCR1   (AXI_BASE + 0x4404U)    /* AXI dram protected area division 1 */
#define DPTDIVCR2   (AXI_BASE + 0x4408U)    /* AXI dram protected area division 2 */
#define DPTDIVCR3   (AXI_BASE + 0x440CU)    /* AXI dram protected area division 3 */
#define DPTDIVCR4   (AXI_BASE + 0x4410U)    /* AXI dram protected area division 4 */
#define DPTDIVCR5   (AXI_BASE + 0x4414U)    /* AXI dram protected area division 5 */
#define DPTDIVCR6   (AXI_BASE + 0x4418U)    /* AXI dram protected area division 6 */
#define DPTDIVCR7   (AXI_BASE + 0x441CU)    /* AXI dram protected area division 7 */
#define DPTDIVCR8   (AXI_BASE + 0x4420U)    /* AXI dram protected area division 8 */
#define DPTDIVCR9   (AXI_BASE + 0x4424U)    /* AXI dram protected area division 9 */
#define DPTDIVCR10  (AXI_BASE + 0x4428U)    /* AXI dram protected area division 10 */
#define DPTDIVCR11  (AXI_BASE + 0x442CU)    /* AXI dram protected area division 11 */
#define DPTDIVCR12  (AXI_BASE + 0x4430U)    /* AXI dram protected area division 12 */
#define DPTDIVCR13  (AXI_BASE + 0x4434U)    /* AXI dram protected area division 13 */
#define DPTDIVCR14  (AXI_BASE + 0x4438U)    /* AXI dram protected area division 14 */

#define DPTCR0      (AXI_BASE + 0x4440U)    /* AXI dram protected area setting 0 */
#define DPTCR1      (AXI_BASE + 0x4444U)    /* AXI dram protected area setting 1 */
#define DPTCR2      (AXI_BASE + 0x4448U)    /* AXI dram protected area setting 2 */
#define DPTCR3      (AXI_BASE + 0x444CU)    /* AXI dram protected area setting 3 */
#define DPTCR4      (AXI_BASE + 0x4450U)    /* AXI dram protected area setting 4 */
#define DPTCR5      (AXI_BASE + 0x4454U)    /* AXI dram protected area setting 5 */
#define DPTCR6      (AXI_BASE + 0x4458U)    /* AXI dram protected area setting 6 */
#define DPTCR7      (AXI_BASE + 0x445CU)    /* AXI dram protected area setting 7 */
#define DPTCR8      (AXI_BASE + 0x4460U)    /* AXI dram protected area setting 8 */
#define DPTCR9      (AXI_BASE + 0x4464U)    /* AXI dram protected area setting 9 */
#define DPTCR10     (AXI_BASE + 0x4468U)    /* AXI dram protected area setting 10 */
#define DPTCR11     (AXI_BASE + 0x446CU)    /* AXI dram protected area setting 11 */
#define DPTCR12     (AXI_BASE + 0x4470U)    /* AXI dram protected area setting 12 */
#define DPTCR13     (AXI_BASE + 0x4474U)    /* AXI dram protected area setting 13 */
#define DPTCR14     (AXI_BASE + 0x4478U)    /* AXI dram protected area setting 14 */
#define DPTCR15     (AXI_BASE + 0x447CU)    /* AXI dram protected area setting 15 */

/* System RAM protection */
#define SPTDIVCR0   (AXI_BASE + 0x4500U)    /* AXI system ram protected area division 0 */
#define SPTDIVCR1   (AXI_BASE + 0x4504U)    /* AXI system ram protected area division 1 */
#define SPTDIVCR2   (AXI_BASE + 0x4508U)    /* AXI system ram protected area division 2 */
#define SPTDIVCR3   (AXI_BASE + 0x450CU)    /* AXI system ram protected area division 3 */
#define SPTDIVCR4   (AXI_BASE + 0x4510U)    /* AXI system ram protected area division 4 */
#define SPTDIVCR5   (AXI_BASE + 0x4514U)    /* AXI system ram protected area division 5 */
#define SPTDIVCR6   (AXI_BASE + 0x4518U)    /* AXI system ram protected area division 6 */
#define SPTDIVCR7   (AXI_BASE + 0x451CU)    /* AXI system ram protected area division 7 */
#define SPTDIVCR8   (AXI_BASE + 0x4520U)    /* AXI system ram protected area division 8 */
#define SPTDIVCR9   (AXI_BASE + 0x4524U)    /* AXI system ram protected area division 9 */
#define SPTDIVCR10  (AXI_BASE + 0x4528U)    /* AXI system ram protected area division 10 */
#define SPTDIVCR11  (AXI_BASE + 0x452CU)    /* AXI system ram protected area division 11 */
#define SPTDIVCR12  (AXI_BASE + 0x4530U)    /* AXI system ram protected area division 12 */
#define SPTDIVCR13  (AXI_BASE + 0x4534U)    /* AXI system ram protected area division 13 */
#define SPTDIVCR14  (AXI_BASE + 0x4538U)    /* AXI system ram protected area division 14 */

#define SPTCR0      (AXI_BASE + 0x4540U)    /* AXI system ram protected area setting 0 */
#define SPTCR1      (AXI_BASE + 0x4544U)    /* AXI system ram protected area setting 1 */
#define SPTCR2      (AXI_BASE + 0x4548U)    /* AXI system ram protected area setting 2 */
#define SPTCR3      (AXI_BASE + 0x454CU)    /* AXI system ram protected area setting 3 */
#define SPTCR4      (AXI_BASE + 0x4550U)    /* AXI system ram protected area setting 4 */
#define SPTCR5      (AXI_BASE + 0x4554U)    /* AXI system ram protected area setting 5 */
#define SPTCR6      (AXI_BASE + 0x4558U)    /* AXI system ram protected area setting 6 */
#define SPTCR7      (AXI_BASE + 0x455CU)    /* AXI system ram protected area setting 7 */
#define SPTCR8      (AXI_BASE + 0x4560U)    /* AXI system ram protected area setting 8 */
#define SPTCR9      (AXI_BASE + 0x4564U)    /* AXI system ram protected area setting 9 */
#define SPTCR10     (AXI_BASE + 0x4568U)    /* AXI system ram protected area setting 10 */
#define SPTCR11     (AXI_BASE + 0x456CU)    /* AXI system ram protected area setting 11 */
#define SPTCR12     (AXI_BASE + 0x4570U)    /* AXI system ram protected area setting 12 */
#define SPTCR13     (AXI_BASE + 0x4574U)    /* AXI system ram protected area setting 13 */
#define SPTCR14     (AXI_BASE + 0x4578U)    /* AXI system ram protected area setting 14 */
#define SPTCR15     (AXI_BASE + 0x457CU)    /* AXI system ram protected area setting 15 */

#define EDCINTEN0   (0xFF840040U)            /* EDC Interrupt Enable Register 0 */
#define EDCINTEN1   (0xFF840044U)            /* EDC Interrupt Enable Register 1 */
#define EDCINTEN2   (0xFF840048U)            /* EDC Interrupt Enable Register 2 */
#define EDCINTEN3   (0xFF84004CU)            /* EDC Interrupt Enable Register 3 */
#define EDCINTEN5   (0xFF8401C0U)            /* EDC Interrupt Enable Register 5 */
#define EDCINTEN6   (0xFF8401C4U)            /* EDC Interrupt Enable Register 6 */
#define EDCINTEN7   (0xFF8401C8U)            /* EDC Interrupt Enable Register 8 */

#define EDC_CFG     (0xFFE90110U)            /* EDC Error control Register(RT-SRAM) V3H_2 */

#endif /* AXI_REGISTER_H_ */
