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 *
 * This software is provided as reference/sample code under the license
 * agreement between Renesas Electronics Corporation and licensee (the
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 * Agreement.
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 ******************************************************************************/

/*******************************************************************************
 * DESCRIPTION   : RPC register header
 ******************************************************************************/

#ifndef RPC_REGISTER_H_
#define RPC_REGISTER_H_


#include <remap_register.h>

/* RPC base address */
/* 0xEE200000 */
#define RPC_BASE    (BASE_RPC_ADDR)

#define RPC_CMNCR       (RPC_BASE + 0x0000U)    /*  Common control register */
#define RPC_SSLDR       (RPC_BASE + 0x0004U)    /*  SSL delay register */
#define RPC_DRCR        (RPC_BASE + 0x000CU)    /*  Data read control register */
#define RPC_DRCMR       (RPC_BASE + 0x0010U)    /*  Data read command setting register */
#define RPC_DREAR       (RPC_BASE + 0x0014U)    /*  Data read extended address register */
#define RPC_DRENR       (RPC_BASE + 0x001CU)    /*  Data read enable setting register */
#define RPC_SMCR        (RPC_BASE + 0x0020U)    /*  Manual mode control register */
#define RPC_SMCMR       (RPC_BASE + 0x0024U)    /*  Manual mode command setting register */
#define RPC_SMADR       (RPC_BASE + 0x0028U)    /*  Manual mode address setting register */
#define RPC_SMOPR       (RPC_BASE + 0x002CU)    /*  Manual mode option setting register */
#define RPC_SMENR       (RPC_BASE + 0x0030U)    /*  Manual mode enable setting register */
#define RPC_SMRDR0      (RPC_BASE + 0x0038U)    /*  Manual mode read data register 0 */
#define RPC_SMRDR1      (RPC_BASE + 0x003CU)    /*  Manual mode read data register 1 */
#define RPC_SMWDR0      (RPC_BASE + 0x0040U)    /*  Manual mode write data register 0 */
#define RPC_CMNSR       (RPC_BASE + 0x0048U)    /*  Common status register */
#define RPC_DRDMCR      (RPC_BASE + 0x0058U)    /*  Data read dummy cycle setting register */
#define RPC_DRDRENR     (RPC_BASE + 0x005CU)    /*  Data read DDR enable register */
#define RPC_SMDMCR      (RPC_BASE + 0x0060U)    /*  Manual mode dummy cycle setting register */
#define RPC_SMDRENR     (RPC_BASE + 0x0064U)    /*  Manual mode DDR enable registerv */
#define RPC_PHYCNT      (RPC_BASE + 0x007CU)    /*  PHY control register */
#define RPC_OFFSET1     (RPC_BASE + 0x0080U)    /*  DDR operation */
#define RPC_OFFSET2     (RPC_BASE + 0x0084U)    /*   */
#define RPC_PHYINT      (RPC_BASE + 0x0088U)    /*  PHY interrupt register */
#define RPC_SEC_CONF    (RPC_BASE + 0x00B8U)    /*  Secure configuration register */
#endif /* RPC_REGISTER_H_ */
