/*
 * Copyright (c) 2018 Renesas Electronics Corporation. All rights reserved.
 */

#ifndef REG_RCARGEN3_H
#define REG_RCARGEN3_H

//CPG
#define	CPG_CPGWPCR						0xE6150904	// R/W	32	CPG Write Protect Control Register
#define	CPG_CPGWPR						0xE6150900	// R/W	32	CPG Write Protect Register
#define	CPG_FRQCRB						0xE6150004	// R/W	32	Frequency control register B
#define	CPG_FRQCRC						0xE61500E0	// R/W	32	Frequency control register C
#define	CPG_PLLECR						0xE61500D0	// R/W	32	PLL Enable Control Register
#define	CPG_PLL0CR						0xE61500D8	// R/W	32	PLL0 control register
#define	CPG_PLL2CR						0xE615002C	// R/W	32	PLL2 control register
#define	CPG_PLL3CR						0xE61500DC	// R/W	32	PLL2 control register
#define	CPG_PLL0STPCR					0xE61500F0	// R/W	32	PLL0 Stop Condition Register
#define	CPG_PLL2STPCR					0xE61500F8	// R/W	32	PLL2 Stop Condition Register
#define	CPG_PLL3STPCR					0xE61500FC	// R/W	32	PLL3 Stop Condition Register
#define	CPG_PLL4STPCR					0xE61501F8	// R/W	32	PLL4 Stop Condition Register
#define	CPG_SD0CKCR						0xE6150074	// R/W	32	SD-IF0 clock frequency control register
#define	CPG_SD1CKCR						0xE6150078	// R/W	32	SD-IF1 clock frequency control register
#define	CPG_SD2CKCR						0xE6150268	// R/W	32	SD-IF2 clock frequency control register
#define	CPG_SD3CKCR						0xE615026C	// R/W	32	SD-IF3 clock frequency control register
#define	CPG_RPCCKCR						0xE6150238	// R/W	32	RPC clock frequency control register
#define	CPG_SSPSRCCKCR					0xE6150248	// R/W	32	SSPSRC clock frequency control register
#define	CPG_SSPRSCKCR					0xE615024C	// R/W	32	SSPRS clock frequency control register
#define	CPG_CANFDCKCR					0xE6150244	// R/W	32	CAN-FD clock frequency control register
#define	CPG_MSOCKCR						0xE6150014	// R/W	32	MSIOF clock frequency control register
#define	CPG_HDMICKCR					0xE6150250	// R/W	32	HDMI-IF clock frequency control register
#define	CPG_CSI0CKCR					0xE615000C	// R/W	32	CSI0 clock frequency control register
#define	CPG_CSIREFCKCR					0xE6150034	// R/W	32	CSIREF clock frequency control register
#define	CPG_RCKCR						0xE6150240	// R/W	32	RCLK frequency control register
#define	CPG_DVFSCR0						0xE6150058	// R/W	32	DVFS control register 0
#define	CPG_DVFSCR1						0xE615005C	// R/W	32	DVFS control register 1
#define	CPG_FSAPBR						0xE6150700	// R/W	32	Functional safety of APB bus interface register
#define	CPG_FSCLKCSR					0xE6150704	// R/W	32	Functional safety of clocks control/status register
#define	CPG_FSCNTCHKH0					0xE6150710	// R/W	32	Functional safety of clocks counter check H register 0
#define	CPG_FSCNTCHKH1					0xE6150714	// R/W	32	Functional safety of clocks counter check H register 1
#define	CPG_FSCNTCHKH2					0xE6150718	// R/W	32	Functional safety of clocks counter check H register 2
#define	CPG_FSCNTCHKH3					0xE615071C	// R/W	32	Functional safety of clocks counter check H register 3
#define	CPG_FSCNTCHKH4					0xE6150720	// R/W	32	Functional safety of clocks counter check H register 4
#define	CPG_FSCNTCHKH5					0xE6150724	// R/W	32	Functional safety of clocks counter check H register 5
#define	CPG_FSCNTCHKH6					0xE6150728	// R/W	32	Functional safety of clocks counter check H register 6
#define	CPG_FSCNTCHKL0					0xE6150730	// R/W	32	Functional safety of clocks counter check L register 0
#define	CPG_FSCNTCHKL1					0xE6150734	// R/W	32	Functional safety of clocks counter check L register 1
#define	CPG_FSCNTCHKL2					0xE6150738	// R/W	32	Functional safety of clocks counter check L register 2
#define	CPG_FSCNTCHKL3					0xE615073C	// R/W	32	Functional safety of clocks counter check L register 3
#define	CPG_FSCNTCHKL4					0xE6150740	// R/W	32	Functional safety of clocks counter check L register 4
#define	CPG_FSCNTCHKL5					0xE6150744	// R/W	32	Functional safety of clocks counter check L register 5
#define	CPG_FSCNTCHKL6					0xE6150748	// R/W	32	Functional safety of clocks counter check L register 6
#define	CPG_FSCNTMON0					0xE6150750	// R	32	Functional safety of clocks monitor register 0
#define	CPG_FSCNTMON1					0xE6150754	// R	32	Functional safety of clocks monitor register 1
#define	CPG_FSCNTMON2					0xE6150758	// R	32	Functional safety of clocks monitor register 2
#define	CPG_FSCNTMON3					0xE615075C	// R	32	Functional safety of clocks monitor register 3
#define	CPG_FSCNTMON4					0xE6150760	// R	32	Functional safety of clocks monitor register 4
#define	CPG_FSCNTMON5					0xE6150764	// R	32	Functional safety of clocks monitor register 5
#define	CPG_FSCNTMON6					0xE6150768	// R	32	Functional safety of clocks monitor register 6
#define	CPG_FSRCHKRA0					0xE6150A00	// R	32	Functional safety reset check register A 0
#define	CPG_FSRCHKRA1					0xE6150A04	// R	32	Functional safety reset check register A 1
#define	CPG_FSRCHKRA2					0xE6150A08	// R	32	Functional safety reset check register A 2
#define	CPG_FSRCHKRA3					0xE6150A0C	// R	32	Functional safety reset check register A 3
#define	CPG_FSRCHKRA4					0xE6150A10	// R	32	Functional safety reset check register A 4
#define	CPG_FSRCHKRA5					0xE6150A14	// R	32	Functional safety reset check register A 5
#define	CPG_FSRCHKRA6					0xE6150A18	// R	32	Functional safety reset check register A 6
#define	CPG_FSRCHKRA7					0xE6150A1C	// R	32	Functional safety reset check register A 7
#define	CPG_FSRCHKRA8					0xE6150A20	// R	32	Functional safety reset check register A 8
#define	CPG_FSRCHKRA9					0xE6150A24	// R	32	Functional safety reset check register A 9
#define	CPG_FSRCHKRA10					0xE6150A28	// R	32	Functional safety reset check register A 10
#define	CPG_FSRCHKRA11					0xE6150A2C	// R	32	Functional safety reset check register A 11
#define	CPG_FSRCHKRA12					0xE6150A30	// R	32	Functional safety reset check register A 12
#define	CPG_FSRCHKRA13					0xE6150A34	// R	32	Functional safety reset check register A 13
#define	CPG_FSRCHKRA14					0xE6150A38	// R	32	Functional safety reset check register A 14
#define	CPG_FSRCHKRA15					0xE6150A3C	// R	32	Functional safety reset check register A 15
#define	CPG_FSRCHKRA16					0xE6150B50	// R	32	Functional safety reset check register A 16
#define	CPG_FSRCHKRA17					0xE6150B54	// R	32	Functional safety reset check register A 17
#define	CPG_FSRCHKRA18					0xE6150B58	// R	32	Functional safety reset check register A 18
#define	CPG_FSRCHKRB0					0xE6150A30	// R	32	Functional safety reset check register B 0
#define	CPG_FSRCHKRB1					0xE6150A34	// R	32	Functional safety reset check register B 1
#define	CPG_FSRCHKRB2					0xE6150A38	// R	32	Functional safety reset check register B 2
#define	CPG_FSRCHKRB3					0xE6150A3C	// R	32	Functional safety reset check register B 3
#define	CPG_FSRCHKRB4					0xE6150A40	// R	32	Functional safety reset check register B 4
#define	CPG_FSRCHKRB5					0xE6150A44	// R	32	Functional safety reset check register B 5
#define	CPG_FSRCHKRB6					0xE6150A48	// R	32	Functional safety reset check register B 6
#define	CPG_FSRCHKRB7					0xE6150A4C	// R	32	Functional safety reset check register B 7
#define	CPG_FSRCHKRB8					0xE6150A50	// R	32	Functional safety reset check register B 8
#define	CPG_FSRCHKRB9					0xE6150A54	// R	32	Functional safety reset check register B 9
#define	CPG_FSRCHKRB10					0xE6150A58	// R	32	Functional safety reset check register B 10
#define	CPG_FSRCHKRB11					0xE6150A5C	// R	32	Functional safety reset check register B 11
#define	CPG_FSRCHKRB13					0xE6150A74	// R	32	Functional safety reset check register B 13
#define	CPG_FSRCHKSETR0					0xE6150A60	// W	32	Functional safety reset check set register 0
#define	CPG_FSRCHKSETR1					0xE6150A64	// W	32	Functional safety reset check set register 1
#define	CPG_FSRCHKSETR2					0xE6150A68	// W	32	Functional safety reset check set register 2
#define	CPG_FSRCHKSETR3					0xE6150A6C	// W	32	Functional safety reset check set register 3
#define	CPG_FSRCHKSETR4					0xE6150A70	// W	32	Functional safety reset check set register 4
#define	CPG_FSRCHKSETR5					0xE6150A74	// W	32	Functional safety reset check set register 5
#define	CPG_FSRCHKSETR6					0xE6150A78	// W	32	Functional safety reset check set register 6
#define	CPG_FSRCHKSETR7					0xE6150A7C	// W	32	Functional safety reset check set register 7
#define	CPG_FSRCHKSETR8					0xE6150A80	// W	32	Functional safety reset check set register 8
#define	CPG_FSRCHKSETR9					0xE6150A84	// W	32	Functional safety reset check set register 9
#define	CPG_FSRCHKSETR10				0xE6150A88	// W	32	Functional safety reset check set register 10
#define	CPG_FSRCHKSETR11				0xE6150A8C	// W	32	Functional safety reset check set register 11
#define	CPG_FSRCHKSETR12				0xE6150AB0	// W	32	Functional safety reset check set register 12
#define	CPG_FSRCHKSETR13				0xE6150AB4	// W	32	Functional safety reset check set register 13
#define	CPG_FSRCHKSETR14				0xE6150AB8	// W	32	Functional safety reset check set register 14
#define	CPG_FSRCHKSETR15				0xE6150ABC	// W	32	Functional safety reset check set register 15
#define	CPG_FSRCHKSETR16				0xE6150B60	// W	32	Functional safety reset check set register 16
#define	CPG_FSRCHKSETR17				0xE6150B64	// W	32	Functional safety reset check set register 17
#define	CPG_FSRCHKSETR18				0xE6150B68	// W	32	Functional safety reset check set register 18
#define	CPG_FSRCHKCLRR0					0xE6150A90	// W	32	Functional safety reset check clear register 0
#define	CPG_FSRCHKCLRR1					0xE6150A94	// W	32	Functional safety reset check clear register 1
#define	CPG_FSRCHKCLRR2					0xE6150A98	// W	32	Functional safety reset check clear register 2
#define	CPG_FSRCHKCLRR3					0xE6150A9C	// W	32	Functional safety reset check clear register 3
#define	CPG_FSRCHKCLRR4					0xE6150AA0	// W	32	Functional safety reset check clear register 4
#define	CPG_FSRCHKCLRR5					0xE6150AA4	// W	32	Functional safety reset check clear register 5
#define	CPG_FSRCHKCLRR6					0xE6150AA8	// W	32	Functional safety reset check clear register 6
#define	CPG_FSRCHKCLRR7					0xE6150AAC	// W	32	Functional safety reset check clear register 7
#define	CPG_FSRCHKCLRR8					0xE6150AB0	// W	32	Functional safety reset check clear register 8
#define	CPG_FSRCHKCLRR9					0xE6150AB4	// W	32	Functional safety reset check clear register 9
#define	CPG_FSRCHKCLRR10				0xE6150AB8	// W	32	Functional safety reset check clear register 10
#define	CPG_FSRCHKCLRR11				0xE6150ABC	// W	32	Functional safety reset check clear register 11
#define	CPG_FSRCHKCLRR12				0xE6150AF0	// W	32	Functional safety reset check clear register 12
#define	CPG_FSRCHKCLRR13				0xE6150AF4	// W	32	Functional safety reset check clear register 13
#define	CPG_FSRCHKCLRR14				0xE6150AF8	// W	32	Functional safety reset check clear register 14
#define	CPG_FSRCHKCLRR15				0xE6150AFC	// W	32	Functional safety reset check clear register 15
#define	CPG_FSRCHKCLRR16				0xE6150B70	// W	32	Functional safety reset check clear register 16
#define	CPG_FSRCHKCLRR17				0xE6150B74	// W	32	Functional safety reset check clear register 17
#define	CPG_FSRCHKCLRR18				0xE6150B78	// W	32	Functional safety reset check clear register 18
#define	CPG_FSSEQCHKR					0xE6150AF0	// R	32	Functional safety Power on sequence Check Register
#define	CPG_FSSEQCHKCSR					0xE6150AF4	// R/W	32	Functional safety Power on sequence Check Control/Status Register


//GPIO
#define	GPIO_IOINTSEL0					0xE6050000	// R/W	32	General IO/interrupt switching register 0
#define	GPIO_INOUTSEL0					0xE6050004	// R/W	32	General input/output switching register 0
#define	GPIO_OUTDT0						0xE6050008	// R/W	32	General output register 0
#define	GPIO_INDT0						0xE605000C	// R	32	General input register 0
#define	GPIO_INTDT0						0xE6050010	// R	32	Interrupt display register 0
#define	GPIO_INTCLR0					0xE6050014	// R/W	32	Interrupt clear register 0
#define	GPIO_INTMSK0					0xE6050018	// R/W	32	Interrupt mask register 0
#define	GPIO_MSKCLR0					0xE605001C	// R/W	32	Interrupt mask clear register 0
#define	GPIO_POSNEG0					0xE6050020	// R/W	32	Positive/negative logic select register 0
#define	GPIO_EDGLEVEL0					0xE6050024	// R/W	32	Edge/level select register 0
#define	GPIO_FILONOFF0					0xE6050028	// R/W	32	Chattering prevention on/off register 0
#define	GPIO_INTMSKS0					0xE6050038	// R/W	32	Interrupt sub mask register 0
#define	GPIO_MSKCLRS0					0xE605003C	// R/W	32	Interrupt sub mask clear register 0
#define	GPIO_OUTDTSEL0					0xE6050040	// R/W	32	Output data select register 0
#define	GPIO_OUTDTH0					0xE6050044	// R/W	32	Output data high register 0
#define	GPIO_OUTDTL0					0xE6050048	// R/W	32	Output data low register 0
#define	GPIO_BOTHEDGE0					0xE605004C	// R/W	32	One edge/both edge select register 0
#define	GPIO_IOINTSEL1					0xE6051000	// R/W	32	General IO/interrupt switching register 1
#define	GPIO_INOUTSEL1					0xE6051004	// R/W	32	General input/output switching register 1
#define	GPIO_OUTDT1						0xE6051008	// R/W	32	General output register 1
#define	GPIO_INDT1						0xE605100C	// R	32	General input register 1
#define	GPIO_INTDT1						0xE6051010	// R	32	Interrupt display register 1
#define	GPIO_INTCLR1					0xE6051014	// R/W	32	Interrupt clear register 1
#define	GPIO_INTMSK1					0xE6051018	// R/W	32	Interrupt mask register 1
#define	GPIO_MSKCLR1					0xE605101C	// R/W	32	Interrupt mask clear register 1
#define	GPIO_POSNEG1					0xE6051020	// R/W	32	Positive/negative logic select register 1
#define	GPIO_EDGLEVEL1					0xE6051024	// R/W	32	Edge/level select register 1
#define	GPIO_FILONOFF1					0xE6051028	// R/W	32	Chattering prevention on/off register 1
#define	GPIO_INTMSKS1					0xE6051038	// R/W	32	Interrupt sub mask register 1
#define	GPIO_MSKCLRS1					0xE605103C	// R/W	32	Interrupt sub mask clear register 1
#define	GPIO_OUTDTSEL1					0xE6051040	// R/W	32	Output data select register 1
#define	GPIO_OUTDTH1					0xE6051044	// R/W	32	Output data high register 1
#define	GPIO_OUTDTL1					0xE6051048	// R/W	32	Output data low register 1
#define	GPIO_BOTHEDGE1					0xE605104C	// R/W	32	One edge/both edge select register 1
#define	GPIO_IOINTSEL2					0xE6052000	// R/W	32	General IO/interrupt switching register 2
#define	GPIO_INOUTSEL2					0xE6052004	// R/W	32	General input/output switching register 2
#define	GPIO_OUTDT2						0xE6052008	// R/W	32	General output register 2
#define	GPIO_INDT2						0xE605200C	// R	32	General input register 2
#define	GPIO_INTDT2						0xE6052010	// R	32	Interrupt display register 2
#define	GPIO_INTCLR2					0xE6052014	// R/W	32	Interrupt clear register 2
#define	GPIO_INTMSK2					0xE6052018	// R/W	32	Interrupt mask register 2
#define	GPIO_MSKCLR2					0xE605201C	// R/W	32	Interrupt mask clear register 2
#define	GPIO_POSNEG2					0xE6052020	// R/W	32	Positive/negative logic select register 2
#define	GPIO_EDGLEVEL2					0xE6052024	// R/W	32	Edge/level select register 2
#define	GPIO_FILONOFF2					0xE6052028	// R/W	32	Chattering prevention on/off register 2
#define	GPIO_INTMSKS2					0xE6052038	// R/W	32	Interrupt sub mask register 2
#define	GPIO_MSKCLRS2					0xE605203C	// R/W	32	Interrupt sub mask clear register 2
#define	GPIO_OUTDTSEL2					0xE6052040	// R/W	32	Output data select register 2
#define	GPIO_OUTDTH2					0xE6052044	// R/W	32	Output data high register 2
#define	GPIO_OUTDTL2					0xE6052048	// R/W	32	Output data low register 2
#define	GPIO_BOTHEDGE2					0xE605204C	// R/W	32	One edge/both edge select register 2
#define	GPIO_IOINTSEL3					0xE6053000	// R/W	32	General IO/interrupt switching register 3
#define	GPIO_INOUTSEL3					0xE6053004	// R/W	32	General input/output switching register 3
#define	GPIO_OUTDT3						0xE6053008	// R/W	32	General output register 3
#define	GPIO_INDT3						0xE605300C	// R	32	General input register 3
#define	GPIO_INTDT3						0xE6053010	// R	32	Interrupt display register 3
#define	GPIO_INTCLR3					0xE6053014	// R/W	32	Interrupt clear register 3
#define	GPIO_INTMSK3					0xE6053018	// R/W	32	Interrupt mask register 3
#define	GPIO_MSKCLR3					0xE605301C	// R/W	32	Interrupt mask clear register 3
#define	GPIO_POSNEG3					0xE6053020	// R/W	32	Positive/negative logic select register 3
#define	GPIO_EDGLEVEL3					0xE6053024	// R/W	32	Edge/level select register 3
#define	GPIO_FILONOFF3					0xE6053028	// R/W	32	Chattering prevention on/off register 3
#define	GPIO_INTMSKS3					0xE6053038	// R/W	32	Interrupt sub mask register 3
#define	GPIO_MSKCLRS3					0xE605303C	// R/W	32	Interrupt sub mask clear register 3
#define	GPIO_OUTDTSEL3					0xE6053040	// R/W	32	Output data select register 3
#define	GPIO_OUTDTH3					0xE6053044	// R/W	32	Output data high register 3
#define	GPIO_OUTDTL3					0xE6053048	// R/W	32	Output data low register 3
#define	GPIO_BOTHEDGE3					0xE605304C	// R/W	32	One edge/both edge select register 3
#define	GPIO_IOINTSEL4					0xE6054000	// R/W	32	General IO/interrupt switching register 4
#define	GPIO_INOUTSEL4					0xE6054004	// R/W	32	General input/output switching register 4
#define	GPIO_OUTDT4						0xE6054008	// R/W	32	General output register 4
#define	GPIO_INDT4						0xE605400C	// R	32	General input register 4
#define	GPIO_INTDT4						0xE6054010	// R	32	Interrupt display register 4
#define	GPIO_INTCLR4					0xE6054014	// R/W	32	Interrupt clear register 4
#define	GPIO_INTMSK4					0xE6054018	// R/W	32	Interrupt mask register 4
#define	GPIO_MSKCLR4					0xE605401C	// R/W	32	Interrupt mask clear register 4
#define	GPIO_POSNEG4					0xE6054020	// R/W	32	Positive/negative logic select register 4
#define	GPIO_EDGLEVEL4					0xE6054024	// R/W	32	Edge/level select register 4
#define	GPIO_FILONOFF4					0xE6054028	// R/W	32	Chattering prevention on/off register 4
#define	GPIO_INTMSKS4					0xE6054038	// R/W	32	Interrupt sub mask register 4
#define	GPIO_MSKCLRS4					0xE605403C	// R/W	32	Interrupt sub mask clear register 4
#define	GPIO_OUTDTSEL4					0xE6054040	// R/W	32	Output data select register 4
#define	GPIO_OUTDTH4					0xE6054044	// R/W	32	Output data high register 4
#define	GPIO_OUTDTL4					0xE6054048	// R/W	32	Output data low register 4
#define	GPIO_BOTHEDGE4					0xE605404C	// R/W	32	One edge/both edge select register 4
#define	GPIO_IOINTSEL5					0xE6055000	// R/W	32	General IO/interrupt switching register 5
#define	GPIO_INOUTSEL5					0xE6055004	// R/W	32	General input/output switching register 5
#define	GPIO_OUTDT5						0xE6055008	// R/W	32	General output register 5
#define	GPIO_INDT5						0xE605500C	// R	32	General input register 5
#define	GPIO_INTDT5						0xE6055010	// R	32	Interrupt display register 5
#define	GPIO_INTCLR5					0xE6055014	// R/W	32	Interrupt clear register 5
#define	GPIO_INTMSK5					0xE6055018	// R/W	32	Interrupt mask register 5
#define	GPIO_MSKCLR5					0xE605501C	// R/W	32	Interrupt mask clear register 5
#define	GPIO_POSNEG5					0xE6055020	// R/W	32	Positive/negative logic select register 5
#define	GPIO_EDGLEVEL5					0xE6055024	// R/W	32	Edge/level select register 5
#define	GPIO_FILONOFF5					0xE6055028	// R/W	32	Chattering prevention on/off register 5
#define	GPIO_INTMSKS5					0xE6055038	// R/W	32	Interrupt sub mask register 5
#define	GPIO_MSKCLRS5					0xE605503C	// R/W	32	Interrupt sub mask clear register 5
#define	GPIO_OUTDTSEL5					0xE6055040	// R/W	32	Output data select register 5
#define	GPIO_OUTDTH5					0xE6055044	// R/W	32	Output data high register 5
#define	GPIO_OUTDTL5					0xE6055048	// R/W	32	Output data low register 5
#define	GPIO_BOTHEDGE5					0xE605504C	// R/W	32	One edge/both edge select register 5
#define	GPIO_IOINTSEL6					0xE6055400	// R/W	32	General IO/interrupt switching register 6
#define	GPIO_INOUTSEL6					0xE6055404	// R/W	32	General input/output switching register 6
#define	GPIO_OUTDT6						0xE6055408	// R/W	32	General output register 6
#define	GPIO_INDT6						0xE605540C	// R	32	General input register 6
#define	GPIO_INTDT6						0xE6055410	// R	32	Interrupt display register 6
#define	GPIO_INTCLR6					0xE6055414	// R/W	32	Interrupt clear register 6
#define	GPIO_INTMSK6					0xE6055418	// R/W	32	Interrupt mask register 6
#define	GPIO_MSKCLR6					0xE605541C	// R/W	32	Interrupt mask clear register 6
#define	GPIO_POSNEG6					0xE6055420	// R/W	32	Positive/negative logic select register 6
#define	GPIO_EDGLEVEL6					0xE6055424	// R/W	32	Edge/level select register 6
#define	GPIO_FILONOFF6					0xE6055428	// R/W	32	Chattering prevention on/off register 6
#define	GPIO_INTMSKS6					0xE6055438	// R/W	32	Interrupt sub mask register 6
#define	GPIO_MSKCLRS6					0xE605543C	// R/W	32	Interrupt sub mask clear register 6
#define	GPIO_OUTDTSEL6					0xE6055440	// R/W	32	Output data select register 6
#define	GPIO_OUTDTH6					0xE6055444	// R/W	32	Output data high register 6
#define	GPIO_OUTDTL6					0xE6055448	// R/W	32	Output data low register 6
#define	GPIO_BOTHEDGE6					0xE605544C	// R/W	32	One edge/both edge select register 6
#define	GPIO_IOINTSEL7					0xE6055800	// R/W	32	General IO/interrupt switching register 7
#define	GPIO_INOUTSEL7					0xE6055804	// R/W	32	General input/output switching register 7
#define	GPIO_OUTDT7						0xE6055808	// R/W	32	General output register 7
#define	GPIO_INDT7						0xE605580C	// R	32	General input register 7
#define	GPIO_INTDT7						0xE6055810	// R	32	Interrupt display register 7
#define	GPIO_INTCLR7					0xE6055814	// R/W	32	Interrupt clear register 7
#define	GPIO_INTMSK7					0xE6055818	// R/W	32	Interrupt mask register 7
#define	GPIO_MSKCLR7					0xE605581C	// R/W	32	Interrupt mask clear register 7
#define	GPIO_POSNEG7					0xE6055820	// R/W	32	Positive/negative logic select register 7
#define	GPIO_EDGLEVEL7					0xE6055824	// R/W	32	Edge/level select register 7
#define	GPIO_FILONOFF7					0xE6055828	// R/W	32	Chattering prevention on/off register 7
#define	GPIO_INTMSKS7					0xE6055838	// R/W	32	Interrupt sub mask register 7
#define	GPIO_MSKCLRS7					0xE605583C	// R/W	32	Interrupt sub mask clear register 7
#define	GPIO_OUTDTSEL7					0xE6055840	// R/W	32	Output data select register 7
#define	GPIO_OUTDTH7					0xE6055844	// R/W	32	Output data high register 7
#define	GPIO_OUTDTL7					0xE6055848	// R/W	32	Output data low register 7
#define	GPIO_BOTHEDGE7					0xE605584C	// R/W	32	One edge/both edge select register 7


//LBSC.h
#define	LBSC_CS0CTRL					0xEE220200	// R/W	32	Area 0 control register
#define	LBSC_CS1CTRL					0xEE220204	// R/W	32	Area 1 control register
#define	LBSC_CSWCR0						0xEE220230	// R/W	32	Area 0 RD/WE pulse control register
#define	LBSC_CSWCR1						0xEE220234	// R/W	32	Area 1 RD/WE pulse control register
#define	LBSC_CSPWCR0					0xEE220280	// R/W	32	Area 0 external wait control register
#define	LBSC_CSPWCR1					0xEE220284	// R/W	32	Area 1 external wait control register
#define	LBSC_EXWTSYNC					0xEE2202A0	// R/W	32	External wait input control register
#define	LBSC_CS0BSTCTL					0xEE2202B0	// R/W	32	Area 0 burst control register
#define	LBSC_CS0BTPH					0xEE2202B4	// R/W	32	Area 0 burst pitch set register
#define	LBSC_CS1GDST					0xEE2202C0	// R/W	32	Area 1 guard setting register
#define	LBSC_BCINTSR					0xEE220330	// R	32	BSC interrupt source status register
#define	LBSC_BCINTCR					0xEE220334	// -/WC1	32	BSC interrupt source clear register
#define	LBSC_BCINTMR					0xEE220338	// R/W	32	BSC interrupt enable register
#define	LBSC_EXWTSTS					0xEE220344	// R	32	External wait status register
#define	LBSC_EXBCT						0xEE2203C0	// R/W	32	EX-BUS wait timeout detection base counter register
#define	LBSC_EXTCT						0xEE2203C4	// R/W	32	EX-BUS wait timeout detection counter register
#define	LBSC_EXTSR						0xEE220010	// R/WC1	32	EX-BUS wait timeout detection access source indication register
#define	LBSC_EXTADR						0xEE220014	// R/W	32	EX-BUS wait timeout detection address indication register


//MSTPRST
#define	CPG_MSTPSR0						0xE6150030	// R	32	Module stop status register 0
#define	CPG_MSTPSR1						0xE6150038	// R	32	Module stop status register 1
#define	CPG_MSTPSR2						0xE6150040	// R	32	Module stop status register 2
#define	CPG_MSTPSR3						0xE6150048	// R	32	Module stop status register 3
#define	CPG_MSTPSR4						0xE615004C	// R	32	Module stop status register 4
#define	CPG_MSTPSR5						0xE615003C	// R	32	Module stop status register 5
#define	CPG_MSTPSR6						0xE61501C0	// R	32	Module stop status register 6
#define	CPG_MSTPSR7						0xE61501C4	// R	32	Module stop status register 7
#define	CPG_MSTPSR8						0xE61509A0	// R	32	Module stop status register 8
#define	CPG_MSTPSR9						0xE61509A4	// R	32	Module stop status register 9
#define	CPG_MSTPSR10					0xE61509A8	// R	32	Module stop status register 10
#define	CPG_MSTPSR11					0xE61509AC	// R	32	Module stop status register 11
#define	CPG_RMSTPCR0					0xE6150110	// R/W	32	Realtime module stop control register 0
#define	CPG_RMSTPCR1					0xE6150114	// R/W	32	Realtime module stop control register 1
#define	CPG_RMSTPCR2					0xE6150118	// R/W	32	Realtime module stop control register 2
#define	CPG_RMSTPCR3					0xE615011C	// R/W	32	Realtime module stop control register 3
#define	CPG_RMSTPCR4					0xE6150120	// R/W	32	Realtime module stop control register 4
#define	CPG_RMSTPCR5					0xE6150124	// R/W	32	Realtime module stop control register 5
#define	CPG_RMSTPCR6					0xE6150128	// R/W	32	Realtime module stop control register 6
#define	CPG_RMSTPCR7					0xE615012C	// R/W	32	Realtime module stop control register 7
#define	CPG_RMSTPCR8					0xE6150980	// R/W	32	Realtime module stop control register 8
#define	CPG_RMSTPCR9					0xE6150984	// R/W	32	Realtime module stop control register 9
#define	CPG_RMSTPCR10					0xE6150988	// R/W	32	Realtime module stop control register 10
#define	CPG_RMSTPCR11					0xE615098C	// R/W	32	Realtime module stop control register 11
#define	CPG_SMSTPCR0					0xE6150130	// R/W	32	System module stop control register 0
#define	CPG_SMSTPCR1					0xE6150134	// R/W	32	System module stop control register 1
#define	CPG_SMSTPCR2					0xE6150138	// R/W	32	System module stop control register 2
#define	CPG_SMSTPCR3					0xE615013C	// R/W	32	System module stop control register 3
#define	CPG_SMSTPCR4					0xE6150140	// R/W	32	System module stop control register 4
#define	CPG_SMSTPCR5					0xE6150144	// R/W	32	System module stop control register 5
#define	CPG_SMSTPCR6					0xE6150148	// R/W	32	System module stop control register 6
#define	CPG_SMSTPCR7					0xE615014C	// R/W	32	System module stop control register 7
#define	CPG_SMSTPCR8					0xE6150990	// R/W	32	System module stop control register 8
#define	CPG_SMSTPCR9					0xE6150994	// R/W	32	System module stop control register 9
#define	CPG_SMSTPCR10					0xE6150998	// R/W	32	System module stop control register 10
#define	CPG_SMSTPCR11					0xE615099C	// R/W	32	System module stop control register 11
#define	CPG_SRCR0						0xE61500A0	// R/W	32	Software reset register 0
#define	CPG_SRCR1						0xE61500A8	// R/W	32	Software reset register 1
#define	CPG_SRCR2						0xE61500B0	// R/W	32	Software reset register 2
#define	CPG_SRCR3						0xE61500B8	// R/W	32	Software reset register 3
#define	CPG_SRCR4						0xE61500BC	// R/W	32	Software reset register 4
#define	CPG_SRCR5						0xE61500C4	// R/W	32	Software reset register 5
#define	CPG_SRCR6						0xE61501C8	// R/W	32	Software reset register 6
#define	CPG_SRCR7						0xE61501CC	// R/W	32	Software reset register 7
#define	CPG_SRCR8						0xE6150920	// R/W	32	Software reset register 8
#define	CPG_SRCR9						0xE6150924	// R/W	32	Software reset register 9
#define	CPG_SRCR10						0xE6150928	// R/W	32	Software reset register 10
#define	CPG_SRCR11						0xE615092C	// R/W	32	Software reset register 11
#define	CPG_SRSTCLR0					0xE6150940	// W	32	Software reset clearing register 0
#define	CPG_SRSTCLR1					0xE6150944	// W	32	Software reset clearing register 1
#define	CPG_SRSTCLR2					0xE6150948	// W	32	Software reset clearing register 2
#define	CPG_SRSTCLR3					0xE615094C	// W	32	Software reset clearing register 3
#define	CPG_SRSTCLR4					0xE6150950	// W	32	Software reset clearing register 4
#define	CPG_SRSTCLR5					0xE6150954	// W	32	Software reset clearing register 5
#define	CPG_SRSTCLR6					0xE6150958	// W	32	Software reset clearing register 6
#define	CPG_SRSTCLR7					0xE615095C	// W	32	Software reset clearing register 7
#define	CPG_SRSTCLR8					0xE6150960	// W	32	Software reset clearing register 8
#define	CPG_SRSTCLR9					0xE6150964	// W	32	Software reset clearing register 9
#define	CPG_SRSTCLR10					0xE6150968	// W	32	Software reset clearing register 10
#define	CPG_SRSTCLR11					0xE615096C	// W	32	Software reset clearing register 11
#define	CPG_SAMSTPCR0					0xE6150C20	// R/W	32	Safety Module Stop Control Register 0
#define	CPG_SAMSTPCR1					0xE6150C24	// R/W	32	Safety Module Stop Control Register 1
#define	CPG_SAMSTPCR2					0xE6150C28	// R/W	32	Safety Module Stop Control Register 2
#define	CPG_SAMSTPCR3					0xE6150C2C	// R/W	32	Safety Module Stop Control Register 3
#define	CPG_SAMSTPCR4					0xE6150C30	// R/W	32	Safety Module Stop Control Register 4
#define	CPG_SAMSTPCR5					0xE6150C34	// R/W	32	Safety Module Stop Control Register 5
#define	CPG_SAMSTPCR6					0xE6150C38	// R/W	32	Safety Module Stop Control Register 6
#define	CPG_SAMSTPCR7					0xE6150C3C	// R/W	32	Safety Module Stop Control Register 7
#define	CPG_SAMSTPCR8					0xE6150C40	// R/W	32	Safety Module Stop Control Register 8
#define	CPG_SAMSTPCR9					0xE6150C44	// R/W	32	Safety Module Stop Control Register 9
#define	CPG_SAMSTPCR10					0xE6150C48	// R/W	32	Safety Module Stop Control Register 10
#define	CPG_SAMSTPCR11					0xE6150C4C	// R/W	32	Safety Module Stop Control Register 11
#define	CPG_SASRSTECR0					0xE6150C80	// R/W	32	Safety Software Reset Access Enable Control Register 0
#define	CPG_SASRSTECR1					0xE6150C84	// R/W	32	Safety Software Reset Access Enable Control Register 1
#define	CPG_SASRSTECR2					0xE6150C88	// R/W	32	Safety Software Reset Access Enable Control Register 2
#define	CPG_SASRSTECR3					0xE6150C8C	// R/W	32	Safety Software Reset Access Enable Control Register 3
#define	CPG_SASRSTECR4					0xE6150C90	// R/W	32	Safety Software Reset Access Enable Control Register 4
#define	CPG_SASRSTECR5					0xE6150C94	// R/W	32	Safety Software Reset Access Enable Control Register 5
#define	CPG_SASRSTECR6					0xE6150C98	// R/W	32	Safety Software Reset Access Enable Control Register 6
#define	CPG_SASRSTECR7					0xE6150C9C	// R/W	32	Safety Software Reset Access Enable Control Register 7
#define	CPG_SASRSTECR8					0xE6150CA0	// R/W	32	Safety Software Reset Access Enable Control Register 8
#define	CPG_SASRSTECR9					0xE6150CA4	// R/W	32	Safety Software Reset Access Enable Control Register 9
#define	CPG_SASRSTECR10					0xE6150CA8	// R/W	32	Safety Software Reset Access Enable Control Register 10
#define	CPG_SASRSTECR11					0xE6150CAC	// R/W	32	Safety Software Reset Access Enable Control Register 11
#define	CPG_SAPTCSR						0xE6150C00	// R/W	32	Safety Protect Control/Status Register
#define	CPG_SAERMIDR					0xE6150C04	// R	32	Safety Error Master ID Register
#define	CPG_SAERADR						0xE6150C08	// R	32	Safety Error Address Regsiter



//PFC
#define	PFC_PMMR						0xE6060000	// R/W	32	LSI Multiplexed Pin Setting Mask Register
#define	PFC_GPSR0						0xE6060100	// R/W	32	GPIO/Peripheral Function Select register 0
#define	PFC_GPSR1						0xE6060104	// R/W	32	GPIO/Peripheral Function Select register 1
#define	PFC_GPSR2						0xE6060108	// R/W	32	GPIO/Peripheral_Function Select register 2
#define	PFC_GPSR3						0xE606010C	// R/W	32	GPIO/Peripheral Function Select register 3
#define	PFC_GPSR4						0xE6060110	// R/W	32	GPIO/Peripheral Function Select register 4
#define	PFC_GPSR5						0xE6060114	// R/W	32	GPIO/Peripheral Function Select register 5
#define	PFC_GPSR6						0xE6060118	// R/W	32	GPIO/Peripheral Function Select register 6
#define	PFC_GPSR7						0xE606011C	// R/W	32	GPIO/Peripheral Function Select register 7
#define	PFC_IPSR0						0xE6060200	// R/W	32	Peripheral Function Select register 0
#define	PFC_IPSR1						0xE6060204	// R/W	32	Peripheral Function Select register 1
#define	PFC_IPSR2						0xE6060208	// R/W	32	Peripheral Function Select register 2
#define	PFC_IPSR3						0xE606020C	// R/W	32	Peripheral Function Select register 3
#define	PFC_IPSR4						0xE6060210	// R/W	32	Peripheral Function Select register 4
#define	PFC_IPSR5						0xE6060214	// R/W	32	Peripheral Function Select register 5
#define	PFC_IPSR6						0xE6060218	// R/W	32	Peripheral Function Select register 6
#define	PFC_IPSR7						0xE606021C	// R/W	32	Peripheral Function Select register 7
#define	PFC_IPSR8						0xE6060220	// R/W	32	Peripheral Function Select register 8
#define	PFC_IPSR9						0xE6060224	// R/W	32	Peripheral Function Select register 9
#define	PFC_IPSR10						0xE6060228	// R/W	32	Peripheral Function Select register 10
#define	PFC_IPSR11						0xE606022C	// R/W	32	Peripheral Function Select register 11
#define	PFC_IPSR12						0xE6060230	// R/W	32	Peripheral Function Select register 12
#define	PFC_IPSR13						0xE6060234	// R/W	32	Peripheral Function Select register 13
#define	PFC_IPSR14						0xE6060238	// R/W	32	Peripheral Function Select register 14
#define	PFC_IPSR15						0xE606023C	// R/W	32	Peripheral Function Select register 15
#define	PFC_IPSR16						0xE6060240	// R/W	32	Peripheral Function Select register 16
#define	PFC_IPSR17						0xE6060244	// R/W	32	Peripheral Function Select register 17
#define	PFC_IPSR18						0xE6060248	// R/W	32	Peripheral Function Select register 18
#define	PFC_DRVCTRL0					0xE6060300	// R/W	32	DRV control register0
#define	PFC_DRVCTRL1					0xE6060304	// R/W	32	DRV control register1
#define	PFC_DRVCTRL2					0xE6060308	// R/W	32	DRV control register2
#define	PFC_DRVCTRL3					0xE606030C	// R/W	32	DRV control register3
#define	PFC_DRVCTRL4					0xE6060310	// R/W	32	DRV control register4
#define	PFC_DRVCTRL5					0xE6060314	// R/W	32	DRV control register5
#define	PFC_DRVCTRL6					0xE6060318	// R/W	32	DRV control register6
#define	PFC_DRVCTRL7					0xE606031C	// R/W	32	DRV control register7
#define	PFC_DRVCTRL8					0xE6060320	// R/W	32	DRV control register8
#define	PFC_DRVCTRL9					0xE6060324	// R/W	32	DRV control register9
#define	PFC_DRVCTRL10					0xE6060328	// R/W	32	DRV control register10
#define	PFC_DRVCTRL11					0xE606032C	// R/W	32	DRV control register11
#define	PFC_DRVCTRL12					0xE6060330	// R/W	32	DRV control register12
#define	PFC_DRVCTRL13					0xE6060334	// R/W	32	DRV control register13
#define	PFC_DRVCTRL14					0xE6060338	// R/W	32	DRV control register14
#define	PFC_DRVCTRL15					0xE606033C	// R/W	32	DRV control register15
#define	PFC_DRVCTRL16					0xE6060340	// R/W	32	DRV control register16
#define	PFC_DRVCTRL17					0xE6060344	// R/W	32	DRV control register17
#define	PFC_DRVCTRL18					0xE6060348	// R/W	32	DRV control register18
#define	PFC_DRVCTRL19					0xE606034C	// R/W	32	DRV control register19
#define	PFC_DRVCTRL20					0xE6060350	// R/W	32	DRV control register20
#define	PFC_DRVCTRL21					0xE6060354	// R/W	32	DRV control register21
#define	PFC_DRVCTRL22					0xE6060358	// R/W	32	DRV control register22
#define	PFC_DRVCTRL23					0xE606035C	// R/W	32	DRV control register23
#define	PFC_DRVCTRL24					0xE6060360	// R/W	32	DRV control register24
#define	PFC_POCCTRL0					0xE6060380	// R/W	32	POC control register0
#define	PFC_TDSELCTRL0					0xE60603C0	// R/W	32	TDSEL control register0
#define	PFC_IOCTRL						0xE60603E0	// R/W	32	IO cell control for IICDVFS
#define	PFC_FUSEMON						0xE60603E4	// R	32	Fuse Monitor register0
#define	PFC_PUEN0						0xE6060400	// R/W	32	LSI pin pull-enable register 0
#define	PFC_PUEN1						0xE6060404	// R/W	32	LSI pin pull-enable register 1
#define	PFC_PUEN2						0xE6060408	// R/W	32	LSI pin pull-enable register 2
#define	PFC_PUEN3						0xE606040C	// R/W	32	LSI pin pull-enable register 3
#define	PFC_PUEN4						0xE6060410	// R/W	32	LSI pin pull-enable register 4
#define	PFC_PUEN5						0xE6060414	// R/W	32	LSI pin pull-enable register 5
#define	PFC_PUEN6						0xE6060418	// R/W	32	LSI pin pull-enable register 6
#define	PFC_PUD0						0xE6060440	// R/W	32	LSI pin pull-up/down control register 0
#define	PFC_PUD1						0xE6060444	// R/W	32	LSI pin pull-up/down control register 1
#define	PFC_PUD2						0xE6060448	// R/W	32	LSI pin pull-up/down control register 2
#define	PFC_PUD3						0xE606044C	// R/W	32	LSI pin pull-up/down control register 3
#define	PFC_PUD4						0xE6060450	// R/W	32	LSI pin pull-up/down control register 4
#define	PFC_PUD5						0xE6060454	// R/W	32	LSI pin pull-up/down control register 5
#define	PFC_PUD6						0xE6060458	// R/W	32	LSI pin pull-up/down control register 6
#define	PFC_MOD_SEL0					0xE6060500	// R/W	32	Module select register 0
#define	PFC_MOD_SEL1					0xE6060504	// R/W	32	Module select register 1
#define	PFC_MOD_SEL2					0xE6060508	// R/W	32	Module select register 2

//V3M
#define	PFC_IOCTRL30					0xE6060380	// R/W	32	MPOC control register 0
#define	PFC_IOCTRL31					0xE6060384	// R/W	32	MPOC control register 0
#define	PFC_IOCTRL32					0xE6060388	// R/W	32	MPOC control register 0
#define	PFC_IOCTRL40					0xE60603C0	// R/W	32	MPOC control register 0


//RST
#define	RST_MODEMR						0xE6160060	// R	32	Mode Monitor Register
#define	RST_CA57RESCNT					0xE6160040	// R/W	32	CA57 Reset Control Register
#define	RST_CA53RESCNT					0xE6160044	// R/W	32	CA53 Reset Control Register
#define	RST_WDTRSTCR					0xE6160054	// R/W	32	Watchdog Timer Reset Control Register
#define	RST_RSTOUTCR					0xE6160058	// R/W	32	PRESETOUT# Control Register
#define	RST_SBAR						0xE6160010	// R/W	32	SYS Boot Address Register
#define	RST_SBAR2						0xE6160014	// R/W	32	SYS Boot Address Register2
#define	RST_CA53BAR						0xE6160030	// R/W	32	CA53 Boot Address Register
#define	RST_CA53BAR2					0xE6160034	// R/W	32	CA53 Boot Address Register2
#define	RST_CA57BAR						0xE6160020	// R/W	32	CA57 Boot Address Register
#define	RST_CA57BAR2					0xE6160024	// R/W	32	CA57 Boot Address Register2
#define	RST_CR7BAR						0xE6160070	// R/W	32	CR7 Boot Address Register
#define	RST_CR7BAR2						0xE6160074	// R/W	32	CR7 Boot Address Register2
#define	RST_CA57CPU0BARH				0xE61600C0	// R/W	32	CA57 CPU0 Boot Address Register for 64-bit mode H
#define	RST_CA57CPU0BARL				0xE61600C4	// R/W	32	CA57 CPU0 Boot Address Register for 64-bit mode L
#define	RST_CA57CPU1BARH				0xE61600D0	// R/W	32	CA57 CPU1 Boot Address Register for 64-bit mode H
#define	RST_CA57CPU1BARL				0xE61600D4	// R/W	32	CA57 CPU1 Boot Address Register for 64-bit mode L
#define	RST_CA57CPU2BARH				0xE61600E0	// R/W	32	CA57 CPU2 Boot Address Register for 64-bit mode H
#define	RST_CA57CPU2BARL				0xE61600E4	// R/W	32	CA57 CPU2 Boot Address Register for 64-bit mode L
#define	RST_CA57CPU3BARH				0xE61600F0	// R/W	32	CA57 CPU3 Boot Address Register for 64-bit mode H
#define	RST_CA57CPU3BARL				0xE61600F4	// R/W	32	CA57 CPU3 Boot Address Register for 64-bit mode L
#define	RST_CA53CPU0BARH				0xE6160080	// R/W	32	CA53 CPU0 Boot Address Register for 64-bit mode H
#define	RST_CA53CPU0BARL				0xE6160084	// R/W	32	CA53 CPU0 Boot Address Register for 64-bit mode L
#define	RST_CA53CPU1BARH				0xE6160090	// R/W	32	CA53 CPU1 Boot Address Register for 64-bit mode H
#define	RST_CA53CPU1BARL				0xE6160094	// R/W	32	CA53 CPU1 Boot Address Register for 64-bit mode L
#define	RST_CA53CPU2BARH				0xE61600A0	// R/W	32	CA53 CPU2 Boot Address Register for 64-bit mode H
#define	RST_CA53CPU2BARL				0xE61600A4	// R/W	32	CA53 CPU2 Boot Address Register for 64-bit mode L
#define	RST_CA53CPU3BARH				0xE61600B0	// R/W	32	CA53 CPU3 Boot Address Register for 64-bit mode H
#define	RST_CA53CPU3BARL				0xE61600B4	// R/W	32	CA53 CPU3 Boot Address Register for 64-bit mode L
#define	RST_APBSFTYCHKR					0xE616005C	// R/W	32	APB bus Safety Check Register
#define	RST_STBCHR0						0xE6160100	// R/W	32	Standby Flag Register 0
#define	RST_STBCHR1						0xE6160104	// R/W	32	Standby Flag Register 1
#define	RST_STBCHR2						0xE6160108	// R/W	32	Standby Flag Register 2
#define	RST_STBCHR3						0xE616010C	// R/W	32	Standby Flag Register 3
#define	RST_STBCHR4						0xE6160120	// R/W	32	Standby Flag Register 4
#define	RST_STBCHR5						0xE6160124	// R/W	32	Standby Flag Register 5
#define	RST_STBCHR6						0xE6160128	// R/W	32	Standby Flag Register 6
#define	RST_STBCHR7						0xE616012C	// R/W	32	Standby Flag Register 7
#define	RST_SRESCR						0xE6160110	// R/W	32	Soft Power On Reset Control Register
#define	RST_RRSTFR						0xE6160114	// R/W	32	RT Reset Flag Register
#define	RST_SRSTFR						0xE6160118	// R/W	32	SYS Reset Flag Register
#define	RST_SCPTCSR						0xE6160180	// R/W	32	Secure Protect Control/Status Register
#define	RST_SCERMIDR					0xE6160184	// R	32	Secure Error Master ID Register
#define	RST_SCERADR						0xE6160188	// R	32	Secure Error Address Register
#define	RST_SAPTCSR						0xE6160190	// R/W	32	Safety Protect Control/Status Register
#define	RST_SAERMIDR					0xE6160194	// R	32	Safety Error Master ID Register
#define	RST_SAERADR						0xE6160198	// R	32	Safety Error Address Register

#define MODEMR_BOOT_CPU_MASK		(0x000000C0U)
#define MODEMR_BOOT_CPU_CR7		(0x000000C0U)
#define MODEMR_BOOT_CPU_CA57		(0x00000000U)
#define MODEMR_BOOT_CPU_CA53		(0x00000040U)
#define MODEMR_BOOT_DEV_MASK		(0x0000001EU)
#define MODEMR_BOOT_DEV_HYPERFLASH160	(0x00000004U)
#define MODEMR_BOOT_DEV_HYPERFLASH80	(0x00000006U)
#define MODEMR_BOOT_DEV_QSPI_FLASH40	(0x00000008U)
#define MODEMR_BOOT_DEV_QSPI_FLASH80	(0x0000000CU)
#define MODEMR_BOOT_DEV_OCTAL_FLASH	(0x0000000EU)
#define MODEMR_BOOT_DEV_EMMC_25X1	(0x0000000AU)
#define MODEMR_BOOT_DEV_EMMC_50X8	(0x0000001AU)
#define MODEMR_BOOT_DEV_SCIF_DOWNLOAD	(0x0000001EU)
#define MODEMR_BOOT_DEV_USB_DOWNLOAD	(0x0000001CU)
#define MODEMR_BOOT_PLL_MASK		(0x00006000U)
#define MODEMR_BOOT_PLL_SHIFT		(13U)


//
#define MFIS_SOFTMDR			(0xE6260600U)


//SCIF0
#define	SCIF0_SCSMR						0xE6E60000	// R/W	16	Serial mode register
#define	SCIF0_SCBRR						0xE6E60004	// R/W	8	Bit rate register
#define	SCIF0_SCSCR						0xE6E60008	// R/W	16	Serial control register
#define	SCIF0_SCFTDR					0xE6E6000C	// W	8	Transmit FIFO data register
#define	SCIF0_SCFSR						0xE6E60010	// R/W	16	Serial status register
#define	SCIF0_SCFRDR					0xE6E60014	// R	8	Receive FIFO data register
#define	SCIF0_SCFCR						0xE6E60018	// R/W	16	FIFO control register
#define	SCIF0_SCFDR						0xE6E6001C	// R	16	FIFO data count register
#define	SCIF0_SCSPTR					0xE6E60020	// R/W	16	Serial port register
#define	SCIF0_SCLSR						0xE6E60024	// R/W	16	Line status register
#define	SCIF0_DL						0xE6E60030	// R/W	16	Frequency division register
#define	SCIF0_CKS						0xE6E60034	// R/W	16	Clock Select register


//SCIF2
#define	SCIF2_SCSMR						0xE6E88000	// R/W	16	Serial mode register
#define	SCIF2_SCBRR						0xE6E88004	// R/W	8	Bit rate register
#define	SCIF2_SCSCR						0xE6E88008	// R/W	16	Serial control register
#define	SCIF2_SCFTDR					0xE6E8800C	// W	8	Transmit FIFO data register
#define	SCIF2_SCFSR						0xE6E88010	// R/W	16	Serial status register
#define	SCIF2_SCFRDR					0xE6E88014	// R	8	Receive FIFO data register
#define	SCIF2_SCFCR						0xE6E88018	// R/W	16	FIFO control register
#define	SCIF2_SCFDR						0xE6E8801C	// R	16	FIFO data count register
#define	SCIF2_SCSPTR					0xE6E88020	// R/W	16	Serial port register
#define	SCIF2_SCLSR						0xE6E88024	// R/W	16	Line status register
#define	SCIF2_DL						0xE6E88030	// R/W	16	Frequency division register
#define	SCIF2_CKS						0xE6E88034	// R/W	16	Clock Select register


/* Appendix A.	*/
#define	PRR			(0xFFF00044)	/* Product Register */
#define PRR_PRODUCT_MASK	(0x00007F00U)
#define PRR_CUT_MASK		(0x000000FFU)
#define PRR_PRODUCT_H3		(0x00004F00U)	/* R-Car H3  */
#define PRR_PRODUCT_M3		(0x00005200U)	/* R-Car M3  */
#define PRR_PRODUCT_M3N		(0x00005500U)	/* R-Car M3N */
#define PRR_PRODUCT_E3		(0x00005700U)	/* R-Car E3  */
#define PRR_PRODUCT_D3		(0x00005800U)	/* R-Car D3  */
#define PRR_PRODUCT_V3M		(0x00005400U)	/* R-Car V3M */
#define PRR_PRODUCT_V3H	(0x00005600U)
#define PRR_CUT_10		(0x00U)
#define PRR_CUT_11		(0x01U)
#define PRR_CUT_20		(0x10U)
#define PRR_CUT_30		(0x20U)
#define PRR_CUT_MAJOR_MASK	(0x000000F0U)
#define PRR_CUT_MINOR_MASK	(0x0000000FU)
#define PRR_PRODUCT_SHIFT	(8U)
#define PRR_MAJOR_SHIFT		(4U)
#define PRR_MINOR_SHIFT		(0U)
#define PRR_MAJOR_OFFSET	(1U)

#endif /* REG_RCARGEN3_H */
