/*******************************************************************************
 * Copyright (c) 2018 Renesas Electronics Corporation. All rights reserved.
 *
 * DESCRIPTION   : remap register header
 ******************************************************************************/

#ifndef REMAP_REGISTER_H_
#define REMAP_REGISTER_H_


#define	REMAP_BASE	(0xFF1FC400U)

#define REMAP_2M_BITS	(21U)
#define REMAP_2M_MASK	((1 << REMAP_2M_BITS) - 1U)

#define REMAP_REG_MAX	(16U)
#define SICREMAP2M(a)	(REMAP_BASE + ((a) * (0x4U)))

#define	ICUMX_PROT0PCMD		(0xFFFEE090U)
#define	ICUMX_PROT0PS		(0xFFFEE094U)
#define	PROTCMD_START		(0x000000A5U)
#define	PROTS0ERR		(0x00000001U)

/* REMAP setting */
/* Remap ID(0 -- 15) */
#define	ICU_REMAP_NUM_RTRAM	(15U)	/* RTRAM */
#define	ICU_REMAP_NUM_CC	(14U)	/* CC63S */
#define	ICU_REMAP_NUM_PFC	(13U)	/* PFC,GPIO,LIFC,CPGA,RESET,SYSC */
#define	ICU_REMAP_NUM_MFIS	(12U)	/* MFIS */
#define	ICU_REMAP_NUM_RPC	(11U)	/* RPC */
#define	ICU_REMAP_NUM_RTDMAC	(10U)	/* RT-DMAC0 */
#define	ICU_REMAP_NUM_SCIF	(9U)	/* SCIF */
#define	ICU_REMAP_NUM_MMC	(8U)	/* MMC */
#define	ICU_REMAP_NUM_HSCIF	(7U)	/* HSCIF */
#define	ICU_REMAP_NUM_DMAC	(6U)	/* SYS-DMAC0 */
#define ICU_REMAP_NUM_PRR	(5U)	/* PRR */
#define ICU_REMAP_NUM_RTACT	(4U)	/* RT-ACT */

/* SICREMAP2M15 */
#define	ICU_REMAP_RTRAM		(0xEB200000U)	/* RTRAM */
/* SICREMAP2M14 */
#define	ICU_REMAP_CC		(0xE6600000U)	/* CC63S,System DMA */
/* SICREMAP2M13 */
#define	ICU_REMAP_PFC		(0xE6000000U)	/* PFC,GPIO,LIFC,CPGA,RESET,SYSC */
/* SICREMAP2M12 */
#define	ICU_REMAP_MFIS		(0xE6200000U)	/* MFIS */
/* SICREMAP2M11 */
#define	ICU_REMAP_RPC		(0xEE200000U)	/* RPC */
/* SICREMAP2M10 */
#define	ICU_REMAP_SCIF		(0xE6E00000U)	/* SCIF */
/* SICREMAP2M9 */
#define	ICU_REMAP_MMC		(0xEE000000U)	/* MMC */
/* SICREMAP2M8 */
#define	ICU_REMAP_RTDMAC	(0xFFC00000U)	/* RT-DMAC0 */
/* SICREMAP2M7 */
#define	ICU_REMAP_HSCIF		(0xE6400000U)	/* HSCIF */
/* SICREMAP2M6 */
#define	ICU_REMAP_DMAC		(0xE7200000U)	/* SYS-DMAC0 */
/* SICREMAP2M5 */
#define	ICU_REMAP_PRR		(0xFFE00000U)	/* PRR */
/* SICREMAP2M4 */
#define	ICU_REMAP_RTACT		(0xFFC00000U)	/* RT-ACT */

#define	ICU_REMAP15_BASE	(ICU_REMAP_RTRAM)	/* RTRAM */
#define	ICU_REMAP14_BASE	(ICU_REMAP_CC)		/* CC63S */
#define	ICU_REMAP13_BASE	(ICU_REMAP_PFC)		/* PFC,GPIO,LIFC,CPGA,RESET,SYSC */
#define	ICU_REMAP12_BASE	(ICU_REMAP_MFIS)	/* MFIS */
#define	ICU_REMAP11_BASE	(ICU_REMAP_RPC)		/* RPC */
#define	ICU_REMAP10_BASE	(ICU_REMAP_RTDMAC)	/* RT-DMAC0 */
#define	ICU_REMAP9_BASE		(ICU_REMAP_SCIF)	/* SCIF */
#define	ICU_REMAP8_BASE		(ICU_REMAP_MMC)		/* MMC */
#define	ICU_REMAP7_BASE		(ICU_REMAP_HSCIF)	/* HSCIF */
#define	ICU_REMAP6_BASE		(ICU_REMAP_DMAC)	/* SYS-DMAC0 */
#define	ICU_REMAP5_BASE		(ICU_REMAP_PRR)		/* PRR,INTC,RT-SRAM protection*/
#define	ICU_REMAP4_BASE		(0x00000000U)		/* Reserved */
#define	ICU_REMAP3_BASE		(0x00000000U)		/* Reserved */
#define	ICU_REMAP2_BASE		(0x00000000U)		/* Reserved */
#define	ICU_REMAP1_BASE		(0x00000000U)		/* Reserved */
#define	ICU_REMAP0_BASE		(0x00000000U)		/* Reserved */

/* Base address offset of each register after remap */
/* REMAP15(0xEB200000U) */
/* RT-SRAM */
#define	ICU_REMAP_OFFSET_RTRAM	(0x000000U)

/* REMAP14(0xE6600000U) */
#define	ICU_REMAP_OFFSET_CC63S	(0x000000U)
#define ICU_REMAP_OFFSET_AXI	(0x184000U)	/* (0xE6784000U) */
#define	ICU_REMAP_OFFSET_DBSC	(0x190000U)	/* (0xE6790000U) */
#define	ICU_REMAP_OFFSET_MSTAT	(0x1e0000U)	/* (0xE67e0000U) */
#define	ICU_REMAP_OFFSET_QOS	(0x1F0000U)	/* (0xE67F0000U) */

/* REMAP13(0xE6000000U) */
/* GPIO */
#define	ICU_REMAP_OFFSET_GPIO0	(0x050000U)
#define	ICU_REMAP_OFFSET_GPIO1	(0x051000U)
#define	ICU_REMAP_OFFSET_GPIO2	(0x052000U)
#define	ICU_REMAP_OFFSET_GPIO3	(0x053000U)
#define	ICU_REMAP_OFFSET_GPIO4	(0x054000U)
#define	ICU_REMAP_OFFSET_GPIO5	(0x055000U)
/* PFC */
#define	ICU_REMAP_OFFSET_PFC	(0x060000U)
/* LIFEC */
#define	ICU_REMAP_OFFSET_LIFEC	(0x110000U)
/* CPGA */
#define	ICU_REMAP_OFFSET_CPGA	(0x150000U)
/* RESET */
#define	ICU_REMAP_OFFSET_RESET	(0x160000U)
/* SYSC */ 
#define	ICU_REMAP_OFFSET_SYSC	(0x180000U)
/* THS1 */
#define	ICU_REMAP_OFFSET_THS1	(0x198000U)	/* (0xE6198000U) */

/* REMAP12(0xE6200000U) */
/* MFIS */
#define	ICU_REMAP_OFFSET_MFIS	(0x060000U)

/* REMAP11(0xEE200000U) */
/*RPC*/
#define	ICU_REMAP_OFFSET_RPC	(0x000000U)

/* REMAP10(0xFFC00000U) */
/* RT-DMA */
#define	ICU_REMAP_OFFSET_RTDMA	(0x010000U)

/* REMAP9(0xE6E00000U) */
/*SCIF*/
#define	ICU_REMAP_OFFSET_SCIF0	(0x060000U)

/* REMAP8(0xEE000000U) */
/* SDHI2/MMC0 */
#define	ICU_REMAP_OFFSET_SDHI	(0x140000U)

/* REMAP7(0xE6400000U) */
/* HSCIF */
#define	ICU_REMAP_OFFSET_HSCIF0	(0x140000U)

/* REMAP6(0xE7200000U) */
/* SYS-DMAC */
#define	ICU_REMAP_OFFSET_SYSDMAC	(0x100000U)

/* REMAP5(0xFFE00000U) */
/* PRR */
#define	ICU_REMAP_OFFSET_PRR	(0x100044U)

/* REMAP4(0xFFE00000U) */
/* RT-ACT */
#define	ICU_REMAP_OFFSET_RTACT	(0x050800U)

/* Calculate the base address of each register after remapping */
#define	ICU_REMAP0		(0xFC000000U)
#define	ICU_REMAP_CALC( val )	(ICU_REMAP0 + (val * 0x200000U))

/* REMAP15(0xEB200000U) */
#define	BASE_RTRAM_ADDR	(ICU_REMAP_CALC(ICU_REMAP_NUM_RTRAM) + ICU_REMAP_OFFSET_RTRAM)
/* REMAP14(0xE6600000U) */
#define BASE_AXI_ADDR	(ICU_REMAP_CALC(ICU_REMAP_NUM_CC) + ICU_REMAP_OFFSET_AXI)
#define BASE_DBSC_ADDR	(ICU_REMAP_CALC(ICU_REMAP_NUM_CC) + ICU_REMAP_OFFSET_DBSC)
#define BASE_MSTAT_ADDR	(ICU_REMAP_CALC(ICU_REMAP_NUM_CC) + ICU_REMAP_OFFSET_MSTAT)
#define BASE_QOS_ADDR	(ICU_REMAP_CALC(ICU_REMAP_NUM_CC) + ICU_REMAP_OFFSET_QOS)
/* REMAP13(0xE6000000U) */
#define	BASE_GPIO_ADDR	(ICU_REMAP_CALC(ICU_REMAP_NUM_PFC) + ICU_REMAP_OFFSET_GPIO0)
#define	BASE_PFC_ADDR	(ICU_REMAP_CALC(ICU_REMAP_NUM_PFC) + ICU_REMAP_OFFSET_PFC)
#define BASE_LIFEC_ADDR	(ICU_REMAP_CALC(ICU_REMAP_NUM_PFC) + ICU_REMAP_OFFSET_LIFEC)
#define	BASE_CPG_ADDR	(ICU_REMAP_CALC(ICU_REMAP_NUM_PFC) + ICU_REMAP_OFFSET_CPGA)
#define	BASE_RESET_ADDR	(ICU_REMAP_CALC(ICU_REMAP_NUM_PFC) + ICU_REMAP_OFFSET_RESET)
#define	BASE_SYSC_ADDR	(ICU_REMAP_CALC(ICU_REMAP_NUM_PFC) + ICU_REMAP_OFFSET_SYSC)
#define	BASE_THS1_ADDR	(ICU_REMAP_CALC(ICU_REMAP_NUM_PFC) + ICU_REMAP_OFFSET_THS1)
/* REMAP12(0xE6200000U) */
#define	BASE_MFIS_ADDR	(ICU_REMAP_CALC(ICU_REMAP_NUM_MFIS) + ICU_REMAP_OFFSET_MFIS)
/* REMAP11(0xEE200000U) */
#define	BASE_RPC_ADDR	(ICU_REMAP_CALC(ICU_REMAP_NUM_RPC) + ICU_REMAP_OFFSET_RPC)
/* REMAP10(0xFFC00000U) */
#define	BASE_RTDMA_ADDR	(ICU_REMAP_CALC(ICU_REMAP_NUM_RTDMAC) + ICU_REMAP_OFFSET_RTDMA)
/* REMAP9(0xE6E00000U) */
#define	BASE_SCIF_ADDR	(ICU_REMAP_CALC(ICU_REMAP_NUM_SCIF) + ICU_REMAP_OFFSET_SCIF0)
/* REMAP8(0xEE000000U) */
#define BASE_MMC0_ADDR	(ICU_REMAP_CALC(ICU_REMAP_NUM_MMC) + ICU_REMAP_OFFSET_SDHI)
/* REMAP7(0xE6400000U) */
#define	BASE_HSCIF_ADDR	(ICU_REMAP_CALC(ICU_REMAP_NUM_HSCIF) + ICU_REMAP_OFFSET_HSCIF0)
/* REMAP6(0xE7200000U) */
#define	BASE_DMA_ADDR	(ICU_REMAP_CALC(ICU_REMAP_NUM_DMAC) + ICU_REMAP_OFFSET_SYSDMAC)
/* REMAP5(0xFFE00000U) */
#define	BASE_PRR_ADDR	(ICU_REMAP_CALC(ICU_REMAP_NUM_PRR) + ICU_REMAP_OFFSET_PRR)
/* REMAP4(0xFFE00000U) */
#define	BASE_RTACT_ADDR	(ICU_REMAP_CALC(ICU_REMAP_NUM_RTACT) + ICU_REMAP_OFFSET_RTACT)

/* MFIS */
#define	MFIS_MFISSOFTMDR	(BASE_MFIS_ADDR + 0x0600U)	/* SOFTMD register */
#define	MFIS_MFISBTSTSR		(BASE_MFIS_ADDR + 0x0604U)	/* (0xE6260604U) */
#define	MFIS_MFISWACNTR		(BASE_MFIS_ADDR + 0x0904U)	/* (0xE6260904U) */ /* Write Access Control Register */

#endif /* REMAP_REGISTER_H_ */
