/*******************************************************************************
 * DISCLAIMER
 * This software is supplied by Renesas Electronics Corporation and is only
 * intended for use with Renesas products. No other uses are authorized. This
 * software is owned by Renesas Electronics Corporation and is protected under
 * all applicable laws, including copyright laws.
 * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
 * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
 * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
 * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
 * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
 * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
 * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
 * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
 * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
 * Renesas reserves the right, without notice, to make changes to this software
 * and to discontinue the availability of this software. By using this software,
 * you agree to the additional terms and conditions found by accessing the
 * following link:
 * http://www.renesas.com/disclaimer
 * Copyright 2023-2024 Renesas Electronics Corporation All rights reserved.
 *******************************************************************************/

#include <stdint.h>
#if defined(__RH850G3K__)
#include "mem_io.h"
#include "log.h"
#else
#include "mem_io.h"
#include "log.h"
#endif
#include "ddr_regdef.h"
#include "init_dram_tbl_v4m_lp5.h"
#include "boot_init_dram_regdef.h"
#include "boot_init_dram.h"
#include "dram_sub_func.h"

/*******************************************************************************
 *    load board configuration
 ******************************************************************************/
#include "boot_init_dram_config.h"

#define DDR_BACKUPMODE
#define FATAL_MSG(x) NOTICE(x)

/*******************************************************************************
 *    variables
 ******************************************************************************/
static uint32_t Prr_Product;
static uint32_t Prr_Cut;
static uint32_t BOARDTYPE;
static uint32_t brd_clk;
static uint32_t brd_clkdiv;
static uint32_t brd_clkdiva;
static uint32_t ddr_mbps;
static uint32_t ddr_mbpsdiv;
static uint32_t sscg;
static uint32_t med_freq_en;
static uint32_t bus_clk, bus_clkdiv;
static uint32_t ddr_tccd;
static const st_boardcnf_t *Boardcnf;
static uint32_t ddr_phyvalid;
static uint32_t ddr_density[DRAM_CH_CNT][CS_CNT];
static uint32_t ch_have_this_cs[CS_CNT];
static uint32_t max_density;
static uint32_t ddr_mul;
static uint32_t ddr_medium_div;
static uint32_t ddr_mul_nf;
static uint32_t ddr_mul_low;
static uint32_t ddr_mul_reg;

#define DDR_PHY_REGSET_MAX    140
#define DDR_PI_REGSET_MAX     1301

static uint32_t DDR_PHY_SLICE_REGSET[DDR_PHY_REGSET_MAX];
static uint32_t DDR_PHY_ADR_V_REGSET[DDR_PHY_REGSET_MAX];
static uint32_t DDR_PHY_ADR_G_REGSET[DDR_PHY_REGSET_MAX];
static uint32_t DDR_PI_REGSET[DDR_PI_REGSET_MAX];
#ifdef DDR_BACKUPMODE
static uint32_t ddrBackup;
#endif /* DDR_BACKUPMODE */
#ifndef RCAR_PLL3_FRAC_MODE
#define RCAR_PLL3_FRAC_MODE    (1U)
#endif
#ifndef RCAR_DDRPHY_REGISTER_FAST_LOAD_MODE
#define RCAR_DDRPHY_REGISTER_FAST_LOAD_MODE    (1U)
#endif
#ifndef RCAR_MEDIUM_FREQUENCY_TRAINING_MODE
#define RCAR_MEDIUM_FREQUENCY_TRAINING_MODE    (1U)
#endif
#define PLL3_LOW_FREQUENCY_MODE                   (0U)
#define PLL3_MEDIUM_FREQUENCY_MODE                (1U)
#define PLL3_HIGH_FREQUENCY_MODE                  (2U)
#define PLL3_HIGH_FREQUENCY_MODE_LOAD_REGISTER    (3U)
#define PLL3_MEDIUM_FREQUENCY_THRESHOLD           (1550U)

/*******************************************************************************
 *    Prototypes
 ******************************************************************************/
static uint32_t r_vch_nxt(uint32_t pos);
static void r_cpg_write_32(uint32_t a, uint32_t v);
static void r_pll3_control(uint32_t mode);
static void r_send_dbcmd(uint32_t cmd);
static uint32_t r_reg_ddrphy_read(uint32_t phyno, uint32_t regadd);
static void r_reg_ddrphy_write(uint32_t phyno, uint32_t regadd, uint32_t regdata);
static void r_reg_ddrphy_write_a(uint32_t regadd, uint32_t regdata);
static void r_reg_ddrphy_masked_write(uint32_t phyno, uint32_t regadd, uint32_t regdata, uint32_t msk);
static void r_ddr_setval_s(uint32_t ch, uint32_t slice, uint32_t regdef, uint32_t val);
static uint32_t r_ddr_getval_s(uint32_t ch, uint32_t slice, uint32_t regdef);
static void r_ddr_setval(uint32_t ch, uint32_t regdef, uint32_t val);
static void r_ddr_setval_ach_s(uint32_t slice, uint32_t regdef, uint32_t val);
static void r_ddr_setval_ach(uint32_t regdef, uint32_t val);
static void r_ddr_setval_ach_as(uint32_t regdef, uint32_t val);
static uint32_t r_ddr_getval(uint32_t ch, uint32_t regdef);
static void r_dbsc_write_32(uintptr_t addr, uint32_t data);
static void r_tbl_copy(uint32_t *to, const uint32_t *from, uint32_t size);
static void r_ddrtbl_setval(uint32_t *tbl, uint32_t regdef, uint32_t val);
static void r_ddrtbl_setval_pi(uint32_t *tbl, uint32_t regdef, uint32_t val);
static uint32_t r_ddrtbl_getval(const uint32_t *tbl, uint32_t regdef);
#if ((RCAR_PERIODIC_WRITE_TRAINING != 0U) || (RCAR_PERIODIC_READ_TRAINING != 0U))
static uint32_t r_ddrtbl_getval_pi(const uint32_t *tbl, uint32_t regdef);
#endif /* ((RCAR_PERIODIC_WRITE_TRAINING != 0U) || (RCAR_PERIODIC_READ_TRAINING != 0U)) */
static uint16_t r_f_scale(uint32_t f_ddr_mbps, uint32_t f_ddr_mbpsdiv, uint32_t ps, uint16_t cyc);
static uint32_t r_f_scale_l(uint32_t f_ddr_mbps, uint32_t f_ddr_mbpsdiv, uint32_t ps, uint32_t cyc);
static void r_f_scale_js2(uint32_t f_ddr_mbps, uint32_t f_ddr_mbpsdiv, uint32_t *f_js2);
static void r_ddrtbl_load(void);
static void r_ddr_config(void);
static void r_dbsc_regset_pre(void);
static void r_dbsc_regset(void);
static void r_dbsc_regset_post(void);
static uint32_t r_pi_training(void);
static void r_write_leveling_adjust(void);
static uint32_t r_wl_gt_training(void);
static void r_write_dca(void);
static uint32_t r_dramdca_training(void);
static uint32_t r_write_leveling(void);
static void r_manual_write_dca(void);
static uint32_t r_read_gate_training(void);
static uint32_t r_read_vref_training(void);
static uint32_t r_read_write_training(void);
static uint32_t r_read_training(void);
static void r_ddr_register_set(void);
static void r_ddr_register_read(void);
static uint32_t r_pi_int_ack_0_assert(uint32_t bit);
static void r_wait_dbpdstat1(uint32_t status);
static uint32_t r_wait_freqchgreq(uint32_t req_assert);
static void r_set_freqchgack(uint32_t ack_assert);
static uint32_t r_pll3_freq(void);
static uint32_t r_init_ddr(void);
#if (RCAR_PERIODIC_TRAINING_SEPARATE_MODE != 0U)
void r_set_pi_rdlvl_interval(void);
#endif /* (RCAR_PERIODIC_TRAINING_SEPARATE_MODE != 0U) */

/*******************************************************************************
 *    macro for channel selection loop
 ******************************************************************************/
static uint32_t r_vch_nxt(uint32_t pos)
{
    uint32_t posn;

    for (posn = pos; posn < DRAM_CH_CNT; posn++)
    {
        if ((ddr_phyvalid & (1U << posn)) != 0x0U)
        {
            break;
        }
    }
    return posn;
}

#define r_foreach_vch(ch) \
for (ch = r_vch_nxt(0); ch < DRAM_CH_CNT; ch = r_vch_nxt(ch + 1U))

#define r_foreach_ech(ch) \
for (ch = 0U; ch < DRAM_CH_CNT; ch++)

/*******************************************************************************
 *    Printing functions
 ******************************************************************************/
#define MSG_LF(...)

/*******************************************************************************
 *    clock settings, reset control
 ******************************************************************************/
static void r_cpg_write_32(uint32_t a, uint32_t v)
{
    mmio_write_32(CPG_CPGWPR, ~v);
    mmio_write_32(a, v);
}

static void r_pll3_control(uint32_t mode)
{
    uint32_t dataDIV, dataMUL;
    uint32_t ssmode, ssmode_high, dataNF;
    /* PLL3VCO       = EXTAL * ddr_mul * 1/2               */
    /* clk_ctlr_sync = PLL3VCO * pll3_div                  */
    /* ddr_mul       = (NI[7:0] + 1) * 2 + NF[24:0] / 2^24 */

#if (RCAR_PLL3_FRAC_MODE == 1U)
    ssmode_high = 0x4U;
#else
    ssmode_high = 0x0U;
#endif /* (RCAR_PLL3_FRAC_MODE == 1U) */

    switch (mode)
    {
        case PLL3_LOW_FREQUENCY_MODE:
            /* Low frequency mode (50MHz) */
            dataMUL = (ddr_mul_low / 2U) - 1U;    /* PLL3VCO = 1600MHz */
            dataDIV = 0x9U;                       /* div     = 32      */
            dataNF = 0x00U;
            ssmode = 0x0U;
            break;
        case PLL3_MEDIUM_FREQUENCY_MODE:
            /* Medium frequency mode */
            dataMUL = (ddr_mul / 2U) - 1U;
            dataDIV = ddr_medium_div;
            dataNF = ddr_mul_nf;
            ssmode = ssmode_high;
            break;
        case PLL3_HIGH_FREQUENCY_MODE:
            /* High frequency mode */
            dataMUL = (ddr_mul / 2U) - 1U;
            dataDIV = 0x0U;                       /* div     = 2 */
            dataNF = ddr_mul_nf;
            ssmode = ssmode_high;
            break;
        case PLL3_HIGH_FREQUENCY_MODE_LOAD_REGISTER:
            /* High frequency mode for loading to DDRPHY registers */
            dataMUL = (ddr_mul_reg / 2U) - 1U;
            dataDIV = 0x0U;                       /* div     = 2 */
            dataNF = 0x00U;
            ssmode = ssmode_high;
            break;
        default:
            /* High frequency mode */
            dataMUL = (ddr_mul / 2U) - 1U;
            dataDIV = 0x0U;                       /* div     = 2 */
            dataNF = ddr_mul_nf;
            ssmode = ssmode_high;
            break;
    }/* mode setting */

    dataMUL = (dataMUL << 20) | (ssmode << 16);
    dataNF  = (dataNF  << 21);

    if (((mmio_read_32(CPG_PLL3CR0) & 0x3FFFFF7FU) != dataMUL) || (mmio_read_32(CPG_PLL3CR1) != dataNF))
    {
        /* PLL3CR0 multiplie set */
        r_cpg_write_32(CPG_PLL3CR0, dataMUL);
        /* PLL3CR1 multiplie set */
        r_cpg_write_32(CPG_PLL3CR1, dataNF);
        r_cpg_write_32(CPG_PLL3CR0, mmio_read_32(CPG_PLL3CR0) | CPG_PLL3CR0_KICK_BIT);
        while ((mmio_read_32(CPG_PLLECR) & CPG_PLLECR_PLL3ST_BIT) != CPG_PLLECR_PLL3ST_BIT)
        {
            ; /* Nothing */
        }
    }

    /* PLL3 DIV set(Target value) */
    while (((mmio_read_32(CPG_FRQCRD0) & CPG_FRQCRD_KICK_BIT)) != 0x0U)
    {
        ; /* Nothing */
    }
    r_cpg_write_32(CPG_FRQCRD0, dataDIV | (mmio_read_32(CPG_FRQCRD0) & 0xFFFFFFF0U));
    r_cpg_write_32(CPG_FRQCRD0, mmio_read_32(CPG_FRQCRD0) | CPG_FRQCRD_KICK_BIT);
    while (((mmio_read_32(CPG_FRQCRD0) & CPG_FRQCRD_KICK_BIT)) != 0x0U)
    {
        ; /* Nothing */
    }
}

/*******************************************************************************
 *    DDR memory register access
 ******************************************************************************/
static void r_send_dbcmd(uint32_t cmd)
{
    /* dummy read */
    (void)mmio_read_32(DBSC_DBCMD);

    while (((mmio_read_32(DBSC_DBWAIT)) & 0x01U) != 0x0U)
    {
        ; /* Nothing */
    }

    r_dbsc_write_32((DBSC_DBCMD), cmd);
}

/*******************************************************************************
 *    DDRPHY register access (raw)
 ******************************************************************************/
static uint32_t r_reg_ddrphy_read(uint32_t phyno, uint32_t regadd)
{
    uint32_t val;

    val = 0U;
    mmio_write_32(DBSC_DBPDRGA(phyno), (regadd | 0x00004000U));
    while (mmio_read_32(DBSC_DBPDRGA(phyno)) != (regadd | 0x0000C000U))
    {
        ; /* Nothing */
    }

    val = mmio_read_32(DBSC_DBPDRGA(phyno));

    mmio_write_32(DBSC_DBPDRGA(phyno), regadd | 0x00008000U);
    while (mmio_read_32(DBSC_DBPDRGA(phyno)) != regadd)
    {
        ; /* Nothing */
    }

    mmio_write_32(DBSC_DBPDRGA(phyno), regadd | 0x00008000U);
    while (mmio_read_32(DBSC_DBPDRGA(phyno)) != regadd)
    {
        ; /* Nothing */
    }

    val = mmio_read_32(DBSC_DBPDRGD(phyno));
    (void)val;

    return val;
}

static void r_reg_ddrphy_write(uint32_t phyno, uint32_t regadd, uint32_t regdata)
{
    mmio_write_32(DBSC_DBPDRGA(phyno), regadd);
    while (mmio_read_32(DBSC_DBPDRGA(phyno)) != regadd)
    {
        ; /* Nothing */
    }

    mmio_write_32(DBSC_DBPDRGD(phyno), regdata);
    while (mmio_read_32(DBSC_DBPDRGA(phyno)) != (regadd | 0x00008000U))
    {
        ; /* Nothing */
    }

    mmio_write_32(DBSC_DBPDRGA(phyno), (regadd | 0x00008000U));
    while (mmio_read_32(DBSC_DBPDRGA(phyno)) != regadd)
    {
        ; /* Nothing */
    }

    mmio_write_32(DBSC_DBPDRGA(phyno), regadd);
}

static void r_reg_ddrphy_write_a(uint32_t regadd, uint32_t regdata)
{
    uint32_t ch;

    r_foreach_vch((ch))
    {
        r_reg_ddrphy_write(ch, regadd, regdata);
    }
}

static void r_reg_ddrphy_masked_write(uint32_t phyno, uint32_t regadd, uint32_t regdata, uint32_t msk)
{
    mmio_write_32(DBSC_DBPDRGM(phyno), msk);
    while (mmio_read_32(DBSC_DBPDRGM(phyno)) != msk)
    {
        ; /* Nothing */
    }

    mmio_write_32(DBSC_DBPDRGA(phyno), regadd);
    while (mmio_read_32(DBSC_DBPDRGA(phyno)) != regadd)
    {
        ; /* Nothing */
    }

    mmio_write_32(DBSC_DBPDRGD(phyno), regdata);
    while (mmio_read_32(DBSC_DBPDRGA(phyno)) != (regadd | 0x00008000U))
    {
        ; /* Nothing */
    }

    mmio_write_32(DBSC_DBPDRGA(phyno), regadd | 0x00008000U);
    while (mmio_read_32(DBSC_DBPDRGA(phyno)) != regadd)
    {
        ; /* Nothing */
    }

    mmio_write_32(DBSC_DBPDRGA(phyno), regadd);

    mmio_write_32(DBSC_DBPDRGM(phyno), 0x00U);
    while (mmio_read_32(DBSC_DBPDRGM(phyno)) != 0x00U)
    {
        ; /* Nothing */
    }
}

/*******************************************************************************
 *    DDRPHY register access (field modify)
 ******************************************************************************/
static void r_ddr_setval_s(uint32_t ch, uint32_t slice, uint32_t regdef, uint32_t val)
{
    uint32_t adr;
    uint32_t lsb;
    uint32_t len;
    uint32_t msk;
    uint32_t tmp;

    adr = DDR_REGDEF_ADR(regdef) + (0x100U * slice);
    len = DDR_REGDEF_LEN(regdef);
    lsb = DDR_REGDEF_LSB(regdef);
    if (len == 0x20U)
    {
        tmp = 0xFFFFFFFFU;
    }
    else
    {
        tmp = ((1U << len) - 1U) << lsb;
    }

    msk = (~(((tmp >> 21) & 0x08U) | ((tmp >> 14) & 0x04U) | ((tmp >> 7) & 0x02U) | (tmp & 0x01U))) & 0x0FU;

    r_reg_ddrphy_masked_write(ch, adr, (val << lsb), msk);
}

static uint32_t r_ddr_getval_s(uint32_t ch, uint32_t slice, uint32_t regdef)
{
    uint32_t adr;
    uint32_t lsb;
    uint32_t len;
    uint32_t msk;
    uint32_t tmp;

    adr = DDR_REGDEF_ADR(regdef) + (0x100U * slice);
    len = DDR_REGDEF_LEN(regdef);
    lsb = DDR_REGDEF_LSB(regdef);
    if (len == 0x20U)
    {
        msk = 0xFFFFFFFFU;
    }
    else
    {
        msk = ((1U << len) - 1U);
    }

    tmp = r_reg_ddrphy_read(ch, adr);
    tmp = (tmp >> lsb) & msk;

    return tmp;
}

static void r_ddr_setval(uint32_t ch, uint32_t regdef, uint32_t val)
{
    r_ddr_setval_s(ch, 0U, regdef, val);
}

static void r_ddr_setval_ach_s(uint32_t slice, uint32_t regdef, uint32_t val)
{
    uint32_t ch;

    r_foreach_vch((ch))
    {
        r_ddr_setval_s(ch, slice, regdef, val);
    }
}

static void r_ddr_setval_ach(uint32_t regdef, uint32_t val)
{
    r_ddr_setval_ach_s(0U, regdef, val);
}

static void r_ddr_setval_ach_as(uint32_t regdef, uint32_t val)
{
    uint32_t slice;

    for (slice = 0U; slice < SLICE_CNT; slice++)
    {
        r_ddr_setval_ach_s(slice, regdef, val);
    }
}

static uint32_t r_ddr_getval(uint32_t ch, uint32_t regdef)
{
    return r_ddr_getval_s(ch, 0U, regdef);
}

/*******************************************************************************
 *    DBSC0 register access
 ******************************************************************************/
static void r_dbsc_write_32(uintptr_t addr, uint32_t data)
{
    *((volatile uint32_t*)addr) = data;
}

/*******************************************************************************
 *    handling functions for setteing ddrphy value table
 ******************************************************************************/
static void r_tbl_copy(uint32_t *to, const uint32_t *from, uint32_t size)
{
    uint32_t i;

    for (i = 0U; i < size; i++)
    {
        to[i] = from[i];
    }
}

static void r_ddrtbl_setval(uint32_t *tbl, uint32_t regdef, uint32_t val)
{
    uint32_t adr;
    uint32_t lsb;
    uint32_t len;
    uint32_t msk;
    uint32_t tmp;
    const uint32_t adrmsk = 0x000000FFU;

    adr = DDR_REGDEF_ADR(regdef);
    len = DDR_REGDEF_LEN(regdef);
    lsb = DDR_REGDEF_LSB(regdef);
    if (len == 0x20U)
    {
        msk = 0xFFFFFFFFU;
    }
    else
    {
        msk = ((1U << len) - 1U) << lsb;
    }

    tmp = tbl[adr & adrmsk];
    tmp = (tmp & (~msk)) | ((val << lsb) & msk);
    tbl[adr & adrmsk] = tmp;
}

static void r_ddrtbl_setval_pi(uint32_t *tbl, uint32_t regdef, uint32_t val)
{
    uint32_t adr;
    uint32_t lsb;
    uint32_t len;
    uint32_t msk;
    uint32_t tmp;
    const uint32_t adrmsk = 0x000007FFU;

    adr = DDR_REGDEF_ADR(regdef);
    len = DDR_REGDEF_LEN(regdef);
    lsb = DDR_REGDEF_LSB(regdef);
    if (len == 0x20U)
    {
        msk = 0xFFFFFFFFU;
    }
    else
    {
        msk = ((1U << len) - 1U) << lsb;
    }

    tmp = tbl[adr & adrmsk];
    tmp = (tmp & (~msk)) | ((val << lsb) & msk);
    tbl[adr & adrmsk] = tmp;
}

static uint32_t r_ddrtbl_getval(const uint32_t *tbl, uint32_t regdef)
{
    uint32_t adr;
    uint32_t lsb;
    uint32_t len;
    uint32_t msk;
    uint32_t tmp;
    const uint32_t adrmsk = 0x000000FFU;

    adr = DDR_REGDEF_ADR(regdef);
    len = DDR_REGDEF_LEN(regdef);
    lsb = DDR_REGDEF_LSB(regdef);
    if (len == 0x20U)
    {
        msk = 0xFFFFFFFFU;
    }
    else
    {
        msk = ((1U << len) - 1U);
    }

    tmp = tbl[adr & adrmsk];
    tmp = (tmp >> lsb) & msk;

    return tmp;
}

#if ((RCAR_PERIODIC_WRITE_TRAINING != 0U) || (RCAR_PERIODIC_READ_TRAINING != 0U))
static uint32_t r_ddrtbl_getval_pi(const uint32_t *tbl, uint32_t regdef)
{
    uint32_t adr;
    uint32_t lsb;
    uint32_t len;
    uint32_t msk;
    uint32_t tmp;
    const uint32_t adrmsk = 0x000007FFU;

    adr = DDR_REGDEF_ADR(regdef);
    len = DDR_REGDEF_LEN(regdef);
    lsb = DDR_REGDEF_LSB(regdef);
    if (len == 0x20U)
    {
        msk = 0xFFFFFFFFU;
    }
    else
    {
        msk = ((1U << len) - 1U);
    }

    tmp = tbl[adr & adrmsk];
    tmp = (tmp >> lsb) & msk;

    return tmp;
}
#endif /* ((RCAR_PERIODIC_WRITE_TRAINING != 0U) || (RCAR_PERIODIC_READ_TRAINING != 0U)) */

/*******************************************************************************
 *    functions and parameters for timing setting
 ******************************************************************************/
typedef struct
{
    uint32_t fx3;
    uint8_t RLset1;
    uint8_t RLset2;
    uint8_t WLsetA;
    uint8_t WLsetB;
    uint32_t nWR;
    uint32_t nRBTP;
    uint32_t ODTLon;
    uint8_t MR1;
    uint8_t MR2;
    uint32_t WCKENLR;
    uint32_t WCKENLW;
    uint32_t WCKENLF;
    uint32_t WCKPRESTA;
    uint32_t WCKPRETGLR;
} jedec_spec1_t;

#define JS1_USABLEC_SPEC_LO    5U
#define JS1_USABLEC_SPEC_HI    11U
#define JS1_FREQ_TBL_NUM       12U
#define JS1_MR1(f)    (0x00U | ((f) << 4))    /* CK mode = 0B */
#define JS1_MR2(f)    (((f) << 4) | (f))

static const jedec_spec1_t js1[JS1_FREQ_TBL_NUM] =
{
    /* fx3,RL1,RL2,WLA.WLB.nWR.nRBTP,ODTLon */
    {  800,  3,  3,  2,  2,  3, 0, 1, JS1_MR1(0),  JS1_MR2(0),  0, 0, 0, 1, 3 }, /*  533.333Mbps */
    { 1600,  4,  4,  2,  3,  5, 0, 1, JS1_MR1(1),  JS1_MR2(1),  0, 0, 0, 1, 4 }, /* 1066.666Mbps */
    { 2400,  5,  6,  3,  4,  7, 0, 2, JS1_MR1(2),  JS1_MR2(2),  1, 1, 1, 1, 4 }, /* 1600.000Mbps */
    { 3200,  7,  7,  4,  5, 10, 0, 2, JS1_MR1(3),  JS1_MR2(3),  2, 1, 1, 2, 4 }, /* 2133.333Mbps */
    { 4000,  8,  9,  4,  7, 12, 1, 2, JS1_MR1(4),  JS1_MR2(4),  2, 1, 1, 2, 5 }, /* 2666.666Mbps */
    { 4800, 10, 10,  5,  8, 14, 1, 3, JS1_MR1(5),  JS1_MR2(5),  4, 2, 1, 2, 5 }, /* 3200.000Mbps */
    { 5600, 11, 12,  6,  9, 16, 2, 4, JS1_MR1(6),  JS1_MR2(6),  4, 2, 1, 3, 5 }, /* 3733.333Mbps */
    { 6400, 13, 14,  6, 11, 19, 2, 3, JS1_MR1(7),  JS1_MR2(7),  5, 2, 1, 3, 6 }, /* 4266.666Mbps */
    { 7200, 14, 15,  7, 12, 21, 3, 4, JS1_MR1(8),  JS1_MR2(8),  6, 3, 2, 3, 6 }, /* 4800.000Mbps */
    { 8250, 16, 17,  8, 14, 24, 4, 5, JS1_MR1(9),  JS1_MR2(9),  7, 3, 2, 4, 6 }, /* 5500.000Mbps */
    { 9000, 17, 19,  9, 15, 26, 4, 6, JS1_MR1(10), JS1_MR2(10), 7, 4, 2, 4, 7 }, /* 6000.000Mbps */
    { 9600, 18, 20,  9, 16, 28, 4, 6, JS1_MR1(11), JS1_MR2(11), 8, 4, 2, 4, 7 }  /* 6400.000Mbps */
};

typedef struct
{
    uint16_t ps;
    uint16_t cyc;
} jedec_spec2_t;

#define JS2_tSR            0U
#define JS2_tXP            1U
#define JS2_tRCD           2U
#define JS2_tRPpb          3U
#define JS2_tRPab          4U
#define JS2_tRAS           5U
#define JS2_tWTR_S         6U
#define JS2_tWTR_L         7U
#define JS2_tRRD           8U
#define JS2_tPPD           9U
#define JS2_tFAW           10U
#define JS2_tMRR           11U
#define JS2_tMRW           12U
#define JS2_tMRD           13U
#define JS2_tZQCALns       14U
#define JS2_tZQLAT         15U
#define JS2_tODTon_min     16U
#define JS2_tPDN_DSM       17U
#define JS2_tXSR_DSM       18U
#define JS2_tXDSM_XP       19U
#define JS2_tWCK2DQI_HF    20U
#define JS2_tWCK2DQO_HF    21U
#define JS2_tWCK2DQI_LF    22U
#define JS2_tWCK2DQO_LF    23U
#define JS2_tOSCODQI       24U
#define JS2_tDQ72DQns      25U
#define JS2_tCAENTns       26U
#define JS2_tCSCAL         27U
#define JS2_tWCKSTOP       28U
#define JS2_TBLCNT         29U

#define JS2_tRCpb        (JS2_TBLCNT)
#define JS2_tRCab        (JS2_TBLCNT + 1U)
#define JS2_tRFCab       (JS2_TBLCNT + 2U)
#define JS2_tRBTP        (JS2_TBLCNT + 3U)
#define JS2_tXSR         (JS2_TBLCNT + 4U)
#define JS2_tPDN         (JS2_TBLCNT + 5U)
#define JS2_tWLWCKOFF    (JS2_TBLCNT + 6U)
#define JS2_CNT          (JS2_TBLCNT + 7U)

#ifndef JS2_DERATE
#define JS2_DERATE    0
#endif

static const jedec_spec2_t jedec_spec2[2][JS2_TBLCNT] =
{
    {
/* tSR */         {  15000,  2 },
/* tXP */         {   7000,  3 },
/* tRCD */        {  18000,  2 },
/* tRPpb */       {  18000,  2 },
/* tRPab */       {  21000,  2 },
/* tRAS */        {  42000,  3 },
/* tWTR_S */      {   6250,  4 },
/* tWTR_L */      {  12000,  4 },
/* tRRD */        {   5000,  2 },
/* tPPD */        {      0,  2 },
/* tFAW */        {  20000,  0 },
/* tMRR */        {      0,  4 },
/* tMRW */        {  10000,  5 },
/* tMRD */        {  14000,  5 },
/* tZQCALns */    {   1500,  0 },
/* tZQLAT */      {  30000,  4 },
/* tODTon_min */  {   1500,  0 },
/* tPDN_DSMus */  {   4000,  0 },
/* tXSR_DSMus */  {    200,  0 },
/* tXDSM_XPus */  {    190,  0 },
/* tWCK2DQI_HF */ {    700,  0 },
/* tWCK2DQO_HF */ {   1600,  0 },
/* tWCK2DQI_LF */ {    900,  0 },
/* tWCK2DQO_LF */ {   1900,  0 },
/* tOSCODQI */    {  40000,  8 },
/* tDQ72DQns */   {    125,  0 },
/* tCAENTns */    {    250,  0 },
/* tCSCAL */      {   1750,  0 },
/* tWCKSTOP */    {   6000,  2 }
    },{
/* tSR */         {  15000,  2 },
/* tXP */         {   7000,  3 },
/* tRCD */        {  19875,  2 },
/* tRPpb */       {  19875,  2 },
/* tRPab */       {  22875,  2 },
/* tRAS */        {  43875,  3 },
/* tWTR_S */      {   6250,  4 },
/* tWTR_L */      {  12000,  4 },
/* tRRD */        {   5000,  2 },
/* tPPD */        {      0,  2 },
/* tFAW */        {  20000,  0 },
/* tMRR */        {      0,  4 },
/* tMRW */        {  10000,  5 },
/* tMRD */        {  14000,  5 },
/* tZQCALns */    {   1500,  0 },
/* tZQLAT */      {  30000,  4 },
/* tODTon_min */  {   1500,  0 },
/* tPDN_DSMus */  {   4000,  0 },
/* tXSR_DSMus */  {    200,  0 },
/* tXDSM_XPus */  {    190,  0 },
/* tWCK2DQI_HF */ {    715,  0 },
/* tWCK2DQO_HF */ {   1635,  0 },
/* tWCK2DQI_LF */ {    920,  0 },
/* tWCK2DQO_LF */ {   1940,  0 },
/* tOSCODQI */    {  40000,  8 },
/* tDQ72DQns */   {    125,  0 },
/* tCAENTns */    {    250,  0 },
/* tCSCAL */      {   1750,  0 },
/* tWCKSTOP */    {   6000,  2 }
    }
};

static const uint16_t jedec_spec2_tRFC_ab[9] =
{
/*  2Gb, 3Gb, 4Gb, 6Gb, 8Gb, 12Gb, 16Gb, 24Gb, 32Gb */
    130, 180, 180, 210, 210, 280,  280,  380,  380
};

static uint32_t js1_ind;
static uint32_t js2[JS2_CNT];
static uint32_t RL;
static uint32_t WL;

static uint16_t r_f_scale(uint32_t f_ddr_mbps, uint32_t f_ddr_mbpsdiv, uint32_t ps, uint16_t cyc)
{
    uint32_t tmp;
    uint32_t f_scale_div;

    tmp = (((uint32_t)(ps) + 9U) / 10U) * f_ddr_mbps;
    f_scale_div = tmp / (800000U * f_ddr_mbpsdiv);
    if (tmp != (f_scale_div * 800000U * f_ddr_mbpsdiv))
    {
        f_scale_div = f_scale_div + 1U;
    }

    if (f_scale_div > cyc)
    {
        cyc = (uint16_t)f_scale_div;
    }

    return cyc;
}

static uint32_t r_f_scale_l(uint32_t f_ddr_mbps, uint32_t f_ddr_mbpsdiv, uint32_t ps, uint32_t cyc)
{
    uint32_t tmp;
    uint32_t f_scale_div;

    tmp = (((uint32_t)(ps) + 9U) / 10U) * f_ddr_mbps;
    f_scale_div = tmp / (8U * f_ddr_mbpsdiv);
    if (tmp != (f_scale_div * 8U * f_ddr_mbpsdiv))
    {
        f_scale_div = f_scale_div + 1U;
    }

    if (f_scale_div > cyc)
    {
        cyc = (uint32_t)f_scale_div;
    }

    return cyc;
}

static void r_f_scale_js2(uint32_t f_ddr_mbps, uint32_t f_ddr_mbpsdiv, uint32_t *f_js2)
{
    uint32_t i;

    for (i = 0U; i < JS2_TBLCNT; i++)
    {
        f_js2[i] = r_f_scale(f_ddr_mbps, f_ddr_mbpsdiv,
            (uint32_t)jedec_spec2[JS2_DERATE][i].ps,
            jedec_spec2[JS2_DERATE][i].cyc);
    }

    f_js2[JS2_tZQCALns]  = r_f_scale(f_ddr_mbps, f_ddr_mbpsdiv, (uint32_t)(jedec_spec2[JS2_DERATE][JS2_tZQCALns].ps) * 1000U, 0U);
    f_js2[JS2_tDQ72DQns] = r_f_scale(f_ddr_mbps, f_ddr_mbpsdiv, (uint32_t)(jedec_spec2[JS2_DERATE][JS2_tDQ72DQns].ps) * 1000U, 0U);
    f_js2[JS2_tCAENTns]  = r_f_scale(f_ddr_mbps, f_ddr_mbpsdiv, (uint32_t)(jedec_spec2[JS2_DERATE][JS2_tCAENTns].ps) * 1000U, 0U);
    f_js2[JS2_tRCpb]     = f_js2[JS2_tRAS] + f_js2[JS2_tRPpb];
    f_js2[JS2_tRCab]     = f_js2[JS2_tRAS] + f_js2[JS2_tRPab];
    f_js2[JS2_tRFCab]    = r_f_scale(f_ddr_mbps, f_ddr_mbpsdiv, 1UL * jedec_spec2_tRFC_ab[max_density] * 1000U, 0U);

    f_js2[JS2_tRBTP]     = r_f_scale(f_ddr_mbps, f_ddr_mbpsdiv, 7500U, 2U) - 2U;
    f_js2[JS2_tXSR]      = f_js2[JS2_tRFCab] + r_f_scale(f_ddr_mbps, f_ddr_mbpsdiv, 7500U, 2U);
    f_js2[JS2_tPDN]      = r_f_scale(f_ddr_mbps, f_ddr_mbpsdiv, 10000U, 0U) + 1U;
    f_js2[JS2_tPDN_DSM]  = r_f_scale_l(f_ddr_mbps, f_ddr_mbpsdiv, (uint32_t)(jedec_spec2[JS2_DERATE][JS2_tPDN_DSM].ps) * 10U, 0U);
    f_js2[JS2_tXSR_DSM]  = r_f_scale_l(f_ddr_mbps, f_ddr_mbpsdiv, (uint32_t)(jedec_spec2[JS2_DERATE][JS2_tXSR_DSM].ps) * 10U, 0U);
    f_js2[JS2_tXDSM_XP]  = r_f_scale_l(f_ddr_mbps, f_ddr_mbpsdiv, (uint32_t)(jedec_spec2[JS2_DERATE][JS2_tXDSM_XP].ps) * 10U, 0U);
    f_js2[JS2_tWLWCKOFF] = r_f_scale(f_ddr_mbps, f_ddr_mbpsdiv, 14000U, 5U);
}

static const uint32_t PI_DARRAY3_0_CSx_Fx[CS_CNT][3] =
{
    {
        PI_DARRAY3_0_CS0_F0,
        PI_DARRAY3_0_CS0_F1,
        PI_DARRAY3_0_CS0_F2
    },
    {
        PI_DARRAY3_0_CS1_F0,
        PI_DARRAY3_0_CS1_F1,
        PI_DARRAY3_0_CS1_F2
    }
};

static const uint32_t PI_DARRAY3_1_CSx_Fx[CS_CNT][3] =
{
    {
        PI_DARRAY3_1_CS0_F0,
        PI_DARRAY3_1_CS0_F1,
        PI_DARRAY3_1_CS0_F2
    },
    {
        PI_DARRAY3_1_CS1_F0,
        PI_DARRAY3_1_CS1_F1,
        PI_DARRAY3_1_CS1_F2
    }
};

/*******************************************************************************
 *    load table data into DDR registers
 ******************************************************************************/
static void r_ddrtbl_load(void)
{
    uint32_t i;
    uint32_t slice;
    uint32_t cs;
    uint32_t adr;
    uint32_t dataL;
    uint32_t tmp[2];

    /* Setting RDDQ delay = 103ps */
    const uint32_t rddq_delay = 103U;

    const uint32_t DDR_PHY_SLICE_REGSET_OFS = DDR_PHY_SLICE_REGSET_OFS_V4M;
    const uint32_t DDR_PHY_ADR_V_REGSET_OFS = DDR_PHY_ADR_V_REGSET_OFS_V4M;
    const uint32_t DDR_PHY_ADR_G_REGSET_OFS = DDR_PHY_ADR_G_REGSET_OFS_V4M;
    const uint32_t DDR_PI_REGSET_OFS        = DDR_PI_REGSET_OFS_V4M;

    const uint32_t DDR_PHY_SLICE_REGSET_SIZE = DDR_PHY_SLICE_REGSET_SIZE_V4M;

    const uint32_t DDR_PHY_SLICE_REGSET_NUM = DDR_PHY_SLICE_REGSET_NUM_V4M;
    const uint32_t DDR_PHY_ADR_V_REGSET_NUM = DDR_PHY_ADR_V_REGSET_NUM_V4M;
    const uint32_t DDR_PHY_ADR_G_REGSET_NUM = DDR_PHY_ADR_G_REGSET_NUM_V4M;
    const uint32_t DDR_PI_REGSET_NUM        = DDR_PI_REGSET_NUM_V4M;

    /***********************************************************************
     * TIMING REGISTERS
     ***********************************************************************/
    /* search jedec_spec1 index */
    for (i = JS1_USABLEC_SPEC_LO; i < (JS1_FREQ_TBL_NUM - 1U); i++)
    {
        if ((js1[i].fx3 * 2U * ddr_mbpsdiv) >= (ddr_mbps * 3U))
        {
            break;
        }
    }

    if (JS1_USABLEC_SPEC_HI < i)
    {
        js1_ind = JS1_USABLEC_SPEC_HI;
    }
    else
    {
        js1_ind = i;
    }

    RL = js1[js1_ind].RLset1;

    WL = js1[js1_ind].WLsetA;

    /* calculate jedec_spec2 */
    r_f_scale_js2(ddr_mbps, ddr_mbpsdiv, js2);

    /***********************************************************************
     * PREPARE TBL
     ***********************************************************************/
    r_tbl_copy(DDR_PHY_SLICE_REGSET,
        DDR_PHY_SLICE_REGSET_V4M, DDR_PHY_SLICE_REGSET_NUM_V4M);
    r_tbl_copy(DDR_PHY_ADR_V_REGSET,
        DDR_PHY_ADR_V_REGSET_V4M, DDR_PHY_ADR_V_REGSET_NUM_V4M);
    r_tbl_copy(DDR_PHY_ADR_G_REGSET,
        DDR_PHY_ADR_G_REGSET_V4M, DDR_PHY_ADR_G_REGSET_NUM_V4M);
    r_tbl_copy(DDR_PI_REGSET,
        DDR_PI_REGSET_V4M, DDR_PI_REGSET_NUM_V4M);

    /***********************************************************************
     * Adjust PI paramters
     ***********************************************************************/
    dataL = 10000U * ddr_mbps / ddr_mbpsdiv / 8U / 256U;
    r_ddrtbl_setval(DDR_PHY_ADR_G_REGSET, PHY_CAL_INTERVAL_COUNT_0, dataL);

    dataL = rddq_delay * ddr_mbps * 256U / (ddr_mbpsdiv * 2U * 1000000U);
    r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_RDDQ0_SLAVE_DELAY, dataL);
    r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_RDDQ1_SLAVE_DELAY, dataL);
    r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_RDDQ2_SLAVE_DELAY, dataL);
    r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_RDDQ3_SLAVE_DELAY, dataL);
    r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_RDDQ4_SLAVE_DELAY, dataL);
    r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_RDDQ5_SLAVE_DELAY, dataL);
    r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_RDDQ6_SLAVE_DELAY, dataL);
    r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_RDDQ7_SLAVE_DELAY, dataL);
    r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_RDDM_SLAVE_DELAY,  dataL);

    r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WRLAT_F2,                  WL);
    r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TWCKENL_WR_ADJ_F2,        (js1[js1_ind].WCKENLW * 4U) + 4U);
    r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TWCKENL_RD_ADJ_F2,        (js1[js1_ind].WCKENLR * 4U) + 4U);
    r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TWCKPRE_STATIC_F2,        (js1[js1_ind].WCKPRESTA * 4U));
    r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TWCKPRE_TOGGLE_RD_F2,     (js1[js1_ind].WCKPRETGLR * 4U));
    r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_CASLAT_F2,                 RL);
    r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TWCKENL_FS_ADJ_F2,        (js1[js1_ind].WCKENLF * 4U) + 4U);
    r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TRFC_F2,                   js2[JS2_tRFCab]);
    r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WRLVL_WCKOFF_F2,          (js2[JS2_tWLWCKOFF]) + 3U);
    r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WRLAT_ADJ_F2,             (WL * 4U) + 2U);
    r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TCAENT_F2,                 js2[JS2_tCAENTns]);
    r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TVREF_LONG_F2,            (js2[JS2_tCAENTns]) + 1U);
    r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TRCD_F2,                   js2[JS2_tRCD]);
    r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TRP_F2,                    js2[JS2_tRPab]);
    r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TRTP_F2,                   js1[js1_ind].nRBTP);
    r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TRAS_MIN_F2,               js2[JS2_tRAS]);
    r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TMRD_F2,                  (js2[JS2_tMRD]) + 1U);
    r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TSR_F2,                    js2[JS2_tSR]);
    r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TZQCAL_F2,                 js2[JS2_tZQCALns]);
    r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TZQLAT_F2,                 js2[JS2_tZQLAT]);
    r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDQ72DQ_F2,                js2[JS2_tDQ72DQns]);
    r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_MC_TRFC_F2,                js2[JS2_tRFCab]);
    r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WDQLVL_WRLAT_ADJ_F2,      (WL * 4U) - 2U);
    r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WDQLVL_TWCKENL_RD_ADJ_F2, (js1[js1_ind].WCKENLR * 4U) + 4U);
    r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDFI_WCK_STOP_F2,         (js2[JS2_tWCKSTOP]) + 2U);

    if (ddr_mbps < (3201U * ddr_mbpsdiv))
    {
        /* 2751 - 3200 */
        r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_LP4_BOOT_RX_PCLK_CLK_SEL, 0x00U);
        r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_WRLVL_PER_START,          0x40U);
        r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_REGULATOR_EN_CNT,         0x05U);
        r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_RX_CAL_ALL_DLY,           0x07U);
        r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_RDDATA_EN_TSEL_DLY,       0x08U);
        r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_RDDATA_EN_OE_DLY,         0x0BU);
        r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_RPTR_UPDATE,              0x07U);
        r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_WRLVL_RESP_WAIT_CNT,      0x25U);
        r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_RDLVL_MAX_EDGE,           0x012DU);
        r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_RDDATA_EN_DLY,            0x0BU);
        r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_RDDQS_LATENCY_ADJUST,     0x04U);
        r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_GTLVL_LAT_ADJ_START,      0x03U);

        r_ddrtbl_setval(DDR_PHY_ADR_V_REGSET, PHY_ADR_MEAS_DLY_STEP_ENABLE, 0x00U);
        r_ddrtbl_setval(DDR_PHY_ADR_V_REGSET, PHY_ADR_CALVL_DLY_STEP,       0x02U);

        r_ddrtbl_setval(DDR_PHY_ADR_G_REGSET, PHY_TCKSRE_WAIT, 0x01U);

        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TCKCKEL_F2,                0x03U);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDELAY_RDWR_2_BUS_IDLE_F2, 0x57U);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WCK_ACTIVE_WR_F2,          0x08U);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WCK_ACTIVE_RD_F2,          0x0DU);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TREF_F2,                   0x000613U);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDFI_WRLVL_WW_F2,          0x002BU);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_RDLAT_ADJ_F2,              0x0022U);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDFI_CALVL_CC_F2,          0x0043U);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDFI_CALVL_CAPTURE_F2,     0x001DU);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TVRCG_ENABLE_F2,           0x0065U);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TVRCG_DISABLE_F2,          0x0029U);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDFI_CALVL_STROBE_F2,      0x06U);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TXP_F2,                    0x07U);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TMRWCKEL_F2,               0x0AU);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TCKEHDQS_F2,               0x12U);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TFC_F2,                    0x0064U);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDFI_WDQLVL_WR_F2,         0x0012U);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDFI_WDQLVL_RW_F2,         0x0010U);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WDQLVL_RDLAT_ADJ_F2,       0x0022U);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TWTR_S_F2,                 0x05U);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TWTR_L_F2,                 0x05U);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TWTR_F2,                   0x05U);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TWR_F2,                    0x0EU);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TRAS_MAX_F2,               0x62B8U);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDQSCK_MAX_F2,             0x01U);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDFI_CTRLUPD_MAX_F2,       0x000C26U);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDFI_CTRLUPD_INTERVAL_F2,  0x0000797CU);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TXSR_F2,                   0x009BU);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TINIT_F2,                  0x013880U);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TINIT1_F2,                 0x013880U);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TINIT3_F2,                 0x0C3500U);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TINIT4_F2,                 0x000014U);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TINIT5_F2,                 0x000320U);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TXSNR_F2,                  0x009BU);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_ZQRESET_F2,                0x0014U);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TCBTRTW_F2,                0x04U);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_16_F2,            0x000064U);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_17_F2,            0x000002U);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_18_F2,            0x000007U);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_19_F2,            0x000002U);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_20_F2,            0x000002U);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_21_F2,            0x000320U);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_22_F2,            0x000002U);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_23_F2,            0x00000EU);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_24_F2,            0x000029U);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_25_F2,            0x000065U);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_26_F2,            0x000005U);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_27_F2,            0x000000U);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_31_F2,            0x000065U);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WP_GAP_0_F2,               0x0016U);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_RP_GAP_0_F2,               0x0003U);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WR_GAP_S_0_F2,             0x000CU);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WR_GAP_L_0_F2,             0x000CU);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_RW_GAP_0_F2,               0x0007U);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WP_GAP_1_F2,               0x0016U);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_RP_GAP_1_F2,               0x0003U);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WR_GAP_S_1_F2,             0x000CU);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WR_GAP_L_1_F2,             0x000CU);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_RW_GAP_1_F2,               0x0007U);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WP_GAP_2_F2,               0x0016U);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_RP_GAP_2_F2,               0x0003U);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WR_GAP_S_2_F2,             0x000CU);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WR_GAP_L_2_F2,             0x000CU);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_RW_GAP_2_F2,               0x0007U);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WP_GAP_3_F2,               0x0016U);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_RP_GAP_3_F2,               0x0003U);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WR_GAP_S_3_F2,             0x000CU);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WR_GAP_L_3_F2,             0x000CU);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_RW_GAP_3_F2,               0x0007U);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_DARRAY3_2_CS0_F2,          0xD6U);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_DARRAY3_2_CS1_F2,          0xD6U);
    }
    else if (ddr_mbps < (3734U * ddr_mbpsdiv))
    {
        /* 3201 - 3733 */
        r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_LP4_BOOT_RX_PCLK_CLK_SEL, 0x00U);
        r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_WRLVL_PER_START,          0x40U);
        r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_REGULATOR_EN_CNT,         0x06U);
        r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_RX_CAL_ALL_DLY,           0x08U);
        r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_RDDATA_EN_TSEL_DLY,       0x0AU);
        r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_RDDATA_EN_OE_DLY,         0x0DU);
        r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_RPTR_UPDATE,              0x08U);
        r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_WRLVL_RESP_WAIT_CNT,      0x2AU);
        r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_RDLVL_MAX_EDGE,           0x0149U);
        r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_RDDATA_EN_DLY,            0x0DU);
        r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_RDDQS_LATENCY_ADJUST,     0x04U);
        r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_GTLVL_LAT_ADJ_START,      0x04U);
        r_ddrtbl_setval(DDR_PHY_ADR_V_REGSET, PHY_ADR_MEAS_DLY_STEP_ENABLE, 0x00U);
        r_ddrtbl_setval(DDR_PHY_ADR_V_REGSET, PHY_ADR_CALVL_DLY_STEP,       0x02U);

        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TCKCKEL_F2,                0x03U);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDELAY_RDWR_2_BUS_IDLE_F2, 0x5BU);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WCK_ACTIVE_WR_F2,          0x0BU);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WCK_ACTIVE_RD_F2,          0x10U);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TREF_F2,                   0x000717U);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDFI_WRLVL_WW_F2,          0x002CU);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_RDLAT_ADJ_F2,              0x0024U);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDFI_CALVL_CC_F2,          0x0045U);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDFI_CALVL_CAPTURE_F2,     0x001FU);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TVRCG_ENABLE_F2,           0x0076U);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TVRCG_DISABLE_F2,          0x0030U);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDFI_CALVL_STROBE_F2,      0x06U);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TXP_F2,                    0x07U);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TMRWCKEL_F2,               0x0AU);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TCKEHDQS_F2,               0x13U);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TFC_F2,                    0x0075U);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDFI_WDQLVL_WR_F2,         0x0014U);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDFI_WDQLVL_RW_F2,         0x0011U);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WDQLVL_RDLAT_ADJ_F2,       0x0024U);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TWTR_S_F2,                 0x06U);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TWTR_L_F2,                 0x06U);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TWTR_F2,                   0x06U);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TWR_F2,                    0x10U);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TRAS_MAX_F2,               0x7329U);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDQSCK_MAX_F2,             0x01U);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDFI_CTRLUPD_MAX_F2,       0x000E2EU);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDFI_CTRLUPD_INTERVAL_F2,  0x00008DCCU);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TXSR_F2,                   0x00B6U);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TINIT_F2,                  0x016C90U);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TINIT1_F2,                 0x016C90U);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TINIT3_F2,                 0x0E3D98U);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TINIT4_F2,                 0x000018U);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TINIT5_F2,                 0x0003A6U);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TXSNR_F2,                  0x00B5U);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_ZQRESET_F2,                0x0018U);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TCBTRTW_F2,                0x05U);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_16_F2,            0x000075U);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_17_F2,            0x000002U);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_18_F2,            0x000007U);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_19_F2,            0x000002U);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_20_F2,            0x000002U);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_21_F2,            0x0003A6U);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_22_F2,            0x000002U);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_23_F2,            0x000011U);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_24_F2,            0x000030U);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_25_F2,            0x000076U);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_26_F2,            0x000007U);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_27_F2,            0x000000U);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_31_F2,            0x000076U);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WP_GAP_0_F2,               0x0019U);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_RP_GAP_0_F2,               0x0004U);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WR_GAP_S_0_F2,             0x000CU);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WR_GAP_L_0_F2,             0x000EU);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_RW_GAP_0_F2,               0x0007U);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WP_GAP_1_F2,               0x0019U);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_RP_GAP_1_F2,               0x0004U);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WR_GAP_S_1_F2,             0x000CU);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WR_GAP_L_1_F2,             0x000EU);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_RW_GAP_1_F2,               0x0007U);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WP_GAP_2_F2,               0x0019U);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_RP_GAP_2_F2,               0x0004U);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WR_GAP_S_2_F2,             0x000CU);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WR_GAP_L_2_F2,             0x000EU);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_RW_GAP_2_F2,               0x0007U);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WP_GAP_3_F2,               0x0019U);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_RP_GAP_3_F2,               0x0004U);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WR_GAP_S_3_F2,             0x000CU);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WR_GAP_L_3_F2,             0x000EU);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_RW_GAP_3_F2,               0x0007U);
    }
    else if (ddr_mbps < (4268U * ddr_mbpsdiv))
    {
        /* 3734 - 4267 */
        r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_LP4_BOOT_RX_PCLK_CLK_SEL, 0x00U);
        r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_WRLVL_PER_START,          0x40U);
        r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_REGULATOR_EN_CNT,         0x07U);
        r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_RX_CAL_ALL_DLY,           0x09U);
        r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_RDDATA_EN_TSEL_DLY,       0x0BU);
        r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_RDDATA_EN_OE_DLY,         0x0EU);
        r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_RPTR_UPDATE,              0x08U);
        r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_WRLVL_RESP_WAIT_CNT,      0x2EU);
        r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_RDLVL_MAX_EDGE,           0x0164U);
        r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_RDDATA_EN_DLY,            0x0EU);
        r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_RDDQS_LATENCY_ADJUST,     0x05U);
        r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_GTLVL_LAT_ADJ_START,      0x04U);

        r_ddrtbl_setval(DDR_PHY_ADR_V_REGSET, PHY_ADR_MEAS_DLY_STEP_ENABLE, 0x00U);
        r_ddrtbl_setval(DDR_PHY_ADR_V_REGSET, PHY_ADR_CALVL_DLY_STEP,       0x02U);

        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TCKCKEL_F2,                0x03U);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDELAY_RDWR_2_BUS_IDLE_F2, 0x64U);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WCK_ACTIVE_WR_F2,          0x0BU);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WCK_ACTIVE_RD_F2,          0x12U);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TREF_F2,                   0x00081CU);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDFI_WRLVL_WW_F2,          0x002DU);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_RDLAT_ADJ_F2,              0x002BU);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDFI_CALVL_CC_F2,          0x0046U);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDFI_CALVL_CAPTURE_F2,     0x0020U);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TVRCG_ENABLE_F2,           0x0087U);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TVRCG_DISABLE_F2,          0x0037U);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TXP_F2,                    0x07U);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TMRWCKEL_F2,               0x0AU);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TCKEHDQS_F2,               0x14U);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TFC_F2,                    0x0086U);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDFI_WDQLVL_WR_F2,         0x0015U);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDFI_WDQLVL_RW_F2,         0x0013U);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WDQLVL_RDLAT_ADJ_F2,       0x002BU);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TWTR_S_F2,                 0x07U);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TWTR_L_F2,                 0x07U);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TWTR_F2,                   0x07U);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TWR_F2,                    0x13U);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TRAS_MAX_F2,               0x83A0U);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDFI_CTRLUPD_MAX_F2,       0x001038U);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDFI_CTRLUPD_INTERVAL_F2,  0x0000A230U);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TXSR_F2,                   0x00CFU);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TINIT_F2,                  0x01A0ABU);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TINIT1_F2,                 0x01A0ABU);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TINIT3_F2,                 0x1046ABU);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TINIT4_F2,                 0x00001BU);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TINIT5_F2,                 0x00042BU);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TXSNR_F2,                  0x00CFU);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_ZQRESET_F2,                0x001BU);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TCBTRTW_F2,                0x06U);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_16_F2,            0x000086U);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_17_F2,            0x000002U);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_18_F2,            0x000007U);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_19_F2,            0x000002U);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_20_F2,            0x000002U);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_21_F2,            0x00042BU);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_22_F2,            0x000002U);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_23_F2,            0x000013U);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_24_F2,            0x000037U);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_25_F2,            0x000087U);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_26_F2,            0x000008U);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_27_F2,            0x000000U);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_31_F2,            0x000087U);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WP_GAP_0_F2,               0x001CU);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_RP_GAP_0_F2,               0x0004U);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WR_GAP_S_0_F2,             0x000CU);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WR_GAP_L_0_F2,             0x000FU);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_RW_GAP_0_F2,               0x0009U);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WP_GAP_1_F2,               0x001CU);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_RP_GAP_1_F2,               0x0004U);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WR_GAP_S_1_F2,             0x000CU);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WR_GAP_L_1_F2,             0x000FU);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_RW_GAP_1_F2,               0x0009U);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WP_GAP_2_F2,               0x001CU);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_RP_GAP_2_F2,               0x0004U);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WR_GAP_S_2_F2,             0x000CU);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WR_GAP_L_2_F2,             0x000FU);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_RW_GAP_2_F2,               0x0009U);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WP_GAP_3_F2,               0x001CU);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_RP_GAP_3_F2,               0x0004U);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WR_GAP_S_3_F2,             0x000CU);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WR_GAP_L_3_F2,             0x000FU);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_RW_GAP_3_F2,               0x0009U);
    }
    else if (ddr_mbps < (4801U * ddr_mbpsdiv))
    {
        /* 4268 - 4800 */
        r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_LP4_BOOT_RX_PCLK_CLK_SEL, 0x00U);
        r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_WRLVL_PER_START,          0x40U);
        r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_REGULATOR_EN_CNT,         0x08U);
        r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_RX_CAL_ALL_DLY,           0x0AU);
        r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_RDDATA_EN_TSEL_DLY,       0x0DU);
        r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_RDDATA_EN_OE_DLY,         0x10U);
        r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_RPTR_UPDATE,              0x08U);
        r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_WRLVL_RESP_WAIT_CNT,      0x31U);
        r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_RDLVL_MAX_EDGE,           0x017FU);
        r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_RDDATA_EN_DLY,            0x10U);
        r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_RDDQS_LATENCY_ADJUST,     0x05U);
        r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_GTLVL_LAT_ADJ_START,      0x05U);

        r_ddrtbl_setval(DDR_PHY_ADR_V_REGSET, PHY_ADR_MEAS_DLY_STEP_ENABLE, 0x00U);
        r_ddrtbl_setval(DDR_PHY_ADR_V_REGSET, PHY_ADR_CALVL_DLY_STEP,       0x02U);

        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TCKCKEL_F2,                0x03U);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDELAY_RDWR_2_BUS_IDLE_F2, 0x68U);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WCK_ACTIVE_WR_F2,          0x0CU);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WCK_ACTIVE_RD_F2,          0x13U);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TREF_F2,                   0x000920U);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDFI_WRLVL_WW_F2,          0x002EU);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_RDLAT_ADJ_F2,              0x002DU);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDFI_CALVL_CC_F2,          0x0047U);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDFI_CALVL_CAPTURE_F2,     0x0021U);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TVRCG_ENABLE_F2,           0x0097U);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TVRCG_DISABLE_F2,          0x003DU);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TXP_F2,                    0x08U);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TMRWCKEL_F2,               0x0AU);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TCKEHDQS_F2,               0x14U);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TFC_F2,                    0x0096U);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDFI_WDQLVL_WR_F2,         0x0017U);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDFI_WDQLVL_RW_F2,         0x0014U);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WDQLVL_RDLAT_ADJ_F2,       0x002DU);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TWTR_S_F2,                 0x08U);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TWTR_L_F2,                 0x08U);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TWTR_F2,                   0x08U);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TWR_F2,                    0x15U);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TRAS_MAX_F2,               0x940BU);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDFI_CTRLUPD_MAX_F2,       0x001240U);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDFI_CTRLUPD_INTERVAL_F2,  0x0000B680U);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TXSR_F2,                   0x00E9U);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TINIT_F2,                  0x01D4A9U);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TINIT1_F2,                 0x01D4A9U);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TINIT3_F2,                 0x124E91U);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TINIT4_F2,                 0x00001EU);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TINIT5_F2,                 0x0004B0U);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TXSNR_F2,                  0x00E9U);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_ZQRESET_F2,                0x001EU);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TCBTRTW_F2,                0x06U);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_16_F2,            0x000096U);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_17_F2,            0x000002U);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_18_F2,            0x000008U);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_19_F2,            0x000002U);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_20_F2,            0x000002U);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_21_F2,            0x0004B0U);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_22_F2,            0x000002U);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_23_F2,            0x000015U);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_24_F2,            0x00003DU);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_25_F2,            0x000097U);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_26_F2,            0x00000AU);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_27_F2,            0x000001U);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_31_F2,            0x000097U);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WP_GAP_0_F2,               0x001FU);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_RP_GAP_0_F2,               0x0005U);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WR_GAP_S_0_F2,             0x000DU);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WR_GAP_L_0_F2,             0x0011U);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_RW_GAP_0_F2,               0x0009U);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WP_GAP_1_F2,               0x001FU);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_RP_GAP_1_F2,               0x0005U);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WR_GAP_S_1_F2,             0x000DU);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WR_GAP_L_1_F2,             0x0011U);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_RW_GAP_1_F2,               0x0009U);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WP_GAP_2_F2,               0x001FU);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_RP_GAP_2_F2,               0x0005U);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WR_GAP_S_2_F2,             0x000DU);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WR_GAP_L_2_F2,             0x0011U);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_RW_GAP_2_F2,               0x0009U);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WP_GAP_3_F2,               0x001FU);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_RP_GAP_3_F2,               0x0005U);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WR_GAP_S_3_F2,             0x000DU);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WR_GAP_L_3_F2,             0x0011U);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_RW_GAP_3_F2,               0x0009U);
    }
    else if (ddr_mbps < (5501U * ddr_mbpsdiv))
    {
        /* 4801 - 5500 */
        r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_LP4_BOOT_RX_PCLK_CLK_SEL, 0x00U);
        r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_REGULATOR_EN_CNT,         0x09U);
        r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_RX_CAL_ALL_DLY,           0x0CU);
        r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_RDDATA_EN_TSEL_DLY,       0x10U);
        r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_RDDATA_EN_OE_DLY,         0x13U);
        r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_WRLVL_RESP_WAIT_CNT,      0x37U);
        r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_RDLVL_MAX_EDGE,           0x01A3U);
        r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_RDDATA_EN_DLY,            0x13U);
        r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_RDDQS_LATENCY_ADJUST,     0x06U);
        r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_GTLVL_LAT_ADJ_START,      0x06U);

        r_ddrtbl_setval(DDR_PHY_ADR_V_REGSET, PHY_ADR_MEAS_DLY_STEP_ENABLE, 0x00U);
        r_ddrtbl_setval(DDR_PHY_ADR_V_REGSET, PHY_ADR_CALVL_DLY_STEP,       0x02U);

        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDELAY_RDWR_2_BUS_IDLE_F2, 0x71U);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WCK_ACTIVE_WR_F2,          0x0DU);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WCK_ACTIVE_RD_F2,          0x15U);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TREF_F2,                   0x000A79U);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDFI_WRLVL_WW_F2,          0x0030U);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_RDLAT_ADJ_F2,              0x0032U);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDFI_CALVL_CC_F2,          0x0049U);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDFI_CALVL_CAPTURE_F2,     0x0023U);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TVRCG_ENABLE_F2,           0x00AEU);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TVRCG_DISABLE_F2,          0x0046U);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TMRWCKEL_F2,               0x0BU);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TCKEHDQS_F2,               0x15U);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TFC_F2,                    0x00ADU);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDFI_WDQLVL_WR_F2,         0x0019U);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDFI_WDQLVL_RW_F2,         0x0016U);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WDQLVL_RDLAT_ADJ_F2,       0x0032U);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TWTR_S_F2,                 0x09U);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TWTR_L_F2,                 0x09U);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TWTR_F2,                   0x09U);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TWR_F2,                    0x18U);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TRAS_MAX_F2,               0xA9D9U);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDFI_CTRLUPD_MAX_F2,       0x0014F2U);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDFI_CTRLUPD_INTERVAL_F2,  0x0000D174U);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TXSR_F2,                   0x010CU);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TINIT_F2,                  0x0219AFU);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TINIT1_F2,                 0x0219AFU);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TINIT3_F2,                 0x1500CFU);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TINIT4_F2,                 0x000023U);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TINIT5_F2,                 0x000561U);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TXSNR_F2,                  0x010BU);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_ZQRESET_F2,                0x0023U);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TCBTRTW_F2,                0x07U);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_16_F2,            0x0000ADU);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_21_F2,            0x000561U);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_23_F2,            0x000019U);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_24_F2,            0x000046U);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_25_F2,            0x0000AEU);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_26_F2,            0x00000CU);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_27_F2,            0x000003U);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_31_F2,            0x0000AEU);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WP_GAP_0_F2,               0x0023U);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WR_GAP_S_0_F2,             0x000FU);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WR_GAP_L_0_F2,             0x0013U);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_RW_GAP_0_F2,               0x000AU);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WP_GAP_1_F2,               0x0023U);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WR_GAP_S_1_F2,             0x000FU);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WR_GAP_L_1_F2,             0x0013U);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_RW_GAP_1_F2,               0x000AU);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WP_GAP_2_F2,               0x0023U);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WR_GAP_S_2_F2,             0x000FU);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WR_GAP_L_2_F2,             0x0013U);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_RW_GAP_2_F2,               0x000AU);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WP_GAP_3_F2,               0x0023U);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WR_GAP_S_3_F2,             0x000FU);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WR_GAP_L_3_F2,             0x0013U);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_RW_GAP_3_F2,               0x000AU);
    }
    else if (ddr_mbps < (6001U * ddr_mbpsdiv))
    {
        /* 5501 - 6000 */
        r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_LP4_BOOT_RX_PCLK_CLK_SEL, 0x00U);
        r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_RDDATA_EN_TSEL_DLY,       0x12U);
        r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_RDDATA_EN_OE_DLY,         0x15U);
        r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_WRLVL_RESP_WAIT_CNT,      0x3AU);
        r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_RDLVL_MAX_EDGE,           0x01BDU);
        r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_RDDATA_EN_DLY,            0x15U);
        r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_GTLVL_LAT_ADJ_START,      0x06U);

        r_ddrtbl_setval(DDR_PHY_ADR_V_REGSET, PHY_ADR_MEAS_DLY_STEP_ENABLE, 0x00U);
        r_ddrtbl_setval(DDR_PHY_ADR_V_REGSET, PHY_ADR_CALVL_DLY_STEP,       0x02U);

        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDELAY_RDWR_2_BUS_IDLE_F2, 0x75U);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WCK_ACTIVE_RD_F2,          0x16U);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TREF_F2,                   0x000B6BU);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDFI_WRLVL_WW_F2,          0x0031U);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_RDLAT_ADJ_F2,              0x0034U);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TVRCG_ENABLE_F2,           0x00BDU);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TVRCG_DISABLE_F2,          0x004DU);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TMRWCKEL_F2,               0x0CU);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TFC_F2,                    0x00BCU);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDFI_WDQLVL_RW_F2,         0x0017U);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WDQLVL_RDLAT_ADJ_F2,       0x0034U);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TWR_F2,                    0x1AU);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TRAS_MAX_F2,               0xB924U);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDFI_CTRLUPD_MAX_F2,       0x0016D6U);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDFI_CTRLUPD_INTERVAL_F2,  0x0000E45CU);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TXSR_F2,                   0x0124U);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TINIT_F2,                  0x024A16U);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TINIT1_F2,                 0x024A16U);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TINIT3_F2,                 0x16E4D8U);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TINIT4_F2,                 0x000026U);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TINIT5_F2,                 0x0005DDU);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TXSNR_F2,                  0x0123U);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_ZQRESET_F2,                0x0026U);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_16_F2,            0x0000BCU);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_21_F2,            0x0005DDU);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_23_F2,            0x00001BU);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_24_F2,            0x00004DU);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_25_F2,            0x0000BDU);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_27_F2,            0x000004U);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_31_F2,            0x0000BDU);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WP_GAP_0_F2,               0x0026U);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_RW_GAP_0_F2,               0x000AU);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WP_GAP_1_F2,               0x0026U);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_RW_GAP_1_F2,               0x000AU);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WP_GAP_2_F2,               0x0026U);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_RW_GAP_2_F2,               0x000AU);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WP_GAP_3_F2,               0x0026U);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_RW_GAP_3_F2,               0x000AU);
    }
    else
    {
        ; /* Nothing */
    } /* (ddr_mbps < (3201U * ddr_mbpsdiv)) */

#if (RCAR_MEDIUM_FREQUENCY_TRAINING_MODE == 1U)
    if (med_freq_en == 0x01U)
    {
        if (ddr_mbps < (1601U * ddr_mbpsdiv * ddr_medium_div))
        {
            /* 1068 - 1600 */
            /* default */
            ;
        }
        else if (ddr_mbps < (2134U * ddr_mbpsdiv * ddr_medium_div))
        {
            /* 1601 - 2133 */
            r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDELAY_RDWR_2_BUS_IDLE_F1, 0x4AU);
            r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WRLAT_F1,                  0x04U);
            r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TWCKENL_RD_ADJ_F1,         0x0CU);
            r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TWCKPRE_STATIC_F1,         0x08U);
            r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WCK_ACTIVE_WR_F1,          0x07U);
            r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WCK_ACTIVE_RD_F1,          0x0AU);
            r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_CASLAT_F1,                 0x07U);
            r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TRFC_F1,                   0x0066U);
            r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TREF_F1,                   0x00040AU);
            r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDFI_WRLVL_WW_F1,          0x0028U);
            r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_RDLAT_ADJ_F1,              0x001AU);
            r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WRLAT_ADJ_F1,              0x12U);
            r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDFI_CALVL_CC_F1,          0x0041U);
            r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDFI_CALVL_CAPTURE_F1,     0x001BU);
            r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TCAENT_F1,                 0x0043U);
            r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TVREF_LONG_F1,             0x0044U);
            r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TVRCG_ENABLE_F1,           0x0044U);
            r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TVRCG_DISABLE_F1,          0x001CU);
            r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TCKEHDQS_F1,               0x11U);
            r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TFC_F1,                    0x0043U);
            r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDFI_WDQLVL_WR_F1,         0x0010U);
            r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDFI_WDQLVL_RW_F1,         0x000DU);
            r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WDQLVL_RDLAT_ADJ_F1,       0x001AU);
            r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WDQLVL_TWCKENL_RD_ADJ_F1,  0x0CU);
            r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TRP_F1,                    0x06U);
            r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TRCD_F1,                   0x05U);
            r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TWR_F1,                    0x0AU);
            r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TRAS_MAX_F1,               0x41D0U);
            r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TRAS_MIN_F1,               0x000CU);
            r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TSR_F1,                    0x04U);
            r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDFI_CTRLUPD_MAX_F1,       0x000814U);
            r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDFI_CTRLUPD_INTERVAL_F1,  0x000050C8U);
            r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TXSR_F1,                   0x0068U);
            r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TINIT_F1,                  0x00D056U);
            r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TINIT1_F1,                 0x00D056U);
            r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TINIT3_F1,                 0x082356U);
            r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TINIT4_F1,                 0x00000EU);
            r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TINIT5_F1,                 0x000216U);
            r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TXSNR_F1,                  0x0068U);
            r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_ZQRESET_F1,                0x000EU);
            r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TZQCAL_F1,                 0x0190U);
            r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TZQLAT_F1,                 0x08U);
            r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDQ72DQ_F1,                0x0022U);
            r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_MC_TRFC_F1,                0x0066U);
            r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_16_F1,            0x000043U);
            r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_21_F1,            0x000216U);
            r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_23_F1,            0x00000AU);
            r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_24_F1,            0x00001CU);
            r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_25_F1,            0x000044U);
            r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_26_F1,            0x000003U);
            r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_31_F1,            0x000044U);
            r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WP_GAP_0_F1,               0x0011U);
            r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WR_GAP_S_0_F1,             0x000AU);
            r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WR_GAP_L_0_F1,             0x000AU);
            r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_RW_GAP_0_F1,               0x0005U);
            r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WP_GAP_1_F1,               0x0011U);
            r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WR_GAP_S_1_F1,             0x000AU);
            r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WR_GAP_L_1_F1,             0x000AU);
            r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_RW_GAP_1_F1,               0x0005U);
            r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WP_GAP_2_F1,               0x0011U);
            r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WR_GAP_S_2_F1,             0x000AU);
            r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WR_GAP_L_2_F1,             0x000AU);
            r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_RW_GAP_2_F1,               0x0005U);
            r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WP_GAP_3_F1,               0x0011U);
            r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WR_GAP_S_3_F1,             0x000AU);
            r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WR_GAP_L_3_F1,             0x000AU);
            r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_RW_GAP_3_F1,               0x0005U);
            r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_DARRAY3_0_CS0_F1,          0x30U);
            r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_DARRAY3_1_CS0_F1,          0x33U);
            r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_DARRAY3_0_CS1_F1,          0x30U);
            r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_DARRAY3_1_CS1_F1,          0x33U);
        }
        else
        {
            /* 2134 - 2750 */
            r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDELAY_RDWR_2_BUS_IDLE_F1, 0x4FU);
            r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WRLAT_F1,                  0x04U);
            r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TWCKENL_RD_ADJ_F1,         0x0CU);
            r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TWCKPRE_STATIC_F1,         0x08U);
            r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TWCKPRE_TOGGLE_RD_F1,      0x14U);
            r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WCK_ACTIVE_WR_F1,          0x07U);
            r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WCK_ACTIVE_RD_F1,          0x0BU);
            r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_CASLAT_F1,                 0x08U);
            r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TRFC_F1,                   0x0083U);
            r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TREF_F1,                   0x000538U);
            r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDFI_WRLVL_WW_F1,          0x002AU);
            r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_RDLAT_ADJ_F1,              0x001CU);
            r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WRLAT_ADJ_F1,              0x12U);
            r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDFI_CALVL_CC_F1,          0x0042U);
            r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDFI_CALVL_CAPTURE_F1,     0x001CU);
            r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TCAENT_F1,                 0x0056U);
            r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TVREF_LONG_F1,             0x0057U);
            r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TVRCG_ENABLE_F1,           0x0057U);
            r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TVRCG_DISABLE_F1,          0x0024U);
            r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TCKEHDQS_F1,               0x12U);
            r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TFC_F1,                    0x0056U);
            r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDFI_WDQLVL_WR_F1,         0x0011U);
            r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDFI_WDQLVL_RW_F1,         0x000EU);
            r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WDQLVL_RDLAT_ADJ_F1,       0x001CU);
            r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WDQLVL_WRLAT_ADJ_F1,       0x0012U);
            r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WDQLVL_TWCKENL_RD_ADJ_F1,  0x0CU);
            r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TRTP_F1,                   0x01U);
            r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TRP_F1,                    0x08U);
            r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TRCD_F1,                   0x07U);
            r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TWTR_S_F1,                 0x05U);
            r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TWTR_L_F1,                 0x05U);
            r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TWTR_F1,                   0x05U);
            r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TWR_F1,                    0x0CU);
            r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TRAS_MAX_F1,               0x54E5U);
            r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TRAS_MIN_F1,               0x000FU);
            r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TSR_F1,                    0x06U);
            r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDFI_CTRLUPD_MAX_F1,       0x000A70U);
            r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDFI_CTRLUPD_INTERVAL_F1,  0x00006860U);
            r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TXSR_F1,                   0x0086U);
            r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TINIT_F1,                  0x010CC0U);
            r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TINIT1_F1,                 0x010CC0U);
            r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TINIT3_F1,                 0x0A7F7BU);
            r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TINIT4_F1,                 0x000012U);
            r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TINIT5_F1,                 0x0002B0U);
            r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TXSNR_F1,                  0x0086U);
            r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_ZQRESET_F1,                0x0012U);
            r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TZQCAL_F1,                 0x0204U);
            r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TZQLAT_F1,                 0x0BU);
            r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDQ72DQ_F1,                0x002BU);
            r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TCBTRTW_F1,                0x04U);
            r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_MC_TRFC_F1,                0x0083U);
            r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDFI_WCK_STOP_F1,          0x05U);
            r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_16_F1,            0x000056U);
            r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_17_F1,            0x000002U);
            r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_19_F1,            0x000002U);
            r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_20_F1,            0x000002U);
            r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_21_F1,            0x0002B0U);
            r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_22_F1,            0x000002U);
            r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_23_F1,            0x00000DU);
            r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_24_F1,            0x000024U);
            r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_25_F1,            0x000057U);
            r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_26_F1,            0x000004U);
            r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_31_F1,            0x000057U);
            r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WP_GAP_0_F1,               0x0013U);
            r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_RP_GAP_0_F1,               0x0003U);
            r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WR_GAP_S_0_F1,             0x000BU);
            r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WR_GAP_L_0_F1,             0x000BU);
            r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_RW_GAP_0_F1,               0x0006U);
            r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WP_GAP_1_F1,               0x0013U);
            r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_RP_GAP_1_F1,               0x0003U);
            r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WR_GAP_S_1_F1,             0x000BU);
            r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WR_GAP_L_1_F1,             0x000BU);
            r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_RW_GAP_1_F1,               0x0006U);
            r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WP_GAP_2_F1,               0x0013U);
            r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_RP_GAP_2_F1,               0x0003U);
            r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WR_GAP_S_2_F1,             0x000BU);
            r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WR_GAP_L_2_F1,             0x000BU);
            r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_RW_GAP_2_F1,               0x0006U);
            r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WP_GAP_3_F1,               0x0013U);
            r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_RP_GAP_3_F1,               0x0003U);
            r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WR_GAP_S_3_F1,             0x000BU);
            r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WR_GAP_L_3_F1,             0x000BU);
            r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_RW_GAP_3_F1,               0x0006U);
            r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_DARRAY3_0_CS0_F1,          0x40U);
            r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_DARRAY3_1_CS0_F1,          0x44U);
            r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_DARRAY3_0_CS1_F1,          0x40U);
            r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_DARRAY3_1_CS1_F1,          0x44U);
        } /* (ddr_mbps < (1601U * ddr_mbpsdiv * ddr_medium_div)) */
    } /* (med_freq_en == 0x01U) */
#endif /* (RCAR_MEDIUM_FREQUENCY_TRAINING_MODE == 1U) */

    tmp[0] = js1[js1_ind].MR1;
    tmp[1] = js1[js1_ind].MR2;

    for (cs = 0U; cs < CS_CNT; cs++)
    {
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_DARRAY3_0_CSx_Fx[cs][2], tmp[0]);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_DARRAY3_1_CSx_Fx[cs][2], tmp[1]);
    }

#ifdef DDR_BACKUPMODE
    if (ddrBackup == DRAM_BOOT_STATUS_WARM)
    {
        r_ddrtbl_setval(DDR_PHY_ADR_G_REGSET, PHY_SET_DFI_INPUT_RST_PAD, 0x01U);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_PWRUP_SREFRESH_EXIT,        0x01U);
    }
#endif /* DDR_BACKUPMODE */

    /***********************************************************************
     * Read Vref (SoC side) Training range
     ***********************************************************************/
    dataL = (uint32_t)(Boardcnf->bdcfg_vref_r);
    if (dataL != 0x0U)
    {
        r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_VREF_INITIAL_START_POINT, dataL & 0x000000FFU);
        r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_VREF_INITIAL_STOP_POINT, (dataL & 0x0000FF00U) >> 8);
        r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_VREF_INITIAL_STEPSIZE,   (dataL & 0x00FF0000U) >> 16);
    }

    /***********************************************************************
     * Write Vref (MR14, MR15) Training range
     ***********************************************************************/
    dataL = (uint32_t)(Boardcnf->bdcfg_vref_w);
    if (dataL != 0x0U)
    {
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WDQLVL_VREF_INITIAL_START_POINT_F0, dataL & 0x00FFU);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WDQLVL_VREF_INITIAL_START_POINT_F1, dataL & 0x00FFU);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WDQLVL_VREF_INITIAL_START_POINT_F2, dataL & 0x00FFU);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WDQLVL_VREF_INITIAL_STOP_POINT_F0, (dataL & 0xFF00U) >> 8);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WDQLVL_VREF_INITIAL_STOP_POINT_F1, (dataL & 0xFF00U) >> 8);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WDQLVL_VREF_INITIAL_STOP_POINT_F2, (dataL & 0xFF00U) >> 8);
    }

    /***********************************************************************
     * CA Vref (MR12) Training range
     ***********************************************************************/
    dataL = (uint32_t)(Boardcnf->bdcfg_vref_ca);
    if (dataL != 0x0U)
    {
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_CALVL_VREF_INITIAL_START_POINT_F2, dataL & 0x00FFU);
        r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_CALVL_VREF_INITIAL_STOP_POINT_F2, (dataL & 0xFF00U) >> 8);
    }

    /***********************************************************************
     * Low Freq setting
     ***********************************************************************/
    if (ddr_mbps < (8U * 640U * ddr_mbpsdiv))
    {
        /* CAL_CLK(10-20MHz) */
        r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_DATA_DC_CAL_CLK_SEL, 0x05U);
        r_ddrtbl_setval(DDR_PHY_ADR_V_REGSET, PHY_CLK_DC_CAL_CLK_SEL,  0x04U);
        r_ddrtbl_setval(DDR_PHY_ADR_G_REGSET, PHY_CAL_CLK_SELECT_0,    0x05U);
    }

    if (ddr_mbps < (8U * 572U * ddr_mbpsdiv))
    {
        /* CAL_CLK(10-20MHz) */
        r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_RX_PCLK_CLK_SEL,         0x03U);
        r_ddrtbl_setval(DDR_PHY_ADR_G_REGSET, PHY_PAD_ACS_RX_PCLK_CLK_SEL, 0x02U);
    }

    if (ddr_mbps < (8U * 401U * ddr_mbpsdiv))
    {
        r_ddrtbl_setval(DDR_PHY_ADR_G_REGSET, PHY_PLL_CTRL,    0x1542U);
        r_ddrtbl_setval(DDR_PHY_ADR_G_REGSET, PHY_PLL_CTRL_8X, 0x3342U);
    }

    /***********************************************************************
     * SET DATA SLICE TABLE
     ***********************************************************************/
    for (slice = 0U; slice < SLICE_CNT; slice++)
    {
        adr = DDR_PHY_SLICE_REGSET_OFS + (DDR_PHY_SLICE_REGSET_SIZE * slice);
        for (i = 0U; i < DDR_PHY_SLICE_REGSET_NUM; i++)
        {
            r_reg_ddrphy_write_a(adr + i, DDR_PHY_SLICE_REGSET[i]);
        }
    }

    /***********************************************************************
     * SET ADR SLICE TABLE
     ***********************************************************************/
    adr = DDR_PHY_ADR_V_REGSET_OFS;
    for (i = 0U; i < DDR_PHY_ADR_V_REGSET_NUM; i++)
    {
        r_reg_ddrphy_write_a(adr + i, DDR_PHY_ADR_V_REGSET[i]);
    }

    /***********************************************************************
     * SET ADRCTRL SLICE TABLE
     ***********************************************************************/
    adr = DDR_PHY_ADR_G_REGSET_OFS;
    for (i = 0U; i < DDR_PHY_ADR_G_REGSET_NUM; i++)
    {
        r_reg_ddrphy_write_a(adr + i, DDR_PHY_ADR_G_REGSET[i]);
    }

    /***********************************************************************
     * SET PI REGISTERS
     ***********************************************************************/
    adr = DDR_PI_REGSET_OFS;
    for (i = 0U; i < DDR_PI_REGSET_NUM; i++)
    {
        r_reg_ddrphy_write_a(adr + i, DDR_PI_REGSET[i]);
    }

#if (RCAR_MEDIUM_FREQUENCY_TRAINING_MODE == 1U)
    /***********************************************************************
    * SET MEDIUM FREQ SETTING
    ************************************************************************/
    if (med_freq_en == 0x01U)
    {
        r_ddr_setval_ach(PHY_FREQ_SEL_MULTICAST_EN, 0x00U);
        r_ddr_setval_ach(PHY_FREQ_SEL_INDEX, 0x00U);

        dataL = rddq_delay * ddr_mbps * 256U / (ddr_mbpsdiv * ddr_medium_div * 2U * 1000000U);
        r_ddr_setval_ach_as(PHY_RDDQ0_SLAVE_DELAY, dataL);
        r_ddr_setval_ach_as(PHY_RDDQ1_SLAVE_DELAY, dataL);
        r_ddr_setval_ach_as(PHY_RDDQ2_SLAVE_DELAY, dataL);
        r_ddr_setval_ach_as(PHY_RDDQ3_SLAVE_DELAY, dataL);
        r_ddr_setval_ach_as(PHY_RDDQ4_SLAVE_DELAY, dataL);
        r_ddr_setval_ach_as(PHY_RDDQ5_SLAVE_DELAY, dataL);
        r_ddr_setval_ach_as(PHY_RDDQ6_SLAVE_DELAY, dataL);
        r_ddr_setval_ach_as(PHY_RDDQ7_SLAVE_DELAY, dataL);
        r_ddr_setval_ach_as(PHY_RDDM_SLAVE_DELAY,  dataL);

        if (ddr_mbps < (1601U * ddr_mbpsdiv * ddr_medium_div))
        {
            /* 1068 - 1600 */
            r_ddr_setval_ach_as(PHY_REGULATOR_EN_CNT,              0x03U);
            r_ddr_setval_ach_as(PHY_RX_CAL_ALL_DLY,                0x04U);
            r_ddr_setval_ach_as(PHY_RX_PCLK_CLK_SEL,               0x02U);
            r_ddr_setval_ach_as(PHY_RDDATA_EN_TSEL_DLY,            0x02U);
            r_ddr_setval_ach_as(PHY_RDDATA_EN_OE_DLY,              0x05U);
            r_ddr_setval_ach_as(PHY_RPTR_UPDATE,                   0x06U);
            r_ddr_setval_ach_as(PHY_WRLVL_RESP_WAIT_CNT,           0x19U);
            r_ddr_setval_ach_as(PHY_RDLVL_MAX_EDGE,                0x00DBU);
            r_ddr_setval_ach_as(PHY_RDDATA_EN_DLY,                 0x05U);
            r_ddr_setval_ach_as(PHY_RDDQS_LATENCY_ADJUST,          0x02U);
            r_ddr_setval_ach_as(PHY_GTLVL_LAT_ADJ_START,           0x01U);
            r_ddr_setval_ach_as(PHY_DATA_DC_WDQLVL_ENABLE,         0x00U);
            r_ddr_setval_ach(PHY_ADR_MEAS_DLY_STEP_ENABLE,         0x00U);
            r_ddr_setval_ach(PHY_ADR_CALVL_DLY_STEP,               0x02U);
            r_ddr_setval_ach(PHY_ADRCTL_MASTER_DELAY_HALF_MEASURE, 0x32U);
            r_ddr_setval_ach(PHY_PAD_ACS_RX_PCLK_CLK_SEL,          0x01U);
            r_ddr_setval_ach(PHY_PLL_CTRL,                         0x1742U);
            r_ddr_setval_ach(PHY_PLL_CTRL_8X,                      0x3542U);
        }
        else if (ddr_mbps < (2134U * ddr_mbpsdiv * ddr_medium_div))
        {
            /* 1601 - 2133 */
            r_ddr_setval_ach_as(PHY_REGULATOR_EN_CNT,              0x04U);
            r_ddr_setval_ach_as(PHY_RX_CAL_ALL_DLY,                0x05U);
            r_ddr_setval_ach_as(PHY_RX_PCLK_CLK_SEL,               0x02U);
            r_ddr_setval_ach_as(PHY_RDDATA_EN_TSEL_DLY,            0x04U);
            r_ddr_setval_ach_as(PHY_RDDATA_EN_OE_DLY,              0x07U);
            r_ddr_setval_ach_as(PHY_RPTR_UPDATE,                   0x07U);
            r_ddr_setval_ach_as(PHY_WRLVL_RESP_WAIT_CNT,           0x1EU);
            r_ddr_setval_ach_as(PHY_RDLVL_MAX_EDGE,                0x00F7U);
            r_ddr_setval_ach_as(PHY_RDDATA_EN_DLY,                 0x07U);
            r_ddr_setval_ach_as(PHY_RDDQS_LATENCY_ADJUST,          0x02U);
            r_ddr_setval_ach_as(PHY_GTLVL_LAT_ADJ_START,           0x02U);
            r_ddr_setval_ach_as(PHY_DATA_DC_WDQLVL_ENABLE,         0x00U);
            r_ddr_setval_ach(PHY_ADR_MEAS_DLY_STEP_ENABLE,         0x00U);
            r_ddr_setval_ach(PHY_ADR_CALVL_DLY_STEP,               0x02U);
            r_ddr_setval_ach(PHY_ADRCTL_MASTER_DELAY_HALF_MEASURE, 0x32U);
            r_ddr_setval_ach(PHY_PAD_ACS_RX_PCLK_CLK_SEL,          0x01U);
            r_ddr_setval_ach(PHY_PLL_CTRL,                         0x1542U);
            r_ddr_setval_ach(PHY_PLL_CTRL_8X,                      0x3342U);
        }
        else
        {
            /* 2134 - 2750 */
            r_ddr_setval_ach_as(PHY_REGULATOR_EN_CNT,              0x05U);
            r_ddr_setval_ach_as(PHY_RX_CAL_ALL_DLY,                0x06U);
            r_ddr_setval_ach_as(PHY_RX_PCLK_CLK_SEL,               0x03U);
            r_ddr_setval_ach_as(PHY_RDDATA_EN_TSEL_DLY,            0x06U);
            r_ddr_setval_ach_as(PHY_RDDATA_EN_OE_DLY,              0x09U);
            r_ddr_setval_ach_as(PHY_RPTR_UPDATE,                   0x07U);
            r_ddr_setval_ach_as(PHY_WRLVL_RESP_WAIT_CNT,           0x22U);
            r_ddr_setval_ach_as(PHY_RDLVL_MAX_EDGE,                0x0116U);
            r_ddr_setval_ach_as(PHY_RDDATA_EN_DLY,                 0x09U);
            r_ddr_setval_ach_as(PHY_RDDQS_LATENCY_ADJUST,          0x03U);
            r_ddr_setval_ach_as(PHY_GTLVL_LAT_ADJ_START,           0x03U);
            r_ddr_setval_ach_as(PHY_DATA_DC_WDQLVL_ENABLE,         0x00U);
            r_ddr_setval_ach(PHY_ADR_MEAS_DLY_STEP_ENABLE,         0x00U);
            r_ddr_setval_ach(PHY_ADR_CALVL_DLY_STEP,               0x02U);
            r_ddr_setval_ach(PHY_ADRCTL_MASTER_DELAY_HALF_MEASURE, 0x32U);
            r_ddr_setval_ach(PHY_PAD_ACS_RX_PCLK_CLK_SEL,          0x02U);
            r_ddr_setval_ach(PHY_PLL_CTRL,                         0x1542U);
            r_ddr_setval_ach(PHY_PLL_CTRL_8X,                      0x3342U);
        } /* (ddr_mbps < (1601U * ddr_mbpsdiv * ddr_medium_div)) */

        if (ddr_mbps < (8U * 160U * ddr_mbpsdiv * ddr_medium_div))
        {
            /* CAL_CLK(10-20MHz) */
            r_ddr_setval_ach_as(PHY_DATA_DC_CAL_CLK_SEL, 0x03U);
            r_ddr_setval_ach(PHY_CLK_DC_CAL_CLK_SEL,     0x02U);
            r_ddr_setval_ach(PHY_CAL_CLK_SELECT_0,       0x03U);
        }
        else if (ddr_mbps < (8U * 320U * ddr_mbpsdiv * ddr_medium_div))
        {
            /* CAL_CLK(10-20MHz) */
            r_ddr_setval_ach_as(PHY_DATA_DC_CAL_CLK_SEL, 0x04U);
            r_ddr_setval_ach(PHY_CLK_DC_CAL_CLK_SEL,     0x03U);
            r_ddr_setval_ach(PHY_CAL_CLK_SELECT_0,       0x04U);
        }
        else
        {
            /* CAL_CLK(10-20MHz) */
            r_ddr_setval_ach_as(PHY_DATA_DC_CAL_CLK_SEL, 0x05U);
            r_ddr_setval_ach(PHY_CLK_DC_CAL_CLK_SEL,     0x04U);
            r_ddr_setval_ach(PHY_CAL_CLK_SELECT_0,       0x05U);
        } /* (ddr_mbps < (8U * 160U * ddr_mbpsdiv * ddr_medium_div)) */

        r_ddr_setval_ach(PHY_FREQ_SEL_MULTICAST_EN, 0x01U);
    } /* (med_freq_en == 0x01U) */
#endif /* (RCAR_MEDIUM_FREQUENCY_TRAINING_MODE == 1U) */
}

/*******************************************************************************
 *    CONFIGURE DDR REGISTERS
 ******************************************************************************/
static void r_ddr_config(void)
{
    uint32_t ch, slice;
    uint32_t dataL;
    uint8_t high_byte[SLICE_CNT];

    r_foreach_vch((ch))
    {
    /***********************************************************************
     * BOARD SETTINGS (DQ, DM, VREF_DRIVING)
     ***********************************************************************/
        for (slice = 0U; slice < SLICE_CNT; slice++)
        {
            high_byte[slice] = ((uint32_t)(Boardcnf->ch[ch].bdcfg_dqs_swap) >> (4U * slice)) % 2U;
            r_ddr_setval_s(ch, slice, PHY_DQ_DM_SWIZZLE0, Boardcnf->ch[ch].bdcfg_dq_swap[slice]);
            r_ddr_setval_s(ch, slice, PHY_DQ_DM_SWIZZLE1, (uint32_t)(Boardcnf->ch[ch].bdcfg_dm_swap[slice]));
            if (high_byte[slice] != 0U)
            {
                /* HIGHER 16 BYTE */
                r_ddr_setval_s(ch, slice, PHY_CALVL_VREF_DRIVING_SLICE, 0x00U);
            }
            else
            {
                /* LOWER 16 BYTE */
                r_ddr_setval_s(ch, slice, PHY_CALVL_VREF_DRIVING_SLICE, 0x01U);
            }
        }
        dataL = (0x000000FFU & (uint32_t)(Boardcnf->ch[ch].bdcfg_dqs_swap));
        r_ddr_setval(ch, PHY_DATA_BYTE_ORDER_SEL, (0x76543200U | dataL));

    /***********************************************************************
     * BOARD SETTINGS (CA, ADDR_MUX)
     ***********************************************************************/
        dataL = (0x0FFFFFFFU & (uint32_t)(Boardcnf->ch[ch].bdcfg_ca_swap));

        /* --- ADDR_MUX --- */
        r_ddr_setval(ch, PI_ADDRESS_MUX_0, (0x000000FU &  dataL));
        r_ddr_setval(ch, PI_ADDRESS_MUX_1, (0x000000FU & (dataL >> 4)));
        r_ddr_setval(ch, PI_ADDRESS_MUX_2, (0x000000FU & (dataL >> 8)));
        r_ddr_setval(ch, PI_ADDRESS_MUX_3, (0x000000FU & (dataL >> 12)));
        r_ddr_setval(ch, PI_ADDRESS_MUX_4, (0x000000FU & (dataL >> 16)));
        r_ddr_setval(ch, PI_ADDRESS_MUX_5, (0x000000FU & (dataL >> 20)));
        r_ddr_setval(ch, PI_ADDRESS_MUX_6, (0x000000FU & (dataL >> 24)));

        /* --- ADR_CALVL_SWIZZLE --- */
        r_ddr_setval(ch, PHY_ADR_CALVL_SWIZZLE0, dataL);

    /***********************************************************************
     * BOARD SETTINGS (CS)
     ***********************************************************************/
        /* --- CKE_MUX --- */
        /* SoC CKE -> DRAM CS */
        dataL = (uint32_t)(Boardcnf->ch[ch].bdcfg_cs_swap);
        r_ddr_setval(ch, PI_CKE_MUX_0, (0x0FU & dataL));
        r_ddr_setval(ch, PI_CKE_MUX_1, (0x0FU & (dataL >> 4)));
        r_ddr_setval(ch, PHY_CS_ACS_ALLOCATION_BIT2_2, ((0x0FU & (dataL)) + 1U));
        r_ddr_setval(ch, PHY_CS_ACS_ALLOCATION_BIT3_2, ((0x0FU & (dataL >> 4)) + 1U));

    /***********************************************************************
     * mask CS_MAP if RANK1 is not found
     ***********************************************************************/
        if ((ch_have_this_cs[1] & (1U << ch)) == 0x0U)
        {
            r_ddr_setval(ch, PHY_ADR_CALVL_RANK_CTRL, 0x00U);
            for (slice = 0U; slice < SLICE_CNT; slice++)
            {
                r_ddr_setval_s(ch, slice, PHY_PER_CS_TRAINING_EN, 0x00U);
            }
        }
    }

    r_foreach_vch((ch))
    {
        /* --- DATA_BYTE_SWAP --- */
        dataL = (uint32_t)(Boardcnf->ch[ch].bdcfg_dqs_swap);
        r_ddr_setval(ch, PI_DATA_BYTE_SWAP_EN,      0x01U);
        r_ddr_setval(ch, PI_DATA_BYTE_SWAP_SLICE0,  dataL & 0x0FU);
        r_ddr_setval(ch, PI_DATA_BYTE_SWAP_SLICE1, (dataL >> 4) & 0x0FU);

        if ((ch_have_this_cs[1] & (1U << ch)) == 0x0U)
        {
            r_ddr_setval(ch, PI_CS_MAP, 0x01U);
        }
    }
}

/*******************************************************************************
 *    DBSC register setting functions
 ******************************************************************************/
static void r_dbsc_regset_pre(void)
{
    uint32_t ch, cs;

    /***********************************************************************
     * PRIMARY SETTINGS
     ***********************************************************************/
    /* LPDDR5, BL=16, DFI interface */
    r_dbsc_write_32(DBSC_DBMEMKIND,  0x0000000CU);
    r_dbsc_write_32(DBSC_DBMEMKINDA, 0x0000000CU);
    r_dbsc_write_32(DBSC_DBBL,       0x00000002U);
    r_dbsc_write_32(DBSC_DBBLA,      0x00000002U);
    r_dbsc_write_32(DBSC_DBPHYCONF0, 0x00000001U);

    r_dbsc_write_32(DBSC_DBSYSCONF0, 0x00000001U);

    /* FREQRATIO=2 */
    r_dbsc_write_32(DBSC_DBSYSCONF1,  0x00020000U);
    r_dbsc_write_32(DBSC_DBSYSCONF1A, 0x00000000U);

    r_dbsc_write_32(DBSC_DBSYSCONF2,  0x00000001U);
    r_dbsc_write_32(DBSC_DBSYSCONF2A, 0x00000241U);

    r_foreach_ech((ch))
    {
        for (cs = 0U; cs < CS_CNT; cs++)
        {
            if (ddr_density[ch][cs] == 0xFFU)
            {
                mmio_write_32(DBSC_DBMEMCONF(ch, cs),  0x00U);
                mmio_write_32(DBSC_DBMEMCONFA(ch, cs), 0x00U);
            }
            else
            {
                mmio_write_32(DBSC_DBMEMCONF(ch, cs),  DBMEMCONF_REGD(ddr_density[ch][cs]));
                mmio_write_32(DBSC_DBMEMCONFA(ch, cs), DBMEMCONF_REGD(ddr_density[ch][cs]));
            }
        }
    }
}

static void r_dbsc_regset(void)
{
    uint32_t tmp[4];

    /* DBTR0.cl : RL */
    r_dbsc_write_32(DBSC_DBTR(0U), RL);

    /* DBTR1.cwl : WL */
    r_dbsc_write_32(DBSC_DBTR(1U), WL);

    /* DBTR2.al = 0 */
    r_dbsc_write_32(DBSC_DBTR(2U), 0x00000000U);

    /* DBTR3.trcd : tRCD */
    r_dbsc_write_32(DBSC_DBTR(3U), js2[JS2_tRCD]);

    /* DBTR4.trpa,trp : tRPab,tRPpb */
    r_dbsc_write_32(DBSC_DBTR(4U), ((js2[JS2_tRPab] << 16) | js2[JS2_tRPpb]));

    /* DBTR5.trc : tRCpb */
    r_dbsc_write_32(DBSC_DBTR(5U), js2[JS2_tRCpb]);

    /* DBTR6.tras : tRAS */
    r_dbsc_write_32(DBSC_DBTR(6U), js2[JS2_tRAS]);

    /* DBTR7.trrd : tRRD */
    r_dbsc_write_32(DBSC_DBTR(7U), (((js2[JS2_tRRD] - 1U) << 16) | (js2[JS2_tRRD] - 1U)));

    /* DBTR8.tfaw : tFAW */
    r_dbsc_write_32(DBSC_DBTR(8U), (js2[JS2_tFAW] - 1U));

    /* DBTR9.trdpr : nRBTP */
    r_dbsc_write_32(DBSC_DBTR(9U), js1[js1_ind].nRBTP);

    /* DBTR10.twr : nWR */
    r_dbsc_write_32(DBSC_DBTR(10U), js1[js1_ind].nWR);

    /* DBTR11.trdwr : RL + BL/n_max + RU(tWCK2DQO(max)/tCK) + RD(tRPST/tCK) - ODTLon - RD(tODTon(min)/tCK) + 1 + feature */
    r_dbsc_write_32(DBSC_DBTR(11U), (RL + 4U + js2[JS2_tWCK2DQO_HF] + 0U - js1[js1_ind].ODTLon - (js2[JS2_tODTon_min] - 1U) + 1U + 0U));

    /* DBTR12.twrrd_s,twrrd : WL + BL/2 + tWTR_S,WL + BL + tWTR_L */
    r_dbsc_write_32(DBSC_DBTR(12U), (((WL + 2U + js2[JS2_tWTR_S]) << 16) | (WL + 4U + js2[JS2_tWTR_L])));

    /* DBTR13.trfcab : tRFCab */
    r_dbsc_write_32(DBSC_DBTR(13U), js2[JS2_tRFCab]);

    /* DBTR14.tcscal,tckehdll,tckeh : tCSCAL,tXP,tXP */
    r_dbsc_write_32(DBSC_DBTR(14U), ((js2[JS2_tCSCAL] << 24) | (js2[JS2_tXP] << 16) | js2[JS2_tXP]));

    /* DBTR15.tespd,tckesr,tckel : tESPD = 2,tSR,tSR */
    r_dbsc_write_32(DBSC_DBTR(15U), ((0x02U << 24) | (js2[JS2_tSR] << 16) | js2[JS2_tSR]));

    /* DBTR16 */
    /* wdql(tphy_wrlat + tphy_wrdata) */
    tmp[0] = (WL * 4U) - 1U + 5U;
    /* dqenltcy(tphy_wrlat) */
    tmp[1] = (WL * 4U) - 2U - 2U + 5U;
    /* dql(tphy_rdlat + trddata_en) : RL * 4 + phy_rptr_update + phy_rddqs_latency_adjust + 39 */
    tmp[2] = (RL * 4U) + r_ddrtbl_getval(DDR_PHY_SLICE_REGSET, PHY_RPTR_UPDATE) + r_ddrtbl_getval(DDR_PHY_SLICE_REGSET, PHY_RDDQS_LATENCY_ADJUST) + 39U;
    /* dqienltncy(trddata_en) : RL * 4 - phy_rddata_en_dly_X + 4 * phy_wck_freq_ratio_X */
    tmp[3] = (RL * 4U) + 4U - r_ddrtbl_getval(DDR_PHY_SLICE_REGSET, PHY_RDDATA_EN_DLY);
    r_dbsc_write_32(DBSC_DBTR(16U), ((tmp[3] << 24) | (tmp[2] << 16) | (tmp[1] << 8) | tmp[0]));

    /* DBTR17.tmodrd,tmod : tMRR,tMRW */
    r_dbsc_write_32(DBSC_DBTR(17U), ((js2[JS2_tMRR] << 24) | (js2[JS2_tMRW] << 16)));

    /* DBTR18.rodtl,rodta = 0 */
    r_dbsc_write_32(DBSC_DBTR(18U), 0x00000000U);

    /* DBTR19.tzqcl,tzqcs = 0 */
    r_dbsc_write_32(DBSC_DBTR(19U), 0x00000000U);

    /* DBTR20.txsdll,txs : tXSR,tXSR */
    r_dbsc_write_32(DBSC_DBTR(20U), ((js2[JS2_tXSR] << 16) | js2[JS2_tXSR]));

    /* DBTR21.tccd */
    r_dbsc_write_32(DBSC_DBTR(21U), ((ddr_tccd << 16) | (ddr_tccd * 2U)));

    /* DBTR22.tzqcal,tzqlat : tZQCAL,tZQLAT */
    r_dbsc_write_32(DBSC_DBTR(22U), ((js2[JS2_tZQCALns] << 16) | js2[JS2_tZQLAT]));

    /* DBTR23.rrspc = 0 */
    r_dbsc_write_32(DBSC_DBTR(23U), 0x00000000U);

    /* DBTR24 */
    /* wrcslat(tphy_wrcslat) */
    tmp[0] = (WL * 4U) - 2U;
    /* wrcsgap(tphy_wrcsgap) */
    tmp[1] = 0x0CU;
    /* rdcslat(tphy_rdcslat) */
    tmp[2] = RL * 4U;
    /* rdcsgap(tphy_rdcsgap) */
    tmp[3] = 0x0CU;
    r_dbsc_write_32(DBSC_DBTR(24U), ((tmp[3] << 24) | (tmp[2] << 16) | (tmp[1] << 8) | tmp[0]));

    /* DBTR25 */
    r_dbsc_write_32(DBSC_DBTR(25U), 0x00000000U);

    /* DBTR26 */
    r_dbsc_write_32(DBSC_DBTR(26U), 0x00000000U);

    /* DBTR27.tpdn : tPDN */
    r_dbsc_write_32(DBSC_DBTR(27U), js2[JS2_tPDN]);

    /* DBTR28.txsrdsm : tXSR_DSM */
    r_dbsc_write_32(DBSC_DBTR(28U), js2[JS2_tXSR_DSM]);

    /* DBTR29.tdsmxp : tXDSM_XP */
    r_dbsc_write_32(DBSC_DBTR(29U), js2[JS2_tXDSM_XP]);

    /* DBTR30.tcmdpd : tCMDPD = 3 */
    r_dbsc_write_32(DBSC_DBTR(30U), 0x00000003U);

    /* DBTR31.twck2dqomax,twck2dqimax : tWCK2DQO_HF/LF,tWCK2DQI_HF/LF */
    r_dbsc_write_32(DBSC_DBTR(31U), ((js2[JS2_tWCK2DQO_HF] << 4) | js2[JS2_tWCK2DQI_HF]));

    /* DBTR32 */
    /* twckenr */
    tmp[0] = (js1[js1_ind].WCKENLR * 4U) + 4U - 1U;
    /* twckenw */
    tmp[1] = (js1[js1_ind].WCKENLW * 4U) + 4U - 1U;
    /* twckenlf */
    tmp[2] = (js1[js1_ind].WCKENLF * 4U) + 4U;
    /* twckpresta */
    tmp[3] = js1[js1_ind].WCKPRESTA * 4U;
    r_dbsc_write_32(DBSC_DBTR(32U), ((tmp[3] << 24) | (tmp[2] << 16) | (tmp[1] << 8) | tmp[0]));

    /* DBTR33 */
    /* twcktgl */
    tmp[0] = 4U;
    /* twckdis : (RL+ bl/n_max) * 4 + RU(tWCKPST/tWCK),tWCKPST = MR10[3:2] = 2.5 */
    tmp[1] = ((RL + 4U) * 4U) + 3U;
    r_dbsc_write_32(DBSC_DBTR(33U), ((tmp[1] << 8) | tmp[0]));

    /* DBTR34 */
    /* twcksus = 4 */
    tmp[0] = 4U;
    /* twckpst : RU(tWCKPST/tCK),tWCKPST = MR10[3:2] = 2.5 */
    tmp[1] = 1U;
    r_dbsc_write_32(DBSC_DBTR(34U), ((tmp[1] << 8) | tmp[0]));

    /* DBTR35 */
    /* trd2wckoff : RL + BL/n_max + RD(tWCKPST/tCK) + 1 */
    tmp[0] = RL + 4U + 0U +1U;
    /* twr2wckoff : WL + BL/n_max + RD(tWCKPST/tCK) + 1 */
    tmp[1] = WL + 4U + 0U +1U;
    r_dbsc_write_32(DBSC_DBTR(35U), ((tmp[1] << 16) | tmp[0]));

    /* DBTR36 */
    /* twssuswrx : CAS(WCKSUS)WRX */
    tmp[0] = 3U;
    /* twsoffwrx : CAS(WS_OFF)WRX */
    tmp[1] = 3U;
    /* twsfswrx : CAS(WS_FS)WRX */
    tmp[2] = 2U;
    r_dbsc_write_32(DBSC_DBTR(36U), ((tmp[2] << 16) | (tmp[1] << 8) | tmp[0]));

    /* DBTR37.tosco : tOSCODQI */
    r_dbsc_write_32(DBSC_DBTR(37U), js2[JS2_tOSCODQI]);

    /* DBRNK2 */
    /* rnkrr = 12 */
    r_dbsc_write_32(DBSC_DBRNK(2U), 0x000000CCU);

    /* DBRNK3 */
    /* rnkrw = 6 */
    r_dbsc_write_32(DBSC_DBRNK(3U), 0x00000066U);

    /* DBRNK4 */
    /* rnkwr = 6 */
    r_dbsc_write_32(DBSC_DBRNK(4U), 0x00000066U);

    /* DBRNK5 */
    /* rnkww = 14 */
    r_dbsc_write_32(DBSC_DBRNK(5U), 0x000000EEU);

    /* DBBUS0CNF1 */
    /* BGADM */
    r_dbsc_write_32(DBSC_DBBUS0CNF1, 0x00010000U);

    /***********************************************************************
     * timing registers for Scheduler
     ***********************************************************************/
    /* SCFCTST0 */
    /* scpreact */
    tmp[0] = 1UL * js2[JS2_tRPpb] * bus_clk * ddr_mbpsdiv * 8U / ddr_mbps / bus_clkdiv;
    /* scactrdwr */
    tmp[1] = 1UL * (WL + 2U + 1U + js1[js1_ind].nWR + js2[JS2_tRPpb]) * bus_clk * ddr_mbpsdiv * 8U / ddr_mbps / bus_clkdiv;
    /* scrdacrt */
    tmp[2] = 1UL * ((js1[js1_ind].nRBTP + 2U) + js2[JS2_tRPpb]) * bus_clk * ddr_mbpsdiv * 8U / ddr_mbps / bus_clkdiv;
    /* scactact */
    tmp[3] = 1UL * js2[JS2_tRCpb] * bus_clk * ddr_mbpsdiv * 8U / ddr_mbps / bus_clkdiv;
    r_dbsc_write_32(DBSC_DBSCHFCTST0, ((tmp[3] << 24) | (tmp[2] << 16) | (tmp[1] << 8) | tmp[0]));

    /* SCFCTST1 */
    /* scasyncofs */
    tmp[0] = 12U;
    /* scactrdwr */
    tmp[1] = 1UL * js2[JS2_tRCD] * bus_clk * ddr_mbpsdiv * 8U / ddr_mbps / bus_clkdiv;
    /* scwrrd */
    tmp[2] = 1UL * (mmio_read_32(DBSC_DBTR(12U)) & 0xFFU) * bus_clk * ddr_mbpsdiv * 8U / ddr_mbps / bus_clkdiv;
    /* scrdwr */
    tmp[3] = 1UL * (mmio_read_32(DBSC_DBTR(11U)) & 0xFFU) * bus_clk * ddr_mbpsdiv * 8U / ddr_mbps / bus_clkdiv;
    r_dbsc_write_32(DBSC_DBSCHFCTST1, ((tmp[3] << 24) | (tmp[2] << 16) | (tmp[1] << 8) | tmp[0]));

    /* DBSCHRW1 */
    /* sctrfcab */
    tmp[0] = 1UL * (js2[JS2_tRFCab] + js2[JS2_tZQLAT]) * bus_clk * ddr_mbpsdiv * 8U / ddr_mbps / bus_clkdiv;
    r_dbsc_write_32(DBSC_DBSCHRW1, tmp[0]);

    /* DBSCHTR0 */
    /* scdt0 */
    tmp[0] = (1UL * 4U * bus_clk * ddr_mbpsdiv * 8U / ddr_mbps / bus_clkdiv) - 1U;
    /* scdt1 */
    tmp[1] = (1UL * 8U * bus_clk * ddr_mbpsdiv * 8U / ddr_mbps / bus_clkdiv) - 1U;
    /* scdt2 */
    tmp[2] = (1UL * 12U * bus_clk * ddr_mbpsdiv * 8U / ddr_mbps / bus_clkdiv) - 1U;
    /* scdt3 */
    tmp[3] = (1UL * 16U * bus_clk * ddr_mbpsdiv * 8U / ddr_mbps / bus_clkdiv) - 1U;
    r_dbsc_write_32(DBSC_DBSCHTR0, ((tmp[3] << 24) | (tmp[2] << 16) | (tmp[1] << 8) | tmp[0]));

    /***********************************************************************
     * QOS and CAM
     ***********************************************************************/
    r_dbsc_write_32(DBSC_DBBCAMDIS, 0x00000001U);
}

static void r_dbsc_regset_post(void)
{
    uint32_t dataL;

#if ((RCAR_PERIODIC_WRITE_TRAINING != 0U) || (RCAR_PERIODIC_READ_TRAINING != 0U))
    uint32_t ctrl_clk;
    uint32_t clk_count;
    uint32_t phymster_req_interval;
#endif /* ((RCAR_PERIODIC_WRITE_TRAINING != 0U) || (RCAR_PERIODIC_READ_TRAINING != 0U)) */

    r_dbsc_write_32(DBSC_DBDBICNT, 0x00000003U);

    /* set REFCYCLE */
    dataL = DBSC_REFINT * ddr_mbps / 8000U / ddr_mbpsdiv;
    /* refpmax=8 */
    r_dbsc_write_32(DBSC_DBRFCNF1, 0x00080000U | (dataL & 0x0000FFFFU));
    /* refpmin=1 */
    r_dbsc_write_32(DBSC_DBRFCNF2, 0x00010000U | DBSC_REFINTS);

#if ((RCAR_PERIODIC_WRITE_TRAINING != 0U) || (RCAR_PERIODIC_READ_TRAINING != 0U))
    r_dbsc_write_32(DBSC_DBDFIPMSTRCNF, 0x00000000U);
#endif /* ((RCAR_PERIODIC_WRITE_TRAINING != 0U) || (RCAR_PERIODIC_READ_TRAINING != 0U)) */

#if (RCAR_PERIODIC_WRITE_TRAINING != 0U)
    /* Periodic-WriteDQ Training setting */
    r_ddr_setval_ach(PI_WDQLVL_EN_F2,              0x03U);
    r_ddr_setval_ach(PI_WDQLVL_VREF_EN,            0x00U);
    r_ddr_setval_ach_as(PHY_DATA_DC_WDQLVL_ENABLE, 0x00U);
    r_ddr_setval_ach(PI_WDQLVL_PERIODIC,           0x01U);
#endif /* (RCAR_PERIODIC_WRITE_TRAINING != 0U) */

#if (RCAR_PERIODIC_READ_TRAINING != 0U)
    /* Periodic-ReadDQ Training setting */
    r_ddr_setval_ach(PI_RDLVL_EN_F2,        0x03U);
    r_ddr_setval_ach(PI_RDLVL_VREF_EN_F2,   0x00U);
    r_ddr_setval_ach_as(PHY_RDLVL_DLY_STEP, 0x04U);
    r_ddr_setval_ach(PI_RDLVL_PERIODIC,     0x01U);
#endif /* (RCAR_PERIODIC_READ_TRAINING != 0U) */

#if ((RCAR_PERIODIC_WRITE_TRAINING != 0U) || (RCAR_PERIODIC_READ_TRAINING != 0U))
    /* DFI_PHYMSTR_ACK , WTmode = b'01 */
    r_dbsc_write_32(DBSC_DBDFIPMSTRCNF, 0x00000011U);
#endif /* ((RCAR_PERIODIC_WRITE_TRAINING != 0U) || (RCAR_PERIODIC_READ_TRAINING != 0U)) */

    /* periodic SoC zqcal enable */
    r_ddr_setval_ach(PHY_CAL_MODE_0, r_ddrtbl_getval(DDR_PHY_ADR_G_REGSET, PHY_CAL_MODE_0) | 0x02U);

#if (RCAR_MEDIUM_FREQUENCY_TRAINING_MODE == 1U)
    if (med_freq_en == 0x01U)
    {
        /* Prepare DFS after initialization */
        /* Medium frequency mode (F1) */
        r_ddr_setval_ach(PI_RDLVL_GATE_EN_F1, 0x03U);
        r_ddr_setval_ach(PI_RDLVL_EN_F1,      0x01U);
        r_ddr_setval_ach(PI_WDQLVL_EN_F1,     0x03U);
        /* High frequency mode (F2) */
        r_ddr_setval_ach(PI_RDLVL_GATE_EN_F2, 0x03U);
        r_ddr_setval_ach(PI_RDLVL_EN_F2,      0x03U);
        r_ddr_setval_ach(PI_WDQLVL_EN_F2,     0x03U);
    }
#endif /* (RCAR_MEDIUM_FREQUENCY_TRAINING_MODE == 1U) */

    /* periodic dram zqcal enable */
    r_dbsc_write_32(DBSC_DBCALCNF, 0x01000010U);

    /* periodic phy ctrl update enable */
    r_dbsc_write_32(DBSC_DBDFICUPDCNF, 0x504C0001U);

#ifdef DDR_BACKUPMODE
    if (ddrBackup == DRAM_BOOT_STATUS_WARM)
    {
        /* SRX */
        r_send_dbcmd(0x0A840001U);
    }
#endif /* DDR_BACKUPMODE */
    /* set Auto Refresh */
    r_dbsc_write_32(DBSC_DBRFEN, 0x00000001U);

#if ((RCAR_PERIODIC_WRITE_TRAINING != 0U) || (RCAR_PERIODIC_READ_TRAINING != 0U))
    /* Periodic-WriteDQ/ReadDQ Training Interval setting */
    phymster_req_interval = PERIODIC_TRAINING_INTERVAL - 3000U;
    clk_count = 1024U - (r_ddrtbl_getval_pi(DDR_PI_REGSET, PI_LONG_COUNT_MASK) * 32U);
    ctrl_clk = ddr_mbps / ddr_mbpsdiv / 8U;
    dataL = phymster_req_interval * ctrl_clk / clk_count;
#endif /* ((RCAR_PERIODIC_WRITE_TRAINING != 0U) || (RCAR_PERIODIC_READ_TRAINING != 0U)) */

#if (RCAR_PERIODIC_WRITE_TRAINING != 0U)
    r_ddr_setval_ach(PI_WDQLVL_INTERVAL, dataL);
#endif /* (RCAR_PERIODIC_WRITE_TRAINING != 0U) */

#if ((RCAR_PERIODIC_READ_TRAINING != 0U) && (RCAR_PERIODIC_TRAINING_SEPARATE_MODE == 0U))
    r_ddr_setval_ach(PI_RDLVL_INTERVAL, dataL);
#endif /* ((RCAR_PERIODIC_READ_TRAINING != 0U) && (RCAR_PERIODIC_TRAINING_SEPARATE_MODE == 0U)) */

    /* dram access enable */
    r_dbsc_write_32(DBSC_DBACEN, 0x00000001U);

    MSG_LF("dbsc_regset_post(done)\n");
}

/*******************************************************************************
 *    DFI_INIT_START and PI_TRAINING
 ******************************************************************************/
static uint32_t r_pi_training(void)
{
    uint32_t ch;
    uint32_t phytrainingok;
    uint32_t retry;
    uint32_t dataL;
    uint32_t frqchg_req;
    uint32_t flag;
    uint32_t complete_ng;
    uint32_t ca_training_ng;
    uint32_t wr_training_ng;
    uint32_t gt_training_ng;
    uint32_t rd_training_ng;
    uint32_t wdq_training_ng;

    const uint32_t RETRY_MAX = 0x10000U;

    /***********************************************************************
     * init start
     **********************************************************************/
#if (RCAR_MEDIUM_FREQUENCY_TRAINING_MODE == 1U)
    if (med_freq_en == 0x01U)
    {
        r_ddr_setval_ach(PI_FREQ_MAP,          0x07U);
        r_ddr_setval_ach(PI_INIT_WORK_FREQ,    0x02U);
        r_ddr_setval_ach(PI_CALVL_EN_F1,       0x01U);
        r_ddr_setval_ach(PI_WRLVL_EN_F1,       0x01U);
        r_ddr_setval_ach(PI_RDLVL_GATE_EN_F1,  0x01U);
        r_ddr_setval_ach(PI_WRDCM_LVL_EN_F1,   0x00U);
        r_ddr_setval_ach(PI_DRAMDCA_LVL_EN_F1, 0x00U);
        r_ddr_setval_ach(PI_RDLVL_EN_F1,       0x01U);
        r_ddr_setval_ach(PI_WDQLVL_EN_F1,      0x01U);
        r_ddr_setval_ach(PI_RDLVL_RDDQ_EN_F1,  0x00U);

        r_ddr_setval_ach(PI_RDLVL_VREF_EN_F1,       0x00U);
        r_ddr_setval_ach_as(PHY_VREF_TRAINING_CTRL, 0x00U);
        r_ddr_setval_ach(PI_WDQLVL_VREF_EN,         0x00U);
    }
#endif /* (RCAR_MEDIUM_FREQUENCY_TRAINING_MODE == 1U) */

    r_ddr_setval_ach(PI_RDLVL_GATE_EN_F2,  0x00U);
    r_ddr_setval_ach(PI_WRDCM_LVL_EN_F2,   0x00U);
    r_ddr_setval_ach(PI_DRAMDCA_LVL_EN_F2, 0x00U);
    r_ddr_setval_ach(PI_RDLVL_EN_F2,       0x00U);
    r_ddr_setval_ach(PI_WDQLVL_EN_F2,      0x00U);
    r_ddr_setval_ach(PI_SEQ_ARRAY_81,      0x00000000U);
    r_ddr_setval_ach(PI_SEQ_ARRAY_82,      0x00000000U);

    /* PI_START */
    r_ddr_setval_ach(PI_START, 0x01U);

#ifdef DDR_BACKUPMODE
    if (ddrBackup == DRAM_BOOT_STATUS_WARM)
    {
        r_ddr_setval_ach(PI_DLL_RST,             0x01U);
        r_ddr_setval_ach(PI_PWRUP_SREFRESH_EXIT, 0x00U);
    }
#endif /* DDR_BACKUPMODE */

    r_foreach_vch((ch))
    {
        mmio_write_32(DBSC_DBDFICNT(ch), 0x00000020U);
    }

    r_foreach_vch((ch))
    {
        mmio_write_32(DBSC_DBDFICNT(ch), 0x00000021U);
    }

    /* Dummy PDE */
    r_send_dbcmd(0x08840000U);

    /* PDX */
    r_send_dbcmd(0x08840001U);

    /***********************************************************************
     * wait init_complete
     ***********************************************************************/
    phytrainingok = 0U;
    retry = 0U;
    while (retry++ < RETRY_MAX)
    {
        frqchg_req = 0U;
        for (ch = 0U; ch < DRAM_CH_CNT; ch++)
        {
            if ((((~phytrainingok) & ddr_phyvalid) & (1U << ch)) != 0x0U)
            {
                if ((mmio_read_32(DBSC_DBPDSTAT0(ch)) & 0x01U) != 0x0U)
                {
                    frqchg_req = 1U;
                    break;
                }
            }
        }

        if (frqchg_req != 0x0U)
        {
            flag = r_pll3_freq();
            if (flag != 0x0U)
            {
                break;
            }
        }
        else
        {
            r_foreach_vch((ch))
            {
                dataL = mmio_read_32(DBSC_DBDFISTAT(ch));
                if ((dataL & 0x00000001U) != 0x0U)
                {
                    phytrainingok |= (1U << ch);
                }
            }
            if (phytrainingok == ddr_phyvalid)
            {
                break;
            }
        }/* frqchg_req != 0x0U */
    }

    /* dbdficnt0:
     * dfi_dram_clk_disable=0
     * dfi_frequency = 0
     * freq_ratio = 10 (4:1)
     * init_start =0
     */
    r_foreach_vch((ch))
    {
        mmio_write_32(DBSC_DBDFICNT(ch), 0x00000020U);
    }

    /* DFI_PHYMSTR_ACK */
    r_dbsc_write_32(DBSC_DBDFIPMSTRCNF, 0x00000001U);

    complete_ng     = 0x0U;
    ca_training_ng  = 0x0U;
    wr_training_ng  = 0x0U;
    gt_training_ng  = 0x0U;
    rd_training_ng  = 0x0U;
    wdq_training_ng = 0x0U;

    /* Err Check */
    r_foreach_vch((ch))
    {
        /* CA/CS Training Err Check */
        dataL = 0x0U;
        dataL = (r_ddr_getval(ch, PI_INT_STATUS) & (0x1U << 4));           /* PI_CALVL_ERROR_BIT */
        dataL |= (r_ddr_getval(ch, PHY_ADR_CALVL_OBS1) & (0x3U << 30));    /* error on decrement/increment pass */
        dataL |= (r_ddr_getval(ch, PHY_ADR_CALVL_OBS2) & (0x3U << 24));    /* start outside of initial search range */
        dataL |= (r_ddr_getval(ch, PHY_CSLVL_OBS1) & (0xFU << 28));        /* CSlvl error */
        if (dataL != 0x0U)
        {
            ca_training_ng |= 1U << ch;
            MSG_LF("pi_training_error:1\n");
        }

        /* Wrlvl Err Check */
        dataL = 0x0U;
        dataL = (r_ddr_getval(ch, PI_INT_STATUS) & (0x1U << 3));                   /* PI_WRLVL_ERROR_BIT */
        dataL |= (r_ddr_getval_s(ch, 0U, PHY_WRLVL_STATUS_OBS) & (0x1U << 12));    /* SLICE0 wrlvl error */
        dataL |= (r_ddr_getval_s(ch, 1U, PHY_WRLVL_STATUS_OBS) & (0x1U << 12));    /* SLICE1 wrlvl error */
        dataL |= r_ddr_getval_s(ch, 0U, PHY_WRLVL_ERROR_OBS);                      /* SLICE0 wrlvl error */
        dataL |= r_ddr_getval_s(ch, 1U, PHY_WRLVL_ERROR_OBS);                      /* SLICE1 wrlvl error */
        if (dataL != 0x0U)
        {
            wr_training_ng |= 1U << ch;
            MSG_LF("pi_training_error:2\n");
        }

#if (RCAR_MEDIUM_FREQUENCY_TRAINING_MODE == 1U)
        if (med_freq_en == 0x01U)
        {
            /* Gtlvl Err Check */
            dataL = 0x0U;
            dataL = (r_ddr_getval(ch, PI_INT_STATUS) & (0x1U << 2));                  /* PI_RDLVL_GATE_ERROR_BIT */
            dataL |= (r_ddr_getval_s(ch, 0U, PHY_GTLVL_STATUS_OBS) & (0x3U << 7));    /* SLICE0 delay setup error */
            dataL |= (r_ddr_getval_s(ch, 1U, PHY_GTLVL_STATUS_OBS) & (0x3U << 7));    /* SLICE1 delay setup error */
            if (dataL != 0x0U)
            {
                gt_training_ng |= 1U << ch;
                MSG_LF("pi_training_error:3\n");
            }

            /* Rdlvl Err Check */
            dataL = 0x0U;
            dataL = (r_ddr_getval(ch, PI_INT_STATUS) & (0x1U << 1));    /* PI_RDLVL_ERROR_BIT */
            if (dataL != 0x0U)
            {
                rd_training_ng |= 1U << ch;
                MSG_LF("pi_training_error:4\n");
            }

            /* Wdqlvl Err Check */
            dataL = 0x0U;
            dataL = (r_ddr_getval(ch, PI_INT_STATUS) & (0x1U << 5));                      /* PI_WDQLVL_ERROR_BIT */
            dataL |= (r_ddr_getval_s(ch, 0U, PHY_WDQLVL_STATUS_OBS) & (0x1FFU << 18));    /* SLICE0 wdqlvl_fail_dqZ */
            dataL |= (r_ddr_getval_s(ch, 1U, PHY_WDQLVL_STATUS_OBS) & (0x1FFU << 18));    /* SLICE1 wdqlvl_fail_dqZ */
            if (dataL != 0x0U)
            {
                wdq_training_ng |= 1U << ch;
                MSG_LF("pi_training_error:5\n");
            }
        }
#endif /* (RCAR_MEDIUM_FREQUENCY_TRAINING_MODE == 1U) */
    }

    complete_ng = (wdq_training_ng | rd_training_ng | gt_training_ng | wr_training_ng | ca_training_ng);
    if (complete_ng != 0x0U)
    {
        return ~complete_ng;
    }

    /* PI_INT_ACK assert */
    r_foreach_vch((ch))
    {
        r_ddr_setval(ch, PI_INT_ACK_0, 0xFFFFFFFFU);
        r_ddr_setval(ch, PI_INT_ACK_1, 0x01U);
    }

    return phytrainingok;
}

/*******************************************************************************
 *    Write Leveling Cycle Adjust
 ******************************************************************************/
static void r_write_leveling_adjust(void)
{
    uint32_t ch;
    uint32_t result_hard0;
    uint32_t result_hard1;
    uint32_t avg;
    uint32_t avg_frac;
    uint32_t avg_cycle;

    r_foreach_vch((ch))
    {
        /* SLICE0 */
        result_hard0 = r_ddr_getval_s(ch, 0U, PHY_WRLVL_HARD0_DELAY_OBS);
        result_hard1 = r_ddr_getval_s(ch, 0U, PHY_WRLVL_HARD1_DELAY_OBS);

        if (result_hard0 <= result_hard1)
        {
            avg = (result_hard0 + result_hard1) / 2U;
        }
        else
        {
            avg = (result_hard0 + result_hard1 + 0x400U) / 2U;
        }
        avg_frac  = avg & 0xFFU;
        avg_cycle = (avg >> 8) & 0x3U;

        if (avg_cycle == 0x3U)
        {
            r_ddr_setval_s(ch, 0U, PHY_WRITE_PATH_LAT_DEC, 0x1U);
            r_ddr_setval_s(ch, 0U, PHY_WRITE_PATH_LAT_ADD, 0x0U);
        }
        else
        {
            r_ddr_setval_s(ch, 0U, PHY_WRITE_PATH_LAT_DEC, 0x0U);
            r_ddr_setval_s(ch, 0U, PHY_WRITE_PATH_LAT_ADD, avg_cycle);
        }
        r_ddr_setval_s(ch, 0U, PHY_WRITE_PATH_LAT_FRAC, avg_frac);

        /* SLICE1 */
        result_hard0 = r_ddr_getval_s(ch, 1U, PHY_WRLVL_HARD0_DELAY_OBS);
        result_hard1 = r_ddr_getval_s(ch, 1U, PHY_WRLVL_HARD1_DELAY_OBS);

        if (result_hard0 <= result_hard1)
        {
            avg = (result_hard0 + result_hard1) / 2U;
        }
        else
        {
            avg = (result_hard0 + result_hard1 + 0x400U) / 2U;
        }
        avg_frac  = avg & 0xFFU;
        avg_cycle = (avg >> 8) & 0x3U;

        if (avg_cycle == 0x3U)
        {
            r_ddr_setval_s(ch, 1U, PHY_WRITE_PATH_LAT_DEC, 0x1U);
            r_ddr_setval_s(ch, 1U, PHY_WRITE_PATH_LAT_ADD, 0x0U);
        }
        else
        {
            r_ddr_setval_s(ch, 1U, PHY_WRITE_PATH_LAT_DEC, 0x0U);
            r_ddr_setval_s(ch, 1U, PHY_WRITE_PATH_LAT_ADD, avg_cycle);
        }
        r_ddr_setval_s(ch, 1U, PHY_WRITE_PATH_LAT_FRAC, avg_frac);
    }

    r_ddr_setval_ach_as(SC_PHY_WCK_CALC, 0x01U);
}

/*******************************************************************************
 *    Re-run Write Leveling & Read Gate Training
 ******************************************************************************/
static uint32_t r_wl_gt_training(void)
{
    uint32_t ch;
    uint32_t phytrainingok;
    uint32_t retry;
    uint32_t dataL;

    uint32_t complete_ng;
    uint32_t wr_training_ng;
    uint32_t gt_training_ng;

    const uint32_t RETRY_MAX = 0x10000U;

    r_ddr_setval_ach(PI_CALVL_EN_F2,        0x00U);
    r_ddr_setval_ach(PI_RDLVL_GATE_EN_F2,   0x01U);
    r_ddr_setval_ach(PI_SEQ_ARRAY_29,       0x181F0000U);
    r_ddr_setval_ach(PI_SEQ_ARRAY_64,       0x00000000U);
    r_ddr_setval_ach(PI_SEQ_ARRAY_65,       0x00000000U);
    r_ddr_setval_ach(PI_SEQ_ARRAY_66,       0x00000000U);
    r_ddr_setval_ach(PI_SEQ_ARRAY_67,       0x00000000U);
    r_ddr_setval_ach(PI_SEQ_ARRAY_68,       0x00000000U);
    r_ddr_setval_ach(PI_SEQ_ARRAY_69,       0x00000000U);
    r_ddr_setval_ach(PI_SEQ_ARRAY_70,       0x00000000U);
    r_ddr_setval_ach(PI_SEQ_ARRAY_71,       0x00000000U);
    r_ddr_setval_ach(PI_SEQ_ARRAY_72,       0x00000000U);
    r_ddr_setval_ach(PI_TRAIN_ALL_FREQ_REQ, 0x01U);
    
    /* Freq Change High to High */
    dataL = r_pll3_freq();
    if (dataL != 0x0U)
    {
        return (1);
    }

    phytrainingok = 0U;
    retry = 0U;
    while (retry++ < RETRY_MAX)
    {
        r_foreach_vch((ch))
        {
            dataL = r_ddr_getval(ch, PI_INT_STATUS);
            if ((dataL & 0x01U) != 0x0U)
            {
                phytrainingok |= (1U << ch);
            }
        }
        if (phytrainingok == ddr_phyvalid)
        {
            break;
        }
    }

    complete_ng     = 0x0U;
    wr_training_ng  = 0x0U;
    gt_training_ng  = 0x0U;

    /* Err Check */
    r_foreach_vch((ch))
    {
        /* Wrlvl Err Check */
        dataL = 0x0U;
        dataL = (r_ddr_getval(ch, PI_INT_STATUS) & (0x1U << 3));                   /* PI_WRLVL_ERROR_BIT */
        dataL |= (r_ddr_getval_s(ch, 0U, PHY_WRLVL_STATUS_OBS) & (0x1U << 12));    /* SLICE0 wrlvl error */
        dataL |= (r_ddr_getval_s(ch, 1U, PHY_WRLVL_STATUS_OBS) & (0x1U << 12));    /* SLICE1 wrlvl error */
        dataL |= r_ddr_getval_s(ch, 0U, PHY_WRLVL_ERROR_OBS);                      /* SLICE0 wrlvl error */
        dataL |= r_ddr_getval_s(ch, 1U, PHY_WRLVL_ERROR_OBS);                      /* SLICE1 wrlvl error */
        if (dataL != 0x0U)
        {
            wr_training_ng |= 1U << ch;
            MSG_LF("wl_gt_training_error:1\n");
        }
        /* Gtlvl Err Check */
        dataL = 0x0U;
        dataL = (r_ddr_getval(ch, PI_INT_STATUS) & (0x1U << 2));                  /* PI_RDLVL_GATE_ERROR_BIT */
        dataL |= (r_ddr_getval_s(ch, 0U, PHY_GTLVL_STATUS_OBS) & (0x3U << 7));    /* SLICE0 delay setup error */
        dataL |= (r_ddr_getval_s(ch, 1U, PHY_GTLVL_STATUS_OBS) & (0x3U << 7));    /* SLICE1 delay setup error */
        if (dataL != 0x0U)
        {
            gt_training_ng |= 1U << ch;
            MSG_LF("wl_gt_training_error:2\n");
        }
    }

    complete_ng = (wr_training_ng | gt_training_ng);
    if (complete_ng != 0x0U)
    {
        return ~complete_ng;
    }

    /* PI_INT_ACK assert */
    r_foreach_vch((ch))
    {
        r_ddr_setval(ch, PI_INT_ACK_0, 0xFFFFFFFFU);
        r_ddr_setval(ch, PI_INT_ACK_1, 0x01U);
    }

    return phytrainingok;
}

/*******************************************************************************
 *    Write DCA Training
 ******************************************************************************/
static void r_write_dca(void)
{
    uint32_t ch;
    uint32_t dataL;
    uint32_t phytrainingok;
    uint32_t retry;
    const uint32_t RETRY_MAX = 0x10000U;

    r_ddr_setval_ach_as(PHY_DATA_DC_CAL_START, 0x01U);
    phytrainingok = 0U;
    retry = 0U;
    while (retry++ < RETRY_MAX)
    {
        r_foreach_vch((ch))
        {
            dataL = (r_ddr_getval_s(ch, 0U, PHY_DATA_DC_CAL_START)) | (r_ddr_getval_s(ch, 1U, PHY_DATA_DC_CAL_START));
            if (dataL == 0x0U)
            {
                phytrainingok |= (1U << ch);
            }
        }
        if (phytrainingok == ddr_phyvalid)
        {
            break;
        }
    }
}

/*******************************************************************************
 *    DRAM DCA Training and Calculations
 ******************************************************************************/
static uint32_t r_dramdca_training(void)
{
    uint32_t ch;
    uint32_t phytrainingok;
    uint32_t dataL;
    uint32_t rank;
    uint32_t dca_result_l_0[DRAM_CH_CNT][CS_CNT];    /* DCA_result_lower_flip0_[ch][cs] */
    uint32_t dca_result_u_0[DRAM_CH_CNT][CS_CNT];    /* DCA_result_upper_flip0_[ch][cs] */
    uint32_t dca_result_l_1[DRAM_CH_CNT][CS_CNT];    /* DCA_result_lower_flip1_[ch][cs] */
    uint32_t dca_result_u_1[DRAM_CH_CNT][CS_CNT];    /* DCA_result_upper_flip1_[ch][cs] */
    uint32_t tempu;
    uint32_t templ;

    const uint32_t    mr30_conv[16] =
    {
        0x08U, 0x07U, 0x06U, 0x05U, 0x04U, 0x03U, 0x02U, 0x01U,
        0x00U, 0x09U, 0x0AU, 0x0BU, 0x0CU, 0x0DU, 0x0EU, 0x0FU
    };

    if (ch_have_this_cs[1] != 0x0U)
    {
        rank = 0x03U;
    }
    else
    {
        rank = 0x01U;
    }

    /***********************************************************************
     * Run DRAM DCA Training for Flip-0
     ***********************************************************************/
    r_ddr_setval_ach(PI_DCMLVL_CS_SW, rank);

    /* DRAMDCA go */
    r_ddr_setval_ach(PI_DRAMDCA_LVL_REQ, 0x01U);

    /* PI_INT_ACK assert */
    phytrainingok = r_pi_int_ack_0_assert(26U);
    if (phytrainingok != ddr_phyvalid)
    {
        return phytrainingok;
    }

    /* result for DRAMDCA flip-0 */
    r_foreach_vch((ch))
    {
        dataL = r_ddr_getval(ch, PI_DARRAY3_20_CS0_F2);
        dca_result_u_0[ch][0] = mr30_conv[dataL >> 4];
        dca_result_l_0[ch][0] = mr30_conv[dataL & 0x0FU];
        if ((rank & 0x02U) != 0x0U)
        {
            dataL = r_ddr_getval(ch, PI_DARRAY3_20_CS1_F2);
            dca_result_u_0[ch][1] = mr30_conv[dataL >> 4];
            dca_result_l_0[ch][1] = mr30_conv[dataL & 0x0FU];
        }
    }

    /***********************************************************************
     * Run DRAM DCA Training for Flip-1
     ***********************************************************************/
    r_ddr_setval_ach(PI_DRAMDCA_FLIP_MASK, 0x01U);
    r_ddr_setval_ach(PI_SEQ_ARRAY_333,     0x00000000U);
    r_ddr_setval_ach(PI_SEQ_ARRAY_334,     0x00000000U);
    r_ddr_setval_ach(PI_SEQ_ARRAY_335,     0x00000000U);

    /* DRAMDCA go */
    r_ddr_setval_ach(PI_DRAMDCA_LVL_REQ, 0x01U);

    /* PI_INT_ACK assert */
    phytrainingok = r_pi_int_ack_0_assert(26U);
    if (phytrainingok != ddr_phyvalid)
    {
        return phytrainingok;
    }

    /* result for DRAMDCA flip-1 */
    r_foreach_vch((ch))
    {
        dataL = r_ddr_getval(ch, PI_DARRAY3_20_CS0_F2);
        dca_result_u_1[ch][0] = mr30_conv[dataL >> 4];
        dca_result_l_1[ch][0] = mr30_conv[dataL & 0x0FU];
        if ((rank & 0x02U) != 0x0U)
        {
            dataL = r_ddr_getval(ch, PI_DARRAY3_20_CS1_F2);
            dca_result_u_1[ch][1] = mr30_conv[dataL >> 4];
            dca_result_l_1[ch][1] = mr30_conv[dataL & 0x0FU];
        }
    }

    /***********************************************************************
     * Calculate and set DRAMDCA value
     ***********************************************************************/
    r_foreach_vch((ch))
    {
        /* CS0 */
        tempu = (dca_result_u_0[ch][0] + dca_result_u_1[ch][0]) / 2U;
        templ = (dca_result_l_0[ch][0] + dca_result_l_1[ch][0]) / 2U;
        dataL = (mr30_conv[tempu] << 4) | (mr30_conv[templ]);
        r_ddr_setval(ch, PI_DARRAY3_20_CS0_F2, dataL);
        if ((rank & 0x02U) != 0x0U)
        {
            /* CS1 */
            tempu = (dca_result_u_0[ch][1] + dca_result_u_1[ch][1]) / 2U;
            templ = (dca_result_l_0[ch][1] + dca_result_l_1[ch][1]) / 2U;
            dataL = (mr30_conv[tempu] << 4) | (mr30_conv[templ]);
            r_ddr_setval(ch, PI_DARRAY3_20_CS1_F2, dataL);
        }
    }

    /* set DRAMDCA value in MR30 */
    r_ddr_setval_ach(PI_SEQ_ARRAY_349, 0x01A11E14U);
    r_ddr_setval_ach(PI_SEQ_ARRAY_350, 0x001F0000U);
    r_ddr_setval_ach(PI_SEQ_DEC_SW_CS, rank);
    r_ddr_setval_ach(PI_SW_SEQ_START,  0x01U);

    /* PI_INT_ACK assert */
    phytrainingok = r_pi_int_ack_0_assert(18U);
    if (phytrainingok != ddr_phyvalid)
    {
        return phytrainingok;
    }

    r_ddr_setval_ach(PI_SEQ_DEC_SW_CS,     0x00U);
    r_ddr_setval_ach(PI_DRAMDCA_FLIP_MASK, 0x02U);
    r_ddr_setval_ach(PI_SEQ_ARRAY_333,     0x001101FCU);
    r_ddr_setval_ach(PI_SEQ_ARRAY_334,     0x00211A00U);
    r_ddr_setval_ach(PI_SEQ_ARRAY_335,     0x00051500U);

    return phytrainingok;
}

/*******************************************************************************
 *    Re-run Write Leveling
 ******************************************************************************/
static uint32_t r_write_leveling(void)
{
    uint32_t ch;
    uint32_t rank;
    uint32_t phytrainingok;
    uint32_t retry;
    uint32_t dataL;
    uint32_t complete_ng;
    uint32_t wr_training_ng;

    const uint32_t RETRY_MAX = 0x10000U;

    if (ch_have_this_cs[1] != 0x0U)
    {
        rank = 0x03U;
    }
    else
    {
        rank = 0x01U;
    }

    r_ddr_setval_ach(PI_CALVL_EN_F2,       0x00U);
    r_ddr_setval_ach(PI_WRDCM_LVL_EN_F2,   0x00U);
    r_ddr_setval_ach(PI_DRAMDCA_LVL_EN_F2, 0x00U);
    r_ddr_setval_ach(PI_WRLVL_CS_SW,       rank);
    r_ddr_setval_ach(PI_WRLVL_REQ,         0x01U);

    phytrainingok = 0U;
    retry = 0U;
    while (retry++ < RETRY_MAX)
    {
        r_foreach_vch((ch))
        {
            dataL = ((r_ddr_getval(ch, PI_INT_STATUS)) >> 27);
            if ((dataL & 0x01U) != 0x0U)
            {
                phytrainingok |= (1U << ch);
            }
        }
        if (phytrainingok == ddr_phyvalid)
        {
            break;
        }
    }

    complete_ng     = 0x0U;
    wr_training_ng  = 0x0U;

    /* Err Check */
    r_foreach_vch((ch))
    {
        /* Wrlvl Err Check */
        dataL = 0x0U;
        dataL = (r_ddr_getval(ch, PI_INT_STATUS) & (0x1U << 3));                   /* PI_WRLVL_ERROR_BIT */
        dataL |= (r_ddr_getval_s(ch, 0U, PHY_WRLVL_STATUS_OBS) & (0x1U << 12));    /* SLICE0 wrlvl error */
        dataL |= (r_ddr_getval_s(ch, 1U, PHY_WRLVL_STATUS_OBS) & (0x1U << 12));    /* SLICE1 wrlvl error */
        dataL |= r_ddr_getval_s(ch, 0U, PHY_WRLVL_ERROR_OBS);                      /* SLICE0 wrlvl error */
        dataL |= r_ddr_getval_s(ch, 1U, PHY_WRLVL_ERROR_OBS);                      /* SLICE1 wrlvl error */
        if (dataL != 0x0U)
        {
            wr_training_ng |= 1U << ch;
            MSG_LF("write_leveling_error:1\n");
        }
    }

    complete_ng = wr_training_ng;
    if (complete_ng != 0x0U)
    {
        return ~complete_ng;
    }

    /* PI_INT_ACK assert */
    r_foreach_vch((ch))
    {
        r_ddr_setval(ch, PI_INT_ACK_0, 0xFFFFFFFFU);
        r_ddr_setval(ch, PI_INT_ACK_1, 0x01U);
    }

    return phytrainingok;
}

/*******************************************************************************
 *    Manual Write DCA Training
 ******************************************************************************/
static void r_manual_write_dca(void)
{
    uint32_t ch;
    uint32_t slice;
    uint32_t rank;
    uint32_t cs;
    uint32_t i;
    uint32_t phy_slv_dly[DRAM_CH_CNT][CS_CNT][SLICE_CNT];
    uint32_t phy_slv_dly_avg[DRAM_CH_CNT][SLICE_CNT];
    uint32_t slv_dly_min[DRAM_CH_CNT][SLICE_CNT];
    uint32_t slv_dly_max[DRAM_CH_CNT][SLICE_CNT];
    uint32_t phy_dcc_code_min[DRAM_CH_CNT][SLICE_CNT];
    uint32_t phy_dcc_code_max[DRAM_CH_CNT][SLICE_CNT];
    uint32_t phy_dcc_code_mid;
    uint32_t tmp;
    uint32_t complete;
    uint32_t retry;
    const uint32_t RETRY_MAX    = 0x10000U;
    const uint8_t ratio_min     = 0x06U;
    const uint8_t ratio_max     = 0x03U;
    const uint8_t ratio_min_div = 0x0AU;
    const uint8_t ratio_max_div = 0x02U;

    if (ch_have_this_cs[1] != 0x0U)
    {
        rank = 0x02U;
    }
    else
    {
        rank = 0x01U;
    }

    r_foreach_vch((ch))
    {
        for (slice = 0U; slice < SLICE_CNT; slice++)
        {
            phy_dcc_code_min[ch][slice] = 0x7FU;
            phy_dcc_code_max[ch][slice] = 0x00U;
        }
    }

    for (cs = 0U; cs < rank; cs++)
    {
        r_ddr_setval_ach_as(PHY_PER_CS_TRAINING_INDEX, cs);
        r_foreach_vch((ch))
        {
            for (slice = 0U; slice < SLICE_CNT; slice++)
            {
                phy_slv_dly[ch][cs][slice] = r_ddr_getval_s(ch, slice, PHY_CLK_WRDQS_SLAVE_DELAY);
            }
        }
    } /* for (cs = 0U; cs < rank; cs++ */

    r_foreach_vch((ch))
    {
        for (slice = 0U; slice < SLICE_CNT; slice++)
        {
            if (rank == 0x02U)
            {
                /* Calculate average between ranks */
                phy_slv_dly_avg[ch][slice] = (phy_slv_dly[ch][0][slice] + phy_slv_dly[ch][1][slice]) / 2U;
            }
            else
            {
                phy_slv_dly_avg[ch][slice] = phy_slv_dly[ch][0][slice];
            }

            /* Determine the search range */
            slv_dly_min[ch][slice] = (phy_slv_dly_avg[ch][slice] & 0x07FU) * ratio_min / ratio_min_div;
            slv_dly_max[ch][slice] = (phy_slv_dly_avg[ch][slice] & 0x07FU) * ratio_max / ratio_max_div;

            if (slv_dly_max[ch][slice] > 0x7FU)
            {
                slv_dly_max[ch][slice] = 0x7FU;
            }
        }
    }

    complete = 0x00U;

    r_ddr_setval_ach_as(PHY_SLV_DLY_CTRL_GATE_DISABLE, 0x01U);

    for (i = 0U; i <= 0x7FU; i++)
    {
        r_foreach_vch((ch))
        {
            for (slice = 0U; slice < SLICE_CNT; slice++)
            {
                if (slv_dly_max[ch][slice] < (slv_dly_min[ch][slice] + i))
                {
                    complete |= ((0x01U << ch) << (8U * slice));
                }
                else
                {
                    /* CS0/1 same setting, Need masked write */
                    r_ddr_setval_s(ch, slice, PHY_CLK_WRDQS_SLAVE_DELAY, (slv_dly_min[ch][slice] + i));
                    r_ddr_setval_s(ch, slice, SC_PHY_WCK_CALC, 0x01U);
                    r_ddr_setval(ch, SC_PHY_MANUAL_UPDATE, 0x01U);
                }
            }
        }

        if (complete == (ddr_phyvalid | (ddr_phyvalid << 8)))
        {
            break;
        }

        /* Exec write dca */
        r_foreach_vch((ch))
        {
            for (slice = 0U; slice < SLICE_CNT; slice++)
            {
                if ((((complete >> (8U * slice)) >> ch) & 0x01U) != 0x01U)
                {
                    r_ddr_setval_s(ch, slice, PHY_DATA_DC_CAL_START, 0x01U);
                }
            }
        }

        r_foreach_vch((ch))
        {
            for (slice = 0U; slice < SLICE_CNT; slice++)
            {
                if ((((complete >> (8U * slice)) >> ch) & 0x01U) != 0x01U)
                {
                    retry = 0U;
                    while (retry++ < RETRY_MAX)
                    {
                        tmp = r_ddr_getval_s(ch, slice, PHY_DATA_DC_CAL_START);
                        if (tmp == 0x00U)
                        {
                            break;
                        }
                    }
                }
            }
        }

        r_foreach_vch((ch))
        {
            for (slice = 0U; slice < SLICE_CNT; slice++)
            {
                if ((slv_dly_min[ch][slice] + i) <= slv_dly_max[ch][slice])
                {
                    tmp = (r_ddr_getval_s(ch, slice, PHY_DATA_DC_DQS_CLK_ADJUST));
                    if ((tmp >> 6) == 0x01U)
                    {
                        tmp = 0x00U;
                    }
                    else if ((tmp >> 6) == 0x02U)
                    {
                        tmp = 0x3FU;
                    }
                    else
                    {
                        ; /* Nothing */
                    }

                    if (tmp < phy_dcc_code_min[ch][slice])
                    {
                        phy_dcc_code_min[ch][slice] = tmp;
                    }

                    if (phy_dcc_code_max[ch][slice] < tmp)
                    {
                        phy_dcc_code_max[ch][slice] = tmp;
                    }
                }
            }
        }
    } /* for (i = 0U; i <= 0x7FU; i++) */

    r_ddr_setval_ach_as(PHY_PER_CS_TRAINING_MULTICAST_EN, 0x00U);

    for (cs = 0U; cs < rank; cs++)
    {
        r_ddr_setval_ach_as(PHY_PER_CS_TRAINING_INDEX, cs);
        r_foreach_vch((ch))
        {
            for (slice = 0U; slice < SLICE_CNT; slice++)
            {
                r_ddr_setval_s(ch, slice, PHY_CLK_WRDQS_SLAVE_DELAY, phy_slv_dly[ch][cs][slice]);
                r_ddr_setval_s(ch, slice, SC_PHY_WCK_CALC, 0x01U);
                r_ddr_setval(ch, SC_PHY_MANUAL_UPDATE, 0x01U);
            }
        }
    }

    r_ddr_setval_ach_as(PHY_SLV_DLY_CTRL_GATE_DISABLE, 0x00U);

    r_ddr_setval_ach_as(PHY_PER_CS_TRAINING_MULTICAST_EN, 0x01U);

    r_foreach_vch((ch))
    {
        for (slice = 0U; slice < SLICE_CNT; slice++)
        {
            phy_dcc_code_mid = (phy_dcc_code_min[ch][slice] + phy_dcc_code_max[ch][slice]) / 2U;
            r_ddr_setval_s(ch, slice, PHY_DATA_DC_DQS_CLK_ADJUST, phy_dcc_code_mid);
        }
    }
}

/*******************************************************************************
 *    Re-run Read Gate Training
 ******************************************************************************/
static uint32_t r_read_gate_training(void)
{
    uint32_t ch;
    uint32_t rank;
    uint32_t dataL;
    uint32_t phytrainingok;
    uint32_t retry;
    uint32_t complete_ng;
    uint32_t gt_training_ng;

    const uint32_t RETRY_MAX = 0x10000U;

    if (ch_have_this_cs[1] != 0x0U)
    {
        rank = 0x03U;
    }
    else
    {
        rank = 0x01U;
    }

    r_ddr_setval_ach(PI_WRLVL_EN_F2,      0x00U);
    r_ddr_setval_ach(PI_RDLVL_GATE_EN_F2, 0x01U);
    r_ddr_setval_ach(PI_RDLVL_CS_SW,      rank);
    r_ddr_setval_ach(PI_RDLVL_GATE_REQ,   0x01U);

    phytrainingok = 0U;
    retry = 0U;
    while (retry++ < RETRY_MAX)
    {
        r_foreach_vch((ch))
        {
            dataL = ((r_ddr_getval(ch, PI_INT_STATUS)) >> 22);
            if ((dataL & 0x01U) != 0x0U)
            {
                phytrainingok |= (1U << ch);
            }
        }
        if (phytrainingok == ddr_phyvalid)
        {
            break;
        }
    }

    complete_ng     = 0x0U;
    gt_training_ng  = 0x0U;

    /* Err Check */
    r_foreach_vch((ch))
    {
        /* Gtlvl Err Check */
        dataL = 0x0U;
        dataL = (r_ddr_getval(ch, PI_INT_STATUS) & (0x1U << 2));                  /* PI_RDLVL_GATE_ERROR_BIT */
        dataL |= (r_ddr_getval_s(ch, 0U, PHY_GTLVL_STATUS_OBS) & (0x3U << 7));    /* SLICE0 delay setup error */
        dataL |= (r_ddr_getval_s(ch, 1U, PHY_GTLVL_STATUS_OBS) & (0x3U << 7));    /* SLICE1 delay setup error */
        if (dataL != 0x0U)
        {
            gt_training_ng |= 1U << ch;
            MSG_LF("read_gate_training_error\n");
        }
    }

    complete_ng = gt_training_ng;
    if (complete_ng != 0x0U)
    {
        return ~complete_ng;
    }

    /* PI_INT_ACK assert */
    r_foreach_vch((ch))
    {
        r_ddr_setval(ch, PI_INT_ACK_0, 0xFFFFFFFFU);
        r_ddr_setval(ch, PI_INT_ACK_1, 0x01U);
    }

    return phytrainingok;
}

/***********************************************************************
 *    Read Data Training with VREF Training
 ***********************************************************************/
static uint32_t r_read_vref_training(void)
{
    uint32_t ch;
    uint32_t phytrainingok;
    uint32_t retry;
    uint32_t dataL;
    uint32_t rank;
    uint32_t curr_rank;
    uint32_t vref_start, vref_stop, vref_step;
    uint32_t vref_stop_index;
    uint32_t dvw_min_byte0[DRAM_CH_CNT], dvw_min_byte1[DRAM_CH_CNT];
    uint32_t obs_sel;
    uint32_t win_byte0, win_byte1;
    uint32_t best_vref_byte0, best_vref_byte1;
    uint32_t best_vref_byte0_index, best_vref_byte1_index;
    uint32_t best_dvw_min_byte0, best_dvw_min_byte1;
    uint32_t best_thrshld;
    uint32_t vref_outlier;
    uint32_t best_lower_vref, best_upper_vref;
    uint32_t outlier_cnt;
    uint32_t tempLE, tempTE;
    uint32_t dvw_min_byte0_table[DRAM_CH_CNT][128];
    uint32_t dvw_min_byte1_table[DRAM_CH_CNT][128];
    int32_t i;

    const uint32_t RETRY_MAX = 0x10000U;

    best_vref_byte0_index = 0U;
    best_vref_byte1_index = 0U;
    phytrainingok = 0U;

    for (ch = 0U; ch < DRAM_CH_CNT; ch++)
    {
        dvw_min_byte0[ch] = 0x0U;
        dvw_min_byte1[ch] = 0x0U;
    }

    if (ch_have_this_cs[1] != 0x0U)
    {
        rank = 0x02U;
    }
    else
    {
        rank = 0x01U;
    }

    r_ddr_setval_ach(PI_RDLVL_EN_F2,            0x03U);
    r_ddr_setval_ach(PI_RDLVL_VREF_EN_F0,       0x00U);
    r_ddr_setval_ach(PI_RDLVL_VREF_EN_F1,       0x00U);
    r_ddr_setval_ach(PI_RDLVL_VREF_EN_F2,       0x00U);
    r_ddr_setval_ach_as(PHY_VREF_TRAINING_CTRL, 0x00U);

    /* ch0 vref_point */
    vref_start = r_ddr_getval(0U, PHY_VREF_INITIAL_START_POINT);
    vref_stop  = r_ddr_getval(0U, PHY_VREF_INITIAL_STOP_POINT);
    vref_step  = r_ddr_getval(0U, PHY_VREF_INITIAL_STEPSIZE);
    vref_stop_index = (vref_stop - vref_start) / vref_step;

    if (vref_stop_index > 0x80U)
    {
        return phytrainingok;
    }

    for (i = 0; i <= vref_stop_index; i++)
    {
        r_foreach_vch((ch))
        {
            dataL = (r_ddr_getval_s(ch, 0U, PHY_PAD_VREF_CTRL_DQ)) & (0xFU << 10);
            r_ddr_setval_s(ch, 0U, PHY_PAD_VREF_CTRL_DQ, (dataL | (0x1U << 9) | (vref_start + (vref_step * i))));
            dataL = (r_ddr_getval_s(ch, 1U, PHY_PAD_VREF_CTRL_DQ)) & (0xFU << 10);
            r_ddr_setval_s(ch, 1U, PHY_PAD_VREF_CTRL_DQ, (dataL | (0x1U << 9) | (vref_start + (vref_step * i))));
        }

        for (curr_rank = 0U; curr_rank < rank; curr_rank++)
        {
            /* All ch Read Training Start */
            r_ddr_setval_ach(PI_RDLVL_CS_SW, (0x1U << curr_rank));
            r_ddr_setval_ach(PI_RDLVL_REQ, 0x01U);

            phytrainingok = 0U;
            retry = 0U;
            while (retry++ < RETRY_MAX)
            {
                r_foreach_vch((ch))
                {
                    dataL = r_ddr_getval(ch, PI_INT_STATUS);
                    if (((dataL >> 23) & 0x01U) != 0x0U)
                    {
                        phytrainingok |= (1U << ch);
                    }
                }
                if (phytrainingok == ddr_phyvalid)
                {
                    break;
                }
            }
            /* Read Training End */
            r_ddr_setval_ach(PI_INT_ACK_0, (0x1U << 23));

            r_foreach_vch((ch))
            {
                /* minimum Data Valie Window for each VREF */
                dvw_min_byte0[ch] = 0xFFFFFFFFU;
                dvw_min_byte1[ch] = 0xFFFFFFFFU;
                for (obs_sel = 0x00U; obs_sel < 0x19U; obs_sel++)
                {
                    if ((obs_sel < 0x11U) || (obs_sel == 0x18U))
                    {
                        r_ddr_setval_s(ch, 0U, PHY_RDLVL_RDDQS_DQ_OBS_SELECT, obs_sel);
                        r_ddr_setval_s(ch, 1U, PHY_RDLVL_RDDQS_DQ_OBS_SELECT, obs_sel);

                        tempLE = r_ddr_getval_s(ch, 0U, PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS);
                        tempTE = r_ddr_getval_s(ch, 0U, PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS);
                        if (tempTE > tempLE)
                        {
                            win_byte0 = tempTE - tempLE;
                        }
                        else
                        {
                            win_byte0 = 0U;
                        }
                        tempLE = r_ddr_getval_s(ch, 1U, PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS);
                        tempTE = r_ddr_getval_s(ch, 1U, PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS);
                        if (tempTE > tempLE)
                        {
                            win_byte1 = tempTE - tempLE;
                        }
                        else
                        {
                            win_byte1 = 0U;
                        }

                        if (dvw_min_byte0[ch] > win_byte0)
                        {
                            dvw_min_byte0[ch] = win_byte0;
                        }
                        if (dvw_min_byte1[ch] > win_byte1)
                        {
                            dvw_min_byte1[ch] = win_byte1;
                        }
                    }
                }
            }
        } /* For all memory rank */
        r_foreach_vch((ch))
        {
            dvw_min_byte0_table[ch][i] = dvw_min_byte0[ch];
            dvw_min_byte1_table[ch][i] = dvw_min_byte1[ch];
        }
    } /* For all vref_stop_index steps */

    r_foreach_vch((ch))
    {
        /* Search best VREF byte0 */
        best_vref_byte0 = vref_start;
        best_vref_byte0_index = 0U;
        best_dvw_min_byte0 = dvw_min_byte0_table[ch][0U];
        for (i = 0; i <= vref_stop_index; i++)
        {
            if (best_dvw_min_byte0 < dvw_min_byte0_table[ch][i])
            {
                best_vref_byte0 = vref_start + (vref_step * i);
                best_vref_byte0_index = i;
                best_dvw_min_byte0 = dvw_min_byte0_table[ch][i];
            }
        }

        /* Search best_lower VREF byte0 */
        dataL = r_ddr_getval_s(ch, 0U, PHY_RDLVL_DLY_STEP);
        if (dataL == 0U)
        {
            best_thrshld = r_ddr_getval_s(ch, 0U, PHY_RDLVL_BEST_THRSHLD);
        }
        else
        {
            best_thrshld = r_ddr_getval_s(ch, 0U, PHY_RDLVL_BEST_THRSHLD) * dataL;
        }

        vref_outlier = r_ddr_getval_s(ch, 0U, PHY_RDLVL_VREF_OUTLIER);
        best_lower_vref = best_vref_byte0;
        outlier_cnt = vref_outlier;
        for (i = best_vref_byte0_index; i >= 0; i--)
        {
            if (dvw_min_byte0_table[ch][i] <= 0U)
            {
                break;
            }
            if (dvw_min_byte0_table[ch][i] >= (best_dvw_min_byte0 - best_thrshld))
            {
                best_lower_vref = vref_start + (vref_step * i);
            }
            else
            {
                if (outlier_cnt > 0U)
                {
                    outlier_cnt--;
                }
                else
                {
                    break;
                }
            }
            if (i == 0)
            {
                break;
            }
        }

        /* Search best_upper VREF byte0 */
        vref_outlier = r_ddr_getval_s(ch, 0U, PHY_RDLVL_VREF_OUTLIER);
        best_upper_vref = best_vref_byte0;
        outlier_cnt = vref_outlier;
        for (i = best_vref_byte0_index; i <= vref_stop_index; i++)
        {
            if (dvw_min_byte0_table[ch][i] <= 0U)
            {
                break;
            }
            if (dvw_min_byte0_table[ch][i] >= (best_dvw_min_byte0 - best_thrshld))
            {
                best_upper_vref = vref_start + (vref_step * i);
            }
            else
            {
                if (outlier_cnt > 0U)
                {
                    outlier_cnt--;
                }
                else
                {
                    break;
                }
            }
        }

        /* Calculate center of best vref range byte0 */
        best_vref_byte0 = (best_lower_vref + best_upper_vref) / 2U;

        /* Search best VREF byte1 */
        best_vref_byte1 = vref_start;
        best_vref_byte1_index = 0U;
        best_dvw_min_byte1 = dvw_min_byte1_table[ch][0U];
        for (i = 0; i <= vref_stop_index; i++)
        {
            if (best_dvw_min_byte1 < dvw_min_byte1_table[ch][i])
            {
                best_vref_byte1 = vref_start + (vref_step * i);
                best_vref_byte1_index = i;
                best_dvw_min_byte1 = dvw_min_byte1_table[ch][i];
            }
        }

        /* Search best_lower VREF byte1 */
        dataL = r_ddr_getval_s(ch, 1U, PHY_RDLVL_DLY_STEP);
        if (dataL == 0U)
        {
            best_thrshld = r_ddr_getval_s(ch, 1U, PHY_RDLVL_BEST_THRSHLD);
        }
        else
        {
            best_thrshld = r_ddr_getval_s(ch, 1U, PHY_RDLVL_BEST_THRSHLD) * dataL;
        }

        vref_outlier = r_ddr_getval_s(ch, 1U, PHY_RDLVL_VREF_OUTLIER);
        best_lower_vref = best_vref_byte1;
        outlier_cnt = vref_outlier;
        for (i = best_vref_byte1_index; i >= 0; i--)
        {
            if (dvw_min_byte1_table[ch][i] <= 0U)
            {
                break;
            }
            if (dvw_min_byte1_table[ch][i] >= (best_dvw_min_byte1 - best_thrshld))
            {
                best_lower_vref = vref_start + (vref_step * i);
            }
            else
            {
                if (outlier_cnt > 0U)
                {
                    outlier_cnt--;
                }
                else
                {
                    break;
                }
            }
            if (i == 0)
            {
                break;
            }
        }

        /* Search best_upper VREF byte1 */
        vref_outlier = r_ddr_getval_s(ch, 1U, PHY_RDLVL_VREF_OUTLIER);
        best_upper_vref = best_vref_byte1;
        outlier_cnt = vref_outlier;
        for (i = best_vref_byte1_index; i <= vref_stop_index; i++)
        {
            if (dvw_min_byte1_table[ch][i] <= 0U)
            {
                break;
            }
            if (dvw_min_byte1_table[ch][i] >= (best_dvw_min_byte1 - best_thrshld))
            {
                best_upper_vref = vref_start + (vref_step * i);
            }
            else
            {
                if (outlier_cnt > 0U)
                {
                    outlier_cnt--;
                }
                else
                {
                    break;
                }
            }
        }

        /* Calculate center of best vref range byte1 */
        best_vref_byte1 = (best_lower_vref + best_upper_vref) / 2U;

        dataL = (r_ddr_getval_s(ch, 0U, PHY_PAD_VREF_CTRL_DQ)) & (0xFU << 10);
        r_ddr_setval_s(ch, 0U, PHY_PAD_VREF_CTRL_DQ, (dataL | (0x1U << 9) | best_vref_byte0));
        dataL = (r_ddr_getval_s(ch, 1U, PHY_PAD_VREF_CTRL_DQ)) & (0xFU << 10);
        r_ddr_setval_s(ch, 1U, PHY_PAD_VREF_CTRL_DQ, (dataL | (0x1U << 9) | best_vref_byte1));
    }

    return phytrainingok;
}

/*******************************************************************************
 *    Read Data & RDDQ Training with best VREF & Write DQ VREF Training
 ******************************************************************************/
static uint32_t r_read_write_training(void)
{
    uint32_t ch;
    uint32_t phytrainingok;
    uint32_t retry;
    uint32_t dataL;
    uint32_t complete_ng;
    uint32_t rd_training_ng;
    uint32_t wdq_training_ng;

    const uint32_t RETRY_MAX = 0x10000U;

    /* RDDQ_SLAVE_DELAY Set 0x0000 */
    r_ddr_setval_ach_as(PHY_RDDQ0_SLAVE_DELAY, 0x0000U);
    r_ddr_setval_ach_as(PHY_RDDQ1_SLAVE_DELAY, 0x0000U);
    r_ddr_setval_ach_as(PHY_RDDQ2_SLAVE_DELAY, 0x0000U);
    r_ddr_setval_ach_as(PHY_RDDQ3_SLAVE_DELAY, 0x0000U);
    r_ddr_setval_ach_as(PHY_RDDQ4_SLAVE_DELAY, 0x0000U);
    r_ddr_setval_ach_as(PHY_RDDQ5_SLAVE_DELAY, 0x0000U);
    r_ddr_setval_ach_as(PHY_RDDQ6_SLAVE_DELAY, 0x0000U);
    r_ddr_setval_ach_as(PHY_RDDQ7_SLAVE_DELAY, 0x0000U);
    r_ddr_setval_ach_as(PHY_RDDM_SLAVE_DELAY,  0x0000U);

    r_ddr_setval_ach(PI_WRLVL_EN_F2,      0x00U);
    r_ddr_setval_ach(PI_RDLVL_GATE_EN_F2, 0x00U);
    r_ddr_setval_ach(PI_RDLVL_EN_F2,      0x03U);
    r_ddr_setval_ach(PI_WDQLVL_EN_F2,     0x03U);

    r_ddr_setval_ach(PI_TRAIN_ALL_FREQ_REQ, 0x01U);

    /* Freq Change High to High */
    dataL = r_pll3_freq();
    if (dataL != 0x0U)
    {
        return (1);
    }

    phytrainingok = 0U;
    retry = 0U;
    while (retry++ < RETRY_MAX)
    {
        r_foreach_vch((ch))
        {
            dataL = r_ddr_getval(ch, PI_INT_STATUS);
            if ((dataL & 0x01U) != 0x0U)
            {
                phytrainingok |= (1U << ch);
            }
        }
        if (phytrainingok == ddr_phyvalid)
        {
            break;
        }
    }

    complete_ng      = 0x0U;
    rd_training_ng   = 0x0U;
    wdq_training_ng  = 0x0U;

    /* Err Check */
    r_foreach_vch((ch))
    {
        /* Rdlvl Err Check */
        dataL = 0x0U;
        dataL = (r_ddr_getval(ch, PI_INT_STATUS) & (0x1U << 1));    /* PI_RDLVL_ERROR_BIT */
        if (dataL != 0x0U)
        {
            rd_training_ng |= 1U << ch;
            MSG_LF("read_write_training_error:1\n");
        }

        /* Wdqlvl Err Check */
        dataL = 0x0U;
        dataL = (r_ddr_getval(ch, PI_INT_STATUS) & (0x1U << 5));                      /* PI_WDQLVL_ERROR_BIT */
        dataL |= (r_ddr_getval_s(ch, 0U, PHY_WDQLVL_STATUS_OBS) & (0x1FFU << 18));    /* SLICE0 wdqlvl_fail_dqZ */
        dataL |= (r_ddr_getval_s(ch, 1U, PHY_WDQLVL_STATUS_OBS) & (0x1FFU << 18));    /* SLICE1 wdqlvl_fail_dqZ */
        if (dataL != 0x0U)
        {
            wdq_training_ng |= 1U << ch;
            MSG_LF("read_write_training_error:2\n");
        }
    }

    complete_ng = (wdq_training_ng | rd_training_ng);
    if (complete_ng != 0x0U)
    {
        return ~complete_ng;
    }

    /* PI_INT_ACK assert */
    r_foreach_vch((ch))
    {
        r_ddr_setval(ch, PI_INT_ACK_0, 0xFFFFFFFFU);
        r_ddr_setval(ch, PI_INT_ACK_1, 0x01U);
    }

    return phytrainingok;
}

/***********************************************************************
 *    Correct RDDQ Training result & Re-Run Read Data Training
 ***********************************************************************/
static uint32_t r_read_training(void)
{
    uint32_t ch;
    uint32_t slice;
    uint32_t rank;
    uint32_t i;
    uint32_t phytrainingok;
    uint32_t dataL;
    uint32_t complete_ng;
    uint32_t rd_training_ng;
    uint32_t rddq_delay_offset;
    uint32_t rddq_delay_max;

    const uint32_t rddq_delay_addr[9] =
    {
        PHY_RDDQ0_SLAVE_DELAY, PHY_RDDQ1_SLAVE_DELAY, PHY_RDDQ2_SLAVE_DELAY,
        PHY_RDDQ3_SLAVE_DELAY, PHY_RDDQ4_SLAVE_DELAY, PHY_RDDQ5_SLAVE_DELAY,
        PHY_RDDQ6_SLAVE_DELAY, PHY_RDDQ7_SLAVE_DELAY, PHY_RDDM_SLAVE_DELAY
    };

    const uint32_t rddq_delay_offset_ps = 0x19U;
    const uint32_t rddq_delay_max_ps = 0x67U;

    rddq_delay_offset = rddq_delay_offset_ps * ddr_mbps * 256U / (ddr_mbpsdiv * 2U * 1000000U);
    rddq_delay_max    = rddq_delay_max_ps    * ddr_mbps * 256U / (ddr_mbpsdiv * 2U * 1000000U);

    if (ch_have_this_cs[1] != 0x0U)
    {
        rank = 0x03U;
    }
    else
    {
        rank = 0x01U;
    }

    r_foreach_vch((ch))
    {
        for (slice = 0U; slice < SLICE_CNT; slice++)
        {
            for (i = 0U; i < 9U; i++)
            {
                dataL = r_ddr_getval_s(ch, slice, rddq_delay_addr[i]) + rddq_delay_offset;
                if (dataL > rddq_delay_max)
                {
                    dataL = rddq_delay_max;
                }
                r_ddr_setval_s(ch, slice, rddq_delay_addr[i], dataL);
            }
        }
    }

    r_ddr_setval_ach(PI_RDLVL_TRAIN_SEQ_1, 0x00089080U);
    r_ddr_setval_ach(PI_RDLVL_TRAIN_SEQ_2, 0x000811C0U);
    r_ddr_setval_ach(PI_RDLVL_TRAIN_SEQ_3, 0x040811C0U);
    r_ddr_setval_ach(PI_RDLVL_TRAIN_SEQ_4, 0x02000000U);
    r_ddr_setval_ach(PI_RDLVL_TRAIN_SEQ_5, 0x00000000U);
    r_ddr_setval_ach(PI_RDLVL_CS_SW,       rank);

    /* Read training go */
    r_ddr_setval_ach(PI_RDLVL_REQ, 0x01U);

    /* PI_INT_ACK assert */
    phytrainingok = 0x0U;
    phytrainingok = r_pi_int_ack_0_assert(23U);
    if (phytrainingok != ddr_phyvalid)
    {
        return phytrainingok;
    }

    complete_ng      = 0x0U;
    rd_training_ng   = 0x0U;

    /* Err Check */
    r_foreach_vch((ch))
    {
        /* Rdlvl Err Check */
        dataL = 0x0U;
        dataL = (r_ddr_getval(ch, PI_INT_STATUS) & (0x1U << 1));    /* PI_RDLVL_ERROR_BIT */
        if (dataL != 0x0U)
        {
            rd_training_ng |= 1U << ch;
            MSG_LF("read_training_error\n");
        }
    }

    complete_ng = rd_training_ng;
    if (complete_ng != 0x0U)
    {
        return ~complete_ng;
    }

    return phytrainingok;
}

/*******************************************************************************
 *    DDR mode register setting
 ******************************************************************************/
static void r_ddr_register_set(void)
{
    /* MR28 ZQ Mode: Command-Based ZQ Calibration, ZQ interval: Background Cal Interval < 64ms */
    r_send_dbcmd(0x0E841C24U);
}

/*******************************************************************************
 *    DDR mode register read
 ******************************************************************************/
static void r_ddr_register_read(void)
{
    uint32_t dataL;

    dataL = (uint32_t)(Boardcnf->bdcfg_rfm_chk);
    if (dataL != 0x0U)
    {
        /* MR27 rank0 */
        r_send_dbcmd(0x0F801B00U);
        /* MR57 rank0 */
        r_send_dbcmd(0x0F803900U);

        if (ch_have_this_cs[1] != 0x0U)
        {
            /* MR27 rank1 */
            r_send_dbcmd(0x0F811B00U);
            /* MR57 rank1 */
            r_send_dbcmd(0x0F813900U);
        }
    }
}

/*******************************************************************************
 *    Training handshake functions
 ******************************************************************************/
static uint32_t r_pi_int_ack_0_assert(uint32_t bit)
{
    uint32_t dataL;
    uint32_t ch;
    uint32_t phytrainingok;
    uint32_t retry;
    const uint32_t RETRY_MAX = 0x10000U;

    phytrainingok = 0U;
    retry = 0U;
    while (retry++ < RETRY_MAX)
    {
        r_foreach_vch((ch))
        {
            dataL = r_ddr_getval(ch, PI_INT_STATUS);
            if (((dataL >> bit) & 0x01U) != 0x0U)
            {
                phytrainingok |= (1U << ch);
            }
        }
        if (phytrainingok == ddr_phyvalid)
        {
            break;
        }
    }
    if (phytrainingok != ddr_phyvalid)
    {
        return phytrainingok;
    }
    r_foreach_vch((ch))
    {
        r_ddr_setval(ch, PI_INT_ACK_0, (0x1U << bit));
    }
    return phytrainingok;
}

static void r_wait_dbpdstat1(uint32_t status)
{
    uint32_t i, ch, dataL;
    uint32_t freqchg_req_chk;

    for (i = 0U; i < 2U; i++)
    {
        do
        {
            dataL = status;
            freqchg_req_chk = 0U;
            r_foreach_vch((ch))
            {
                dataL &= mmio_read_32(DBSC_DBPDSTAT1(ch));
                freqchg_req_chk |= mmio_read_32(DBSC_DBPDSTAT0(ch));
            }
        } while ((dataL != status) && ((freqchg_req_chk & 0x1U) == 0x0U));
    }
}

static uint32_t r_wait_freqchgreq(uint32_t req_assert)
{
    uint32_t dataL;
    uint32_t count;
    uint32_t ch;

    count = 0xFFFFFFU;

    if (req_assert != 0x0U)
    {
        do
        {
            dataL = 1U;
            r_foreach_vch((ch))
            {
                dataL &= mmio_read_32(DBSC_DBPDSTAT0(ch));
            }
            count = count - 1U;
        } while (((dataL & 0x1U) != 0x1U) && (count != 0U));
    }
    else
    {
        do
        {
            dataL = 0U;
            r_foreach_vch((ch))
            {
                dataL |= mmio_read_32(DBSC_DBPDSTAT0(ch));
            }
            count = count - 1U;
        } while (((dataL & 0x1U) != 0x0U) && (count != 0U));
    } /* (req_assert != 0x0U) */

    return (count == 0U);
}

static void r_set_freqchgack(uint32_t ack_assert)
{
    uint32_t ch;
    uint32_t dataL;

    if (ack_assert != 0x0U)
    {
        dataL = 0x0000CF01U;
    }
    else
    {
        dataL = 0x00000000U;
    }

    r_foreach_vch((ch))
    {
        mmio_write_32(DBSC_DBPDCNT2(ch), dataL);
    }
}

static uint32_t r_pll3_freq(void)
{
    uint32_t timeout;
    uint32_t fsel;

    (void)r_wait_freqchgreq(1);

    fsel = (0x0300U & mmio_read_32(DBSC_DBPDSTAT0(0U))) >> 8;
    if (fsel == 0U)
    {
        r_pll3_control(PLL3_LOW_FREQUENCY_MODE);       /* Low frequency mode */
    }
    else if (fsel == 1U)
    {
        r_pll3_control(PLL3_MEDIUM_FREQUENCY_MODE);    /* Medium frequency mode */
    }
    else
    {
        r_pll3_control(PLL3_HIGH_FREQUENCY_MODE);      /* High frequency mode */
    }

    r_set_freqchgack(1U);

    timeout = r_wait_freqchgreq(0);
    r_set_freqchgack(0U);

    if (timeout != 0x0U)
    {
        FATAL_MSG("Time out\n");
        return (1);
    }

    r_wait_dbpdstat1(0x07U);

    return (0);
}

/*******************************************************************************
 *    Initialize ddr
 ******************************************************************************/
static uint32_t r_init_ddr(void)
{
    uint32_t phytrainingok;
    uint32_t ch;
    uint32_t err;

    MSG_LF("init_ddr:0\n");
#ifdef DDR_BACKUPMODE
    R_DRAM_Get_Boot_Status(&ddrBackup);
#endif /* DDR_BACKUPMODE */

    /***********************************************************************
     * PLL3 initialization setting
     **********************************************************************/
    /* Reset Status Monitor clear */
    r_cpg_write_32(CPG_FSRCHKCLRR4, 0x00000200U);
    /* Reset Status Monitor set */
    r_cpg_write_32(CPG_FSRCHKSETR4, 0x00000200U);
    /* ddrphy soft reset assert */
    r_cpg_write_32(CPG_SRCR4, mmio_read_32(CPG_SRCR4) | 0x00000200U);
    /* wait reset FB */
    while ((mmio_read_32(CPG_FSRCHKRA4) & 0x00000200U) != 0U)
    {
        ; /* Nothing */
    }
    /* Reset Status Monitor clear */
    r_cpg_write_32(CPG_FSRCHKCLRR4, 0x00000200U);

#if (RCAR_DDRPHY_REGISTER_FAST_LOAD_MODE == 1U)
    r_pll3_control(PLL3_HIGH_FREQUENCY_MODE_LOAD_REGISTER);    /* Initialize PLL3 setting */
#else
    r_pll3_control(PLL3_HIGH_FREQUENCY_MODE);    /* Initialize PLL3 setting */
#endif /* (RCAR_DDRPHY_REGISTER_FAST_LOAD_MODE == 1U) */

    /* ddrphy soft reset negate */
    r_cpg_write_32(CPG_SRSTCLR4, 0x00000200U);
    while ((mmio_read_32(CPG_SRCR4) & 0x00000200U) != 0U)
    {
        ; /* Nothing */
    }

    /***********************************************************************
     * unlock phy
     **********************************************************************/
    /* Unlock DDRPHY register */
    r_foreach_vch((ch))
    {
        mmio_write_32(DBSC_DBPDLK(ch), 0x0000A55AU);
    }

    /***********************************************************************
     * dbsc register pre-setting
     ***********************************************************************/
    r_dbsc_regset_pre();

    /***********************************************************************
     * load ddrphy registers
     ***********************************************************************/
    r_ddrtbl_load();

    /***********************************************************************
     * configure ddrphy registers
     ***********************************************************************/
    r_ddr_config();

    /***********************************************************************
     * ddr backupmode end
     ***********************************************************************/
#ifdef DDR_BACKUPMODE
    if (ddrBackup != 0x0U)
    {
        NOTICE("[WARM_BOOT]\n");
    }
    else
    {
        NOTICE("[COLD_BOOT]\n");
    }

    err = R_DRAM_Update_Boot_Status(ddrBackup);
    if (err != 0x0U)
    {
        NOTICE("[BOOT_STATUS_UPDATE_ERROR]\n");
        return INITDRAM_ERR_I;
    }
#endif /* DDR_BACKUPMODE */
    MSG_LF("init_ddr:1\n");

    /***********************************************************************
     * dbsc register set
     ***********************************************************************/
    r_dbsc_regset();

    MSG_LF("init_ddr:2\n");

    /***********************************************************************
     * dfi_init_start (start ddrphy) & exec pi_training
     ***********************************************************************/
    phytrainingok = r_pi_training();

    if (ddr_phyvalid != phytrainingok)
    {
        MSG_LF("init_ddr_error:1\n");
        return (phytrainingok);
    }

    MSG_LF("init_ddr:3\n");

    /***********************************************************************
     * frequency selection change (F1->F2)
     ***********************************************************************/
    r_ddr_setval_ach(PHY_FREQ_SEL_INDEX,        0x01U);
    r_ddr_setval_ach(PHY_FREQ_SEL_MULTICAST_EN, 0x00U);
#if (RCAR_MEDIUM_FREQUENCY_TRAINING_MODE == 1U)
    if (med_freq_en == 0x01U)
    {
        r_ddr_setval_ach(PI_WDQLVL_VREF_EN, 0x01U);
        r_ddr_setval_ach(PI_FREQ_MAP,       0x04U);
        r_ddr_setval_ach(PI_INIT_WORK_FREQ, 0x02U);
    }
#endif /* (RCAR_MEDIUM_FREQUENCY_TRAINING_MODE == 1U) */

    /***********************************************************************
     * write leveling cycle adjust
     ***********************************************************************/
    r_write_leveling_adjust();

    MSG_LF("init_ddr:4\n");

    /***********************************************************************
     * exec write leveling & read gate training
     ***********************************************************************/
    phytrainingok = r_wl_gt_training();

    if (ddr_phyvalid != phytrainingok)
    {
        MSG_LF("init_ddr_error:2\n");
        return (phytrainingok);
    }

    MSG_LF("init_ddr:5\n");

    /***********************************************************************
     * exec write dca training
     ***********************************************************************/
    r_write_dca();

    MSG_LF("init_ddr:6\n");

    /***********************************************************************
     * exec dram dca training
     ***********************************************************************/
    phytrainingok = r_dramdca_training();

    if (ddr_phyvalid != phytrainingok)
    {
        MSG_LF("init_ddr_error:3\n");
        return (phytrainingok);
    }

    MSG_LF("init_ddr:7\n");

    /***********************************************************************
     * exec write leveling
     ***********************************************************************/
    phytrainingok = r_write_leveling();

    if (ddr_phyvalid != phytrainingok)
    {
        MSG_LF("init_ddr_error:4\n");
        return (phytrainingok);
    }

    MSG_LF("init_ddr:8\n");

    /***********************************************************************
     * exec manual write dca training
     ***********************************************************************/
    r_manual_write_dca();

    MSG_LF("init_ddr:9\n");

    /***********************************************************************
     * exec read gate training
     ***********************************************************************/
    phytrainingok = r_read_gate_training();

    if (ddr_phyvalid != phytrainingok)
    {
        MSG_LF("init_ddr_error:5\n");
        return (phytrainingok);
    }

    MSG_LF("init_ddr:10\n");

    /***********************************************************************
     * exec read vref training
     ***********************************************************************/
    phytrainingok = r_read_vref_training();

    if (ddr_phyvalid != phytrainingok)
    {
        MSG_LF("init_ddr_error:6\n");
        return (phytrainingok);
    }

    MSG_LF("init_ddr:11\n");

    /***********************************************************************
     * exec read dq & write dq training with best vref
     ***********************************************************************/
    phytrainingok = r_read_write_training();

    if (ddr_phyvalid != phytrainingok)
    {
        MSG_LF("init_ddr_error:7\n");
        return (phytrainingok);
    }

    MSG_LF("init_ddr:12\n");

    /***********************************************************************
     * correct rddq training result & exec read dq training
     ***********************************************************************/
    phytrainingok = r_read_training();

    if (ddr_phyvalid != phytrainingok)
    {
        MSG_LF("init_ddr_error:8\n");
        return (phytrainingok);
    }

    MSG_LF("init_ddr:13\n");

    /***********************************************************************
     * PER_CS_TRAINING_MULTICAST SET (disable)
     ***********************************************************************/
    r_ddr_setval_ach_as(PHY_PER_CS_TRAINING_MULTICAST_EN, 0x00U);

    /***********************************************************************
     * Restore PI_SEQ_ARRAY for DFS
     ***********************************************************************/
#if (RCAR_MEDIUM_FREQUENCY_TRAINING_MODE == 1U)
    if (med_freq_en == 0x01U)
    {
        r_ddr_setval_ach(PI_SEQ_ARRAY_29, 0x11910048U);
        r_ddr_setval_ach(PI_SEQ_ARRAY_64, 0x1810214AU);
        r_ddr_setval_ach(PI_SEQ_ARRAY_65, 0x1810314BU);
        r_ddr_setval_ach(PI_SEQ_ARRAY_66, 0x18101149U);
        r_ddr_setval_ach(PI_SEQ_ARRAY_67, 0x18061180U);
        r_ddr_setval_ach(PI_SEQ_ARRAY_68, 0x18067FC0U);
        r_ddr_setval_ach(PI_SEQ_ARRAY_69, 0x18101149U);
        r_ddr_setval_ach(PI_SEQ_ARRAY_70, 0x18051200U);
        r_ddr_setval_ach(PI_SEQ_ARRAY_71, 0x19A11C15U);
        r_ddr_setval_ach(PI_SEQ_ARRAY_72, 0x19A11009U);
        r_ddr_setval_ach(PI_FREQ_MAP,     0x07U);
    }
#endif /* (RCAR_MEDIUM_FREQUENCY_TRAINING_MODE == 1U) */
    MSG_LF("init_ddr:14\n");

    /***********************************************************************
     * setup DDR mode registers
     ***********************************************************************/
    /* MRS */
    r_ddr_register_set();

    /* MRR */
    r_ddr_register_read();

    MSG_LF("init_ddr:15\n");

    /***********************************************************************
     * training complete, setup dbsc
     ***********************************************************************/
    r_dbsc_regset_post();

    MSG_LF("init_ddr:16\n");

    /***********************************************************************
     * lock phy
     ***********************************************************************/
    /* Lock DDRPHY register */
    r_foreach_vch((ch))
    {
        mmio_write_32(DBSC_DBPDLK(ch), 0x00000000U);
    }

    return phytrainingok;
}

/*******************************************************************************
 *    DDR Initialize entry
 ******************************************************************************/
uint32_t R_DRAM_Init(void)
{
    uint32_t ch, cs;
    uint32_t dataL;
    uint32_t failcount;

    r_dbsc_write_32(DBSC_DBSYSCNT0,  0x00001234U);
    r_dbsc_write_32(DBSC_DBSYSCNT0A, 0x00001234U);

    /***********************************************************************
     * Judge product and cut
     ***********************************************************************/
    Prr_Product = mmio_read_32(PRR) & PRR_PRODUCT_MASK;
    Prr_Cut = mmio_read_32(PRR) & PRR_CUT_MASK;

    if (Prr_Product != PRR_PRODUCT_V4M)
    {
        FATAL_MSG("DDR:Unknown Product\n");
        return 0xFFU;
    }
    else if (Prr_Cut > 0xFFU)
    {
        FATAL_MSG("DDR:Unknown Product Version\n");
        return 0xFFU;
    }
    else
    {
        ; /* Nothing */
    }

    /***********************************************************************
     * Judge board type
     ***********************************************************************/
    BOARDTYPE = r_boardcnf_get_brd_type();
    if (BOARDTYPE >= BOARDNUM)
    {
        FATAL_MSG("DDR:Unknown Board\n");
        return 0xFFU;
    }

    Boardcnf = (const st_boardcnf_t *)&boardcnfs[BOARDTYPE];

    ddr_phyvalid = (uint32_t)(Boardcnf->bdcfg_phyvalid);

    max_density = 0U;

    for (cs = 0U; cs < CS_CNT; cs++)
    {
        ch_have_this_cs[cs] = 0U;
    }

    r_foreach_ech((ch))
    {
        for (cs = 0U; cs < CS_CNT; cs++)
        {
            ddr_density[ch][cs] = 0xFFU;
        }
    }

    r_foreach_vch((ch))
    {
        for (cs = 0U; cs < CS_CNT; cs++)
        {
            dataL = (uint32_t)(Boardcnf->ch[ch].bdcfg_ddr_density[cs]);
            ddr_density[ch][cs] = dataL;
            if (dataL == 0xFFU)
            {
                continue;
            }
            if (dataL > max_density)
            {
                max_density = dataL;
            }
            ch_have_this_cs[cs] |= (1U << ch);
        }
    }

    /***********************************************************************
     * Judge board clock frequency (in MHz)
     ***********************************************************************/
    r_boardcnf_get_brd_clk(BOARDTYPE, &brd_clk, &brd_clkdiv);
    if (((0x01U << 14) & mmio_read_32(RST_MODEMR0)) != 0x0U)
    {
        brd_clkdiva = 1U;
    }
    else
    {
        brd_clkdiva = 0U;
    }

    /***********************************************************************
     * Judge ddr operating frequency clock(in Mbps)
     ***********************************************************************/
    r_boardcnf_get_ddr_mbps(BOARDTYPE, &ddr_mbps, &ddr_mbpsdiv, &sscg, &med_freq_en);

    ddr_mul     = CLK_DIV(ddr_mbps, ddr_mbpsdiv * 2U, brd_clk, brd_clkdiv * (brd_clkdiva + 1U));
    ddr_mul_low = CLK_DIV(6400U,             1U * 2U, brd_clk, brd_clkdiv * (brd_clkdiva + 1U));

    if (ddr_mbps >= (PLL3_MEDIUM_FREQUENCY_THRESHOLD * ddr_mbpsdiv * 4U))
    {
        /* divider N = 8 */
        ddr_medium_div = 0x04U;
    }
    else if (ddr_mbps >= (PLL3_MEDIUM_FREQUENCY_THRESHOLD * ddr_mbpsdiv * 3U))
    {
        /* divider N = 6 */
        ddr_medium_div = 0x03U;
    }
    else
    {
        /* divider N = 4 */
        ddr_medium_div = 0x02U;
    }

    if ((sscg == 0x1U) || (sscg == 0x3U))
    {
        ddr_mul_reg = ddr_mul_low - 2U;
    }
    else
    {
        ddr_mul_reg = ddr_mul_low;
    }

#if (RCAR_PLL3_FRAC_MODE == 1U)
    ddr_mul_nf = ((8U * ddr_mbps * brd_clkdiv * (brd_clkdiva + 1U)) / (ddr_mbpsdiv * brd_clk * 2U)) - (8U * (ddr_mul / 2U) * 2U);
#else
    ddr_mul_nf = 0x00U;
#endif /* (RCAR_PLL3_FRAC_MODE == 1U) */

    dataL = 0x03U & (mmio_read_32(RST_MODEMR0) >> 13);
    bus_clk = 0U;
    bus_clkdiv = 0U;

    switch (dataL)
    {
        case 0U:
            bus_clk = brd_clk * 0x18U;
            bus_clkdiv = brd_clkdiv;
            break;
        case 1U:
            bus_clk = brd_clk * 0x14U;
            bus_clkdiv = brd_clkdiv;
            break;
        case 2U:
            /* Not supported */
            bus_clk = brd_clk * 0x20U;
            bus_clkdiv = brd_clkdiv * 2U;
            break;
        case 3U:
            bus_clk = brd_clk * 0x18U;
            bus_clkdiv = brd_clkdiv * 2U;
            break;
        default:
            bus_clk = brd_clk * 0x18U;
            bus_clkdiv = brd_clkdiv * 2U;
            break;
    }

    /***********************************************************************
     * Adjust tccd
     ***********************************************************************/
    ddr_tccd = 2U;

#if (RCAR_MEDIUM_FREQUENCY_TRAINING_MODE == 1U)
    if (med_freq_en == 0x01U)
    {
        NOTICE("DDR%d/%d(%s)\n", ddr_mbps / ddr_mbpsdiv, ddr_mbps / ddr_mbpsdiv / ddr_medium_div, RCAR_DDR_VERSION);
    }
    else
    {
        NOTICE("DDR%d(%s)\n", ddr_mbps / ddr_mbpsdiv, RCAR_DDR_VERSION);
    }
#else
    NOTICE("DDR%d(%s)\n", ddr_mbps / ddr_mbpsdiv, RCAR_DDR_VERSION);
#endif /* (RCAR_MEDIUM_FREQUENCY_TRAINING_MODE == 1U) */

    MSG_LF("Start\n");

    /***********************************************************************
     * initialize DDR
     ***********************************************************************/
    dataL = r_init_ddr();
    if (dataL == ddr_phyvalid)
    {
        failcount = 0U;
    }
    else
    {
        failcount = 1U;
    }

    NOTICE("..%d\n", failcount);

    r_dbsc_write_32(DBSC_DBSYSCNT0,  0x00000000U);
    r_dbsc_write_32(DBSC_DBSYSCNT0A, 0x00000000U);

    if (failcount == 0U)
    {
        return INITDRAM_OK;
    }
    else
    {
        return INITDRAM_NG;
    }
}

#if (RCAR_PERIODIC_TRAINING_SEPARATE_MODE != 0U)
void r_set_pi_rdlvl_interval(void)
{
    uint32_t ch;
    uint32_t dataL;
    uint32_t ctrl_clk;
    uint32_t clk_count;
    uint32_t phymster_req_interval;

    r_dbsc_write_32(DBSC_DBSYSCNT0,  0x00001234U);
    r_dbsc_write_32(DBSC_DBSYSCNT0A, 0x00001234U);

    /* Unlock DDRPHY register */
    r_foreach_vch((ch))
    {
        mmio_write_32(DBSC_DBPDLK(ch), 0x0000A55AU);
    }

    /* PI_INT_STATUS clear */
    r_foreach_vch((ch))
    {
        r_ddr_setval(ch, PI_INT_ACK_0, 0xFFFFFFFFU);
        r_ddr_setval(ch, PI_INT_ACK_1, 0x01U);
    }

    /* wait wdq training done */
    (void)r_pi_int_ack_0_assert(29U);

    /* set pi_rdlvl_interval */
    phymster_req_interval = PERIODIC_TRAINING_INTERVAL - 3000U;
    clk_count = 1024U - (r_ddrtbl_getval_pi(DDR_PI_REGSET, PI_LONG_COUNT_MASK) * 32U);
    ctrl_clk = ddr_mbps / ddr_mbpsdiv / 8U;
    dataL = phymster_req_interval * ctrl_clk / clk_count;
    r_ddr_setval_ach(PI_RDLVL_INTERVAL, dataL);

    /* Lock DDRPHY register */
    r_foreach_vch((ch))
    {
        mmio_write_32(DBSC_DBPDLK(ch), 0x00000000U);
    }

    r_dbsc_write_32(DBSC_DBSYSCNT0,  0x00000000U);
    r_dbsc_write_32(DBSC_DBSYSCNT0A, 0x00000000U);
}
#endif /* (RCAR_PERIODIC_TRAINING_SEPARATE_MODE != 0U) */

/*******************************************************************************
 * END
 ******************************************************************************/
