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/*******************************************************************************
 * DESCRIPTION   : Registers of SDMAC on ICUMX
 ******************************************************************************/

#ifndef SDMAC_REGISTER_H__
#define SDMAC_REGISTER_H__

/* SDMAC on ICUMX base address */
#define ICUMX_SDMAC_BASE    (0xFF600000U)

/* Channel offset address */
#define ICUMX_SDMAC_CH0      (0x80U * 0U)
#define ICUMX_SDMAC_CH1      (0x80U * 1U)
#define ICUMX_SDMAC_CH2      (0x80U * 2U)

/* SDMAC Interrupt Status Register */
#define ICUMX_DMAISTA       (ICUMX_SDMAC_BASE + 0x0020U)
/* SDMAC Operation Register */
#define ICUMX_DMAOR         (ICUMX_SDMAC_BASE + 0x0060U)
/* SDMAC Channel Reset Register */
#define ICUMX_DMACHRST      (ICUMX_SDMAC_BASE + 0x0080U)
/* SDMAC Source Address Register */
#define ICUMX_DMASAR_0      (ICUMX_SDMAC_BASE + 0x2000U + ICUMX_SDMAC_CH0)
#define ICUMX_DMASAR_1      (ICUMX_SDMAC_BASE + 0x2000U + ICUMX_SDMAC_CH1)
#define ICUMX_DMASAR_2      (ICUMX_SDMAC_BASE + 0x2000U + ICUMX_SDMAC_CH2)
/* SDMAC Destination Address Register */
#define ICUMX_DMADAR_0      (ICUMX_SDMAC_BASE + 0x2004U + ICUMX_SDMAC_CH0)
#define ICUMX_DMADAR_1      (ICUMX_SDMAC_BASE + 0x2004U + ICUMX_SDMAC_CH1)
#define ICUMX_DMADAR_2      (ICUMX_SDMAC_BASE + 0x2004U + ICUMX_SDMAC_CH2)
/* SDMAC Transfer Size Register */
#define ICUMX_DMATSR_0      (ICUMX_SDMAC_BASE + 0x2008U + ICUMX_SDMAC_CH0)
#define ICUMX_DMATSR_1      (ICUMX_SDMAC_BASE + 0x2008U + ICUMX_SDMAC_CH1)
#define ICUMX_DMATSR_2      (ICUMX_SDMAC_BASE + 0x2008U + ICUMX_SDMAC_CH2)
/* SDMAC Transfer Mode Register */
#define ICUMX_DMATMR_0      (ICUMX_SDMAC_BASE + 0x2010U + ICUMX_SDMAC_CH0)
#define ICUMX_DMATMR_1      (ICUMX_SDMAC_BASE + 0x2010U + ICUMX_SDMAC_CH1)
#define ICUMX_DMATMR_2      (ICUMX_SDMAC_BASE + 0x2010U + ICUMX_SDMAC_CH2)
/* SDMAC Channel Control Register */
#define ICUMX_DMACHCR_0     (ICUMX_SDMAC_BASE + 0x2014U + ICUMX_SDMAC_CH0)
#define ICUMX_DMACHCR_1     (ICUMX_SDMAC_BASE + 0x2014U + ICUMX_SDMAC_CH1)
#define ICUMX_DMACHCR_2     (ICUMX_SDMAC_BASE + 0x2014U + ICUMX_SDMAC_CH2)
/* SDMAC Channel Status Register */
#define ICUMX_DMACHSTA_0    (ICUMX_SDMAC_BASE + 0x2018U + ICUMX_SDMAC_CH0)
#define ICUMX_DMACHSTA_1    (ICUMX_SDMAC_BASE + 0x2018U + ICUMX_SDMAC_CH1)
#define ICUMX_DMACHSTA_2    (ICUMX_SDMAC_BASE + 0x2018U + ICUMX_SDMAC_CH2)
/* SDMAC Channel Flag Clear Register */
#define ICUMX_DMACHFCR_0    (ICUMX_SDMAC_BASE + 0x201CU + ICUMX_SDMAC_CH0)
#define ICUMX_DMACHFCR_1    (ICUMX_SDMAC_BASE + 0x201CU + ICUMX_SDMAC_CH1)
#define ICUMX_DMACHFCR_2    (ICUMX_SDMAC_BASE + 0x201CU + ICUMX_SDMAC_CH2)
/* SDMAC Resource Select Register */
#define ICUMX_DMARS_1       (ICUMX_SDMAC_BASE + 0x2040U + ICUMX_SDMAC_CH1)
#define ICUMX_DMARS_2       (ICUMX_SDMAC_BASE + 0x2040U + ICUMX_SDMAC_CH2)

#endif /* SDMAC_REGISTER_H__ */
