/*
 * Copyright (c) 2015-2021, Renesas Electronics Corporation
 * All rights reserved.
 */

/******************************************************************************
 * @file          protection_setting.c
 * - Version      : 0.01
 * @brief         Initial setting process of security setting.
 * .
 *****************************************************************************/
/******************************************************************************
 * History : DD.MM.YYYY Version  Description
 *         : 29.05.2020 0.01     First Release
 *****************************************************************************/

#include <arm_gic.h>
#include <gic_v2.h>
#include "axi_register.h"
#include "protection_setting.h"
#include "mmio.h"
#include "micro_wait.h"
#include "rcar_def.h"
#include "debug.h"

#define CR7_GICD_CTLR       (GICD_BASE + GICD_CTLR)
#define CR7_GICD_IGROUPR    (GICD_BASE + GICD_IGROUPR)
#define CR7_GICD_ISENABLER  (GICD_BASE + GICD_ISENABLER)
#define CR7_GICD_IPRIORITYR (GICD_BASE + GICD_IPRIORITYR)
#define CR7_GICD_ITARGETSR  (GICD_BASE + GICD_ITARGETSR)
#define CR7_GICC_CTLR       (GICC_BASE + GICC_CTLR)

#define TARGET_CPU      (0x01U)

#define SPI_NUM     (512U)

/* LIFEC0 (SECURITY) base address */
#define LIFEC_SEC_BASE  (0xE6110000U)

/* Security attribute setting for master ports */
#define SEC_SRC     (LIFEC_SEC_BASE + 0x0008U)

/* SYSC Power control protection register   */
#define RCAR_SYSCPCPR           (0xE618004CU)
#define SYSCPCPR_A3VP           ((uint32_t)0U << 10U)
#define SYSCPCPR_A3VC           ((uint32_t)0U << 9U)
#define SYSCPCPR_A2VC           ((uint32_t)0U << 8U)
#define SYSCPCPR_3DG            ((uint32_t)0U << 7U)
#define SYSCPCPR_CA57SCU        ((uint32_t)0U << 6U)
#define SYSCPCPR_CA57CPU        ((uint32_t)0U << 5U)
#define SYSCPCPR_MP_A3IR        ((uint32_t)0U << 4U)
#define SYSCPCPR_A2IR_A2SC      ((uint32_t)0U << 3U)
#define SYSCPCPR_CR7            ((uint32_t)1U << 2U)
#define SYSCPCPR_CA53SCU        ((uint32_t)1U << 1U)
#define SYSCPCPR_CA53CPU        ((uint32_t)0U << 0U)

/* SRAM/DRAM protection setting */
void axi_security_setting(void)
{
    int32_t     i;
    int32_t     ie;

    /* AXI settings */
static const struct {
    uint32_t    adr;
    uint32_t    val;
} s_axi_reg_setting[] = {

    /* DRAM protection */

    /* AXI dram protected area division */
    {AXI_DPTDIVCR0,     0xEB040020U},
    {AXI_DPTDIVCR1,     0xEB040820U},
    {AXI_DPTDIVCR2,     0xEB041020U},
    {AXI_DPTDIVCR3,     0xEB050000U},
    {AXI_DPTDIVCR4,     0xEB050000U},
    {AXI_DPTDIVCR5,     0xEB050000U},
    {AXI_DPTDIVCR6,     0xEB050000U},
    {AXI_DPTDIVCR7,     0xEB050000U},
    {AXI_DPTDIVCR8,     0xEB050000U},
    {AXI_DPTDIVCR9,     0xEB050000U},
    {AXI_DPTDIVCR10,    0xEB050000U},
    {AXI_DPTDIVCR11,    0xEB050000U},
    {AXI_DPTDIVCR12,    0xEB050000U},
    {AXI_DPTDIVCR13,    0xEB050000U},
    {AXI_DPTDIVCR14,    0xEB050000U},

    /* AXI dram protected area setting */
    {AXI_DPTCR0,        0xEB00BBBBU},
    {AXI_DPTCR1,        0xEB00ABABU},
    {AXI_DPTCR2,        0xEB00EBEBU},
    {AXI_DPTCR3,        0xEB00BBBBU},
    {AXI_DPTCR4,        0xEB000000U},
    {AXI_DPTCR5,        0xEB000000U},
    {AXI_DPTCR6,        0xEB000000U},
    {AXI_DPTCR7,        0xEB000000U},
    {AXI_DPTCR8,        0xEB000000U},
    {AXI_DPTCR9,        0xEB000000U},
    {AXI_DPTCR10,       0xEB000000U},
    {AXI_DPTCR11,       0xEB000000U},
    {AXI_DPTCR12,       0xEB000000U},
    {AXI_DPTCR13,       0xEB000000U},
    {AXI_DPTCR14,       0xEB000000U},
    {AXI_DPTCR15,       0xEB000000U},


    /* SRAM ptotection */

    /* AXI sram protected area division */
    {AXI_SPTDIVCR0,     0xEB0E6350U},
    {AXI_SPTDIVCR1,     0xEB0E6370U},
    {AXI_SPTDIVCR2,     0xEB0E6370U},
    {AXI_SPTDIVCR3,     0xEB0E6370U},
    {AXI_SPTDIVCR4,     0xEB0E6370U},
    {AXI_SPTDIVCR5,     0xEB0E6370U},
    {AXI_SPTDIVCR6,     0xEB0E6370U},
    {AXI_SPTDIVCR7,     0xEB0E6370U},
    {AXI_SPTDIVCR8,     0xEB0E6370U},
    {AXI_SPTDIVCR9,     0xEB0E6370U},
    {AXI_SPTDIVCR10,    0xEB0E6370U},
    {AXI_SPTDIVCR11,    0xEB0E6370U},
    {AXI_SPTDIVCR12,    0xEB0E6370U},
    {AXI_SPTDIVCR13,    0xEB0E6370U},
    {AXI_SPTDIVCR14,    0xEB0E6370U},

    /* AXI sram protected area setting */
    {AXI_SPTCR0,        0xEB00ABABU},
    {AXI_SPTCR1,        0xEB00DFDFU},
    {AXI_SPTCR2,        0xEB000000U},
    {AXI_SPTCR3,        0xEB000000U},
    {AXI_SPTCR4,        0xEB000000U},
    {AXI_SPTCR5,        0xEB000000U},
    {AXI_SPTCR6,        0xEB000000U},
    {AXI_SPTCR7,        0xEB000000U},
    {AXI_SPTCR8,        0xEB000000U},
    {AXI_SPTCR9,        0xEB000000U},
    {AXI_SPTCR10,       0xEB000000U},
    {AXI_SPTCR11,       0xEB000000U},
    {AXI_SPTCR12,       0xEB000000U},
    {AXI_SPTCR13,       0xEB000000U},
    {AXI_SPTCR14,       0xEB000000U},
    {AXI_SPTCR15,       0xEB000000U}

};


    i = 0;
    ie = (int32_t)(sizeof(s_axi_reg_setting) / sizeof(s_axi_reg_setting[0]));
    for (; i < ie; i++)
    {
        mmio_write_32((uintptr_t)s_axi_reg_setting[i].adr,
            s_axi_reg_setting[i].val);

    }

    micro_wait(10U);        /* 10us wait */
    return;
}
/* End of function axi_security_setting */

void gic_security_setting(void)
{
    gicc_write_pmr(GICC_BASE, GIC_PRI_MASK);
    return;
}
/* End of function gic_security_setting */

/* System Controller setting */
void sysc_security_setting(void)
{
    mmio_write_32(RCAR_SYSCPCPR, SYSCPCPR_A3VP
                    | SYSCPCPR_A3VC
                    | SYSCPCPR_A2VC
                    | SYSCPCPR_3DG
                    | SYSCPCPR_CA57SCU
                    | SYSCPCPR_CA57CPU
                    | SYSCPCPR_MP_A3IR
                    | SYSCPCPR_A2IR_A2SC
                    | SYSCPCPR_CR7
                    | SYSCPCPR_CA53SCU
                    | SYSCPCPR_CA53CPU);

    return;
}
/* End of function sysc_security_setting */

