/*
 * Copyright (c) 2018 Renesas Electronics Corporation. All rights reserved.
 */

;# W0-W30 : 32bit Register (W30=Link Register)
;# X0-X30 : 64bit Register (X30=Link Register)
;# WZR    : 32bit Zero Register
;# XZR    : 64bit Zero Register
;# WSP    : 32bit Stack Pointer
;# SP     : 64bit Stack Pointer

	.INCLUDE		"boot_mon.h"
	.ALIGN	4

;# Initialize registers
Register_init:
	LDR		X0, =0
	LDR		X1, =0
	LDR		X2, =0
	LDR		X3, =0
	LDR		X4, =0
	LDR		X5, =0
	LDR		X6, =0
	LDR		X7, =0
	LDR		X8, =0
	LDR		X9, =0
	LDR		X10, =0
	LDR		X11, =0
	LDR		X12, =0
	LDR		X13, =0
	LDR		X14, =0
	LDR		X15, =0
	LDR		X16, =0
	LDR		X17, =0
	LDR		X18, =0
	LDR		X19, =0
	LDR		X20, =0
	LDR		X21, =0
	LDR		X22, =0
	LDR		X23, =0
	LDR		X24, =0
	LDR		X25, =0
	LDR		X26, =0
	LDR		X27, =0
	LDR		X28, =0
	LDR		X29, =0
	LDR		X30, =0

Set_EnableRAM:
;#	LDR		X0, =0xE67F0018
;#	LDR		W1, =0x00000001			;#Enable  DRAM/SECRAM/PUBRAM
;#	STR		W1, [X0]

    MRS X0, CurrentEL
    CMP X0, #0x0000000C
    BEQ current_EL3


current_EL1:
;# Loader
    LDR x0, =__STACKS_END__
;#    MSR SP_EL0,x0
;#    MSR SP_EL1,x0
;#    MSR SP_EL2,x0
    MOV sp,x0
    MOV x0, #0x50000000
    MSR ELR_EL1,x0
;#    MSR ELR_EL2,x0
;#    MSR ELR_EL3,x0
	MOV x0, #0x03C5
    MSR SPSR_EL1,x0
;#    MSR SPSR_EL2,x0
;#    MSR SPSR_EL3,x0

;# Enable cache
;#	mov x1, #(SCTLR_I_BIT | SCTLR_A_BIT | SCTLR_SA_BIT)
	mrs x0, sctlr_el1
	orr x0, x0, #(0x1 << 12)
	orr x0, x0, #(0x1 <<  1)
	orr x0, x0, #(0x1 <<  3)
	msr sctlr_el1, x0
	isb
	b bss_clr

current_EL3:
;# Loader
    LDR x0, =__STACKS_END__
;#    MSR SP_EL0,x0
;#    MSR SP_EL1,x0
;#    MSR SP_EL2,x0
    MOV sp,x0
    MOV x0, #0xE38
    MSR SCR_EL3, x0
    MOV x0, #0x44100000
;#    MSR ELR_EL1,x0
;#    MSR ELR_EL2,x0
    MSR ELR_EL3,x0
    MOV x0, #0x03C5
;#    MSR SPSR_EL1,x0
;#    MSR SPSR_EL2,x0
    MSR SPSR_EL3,x0

;# Board Initialize
.ifdef Area0Boot

Init_set_WDT:
	LDR		W0, =RWDT_RWTCSRA
	LDR		W1, =0xA5A5A500				;#Timer disabled
	STR		W1, [X0]

Init_set_SYSWDT:
	LDR		W0, =SYSWDT_WTCSRA
	LDR		W1, =0xA5A5A500				;#Timer  disabled (Enable -> disabled)
	STR		W1, [X0]

.endif



;# Enable cache
;#	mov x1, #(SCTLR_I_BIT | SCTLR_A_BIT | SCTLR_SA_BIT)
	mrs x0, sctlr_el3
	orr x0, x0, #(0x1 << 12)
	orr x0, x0, #(0x1 <<  1)
	orr x0, x0, #(0x1 <<  3)
	msr sctlr_el3, x0
	isb


	/* clear bss section */
bss_clr:
	mov	X0, #0x0
	ldr	X1, =__BSS_START__
	ldr	X2, =__BSS_SIZE__
bss_loop:
	subs	X2, X2, #4
	bcc	bss_end
	str	W0, [X1, X2]
	b	bss_loop
bss_end:

.ifdef Area0Boot
	/* copy data section */
	ldr	X0, =__DATA_COPY_START__
	ldr	X1, =__DATA_START__
	ldr	X2, =__DATA_SIZE__
data_loop:
	subs	X2, X2, #4
	bcc	data_end
	ldr	W3, [X0, X2]
	str	W3, [X1, X2]
	b	data_loop
.endif

data_end:

;#	BL InitScif

	BL		Main

	mov	X1, #0x50000000
	BR	X1

	.END

