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/*******************************************************************************
 * DESCRIPTION   : Image load function for eMMC header
 ******************************************************************************/
/******************************************************************************
 * @file          image_load_emmc.h
 * - Version      : 0.05
 * @brief         Access protection setting driver.
 * .
 *****************************************************************************/
/******************************************************************************
 * History : DD.MM.YYYY Version  Description
 *         : 02.02.2022 0.01     First Release
 *         : 17.02.2022 0.02     Support AArch32
 *         : 10.05.2022 0.03     Defined value integration
 *                               Change the argument type of get_part_num_in_cert
 *                               Added argument check
 *                               Changed define name
 *                               Change log output
 *                               Change the direct value reference
 *                               Remove Prototype
 *         : 08.07.2022 0.04     Change log output
 *                               Adds the defined used in the emmc_trans_data argument
 *         : 31.10.2022 0.05     License notation change.
 *****************************************************************************/

#ifndef LOAD_IMAGE_EMMC_H_
#define LOAD_IMAGE_EMMC_H_

#include <image_load.h>
#include <log.h>

/* define */
/* eMMC */
#define CX_EMMC_TOP            (0x00000000U)
#define CX_EMMC_BOOT_PART_SIZE (31U * 1024U * 1024U)    /* 31MB */
#define CX_EMMC_END            ((CX_EMMC_TOP + CX_EMMC_BOOT_PART_SIZE) - 1U)
#define SRC_TOP (CX_EMMC_TOP)

/* For eMMC */
#define CX_EMMC_SECTOR_SIZE_SHIFT           (9U)           /* 512 = 2^9 */
#define CX_EMMC_SECTOR_SIZE                 (512U)
#define CX_EMMC_CONTENT_CERT_ADDR           (0x00240000U)
#define CX_EMMC_CONTENT_CERT_SECTOR_NUMBER  (CX_EMMC_CONTENT_CERT_ADDR >> CX_EMMC_SECTOR_SIZE_SHIFT)

/* A side certificate setting */
/* RT-SRAM Offset */
#define SEC_BOOT_KEY_CERT_OFFSET	(0x00001000U)
#define SEC_DEBUG_SEC_CERT_OFFSET		(0x00006000U)

/* A side RT-SRAM physical address */
/* RT-SRAM(0xEB200000) + CERT_OFFSET */
#define SEC_BOOT_KEY_CERT_ADDR		(ADDR_RT_SRAM_TOP + SEC_BOOT_KEY_CERT_OFFSET)

/* A/B side certificate setting */
/* Boot side Offset */
#define CERT_OFFSET_2ND			(0x8000U)
	
/* A/B side RT-SRAM physical address */
/* RT-SRAM(0xEB200000) + CERT_OFFSET (+ 2nd OFFSET)*/
#define GET_SEC_BOOT_KEY_CERT_ADDR(a)	((SEC_BOOT_KEY_CERT_ADDR) + ((CERT_OFFSET_2ND) * (a)))

#define SEC_DEBUG_CERT_SIZE		(6396U)


static inline void load_image_info_print_for_emmc(LOAD_INFO* li)
{

    NOTICE("======== %s image load info ========\n", li->name);
    NOTICE("load address \t= 0x%x\n" "image size \t= 0x%x\n"
        "source address \t= (p:%u)0x%x\n",
        (unsigned int)li->boot_addr, (unsigned int)(li->image_size),
        (unsigned int)li->part_num, (unsigned int)li->src_addr );
}

static inline uint32_t get_part_num_in_cert(uint32_t id)
{
    /* INT30-C Pre confirmation */
    if (UINT32_MAX - id < 1U)
    {
        ERROR("get_part_num_in_cert id error.\n");
        panic;
    }

    return (CONTENT_CERT_DEST_ADDR + ((id + 1U) * 0x10U));
}

#endif /* LOAD_IMAGE_EMMC_H_ */

