/*******************************************************************************
 * Copyright (c) 2018-2021 Renesas Electronics Corporation. All rights reserved.
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 *
 * This software is provided as reference/sample code under the license
 * agreement between Renesas Electronics Corporation and licensee (the
 * "License Agreement") and shall be treated as specified in the License
 * Agreement.
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 ******************************************************************************/

/*******************************************************************************
 * DESCRIPTION   : CPG register header
 ******************************************************************************/

#ifndef CPG_REGISTER_H__
#define CPG_REGISTER_H__

#include <remap_register.h>

/* CPG base address */
/* 0xE6150000 */
#define CPG_BASE    (BASE_CPG_ADDR)

/* CPG write protect */
#define CPG_CPGWPR      (CPG_BASE + 0x0900U)
/* CPG write protect control */
#define CPG_CPGWPCR     (CPG_BASE + 0x0904U)

#define CPG_MSTPSR0     (CPG_BASE + 0x0030U)    /* Module stop status register 0 */
#define CPG_MSTPSR1     (CPG_BASE + 0x0038U)    /* Module stop status register 1 */
#define CPG_MSTPSR2     (CPG_BASE + 0x0040U)    /* Module stop status register 2 */
#define CPG_MSTPSR3     (CPG_BASE + 0x0048U)    /* Module stop status register 3 */
#define CPG_MSTPSR4     (CPG_BASE + 0x004CU)    /* Module stop status register 4 */
#define CPG_MSTPSR5     (CPG_BASE + 0x003CU)    /* Module stop status register 5 */
#define CPG_MSTPSR6     (CPG_BASE + 0x01C0U)    /* Module stop status register 6 */
#define CPG_MSTPSR7     (CPG_BASE + 0x01C4U)    /* Module stop status register 7 */
#define CPG_MSTPSR8     (CPG_BASE + 0x09A0U)    /* Module stop status register 8 */
#define CPG_MSTPSR9     (CPG_BASE + 0x09A4U)    /* Module stop status register 9 */
#define CPG_MSTPSR10    (CPG_BASE + 0x09A8U)    /* Module stop status register 10 */
#define CPG_MSTPSR11    (CPG_BASE + 0x09ACU)    /* Module stop status register 11 */

/* CPG (Realtime) registers */
#define CPG_RMSTPCR0    (CPG_BASE + 0x0110U)    /* Realtime Module Stop Control Register 0 */
#define CPG_RMSTPCR1    (CPG_BASE + 0x0114U)    /* Realtime Module Stop Control Register 1 */
#define CPG_RMSTPCR2    (CPG_BASE + 0x0118U)    /* Realtime Module Stop Control Register 2 */
#define CPG_RMSTPCR3    (CPG_BASE + 0x011CU)    /* Realtime Module Stop Control Register 3 */
#define CPG_RMSTPCR4    (CPG_BASE + 0x0120U)    /* Realtime Module Stop Control Register 4 */
#define CPG_RMSTPCR5    (CPG_BASE + 0x0124U)    /* Realtime Module Stop Control Register 5 */
#define CPG_RMSTPCR6    (CPG_BASE + 0x0128U)    /* Realtime Module Stop Control Register 6 */
#define CPG_RMSTPCR7    (CPG_BASE + 0x012CU)    /* Realtime Module Stop Control Register 7 */
#define CPG_RMSTPCR8    (CPG_BASE + 0x0980U)    /* Realtime Module Stop Control Register 8 */
#define CPG_RMSTPCR9    (CPG_BASE + 0x0984U)    /* Realtime Module Stop Control Register 9 */
#define CPG_RMSTPCR10   (CPG_BASE + 0x0988U)    /* Realtime Module Stop Control Register 10 */
#define CPG_RMSTPCR11   (CPG_BASE + 0x098CU)    /* Realtime Module Stop Control Register 11 */

/* CPG (System) registers */
#define CPG_SMSTPCR0    (CPG_BASE + 0x0130U)    /* System Module Stop Control Register 0 */
#define CPG_SMSTPCR1    (CPG_BASE + 0x0134U)    /* System Module Stop Control Register 1 */
#define CPG_SMSTPCR2    (CPG_BASE + 0x0138U)    /* System Module Stop Control Register 2 */
#define CPG_SMSTPCR3    (CPG_BASE + 0x013CU)    /* System Module Stop Control Register 3 */
#define CPG_SMSTPCR4    (CPG_BASE + 0x0140U)    /* System Module Stop Control Register 4 */
#define CPG_SMSTPCR5    (CPG_BASE + 0x0144U)    /* System Module Stop Control Register 5 */
#define CPG_SMSTPCR6    (CPG_BASE + 0x0148U)    /* System Module Stop Control Register 6 */
#define CPG_SMSTPCR7    (CPG_BASE + 0x014CU)    /* System Module Stop Control Register 7 */
#define CPG_SMSTPCR8    (CPG_BASE + 0x0990U)    /* System Module Stop Control Register 8 */
#define CPG_SMSTPCR9    (CPG_BASE + 0x0994U)    /* System Module Stop Control Register 9 */
#define CPG_SMSTPCR10   (CPG_BASE + 0x0998U)    /* System Module Stop Control Register 10 */
#define CPG_SMSTPCR11   (CPG_BASE + 0x099CU)    /* System Module Stop Control Register 11 */

/* CPG (SECURITY) registers */
#define CPG_SCMSTPCR0   (CPG_BASE + 0x0B20U)    /* Secure Module Stop Control Register 0 */
#define CPG_SCMSTPCR1   (CPG_BASE + 0x0B24U)    /* Secure Module Stop Control Register 1 */
#define CPG_SCMSTPCR2   (CPG_BASE + 0x0B28U)    /* Secure Module Stop Control Register 2 */
#define CPG_SCMSTPCR3   (CPG_BASE + 0x0B2CU)    /* Secure Module Stop Control Register 3 */
#define CPG_SCMSTPCR4   (CPG_BASE + 0x0B30U)    /* Secure Module Stop Control Register 4 */
#define CPG_SCMSTPCR5   (CPG_BASE + 0x0B34U)    /* Secure Module Stop Control Register 5 */
#define CPG_SCMSTPCR6   (CPG_BASE + 0x0B38U)    /* Secure Module Stop Control Register 6 */
#define CPG_SCMSTPCR7   (CPG_BASE + 0x0B3CU)    /* Secure Module Stop Control Register 7 */
#define CPG_SCMSTPCR8   (CPG_BASE + 0x0B40U)    /* Secure Module Stop Control Register 8 */
#define CPG_SCMSTPCR9   (CPG_BASE + 0x0B44U)    /* Secure Module Stop Control Register 9 */
#define CPG_SCMSTPCR10  (CPG_BASE + 0x0B48U)    /* Secure Module Stop Control Register 10 */
#define CPG_SCMSTPCR11  (CPG_BASE + 0x0B4CU)    /* Secure Module Stop Control Register 11 */

/* CPG (SAFETY) registers */
#define CPG_SAMSTPCR0   (CPG_BASE + 0x0C20U)    /* Safety Module Stop Control Register 0 */
#define CPG_SAMSTPCR1   (CPG_BASE + 0x0C24U)    /* Safety Module Stop Control Register 1 */
#define CPG_SAMSTPCR2   (CPG_BASE + 0x0C28U)    /* Safety Module Stop Control Register 2 */
#define CPG_SAMSTPCR3   (CPG_BASE + 0x0C2CU)    /* Safety Module Stop Control Register 3 */
#define CPG_SAMSTPCR4   (CPG_BASE + 0x0C30U)    /* Safety Module Stop Control Register 4 */
#define CPG_SAMSTPCR5   (CPG_BASE + 0x0C34U)    /* Safety Module Stop Control Register 5 */
#define CPG_SAMSTPCR6   (CPG_BASE + 0x0C38U)    /* Safety Module Stop Control Register 6 */
#define CPG_SAMSTPCR7   (CPG_BASE + 0x0C3CU)    /* Safety Module Stop Control Register 7 */
#define CPG_SAMSTPCR8   (CPG_BASE + 0x0C40U)    /* Safety Module Stop Control Register 8 */
#define CPG_SAMSTPCR9   (CPG_BASE + 0x0C44U)    /* Safety Module Stop Control Register 9 */
#define CPG_SAMSTPCR10  (CPG_BASE + 0x0C48U)    /* Safety Module Stop Control Register 10 */
#define CPG_SAMSTPCR11  (CPG_BASE + 0x0C4CU)    /* Safety Module Stop Control Register 11 */

#define CPG_SRSTCLR2    (CPG_BASE + 0x0948U)    /* Software Reset Clearing Register 2 */

/* APMU */
#define APMU_CA53WUPCR  (CPG_BASE + 0x1010U)    /* Wake-up control register for A53 */
#define APMU_CR7PSTR    (CPG_BASE + 0x3040U)    /* Wake-up control register for A53 */

/* IMP core */
#define ASTPOFFR        (CPG_BASE + 0x0278U)    /* Automatic Module clock stop function off register */

#endif  /* CPG_REGISTER_H__ */
