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#ifndef BOOT_INIT_DRAM_REGDEF
#define BOOT_INIT_DRAM_REGDEF

#if defined(__RH850G3K__)
#include "remap_register.h"
#endif

//! @details The version of DDR code
#define RCAR_DDR_VERSION           "rev.1.10"
//! @details The number of channels V4H has
#define DRAM_CH_CNT                 0x04U
//! @details The number of slices V4H has
#define SLICE_CNT                   0x02U
//! @details The number of chip select V4H has
#define CS_CNT                      0x02U

//! @details for pll setting
#define CLK_DIV(a, diva, b, divb)   (((a) * (divb)) / ((b) * (diva)))

//! @details for ddr density setting
#define DBMEMCONF_REG(d3, row, BG, bank, col, dw)   (((d3) << 30U) | ((row) << 24U) | ((BG) << 20U) | ((bank) << 16U) | ((col) << 8U) | (dw))
//! @details for 16bit value
#define DBMEMCONF_REGD(density)     (DBMEMCONF_REG((density % 2U), (((density+ 1U) / 2U) + (28U - 2U - 2U - 10U - 1U)), 2U, 2U, 10U, 1U))   /* 16bit */

//! @details Kick bit setting CPG PLL3 division
#define CPG_FRQCRD_KICK_BIT         (1U << 31)
//! @details Kick bit to reflect setting CPG PLL3 value
#define CPG_PLL3CR0_KICK_BIT        (1U << 31)
//! @details Status bit to check CPG PLL3 works normally
#define CPG_PLLECR_PLL3ST_BIT       (1U << 11)

#if defined(__RH850G3K__)
//! @details If this bin is processed by RH850G3K, address will be remapped.
#define CPG_BASE    (BASE_CPG_ADDR)
#else
//! @details If this bin is processed by Arm core, address will be "0xE6150000U".
#define CPG_BASE                    (0xE6150000U)
#endif
//! @details 32-bit readable/writable register
#define CPG_CPGWPR                  (CPG_BASE + 0x0000U)
//! @details The register specifies the DDR and DBSC clock (ZB3, ZB3D2,ZB3D4) frequency
#define CPG_FRQCRD0                 (CPG_BASE + 0x080CU)
//! @details PLL Enable Control Register
#define CPG_PLLECR                  (CPG_BASE + 0x0820U)
//! @details The register specifies the integer multiplication ratio
#define CPG_PLL3CR0                 (CPG_BASE + 0x083CU)
//! @details The register specifies the fractional multiplication
#define CPG_PLL3CR1                 (CPG_BASE + 0x08C0U)
//! @details Functional Safety Reset Check Clear Register
#define CPG_FSRCHKCLRR4             (CPG_BASE + 0x0590U)
//! @details Functional Safety Reset Check Set Register
#define CPG_FSRCHKSETR4             (CPG_BASE + 0x0510U)
//! @details Functional Safety Reset Check Register A
#define CPG_FSRCHKRA4               (CPG_BASE + 0x0410U)
//! @details Software Reset Status Register
#define CPG_SRCR4                   (CPG_BASE + 0x2C10U)
//! @details Software Reset Clearing Register
#define CPG_SRSTCLR4                (CPG_BASE + 0x2C90U)

#if defined(__RH850G3K__)
//! @details If this bin is processed by RH850G3K, address will be remapped.
#define RST_BASE    (BASE_RESET_ADDR)
#else
//! @details If this bin is processed by Arm core, address will be 0xE6160000U.
#define RST_BASE                    (0xE6160000U)
#endif
//! @details 32-bit read-only register, which is initialized only by POR.
#define RST_MODEMR0                 (RST_BASE + 0x0000U)
//! @details 32-bit read-only register, which is initialized only by POR.
#define RST_MODEMR1                 (RST_BASE + 0x0004U)

#if defined(__RH850G3K__)
#define OTP_MEM_1_BASE               (BASE_OTP_MEM_ADDR)
#else
#define OTP_MEM_1_BASE               (0xE61BF000U)
#endif
#define OTP_MEM_OTPMONITOR17         (OTP_MEM_1_BASE + 0x0144U)
#define OTP_MEM_PRODUCT_MASK         (0x000000FFU)

/* Product Register */
#define PRR                         (0xFFF00044U)
#define PRR_PRODUCT_MASK            (0x00007F00U)
#define PRR_CUT_MASK                (0x000000FFU)

#define PRR_PRODUCT_V4H             (0x00005C00U)   /* R-Car V4H */

#define PRR_PRODUCT_30              (0x00000020U)    /* ver 3.0 */

/* DBSC registers */
#if defined(__RH850G3K__)
//! @details If this bin is processed by RH850G3K, address will be remapped.
#define DBSC_D_BASE                 (BASE_DBSC_ADDR + 0x14000U)    /* forV4H DBSC0 clk_dbsc region    DBSC1_D_BASE = 0xE67A8000U */
#define DBSC_A_BASE                 (BASE_DBSC_ADDR)            /* forV4H DBSC0 clk_axim region    DBSC1_A_BASE = 0xE6798000U */
#else
//! @details If this bin is processed by RH850G3K, address will be remapped.
#define DBSC_D_BASE                 (0xE67A4000U)   /* forV4H DBSC0 clk_dbsc region    DBSC1_D_BASE = 0xE67A8000U */
#define DBSC_A_BASE                 (0xE6790000U)   /* forV4H DBSC0 clk_axim region    DBSC1_A_BASE = 0xE6798000U */
#endif
//! @details DBSC4 System Configuration Register 0
#define DBSC_DBSYSCONF0         (DBSC_A_BASE + 0x0000U)
//! @details DBSC4 System Configuration Register 1(for DFI domain)
#define DBSC_DBSYSCONF1         (DBSC_D_BASE + 0x0000U)
//! @details DBSC4 System Configuration Register 1(for AXI domain)
#define DBSC_DBSYSCONF1A        (DBSC_A_BASE + 0x0004U)
//! @details DBSC4 System Configuration Register 2
#define DBSC_DBSYSCONF2         (DBSC_D_BASE + 0x0004U)
//! @details PHY type Configuration Register
#define DBSC_DBPHYCONF0         (DBSC_D_BASE + 0x0008U)
//! @details PHY type Configuration Register 2A
#define DBSC_DBSYSCONF2A        (DBSC_A_BASE + 0x0008U)
//! @details Memory Type register (for DFI domain)
#define DBSC_DBMEMKIND          (DBSC_D_BASE + 0x0020U)
//! @details Memory Type register (for AXI domain)
#define DBSC_DBMEMKINDA         (DBSC_A_BASE + 0x0020U)
//! @details SDRAM Configuration setting Register (for DFI domain)
#define DBSC_DBMEMCONF(ch,cs)   (DBSC_D_BASE + 0x0030U + (0x2000U * (ch & 0x02U)) + (0x10U * (ch & 0x01U)) + (0x04U * (cs)))
//! @details SDRAM Configuration setting Register (for AXI domain)
#define DBSC_DBMEMCONFA(ch,cs)  (DBSC_A_BASE + 0x0030U + (0x4000U * (ch & 0x02U)) + (0x10U * (ch & 0x01U)) + (0x04U * (cs)))
//! @details DBSC System Register 0(For DFI Domain)
#define DBSC_DBSYSCNT0          (DBSC_D_BASE + 0x0100U)
//! @details DBSC System Register 0(For AXI Domain)
#define DBSC_DBSYSCNT0A         (DBSC_A_BASE + 0x0100U)
//! @details SDRAM Access Enable Register
#define DBSC_DBACEN             (DBSC_A_BASE + 0x0200U)
//! @details Auto-Refresh Enable Register
#define DBSC_DBRFEN             (DBSC_D_BASE + 0x0204U)
//! @details Manual Command-Issuing Register
#define DBSC_DBCMD              (DBSC_D_BASE + 0x0208U)
//! @details Operation Complition Waiting Register
#define DBSC_DBWAIT             (DBSC_D_BASE + 0x0210U)
//! @details SDRAM Operation Setting Register(for DFI domain)
#define DBSC_DBBL               (DBSC_D_BASE + 0x0400U)
//! @details SDRAM Operation Setting Register(for AXI domain)
#define DBSC_DBBLA              (DBSC_A_BASE + 0x0400U)
//! @details Refresh Configuration Register 1
#define DBSC_DBRFCNF1           (DBSC_D_BASE + 0x0414U)
//! @details Refresh Configuration Register 2
#define DBSC_DBRFCNF2           (DBSC_D_BASE + 0x0418U)
//! @details SDRAM Callibration Configuration Register
#define DBSC_DBCALCNF           (DBSC_D_BASE + 0x0424U)
//! @details DBI Configuration Register
#define DBSC_DBDBICNT           (DBSC_D_BASE + 0x0518U)
//! @details DFI PHY Master Control Register
#define DBSC_DBDFIPMSTRCNF      (DBSC_D_BASE + 0x0520U)
//! @details DFI Control Update Configuration Register
#define DBSC_DBDFICUPDCNF       (DBSC_D_BASE + 0x0540U)
//! @details CAM Unit Operation Setting Register
#define DBSC_DBBCAMDIS          (DBSC_A_BASE + 0x09FCU)
//! @details Read/Write Scheduling Setting Register 1
#define DBSC_DBSCHRW1           (DBSC_A_BASE + 0x1024U)
//! @details Data Transfer Cycle Setting
#define DBSC_DBSCHTR0           (DBSC_A_BASE + 0x1030U)
//! @details SDRAM Timing Register X
#define DBSC_DBTR(x)            (DBSC_D_BASE + 0x0300U + (0x04U * (x)))
//! @details Multirank Operation Setting Register x
#define DBSC_DBRNK(x)           (DBSC_D_BASE + 0x0430U + (0x04U * (x)))
//! @details DFI Status Interface Input Regiser
#define DBSC_DBDFISTAT(ch)      (DBSC_D_BASE + 0x0600U + (0x2000U * (ch & 0x02U)) + (0x40U * (ch & 0x01U)))
//! @details DFI Status Interface Output Regiser
#define DBSC_DBDFICNT(ch)       (DBSC_D_BASE + 0x0604U + (0x2000U * (ch & 0x02U)) + (0x40U * (ch & 0x01U)))
//! @details PHY Unit Control Register 02
#define DBSC_DBPDCNT2(ch)       (DBSC_D_BASE + 0x0618U + (0x2000U * (ch & 0x02U)) + (0x40U * (ch & 0x01U)))
//! @details PHY Unit Lock register
#define DBSC_DBPDLK(ch)         (DBSC_D_BASE + 0x0620U + (0x2000U * (ch & 0x02U)) + (0x40U * (ch & 0x01U)))
//! @details PHY Unit register address
#define DBSC_DBPDRGA(ch)        (DBSC_D_BASE + 0x0624U + (0x2000U * (ch & 0x02U)) + (0x40U * (ch & 0x01U)))
//! @details PHY Unit register access
#define DBSC_DBPDRGD(ch)        (DBSC_D_BASE + 0x0628U + (0x2000U * (ch & 0x02U)) + (0x40U * (ch & 0x01U)))
//! @details PHY Unit Registers Mask for channel
#define DBSC_DBPDRGM(ch)        (DBSC_D_BASE + 0x062CU + (0x2000U * (ch & 0x02U)) + (0x40U * (ch & 0x01U)))
//! @details PHY Status Register0 ch
#define DBSC_DBPDSTAT0(ch)      (DBSC_D_BASE + 0x0630U + (0x2000U * (ch & 0x02U)) + (0x40U * (ch & 0x01U)))
//! @details PHY Status Register1 ch
#define DBSC_DBPDSTAT1(ch)      (DBSC_D_BASE + 0x0634U + (0x2000U * (ch & 0x02U)) + (0x40U * (ch & 0x01U)))
//! @details Interval Setting for scheduler 
#define DBSC_DBSCHFCTST0        (DBSC_A_BASE + 0x1040U)
//! @details Interval Setting for scheduler 
#define DBSC_DBSCHFCTST1        (DBSC_A_BASE + 0x1044U)

#endif /* BOOT_INIT_DRAM_REGDEF */
