/*******************************************************************************
 * DISCLAIMER
 * This software is supplied by Renesas Electronics Corporation and is only
 * intended for use with Renesas products. No other uses are authorized. This
 * software is owned by Renesas Electronics Corporation and is protected under
 * all applicable laws, including copyright laws.
 * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
 * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
 * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
 * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
 * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
 * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
 * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
 * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
 * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
 * Renesas reserves the right, without notice, to make changes to this software
 * and to discontinue the availability of this software. By using this software,
 * you agree to the additional terms and conditions found by accessing the
 * following link:
 * http://www.renesas.com/disclaimer
 * Copyright 2023-2024 Renesas Electronics Corporation All rights reserved.
 *******************************************************************************/

#ifndef DDR_REGDEF_H_
#define DDR_REGDEF_H_

#define PHY_LP4_BOOT_RX_PCLK_CLK_SEL                  0x10031000U
#define PHY_PER_CS_TRAINING_MULTICAST_EN              0x18011006U
#define PHY_PER_CS_TRAINING_INDEX                     0x00011007U
#define PHY_VREF_INITIAL_STEPSIZE                     0x1808100EU
#define PHY_RDLVL_BEST_THRSHLD                        0x0004100FU
#define PHY_RDLVL_VREF_OUTLIER                        0x1003100FU
#define SC_PHY_WCK_CALC                               0x1801101BU
#define PHY_WRLVL_PER_START                           0x00071020U
#define PHY_RDLVL_RDDQS_DQ_OBS_SELECT                 0x08051022U
#define PHY_CALVL_VREF_DRIVING_SLICE                  0x08011026U
#define PHY_WRLVL_HARD0_DELAY_OBS                     0x000A102DU
#define PHY_WRLVL_HARD1_DELAY_OBS                     0x100A102DU
#define PHY_WRLVL_STATUS_OBS                          0x001C102EU
#define PHY_WRLVL_ERROR_OBS                           0x00021030U
#define PHY_GTLVL_STATUS_OBS                          0x00121032U
#define PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS                 0x10091033U
#define PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS                 0x00091034U
#define PHY_WDQLVL_STATUS_OBS                         0x00201038U
#define PHY_DATA_DC_CAL_START                         0x08011041U
#define PHY_SLV_DLY_CTRL_GATE_DISABLE                 0x00011042U
#define PHY_REGULATOR_EN_CNT                          0x00061044U
#define PHY_VREF_INITIAL_START_POINT                  0x00091048U
#define PHY_VREF_INITIAL_STOP_POINT                   0x10091048U
#define PHY_VREF_TRAINING_CTRL                        0x00021049U
#define PHY_RDDQ0_SLAVE_DELAY                         0x00091050U
#define PHY_RDDQ1_SLAVE_DELAY                         0x10091050U
#define PHY_RDDQ2_SLAVE_DELAY                         0x00091051U
#define PHY_RDDQ3_SLAVE_DELAY                         0x10091051U
#define PHY_RDDQ4_SLAVE_DELAY                         0x00091052U
#define PHY_RDDQ5_SLAVE_DELAY                         0x10091052U
#define PHY_RDDQ6_SLAVE_DELAY                         0x00091053U
#define PHY_RDDQ7_SLAVE_DELAY                         0x10091053U
#define PHY_RDDM_SLAVE_DELAY                          0x00091054U
#define PHY_RX_CAL_ALL_DLY                            0x18061054U
#define PHY_RX_PCLK_CLK_SEL                           0x00031055U
#define PHY_DATA_DC_CAL_CLK_SEL                       0x08031055U
#define PHY_PAD_VREF_CTRL_DQ                          0x100E1058U
#define PHY_PER_CS_TRAINING_EN                        0x10011059U
#define PHY_RDDATA_EN_TSEL_DLY                        0x0805105BU
#define PHY_RDDATA_EN_OE_DLY                          0x1005105BU
#define PHY_RPTR_UPDATE                               0x0804105EU
#define PHY_WRLVL_RESP_WAIT_CNT                       0x0006105FU
#define PHY_RDLVL_DLY_STEP                            0x08041062U
#define PHY_RDLVL_MAX_EDGE                            0x00091063U
#define PHY_DATA_DC_WDQLVL_ENABLE                     0x08021068U
#define PHY_RDDATA_EN_DLY                             0x10051069U
#define PHY_DQ_DM_SWIZZLE0                            0x0020106AU
#define PHY_DQ_DM_SWIZZLE1                            0x0004106BU
#define PHY_CLK_WRDQS_SLAVE_DELAY                     0x00091071U
#define PHY_WRITE_PATH_LAT_DEC                        0x10011071U
#define PHY_RDDQS_LATENCY_ADJUST                      0x1005107BU
#define PHY_WRITE_PATH_LAT_ADD                        0x1803107BU
#define PHY_WRITE_PATH_LAT_FRAC                       0x0008107CU
#define PHY_GTLVL_LAT_ADJ_START                       0x0005107DU
#define PHY_DATA_DC_DQS_CLK_ADJUST                    0x0008107FU
#define PHY_ADR_CALVL_SWIZZLE0                        0x00201202U
#define PHY_ADR_MEAS_DLY_STEP_ENABLE                  0x10011203U
#define PHY_ADR_CALVL_RANK_CTRL                       0x18021205U
#define PHY_ADR_CALVL_OBS1                            0x0020120AU
#define PHY_ADR_CALVL_OBS2                            0x0020120BU
#define PHY_ADR_CALVL_DLY_STEP                        0x00041210U
#define PHY_CS_ACS_ALLOCATION_BIT2_2                  0x08021215U
#define PHY_CS_ACS_ALLOCATION_BIT3_2                  0x10021215U
#define PHY_CSLVL_OBS1                                0x00201221U
#define PHY_ADRCTL_MASTER_DELAY_HALF_MEASURE          0x1008122DU
#define PHY_CLK_DC_CAL_CLK_SEL                        0x0803123AU
#define PHY_FREQ_SEL_MULTICAST_EN                     0x08011301U
#define PHY_FREQ_SEL_INDEX                            0x10021301U
#define SC_PHY_MANUAL_UPDATE                          0x18011304U
#define PHY_SET_DFI_INPUT_RST_PAD                     0x18011311U
#define PHY_TCKSRE_WAIT                               0x1004131FU
#define PHY_CAL_MODE_0                                0x000D132CU
#define PHY_CAL_INTERVAL_COUNT_0                      0x0020132DU
#define PHY_DATA_BYTE_ORDER_SEL                       0x0020133FU
#define PHY_PAD_ACS_RX_PCLK_CLK_SEL                   0x1003134AU
#define PHY_PLL_CTRL                                  0x000E134DU
#define PHY_PLL_CTRL_8X                               0x100E134DU
#define PHY_CAL_CLK_SELECT_0                          0x00031361U

#define PI_START                                      0x00010800U
#define PI_TRAIN_ALL_FREQ_REQ                         0x18010804U
#define PI_FREQ_MAP                                   0x0020080DU
#define PI_INIT_WORK_FREQ                             0x0005080EU
#define PI_CS_MAP                                     0x08020815U
#define PI_WRLVL_REQ                                  0x0801081FU
#define PI_WRLVL_CS_SW                                0x1002081FU
#define PI_RDLVL_REQ                                  0x10010827U
#define PI_RDLVL_GATE_REQ                             0x18010827U
#define PI_RDLVL_CS_SW                                0x00020828U
#define PI_RDLVL_PERIODIC                             0x08010831U
#define PI_RDLVL_INTERVAL                             0x08100838U
#define PI_DRAMDCA_FLIP_MASK                          0x0802083EU
#define PI_DRAMDCA_LVL_REQ                            0x10010840U
#define PI_DCMLVL_CS_SW                               0x18020840U
#define PI_WRDCM_LVL_EN_F1                            0x00020842U
#define PI_DRAMDCA_LVL_EN_F1                          0x08020842U
#define PI_WRDCM_LVL_EN_F2                            0x18020842U
#define PI_DRAMDCA_LVL_EN_F2                          0x00020843U
#define PI_TCKCKEL_F2                                 0x18040851U
#define PI_WDQLVL_VREF_EN                             0x08040852U
#define PI_WDQLVL_PERIODIC                            0x00010854U
#define PI_WDQLVL_INTERVAL                            0x00100858U
#define PI_INT_STATUS                                 0x002008B7U
#define PI_INT_ACK_0                                  0x002008B9U
#define PI_INT_ACK_1                                  0x000108BAU
#define PI_LONG_COUNT_MASK                            0x100508BCU
#define PI_ADDRESS_MUX_0                              0x000308BDU
#define PI_ADDRESS_MUX_1                              0x080308BDU
#define PI_ADDRESS_MUX_2                              0x100308BDU
#define PI_ADDRESS_MUX_3                              0x180308BDU
#define PI_ADDRESS_MUX_4                              0x000308BEU
#define PI_ADDRESS_MUX_5                              0x080308BEU
#define PI_ADDRESS_MUX_6                              0x100308BEU
#define PI_DATA_BYTE_SWAP_EN                          0x180108BEU
#define PI_DATA_BYTE_SWAP_SLICE0                      0x000108BFU
#define PI_DATA_BYTE_SWAP_SLICE1                      0x080108BFU
#define PI_PWRUP_SREFRESH_EXIT                        0x100108C2U
#define PI_DLL_RST                                    0x000108C6U
#define PI_TDELAY_RDWR_2_BUS_IDLE_F1                  0x000808E8U
#define PI_TDELAY_RDWR_2_BUS_IDLE_F2                  0x000808E9U
#define PI_WRLAT_F1                                   0x100708EDU
#define PI_TWCKENL_RD_ADJ_F1                          0x000608EEU
#define PI_TWCKPRE_STATIC_F1                          0x080608EEU
#define PI_TWCKPRE_TOGGLE_RD_F1                       0x180608EEU
#define PI_WCK_ACTIVE_WR_F1                           0x000708EFU
#define PI_WCK_ACTIVE_RD_F1                           0x080708EFU
#define PI_CASLAT_F1                                  0x180708EFU
#define PI_WRLAT_F2                                   0x000708F0U
#define PI_TWCKENL_WR_ADJ_F2                          0x080608F0U
#define PI_TWCKENL_RD_ADJ_F2                          0x100608F0U
#define PI_TWCKPRE_STATIC_F2                          0x180608F0U
#define PI_TWCKPRE_TOGGLE_RD_F2                       0x080608F1U
#define PI_WCK_ACTIVE_WR_F2                           0x100708F1U
#define PI_WCK_ACTIVE_RD_F2                           0x180708F1U
#define PI_TWCKENL_FS_ADJ_F2                          0x000608F2U
#define PI_CASLAT_F2                                  0x080708F2U
#define PI_TRFC_F1                                    0x000A08F4U
#define PI_TREF_F1                                    0x001408F5U
#define PI_TRFC_F2                                    0x000A08F6U
#define PI_TREF_F2                                    0x001408F7U
#define PI_WRLVL_EN_F1                                0x000208FAU
#define PI_TDFI_WRLVL_WW_F1                           0x080A08FAU
#define PI_WRLVL_EN_F2                                0x000208FBU
#define PI_TDFI_WRLVL_WW_F2                           0x080A08FBU
#define PI_WRLVL_WCKOFF_F2                            0x180808FBU
#define PI_RDLVL_EN_F1                                0x100208FFU
#define PI_RDLVL_GATE_EN_F1                           0x180208FFU
#define PI_RDLVL_EN_F2                                0x00020900U
#define PI_RDLVL_GATE_EN_F2                           0x08020900U
#define PI_RDLVL_VREF_EN_F0                           0x18040900U
#define PI_RDLVL_RDDQ_EN_F1                           0x00040902U
#define PI_RDLVL_VREF_EN_F1                           0x08040902U
#define PI_RDLVL_VREF_EN_F2                           0x18040903U
#define PI_RDLAT_ADJ_F1                               0x10090905U
#define PI_RDLAT_ADJ_F2                               0x00090906U
#define PI_WRLAT_ADJ_F1                               0x18070906U
#define PI_WRLAT_ADJ_F2                               0x00070907U
#define PI_TDFI_CALVL_CC_F1                           0x000A0909U
#define PI_TDFI_CALVL_CAPTURE_F1                      0x100A0909U
#define PI_TDFI_CALVL_CC_F2                           0x000A090AU
#define PI_TDFI_CALVL_CAPTURE_F2                      0x100A090AU
#define PI_CALVL_EN_F1                                0x0802090BU
#define PI_CALVL_EN_F2                                0x1002090BU
#define PI_TCAENT_F1                                  0x000E090DU
#define PI_TCAENT_F2                                  0x000E090EU
#define PI_TVREF_LONG_F1                              0x000A0912U
#define PI_TVRCG_ENABLE_F1                            0x100A0912U
#define PI_TVRCG_DISABLE_F1                           0x000A0913U
#define PI_TVREF_LONG_F2                              0x100A0914U
#define PI_TVRCG_ENABLE_F2                            0x000A0915U
#define PI_TVRCG_DISABLE_F2                           0x100A0915U
#define PI_CALVL_VREF_INITIAL_START_POINT_F2          0x10070917U
#define PI_CALVL_VREF_INITIAL_STOP_POINT_F2           0x18070917U
#define PI_TDFI_CALVL_STROBE_F2                       0x0804091AU
#define PI_TXP_F2                                     0x1005091AU
#define PI_TMRWCKEL_F2                                0x1808091AU
#define PI_TCKEHDQS_F1                                0x10060921U
#define PI_TFC_F1                                     0x000A0922U
#define PI_TCKEHDQS_F2                                0x10060922U
#define PI_TFC_F2                                     0x000A0923U
#define PI_WDQLVL_VREF_INITIAL_START_POINT_F0         0x10070925U
#define PI_WDQLVL_VREF_INITIAL_STOP_POINT_F0          0x18070925U
#define PI_TDFI_WDQLVL_WR_F1                          0x080A0928U
#define PI_TDFI_WDQLVL_RW_F1                          0x000A0929U
#define PI_WDQLVL_VREF_INITIAL_START_POINT_F1         0x10070929U
#define PI_WDQLVL_VREF_INITIAL_STOP_POINT_F1          0x18070929U
#define PI_WDQLVL_EN_F1                               0x0802092AU
#define PI_WDQLVL_RDLAT_ADJ_F1                        0x0009092BU
#define PI_WDQLVL_WRLAT_ADJ_F1                        0x1009092BU
#define PI_WDQLVL_TWCKENL_RD_ADJ_F1                   0x0006092CU
#define PI_TDFI_WDQLVL_WR_F2                          0x080A092CU
#define PI_TDFI_WDQLVL_RW_F2                          0x000A092DU
#define PI_WDQLVL_VREF_INITIAL_START_POINT_F2         0x1007092DU
#define PI_WDQLVL_VREF_INITIAL_STOP_POINT_F2          0x1807092DU
#define PI_WDQLVL_EN_F2                               0x0802092EU
#define PI_WDQLVL_RDLAT_ADJ_F2                        0x0009092FU
#define PI_WDQLVL_WRLAT_ADJ_F2                        0x1009092FU
#define PI_WDQLVL_TWCKENL_RD_ADJ_F2                   0x00060930U
#define PI_TRTP_F1                                    0x18080936U
#define PI_TRP_F1                                     0x00080937U
#define PI_TRCD_F1                                    0x08080937U
#define PI_TWTR_S_F1                                  0x18060937U
#define PI_TWTR_L_F1                                  0x00060938U
#define PI_TWTR_F1                                    0x10060938U
#define PI_TWR_F1                                     0x18080938U
#define PI_TRAS_MAX_F1                                0x00100939U
#define PI_TRAS_MIN_F1                                0x10090939U
#define PI_TSR_F1                                     0x1008093AU
#define PI_TRTP_F2                                    0x0808093BU
#define PI_TRP_F2                                     0x1008093BU
#define PI_TRCD_F2                                    0x1808093BU
#define PI_TWTR_S_F2                                  0x0806093CU
#define PI_TWTR_L_F2                                  0x1006093CU
#define PI_TWTR_F2                                    0x0006093DU
#define PI_TWR_F2                                     0x0808093DU
#define PI_TRAS_MAX_F2                                0x1010093DU
#define PI_TRAS_MIN_F2                                0x0009093EU
#define PI_TDQSCK_MAX_F2                              0x1004093EU
#define PI_TSR_F2                                     0x0008093FU
#define PI_TMRD_F2                                    0x0808093FU
#define PI_TDFI_CTRLUPD_MAX_F1                        0x00150942U
#define PI_TDFI_CTRLUPD_INTERVAL_F1                   0x00200943U
#define PI_TDFI_CTRLUPD_MAX_F2                        0x00150944U
#define PI_TDFI_CTRLUPD_INTERVAL_F2                   0x00200945U
#define PI_TXSR_F1                                    0x10100946U
#define PI_TXSR_F2                                    0x00100947U
#define PI_TINIT_F1                                   0x0018094EU
#define PI_TINIT1_F1                                  0x0018094FU
#define PI_TINIT3_F1                                  0x00180950U
#define PI_TINIT4_F1                                  0x00180951U
#define PI_TINIT5_F1                                  0x00180952U
#define PI_TXSNR_F1                                   0x00100953U
#define PI_TINIT_F2                                   0x00180954U
#define PI_TINIT1_F2                                  0x00180955U
#define PI_TINIT3_F2                                  0x00180956U
#define PI_TINIT4_F2                                  0x00180957U
#define PI_TINIT5_F2                                  0x00180958U
#define PI_TXSNR_F2                                   0x00100959U
#define PI_TZQCAL_F1                                  0x100C095CU
#define PI_TZQLAT_F1                                  0x0007095DU
#define PI_TZQCAL_F2                                  0x100C095EU
#define PI_TZQLAT_F2                                  0x0007095FU
#define PI_ZQRESET_F1                                 0x000C0960U
#define PI_ZQRESET_F2                                 0x100C0960U
#define PI_TDQ72DQ_F1                                 0x000A0964U
#define PI_TCBTRTW_F1                                 0x10060964U
#define PI_TDQ72DQ_F2                                 0x100A0965U
#define PI_TCBTRTW_F2                                 0x00060966U
#define PI_MC_TRFC_F1                                 0x100A0968U
#define PI_MC_TRFC_F2                                 0x000A0969U
#define PI_TDFI_WCK_STOP_F1                           0x0808096EU
#define PI_TDFI_WCK_STOP_F2                           0x1808096EU
#define PI_CKE_MUX_0                                  0x1802096FU
#define PI_CKE_MUX_1                                  0x00020970U
#define PI_SEQ_DEC_SW_CS                              0x0002097BU
#define PI_SW_SEQ_START                               0x1001097BU
#define PI_SEQ_ARRAY_29                               0x001D09C9U
#define PI_SEQ_ARRAY_64                               0x001D09ECU
#define PI_SEQ_ARRAY_65                               0x001D09EDU
#define PI_SEQ_ARRAY_66                               0x001D09EEU
#define PI_SEQ_ARRAY_67                               0x001D09EFU
#define PI_SEQ_ARRAY_68                               0x001D09F0U
#define PI_SEQ_ARRAY_69                               0x001D09F1U
#define PI_SEQ_ARRAY_70                               0x001D09F2U
#define PI_SEQ_ARRAY_71                               0x001D09F3U
#define PI_SEQ_ARRAY_72                               0x001D09F4U
#define PI_SEQ_ARRAY_81                               0x001D09FDU
#define PI_SEQ_ARRAY_82                               0x001D09FEU
#define PI_SEQ_ARRAY_333                              0x001B0AF9U
#define PI_SEQ_ARRAY_334                              0x001B0AFAU
#define PI_SEQ_ARRAY_335                              0x001B0AFBU
#define PI_SEQ_ARRAY_349                              0x001B0B09U
#define PI_SEQ_ARRAY_350                              0x001B0B0AU
#define PI_RDLVL_TRAIN_SEQ_1                          0x001B0B9EU
#define PI_RDLVL_TRAIN_SEQ_2                          0x001B0B9FU
#define PI_RDLVL_TRAIN_SEQ_3                          0x001B0BA0U
#define PI_RDLVL_TRAIN_SEQ_4                          0x001B0BA1U
#define PI_RDLVL_TRAIN_SEQ_5                          0x001B0BA2U
#define PI_SEQ_WAIT_16_F1                             0x00180BD2U
#define PI_SEQ_WAIT_16_F2                             0x00180BD3U
#define PI_SEQ_WAIT_17_F1                             0x00180BD5U
#define PI_SEQ_WAIT_17_F2                             0x00180BD6U
#define PI_SEQ_WAIT_18_F2                             0x00180BD9U
#define PI_SEQ_WAIT_19_F1                             0x00180BDBU
#define PI_SEQ_WAIT_19_F2                             0x00180BDCU
#define PI_SEQ_WAIT_20_F1                             0x00180BDEU
#define PI_SEQ_WAIT_20_F2                             0x00180BDFU
#define PI_SEQ_WAIT_21_F1                             0x00180BE1U
#define PI_SEQ_WAIT_21_F2                             0x00180BE2U
#define PI_SEQ_WAIT_22_F1                             0x00180BE4U
#define PI_SEQ_WAIT_22_F2                             0x00180BE5U
#define PI_SEQ_WAIT_23_F1                             0x00180BE7U
#define PI_SEQ_WAIT_23_F2                             0x00180BE8U
#define PI_SEQ_WAIT_24_F1                             0x00180BEAU
#define PI_SEQ_WAIT_24_F2                             0x00180BEBU
#define PI_SEQ_WAIT_25_F1                             0x00180BEDU
#define PI_SEQ_WAIT_25_F2                             0x00180BEEU
#define PI_SEQ_WAIT_26_F1                             0x00180BF0U
#define PI_SEQ_WAIT_26_F2                             0x00180BF1U
#define PI_SEQ_WAIT_27_F2                             0x00180BF4U
#define PI_SEQ_WAIT_31_F1                             0x00180BFFU
#define PI_SEQ_WAIT_31_F2                             0x00180C00U
#define PI_WP_GAP_0_F1                                0x100F0C0DU
#define PI_WP_GAP_0_F2                                0x000F0C0EU
#define PI_RP_GAP_0_F1                                0x000F0C0FU
#define PI_RP_GAP_0_F2                                0x100F0C0FU
#define PI_WR_GAP_S_0_F1                              0x100F0C10U
#define PI_WR_GAP_S_0_F2                              0x000F0C11U
#define PI_WR_GAP_L_0_F1                              0x000F0C12U
#define PI_WR_GAP_L_0_F2                              0x100F0C12U
#define PI_RW_GAP_0_F1                                0x100F0C13U
#define PI_RW_GAP_0_F2                                0x000F0C14U
#define PI_WP_GAP_1_F1                                0x000F0C1BU
#define PI_WP_GAP_1_F2                                0x100F0C1BU
#define PI_RP_GAP_1_F1                                0x100F0C1CU
#define PI_RP_GAP_1_F2                                0x000F0C1DU
#define PI_WR_GAP_S_1_F1                              0x000F0C1EU
#define PI_WR_GAP_S_1_F2                              0x100F0C1EU
#define PI_WR_GAP_L_1_F1                              0x100F0C1FU
#define PI_WR_GAP_L_1_F2                              0x000F0C20U
#define PI_RW_GAP_1_F1                                0x000F0C21U
#define PI_RW_GAP_1_F2                                0x100F0C21U
#define PI_WP_GAP_2_F1                                0x100F0C28U
#define PI_WP_GAP_2_F2                                0x000F0C29U
#define PI_RP_GAP_2_F1                                0x000F0C2AU
#define PI_RP_GAP_2_F2                                0x100F0C2AU
#define PI_WR_GAP_S_2_F1                              0x100F0C2BU
#define PI_WR_GAP_S_2_F2                              0x000F0C2CU
#define PI_WR_GAP_L_2_F1                              0x000F0C2DU
#define PI_WR_GAP_L_2_F2                              0x100F0C2DU
#define PI_RW_GAP_2_F1                                0x100F0C2EU
#define PI_RW_GAP_2_F2                                0x000F0C2FU
#define PI_WP_GAP_3_F1                                0x000F0C36U
#define PI_WP_GAP_3_F2                                0x100F0C36U
#define PI_RP_GAP_3_F1                                0x100F0C37U
#define PI_RP_GAP_3_F2                                0x000F0C38U
#define PI_WR_GAP_S_3_F1                              0x000F0C39U
#define PI_WR_GAP_S_3_F2                              0x100F0C39U
#define PI_WR_GAP_L_3_F1                              0x100F0C3AU
#define PI_WR_GAP_L_3_F2                              0x000F0C3BU
#define PI_RW_GAP_3_F1                                0x000F0C3CU
#define PI_RW_GAP_3_F2                                0x100F0C3CU
#define PI_DARRAY3_0_CS0_F0                           0x00080C9DU
#define PI_DARRAY3_1_CS0_F0                           0x08080C9DU
#define PI_DARRAY3_0_CS0_F1                           0x00080CA7U
#define PI_DARRAY3_1_CS0_F1                           0x08080CA7U
#define PI_DARRAY3_0_CS0_F2                           0x00080CB1U
#define PI_DARRAY3_1_CS0_F2                           0x08080CB1U
#define PI_DARRAY3_2_CS0_F2                           0x10080CB1U
#define PI_DARRAY3_20_CS0_F2                          0x00080CB6U
#define PI_DARRAY3_0_CS1_F0                           0x00080CBBU
#define PI_DARRAY3_1_CS1_F0                           0x08080CBBU
#define PI_DARRAY3_0_CS1_F1                           0x00080CC5U
#define PI_DARRAY3_1_CS1_F1                           0x08080CC5U
#define PI_DARRAY3_0_CS1_F2                           0x00080CCFU
#define PI_DARRAY3_1_CS1_F2                           0x08080CCFU
#define PI_DARRAY3_2_CS1_F2                           0x10080CCFU
#define PI_DARRAY3_20_CS1_F2                          0x00080CD4U

#define DDR_REGDEF_ADR(regdef) ((regdef) & 0xFFFFU)
#define DDR_REGDEF_LEN(regdef) (((regdef) >> 16) & 0xFFU)
#define DDR_REGDEF_LSB(regdef) (((regdef) >> 24) & 0xFFU)

#endif /* DDR_REGDEF_H_ */
