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d411edd9b47003e0a9ef98de9aef8259ddea419d
Gen4_R-Car_Trace32/2_Trunk/perpsoc4000.per
woody d411edd9b4 add Trace32 File
2025-10-14 09:52:32 +09:00

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; --------------------------------------------------------------------------------
; @Title: PSoC 4000 On-Chip Peripherals
; @Props: Released
; @Author: KWI, DAB
; @Changelog: 2019-01-23 KWI
; 2022-01-20 DAB
; @Manufacturer: CYPRESS - Cypress Semiconductor Corporation
; @Doc: CY8C40xx.svd
; @Core: Cortex-M0
; @Chip: CY8C4013SXI-400, CY8C4013SXI-410, CY8C4013SXI-411, CY8C4013LQI-411,
; CY8C4014SXI-411, CY8C4014SXI-421, CY8C4014LQI-421, CY8C4014LQI-412,
; CY8C4014LQI-422, CY8C4014PVI-412, CY8C4014PVI-422, CY8C4014FNI-421,
; CY8C4014FNI-421A, CY8C4014LQI-SLT2, CY8C4014SXA-421Z, CY8C4014LQA-422Z
; CY8C4014SXS-421Z, CY8C4014LQS-422Z
; @Copyright: (C) 1989-2022 Lauterbach GmbH, licensed for use with TRACE32(R) only
; --------------------------------------------------------------------------------
; $Id: perpsoc4000.per 14191 2022-01-27 13:52:46Z kwisniewski $
config 16. 8.
tree.close "Core Registers (Cortex-M0)"
AUTOINDENT.PUSH
AUTOINDENT.OFF
tree "System Control"
sif COMPonent.AVAILABLE("COREDEBUG")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
width 0x8
if (CORENAME()=="CORTEXM1")
group.long 0x10++0x0b
line.long 0x00 "STCSR,SysTick Control and Status Register"
bitfld.long 0x00 16. " COUNTFLAG ,Returns 1 if timer counted to 0" "0,1"
bitfld.long 0x00 2. " CLKSOURCE ,Always reads as one" "No effect,Processor clock"
textline " "
bitfld.long 0x00 1. " TICKINT ,Counting down to 0 " "No SysTick,SysTick"
bitfld.long 0x00 0. " ENABLE ,Counter enable" "Disabled,Enabled"
line.long 0x04 "STRVR,SysTick Reload Value Register"
hexmask.long.tbyte 0x04 0.--23. 1. " RELOAD ,Value to load into the STCVR when the counter reaches 0"
line.long 0x08 "STCVR,SysTick Current Value Register"
hexmask.long.tbyte 0x08 0.--23. 1. " CURRENT ,Reads return the current value of the SysTick counter"
else
group.long 0x10++0x0b
line.long 0x00 "STCSR,SysTick Control and Status Register"
bitfld.long 0x00 16. " COUNTFLAG ,Returns 1 if timer counted to 0" "0,1"
bitfld.long 0x00 2. " CLKSOURCE ,Always reads as one" "External clock,Processor clock"
textline " "
bitfld.long 0x00 1. " TICKINT ,Counting down to 0 " "No SysTick,SysTick"
bitfld.long 0x00 0. " ENABLE ,Counter enable" "Disabled,Enabled"
line.long 0x04 "STRVR,SysTick Reload Value Register"
hexmask.long.tbyte 0x04 0.--23. 1. " RELOAD ,Value to load into the STCVR when the counter reaches 0"
line.long 0x08 "STCVR,SysTick Current Value Register"
hexmask.long.tbyte 0x08 0.--23. 1. " CURRENT ,Reads return the current value of the SysTick counter"
endif
if (CORENAME()=="CORTEXM1")
rgroup.long 0x1c++0x03
line.long 0x00 "STCR,SysTick Calibration Value Register"
bitfld.long 0x00 31. " NOREF ,Reads as one" "0,1"
bitfld.long 0x00 30. " SKEW ,Reads as zero" "0,1"
textline " "
hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,Indicates calibration value is not known"
else
rgroup.long 0x1c++0x03
line.long 0x00 "STCR,SysTick Calibration Value Register"
bitfld.long 0x00 31. " NOREF ,Indicates whether the IMPL_DEF reference clock is provided" "Implemented,Not implemented"
bitfld.long 0x00 30. " SKEW ,Indicates whether the 10ms calibration value is exact" "Exact,Inexact"
textline " "
hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,Holds a reload value to be used for 10ms (100Hz) timing subject to system clock skew errors"
endif
rgroup.long 0xd00++0x03
line.long 0x00 "CPUID,CPU ID Base Register"
hexmask.long.byte 0x00 24.--31. 1. " IMPLEMENTER ,Implementer code"
hexmask.long.byte 0x00 20.--23. 1. " VARIANT ,Implementation defined variant number"
textline " "
hexmask.long.byte 0x00 4.--15. 1. " PARTNO ,Number of processor within family"
hexmask.long.byte 0x00 0.--3. 1. " REVISION ,Implementation defined revision number"
group.long 0xd04++0x03
line.long 0x00 "ICSR,Interrupt Control State Register"
bitfld.long 0x00 31. " NMIPENDSET ,Setting this bit will activate an NMI" "No effect,Set pending"
bitfld.long 0x00 28. " PENDSVSET ,Set a pending PendSV interrupt" "No effect,Set pending"
textline " "
bitfld.long 0x00 27. " PENDSVCLR ,Clear a pending PendSV interrupt" "No effect,Clear pending"
bitfld.long 0x00 26. " PENDSTSET ,Set a pending SysTick" "No effect,Set pending"
textline " "
bitfld.long 0x00 25. " PENDSVCLR ,Clear a pending SysTick" "No effect,Clear pending"
bitfld.long 0x00 23. " ISRPREEMPT ,Pending exception service" "No service,Service"
textline " "
bitfld.long 0x00 22. " ISRPENDING ,External interrupt pending flag" "No interrupt,Interrupt"
hexmask.long.byte 0x00 12.--17. 1. " VECTPENDING ,Active exception number field"
textline " "
hexmask.long.byte 0x00 0.--5. 1. " VECTACTIVET ,Active exception number field"
if (CORENAME()=="CORTEXM0+")
group.long 0xd08++0x03
line.long 0x00 "VTOR,Vector Table Offset Register"
hexmask.long 0x00 7.--31. 0x80 " TBLOFF ,Vector table address"
else
textline " "
endif
group.long 0xd0c++0x03
line.long 0x00 "AIRCR,Application Interrupt and Reset Control Register"
hexmask.long.word 0x00 16.--31. 1. " VECTKEY ,Vector Key"
bitfld.long 0x00 15. " ENDIANNESS ,Data endianness bit" "Little-endian,Big-endian"
textline " "
bitfld.long 0x00 2. " SYSRESETREQ ,System reset setup request" "No effect,Reset"
bitfld.long 0x00 1. " VECTCLRACTIVE ,Clears all active state information" "No clear,Clear"
group.long 0xd10++0x03
line.long 0x00 "SCR,System Control Register"
bitfld.long 0x00 4. " SEVONPEND ,Determines whether an interrupt transition from inactive state to pending state is a wakeup event" "Not wakeup,Wakeup"
bitfld.long 0x00 2. " SLEEPDEEP ,Provides a qualifying hint indicating that waking from sleep might take longer" "Not deep sleep,Deep sleep"
textline " "
bitfld.long 0x00 1. " SLEEPONEXIT ,Determines whether, on an exit from an ISR that returns to the base level of execution priority, the processor enters a sleep state" "Disabled,Enabled"
rgroup.long 0xd14++0x03
line.long 0x00 "CCR,Configuration and Control Register"
bitfld.long 0x00 9. " STKALIGN ,Indicates whether on exception entry all exceptions are entered with 8-byte stack alignment and the context to restore it is saved" "Reserved,Aligned"
bitfld.long 0x00 3. " UNALIGN_TRP ,Indicates that all unaligned accesses results in a Hard Fault" "Reserved,Trapped"
group.long 0xd1c++0x0b
line.long 0x00 "SHPR2,System Handler Priority Register 2"
bitfld.long 0x00 30.--31. " PRI_11 ,Priority of system handler 11-SVCall" "00,01,10,11"
line.long 0x04 "SHPR3,System Handler Priority Register 3"
bitfld.long 0x04 30.--31. " PRI_15 ,Priority of system handler 15-SysTick" "00,01,10,11"
bitfld.long 0x04 22.--23. " PRI_14 ,Priority of system handler 14- PendSV" "00,01,10,11"
line.long 0x08 "SHCSR,System Handler Control and State Register"
bitfld.long 0x08 15. " SVCALLPENDED ,Reads as 1 if SVCall is pending" "Not pending,Pending"
if (CORENAME()=="CORTEXM0+")
hgroup.long 0x08++0x03
hide.long 0x00 "ACTLR,Auxiliary Control Register"
else
textline " "
endif
else
newline
textline "COREDEBUG component base address not specified"
newline
endif
tree.end
tree "Nested Vectored Interrupt Controller (NVIC)"
sif COMPonent.AVAILABLE("COREDEBUG")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
width 12.
tree "Interrupt Enable Registers"
group.long 0x100++0x03
line.long 0x00 "SET/CLREN,Interrupt Set/Clear Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
tree.end
tree "Interrupt Pending Registers"
group.long 0x200++0x03
line.long 0x00 "SET/CLRPEN,Interrupt Set/Clear Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
tree.end
width 6.
tree "Interrupt Priority Registers"
group.long 0x400++0x1F
line.long 0x00 "INT0,Interrupt Priority Register"
bitfld.long 0x00 30.--31. " IP_3 ,Priority of interrupt 3" "0,1,2,3"
bitfld.long 0x00 22.--23. " IP_2 ,Priority of interrupt 2" "0,1,2,3"
bitfld.long 0x00 14.--15. " IP_1 ,Priority of interrupt 1" "0,1,2,3"
bitfld.long 0x00 6.--7. " IP_0 ,Priority of interrupt 0" "0,1,2,3"
line.long 0x04 "INT1,Interrupt Priority Register"
bitfld.long 0x04 30.--31. " IP_7 ,Priority of interrupt 7" "0,1,2,3"
bitfld.long 0x04 22.--23. " IP_6 ,Priority of interrupt 6" "0,1,2,3"
bitfld.long 0x04 14.--15. " IP_5 ,Priority of interrupt 5" "0,1,2,3"
bitfld.long 0x04 6.--7. " IP_4 ,Priority of interrupt 4" "0,1,2,3"
line.long 0x08 "INT2,Interrupt Priority Register"
bitfld.long 0x08 30.--31. " IP_11 ,Priority of interrupt 11" "0,1,2,3"
bitfld.long 0x08 22.--23. " IP_10 ,Priority of interrupt 10" "0,1,2,3"
bitfld.long 0x08 14.--15. " IP_9 ,Priority of interrupt 9" "0,1,2,3"
bitfld.long 0x08 6.--7. " IP_8 ,Priority of interrupt 8" "0,1,2,3"
line.long 0x0C "INT3,Interrupt Priority Register"
bitfld.long 0x0C 30.--31. " IP_15 ,Priority of interrupt 15" "0,1,2,3"
bitfld.long 0x0C 22.--23. " IP_14 ,Priority of interrupt 14" "0,1,2,3"
bitfld.long 0x0C 14.--15. " IP_13 ,Priority of interrupt 13" "0,1,2,3"
bitfld.long 0x0C 6.--7. " IP_12 ,Priority of interrupt 12" "0,1,2,3"
line.long 0x10 "INT4,Interrupt Priority Register"
bitfld.long 0x10 30.--31. " IP_19 ,Priority of interrupt 19" "0,1,2,3"
bitfld.long 0x10 22.--23. " IP_18 ,Priority of interrupt 18" "0,1,2,3"
bitfld.long 0x10 14.--15. " IP_17 ,Priority of interrupt 17" "0,1,2,3"
bitfld.long 0x10 6.--7. " IP_16 ,Priority of interrupt 16" "0,1,2,3"
line.long 0x14 "INT5,Interrupt Priority Register"
bitfld.long 0x14 30.--31. " IP_23 ,Priority of interrupt 23" "0,1,2,3"
bitfld.long 0x14 22.--23. " IP_22 ,Priority of interrupt 22" "0,1,2,3"
bitfld.long 0x14 14.--15. " IP_21 ,Priority of interrupt 21" "0,1,2,3"
bitfld.long 0x14 6.--7. " IP_20 ,Priority of interrupt 20" "0,1,2,3"
line.long 0x18 "INT6,Interrupt Priority Register"
bitfld.long 0x18 30.--31. " IP_27 ,Priority of interrupt 27" "0,1,2,3"
bitfld.long 0x18 22.--23. " IP_26 ,Priority of interrupt 26" "0,1,2,3"
bitfld.long 0x18 14.--15. " IP_25 ,Priority of interrupt 25" "0,1,2,3"
bitfld.long 0x18 6.--7. " IP_24 ,Priority of interrupt 24" "0,1,2,3"
line.long 0x1C "INT7,Interrupt Priority Register"
bitfld.long 0x1C 30.--31. " IP_31 ,Priority of interrupt 31" "0,1,2,3"
bitfld.long 0x1C 22.--23. " IP_30 ,Priority of interrupt 30" "0,1,2,3"
bitfld.long 0x1C 14.--15. " IP_29 ,Priority of interrupt 29" "0,1,2,3"
bitfld.long 0x1C 6.--7. " IP_28 ,Priority of interrupt 28" "0,1,2,3"
tree.end
width 0x0B
else
newline
textline "COREDEBUG component base address not specified"
newline
endif
tree.end
tree "Debug"
tree "Core Debug"
sif COMPonent.AVAILABLE("COREDEBUG")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
width 0xA
group.long 0xD30++0x03
line.long 0x00 "DFSR,Data Fault Status Register"
eventfld.long 0x00 4. " EXTERNAL ,External debug request flag" "No occurred,Occurred"
eventfld.long 0x00 3. " VCATCH ,Vector catch flag" "No occurred,Occurred"
textline " "
eventfld.long 0x00 2. " DWTRAP ,Data Watchpoint flag" "No match,Match"
textline " "
eventfld.long 0x00 1. " BKPT ,BKPT flag" "No match,Match"
eventfld.long 0x00 0. " HALTED ,Halt request flag" "No request,Request"
if (CORENAME()=="CORTEXM1")
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDF0))&0x01)==0x00)
group.long 0xDF0++0x03
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not completed,Completed"
textline " "
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 19. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 18. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available"
textline " "
textline " "
textfld " "
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
else
group.long 0xDF0++0x03
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not read,Read"
textline " "
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 19. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 18. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available"
textline " "
bitfld.long 0x00 3. " C_MASKINTS ,Interrupts Mask" "Not masked,Masked"
bitfld.long 0x00 2. " C_STEP ,Steps the core in halted debug" "Not halted,Halted"
textline " "
bitfld.long 0x00 1. " C_HALT ,Core Halted" "Not halted,Halted"
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
endif
else
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDF0))&0x01)==0x00)
group.long 0xDF0++0x03
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not completed,Completed"
textline " "
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 19. " S_LOCKUP/DBGKEY ,Core Lockup Status/Debug Key" "Not locked up,Locked up"
bitfld.long 0x00 18. " S_SLEEP/DBGKEY ,Core Sleep Status/Debug Key" "Not sleeping,Sleeping"
textline " "
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available"
textline " "
textline " "
textfld " "
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
else
group.long 0xDF0++0x03
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not read,Read"
textline " "
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 19. " S_LOCKUP/DBGKEY ,Core Lockup Status/Debug Key" "Not locked up,Locked up"
bitfld.long 0x00 18. " S_SLEEP/DBGKEY ,Core Sleep Status/Debug Key" "Not sleeping,Sleeping"
textline " "
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available"
textline " "
bitfld.long 0x00 3. " C_MASKINTS ,Interrupts Mask" "Not masked,Masked"
bitfld.long 0x00 2. " C_STEP ,Steps the core in halted debug" "Not halted,Halted"
textline " "
bitfld.long 0x00 1. " C_HALT ,Core Halted" "Not halted,Halted"
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
endif
endif
wgroup.long 0xDF4++0x03
line.long 0x00 "DCRSR,Debug Core Selector Register"
bitfld.long 0x00 16. " REGWnR ,Register Read/Write" "Read,Write"
bitfld.long 0x00 0.--4. " REGSEL ,Register Selection" "R0,R1,R2,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,Current SP,LR,DebugReturnAddress,xPSR Flags,MSP,PSP,Reserved,CONTROL[1]/PRIMASK[0],?..."
group.long 0xDF8++0x07
line.long 0x00 "DCRDR,Debug Core Register Data Register"
hexmask.long 0x00 0.--31. 1. " DATA ,Data for reading and writing registers to and from the processor"
line.long 0x04 "DEMCR,Debug Exception and Monitor Control Register"
bitfld.long 0x04 24. " DWTENA ,Global enable or disable for the DW unit" "Disabled,Enabled"
bitfld.long 0x04 10. " VC_HARDERR ,Debug trap on a Hard Fault" "No error,Error"
textline " "
bitfld.long 0x04 0. " VC_CORERESET ,Reset Vector Catch" "No reset,Reset"
width 0x0B
else
newline
textline "COREDEBUG component base address not specified"
newline
endif
tree.end
tree "Breakpoint Unit (BPU)"
sif COMPonent.AVAILABLE("BPU")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("BPU",-1))
width 8.
group.long 0x00++0x03
line.long 0x00 "BP_CTRL,Breakpoint Control Register"
bitfld.long 0x00 4.--7. " NUM_CODE1 ,Number of comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 1. " KEY ,Key field" "No write,Write"
bitfld.long 0x00 0. " ENABLE ,Breakpoint unit enable bit" "Disabled,Enabled"
group.long 0x8++0x03
line.long 0x00 "B_COMP0,Breakpoint Comparator Registers 0"
bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords"
hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address"
bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 0" "Disabled,Enabled"
group.long 0xC++0x03
line.long 0x00 "B_COMP1,Breakpoint Comparator Registers 1"
bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords"
hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address"
bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 1" "Disabled,Enabled"
group.long 0x10++0x03
line.long 0x00 "B_COMP2,Breakpoint Comparator Registers 2"
bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords"
hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address"
bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 2" "Disabled,Enabled"
group.long 0x14++0x03
line.long 0x00 "B_COMP3,Breakpoint Comparator Registers 3"
bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords"
hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address"
bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 3" "Disabled,Enabled"
else
newline
textline "BPU component base address not specified"
newline
endif
tree.end
tree "Data Watchpoint and Trace Unit (DWT)"
sif COMPonent.AVAILABLE("DWT")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))
width 14.
rgroup.long 0x00++0x03
line.long 0x00 "DW_CTRL,DW Control Register "
bitfld.long 0x00 28.--31. " NUM_CODE1 ,Number of comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rgroup.long 0x1c++0x03
line.long 0x00 "DW_PCSR,DW Program Counter Sample Register"
hexmask.long 0x00 0.--31. 1. " EIASAMPLE ,Execution instruction address sample or 0xFFFFFFFF"
group.long 0x20++0x0b
line.long 0x00 "DW_COMP0,DW Comparator Register 0"
hexmask.long 0x00 0.--31. 1. " COMP1 ,Compare against PC or the data address"
line.long 0x04 "DW_MASK0,DW Mask Register 0"
hexmask.long.byte 0x04 0.--4. 1. " MASK ,Mask on data address when matching against COMP"
line.long 0x08 "DW_FUNCTION0,DW Function Register 0"
bitfld.long 0x08 24. " MATCHED ,Comparator match" "No match,Match"
bitfld.long 0x08 0.--3. " FUNCTION , Settings for DW Function Registers" "Disabled,Reserved,Reserved,Reserved,On PC match,Read address,Write address,R/W address,?..."
group.long 0x30++0x0b
line.long 0x00 "DW_COMP1,DW Comparator Register 1"
hexmask.long 0x00 0.--31. 1. " COMP ,Compare against PC or the data address"
line.long 0x04 "DW_MASK1,DW Mask Register 1 "
hexmask.long.byte 0x04 0.--4. 1. " MASK ,Mask on data address when matching against COMP"
line.long 0x08 "DW_FUNCTION1,DW Function Register 1"
bitfld.long 0x08 24. " MATCHED ,Comparator match" "No match,Match"
bitfld.long 0x08 0.--3. " FUNCTION , Settings for DW Function Registers" "Disabled,Reserved,Reserved,Reserved,On PC match,Read address,Write address,R/W address,?..."
else
newline
textline "DWT component base address not specified"
newline
endif
tree.end
tree.end
AUTOINDENT.POP
tree.end
autoindent.on center tree
tree "CM0 (Cortex-M0 System Bus (ARM PPB Peripherals))"
base ad:0xE0000000
group.long 0x1FD0++0x03
line.long 0x00 "DWT_PID4,Watchpoint Unit CoreSight ROM Table Peripheral ID #4"
hexmask.long 0x00 0.--31. 1. "VALUE,Peripheral ID #4"
group.long 0x1FE0++0x03
line.long 0x00 "DWT_PID0,Watchpoint Unit CoreSight ROM Table Peripheral ID #0"
hexmask.long 0x00 0.--31. 1. "VALUE,Peripheral ID #0"
group.long 0x1FE4++0x03
line.long 0x00 "DWT_PID1,Watchpoint Unit CoreSight ROM Table Peripheral ID #1"
hexmask.long 0x00 0.--31. 1. "VALUE,Peripheral ID #1"
group.long 0x1FE8++0x03
line.long 0x00 "DWT_PID2,Watchpoint Unit CoreSight ROM Table Peripheral ID #2"
hexmask.long 0x00 0.--31. 1. "VALUE,Peripheral ID #2"
group.long 0x1FEC++0x03
line.long 0x00 "DWT_PID3,Watchpoint Unit CoreSight ROM Table Peripheral ID #3"
hexmask.long 0x00 0.--31. 1. "VALUE,Peripheral ID #3"
group.long 0x1FF0++0x03
line.long 0x00 "DWT_CID0,Watchpoint Unit CoreSight ROM Table Component ID #0"
hexmask.long 0x00 0.--31. 1. "VALUE,Component ID #0"
group.long 0x1FF4++0x03
line.long 0x00 "DWT_CID1,Watchpoint Unit CoreSight ROM Table Component ID #1"
hexmask.long 0x00 0.--31. 1. "VALUE,Component ID #1"
group.long 0x1FF8++0x03
line.long 0x00 "DWT_CID2,Watchpoint Unit CoreSight ROM Table Component ID #2"
hexmask.long 0x00 0.--31. 1. "VALUE,Component ID #2"
group.long 0x1FFC++0x03
line.long 0x00 "DWT_CID3,Watchpoint Unit CoreSight ROM Table Component ID #3"
hexmask.long 0x00 0.--31. 1. "VALUE,Component ID #3"
group.long 0x2FD0++0x03
line.long 0x00 "BP_PID4,Breakpoint Unit CoreSight ROM Table Peripheral ID #4"
hexmask.long 0x00 0.--31. 1. "VALUE,Peripheral ID #4"
group.long 0x2FE0++0x03
line.long 0x00 "BP_PID0,Breakpoint Unit CoreSight ROM Table Peripheral ID #0"
hexmask.long 0x00 0.--31. 1. "VALUE,Peripheral ID #0"
group.long 0x2FE4++0x03
line.long 0x00 "BP_PID1,Breakpoint Unit CoreSight ROM Table Peripheral ID #1"
hexmask.long 0x00 0.--31. 1. "VALUE,Peripheral ID #1"
group.long 0x2FE8++0x03
line.long 0x00 "BP_PID2,Breakpoint Unit CoreSight ROM Table Peripheral ID #2"
hexmask.long 0x00 0.--31. 1. "VALUE,Peripheral ID #2"
group.long 0x2FEC++0x03
line.long 0x00 "BP_PID3,Breakpoint Unit CoreSight ROM Table Peripheral ID #3"
hexmask.long 0x00 0.--31. 1. "VALUE,Peripheral ID #3"
group.long 0x2FF0++0x03
line.long 0x00 "BP_CID0,Breakpoint Unit CoreSight ROM Table Component ID #0"
hexmask.long 0x00 0.--31. 1. "VALUE,Component ID #0"
group.long 0x2FF4++0x03
line.long 0x00 "BP_CID1,Breakpoint Unit CoreSight ROM Table Component ID #1"
hexmask.long 0x00 0.--31. 1. "VALUE,Component ID #1"
group.long 0x2FF8++0x03
line.long 0x00 "BP_CID2,Breakpoint Unit CoreSight ROM Table Component ID #2"
hexmask.long 0x00 0.--31. 1. "VALUE,Component ID #2"
group.long 0x2FFC++0x03
line.long 0x00 "BP_CID3,Breakpoint Unit CoreSight ROM Table Component ID #3"
hexmask.long 0x00 0.--31. 1. "VALUE,Component ID #3"
group.long 0xE010++0x03
line.long 0x00 "SYST_CSR,SysTick Control & Status"
rbitfld.long 0x00 16. "COUNTFLAG,Indicates whether the counter has counted to 0 since the last read of this register:?'0': counter has not counted to 0 .?'1': counter has counted to 0 .??COUNTFLAG is set to '1' by a count transition from 1 to 0 .?COUNTFLAG is cleared to '0'.." "0,1"
bitfld.long 0x00 2. "CLKSOURCE,Indicates the SysTick counter clock source:?'0': SysTick uses the low frequency clock clk_lf" "0,1"
newline
bitfld.long 0x00 1. "TICKINT,Indicates whether counting to 0 causes the status of the SysTick exception to change to pending:?'0': count to 0 does not affect the SysTick exception status.?'1': count to 0 changes the SysTick exception status to pending.??Changing the value.." "0,1"
bitfld.long 0x00 0. "ENABLE,Indicates the enabled status of the SysTick counter:?'0': counter is disabled.?'1': counter is operating" "0,1"
group.long 0xE014++0x03
line.long 0x00 "SYST_RVR,SysTick Reload Value"
hexmask.long.tbyte 0x00 0.--23. 1. "RELOAD,The value to load into the SYST_CVR register when the counter reaches 0"
group.long 0xE018++0x03
line.long 0x00 "SYST_CVR,SysTick Current Value"
hexmask.long.tbyte 0x00 0.--23. 1. "CURRENT,Current counter value.?This is the value of the counter at the time it is sampled"
group.long 0xE01C++0x03
line.long 0x00 "SYST_CALIB,SysTick Calibration Value"
rbitfld.long 0x00 31. "NOREF,Indicates whether a implementation defined reference clock is provided:?'0': the reference clock is provided.?'1': the reference clock is not provided.?When this bit is '1' the SYST_CSR.CLKSOURCEis forced to '1' and cannot be cleared to '0'.??In.." "0,1"
rbitfld.long 0x00 30. "SKEW,Indicates whether the 10ms calibration value is exact:?'0': 10ms calibration value is exact.?'1': 10ms calibration value is inexact because of the clock frequency.??In PSoC4A-BLE (and later products) SysTick counter functionality on the low.." "0,1"
newline
hexmask.long.tbyte 0x00 0.--23. 1. "TENMS,Optionally holds a reload value to be used for 10ms (100Hz) timing subject to system clock skew errors"
group.long 0xE100++0x03
line.long 0x00 "ISER,Interrupt Set-Enable Register"
hexmask.long 0x00 0.--31. 1. "SETENA,Enables or reads the enabled state of one or more interrupts"
group.long 0xE180++0x03
line.long 0x00 "ICER,Interrupt Clear Enable Register"
hexmask.long 0x00 0.--31. 1. "CLRENA,Disables or reads the enabled state of one or more interrupts"
group.long 0xE200++0x03
line.long 0x00 "ISPR,Interrupt Set-Pending Register"
hexmask.long 0x00 0.--31. 1. "SETPEND,Changes the state of one or more interrupts to pending"
group.long 0xE280++0x03
line.long 0x00 "ICPR,Interrupt Clear-Pending Register"
hexmask.long 0x00 0.--31. 1. "CLRPEND,Changes the state of one or more interrupts to not pending"
repeat 8. (strings "0" "1" "2" "3" "4" "5" "6" "7" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C )
group.long ($2+0xE400)++0x03
line.long 0x00 "IPR$1,Interrupt Priority Registers"
bitfld.long 0x00 30.--31. "PRI_N3,Priority of interrupt number N+3" "0,1,2,3"
bitfld.long 0x00 22.--23. "PRI_N2,Priority of interrupt number N+2" "0,1,2,3"
newline
bitfld.long 0x00 14.--15. "PRI_N1,Priority of interrupt number N+1" "0,1,2,3"
bitfld.long 0x00 6.--7. "PRI_N0,Priority of interrupt number N" "0,1,2,3"
repeat.end
group.long 0xED00++0x03
line.long 0x00 "CPUID,CPUID Register"
hexmask.long.byte 0x00 24.--31. 1. "IMPLEMENTER,Implementer code for ARM"
rbitfld.long 0x00 20.--23. "VARIANT,Implementation defined" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
rbitfld.long 0x00 16.--19. "CONSTANT,Indicates the architecture ARMv6-M" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x00 4.--15. 1. "PARTNO,Indicates part number Cortex-M0"
newline
rbitfld.long 0x00 0.--3. "REVISION,Indicates revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xED04++0x03
line.long 0x00 "ICSR,Interrupt Control State Register"
bitfld.long 0x00 31. "NMIPENDSET,Activates an NMI exception or reads back the current state.?Because NMI is the highest priority exception it activates as soon as it is registered" "0,1"
bitfld.long 0x00 28. "PENDSVSET,Sets a pending PendSV interrupt or reads back the current state" "0,1"
newline
bitfld.long 0x00 27. "PENDSVCLR,Clears a pending PendSV interrupt" "0,1"
bitfld.long 0x00 26. "PENDSTSETb,Sets a pending SysTick or reads back the current state" "0,1"
newline
bitfld.long 0x00 25. "PENDSTCLR,Clears a pending SysTick whether set here or by the timer hardware" "0,1"
rbitfld.long 0x00 23. "ISRPREEMPT,Indicates whether a pending exception will be serviced on exit from debug halt state" "0,1"
newline
rbitfld.long 0x00 22. "ISRPENDING,Indicates if an external configurable NVIC generated interrupt is pending" "0,1"
hexmask.long.word 0x00 12.--20. 1. "VECTPENDING,The exception number for the highest priority pending exception"
newline
hexmask.long.word 0x00 0.--8. 1. "VECTACTIVE,The exception number for the current executing exception"
group.long 0xED0C++0x03
line.long 0x00 "AIRCR,Application Interrupt and Reset Control Register"
hexmask.long.word 0x00 16.--31. 1. "VECTKEY,Vector Key"
rbitfld.long 0x00 15. "ENDIANNESS,Indicates the memory system data endianness:?0 little endian?1 big endian.?See Endian support on page A3-44 for more information" "0,1"
newline
bitfld.long 0x00 2. "SYSRESETREQ,System Reset Request" "0,1"
bitfld.long 0x00 1. "VECTCLRACTIVE,Clears all active state information for fixed and configurable?exceptions" "0,1"
group.long 0xED10++0x03
line.long 0x00 "SCR,System Control Register"
bitfld.long 0x00 4. "SEVONPEND,Determines whether an interrupt transition from inactive state to pending state is a wakeup event:?0: transitions from inactive to pending are not wakeup events.?1: transitions from inactive to pending are wakeup events.?See WFE on page A6-197.." "0,1"
bitfld.long 0x00 2. "SLEEPDEEP,An implementation can use this bit to select DeepSleep/Hibernate power modes upon execution of WFI/WFE:?0: Select Sleep mode?1: Select DeepSleep/Hibernate (depends on PWR_CONTROL.HIBERNATE)" "0,1"
newline
bitfld.long 0x00 1. "SLEEPONEXIT,Determines whether on an exit from an ISR that returns to the base level of execution priority the processor enters a sleep state:?0 do not enter sleep state.?1 enter sleep state.?See Power management on page B1-240 for more information" "0,1"
group.long 0xED14++0x03
line.long 0x00 "CCR,Configuration and Control Register"
rbitfld.long 0x00 9. "STKALIGN," "0,1"
rbitfld.long 0x00 3. "UNALIGN_TRP," "0,1"
group.long 0xED1C++0x03
line.long 0x00 "SHPR2,System Handler Priority Register 2"
bitfld.long 0x00 30.--31. "PRI_11,Priority of system handler 11 SVCall" "0,1,2,3"
group.long 0xED20++0x03
line.long 0x00 "SHPR3,System Handler Priority Register 3"
bitfld.long 0x00 30.--31. "PRI_15,Priority of system handler 15 SysTick" "0,1,2,3"
bitfld.long 0x00 22.--23. "PRI_14,Priority of system handler 14 PendSV" "0,1,2,3"
group.long 0xED24++0x03
line.long 0x00 "SHCSR,System Handler Control and State Register"
bitfld.long 0x00 15. "SVCALLPENDED,0 SVCall is not pending.?1 SVCall is pending.?This bit reflects the pending state on a read and updates the pending state to the value written on a" "0,1"
group.long 0xEFD0++0x03
line.long 0x00 "SCS_PID4,System Control Space ROM Table Peripheral ID #4"
hexmask.long 0x00 0.--31. 1. "VALUE,Peripheral ID #4"
group.long 0xEFE0++0x03
line.long 0x00 "SCS_PID0,System Control Space ROM Table Peripheral ID #0"
hexmask.long 0x00 0.--31. 1. "VALUE,Peripheral ID #0"
group.long 0xEFE4++0x03
line.long 0x00 "SCS_PID1,System Control Space ROM Table Peripheral ID #1"
hexmask.long 0x00 0.--31. 1. "VALUE,Peripheral ID #1"
group.long 0xEFE8++0x03
line.long 0x00 "SCS_PID2,System Control Space ROM Table Peripheral ID #2"
hexmask.long 0x00 0.--31. 1. "VALUE,Peripheral ID #2"
group.long 0xEFEC++0x03
line.long 0x00 "SCS_PID3,System Control Space ROM Table Peripheral ID #3"
hexmask.long 0x00 0.--31. 1. "VALUE,Peripheral ID #3"
group.long 0xEFF0++0x03
line.long 0x00 "SCS_CID0,System Control Space ROM Table Component ID #0"
hexmask.long 0x00 0.--31. 1. "VALUE,Component ID #0"
group.long 0xEFF4++0x03
line.long 0x00 "SCS_CID1,System Control Space ROM Table Component ID #1"
hexmask.long 0x00 0.--31. 1. "VALUE,Component ID #1"
group.long 0xEFF8++0x03
line.long 0x00 "SCS_CID2,System Control Space ROM Table Component ID #2"
hexmask.long 0x00 0.--31. 1. "VALUE,Component ID #2"
group.long 0xEFFC++0x03
line.long 0x00 "SCS_CID3,System Control Space ROM Table Component ID #3"
hexmask.long 0x00 0.--31. 1. "VALUE,Component ID #3"
group.long 0xFF000++0x03
line.long 0x00 "ROM_SCS,CM0 CoreSight ROM Table Peripheral #0"
hexmask.long 0x00 0.--31. 1. "VALUE,Offset to SCS ROM Table"
group.long 0xFF004++0x03
line.long 0x00 "ROM_DWT,CM0 CoreSight ROM Table Peripheral #1"
hexmask.long 0x00 0.--31. 1. "VALUE,Offset to DWT ROM Table"
group.long 0xFF008++0x03
line.long 0x00 "ROM_BPU,CM0 CoreSight ROM Table Peripheral #2"
hexmask.long 0x00 0.--31. 1. "VALUE,Offset to BPU ROM Table"
group.long 0xFF00C++0x03
line.long 0x00 "ROM_END,CM0 CoreSight ROM Table End Marker"
hexmask.long 0x00 0.--31. 1. "VALUE,End marker in peripheral list"
group.long 0xFFFCC++0x03
line.long 0x00 "ROM_CSMT,CM0 CoreSight ROM Table Memory Type"
hexmask.long 0x00 0.--31. 1. "VALUE,Memory Type"
group.long 0xFFFD0++0x03
line.long 0x00 "ROM_PID4,CM0 CoreSight ROM Table Peripheral ID #4"
hexmask.long 0x00 0.--31. 1. "VALUE,Peripheral ID #4"
group.long 0xFFFE0++0x03
line.long 0x00 "ROM_PID0,CM0 CoreSight ROM Table Peripheral ID #0"
hexmask.long 0x00 0.--31. 1. "VALUE,Peripheral ID #0"
group.long 0xFFFE4++0x03
line.long 0x00 "ROM_PID1,CM0 CoreSight ROM Table Peripheral ID #1"
hexmask.long 0x00 0.--31. 1. "VALUE,Peripheral ID #1"
group.long 0xFFFE8++0x03
line.long 0x00 "ROM_PID2,CM0 CoreSight ROM Table Peripheral ID #2"
hexmask.long 0x00 0.--31. 1. "VALUE,Peripheral ID #2"
group.long 0xFFFEC++0x03
line.long 0x00 "ROM_PID3,CM0 CoreSight ROM Table Peripheral ID #3"
hexmask.long 0x00 0.--31. 1. "VALUE,Peripheral ID #3"
group.long 0xFFFF0++0x03
line.long 0x00 "ROM_CID0,CM0 CoreSight ROM Table Component ID #0"
hexmask.long 0x00 0.--31. 1. "VALUE,Component ID #0"
group.long 0xFFFF4++0x03
line.long 0x00 "ROM_CID1,CM0 CoreSight ROM Table Component ID #1"
hexmask.long 0x00 0.--31. 1. "VALUE,Component ID #1"
group.long 0xFFFF8++0x03
line.long 0x00 "ROM_CID2,CM0 CoreSight ROM Table Component ID #2"
hexmask.long 0x00 0.--31. 1. "VALUE,Component ID #2"
group.long 0xFFFFC++0x03
line.long 0x00 "ROM_CID3,CM0 CoreSight ROM Table Component ID #3"
hexmask.long 0x00 0.--31. 1. "VALUE,Component ID #3"
tree.end
tree "CPUSS (CPU Subsystem)"
base ad:0x40100000
group.long 0x00++0x03
line.long 0x00 "CONFIG,Configuration register"
bitfld.long 0x00 0. "VECT_IN_RAM,0': Vector Table is located at 0x0000:0000 in flash?'1': Vector Table is located at 0x2000:0000 in SRAM?Note that vectors for RESET and FAULT are always fetched from ROM" "0,1"
group.long 0x04++0x03
line.long 0x00 "SYSREQ,SYSCALL control register"
bitfld.long 0x00 31. "SYSCALL_REQ,CPU/DAP writes a '1' to this field to request a SystemCall" "0,1"
rbitfld.long 0x00 30. "HMASTER_0,Indicates the source of the write access to the SYSREQ register.?'0': CPU write access.?'1': DAP write access.?HW sets this field when the SYSREQ register is written to and SYSCALL_REQ is '0' (the last time it is set is when SW sets.." "0,1"
newline
rbitfld.long 0x00 29. "ROM_ACCESS_EN,Indicates that executing from Boot ROM is enabled" "0,1"
bitfld.long 0x00 28. "PRIVILEGED,Indicates whether the system is in privileged ('1') or user mode ('0')" "0,1"
newline
bitfld.long 0x00 27. "DIS_RESET_VECT_REL,Disable Reset Vector fetch relocation:?'0': CPU accesses to locations 0x0000:0000" "0,1"
hexmask.long.word 0x00 0.--15. 1. "SYSCALL_COMMAND,Opcode of the system call being requested"
group.long 0x08++0x03
line.long 0x00 "SYSARG,SYSARG control register"
hexmask.long 0x00 0.--31. 1. "SYSCALL_ARG,Argument to System Call specified in SYSREQ"
group.long 0x0C++0x03
line.long 0x00 "PROTECTION,Protection control register"
bitfld.long 0x00 31. "PROTECTION_LOCK,Setting this field will block (ignore) any further writes to the PROTECTION_MODE field in this register" "0,1"
bitfld.long 0x00 0.--3. "PROTECTION_MODE,Current protection mode this field is available as a global signal everywhere in the system" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x10++0x03
line.long 0x00 "PRIV_ROM,ROM privilege register"
abitfld.long 0x00 0.--7. "BROM_PROT_LIMIT,Indicates the limit where the privileged area of the Boot ROM partition starts in increments of 256 Bytes.?" "0x00=0: Entire Boot ROM is Privileged.?,0x01=1: First 256 Bytes are User"
group.long 0x14++0x03
line.long 0x00 "PRIV_RAM,RAM privilege register"
abitfld.long 0x00 0.--8. "RAM_PROT_LIMIT,Indicates the limit where the privileged area of SRAM starts in increments of 256 Bytes.?" "0x000=0: Entire SRAM is Privileged.?,0x001=1: First 256 Bytes are User.."
group.long 0x18++0x03
line.long 0x00 "PRIV_FLASH,ROM privilege register"
abitfld.long 0x00 0.--10. "FLASH_PROT_LIMIT,Indicates the limit where the privileged area of flash starts in increments of 256 Bytes.?" "0x000=0: Entire flash is Privileged.?,0x001=1: First 256 Bytes are User.."
group.long 0x1C++0x03
line.long 0x00 "WOUNDING,Wounding register"
bitfld.long 0x00 20.--22. "FLASH_WOUND,Indicates the amount of accessible flash in this part" "0: entire memory accessible?,1: first 1/2 of the memory accessible?,2: first 1/4 of the memory accessible?,3: first 1/8 of the memory accessible?,4: first 1/16 of the memory accessible?,5: first 1/32 of the memory accessible?,6: first 1/64 of the memory accessible?,7: first 1/128 of the memory accessible (used for"
bitfld.long 0x00 16.--18. "RAM_WOUND,Indicates the amount of accessible RAM 0 memory capacitty in this part" "0: entire memory accessible?,1: first 1/2 of the memory accessible?,2: first 1/4 of the memory accessible?,3: first 1/8 of the memory accessible?,4: first 1/16 of the memory accessible?,5: first 1/32 of the memory accessible?,6: first 1/64 of the memory accessible?,7: first 1/128 of the memory accessible"
group.long 0x30++0x03
line.long 0x00 "FLASH_CTL,FLASH control register"
bitfld.long 0x00 8. "FLASH_INVALIDATE,1': Invalidates the content of the flash controller's buffers" "0,1"
bitfld.long 0x00 4. "PREF_EN,Prefetch enable:?'0': disabled" "0,1"
newline
bitfld.long 0x00 0.--1. "FLASH_WS,Amount of ROM wait states:?" "0: 0 wait states (fast flash: [0 24] MHz system,1: 1 wait state (fast flash: [24 48] MHz system,2: 2 wait states (slow flash: [32 48] MHz system,3: undefined"
group.long 0x34++0x03
line.long 0x00 "ROM_CTL,ROM control register"
bitfld.long 0x00 0. "ROM_WS,Amount of ROM wait states:?'0': 0 wait states" "0,1"
tree.end
tree "CSD (Capsense Controller)"
base ad:0x40080000
group.long 0x00++0x03
line.long 0x00 "ID,ID & Revision Number"
hexmask.long.word 0x00 16.--31. 1. "REVISION,the version number is 0x0001"
hexmask.long.word 0x00 0.--15. 1. "ID,the ID of CSD peripheral is 0xE0E1"
group.long 0x04++0x03
line.long 0x00 "CONFIG,Configuration and Control"
bitfld.long 0x00 31. "ENABLE,Master enable of the CSD IP" "0,1"
bitfld.long 0x00 30. "DDFTCOMP,Changes comp_out signal for DFT purpose only" "0: No description available,1: No description available"
newline
bitfld.long 0x00 29. "ADFTEN,When selected convert IDAC1/2 outputs from current to voltage before sending to AMUXBUS-A/B" "0,1"
bitfld.long 0x00 26.--28. "DDFTSEL,Changes the dsi_sample_out signal from its normal function (sample_out) to a selection of other DDFT signals" "0: No description available,1: No description available,2: No description available,3: No description available,4: No description available,?..."
newline
bitfld.long 0x00 23.--24. "REFBUF_DRV,Current drive strength for reference buffer" "0: No description available,1: No description available,2: No description available,3: No description available"
bitfld.long 0x00 22. "SENSE_INSEL,Selects how to connect the sensing comparator to the Cmod capacitor" "0: No description available,1: No description available"
newline
bitfld.long 0x00 21. "REBUF_OUTSEL,Selects which AMUXBUS the reference buffer connects to" "0: No description available,1: No description available"
bitfld.long 0x00 19. "SENSE_COMP_EN,Turns on the sense comparator circuit" "0,1"
newline
bitfld.long 0x00 18. "MUTUAL_CAP,Enables mutual cap sensing mode" "0: No description available,1: No description available"
bitfld.long 0x00 17. "POLARITY2,For normal CSD operations this field is not used" "0: No description available,1: No description available"
newline
bitfld.long 0x00 16. "POLARITY,Selects the polarity of the sensing operation" "0: No description available,1: No description available"
bitfld.long 0x00 15. "COMP_PIN,Connects either the Cmod or Csh_tank sense return line to the reference buffer comparator" "0: No description available,1: No description available"
newline
bitfld.long 0x00 14. "COMP_MODE,Selects between charging of the Cmod/Csh_tank capacitor using the GPIO digital output buffer or the CSD reference buffer" "0: No description available,1: No description available"
bitfld.long 0x00 13. "REFBUF_EN,Enables the reference buffer/comparator circuits for charging Cmod/Csh_tank using the mode selected in COMP_MODE" "0,1"
newline
bitfld.long 0x00 12. "SENSE_EN,Enables the sense modulator output" "0,1"
bitfld.long 0x00 11. "SENSE_COMP_BW,Selects bandwidth for sensing comparator" "0: No description available,1: No description available"
newline
bitfld.long 0x00 9.--10. "SHIELD_DELAY,Selects the delay by which csd_shield is delayed relative to csd_sense" "0: No description available,?,2: No description available,3: No description available"
bitfld.long 0x00 8. "DSI_SENSE_EN,Enables the use of the dsi_sense_in input instead of the internally generated modulation signal to drive csd_sense and csd_shield signals" "0,1"
newline
bitfld.long 0x00 7. "PRS_12_8,Selects between 8 or 12b PRS sequence" "0: No description available,1: No description available"
bitfld.long 0x00 6. "PRS_SELECT,Selects between PRS or simple divide by 2 sense modulation" "0: No description available,1: No description available"
newline
bitfld.long 0x00 5. "PRS_CLEAR,When set forces the pseudo-random generator to it's initial state" "0,1"
bitfld.long 0x00 4. "DUAL_CAP_EN,Enables dual cap mode when MUTUAL_CAP=1 do not use when MUTUAL_CAP=0" "0: No description available,1: No description available"
newline
bitfld.long 0x00 3. "FILTER_ENABLE,Enables the digital filter on the CSD comparator" "0: No description available,1: No description available"
bitfld.long 0x00 2. "BYPASS_SEL,Selects whether to use CSD1 clock for modulation directly or use PRS/Divide-by-2 modulation (default)" "0: No description available,1: No description available"
newline
bitfld.long 0x00 1. "SAMPLE_SYNC,Enables double synchronizing of sample input from DSI (only relevant when DSI_SAMPLE_EN=1)" "0,1"
bitfld.long 0x00 0. "DSI_SAMPLE_EN,Enables the use of the dsi_sample_in input instead of the comparator output to strobe COUNTER" "0,1"
group.long 0x08++0x03
line.long 0x00 "IDAC,IDAC Configuration"
bitfld.long 0x00 30. "FEEDBACK_MODE,This bit controls whether during CSD operation the IDAC is controlled from the sampling flip-flop or directly from the comparator" "0: No description available,1: No description available"
bitfld.long 0x00 28. "POLARITY2_MIR,Mirror bit for POLARITY2 bit in CONFIG register" "0,1"
newline
bitfld.long 0x00 26. "IDAC2_RANGE,Current multiplier setting for IDAC2" "0: No description available,1: No description available"
bitfld.long 0x00 24.--25. "IDAC2_MODE,Controls the usage mode of IDAC2" "0: No description available,1: No description available,2: No description available,3: No description available"
newline
hexmask.long.byte 0x00 16.--22. 1. "IDAC2,Current setting for IDAC2 (7 bits)"
bitfld.long 0x00 12. "POLARITY1_MIR,Mirror bit for POLARITY bit in CONFIG register" "0,1"
newline
bitfld.long 0x00 10. "IDAC1_RANGE,Current multiplier setting for IDAC1" "0: No description available,1: No description available"
bitfld.long 0x00 8.--9. "IDAC1_MODE,Controls the usage mode of IDAC1" "0: No description available,1: No description available,2: No description available,3: No description available"
newline
hexmask.long.byte 0x00 0.--7. 1. "IDAC1,Current setting for IDAC1 (8 bits)"
group.long 0x0C++0x03
line.long 0x00 "COUNTER,CSD Counter Register"
hexmask.long.word 0x00 16.--31. 1. "PERIOD,The remaining period (in clk_csd2 cycles) during which COUNTER will count the comparator output count.?Firmware will write this field to the desired period after which it will start counting down to 0"
hexmask.long.word 0x00 0.--15. 1. "COUNTER,This field increments whenever the comparator is sampled and the sample is 1"
group.long 0x10++0x03
line.long 0x00 "STATUS,Status Register"
rbitfld.long 0x00 3. "SAMPLE,Output of main sensing comparator" "0,1"
rbitfld.long 0x00 2. "COMP_OUT,Output of reference buffer comparator used to charge up Cmod or Csh_tank" "0: No description available,1: No description available"
newline
rbitfld.long 0x00 1. "CSD_SENSE,Signal used to drive the Cs switches" "0,1"
rbitfld.long 0x00 0. "CSD_CHARGE,Qualified and possible inverted value of COMP_OUT that is used to drive GPIO's charging Cmod or Csh_tank" "0,1"
group.long 0x14++0x03
line.long 0x00 "INTR,CSD Interrupt Request Register"
bitfld.long 0x00 0. "CSD,The CSD IRQ bit is set" "0,1"
group.long 0x18++0x03
line.long 0x00 "INTR_SET,CSD Interrupt set register"
bitfld.long 0x00 0. "CSD,Write with '1' to set corresponding bit in interrupt request register" "0,1"
group.long 0x1C++0x03
line.long 0x00 "PWM,CSD PWM Register"
bitfld.long 0x00 4.--5. "PWM_SEL,The mode of the PWM modulator" "0: No description available,?,2: No description available,3: No description available"
bitfld.long 0x00 0.--3. "PWM_COUNT,The length of the modulation pulse in clk_csd2 cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xFF00++0x03
line.long 0x00 "TRIM1,CSD Trim Register"
bitfld.long 0x00 4.--7. "IDAC2_SRC_TRIM,IDAC2 trim bits for gain control in current source mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "IDAC1_SRC_TRIM,IDAC1 trim bits for gain control in current source mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xFF04++0x03
line.long 0x00 "TRIM2,CSD Trim Register"
bitfld.long 0x00 4.--7. "IDAC2_SNK_TRIM,IDAC2 trim bits for gain control in current sink mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "IDAC1_SNK_TRIM,IDAC1 trim bits for gain control in current sink mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
tree.end
tree "GPIO (General Purpose I/O Ports And Peripheral I/O Lines)"
base ad:0x40040000
group.long 0x1000++0x03
line.long 0x00 "INTR_CAUSE,Interrupt port cause register"
rbitfld.long 0x00 0.--3. "PORT_INT,Each IO port has an associated bit field in this register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
tree.end
tree "GPIO_PRT (GPIO port registers)"
repeat 2. (list 0. 1.) (list ad:0x40040000 ad:0x40040100)
tree "GPIO_PRT$1"
base $2
group.long 0x00++0x03
line.long 0x00 "DR,Port output data register"
bitfld.long 0x00 7. "DATA7,IO pad 7 output data" "0,1"
bitfld.long 0x00 6. "DATA6,IO pad 6 output data" "0,1"
newline
bitfld.long 0x00 5. "DATA5,IO pad 5 output data" "0,1"
bitfld.long 0x00 4. "DATA4,IO pad 4 output data" "0,1"
newline
bitfld.long 0x00 3. "DATA3,IO pad 3 output data" "0,1"
bitfld.long 0x00 2. "DATA2,IO pad 2 output data" "0,1"
newline
bitfld.long 0x00 1. "DATA1,IO pad 1 output data" "0,1"
bitfld.long 0x00 0. "DATA0,IO pad 0 output data" "0,1"
group.long 0x04++0x03
line.long 0x00 "PS,Port IO pad state register"
rbitfld.long 0x00 8. "FLT_DATA,Reads of this register return the logical state of the filtered pin" "0,1"
rbitfld.long 0x00 7. "DATA7,IO pad 7 state" "0,1"
newline
rbitfld.long 0x00 6. "DATA6,IO pad 6 state" "0,1"
rbitfld.long 0x00 5. "DATA5,IO pad 5 state" "0,1"
newline
rbitfld.long 0x00 4. "DATA4,IO pad 4 state" "0,1"
rbitfld.long 0x00 3. "DATA3,IO pad 3 state" "0,1"
newline
rbitfld.long 0x00 2. "DATA2,IO pad 2 state" "0,1"
rbitfld.long 0x00 1. "DATA1,IO pad 1 state" "0,1"
newline
rbitfld.long 0x00 0. "DATA0,IO pad 0 state:?1: Logic high if the pin voltage is above the input buffer threshold logic high.?0: Logic low if the pin voltage is below that threshold logic low.?If the drive mode for the pin is set to high Z Analog the pin state will read 0.." "0,1"
group.long 0x08++0x03
line.long 0x00 "PC,Port configuration register"
bitfld.long 0x00 25. "PORT_SLOW,This field controls the output edge rate of all pins on the port:?'0': fast.?'1': slow" "0,1"
bitfld.long 0x00 24. "PORT_VTRIP_SEL,The GPIO cells include a VTRIP_SEL signal to alter the input buffer voltage" "0,1"
newline
bitfld.long 0x00 21.--23. "DM7,The GPIO drive mode for IO pad 7" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 18.--20. "DM6,The GPIO drive mode for IO pad 6" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 15.--17. "DM5,The GPIO drive mode for IO pad 5" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "DM4,The GPIO drive mode for IO pad 4" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 9.--11. "DM3,The GPIO drive mode for IO pad 3" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--8. "DM2,The GPIO drive mode for IO pad 2" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 3.--5. "DM1,The GPIO drive mode for IO pad 1" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--2. "DM0,The GPIO drive mode for IO pad 0.?Note: when initializing IO's that are connected to a live bus (such as I2C) make sure the HSIOM is properly configured (HSIOM_PRT_SELx) before turning the IO on here to avoid producing glitches on the bus" "0: No description available,1: No description available,2: No description available,3: No description available,4: No description available,5: No description available,6: No description available,7: No description available"
group.long 0x0C++0x03
line.long 0x00 "INTR_CFG,Port interrupt configuration register"
bitfld.long 0x00 18.--20. "FLT_SEL,Selects which pin is routed through the 50ns glitch filter to provide a glitch-safe interrupt" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 16.--17. "FLT_EDGE_SEL,Same for the glitch filtered pin (selected by FLT_SELECT)" "0: No description available,1: No description available,2: No description available,3: No description available"
newline
bitfld.long 0x00 14.--15. "EDGE7_SEL,Sets which edge will trigger an IRQ for IO pad 7" "0,1,2,3"
bitfld.long 0x00 12.--13. "EDGE6_SEL,Sets which edge will trigger an IRQ for IO pad 6" "0,1,2,3"
newline
bitfld.long 0x00 10.--11. "EDGE5_SEL,Sets which edge will trigger an IRQ for IO pad 5" "0,1,2,3"
bitfld.long 0x00 8.--9. "EDGE4_SEL,Sets which edge will trigger an IRQ for IO pad 4" "0,1,2,3"
newline
bitfld.long 0x00 6.--7. "EDGE3_SEL,Sets which edge will trigger an IRQ for IO pad 3" "0,1,2,3"
bitfld.long 0x00 4.--5. "EDGE2_SEL,Sets which edge will trigger an IRQ for IO pad 2" "0,1,2,3"
newline
bitfld.long 0x00 2.--3. "EDGE1_SEL,Sets which edge will trigger an IRQ for IO pad 1" "0,1,2,3"
bitfld.long 0x00 0.--1. "EDGE0_SEL,Sets which edge will trigger an IRQ for IO pad 0" "0: No description available,1: No description available,2: No description available,3: No description available"
group.long 0x10++0x03
line.long 0x00 "INTR,Port interrupt status register"
rbitfld.long 0x00 24. "PS_FLT_DATA,This is a duplicate of the contents of the PS register provided here to allow reading of both pin state and interrupt state of the port in a single read operation" "0,1"
rbitfld.long 0x00 23. "PS_DATA7,No description available" "0,1"
newline
rbitfld.long 0x00 22. "PS_DATA6,No description available" "0,1"
rbitfld.long 0x00 21. "PS_DATA5,No description available" "0,1"
newline
rbitfld.long 0x00 20. "PS_DATA4,No description available" "0,1"
rbitfld.long 0x00 19. "PS_DATA3,No description available" "0,1"
newline
rbitfld.long 0x00 18. "PS_DATA2,No description available" "0,1"
rbitfld.long 0x00 17. "PS_DATA1,No description available" "0,1"
newline
rbitfld.long 0x00 16. "PS_DATA0,`" "0,1"
bitfld.long 0x00 8. "FLT_DATA,Deglitched interrupt pending (selected by FLT_SELECT)" "0,1"
newline
bitfld.long 0x00 7. "DATA7,Interrupt pending on IO pad 7" "0,1"
bitfld.long 0x00 6. "DATA6,Interrupt pending on IO pad 6" "0,1"
newline
bitfld.long 0x00 5. "DATA5,Interrupt pending on IO pad 5" "0,1"
bitfld.long 0x00 4. "DATA4,Interrupt pending on IO pad 4" "0,1"
newline
bitfld.long 0x00 3. "DATA3,Interrupt pending on IO pad 3" "0,1"
bitfld.long 0x00 2. "DATA2,Interrupt pending on IO pad 2" "0,1"
newline
bitfld.long 0x00 1. "DATA1,Interrupt pending on IO pad 1" "0,1"
bitfld.long 0x00 0. "DATA0,Interrupt pending on IO pad 0" "0,1"
group.long 0x18++0x03
line.long 0x00 "PC2,Port configuration register 2"
bitfld.long 0x00 7. "INP_DIS7,Disables the input buffer for IO pad 7" "0,1"
bitfld.long 0x00 6. "INP_DIS6,Disables the input buffer for IO pad 6" "0,1"
newline
bitfld.long 0x00 5. "INP_DIS5,Disables the input buffer for IO pad 5" "0,1"
bitfld.long 0x00 4. "INP_DIS4,Disables the input buffer for IO pad 4" "0,1"
newline
bitfld.long 0x00 3. "INP_DIS3,Disables the input buffer for IO pad 3" "0,1"
bitfld.long 0x00 2. "INP_DIS2,Disables the input buffer for IO pad 2" "0,1"
newline
bitfld.long 0x00 1. "INP_DIS1,Disables the input buffer for IO pad 1" "0,1"
bitfld.long 0x00 0. "INP_DIS0,Disables the input buffer for IO pad 0 independent of the port control drive mode (PC.DM)" "0,1"
group.long 0x40++0x03
line.long 0x00 "DR_SET,Port output data set register"
hexmask.long.byte 0x00 0.--7. 1. "DATA,IO pad i:?'0': Output state DR.DATA[i] not affected.?'1': Output state DR.DATA[i] set to '1'"
group.long 0x44++0x03
line.long 0x00 "DR_CLR,Port output data clear register"
hexmask.long.byte 0x00 0.--7. 1. "DATA,IO pad i:?'0': Output state DR.DATA[i] not affected.?'1': Output state DR.DATA[i] set to '0'"
group.long 0x48++0x03
line.long 0x00 "DR_INV,Port output data invert register"
hexmask.long.byte 0x00 0.--7. 1. "DATA,IO pad i:?'0': Output state DR.DATA[i] not affected.?'1': Output state DR.DATA[i] inverted ('0' => '1' '1' => '0')"
tree.end
repeat.end
tree "GPIO_PRT2"
base ad:0x40040200
group.long 0x00++0x03
line.long 0x00 "DR,Port output data register"
bitfld.long 0x00 0. "DATA0,IO pad 0 output data" "0,1"
group.long 0x04++0x03
line.long 0x00 "PS,Port IO pad state register"
rbitfld.long 0x00 8. "FLT_DATA,Reads of this register return the logical state of the filtered pin" "0,1"
rbitfld.long 0x00 0. "DATA0,IO pad 0 state:?1: Logic high if the pin voltage is above the input buffer threshold logic high.?0: Logic low if the pin voltage is below that threshold logic low.?If the drive mode for the pin is set to high Z Analog the pin state will read 0.." "0,1"
group.long 0x08++0x03
line.long 0x00 "PC,Port configuration register"
bitfld.long 0x00 25. "PORT_SLOW,This field controls the output edge rate of all pins on the port:?'0': fast.?'1': slow" "0,1"
bitfld.long 0x00 24. "PORT_VTRIP_SEL,The GPIO cells include a VTRIP_SEL signal to alter the input buffer voltage" "0,1"
newline
bitfld.long 0x00 0.--2. "DM0,The GPIO drive mode for IO pad 0.?Note: when initializing IO's that are connected to a live bus (such as I2C) make sure the HSIOM is properly configured (HSIOM_PRT_SELx) before turning the IO on here to avoid producing glitches on the bus" "0: No description available,1: No description available,2: No description available,3: No description available,4: No description available,5: No description available,6: No description available,7: No description available"
group.long 0x0C++0x03
line.long 0x00 "INTR_CFG,Port interrupt configuration register"
bitfld.long 0x00 18.--20. "FLT_SEL,Selects which pin is routed through the 50ns glitch filter to provide a glitch-safe interrupt" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 16.--17. "FLT_EDGE_SEL,Same for the glitch filtered pin (selected by FLT_SELECT)" "0: No description available,1: No description available,2: No description available,3: No description available"
newline
bitfld.long 0x00 0.--1. "EDGE0_SEL,Sets which edge will trigger an IRQ for IO pad 0" "0: No description available,1: No description available,2: No description available,3: No description available"
group.long 0x10++0x03
line.long 0x00 "INTR,Port interrupt status register"
rbitfld.long 0x00 24. "PS_FLT_DATA,This is a duplicate of the contents of the PS register provided here to allow reading of both pin state and interrupt state of the port in a single read operation" "0,1"
rbitfld.long 0x00 16. "PS_DATA0,`" "0,1"
newline
bitfld.long 0x00 8. "FLT_DATA,Deglitched interrupt pending (selected by FLT_SELECT)" "0,1"
bitfld.long 0x00 0. "DATA0,Interrupt pending on IO pad 0" "0,1"
group.long 0x18++0x03
line.long 0x00 "PC2,Port configuration register 2"
bitfld.long 0x00 0. "INP_DIS0,Disables the input buffer for IO pad 0 independent of the port control drive mode (PC.DM)" "0,1"
group.long 0x40++0x03
line.long 0x00 "DR_SET,Port output data set register"
hexmask.long.byte 0x00 0.--7. 1. "DATA,IO pad i:?'0': Output state DR.DATA[i] not affected.?'1': Output state DR.DATA[i] set to '1'"
group.long 0x44++0x03
line.long 0x00 "DR_CLR,Port output data clear register"
hexmask.long.byte 0x00 0.--7. 1. "DATA,IO pad i:?'0': Output state DR.DATA[i] not affected.?'1': Output state DR.DATA[i] set to '0'"
group.long 0x48++0x03
line.long 0x00 "DR_INV,Port output data invert register"
hexmask.long.byte 0x00 0.--7. 1. "DATA,IO pad i:?'0': Output state DR.DATA[i] not affected.?'1': Output state DR.DATA[i] inverted ('0' => '1' '1' => '0')"
tree.end
tree "GPIO_PRT3"
base ad:0x40040300
group.long 0x00++0x03
line.long 0x00 "DR,Port output data register"
bitfld.long 0x00 2. "DATA2,IO pad 2 output data" "0,1"
bitfld.long 0x00 1. "DATA1,IO pad 1 output data" "0,1"
newline
bitfld.long 0x00 0. "DATA0,IO pad 0 output data" "0,1"
group.long 0x04++0x03
line.long 0x00 "PS,Port IO pad state register"
rbitfld.long 0x00 8. "FLT_DATA,Reads of this register return the logical state of the filtered pin" "0,1"
rbitfld.long 0x00 2. "DATA2,IO pad 2 state" "0,1"
newline
rbitfld.long 0x00 1. "DATA1,IO pad 1 state" "0,1"
rbitfld.long 0x00 0. "DATA0,IO pad 0 state:?1: Logic high if the pin voltage is above the input buffer threshold logic high.?0: Logic low if the pin voltage is below that threshold logic low.?If the drive mode for the pin is set to high Z Analog the pin state will read 0.." "0,1"
group.long 0x08++0x03
line.long 0x00 "PC,Port configuration register"
bitfld.long 0x00 25. "PORT_SLOW,This field controls the output edge rate of all pins on the port:?'0': fast.?'1': slow" "0,1"
bitfld.long 0x00 24. "PORT_VTRIP_SEL,The GPIO cells include a VTRIP_SEL signal to alter the input buffer voltage" "0,1"
newline
bitfld.long 0x00 6.--8. "DM2,The GPIO drive mode for IO pad 2" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 3.--5. "DM1,The GPIO drive mode for IO pad 1" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 0.--2. "DM0,The GPIO drive mode for IO pad 0.?Note: when initializing IO's that are connected to a live bus (such as I2C) make sure the HSIOM is properly configured (HSIOM_PRT_SELx) before turning the IO on here to avoid producing glitches on the bus" "0: No description available,1: No description available,2: No description available,3: No description available,4: No description available,5: No description available,6: No description available,7: No description available"
group.long 0x0C++0x03
line.long 0x00 "INTR_CFG,Port interrupt configuration register"
bitfld.long 0x00 18.--20. "FLT_SEL,Selects which pin is routed through the 50ns glitch filter to provide a glitch-safe interrupt" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 16.--17. "FLT_EDGE_SEL,Same for the glitch filtered pin (selected by FLT_SELECT)" "0: No description available,1: No description available,2: No description available,3: No description available"
newline
bitfld.long 0x00 4.--5. "EDGE2_SEL,Sets which edge will trigger an IRQ for IO pad 2" "0,1,2,3"
bitfld.long 0x00 2.--3. "EDGE1_SEL,Sets which edge will trigger an IRQ for IO pad 1" "0,1,2,3"
newline
bitfld.long 0x00 0.--1. "EDGE0_SEL,Sets which edge will trigger an IRQ for IO pad 0" "0: No description available,1: No description available,2: No description available,3: No description available"
group.long 0x10++0x03
line.long 0x00 "INTR,Port interrupt status register"
rbitfld.long 0x00 24. "PS_FLT_DATA,This is a duplicate of the contents of the PS register provided here to allow reading of both pin state and interrupt state of the port in a single read operation" "0,1"
rbitfld.long 0x00 18. "PS_DATA2,No description available" "0,1"
newline
rbitfld.long 0x00 17. "PS_DATA1,No description available" "0,1"
rbitfld.long 0x00 16. "PS_DATA0,`" "0,1"
newline
bitfld.long 0x00 8. "FLT_DATA,Deglitched interrupt pending (selected by FLT_SELECT)" "0,1"
bitfld.long 0x00 2. "DATA2,Interrupt pending on IO pad 2" "0,1"
newline
bitfld.long 0x00 1. "DATA1,Interrupt pending on IO pad 1" "0,1"
bitfld.long 0x00 0. "DATA0,Interrupt pending on IO pad 0" "0,1"
group.long 0x18++0x03
line.long 0x00 "PC2,Port configuration register 2"
bitfld.long 0x00 2. "INP_DIS2,Disables the input buffer for IO pad 2" "0,1"
bitfld.long 0x00 1. "INP_DIS1,Disables the input buffer for IO pad 1" "0,1"
newline
bitfld.long 0x00 0. "INP_DIS0,Disables the input buffer for IO pad 0 independent of the port control drive mode (PC.DM)" "0,1"
group.long 0x40++0x03
line.long 0x00 "DR_SET,Port output data set register"
hexmask.long.byte 0x00 0.--7. 1. "DATA,IO pad i:?'0': Output state DR.DATA[i] not affected.?'1': Output state DR.DATA[i] set to '1'"
group.long 0x44++0x03
line.long 0x00 "DR_CLR,Port output data clear register"
hexmask.long.byte 0x00 0.--7. 1. "DATA,IO pad i:?'0': Output state DR.DATA[i] not affected.?'1': Output state DR.DATA[i] set to '0'"
group.long 0x48++0x03
line.long 0x00 "DR_INV,Port output data invert register"
hexmask.long.byte 0x00 0.--7. 1. "DATA,IO pad i:?'0': Output state DR.DATA[i] not affected.?'1': Output state DR.DATA[i] inverted ('0' => '1' '1' => '0')"
tree.end
tree.end
tree "HSIOM (High Speed IO Matrix (HSIOM))"
base ad:0x40020000
repeat 2. (strings "0" "1" )(list 0x0 0x100 )
group.long ($2+0x00)++0x03
line.long 0x00 "PORT_SEL$1,Port selection register"
bitfld.long 0x00 28.--31. "IO7_SEL,Selects connection for IO pad 7 route" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 24.--27. "IO6_SEL,Selects connection for IO pad 6 route" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 20.--23. "IO5_SEL,Selects connection for IO pad 5 route" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 16.--19. "IO4_SEL,Selects connection for IO pad 4 route" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 12.--15. "IO3_SEL,Selects connection for IO pad 3 route" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "IO2_SEL,Selects connection for IO pad 2 route" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "IO1_SEL,Selects connection for IO pad 1 route" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "IO0_SEL,Selects connection for IO pad 0 route" "0: No description available,1: No description available,2: No description available,3: No description available,4: No description available,5: No description available,6: No description available,7: No description available,8: No description available,9: No description available,10: No description available,11: No description available,12: No description available,13: No description available,14: No description available,15: No description available"
repeat.end
group.long 0x200++0x03
line.long 0x00 "PORT_SEL2,Port selection register"
bitfld.long 0x00 0.--3. "IO0_SEL,Selects connection for IO pad 0 route" "0: No description available,1: No description available,2: No description available,3: No description available,4: No description available,5: No description available,6: No description available,7: No description available,8: No description available,9: No description available,10: No description available,11: No description available,12: No description available,13: No description available,14: No description available,15: No description available"
group.long 0x300++0x03
line.long 0x00 "PORT_SEL3,Port selection register"
bitfld.long 0x00 8.--11. "IO2_SEL,Selects connection for IO pad 2 route" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 4.--7. "IO1_SEL,Selects connection for IO pad 1 route" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 0.--3. "IO0_SEL,Selects connection for IO pad 0 route" "0: No description available,1: No description available,2: No description available,3: No description available,4: No description available,5: No description available,6: No description available,7: No description available,8: No description available,9: No description available,10: No description available,11: No description available,12: No description available,13: No description available,14: No description available,15: No description available"
group.long 0x2000++0x03
line.long 0x00 "PUMP_CTL,Pump control"
bitfld.long 0x00 31. "ENABLED,Pump enabled:?'0': Disabled.?'1': Enabled" "0,1"
bitfld.long 0x00 0. "CLOCK_SEL,Clock select:?'0': External clock.?'1': Internal clock (deprecated)" "0,1"
tree.end
tree "PERI (Peripheral Interconnect)"
base ad:0x40010000
group.long 0x00++0x03
line.long 0x00 "DIV_CMD,Divider command register"
bitfld.long 0x00 31. "ENABLE,Clock divider enable command (mutually exclusive with DISABLE)" "0,1"
bitfld.long 0x00 30. "DISABLE,Clock divider disable command (mutually exlusive with ENABLE)" "0,1"
newline
bitfld.long 0x00 14.--15. "PA_SEL_TYPE,Specifies the divider type of the divider to which phase alignment is performed for the clock enable command:?0: 8.0 (integer) clock dividers.?1: 16.0 (integer) clock dividers.?2: 16.5 (fractional) clock dividers.?3: 24.5 (fractional) clock.." "0,1,2,3"
bitfld.long 0x00 8.--13. "PA_SEL_DIV,(PA_SEL_TYPE PA_SEL_DIV) pecifies the divider to which phase alignment is performed for the clock enable command" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 6.--7. "SEL_TYPE,Specifies the divider type of the divider on which the command is performed:?0: 8.0 (integer) clock dividers.?1: 16.0 (integer) clock dividers.?2: 16.5 (fractional) clock dividers.?3: 24.5 (fractional) clock dividers" "0,1,2,3"
bitfld.long 0x00 0.--5. "SEL_DIV,(SEL_TYPE SEL_DIV) specifies the divider on which the command (DISABLE/ENABLE) is performed.? ?If SEL_DIV is 63 and SEL_TYPE is 3 (default/reset value) no divider is specified and no clock signal(s) are generated" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
repeat 4. (strings "0" "1" "2" "3" )(list 0x00 0x04 0x08 0x0C )
group.long ($2+0x100)++0x03
line.long 0x00 "PCLK_CTL$1,Programmable clock control register"
bitfld.long 0x00 6.--7. "SEL_TYPE,Specifies divider type:?0: 8.0 (integer) clock dividers.?1: 16.0 (integer) clock dividers.?2: 16.5 (fractional) clock dividers.?3: 24.5 (fractional) clock dividers" "0,1,2,3"
bitfld.long 0x00 0.--1. "SEL_DIV,Specifies one of the dividers of the divider type specified by SEL_TYPE.? ?If SEL_DIV is 63 and SEL_TYPE is 3 (default/reset value) no divider is specified and no clock control signal(s) are generated.? ?When transitioning a clock between two.." "0,1,2,3"
repeat.end
repeat 4. (strings "0" "1" "2" "3" )(list 0x00 0x04 0x08 0x0C )
group.long ($2+0x300)++0x03
line.long 0x00 "DIV_16_CTL$1,Divider control register (for 16.0 divider)"
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
repeat.end
tree.end
tree "ROMTABLE (CoreSight ROM-Table with Cypress Vendor/Silicon ID)"
base ad:0xF0000000
group.long 0x00++0x03
line.long 0x00 "ADDR,Link to Cortex M0 ROM Table"
abitfld.long 0x00 12.--31. "ADDR_OFFSET,Address offset of the Cortex-M0 ROM Table base address (0xe00f:f000) wrt" "0x0E00F=57359: f,0x0F00F=61455: f"
rbitfld.long 0x00 1. "FORMAT_32BIT,ROM Table format:?'0: 8-bit format.?'1': 32-bit format" "0,1"
newline
rbitfld.long 0x00 0. "PRESENT,Entry present" "0,1"
group.long 0xFCC++0x03
line.long 0x00 "DID,Device Type Identifier register"
hexmask.long 0x00 0.--31. 1. "VALUE,"
group.long 0xFD0++0x03
line.long 0x00 "PID4,Peripheral Identification Register 4"
rbitfld.long 0x00 4.--7. "COUNT,Size of ROM Table is 2^COUNT * 4 KByte" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 0.--3. "JEP_CONTINUATION,JEP106 continuation code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
repeat 3. (strings "5" "6" "7" )(list 0x00 0x04 0x08 )
group.long ($2+0xFD4)++0x03
line.long 0x00 "PID$1,Peripheral Identification Register 5"
hexmask.long 0x00 0.--31. 1. "VALUE,"
repeat.end
group.long 0xFE0++0x03
line.long 0x00 "PID0,Peripheral Identification Register 0"
hexmask.long.byte 0x00 0.--7. 1. "PN_MIN,JEP106 part number"
group.long 0xFE4++0x03
line.long 0x00 "PID1,Peripheral Identification Register 1"
rbitfld.long 0x00 4.--7. "JEPID_MIN,JEP106 vendor id" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 0.--3. "PN_MAJ,JEP106 part number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xFE8++0x03
line.long 0x00 "PID2,Peripheral Identification Register 2"
rbitfld.long 0x00 4.--7. "REV,Major REVision number (chip specific)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 0.--2. "JEPID_MAJ,JEP106 vendor id" "0,1,2,3,4,5,6,7"
group.long 0xFEC++0x03
line.long 0x00 "PID3,Peripheral Identification Register 3"
rbitfld.long 0x00 4.--7. "REV_AND,Minor REVision number (chip specific)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 0.--3. "CM,Customer modified field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xFF0++0x03
line.long 0x00 "CID0,Component Identification Register 0"
hexmask.long 0x00 0.--31. 1. "VALUE,Component identification byte 0 of 4-byte component identification 0xB105:100D"
group.long 0xFF4++0x03
line.long 0x00 "CID1,Component Identification Register 1"
hexmask.long 0x00 0.--31. 1. "VALUE,Component identification byte 1 of 4-byte component identification 0xB105:100D"
group.long 0xFF8++0x03
line.long 0x00 "CID2,Component Identification Register 2"
hexmask.long 0x00 0.--31. 1. "VALUE,Component identification byte 2 of 4-byte component identification 0xB105:100D"
group.long 0xFFC++0x03
line.long 0x00 "CID3,Component Identification Register 3"
hexmask.long 0x00 0.--31. 1. "VALUE,Component identification byte 3 of 4-byte component identification 0xB105:100D"
tree.end
tree "SCB (Serial Communications Block (SPI/UART/I2C))"
base ad:0x40060000
group.long 0x00++0x03
line.long 0x00 "CTRL,Generic control register"
bitfld.long 0x00 31. "ENABLED,IP enabled ('1') or not ('0')" "0,1"
bitfld.long 0x00 24.--25. "MODE,Mode of operation (3: Reserved)" "0: No description available,1: No description available,2: No description available,?..."
newline
bitfld.long 0x00 17. "BLOCK,Only used in externally clocked mode" "0,1"
bitfld.long 0x00 16. "ADDR_ACCEPT,Determines whether a received matching address is accepted in the RX FIFO ('1') or not ('0').??In I2C mode this field is used to allow the slave to put the received slave address or general call address in the RX FIFO" "0,1"
newline
bitfld.long 0x00 11. "BYTE_MODE,Determines the number of bits per FIFO data element:?'0': 16-bit FIFO data elements.?'1': 8-bit FIFO data elements" "0,1"
bitfld.long 0x00 10. "EZ_MODE,Non EZ mode ('0') or EZ mode ('1')" "0,1"
newline
bitfld.long 0x00 9. "EC_OP_MODE,Internally clocked mode ('0') or externally clocked mode ('1') operation" "0,1"
bitfld.long 0x00 8. "EC_AM_MODE,Internally clocked mode ('0') or externally clocked mode ('1') address matching (I2C) or selection (SPI)" "0,1"
newline
bitfld.long 0x00 0.--3. "OVS,Serial interface bit period oversampling factor expressed in lP clock cycles" "0: 16 times oversampling.? IP clock frequency of,1: 32 times oversampling.? IP clock frequency of,2: 48 times oversampling.? IP clock frequency of,3: 96 times oversampling.? IP clock frequency of,4: 192 times oversampling.? IP clock frequency of,5: 768 times oversampling.? IP clock frequency of,6: 1536 times oversampling.? IP clock frequency of,?..."
group.long 0x04++0x03
line.long 0x00 "STATUS,Generic status register"
rbitfld.long 0x00 0. "EC_BUSY,Inidicates whether the externally clocked logic is potentially accessing the EZ memory (this is only possible in EZ mode)" "0,1"
group.long 0x60++0x03
line.long 0x00 "I2C_CTRL,I2C control register"
bitfld.long 0x00 31. "MASTER_MODE,Master mode enabled ('1') or not ('0')" "0,1"
bitfld.long 0x00 30. "SLAVE_MODE,Slave mode enabled ('1') or not ('0')" "0,1"
newline
bitfld.long 0x00 16. "LOOPBACK,Local loopback control (does NOT affect the information on the pins)" "0,1"
bitfld.long 0x00 15. "S_NOT_READY_DATA_NACK,For internally clocked logic only" "0: clock stretching is performed (till the..,1: a received data element byte the slave is"
newline
bitfld.long 0x00 14. "S_NOT_READY_ADDR_NACK,For internally clocked logic (EC_AM is '0' and EC_OP is '0') on an address match or general call address (and S_GENERAL_IGNORE is '0')" "0: clock stretching is performed (till the,1: a received (matching or general) slave address"
bitfld.long 0x00 13. "S_READY_DATA_ACK,When '1' a received data element by the slave is immediately ACK'd when the receiver FIFO is not full" "0,1"
newline
bitfld.long 0x00 12. "S_READY_ADDR_ACK,When '1' a received (matching) slave address is immediately ACK'd when the receiver FIFO is not full" "0,1"
bitfld.long 0x00 11. "S_GENERAL_IGNORE,When '1' a received general call slave address is immediately NACK'd (no ACK or clock stretching) and treated as a non matching slave address" "0,1"
newline
bitfld.long 0x00 9. "M_NOT_READY_DATA_NACK,When '1' a received data element byte the master is immediately NACK'd when the receiver FIFO is full" "0,1"
bitfld.long 0x00 8. "M_READY_DATA_ACK,When '1' a received data element by the master is immediately ACK'd when the receiver FIFO is not full" "0,1"
newline
bitfld.long 0x00 4.--7. "LOW_PHASE_OVS,Serial I2C interface low phase oversampling factor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "HIGH_PHASE_OVS,Serial I2C interface high phase oversampling factor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x64++0x03
line.long 0x00 "I2C_STATUS,I2C status register"
hexmask.long.byte 0x00 16.--23. 1. "BASE_EZ_ADDR,I2C slave base EZ address"
hexmask.long.byte 0x00 8.--15. 1. "CURR_EZ_ADDR,I2C slave current EZ address"
newline
rbitfld.long 0x00 5. "M_READ,I2C master read transfer ('1') or I2C master write transfer ('0')" "0,1"
rbitfld.long 0x00 4. "S_READ,I2C slave read transfer ('1') or I2C slave write transfer ('0')" "0,1"
newline
rbitfld.long 0x00 1. "I2C_EC_BUSY,Inidicates whether the externally clocked logic is potentially accessing the EZ memory and/or updating BASE_ADDR or CURR_ADDR (this is only possible in EZ mode)" "0,1"
rbitfld.long 0x00 0. "BUS_BUSY,I2C bus is busy" "0,1"
group.long 0x68++0x03
line.long 0x00 "I2C_M_CMD,I2C master command register"
bitfld.long 0x00 4. "M_STOP,When '1' attempt to transmit a STOP" "0,1"
bitfld.long 0x00 3. "M_NACK,When '1' attempt to transmit a negative acknowledgement (NACK)" "0,1"
newline
bitfld.long 0x00 2. "M_ACK,When '1' attempt to transmit an acknowledgement (ACK)" "0,1"
bitfld.long 0x00 1. "M_START_ON_IDLE,When '1' transmit a START as soon as the bus is idle (I2C_STATUS.BUS_BUSY is '0' note that BUSY has a default value of '0')" "0,1"
newline
bitfld.long 0x00 0. "M_START,When '1' transmit a START or REPEATED START" "0,1"
group.long 0x6C++0x03
line.long 0x00 "I2C_S_CMD,I2C slave command register"
bitfld.long 0x00 1. "S_NACK,When '1' attempt to transmit a negative acknowledgement (NACK)" "0,1"
bitfld.long 0x00 0. "S_ACK,When '1' attempt to transmit an acknowledgement (ACK)" "0,1"
group.long 0x70++0x03
line.long 0x00 "I2C_CFG,I2C configuration register"
bitfld.long 0x00 28.--29. "SDA_OUT_FILT_SEL,Selection of cumulative i2c_sda_out filter delay:?" "0: 0 ns.?,1: 50 ns (filter 0 enabled).?,2: 100 ns (filters 0 and 1 enabled).?,3: 150 ns (filters 0 1 and 2 enabled)"
bitfld.long 0x00 20.--21. "SDA_OUT_FILT2_TRIM,Trim bits for i2c_sda_out 50 ns filter 2" "0,1,2,3"
newline
bitfld.long 0x00 18.--19. "SDA_OUT_FILT1_TRIM,Trim bits for i2c_sda_out 50 ns filter 1" "0,1,2,3"
bitfld.long 0x00 16.--17. "SDA_OUT_FILT0_TRIM,Trim bits for i2c_sda_out 50 ns filter 0" "0,1,2,3"
newline
bitfld.long 0x00 12. "SCL_IN_FILT_SEL,Selection of i2c_scl_in filter delay:?'0': 0 ns.?'1: 50 ns (filter enabled)" "0,1"
bitfld.long 0x00 8.--9. "SCL_IN_FILT_TRIM,Trim bits for i2c_scl_in 50 ns filter" "0,1,2,3"
newline
bitfld.long 0x00 4. "SDA_IN_FILT_SEL,Selection of i2c_sda_in filter delay:?'0': 0 ns.?'1: 50 ns (filter enabled)" "0,1"
bitfld.long 0x00 0.--1. "SDA_IN_FILT_TRIM,Trim bits for i2c_sda_in 50 ns filter" "0,1,2,3"
group.long 0x200++0x03
line.long 0x00 "TX_CTRL,Transmitter control register"
bitfld.long 0x00 8. "MSB_FIRST,Least significant bit first ('0') or most significant bit first ('1')" "0,1"
bitfld.long 0x00 0.--3. "DATA_WIDTH,Dataframe width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x204++0x03
line.long 0x00 "TX_FIFO_CTRL,Transmitter FIFO control register"
bitfld.long 0x00 17. "FREEZE,When '1' hardware reads from the transmitter FIFO do not remove FIFO entries" "0,1"
bitfld.long 0x00 16. "CLEAR,When '1' the transmitter FIFO and transmitter shift register are cleared/invalidated" "0,1"
newline
bitfld.long 0x00 0.--3. "TRIGGER_LEVEL,Trigger level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x208++0x03
line.long 0x00 "TX_FIFO_STATUS,Transmitter FIFO status register"
rbitfld.long 0x00 24.--27. "WR_PTR,FIFO write pointer: FIFO location at which a new data frame is written" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 16.--19. "RD_PTR,FIFO read pointer: FIFO location from which a data frame is read by the hardware" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
rbitfld.long 0x00 15. "SR_VALID,Indicates whether the TX shift registers holds a valid data frame ('1') or not ('0')" "0,1"
rbitfld.long 0x00 0.--4. "USED,Amount of enties in the transmitter FIFO" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x240++0x03
line.long 0x00 "TX_FIFO_WR,Transmitter FIFO write register"
hexmask.long.word 0x00 0.--15. 1. "DATA,Data frame written into the transmitter FIFO"
group.long 0x300++0x03
line.long 0x00 "RX_CTRL,Receiver control register"
bitfld.long 0x00 9. "MEDIAN,Median filter" "0,1"
bitfld.long 0x00 8. "MSB_FIRST,Least significant bit first ('0') or most significant bit first ('1')" "0,1"
newline
bitfld.long 0x00 0.--3. "DATA_WIDTH,Dataframe width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x304++0x03
line.long 0x00 "RX_FIFO_CTRL,Receiver FIFO control register"
bitfld.long 0x00 17. "FREEZE,When '1' hardware writes to the receiver FIFO have no effect" "0,1"
bitfld.long 0x00 16. "CLEAR,When '1' the receiver FIFO and receiver shift register are cleared/invalidated" "0,1"
newline
bitfld.long 0x00 0.--3. "TRIGGER_LEVEL,Trigger level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x308++0x03
line.long 0x00 "RX_FIFO_STATUS,Receiver FIFO status register"
rbitfld.long 0x00 24.--27. "WR_PTR,FIFO write pointer: FIFO location at which a new data frame is written by the hardware" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 16.--19. "RD_PTR,FIFO read pointer: FIFO location from which a data frame is" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
rbitfld.long 0x00 15. "SR_VALID,Indicates whether the RX shift registers holds a (partial) valid data frame ('1') or not ('0')" "0,1"
rbitfld.long 0x00 0.--4. "USED,Amount of enties in the receiver FIFO" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x310++0x03
line.long 0x00 "RX_MATCH,Slave address and mask register"
hexmask.long.byte 0x00 16.--23. 1. "MASK,Slave device address mask"
hexmask.long.byte 0x00 0.--7. 1. "ADDR,Slave device address.??In UART multi-processor mode all 8 bits are used.??In I2C slave mode only bits 7 down to 1 are used"
group.long 0x340++0x03
line.long 0x00 "RX_FIFO_RD,Receiver FIFO read register"
hexmask.long.word 0x00 0.--15. 1. "DATA,Data read from the receiver FIFO"
group.long 0x344++0x03
line.long 0x00 "RX_FIFO_RD_SILENT,Receiver FIFO read register"
hexmask.long.word 0x00 0.--15. 1. "DATA,Data read from the receiver FIFO"
repeat 16. (strings "0" "1" "2" "3" "4" "5" "6" "7" "8" "9" "10" "11" "12" "13" "14" "15" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x400)++0x03
line.long 0x00 "EZ_DATA$1,Memory buffer registers"
hexmask.long.byte 0x00 0.--7. 1. "EZ_DATA,Data in buffer memory location"
repeat.end
repeat 16. (strings "16" "17" "18" "19" "20" "21" "22" "23" "24" "25" "26" "27" "28" "29" "30" "31" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x440)++0x03
line.long 0x00 "EZ_DATA$1,Memory buffer registers"
hexmask.long.byte 0x00 0.--7. 1. "EZ_DATA,Data in buffer memory location"
repeat.end
group.long 0xE00++0x03
line.long 0x00 "INTR_CAUSE,Active clocked interrupt signal register"
rbitfld.long 0x00 4. "I2C_EC,Externally clock I2C interrupt active ( interrupt_i2c_ec ): INTR_I2C_EC_MASKED != 0" "0,1"
rbitfld.long 0x00 3. "RX,Receiver interrupt active ( interrupt_rx ): INTR_RX_MASKED != 0" "0,1"
newline
rbitfld.long 0x00 2. "TX,Transmitter interrupt active ( interrupt_tx ): INTR_TX_MASKED != 0" "0,1"
rbitfld.long 0x00 1. "S,Slave interrupt active ( interrupt_slave ): INTR_S_MASKED != 0" "0,1"
newline
rbitfld.long 0x00 0. "M,Master interrupt active ( interrupt_master ): INTR_M_MASKED != 0" "0,1"
group.long 0xE80++0x03
line.long 0x00 "INTR_I2C_EC,Externally clocked I2C interrupt request register"
bitfld.long 0x00 3. "EZ_READ_STOP,STOP detection after a read transfer occurred" "0,1"
bitfld.long 0x00 2. "EZ_WRITE_STOP,STOP detection after a write transfer occurred" "0,1"
newline
bitfld.long 0x00 1. "EZ_STOP,STOP detection" "0,1"
bitfld.long 0x00 0. "WAKE_UP,Wake up request" "0,1"
group.long 0xE88++0x03
line.long 0x00 "INTR_I2C_EC_MASK,Externally clocked I2C interrupt mask register"
bitfld.long 0x00 3. "EZ_READ_STOP,Mask bit for corresponding bit in interrupt request register" "0,1"
bitfld.long 0x00 2. "EZ_WRITE_STOP,Mask bit for corresponding bit in interrupt request register" "0,1"
newline
bitfld.long 0x00 1. "EZ_STOP,Mask bit for corresponding bit in interrupt request register" "0,1"
bitfld.long 0x00 0. "WAKE_UP,Mask bit for corresponding bit in interrupt request register" "0,1"
group.long 0xE8C++0x03
line.long 0x00 "INTR_I2C_EC_MASKED,Externally clocked I2C interrupt masked register"
rbitfld.long 0x00 3. "EZ_READ_STOP,Logical and of corresponding request and mask bits" "0,1"
rbitfld.long 0x00 2. "EZ_WRITE_STOP,Logical and of corresponding request and mask bits" "0,1"
newline
rbitfld.long 0x00 1. "EZ_STOP,Logical and of corresponding request and mask bits" "0,1"
rbitfld.long 0x00 0. "WAKE_UP,Logical and of corresponding request and mask bits" "0,1"
group.long 0xF00++0x03
line.long 0x00 "INTR_M,Master interrupt request register"
bitfld.long 0x00 8. "I2C_BUS_ERROR,I2C master bus error (unexpected detection of START or STOP condition)" "0,1"
bitfld.long 0x00 4. "I2C_STOP,I2C master STOP" "0,1"
newline
bitfld.long 0x00 2. "I2C_ACK,I2C master acknowledgement" "0,1"
bitfld.long 0x00 1. "I2C_NACK,I2C master negative acknowledgement" "0,1"
newline
bitfld.long 0x00 0. "I2C_ARB_LOST,I2C master lost arbitration: the value driven by the master on the SDA line is not the same as the value observed on the SDA line" "0,1"
group.long 0xF04++0x03
line.long 0x00 "INTR_M_SET,Master interrupt set request register"
bitfld.long 0x00 8. "I2C_BUS_ERROR,Write with '1' to set corresponding bit in interrupt request register" "0,1"
bitfld.long 0x00 4. "I2C_STOP,Write with '1' to set corresponding bit in interrupt request register" "0,1"
newline
bitfld.long 0x00 2. "I2C_ACK,Write with '1' to set corresponding bit in interrupt request register" "0,1"
bitfld.long 0x00 1. "I2C_NACK,Write with '1' to set corresponding bit in interrupt request register" "0,1"
newline
bitfld.long 0x00 0. "I2C_ARB_LOST,Write with '1' to set corresponding bit in interrupt request register" "0,1"
group.long 0xF08++0x03
line.long 0x00 "INTR_M_MASK,Master interrupt mask register"
bitfld.long 0x00 8. "I2C_BUS_ERROR,Mask bit for corresponding bit in interrupt request register" "0,1"
bitfld.long 0x00 4. "I2C_STOP,Mask bit for corresponding bit in interrupt request register" "0,1"
newline
bitfld.long 0x00 2. "I2C_ACK,Mask bit for corresponding bit in interrupt request register" "0,1"
bitfld.long 0x00 1. "I2C_NACK,Mask bit for corresponding bit in interrupt request register" "0,1"
newline
bitfld.long 0x00 0. "I2C_ARB_LOST,Mask bit for corresponding bit in interrupt request register" "0,1"
group.long 0xF0C++0x03
line.long 0x00 "INTR_M_MASKED,Master interrupt masked request register"
rbitfld.long 0x00 8. "I2C_BUS_ERROR,Logical and of corresponding request and mask bits" "0,1"
rbitfld.long 0x00 4. "I2C_STOP,Logical and of corresponding request and mask bits" "0,1"
newline
rbitfld.long 0x00 2. "I2C_ACK,Logical and of corresponding request and mask bits" "0,1"
rbitfld.long 0x00 1. "I2C_NACK,Logical and of corresponding request and mask bits" "0,1"
newline
rbitfld.long 0x00 0. "I2C_ARB_LOST,Logical and of corresponding request and mask bits" "0,1"
group.long 0xF40++0x03
line.long 0x00 "INTR_S,Slave interrupt request register"
bitfld.long 0x00 8. "I2C_BUS_ERROR,I2C slave bus error (unexpected detection of START or STOP condition)" "0,1"
bitfld.long 0x00 7. "I2C_GENERAL,I2C slave general call address received" "0,1"
newline
bitfld.long 0x00 6. "I2C_ADDR_MATCH,I2C slave matching address received" "0,1"
bitfld.long 0x00 5. "I2C_START,I2C slave START received" "0,1"
newline
bitfld.long 0x00 4. "I2C_STOP,I2C STOP event for I2C (read or write) transfer intended for this slave (address matching is performed)" "0,1"
bitfld.long 0x00 3. "I2C_WRITE_STOP,I2C STOP event for I2C write transfer intended for this slave (address matching is performed)" "0,1"
newline
bitfld.long 0x00 2. "I2C_ACK,I2C slave acknowledgement received" "0,1"
bitfld.long 0x00 1. "I2C_NACK,I2C slave negative acknowledgement received" "0,1"
newline
bitfld.long 0x00 0. "I2C_ARB_LOST,I2C slave lost arbitration: the value driven on the SDA line is not the same as the value observed on the SDA line (while the SCL line is '1')" "0,1"
group.long 0xF44++0x03
line.long 0x00 "INTR_S_SET,Slave interrupt set request register"
bitfld.long 0x00 8. "I2C_BUS_ERROR,Write with '1' to set corresponding bit in interrupt request register" "0,1"
bitfld.long 0x00 7. "I2C_GENERAL,Write with '1' to set corresponding bit in interrupt request register" "0,1"
newline
bitfld.long 0x00 6. "I2C_ADDR_MATCH,Write with '1' to set corresponding bit in interrupt request register" "0,1"
bitfld.long 0x00 5. "I2C_START,Write with '1' to set corresponding bit in interrupt request register" "0,1"
newline
bitfld.long 0x00 4. "I2C_STOP,Write with '1' to set corresponding bit in interrupt request register" "0,1"
bitfld.long 0x00 3. "I2C_WRITE_STOP,Write with '1' to set corresponding bit in interrupt request register" "0,1"
newline
bitfld.long 0x00 2. "I2C_ACK,Write with '1' to set corresponding bit in interrupt request register" "0,1"
bitfld.long 0x00 1. "I2C_NACK,Write with '1' to set corresponding bit in interrupt request register" "0,1"
newline
bitfld.long 0x00 0. "I2C_ARB_LOST,Write with '1' to set corresponding bit in interrupt request register" "0,1"
group.long 0xF48++0x03
line.long 0x00 "INTR_S_MASK,Slave interrupt mask register"
bitfld.long 0x00 8. "I2C_BUS_ERROR,Mask bit for corresponding bit in interrupt request register" "0,1"
bitfld.long 0x00 7. "I2C_GENERAL,Mask bit for corresponding bit in interrupt request register" "0,1"
newline
bitfld.long 0x00 6. "I2C_ADDR_MATCH,Mask bit for corresponding bit in interrupt request register" "0,1"
bitfld.long 0x00 5. "I2C_START,Mask bit for corresponding bit in interrupt request register" "0,1"
newline
bitfld.long 0x00 4. "I2C_STOP,Mask bit for corresponding bit in interrupt request register" "0,1"
bitfld.long 0x00 3. "I2C_WRITE_STOP,Mask bit for corresponding bit in interrupt request register" "0,1"
newline
bitfld.long 0x00 2. "I2C_ACK,Mask bit for corresponding bit in interrupt request register" "0,1"
bitfld.long 0x00 1. "I2C_NACK,Mask bit for corresponding bit in interrupt request register" "0,1"
newline
bitfld.long 0x00 0. "I2C_ARB_LOST,Mask bit for corresponding bit in interrupt request register" "0,1"
group.long 0xF4C++0x03
line.long 0x00 "INTR_S_MASKED,Slave interrupt masked request register"
rbitfld.long 0x00 8. "I2C_BUS_ERROR,Logical and of corresponding request and mask bits" "0,1"
rbitfld.long 0x00 7. "I2C_GENERAL,Logical and of corresponding request and mask bits" "0,1"
newline
rbitfld.long 0x00 6. "I2C_ADDR_MATCH,Logical and of corresponding request and mask bits" "0,1"
rbitfld.long 0x00 5. "I2C_START,Logical and of corresponding request and mask bits" "0,1"
newline
rbitfld.long 0x00 4. "I2C_STOP,Logical and of corresponding request and mask bits" "0,1"
rbitfld.long 0x00 3. "I2C_WRITE_STOP,Logical and of corresponding request and mask bits" "0,1"
newline
rbitfld.long 0x00 2. "I2C_ACK,Logical and of corresponding request and mask bits" "0,1"
rbitfld.long 0x00 1. "I2C_NACK,Logical and of corresponding request and mask bits" "0,1"
newline
rbitfld.long 0x00 0. "I2C_ARB_LOST,Logical and of corresponding request and mask bits" "0,1"
group.long 0xF80++0x03
line.long 0x00 "INTR_TX,Transmitter interrupt request register"
bitfld.long 0x00 7. "BLOCKED,AHB-Lite write transfer can not get access to the EZ memory (EZ data access) due to an externally clocked EZ access" "0,1"
bitfld.long 0x00 6. "UNDERFLOW,Attempt to read from an empty TX FIFO" "0,1"
newline
bitfld.long 0x00 5. "OVERFLOW,Attempt to write to a full TX FIFO.??Only used in FIFO mode" "0,1"
bitfld.long 0x00 4. "EMPTY,TX FIFO is empty i.e" "0,1"
newline
bitfld.long 0x00 1. "NOT_FULL,TX FIFO is not full" "0,1"
bitfld.long 0x00 0. "TRIGGER,Less entries in the TX FIFO than the value specified by TX_FIFO_CTRL" "0,1"
group.long 0xF84++0x03
line.long 0x00 "INTR_TX_SET,Transmitter interrupt set request register"
bitfld.long 0x00 7. "BLOCKED,Write with '1' to set corresponding bit in interrupt request register" "0,1"
bitfld.long 0x00 6. "UNDERFLOW,Write with '1' to set corresponding bit in interrupt request register" "0,1"
newline
bitfld.long 0x00 5. "OVERFLOW,Write with '1' to set corresponding bit in interrupt request register" "0,1"
bitfld.long 0x00 4. "EMPTY,Write with '1' to set corresponding bit in interrupt request register" "0,1"
newline
bitfld.long 0x00 1. "NOT_FULL,Write with '1' to set corresponding bit in interrupt request register" "0,1"
bitfld.long 0x00 0. "TRIGGER,Write with '1' to set corresponding bit in interrupt request register" "0,1"
group.long 0xF88++0x03
line.long 0x00 "INTR_TX_MASK,Transmitter interrupt mask register"
bitfld.long 0x00 7. "BLOCKED,Mask bit for corresponding bit in interrupt request register" "0,1"
bitfld.long 0x00 6. "UNDERFLOW,Mask bit for corresponding bit in interrupt request register" "0,1"
newline
bitfld.long 0x00 5. "OVERFLOW,Mask bit for corresponding bit in interrupt request register" "0,1"
bitfld.long 0x00 4. "EMPTY,Mask bit for corresponding bit in interrupt request register" "0,1"
newline
bitfld.long 0x00 1. "NOT_FULL,Mask bit for corresponding bit in interrupt request register" "0,1"
bitfld.long 0x00 0. "TRIGGER,Mask bit for corresponding bit in interrupt request register" "0,1"
group.long 0xF8C++0x03
line.long 0x00 "INTR_TX_MASKED,Transmitter interrupt masked request register"
rbitfld.long 0x00 7. "BLOCKED,Logical and of corresponding request and mask bits" "0,1"
rbitfld.long 0x00 6. "UNDERFLOW,Logical and of corresponding request and mask bits" "0,1"
newline
rbitfld.long 0x00 5. "OVERFLOW,Logical and of corresponding request and mask bits" "0,1"
rbitfld.long 0x00 4. "EMPTY,Logical and of corresponding request and mask bits" "0,1"
newline
rbitfld.long 0x00 1. "NOT_FULL,Logical and of corresponding request and mask bits" "0,1"
rbitfld.long 0x00 0. "TRIGGER,Logical and of corresponding request and mask bits" "0,1"
group.long 0xFC0++0x03
line.long 0x00 "INTR_RX,Receiver interrupt request register"
bitfld.long 0x00 7. "BLOCKED,AHB-Lite read transfer can not get access to the EZ memory (EZ_DATA accesses) due to an externally clocked EZ access" "0,1"
bitfld.long 0x00 6. "UNDERFLOW,Attempt to read from an empty RX FIFO.??Only used in FIFO mode" "0,1"
newline
bitfld.long 0x00 5. "OVERFLOW,Attempt to write to a full RX FIFO" "0,1"
bitfld.long 0x00 3. "FULL,RX FIFO is full" "0,1"
newline
bitfld.long 0x00 2. "NOT_EMPTY,RX FIFO is not empty.??Only used in FIFO mode" "0,1"
bitfld.long 0x00 0. "TRIGGER,More entries in the RX FIFO than the value specified by TRIGGER_LEVEL in SCB_RX_FIFO_CTL.??Only used in FIFO mode" "0,1"
group.long 0xFC4++0x03
line.long 0x00 "INTR_RX_SET,Receiver interrupt set request register"
bitfld.long 0x00 7. "BLOCKED,Write with '1' to set corresponding bit in interrupt status register" "0,1"
bitfld.long 0x00 6. "UNDERFLOW,Write with '1' to set corresponding bit in interrupt status register" "0,1"
newline
bitfld.long 0x00 5. "OVERFLOW,Write with '1' to set corresponding bit in interrupt status register" "0,1"
bitfld.long 0x00 3. "FULL,Write with '1' to set corresponding bit in interrupt status register" "0,1"
newline
bitfld.long 0x00 2. "NOT_EMPTY,Write with '1' to set corresponding bit in interrupt status register" "0,1"
bitfld.long 0x00 0. "TRIGGER,Write with '1' to set corresponding bit in interrupt request register" "0,1"
group.long 0xFC8++0x03
line.long 0x00 "INTR_RX_MASK,Receiver interrupt mask register"
bitfld.long 0x00 7. "BLOCKED,Mask bit for corresponding bit in interrupt request register" "0,1"
bitfld.long 0x00 6. "UNDERFLOW,Mask bit for corresponding bit in interrupt request register" "0,1"
newline
bitfld.long 0x00 5. "OVERFLOW,Mask bit for corresponding bit in interrupt request register" "0,1"
bitfld.long 0x00 3. "FULL,Mask bit for corresponding bit in interrupt request register" "0,1"
newline
bitfld.long 0x00 2. "NOT_EMPTY,Mask bit for corresponding bit in interrupt request register" "0,1"
bitfld.long 0x00 0. "TRIGGER,Mask bit for corresponding bit in interrupt request register" "0,1"
group.long 0xFCC++0x03
line.long 0x00 "INTR_RX_MASKED,Receiver interrupt masked request register"
rbitfld.long 0x00 7. "BLOCKED,Logical and of corresponding request and mask bits" "0,1"
rbitfld.long 0x00 6. "UNDERFLOW,Logical and of corresponding request and mask bits" "0,1"
newline
rbitfld.long 0x00 5. "OVERFLOW,Logical and of corresponding request and mask bits" "0,1"
rbitfld.long 0x00 3. "FULL,Logical and of corresponding request and mask bits" "0,1"
newline
rbitfld.long 0x00 2. "NOT_EMPTY,Logical and of corresponding request and mask bits" "0,1"
rbitfld.long 0x00 0. "TRIGGER,Logical and of corresponding request and mask bits" "0,1"
tree.end
tree "SFLASH (Supervisory Flash Area (Cypress Trim & Wounding Info))"
base ad:0xFFFF000
repeat 16. (strings "0" "1" "2" "3" "4" "5" "6" "7" "8" "9" "10" "11" "12" "13" "14" "15" )(list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )
group.byte ($2+0x00)++0x00
line.byte 0x00 "PROT_ROW$1,Per Page Write Protection"
hexmask.byte 0x00 0.--7. 1. "DATA8,Protection Data (1b per page)"
repeat.end
repeat 16. (strings "16" "17" "18" "19" "20" "21" "22" "23" "24" "25" "26" "27" "28" "29" "30" "31" )(list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )
group.byte ($2+0x10)++0x00
line.byte 0x00 "PROT_ROW$1,Per Page Write Protection"
hexmask.byte 0x00 0.--7. 1. "DATA8,Protection Data (1b per page)"
repeat.end
repeat 16. (strings "32" "33" "34" "35" "36" "37" "38" "39" "40" "41" "42" "43" "44" "45" "46" "47" )(list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )
group.byte ($2+0x20)++0x00
line.byte 0x00 "PROT_ROW$1,Per Page Write Protection"
hexmask.byte 0x00 0.--7. 1. "DATA8,Protection Data (1b per page)"
repeat.end
repeat 16. (strings "48" "49" "50" "51" "52" "53" "54" "55" "56" "57" "58" "59" "60" "61" "62" "63" )(list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )
group.byte ($2+0x30)++0x00
line.byte 0x00 "PROT_ROW$1,Per Page Write Protection"
hexmask.byte 0x00 0.--7. 1. "DATA8,Protection Data (1b per page)"
repeat.end
group.byte 0x7F++0x00
line.byte 0x00 "PROT_PROTECTION,Protection Level"
bitfld.byte 0x00 0.--1. "PROT_LEVEL,Current Protection Mode - note that encoding is different from CPUSS_PROTECTION !!" "0: No description available,1: No description available,2: No description available,3: No description available"
repeat 16. (strings "0" "1" "2" "3" "4" "5" "6" "7" "8" "9" "10" "11" "12" "13" "14" "15" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x100)++0x03
line.long 0x00 "AV_PAIRS_32B$1,32b Addr/Value pair Section"
hexmask.long 0x00 0.--31. 1. "DATA32,Address or Value Word"
repeat.end
group.long 0x144++0x03
line.long 0x00 "SILICON_ID,Silicon ID"
hexmask.long.word 0x00 0.--15. 1. "ID,Silicon ID"
group.word 0x150++0x01
line.word 0x00 "HIB_KEY_DELAY,Hibernate wakeup value for PWR_KEY_DELAY"
hexmask.word 0x00 0.--9. 1. "WAKEUP_HOLDOFF,Delay (in 12MHz IMO clock cycles) to wait for references to settle on wakeup from hibernate/deepsleep"
group.word 0x152++0x01
line.word 0x00 "DPSLP_KEY_DELAY,DeepSleep wakeup value for PWR_KEY_DELAY"
hexmask.word 0x00 0.--9. 1. "WAKEUP_HOLDOFF,Delay (in 12MHz IMO clock cycles) to wait for references to settle on wakeup from hibernate/deepsleep"
group.byte 0x154++0x00
line.byte 0x00 "SWD_CONFIG,SWD pinout selector (not present in TSG4/TSG5-M)"
bitfld.byte 0x00 0. "SWD_SELECT," "0,1"
group.long 0x158++0x03
line.long 0x00 "SWD_LISTEN,Listen Window Length"
hexmask.long 0x00 0.--31. 1. "CYCLES,Number of clock cycles"
group.long 0x15C++0x03
line.long 0x00 "FLASH_START,Flash Image Start Address"
hexmask.long 0x00 0.--31. 1. "ADDRESS,Start Address"
group.byte 0x160++0x00
line.byte 0x00 "CSD_TRIM1_HVIDAC,CSD Trim Data for HVIDAC operation"
hexmask.byte 0x00 0.--7. 1. "TRIM8,Trim data"
group.byte 0x161++0x00
line.byte 0x00 "CSD_TRIM2_HVIDAC,CSD Trim Data for HVIDAC operation"
hexmask.byte 0x00 0.--7. 1. "TRIM8,Trim data"
group.byte 0x162++0x00
line.byte 0x00 "CSD_TRIM1_CSD,CSD Trim Data for (normal) CSD operation"
hexmask.byte 0x00 0.--7. 1. "TRIM8,Trim data"
group.byte 0x163++0x00
line.byte 0x00 "CSD_TRIM2_CSD,CSD Trim Data for (normal) CSD operation"
hexmask.byte 0x00 0.--7. 1. "TRIM8,Trim data"
repeat 8. (strings "0" "1" "2" "3" "4" "5" "6" "7" )(list 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 )
group.byte ($2+0x170)++0x00
line.byte 0x00 "PROT_VIRGINKEY$1,Virgin Protection Mode Key"
hexmask.byte 0x00 0.--7. 1. "KEY8,Key Byte"
repeat.end
repeat 3. (strings "0" "1" "2" )(list 0x00 0x01 0x02 )
group.byte ($2+0x178)++0x00
line.byte 0x00 "DIE_LOT$1,Lot Number (3 bytes)"
hexmask.byte 0x00 0.--7. 1. "LOT,Lot Number Byte"
repeat.end
group.byte 0x17B++0x00
line.byte 0x00 "DIE_WAFER,Wafer Number"
hexmask.byte 0x00 0.--7. 1. "WAFER,Wafer Number"
group.byte 0x17C++0x00
line.byte 0x00 "DIE_X,X Position on Wafer CRI Pass/Fail Bin"
hexmask.byte 0x00 0.--7. 1. "X,X Position"
group.byte 0x17D++0x00
line.byte 0x00 "DIE_Y,Y Position on Wafer CHI Pass/Fail Bin"
hexmask.byte 0x00 0.--7. 1. "Y,Y Position"
group.byte 0x17E++0x00
line.byte 0x00 "DIE_SORT,Sort1/2/3 Pass/Fail Bin"
bitfld.byte 0x00 5. "ENG_PASS,ENG Pass Bin" "0,1"
bitfld.byte 0x00 4. "CHI_PASS,CHI Pass Bin (1) or 0 (Fail Bin)" "0,1"
newline
bitfld.byte 0x00 3. "CRI_PASS,CRI Pass Bin (1) or 0 (Fail Bin)" "0,1"
bitfld.byte 0x00 2. "S3_PASS,SORT3 Pass Bin (1) or 0 (Fail Bin)" "0,1"
newline
bitfld.byte 0x00 1. "S2_PASS,SORT2 Pass Bin (1) or 0 (Fail Bin)" "0,1"
bitfld.byte 0x00 0. "S1_PASS,SORT1 Pass Bin (1) or 0 (Fail Bin)" "0,1"
group.byte 0x17F++0x00
line.byte 0x00 "DIE_MINOR,Minor Revision Number"
hexmask.byte 0x00 0.--7. 1. "MINOR,Minor revision number"
group.byte 0x1BE++0x00
line.byte 0x00 "IMO_TRIM_USBMODE_24,USB IMO TRIM 24MHz"
hexmask.byte 0x00 0.--7. 1. "TRIM_24,TRIM value for IMO with USB at 24MHz"
group.byte 0x1BF++0x00
line.byte 0x00 "IMO_TRIM_USBMODE_48,USB IMO TRIM 48MHz"
hexmask.byte 0x00 0.--7. 1. "TRIM_24,TRIM value for IMO with USB at 24MHz"
repeat 16. (strings "0" "1" "2" "3" "4" "5" "6" "7" "8" "9" "10" "11" "12" "13" "14" "15" )(list 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F )
group.byte ($2+0x1CC)++0x00
line.byte 0x00 "IMO_TCTRIM_LT$1,IMO TempCo Trim Register (SRSS-Lite)"
bitfld.byte 0x00 5.--6. "TCTRIM,IMO temperature compesation trim" "0,1,2,3"
bitfld.byte 0x00 0.--4. "STEPSIZE,IMO trim stepsize bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
repeat.end
repeat 9. (strings "16" "17" "18" "19" "20" "21" "22" "23" "24" )(list 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 )
group.byte ($2+0x1DC)++0x00
line.byte 0x00 "IMO_TCTRIM_LT$1,IMO TempCo Trim Register (SRSS-Lite)"
bitfld.byte 0x00 5.--6. "TCTRIM,IMO temperature compesation trim" "0,1,2,3"
bitfld.byte 0x00 0.--4. "STEPSIZE,IMO trim stepsize bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
repeat.end
repeat 16. (strings "0" "1" "2" "3" "4" "5" "6" "7" "8" "9" "10" "11" "12" "13" "14" "15" )(list 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F )
group.byte ($2+0x1E5)++0x00
line.byte 0x00 "IMO_TRIM_LT$1,IMO Frequency Trim Register (SRSS-Lite)"
hexmask.byte 0x00 0.--7. 1. "OFFSET,Frequency trim bits"
repeat.end
repeat 9. (strings "16" "17" "18" "19" "20" "21" "22" "23" "24" )(list 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 )
group.byte ($2+0x1F5)++0x00
line.byte 0x00 "IMO_TRIM_LT$1,IMO Frequency Trim Register (SRSS-Lite)"
hexmask.byte 0x00 0.--7. 1. "OFFSET,Frequency trim bits"
repeat.end
tree.end
tree "SPCIF (Flash Control Interface)"
base ad:0x40110000
group.long 0x00++0x03
line.long 0x00 "GEOMETRY,Flash/NVL geometry information"
bitfld.long 0x00 31. "DE_CPD_LP,0': SRAM busy wait loop has not been copied.?'1': Busy wait loop has been written into SRAM" "0,1"
rbitfld.long 0x00 22.--23. "FLASH_ROW,Page size in 64 Byte multiples (chip dependent):?" "0: 64 byte?,1: 128 byte?,2: 192 byte?,3: 256 byte??The page size"
newline
rbitfld.long 0x00 20.--21. "NUM_FLASH,Number of flash macros (chip dependent):?" "0: 1 flash macro?,1: 2 flash macros?,2: 3 flash macros?,3: 4 flash macros"
rbitfld.long 0x00 16.--19. "SFLASH,Supervisory flash capacity in 256 Byte multiples (chip dependent)" "0: 256 Bytes.?,1: 2*256 Bytes.?...?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: 16*256 Bytes"
newline
abitfld.long 0x00 0.--15. "FLASH,Regular flash capacity in 256 Byte multiples (chip dependent)" "0x0000=0: 256 Bytes.?,0x0001=1: 2*256 Bytes.?...?,0xFFFF=65535: 65536*256 Bytes"
group.long 0x7F0++0x03
line.long 0x00 "INTR,SPCIF interrupt request register"
bitfld.long 0x00 0. "TIMER,Timer counter value reaches 0" "0,1"
group.long 0x7F4++0x03
line.long 0x00 "INTR_SET,SPCIF interrupt set request register"
bitfld.long 0x00 0. "TIMER,Write INTR_SET field with '1' to set corresponding INTR field" "0,1"
group.long 0x7F8++0x03
line.long 0x00 "INTR_MASK,SPCIF interrupt mask register"
bitfld.long 0x00 0. "TIMER,Mask for corresponding field in INTR register" "0,1"
group.long 0x7FC++0x03
line.long 0x00 "INTR_MASKED,SPCIF interrupt masked request register"
rbitfld.long 0x00 0. "TIMER,Logical and of corresponding request and mask fields" "0,1"
tree.end
tree "SRSSLT (System Resources Lite Subsystem)"
base ad:0x40030000
group.long 0x00++0x03
line.long 0x00 "PWR_CONTROL,Power Mode Control"
bitfld.long 0x00 23. "EXT_VCCD,Always write 0 except as noted below" "0,1"
rbitfld.long 0x00 18.--19. "SPARE,Spare AHB readback bits that are hooked to PWR_PWRSYS_TRIM1.SPARE_TRIM[1:0] through spare logic equivalent to bitwise inversion" "0,1,2,3"
newline
bitfld.long 0x00 17. "OVER_TEMP_THRESH,Over-temperature threshold.?0: TEMP_HIGH condition occurs between 120C and 125C.?1: TEMP_HIGH condition occurs between 60C and 75C (used for testing)" "0,1"
bitfld.long 0x00 16. "OVER_TEMP_EN,Enables the die over temperature sensor" "0,1"
newline
rbitfld.long 0x00 5. "LPM_READY,Indicates whether the low power mode regulator is ready to enter DEEPSLEEP mode" "0,1"
rbitfld.long 0x00 4. "DEBUG_SESSION,Indicates whether a debug session is active (CDBGPWRUPREQ signal is 1)" "0: No description available,1: No description available"
newline
rbitfld.long 0x00 0.--3. "POWER_MODE,Current power mode of the device" "0: No description available,1: No description available,2: No description available,3: No description available,?..."
group.long 0x04++0x03
line.long 0x00 "PWR_KEY_DELAY,Power System Key&Delay Register"
hexmask.long.word 0x00 0.--9. 1. "WAKEUP_HOLDOFF,Delay to wait for references to settle on wakeup from deepsleep"
group.long 0x0C++0x03
line.long 0x00 "PWR_DDFT_SELECT,Power DDFT Mode Selection Register"
bitfld.long 0x00 4.--7. "DDFT1_SEL,Select signal for power DDFT output #1" "0: No description available,1: No description available,2: No description available,3: No description available,4: No description available,5: No description available,6: No description available,7: No description available,8: No description available,9: No description available,10: No description available,11: No description available,12: No description available,13: No description available,14: No description available,15: No description available"
bitfld.long 0x00 0.--3. "DDFT0_SEL,Select signal for power DDFT output #0" "0: No description available,1: No description available,2: No description available,3: No description available,4: No description available,5: No description available,6: No description available,7: No description available,8: No description available,9: No description available,10: No description available,11: No description available,12: No description available,13: No description available,14: No description available,15: No description available"
group.long 0x14++0x03
line.long 0x00 "TST_MODE,Test Mode Control Register"
bitfld.long 0x00 31. "TEST_MODE," "0,1"
rbitfld.long 0x00 30. "TEST_KEY_DFT_EN,This bit is set when a XRES test mode key is shifted in" "0,1"
newline
bitfld.long 0x00 28. "BLOCK_ALT_XRES,Relevant only for parts that have the alternate XRES mechanism of overloading a GPIO pin temporarily as alternate XRES during test" "0,1"
rbitfld.long 0x00 2. "SWD_CONNECTED," "0,1"
group.long 0x18++0x03
line.long 0x00 "TST_DDFT_CTRL,Digital DFT Control Register"
bitfld.long 0x00 31. "ENABLE," "0,1"
bitfld.long 0x00 8.--11. "DFT_SEL1,Select signal for DDFT output #1" "0: No description available,1: No description available,2: No description available,3: No description available,4: No description available,5: No description available,6: No description available,7: No description available,8: No description available,9: No description available,10: No description available,11: No description available,12: No description available,13: No description available,14: No description available,15: No description available"
newline
bitfld.long 0x00 0.--3. "DFT_SEL0,Select signal for DDFT output #0" "0: No description available,1: No description available,2: No description available,3: No description available,4: No description available,5: No description available,6: No description available,7: No description available,8: No description available,9: No description available,10: No description available,11: No description available,12: No description available,13: No description available,14: No description available,15: No description available"
group.long 0x1C++0x03
line.long 0x00 "TST_TRIM_CNTR1,IMO trim down-counter and status (clk_sys)"
rbitfld.long 0x00 31. "COUNTER_DONE,Status bit indicating that TRIM_CNTR1.COUNTER==0 and TRIM_CNT2.COUNTER stopped counting up" "0,1"
hexmask.long.word 0x00 0.--15. 1. "COUNTER,Down-counter clocked on clk_sys"
group.long 0x20++0x03
line.long 0x00 "TST_TRIM_CNTR2,IMO trim up-counter (ddft)"
hexmask.long.word 0x00 0.--15. 1. "COUNTER,Up-counter clocked on Clock DDFT output #1"
group.long 0x24++0x03
line.long 0x00 "TST_ADFT_CTRL,ADFT buffer/comparator control register"
bitfld.long 0x00 31. "BUF_EN,Enables the functionality of the ADFT buffer/comparator" "0,1"
rbitfld.long 0x00 16. "BUF_COMP_OUT,Output of the ADFT comparator 0 if in analog voltage buffer mode" "0,1"
newline
bitfld.long 0x00 8.--9. "BUF_MODE,Selects the operating mode for the ADFT buffer/comparator:?0: Voltage buffer input is amuxbusa output is amuxbusb?1: Voltage buffer input is amuxbusb output is amuxbusa?2: Comparator input+ is amuxbusa input- is amuxbusb?3: Comparator input+ is.." "0,1,2,3"
bitfld.long 0x00 0. "BUF_AUTO_ZERO,The ADFT buffer/comparator has a common mode dependent offset that can be greatly reduced by using this register bit" "0,1"
group.long 0x28++0x03
line.long 0x00 "CLK_SELECT,Clock Select Register"
bitfld.long 0x00 6.--7. "SYSCLK_DIV,Select clk_sys prescaler value" "0: No description available,1: No description available,2: No description available,3: No description available"
bitfld.long 0x00 4.--5. "PUMP_SEL,Selects clock source for charge pump clock" "0: No description available,1: No description available,2: No description available,?..."
newline
bitfld.long 0x00 2.--3. "HFCLK_DIV,Selects clk_hf predivider value" "0: No description available,1: No description available,2: No description available,3: No description available"
bitfld.long 0x00 0.--1. "HFCLK_SEL,Selects a source for clk_hf and dsi_in[0]" "0: No description available,1: No description available,2: No description available,?..."
group.long 0x2C++0x03
line.long 0x00 "CLK_ILO_CONFIG,ILO Configuration"
bitfld.long 0x00 31. "ENABLE,Master enable for ILO oscillator" "0,1"
group.long 0x30++0x03
line.long 0x00 "CLK_IMO_CONFIG,IMO Configuration"
bitfld.long 0x00 31. "ENABLE,Master enable for IMO oscillator" "0,1"
group.long 0x34++0x03
line.long 0x00 "CLK_DFT_SELECT,Clock DFT Mode Selection Register"
bitfld.long 0x00 14. "DFT_EDGE1,Edge sensitivity for in-line divider on output #1 (only relevant when DIV1>0)" "0: No description available,1: No description available"
bitfld.long 0x00 12.--13. "DFT_DIV1,DFT Output Divide Down" "0: No description available,1: No description available,2: No description available,3: No description available"
newline
bitfld.long 0x00 8.--11. "DFT_SEL1,Select signal for DFT output #1" "0: No description available,1: No description available,2: No description available,3: No description available,4: No description available,5: No description available,6: No description available,7: No description available,8: No description available,9: No description available,?..."
bitfld.long 0x00 6. "DFT_EDGE0,Edge sensitivity for in-line divider on output #0 (only relevant when DIV0>0)" "0: No description available,1: No description available"
newline
bitfld.long 0x00 4.--5. "DFT_DIV0,DFT Output Divide Down" "0: No description available,1: No description available,2: No description available,3: No description available"
bitfld.long 0x00 0.--3. "DFT_SEL0,Select signal for DFT output #0" "0: No description available,1: No description available,2: No description available,3: No description available,4: No description available,5: No description available,6: No description available,7: No description available,8: No description available,9: No description available,?..."
group.long 0x38++0x03
line.long 0x00 "WDT_DISABLE_KEY,Watchdog Disable Key Register"
hexmask.long 0x00 0.--31. 1. "KEY,Disables WDT reset when equal to 0xACED8865"
group.long 0x3C++0x03
line.long 0x00 "WDT_COUNTER,Watchdog Counter Register"
hexmask.long.word 0x00 0.--15. 1. "COUNTER,Current value of WDT Counter"
group.long 0x40++0x03
line.long 0x00 "WDT_MATCH,Watchdog Match Register"
bitfld.long 0x00 16.--19. "IGNORE_BITS,The number of MSB bits of the watchdog timer that are NOT checked against MATCH" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x00 0.--15. 1. "MATCH,Match value for Watchdog counter"
group.long 0x44++0x03
line.long 0x00 "SRSS_INTR,SRSS Interrupt Register"
bitfld.long 0x00 1. "TEMP_HIGH,Regulator over-temp interrupt" "0,1"
bitfld.long 0x00 0. "WDT_MATCH,WDT Interrupt Request" "0,1"
group.long 0x48++0x03
line.long 0x00 "SRSS_INTR_SET,SRSS Interrupt Set Register"
bitfld.long 0x00 1. "TEMP_HIGH,Writing 1 to this bit internally sets the overtemp interrupt" "0,1"
group.long 0x4C++0x03
line.long 0x00 "SRSS_INTR_MASK,SRSS Interrupt Mask Register"
bitfld.long 0x00 1. "TEMP_HIGH,Masks REG_OVERTEMP interrupt" "0,1"
bitfld.long 0x00 0. "WDT_MATCH,Clearing this bit will not forward the interrupt to the CPU" "0,1"
group.long 0x54++0x03
line.long 0x00 "RES_CAUSE,Reset Cause Observation Register"
bitfld.long 0x00 4. "RESET_SOFT,Cortex-M0 requested a system reset through it's SYSRESETREQ" "0,1"
bitfld.long 0x00 3. "RESET_PROT_FAULT,A protection violation occurred that requires a RESET" "0,1"
newline
bitfld.long 0x00 0. "RESET_WDT,A WatchDog Timer reset has occurred since last power cycle" "0,1"
group.long 0xF00++0x03
line.long 0x00 "PWR_BG_TRIM1,Bandgap Trim Register"
bitfld.long 0x00 0.--5. "REF_VTRIM,Trims the bandgap reference voltage output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0xF04++0x03
line.long 0x00 "PWR_BG_TRIM2,Bandgap Trim Register"
bitfld.long 0x00 0.--5. "REF_ITRIM,Trims the bandgap reference current output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0xF08++0x03
line.long 0x00 "CLK_IMO_SELECT,IMO Frequency Select Register"
bitfld.long 0x00 0.--2. "FREQ,Select operating frequency" "0: No description available,1: No description available,2: No description available,3: No description available,4: No description available,5: No description available,6: No description available,?..."
group.long 0xF0C++0x03
line.long 0x00 "CLK_IMO_TRIM1,IMO Trim Register"
hexmask.long.byte 0x00 0.--7. 1. "OFFSET,Frequency trim bits"
group.long 0xF10++0x03
line.long 0x00 "CLK_IMO_TRIM2,IMO Trim Register"
bitfld.long 0x00 0.--2. "FSOFFSET,Frequency trim bits" "0,1,2,3,4,5,6,7"
group.long 0xF14++0x03
line.long 0x00 "PWR_PWRSYS_TRIM1,Power System Trim Register"
bitfld.long 0x00 4.--7. "SPARE_TRIM,Active-Reference temperature compensation trim (repurposed from spare bits).?Bits [7:6] - trim the Active-Reference IREF temperature coefficient (TC).?" "0: TC = 0 (unchanged)?,1: TC = -50ppm/C ?,?,?,?,?,?,?,?,?,10: TC = -80ppm/C?,11: TC = +150ppm/C,?..."
bitfld.long 0x00 0.--3. "DPSLP_REF_TRIM,Trims the DeepSleep reference that is used by the DeepSleep regulator and DeepSleep power comparator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xF18++0x03
line.long 0x00 "CLK_IMO_TRIM3,IMO Trim Register"
bitfld.long 0x00 5.--6. "TCTRIM,IMO temperature compesation trim" "0,1,2,3"
bitfld.long 0x00 0.--4. "STEPSIZE,IMO trim stepsize bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
tree.end
tree "TCPWM (Timer/Counter/PWM)"
base ad:0x40050000
group.long 0x00++0x03
line.long 0x00 "CTRL,TCPWM control register 0"
bitfld.long 0x00 0. "COUNTER_ENABLED,Counter enables for counters 0 up to CNT_NR-1.?'0': counter disabled.?'1': counter enabled.?Counter static configuration information (e.g. CTRL.MODE all TR_CTRL0 TR_CTRL1 and TR_CTRL2 register fields) should only be modified when the.." "0,1"
group.long 0x08++0x03
line.long 0x00 "CMD,TCPWM command register"
bitfld.long 0x00 24. "COUNTER_START,Counters SW start trigger" "0,1"
bitfld.long 0x00 16. "COUNTER_STOP,Counters SW stop trigger" "0,1"
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bitfld.long 0x00 8. "COUNTER_RELOAD,Counters SW reload trigger" "0,1"
bitfld.long 0x00 0. "COUNTER_CAPTURE,Counters SW capture trigger" "0,1"
group.long 0x0C++0x03
line.long 0x00 "INTR_CAUSE,TCPWM Counter interrupt cause register"
rbitfld.long 0x00 0. "COUNTER_INT,Counters interrupt signal active" "0,1"
tree.end
tree "TCPWM_CNT (Timer/Counter/PWM Counter Module)"
base ad:0x40050100
group.long 0x00++0x03
line.long 0x00 "CTRL,Counter control register"
bitfld.long 0x00 24.--26. "MODE,Counter mode" "0: No description available,?,2: No description available,3: No description available,4: No description available,5: No description available,6: No description available,?..."
bitfld.long 0x00 20.--21. "QUADRATURE_MODE,In QUAD mode selects quadrature encoding mode (X1/X2/X4).?In PWM PWM_DT and PWM_PR modes these two bits can be used to invert dt_line_out and dt_line_compl_out" "0: No description available,1: No description available,2: No description available,?..."
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bitfld.long 0x00 18. "ONE_SHOT,When '0' counter runs continuous" "0,1"
bitfld.long 0x00 16.--17. "UP_DOWN_MODE,Determines counter direction" "0: No description available,1: No description available,2: No description available,3: No description available"
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hexmask.long.byte 0x00 8.--15. 1. "GENERIC,Generic 8-bit control field"
bitfld.long 0x00 3. "PWM_STOP_ON_KILL,Specifies whether the counter stops on a kill events:?'0': kill event does NOT stop counter.?'1': kill event stops counter.??This field has a function in PWM PWM_DT and PWM_PR modes only" "0,1"
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bitfld.long 0x00 2. "PWM_SYNC_KILL,Specifies asynchronous/synchronous kill behavior:?'1': synchronous kill mode: the kill event disables the dt_line_out and dt_line_compl_out signals till the next terminal count event (synchronous kill)" "0,1"
bitfld.long 0x00 1. "AUTO_RELOAD_PERIOD,Specifies switching of the PERIOD and buffered PERIOD values" "0,1"
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bitfld.long 0x00 0. "AUTO_RELOAD_CC,Specifies switching of the CC and buffered CC values" "0,1"
group.long 0x04++0x03
line.long 0x00 "STATUS,Counter status register"
rbitfld.long 0x00 31. "RUNNING,When '0' the counter is NOT running" "0,1"
hexmask.long.byte 0x00 8.--15. 1. "GENERIC,Generic 8-bit counter field"
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rbitfld.long 0x00 0. "DOWN,When '0' counter is counting up" "0,1"
group.long 0x08++0x03
line.long 0x00 "COUNTER,Counter count register"
hexmask.long.word 0x00 0.--15. 1. "COUNTER,16-bit counter value"
group.long 0x0C++0x03
line.long 0x00 "CC,Counter compare/capture register"
hexmask.long.word 0x00 0.--15. 1. "CC,In CAPTURE mode captures the counter value"
group.long 0x10++0x03
line.long 0x00 "CC_BUFF,Counter buffered compare/capture register"
hexmask.long.word 0x00 0.--15. 1. "CC,Additional buffer for counter CC register"
group.long 0x14++0x03
line.long 0x00 "PERIOD,Counter period register"
hexmask.long.word 0x00 0.--15. 1. "PERIOD,Period value: upper value of the counter"
group.long 0x18++0x03
line.long 0x00 "PERIOD_BUFF,Counter buffered period register"
hexmask.long.word 0x00 0.--15. 1. "PERIOD,Additional buffer for counter PERIOD register"
group.long 0x20++0x03
line.long 0x00 "TR_CTRL0,Counter trigger control register 0"
bitfld.long 0x00 16.--19. "START_SEL,Selects one of the 16 input triggers as a start trigger" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 12.--15. "STOP_SEL,Selects one of the 16 input triggers as a stop trigger" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 8.--11. "RELOAD_SEL,Selects one of the 16 input triggers as a reload trigger" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 4.--7. "COUNT_SEL,Selects one of the 16 input triggers as a count trigger" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0.--3. "CAPTURE_SEL,Selects one of the 16 input triggers as a capture trigger" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x24++0x03
line.long 0x00 "TR_CTRL1,Counter trigger control register 1"
bitfld.long 0x00 8.--9. "START_EDGE,A start event will start the counter i.e" "0: No description available,1: No description available,2: No description available,3: No description available"
bitfld.long 0x00 6.--7. "STOP_EDGE,A stop event will stop the counter i.e" "0: No description available,1: No description available,2: No description available,3: No description available"
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bitfld.long 0x00 4.--5. "RELOAD_EDGE,A reload event will initialize the counter" "0: No description available,1: No description available,2: No description available,3: No description available"
bitfld.long 0x00 2.--3. "COUNT_EDGE,A counter event will increase or decrease the counter by '1'" "0: No description available,1: No description available,2: No description available,3: No description available"
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bitfld.long 0x00 0.--1. "CAPTURE_EDGE,A capture event will copy the counter value into the CC register" "0: No description available,1: No description available,2: No description available,3: No description available"
group.long 0x28++0x03
line.long 0x00 "TR_CTRL2,Counter trigger control register 2"
bitfld.long 0x00 4.--5. "UNDERFLOW_MODE,Determines the effect of a counter underflow event (COUNTER reaches 0 ) on the line_out output signals" "0: No description available,1: No description available,2: No description available,3: No description available"
bitfld.long 0x00 2.--3. "OVERFLOW_MODE,Determines the effect of a counter overflow event (COUNTER reaches PERIOD) on the line_out output signals" "0: No description available,1: No description available,2: No description available,3: No description available"
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bitfld.long 0x00 0.--1. "CC_MATCH_MODE,Determines the effect of a compare match event (COUNTER equals CC register) on the line_out output signals" "0: No description available,1: No description available,2: No description available,3: No description available"
group.long 0x30++0x03
line.long 0x00 "INTR,Interrupt request register"
bitfld.long 0x00 1. "CC_MATCH,Counter matches CC register event" "0,1"
bitfld.long 0x00 0. "TC,Terminal count event" "0,1"
group.long 0x34++0x03
line.long 0x00 "INTR_SET,Interrupt set request register"
bitfld.long 0x00 1. "CC_MATCH,Write with '1' to set corresponding bit in interrupt request register" "0,1"
bitfld.long 0x00 0. "TC,Write with '1' to set corresponding bit in interrupt request register" "0,1"
group.long 0x38++0x03
line.long 0x00 "INTR_MASK,Interrupt mask register"
bitfld.long 0x00 1. "CC_MATCH,Mask bit for corresponding bit in interrupt request register" "0,1"
bitfld.long 0x00 0. "TC,Mask bit for corresponding bit in interrupt request register" "0,1"
group.long 0x3C++0x03
line.long 0x00 "INTR_MASKED,Interrupt masked request register"
rbitfld.long 0x00 1. "CC_MATCH,Logical and of corresponding request and mask bits" "0,1"
rbitfld.long 0x00 0. "TC,Logical and of corresponding request and mask bits" "0,1"
tree.end
autoindent.off
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