4388 lines
533 KiB
Plaintext
4388 lines
533 KiB
Plaintext
; --------------------------------------------------------------------------------
|
|
; @Title: NUC2201 On-Chip Peripherals
|
|
; @Props: Released
|
|
; @Author: NEJ
|
|
; @Changelog: 2022-03-04 NEJ
|
|
; @Manufacturer: NUVOTON - Nuvoton Technology Corp.
|
|
; @Doc: SVD generated based on: NUC2201AE_v1.svd (ver. 1.0)
|
|
; @Core: Cortex-M0
|
|
; @Chip: NUC2201LE3AE, NUC2201SE3AE
|
|
; @Copyright: (C) 1989-2022 Lauterbach GmbH, licensed for use with TRACE32(R) only
|
|
; --------------------------------------------------------------------------------
|
|
; $Id: pernuc2201.per 14448 2022-03-04 10:14:40Z kwisniewski $
|
|
|
|
tree.close "Core Registers (Cortex-M0)"
|
|
AUTOINDENT.PUSH
|
|
AUTOINDENT.OFF
|
|
tree "System Control"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 0x8
|
|
if (CORENAME()=="CORTEXM1")
|
|
group.long 0x10++0x0b
|
|
line.long 0x00 "STCSR,SysTick Control and Status Register"
|
|
bitfld.long 0x00 16. " COUNTFLAG ,Returns 1 if timer counted to 0" "0,1"
|
|
bitfld.long 0x00 2. " CLKSOURCE ,Always reads as one" "No effect,Processor clock"
|
|
textline " "
|
|
bitfld.long 0x00 1. " TICKINT ,Counting down to 0 " "No SysTick,SysTick"
|
|
bitfld.long 0x00 0. " ENABLE ,Counter enable" "Disabled,Enabled"
|
|
line.long 0x04 "STRVR,SysTick Reload Value Register"
|
|
hexmask.long.tbyte 0x04 0.--23. 1. " RELOAD ,Value to load into the STCVR when the counter reaches 0"
|
|
line.long 0x08 "STCVR,SysTick Current Value Register"
|
|
hexmask.long.tbyte 0x08 0.--23. 1. " CURRENT ,Reads return the current value of the SysTick counter"
|
|
else
|
|
group.long 0x10++0x0b
|
|
line.long 0x00 "STCSR,SysTick Control and Status Register"
|
|
bitfld.long 0x00 16. " COUNTFLAG ,Returns 1 if timer counted to 0" "0,1"
|
|
bitfld.long 0x00 2. " CLKSOURCE ,Always reads as one" "External clock,Processor clock"
|
|
textline " "
|
|
bitfld.long 0x00 1. " TICKINT ,Counting down to 0 " "No SysTick,SysTick"
|
|
bitfld.long 0x00 0. " ENABLE ,Counter enable" "Disabled,Enabled"
|
|
line.long 0x04 "STRVR,SysTick Reload Value Register"
|
|
hexmask.long.tbyte 0x04 0.--23. 1. " RELOAD ,Value to load into the STCVR when the counter reaches 0"
|
|
line.long 0x08 "STCVR,SysTick Current Value Register"
|
|
hexmask.long.tbyte 0x08 0.--23. 1. " CURRENT ,Reads return the current value of the SysTick counter"
|
|
endif
|
|
if (CORENAME()=="CORTEXM1")
|
|
rgroup.long 0x1c++0x03
|
|
line.long 0x00 "STCR,SysTick Calibration Value Register"
|
|
bitfld.long 0x00 31. " NOREF ,Reads as one" "0,1"
|
|
bitfld.long 0x00 30. " SKEW ,Reads as zero" "0,1"
|
|
textline " "
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,Indicates calibration value is not known"
|
|
else
|
|
rgroup.long 0x1c++0x03
|
|
line.long 0x00 "STCR,SysTick Calibration Value Register"
|
|
bitfld.long 0x00 31. " NOREF ,Indicates whether the IMPL_DEF reference clock is provided" "Implemented,Not implemented"
|
|
bitfld.long 0x00 30. " SKEW ,Indicates whether the 10ms calibration value is exact" "Exact,Inexact"
|
|
textline " "
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,Holds a reload value to be used for 10ms (100Hz) timing subject to system clock skew errors"
|
|
endif
|
|
rgroup.long 0xd00++0x03
|
|
line.long 0x00 "CPUID,CPU ID Base Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " IMPLEMENTER ,Implementer code"
|
|
hexmask.long.byte 0x00 20.--23. 1. " VARIANT ,Implementation defined variant number"
|
|
textline " "
|
|
hexmask.long.byte 0x00 4.--15. 1. " PARTNO ,Number of processor within family"
|
|
hexmask.long.byte 0x00 0.--3. 1. " REVISION ,Implementation defined revision number"
|
|
group.long 0xd04++0x03
|
|
line.long 0x00 "ICSR,Interrupt Control State Register"
|
|
bitfld.long 0x00 31. " NMIPENDSET ,Setting this bit will activate an NMI" "No effect,Set pending"
|
|
bitfld.long 0x00 28. " PENDSVSET ,Set a pending PendSV interrupt" "No effect,Set pending"
|
|
textline " "
|
|
bitfld.long 0x00 27. " PENDSVCLR ,Clear a pending PendSV interrupt" "No effect,Clear pending"
|
|
bitfld.long 0x00 26. " PENDSTSET ,Set a pending SysTick" "No effect,Set pending"
|
|
textline " "
|
|
bitfld.long 0x00 25. " PENDSVCLR ,Clear a pending SysTick" "No effect,Clear pending"
|
|
bitfld.long 0x00 23. " ISRPREEMPT ,Pending exception service" "No service,Service"
|
|
textline " "
|
|
bitfld.long 0x00 22. " ISRPENDING ,External interrupt pending flag" "No interrupt,Interrupt"
|
|
hexmask.long.byte 0x00 12.--17. 1. " VECTPENDING ,Active exception number field"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--5. 1. " VECTACTIVET ,Active exception number field"
|
|
if (CORENAME()=="CORTEXM0+")
|
|
group.long 0xd08++0x03
|
|
line.long 0x00 "VTOR,Vector Table Offset Register"
|
|
hexmask.long 0x00 7.--31. 0x80 " TBLOFF ,Vector table address"
|
|
else
|
|
textline " "
|
|
endif
|
|
group.long 0xd0c++0x03
|
|
line.long 0x00 "AIRCR,Application Interrupt and Reset Control Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " VECTKEY ,Vector Key"
|
|
bitfld.long 0x00 15. " ENDIANNESS ,Data endianness bit" "Little-endian,Big-endian"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SYSRESETREQ ,System reset setup request" "No effect,Reset"
|
|
bitfld.long 0x00 1. " VECTCLRACTIVE ,Clears all active state information" "No clear,Clear"
|
|
group.long 0xd10++0x03
|
|
line.long 0x00 "SCR,System Control Register"
|
|
bitfld.long 0x00 4. " SEVONPEND ,Determines whether an interrupt transition from inactive state to pending state is a wakeup event" "Not wakeup,Wakeup"
|
|
bitfld.long 0x00 2. " SLEEPDEEP ,Provides a qualifying hint indicating that waking from sleep might take longer" "Not deep sleep,Deep sleep"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SLEEPONEXIT ,Determines whether, on an exit from an ISR that returns to the base level of execution priority, the processor enters a sleep state" "Disabled,Enabled"
|
|
rgroup.long 0xd14++0x03
|
|
line.long 0x00 "CCR,Configuration and Control Register"
|
|
bitfld.long 0x00 9. " STKALIGN ,Indicates whether on exception entry all exceptions are entered with 8-byte stack alignment and the context to restore it is saved" "Reserved,Aligned"
|
|
bitfld.long 0x00 3. " UNALIGN_TRP ,Indicates that all unaligned accesses results in a Hard Fault" "Reserved,Trapped"
|
|
group.long 0xd1c++0x0b
|
|
line.long 0x00 "SHPR2,System Handler Priority Register 2"
|
|
bitfld.long 0x00 30.--31. " PRI_11 ,Priority of system handler 11-SVCall" "00,01,10,11"
|
|
line.long 0x04 "SHPR3,System Handler Priority Register 3"
|
|
bitfld.long 0x04 30.--31. " PRI_15 ,Priority of system handler 15-SysTick" "00,01,10,11"
|
|
bitfld.long 0x04 22.--23. " PRI_14 ,Priority of system handler 14- PendSV" "00,01,10,11"
|
|
line.long 0x08 "SHCSR,System Handler Control and State Register"
|
|
bitfld.long 0x08 15. " SVCALLPENDED ,Reads as 1 if SVCall is pending" "Not pending,Pending"
|
|
if (CORENAME()=="CORTEXM0+")
|
|
hgroup.long 0x08++0x03
|
|
hide.long 0x00 "ACTLR,Auxiliary Control Register"
|
|
else
|
|
textline " "
|
|
endif
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Nested Vectored Interrupt Controller (NVIC)"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 12.
|
|
tree "Interrupt Enable Registers"
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "SET/CLREN,Interrupt Set/Clear Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
tree.end
|
|
tree "Interrupt Pending Registers"
|
|
group.long 0x200++0x03
|
|
line.long 0x00 "SET/CLRPEN,Interrupt Set/Clear Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
tree.end
|
|
width 6.
|
|
tree "Interrupt Priority Registers"
|
|
group.long 0x400++0x1F
|
|
line.long 0x00 "INT0,Interrupt Priority Register"
|
|
bitfld.long 0x00 30.--31. " IP_3 ,Priority of interrupt 3" "0,1,2,3"
|
|
bitfld.long 0x00 22.--23. " IP_2 ,Priority of interrupt 2" "0,1,2,3"
|
|
bitfld.long 0x00 14.--15. " IP_1 ,Priority of interrupt 1" "0,1,2,3"
|
|
bitfld.long 0x00 6.--7. " IP_0 ,Priority of interrupt 0" "0,1,2,3"
|
|
line.long 0x04 "INT1,Interrupt Priority Register"
|
|
bitfld.long 0x04 30.--31. " IP_7 ,Priority of interrupt 7" "0,1,2,3"
|
|
bitfld.long 0x04 22.--23. " IP_6 ,Priority of interrupt 6" "0,1,2,3"
|
|
bitfld.long 0x04 14.--15. " IP_5 ,Priority of interrupt 5" "0,1,2,3"
|
|
bitfld.long 0x04 6.--7. " IP_4 ,Priority of interrupt 4" "0,1,2,3"
|
|
line.long 0x08 "INT2,Interrupt Priority Register"
|
|
bitfld.long 0x08 30.--31. " IP_11 ,Priority of interrupt 11" "0,1,2,3"
|
|
bitfld.long 0x08 22.--23. " IP_10 ,Priority of interrupt 10" "0,1,2,3"
|
|
bitfld.long 0x08 14.--15. " IP_9 ,Priority of interrupt 9" "0,1,2,3"
|
|
bitfld.long 0x08 6.--7. " IP_8 ,Priority of interrupt 8" "0,1,2,3"
|
|
line.long 0x0C "INT3,Interrupt Priority Register"
|
|
bitfld.long 0x0C 30.--31. " IP_15 ,Priority of interrupt 15" "0,1,2,3"
|
|
bitfld.long 0x0C 22.--23. " IP_14 ,Priority of interrupt 14" "0,1,2,3"
|
|
bitfld.long 0x0C 14.--15. " IP_13 ,Priority of interrupt 13" "0,1,2,3"
|
|
bitfld.long 0x0C 6.--7. " IP_12 ,Priority of interrupt 12" "0,1,2,3"
|
|
line.long 0x10 "INT4,Interrupt Priority Register"
|
|
bitfld.long 0x10 30.--31. " IP_19 ,Priority of interrupt 19" "0,1,2,3"
|
|
bitfld.long 0x10 22.--23. " IP_18 ,Priority of interrupt 18" "0,1,2,3"
|
|
bitfld.long 0x10 14.--15. " IP_17 ,Priority of interrupt 17" "0,1,2,3"
|
|
bitfld.long 0x10 6.--7. " IP_16 ,Priority of interrupt 16" "0,1,2,3"
|
|
line.long 0x14 "INT5,Interrupt Priority Register"
|
|
bitfld.long 0x14 30.--31. " IP_23 ,Priority of interrupt 23" "0,1,2,3"
|
|
bitfld.long 0x14 22.--23. " IP_22 ,Priority of interrupt 22" "0,1,2,3"
|
|
bitfld.long 0x14 14.--15. " IP_21 ,Priority of interrupt 21" "0,1,2,3"
|
|
bitfld.long 0x14 6.--7. " IP_20 ,Priority of interrupt 20" "0,1,2,3"
|
|
line.long 0x18 "INT6,Interrupt Priority Register"
|
|
bitfld.long 0x18 30.--31. " IP_27 ,Priority of interrupt 27" "0,1,2,3"
|
|
bitfld.long 0x18 22.--23. " IP_26 ,Priority of interrupt 26" "0,1,2,3"
|
|
bitfld.long 0x18 14.--15. " IP_25 ,Priority of interrupt 25" "0,1,2,3"
|
|
bitfld.long 0x18 6.--7. " IP_24 ,Priority of interrupt 24" "0,1,2,3"
|
|
line.long 0x1C "INT7,Interrupt Priority Register"
|
|
bitfld.long 0x1C 30.--31. " IP_31 ,Priority of interrupt 31" "0,1,2,3"
|
|
bitfld.long 0x1C 22.--23. " IP_30 ,Priority of interrupt 30" "0,1,2,3"
|
|
bitfld.long 0x1C 14.--15. " IP_29 ,Priority of interrupt 29" "0,1,2,3"
|
|
bitfld.long 0x1C 6.--7. " IP_28 ,Priority of interrupt 28" "0,1,2,3"
|
|
tree.end
|
|
width 0x0B
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Debug"
|
|
tree "Core Debug"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 0xA
|
|
group.long 0xD30++0x03
|
|
line.long 0x00 "DFSR,Data Fault Status Register"
|
|
eventfld.long 0x00 4. " EXTERNAL ,External debug request flag" "No occurred,Occurred"
|
|
eventfld.long 0x00 3. " VCATCH ,Vector catch flag" "No occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 2. " DWTRAP ,Data Watchpoint flag" "No match,Match"
|
|
textline " "
|
|
eventfld.long 0x00 1. " BKPT ,BKPT flag" "No match,Match"
|
|
eventfld.long 0x00 0. " HALTED ,Halt request flag" "No request,Request"
|
|
if (CORENAME()=="CORTEXM1")
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDF0))&0x01)==0x00)
|
|
group.long 0xDF0++0x03
|
|
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
|
|
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
|
|
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not completed,Completed"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 18. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
|
|
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available"
|
|
textline " "
|
|
textline " "
|
|
textfld " "
|
|
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xDF0++0x03
|
|
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
|
|
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
|
|
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not read,Read"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 18. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
|
|
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available"
|
|
textline " "
|
|
bitfld.long 0x00 3. " C_MASKINTS ,Interrupts Mask" "Not masked,Masked"
|
|
bitfld.long 0x00 2. " C_STEP ,Steps the core in halted debug" "Not halted,Halted"
|
|
textline " "
|
|
bitfld.long 0x00 1. " C_HALT ,Core Halted" "Not halted,Halted"
|
|
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDF0))&0x01)==0x00)
|
|
group.long 0xDF0++0x03
|
|
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
|
|
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
|
|
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not completed,Completed"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " S_LOCKUP/DBGKEY ,Core Lockup Status/Debug Key" "Not locked up,Locked up"
|
|
bitfld.long 0x00 18. " S_SLEEP/DBGKEY ,Core Sleep Status/Debug Key" "Not sleeping,Sleeping"
|
|
textline " "
|
|
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
|
|
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available"
|
|
textline " "
|
|
textline " "
|
|
textfld " "
|
|
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xDF0++0x03
|
|
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
|
|
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
|
|
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not read,Read"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " S_LOCKUP/DBGKEY ,Core Lockup Status/Debug Key" "Not locked up,Locked up"
|
|
bitfld.long 0x00 18. " S_SLEEP/DBGKEY ,Core Sleep Status/Debug Key" "Not sleeping,Sleeping"
|
|
textline " "
|
|
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
|
|
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available"
|
|
textline " "
|
|
bitfld.long 0x00 3. " C_MASKINTS ,Interrupts Mask" "Not masked,Masked"
|
|
bitfld.long 0x00 2. " C_STEP ,Steps the core in halted debug" "Not halted,Halted"
|
|
textline " "
|
|
bitfld.long 0x00 1. " C_HALT ,Core Halted" "Not halted,Halted"
|
|
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
wgroup.long 0xDF4++0x03
|
|
line.long 0x00 "DCRSR,Debug Core Selector Register"
|
|
bitfld.long 0x00 16. " REGWnR ,Register Read/Write" "Read,Write"
|
|
bitfld.long 0x00 0.--4. " REGSEL ,Register Selection" "R0,R1,R2,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,Current SP,LR,DebugReturnAddress,xPSR Flags,MSP,PSP,Reserved,CONTROL[1]/PRIMASK[0],?..."
|
|
group.long 0xDF8++0x07
|
|
line.long 0x00 "DCRDR,Debug Core Register Data Register"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,Data for reading and writing registers to and from the processor"
|
|
line.long 0x04 "DEMCR,Debug Exception and Monitor Control Register"
|
|
bitfld.long 0x04 24. " DWTENA ,Global enable or disable for the DW unit" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " VC_HARDERR ,Debug trap on a Hard Fault" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x04 0. " VC_CORERESET ,Reset Vector Catch" "No reset,Reset"
|
|
width 0x0B
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Breakpoint Unit (BPU)"
|
|
sif COMPonent.AVAILABLE("BPU")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("BPU",-1))
|
|
width 8.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "BP_CTRL,Breakpoint Control Register"
|
|
bitfld.long 0x00 4.--7. " NUM_CODE1 ,Number of comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 1. " KEY ,Key field" "No write,Write"
|
|
bitfld.long 0x00 0. " ENABLE ,Breakpoint unit enable bit" "Disabled,Enabled"
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "B_COMP0,Breakpoint Comparator Registers 0"
|
|
bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords"
|
|
hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 0" "Disabled,Enabled"
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "B_COMP1,Breakpoint Comparator Registers 1"
|
|
bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords"
|
|
hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 1" "Disabled,Enabled"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "B_COMP2,Breakpoint Comparator Registers 2"
|
|
bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords"
|
|
hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 2" "Disabled,Enabled"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "B_COMP3,Breakpoint Comparator Registers 3"
|
|
bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords"
|
|
hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 3" "Disabled,Enabled"
|
|
else
|
|
newline
|
|
textline "BPU component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Data Watchpoint and Trace Unit (DWT)"
|
|
sif COMPonent.AVAILABLE("DWT")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))
|
|
width 14.
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "DW_CTRL,DW Control Register "
|
|
bitfld.long 0x00 28.--31. " NUM_CODE1 ,Number of comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0x1c++0x03
|
|
line.long 0x00 "DW_PCSR,DW Program Counter Sample Register"
|
|
hexmask.long 0x00 0.--31. 1. " EIASAMPLE ,Execution instruction address sample or 0xFFFFFFFF"
|
|
group.long 0x20++0x0b
|
|
line.long 0x00 "DW_COMP0,DW Comparator Register 0"
|
|
hexmask.long 0x00 0.--31. 1. " COMP1 ,Compare against PC or the data address"
|
|
line.long 0x04 "DW_MASK0,DW Mask Register 0"
|
|
hexmask.long.byte 0x04 0.--4. 1. " MASK ,Mask on data address when matching against COMP"
|
|
line.long 0x08 "DW_FUNCTION0,DW Function Register 0"
|
|
bitfld.long 0x08 24. " MATCHED ,Comparator match" "No match,Match"
|
|
bitfld.long 0x08 0.--3. " FUNCTION , Settings for DW Function Registers" "Disabled,Reserved,Reserved,Reserved,On PC match,Read address,Write address,R/W address,?..."
|
|
group.long 0x30++0x0b
|
|
line.long 0x00 "DW_COMP1,DW Comparator Register 1"
|
|
hexmask.long 0x00 0.--31. 1. " COMP ,Compare against PC or the data address"
|
|
line.long 0x04 "DW_MASK1,DW Mask Register 1 "
|
|
hexmask.long.byte 0x04 0.--4. 1. " MASK ,Mask on data address when matching against COMP"
|
|
line.long 0x08 "DW_FUNCTION1,DW Function Register 1"
|
|
bitfld.long 0x08 24. " MATCHED ,Comparator match" "No match,Match"
|
|
bitfld.long 0x08 0.--3. " FUNCTION , Settings for DW Function Registers" "Disabled,Reserved,Reserved,Reserved,On PC match,Read address,Write address,R/W address,?..."
|
|
else
|
|
newline
|
|
textline "DWT component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree.end
|
|
AUTOINDENT.POP
|
|
tree.end
|
|
autoindent.on center tree
|
|
tree "ADC"
|
|
base ad:0x400E0000
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "ADDR0,ADC Data Register 0"
|
|
bitfld.long 0x00 17. "VALID,Valid Flag\nThis bit is set to 1 when corresponding channel analog input conversion is completed and cleared by hardware after ADDR register is read.\nThis is a read only bit" "0: Data in RSLT bits (ADDRx[15:0] x=0~7) is not..,1: Data in RSLT bits (ADDRx[15:0] x=0~7) is valid"
|
|
bitfld.long 0x00 16. "OVERRUN,Overrun Flag\nIf converted data in RSLT has not been read before new conversion result is loaded to this register OVERRUN is set to 1 and previous conversion result is gone" "0: Data in RSLT (ADDRx[15:0] x=0~11) is recent..,1: Data in RSLT (ADDRx[15:0] x=0~11) is.."
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "RSLT,A/D Conversion Result\nThis field contains conversion result of ADC"
|
|
repeat 7. (strings "1" "2" "3" "4" "5" "6" "7" )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 )
|
|
group.long ($2+0x04)++0x03
|
|
line.long 0x00 "ADDR$1,ADC Data Register $1"
|
|
rbitfld.long 0x00 17. "VALID,Valid Flag\nThis bit is set to 1 when corresponding channel analog input conversion is completed and cleared by hardware after ADDR register is read.\nThis is a read only bit" "0: Data in RSLT bits (ADDRx[15:0] x=0~7) is not..,1: Data in RSLT bits (ADDRx[15:0] x=0~7) is valid"
|
|
rbitfld.long 0x00 16. "OVERRUN,Overrun Flag\nIf converted data in RSLT has not been read before new conversion result is loaded to this register OVERRUN is set to 1 and previous conversion result is gone" "0: Data in RSLT (ADDRx[15:0] x=0~11) is recent..,1: Data in RSLT (ADDRx[15:0] x=0~11) is.."
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "RSLT,A/D Conversion Result\nThis field contains conversion result of ADC"
|
|
repeat.end
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "ADCR,ADC Control Register"
|
|
bitfld.long 0x00 31. "DMOF,A/D Differential Input Mode Output Format" "0: A/D Conversion result will be filled in RSLT..,1: A/D Conversion result will be filled in RSLT.."
|
|
bitfld.long 0x00 11. "ADST,A/D Conversion Start\nADST bit can be set to 1 from three sources: software PWM Center-aligned trigger and external pin STADC" "0: Conversion stops and A/D converter enter idle..,1: Conversion starts"
|
|
newline
|
|
bitfld.long 0x00 10. "DIFFEN,Differential Input Mode Control" "0: Single-end analog input mode,1: Differential analog input mode"
|
|
bitfld.long 0x00 9. "PTEN,PDMA Transfer Enable Bit" "0: PDMA data transfer Disabled,1: PDMA data transfer in ADDR 0~11 Enabled"
|
|
newline
|
|
bitfld.long 0x00 8. "TRGEN,Hardware Trigger Enable Bit\nEnable or disable triggering of A/D conversion by hardware (external STADC pin or PWM Center-aligned trigger).\nADC hardware trigger function is only supported in single-cycle scan mode.\nIf hardware trigger mode the.." "0: Disabled,1: Enabled"
|
|
bitfld.long 0x00 6.--7. "TRGCOND,External Trigger Condition\nThese two bits decide external pin STADC trigger event is level or edge" "0: Low level,1: High level,2: Falling edge,3: Rising edge"
|
|
newline
|
|
bitfld.long 0x00 4.--5. "TRGS,Hardware Trigger Source\nSoftware should disable TRGEN (ADCR[8]) and ADST (ADCR[11]) before change TRGS" "0: A/D conversion is started by external STADC pin,?,?,3: A/D conversion is started by PWM.."
|
|
bitfld.long 0x00 2.--3. "ADMD,A/D Converter Operation Mode\nWhen changing the operation mode software should disable ADST bit (ADCR[11]) firstly" "0: Single conversion,1: Reserved,2: Single-cycle scan,3: Continuous scan"
|
|
newline
|
|
bitfld.long 0x00 1. "ADIE,A/D Interrupt Enable Bit\nA/D conversion end interrupt request is generated if ADIE bit (ADCR[1]) is set to 1" "0: A/D interrupt function Disabled,1: A/D interrupt function Enabled"
|
|
bitfld.long 0x00 0. "ADEN,A/D Converter Enable Bit\nBefore starting A/D conversion function this bit should be set to 1" "0: Disabled,1: Enabled"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "ADCHER,ADC Channel Enable Register"
|
|
bitfld.long 0x00 10.--13. "CHEN1,Analog Input Channel Enable Bit 1\nSet CHEN[14:10] to enable the corresponding analog input channel 11 ~ 8" "0: ADC input channel Disabled,1: ADC input channel Enabled,?..."
|
|
bitfld.long 0x00 8.--9. "PRESEL,Analog Input Channel 7 Selection" "0: External analog input,1: Internal band-gap voltage,2: Internal temperature sensor,3: Reserved"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "CHEN,Analog Input Channel Enable Bit\nSet CHEN[7:0] to enable the corresponding analog input channel 7 ~ 0"
|
|
repeat 2. (strings "0" "1" )(list 0x0 0x4 )
|
|
group.long ($2+0x28)++0x03
|
|
line.long 0x00 "ADCMPR$1,ADC Compare Register $1"
|
|
hexmask.long.word 0x00 16.--27. 1. "CMPD,Comparison Data\nThe 12-bit data is used to compare with conversion result of specified channel.\nWhen DMOF bit (ADCR[31]) is set to 0 ADC comparator compares CMPD with conversion result with unsigned format"
|
|
bitfld.long 0x00 8.--11. "CMPMATCNT,Compare Match Count\nWhen the specified A/D channel analog conversion result matches the compare condition defined by CMPCOND (ADCMPR0/1[2]) the internal match counter will increase 1 The comparing data must successively matched with the.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 3.--6. "CMPCH,Compare Channel Selection" "0: Channel 0 conversion result is selected to be..,1: Channel 1 conversion result is selected to be..,2: Channel 2 conversion result is selected to be..,3: Channel 3 conversion result is selected to be..,4: Channel 4 conversion result is selected to be..,5: Channel 5 conversion result is selected to be..,6: Channel 6 conversion result is selected to be..,7: Channel 7 conversion result is selected to be..,8: Channel 8 conversion result is selected to be..,9: Channel 9 conversion result is selected to be..,10: Channel 10 conversion result is selected to..,11: Channel 11 conversion result is selected to..,?..."
|
|
bitfld.long 0x00 2. "CMPCOND,Compare Condition\nNote: When the internal counter reaches the value to (CMPMATCNT (ADCMPR0/1[11:8])+1) the CMPF0/1 bit (ADSR[1]/[2]) will be set" "0: Set the compare condition as that when a..,1: Set the compare condition as that when a.."
|
|
newline
|
|
bitfld.long 0x00 1. "CMPIE,Compare Interrupt Enable Bit\nIf the compare function is enabled and the compare condition matches the setting of CMPCOND (ADCMPR0/1[2]) and CMPMATCNT (ADCMPR0/1[11:8]) CMPF0/1 bit (ADSR[1]/[2]) will be asserted in the meanwhile if CMPIE.." "0: Compare function interrupt Disabled,1: Compare function interrupt Enabled"
|
|
bitfld.long 0x00 0. "CMPEN,Compare Enable Bit\nSet this bit to 1 to enable ADC controller to compare CMPD (ADCMPR0/1[27:16]) with specified channel conversion result when converted data is loaded into ADDR register" "0: Compare function Disabled,1: Compare function Enabled"
|
|
repeat.end
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "ADSR,ADC Status Register"
|
|
bitfld.long 0x00 28.--31. "OVERRUN1,Overrun Flag\nIt is a mirror to OVERRUN bit (ADDR8~11[16]).\nIt is read only" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. "VALID1,Data Valid Flag\nIt is a mirror of VALID bit (ADDR8~11[17]).\nIt is read only" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. "OVERRUN0,Overrun Flag\nIt is a mirror to OVERRUN bit (ADDR0~7[16]).\nIt is read only"
|
|
hexmask.long.byte 0x00 8.--15. 1. "VALID0,Data Valid Flag\nIt is a mirror of VALID bit (ADDR0~7[17]).\nIt is read only"
|
|
newline
|
|
bitfld.long 0x00 4.--7. "CHANNEL,Current Conversion Channel\nIt is read only" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 3. "BUSY,BUSY/IDLE\nThis bit is mirror of as ADST bit (ADCR[11]).\nIt is read only" "0: A/D converter is in idle state,1: A/D converter is busy at conversion"
|
|
newline
|
|
bitfld.long 0x00 2. "CMPF1,Compare Flag\nWhen the selected channel A/D conversion result meets setting condition in ADCMPR1 then this bit is set to 1" "0: Conversion result in ADDR does not meet..,1: Conversion result in ADDR meets ADCMPR1 setting"
|
|
bitfld.long 0x00 1. "CMPF0,Compare Flag\nWhen the selected channel A/D conversion result meets setting condition in ADCMPR0 then this bit is set to 1" "0: Conversion result in ADDR does not meet..,1: Conversion result in ADDR meets ADCMPR0 setting"
|
|
newline
|
|
bitfld.long 0x00 0. "ADF,A/D Conversion End Flag\nA status flag that indicates the end of A/D conversion.\nADF is set to 1 at these two conditions:\n1" "0,1"
|
|
rgroup.long 0x40++0x03
|
|
line.long 0x00 "ADPDMA,ADC PDMA Current Transfer Data Register"
|
|
hexmask.long.tbyte 0x00 0.--17. 1. "AD_PDMA,ADC PDMA Current Transfer Data Register\nWhen PDMA transferring read this register can monitor current PDMA transfer data.\nCurrent PDMA transfer data is the content of ADDR0 ~ ADDR11.\nThis is a read only register"
|
|
repeat 4. (strings "8" "9" "10" "11" )(list 0x0 0x4 0x8 0xC )
|
|
group.long ($2+0x50)++0x03
|
|
line.long 0x00 "ADDR$1,ADC Data Register $1"
|
|
rbitfld.long 0x00 17. "VALID,Valid Flag\nThis bit is set to 1 when corresponding channel analog input conversion is completed and cleared by hardware after ADDR register is read.\nThis is a read only bit" "0: Data in RSLT bits (ADDRx[15:0] x=0~7) is not..,1: Data in RSLT bits (ADDRx[15:0] x=0~7) is valid"
|
|
rbitfld.long 0x00 16. "OVERRUN,Overrun Flag\nIf converted data in RSLT has not been read before new conversion result is loaded to this register OVERRUN is set to 1 and previous conversion result is gone" "0: Data in RSLT (ADDRx[15:0] x=0~11) is recent..,1: Data in RSLT (ADDRx[15:0] x=0~11) is.."
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "RSLT,A/D Conversion Result\nThis field contains conversion result of ADC"
|
|
repeat.end
|
|
tree.end
|
|
tree "CLK"
|
|
base ad:0x50000200
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "PWRCON,System Power-down Control Register"
|
|
bitfld.long 0x00 12. "OSC48M_EN,48 MHz Internal High Speed RC Oscillator (HIRC48) Enable Bit (Write Protect)\nNote: This bit is write protected" "0: 48 MHz internal high speed RC oscillator..,1: 48 MHz internal high speed RC oscillator.."
|
|
bitfld.long 0x00 8. "PD_WAIT_CPU,Power-Down Entry Condition Control (Write Protect)\nNote: This bit is the protected bit and programming it needs to write '59h' '16h' and '88h' to address 0x5000_0100 to disable register protection" "0: Chip enters Power-down mode when the..,1: Chip enters Power- down mode when the both.."
|
|
newline
|
|
bitfld.long 0x00 7. "PWR_DOWN_EN,System Power-Down Enable Bit (Write Protect)\nWhen this bit is set to 1 Power-down mode is enabled and chip Power-down behavior will depends on the PD_WAIT_CPU bit\n(a) If the PD_WAIT_CPU is 0 the chip enters Power-down mode immediately.." "0: Chip operating normally or chip in Idle mode..,1: Chip enters Power-down mode instantly or.."
|
|
bitfld.long 0x00 6. "PD_WU_STS,Power-Down Mode Wake-Up Interrupt Status\nSet by 'Power-down wake-up event' it indicates that resume from Power-down mode' \nThe flag is set if the GPIO USB UART WDT I2C TIMER BOD or RTC wake-up occurred\nWrite 1 to clear the bit to 0.\nNote:.." "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "PD_WU_INT_EN,Power-Down Mode Wake-Up Interrupt Enable Bit (Write Protect)\nNote1: The interrupt will occur when both PD_WU_STS and PD_WU_INT_EN are high.\nNote2: This bit is the protected bit and programming it needs to write '59h' '16h' and '88h' to.." "0: Power-down mode wake-up interrupt Disabled,1: Power-down mode wake-up interrupt Enabled"
|
|
bitfld.long 0x00 4. "PD_WU_DLY,Wake-Up Delay Counter Enable Bit (Write Protect)\nWhen the chip wakes up from Power-down mode the clock control will delay certain clock cycles to wait system clock stable.\nThe delayed clock cycle is 4096 clock cycles when chip work at.." "0: Clock cycles delay Disabled,1: Clock cycles delay Enabled"
|
|
newline
|
|
bitfld.long 0x00 3. "OSC10K_EN,10 KHz Internal Low Speed RC Oscillator (LIRC) Enable Bit (Write Protect)\nNote: This bit is the protected bit and programming it needs to write '59h' '16h' and '88h' to address 0x5000_0100 to disable register protection" "0: 10 kHz internal low speed RC oscillator..,1: 10 kHz internal low speed RC oscillator.."
|
|
bitfld.long 0x00 2. "OSC22M_EN,22.1184 MHz Internal High Speed RC Oscillator (HIRC) Enable Bit (Write Protect)\nNote: This bit is the protected bit and programming it needs to write '59h' '16h' and '88h' to address 0x5000_0100 to disable register protection" "0: 22.1184 MHz internal high speed RC oscillator..,1: 22.1184 MHz internal high speed RC oscillator.."
|
|
newline
|
|
bitfld.long 0x00 1. "XTL32K_EN,32.768 KHz External Low Speed Crystal Oscillator (LXT) Enable Bit (Write Protect)\nNote: This bit is the protected bit and programming it needs to write '59h' '16h' and '88h' to address 0x5000_0100 to disable register protection" "0: 32.768 kHz external low speed crystal..,1: 32.768 kHz external low speed crystal.."
|
|
bitfld.long 0x00 0. "XTL12M_EN,4~24 MHz External High Speed Crystal Oscillator (HXT) Enable Bit (Write Protect)\nThe bit default value is set by flash controller user configuration register CONFIG0 [26:24]" "0: 4 ~ 24 MHz external high speed crystal..,1: 4~24 MHz external high speed crystal.."
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "AHBCLK,AHB Devices Clock Enable Control Register"
|
|
bitfld.long 0x00 3. "EBI_EN,EBI Controller Clock Enable Control" "0: EBI engine clock Disabled,1: EBI engine clock Enabled"
|
|
bitfld.long 0x00 2. "ISP_EN,Flash ISP Controller Clock Enable Bit" "0: Flash ISP peripherial clock Disabled,1: Flash ISP peripherial clock Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. "PDMA_EN,PDMA Controller Clock Enable Bit" "0: PDMA peripherial clock Disabled,1: PDMA peripherial clock Enabled"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "APBCLK,APB Devices Clock Enable Control Register"
|
|
bitfld.long 0x00 28. "ADC_EN,Analog-Digital-Converter (ADC) Clock Enable Bit" "0: ADC clock Disabled,1: ADC clock Enabled"
|
|
bitfld.long 0x00 27. "USBD_EN,USB 2.0 FS Device Controller Clock Enable Bit" "0: USB clock Disabled,1: USB clock Enabled"
|
|
newline
|
|
bitfld.long 0x00 22. "PWM45_EN,PWM_45 Clock Enable Bit" "0: PWM45 clock Disabled,1: PWM45 clock Enabled"
|
|
bitfld.long 0x00 21. "PWM23_EN,PWM_23 Clock Enable Bit" "0: PWM23 clock Disabled,1: PWM23 clock Enabled"
|
|
newline
|
|
bitfld.long 0x00 20. "PWM01_EN,PWM_01 Clock Enable Bit" "0: PWM01 clock Disabled,1: PWM01 clock Enabled"
|
|
bitfld.long 0x00 18. "UART2_EN,UART2 Clock Enable Bit" "0: UART2 clock Disabled,1: UART2 clock Enabled"
|
|
newline
|
|
bitfld.long 0x00 17. "UART1_EN,UART1 Clock Enable Bit" "0: UART1 clock Disabled,1: UART1 clock Enabled"
|
|
bitfld.long 0x00 16. "UART0_EN,UART0 Clock Enable Bit" "0: UART0 clock Disabled,1: UART0 clock Enabled"
|
|
newline
|
|
bitfld.long 0x00 13. "SPI1_EN,SPI1 Clock Enable Bit" "0: SPI1 clock Disabled,1: SPI1 clock Enabled"
|
|
bitfld.long 0x00 12. "SPI0_EN,SPI0 Clock Enable Bit" "0: SPI0 clock Disabled,1: SPI0 clock Enabled"
|
|
newline
|
|
bitfld.long 0x00 9. "I2C1_EN,I2C1 Clock Enable Bit" "0: I2C1 clock Disabled,1: I2C1 clock Enabled"
|
|
bitfld.long 0x00 8. "I2C0_EN,I2C0 Clock Enable Bit" "0: I2C0 clock Disabled,1: I2C0 clock Enabled"
|
|
newline
|
|
bitfld.long 0x00 6. "FDIV_EN,Frequency Divider Output Clock Enable Bit" "0: FDIV clock Disabled,1: FDIV clock Enabled"
|
|
bitfld.long 0x00 5. "TMR3_EN,Timer3 Clock Enable Bit" "0: Timer3 clock Disabled,1: Timer3 clock Enabled"
|
|
newline
|
|
bitfld.long 0x00 4. "TMR2_EN,Timer2 Clock Enable Bit" "0: Timer2 clock Disabled,1: Timer2 clock Enabled"
|
|
bitfld.long 0x00 3. "TMR1_EN,Timer1 Clock Enable Bit" "0: Timer1 clock Disabled,1: Timer1 clock Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. "TMR0_EN,Timer0 Clock Enable Bit" "0: Timer0 clock Disabled,1: Timer0 clock Enabled"
|
|
bitfld.long 0x00 1. "RTC_EN,Real-Time-Clock APB Interface Clock Enable Bit\nThis bit is used to control the RTC APB clock only The RTC peripheral clock source is selected from RTC_SEL_10K(CLKSEL2[18])" "0: RTC clock Disabled,1: RTC clock Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. "WDT_EN,Watchdog Timer Clock Enable Bit (Write Protect)\nNote: This bit is the protected bit and programming it needs to write '59h' '16h' and '88h' to address 0x5000_0100 to disable register protection" "0: Watchdog Timer clock Disabled,1: Watchdog Timer clock Enabled"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "CLKSTATUS,Clock Status Monitor Register"
|
|
rbitfld.long 0x00 7. "CLK_SW_FAIL,Clock Switching Fail Flag (Read Only)\nThis bit is an index that if current system clock source is match as user defined at HCLK_S (CLKSEL[2:0])" "0: Clock switching success,1: Clock switching failure"
|
|
rbitfld.long 0x00 5. "OSC48M_STB,48 MHz Internal High Speed RC Oscillator (HIRC48) Clock Source Stable Flag (Read Only)" "0: 48MHz internal high speed RC oscillator..,1: 48MHz internal high speed RC oscillator.."
|
|
newline
|
|
rbitfld.long 0x00 4. "OSC22M_STB,22.1184 MHz Internal High Speed RC Oscillator (HIRC) Clock Source Stable Flag (Read Only)" "0: 22.1184 MHz internal high speed RC oscillator..,1: 22.1184 MHz internal high speed RC oscillator.."
|
|
rbitfld.long 0x00 3. "OSC10K_STB,Internal 10 KHz Low Speed Oscillator (LIRC) Clock Source Stable Flag (Read Only)" "0: 10 kHz internal low speed RC oscillator..,1: 10 kHz internal low speed RC oscillator.."
|
|
newline
|
|
rbitfld.long 0x00 2. "PLL_STB,Internal PLL Clock Source Stable Flag (Read Only)" "0: Internal PLL clock is not stable or disabled,1: Internal PLL clock is stable in normal mode"
|
|
rbitfld.long 0x00 1. "XTL32K_STB,32.768 KHz External Low Speed Crystallator Oscillator (LXT) Clock Source Stable Flag (Read Only)" "0: 32.768 kHz external low speed crystal..,1: 32.768 kHz external low speed crystal.."
|
|
newline
|
|
rbitfld.long 0x00 0. "XTL12M_STB,4~24 MHz External High Speed Crystal Oscillator (HXT) Clock Source Stable Flag (Read Only)" "0: 4~24 MHz external high speed crystal..,1: 4~24 MHz external high speed crystal.."
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "CLKSEL0,Clock Source Select Control Register 0"
|
|
bitfld.long 0x00 8. "USB_S,USB Clock Source Selection" "0: Clock source from PLL clock,1: Clock source from 48 MHz high speed RC.."
|
|
bitfld.long 0x00 3.--5. "STCLK_S,Cortex-M0 SysTick Clock Source Select (Write Protect)" "0: Clock source from 4~24 MHz external high..,1: Clock source from 32.768 kHz external low..,2: Clock source from 4~24 MHz external high..,3: Clock source from HCLK/2,?,?,?,7: Clock source from 22.1184 MHz internal high.."
|
|
newline
|
|
bitfld.long 0x00 0.--2. "HCLK_S,HCLK Clock Source Select (Write Protect)\nBefore clock switching the related clock sources (both pre-select and new-select) must be enabled\nThe 3-bit default value is reloaded from the value of CFOSC (CONFIG0[26:24]) in user configuration.." "0: Clock source from 4~24 MHz external high..,1: Clock source from 32.768 kHz external low..,2: Clock source from PLL clock,3: Clock source from 10 kHz internal low speed..,?,?,?,7: Clock source from 22.1184 MHz internalhigh.."
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "CLKSEL1,Clock Source Select Control Register 1"
|
|
bitfld.long 0x00 30.--31. "PWM23_S,PWM2 And PWM3 Clock Source Selection\nPWM2 and PWM3 used the same peripheral clock source both of them used the same prescaler" "0: Clock source from 4~24 MHz external high..,1: Clock source from 32.768 kHz external low..,2: Clock source from HCLK.\nReserved,3: Clock source from 22.1184 MHz internal high.."
|
|
bitfld.long 0x00 28.--29. "PWM01_S,PWM0 And PWM1 Clock Source Selection\nPWM0 and PWM1 used the same peripheral clock source both of them used the same prescaler" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 24.--25. "UART_S,UART Clock Source Selection" "0: Clock source from 4~24 MHz external high..,1: Clock source from PLL clock,?,3: Clock source from 22.1184 MHz internal high.."
|
|
bitfld.long 0x00 20.--22. "TMR3_S,TIMER3 Clock Source Selection" "0: Clock source from 4~24 MHz external high..,1: Clock source from 32.768 kHz external low..,2: Clock source from HCLK,3: Clock source from external trigger,?,5: Clock source from 10 kHz internal low speed..,?,7: Clock source from 22.1184 MHz internal high.."
|
|
newline
|
|
bitfld.long 0x00 16.--18. "TMR2_S,TIMER2 Clock Source Selection" "0: Clock source from external 4~24 MHz high..,1: Clock source from external 32.768 kHz low..,2: Clock source from HCLK,3: Clock source from external trigger,?,5: Clock source from internal 10 kHz low speed..,?,7: Clock source from internal 22.1184 MHz high.."
|
|
bitfld.long 0x00 12.--14. "TMR1_S,TIMER1 Clock Source Selection" "0: Clock source from 4~24 MHz external high..,1: Clock source from 32.768 kHz external low..,2: Clock source from HCLK,3: Clock source from external trigger,?,5: Clock source from 10 kHz internal low speed..,?,7: Clock source from 22.1184 MHz internal high.."
|
|
newline
|
|
bitfld.long 0x00 8.--10. "TMR0_S,TIMER0 Clock Source Selection" "0: Clock source from 4~24 MHz external high..,1: Clock source from 32.768 kHz external low..,2: Clock source from HCLK,3: Clock source from external trigger,?,5: Clock source from 10 kHz internal low speed..,?,7: Clock source from 22.1184 MHz internal high.."
|
|
bitfld.long 0x00 5. "SPI1_S,SPI1 Clock Source Selection" "0: Clock source from PLL clock,1: Clock source from HCLK"
|
|
newline
|
|
bitfld.long 0x00 4. "SPI0_S,SPI0 Clock Source Selection" "0: Clock source from PLL clock,1: Clock source from HCLK"
|
|
bitfld.long 0x00 2.--3. "ADC_S,ADC Clock Source Select" "0: Clock source from 4~24 MHz external high..,1: Clock source from PLL clock,2: Clock source from HCLK,3: Clock source from 22.1184 MHz internal high.."
|
|
newline
|
|
bitfld.long 0x00 0.--1. "WDT_S,Watchdog Timer Clock Source Select (Write Protect)\nNote: This bit is the protected bit and programming it needs to write '59h' '16h' and '88h' to address 0x5000_0100 to disable register protection" "0: Reserved,1: Clock source from 32.768 kHz external low..,2: Clock source from HCLK/2048 clock,3: Clock source from 10 kHz internal low speed.."
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "CLKDIV,Clock Divider Number Register"
|
|
hexmask.long.byte 0x00 16.--23. 1. "ADC_N,ADC Clock Divide Number From ADC Clock Source"
|
|
bitfld.long 0x00 8.--11. "UART_N,UART Clock Divide Number From UART Clock Source" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 4.--7. "USB_N,USB Clock Divide Number From PLL Clock" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "HCLK_N,HCLK Clock Divide Number From HCLK Clock Source" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "CLKSEL2,Clock Source Select Control Register 2"
|
|
bitfld.long 0x00 18. "RTC_SEL_10K,RTC Clock Source Selection" "0: Clock source from 32.768 kHz external low..,1: Clock source from 10 kHz internal low speed.."
|
|
bitfld.long 0x00 16.--17. "WWDT_S,Window Watchdog Timer Clock Source Selection" "?,?,2: Clock source from HCLK/2048 clock,3: Clock source from 10 kHz internal low speed.."
|
|
newline
|
|
bitfld.long 0x00 10. "PWM45_S_E,PWM4 And PWM5 Clock Source Selection Extend\nPWM4 and PWM5 used the same peripheral clock source both of them used the same prescaler" "0,1"
|
|
bitfld.long 0x00 9. "PWM23_S_E,PWM2 And PWM3 Clock Source Selection Extend\nPWM2 and PWM3 used the same peripheral clock source both of them used the same prescaler" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "PWM01_S_E,PWM0 And PWM1 Clock Source Selection Extend\nPWM0 and PWM1 used the same peripheral clock source both of them used the same prescaler" "0,1"
|
|
bitfld.long 0x00 4.--5. "PWM45_S,PWM4 And PWM5 Clock Source Selection\nPWM4 and PWM5 used the same peripheral clock source both of them used the same prescaler" "0: Clock source from 4~24 MHz external high..,1: Clock source from 32.768 kHz external low..,2: Clock source from HCLK.\nReserved,3: Clock source from 22.1184 MHz internal high.."
|
|
newline
|
|
bitfld.long 0x00 2.--3. "FRQDIV_S,Clock Divider Clock Source Selection" "0: Clock source from 4~24 MHz external high..,1: Clock source from 32.768 kHz external low..,2: Clock source from HCLK,3: Clock source from 22.1184 MHz internal high.."
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "PLLCON,PLL Control Register"
|
|
bitfld.long 0x00 19. "PLL_SRC,PLL Source Clock Selection" "0: PLL source clock from 4~24 MHz external high..,1: PLL source clock from 22.1184 MHz internal.."
|
|
bitfld.long 0x00 18. "OE,PLL OE (FOUT Enable) Pin Control" "0: PLL FOUT Enabled,1: PLL FOUT is fixed low"
|
|
newline
|
|
bitfld.long 0x00 17. "BP,PLL Bypass Control" "0: PLL is in Normal mode (default),1: PLL clock output is same as PLL source clock.."
|
|
bitfld.long 0x00 16. "PD,Power-Down Mode\nIf the PWR_DOWN_EN bit is set to 1 in PWRCON register the PLL will enter Power-down mode too" "0: PLL is in Normal mode,1: PLL is in Power-down mode (default)"
|
|
newline
|
|
bitfld.long 0x00 14.--15. "OUT_DV,PLL Output Divider Control Bits\nRefer to the formulas below the table" "0,1,2,3"
|
|
bitfld.long 0x00 9.--13. "IN_DV,PLL Input Divider Control Bits\nRefer to the formulas below the table" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
hexmask.long.word 0x00 0.--8. 1. "FB_DV,PLL Feedback Divider Control Bits\nRefer to the formulas below the table"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "FRQDIV,Frequency Divider Control Register"
|
|
bitfld.long 0x00 6. "CLKO_1HZ_EN,Clock Output 1Hz Enable Bit" "0: 1 Hz clock output for 32.768 kHz external low..,1: 1 Hz clock output for 32.768 kHz external low.."
|
|
bitfld.long 0x00 5. "DIVIDER1,Frequency Divider One Enable Bit" "0: Frequency divider will output clock with..,1: Frequency divider will output clock with.."
|
|
newline
|
|
bitfld.long 0x00 4. "DIVIDER_EN,Frequency Divider Enable Bit" "0: Frequency Divider function Disabled,1: Frequency Divider function Enabled"
|
|
bitfld.long 0x00 0.--3. "FSEL,Divider Output Frequency Selection Bits\nThe formula of output frequency is\nFin is the input clock frequency.\nFout is the frequency of divider output clock.\nN is the 4-bit value of FSEL[3:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
tree.end
|
|
tree "EBI"
|
|
base ad:0x50010000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "EBICON,External Bus Interface General Control Register"
|
|
bitfld.long 0x00 16.--18. "ExttALE,Expand Time of ALE\nThis field is used for control the ALE pulse width (tALE) for latch the address" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8.--10. "MCLKDIV,External Output Clock Divider" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 1. "ExtBW16,EBI Data Width 16-bit/8-bit\nThis bit defines if the data bus is 8-bit or 16-bit" "0: EBI data width is 8-bit,1: EBI data width is 16-bit"
|
|
bitfld.long 0x00 0. "ExtEN,EBI Enable\nThis bit is the functional enable bit for EBI" "0: EBI function Disabled,1: EBI function Enabled"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "EXTIME,External Bus Interface Timing Control Register"
|
|
bitfld.long 0x00 24.--27. "ExtIR2R,Idle State Cycle Between Read-Read\nWhen read action is finished and the next action is going to read idle state is inserted and nCS signal return to high if ExtIR2R is not zero" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. "ExtIW2X,Idle State Cycle After Write\nWhen write action is finished idle state is inserted and nCS signal return to high if ExtIW2X is not zero" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 8.--10. "ExttAHD,EBI Data Access Hold Time\nExttAHD defines data access hold time (tAHD)" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 3.--7. "ExttACC,EBI Data Access Time\nExttACC defines data access time (tACC)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "EBICON2,External Bus Interface General Control Register 2"
|
|
bitfld.long 0x00 2. "WAHD_OFF,Access Hold Time Disable Control When" "0: tAHD is controlled by ExttAHD when write..,1: No tAHD when write through EBI"
|
|
bitfld.long 0x00 1. "RAHD_OFF,Access Hold Time Disable Control When" "0: tAHD is controlled by ExttAHD when read..,1: No tAHD when read through EBI"
|
|
newline
|
|
bitfld.long 0x00 0. "WBUFF_EN,EBI Write Buffer Enable" "0: EBI write buffer disable,1: EBI write buffer enable"
|
|
tree.end
|
|
tree "FMC"
|
|
base ad:0x5000C000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "ISPCON,ISP Control Register"
|
|
bitfld.long 0x00 6. "ISPFF,ISP Fail Flag (Write Protect)\nThis bit is set by hardware when a triggered ISP meets any of the following conditions:\n(1) APROM writes to itself if APUEN is set to 0\n(2) LDROM writes to itself if LDUEN is set to 0\n(3) CONFIG is.." "0,1"
|
|
bitfld.long 0x00 5. "LDUEN,LDROM Update Enable Bit (Write Protect)" "0: LDROM cannot be updated,1: LDROM can be updated when chip runs in APROM"
|
|
newline
|
|
bitfld.long 0x00 4. "CFGUEN,Enable Config Update By ISP (Write Protect)" "0: ISP update config-bit Disabled,1: ISP update config-bit Enabled"
|
|
bitfld.long 0x00 3. "APUEN,APROM Update Enable Bit (Write Protect)" "0: APROM cannot be updated when chip runs in APROM,1: APROM can be updated when chip runs in APROM"
|
|
newline
|
|
bitfld.long 0x00 1. "BS,Boot Select (Write Protect )\nSet/clear this bit to select next booting from LDROM/APROM respectively" "0: Boot from APROM,1: Boot from LDROM"
|
|
bitfld.long 0x00 0. "ISPEN,ISP Enable Bit (Write Protect )\nISP function enable bit" "0: ISP function Disabled,1: ISP function Enabled"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "ISPADR,ISP Address Register"
|
|
hexmask.long 0x00 0.--31. 1. "ISPADR,ISP Address\nThe NuMicro NUC2201 series has a maximum of 32Kx32 (128 KB) embedded Flash which supports word program only"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "ISPDAT,ISP Data Register"
|
|
hexmask.long 0x00 0.--31. 1. "ISPDAT,ISP Data\nWrite data to this register before ISP program operation\nRead data from this register after ISP read operation"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "ISPCMD,ISP Command Register"
|
|
bitfld.long 0x00 0.--5. "ISPCMD,ISP Command\nISP command table is shown below" "0: ,?,?,?,4: Read Unique ID,?,?,?,?,?,?,11: Read Company ID (0xDA),?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,33: Program,34: Page Erase,?,?,?,?,?,?,?,?,?,?,?,46: Set Vector Page Re-Map,?..."
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "ISPTRG,ISP Trigger Control Register"
|
|
bitfld.long 0x00 0. "ISPGO,ISP Start Trigger (Write-Protection Bit)\nWrite 1 to start ISP operation and this bit will be cleared to 0 by hardware automatically when ISP operation is finished.\nThis bit is the protected bit It means programming this bit needs to write '59h'.." "0: ISP operation finished,1: ISP progressed"
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "DFBADR,Data Flash Base Address"
|
|
hexmask.long 0x00 0.--31. 1. "DFBADR,Data Flash Base Address\nThis register indicates Data Flash start address"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "FATCON,Flash Access Time Control Register"
|
|
bitfld.long 0x00 6. "FOMSEL1,Chip Frequency Optimization Mode Select1 (Write-protection Bit)" "0,1"
|
|
bitfld.long 0x00 4. "FOMSEL0,Chip Frequency Optimization Mode Select 0 (Write-Protection Bit)\nWhen CPU frequency is lower than 72 MHz user can modify flash access delay cycle by FOMSEL1 and FOMSEL0 to improve system performance" "0,1"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "ISPSTA,ISP Status Register"
|
|
hexmask.long.word 0x00 9.--20. 1. "VECMAP,Vector Page Mapping Address (Read Only)\nThe current flash address space 0x0000_0000~0x0000_01FF is mapping to address {VECMAP[11:0] 9'h000} ~ {VECMAP[11:0] 9'h1FF}"
|
|
bitfld.long 0x00 6. "ISPFF,ISP Fail Flag (Write-Protection Bit)\nThis bit is set by hardware when a triggered ISP meets any of the following conditions:\n(1) APROM writes to itself\n(2) LDROM writes to itself\n(3) CONFIG is erased/programmed if CFGUEN is set to 0\n(4).." "0,1"
|
|
newline
|
|
rbitfld.long 0x00 1.--2. "CBS,Chip Boot Selection (Read Only)\nThis is a mirror of CBS in CONFIG0" "0,1,2,3"
|
|
rbitfld.long 0x00 0. "ISPGO,ISP Start Trigger (Read Only)\nWrite 1 to start ISP operation and this bit will be cleared to 0 by hardware automatically when ISP operation is finished.\nNote: This bit is the same as ISPTRG bit0" "0: ISP operation finished,1: ISP operation progressed"
|
|
tree.end
|
|
tree "GCR"
|
|
base ad:0x50000000
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "PDID,Part Device Identification Number Register"
|
|
hexmask.long 0x00 0.--31. 1. "PDID,Part Device Identification Number\nThis register reflects device part number code"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "RSTSRC,System Reset Source Register"
|
|
bitfld.long 0x00 7. "RSTS_CPU,CPU Reset Flag\nThe RSTS_CPU flag Is set by hardware if software writes CPU_RST (IPRSTC1[1]) 1 To reset Cortex-M0 kernel and flash memory controller (FMC).\nNote: Write 1 to clear this bit to 0" "0: No reset from CPU,1: Cortex-M0 CPU kernel and FMC are reset by.."
|
|
bitfld.long 0x00 5. "RSTS_SYS,SYS Reset Flag\nThe RSTS_SYS flag Is set by the 'Reset Signal' from the Cortex-M0 kernel to indicate the previous reset source.\nNote: Write 1 to clear this bit to 0" "0: No reset from Cortex-M0,1: The Cortex-M0 had issued the reset signal to.."
|
|
newline
|
|
bitfld.long 0x00 4. "RSTS_BOD,Brown-Out Detector Reset Flag\nThe RSTS_BOD flag is set by the 'Reset Signal' from the Brown-Out Detector to indicate the previous reset source.\nNote: Write 1 to clear this bit to 0" "0: No reset from BOD,1: The BOD had issued the reset signal to reset.."
|
|
bitfld.long 0x00 3. "RSTS_LVR,Low Voltage Reset Flag\nThe RSTS_LVR flag is set by the 'Reset Signal' from the Low-Voltage-Reset controller to indicate the previous reset source.\nNote: Write 1 to clear this bit to 0" "0: No reset from LVR,1: The LVR controller had issued the reset.."
|
|
newline
|
|
bitfld.long 0x00 2. "RSTS_WDT,Watchdog Timer Reset Flag\nThe RSTS_WDT flag is set by the 'Reset Signal' from the watchdog timer or window watchdog timer to indicate the previous reset source.\nNote1: Write 1 to clear this bit to 0.\nNote2: Watchdog Timer register.." "0: No reset from watchdog timer or window..,1: The watchdog timer or window watchdog timer.."
|
|
bitfld.long 0x00 1. "RSTS_RESET,Reset Pin Reset Flag\nThe RSTS_RESET flag is set by the 'Reset Signal' from the nRESET Pin to indicate the previous reset source\nNote: Write 1 to clear this bit to 0" "0: No reset from nRESET pin,1: The Pin nRESET had issued the reset signal to.."
|
|
newline
|
|
bitfld.long 0x00 0. "RSTS_POR,Power-On Reset Flag\nThe RSTS_POR Flag is set by the 'Reset Signal' from the Power-On Reset (POR) vontroller or bit CHIP_RST (IPRSTC1[0]) to indicate the previous reset source\nNote: Write 1 to clear this bit to 0" "0: No reset from POR or CHIP_RST (IPRSTC1[0]),1: Power-on Reset (POR) or CHIP_RST (IPRSTC1[0]).."
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "IPRSTC1,Peripheral Reset Control Register 1"
|
|
bitfld.long 0x00 3. "EBI_RST,EBI Controller Reset (Write-protection Bit)\nSet this bit to 1 will generate a reset signal to the EBI" "0: EBI controller normal operation,1: EBI controller reset"
|
|
bitfld.long 0x00 2. "PDMA_RST,PDMA Controller Reset (Write Protect)\nSetting this bit to 1 will generate a reset signal to the PDMA" "0: PDMA controller normal operation,1: PDMA controller reset"
|
|
newline
|
|
bitfld.long 0x00 1. "CPU_RST,CPU Kernel One-Shot Reset (Write Protect)\nSetting this bit will only reset the CPU kernel and Flash Memory Controller(FMC) and this bit will automatically return 0 after the two clock cycles\nNote: This bit is the protected bit and programming.." "0: CPU normal operation,1: CPU one-shot reset"
|
|
bitfld.long 0x00 0. "CHIP_RST,CHIP One-Shot Reset (Write Protect)\nSetting this bit will reset the whole chip including CPU kernel and all peripherals and this bit will automatically return to 0 after the 2 clock cycles.\nThe CHIP_RST is the same as the POR reset all the.." "0: CHIP normal operation,1: CHIP one-shot reset"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "IPRSTC2,Peripheral Reset Control Register 2"
|
|
bitfld.long 0x00 28. "ADC_RST,ADC Controller Reset" "0: ADC controller normal operation,1: ADC controller reset"
|
|
bitfld.long 0x00 27. "USBD_RST,USB Device Controller Reset" "0: USB device controller normal operation,1: USB device controller reset"
|
|
newline
|
|
bitfld.long 0x00 21. "PWM45_RST,PWM45 Controller Reset" "0: PWM45 controller normal operation,1: PWM45 controller reset"
|
|
bitfld.long 0x00 20. "PWM03_RST,PWM03 Controller Reset" "0: PWM03 controller normal operation,1: PWM03 controller reset"
|
|
newline
|
|
bitfld.long 0x00 18. "UART2_RST,UART2 Controller Reset" "0: UART2 controller normal operation,1: UART2 controller reset"
|
|
bitfld.long 0x00 17. "UART1_RST,UART1 Controller Reset" "0: UART1 controller normal operation,1: UART1 controller reset"
|
|
newline
|
|
bitfld.long 0x00 16. "UART0_RST,UART0 Controller Reset" "0: UART0 controller normal operation,1: UART0 controller reset"
|
|
bitfld.long 0x00 13. "SPI1_RST,SPI1 Controller Reset" "0: SPI1 controller normal operation,1: SPI1 controller reset"
|
|
newline
|
|
bitfld.long 0x00 12. "SPI0_RST,SPI0 Controller Reset" "0: SPI0 controller normal operation,1: SPI0 controller reset"
|
|
bitfld.long 0x00 9. "I2C1_RST,I2C1 Controller Reset" "0: I2C1 controller normal operation,1: I2C1 controller reset"
|
|
newline
|
|
bitfld.long 0x00 8. "I2C0_RST,I2C0 Controller Reset" "0: I2C0 controller normal operation,1: I2C0 controller reset"
|
|
bitfld.long 0x00 5. "TMR3_RST,Timer3 Controller Reset" "0: Timer3 controller normal operation,1: Timer3 controller reset"
|
|
newline
|
|
bitfld.long 0x00 4. "TMR2_RST,Timer2 Controller Reset" "0: Timer2 controller normal operation,1: Timer2 controller reset"
|
|
bitfld.long 0x00 3. "TMR1_RST,Timer1 Controller Reset" "0: Timer1 controller normal operation,1: Timer1 controller reset"
|
|
newline
|
|
bitfld.long 0x00 2. "TMR0_RST,Timer0 Controller Reset" "0: Timer0 controller normal operation,1: Timer0 controller reset"
|
|
bitfld.long 0x00 1. "GPIO_RST,GPIO Controller Reset" "0: GPIO controller normal operation,1: GPIO controller reset"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "BODCR,Brown-out Detector Control Register"
|
|
bitfld.long 0x00 7. "LVR_EN,Low Voltage Reset Enable Bit (Write Protect)\nThe LVR function reset the chip when the input power voltage is lower than LVR circuit setting" "0: Low Voltage Reset function Disabled,1: Low Voltage Reset function Enabled - After.."
|
|
bitfld.long 0x00 6. "BOD_OUT,Brown-Out Detector Output Status" "0: Brown-out Detector output status is 0,1: Brown-out Detector output status is 1"
|
|
newline
|
|
bitfld.long 0x00 5. "BOD_LPM,Brown-Out Detector Low Power Mode (Write Protect)\nNote1: The BOD consumes about 100 uA in Normal mode and the low power mode can reduce the current to about 1/10 but slow the BOD response.\nNote2: This bit is the protected bit and programming.." "0: BOD operated in Normal mode (default),1: BOD Low Power mode Enabled"
|
|
bitfld.long 0x00 4. "BOD_INTF,Brown-Out Detector Interrupt Flag\nNote: Write 1 to clear this bit to 0" "0: Brown-out Detector does not detect any..,1: When Brown-out Detector detects the VDD is.."
|
|
newline
|
|
bitfld.long 0x00 3. "BOD_RSTEN,Brown-Out Reset Enable Bit (Write Protect)\nWhile the Brown-out Detector function is enabled (BOD_EN high) and BOD reset function is enabled (BOD_RSTEN high) BOD will assert a signal to reset chip when the detected voltage is lower than the.." "0: Brown-out 'INTERRUPT' function Enabled,1: Brown-out 'RESET' function Enabled"
|
|
bitfld.long 0x00 1.--2. "BOD_VL,Brown-Out Detector Threshold Voltage Selection (Write Protect)\nThe default value is set by flash momory controller user configuration register CBOV(CONFIG0[22:21]) bit .\nNote: This bit is the protected bit" "0: Brown-out voltage is 2.2V,1: Brown-out voltage is 2.7V,2: Brown-out voltage is 3.7V,3: Brown-out voltage is 4.4V"
|
|
newline
|
|
bitfld.long 0x00 0. "BOD_EN,Brown-Out Detector Enable Bit (Write Protect)\nThe default value is set by flash memory controller user configuration register CBODEN(CONFIG0[23]) bit.\nNote: This bit is the protected bit" "0: Brown-out Detector function Disabled,1: Brown-out Detector function Enabled"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "TEMPCR,Temperature Sensor Control Register"
|
|
bitfld.long 0x00 0. "VTEMP_EN,Temperature Sensor Enable Bit\nThis bit is used to enable/disable temperature sensor function.\nNote: After this bit is set to 1 the value of temperature can be obtained from ADC conversion result by ADC channel selecting channel 7 and.." "0: Temperature sensor function Disabled (default),1: Temperature sensor function Enabled"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "PORCR,Power-on-reset Controller Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "POR_DIS_CODE,Power-On-Reset Enable Bit (Write Protect)\nWhen powered on the POR circuit generates a reset signal to reset the whole chip function but noise on the power may cause the POR active again"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "GPA_MFP,GPIOA Multiple Function and Input Type Control Register"
|
|
hexmask.long.word 0x00 16.--31. 1. "GPA_TYPEn,Trigger Function Selection"
|
|
bitfld.long 0x00 15. "GPA_MFP15,PA.15 Pin Function Selection" "0: GPIOA function is selected,1: PWM3 function is selected"
|
|
newline
|
|
bitfld.long 0x00 14. "GPA_MFP14,PA.14 Pin Function Selection\nBits EBI_HB_EN[7] (ALT_MFP[23]) EBI_EN (ALT_MFP[11]) and GPA_MFP[14] determine the PA.14 function.\n(EBI_HB_EN EBI_EN GPA_MFP14) value and function mapping is as following list" "0,1"
|
|
bitfld.long 0x00 13. "GPA_MFP13,PA.13 Pin Function Selection\nBits EBI_HB_EN[6] (ALT_MFP[22]) EBI_EN (ALT_MFP[11]) and GPA_MFP[13] determine the PA.13 function.\n(EBI_HB_EN EBI_EN GPA_MFP13) value and function mapping is as following list" "0,1"
|
|
newline
|
|
bitfld.long 0x00 12. "GPA_MFP12,PA.12 Pin Function Selection\nBits EBI_HB_EN[5] (ALT_MFP[21]) EBI_EN (ALT_MFP[11]) and GPA_MFP[12] determine the PA.12 function.\n(EBI_HB_EN EBI_EN GPA_MFP12) value and function mapping is as following list" "0,1"
|
|
bitfld.long 0x00 11. "GPA_MFP11,PA.11 Pin Function Selection\nBits EBI_EN (ALT_MFP[11]) and GPA_MFP[11] determine the PA.11 function.\n(EBI_EN GPA_MFP11) value and function mapping is as following list" "0,1"
|
|
newline
|
|
bitfld.long 0x00 10. "GPA_MFP10,PA.10 Pin Function Selection\nBits EBI_EN (ALT_MFP[11]) and GPA_MFP[10] determine the PA.10 function.\n(EBI_EN GPA_MFP10) value and function mapping is as following list" "0,1"
|
|
bitfld.long 0x00 9. "GPA_MFP9,PA.9 Pin Function Selection\nBit GPA_MFP[9] determines the PA.9 function" "0: GPIO function is selected,1: I2C0_SCL function is selected"
|
|
newline
|
|
bitfld.long 0x00 8. "GPA_MFP8,PA.8 Pin Function Selection\nBit GPA_MFP[8] determines the PA.9 function" "0: GPIO function is selected to the pin PA.8,1: I2C0_SDA function is selected to the pin PA.8"
|
|
bitfld.long 0x00 7. "GPA_MFP7,Reserved" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "GPA_MFP6,PA.6 Pin Function Selection\nBits EBI_EN (ALT_MFP[11]) and GPA_MFP[6] determine the PA.6 function.\n(EBI_EN GPA_MFP6) value and function mapping is as following list" "0,1"
|
|
bitfld.long 0x00 5. "GPA_MFP5,PA.5 Pin Function Selection\nBits EBI_HB_EN[0] (ALT_MFP[16]) EBI_EN (ALT_MFP[11]) and GPA_MFP[5] determine the PA.5 function.\n(EBI_HB_EN EBI_EN GPA_MFP5) value and function mapping is as following list" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "GPA_MFP4,PA.4 Pin Function Selection\nBits EBI_HB_EN[1] (ALT_MFP[17]) EBI_EN (ALT_MFP[11]) and GPA_MFP[4] determine the PA.4 function.\n(EBI_HB_EN EBI_EN GPA_MFP4) value and function mapping is as following list" "0,1"
|
|
bitfld.long 0x00 3. "GPA_MFP3,PA.3 Pin Function Selection\nBits EBI_HB_EN[2] (ALT_MFP[18]) EBI_EN (ALT_MFP[11]) and GPA_MFP[3] determine the PA.3 function.\n(EBI_HB_EN EBI_EN GPA_MFP3) value and function mapping is as following list" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "GPA_MFP2,PA.2 Pin Function Selection\nBits EBI_HB_EN[3] (ALT_MFP[19]) EBI_EN (ALT_MFP[11]) and GPA_MFP[2] determine the PA.2 function.\n(EBI_HB_EN EBI_EN GPA_MFP2) value and function mapping is as following list" "0,1"
|
|
bitfld.long 0x00 1. "GPA_MFP1,PA.1 Pin Function Selection\nBit EBI_HB_EN[4] (ALT_MFP[20]) EBI_EN (ALT_MFP[11]) and GPA_MFP[1] determine the PA.1 function.\n(EBI_HB_EN EBI_EN GPA_MFP1) value and function mapping is as following list" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "GPA_MFP0,PA.0 Pin Function Selection" "0: GPIO function is selected,1: ADC0 function is selected"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "GPB_MFP,GPIOB Multiple Function and Input Type Control Register"
|
|
hexmask.long.word 0x00 16.--31. 1. "GPB_TYPEn,Trigger Function Selection"
|
|
bitfld.long 0x00 15. "GPB_MFP15,PB.15 Pin Function Selection\nBits PB14_15_EBI (ALT_MFP2[1]) PB15_T0EX (ALT_MFP[24]) PB15_TM0 (ALT_MFP2[2]) and GPB_MFP[15] determine the PB.15 function.\n(PB14_15_EBI PB15_T0EX PB15_TM0 GPB_MFP15) value and function mapping is as following list" "0,1"
|
|
newline
|
|
bitfld.long 0x00 14. "GPB_MFP14,PB.14 Pin Function Selection\nBits PB14_15_EBI (ALT_MFP2[1]) and GPB_MFP[14] determine the PB.14 function.\n(PB14_15_EBI GPB_MFP14) value and function mapping is as following list" "0,1"
|
|
bitfld.long 0x00 13. "GPB_MFP13,PB.13 Pin Function Selection" "0: GPIO function is selected to the pin PB.13,1: AD1 function is selected"
|
|
newline
|
|
bitfld.long 0x00 12. "GPB_MFP12,Reserved" "0,1"
|
|
bitfld.long 0x00 11. "GPB_MFP11,PB.11 Pin Function Selection\nBits PB11_PWM4 (ALT_MFP[4]) and GPB_MFP[11] determine the PB.11 function.\n(PB11_PWM4 GPB_MFP11) value and function mapping is as following list" "0,1"
|
|
newline
|
|
bitfld.long 0x00 10. "GPB_MFP10,PB.10 Pin Function Selection\nBits PB10_S01 (ALT_MFP[0]) and GPB_MFP[10] determine the PB.10 function.\n(PB10_S01 GPB_MFP10) value and function mapping is as following list" "0,1"
|
|
bitfld.long 0x00 9. "GPB_MFP9,PB.9 Pin Function Selection\nBits PB9_S11 (ALT_MFP[1]) and GPB_MFP[9] determine the PB.9 function.\n(PB9_S11 GPB_MFP9) value and function mapping is as following list" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "GPB_MFP8,PB.8 Pin Function Selection\nBits PB8_CLKO (ALT_MFP[29]) and GPB_MFP[8] determine the PB.8 function.\n(PB8_CLKO GPB_MFP8) value and function mapping is as following list" "0,1"
|
|
bitfld.long 0x00 7. "GPB_MFP7,PB.7 Pin Function Selection\nBit EBI_EN (ALT_MFP[11]) GPB_MFP[7] determines the PB.7 function.\n(EBI_EN GPB_MFP7) value and function mapping is as following list" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "GPB_MFP6,PB.6 Pin Function Selection\nBit EBI_EN (ALT_MFP[11]) GPB_MFP[6] determines the PB.6 function.\n(EBI_EN GPB_MFP6) value and function mapping is as following list" "0,1"
|
|
bitfld.long 0x00 5. "GPB_MFP5,PB 5 Pin Function Selection\nBit GPB_MFP[5] determines the PB.5 function" "0: GPIO function is selected to the pin PB.5,1: UART1_TXD function is selected to the pin PB.5"
|
|
newline
|
|
bitfld.long 0x00 4. "GPB_MFP4,PB.4 Pin Function Selection\nBit GPB_MFP[4] determines the PB.4 function" "0: GPIO function is selected to the pin PB.4,1: UART1_RXD function is selected to the pin PB.4"
|
|
bitfld.long 0x00 3. "GPB_MFP3,PB.3 Pin Function Selection\nBits EBI_nWRH_EN (ALT_MFP[14]) EBI_EN (ALT_MFP[11]) PB3_TM3 (ALT_MFP2[5]) PB3_T3EX (ALT_MFP[27]) and GPB_MFP[3] determine the PB.3 function.\n(EBI_nWRH_EN EBI_EN PB3_TM3 PB3_T3EX GPB_MFP3) value and function mapping.." "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "GPB_MFP2,PB.2 Pin Function Selection\nBits EBI_nWRL_EN (ALT_MFP[13]) EBI_EN (ALT_MFP[11]) PB2_TM2 (ALT_MFP2[4]) PB2_T2EX (ALT_MFP[26]) and GPB_MFP[2] determine the PB.2 function.\n(EBI_nWRL_EN EBI_EN PB2_TM2 PB2_T2EX GPB_MFP2) value and function mapping.." "0,1"
|
|
bitfld.long 0x00 1. "GPB_MFP1,PB.1 Pin Function Selection\nBit GPB_MFP[1] determines the PB.1 function" "0: GPIO function is selected to the pin PB.1,1: UART0_TXD function is selected to the pin PB.1"
|
|
newline
|
|
bitfld.long 0x00 0. "GPB_MFP0,PB.0 Pin Function Selection\nBit GPB_MFP[0] determines the PB.0 function" "0: GPIO function is selected to the pin PB.0,1: UART0_RXD function is selected to the pin PB.0"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "GPC_MFP,GPIOC Multiple Function and Input Type Control Register"
|
|
hexmask.long.word 0x00 16.--31. 1. "GPC_TYPEn,Trigger Function Selection"
|
|
bitfld.long 0x00 15. "GPC_MFP15,PC.15 Pin Function Selection\nBits EBI_EN (ALT_MFP[11]) and GPC_MFP[15] determine the PC.15 function.\n(EBI_EN GPC_MFP15) value and function mapping is as following list" "0,1"
|
|
newline
|
|
bitfld.long 0x00 14. "GPC_MFP14,PC.14 Pin Function Selection\nBits EBI_EN (ALT_MFP[11]) and GPC_MFP[14] determine the PC.14 function.\n(EBI_EN GPC_MFP14) value and function mapping is as following list" "0,1"
|
|
bitfld.long 0x00 13. "GPC_MFP13,Reserved" "0,1"
|
|
newline
|
|
bitfld.long 0x00 12. "GPC_MFP12,Reserved" "0,1"
|
|
bitfld.long 0x00 11. "GPC_MFP11,PC.11 Pin Function Selection\nBit GPC_MFP[11] determines the PC.11 function" "0: GPIO function is selected to the pin PC.11,1: SPI1_MOSI0 function is selected to the pin.."
|
|
newline
|
|
bitfld.long 0x00 10. "GPC_MFP10,PC.10 Pin Function Selection\nBit GPC_MFP[10] determines the PC.10 function" "0: GPIO function is selected to the pin PC.10,1: SPI1_MISO0 function is selected to the pin.."
|
|
bitfld.long 0x00 9. "GPC_MFP9,PC.9 Pin Function Selection\nBit GPC_MFP[9] determines the PC.9 function" "0: GPIO function is selected to the pin PC.9,1: SPI1_CLK function is selected to the pin PC.9"
|
|
newline
|
|
bitfld.long 0x00 8. "GPC_MFP8,PC.8 Pin Function Selection\nBits EBI_MCLK_EN (ALT_MFP[12]) EBI_EN (ALT_MFP[11]) GPC_MFP[8] determine the PC.8 function.\n(EBI_MCLK_EN EBI_EN GPC_MFP8) value and function mapping is as following list" "0,1"
|
|
bitfld.long 0x00 7. "GPC_MFP7,PC.7 Pin Function Selection\nBits EBI_EN (ALT_MFP[11]) and GPC_MFP[7] determine the PC.7 function.\n(EBI_EN GPC_MFP7) value and function mapping is as following list" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "GPC_MFP6,PC.6 Pin Function Selection\nBits EBI_EN (ALT_MFP[11]) and GPC_MFP[6] determine the PC.6 function.\n(EBI_EN GPB_MFP6) value and function mapping is as following list" "0,1"
|
|
bitfld.long 0x00 5. "GPC_MFP5,Reserved" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "GPC_MFP4,Reserved" "0,1"
|
|
bitfld.long 0x00 3. "GPC_MFP3,PC.3 Pin Function Selection" "0: GPIO function is selected,1: SPI0_MOSI0 function is selected"
|
|
newline
|
|
bitfld.long 0x00 2. "GPC_MFP2,PC.2 Pin Function Selection" "0: GPIO function is selected,1: SPI0_MISO0 function is selected"
|
|
bitfld.long 0x00 1. "GPC_MFP1,PC.1 Pin Function Selection" "0: GPIO function is selected,1: SPI0_CLK function is selected"
|
|
newline
|
|
bitfld.long 0x00 0. "GPC_MFP0,PC.0 Pin Function Selection" "0: GPIO function is selected,1: SPI0_SS0 function is selected"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "GPE_MFP,GPIOE Multiple Function and Input Type Control Register"
|
|
hexmask.long.word 0x00 16.--31. 1. "GPE_TYPEn,Trigger Function Selection"
|
|
bitfld.long 0x00 5. "GPE_MFP5,PE.5 Pin Function Selection\nBits PE5_T1EX (ALT_MFP[25]) PE5_TM1 (ALT_MFP2[3]) and GPE_MFP5 determine the PE.5 function.\n(PE5_T1EX PE5_TM1 GPE_MFP5) value and function mapping is as following list" "0,1"
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "GPF_MFP,GPIOF Multiple Function and Input Type Control Register"
|
|
bitfld.long 0x00 16.--19. "GPF_TYPEn,Trigger Function Selection" "0: GPIOF[3:0] I/O input Schmitt Trigger function..,1: GPIOF[3:0] I/O input Schmitt Trigger function..,?..."
|
|
bitfld.long 0x00 1. "GPF_MFP1,PF.1 Pin Function Selection \nBit GPF_MFP[1] determines the PF.1 function.\nNote: This bit is read only and is decided by user configuration CGPFMFP (CONFIG0[27])" "0: GPIO function is selected to the pin PF.1,1: XT1_IN function is selected to the pin PF.1"
|
|
newline
|
|
bitfld.long 0x00 0. "GPF_MFP0,PF.0 Pin Function Selection\nBit GPF_MFP[0] determines the PF.0 function\nNote: This bit is read only and is decided by user configuration CGPFMFP (CONFIG0[27])" "0: GPIO function is selected to the pin PF.0,1: XT1_OUT function is selected to the pin PF.0"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "ALT_MFP,Alternative Multiple Function Pin Control Register"
|
|
bitfld.long 0x00 29. "PB8_CLKO,PB.8 Pin Alternative Function Selection\nBits PB8_CLKO (ALT_MFP[29]) and GPB_MFP[8] determine the PB.8 function.\n(PB8_CLKO GPB_MFP8) value and function mapping is as following list" "0,1"
|
|
bitfld.long 0x00 27. "PB3_T3EX,PB.3 Pin Alternative Function Selection\nBits EBI_nWRH_EN (ALT_MFP[14]) EBI_EN (ALT_MFP[11]) PB3_TM3 (ALT_MFP2[5]) PB3_T3EX (ALT_MFP[27]) and GPB_MFP[3] determine the PB.3 function.\n(EBI_nWRH_EN EBI_EN PB3_TM3 PB3_T3EX GPB_MFP3) value and.." "0,1"
|
|
newline
|
|
bitfld.long 0x00 26. "PB2_T2EX,PB.2 Pin Alternative Function Selection\nBits EBI_nWRL_EN (ALT_MFP[13]) EBI_EN (ALT_MFP[11]) PB2_TM2 (ALT_MFP2[4]) PB2_T2EX (ALT_MFP[26]) and GPB_MFP[2] determine the PB.2 function.\n(EBI_nWRL_EN EBI_EN PB2_TM2 PB2_T2EX GPB_MFP2) value and.." "0,1"
|
|
bitfld.long 0x00 25. "PE5_T1EX,PE.5 Pin Alternative Function Selection\nBits PE5_T1EX (ALT_MFP[25]) PE5_TM1 (ALT_MFP2[3]) and GPE_MFP5 determine the PE.5 function.\n(PE5_T1EX PE5_TM1 GPE_MFP5) value and function mapping is as following list" "0,1"
|
|
newline
|
|
bitfld.long 0x00 24. "PB15_T0EX,PB.15 Pin Alternative Function Selection\nBits PB14_15_EBI (ALT_MFP2[1]) PB15_T0EX (ALT_MFP[24]) PB15_TM0 (ALT_MFP2[2]) and GPB_MFP[15] determine the PB.15 function.\n(PB14_15_EBI PB15_T0EX PB15_TM0 GPB_MFP15) value and function mapping is as.." "0,1"
|
|
bitfld.long 0x00 23. "EBI_HB_EN7,Bits EBI_HB_EN[7] (ALT_MFP[23]) EBI_EN (ALT_MFP[11]) and GPA_MFP[14] determine the PA.14 function.\n(EBI_HB_EN EBI_EN GPA_MFP14) value and function mapping is as following list" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "EBI_HB_EN6,Bits EBI_HB_EN[6] (ALT_MFP[22]) EBI_EN (ALT_MFP[11]) and GPA_MFP[13] determine the PA.13 function.\n(EBI_HB_EN EBI_EN GPA_MFP13) value and function mapping is as following list" "0,1"
|
|
bitfld.long 0x00 21. "EBI_HB_EN5,Bits EBI_HB_EN[5] (ALT_MFP[21]) EBI_EN (ALT_MFP[11]) and GPA_MFP[12] determine the PA.12 function.\n(EBI_HB_EN EBI_EN GPA_MFP12) value and function mapping is as following list" "0,1"
|
|
newline
|
|
bitfld.long 0x00 20. "EBI_HB_EN4,Bit EBI_HB_EN[4] (ALT_MFP[20]) EBI_EN (ALT_MFP[11]) and GPA_MFP[1] determine the PA.1 function.\n(EBI_HB_EN EBI_EN GPA_MFP1) value and function mapping is as following list" "0,1"
|
|
bitfld.long 0x00 19. "EBI_HB_EN3,Bits EBI_HB_EN[3] (ALT_MFP[19]) EBI_EN (ALT_MFP[11]) and GPA_MFP[2] determine the PA.2 function.\n(EBI_HB_EN EBI_EN GPA_MFP2) value and function mapping is as following list" "0,1"
|
|
newline
|
|
bitfld.long 0x00 18. "EBI_HB_EN2,Bits EBI_HB_EN[2] (ALT_MFP[18]) EBI_EN (ALT_MFP[11]) and GPA_MFP[3] determine the PA.3 function.\n(EBI_HB_EN EBI_EN GPA_MFP3) value and function mapping is as following list" "0,1"
|
|
bitfld.long 0x00 17. "EBI_HB_EN1,Bits EBI_HB_EN[1] (ALT_MFP[17]) EBI_EN (ALT_MFP[11]) and GPA_MFP[4] determine the PA.4 function.\n(EBI_HB_EN EBI_EN GPA_MFP4) value and function mapping is as following list" "0,1"
|
|
newline
|
|
bitfld.long 0x00 16. "EBI_HB_EN0,Bits EBI_HB_EN[0] (ALT_MFP[16]) EBI_EN (ALT_MFP[11]) and GPA_MFP[5] determine the PA.5 function.\n(EBI_HB_EN EBI_EN GPA_MFP5) value and function mapping is as following list" "0,1"
|
|
bitfld.long 0x00 14. "EBI_nWRH_EN,Bits EBI_nWRH_EN (ALT_MFP[14]) EBI_EN (ALT_MFP[11]) PB3_TM3 (ALT_MFP2[5]) PB3_T3EX (ALT_MFP[27]) and GPB_MFP[3] determine the PB.3 function.\n(EBI_nWRH_EN EBI_EN PB3_TM3 PB3_T3EX GPB_MFP3) value and function mapping is as following list" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "EBI_nWRL_EN,Bits EBI_nWRL_EN (ALT_MFP[13]) EBI_EN (ALT_MFP[11]) PB2_TM2 (ALT_MFP2[4]) PB2_T2EX (ALT_MFP[26]) and GPB_MFP[2] determine the PB.2 function.\n(EBI_nWRL_EN EBI_EN PB2_TM2 PB2_T2EX GPB_MFP2) value and function mapping is as following list" "0,1"
|
|
bitfld.long 0x00 12. "EBI_MCLK_EN,Bits EBI_MCLK_EN (ALT_MFP[12]) EBI_EN (ALT_MFP[11]) GPC_MFP[8] determine the PC.8 function.\n(EBI_MCLK_EN EBI_EN GPC_MFP8) value and function mapping is as following list" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. "EBI_EN,EBI_EN is use to switch GPIO function to EBI function (AD[15:0] ALE RE WE CS MCLK) it need additional registers EBI_EN[7:0] and EBI_MCLK_EN for some GPIO to switch to EBI function(AD[15:8] MCLK)" "0,1"
|
|
bitfld.long 0x00 4. "PB11_PWM4,PB.11 Pin Alternative Function Selection\nBits PB11_PWM4 (ALT_MFP[4]) and GPB_MFP[11] determine the PB.11 function.\n(PB11_PWM4 GPB_MFP11) value and function mapping is as following list" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "PB14_S31,PB.14 Pin Alternative Function Selection\nBits PB14_15_EBI (ALT_MFP2[1]) and GPB_MFP[14] determine the PB.14 function.\n(PB14_15_EBI GPB_MFP14) value and function mapping is as following list" "0,1"
|
|
bitfld.long 0x00 1. "PB9_S11,PB.9 Pin Alternative Function Selection\nBits PB9_S11 (ALT_MFP[1]) and GPB_MFP[9] determine the PB.9 function.\n(PB9_S11 GPB_MFP9) value and function mapping is as following list" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "PB10_S01,PB.10 Pin Alternative Function Selection\nBits PB10_S01 (ALT_MFP[0]) and GPB_MFP[10] determine the PB.10 function.\n(PB10_S01 GPB_MFP10) value and function mapping is as following list" "0,1"
|
|
group.long 0x5C++0x03
|
|
line.long 0x00 "ALT_MFP2,Alternative Multiple Function Pin Control Register 2"
|
|
bitfld.long 0x00 5. "PB3_TM3,PB.3 Pin Alternative Function Selection\nBits EBI_nWRH_EN (ALT_MFP[14]) EBI_EN (ALT_MFP[11]) PB3_TM3 (ALT_MFP2[5]) PB3_T3EX (ALT_MFP[27]) and GPB_MFP[3] determine the PB.3 function.\n(EBI_nWRH_EN EBI_EN PB3_TM3 PB3_T3EX GPB_MFP3) value and.." "0,1"
|
|
bitfld.long 0x00 4. "PB2_TM2,PB.2 Pin Alternative Function Selection\nBits EBI_nWRL_EN (ALT_MFP[13]) EBI_EN (ALT_MFP[11]) PB2_TM2 (ALT_MFP2[4]) PB2_T2EX (ALT_MFP[26]) and GPB_MFP[2] determine the PB.2 function.\n(EBI_nWRL_EN EBI_EN PB2_TM2 PB2_T2EX GPB_MFP2) value and.." "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "PE5_TM1,PE.5 Pin Alternative Function Selection\nBits PE5_T1EX (ALT_MFP[25]) PE5_TM1 (ALT_MFP2[3]) and GPE_MFP5 determine the PE.5 function.\n(PE5_T1EX PE5_TM1 GPE_MFP5) value and function mapping is as following list" "0,1"
|
|
bitfld.long 0x00 2. "PB15_TM0,PB.15 Pin Alternative Function Selection\nBits PB14_15_EBI (ALT_MFP2[1]) PB15_T0EX (ALT_MFP[24]) PB15_TM0 (ALT_MFP2[2]) and GPB_MFP[15] determine the PB.15 function.\n(PB14_15_EBI PB15_T0EX PB15_TM0 GPB_MFP15) value and function mapping is as.." "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "PB14_15_EBI,PB .14 and PB.15 Pin Alternative Function Selection\nBits PB14_15_EBI (ALT_MFP2[1]) PB15_T0EX (ALT_MFP[24]) PB15_TM0 (ALT_MFP2[2]) and GPB_MFP[15] determine the PB.15 function.\n(PB14_15_EBI PB15_T0EX PB15_TM0 GPB_MFP15) value and function.." "0,1"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "IRCTCTL,IRC Trim Control Register"
|
|
bitfld.long 0x00 8. "CLKERR_STOP_EN,Clock Error Stop Enable Bit" "0: The trim operation is kept going if clock is..,1: The trim operation is stopped if clock is.."
|
|
bitfld.long 0x00 6.--7. "TRIM_RETRY_CNT,Trim Value Update Limitation Count\nThe field defines that how many times of HIRC trim value is updated by auto trim circuit before the HIRC frequency locked.\nOnce the HIRC locked the internal trim value update counter will be reset.\nIf.." "0: Trim retry count limitation is 64,1: Trim retry count limitation is 128,2: Trim retry count limitation is 256,3: Trim retry count limitation is 512"
|
|
newline
|
|
bitfld.long 0x00 4.--5. "TRIM_LOOP,Trim Calculation Loop\nThis field defines that trim value calculation is based on how many 32.768 kHz clocks in.\nFor example if TRIM_LOOP is set as 00 auto trim circuit will calculate trim value based on the average frequency difference in 4.." "0: Trim value calculation is based on average..,1: Trim value calculation is based on average..,2: Trim value calculation is based on average..,3: Trim value calculation is based on average.."
|
|
bitfld.long 0x00 0.--1. "TRIM_SEL,Trim Frequency Selection\nThis field indicates the target frequency of internal 22.1184 MHz high speed oscillator will trim to precise 22.1184MHz or 24MHz automatically.\nIf no any target frequency is selected (TRIM_SEL is 00) the HIRC auto.." "0: HIRC auto trim function Disabled,1: HIRC auto trim function Enabled and HIRC..,2: HIRC auto trim function Enabled and HIRC..,3: Reserved"
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "IRCTIEN,IRC Trim Interrupt Enable Register"
|
|
bitfld.long 0x00 2. "CLKERR_IEN,Clock Error Interrupt Enable Bit\nThis bit controls if CPU would get an interrupt while clock is inaccuracy during auto trim operation.\nIf this bit is set to1 and CLKERR_INT (IRCTRIMINT[2]) is set during auto trim operation" "0: CLKERR_INT (IRCTRIMINT[2]) status to trigger..,1: CLKERR_INT (IRCTRIMINT[2]) status to trigger.."
|
|
bitfld.long 0x00 1. "TRIM_FAIL_IEN,Trim Failure Interrupt Enable Bit\nThis bit controls if an interrupt will be triggered while HIRC trim value update limitation count reached and HIRC frequency still not locked on target frequency set by TRIM_SEL (IRCTCTL[1:0]).\nIf this.." "0: TRIM_FAIL_INT (IRCTRIMINT[1]) status to..,1: TRIM_FAIL_INT (IRCTRIMINT[1]) status to.."
|
|
group.long 0x88++0x03
|
|
line.long 0x00 "IRCTSTS,IRC Trim Interrupt Status Register"
|
|
bitfld.long 0x00 2. "CLKERR_INT,Clock Error Interrupt Status\nWhen the frequency of external 32.768 kHz low speed crystal or internal 22.1184 MHz high speed oscillator is shift larger to unreasonable value this bit will be set and to be an indicate that clock frequency is.." "0: Clock frequency is accurate,1: Clock frequency is inaccurate"
|
|
bitfld.long 0x00 1. "TRIM_FAIL_INT,Trim Failure Interrupt Status\nThis bit indicates that internal 22.1184 MHz high speed oscillator trim value update limitation count reached and the internal 22.1184 MHz high speed oscillator clock frequency still doesn't be locked" "0: Trim value update limitation count did not..,1: Trim value update limitation count reached.."
|
|
newline
|
|
bitfld.long 0x00 0. "FREQ_LOCK,HIRC Frequency Lock Status\nThis bit indicates the internal 22.1184 MHz high speed oscillator frequency is locked.\nThis is a status bit and doesn't trigger any interrupt" "0,1"
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "HIRCTCTL,HIRC Trim Control Register"
|
|
bitfld.long 0x00 16.--20. "BOUNDARY,Boundary Selection\nFill the boundary range from 1 to 31 0 is reserved.\nNote: This field is effective only when the BOUNDEN(SYS_HIRCTCTL[9]) is enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 9. "BOUNDEN,Boundary Enable" "0: Boundary function is disable,1: Boundary function is enable"
|
|
newline
|
|
bitfld.long 0x00 8. "CESTOPEN,Clock Error Stop Enable Bit" "0: The trim operation is keep going if clock is..,1: The trim operation is stopped if clock is.."
|
|
bitfld.long 0x00 6.--7. "RETRYCNT,Trim Value Update Limitation Count\nThis field defines that how many times the auto trim circuit will try to update the HIRC trim value before the frequency of HIRC locked.\nOnce the HIRC locked the internal trim value update counter will be.." "0: Trim retry count limitation is 64 loops,1: Trim retry count limitation is 128 loops,2: Trim retry count limitation is 256 loops,3: Trim retry count limitation is 512 loops"
|
|
newline
|
|
bitfld.long 0x00 4.--5. "LOOPSEL,Trim Calculation Loop Selection\nThis field defines that trim value calculation is based on how many reference clocks.\nNote: For example if LOOPSEL is set as 00 auto trim circuit will calculate trim value based on the average frequency.." "0: Trim value calculation is based on average..,1: Trim value calculation is based on average..,2: Trim value calculation is based on average..,3: Trim value calculation is based on average.."
|
|
bitfld.long 0x00 0.--1. "FREQSEL,Trim Frequency Selection\nThis field indicates the target frequency of 48 MHz internal high speed RC oscillator (HIRC) auto trim.\nDuring auto trim operation if clock error detected with CESTOPEN is set to 1 or trim retry limitation count.." "0: Disable HIRC auto trim function,1: Enable HIRC auto trim function and trim HIRC..,2: Reserved,3: Reserved"
|
|
group.long 0x94++0x03
|
|
line.long 0x00 "HIRCTIEN,HIRC Trim Interrupt Enable Register"
|
|
bitfld.long 0x00 2. "CLKEIEN,Clock Error Interrupt Enable Bit\nThis bit controls if CPU would get an interrupt while clock is inaccuracy during auto trim operation.\nIf this bit is set to1 and CLKERRIF(SYS_HIRCTSTS[2]) is set during auto trim operation an interrupt will be.." "0: Disable CLKERRIF(SYS_HIRCTSTS[2]) status to..,1: Enable CLKERRIF(SYS_HIRCTSTS[2]) status to.."
|
|
bitfld.long 0x00 1. "TFALIEN,Trim Failure Interrupt Enable Bit\nThis bit controls if an interrupt will be triggered while HIRC trim value update limitation count reached and HIRC frequency still not locked on target frequency set by FREQSEL(SYS_HIRCTCTL[1:0]).\nIf this bit.." "0: Disable TFAILIF(SYS_HIRCTSTS[1]) status to..,1: Enable TFAILIF(SYS_HIRCTSTS[1]) status to.."
|
|
group.long 0x98++0x03
|
|
line.long 0x00 "HIRCTSTS,HIRC Trim Interrupt Status Register"
|
|
bitfld.long 0x00 3. "OVBDIF,Over Boundary Status\nWhen the over boundary function is set if there occurs the over boundary condition this flag will be set.\nNote: Write 1 to clear this flag" "0: Over boundary coundition did not occur,1: Over boundary coundition occurred"
|
|
bitfld.long 0x00 2. "CLKERIF,Clock Error Interrupt Status\nWhen the reference clock or 48MHz internal high speed RC oscillator (HIRC) is shift larger to unreasonable value this bit will be set and to be an indicate that clock frequency is inaccuracy\nOnce this bit is set to.." "0: Clock frequency is accuracy,1: Clock frequency is inaccuracy"
|
|
newline
|
|
bitfld.long 0x00 1. "TFAILIF,Trim Failure Interrupt Status\nThis bit indicates that HIRC trim value update limitation count reached and the HIRC clock frequency still doesn't be locked" "0: Trim value update limitation count does not..,1: Trim value update limitation count reached.."
|
|
bitfld.long 0x00 0. "FREQLOCK,HIRC Frequency Lock Status\nThis bit indicates the HIRC frequency is locked.\nThis is a status bit and doesn't trigger any interrupt\nWrite 1 to clear this to 0" "0: The internal high-speed oscillator frequency..,1: The internal high-speed oscillator frequency.."
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "REGWRPROT,Register Write Protection Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. "REGWRPROT,Register Write-Protection Code (Write Only)\nSome registers have write-protection function"
|
|
tree.end
|
|
tree "GPIO"
|
|
base ad:0x50004000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "GPIOA_PMD,GPIO Port A Pin I/O Mode Control Register"
|
|
bitfld.long 0x00 30.--31. "PMD15,GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nNote3: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored" "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,2: GPIO port [n] pin is in Open-drain Output mode,3: GPIO port [n] pin is in Quasi-bidirectional.."
|
|
bitfld.long 0x00 28.--29. "PMD14,GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nNote3: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored" "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,2: GPIO port [n] pin is in Open-drain Output mode,3: GPIO port [n] pin is in Quasi-bidirectional.."
|
|
newline
|
|
bitfld.long 0x00 26.--27. "PMD13,GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nNote3: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored" "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,2: GPIO port [n] pin is in Open-drain Output mode,3: GPIO port [n] pin is in Quasi-bidirectional.."
|
|
bitfld.long 0x00 24.--25. "PMD12,GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nNote3: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored" "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,2: GPIO port [n] pin is in Open-drain Output mode,3: GPIO port [n] pin is in Quasi-bidirectional.."
|
|
newline
|
|
bitfld.long 0x00 22.--23. "PMD11,GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nNote3: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored" "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,2: GPIO port [n] pin is in Open-drain Output mode,3: GPIO port [n] pin is in Quasi-bidirectional.."
|
|
bitfld.long 0x00 20.--21. "PMD10,GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nNote3: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored" "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,2: GPIO port [n] pin is in Open-drain Output mode,3: GPIO port [n] pin is in Quasi-bidirectional.."
|
|
newline
|
|
bitfld.long 0x00 18.--19. "PMD9,GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nNote3: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored" "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,2: GPIO port [n] pin is in Open-drain Output mode,3: GPIO port [n] pin is in Quasi-bidirectional.."
|
|
bitfld.long 0x00 16.--17. "PMD8,GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nNote3: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored" "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,2: GPIO port [n] pin is in Open-drain Output mode,3: GPIO port [n] pin is in Quasi-bidirectional.."
|
|
newline
|
|
bitfld.long 0x00 14.--15. "PMD7,GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nNote3: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored" "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,2: GPIO port [n] pin is in Open-drain Output mode,3: GPIO port [n] pin is in Quasi-bidirectional.."
|
|
bitfld.long 0x00 12.--13. "PMD6,GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nNote3: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored" "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,2: GPIO port [n] pin is in Open-drain Output mode,3: GPIO port [n] pin is in Quasi-bidirectional.."
|
|
newline
|
|
bitfld.long 0x00 10.--11. "PMD5,GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nNote3: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored" "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,2: GPIO port [n] pin is in Open-drain Output mode,3: GPIO port [n] pin is in Quasi-bidirectional.."
|
|
bitfld.long 0x00 8.--9. "PMD4,GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nNote3: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored" "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,2: GPIO port [n] pin is in Open-drain Output mode,3: GPIO port [n] pin is in Quasi-bidirectional.."
|
|
newline
|
|
bitfld.long 0x00 6.--7. "PMD3,GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nNote3: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored" "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,2: GPIO port [n] pin is in Open-drain Output mode,3: GPIO port [n] pin is in Quasi-bidirectional.."
|
|
bitfld.long 0x00 4.--5. "PMD2,GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nNote3: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored" "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,2: GPIO port [n] pin is in Open-drain Output mode,3: GPIO port [n] pin is in Quasi-bidirectional.."
|
|
newline
|
|
bitfld.long 0x00 2.--3. "PMD1,GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nNote3: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored" "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,2: GPIO port [n] pin is in Open-drain Output mode,3: GPIO port [n] pin is in Quasi-bidirectional.."
|
|
bitfld.long 0x00 0.--1. "PMD0,GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nNote3: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored" "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,2: GPIO port [n] pin is in Open-drain Output mode,3: GPIO port [n] pin is in Quasi-bidirectional.."
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "GPIOA_OFFD,GPIO Port A Pin Digital Input Path Disable Register"
|
|
hexmask.long.word 0x00 16.--31. 1. "OFFD,GPIOx Pin[N] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding GPIO pin is disabled"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "GPIOA_DOUT,GPIO Port A Data Output Value Register"
|
|
bitfld.long 0x00 15. "DOUT15,GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode.\nNote2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored" "0: GPIO port [A/B/C/E/F] Pin[n] will drive Low..,1: GPIO port [A/B/C/E/F] Pin[n] will drive High.."
|
|
bitfld.long 0x00 14. "DOUT14,GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode.\nNote2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored" "0: GPIO port [A/B/C/E/F] Pin[n] will drive Low..,1: GPIO port [A/B/C/E/F] Pin[n] will drive High.."
|
|
newline
|
|
bitfld.long 0x00 13. "DOUT13,GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode.\nNote2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored" "0: GPIO port [A/B/C/E/F] Pin[n] will drive Low..,1: GPIO port [A/B/C/E/F] Pin[n] will drive High.."
|
|
bitfld.long 0x00 12. "DOUT12,GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode.\nNote2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored" "0: GPIO port [A/B/C/E/F] Pin[n] will drive Low..,1: GPIO port [A/B/C/E/F] Pin[n] will drive High.."
|
|
newline
|
|
bitfld.long 0x00 11. "DOUT11,GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode.\nNote2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored" "0: GPIO port [A/B/C/E/F] Pin[n] will drive Low..,1: GPIO port [A/B/C/E/F] Pin[n] will drive High.."
|
|
bitfld.long 0x00 10. "DOUT10,GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode.\nNote2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored" "0: GPIO port [A/B/C/E/F] Pin[n] will drive Low..,1: GPIO port [A/B/C/E/F] Pin[n] will drive High.."
|
|
newline
|
|
bitfld.long 0x00 9. "DOUT9,GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode.\nNote2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored" "0: GPIO port [A/B/C/E/F] Pin[n] will drive Low..,1: GPIO port [A/B/C/E/F] Pin[n] will drive High.."
|
|
bitfld.long 0x00 8. "DOUT8,GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode.\nNote2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored" "0: GPIO port [A/B/C/E/F] Pin[n] will drive Low..,1: GPIO port [A/B/C/E/F] Pin[n] will drive High.."
|
|
newline
|
|
bitfld.long 0x00 7. "DOUT7,GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode.\nNote2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored" "0: GPIO port [A/B/C/E/F] Pin[n] will drive Low..,1: GPIO port [A/B/C/E/F] Pin[n] will drive High.."
|
|
bitfld.long 0x00 6. "DOUT6,GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode.\nNote2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored" "0: GPIO port [A/B/C/E/F] Pin[n] will drive Low..,1: GPIO port [A/B/C/E/F] Pin[n] will drive High.."
|
|
newline
|
|
bitfld.long 0x00 5. "DOUT5,GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode.\nNote2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored" "0: GPIO port [A/B/C/E/F] Pin[n] will drive Low..,1: GPIO port [A/B/C/E/F] Pin[n] will drive High.."
|
|
bitfld.long 0x00 4. "DOUT4,GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode.\nNote2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored" "0: GPIO port [A/B/C/E/F] Pin[n] will drive Low..,1: GPIO port [A/B/C/E/F] Pin[n] will drive High.."
|
|
newline
|
|
bitfld.long 0x00 3. "DOUT3,GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode.\nNote2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored" "0: GPIO port [A/B/C/E/F] Pin[n] will drive Low..,1: GPIO port [A/B/C/E/F] Pin[n] will drive High.."
|
|
bitfld.long 0x00 2. "DOUT2,GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode.\nNote2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored" "0: GPIO port [A/B/C/E/F] Pin[n] will drive Low..,1: GPIO port [A/B/C/E/F] Pin[n] will drive High.."
|
|
newline
|
|
bitfld.long 0x00 1. "DOUT1,GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode.\nNote2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored" "0: GPIO port [A/B/C/E/F] Pin[n] will drive Low..,1: GPIO port [A/B/C/E/F] Pin[n] will drive High.."
|
|
bitfld.long 0x00 0. "DOUT0,GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode.\nNote2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored" "0: GPIO port [A/B/C/E/F] Pin[n] will drive Low..,1: GPIO port [A/B/C/E/F] Pin[n] will drive High.."
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "GPIOA_DMASK,GPIO Port A Data Output Write Mask Register"
|
|
bitfld.long 0x00 15. "DMASK15,Port [A/B/C/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT[n] bit" "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected"
|
|
bitfld.long 0x00 14. "DMASK14,Port [A/B/C/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT[n] bit" "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected"
|
|
newline
|
|
bitfld.long 0x00 13. "DMASK13,Port [A/B/C/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT[n] bit" "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected"
|
|
bitfld.long 0x00 12. "DMASK12,Port [A/B/C/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT[n] bit" "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected"
|
|
newline
|
|
bitfld.long 0x00 11. "DMASK11,Port [A/B/C/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT[n] bit" "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected"
|
|
bitfld.long 0x00 10. "DMASK10,Port [A/B/C/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT[n] bit" "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected"
|
|
newline
|
|
bitfld.long 0x00 9. "DMASK9,Port [A/B/C/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT[n] bit" "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected"
|
|
bitfld.long 0x00 8. "DMASK8,Port [A/B/C/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT[n] bit" "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected"
|
|
newline
|
|
bitfld.long 0x00 7. "DMASK7,Port [A/B/C/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT[n] bit" "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected"
|
|
bitfld.long 0x00 6. "DMASK6,Port [A/B/C/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT[n] bit" "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected"
|
|
newline
|
|
bitfld.long 0x00 5. "DMASK5,Port [A/B/C/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT[n] bit" "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected"
|
|
bitfld.long 0x00 4. "DMASK4,Port [A/B/C/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT[n] bit" "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected"
|
|
newline
|
|
bitfld.long 0x00 3. "DMASK3,Port [A/B/C/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT[n] bit" "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected"
|
|
bitfld.long 0x00 2. "DMASK2,Port [A/B/C/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT[n] bit" "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected"
|
|
newline
|
|
bitfld.long 0x00 1. "DMASK1,Port [A/B/C/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT[n] bit" "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected"
|
|
bitfld.long 0x00 0. "DMASK0,Port [A/B/C/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT[n] bit" "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected"
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "GPIOA_PIN,GPIO Port A Pin Value Register"
|
|
bitfld.long 0x00 15. "PIN15,Port [A/B/C/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin" "0,1"
|
|
bitfld.long 0x00 14. "PIN14,Port [A/B/C/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "PIN13,Port [A/B/C/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin" "0,1"
|
|
bitfld.long 0x00 12. "PIN12,Port [A/B/C/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. "PIN11,Port [A/B/C/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin" "0,1"
|
|
bitfld.long 0x00 10. "PIN10,Port [A/B/C/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "PIN9,Port [A/B/C/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin" "0,1"
|
|
bitfld.long 0x00 8. "PIN8,Port [A/B/C/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "PIN7,Port [A/B/C/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin" "0,1"
|
|
bitfld.long 0x00 6. "PIN6,Port [A/B/C/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "PIN5,Port [A/B/C/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin" "0,1"
|
|
bitfld.long 0x00 4. "PIN4,Port [A/B/C/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "PIN3,Port [A/B/C/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin" "0,1"
|
|
bitfld.long 0x00 2. "PIN2,Port [A/B/C/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "PIN1,Port [A/B/C/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin" "0,1"
|
|
bitfld.long 0x00 0. "PIN0,Port [A/B/C/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin" "0,1"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "GPIOA_DBEN,GPIO Port A De-bounce Enable Register"
|
|
bitfld.long 0x00 15. "DBEN15,Port [A/B/C/E/F] Input Signal De-Bounce Enable Bit\nDBEN[n] is used to enable the de-bounce function for each corresponding bit" "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled"
|
|
bitfld.long 0x00 14. "DBEN14,Port [A/B/C/E/F] Input Signal De-Bounce Enable Bit\nDBEN[n] is used to enable the de-bounce function for each corresponding bit" "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled"
|
|
newline
|
|
bitfld.long 0x00 13. "DBEN13,Port [A/B/C/E/F] Input Signal De-Bounce Enable Bit\nDBEN[n] is used to enable the de-bounce function for each corresponding bit" "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled"
|
|
bitfld.long 0x00 12. "DBEN12,Port [A/B/C/E/F] Input Signal De-Bounce Enable Bit\nDBEN[n] is used to enable the de-bounce function for each corresponding bit" "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled"
|
|
newline
|
|
bitfld.long 0x00 11. "DBEN11,Port [A/B/C/E/F] Input Signal De-Bounce Enable Bit\nDBEN[n] is used to enable the de-bounce function for each corresponding bit" "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled"
|
|
bitfld.long 0x00 10. "DBEN10,Port [A/B/C/E/F] Input Signal De-Bounce Enable Bit\nDBEN[n] is used to enable the de-bounce function for each corresponding bit" "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled"
|
|
newline
|
|
bitfld.long 0x00 9. "DBEN9,Port [A/B/C/E/F] Input Signal De-Bounce Enable Bit\nDBEN[n] is used to enable the de-bounce function for each corresponding bit" "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled"
|
|
bitfld.long 0x00 8. "DBEN8,Port [A/B/C/E/F] Input Signal De-Bounce Enable Bit\nDBEN[n] is used to enable the de-bounce function for each corresponding bit" "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. "DBEN7,Port [A/B/C/E/F] Input Signal De-Bounce Enable Bit\nDBEN[n] is used to enable the de-bounce function for each corresponding bit" "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled"
|
|
bitfld.long 0x00 6. "DBEN6,Port [A/B/C/E/F] Input Signal De-Bounce Enable Bit\nDBEN[n] is used to enable the de-bounce function for each corresponding bit" "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled"
|
|
newline
|
|
bitfld.long 0x00 5. "DBEN5,Port [A/B/C/E/F] Input Signal De-Bounce Enable Bit\nDBEN[n] is used to enable the de-bounce function for each corresponding bit" "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled"
|
|
bitfld.long 0x00 4. "DBEN4,Port [A/B/C/E/F] Input Signal De-Bounce Enable Bit\nDBEN[n] is used to enable the de-bounce function for each corresponding bit" "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled"
|
|
newline
|
|
bitfld.long 0x00 3. "DBEN3,Port [A/B/C/E/F] Input Signal De-Bounce Enable Bit\nDBEN[n] is used to enable the de-bounce function for each corresponding bit" "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled"
|
|
bitfld.long 0x00 2. "DBEN2,Port [A/B/C/E/F] Input Signal De-Bounce Enable Bit\nDBEN[n] is used to enable the de-bounce function for each corresponding bit" "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. "DBEN1,Port [A/B/C/E/F] Input Signal De-Bounce Enable Bit\nDBEN[n] is used to enable the de-bounce function for each corresponding bit" "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled"
|
|
bitfld.long 0x00 0. "DBEN0,Port [A/B/C/E/F] Input Signal De-Bounce Enable Bit\nDBEN[n] is used to enable the de-bounce function for each corresponding bit" "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "GPIOA_IMD,GPIO Port A Interrupt Mode Control Register"
|
|
bitfld.long 0x00 15. "IMD15,Port [A/B/C/E/F] Edge Or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
|
|
bitfld.long 0x00 14. "IMD14,Port [A/B/C/E/F] Edge Or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
|
|
newline
|
|
bitfld.long 0x00 13. "IMD13,Port [A/B/C/E/F] Edge Or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
|
|
bitfld.long 0x00 12. "IMD12,Port [A/B/C/E/F] Edge Or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
|
|
newline
|
|
bitfld.long 0x00 11. "IMD11,Port [A/B/C/E/F] Edge Or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
|
|
bitfld.long 0x00 10. "IMD10,Port [A/B/C/E/F] Edge Or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
|
|
newline
|
|
bitfld.long 0x00 9. "IMD9,Port [A/B/C/E/F] Edge Or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
|
|
bitfld.long 0x00 8. "IMD8,Port [A/B/C/E/F] Edge Or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
|
|
newline
|
|
bitfld.long 0x00 7. "IMD7,Port [A/B/C/E/F] Edge Or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
|
|
bitfld.long 0x00 6. "IMD6,Port [A/B/C/E/F] Edge Or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
|
|
newline
|
|
bitfld.long 0x00 5. "IMD5,Port [A/B/C/E/F] Edge Or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
|
|
bitfld.long 0x00 4. "IMD4,Port [A/B/C/E/F] Edge Or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
|
|
newline
|
|
bitfld.long 0x00 3. "IMD3,Port [A/B/C/E/F] Edge Or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
|
|
bitfld.long 0x00 2. "IMD2,Port [A/B/C/E/F] Edge Or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
|
|
newline
|
|
bitfld.long 0x00 1. "IMD1,Port [A/B/C/E/F] Edge Or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
|
|
bitfld.long 0x00 0. "IMD0,Port [A/B/C/E/F] Edge Or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "GPIOA_IEN,GPIO Port A Interrupt Enable Register"
|
|
bitfld.long 0x00 31. "IR_EN15,Port [A/B/C/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] level-high or low-to-high interrupt..,1: PIN[n] level-high or low-to-high interrupt.."
|
|
bitfld.long 0x00 30. "IR_EN14,Port [A/B/C/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] level-high or low-to-high interrupt..,1: PIN[n] level-high or low-to-high interrupt.."
|
|
newline
|
|
bitfld.long 0x00 29. "IR_EN13,Port [A/B/C/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] level-high or low-to-high interrupt..,1: PIN[n] level-high or low-to-high interrupt.."
|
|
bitfld.long 0x00 28. "IR_EN12,Port [A/B/C/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] level-high or low-to-high interrupt..,1: PIN[n] level-high or low-to-high interrupt.."
|
|
newline
|
|
bitfld.long 0x00 27. "IR_EN11,Port [A/B/C/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] level-high or low-to-high interrupt..,1: PIN[n] level-high or low-to-high interrupt.."
|
|
bitfld.long 0x00 26. "IR_EN10,Port [A/B/C/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] level-high or low-to-high interrupt..,1: PIN[n] level-high or low-to-high interrupt.."
|
|
newline
|
|
bitfld.long 0x00 25. "IR_EN9,Port [A/B/C/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] level-high or low-to-high interrupt..,1: PIN[n] level-high or low-to-high interrupt.."
|
|
bitfld.long 0x00 24. "IR_EN8,Port [A/B/C/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] level-high or low-to-high interrupt..,1: PIN[n] level-high or low-to-high interrupt.."
|
|
newline
|
|
bitfld.long 0x00 23. "IR_EN7,Port [A/B/C/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] level-high or low-to-high interrupt..,1: PIN[n] level-high or low-to-high interrupt.."
|
|
bitfld.long 0x00 22. "IR_EN6,Port [A/B/C/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] level-high or low-to-high interrupt..,1: PIN[n] level-high or low-to-high interrupt.."
|
|
newline
|
|
bitfld.long 0x00 21. "IR_EN5,Port [A/B/C/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] level-high or low-to-high interrupt..,1: PIN[n] level-high or low-to-high interrupt.."
|
|
bitfld.long 0x00 20. "IR_EN4,Port [A/B/C/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] level-high or low-to-high interrupt..,1: PIN[n] level-high or low-to-high interrupt.."
|
|
newline
|
|
bitfld.long 0x00 19. "IR_EN3,Port [A/B/C/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] level-high or low-to-high interrupt..,1: PIN[n] level-high or low-to-high interrupt.."
|
|
bitfld.long 0x00 18. "IR_EN2,Port [A/B/C/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] level-high or low-to-high interrupt..,1: PIN[n] level-high or low-to-high interrupt.."
|
|
newline
|
|
bitfld.long 0x00 17. "IR_EN1,Port [A/B/C/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] level-high or low-to-high interrupt..,1: PIN[n] level-high or low-to-high interrupt.."
|
|
bitfld.long 0x00 16. "IR_EN0,Port [A/B/C/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] level-high or low-to-high interrupt..,1: PIN[n] level-high or low-to-high interrupt.."
|
|
newline
|
|
bitfld.long 0x00 15. "IF_EN15,Port [A/B/C/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] state low-level or high-to-low change..,1: PIN[n] state low-level or high-to-low change.."
|
|
bitfld.long 0x00 14. "IF_EN14,Port [A/B/C/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] state low-level or high-to-low change..,1: PIN[n] state low-level or high-to-low change.."
|
|
newline
|
|
bitfld.long 0x00 13. "IF_EN13,Port [A/B/C/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] state low-level or high-to-low change..,1: PIN[n] state low-level or high-to-low change.."
|
|
bitfld.long 0x00 12. "IF_EN12,Port [A/B/C/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] state low-level or high-to-low change..,1: PIN[n] state low-level or high-to-low change.."
|
|
newline
|
|
bitfld.long 0x00 11. "IF_EN11,Port [A/B/C/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] state low-level or high-to-low change..,1: PIN[n] state low-level or high-to-low change.."
|
|
bitfld.long 0x00 10. "IF_EN10,Port [A/B/C/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] state low-level or high-to-low change..,1: PIN[n] state low-level or high-to-low change.."
|
|
newline
|
|
bitfld.long 0x00 9. "IF_EN9,Port [A/B/C/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] state low-level or high-to-low change..,1: PIN[n] state low-level or high-to-low change.."
|
|
bitfld.long 0x00 8. "IF_EN8,Port [A/B/C/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] state low-level or high-to-low change..,1: PIN[n] state low-level or high-to-low change.."
|
|
newline
|
|
bitfld.long 0x00 7. "IF_EN7,Port [A/B/C/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] state low-level or high-to-low change..,1: PIN[n] state low-level or high-to-low change.."
|
|
bitfld.long 0x00 6. "IF_EN6,Port [A/B/C/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] state low-level or high-to-low change..,1: PIN[n] state low-level or high-to-low change.."
|
|
newline
|
|
bitfld.long 0x00 5. "IF_EN5,Port [A/B/C/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] state low-level or high-to-low change..,1: PIN[n] state low-level or high-to-low change.."
|
|
bitfld.long 0x00 4. "IF_EN4,Port [A/B/C/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] state low-level or high-to-low change..,1: PIN[n] state low-level or high-to-low change.."
|
|
newline
|
|
bitfld.long 0x00 3. "IF_EN3,Port [A/B/C/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] state low-level or high-to-low change..,1: PIN[n] state low-level or high-to-low change.."
|
|
bitfld.long 0x00 2. "IF_EN2,Port [A/B/C/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] state low-level or high-to-low change..,1: PIN[n] state low-level or high-to-low change.."
|
|
newline
|
|
bitfld.long 0x00 1. "IF_EN1,Port [A/B/C/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] state low-level or high-to-low change..,1: PIN[n] state low-level or high-to-low change.."
|
|
bitfld.long 0x00 0. "IF_EN0,Port [A/B/C/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] state low-level or high-to-low change..,1: PIN[n] state low-level or high-to-low change.."
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "GPIOA_ISRC,GPIO Port A Interrupt Source Flag Register"
|
|
bitfld.long 0x00 15. "ISRC15,Port [A/B/C/E/F] Interrupt Source Flag\nRead :\nNote2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored" "0: No interrupt at GPIOx[n].\nNo action,1: GPIOx[n] generates an interrupt.\nClear the.."
|
|
bitfld.long 0x00 14. "ISRC14,Port [A/B/C/E/F] Interrupt Source Flag\nRead :\nNote2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored" "0: No interrupt at GPIOx[n].\nNo action,1: GPIOx[n] generates an interrupt.\nClear the.."
|
|
newline
|
|
bitfld.long 0x00 13. "ISRC13,Port [A/B/C/E/F] Interrupt Source Flag\nRead :\nNote2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored" "0: No interrupt at GPIOx[n].\nNo action,1: GPIOx[n] generates an interrupt.\nClear the.."
|
|
bitfld.long 0x00 12. "ISRC12,Port [A/B/C/E/F] Interrupt Source Flag\nRead :\nNote2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored" "0: No interrupt at GPIOx[n].\nNo action,1: GPIOx[n] generates an interrupt.\nClear the.."
|
|
newline
|
|
bitfld.long 0x00 11. "ISRC11,Port [A/B/C/E/F] Interrupt Source Flag\nRead :\nNote2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored" "0: No interrupt at GPIOx[n].\nNo action,1: GPIOx[n] generates an interrupt.\nClear the.."
|
|
bitfld.long 0x00 10. "ISRC10,Port [A/B/C/E/F] Interrupt Source Flag\nRead :\nNote2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored" "0: No interrupt at GPIOx[n].\nNo action,1: GPIOx[n] generates an interrupt.\nClear the.."
|
|
newline
|
|
bitfld.long 0x00 9. "ISRC9,Port [A/B/C/E/F] Interrupt Source Flag\nRead :\nNote2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored" "0: No interrupt at GPIOx[n].\nNo action,1: GPIOx[n] generates an interrupt.\nClear the.."
|
|
bitfld.long 0x00 8. "ISRC8,Port [A/B/C/E/F] Interrupt Source Flag\nRead :\nNote2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored" "0: No interrupt at GPIOx[n].\nNo action,1: GPIOx[n] generates an interrupt.\nClear the.."
|
|
newline
|
|
bitfld.long 0x00 7. "ISRC7,Port [A/B/C/E/F] Interrupt Source Flag\nRead :\nNote2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored" "0: No interrupt at GPIOx[n].\nNo action,1: GPIOx[n] generates an interrupt.\nClear the.."
|
|
bitfld.long 0x00 6. "ISRC6,Port [A/B/C/E/F] Interrupt Source Flag\nRead :\nNote2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored" "0: No interrupt at GPIOx[n].\nNo action,1: GPIOx[n] generates an interrupt.\nClear the.."
|
|
newline
|
|
bitfld.long 0x00 5. "ISRC5,Port [A/B/C/E/F] Interrupt Source Flag\nRead :\nNote2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored" "0: No interrupt at GPIOx[n].\nNo action,1: GPIOx[n] generates an interrupt.\nClear the.."
|
|
bitfld.long 0x00 4. "ISRC4,Port [A/B/C/E/F] Interrupt Source Flag\nRead :\nNote2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored" "0: No interrupt at GPIOx[n].\nNo action,1: GPIOx[n] generates an interrupt.\nClear the.."
|
|
newline
|
|
bitfld.long 0x00 3. "ISRC3,Port [A/B/C/E/F] Interrupt Source Flag\nRead :\nNote2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored" "0: No interrupt at GPIOx[n].\nNo action,1: GPIOx[n] generates an interrupt.\nClear the.."
|
|
bitfld.long 0x00 2. "ISRC2,Port [A/B/C/E/F] Interrupt Source Flag\nRead :\nNote2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored" "0: No interrupt at GPIOx[n].\nNo action,1: GPIOx[n] generates an interrupt.\nClear the.."
|
|
newline
|
|
bitfld.long 0x00 1. "ISRC1,Port [A/B/C/E/F] Interrupt Source Flag\nRead :\nNote2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored" "0: No interrupt at GPIOx[n].\nNo action,1: GPIOx[n] generates an interrupt.\nClear the.."
|
|
bitfld.long 0x00 0. "ISRC0,Port [A/B/C/E/F] Interrupt Source Flag\nRead :\nNote2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored" "0: No interrupt at GPIOx[n].\nNo action,1: GPIOx[n] generates an interrupt.\nClear the.."
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "GPIOB_PMD,GPIO Port B Pin I/O Mode Control Register"
|
|
bitfld.long 0x00 30.--31. "PMD15,GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nNote3: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored" "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,2: GPIO port [n] pin is in Open-drain Output mode,3: GPIO port [n] pin is in Quasi-bidirectional.."
|
|
bitfld.long 0x00 28.--29. "PMD14,GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nNote3: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored" "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,2: GPIO port [n] pin is in Open-drain Output mode,3: GPIO port [n] pin is in Quasi-bidirectional.."
|
|
newline
|
|
bitfld.long 0x00 26.--27. "PMD13,GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nNote3: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored" "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,2: GPIO port [n] pin is in Open-drain Output mode,3: GPIO port [n] pin is in Quasi-bidirectional.."
|
|
bitfld.long 0x00 24.--25. "PMD12,GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nNote3: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored" "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,2: GPIO port [n] pin is in Open-drain Output mode,3: GPIO port [n] pin is in Quasi-bidirectional.."
|
|
newline
|
|
bitfld.long 0x00 22.--23. "PMD11,GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nNote3: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored" "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,2: GPIO port [n] pin is in Open-drain Output mode,3: GPIO port [n] pin is in Quasi-bidirectional.."
|
|
bitfld.long 0x00 20.--21. "PMD10,GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nNote3: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored" "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,2: GPIO port [n] pin is in Open-drain Output mode,3: GPIO port [n] pin is in Quasi-bidirectional.."
|
|
newline
|
|
bitfld.long 0x00 18.--19. "PMD9,GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nNote3: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored" "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,2: GPIO port [n] pin is in Open-drain Output mode,3: GPIO port [n] pin is in Quasi-bidirectional.."
|
|
bitfld.long 0x00 16.--17. "PMD8,GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nNote3: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored" "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,2: GPIO port [n] pin is in Open-drain Output mode,3: GPIO port [n] pin is in Quasi-bidirectional.."
|
|
newline
|
|
bitfld.long 0x00 14.--15. "PMD7,GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nNote3: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored" "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,2: GPIO port [n] pin is in Open-drain Output mode,3: GPIO port [n] pin is in Quasi-bidirectional.."
|
|
bitfld.long 0x00 12.--13. "PMD6,GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nNote3: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored" "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,2: GPIO port [n] pin is in Open-drain Output mode,3: GPIO port [n] pin is in Quasi-bidirectional.."
|
|
newline
|
|
bitfld.long 0x00 10.--11. "PMD5,GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nNote3: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored" "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,2: GPIO port [n] pin is in Open-drain Output mode,3: GPIO port [n] pin is in Quasi-bidirectional.."
|
|
bitfld.long 0x00 8.--9. "PMD4,GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nNote3: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored" "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,2: GPIO port [n] pin is in Open-drain Output mode,3: GPIO port [n] pin is in Quasi-bidirectional.."
|
|
newline
|
|
bitfld.long 0x00 6.--7. "PMD3,GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nNote3: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored" "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,2: GPIO port [n] pin is in Open-drain Output mode,3: GPIO port [n] pin is in Quasi-bidirectional.."
|
|
bitfld.long 0x00 4.--5. "PMD2,GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nNote3: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored" "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,2: GPIO port [n] pin is in Open-drain Output mode,3: GPIO port [n] pin is in Quasi-bidirectional.."
|
|
newline
|
|
bitfld.long 0x00 2.--3. "PMD1,GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nNote3: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored" "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,2: GPIO port [n] pin is in Open-drain Output mode,3: GPIO port [n] pin is in Quasi-bidirectional.."
|
|
bitfld.long 0x00 0.--1. "PMD0,GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nNote3: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored" "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,2: GPIO port [n] pin is in Open-drain Output mode,3: GPIO port [n] pin is in Quasi-bidirectional.."
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "GPIOB_OFFD,GPIO Port B Pin Digital Input Path Disable Register"
|
|
hexmask.long.word 0x00 16.--31. 1. "OFFD,GPIOx Pin[N] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding GPIO pin is disabled"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "GPIOB_DOUT,GPIO Port B Data Output Value Register"
|
|
bitfld.long 0x00 15. "DOUT15,GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode.\nNote2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored" "0: GPIO port [A/B/C/E/F] Pin[n] will drive Low..,1: GPIO port [A/B/C/E/F] Pin[n] will drive High.."
|
|
bitfld.long 0x00 14. "DOUT14,GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode.\nNote2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored" "0: GPIO port [A/B/C/E/F] Pin[n] will drive Low..,1: GPIO port [A/B/C/E/F] Pin[n] will drive High.."
|
|
newline
|
|
bitfld.long 0x00 13. "DOUT13,GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode.\nNote2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored" "0: GPIO port [A/B/C/E/F] Pin[n] will drive Low..,1: GPIO port [A/B/C/E/F] Pin[n] will drive High.."
|
|
bitfld.long 0x00 12. "DOUT12,GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode.\nNote2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored" "0: GPIO port [A/B/C/E/F] Pin[n] will drive Low..,1: GPIO port [A/B/C/E/F] Pin[n] will drive High.."
|
|
newline
|
|
bitfld.long 0x00 11. "DOUT11,GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode.\nNote2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored" "0: GPIO port [A/B/C/E/F] Pin[n] will drive Low..,1: GPIO port [A/B/C/E/F] Pin[n] will drive High.."
|
|
bitfld.long 0x00 10. "DOUT10,GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode.\nNote2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored" "0: GPIO port [A/B/C/E/F] Pin[n] will drive Low..,1: GPIO port [A/B/C/E/F] Pin[n] will drive High.."
|
|
newline
|
|
bitfld.long 0x00 9. "DOUT9,GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode.\nNote2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored" "0: GPIO port [A/B/C/E/F] Pin[n] will drive Low..,1: GPIO port [A/B/C/E/F] Pin[n] will drive High.."
|
|
bitfld.long 0x00 8. "DOUT8,GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode.\nNote2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored" "0: GPIO port [A/B/C/E/F] Pin[n] will drive Low..,1: GPIO port [A/B/C/E/F] Pin[n] will drive High.."
|
|
newline
|
|
bitfld.long 0x00 7. "DOUT7,GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode.\nNote2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored" "0: GPIO port [A/B/C/E/F] Pin[n] will drive Low..,1: GPIO port [A/B/C/E/F] Pin[n] will drive High.."
|
|
bitfld.long 0x00 6. "DOUT6,GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode.\nNote2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored" "0: GPIO port [A/B/C/E/F] Pin[n] will drive Low..,1: GPIO port [A/B/C/E/F] Pin[n] will drive High.."
|
|
newline
|
|
bitfld.long 0x00 5. "DOUT5,GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode.\nNote2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored" "0: GPIO port [A/B/C/E/F] Pin[n] will drive Low..,1: GPIO port [A/B/C/E/F] Pin[n] will drive High.."
|
|
bitfld.long 0x00 4. "DOUT4,GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode.\nNote2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored" "0: GPIO port [A/B/C/E/F] Pin[n] will drive Low..,1: GPIO port [A/B/C/E/F] Pin[n] will drive High.."
|
|
newline
|
|
bitfld.long 0x00 3. "DOUT3,GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode.\nNote2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored" "0: GPIO port [A/B/C/E/F] Pin[n] will drive Low..,1: GPIO port [A/B/C/E/F] Pin[n] will drive High.."
|
|
bitfld.long 0x00 2. "DOUT2,GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode.\nNote2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored" "0: GPIO port [A/B/C/E/F] Pin[n] will drive Low..,1: GPIO port [A/B/C/E/F] Pin[n] will drive High.."
|
|
newline
|
|
bitfld.long 0x00 1. "DOUT1,GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode.\nNote2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored" "0: GPIO port [A/B/C/E/F] Pin[n] will drive Low..,1: GPIO port [A/B/C/E/F] Pin[n] will drive High.."
|
|
bitfld.long 0x00 0. "DOUT0,GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode.\nNote2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored" "0: GPIO port [A/B/C/E/F] Pin[n] will drive Low..,1: GPIO port [A/B/C/E/F] Pin[n] will drive High.."
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "GPIOB_DMASK,GPIO Port B Data Output Write Mask Register"
|
|
bitfld.long 0x00 15. "DMASK15,Port [A/B/C/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT[n] bit" "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected"
|
|
bitfld.long 0x00 14. "DMASK14,Port [A/B/C/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT[n] bit" "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected"
|
|
newline
|
|
bitfld.long 0x00 13. "DMASK13,Port [A/B/C/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT[n] bit" "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected"
|
|
bitfld.long 0x00 12. "DMASK12,Port [A/B/C/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT[n] bit" "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected"
|
|
newline
|
|
bitfld.long 0x00 11. "DMASK11,Port [A/B/C/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT[n] bit" "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected"
|
|
bitfld.long 0x00 10. "DMASK10,Port [A/B/C/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT[n] bit" "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected"
|
|
newline
|
|
bitfld.long 0x00 9. "DMASK9,Port [A/B/C/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT[n] bit" "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected"
|
|
bitfld.long 0x00 8. "DMASK8,Port [A/B/C/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT[n] bit" "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected"
|
|
newline
|
|
bitfld.long 0x00 7. "DMASK7,Port [A/B/C/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT[n] bit" "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected"
|
|
bitfld.long 0x00 6. "DMASK6,Port [A/B/C/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT[n] bit" "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected"
|
|
newline
|
|
bitfld.long 0x00 5. "DMASK5,Port [A/B/C/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT[n] bit" "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected"
|
|
bitfld.long 0x00 4. "DMASK4,Port [A/B/C/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT[n] bit" "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected"
|
|
newline
|
|
bitfld.long 0x00 3. "DMASK3,Port [A/B/C/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT[n] bit" "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected"
|
|
bitfld.long 0x00 2. "DMASK2,Port [A/B/C/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT[n] bit" "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected"
|
|
newline
|
|
bitfld.long 0x00 1. "DMASK1,Port [A/B/C/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT[n] bit" "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected"
|
|
bitfld.long 0x00 0. "DMASK0,Port [A/B/C/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT[n] bit" "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "GPIOB_PIN,GPIO Port B Pin Value Register"
|
|
rbitfld.long 0x00 15. "PIN15,Port [A/B/C/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin" "0,1"
|
|
rbitfld.long 0x00 14. "PIN14,Port [A/B/C/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 13. "PIN13,Port [A/B/C/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin" "0,1"
|
|
rbitfld.long 0x00 12. "PIN12,Port [A/B/C/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 11. "PIN11,Port [A/B/C/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin" "0,1"
|
|
rbitfld.long 0x00 10. "PIN10,Port [A/B/C/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 9. "PIN9,Port [A/B/C/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin" "0,1"
|
|
rbitfld.long 0x00 8. "PIN8,Port [A/B/C/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 7. "PIN7,Port [A/B/C/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin" "0,1"
|
|
rbitfld.long 0x00 6. "PIN6,Port [A/B/C/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 5. "PIN5,Port [A/B/C/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin" "0,1"
|
|
rbitfld.long 0x00 4. "PIN4,Port [A/B/C/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 3. "PIN3,Port [A/B/C/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin" "0,1"
|
|
rbitfld.long 0x00 2. "PIN2,Port [A/B/C/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 1. "PIN1,Port [A/B/C/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin" "0,1"
|
|
rbitfld.long 0x00 0. "PIN0,Port [A/B/C/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin" "0,1"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "GPIOB_DBEN,GPIO Port B De-bounce Enable Register"
|
|
bitfld.long 0x00 15. "DBEN15,Port [A/B/C/E/F] Input Signal De-Bounce Enable Bit\nDBEN[n] is used to enable the de-bounce function for each corresponding bit" "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled"
|
|
bitfld.long 0x00 14. "DBEN14,Port [A/B/C/E/F] Input Signal De-Bounce Enable Bit\nDBEN[n] is used to enable the de-bounce function for each corresponding bit" "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled"
|
|
newline
|
|
bitfld.long 0x00 13. "DBEN13,Port [A/B/C/E/F] Input Signal De-Bounce Enable Bit\nDBEN[n] is used to enable the de-bounce function for each corresponding bit" "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled"
|
|
bitfld.long 0x00 12. "DBEN12,Port [A/B/C/E/F] Input Signal De-Bounce Enable Bit\nDBEN[n] is used to enable the de-bounce function for each corresponding bit" "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled"
|
|
newline
|
|
bitfld.long 0x00 11. "DBEN11,Port [A/B/C/E/F] Input Signal De-Bounce Enable Bit\nDBEN[n] is used to enable the de-bounce function for each corresponding bit" "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled"
|
|
bitfld.long 0x00 10. "DBEN10,Port [A/B/C/E/F] Input Signal De-Bounce Enable Bit\nDBEN[n] is used to enable the de-bounce function for each corresponding bit" "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled"
|
|
newline
|
|
bitfld.long 0x00 9. "DBEN9,Port [A/B/C/E/F] Input Signal De-Bounce Enable Bit\nDBEN[n] is used to enable the de-bounce function for each corresponding bit" "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled"
|
|
bitfld.long 0x00 8. "DBEN8,Port [A/B/C/E/F] Input Signal De-Bounce Enable Bit\nDBEN[n] is used to enable the de-bounce function for each corresponding bit" "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. "DBEN7,Port [A/B/C/E/F] Input Signal De-Bounce Enable Bit\nDBEN[n] is used to enable the de-bounce function for each corresponding bit" "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled"
|
|
bitfld.long 0x00 6. "DBEN6,Port [A/B/C/E/F] Input Signal De-Bounce Enable Bit\nDBEN[n] is used to enable the de-bounce function for each corresponding bit" "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled"
|
|
newline
|
|
bitfld.long 0x00 5. "DBEN5,Port [A/B/C/E/F] Input Signal De-Bounce Enable Bit\nDBEN[n] is used to enable the de-bounce function for each corresponding bit" "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled"
|
|
bitfld.long 0x00 4. "DBEN4,Port [A/B/C/E/F] Input Signal De-Bounce Enable Bit\nDBEN[n] is used to enable the de-bounce function for each corresponding bit" "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled"
|
|
newline
|
|
bitfld.long 0x00 3. "DBEN3,Port [A/B/C/E/F] Input Signal De-Bounce Enable Bit\nDBEN[n] is used to enable the de-bounce function for each corresponding bit" "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled"
|
|
bitfld.long 0x00 2. "DBEN2,Port [A/B/C/E/F] Input Signal De-Bounce Enable Bit\nDBEN[n] is used to enable the de-bounce function for each corresponding bit" "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. "DBEN1,Port [A/B/C/E/F] Input Signal De-Bounce Enable Bit\nDBEN[n] is used to enable the de-bounce function for each corresponding bit" "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled"
|
|
bitfld.long 0x00 0. "DBEN0,Port [A/B/C/E/F] Input Signal De-Bounce Enable Bit\nDBEN[n] is used to enable the de-bounce function for each corresponding bit" "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled"
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "GPIOB_IMD,GPIO Port B Interrupt Mode Control Register"
|
|
bitfld.long 0x00 15. "IMD15,Port [A/B/C/E/F] Edge Or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
|
|
bitfld.long 0x00 14. "IMD14,Port [A/B/C/E/F] Edge Or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
|
|
newline
|
|
bitfld.long 0x00 13. "IMD13,Port [A/B/C/E/F] Edge Or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
|
|
bitfld.long 0x00 12. "IMD12,Port [A/B/C/E/F] Edge Or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
|
|
newline
|
|
bitfld.long 0x00 11. "IMD11,Port [A/B/C/E/F] Edge Or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
|
|
bitfld.long 0x00 10. "IMD10,Port [A/B/C/E/F] Edge Or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
|
|
newline
|
|
bitfld.long 0x00 9. "IMD9,Port [A/B/C/E/F] Edge Or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
|
|
bitfld.long 0x00 8. "IMD8,Port [A/B/C/E/F] Edge Or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
|
|
newline
|
|
bitfld.long 0x00 7. "IMD7,Port [A/B/C/E/F] Edge Or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
|
|
bitfld.long 0x00 6. "IMD6,Port [A/B/C/E/F] Edge Or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
|
|
newline
|
|
bitfld.long 0x00 5. "IMD5,Port [A/B/C/E/F] Edge Or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
|
|
bitfld.long 0x00 4. "IMD4,Port [A/B/C/E/F] Edge Or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
|
|
newline
|
|
bitfld.long 0x00 3. "IMD3,Port [A/B/C/E/F] Edge Or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
|
|
bitfld.long 0x00 2. "IMD2,Port [A/B/C/E/F] Edge Or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
|
|
newline
|
|
bitfld.long 0x00 1. "IMD1,Port [A/B/C/E/F] Edge Or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
|
|
bitfld.long 0x00 0. "IMD0,Port [A/B/C/E/F] Edge Or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
|
|
group.long 0x5C++0x03
|
|
line.long 0x00 "GPIOB_IEN,GPIO Port B Interrupt Enable Register"
|
|
bitfld.long 0x00 31. "IR_EN15,Port [A/B/C/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] level-high or low-to-high interrupt..,1: PIN[n] level-high or low-to-high interrupt.."
|
|
bitfld.long 0x00 30. "IR_EN14,Port [A/B/C/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] level-high or low-to-high interrupt..,1: PIN[n] level-high or low-to-high interrupt.."
|
|
newline
|
|
bitfld.long 0x00 29. "IR_EN13,Port [A/B/C/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] level-high or low-to-high interrupt..,1: PIN[n] level-high or low-to-high interrupt.."
|
|
bitfld.long 0x00 28. "IR_EN12,Port [A/B/C/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] level-high or low-to-high interrupt..,1: PIN[n] level-high or low-to-high interrupt.."
|
|
newline
|
|
bitfld.long 0x00 27. "IR_EN11,Port [A/B/C/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] level-high or low-to-high interrupt..,1: PIN[n] level-high or low-to-high interrupt.."
|
|
bitfld.long 0x00 26. "IR_EN10,Port [A/B/C/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] level-high or low-to-high interrupt..,1: PIN[n] level-high or low-to-high interrupt.."
|
|
newline
|
|
bitfld.long 0x00 25. "IR_EN9,Port [A/B/C/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] level-high or low-to-high interrupt..,1: PIN[n] level-high or low-to-high interrupt.."
|
|
bitfld.long 0x00 24. "IR_EN8,Port [A/B/C/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] level-high or low-to-high interrupt..,1: PIN[n] level-high or low-to-high interrupt.."
|
|
newline
|
|
bitfld.long 0x00 23. "IR_EN7,Port [A/B/C/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] level-high or low-to-high interrupt..,1: PIN[n] level-high or low-to-high interrupt.."
|
|
bitfld.long 0x00 22. "IR_EN6,Port [A/B/C/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] level-high or low-to-high interrupt..,1: PIN[n] level-high or low-to-high interrupt.."
|
|
newline
|
|
bitfld.long 0x00 21. "IR_EN5,Port [A/B/C/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] level-high or low-to-high interrupt..,1: PIN[n] level-high or low-to-high interrupt.."
|
|
bitfld.long 0x00 20. "IR_EN4,Port [A/B/C/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] level-high or low-to-high interrupt..,1: PIN[n] level-high or low-to-high interrupt.."
|
|
newline
|
|
bitfld.long 0x00 19. "IR_EN3,Port [A/B/C/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] level-high or low-to-high interrupt..,1: PIN[n] level-high or low-to-high interrupt.."
|
|
bitfld.long 0x00 18. "IR_EN2,Port [A/B/C/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] level-high or low-to-high interrupt..,1: PIN[n] level-high or low-to-high interrupt.."
|
|
newline
|
|
bitfld.long 0x00 17. "IR_EN1,Port [A/B/C/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] level-high or low-to-high interrupt..,1: PIN[n] level-high or low-to-high interrupt.."
|
|
bitfld.long 0x00 16. "IR_EN0,Port [A/B/C/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] level-high or low-to-high interrupt..,1: PIN[n] level-high or low-to-high interrupt.."
|
|
newline
|
|
bitfld.long 0x00 15. "IF_EN15,Port [A/B/C/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] state low-level or high-to-low change..,1: PIN[n] state low-level or high-to-low change.."
|
|
bitfld.long 0x00 14. "IF_EN14,Port [A/B/C/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] state low-level or high-to-low change..,1: PIN[n] state low-level or high-to-low change.."
|
|
newline
|
|
bitfld.long 0x00 13. "IF_EN13,Port [A/B/C/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] state low-level or high-to-low change..,1: PIN[n] state low-level or high-to-low change.."
|
|
bitfld.long 0x00 12. "IF_EN12,Port [A/B/C/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] state low-level or high-to-low change..,1: PIN[n] state low-level or high-to-low change.."
|
|
newline
|
|
bitfld.long 0x00 11. "IF_EN11,Port [A/B/C/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] state low-level or high-to-low change..,1: PIN[n] state low-level or high-to-low change.."
|
|
bitfld.long 0x00 10. "IF_EN10,Port [A/B/C/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] state low-level or high-to-low change..,1: PIN[n] state low-level or high-to-low change.."
|
|
newline
|
|
bitfld.long 0x00 9. "IF_EN9,Port [A/B/C/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] state low-level or high-to-low change..,1: PIN[n] state low-level or high-to-low change.."
|
|
bitfld.long 0x00 8. "IF_EN8,Port [A/B/C/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] state low-level or high-to-low change..,1: PIN[n] state low-level or high-to-low change.."
|
|
newline
|
|
bitfld.long 0x00 7. "IF_EN7,Port [A/B/C/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] state low-level or high-to-low change..,1: PIN[n] state low-level or high-to-low change.."
|
|
bitfld.long 0x00 6. "IF_EN6,Port [A/B/C/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] state low-level or high-to-low change..,1: PIN[n] state low-level or high-to-low change.."
|
|
newline
|
|
bitfld.long 0x00 5. "IF_EN5,Port [A/B/C/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] state low-level or high-to-low change..,1: PIN[n] state low-level or high-to-low change.."
|
|
bitfld.long 0x00 4. "IF_EN4,Port [A/B/C/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] state low-level or high-to-low change..,1: PIN[n] state low-level or high-to-low change.."
|
|
newline
|
|
bitfld.long 0x00 3. "IF_EN3,Port [A/B/C/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] state low-level or high-to-low change..,1: PIN[n] state low-level or high-to-low change.."
|
|
bitfld.long 0x00 2. "IF_EN2,Port [A/B/C/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] state low-level or high-to-low change..,1: PIN[n] state low-level or high-to-low change.."
|
|
newline
|
|
bitfld.long 0x00 1. "IF_EN1,Port [A/B/C/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] state low-level or high-to-low change..,1: PIN[n] state low-level or high-to-low change.."
|
|
bitfld.long 0x00 0. "IF_EN0,Port [A/B/C/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] state low-level or high-to-low change..,1: PIN[n] state low-level or high-to-low change.."
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "GPIOB_ISRC,GPIO Port B Interrupt Source Flag Register"
|
|
bitfld.long 0x00 15. "ISRC15,Port [A/B/C/E/F] Interrupt Source Flag\nRead :\nNote2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored" "0: No interrupt at GPIOx[n].\nNo action,1: GPIOx[n] generates an interrupt.\nClear the.."
|
|
bitfld.long 0x00 14. "ISRC14,Port [A/B/C/E/F] Interrupt Source Flag\nRead :\nNote2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored" "0: No interrupt at GPIOx[n].\nNo action,1: GPIOx[n] generates an interrupt.\nClear the.."
|
|
newline
|
|
bitfld.long 0x00 13. "ISRC13,Port [A/B/C/E/F] Interrupt Source Flag\nRead :\nNote2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored" "0: No interrupt at GPIOx[n].\nNo action,1: GPIOx[n] generates an interrupt.\nClear the.."
|
|
bitfld.long 0x00 12. "ISRC12,Port [A/B/C/E/F] Interrupt Source Flag\nRead :\nNote2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored" "0: No interrupt at GPIOx[n].\nNo action,1: GPIOx[n] generates an interrupt.\nClear the.."
|
|
newline
|
|
bitfld.long 0x00 11. "ISRC11,Port [A/B/C/E/F] Interrupt Source Flag\nRead :\nNote2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored" "0: No interrupt at GPIOx[n].\nNo action,1: GPIOx[n] generates an interrupt.\nClear the.."
|
|
bitfld.long 0x00 10. "ISRC10,Port [A/B/C/E/F] Interrupt Source Flag\nRead :\nNote2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored" "0: No interrupt at GPIOx[n].\nNo action,1: GPIOx[n] generates an interrupt.\nClear the.."
|
|
newline
|
|
bitfld.long 0x00 9. "ISRC9,Port [A/B/C/E/F] Interrupt Source Flag\nRead :\nNote2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored" "0: No interrupt at GPIOx[n].\nNo action,1: GPIOx[n] generates an interrupt.\nClear the.."
|
|
bitfld.long 0x00 8. "ISRC8,Port [A/B/C/E/F] Interrupt Source Flag\nRead :\nNote2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored" "0: No interrupt at GPIOx[n].\nNo action,1: GPIOx[n] generates an interrupt.\nClear the.."
|
|
newline
|
|
bitfld.long 0x00 7. "ISRC7,Port [A/B/C/E/F] Interrupt Source Flag\nRead :\nNote2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored" "0: No interrupt at GPIOx[n].\nNo action,1: GPIOx[n] generates an interrupt.\nClear the.."
|
|
bitfld.long 0x00 6. "ISRC6,Port [A/B/C/E/F] Interrupt Source Flag\nRead :\nNote2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored" "0: No interrupt at GPIOx[n].\nNo action,1: GPIOx[n] generates an interrupt.\nClear the.."
|
|
newline
|
|
bitfld.long 0x00 5. "ISRC5,Port [A/B/C/E/F] Interrupt Source Flag\nRead :\nNote2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored" "0: No interrupt at GPIOx[n].\nNo action,1: GPIOx[n] generates an interrupt.\nClear the.."
|
|
bitfld.long 0x00 4. "ISRC4,Port [A/B/C/E/F] Interrupt Source Flag\nRead :\nNote2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored" "0: No interrupt at GPIOx[n].\nNo action,1: GPIOx[n] generates an interrupt.\nClear the.."
|
|
newline
|
|
bitfld.long 0x00 3. "ISRC3,Port [A/B/C/E/F] Interrupt Source Flag\nRead :\nNote2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored" "0: No interrupt at GPIOx[n].\nNo action,1: GPIOx[n] generates an interrupt.\nClear the.."
|
|
bitfld.long 0x00 2. "ISRC2,Port [A/B/C/E/F] Interrupt Source Flag\nRead :\nNote2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored" "0: No interrupt at GPIOx[n].\nNo action,1: GPIOx[n] generates an interrupt.\nClear the.."
|
|
newline
|
|
bitfld.long 0x00 1. "ISRC1,Port [A/B/C/E/F] Interrupt Source Flag\nRead :\nNote2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored" "0: No interrupt at GPIOx[n].\nNo action,1: GPIOx[n] generates an interrupt.\nClear the.."
|
|
bitfld.long 0x00 0. "ISRC0,Port [A/B/C/E/F] Interrupt Source Flag\nRead :\nNote2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored" "0: No interrupt at GPIOx[n].\nNo action,1: GPIOx[n] generates an interrupt.\nClear the.."
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "GPIOC_PMD,GPIO Port C Pin I/O Mode Control Register"
|
|
bitfld.long 0x00 30.--31. "PMD15,GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nNote3: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored" "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,2: GPIO port [n] pin is in Open-drain Output mode,3: GPIO port [n] pin is in Quasi-bidirectional.."
|
|
bitfld.long 0x00 28.--29. "PMD14,GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nNote3: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored" "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,2: GPIO port [n] pin is in Open-drain Output mode,3: GPIO port [n] pin is in Quasi-bidirectional.."
|
|
newline
|
|
bitfld.long 0x00 26.--27. "PMD13,GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nNote3: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored" "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,2: GPIO port [n] pin is in Open-drain Output mode,3: GPIO port [n] pin is in Quasi-bidirectional.."
|
|
bitfld.long 0x00 24.--25. "PMD12,GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nNote3: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored" "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,2: GPIO port [n] pin is in Open-drain Output mode,3: GPIO port [n] pin is in Quasi-bidirectional.."
|
|
newline
|
|
bitfld.long 0x00 22.--23. "PMD11,GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nNote3: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored" "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,2: GPIO port [n] pin is in Open-drain Output mode,3: GPIO port [n] pin is in Quasi-bidirectional.."
|
|
bitfld.long 0x00 20.--21. "PMD10,GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nNote3: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored" "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,2: GPIO port [n] pin is in Open-drain Output mode,3: GPIO port [n] pin is in Quasi-bidirectional.."
|
|
newline
|
|
bitfld.long 0x00 18.--19. "PMD9,GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nNote3: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored" "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,2: GPIO port [n] pin is in Open-drain Output mode,3: GPIO port [n] pin is in Quasi-bidirectional.."
|
|
bitfld.long 0x00 16.--17. "PMD8,GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nNote3: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored" "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,2: GPIO port [n] pin is in Open-drain Output mode,3: GPIO port [n] pin is in Quasi-bidirectional.."
|
|
newline
|
|
bitfld.long 0x00 14.--15. "PMD7,GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nNote3: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored" "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,2: GPIO port [n] pin is in Open-drain Output mode,3: GPIO port [n] pin is in Quasi-bidirectional.."
|
|
bitfld.long 0x00 12.--13. "PMD6,GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nNote3: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored" "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,2: GPIO port [n] pin is in Open-drain Output mode,3: GPIO port [n] pin is in Quasi-bidirectional.."
|
|
newline
|
|
bitfld.long 0x00 10.--11. "PMD5,GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nNote3: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored" "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,2: GPIO port [n] pin is in Open-drain Output mode,3: GPIO port [n] pin is in Quasi-bidirectional.."
|
|
bitfld.long 0x00 8.--9. "PMD4,GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nNote3: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored" "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,2: GPIO port [n] pin is in Open-drain Output mode,3: GPIO port [n] pin is in Quasi-bidirectional.."
|
|
newline
|
|
bitfld.long 0x00 6.--7. "PMD3,GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nNote3: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored" "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,2: GPIO port [n] pin is in Open-drain Output mode,3: GPIO port [n] pin is in Quasi-bidirectional.."
|
|
bitfld.long 0x00 4.--5. "PMD2,GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nNote3: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored" "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,2: GPIO port [n] pin is in Open-drain Output mode,3: GPIO port [n] pin is in Quasi-bidirectional.."
|
|
newline
|
|
bitfld.long 0x00 2.--3. "PMD1,GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nNote3: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored" "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,2: GPIO port [n] pin is in Open-drain Output mode,3: GPIO port [n] pin is in Quasi-bidirectional.."
|
|
bitfld.long 0x00 0.--1. "PMD0,GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nNote3: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored" "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,2: GPIO port [n] pin is in Open-drain Output mode,3: GPIO port [n] pin is in Quasi-bidirectional.."
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "GPIOC_OFFD,GPIO Port C Pin Digital Input Path Disable Register"
|
|
hexmask.long.word 0x00 16.--31. 1. "OFFD,GPIOx Pin[N] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding GPIO pin is disabled"
|
|
group.long 0x88++0x03
|
|
line.long 0x00 "GPIOC_DOUT,GPIO Port C Data Output Value Register"
|
|
bitfld.long 0x00 15. "DOUT15,GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode.\nNote2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored" "0: GPIO port [A/B/C/E/F] Pin[n] will drive Low..,1: GPIO port [A/B/C/E/F] Pin[n] will drive High.."
|
|
bitfld.long 0x00 14. "DOUT14,GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode.\nNote2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored" "0: GPIO port [A/B/C/E/F] Pin[n] will drive Low..,1: GPIO port [A/B/C/E/F] Pin[n] will drive High.."
|
|
newline
|
|
bitfld.long 0x00 13. "DOUT13,GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode.\nNote2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored" "0: GPIO port [A/B/C/E/F] Pin[n] will drive Low..,1: GPIO port [A/B/C/E/F] Pin[n] will drive High.."
|
|
bitfld.long 0x00 12. "DOUT12,GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode.\nNote2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored" "0: GPIO port [A/B/C/E/F] Pin[n] will drive Low..,1: GPIO port [A/B/C/E/F] Pin[n] will drive High.."
|
|
newline
|
|
bitfld.long 0x00 11. "DOUT11,GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode.\nNote2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored" "0: GPIO port [A/B/C/E/F] Pin[n] will drive Low..,1: GPIO port [A/B/C/E/F] Pin[n] will drive High.."
|
|
bitfld.long 0x00 10. "DOUT10,GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode.\nNote2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored" "0: GPIO port [A/B/C/E/F] Pin[n] will drive Low..,1: GPIO port [A/B/C/E/F] Pin[n] will drive High.."
|
|
newline
|
|
bitfld.long 0x00 9. "DOUT9,GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode.\nNote2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored" "0: GPIO port [A/B/C/E/F] Pin[n] will drive Low..,1: GPIO port [A/B/C/E/F] Pin[n] will drive High.."
|
|
bitfld.long 0x00 8. "DOUT8,GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode.\nNote2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored" "0: GPIO port [A/B/C/E/F] Pin[n] will drive Low..,1: GPIO port [A/B/C/E/F] Pin[n] will drive High.."
|
|
newline
|
|
bitfld.long 0x00 7. "DOUT7,GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode.\nNote2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored" "0: GPIO port [A/B/C/E/F] Pin[n] will drive Low..,1: GPIO port [A/B/C/E/F] Pin[n] will drive High.."
|
|
bitfld.long 0x00 6. "DOUT6,GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode.\nNote2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored" "0: GPIO port [A/B/C/E/F] Pin[n] will drive Low..,1: GPIO port [A/B/C/E/F] Pin[n] will drive High.."
|
|
newline
|
|
bitfld.long 0x00 5. "DOUT5,GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode.\nNote2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored" "0: GPIO port [A/B/C/E/F] Pin[n] will drive Low..,1: GPIO port [A/B/C/E/F] Pin[n] will drive High.."
|
|
bitfld.long 0x00 4. "DOUT4,GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode.\nNote2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored" "0: GPIO port [A/B/C/E/F] Pin[n] will drive Low..,1: GPIO port [A/B/C/E/F] Pin[n] will drive High.."
|
|
newline
|
|
bitfld.long 0x00 3. "DOUT3,GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode.\nNote2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored" "0: GPIO port [A/B/C/E/F] Pin[n] will drive Low..,1: GPIO port [A/B/C/E/F] Pin[n] will drive High.."
|
|
bitfld.long 0x00 2. "DOUT2,GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode.\nNote2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored" "0: GPIO port [A/B/C/E/F] Pin[n] will drive Low..,1: GPIO port [A/B/C/E/F] Pin[n] will drive High.."
|
|
newline
|
|
bitfld.long 0x00 1. "DOUT1,GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode.\nNote2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored" "0: GPIO port [A/B/C/E/F] Pin[n] will drive Low..,1: GPIO port [A/B/C/E/F] Pin[n] will drive High.."
|
|
bitfld.long 0x00 0. "DOUT0,GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode.\nNote2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored" "0: GPIO port [A/B/C/E/F] Pin[n] will drive Low..,1: GPIO port [A/B/C/E/F] Pin[n] will drive High.."
|
|
group.long 0x8C++0x03
|
|
line.long 0x00 "GPIOC_DMASK,GPIO Port C Data Output Write Mask Register"
|
|
bitfld.long 0x00 15. "DMASK15,Port [A/B/C/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT[n] bit" "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected"
|
|
bitfld.long 0x00 14. "DMASK14,Port [A/B/C/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT[n] bit" "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected"
|
|
newline
|
|
bitfld.long 0x00 13. "DMASK13,Port [A/B/C/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT[n] bit" "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected"
|
|
bitfld.long 0x00 12. "DMASK12,Port [A/B/C/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT[n] bit" "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected"
|
|
newline
|
|
bitfld.long 0x00 11. "DMASK11,Port [A/B/C/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT[n] bit" "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected"
|
|
bitfld.long 0x00 10. "DMASK10,Port [A/B/C/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT[n] bit" "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected"
|
|
newline
|
|
bitfld.long 0x00 9. "DMASK9,Port [A/B/C/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT[n] bit" "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected"
|
|
bitfld.long 0x00 8. "DMASK8,Port [A/B/C/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT[n] bit" "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected"
|
|
newline
|
|
bitfld.long 0x00 7. "DMASK7,Port [A/B/C/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT[n] bit" "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected"
|
|
bitfld.long 0x00 6. "DMASK6,Port [A/B/C/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT[n] bit" "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected"
|
|
newline
|
|
bitfld.long 0x00 5. "DMASK5,Port [A/B/C/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT[n] bit" "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected"
|
|
bitfld.long 0x00 4. "DMASK4,Port [A/B/C/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT[n] bit" "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected"
|
|
newline
|
|
bitfld.long 0x00 3. "DMASK3,Port [A/B/C/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT[n] bit" "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected"
|
|
bitfld.long 0x00 2. "DMASK2,Port [A/B/C/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT[n] bit" "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected"
|
|
newline
|
|
bitfld.long 0x00 1. "DMASK1,Port [A/B/C/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT[n] bit" "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected"
|
|
bitfld.long 0x00 0. "DMASK0,Port [A/B/C/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT[n] bit" "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected"
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "GPIOC_PIN,GPIO Port C Pin Value Register"
|
|
rbitfld.long 0x00 15. "PIN15,Port [A/B/C/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin" "0,1"
|
|
rbitfld.long 0x00 14. "PIN14,Port [A/B/C/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 13. "PIN13,Port [A/B/C/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin" "0,1"
|
|
rbitfld.long 0x00 12. "PIN12,Port [A/B/C/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 11. "PIN11,Port [A/B/C/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin" "0,1"
|
|
rbitfld.long 0x00 10. "PIN10,Port [A/B/C/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 9. "PIN9,Port [A/B/C/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin" "0,1"
|
|
rbitfld.long 0x00 8. "PIN8,Port [A/B/C/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 7. "PIN7,Port [A/B/C/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin" "0,1"
|
|
rbitfld.long 0x00 6. "PIN6,Port [A/B/C/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 5. "PIN5,Port [A/B/C/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin" "0,1"
|
|
rbitfld.long 0x00 4. "PIN4,Port [A/B/C/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 3. "PIN3,Port [A/B/C/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin" "0,1"
|
|
rbitfld.long 0x00 2. "PIN2,Port [A/B/C/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 1. "PIN1,Port [A/B/C/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin" "0,1"
|
|
rbitfld.long 0x00 0. "PIN0,Port [A/B/C/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin" "0,1"
|
|
group.long 0x94++0x03
|
|
line.long 0x00 "GPIOC_DBEN,GPIO Port C De-bounce Enable Register"
|
|
bitfld.long 0x00 15. "DBEN15,Port [A/B/C/E/F] Input Signal De-Bounce Enable Bit\nDBEN[n] is used to enable the de-bounce function for each corresponding bit" "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled"
|
|
bitfld.long 0x00 14. "DBEN14,Port [A/B/C/E/F] Input Signal De-Bounce Enable Bit\nDBEN[n] is used to enable the de-bounce function for each corresponding bit" "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled"
|
|
newline
|
|
bitfld.long 0x00 13. "DBEN13,Port [A/B/C/E/F] Input Signal De-Bounce Enable Bit\nDBEN[n] is used to enable the de-bounce function for each corresponding bit" "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled"
|
|
bitfld.long 0x00 12. "DBEN12,Port [A/B/C/E/F] Input Signal De-Bounce Enable Bit\nDBEN[n] is used to enable the de-bounce function for each corresponding bit" "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled"
|
|
newline
|
|
bitfld.long 0x00 11. "DBEN11,Port [A/B/C/E/F] Input Signal De-Bounce Enable Bit\nDBEN[n] is used to enable the de-bounce function for each corresponding bit" "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled"
|
|
bitfld.long 0x00 10. "DBEN10,Port [A/B/C/E/F] Input Signal De-Bounce Enable Bit\nDBEN[n] is used to enable the de-bounce function for each corresponding bit" "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled"
|
|
newline
|
|
bitfld.long 0x00 9. "DBEN9,Port [A/B/C/E/F] Input Signal De-Bounce Enable Bit\nDBEN[n] is used to enable the de-bounce function for each corresponding bit" "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled"
|
|
bitfld.long 0x00 8. "DBEN8,Port [A/B/C/E/F] Input Signal De-Bounce Enable Bit\nDBEN[n] is used to enable the de-bounce function for each corresponding bit" "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. "DBEN7,Port [A/B/C/E/F] Input Signal De-Bounce Enable Bit\nDBEN[n] is used to enable the de-bounce function for each corresponding bit" "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled"
|
|
bitfld.long 0x00 6. "DBEN6,Port [A/B/C/E/F] Input Signal De-Bounce Enable Bit\nDBEN[n] is used to enable the de-bounce function for each corresponding bit" "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled"
|
|
newline
|
|
bitfld.long 0x00 5. "DBEN5,Port [A/B/C/E/F] Input Signal De-Bounce Enable Bit\nDBEN[n] is used to enable the de-bounce function for each corresponding bit" "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled"
|
|
bitfld.long 0x00 4. "DBEN4,Port [A/B/C/E/F] Input Signal De-Bounce Enable Bit\nDBEN[n] is used to enable the de-bounce function for each corresponding bit" "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled"
|
|
newline
|
|
bitfld.long 0x00 3. "DBEN3,Port [A/B/C/E/F] Input Signal De-Bounce Enable Bit\nDBEN[n] is used to enable the de-bounce function for each corresponding bit" "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled"
|
|
bitfld.long 0x00 2. "DBEN2,Port [A/B/C/E/F] Input Signal De-Bounce Enable Bit\nDBEN[n] is used to enable the de-bounce function for each corresponding bit" "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. "DBEN1,Port [A/B/C/E/F] Input Signal De-Bounce Enable Bit\nDBEN[n] is used to enable the de-bounce function for each corresponding bit" "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled"
|
|
bitfld.long 0x00 0. "DBEN0,Port [A/B/C/E/F] Input Signal De-Bounce Enable Bit\nDBEN[n] is used to enable the de-bounce function for each corresponding bit" "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled"
|
|
group.long 0x98++0x03
|
|
line.long 0x00 "GPIOC_IMD,GPIO Port C Interrupt Mode Control Register"
|
|
bitfld.long 0x00 15. "IMD15,Port [A/B/C/E/F] Edge Or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
|
|
bitfld.long 0x00 14. "IMD14,Port [A/B/C/E/F] Edge Or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
|
|
newline
|
|
bitfld.long 0x00 13. "IMD13,Port [A/B/C/E/F] Edge Or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
|
|
bitfld.long 0x00 12. "IMD12,Port [A/B/C/E/F] Edge Or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
|
|
newline
|
|
bitfld.long 0x00 11. "IMD11,Port [A/B/C/E/F] Edge Or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
|
|
bitfld.long 0x00 10. "IMD10,Port [A/B/C/E/F] Edge Or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
|
|
newline
|
|
bitfld.long 0x00 9. "IMD9,Port [A/B/C/E/F] Edge Or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
|
|
bitfld.long 0x00 8. "IMD8,Port [A/B/C/E/F] Edge Or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
|
|
newline
|
|
bitfld.long 0x00 7. "IMD7,Port [A/B/C/E/F] Edge Or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
|
|
bitfld.long 0x00 6. "IMD6,Port [A/B/C/E/F] Edge Or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
|
|
newline
|
|
bitfld.long 0x00 5. "IMD5,Port [A/B/C/E/F] Edge Or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
|
|
bitfld.long 0x00 4. "IMD4,Port [A/B/C/E/F] Edge Or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
|
|
newline
|
|
bitfld.long 0x00 3. "IMD3,Port [A/B/C/E/F] Edge Or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
|
|
bitfld.long 0x00 2. "IMD2,Port [A/B/C/E/F] Edge Or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
|
|
newline
|
|
bitfld.long 0x00 1. "IMD1,Port [A/B/C/E/F] Edge Or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
|
|
bitfld.long 0x00 0. "IMD0,Port [A/B/C/E/F] Edge Or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
|
|
group.long 0x9C++0x03
|
|
line.long 0x00 "GPIOC_IEN,GPIO Port C Interrupt Enable Register"
|
|
bitfld.long 0x00 31. "IR_EN15,Port [A/B/C/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] level-high or low-to-high interrupt..,1: PIN[n] level-high or low-to-high interrupt.."
|
|
bitfld.long 0x00 30. "IR_EN14,Port [A/B/C/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] level-high or low-to-high interrupt..,1: PIN[n] level-high or low-to-high interrupt.."
|
|
newline
|
|
bitfld.long 0x00 29. "IR_EN13,Port [A/B/C/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] level-high or low-to-high interrupt..,1: PIN[n] level-high or low-to-high interrupt.."
|
|
bitfld.long 0x00 28. "IR_EN12,Port [A/B/C/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] level-high or low-to-high interrupt..,1: PIN[n] level-high or low-to-high interrupt.."
|
|
newline
|
|
bitfld.long 0x00 27. "IR_EN11,Port [A/B/C/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] level-high or low-to-high interrupt..,1: PIN[n] level-high or low-to-high interrupt.."
|
|
bitfld.long 0x00 26. "IR_EN10,Port [A/B/C/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] level-high or low-to-high interrupt..,1: PIN[n] level-high or low-to-high interrupt.."
|
|
newline
|
|
bitfld.long 0x00 25. "IR_EN9,Port [A/B/C/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] level-high or low-to-high interrupt..,1: PIN[n] level-high or low-to-high interrupt.."
|
|
bitfld.long 0x00 24. "IR_EN8,Port [A/B/C/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] level-high or low-to-high interrupt..,1: PIN[n] level-high or low-to-high interrupt.."
|
|
newline
|
|
bitfld.long 0x00 23. "IR_EN7,Port [A/B/C/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] level-high or low-to-high interrupt..,1: PIN[n] level-high or low-to-high interrupt.."
|
|
bitfld.long 0x00 22. "IR_EN6,Port [A/B/C/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] level-high or low-to-high interrupt..,1: PIN[n] level-high or low-to-high interrupt.."
|
|
newline
|
|
bitfld.long 0x00 21. "IR_EN5,Port [A/B/C/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] level-high or low-to-high interrupt..,1: PIN[n] level-high or low-to-high interrupt.."
|
|
bitfld.long 0x00 20. "IR_EN4,Port [A/B/C/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] level-high or low-to-high interrupt..,1: PIN[n] level-high or low-to-high interrupt.."
|
|
newline
|
|
bitfld.long 0x00 19. "IR_EN3,Port [A/B/C/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] level-high or low-to-high interrupt..,1: PIN[n] level-high or low-to-high interrupt.."
|
|
bitfld.long 0x00 18. "IR_EN2,Port [A/B/C/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] level-high or low-to-high interrupt..,1: PIN[n] level-high or low-to-high interrupt.."
|
|
newline
|
|
bitfld.long 0x00 17. "IR_EN1,Port [A/B/C/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] level-high or low-to-high interrupt..,1: PIN[n] level-high or low-to-high interrupt.."
|
|
bitfld.long 0x00 16. "IR_EN0,Port [A/B/C/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] level-high or low-to-high interrupt..,1: PIN[n] level-high or low-to-high interrupt.."
|
|
newline
|
|
bitfld.long 0x00 15. "IF_EN15,Port [A/B/C/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] state low-level or high-to-low change..,1: PIN[n] state low-level or high-to-low change.."
|
|
bitfld.long 0x00 14. "IF_EN14,Port [A/B/C/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] state low-level or high-to-low change..,1: PIN[n] state low-level or high-to-low change.."
|
|
newline
|
|
bitfld.long 0x00 13. "IF_EN13,Port [A/B/C/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] state low-level or high-to-low change..,1: PIN[n] state low-level or high-to-low change.."
|
|
bitfld.long 0x00 12. "IF_EN12,Port [A/B/C/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] state low-level or high-to-low change..,1: PIN[n] state low-level or high-to-low change.."
|
|
newline
|
|
bitfld.long 0x00 11. "IF_EN11,Port [A/B/C/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] state low-level or high-to-low change..,1: PIN[n] state low-level or high-to-low change.."
|
|
bitfld.long 0x00 10. "IF_EN10,Port [A/B/C/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] state low-level or high-to-low change..,1: PIN[n] state low-level or high-to-low change.."
|
|
newline
|
|
bitfld.long 0x00 9. "IF_EN9,Port [A/B/C/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] state low-level or high-to-low change..,1: PIN[n] state low-level or high-to-low change.."
|
|
bitfld.long 0x00 8. "IF_EN8,Port [A/B/C/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] state low-level or high-to-low change..,1: PIN[n] state low-level or high-to-low change.."
|
|
newline
|
|
bitfld.long 0x00 7. "IF_EN7,Port [A/B/C/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] state low-level or high-to-low change..,1: PIN[n] state low-level or high-to-low change.."
|
|
bitfld.long 0x00 6. "IF_EN6,Port [A/B/C/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] state low-level or high-to-low change..,1: PIN[n] state low-level or high-to-low change.."
|
|
newline
|
|
bitfld.long 0x00 5. "IF_EN5,Port [A/B/C/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] state low-level or high-to-low change..,1: PIN[n] state low-level or high-to-low change.."
|
|
bitfld.long 0x00 4. "IF_EN4,Port [A/B/C/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] state low-level or high-to-low change..,1: PIN[n] state low-level or high-to-low change.."
|
|
newline
|
|
bitfld.long 0x00 3. "IF_EN3,Port [A/B/C/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] state low-level or high-to-low change..,1: PIN[n] state low-level or high-to-low change.."
|
|
bitfld.long 0x00 2. "IF_EN2,Port [A/B/C/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] state low-level or high-to-low change..,1: PIN[n] state low-level or high-to-low change.."
|
|
newline
|
|
bitfld.long 0x00 1. "IF_EN1,Port [A/B/C/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] state low-level or high-to-low change..,1: PIN[n] state low-level or high-to-low change.."
|
|
bitfld.long 0x00 0. "IF_EN0,Port [A/B/C/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] state low-level or high-to-low change..,1: PIN[n] state low-level or high-to-low change.."
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "GPIOC_ISRC,GPIO Port C Interrupt Source Flag Register"
|
|
bitfld.long 0x00 15. "ISRC15,Port [A/B/C/E/F] Interrupt Source Flag\nRead :\nNote2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored" "0: No interrupt at GPIOx[n].\nNo action,1: GPIOx[n] generates an interrupt.\nClear the.."
|
|
bitfld.long 0x00 14. "ISRC14,Port [A/B/C/E/F] Interrupt Source Flag\nRead :\nNote2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored" "0: No interrupt at GPIOx[n].\nNo action,1: GPIOx[n] generates an interrupt.\nClear the.."
|
|
newline
|
|
bitfld.long 0x00 13. "ISRC13,Port [A/B/C/E/F] Interrupt Source Flag\nRead :\nNote2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored" "0: No interrupt at GPIOx[n].\nNo action,1: GPIOx[n] generates an interrupt.\nClear the.."
|
|
bitfld.long 0x00 12. "ISRC12,Port [A/B/C/E/F] Interrupt Source Flag\nRead :\nNote2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored" "0: No interrupt at GPIOx[n].\nNo action,1: GPIOx[n] generates an interrupt.\nClear the.."
|
|
newline
|
|
bitfld.long 0x00 11. "ISRC11,Port [A/B/C/E/F] Interrupt Source Flag\nRead :\nNote2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored" "0: No interrupt at GPIOx[n].\nNo action,1: GPIOx[n] generates an interrupt.\nClear the.."
|
|
bitfld.long 0x00 10. "ISRC10,Port [A/B/C/E/F] Interrupt Source Flag\nRead :\nNote2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored" "0: No interrupt at GPIOx[n].\nNo action,1: GPIOx[n] generates an interrupt.\nClear the.."
|
|
newline
|
|
bitfld.long 0x00 9. "ISRC9,Port [A/B/C/E/F] Interrupt Source Flag\nRead :\nNote2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored" "0: No interrupt at GPIOx[n].\nNo action,1: GPIOx[n] generates an interrupt.\nClear the.."
|
|
bitfld.long 0x00 8. "ISRC8,Port [A/B/C/E/F] Interrupt Source Flag\nRead :\nNote2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored" "0: No interrupt at GPIOx[n].\nNo action,1: GPIOx[n] generates an interrupt.\nClear the.."
|
|
newline
|
|
bitfld.long 0x00 7. "ISRC7,Port [A/B/C/E/F] Interrupt Source Flag\nRead :\nNote2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored" "0: No interrupt at GPIOx[n].\nNo action,1: GPIOx[n] generates an interrupt.\nClear the.."
|
|
bitfld.long 0x00 6. "ISRC6,Port [A/B/C/E/F] Interrupt Source Flag\nRead :\nNote2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored" "0: No interrupt at GPIOx[n].\nNo action,1: GPIOx[n] generates an interrupt.\nClear the.."
|
|
newline
|
|
bitfld.long 0x00 5. "ISRC5,Port [A/B/C/E/F] Interrupt Source Flag\nRead :\nNote2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored" "0: No interrupt at GPIOx[n].\nNo action,1: GPIOx[n] generates an interrupt.\nClear the.."
|
|
bitfld.long 0x00 4. "ISRC4,Port [A/B/C/E/F] Interrupt Source Flag\nRead :\nNote2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored" "0: No interrupt at GPIOx[n].\nNo action,1: GPIOx[n] generates an interrupt.\nClear the.."
|
|
newline
|
|
bitfld.long 0x00 3. "ISRC3,Port [A/B/C/E/F] Interrupt Source Flag\nRead :\nNote2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored" "0: No interrupt at GPIOx[n].\nNo action,1: GPIOx[n] generates an interrupt.\nClear the.."
|
|
bitfld.long 0x00 2. "ISRC2,Port [A/B/C/E/F] Interrupt Source Flag\nRead :\nNote2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored" "0: No interrupt at GPIOx[n].\nNo action,1: GPIOx[n] generates an interrupt.\nClear the.."
|
|
newline
|
|
bitfld.long 0x00 1. "ISRC1,Port [A/B/C/E/F] Interrupt Source Flag\nRead :\nNote2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored" "0: No interrupt at GPIOx[n].\nNo action,1: GPIOx[n] generates an interrupt.\nClear the.."
|
|
bitfld.long 0x00 0. "ISRC0,Port [A/B/C/E/F] Interrupt Source Flag\nRead :\nNote2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored" "0: No interrupt at GPIOx[n].\nNo action,1: GPIOx[n] generates an interrupt.\nClear the.."
|
|
group.long 0xC0++0x03
|
|
line.long 0x00 "GPIOD_PMD,GPIO Port D Pin I/O Mode Control Register"
|
|
group.long 0xC4++0x03
|
|
line.long 0x00 "GPIOD_OFFD,GPIO Port D Pin Digital Input Path Disable Register"
|
|
group.long 0xC8++0x03
|
|
line.long 0x00 "GPIOD_DOUT,GPIO Port D Data Output Value Register"
|
|
group.long 0xCC++0x03
|
|
line.long 0x00 "GPIOD_DMASK,GPIO Port D Data Output Write Mask Register"
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "GPIOE_PMD,GPIO Port E Pin I/O Mode Control Register"
|
|
bitfld.long 0x00 30.--31. "PMD15,GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nNote3: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored" "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,2: GPIO port [n] pin is in Open-drain Output mode,3: GPIO port [n] pin is in Quasi-bidirectional.."
|
|
bitfld.long 0x00 28.--29. "PMD14,GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nNote3: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored" "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,2: GPIO port [n] pin is in Open-drain Output mode,3: GPIO port [n] pin is in Quasi-bidirectional.."
|
|
newline
|
|
bitfld.long 0x00 26.--27. "PMD13,GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nNote3: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored" "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,2: GPIO port [n] pin is in Open-drain Output mode,3: GPIO port [n] pin is in Quasi-bidirectional.."
|
|
bitfld.long 0x00 24.--25. "PMD12,GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nNote3: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored" "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,2: GPIO port [n] pin is in Open-drain Output mode,3: GPIO port [n] pin is in Quasi-bidirectional.."
|
|
newline
|
|
bitfld.long 0x00 22.--23. "PMD11,GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nNote3: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored" "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,2: GPIO port [n] pin is in Open-drain Output mode,3: GPIO port [n] pin is in Quasi-bidirectional.."
|
|
bitfld.long 0x00 20.--21. "PMD10,GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nNote3: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored" "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,2: GPIO port [n] pin is in Open-drain Output mode,3: GPIO port [n] pin is in Quasi-bidirectional.."
|
|
newline
|
|
bitfld.long 0x00 18.--19. "PMD9,GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nNote3: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored" "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,2: GPIO port [n] pin is in Open-drain Output mode,3: GPIO port [n] pin is in Quasi-bidirectional.."
|
|
bitfld.long 0x00 16.--17. "PMD8,GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nNote3: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored" "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,2: GPIO port [n] pin is in Open-drain Output mode,3: GPIO port [n] pin is in Quasi-bidirectional.."
|
|
newline
|
|
bitfld.long 0x00 14.--15. "PMD7,GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nNote3: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored" "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,2: GPIO port [n] pin is in Open-drain Output mode,3: GPIO port [n] pin is in Quasi-bidirectional.."
|
|
bitfld.long 0x00 12.--13. "PMD6,GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nNote3: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored" "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,2: GPIO port [n] pin is in Open-drain Output mode,3: GPIO port [n] pin is in Quasi-bidirectional.."
|
|
newline
|
|
bitfld.long 0x00 10.--11. "PMD5,GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nNote3: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored" "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,2: GPIO port [n] pin is in Open-drain Output mode,3: GPIO port [n] pin is in Quasi-bidirectional.."
|
|
bitfld.long 0x00 8.--9. "PMD4,GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nNote3: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored" "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,2: GPIO port [n] pin is in Open-drain Output mode,3: GPIO port [n] pin is in Quasi-bidirectional.."
|
|
newline
|
|
bitfld.long 0x00 6.--7. "PMD3,GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nNote3: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored" "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,2: GPIO port [n] pin is in Open-drain Output mode,3: GPIO port [n] pin is in Quasi-bidirectional.."
|
|
bitfld.long 0x00 4.--5. "PMD2,GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nNote3: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored" "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,2: GPIO port [n] pin is in Open-drain Output mode,3: GPIO port [n] pin is in Quasi-bidirectional.."
|
|
newline
|
|
bitfld.long 0x00 2.--3. "PMD1,GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nNote3: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored" "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,2: GPIO port [n] pin is in Open-drain Output mode,3: GPIO port [n] pin is in Quasi-bidirectional.."
|
|
bitfld.long 0x00 0.--1. "PMD0,GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nNote3: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored" "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,2: GPIO port [n] pin is in Open-drain Output mode,3: GPIO port [n] pin is in Quasi-bidirectional.."
|
|
group.long 0x104++0x03
|
|
line.long 0x00 "GPIOE_OFFD,GPIO Port E Pin Digital Input Path Disable Register"
|
|
hexmask.long.word 0x00 16.--31. 1. "OFFD,GPIOx Pin[N] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding GPIO pin is disabled"
|
|
group.long 0x108++0x03
|
|
line.long 0x00 "GPIOE_DOUT,GPIO Port E Data Output Value Register"
|
|
bitfld.long 0x00 15. "DOUT15,GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode.\nNote2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored" "0: GPIO port [A/B/C/E/F] Pin[n] will drive Low..,1: GPIO port [A/B/C/E/F] Pin[n] will drive High.."
|
|
bitfld.long 0x00 14. "DOUT14,GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode.\nNote2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored" "0: GPIO port [A/B/C/E/F] Pin[n] will drive Low..,1: GPIO port [A/B/C/E/F] Pin[n] will drive High.."
|
|
newline
|
|
bitfld.long 0x00 13. "DOUT13,GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode.\nNote2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored" "0: GPIO port [A/B/C/E/F] Pin[n] will drive Low..,1: GPIO port [A/B/C/E/F] Pin[n] will drive High.."
|
|
bitfld.long 0x00 12. "DOUT12,GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode.\nNote2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored" "0: GPIO port [A/B/C/E/F] Pin[n] will drive Low..,1: GPIO port [A/B/C/E/F] Pin[n] will drive High.."
|
|
newline
|
|
bitfld.long 0x00 11. "DOUT11,GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode.\nNote2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored" "0: GPIO port [A/B/C/E/F] Pin[n] will drive Low..,1: GPIO port [A/B/C/E/F] Pin[n] will drive High.."
|
|
bitfld.long 0x00 10. "DOUT10,GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode.\nNote2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored" "0: GPIO port [A/B/C/E/F] Pin[n] will drive Low..,1: GPIO port [A/B/C/E/F] Pin[n] will drive High.."
|
|
newline
|
|
bitfld.long 0x00 9. "DOUT9,GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode.\nNote2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored" "0: GPIO port [A/B/C/E/F] Pin[n] will drive Low..,1: GPIO port [A/B/C/E/F] Pin[n] will drive High.."
|
|
bitfld.long 0x00 8. "DOUT8,GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode.\nNote2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored" "0: GPIO port [A/B/C/E/F] Pin[n] will drive Low..,1: GPIO port [A/B/C/E/F] Pin[n] will drive High.."
|
|
newline
|
|
bitfld.long 0x00 7. "DOUT7,GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode.\nNote2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored" "0: GPIO port [A/B/C/E/F] Pin[n] will drive Low..,1: GPIO port [A/B/C/E/F] Pin[n] will drive High.."
|
|
bitfld.long 0x00 6. "DOUT6,GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode.\nNote2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored" "0: GPIO port [A/B/C/E/F] Pin[n] will drive Low..,1: GPIO port [A/B/C/E/F] Pin[n] will drive High.."
|
|
newline
|
|
bitfld.long 0x00 5. "DOUT5,GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode.\nNote2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored" "0: GPIO port [A/B/C/E/F] Pin[n] will drive Low..,1: GPIO port [A/B/C/E/F] Pin[n] will drive High.."
|
|
bitfld.long 0x00 4. "DOUT4,GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode.\nNote2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored" "0: GPIO port [A/B/C/E/F] Pin[n] will drive Low..,1: GPIO port [A/B/C/E/F] Pin[n] will drive High.."
|
|
newline
|
|
bitfld.long 0x00 3. "DOUT3,GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode.\nNote2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored" "0: GPIO port [A/B/C/E/F] Pin[n] will drive Low..,1: GPIO port [A/B/C/E/F] Pin[n] will drive High.."
|
|
bitfld.long 0x00 2. "DOUT2,GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode.\nNote2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored" "0: GPIO port [A/B/C/E/F] Pin[n] will drive Low..,1: GPIO port [A/B/C/E/F] Pin[n] will drive High.."
|
|
newline
|
|
bitfld.long 0x00 1. "DOUT1,GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode.\nNote2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored" "0: GPIO port [A/B/C/E/F] Pin[n] will drive Low..,1: GPIO port [A/B/C/E/F] Pin[n] will drive High.."
|
|
bitfld.long 0x00 0. "DOUT0,GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode.\nNote2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored" "0: GPIO port [A/B/C/E/F] Pin[n] will drive Low..,1: GPIO port [A/B/C/E/F] Pin[n] will drive High.."
|
|
group.long 0x10C++0x03
|
|
line.long 0x00 "GPIOE_DMASK,GPIO Port E Data Output Write Mask Register"
|
|
bitfld.long 0x00 15. "DMASK15,Port [A/B/C/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT[n] bit" "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected"
|
|
bitfld.long 0x00 14. "DMASK14,Port [A/B/C/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT[n] bit" "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected"
|
|
newline
|
|
bitfld.long 0x00 13. "DMASK13,Port [A/B/C/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT[n] bit" "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected"
|
|
bitfld.long 0x00 12. "DMASK12,Port [A/B/C/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT[n] bit" "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected"
|
|
newline
|
|
bitfld.long 0x00 11. "DMASK11,Port [A/B/C/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT[n] bit" "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected"
|
|
bitfld.long 0x00 10. "DMASK10,Port [A/B/C/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT[n] bit" "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected"
|
|
newline
|
|
bitfld.long 0x00 9. "DMASK9,Port [A/B/C/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT[n] bit" "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected"
|
|
bitfld.long 0x00 8. "DMASK8,Port [A/B/C/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT[n] bit" "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected"
|
|
newline
|
|
bitfld.long 0x00 7. "DMASK7,Port [A/B/C/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT[n] bit" "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected"
|
|
bitfld.long 0x00 6. "DMASK6,Port [A/B/C/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT[n] bit" "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected"
|
|
newline
|
|
bitfld.long 0x00 5. "DMASK5,Port [A/B/C/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT[n] bit" "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected"
|
|
bitfld.long 0x00 4. "DMASK4,Port [A/B/C/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT[n] bit" "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected"
|
|
newline
|
|
bitfld.long 0x00 3. "DMASK3,Port [A/B/C/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT[n] bit" "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected"
|
|
bitfld.long 0x00 2. "DMASK2,Port [A/B/C/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT[n] bit" "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected"
|
|
newline
|
|
bitfld.long 0x00 1. "DMASK1,Port [A/B/C/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT[n] bit" "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected"
|
|
bitfld.long 0x00 0. "DMASK0,Port [A/B/C/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT[n] bit" "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected"
|
|
group.long 0x110++0x03
|
|
line.long 0x00 "GPIOE_PIN,GPIO Port E Pin Value Register"
|
|
rbitfld.long 0x00 15. "PIN15,Port [A/B/C/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin" "0,1"
|
|
rbitfld.long 0x00 14. "PIN14,Port [A/B/C/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 13. "PIN13,Port [A/B/C/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin" "0,1"
|
|
rbitfld.long 0x00 12. "PIN12,Port [A/B/C/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 11. "PIN11,Port [A/B/C/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin" "0,1"
|
|
rbitfld.long 0x00 10. "PIN10,Port [A/B/C/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 9. "PIN9,Port [A/B/C/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin" "0,1"
|
|
rbitfld.long 0x00 8. "PIN8,Port [A/B/C/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 7. "PIN7,Port [A/B/C/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin" "0,1"
|
|
rbitfld.long 0x00 6. "PIN6,Port [A/B/C/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 5. "PIN5,Port [A/B/C/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin" "0,1"
|
|
rbitfld.long 0x00 4. "PIN4,Port [A/B/C/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 3. "PIN3,Port [A/B/C/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin" "0,1"
|
|
rbitfld.long 0x00 2. "PIN2,Port [A/B/C/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 1. "PIN1,Port [A/B/C/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin" "0,1"
|
|
rbitfld.long 0x00 0. "PIN0,Port [A/B/C/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin" "0,1"
|
|
group.long 0x114++0x03
|
|
line.long 0x00 "GPIOE_DBEN,GPIO Port E De-bounce Enable Register"
|
|
bitfld.long 0x00 15. "DBEN15,Port [A/B/C/E/F] Input Signal De-Bounce Enable Bit\nDBEN[n] is used to enable the de-bounce function for each corresponding bit" "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled"
|
|
bitfld.long 0x00 14. "DBEN14,Port [A/B/C/E/F] Input Signal De-Bounce Enable Bit\nDBEN[n] is used to enable the de-bounce function for each corresponding bit" "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled"
|
|
newline
|
|
bitfld.long 0x00 13. "DBEN13,Port [A/B/C/E/F] Input Signal De-Bounce Enable Bit\nDBEN[n] is used to enable the de-bounce function for each corresponding bit" "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled"
|
|
bitfld.long 0x00 12. "DBEN12,Port [A/B/C/E/F] Input Signal De-Bounce Enable Bit\nDBEN[n] is used to enable the de-bounce function for each corresponding bit" "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled"
|
|
newline
|
|
bitfld.long 0x00 11. "DBEN11,Port [A/B/C/E/F] Input Signal De-Bounce Enable Bit\nDBEN[n] is used to enable the de-bounce function for each corresponding bit" "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled"
|
|
bitfld.long 0x00 10. "DBEN10,Port [A/B/C/E/F] Input Signal De-Bounce Enable Bit\nDBEN[n] is used to enable the de-bounce function for each corresponding bit" "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled"
|
|
newline
|
|
bitfld.long 0x00 9. "DBEN9,Port [A/B/C/E/F] Input Signal De-Bounce Enable Bit\nDBEN[n] is used to enable the de-bounce function for each corresponding bit" "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled"
|
|
bitfld.long 0x00 8. "DBEN8,Port [A/B/C/E/F] Input Signal De-Bounce Enable Bit\nDBEN[n] is used to enable the de-bounce function for each corresponding bit" "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. "DBEN7,Port [A/B/C/E/F] Input Signal De-Bounce Enable Bit\nDBEN[n] is used to enable the de-bounce function for each corresponding bit" "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled"
|
|
bitfld.long 0x00 6. "DBEN6,Port [A/B/C/E/F] Input Signal De-Bounce Enable Bit\nDBEN[n] is used to enable the de-bounce function for each corresponding bit" "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled"
|
|
newline
|
|
bitfld.long 0x00 5. "DBEN5,Port [A/B/C/E/F] Input Signal De-Bounce Enable Bit\nDBEN[n] is used to enable the de-bounce function for each corresponding bit" "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled"
|
|
bitfld.long 0x00 4. "DBEN4,Port [A/B/C/E/F] Input Signal De-Bounce Enable Bit\nDBEN[n] is used to enable the de-bounce function for each corresponding bit" "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled"
|
|
newline
|
|
bitfld.long 0x00 3. "DBEN3,Port [A/B/C/E/F] Input Signal De-Bounce Enable Bit\nDBEN[n] is used to enable the de-bounce function for each corresponding bit" "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled"
|
|
bitfld.long 0x00 2. "DBEN2,Port [A/B/C/E/F] Input Signal De-Bounce Enable Bit\nDBEN[n] is used to enable the de-bounce function for each corresponding bit" "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. "DBEN1,Port [A/B/C/E/F] Input Signal De-Bounce Enable Bit\nDBEN[n] is used to enable the de-bounce function for each corresponding bit" "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled"
|
|
bitfld.long 0x00 0. "DBEN0,Port [A/B/C/E/F] Input Signal De-Bounce Enable Bit\nDBEN[n] is used to enable the de-bounce function for each corresponding bit" "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled"
|
|
group.long 0x118++0x03
|
|
line.long 0x00 "GPIOE_IMD,GPIO Port E Interrupt Mode Control Register"
|
|
bitfld.long 0x00 15. "IMD15,Port [A/B/C/E/F] Edge Or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
|
|
bitfld.long 0x00 14. "IMD14,Port [A/B/C/E/F] Edge Or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
|
|
newline
|
|
bitfld.long 0x00 13. "IMD13,Port [A/B/C/E/F] Edge Or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
|
|
bitfld.long 0x00 12. "IMD12,Port [A/B/C/E/F] Edge Or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
|
|
newline
|
|
bitfld.long 0x00 11. "IMD11,Port [A/B/C/E/F] Edge Or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
|
|
bitfld.long 0x00 10. "IMD10,Port [A/B/C/E/F] Edge Or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
|
|
newline
|
|
bitfld.long 0x00 9. "IMD9,Port [A/B/C/E/F] Edge Or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
|
|
bitfld.long 0x00 8. "IMD8,Port [A/B/C/E/F] Edge Or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
|
|
newline
|
|
bitfld.long 0x00 7. "IMD7,Port [A/B/C/E/F] Edge Or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
|
|
bitfld.long 0x00 6. "IMD6,Port [A/B/C/E/F] Edge Or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
|
|
newline
|
|
bitfld.long 0x00 5. "IMD5,Port [A/B/C/E/F] Edge Or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
|
|
bitfld.long 0x00 4. "IMD4,Port [A/B/C/E/F] Edge Or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
|
|
newline
|
|
bitfld.long 0x00 3. "IMD3,Port [A/B/C/E/F] Edge Or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
|
|
bitfld.long 0x00 2. "IMD2,Port [A/B/C/E/F] Edge Or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
|
|
newline
|
|
bitfld.long 0x00 1. "IMD1,Port [A/B/C/E/F] Edge Or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
|
|
bitfld.long 0x00 0. "IMD0,Port [A/B/C/E/F] Edge Or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
|
|
group.long 0x11C++0x03
|
|
line.long 0x00 "GPIOE_IEN,GPIO Port E Interrupt Enable Register"
|
|
bitfld.long 0x00 31. "IR_EN15,Port [A/B/C/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] level-high or low-to-high interrupt..,1: PIN[n] level-high or low-to-high interrupt.."
|
|
bitfld.long 0x00 30. "IR_EN14,Port [A/B/C/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] level-high or low-to-high interrupt..,1: PIN[n] level-high or low-to-high interrupt.."
|
|
newline
|
|
bitfld.long 0x00 29. "IR_EN13,Port [A/B/C/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] level-high or low-to-high interrupt..,1: PIN[n] level-high or low-to-high interrupt.."
|
|
bitfld.long 0x00 28. "IR_EN12,Port [A/B/C/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] level-high or low-to-high interrupt..,1: PIN[n] level-high or low-to-high interrupt.."
|
|
newline
|
|
bitfld.long 0x00 27. "IR_EN11,Port [A/B/C/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] level-high or low-to-high interrupt..,1: PIN[n] level-high or low-to-high interrupt.."
|
|
bitfld.long 0x00 26. "IR_EN10,Port [A/B/C/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] level-high or low-to-high interrupt..,1: PIN[n] level-high or low-to-high interrupt.."
|
|
newline
|
|
bitfld.long 0x00 25. "IR_EN9,Port [A/B/C/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] level-high or low-to-high interrupt..,1: PIN[n] level-high or low-to-high interrupt.."
|
|
bitfld.long 0x00 24. "IR_EN8,Port [A/B/C/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] level-high or low-to-high interrupt..,1: PIN[n] level-high or low-to-high interrupt.."
|
|
newline
|
|
bitfld.long 0x00 23. "IR_EN7,Port [A/B/C/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] level-high or low-to-high interrupt..,1: PIN[n] level-high or low-to-high interrupt.."
|
|
bitfld.long 0x00 22. "IR_EN6,Port [A/B/C/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] level-high or low-to-high interrupt..,1: PIN[n] level-high or low-to-high interrupt.."
|
|
newline
|
|
bitfld.long 0x00 21. "IR_EN5,Port [A/B/C/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] level-high or low-to-high interrupt..,1: PIN[n] level-high or low-to-high interrupt.."
|
|
bitfld.long 0x00 20. "IR_EN4,Port [A/B/C/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] level-high or low-to-high interrupt..,1: PIN[n] level-high or low-to-high interrupt.."
|
|
newline
|
|
bitfld.long 0x00 19. "IR_EN3,Port [A/B/C/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] level-high or low-to-high interrupt..,1: PIN[n] level-high or low-to-high interrupt.."
|
|
bitfld.long 0x00 18. "IR_EN2,Port [A/B/C/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] level-high or low-to-high interrupt..,1: PIN[n] level-high or low-to-high interrupt.."
|
|
newline
|
|
bitfld.long 0x00 17. "IR_EN1,Port [A/B/C/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] level-high or low-to-high interrupt..,1: PIN[n] level-high or low-to-high interrupt.."
|
|
bitfld.long 0x00 16. "IR_EN0,Port [A/B/C/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] level-high or low-to-high interrupt..,1: PIN[n] level-high or low-to-high interrupt.."
|
|
newline
|
|
bitfld.long 0x00 15. "IF_EN15,Port [A/B/C/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] state low-level or high-to-low change..,1: PIN[n] state low-level or high-to-low change.."
|
|
bitfld.long 0x00 14. "IF_EN14,Port [A/B/C/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] state low-level or high-to-low change..,1: PIN[n] state low-level or high-to-low change.."
|
|
newline
|
|
bitfld.long 0x00 13. "IF_EN13,Port [A/B/C/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] state low-level or high-to-low change..,1: PIN[n] state low-level or high-to-low change.."
|
|
bitfld.long 0x00 12. "IF_EN12,Port [A/B/C/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] state low-level or high-to-low change..,1: PIN[n] state low-level or high-to-low change.."
|
|
newline
|
|
bitfld.long 0x00 11. "IF_EN11,Port [A/B/C/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] state low-level or high-to-low change..,1: PIN[n] state low-level or high-to-low change.."
|
|
bitfld.long 0x00 10. "IF_EN10,Port [A/B/C/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] state low-level or high-to-low change..,1: PIN[n] state low-level or high-to-low change.."
|
|
newline
|
|
bitfld.long 0x00 9. "IF_EN9,Port [A/B/C/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] state low-level or high-to-low change..,1: PIN[n] state low-level or high-to-low change.."
|
|
bitfld.long 0x00 8. "IF_EN8,Port [A/B/C/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] state low-level or high-to-low change..,1: PIN[n] state low-level or high-to-low change.."
|
|
newline
|
|
bitfld.long 0x00 7. "IF_EN7,Port [A/B/C/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] state low-level or high-to-low change..,1: PIN[n] state low-level or high-to-low change.."
|
|
bitfld.long 0x00 6. "IF_EN6,Port [A/B/C/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] state low-level or high-to-low change..,1: PIN[n] state low-level or high-to-low change.."
|
|
newline
|
|
bitfld.long 0x00 5. "IF_EN5,Port [A/B/C/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] state low-level or high-to-low change..,1: PIN[n] state low-level or high-to-low change.."
|
|
bitfld.long 0x00 4. "IF_EN4,Port [A/B/C/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] state low-level or high-to-low change..,1: PIN[n] state low-level or high-to-low change.."
|
|
newline
|
|
bitfld.long 0x00 3. "IF_EN3,Port [A/B/C/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] state low-level or high-to-low change..,1: PIN[n] state low-level or high-to-low change.."
|
|
bitfld.long 0x00 2. "IF_EN2,Port [A/B/C/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] state low-level or high-to-low change..,1: PIN[n] state low-level or high-to-low change.."
|
|
newline
|
|
bitfld.long 0x00 1. "IF_EN1,Port [A/B/C/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] state low-level or high-to-low change..,1: PIN[n] state low-level or high-to-low change.."
|
|
bitfld.long 0x00 0. "IF_EN0,Port [A/B/C/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] state low-level or high-to-low change..,1: PIN[n] state low-level or high-to-low change.."
|
|
group.long 0x120++0x03
|
|
line.long 0x00 "GPIOE_ISRC,GPIO Port E Interrupt Source Flag Register"
|
|
bitfld.long 0x00 15. "ISRC15,Port [A/B/C/E/F] Interrupt Source Flag\nRead :\nNote2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored" "0: No interrupt at GPIOx[n].\nNo action,1: GPIOx[n] generates an interrupt.\nClear the.."
|
|
bitfld.long 0x00 14. "ISRC14,Port [A/B/C/E/F] Interrupt Source Flag\nRead :\nNote2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored" "0: No interrupt at GPIOx[n].\nNo action,1: GPIOx[n] generates an interrupt.\nClear the.."
|
|
newline
|
|
bitfld.long 0x00 13. "ISRC13,Port [A/B/C/E/F] Interrupt Source Flag\nRead :\nNote2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored" "0: No interrupt at GPIOx[n].\nNo action,1: GPIOx[n] generates an interrupt.\nClear the.."
|
|
bitfld.long 0x00 12. "ISRC12,Port [A/B/C/E/F] Interrupt Source Flag\nRead :\nNote2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored" "0: No interrupt at GPIOx[n].\nNo action,1: GPIOx[n] generates an interrupt.\nClear the.."
|
|
newline
|
|
bitfld.long 0x00 11. "ISRC11,Port [A/B/C/E/F] Interrupt Source Flag\nRead :\nNote2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored" "0: No interrupt at GPIOx[n].\nNo action,1: GPIOx[n] generates an interrupt.\nClear the.."
|
|
bitfld.long 0x00 10. "ISRC10,Port [A/B/C/E/F] Interrupt Source Flag\nRead :\nNote2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored" "0: No interrupt at GPIOx[n].\nNo action,1: GPIOx[n] generates an interrupt.\nClear the.."
|
|
newline
|
|
bitfld.long 0x00 9. "ISRC9,Port [A/B/C/E/F] Interrupt Source Flag\nRead :\nNote2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored" "0: No interrupt at GPIOx[n].\nNo action,1: GPIOx[n] generates an interrupt.\nClear the.."
|
|
bitfld.long 0x00 8. "ISRC8,Port [A/B/C/E/F] Interrupt Source Flag\nRead :\nNote2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored" "0: No interrupt at GPIOx[n].\nNo action,1: GPIOx[n] generates an interrupt.\nClear the.."
|
|
newline
|
|
bitfld.long 0x00 7. "ISRC7,Port [A/B/C/E/F] Interrupt Source Flag\nRead :\nNote2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored" "0: No interrupt at GPIOx[n].\nNo action,1: GPIOx[n] generates an interrupt.\nClear the.."
|
|
bitfld.long 0x00 6. "ISRC6,Port [A/B/C/E/F] Interrupt Source Flag\nRead :\nNote2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored" "0: No interrupt at GPIOx[n].\nNo action,1: GPIOx[n] generates an interrupt.\nClear the.."
|
|
newline
|
|
bitfld.long 0x00 5. "ISRC5,Port [A/B/C/E/F] Interrupt Source Flag\nRead :\nNote2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored" "0: No interrupt at GPIOx[n].\nNo action,1: GPIOx[n] generates an interrupt.\nClear the.."
|
|
bitfld.long 0x00 4. "ISRC4,Port [A/B/C/E/F] Interrupt Source Flag\nRead :\nNote2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored" "0: No interrupt at GPIOx[n].\nNo action,1: GPIOx[n] generates an interrupt.\nClear the.."
|
|
newline
|
|
bitfld.long 0x00 3. "ISRC3,Port [A/B/C/E/F] Interrupt Source Flag\nRead :\nNote2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored" "0: No interrupt at GPIOx[n].\nNo action,1: GPIOx[n] generates an interrupt.\nClear the.."
|
|
bitfld.long 0x00 2. "ISRC2,Port [A/B/C/E/F] Interrupt Source Flag\nRead :\nNote2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored" "0: No interrupt at GPIOx[n].\nNo action,1: GPIOx[n] generates an interrupt.\nClear the.."
|
|
newline
|
|
bitfld.long 0x00 1. "ISRC1,Port [A/B/C/E/F] Interrupt Source Flag\nRead :\nNote2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored" "0: No interrupt at GPIOx[n].\nNo action,1: GPIOx[n] generates an interrupt.\nClear the.."
|
|
bitfld.long 0x00 0. "ISRC0,Port [A/B/C/E/F] Interrupt Source Flag\nRead :\nNote2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored" "0: No interrupt at GPIOx[n].\nNo action,1: GPIOx[n] generates an interrupt.\nClear the.."
|
|
group.long 0x140++0x03
|
|
line.long 0x00 "GPIOF_PMD,GPIO Port F Pin I/O Mode Control Register"
|
|
bitfld.long 0x00 30.--31. "PMD15,GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nNote3: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored" "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,2: GPIO port [n] pin is in Open-drain Output mode,3: GPIO port [n] pin is in Quasi-bidirectional.."
|
|
bitfld.long 0x00 28.--29. "PMD14,GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nNote3: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored" "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,2: GPIO port [n] pin is in Open-drain Output mode,3: GPIO port [n] pin is in Quasi-bidirectional.."
|
|
newline
|
|
bitfld.long 0x00 26.--27. "PMD13,GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nNote3: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored" "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,2: GPIO port [n] pin is in Open-drain Output mode,3: GPIO port [n] pin is in Quasi-bidirectional.."
|
|
bitfld.long 0x00 24.--25. "PMD12,GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nNote3: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored" "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,2: GPIO port [n] pin is in Open-drain Output mode,3: GPIO port [n] pin is in Quasi-bidirectional.."
|
|
newline
|
|
bitfld.long 0x00 22.--23. "PMD11,GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nNote3: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored" "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,2: GPIO port [n] pin is in Open-drain Output mode,3: GPIO port [n] pin is in Quasi-bidirectional.."
|
|
bitfld.long 0x00 20.--21. "PMD10,GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nNote3: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored" "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,2: GPIO port [n] pin is in Open-drain Output mode,3: GPIO port [n] pin is in Quasi-bidirectional.."
|
|
newline
|
|
bitfld.long 0x00 18.--19. "PMD9,GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nNote3: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored" "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,2: GPIO port [n] pin is in Open-drain Output mode,3: GPIO port [n] pin is in Quasi-bidirectional.."
|
|
bitfld.long 0x00 16.--17. "PMD8,GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nNote3: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored" "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,2: GPIO port [n] pin is in Open-drain Output mode,3: GPIO port [n] pin is in Quasi-bidirectional.."
|
|
newline
|
|
bitfld.long 0x00 14.--15. "PMD7,GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nNote3: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored" "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,2: GPIO port [n] pin is in Open-drain Output mode,3: GPIO port [n] pin is in Quasi-bidirectional.."
|
|
bitfld.long 0x00 12.--13. "PMD6,GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nNote3: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored" "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,2: GPIO port [n] pin is in Open-drain Output mode,3: GPIO port [n] pin is in Quasi-bidirectional.."
|
|
newline
|
|
bitfld.long 0x00 10.--11. "PMD5,GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nNote3: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored" "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,2: GPIO port [n] pin is in Open-drain Output mode,3: GPIO port [n] pin is in Quasi-bidirectional.."
|
|
bitfld.long 0x00 8.--9. "PMD4,GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nNote3: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored" "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,2: GPIO port [n] pin is in Open-drain Output mode,3: GPIO port [n] pin is in Quasi-bidirectional.."
|
|
newline
|
|
bitfld.long 0x00 6.--7. "PMD3,GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nNote3: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored" "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,2: GPIO port [n] pin is in Open-drain Output mode,3: GPIO port [n] pin is in Quasi-bidirectional.."
|
|
bitfld.long 0x00 4.--5. "PMD2,GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nNote3: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored" "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,2: GPIO port [n] pin is in Open-drain Output mode,3: GPIO port [n] pin is in Quasi-bidirectional.."
|
|
newline
|
|
bitfld.long 0x00 2.--3. "PMD1,GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nNote3: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored" "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,2: GPIO port [n] pin is in Open-drain Output mode,3: GPIO port [n] pin is in Quasi-bidirectional.."
|
|
bitfld.long 0x00 0.--1. "PMD0,GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nNote3: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored" "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,2: GPIO port [n] pin is in Open-drain Output mode,3: GPIO port [n] pin is in Quasi-bidirectional.."
|
|
group.long 0x144++0x03
|
|
line.long 0x00 "GPIOF_OFFD,GPIO Port F Pin Digital Input Path Disable Register"
|
|
hexmask.long.word 0x00 16.--31. 1. "OFFD,GPIOx Pin[N] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding GPIO pin is disabled"
|
|
group.long 0x148++0x03
|
|
line.long 0x00 "GPIOF_DOUT,GPIO Port F Data Output Value Register"
|
|
bitfld.long 0x00 15. "DOUT15,GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode.\nNote2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored" "0: GPIO port [A/B/C/E/F] Pin[n] will drive Low..,1: GPIO port [A/B/C/E/F] Pin[n] will drive High.."
|
|
bitfld.long 0x00 14. "DOUT14,GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode.\nNote2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored" "0: GPIO port [A/B/C/E/F] Pin[n] will drive Low..,1: GPIO port [A/B/C/E/F] Pin[n] will drive High.."
|
|
newline
|
|
bitfld.long 0x00 13. "DOUT13,GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode.\nNote2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored" "0: GPIO port [A/B/C/E/F] Pin[n] will drive Low..,1: GPIO port [A/B/C/E/F] Pin[n] will drive High.."
|
|
bitfld.long 0x00 12. "DOUT12,GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode.\nNote2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored" "0: GPIO port [A/B/C/E/F] Pin[n] will drive Low..,1: GPIO port [A/B/C/E/F] Pin[n] will drive High.."
|
|
newline
|
|
bitfld.long 0x00 11. "DOUT11,GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode.\nNote2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored" "0: GPIO port [A/B/C/E/F] Pin[n] will drive Low..,1: GPIO port [A/B/C/E/F] Pin[n] will drive High.."
|
|
bitfld.long 0x00 10. "DOUT10,GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode.\nNote2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored" "0: GPIO port [A/B/C/E/F] Pin[n] will drive Low..,1: GPIO port [A/B/C/E/F] Pin[n] will drive High.."
|
|
newline
|
|
bitfld.long 0x00 9. "DOUT9,GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode.\nNote2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored" "0: GPIO port [A/B/C/E/F] Pin[n] will drive Low..,1: GPIO port [A/B/C/E/F] Pin[n] will drive High.."
|
|
bitfld.long 0x00 8. "DOUT8,GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode.\nNote2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored" "0: GPIO port [A/B/C/E/F] Pin[n] will drive Low..,1: GPIO port [A/B/C/E/F] Pin[n] will drive High.."
|
|
newline
|
|
bitfld.long 0x00 7. "DOUT7,GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode.\nNote2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored" "0: GPIO port [A/B/C/E/F] Pin[n] will drive Low..,1: GPIO port [A/B/C/E/F] Pin[n] will drive High.."
|
|
bitfld.long 0x00 6. "DOUT6,GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode.\nNote2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored" "0: GPIO port [A/B/C/E/F] Pin[n] will drive Low..,1: GPIO port [A/B/C/E/F] Pin[n] will drive High.."
|
|
newline
|
|
bitfld.long 0x00 5. "DOUT5,GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode.\nNote2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored" "0: GPIO port [A/B/C/E/F] Pin[n] will drive Low..,1: GPIO port [A/B/C/E/F] Pin[n] will drive High.."
|
|
bitfld.long 0x00 4. "DOUT4,GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode.\nNote2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored" "0: GPIO port [A/B/C/E/F] Pin[n] will drive Low..,1: GPIO port [A/B/C/E/F] Pin[n] will drive High.."
|
|
newline
|
|
bitfld.long 0x00 3. "DOUT3,GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode.\nNote2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored" "0: GPIO port [A/B/C/E/F] Pin[n] will drive Low..,1: GPIO port [A/B/C/E/F] Pin[n] will drive High.."
|
|
bitfld.long 0x00 2. "DOUT2,GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode.\nNote2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored" "0: GPIO port [A/B/C/E/F] Pin[n] will drive Low..,1: GPIO port [A/B/C/E/F] Pin[n] will drive High.."
|
|
newline
|
|
bitfld.long 0x00 1. "DOUT1,GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode.\nNote2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored" "0: GPIO port [A/B/C/E/F] Pin[n] will drive Low..,1: GPIO port [A/B/C/E/F] Pin[n] will drive High.."
|
|
bitfld.long 0x00 0. "DOUT0,GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output open-drain output or quasi-bidirectional mode.\nNote2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored" "0: GPIO port [A/B/C/E/F] Pin[n] will drive Low..,1: GPIO port [A/B/C/E/F] Pin[n] will drive High.."
|
|
group.long 0x14C++0x03
|
|
line.long 0x00 "GPIOF_DMASK,GPIO Port F Data Output Write Mask Register"
|
|
bitfld.long 0x00 15. "DMASK15,Port [A/B/C/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT[n] bit" "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected"
|
|
bitfld.long 0x00 14. "DMASK14,Port [A/B/C/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT[n] bit" "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected"
|
|
newline
|
|
bitfld.long 0x00 13. "DMASK13,Port [A/B/C/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT[n] bit" "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected"
|
|
bitfld.long 0x00 12. "DMASK12,Port [A/B/C/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT[n] bit" "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected"
|
|
newline
|
|
bitfld.long 0x00 11. "DMASK11,Port [A/B/C/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT[n] bit" "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected"
|
|
bitfld.long 0x00 10. "DMASK10,Port [A/B/C/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT[n] bit" "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected"
|
|
newline
|
|
bitfld.long 0x00 9. "DMASK9,Port [A/B/C/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT[n] bit" "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected"
|
|
bitfld.long 0x00 8. "DMASK8,Port [A/B/C/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT[n] bit" "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected"
|
|
newline
|
|
bitfld.long 0x00 7. "DMASK7,Port [A/B/C/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT[n] bit" "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected"
|
|
bitfld.long 0x00 6. "DMASK6,Port [A/B/C/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT[n] bit" "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected"
|
|
newline
|
|
bitfld.long 0x00 5. "DMASK5,Port [A/B/C/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT[n] bit" "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected"
|
|
bitfld.long 0x00 4. "DMASK4,Port [A/B/C/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT[n] bit" "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected"
|
|
newline
|
|
bitfld.long 0x00 3. "DMASK3,Port [A/B/C/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT[n] bit" "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected"
|
|
bitfld.long 0x00 2. "DMASK2,Port [A/B/C/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT[n] bit" "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected"
|
|
newline
|
|
bitfld.long 0x00 1. "DMASK1,Port [A/B/C/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT[n] bit" "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected"
|
|
bitfld.long 0x00 0. "DMASK0,Port [A/B/C/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT[n] bit" "0: Corresponding GPIOx_DOUT[n] bit can be updated,1: Corresponding GPIOx_DOUT[n] bit protected"
|
|
group.long 0x150++0x03
|
|
line.long 0x00 "GPIOF_PIN,GPIO Port F Pin Value Register"
|
|
rbitfld.long 0x00 15. "PIN15,Port [A/B/C/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin" "0,1"
|
|
rbitfld.long 0x00 14. "PIN14,Port [A/B/C/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 13. "PIN13,Port [A/B/C/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin" "0,1"
|
|
rbitfld.long 0x00 12. "PIN12,Port [A/B/C/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 11. "PIN11,Port [A/B/C/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin" "0,1"
|
|
rbitfld.long 0x00 10. "PIN10,Port [A/B/C/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 9. "PIN9,Port [A/B/C/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin" "0,1"
|
|
rbitfld.long 0x00 8. "PIN8,Port [A/B/C/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 7. "PIN7,Port [A/B/C/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin" "0,1"
|
|
rbitfld.long 0x00 6. "PIN6,Port [A/B/C/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 5. "PIN5,Port [A/B/C/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin" "0,1"
|
|
rbitfld.long 0x00 4. "PIN4,Port [A/B/C/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 3. "PIN3,Port [A/B/C/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin" "0,1"
|
|
rbitfld.long 0x00 2. "PIN2,Port [A/B/C/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 1. "PIN1,Port [A/B/C/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin" "0,1"
|
|
rbitfld.long 0x00 0. "PIN0,Port [A/B/C/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin" "0,1"
|
|
group.long 0x154++0x03
|
|
line.long 0x00 "GPIOF_DBEN,GPIO Port F De-bounce Enable Register"
|
|
bitfld.long 0x00 15. "DBEN15,Port [A/B/C/E/F] Input Signal De-Bounce Enable Bit\nDBEN[n] is used to enable the de-bounce function for each corresponding bit" "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled"
|
|
bitfld.long 0x00 14. "DBEN14,Port [A/B/C/E/F] Input Signal De-Bounce Enable Bit\nDBEN[n] is used to enable the de-bounce function for each corresponding bit" "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled"
|
|
newline
|
|
bitfld.long 0x00 13. "DBEN13,Port [A/B/C/E/F] Input Signal De-Bounce Enable Bit\nDBEN[n] is used to enable the de-bounce function for each corresponding bit" "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled"
|
|
bitfld.long 0x00 12. "DBEN12,Port [A/B/C/E/F] Input Signal De-Bounce Enable Bit\nDBEN[n] is used to enable the de-bounce function for each corresponding bit" "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled"
|
|
newline
|
|
bitfld.long 0x00 11. "DBEN11,Port [A/B/C/E/F] Input Signal De-Bounce Enable Bit\nDBEN[n] is used to enable the de-bounce function for each corresponding bit" "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled"
|
|
bitfld.long 0x00 10. "DBEN10,Port [A/B/C/E/F] Input Signal De-Bounce Enable Bit\nDBEN[n] is used to enable the de-bounce function for each corresponding bit" "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled"
|
|
newline
|
|
bitfld.long 0x00 9. "DBEN9,Port [A/B/C/E/F] Input Signal De-Bounce Enable Bit\nDBEN[n] is used to enable the de-bounce function for each corresponding bit" "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled"
|
|
bitfld.long 0x00 8. "DBEN8,Port [A/B/C/E/F] Input Signal De-Bounce Enable Bit\nDBEN[n] is used to enable the de-bounce function for each corresponding bit" "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. "DBEN7,Port [A/B/C/E/F] Input Signal De-Bounce Enable Bit\nDBEN[n] is used to enable the de-bounce function for each corresponding bit" "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled"
|
|
bitfld.long 0x00 6. "DBEN6,Port [A/B/C/E/F] Input Signal De-Bounce Enable Bit\nDBEN[n] is used to enable the de-bounce function for each corresponding bit" "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled"
|
|
newline
|
|
bitfld.long 0x00 5. "DBEN5,Port [A/B/C/E/F] Input Signal De-Bounce Enable Bit\nDBEN[n] is used to enable the de-bounce function for each corresponding bit" "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled"
|
|
bitfld.long 0x00 4. "DBEN4,Port [A/B/C/E/F] Input Signal De-Bounce Enable Bit\nDBEN[n] is used to enable the de-bounce function for each corresponding bit" "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled"
|
|
newline
|
|
bitfld.long 0x00 3. "DBEN3,Port [A/B/C/E/F] Input Signal De-Bounce Enable Bit\nDBEN[n] is used to enable the de-bounce function for each corresponding bit" "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled"
|
|
bitfld.long 0x00 2. "DBEN2,Port [A/B/C/E/F] Input Signal De-Bounce Enable Bit\nDBEN[n] is used to enable the de-bounce function for each corresponding bit" "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. "DBEN1,Port [A/B/C/E/F] Input Signal De-Bounce Enable Bit\nDBEN[n] is used to enable the de-bounce function for each corresponding bit" "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled"
|
|
bitfld.long 0x00 0. "DBEN0,Port [A/B/C/E/F] Input Signal De-Bounce Enable Bit\nDBEN[n] is used to enable the de-bounce function for each corresponding bit" "0: Bit[n] de-bounce function Disabled,1: Bit[n] de-bounce function Enabled"
|
|
group.long 0x158++0x03
|
|
line.long 0x00 "GPIOF_IMD,GPIO Port F Interrupt Mode Control Register"
|
|
bitfld.long 0x00 15. "IMD15,Port [A/B/C/E/F] Edge Or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
|
|
bitfld.long 0x00 14. "IMD14,Port [A/B/C/E/F] Edge Or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
|
|
newline
|
|
bitfld.long 0x00 13. "IMD13,Port [A/B/C/E/F] Edge Or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
|
|
bitfld.long 0x00 12. "IMD12,Port [A/B/C/E/F] Edge Or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
|
|
newline
|
|
bitfld.long 0x00 11. "IMD11,Port [A/B/C/E/F] Edge Or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
|
|
bitfld.long 0x00 10. "IMD10,Port [A/B/C/E/F] Edge Or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
|
|
newline
|
|
bitfld.long 0x00 9. "IMD9,Port [A/B/C/E/F] Edge Or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
|
|
bitfld.long 0x00 8. "IMD8,Port [A/B/C/E/F] Edge Or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
|
|
newline
|
|
bitfld.long 0x00 7. "IMD7,Port [A/B/C/E/F] Edge Or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
|
|
bitfld.long 0x00 6. "IMD6,Port [A/B/C/E/F] Edge Or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
|
|
newline
|
|
bitfld.long 0x00 5. "IMD5,Port [A/B/C/E/F] Edge Or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
|
|
bitfld.long 0x00 4. "IMD4,Port [A/B/C/E/F] Edge Or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
|
|
newline
|
|
bitfld.long 0x00 3. "IMD3,Port [A/B/C/E/F] Edge Or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
|
|
bitfld.long 0x00 2. "IMD2,Port [A/B/C/E/F] Edge Or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
|
|
newline
|
|
bitfld.long 0x00 1. "IMD1,Port [A/B/C/E/F] Edge Or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
|
|
bitfld.long 0x00 0. "IMD0,Port [A/B/C/E/F] Edge Or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
|
|
group.long 0x15C++0x03
|
|
line.long 0x00 "GPIOF_IEN,GPIO Port F Interrupt Enable Register"
|
|
bitfld.long 0x00 31. "IR_EN15,Port [A/B/C/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] level-high or low-to-high interrupt..,1: PIN[n] level-high or low-to-high interrupt.."
|
|
bitfld.long 0x00 30. "IR_EN14,Port [A/B/C/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] level-high or low-to-high interrupt..,1: PIN[n] level-high or low-to-high interrupt.."
|
|
newline
|
|
bitfld.long 0x00 29. "IR_EN13,Port [A/B/C/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] level-high or low-to-high interrupt..,1: PIN[n] level-high or low-to-high interrupt.."
|
|
bitfld.long 0x00 28. "IR_EN12,Port [A/B/C/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] level-high or low-to-high interrupt..,1: PIN[n] level-high or low-to-high interrupt.."
|
|
newline
|
|
bitfld.long 0x00 27. "IR_EN11,Port [A/B/C/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] level-high or low-to-high interrupt..,1: PIN[n] level-high or low-to-high interrupt.."
|
|
bitfld.long 0x00 26. "IR_EN10,Port [A/B/C/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] level-high or low-to-high interrupt..,1: PIN[n] level-high or low-to-high interrupt.."
|
|
newline
|
|
bitfld.long 0x00 25. "IR_EN9,Port [A/B/C/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] level-high or low-to-high interrupt..,1: PIN[n] level-high or low-to-high interrupt.."
|
|
bitfld.long 0x00 24. "IR_EN8,Port [A/B/C/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] level-high or low-to-high interrupt..,1: PIN[n] level-high or low-to-high interrupt.."
|
|
newline
|
|
bitfld.long 0x00 23. "IR_EN7,Port [A/B/C/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] level-high or low-to-high interrupt..,1: PIN[n] level-high or low-to-high interrupt.."
|
|
bitfld.long 0x00 22. "IR_EN6,Port [A/B/C/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] level-high or low-to-high interrupt..,1: PIN[n] level-high or low-to-high interrupt.."
|
|
newline
|
|
bitfld.long 0x00 21. "IR_EN5,Port [A/B/C/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] level-high or low-to-high interrupt..,1: PIN[n] level-high or low-to-high interrupt.."
|
|
bitfld.long 0x00 20. "IR_EN4,Port [A/B/C/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] level-high or low-to-high interrupt..,1: PIN[n] level-high or low-to-high interrupt.."
|
|
newline
|
|
bitfld.long 0x00 19. "IR_EN3,Port [A/B/C/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] level-high or low-to-high interrupt..,1: PIN[n] level-high or low-to-high interrupt.."
|
|
bitfld.long 0x00 18. "IR_EN2,Port [A/B/C/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] level-high or low-to-high interrupt..,1: PIN[n] level-high or low-to-high interrupt.."
|
|
newline
|
|
bitfld.long 0x00 17. "IR_EN1,Port [A/B/C/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] level-high or low-to-high interrupt..,1: PIN[n] level-high or low-to-high interrupt.."
|
|
bitfld.long 0x00 16. "IR_EN0,Port [A/B/C/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] level-high or low-to-high interrupt..,1: PIN[n] level-high or low-to-high interrupt.."
|
|
newline
|
|
bitfld.long 0x00 15. "IF_EN15,Port [A/B/C/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] state low-level or high-to-low change..,1: PIN[n] state low-level or high-to-low change.."
|
|
bitfld.long 0x00 14. "IF_EN14,Port [A/B/C/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] state low-level or high-to-low change..,1: PIN[n] state low-level or high-to-low change.."
|
|
newline
|
|
bitfld.long 0x00 13. "IF_EN13,Port [A/B/C/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] state low-level or high-to-low change..,1: PIN[n] state low-level or high-to-low change.."
|
|
bitfld.long 0x00 12. "IF_EN12,Port [A/B/C/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] state low-level or high-to-low change..,1: PIN[n] state low-level or high-to-low change.."
|
|
newline
|
|
bitfld.long 0x00 11. "IF_EN11,Port [A/B/C/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] state low-level or high-to-low change..,1: PIN[n] state low-level or high-to-low change.."
|
|
bitfld.long 0x00 10. "IF_EN10,Port [A/B/C/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] state low-level or high-to-low change..,1: PIN[n] state low-level or high-to-low change.."
|
|
newline
|
|
bitfld.long 0x00 9. "IF_EN9,Port [A/B/C/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] state low-level or high-to-low change..,1: PIN[n] state low-level or high-to-low change.."
|
|
bitfld.long 0x00 8. "IF_EN8,Port [A/B/C/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] state low-level or high-to-low change..,1: PIN[n] state low-level or high-to-low change.."
|
|
newline
|
|
bitfld.long 0x00 7. "IF_EN7,Port [A/B/C/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] state low-level or high-to-low change..,1: PIN[n] state low-level or high-to-low change.."
|
|
bitfld.long 0x00 6. "IF_EN6,Port [A/B/C/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] state low-level or high-to-low change..,1: PIN[n] state low-level or high-to-low change.."
|
|
newline
|
|
bitfld.long 0x00 5. "IF_EN5,Port [A/B/C/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] state low-level or high-to-low change..,1: PIN[n] state low-level or high-to-low change.."
|
|
bitfld.long 0x00 4. "IF_EN4,Port [A/B/C/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] state low-level or high-to-low change..,1: PIN[n] state low-level or high-to-low change.."
|
|
newline
|
|
bitfld.long 0x00 3. "IF_EN3,Port [A/B/C/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] state low-level or high-to-low change..,1: PIN[n] state low-level or high-to-low change.."
|
|
bitfld.long 0x00 2. "IF_EN2,Port [A/B/C/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] state low-level or high-to-low change..,1: PIN[n] state low-level or high-to-low change.."
|
|
newline
|
|
bitfld.long 0x00 1. "IF_EN1,Port [A/B/C/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] state low-level or high-to-low change..,1: PIN[n] state low-level or high-to-low change.."
|
|
bitfld.long 0x00 0. "IF_EN0,Port [A/B/C/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]" "0: PIN[n] state low-level or high-to-low change..,1: PIN[n] state low-level or high-to-low change.."
|
|
group.long 0x160++0x03
|
|
line.long 0x00 "GPIOF_ISRC,GPIO Port F Interrupt Source Flag Register"
|
|
bitfld.long 0x00 15. "ISRC15,Port [A/B/C/E/F] Interrupt Source Flag\nRead :\nNote2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored" "0: No interrupt at GPIOx[n].\nNo action,1: GPIOx[n] generates an interrupt.\nClear the.."
|
|
bitfld.long 0x00 14. "ISRC14,Port [A/B/C/E/F] Interrupt Source Flag\nRead :\nNote2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored" "0: No interrupt at GPIOx[n].\nNo action,1: GPIOx[n] generates an interrupt.\nClear the.."
|
|
newline
|
|
bitfld.long 0x00 13. "ISRC13,Port [A/B/C/E/F] Interrupt Source Flag\nRead :\nNote2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored" "0: No interrupt at GPIOx[n].\nNo action,1: GPIOx[n] generates an interrupt.\nClear the.."
|
|
bitfld.long 0x00 12. "ISRC12,Port [A/B/C/E/F] Interrupt Source Flag\nRead :\nNote2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored" "0: No interrupt at GPIOx[n].\nNo action,1: GPIOx[n] generates an interrupt.\nClear the.."
|
|
newline
|
|
bitfld.long 0x00 11. "ISRC11,Port [A/B/C/E/F] Interrupt Source Flag\nRead :\nNote2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored" "0: No interrupt at GPIOx[n].\nNo action,1: GPIOx[n] generates an interrupt.\nClear the.."
|
|
bitfld.long 0x00 10. "ISRC10,Port [A/B/C/E/F] Interrupt Source Flag\nRead :\nNote2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored" "0: No interrupt at GPIOx[n].\nNo action,1: GPIOx[n] generates an interrupt.\nClear the.."
|
|
newline
|
|
bitfld.long 0x00 9. "ISRC9,Port [A/B/C/E/F] Interrupt Source Flag\nRead :\nNote2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored" "0: No interrupt at GPIOx[n].\nNo action,1: GPIOx[n] generates an interrupt.\nClear the.."
|
|
bitfld.long 0x00 8. "ISRC8,Port [A/B/C/E/F] Interrupt Source Flag\nRead :\nNote2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored" "0: No interrupt at GPIOx[n].\nNo action,1: GPIOx[n] generates an interrupt.\nClear the.."
|
|
newline
|
|
bitfld.long 0x00 7. "ISRC7,Port [A/B/C/E/F] Interrupt Source Flag\nRead :\nNote2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored" "0: No interrupt at GPIOx[n].\nNo action,1: GPIOx[n] generates an interrupt.\nClear the.."
|
|
bitfld.long 0x00 6. "ISRC6,Port [A/B/C/E/F] Interrupt Source Flag\nRead :\nNote2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored" "0: No interrupt at GPIOx[n].\nNo action,1: GPIOx[n] generates an interrupt.\nClear the.."
|
|
newline
|
|
bitfld.long 0x00 5. "ISRC5,Port [A/B/C/E/F] Interrupt Source Flag\nRead :\nNote2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored" "0: No interrupt at GPIOx[n].\nNo action,1: GPIOx[n] generates an interrupt.\nClear the.."
|
|
bitfld.long 0x00 4. "ISRC4,Port [A/B/C/E/F] Interrupt Source Flag\nRead :\nNote2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored" "0: No interrupt at GPIOx[n].\nNo action,1: GPIOx[n] generates an interrupt.\nClear the.."
|
|
newline
|
|
bitfld.long 0x00 3. "ISRC3,Port [A/B/C/E/F] Interrupt Source Flag\nRead :\nNote2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored" "0: No interrupt at GPIOx[n].\nNo action,1: GPIOx[n] generates an interrupt.\nClear the.."
|
|
bitfld.long 0x00 2. "ISRC2,Port [A/B/C/E/F] Interrupt Source Flag\nRead :\nNote2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored" "0: No interrupt at GPIOx[n].\nNo action,1: GPIOx[n] generates an interrupt.\nClear the.."
|
|
newline
|
|
bitfld.long 0x00 1. "ISRC1,Port [A/B/C/E/F] Interrupt Source Flag\nRead :\nNote2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored" "0: No interrupt at GPIOx[n].\nNo action,1: GPIOx[n] generates an interrupt.\nClear the.."
|
|
bitfld.long 0x00 0. "ISRC0,Port [A/B/C/E/F] Interrupt Source Flag\nRead :\nNote2: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored" "0: No interrupt at GPIOx[n].\nNo action,1: GPIOx[n] generates an interrupt.\nClear the.."
|
|
group.long 0x180++0x03
|
|
line.long 0x00 "DBNCECON,External Interrupt De-bounce Control Register"
|
|
bitfld.long 0x00 5. "ICLK_ON,Interrupt Clock On Mode\nIt is recommended to disable this bit to save system power if no special application concern" "0: Edge detection circuit is active only if I/O..,1: All I/O pins edge detection circuit is always.."
|
|
bitfld.long 0x00 4. "DBCLKSRC,De-Bounce Counter Clock Source Selection" "0: De-bounce counter clock source is the HCLK,1: De-bounce counter clock source is the.."
|
|
newline
|
|
bitfld.long 0x00 0.--3. "DBCLKSEL,De-Bounce Sampling Cycle Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x200++0x03
|
|
line.long 0x00 "PA0_PDIO,GPIO PA.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "Pxn_PDIO,GPIO Px.N Pin Data Input/Output\nWrite this bit can control one GPIO pin output value\nNote3: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x204++0x03
|
|
line.long 0x00 "PA1_PDIO,GPIO PA.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "Pxn_PDIO,GPIO Px.N Pin Data Input/Output\nWrite this bit can control one GPIO pin output value\nNote3: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x208++0x03
|
|
line.long 0x00 "PA2_PDIO,GPIO PA.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "Pxn_PDIO,GPIO Px.N Pin Data Input/Output\nWrite this bit can control one GPIO pin output value\nNote3: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x20C++0x03
|
|
line.long 0x00 "PA3_PDIO,GPIO PA.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "Pxn_PDIO,GPIO Px.N Pin Data Input/Output\nWrite this bit can control one GPIO pin output value\nNote3: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x210++0x03
|
|
line.long 0x00 "PA4_PDIO,GPIO PA.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "Pxn_PDIO,GPIO Px.N Pin Data Input/Output\nWrite this bit can control one GPIO pin output value\nNote3: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x214++0x03
|
|
line.long 0x00 "PA5_PDIO,GPIO PA.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "Pxn_PDIO,GPIO Px.N Pin Data Input/Output\nWrite this bit can control one GPIO pin output value\nNote3: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x218++0x03
|
|
line.long 0x00 "PA6_PDIO,GPIO PA.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "Pxn_PDIO,GPIO Px.N Pin Data Input/Output\nWrite this bit can control one GPIO pin output value\nNote3: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x21C++0x03
|
|
line.long 0x00 "PA7_PDIO,GPIO PA.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "Pxn_PDIO,GPIO Px.N Pin Data Input/Output\nWrite this bit can control one GPIO pin output value\nNote3: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x220++0x03
|
|
line.long 0x00 "PA8_PDIO,GPIO PA.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "Pxn_PDIO,GPIO Px.N Pin Data Input/Output\nWrite this bit can control one GPIO pin output value\nNote3: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x224++0x03
|
|
line.long 0x00 "PA9_PDIO,GPIO PA.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "Pxn_PDIO,GPIO Px.N Pin Data Input/Output\nWrite this bit can control one GPIO pin output value\nNote3: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x228++0x03
|
|
line.long 0x00 "PA10_PDIO,GPIO PA.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "Pxn_PDIO,GPIO Px.N Pin Data Input/Output\nWrite this bit can control one GPIO pin output value\nNote3: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x22C++0x03
|
|
line.long 0x00 "PA11_PDIO,GPIO PA.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "Pxn_PDIO,GPIO Px.N Pin Data Input/Output\nWrite this bit can control one GPIO pin output value\nNote3: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x230++0x03
|
|
line.long 0x00 "PA12_PDIO,GPIO PA.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "Pxn_PDIO,GPIO Px.N Pin Data Input/Output\nWrite this bit can control one GPIO pin output value\nNote3: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x234++0x03
|
|
line.long 0x00 "PA13_PDIO,GPIO PA.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "Pxn_PDIO,GPIO Px.N Pin Data Input/Output\nWrite this bit can control one GPIO pin output value\nNote3: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x238++0x03
|
|
line.long 0x00 "PA14_PDIO,GPIO PA.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "Pxn_PDIO,GPIO Px.N Pin Data Input/Output\nWrite this bit can control one GPIO pin output value\nNote3: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x23C++0x03
|
|
line.long 0x00 "PA15_PDIO,GPIO PA.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "Pxn_PDIO,GPIO Px.N Pin Data Input/Output\nWrite this bit can control one GPIO pin output value\nNote3: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x240++0x03
|
|
line.long 0x00 "PB0_PDIO,GPIO PB.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "Pxn_PDIO,GPIO Px.N Pin Data Input/Output\nWrite this bit can control one GPIO pin output value\nNote3: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x244++0x03
|
|
line.long 0x00 "PB1_PDIO,GPIO PB.n Pin Data Input/Output Register"
|
|
group.long 0x248++0x03
|
|
line.long 0x00 "PB2_PDIO,GPIO PB.n Pin Data Input/Output Register"
|
|
group.long 0x24C++0x03
|
|
line.long 0x00 "PB3_PDIO,GPIO PB.n Pin Data Input/Output Register"
|
|
group.long 0x250++0x03
|
|
line.long 0x00 "PB4_PDIO,GPIO PB.n Pin Data Input/Output Register"
|
|
group.long 0x254++0x03
|
|
line.long 0x00 "PB5_PDIO,GPIO PB.n Pin Data Input/Output Register"
|
|
group.long 0x258++0x03
|
|
line.long 0x00 "PB6_PDIO,GPIO PB.n Pin Data Input/Output Register"
|
|
group.long 0x25C++0x03
|
|
line.long 0x00 "PB7_PDIO,GPIO PB.n Pin Data Input/Output Register"
|
|
group.long 0x260++0x03
|
|
line.long 0x00 "PB8_PDIO,GPIO PB.n Pin Data Input/Output Register"
|
|
group.long 0x264++0x03
|
|
line.long 0x00 "PB9_PDIO,GPIO PB.n Pin Data Input/Output Register"
|
|
group.long 0x268++0x03
|
|
line.long 0x00 "PB10_PDIO,GPIO PB.n Pin Data Input/Output Register"
|
|
group.long 0x26C++0x03
|
|
line.long 0x00 "PB11_PDIO,GPIO PB.n Pin Data Input/Output Register"
|
|
group.long 0x270++0x03
|
|
line.long 0x00 "PB12_PDIO,GPIO PB.n Pin Data Input/Output Register"
|
|
group.long 0x274++0x03
|
|
line.long 0x00 "PB13_PDIO,GPIO PB.n Pin Data Input/Output Register"
|
|
group.long 0x278++0x03
|
|
line.long 0x00 "PB14_PDIO,GPIO PB.n Pin Data Input/Output Register"
|
|
group.long 0x27C++0x03
|
|
line.long 0x00 "PB15_PDIO,GPIO PB.n Pin Data Input/Output Register"
|
|
group.long 0x280++0x03
|
|
line.long 0x00 "PC0_PDIO,GPIO PC.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "Pxn_PDIO,GPIO Px.N Pin Data Input/Output\nWrite this bit can control one GPIO pin output value\nNote3: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x284++0x03
|
|
line.long 0x00 "PC1_PDIO,GPIO PC.n Pin Data Input/Output Register"
|
|
group.long 0x288++0x03
|
|
line.long 0x00 "PC2_PDIO,GPIO PC.n Pin Data Input/Output Register"
|
|
group.long 0x28C++0x03
|
|
line.long 0x00 "PC3_PDIO,GPIO PC.n Pin Data Input/Output Register"
|
|
group.long 0x290++0x03
|
|
line.long 0x00 "PC4_PDIO,GPIO PC.n Pin Data Input/Output Register"
|
|
group.long 0x294++0x03
|
|
line.long 0x00 "PC5_PDIO,GPIO PC.n Pin Data Input/Output Register"
|
|
group.long 0x298++0x03
|
|
line.long 0x00 "PC6_PDIO,GPIO PC.n Pin Data Input/Output Register"
|
|
group.long 0x29C++0x03
|
|
line.long 0x00 "PC7_PDIO,GPIO PC.n Pin Data Input/Output Register"
|
|
group.long 0x2A0++0x03
|
|
line.long 0x00 "PC8_PDIO,GPIO PC.n Pin Data Input/Output Register"
|
|
group.long 0x2A4++0x03
|
|
line.long 0x00 "PC9_PDIO,GPIO PC.n Pin Data Input/Output Register"
|
|
group.long 0x2A8++0x03
|
|
line.long 0x00 "PC10_PDIO,GPIO PC.n Pin Data Input/Output Register"
|
|
group.long 0x2AC++0x03
|
|
line.long 0x00 "PC11_PDIO,GPIO PC.n Pin Data Input/Output Register"
|
|
group.long 0x2B0++0x03
|
|
line.long 0x00 "PC12_PDIO,GPIO PC.n Pin Data Input/Output Register"
|
|
group.long 0x2B4++0x03
|
|
line.long 0x00 "PC13_PDIO,GPIO PC.n Pin Data Input/Output Register"
|
|
group.long 0x2B8++0x03
|
|
line.long 0x00 "PC14_PDIO,GPIO PC.n Pin Data Input/Output Register"
|
|
group.long 0x2BC++0x03
|
|
line.long 0x00 "PC15_PDIO,GPIO PC.n Pin Data Input/Output Register"
|
|
group.long 0x300++0x03
|
|
line.long 0x00 "PE0_PDIO,GPIO PE.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "Pxn_PDIO,GPIO Px.N Pin Data Input/Output\nWrite this bit can control one GPIO pin output value\nNote3: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x304++0x03
|
|
line.long 0x00 "PE1_PDIO,GPIO PE.n Pin Data Input/Output Register"
|
|
group.long 0x308++0x03
|
|
line.long 0x00 "PE2_PDIO,GPIO PE.n Pin Data Input/Output Register"
|
|
group.long 0x30C++0x03
|
|
line.long 0x00 "PE3_PDIO,GPIO PE.n Pin Data Input/Output Register"
|
|
group.long 0x310++0x03
|
|
line.long 0x00 "PE4_PDIO,GPIO PE.n Pin Data Input/Output Register"
|
|
group.long 0x314++0x03
|
|
line.long 0x00 "PE5_PDIO,GPIO PE.n Pin Data Input/Output Register"
|
|
group.long 0x318++0x03
|
|
line.long 0x00 "PE6_PDIO,GPIO PE.n Pin Data Input/Output Register"
|
|
group.long 0x31C++0x03
|
|
line.long 0x00 "PE7_PDIO,GPIO PE.n Pin Data Input/Output Register"
|
|
group.long 0x320++0x03
|
|
line.long 0x00 "PE8_PDIO,GPIO PE.n Pin Data Input/Output Register"
|
|
group.long 0x324++0x03
|
|
line.long 0x00 "PE9_PDIO,GPIO PE.n Pin Data Input/Output Register"
|
|
group.long 0x328++0x03
|
|
line.long 0x00 "PE10_PDIO,GPIO PE.n Pin Data Input/Output Register"
|
|
group.long 0x32C++0x03
|
|
line.long 0x00 "PE11_PDIO,GPIO PE.n Pin Data Input/Output Register"
|
|
group.long 0x330++0x03
|
|
line.long 0x00 "PE12_PDIO,GPIO PE.n Pin Data Input/Output Register"
|
|
group.long 0x334++0x03
|
|
line.long 0x00 "PE13_PDIO,GPIO PE.n Pin Data Input/Output Register"
|
|
group.long 0x338++0x03
|
|
line.long 0x00 "PE14_PDIO,GPIO PE.n Pin Data Input/Output Register"
|
|
group.long 0x33C++0x03
|
|
line.long 0x00 "PE15_PDIO,GPIO PE.n Pin Data Input/Output Register"
|
|
group.long 0x340++0x03
|
|
line.long 0x00 "PF0_PDIO,GPIO PF.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "Pxn_PDIO,GPIO Px.N Pin Data Input/Output\nWrite this bit can control one GPIO pin output value\nNote3: The PA.7 PB.12 PC.4 PC.5 PC.12 PC.13 pin is ignored" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x344++0x03
|
|
line.long 0x00 "PF1_PDIO,GPIO PF.n Pin Data Input/Output Register"
|
|
group.long 0x348++0x03
|
|
line.long 0x00 "PF2_PDIO,GPIO PF.n Pin Data Input/Output Register"
|
|
group.long 0x34C++0x03
|
|
line.long 0x00 "PF3_PDIO,GPIO PF.n Pin Data Input/Output Register"
|
|
tree.end
|
|
tree "I2C"
|
|
repeat 2. (list 0. 1.) (list ad:0x40020000 ad:0x40012000)
|
|
tree "I2C$1"
|
|
base $2
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "I2CON,I2C Control Register"
|
|
bitfld.long 0x00 7. "EI,Interrupt Enable Bit" "0: I2C interrupt Disabled,1: I2C interrupt Enabled"
|
|
bitfld.long 0x00 6. "ENS1,I2C Controller Enable Bit" "0: Disabled,1: Enabled"
|
|
newline
|
|
bitfld.long 0x00 5. "STA,I2C START Control\nSetting STA to logic 1 to enter Master mode the I2C hardware sends a START or repeat START condition to bus when the bus is free" "0,1"
|
|
bitfld.long 0x00 4. "STO,I2C STOP Control\nIn Master mode setting STO to transmit a STOP condition to bus then I2C hardware will check the bus condition if a STOP condition is detected this bit will be cleared by hardware automatically" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "SI,I2C Interrupt Flag\nWhen a new I2C state is present in the I2CSTATUS register the SI flag is set by hardware and if bit EI (I2CON [7]) is set the I2C interrupt is requested" "0,1"
|
|
bitfld.long 0x00 2. "AA,Assert Acknowledge Control" "0,1"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "I2CADDR0,I2C Slave Address Register0"
|
|
hexmask.long.byte 0x00 1.--7. 1. "I2CADDR,I2C Address Register\nThe content of this register is irrelevant when I2C is in Master mode"
|
|
bitfld.long 0x00 0. "GC,General Call Function" "0: General Call Function Disabled,1: General Call Function Enabled"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "I2CDAT,I2C Data Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. "I2CDAT,I2C Data Register\nThis field is located with the 8-bit transferred data of I2C serial port"
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "I2CSTATUS,I2C Status Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. "I2CSTATUS,I2C Status Register\nThere are 26 possible status codes"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "I2CLK,I2C Clock Divided Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. "I2CLK,I2C Clock Divided Register\nNote: The minimum value of I2CLK is 4"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "I2CTOC,I2C Time-out Counter Register"
|
|
bitfld.long 0x00 2. "ENTI,Time-Out Counter Enable Bit \nWhen Enabled the 14-bit time-out counter will start counting when SI(I2CON[3]) is clear" "0: Disabled,1: Enabled"
|
|
bitfld.long 0x00 1. "DIV4,Time-Out Counter Input Clock Divided By 4\nWhen Enabled The time-out period is extend 4 times" "0: Disabled,1: Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. "TIF,Time-Out Flag\nThis bit is set by hardware when I2C time-out happened and it can interrupt CPU if I2C interrupt enable bit EI(I2CON[7]) is set to 1.\nNote: Write 1 to clear this bit" "0,1"
|
|
repeat 3. (strings "1" "2" "3" )(list 0x0 0x4 0x8 )
|
|
group.long ($2+0x18)++0x03
|
|
line.long 0x00 "I2CADDR$1,I2C Slave Address Register $1"
|
|
hexmask.long.byte 0x00 1.--7. 1. "I2CADDR,I2C Address Register\nThe content of this register is irrelevant when I2C is in Master mode"
|
|
bitfld.long 0x00 0. "GC,General Call Function" "0: General Call Function Disabled,1: General Call Function Enabled"
|
|
repeat.end
|
|
repeat 4. (strings "0" "1" "2" "3" )(list 0x0 0x4 0x8 0xC )
|
|
group.long ($2+0x24)++0x03
|
|
line.long 0x00 "I2CADM$1,I2C Slave Address Mask Register $1"
|
|
hexmask.long.byte 0x00 1.--7. 1. "I2CADM,I2C Address Mask Register\nI2C bus controllers support multiple address recognition with four address mask register"
|
|
repeat.end
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "I2CWKUPCON,I2C Wake-up Control Register"
|
|
bitfld.long 0x00 0. "WKUPEN,I2C Wake-Up Enable Bit" "0: I2C wake-up function Disabled,1: I2C wake-up function Enabled"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "I2CWKUPSTS,I2C Wake-up Status Register"
|
|
bitfld.long 0x00 0. "WKUPIF,I2C Wake-Up Flag\nNote: Software can write 1 to clear this bit" "0: Chip is not woken-up from Power-down mode by..,1: Chip is woken-up from Power-down mode by I2C"
|
|
tree.end
|
|
repeat.end
|
|
tree.end
|
|
tree "INT"
|
|
base ad:0x50000300
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "IRQ0_SRC,IRQ0 (BOD) Interrupt Source Identity"
|
|
bitfld.long 0x00 0.--3. "INT_SRC,Interrupt Source\nDefine the interrupt sources for interrupt event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "IRQ1_SRC,IRQ1 (WDT) Interrupt Source Identity"
|
|
rbitfld.long 0x00 0.--3. "INT_SRC,Interrupt Source\nDefine the interrupt sources for interrupt event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "IRQ2_SRC,IRQ2 (EINT0) Interrupt Source Identity"
|
|
rbitfld.long 0x00 0.--3. "INT_SRC,Interrupt Source\nDefine the interrupt sources for interrupt event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "IRQ3_SRC,IRQ3 (EINT1) Interrupt Source Identity"
|
|
rbitfld.long 0x00 0.--3. "INT_SRC,Interrupt Source\nDefine the interrupt sources for interrupt event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "IRQ4_SRC,IRQ4 (GPA/B) Interrupt Source Identity"
|
|
rbitfld.long 0x00 0.--3. "INT_SRC,Interrupt Source\nDefine the interrupt sources for interrupt event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "IRQ5_SRC,IRQ5 (GPC/E/F) Interrupt Source Identity"
|
|
rbitfld.long 0x00 0.--3. "INT_SRC,Interrupt Source\nDefine the interrupt sources for interrupt event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "IRQ6_SRC,IRQ6 (PWMA) Interrupt Source Identity"
|
|
rbitfld.long 0x00 0.--3. "INT_SRC,Interrupt Source\nDefine the interrupt sources for interrupt event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "IRQ7_SRC,IRQ7 (PWMB) Interrupt Source Identity"
|
|
rbitfld.long 0x00 0.--3. "INT_SRC,Interrupt Source\nDefine the interrupt sources for interrupt event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "IRQ8_SRC,IRQ8 (TMR0) Interrupt Source Identity"
|
|
rbitfld.long 0x00 0.--3. "INT_SRC,Interrupt Source\nDefine the interrupt sources for interrupt event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "IRQ9_SRC,IRQ9 (TMR1) Interrupt Source Identity"
|
|
rbitfld.long 0x00 0.--3. "INT_SRC,Interrupt Source\nDefine the interrupt sources for interrupt event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "IRQ10_SRC,IRQ10 (TMR2) Interrupt Source Identity"
|
|
rbitfld.long 0x00 0.--3. "INT_SRC,Interrupt Source\nDefine the interrupt sources for interrupt event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "IRQ11_SRC,IRQ11 (TMR3) Interrupt Source Identity"
|
|
rbitfld.long 0x00 0.--3. "INT_SRC,Interrupt Source\nDefine the interrupt sources for interrupt event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "IRQ12_SRC,IRQ12 (UART0/2) Interrupt Source Identity"
|
|
rbitfld.long 0x00 0.--3. "INT_SRC,Interrupt Source\nDefine the interrupt sources for interrupt event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "IRQ13_SRC,IRQ13 (UART1) Interrupt Source Identity"
|
|
rbitfld.long 0x00 0.--3. "INT_SRC,Interrupt Source\nDefine the interrupt sources for interrupt event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "IRQ14_SRC,IRQ14 (SPI0) Interrupt Source Identity"
|
|
rbitfld.long 0x00 0.--3. "INT_SRC,Interrupt Source\nDefine the interrupt sources for interrupt event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "IRQ15_SRC,IRQ15 (SPI1) Interrupt Source Identity"
|
|
rbitfld.long 0x00 0.--3. "INT_SRC,Interrupt Source\nDefine the interrupt sources for interrupt event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "IRQ16_SRC,Reserved"
|
|
rbitfld.long 0x00 0.--3. "INT_SRC,Interrupt Source\nDefine the interrupt sources for interrupt event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "IRQ17_SRC,Reserved"
|
|
rbitfld.long 0x00 0.--3. "INT_SRC,Interrupt Source\nDefine the interrupt sources for interrupt event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "IRQ18_SRC,IRQ18 (I2C0) Interrupt Source Identity"
|
|
rbitfld.long 0x00 0.--3. "INT_SRC,Interrupt Source\nDefine the interrupt sources for interrupt event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "IRQ19_SRC,IRQ19 (I2C1) Interrupt Source Identity"
|
|
rbitfld.long 0x00 0.--3. "INT_SRC,Interrupt Source\nDefine the interrupt sources for interrupt event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "IRQ20_SRC,Reserved"
|
|
rbitfld.long 0x00 0.--3. "INT_SRC,Interrupt Source\nDefine the interrupt sources for interrupt event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "IRQ21_SRC,Reserved"
|
|
rbitfld.long 0x00 0.--3. "INT_SRC,Interrupt Source\nDefine the interrupt sources for interrupt event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "IRQ22_SRC,Reserved"
|
|
rbitfld.long 0x00 0.--3. "INT_SRC,Interrupt Source\nDefine the interrupt sources for interrupt event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x5C++0x03
|
|
line.long 0x00 "IRQ23_SRC,IRQ23 (USBD) Interrupt Source Identity"
|
|
rbitfld.long 0x00 0.--3. "INT_SRC,Interrupt Source\nDefine the interrupt sources for interrupt event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "IRQ24_SRC,Reserved"
|
|
rbitfld.long 0x00 0.--3. "INT_SRC,Interrupt Source\nDefine the interrupt sources for interrupt event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x64++0x03
|
|
line.long 0x00 "IRQ25_SRC,Reserved"
|
|
rbitfld.long 0x00 0.--3. "INT_SRC,Interrupt Source\nDefine the interrupt sources for interrupt event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x68++0x03
|
|
line.long 0x00 "IRQ26_SRC,IRQ26 (PDMA) Interrupt Source Identity"
|
|
rbitfld.long 0x00 0.--3. "INT_SRC,Interrupt Source\nDefine the interrupt sources for interrupt event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x6C++0x03
|
|
line.long 0x00 "IRQ27_SRC,Reserved"
|
|
rbitfld.long 0x00 0.--3. "INT_SRC,Interrupt Source\nDefine the interrupt sources for interrupt event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "IRQ28_SRC,IRQ28 (PWRWU) Interrupt Source Identity"
|
|
rbitfld.long 0x00 0.--3. "INT_SRC,Interrupt Source\nDefine the interrupt sources for interrupt event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x74++0x03
|
|
line.long 0x00 "IRQ29_SRC,IRQ29 (ADC) Interrupt Source Identity"
|
|
rbitfld.long 0x00 0.--3. "INT_SRC,Interrupt Source\nDefine the interrupt sources for interrupt event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x78++0x03
|
|
line.long 0x00 "IRQ30_SRC,IRQ30 (IRC) Interrupt Source Identity"
|
|
rbitfld.long 0x00 0.--3. "INT_SRC,Interrupt Source\nDefine the interrupt sources for interrupt event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "IRQ31_SRC,IRQ31 (RTC) Interrupt Source Identity"
|
|
rbitfld.long 0x00 0.--3. "INT_SRC,Interrupt Source\nDefine the interrupt sources for interrupt event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "NMI_SEL,NMI Source Interrupt Select Control Register"
|
|
bitfld.long 0x00 8. "NMI_EN,NMI Interrupt Enable Bit (Write Protect)\nNote: This bit is the protected bit and programming it needs to write '59h' '16h' and '88h' to address 0x5000_0100 to disable register protection" "0: NMI interrupt Disabled,1: NMI interrupt Enabled"
|
|
bitfld.long 0x00 0.--4. "NMI_SEL,NMI Interrupt Source Selection\nThe NMI interrupt to Cortex-M0 can be selected from one of the peripheral interrupt by setting NMI_SEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "MCU_IRQ,MCU Interrupt Request Source Register"
|
|
hexmask.long 0x00 0.--31. 1. "MCU_IRQ,MCU IRQ Source Register\nThe MCU_IRQ collects all the interrupts from the peripherals and generates the synchronous interrupt to Cortex-M0"
|
|
group.long 0x88++0x03
|
|
line.long 0x00 "MCU_IRQCR,MCU Interrupt Request Control Register"
|
|
bitfld.long 0x00 0. "FAST_IRQ,Fast IRQ Latency Enable Bit" "0: MCU IRQ latency is fixed at 13 clock cycles..,1: MCU IRQ latency will not fixed MCU will enter.."
|
|
tree.end
|
|
tree "PDMA"
|
|
tree "CRC"
|
|
base ad:0x50008E00
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CRC_CTL,CRC Control Register"
|
|
bitfld.long 0x00 30.--31. "CRC_MODE,CRC Polynomial Mode\nThis field indicates the CRC operation polynomial mode" "0: CRC-CCITT Polynomial Mode,1: CRC-8 Polynomial Mode,2: CRC-16 Polynomial Mode,3: CRC-32 Polynomial Mode"
|
|
bitfld.long 0x00 28.--29. "CPU_WDLEN,CPU Write Data Length\nThis field indicates the CPU write data length only when operating in CPU PIO mode.\nNote1: This field is only valid when operating in CPU PIO mode.\nNote2: When the write data length is 8-bit mode the valid data in.." "0: The write data length is 8-bit mode,1: The write data length is 16-bit mode,2: The write data length is 32-bit mode,3: Reserved"
|
|
newline
|
|
bitfld.long 0x00 27. "CHECKSUM_COM,Checksum 1's Complement\nThis bit is used to enable the 1's complement function for checksum result in CRC_CHECKSUM register" "0: 1's complement for CRC checksum Disabled,1: 1's complement for CRC checksum Enabled"
|
|
bitfld.long 0x00 26. "WDATA_COM,Write Data 1's Complement\nThis bit is used to enable the 1's complement function for write data value in CRC_WDATA register" "0: 1's complement for CRC write data in Disabled,1: 1's complement for CRC write data in Enabled"
|
|
newline
|
|
bitfld.long 0x00 25. "CHECKSUM_RVS,Checksum Reverse\nThis bit is used to enable the bit order reverse function for write data value in CRC_CHECKSUM register.\nNote: If the checksum result is 0XDD7B0F2E the bit order reverse for CRC checksum is 0x74F0DEBB" "0: Bit order reverse for CRC checksum Disabled,1: Bit order reverse for CRC checksum Enabled"
|
|
bitfld.long 0x00 24. "WDATA_RVS,Write Data Order Reverse\nThis bit is used to enable the bit order reverse function for write data value in CRC_WDATA register.\nNote: If the write data is 0xAABBCCDD the bit order reverse for CRC write data in is 0x55DD33BB" "0: Bit order reverse for CRC write data in..,1: Bit order reverse for CRC write data in.."
|
|
newline
|
|
bitfld.long 0x00 23. "TRIG_EN,Trigger Enable Bit\nThis bit is used to trigger the CRC DMA transfer.\nNote1: If this bit asserts which indicates the CRC engine operation in CRC DMA mode do not fill in any data in CRC_WDATA register.\nNote2: When CRC DMA transfer completed.." "0: No effect,1: CRC DMA data read or write transfer Enabled"
|
|
bitfld.long 0x00 1. "CRC_RST,CRC Engine Reset\nNote: When operated in CPU PIO mode setting this bit will reload the initial seed value (CRC_SEED register)" "0: No effect,1: Reset the internal CRC state machine and.."
|
|
newline
|
|
bitfld.long 0x00 0. "CRCCEN,CRC Channel Enable Bit" "0: No effect,1: CRC operation Enabled"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CRC_DMASAR,CRC DMA Source Address Register"
|
|
hexmask.long 0x00 0.--31. 1. "CRC_DMASAR,CRC DMA Transfer Source Address Register\nThis field indicates a 32-bit source address of CRC DMA.\nNote: The source address must be word alignment"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "CRC_DMABCR,CRC DMA Transfer Byte Count Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "CRC_DMABCR,CRC DMA Transfer Byte Count Register\nThis field indicates a 16-bit total transfer byte count number of CRC DMA"
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "CRC_DMACSAR,CRC DMA Current Source Address Register"
|
|
hexmask.long 0x00 0.--31. 1. "CRC_DMACSAR,CRC DMA Current Source Address Register (Read Only)\nThis field indicates the current source address where the CRC DMA transfer just occurs"
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "CRC_DMACBCR,CRC DMA Current Transfer Byte Count Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "CRC_DMACBCR,CRC DMA Current Remained Byte Count Register (Read Only)\nThis field indicates the current remained byte count of CRC DMA.\nNote: Setting CRC_RST (CRC_CTL[1]) bit to 1 will clear this register value"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "CRC_DMAIER,CRC DMA Interrupt Enable Register"
|
|
bitfld.long 0x00 1. "CRC_BLKD_IE,CRC DMA Block Transfer Done Interrupt Enable Bit\nEnable this bit will generate the CRC DMA Transfer Done interrupt signal while CRC_BLKD_IF (CRC_DMAISR[1]) bit is set to 1" "0: Interrupt generator Disabled when CRC DMA..,1: Interrupt generator Enabled when CRC DMA.."
|
|
bitfld.long 0x00 0. "CRC_TABORT_IE,CRC DMA Read/Write Target Abort Interrupt Enable Bit\nEnable this bit will generate the CRC DMA Target Abort interrupt signal while CRC_TARBOT_IF (CRC_DMAISR[0]) bit is set to 1" "0: Target abort interrupt generation Disabled..,1: Target abort interrupt generation Enabled.."
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "CRC_DMAISR,CRC DMA Interrupt Status Register"
|
|
bitfld.long 0x00 1. "CRC_BLKD_IF,CRC DMA Block Transfer Done Interrupt Flag\nThis bit indicates that CRC DMA transfer has finished or not.\nIt is cleared by writing 1 to it through software..\n(When CRC DMA transfer done TRIG_EN (CRC_CTL[23]) bit will be cleared.." "0: Not finished if TRIG_EN (CRC_CTL[23]) bit has..,1: CRC transfer done if TRIG_EN (CRC_CTL[23]).."
|
|
bitfld.long 0x00 0. "CRC_TABORT_IF,CRC DMA Read/Write Target Abort Interrupt Flag\nThis bit indicates that CRC bus has error or not during CRC DMA transfer.\nIt is cleared by writing 1 to it through software.\nNote: The bit filed indicate bus master received error response.." "0: No bus error response received during CRC DMA..,1: Bus error response received during CRC DMA.."
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "CRC_WDATA,CRC Write Data Register"
|
|
hexmask.long 0x00 0.--31. 1. "CRC_WDATA,CRC Write Data Register\nWhen operating in CPU PIO mode software can write data to this field to perform CRC operation.\nWhen operating in DMA mode this field indicates the DMA read data from memory and cannot be written.\nNote: When the write.."
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "CRC_SEED,CRC Seed Register"
|
|
hexmask.long 0x00 0.--31. 1. "CRC_SEED,CRC Seed Register\nThis field indicates the CRC seed value"
|
|
rgroup.long 0x88++0x03
|
|
line.long 0x00 "CRC_CHECKSUM,CRC Checksum Register"
|
|
hexmask.long 0x00 0.--31. 1. "CRC_CHECKSUM,CRC Checksum Register\nThis fields indicates the CRC checksum result"
|
|
tree.end
|
|
repeat 9. (list 0. 1. 2. 3. 4. 5. 6. 7. 8.) (list ad:0x50008000 ad:0x50008100 ad:0x50008200 ad:0x50008300 ad:0x50008400 ad:0x50008500 ad:0x50008600 ad:0x50008700 ad:0x50008800)
|
|
tree "PDMA_CH$1"
|
|
base $2
|
|
repeat 9. (strings "0" "1" "2" "3" "4" "5" "6" "7" "8" )(list 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 )
|
|
group.long ($2+0x00)++0x03
|
|
line.long 0x00 "PDMA_CSR$1,PDMA Channel x Control Register"
|
|
bitfld.long 0x00 23. "TRIG_EN,Trigger Enable Bit\nNote: When PDMA transfer completed this bit will be cleared automatically.\nIf the bus error occurs all PDMA transfer will be stopped" "0: No effect,1: PDMA data read or write transfer Enabled"
|
|
bitfld.long 0x00 19.--20. "APB_TWS,Peripheral Transfer Width Selection\nNote: This field is meaningful only when MODE_SEL (PDMA_CSRx[3:2]) is Peripheral to Memory mode (Peripheral-to-Memory) or Memory to Peripheral mode (Memory-to-Peripheral)" "0: One word (32-bit) is transferred for every..,1: One byte (8-bit) is transferred for every..,2: One half-word (16-bit) is transferred for..,3: Reserved"
|
|
newline
|
|
bitfld.long 0x00 6.--7. "DAD_SEL,Transfer Destination Address Direction Selection" "0: Transfer destination address is increasing..,1: Reserved,2: Transfer destination address is fixed,3: Reserved"
|
|
bitfld.long 0x00 4.--5. "SAD_SEL,Transfer Source Address Direction Selection" "0: Transfer source address is increasing..,1: Reserved,2: Transfer source address is fixed (This..,3: Reserved"
|
|
newline
|
|
bitfld.long 0x00 2.--3. "MODE_SEL,PDMA Mode Selection" "0: Memory to Memory mode (Memory-to-Memory),1: Peripheral to Memory mode..,2: Memory to Peripheral mode..,?..."
|
|
bitfld.long 0x00 1. "SW_RST,Software Engine Reset" "0: No effect,1: Reset the internal state machine pointers and.."
|
|
newline
|
|
bitfld.long 0x00 0. "PDMACEN,PDMA Channel Enable Bit\nSetting this bit to 1 enables PDMA operation" "0,1"
|
|
repeat.end
|
|
repeat 9. (strings "0" "1" "2" "3" "4" "5" "6" "7" "8" )(list 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 )
|
|
group.long ($2+0x04)++0x03
|
|
line.long 0x00 "PDMA_SAR$1,PDMA Channel x Source Address Register"
|
|
hexmask.long 0x00 0.--31. 1. "PDMA_SAR,PDMA Transfer Source Address Register\nThis field indicates a 32-bit source address of PDMA.\nNote: The source address must be word alignment"
|
|
repeat.end
|
|
repeat 9. (strings "0" "1" "2" "3" "4" "5" "6" "7" "8" )(list 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 )
|
|
group.long ($2+0x08)++0x03
|
|
line.long 0x00 "PDMA_DAR$1,PDMA Channel x Destination Address Register"
|
|
hexmask.long 0x00 0.--31. 1. "PDMA_DAR,PDMA Transfer Destination Address Register\nThis field indicates a 32-bit destination address of PDMA.\nNote: The destination address must be word alignment"
|
|
repeat.end
|
|
repeat 9. (strings "0" "1" "2" "3" "4" "5" "6" "7" "8" )(list 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 )
|
|
group.long ($2+0x0C)++0x03
|
|
line.long 0x00 "PDMA_BCR$1,PDMA Channel x Transfer Byte Count Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "PDMA_BCR,PDMA Transfer Byte Count Register\nThis field indicates a 16-bit transfer byte count number of PDMA it must be word alignment"
|
|
repeat.end
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "PDMA_POINT0,PDMA Channel x Internal Buffer Pointer Register"
|
|
bitfld.long 0x00 0.--3. "PDMA_POINT,PDMA Internal Buffer Pointer Register (Read Only)\nThis field indicates the internal buffer pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
repeat 8. (strings "1" "2" "3" "4" "5" "6" "7" "8" )(list 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 )
|
|
group.long ($2+0x10)++0x03
|
|
line.long 0x00 "PDMA_POINT$1,PDMA Channel x Internal Buffer Pointer Register"
|
|
rbitfld.long 0x00 0.--3. "PDMA_POINT,PDMA Internal Buffer Pointer Register (Read Only)\nThis field indicates the internal buffer pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
repeat.end
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "PDMA_CSAR0,PDMA Channel x Current Source Address Register"
|
|
hexmask.long 0x00 0.--31. 1. "PDMA_CSAR,PDMA Current Source Address Register (Read Only)\nThis field indicates the source address where the PDMA transfer just occurred"
|
|
repeat 8. (strings "1" "2" "3" "4" "5" "6" "7" "8" )(list 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 )
|
|
group.long ($2+0x14)++0x03
|
|
line.long 0x00 "PDMA_CSAR$1,PDMA Channel x Current Source Address Register"
|
|
hexmask.long 0x00 0.--31. 1. "PDMA_CSAR,PDMA Current Source Address Register (Read Only)\nThis field indicates the source address where the PDMA transfer just occurred"
|
|
repeat.end
|
|
rgroup.long 0x18++0x03
|
|
line.long 0x00 "PDMA_CDAR0,PDMA Channel x Current Destination Address Register"
|
|
hexmask.long 0x00 0.--31. 1. "PDMA_CDAR,PDMA Current Destination Address Register (Read Only)\nThis field indicates the destination address where the PDMA transfer just occurred"
|
|
repeat 8. (strings "1" "2" "3" "4" "5" "6" "7" "8" )(list 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 )
|
|
group.long ($2+0x18)++0x03
|
|
line.long 0x00 "PDMA_CDAR$1,PDMA Channel x Current Destination Address Register"
|
|
hexmask.long 0x00 0.--31. 1. "PDMA_CDAR,PDMA Current Destination Address Register (Read Only)\nThis field indicates the destination address where the PDMA transfer just occurred"
|
|
repeat.end
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "PDMA_CBCR0,PDMA Channel x Current Transfer Byte Count Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "PDMA_CBCR,PDMA Current Byte Count Register (Read Only)\nThis field indicates the current remained byte count of PDMA.\nNote: This field value will be cleared to 0 when software set SW_RST (PDMA_CSRx[1]) to '1'"
|
|
repeat 8. (strings "1" "2" "3" "4" "5" "6" "7" "8" )(list 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 )
|
|
group.long ($2+0x1C)++0x03
|
|
line.long 0x00 "PDMA_CBCR$1,PDMA Channel x Current Transfer Byte Count Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "PDMA_CBCR,PDMA Current Byte Count Register (Read Only)\nThis field indicates the current remained byte count of PDMA.\nNote: This field value will be cleared to 0 when software set SW_RST (PDMA_CSRx[1]) to '1'"
|
|
repeat.end
|
|
repeat 9. (strings "0" "1" "2" "3" "4" "5" "6" "7" "8" )(list 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 )
|
|
group.long ($2+0x20)++0x03
|
|
line.long 0x00 "PDMA_IER$1,PDMA Channel x Interrupt Enable Register"
|
|
bitfld.long 0x00 1. "BLKD_IE,PDMA Block Transfer Done Interrupt Enable Bit" "0: Interrupt generator Disabled when PDMA..,1: Interrupt generator Enabled when PDMA.."
|
|
bitfld.long 0x00 0. "TABORT_IE,PDMA Read/Write Target Abort Interrupt Enable Bit" "0: Target abort interrupt generation Disabled..,1: Target abort interrupt generation Enabled.."
|
|
repeat.end
|
|
repeat 9. (strings "0" "1" "2" "3" "4" "5" "6" "7" "8" )(list 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 )
|
|
group.long ($2+0x24)++0x03
|
|
line.long 0x00 "PDMA_ISR$1,PDMA Channel x Interrupt Status Register"
|
|
bitfld.long 0x00 1. "BLKD_IF,PDMA Block Transfer Done Interrupt Flag\nThis bit indicates that PDMA has finished all transfers.\nWrite 1 to clear this bit to 0" "0: Not finished,1: Done"
|
|
bitfld.long 0x00 0. "TABORT_IF,PDMA Read/Write Target Abort Interrupt Flag\nWrite 1 to clear this bit to 0.\nNote: This bit filed indicates bus master received ERROR response or not" "0: No bus ERROR response received,1: Bus ERROR response received"
|
|
repeat.end
|
|
rgroup.long 0x80++0x03
|
|
line.long 0x00 "PDMA_SBUF0_C0,PDMA Channel x Shared Buffer FIFO 0 Register"
|
|
hexmask.long 0x00 0.--31. 1. "PDMA_SBUF0,PDMA Shared Buffer FIFO 0 (Read Only)\nEach channel has its own 1 word internal buffer"
|
|
repeat 8. (strings "1" "2" "3" "4" "5" "6" "7" "8" )(list 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 )
|
|
group.long ($2+0x80)++0x03
|
|
line.long 0x00 "PDMA_SBUF0_C$1,PDMA Channel x Shared Buffer FIFO 0 Register"
|
|
hexmask.long 0x00 0.--31. 1. "PDMA_SBUF0,PDMA Shared Buffer FIFO 0 (Read Only)\nEach channel has its own 1 word internal buffer"
|
|
repeat.end
|
|
tree.end
|
|
repeat.end
|
|
tree "PDMA_GCR"
|
|
base ad:0x50008F00
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "PDMA_GCRCSR,PDMA Global Control Register"
|
|
bitfld.long 0x00 24. "CRC_CLK_EN,CRC Controller Clock Enable Bit" "0: Disabled,1: Enabled"
|
|
bitfld.long 0x00 16. "CLK8_EN,PDMA Controller Channel 8 Clock Enable Bit" "0: Disabled,1: Enabled"
|
|
newline
|
|
bitfld.long 0x00 15. "CLK7_EN,PDMA Controller Channel 7 Clock Enable Bit" "0: Disabled,1: Enabled"
|
|
bitfld.long 0x00 14. "CLK6_EN,PDMA Controller Channel 6 Clock Enable Bit" "0: Disabled,1: Enabled"
|
|
newline
|
|
bitfld.long 0x00 13. "CLK5_EN,PDMA Controller Channel 5 Clock Enable Bit" "0: Disabled,1: Enabled"
|
|
bitfld.long 0x00 12. "CLK4_EN,PDMA Controller Channel 4 Clock Enable Bit" "0: Disabled,1: Enabled"
|
|
newline
|
|
bitfld.long 0x00 11. "CLK3_EN,PDMA Controller Channel 3 Clock Enable Bit" "0: Disabled,1: Enabled"
|
|
bitfld.long 0x00 10. "CLK2_EN,PDMA Controller Channel 2 Clock Enable Bit" "0: Disabled,1: Enabled"
|
|
newline
|
|
bitfld.long 0x00 9. "CLK1_EN,PDMA Controller Channel 1 Clock Enable Bit" "0: Disabled,1: Enabled"
|
|
bitfld.long 0x00 8. "CLK0_EN,PDMA Controller Channel 0 Clock Enable Bit" "0: Disabled,1: Enabled"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "PDMA_PDSSR0,PDMA Service Selection Control Register 0"
|
|
bitfld.long 0x00 28.--31. "SPI3_TXSEL,PDMA SPI3 TX Selection\nThis field defines which PDMA channel is connected to the on-chip peripheral SPI3 TX" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. "SPI3_RXSEL,PDMA SPI3 RX Selection \nThis field defines which PDMA channel is connected to the on-chip peripheral SPI3 RX" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 20.--23. "SPI2_TXSEL,PDMA SPI2 TX Selection\nThis field defines which PDMA channel is connected to the on-chip peripheral SPI2 TX" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. "SPI2_RXSEL,PDMA SPI2 RX Selection\nThis field defines which PDMA channel is connected to the on-chip peripheral SPI2 RX" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 12.--15. "SPI1_TXSEL,PDMA SPI1 TX Selection\nThis field defines which PDMA channel is connected to the on-chip peripheral SPI1 TX" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. "SPI1_RXSEL,PDMA SPI1 RX Selection\nThis field defines which PDMA channel is connected to the on-chip peripheral SPI1 RX" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 4.--7. "SPI0_TXSEL,PDMA SPI0 TX Selection\nThis field defines which PDMA channel is connected to the on-chip peripheral SPI0 TX" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "SPI0_RXSEL,PDMA SPI0 RX Selection\n0000: CH0\n0001: CH1\n0010: CH2\n0011: CH3 \n0100: CH4 \n0101: CH5\n0110: CH6\n0111: CH7\n1000: CH8\nOthers : Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "PDMA_PDSSR1,PDMA Service Selection Control Register 1"
|
|
bitfld.long 0x00 24.--27. "ADC_RXSEL,PDMA ADC RX Selection\nThis field defines which PDMA channel is connected to the on-chip peripheral ADC RX" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. "UART1_TXSEL,PDMA UART1 TX Selection\nThis field defines which PDMA channel is connected to the on-chip peripheral UART1 TX" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 8.--11. "UART1_RXSEL,PDMA UART1 RX Selection\nThis field defines which PDMA channel is connected to the on-chip peripheral UART1 RX" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. "UART0_TXSEL,PDMA UART0 TX Selection\nThis field defines which PDMA channel is connected to the on-chip peripheral UART0 TX" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 0.--3. "UART0_RXSEL,PDMA UART0 RX Selection\n0000: CH0\n0001: CH1\n0010: CH2\n0011: CH3 \n0100: CH4 \n0101: CH5\n0110: CH6\n0111: CH7\n1000: CH8\nOthers : Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "PDMA_GCRISR,PDMA Global Interrupt Status Register"
|
|
bitfld.long 0x00 31. "INTR,Interrupt Status\nThis bit is the interrupt status of PDMA controller.\nNote: This bit is read only" "0,1"
|
|
bitfld.long 0x00 16. "INTRCRC,Interrupt Status Of CRC Controller\nThis bit is the interrupt status of CRC controller\nNote: This bit is read only" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "INTR8,Interrupt Status Of Channel 8 \nThis bit is the interrupt status of PDMA channel8.\nNote: This bit is read only" "0,1"
|
|
bitfld.long 0x00 7. "INTR7,Interrupt Status Of Channel 7 \nThis bit is the interrupt status of PDMA channel7.\nNote: This bit is read only" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "INTR6,Interrupt Status Of Channel 6 \nThis bit is the interrupt status of PDMA channel6.\nNote: This bit is read only" "0,1"
|
|
bitfld.long 0x00 5. "INTR5,Interrupt Status Of Channel 5 \nThis bit is the interrupt status of PDMA channel5.\nNote: This bit is read only" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "INTR4,Interrupt Status Of Channel 4\nThis bit is the interrupt status of PDMA channel4.\nNote: This bit is read only" "0,1"
|
|
bitfld.long 0x00 3. "INTR3,Interrupt Status Of Channel 3\nThis bit is the interrupt status of PDMA channel3.\nNote: This bit is read only" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "INTR2,Interrupt Status Of Channel 2\nThis bit is the interrupt status of PDMA channel2.\nNote: This bit is read only" "0,1"
|
|
bitfld.long 0x00 1. "INTR1,Interrupt Status Of Channel 1\nThis bit is the interrupt status of PDMA channel1.\nNote: This bit is read only" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "INTR0,Interrupt Status Of Channel 0\nThis bit is the interrupt status of PDMA channel0.\nNote: This bit is read only" "0,1"
|
|
tree.end
|
|
tree.end
|
|
tree "PWM"
|
|
tree "PWMA"
|
|
base ad:0x40040000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "PPR,PWM Prescaler Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DZI23,Dead-Zone Interval For Pair Of Channel2 And Channel3 (PWM2 And PWM3 Pair For PWM Group A)\nThese 8-bit determine the Dead-zone length"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DZI01,Dead-Zone Interval For Pair Of Channel 0 And Channel 1 (PWM0 And PWM1 Pair For PWM Group A PWM4 And PWM5 Pair For PWM Group B)\nThese 8-bit determine the Dead-zone length"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "CP23,Clock Prescaler 2 (PWM-Timer2 / 3 For Group A)\nClock input is divided by (CP23 + 1) before it is fed to the corresponding PWM-timer"
|
|
hexmask.long.byte 0x00 0.--7. 1. "CP01,Clock Prescaler 0 (PWM-Timer 0 / 1 For Group A And PWM-Timer 4 / 5 For Group B)\nClock input is divided by (CP01 + 1) before it is fed to the corresponding PWM-timer"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CSR,PWM Clock Source Divider Select Register"
|
|
bitfld.long 0x00 12.--14. "CSR3,PWM Timer 3 Clock Source Divider Selection (PWM Timer 3 For Group A)\nSelect clock source divider for PWM timer 3" "0: 0,1: 1,2: 2,3: 16,4: 4,?..."
|
|
bitfld.long 0x00 8.--10. "CSR2,PWM Timer 2 Clock Source Divider Selection (PWM Timer 2 For Group A)\nSelect clock source divider for PWM timer 2.\n(Table is the same as CSR3)" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 4.--6. "CSR1,PWM Timer 1 Clock Source Divider Selection (PWM Timer 1 For Group A And PWM Timer 5 For Group B)\nSelect clock source divider for PWM timer 1.\n(Table is the same as CSR3)" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. "CSR0,PWM Timer 0 Clock Source Divider Selection (PWM Timer 0 For Group A And PWM Timer 4 For Group B)\nSelect clock source divider for PWM timer 0.\n(Table is the same as CSR3)" "0,1,2,3,4,5,6,7"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "PCR,PWM Control Register"
|
|
bitfld.long 0x00 31. "PWM23TYPE,PWM23 Aligned Type Selection (PWM2 And PWM3 Pair For PWM Group A)" "0: Edge-aligned type,1: Center-aligned type"
|
|
bitfld.long 0x00 30. "PWM01TYPE,PWM01 Aligned Type Selection (PWM0 And PWM1 Pair For PWM Group A PWM4 And PWM5 Pair For PWM Group B)" "0: Edge-aligned type,1: Center-aligned type"
|
|
newline
|
|
bitfld.long 0x00 27. "CH3MOD,PWM-Timer 3 Auto-Reload/One-Shot Mode (PWM Timer 3 For Group A)\nNote: If there is a transition at this bit it will cause CNR3 and CMR3 be cleared" "0: One-shot mode,1: Auto-reload mode"
|
|
bitfld.long 0x00 26. "CH3INV,PWM-Timer 3 Output Inverter Enable (PWM Timer 3 For Group A)" "0: Inverter Disabled,1: Inverter Enabled"
|
|
newline
|
|
bitfld.long 0x00 25. "CH3PINV,PWM-Timer 3 Output Polar Inverse Enable (PWM Timer 3 For Group A)" "0: PWM3 output polar inverse Disable,1: PWM3 output polar inverse Enable"
|
|
bitfld.long 0x00 24. "CH3EN,PWM-Timer 3 Enable (PWM Timer 3 For Group A)" "0: Corresponding PWM-Timer Stopped,1: Corresponding PWM-Timer Start Running"
|
|
newline
|
|
bitfld.long 0x00 19. "CH2MOD,PWM-Timer 2 Auto-Reload/One-Shot Mode (PWM Timer 2 For Group A)\nNote: If there is a transition at this bit it will cause CNR2 and CMR2 be cleared" "0: One-shot mode,1: Auto-reload mode"
|
|
bitfld.long 0x00 18. "CH2INV,PWM-Timer 2 Output Inverter Enable (PWM Timer 2 For Group A)" "0: Inverter Disabled,1: Inverter Enabled"
|
|
newline
|
|
bitfld.long 0x00 17. "CH2PINV,PWM-Timer 2 Output Polar Inverse Enable (PWM Timer 2 For Group A)" "0: PWM2 output polar inverse Disabled,1: PWM2 output polar inverse Enabled"
|
|
bitfld.long 0x00 16. "CH2EN,PWM-Timer 2 Enable (PWM Timer 2 For Group A)" "0: Corresponding PWM-Timer Stopped,1: Corresponding PWM-Timer Start Running"
|
|
newline
|
|
bitfld.long 0x00 11. "CH1MOD,PWM-Timer 1 Auto-Reload/One-Shot Mode (PWM Timer 1 For Group A And PWM Timer 5 For Group B)\nNote: If there is a transition at this bit it will cause CNR1 and CMR1 be cleared" "0: One-shot mode,1: Auto-reload mode"
|
|
bitfld.long 0x00 10. "CH1INV,PWM-Timer 1 Output Inverter Enable (PWM Timer 1 For Group A And PWM Timer 5 For Group B)" "0: Inverter Disable,1: Inverter Enable"
|
|
newline
|
|
bitfld.long 0x00 9. "CH1PINV,PWM-Timer 1 Output Polar Inverse Enable (PWM Timer 1 For Group A And PWM Timer 5 For Group B)" "0: PWM1 output polar inverse Disabled,1: PWM1 output polar inverse Enabled"
|
|
bitfld.long 0x00 8. "CH1EN,PWM-Timer 1 Enable (PWM Timer 1 For Group A And PWM Timer 5 For Group B)" "0: Corresponding PWM-Timer Stopped,1: Corresponding PWM-Timer Start Running"
|
|
newline
|
|
bitfld.long 0x00 5. "DZEN23,Dead-Zone 2 Generator Enable (PWM2 And PWM3 Pair For PWM Group A)\nNote: When Dead-zone generator is enabled the pair of PWM2 and PWM3 becomes a complementary pair for PWM group A" "0: Disabled,1: Enabled"
|
|
bitfld.long 0x00 4. "DZEN01,Dead-Zone 0 Generator Enable (PWM0 And PWM1 Pair For PWM Group A PWM4 And PWM5 Pair For PWM Group B)\nNote: When Dead-zone generator is enabled the pair of PWM0 and PWM1 becomes a complementary pair for PWM group A and the pair of PWM4 and PWM5.." "0: Disabled,1: Enabled"
|
|
newline
|
|
bitfld.long 0x00 3. "CH0MOD,PWM-Timer 0 Auto-Reload/One-Shot Mode (PWM Timer 0 For Group A And PWM Timer 4 For Group B)\nNote: If there is a transition at this bit it will cause CNR0 and CMR0 be cleared" "0: One-shot mode,1: Auto-reload mode"
|
|
bitfld.long 0x00 2. "CH0INV,PWM-Timer 0 Output Inverter Enable (PWM Timer 0 For Group A And PWM Timer 4 For Group B)" "0: Inverter Disabled,1: Inverter Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. "CH0PINV,PWM-Timer 0 Output Polar Inverse Enable (PWM Timer 0 For Group A And PWM Timer 4 For Group B)" "0: PWM0 output polar inverse Disabled,1: PWM0 output polar inverse Enabled"
|
|
bitfld.long 0x00 0. "CH0EN,PWM-Timer 0 Enable (PWM Timer 0 For Group A And PWM Timer 4 For Group B)" "0: The corresponding PWM-Timer stops running,1: The corresponding PWM-Timer starts running"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "CNR0,PWM Counter Register 0"
|
|
hexmask.long.word 0x00 0.--15. 1. "CNRx,PWM Timer Loaded Value\nCNR determines the PWM period.\nNote: Any write to CNR will take effect in next PWM cycle.\nNote: When PWM operating at Center-aligned type CNR value should be set between 0x0000 to 0xFFFE"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "CMR0,PWM Comparator Register 0"
|
|
hexmask.long.word 0x00 0.--15. 1. "CMRx,PWM Comparator Register\nCMR determines the PWM duty.\nNote: Any write to CNR will take effect in next PWM cycle"
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "PDR0,PWM Data Register 0"
|
|
hexmask.long.word 0x00 0.--15. 1. "PDRx,PWM Data Register\nUser can monitor PDR to know the current value in 16-bit counter"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "CNR1,PWM Counter Register 1"
|
|
hexmask.long.word 0x00 0.--15. 1. "CNRx,PWM Timer Loaded Value\nCNR determines the PWM period.\nNote: Any write to CNR will take effect in next PWM cycle.\nNote: When PWM operating at Center-aligned type CNR value should be set between 0x0000 to 0xFFFE"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "CMR1,PWM Comparator Register 1"
|
|
hexmask.long.word 0x00 0.--15. 1. "CMRx,PWM Comparator Register\nCMR determines the PWM duty.\nNote: Any write to CNR will take effect in next PWM cycle"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "PDR1,PWM Data Register 1"
|
|
hexmask.long.word 0x00 0.--15. 1. "PDRx,PWM Data Register\nUser can monitor PDR to know the current value in 16-bit counter"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "CNR2,PWM Counter Register 2"
|
|
hexmask.long.word 0x00 0.--15. 1. "CNRx,PWM Timer Loaded Value\nCNR determines the PWM period.\nNote: Any write to CNR will take effect in next PWM cycle.\nNote: When PWM operating at Center-aligned type CNR value should be set between 0x0000 to 0xFFFE"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "CMR2,PWM Comparator Register 2"
|
|
hexmask.long.word 0x00 0.--15. 1. "CMRx,PWM Comparator Register\nCMR determines the PWM duty.\nNote: Any write to CNR will take effect in next PWM cycle"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "PDR2,PWM Data Register 2"
|
|
hexmask.long.word 0x00 0.--15. 1. "PDRx,PWM Data Register\nUser can monitor PDR to know the current value in 16-bit counter"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "CNR3,PWM Counter Register 3"
|
|
hexmask.long.word 0x00 0.--15. 1. "CNRx,PWM Timer Loaded Value\nCNR determines the PWM period.\nNote: Any write to CNR will take effect in next PWM cycle.\nNote: When PWM operating at Center-aligned type CNR value should be set between 0x0000 to 0xFFFE"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "CMR3,PWM Comparator Register 3"
|
|
hexmask.long.word 0x00 0.--15. 1. "CMRx,PWM Comparator Register\nCMR determines the PWM duty.\nNote: Any write to CNR will take effect in next PWM cycle"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "PDR3,PWM Data Register 3"
|
|
hexmask.long.word 0x00 0.--15. 1. "PDRx,PWM Data Register\nUser can monitor PDR to know the current value in 16-bit counter"
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "PBCR,PWM Backward Compatible Register"
|
|
bitfld.long 0x00 0. "BCn,PWM Backward Compatible Register\nRefer to the CCR0/CCR2 register bit 6 7 22 23 description\nNote: It is recommended that this bit be set to 1 to prevent CFLRIx and CRLRIx from being cleared when writing CCR0/CCR2" "0: Configure write 0 to clear CFLRI0~3 and..,1: Configure write 1 to clear CFLRI0~3 and.."
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "PIER,PWM Interrupt Enable Register"
|
|
bitfld.long 0x00 17. "INT23TYPE,PWM23 Interrupt Period Type Selection Bit (PWM2 And PWM3 Pair For PWM Group A)\nNote: This bit is effective when PWM in Center-aligned type only" "0: PWMIFn will be set if PWM counter underflow,1: PWMIFn will be set if PWM counter matches.."
|
|
bitfld.long 0x00 16. "INT01TYPE,PWM01 Interrupt Period Type Selection Bit (PWM0 And PWM1 Pair For PWM Group A PWM4 And PWM5 Pair For PWM Group B)\nNote: This bit is effective when PWM in Center-aligned type only" "0: PWMIFn will be set if PWM counter underflow,1: PWMIFn will be set if PWM counter matches.."
|
|
newline
|
|
bitfld.long 0x00 11. "PWMDIE3,PWM Channel 3 Duty Interrupt Enable Bit" "0: Disabled,1: Enabled"
|
|
bitfld.long 0x00 10. "PWMDIE2,PWM Channel 2 Duty Interrupt Enable Bit" "0: Disabled,1: Enabled"
|
|
newline
|
|
bitfld.long 0x00 9. "PWMDIE1,PWM Channel 1 Duty Interrupt Enable Bit" "0: Disabled,1: Enabled"
|
|
bitfld.long 0x00 8. "PWMDIE0,PWM Channel 0 Duty Interrupt Enable Bit" "0: Disabled,1: Enabled"
|
|
newline
|
|
bitfld.long 0x00 3. "PWMIE3,PWM Channel 3 Period Interrupt Enable Bit" "0: Disabled,1: Enabled"
|
|
bitfld.long 0x00 2. "PWMIE2,PWM Channel 2 Period Interrupt Enable Bit" "0: Disabled,1: Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. "PWMIE1,PWM Channel 1 Period Interrupt Enable Bit" "0: Disabled,1: Enabled"
|
|
bitfld.long 0x00 0. "PWMIE0,PWM Channel 0 Period Interrupt Enable Bit" "0: Disabled,1: Enabled"
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "PIIR,PWM Interrupt Indication Register"
|
|
bitfld.long 0x00 11. "PWMDIF3,PWM Channel 3 Duty Interrupt Flag\nFlag is set by hardware when channel 3 PWM counter down count and reaches CMR3 software can clear this bit by writing a one to it.\nNote: If CMR equal to CNR this flag is not working in Edge-aligned type.." "0,1"
|
|
bitfld.long 0x00 10. "PWMDIF2,PWM Channel 2 Duty Interrupt Flag\nFlag is set by hardware when channel 2 PWM counter down count and reaches CMR2 software can clear this bit by writing a one to it.\nNote: If CMR equal to CNR this flag is not working in Edge-aligned type.." "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "PWMDIF1,PWM Channel 1 Duty Interrupt Flag\nFlag is set by hardware when channel 1 PWM counter down count and reaches CMR1 software can clear this bit by writing a one to it.\nNote: If CMR equal to CNR this flag is not working in Edge-aligned type.." "0,1"
|
|
bitfld.long 0x00 8. "PWMDIF0,PWM Channel 0 Duty Interrupt Flag\nFlag is set by hardware when channel 0 PWM counter down count and reaches CMR0 software can clear this bit by writing a one to it.\nNote: If CMR equal to CNR this flag is not working in Edge-aligned type.." "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "PWMIF3,PWM Channel 3 Period Interrupt Status\nThis bit is set by hardware when PWM3 counter reaches the requirement of interrupt (depend on INT23TYPE bit of PIER register) software can write 1 to clear this bit to 0" "0,1"
|
|
bitfld.long 0x00 2. "PWMIF2,PWM Channel 2 Period Interrupt Status\nThis bit is set by hardware when PWM2 counter reaches the requirement of interrupt (depend on INT23TYPE bit of PIER register) software can write 1 to clear this bit to 0" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "PWMIF1,PWM Channel 1 Period Interrupt Status\nThis bit is set by hardware when PWM1 counter reaches the requirement of interrupt (depend on INT01TYPE bit of PIER register) software can write 1 to clear this bit to 0" "0,1"
|
|
bitfld.long 0x00 0. "PWMIF0,PWM Channel 0 Period Interrupt Status\nThis bit is set by hardware when PWM0 counter reaches the requirement of interrupt (depend on INT01TYPE bit of PIER register) software can write 1 to clear this bit to 0" "0,1"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "CCR0,PWM Capture Control Register 0"
|
|
bitfld.long 0x00 23. "CFLRI1,CFLR1 Latched Indicator Bit\nWhen PWM group input channel 1 has a falling transition CFLR1 was latched with the value of PWM down-counter and this bit is set by hardware.\nSoftware can write 0 to clear this bit to 0 if BCn bit is 0 and can write.." "0,1"
|
|
bitfld.long 0x00 22. "CRLRI1,CRLR1 Latched Indicator Bit\nWhen PWM group input channel 1 has a rising transition CRLR1 was latched with the value of PWM down-counter and this bit is set by hardware.\nSoftware can write 0 to clear this bit to 0 if BCn bit is 0 and can write 1.." "0,1"
|
|
newline
|
|
bitfld.long 0x00 20. "CAPIF1,Channel 1 Capture Interrupt Indication Flag\nWrite 1 to clear this bit to 0" "0,1"
|
|
bitfld.long 0x00 19. "CAPCH1EN,Channel 1 Capture Function Enable Bit\nWhen Enabled Capture latched the PWM-counter and saved to CRLR (Rising latch) and CFLR (Falling latch).\nWhen Disabled Capture does not update CRLR and CFLR and disable PWM group channel 1 Interrupt" "0: Capture function on PWM group channel 1..,1: Capture function on PWM group channel 1 Enabled"
|
|
newline
|
|
bitfld.long 0x00 18. "CFL_IE1,Channel 1 Falling Latch Interrupt Enable Bit\nWhen Enabled if Capture detects PWM group channel 1 has falling transition Capture will issue an Interrupt" "0: Falling latch interrupt Disabled,1: Falling latch interrupt Enabled"
|
|
bitfld.long 0x00 17. "CRL_IE1,Channel 1 Rising Latch Interrupt Enable Bit\nWhen Enabled if Capture detects PWM group channel 1 has rising transition Capture will issue an Interrupt" "0: Rising latch interrupt Disabled,1: Rising latch interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x00 16. "INV1,Channel 1 Inverter Enable Bit" "0: Inverter Disabled,1: Inverter Enabled"
|
|
bitfld.long 0x00 7. "CFLRI0,CFLR0 Latched Indicator\nWhen PWM group input channel 0 has a falling transition CFLR0 was latched with the value of PWM down-counter and this bit is set by hardware.\nSoftware can write 0 to clear this bit to 0 if the BCn bit is 0 and can write.." "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "CRLRI0,CRLR0 Latched Indicator\nWhen PWM group input channel 0 has a rising transition CRLR0 was latched with the value of PWM down-counter and this bit is set by hardware.\nSoftware can write 0 to clear this bit to 0 if the BCn bit is 0 and can write 1.." "0,1"
|
|
bitfld.long 0x00 4. "CAPIF0,Channel 0 Capture Interrupt Indication Flag\nWrite 1 to clear this bit to 0" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "CAPCH0EN,Channel 0 Capture Function Enable\nWhen Enabled Capture latched the PWM-counter value and saved to CRLR (Rising latch) and CFLR (Falling latch).\nWhen Disabled Capture does not update CRLR and CFLR and disable PWM group channel 0 Interrupt" "0: Capture function on PWM group channel 0..,1: Capture function on PWM group channel 0 Enabled"
|
|
bitfld.long 0x00 2. "CFL_IE0,Channel 0 Falling Latch Interrupt Enable Bit\nWhen Enabled if Capture detects PWM group channel 0 has falling transition Capture will issue an Interrupt" "0: Falling latch interrupt Disabled,1: Falling latch interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. "CRL_IE0,Channel 0 Rising Latch Interrupt Enable Bit\nWhen Enabled if Capture detects PWM group channel 0 has rising transition Capture will issue an Interrupt" "0: Rising latch interrupt Disabled,1: Rising latch interrupt Enabled"
|
|
bitfld.long 0x00 0. "INV0,Channel 0 Inverter Enable Bit" "0: Inverter Disabled,1: Inverter Enabled"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "CCR2,PWM Capture Control Register 2"
|
|
bitfld.long 0x00 23. "CFLRI3,CFLR3 Latched Indicator\nWhen PWM group input channel 3 has a falling transition CFLR3 was latched with the value of PWM down-counter and this bit is set by hardware.\nSoftware can write 0 to clear this bit to 0 if the BCn bit is 0 and can write.." "0,1"
|
|
bitfld.long 0x00 22. "CRLRI3,CRLR3 Latched Indicator\nWhen PWM group input channel 3 has a rising transition CRLR3 was latched with the value of PWM down-counter and this bit is set by hardware.\nSoftware can write 0 to clear this bit to 0 if the BCn bit is 0 and can write 1.." "0,1"
|
|
newline
|
|
bitfld.long 0x00 20. "CAPIF3,Channel 3 Capture Interrupt Indication Flag\nWrite 1 to clear this bit to 0" "0,1"
|
|
bitfld.long 0x00 19. "CAPCH3EN,Channel 3 Capture Function Enable Bit\nWhen Enabled Capture latched the PWM-counter and saved to CRLR (Rising latch) and CFLR (Falling latch).\nWhen Disabled Capture does not update CRLR and CFLR and disable PWM group channel 3 Interrupt" "0: Capture function on PWM group channel 3..,1: Capture function on PWM group channel 3 Enabled"
|
|
newline
|
|
bitfld.long 0x00 18. "CFL_IE3,Channel 3 Falling Latch Interrupt Enable Bit\nWhen Enabled if Capture detects PWM group channel 3 has falling transition Capture will issue an Interrupt" "0: Falling latch interrupt Disabled,1: Falling latch interrupt Enabled"
|
|
bitfld.long 0x00 17. "CRL_IE3,Channel 3 Rising Latch Interrupt Enable Bit\nWhen Enabled if Capture detects PWM group channel 3 has rising transition Capture will issue an Interrupt" "0: Rising latch interrupt Disabled,1: Rising latch interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x00 16. "INV3,Channel 3 Inverter Enable Bit" "0: Inverter Disabled,1: Inverter Enabled"
|
|
bitfld.long 0x00 7. "CFLRI2,CFLR2 Latched Indicator\nWhen PWM group input channel 2 has a falling transition CFLR2 was latched with the value of PWM down-counter and this bit is set by hardware.\nSoftware can write 0 to clear this bit to 0 if BCn bit is 0 and can write 1 to.." "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "CRLRI2,CRLR2 Latched Indicator\nWhen PWM group input channel 2 has a rising transition CRLR2 was latched with the value of PWM down-counter and this bit is set by hardware.\nSoftware can write 0 to clear this bit to 0 if the BCn bit is 0 and can write 1.." "0,1"
|
|
bitfld.long 0x00 4. "CAPIF2,Channel 2 Capture Interrupt Indication Flag\nWrite 1 to clear this bit to 0" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "CAPCH2EN,Channel 2 Capture Function Enable Bit\nWhen Enabled Capture latched the PWM-counter value and saved to CRLR (Rising latch) and CFLR (Falling latch).\nWhen Disabled Capture does not update CRLR and CFLR and disable PWM group channel 2 Interrupt" "0: Capture function on PWM group channel 2..,1: Capture function on PWM group channel 2 Enabled"
|
|
bitfld.long 0x00 2. "CFL_IE2,Channel 2 Falling Latch Interrupt Enable Bit\nWhen Enabled if Capture detects PWM group channel 2 has falling transition Capture will issue an Interrupt" "0: Falling latch interrupt Disabled,1: Falling latch interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. "CRL_IE2,Channel 2 Rising Latch Interrupt Enable Bit\nWhen Enabled if Capture detects PWM group channel 2 has rising transition Capture will issue an Interrupt" "0: Rising latch interrupt Disabled,1: Rising latch interrupt Enabled"
|
|
bitfld.long 0x00 0. "INV2,Channel 2 Inverter Enable Bit" "0: Inverter Disabled,1: Inverter Enabled"
|
|
rgroup.long 0x58++0x03
|
|
line.long 0x00 "CRLR0,PWM Capture Rising Latch Register (Channel 0)"
|
|
hexmask.long.word 0x00 0.--15. 1. "CRLRx,Capture Rising Latch Register\nLatch the PWM counter when Channel 0/1/2/3 has rising transition"
|
|
rgroup.long 0x5C++0x03
|
|
line.long 0x00 "CFLR0,PWM Capture Falling Latch Register (Channel 0)"
|
|
hexmask.long.word 0x00 0.--15. 1. "CFLRx,Capture Falling Latch Register\nLatch the PWM counter when Channel 0/1/2/3 has Falling transition"
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "CRLR1,PWM Capture Rising Latch Register (Channel 1)"
|
|
hexmask.long.word 0x00 0.--15. 1. "CRLRx,Capture Rising Latch Register\nLatch the PWM counter when Channel 0/1/2/3 has rising transition"
|
|
group.long 0x64++0x03
|
|
line.long 0x00 "CFLR1,PWM Capture Falling Latch Register (Channel 1)"
|
|
hexmask.long.word 0x00 0.--15. 1. "CFLRx,Capture Falling Latch Register\nLatch the PWM counter when Channel 0/1/2/3 has Falling transition"
|
|
group.long 0x68++0x03
|
|
line.long 0x00 "CRLR2,PWM Capture Rising Latch Register (Channel 2)"
|
|
hexmask.long.word 0x00 0.--15. 1. "CRLRx,Capture Rising Latch Register\nLatch the PWM counter when Channel 0/1/2/3 has rising transition"
|
|
group.long 0x6C++0x03
|
|
line.long 0x00 "CFLR2,PWM Capture Falling Latch Register (Channel 2)"
|
|
hexmask.long.word 0x00 0.--15. 1. "CFLRx,Capture Falling Latch Register\nLatch the PWM counter when Channel 0/1/2/3 has Falling transition"
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "CRLR3,PWM Capture Rising Latch Register (Channel 3)"
|
|
hexmask.long.word 0x00 0.--15. 1. "CRLRx,Capture Rising Latch Register\nLatch the PWM counter when Channel 0/1/2/3 has rising transition"
|
|
group.long 0x74++0x03
|
|
line.long 0x00 "CFLR3,PWM Capture Falling Latch Register (Channel 3)"
|
|
hexmask.long.word 0x00 0.--15. 1. "CFLRx,Capture Falling Latch Register\nLatch the PWM counter when Channel 0/1/2/3 has Falling transition"
|
|
group.long 0x78++0x03
|
|
line.long 0x00 "CAPENR,PWM Capture Input 0~3 Enable Register"
|
|
bitfld.long 0x00 3. "CINEN3,Channel 3 Capture Input Enable Bit" "0: PWM Channel 3 capture input path Disabled,1: PWM Channel 3 capture input path Enabled"
|
|
bitfld.long 0x00 2. "CINEN2,Channel 2 Capture Input Enable Bit" "0: PWM Channel 2 capture input path Disabled,1: PWM Channel 2 capture input path Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. "CINEN1,Channel 1 Capture Input Enable Bit" "0: PWM Channel 1 capture input path Disabled,1: PWM Channel 1 capture input path Enabled"
|
|
bitfld.long 0x00 0. "CINEN0,Channel 0 Capture Input Enable Bit" "0: PWM Channel 0 capture input path Disabled,1: PWM Channel 0 capture input path Enabled"
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "POE,PWM Output Enable for Channel 0~3"
|
|
bitfld.long 0x00 3. "POE3,Channel 3 Output Enable Bit\nNote: The corresponding GPIO pin must also be switched to PWM function" "0: PWM channel 3 output to pin Disabled,1: PWM channel 3 output to pin Enabled"
|
|
bitfld.long 0x00 2. "POE2,Channel 2 Output Enable Bit\nNote: The corresponding GPIO pin must also be switched to PWM function" "0: PWM channel 2 output to pin Disabled,1: PWM channel 2 output to pin Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. "POE1,Channel 1 Output Enable Bit\nNote: The corresponding GPIO pin must also be switched to PWM function" "0: PWM channel 1 output to pin Disabled,1: PWM channel 1 output to pin Enabled"
|
|
bitfld.long 0x00 0. "POE0,Channel 0 Output Enable Bit\nNote: The corresponding GPIO pin must also be switched to PWM function" "0: PWM channel 0 output to pin Disabled,1: PWM channel 0 output to pin Enabled"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "TCON,PWM Trigger Control for Channel 0~3"
|
|
bitfld.long 0x00 3. "PWM3TEN,Channel 3 Center-Aligned Trigger Enable Bit\nPWM can trigger ADC to start conversion when PWM counter up count to CNR if this bit is set to 1.\nNote: This function is only supported when PWM operating at Center-aligned type" "0: PWM channel 3 trigger ADC function Disabled,1: PWM channel 3 trigger ADC function Enabled"
|
|
bitfld.long 0x00 2. "PWM2TEN,Channel 2 Center-Aligned Trigger Enable Bit\nPWM can trigger ADC to start conversion when PWM counter up count to CNR if this bit is set to 1.\nNote: This function is only supported when PWM operating at Center-aligned type" "0: PWM channel 2 trigger ADC function Disabled,1: PWM channel 2 trigger ADC function Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. "PWM1TEN,Channel 1 Center-Aligned Trigger Enable Bit\nPWM can trigger ADC to start conversion when PWM counter up count to CNR if this bit is set to 1.\nNote: This function is only supported when PWM operating at Center-aligned type" "0: PWM channel 1 trigger ADC function Disabled,1: PWM channel 1 trigger ADC function Enabled"
|
|
bitfld.long 0x00 0. "PWM0TEN,Channel 0 Center-Aligned Trigger Enable Bit\nPWM can trigger ADC to start conversion when PWM counter up count to CNR if this bit is set to 1.\nNote: This function is only supported when PWM operating at Center-aligned type" "0: PWM channel 0 trigger ADC function Disabled,1: PWM channel 0 trigger ADC function Enabled"
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "TSTATUS,PWM Trigger Status Register"
|
|
bitfld.long 0x00 3. "PWM3TF,Channel 3 Center-Aligned Trigger Flag\nFor Center-aligned Operating mode this bit is set to 1 by hardware when PWM counter up count to CNR if PWM3TEN bit is set to 1" "0,1"
|
|
bitfld.long 0x00 2. "PWM2TF,Channel 2 Center-Aligned Trigger Flag\nFor Center-aligned Operating mode this bit is set to 1 by hardware when PWM counter up count to CNR if PWM2TEN bit is set to 1" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "PWM1TF,Channel 1 Center-Aligned Trigger Flag\nFor Center-aligned Operating mode this bit is set to 1 by hardware when PWM counter up count to CNR if PWM1TEN bit is set to 1" "0,1"
|
|
bitfld.long 0x00 0. "PWM0TF,Channel 0 Center-Aligned Trigger Flag\nFor Center-aligned Operating mode this bit is set to 1 by hardware when PWM counter up counts to CNR if PWM0TEN bit is set to 1" "0,1"
|
|
rgroup.long 0x88++0x03
|
|
line.long 0x00 "SYNCBUSY0,PWM0 Synchronous Busy Status Register"
|
|
bitfld.long 0x00 0. "S_BUSY,PWM Synchronous Busy\nWhen software writes CNR0/CMR0/PPR or switches PWM0 operation mode (PCR[3]) PWM will have a busy time to update these values completely because PWM clock may be different from system clock domain" "0,1"
|
|
rgroup.long 0x8C++0x03
|
|
line.long 0x00 "SYNCBUSY1,PWM1 Synchronous Busy Status Register"
|
|
bitfld.long 0x00 0. "S_BUSY,PWM Synchronous Busy\nWhen Software writes CNR1/CMR1/PPR or switches PWM1 operation mode (PCR[11]) PWM will have a busy time to update these values completely because PWM clock may be different from system clock domain" "0,1"
|
|
rgroup.long 0x90++0x03
|
|
line.long 0x00 "SYNCBUSY2,PWM2 Synchronous Busy Status Register"
|
|
bitfld.long 0x00 0. "S_BUSY,PWM Synchronous Busy\nWhen Software writes CNR2/CMR2/PPR or switch PWM2 operation mode (PCR[19]) PWM will have a busy time to update these values completely because PWM clock may be different from system clock domain" "0,1"
|
|
rgroup.long 0x94++0x03
|
|
line.long 0x00 "SYNCBUSY3,PWM3 Synchronous Busy Status Register"
|
|
bitfld.long 0x00 0. "S_BUSY,PWM Synchronous Busy\nWhen Software writes CNR3/CMR3/PPR or switch PWM3 operation mode (PCR[27]) PWM will have a busy time to update these values completely because PWM clock may be different from system clock domain" "0,1"
|
|
tree.end
|
|
tree "PWMB"
|
|
base ad:0x40140000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "PPR,PWM Prescaler Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DZI23,Dead-Zone Interval For Pair Of Channel2 And Channel3 (PWM2 And PWM3 Pair For PWM Group A)\nThese 8-bit determine the Dead-zone length"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DZI01,Dead-Zone Interval For Pair Of Channel 0 And Channel 1 (PWM0 And PWM1 Pair For PWM Group A PWM4 And PWM5 Pair For PWM Group B)\nThese 8-bit determine the Dead-zone length"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "CP23,Clock Prescaler 2 (PWM-Timer2 / 3 For Group A)\nClock input is divided by (CP23 + 1) before it is fed to the corresponding PWM-timer"
|
|
hexmask.long.byte 0x00 0.--7. 1. "CP01,Clock Prescaler 0 (PWM-Timer 0 / 1 For Group A And PWM-Timer 4 / 5 For Group B)\nClock input is divided by (CP01 + 1) before it is fed to the corresponding PWM-timer"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CSR,PWM Clock Source Divider Select Register"
|
|
bitfld.long 0x00 12.--14. "CSR3,PWM Timer 3 Clock Source Divider Selection (PWM Timer 3 For Group A)\nSelect clock source divider for PWM timer 3" "0: 0,1: 1,2: 2,3: 16,4: 4,?..."
|
|
bitfld.long 0x00 8.--10. "CSR2,PWM Timer 2 Clock Source Divider Selection (PWM Timer 2 For Group A)\nSelect clock source divider for PWM timer 2.\n(Table is the same as CSR3)" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 4.--6. "CSR1,PWM Timer 1 Clock Source Divider Selection (PWM Timer 1 For Group A And PWM Timer 5 For Group B)\nSelect clock source divider for PWM timer 1.\n(Table is the same as CSR3)" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. "CSR0,PWM Timer 0 Clock Source Divider Selection (PWM Timer 0 For Group A And PWM Timer 4 For Group B)\nSelect clock source divider for PWM timer 0.\n(Table is the same as CSR3)" "0,1,2,3,4,5,6,7"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "PCR,PWM Control Register"
|
|
bitfld.long 0x00 31. "PWM23TYPE,PWM23 Aligned Type Selection (PWM2 And PWM3 Pair For PWM Group A)" "0: Edge-aligned type,1: Center-aligned type"
|
|
bitfld.long 0x00 30. "PWM01TYPE,PWM01 Aligned Type Selection (PWM0 And PWM1 Pair For PWM Group A PWM4 And PWM5 Pair For PWM Group B)" "0: Edge-aligned type,1: Center-aligned type"
|
|
newline
|
|
bitfld.long 0x00 27. "CH3MOD,PWM-Timer 3 Auto-Reload/One-Shot Mode (PWM Timer 3 For Group A)\nNote: If there is a transition at this bit it will cause CNR3 and CMR3 be cleared" "0: One-shot mode,1: Auto-reload mode"
|
|
bitfld.long 0x00 26. "CH3INV,PWM-Timer 3 Output Inverter Enable (PWM Timer 3 For Group A)" "0: Inverter Disabled,1: Inverter Enabled"
|
|
newline
|
|
bitfld.long 0x00 25. "CH3PINV,PWM-Timer 3 Output Polar Inverse Enable (PWM Timer 3 For Group A)" "0: PWM3 output polar inverse Disable,1: PWM3 output polar inverse Enable"
|
|
bitfld.long 0x00 24. "CH3EN,PWM-Timer 3 Enable (PWM Timer 3 For Group A)" "0: Corresponding PWM-Timer Stopped,1: Corresponding PWM-Timer Start Running"
|
|
newline
|
|
bitfld.long 0x00 19. "CH2MOD,PWM-Timer 2 Auto-Reload/One-Shot Mode (PWM Timer 2 For Group A)\nNote: If there is a transition at this bit it will cause CNR2 and CMR2 be cleared" "0: One-shot mode,1: Auto-reload mode"
|
|
bitfld.long 0x00 18. "CH2INV,PWM-Timer 2 Output Inverter Enable (PWM Timer 2 For Group A)" "0: Inverter Disabled,1: Inverter Enabled"
|
|
newline
|
|
bitfld.long 0x00 17. "CH2PINV,PWM-Timer 2 Output Polar Inverse Enable (PWM Timer 2 For Group A)" "0: PWM2 output polar inverse Disabled,1: PWM2 output polar inverse Enabled"
|
|
bitfld.long 0x00 16. "CH2EN,PWM-Timer 2 Enable (PWM Timer 2 For Group A)" "0: Corresponding PWM-Timer Stopped,1: Corresponding PWM-Timer Start Running"
|
|
newline
|
|
bitfld.long 0x00 11. "CH1MOD,PWM-Timer 1 Auto-Reload/One-Shot Mode (PWM Timer 1 For Group A And PWM Timer 5 For Group B)\nNote: If there is a transition at this bit it will cause CNR1 and CMR1 be cleared" "0: One-shot mode,1: Auto-reload mode"
|
|
bitfld.long 0x00 10. "CH1INV,PWM-Timer 1 Output Inverter Enable (PWM Timer 1 For Group A And PWM Timer 5 For Group B)" "0: Inverter Disable,1: Inverter Enable"
|
|
newline
|
|
bitfld.long 0x00 9. "CH1PINV,PWM-Timer 1 Output Polar Inverse Enable (PWM Timer 1 For Group A And PWM Timer 5 For Group B)" "0: PWM1 output polar inverse Disabled,1: PWM1 output polar inverse Enabled"
|
|
bitfld.long 0x00 8. "CH1EN,PWM-Timer 1 Enable (PWM Timer 1 For Group A And PWM Timer 5 For Group B)" "0: Corresponding PWM-Timer Stopped,1: Corresponding PWM-Timer Start Running"
|
|
newline
|
|
bitfld.long 0x00 5. "DZEN23,Dead-Zone 2 Generator Enable (PWM2 And PWM3 Pair For PWM Group A)\nNote: When Dead-zone generator is enabled the pair of PWM2 and PWM3 becomes a complementary pair for PWM group A" "0: Disabled,1: Enabled"
|
|
bitfld.long 0x00 4. "DZEN01,Dead-Zone 0 Generator Enable (PWM0 And PWM1 Pair For PWM Group A PWM4 And PWM5 Pair For PWM Group B)\nNote: When Dead-zone generator is enabled the pair of PWM0 and PWM1 becomes a complementary pair for PWM group A and the pair of PWM4 and PWM5.." "0: Disabled,1: Enabled"
|
|
newline
|
|
bitfld.long 0x00 3. "CH0MOD,PWM-Timer 0 Auto-Reload/One-Shot Mode (PWM Timer 0 For Group A And PWM Timer 4 For Group B)\nNote: If there is a transition at this bit it will cause CNR0 and CMR0 be cleared" "0: One-shot mode,1: Auto-reload mode"
|
|
bitfld.long 0x00 2. "CH0INV,PWM-Timer 0 Output Inverter Enable (PWM Timer 0 For Group A And PWM Timer 4 For Group B)" "0: Inverter Disabled,1: Inverter Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. "CH0PINV,PWM-Timer 0 Output Polar Inverse Enable (PWM Timer 0 For Group A And PWM Timer 4 For Group B)" "0: PWM0 output polar inverse Disabled,1: PWM0 output polar inverse Enabled"
|
|
bitfld.long 0x00 0. "CH0EN,PWM-Timer 0 Enable (PWM Timer 0 For Group A And PWM Timer 4 For Group B)" "0: The corresponding PWM-Timer stops running,1: The corresponding PWM-Timer starts running"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "CNR0,PWM Counter Register 0"
|
|
hexmask.long.word 0x00 0.--15. 1. "CNRx,PWM Timer Loaded Value\nCNR determines the PWM period.\nNote: Any write to CNR will take effect in next PWM cycle.\nNote: When PWM operating at Center-aligned type CNR value should be set between 0x0000 to 0xFFFE"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "CMR0,PWM Comparator Register 0"
|
|
hexmask.long.word 0x00 0.--15. 1. "CMRx,PWM Comparator Register\nCMR determines the PWM duty.\nNote: Any write to CNR will take effect in next PWM cycle"
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "PDR0,PWM Data Register 0"
|
|
hexmask.long.word 0x00 0.--15. 1. "PDRx,PWM Data Register\nUser can monitor PDR to know the current value in 16-bit counter"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "CNR1,PWM Counter Register 1"
|
|
hexmask.long.word 0x00 0.--15. 1. "CNRx,PWM Timer Loaded Value\nCNR determines the PWM period.\nNote: Any write to CNR will take effect in next PWM cycle.\nNote: When PWM operating at Center-aligned type CNR value should be set between 0x0000 to 0xFFFE"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "CMR1,PWM Comparator Register 1"
|
|
hexmask.long.word 0x00 0.--15. 1. "CMRx,PWM Comparator Register\nCMR determines the PWM duty.\nNote: Any write to CNR will take effect in next PWM cycle"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "PDR1,PWM Data Register 1"
|
|
hexmask.long.word 0x00 0.--15. 1. "PDRx,PWM Data Register\nUser can monitor PDR to know the current value in 16-bit counter"
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "PBCR,PWM Backward Compatible Register"
|
|
bitfld.long 0x00 0. "BCn,PWM Backward Compatible Register\nRefer to the CCR0/CCR2 register bit 6 7 22 23 description\nNote: It is recommended that this bit be set to 1 to prevent CFLRIx and CRLRIx from being cleared when writing CCR0/CCR2" "0: Configure write 0 to clear CFLRI0~3 and..,1: Configure write 1 to clear CFLRI0~3 and.."
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "PIER,PWM Interrupt Enable Register"
|
|
bitfld.long 0x00 17. "INT23TYPE,PWM23 Interrupt Period Type Selection Bit (PWM2 And PWM3 Pair For PWM Group A)\nNote: This bit is effective when PWM in Center-aligned type only" "0: PWMIFn will be set if PWM counter underflow,1: PWMIFn will be set if PWM counter matches.."
|
|
bitfld.long 0x00 16. "INT01TYPE,PWM01 Interrupt Period Type Selection Bit (PWM0 And PWM1 Pair For PWM Group A PWM4 And PWM5 Pair For PWM Group B)\nNote: This bit is effective when PWM in Center-aligned type only" "0: PWMIFn will be set if PWM counter underflow,1: PWMIFn will be set if PWM counter matches.."
|
|
newline
|
|
bitfld.long 0x00 11. "PWMDIE3,PWM Channel 3 Duty Interrupt Enable Bit" "0: Disabled,1: Enabled"
|
|
bitfld.long 0x00 10. "PWMDIE2,PWM Channel 2 Duty Interrupt Enable Bit" "0: Disabled,1: Enabled"
|
|
newline
|
|
bitfld.long 0x00 9. "PWMDIE1,PWM Channel 1 Duty Interrupt Enable Bit" "0: Disabled,1: Enabled"
|
|
bitfld.long 0x00 8. "PWMDIE0,PWM Channel 0 Duty Interrupt Enable Bit" "0: Disabled,1: Enabled"
|
|
newline
|
|
bitfld.long 0x00 3. "PWMIE3,PWM Channel 3 Period Interrupt Enable Bit" "0: Disabled,1: Enabled"
|
|
bitfld.long 0x00 2. "PWMIE2,PWM Channel 2 Period Interrupt Enable Bit" "0: Disabled,1: Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. "PWMIE1,PWM Channel 1 Period Interrupt Enable Bit" "0: Disabled,1: Enabled"
|
|
bitfld.long 0x00 0. "PWMIE0,PWM Channel 0 Period Interrupt Enable Bit" "0: Disabled,1: Enabled"
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "PIIR,PWM Interrupt Indication Register"
|
|
bitfld.long 0x00 11. "PWMDIF3,PWM Channel 3 Duty Interrupt Flag\nFlag is set by hardware when channel 3 PWM counter down count and reaches CMR3 software can clear this bit by writing a one to it.\nNote: If CMR equal to CNR this flag is not working in Edge-aligned type.." "0,1"
|
|
bitfld.long 0x00 10. "PWMDIF2,PWM Channel 2 Duty Interrupt Flag\nFlag is set by hardware when channel 2 PWM counter down count and reaches CMR2 software can clear this bit by writing a one to it.\nNote: If CMR equal to CNR this flag is not working in Edge-aligned type.." "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "PWMDIF1,PWM Channel 1 Duty Interrupt Flag\nFlag is set by hardware when channel 1 PWM counter down count and reaches CMR1 software can clear this bit by writing a one to it.\nNote: If CMR equal to CNR this flag is not working in Edge-aligned type.." "0,1"
|
|
bitfld.long 0x00 8. "PWMDIF0,PWM Channel 0 Duty Interrupt Flag\nFlag is set by hardware when channel 0 PWM counter down count and reaches CMR0 software can clear this bit by writing a one to it.\nNote: If CMR equal to CNR this flag is not working in Edge-aligned type.." "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "PWMIF3,PWM Channel 3 Period Interrupt Status\nThis bit is set by hardware when PWM3 counter reaches the requirement of interrupt (depend on INT23TYPE bit of PIER register) software can write 1 to clear this bit to 0" "0,1"
|
|
bitfld.long 0x00 2. "PWMIF2,PWM Channel 2 Period Interrupt Status\nThis bit is set by hardware when PWM2 counter reaches the requirement of interrupt (depend on INT23TYPE bit of PIER register) software can write 1 to clear this bit to 0" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "PWMIF1,PWM Channel 1 Period Interrupt Status\nThis bit is set by hardware when PWM1 counter reaches the requirement of interrupt (depend on INT01TYPE bit of PIER register) software can write 1 to clear this bit to 0" "0,1"
|
|
bitfld.long 0x00 0. "PWMIF0,PWM Channel 0 Period Interrupt Status\nThis bit is set by hardware when PWM0 counter reaches the requirement of interrupt (depend on INT01TYPE bit of PIER register) software can write 1 to clear this bit to 0" "0,1"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "CCR0,PWM Capture Control Register 0"
|
|
bitfld.long 0x00 23. "CFLRI1,CFLR1 Latched Indicator Bit\nWhen PWM group input channel 1 has a falling transition CFLR1 was latched with the value of PWM down-counter and this bit is set by hardware.\nSoftware can write 0 to clear this bit to 0 if BCn bit is 0 and can write.." "0,1"
|
|
bitfld.long 0x00 22. "CRLRI1,CRLR1 Latched Indicator Bit\nWhen PWM group input channel 1 has a rising transition CRLR1 was latched with the value of PWM down-counter and this bit is set by hardware.\nSoftware can write 0 to clear this bit to 0 if BCn bit is 0 and can write 1.." "0,1"
|
|
newline
|
|
bitfld.long 0x00 20. "CAPIF1,Channel 1 Capture Interrupt Indication Flag\nWrite 1 to clear this bit to 0" "0,1"
|
|
bitfld.long 0x00 19. "CAPCH1EN,Channel 1 Capture Function Enable Bit\nWhen Enabled Capture latched the PWM-counter and saved to CRLR (Rising latch) and CFLR (Falling latch).\nWhen Disabled Capture does not update CRLR and CFLR and disable PWM group channel 1 Interrupt" "0: Capture function on PWM group channel 1..,1: Capture function on PWM group channel 1 Enabled"
|
|
newline
|
|
bitfld.long 0x00 18. "CFL_IE1,Channel 1 Falling Latch Interrupt Enable Bit\nWhen Enabled if Capture detects PWM group channel 1 has falling transition Capture will issue an Interrupt" "0: Falling latch interrupt Disabled,1: Falling latch interrupt Enabled"
|
|
bitfld.long 0x00 17. "CRL_IE1,Channel 1 Rising Latch Interrupt Enable Bit\nWhen Enabled if Capture detects PWM group channel 1 has rising transition Capture will issue an Interrupt" "0: Rising latch interrupt Disabled,1: Rising latch interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x00 16. "INV1,Channel 1 Inverter Enable Bit" "0: Inverter Disabled,1: Inverter Enabled"
|
|
bitfld.long 0x00 7. "CFLRI0,CFLR0 Latched Indicator\nWhen PWM group input channel 0 has a falling transition CFLR0 was latched with the value of PWM down-counter and this bit is set by hardware.\nSoftware can write 0 to clear this bit to 0 if the BCn bit is 0 and can write.." "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "CRLRI0,CRLR0 Latched Indicator\nWhen PWM group input channel 0 has a rising transition CRLR0 was latched with the value of PWM down-counter and this bit is set by hardware.\nSoftware can write 0 to clear this bit to 0 if the BCn bit is 0 and can write 1.." "0,1"
|
|
bitfld.long 0x00 4. "CAPIF0,Channel 0 Capture Interrupt Indication Flag\nWrite 1 to clear this bit to 0" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "CAPCH0EN,Channel 0 Capture Function Enable\nWhen Enabled Capture latched the PWM-counter value and saved to CRLR (Rising latch) and CFLR (Falling latch).\nWhen Disabled Capture does not update CRLR and CFLR and disable PWM group channel 0 Interrupt" "0: Capture function on PWM group channel 0..,1: Capture function on PWM group channel 0 Enabled"
|
|
bitfld.long 0x00 2. "CFL_IE0,Channel 0 Falling Latch Interrupt Enable Bit\nWhen Enabled if Capture detects PWM group channel 0 has falling transition Capture will issue an Interrupt" "0: Falling latch interrupt Disabled,1: Falling latch interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. "CRL_IE0,Channel 0 Rising Latch Interrupt Enable Bit\nWhen Enabled if Capture detects PWM group channel 0 has rising transition Capture will issue an Interrupt" "0: Rising latch interrupt Disabled,1: Rising latch interrupt Enabled"
|
|
bitfld.long 0x00 0. "INV0,Channel 0 Inverter Enable Bit" "0: Inverter Disabled,1: Inverter Enabled"
|
|
rgroup.long 0x58++0x03
|
|
line.long 0x00 "CRLR0,PWM Capture Rising Latch Register (Channel 0)"
|
|
hexmask.long.word 0x00 0.--15. 1. "CRLRx,Capture Rising Latch Register\nLatch the PWM counter when Channel 0/1/2/3 has rising transition"
|
|
rgroup.long 0x5C++0x03
|
|
line.long 0x00 "CFLR0,PWM Capture Falling Latch Register (Channel 0)"
|
|
hexmask.long.word 0x00 0.--15. 1. "CFLRx,Capture Falling Latch Register\nLatch the PWM counter when Channel 0/1/2/3 has Falling transition"
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "CRLR1,PWM Capture Rising Latch Register (Channel 1)"
|
|
hexmask.long.word 0x00 0.--15. 1. "CRLRx,Capture Rising Latch Register\nLatch the PWM counter when Channel 0/1/2/3 has rising transition"
|
|
group.long 0x64++0x03
|
|
line.long 0x00 "CFLR1,PWM Capture Falling Latch Register (Channel 1)"
|
|
hexmask.long.word 0x00 0.--15. 1. "CFLRx,Capture Falling Latch Register\nLatch the PWM counter when Channel 0/1/2/3 has Falling transition"
|
|
group.long 0x78++0x03
|
|
line.long 0x00 "CAPENR,PWM Capture Input 0~3 Enable Register"
|
|
bitfld.long 0x00 3. "CINEN3,Channel 3 Capture Input Enable Bit" "0: PWM Channel 3 capture input path Disabled,1: PWM Channel 3 capture input path Enabled"
|
|
bitfld.long 0x00 2. "CINEN2,Channel 2 Capture Input Enable Bit" "0: PWM Channel 2 capture input path Disabled,1: PWM Channel 2 capture input path Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. "CINEN1,Channel 1 Capture Input Enable Bit" "0: PWM Channel 1 capture input path Disabled,1: PWM Channel 1 capture input path Enabled"
|
|
bitfld.long 0x00 0. "CINEN0,Channel 0 Capture Input Enable Bit" "0: PWM Channel 0 capture input path Disabled,1: PWM Channel 0 capture input path Enabled"
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "POE,PWM Output Enable for Channel 0~3"
|
|
bitfld.long 0x00 3. "POE3,Channel 3 Output Enable Bit\nNote: The corresponding GPIO pin must also be switched to PWM function" "0: PWM channel 3 output to pin Disabled,1: PWM channel 3 output to pin Enabled"
|
|
bitfld.long 0x00 2. "POE2,Channel 2 Output Enable Bit\nNote: The corresponding GPIO pin must also be switched to PWM function" "0: PWM channel 2 output to pin Disabled,1: PWM channel 2 output to pin Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. "POE1,Channel 1 Output Enable Bit\nNote: The corresponding GPIO pin must also be switched to PWM function" "0: PWM channel 1 output to pin Disabled,1: PWM channel 1 output to pin Enabled"
|
|
bitfld.long 0x00 0. "POE0,Channel 0 Output Enable Bit\nNote: The corresponding GPIO pin must also be switched to PWM function" "0: PWM channel 0 output to pin Disabled,1: PWM channel 0 output to pin Enabled"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "TCON,PWM Trigger Control for Channel 0~3"
|
|
bitfld.long 0x00 3. "PWM3TEN,Channel 3 Center-Aligned Trigger Enable Bit\nPWM can trigger ADC to start conversion when PWM counter up count to CNR if this bit is set to 1.\nNote: This function is only supported when PWM operating at Center-aligned type" "0: PWM channel 3 trigger ADC function Disabled,1: PWM channel 3 trigger ADC function Enabled"
|
|
bitfld.long 0x00 2. "PWM2TEN,Channel 2 Center-Aligned Trigger Enable Bit\nPWM can trigger ADC to start conversion when PWM counter up count to CNR if this bit is set to 1.\nNote: This function is only supported when PWM operating at Center-aligned type" "0: PWM channel 2 trigger ADC function Disabled,1: PWM channel 2 trigger ADC function Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. "PWM1TEN,Channel 1 Center-Aligned Trigger Enable Bit\nPWM can trigger ADC to start conversion when PWM counter up count to CNR if this bit is set to 1.\nNote: This function is only supported when PWM operating at Center-aligned type" "0: PWM channel 1 trigger ADC function Disabled,1: PWM channel 1 trigger ADC function Enabled"
|
|
bitfld.long 0x00 0. "PWM0TEN,Channel 0 Center-Aligned Trigger Enable Bit\nPWM can trigger ADC to start conversion when PWM counter up count to CNR if this bit is set to 1.\nNote: This function is only supported when PWM operating at Center-aligned type" "0: PWM channel 0 trigger ADC function Disabled,1: PWM channel 0 trigger ADC function Enabled"
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "TSTATUS,PWM Trigger Status Register"
|
|
bitfld.long 0x00 3. "PWM3TF,Channel 3 Center-Aligned Trigger Flag\nFor Center-aligned Operating mode this bit is set to 1 by hardware when PWM counter up count to CNR if PWM3TEN bit is set to 1" "0,1"
|
|
bitfld.long 0x00 2. "PWM2TF,Channel 2 Center-Aligned Trigger Flag\nFor Center-aligned Operating mode this bit is set to 1 by hardware when PWM counter up count to CNR if PWM2TEN bit is set to 1" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "PWM1TF,Channel 1 Center-Aligned Trigger Flag\nFor Center-aligned Operating mode this bit is set to 1 by hardware when PWM counter up count to CNR if PWM1TEN bit is set to 1" "0,1"
|
|
bitfld.long 0x00 0. "PWM0TF,Channel 0 Center-Aligned Trigger Flag\nFor Center-aligned Operating mode this bit is set to 1 by hardware when PWM counter up counts to CNR if PWM0TEN bit is set to 1" "0,1"
|
|
rgroup.long 0x88++0x03
|
|
line.long 0x00 "SYNCBUSY0,PWM0 Synchronous Busy Status Register"
|
|
bitfld.long 0x00 0. "S_BUSY,PWM Synchronous Busy\nWhen software writes CNR0/CMR0/PPR or switches PWM0 operation mode (PCR[3]) PWM will have a busy time to update these values completely because PWM clock may be different from system clock domain" "0,1"
|
|
rgroup.long 0x8C++0x03
|
|
line.long 0x00 "SYNCBUSY1,PWM1 Synchronous Busy Status Register"
|
|
bitfld.long 0x00 0. "S_BUSY,PWM Synchronous Busy\nWhen Software writes CNR1/CMR1/PPR or switches PWM1 operation mode (PCR[11]) PWM will have a busy time to update these values completely because PWM clock may be different from system clock domain" "0,1"
|
|
tree.end
|
|
tree.end
|
|
tree "RTC"
|
|
base ad:0x40008000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "INIR,RTC Initiation Register"
|
|
hexmask.long 0x00 1.--31. 1. "INIR,RTC Initiation\nWhen RTC block is powered on RTC is at reset state"
|
|
rbitfld.long 0x00 0. "INIR_Active,RTC Active Status (Read Only)" "0: RTC is at reset state,1: RTC is at normal active state"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "AER,RTC Access Enable Register"
|
|
rbitfld.long 0x00 16. "ENF,RTC Register Access Enable Flag (Read Only)\nNote: This bit will be set after AER[15:0] is load a 0xA965 and will be cleared automatically after 1024 RTC clocks" "0: RTC register read/write access Disabled,1: RTC register read/write access Enabled"
|
|
hexmask.long.word 0x00 0.--15. 1. "AER,RTC Register Access Enable Password (Write Only)\nWriting 0xA965 to this register will enable RTC access and keep 1024 RTC clocks"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "FCR,RTC Frequency Compensation Register"
|
|
bitfld.long 0x00 8.--11. "INTEGER,Integer Part\nPlease refer to 6.12.5.4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--5. "FRACTION,Fraction Part\nNote: Digit in FCR must be expressed as hexadecimal number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "TLR,Time Loading Register"
|
|
bitfld.long 0x00 20.--21. "_10HR,10-Hour Time Digit (0~2)" "0,1,2,3"
|
|
bitfld.long 0x00 16.--19. "_1HR,1-Hour Time Digit (0~9)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 12.--14. "_10MIN,10-Min Time Digit (0~5)" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8.--11. "_1MIN,1-Min Time Digit (0~9)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 4.--6. "_10SEC,10-Sec Time Digit (0~5)" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--3. "_1SEC,1-Sec Time Digit (0~9)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "CLR,Calendar Loading Register"
|
|
bitfld.long 0x00 20.--23. "_10YEAR,10-Year Calendar Digit (0~9)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. "_1YEAR,1-Year Calendar Digit (0~9)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 12. "_10MON,10-Month Calendar Digit (0~1)" "0,1"
|
|
bitfld.long 0x00 8.--11. "_1MON,1-Month Calendar Digit (0~9)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 4.--5. "_10DAY,10-Day Calendar Digit (0~3)" "0,1,2,3"
|
|
bitfld.long 0x00 0.--3. "_1DAY,1-Day Calendar Digit (0~9)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "TSSR,Time Scale Selection Register"
|
|
bitfld.long 0x00 0. "_24H_12H,24-Hour / 12-Hour Time Scale Selection\nIt indicates that RTC TLR and TAR counter are in 24-hour time scale or 12-hour time scale" "0: 24-hour time scale selected,1: 24-hour time scale selected"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "DWR,Day of the Week Register"
|
|
bitfld.long 0x00 0.--2. "DWR,Day Of The Week Register" "0: Sunday,1: Monday,2: Tuesday,3: Wednesday,4: Thursday,5: Friday,6: Saturday,7: Reserved"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "TAR,Time Alarm Register"
|
|
bitfld.long 0x00 20.--21. "_10HR,10-Hour Time Digit of Alarm Setting (0~2)" "0,1,2,3"
|
|
bitfld.long 0x00 16.--19. "_1HR,1-Hour Time Digit of Alarm Setting (0~9)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 12.--14. "_10MIN,10-Min Time Digit of Alarm Setting (0~5)" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8.--11. "_1MIN,1-Min Time Digit of Alarm Setting (0~9)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 4.--6. "_10SEC,10-Sec Time Digit of Alarm Setting (0~5)" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--3. "_1SEC,1-Sec Time Digit of Alarm Setting (0~9)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "CAR,Calendar Alarm Register"
|
|
bitfld.long 0x00 20.--23. "_10YEAR,10-Year Calendar Digit of Alarm Setting (0~9)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. "_1YEAR,1-Year Calendar Digit of Alarm Setting (0~9)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 12. "_10MON,10-Month Calendar Digit of Alarm Setting (0~1)" "0,1"
|
|
bitfld.long 0x00 8.--11. "_1MON,1-Month Calendar Digit of Alarm Setting (0~9)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 4.--5. "_10DAY,10-Day Calendar Digit of Alarm Setting (0~3)" "0,1,2,3"
|
|
bitfld.long 0x00 0.--3. "_1DAY,1-Day Calendar Digit of Alarm Setting (0~9)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "LIR,Leap Year Indicator Register"
|
|
bitfld.long 0x00 0. "LIR,Leap Year Indication Register (Read Only)" "0: This year is not a leap year,1: This year is a leap year"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "RIER,RTC Interrupt Enable Register"
|
|
bitfld.long 0x00 1. "TIER,Time Tick Interrupt Enable Bit\nThis bit is used to enable/disable RTC Time Tick Interrupt and generate an interrupt signal if TIF (RIIR[1] RTC Time Tick Interrupt Flag) is set to 1.\nNote: This bit will also trigger a wake-up event while system.." "0: RTC Time Tick Interrupt Disabled,1: RTC Time Tick Interrupt Enabled"
|
|
bitfld.long 0x00 0. "AIER,Alarm Interrupt Enable Bit\nThis bit is used to enable/disable RTC Alarm Interrupt and generate an interrupt signal if AIF (RIIR[0] RTC Alarm Interrupt Flag) is set to 1.\nNote: This bit will also trigger a wake-up event while system runs in.." "0: RTC Alarm Interrupt Disabled,1: RTC Alarm Interrupt Enabled"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "RIIR,RTC Interrupt Indicator Register"
|
|
bitfld.long 0x00 1. "TIF,RTC Time Tick Interrupt Flag\nWhen RTC time tick happened this bit will be set to 1 and an interrupt will be generated if RTC Tick Interrupt enabled TIER (RIER[1]) is set to 1" "0: Tick condition does not occur,1: Tick condition occur"
|
|
bitfld.long 0x00 0. "AIF,RTC Alarm Interrupt Flag\nWhen RTC time counters TLR and CLR match the alarm setting time registers TAR and CAR this bit will be set to 1 and an interrupt will be generated if RTC Alarm Interrupt enabled AIER (RIER[0]) is set to 1" "0: Alarm condition is not matched,1: Alarm condition is matched"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "TTR,RTC Time Tick Register"
|
|
bitfld.long 0x00 0.--2. "TTR,Time Tick Register\nThese bits are used to select RTC time tick period for Periodic Time Tick Interrupt request" "0: Time tick is 1 second,1: Time tick is 1/2 second,2: Time tick is 1/4 second,3: Time tick is 1/8 second,4: Time tick is 1/16 second,5: Time tick is 1/32 second,6: Time tick is 1/64 second,7: Time tick is 1/28 second"
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "SPRCTL,RTC Spare Functional Control Register"
|
|
bitfld.long 0x00 7. "SPRRDY,SPR Register Ready\nThis bit indicates if the registers SPRCTL SPR0 ~ SPR19 are ready to be accessed.\nAfter user writing registers SPRCTL SPR0 ~ SPR19 read this bit to check if these registers are updated done is necessary.\nNote: This bit is.." "0: SPRCTL SPR0 ~ SPR19 updating is in progress,1: SPRCTL SPR0 ~ SPR19 are updated done and.."
|
|
bitfld.long 0x00 2. "SPREN,SPR Register Enable Bit\nNote: When spare register is disabled RTC SPR0 ~ SPR19 cannot be accessed" "0: Spare register is Disabled,1: Spare register is Enabled"
|
|
repeat 16. (strings "0" "1" "2" "3" "4" "5" "6" "7" "8" "9" "10" "11" "12" "13" "14" "15" )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
|
|
group.long ($2+0x40)++0x03
|
|
line.long 0x00 "SPR$1,RTC Spare Register $1"
|
|
repeat.end
|
|
repeat 4. (strings "16" "17" "18" "19" )(list 0x0 0x4 0x8 0xC )
|
|
group.long ($2+0x80)++0x03
|
|
line.long 0x00 "SPR$1,RTC Spare Register $1"
|
|
repeat.end
|
|
tree.end
|
|
tree "SPI"
|
|
repeat 2. (list 0. 1.) (list ad:0x40030000 ad:0x40034000)
|
|
tree "SPI$1"
|
|
base $2
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "SPI_CNTRL,Control and Status Register"
|
|
rbitfld.long 0x00 27. "TX_FULL,Transmit FIFO Buffer Full Indicator (Read Only)\nIt is a mutual mirror bit of SPI_STATUS[27]" "0: Transmit FIFO buffer is not full,1: Transmit FIFO buffer is full"
|
|
rbitfld.long 0x00 26. "TX_EMPTY,Transmit FIFO Buffer Empty Indicator (Read Only)\nIt is a mutual mirror bit of SPI_STATUS[26]" "0: Transmit FIFO buffer is not empty,1: Transmit FIFO buffer is empty"
|
|
newline
|
|
rbitfld.long 0x00 25. "RX_FULL,Receive FIFO Buffer Full Indicator (Read Only)\nIt is a mutual mirror bit of SPI_STATUS[25]" "0: Receive FIFO buffer is not full,1: Receive FIFO buffer is full"
|
|
rbitfld.long 0x00 24. "RX_EMPTY,Receive FIFO Buffer Empty Indicator (Read Only)\nIt is a mutual mirror bit of SPI_CNTRL[24]" "0: Receive FIFO buffer is not empty,1: Receive FIFO buffer is empty"
|
|
newline
|
|
bitfld.long 0x00 23. "VARCLK_EN,Variable Clock Enable Bit (Master Only)\nNote: When this VARCLK_EN bit is set to 1 the setting of TX_BIT_LEN must be programmed as 0x10 (16-bit mode)" "0: SPI clock output frequency is fixed and..,1: SPI clock output frequency is variable"
|
|
bitfld.long 0x00 21. "FIFO,FIFO Mode EnableBit\nNote1: Before enabling FIFO mode the other related settings should be set in advance.\nNote2: In Master mode if the FIFO mode is enabled the GO_BUSY bit will be set to 1 automatically after writing data to the transmit FIFO.." "0: FIFO mode Disabled,1: FIFO mode Enabled"
|
|
newline
|
|
bitfld.long 0x00 19. "REORDER,Byte Reorder Function EnableBit\nNote1: Byte Reorder function is only available if TX_BIT_LEN is defined as 16 24 and 32 bits.\nNote2: In Slave mode with level-trigger configuration the slave select pin must be kept at active state during the.." "0: Byte Reorder function Disabled,1: Byte Reorder function Enabled"
|
|
bitfld.long 0x00 18. "SLAVE,Slave Mode EnableBit" "0: Master mode,1: Slave mode"
|
|
newline
|
|
bitfld.long 0x00 17. "IE,Unit Transfer Interrupt EnableBit" "0: SPI unit transfer interrupt Disabled,1: SPI unit transfer interrupt Enabled"
|
|
bitfld.long 0x00 16. "IF,Unit Transfer Interrupt Flag\nNote: This bit will be cleared by writing 1 to itself" "0: No transaction has been finished since this..,1: SPI controller has finished one unit transfer"
|
|
newline
|
|
bitfld.long 0x00 12.--15. "SP_CYCLE,Suspend Interval (Master Only)\nThe four bits provide configurable suspend interval between two successive transmit/receive transaction in a transfer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 11. "CLKP,Clock Polarity" "0: SPI bus clock is idle low,1: SPI bus clock is idle high"
|
|
newline
|
|
bitfld.long 0x00 10. "LSB,Send LSB First" "0: The MSB which bit of transmit/receive..,1: The LSB bit 0 of the SPI TX0 register is sent.."
|
|
bitfld.long 0x00 3.--7. "TX_BIT_LEN,Transmit Bit Length\nThis field specifies how many bits can be transmitted / received in one transaction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 2. "TX_NEG,Transmit On Negative Edge" "0: Transmitted data output signal is changed on..,1: Transmitted data output signal is changed on.."
|
|
bitfld.long 0x00 1. "RX_NEG,Receive On Negative Edge" "0: Received data input signal is latched on the..,1: Received data input signal is latched on the.."
|
|
newline
|
|
bitfld.long 0x00 0. "GO_BUSY,SPI Transfer Control Bit And Busy Status\nIf FIFO mode is disabled during the data transfer this bit keeps the value of 1" "0: Data transfer stopped,1: In Master mode writing 1 to this bit to start.."
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI_DIVIDER,Clock Divider Register"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DIVIDER2,Clock Divider 2 Register (Master Only)\nThe value in this field is the 2nd frequency divider for generating the second clock of the variable clock function"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DIVIDER,Clock Divider 1 Register \nThe value in this field is the frequency divider for generating the SPI peripheral clock fspi_eclk and the SPI bus clock of SPI master"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "SPI_SSR,Slave Select Register"
|
|
bitfld.long 0x00 5. "LTRIG_FLAG,Level Trigger Accomplish Flag\nIn Slave mode this bit indicates whether the received bit number meets the requirement or not after the current transaction done" "0: Transferred bit length of one transaction..,1: Transferred bit length meets the specified.."
|
|
bitfld.long 0x00 4. "SS_LTRIG,Slave Select Level Trigger Enable Bit (Slave Only)" "0: Slave select signal is edge-trigger,1: Slave select signal is level-trigger"
|
|
newline
|
|
bitfld.long 0x00 3. "AUTOSS,Automatic Slave Select Function Enable Bit (Master Only)" "0: If this bit is cleared slave select signals..,1: If this bit is set SPIn_SPISS0 signals will.."
|
|
bitfld.long 0x00 2. "SS_LVL,Slave Select Active Level\nThis bit defines the active status of slave select signal (SPIn_SPISS0)" "0: The slave select signal SPIn_SPISS0 is active..,1: The slave select signal SPIn_SPISS0 is active.."
|
|
newline
|
|
bitfld.long 0x00 0. "SSR,Slave Select Control Bits (Master Only)\nIf AUTOSS bit is cleared writing 1 to any bit of this field sets the SPIn_SPISS0 line to an active state and writing 0 sets the line back to inactive state.\nIf the AUTOSS bit is set writing 0 to this field.." "0,1"
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "SPI_RX0,Data Receive Register 0"
|
|
hexmask.long 0x00 0.--31. 1. "RX,Data Receive Register\nThe data receive register holds the datum received from SPI data input pin"
|
|
wgroup.long 0x20++0x03
|
|
line.long 0x00 "SPI_TX0,Data Transmit Register 0"
|
|
abitfld.long 0x00 0.--31. "TX,Data Transmit Register\nThe data transmit registers hold the data to be transmitted in the next transfer" "0x00000001=1: When the SPI controller is..,0x00000002=2: In Master mode SPI controller will.."
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "SPI_VARCLK,Variable Clock Pattern Register"
|
|
hexmask.long 0x00 0.--31. 1. "VARCLK,Variable Clock Pattern\nThis register defines the clock pattern of the SPI transfer"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "SPI_DMA,SPI DMA Control Register"
|
|
bitfld.long 0x00 2. "PDMA_RST,PDMA Reset" "0: No effect,1: Reset the PDMA control logic of the SPI.."
|
|
bitfld.long 0x00 1. "RX_DMA_GO,Receive DMA Start\nSetting this bit to 1 will start the receive PDMA process" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "TX_DMA_GO,Transmit DMA Start\nSetting this bit to 1 will start the transmit PDMA process" "0,1"
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "SPI_CNTRL2,Control and Status Register 2"
|
|
bitfld.long 0x00 31. "BCn,SPI Peripheral Clock Backward Compatible Option\nRefer to the description of SPI_DIVIDER register for details" "0: Backward compatible clock configuration,1: Clock configuration is not backward compatible"
|
|
bitfld.long 0x00 16. "SS_INT_OPT,Slave Select Inactive Interrupt Option \nThis setting is only available if the SPI controller is configured as level trigger slave device" "0: As the slave select signal goes to inactive..,1: As the slave select signal goes to inactive.."
|
|
newline
|
|
bitfld.long 0x00 13. "DUAL_IO_EN,Dual I/O Mode EnableBit" "0: Dual I/O mode Disabled,1: Dual I/O mode Enabled"
|
|
bitfld.long 0x00 12. "DUAL_IO_DIR,Dual I/O Mode Direction Control" "0: Dual Input mode,1: Dual Output mode"
|
|
newline
|
|
bitfld.long 0x00 11. "SLV_START_INTSTS,Slave 3-Wire Mode Start Interrupt Status\nThis bit indicates if a transaction has started in Slave 3-wire mode" "0: Slave has not detected any SPI clock..,1: A transaction has started in Slave 3-wire mode"
|
|
bitfld.long 0x00 10. "SSTA_INTEN,Slave 3-Wire Mode Start Interrupt EnableBit\nUsed to enable interrupt when the transfer has started in Slave 3-wire mode" "0: Transaction start interrupt Disabled,1: Transaction start interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x00 9. "SLV_ABORT,Slave 3-Wire Mode Abort Control\nIn normal operation there is an interrupt event when the received data meet the required bits which defined in TX_BIT_LEN.\nIf the received bits are less than the requirement and there is no more SPI clock.." "0,1"
|
|
bitfld.long 0x00 8. "NOSLVSEL,Slave 3-Wire Mode Enable Bit\nThis is used to ignore the slave select signal in Slave mode" "0: 4-wire bi-direction interface,1: 3-wire bi-direction interface"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "SPI_FIFO_CTL,SPI FIFO Control Register"
|
|
bitfld.long 0x00 28.--30. "TX_THRESHOLD,Transmit FIFO Threshold\nIf the valid data count of the transmit FIFO buffer is less than or equal to the TX_THRESHOLD setting the TX_INTSTS bit will be set to 1 else the TX_INTSTS bit will be cleared to 0" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24.--26. "RX_THRESHOLD,Receive FIFO Threshold\nIf the valid data count of the receive FIFO buffer is larger than the RX_THRESHOLD setting the RX_INTSTS bit will be set to 1 else the RX_INTSTS bit will be cleared to 0" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 21. "TIMEOUT_INTEN,Receive FIFO Time-Out Interrupt Enable Bit" "0: Time-out interrupt Disabled,1: Time-out interrupt Enabled"
|
|
bitfld.long 0x00 6. "RXOV_INTEN,Receive FIFO Overrun Interrupt Enable Bit" "0: Receive FIFO overrun interrupt Disabled,1: Receive FIFO overrun interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x00 3. "TX_INTEN,Transmit Threshold Interrupt Enable Bit" "0: TX threshold interrupt Disabled,1: TX threshold interrupt Enabled"
|
|
bitfld.long 0x00 2. "RX_INTEN,Receive Threshold Interrupt Enable Bit" "0: RX threshold interrupt Disabled,1: RX threshold interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. "TX_CLR,Clear Transmit FIFO Buffer" "0: No effect,1: Clear transmit FIFO buffer"
|
|
bitfld.long 0x00 0. "RX_CLR,Clear Receive FIFO Buffer" "0: No effect,1: Clear receive FIFO buffer"
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "SPI_STATUS,SPI Status Register"
|
|
rbitfld.long 0x00 28.--31. "TX_FIFO_COUNT,Transmit FIFO Data Count (Read Only)\nThis bit field indicates the valid data count of transmit FIFO buffer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x00 27. "TX_FULL,Transmit FIFO Buffer Full Indicator (Read Only)\nIt is a mutual mirror bit of SPI_CNTRL[27]" "0: Transmit FIFO buffer is not full,1: Transmit FIFO buffer is full"
|
|
newline
|
|
rbitfld.long 0x00 26. "TX_EMPTY,Transmit FIFO Buffer Empty Indicator (Read Only)\nIt is a mutual mirror bit of SPI_CNTRL[26]" "0: Transmit FIFO buffer is not empty,1: Transmit FIFO buffer is empty"
|
|
rbitfld.long 0x00 25. "RX_FULL,Receive FIFO Buffer Empty Indicator (Read Only)\nIt is a mutual mirror bit of SPI_CNTRL[24]" "0: Receive FIFO buffer is not empty,1: Receive FIFO buffer is empty"
|
|
newline
|
|
rbitfld.long 0x00 24. "RX_EMPTY,Receive FIFO Buffer Empty Indicator (Read Only)\nIt is a mutual mirror bit of SPI_CNTRL[24]" "0: Receive FIFO buffer is not empty,1: Receive FIFO buffer is empty"
|
|
bitfld.long 0x00 20. "TIMEOUT,Time-Out Interrupt Flag\nNote: This bit will be cleared by writing 1 to itself" "0: No receive FIFO time-out event,1: Receive FIFO buffer is not empty and no read.."
|
|
newline
|
|
bitfld.long 0x00 16. "IF,SPI Unit Transfer Interrupt Flag\nIt is a mutual mirror bit of SPI_CNTRL[16].\nNote: This bit will be cleared by writing 1 to itself" "0: No transaction has been finished since this..,1: SPI controller has finished one unit transfer"
|
|
rbitfld.long 0x00 12.--15. "RX_FIFO_COUNT,Receive FIFO Data Count (Read Only)\nThis bit field indicates the valid data count of receive FIFO buffer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 11. "SLV_START_INTSTS,Slave Start Interrupt Status\nIt is used to dedicate if a transaction has started in Slave 3-wire mode" "0: Slave has not detected any SPI clock..,1: A transaction has started in Slave 3-wire mode"
|
|
rbitfld.long 0x00 4. "TX_INTSTS,Transmit FIFO Threshold Interrupt Status (Read Only)" "0: The valid data count within the transmit FIFO..,1: The valid data count within the transmit FIFO.."
|
|
newline
|
|
bitfld.long 0x00 2. "RX_OVERRUN,Receive FIFO Overrun Status\nWhen the receive FIFO buffer is full the follow-up data will be dropped and this bit will be set to 1.\nNote: This bit will be cleared by writing 1 to itself" "0,1"
|
|
rbitfld.long 0x00 0. "RX_INTSTS,Receive FIFO Threshold Interrupt Status (Read Only)" "0: The valid data count within the Rx FIFO..,1: The valid data count within the receive FIFO.."
|
|
tree.end
|
|
repeat.end
|
|
tree.end
|
|
tree "SYST_NVIC_SCS"
|
|
base ad:0xE000E000
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "SYST_CSR,SysTick Control and Status Register"
|
|
bitfld.long 0x00 16. "COUNTFLAG,Returns 1 If Timer Counted To 0 Since Last Time This Register Was Read\nCOUNTFLAG is set by a count transition from 1 to 0.\nCOUNTFLAG is cleared on read or by a write to the Current Value register" "0,1"
|
|
bitfld.long 0x00 2. "CLKSRC,System Tick Clock Source Selection" "0: Clock source is (optional) external reference..,1: Core clock used for SysTick"
|
|
newline
|
|
bitfld.long 0x00 1. "TICKINT,System Tick Interrupt Enabled" "0: Counting down to 0 does not cause the SysTick..,1: Counting down to 0 will cause the SysTick.."
|
|
bitfld.long 0x00 0. "ENABLE,System Tick Counter Enabled" "0: Counter Disabled,1: Counter will operate in a multi-shot manner"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "SYST_RVR,SysTick Reload Value Register"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. "RELOAD,Value to load into the Current Value register when the counter reaches 0"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "SYST_CVR,SysTick Current Value Register"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. "CURRENT,System Tick Current Value\nCurrent counter value"
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "NVIC_ISER,IRQ0 ~ IRQ31 Set-enable Control Register"
|
|
hexmask.long 0x00 0.--31. 1. "SETENA,Interrupt Enable Register\nEnable one or more interrupts"
|
|
group.long 0x180++0x03
|
|
line.long 0x00 "NVIC_ICER,IRQ0 ~ IRQ31 Clear-enable Control Register"
|
|
hexmask.long 0x00 0.--31. 1. "CLRENA,Interrupt Disable Bits\nDisable one or more interrupts"
|
|
group.long 0x200++0x03
|
|
line.long 0x00 "NVIC_ISPR,IRQ0 ~ IRQ31 Set-pending Control Register"
|
|
hexmask.long 0x00 0.--31. 1. "SETPEND,Set Interrupt Pending Register\nWrite Operation:\nRead value indicates the current pending status"
|
|
group.long 0x280++0x03
|
|
line.long 0x00 "NVIC_ICPR,IRQ0 ~ IRQ31 Clear-pending Control Register"
|
|
hexmask.long 0x00 0.--31. 1. "CLRPEND,Clear Interrupt Pending Register\nWrite Operation:\nRead value indicates the current pending status"
|
|
group.long 0x400++0x03
|
|
line.long 0x00 "NVIC_IPR0,IRQ0 ~ IRQ3 Priority Control Register"
|
|
bitfld.long 0x00 30.--31. "PRI_3,Priority Of IRQ3\n'0' denotes the highest priority and '3' denotes the lowest priority" "0,1,2,3"
|
|
bitfld.long 0x00 22.--23. "PRI_2,Priority Of IRQ2\n'0' denotes the highest priority and '3' denotes the lowest priority" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 14.--15. "PRI_1,Priority Of IRQ1\n'0' denotes the highest priority and '3' denotes the lowest priority" "0,1,2,3"
|
|
bitfld.long 0x00 6.--7. "PRI_0,Priority Of IRQ0\n'0' denotes the highest priority and '3' denotes the lowest priority" "0,1,2,3"
|
|
group.long 0x404++0x03
|
|
line.long 0x00 "NVIC_IPR1,IRQ4 ~ IRQ7 Priority Control Register"
|
|
bitfld.long 0x00 30.--31. "PRI_7,Priority Of IRQ7\n'0' denotes the highest priority and '3' denotes the lowest priority" "0,1,2,3"
|
|
bitfld.long 0x00 22.--23. "PRI_6,Priority Of IRQ6\n'0' denotes the highest priority and '3' denotes the lowest priority" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 14.--15. "PRI_5,Priority Of IRQ5\n'0' denotes the highest priority and '3' denotes the lowest priority" "0,1,2,3"
|
|
bitfld.long 0x00 6.--7. "PRI_4,Priority Of IRQ4\n'0' denotes the highest priority and '3' denotes the lowest priority" "0,1,2,3"
|
|
group.long 0x408++0x03
|
|
line.long 0x00 "NVIC_IPR2,IRQ8 ~ IRQ11 Priority Control Register"
|
|
bitfld.long 0x00 30.--31. "PRI_11,Priority Of IRQ11\n'0' denotes the highest priority and '3' denotes the lowest priority" "0,1,2,3"
|
|
bitfld.long 0x00 22.--23. "PRI_10,Priority Of IRQ10\n'0' denotes the highest priority and '3' denotes the lowest priority" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 14.--15. "PRI_9,Priority Of IRQ9\n'0' denotes the highest priority and '3' denotes the lowest priority" "0,1,2,3"
|
|
bitfld.long 0x00 6.--7. "PRI_8,Priority Of IRQ8\n'0' denotes the highest priority and '3' denotes the lowest priority" "0,1,2,3"
|
|
group.long 0x40C++0x03
|
|
line.long 0x00 "NVIC_IPR3,IRQ12 ~ IRQ15 Priority Control Register"
|
|
bitfld.long 0x00 30.--31. "PRI_15,Priority Of IRQ15\n'0' denotes the highest priority and '3' denotes the lowest priority" "0,1,2,3"
|
|
bitfld.long 0x00 22.--23. "PRI_14,Priority Of IRQ14\n'0' denotes the highest priority and '3' denotes the lowest priority" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 14.--15. "PRI_13,Priority Of IRQ13\n'0' denotes the highest priority and '3' denotes the lowest priority" "0,1,2,3"
|
|
bitfld.long 0x00 6.--7. "PRI_12,Priority Of IRQ12\n'0' denotes the highest priority and '3' denotes the lowest priority" "0,1,2,3"
|
|
group.long 0x410++0x03
|
|
line.long 0x00 "NVIC_IPR4,IRQ16 ~ IRQ19 Priority Control Register"
|
|
bitfld.long 0x00 30.--31. "PRI_19,Priority Of IRQ19\n'0' denotes the highest priority and '3' denotes the lowest priority" "0,1,2,3"
|
|
bitfld.long 0x00 22.--23. "PRI_18,Priority Of IRQ18\n'0' denotes the highest priority and '3' denotes the lowest priority" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 14.--15. "PRI_17,Priority Of IRQ17\n'0' denotes the highest priority and '3' denotes the lowest priority" "0,1,2,3"
|
|
bitfld.long 0x00 6.--7. "PRI_16,Priority Of IRQ16\n'0' denotes the highest priority and '3' denotes the lowest priority" "0,1,2,3"
|
|
group.long 0x414++0x03
|
|
line.long 0x00 "NVIC_IPR5,IRQ20 ~ IRQ23 Priority Control Register"
|
|
bitfld.long 0x00 30.--31. "PRI_23,Priority Of IRQ23\n'0' denotes the highest priority and '3' denotes the lowest priority" "0,1,2,3"
|
|
bitfld.long 0x00 22.--23. "PRI_22,Priority Of IRQ22\n'0' denotes the highest priority and '3' denotes the lowest priority" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 14.--15. "PRI_21,Priority Of IRQ21\n'0' denotes the highest priority and '3' denotes the lowest priority" "0,1,2,3"
|
|
bitfld.long 0x00 6.--7. "PRI_20,Priority Of IRQ20\n'0' denotes the highest priority and '3' denotes the lowest priority" "0,1,2,3"
|
|
group.long 0x418++0x03
|
|
line.long 0x00 "NVIC_IPR6,IRQ24 ~ IRQ27 Priority Control Register"
|
|
bitfld.long 0x00 30.--31. "PRI_27,Priority Of IRQ27\n'0' denotes the highest priority and '3' denotes the lowest priority" "0,1,2,3"
|
|
bitfld.long 0x00 22.--23. "PRI_26,Priority Of IRQ26\n'0' denotes the highest priority and '3' denotes the lowest priority" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 14.--15. "PRI_25,Priority Of IRQ25\n'0' denotes the highest priority and '3' denotes the lowest priority" "0,1,2,3"
|
|
bitfld.long 0x00 6.--7. "PRI_24,Priority Of IRQ24\n'0' denotes the highest priority and '3' denotes the lowest priority" "0,1,2,3"
|
|
group.long 0x41C++0x03
|
|
line.long 0x00 "NVIC_IPR7,IRQ28 ~ IRQ31 Priority Control Register"
|
|
bitfld.long 0x00 30.--31. "PRI_31,Priority Of IRQ31\n'0' denotes the highest priority and '3' denotes the lowest priority" "0,1,2,3"
|
|
bitfld.long 0x00 22.--23. "PRI_30,Priority Of IRQ30\n'0' denotes the highest priority and '3' denotes the lowest priority" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 14.--15. "PRI_29,Priority Of IRQ29\n'0' denotes the highest priority and '3' denotes the lowest priority" "0,1,2,3"
|
|
bitfld.long 0x00 6.--7. "PRI_28,Priority Of IRQ28\n'0' denotes the highest priority and '3' denotes the lowest priority" "0,1,2,3"
|
|
rgroup.long 0xD00++0x03
|
|
line.long 0x00 "CPUID,CPUID Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "IMPLEMENTER,Implementer Code Assigned By ARM"
|
|
bitfld.long 0x00 16.--19. "PART,Architecture Of The Processor\nRead as 0xC for ARMv6-M parts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.long.word 0x00 4.--15. 1. "PARTNO,Part Number Of The Processor\nRead as 0xC20"
|
|
bitfld.long 0x00 0.--3. "REVISION,Revision Number\nRead as 0x0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0xD04++0x03
|
|
line.long 0x00 "ICSR,Interrupt Control and State Register"
|
|
bitfld.long 0x00 31. "NMIPENDSET,NMI Set-Pending Bit\nWrite Operation:\nBecause NMI is the highest-priority exception normally the processor enters the NMI exception handler as soon as it detects a write of 1 to this bit" "0: No effect.\nNMI exception not pending,1: Changes NMI exception state to pending.\nNMI.."
|
|
bitfld.long 0x00 28. "PENDSVSET,PendSV Set-Pending Bit\nWrite Operation:\nNote: Writing 1 to this bit is the only way to set the PendSV exception state to pending" "0: No effect.\nPendSV exception is not pending,1: Changes PendSV exception state to.."
|
|
newline
|
|
bitfld.long 0x00 27. "PENDSVCLR,PendSV Clear-Pending Bit\nWrite Operation:\nThis is a write only bit" "0: No effect,1: Removes the pending state from the PendSV.."
|
|
bitfld.long 0x00 26. "PENDSTSET,SysTick Exception Set-Pending Bit\nWrite Operation" "0: No effect.\nSysTick exception is not pending,1: Changes SysTick exception state to.."
|
|
newline
|
|
bitfld.long 0x00 25. "PENDSTCLR,SysTick Exception Clear-Pending Bit\nWrite Operation:\nThis is a write only bit" "0: No effect,1: Removes the pending state from the SysTick.."
|
|
bitfld.long 0x00 23. "ISRPREEMPT,If Set A Pending Exception Will Be Serviced On Exit From The Debug Halt State\nThis bit is read only" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "ISRPENDING,Interrupt Pending Flag Excluding NMI And Faults:\nThis bit is read only" "0: Interrupt not pending,1: Interrupt pending"
|
|
bitfld.long 0x00 12.--17. "VECTPENDING,Indicates The Exception Number Of The Highest Priority Pending Enabled Exception" "0: No pending exceptions,?..."
|
|
newline
|
|
bitfld.long 0x00 0.--5. "VECTACTIVE,Contains The Active Exception Number" "0: Thread mode,?..."
|
|
group.long 0xD0C++0x03
|
|
line.long 0x00 "AIRCR,Application Interrupt and Reset Control Register"
|
|
hexmask.long.word 0x00 16.--31. 1. "VECTORKEY,Register Access Key\nWrite Operation:\nWhen writing to this register the VECTORKEY field need to be set to 0x05FA otherwise the write operation would be ignored"
|
|
bitfld.long 0x00 2. "SYSRESETREQ,System Reset Request\nWriting this bit 1 will cause a reset signal to be asserted to the chip to indicate a reset is requested.\nThe bit is a write only bit and self-clears as part of the reset sequence" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "VECTCLRACTIVE,Exception Active Status Clear Bit\nReserved for debug use" "0,1"
|
|
group.long 0xD10++0x03
|
|
line.long 0x00 "SCR,System Control Register"
|
|
bitfld.long 0x00 4. "SEVONPEND,Send Event On Pending Bit\nWhen an event or interrupt enters pending state the event signal wakes up the processor from WFE" "0: Only enabled interrupts or events can wake-up..,1: Enabled events and all interrupts including.."
|
|
bitfld.long 0x00 2. "SLEEPDEEP,Processor Deep Sleep And Sleep Mode Selection\nControls whether the processor uses sleep or deep sleep as its low power mode" "0: Sleep mode,1: Deep Sleep mode"
|
|
newline
|
|
bitfld.long 0x00 1. "SLEEPONEXIT,Sleep-On-Exit Enable Bit\nThis bit indicates sleep-on-exit when returning from Handler mode to Thread mode.\nSetting this bit to 1 enables an interrupt driven application to avoid returning to an empty main application" "0: Do not sleep when returning to Thread mode,1: Enter Sleep or Deep Sleep when returning from.."
|
|
group.long 0xD1C++0x03
|
|
line.long 0x00 "SHPR2,System Handler Priority Register 2"
|
|
bitfld.long 0x00 30.--31. "PRI_11,Priority Of System Handler" "0,1,2,3"
|
|
group.long 0xD20++0x03
|
|
line.long 0x00 "SHPR3,System Handler Priority Register 3"
|
|
bitfld.long 0x00 30.--31. "PRI_15,Priority Of System Handler" "0,1,2,3"
|
|
bitfld.long 0x00 22.--23. "PRI_14,Priority Of System Handler" "0,1,2,3"
|
|
tree.end
|
|
tree "TIMER"
|
|
tree "TMR01"
|
|
base ad:0x40010000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "TCSR0,Timer0 Control and Status Register"
|
|
bitfld.long 0x00 31. "DBGACK_TMR,ICE Debug Mode Acknowledge Disable Bit (Write Protect)\nTIMER counter will keep going no matter CPU is held by ICE or not" "0: ICE debug mode acknowledgement effects TIMER..,1: ICE debug mode acknowledgement Disabled"
|
|
bitfld.long 0x00 30. "CEN,Timer Enable Bit" "0: Stops/Suspends counting,1: Starts counting"
|
|
newline
|
|
bitfld.long 0x00 29. "IE,Interrupt Enable Bit\nIf this bit is enabled when the timer interrupt flag TIF (TISR[0]) is set to 1 the timer interrupt signal is generated and inform to CPU" "0: Timer Interrupt function Disabled,1: Timer Interrupt function Enabled"
|
|
bitfld.long 0x00 27.--28. "MODE,Timer Operating Mode" "0: The Timer controller is operated in One-shot..,1: The Timer controller is operated in Periodic..,2: The Timer controller is operated in..,3: The Timer controller is operated in.."
|
|
newline
|
|
bitfld.long 0x00 26. "CRST,Timer Reset" "0: No effect,1: Reset 8-bit prescale counter 24-bit up.."
|
|
rbitfld.long 0x00 25. "CACT,Timer Active Status (Read Only)\nThis bit indicates the 24-bit up counter status" "0: 24-bit up counter is not active,1: 24-bit up counter is active"
|
|
newline
|
|
bitfld.long 0x00 24. "CTB,Counter Mode Enable Bit \nThis bit is for external counting pin function enabled" "0: External counter mode Disabled,1: External counter mode Enabled"
|
|
bitfld.long 0x00 23. "WAKE_EN,Wake Up Function Enable Bit" "0: Wake-up trigger event Disabled,1: Wake-up trigger event Enabled"
|
|
newline
|
|
bitfld.long 0x00 16. "TDR_EN,Data Load Enable Bit\nWhen TDR_EN is set TDR (Timer Data Register) will be updated continuously with the 24-bit up-timer value as the timer is counting" "0: Timer Data Register update Disabled,1: Timer Data Register update Enabled while.."
|
|
hexmask.long.byte 0x00 0.--7. 1. "PRESCALE,Prescale Counter"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "TCMPR0,Timer0 Compare Register"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. "TCMP,Timer Compared Value\nTCMP is a 24-bit compared value register"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "TISR0,Timer0 Interrupt Status Register"
|
|
bitfld.long 0x00 1. "TWF,Timer Wake-Up Flag\nThis bit indicates the interrupt wake-up flag status of Timer.\nNote: This bit is cleared by writing 1 to it" "0: Timer does not cause CPU wake-up,1: CPU wake-up from Idle or Power-down mode if.."
|
|
bitfld.long 0x00 0. "TIF,Timer Interrupt Flag\nThis bit indicates the interrupt flag status of Timer while TDR value reaches to TCMP value.\nNote: This bit is cleared by writing 1 to it" "0: No effect,1: TDR value matches the TCMP value"
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "TDR0,Timer0 Data Register"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. "TDR,Timer Data Register\nIf TDR_EN (TCSR[16]) is set to 1 TDR register will be updated continuously to monitor 24-bit up counter value"
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "TCAP0,Timer0 Capture Data Register"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. "TCAP,Timer Capture Data Register\nWhen TEXIF (TEXISR[0]) flag and RSTCAPSEL (TEXCON[4]) is set to 1 the current TDR value will be auto-loaded into this TCAP filed immediately"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "TEXCON0,Timer0 External Control Register"
|
|
bitfld.long 0x00 7. "TCDB,Timer External Counter Input Pin De-Bounce Enable Bit\nIf this bit is enabled the edge detection of TMx pin is detected with de-bounce circuit" "0: TMx pin de-bounce Disabled,1: TMx pin de-bounce Enabled"
|
|
bitfld.long 0x00 6. "TEXDB,Timer External Capture Input Pin De-Bounce Enable Bit\nIf this bit is enabled the edge detection of TMx_EXT pin is detected with de-bounce circuit" "0: TMx_EXT pin de-bounce Disabled,1: TMx_EXT pin de-bounce Enabled"
|
|
newline
|
|
bitfld.long 0x00 5. "TEXIEN,Timer External Capture Interrupt Enable Bit\nIf TEXIEN enabled Timer will raise an external capture interrupt signal and inform to CPU while TEXIF flag is set to 1" "0: TMx_EXT pin detection Interrupt Disabled,1: TMx_EXT pin detection Interrupt Enabled"
|
|
bitfld.long 0x00 4. "RSTCAPSEL,Timer External Reset Counter / Timer External Capture Mode Selection" "0: Transition on TMx_EXT pin is using to save..,1: Transition on TMx_EXT pin is using to reset.."
|
|
newline
|
|
bitfld.long 0x00 3. "TEXEN,Timer External Pin Function Enable Bit\nThis bit enables the RSTCAPSEL function on the TMx_EXT pin" "0: RSTCAPSEL function of TMx_EXT pin will be..,1: RSTCAPSEL function of TMx_EXT pin is active"
|
|
bitfld.long 0x00 1.--2. "TEX_EDGE,Timer External Capture Pin Edge Detect Selection" "0: A 1 to 0 transition on TMx_EXT pin will be..,1: A 0 to 1 transition on TMx_EXT pin will be..,2: Either 1 to 0 or 0 to 1 transition on TMx_EXT..,3: Reserved"
|
|
newline
|
|
bitfld.long 0x00 0. "TX_PHASE,Timer External Count Pin Phase Detect Selection\nThis bit indicates the detection phase of TMx_EXT pin" "0: A falling edge of TMx_EXT pin will be counted,1: A rising edge of TMx_EXT pin will be counted"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "TEXISR0,Timer0 External Interrupt Status Register"
|
|
bitfld.long 0x00 0. "TEXIF,Timer External Capture Interrupt Flag\nThis bit indicates the external capture interrupt flag status.\nWhen TEXEN (TEXCON[3]) enabled TMx_EXT pin selected as external capture function and a transition on TMx_EXT pin matched the TEX_EDGE.." "0: TMx_EXT pin interrupt did not occur,1: TMx_EXT pin interrupt occurred"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "TCSR1,Timer1 Control and Status Register"
|
|
bitfld.long 0x00 31. "DBGACK_TMR,ICE Debug Mode Acknowledge Disable Bit (Write Protect)\nTIMER counter will keep going no matter CPU is held by ICE or not" "0: ICE debug mode acknowledgement effects TIMER..,1: ICE debug mode acknowledgement Disabled"
|
|
bitfld.long 0x00 30. "CEN,Timer Enable Bit" "0: Stops/Suspends counting,1: Starts counting"
|
|
newline
|
|
bitfld.long 0x00 29. "IE,Interrupt Enable Bit\nIf this bit is enabled when the timer interrupt flag TIF (TISR[0]) is set to 1 the timer interrupt signal is generated and inform to CPU" "0: Timer Interrupt function Disabled,1: Timer Interrupt function Enabled"
|
|
bitfld.long 0x00 27.--28. "MODE,Timer Operating Mode" "0: The Timer controller is operated in One-shot..,1: The Timer controller is operated in Periodic..,2: The Timer controller is operated in..,3: The Timer controller is operated in.."
|
|
newline
|
|
bitfld.long 0x00 26. "CRST,Timer Reset" "0: No effect,1: Reset 8-bit prescale counter 24-bit up.."
|
|
rbitfld.long 0x00 25. "CACT,Timer Active Status (Read Only)\nThis bit indicates the 24-bit up counter status" "0: 24-bit up counter is not active,1: 24-bit up counter is active"
|
|
newline
|
|
bitfld.long 0x00 24. "CTB,Counter Mode Enable Bit \nThis bit is for external counting pin function enabled" "0: External counter mode Disabled,1: External counter mode Enabled"
|
|
bitfld.long 0x00 23. "WAKE_EN,Wake Up Function Enable Bit" "0: Wake-up trigger event Disabled,1: Wake-up trigger event Enabled"
|
|
newline
|
|
bitfld.long 0x00 16. "TDR_EN,Data Load Enable Bit\nWhen TDR_EN is set TDR (Timer Data Register) will be updated continuously with the 24-bit up-timer value as the timer is counting" "0: Timer Data Register update Disabled,1: Timer Data Register update Enabled while.."
|
|
hexmask.long.byte 0x00 0.--7. 1. "PRESCALE,Prescale Counter"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "TCMPR1,Timer1 Compare Register"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. "TCMP,Timer Compared Value\nTCMP is a 24-bit compared value register"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "TISR1,Timer1 Interrupt Status Register"
|
|
bitfld.long 0x00 1. "TWF,Timer Wake-Up Flag\nThis bit indicates the interrupt wake-up flag status of Timer.\nNote: This bit is cleared by writing 1 to it" "0: Timer does not cause CPU wake-up,1: CPU wake-up from Idle or Power-down mode if.."
|
|
bitfld.long 0x00 0. "TIF,Timer Interrupt Flag\nThis bit indicates the interrupt flag status of Timer while TDR value reaches to TCMP value.\nNote: This bit is cleared by writing 1 to it" "0: No effect,1: TDR value matches the TCMP value"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "TDR1,Timer1 Data Register"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. "TDR,Timer Data Register\nIf TDR_EN (TCSR[16]) is set to 1 TDR register will be updated continuously to monitor 24-bit up counter value"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "TCAP1,Timer1 Capture Data Register"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. "TCAP,Timer Capture Data Register\nWhen TEXIF (TEXISR[0]) flag and RSTCAPSEL (TEXCON[4]) is set to 1 the current TDR value will be auto-loaded into this TCAP filed immediately"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "TEXCON1,Timer1 External Control Register"
|
|
bitfld.long 0x00 7. "TCDB,Timer External Counter Input Pin De-Bounce Enable Bit\nIf this bit is enabled the edge detection of TMx pin is detected with de-bounce circuit" "0: TMx pin de-bounce Disabled,1: TMx pin de-bounce Enabled"
|
|
bitfld.long 0x00 6. "TEXDB,Timer External Capture Input Pin De-Bounce Enable Bit\nIf this bit is enabled the edge detection of TMx_EXT pin is detected with de-bounce circuit" "0: TMx_EXT pin de-bounce Disabled,1: TMx_EXT pin de-bounce Enabled"
|
|
newline
|
|
bitfld.long 0x00 5. "TEXIEN,Timer External Capture Interrupt Enable Bit\nIf TEXIEN enabled Timer will raise an external capture interrupt signal and inform to CPU while TEXIF flag is set to 1" "0: TMx_EXT pin detection Interrupt Disabled,1: TMx_EXT pin detection Interrupt Enabled"
|
|
bitfld.long 0x00 4. "RSTCAPSEL,Timer External Reset Counter / Timer External Capture Mode Selection" "0: Transition on TMx_EXT pin is using to save..,1: Transition on TMx_EXT pin is using to reset.."
|
|
newline
|
|
bitfld.long 0x00 3. "TEXEN,Timer External Pin Function Enable Bit\nThis bit enables the RSTCAPSEL function on the TMx_EXT pin" "0: RSTCAPSEL function of TMx_EXT pin will be..,1: RSTCAPSEL function of TMx_EXT pin is active"
|
|
bitfld.long 0x00 1.--2. "TEX_EDGE,Timer External Capture Pin Edge Detect Selection" "0: A 1 to 0 transition on TMx_EXT pin will be..,1: A 0 to 1 transition on TMx_EXT pin will be..,2: Either 1 to 0 or 0 to 1 transition on TMx_EXT..,3: Reserved"
|
|
newline
|
|
bitfld.long 0x00 0. "TX_PHASE,Timer External Count Pin Phase Detect Selection\nThis bit indicates the detection phase of TMx_EXT pin" "0: A falling edge of TMx_EXT pin will be counted,1: A rising edge of TMx_EXT pin will be counted"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "TEXISR1,Timer1 External Interrupt Status Register"
|
|
bitfld.long 0x00 0. "TEXIF,Timer External Capture Interrupt Flag\nThis bit indicates the external capture interrupt flag status.\nWhen TEXEN (TEXCON[3]) enabled TMx_EXT pin selected as external capture function and a transition on TMx_EXT pin matched the TEX_EDGE.." "0: TMx_EXT pin interrupt did not occur,1: TMx_EXT pin interrupt occurred"
|
|
tree.end
|
|
tree "TMR23"
|
|
base ad:0x40110000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "TCSR2,Timer2 Control and Status Register"
|
|
bitfld.long 0x00 31. "DBGACK_TMR,ICE Debug Mode Acknowledge Disable Bit (Write Protect)\nTIMER counter will keep going no matter CPU is held by ICE or not" "0: ICE debug mode acknowledgement effects TIMER..,1: ICE debug mode acknowledgement Disabled"
|
|
bitfld.long 0x00 30. "CEN,Timer Enable Bit" "0: Stops/Suspends counting,1: Starts counting"
|
|
newline
|
|
bitfld.long 0x00 29. "IE,Interrupt Enable Bit\nIf this bit is enabled when the timer interrupt flag TIF (TISR[0]) is set to 1 the timer interrupt signal is generated and inform to CPU" "0: Timer Interrupt function Disabled,1: Timer Interrupt function Enabled"
|
|
bitfld.long 0x00 27.--28. "MODE,Timer Operating Mode" "0: The Timer controller is operated in One-shot..,1: The Timer controller is operated in Periodic..,2: The Timer controller is operated in..,3: The Timer controller is operated in.."
|
|
newline
|
|
bitfld.long 0x00 26. "CRST,Timer Reset" "0: No effect,1: Reset 8-bit prescale counter 24-bit up.."
|
|
rbitfld.long 0x00 25. "CACT,Timer Active Status (Read Only)\nThis bit indicates the 24-bit up counter status" "0: 24-bit up counter is not active,1: 24-bit up counter is active"
|
|
newline
|
|
bitfld.long 0x00 24. "CTB,Counter Mode Enable Bit \nThis bit is for external counting pin function enabled" "0: External counter mode Disabled,1: External counter mode Enabled"
|
|
bitfld.long 0x00 23. "WAKE_EN,Wake Up Function Enable Bit" "0: Wake-up trigger event Disabled,1: Wake-up trigger event Enabled"
|
|
newline
|
|
bitfld.long 0x00 16. "TDR_EN,Data Load Enable Bit\nWhen TDR_EN is set TDR (Timer Data Register) will be updated continuously with the 24-bit up-timer value as the timer is counting" "0: Timer Data Register update Disabled,1: Timer Data Register update Enabled while.."
|
|
hexmask.long.byte 0x00 0.--7. 1. "PRESCALE,Prescale Counter"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "TCMPR2,Timer2 Compare Register"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. "TCMP,Timer Compared Value\nTCMP is a 24-bit compared value register"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "TISR2,Timer2 Interrupt Status Register"
|
|
bitfld.long 0x00 1. "TWF,Timer Wake-Up Flag\nThis bit indicates the interrupt wake-up flag status of Timer.\nNote: This bit is cleared by writing 1 to it" "0: Timer does not cause CPU wake-up,1: CPU wake-up from Idle or Power-down mode if.."
|
|
bitfld.long 0x00 0. "TIF,Timer Interrupt Flag\nThis bit indicates the interrupt flag status of Timer while TDR value reaches to TCMP value.\nNote: This bit is cleared by writing 1 to it" "0: No effect,1: TDR value matches the TCMP value"
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "TDR2,Timer2 Data Register"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. "TDR,Timer Data Register\nIf TDR_EN (TCSR[16]) is set to 1 TDR register will be updated continuously to monitor 24-bit up counter value"
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "TCAP2,Timer2 Capture Data Register"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. "TCAP,Timer Capture Data Register\nWhen TEXIF (TEXISR[0]) flag and RSTCAPSEL (TEXCON[4]) is set to 1 the current TDR value will be auto-loaded into this TCAP filed immediately"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "TEXCON2,Timer2 External Control Register"
|
|
bitfld.long 0x00 7. "TCDB,Timer External Counter Input Pin De-Bounce Enable Bit\nIf this bit is enabled the edge detection of TMx pin is detected with de-bounce circuit" "0: TMx pin de-bounce Disabled,1: TMx pin de-bounce Enabled"
|
|
bitfld.long 0x00 6. "TEXDB,Timer External Capture Input Pin De-Bounce Enable Bit\nIf this bit is enabled the edge detection of TMx_EXT pin is detected with de-bounce circuit" "0: TMx_EXT pin de-bounce Disabled,1: TMx_EXT pin de-bounce Enabled"
|
|
newline
|
|
bitfld.long 0x00 5. "TEXIEN,Timer External Capture Interrupt Enable Bit\nIf TEXIEN enabled Timer will raise an external capture interrupt signal and inform to CPU while TEXIF flag is set to 1" "0: TMx_EXT pin detection Interrupt Disabled,1: TMx_EXT pin detection Interrupt Enabled"
|
|
bitfld.long 0x00 4. "RSTCAPSEL,Timer External Reset Counter / Timer External Capture Mode Selection" "0: Transition on TMx_EXT pin is using to save..,1: Transition on TMx_EXT pin is using to reset.."
|
|
newline
|
|
bitfld.long 0x00 3. "TEXEN,Timer External Pin Function Enable Bit\nThis bit enables the RSTCAPSEL function on the TMx_EXT pin" "0: RSTCAPSEL function of TMx_EXT pin will be..,1: RSTCAPSEL function of TMx_EXT pin is active"
|
|
bitfld.long 0x00 1.--2. "TEX_EDGE,Timer External Capture Pin Edge Detect Selection" "0: A 1 to 0 transition on TMx_EXT pin will be..,1: A 0 to 1 transition on TMx_EXT pin will be..,2: Either 1 to 0 or 0 to 1 transition on TMx_EXT..,3: Reserved"
|
|
newline
|
|
bitfld.long 0x00 0. "TX_PHASE,Timer External Count Pin Phase Detect Selection\nThis bit indicates the detection phase of TMx_EXT pin" "0: A falling edge of TMx_EXT pin will be counted,1: A rising edge of TMx_EXT pin will be counted"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "TEXISR2,Timer2 External Interrupt Status Register"
|
|
bitfld.long 0x00 0. "TEXIF,Timer External Capture Interrupt Flag\nThis bit indicates the external capture interrupt flag status.\nWhen TEXEN (TEXCON[3]) enabled TMx_EXT pin selected as external capture function and a transition on TMx_EXT pin matched the TEX_EDGE.." "0: TMx_EXT pin interrupt did not occur,1: TMx_EXT pin interrupt occurred"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "TCSR3,Timer3 Control and Status Register"
|
|
bitfld.long 0x00 31. "DBGACK_TMR,ICE Debug Mode Acknowledge Disable Bit (Write Protect)\nTIMER counter will keep going no matter CPU is held by ICE or not" "0: ICE debug mode acknowledgement effects TIMER..,1: ICE debug mode acknowledgement Disabled"
|
|
bitfld.long 0x00 30. "CEN,Timer Enable Bit" "0: Stops/Suspends counting,1: Starts counting"
|
|
newline
|
|
bitfld.long 0x00 29. "IE,Interrupt Enable Bit\nIf this bit is enabled when the timer interrupt flag TIF (TISR[0]) is set to 1 the timer interrupt signal is generated and inform to CPU" "0: Timer Interrupt function Disabled,1: Timer Interrupt function Enabled"
|
|
bitfld.long 0x00 27.--28. "MODE,Timer Operating Mode" "0: The Timer controller is operated in One-shot..,1: The Timer controller is operated in Periodic..,2: The Timer controller is operated in..,3: The Timer controller is operated in.."
|
|
newline
|
|
bitfld.long 0x00 26. "CRST,Timer Reset" "0: No effect,1: Reset 8-bit prescale counter 24-bit up.."
|
|
rbitfld.long 0x00 25. "CACT,Timer Active Status (Read Only)\nThis bit indicates the 24-bit up counter status" "0: 24-bit up counter is not active,1: 24-bit up counter is active"
|
|
newline
|
|
bitfld.long 0x00 24. "CTB,Counter Mode Enable Bit \nThis bit is for external counting pin function enabled" "0: External counter mode Disabled,1: External counter mode Enabled"
|
|
bitfld.long 0x00 23. "WAKE_EN,Wake Up Function Enable Bit" "0: Wake-up trigger event Disabled,1: Wake-up trigger event Enabled"
|
|
newline
|
|
bitfld.long 0x00 16. "TDR_EN,Data Load Enable Bit\nWhen TDR_EN is set TDR (Timer Data Register) will be updated continuously with the 24-bit up-timer value as the timer is counting" "0: Timer Data Register update Disabled,1: Timer Data Register update Enabled while.."
|
|
hexmask.long.byte 0x00 0.--7. 1. "PRESCALE,Prescale Counter"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "TCMPR3,Timer3 Compare Register"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. "TCMP,Timer Compared Value\nTCMP is a 24-bit compared value register"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "TISR3,Timer3 Interrupt Status Register"
|
|
bitfld.long 0x00 1. "TWF,Timer Wake-Up Flag\nThis bit indicates the interrupt wake-up flag status of Timer.\nNote: This bit is cleared by writing 1 to it" "0: Timer does not cause CPU wake-up,1: CPU wake-up from Idle or Power-down mode if.."
|
|
bitfld.long 0x00 0. "TIF,Timer Interrupt Flag\nThis bit indicates the interrupt flag status of Timer while TDR value reaches to TCMP value.\nNote: This bit is cleared by writing 1 to it" "0: No effect,1: TDR value matches the TCMP value"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "TDR3,Timer3 Data Register"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. "TDR,Timer Data Register\nIf TDR_EN (TCSR[16]) is set to 1 TDR register will be updated continuously to monitor 24-bit up counter value"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "TCAP3,Timer3 Capture Data Register"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. "TCAP,Timer Capture Data Register\nWhen TEXIF (TEXISR[0]) flag and RSTCAPSEL (TEXCON[4]) is set to 1 the current TDR value will be auto-loaded into this TCAP filed immediately"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "TEXCON3,Timer3 External Control Register"
|
|
bitfld.long 0x00 7. "TCDB,Timer External Counter Input Pin De-Bounce Enable Bit\nIf this bit is enabled the edge detection of TMx pin is detected with de-bounce circuit" "0: TMx pin de-bounce Disabled,1: TMx pin de-bounce Enabled"
|
|
bitfld.long 0x00 6. "TEXDB,Timer External Capture Input Pin De-Bounce Enable Bit\nIf this bit is enabled the edge detection of TMx_EXT pin is detected with de-bounce circuit" "0: TMx_EXT pin de-bounce Disabled,1: TMx_EXT pin de-bounce Enabled"
|
|
newline
|
|
bitfld.long 0x00 5. "TEXIEN,Timer External Capture Interrupt Enable Bit\nIf TEXIEN enabled Timer will raise an external capture interrupt signal and inform to CPU while TEXIF flag is set to 1" "0: TMx_EXT pin detection Interrupt Disabled,1: TMx_EXT pin detection Interrupt Enabled"
|
|
bitfld.long 0x00 4. "RSTCAPSEL,Timer External Reset Counter / Timer External Capture Mode Selection" "0: Transition on TMx_EXT pin is using to save..,1: Transition on TMx_EXT pin is using to reset.."
|
|
newline
|
|
bitfld.long 0x00 3. "TEXEN,Timer External Pin Function Enable Bit\nThis bit enables the RSTCAPSEL function on the TMx_EXT pin" "0: RSTCAPSEL function of TMx_EXT pin will be..,1: RSTCAPSEL function of TMx_EXT pin is active"
|
|
bitfld.long 0x00 1.--2. "TEX_EDGE,Timer External Capture Pin Edge Detect Selection" "0: A 1 to 0 transition on TMx_EXT pin will be..,1: A 0 to 1 transition on TMx_EXT pin will be..,2: Either 1 to 0 or 0 to 1 transition on TMx_EXT..,3: Reserved"
|
|
newline
|
|
bitfld.long 0x00 0. "TX_PHASE,Timer External Count Pin Phase Detect Selection\nThis bit indicates the detection phase of TMx_EXT pin" "0: A falling edge of TMx_EXT pin will be counted,1: A rising edge of TMx_EXT pin will be counted"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "TEXISR3,Timer3 External Interrupt Status Register"
|
|
bitfld.long 0x00 0. "TEXIF,Timer External Capture Interrupt Flag\nThis bit indicates the external capture interrupt flag status.\nWhen TEXEN (TEXCON[3]) enabled TMx_EXT pin selected as external capture function and a transition on TMx_EXT pin matched the TEX_EDGE.." "0: TMx_EXT pin interrupt did not occur,1: TMx_EXT pin interrupt occurred"
|
|
tree.end
|
|
tree.end
|
|
tree "UART"
|
|
tree "UART0"
|
|
base ad:0x40050000
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "UA_RBR,UART Receive Buffer Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. "RBR,Receive Buffer Register (Read Only)\nBy reading this register the UART will return the 8-bit data received from RX pin (LSB first)"
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "UA_THR,UART Transmit Holding Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. "THR,Transmit Holding Register\nBy writing one byte to this register the data byte will be stored in transmitter FIFO"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "UA_IER,UART Interrupt Enable Register"
|
|
bitfld.long 0x00 15. "DMA_RX_EN,RX DMA Enable Bit (Not Available In UART2 Channel)\nThis bit can enable or disable RX DMA service" "0: RX DMA Disabled,1: RX DMA Enabled"
|
|
bitfld.long 0x00 14. "DMA_TX_EN,TX DMA Enable Bit (Not Available In UART2 Channel)\nThis bit can enable or disable TX DMA service" "0: TX DMA Disabled,1: TX DMA Enabled"
|
|
newline
|
|
bitfld.long 0x00 13. "AUTO_CTS_EN,CTS Auto Flow Control Enable Bit (Not Available In UART2 Channel)\nWhen CTS auto-flow is enabled the UART will send data to external device when CTS input assert (UART will not send data to device until CTS is asserted)" "0: CTS auto flow control Disabled,1: CTS auto flow control Enabled"
|
|
bitfld.long 0x00 12. "AUTO_RTS_EN,RTS Auto Flow Control Enable Bit (Not Available In UART2 Channel)\nWhen RTS auto-flow is enabled if the number of bytes in the RX FIFO equals the RTS_TRI_LEV (UA_FCR [19:16]) the UART will de-assert RTS signal" "0: RTS auto flow control Disabled,1: RTS auto flow control Enabled"
|
|
newline
|
|
bitfld.long 0x00 11. "TIME_OUT_EN,Time-Out Counter Enable Bit" "0: Time-out counter Disabled,1: Time-out counter Enabled"
|
|
bitfld.long 0x00 8. "LIN_IEN,LIN Bus Interrupt Enable Bit\nNote: This field is used for LIN function mode" "0: Lin bus interrupt Disabled,1: Lin bus interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x00 6. "WAKE_EN,UART Wake-Up Function Enable Bit (Not Available In UART2 Channel)" "0: UART wake-up function Disabled,1: UART wake-up function Enabled when the chip.."
|
|
bitfld.long 0x00 5. "BUF_ERR_IEN,Buffer Error Interrupt Enable Bit" "0: BUF_ERR_INT Masked off,1: BUF_ERR_INT Enabled"
|
|
newline
|
|
bitfld.long 0x00 4. "TOUT_IEN,RX Time-Out Interrupt Enable Bit" "0: TOUT_INT Masked off,1: TOUT_INT Enabled"
|
|
bitfld.long 0x00 3. "MODEM_IEN,Modem Status Interrupt Enable Bit (Not Available In UART2 Channel)" "0: MODEM_INT Masked off,1: MODEM_INT Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. "RLS_IEN,Receive Line Status Interrupt Enable Bit" "0: RLS_INT Masked off,1: RLS_INT Enabled"
|
|
bitfld.long 0x00 1. "THRE_IEN,Transmit Holding Register Empty Interrupt Enable Bit" "0: THRE_INT Masked off,1: THRE_INT Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. "RDA_IEN,Receive Data Available Interrupt Enable Bit" "0: RDA_INT Masked off,1: RDA_INT Enabled"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "UA_FCR,UART FIFO Control Register"
|
|
bitfld.long 0x00 16.--19. "RTS_TRI_LEV,RTS Trigger Level For Auto-Flow Control Use (Not Available In UART2 Channel)\nNote: This field is used for RTS auto-flow control" "0: RTS Trigger Level is 1 byte,1: RTS Trigger Level is 4 bytes,2: RTS Trigger Level is 8 bytes,3: RTS Trigger Level is 14 bytes,4: RTS Trigger Level is 30/14 bytes (High..,5: RTS Trigger Level is 46/14 bytes (High..,6: RTS Trigger Level is 62/14 bytes (High..,?..."
|
|
bitfld.long 0x00 8. "RX_DIS,Receiver Disable Bit\nThe receiver is disabled or not (set 1 to disable receiver)\nNote: This field is used for RS-485 Normal Multi-drop mode" "0: Receiver Enabled,1: Receiver Disabled"
|
|
newline
|
|
bitfld.long 0x00 4.--7. "RFITL,RX FIFO Interrupt (INT_RDA) Trigger Level\nWhen the number of bytes in the receive FIFO equals the RFITL the RDA_IF will be set (if UA_IER [RDA_IEN] enabled and an interrupt will be generated)" "0: RX FIFO Interrupt Trigger Level is 1 byte,1: RX FIFO Interrupt Trigger Level is 4 bytes,2: RX FIFO Interrupt Trigger Level is 8 bytes,3: RX FIFO Interrupt Trigger Level is 14 bytes,4: RX FIFO Interrupt Trigger Level is 30/14..,5: RX FIFO Interrupt Trigger Level is 46/14..,6: RX FIFO Interrupt Trigger Level is 62/14..,?..."
|
|
bitfld.long 0x00 2. "TFR,TX Field Software Reset\nWhen TFR is set all the byte in the transmit FIFO and TX internal state machine are cleared.\nNote: This bit will automatically clear at least 3 UART peripherial clock cycles" "0: No effect,1: Reset the TX internal state machine and.."
|
|
newline
|
|
bitfld.long 0x00 1. "RFR,RX Field Software Reset\nWhen RFR is set all the byte in the receiver FIFO and RX internal state machine are cleared.\nNote: This bit will automatically clear at least 3 UART peripherial clock cycles" "0: No effect,1: Reset the RX internal state machine and.."
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "UA_LCR,UART Line Control Register"
|
|
bitfld.long 0x00 6. "BCB,Break Control Bit\nWhen this bit is set to logic 1 the serial data output (TX) is forced to the Spacing State (logic 0)" "0,1"
|
|
bitfld.long 0x00 5. "SPE,Stick Parity Enable Bit" "0: Stick parity Disabled,1: If PBE (UA_LCR[3]) and EBE (UA_LCR[4]) are.."
|
|
newline
|
|
bitfld.long 0x00 4. "EPE,Even Parity Enable Bit\nThis bit has effect only when PBE (UA_LCR[3]) is set" "0: Odd number of logic 1's is transmitted and..,1: Even number of logic 1's is transmitted and.."
|
|
bitfld.long 0x00 3. "PBE,Parity Bit Enable Bit" "0: No parity bit,1: Parity bit is generated on each outgoing.."
|
|
newline
|
|
bitfld.long 0x00 2. "NSB,Number Of 'STOP Bit'" "0: One ' STOP bit' is generated in the..,1: When select 5-bit word length 1.5 'STOP bit'.."
|
|
bitfld.long 0x00 0.--1. "WLS,Word Length Selection" "0: Word length is 5-bit,1: Word length is 6-bit,2: Word length is 7-bit,3: Word length is 8-bit"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "UA_MCR,UART Modem Control Register"
|
|
rbitfld.long 0x00 13. "RTS_ST,RTS Pin State (Read Only) (Not Available In UART2 Channel)\nThis bit mirror from RTS pin output of voltage logic status" "0: RTS pin output is low level voltage logic state,1: RTS pin output is high level voltage logic.."
|
|
bitfld.long 0x00 9. "LEV_RTS,RTS Pin Active Level (Not Available In UART2 Channel)\nThis bit defines the active level state of RTS pin output.\nNote1: Refer to Figure 6.136 and Figure 6.137 for UART function mode.\nNote2: Refer to Figure 6.1317 And Figure 6.1318 for RS-485.." "0: RTS pin output is high level active,1: RTS pin output is low level active"
|
|
newline
|
|
bitfld.long 0x00 1. "RTS,RTS (Request-To-Send) Signal Control (Not Available In UART2 Channel)\nThis bit is direct control internal RTS signal active or not and then drive the RTS pin output with LEV_RTS bit configuration.\nNote1: This RTS signal control bit is not.." "0: RTS signal is active,1: RTS signal is inactive"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "UA_MSR,UART Modem Status Register"
|
|
bitfld.long 0x00 8. "LEV_CTS,CTS Pin Active Level\nThis bit defines the active level state of CTS pin input.\nNote: Refer to Figure 6.135 for more information" "0: CTS pin input is high level active,1: CTS pin input is low level active"
|
|
rbitfld.long 0x00 4. "CTS_ST,CTS Pin Status (Read Only) (Not Available In UART2 Channel)\nThis bit mirror from CTS pin input of voltage logic status.\nNote: This bit echoes when UART Controller peripheral clock is enabled and CTS multi-function port is selected" "0: CTS pin input is low level voltage logic state,1: CTS pin input is high level voltage logic state"
|
|
newline
|
|
rbitfld.long 0x00 0. "DCTSF,Detect CTS State Change Flag (Read Only) (Not Available In UART2 Channel)\nThis bit is set whenever CTS input has change state and it will generate Modem interrupt to CPU when MODEM_IEN (UA_IER [3]) is set to 1.\nNote: This bit is read only but.." "0: CTS input has not change state,1: CTS input has change state"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "UA_FSR,UART FIFO Status Register"
|
|
rbitfld.long 0x00 28. "TE_FLAG,Transmitter Empty Flag (Read Only)\nThis bit is set by hardware when TX FIFO (UA_THR) is empty and the STOP bit of the last byte has been transmitted.\nNote: This bit is cleared automatically when TX FIFO is not empty or the last byte.." "0: TX FIFO is not empty,1: TX FIFO is empty"
|
|
rbitfld.long 0x00 24. "TX_OVER_IF,TX Overflow Error Interrupt Flag (Read Only)\nIf TX FIFO (UA_THR) is full an additional write to UA_THR will cause this bit to logic 1.\nNote: This bit is read only but can be cleared by writing '1' to it" "0: TX FIFO is not overflow,1: TX FIFO is overflow"
|
|
newline
|
|
rbitfld.long 0x00 23. "TX_FULL,Transmitter FIFO Full (Read Only)\nThis bit indicates TX FIFO full or not.\nThis bit is set when the number of usage in TX FIFO Buffer is equal to 64/16/16(UART0/UART1/UART2) otherwise is cleared by hardware" "0: TX FIFO is not full,1: TX FIFO is full"
|
|
rbitfld.long 0x00 22. "TX_EMPTY,Transmitter FIFO Empty (Read Only)\nThis bit indicates TX FIFO empty or not.\nNote: When the last byte of TX FIFO has been transferred to Transmitter Shift Register hardware sets this bit high" "0: TX FIFO is not empty,1: TX FIFO is empty"
|
|
newline
|
|
rbitfld.long 0x00 16.--21. "TX_POINTER,TX FIFO Pointer (Read Only)\nThis field indicates the TX FIFO Buffer Pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rbitfld.long 0x00 15. "RX_FULL,Receiver FIFO Full (Read Only)\nThis bit initiates RX FIFO is full or not.\nNote: This bit is set when the number of usage in RX FIFO Buffer is equal to 64/16/16(UART0/UART1/UART2) otherwise is cleared by hardware" "0: RX FIFO is not full,1: RX FIFO is full"
|
|
newline
|
|
rbitfld.long 0x00 14. "RX_EMPTY,Receiver FIFO Empty (Read Only)\nThis bit initiate RX FIFO empty or not.\nNote: When the last byte of RX FIFO has been read by CPU hardware sets this bit high" "0: RX FIFO is not empty,1: RX FIFO is empty"
|
|
rbitfld.long 0x00 8.--13. "RX_POINTER,RX FIFO Pointer (Read Only)\nThis field indicates the RX FIFO Buffer Pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
rbitfld.long 0x00 6. "BIF,Break Interrupt Flag (Read Only)\nThis bit is set to logic 1 whenever the received data input(RX) is held in the 'spacing state' (logic 0) for longer than a full word transmission time (that is the total time of 'start bit' + data bits + parity +.." "0: No Break interrupt is generated,1: Break interrupt is generated"
|
|
rbitfld.long 0x00 5. "FEF,Framing Error Flag (Read Only)\nThis bit is set to logic 1 whenever the received character does not have a valid 'stop bit' (that is the stop bit following the last data bit or parity bit is detected as logic 0) and is reset whenever the CPU writes.." "0: No framing error is generated,1: Framing error is generated"
|
|
newline
|
|
rbitfld.long 0x00 4. "PEF,Parity Error Flag (Read Only)\nThis bit is set to logic 1 whenever the received character does not have a valid 'parity bit' and is reset whenever the CPU writes 1 to this bit.\nNote: This bit is read only but can be cleared by writing '1' to it" "0: No parity error is generated,1: Parity error is generated"
|
|
rbitfld.long 0x00 3. "RS485_ADD_DETF,RS-485 Address Byte Detection Flag (Read Only) \nNote1: This field is used for RS-485 function mode and RS485_ADD_EN (UA_ALT_CSR[15]) is set to 1 to enable Address detection mode.\nNote2: This bit is read only but can be cleared by.." "0: Receiver detects a data that is not an..,1: Receiver detects a data that is an address.."
|
|
newline
|
|
rbitfld.long 0x00 0. "RX_OVER_IF,RX Overflow Error IF (Read Only)\nThis bit is set when RX FIFO overflow.\nIf the number of bytes of received data is greater than RX_FIFO (UA_RBR) size 64/16/16 bytes of UART0/UART1/UART2 this bit will be set.\nNote: This bit is read only but.." "0: RX FIFO is not overflow,1: RX FIFO is overflow"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "UA_ISR,UART Interrupt Status Register"
|
|
rbitfld.long 0x00 29. "HW_BUF_ERR_INT,In DMA Mode Buffer Error Interrupt Indicator (Read Only)\nThis bit is set if BUF_ERR_IEN (UA_IER[5]) and HW_BUF_ERR_IF (UA_ISR[5])are both set to 1" "0: No buffer error interrupt is generated in DMA..,1: Buffer error interrupt is generated in DMA mode"
|
|
rbitfld.long 0x00 28. "HW_TOUT_INT,In DMA Mode Time-Out Interrupt Indicator (Read Only)\nThis bit is set if TOUT_IEN (UA_IER[4])and HW_TOUT_IF(UA_ISR[20]) are both set to 1" "0: No Tout interrupt is generated in DMA mode,1: Tout interrupt is generated in DMA mode"
|
|
newline
|
|
rbitfld.long 0x00 27. "HW_MODEM_INT,In DMA Mode MODEM Status Interrupt Indicator (Read Only) (Not Available In UART2 Channel)\nThis bit is set if MODEM_IEN(UA_IER[3]) and HW_MODEM_IF(UA_ ISR[3]) are both set to 1" "0: No Modem interrupt is generated in DMA mode,1: Modem interrupt is generated in DMA mode"
|
|
rbitfld.long 0x00 26. "HW_RLS_INT,In DMA Mode Receive Line Status Interrupt Indicator (Read Only)\nThis bit is set if RLS_IEN (UA_IER[2])and HW_RLS_IF(UA_ISR[18]) are both set to 1" "0: No RLS interrupt is generated in DMA mode,1: RLS interrupt is generated in DMA mode"
|
|
newline
|
|
rbitfld.long 0x00 21. "HW_BUF_ERR_IF,In DMA Mode Buffer Error Interrupt Flag (Read Only)\nThis bit is set when the TX or RX FIFO overflows (TX_OVER_IF (UA__FSR[24]) or RX_OVER_IF (UA_FSR[0]) is set)" "0: No buffer error interrupt flag is generated,1: Buffer error interrupt flag is generated"
|
|
rbitfld.long 0x00 20. "HW_TOUT_IF,In DMA Mode Time-Out Interrupt Flag (Read Only)\nThis bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC (UA_TOR[7:0])" "0: No Time-out interrupt flag is generated,1: Time-out interrupt flag is generated"
|
|
newline
|
|
rbitfld.long 0x00 19. "HW_MODEM_IF,In DMA Mode MODEM Interrupt Flag (Read Only) (Not Available In UART2 Channel)\nNote: This bit is read only and reset to 0 when the bit DCTSF(US_MSR[0]) is cleared by writing 1 on DCTSF (US_MSR[0])" "0: No Modem interrupt flag is generated,1: Modem interrupt flag is generated"
|
|
rbitfld.long 0x00 18. "HW_RLS_IF,In DMA Mode Receive Line Status Flag (Read Only)\nThis bit is set when the RX receive data have parity error frame error or break error (at least one of 3 bits BIF (UA_FSR[6]) FEF (UA_FSR[5]) and PEF (UA_FSR[4]) is set)" "0: No RLS interrupt flag is generated,1: RLS interrupt flag is generated"
|
|
newline
|
|
rbitfld.long 0x00 15. "LIN_INT,LIN Bus Interrupt Indicator (Read Only)\nThis bit is set if LIN_IEN (UA_IER[8]) and LIN _IF(UA_ISR[7]) are both set to 1" "0: No LIN Bus interrupt is generated,1: The LIN Bus interrupt is generated"
|
|
rbitfld.long 0x00 13. "BUF_ERR_INT,Buffer Error Interrupt Indicator (Read Only)\nThis bit is set if BUF_ERR_IEN(UA_IER[5] and BUF_ERR_IF(UA_ISR[5]) are both set to 1" "0: No buffer error interrupt is generated,1: Buffer error interrupt is generated"
|
|
newline
|
|
rbitfld.long 0x00 12. "TOUT_INT,Time-Out Interrupt Indicator (Read Only)\nThis bit is set if TOUT_IEN(UA_IER[4]) and TOUT_IF(UA_ISR[4]) are both set to 1" "0: No Tout interrupt is generated,1: Tout interrupt is generated"
|
|
rbitfld.long 0x00 11. "MODEM_INT,MODEM Status Interrupt Indicator (Read Only) (Not Available In UART2 Channel)\nThis bit is set if MODEM_IEN(UA_IER[3] and MODEM_IF(UA_ISR[4]) are both set to 1" "0: No Modem interrupt is generated,1: Modem interrupt is generated"
|
|
newline
|
|
rbitfld.long 0x00 10. "RLS_INT,Receive Line Status Interrupt Indicator (Read Only) \nThis bit is set if RLS_IEN (UA_IER[2]) and RLS_IF(UA_ISR[2]) are both set to 1" "0: No RLS interrupt is generated,1: RLS interrupt is generated"
|
|
rbitfld.long 0x00 9. "THRE_INT,Transmit Holding Register Empty Interrupt Indicator (Read Only)\nThis bit is set if THRE_IEN (UA_IER[1])and THRE_IF(UA_SR[1]) are both set to 1" "0: No THRE interrupt is generated,1: THRE interrupt is generated"
|
|
newline
|
|
rbitfld.long 0x00 8. "RDA_INT,Receive Data Available Interrupt Indicator (Read Only)\nThis bit is set if RDA_IEN (UA_IER[0]) and RDA_IF (UA_ISR[0]) are both set to 1" "0: No RDA interrupt is generated,1: RDA interrupt is generated"
|
|
rbitfld.long 0x00 7. "LIN_IF,LIN Bus Flag (Read Only)\nNote: This bit is read only" "0: None of LINS_HDET_F LIN_BKDET_F BIT_ERR_F..,1: At least one of LINS_HDET_F LIN_BKDET_F.."
|
|
newline
|
|
rbitfld.long 0x00 5. "BUF_ERR_IF,Buffer Error Interrupt Flag (Read Only)\nThis bit is set when the TX FIFO or RX FIFO overflows (TX_OVER_IF (UA_FSR[24]) or RX_OVER_IF (UA_FSR[0]) is set)" "0: No buffer error interrupt flag is generated,1: Buffer error interrupt flag is generated.0 =.."
|
|
rbitfld.long 0x00 4. "TOUT_IF,Time-Out Interrupt Flag (Read Only)\nThis bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC" "0: No Time-out interrupt flag is generated,1: Time-out interrupt flag is generated"
|
|
newline
|
|
rbitfld.long 0x00 3. "MODEM_IF,MODEM Interrupt Flag (Read Only) (Not Available In UART2 Channel)\nNote: This bit is read only and reset to 0 when bit DCTSF is cleared by a write 1 on DCTSF(UA_MSR[0])" "0: No Modem interrupt flag is generated,1: Modem interrupt flag is generated"
|
|
rbitfld.long 0x00 2. "RLS_IF,Receive Line Interrupt Flag (Read Only) \nThis bit is set when the RX receive data have parity error frame error or break error (at least one of 3 bits BIF(UA_FSR[6]) FEF(UA_FSR[5]) and PEF(UA_FSR[4]) is set)" "0: No RLS interrupt flag is generated,1: RLS interrupt flag is generated"
|
|
newline
|
|
rbitfld.long 0x00 1. "THRE_IF,Transmit Holding Register Empty Interrupt Flag (Read Only) \nThis bit is set when the last data of TX FIFO is transferred to Transmitter Shift Register" "0: No THRE interrupt flag is generated,1: THRE interrupt flag is generated"
|
|
rbitfld.long 0x00 0. "RDA_IF,Receive Data Available Interrupt Flag (Read Only)\nWhen the number of bytes in the RX FIFO equals the RFITL then the RDA_IF(UA_ISR[0]) will be set" "0: No RDA interrupt flag is generated,1: RDA interrupt flag is generated"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "UA_TOR,UART Time-out Register"
|
|
hexmask.long.byte 0x00 8.--15. 1. "DLY,TX Delay Time Value \nThis field is used to programming the transfer delay time between the last stop bit and next start bit"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TOIC,Time-Out Interrupt Comparator"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "UA_BAUD,UART Baud Rate Divisor Register"
|
|
bitfld.long 0x00 29. "DIV_X_EN,Divider X Enable Bit\nRefer to Table 6.132 for more information.\nNote: In IrDA mode this bit must disable" "0: Divider X Disabled (the equation of M = 16),1: Divider X Enabled (the equation of M = X+1.."
|
|
bitfld.long 0x00 28. "DIV_X_ONE,Divider X Equal To 1\nRefer to Table 6.132 for more information" "0: Divider M = X (the equation of M = X+1 but..,1: Divider M = 1 (the equation of M = 1 but BRD.."
|
|
newline
|
|
bitfld.long 0x00 24.--27. "DIVIDER_X,Divider X" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--15. 1. "BRD,Baud Rate Divider\nThe field indicates the baud rate divider"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "UA_IRCR,UART IrDA Control Register"
|
|
bitfld.long 0x00 6. "INV_RX,IrDA Inverse Receive Input Signal Control" "0: None inverse receiving input signal,1: Inverse receiving input signal"
|
|
bitfld.long 0x00 5. "INV_TX,IrDA Inverse Transmitting Output Signal Control" "0: None inverse transmitting signal,1: Inverse transmitting output signal"
|
|
newline
|
|
bitfld.long 0x00 1. "TX_SELECT,TX_SELECT" "0: IrDA Transmitter Disabled and Receiver Enabled,1: IrDA Transmitter Enabled and Receiver Disabled"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "UA_ALT_CSR,UART Alternate Control/Status Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "ADDR_MATCH,Address Match Value Register \nThis field contains the RS-485 address match values.\nNote: This field is used for RS-485 auto address detection mode"
|
|
bitfld.long 0x00 15. "RS485_ADD_EN,RS-485 Address Detection Enable Bit\nThis bit is used to enable RS-485 Address Detection mode" "0: Address detection mode Disabled,1: Address detection mode Enabled"
|
|
newline
|
|
bitfld.long 0x00 10. "RS485_AUD,RS-485 Auto Direction Mode (AUD) \nNote: It can be active with RS-485_AAD or RS-485_NMM operation mode" "0: RS-485 Auto Direction Operation mode (AUO)..,1: RS-485 Auto Direction Operation mode (AUO).."
|
|
bitfld.long 0x00 9. "RS485_AAD,RS-485 Auto Address Detection Operation Mode (AAD)\nNote: It cannot be active with RS-485_NMM operation mode" "0: RS-485 Auto Address Detection Operation mode..,1: RS-485 Auto Address Detection Operation mode.."
|
|
newline
|
|
bitfld.long 0x00 8. "RS485_NMM,RS-485 Normal Multi-Drop Operation Mode (NMM) \nNote: It cannot be active with RS-485_AAD operation mode" "0: RS-485 Normal Multi-drop Operation mode (NMM)..,1: RS-485 Normal Multi-drop Operation mode (NMM).."
|
|
bitfld.long 0x00 7. "LIN_TX_EN,LIN TX Break Mode Enable Bit\nNote: When TX break field transfer operation finished this bit will be cleared automatically" "0: LIN TX Break mode Disabled,1: LIN TX Break mode Enabled"
|
|
newline
|
|
bitfld.long 0x00 6. "LIN_RX_EN,LIN RX Enable Bit" "0: LIN RX mode Disabled,1: LIN RX mode Enabled"
|
|
bitfld.long 0x00 0.--3. "LIN_BKFL,UART LIN Break Field Length\nThis field indicates a 4-bit LIN TX break field count.\nNote1: This break field length is UA_LIN_BKFL + 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "UA_FUN_SEL,UART Function Select Register"
|
|
bitfld.long 0x00 0.--1. "FUN_SEL,Function Select Enable Bit" "0: UART function Enabled,1: LIN function Enabled,2: IrDA function Enabled,3: RS-485 function Enabled"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "UA_LIN_CTL,UART LIN Control Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "LIN_PID,LIN PID Register\nIf the parity generated by hardware user fill ID0~ID5 (LIN_PID [29:24] )hardware will calculate P0 (LIN_PID[30]) and P1 (LIN_PID[31]) otherwise user must filled frame ID and parity in this field.\n\nNote1: User can fill any.."
|
|
bitfld.long 0x00 22.--23. "LIN_HEAD_SEL,LIN Header Select" "0: The LIN header includes 'break field',1: The LIN header includes 'break field' and..,2: The LIN header includes 'break field' 'sync..,3: Reserved"
|
|
newline
|
|
bitfld.long 0x00 20.--21. "LIN_BS_LEN,LIN Break/Sync Delimiter Length\n\nNote: This bit used for LIN master to sending header field" "0: The LIN break/sync delimiter length is 1 bit..,?,2: The LIN break/sync delimiter length is 2 bit..,3: The LIN break/sync delimiter length is 4 bit.."
|
|
bitfld.long 0x00 16.--19. "LIN_BKFL,LIN Break Field Length\nThis field indicates a 4-bit LIN TX break field count.\nNote1: These registers are shadow registers of LIN_BKFL User can read/write it by setting LIN_BKFL (UA_ALT_CSR[3:0]) or LIN_BKFL (UA_LIN_CTL[19:16].\nNote2: This.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 12. "BIT_ERR_EN,Bit Error Detect Enable Bit" "0: Bit error detection function Disabled,1: Bit error detection Enabled"
|
|
bitfld.long 0x00 11. "LIN_RX_DIS,LIN Receiver Disable Bit" "0: LIN receiver Enabled,1: LIN receiver Disabled"
|
|
newline
|
|
bitfld.long 0x00 10. "LIN_BKDET_EN,LIN Break Detection Enable Bit" "0: LIN break detection Disabled,1: LIN break detection Enabled"
|
|
bitfld.long 0x00 9. "LIN_IDPEN,LIN ID Parity Enable Bit" "0: LIN frame ID parity Disabled,1: LIN frame ID parity Enabled"
|
|
newline
|
|
bitfld.long 0x00 8. "LIN_SHD,LIN TX Send Header Enable Bit\nThe LIN TX header can be 'break field' or 'break and sync field' or 'break sync and frame ID field' it is depend on setting LIN_HEAD_SEL (UA_LIN_CTL[23:22]).\nNote1: These registers are shadow registers of LIN_SHD.." "0: Send LIN TX header Disabled,1: Send LIN TX header Enabled"
|
|
bitfld.long 0x00 4. "LIN_MUTE_EN,LIN Mute Mode Enable Bit\nNote: The exit from mute mode condition and each control and interactions of this field are explained in (LIN slave mode)" "0: LIN mute mode Disabled,1: LIN mute mode Enabled"
|
|
newline
|
|
bitfld.long 0x00 3. "LINS_DUM_EN,LIN Slave Divider Update Method Enable Bit\nNote2: This bit used for LIN Slave Automatic Resynchronization mode" "0: UA_BAUD updated is written by software (if no..,1: UA_BAUD is updated at the next received.."
|
|
bitfld.long 0x00 2. "LINS_ARS_EN,LIN Slave Automatic Resynchronization Mode Enable Bit\nNote2: When operation in Automatic Resynchronization mode the baud rate setting must be mode2 (BAUD_M1 (UA_BAUD [29]) and BAUD_M0 (UA_BAUD [28]) must be 1).\nNote3: The control and.." "0: LIN automatic resynchronization Disabled,1: LIN automatic resynchronization Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. "LINS_HDET_EN,LIN Slave Header Detection Enable Bit" "0: LIN slave header detection Disabled,1: LIN slave header detection Enabled"
|
|
bitfld.long 0x00 0. "LINS_EN,LIN Slave Mode Enable Bit" "0: LIN slave mode Disabled,1: LIN slave mode Enabled"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "UA_LIN_SR,UART LIN Status Register"
|
|
rbitfld.long 0x00 9. "BIT_ERR_F,Bit Error Detect Status Flag (Read Only)\nAt TX transfer state hardware will monitoring the bus state if the input pin (SIN) state not equals to the output pin (SOUT) state BIT_ERR_F (UA_LIN_SR[9]) will be set" "0,1"
|
|
rbitfld.long 0x00 8. "LIN_BKDET_F,LIN Break Detection Flag (Read Only)\nThis bit is set by hardware when a break is detected and be cleared by writing 1 to it through software" "0: LIN break not detected,1: LIN break detected"
|
|
newline
|
|
bitfld.long 0x00 3. "LINS_SYNC_F,LIN Slave Sync Field\nThis bit indicates that the LIN sync field is being analyzed in Automatic Resynchronization mode" "0: The current character is not at LIN sync state,1: The current character is at LIN sync state"
|
|
rbitfld.long 0x00 2. "LINS_IDPERR_F,LIN Slave ID Parity Error Flag (Read Only)\nThis bit is set by hardware when receipted frame ID parity is not correct" "0: No active,1: Receipted frame ID parity is not correct"
|
|
newline
|
|
rbitfld.long 0x00 1. "LINS_HERR_F,LIN Slave Header Error Flag (Read Only)\nThis bit is set by hardware when a LIN header error is detected in LIN slave mode and be cleared by writing 1 to it" "0: LIN header error not detected,1: LIN header error detected"
|
|
rbitfld.long 0x00 0. "LINS_HDET_F,LIN Slave Header Detection Flag (Read Only)\nThis bit is set by hardware when a LIN header is detected in LIN slave mode and be cleared by writing 1 to it.\nNote3: When enable ID parity check LIN_IDPEN (UA_LIN_CTL [9]) if hardware detect.." "0: LIN header not detected,1: LIN header detected (break + sync + frame ID)"
|
|
tree.end
|
|
tree "UART1"
|
|
base ad:0x40150000
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "UA_RBR,UART Receive Buffer Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. "RBR,Receive Buffer Register (Read Only)\nBy reading this register the UART will return the 8-bit data received from RX pin (LSB first)"
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "UA_THR,UART Transmit Holding Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. "THR,Transmit Holding Register\nBy writing one byte to this register the data byte will be stored in transmitter FIFO"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "UA_IER,UART Interrupt Enable Register"
|
|
bitfld.long 0x00 15. "DMA_RX_EN,RX DMA Enable Bit (Not Available In UART2 Channel)\nThis bit can enable or disable RX DMA service" "0: RX DMA Disabled,1: RX DMA Enabled"
|
|
bitfld.long 0x00 14. "DMA_TX_EN,TX DMA Enable Bit (Not Available In UART2 Channel)\nThis bit can enable or disable TX DMA service" "0: TX DMA Disabled,1: TX DMA Enabled"
|
|
newline
|
|
bitfld.long 0x00 13. "AUTO_CTS_EN,CTS Auto Flow Control Enable Bit (Not Available In UART2 Channel)\nWhen CTS auto-flow is enabled the UART will send data to external device when CTS input assert (UART will not send data to device until CTS is asserted)" "0: CTS auto flow control Disabled,1: CTS auto flow control Enabled"
|
|
bitfld.long 0x00 12. "AUTO_RTS_EN,RTS Auto Flow Control Enable Bit (Not Available In UART2 Channel)\nWhen RTS auto-flow is enabled if the number of bytes in the RX FIFO equals the RTS_TRI_LEV (UA_FCR [19:16]) the UART will de-assert RTS signal" "0: RTS auto flow control Disabled,1: RTS auto flow control Enabled"
|
|
newline
|
|
bitfld.long 0x00 11. "TIME_OUT_EN,Time-Out Counter Enable Bit" "0: Time-out counter Disabled,1: Time-out counter Enabled"
|
|
bitfld.long 0x00 8. "LIN_IEN,LIN Bus Interrupt Enable Bit\nNote: This field is used for LIN function mode" "0: Lin bus interrupt Disabled,1: Lin bus interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x00 6. "WAKE_EN,UART Wake-Up Function Enable Bit (Not Available In UART2 Channel)" "0: UART wake-up function Disabled,1: UART wake-up function Enabled when the chip.."
|
|
bitfld.long 0x00 5. "BUF_ERR_IEN,Buffer Error Interrupt Enable Bit" "0: BUF_ERR_INT Masked off,1: BUF_ERR_INT Enabled"
|
|
newline
|
|
bitfld.long 0x00 4. "TOUT_IEN,RX Time-Out Interrupt Enable Bit" "0: TOUT_INT Masked off,1: TOUT_INT Enabled"
|
|
bitfld.long 0x00 3. "MODEM_IEN,Modem Status Interrupt Enable Bit (Not Available In UART2 Channel)" "0: MODEM_INT Masked off,1: MODEM_INT Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. "RLS_IEN,Receive Line Status Interrupt Enable Bit" "0: RLS_INT Masked off,1: RLS_INT Enabled"
|
|
bitfld.long 0x00 1. "THRE_IEN,Transmit Holding Register Empty Interrupt Enable Bit" "0: THRE_INT Masked off,1: THRE_INT Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. "RDA_IEN,Receive Data Available Interrupt Enable Bit" "0: RDA_INT Masked off,1: RDA_INT Enabled"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "UA_FCR,UART FIFO Control Register"
|
|
bitfld.long 0x00 16.--19. "RTS_TRI_LEV,RTS Trigger Level For Auto-Flow Control Use (Not Available In UART2 Channel)\nNote: This field is used for RTS auto-flow control" "0: RTS Trigger Level is 1 byte,1: RTS Trigger Level is 4 bytes,2: RTS Trigger Level is 8 bytes,3: RTS Trigger Level is 14 bytes,4: RTS Trigger Level is 30/14 bytes (High..,5: RTS Trigger Level is 46/14 bytes (High..,6: RTS Trigger Level is 62/14 bytes (High..,?..."
|
|
bitfld.long 0x00 8. "RX_DIS,Receiver Disable Bit\nThe receiver is disabled or not (set 1 to disable receiver)\nNote: This field is used for RS-485 Normal Multi-drop mode" "0: Receiver Enabled,1: Receiver Disabled"
|
|
newline
|
|
bitfld.long 0x00 4.--7. "RFITL,RX FIFO Interrupt (INT_RDA) Trigger Level\nWhen the number of bytes in the receive FIFO equals the RFITL the RDA_IF will be set (if UA_IER [RDA_IEN] enabled and an interrupt will be generated)" "0: RX FIFO Interrupt Trigger Level is 1 byte,1: RX FIFO Interrupt Trigger Level is 4 bytes,2: RX FIFO Interrupt Trigger Level is 8 bytes,3: RX FIFO Interrupt Trigger Level is 14 bytes,4: RX FIFO Interrupt Trigger Level is 30/14..,5: RX FIFO Interrupt Trigger Level is 46/14..,6: RX FIFO Interrupt Trigger Level is 62/14..,?..."
|
|
bitfld.long 0x00 2. "TFR,TX Field Software Reset\nWhen TFR is set all the byte in the transmit FIFO and TX internal state machine are cleared.\nNote: This bit will automatically clear at least 3 UART peripherial clock cycles" "0: No effect,1: Reset the TX internal state machine and.."
|
|
newline
|
|
bitfld.long 0x00 1. "RFR,RX Field Software Reset\nWhen RFR is set all the byte in the receiver FIFO and RX internal state machine are cleared.\nNote: This bit will automatically clear at least 3 UART peripherial clock cycles" "0: No effect,1: Reset the RX internal state machine and.."
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "UA_LCR,UART Line Control Register"
|
|
bitfld.long 0x00 6. "BCB,Break Control Bit\nWhen this bit is set to logic 1 the serial data output (TX) is forced to the Spacing State (logic 0)" "0,1"
|
|
bitfld.long 0x00 5. "SPE,Stick Parity Enable Bit" "0: Stick parity Disabled,1: If PBE (UA_LCR[3]) and EBE (UA_LCR[4]) are.."
|
|
newline
|
|
bitfld.long 0x00 4. "EPE,Even Parity Enable Bit\nThis bit has effect only when PBE (UA_LCR[3]) is set" "0: Odd number of logic 1's is transmitted and..,1: Even number of logic 1's is transmitted and.."
|
|
bitfld.long 0x00 3. "PBE,Parity Bit Enable Bit" "0: No parity bit,1: Parity bit is generated on each outgoing.."
|
|
newline
|
|
bitfld.long 0x00 2. "NSB,Number Of 'STOP Bit'" "0: One ' STOP bit' is generated in the..,1: When select 5-bit word length 1.5 'STOP bit'.."
|
|
bitfld.long 0x00 0.--1. "WLS,Word Length Selection" "0: Word length is 5-bit,1: Word length is 6-bit,2: Word length is 7-bit,3: Word length is 8-bit"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "UA_MCR,UART Modem Control Register"
|
|
rbitfld.long 0x00 13. "RTS_ST,RTS Pin State (Read Only) (Not Available In UART2 Channel)\nThis bit mirror from RTS pin output of voltage logic status" "0: RTS pin output is low level voltage logic state,1: RTS pin output is high level voltage logic.."
|
|
bitfld.long 0x00 9. "LEV_RTS,RTS Pin Active Level (Not Available In UART2 Channel)\nThis bit defines the active level state of RTS pin output.\nNote1: Refer to Figure 6.136 and Figure 6.137 for UART function mode.\nNote2: Refer to Figure 6.1317 And Figure 6.1318 for RS-485.." "0: RTS pin output is high level active,1: RTS pin output is low level active"
|
|
newline
|
|
bitfld.long 0x00 1. "RTS,RTS (Request-To-Send) Signal Control (Not Available In UART2 Channel)\nThis bit is direct control internal RTS signal active or not and then drive the RTS pin output with LEV_RTS bit configuration.\nNote1: This RTS signal control bit is not.." "0: RTS signal is active,1: RTS signal is inactive"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "UA_MSR,UART Modem Status Register"
|
|
bitfld.long 0x00 8. "LEV_CTS,CTS Pin Active Level\nThis bit defines the active level state of CTS pin input.\nNote: Refer to Figure 6.135 for more information" "0: CTS pin input is high level active,1: CTS pin input is low level active"
|
|
rbitfld.long 0x00 4. "CTS_ST,CTS Pin Status (Read Only) (Not Available In UART2 Channel)\nThis bit mirror from CTS pin input of voltage logic status.\nNote: This bit echoes when UART Controller peripheral clock is enabled and CTS multi-function port is selected" "0: CTS pin input is low level voltage logic state,1: CTS pin input is high level voltage logic state"
|
|
newline
|
|
rbitfld.long 0x00 0. "DCTSF,Detect CTS State Change Flag (Read Only) (Not Available In UART2 Channel)\nThis bit is set whenever CTS input has change state and it will generate Modem interrupt to CPU when MODEM_IEN (UA_IER [3]) is set to 1.\nNote: This bit is read only but.." "0: CTS input has not change state,1: CTS input has change state"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "UA_FSR,UART FIFO Status Register"
|
|
rbitfld.long 0x00 28. "TE_FLAG,Transmitter Empty Flag (Read Only)\nThis bit is set by hardware when TX FIFO (UA_THR) is empty and the STOP bit of the last byte has been transmitted.\nNote: This bit is cleared automatically when TX FIFO is not empty or the last byte.." "0: TX FIFO is not empty,1: TX FIFO is empty"
|
|
rbitfld.long 0x00 24. "TX_OVER_IF,TX Overflow Error Interrupt Flag (Read Only)\nIf TX FIFO (UA_THR) is full an additional write to UA_THR will cause this bit to logic 1.\nNote: This bit is read only but can be cleared by writing '1' to it" "0: TX FIFO is not overflow,1: TX FIFO is overflow"
|
|
newline
|
|
rbitfld.long 0x00 23. "TX_FULL,Transmitter FIFO Full (Read Only)\nThis bit indicates TX FIFO full or not.\nThis bit is set when the number of usage in TX FIFO Buffer is equal to 64/16/16(UART0/UART1/UART2) otherwise is cleared by hardware" "0: TX FIFO is not full,1: TX FIFO is full"
|
|
rbitfld.long 0x00 22. "TX_EMPTY,Transmitter FIFO Empty (Read Only)\nThis bit indicates TX FIFO empty or not.\nNote: When the last byte of TX FIFO has been transferred to Transmitter Shift Register hardware sets this bit high" "0: TX FIFO is not empty,1: TX FIFO is empty"
|
|
newline
|
|
rbitfld.long 0x00 16.--21. "TX_POINTER,TX FIFO Pointer (Read Only)\nThis field indicates the TX FIFO Buffer Pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rbitfld.long 0x00 15. "RX_FULL,Receiver FIFO Full (Read Only)\nThis bit initiates RX FIFO is full or not.\nNote: This bit is set when the number of usage in RX FIFO Buffer is equal to 64/16/16(UART0/UART1/UART2) otherwise is cleared by hardware" "0: RX FIFO is not full,1: RX FIFO is full"
|
|
newline
|
|
rbitfld.long 0x00 14. "RX_EMPTY,Receiver FIFO Empty (Read Only)\nThis bit initiate RX FIFO empty or not.\nNote: When the last byte of RX FIFO has been read by CPU hardware sets this bit high" "0: RX FIFO is not empty,1: RX FIFO is empty"
|
|
rbitfld.long 0x00 8.--13. "RX_POINTER,RX FIFO Pointer (Read Only)\nThis field indicates the RX FIFO Buffer Pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
rbitfld.long 0x00 6. "BIF,Break Interrupt Flag (Read Only)\nThis bit is set to logic 1 whenever the received data input(RX) is held in the 'spacing state' (logic 0) for longer than a full word transmission time (that is the total time of 'start bit' + data bits + parity +.." "0: No Break interrupt is generated,1: Break interrupt is generated"
|
|
rbitfld.long 0x00 5. "FEF,Framing Error Flag (Read Only)\nThis bit is set to logic 1 whenever the received character does not have a valid 'stop bit' (that is the stop bit following the last data bit or parity bit is detected as logic 0) and is reset whenever the CPU writes.." "0: No framing error is generated,1: Framing error is generated"
|
|
newline
|
|
rbitfld.long 0x00 4. "PEF,Parity Error Flag (Read Only)\nThis bit is set to logic 1 whenever the received character does not have a valid 'parity bit' and is reset whenever the CPU writes 1 to this bit.\nNote: This bit is read only but can be cleared by writing '1' to it" "0: No parity error is generated,1: Parity error is generated"
|
|
rbitfld.long 0x00 3. "RS485_ADD_DETF,RS-485 Address Byte Detection Flag (Read Only) \nNote1: This field is used for RS-485 function mode and RS485_ADD_EN (UA_ALT_CSR[15]) is set to 1 to enable Address detection mode.\nNote2: This bit is read only but can be cleared by.." "0: Receiver detects a data that is not an..,1: Receiver detects a data that is an address.."
|
|
newline
|
|
rbitfld.long 0x00 0. "RX_OVER_IF,RX Overflow Error IF (Read Only)\nThis bit is set when RX FIFO overflow.\nIf the number of bytes of received data is greater than RX_FIFO (UA_RBR) size 64/16/16 bytes of UART0/UART1/UART2 this bit will be set.\nNote: This bit is read only but.." "0: RX FIFO is not overflow,1: RX FIFO is overflow"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "UA_ISR,UART Interrupt Status Register"
|
|
rbitfld.long 0x00 29. "HW_BUF_ERR_INT,In DMA Mode Buffer Error Interrupt Indicator (Read Only)\nThis bit is set if BUF_ERR_IEN (UA_IER[5]) and HW_BUF_ERR_IF (UA_ISR[5])are both set to 1" "0: No buffer error interrupt is generated in DMA..,1: Buffer error interrupt is generated in DMA mode"
|
|
rbitfld.long 0x00 28. "HW_TOUT_INT,In DMA Mode Time-Out Interrupt Indicator (Read Only)\nThis bit is set if TOUT_IEN (UA_IER[4])and HW_TOUT_IF(UA_ISR[20]) are both set to 1" "0: No Tout interrupt is generated in DMA mode,1: Tout interrupt is generated in DMA mode"
|
|
newline
|
|
rbitfld.long 0x00 27. "HW_MODEM_INT,In DMA Mode MODEM Status Interrupt Indicator (Read Only) (Not Available In UART2 Channel)\nThis bit is set if MODEM_IEN(UA_IER[3]) and HW_MODEM_IF(UA_ ISR[3]) are both set to 1" "0: No Modem interrupt is generated in DMA mode,1: Modem interrupt is generated in DMA mode"
|
|
rbitfld.long 0x00 26. "HW_RLS_INT,In DMA Mode Receive Line Status Interrupt Indicator (Read Only)\nThis bit is set if RLS_IEN (UA_IER[2])and HW_RLS_IF(UA_ISR[18]) are both set to 1" "0: No RLS interrupt is generated in DMA mode,1: RLS interrupt is generated in DMA mode"
|
|
newline
|
|
rbitfld.long 0x00 21. "HW_BUF_ERR_IF,In DMA Mode Buffer Error Interrupt Flag (Read Only)\nThis bit is set when the TX or RX FIFO overflows (TX_OVER_IF (UA__FSR[24]) or RX_OVER_IF (UA_FSR[0]) is set)" "0: No buffer error interrupt flag is generated,1: Buffer error interrupt flag is generated"
|
|
rbitfld.long 0x00 20. "HW_TOUT_IF,In DMA Mode Time-Out Interrupt Flag (Read Only)\nThis bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC (UA_TOR[7:0])" "0: No Time-out interrupt flag is generated,1: Time-out interrupt flag is generated"
|
|
newline
|
|
rbitfld.long 0x00 19. "HW_MODEM_IF,In DMA Mode MODEM Interrupt Flag (Read Only) (Not Available In UART2 Channel)\nNote: This bit is read only and reset to 0 when the bit DCTSF(US_MSR[0]) is cleared by writing 1 on DCTSF (US_MSR[0])" "0: No Modem interrupt flag is generated,1: Modem interrupt flag is generated"
|
|
rbitfld.long 0x00 18. "HW_RLS_IF,In DMA Mode Receive Line Status Flag (Read Only)\nThis bit is set when the RX receive data have parity error frame error or break error (at least one of 3 bits BIF (UA_FSR[6]) FEF (UA_FSR[5]) and PEF (UA_FSR[4]) is set)" "0: No RLS interrupt flag is generated,1: RLS interrupt flag is generated"
|
|
newline
|
|
rbitfld.long 0x00 15. "LIN_INT,LIN Bus Interrupt Indicator (Read Only)\nThis bit is set if LIN_IEN (UA_IER[8]) and LIN _IF(UA_ISR[7]) are both set to 1" "0: No LIN Bus interrupt is generated,1: The LIN Bus interrupt is generated"
|
|
rbitfld.long 0x00 13. "BUF_ERR_INT,Buffer Error Interrupt Indicator (Read Only)\nThis bit is set if BUF_ERR_IEN(UA_IER[5] and BUF_ERR_IF(UA_ISR[5]) are both set to 1" "0: No buffer error interrupt is generated,1: Buffer error interrupt is generated"
|
|
newline
|
|
rbitfld.long 0x00 12. "TOUT_INT,Time-Out Interrupt Indicator (Read Only)\nThis bit is set if TOUT_IEN(UA_IER[4]) and TOUT_IF(UA_ISR[4]) are both set to 1" "0: No Tout interrupt is generated,1: Tout interrupt is generated"
|
|
rbitfld.long 0x00 11. "MODEM_INT,MODEM Status Interrupt Indicator (Read Only) (Not Available In UART2 Channel)\nThis bit is set if MODEM_IEN(UA_IER[3] and MODEM_IF(UA_ISR[4]) are both set to 1" "0: No Modem interrupt is generated,1: Modem interrupt is generated"
|
|
newline
|
|
rbitfld.long 0x00 10. "RLS_INT,Receive Line Status Interrupt Indicator (Read Only) \nThis bit is set if RLS_IEN (UA_IER[2]) and RLS_IF(UA_ISR[2]) are both set to 1" "0: No RLS interrupt is generated,1: RLS interrupt is generated"
|
|
rbitfld.long 0x00 9. "THRE_INT,Transmit Holding Register Empty Interrupt Indicator (Read Only)\nThis bit is set if THRE_IEN (UA_IER[1])and THRE_IF(UA_SR[1]) are both set to 1" "0: No THRE interrupt is generated,1: THRE interrupt is generated"
|
|
newline
|
|
rbitfld.long 0x00 8. "RDA_INT,Receive Data Available Interrupt Indicator (Read Only)\nThis bit is set if RDA_IEN (UA_IER[0]) and RDA_IF (UA_ISR[0]) are both set to 1" "0: No RDA interrupt is generated,1: RDA interrupt is generated"
|
|
rbitfld.long 0x00 7. "LIN_IF,LIN Bus Flag (Read Only)\nNote: This bit is read only" "0: None of LINS_HDET_F LIN_BKDET_F BIT_ERR_F..,1: At least one of LINS_HDET_F LIN_BKDET_F.."
|
|
newline
|
|
rbitfld.long 0x00 5. "BUF_ERR_IF,Buffer Error Interrupt Flag (Read Only)\nThis bit is set when the TX FIFO or RX FIFO overflows (TX_OVER_IF (UA_FSR[24]) or RX_OVER_IF (UA_FSR[0]) is set)" "0: No buffer error interrupt flag is generated,1: Buffer error interrupt flag is generated.0 =.."
|
|
rbitfld.long 0x00 4. "TOUT_IF,Time-Out Interrupt Flag (Read Only)\nThis bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC" "0: No Time-out interrupt flag is generated,1: Time-out interrupt flag is generated"
|
|
newline
|
|
rbitfld.long 0x00 3. "MODEM_IF,MODEM Interrupt Flag (Read Only) (Not Available In UART2 Channel)\nNote: This bit is read only and reset to 0 when bit DCTSF is cleared by a write 1 on DCTSF(UA_MSR[0])" "0: No Modem interrupt flag is generated,1: Modem interrupt flag is generated"
|
|
rbitfld.long 0x00 2. "RLS_IF,Receive Line Interrupt Flag (Read Only) \nThis bit is set when the RX receive data have parity error frame error or break error (at least one of 3 bits BIF(UA_FSR[6]) FEF(UA_FSR[5]) and PEF(UA_FSR[4]) is set)" "0: No RLS interrupt flag is generated,1: RLS interrupt flag is generated"
|
|
newline
|
|
rbitfld.long 0x00 1. "THRE_IF,Transmit Holding Register Empty Interrupt Flag (Read Only) \nThis bit is set when the last data of TX FIFO is transferred to Transmitter Shift Register" "0: No THRE interrupt flag is generated,1: THRE interrupt flag is generated"
|
|
rbitfld.long 0x00 0. "RDA_IF,Receive Data Available Interrupt Flag (Read Only)\nWhen the number of bytes in the RX FIFO equals the RFITL then the RDA_IF(UA_ISR[0]) will be set" "0: No RDA interrupt flag is generated,1: RDA interrupt flag is generated"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "UA_TOR,UART Time-out Register"
|
|
hexmask.long.byte 0x00 8.--15. 1. "DLY,TX Delay Time Value \nThis field is used to programming the transfer delay time between the last stop bit and next start bit"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TOIC,Time-Out Interrupt Comparator"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "UA_BAUD,UART Baud Rate Divisor Register"
|
|
bitfld.long 0x00 29. "DIV_X_EN,Divider X Enable Bit\nRefer to Table 6.132 for more information.\nNote: In IrDA mode this bit must disable" "0: Divider X Disabled (the equation of M = 16),1: Divider X Enabled (the equation of M = X+1.."
|
|
bitfld.long 0x00 28. "DIV_X_ONE,Divider X Equal To 1\nRefer to Table 6.132 for more information" "0: Divider M = X (the equation of M = X+1 but..,1: Divider M = 1 (the equation of M = 1 but BRD.."
|
|
newline
|
|
bitfld.long 0x00 24.--27. "DIVIDER_X,Divider X" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--15. 1. "BRD,Baud Rate Divider\nThe field indicates the baud rate divider"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "UA_IRCR,UART IrDA Control Register"
|
|
bitfld.long 0x00 6. "INV_RX,IrDA Inverse Receive Input Signal Control" "0: None inverse receiving input signal,1: Inverse receiving input signal"
|
|
bitfld.long 0x00 5. "INV_TX,IrDA Inverse Transmitting Output Signal Control" "0: None inverse transmitting signal,1: Inverse transmitting output signal"
|
|
newline
|
|
bitfld.long 0x00 1. "TX_SELECT,TX_SELECT" "0: IrDA Transmitter Disabled and Receiver Enabled,1: IrDA Transmitter Enabled and Receiver Disabled"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "UA_ALT_CSR,UART Alternate Control/Status Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "ADDR_MATCH,Address Match Value Register \nThis field contains the RS-485 address match values.\nNote: This field is used for RS-485 auto address detection mode"
|
|
bitfld.long 0x00 15. "RS485_ADD_EN,RS-485 Address Detection Enable Bit\nThis bit is used to enable RS-485 Address Detection mode" "0: Address detection mode Disabled,1: Address detection mode Enabled"
|
|
newline
|
|
bitfld.long 0x00 10. "RS485_AUD,RS-485 Auto Direction Mode (AUD) \nNote: It can be active with RS-485_AAD or RS-485_NMM operation mode" "0: RS-485 Auto Direction Operation mode (AUO)..,1: RS-485 Auto Direction Operation mode (AUO).."
|
|
bitfld.long 0x00 9. "RS485_AAD,RS-485 Auto Address Detection Operation Mode (AAD)\nNote: It cannot be active with RS-485_NMM operation mode" "0: RS-485 Auto Address Detection Operation mode..,1: RS-485 Auto Address Detection Operation mode.."
|
|
newline
|
|
bitfld.long 0x00 8. "RS485_NMM,RS-485 Normal Multi-Drop Operation Mode (NMM) \nNote: It cannot be active with RS-485_AAD operation mode" "0: RS-485 Normal Multi-drop Operation mode (NMM)..,1: RS-485 Normal Multi-drop Operation mode (NMM).."
|
|
bitfld.long 0x00 7. "LIN_TX_EN,LIN TX Break Mode Enable Bit\nNote: When TX break field transfer operation finished this bit will be cleared automatically" "0: LIN TX Break mode Disabled,1: LIN TX Break mode Enabled"
|
|
newline
|
|
bitfld.long 0x00 6. "LIN_RX_EN,LIN RX Enable Bit" "0: LIN RX mode Disabled,1: LIN RX mode Enabled"
|
|
bitfld.long 0x00 0.--3. "LIN_BKFL,UART LIN Break Field Length\nThis field indicates a 4-bit LIN TX break field count.\nNote1: This break field length is UA_LIN_BKFL + 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "UA_FUN_SEL,UART Function Select Register"
|
|
bitfld.long 0x00 0.--1. "FUN_SEL,Function Select Enable Bit" "0: UART function Enabled,1: LIN function Enabled,2: IrDA function Enabled,3: RS-485 function Enabled"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "UA_LIN_CTL,UART LIN Control Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "LIN_PID,LIN PID Register\nIf the parity generated by hardware user fill ID0~ID5 (LIN_PID [29:24] )hardware will calculate P0 (LIN_PID[30]) and P1 (LIN_PID[31]) otherwise user must filled frame ID and parity in this field.\n\nNote1: User can fill any.."
|
|
bitfld.long 0x00 22.--23. "LIN_HEAD_SEL,LIN Header Select" "0: The LIN header includes 'break field',1: The LIN header includes 'break field' and..,2: The LIN header includes 'break field' 'sync..,3: Reserved"
|
|
newline
|
|
bitfld.long 0x00 20.--21. "LIN_BS_LEN,LIN Break/Sync Delimiter Length\n\nNote: This bit used for LIN master to sending header field" "0: The LIN break/sync delimiter length is 1 bit..,?,2: The LIN break/sync delimiter length is 2 bit..,3: The LIN break/sync delimiter length is 4 bit.."
|
|
bitfld.long 0x00 16.--19. "LIN_BKFL,LIN Break Field Length\nThis field indicates a 4-bit LIN TX break field count.\nNote1: These registers are shadow registers of LIN_BKFL User can read/write it by setting LIN_BKFL (UA_ALT_CSR[3:0]) or LIN_BKFL (UA_LIN_CTL[19:16].\nNote2: This.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 12. "BIT_ERR_EN,Bit Error Detect Enable Bit" "0: Bit error detection function Disabled,1: Bit error detection Enabled"
|
|
bitfld.long 0x00 11. "LIN_RX_DIS,LIN Receiver Disable Bit" "0: LIN receiver Enabled,1: LIN receiver Disabled"
|
|
newline
|
|
bitfld.long 0x00 10. "LIN_BKDET_EN,LIN Break Detection Enable Bit" "0: LIN break detection Disabled,1: LIN break detection Enabled"
|
|
bitfld.long 0x00 9. "LIN_IDPEN,LIN ID Parity Enable Bit" "0: LIN frame ID parity Disabled,1: LIN frame ID parity Enabled"
|
|
newline
|
|
bitfld.long 0x00 8. "LIN_SHD,LIN TX Send Header Enable Bit\nThe LIN TX header can be 'break field' or 'break and sync field' or 'break sync and frame ID field' it is depend on setting LIN_HEAD_SEL (UA_LIN_CTL[23:22]).\nNote1: These registers are shadow registers of LIN_SHD.." "0: Send LIN TX header Disabled,1: Send LIN TX header Enabled"
|
|
bitfld.long 0x00 4. "LIN_MUTE_EN,LIN Mute Mode Enable Bit\nNote: The exit from mute mode condition and each control and interactions of this field are explained in (LIN slave mode)" "0: LIN mute mode Disabled,1: LIN mute mode Enabled"
|
|
newline
|
|
bitfld.long 0x00 3. "LINS_DUM_EN,LIN Slave Divider Update Method Enable Bit\nNote2: This bit used for LIN Slave Automatic Resynchronization mode" "0: UA_BAUD updated is written by software (if no..,1: UA_BAUD is updated at the next received.."
|
|
bitfld.long 0x00 2. "LINS_ARS_EN,LIN Slave Automatic Resynchronization Mode Enable Bit\nNote2: When operation in Automatic Resynchronization mode the baud rate setting must be mode2 (BAUD_M1 (UA_BAUD [29]) and BAUD_M0 (UA_BAUD [28]) must be 1).\nNote3: The control and.." "0: LIN automatic resynchronization Disabled,1: LIN automatic resynchronization Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. "LINS_HDET_EN,LIN Slave Header Detection Enable Bit" "0: LIN slave header detection Disabled,1: LIN slave header detection Enabled"
|
|
bitfld.long 0x00 0. "LINS_EN,LIN Slave Mode Enable Bit" "0: LIN slave mode Disabled,1: LIN slave mode Enabled"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "UA_LIN_SR,UART LIN Status Register"
|
|
rbitfld.long 0x00 9. "BIT_ERR_F,Bit Error Detect Status Flag (Read Only)\nAt TX transfer state hardware will monitoring the bus state if the input pin (SIN) state not equals to the output pin (SOUT) state BIT_ERR_F (UA_LIN_SR[9]) will be set" "0,1"
|
|
rbitfld.long 0x00 8. "LIN_BKDET_F,LIN Break Detection Flag (Read Only)\nThis bit is set by hardware when a break is detected and be cleared by writing 1 to it through software" "0: LIN break not detected,1: LIN break detected"
|
|
newline
|
|
bitfld.long 0x00 3. "LINS_SYNC_F,LIN Slave Sync Field\nThis bit indicates that the LIN sync field is being analyzed in Automatic Resynchronization mode" "0: The current character is not at LIN sync state,1: The current character is at LIN sync state"
|
|
rbitfld.long 0x00 2. "LINS_IDPERR_F,LIN Slave ID Parity Error Flag (Read Only)\nThis bit is set by hardware when receipted frame ID parity is not correct" "0: No active,1: Receipted frame ID parity is not correct"
|
|
newline
|
|
rbitfld.long 0x00 1. "LINS_HERR_F,LIN Slave Header Error Flag (Read Only)\nThis bit is set by hardware when a LIN header error is detected in LIN slave mode and be cleared by writing 1 to it" "0: LIN header error not detected,1: LIN header error detected"
|
|
rbitfld.long 0x00 0. "LINS_HDET_F,LIN Slave Header Detection Flag (Read Only)\nThis bit is set by hardware when a LIN header is detected in LIN slave mode and be cleared by writing 1 to it.\nNote3: When enable ID parity check LIN_IDPEN (UA_LIN_CTL [9]) if hardware detect.." "0: LIN header not detected,1: LIN header detected (break + sync + frame ID)"
|
|
tree.end
|
|
tree "UART2"
|
|
base ad:0x40154000
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "UA_RBR,UART Receive Buffer Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. "RBR,Receive Buffer Register (Read Only)\nBy reading this register the UART will return the 8-bit data received from RX pin (LSB first)"
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "UA_THR,UART Transmit Holding Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. "THR,Transmit Holding Register\nBy writing one byte to this register the data byte will be stored in transmitter FIFO"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "UA_IER,UART Interrupt Enable Register"
|
|
bitfld.long 0x00 15. "DMA_RX_EN,RX DMA Enable Bit (Not Available In UART2 Channel)\nThis bit can enable or disable RX DMA service" "0: RX DMA Disabled,1: RX DMA Enabled"
|
|
bitfld.long 0x00 14. "DMA_TX_EN,TX DMA Enable Bit (Not Available In UART2 Channel)\nThis bit can enable or disable TX DMA service" "0: TX DMA Disabled,1: TX DMA Enabled"
|
|
newline
|
|
bitfld.long 0x00 13. "AUTO_CTS_EN,CTS Auto Flow Control Enable Bit (Not Available In UART2 Channel)\nWhen CTS auto-flow is enabled the UART will send data to external device when CTS input assert (UART will not send data to device until CTS is asserted)" "0: CTS auto flow control Disabled,1: CTS auto flow control Enabled"
|
|
bitfld.long 0x00 12. "AUTO_RTS_EN,RTS Auto Flow Control Enable Bit (Not Available In UART2 Channel)\nWhen RTS auto-flow is enabled if the number of bytes in the RX FIFO equals the RTS_TRI_LEV (UA_FCR [19:16]) the UART will de-assert RTS signal" "0: RTS auto flow control Disabled,1: RTS auto flow control Enabled"
|
|
newline
|
|
bitfld.long 0x00 11. "TIME_OUT_EN,Time-Out Counter Enable Bit" "0: Time-out counter Disabled,1: Time-out counter Enabled"
|
|
bitfld.long 0x00 8. "LIN_IEN,LIN Bus Interrupt Enable Bit\nNote: This field is used for LIN function mode" "0: Lin bus interrupt Disabled,1: Lin bus interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x00 6. "WAKE_EN,UART Wake-Up Function Enable Bit (Not Available In UART2 Channel)" "0: UART wake-up function Disabled,1: UART wake-up function Enabled when the chip.."
|
|
bitfld.long 0x00 5. "BUF_ERR_IEN,Buffer Error Interrupt Enable Bit" "0: BUF_ERR_INT Masked off,1: BUF_ERR_INT Enabled"
|
|
newline
|
|
bitfld.long 0x00 4. "TOUT_IEN,RX Time-Out Interrupt Enable Bit" "0: TOUT_INT Masked off,1: TOUT_INT Enabled"
|
|
bitfld.long 0x00 3. "MODEM_IEN,Modem Status Interrupt Enable Bit (Not Available In UART2 Channel)" "0: MODEM_INT Masked off,1: MODEM_INT Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. "RLS_IEN,Receive Line Status Interrupt Enable Bit" "0: RLS_INT Masked off,1: RLS_INT Enabled"
|
|
bitfld.long 0x00 1. "THRE_IEN,Transmit Holding Register Empty Interrupt Enable Bit" "0: THRE_INT Masked off,1: THRE_INT Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. "RDA_IEN,Receive Data Available Interrupt Enable Bit" "0: RDA_INT Masked off,1: RDA_INT Enabled"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "UA_FCR,UART FIFO Control Register"
|
|
bitfld.long 0x00 16.--19. "RTS_TRI_LEV,RTS Trigger Level For Auto-Flow Control Use (Not Available In UART2 Channel)\nNote: This field is used for RTS auto-flow control" "0: RTS Trigger Level is 1 byte,1: RTS Trigger Level is 4 bytes,2: RTS Trigger Level is 8 bytes,3: RTS Trigger Level is 14 bytes,4: RTS Trigger Level is 30/14 bytes (High..,5: RTS Trigger Level is 46/14 bytes (High..,6: RTS Trigger Level is 62/14 bytes (High..,?..."
|
|
bitfld.long 0x00 8. "RX_DIS,Receiver Disable Bit\nThe receiver is disabled or not (set 1 to disable receiver)\nNote: This field is used for RS-485 Normal Multi-drop mode" "0: Receiver Enabled,1: Receiver Disabled"
|
|
newline
|
|
bitfld.long 0x00 4.--7. "RFITL,RX FIFO Interrupt (INT_RDA) Trigger Level\nWhen the number of bytes in the receive FIFO equals the RFITL the RDA_IF will be set (if UA_IER [RDA_IEN] enabled and an interrupt will be generated)" "0: RX FIFO Interrupt Trigger Level is 1 byte,1: RX FIFO Interrupt Trigger Level is 4 bytes,2: RX FIFO Interrupt Trigger Level is 8 bytes,3: RX FIFO Interrupt Trigger Level is 14 bytes,4: RX FIFO Interrupt Trigger Level is 30/14..,5: RX FIFO Interrupt Trigger Level is 46/14..,6: RX FIFO Interrupt Trigger Level is 62/14..,?..."
|
|
bitfld.long 0x00 2. "TFR,TX Field Software Reset\nWhen TFR is set all the byte in the transmit FIFO and TX internal state machine are cleared.\nNote: This bit will automatically clear at least 3 UART peripherial clock cycles" "0: No effect,1: Reset the TX internal state machine and.."
|
|
newline
|
|
bitfld.long 0x00 1. "RFR,RX Field Software Reset\nWhen RFR is set all the byte in the receiver FIFO and RX internal state machine are cleared.\nNote: This bit will automatically clear at least 3 UART peripherial clock cycles" "0: No effect,1: Reset the RX internal state machine and.."
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "UA_LCR,UART Line Control Register"
|
|
bitfld.long 0x00 6. "BCB,Break Control Bit\nWhen this bit is set to logic 1 the serial data output (TX) is forced to the Spacing State (logic 0)" "0,1"
|
|
bitfld.long 0x00 5. "SPE,Stick Parity Enable Bit" "0: Stick parity Disabled,1: If PBE (UA_LCR[3]) and EBE (UA_LCR[4]) are.."
|
|
newline
|
|
bitfld.long 0x00 4. "EPE,Even Parity Enable Bit\nThis bit has effect only when PBE (UA_LCR[3]) is set" "0: Odd number of logic 1's is transmitted and..,1: Even number of logic 1's is transmitted and.."
|
|
bitfld.long 0x00 3. "PBE,Parity Bit Enable Bit" "0: No parity bit,1: Parity bit is generated on each outgoing.."
|
|
newline
|
|
bitfld.long 0x00 2. "NSB,Number Of 'STOP Bit'" "0: One ' STOP bit' is generated in the..,1: When select 5-bit word length 1.5 'STOP bit'.."
|
|
bitfld.long 0x00 0.--1. "WLS,Word Length Selection" "0: Word length is 5-bit,1: Word length is 6-bit,2: Word length is 7-bit,3: Word length is 8-bit"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "UA_FSR,UART FIFO Status Register"
|
|
rbitfld.long 0x00 28. "TE_FLAG,Transmitter Empty Flag (Read Only)\nThis bit is set by hardware when TX FIFO (UA_THR) is empty and the STOP bit of the last byte has been transmitted.\nNote: This bit is cleared automatically when TX FIFO is not empty or the last byte.." "0: TX FIFO is not empty,1: TX FIFO is empty"
|
|
rbitfld.long 0x00 24. "TX_OVER_IF,TX Overflow Error Interrupt Flag (Read Only)\nIf TX FIFO (UA_THR) is full an additional write to UA_THR will cause this bit to logic 1.\nNote: This bit is read only but can be cleared by writing '1' to it" "0: TX FIFO is not overflow,1: TX FIFO is overflow"
|
|
newline
|
|
rbitfld.long 0x00 23. "TX_FULL,Transmitter FIFO Full (Read Only)\nThis bit indicates TX FIFO full or not.\nThis bit is set when the number of usage in TX FIFO Buffer is equal to 64/16/16(UART0/UART1/UART2) otherwise is cleared by hardware" "0: TX FIFO is not full,1: TX FIFO is full"
|
|
rbitfld.long 0x00 22. "TX_EMPTY,Transmitter FIFO Empty (Read Only)\nThis bit indicates TX FIFO empty or not.\nNote: When the last byte of TX FIFO has been transferred to Transmitter Shift Register hardware sets this bit high" "0: TX FIFO is not empty,1: TX FIFO is empty"
|
|
newline
|
|
rbitfld.long 0x00 16.--21. "TX_POINTER,TX FIFO Pointer (Read Only)\nThis field indicates the TX FIFO Buffer Pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rbitfld.long 0x00 15. "RX_FULL,Receiver FIFO Full (Read Only)\nThis bit initiates RX FIFO is full or not.\nNote: This bit is set when the number of usage in RX FIFO Buffer is equal to 64/16/16(UART0/UART1/UART2) otherwise is cleared by hardware" "0: RX FIFO is not full,1: RX FIFO is full"
|
|
newline
|
|
rbitfld.long 0x00 14. "RX_EMPTY,Receiver FIFO Empty (Read Only)\nThis bit initiate RX FIFO empty or not.\nNote: When the last byte of RX FIFO has been read by CPU hardware sets this bit high" "0: RX FIFO is not empty,1: RX FIFO is empty"
|
|
rbitfld.long 0x00 8.--13. "RX_POINTER,RX FIFO Pointer (Read Only)\nThis field indicates the RX FIFO Buffer Pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
rbitfld.long 0x00 6. "BIF,Break Interrupt Flag (Read Only)\nThis bit is set to logic 1 whenever the received data input(RX) is held in the 'spacing state' (logic 0) for longer than a full word transmission time (that is the total time of 'start bit' + data bits + parity +.." "0: No Break interrupt is generated,1: Break interrupt is generated"
|
|
rbitfld.long 0x00 5. "FEF,Framing Error Flag (Read Only)\nThis bit is set to logic 1 whenever the received character does not have a valid 'stop bit' (that is the stop bit following the last data bit or parity bit is detected as logic 0) and is reset whenever the CPU writes.." "0: No framing error is generated,1: Framing error is generated"
|
|
newline
|
|
rbitfld.long 0x00 4. "PEF,Parity Error Flag (Read Only)\nThis bit is set to logic 1 whenever the received character does not have a valid 'parity bit' and is reset whenever the CPU writes 1 to this bit.\nNote: This bit is read only but can be cleared by writing '1' to it" "0: No parity error is generated,1: Parity error is generated"
|
|
rbitfld.long 0x00 3. "RS485_ADD_DETF,RS-485 Address Byte Detection Flag (Read Only) \nNote1: This field is used for RS-485 function mode and RS485_ADD_EN (UA_ALT_CSR[15]) is set to 1 to enable Address detection mode.\nNote2: This bit is read only but can be cleared by.." "0: Receiver detects a data that is not an..,1: Receiver detects a data that is an address.."
|
|
newline
|
|
rbitfld.long 0x00 0. "RX_OVER_IF,RX Overflow Error IF (Read Only)\nThis bit is set when RX FIFO overflow.\nIf the number of bytes of received data is greater than RX_FIFO (UA_RBR) size 64/16/16 bytes of UART0/UART1/UART2 this bit will be set.\nNote: This bit is read only but.." "0: RX FIFO is not overflow,1: RX FIFO is overflow"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "UA_ISR,UART Interrupt Status Register"
|
|
rbitfld.long 0x00 29. "HW_BUF_ERR_INT,In DMA Mode Buffer Error Interrupt Indicator (Read Only)\nThis bit is set if BUF_ERR_IEN (UA_IER[5]) and HW_BUF_ERR_IF (UA_ISR[5])are both set to 1" "0: No buffer error interrupt is generated in DMA..,1: Buffer error interrupt is generated in DMA mode"
|
|
rbitfld.long 0x00 28. "HW_TOUT_INT,In DMA Mode Time-Out Interrupt Indicator (Read Only)\nThis bit is set if TOUT_IEN (UA_IER[4])and HW_TOUT_IF(UA_ISR[20]) are both set to 1" "0: No Tout interrupt is generated in DMA mode,1: Tout interrupt is generated in DMA mode"
|
|
newline
|
|
rbitfld.long 0x00 27. "HW_MODEM_INT,In DMA Mode MODEM Status Interrupt Indicator (Read Only) (Not Available In UART2 Channel)\nThis bit is set if MODEM_IEN(UA_IER[3]) and HW_MODEM_IF(UA_ ISR[3]) are both set to 1" "0: No Modem interrupt is generated in DMA mode,1: Modem interrupt is generated in DMA mode"
|
|
rbitfld.long 0x00 26. "HW_RLS_INT,In DMA Mode Receive Line Status Interrupt Indicator (Read Only)\nThis bit is set if RLS_IEN (UA_IER[2])and HW_RLS_IF(UA_ISR[18]) are both set to 1" "0: No RLS interrupt is generated in DMA mode,1: RLS interrupt is generated in DMA mode"
|
|
newline
|
|
rbitfld.long 0x00 21. "HW_BUF_ERR_IF,In DMA Mode Buffer Error Interrupt Flag (Read Only)\nThis bit is set when the TX or RX FIFO overflows (TX_OVER_IF (UA__FSR[24]) or RX_OVER_IF (UA_FSR[0]) is set)" "0: No buffer error interrupt flag is generated,1: Buffer error interrupt flag is generated"
|
|
rbitfld.long 0x00 20. "HW_TOUT_IF,In DMA Mode Time-Out Interrupt Flag (Read Only)\nThis bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC (UA_TOR[7:0])" "0: No Time-out interrupt flag is generated,1: Time-out interrupt flag is generated"
|
|
newline
|
|
rbitfld.long 0x00 19. "HW_MODEM_IF,In DMA Mode MODEM Interrupt Flag (Read Only) (Not Available In UART2 Channel)\nNote: This bit is read only and reset to 0 when the bit DCTSF(US_MSR[0]) is cleared by writing 1 on DCTSF (US_MSR[0])" "0: No Modem interrupt flag is generated,1: Modem interrupt flag is generated"
|
|
rbitfld.long 0x00 18. "HW_RLS_IF,In DMA Mode Receive Line Status Flag (Read Only)\nThis bit is set when the RX receive data have parity error frame error or break error (at least one of 3 bits BIF (UA_FSR[6]) FEF (UA_FSR[5]) and PEF (UA_FSR[4]) is set)" "0: No RLS interrupt flag is generated,1: RLS interrupt flag is generated"
|
|
newline
|
|
rbitfld.long 0x00 15. "LIN_INT,LIN Bus Interrupt Indicator (Read Only)\nThis bit is set if LIN_IEN (UA_IER[8]) and LIN _IF(UA_ISR[7]) are both set to 1" "0: No LIN Bus interrupt is generated,1: The LIN Bus interrupt is generated"
|
|
rbitfld.long 0x00 13. "BUF_ERR_INT,Buffer Error Interrupt Indicator (Read Only)\nThis bit is set if BUF_ERR_IEN(UA_IER[5] and BUF_ERR_IF(UA_ISR[5]) are both set to 1" "0: No buffer error interrupt is generated,1: Buffer error interrupt is generated"
|
|
newline
|
|
rbitfld.long 0x00 12. "TOUT_INT,Time-Out Interrupt Indicator (Read Only)\nThis bit is set if TOUT_IEN(UA_IER[4]) and TOUT_IF(UA_ISR[4]) are both set to 1" "0: No Tout interrupt is generated,1: Tout interrupt is generated"
|
|
rbitfld.long 0x00 11. "MODEM_INT,MODEM Status Interrupt Indicator (Read Only) (Not Available In UART2 Channel)\nThis bit is set if MODEM_IEN(UA_IER[3] and MODEM_IF(UA_ISR[4]) are both set to 1" "0: No Modem interrupt is generated,1: Modem interrupt is generated"
|
|
newline
|
|
rbitfld.long 0x00 10. "RLS_INT,Receive Line Status Interrupt Indicator (Read Only) \nThis bit is set if RLS_IEN (UA_IER[2]) and RLS_IF(UA_ISR[2]) are both set to 1" "0: No RLS interrupt is generated,1: RLS interrupt is generated"
|
|
rbitfld.long 0x00 9. "THRE_INT,Transmit Holding Register Empty Interrupt Indicator (Read Only)\nThis bit is set if THRE_IEN (UA_IER[1])and THRE_IF(UA_SR[1]) are both set to 1" "0: No THRE interrupt is generated,1: THRE interrupt is generated"
|
|
newline
|
|
rbitfld.long 0x00 8. "RDA_INT,Receive Data Available Interrupt Indicator (Read Only)\nThis bit is set if RDA_IEN (UA_IER[0]) and RDA_IF (UA_ISR[0]) are both set to 1" "0: No RDA interrupt is generated,1: RDA interrupt is generated"
|
|
rbitfld.long 0x00 7. "LIN_IF,LIN Bus Flag (Read Only)\nNote: This bit is read only" "0: None of LINS_HDET_F LIN_BKDET_F BIT_ERR_F..,1: At least one of LINS_HDET_F LIN_BKDET_F.."
|
|
newline
|
|
rbitfld.long 0x00 5. "BUF_ERR_IF,Buffer Error Interrupt Flag (Read Only)\nThis bit is set when the TX FIFO or RX FIFO overflows (TX_OVER_IF (UA_FSR[24]) or RX_OVER_IF (UA_FSR[0]) is set)" "0: No buffer error interrupt flag is generated,1: Buffer error interrupt flag is generated.0 =.."
|
|
rbitfld.long 0x00 4. "TOUT_IF,Time-Out Interrupt Flag (Read Only)\nThis bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC" "0: No Time-out interrupt flag is generated,1: Time-out interrupt flag is generated"
|
|
newline
|
|
rbitfld.long 0x00 3. "MODEM_IF,MODEM Interrupt Flag (Read Only) (Not Available In UART2 Channel)\nNote: This bit is read only and reset to 0 when bit DCTSF is cleared by a write 1 on DCTSF(UA_MSR[0])" "0: No Modem interrupt flag is generated,1: Modem interrupt flag is generated"
|
|
rbitfld.long 0x00 2. "RLS_IF,Receive Line Interrupt Flag (Read Only) \nThis bit is set when the RX receive data have parity error frame error or break error (at least one of 3 bits BIF(UA_FSR[6]) FEF(UA_FSR[5]) and PEF(UA_FSR[4]) is set)" "0: No RLS interrupt flag is generated,1: RLS interrupt flag is generated"
|
|
newline
|
|
rbitfld.long 0x00 1. "THRE_IF,Transmit Holding Register Empty Interrupt Flag (Read Only) \nThis bit is set when the last data of TX FIFO is transferred to Transmitter Shift Register" "0: No THRE interrupt flag is generated,1: THRE interrupt flag is generated"
|
|
rbitfld.long 0x00 0. "RDA_IF,Receive Data Available Interrupt Flag (Read Only)\nWhen the number of bytes in the RX FIFO equals the RFITL then the RDA_IF(UA_ISR[0]) will be set" "0: No RDA interrupt flag is generated,1: RDA interrupt flag is generated"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "UA_TOR,UART Time-out Register"
|
|
hexmask.long.byte 0x00 8.--15. 1. "DLY,TX Delay Time Value \nThis field is used to programming the transfer delay time between the last stop bit and next start bit"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TOIC,Time-Out Interrupt Comparator"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "UA_BAUD,UART Baud Rate Divisor Register"
|
|
bitfld.long 0x00 29. "DIV_X_EN,Divider X Enable Bit\nRefer to Table 6.132 for more information.\nNote: In IrDA mode this bit must disable" "0: Divider X Disabled (the equation of M = 16),1: Divider X Enabled (the equation of M = X+1.."
|
|
bitfld.long 0x00 28. "DIV_X_ONE,Divider X Equal To 1\nRefer to Table 6.132 for more information" "0: Divider M = X (the equation of M = X+1 but..,1: Divider M = 1 (the equation of M = 1 but BRD.."
|
|
newline
|
|
bitfld.long 0x00 24.--27. "DIVIDER_X,Divider X" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--15. 1. "BRD,Baud Rate Divider\nThe field indicates the baud rate divider"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "UA_IRCR,UART IrDA Control Register"
|
|
bitfld.long 0x00 6. "INV_RX,IrDA Inverse Receive Input Signal Control" "0: None inverse receiving input signal,1: Inverse receiving input signal"
|
|
bitfld.long 0x00 5. "INV_TX,IrDA Inverse Transmitting Output Signal Control" "0: None inverse transmitting signal,1: Inverse transmitting output signal"
|
|
newline
|
|
bitfld.long 0x00 1. "TX_SELECT,TX_SELECT" "0: IrDA Transmitter Disabled and Receiver Enabled,1: IrDA Transmitter Enabled and Receiver Disabled"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "UA_ALT_CSR,UART Alternate Control/Status Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "ADDR_MATCH,Address Match Value Register \nThis field contains the RS-485 address match values.\nNote: This field is used for RS-485 auto address detection mode"
|
|
bitfld.long 0x00 15. "RS485_ADD_EN,RS-485 Address Detection Enable Bit\nThis bit is used to enable RS-485 Address Detection mode" "0: Address detection mode Disabled,1: Address detection mode Enabled"
|
|
newline
|
|
bitfld.long 0x00 10. "RS485_AUD,RS-485 Auto Direction Mode (AUD) \nNote: It can be active with RS-485_AAD or RS-485_NMM operation mode" "0: RS-485 Auto Direction Operation mode (AUO)..,1: RS-485 Auto Direction Operation mode (AUO).."
|
|
bitfld.long 0x00 9. "RS485_AAD,RS-485 Auto Address Detection Operation Mode (AAD)\nNote: It cannot be active with RS-485_NMM operation mode" "0: RS-485 Auto Address Detection Operation mode..,1: RS-485 Auto Address Detection Operation mode.."
|
|
newline
|
|
bitfld.long 0x00 8. "RS485_NMM,RS-485 Normal Multi-Drop Operation Mode (NMM) \nNote: It cannot be active with RS-485_AAD operation mode" "0: RS-485 Normal Multi-drop Operation mode (NMM)..,1: RS-485 Normal Multi-drop Operation mode (NMM).."
|
|
bitfld.long 0x00 7. "LIN_TX_EN,LIN TX Break Mode Enable Bit\nNote: When TX break field transfer operation finished this bit will be cleared automatically" "0: LIN TX Break mode Disabled,1: LIN TX Break mode Enabled"
|
|
newline
|
|
bitfld.long 0x00 6. "LIN_RX_EN,LIN RX Enable Bit" "0: LIN RX mode Disabled,1: LIN RX mode Enabled"
|
|
bitfld.long 0x00 0.--3. "LIN_BKFL,UART LIN Break Field Length\nThis field indicates a 4-bit LIN TX break field count.\nNote1: This break field length is UA_LIN_BKFL + 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "UA_FUN_SEL,UART Function Select Register"
|
|
bitfld.long 0x00 0.--1. "FUN_SEL,Function Select Enable Bit" "0: UART function Enabled,1: LIN function Enabled,2: IrDA function Enabled,3: RS-485 function Enabled"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "UA_LIN_CTL,UART LIN Control Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "LIN_PID,LIN PID Register\nIf the parity generated by hardware user fill ID0~ID5 (LIN_PID [29:24] )hardware will calculate P0 (LIN_PID[30]) and P1 (LIN_PID[31]) otherwise user must filled frame ID and parity in this field.\n\nNote1: User can fill any.."
|
|
bitfld.long 0x00 22.--23. "LIN_HEAD_SEL,LIN Header Select" "0: The LIN header includes 'break field',1: The LIN header includes 'break field' and..,2: The LIN header includes 'break field' 'sync..,3: Reserved"
|
|
newline
|
|
bitfld.long 0x00 20.--21. "LIN_BS_LEN,LIN Break/Sync Delimiter Length\n\nNote: This bit used for LIN master to sending header field" "0: The LIN break/sync delimiter length is 1 bit..,?,2: The LIN break/sync delimiter length is 2 bit..,3: The LIN break/sync delimiter length is 4 bit.."
|
|
bitfld.long 0x00 16.--19. "LIN_BKFL,LIN Break Field Length\nThis field indicates a 4-bit LIN TX break field count.\nNote1: These registers are shadow registers of LIN_BKFL User can read/write it by setting LIN_BKFL (UA_ALT_CSR[3:0]) or LIN_BKFL (UA_LIN_CTL[19:16].\nNote2: This.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 12. "BIT_ERR_EN,Bit Error Detect Enable Bit" "0: Bit error detection function Disabled,1: Bit error detection Enabled"
|
|
bitfld.long 0x00 11. "LIN_RX_DIS,LIN Receiver Disable Bit" "0: LIN receiver Enabled,1: LIN receiver Disabled"
|
|
newline
|
|
bitfld.long 0x00 10. "LIN_BKDET_EN,LIN Break Detection Enable Bit" "0: LIN break detection Disabled,1: LIN break detection Enabled"
|
|
bitfld.long 0x00 9. "LIN_IDPEN,LIN ID Parity Enable Bit" "0: LIN frame ID parity Disabled,1: LIN frame ID parity Enabled"
|
|
newline
|
|
bitfld.long 0x00 8. "LIN_SHD,LIN TX Send Header Enable Bit\nThe LIN TX header can be 'break field' or 'break and sync field' or 'break sync and frame ID field' it is depend on setting LIN_HEAD_SEL (UA_LIN_CTL[23:22]).\nNote1: These registers are shadow registers of LIN_SHD.." "0: Send LIN TX header Disabled,1: Send LIN TX header Enabled"
|
|
bitfld.long 0x00 4. "LIN_MUTE_EN,LIN Mute Mode Enable Bit\nNote: The exit from mute mode condition and each control and interactions of this field are explained in (LIN slave mode)" "0: LIN mute mode Disabled,1: LIN mute mode Enabled"
|
|
newline
|
|
bitfld.long 0x00 3. "LINS_DUM_EN,LIN Slave Divider Update Method Enable Bit\nNote2: This bit used for LIN Slave Automatic Resynchronization mode" "0: UA_BAUD updated is written by software (if no..,1: UA_BAUD is updated at the next received.."
|
|
bitfld.long 0x00 2. "LINS_ARS_EN,LIN Slave Automatic Resynchronization Mode Enable Bit\nNote2: When operation in Automatic Resynchronization mode the baud rate setting must be mode2 (BAUD_M1 (UA_BAUD [29]) and BAUD_M0 (UA_BAUD [28]) must be 1).\nNote3: The control and.." "0: LIN automatic resynchronization Disabled,1: LIN automatic resynchronization Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. "LINS_HDET_EN,LIN Slave Header Detection Enable Bit" "0: LIN slave header detection Disabled,1: LIN slave header detection Enabled"
|
|
bitfld.long 0x00 0. "LINS_EN,LIN Slave Mode Enable Bit" "0: LIN slave mode Disabled,1: LIN slave mode Enabled"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "UA_LIN_SR,UART LIN Status Register"
|
|
rbitfld.long 0x00 9. "BIT_ERR_F,Bit Error Detect Status Flag (Read Only)\nAt TX transfer state hardware will monitoring the bus state if the input pin (SIN) state not equals to the output pin (SOUT) state BIT_ERR_F (UA_LIN_SR[9]) will be set" "0,1"
|
|
rbitfld.long 0x00 8. "LIN_BKDET_F,LIN Break Detection Flag (Read Only)\nThis bit is set by hardware when a break is detected and be cleared by writing 1 to it through software" "0: LIN break not detected,1: LIN break detected"
|
|
newline
|
|
bitfld.long 0x00 3. "LINS_SYNC_F,LIN Slave Sync Field\nThis bit indicates that the LIN sync field is being analyzed in Automatic Resynchronization mode" "0: The current character is not at LIN sync state,1: The current character is at LIN sync state"
|
|
rbitfld.long 0x00 2. "LINS_IDPERR_F,LIN Slave ID Parity Error Flag (Read Only)\nThis bit is set by hardware when receipted frame ID parity is not correct" "0: No active,1: Receipted frame ID parity is not correct"
|
|
newline
|
|
rbitfld.long 0x00 1. "LINS_HERR_F,LIN Slave Header Error Flag (Read Only)\nThis bit is set by hardware when a LIN header error is detected in LIN slave mode and be cleared by writing 1 to it" "0: LIN header error not detected,1: LIN header error detected"
|
|
rbitfld.long 0x00 0. "LINS_HDET_F,LIN Slave Header Detection Flag (Read Only)\nThis bit is set by hardware when a LIN header is detected in LIN slave mode and be cleared by writing 1 to it.\nNote3: When enable ID parity check LIN_IDPEN (UA_LIN_CTL [9]) if hardware detect.." "0: LIN header not detected,1: LIN header detected (break + sync + frame ID)"
|
|
tree.end
|
|
tree.end
|
|
tree "USB"
|
|
base ad:0x40060000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "USB_INTEN,USB Interrupt Enable Register"
|
|
bitfld.long 0x00 15. "INNAK_EN,Active NAK Function And Its Status In IN Token" "0: When device responds NAK after receiving IN..,1: IN NAK status will be updated to USBD_EPSTS.."
|
|
bitfld.long 0x00 8. "WAKEUP_EN,Wake-Up Function Enable Bit" "0: USB wake-up function Disabled,1: USB wake-up function Enabled"
|
|
newline
|
|
bitfld.long 0x00 3. "WAKEUP_IE,USB Wake-Up Interrupt Enable Bit" "0: Wake-up Interrupt Disabled,1: Wake-up Interrupt Enabled"
|
|
bitfld.long 0x00 2. "FLDET_IE,Floating Detection Interrupt Enable Bit" "0: Floating detection Interrupt Disabled,1: Floating detection Interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. "USB_IE,USB Event Interrupt Enable Bit" "0: USB event interrupt Disabled,1: USB event interrupt Enabled"
|
|
bitfld.long 0x00 0. "BUS_IE,Bus Event Interrupt Enable Bit" "0: BUS event interrupt Disabled,1: BUS event interrupt Enabled"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "USB_INTSTS,USB Interrupt Event Status Register"
|
|
bitfld.long 0x00 31. "SETUP,Setup Event Status" "0: No Setup event,1: SETUP event occurred cleared by write 1 to.."
|
|
bitfld.long 0x00 23. "EPEVT7,Endpoint 7's USB Event Status" "0: No event occurred on endpoint 7,1: USB event occurred on Endpoint 7 check.."
|
|
newline
|
|
bitfld.long 0x00 22. "EPEVT6,Endpoint 6's USB Event Status" "0: No event occurred on endpoint 6,1: USB event occurred on Endpoint 6 check.."
|
|
bitfld.long 0x00 21. "EPEVT5,Endpoint 5's USB Event Status" "0: No event occurred on endpoint 5,1: USB event occurred on Endpoint 5 check.."
|
|
newline
|
|
bitfld.long 0x00 20. "EPEVT4,Endpoint 4's USB Event Status" "0: No event occurred on endpoint 4,1: USB event occurred on Endpoint 4 check.."
|
|
bitfld.long 0x00 19. "EPEVT3,Endpoint 3's USB Event Status" "0: No event occurred on endpoint 3,1: USB event occurred on Endpoint 3 check.."
|
|
newline
|
|
bitfld.long 0x00 18. "EPEVT2,Endpoint 2's USB Event Status" "0: No event occurred on endpoint 2,1: USB event occurred on Endpoint 2 check.."
|
|
bitfld.long 0x00 17. "EPEVT1,Endpoint 1's USB Event Status" "0: No event occurred on endpoint 1,1: USB event occurred on Endpoint 1 check.."
|
|
newline
|
|
bitfld.long 0x00 16. "EPEVT0,Endpoint 0's USB Event Status" "0: No event occurred on endpoint 0,1: USB event occurred on Endpoint 0 check.."
|
|
bitfld.long 0x00 4. "SOSOF_STS,Start of Frame Interrupt Status" "0: SOF event does not occur,1: SOF event occurred cleared by write 1 to.."
|
|
newline
|
|
bitfld.long 0x00 3. "WAKEUP_STS,Wake-Up Interrupt Status" "0: No Wake-up event occurred,1: Wake-up event occurred cleared by write 1 to.."
|
|
bitfld.long 0x00 2. "FLDET_STS,Floating Detection Interrupt Status" "0: There is not attached/detached event in the USB,1: There is attached/detached event in the USB.."
|
|
newline
|
|
bitfld.long 0x00 1. "USB_STS,USB Event Interrupt Status\nThe USB event includes the SETUP Token IN Token OUT ACK ISO IN or ISO OUT events in the bus" "0: No USB event occurred,1: USB event occurred check EPSTS0~7 to know.."
|
|
bitfld.long 0x00 0. "BUS_STS,BUS Interrupt Status\nThe BUS event means that there is one of the suspense or the resume function in the bus" "0: No BUS event occurred,1: Bus event occurred check USB_ATTR[3:0] to.."
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "USB_FADDR,USB Device Function Address Register"
|
|
hexmask.long.byte 0x00 0.--6. 1. "FADDR,USB Device Function Address"
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "USB_EPSTS,USB Endpoint Status Register"
|
|
bitfld.long 0x00 29.--31. "EPSTS7,Endpoint 7 Bus Status\nThese bits are used to indicate the current status of this endpoint" "0: In ACK,1: In NAK,2: Out Packet Data0 ACK,3: Setup ACK,?,?,6: Out Packet Data1 ACK,7: Isochronous transfer end"
|
|
bitfld.long 0x00 26.--28. "EPSTS6,Endpoint 6 Bus Status\nThese bits are used to indicate the current status of this endpoint" "0: In ACK,1: In NAK,2: Out Packet Data0 ACK,3: Setup ACK,?,?,6: Out Packet Data1 ACK,7: Isochronous transfer end"
|
|
newline
|
|
bitfld.long 0x00 23.--25. "EPSTS5,Endpoint 5 Bus Status\nThese bits are used to indicate the current status of this endpoint" "0: In ACK,1: In NAK,2: Out Packet Data0 ACK,3: Setup ACK,?,?,6: Out Packet Data1 ACK,7: Isochronous transfer end"
|
|
bitfld.long 0x00 20.--22. "EPSTS4,Endpoint 4 Bus Status\nThese bits are used to indicate the current status of this endpoint" "0: In ACK,1: In NAK,2: Out Packet Data0 ACK,3: Setup ACK,?,?,6: Out Packet Data1 ACK,7: Isochronous transfer end"
|
|
newline
|
|
bitfld.long 0x00 17.--19. "EPSTS3,Endpoint 3 Bus Status\nThese bits are used to indicate the current status of this endpoint" "0: In ACK,1: In NAK,2: Out Packet Data0 ACK,3: Setup ACK,?,?,6: Out Packet Data1 ACK,7: Isochronous transfer end"
|
|
bitfld.long 0x00 14.--16. "EPSTS2,Endpoint 2 Bus Status\nThese bits are used to indicate the current status of this endpoint" "0: In ACK,1: In NAK,2: Out Packet Data0 ACK,3: Setup ACK,?,?,6: Out Packet Data1 ACK,7: Isochronous transfer end"
|
|
newline
|
|
bitfld.long 0x00 11.--13. "EPSTS1,Endpoint 1 Bus Status\nThese bits are used to indicate the current status of this endpoint" "0: In ACK,1: In NAK,2: Out Packet Data0 ACK,3: Setup ACK,?,?,6: Out Packet Data1 ACK,7: Isochronous transfer end"
|
|
bitfld.long 0x00 8.--10. "EPSTS0,Endpoint 0 Bus Status\nThese bits are used to indicate the current status of this endpoint" "0: In ACK,1: In NAK,2: Out Packet Data0 ACK,3: Setup ACK,?,?,6: Out Packet Data1 ACK,7: Isochronous transfer end"
|
|
newline
|
|
bitfld.long 0x00 7. "OVERRUN,Overrun\nIt indicates that the received data is over the maximum payload number or not" "0: No overrun,1: Out Data is more than the Max Payload in.."
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "USB_ATTR,USB Bus Status and Attribution Register"
|
|
bitfld.long 0x00 10. "BYTEM,CPU Access USB SRAM Size Mode Selection" "0: Word mode,1: Byte mode"
|
|
bitfld.long 0x00 9. "PWRDN,Power-Down PHY Transceiver Low Active" "0: Power-down related circuit of PHY transceiver,1: Turn-on related circuit of PHY transceiver"
|
|
newline
|
|
bitfld.long 0x00 8. "DPPU_EN,Pull-Up Resistor On USB_D+ Enable Bit" "0: Pull-up resistor in USB_D+ pin Disabled,1: Pull-up resistor in USB_D+ pin Enabled"
|
|
bitfld.long 0x00 7. "USB_EN,USB Controller Enable Bit" "0: USB Controller Disabled,1: USB Controller Enabled"
|
|
newline
|
|
bitfld.long 0x00 5. "RWAKEUP,Remote Wake-Up" "0: Release the USB bus from K state,1: Force USB bus to K (USB_D+ low USB_D- high).."
|
|
bitfld.long 0x00 4. "PHY_EN,PHY Transceiver Function Enable Bit" "0: PHY transceiver function Disabled,1: PHY transceiver function Enabled"
|
|
newline
|
|
bitfld.long 0x00 3. "TIMEOUT,Time-Out Status\nNote: This bit is read only" "0: No time-out,1: No Bus response more than 18 bits time"
|
|
bitfld.long 0x00 2. "RESUME,Resume Status\nNote: This bit is read only" "0: No bus resume,1: Resume from suspend"
|
|
newline
|
|
bitfld.long 0x00 1. "SUSPEND,Suspend Status\nNote: This bit is read only" "0: Bus no suspend,1: Bus idle more than 3ms either cable is.."
|
|
bitfld.long 0x00 0. "USBRST,USB Reset Status\nNote: This bit is read only" "0: Bus no reset,1: Bus reset when SE0 (single-ended 0) is.."
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "USB_FLDET,USB Floating Detection Register"
|
|
bitfld.long 0x00 0. "FLDET,Device Floating Detected" "0: Controller is not attached into the USB host,1: Controller is attached into the BUS"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "USB_STBUFSEG,Setup Token Buffer Segmentation Register"
|
|
bitfld.long 0x00 3.--8. "STBUFSEG,Setup Token Buffer Segmentation\nIt is used to indicate the offset address for the SETUP token with the USB Device SRAM starting address The effective starting address is\nUSB_SRAM address + {STBUFSEG[8:3] 3'b000} \nNote: It is used for SETUP.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rgroup.long 0x8C++0x03
|
|
line.long 0x00 "USBD_FN,USB Frame Number Register"
|
|
hexmask.long.word 0x00 0.--10. 1. "FN,Frame Number\nThese bits contain the 11-bits frame number in the last received SOF packet"
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "USB_DRVSE0,USB Drive SE0 Control Register"
|
|
bitfld.long 0x00 0. "DRVSE0,Drive Single Ended Zero In USB Bus\nThe Single Ended Zero (SE0) is when both lines (USB_D+ and USB_D-) are being pulled low" "0: None,1: Force USB PHY transceiver to drive SE0"
|
|
group.long 0x500++0x03
|
|
line.long 0x00 "USB_BUFSEG0,Endpoint 0 Buffer Segmentation Register"
|
|
bitfld.long 0x00 3.--8. "BUFSEG,Endpoint Buffer Segmentation\nIt is used to indicate the offset address for each endpoint with the USB SRAM starting address The effective starting address of the endpoint is\nUSB_SRAM address + { BUFSEG[8:3] 3'b000}\nRefer to the section 5.4.4.7.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x504++0x03
|
|
line.long 0x00 "USB_MXPLD0,Endpoint 0 Maximal Payload Register"
|
|
hexmask.long.word 0x00 0.--8. 1. "MXPLD,Maximal Payload\nDefine the data length which is transmitted to host (IN token) or the actual data length which is received from the host (OUT token)"
|
|
group.long 0x508++0x03
|
|
line.long 0x00 "USB_CFG0,Endpoint 0 Configuration Register"
|
|
bitfld.long 0x00 9. "CSTALL,Clear STALL Response" "0: Disable the device to clear the STALL..,1: Clear the device to response STALL handshake.."
|
|
bitfld.long 0x00 7. "DSQ_SYNC,Data Sequence Synchronization\nNote: It is used to specify the DATA0 or DATA1 PID in the following IN token transaction" "0: DATA0 PID,1: DATA1 PID"
|
|
newline
|
|
bitfld.long 0x00 5.--6. "STATE,Endpoint STATE" "0: Endpoint is Disabled,1: Out endpoint,2: IN endpoint,3: Undefined"
|
|
bitfld.long 0x00 4. "ISOCH,Isochronous Endpoint\nThis bit is used to set the endpoint as Isochronous endpoint no handshake" "0: No Isochronous endpoint,1: Isochronous endpoint"
|
|
newline
|
|
bitfld.long 0x00 0.--3. "EP_NUM,Endpoint Number\nThese bits are used to define the endpoint number of the current endpoint" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x50C++0x03
|
|
line.long 0x00 "USB_CFGP0,Endpoint 0 Set Stall and Clear In/Out Ready Control Register"
|
|
bitfld.long 0x00 1. "SSTALL,Set STALL" "0: Disable the device to response STALL,1: Set the device to respond STALL automatically"
|
|
bitfld.long 0x00 0. "CLRRDY,Clear Ready\nWhen the USB_MXPLD register is set by user it means that the endpoint is ready to transmit or receive data" "0,1"
|
|
group.long 0x510++0x03
|
|
line.long 0x00 "USB_BUFSEG1,Endpoint 1 Buffer Segmentation Register"
|
|
bitfld.long 0x00 3.--8. "BUFSEG,Endpoint Buffer Segmentation\nIt is used to indicate the offset address for each endpoint with the USB SRAM starting address The effective starting address of the endpoint is\nUSB_SRAM address + { BUFSEG[8:3] 3'b000}\nRefer to the section 5.4.4.7.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x514++0x03
|
|
line.long 0x00 "USB_MXPLD1,Endpoint 1 Maximal Payload Register"
|
|
hexmask.long.word 0x00 0.--8. 1. "MXPLD,Maximal Payload\nDefine the data length which is transmitted to host (IN token) or the actual data length which is received from the host (OUT token)"
|
|
group.long 0x518++0x03
|
|
line.long 0x00 "USB_CFG1,Endpoint 1 Configuration Register"
|
|
bitfld.long 0x00 9. "CSTALL,Clear STALL Response" "0: Disable the device to clear the STALL..,1: Clear the device to response STALL handshake.."
|
|
bitfld.long 0x00 7. "DSQ_SYNC,Data Sequence Synchronization\nNote: It is used to specify the DATA0 or DATA1 PID in the following IN token transaction" "0: DATA0 PID,1: DATA1 PID"
|
|
newline
|
|
bitfld.long 0x00 5.--6. "STATE,Endpoint STATE" "0: Endpoint is Disabled,1: Out endpoint,2: IN endpoint,3: Undefined"
|
|
bitfld.long 0x00 4. "ISOCH,Isochronous Endpoint\nThis bit is used to set the endpoint as Isochronous endpoint no handshake" "0: No Isochronous endpoint,1: Isochronous endpoint"
|
|
newline
|
|
bitfld.long 0x00 0.--3. "EP_NUM,Endpoint Number\nThese bits are used to define the endpoint number of the current endpoint" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x51C++0x03
|
|
line.long 0x00 "USB_CFGP1,Endpoint 1 Set Stall and Clear In/Out Ready Control Register"
|
|
bitfld.long 0x00 1. "SSTALL,Set STALL" "0: Disable the device to response STALL,1: Set the device to respond STALL automatically"
|
|
bitfld.long 0x00 0. "CLRRDY,Clear Ready\nWhen the USB_MXPLD register is set by user it means that the endpoint is ready to transmit or receive data" "0,1"
|
|
group.long 0x520++0x03
|
|
line.long 0x00 "USB_BUFSEG2,Endpoint 2 Buffer Segmentation Register"
|
|
bitfld.long 0x00 3.--8. "BUFSEG,Endpoint Buffer Segmentation\nIt is used to indicate the offset address for each endpoint with the USB SRAM starting address The effective starting address of the endpoint is\nUSB_SRAM address + { BUFSEG[8:3] 3'b000}\nRefer to the section 5.4.4.7.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x524++0x03
|
|
line.long 0x00 "USB_MXPLD2,Endpoint 2 Maximal Payload Register"
|
|
hexmask.long.word 0x00 0.--8. 1. "MXPLD,Maximal Payload\nDefine the data length which is transmitted to host (IN token) or the actual data length which is received from the host (OUT token)"
|
|
group.long 0x528++0x03
|
|
line.long 0x00 "USB_CFG2,Endpoint 2 Configuration Register"
|
|
bitfld.long 0x00 9. "CSTALL,Clear STALL Response" "0: Disable the device to clear the STALL..,1: Clear the device to response STALL handshake.."
|
|
bitfld.long 0x00 7. "DSQ_SYNC,Data Sequence Synchronization\nNote: It is used to specify the DATA0 or DATA1 PID in the following IN token transaction" "0: DATA0 PID,1: DATA1 PID"
|
|
newline
|
|
bitfld.long 0x00 5.--6. "STATE,Endpoint STATE" "0: Endpoint is Disabled,1: Out endpoint,2: IN endpoint,3: Undefined"
|
|
bitfld.long 0x00 4. "ISOCH,Isochronous Endpoint\nThis bit is used to set the endpoint as Isochronous endpoint no handshake" "0: No Isochronous endpoint,1: Isochronous endpoint"
|
|
newline
|
|
bitfld.long 0x00 0.--3. "EP_NUM,Endpoint Number\nThese bits are used to define the endpoint number of the current endpoint" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x52C++0x03
|
|
line.long 0x00 "USB_CFGP2,Endpoint 2 Set Stall and Clear In/Out Ready Control Register"
|
|
bitfld.long 0x00 1. "SSTALL,Set STALL" "0: Disable the device to response STALL,1: Set the device to respond STALL automatically"
|
|
bitfld.long 0x00 0. "CLRRDY,Clear Ready\nWhen the USB_MXPLD register is set by user it means that the endpoint is ready to transmit or receive data" "0,1"
|
|
group.long 0x530++0x03
|
|
line.long 0x00 "USB_BUFSEG3,Endpoint 3 Buffer Segmentation Register"
|
|
bitfld.long 0x00 3.--8. "BUFSEG,Endpoint Buffer Segmentation\nIt is used to indicate the offset address for each endpoint with the USB SRAM starting address The effective starting address of the endpoint is\nUSB_SRAM address + { BUFSEG[8:3] 3'b000}\nRefer to the section 5.4.4.7.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x534++0x03
|
|
line.long 0x00 "USB_MXPLD3,Endpoint 3 Maximal Payload Register"
|
|
hexmask.long.word 0x00 0.--8. 1. "MXPLD,Maximal Payload\nDefine the data length which is transmitted to host (IN token) or the actual data length which is received from the host (OUT token)"
|
|
group.long 0x538++0x03
|
|
line.long 0x00 "USB_CFG3,Endpoint 3 Configuration Register"
|
|
bitfld.long 0x00 9. "CSTALL,Clear STALL Response" "0: Disable the device to clear the STALL..,1: Clear the device to response STALL handshake.."
|
|
bitfld.long 0x00 7. "DSQ_SYNC,Data Sequence Synchronization\nNote: It is used to specify the DATA0 or DATA1 PID in the following IN token transaction" "0: DATA0 PID,1: DATA1 PID"
|
|
newline
|
|
bitfld.long 0x00 5.--6. "STATE,Endpoint STATE" "0: Endpoint is Disabled,1: Out endpoint,2: IN endpoint,3: Undefined"
|
|
bitfld.long 0x00 4. "ISOCH,Isochronous Endpoint\nThis bit is used to set the endpoint as Isochronous endpoint no handshake" "0: No Isochronous endpoint,1: Isochronous endpoint"
|
|
newline
|
|
bitfld.long 0x00 0.--3. "EP_NUM,Endpoint Number\nThese bits are used to define the endpoint number of the current endpoint" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x53C++0x03
|
|
line.long 0x00 "USB_CFGP3,Endpoint 3 Set Stall and Clear In/Out Ready Control Register"
|
|
bitfld.long 0x00 1. "SSTALL,Set STALL" "0: Disable the device to response STALL,1: Set the device to respond STALL automatically"
|
|
bitfld.long 0x00 0. "CLRRDY,Clear Ready\nWhen the USB_MXPLD register is set by user it means that the endpoint is ready to transmit or receive data" "0,1"
|
|
group.long 0x540++0x03
|
|
line.long 0x00 "USB_BUFSEG4,Endpoint 4 Buffer Segmentation Register"
|
|
bitfld.long 0x00 3.--8. "BUFSEG,Endpoint Buffer Segmentation\nIt is used to indicate the offset address for each endpoint with the USB SRAM starting address The effective starting address of the endpoint is\nUSB_SRAM address + { BUFSEG[8:3] 3'b000}\nRefer to the section 5.4.4.7.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x544++0x03
|
|
line.long 0x00 "USB_MXPLD4,Endpoint 4 Maximal Payload Register"
|
|
hexmask.long.word 0x00 0.--8. 1. "MXPLD,Maximal Payload\nDefine the data length which is transmitted to host (IN token) or the actual data length which is received from the host (OUT token)"
|
|
group.long 0x548++0x03
|
|
line.long 0x00 "USB_CFG4,Endpoint 4 Configuration Register"
|
|
bitfld.long 0x00 9. "CSTALL,Clear STALL Response" "0: Disable the device to clear the STALL..,1: Clear the device to response STALL handshake.."
|
|
bitfld.long 0x00 7. "DSQ_SYNC,Data Sequence Synchronization\nNote: It is used to specify the DATA0 or DATA1 PID in the following IN token transaction" "0: DATA0 PID,1: DATA1 PID"
|
|
newline
|
|
bitfld.long 0x00 5.--6. "STATE,Endpoint STATE" "0: Endpoint is Disabled,1: Out endpoint,2: IN endpoint,3: Undefined"
|
|
bitfld.long 0x00 4. "ISOCH,Isochronous Endpoint\nThis bit is used to set the endpoint as Isochronous endpoint no handshake" "0: No Isochronous endpoint,1: Isochronous endpoint"
|
|
newline
|
|
bitfld.long 0x00 0.--3. "EP_NUM,Endpoint Number\nThese bits are used to define the endpoint number of the current endpoint" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x54C++0x03
|
|
line.long 0x00 "USB_CFGP4,Endpoint 4 Set Stall and Clear In/Out Ready Control Register"
|
|
bitfld.long 0x00 1. "SSTALL,Set STALL" "0: Disable the device to response STALL,1: Set the device to respond STALL automatically"
|
|
bitfld.long 0x00 0. "CLRRDY,Clear Ready\nWhen the USB_MXPLD register is set by user it means that the endpoint is ready to transmit or receive data" "0,1"
|
|
group.long 0x550++0x03
|
|
line.long 0x00 "USB_BUFSEG5,Endpoint 5 Buffer Segmentation Register"
|
|
bitfld.long 0x00 3.--8. "BUFSEG,Endpoint Buffer Segmentation\nIt is used to indicate the offset address for each endpoint with the USB SRAM starting address The effective starting address of the endpoint is\nUSB_SRAM address + { BUFSEG[8:3] 3'b000}\nRefer to the section 5.4.4.7.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x554++0x03
|
|
line.long 0x00 "USB_MXPLD5,Endpoint 5 Maximal Payload Register"
|
|
hexmask.long.word 0x00 0.--8. 1. "MXPLD,Maximal Payload\nDefine the data length which is transmitted to host (IN token) or the actual data length which is received from the host (OUT token)"
|
|
group.long 0x558++0x03
|
|
line.long 0x00 "USB_CFG5,Endpoint 5 Configuration Register"
|
|
bitfld.long 0x00 9. "CSTALL,Clear STALL Response" "0: Disable the device to clear the STALL..,1: Clear the device to response STALL handshake.."
|
|
bitfld.long 0x00 7. "DSQ_SYNC,Data Sequence Synchronization\nNote: It is used to specify the DATA0 or DATA1 PID in the following IN token transaction" "0: DATA0 PID,1: DATA1 PID"
|
|
newline
|
|
bitfld.long 0x00 5.--6. "STATE,Endpoint STATE" "0: Endpoint is Disabled,1: Out endpoint,2: IN endpoint,3: Undefined"
|
|
bitfld.long 0x00 4. "ISOCH,Isochronous Endpoint\nThis bit is used to set the endpoint as Isochronous endpoint no handshake" "0: No Isochronous endpoint,1: Isochronous endpoint"
|
|
newline
|
|
bitfld.long 0x00 0.--3. "EP_NUM,Endpoint Number\nThese bits are used to define the endpoint number of the current endpoint" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x55C++0x03
|
|
line.long 0x00 "USB_CFGP5,Endpoint 5 Set Stall and Clear In/Out Ready Control Register"
|
|
bitfld.long 0x00 1. "SSTALL,Set STALL" "0: Disable the device to response STALL,1: Set the device to respond STALL automatically"
|
|
bitfld.long 0x00 0. "CLRRDY,Clear Ready\nWhen the USB_MXPLD register is set by user it means that the endpoint is ready to transmit or receive data" "0,1"
|
|
group.long 0x560++0x03
|
|
line.long 0x00 "USB_BUFSEG6,Endpoint 6 Buffer Segmentation Register"
|
|
bitfld.long 0x00 3.--8. "BUFSEG,Endpoint Buffer Segmentation\nIt is used to indicate the offset address for each endpoint with the USB SRAM starting address The effective starting address of the endpoint is\nUSB_SRAM address + { BUFSEG[8:3] 3'b000}\nRefer to the section 5.4.4.7.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x564++0x03
|
|
line.long 0x00 "USB_MXPLD6,Endpoint 6 Maximal Payload Register"
|
|
hexmask.long.word 0x00 0.--8. 1. "MXPLD,Maximal Payload\nDefine the data length which is transmitted to host (IN token) or the actual data length which is received from the host (OUT token)"
|
|
group.long 0x568++0x03
|
|
line.long 0x00 "USB_CFG6,Endpoint 6 Configuration Register"
|
|
bitfld.long 0x00 9. "CSTALL,Clear STALL Response" "0: Disable the device to clear the STALL..,1: Clear the device to response STALL handshake.."
|
|
bitfld.long 0x00 7. "DSQ_SYNC,Data Sequence Synchronization\nNote: It is used to specify the DATA0 or DATA1 PID in the following IN token transaction" "0: DATA0 PID,1: DATA1 PID"
|
|
newline
|
|
bitfld.long 0x00 5.--6. "STATE,Endpoint STATE" "0: Endpoint is Disabled,1: Out endpoint,2: IN endpoint,3: Undefined"
|
|
bitfld.long 0x00 4. "ISOCH,Isochronous Endpoint\nThis bit is used to set the endpoint as Isochronous endpoint no handshake" "0: No Isochronous endpoint,1: Isochronous endpoint"
|
|
newline
|
|
bitfld.long 0x00 0.--3. "EP_NUM,Endpoint Number\nThese bits are used to define the endpoint number of the current endpoint" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x56C++0x03
|
|
line.long 0x00 "USB_CFGP6,Endpoint 6 Set Stall and Clear In/Out Ready Control Register"
|
|
bitfld.long 0x00 1. "SSTALL,Set STALL" "0: Disable the device to response STALL,1: Set the device to respond STALL automatically"
|
|
bitfld.long 0x00 0. "CLRRDY,Clear Ready\nWhen the USB_MXPLD register is set by user it means that the endpoint is ready to transmit or receive data" "0,1"
|
|
group.long 0x570++0x03
|
|
line.long 0x00 "USB_BUFSEG7,Endpoint 7 Buffer Segmentation Register"
|
|
bitfld.long 0x00 3.--8. "BUFSEG,Endpoint Buffer Segmentation\nIt is used to indicate the offset address for each endpoint with the USB SRAM starting address The effective starting address of the endpoint is\nUSB_SRAM address + { BUFSEG[8:3] 3'b000}\nRefer to the section 5.4.4.7.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x574++0x03
|
|
line.long 0x00 "USB_MXPLD7,Endpoint 7 Maximal Payload Register"
|
|
hexmask.long.word 0x00 0.--8. 1. "MXPLD,Maximal Payload\nDefine the data length which is transmitted to host (IN token) or the actual data length which is received from the host (OUT token)"
|
|
group.long 0x578++0x03
|
|
line.long 0x00 "USB_CFG7,Endpoint 7 Configuration Register"
|
|
bitfld.long 0x00 9. "CSTALL,Clear STALL Response" "0: Disable the device to clear the STALL..,1: Clear the device to response STALL handshake.."
|
|
bitfld.long 0x00 7. "DSQ_SYNC,Data Sequence Synchronization\nNote: It is used to specify the DATA0 or DATA1 PID in the following IN token transaction" "0: DATA0 PID,1: DATA1 PID"
|
|
newline
|
|
bitfld.long 0x00 5.--6. "STATE,Endpoint STATE" "0: Endpoint is Disabled,1: Out endpoint,2: IN endpoint,3: Undefined"
|
|
bitfld.long 0x00 4. "ISOCH,Isochronous Endpoint\nThis bit is used to set the endpoint as Isochronous endpoint no handshake" "0: No Isochronous endpoint,1: Isochronous endpoint"
|
|
newline
|
|
bitfld.long 0x00 0.--3. "EP_NUM,Endpoint Number\nThese bits are used to define the endpoint number of the current endpoint" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x57C++0x03
|
|
line.long 0x00 "USB_CFGP7,Endpoint 7 Set Stall and Clear In/Out Ready Control Register"
|
|
bitfld.long 0x00 1. "SSTALL,Set STALL" "0: Disable the device to response STALL,1: Set the device to respond STALL automatically"
|
|
bitfld.long 0x00 0. "CLRRDY,Clear Ready\nWhen the USB_MXPLD register is set by user it means that the endpoint is ready to transmit or receive data" "0,1"
|
|
tree.end
|
|
tree "WDT"
|
|
base ad:0x40004000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "WTCR,Watchdog Timer Control Register"
|
|
bitfld.long 0x00 31. "DBGACK_WDT,ICE Debug Mode Acknowledge Disable Bit (Write Protect)\nWDT up counter will keep going no matter CPU is held by ICE or not" "0: ICE debug mode acknowledgement effects WDT..,1: ICE debug mode acknowledgement Disabled"
|
|
bitfld.long 0x00 8.--10. "WTIS,Watchdog Timer Time-Out Interval Selection (Write Protect)\nThese three bits select the time-out interval period for the WDT" "0: 24 *TWDT,1: 26 * TWDT,2: 28 * TWDT,3: 210 * TWDT,4: 212 * TWDT,5: 214 * TWDT,6: 216 * TWDT,7: 218 * TWDT"
|
|
newline
|
|
bitfld.long 0x00 7. "WTE,Watchdog Timer Enable Bit (Write Protect)\nNote: If CWDTEN (CONFIG0[31] Watchdog Enable) bit is set to 0 this bit is forced as 1 and user cannot change this bit to 0" "0: WDT Disabled,1: WDT Enabled"
|
|
bitfld.long 0x00 6. "WTIE,Watchdog Timer Time-Out Interrupt Enable Bit (Write Protect)\nIf this bit is enabled the WDT time-out interrupt signal is generated and inform to CPU" "0: WDT time-out interrupt Disabled,1: WDT time-out interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x00 5. "WTWKF,Watchdog Timer Time-Out Wake-Up Flag\nThis bit indicates the interrupt wake-up flag status of WDT.\nNote: This bit is cleared by writing 1 to it" "0: WDT does not cause chip wake-up,1: Chip wake-up from Idle or Power-down mode if.."
|
|
bitfld.long 0x00 4. "WTWKE,Watchdog Timer Time-Out Wake-Up Function Control (Write Protect)\nIf this bit is set to 1 while WTIF is generated to 1 and WTIE enabled the WDT time-out interrupt signal will generate a wake-up trigger event to chip.\nNote: Chip can be woken-up by.." "0: Wake-up trigger event Disabled if WDT..,1: Wake-up trigger event Enabled if WDT time-out.."
|
|
newline
|
|
bitfld.long 0x00 3. "WTIF,Watchdog Timer Time-Out Interrupt Flag\nThis bit will set to 1 while WDT up counter value reaches the selected WDT time-out interval.\nNote: This bit is cleared by writing 1 to it" "0: WDT time-out interrupt did not occur,1: WDT time-out interrupt occurred"
|
|
bitfld.long 0x00 2. "WTRF,Watchdog Timer Time-Out Reset Flag\nThis bit indicates the system has been reset by WDT time-out reset or not.\nNote: This bit is cleared by writing 1 to it" "0: WDT time-out reset did not occur,1: WDT time-out reset occurred"
|
|
newline
|
|
bitfld.long 0x00 1. "WTRE,Watchdog Timer Reset Enable Bit (Write Protect)\nSetting this bit will enable the WDT time-out reset function if the WDT up counter value has not been cleared after the specific WDT reset delay period expires" "0: WDT time-out reset function Disabled,1: WDT time-out reset function Enabled"
|
|
bitfld.long 0x00 0. "WTR,Reset Watchdog Timer Up Counter (Write Protect)\nNote: This bit will be automatically cleared by hardware" "0: No effect,1: Reset the internal 18-bit WDT up counter value"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "WTCRALT,Watchdog Timer Alternative Control Register"
|
|
bitfld.long 0x00 0.--1. "WTRDSEL,Watchdog Timer Reset Delay Selection (Write Protect)\nWhen WDT time-out happened user has a time named WDT Reset Delay Period to clear WDT counter to prevent WDT time-out reset happened" "0: Watchdog Timer Reset Delay Period is 1026 *..,1: Watchdog Timer Reset Delay Period is 130 *..,2: Watchdog Timer Reset Delay Period is 18 *..,3: Watchdog Timer Reset Delay Period is 3 *.."
|
|
tree.end
|
|
tree "WWDT"
|
|
base ad:0x40004100
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "WWDTRLD,Window Watchdog Timer Reload Counter Register"
|
|
hexmask.long 0x00 0.--31. 1. "WWDTRLD,WWDT Reload Counter Register\nWriting 0x00005AA5 to this register will reload the WWDT counter value to 0x3F"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "WWDTCR,Window Watchdog Timer Control Register"
|
|
bitfld.long 0x00 31. "DBGACK_WWDT,ICE Debug Mode Acknowledge Disable Bit\nWWDT down counter will keep going no matter CPU is held by ICE or not" "0: ICE debug mode acknowledgement effects WWDT..,1: ICE debug mode acknowledgement Disabled"
|
|
bitfld.long 0x00 16.--21. "WINCMP,WWDT Window Compare Register\nSet this register to adjust the valid reload window" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 8.--11. "PERIODSEL,WWDT Counter Prescale Period Selection" "0: Pre-scale is 1 Max time-out period is 1 * 64..,1: Pre-scale is 2 Max time-out period is 2 * 64..,2: Pre-scale is 4 Max time-out period is 4 * 64..,3: Pre-scale is 8 Max time-out period is 8 * 64..,4: Pre-scale is 16 Max time-out period is 16 *..,5: Pre-scale is 32 Max time-out period is 32 *..,6: Pre-scale is 64 Max time-out period is 64 *..,7: Pre-scale is 128 Max time-out period is 128 *..,8: Pre-scale is 192 Max time-out period is 192 *..,9: Pre-scale is 256 Max time-out period is 256 *..,10: Pre-scale is 384 Max time-out period is 384..,11: Pre-scale is 512 Max time-out period is 512..,12: Pre-scale is 768 Max time-out period is 768..,13: Pre-scale is 1024 Max time-out period is..,14: Pre-scale is 1536 Max time-out period is..,15: Pre-scale is 2048 Max time-out period is.."
|
|
bitfld.long 0x00 1. "WWDTIE,WWDT Interrupt Enable Bit\nIf this bit is enabled the WWDT counter compare match interrupt signal is generated and inform to CPU" "0: WWDT counter compare match interrupt Disabled,1: WWDT counter compare match interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. "WWDTEN,WWDT Enable Bit\nSet this bit to enable WWDT counter counting" "0: WWDT counter is stopped,1: WWDT counter is starting counting"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "WWDTSR,Window Watchdog Timer Status Register"
|
|
bitfld.long 0x00 1. "WWDTRF,WWDT Time-Out Reset Flag\nThis bit indicates the system has been reset by WWDT time-out reset or not.\nNote: This bit is cleared by writing 1 to it" "0: WWDT time-out reset did not occur,1: WWDT time-out reset occurred"
|
|
bitfld.long 0x00 0. "WWDTIF,WWDT Compare Match Interrupt Flag\nThis bit indicates the interrupt flag status of WWDT while WWDT counter value matches WINCMP value.\nNote: This bit is cleared by writing 1 to it" "0: No effect,1: WWDT counter value matches WINCMP value"
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "WWDTCVR,Window Watchdog Timer Counter Value Register"
|
|
bitfld.long 0x00 0.--5. "WWDTCVAL,WWDT Counter Value\nWWDTCVAL will be updated continuously to monitor 6-bit down counter value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
tree.end
|
|
autoindent.off
|
|
newline
|